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AH-FF45A-MC

July 1985

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Document:	CZLDIA0 DECSA DECSA LOADABLE IMAGE JUL 1985 bw
Order Number:	AH-FF45A-MC
Revision:	000
Pages:	62
Original Filename:	CZLDIA0__DECSA__DECSA_LOADABLE_IMAGE__AH-FF45A-MC__JUL_1985_gray.pdf

OCR Text

DECSA LOADABLE IMAGE

CZLDIAO

AH-FF45A-MC

10F1

JUL 1985

Euauan
MADE IN USA

———

MACRO M1200

25-APR-8S 14:05

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PAGE 1

ownm

' CZLDIAO LOADABLE IMAGE

IDENTIFICATION

.REM =

PRODUCT CODE:

AC-FF44A-MC

PRODUCT NAME:

CZLDIAO DECSA LOADABLE IMAGE

PRODUCT DATE:

1-APRIL-85

MAINTAINER:

DISTRIBUTED SYSTEMS

DIAGNOSTIC ENGINEERING

THE INFORMATION IN THIS DOCUMENT IS
SUBJECT
TO
CHANGE WITHOUT
NOTICE
AND
SHOULD
NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION.
DIGITAL EQUIPMENT CORPORATION ASSUMES NO

RESPONSIBILITY FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMEN
T.
NO RESPONSIBILITY IS ASSUMED
FOR
SOFTWARE ON EQUIPMENT THAT IS NOT
AFFILIATED COMPANIES.

THE
USE
SUPPLIED

OR
BY

RELIABILITY
OF
DIGITAL
OR ITS

DIGITAL
DEC

PDP

DECUS

UNIBUS

DECTAPE

MASSBUS

' CZLDIAO LOADABLE IMAGE

MACRO M1200

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PAGE 2

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87
58

DECSA
LOADABLE DIAGNOSTIC IMAGE

USERS GUIDE
APRIL

1985

AC-FF44A-MC

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Loadable Diagnostic Image

1.0 General Information for the Loadable Diagnostic
Image

SECTION TWO

SECTION THREE

Line Card Repair Diagnostics

3.0 General Info for CIDSCA and CIDSDA Line Card Tests
3.0
Program Abstract
System Requirements
Diagnostic Hierarchy Prerequisites
Assumptions - Restrictions
Operating Instructions
Hardwere Questions
Error Information

Configuration Information

>
Test
ries for CIDSCA Line Card Test #1
3.10 Test Summaries for CIDSDA Line Card Test #2
SECTION FOUR

System Requirements

Assumptions
Operating Instructions
Hardware Questions

Software Questions

Error Mes

Formats

4.10 Test Summaries for CIDSEA

SECTION FIVE

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41
42

CBT Repair Diagnostic

4.0 General Information for CIDSEA CBT Test
4.1
Program Abstract

Types of Error Messages
Device Error Messages
Test Summaries for CIDSAA PAM Test #1
Test Summaries for CIDSBA PAM Test #2

ags
Hardware Questions

Commands

g;itches

VOV VR VT VT VYV VY

2.0 General Information for CIDSAA and CIDSBA PAM Tests
2.1
Program Abstract
System Requirements
Releated Documents and Standards
Diagnostic Hierarchy Prerequisites
Assumptions - Restrictions
Operating Instructions

N
OCOVO®NNNNNNN

PAM Repair Diagnostics

:F‘PHHOGQOU“NN
W=
O

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SECTION ONE

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PAGE 3

WAL

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VONOVNH
W

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MACRO M1200

Veyounn

- ———

WWWWWHWWW

| CZLDIAO LOADABLE IMAGE

LLbbHD

S1
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S1
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System Exerciser

5.0 General Information for SYSEXE - System Exerciser
S.1
Operating Instructions
5.2
Line and Slot Identification Under SYSEXE

57
57
57

SECTION SIX

Updating the LDI to BLO6 - CSVLDI.SYS

SECTION SEVEN

Known Problems with LDI BLO6

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PAGE 4

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1.0

GENERAL INFORMATION for the Loadable Diagnostic Image

The LDI consists of many software components residi
ng in one
lerge image. The purpose of one image is to allow the
testing
of the DECSA Subsystem as configured without user interac
tion.
Execution of the LDI (once the image has been loaded
) requires
PLUMON to be loaded in a run state. The VMR utility allows
you to issue @ RUN command to an installed task before
the
image is saved. Both the RSX-11S and PLUMON (PLU>) will be
in
this state. PLUMON is the initial controlling task
for the
LDI. Upon initial execution PLUMON will determine the mode of

operation, AUTO or MANUAL. The mode selection in
made from a
velue in a CBT read/write register. The CBT ROM code
will
deposit a -1 value in this register for AUTO mode and clear
it
for MANUAL mode.

DECSA short self-test and LDI load

is selected by first

pressing the “start” button and then when the LEDs are
flashing at the quick rate pressing the "test” button.

Manual mode is selected by putting the test button
in the out
position while the LDI is being loaded, as indicated by the
L Sn in the LEDs.

Automatic mode is selected by the "test” button being
in the
"in" position when the LDI has completed loadin
g and has

started.

Uses of the DECSA TEST BUTTON.
test button

mode

comments

automatic mode

The 5 diags + sysexe should

execute followed by operating
system boot. Verify all diags
are complete.
out

manual

mode

The PLU>

should be displayed.

Run SYSEXE selecting # of

passes and loopback.

out

manual mode

The PLU> should be di.plaxod.
Run each of the S diags.
Run
the diags selecting external

loopback.
out

manual mode

The PLU> should be displayed.

Type in "AUTO”, The S dioro
and SYSEXE should run followed
by a boot request for the
operating system.

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PAGE S

Currently there are five diagnostics and a system exercis
er
thet can be executed either in AUTO mode or execu
ted separately
in MANUAL mode.
DIAGNOSTICS:

CIDSAR
CIDSBA
CIDSCA
CIDSDA
CIDSEA

REV C
REV C
REV C

REV
REV C

SYSTEM EXERCISER:
SYSEXE

PAM REPAIR TEST @1
PAM REPAIR TEST @2
LINE CARD REPAIR TEST #1
LINE CARD REPAIR TEST #2

CBT TEST

' CZLDIAO LOADABLE IMAGE

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MACRO M1200

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LOADABLE DIAGNOSTIC IMAGE
MEMORY ALLOCATION
Lt

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PAGE 6

RSX11-S

=
i

DECNET

UNA MICROCODE
PAM MICROCODE

=
%

L e,
=

i«

PLUMON

5«
kkkkkk

ko kR Rk

FRUMON

Rk kkkkkkkk
Rk k ke Rk

=«

DRS/RSX MODULE

kkkhkk Rk

kkkkk kR kR h kR

PAM DIAGNOSTICS

Rkkk
Rk kkkkkkk
kk
kkkd
kR
*

* LINE CARD DIAGNOSTICS
TM

Rkkk kb bk k kR kR hkkk
*

CBT DIAGNOSTIC

Shkkkkk bk

ok
#

kk kR ke k&

SYSEXE

T T

*
*

COMMON MSG BUFFER
COMMON DATA BUFFER

DEVICE I/0 PAGE DEF

LA LI

=
=

=
*

CZLDIAO LOADABLE IMAGE

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PAGE 7

2.0

GENERAL INFORMATION for CIDSAA and CIDSBA PAM Tests

2.1

PROGRAM ABSTRACT

The “PAM" repair level diagnostic (1) progrems is meant
to
orovide field service and manufacturing with a tool to
maintain the “digital ethernet communication server,”
“protocol assist modules (PAM). "The progrem will provide the

coverage necessary to detect

failures

the

"PAM" module

only. Fault detection is to the functional level,
isolation is to board (M3110 or M3111).

2.2

SYSTEM REQUIREMENTS

In order to run this diagnostic program,

hardware

is required:

the following minimum

A PDP-11 CPU_
"PROTOCOL PROCESSOR (PP)" (PDP 11/24)
MINIMUM OF 256K WORDS OF SYSTEM MEMORY
CONSOLE BOOT TERMINATOR (CBT)
RSX11-S “LDI" SOFTWARE OR XXDP+ SUPPORTED LOAD MEDIA
:PTI) ng{;} ONE "“PAM" MODULE SET CONSISTING OF AN M3110
1

2.3
-

set

while fault

RELATED DOCUMENTS AND STANDARDS

XXDP+ USER’'S MANUAL (CHQUS?.SEQ WHERE ? IS THE REV.

2.4

THE MANUAL -

“C” IS THE CURRENT REV.).

LEVEL OF

DIAGNOSTIC HIERARCHY PREREQUISITES

The goal of the "PAM” diagnostic program is to test the
M3110
and M3111 therefore, it is assumed that the "self test
di
tic” has run, and the "CBT" and “system memory"” are
fully functional. A failure in the aforementioned device
s
could fail this diagnostic and the user should be aware of
this possibility.
2.5

ASSUMPTIONS - RESTRICTIONS

It is assumed that the prerequisite diagnostics have been
executed (refer to section 2.4). The operator should
also

be femiliar with the operating
2.6

instructions

in section 2.6.

OPERATING INSTRUCTIONS

Section 2.7 - 2.10 contains a brief description of the Pluto
runtime services (PLU>). For detailed information, refer
to
the XXDP+ user’s manual (CHQUS).

295
296
297
298
299
300
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302
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313

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3¢5
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333
334
335
336
337
338

COMMANDS

There are eleven legal commands for the diagnostic
runtime
services (SUPERVISOR). This section lists the commands
and
gives a very brief description of them. The XXDP+
user's
manual has more details.
o

291
292
293
294

2.7

PAGE 8

COMMAND

EFFECT

START

START THE DIAGNOSTIC FROM AN INITIAL STATE

RESTART
CONTINUE
PROCEED

286

287
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MACRO Mi200

—

CZLDIAO LOADABLE IMAGE

START THE DIAGNOSTIC WITHCUT INITIALIZING
CONTINUE AT TEST THAT WAS INTERRUPTED
CONTINUE FROM AN ERROR HALT

*EXIT
ADD

RETURN TO PLUMON (SEE NOTE)
ACTIVATE A UNIT FOR TESTING (ALL UNITS ARE

DROP

DEACTIVATE A UNIT

CONSIDERED TO BE ACTIVE AT START TIME)

PRINT STATISTICAL INFORMATION (NOT IMPLEMENTED
BY THE LDI)

DISPLAY

TYPE A LIST OF ALL DEVICE INFORMATION

FLAGS
ZFLAGS

TYPE THE STATE OF ALL FLAGS
CLEAR ALL FLAGS

A command can be recognized by the first three characters.

you may,
*NOTE:

for example,

type

“STA"

instead of

After completion of a diagnostic

run,

"START".
type

"EXIT"

the DR> prompt to get back to the PLUMON prompt

to run the next diagnostic or SYSEXE.

NOTE

2.8

in section 2.8 on switches.

"PLU>"

Also refer to the

SWITCHES

There are several switches which are used to modify supervi
sor

operation. These switches are appended to the legal
commands.
All of the legal switches are tabulated below with
e brief

description of

number

each.

In the descriptions below,

is designated by

"DDDDD”.

a decimal

SWITCH

EFFECT

/TESTS:LIST

EXECUTE ONLY THOSE TESTS SPECIFIED IN
THE LIST.
LIST IS A STRING OF TEST
NUMBERS, FOR EXAMPLE - /TESTS:1:5:7-10.
THIS LIST WILL CAUSE TESTS 1,5,7,8,9,10 T0
BE RUN.
ALL OTHER TESTS WILL NOT BE RUN.

/PASS : DDDDD
/FLAGS:FLGS

/EOP :DDDDD

EXECUTE DDDDD PASSES (DDDDD = 1 TO 64000)
SET SPECIFIED FLAGS. (SEE SECTION 2.9)
REPORT END OF PASS MESSAGE AFTER EVERY

ZUNITS:LIST

TEST/ADD/DROP ONLY THOSE UNITS SPECIFIED

DDDDD PASSES ONLY.

(DDDDD = 1 TO 64000)

IN THE LIST.
LIST EXAMPLE - /UNITS:0:5:10-12
USE UNITS 0,5,10,11,12 (UNIT NUMBERS = 0-63)

CZLDIAO LOADABLE IMAGE
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25-APR-85 14:05

PAGE 9

EXAMPLE OF SWITCH USAGE:

START/TESTS:1-5/PASS:1000/E0P: 100
The effect of this command will be:

1) TESTS 1 THROUGH S WILL BE EXECUTED.
2) ALL UNITS WILL TESTED 1000 TIMES.
3) THE END OF PASS MESSAGES WILL BE PRINTED AFTER EACH 100

PASSES ONLY.
A switch cen be recognized by the first three charact
ers. you
may, for example, type "/TES:1-5" instead of "/TESTS:1-5".

NOTE:

When running under the LDI it is good practice to set
the PASS and HALT ON ERROR Flags, so you can get back
to the PLU> prompt by typing "EXIT".
STA/PASS:1/FLA:HOE

BELOW IS A TABLE THAT SPECIFIES WHICH SWITCHES CAN BE USED
BY EACH COMMAND.
TESTS

PASS

FLAGS

EOP

UNITS

364
365
366
367
368
369

370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
39
392
393
394
39S
396

2.9

FLAGS

Flor are used to set up certain operational parameters such
as
looping on error. All flags are cleared at startup and
remain cleared until explicitly set using the flags
switch.
Flags asre also cleared after a start command unless set
using
the flag switch. The ZFLAGS command may
also be used to clear
all flags. With the exception of the START and ZFLAGS

commands,

no commands affect the state of the flags they

remain set or cleared as specified by the last flag switch.

FLAG

HOE

EFFECT

HALT ON ERROR - CONTROL IS RETURNED TO

RUNTIME SERVICES COMMAND MODE

LOE

LOOP ON ERROR

IBE+*

INHIBIT ALL ERROR REPORTS EXCEPT

IER*

IXE=

INHIBIT ALL ERROR REPORTS

FIRST LEVEL

(FIRST LEVEL CONTAINS

ERROR TYPE, NUMBER, PC, TEST AND UNIT)
INHIBIT EXTENDED ERROR REPORTS (THOSE
CALLED BY PRINTX MACRO'S)

CZLDIAO LOADABLE IMAGE

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407

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MACRO M1200

2S5-APR-85 14:05

PAGE 10

PRI
PNT
BOE
UAM
ISR

L1
DIRECT MESSAGES TO LINE PRINTER
PRINT TEST NUMBER AS TEST EXECUTES
“BELL" ON ERROR
UNATTENDED MODE (NO MANUAL INTERVENTION)
INHIBIT STATISTICAL REPORTS (DOES NOT

RAPPLY TO DIAGNOSTICS WHICH DO NOT SUPPORT
STATISTICAL REPORTING)

IDR
ADR

INHIBIT PROGRAM DROPPING OF UNITS
EXECUTE AUTODROP CODE

LOT

LOOP ON TEST

EVL

EXECUTE EVALUATION (ON DIAGNOSTICS WHICH

HAVE EVALUATION SUPPORT)

411

+ERROR MESSAGES ARE DESCRIBED IN SECTIONS 2.11, 3.10 AND 4.7

413
414
415
416
417
418
419
420
421
422
423
424

See the XXDP+ user's manual for more details on flags. You may
specify more than one FLAG with the fl.g switch. For
example,
to ceuse the program to loop on error, inhibit error reports

412

425
426
427

428
429
430
431
432
433
434
435
436
437

and type &

“BELL" on error,

you may use the following string:

/FLAGS:LOE : IER:BOE

2.10

HARDWARE QUESTIONS

When e diagnostic is started, the runtime services will
prompt
the user for hardware informetion by typing “CHANGE HW
(L) 2"

you must enswer

"Y" after a start commend unless the hardware

information has been “preloaded” using the setup utilit
y (see
chapter 6 of the XXDP+ user's menual).
When you answer this
question with a "Y”, the runtime services will ask
for the

number of units (in decimal).

The "PAM" repeir diagnostic will test up to two units.
However, the di
tic sutomatically checks to see if the

requested units
for test are there and drops any not
responding. Also, the “CBT" is checked for a one or two "PAM"
system indicetor (CBT DCR BITO) end drops those units
that do
not, according to the sizing progrem, belong. The user
may

wish to inhibit the droping of units by setting the
flag
"inhibit progrem drop macro (IDU)".

CZLDIAO LOADABLE IMAGE

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25-APR-8S 14:05

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44]
442

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450
451

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459
460

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466

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470

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474

475

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477
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481
482

483

484
485
486

487
488

489
490

49)

PAGE 11

@ UNITS (D)

? 2<CR>

UNIT O
Unibus Address of “PAM" ? 171200<CR>
Herd Error Interrupt Vector ? 130 <CR>
Soft Error Interrupt Vector ? 134 <CR>

UNIT 1
Unibus Address of “PAM" ? 171000<CR>
Hard Error Interrupt Vector ? 140 <CR>

Soft Error Interrupt Vector ? 144 <CR>

2.11 TYPES OF ERROR MESSAGES

There sre three levels of error messages that may be issued
by
8 diegnostic: general, basic and extended. General error

messages are alwsys printed unless the

(section 2.9).

NAME
TYPE
NUMBER
ERROR MESSAGE

WHERE

“IER” flag

is set

The general error message is of the form:
ON UNIT NUMBER

TST NUMBER PC:XXXXXX

NAME = DIAGNOSTIC NAME
TYPE = ERROR TYPE (SYS FATAL, DEV FATAL, HARD OR SOFT)
NUMBER = ERROR NUMBER
UNIT NUMBER = O - N (N IS LAST UNIT IN PTABLE)
TST NUMBER = TEST AND SUBTEST WHERE ERROR OCCURR
ED

PC:XXXXXX = ADDRESS OF ERRCR MESSAGE CALL
Basic error messeges are

that contain some additional

information sbout the error.
hese are slways printed unless
the “IER” or "IBE” fl
ere set (section 2.9).
These

messages ere printed after the associsted general message
.

Extended error messeges contain supplementery error
informetion such ss register contents or good/
bad dete. These
ere slways printed unless the "IER”, “IBE" or "IXE" flags
are
set (section 2.9). These messages are printed sfter the
essociested genersl error messege and any essocisted basic

error

messages.

2.12

DEVICE ERROR MESSAGES

Error messages that occur in the initialize code., due to the
SIZING progrem finding feult with the expected snd rece;ved

PAM configuration,

sre as follows:

The SIZE progrem couldn‘t find PAM1
e.1. PAM]1

is not

in the system.

in the system end should be: Unit O dropped

b. The SIZE program couldn’'t find PAM2 in the system but the
CBT indicates it should be there ( BITO0=0 in DCR ).

o —
e

CZLDIAQ LOADABLE IMAGE
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25-APR-85 14:05

PAGE 12

b.1.

PAM2

is not

in the system and should be:

Unit 1 dropped

The SIZE program found PAM2 in the system but the CBT
indicates that it shouldn't be there ( BITO=1 in DCR ).
c.1.

500
501
502
503
S04
505

PAM2

is present and should not be.

The following is @ list of the basic format followed
printing Device Error messages in this diagnostic.

This message says that the Micro-Instruction LSI[]
to move data to Local Storege correctly.

506

S07

508
509
510
511
512
513
514
515
516
517
518
519
520
Se1
522
523

failed

Locel Storage Address Mux Test Failed
Local Storage Addressing Scheme

Address

LSI[) Failed

in Error == 171234

Expected Data == 125
Received Data ==

333

Contents of (SEQA) == 00043

This message says that the Soft error Interrupt occurr
ed before
the hsrd error interrupt.

S24
525
526
527

Force Herd/Soft error Interrupt test failed
Interrupts occurred out of sequence

528
529
530
531
532
533
534
535
536
537
S38
539

Lest Interrupt Expected == 130

last Interrupt Received == 134
ettt

This me

says that an ADD

nibble 290! slice.

instruction failed

in the high

ALU (2901) Function test failed
Expected results == 340

Oprnd 1 ==000
Oprnd 2 ==340
ADD

—

L ————

—

Function ==

c————

——1

CZLDIAO LOADABLE IMAGE

MACRO M1200

2S5-APR-85 14:05

PAGE 13

g:g

Results == 240

ggg

2.13

ggg

TEST 1

554

TEST SUMMARIES For CIDSAA PAM Test @1

This test will check

555
556
557
558
559

the ability to Read/Write all

locations

ggg

in the PAM address space. The interrupt service routine
(VECTOR 4) will set an error fl
to indicate that an
interrupt occurred. The diagnostic does a Read, checks the
error flag, Write and checks the error flag again. If an error
flag was set after the read or write, the diagnostic will

;gg

TEST 2

564

This test will check

that CSR1 R/M bits cen be set and cleared

“INTENB", "INIT", “RUN "

"SINGLE STEP”") and then checked to see

report the address and the function

in error.

565
566

S67

from the Unibus and can be cleared by "INIT" (Bit 03). All
bits are first written with ones (except "FORCE PE”, "LCPRS"
,

568
569

570

that the correct bits were set. CSR1 is then written with
Zeros and reread to check that the bits cleared. CSR1 is

571
572
g;S
4

STS
576

577

;;3
580

581

582

583
584
585
586

587

588

589
290
91
592
593
594
595

.saén written with ones ( except “FORCE PE", “LCPRS", "INTENB
",
”
* and "SINGLE STEP") but this time "INIT” is set (Bit 03)

also. All bits, except Line card Present which
should be cleared when reread.

is not checked,

TEST 3
This

test

will

check

that CSR2 R/W bits can be

from the Unibus and cen be cleared by

The register
checked to

CSR2

CSR1.

“INIT"

set

and cleared

(CSR1 Bit 03).

is written with different data patterns and

see

that the correct bits were set or cleared.
is again written with ones but this time "INIT"
is set

All bits should be cleared when read and rechecked
by

the diagnostic.

TEST 4
This test checks for SAl end SAO bits

writing several data pattern

to the

in the WCSA register by

reading/verifying the results of the write.
patterns are used:

125252
052525
031463
007417

and

The following

| CZLDIAO LOADABLE IMAGE

MACRO M1200

597

Ce2

PAGE 14

This test will check for SAO and SAl bits in WCS
by first
writing
all location with a given pattern and then
reading WCS
to verify the data. The diagnostic will dump the address
in

600
601
602
603
604
605
606
607
608
609
610
611
612
613
614

error,

expected data,

received data

following patterns are used:

and

XOR

data.

The

252
125
063
017
TEST 6
This test will perform a dynamic check of WCS by
using a

modified Moving Inversions algorithm. Sterting with WCS
clesred to all zeros, 24 passes are made (one for each data
bit) from the lowest to the highest address. Esch location

615

616

641
642
643
644
645
646
647
648
649
650

25-APR-85 14:05

TEST S

598
599

617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640

———

is first read to verify

that the background

n was stored
correctly, then a single bit is rewritten topatter
the location and
reread to verify

that

the new-pattern

was

stored correctly.

This process is repeated until WCS is filled with
all ones.
The next step ( step 2 ) is to repeat the sbove proces
s on

WCS, now with an all ones background pattern, but this time
each individual bit is cleared. This will leave WCS filled
with zeros and ready for the next step. Step 3 and 4 are the

same as 1 and 2 but the sequence starts at the Highest
WCS
address and works to the lowest. The key to the moving
inversions test is doing the Read-Write-Read sequen
ce as fast
as possible. Therefore, the check of date is done after
the
Read-Urite-Read sequence has completed.

TEST 7
This test will check for SAl and SAO bits in
Local Storage.
All Local Storage location are first written with
a given data
pattern. The diagnostic then reads all locati
ons and verifies
the date. If an error occurs, the LS Address, Deta Written,
Data Read and the XOR Data are output to the terminal.

TEST 8
This test will perform a dynamic check of Local Storag
e by
using a modified Moving Inversions algorithm. Sterting with

local storege clesred to all zeros, 8 passes are made (one for

each data bit) from the lowest to the highest address.

location

Each

is first read to verify that the background pattern

was stored correctly,

then a single bit

is rewritten to the

location and reread to verify that the new-pattern wes stored

correctly. This process is repeated until local storage is
filled with all ones. The next step ( step 2 ) is to repeat
the above process on local storage, now with an all ones

background pattern,

but this time each

individusl bit

CZLDIAO LOADABLE IMAGE
.

652

{
-

653
654
655
656
657
658
659
660
661
662
663
664
665
666

667

668
669
670
671
672
673
674
675
676
677
678
679
680

681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698

————

MACRO M1200

2S5-APR-85 14:05

PAGE 1S

cleared.

This will leave local stor.gc filled with zeros and

ready for the next step. Step 3 and 4 are
the same as 1 and 2
but the sequence starts at the Highest local storag
e address
and works to the lowest. The key to the moving inversi
ons test

is doing the Read-Write-Read sequence as fast as possibl
e.
Therefore, the check of data is done after the Read-U
rite-Read

sequence has completed.

TEST 9

This test will check that a Local Storage parity error
can
be forced by using "Force Parity Error” in CSR1. Force Parity
error (FPE) is set in CSR1 end then data is written in Local
Storage. The data written should have bad parity and should
cause a parity error (LSPE) when read. The diagnostic
will

read the Local Storage location and then check that
LSPE and
PE both set in CSR1. Several data patterns are
used when

loading local Storage to assure the

checkers and generators.

integrity of the Parity

*++xx% Interrupts are disabled

in this test

###ss%

TEST 10

This test will check that the 2911 Microsequenc
ers are able to
Sequence through all WCS Addresses. This is accomplished by
loading all locations in WCS with A HALT instruction
then
overwriting locations as follows:
Location

0000
0001
0001
1463

1464

2525
2526

7417
7420
7421

Instruction

R[0] <-- [1]
LS[7760] <-- R[O]
BR[1463)
LS[7761] <-- R[O]

;
;
;

LS[7762) <-- R[O])
BR[7417)

; Write LS+2
; Branch

BR([2525)

LS[7763]
LS[END]
HALT

<-- R[O]
<-- [-1]

Load A number
Write LS
Branch
Write LS-1

in Reg.

; Branch

;
;
;

Write LS+3
Set done
HALT

When this Microroutine Runs, Local Storage Locati
ons 7760 to
7763 will be Incremented and the Microsequencers
should halt
at Location 7421. The Macrocode will report, if an error

occurs,

the Expected and Received HALTED SEQUENCER ADDRESS
,

and the Expected and Received contents of LOCAL STORAGE.

| CZLDIAO LOADABLE IMAGE

MACRO M1200

25-APR-85 14:05

PAGE 16

700
701
702
703
704
705
706
707
708
709
710
711
712
713

714
715
716
4 44
718
719
720
721
722
723

724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753

TEST

This

is a test of the ability to read and write the MSR.

Co-nand-Segnent-Dcscriptor-Block-Entry

is first set

in CSR1

and then microcode is started. The micro-code
will write zeros
to all bits except 6 ( Clock ) in the MSR and then
store the
contents of MSR in Local Storage. All bits in the
MSR are then
written with ones except 7,6 and 1 ( hrd-er
r-int, clock and
sft-err-int ). After several micro-cycles the MSR is again
read and the contents stored. The
micro-cycles between write
and read of the MSR is to allow bit 6 (clock) to reset.
This
test is not a check of Clock timing, only a check of
read/write bits in the MSR.

TEST 12

This test will check to see that the Local Storage
Address
Mux can properly select the correct input for the differe
nt
Local Storage Addressing modes.
Local Storage 2525 and 5252 are the locations used as the
sources and destinations for for the MOV

instructions.

LIMITATIONS:
The Programmable Line Number register must be operational
for
this test to work. The Local Storage addressed by Specia
l
Character MOV instruction is not used in this test. This
instruction will be tested in a later test.
TEST 13

This test will check that there are no Ram A/B addres
s
lines SA1/SA0 or shorted together. All Ram locations, except
locations "5","12", end “14", are first written with Zero.
The locations
5,12, and 14
are then written with Ones,
followed by a read of all other locations to Local
Storage.
The action of writing the ones will overwrite any
zero'd
locations address with ones if the address lines are tied

together. Fore example: if address lines O and 1 are
shorted,
then when address S is written, location 7 would be

overwritten with Ones. The next step is to rewrite all
locations with zero except locations 5,12 and 14 and then read
and seve in Local Storage the unwritten locations ( 5.12,1
4 ).
The action of uriting the locations will again force an

overwrite into one of
the unwritten locations ( 5,12,14 ) if
the address lines ars shorted. The diagnostic will read Local

Storage an verify the

Ram location.

integrity of the data written to each

TEST 14
This test will check the 2901 Ram locetions for SAl and SAO

bits. Data patterns are written to Ram and the Ram is written
to local storage for verification bgzthe diagnostic. The
following patterns are used: 125, 252, 314 and 360.

——

{CZLOIAO LOADABLE IMAGE
755
756
757
758
759
760
761
762
763
764
765
766

767
768
769
770
173
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786

787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802

803

804
805
806
807
808

MACRO M1200

2S5-APR-85 14:05

PAGE 17

TEST 1S

This test will check the ability of the 2901 to rotate
the RAM
left. A ram location is loaded with data to be
shifted. The
data is then shifted and written to Local Storage
for
examination by the diagnostic. Local Storage should
look as
follows when the test completes:

LS Address
7760
7761
7762
7763
7764
7765
7766
7767

Data
002
004
010
020
040
100
200
001

TEST 16

This test will check that the 2901 RAM can be shifted
Right.
Date is loaded into a ram location to be shifted. The RAM
location is then shifted and the results written to Local
Storage for examination by the diagnostic. Local Storage
should look as follows when the test completes:
Local Storage Address

DATA

7760
7761
7762
7763
7764
7765
7766
7767

100
040
020
010
004
002
001
200

TEST 17

This test will check that the Q register and the RAM can
be

shifted left. Both the Q and a RAM location are loaded with
data to be shifted. The registers are shifted eight
times and
read efter each shift to Local Storage. Local Storage
should

look as follows when the test completes:

Local Storage address

Data

7740
7741
7742
7743
7744

002
004
010
020
040

7745

100

(

Q@ register data

)

gCZLDIAO LOADABLE IMAGE

MACRO TMM1200

2S5-APR-85 14:05

PAGE 18

810

gié

7746

813

aae
=

ggg

020

040

7756

200

7757

001

wai:

100

i
This
test 3 will check that the Q regi
gister and the RAM can be
shifted R-ght: Both the Q@ and a RAM location are loaded with

data

each

time

Storage

shifted.
writing

should

The

the

look

registers

shifted

follows

414
34

424
2

841

322

040

7742

020

7743

010

7744

004

7745

002

7746

001

7747

200

eight

times,

Storage.

test

(

100

Local

completes:

(

Q@ register da ta

RAM

data

)

020

7753

:‘7

the

100

7741

7752

345

shifted
Local

Date

7750
et

when

7740

gae

are

data

Local Storage address

832

7753

7754

RAM

TEST 18

ggz
4

010

7755

819

824
ggz

004

7752

ggg

002

7751

gig
816

001

7750

814

200

7747

010

7754

004

7755

002

7756

001

7757

200

:gg

TEST

852
:g:

This test
will check the Q register for SA1/SA0 bits and Check
st
that writing the OIRQH locations do not affect each
other. The

- o
o

f-rog

contents

cleoroq
saved

end

written

with

data

saved

in Local

the

written

local

storage

contents of the Q

and

patterns

Stor

with

377.

again

is then saved

and

Next,

The

written

each
Ram

RAM

time

location

with

the

location

ZERO.

in Local Storage.

is
The

then

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MACRO M1200

2S5-APR-85 14:05

PAGE 19

860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876

TEST 20
This test will check the ALU ( 2901 ) functions using
the
microcode CALC instructions ( the opcode roms are not
tested).
The microcode will fetch two Operands from Local Storage
. Each
function is executed on the Operands and the result
s written
to an assigned Local Storage location. The diagno
stic will
read and verify the results of each operation. Several
passes

through the diagnostic are made with different operand pairs
to fully check 2901 operestion. Local Storage locations are
assigned as follows:
Local Storage Address

877
878
879
880
881
882
883
884

885
886
887
888

889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912

Function assigned

7760
7761
7762
7763

"OR"
"AND*
"XOR*
“XNOR"

results
results
results
results

7765

"ADD"

results

7764

"NOTRS" results

7766

"SUBR"

7767
7770
7771

results

"SUBS"
results
Operand 1
Operand 2

TEST 21

This test will check the ALU ( 2901 ) functions using the
microcode Opcode “G” instructions in an attempt to check
the
170 of the opcode roms. Each function is executed on
an
Operand and the results written to an assigned Local Storage
location. This test is not an attempt to check the 2901 ALU,
only the opcode roms inputs end outputs. Local Storage
locations are assigned as follows:
Local Storage Address

Function assigned

7760

"ADD"

results (Opcode 40)

7761
7762
7763

“ADD”
"SUBS”
“SUBS”

results (Opcode 50)
results (Opcode 41)
results (Opcode S51)

7765

“SUBD"”

results (Opcode 52)

7767
7770
7771
7772
7773
7774
;775
776
7777

“OR"
“AND"
“AND"”
“XOR”
“XOR”
“XNOR”
“XNOR”

results
results
results
results
results
results
results

7764

“SUBD”

7766

“"OR"

results (Opcode 42)

results (Opcode 43)

DONE FLAG

(Opcode
(Opcode
(Opcode
(Opcode
(Opcode
(Opcode
(Opcode

53)
44)
54)
46)
S56)
47)
57)

!CZLDIAO LOADABLE IMAGE
gig
916

917

918

9219
920
921
922
923
924

MACRO M1200

25-APR-85 14:05

PAGE 20

TEST 22
This test

will

check

that

all

read modify write

used on Local Storage work correctly.

instructions

The test mainly checks

the two Opcode Decode Roms on the M3110 board.

Microcode

operates on instruction dependent operands stored in Local

Storage. The operands are chosen to assure that Both 2901
slices must work on the data. The Diagnostic will then check
Local Storage locations for correctness of data and report
any errors.

ggg

TEST 23

927
928
929
930
931
932
933
934
935
936

This test will check that the CALL and RTS functions in
Microcode work and the Micro-Stack is the correct depth. Four
consecutive CALLS are made to different routines in WCS. Each
routine does a CALL to the next routine until the last routine
is reached. The last ( routine 4 ) Microroutine writes a
location in Local Storage and then does an RTS to the
previously called routine which also increments a Local
Storage location and an RTS. The process is continued
(Increment Local Storage then do RTS) until the Micro-Stack is
empty and the Micro-PC has returned to the starting

937

938

923
9

Micro-Address+1.

Diagnostic

Storage should contain the following:

941

942

943

945

946

951

952

953

954

955

956

957
958
959
960
961
962
963

964
965

Data

7760

7761

001
001

7762

001

7763

947

245

Address

a
foapre
5
sl ottt
k
i s sk i :

944

950

Local Storagc will then be read by the
tc verify that all
Micro-Routines were hit. Local

001

7764

001

It should be noted that the Micro-Routines are NOT
in

contiguous

WCS

locations

may

appear

the

loaded
listing.

TEST 24

This test will check

the POP function

in Microcode.

consecutive CALLS are made to different routines

Four

in WCS.

Each

routine does a CALL to the next routine until the last routine
is reached. The last Microroutine ( routine 4 ) writes a
location in Local Storage and then does three consecutive POPs
of the Micro-Stack followed by an RTS. The RTS should bring
the Micro-PC back to the starting Micro-Address+1. Local
Storage will then be read by the Diagnostic to verify that the
first and last Microroutines increment Local Storage (NO OTHER

MICROROUTINE WAS RETURNED TO).
the following:

Local Storage should contain

' CZLDIAO LOADABLE IMAGE
|
|

—
]

——————

MACRO M1200

25-APR-85 14:05

PAGE 21

%67
968

969
970
971
972
973
974
975
976

977

978
979
980
981
982
983

984
985
986
987
988
989
990
991
1992
993

994
995
996
997
998
999
1000
1001
1002

1003
1004
1005
1006
1007
1008
1009
1010
1011

1012
1013
1014
1015

Address

Data

7760
7761
7762
7763
7764

001
000
000
000
001

It should be noted that the Micro-Routines are NOT loaded
in contiguous WCS locations as it may appear in the listing
.
TEST 25

This test checks that the Micro-sequencer is capable of Single
Stepping through a Microroutine and the Micro-sequencer

address register is operating correctly. The micro-routine is
single-stepped through each micro-instruction while examining

the contents of the Sequencer address register. If the
address
is correct in the register, then the Sequencer is
single-stepped again. This process continues until the
Micro-routine has halted. Local Storage is then examined
to
verify that all instructions functioneg correctly.

Local Storage should contain the following:
Address

Data

7760
7761
7762
7763
7764

001
001
001
001
001

It should be noted that the Micro-Routines are NOT loaded
in contiguous WCS locations as it may appear in the
listing.
TEST 26

This test will check that the SYNC bit in the Microw
ord will
halt the Microprocessor and will set PE and SYNC ACK
in CSR1.
A Microroutine is loaded that has SYNC set in two of
the
microwords. The diagnostic will start the microcode
and wait
for SYNC ACK end PE to set and the RUN bit to clear
in CSR1.

SYNC ACK and PE are then clesred and RUN reset to allow the

Microroutine to continue.

Again the aforementioned sequence

repeated and the expected results of the Microroutine

examined.
reported.

Any errors

in status or the Microroutine results

CZLDIAO LOADABLE IMAGE

1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029

1030
1031
1032
1033
1034

A——

MACRO M1200

25-APR-85 14:05

TEST 27

This test will check that a WCS parity error can
be forced and
the correct bits set in CSR1. A Microroutine is loaded in
WCs
with a bad parity microwords. The diagnostic will start
the
routine and check

on error

1052
1053
1054
1055
1056
1057
1058
1059
1060

1061
1062
1063
1064

1065
1066
1067

that WCSPE and PE both set

in CSR1.

Process

is also set so the Microroutine should complete the

Microroutine correctly.

***5%% Interrupts are disabled

in this test

ssssss

Local Storege locations are assigned as follows:

Local Storage Address
7760

7761
7762
7763

1035
1036
1037
1038

1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051

PAGE 22

7764
7765
7766
7767
7770
7771

Function assigned
"OR"

“AND "
“XOR"
“XNOR”

results

results
results
results
"NOTRS” results
“ADD"
results
“SUBR”
results
“SUBS”
results
Operand 1
Operand 2

TEST 28

This is a check of the Special Character Rec
ition Register
bits 0 to 2 and Mux. The microcode loads the
cial Character
register (SCR) by doing consecutive loads of the
Destination
Register (DR). Bits O to 2 of the SCR select the bit
in the

DR to be tested.

If the selected bit

is set then the Branch on

Special Condition will be taken. Both branch and no branch

conditions are tested ( bit under test set and cleared
all bits in the destination register.

) for

TEST 29

This

is @ check that Local Storege can be addressed by
Special

Cher. register. Local Storage cen be addressed by
combination of Special Character register, Line

r
register and Microword. The Line Number register contents
is
used as LS address bits 3 to 7, while the
ial Char. reg.’
contents is used as LS address bits O to 2 and 8 to 9.
LS
address bits 10 end 11 are derived from the Microword.
Locations 2525 and 5252 in Locel Storage are used in the
trensfer of dets. These locations correspond to setting and
clcorin’ each bit in the Local Storage address. The test is
successful if deta is correctly moved to and from these
locations.

CZLDIAO LOADABLE IMAGE
1069
1070
1071
1072
1073
1074
1075
1076
1077

1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094

1095
1096
1097
1098
1099
1100

1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111

MACRO M1200

25-APR-85 14:05

PAGE 23

TEST 30

This test will check that the Interlock function

is work ing

correctly. The microcode loads a location in Local Storage
with Bit O Set. The location is then complemented
-leaving the

locstion with bit O clear ( 376 )- and the

interlock branch

tested. Since Bit 0 was set before the compliment functio
n,
the interlock flop will set and the branch will be taken.
The

locel storage location

is again complimented (001) leaving

bit O set and the branch is agein tested. Since bit 0 was
clear before the compliment, the branch will not be taken.
TEST 31
This test will check that the microcode cen do a
CALL,

RIS and

POP on a condition code. The interlock condition is used only
because forcing interlock requires minimal hardware and
because it has already been tested. No attempt is made to test
all the possible condition codes only the Micro-sequencer
control bits are tested. Local Stor
locations are used to
save function indicator codes as follows:
Local Storage Address
7760
7761

7761
7761

7775
7776
777

function

Work Location
CALL_IL ()

RTS_IL
POP_IL

ERROR FLAG
ERROR FLAG
DONE
FLAG

code

1 or 376
1l or 2 (condition set

- clear)
3 or 4 (condition set - clear)
S or 6 (condition set - clear)

1
1
377

( Micro-Stack error
(Function error)

)

When the function is sterted (CALL_IL, POP_IL or RTS_IL)
, the
routine will write its code to Local Storage. If the
routine
worked then the test continues to the next function; but, if
the routine failed then the error flag is set and the
gicroroutinc halts leaving the failing function
code in Local
torage.
TEST 32

This test will check the Micro-Sequencer control logic
and the
Oring Mux during @ CALL on Low Nibble. The destination
register

is loaded with a date pattern and @ CALL_LN []

done to & 16 location terget ares. The CALL_LN will “OR" the
low nibble of the destination register with bits O to 3 of the
celled sddress. Each location in the terget sres will
increment the seme location in Local Storsge until the table
is exhausted and the RTS is performed. If the first locetion
in the table is hit (lowest address in the table), then the
number in Local Storege when when the RTS is performed will be
"20" (octal) if the location “12" (oct.) is hit then the Locel
Storege location will contein a “6“. Seversl data pstterns sre

CZLDIAO LOADABLE IMAGE

1123
1124
1125
1126
1127
1128
1129

1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154

1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177

MACRO M1200

25-APR-8S 14:05

PAGE 24

loaded to the destination register to check the

the Oring Mux during the call

integrity of

and are as follows:

005
012

014
165
172

174

TEST 33

This test will check the Micro-Sequencer control logic
and the
Oring Mux during @ CALL on High Nibble. The destination

register is loaded with a dats pattern and @ CALL_M
N () is
done to a 16 location target eres. The CALL_HN will "OR" the
high nibble of the destination register with bits
0 to 3 of
the called address. Eech location in the target ares will
increment the same location in Local Storage until
the table
is exhsusted and the RTS is performed. If the first
location
in the teble is hit (lowest address in the table), then
the
number in Local Storage when when the RTS is performed
will be

“20" (decimal) if the locetion “12” (oct) is hit then the
Locel Storage location will contein & “6“. Several dets

patterns ere loaded to the destination reristcr

integrity of the Oring Mux during the call

to check

the

and sre as follows:

120
240
300
137
257
317
TEST

This test will check that the Micro-sequencer is
sble to
brench correctly on High Nibble and Low Nibble. The
test only
checks thet the brenches cen be taken properly withou
t

affecting the micro-stack.

Mux

It should be sssumed that the Oring

is working properly by virtue of previous testing.

TEST 35
This test will check Bit-Test Mux and the Micro-sequence
r
functionality
by u.inr micro-code Bit-Test instructions. The
micro-code flosts @ “1” on & background pettern of zeros end

e "0" on @ background pattern of ones throur\ the destination
register. The Micro-code sequence is as follows:

Do the following for bits O to 7
1. Set the bit to test.
2. Test the bit.
3. Compliment the bit pattern.
4.

Test

the bit.

1179
1180
1181
1182
1183
1184
1185
1186
1187

1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214

1215

1216
1217
1218
1219

1220

1221

1222
1223
1224
1225
1226
1227
1228
1229
1230
1231

1232

——

MACRO M1200

2S5-APR-85 14:05

PAGE 25

TEST 36

This test will check that the “N” bit will set/cl
ear and not
effect, or be affected by the Z.C or V condition codes. The

Micro-code will write @ register with a negati
ve number and
then store the register contents in Local Storage.
The

condition codes are then checked by taking the correc
t brench.

If the brench fails, en errcr flag,

CC set/clear flag., dete

used
and a function code are written to Local Storege.
function codes are as follows:

BMI
BPL
BEQ
BNE
BCS
BCC
BVS

==
==
==
==
==
==
==

The

NOVNAUWN=O

CZLDIAO LOADABLE IMAGE

[

BVC ==

TEST 37

This test will check that the “C” bit will set/clear and not
effect, or be affected by the Z,N or V condition codes. The

Micro-code will write two registers with different
operands
for the ALU to to ADD. The condition codes are
then checked by
" taking the correct branch. If the branch fails,
an error fleg.

CC set/cleer flag, date used, results of the add and o

function code are written to Locel Storage.
ere as follows:
BMI

BPL

BEQ ==

BNE

BCS
BCC
BVS
BVC

==
==
==
==

The function codes

NONs U= O

TEST 38

This test will check that the

“V” bit will set/clesr and not

effect, or be effected by the Z,N or C condition codes.

The

Micro-code will write two registers with different operand
s
for the ALU to to ADD. The condition codes are then checked
by
teking the correct branch. If the brench fails, sn error
flag,

CC set/zlear flag, datea used, results of the add end o

function code are written to Locel Storage.
ere as follows:

BMI == 0
8PL == }
BEQ == 2

The function codes

1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269

1270
1271
1272
1273
1274
1275
1276
1277
1278
1279

1280
1281
1282
1283
1284
1285
1286
1287

MACRO M1200

2S5-APR-85 14:05
BNE
BCS
BCC
BVS
BVC

PAGE 26

==
==
==
==
==

~onaw

CZLDIAO LOADABLE IMAGE

TEST 39

This test will check that the “Z" bit will set/cl
eer and not
effect, or be affected by the N,C or V condition codes. The

Micro-code will write a register with date patterns
to set or

clear the Z Bit. The condition codes are then checked by
taking the correct branch. If the branch fails, an error
flag,
CC set/clear flag, data used
and a function code are written

to Local Storage.
BMI

BPL

BEQ ==
BNE

BCS
BCC
BVS
BVC

==
==
==
==

The function codes are as follows:

NOVNBUWNO

TEST 40

This test will check the hard error
through

interrupt control function

interrupt vector 130 or 140 (PAM1 or PAM2).

interrupt is forced by setting "Hard Error Interr
upt” in the
Micro-code Status register. The interrupt servic
e routine

( HARDSERV ) will save the status in CSR1, clear the error
condition and restart the micro-code.
The interrupt service routines for hard and soft error
interrupts use @ common flag word in memory and its
format
as follows:

Bits
O to 7 = Interrupt Vector (Written by Service routine)
Bit
8 = Hard Error Interrupt (Vector 1307140 Ser. rout. sets)
Bit
9 = Soft Error Interrupt (Vector 134/140 Ser. rout. sets)
Bit 10 = Double interrupt through vector 130/140
Bit 11 = Double interrupt through vector 134/144
If the reported CSR1 status

is O then the

routine did not read status at time of

interrupt service

interrupt.

TEST 41
This test will check the Soft error interrupt control
function through interrupt vector 134 or 144 (PAM1 OR PAM2).
An interrupt is forced by setting “Status Segment Descriptor

Block Interrupt”
The

in the Micro-code Status register.

interrupt service routine(

SOFTSERV

) will save the status

CZLDIAO LOADABLE IMAGE
1289
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1300
1301

1302
1303
1304
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i312
1313
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1316

1317
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1333
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1341

MACRO M1200

2S5-APR-85 14:05

PAGE 27

in CSR1 at
The status

interrupt time and load the interrupt flag word.
in CSR1 should reveal that the Run bit remained set.

The interrupt service routines for hard and soft error
interrupts use a common flag word in memory and
its format
as follows:

Bits 0
Bit
8
Bit
9
Bit 10
Bit 11

to 7 = Interrupt Vector (Written by Service routine)
= Hard Error Interrupt (Vector 130/140 Serv. rou. sets)
= Soft Error Interrupt (Vector 134/144 Serv. rou.
sets)
= Double interrupt through vector 130/140
= Double interrupt through vector 134/144

If the reported CSR1 status

is 0 then the

routine did not read status at time of

interrupt service

interrupt._

TEST 42

This test will attempt to force both Hard error and Soft error
interrupts through interrupt vectors 130/140 and
1347144,

respectively.

The

interrupts are forced by setting

"Hard Error

Interrupt” and "Status Segment Descriptor Block Interrupt”
in
the Microcode Status register. Both bits, in the
microcode
Status register, are set at the seme time this should
cause
the Hard
Error Interrupt to occur first ( Vector 130/140 ) and
then the Soft Error Interrupt ( Vector 134/144 ). The
hard

error

interrupt will halt the PAM ; therefore,
the RUN bit is
reset by the interrupt service routine. The soft error
interrupt has no effect on the PAM microprocess
or and will not

halt the PAM.
The

interrupt service routines use a common flag word

memory to

indicate which

The Flag Word

interrupt occurred first.

is written as follows:

Bits
0 to 7 = Interrupt Vector (Written by Service routin
e)
Bit
8 = Herd Error Interrupt (Vector 130/140 Ser.
rout. sets)

Bit
9 = Soft Error Interrupt (Vector 134/144 Ser. rout.
Bit 10 = Double interrupt through vector 130 or 140
Bit 11 = Double interrupt through vector 134 or 140
2.14

sets)

TEST SUMMARIES for CIDSBA PAM Test #2

TEST 1
This test will check the path to and from the Desh Bus
using
Scanner "Msintenance Mode“” in "Address Wrap” and the 11/24
Dash Bus Window.
The test sequence is as follows:
1.
2.
3.

Set CSR2 Bit 13 ( Data Address Wrap )
Set CSR1 Bit S
( Maintenance Mode )
Read Dash Bus address window

| CZLDIAO LOADABLE IMAGE

[

1343

1344

1345
1346
1347
1348
1349
1350
1351
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1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370

1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395

MACRO M1200

25-APR-85 14:05

PAGE 28

The data read from the Dash Bus wirdow should consis
t of the

contents of CSR2 Bits 0-3 in the high nibble
(Bits 4-7) the
fiurrens Dgsh Bus window number should be in
the low nibble

Bits

0-3).

TEST 2

This test will check the path to and from the Dash Bus
using
Scanner “Maintenance Mode” in "Data Wrep” and the 11/24
Dash
Bus Window.
The test sequence is as follows:

1.
2.
3.

Clear CSR2 Bit 13 ( Data Address Wrap )
Set CSR1 Bit S
( Maintenance Mode )
Write the Dash Bus address window

Read the Dash Bus address window

The data read from the Dash Bus window should be
the same as
the date written. Any window location read should
fetch the
same data, indifferent to the window location written.

TESY 3

This test will attempt to force a DASH BUS parity error

through the 11/24 DASH BUS Window.

The diagnostic will set

"Maintenance Mode” and "Force Parity Error” in CSR1 (
Bits S
and 4 ) and then read an address in the Dash Bus Window.
Status is then checked to see that "Dash PE” sets in CSR1
and
“11/24 Dash PE" sets in CSR2. The process is again repeat
ed

and the error bits are written with a 1 to check

clear.

The final check

that both

is to force the error and then set INIT

to again check that the error bits clear.

TEST 4

This test will check the sbility of the PAM to read
data from

the Dash Bus.

This is accomplished by setting the "Address

Wrap” bit in CSR2, "Maintenance Mode” in CSR1 and
having the
PAM microcode do reads to the Dash Bus. The microc
ode loads
the desired line number, using the programmasbl
e line register,
and reads the desired Dash Bus Register (DBR).
The data read
should be & combination of the Line Number and the Registe
r

number
:

BITS 7 70O 4 == Line Number

BITS 4 TO O == Register Number

Local Storage will look as follows:
7760 ==

(

last line number used

)

If the branch condition fails for a specific line number,

line number in error will be saved in 7760 and one of the
error flags will set as described below.

the

! CZLDIAO LOADABLE IMAGE

—

MACRO M1200

25-APR-85 14:05

PAGE 29

1397
1398
1399
1400
1401
1402
1403

7761

1408
1409
1410
1411
1412

1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435

1436
1437
1438
1439

1440
1441
1442

{
(
(

Branch did not clear

NOTE!!

)

)
)
)

if bit 0 == 1,

This is the first test that will check the branch
conditions “BPE” ( Branch on Dash Parity error ) and
"BDE” ( Branch on Read Not Done or Dash Parity Error)
.

TEST S

This test will check the ability of the PAM to do WRITES
to
the Dash Bus. This is accomplished by clearing Data/Adrs
wrap
in CSR2, Setting "Maintenance Mode” in CSR1 and having
the PAM
microcode write data to the DBR's. The microcode
loads the the
line number and writes a Dash Bus Register with a data
pattern. A different DBR is read to verify that the
data

pattern

is the same as was written.

The above process (

write

DBR - read
different DBR ) is done with several dates patterns
to verify the integrity of the data path. An attemp
t is is
also made to test the STALL feature by doing successive
writes,
with different dats patterns, to the dash bus each
time &
write/read cycle is done.

Local Storage will look as follows:
7760 == 360

( Last Data Pattern Written

)

If the branch condition fails for a specific data patter
n
used, the pattern in error will be saved in 7760 and one
of
the error flags will set as described below.

7761
7762
7763
7764

==
==
==
==

125(Data
252(Data
314(Data
360(Data

Pattern
Pattern
Pattern
Pattern

Read)**If
Read)**If
Read)**If
Read)#*If

NO
NO
NO
NO

Parity
Parity
Parity
Parity

Error
Error
Error
Error

on
on
on
on

read
read
read
read

&
**
*»
#*#

7775 == Dash Bus Par Error (BPE) Branch was taken
if bit 0=1.
7776 == Read Not Done OR Dash Bus Parity Error (BDE) Branch

did not clear

1443

1444
1445
1446
1447
1448
1449

( Register and line number wrapped

7775 == Dash Bus Parity Error (BPE) Branch
was taken
if bit 0 == 1,
7776 == Read Not Done OR Dash Bus Parity
Error (BDE)

1404

1405
1406
1407

== 125

7762 == 252
7763 == 314
7764 == 360

if bit 0 == 1.

TEST 6
This test will attempt to force an Underrun condition and
Transmit Error in Scanner “Maintenance Mode”. The PAM
microcode writes data to the Dash Bus that has “Bit 2" set

(Bit 2 corresponds to XMIT ERR in the line status registers).

—

;CZLDIAO LOADABLE IMAGE

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1471
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1477
1478
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1489
1490
1491
1492
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1500
1501
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MACRO M1200

25-APR-85 14:05

PAGE 30

Microcode informs the diagnostic
then waits for a response.

thet the data was written and

The Macrocode will set “Sync”,"Transmit Flo?“ end
"Maintenance
Mode”, then tell the Microcode to proceed.
The PAM microcode
will, when “Scen Entry” sets in the MSR, read and ,in Local
Storage, store the contents of the "Data FIFO ", "Status
FIFO"
and the "MSR". The Microcode then informs the Macroc
ode that
the function is done.
If the microcode is unable to flush the FIFO's correc
tly,
which indicates that Scanner Entry remains set,
the microcode
will set @ Timeout flag in LS location 7776.
TEST 7

This test will attempt to force a "Receive Error”
condition
“Synchronous mode”, using Maintenance mode.

The PAM microcode writes a data pattern, thet the
Macrocode
has passed to Local Storage, to the Dash Bus and waits
for a
response from the diagnostic.

The Macrocode will then set

"Sync” and "Receive Flag”

set "Maintenance Mode”
continue.

in CSR1

The PAM microcode will,

when

read and store

in CSR2,

and tell the microcode to

"Scan Entry” sets

in the MSR,

(in Local Storage) the contents of the

“Data

FIFO ", "Status FIFO" and the "MSR”. The Microcode then
informs the Macrocode that the function was done.

The contents of the "Status FIFO" and "Data FIFO"
is dependent
on the date pattern written to the “Dash Bus” and whethe
r the
"Sync” bit is set in “CSR2". In “Synchronous” mode
bits 0 to 3
will cause a "Receive Error” to set in the "Statu
s FIFO". Two
entries will be entered in each FIFO for the error
condition
as follows:

STATUS FIFO
1. Error set
2. No error set

DATA FIFO
Line Reg. 1
( DATA WRITTEN )
Char. in Err.( DATA WRITTEN )

Bits 4 to 7 should not cause an error condition and the FIFOS'

will look as follows:

STATUS FIFO
1. No Error set

NO Error set

DATA FIFO
Received Char.
Received Char.

If the microcode is unable to flush the FIFO's correctly,
which indicates that Scanner Entry remains set, the microcode
Wwill set a Timeout flag in LS location 7776.

CR—

iCZLDIAO LOADABLE IMAGE MACRO M1200 2S-APR-85 14:05 PAGE 31
1505
1506
1507
1508
1509
1510
1511
1512

1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558

TEST 8

This test will attempt to force a "Receive Error”
condition
"Asynchronous mode”, using Maintenance mode.

The PAM microcode writes a data pattern, that the
Macrocode
hes passed to Local Storage, to the Dash Bus and
waits for a
response

from the diagnostic.

The Macrocode will then set “Enable Scan Cntr” and
"Receive
Flag” in CSR2, then set “Maintenance Mode” in CSR1
and again
wait for response from the PAM.
The PAM microcode will,
read and store

when

"Scan Entry” sets

in the MSR,

(in Local Storage) the contents of the

"Data

FIFO “, "Status
FIFO" and the "MSR". The Microcode then
informs the Macrocode that the function was done.

The contents of the "Status FIFO" and “Data FIFO" is
dependent
on the data pattern written to the "Dash Bus” and
whether the
"Sync” bit is set in "CSR2".

In "Asynchronous” mode bits 3 to 5 will cause a "Receive
Error”
to set in the “Status FIFO”. Two entries will be entered
in
each FIFO for the error condition as follows:

STATUS FIFO
1. Error set
2. No error set

DATA FIFO
Line Reg. 1
(
Char. in Err.(

DATA WRITTEN
DATA WRITTEN

)
)

All bits , other than bits 3 to S5, should not cause an error
condition and the FIFOS' will look as follows:
STATUS FIFO
1. No Error set
2. No Error set

DATA FIFO
Received Char.
Received Char.

If the microcode is unable to flush the FIFO's correc
tly,
which indicates that Scanner Entry remains set,
the microcode
Wwill set a Timeout flag in LS location 7776.
TEST 9

This test will attempt to force a “Receive Error” condition
"Synchronous mode”, using Address Wrap.

The Microcode writes a location in Local Storage
Macrocode that it is ready to proceed.

informing the

The Macrocode will then set “Sync”, "Receive Flag” and "Address
Wrap” in CSR2 and then set "Maintenance mode” in CSR1. The

Diagnostic then

informs the PAM that the function was done.

The PAM Microcode will,

when

“Scan Entry” sets

in the MSR,

:CZLDIAO LOADABLE IMAGE

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1601
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MACRO M1200

25-APR-85 14:05

PAGE 32

read and store

(in Local Storage)

the contents of the

"Data

FIFO “, "Status FIFO" and the "MSR”. The Microcode
then
informs the Diagnostic that the function is done.
This test
loops through all the line numbers.

The contents of the “Status FIFO" and "Data FIFO" ;s
dependent
on the “Dash Bus” address the “Scanner” is referencing
and
whether the “Sync” bit is set in "CSR2".

The Scanner reads Line Register "1",
when it sees a Receive
Flag in Line Register "9" the address currently on the Dash
Bus ( Line Register 1 ) will appear as data of Line Registe
r
“1". Therefor, an error will be recorded in the status FIFQ

because

"Bit 00" will be set.

In "Synchronous” mode bits O to 3 will ceuse "Error” to set
in
the "Status FIFO" . Two entries will be entered in each FIFO
for the error condition as follows:

STATUS FIFO
1. Error set
2. No error set

DATA FIFO
Line Reg. 1 (ADDRESS WRITTEN)
Line Reg. O (ADDRESS WRITTEN)

If the microcode is unable to flush the FIFO's
correctly,
which indicates that Scanner Entry remains set, the microc
ode
will set a Timeout flag in LS location 7776.
TEST 10

This test will attempt to force a "Receive Error” condition
"Asynchronous mode”, using Address Wrap.

The Microcode writes a location

Macrocode that

in Local Storage

is ready to proceed.

informing the

The Macrocode will then set "Receive Flag” and "Address
Wrap”
in CSR2 and then sets "Maintenance mode” in CSR1. The
Diagnostic then informs the PAM that the function was
done.
The PAM Microcode will,

when

"Scan Entry” sets

in the MSR,

read and store (in Local Storage) the contents of the
"Data
FIFO ", “Status FIFO" and the “MSR”. The Microcode
then

informs the Macrocode that the function
will loop through all the line numbers.

is done.

This test

The contents of the "Status FIFO" and "Data FIFO” is depende
nt
on the "Dash Bus" address the “Scenner” is referencing and
whether the “Sync” bit is set in "CSR2".

The Scanner reads Line Register “1”,
when it sees a Receive
Flag in Line Register “9”, and the address currently on the
Dash Bus ( Line Register 1 ) will appear as the data of Line
Register “1". An error will “NOT” be recorded in the status
FIFO for the following Line Numbers: 0,4,8 and 12 all Line

S—

———

éCZLDIAO LUADABLE IMAGE MACRO M1200 25-APR-85 14:05 PAGE 33
1615

16%?
16

1618

1619

iggg

Numbers,

except those listed,

in the Status FIFO.

"Asynchronous”

in the

mode bits

“Status FIFO"

will cause an Error bit to set

to 5

will

cause

“Error"”

Two entries will be entered

FIFO for the error condition as follows:

1622
1623

STATUS FIFO
1. Error set

iggg

DATA FIFO
Line Reg. 1

No error set

Char.

(

in Err.(

to set

in each

ADDRESS WRITTEN )

1€26
1627
iggg

If the microcode is unable to flush the FIFO's correctly, which
indicates that Scanner Entry remains set, the microcode will
set a Timeout flag in LS location 7776.

1630
1631
1632
1633

TEST 11

1634
1635

1636
1637
1638
1639

1640

1641

1642
1643
1644

1645
1646

1647

1648

1649

1650

1651

1652
1653
1654

1655
1656

1657

1658

1659

1:60
1661

This test will force the scanner to record a Modem Change for
all line numbers. The test will start by forcing a Modem

Change for all lines, with a known data pattern
( zeros' 3.
The Status and FIFO entries are ignored for the
first data

pattern used, since the initial values in the modem change ram
is unknown. Subsequent patterns should xicld the following:
MEC should set in the STATUS FIFO the DATA FIFO should have
the EXCLUSIVE

written.

The

increment i

verify the
locations).

“OR" of the previous pattern and the pattern

pattern

from

set

that

a Timeout

TEST

This

test

to 20

unable

(

after

(OCT.).

the pattern of ZEROS ) is
This pattern sequence will

DEPTH of the Modem Change Ram (16 Decimal

If the microcode
indicates

used

Scanner

flag

will

Entry

flush
remains

the FIFO's correctly,
set,

the

record

in LS location 7776.

force

the

scanner

all

microcode

Modem

which

will

Change

for

line numbers. The test will start by forci
a Modem
Change for all lines with & known data patter
n ( zeros'
). The
Status and FIFO entries are ignored for the
first data pattern

used, since the initial values in the modem ch
rem is
unknown. Subsequent patterns should ¥ield the following:
MEC

should set in the STATUS FIFO the DATA FIFO should have the

EXCLUSIVE
written.

“OR” of the previous pattern and the pattern

Four

data patterns

integrity of the ram,

1662
1663
1664

iggz

;

1667

If the microcode

1. 252
2. 125
3. 063

017

are used to verify

as follows:

the dates

Alternate zeros and ones
Above shifted right
Adjacent bits set and cleared

Adjecent nibbles set and cleared

is unable to flush the FIF0's correctly,

| CZLDIAO LOADABLE IMAGE

1669
1670
1671
1672
1673

1674
1675
1676
1677

1678
1679
1680
1681
1682
1683
1684

1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721

p—

MACRO M1200

25-APR-85 14:05

PAGE 34

which indicates that Scanner Entry remains set,
will set a Timeout flag in LS location 7776.

the microcode

TEST 13

This test will force a Dash Bus parity error for
PAM WUrites to
the Dash Bus. The Microroutine first flushes the FIFO's
and
waits for the diagnostic to setup the function. The
diagnostic
will set Force PE, in CSR1, and informs the microcode
that the
function was done. When the microcode writes the Dash Bus
window, Line in error and Dash Bus Parity error bit,
.long
with the bad date, will load in the FIFOS. The conten
ts of
the
Date and Status FIFOS is stored.in local Storage.
The Microcode will then test two Condition codes while
the
Force PE is set. A read will indicate the parity error
by
setting two microbranch condition codes: "Read Not Done or
Parity Error“and "Read Dash Bus Parity Error”. The state
of
the condition codes is saved in Local Storage for the Read
end
Write operations.

The transfer of data to end from Local Storage will cause
a
"Local Storage Parity error” when Force Parity error is set.
Therefore, the existence of this error bit is expecte
d. It
should also be noted that the contents of the Status and
Data
FIFO's is invalid unless Scan Entry is set in the MSR
for each

entry read.

TEST 14

This test will check that the Scenner can be disabled
b

setting Disable Scan

in CSR2 (Bit 6) and starting a XMIT/REC

function in "Maintenance Mode”. The diagnostic first does
a
velid Scenner function to assure that known data will appear
in the FIFO's. Scenner Disable is then set, the FIFO's
flushed
and a different type of Scenner function started. There should

be no entries into any of the FIFO's form subsequent transfe
rs
and this will be verified by the diagnostic.

If the microcode

is unable to flush the FIFO's correctly,

which indicates that Scenner Entry remains set,
will set a Timeout flag in LS location 7776.

the microcode

TEST 15

This test will check the Block Mover memory address register
bits 0 to 21. A pattern is passed to Local Storage for the
microcode to read and pass to the Block Mover address
register. The microcode then starts a one word DATA-IN to
Local Storage with the Block Mover. When the block move stops,
the microcode will pass the contents of Last Memory Address
register to Local Storage for verification by the program.

foglouing patterns are used as addresses:

The

CZLDIAO LOADABLE IMAGE

1723
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1721
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748

1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
177
1772
1773
1774
1775

MACRO M1200

25-APR-85 14:05

PAGE 35
1.
2.
3.

05252525
12525252
14631463

TEST 16

The block mover is given an address of ALL ONES end & block
move is started. The "PAM“ should detect an "NXM” in the

Micro-Status register and the block mover should
stop. The
microcode should be “Forced to Zero” when the “NXM"
condition
occurs and a check is made to see that the force condition
occurred once only.

TEST 17

This is a test of the Block Movers ability to do a DATA-IN
form system memory. A data pattern is first writte
n into
system memory for the Block Mover to transfer. The Microco
de
fetches the memory address to write the data, number
of words
to transfer and Local Stor
location to write, from the
Pseudo CSR locations. The Block mover should be able
tc read
the deta from system memory ( BUFFER ) and write it to
contiguous Local
Storage locations. The pattern used is

incrementing from 1 to 40 (octal).

The microcode is “Forced to
"NXM" ( Non Existent Memory
A check is made to see that
micro-location zero is made

Zero” for the following conditions:
), “MPE” ( Memory Parity Errors).
onlxRonc traverse through
(START) by the Microroutine.

TEST 18
This is a test of the Block Movers ability to do
a DATA-OUT to
system memory. A date pattern is first written into
Local

Storage for the Block Mover to transfer. The Microcode
fetches
the memory address to write the data, number of words
to
transfer and Local Storasge location to read from
the Pseudo

CSR locations.

The Block mover should be able to read the datas

from Local Storage and write it to a system memory
location
celled BUFFER. The pattern used is incrementing from
1 to 40

(octal).

The totel transfer should be 16 Words. The microcode

is "Forced to Zero” for the following conditions: “NXM"
( Non
Existent Memory ), "MPE" ( Memory Parity Errors). A check is
made to see that only one traverse through micro-location
zero

is made (START) by the Microroutine.

TEST 19

This is a test of the Block Mover Local Storage address
register. A date pattern is first written into Local Storage
for the Block Mover to READ. The Microcode fetches the memory
address to write the data and number of words to transfer from

the Pseudo CSR locations.

The Block mover should be able to

CZLDIAO LOADABLE IMAGE
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792

1793
1794
1795
1796
1797
1798
1799
1800

1801
1802
1803

1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820

1821
1822

1823
1824
1825
1826
1827

1828
1829

———

MACRO M1200

25-APR-85 14:05

PAGE 36

read the data from Local Storage and write
memory location called BUFFER.

to a system

The following Local Storage locations are used:

LS Address
5252
5253
2525
2526
1463
1464
3777
4000

LS Data
NONS
N -

—

The microcode is “Forced to Zero” for the following
conditions:
"NXM“ ( Non Existent Memory ), “MPE" (Memory Parity Errors). A
check is made to see that only one traverse through
micro-location zero is made (START) by the Microroutine
.
TEST 20

This test will check the Block Movers ability to do
a DATA_IN
followed by @ DATA_OUT. The PAM microcode first reads
Local

Stor

to fetch H.-or¥ address,

Word transfer count and

starting function ( DATA_IN ). The microcode will then
stert,
wait for BM to finish and then write the data resd back
to
system memory. A check is made to see that STATUS,
MSR and

LAST MEMORY ADDRESS registers are correct.
memory

is then checked for correctness.

The dats

in system

The microcode is "Forced to Zero” for the follow
ing conditions:
“NXM” ( Non Existent Memory ), “MPE” (Memory Parity Errors)
. A
check is mede to see that only one traverse through
micro-location zero is made (START) by the Micror
outine.

TEST 21
This test will force @ Local Storege Parity error
and see that

the Block Mover will stop when the parity

Force Parity error

Storage

is set

in CSR1 eand @

error

location

is detected.
in Locsl

is written ceusing that locetion to have bad perity.

When the Block Mover

is started and reads the Bad Pearit

Location, it should stop the trensfer. LSPE and PE ohouxd set
in CSR1 but the microcode should not be Forced to Zero for

this error condition. The first pass through the diegnostic
POERR is set in CSR1. This will allow the block mover to
complete the trensfer of deta. The second pess will CLEAR

POERR and should halt the BLOCK MOVER end MICROCODE when
bed

perity

is read.

The microcode is “Forced to Zero” for the following conditions:
"NXM” ( Non Existent Memory ), “MPE"” (Memory Parity Errors). A

CZLDIAO LOADABLE IMAGE

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1843
1844
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1846
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1848
1849

1850
1851
1852
1853

1854
1855

1856
1857
1858
1859
1860
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1862
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1865
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1867

1868
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1870
1871

MACRO M1200

25-APR-85 14:05

PAGE 37

check is made to see that only one traverse throug
h
micro-location zero is made (START) by the
Microroutine.

TEST 22

This test will check the Block Movers ability to

do a DATA_IN

followed by @ DATA_OUT while the previous Block Move
in progress.

is still

The PAM microcode first reads Local Storage
to

fetch Memory address. Word transfer count and function for
both trensfers. The microcode will start the DATA_IN then
immediately stert a Dete-out with both transfers using
the
seme Local Storege locations. If the Block Mover hasn't
finished when another block move is staerted., o STALL of the

microcode tekes place until the first block move
has finished.
The Block Mover should be sble to complete both
block move

operations.

A check

is made to see that Status. MSR end Least

Memory address registers sre correct; the deta
memory is then checked for correctness.

The microcode

in system

is “Forced to Zero” for the following conditions:

"NXM“ ( Non Existent Memory ), “MPE” (Memory Parity Errors).
check is made to see thet only one traverse through
micro-location zero is made (START) by the Micror
outine.

TEST 23

This test will check that the STEAL IBUS cycle operates
cormtlz from the Fest-bus (Unibus) end PAM sides of the

IBUS.

DATA_OUT block move

is sterted by the Pem Microcode.

While the block mover is opontin’. a series of reads
end
writes ere done to _Locel Stor
rom the Pem and Unibus et
the seme time. Each time the
is requested while the block
mover is opersting, the requesting operation will Stesl
en IBUS
cycle from the block mover. Both the block move and the
function thet did the steasl should continue to
completion
without error.

The microcode is “Forced to Zero” for the following conditions:

"NXM" ( Non Existent Memory ), “MPE“ (Memory Perity Errors)
.
check is made to see thet onlg one traverse through
micro-location zero is made (START) by the Micror
outine.

—

CZLDIAO LOADABLE IMAGE

MACRO M1200

25-APR-85 14:05

—

———
.
—

PAGE 38

1873

3.0

GENERAL INFORMATION For CIDSCA end CIDSDA Line Card
Tests

1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890

3.1

PROGRAM ABSTRACT

1874

1891
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1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924

The line card repair levcl.:;:,nootic (1) progrems

provide field service and

acturing with a tool

is meant to

to maintain

“digitel ethernet communicetion server*” digital menufa
ctured

line cerds.

The program will provide the coverage necessary to

detect o failure in @ line cerd function. The di
tic is
usually cepsble of isoleting a fault to @ perticuler line
cerd.

Line cerd types covered are M3100 sync,
and the M3102 duel essync line card.
3.2

M3101 high speed sync,

SYSTEM REQUIREMENTS

In order to run this diegnostic program,
minimum hardwere is required:

the following

- A PDP-11 CPU_
"PROTOCOL PROCESSOR (PP)" (PDP 11/24)
- MINIMUM OF 256K WORDS OF SYSTEM MEMORY

- CONSOLE BOOT TERMINATOR (CBT)

- RSX11-S “LDI” SOFTWARE OR XXDPs+ SUPPORTED LOAD MEDIA
- AT LEAST ONE “PAM“ MODULE SET CONSISTING OF AN M3110
& M3111
- THE LINE CARD UNDER TEST

3.3
The

DIAGNOSTIC HIERARCHY PREREQUISITES
1l of the

"PAM” di

manufactured line cerds.

tic progrem

is to test digitel

is assumed that the

“self test

diegnostic” has run,end the “CBT”,“SYSTEM MEMORY"” and "PAM(S)
"
are fully functional. A failure in the aforementioned device
s
could feil this diegnostic and the user should be aware of

this possibility.

3.4

ASSUMPTIONS - RESTRICTIONS

It is essumed that the prerequisite diagnostics have been
executed (refer to section 3.3). The operator should slso
be familier with the operating instructions in section 3.5.
3.5

OPERATING INSTRUCTIONS

Refer to section 2.6 for a complete description of the
operating instructions.
:

NOTE: After masking one pass of the diagnostic the UNIT fleg
cen be used to test a single unit or more.

STA/PASS:1/FLA:HOE/UNIT:1

!test unit 1 only.

STA/PASS:1/FLA:HOE/UNIT:0-4

!tests units 0-4 only.

——

CZLDIAO LOADABLE IMAGE
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
194
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956

1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972

1973
1974

MACRO M1200

25-APR-85 14:05

PAGE 39

STA/PASS:1/FLA:HOE/UNIT:1:3:6

3.6

!tests units 1,3 end 6

HARDWARE QUESTIONS

When & diagnostic is started, the runtime servic
es will prompt
the user for hardware information by typing "CHANGE
HW (L) 2*.

If you answer

“NO" the program will run with parameters

hard coded hardware P-tables.

will

you answer "Y" after a start command,

in the

the runtime services

ask for the number of units (in decimal).
sx2s%

WARNING

s#2ax

[ THE NUMBER OF UNITS MUST ALWAYS BE 16.

)

The line card repair diagnostic will test up to
16 units.
However, the di
tic automatically checks to see if the
requested units
for test are there and drops any not
responding. Also, the “CBT” is checked for a one or two "PAM"
system indicator and drops line cerd unit associated with any
PAM not present or not responding. If the PAM confi
guntion
does not agree with valid PLUTO configurations or with
information in the CBT configuration register an
initislizetion error message is output. An initializati
on

error message

is also output

sizing line cards.

if the prograem has difficulty

Initialization error messages are

by error numbers of the form INI XXXXXX.

indicated

The hardware P-tables exist to communicate operational

parameters for each unit to the diagnostic.

These parameters

consist of an “LOOPBACK"” flag. Loopback indicates that
loopback connector(s) are permanently installed on all
the
line cards that sre selected and that externsl loopback
tests
may be run without operator intervention. The DRS prompt
ing
for P-table paremeters includes @ indication
of the default
value which may be used by responding with a <CR>. All
remaining P-table questions for any unit may be
defaulted by

typing @ single <CTRL 2>.

The operational parameters are:
LOOP-BACK MODE - Indicates

if external loopback connectors

are permeanently

instelled on all the

selected line cerds.

The following P-table dialog alters the defasult by setting

loopback mode for units 0 and 1.

CZLDIAO LOADABLE IMAGE
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008

2009

2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024

2025
2026
2027
2028

MACRO M1200

25-APR-85 14:05

PAGE 40

# UNITS (D)

C4
? 16<CR>

UNIT O
INPUT MARGIN O CONDITION: (0) O ?7<CR>
INPUT MARGIN 1 CONDITION: (0) 252 7<CR>
INPUT MARGIN 2 CONDITION: (0) 252 ?<CR>
INPUT MARGIN 3 CONDITION: (0) 152 7<CR>
INPUT MARGIN 4 CONDITION: (0) 125 ?<Ck>
TEST IN AUTO-LOOPBACK MODE ? (L) N ? <CR>

UNIT 1
INPUT MARGIN O CONDITION:
UNIT 2

UNIT 15

INPUT MARGIN O CONDITION:

3.7

(0) O ?<CTRL 2>

ERROR INFORMATION

There ere three levels of error messages that may
be issued by
@ disgnostic: general, basic and extended.
General error

messages are always printed unless the

(section 2.7).

“IER”

The general error message

flag

is set

is of the form:

NAME
TYPE
NUMBER
ON UNIT NUMBER
TST NUMBER PC:XXXX
ERROR MESSAGE
'"WERE
NAME = DIAGNOSTIC NAME
TYPE = ERROR TYPE (SYS FATAL, DEV FATAL, HARD OR SOFT)
NUMBER = ERROR NUMBER
UNIT NUMBER = O - N (N IS LAST UNIT IN PTABLE)
TST NUMBER = TEST AND SUBTEST WHERE ERROR OCCURRED
PC:XXXXXX = ADDRESS OF ERROR MESSAGE CALL

Besic error messages are messages that contain
some additional
information about the error,
hese are -1u0¥t printed unless
the "IER" or "IBE” flags sre set (section 2.7).
These messages
are printed after the associsted general message.
Extended error messages contain supplementary error
information

such as
ister contents or
bad data.
These are always
printed unless the "IER”, "IBE" or "IXE” flags are
set

(section 2.7).

These messages are printed after the associated

general error message and any associated basic error messages.
This diagnostic does not use any extended error message
s.

Initielizetion error messages are of the format

NAME INI NUMBER MESSAGE

These are always printed and occur because of confi
rotign.
errors found in the diagnostic initialization, problems sizing

| CZLDIAO LOADABLE IMAGE

2030

2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058

2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
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MACRO M1200

25-APR-85 14:05

PAGE 41

line cards or operational parameters which should
not be used

with this specific diagnostic.
diagnostic is aborted.

A warning

line cerd

3.8

After the error

is output when the diagnostic

is found.

The diagnostic

is output,

the

is run and no standard

is then aborted.

CONFIGURATION INFORMATION

The Pluto system configuration presumes that 1 or 2 PAMS
are

attached to the PDP-11/24 protocol processor and that each
PAM
has 8 dash bus slots. The PAM UNIBUS addresses for PAMO
and
PAM1 are known. PAM sizing is done via accessing
a PAMO and
PAM1 register. If a Timeout interrupt results
then it is
assumed that either the PAM is not present or it is incapabl
e

of responding. The number of PAMS which should reside in a
system is determined by reading the display/configurat
ion
register in the console-boot-terminator module. If
one
PAM
exists in a system it should be PAMO.
Line cards of any type(s) may be arbitrarily

dash bus slots subject to system constraints.

sized to determine what type of line cards,
attached to each dash bus slot.

inserted

into the

The dash bus

if any,

are

Default hardware P-tables are set up to run diagno
stics on all
line cards in both PAMS. Automatic sizing determines the

appropriate line card tests to be run. Empty
are skipped, i.e. no tests are run. User and
cards are not tested. If line card types are
tests cen be run from this or companion line

8 warning message will be displayed.

dash bus slots
undefined line
such that no
card diagnostics,

Errors or system configuration violations, if found by
the
diagnostic initialization, will result in initialization error

messages and will cause an abort.

The auto-loopback question is asked for each unit. This
informs DRS that a loopback connector (2 connectors for
dual line cards) is permanently installed on that unit.
All spplicable tests, including external loopba
ck tests,

are executed.

;

If the suto-looback question was answered NO and DRS is run
UNATTENDED MODE, no external loopback tests are run. If NOT
UNATTENDED MODE, the operator is prompted to install
a
loopback connector on the appropriste line card port/unit.

in
in

2093
2094

2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2ll2
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132

TEST 1
Line card INIT,

This
line
that
dash

led and dash bus dual addressing test.X X X

test verifies that the led bit can be set via a
card INIT or by writing @ 1 to the led bit, and
the bit can be cleared. this test also checks for
bus dual addressing.

TEST 2
Line card generate bad parity check.

X X X

This test bit bangs the line parameter reg for the purpos
e
of determining if the generate bad parity bit has any stuck
at or short type faults.

TEST 3
Line card reg cleer on INIT test.

This test inits the line card and then checks
r;gis::rs which should be cleared on INIT are

cleared.

TEST 4
Line cerd register

This test

if the 2661
in fact

initialization test.

inits the line card and then checks

r;gistcro which should be cleared on INIT are
cleared.

TEST S
Line card 2661 register dual addressing test.

- X

X X -

if the 2652
in fact

- X

This test inits the line card and checks the 2661 registers
(reg space 0 - 7) and generic registers (reg space 8 - 15)
for dual addressing.

TEST 6
Line card 2652 register dual addressing test.
This test

XX -

inits the line card and checks the 2652 registers

(reg space 0 - 7) and generic registers (reg space 8 - 15)

for dual

addressing.

-4xm

VOO

N
0

VOOr:

114
000
012
.
.
.

MMM
333

T
E
S
T

—AZmH

TEST SUMMARIES For CIDSCA Line Card Test #1
OO

3.9

PAGE 42

2088
2089
2090
2091
2092

2S5-APR-85 14:05

«c

2078
2079
2080
2081
2082
2083
2084
2085
2086
2087

MACRO M1200

cOZ<OD

}CZLDIAO LOADABLE IMAGE

;CZLDIAO LOADABLE IMAGE

2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2158
2156
2157
2158
2159
2160
2161
2162

2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183

MACRO M1200

25-APR-85 14:05

PAGE 43

Fa4

MMM

221E

141
&
&
B
o IS
.
.

837TY
T
o
R
A.00
$.00
\
MR 4
M.«

333

S
T
N

66NX

TEST 7
Line card 2661/2652 register interference test.
- = =
- = = =
(THIS TEST IS SKIPPED
BECAUSE 2661 MODE WAS REMOVED FROM THE M3100.)
This test checks for interference between registers
of the
2661 and 2652 protocol chips.

TEST 8
Line card 2661/2661

interference test.

==X

This test checks for interference between registers
of the
the 2 2661 protocol chips on the line card.
TEST 9

Bit bang 2661 and generic registers.

- X

This test bit bangs the line card generic registers (re?
addr 8 - 15) and the 2661 registers (reg addresses
0 7).
Also checks scanner retry on mode registers with forced

par

err.

TEST 10
Bit bang line card 2652 and generic registers.

XX -

---.

This test bit bangs the line card generic registers (re

addr 8 - 15) and the 2652 registers (reg addresses 0 - 3).
TEST 11
Modem in register external loopback test.

This test bit bangs the modem

XXX

==X

-X-

-X

in register via the modem

output register and an external loopback connector.

TEST 12
2652 select and 2661 xmitter ready test.

This test verifies that 2661 and 2652 mode can be selected
if applicable. Functioning of 2661 xmit buff avail <TXBAV>,
xnit:er empty <TXEMT> and xmitter ready <TXRDY> bits is
verified.

SESSp—-

————

ECZLDIAO LOADABLE IMAGE MACRO M1200 25-APR-85 14:05 PAGE 44
2185

gi:g

2188
2189
2190
2191
2192
2193
2194
2195
2196
gigg

2199
2200
gggg
2203
gggg

2206

2207

gggg

2210
ggli
12

2213

2§ig

2
2216

551;

2219
2220

2221
2222

2532

2225
2226

2227
2228
2229
2230

gggé

2233

2234

MMM

221

338

6 % N E

XX -

-N-

N
0
.

.
TEST 13
2652 xmitter ready test.

This test checks the functioning of the 2652 transmitter
related bits <TXBAV>, <TXEN2> and <TSOM>. No data is
actually looped. Checks are made in both BOP and BCP modes.
TEST 14
2661 receiver check.

- X

-X-X

This test checks the functioning of the 2661 RCV data avail
<RCVDAV>

and RCVR

in async mode.

enable

<RXEN1>

bits.

The

test

Verifies operation of line par

performed

<SYNC XMIT ERR>.

TEST 1S
2652 receiver check.
This test

avail

checks the

<RXDAV>

XX -

-XX-

-X-

X -

functioning of the 2652 RCV data

and RCVR enable

<RXEN2> bits.

TEST 16

2661 all character length data xfer test.

Loop data pattern through 2661 (async mode)
and 8 bit characters at 19.2 kbaud.

for S,

TEST 17
M3101

transmit buffer ram address sequence test.

Insure that transmitter buffer ram address pointer
being autoincremented, following each write to the

control byte, when 'load ram’
control register.

is
ram

is set in transmit buffer

TEST 18

M3101 transmit ram data test.

Verify that all trensmit data,

are free of stuck bits.

and command byte ram bytes

iCZLDIAO LOADABLE IMAGE MACRO M1200 25-APR-85 14:05 PAGE 45

2254
2255
2256

2257
2258
2259
2260
2261
2262
2263

2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280

2281
2282
2283
2284
2285

M3101 autoload of transmit control ram test.

Verify that with ‘load ram' set in transmit buffer control
,
that a data byte written to the multi memory regist
er will
be placed into the data portion of the transmit ram, and
at
the same time, causes a default value to be placed into
the
same

ram address,

then

autoincrements the

ram address pointer.

TEST 20
M3101 low speed transmit ram data transfer test.

This test,

operating

in the maintenance mode at 19.2 kbaud,

will verify operation of the transmit ram,
mode at 19.2 kbaud

in the buffered

TEST 21

M3101 trensmit buffer ram address overflow test.

in the maintenance mode at 19.2 kbaud this test
Operati
will verify that an overflow of the ram address buffer
will set '‘end of buffer’ and 'transmit buffer avail’.

TEST 22
M3101 buffered mode transmitter underrun test.

Operating in the maintenance mode at 19.2 kbaud this test
will verify that while a data trensmission from the transm
it
buffer ram is taking place, clearing 'send ram’ will cause
a transmitter underrun.

TEST 23
M3101 high
speed bop internal loopback test.
(UTILIZES DIAGNOSTIC MICROCODE)

Operating

in maintenance mode at 500 kbaud, internal

loopback, bop mode,with the line card in the buffered

mode, will verify that deta can be successfully
transferred.

—~ZH

—xm
voOr:

CLCRY
- Y]

VOO

NOMFWI
¢

TEST 19

COZ<D
= OON

OOMWI

HOWI

2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253

=-“unm-

— ———

—_—

—

éCZLDIAO LOADABLE IMAGE MACRO M1200 25-APR-85 14:05 PAGE 46

SAME AS #24, EXCEPT IN EXTERNAL LOOPBACK

2304
2305
sggg

TEST 25
M3101 high speed BCP internal loopback test.
(UTILIZES DIAGNOSTIC MICROCODE)

2308
2309
2310
2311
2312
2313

Operating in maintenance mode at S00 kbaud, internal
loopback, BCP mode, with line card in the buffered
mode, will verify that data can be successfully
transferred.

2317

2318

2319

-«4xm
VOO«
+«

«4Zm

VOOV
«c

VOO«
¢

HOON

NOF WX
*r

TEST 26
M3101

high

speed,

parity error.
This

test

will

BOP mode,

force

XMT

BUFF

RAM

(UTILIZES DIAGNOSTIC MICROCODE)
verify

that on detection of a

transmit

buffer ram parity error, during a data transfer attempt,
'transmitter error’

bit will

set.

———

2315
2316

OO+ WX

gggg

2314

¢t

—

2299

gggg

2297
2298

"
3
4
TEST 24
M3101 high speed bop external loopback test.
(UTILIZES DIAGNOSTIC MICROCODE)

FOZ<B

2294

2295
2296

2287
2288
2289
2290
2291
2292
2293

=M=

25-APR-85 14:05

TEST 1 All baud rates data xfer test.

Loop and check data date pattern through 2661 (async mode)
via internal at all baud rates from SOmbaud to 19.2 kbaud.

Baud rate accuracy

is not checked.

TEST 2 2661 All stop bit length deta xfer test.

Loop data pattern via 2661 asyrc mode with 1, 1.5 and 2
stop bits. Check data and relstive timinto
g verify that
the correct number of ston Lits are being used.

TEST 3 2652 Sync generation test.

XX -

Check the ability of the 2652 to rcnor-te syn characters
from the syn register and xmit ho ding register. Also
check the nbility to strip the 1st 2 syn characters and
the ability to discriminate against non-syn characters.
TEST 4 2652 Trensmitter flag generation test.

X X -

Check the ability of the 2661 (bop mode) to generate and
strip flags characters. transmit data where data = fleg.
Date integrity verifies 0 stuffing.
TEST 5 2652 BOP mode 2ndary addr RSOM and REOM test.

XX -

Loop data in 2652 bop internal loopback mode with secondary
address recognition enabled. Data integrity, RCVR errors
and the ability of REOM to set and clear is checked.
TEST 6 2652 BCP mode

internal date wrap test.

XX -

Loop a data pattern in 2652 internal loopback mode and
verify the data integrity. Test is performed at 19.2 kbaud
and for 5 thru 8 bit character lengths.

«AZm-

—«xm

VOOr:

VOO«

012
‘
.

N
0

2330
2331
2332
2333
2334
2335
2336
2337

MMM
333
1233
000

T
E
S
T

TEST SUMMARIES For CIDSDA Line Card Test #2
OO0V

3.9

PAGE 47

CEL

MACRO M1200

2321
2322
2323
2324
2325
2326
2327
2328
2329

2338
2339
2340
2341
2342
2343
2344
2345
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2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369

———

OZ<V>D:

! CZLDIAO LOADABLE IMAGE

o] ~———

2388
2389
2390
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2400
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2408
2409
2410
2411
e4le
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422

TEST 7 2652 BOP mode data wrsp/ bit stuff test.

XX -

~«Zm

233
113
000
012

VOO

MMM

¢+

3
S
T

=0000N

DUV

PAGE 48

¢«

25-APR-85 14:05

2371
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2377
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2379
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MACRO M1200

OZ<0>D

CZLDIAO LOADABLE IMAGE

X X

Loop a data pattern in 2652 bop mode at 19.2 kbaud for 4
thru 8 bits/char, and at 4.8 kbaud for 2-3 bits/character.

The data pattern exercises the 2652 bit stuffing feature.

TEST 8 2652 0/1/2 Starting syn test.

XX -

X X

Attempt to loop date in 2652 internal loopback bop mode with
0, 1 and 2 starting syn characters. The receiver should sync
up only with 2 leading syns.
TEST 9 2652 Mult stert syns w/wo strip sync.

X X -

X X

Loop a date pattern with multiple starting and embedd
ed syns.
with strip syn disabled verify that 2 starting syns are

stripped.

With strip syn enabled,

syns are stripped.

verify that all starting

TEST 10 2652 Multiple syn character test.

X X -

X X

Deste patterns are looped using different syn characters
to
find stuck bits or lines

in the syn related circuitry.

TEST 11 2652 Syn cheracter discrimination test.

XX -

X X

An attempt is made to loop data using xmitted syn characters
differing from syn characters in the low byte par reg
by 1
bit. If the RCVR syncs up en error is indicated. Correct syn
chars sre also xmitted to verify thet the RCVR cen sync up.
TEST 12 2652 Secondary address mode test.

X X -

X X

XX -

X X

This test checks the ability of the 2652 2ndery address
mode bit to put the 2652 into 2ndery address mode.
TEST 13 Right/wrong secondary address test.

Attempt to loop dets patterns 2ndary addresses which sre
incorrect by 1 bit. No data xfer should occur. Correct endary
addresses are also used to verify that dets xfers cen occur.

2447

<448
2449

2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2456
4.7

246"
2465

2470
2471
2472
2473
2474
2475
2476

2477

2478

This test checks the ability of the 2652 to reject
an all

parties message when not

in the all parties addressed mode.

TEST 15 2652 All parties addressed detection
discrimination test.

X X

With all perties addressed (apa) set, sttempt to loop
date
with 2ndery addresses differing from all parties address

(377) by 1 bit. Dete should not be received.

The correct all

parties address (377) is also used to verify that
data can
be received in this mode. A correct 2nd addr is sent to
verify reception in apa mode.

TEST 16 2652 Abort detection/generation test.

X X

While looping dete a check is made that setting TEOM
sends
abort if idle = 0 and sends a fl
if idle = 1. Abort
reception should ceuse RAB end REOM

that these bits properly cleasr.

to set.

A check

is made

Flag reception should allow

receipt of the character before the flag.

TEST 17 2652 Go-shead gen/detect,sbort with go-shead
test.

Check the functionslity of the 2652

detect features
TEST 18

incl the <RAB/GA>,

X X

go-shead generation and

<TEOM> end <TGA> bits.

2661 Async forced bresk test.

- X

Verify that the 2661 command register bresk bit

is functionel.

TEST 19

2661 Async mode perity error test (no error).

Verify 2661 async mode dets cen be looped with odd and even

parity checking ensbled without s perity error occurri
ng.

TEST 20

2661 Async mode odd/even perity gen/det test.

- X

Loop date with odd and even parity ehcckin’ enabled. Perity
errors are forced and verified vie the perity error bit.
With with parity disabled, the perity err bit should not set.

—«Zwm

-4xm

VOOr:

VOOr:«

MXe
¢ o

XX -

=000N

=OMWI

¢t OOMWUI

iEST 14 2652 All parties addressed enabie test.

NIV

L4
¢t NOWI

PAGE 49

OZ<0D:

2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446

25-APR-85 14:05
=-“uvmMmw

2424
2425
2426
2427
2428
2429
2430

MACRO M1200

CZLDIAO LOADABLE IMAGE

2493
2494
2495
2496
2497
2498
2499

2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
€315
2516
2517
2518

2661 Async overrun test.

TEST 21

Generate an overrun while looping data in 2661 async mode
end verify that the overrun bit sets.

TEST 22

2661

Async mode freming error test.

Check the ability to detect a freming error. Freming

errors are generated by

end RCV clock reates.

looping dete st different

xmit

TEST 23 2652 Error control modes test.

XX
-

This test loops dets in each of the 2652 error control
modes.
Errors sre generasted end error detection is verified. A cneck
is also mede to verify that error detection can be disable
d.

TEST 24 2652 Underrun test.

The 2652 response to en underrun

is checked

in both

BOP end BCP mode with the IDLE bit both set and cleer.
TEST 25 2652 Overrun test.

Generste an overrun in both BOP and BCP mode. Verify thet
the RCVR steatus r;a overrun bit is set, and that it cen
be clesred vie o
VR status reg read, a reset error command,
or by disabling the receiver.

«ZTwm

-xm
VOO

VOOr:

s
r

=00N

NN
e

OZ<OD:

WX
NO

881
OO WUZ

PAGE SO

14:05

2S5-APR-8S

—«“unmau

2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492

MACRO M1200

CZLDIAO LOADABLE IMAGE

CZLDIAO LOADABLE IMAGE
2520
2521
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2532

2533
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MACRO M1200

25-APR-85 14:05

PAGE S1

4.0 GENERAL

INFORMATION For CIDSEA CBT

Test

4.1 PROGRAM ABSTRACT

This progrem

is @ repeir level disgnostic for

(Console,.Boot,Terminator) module.

The CBT (M3112) isA
pinout that contains:

stendard

Hex

module

the

with

M3112

CBT

Unibus

SPC

ROM Bootstrep supporting 8 ROM sockets (64kb totsl).

Off/0On/Lock/Standby key switch

Stert end Test pushbuttons

Four seven segment leds

(e.g.

replece bad unit)

identify

operator

Serisl Line Unit fixed ot
console.

EIA console serial line connector,
the 11/24.

Unibus terminator for the end of the Unibus.

1200

baud,

for

action

virtual

for local control of

Thic_di.gno.tfc has been written for use with

.the

diegnostic

Tntaruce 0 Sie SSorter Sad To 50 SoTey ST ol

4.2 SYSTEM REQUIREMENTS

The Minimum system required is:

11724 Processor with

28Kw of Unibus memory

CBT (Console,Boot,Terminator) module

its SLU1 set to 1200 beud

4.4 PREREQUISITES

The 11/24 option di.groctic (CJDFA) or equivalent must be
to insure a working
SLU1.

4.5 ASSUMPTIONS
The SLUl1

in the 11724 Processor must be functionel.

run

2570
2571
2572
2573
2574
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2577
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2601
2602
2603
2604

2605
2606
2607
2608
2609
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2611
2612
2613
2614
2615
2616
2617
2618
2619
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MACRO M1200

25-APR-85 14:05

PAGE S2

4.6 OPERATING INSTRUCTIONS
Refer to section 2.6 for a complete description
of the
operating instructions.

The following

is a sample CBT diagnostic run:

Start the Diagnostic under DRS

DR> STA/FLA:PNT:HOE/PAS:1
CHANGE HW (L)
TST
TST
TST
T1ST
T1ST
TST
TST
ST

? N

g88gagase

CZLDIAO LOADABLE IMAGE

READ/MWRITE REGISTER TEST
PCR REGISTER TEST
MAINTENANCE REGISTER TEST
RECEIVER CSR REGISTER TEST
DLART INTERNAL LOOPBACK TEST (10 SECS)
CBT TO 11/24 SLU1 TEST (20 SECS)
UNIBUS REGISTER ADDRESS DECODE TEST
ROM CRC-16 CHECKWORD TEST
ST
SEVEN SEGMENT DISPLAY REGISTER TEST
TST 010: SINGLE LEDS DISPLAY TEST
ST 011: CONFIGURATION REGISTER PRINTOUT TEST
CONFIGURATION REGISTER CONTENTS
BIT<8>=1
JUMPER W4 IS NOT INSTALLED
BIT<7>=1
JUMPER W1 IS NOT INSTALLED
BIT<6>=1
JUMPER W2 IS NOT INSTALLED
BIT<S>=1
JUMPER W3 IS NOT INSTALLED
BIT<4>=1
BATTERY BACKUP IS NOT PRESENT
BIT<3>=0 MARGINING BOX IS NOT PRESENT
BIT<2>=0 UNUSED
BIT<1>=1
TEST PUSHBUTTON IS OFF
BIT<0>=1
ONE PAM SET IS PRESENT
ST 012: ROM CONFIGURATION PRINTOUT TEST
ROM O
- PART NUMBER IN ROM = 23-abcde-fg
SLOT NUMBER IN ROM = 0
SIZE IN ROM
= 1KB
CRC CALCULATED
= 000000

( THIS IS REPEATED FOR ALL EIGHT ROMS )
DR>

Tests 11 and 12 will be skiped when the UAM flag is set.
Exemple:
4.7

DR> START/FLA:PNT:UAM

HARDWARE QUESTIONS

When a diagnostic

is started,

the runtime services will prompt

;CZLDIAO LOADABLE IMAGE
|
|

2622
2623
2624

2625
2626
2627
2628
2629
2630
2631
2632
2633 .
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652

2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663

2664
2665
2666
2667
2668
2669

Y —

MACRO M1200

25-APR-85 14:05

PAGE 53

the user for hardware

CHANGE HW (L)

information by printing:

You must enter Y after a STArt command, unless
the information
has
been
preloaded
via
the
setup
utility.
See the XXDP.
manual

for more

information on the setup utility.

The DRS will then ask for the number of units
this diagnostic always enswer 1.
For Example:

CHANGE HW (L)

# UNITS (D)
4.8

test.

For

2?2 Y
T3

SOFTWARE QUESTIONS

This diagnostic does NOT ask any software questi
ons.
4.9

ERROR MESSAGE FORMATS

The error messages are

in the following format:

M3112 HRD ERR 00514 ON UNIT 00 TST 005 SUB 007 PC:12762
CBT Data error in loopback mode
EXPD: 000005

RECV:

0C0004

XOR:

000001

Where:

"M3112"

"HRD ERR" indicates
a
non-recoversble
(hard)
error.
All
CBT
errors
are
considered hard errors, or fatal

is the CBT module name

(FTL ERR) errors.

"00514” is the test and error number.
test S error number 14.

"ON UNIT 00" is Fixed.
unit per processor.

"TST 00S SUB
007"
indicates
executing at error call.

"PC:12762" is the virtual pc at the error.
The pr-ogrn
may actually be executing at a different physical PC
if
it is running under a monitor other than XXDPs.

This example

The CBT consists

test

only

subtest

is
one

was

' CZLDIAO LOADABLE IMAGE

2671
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2708

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MACRO M1200

25-APR-85 14:05

PAGE 54

“EXPD:"

is the expected data.

"RECV:"

is the received data.

"XOR:
" is the bits that
EXPD and RECV date.

are

different

between

the

4.10 TEST SUMMARIES for CIDSEA

TEST 1:

READ/WRITE REGISTER TEST

This test verifies the READ/WRITE register
is
addressable
from the 11/24 and has no bits shorted together or
stuck at
a high or low level.

TEST 2:

PAGE CONTROL REGISTER (PCR) TEST

This test verifies the PCR is addressable
Ind lhas no bits shorted together or stuck
evel.

TEST 3:

from
the
11724
at a high or low

MAINTENANCE REGISTER TEST

This test verifies the MAINTENANCE register is
addressable
from the 11724 and has no bits shorted together
or stuck at
8 high or low level.

TEST 4:

CBT RECEIVER CSR REGISTER TEST

This test verifies
the
DLART
RECEIVER
CSR
register
is
addressable from the 11/24 and has no bits shorted together

or stuck at a high or low level.

TEST 5:

CBT DLART INTERNAL LOOPBACK TEST

This test verifies that data can be transmitted to
the
CBT
serial
line
wunit
(DLART) and received in loop back mode.
In addition the DLART status bits are checked.
TEST 6:

CBT 7O 11/24 SLU1 TEST

This test verifies data can be transmitted between the
CBT
serial
line
unit
(DLART)
and
the 11/24 serial line unit

(SLu1).

TEST 7:

UNIBUS REGISTER ADDRESS DECODE TEST

This test verifies that the
CBT
register
address
decode
logic
is
functioning correctly so that each register will
only respond to their valid Unibus addresses.

—

éCZLDIAO LOADABLE IMAGE

—

MACRO M1200

25-APR-85 14:05

PAGE S5

g;sg

2724

g;gz

2727

g;gg

1034
2731

2732
g;gz
g;gz

2737
g;gg
e

2741

S;:§

2744

2745
27‘6

TEST 8:

ROM CRC-16 CHECKWORD TEST

This test verifies each ROM CRC-

g;gg

2752
g;gi
4
4738

g;gs

is assumed empty

if -1

last locations.

KWOR

(checksum)

for

roms.

is read back from the first and

in veritiad the reslt of e CIE seleuletion Talgiie ot
CHECKWORD blasted into the ROM is zero? R
TEST 9:

SEVEN SEGMENT LEDS DISPLAY TEST

i
This
test : will verif
rify the displa
i
i
y
regist
i
er
will
cause
Unibus
Timeout
if urittcn
into with a byte instruction?

The

Seven

Here

segment

led

is how the digits are

e
e

display

et o

porlag

the

seven

ISy

tested.

rme

also

formed

Each segment and decimal points are lit

segment

individually

sequence.

TEST 10:

SINGLE LEDS DISPLAY TEST

This test will light the single leds in a
fixed
The
CBT
contains Four si
e leds (with room rescr3:: f:r
1

two

more)

status

other

arranged

such

leds

located

The test will

c.b}e

All Leds

g;:g

No Leds

g;:;

Light each Led

g;gg

Turn off each led

This

sequence.

row.

faults

the

Thcy
or

TEST

light the leds

2768

CHEC

Each ROM is read and a CRC-16 CHECKWORD

g;:g

2769

The test
first searches all eight ROM slots
:

slot

g;:;

ifi

will

line

and

in the

used

faults.

START

There

indicate
are

two

switches.

following sequences:

in turn from left to right
in turn

from left to right

is not a Manual Intervention test but will r e

operator to determine if the display is corr:ct.

—

iCZLDIAO LOADABLE IMAGE

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MACRO M1200

25-APR-85 14:05

PAGE S6

TEST 11:

CONFIGURATION PRINTOUT TEST

This is a Manual Intervention test to printo
ut the contents
of
the Configuration Register.
The Configuration Register
is a Read-only register that indicates
which
options
are

present,

TEST 12:

such

as hardware

jumpers on

the CBT module.

ROM CONFIGURATION PRINTOUT TEST

This
is
a
Manual
Intervention
test
to
printout
the
configuration
of
the Roms currently installed in the CBT.
The test sizes automatically for the
roms
and
calculates
the CRC-16 on each ROM.
The calculated CRC-16 is always
required
to
be
zero,
since it includes the CHECKWORD blasted into the ROM.

| CZLDIAO LOADABLE IMAGE

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PAGE 57

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5.0

GENERAL INFORMATION for SYSEXE

The system exerciser (SYSEXE) is a RSX11-S task which
is part
of the DECSA Loadable Diagnostic Image (LDI). Its purpos
e is

to create es much activity between the PDP-11
/24 and PAM/LINE

units as possible. This is accomplished by transmitting
and
receiving 576 byte data messages on all available lines.
These
lines may be M3100/M3101 SYNC or M3102 ASYNC and the
DEUNA. If
mixed line cards are sized by SYSEXE, the majority
line type
will be exercised.
Activity

is built up gradually by phases.

PHASE O - START PAM O AND LOOP DATA MESSAGES ON
EACH LINE
PRESENT.
PHASE 1

START PAM 1 WHILE KEEPING PAM O GOING.

MESSAGES ON EACH LINE PRESENT.

LOOP DATA

PHASE 2 - KEEPING BOTH PAMS GOING START THE UNA LOOPING
DATA
MESSAGES.

5.1

OPERATING INSTRUCTIONS

To execute SYSEXE at the PLU> prompt type “RUN SYSEXE"

then prompt you for number of passes and
with loopbacks connected.

5.2

LINE AND SLOT IDENTIFICATION UNDER SYSEXE
LINE

LINE

slgt 298 )

slgt) 19 )

10)

4 )3

12)

$23%3.13)

)

8)Y7

)

208

)

223

)

13 Y4

12 )

14 3} S

13)

15 )6

14 )

16 > 7

15 )

11)

45)

)

it will

if you want to run

ECZLDIAO LOADABLE IMAGE
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MACRO M1200

25-APR-85 14:05

PAGE 58

6.0

UPDATING CSVLDI.SYS (LDI BLO6)

These

instruction are

intentionally general due to the large

number of possible load device names on VMS and
RSX11lme
systems. See the system manager for the specific
device name

of RLO2 or magtape on the target system.

is also

recommended that you verify the location of the

disk:[targetuic](this area was created when the operational
DECSA software package was installed) for the LDI with the
system manager.

The distribution media is in Filesll format. Label
name is
CZLDIA. After copying, verify CSVLDI.sys size is 1002 blocks.
VMS

installation do:
For RLO2 do:

$ mount rl02:czldia
$ copy/conti
$_From: rl02:[1diJcsvldi.sys
$_To: sysésystem:csvldi.sys
End RLO2.
For Tepe do:

$ mount tape:czldia
$ copy/contiguous
$_From: tape:csvldi.sys
$_To: sysésystem:csvldi.sys
End VMS
RSX1im+

End Tape.
installation.
installation do:
For RLO2 do (DCL assumed):
> mount rl02:czldia

copy/conti

From? rl02:[1diJcsvldi.sys

To? disk:[targetuiclcsvldi.sys

End RLO2.
For Tape do (DCL assumed):
> mount tape:czldia
> copy/contiguous

From? tapo:covldi.s‘s
To? disk:[targetuiclcsvldi.sys
End Tape.
End RSX11.

—

———

ECZLDIAO LOADABLE IMAGE MACRO M1200 25-APR-85 14:05 PAGE 59

!
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2909

2910

7.0

KNOWN PROBLEMS WITH LDI BLO6

This

is the current list of problems with LDI BLO6.

assumed that these are software problems and should
be fixed

in BLO7.

SYSEXE errors when started the second time from PLU »>.
The LDI must be reloaded.

Control C not handled by PLUMON.

Refer to sections 2.7 and 2.8

problem.

000001

.END

M3101 in slot 1 causing M3100s
while running SYSEXE.
%

"NOTES" for help on this

in other slots to error

_——

—

e a—

' CZLDIAO LOADABLE IMAGE

' SYMBOL TABLE

ABS.

000000
000000
ERRORS DETECTED:

——

MACRO M1200

2S5-APR-85 14:05

000
001

VIRTUAL MEMORY USED:

19 WORDS

DYNAMIC MEMORY:
20324 WORDS
ELAPSED TIME:
00:01:16

+CZLDIA.SEQ/-SP=CZLDIA.MEM

(

1 PAGES)

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