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AH-FF45A-MC

July 1985

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Document:	CZLDIA0 DECSA DECSA LOADABLE IMAGE JUL 1985 bw
Order Number:	AH-FF45A-MC
Revision:	000
Pages:	62
Original Filename:	CZLDIA0__DECSA__DECSA_LOADABLE_IMAGE__AH-FF45A-MC__JUL_1985_bw.pdf

OCR Text

DECSA LOADABLE IMAGE

CZLDIAO

AH-FF45A-MC

10F1

JUL 1985

Euauan
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CZLDIAO LOADABLE IMAGE

10
11
12
13

15
16

17
18
19
20
21
22
23
24
25
26
27
28

30
31
32
33
34
35
36
37

MACRO M1200

25 APR 85 14:05

PAGE 1

IDENTIFICATION
PRODUCT

CODE:

.REM «

FF44A-MC

PRODUCT NAME:

CZLDIAO DECSA LOADABLE IMAGE

PRODUCT

DATE:

MAINTAINER:

APRIL-85

DISTRIBUTED SYSTEMS

DIAGNOSTIC ENGINEERING

THE INFORMATION IN THIS DOCUMENT IS
SUBJECT
TO
CHANGE WITHOUT
NOTICE
AND
SHOULD
NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION.
DIGITAL EQUIPMENT CORPORATION ASSUMES NO
RESPONSIBILITY FOR ANY ERRORS THAT MAY APPEAR
IN THIS DOCUMENT.

NO RESPONSIBILITY IS ASSUMED
FOR
SOFTWARE ON EQUIPMENT THAT IS NOT

AFFILIATED

COMPANIES.

THE
USE
SUPPLIED

OR
BY

RELIABILITY
OF
DIGITAL
OR ITS

DIGITAL
DEC

PDP
DECUS

UNIBUS
DECTAPE

CORPORATION:

MASSBUS

CZLDIAO LOADABLE IMAGE

MACRO M1200

25-APR-85 14:05

PAGE 2

40
4]
42

43
44
45
46
47
48
49

50
51
52
53
54
55
56
57
58

DECSA
LOADABLE DIAGNOSTIC IMAGE

USERS GUIDE
APRIL

1985

AC-FFa4A-MC

E1l

PAGE 3

SECTION ONE

Loadable Diagnostic

1.0 General

SECTION TWO

Image

Information for the Loadable Diagnostic

Image

PAM Repair Diagnostics

s \O OO
N O

000~
U BW

N NN

2.0 General Information for CIDSAA and CIDSBA PAM Tests
Program Abstract
2.1
System Requirements
Releated Documents and Standards
Diagnostic Hierarchy Prerequisites
Assumptions
Restrictions
Operating Instructions
Commands
Switches
Flags
Hardware

Questions

e
o- b

Types of Error Messages
Device Error Messages
Test Summeries for CIDSAA PAM Test #1
Test Summaries for CIDSBA PAM Test #2

SECTION THREE

N e b [y
=~ (A = OOV~~~
~~

25 APR 85 14:05

Line Card Repair Diagnostics

VO NN SN

VWU WWANW®W

3.0 General Info for CIDSCA and CIDSDA Line Card Tests
Program Abstract
3.0
System Requirements
Diagnostic Hierarchy Prerequisites
Assumptions - Restrictions
Operating Instructions
Hardwere Questions
Error Information
Configuration Information
Test Summaries for CIDSCA Line Card Test #1
3.10 Test Summaries for CIDSDA Line Card Test
#2

SECTION FOUR

CBT Repair Diagnostic

4.0 General Information for CIDSEA CBT Test
4.1
Program Abstract
System Requirements
Assumptions
Operating Instructions

H (- R -RW

MACRO M1200

[ we~Jdoun

CZLOIAC LOADABLE IMAGE

SECTION FIVE

Hardware Questions

Software Questions
Error Message Formats
Test Summaries for CIDSEA

51
S1
51
52
52
53
53
54

System Exerciser

5.0 General Information for SYSEXE - System Exerciser
5.1
Operating Instructions
5.2
Line and Slot Identification Under SYSEXE

SECTION SIX

Updating the LDI to BLO6

SECTION SEVEN

Known Problems with LDI BLO6

CSVLDI.SYS

37
57
57
58
59

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MACRO M1200

25-APR-85 14:05

1.0

PAGE 4

GENERAL

F1
INFORMATION fcr the Loadable Diagnostic

Image

The LDI consists of many software components residi
ng in one
large image. The purpose of one image is to allow
the testing

of the DECSA Subsystem as configured without user

interaction.

Execution of the LDI (once the image has been
loaded) requires
PLUMON to be loaded in a run state. The VMR utilit
y allows
you to issue a RUN command to an installed task before
the
image is saved. Both the RSX-11S and PLUMON (PLU>) will
be in
this state. PLUMON is the initial controlling task
for the
LDI. Upon initial execution PLUMON will determine the mode of
operation, AUTO or MANUAL. The mode selection in made
from a
value in a CBT read/write register. The CBT ROM code will
deposit a -1 value in this register for AUTO mode and
clear it
for MANUAL mode.

DECSA short self test and LDI load

is selected by first

pressing the “start” button and then when the LEDs
are
flashing at the quick rate pressing the "test”
button.

Manual mode is selected by putting the test button
in the out
position while the LDI is being loaded, as indicated by
the
L 5n in the LEDs.

Automatic mode is selected by the "test” button being
in the
"in" position when the LDI has completed loadin
g and has

started.

Uses of the DECSA TEST BUTTON.
test button

mode

comments

automatic mode

The 5 diags

sysexe should

execute followed by
system boot. Verify
are complete.

out

manual

mode

manual mode

diags

The PLU> should be displayed.
Run SYSEXE selecting # of
passes

out

operating
all

and

loopback.

The PLU> should be displayed.
Run each of the 5 diags. Run
the diags selecting external

loopback.

out

manual

mode

The PLU>

should be displayed.

Type in "AUTO". The S diags
and SYSEXE should run followed
by a boot reguest for the
operating system.

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MACRO M1200

25 APR-85 14:05

PAGE S

Currently there are five diagnostics and a system exerciser

that can be executed either
in MANUAL mode.

in AUTO mode or executed separately

DIAGNOSTICS:

CIDSAA
CIDSBA
CIDSCA
CIDSDA
CIDSEA

REV
REV
REV
REV
REV

SYSTEM EXERCISER:

SYSEXE

C
C
C
C
C

PAM REPAIR TEST @1
PAM REPAIR TEST @2
LINE CARD REPAIR TEST
LINE CARD REPAIR TEST

CBT TEST

¢1
@2

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25 APR 85 14:05

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LOADABLE DIAGNOSTIC IMAGE
MEMORY ALLOCATION
e

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22l
222
223
224
223
226
227
228
229
230
a3l
232
233
234

RSX11

*®

DECNET

UNA

PAM MICROCODE

MICROCODE

*
*

PLUMON

FRUMON

e ey

]

L1 TR L

195
196

205
206
207
208
209
210
ell
el2
213
2l4
213
216

194

197
198
199
200
201
202
203
204

PAGE 6

DRS/RSX

MODULE

SR
kR
R
kR k
kK&
*

PAM DIAGNOSTICS

kkkkk

kR Rk

kk ko

LINE

CARD

DIAGNOSTICS

=
*

LI
Y T I T
*

CBT

DIAGNOSTIC

L YTy

SYSEXE

*
«
*
*

COMMON MSG BUFFER
COMMON DATA BUFFER
DEVICE 1/0 PAGE DEF

=«
=
»
*

* (232212322222
2222
228
0% 7 *

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MACRO M1200

25 APR-85 14:05

PAGE 7

2.0

GENERAL INFORMATION for CIDSAA and CIDSBA PAM Tests

2.1

PROGRAM ABSTRACT

The “PAM“ repair level diagnostic (1) programs is
meant to
orovide field service and manufacturing with a tcol to
maintain the “digital ethernet communication server,*”
“protocol assist modules (PAM). “The program will provide
the

coverage

only.

necessary

isolation
2.2

Fault detection

detect

failures

the

is to the functional

is to board (M3110 or M3111).

"PAM"

level,

module

while

SYSTEM REQUIREMENTS

In order to run this diagnostic program,

hardware

the following minimum

is required:

A PDP-11

MINIMUM OF 256K WORDS OF SYSTEM MEMORY
CONSOLE BOOT TERMINATOR (CBT)
R5X11-S “LDI" SOFTWARE OR XXDP+ SUPPORTED LOAD MEDIA
ATDLEAST ONE "PAM” MODULE SET CONSISTING OF AN M3110
AND
M3111

2.3
-

CPU_

"PROTOCOL

PROCESSOR

(PP)*

(PDP

11/24)

RELATED DOCUMENTS AND STANDARDS

XXDP+

USER’'S MANUAL

THE MANUAL
2.4

set

fault

(CHQUS?.SEQ WHERE

THE REV.

“C" IS THE CURRENT REV.).

LEVEL

DIAGNOSTIC HIERARCHY PREREQUISITES

The goal of the "PAM" diagnostic program is to test
the M3110
and M3111 therefore, it is assumed that the "self
test
diagnostic” has run, and the "CBT" and "system memory
" are
fully functional. A failure in the aforemention
ed devices
could fail this diagnostic and the user should be aware
of
this possibility.

2.5

ASSUMPTIONS

RESTRICTIONS

It is assumed that the prerequisite diagnostics have been
executed (refer to section 2.4). The operator should
also
be familiar with the operating instructions in sectio
n 2.6.
2.6

OPERATING INSTRUCTIONS

Section 2.7

- 2.10 contains a brief description of the Pluto

runtime services (PLU>). For detailed
the XXDP+ user’'s manual (CHQUS).

information,

refer to

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25-APR 85 14:05

2.7

PAGE 8

COMMANDS

There are eleven legal
services (SUPERVISOR).

commands for the diagnostic runtime
This section lists the commands and

gives a very brief description of them.

The XXDP+ user's

manual

has more details.

COMMAND

EFFECT

START
RESTART
CONTINUE
PROCEED
sEXIT
ADD

START THE DIAGNOSTIC FROM AN INITIAL STATE
START THE DIAGNOSTIC WITHCUT INITIALIZING
CONTINUE AT TEST THAT WAS INTERRUPTED
CONTINUE FROM AN ERROR HALT
RETURN TO PLUMON (SEE NOTE)
ACTIVATE A UNIT FOR TESTING (ALL UNITS ARE

CONSIDERED TO BE ACTIVE AT START TIME)
DEACTIVATE A UNIT
PRINT STATISTICAL INFORMATION (NOT IMPLEMENTED
8Y THE LDI)
TYPE A LIST OF ALL DEVICE INFORMATION
TYPE THE STATE OF ALL FLAGS
CLEAR ALL FLAGS

DROP
PRINT
DISPLAY
FLAGS
ZFLAGS

A command can be recognized by the first three charact
ers.
you may, for example, type "“STA” instead of "START".
*NOTE:

2.8

After completion of a diagnostic run, type "EXIT"
at
the DR> prompt to get back to the PLUMON prompt "PLU>"
to run the next diagnostic or SYSEXE. Also refer
to the
NOTE in section 2.8 on switches.

SWITCHES

There are several switches which are used to modify supervi
sor
operation. These switches are appended to the legal command
s.
All of the legal switches are tabulated below with & brijef
description of each. In the descriptions below, a decima
l
number

designated

“DDDDD".

SWITCH

EFFECT

/TESTS:LIST

EXECUTE ONLY THOSE TESTS SPECIFIED IN
THE LIST.
LIST IS A STRING OF TEST
NUMBERS, FOR EXAMPLE - /TESTS:1:5:7-10.
THIS LIST WILL CAUSE TESTS 1,5,7,8,9,10 TO
BE RUN.
ALL OTHER TESTS WILL NOT BE RUN.
EXECUTE DDDDD PASSES (DDDDD = 1 TO 64000)
SET SPECIFIED FLAGS. (SEE SECTION 2.9)
REPORT END OF PASS MESSAGE AFTER EVERY
DODDD PASSES ONLY.
(DDDDD = 1 TO 64000)
TEST/ADD/DROP ONLY THOSE UNITS SPECIFIED
IN THE LIST.
LIST EXAMPLE - /UNITS:0:5:10-12
USE UNITS 0,5,10,11,12 (UNIT NUMBERS = 0-63)

330

331
332
333
334
335
336
337
338

/PASS :0DDDD
/FLAGS:FLGS
/EOP : DDDDD
/UNITS:LIST

CZLDIAO LOADABLE IMAGE
gzo
1

MACRO M1200

25-APR-85 14:05

EXAMPLE OF SWITCH USAGE:

g:g
344

345
346
347
348
349

;gg

82
3

iK1

PAGE 9

START/TESTS:1-5/PASS:1000/E0P:100
The effect of this command will be:

1) TESTS 1 THROUGH S WILL BE EXECUTED.
2) ALL UNITS WILL TESTED 1000 TIMES.
3) THE END OF PASS MESSAGES WILL BE PRINTED AFTER EACH 100
PASSES ONLY.
A switch can be recognized by the first three characters. you

may,

for example,

NOTE:

372
373
374

g;s

377

378
379

380
381

3182
383
ggg

gag
8

388
389
390
391
392
393

"/TESTS:1-S*.

is good practice to set

so you can get back

"EXIT".

STA/PASS:1/FLA:HOE
BELOW IS A TABLE THAT SPECIFIES WHICH SWITCHES CAN BE USED
BY EACH COMMAND.
TESTS

PASS

FLAGS

EOP

START

RESTART
CONTINUE
PROCEED
DROP
ADD
PRINT
DISPLAY
FLAGS

X
X

X
X
X

UNITS

X
X

_-X-X

X
X

ZFLAGS
EXIT

2.9

FLAGS

Flags

are

used

looping

remain

Flags
the

sre

flag

also

HOE
LOE
IERx
IBE*

IXEx*

set

until

All

flags

after

ZFLAGS

set

operational

sre

explicitly

cleared
The

certain

parameters

cleared

using

the

set

start

commend

command
may

startup
flags

unless

also

used

cleared

the

state

specified by

the

flags

the

last

flag

and

set
to

they

e mesceccs
s ccc e mmmmec
e,
r
.-

HALT ON ERROR - CONTROL IS RETURNED TO
RUNTIME SERVICES COMMAND MODE
LOOP ON ERROR
INHIBIT ALL ERROR REPORTS
INHIBIT ALL ERROR REPORTS EXCEPT
FIRST LEVEL
(FIRST LEVEL CONTAINS
ERROR TYPE,

NUMBER,

PC,

TEST

using
clear

switch.

EFFECT
e

such

switch.

With the exception of the START and ZFLAGS

no commands affect

FLAG
amames

error.

switch.

all flegs.

remain

cleared

commands,

394

39S
396

to the PLU> prompt by typing

ggé

363

instead of

the PASS and HALT ON ERROR Flags.,

;gg

354
365
366
367
368
369
370
371

"/TES:1-5"

When running under the LDI

ggg

358
ggg

type

AND UNIT)

INHIBIT EXTENDED ERROR REPORTS (THOSE
CALLED BY PRINTX MACRO'S)

CZLDIAO LOADABLE IMAGE
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400

401
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404
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408
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a11

412

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414
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424

425

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427
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430
43}
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MACRO M1200

25-APR-85 14:05

PAGE 10

PRI
PNT

DIRECT MESSAGES TO LINE PRINTER
PRINT TEST NUMBER AS TEST EXECUTES

BOE
UAM
ISR

“BELL"” ON ERROR
UNATTENDED MODE (NO MANUAL INTERVENTION)
INHIBIT STATISTICAL REPORTS (DOES NOT
RPPLY TO DIAGNOSTICS WHICH DO NOT SUPPQORT
STATISTICAL REPORTING)
INHIBIT PROGRAM DROPPING OF UNITS
EXECUTE AUTODROP CODE
LOOP ON TEST
EXECUTE EVALUATION (ON DIAGNOSTICS WHICH

IDR
ADR
LOT
EVL

HAVE EVALUATION SUPPORT)
*ERROR MESSAGES

ARE DESCRIBED

IN SECTIONS

2.11,

3.10

AND 4.7

See the XXDP+ user's manual for more details on flags. You may
specify more than one FLAG with the flag switch. For example,
to cause the program to loop on error, inhibit error reports
and type

"BELL"

on error,

you may

use

the

following string:

/FLAGS::LO
IER:BOE
E

2.10

HARDWARE QUESTZONS

When a diagnostic is started, the runtime servic
es will prompt
the user for hardware information by typing “CHANGE
HW (L) 2"
you must answer "Y” after & start command unless the hardware
information has been “prelosded” using the setup utilit
y (see
chepter 6 of the XXDP+ user's manual).
When you snswer this
question with a "Y”, the runtime services will ask
for the
number of

units

(ir

decimal).

The "PAM" repair diagnostic will test up to two units.
However, the diagnostic eutomatically checks to see if the

requested units for test are there and drops any
not
responding. Also, the "CBT" is checked for a one
or two "PAM"
system indicetor (CBT DCR BITO) end drops those units
that do
not, according to the sizing program, belong. The
user may

wish to inhibit the droping of units by setting
the flag
"inhibit progrem drop macro (IDU)".

CZLDIARO LUADABLE

423

ITMMAGE

MACRO M1200

25 APR 85 14:05

PAGE 11

@ UNITS

(D)

R
2<«CR>

Pt
aa3
4‘23

g:¥bus Address of “PAM* ? 171200<CR>
Hard Error Interrupt
Vector ? 130 <CR>
Soft Error Interrupt Vector ? 134 <CR>

Pyt
ol
::g
:g?

gfi%bu: Address of “PAM” ? 171000<CR>
Hard Error Interrupt Vector ? 140 <CR>
Soft Error Interrupt Vector ? 144 <CR>
2.11 TYPES OF ERROR MESSAGES

445

pEH

ptH
pt
:gz

ptH

:gg

460

:25
prH
Py

h
levels
error
es that may be issued by
:hz?:g:;;t?c:e;e
n::al. of
basic andmessag
extended.
error
messages are always printed unless the “IER"General_
flag
is
set
(section 2.9). The general error message is of the form:

NAME TYPE NUMBER ON UNIT NUMBER TST NUMBER PC:XXXXXX

ERROR MESSAGE
A

DIAGNOSTIC NAME

WHERE ?Ygg = ERROR TYPE (SYS FATAL, DEV FATAL, HARD OR SOFT)
NUMBER = ERROR NUMBER
UNITENUHBER = 0 - N (N IS LAST UNIT IN PTABLE)

:22
Py
pr2d
4

TST NUMBER = TEST AND SUBTES WHERE ERROR OCCURRED
PC:XXXXXX = ADDRESS OF ERRCRT MESSAG
E CALL
i
messages are messages that contain some additional
?::;:n::?:: abou:O:he
error, .¥:ese ore slways printed unless
the “IER“ or “IBE’' flags ere set
(section 2.9). These
messages ere

pié
p
475

E:::::::io: such os.gzgister contents or good/bad deta. These
are always printed unless the "IER*, “IBE* or "IXE" flags are
set (section 2.9).

:;?
i

pis4
:;;

:;3
Pt

Pt
::2
::2
:::
:gg
49}

printed after the associated genersl message.
error mess s contain supplementary error
These messages are printe

d sfter the
associsted generel error message and any associa
ted basic
error messages.

2.12 DEVICE ERROR MESSAGES
8 that occur in the initielize code., due to the

g;Eg;G.:::;gzn finding fault with the expected end received
PAM configurastion., are as
follows:
a. The SIZE progrem couldn't find PAM1 in the system.
a.1. PAM]1 is not in the system snd should be: Unit O dropped
b. The SIZE progrem couldn't find PAM2 in the system but the
CBT indicates it should
be there (

BITO0=0

in DCR

CZLOIAO LOADABLE IMAGE
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494
495
4%
497
498
499

500
501
502
503
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506
$07

508
509
510
511
512
51%
S14
515

516
517
518

519
520
521

522
523
524
523

526
527
528
529

530
531
532

533
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536
537
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540

S41
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MACRO M1200

2S5-APR-8S 14:05

PAGE 12

b.1.

¢.

PAM2

is not

in the system and should be:

Unit

1 dropped

The SIZE progrem found PAM2 in the system but the CBYV
indicetes that it shouldn’'t be there ( BITO=1 in DCR
).
c.1.

PAM2

is present

The following

and should not be.

is @ list of the basic format followed

printing Device Error

messages

This message says that

to move

Local

data to Local

this diagnostic.

the Micro-Instruction LSI[]

Storage

correctly.

failed

Storage Address Mux Test Failed

Local
Address

Storage Addressing Scheme
in Error

Failed

171234

Expected Datas ==

125

Received Data ==

333

Contents of (SEQAR)

LSI[])

== 00043

This message says that the Soft error Interrupt occurr
ed before

the hard error

interrupt.

Force Hard/Soft error Interrupt

test

failed

Interrupts occurred out of sequence

Lest Interrupt Expected ==

130

last Interrupt Received ==

134

et
it

This message says that an ADD
nibble 2901 slice.

instruction failed

ALU (2901) Function test failed

Expected results == 340
Oprnd 1

==000

Oprnd 2 ==340
Function

ADD

ey Sy

in the high

CZLDIAO LOADABLE IMAGE
548

549
550
551
552
553
554
555
556
557
558
559
$60
Sé61
562
563
564
565
566
S67
S68
So9
570
571
572
573
574
575
576
577
578
579
580
S81
582
583

584
585
586
587
588

589
590
S91
592
593
594
595

MACRO M1200

2S5-APR-85 14:05

PAGE 13

Results == 240

2.13
TEST

TEST SUMMARIES For CIDSAA PAM Test 61
1

This test will check the ability to Read/Write
sll locations
in the PAM address space. The interrupt service routin
e

(VECTOR 4) will set an error flag to

indicate that an

interrupt occurred. The diagnostic does a Read, checks
the
error flag, Write and checks the error flag again. If
an error
flag was set after the read or write, the diagnostic
will

report

the

address

and

the

function

error.

TEST 2

This test will check that CSR1 R/M bits cen be set
and cleared
from the Unibus and can be cleared by “INIT” (Bit
03). All
bits are first written with ones (except "FORCE
PE", "LCPRS",
“INTENB", "INIT", "RUN" "SINGLE STEP") and then checke
d to see
that the correct bits were set. CSR1 is then written
with
zZeros and reread to check that the bits cleared. CSR1
is
again written with ones ( except "FORCE PE”,"LCPRS”,
"INTENB",
“RUN" end "SINGLE STEP") but this time "INIT”
is set (Bit 03)

also. All bits, except Line card Present which
should be cleared when reread.
TEST

is not checked,

This test will check that CSR2 R/W bits can be
set and cleared
from the Unibus and cen be cleared by “INIT"
(CSR1 Bit 03).
The register is mritten with different data patter
ns and
checked to see that the correct bits were set or
cleared.

CSR2 is again written with ones but this time "INIT" is
set
CSR1. All bits should be cleared when read and rechecked
by

the diagnostic.

TEST 4

This test checks for SAl end SAO bits in the WCSA regist
er by
writing several data pattern to the register and

reading/verifying the results of the write.
patterns are used:

125252
052525
031463
007417

The

following

CZLOIAO LOADABLE IMAGE

MACRO M1200

597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612

TEST

641
642

643

644
645
646
647
648
649
650

expected

data,

following patterns

received

are used:

date

and

XOR

dats.

The

252
125

063

017
TEST 6

615

638
639
640

error,

614

620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637

PAGE 14

This test will check for SAQ and SAl bits in WCS
by first
writing all location with a given pattern
and then reading WCS
to verify the data. The diagnostic will dump the address
n

613

616
617
618
619

25 APR BS 14:05

~S,

This test will perform a dynamic check of WCS by using
a
modified Moving Inversions algorithm. Starting with WCS
cleared to all zeros, 24 passes are made (one for each
data
bit) from the lowest to the highest address. Each location
is first read to verify that the background pattern
was stored
correctly, then a single bit is rewritten to the locatio
n and
reread

verify

that

the

new-pattern

was

stored correctly.

This process is repeated until WCS is filled with
all ones.
The next step ( step 2 ) is to repeat the above proces
s on
WCS, now with an all ones background pattern, but this
time
each individusl bit is cleared. This will leave WCS
filled
with zeros and ready for the next step. Step 3 and
4 are the
seme 8s 1 and 2 but the sequence starts at the Highest
WCS
address and works to the lowest. The key to the moving
inversions test is doing the Read-Write-Read sequen
ce as fast
as possible. Therefore, the check of dats is done after
the
Read-Urite-Read sequence has completed.

TEST

This test will check for SA1l and SAO bits in
Local Storage.
All Local Storage location are first written with
a given datea
pattern. The diagnostic then reads all locations
and verifies
the data. If an error occurs, the LS Address, Data Written
,
Date Read and the XOR Data are output to the terminal.
TEST 8
This test will perform a dynamic check of Local Storag
e by

using a modified Moving Inversions algorithm. Starting with
local storage cleared to all zeros, 8 passes are made (one
for

each detea bit)

location

from the lowest to the highest address.

Each

is first read to verify that the background pattern

was stored correctly,

then

a single bit

rewritten

the

location and reread to verify that the new-pattern was stored

correctly. This process is repeated until locsl storage is
filled with all ones. The next step ( step 2 ) is to repeat

the above process on local storage, now with sn all ones
background pattern, but this time each individual bit is

CZLDIAO LOADABLE IMAGE
652
653
654
655
656
657
658
659
660
661

662
663
664

665

666
667
668
669
670
671
672
673
674
675
676
677
678
679
680

681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698

MACRO M1200

25 APR

14:05

PAGE

cleared.

This will

leave

local

storage

filled with

zeros and

ready for the next step. Step 3 and 4 are
the same as 1 and 2
but the sequence starts at the Highest local
storage address
and works to the lowest. The key to the
moving inversions test

is doing the Read-Write Read sequence as fast as possibl
e.
Therefore, the check of dats is done after the
Read-Write-Read
sequence has completed.

TEST

This test will check that a Local Storage parity
error can
be forced by using "Force Parity Error” in CSR1. Force
Parity
error (FPE) is set in CSR1 and then data is writte
n in Local
Storage. The data written should have bad parity and should
cause a perity error (LSPE) when read. The diagno
stic will
read

the

Local

Storage

location

and

then

check

that

LSPE

and

PE both set in CSR1. Several deta patterns are used when
loading local Storage to assure the integrity of the Parity

checkers and generators.

*s+3xx Interrupts

TEST

are disabled

in this test

*sxs&s

This test will check that the 2911 Microsequenc
ers are able to
Sequence through all WCS Addresses. This is accomplished by
loading all locations in WCS with A HALT instruction then
overwriting locations as follows:
Location

0000
0001
0001
1463

RI{O) «<-LS{7760]
BR(1463]
LS[{7761]

2525

1464

2526

7417
7420
7421

Instruction

[1]
<-- R[O]
<-- R{O)

;
;
i

Load A number
Write LS
Branch
Write LS+1

LS(7762]

<-- R[O]

;

Urite LS+2

LS[7763]
LS(END]
HALT

<-<--

;
;
;

Write LS+3
Set done
HALT

BR({2525]

BR(7417])

R[O]
[-1]

in Reg.

; Branch

; Brench

When this Microroutine Runs, Local Storage Locati
ons 7760 to
7763 will be Incremented and the Microsequencers
should halt
at Location 7421. The Mecrocode will report, if an error
occurs, the Expected and Received HALTED SEQUENCER
ADDRESS,
and the Expected and Received contents of LOCAL STORAGE
.

CZLDIAO LOADABLE IMAGE
700

Jos
708
704
e
708
708
708
799
730
;10
715

713
7lg

MACRO M1200

2S5-APR-85 14:05

TEST

PAGE 16

is i
ili
ite the MSR.
Eo;:a;:-gegment-oescriptor-Blo
ck-Ent
ry
is
Furst_s
in CSR1
and then microcode is started. The micro-code Willet write
zeros
to all bits except 6 ( Clock ) in the MSR and then store the
contents of MSR
Local Storage. All bits in the MSR are then
written with onesin except
7.6 and 1 ( hrd-err-int, glock and
sft-err-int ). After several
ycles the MSR is again_
read and the contents stored. micro-c
The
microcycles between write
and read of the MSR is to allow bit 6 (clock)
tc reset. This
test is not a check of Clock timing, only a check
of
read/write bits in the MSR.
h

test of

the

ability

read

and write

TEST 12

1
;ig
e
;ég

721

i test i 11 check to see that the Loca 1 Storagee Addres
A
s
;E;sca:spr:;erly select
the
correct
input
for
the
differe
nt
Storage Addressing modes.
.
tgzgi Stgrage 2525 and 5252
are
the
locatgo
ns used as the
sources and destinations for for the MOV instruc
tions.

722
L
L
;gz

727

.
%geIProgrammable Line Number register must be operatnoqal
this test to work. The Local Storage agdres§ed by Spec!al for
Character MOV instruction is not used in this test. This
instruction will be tested in a later test.

;gg

TEST

3
3
732
T3
I3e
735

there are no Rem A/B address
li;:s SAl/SAO or shorted togethe
All Ran_locatngns. except
locations *S”,"12", and “14%, arer. first
urntten’auth Zero.
The locations 5,12, and 14 are then writte
with Ones,
followed by & read of all other locations tonLocal
Storage.
The
action of writing
ones
will
overwr
ite
any
zero'd
locations address with the
ones if the address

This

test will check that

736

e
720
73
Jas
738

Iyt

743
7485
74

746

;:;
T

73
755
;gg

;

MITATIONS:

together.

Fore example:

lines are tied
if address lipes 0 and 1
are shorted,

then when address 5 is written, locat!on 7 uoulg be
The next step is to rewrit
e all
locations with zero except locations 5,12 end 14
then read
and save in Local Storage the unwritten locations and
(
5,12,1
The action of writing the locations will again force an 4. ).
overwrite into one of the unwritte
overwritten with Ones.

locatnoqs (. 5.,12,14 ) if
the address lines are shorted. The diagno
stic will read Local
Storage an verify the integrity of the data
written to each

Ram location.

TEST 14
i test i 11 check the 2901 Ram 1 locutio
ions for SAl . and SAO
:

;?é:. B:ta“;ntterns are written to Rem and the Ra@ is written
to local storage for verification by the diagnostic. The
following patterns are used: 125, 252, 314 and 360.

‘

CZLDIAO LOADABLE IMAGE

MACRO M1200

25-APR-85 14:05

PAGE 17

755
756

TEST

757

This test will check the ability of the 2901 to rotate the
RAM
left. A ram location is loaded with data to be shifted.
The
data is then shifted and written to Local Storage for

758
759
760
761
762
763

764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800

801
802
803
804
805
806
807
808

examination by

the diagnostic.

Local

follows when the test completes:

LS Address

7760
7761
7762
7763
7764
7765
7766
7767
TEST

Storage

should look

Data

002
004
010
020
040
100
200
001

This test will check that the 2901 RAM can be shifted Right.
Date is loaded into a ram location to be shifted. The RAM
location is then shifted and the results written to Local
Storage for examination by the diagnostic. Local Storag
e
should look as follows when the test completes:

Locel Storage Address

DATA

7760
7761
7762
7763
7764
7765
7766
7767

100
040
020
010
004
002
001
200

TEST 17

This test will check that the Q register and the RAM
can be
shifted left. Both the Q@ and a RAM location are loaded
with
dete to be shifted. The registers are shifted eight times
and
read after each shift

to Local

Storage.

look as follows when the test completes:
Local Storage address

Data

7740
7741
7742
7743
7744
7745

002
004
010
020
040
100

Local

(

Storage should

Q@ register data

)

CZLDIAO LOADABLE IMAGE

810
811
812
813
814
815
816
817
818
819
820
821
822
823

824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
830
851
852
853
854
855

856
857
853

MACRO M1200

25 APR 85 14:05

PAGE 18

7746
7747

200
001

7750
7751
7752
7753
7754
7755
7756

002
004

RAM data

)

010
020
040
100
200

7757
TEST

(

001

This test will check that the Q register and the RAM can
be
shifted Right. Both the @ and a RAM location are loaded with

data to be shifted. The registers are shifted eight
times,
each time writing the shjfted data to Local Storage. Local
Storage should look as follows when the test completes:

Local

Storage

address

Data

7740
7741
7742
7743
7744
7745
7746
7747

100
040
020
010
004
002
001
200

(

7750
7751
7752
7753
7754
7755
7756
7757

100
040
020
010
004
002
001
200

(

RAM data

data

)

TEST 19

This test will check the Q register for SA1/SA0 bits
and Check
that writing the Q/RAM locations do not affect each
other. The
Q is first written with data patterns and each time the
contents is saved in Local Storage. Next, Ram location O
is
cleared and the Q written with 377. The RAM location is then
saved in local storage and again written with ZERO. The
contents of the Q is then saved in Local Storage.

CZLODIAO LOADABLE IMAGE

860
861
862
863
864
865
866

867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884

885
886
887
888
889
890
891
892
893
894
895
896
897
898
899

900
901
902
903
904
905
906
907
908
909
910
911
912

MACRO M1200

25-APR-85 14:05

PAGE 19

TEST 20

This test will check the ALU (

2901

) functions using the

microcode CALC instructions ( the opcode roms
are not tested).
The microcode will fetch two Operands from Local Storage
. Each
function is executed on the Operands and the
results written
to an assigned Local Storage location. The diagnostic
will
read and verify the results of each operation.
Severai passes
through the diagnostic are made with different operand
pairs
to fully check 2901 operetion. Local Storage locations
are
assigned as follows:

Local

Storage Address

Function assigned

7760
7761
7762
7763
7764
7765
7766
7767
7770
7771

"OR"
"AND "
"XOR"
"XNOR”
"NOTRS"
"ADD "
"SUBR"
*SUBS"
Operand
Operand

results
results
results
results
results
results
results
results
1
2

TEST 21
This test will check the ALU ( 2901 ) functions using
the
microcode Opcode "G" instructions in an attempt to check
the
I1/0 of the opcode roms. Each function is executed on an
Operand and the results written to an assigned
Local Storage
location. This test is not an attempt to check the 2901 ALU,
only the opcode roms inputs and outputs. Local Storage
locations are assigned as follows:

Local Storage Address
7760
7761
7762
7763
7764
7765
1766
7767
7770
7771
7772
7773
7774
7775
7776
1777

Function assigned

’

"ADD*
"ADD"
“SUBS”
“SUBS”
“SUBD”
“SUBD"”
“OR*
"OR*
"AND*
“AND
»XOR"
"XO0R "
“XNOR"
"XNOR”

results
results
results
results
results
results
results
results
results
results
results
results
results
results

DONE FLAG

(Opcode 40)
(Opcode 50)
(Opcode 41)
(Opcode 51)
(Opcode 42)
(Opcode 52)
(Opcode 43)
(Opcode S3)
(Opcode 44)
(Opcode S4)
(Opcode 46)
(Opcode $6)
(Opcode 47)
(Opcode 57)

CZLOIAO LOADABLE IMAGE

MACRO M1200

25 APR 85 14:05

PAGE 20

g%g

TEST

916
917
918
919
920

This test will check that all read modify write instructions
used on Local Storage work correctly. The test mainly
checks
the two Opcode Decode Roms on the M3110 board. Microco
de
operates on instruction dependent operands stored in Local
Storage. The operands are chosen to assure that Both 2901

921
922
923
924
925
926
927

slices must work on the data. The Diagnostic will then check
Local Storage locations for correctness of data and report
any errors.

TEST 23

This test will check

that the CALL

and RTS

functions

928
929
930
931
932
933
934

Microcode work and the Micro-Stack is the correct depth. Four
consecutive CALLS are made to different routines in WCS. Each
routine does a CALL to the next routine until the last routine
is reached. The last ( routine 4 ) Microroutine writes a
location in Local Storage and then does an RTS to the
previously called routine which also increments s Local
Storage location and an RTS. The process is continued

936

empty and the Micro-PC has returned to the starting

935
937

938

939

940

(Increment Local Storage then do RTS) until

the Micro-Stack

Micro-Address+«i.

read

Diagnostic

944

Address

946
947

948
949

950

952

953

954

955
956
957
958

959
960
961
962
963
964
965

will

then

the

Micro-Routines were hit.

Local

Data

R LT
T R PP :
7760
001

945

951

Storage

that all

Storage should contain the following:

941

942
943

Local

tc verify

7761

001

7762

001

7763

001

7764

001

should

contiguous

TEST

noted
WCS

that

the

locations

Micro-Routines
as

may

are

appear

NOT
the

loaded
listing.

This test will check the POP function in Microcode. Four
consecutive CALLS are made to different routines in WCS.
Each
routine does a CALL to the next routine until the last routine
is reached. The last Microroutine ( routine 4 ) writes a

location in Local Storage and then does three consecutive POPs
of the Micro-Stack followed by an RTS. The RTS should bring
the Micro-PC back to the starting Micro-Address+l. Local
Storage will then be read by the Diagnostic to verify that the
first and last Microroutines increment Local Storage (NO OTHER
MICROROUTINE WAS RETURNED TO). Local Storage should contain
the following:

CZLDIAO LOADABLE IMAGE

967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000

1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015

MACRO M1200

2S5-APR-85 14:05

PAGE 21

Address

Data

7760
7761
7762
7763
7764

001
000
000
000
001

It should be noted that the Micro-Routines are NOT
loaded
in contiguous WCS locations as it may appear in the
listing.
TEST 25

This test checks that the Micro-sequencer is capabl
e of Single
Stepping through a Microroutine and the Micro-sequencer
address register is operating correctly. The micro-r
outine s
single-stepped through each micro-instruction while examining

the

contents of

the

Sequencer

address

the

address

is correct in the register, then the Sequencer is
single-stepped again. This process continues until the
Micro-routine has halted. Local Storage is then examin
ed to
verify that all instructions functionea correctly.

Local Storage should contain the following:
Address

Data

7760

Q01

7761
7762
7763
7764

001
001
001
001

It should be noted that the Micro-Routines are NOT
loaded
in contiguous WCS locations as it may appear in the listing
.
TEST 26

This test will check that the SYNC bit in the Microw
ord will
halt the Microprocessor and will set PE and SYNC ACK in CSR1.
A Microroutine is loaded that has SYNC set in two of
the

microwords. The diagnostic will start the microcode and
wait
for SYNC ACK and PE to set and the RUN bit to clesr
in CSR1.

SYNC ACK and PE are then cleared and RUN reset to allow the

Microroutine to continue.
repeated

examined.
reported.

and

the

expected

Any errors

Again the
results

aforementioned sequence
the

Microroutine

in status or the Microroutine results

CZLDIAO L OADABLE IMAGE
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032

MACRO M1200

25 APR 85 14:05

TEST 27

This test will check that a WCS parity error can
be forced and
the correct bits set in CSR1. A Microroutine is loaded
in Wes
with a bad parity microwords. The diagnostic will start
the

routine and check that WCSPE and PE both set in
CSR1. Process
on error is al3o set so the Microroutine should complet
e the
Microroutine correctly.

ssx25x Interrupts are disabled

Local

Storage

Local

Storage Address

1050

1051
1052
105%
1054
1055
1056
1057
1058

1059
1060
1061
1062

1063

1064
1065
1066
1067

in this test

locations are assigned as

7760
7761
7762
7763

1033
1034
1035
1036
1037
1038
1039

1040
1041
1042
1043
1044
1045
1046
1047
1048
1049

PAGE 22

7764

7770
7771

follows:

Function assigned
“OR"
“AND "
“X0R*"
"XNOR"
"NOTRS"”
"ADD"
"SUBR"
“SUBS”
Operend
Operand

7765
7766
1767

sssess

results
results
results
results
results

results
results
results
1
2

TEST 28

This is & check of the Special Character Recognition Register
bits O to 2 and Mux. The microcode loads the Special Characte
r
register (SCR) by doing consecutive loads of the Destination
Register (DR). Bits O to 2 of the SCR select the
bit in the
DR to be tested. If the selected bit is set then the Branch on
Special Condition will be teken. Both branch and no branch
conditions are tested ( bit under test set and cleared ) for

all bits

in the destination register.

TEST

This

is a check

that Local

Storage cen be addressed by Special

Char. register. Local Storage cen be addressed by a
combination of Special Character register, Line Number

register and Microword. The Line Number register
contents is
used as LS address bits 3 to 7, while the Special Char. reg.
contents is used as LS eddress bits O to 2 end 8 to 9. LS
address bits 10 and 11 are derived from the Microword.
Locations 2525 end 5252 in Locel Storage are used in the
transfer of date. These locations correspond to setting and
clearing each bit in the Local Storage address. The test is
successful if deta is correctly moved to and from these
locations.

CZLDIAO LOADABLE

1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082

1083
1084
1085
1086

1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1108
1106
1107

IMAGE

MACRO M1200

25 APR 85 14:05

TEST

PAGE 23

This test will check that the Interlock function is
work ing
correctly. The microcode loads a location in Locsl Storage
with Bit O Set. The location is then complemented-leavi
ng the
location with bit 0 clear ( 376 )- and the interlock brench
is
tested. Since Bit 0 was set before the compliment functio
n,
the interlock flop will set and the brench will
be taken. The
locel storage location is again complimented (001) leaving
bit O set and the branch is again tested. Since bit 0 was
clear before the compliment, the branch will not be taken.

TEST

This test will check that the microcode can do a
CALL, RIS and
POP on a condition code. The interlock condition
is used only
because forcing interlock requires minimal hardware and
because it has slready been tested. No attempt is made
to test

all the possible condition codes only the Micro-sequencer
control bits are tested. Local Storage locations are used to
save function indicator codes as follows:
Local Storage Address
7760
7761
7761
7761
7775
7776
7777

function

Work Location
CALL_IL (]
RTS_IL
POP_IL
ERROR FLAG
ERROR FLAG
DONE
FLAG

When the function

routine will

write

1
1

or
or
3 or
5 or
1
1
377

code
376
2 (condition

4
6

is sterted (CALL_IL,
its code to Local

set

clear)

(condition set - clear)
(condition set - clear)
( Micro-Stack error )
(Function error)

POP_IL or RTS_IL),

Storage.

If the

the

routine

worked then the test continues to the next function; but, ;f
the routine failed then the error flag is set and the
Hicroroutine halts lesving the failing functi
on code in Local
Storege.
TEST 32

This test will check

the Micro-Sequencer control

P 00 oo §ots P

oo o

~ OOV NONLW

PN N

[t et ad et et ad ol o

|t vdatetad
ad ot ad o

Oring Mux during & CALL on Low Nibble.

logic

The destination

end the

register is loaded with a datas pattern and @ CALL_L
N [) is
done to & 16 location target ares. The CALL_LN will “OR” the

low nibble of the destination register with bits 0 to 3 of the
celled address. Each locetion in the target sres will
increment the seme location in Local Storasge until the teble
is exhausted and the RTS is performed. If the first location
in the table is hit (lowest address in the table), then the

number

in Local

Storage when when the RTS

is performed will

"20" (octal) if the location “12" (oct.) is hit then the Locesl
Storage location will contain @ "6". Seversl dats pstterns are

CZLDIAO LOADABLE IMAGE

MACRO M1200

25 APR-85 14:05

PAGE 23

1123
1124
1125
1126
1127
1120
1129

loaded to the destination register to check the integrity of
the Oring Mux during the call and are as follows:

1133
1134
1135
1136
1137
1138
1139

TEST

005
012

014
165
172
174

1130
1131
1132

1150
1151
1152
1133
1154
1155
1156
1157
1158
1139
1160

1161
1162
1163
1164
1163
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177

This test will

check

the Micro-Sequencer control

Oring Mux during a CALL on High Nibble.

logic

The destination

end the

register is losded with a dats pattern end o CALL_H
N () is
done to a 16 location target ares. The CALL_HN will
"OR"” the
high nibble of the destination register with bits 0 to 3 of
the called address. Eech locetion in the target sres will
increment the same location in Local Storage until
the table
is exhausted and the RTS is performed. If the first locatio
n
in the teble is hit (lowest address in the table), then
the

number

Local

Storage

when

the

KTS

is performed

will

“20“ (decimal) if the locetion “12" (oct) is hit then the
Locel Storege location will contain & “6“%. Several deta

patterns

ere

losded to the destination

integrity of the Oring Mux during the call

to check

the

and are as follows:

120
240
300
137

257
317
TEST

This test will check that the Micro-sequencer is
sble to
brench correctly on High Nibble end Low Nibble. The
test only
checks that the braenches cen be taken properly without

affecting the micro-stack. It should be sssumed that the Oring
Mux is working properly by virtue of previous testing.
TEST 35

This test will check Bit-Test Mux and the Micro-sequence
r
functionslity by using micro-code Bit-Test instructions.
The
micro-code floats & "1 on a background psttern of zeros end
a “0“ on & background pattern of ones through the destinstion
register. The Micro-code sequence is os follows:
A.

Do the
& WIN
I

1140
114}
1142
1143
1144
1145
1146
1147
1148
1149

folloming for bits O to 7

Set the bit to test.
Test the bit.
Compl iment the bit pattern.
Test the bit.

1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
l222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232

25-APR 85 14:05
TEST

PAGE 25

This test will check

effect,

that the

"N”

bit

wi)l

set/clear

end not

or be affected by the Z.C or V condition codes.

The

Micro-code will write @ register with a negati
ve number and
then store the register contents in Locel Storage. The
condition codes are then checked by taking the correct
branch.

If the branch fails,

en errc~ flag,

CC set/cleer flag.

used
and a function code are written to Local
function codes are as follows:
BMI

BPL

BEQ ==

BNE

BCS ==
BCC ==

BVS ==
BVC ==

TEST

Storage.

deata
The

NOVBLN=O

1179
1180
1181
1182
1183
1184
11685
1186
1187
1168
1189
1190
1191
1192
1193
1194

MACRO MI200

This test will check that the “C” bit will set/clear and not
effect, or be affected by the Z,N or V condition codes. The
Micro-code will write two registers with different
operands
for the ALU to to ADD. The condition codes are then
checked by
" taking the correct branch. If the branch fails, an error fleg,

CC set/clear fleg, dats used,

results of the add and a

function code are written to Local Storage.
sre as follows:

BMI ==
BPL ==
BEQ ==

BNE

BCS ==
B8CC ==
BVS ==

BVC ==

The function codes

NOVNSBWN-O

CZLDIAO LOADABLE IMAGE

TEST 38

This test will check that the

effect,

“V” bit will set/clesr and not

or be effected by the Z,N or C condition codes.

The

Micro-code will write two registers with different opereand
s
for the ALU to to ADD. The condition codes asre then checked
by
taking the correct brench. If the branch fails, an error
fleg,

CC set/-lear flag,

data used,

results of the add end o

function code are written to Local
ere as follows:

BMI == 0
BPL == 1
BEQ == 2

Storage.

The

function codes

1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250

MACRO M1200

25-APR-85 14:05

PAGE 26

BNE

BCS
BCC
BVS
BVC

==
=»
==
==

TEST

NN bew

!CZLDIAO LOADABLE IMAGE

This test will check that

effect,

the

"Z" bit will set/clear and not

or be affected by the N,C or V condition codes.

The

Micro-code will write a register with data patterns to
set or

clear the Z Bit. The condition codes are then checked by
taking the correct branch. If the branch fails, an
error flag,
CC set/clear flag, data used
end a function code sre written
to Local

Storage.

The function codes are as follows:

1251
1252
1253
1254

1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269

1270

1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286

1287

TEST 40
This test will check the hard error interrupt control
function
through interrupt vector 130 or 140 (PAM1 or PAM2).
An

interrupt

is forced by setting "Hard Error Interrupt”

Micro-code Status register.

The

interrupt service

( HARDSERV ) will save the status in CSR1,
condition and restart the micro-code.

in the

routine

clear the error

The interrupt service routines for hard and soft error
interrupts use a common flag word in memory and
its format
as follows:

Bits O
Bit
8
Bit
9
Bit 10
Bit 11

to 7 = Interrupt Vector (Written by Service routin
e)
= Hard Error Interrupt (Vector 1307140 Ser. rout. sets)
Soft Error Interrupt (Vector 134/140 Ser. rout. sets)
= Double interrupt through vector 130/14)
= Double interrupt through vector 134/144

If the reported CSR1 status

routine did not

is O then the

read status at

time of

interrupt service

interrupt.

TEST a1

This test will check the Soft error

interrupt control

function through interrupt vector 134 or 144 (PAM1 OR
PAM2).
An interrupt is forced by setting “Status Segment Descriptor

Block Interrupt”
The

in the Micro-code Status register.

interrupt service

routine(

SOFTSERV

) will

save the status

CZLDIAO LOADABLE IMAGE

1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1302
1306
1307
1308
1309
1310

1311
i312
1313
1314
1315
1316

1317
1318
1319

1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341

MACRO M1200

25 APR 8S 14:05

PAGE 27

in CSR1 at
The status

interrupt time and load the interrupt flag word.
in CSR1 should reveal that the Run bt remained
set.

The interrupt service routines for hard and soft
error
interrupts use a common flag word in memory and
its format
as follows:

Bits 0 to 7 = Interrupt Vecter (UWritten by Service
routine)
Bit
8 = Hard Error Interrupt (Vector 130/140 Serv. rou. sets)

Bit

9 =

Soft Error Interrupt (Vector

Bit 10 = Double
Bit 11 = Double

134/144 Serv.

interrupt through vector 130/140
interrupt through vector 134/144

rou.

sets)

If the reported CSR1 status is O then the interru
pt service
routine did not read status at time of interrupt.
TEST 42

This test will attempt to force both Hard error and Soft
error
interrupts through inte-rupt vectors 130/140 and 134/144,
respectively. The interrupts are forced by settin
g "Hard Error
Interrupt” end "Status Segment Descriptor Block Interrupt” in
the Microcode Status register. Both bits, in the microc
ode
Status register, are set at the same time this should cause
the Hard Error Interrupt to occur first ( Vector
130/140 ) and
then the Soft Error Interrupt ( Vector 134/144 ).
The hard
error interrupt will halt the PAM ; therefore, the RUN bit
is

reset by the interrupt service routine. The soft error
interrupt has no effect on the PAM microprocess
or and will
halt the PAM,

The interrupt service routines use a common flag word
memory to indicate which interrupt occurred first.
The Flag Word is written as follows:

Bits O
Bit
8
Bit
9
Bit 10
Bit 11

2.14

not

to 7 = Interrupt Vector (Written by Service routine)
= Hard Error Interrupt (Vector 130/140 Ser.
rout. sets)
= Soft Error Interrupt (Vector 134/144 Ser. rout.
sets)
= Double interrupt through vector 130 or 140
= Double interrupt through vector 134 or 140

TEST SUMMARIES for CIDSBA PAM Test #2

TEST

This test will check the path to and from the Dash Bus using
Scanner "Maintenance Mode” in "Address Wrap” and the 11/24
Dash Bus Window.
The test sequence is as follows:
1.
2.
3.

Set CSR2 Bit 13 ( Data Address Wrap )
Set CSR1 Bit S
( Maintenance Mode )
Read Dash Bus address window

CZLDIAO LOADABLE IMAGE

1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358

1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370

1371

1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395

MACRO M1200

25 APR-85 14:05

PAGE 28

The data read from the Dash Bus wirdow should
consist of the

contents of CSR2 Bits 0-3 in the high nibble
(Bits 4-7) the
current Dgsh Bus window number should be in the
low nibble

(Bits 0 3).

TEST

This test will check the path to and from the Dash Bus using
Scanner "Maintenance Mode" in "Data Wrap” and the 11/24
Dash

Bus Window.

The test sequence

1.
2.
3.
4.

is as follows:

Clear CSR2 Bit 13 ( Data Address Wrap
Set CSR1 Bit S
( Maintenance Mode )
Urite the NDash Bus address window
Read the Dash Bus address window

)

The date read from the Dash Bus window should be the
same as
the data written. Any window location read should
fetch the
same

data,

indifferent

the

window

location

wrijtten.

1EST 3

This test will attempt to force a DASH BUS parity error
through the 11/24 DASH BUS Window. The diagnostic
will set
"Maintenance Mode"” and "Force Parity Error” in
CSR1 ( Bits 5
and 4 ) and then read an address in the Dash Bus
Window.
Status is then checked to see that "Dash PE" sets
in CSR1 and
“11/24 Dash PE" sets in CSR2. The process is again repeate
d
and the error bits are written with a 1 to check that
both

clear. The final check is to force the error and then
set INIT
to again check that the error bits clear.
TEST 4

This test will check the ability of the PAM to read
data from
the Desh Bus. This is accomplished by setting the "Addres
s

Wrap” bit in CSR2, "Maintenance Mode" in CSR1
and having the
PAM microcode do reads to the Dash Bus. The
microcode loads
the desired line number, using the progr
ammable line register,
and reads the desired Dash Bus Register (DBR).
The data read
should be a combination of the Line Number and the Registe
r

number:

BITS 7 70 & == Line Number
Local

Storage will

7760 ==

(

look
last

BITS 4 TO 0 == Register Number

as follows:
line number used

)

If the branch condition fails for a specific line number,

line number

error

in error will be saved

flags will

set

in 7760 and one of the

as described below.

the

CZLDIAO LOADABLE IMAGE

1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424

1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445

1446
1447
14438
1449

MACRO M1200

2S5-APR 85 14:05

PAGE 29

7761
7762
7763
7764
7775

==
==
==
-=

125
252
314
360

Dash

(
{
(
(

Bus Parity

and

Error

line

(BPE)

number

taken

Error
.

(BDE)

This is the first test that will check the branch
conditions “BPE” ( Branch on Dash Parity error ) and

“BDE"” (

TEST

)

Branch was

if bit 0 == 1,
7776 == Read Not Done OR Dash Bus Parity
Branch did not clear if bit 0 ==
NOTE!!

wrapped

)
)
)

Branch on Read Not Done or Dash Parity Error).

This test will check the ability of the PAM to do WRITES
to
the Dash Bus. This is sccomplished by clearing Data/A
drs wrap
in CSR2, Setting "Maintenance Mode” in CSR1 and having the
PAM
microcode write date to the DBR's. The microcode
loads the the
line number and writes a Dash Bus Register with a data
pattern.

pattern

is the same

DBR -

read

different

DBR

read to verify

as was written.

different DBR

)

that

the

data

The above process (

write

is done with several data patterns

to verify the integrity of the data path. An attemp
t is is
also made to test the STALL feature by doing succes
sive writes,
with different data patterns, to the dash bus each
time a
write/read cycle is done.

Local Storage will
7760 ==

look as follows:

360

(

Lest Data Pattern Written

)

If the branch condition fails for a specific data patter
n
used, the pattern in error will be saved in 7760 and one
of
the error flags will set as described below.

7761 == 125(Date
7762 == 252(Data
7763 == 314(Data
7764 == 360(Data
7775 ==
7776 ==

Pattern
Pattern
Pattern
Pattern

Read)s**If
Read)ssIf
Read)**If
Read)*sIf

NO
NO
NO
NO

Parity
Parity
Parity
Parity

Error
Error
Error
Error

on
on
on
on

read
read
read
read

»*
==
s»
s#

Dash Bus Par Error (BPE) Branch was taken if
bit 0=1.
Read Not Done OR Dash Bus Parity Error (BDE) Branch

did not clear

if bit 0 ==

TEST 6

This test will attempt to force an Underrun condition and
Transmit Error in Scanner "Maintenance Mode”. The PAM
microcode writes data to the Dash Bus that has “Bit 2" set
(Bit 2 corresponds to XMIT ERR in the line status registers),

CZLDIAO LOADABLE IMAGE
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476

1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503

MACRO M1200

2S5-APR-85 14:05

PAGE 30

Microcode

then waits

informs the diagnostic
for

response.

thet the data was written and

The Macrocode will set “Sync”,“Transmit Flag” and
"Maintenance
Mode”, then tell the Microcode to proceed. The PAM
microcode
will, when "Scan Entry” sets in the MSR, read and
,in Local

Storage,

and the

store the contents of the

"MSR".

the function

The

Microcode then

is done.

If the microcode

“Date FIFO

"Status FIFO"

informs the Macrocode

that

is unable to flush the FIFQ's correctly,

which indicates that Scanner Entry remains set,
will set & Timeout flag in LS location 7776.

the microcode

TEST 7

This test will attempt to force a "Receive Error” condit
ion
“Synchronous mode"”, using Maintenance mode.

The PAM microcode writes a data pattern, thet the Macroc
ode
has passed to Locel Storage, to the Dash Bus and
waits for a
response from the diagnostic.
The Macrocode will then set "Sync” and “Receive
Flag”
set "Maintenance Mode"” in CSR1 and tell the
microcode
continue.
The PAM microcode will,
read and store

(in

Local

when

"Scan Entry” sets

Storage)

in CSRZ,
to

in the MSR,

the contents of

the

"Data

FIFO “, "Status FIFO" and the "MSR". The Microcode
then
informs the Macrocode that the function was done.

The contents of the "Status FIFO* and "Data FIFO"
is dependent
on the data pattern written to the "Dash Bus” and
whether the

“Sync” bit

is set

"CSR2".

"Synchronous” mode bits 0 to 3

will cause a "Receive Error” to set in the “Statu
s FIFO”". Two
entries will be entered in each FIFO for the error
condition
as follows:

STATUS FIFO
1. Error set
2. No error set

DATA FIFO
Line Reg. 1
(
Char. in Err.(

DATA WRATTEN
DATA WRITTEN

)
)

Bits 4 to 7 should not cause an error condition and the
FIFOS'
will look

as follows:

STATUS FIFO
1. No Error set
2. NO Error set

DATA FIFO
Received Char,
Received Char.

If the microcode is unable to flush the FIFQO's correct
ly,
which indicates that Scanner Entry remains set, the microcode
Wwill set a Timeout flag in LS location 7776.

CZLDIAO LOADABLE TIMAGE

1505
1506
1507
1208
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523

1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544

1545
1546
1547
1548

1549

1550
1551
1352
1553
1554
1555
1556
1357
1558

MACRO Mi200

25-APR-85 14:05

PAGE 31

TEST 8
This test will attempt to force a "Receive Error”
condition
"Asynchronous mode”, using Maintenance mode.

The PAM microcode writes a data pattern, that
the Macrocode
has passed to Local Storage, to the Dash Bus and
waits for a
response from the diagnostic.
The Macrocode will then set "Enable Scan Cntr”
and "Receive
Flag” in CSR2, then set “Maintenance Mode” in CSR1
and again
wait for response from the PAM.

The PAM microcode will,
read and

store

(in Local

when

"Scan Entry” sets

Storage)

the

in the MSR,

contents of

the

"Data

FIFO “, "Status
FIFO" and the "MSR". The Microcode then
informs the Macrocode that the function was done.

The contents of the "“Status FIFO" and "Data FIFO"
is dependent
on the data pattern written to the "Dash Bus” and whether
the
"Sync” bit is set in "CSR2".

"Asynchronous” mode bits 3 to 5 will cause a

to set in
each FIFO

the
for

“Status FIFO"”. Two entries will
the error condition as follows:

STATUS FIFO
1. Error set
2. No error set

DATA FIFO
Line Reg. 1
(
Char. in Err.(

All bits , other than bits 3 to 5,
condition and the FIF0S’ will look

STATUS FIFO

1.
2.

DATA WRITTEN
DATA WRITTEN

)
)

should not cause an error
as follows:

DATA FIFOQ

No Error set
No Error set

If the microcode

"Recejve Error”

be entered

Received Char.
Received Char.

is unable 40 flush the FIFO's correctly,

which indicates that Scanner Entry remains
set,
will set a Timeout flag in LS location 7776.

the microcode

TEST 9
This test will attempt to force a “Receive Error” conditi
on
"Synchronous mode”, using Address Wrap.
The Microcode writes a location in Local Storage
Macrocode that it is ready to proceed.

The Macrocode will then set

Wrap”

in CSR2 and then set

Diagnostic then

informing the

“Sync”, "Receive Flag” and "Address

"Maintenance mode”

in CSR1.

The

informs the PAM that the function was done.

The PAM Microcode will,

when

“Scan Entry” sets

in the MSR,

CZLOIAO LOADABLE IMAGE
1560
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MACRO M1200

25 APR 85 14:05

read

PAGE 32

and store

FIFO ",
informs

(in

Local

Storage)

the

contents

the

“Data

"Status FIFO" and the “MSR". The Microcode then
the Diagnostic that the function is done. This test

loops through all the line numbers.

The contents of the “Status FIFO" and "Data FIFO"
s dependent
on the “Dash Bus” address the "Scanner” is referencing
and
whether the “Sync” bit is set in "CSR2".

The Scanner reads Line Register "1",
when it sees a Receive
Flag in Line Register "9" the address currently on the Dash
Bus ( Line Register 1 ) will appear as data of Line Registe
r
"1". Therefor, an error will be recorded in the status
FIFQ
because "Bit 00" will be set.
In "Synchronous” mode bits O to 3 will cause "Error” to
set in
the "Status FIF0" . Two entries will be entered in each
FIFO
for the error condition as follows:

STATUS FIFO
1. Error set
2. No error set

If the microcode

DATA FIFO
Line Reg. 1 (ADDRESS WRITTEN)
Line Reg. O (ADDRESS WRITTEN)

is unable to flush the FIFO's correctly,

which indicates that Scanner Entry remains set,
will set a Timeout flag in LS location 7776.

the microcode

TEST 10
This test will attempt to force a "Recejve Error” condit
ion
"Asynchronous mode”, using Address Wrap.

The Microcode writes a location in Local
Macrocode that it is ready to proceed.

Storage

informing the

The Macrocode will then set "Receive Flag” and "Addres
s Wrap”
in CSR2 and then sets "Maintenance mode” in CSR1. The
Diagnostic then informs the PAM that the function was
done.
The PAM Microcode will,
read and store

(in Local

when

"Scan Entry” sets

Storage)

in the MSR,

the contents of the

"Data

FIFO ", “Status FIFO” and the “MSR”. The Microcode then
informs the Macrocode that the function is done.
This test
will loop through all the line numbers.

The contents of the “Stetus FIFQ" and “Data FIFO” ;s depende
nt
on the “"Dash Bus” address the “Scanner” is referencing and

whether the

“Sync” bit

is set

“CSR2".

The Scanner reads Line Register “1“,
when it sees s Receive
Flag in Line Register “9”, and the address currently on the

Dash Bus ( Line Register 1

) will appear as the data of Line

CZLDIAO LUADABLE IMAGE

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MACRO M1200

25 APR 85 14:05

PAGE 33

Numbers, except those listed,
in the Status FIFO.

will cause an Error bit

to set

In "Asynchronous” mode bits 3 to S will cause
“Error" to set
in the “Status FIFO" . Two entries will be entered in
each
FIFO for the error condition as follows:

STATUS FIFQ
1. Error set
2. No error set

DATA FIFO
Line Reg. 1
(
Char. in Err.(

ADDRESS WRITTEN
ADDRESS WRITTEN

If the microcode is unable to flush the FIFQ's correctly,
which
indicates that Scanner Entry remains set, the microcode
will
set a Timeout flag in LS location 7776.
TEST 11

This test will force the scanner to record a Modem Change for
all line numbers. The test will start by forcing a Modem
Chenge for all lines, with a known data pattern ( zeros'
).
The Status and FIFO entries are ignored for the first
data

pattern used,

since

the

initial

values

in the modem change

is unknown. Subsequent patterns should yield the followi
ng:
MEC should set in the STATUS FIFO the DATA FIFO should have

ram

the EXCLUSIVE “OR” of the previous pattern and the
pattern
written. The pattern used ( after the pattern of
ZEROS ) is
incrementing from 1 to 20 (OCT.). This pattern
sequence will
verify the DEPTH of the Modem Change Ram (16
Decimal

locations).

If the microcode is unaeble to flush the FIFQ's
correctly, which
indicates thet Scanner Entry remains set, the microc
ode will
set a Timeout flag in LS location 7776.
TEST 12

This test will force the scanner to record a Modem
Change for
all line numbers. The test will start by forcing
a Modem
Chaenge for all lines with a known data pattern ( zeros'
). The
Status and FIFO entries are ignored for the first data pattern
used, since the initial values in the modem change ram
is
unknown. Subsequent patterns should yield the following:
MEC
should set in the STATUS FIFO the DATA FIFO should have the
EXCLUSIVE "OR" of the previous pattern and the pattern
written. Four data patterns
are used to verify the data
integrity of the ram, as follows:

1.
2.
3.

If the microcode

252
125
063

017

Alternate zeros and ones
Above shifted right
Adjacent bits set and cleared

Adjacent nibbles set and cleared

is unable to flush the FIFO's correctly,

)
)

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MACRO M1200

25 APR-85 14:05

PAGE 34

which indicates that Scanner Entry remains set,
will set a Timeout flag in LS location 7776.
TEST

the microcode

This test will force a Dash Bus parity error for
PAM Writes to
the Dash Bus. The Microroutine first flushes the FIFQ's
end
waits for the diagnostic to setup the function. The
diagnostic
will set Force PE, in CSR1, and informs the microc
ode that the
function was done. When the microcode writes the Dash
Bus
window, Line in error and Dash Bus Parity error bit, along
with the bad data, will load in the FIFOS. The conten
ts of the

Date and Stetus FIFOS

is stored

in loceal Storage.

The Microcode will then test two Condition codes
while the
Force PE is set. A read will indicate the parity error by
setting two microbranch condition codes: "Read Not Done or

Parity Error”and "Read Dash Bus Parity Error”. The state
of
the condition codes is saved in Local Storage for the
Read and
Write operations.

The transfer of data to and from Local Storage will
cause a
"Local Storage Parity error' when Force Parity error is
set.
Therefore, the existence of this error bit is expecte
d. It
should also be noted that the contents of the Status and
Data
FIFO's is invalid unless Scan Entry is set in the
MSR for each

entry

read.

TEST 14

This test will check that the Scanner can be disabled
by
setting Disable Scan in CSR2 (Bit 6) end starting a XMIT/RE
C
function in “Maintenance Mode”. The diagnostic
first does a
velid Scanner function to assure that known data will
appear
in the FIFO's. Scanner Disable is then set, the
FIFO's flushed
and a different type of Scanner function started.
There should
be no entries into any of the FIFO's form subsequent
transfers
and this will be verified by the diagnostic.

If the microcode is unable to flush the FIFO's correctly,
which indicates that Scanner Entry remains set, the
microcode
will set a Timeout flag in LS location 7776.
TEST

This test will check the Block Mover memory address register
bits O to 21. A pattern is passed to Local Storage for the
microcode to read and pass to the Block Mover address
register.

The microcode then starts a one word DATA-IN to

Local Storage with the Block Mover. When the block move stops.
the microcode will pass the contents of Last Memory nddress
register to Local Storage for verificetion by the program. The
following patterns are used as addresses:

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MACRO M1200

25-APR-85 14:05

IK3

PAGE 35

1.
2.
3.

05252525
12525252
14631463

TEST 16

The block mover is given an address of ALL ONES and s
block
move iS started. The “PAM“ should detect an “NXM" in the
Micro-Status register snd the block mover should
stop. The
microcode should be "Forced to Zero" when the "NXM"
condition

occurs and a check is made
occurred once only.

TEST

see

that

the

force

condition

This is a test of the Block Movers ability to do a DATA-IN
form system memory. A data pattern is first
written into
system memory for the Block Mover to transfer. The Microcod
e
fetches the memory address to write the data, number of
words
to transfer and Local Storage location to write, from the
Pseudo CSR locations. The Block mover should be able tc
read
the data from system memory ( BUFFER ) and write it to
contiguous Local Storage locations. The pattern used
is
incrementing from 1 to 40 (octal).

The microcode is "Forced to Zero" for the following
conditions:
"NXM” ( Non Existent Memory ), “MPE” ( Memory Parity
Errors).
R check is made to see that only one traverse through
micro-location zero is made (START) by the Microro
utine.
TEST 18
This is a test of the Block Movers ability to
do & DATA-OUT
system memory. A date pattern is first written into
Local

Storage for the Block Mover to transfer.
the memory address

to write

the data,

The Microcode fetches

number of words to

transfer and Local Storage location to read from the
Pseudo

CSR locations.

The Block mover should be able to read the data

called BUFFER.

The pattern used

from Local

(octal).
is

Storage and write

to a system memory

"Forced to Zero”
to see

that

for the following conditions:
traverse

to 40

The microcode

"MPE" ( Memory Parity Errors).

only one

location

incrementing from 1

The totel transfer should be 16 Words.

Existent Memory

made

"NXM"

(

A check

through micro-location

is made (START) by the Microroutine.
TEST

Non

zero

This is a test of the Block Mover Loceal Storage address
register. A date pattern is first written into Local Storage
for the Block Mover to READ. The Microcode fetches the memory

address to write

the data

the Pseudo CSR locations.

and number of words

to transfer

from

The Block mover should be sble to

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MACRO M1200

25-APR-85 14:05

PAGE 36

read

the

memory

data

L3
from Local

Storage

locaticn called BUFFER.

and write

system

The following Local Storage locations are used:
LS Address
5252
5253
2525
2526
1463
1464
3777
4000

LS Data
NON
S LN

CZLDIAO LOADABLE IMAGE

The microcode is “Forced to Zero* for the following
conditions:
“NXM" ( Non Existent Memory ), “MPE" (Memory Parity Errors).
A
check is made to see that only one traverse through
micro-location zero is made (START) by the Microro
utine.
TEST

This test will check the Block Movers ebility to
do a DATA_IN
followed by a DATA_OUT. The PAM microcode first resds
Locel

Storage to fetch Memory address,

Word transfer count and

starting function ( DATA_IN ). The microcode will then
stert,
wait for BM to finish end then write the data read
beck to
system memory. A check is made to see that STATUS,
MSR and

LAST MEMORY ADDRESS registers are correct.
memory is then checked for correctness.

The data

in system

The microcode is “Forced to Zero" for the follow
ing conditions:
“NXM" ( Non Existent Memory ), “MPETM (Memory Parity
Errors). A
check is made to see that only one traverse through
micro-location zero is made (START) by the Micror
outine.
TEST 21
This test will

force o Local Storege Parity error

When the Block

Mover

and see that

the Block Mover will stop when the parity error is detecte
d.
Force Perity error is set in CSR1 and & locstion in Locel
Storage is written ceusing that location to have bad parity.
is started and reads the Bad Parity

Location, it should stop the trensfer. LSPE and PE should set
in CSR1 but the microcode should not be Forced to Zero for

this error condition.

POERR

is set

in CSR1.

The

first pess through the disgnostic

This will sllow the block mover to

complete the trensfer of deta. The second pess will CLEAR
POERR end should halt the BLOCK MOVER and MICROCODE when
bad

parity

is read.

The microcode is “Forced to Zero” for the following conditions:
"NXM” ( Non Existent Memory ), “MPE" (Memory Parity Errors). A

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25-APR 85 14:05

PAGE 37

check is made to see that only one traverse through
micro-locetion zero 1s made (START) by the Microroutine.
TEST

This test will check

the Block

Movers sbility to

do e DATA_IN

followed by @ DATA_QUT while the previous Block Move
in progress.

The PAM microcode

first

resds Locel

is still

Storage

fetch Memory address. Word transfer count and function for
both trensfers. The microcode will start the DATA_IN then

immediostely start e Dete-out with both transfers
using the
seme Locel Storesge locetions. If the Block Mover hasn't
finished when another block move is sterted, a STALL of
the
microcode tekes plece until the first block move
has finished.
The Block Mover should be sble to complete both block
move

operations. A check is made to see that Status, MSR end Last
Memory address registers sre correct;: the deta in system
memory is then checked for correctness.

The microcode is "Forced to Zero" for the following conditi
ons:
"NXM" ( Non Existent Memory ), “MPE” (Memory Perity Errors). A

check

is made to see that only one traverse through

micro-location zero

is mede (START) by the Microroutine.

TEST 23

This test will check that the STEAL IBUS cycle operates
correctly from the Fest-bus (Unibus) end PAM sides of the
IBUS. A DATA_OUT block move is sterted by the Pem Microcode.

mover is opersting, the requesting operstion will Stesl on
I8US
cycle from the block mover. Both the block move end the
function thet did the

The microcode

stesl

should continue

to completion

—

without error.

—

While the block mover is operating, e series of reads
snd
writes sre done to Loceal Stor
from the Pam and Unibus at
the same time. Each time the IBUS is requested while the block

"Forced to Zero” for the following conditions:

"NXH* ( Non Existent Memory ), "MPE" (Memory Perity
Errors).
check is made to see that only one traverse through
micro-location zero is made (START) by the Microroutine.

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MACRO M1200

————r

CZLDIAO LOADABLE IMAGE

CZLOIAO LOADABLE IMAGE

MACRO M1200

2S-APR-85 14:05

PAGE

1873

3.0

GENERAL INFORMATION For CIDSCA end CIDSDA Line
Card Tests

1875
1876
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3.1

PROGRAM ABSTRACT

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1896

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1910
1911
1912
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1914
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1917
1918
1919
1920
1921
1922

1923

1924

The line cerd repair level diagnostic (1)
progrems is meant to
provide field service and menufacturing with a tool
to meinte;n

“digital ethernet communication server” digital menufactured
line cards. The program will provide the coverage necess
ery

detect o failure in @ line card function. The di
ostic is
usually cepsble of isolating a fault to s particular line
card.

Line card types covered are M3100 sync,
and the M3102 dusl

3.2

esync

M3101 high speed sync,

line card.

SYSTEM REQUIREMENTS

In order to run this diagnostic program,
minimum hardware is required:
-

the following

A PDP-11 CPU_
"“PROTOCOL PROCESSOR (PP)*
MINIMUM OF 256K WORDS OF SYSTEM MEMOPY

(PDP

11/24)

- CONSOLE BOOT TERMINATOR (CBT)
- RSX11-S “LDI* SOFTWARE OR XXDP+ SUPPORTED LOAD MEDIA
- AT LEAST ONE “PAM“ MODULE SET CONSISTING OF AN M3110
& M3111
- THE LINE CARD UNDER TEST
3.3

DIAGNOSTIC HIERARCHY PREREQUISITES

The gool of the

“PAM“" diagnostic progrem

menufactured line cerds.

is to test digital

assumed that

the

“self

test

diagnostic“ has run,end the “CBT",*SYSTEM MEMORY"” and
"PAM(S)"
are fully functional. A failure in the aforementioned
devices
could fail this diegnostic and the user should be awsre of
this possibility.

3.4

ASSUMPTIONS

- RESTRICTIONS

It is assumed thet the prerequisite diagnostics have been
executed (refer to section 3.3). The operator should
slso

be femilier with the operating
3.5

instructions

in section 3.5.

OPERATING INSTRUCTIONS

Refer to section 2.6 for a complete description of
the
operating instructions.
NOTE:

After meking one pass of the diagnostic the UNIT
cen be used to test & single unit or more.

flag

STA/PASS:1/FLA:HOE/UNIT:1

!test unit 1 only.

STA/PASS:1/FLA:HOE/UNIT:0-4

!tests units 0-4 only.

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1973
1974

MACRO M1200

2S-APR-85 14:05

PAGE 39

STA/PASS:31/FLA:HOE/UNIT:1:3:6
3.6

!tests units 1,3 and 6

HARDUWARE QUESTIONS

When a diagnostic is started, the runtime servic
es will prompt
the user for hardware information by typing "CHANG
E HW (L) ?°.

If you answer

“NO“" the program will

If you answer

"Y“ after a start command,

hard coded hardware P-tables.

will

ask

run with parameters

the runtime services

for the number of units (in decimal).
saknk

WARNING

=+2xa

{ THE NUMBER OF UNITS MUST ALWAYS BE 16.
The

in the

]

line card repair diagnostic will test up to 16
units.

However,

the diagnostic automatically checks to see

requested units

for

test

are

there

and drops

any

if the

not

responding. Also, the “CBT” is checked for s one or two "PAM*
system indicator and drops iine card unit associated with any
PAM not present or not responding. If the PAM
configuration
does not agree with valid PLUTO configurations or with
information in the CBT configuration register an
initialization error message is output. An initia
lization

error

message

also output

sizing line cards.

the program has difficulty

Initislization error messages are

by error numbers of the form INI XXXXXX.

indicated

The hardware P-tables exist to communicate operat
ional

paremeters for each unit to the diagnostic.

These parameters

consist of an “LOOPBACK" flag. Loopback indicates that
loopback connector(s) are permanently installed on all
the
line cards that sre selected and that external loopback
tests

may be run without operator intervention. The
DRS prompting
for P-table parameters includes a indication
of the default

value which may be used by responding with a <CR>.

All

remaining P-table questions for any unit may be
defaulted by

typing & single <CTRL 2>.

The operational parameters are:

LOOP-BACK MODE -

Indicates

if external loopback connectors

are permenently

installed on

selected line cerds.

all

the

The following P-table dialog alters the default by setting
loopback mode for units O and 1.

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2015
2016

2017
2018
2019
2020
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MACRO M1200

25 APR 85 14:05

PAGE 40

UNITS

(D)

16<CR>

UNIT O
INPUT MARGIN O CONDITION:
INPUT MARGIN 1 CONDITION:

INPUT

MARGIN 2 CONDITION:

(0) O ?<CR>
(0) 252 ?<CR>
(0)

252

?<CR>

INPUT MARGIN 3 CONDITION: (0) 152 ?7<CR>
INPUT MARGIN 4 CONDITION: (0) 125 ?<Ch>
TEST IN AUTO-LOOPBACK MODE ? (L) N ? <CR>
UNIT 1
INPUT MARGIN O CONDITION:
UNIT 2

UNIT 15

INPUT MARGIN O CONDITION:

3.7

(0) O

?<CTRL 2>

(0) O

?<CTRL

ERROR INFORMATION

There ere three levels of error messages that may
be issued by
a diagnostic: general, basic and extended.
General error

messages

are

always

(section 2.7).
NAME

printed

unless

the

“IER"

The general error message
TYPE

NUMBER

ERROR MESSAGE

flag

set

is of the form:

ON UNIT NUMBER

TST

NUMBER PC:XXXX

tn IFRE

NAME = DIAGNOSTIC NAME
TYPE = ERROR TYPE (SYS FATAL, DEV FATAL, HARD OR
SOFT)
NUMBER = ERROR NUMBER
UNIT NUMBER = O - N (N IS LAST UNIT IN PTABLE)
TST NUMBER = TEST AND SUBTEST WHERE ERROR OCCURR
ED
PC:XXXXXX = ADDRESS OF ERROR MESSAGE CALL

Besic error messeges are messages that contain some
additional
information about the error.
These are slways printed unless
the “IER" or "IBE” flags are set (section 2.7).
These messages
are printed after the associated general message.
Extended error messages contain supplementary error informa
tion

such as register contents or good/bad data.
These are always
printed unless the "IER”, “IBE" or “IXE" flags are
set

(section 2.7).

These messages are printed after the associated

genersl error message and any essociated basic error message
s.
This disgnostic does not use any extended error message
s.

Initislization error messages are of the format

NAME INI NUMBER MESSAGE
These are always printed and occur because of conriguratign.

errors

found

the diagnostic

initialization,

problems sizing

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2069
2070
2071
2072
2073
2074
2075
2076

MACRO M1200

25 APR 85 14:05

PAGE 41

line cards or operational parameters which should
not be used

with

this specific diagnostic.
diagnostic is aborted.

A werning
line cerd

3.8

After

the error

;s output,

the

is output when the diagnostic is run and no standa
rd
is found. The diagnostic is then aborted.

CONFIGURATION INFORMATION

The Pluto system configuration presumes that 1 or
2 PAMS are
attached to the PDP-11/24 protocol processor and that
each PAM
has 8 dash bus slots. The PAM UNIBUS addresses for
PAMO and
PAM1 are known. PAM sizing is done via accessing a PAMO
and
PAMl register. If a Timeout interrupt results then
it is
assumed that either the PAM is not present or
it is incapable

of responding.

The number of PAMS which should reside

in a

system is determined by reading the display/configuration
register in the console-boot-terminator module. If one
PAM
exists in a system it should be PAMO.
Line cards of any type(s) may be arbitrarily inserte
d into the
dash bus slots subject to system constraints. The
dash bus ;s
sized to determine what type of line cards, if any, are
attached to each dash bus slot.

Default hardware P-tables are set up to run diagnostics
on all
line cards in both PAMS. Automatic sizing determires the

appropriate line card tests to be run.
Empty
are skipped., i.e. no tests are run. User and
cards are not tested. If line card types are
tests can be run from this or companion line
& warning message will be displayed.

Errors or system configuration violations,

diagnostic initialization, will result
messages and will cause an abort.

dash bus slots
undefined line

such that no
card diagnostics,

if found by the

initialization error

The auto-loopback question is asked for each unit.
This
informs DRS that a loopback connector (2 connectors for
dusl line cards) is permanently installed on that unit.
All spplicable tests, including external loopback tests,
are executed.

If the auto-looback question wes answered NO and DRS is run
UNATTENDED MODE, no external loopback tests are run. If NOT
UNATTENDED MODE, the operator is prompted to install
a
loopback connector on the appropriate line card port/unit.

in
in

2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132

led and dash bus dual

addressing test.X

This test verifies that the led bit can be set via a
line card INIT or by writing a 1 to the led bit, and
that the bit can be cleared. this test also checks for

dash bus dual

addressing.

TEST 2
Line card generate bad parity check.
This test bit bangs the line parameter

of determining
at or

short

X XX

reg for the purpose

if the generate bad perity bit has sny stuck

type

faults.

TEST 3
Line card reg cleer on INIT test.
This test inits the line card and then checks
registers which should be cleared on INIT are
cleared.

TEST 4
Line card register
This test

initialization test.

inits the line card and then checks
cleared on INIT are

registers which should be

cleared.

TEST S
Line card 2661 register dual

addressing test.

if the 2661

in fact

if the 2652
in fact

This test

inits the line card and checks the 2661 registers
7) and generic registers (reg space 8 - 15)
for dual sddressing.

(reg space 0

TEST 6
Line card 2652 register dual
This test

addressing test,

inits the line card and checks the 2652 registers

(reg space 0 - 7) and generic registers (reg space 8 - 15)

for dusl

addressing.

—-AXm

—42Zr
VOOr:

VOOr:

RV, R0,0

Line card INIT,

WX
O

WI
OO
¢«

TEST 1

TEST SUMMARIES For CIDSCA Line Card Test #1
ORI

3.9

PAGE 42

COZ<ND

2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105

25-APR-85 14:05

=—unm-

2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089

MACRO M1200

CZLDIAO LOADABLE IMAGE

2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
gigg

2154
gigz

2157
glgg
1

2160
2161

2162

2163

2164
2165

2166

2167

2168
2169

2170

217

2172

2173

2174
2175

2176

2177

2178
2179
2180
2181
2182
2183

MACRO M1200

25 APR 85 14:05

PAGE 43

T
E
S
T

MMM
333
111
000
012
..

N
0

221E
66NYX
657171
1 2.
. .ttt
A
.00
S.00
Y.PP
N . .
c .

.
.
TEST 7
Line card 2661/2652 register interference test.
- - - - ..
(THIS TEST IS SKIPPED BECAUSE 2661 MODE WAS REMOVED FROM THE M3100.)
This test checks for interference between registers of the
2661 and 2652 protocol chips.

TEST 8

Line card 2661/2661

interference test.

XXX

-X

-X-

This test checks for interference between registers of the
the 2 2661 protocol chips on the line card.

TEST 9
Bit bang 2661 and generic registers.
This

test

addr

bit
15)

Also checks
par err,

bangs
and

the

scanner

line

2661

retry

card

generic

registers

mode

(reg

registers
addresses

registers

with

- X

(reg
0

7).

forced

TEST 10
Bit

bang

This

test

addr

TEST

line

card 2652

bit bangs
15)

and

the

and

generic

line

2652

card generic

registers

(reg

loopback

test.

registers
addresses

(reg
0

7).

Modem

external

This test bit bangs the modem

output
TEST

registers,

and

in register via the modem

external

loopback

connector.

2652 select and 2661 xmitter ready test.

This test verifies that 2661 and 2652 mode can be selected
if eapplicable. Functioning of 2661 xmit buff avail <TXBAV>,
xmitter empty <TXEMT> and xmitter ready <TXRDY> bits is
verified.

012
.
.

N
0

TEST 13
2652 xmitter ready test.

X X

This test checks the functioning of the 2652 transmitter
related bits <TXBAV>, <TXEN2> and <TSOM>. No data is
actually looped. Checks are made in both BOP and BCP modes.
TEST 14
2661 receiver check.

This test checks the functioning of the 2661 RCV data
avail
<RCVDAV> and RCVR enable <RXEN1> bits. The test is perform
ed
in async mode. Verifies operation of line par <SYNC
XMIT ERR>.
TEST 15
2652 receiver check.

X X

This test checks the functioning of the 2652 RCV
data
avail <RXDAV> and RCVR enable <RXEN2> bits.

TEST 16
2661 all character length data xfer test.
Loop datea pattern through 2661 (async mode)
and 8 bit characters at 19.2 kbaud.

for S5,

TEST 17
M3101 transmit buffer ram address sequence test.
Insure that trensmitter buffer ram address pointer is
being autoincremented, following each write to the ram
control byte, when ‘load ram’
is set in transmit buffer
control register.
TEST 18
M3101 transmit ram data test.
Verify that all transmit data,
are free of stuck bits,

and command byte

ram bytes

4204
VOO

000

VOO

333
111

MMM

E
S

U OV

G4
OO

PAGE 44

2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234

2S5-APR 85 14:05

2185
2186
2187
2188
2189
2190
2191
2192
2193

MACRO M1200

FOZ<B

CZLDIAO LOADABLE IMAGE

2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263

2264

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2276
2277
2278
2279
2280
2281
2282
2283
2284
2285

TEST 19
M3101 autoload of transmit control rsm test.

Verify that with ‘load rem' set in transmit buffer
control,
that a data byte written to the multi memory regist
er will
be placed into the data portion of the transmit ram, and
at
the same time, causes a default value to be placed into
the
same

ram

address,

then

autoincrements

the

ram

address

pointer,

TEST 20

M3101 low speed transmit ram data transfer test.

X -

This test, operating in the maintenance mode at 19.2 kbaud,
will verify operation of the transmit ram, in the buffere
d
mode at 19.2 kbaud
TEST 21

M3101 transmit buffer rem address overflow test.

Operating in the maintenance mode at 19.2 kbaud this
test
will verify that an overflow of the ram address buffer
will set '‘end of buffer’' and 'transmit buffer avail’.

TEST 22
M3101 buffered mode transmitter underrun test.

Operating in the maintenance mode at 19.2 kbaud this test
will verify that while a dota transmission from the
transmit
buffer rem is taking place, clearing 'send ram' will cause
a transmitter underrun.
TEST 23
M3101 high speed bop

internal loopback test.
(UTILIZES DIAGNOSTIC MICROCODE)

Operating in maintenance mode st 500 kbaud, internal
loopback, bop mode,with the line card in the buffered
mode, will verify that data cen be successfully
transferred.

X -

—4XM

—42Zm4

VOO

012

DAL

MMM
333
111
000

VOO

T
3
S
T

PAGE 35

25-APR-85 14:05

DZ<X<WND-

2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249

MACRO M1200

CZLDIAO LOADABLE IMAGE

2302
2303
2304
2305

2306
2307
2308
2309

2310
2311
2312
2313
2314
2315
2316
2317
2318
2319

SAME AS #24,

test.

EXCEPT IN EXTERNAL LOOPBACK

TEST 25
M3101 high speed BCP

internal

loopback

(UTILIZES DIAGNOSTIC MICROCODE)

test.

Operating in maintenance mode at S00 kbaud, internal
loopback, BCP mode, with line card in the buffered

mode, will verify
transferred.

that data cen be successfully

TEST 26
M3101 high speed,

parity error.

BOP mode,

force XMT BUFF RAM

(UTILIZES DIAGNOSTIC MICROCODE)

This test will verify that on detection of a transmit
buffer ram parity error, during a data transfer attempt,
‘transmitter error’

bit will

set.

«4xm
VOO
«

A2+

DN
s
s

VOO
:

OO
crOZ<WWP

WX
O
s

M3101 high speed bop external loopback
(UTILIZES DIAGNOSTIC MICROCODE)

TEST 24

PAGE 46

25 APR-85 14:05

—~-unMm-—

2287
2288
2289
2290
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2292
2293
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2295
2296
2297
2298
2299
2300
2301

MACRO M1200

CZLDIAO LOADABLE IMAGE

2340
2341

2342
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2354
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2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369

Loop and check data data pattern through 2661 (async mode)
via internal at all baud rates from 50mbaud to 19.2 kbaud.

Baud rate accuracy
TEST 2 2661

All

is not checked.

stop bit

length de _.a xfer test.

Loop data pattern via 2661 asy"c mode with 1, 1.5 and
2
stop bits. Check data and el.tive timing to verify that
the correct number of storn I..ts are being used.

TEST 3 2652 Sync generati
., test.

Check the ability of the 2652 to generate syn charac
ters
from the syn register and xmit holding register. Also

check the ability to strip the 1st 2 syn characters
and
the ability to discriminate against non-syn charact
ers.

TEST 4 2652 Trensmitter flag generation test.

X X

Check the ability of the 2661 (bop mode) to generate and
strip flags characters. transmit data where data = flag.
Data integrity verifies 0 stuffing.
TEST 5 2652 BOP mode 2ndary addr RSOM and REOM test.

Loop data in 2652 bop internal loopback mode with secondary
address recognition enabled. Dats integrity, RCVR errors
and the ability of REOM to set and clear is checked.
TEST 6 2652 BCP mode
Loop a date pattern

internal data wrap test.
in 2652

internsl

loopback

X X
mode and

verify the data integrity. Test is performed at 19.2 kbaud
and for 5 thru 8 bit character lengths.

«2Zwm

—«Axm

VOOr:

VOOr--+

¢+

=000V

OZ<I>D

iEST 1 All baud rates data xfer test.

WX
O

2335
2336
2337
2338
2339

TEST SUMMARIES For CIDSDA Line Card Test #2

2329
2330
2331
2332
2333
2334

3.9

PAGE 47

2325

2326
2327
2328

25-APR-85 14:05

=-vwMm—

2321
2322
2323
2324

MACRO M1200

CZLDIAO LOADABLE IMAGE

2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398

2399
2400

2401
2402
2403
2404
2405
2406
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2408
2409
24i0
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422

X X

Loop a data pattern in 2652 bop mode at 19.2 kbaud for 4
thru 8 bits/char, and at 4.8 kbaud for 2-3 bits/character
.

The data pattern exercises the 2652 bit stuffing feature.
TEST 8 2652 0/1/2 Starting syn test.

X X

Attempt to loop dete in 2652 internal loopback bop mode with
0. 1 and 2 starting syn characters. The receiver should
sync
up only with 2 leading syns.
TEST 9 2652 Mult start syns w/wo strip sync.

X X

Loop a data pattern with multiple starting end embedd
ed syns.
with strip syn disabled verify that 2 starting syns
are
stripped. With strip syn enabled, verify that all startin
g
syns

are

stripped.

TEST 10 2652 Multiple syn character test.

X X

Data patterrs are looped using different syn chareacters
to
find stuck bits or lines

in the syn related circuitry,

TEST 11 2652 Syn character discrimination test.

An attempt is made to loop dates using xmitted syn charact
ers
differing from syn characters in the low byte par reg by
1
bit. If the RCVR syncs up an error is indicated. Correct
syn
chars are elso xmitted to verify thet the RCVR can sync
up.
TEST

12 2652 Secondary address mode test.

X X

This test checks the ability of the 2652 2rdary address
mode bit to put the 2652 into 2ndary address mode.

TEST

13 Right/wrong secondary address test.

Attempt to loop data patterns 2ndary addresses which are
incorrect by 1 bit. No deta xfer should occur. Correct 2ndeary

addresses are

also used to verify

thst data xfers can occur.

—<4xm
¢

—~Zk
VOOM:

VOOr.

DUVON
s
«

X X -

OZ<WVP

WX
OO
r

TEST 7 2652 BOP mode data wrap/ bit stuff test.

POON

O WX

PAGE 48

—OMWI

25-APR 85 14:05

M-

2371
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2377
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2380
2381
2382
2383
2384
2385
2386
2387

MACRO M1200

CZLDIAO LOADABLE IMAGE

2443
2444
2445
2446

2447

448
2449
2450
2451
2452
2453
2454
2455
2456
2457

2458
2459
2460
2461
2462
2463
2464
2465
2456
24,7

2467
2466

24170
2471
2472

2473
2474
2475

2476

2477
2478

N
0

TEST

14 2652 All parties addressed ensbie test.

-“xXmM

000
0122
.
.
.

vVoor

—Zri

333
111

VOOIr:

MMM

E
S

NNV

PAGE 49

=O0N

£5-APR-85 14:05

2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442

MACRO M1200

COZ<ND

CZLDIAG LCADABLE IMAGE

X X

This test checks the ability of the 2652 to reject an all
parties message when not in the all parties addressed mode.
TEST

1S5 2652 All

parties

addressed detection

discrimination test.

With all parties addressed (espa) set, attempt to
loop dates
with 2ndery addresses differing from all parties address

(377) by 1 bit.

Deta should not be received.

The correct all

parties address (377) is slso used to verify that date cen
be received in this mode. A correct 2nd addr is sent
to
verify reception in apa mode.

TEST

16 2652 Abort detection/generation test.

While

looping data a check

X X

is made that setting TEOM sends

abort if idle = O and sends a flag if idle = 1. Abort
reception should cause RAB and REOM to set. A check is made
that these bits properiy clesr. Flag reception should
allow
receipt of the cherscter before the flag.

TEST

17 2652 Go-ahead gen/detect,sbort with go-shead
test.

X X

Check the functionslity of the 2652 ¥o-nheod generation and

detect features
TEST

2661

incl the

Async

forced break

Verify that the 2661
is functionel.

TEST 19

<RAB’/GA>,

<TEOM>

and <TGA> bits.

test.

commend register break bit

2661 Async mode perity error test (no error).

Verify 2661 async mode dete cen be looped with odd and even
parity checking enabled without a perity error occurring,
TEST

2661

Async mode odd/even perity gen/det

test.

Loop date with odd and even parity checking enabled. Parity
errors are forced and verified via the parity error bit.
With with parity disabled, the parity err bit should not set.

2493
2494
2495

2496

2497
2498
2499
2500
<2501
2502
250%
2504
23035
2506
2507
2508
2509
2510
2511
2512
2513
2514
eS15
2516
2517
2518

Generate an overrun while looping dats
ond verify that

the overrun bit sets.

in 2661

TEST 22

2661 Async mode freming error test.

Check

the sbility to detect a framing error.

errors

are

generated by

and RCV clock

reates.

looping

dats

Freming

different

xmit

TEST 23 2652 Error control modes test.

This test loops dets in each of the 2652 error
control modes.
Errors sre generated end error detection is verifie
d. A cneck
is also made to verify that error detection can be
dissbled.

TEST 24 2652 Underrun test.

The 2652 response to en underrun is checked in both
BOP end BCP mode with the IDLE bit both set end clear.
TEST 25 2652 Overrun test.

Generate sn overrun in both BOP and BCP mode. Verify thet
the RCVR status rce overrun bit is set, and that it cen
be clesred vis 8 R '{R status reg read, a reset error comman
d,
or by disabling the receiver.

-t
3 (M

«Zw
VOOr:.

voor..

=00N
OZ<D:
e

async mode

IOV

e Ore
X

F
»
&

WX
QOr
c
@

o
8

2661 Async overrun test.

iEST 21

S50

PAGE

} ]

14:05

2483
2484
2485
2486
2487
2488
2489
2490
2491
2492

25-APR-85

~uvmMmw

2480
2481
2482

MACRO M1200

O2Z

CZLOIAO LOADABLE IMAGE

CZLDIAO LOADABLE IMAGE

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MACRO M1200

25-APR-85 14:05

4.0 GENERAL
4.1

PAGE 51

INFORMATION For

CIDSEA

CBT

Test

PROGRAM ABSTRACT

This program

is e repsir

level diagnostic

(Console,.Boot, Terminator) module.
The CBT (M3112) is A
pinout that contains:

standard

Hex

for

module

the

wmith

M3112

cerv

Unibus

SPC

ROM Bootstrep supporting 8 ROM sockets (64kb totasl).

Off/0n/Lock/Standby key switch

Stert and Test pushbuttons

Four seven segment

(e.g.

leds

replace bad unit)

identify

Seriel Line Unit fixed at
console.

EIA console serial line connector,
the 11/24.

1200

bsud,

operstor

for

ection

virtual

for local control of

Unibus terminator for the end of the Unibus.

This disgnostic has been written for use with

the

dia

ostic

runtime
services
software (DR>).
These services provide
interface to the operator end to the software environ
ment,

the

4.2 SYSTEM REQUIRCMENTS

The Minimum system required

is:

11/24 Processor with

28Kw of Unibus memory

(BT (Console.Boot,Terminator) module

its SLUl set to 1200 baud

4.4 PREREQUISITES

The 11724 option diagnostic (CJDFA) or equivalent must be
to insure a working SLUL.
4.5 ASSUMPTIONS

The 5LU1

in the 11724 Processor must be functional.

run

CZLDIAO LOADABLE IMAGE

2570
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2591

MACRO M1200

2S5-APR-85 14:05
4.6

OPERATING INSTRUCTIONS

Refer

to section 2.6 for a complete description of
the
operating instructions.

The

following

is a sample CBT diagnostic run:

Start the Diagnostic under DRS
OR>

STA/FLA:PNT:HOE/PAS:1

CHANGE HW (L)
TST
TST
TST
TST
TST
TST
TST
TST
TST
TST
TST

2592
2593
2594
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2600
2601

2602
2603
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2605
2606
2607
2608
2609
2610
2611
2612
2613
26la
2615
2616
2617
2618
2619
2620

PAGE S2

001:
002:
003:
004:
005:
006:
007:
008:
009:
010:
011:

? N

READ/WRITE REGISTER TEST
PCR REGISTER TEST
MAINTENANCE REGISTER TFST
RECEIVER CSR REGISTER TEST
DLART INTERNAL LOOPBACK TEST (10 SECS)
CBT TO 11/24 SLU1 TEST (20 SECS)
UNIBUS REGISTER ADDRESS DECODE TEST
ROM CRC-16 CHECKWORD TEST
SEVEN SEGMENT DISPLAY REGISTER TEST
SINGLE LEDS DISPLAY TEST
CONFIGURATION REGISTER PRINTOUT TEST
CONFIGURATION REGISTER CONTENTS
BIT<8>=1
JUMPER W4 IS NOT INSTALLED
BIT<7>=1
JUMPER W1 IS NOT INSTALLED

BIT<6>=1

JUMPER W2 IS NOT INSTALLED

BIT<S>=1
JUMPER W3 IS NOT INSTALLED
BIT<4>=1
BATTERY BACKUP IS NOT PRESENT
BIT<3>=0
MARGINING BOX IS NOT PRESENT
BIT<2>=0
UNUSED
BIT<1>=1
TEST PUSHBUTTON IS OFF
BIT<0>=1
ONE PAM SET IS PRESENT
TST 012: ROM CONFIGURATION PRINTOUT TEST
ROM O
- PART NUMBER IN ROM = 23-abcde-fg
SLOT NUMBER IN ROM = 0O
SIZE IN ROM
= 1KB
CRC CALCULATED
000000

(

THIS IS REPEATED FOR ALL EIGHT ROMS

)

DR>
Tests 11

and 12 will be skiped when the UAM flag
Exemple:

4.7

HARDWARE QUESTIONS

When

a diagnostic

DR>

is started,

is set.

START/FLA:PNT:UAM

the

runtime

services will

prompt

CZLDIAO LOADABLE IMAGE
2622
2623

MACRO M1200

2S5-APR 85 14:05

the user

2624
2625

2626
2627
2628
2629
2630
2631
2632
2633 .

2634
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2641
2642
2643
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2645
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2648
2649
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2654
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2656
2657
2658
2659
2660
2661
2662
2663
2664
2663
2666
2667
2668
2669

PAGE S3

for

hardware

CHANGE HW (L)
You must enter

has

been

manual

information by printing:

Y after

prelosded

for more

a STArt command,

via

the

setup

unless the

utility.

information on the setup utility,

The DRS will then ask for the number of units
this diagnostic always answer 1.
For Example:

CHANGE HW (L)

# UNITS
4.8

SOFTWARE

the

XXDP.

test.

For

? Y

(D)

QUESTIONS

This diagnostic does NOT
4.9

information

See

ask

any software questions.

ERROR MESSAGE FORMATS

The error messages are

in the following format:

M3112 HRD ERR 00514 ON UNIT 00 TST 005 SUB 007
PC:12762

CBT Data error

EXPD:

000005

in loopback mode

RECV:

0C0004

XOR:

000001

Where:

1.
2.

"M3112"

is the CBT module name

"HRD ERR”

All

CBT

indicates

errors

(FTL ERR) errors.
3.

*00514"

test
4.

are

is the test and error number.

"ON UNIT

00"

"TST 005 SUB

is Fixed.

007"

The

"PC:12762"

may

CBT

indicates

executing at error call.

(hard)

consists

test

executing at

fatal

only

subtest

is the virtual pc at the error.

actuslly be

error,
or

This example

S error number 14.

unit per processor.

non-recoverable

considered hard errors,

one

was

The program

a different physical

is running under a monitor other than XXDP..

CZLDIAO LOADABLE IMAGE

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2698
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717
2718
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MACRO M1200

25-APR-85 14:05

PAGE 54

“EXPD:"

is the expected data.

"RECV:”

is the

"XOR:
" is the bits that
EXPD and RECV date.

4.10 TEST SUMMARIES
TEST

received data.

are

different

between

the

for CIDSEA

READ/WRITE REGISTER TEST

This test verifies the READ/WRITE register
is
addressable
from the 11/24 and has no bits shorted together or
stuck at
a high or low level.

TEST 2:

PAGE CONTROL REGISTER (PCR) TEST

This test verifies the PCR is addressable
and
has no bits shorted together or stuck

level.

TEST 3:

from
the
11/24
at a high or low

MAINTENANCE REGISTER TEST

This test verifies the MAINTENANCE register is
addressable
from the 11/24 and has no bits shorted together
or stuck at
e high or low level.

TEST 4:

CBT RECEIVER CSR REGISTER TEST

This test verifies
the
DLART
RECEIVER
CSR
register
s
addressable from the 11/24 and has no bits shorted togethe
r
or stuck at a high or low level.

TEST 5:

(BT DLART INTERNAL LOOPBACK TEST

This test verifies that date can be transmitted to
the
(BT
serial
line
unit
(DLART) and received in loop back mode.
In addition the DLART status bits are checked.
TEST 6:

CBT TO 11/24 SLU1 TEST

This test verifies data can be transmitted between the
ceT
serial
line
unit
(DLART)
and
the 11/24 serial line unit
(sLu1).
TEST 7:

UNIBUS REGISTER ADDRESS DECODE TEST

This test verifies that the
CBT
register
address
decode
logic
is
functioning correctly so that each register will
only respond to their valid Unibus addresses.

CZLOIAO LOADABLE IMAGE

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MACRO M1200

25 APR-85 14:05

PAGE 55

TEST 8:

ROM CRC-16 CHECKWORD TEST

This test verifies each ROM CRC-16 CHECKWORD
(checksum)

correct.

The test first searches all eight ROM slots
for
roms.
A
slot is assumed empty if -1 is read back from the first and
last locations.
Each ROM is read and a CRC-16 CHECKWORD is calculated.
It
is verified the result of the CRC calculation including
the
CHECKWORD blasted into the ROM is zero.

TEST 9:

SEVEN SEGMENT LEDS DISPLAY TEST

This test will verify the display
register
will
cause
a
Unibus
Timeout
if
written
into with a byte instruction.
The Seven segment led display is also tested.

Here is how the digits are
display test:

formed

Each segment and decimal points are lit

sequence.

TEST 10:

the

seven

segment

individually

SINGLE LEDS DISPLAY TEST

This test will light the single leds in a
fixed
sequence.
The
CBT
contains Four single leds (with room reserved for
two more) arranged in a row.
They will be used to indicate

status

such

as cable

other leds located

faults or

The test will light the leds
1.

All Leds

No Leds

Light each Led

Turn off each led

This

line

faults.

There

in the TEST and START switches.

are

two

in the following sequences:

in turn from left to right
in turn

from left to right

is not a Manual Intervention test but will

operator to determine

if the display

is correct.

require

CZLDIAO LOADABLE IMAGE

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MACRO M1200

25-APR-85 14:05

TEST

PAGE S6

11:

This

CONFIGURATION PRINTOUT

TEST

is a Manual Intervention test

the Configuration Register.

is & Read-only

present,

TEST 12:

such

hardware

to printout the contents

The Configuration Register

indicates

jumpers

the

which
CBT

options

are

module.

ROM CONFIGURATION PRINTOUT TEST

This
is
&
Manual
Intervention
test
to
printout
the
configuration
of
the Roms currently installed in the CBT.
The test sizes automatically for the
roms
and
calculates
the CRC-16 on each ROM.

The calculeted CRC-16 is always
required
to
be
zero,
since it includes the CHECKWORD blasted into the
ROM.

CZLDIAO LOADABLE IMAGE

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MACRO M1200

25-APR-85 14:05

5.0

PAGE S7

GENERAL INFORMATION for SYSEXE

The system exerciser (SYSEXE) is a RSX11-S task which
is part
of the DECSA Loadable Diagnost.c Image (LDI). Its purpos
e is
to create

much

units as possible.

activity between

This

the

PDP-11/24

and PAM/LINE

is accomplished by transmitting and

receiving 576 byte data messages on all

available

lines.

the majoricty

line

These

lines may be M3100/M3101 SYNC or M3102 ASYNC end the DEUNA.

mixed line cards are
will be exercised.

Activity

sized by SYSEXE,

is built up gradually by phases.

PHASE O

START PAM O AND LOOP DATA MESSAGES ON EACH LINE
PRESENT
.

PHASE 1

START PAM 1 WHILE KEEPING PAM O GOING.
MESSAGES ON EACH LINE PRESENT,

PHASE 2

KEEPING BOTH PAMS GOING START
MESSAGES.

5.1

type

LOOP DATA

THE UNA LOOPING DATA

OPERATING INSTRUCTIONS

To execute SYSEXE at the PLU> prompt type “RUN
SYSEXE” it will
then prompt you for number of passes and if you want to
run
with loopbacks connected.

5.2

LINE AND SLOT IDENTIFICATION UNDER SYSEXE
LINE

LINE

slgt >o 8 )

slgt} 1 9 )

10)

})3

)

14)

8)7

)

15)

}

)

101

)

123

)

> 7

)

CZLDIAO LOADABLE IMAGE

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MACRQ M1200

25 APR-85 14:05

6.0

UPDATING CSVLDI.SYS

(LDI 8LO6)

These instruction are intentionally general due to
the large
number of possible load device names on VMS and RSX1ime
systems. See the system manager for the specif
ic device name

of RLO2 or magtape on the target system.
recommended

that

you

verify

the

location

is also

the

disk:(targetuicl(this area was created when the operational
DECSA software package was installed) for the LDI with the
system manager.

The distribution media

CZLDIA.
VMS

After copying,

in Filesll

format.

verify CSVLDI.sys size

installation do:
For RLO2 do:

$ mount rl02:czldia
$ copy/contiguous
$_From: rl02:[1dilcsvldi.sys
$_To: sysésystem:csvldi.sys

2857

2858
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PAGE 58

End RLOZ2.
For

Tape do:

$ mount tape:czldia
$ copy/contiguous
$_From: tape:csvldi.sys
$_To: sysésystem:csvldi.sys
End VMS
RSX11im«

End Tape.
installation.
installation do:
For RLO2 do (DCL assumed):

mount rl02:czldia

copy/contiguous

From?

rl02:(1ldilcsvldi.sys

To? disk:(targetuiclcsvldi.sys
End RLOZ2.
For Tape do (DCL assumed):
> mount tepe:czldia
> copy/contiguous
From? tape:csvldi.sys

To? disk:(targetuicgcsvldi.sys

End Tape.
End RSX11.

Label name

is 1002 blocks.

CZLDIAO LOADABLE IMAGE

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25 APR 85 14:05

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2900
2901
2902
2903

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PAGE 59

7.0

KNOWN PROBLEMS WITH LDI BLO6

This

is the current list of problems with LDI BLO6.

assumed

in BLO7.

that

these

are

software

should be

is
fixed

SYSEXE errors when started the second time from PLU >,
The LDI must be reloaded.

Control C not handled by PLUMON.

.END

and

Refer to sections 2.7
problem.

000001

problems

M3101
while

and 2.8

in slot 1 causing M3100s
running SYSEXE.
«

"NOTES"”

for help on this

in other slots to error

CZLDIAO LOADABLE IMAGE
SYMBOL TABLE

ABS.

000000
000000
ERRORS DETECTED:
VIRTUAL

MACRO M1200

25-APR-85 14:05

PAGE 60

000
001

MEMORY USED:

19 WORDS

DYNAMIC MEMORY:
20324 WORDS
ELAPSED TIME:
00:01:16

(

1 PAGES)

78 PAGES)

+CZLDIA.SEQ/-SP=CZLDIA.MEM