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Document:	AlphaServer 1200 DIGITAL Ultimate Workstation 533 Service Manual
Order Number:	EK-AS120-SV
Revision:	A01
Pages:	266
Original Filename:

OCR Text

AlphaServer 1200
DIGITAL Ultimate Workstation 533
Service Manual

Order Number:

EK–AS120–SV. A01

This manual is for anyone who services these systems. It includes
troubleshooting information, configuration rules, and instructions for
removal and replacement of field-replaceable units.

Digital Equipment Corporation
Maynard, Massachusetts

First Printing, January 1998
Digital Equipment Corporation makes no representations that the use of its products in the
manner described in this publication will not infringe on existing or future patent rights, nor do
the descriptions contained in this publication imply the granting of licenses to make, use, or sell
equipment or software in accordance with the description.
The information in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation.
Digital Equipment Corporation assumes no responsibility for any errors that may appear in this
document.
The software, if any, described in this document is furnished under a license and may be used or
copied only in accordance with the terms of such license. No responsibility is assumed for the
use or reliability of software or equipment that is not supplied by Digital Equipment
Corporation or its affiliated companies.
Copyright  1998 by Digital Equipment Corporation. All rights reserved.
The following are trademarks of Digital Equipment Corporation: AlphaServer, OpenVMS,
StorageWorks, VAX, and the DIGITAL logo.
The following are third-party trademarks: Lifestyle 28.8 DATA/FAX Modem is a trademark of
Motorola, Inc. UNIX is a registered trademark in the U.S. and other countries, licensed
exclusively through X/Open Company Ltd. U.S. Robotics and Sportster are registered
trademarks of U.S. Robotics. Windows NT is a trademark of Microsoft, Inc. All other
trademarks and registered trademarks are the property of their respective holders.
FCC Notice: The equipment described in this manual generates, uses, and may emit radio
frequency energy. The equipment has been type tested and found to comply with the limits for a
Class A digital device pursuant to Part 15 of FCC Rules, which are designed to provide
reasonable protection against such radio frequency interference. Operation of this equipment in
a residential area may cause interference, in which case the user at his own expense will be
required to take whatever measures are required to correct the interference.
Shielded Cables: If shielded cables have been supplied or specified, they must be used on the
system in order to maintain international regulatory compliance.
Warning! This is a Class A product. In a domestic environment this product may cause radio
interference, in which case the user may be required to take adequate measures.
Achtung! Dieses ist ein Gerät der Funkstörgrenzwertklasse A. In Wohnbereichen können bei
Betrieb dieses Gerätes Rundfunkstörungen auftreten, in welchen Fällen der Benutzer für
entsprechende Gegenmaßnahmen verantwortlich ist.
Avertissement! Cet appareil est un appareil de Classe A. Dans un environnement résidentiel,
cet appareil peut provoquer des brouillages radioélectriques. Dans ce cas, il peut être demandé à
l'utilisateur de prendre les mesures appropriées.

Contents
Preface ...................................................................................... xi
Chapter 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.8.1
1.8.2
1.8.3
1.8.4
1.8.5
1.9
1.10
1.11
1.12
1.13

System Enclosure ..................................................................................... 1-2
Operator Control Panel and Drives ........................................................... 1-4
System Consoles ...................................................................................... 1-6
System Architecture ................................................................................. 1-8
CPU Types............................................................................................. 1-10
Memory ................................................................................................. 1-12
Memory Addressing............................................................................... 1-14
System Motherboard .............................................................................. 1-16
System Bus (Backplane).................................................................. 1-18
System Bus to PCI Bus Bridge......................................................... 1-20
PCI I/O Subsystem .......................................................................... 1-22
Remote Control Logic ..................................................................... 1-24
Power Control Logic ....................................................................... 1-26
Power Circuit and Cover Interlock.......................................................... 1-28
Power Supply......................................................................................... 1-30
Power Up/Down Sequence ..................................................................... 1-32
2
Maintenance Bus (I C Bus)..................................................................... 1-34
StorageWorks......................................................................................... 1-36

Chapter 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10

Overview

Power-Up

Control Panel ........................................................................................... 2-2
Power-Up Sequence ................................................................................. 2-4
SROM Power-Up Test Flow..................................................................... 2-8
SROM Errors Reported .......................................................................... 2-11
XSROM Power-Up Test Flow ................................................................ 2-12
XSROM Errors Reported ....................................................................... 2-15
Console Power-Up Tests ........................................................................ 2-16
Console Device Determination ............................................................... 2-18
Console Power-Up Display..................................................................... 2-20
Fail-Safe Loader..................................................................................... 2-24

iii

Chapter 3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.6

Troubleshooting with LEDs...................................................................... 3-2
Troubleshooting Power Problems ............................................................. 3-4
Running Diagnostics — Test Command ................................................... 3-6
Releasing Secure Mode ............................................................................ 3-7
Testing an Entire System .......................................................................... 3-8
Testing Memory .............................................................................. 3-10
Testing PCI ..................................................................................... 3-12
Other Useful Console Commands ........................................................... 3-14

Chapter 4
4.1
4.1.1
4.1.2
4.1.3
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.4.10
4.4.11
4.5
4.5.1
4.5.2

Troubleshooting

Error Logs

Using Error Logs...................................................................................... 4-2
Hard Errors ....................................................................................... 4-4
Soft Errors......................................................................................... 4-4
Error Log Events ............................................................................... 4-5
Using DECevent ...................................................................................... 4-6
Translating Event Files ...................................................................... 4-7
Filtering Events ................................................................................. 4-8
Selecting Alternative Reports........................................................... 4-10
Error Log Examples and Analysis........................................................... 4-11
MCHK 670 CPU-Detected Failure................................................... 4-11
MCHK 670 CPU and IOD-Detected Failure..................................... 4-16
MCHK 670 Read Dirty CPU-Detected Failure ................................. 4-21
MCHK 660 IOD-Detected Failure (System Bus Error)..................... 4-27
MCHK 660 IOD-Detected Failure (PCI Error) ................................. 4-32
MCHK 630 Correctable CPU Error.................................................. 4-41
MCHK 620 Correctable Error.......................................................... 4-44
Troubleshooting IOD-Detected Errors .................................................... 4-47
System Bus ECC Error .................................................................... 4-48
System Bus Nonexistent Address Error............................................ 4-49
System Bus Address Parity Error ..................................................... 4-50
PIO Buffer Overflow Error (PIO_OVFL)......................................... 4-51
Page Table Entry Invalid Error ........................................................ 4-52
PCI Master Abort ............................................................................ 4-52
PCI System Error ............................................................................ 4-52
PCI Parity Error............................................................................... 4-52
Broken Memory .............................................................................. 4-53
Command Codes ............................................................................. 4-55
Node IDs......................................................................................... 4-56
Double Error Halts and Machine Checks While in PAL Mode ................ 4-57
PALcode Overview ......................................................................... 4-57
Double Error Halt............................................................................ 4-58
iv

4.5.3

Machine Checks While in PAL........................................................ 4-58

Chapter 5
5.1
5.2
5.3
5.4
5.5
5.6

External Interface Status Register - EL_STAT .......................................... 5-2
External Interface Address Register - EI_ADDR ....................................... 5-6
MC Error Information Register 0 (MC_ERR0 - Offset = 800) .................. 5-8
MC Error Information Register 1 (MC_ERR1 - Offset = 840) .................. 5-9
CAP Error Register (CAP_ERR - Offset = 880) ..................................... 5-11
PCI Error Status Register 1 (PCI_ERR1 - Offset = 1040) ........................ 5-14

Chapter 6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19

Removal and Replacement

System Safety .......................................................................................... 6-1
FRU List .................................................................................................. 6-2
System Exposure...................................................................................... 6-6
CPU Removal and Replacement ............................................................... 6-8
CPU Fan Removal and Replacement ...................................................... 6-10
Memory Riser Card Removal and Replacement ...................................... 6-12
DIMM Removal and Replacement.......................................................... 6-14
System Motherboard Removal and Replacement..................................... 6-16
PCI/EISA Option Removal and Replacement.......................................... 6-18
Power Supply Removal and Replacement ............................................... 6-20
Power Harness Removal and Replacement.............................................. 6-22
System Fan Removal and Replacement................................................... 6-24
Cover Interlock Removal and Replacement............................................. 6-26
Operator Control Panel Removal and Replacement ................................. 6-28
CD-ROM Removal and Replacement ..................................................... 6-30
Floppy Removal and Replacement.......................................................... 6-32
SCSI Disk Removal and Replacement .................................................... 6-34
StorageWorks Backplane Removal and Replacement.............................. 6-36
StorageWorks Ultra SCSI Bus Extender Removal and Replacement........ 6-38

Appendix A
A.1
A.2
A.3
A.4
A.5
A.5.1
A.5.2
A.5.3
A.5.4
A.5.5

Error Registers

Running Utilities

Running Utilities from a Graphics Monitor .............................................. A-2
Running Utilities from a Serial Terminal ................................................. A-3
Running ECU.......................................................................................... A-4
Running RAID Standalone Configuration Utility ..................................... A-5
Updating Firmware with LFU.................................................................. A-6
Updating Firmware from the CD-ROM ................................................... A-8
Updating Firmware from the Floppy Disk — Creating the Diskettes ...... A-12
Updating Firmware from the Floppy Disk — Performing the Update ..... A-14
Updating Firmware from a Network Device........................................... A-18
LFU Commands................................................................................... A-22
v

A.6
A.7

Updating Firmware from AlphaBIOS .................................................... A-25
Upgrading AlphaBIOS .......................................................................... A-26

Appendix B
B.1
B.2
B.3
B.1
B.1.1
B.2

Halt Button Functions.............................................................................. B-2
Using the Halt Button ............................................................................. B-3
Halt Assertion ........................................................................................ B-4
Summary of SRM Console Commands ................................................... B-6
Summary of SRM Environment Variables ............................................... B-8
Recording Environment Variables ......................................................... B-10

Appendix C
C.1
C.2
C.2.1
C.2.2
C.2.3
C.3
C.4
C.5
C.6
C.7

Halts, Console Commands,
and Environment Variables

Running Utilities

RCM Overview....................................................................................... C-2
First-Time Setup ..................................................................................... C-3
Configuring the Modem .......................................................................... C-4
Dialing In and Invoking RCM ................................................................. C-5
Using RCM Locally ................................................................................ C-6
RCM Commands..................................................................................... C-7
Dial-Out Alerts...................................................................................... C-16
Using the RCM Switchpack................................................................... C-19
Troubleshooting Guide ......................................................................... C-23
Modem Dialog Details .......................................................................... C-26

Index
Examples
2–1
2–2
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
4–1
4–2
4–3
4–4
4–5

SROM Errors Reported at Power-Up ...................................................... 2-11
XSROM Errors Reported at Power-Up ................................................... 2-15
Test Command Syntax ............................................................................. 3-6
Releasing/Reestablishing Secure Mode..................................................... 3-7
Sample Test Command............................................................................. 3-8
Sample Test Memory Command............................................................. 3-10
Sample Test Command for PCI .............................................................. 3-12
Show Power........................................................................................... 3-14
Show Memory........................................................................................ 3-14
Show FRU ............................................................................................. 3-15
MCHK 670 ............................................................................................ 4-12
MCHK 670 CPU and IOD-Detected Failure ........................................... 4-17
MCHK 670 Read Dirty Failure............................................................... 4-22
MCHK 660 IOD-Detected Failure (System Bus Error)............................ 4-28
MCHK 660 IOD-Detected Failure (PCI Error)........................................ 4-33
vi

4–6
4–7
4–8
4–9
4–10
A–1
A–2
A–3
A–4
A–5
A–6
A–7
C–1
C–2
C–3
C–4

MCHK 630 Correctable CPU Error ........................................................ 4-42
MCHK 620 Correctable Error................................................................. 4-45
INFO 3 Command.................................................................................. 4-59
INFO 5 Command.................................................................................. 4-61
INFO 8 Command.................................................................................. 4-63
Starting LFU from the SRM Console ....................................................... A-5
Booting LFU from the CD-ROM............................................................. A-6
Updating Firmware from the Internal CD-ROM....................................... A-7
Creating Update Diskettes on an OpenVMS System............................... A-12
Updating Firmware from the Internal Floppy Disk ................................. A-13
Selecting AS1200FW to Update Firmware from the Internal Floppy ..... A-16
Updating Firmware from a Network Device........................................... A-17
Sample Remote Dial-In Dialog ................................................................ C-5
Invoking and Leaving RCM Locally........................................................ C-6
Configuring the Modem for Dial-Out Alerts .......................................... C-16
Typical RCM Dial-Out Command ......................................................... C-17

Figures
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-18
2-1
2-2
2-3
2-4
2-5
2-6
2-7

System Enclosure ..................................................................................... 1-2
Cover Interlock Circuit............................................................................. 1-3
Control Panel Assembly ........................................................................... 1-4
Architecture Diagram ............................................................................... 1-8
CPU Module Placement ......................................................................... 1-10
Memory Placement ................................................................................ 1-12
How Memory Addressing Is Calculated.................................................. 1-14
System Motherboard .............................................................................. 1-16
System Bus Block Diagram .................................................................... 1-18
System Bus to PCI Bus Bridge Block Diagram ....................................... 1-20
PCI Block Diagram ................................................................................ 1-22
Remote Control Logic ............................................................................ 1-24
Power Control Logic .............................................................................. 1-26
Power Circuit Diagram........................................................................... 1-28
Back of Power Supply and Location ....................................................... 1-30
Power Up/Down Sequence Flowchart..................................................... 1-32
2
I C Bus Block Diagram .......................................................................... 1-34
StorageWorks Drive Location................................................................. 1-36
Control Panel and LCD Display................................................................ 2-2
Power-Up Flow........................................................................................ 2-4
Contents of FEPROMs ............................................................................. 2-5
Console Code Critical Path (1200 Block Diagram).................................... 2-6
SROM Power-Up Test Flow..................................................................... 2-8
XSROM Power-Up Flowchart ................................................................ 2-12
Console Device Determination Flowchart ............................................... 2-18
vii

3-1
4-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
A-1
A-2
A-3
A-1
C-1
C-2
C-3

System Motherboard LEDs....................................................................... 3-2
Error Detector Placement ......................................................................... 4-2
System FRU Locations............................................................................. 6-2
Exposing the System ................................................................................ 6-6
Removing CPU Module ........................................................................... 6-8
Removing CPU Fan ............................................................................... 6-10
Removing Memory Riser Card ............................................................... 6-12
Removing A DIMM from a Memory Riser Card..................................... 6-14
Removing System Motherboard.............................................................. 6-16
Removing PCI/EISA Option................................................................... 6-18
Removing Power Supply ........................................................................ 6-20
Removing Power Harness....................................................................... 6-22
Removing System Fan............................................................................ 6-24
Removing Cover Interlocks .................................................................... 6-26
Removing OCP ...................................................................................... 6-28
Removing CD_ROM.............................................................................. 6-30
Removing Floppy................................................................................... 6-32
Removing StorageWorks Disk................................................................ 6-34
Removing StorageWorks Backplane....................................................... 6-36
Removing StorageWorks Ultra SCSI Bus Extender................................. 6-38
Running a Utility from a Graphics Monitor.............................................. A-2
Starting LFU from the AlphaBIOS Console ............................................. A-6
AlphaBIOS Setup Screen ...................................................................... A-25
System Partition Not Defined ................................................................ A-29
RCM Connections................................................................................... C-3
Location of RCM Switchpack on System Board..................................... C-19
RCM Switches (Factory Settings) .......................................................... C-20

Tables
1-1
2-1
2-2
2-3
2-4
2-5
2-6
4-1
4-2
4-3
4-4
4-5
4-6
4-7

PCI Motherboard Slot Numbering .......................................................... 1-23
Control Panel Display............................................................................... 2-3
SROM Tests........................................................................................... 2-10
XSROM Tests........................................................................................ 2-13
Memory Tests ........................................................................................ 2-14
IOD Tests............................................................................................... 2-16
PCI Motherboard Tests........................................................................... 2-17
Types of Error Log Events........................................................................ 4-5
DECevent Report Formats...................................................................... 4-10
CAP Error Register Data Pattern............................................................. 4-47
System Bus ECC Error Data Pattern ....................................................... 4-48
System Bus Nonexistent Address Error Troubleshooting......................... 4-49
Address Parity Error Troubleshooting..................................................... 4-50
Cause of PIO_OVFL Error ..................................................................... 4-51
viii

4-8
4-9
4-10
5-1
5-2
5-3
5-4
5-5
5-6
6-1
A-1
A-2
A-3
B-1
B-2
B-3
C-1
C-2
C-3
C-4

ECC Syndrome Bits Table...................................................................... 4-54
Decoding Commands ............................................................................. 4-55
Node IDs................................................................................................ 4-56
External Interface Status Register ............................................................. 5-4
Loading and Locking Rules for External Interface Registers ..................... 5-7
MC Error Information Register 0.............................................................. 5-8
MC Error Information Register 1............................................................ 5-10
CAP Error Register ................................................................................ 5-12
PCI Error Status Register 1..................................................................... 5-14
Field-Replaceable Unit Part Numbers ....................................................... 6-3
AlphaBIOS Option Key Mapping............................................................ A-3
File Locations for Creating Update Diskettes on a PC ............................ A-12
LFU Command Summary...................................................................... A-22
Results of Pushing the Halt Button .......................................................... B-2
Summary of SRM Console Commands.................................................... B-6
Environment Variable Summary.............................................................. B-8
RCM Command Summary ...................................................................... C-7
RCM Status Command Fields................................................................ C-15
Elements of the Dial-Out String............................................................. C-18
RCM Troubleshooting........................................................................... C-23

Preface

Intended Audience
This manual is written for the customer service engineer.

Document Structure
This manual uses a structured documentation design. Topics are organized into small
sections for efficient online and printed reference. Each topic begins with an abstract,
followed by an illustration or example, and ends with descriptive text.
This manual has six chapters and three appendixes, as follows:
•

Chapter 1, System Overview, introduces the DIGITAL AlphaServer 1200 and
the DIGITAL Ultimate Workstation 533 systems. It describes each system
component.

•

Chapter 2, Power-Up, provides information on how to interpret the power-up
display on the operator control panel, the console screen, and system LEDs. It
also describes how hardware diagnostics execute when the system is initialized.

•

Chapter 3, Troubleshooting, describes troubleshooting during power-up and
booting, as well as the test command.

•

Chapter 4, Error Logs, explains how to interpret error logs and how to use
DECevent.

•

Chapter 5, Error Registers, describes the error registers used to hold error
information.

•

Chapter 6, Removal and Replacement, describes removal and replacement
procedures for field-replaceable units (FRUs).

•

Appendix A, Running Utilities, explains how to run utilities such as the EISA
Configuration Utility and RAID Standalone Configuration Utility.

•

Appendix B, Halts, Console Commands, and Environment Variables,
summarizes the commands used to examine and alter the system configuration.

•

Appendix C, Operating the System Remotely, describes how to use the Remote
Console Manager (RCM) to monitor and control the system remotely.

Documentation Titles
Table 1 lists books in the documentation set for both systems.

Table 1 System Documentation
Title

Order Number

User and Installation Documentation Kit

QZ–011AA–GW

AlphaServer 1200 User’s Guide

EK–AS120–UG

AlphaServer 1200 Basic Installation

EK–AS120–IG

User and Installation Documentation Kit

QZ–013AA–GW

DIGITAL Ultimate Workstation 533 User’s Guide

EK–UW120–UG

DIGITAL Ultimate Workstation 533 Basic Installation

EK–UW120–IG

Service Information
AlphaServer 1200 /DIGITAL Ultimate Workstation
533 Service Manual

EK–AS120–SV

Information on the Internet
Using a Web browser you can access the AlphaServer InfoCenter at:
http://www.digital.com/info/alphaserver/products.html
Access the latest system firmware either with a Web browser or via FTP as follows:
ftp://ftp.digital.com/pub/Digital/Alpha/firmware/
Interim firmware released since the last firmware CD is located at:
ftp://ftp.digital.com/pub/Digital/Alpha/firmware/interim/

xii

Chapter 1
System Overview
The DIGITAL AlphaServer 1200 and DIGITAL Ultimate Workstation 533 systems
are made from the same base system unit. The base unit consists of up to two CPUs,
up to 2 Gbytes of memory, 6 I/O slots, and up to 7 SCSI storage devices. Both
systems are enclosed in pedestals. AlphaServer 1200 systems can be mounted in a
standard 19” rack.
AlphaServer 1200 systems support OpenVMS, DIGITAL UNIX, and Windows NT.
Ultimate Workstation 533 systems support Windows NT and graphics.
Topics in this chapter include the following:
•

System Enclosure

•

Operator Control Panel and Drives

•

System Consoles

•

System Architecture

•

CPU Types

•

Memory

•

Memory Addressing

•

System Motherboard

•

System Bus Backplane

•

System Bus to PCI Bus Bridge

•

PCI I/O Subsystem

•

Remote Control Logic

•

Power Control Logic

•

Power Circuit and Cover Interlock

•

Power Supply

•

Power Up/Down Sequence

•

Maintenance Bus (I C Bus)

•

StorageWorks Drives

System Overview

1-1

1.1

System Enclosure

The system has up to two CPU modules and up to 2 Gbytes of memory. A single
fast wide or fast wide Ultra SCSI StorageWorks shelf provides storage.

Figure 1-1 System Enclosure

4
1

2
6

5
PKW-0500-97

System Overview

1-2

The numbered callouts in Figure 1-1 refer to the system components.

➊ System card cage, which holds the system motherboard and the CPU, memory,
and system I/O.

➋ PCI/EISA section of the system card cage.
➌ Operator control panel assembly, which includes the control panel, the LCD
display, and the floppy drive.

➍ CD-ROM drive.
➎ Cooling section containing two fans.
➏ StorageWorks shelf.
Cover Interlock
The system has a single cover interlock switch tripped by the top cover.

Figure 1-2 Cover Interlock Circuit
Power Supply
Cover
Interlock

J30

Push button
ON/OFF
Switch
pack

J2
J7

Motherboard

OCP
DC_ENABLE_L

Cover
Interlock
Switch

PKW0503-97

NOTE: The cover interlock must be engaged to enable power-up.
To override the cover interlock, use a suitable object to close the interlock circuit.
Disk damage will result if the system is run with the top cover off.

System Overview

1-3

1.2

Operator Control Panel and Drives

The control panel includes the On/Off, Halt, and Reset buttons and an LCD
display.

Figure 1-3 Control Panel Assembly

CD-ROM
Floppy
OCP Display
1

PKW-0501-97

OCP display. The OCP display is a 16-character LCD that indicates status during
power-up and self-test. While the operating system is running, the LCD displays the
system type. Its controller is on the XBUS.
CD-ROM. The CD-ROM drive is used to load software, firmware, and updates. Its
controller is on PCI1 on the PCI backplane on the system motherboard.
Floppy disk. The floppy drive is used to load software and firmware updates. The
floppy controller is on the XBUS on the PCI backplane on the system motherboard.

System Overview

1-4

➊

On/Off button. Powers the system on or off. When the LED to the right of the
button is lit, the power is on. The On/Off button is connected to the power
supplies through the system interlock and the RCM logic.

➋

Reset button. Initializes the system.

➌

Halt button. When the halt button is pressed, different results are manifest
depending upon the state of the machine.
The major function of the Halt button is to stop whatever the machine is doing
and return the system to the SRM console.
To get to the SRM console, for systems running OpenVMS or DIGITAL UNIX
press the Halt button.
To get to the SRM console, for systems running Windows NT press the Halt
button and then press the Reset button. (Pressing the Halt button when the
system is running Windows NT causes a “halt assertion” flag to be set in the
firmware. When Reset is pressed the console reads the “halt assertion” flag and
ignores environment variables that would cause the system to boot.)
Function of the Halt button is complex because it depends upon the state of the
machine when the button is pressed. See Section B.1 for a full discussion of the
Halt button.

System Overview

1-5

1.3

System Consoles

There are two console programs: the SRM console and the AlphaBIOS console.

SRM Console Prompt
On systems running the DIGITAL UNIX or OpenVMS operating system, the
following console prompt is displayed after system startup messages are displayed, or
whenever the SRM console is invoked:
P00>>>
NOTE: The console prompt displays only after the entire power-up sequence is
complete. This can take up to several minutes if the memory is very large.
AlphaBIOS Boot Menu
On systems running the Windows NT operating system, the Boot menu is displayed
when the AlphaBIOS console is invoked:

AlphaBIOS 5.32
Please select the operating system to start:
Windows NT Server 4.0

Use and to move the highlight to your choice.
Press Enter to choose.

digi tal

AlphaServer 1200
Family
Press <F2> to enter SETUP
PKW0560-97

System Overview

1-6

SRM Console
The SRM console is a command-line interface that is used to boot the DIGITAL
UNIX and OpenVMS operating systems. It also provides support for examining and
modifying the system state and configuring and testing the system. The SRM console
can be run from a serial terminal or a graphics monitor.
AlphaBIOS Console
The AlphaBIOS console is a menu-based interface that supports the Microsoft
Windows NT operating system. AlphaBIOS is used to set up operating system
selections, boot Windows NT, and display information about the system configuration.
The EISA Configuration Utility and the RAID Standalone Configuration Utility are
run from the AlphaBIOS console. AlphaBIOS runs on either a serial or graphics
terminal. Windows NT requires a graphics monitor.
Environment Variables
Environment variables are software parameters that define, among other things, the
system configuration. They are used to pass information to different pieces of
software running in the system at various times. The os_type environment variable,
which can be set to VMS, UNIX, or NT, determines which of the two consoles is
used. The SRM console is always brought into memory, but AlphaBIOS is loaded if
os_type is set to NT and the Halt LED is not lit.
Refer to Appendix B of this guide for a list of the environment variables used to
configure a system.
Refer to your system User’s Guide for information on setting environment variables.
Most environment variables are stored in the NVRAM that is placed in a socket on the
system motherboard. Even though the NVRAM can be removed and replaced on a
new system motherboard, it is recommended that you keep a record of the
environment variables for each system that you service. Some environment variable
settings are lost when a module is swapped and must be restored after the new module
is installed. Refer to Appendix B for a convenient worksheet for recording
environment variable settings.

System Overview

1-7

1.4

System Architecture

Alpha microprocessor chips are used in these systems. The CPU, memory, and
the I/O modules are connected to the system motherboard.

Figure 1-4 Architecture Diagram

Memory
Pair

CPU
System Bus

128-Bit Data Bus + 16 ECC and 40-Bit Command/Address Bus
PCI Bus 0

System to
PCI Bus
Bridge 0
IOD0

64 Bits
EISA
Bridge

System to
PCI Bus
Bridge 1
IOD1

PCI Slot

System
Motherboard

PCI Slot

PCI Slot
Note: When the EISA/ISA slot
on PCI Bus 0 is used, the last
PCI slot on PCI Bus 1 is not
available.

EISA
PCI Slot

Bus

PCI Bus 1
64 Bits

PCI Slot

EISA Slot
XBUS

XBUS
Xceivers
Real-Time
Clock

Combo I/O:
serial ports
parallel port
floppy cntrl

BDATA
Xceivers

Mouse/

I2C Bus

NVRAM

Keyboard

Interface

8Kx8

Flash
ROM
2MB

PKW0502-97

System Overview

1-8

Both systems use the Alpha chip for the CPU. The CPU, memory, and I/O devices
connect to the system motherboard. On the system motherboard is:
•

The system bus

•

Two system bus to PCI bus chip sets that bridge two PCI buses to the system bus

•

Two 64-bit PCI buses with three PCI options slots each

•

One EISA/ISA bus bridged to one of the PCIs (If an EISA/ISA option is used, one
PCI slot cannot be used)

•

One CD-ROM controller built in to the other PCI

•

One EISA/ISA to XBUS bridge to the built-in XBUS options

A fully configured system can have two CPUs, eight DIMM memory pairs, and a total
of six I/O options. The I/O options can be all PCI options or a combination of PCI
options and a single EISA/ISA option.
The system bus has a 144-bit data bus, protected by 16 bits of ECC, and a 40-bit
command/address bus, protected by parity. The bus speed is set to 66.6 MHz. The
40-bit address bus can create one terabyte of addresses (that’s a million million). The
bus connects CPUs, memory, and the system bus to PCI bus bridge(s).
There is a cache external to the CPU chip on CPU modules. The Alpha chip has an 8Kbyte instruction cache (I-cache), an 8-Kbyte write-through data cache (D-cache), and
a 96-Kbyte, write-back secondary data cache (S-cache). The cache system is writeback. The system supports up to two CPUs.
Memory on these systems is constructed of DIMM memory pairs placed onto two
memory modules called riser cards. The riser cards are placed into the two memory
slots on the system motherboard. One member of a DIMM pair is placed onto one
riser card, and the other member is placed onto another riser card. Each riser card
drives half of the system bus, along with the associated ECC bits. Memory pairs
consist of two synchronous DIMMs of the same size and are placed into the same slot
on each riser card.
The system bus to PCI bus bridge chip set translates system bus commands and data
addressed to I/O space to PCI commands and data. It also translates PCI bus
commands and data addressed to system memory or CPUs to system bus commands
and data. The PCI bus is a 64-bit wide bus used for I/O.
Logic and sensors on the system motherboard monitor power status and the system
environment (temperature and fan speeds).

System Overview

1-9

1.5

CPU Types

There are several CPU variants differentiated by CPU speeds.

Figure 1-5 CPU Module Placement
Power connectors

Floppy
connector
Fan
connectors
CPU 0
MEM L

Bulkhead
connectors
CPU 1
RCM
Switchpack

MEM H
LEDs
PCI Bridges

PCI 0 Slot 2
Internal SCSI
connector

PCI 0 Slot 3
PCI 0 Slot 4

RCM power-down
connector

PCI 1 Slot 2
PCI 1 Slot 3
PCI 1 Slot 4

Speaker
connector

EISA/ISA Slot
OCP
connector

PKW0504A-97

System Overview

1-10

Alpha Chip Composition
The Alpha chip is made using state-of-the-art chip technology, has a transistor count
of 9.3 million, consumes 50 watts of power, and is air cooled (a fan is on the chip).
The default cache system is write-back and when the module has an external cache, it
is write-back. The Alpha chip used in these systems is the 21164.
Chip Description
Unit

Description

Instruction
Execution

8-Kbyte cache, 4-way issue
4-way execution; 2 integer units, 1 floating-point adder,
1 floating-point multiplier
Merge logic, 8-Kbyte write-through first-level data cache,
96-Kbyte write-back second-level data cache, bus interface
unit

Memory

CPU Variants
Module Variant

Clock Frequency

Onboard Cache

Color

B3007-AA
B3007-CA

400 MHz
533 MHz

4 Mbytes
4 Mbytes

Orange
Violet

CPU Configuration Rules
•

The first CPU must be in CPU slot 0 to provide the system clock.

•

The second CPU should be installed in CPU slot 1.

•

Both CPUs must have the same Alpha chip clock speed. The system bus may
hang without an error message if the oscillators clocking the CPUs are different.

System Overview

1-11

1.6

Memory

Memory consists of two riser cards and up to eight pairs of DIMMs. Each riser
card receives one of the two DIMMs in the DIMM pair. There are two DIMM
variants: a 32-Mbyte version and a 128-Mbyte version.

Figure 1-6 Memory Placement
Power connectors

Floppy
connector
Fan
connectors
CPU 0
MEM L

Bulkhead
connectors
CPU 1
RCM
Switchpack

MEM H
LEDs
PCI Bridges

PCI 0 Slot 2
Internal SCSI
connector

PCI 0 Slot 3
PCI 0 Slot 4

RCM power-down
connector

PCI 1 Slot 2
PCI 1 Slot 3
PCI 1 Slot 4

Speaker
connector

EISA/ISA Slot
OCP
connector

PKW0504B-97

System Overview

1-12

Memory Variants
Memory consists of two riser cards supporting eight DIMM pairs. There are two
DIMM variants: a 32-Mbyte version and a 128-Mbyte version. Maximum memory
using 32-Mbyte DIMMs is 128 Mbytes and the maximum memory using 128-Mbyte
DIMMs is 2 Gbytes. All memory is synchronous.
DRAM
Option

Size

Module

Type

Number

MS300-BA

64 MB

Synch.

MS300-DA

256 MB

54-25084-DA
20-47405-D3
54-25092-DA
20-45619-D3

Synch.

Size

4M x 72 =
32MB
16M x 72 =
128MB

Memory Operation
Each DIMM in the pair provides half the data, or 64 bits plus 8 ECC bits, of the
octaword (16 byte) transferred on the system bus. DIMMs are placed in slots on the
riser cards, and the riser cards are placed in the slots designated MEM L and MEM H
on the system motherboard.
NOTE: Memory in slot MEM L does not drive the lower 8 bytes, and memory in slot
MEM H does not drive the higher 8 bytes of the 16-byte transfer. Some bits
originating from MEM L are high order bits, and some bits originating from MEM H
are low order bits.
Memory drives the system bus in bursts. Upon each memory fetch, data is transferred
in 4 consecutive cycles transferring 64 bytes.
Memory Configuration Rules
In a system, memories of different sizes are permitted, but:
•

DIMMs are installed and used in pairs. Both DIMMs in a memory pair must be
of the same size.

•

Each riser card receives one DIMM of the DIMM pair.

•

The largest DIMM pair must be in riser card slot 0.

•

Other memory pairs must be the same size or smaller than the first memory pair.

•

Memory pairs must be installed in consecutive slots.

•

Memory configurations that have a 64-Mbyte pair in riser card slot 0 are limited
to two DIMM pairs or 128 Mbytes for the system. (The reason for this restriction
is that the bit map describing memory holes can grow larger than physical
memory.)
System Overview

1-13

1.7

Memory Addressing

Memory addressing in these systems is fixed regardless of the size of the DIMMs.
The address of a DIMM pair is fixed according to the slot in which the pair is
placed. The starting address of each pair in each slot on the riser card starts on a
512-Mbyte boundary.

Figure 1-7 How Memory Addressing Is Calculated
Address Space
Gbytes

Riser Card
Slot

4.0
3.5

e0000000

6
3.0

c0000000

2.5

a0000000

2.0

80000000

1.5

60000000

1.0

40000000

20000000

00000000

5
4
3
2

1
0

PKW0505-97

System Overview

1-14

The rules for addressing memory are as follows:
1.

A memory pair consists of two DIMMs of the same size.

Memory pairs in riser cards may be of different sizes.

The memory pair in slot 0 must be the largest of all memory pairs. Other memory
pairs may be as large but none may be larger.

The physical starting address of each memory pair is N times 512 Mbytes (200
0000) where N is the slot number on the riser card.

Memory addresses are contiguous within each memory pair.

If memory pairs do not completely fill the 512-Mbyte space provided, memory
“holes” occur in the physical address space.

Software creates contiguous virtual memory even though physical memory may
not be contiguous.

System Overview

1-15

1.8

System Motherboard

The system motherboard contains five major logic sections performing five
major system functions.

Figure 1-8

System Motherboard
Power connectors

Floppy
connector
Fan
connectors
CPU 0

Power
Control
Logic

MEM L
System Bus Backplane
CPU 1

Remote
Control
Logic

MEM H
System Bus
to
PCI Bus Bridges

PCI 0 Slot 2
PCI 0 Slot 3

Internal SCSI
connector

PCI 0 Slot 4
PCI 1 Slot 2
PCI 1 Slot 3

PCI Backplane
and Legacy I/O
Devices

PCI 1 Slot 4
Speaker
connector

EISA/ISA Slot
OCP
connector

PKW0504F-97

System Overview

1-16

The five sections on the system motherboard are:
•

The system bus or the CPU and memory backplane

•

The power control logic

•

The remote control logic

•

The system bus to PCI bus bridges

•

The PCI backplane containing two PCI buses, an EISA/ISA bus, a built-in CDROM controller, and an XBUS with several devices integral to the system.

System Overview

1-17

1.8.1 System Bus (Backplane)
The system bus consists of a 40-bit command/address bus, a 128-bit plus ECC
data bus, and several control signals and clocks. The system bus is part of the
system motherboard.

Figure 1-9 System Bus Block Diagram
MEM0
ADR

ROW
COL

SIM_ADR

DATA

SYNC
DRAMS

CTRL

MEM CTRL&
CNTRL ARB

MC Bus
Control
CPU1
CPU0

MC ADR
<39:4>
A
L
P
H
A

CTRL
EV_ADR

ADR

MC DATA
<127:0>

EV_DATA

PCI/ISA

MC to PCI Bridge

PCI/ISA0

IOD0

PCI1

IOD1

PKW0506-97

System Overview

1-18

The system bus consists of a 40-bit command/address bus, a 128-bit plus ECC data
bus, and several control signals, clocks, and a bus arbiter. The bus requires that all
CPUs have the same high-speed oscillator providing the clock to the Alpha chip.
The system bus connects up to two CPUs, up to eight DIMM memory pairs on two
riser cards, and two I/O bus bridges.
The system bus clock is provided by an oscillator on the CPU in slot CPU0. This
oscillator is adjusted to maintain the system bus at a 66 MHz speed no matter what the
speed of the CPU is.
The system bus backplane initiates memory refresh transactions.
Five volt, 3.43 volt, and 12 volt power is provided directly to the motherboard from
the power supplies.

System Overview

1-19

1.8.2 System Bus to PCI Bus Bridge
The bridge is the physical interconnect between the system bus and the PCI bus.

Figure 1-10 System Bus to PCI Bus Bridge Block Diagram
System Bus

PCI Bus

Control

CAP

AD<31:0>

Address
Control

ECC & Data
<63:0>

Data A
to B bus
MDPA
Data A to B &
B to A bus

ECC & Data
<127:64>

MDPB

AD<63:32>

PKW0507-97

System Overview

1-20

The system bus to PCI bus bridge module converts system bus commands and data
addressed to I/O space to PCI commands and data; and converts PCI bus commands
and data addressed to system memory or CPUs to system bus commands and data.
The bridge has two major components:
•

Command/address processor (CAP) chip

•

Two data path chips (MDPA and MDPB)

There are two sets of these three chips, one set for each PCI.
The interface on the system bus side of the bridge responds to system bus commands
addressed to the upper 64 Gbytes of I/O space. I/O space is addressed whenever bit
<39> on the system bus address lines is set. The space so defined is 512 Gbytes in
size. The first 448 Gbytes are reserved and the last 64 Gbytes, when bits <38:36> are
set, are mapped to the PCI I/O buses.
The interface on the PCI side of the bridge responds to commands addressed to CPUs
and memory on the system bus. On the PCI side, the bridge provides the interface to
the PCIs. Each PCI bus is addressed separately. The bridge does not respond to
devices communicating with each other on the same PCI bus. However, should a
device on one PCI address a device on the other PCI bus, commands, addresses, and
data run through the bridge out onto the system bus and back through the bridge to the
other PCI bus.
In addition to its bridge function, the system bus to PCI bus bridge module monitors
every transaction on the system bus for errors. It monitors the data lines for ECC
errors and the command/address lines for parity errors.

System Overview

1-21

1.8.3 PCI I/O Subsystem
The I/O subsystem consists of two 64-bit PCI buses. One has an embedded
EISA/ISA bridge and three PCI option slots; the other has a built-in CD-ROM
driver and three PCI option slots.

Figure 1-11 PCI Block Diagram
PCI-1 Bus
Serial
Interrupt
Logic

S
y
s
t
e
m

SCSI Control
53C810
Connector

PCI-1
3 64-bit slots

40MHz
Clock

33.3MHz
Osc
Clock Bfr

3&, %XV

B
u
s

XBUS

BDATA
Xceivers
NVRAM
8Kx8

Flash
ROM
2MB

PCI to EISA/ISA
Bridge Chipset

PCI-0
2 64-bit slots
1 32-bit slot

Serial
Interrupt
Logic

Realtime
Clock

Combo I/O:
serial ports
parallel port
floppy cntrl

EISA
Data
Bus

XBUS
Xceivers
Mouse/

I2C Bus

Keyboard

Interface

EISA:
1 16bit slot

PKW0508-97

System Overview

1-22

Table 1-1 PCI Motherboard Slot Numbering
Slot

PCI0

PCI1

PCI to EISA/ISA
bridge

Internal CD-ROM
controller

PCI slot

The logic for two PCI buses is on each PCI motherboard.
•

PCI0 is a 64-bit bus with a built-in PCI to EISA/ISA bus bridge. PCI0 has three
PCI slots and one EISA/ISA slot. When the EISA/ISA slot is used, PCI slot 4 on
PCI bus 1 is not available. An 8-bit XBUS is connected to the EISA/ISA bus. On
this bus there is an interface to the system I2 C bus; mouse and keyboard support;
an I/O combo controller supporting two serial ports, the floppy controller, and a
parallel port; a real-time clock; two 1-Mbyte flash ROMs containing system
firmware, and an 8-Kbyte NVRAM.

•

PCI1 is a 64-bit bus with a built-in CD-ROM SCSI controller with three PCI
slots.

Cable connectors to the CD-ROM, the floppy, and the OCP are on the motherboard.
Connectors for the mouse, keyboard, two COM ports, the serial port, and a modem are
on the system bulkhead. The bulkhead is part of the system motherboard.

System Overview

1-23

1.8.4 Remote Control Logic
A section of the motherboard provides remote control operation of the system. A
four-switch switchpack enables or disables remote control features.

Figure 1-12 Remote Control Logic
System Motherboard
RCM
Switchpack
SET DEF

RPD DIS

MODEM OFF
EN RCM

2
1

RCM power
VAUX from
power supplies

PKW0504C-97

System Overview

1-24

The system allows both local and remote control. A set of switches enables or
disables remote control.

Table 1-2 Remote Control Switch Functions
Switch

Condition

Function

1 EN RCM

On (default)
Off

Allows remote system control
Does not allow remote system control

2 Modem Off

On
Off (default)

Disables the RCM modem port
Enable the RCM modem port

3 RPD DIS

On
Off (default)

Disables remote power down
Enables remote power down

4 SET DEF

On
Off (default)

Resets the RCM microprocessor defaults
Allows use of conditions set by the user

The default settings allow complete remote control. The user would have to change
the switch settings to any other desired control.
See Appendix C for information on controlling the system remotely.
The remote console manager connects to a modem through the modem port on the
bulkhead. The RCM uses VAUX power provided by the system power supplies.
The standard I/O ports (keyboard, mouse, COM1 and COM2 serial ports, and parallel
ports) are on the same bulkhead.

System Overview

1-25

1.8.5 Power Control Logic
The power control section of the motherboard controls power sequencing and
monitors power supply voltage, system temperature, and fans.

Figure 1-13 Power Control Logic
System Motherboard

Power
control
logic

PKW0504D-97

System Overview

1-26

The power control logic performs these functions:
•

Monitors system temperature and powers down the system 30 seconds after it
detects that internal temperature of the system is above the value of the
environment variable over_temp. Default = 550 C.

•

Monitors the system and CPU fans at one second intervals and powers down the
system 30 seconds after it detects a fan failure.

•

Provides some visual indication of faults through LEDs.

•

Controls reset sequencing.

•

Provides I C interface for fans, power supplies, and temperature signals:

Power supply 0, 1: present

Power supply 0, 1: power OK

CPU fan 0, 1: OK

CPU 1: present

Overtemp: Temp OK

System fan 0, 1: OK

Fan Kit OK

System Overview

1-27

1.9

Power Circuit and Cover Interlock

Power is distributed throughout the system and mechanically can be broken by
the On/Off switch, the cover interlock, or remotely through the RCM.

Figure 1-14 Power Circuit Diagram

Power Supply
J30

Cover
Interlock

Push button
ON/OFF
J2

Switch
pack
J7

OCP
DC_ENABLE_L

Motherboard
PKW0503A-97

System Overview

1-28

Figure 1-14 shows the distribution of power throughout the system. Opens in the
circuit or the RCM signal RCM_DC_EN_L, or a power supply detected power fault
interrupt DC power applied to the system. The opens can be caused by the On/Off
button or the cover interlock.
A failure anywhere in the circuit will result in the removal of DC power. A potential
failure is the relay used in the remote control logic to control the RCM_DC_EN_L
signal.
The cover interlock is located under the top cover between the system card cage and
the storage area. To override the interlock, place a suitable object in the interlock
switch that closes it.

System Overview

1-29

1.10 Power Supply
Two power supplies provide system power.

Figure 1-15 Back of Power Supply and Location

Power
Supply 1

Current
share

Power
Supply 0

+5V/Return
+12V/Return

+5V/Return

+3.4V/Return

Misc.
Signal

PKW0513-97

System Overview

1-30

Description
Two power supplies each provide 450 W to the system. Redundant power is not
available at this time.
Power Supply Features
•

88–132 and 176–264 Vrms AC input

•

450 watts output. Output voltages are as follows:

•

Output Voltage

Min. Voltage

Max. Voltage

Max. Current

+5.0

4.90

5.25

+3.43

3.400

3.465

37.4

+12

11.5

12.6

–12

–13.2

–10.9

0.5

–5.0

–5.5

–4.6

0.2

Vaux

4.85

5.25

0.6

Remote sense on +5.0V and +3.43V
+5.0V is sensed on the system motherboard.
+3.43V is sensed on all CPUs in the system and the system bus motherboard.

•

Current share on +5.0V, +3.43V, and +12V.

•

1 % regulation on +3.43V.

•

Fault protection (latched). If a fault is detected by the power supply, it will shut
down. The power supply faults detected are:
Fan Failure
Over-voltage
Overcurrent
Power overload

•

DC_ENABLE_L input signal starts the DC outputs.

•

SHUTDOWN_H input signal shuts the power supply off in case of a system fan
or CPU fan failure.

•

POK_H output signal indicates that the power supply is operating properly.

System Overview

1-31

1.11 Power Up/Down Sequence
System power can be controlled manually by the On/Off button on the OCP or
remotely through the RCM. The power-up/down sequence flow is shown below.

Figure 1-16 Power Up/Down Sequence Flowchart
Apply AC
Power

Vaux on

On-Off
Button
Off

Off

On
On

On-Off
Button

Assert
DC_ENABLE_L
Power Supply
Starts

Disable Outputs
Deassert POK

Yes

Any
Faults
No

Assert
SHUTDOWN

Assert
POK

On
On-Off
Button

30 Second
Delay

Off

Fan/Temp
OK
Yes
PKW-0513A-97

System Overview

1-32

When AC is applied to the system, Vaux (auxiliary voltage) is asserted and is sensed
by the power control logic (PCL) section of the motherboard if the On-Off Button is
On. The PCL asserts DC_ENABLE_L starting the power supplies. If there is a hard
fault on power-up, the power supplies shut down immediately; otherwise, the power
system powers up and remains up until the system is shut off or the PCL senses a
fault. If a power fault is sensed, the signal SHUTDOWN is asserted after a 30 second
delay. Cycling the On-Off button can restore the power.

System Overview

1-33

1.12 Maintenance Bus (I C Bus)
2

The I C bus (referred to as the “I squared C bus”) is a small internal
maintenance bus used to monitor system conditions scanned by the power control
logic, write the fault display, store error state, and track configuration
information in the system. Although all system modules (not I/O modules) sit on
2
the maintenance bus, only the I C controller accesses it.

Figure 1-17 I2C Bus Block Diagram

Motherboard
Thermom/
Thermostat
1

CPU 0

PCL
Registers

up to 8

Memory
Pairs

MEMs

I C Bus

IOD 1

CPUs

PCI 1

IOD0
IOD 0

PCI 0

OCP
Controller

PCI0
2

I C Bus
Controller

XBUS

ISA

PKW0511-97

System Overview

1-34

Monitor
2

The I C bus monitors the state of system conditions scanned by the power control
logic. There are two registers that the PC logic writes data to:
•

One records the state of the fans and power supplies and is latched when there is a
fault.

•

The other causes an interrupt on the I2C bus when a CPU or system fan fails, an
overtemperature condition exists, or power supplied to the system exhibits an
overcurrent condition.
2

The interrupt received by the I C bus controller on PCI 0 and passed on to the IOD 0
chip set alerts the system of imminent power shutdown. The controller has 30 seconds
to read the two registers and store the information in the EEPROM on the
motherboard. The SRM console command show power reads these registers.
Fault Display
The OCP display is written through the I2C bus.

Error State
Error state is stored for power, fan, and overtemperature conditions on the I2C bus.
Configuration Tracking
Each CPU and each logical section of the system motherboard (the PCI bridge, the
PCI backplane, the power control logic, the remote console manager), and the system
motherboard itself has an EEPROM that contains information about the module that
2
can be written and read over the I C bus. All EEPROMs contain the following
information:
•

Module type

•

Module serial number

•

Hardware revision for the logical block

•

Firmware revision

System Overview

1-35

1.13 StorageWorks Drives
The system supports up to seven StorageWorks drives.

Figure 1-18 StorageWorks Drive Location

StorageWorks
Drives Shelf

PKW0514-97

System Overview

1-36

The StorageWorks drives are to the right of the system cage. Up to seven drives fit
into the shelf. The system supports fast wide Ultra SCSI disk drives. The RAID
controller is also supported. With an optional Ultra SCSI Bus Splitter Kit the
StorageWorks shelf can be split into two buses.

System Overview

1-37

Chapter 2
Power-Up
This chapter describes system power-up testing and explains the power-up displays.
The following topics are covered:
•

Control Panel

•

Power-Up Sequence

•

SROM Power-Up Test Flow

•

SROM Errors Reported

•

XSROM Power-Up Test Flow

•

XSROM Errors Reported

•

Console Power-Up Tests

•

Console Device Determination

•

Console Power-Up Display

•

Fail-Safe Loader

Power-Up

2-1

2.1

Control Panel

The control panel display indicates the likely device when testing fails.

Figure 2-1 Control Panel and LCD Display

&RQWURO 3DQHO

P0 TEST 11 CPU0

PKW0510-97

•

When the On/Off button LED is on, power is applied and the system is running.
When it is off, the system is not running, but power may or may not be present. If
the power supplies are receiving AC power, Vaux is present on the system
motherboard regardless of the condition of the On/Off switch.

•

When the Halt button LED is lit and the On/Off button LED is on, the system
should be running either the SRM console or Windows NT.

Power-Up

2-2

Table 2-1 Control Panel Display
Field

Content

Display

Meaning

➊
➋

CPU number

P0–P1

CPU reporting status

Status

TEST

Tests are executing

FAIL

Failure has been detected

MCHK

Machine check has occurred

INTR

Error interrupt has occurred

CPU0–1

CPU module number

MEM0–7 and L,
H, or *

Memory pair number and low
DIMM, high DIMM, or either

IOD0

Bridge to PCI bus 0

IOD1

Bridge to PCI bus 1

FROM0

Flash ROM

COMBO

COM controller

PCEB

PCI-to-EISA bridge

ESC

EISA system controller

NVRAM

Nonvolatile RAM

TOY

Real-time clock

I8242

Keyboard and mouse controller

➌
➍

Test number
Suspected device

1
1

1
1
1
1

1
1

The potentiometer, accessible through the access hole just above the Reset button
controls the intensity of the LCD. Use a small Phillips head screwdriver to adjust.

On the system motherboard (54-25147-01)

Power-Up

2-3

2.2

Power-Up Sequence

Console and most power-up tests reside on the I/O subsystem, not on the CPU
nor on any other module on the system bus.

Figure 2-2 Power-Up Flow

Power-Up/Reset

XSROM tests execute

SROM code loaded
into each CPU’s
I-cache

SRM console loaded
into memory

SROM tests execute

SRM console tests
execute

XSROM loaded into
each CPU’s S-cache

SRM console either
remains in the system
or loads AlphaBIOS
console
PKW0432B-96

Definitions
SROM. The SROM is a 128-Kbit ROM on each CPU module. The ROM contains
minimal diagnostics that test the Alpha chip and the path to the XSROM. Once the
path is verified, it loads XSROM code into the Alpha chip and jumps to it.
XSROM. The XSROM, or extended SROM, contains back-up cache and memory
tests, the I/O subsystem tests for embedded devices, and a fail-safe loader. The
Power-Up

2-4

XSROM code resides in sector 0 of FEPROM 0 on the XBUS. Sector 2 of FEPROM
0 contains a duplicate copy of the code and is used if sector 0 is corrupt. Code for
sizing DIMM memory resides in sector 1 of FEPROM 0 along with the PAL code.
FEPROM. Two 1-Mbyte programmable ROMs (FEPROMS) are on the XBUS on
PCI0. FEPROM 0 contains two copies of the XSROM, the OpenVMS and DIGITAL
UNIX PAL code, and the SRM console and decompression code. FEPROM 1
contains the AlphaBIOS and NT HAL code. See Figure 2-3. These two FEPROMs
can be flash updated. Refer to Appendix A.

Figure 2-3 Contents of FEPROMs
FEPROM 0

FEPROM 1

Sector
0

XSROM
and
Fail Safe ldr

Pal Code

64Kb

XSROM DIMM

XSROM
and
64Kb
Fail Safe ldr
Decompress

AlphaBIOS
Code

3
1 Mbyte

SRM
Console
Code

64Kb
PKW0515-97

Power-Up

2-5

For the console to run, the path from the CPU to the XSROM must be functional. The
XSROM resides in FEPROM0 on the XBUS, off the EISA bus, off PCI 0, off IOD 0.
See Figure 2-4. This path is minimally tested by SROM.

Figure 2-4 Console Code Critical Path (Block Diagram)

Memory
Pair

CPU
System Bus

128-Bit Data Bus + 16 ECC and 40-Bit Command/Address Bus
PCI Bus 0

System to
PCI Bus
Bridge 0
IOD0

64 Bits
EISA
Bridge

PCI Bus 1
64 Bits

System to
PCI Bus
Bridge 1
IOD1

PCI Slot

System
Motherboard

PCI Slot

EISA
Bus

Note: When the EISA slot on
PCI Bus 0 is used, the last
PCI slot on PCI Bus 1 is not
available.

PCI Slot

EISA Slot
XBUS

XBUS
Xceivers
Real-Time
Clock

Combo I/O:
serial ports
parallel port
floppy cntrl

BDATA
Xceivers

Mouse/

I2 C Bus

NVRAM

Keyboard

Interface

8Kx8

Flash
ROM
2MB

PKW0502A-97

Power-Up

2-6

The SROM contents are loaded into each CPU’s I-cache and executed on powerup/reset. After testing the caches on each processor chip, it tests the path to the
XSROM. Once this path is tested and deemed reliable, layers of the XSROM are
loaded sequentially into the processor chip on each CPU. None of the SROM or
XSROM power-up tests are run from memory—all run from the caches in the CPU
chip, thus providing excellent diagnostic isolation. Later power-up tests, run under the
console, are used to complete testing of the I/O subsystem.
There are two console programs: the SRM console and the AlphaBIOS console, as
detailed in your system User’s Guide. By default, the SRM console is always loaded
and I/O system tests are run under it before the system loads AlphaBIOS. To load
AlphaBIOS, the os_type environment variable must be set to NT and “halt assertion”
must be clear. Otherwise, the SRM console continues to run.

Power-Up

2-7

2.3

SROM Power-Up Test Flow

The SROM tests the CPU chip and the path to the XSROM.

Figure 2-5

SROM Power-Up Test Flow
For each CPU
Initialize CPU chip
Turn off CPU LED

HANG

Yes

Initialize
PCI-EISA bridge
chip

D-cache
errors

Read TOY
NVRAM

No
HANG

All 3 S-cache
banks pass

Initialize Combo Chip
on XBUS for access
to COM port 1

Yes

Yes
HANG

Initialize OCP port
on XBUS for access
to OCP display

Dupilcate Tag or
Fill errors
No
Light CPU LED

Print to console
device and OCP

Determine Primary

Initialize all S-cache
banks

Size IOD
Check integrity of
XSROM
Fail
Loopback on
each IOD
Pass
Light IOD LEDs

Fail
twice
HANG

Pass
Load first 8K of
XSROM into
S-cache

Jump to XSROM
overlay in S-cache
PKW0432-96

Power-Up

2-8

The Alpha chip built-in self-test tests the I-cache at power-up and upon reset.
Each CPU chip loads its SROM code into its I-cache and starts executing it. If the
chip is partially functional, the SROM code continues to execute. However, if the
chip cannot perform most of its functions, that CPU hangs and that CPU pass/fail LED
remains off. (In these systems, the CPU pass/fail LED is not visible.)
If the system has more than one CPU and at least one passes both the SROM and
XSROM power-up tests, the system will bring up the console. The console checks the
FW_SCRATCH register where evidence of the power-up failure is left. Upon finding
the error, the console sends these messages to COM1 and the OCP:
•

COM1 (or VGA):

Power-up tests have detected a problem with your system

•

OCP:

Power-up failure

Power-Up

2-9

Table 2-2 lists the tests performed by the SROM.

Table 2-2 SROM Tests
Test Name

Logic Tested

D-cache RAM March
test

D-cache access, D-cache data, D-cache address logic

D-cache Tag RAM
March test

D-cache tag store RAM, D-cache bank address logic

S-cache Data March
test

S-cache RAM cells, S-cache data path, S-cache address
path

S-cache Tag RAM
March test

S-cache tag store RAM, S-cache bank address logic

I-cache Parity Error
test

I-cache parity error detection, ISCR register and error
forcing logic, IC_PERR_STAT register and reporting
logic

D-cache Parity Error
test

D-cache parity error detection, DC_MODE register and
parity error forcing logic, DC_PERR_STAT register and
reporting logic

S-cache Parity Error
test

S-cache parity error detection, SC_CTL register and
parity error forcing logic, SC_STAT register and
reporting logic

IOD Access test

Access to IOD CSRs, data path through CAP chip and
MDP0 on each IOD, PCI0 A/D lines <31:0>

Power-Up

2-10

2.4

SROM Errors Reported

The SROM reports machine checks, pending interrupt/exception errors, and
errors related to corruption of FEPROM 0. If SROM errors are fatal, the
particular CPU will hang and only the CPU self-test pass LEDs and/or the LEDs
on the system motherboard will indicate the failure. The CPU self-test pass LED
is not visible but the IOD0 and IOD1 pass LEDs are.

Example 2–1 SROM Errors Reported at Power-Up
Unexpected Machine Check (CPU Error)
UNEX MCHK on CPU 0
EXC_ADR 42a9
EI_STAT fffffff004ffffff
EI_ADDR ffffff000000801f
SC_STAT 0
SC_ADDR FFFFFF0000005F2F
Pending Interrupt/Exception (CPU Error)
INT-EXC on CPU0
ISR
400000
EI_STAT fffffff007ffffff
EI_ADDR ffffff7fffffffdf
FIL_SYN 631B
BCTGADR ffffffa7fffcafff
FEPROM Failures (PCI Motherboard Error)
Sector 0 failures (XSROM flash unload failure)
Sctr 0 -XSROM headr PTTRN fail
Sctr 0 -XSROM headr CHKSM fail
Sctr 0 -XSROM code CHKSM fail
Sector 2 failures (XSROM recovery flash unload failure)
Sctr 2 -XSROM headr PTTRN fail
Sctr 2 -XSROM headr CHKSM fail
Sctr 2 -XSROM code CHKSM fail

Power-Up

2-11

2.5

XSROM Power-Up Test Flow

Once the SROM has completed its tests and verified the path to the FEPROM
containing the XSROM code, it loads the first 8 Kbytes of XSROM into the
primary CPU’s S-cache and jumps to it.

Figure 2-6 XSROM Power-Up Flowchart

XSROM banner to
OCP/console device

Clear SC_FHIT (force hit)
Enable all 3 S-cache banks

Run memory texts.
Print trace to OCP/console dev.
Print errors to OCP/console dev.
Done message to console dev.

Run B-cache tests
Print errors to OCP/console dev.
Done message to console dev.

Boot processor
redetermination

Primary
verifies checksum
of PAL/decomp/console
code

Initialize B-cache
and enable duplicate tag

Size system memory
through I squared C bus

Print mem info to console dev.
Check for illegal memory config.
Print warnings to console dev.
and OCP.
Initialize all memory pairs.

Fail

Fail-safe
loader

Pass
Primary unloads PAL/
decompression code or
fail-safe loader depending
upon results of checksum

Primary jumps to PALcode
and starts the console

Secondaries alerted that
console has started. They
jump to and run PALcode
joining the console.

Note: The XSROM can only print to the console device if
the environment variable console = serial. It always sends
output to the OCP.

PKW0432A-96

XSROM tests are described in Table 2-3. Failure indicates a CPU failure.

Power-Up

2-12

After jumping to the primary CPU’s S-cache, the code then intentionally I-caches itself
and is completely register based (no D-stream for stack or data storage is used). The
only D-stream accesses are writes/reads during testing.
Each FEPROM has sixteen 64-Kbyte sectors. The first sector contains B-cache tests,
memory tests, and a fail-safe loader. The second sector contains support for system
memory and PALcode. The third sector contains a copy of the first sector. The
remaining thirteen sectors contain the SRM console and decompression code.
NOTE: Memory tests are run during power-up and reset (see Table 2-4). They are
also affected by the state of the memory_test environment variable, which can have the
following values:
FULL
PARTIAL
NONE

Test all memory
Test up to the first 256 Mbytes
Test 32 Mbytes

Table 2-3 XSROM Tests
Test

Test Name

Logic Tested

B-cache Data March test

B-cache data RAMs, CPU chip B-cache
control, CPU chip B-cache address decode,
INDEX_H<23:6> (address bus)

B-cache Tag March test

B-cache tag store RAMs, B-cache STAT
store RAMs

B-cache ECC Data Line test

CPU chip ECC generation and checking
logic, ECC lines from CPU chip to Bcache, B-cache ECC RAMs

B-cache Tag Data Line test

Access to B-cache tags, shorts between tag
data and its status and parity bits

B-cache Data Line test

B-cache data lines to B-cache data RAMs,
B-cache read/write logic

B-cache ECC Data Line test

CPU chip ECC generation and checking
logic, ECC lines from CPU chip to Bcache, B-cache ECC RAMs

Power-Up

2-13

Table 2-4 Memory Tests
Test

Test Name

Logic Tested

Description

Memory
Data test

Data path to and from
memory
Data path on memory and
RAMs

Test floats 1 and 0 across data
and check bit data lines.
Errors are reported for each
DIMM memory card from
MEM0_L to MEM7_H.

Memory
Address test

Address path to and from
memory
Address path on memory
and RAMs

Same as test 20.

23*

Memory
Bitmap
Building

No new logic

Maps out bad memory by way
of the bitmap. It does not
completely fail memory.

Memory
March test

No new logic

Maps out bad memory.

* There is no test 22.

Power-Up

2-14

2.6

XSROM Errors Reported

The XSROM reports B-cache test errors and memory test errors. It also reports
a warning if memory is illegally configured.

Example 2–2 XSROM Errors Reported at Power-Up
B-cache Error (CPU Error)
TEST ERR on cpu0
FRU
cpu0
err# 2
tst# 11
exp: 5555555555555555
rcv: aaaaaaaaaaaaaaaa
adr: ffff8

#CPU running the test

#Expected data
#Received data
#B-cache location
#error occurred

Memory Error (Memory Module Indicated)
20..21..
TEST ERR on cpu0
#CPU running test
FRU: MEM1L
#Low member of memory pair 1
err# c
tst# 21
22..23..24..Memory testing complete on cpu0
Memory Configuration Error (Operator Error)
ERR!
ERR!
ERR!
ERR!

mem_pair0 misconfigured
mem_pair1 card size mismatch
mem_pair6 card type mismatch
mem_pair1 EMPTY

FEPROM Failures (PCI Error)
Sctr 1 -PAL headr PTTRN fail
Sctr 1 -PAL headr CHKSM fail
Sctr 1 -PAL code CHKSM fail
Sctr 3 -CONSLE headr PTTRN fail
Sctr 3 -CONSLE headr CHKSM fail
Sctr 3 -CONSLE code CHKSM fail

Power-Up

2-15

2.7

Console Power-Up Tests

Once the SRM console is loaded, it tests each IOD further. Table 2-5 describes
the IOD power-up tests, and Table 2-6 describes the PCI power-up tests.

Table 2-5 IOD Tests
Test #

Test Name

Description

IOD CSR Access test

Read and write all CSRs in each IOD.

Loopback test

Dense space writes to the IOD’s PCI dense
space to check the integrity of ECC lines.

ECC test

Loopback tests similar to test 2 but with a
varying pattern to create an ECC of 0s.
Single- and double-bit errors are checked.

Parity Error and Fill
Error tests

Parity errors are forced on the address and
data lines on system bus and PCI buses. A
fill error transaction is forced on the system
bus.

Translation Error test

A loopback test using scatter/gather address
translation logic on each IOD.

Write Pending test

Runs test 2 with the write-pending bit set
and clear in the CAP chip control register.

PCI Loopback test

Loops data through each PCI on each IOD,
testing the mask field of the system bus.

PCI Peer-to-Peer
Byte Mask test

Tests that devices on the same PCI and on
different PCIs can communicate.

Page Table Entry test
1 (CAP chip)

Tests every PTE using scatter/gather
translation and addressing.

Page Table Entry test
2 (CAP chip)

Tests random PTEs forcing use of all
interesting tag and page registers.

Not run on power-up. These tests take approximately 30 seconds and are run in user mode.

Power-Up

2-16

Table 2-6 PCI Motherboard Tests
Test
Number

Test Name

Diagnostic
Name

Description

PCEB

pceb_diag

Tests the PCI to EISA bridge chip

ESC

esc_diag

Tests the EISA system controller

8K NVRAM

nvram_diag

Tests the NVRAM

Real-Time Clock

ds1287_diag

Tests the real-time clock chip

Keyboard and
Mouse

i8242_diag

Tests the keyboard/mouse chip

Flash ROM

flash_diag

Dumps contents of flash ROM

Serial and
Parallel Ports and
Floppy

combo_diag

Tests COM ports 1 and 2, the
parallel port, and the floppy

CD-ROM

ncr810_diag

Tests the CD-ROM controller

For both IOD tests and PCI 0 and PCI 1 tests, trace and failure status is sent to the
OCP. If any of these tests fail, a warning is sent to the SRM console device after the
console prompt (or AlphaBIOS pop-up box). The IOD LEDs on the system
motherboard are controlled by the diagnostics. If a LED is off, a failure occurred.

Power-Up

2-17

2.8

Console Device Determination

After the SROM and XSROM have completed their tasks, the SRM console
program, as it starts, determines where to send its power-up messages.

Figure 2-7 Console Device Determination Flowchart
Power-Up/Reset
or
P00>>> Init

Console Envar
= serial

Yes
Enable COM port 1
and send messages
as system is powering up

Console Envar
= graphics

Yes

VGA adapter
on
PCI0

Yes

VGA becomes the
console device.

No
Enable COM port 1
and send messages
as system is powering up.
Warning message sent if a
VGA adapter is seen on PCI 1
PKW0434-96

Power-Up

2-18

Console Device Options
The console device can be either a serial terminal or a graphics monitor. Specifically:
•

A serial terminal connected to COM1 off the bulkhead. The terminal connected
to COM1 must be set to 9600 baud. This baud rate cannot be changed.

•

A graphics monitor off an adapter on PCI0.

Systems running Windows NT must have a graphics monitor as the console device
and run AlphaBIOS as the console program.
During power-up, the SROM and the XSROM always send progress and error
messages to the OCP and to the COM1 serial port if the SRM console environment
variable (set with the set console command) is set to serial. If the console
environment variable is set to graphics, no messages are sent to COM1.
If the console device is connected to COM1, the SROM, XSROM, and console powerup messages are sent to it once it has been initialized. If the console device is a
graphics device, console power-up messages are sent to it, but SROM and XSROM
power-up messages are lost. No matter what the console environment variable setting,
each of the three programs sends messages to the control panel display.

Messages
Sent By
SROM
XSROM
SRM console

Console Set to
Serial
Graphics
COM1
Lost, though a subset is sent to the OCP
COM1
Lost, though a subset is sent to the OCP
COM1
VGA, though a subset is sent to the OCP

Changing Where the Console Output Is Displayed
You can change where console output is displayed, assuming the SRM console has
fully powered up and the os_type environment variable is set to openvms or unix.
(The following does not work if os_type is set to nt.)
If the console environment variable is set to serial and no serial terminal is attached to
COM1, pressing a carriage return on a graphics monitor attached to the system makes
it the console device and the console prompt is sent to it. If the console environment
variable is set to graphics and no graphics monitor is attached to the adapter, pressing
a carriage return on a serial terminal attached to COM1 makes it the console device
and the console prompt is sent to it. In either case power-up information is lost.

Power-Up

2-19

2.9

Console Power-Up Display

The entire power-up display prints to a serial terminal (if the console
environment variable is set to serial), and parts of it print to the control panel
display. The last several lines print to either a serial terminal or a graphics
monitor.

Example 2–3 Power-Up Display
SROM V3.0 on cpu0
SROM V3.0 on cpu1
XSROM V5.0 on cpu0
XSROMb V5.0 on cpu1
BCache testing complete on cpu1
BCache testing complete on cpu0
mem_pair0 - 256 MB
mem_pair1 - 256 MB
mem_pair2 - 64 MB
mem_pair3 - 64 MB
20..21..20..21..23..24..24..
Memory testing complete on cpu0
Memory testing complete on cpu1

➊
➋
➌
➍

➎

Power-Up

2-20

➊

At power-up or reset, the SROM code on each CPU module is loaded into that
module’s I-cache and tests the module. If all tests pass, the processor’s LED
lights. If any test fails, the LED remains off and power-up testing terminates on
that CPU.
The first determination of the primary processor is made, and the primary
processor executes a loopback test to each PCI bridge. If this test passes, the
bridge LED lights. If it fails, the LED remains off and power-up continues. The
EISA system controller, PCI-to-EISA bridge, COM1 port, and control panel
port are all initialized thereafter.
Each CPU prints an SROM banner to the device attached to the COM1 port
and to the control panel display. (The banner prints to COM1 if the console
environment variable is set to serial. If it is set to graphics, nothing prints to
the console terminal, only to the control panel display, until ➏ occurs).

➋

Each processor's S-cache is initialized, and the XSROM code in the FEPROM
on the PCI 0 is unloaded into them. (If the unload is not successful, a copy is
unloaded from a different FEPROM sector. If the second try fails, the CPU
hangs.)
Each processor jumps to the XSROM code and sends an XSROM banner to the
COM1 port and to the control panel display.

➌

The three S-cache banks on each processor are enabled, and then the
B-cache is tested. If a failure occurs, a message is sent to the COM1 port and
to the control panel display.
Each CPU sends a B-cache completion message to COM1.

➍

The primary CPU is again determined, and memory is sized using code in
sector 1 of FEPROM 0.
The information on memory pairs is sent to COM1. If an illegal memory
configuration is detected, a warning message is sent to COM1 and the control
panel display.

➎

Memory is initialized and tested, and the test trace is sent to COM1 and the
control panel display. Each CPU participates in the memory testing. The
numbers for tests 20 and 21 might appear interspersed, as in Example 2–3.
This is normal behavior. Test 24 can take several minutes if the memory is
very large. The message “P0 TEST 24 MEM**” is displayed on the control
panel display; the second asterisk rotates to indicate that testing is continuing.
If a failure occurs, a message is sent to the COM1 port and to the control panel
display.
Each CPU sends a test completion message to COM1.
Continued on next page
Power-Up

2-21

Example 2–3 Power-Up Display (Continued)
starting console on CPU 0
➏
sizing memory
➐
0
256 MB DIMM
1
256 MB DIMM
64 MB DIMM
64 MB DIMM
starting console on CPU 1
probing IOD1 hose 1
➑
bus 0 slot 1 - NCR 53C810
bus 0 slot 2 - DECchip 21041-AA
bus 0 slot 3 - NCR 53C810
probing IOD0 hose 0
bus 0 slot 1 – PCEB
probing EISA Bridge, bus 1
bus 0 slot 2 – S3 Trio64/Trio32
bus 0 slot 3 – DECchip 21140-AA
Configuring I/O adapters...
Ncr0, hose 1, bus 0, slot 1
Tulip0, hose 1, bus 0, slot 2
Ncr1, hose 1, bus 0, slot 3
Floppy0, hose 0, bus 1 slot 0
Mc0, hose 0 bus 0, slot 2
tulip1, hose 0, bus 0, slot 3
System temperature is 31 degrees C
AlphaServer 1200 Console V5.0, 02-SEP-1997 18:18:26 ➒
P00>>>

Power-Up

2-22

➏

The final primary CPU determination is made. The primary CPU unloads
PALcode and decompression code from the FEPROM on PCI 0 to its B-cache.
The primary CPU then jumps to the PALcode to start the SRM console.
The primary CPU prints a message indicating that it is running the console.
Starting with this message, the power-up display is printed to the default
console terminal, regardless of the state of the console environment variable.
(If console is set to graphics, the display from here to the end is saved in a
memory buffer and printed to the graphics monitor after the PCI buses are
sized and the graphics device is initialized.)

➐

The size and type of each memory pair is determined.
The console is started on each of the secondary CPUs. A status message prints
for each CPU.

➑

The PCI bridges (indicated as IODn) are probed and the devices are reported.
I/O adapters are configured.

➒

The SRM console banner and prompt are printed. (The SRM prompt is shown
in this manual as P00>>>. It can, however, be P01>>>.) If the auto_action
environment variable is set to boot or restart and the os_type environment
variable is set to unix or openvms, the DIGITAL UNIX or OpenVMS
operating system boots.
If the system is running the Windows NT operating system (the os_type
environment variable is set to nt), the SRM console loads and starts the
AlphaBIOS console and does not print the SRM banner or prompt.

Power-Up

2-23

2.10 Fail-Safe Loader
The fail-safe loader is a software routine that loads the SRM console image from
floppy. Once the console is running you will want to run LFU to update
FEPROM 0 with a new image.

NOTE: FEPROM 0 contains images of the SROM, XSROM, PAL, decompression,
and SRM console code.
If the fail-safe loader loads, the following conditions exist on the machine:
•

The SROM has passed its tests and successfully unloaded the XSROM. If the
SROM fails to unload both copies of XSROM, it reports the failure to the control
panel display and COM1 if possible, and the system hangs.

•

The XSROM has completed its B-cache and memory tests but has failed to
unload the PALcode in FEPROM 0 sector 1 or the SRM console code.

•

The XSROM reports the errors encountered and loads the fail-safe loader.

Power-Up

2-24

Chapter 3
Troubleshooting
This chapter describes troubleshooting during power-up and booting. It also describes
the console test command and other useful commands. The following topics are
covered:
•

Troubleshooting with LEDs

•

Troubleshooting Power Problems

•

Running Diagnostics—Test Command

•

Releasing Secure Mode

•

Testing an Entire System

•

Other Useful Console Commands

Troubleshooting

3-1

3.1

Troubleshooting with LEDs

During power-up, reset, initialization, or testing, diagnostics are run on CPUs,
memories, I/O bridges, and the PCI backplane and its embedded options. This
section describes possible problems that can be identified by checking LEDs.
Unfortunately LEDs on the CPU module are not visible; the only visible LEDs
are on the system motherboard.

Figure 3-1 System Motherboard LEDs
System Motherboard

LEDs
IOD0 Pass
IOD1 Pass
Fan Fault
Temp OK

PKW0504G-97

Troubleshooting

3-2

System Motherboard LEDs
You see the system motherboard LEDs by looking through the grate at the back of the
machine. The normal state of the LEDs is shown in Figure 3-1.
•

If one of the IOD LEDs is off, the system bus to PCI bus bridge has failed.
Replace the system motherboard.

•

If the Fan Fault LED is ON, at least one of the four fans is broken. If this
condition occurs while the system is up and running, an error message identifying
the FRU is printed to the console. If this condition occurs during a cold start,
identifying which fan caused the fan fault depends upon which type of console the
system has. If your console is a serial terminal (for OpenVMS or DIGITAL
UNIX), the error identifying which fan failed is reported at the console. If your
console is a graphics monitor (for NT), reset the system and watch the OCP
display. During the first 30 seconds, one of the following message should occur:
•

SYSx Fan Failed where x = 0 or 1

•

CPUx Fan Failed where x = 0 or 1

Replace the failing FRU.
•

If the Temp OK LED is OFF, an overtemperature condition exists. Several things
can cause this condition: blocked airflow, temperature in the room where the
system is located is too high, the system card cage is open and air is not channeled
properly over the system. Fix any of these conditions, if possible. The
overtemperature threshold is programmable and is controlled by the environment
variable over_temp. Its default is 55 degrees C. After the system has cooled
down and can be powered up, you can change the threshold. If you do this and
the temperature inside the system gets too hot, it is likely that system errors will
occur and the system may crash.

Troubleshooting

3-3

3.2

Troubleshooting Power Problems

Power problems can occur before the system is up or while the system is running.

Power Problem List
The system will halt for the following reasons:
1.

A CPU fan failure

A system fan failure

An overtemperature condition

Power supply failure

Circuit beaker(s) tripped

AC problem

Interlock switch activation or failure

Environmental electrical failure or unrecoverable system fault with auto_action ev
= halt or boot

Cable failure

Indication of failure:
1.

LEDs indicate fan and overtemperature condition

The OCP display

Circuit breaker(s) tripped

There is no obvious indication for failures 7 – 10 from the power system.

Troubleshooting

3-4

Halt Caused by Power, Fan, or Overtemperature Condition
If a system is stopped because of a power, fan, or overtemperature problem, the
console and the OCP should report the problem.
If Power Problem Occurs at Power-Up
If the system has a power problem on a cold start, the motherboard LEDs and the OCP
display will indicate a problem. The console, for systems running DIGITAL UNIX or
OpenVMS, will also indicate the problem. The console on systems running NT will
not print an error message. Causes of power problems are:
•

Broken system fan

•

Broken CPU fan

•

A power supply could be broken and the system could still power up
momentarily. (During power-up, an overcurrent condition occurs with two power
supplies and is tolerated for a short period but a persistent overcurrent is not.)

•

Power control logic on the motherboard could fail

•

Interlock failure

•

Wire problems

•

Temperature problem (unlikely)

Recommended Order for Troubleshooting Failure at Power-Up
1.

If the SRM console does not come all the way up, check the console test output
on OpenVMS or DIGITAL UNIX systems. Restart the system if the system runs
NT and watch for an error message on the OCP display. Replace the FRU
indicated.

If you can get to the SRM console, use the show power command. It will show
the last power fault.

If neither step one nor step 2 identifies a FRU, replace the motherboard.

Troubleshooting

3-5

3.3

Running Diagnostics — Test Command

The test command runs diagnostics on the entire system, CPU devices, memory
devices, and the PCI I/O subsystem. The test command runs only from the SRM
console. Ctrl/C stops the test. The console cannot be secure.

Example 3–1 Test Command Syntax
P00>>> help test
FUNCTION
SYNOPSIS
test ([-q] [-t <time>] [option]
where option is:
cpun
memn
pcin
where n = 0, 1 or * for CPUs and PCIs
where n = 0 through 7 or * for MEM
The entire system is tested by default if no is option
specified.
NOTE: If you are running the Microsoft Windows NT operating system, switch from
AlphaBIOS to the SRM console in order to enter the test command. From the
AlphaBIOS console, press in the Halt button (the LED will light) and reset the system,
or select DIGITAL UNIX (SRM) or OpenVMS (SRM) from the Advanced CMOS
Setup screen and reset the system.
test [-t time] [-q] [option]
-t time

Specifies the run time in seconds. The default for system test is 600
seconds (10 minutes).

-q

Disables the display of status messages as exerciser processes are started
and stopped during testing.

option

Either cpun, memn, or pcin, where n is 0, 1, or * for CPUs and PCIs; or
where n is 0 through 7 or * for memory. If nothing is specified, the entire
system is tested.

Troubleshooting

3-6

3.4

Releasing Secure Mode

The console cannot be secure for most SRM console commands to run. If the
console is not secure, user mode console commands can be entered. See the
system manager if the system is secure and you do not know the password.

Example 3–2

Releasing/Reestablishing Secure Mode

P00>>> login
Please enter password: xxxx
P00>>>
[User mode SRM console commands are now available.]
P00>>> set secure
The console command login clears secure.
If the password has been forgotten and the system is in secure mode, the procedure for
regaining control is:
1.

Enter the login command

At the please enter password: prompt, press the Halt button and then
press the Return key.

P00>>> login

The password is now cleared and the console is in user mode. A new password must
be set to put the console into secure mode again.
For a full discussion of securing the console, see your system User’s Guide.

Troubleshooting

3-7

3.5

Testing an Entire System

A test command with no modifiers runs all exercisers for subsystems and devices
on the system. I/O devices tested are supported boot devices. The test runs for
10 minutes.

Example 3–3 Sample Test Command
P00>>> test
Console is in diagnostic mode
System test, runtime 600 seconds
Type ^C to stop testing
Configuring system..
polling ncr0 (NCR 53C810) slot 1, bus 0 PCI, hose 1
SCSI Bus ID 7
dka500.5.0.1.1
DKa500
RRD45 1645
polling ncr1 (NCR 53C810) slot 3, bus 0 PCI, hose 1
SCSI Bus ID 7
dkb200.2.0.3.1
DKb200
RZ29B 0007
dkb400.4.0.3.1
DKb400
RZ29B 0007
polling floppy0 (FLOPPY) PCEB - XBUS hose 0
dva0.0.0.1000.0
DVA0
RX23
polling tulip0 (DECchip 21040-AA) slot 2, bus 0 PCI, hose 1
ewa0.0.0.2.1: 08-00-2B-E5-B4-1A
Testing EWA0 network device
Testing VGA (alphanumeric mode only)
Starting background memory test, affinity to all CPUs..
Starting processor/cache thrasher on each CPU..
Starting processor/cache thrasher on each CPU..
Testing SCSI disks (read-only)
No CD/ROM present, skipping embedded SCSI test
Testing other SCSI devices (read-only)..
Testing floppy drive (dva0, read-only)

Troubleshooting

3-8

ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------00003047
memtest memory
1
0
0
134217728
134217728
00003050
memtest memory
205
0
0
213883392
213883392
00003059
memtest memory
192
0
0
200253568
200253568
00003062
memtest memory
192
0
0
200253568
200253568
00003084
memtest memory
80
0
0
82827392
82827392
000030d8
exer_kid dkb200.2.0.3
26
0
0
0
13690880
000030d9
exer_kid dkb400.4.0.3
26
0
0
0
13674496
0000310d
exer_kid dva0.0.0.100
0
0
0
0
0
ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------00003047
memtest memory
1
0
0
432013312
432013312
00003050
memtest memory
635
0
0
664716032
664716032
00003059
memtest memory
619
0
0
647940864
647940864
00003062
memtest memory
620
0
0
648989312
648989312
00003084
memtest memory
263
0
0
274693376
274693376
000030d8
exer_kid dkb200.2.0.3
90
0
0
0
47572992
000030d9
exer_kid dkb400.4.0.3
90
0
0
0
47523840
0000310d
exer_kid dva0.0.0.100
0
0
0
0
327680
ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------00003047
memtest memory
1
0
0
727711744
727711744
00003050
memtest memory
1054
0
0
1104015744
1104015744
00003059
memtest memory
1039
0
0
1088289024
1088289024
00003062
memtest memory
1041
0
0
1090385920
1090385920
00003084
memtest memory
447
0
0
467607808
467607808
000030d8
exer_kid dkb200.2.0.3
155
0
0
0
81488896
000030d9
exer_kid dkb400.4.0.3
155
0
0
0
81472512
0000310d
exer_kid dva0.0.0.100
1
0
0
0
607232
Testing aborted. Shutting down tests.
Please wait..
System test complete
^C
P00>>>

Troubleshooting

3-9

3.5.1 Testing Memory
The test mem command tests individual memory devices or all memory. The test
shown in Example 3–4 runs for 2 minutes.

Example 3–4 Sample Test Memory Command
P00>>> test memory
Console is in diagnostic mode
System test, runtime 120 seconds
Type ^C to stop testing
Starting background memory test, affinity to all CPUs..
Starting memory thrasher on each CPU..
Starting memory thrasher on each CPU..
ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------000046d7
memtest memory
1
0
0
48234496
48234496
000046e0
memtest memory
122
0
0
126862208
126862208
000046e9
memtest memory
111
0
0
115329280
115329280
000046f2
memtest memory
109
0
0
113232384
113232384
000046fb
memtest memory
41
0
0
41937920
41937920
ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------000046d7
memtest memory
1
0
0
226492416
226492416
000046e0
memtest memory
566
0
0
592373120
592373120
000046e9
memtest memory
555
0
0
580840192
580840192
000046f2
memtest memory
554
0
0
579791744
579791744
000046fb
memtest memory
211
0
0
220174080
220174080
ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------000046d7
memtest memory
1
0
0
404750336
404750336
000046e0
memtest memory
1011
0
0
1058932480
1058932480
000046e9
memtest memory
1000
0
0
1047399552
1047399552
000046f2
memtest memory
999
0
0
1046351104
1046351104
000046fb
memtest memory
381
0
0
398410240
398410240

Troubleshooting

3-10

ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------000046d7
memtest memory
1
0
0
583008256
583008256
000046e0
memtest memory
1456
0
0
1525491840
1525491840
000046e9
memtest memory
1446
0
0
1515007360
1515007360
000046f2
memtest memory
1444
0
0
1512910464
1512910464
000046fb
memtest memory
550
0
0
575597952
575597952
ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------000046d7
memtest memory
1
0
0
761266176
761266176
000046e0
memtest memory
1901
0
0
1992051200
1992051200
000046e9
memtest memory
1892
0
0
1982615168
1982615168
000046f2
memtest memory
1889
0
0
1979469824
1979469824
000046fb
memtest memory
720
0
0
753834112
753834112
ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------000046d7
memtest memory
1
0
0
937426944
937426944
000046e0
memtest memory
2346
0
0
2458610560
2458610560
000046e9
memtest memory
2337
0
0
2449174528
2449174528
000046f2
memtest memory
2333
0
0
2444980736
2444980736
000046fb
memtest memory
890
0
0
932070272
932070272
Memory test complete
Test time has expired...
P00>>>

Troubleshooting

3-11

3.5.2 Testing PCI
The test pci command tests PCI buses and devices. The test runs for 2 minutes.

Example 3–5 Sample Test Command for PCI
P00>>> test pci*
Console is in diagnostic mode
System test, runtime 120 seconds
Type ^C to stop testing
Configuring all PCI buses..
polling ncr0 (NCR 53C810) slot 1, bus 0 PCI, hose 1
SCSI Bus ID 7
dka500.5.0.1.1
DKa500
RRD45 1645
polling ncr1 (NCR 53C810) slot 3, bus 0 PCI, hose 1
SCSI Bus ID 7
dkb200.2.0.3.1
DKb200
RZ29B 0007
dkb400.4.0.3.1
DKb400
RZ29B 0007
polling tulip0 (DECchip 21040-AA) slot 2, bus 0 PCI, hose 1
ewa0.0.0.2.1: 08-00-2B-E5-B4-1A
polling floppy0 (FLOPPY) PCEB - XBUS hose 0
dva0.0.0.1000.0
DVA0
RX23
Testing all PCI buses..
Testing EWA0 network device
Testing VGA (alphanumeric mode only)
Testing SCSI disks (read-only)
Testing floppy (dva0, read-only)
ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- -----------00002c29
exer_kid dkb200.2.0.3
27
0
0
0
14642176
00002c2a
exer_kid dkb400.4.0.3
27
0
0
0
14642176
00002c5e
exer_kid dva0.0.0.100
0
0
0
0
0

Troubleshooting

3-12

ID
Program
Device
Pass Hard/Soft Bytes Written Bytes Read
-------- ------------ ------------ ------ --------- ------------- ----------00002c29
exer_kid dkb200.2.0.3
92
0
0
0
48689152
00002c2a
exer_kid dkb400.4.0.3
92
0
0
0
48689152
00002c5e
exer_kid dva0.0.0.100
0
0
0
0
286720
Testing aborted. Shutting down tests.
Please wait..
Testing complete
^C
P00>>>

Troubleshooting

3-13

3.6

Other Useful Console Commands

There are several console commands that help diagnose the system.

The show power command can be used to identify power, temperature, and fan faults.

Example 3–6

Show Power

P00>>> show power
Status
good
good
good
good
good

Power Supply 0
Power Supply 1
System Fans
CPU Fans
Temperature

Current ambient temperature is 20 degrees C
System shutdown temperature is set to 55 degrees C
The system was last reset via a system software reset
0 Environmental events are logged in nvram
The show memory command shows memory DIMMs and their starting addresses.

Example 3–7 Show Memory
P00>>> show memory
Slot
---0
1
2
3
Total

Type
---DIMM
DIMM
DIMM
DIMM

MB
---256
256
256
256

Base
-------0
20000000
40000000
60000000

1.2GB

Troubleshooting

3-14

The show fru command lists all FRUs in the system.

Example 3–8

Show FRU

P00>>> show fru
Digital Equipment Corporation
AlphaServer 1200
Console V5.0-2 OpenVMS PALcode V1.19-12, Digital UNIX
PALcode V1.21-20
Module
Serial #
System Motherboard
NI72000047
Memory 256 MB DIMM
Memory 256 MB DIMM
Memory 256 MB DIMM
Memory 256 MB DIMM
CPU (4MB Cache)
KA705TRVNS
Bridge (IOD0/IOD1)
NI72000047
PCI Motherboard
NI72000047

Part #

Type

Rev

Name

25147-01

0000

mthrbrd0

N/A
N/A
N/A
N/A
B3007-AA

0
0
0
0
3

0000
0000
0000
0000
0000

mem0
mem1
mem2
mem3
cpu0

25147-01

600

0032

iod0/iod1

25147-01

0003

saddle0

Type
Rev
4828086 0005
88115333 0054
141011
0011

Name
pceb0
vga0
tulip0

Bus 0
Slot
1
2
3

iod0 (PCI0)
Option Name
PCEB
S3 Trio64/Trio32
DECchip 21041-AA

Bus 1
Slot

pceb0 (EISA Bridge connected to iod0, slot 1)
Option Name
Type
Rev
Name

Bus 0
Slot
1
4

iod1 (PCI1)
Option Name
NCR 53C810
QLogic ISP1020

Type
Rev
11000
0002
10201077 0005

N/A
N/A
N/A
N/A

Name
ncr0
isp0

Troubleshooting

3-15

Chapter 4
Error Logs
This chapter provides information on troubleshooting with error logs. The following
topics are covered:
•

Using Error Logs

•

Using DECevent

•

Error Log Examples and Analysis

•

Troubleshooting IOD-Detected Errors

•

Double Error Halts and Machine Checks While in PAL Mode

Error registers are described in Chapter 5.

Error Logs

4-1

4.1

Using Error Logs

Error detection is performed by CPUs, the IOD, and the EISA to PCI bus bridge.
(The IOD is the acronym used by software to refer to the system bus to PCI bus
bridge.)

Figure 4-1 Error Detector Placement

Memory
ECC PS
S

CPU Module
X
C
V
R

ECC

CPU Chip
P

System Bus

Tag & Status
Data

ECC
S

Sys/PCI
Bus Bridge
P

Comd/add

B-cache
PS

ECC

Data
System Bus

EISA Bus
Bridge

EISA
VCTY ASIC

Duplicate Tag
Tag & Status

PCI

Parity logic

Parity stored

ECC

ECC logic

ECC
S

ECC stored

PS
PKW0450A-96

Error Logs

4-2

Lines Protected

Device
ECC Protected

System bus data lines

IOD on every transaction,
CPU when using the bus

B-cache

IOD on every transaction,
CPU when using the bus
Parity Protected

System bus command/address lines

IOD on every transaction,
CPU when using the bus

Duplicate tag store

IOD on every transaction,
CPU when using the bus

B-cache index lines

CPU

PCI bus

IOD

EISA bus

EISA bridge

As shown in Figure 4-1 and the accompanying table, the CPU chip is isolated by
transceivers (XVER) from the data and command/address lines on the module. This
allows the CPU chip access to the duplicate tag and B-cache while the system bus is in
use. The CPU detects errors only when it is the consumer of the data. The IOD
detects errors on each system bus cycle regardless of whether it is involved in the
transaction.
System bus errors detected by the CPU may also be detected by the IOD. It is
necessary to check the IOD for errors any time there is a CPU machine check.
•

If the CPU sees bad data and the IOD does not, the CPU is at fault.

•

If both the CPU and the IOD see bad data on the system bus, either memory or a
secondary CPU is the cause. In such a case, the Dirty bit, bit<20>, in the IOD
MC_ERR1 Register should be set or clear. If the Dirty bit is set, the source of the
data is a CPU’s cache destined for a different CPU. If the Dirty bit is not set,
memory caused the bad data on the bus. In this case, multiple error log entries
occur and must be analyzed together to determine the cause of the error.

Error Logs

4-3

4.1.1 Hard Errors
There are two categories of hard errors:
•

System-independent errors detected by the CPU. These errors are processor
machine checks handled as MCHK 670 interrupts and are:
Internal EV5 or EV56 cache errors
CPU B-cache module errors

•

System-dependent errors detected by both the CPU and IOD. These errors are
system machine checks handled as MCHK 660 interrupts and are:
CPU-detected external reference errors
IOD hard error interrupts

The IOD can detect hard errors on either side of the bridge.

4.1.2 Soft Errors
There are two categories of soft errors:
•

System-independent errors detected and corrected by the CPU. These errors are
CPU module correctable errors handled as MCHK 630 interrupts.

•

System-dependent errors that are correctable single-bit errors on the system bus
and are handled as MCHK 620 interrupts.

Error Logs

4-4

4.1.3 Error Log Events
Several different events are logged by OpenVMS and DIGITAL UNIX. Windows NT
does not log errors in this fashion.

Table 4-1 Types of Error Log Events
Error Log Event

Description

MCHK 670

Processor machine checks. These are synchronous
errors that inform precisely what happened at the time
the error occurred. They are detected inside the CPU
chip and are fatal errors.

MCHK 660

System machine checks. These are asynchronous
errors that are recorded after the error has occurred.
Data on exactly what was going on in the machine at
the time of the error may not be known. They are fatal
errors.

MCHK 630

Processor correctable errors

MCHK 620

System correctable errors

Last fail

Used to collect system bus registers prior to crashing

I/O error interrupt

IOD error interrupts

System environment

Used to provide status on power, fans, and temperature

Configuration

Used to provide system configuration information

Error Logs

4-5

4.2

Using DECevent

DECevent produces bit-to-text ASCII reports derived from system event entries
or user-supplied event logs. The format of the reports is determined by
commands, qualifiers, parameters, and keywords appended to the comand. The
maximum command line length is 255 characters.

DECevent allows you to do the following:
•

Translate event log files into readable reports

•

Select alternate input and output files

•

Filter input events

•

Select alternative reports

•

Translate events as they occur

•

Maintain and customize your environment with the interactive shell commands

To access on-line help:
OpenVMS
$ HELP DIAGNOSE or
$ DIA /INTERACTIVE
DIA> HELP
DIGITAL UNIX
> man dia
> dia hlp

Privileges necessary to use DECevent:
•

SYSPRV for the utility

•

DIAGNOSE to use the /CONTINUOUS qualifier

Error Logs

4-6

4.2.1 Translating Event Files
To produce a translated event report using the default event log file,
SYS$ERRORLOG:ERRLOG.SYS, enter the following command:
OpenVMS
$ DIAGNOSE
DIGITAL UNIX
> dia -a
The DIAGNOSE command allows DECevent to use built-in defaults. This command
produces a full report, directed to the terminal screen, from the input event file,
SYS$ERRORLOG:ERRLOG.SYS. The /TRANSLATE qualifier is understood on the
command line.
To select an alternate input file
OpenVMS
$ DIAGNOSE ERRORLOG.OLD
DIGITAL UNIX
> dia -a -f syserr-old.hostname
These commands select an alternate input file (ERRORLOG.OLD or syserr-old) as the
event log to translate. The file name can contain the directory or path, if needed.
Wildcard characters can be used.
To send reports to an output file
OpenVMS
$ DIAGNOSE/OUTPUT=ERRLOG_OLD.TXT
DIGITAL UNIX
> dia -a > syserr-old.txt
These commands direct the output of DECevent to ERRLOG_OLD.TXT or
syserr -old.txt.

Error Logs

4-7

To reverse the order of the input events
OpenVMS
$ DIAGNOSE/TRANSLATE/REVERSE
DIGITAL UNIX
> dia -R
These commands reverse the order in which events are displayed. The default order is
forward chronologically.

4.2.2 Filtering Events
/INCLUDE and /EXCLUDE qualifiers allow you to filter input event log files.
The /INCLUDE qualifier is used to create output for devices named in the command.
OpenVMS
$ DIAGNOSE/TRANSLATE/INCLUDE=(DISK=RZ,DISK=RA92,CPU)
DIGITAL UNIX
> dia -i disk=rz disk=ra92 cpu
The commands shown here create output using only the entries for RZ disks, RA92
disks, and CPUs.
The /EXCLUDE qualifier is used to create output for all devices except those named
in the command.
OpenVMS
$ DIAGNOSE/TRANSLATE/EXCLUDE=(MEMORY)
DIGITAL UNIX
> dia -x mem

Error Logs

4-8

Use the /BEFORE and /SINCE qualifiers to select events before or after a certain
date and time.
OpenVMS
$ DIAGNOSE/TRANSLATE/BEFORE=15-JAN-1997:10:30:00
or
$ DIAGNOSE/TRANSLATE/SINCE=15-JAN-1997:10:30:00
DIGITAL UNIX
> dia -t s:15-jan-1997 e:20-jan-1997
If no time is specified, the default time is 00:00:00, and all events for that day are
selected.
The /BEFORE and /SINCE qualifiers can be combined to select a certain period of
time.
OpenVMS
$ DIAGNOSE/TRANSLATE/SINCE=15-JAN-1997/BEFORE=20-JAN-1997
If no value is supplied with the /SINCE or /BEFORE qualifiers, DECevent defaults
to TODAY.

Error Logs

4-9

4.2.3 Selecting Alternative Reports
Table 4-2 describes the DECevent report formats. Report formats are mutually
exclusive. No combinations are allowed. The default format is /Full.

Table 4-2 DECevent Report Formats
Format

Description

/Full

Translates all available information for each event

/Brief

Translates key information for each event

/Terse

Provides binary event information and displays register values
and other ASCII messages in a condensed format

/Summary

Produces a statistical summary of the events in the log

/Fsterr

Produces a one-line-per-entry report for disk and tape devices

The syntax is:
OpenVMS
$ DIAGNOSE/TRANSLATE/<format>
DIGITAL UNIX
> dia -o <format>

Error Logs

4-10

4.3

Error Log Examples and Analysis

The following sections provide examples and analysis of error logs.

4.3.1 MCHK 670 CPU-Detected Failure
The error log in Example 4–1 shows the following:

➊
➋

CPU1 logged the error in a system with two CPUs.

➌

Neither IOD CAP Error Register saw an error.

During a D-ref fill, the External Interface Status Register logged an
uncorrectable EEC error. (When a CPU chip does not find data it needs to
perform a task in any of its caches, it requests data from off the chip to fill its
D-caches. It performs a “D-ref fill.”) Bit<30> is clear, indicating that the
source of the error is the B-cache.

The error was detected by a CPU and the data was not on the system bus. Otherwise,
the IODs would have seen the error. Therefore, CPU1 is broken.
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “MC” bus is the system bus.
Refer to Table 4-9 for information on decoding commands, and refer to Table 4-10 for
information on node IDs.

Error Logs

4-11

Example 4–1 MCHK 670
Logging OS
System Architecture
Event sequence number
Timestamp of occurrence
Host name

2. DIGITAL UNIX
2. Alpha
4.
04-APR-1997 17:20:04
whip16

System type register
x00000016
Number of CPUs (mpnum)
x00000002
CPU logging event (mperr) x00000001

AlphaServer 4000/1200 Series

➊

Event validity
Event severity
Entry type

1. O/S claims event is valid
1. Severe Priority
100. CPU Machine Check Errors

CPU Minor class

1. Machine check (670 entry)

Software Flags

x0000000300000000
IOD 1 Register Subpkt Pres
IOD 2 Register Subpkt Pres
x00000003
x00000000
C1563

Active CPUs
Hardware Rev
System Serial Number
Module Serial Number
Module Type
System Revision
* MCHK 670 Regs *
Flags:
PCI Mask
Machine Check Reason
PAL SHADOW REG 0
PAL SHADOW REG 1
.
.
.
PAL SHADOW REG 6
PAL SHADOW REG 7
PALTEMP0
PALTEMP1
PALTEMP2
.
.
.
PALTEMP22
PALTEMP23
Exception Address Reg
Exception Summary Reg
Exception Mask Reg
PAL BASE
Interrupt Summary Reg
IBOX Ctrl and Status Reg

x0000
x00000000
x00000000
x0000
x0098
x00000000
x00000000

x00000000
x00000000
x00000000E87C7A58
xFFFFFFFE8F658000
xFFFFFC00003C9F40

xFFFFFC00004F9D60
x00000000E8709A58
xFFFFFC00003BFB88
Native-mode instruction
Exception PC x3FFFFF00000EFEE2
x00000000
x00000000
x00000000020000
Base addr for palcode = x0000000008
x00000000
AST requests 3 - 0 x00000000
x000000C160000000
Timeout Bit Not Set
PAL Shadow Registers Enabled
Correctable Err Intrpts Enabled
ICACHE BIST Successful
TEST_STATUS_H Pin Asserted

Error Logs

4-12

Icache Par Err Stat Reg
Dcache Par Err Stat Reg
Virtual Address Reg
Memory Mgmt Flt Sts Reg

x00000000
x00000000
xFFFFFFFE8F63BD38
x000000000166D1
Ref which caused err was a write
Ref resulted in DTB miss
RA Field x0000000000001B
Opcode Field
x0000000000002C
Scache Address Reg
xFFFFFF00000254BF
Scache Status Reg
x00000000
Bcache Tag Address Reg
xFFFFFF80E98F7FFF
External cache hit
Parity for ds and v bits
Cache block dirty
Cache block valid
Ext cache tag addr parity bit
Tag address<38:20> is
x00000000000E98
Ext Interface Address Reg xFFFFFF00E984DBCF
Fill Syndrome Reg
x0000000000002B
Ext Interface Status Reg xFFFFFFF104FFFFFF
➋
Uncorrectable ECC error
Error occurred during D-ref fill
LD LOCK
xFFFFFF003797340F
** IOD SUBPACKET -> **
WHOAMI

IOD 0 Register Subpacket
Device ID x0000003B
Bcache Size = 2MB
VCTY ASIC Rev = 0
Module Revision 0.
Base Address of Bridge
x000000F9E0000000
Dev Type & Rev Register
x06008021 CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
MC-PCI Command Register
x46480FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE PCI Arbitration: Round Robin
Memory Host Addr Exten
x00000000
IO Host Addr Extension
x00000000
Interrupt Control
x00000003 MC-PCI Intr Enabled
Device intr info enabled if en_int=
1
Interrupt Request
x00000000 Interrupts asserted x00000000
Interrupt Mask Register 0 x00C50010
Interrupt Mask Register 1 x00000000
MC Error Info Register 0 xE0000000 MC bus trans addr <31:4> x0E000000
MC Error Info Register 1 x000E88FD MC bus trans addr <39:32>x000000FD
MC_Command x00000008
Device Id x0000003A
CAP Error Register
x00000000
(no error seen)
➌
PCI Bus Trans Error Adr
x00000000
x000000BB

Error Logs

4-13

MDPA Status Register
MDPA Error Syndrome Reg

x00000000
x00000000

MDPB Status Register
MDPB Error Syndrome Reg

x00000000
x00000000

** IOD SUBPACKET -> **
WHOAMI

x000000BB

MDPA Chip Revision x00000000
Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000
MDPB Chip Revision x00000000
Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000

IOD 1 Register Subpacket
Device ID x0000003B
Bcache Size = 2MB
VCTY ASIC Rev = 0
Module Revision 0.
Base Address of Bridge
x000000FBE0000000
Dev Type & Rev Register
x06008021 CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
MC-PCI Command Register
x46480FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE PCI Arbitration: Round Robin
Memory Host Addr Exten
x00000000
IO Host Addr Extension
x00000000
Interrupt Control
x00000003 MC-PCI Intr Enabled
Device intr info enabled if en_int
= 1
Interrupt Request
x00000000 Interrupts asserted x00000000
Interrupt Mask Register 0 x00C50001
Interrupt Mask Register 1 x00000000
MC Error Info Register 0 xE0000000 MC bus trans addr <31:4> x0E000000
MC Error Info Register 1 x000E88FD MC bus trans addr <39:32> x000000FD
MC_Command x00000008
Device Id x0000003A
CAP Error Register
x00000000
(no error seen)
➌
PCI Bus Trans Error Adr
xC0018B48
MDPA Status Register
x00000000 MDPA Chip Revision x00000000
MDPA Error Syndrome Reg
x00000000 Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000
MDPB Status Register
x00000000 MDPB Chip Revision x00000000
MDPB Error Syndrome Reg
x00000000 Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000
PALcode Revision
Palcode Rev: 1.21-3

Error Logs

4-14

4.3.2 MCHK 670 CPU and IOD-Detected Failure
The error log in Example 4–2 shows the following:

➊
➋

CPU1 logged the error in a system with two CPUs.

➌
➍
➎
➏

Both IOD CAP Error Registers logged an error.

The External Interface Status Register logged an uncorrectable ECC error
during a D-ref fill. (When a CPU chip does not find data it needs to perform a
task in any of its caches, it requests data from off the chip to fill its D-cache. It
performs a “D-ref fill.”) Bit <30> is set, indicating that the source of the error
is memory or the system. Bits <32> and <35> are set, indicating an
uncorrectable ECC error and a second external interface hard error,
respectively.

The command at the time of the error was a read.
The bus master at the time of the error was CPU1.

The Dirty bit, bit <20> in the MC_ERR1 Register is clear, indicating the data is
clean and comes from memory.
The error was detected by a CPU, and the data was on the system bus and is clean.
Therefore, a memory module provided the wrong data. (If the Dirty bit had been set,
the data would have come from the cache of another CPU.) To determine which
memory, see Section 4.4.
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “MC” bus is the system bus.
Refer to Table 4-9 for information on decoding commands, and refer to Table 4-10 for
information on node IDs.

Error Logs

4-15

Example 4–2 MCHK 670 CPU and IOD-Detected Failure
Logging OS
System Architecture
Event sequence number
Timestamp of occurrence
Host name

2. DIGITAL UNIX
2. Alpha
6.
08-APR-1997 11:27:55
whip16

System type register
x00000016
Number of CPUs (mpnum)
x00000002
CPU logging event (mperr) x00000001

AlphaServer 4000/1200 Series

➊

Event validity
Event severity
Entry type

1. O/S claims event is valid
1. Severe Priority
100. CPU Machine Check Errors

CPU Minor class

1. Machine check (670 entry)

Software Flags

x0000000300000000
IOD 1 Register Subpkt Pres
IOD 2 Register Subpkt Pres
x00000002
x00000000
C1563

Active CPUs
Hardware Rev
System Serial Number
Module Serial Number
Module Type
System Revision
* MCHK 670 Regs *
Flags:
PCI Mask
Machine Check Reason
PAL SHADOW REG 0
PAL SHADOW REG 1
.
.
.
PAL SHADOW REG 6
PAL SHADOW REG 7
PALTEMP0
PALTEMP1
.
.
.
PALTEMP23
Exception Address Reg
Exception Summary Reg
Exception Mask Reg
PAL BASE
Interrupt Summary Reg
IBOX Ctrl and Status Reg

Icache Par Err Stat Reg
Dcache Par Err Stat Reg

x0000
x00000000
x00000000
x0000
x0098
x00000000
x00000000

x00000000
x00000000
x00000001401A7A90
x00000000000021

x00000000ECE77A58
x000000012005A8B4
Native-mode instruction
Exception PC x0000000048016A2D
x00000000
x00000000
x00000000020000
Base addr for palcode = x0000000008
x00000000
AST requests 3 - 0 x00000000
x000000C164000000
Timeout Bit Not Set
Floating Point Instr. may be issued
PAL Shadow Registers Enabled
Correctable Err Intrpts Enabled
ICACHE BIST Successful
TEST_STATUS_H Pin Asserted
x00000000
x00000000

Error Logs

4-16

Virtual Address Reg
Memory Mgmt Flt Sts Reg

x00000001407D6000
x00000000011A10
Ref resulted in DTB miss
RA Field x0000000008

Opcode Field
x00000000000023
xFFFFFF00000254BF
x00000000
xFFFFFF80286F7FFF
External cache hit
Parity for ds and v bits
Cache block dirty
Cache block valid
Ext cache tag addr parity bit
Tag address<38:20> is
x00000000000286
Ext Interface Address Reg xFFFFFF0028681A8F
Fill Syndrome Reg
x00000000004B00
Ext Interface Status Reg xFFFFFFF984FFFFFF
➋
Uncorrectable ECC error
Error occurred during D-ref fill
Second external interface hard
error
LD LOCK
xFFFFFF000020040F
Scache Address Reg
Scache Status Reg
Bcache Tag Address Reg

** IOD SUBPACKET -> **
WHOAMI

IOD 0 Register Subpacket
Device ID x0000003F
Bcache Size = 2MB
VCTY ASIC Rev = 0
Module Revision 0.
Base Address of Bridge
x000000F9E0000000
Dev Type & Rev Register
x06008021 CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
MC-PCI Command Register
x46480FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE PCI Arbitration: Round Robin
Memory Host Addr Exten
x00000000
IO Host Addr Extension
x00000000
Interrupt Control
x00000003 MC-PCI Intr Enabled
Device intr info enabled if en_int
= 1
Interrupt Request
x00810000 Interrupts asserted x00010000
Hard Error
Interrupt Mask Register 0 x00C50010
Interrupt Mask Register 1 x00000000
MC Error Info Register 0 x28681A80 MC bus trans addr <31:4> x028681A8 ➏
MC Error Info Register 1 x800ED800 MC bus trans addr <39:32> x00000000
➍
MC_Command x00000018
x000000BF

Device Id x0000003B

➎
Error Logs

4-17

CAP Error Register
PCI Bus Trans Error Adr
MDPA Status Register
MDPA Error Syndrome Reg

MDPB Status Register

MC error info valid
xC0000000 Uncorrectable ECC err det by MDPB
➌
MC error info latched
x000003FD
x00000000 MDPA Chip Revision x00000000
x00000000 Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000
x00000000 MDPB Chip Revision x00000000
MPDB Error Syndrome of
uncorrectable read error

MDPB Error Syndrome Reg

x00000000

** IOD SUBPACKET -> **
WHOAMI

x000000BF

Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000

IOD 1 Register Subpacket
Device ID x0000003F
Bcache Size = 2MB
VCTY ASIC Rev = 0
Module Revision 0.
Base Address of Bridge
x000000FBE0000000
Dev Type & Rev Register
x06008021 CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
MC-PCI Command Register
x46480FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE PCI Arbitration: Round Robin
Memory Host Addr Exten
x00000000
IO Host Addr Extension
x00000000
Interrupt Control
x00000003 MC-PCI Intr Enabled
Device intr info enabled if en_int
= 1
Interrupt Request
x00800000 Interrupts asserted x00000000
Hard Error
Interrupt Mask Register 0 x00C50001
Interrupt Mask Register 1 x00000000
MC Error Info Register 0 x28681A80 MC bus trans addr <31:4> x028681A8 ➏
MC Error Info Register 1 x800FD800 MC bus trans addr <39:32> x00000000
➍
MC_Command x00000018

CAP Error Register
PCI Bus Trans Error Adr
MDPA Status Register
MDPA Error Syndrome Reg

Device Id x0000003B
➎
MC error info valid
xC0000000 Uncorrectable ECC err det by MDPB
MC error info latched
x00000000
x00000000 MDPA Chip Revision x00000000
x00000000 Cycle 0 ECC Syndrome x00000000

Error Logs

➌

4-18

MDPB Status Register

x00000000

MDPB Error Syndrome Reg

x00000000

PALcode Revision

Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000
MDPB Chip Revision x00000000
MPDB Error Syndrome of
uncorrectable read error
Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000
Palcode Rev: 1.21-3

Error Logs

4-19

4.3.3 MCHK 670 Read Dirty CPU-Detected Failure
The error log in Example 4–3 shows the following:

➊
➋

CPU0 logged the error in a system with two CPUs.

➌
➍
➎
➏
➐
➑

Both IOD CAP Error Registers logged an error.

The External Interface Status Register records an uncorrectable ECC error from
the system (bit <30> set).

The MC Error Info Registers 0 and 1 have captured the error information.
The commander at the time of the error was CPU0 (known from MC_ERR1).
The command on the bus at the time was a read memory command.
The address read was a memory address, not an I/O address.

The data associated with the read was dirty.
From this information you know CPU0 requested data that was dirty; therefore,
memory did not provide it, nor did an I/O device. Only another CPU could have
provided the data from its cache. There is only one other CPU in this system, and it is
faulty. See Section 4.4 for a procedure designed to help with IOD-detected errors.
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “MC” bus is the system bus.
Refer to Table 4-9 for information on decoding commands, and refer to Table 4-10 for
information on node IDs.

Error Logs

4-20

Example 4–3 MCHK 670 Read Dirty Failure
Logging OS
System Architecture
Event sequence number
Timestamp of occurrence
Host name

2. DIGITAL UNIX
2. Alpha
4.
08-APR-1997 10:20:37
sect06

System type register
x00000016 AlphaServer 4000/1200 Series
Number of CPUs (mpnum)
x00000002
➊
CPU logging event (mperr) x00000000
Event validity
Event severity
Entry type

1. O/S claims event is valid
1. Severe Priority
100. CPU Machine Check Errors

CPU Minor class

1. Machine check (670 entry)

Software Flags

x0000000300000000
IOD 0 Register Subpkt Pres
IOD 1 Register Subpkt Pres
x00000003
x00000000
C1563

Active CPUs
Hardware Rev
System Serial Number
Module Serial Number
Module Type
System Revision
* MCHK 670 Regs *
Flags:
PCI Mask
Machine Check Reason
PAL SHADOW REG 0
PAL SHADOW REG 1
PAL SHADOW REG 2
PAL SHADOW REG 3
PAL SHADOW REG 4
PAL SHADOW REG 5
PAL SHADOW REG 6
PAL SHADOW REG 7
PALTEMP0
PALTEMP1
PALTEMP2
.
.
.
PALTEMP22
PALTEMP23
Exception Address Reg
Exception Summary Reg
Exception Mask Reg
PAL Base Address Reg
Interrupt Summary Reg
IBOX Ctrl and Status Reg

x0000
x00000000
x00000000
x0000
x0098 Fatal Alpha Chip Detected HardError
x0000000000000000
x0000000000000000
x0000000000000000
x0000000000000000
x0000000000000000
x0000000000000000
x0000000000000000
x0000000000000000
xFFFFFC00006C00C0
x00000000000061A8
xFFFFFC00004E1E00

xFFFFFC00006530E0
x0000000003D2BA58
xFFFFFC000047395C
Native-mode Instruction
Exception PC x3FFFFF000011CE57
x0000000000000000
x0000000000000000
x0000000000020000
Bse Addr for PALcode: = x0000000000000008
x0000000000200000
External HW Interrupt at IPL21
AST Requests 3-0: x0000000000000000
x000000C160000000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.

Error Logs

4-21

Icache Par Err Stat Reg
Dcache Par Err Stat Reg
Virtual Address Reg
Memory Mgmt Flt Sts Reg

Floating Point Instructions will
cause FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts
Enabled.
ICACHE BIST (Self Test) Was
Successful.
TEST_STATUS_H Pin Asserted
x0000000000000000
x0000000000000000
x0000000000044000
x0000000000005D10
If Err, Reference Resulted in DTB
Miss
Fault Inst RA Field: x0000000000000014

Fault Inst Opcode: x000000000000000B
xFFFFFF00000254BF
x0000000000000000
xFFFFFF8007EE2FFF
Last Bcache Access Resulted in a
Miss.
Value of Parity Bit for Tag Control
Status
Bits Dirty, Shared & Valid is Set.
Value of Tag Control Dirty Bit is
Clear.
Value of Tag Control Shared Bit is
Clear.
Value of Tag Control Valid Bit is
Clear.
Value of Parity Bit Covering Tag
Store ddress Bits is Set.
Tag Address<38:20> Is: x000000000000007E
Ext Interface Address Reg xFFFFFF0007FBF08F
Fill Syndrome Reg
x000000000000D189
Ext Interface Status Reg xFFFFFFF944FFFFFF
➋
Error Source is Memory or System
UNCORRECTABLE ECC ERROR
Error Occurred During D-ref Fill
Error
LD LOCK
xFFFFFF0007FBF00F
Scache Address Reg
Scache Status Reg
Bcache Tag Address Reg

** IOD SUBPACKET -> **

IOD 0 Register Subpacket

WHOAMI

x000000BA

Base Address of Bridge
Dev Type & Rev Register

x000000F9E0000000
x06008021 CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
x06480FF1 Module SelfTest Passed LED on
Delayed PCI Bus Reads Protocol:
Enabled
Bridge to PCI Transactions: Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check: Enabled
MC Bus CMD/Addr Parity Check: Enabled
MC Bus NXM Check: Enabled

MC-PCI Command Register

Module Revision 0.
VCTY ASIC Rev = 0
Bcache Size = 2MB
MID 2.
GID 7.

Error Logs

4-22

Mem Host Address Ext Reg
IO Host Adr Ext Register
Interrupt Ctrl Register
Interrupt Request
Interrupt Mask0 Register
Interrupt Mask1 Register
MC Error Info Register 0
MC Error Info Register 1

Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE Arbitration: MC-PCI Priority Mode
x00000000 HAE Sparse Mem Adr<31:27> x00000000
x00000000 PCI Upper Adr Bits<31:25> x00000000
x00000003 Write Device Interrupt Info Struct:Enabled
x00800000 Interrupts asserted x00000000
Hard Error
x00C50010
x00000000
x07FBF080
MC Bus Trans Addr<31:4>: 7FBF080

x801E8800

➐
➏
Device ID 2 x00000002
➎
MC bus error assoc w read/dirty➑

MC bus trans addr <39:32> x00000000

MC Command is Read0-Mem

MC error info valid
CAP Error Register

xE0000000

Uncorrectable ECC err det by MDPA

➌

Uncorrectable ECC err det by MDPB
MC error info latched
➍
Sys Environmental Regs
PCI Bus Trans Error Adr
MDPA Status Register
MDPA Error Syndrome Reg
MDPB Status Register
MDPB Error Syndrome Reg

x00000000
x00000000
x00000000
x00000000
x00000000
x000D00D0

** IOD SUBPACKET -> **

MDPA Status Register Data Not Valid
MDPA Syndrome Register Data Not Valid
MDPB Status Register Data Not Valid
MDPB Syndrome Register Data Not Valid
IOD 1 Register Subpacket

WHOAMI

x000000BA

Base Address of Bridge
Dev Type & Rev Register

x000000FBE0000000
x06008021 CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
x06480FF1 Module SelfTest Passed LED on
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions: Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check: Enabled
MC Bus CMD/Addr Parity Check: Enabled
MC Bus NXM Check: Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE Arbitration: MC-PCI Priority Mode
x00000000 HAE Sparse Mem Adr<31:27> x00000000
x00000000 PCI Upper Adr Bits<31:25> x00000000

MC-PCI Command Register

Mem Host Address Ext Reg
IO Host Adr Ext Register

Module Revision 0.
VCTY ASIC Rev = 0
Bcache Size = 2MB
MID 2.
GID 7.

Error Logs

4-23

Interrupt Ctrl Register
Interrupt Request

x00000003
x00800001

Interrupt Mask0 Register
Interrupt Mask1 Register

x00C50001
x00000000

MC Error Info Register 0

x07FBF080

MC Error Info Register 1

x801E8800

Write Device Interrupt Info Struct:Enabled
Interrupts asserted x00000001
Hard Error

➐

MC Bus Trans Addr<31:4>: 7FBF080
MC bus trans addr <39:32> x00000000
MC Command is Read0-Mem
Device ID 2

x00000002

MC bus error assoc w read/dirty
MC error info valid
CAP Error Register
xE0000000
Uncorrectable ECC err det by MDPB

Sys Environmental Regs
PCI Bus Trans Error Adr
MDPA Status Register
MDPA Error Syndrome Reg
MDPB Status Register
MDPB Error Syndrome Reg
PALcode Revision

x00000000
x00000000
x00000000
x00000000
x00000000
x000D00D0

➏
➎
➑

Uncorrectable ECC err det by MDPA

➌

MC error info latched

➍

MDPA Status Register Data Not Valid
MDPA Syndrome Register Data Not Valid
MDPB Status Register Data Not Valid
MDPB Syndrome Register Data Not Valid
Palcode Rev: 1.21-3

Error Logs

4-24

4.3.4 MCHK 660 IOD-Detected Failure (System Bus Error)
The error log in Example 4–4 shows the following:

➊
➋
➌
➍
➎
➏

CPU0 logged the error in a system with two CPUs.
The External Interface Status Register does not record an error.
Both IOD CAP Error Registers logged an error.
The MC Error Info Registers 0 and 1 captured the error information.
The commander at the time of the error was CPU1 (known from MC_ERR1).

The command on the bus at the time was a write-back memory command.
Since this is an MCHK 660, the IOD detected the error on the bus, and CPU0 is
logging the error. CPU0 registers are not important in this case since it is servicing the
IOD interrupt. There are three devices that can put data on the system bus: CPUs,
memory, or an IOD. From MC_ERR Register 1 we know that at the time of the error
CPU1 put bad data on the bus while writing to memory. See Section 4.4 for a
procedure designed to help with IOD-detected errors.
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “MC” bus is the system bus.
Refer to Table 4-9 for information on decoding commands, and refer to Table 4-10 for
information on node IDs.

Error Logs

4-25

Example 4–4 MCHK 660 IOD-Detected Failure (System Bus Error)
Logging OS
System Architecture
Event sequence number
Timestamp of occurrence
Host name

2. DIGITAL UNIX
2. Alpha
6.
04-APR-1996 17:20:04
whip16

System type register
x00000016 AlphaServer 4000/1200 Series
Number of CPUs (mpnum)
x00000002
➊
CPU logging event (mperr) x00000000
Event validity
1. O/S claims event is valid
Event severity
1. Severe Priority
Entry type
100. CPU Machine Check Errors
CPU Minor class
Software Flags
Active CPUs
Hardware Rev
System Serial Number
Module Serial Number
Module Type
System Revision
* MCHK 660 Regs *
Flags:
PCI Mask
Machine Check Reason
PAL SHADOW REG 0
.
.
PAL SHADOW REG 7
PALTEMP0
.
.
PALTEMP23
Exception Address Reg
Exception Summary Reg
Exception Mask Reg
PAL BASE
Interrupt Summary Reg
IBOX Ctrl and Status Reg

Icache Par Err Stat Reg
Dcache Par Err Stat Reg
Virtual Address Reg
Memory Mgmt Flt Sts Reg

2. 660 Entry
x0000000300000000
IOD 1 Register Subpkt Pres
IOD 2 Register Subpkt Pres
x00000003
x00000000
C1563
x0000
x00000000
x00000000
x0000
x0202
x00000000
x00000000
x0000000007
x00000000047FDA58
xFFFFFC000038D784
Native-mode instruction
Exception PC x3FFFFF00000E35E1
x00000000
x00000000
x00000000020000
Base addr for palcode = x0000000008
x00000000200000
EXT. HW interrupt at IPL21
AST requests 3 - 0 x00000000
x000000C160000000
Timeout Bit Not Set
PAL Shadow Registers Enabled
Correctable Err Intrpts Enabled
ICACHE BIST Successful
TEST_STATUS_H Pin Asserted
x00000000
x00000000
xFFFFFFFFFF800130
x00000000014990
Ref resulted in DTB miss
RA Field x0000000006

Error Logs

4-26

Opcode Field
x00000000000029
xFFFFFF0000024EAF
x00000000
xFFFFFF80FFED6FFF
Parity for ds and v bits
Cache block dirty
Cache block valid
Tag address<38:20> is
x00000000000FFE
Ext Interface Address Reg xFFFFFF00FC00000F
Fill Syndrome Reg
x0000000000C5D2
Ext Interface Status Reg xFFFFFFF004FFFFFF
Error occurred during D-ref fill ➋
LD LOCK
xFFFFFF000020065F
Scache Address Reg
Scache Status Reg
Bcache Tag Address Reg

** IOD SUBPACKET -> **
WHOAMI

IOD 0 Register Subpacket
Device ID x0000003A
Bcache Size = 2MB
VCTY ASIC Rev = 0
Module Revision 0.
Base Address of Bridge
x000000F9E0000000
Dev Type & Rev Register
x06008021 CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
MC-PCI Command Register
x46480FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE PCI Arbitration: Round Robin
Memory Host Addr Exten
x00000000
IO Host Addr Extension
x00000000
Interrupt Control
x00000003 MC-PCI Intr Enabled
Device intr info enabled if en_int
= 1
Interrupt Request
x00800000 Interrupts asserted x00000000
Hard Error
Interrupt Mask Register 0 x00C50010
Interrupt Mask Register 1 x00000000
MC Error Info Register 0 x4A26DBF0 MC bus trans addr <31:4> x04A26DBF
MC Error Info Register 1 x800ED600 MC bus trans addr <39:32> x00000000
MC_Command x00000016
➏
x000000BA

Device Id x0000003B
MC error info valid
CAP Error Register

xA0000000

Uncorrectable ECC err det by MDPA

MC error info latched
PCI Bus Trans Error Adr
MDPA Status Register

x00000000
x80000000

MDPA Error Syndrome Reg

x1E00001E

➎
➌
➍

MDPA Chip Revision x00000000
MDPA Error Syndrome of
uncorrectable read error
Cycle 0 ECC Syndrome x0000000000001E
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000

Error Logs

4-27

MDPB Status Register
MDPB Error Syndrome Reg

x00000000
x00000000

** IOD SUBPACKET -> **
WHOAMI

x000000BA

Cycle 3 ECC Syndrome x0000000000001E
MDPB Chip Revision x00000000
Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000

IOD 1 Register Subpacket
Device ID x0000003A
Bcache Size = 2MB
VCTY ASIC Rev = 0
Module Revision 0.
Base Address of Bridge
x000000FBE0000000
Dev Type & Rev Register
x06008021 CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
MC-PCI Command Register
x46480FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE PCI Arbitration: Round Robin
Memory Host Addr Exten
x00000000
IO Host Addr Extension
x00000000
Interrupt Control
x00000003 MC-PCI Intr Enabled
Device intr info enabled if en_int
= 1
Interrupt Request
x00800000 Interrupts asserted x00000000
Hard Error
Interrupt Mask Register 0 x00C50001
Interrupt Mask Register 1 x00000000
MC Error Info Register 0 x4A26DBF0 MC bus trans addr <31:4> x04A26DBF
MC Error Info Register 1 x800ED600 MC bus trans addr <39:32> x00000000
MC_Command x00000016
➏

➎

Device Id x0000003B
MC error info valid
CAP Error Register

xA0000000

Uncorrectable ECC err det by MDPA

MC error info latched
PCI Bus Trans Error Adr
MDPA Status Register

x00000000
x80000000

MDPA Error Syndrome Reg

x1E00001E

MDPB Status Register
MDPB Error Syndrome Reg

x00000000
x00000000

PALcode Revision

➌

➍

MDPA Chip Revision x00000000
MDPA Error Syndrome of
uncorrectable read error
Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000
MDPB Chip Revision x00000000
Cycle 0 ECC Syndrome x00000000
Cycle 1 ECC Syndrome x00000000
Cycle 2 ECC Syndrome x00000000
Cycle 3 ECC Syndrome x00000000
Palcode Rev: 1.21-3

Error Logs

4-28

4.3.5 MCHK 660 IOD-Detected Failure (PCI Error)
The error log in Example 4–5 shows the following:

➊
➋

CPU 0 logged the error in a system with two CPUs.

➌

The External Interface Status Register records that the error occurred during a
D-ref Fill but does not indicate what the error is.

➍
➎
➏

The CAP Error Register for IOD0 did not see an error.

➐

There is a PCI Subpacket from PCI1 with four nodes on it. Two devices on the
PCI bus did not see an error, however two did, the Mylex DAC960 and the
DEC_KZPSA. Either device could have caused the parity error.

The MCHK 660 register gives the reason for the machine check as an IODdetected hard error or a Dtag Parity Error (if cached CPU)

The CAP Error Register for IOD1, however, records a serious PCI error.
The MC Error Info Registers 0 and 1 are not valid since the valid bit, <31> is
not set. Exactly what was happening at the time of the error is not known.

Since this is an MCHK 660, the IOD detected the error on the bus, and CPU0 is
logging the error. CPU0 registers are not important in this case since it is servicing the
IOD interrupt. There are three devices that can put data on the system bus: CPUs,
memory, or an IOD. The CAP Error Register for IOD1 saw a serious error and the
MC Error Info Register was not able to captured error information. The presence of
PCI Subpackets informs the diagnosis summarized by ➐.
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “MC” bus is the system bus.
Refer to Table 4-9 for information on decoding commands, and refer to Table 4-10 for
information on node IDs.

Error Logs

4-29

Example 4–5 MCHK 660 IOD-Detected Failure (PCI Error)
Timestamp of occurrence
Host name

19-AUG-1997 12:53:41
sect04

Active CPUs
Hardware Rev
System Serial Number
Module Serial Number
Module Type
System Revision
* MCHK 660 Regs *
Flags:
PCI Mask
Machine Check Reason
PAL SHADOW REG 0
PAL SHADOW REG 1
PAL SHADOW REG 2
PAL SHADOW REG 3
PAL SHADOW REG 4
PAL SHADOW REG 5
PAL SHADOW REG 6
PAL SHADOW REG 7
PALTEMP0
PALTEMP1
PALTEMP2
.
.
.
PALTEMP22
PALTEMP23
Exception Address Reg
Exception Summary Reg
Exception Mask Reg
PAL Base Address Reg
Interrupt Summary Reg
IBOX Ctrl and Status Reg

2. 660 Entry
x0000002300000000
IOD 0 Register Subpkt Pres
IOD 1 Register Subpkt Pres
PCI 1 Bus Snapshot Present
x00000003
x00000000
GA12000000
x0000
x00000000

➋
x00000000
x0002
x0202

IOD-Detected Hard Error -ORDTag Parity Error (If Cached CPU)
x0000000000000000
x0000000000000000
x0000000000000000
x0000000000000000
x00000B6D00000000
x0000000000000000
x0000000000000000
x0000000000000000
x00000000000000B6
x0000000000000001
xFFFFFC00003B8B90

xFFFFFC000052E3A0
x0000000002729A38
x00000001200077F0
Native-mode Instruction
Exception PC x0000000048001DFC
x0000000000000000
x0000000000000000
x0000000000014000
Base Addr for PALcode: x0000000000000005
x0000000000200000
External HW Interrupt at IPL21
AST Requests 3-0: x0000000000000000
x000000C160020000
Timeout Counter Bit Clear.
IBOX Timeout Counter Enabled.

Error Logs

4-30

Icache Par Err Stat Reg
Dcache Par Err Stat Reg
Virtual Address Reg
Memory Mgmt Flt Sts Reg

Floating Point Instructions will Cause
FEN Exceptions.
PAL Shadow Registers Enabled.
Correctable Error Interrupts Enabled.
ICACHE BIST (Self Test) Was Successful.
TEST_STATUS_H Pin Asserted
x0000000000000000
x0000000000000000
x0000000140008000
x0000000000005F10
If Err, Reference Resulted in DTB Miss
Fault Inst RA Field: x000000000000001C

Fault Inst Opcode: x000000000000000B
xFFFFFF0000018FEF
x0000000000000000
xFFFFFF8061CD0FFF
Last Bcache Access Resulted in a Miss.
Value of Parity Bit for Tag Control Status
Bits Dirty, Shared & Valid is Clear.
Value of Tag Control Dirty Bit is Clear.
Value of Tag Control Shared Bit is Clear.
Value of Tag Control Valid Bit is Set.
Value of Parity Bit Covering Tag Store
Address Bits is Clear.
Tag Address<38:20> Is: x000000000000061C
Ext Interface Address Reg xFFFFFF006000050F
Fill Syndrome Reg
x0000000000000C0C
Ext Interface Status Reg xFFFFFFF005FFFFFF
➌
Error Occurred During D-ref Fill
LD LOCK
xFFFFFF00002006FF
Scache Address Reg
Scache Status Reg
Bcache Tag Address Reg

** IOD SUBPACKET -> **
WHOAMI

IOD 0 Register Subpacket
x000002FA

Module Revision 0.
VCTY ASIC Rev = 1
Bcache Size = 4MB
CPU = 0

This Bus Bridge Phy Addr

x000000F9E0000000
IOD# 0
Dev Type & Rev Register
x0600A332 CAP Chip Revision:
x00000002
Host to PCI Revision:
x00000003
I/O Backplane Revision:
x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host Bus to PCI Bridg MC-PCI
Command Register
x46480FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE PCI Arbitration: Round Robin
Mem Host Address Ext Reg
IO Host Adr Ext Register
Interrupt Ctrl Register

x00000000
x00000000
x00000003

HAE Sparse Mem Adr<31:27> x00000000
PCI Upper Adr Bits<31:25> x00000000
Write Device Interrupt Info Struct:Enabled

Error Logs

4-31

Interrupt Request
Interrupt Mask0 Register
Interrupt Mask1 Register
MC Error Info Register 0

x00000000
x00C50110
x00000000
xE0000000

MC Error Info Register 1

x000E88FD

CAP Error Register
PCI Bus Trans Error Adr
MDPA Status Register
MDPA Error Syndrome Reg
MDPB Status Register
MDPB Error Syndrome Reg

x00000000
x00000000
x00000000
x00000000
x00000000
x00000000

** IOD SUBPACKET -> **

Interrupts asserted

x00000000

MC Bus Trans Addr<31:4>: E0000000
MC bus trans addr <39:32> x000000FD
MC Command is Read0-IO
CPU0 Master at Time of Error
Device ID 2 x00000002

➍
MDPA Status Register Data Not Valid
MDPA Syndrome Register Data Not Valid
MDPB Status Register Data Not Valid
MDPB Syndrome Register Data Not Valid

IOD 1 Register Subpacket

WHOAMI

x000002FA

This Bus Bridge Phy Addr

x000000FBE0000000
IOD# 1
x06002332 CAP Chip Revision:
x00000002
Host to PCI Revision:
x00000003
I/O Backplane Revision:
x00000003
Internal CAP Chip Arbiter: Enabled
Device Class: Host Bus to PCI Bridg
x46480FF1 Module Self-Test Passed LED On.
Delayed PCI Bus Reads Protocol: Enabled
Bridge to PCI Transactions:
Enabled
Bridge REQUESTS 64 Bit Data Transactions
Bridge ACCEPTS 64 Bit Data Transactions
PCI Address Parity Check:
Enabled
MC Bus CMD/Addr Parity Check:
Enabled
MC Bus NXM Check:
Enabled
Check ALL Transactions for Errors
Use MC_BMSK for 16 Byte Align Blk Mem Wrt
Wrt PEND_NUM Threshold: 8.
RD_TYPE Memory Prefetch Algorithm: Short
RL_TYPE Mem Rd Line Prefetch Type: Medium
RM_TYPE Mem Rd Multiple Cmd Type: Long
ARB_MODE PCI Arbitration: Round Robin
x00000000 HAE Sparse Mem Adr<31:27> x00000000
x00000000 PCI Upper Adr Bits<31:25> x00000000
x00000003 Write Device Interrupt Info Struct:Enabled
x00800000 Interrupts asserted x00000000
Hard Error
x00C50111
x00000000
xE0000000
MC Bus Trans Addr<31:4>: E0000000
x000E88FD MC bus trans addr <39:32> x000000FD
MC Command is Read0-IO
CPU0 Master at Time of Error
Device ID 2 x00000002
NOT VALID!
➏

Dev Type & Rev Register

MC-PCI Command Register

Mem Host Address Ext Reg
IO Host Adr Ext Register
Interrupt Ctrl Register
Interrupt Request
Interrupt Mask0 Register
Interrupt Mask1 Register
MC Error Info Register 0
MC Error Info Register 1

CAP Error Register

x00000012

PCI Bus Trans Error Adr
MDPA Status Register

xC157B5C0
x00000000

Module Revision 0.
VCTY ASIC Rev = 1
Bcache Size = 4MB
CPU = 0

Serious error
PCI error address reg locked

➎

MDPA Status Register Data Not Valid

Error Logs

4-32

MDPA Error Syndrome Reg
MDPB Status Register
MDPB Error Syndrome Reg

x00000000
x00000000
x00000000

MDPA Syndrome Register Data Not Valid
MDPB Status Register Data Not Valid
MDPB Syndrome Register Data Not Valid

PALcode Revision

Palcode Rev: 1.21-20

** PCI SUBPACKET -> **

PCI 1 Subpacket

Node Qty

CONFIG Address

x000000FBC0000800
Slot or Device Number: 1
Device and Vendor ID
x00011000 NCR 53C810 NCR_810 SCSI Narrow SingleEnded
Vendor ID: x1000 (NCR)
Device ID: x00000001
Command Register
x0147 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability:
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds:DISABLED
Parity Error Detection Response: Normal
Wait Cycle Address/Data Stepping:DISABLED
SERR# Sys Err Driver Capability: Enabled
Fast Back-to-Back to Many Target:DISABLED
Status Register
x0200 Device is 33 Mhz Capable.
➐
No Support for User Defineable Features.
Fast Back-to-Back to Different Targets,
Is Not Supported in Target Device.
Device Select Timing: Medium.
Revision ID
x02
Device Class Code
x010000 Mass Storage: SCSI Bus Controller
Cache Line S
x00
Latency T.
xFF
Header Type
x00 Single Function Device
Bist
x00
Base Address Register 1
x00101200
Base Address Register 2
x0412A100
Base Address Register 3
x00000000
Base Address Register 4
x00000000
Base Address Register 5
x00000000
Base Address Register 6
x00000000
Expansion Rom Base Addres x00000000
Interrupt P1
x04
Interrupt P2
x01
Min Gnt
x00
Max Lat
x00

CONFIG Address
Device and Vendor ID
Command Register

x000000FBC0001000
Slot or Device Number: 2
x10201077 QLogic ISP_1020
Vendor ID: x102B (QLogic)
Device ID: x00001020
x0107 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability:
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds: DISABLED
Parity Error Detection Response: *IGNORE*
Wait Cycle Address/Data Stepping: DISABLED
SERR# Sys Err Driver Capability: Enabled
Fast Back-to-Back to Many Target: DISABLED

Error Logs

4-33

x0200 Device is 33 Mhz Capable.
➐
No Support for User Defineable Features.
Fast Back-to-Back to Different Targets,
Is Not Supported in Target Device.
Device Select Timing: Medium.
Revision ID
x05
Device Class Code
x010000 Mass Storage: SCSI Bus Controller
Cache Line S
x10
Latency T.
xF8
Header Type
x00 Single Function Device
Bist
x00
Base Address Register 1
x00101100
Base Address Register 2
x04129000
Base Address Register 3
x00000000
Base Address Register 4
x00000000
Base Address Register 5
x00000000
Base Address Register 6
x00000000
Expansion Rom Base Addres x04110000
Interrupt P1
x08
Interrupt P2
x01
Min Gnt
x00
Max Lat
x00
Status Register

CONFIG Address

x000000FBC0001800
Slot or Device Number: 3
Device and Vendor ID
x00011069 Mylex DAC960 KZPSC RAID Controller
Vendor ID: x1069 (Mylex)
Device ID: x00000001
Command Register
x0107 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability:
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds: DISABLED
Parity Error Detection Response: *IGNORE*
Wait Cycle Address/Data Stepping: DISABLED
SERR# Sys Err Driver Capability: Enabled
Fast Back-to-Back to Many Target: DISABLED
Status Register
x8200 Device is 33 Mhz Capable.
➐
No Support for User Defineable Features.
Fast Back-to-Back to Different Targets,
Is Not Supported in Target Device.
Device Select Timing: Medium.
DETECTED PARITY ERROR:This Device Detected
Revision ID
x02
Device Class Code
x010400 Mass Storage: RAID Controller
Cache Line S
x10
Latency T.
xFF
Header Type
x00 Single Function Device
Bist
x00
Base Address Register 1
x00101000
Base Address Register 2
x0412A000
Base Address Register 3
x00000000
Base Address Register 4
x00000000
Base Address Register 5
x00000000
Base Address Register 6
x00000000
Expansion Rom Base Addres x04120000
Interrupt P1
x0C
Interrupt P2
x01
Min Gnt
x04
Max Lat
x00

Error Logs

4-34

CONFIG Address

x000000FBC0002000
Slot or Device Number: 4
Device and Vendor ID
x00081011 DEC_KZPSA Fast-Wide-Differential SCSI
Vendor ID: x1011 (Digital Equip Corp)
Device ID: x00000008
Command Register
x0107 I/O Space Accesses Response:
Enabled
Memory Space Accesses Response:
Enabled
PCI Bus Master Capability:
Enabled
Monitor for Special Cycle Ops:
DISABLED
Generate Mem Wrt/Invalidate Cmds: DISABLED
Parity Error Detection Response: *IGNORE*
Wait Cycle Address/Data Stepping: DISABLED
SERR# Sys Err Driver Capability: Enabled
Fast Back-to-Back to Many Target: DISABLED
Status Register
xA2C0 Device is 33 Mhz Capable.
➐
Device Supports User Defineable Features.
Fast Back-to-Back to Different Targets,
Is Supported in Target Device.
Device Select Timing: Medium.
RECEIVED MASTER-ABORT:Master Sets When Its
Transaction Terminated by MasterAbort.
DETECTED PARITY ERROR:This Device Detected
Revision ID
x00
Device Class Code
x010000 Mass Storage: SCSI Bus Controller
Cache Line S
x10
Latency T.
xFF
Header Type
x00 Single Function Device
Bist
x80
Base Address Register 1
x04128000
Base Address Register 2
x00000000
Base Address Register 3
x00100000
Base Address Register 4
x04000000
Base Address Register 5
x00000000
Base Address Register 6
x00000000
Expansion Rom Base Addres x04100000
Interrupt P1
x10
Interrupt P2
x01
Min Gnt
x08
Max Lat
x7F

Error Logs

4-35

4.3.6 MCHK 630 Correctable CPU Error
The error log in Example 4–6 shows the following:

➊
➋

CPU0 logged the error in a system with two CPUs.

➌
➍

Both IOD CAP Error Registers logged no error.

During a D-ref fill, the External Interface Status Register shows no error but
states that the “data source is b-cache.” (When a CPU chip does not find data it
needs to perform a task in any of its caches, it requests data from off the chip to
fill its D-cache. It performs a D-ref fill.)

The FIL Syndrome Register has a valid ECC code for the lower half of the
data.
Machine check 630s are detected by CPUs when they either take data off the system
bus or when they access their own B-cache. In this case, the data did not come from
the system bus, otherwise bit <30> would be set in the External Interface Status
Register. CPU0 had a single-bit, ECC correctable error.
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “MC” bus is the system bus.
Refer to Table 4-9 for information on decoding commands, and refer to Table 4-10 for
information on node IDs.

Error Logs

4-36

Example 4–6 MCHK 630 Correctable CPU Error
Logging OS
System Architecture
Event sequence number
Timestamp of occurrence
Host name

2. DIGITAL UNIX
2. Alpha 4000/1200 Series
415.
15-JUN-1997 14:56:30
whip16

System type register
x00000016 AlphaServer 4000/1200 Series
Number of CPUs (mpnum)
x00000002
CPU logging event (mperr) x00000000
Event validity
1. O/S claims event is valid
Event severity
3. High Priority
Entry type
100. CPU Machine Check Errors
CPU Minor class

➊

3. Bcache error (630 entry)

Software Flags
Active CPUs
Hardware Rev
System Serial Number
Module Serial Number
Module Type
System Revision

x00000000
x00000003
x00000000

Machine Check Reason
EI STAT

x0086 Alpha Chip Detected ECC Err, From B-Cache
xFFFFFFF085FFFFFF
DATA SOURCE IS BCACHE ➋

C1563
x0000
x00000000

D-ref fill
EI ADDRESS
FIL SYNDROME
ISR

EV56 Chip Rev 5
xFFFFFF00138D85EF
x00000000000800
x0000000100200000

WHOAMI

x00000000

Sys Environmental Regs
Base Addr of Bridge
Dev Type & Rev Register

x00000000
x00000000
x06008021

MC Error Info Register 0

x00000000

MC Error Info Register 1

x00000000

CAP Error Register
MDPA Status Register

x00000000
x00000000

MDPA Error Syndrome Reg

MDPB Status Register
MDPB Error Syndrome Reg

PALcode Revision

x00000000

CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
MC Bus Trans Addr<31:4>: 0
MC bus trans addr <39:32> x00000000
MC Command is Illegal
Illegal
Device ID 2 x00000000

➌
MDPA Status Register Data Not Valid

MDPA Syndrome Register Data Not Valid

x00000000
x00000000

Module Revision
MID 0.
GID 0.

➍

MDPB Status Register Data Not Valid

MDPB Syndrome Register Data Not Valid

Palcode Rev: 1.21-3

Error Logs

4-37

4.3.7 MCHK 620 Correctable Error
The MCHK 620 error is a correctable error detected by the IOD.
The error log in Example 4–7 shows the following:

➊
➋
➌
➍
➎

CPU0 logged the error in a system with two CPUs.
The External Interface Status Register is not valid.
The MC Error Info Registers 0 and 1 captured the error information.
The commander at the time of the error was CPU0.

The command at the time of the error was a write-back memory command.
The IOD detected a recoverable error on the system bus. The MC command at the
time of the error is a Write Back-Mem Command (x00000016). The system bus
commander at the time of the error is CPU0. Since this is a write, the defective FRU
is CPU0.
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “MC” bus is the system bus.
Refer to Table 4-9 for information on decoding commands, and refer to Table 4-10 for
information on node IDs.

Error Logs

4-38

Example 4–7 MCHK 620 Correctable Error
Logging OS
System Architecture
Event sequence number
Timestamp of occurrence
Host name

2. DIGITAL UNIX
2. Alpha
32.
28-JUN-1997 19:45:42
sect06

System type register
x00000016 AlphaServer 4000/1200 Series
Number of CPUs (mpnum)
x00000002
➊
CPU logging event (mperr) x00000000
Event validity
Event severity
Entry type
CPU Minor class

1. O/S claims event is valid
5. Low Priority
100. CPU Machine Check Errors
4. 620 System Correctable Error

Software Flags
Active CPUs
Hardware Rev
System Serial Number
Module Serial Number
Module Type
System Revision

x0000000000000000
x00000003
x00000000
C1563

Machine Check Reason
Ext Interface Status Reg

x0204 IOD Detected Soft Error
x0000000000000000
Not Valid for 620 System

x0000
x00000000

➋

Correctable Errors
Ext Interface Address Reg x0000000000000000
Not Valid for 620 System
Correctable Errors
Fill Syndrome Reg
x0000000000000000
Not Valid for 620 System
Correctable Errors
Interrupt Summary Reg
x0000000000000000
Not Valid for 620 System
Correctable Errors
WHOAMI
x00000000 Module Revision 0.
MID 0.
GID 0.
Sys Environmental Regs
x00000000
Base Addr of Bridge
x000000FBE0000000
Dev Type & Rev Register
x06008021 CAP Chip Revision
x00000001
Host to PCI Revision
x00000003
I/O Backplane Revision x00000003
PCI-EISA Bus Bridge Present on PCI
Device Class: Host bus to PCI Bridg
MC Error Info Register 0 x122D5640
MC Bus Trans Addr<31:4>: 122D5640
MC Error Info Register 1 x800E9600 MC bus trans addr <39:32> x00000000
MC Command is WriteBack Mem ➎
CPU0 Master at Time of Error
Device ID 2 x00000002
➍
MC error info valid
CAP Error Register
x89000000 Error Detected but Not Logged

Error Logs

4-39

Correctable ECC err det by MDPA
MC error info latched
MDPA Status Register
MDPA Error Syndrome Reg
MDPB Status Register
MDPB Error Syndrome Reg
PALcode Revision

x00000000
x00000000
x00000000
x00000000

➌

MDPA Status Register Data Not Valid
MDPA Syndrome Register Data Not Valid
MDPB Status Register Data Not Valid
MDPB Syndrome Register Data Not Valid
Palcode Rev: 0.0-1

Error Logs

4-40

4.4

Troubleshooting IOD-Detected Errors

Step 1
Read the CAP Error Registers on both PCI bridges (F9E0000880 and FBE0000880).
If one or both of these registers shows an error, match the register contents with the
data pattern and perform the action indicated.

Table 4-3 CAP Error Register Data Pattern
Data Pattern

Most Likely Cause

Action

110x x00x x000 0000 0000 0000 000x xxxx

RDSB - Uncorrectable ECC
error detected on upper QW of
MC bus (D127:64>)

Go to Step 2

101x x00x x000 0000 0000 0000 000x xxxx

RDSA - Uncorrectable ECC
error detected on lower QW of
MC bus (D63:0>)

Go to Step 2

111x x00x x000 0000 0000 0000 000x xxxx

RDS detected in both QWs

Go t to Step 2

1001 1000 x000 0000 0000 0000 000x xxxx

CRDB - Correctable ECC error
detected on upper QW of MC
bus (D127:64>)

Go to Step 2

1000 0000 x000 0000 0000 0000 000x xxxx

CRDA - Correctable ECC error
detected on lower QW of MC
bus (D63:0>)

Go to Step 2

1001 1000 x000 0000 0000 0000 000x xxxx

CRD detected in both QWs.

Go to Step 2

100x x10x x000 0000 0000 0000 000x xxxx

NXM - Nonexistent MC bus
address

Go to Step 3

100x x01x x000 0000 0000 0000 000x xxxx

MC_ADR_PERR - MC bus
address parity error

Go to Step 4

100x x00x 1000 0000 0000 0000 000x xxxx

PIO_OVFL - PIO buffer
overflow

Go to Step 5

0000 0000 0000 0000 0000 0000 0001 1xxx

PTE_INV - Page table entry is
invalid

Go to Step 6

0000 0000 0000 0000 0000 0000 0001 x1xx

MAB - Master abort

Go to Step 7

0000 0000 0000 0000 0000 0000 0001 xx1x

SERR - PCI system error

Go to Step 8

0000 0000 0000 0000 0000 0000 0001 xxx1

PERR - PCI parity error

Go to Step 9

Error Logs

4-41

4.4.1 System Bus ECC Error
Step 2
Read the MC_ERR1 register and match the contents with the data pattern. Perform
the action indicated.

Table 4-4 System Bus ECC Error Data Pattern
MC_ERR1 Data Pattern

Most Likely Cause

Action

1000 0000 0000 xxxx xxxx 10xx 0xxx xxxx

Bad nondirty data from
memory (bad memory)

Go to Step 10

1000 0000 0000 xxxx xxxx 111x 0xxx xxxx

Bad nondirty data from
memory (bad memory)

Go to Step 10

1000 0000 0001 xxxx xxxx 10xx 0xxx xxx

Bad dirty data from a
CPU

Replace CPU(s)

1000 0000 0001 xxxx xxxx 111x 0xxx xxxx

Bad dirty data from a
CPU

Replace CPU(s)

1000 0000 000x xxx0 10xx 011x xxxx xxxx

Bad data from MID = 2

Replace CPU0

1000 0000 000x xxx0 11xx 011x xxxx xxxx

Bad data from MID = 3

Replace CPU1

1000 0000 000x xxx1 00xx 011x xxxx xxxx

Bad data from MID = 4

Replace Mbrd

1000 0000 000x xxx1 01xx 011x xxxx xxxx

Bad data from MID = 5

Replace Mbrd

for Memory Fill Transactions
1000 0000 000x xxx1 00xx 110x xxxx xxxx

Bad data from MID = 4

Replace Mbrd

1000 0000 000x xxx1 01xx 110x xxxx xxxx

Bad data from MID = 5

Replace Mbrd

1000 0000 000x xxx1 10xx 110x xxxx xxxx

Bad data from MID = 6

Replace Mbrd

1000 0000 000x xxx1 11xx 110x xxxx xxxx

Bad data from MID = 7

Replace Mbrd

for Memory Read

for Memory or I/O Write

Error Logs

4-42

4.4.2 System Bus Nonexistent Address Error
Step 3
Determine which node (if any) should have responded to the command/address
identified in MC_ERR1. Perform the action indicated.

Table 4-5 System Bus Nonexistent Address Error Troubleshooting
MC_ERR1 Data Pattern

Most Likely Cause

Action

1000 0000000x xxxx xxxx xxxx 0xxx xxxx

Software generated an MC
ADDR > TOP_OF_MEM
reg

Fix software

1000 00000000 xxxx xxxx xxxx 1xxx 100x

PCI0 bridge did not
respond

Replace Mbrd

1000 00000000 xxxx xxxx xxxx 1xxx 101x

PCI1 bridge did not
respond

Replace Mbrd

1000 00000000 xxxx xxxx xxxx 1xxx 110x

PCI2 bridge did not
respond

Replace Mbrd

1000 00000000 xxxx xxxx xxxx 1xxx 111x

PCI3 bridge did not
respond

Replace Mbrd

Error Logs

4-43

4.4.3 System Bus Address Parity Error
Step 4
Determine which node put the bad command/adress on the system bus identified in
MC_ERR1. Perform the action indicated.

Table 4-6 Address Parity Error Troubleshooting
MC_ERR1 Data Pattern

Most Likely Cause

Action

1000 0000000x xxx0 10xx xxxx xxxx xxxx

Data sourced by MID = 2

Replace CPU0

1000 0000000x xxx0 11xx xxxx xxxx xxxx

Data sourced by MID = 3

Replace CPU1

1000 0000000x xxx1 00xx xxxx xxxx xxxx

Data sourced by MID = 4

Replace Mbrd

1000 0000000x xxx1 01xx xxxx xxxx xxxx

Data sourced by MID = 5

Replace Mbrd

Error Logs

4-44

4.4.4 PIO Buffer Overflow Error (PIO_OVFL)
Step 5
Enter the value of the CAP_CTRL register bits<19:16> (Actual_PEND_NUM) in the
following formula. Compare the results as indicated in Table 4-7 to determine the
most likely cause of the error. When an IOD is implicated in the analysis of the error,
replace the one that capturered the error in its CAP Error Register.
Expected_PEND_NUM = 12 - ((2 * (X - 1)) + Y)
Where: X = Number of PCIs
Y = Number of CPUs

Table 4-7 Cause of PIO_OVFL Error
Comparison

Most Likely Cause

Action

Actual_PEND_NUM =
Expected_PEND_NUM

Broken hardware on IOD

Replace Mbrd

Actual_PEND_NUM <
Expected_PEND_NUM

Broken hardware on IOD

Replace Mbrd

Actual_PEND_NUM >
Expected_PEND_NUM

PEND_NUM setup incorrect

Fix the software

Error Logs

4-45

4.4.5 Page Table Entry Invalid Error
Step 6
This error is almost always a software problem. However, if the software is known to
be good and the hardware is suspected, swap the motherboard.

4.4.6 PCI Master Abort
Step 7
Master aborts normally occur when the operating system is sizing the PCI bus.
However, if the master abort occurs after the system is booted, read PCI_ERR1 and
determine which PCI device should have responded to this PCI address. Replace this
device.

4.4.7 PCI System Error
Step 8
For this error to occur a PCI device asserted SERR. Read the error registers in all the
PCI devices to determine which device. The PCI device that set SERR should have
information logged in its error registers that should indicate a device.

4.4.8 PCI Parity Error
Step 9
Read PCI_ERR1 and determine which PCI device normally uses that PCI address
space. Replace that device. Also, read the error registers in all the PCI devices to
determine which device was driving the PCI bus when the parity error occurred.

Error Logs

4-46

4.4.9 Broken Memory
Step 10
Refer to the following sections.
For a Read Data Substitute Error (uncorrectable ECC error)
When a read data substitute (RDS) error occurs, determine which memory module pair
caused the error as follows:
1.

Run the memory diagnostic to see if it catches the bad memory. If so, replace the
memory module that it reports as bad.

At the SRM console prompt, enter the show mem command.
P00>>> show mem
This command displays the base address and size of the memory module pair for
each slot.
OR
Read the configuration packet, found in the error log, to retrieve the base address
and size of the memory module pair.

Compare this address to the failing address from the MC_ERR1 and MC_ERR0
Registers to determine which memory slot is failing.

Replace both memory modules (high and low) for that slot. For an RDS error,
there is no way to know which memory module (high or low) is bad.

For a Corrected Read Data Error (CRD)
When a CRD error occurs, determine which memory module pair caused the error as
follows:
1.

At the SRM console prompt, enter the show mem command. This command
displays the base address and size of the memory module pair for each slot.

Compare this address to the failing address from the MC_ERR1 and MC_ERR0
Registers to determine which memory slot is failing.

P00>>> show mem

Error Logs

4-47

When you have isolated the failing memory pair, determine which of the two
DIMMs is bad. (You cannot do this if the operating system is Windows NT.)
Read the CPU FIL SYNDROME Register. If this register is non-zero, use the
ECC syndrome bits in Table 4-8 to determine which DIMM had the single-bit
error.

Table 4-8 ECC Syndrome Bits Table
CPU Syndrome Values for Low-Order Memory
01

CPU Syndrome Values for High-Order Memory
2A

Error Logs

4-48

4.4.10 Command Codes
Table 4-9 shows the command codes for transactions on the system bus. Note that
they are affected by the commander in charge of the bus during the transaction. The
command is a six-bit field in the command address (bits<5:0>). Bit-to-text
translations give six-bit data (the top two bits may or may not be relevant). Note that
address bit<39> defines the command as being either a system space or an I/O
command.

Table 4-9 Decoding Commands
54

MC_CMD
3210

CMD
in Hex

MC_ADR
<39>

0000

0010

Description

IOD

Mem Idle

Write Pend Ack

0011

Mem Refresh

0101

Set Dirty

0110

0/2 6

Write Thru - Mem

0110

0/2 6

Write Thru - I/O

0110

3/1 6

Write Back - Mem

0110

3/1 6

Write Intr - I/O

0111

Write Full - Mem

0111

Write Part - Mem

0111

0/2 7

Write Mask - I/O

0111

0/2 7

Write Merge - Mem

1000

Read0 - Mem

1000

Read0 - I/O

1001

Read1 - Mem

1001

Read1 - I/O

1010

Read Mod0 - Mem

Y
Y

Error Logs

4-49

Table 4-9 Decoding Commands (continued)
54

MC_CMD
3210

CMD
in Hex

MC_ADR
<39>

Description

IOD

1010

Read Peer0 - I/O

1011

Read Mod1 - Mem

1011

Read Peer1 - I/O

1100

FILL0 (due to
Read0/Peer0)

1101

FILL1 (due to
Read1/Peer1)

1110

Read0 - Mem

1111

Read1 - Mem

4.4.11 Node IDs
The node ID is a six-bit field in the command address (bits<38:33>). The high-order
three bits are always set, and the last three indicate the node. Bit-to-text translations
give six-bit data, although only the last three bits define the node.

Table 4-10 Node IDs
Node ID <2:0>

Six Bit (Hex)

Node

000

001

Memory

010

CPU0

011

CPU1

100

IOD0 on Mbrd

101

IOD1 on Mbrd

110

111

Error Logs

4-50

4.5

Double Error Halts and Machine Checks While
in PAL Mode

Two error cases require special attention. Neither double error halts or machine
checks while the machine is in PAL mode result in error log entries.
Nevertheless, information is available that can help determine what error
occurred.

4.5.1 PALcode Overview
PALcode, privileged architecture library code, is used to implement a number of
functions at the machine level without the use of microcode. This allows operating
systems to make common calls to PALcode routines without knowing the hardware
specifics of each system the operating system is running on. PALcode routines
handle:
•

Instructions that require complex sequencing, such as atomic operations

•

Instructions that require VAX-style interlocked memory access

•

Privileged instructions

•

Memory management

•

Context swapping

•

Interrupt and exception dispatching

•

Power-up initialization and booting

•

Console functions

•

Emulation of instructions with no hardware support

Error Logs

4-51

4.5.2 Double Error Halt
A double error halt occurs under the following conditions:
•

A machine check occurs.

•

PAL completes its tasks and returns control to the operating system.

•

A second machine check occurs before the operating system completes its tasks.

The machine returns to the console and displays the following message:
halt code = 6
double error halt
PC = 20000004
Your system has halted due to an irrecoverable
error. Record the error halt code and PC and
contact your Digital Services representative. In
addition, type INFO 5 and INFO 8 at the console and
record the results.

The info 5 command (Example 4–9) causes the SRM console to read the PAL-built
logout area that contains all the data used by the operating system to create the error
entry.
The info 8 command (Example 4–10) causes the SRM console to read the IOD 0 and
IOD 1 registers.

4.5.3 Machine Checks While in PAL
If a machine check occurs while the system is running PALcode, PALcode returns to
the SRM console, not to the operating system. The SRM console writes:
halt code = 7
machine check while in PAL mode
PC = 20000004
Your system has halted due to an irrecoverable
error. Record the error halt code and PC and contact
your Digital Services representative. In
addition, type
INFO 3 and INFO 8 at the console and
record the results.

The info 3 command (Example 4–8) causes the SRM console to read the “impure
area,” which contains the state of the CPU before it entered PAL.

Example 4–8 INFO 3 Command
P00>>> info 3
cpu00
per_cpu impure area
cns$flag
cns$flag+4
cns$hlt
cns$hlt+4

00004400
00000001 : 0000
00000000 : 0004
00000000 : 0008
00000000 : 000c

Error Logs

4-52

cns$mchkflag
cns$mchkflag+4
cns$exc_addr
cns$exc_addr+4
cns$pal_base
cns$pal_base+4
cns$mm_stat
cns$mm_stat+4
cns$va
cns$va+4
cns$icsr
cns$icsr+4
cns$ipl
cns$ipl+4
cns$ps
cns$ps+4
cns$itb_asn
cns$itb_asn+4
cns$aster
cns$aster+4
cns$astrr
cns$astrr+4
cns$isr
cns$isr+4
cns$ivptbr
cns$ivptbr+4
cns$mcsr
cns$mcsr+4
cns$dc_mode
cns$dc_mode+4
cns$maf_mode
cns$maf_mode+4
cns$sirr
cns$sirr+4
cns$fpcsr
cns$fpcsr+4
cns$icperr_stat
cns$icperr_stat+4
cns$pmctr
cns$pmctr+4
cns$exc_sum
cns$exc_sum+4
cns$exc_mask
cns$exc_mask+4
cns$intid
cns$intid+4
cns$dcperr_stat
cns$dcperr_stat+4
cns$sc_stat
cns$sc_stat+4
cns$sc_addr
cns$sc_addr+4
cns$sc_ctl
cns$sc_ctl+4
cns$bc_tag_addr
cns$bc_tag_addr+4
cns$ei_stat
cns$ei_stat+4
cns$fill_syn
cns$fill_syn+4
cns$ld_lock
cns$ld_lock+4

00000228 : 0210
00000000 : 0214
20000004 : 0318
00000000 : 031c
00000000 : 0320
00000000 : 0324
0000da10 : 0338
00000000 : 033c
00080000 : 0340
00000002 : 0344
40000000 : 0348
000000c1 : 034c
0000001f : 0350
00000000 : 0354
00000000 : 0358
00000000 : 035c
00000000 : 0360
00000000 : 0364
00000000 : 0368
00000000 : 036c
00000000 : 0370
00000000 : 0374
00400000 : 0378
00000000 : 037c
00000000 : 0380
00000002 : 0384
00000000 : 0388
00000000 : 038c
00000001 : 0390
00000000 : 0394
00000080 : 0398
00000000 : 039c
00000000 : 03a0
00000000 : 03a4
00000000 : 03a8
ff900000 : 03ac
00000000 : 03b0
00000000 : 03b4
00000000 : 03b8
00000000 : 03bc
00000000 : 03c0
00000000 : 03c4
00000000 : 03c8
00000000 : 03cc
00000016 : 03d0
00000000 : 03d4
00000000 : 03d8
00000000 : 03dc
00000000 : 03e0
00000000 : 03e4
000047cf : 03e8
ffffff00 : 03ec
0000f000 : 03f0
00000000 : 03f4
ff7fefff : 03f8
ffffffff : 03fc
04ffffff : 0400
fffffff0 : 0404
000000a7 : 0410
00000000 : 0414
0004eaef : 0418
ffffff00 : 041c

Error Logs

4-53

Example 4–9 INFO 5 Command
P00>>> info 5
cpu00
per_cpu logout area
mchk$crd_flag
mchk$crd_flag+4
mchk$crd_offsets
mchk$crd_offsets+4
mchk$crd_mchk_code
mchk$crd_mchk_code+4
mchk$crd_ei_stat
mchk$crd_ei_stat+4
mchk$crd_ei_addr
mchk$crd_ei_addr+4
mchk$crd_fill_syn
mchk$crd_fill_syn+4
mchk$crd_isr
mchk$crd_isr+4
mchk$flag
mchk$flag+4
mchk$isr
mchk$isr+4
mchk$icsr
mchk$icsr+4
mchk$ic_perr_stat
mchk$ic_perr_stat+4
mchk$dc_perr_stat
mchk$dc_perr_stat+4
mchk$va
mchk$va+4
mchk$mm_stat
mchk$mm_stat+4
mchk$sc_addr
mchk$sc_addr+4
mchk$sc_stat
mchk$sc_stat+4
mchk$bc_tag_addr
mchk$bc_tag_addr+4
mchk$ei_addr
mchk$ei_addr+4
mchk$fill_syn
mchk$fill_syn+4
mchk$ei_stat
mchk$ei_stat+4
mchk$ld_lock
mchk$ld_lock+4

00004838
00000320 : 0000
00000000 : 0004
00000118 : 0008
00001328 : 000c
00980000 : 0010
00000000 : 0014
eba00003 : 0018
4143040a : 001c
d1200067 : 0020
47f90416 : 0024
eba00003 : 0028
d1200068 : 002c
7ec38000 : 0030
63ff4000 : 0034
00000320 : 0000
00000000 : 0004
00000000 : 0138
00000000 : 013c
60000000 : 0140
000000c1 : 0144
00000000 : 0148
00000000 : 014c
00000000 : 0150
00000000 : 0154
ff8000a0 : 0158
ffffffff : 015c
000149d0 : 0160
00000000 : 0164
0001904f : 0168
ffffff00 : 016c
00000000 : 0170
00000000 : 0174
ff7fefff : 0178
ffffffff : 017c
066bc3ef : 0180
ffffff00 : 0184
000000a7 : 0188
00000000 : 018c
04ffffff : 0190
fffffff0 : 0194
00005b6f : 0198
ffffff00 : 019c

IOD: 0 base address: f9e0000000
WHOAMI:
CAP_CTL:
INT_CTL:
INT_MASK1:
CAP_ERR:
MDPA_SYN:

0000003a
02490fb1
00000003
00000000
84000000
00000000

PCI_REV:
HAE_MEM:
INT_REQ:
MC_ERR0:
PCI_ERR:
MDPB_STAT:

06008221
00000000
00800000
e0000000
00000000
00000000

HAE_IO:
INT_MASK0:
MC_ERR1:
MDPA_STAT:
MDPB_SYN:

00000000
00010000
800e88fd
00000000
00000000

IOD: 1 base address: fbe0000000
WHOAMI:

0000003a

PCI_REV:

06000221

Error Logs

4-54

CAP_CTL:
INT_CTL:
INT_MASK1:
CAP_ERR:
MDPA_SYN:

02490fb1
00000003
00000000
84000000
00000000

HAE_MEM:
INT_REQ:
MC_ERR0:
PCI_ERR:
MDPB_STAT:

00000000
00800000
e0000000
00000000
00000000

HAE_IO:
INT_MASK0:
MC_ERR1:
MDPA_STAT:
MDPB_SYN:

00000000
00010000
800e88fd
00000000
00000000

Error Logs

4-55

Example 4–10 INFO 8 Command
P00>>> info 8
IOD 0
WHOAMI:
CAP_CTL:
INT_CTL:
INT_MASK1:
CAP_ERR:
MDPA_SYN:
INT_TARG:
PERF_MON:
DIAG_CHKA:
W0_BASE:
W1_BASE:
W2_BASE:
W3_BASE:
W_DAC:

0000003a
02490fb1
00000003
00000000
00000000
00000000
0000003a
00406ebf
10000000
00100001
00800001
8000000
00000000
00000000

PCI_REV:
HAE_MEM:
INT_REQ:
MC_ERR0:
PCI_ERR:
MDPB_STAT:
INT_ADR:
PERF_CONT:
DIAG_CHKB:
W0_MASK:
W1_MASK:
W2_MASK:
W3_MASK:
SG_TBIA:

06008221
00000000
00000000
e0000000
00000000
00000000
00006000
00000000
10000000
00000000
00700000
3ff00000
1ff00000
00000000

HAE_IO:
INT_MASK0:
MC_ERR1:
MDPA_STAT:
MDPB_SYN:
INT_ADR_EXT:
CAP_DIAG:
SCRATCH:
T0_BASE:
T1_BASE:
T2_BASE:
T3_BASE:
HBASE:

00000000
00210000
000e88fd
00000000
00000000
00000000
00000000
21011131
00001000
00008000
00000000
0000b800
00000000

0000003a
02490fb1
00000003
00000000
00000000
00000000
0000003a
004e31a6
10000000
00100001
00800001
80000001
00000000
00000000

PCI_REV:
HAE_MEM:
INT_REQ:
MC_ERR0:
PCI_ERR:
MDPB_STAT:
INT_ADR:
PERF_CONT:
DIAG_CHKB:
W0_MASK:
W1_MASK:
W2_MASK:
W3_MASK:
SG_TBIA:

06000221
00000000
00000000
e0000000
00000000
00000000
00006000
00000000
10000000
00000000
00700000
3ff00000
1ff00000
00000000

HAE_IO:
INT_MASK0:
MC_ERR1:
MDPA_STAT:
MDPB_SYN:
INT_ADR_EXT:
CAP_DIAG:
SCRATCH:
T0_BASE:
T1_BASE:
T2_BASE:
T3_BASE:
HBASE:

00000000
00000000
000e88fd
00000000
00000000
00000000
00000000
00000000
00001000
00008000
00000000
0000a000
00000000

IOD 1
WHOAMI:
CAP_CTL:
INT_CTL:
INT_MASK1:
CAP_ERR:
MDPA_SYN:
INT_TARG:
PERF_MON:
DIAG_CHKA:
W0_BASE:
W1_BASE:
W2_BASE:
W3_BASE:
W_DAC:

Error Logs

4-56

Chapter 5
Error Registers
This chapter describes the registers used to hold error information. These registers
include:
•

External Interface Status Register

•

External Interface Address Register

•

MC Error Information Register 0

•

MC Error Information Register 1

•

CAP Error Register

•

PCI Error Status Register 1

Error Registers

5-1

5.1

External Interface Status Register - EI_STAT

The EI_STAT register is a read-only register that is unlocked and cleared by any
PALcode read.
A read of this register also unlocks the EI_ADDR,
BC_TAG_ADDR, and FILL_SYN registers subject to some restrictions. The
EI_STAT register is not unlocked or cleared by reset.
Address

FF FFF0 0168

Type

3130 29 28 27

24 23

All 1s
CHIP_ID <3:0>
BC_TPERR
BC_TC_PERR
EI_ES
COR_ECC_ERR
61

36 35 34 33 32

All 1s
SEO_HRD_ERR
FIL_IRD
EI_PAR_ERR
UNC_ECC_ERR
PKW0453-96

Error Registers

5-2

Fill data from B-cache or main memory could have correctable or uncorrectable errors
in ECC mode. System address/command parity errors are always treated as
uncorrectable hard errors, irrespective of the mode. The sequence for reading,
unlocking, and clearing EI_STAT, EI_ADDR, BC_TAG_ADDR, and FILL_SYN is
as follows:
1.

Read the EI_ADDR, BC_TAG_ADDR, and FIL_SYN registers in any order.
Does not unlock or clear any register.

Read the EI_STAT register. This operation unlocks the EI_ADDR,
BC_TAG_ADDR, and FILL_SYN registers. It also unlocks the EI_STAT
register subject to conditions given in Table 5-2, which defines the loading and
locking rules for external interface registers.

NOTE: If the first error is correctable, the registers are loaded but not locked. On
the second correctable error, the registers are neither loaded nor locked.
Registers are locked on the first uncorrectable error except the second hard error bit.
This bit is set only for an uncorrectable error that follows an uncorrectable error. A
correctable error that follows an uncorrectable error is not logged as a second error.
B-cache tag parity errors are uncorrectable in this context.

Error Registers

5-3

Table 5-1 External Interface Status Register
Name

Bits

Type

Description

COR_ECC_ERR <31>

Correctable ECC Error. Indicates that fill
data received from outside the CPU
contained a correctable ECC error.

EI_ES

External Interface Error Source. When
set, indicates that the error source is fill
data from main memory or a system
address/command parity error. When clear,
the error source is fill data from the Bcache.

<30>

This bit is only meaningful when
<COR_ECC_ERR>, <UNC_ECC_ERR>,
or <EI_PAR_ERR> is set in this register.
This bit is not defined for a B-cache tag
error (BC_TPERR) or a B-cache tag control
parity error (BC_TC_ERR).
BC_TC_PERR

<29>

B-Cache Tag Control Parity Error.
Indicates that a B-cache read transaction
encountered bad parity in the tag control
RAM.

BC_TPERR

<28>

B-Cache Tag Address Parity Error.
Indicates that a B-cache read transaction
encountered bad parity in the tag address
RAM.

CHIP_ID

<27:24>

Chip Identification. Read as “5.” Future
update revisions to the chip will return new
unique values.

<23:0>

All ones.

Error Registers

5-4

Table 5-1 External Interface Status Register (continued)
Name

Bits

Type Description

<63:36>

All ones.

SEO_HRD_ERR <35>

Second External Interface Hard Error.
Indicates that a fill from B-cache or main
memory, or a system address/command
received by the CPU has a hard error while
one of the hard error bits in the EI_STST
register is already set.

FIL_IRD

Fill I-Ref D-Ref. When set, indicates that
the error occurred during an I-ref fill. When
clear, indicates that the error occurred during
a D-ref fill. This bit has meaning only when
one of the ECC or parity error bits is set.

<34>

This bit is not defined for a B-cache tag parity
error (BC_TPERR) or a B-cache tag control
parity error (BC_TC_ERR).
EI_PAR_ERR

<33>

External Interface Command/Address
Parity Error. Indicates that an address and
command received by the CPU has a parity
error.

UNC_ECC_ERR <32>

Uncorrectable ECC Error. Indicates that
fill data received from outside the CPU
contained an uncorrectable ECC error. In
parity mode, this bit indicates a data parity
error.

Error Registers

5-5

5.2

External Interface Address Register - EI_ADDR

The EI_ADDR register contains the physical address associated with errors
reported by the EI_STAT register. It is unlocked by a read of the EI_STAT
Register. This register is meaningful only when one of the error bits is set.
Address

FF FFF0 0148

Access

4 3

All 1s

40 39

All 1s

EI_ADDR
<39:32>
PKW0454-96

Error Registers

5-6

Table 5-2 Loading and Locking Rules for External
Interface Registers
Correct
-able
Error

Uncorrectable Error

Second
Hard
Error

Load
Register

Lock
Register

Action When
EI_STAT Is Read

Not
possible

Clears and unlocks
all registers

Not
possible

Yes

Clears and unlocks
all registers

Yes

Clears and unlocks
all registers

Yes

Clear bit (c) does
not unlock.
Transition to
“0,1,0” state.

Already
locked

Clears and unlocks
all registers

Already
locked

Clear bit (c) does
not unlock.
Transition to
“0,1,1” state.

These are special cases. It is possible that when EI_ADDR is read, only the correctable error bit is set and

the registers are not locked. By the time EI_STAT is read, an uncorrectable error is detected and the
registers are loaded again and locked. The value of EI_ADDR read earlier is no longer valid. Therefore, for
the “1,1,x” case, when EI_STAT is read correctable, the error bit is cleared and the registers are not
unlocked or cleared. Software must reexecute the IPR read sequence. On the second read operation, error
bits are in “0,1,x” state, all the related IPRs are unlocked, and EI_STAT is cleared.

Error Registers

5-7

5.3

MC Error Information Register 0
(MC_ERR0 - Offset = 800)

The low-order MC bus (system bus) address bits are latched into this register
when the system bus to PCI bus bridge detects an error event. If the event is a
hard error, the register bits are locked. A write to clear symptom bits in the CAP
Error Register unlocks this register. When the valid bit (MC_ERR_VALID) in
the CAP Error Register is clear, the contents are undefined.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 11 10 09 08 07 06 05 04 03 02 01 00

Failing Address ADDR<31:4>
PKW0551-97

Table 5-3 MC Error Information Register 0
Name

Bits

Type

Initial
State

ADDR<31:4>

<31:4>

Reserved

<3:0>

Description
Contains the address of the
transaction on the system
bus when an error is
detected.

Error Registers

5-8

5.4

MC Error Information Register 1
(MC_ERR1 - Offset = 840)

The high-order MC bus (system bus) address bits and error symptoms are
latched into this register when the system bus to PCI bus bridge detects an error.
If the event is a hard error, the register bits are locked. A write to clear symptom
bits in the CAP Error Register unlocks this register. When the valid bit
(MC_ERR_VALID) in the CAP Error Register is clear, the contents are
undefined.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 11 10 09 08 07 06 05 04 03 02 01 00

reserved (0)

1 1 1

VALID bit
Dirty bit
DEVICE_ID
MC Command <5:0>
Failing Address ADDR<39:32>

PKW0551A-97

Error Registers

5-9

Table 5-4 MC Error Information Register 1
Name

Bits

Type

Initial
State

VALID

<31>

Reserved

<30:21>

Dirty

<20>

Set if the system bus
error was associated with
a Read/Dirty transaction.
When set, the device ID
field <19:14> does not
indicate the source of the
data.

Reserved

<19:17>

All ones.

DEVICE_ID

<16:14>

Slot number of bus
master at the time of the
error.

MC_CMD<5:0>

<13:8>

Active command at the
time the error was
detected.

ADDR<39:32>

<7:0>

Address bits <39:32> of
the transaction on the
system bus when an
error is detected.

Description
Logical OR of bits
<30:23> in the
CAP_ERR Register. Set
if MC_ERR0 and
MC_ERR1 contain a
valid address.

Error Registers

5-10

5.5

CAP Error Register
(CAP_ERR - Offset = 880)

CAP_ERR is used to log information pertaining to an error detected by the CAP
or MDP ASIC. If the error is a hard error, the register is locked. All bits, except
the LOST_MC_ERR bit, are locked on hard errors. CAP_ERR remains locked
until the CAP error is written to clear each individual error bit.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 11 10 09 08 07 06 05 04 03 02 01 00

reserved
PIO_OVFL
LOST_MC_ERR
MC_ADR_PERR
NXM
CRDA
CRDB
RDSA
RDSB
MC_ERR_VALID

PERR
SERR
MAB
PTE_INV
PCI_ERR_VALID

PKW0551B-97

Error Registers

5-11

Table 5-5 CAP Error Register
Name

Bits

Type

Initial
State

MC_ERR VALID

<31>

Logical OR of bits <30:23> in
this register. When set
MC_ERR0 and MC_ERR1
are latched.

RDSB

<30>

RW1C

Uncorrectable ECC error
detected by MDPB. Clear
state in MDPB before
clearing this bit.

RDSA

<29>

RW1C

Uncorrectable ECC error
detected by MDPA. Clear
state in MDPA before
clearing this bit.

CRDB

<28>

RW1C

Correctable ECC error
detected by MDPB. Clear
state in MDPB_STAT before
clearing this bit.

CRDA

<27>

RW1C

Correctable ECC error
detected by MDPA. Clear
state in MDPA_STAT before
clearing this bit.

NXM

<26>

RW1C

System bus master transaction
status NXM (Read with
Address bit <39> set but
transaction not pended or
transaction target above the
top of memory register.) CPU
will also get a fill error on
reads.

MC_ADR_PERR

<25>

RW1C

Set when a system bus
command/address parity error
is detected.

Description

Error Registers

5-12

Table 5-5 CAP Error Register (continued)
Name

Bits

Type

Initial
State

LOST_MC_ERR

<24>

RW1C

Set when an error is detected
but not logged because the
associated symptom fields
and registers are locked with
the state of an earlier error.

PIO_OVFL

<23>

RW1C

Set when a transaction that
targets this system bus to PCI
bus bridge is not serviced
because the buffers are full.
This is a symptom of setting
the PEND_NUM field in
CAP_CNTL to an incorrect
value.

Reserved

<22:5> RO

PCI_ERR_VALID

<4>

Logical OR of bits <3:0> of
this register. When set, the
PCI error address register is
locked.

PTE_INV

<3>

RW1C

Invalid page table entry on
scatter/gather access.

MAB

<2>

RW1C

PCI master state machine
detected PCI Target Abort
(likely cause: NXM) (except
Special Cycle). On reads fill
error is also returned.

SERR

<1>

RW1C

PCI target state machine
observed SERR#. CAP
asserts SERR when it is
master and detects target
abort.

PERR

<0>

RW1C

PCI master state machine
observed PERR#.

Description

Error Registers

5-13

5.6

PCI Error Status Register 1
(PCI_ERR1 - Offset = 1040)

PCI_ERR1 is used by the system bus to PCI bus bridge to log bus address <31:0>
pertaining to an error condition logged in CAP_ERR. This register always
captures PCI address <31:0>, even for a PCI DAC cycle. When the
PCI_ERR_VALID bit in CAP_ERR is clear, the contents are undefined.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 11 10 09 08 07 06 05 04 03 02 01 00

Failing Address ADDR<31:0>
PKW0551C-97

Table 5-6 PCI Error Status Register 1
Name

Bits

Type

Initial
State

ADDR<31:0>

<31:0>

Description
Contains address bits
<31:0> of the transaction
on the PCI bus when an
error is detected.

Error Registers

5-14

Chapter 6
Removal and Replacement
This chapter describes removal and replacement procedures for field-replaceable units
(FRUs).

6.1

System Safety

Observe the safety guidelines in this section to prevent personal injury.

CAUTION: Wear an antistatic wrist strap whenever you work on a system.
WARNING: When the system interlocks are disabled and the system is still powered
on, voltages are low in the system, but current is high. Observe the following
guidelines to prevent personal injury.
1.
2.

Remove any jewelry that may conduct electricity before working on the system.
If you need to access the system card cage, power down the system and wait 2
minutes to allow components in that area to cool.

Removal and Replacement

6-1

6.2

FRU List

Figure 6-1 shows the locations of FRUs, and Table 6-1 lists the part numbers of all
field-replaceable units.

Figure 6-1 System FRU Locations
CD-ROM
CPUs
CPU

SCSI
Disks

OCP and
Display

Floppy

Memory

Power
Supplies

I/O Options

PKW0521-97

Removal and Replacement

6-2

Table 6-1 Field-Replaceable Unit Part Numbers
CPU Modules
B3007-AA

400 MHz CPU 4 Mbyte cache

B3007-CA

533 MHz CPU, 4 Mbyte cache

Memory Modules
54-25084-DA
20-47405-D3

32 Mbyte DIMM (synchronous)

54-25092-DA
20-45619-D3

128 Mbyte DIMM (synchronous)

54-25149-01

Memory riser card

System Backplane, Display, and support hardware
54-25147-01

System motherboard

RX23L-AB

Floppy
CD-ROM

54-23302-02

OCP assembly

70-31349-01

Speaker assembly

Fans
70-31351-01

Cooling fan 120x120

70-31350-01

Cooling fan 92x92

12-24701-34

CPU fan

Power System Components
30-43120-02

Power supply

SCSI Hardware
54-23365-01

SCSI backplane
Ultra SCSI bus extender

Removal and Replacement

6-3

Table 6-1 Field-Replaceable Unit Part Numbers (continued)
Power Cords
BN26J-1K

North America, Japan 12V, 75-inches long

BN19H-2E

Australia, New Zealand, 2.5m long

BN19C-2E

Central Europe, 2.5m long

BN19A-2E

UK, Ireland, 2.5m long

BN19E-2E

Switzerland 2.5m long

BN19K-2E

Denmark, 2.5m long

BN19Z-2E

Italy, 2.5m long

BN19S-2E

Egypt, India, South Africa, 2.5m long

BN18L-2E

Israel, 2.5m long

Ultra SCSI Cables and
Jumpers

From

17-04143-01

68 pin con cable

SCSI controller

Ultra SCSI bus extender

17-04022-03

68 pin con cable

Ultra SCSI bus
extender

SCSI backpln signal con

17-04021-01

68 pin con jumpr

SCSI backpln

17-04019-02

68 pin con cable

External prt on
SCSI backpln

Terminator

12-41768-03

68 pin terminator

End or 17-04019-02

Removal and Replacement

6-4

Table 6-1 Field-Replaceable Unit Part Numbers (continued)
System Cables and
Jumpers

From

17-01495-01

Current share
cable

Current share
conn on PS0

Current share conn on
PS1

17-03970-02

Floppy signal
cable (34 pin)

Floppy conn
on mbrd

Floppy

17-03971-01

OCP signal

OCP conn on
mbrd

OCP signal

Twisted pair
(yellow and green)

J2 RCM conn
on mbrd

Power conn on OCP

Twisted pair (red
and black)

OCP

Interlock switch pigtail

70-31348-01

Interlock switch
and pigtail cable

Interlock
switch assy

Twisted pair (red and
black) OCP DC enable
pwr cable from OCP conn

17-04685-01

SCSI CD-ROM
sig cable

CD-ROM
conn on mbrd

CD-ROM sig conn

70-37346-01

Power harness

Power
supply(s)

3 conns. On sys mbrd
CD-ROM drv pwr
Floppy pwr
Optional drive above Flop
Single ultra SCSI config
StorageWorks backpln
and pwr cable to Ultra
SCSI bus extender
Dual Ultra SCSI config
two pwr cables to two
SCSI bus extenders

17-04700-01

Power cable to
Ultra SCSI bus
extndr(s) Y
cable(s)

Ultra SCSI bus
extndr(s) pwr
and StrWrks
backpln

Power harness

Removal and Replacement

6-5

6.3

System Exposure

The system has three sheet metal covers, one on top and one on each side. The
covers are removed to expose the system card cage and the power/SCSI sections.

Figure 6-2 Exposing the System
Top Cover
Release Latch

Removal and Replacement

6-6

Exposing the System
CAUTION: Be sure the system On/Off button is in the “off” position before removing
system covers.
1.

Shutdown the operating system.

Press the On/Off button to turn the system off.

Unlock and open the door that exposes the storage shelf.

Pull down the top cover latch shown in Figure 6-2 until it latches in the down
position.

Grasp the finger groove at the rear of the top cover and pull it straight back about
2 inches and then lift it off the cabinet.

Pull a side panel back a few inches, tilt the top away from the machine, and lift it
off. (Repeat for the other side)

Dressing the System
Reverse the steps in the exposure process.

Removal and Replacement

6-7

6.4

CPU Removal and Replacement

CAUTION: Several different CPU modules work in these systems. Unless you are
upgrading the system be sure you are replacing the CPU you are removing with the
same variant of CPU.

Figure 6-3 Removing CPU Module

WARNING: CPU modules and memory modules have parts that operate at high
temperatures. Wait 2 minutes after power is removed before touching any module.

Removal and Replacement

6-8

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

Remove the memory riser card next to the CPU you are removing (see Section
6.6).

Loosen the two captive screws holding the module to the card cage.

The CPU is held in place with levers at both ends; simultaneously pull the levers
away from the module handle and pull the CPU from the cage.

Replacement
Reverse the steps in the Removal procedure.
Verification — DIGITAL UNIX and OpenVMS Systems
1.

Bring the system up to the SRM console by pressing the Halt button, if necessary.

Issue the show cpu command to display the status of the new module.

Verification — Windows NT Systems
1.

Start AlphaBIOS Setup, select Display System Configuration, and press Enter.

Using the arrow keys, select MC Bus Configuration to display the status of the
new module.

Removal and Replacement

6-9

6.5

CPU Fan Removal and Replacement

Figure 6-4 Removing CPU Fan

PKW-0516-97

Removal and Replacement

6-10

Removal
1.

Follow the CPU Removal and Replacement procedure.

Unplug the fan from the module.

Remove the four Phillips head screws holding the fan to the Alpha chip’s
heatsink.

Replacement
Reverse the above procedure.
Verification
If the system powers up, the CPU fan is working.

Removal and Replacement

6-11

6.6

Memory Riser Card Removal and
Replacement

CAUTION: Several different memory DIMMs work in these systems. Be sure you are
replacing the broken DIMM with the same variant.

Figure 6-5 Removing Memory Riser Card

,3%

WARNING: CPU modules and memory riser cards have parts that operate at high
temperatures. Wait 2 minutes after power is removed before touching any module.

Removal and Replacement

6-12

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

There are two riser cards, one High and one Low. After you have determined
which should be removed, loosen the two captive screws that secure the riser card
to the card cage.

Lift the riser card from the card cage.

Replacement
Reverse the steps in the Removal procedure.
NOTE: Memory DIMMs are installed in pairs and it is important that the pairs are
the same size. When you replace a bad DIMM, be sure to replace it with the same size
DIMM as the one you removed.
Verification — DIGITAL UNIX and OpenVMS Systems
1.

Bring the system up to the SRM console by pressing the Halt button, if necessary.

Issue the show memory command to display the status of the new memory.

Verify the functioning of the new memory by issuing the command test memn,
where n is 0, 1, 2, 3, or *.

Verification — Windows NT Systems
1.

Start AlphaBIOS Setup, select Display System Configuration, and press Enter.

Using the arrow keys, select Memory Configuration to display the status of the
new memory.

Switch to the SRM console (press the Halt button in so that the LED on the button
lights and reset the system). Verify the functioning of the new memory by issuing
the command test memn, where n is 0, 1, 2, 3, or *.

Removal and Replacement

6-13

6.7

DIMM Removal and Replacement

Figure 6-6 Removing a DIMM from a Memory Riser Card

DIMM
Riser Card

7
6
5
4
3
2

1
0

Largest DIMM
goes here.

PKW0505B-97

Removal and Replacement

6-14

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

Remove the memory riser card that has the broken memory DIMM (see Section
6.6).

There are prying/retaining levers on the connectors in each slot on the riser card.
Press both levers in an arc away from the DIMM and gently pull the DIMM from
the connector.

Replacement
Reverse the steps in the Removal procedure.
Verification
Follow the verification procedure recommended for the memory riser card, Section
6.6.

Removal and Replacement

6-15

6.8

System Motherboard Removal and
Replacement

Figure 6-7 Removing System Motherboard

Module
Brace

System Motherboard

PKW0518-97

Removal and Replacement

6-16

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

Remove both memory riser cards.

Remove all CPUs.

Remove all PCI and EISA options.

From the back of the cabinet, using a Phillips head screwdriver, unscrew the four
screws holding the CPU and memory riser card brace from the system frame.
Remove the brace.

Unplug all cables connected to the motherboard and clear access to all screws
holding the motherboard in place.

Using a Phillips head screwdriver unscrew the eleven screws holding the
motherboard in place and remove it from the system. Note the two guide studs,
one in the upper right corner and the other in the lower left corner, that protrude
through holes in the motherboard.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system (press the Halt button if necessary to bring up the SRM console)
and issue the show device command at the console prompt to verify that the system
sees all system options and peripherals.

Removal and Replacement

6-17

6.9

PCI/EISA Option Removal and Replacement

Figure 6-8 Removing PCI/EISA Option

Slot Cover
Screws

Option Card
IP00225

WARNING: To prevent fire, use only modules with current limited outputs. See
National Electrical Code NFPA 70 or Safety of Information Technology Equipment,
Including Electrical Business Equipment EN 60 950.

Removal and Replacement

6-18

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

To remove the faulty option: Disconnect cables connected to the option. Remove
cables to other options that obstruct the option you are removing. Unscrew the
small Phillips head screw securing the option to the card cage. Slide it from the
system.

Replacement
Reverse the steps in the Removal procedure.
Verification — DIGITAL UNIX and OpenVMS Systems
1.

Power up the system (press the Halt button if necessary to bring up the SRM
console) and run the ECU to restore EISA configuration data.

Issue the show config command or show device command at the console prompt
to verify that the system sees the option you replaced.

Run any diagnostic appropriate for the option you replaced.

Verification — Windows NT Systems
1.

Start AlphaBIOS Setup, select Display System Configuration, and press Enter.

Using the arrow keys, select PCI Configuration or EISA Configuration to
determine that the new option is listed.

Removal and Replacement

6-19

6.10 Power Supply Removal and Replacement
Figure 6-9 Removing Power Supply
4 rear screws
6/32 inch

Power
Supply 1

Power
Supply 0

2 internal
screws 3.5 mm
PKW0517-97

Removal and Replacement

6-20

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

Unplug the power supply you are replacing.

Remove the four screws at the back of the system cabinet and the two screws at
the back of the power supply that hold the power supply in place.

If you are removing power supply 0, slide the supply out the side of the cabinet.
If you are removing power supply 1, lift the supply out the top of the cabinet.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system.

Removal and Replacement

6-21

6.11 Power Harness Removal and Replacement
Figure 6-10 Removing Power Harness

To Floppy and
Optional Device
Cable
Clip

To CD-ROM and
StorageWorks Shelf

To Motherboard

To Power Supplies

Power Harness
(70-31346-01)

Current Share
(17-01495-01)
PKW0522-97

Removal and Replacement

6-22

Removal
1.

Shut down the operating system and power down the system.

Remove the AC power cords.

Expose both the card cage section and the power section of the system (see
Section 6.3).

Remove the cable clip between the two sections of the system.

Unplug the three cable connections to the motherboard and bend the cable back
over the power section of the system.

Unplug the cable connection to the floppy and, if applicable, to the optional
device above the floppy. Bend the cable back over the power section of the
system.

Unplug the cable connection to the CD-ROM.

Unplug the cable connection to the StorageWorks backplane.

Remove the power harness from the system.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system.

Removal and Replacement

6-23

6.12 System Fan Removal and Replacement
Figure 6-11 Removing System Fan

Cable to Fan 0
Cable to Fan 1

Fan 0
(17-31351-01)
Module Guides
Fan 1
(17-31350-01)

PKW0523-97

Removal and Replacement

6-24

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

Removing Fan 0
3.

Remove the CPU module(s).

Remove memory.

Trace the wire from the fan to the motherboard to determine which power cord to
unplug. Unplug the power cord to fan 0 and pass it through the sheet metal to the
fan compartment.

Remove the plastic module guides that interfere with access to the four Phillips
head screws holding the fan in place.

Unscrew the fan from the frame and remove it from the system.

Removing Fan 1
3.

Remove any PCI modules that prevent access to the four Phillips head screws that
hold fan 1 in place.

Remove any plastic module guides that prevent access to the Phillips head screws
that hold fan 1 in place.

Trace the wire from the fan to the motherboard to determine which power cord to
unplug. Unplug the power cord to fan 1 and pass it through the sheet metal to the
fan compartment.

Unscrew the fan from the frame and remove it from the system.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system. If the fan you installed is faulty, the system will not power up.

Removal and Replacement

6-25

6.13 Cover Interlock Removal and Replacement
Figure 6-12 Removing Cover Interlock
Interlock
Switch

1
PKW0519A-97

Removal and Replacement

6-26

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

Loosen the screw that holds the CD-ROM bracket to the system (➊ in Figure
6-12).

Detach both the power and the signal connectors at the rear of the CD-ROM.

Pull the CD-ROM and the bracket a short distance toward the rear of the system
and lift them out of the cabinet.

Unplug the interlock switch’s pigtail cable from the cable it is connected to.

Remove the two screws holding the interlock in place and remove the interlock
(➋).

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system. If the switch is faulty, the system will not power up.

Removal and Replacement

6-27

6.14 Operator Control Panel Removal and
Replacement
Figure 6-13 Removing the OCP

PKW-0501A-97

Removal and Replacement

6-28

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

To remove the StorageWorks door:
a.

Open the door slightly and grab the left edge of the door with your left hand
and the right edge of the door with your right hand.

While pushing the door up, bend it by pulling it away from the system. The
door compresses enough so its bottom post slips out of its retaining hole.

Once the bottom of the door is free, gently pull the top down to release it
from the post on the door jam and release it from the spring.

Put the door aside.

Using a Phillips head screwdriver, remove the nine screws holding the molded
plastic front panel to the system. (Six screws are accessed from the front of the
system and three through the fan compartment of the system.)

Tilt the front panel away from the system and disconnect all the cables from the
OCP.

Once the front panel is removed, unscrew the four screws holding the OCP to the
front panel.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system. If the OCP you installed is faulty, the system will not power up.

Removal and Replacement

6-29

6.15 CD-ROM Removal and Replacement
Figure 6-14 Removing CD-ROM

PKW0519-97

Removal and Replacement

6-30

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

Loosen the two screws holding the CD-ROM to its bracket (see Figure 6-14).

Detach both the power and signal connectors at the rear of the CD-ROM.

Pull the CD-ROM forward out of the system.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system. Use the following SRM console commands to test the floppy:
P00>>> show dev ncr0
P00>>> HD buf/dka nnn
where nnn is the device number; for example, dka500.

Removal and Replacement

6-31

6.16 Floppy Removal and Replacement
Figure 6-15 Removing Floppy

PKW0520-97

Removal and Replacement

6-32

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

Remove the two Phillips head screws holding the floppy in the system (➊ in
Figure 6-15).

Slide the floppy out the front of the system.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system (press the Halt button if necessary to bring up the SRM console).
Use the following SRM console commands to test the CD-ROM:
P00>>> show dev floppy
P00>>> HD buf/dva0

Removal and Replacement

6-33

6.17 SCSI Disk Removal and Replacement
Figure 6-16 Removing StorageWorks Disk

PKW0501B-97

Removal and Replacement

6-34

Removal
1.

Shut down the operating system and power down the system.

Open the front door exposing the StorageWorks disks.

Pinch the clips on both sides of the disk and slide it out of the shelf.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system. Use the show device console commands to verify that the
system sees the disk you replaced.

Removal and Replacement

6-35

6.18 StorageWorks Backplane Removal and
Replacement
Figure 6-17 Removing StorageWorks Backplane
StorageWorks
Backplane

Ultra SCSI
bus extender
(optional)

Ultra SCSI
bus extender

PKW0522B-97

Removal and Replacement

6-36

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system (see Section 6.3).

Remove the power and signal cables from the Ultra SCSI bus extender on the side
of the StorageWorks shelf.

Remove the power harness and all signal cables from the StorageWorks
backplane.

Using a short Phillips head screwdriver, remove the screws holding the backplane
to the back of the shelf and remove from the system.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system. Use the show device console command to verify that the
StorageWorks shelf is configured into the system.

Removal and Replacement

6-37

6.19 StorageWorks Ultra SCSI Bus Extender
Removal and Replacement
Figure 6-18 Removing StorageWorks Ultra SCSI Bus Extender

StorageWorks
Backplane

Ultra SCSI
bus extender
(optional)

Ultra SCSI
bus extender

PKW0522B-97

Removal and Replacement

6-38

Removal
1.

Shut down the operating system and power down the system.

Expose the card cage side of the system. See Section 6.3.

Remove the power and signal cables from the Ultra SCSI bus extender on the side
of the StorageWorks shelf.

On early systems the Ultra SCSI bus extender is stuck to the side of the
StorageWorks enclosure with adhesive standoffs; in later systems it is mounted on
plastic standoffs to which it snaps. If the system has the adhesive, simply pry
each corner of the extender free and remove it. If the system has plastic mounts,
pinch each with a pair of pliers, free the corner, and pull the bus extender from the
enclosure.

Replacement
Reverse the steps in the Removal procedure.
Verification
Power up the system. Use the show device console command to verify that the
StorageWorks shelf is configured into the system.

Removal and Replacement

6-39

Appendix A
Running Utilities
This appendix provides a brief overview of how to load and run utilities. The
following topics are covered:
•

Running Utilities from a Graphics Monitor

•

Running Utilities from a Serial Terminal

•

Running ECU

•

Running RAID Standalone Configuration Utility

•

Updating Firmware with LFU

•

Updating Firmware from AlphaBIOS

•

Upgrading AlphaBIOS

Running Utilities

A-1

A.1

Running Utilities from a Graphics Monitor

Start AlphaBIOS and select Utilities from the menu. The next selection depends
on the utility to be run. For example, to run ECU, select Run ECU from floppy.
To run RCU, select Run Maintenance Program.

Figure A-1 Running a Utility from a Graphics Monitor
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PK-0729-96

Running Utilities

A-2

A.2

Running Utilities from a Serial Terminal

Utilities are run from a serial terminal in the same way as from a graphics
monitor. The menus are the same, but some keys are different.

Table A-1 AlphaBIOS Option Key Mapping
AlphaBIOS Key

VTxxx Key

Ctrl/A

Ctrl/B

Ctrl/C

Ctrl/D

Ctrl/E

Ctrl/F

Ctrl/P

Ctrl/R

Ctrl/T

F10

Ctrl/U

Insert

Ctrl/V

Delete

Ctrl/W

Backspace

Ctrl/H

Escape

Ctrl/[

Running Utilities

A-3

A.3

Running ECU

The EISA Configuration Utility (ECU) is used to configure EISA options on these
systems. The ECU can be run either from a graphics monitor or a serial
terminal.

Start AlphaBIOS Setup. If the system is in the SRM console, issue the command
alphabios. (If the system has a graphics monitor, you can set the SRM console
environment variable to graphics.)

From AlphaBIOS Setup, select Utilities, then select Run ECU from floppy…
from the submenu that displays, and press Enter.
NOTE: The EISA Configuration Utility is supplied on diskettes shipped with the
system. There is a diskette for Microsoft Windows NT and a diskette for DIGITAL
UNIX and OpenVMS.

Insert the correct ECU diskette for the operating system and press Enter to run it.

The ECU main menu displays the following options:
EISA Configuration Utility
Steps in configuring your computer
STEP 1:
STEP 2:
STEP 3:
STEP 4:
STEP 5:

Important EISA configuration information
Add or remove boards
View or edit details
Examine required details
Save and exit

NOTE: Step 1 of the ECU provides online help. It is recommended that you select
this step and become familiar with the utility before proceeding.

Running Utilities

A-4

A.4

Running RAID Standalone Configuration Utility

The RAID Standalone Configuration Utility is used to set up RAID disk drives
and logical units. The Standalone Utility is run from the AlphaBIOS Utility
menu.

These systems support the KZPSC-xx PCI RAID controller (SWXCR). The KZPSCxx kit includes the controller, RAID Array 230 Subsystems software, and
documentation.
1.

Start AlphaBIOS Setup. If the system is in the SRM console, issue the command
alphabios. (If the system has a graphics monitor, you can set the SRM console
environment variable to graphics.)

At the Utilities screen, select Run Maintenance Program. Press Enter.

In the Run Maintenance Program dialog box, type swxcrmgr in the Program
Name: field.

4. Press Enter to execute the program. The Main menu displays the following
options:
[01.View/Update Configuration]
02.Automatic Configuration
03.New Configuration
04.Initialize Logical Drive
05.Parity Check
06.Rebuild
07.Tools
08.Select SWXCR
09.Controller Setup
10.Diagnostics
Refer to the RAID Array Subsystems documentation for information on using the
Standalone Configuration Utility to set up RAID drives.

Running Utilities

A-5

A.5

Updating Firmware with LFU

Start the Loadable Firmware Update (LFU) utility by issuing the lfu command at
the SRM console prompt or by selecting Update AlphaBIOS in the AlphaBIOS
Setup screen. LFU is part of the SRM console.

Example A–1 Starting LFU from the SRM Console
P00>>> lfu
***** Loadable Firmware Update Utility *****
Select firmware load device (cda0, dva0, ewa0), or
Press <return> to bypass loading and proceed to LFU: cda0
.
UPD>

Figure A-2 Starting LFU from the AlphaBIOS Console

AlphaBIOS Setup

Display System Configuration...
Upgrade AlphaBIOS
Hard Disk Setup
CMOS Setup...
Install Windows NT
Utilities
About AlphaBIOS...

Press ENTER to upgrade your AlphaBIOS from floppy or CD-ROM.

ESC=Exit
PK-0726A-96

Running Utilities

A-6

Use the Loadable Firmware Update (LFU) utility to update system firmware.
You can start LFU from either the SRM console or the AlphaBIOS console.
•

From the SRM console, start LFU by issuing the lfu command.

•

From the AlphaBIOS console, select Upgrade AlphaBIOS from the AlphaBIOS
Setup screen (see Figure A-2).

A typical update procedure is:
1.

Start LFU.

Use the LFU list command to show the revisions of modules that LFU can update
and the revisions of update firmware.

Use the LFU update command to write the new firmware.

Use the LFU exit command to exit back to the console.

The sections that follow show examples of updating firmware from the local CDROM, the local floppy, and a network device. Following the examples is an LFU
command reference.

Example A–2 Booting LFU from the CD-ROM
P00>>> show dev ncr0
polling ncr0 (NCR 53C810) slot 1, bus 0 PCI, hose 1 SCSI Bus ID 7
dka500.5.0.1.1
DKa500
RRD46 1645
P00>>> boot dka500
(boot dka500.5.0.1.1 -flags 0,0)
block 0 of dka500.5.0.1.1 is a valid boot block
.
.
.
jumping to bootstrap code
The default bootfile for this platform is
[AS1200]AS1200_LFU.EXE
Hit <RETURN> at the prompt to use the default bootfile.

Running Utilities

A-7

A.5.1

Updating Firmware from the CD-ROM

Insert the update CD-ROM, start LFU, and select cda0 as the load device.

Example A–3 Updating Firmware from the CD-ROM
***** Loadable Firmware Update Utility *****
Select firmware load device (cda0, dva0, ewa0), or
Press <return> to bypass loading and proceed to LFU: cda0

➊
Please enter the name of the options firmware files list, or
Press <return> to use the default filename [AS1200FW]: AS1200CP

➋
Copying AS1200CP from DKA500.5.0.1.1 .
Copying [as1200]TCREADME from DKA500.5.0.1.1 .
Copying [as1200]TCSRMROM from DKA500.5.0.1.1
....................
Copying [as1200]TCARCROM from DKA500.5.0.1.1 .............
---------------------------------------------------------------Function
Description

➌
---------------------------------------------------------------Display
Displays the system’s configuration table.
Exit
Done exit LFU (reset).
List
Lists the device, revision, firmware name, and
update revision.
Lfu
Restarts LFU.
Readme
Lists important release information.
Update
Replaces current firmware with loadable data image.
Verify
Compares loadable and hardware images.
? or Help
Scrolls this function table.
---------------------------------------------------------------UPD> list

➍
Device
Revision
AlphaBIOS
srmflash

Current Revision
V5.32-0
V5.0-1

Filename
arcrom
srmrom

Update
V6.40-1
V6.0-3

Running Utilities

A-8

➊

Select the device from which firmware will be loaded. The choices are the
internal CD-ROM, the internal floppy disk, or a network device. In this example,
the internal CD-ROM is selected.

➋

Select the file that has the firmware update, or press Enter to select the default
file. The file options are:
AS1200FW (default)

SRM console, AlphaBIOS console, and I/O adapter
firmware

AS1200CP

SRM console and AlphaBIOS console firmware only

AS1200IO

I/O adapter firmware only

In this example the file for console firmware (AlphaBIOS and SRM) is selected.

➌
➍

The LFU function table and prompt (UPD>) display.
Use the LFU list command to determine the revision of firmware in a device and
the most recent revision of that firmware available in the selected file. In this
example, the resident firmware for each console (SRM and AlphaBIOS) is at an
earlier revision than the firmware in the update file.
Continued on next page

Running Utilities

A-10

Example A–3 Updating Firmware from the CD-ROM (Continued)

➎

UPD> update *

WARNING: updates may take several minutes to complete for each device.

Confirm update on: AlphaBIOS
AlphaBIOS

➏

[Y/(N)] y

DO NOT ABORT!
Updating to V6.40-1... Verifying V6.40-1... PASSED.

Confirm update on: srmflash

[Y/(N)] y

srmflash

DO NOT ABORT!
Updating to V6.0-3... Verifying V6.0-3... PASSED.

UPD> exit

➐

Running Utilities

A-11

➎

The update command updates the device specified or all devices. In this
example, the wildcard indicates that all devices supported by the selected update
file will be updated.

➏

For each device, you are asked to confirm that you want to update the firmware.
The default is no. Once the update begins, do not abort the operation. Doing so
will corrupt the firmware on the module.

➐

The exit command returns you to the console from which you entered LFU
(either SRM or AlphaBIOS).

Running Utilities

A-12

A.5.2

Updating Firmware from the Floppy Disk —
Creating the Diskettes

Create the update diskettes before starting LFU. See Section A.4.3 for an
example of the update procedure.

Table A-2 File Locations for Creating Update Diskettes on a PC
Console Update Diskette

I/O Update Diskette

AS1200FW.TXT

AS1200IO.TXT

AS1200CP.TXT

TCREADME.SYS

CIPCA315.SYS

TCSRMROM.SYS

DFPAA310.SYS

TCARCROM.SYS

KZPAAA11.SYS

To update system firmware from floppy disk, you first must create the firmware
update diskettes. You will need to create two diskettes: one for console updates, and
one for I/O.
1.

Download the update files from the Internet.

On a PC, copy files onto two FAT-formatted diskettes.

From an OpenVMS system, copy files onto two ODS2-formatted diskettes as shown
in Example A–4.

Running Utilities

A-13

Example A–4 Creating Update Diskettes on an OpenVMS
System
Console Update Diskette
$ inquire ignore "Insert blank HD floppy in DVA0, then continue"
$ set verify
$ set proc/priv=all
$ init /density=hd/index=begin dva0: tcods2cp
$ mount dva0: tcods2cp
$ create /directory dva0:[as1200]
$ copy tcreadme.sys dva0:[as1200]tcreadme.sys
$ copy as1200fw.txt dva0:[as1200]as1200fw.txt
$ copy as1200cp.txt dva0:[as1200]as1200cp.txt
$ copy tcsrmrom.sys dva0:[as1200]tcsrmrom.sys
$ copy tcarcrom.sys dva0:[as1200]tcarcrom.sys
$ dismount dva0:
$ set noverify
$ exit
I/O Update Diskette
$ inquire ignore "Insert blank HD floppy in DVA0, then continue"
$ set verify
$ set proc/priv=all
$ init /density=hd/index=begin dva0: tcods2io
$ mount dva0: tcods2io
$ create /directory dva0:[as1200]
$ create /directory dva0:[options]
$ copy tcreadme.sys dva0:[as1200]tcreadme.sys
$ copy as1200fw.txt dva0:[as1200]as1200fw.txt
$ copy as1200io.txt dva0:[as1200]as1200io.txt
$ copy cipca315.sys dva0:[options]cipca315.sys
$ copy dfpaa310.sys dva0:[options]dfpaa310.sys
$ copy kzpsaA10.sys dva0:[options]kzpsaa10.sys
$ dismount dva0:
$ set noverify
$ exit

Running Utilities

A-14

A.5.3

Updating Firmware from the Floppy Disk —
Performing the Update

Insert an update diskette (see Section A.5.2) into the floppy drive. Start LFU and
select dva0 as the load device.

Example A–5 Updating Firmware from the Floppy Disk
***** Loadable Firmware Update Utility *****
Select firmware load device (cda0, dva0, ewa0), or
Press <return> to bypass loading and proceed to LFU: dva0

➊

Please enter the name of the options firmware files list, or
Press <return> to use the default filename [AS1200IO,(AS1200CP)]:
➋
AS1200IO
Copying AS1200IO from DVA0 .
Copying TCREADME from DVA0 .
Copying CIPCA315 from DVA0 .
Copying DFPAA252 from DVA0 ...
Copying KZPSAA11 from DVA0 ...
.
. (The function table displays, followed by the UPD> prompt, as
. shown in Example A–3.)

➌

UPD> list
Device
AlphaBIOS
pfi0
srmflash

Current Revision
V5.12-3
2.46
T3.2-21

Filename
arcrom
dfpaa_fw
srmrom
cipca_fw
kzpsa_fw

Update Revision
Missing file
2.52
Missing file
A315
A11
Continued on next page

Running Utilities

A-15

➊

Select the device from which firmware will be loaded. The choices are the
internal CD-ROM, the internal floppy disk, or a network device. In this example,
the internal floppy disk is selected.

➋

Select the file that has the firmware update, or press Enter to select the default
file. When the internal floppy disk is the load device, the file options are:
AS1200CP (default)

SRM console and AlphaBIOS console firmware only

AS1200IO

I/O adapter firmware only

The default option in Example A–3 (AS1200FW) is not available, since the file
is too large to fit on a 1.44 MB diskette. This means that when a floppy disk is
the load device, you can update either console firmware or I/O adapter firmware,
but not both in the same LFU session. If you need to update both, after finishing
the first update, restart LFU with the lfu command and insert the floppy disk
with the other file.
In this example the file for I/O adapter firmware is selected.

➌

Use the LFU list command to determine the revision of firmware in a device and
the most recent revision of that firmware available in the selected file. In this
example, the update revision for console firmware displays as “Missing file”
because only the I/O firmware files are available on the floppy disk.
Continued on next page

Running Utilities

A-16

Example A–5 Updating Firmware from the Floppy Disk
(Continued)

➍

UPD> update pfi0

WARNING: updates may take several minutes to complete for each device.

Confirm update on: pfi0
pfi0

➎

[Y/(N)] y

DO NOT ABORT!
Updating to 3.10... Verifying to 3.10... PASSED.

➏

UPD> lfu
***** Loadable Firmware Update Utility *****
Select firmware load device (cda0, dva0, ewa0), or
Press <return> to bypass loading and proceed to LFU: dva0

Please enter the name of the options firmware files list, or
Press <return> to use the default filename [AS1200IO, (AS1200CP)]:➐
.
. (The function table displays, followed by the UPD> prompt.
. Console firmware can now be updated.)
UPD> exit

➑

Running Utilities

A-17

➍
➎

The update command updates the device specified or all devices.

➏

The lfu command restarts the utility so that console firmware can be updated.
(Another method is shown in Example A–6, where the user specifies the file
AS1200FW and is prompted to insert the second diskette.)

➐

The default update file, AS1200CP, is selected. The console firmware can now
be updated, using the same procedure as for the I/O firmware.

➑

The exit command returns you to the console from which you entered LFU
(either SRM or AlphaBIOS).

Example A–6 Selecting AS1200FW to Update Firmware from the
Floppy Disk
P00>>> lfu
***** Loadable Firmware Update Utility *****
Select firmware load device (cda0, dva0, ewa0), or
Press <return> to bypass loading and proceed to LFU: dva0
Please enter the name of the firmware files list, or
Press <return> to use the default filename [AS1200IO,(AS1200CP)]: as1200fw
Copying AS1200FW from DVA0 .
Copying TCREADME from DVA0 .
Copying TCSRMROM from DVA0 ..........................
Copying TCARCROM from DVA0 ...............
Copying CIPCA315 from DVA0
Please insert next floppy containing the firmware,
Press <return> when ready. Or type DONE to abort.
Copying CIPCA315 from DVA0 .
Copying DFPAA310 from DVA0 ...
Copying KZPSAA10 from DVA0 ...
.
.
.

Running Utilities

A-18

A.5.4

Updating Firmware from a Network Device

Copy files to the local MOP server’s MOP load area, start LFU, and select ewa0
as the load device.

Example A–7 Updating Firmware from a Network Device
***** Loadable Firmware Update Utility *****
Select firmware load device (cda0, dva0, ewa0), or
Press <return> to bypass loading and proceed to LFU: ewa0

➊

Please enter the name of the options firmware files list, or
Press <return> to use the default filename [AS1200FW]:

➋

Copying AS1200FW from EWA0 .
Copying TCREADME from EWA0 .
Copying TCSRMROM from EWA0 ...........................
Copying TCARCROM from EWA0 ............
Copying CIPCA315 from EWA0 .
Copying DFPAA310 from EWA0 ...
Copying KZPSAA11 from EWA0 ...
.
.

[The function table displays, followed by the UPD>
prompt, as shown in Example A–3.]

.
UPD> list
Device
AlphaBIOS
kzpsa0
kzpsa1
srmflash

➌
Current Revision
V5.12-2
A10
A10
V1.0-9

Filename
arcrom
kzpsa_fw
kzpsa_fw
srmrom
cipca_fw
dfpaa_fw

Update Revision
V6.40-1
A11
A11
V6.0-3
A315
2.46
Continued on next page

Running Utilities

A-19

Before starting LFU, download the update files from the Internet (see Preface). You
will need the files with the extension .SYS. Copy these files to your local MOP
server’s MOP load area.

➊

Select the device from which firmware will be loaded. The choices are the
internal CD-ROM, the internal floppy disk, or a network device. In this example,
a network device is selected.

➋

Select the file that has the firmware update, or press Enter to select the default
file. The file options are:
AS1200FW (default)

SRM console, AlphaBIOS console, and I/O adapter
firmware

AS1200CP

SRM console and AlphaBIOS console firmware only

AS1200IO

I/O adapter firmware only

In this example the default file, which has both console firmware (AlphaBIOS
and SRM) and I/O adapter firmware, is selected.

➌

Use the LFU list command to determine the revision of firmware in a device and
the most recent revision of that firmware available in the selected file. In this
example, the resident firmware for each console (SRM and AlphaBIOS) and I/O
adapter is at an earlier revision than the firmware in the update file.
Continued on next page

Running Utilities

A-20

Example A–7 Updating Firmware from a Network Device
(Continued)
UPD> update * -all
➍
WARNING: updates may take several minutes to complete for each
device.
AlphaBIOS

DO NOT ABORT!
Updating to V6.40-1... Verifying V6.40-1... PASSED.

kzpsa0

DO NOT ABORT!
Updating to A11
... Verifying A11... PASSED.

kzpsa1

DO NOT ABORT!
Updating to A11
... Verifying A11... PASSED.

srmflash

DO NOT ABORT!
Updating to V6.0-3... Verifying V6.0-3... PASSED.

UPD> exit

➎

Running Utilities

A-21

➍

The update command updates the device specified or all devices. In this
example, the wildcard indicates that all devices supported by the selected update
file will be updated. Typically, LFU requests confirmation before updating each
console’s or device’s firmware. The -all option removes the update confirmation
requests.

➎

The exit command returns you to the console from which you entered LFU
(either SRM or AlphaBIOS).

Running Utilities

A-22

A.5.5

LFU Commands

The commands summarized in Table A-3 are used to update system firmware.

Table A-3 LFU Command Summary
Command

Function

display

Shows the system physical configuration.

exit

Terminates the LFU program.

help

Displays the LFU command list.

lfu

Restarts the LFU program.

list

Displays the inventory of update firmware on the selected device.

readme

Lists release notes for the LFU program.

update

Writes new firmware to the module.

verify

Reads the firmware from the module into memory and compares it
with the update firmware.

These commands are described in the following pages.

Running Utilities

A-23

display
The display command shows the system physical configuration. Display is equivalent
to issuing the SRM console command show configuration. Because it shows the slot
for each module, display can help you identify the location of a device.

exit
The exit command terminates the LFU program, causes system initialization and
testing, and returns the system to the console from which LFU was called.

help
The help (or ?) command displays the LFU command list, shown below.
--------------------------------------------------------------------Function
Description
--------------------------------------------------------------------Display
Displays the system’s configuration table.
Exit
Done exit LFU (reset).
List
Lists the device, revision, firmware name, and update
revision.
Lfu
Restarts LFU.
Readme
Lists important release information.
Update
Replaces current firmware with loadable data image.
Verify
Compares loadable and hardware images.
? or Help Scrolls this function table.
---------------------------------------------------------------------

lfu
The lfu command restarts the LFU program. This command is used when the update
files are on a floppy disk. The files for updating both console firmware and I/O
firmware are too large to fit on a 1.44 MB disk, so only one type of firmware can be
updated at a time. Restarting LFU enables you to specify another update file.

Running Utilities

A-24

list
The list command displays the inventory of update firmware on the CD-ROM,
network, or floppy. Only the devices listed at your terminal are supported for firmware
updates.
The list command shows three pieces of information for each device:
•

Current Revision — The revision of the device’s current firmware

•

Filename — The name of the file used to update that firmware

•

Update revision — The revision of the firmware update image

readme
The readme command lists release notes for the LFU program.

update
The update command writes new firmware to the module. Then LFU automatically
verifies the update by reading the new firmware image from the module into memory
and comparing it with the source image.
To update more than one device, you may use a wildcard but not a list. For example,
update k* updates all devices with names beginning with k, and update * updates all
devices. When you do not specify a device name, LFU tries to update all devices; it
lists the selected devices to update and prompts before devices are updated. (The
default is no.) The -all option removes the update confirmation requests, enabling the
update to proceed without operator intervention.
CAUTION: Never abort an update operation. Aborting corrupts the firmware on the
module.
verify
The verify command reads the firmware from the module into memory and compares
it with the update firmware. If a module already verified successfully when you
updated it, but later failed tests, you can use verify to tell whether the firmware has
become corrupted.

Running Utilities

A-25

A.6

Updating Firmware from AlphaBIOS

Insert the CD-ROM or diskette with the updated firmware and select Upgrade
AlphaBIOS from the main AlphaBIOS Setup screen. Use the Loadable Firmware
Update (LFU) utility to perform the update. The LFU exit command causes a
system reset.

Figure A-3 AlphaBIOS Setup Screen

AlphaBIOS Setup

Display System Configuration...
Upgrade AlphaBIOS
Hard Disk Setup
CMOS Setup...
Install Windows NT
Utilities
About AlphaBIOS...

Press ENTER to upgrade your AlphaBIOS from floppy or CD-ROM.

ESC=Exit
PK-0726A-96

Running Utilities

A-26

A.7

Upgrading AlphaBIOS

It may become necessary to upgrade AlphaBIOS to work with new versions of
Windows NT or when enhancements are made.

Use this procedure to upgrade from an earlier version of AlphaBIOS:
1.

Insert the diskette or CD-ROM containing the AlphaBIOS upgrade.

If you are not already running AlphaBIOS Setup, start it by restarting your
system and pressing F2 when the Boot screen is displayed.

In the main AlphaBIOS Setup screen, select Upgrade AlphaBIOS and press
Enter.
The system is reset and the Loadable Firmware Update (LFU) utility is started.
See Section A5.5 for LFU commands.

When the upgrade is complete, issue the LFU exit command. The system is reset
and you are returned to AlphaBIOS.
If you press the Reset button instead of issuing the LFU exit command, the
system is reset and you are returned to LFU.

Running Utilities

A-27

Appendix B
Halts, Console Commands, and
Environment Variables
This appendix discusses halting the system and provides a summary of the SRM
console commands and environment variables. The test command is described in
Chapter 3 of this document. For complete reference information on other SRM
commands and environment variables, see your system User’s Guide.
NOTE: It is recommended that you keep a list of the environment variable settings for
systems that you service, because you will need to restore certain environment
variable settings after swapping modules. Refer to Table B-4 for a convenient
worksheet.

Halts, Console Commands, and Environment Variables

B-1

B.1

Halt Button Functions

The Halt button causes the system to perform in various ways depending upon
the system state at the time the button is pressed.

When the halt button is pressed, results differ depending upon the state of the
machine. Table B-1 describes the full function of the halt button.

Table B-1 Results of Pressing the Halt Button
Machine State
OpenVMS running/hung
DIGITAL UNIX running/hung
Windows NT running/hung
AlphaBIOS running/hung
SRM console running

SROM (1st 2 secs. of pwr-up)
XSROM power-up
SRM console power-up

Result
SRM console runs
SRM console runs
Nothing
Nothing
Sets halt assertion flag: the SRM console
continues to run
Nothing
Sets halt assertion flag, auto boot ignored
Sets halt assertion flag, auto boot ignored

A simple halt causes suspension of a system that is hung or running DIGITAL UNIX
or OpenVMS and starts the SRM console.
The halt assertion flag is set in the TOY NVRAM; it is read and cleared by the console
only during power-up or reset. When the SRM console finds the halt assertion flag
set, the conditions of the environment variables auto_action = boot/restart and
os_type = NT are ignored; the SRM console runs and prints the following message:
Halt assertion detected
NVRAM power-up script not executed
AUTO_ACTION=BOOT/RESTART and OS_TYPE=NT ignored, if applicable
P00>>>

Halts, Console Commands, and Environment Variables

B-2

B.2

Using the Halt Button

Use the Halt button to halt the DIGITAL UNIX or OpenVMS operating system
when it hangs or you want to use the SRM console. Use the Halt button to force
Windows NT systems to bring up the SRM console rather than booting or halting
in AlphaBIOS.

Using Halt to Shut Down the Operating System
You can use the Halt button if the DIGITAL UNIX or OpenVMS operating system
hangs. Pressing the Halt button halts the operating system back to the SRM console
firmware. From the console, you can use the crash command to force a crash dump at
the operating system level.
The Windows NT operating system does not support halts on this system. Pressing
the Halt button during a Windows NT session has no effect.
Using Halt to Clear the Console Password
The SRM console firmware allows you to set a password to prevent unauthorized
access to the console. If you forget the password, the Halt button, with the login
command, lets you clear the password and regain control of the console. See Section
4.8 of your system User’s Guide.

Halts, Console Commands, and Environment Variables

B-3

B.3

Halt Assertion

A halt assertion allows you to disable automatic boots of the operating system so
that you can perform tasks from the SRM console.

Under certain conditions, you might want to force a “halt assertion.” A halt assertion
differs from a simple halt in that the SRM console “remembers” the halt. The next
time you power up, the system ignores the SRM power-up script (nvram) and ignores
any environment variables that you have set to cause an automatic boot of the
operating system. The SRM console displays this message:
Halt assertion detected
NVRAM power-up script not executed
AUTO_ACTION=BOOT/RESTART and OS_TYPE=NT ignored, if applicable
Halt assertion is useful for disabling automatic boots of the operating system when
you want to perform tasks from the SRM console. It is also useful for disabling the
SRM power-up script if you have accidentally inserted a command in the script that
will cause a system problem. These conditions are described in the sections
“Disabling Autoboot” and “Disabling the SRM Power-Up Script.”
You can force a halt assertion using the Halt button, the RCM halt command, or the
RCM haltin command. Observe the following guidelines for forcing a halt assertion.
Halt Assertion with Halt Button or RCM Halt Command
Press the Halt button on the local system (or enter the RCM halt command from a
remote system) while the system is powering up or the SRM console is running. The
system halts at the SRM console, and the halt status is saved. The next time the
system powers up, the saved halt status is checked.
NOTE: Wait 5 seconds after the system begins powering up before pressing the Halt
button or remotely entering the RCM halt command.
Halt Assertion with RCM Haltin Command
Enter the RCM haltin command at any time except during power-up. For example,
enter haltin during an operating system session or when the AlphaBIOS console is
running.
If you enter the RCM haltin command during a DIGITAL UNIX or OpenVMS
session, the system halts back to the SRM console, and the halt status is saved. The
next time the system powers up, the saved halt status is checked.
If you enter the RCM haltin command when Windows NT or AlphaBIOS is running,
the interrupt is ignored. However, you can enter the RCM haltin command followed

Halts, Console Commands, and Environment Variables

B-4

by the RCM reset command to force a halt assertion. Upon reset, the system powers
up to the SRM console, but the SRM console does not load the AlphaBIOS console.
Clearing a Halt Assertion
Clear a halt assertion as follows:
•

If the halt assertion was caused by pressing the Halt button or remotely entering
the RCM halt command, the console uses the halt assertion once, then clears it.

•

If the halt assertion was caused by entering the RCM haltin command, enter the
RCM haltout command or cycle power on the local system.

Disabling Autoboot
The system automatically boots the selected operating system at power-up or reset if
the following environment variables are set:
•

For DIGITAL UNIX and OpenVMS, the SRM environment variables os_type,
auto_action, bootdef_dev, boot_file, and boot_osflags

•

For Windows NT, the SRM os_type environment variable and the Auto Start
selection in the AlphaBIOS Standard CMOS Setup screen

You might want to prevent the system from autobooting so you can perform tasks
from the SRM console. Use one of the methods described previously to force a halt
assertion. When the SRM console prompt is displayed, you can enter commands to
configure or test the system. Chapter 4 of your system User’s Guide describes the
SRM console commands and environment variables.
Disabling the SRM Power-Up Script
The system has a power-up script (file) named “nvram” that runs every time the
system powers up. If you accidentally insert a command in the script that will cause a
system problem, disable the script by using one of the methods described previously to
force a halt assertion. When the SRM console prompt is displayed, edit the script to
delete the offending command. See Section 4.4 of your system User’s Guide for more
information on editing the nvram script.

Halts, Console Commands, and Environment Variables

B-5

B.4

Summary of SRM Console Commands

The SRM console commands are used to examine or modify the system state.

Table B-2 Summary of SRM Console Commands
Command

Function

alphabios

Loads and starts the AlphaBIOS console.

boot

Loads and starts the operating system.

clear envar

Resets an environment variable to its default value.

clear password

Sets the password to 0.

continue

Resumes program execution.

crash

Forces a crash dump at the operating system level.

deposit

Writes data to the specified address.

edit

Invokes the console line editor on a RAM file or on the nvram file
(power-up script).

examine

Displays the contents of a memory location, register, or device.

halt

Halts the specified processor. (Same as stop.)

help

Displays information about the specified console command.

info num

Displays various types of information about the system:
Info shows a list describing the num qualifier.
Info 3 reads the impure area that contains the state of the CPU
before it entered PAL mode.
Info 5 reads the PAL built logout area that contains the data used
by the operating system to create the error entry
Info 8 reads the IOD and IOD1 registers.

initialize

Resets the system.

lfu

Runs the Loadable Firmware Update Utility.
Continued on next page

Halts, Console Commands, and Environment Variables

B-6

Table B-2 Summary of SRM Console Commands (Continued)
Command

Function

Turns off secure mode, enabling access to all SRM console
commands during the current session.

man

Displays information about the specified console command.

Displays a file one screen at a time.

prcache

Initializes and displays status of the PCI NVRAM.

set envar

Sets or modifies the value of an environment variable.

set host

Connects to an MSCP DUP server on a DSSI device.

set password

Sets the console password or changes an existing password.

set rcm_dialout

Sets a modem dialout string.

set secure

Enables secure mode without requiring a restart of the console.

show envar

Displays the state of the specified environment variable.

show config

Displays the configuration at the last system initialization.

show cpu

Displays the state of each processor in the system.

show device

Displays a list of controllers and their devices in the system.

show fru

Displays the serial number and revision level of all options.

show memory

Displays memory module information.

show network

Displays the state of network devices in the system.

show pal

Displays the version of the privileged architecture library code
(PALcode).

show power

Displays information about the power supplies, system fans,
CPU fans, and temperature.

show rcm_dialout

Displays the modem dialout string.

show version

Displays the version of the console program.

start

Starts a program previously loaded on the processor specified.

stop

Halts the specified processor. (Same as halt.)

test

Runs firmware diagnostics for the system.

Halts, Console Commands, and Environment Variables

B-7

B.4.1

Summary of SRM Environment Variables

Environment variables pass configuration information between the console and
the operating system. Their settings determine how the system powers up, boots
the operating system, and operates. Environment variables are set or changed
with the set envar command and returned to their default values with the clear
envar command. Their values are viewed with the show envar command. The
SRM environment variables are specific to the SRM console.

Table B-3 Environment Variable Summary
Environment
Variable

Function

auto_action

Specifies the console’s action at power-up, a failure, or a reset.

bootdef_dev

Specifies the default boot device string.

boot_osflags

Specifies the default operating system boot flags.

com*_baud

Changes the default baud rate of the COM1 or the COM2
serial port.

console

Specifies the device on which power-up output is displayed
(serial terminal or graphics monitor).

cpu_enabled

Enables or disables a specific secondary CPU.

ew*0_mode

Specifies the connection type of the default Ethernet
controller.

ew*0_protocols

Specifies network protocols for booting over the Ethernet
controller.

kbd_hardware_
type

Specifies the default console keyboard type.

kzpsa*_host_id

Specifies the default value for the KZPSA host SCSI bus node
ID.

language

Specifies the console keyboard layout.
Continued on next page

Halts, Console Commands, and Environment Variables

B-8

Table B-3 Environment Variable Summary (Continued)
Environment
Variable

Function

memory_test

Specifies the extent to which memory will be tested. For
DIGITAL UNIX systems only.

ocp_text

Overrides the default OCP display text with specified text.

os_type

Specifies the operating system and sets the appropriate console
interface.

pci_parity

Disables or enables parity checking on the PCI bus.

pk*0_fast

Enables fast SCSI mode.

pk*0_host_id

Specifies the default value for a controller host bus node ID.

pk*0_soft_term

Enables or disables SCSI terminators on systems that use the
QLogic ISP1020 SCSI controller.

sys_model_num

Displays the system model number and computes certain
information passed to the operating system. Must be restored
after a PCI motherboard is replaced.

sys_serial_num

Restores the system serial number. Must be set if the system
motherboard is replaced.

sys_type

Displays the system type and computes certain information
passed to the operating system. Must be restored after a PCI
motherboard is replaced.

tga_sync_green

Specifies the location of the SYNC signal generated by the
DIGITAL ZLXp-E PCI graphics accelerator option.

tt_allow_login

Enables or disables login to the SRM console firmware on
other console ports.

Halts, Console Commands, and Environment Variables

B-9

B.5

Recording Environment Variables

This worksheet lists all environment variables. Copy it and record the settings
for each system. Use the show* command to list environment variable settings.

Table B-4 Environment Variables Worksheet
Environment
Variable

System Name

auto_action
bootdef_dev
boot_osflags
com1_baud
com2_baud
console
cpu_enabled
ew*0_mode
ew*0_protocols
kbd_hardware_
type
kzpsa*_host_id
language
memory_test
ocp_text
os_type
pci_parity
pk*0_fast
pk*0_host_id

Halts, Console Commands, and Environment Variables

B-10

Table B-4 Environment Variables Worksheet (Continued)
Environment
Variable

System Name

pk*0_soft_term
sys_model_num
sys_serial_num
sys_type
tga_sync_green
tt_allow_login

Halts, Console Commands, and Environment Variables

B-11

Appendix C
Managing the System Remotely
This chapter describes how to manage the system from a remote location using the
remote console manager (RCM). You can use the RCM from a console terminal at a
remote location. You can also use the RCM from the local console terminal.
Sections in this chapter are:
•

RCM Overview

•

First-Time Setup

•

RCM Commands

•

Dial-Out Alerts

•

Using the RCM Switchpack

•

Troubleshooting Guide

•

Modem Dialog Details

Managing the System Remotely

C-1

C.1 RCM Overview
The remote console manager (RCM) monitors and controls the system remotely.
The control logic resides on the system board.

The RCM is a separate console from the SRM and AlphaBIOS consoles. The RCM is
run from a serial console terminal or terminal emulator. A command interface lets you
reset, halt, and power the system on or off, regardless of the state of the operating
system or hardware. You can also use RCM to monitor system power and
temperature.
You can invoke the RCM either remotely or through the local serial console terminal.
Once in RCM command mode, you can enter commands to control and monitor the
system. Only one RCM session can be active at a time.
•

To connect to the RCM remotely, you dial in through a modem, enter a password,
and then type an escape sequence that invokes RCM command mode. You must
set up the modem before you can dial in remotely.

•

To connect to the RCM locally, you type the escape sequence at the SRM console
prompt on the local serial console terminal.

When you are not monitoring the system remotely, you can use the RCM dial-out alert
feature. With dial-out alerts enabled, the RCM dials a paging service to alert you
about a power failure within the system.
CAUTION: Do not issue RCM commands until the system has powered up. If you
enter certain RCM commands during power-up or reset, the system may hang. In that
case you would have to disconnect the power cord at the power outlet. You can,
however, use the RCM halt command during power-up to force a halt assertion. Refer
to Section B.3 for information on halt assertion.

Managing the System Remotely

C-2

C.2 First-Time Setup
To set up the RCM to monitor a system remotely, connect the console terminal
and modem to the ports at the back of the system, configure the modem port for
dial-in, and dial in.

Figure C-1 RCM Connections

VTxxx

RCM

PK-0906-97

Managing the System Remotely

C-3

C.2.1

Configuring the Modem

The RCM requires a Hayes-compatible modem. The controls that the RCM sends to
the modem are acceptable to a wide selection of modems. After selecting the modem,
connect it and configure it.
Qualified Modems
The modems that have been tested and qualified with this system are:
•

Motorola 3400 Lifestyle 28.8

•

AT&T Dataport 14.4/FAX

•

Hayes Smartmodem Optima 288 V-34/V.FC + FAX

Modem Configuration Procedure
1.

Connect a Hayes-compatible modem to the RCM as shown in Figure C-1, and
power up the modem.

From the local serial console terminal, type the following escape sequence to
invoke the RCM:
P00>>> ^]^]rcm
The character “^” is created by simultaneously holding down the Ctrl key and
pressing the ] key (right square bracket). The SRM prompt, RCM>, is displayed.

Use the setpass command to set a modem password.

Enable the modem port with the enable command.

Enter the quit command to leave the RCM.

You are now ready to dial in remotely.

Managing the System Remotely

C-4

C.2.2

Dialing In and Invoking RCM

To dial in to the RCM modem port, dial the modem, enter the modem password at the
# prompt, and type the escape sequence. Use the hangup command to terminate the
session.
A sample dial-in dialog would look similar to the following:

Example C–1 Sample Remote Dial-In Dialog
ATQ0V1E1S0=0
OK
ATDT30167
CONNECT 9600
#
RCM V2.0

➊

➋
➌

RCM>
Dialing In and Invoking RCM
1.

Dial the number for the modem connected to the modem port. See ➊ in Example
C–1 for an example.
The RCM prompts for a password with a “#” character. See ➋.

Enter the password that you set with the setpass command.
You have three tries to correctly enter the password. After three incorrect tries,
the connection is terminated, and the modem is not answered again for 5 minutes.
When you successfully enter the password, the RCM banner is displayed. See ➌.
You are connected to the system COM1 port, and you have control of the SRM
console.
NOTE: At this point no one at the local terminal can perform any tasks except for
typing the RCM escape sequence. The local terminal displays any SRM console
output entered remotely.

3. Type the RCM escape sequence (not echoed).
^]^]rcm
RCM>
NOTE: From RCM command mode, you can change the escape sequence for
invoking RCM, if desired. Use the setesc command to change the sequence. Be
sure to record the new escape sequence.

Managing the System Remotely

C-5

To terminate the modem connection, enter the RCM hangup command.
RCM> hangup
If the modem connection is terminated without using the hangup command or if
the line is dropped due to phone-line problems, the RCM will detect carrier loss
and initiate an internal hangup command. If the modem link is idle for more than
20 minutes, the RCM initiates an auto hangup.
NOTE: Auto hangup can take a minute or more, and the local terminal is locked
out until the auto hangup is completed.

C.2.3

Using RCM Locally

Use the default escape sequence to invoke the RCM mode locally for the first time.
You can invoke RCM from the SRM console, the operating system, or an application.
The RCM quit command reconnects the terminal to the system console port.
1.

To invoke the RCM locally, type the RCM escape sequence. See ➊ in Example
C–2 for the default sequence.
The escape sequence is not echoed on the terminal or sent to the system. At the
RCM> prompt, you can enter RCM commands.

To exit RCM and reconnect to the system console port, enter the quit command.
(see ➋). Press Return to get a prompt from the operating system or system
console.

Example C–2 Invoking and Leaving RCM Locally
P00>>> ^]^]rcm
RCM>

➊

➋
RCM> quit
Focus returned to COM port

Managing the System Remotely

C-6

C.3 RCM Commands
The RCM commands given in Table C-1 are used to control and monitor a
system remotely.

Table C-1 RCM Command Summary
Command

Function

alert_clr

Clears alert flag, stopping dial-out alert cycle

alert_dis

Disables the dial-out alert function

alert_ena

Enables the dial-out alert function

disable

Disables remote access to the modem port

enable

Enables remote access to the modem port

halt

Halts the server. Emulates pressing the Halt button and immediately
releasing it.

haltin

Causes a halt assertion. Emulates pressing the Halt button and
holding it in.

haltout

Terminates a halt assertion created with haltin. Emulates releasing
the Halt button after holding it in.

hangup

Terminates the modem connection

help or ?

Displays the list of commands

poweroff

Turns off power. Emulates pressing the On/Off button to the off
position.

poweron

Turns on power. Emulates pressing the On/Off button to the on
position.

quit

Exits console mode and returns to system console port

reset

Resets the server. Emulates pressing the Reset button.

setesc

Changes the escape sequence for invoking command mode

setpass

Changes the modem access password

status

Displays system status and sensors

Managing the System Remotely

C-7

Command Conventions
•
•
•
•
•

The commands are not case sensitive.
A command must be entered in full.
You can delete an incorrect command with the Backspace key before you press
Enter.
If you type a valid RCM command, followed by extra characters, and press Enter,
the RCM accepts the correct command and ignores the extra characters.
If you type an incorrect command and press Enter, the command fails with the
message:
*** ERROR - unknown command ***

alert_clr
The alert_clr command clears an alert condition within the RCM. The alert enable
condition remains active, and the RCM will again enter the alert condition if it detects
a system power failure.
RCM>alert_clr
alert_dis
The alert_dis command disables RCM dial-out. It also clears any outstanding alerts.
Dial-out remains disabled until the alert_enable command is issued. See also the
enable and disable commands.
RCM>alert_dis
alert_ena
The alert_ena command enables the RCM to automatically dial out when it detects a
power failure within the system. The RCM repeats the dial-out alert at 30-minute
intervals until the alert is cleared. Dial-out remains enabled until the alert_disable
command or the disable command is issued. See also the enable and disable
commands.
RCM>alert_ena

Managing the System Remotely

C-8

Two conditions must be met for the alert_enable command to work:
•

A modem dial-out string must be entered from the system console.

•

Remote access to the RCM modem port must be enabled with the enable
command.

If the alert_enable command is entered when remote access is disabled, the following
message is displayed:
*** error ***
disable
The disable command disables remote access to the RCM modem port. It also
disables RCM dial-out.
RCM>disable
When the modem is disabled, it remains disabled until the enable command is issued.
If a modem connection is in progress, entering the disable command terminates it.
NOTE: If the modem has been disabled from the RCM switchpack on the
motherboard, the enable command does not work. To enable the modem, reset the
switch 2 (MODEM OFF) on the switchpack to OFF (enabled). See Section C.5 for
information on the switchpack.
enable
The enable command enables remote access to the RCM modem port. It can take up
to 10 seconds for the enable command to be executed.
RCM>enable
When the modem is enabled, it remains enabled until the disable command is issued.

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The enable command can fail for the following reasons:
•

No modem access password was set.

•

The initialization string or the answer string might not be set properly. (See
Section C.7.)

•

The modem is not connected or is not working properly.

•

The modem has been disabled from the RCM switchpack. To enable the modem,
reset switch 2 (MODEM OFF) on the switchpack to OFF (enabled).

If the enable command fails, the following message is displayed:
*** ERROR - enable failed ***
hangup
The hangup command terminates the modem session. When this command is issued,
the remote user is disconnected from the server. This command can be issued from
either the local or remote console.
RCM>hangup
halt
The halt command halts the managed system. The halt command is equivalent to
pressing the Halt button on the control panel and then immediately releasing it. The
RCM firmware exits command mode and reconnects the user’s terminal to the system
COM1 serial port.
RCM>halt
Focus returned to COM port
The halt command can be used to force a halt assertion. See Section B.3 for
information on halt assertion.
NOTE: If you are running Windows NT, the halt command has no effect.

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haltin
The haltin command halts a managed system and forces a halt assertion. The haltin
command is equivalent to pressing the Halt button on the control panel and holding it
in. This command can be used at any time after system power-up to allow you to
perform system management tasks. See Section B.3 for information on halt assertion.
NOTE: If you are running Windows NT, the haltin command does not affect the
operating system session, but it does cause a halt assertion.
haltout
The haltout command terminates a halt assertion that was done with the haltin
command. It is equivalent to releasing the Halt button on the control panel after
holding it in (rather than pressing it once and releasing it immediately). This
command can be used at any time after system power-up. See Section B.3 for
information on halt assertion.
help or ?
The help or ? command displays the RCM firmware commands.
poweroff
The poweroff command requests the RCM to power off the system. The poweroff
command is equivalent to pressing the On/Off button on the control panel to the off
position.
RCM>poweroff
If the system is already powered off or if switch 3 (RPD DIS) on the switchpack has
been set to the on setting (disabled), this command has no immediate effect.
To power the system on again after using the poweroff command, you must issue the
poweron command.
If, for some reason, it is not possible to issue the poweron command, the local
operator can start the system as follows:
1.

Press the On/Off button to the off position and disconnect the power cord.

Reconnect the power cord and press the On/Off button to the on position.

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poweron
The poweron command requests the RCM to power on the system. The poweron
command is equivalent to pressing the On/Off button on the control panel to the on
position. For the system power to come on, the following conditions must be met:
•

AC power must be present at the power supply inputs.

•

The On/Off button must be in the on position.

•

All system interlocks must be set correctly.

The RCM exits command mode and reconnects the user’s terminal to the system
console port.
RCM>poweron
Focus returned to COM port
NOTE: If the system is powered off with the On/Off button, the system will not power
up. The RCM will not override the “off” state of the On/Off button. If the system is
already powered on, the poweron command has no effect.
quit
The quit command exits the user from command mode and reconnects the serial
terminal to the system console port. The following message is displayed:
Focus returned to COM port
The next display depends on what the system was doing when the RCM was invoked.
For example, if the RCM was invoked from the SRM console prompt, the console
prompt will be displayed when you enter a carriage return. Or, if the RCM was
invoked from the operating system prompt, the operating system prompt will be
displayed when you enter a carriage return.
reset
The reset command requests the RCM to reset the hardware. The reset command is
equivalent to pressing the Reset button on the control panel.
RCM>reset
Focus returned to COM port

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The following events occur when the reset command is executed:
•

The system restarts and the system console firmware reinitializes.

•

The console exits RCM command mode and reconnects the serial terminal to the
system COM1 serial port.

•

The power-up messages are displayed, and then the console prompt is displayed
or the operating system boot messages are displayed, depending on how the
startup sequence has been defined.

setesc
The setesc command resets the default escape sequence for invoking RCM. The
escape sequence can be any character string. A typical sequence consists of 2 or more
characters, to a maximum of 15 characters. The escape sequence is stored in the
module’s on-board NVRAM.
NOTE: Be sure to record the new escape sequence. Although the factory defaults can
be restored if you forget the escape sequence, this requires resetting the EN RCM
switch on the RCM switchpack.
The following sample escape sequence consists of 5 iterations of the Ctrl key and the
letter “o”.
RCM>setesc
^o^o^o^o^o
RCM>
If the escape sequence entered exceeds 15 characters, the command fails with the
message:
*** ERROR ***
When changing the default escape sequence, avoid using special characters that are
used by the system’s terminal emulator or applications.
Control characters are not echoed when entering the escape sequence. Use the status
command to verify the complete escape sequence.
setpass
The setpass command allows the user to change the modem access password that is
prompted for at the beginning of a modem session.
RCM>setpass
new pass>*********
RCM>

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The maximum length for the password is 15 characters. If the password exceeds 15
characters, the command fails with the message:
*** ERROR ***
The minimum password length is one character, followed by a carriage return. If only
a carriage return is entered, the command fails with the message:
*** ERROR - illegal password ***
If you forget the password, you can enter a new password.
status
The status command displays the current state of the system sensors, as well as the
current escape sequence and alarm information. The following is an example of the
display.
RCM>status
Firmware Rev: V2.0
Escape Sequence: ^]^]RCM
Remote Access: ENABLE
Alerts: DISABLE
Alert Pending: NO
Temp (C): 26.0
RCM Power Control: ON
RCM Halt: Deasserted
External Power: ON
Server Power: ON
RCM>
The status fields are explained in Table C-2.

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Table C-2 RCM Status Command Fields
Item

Description

Firmware Rev:

Revision of RCM firmware.

Escape Sequence:

Current escape sequence to invoke RCM.

Remote Access:

Modem remote access state. (ENABLE/DISABLE)

Alerts:

Alert dial-out state. (ENABLE/DISABLE)

Alert Pending:

Alert condition triggered. (YES/NO)

Temp (C):

Current system temperature in degrees Celsius.

RCM Power Control:

Current state of RCM system power control. (ON/OFF)

RCM Halt:

Asserted indicates that halt has been asserted with the
haltin command. Deasserted indicates that halt has been
deasserted with the haltout command or by cycling
power with the On/Off button on the control panel. The
RCM Halt: field does not report halts caused by pressing
the Halt button.

External Power:

Current state of power to RCM. Always on.

Server Power:

Indicates whether power to the system is on or off.

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C.4 Dial-Out Alerts
When you are not monitoring the system remotely, you can use the RCM dial-out
feature to notify you of a power failure within the system.

When a dial-out alert is triggered, the RCM initializes the modem for dial-out, sends
the dial-out string, hangs up the modem, and reconfigures the modem for dial-in. The
modem must continue to be powered, and the phone line must remain active, for the
dial-out alert feature to work. Also, if you are connected to the system remotely, the
dial-out feature does not work.
Enabling Dial-Out Alerts
1.

Enter the set rcm_dialout command, followed by a dial-out alert string, from the
SRM console (see ➊ in Example C–3). See the next topic for details on
composing the modem dial-out string.

Invoke the RCM and enter the enable command to enable remote access dial-in.
The RCM status command should display “Remote Access: Enable.” See ➋.

Enter the alert_ena command to enable outgoing alerts. See ➌.

Example C–3 Configuring the Modem for Dial-Out Alerts
P00>>> set rcm_dialout “ATDTstring#;”
RCM>enable
RCM>status
.
.
Remote Access:
.
RCM>alert_ena

Enable

➊

➋
➌

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Composing the Dial-Out String
Enter the set rcm_dialout command from the SRM console to compose the dial-out
string. Use the show command to verify the string. See Example C–4.

Example C–4 Typical RCM Dial-Out Command
P00>>> set rcm_dialout “ATXDT9,15085553333,,,,,,5085553332#;”
P00>>> show rcm_dialout
rcm_dialout
ATXDT9,15085553333,,,,,,5085553332#;

The dial-out string has the following requirements:
•

The string cannot exceed 47 characters.

•

Enclose the entire string following the set rcm_dialout command in quotation
marks.

•

Enter the characters ATDT after the opening quotation marks. Do not mix case.

•

Enter the character X after “AT” if the line to be used also carries voice mail.

•

The valid characters for the dial-out string are the characters on a phone keypad:
0–9, *, and #. A comma (,) requests that the modem pause for 2 seconds, and a
semicolon (;) is required to terminate the string.

The elements of the dial-out string are explained in Table C-3.

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Table C-3 Elements of the Dial-Out String
ATXDT

AT = Attention
X = Forces the modem to dial “blindly” (not look for a dial
tone). Enter X if the dial-out line modifies its dial tone
when used for services such as voice mail.
D = Dial
T = Tone (for touch-tone)
, = Pause for 2 seconds

In the example, “9” gets an outside line. Enter the number
for an outside line if your system requires it.

15085553333

Dial the paging service.

,,,,,,

Pause for 12 seconds for paging service to answer

5085553332#

“Message,” usually a call-back number for the paging
service.

;

Return to command mode. Must be entered at end of
string.

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C.5 Using the RCM Switchpack
The RCM operating mode is controlled by a switchpack on the system board.
Use the switches to enable or disable certain RCM functions, if desired.

Figure C-2 Location of RCM Switchpack on System Board
System Motherboard
RCM
Switchpack
SET DEF

RPD DIS

MODEM OFF
EN RCM

2
1

RCM power
VAUX from
power supplies

PKW0504C-97

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Figure C-3 RCM Switches (Factory Settings)

PKW0950-97

Switch

Name

Description

EN RCM

Enables or disables the RCM. The default is ON
(RCM enabled). The OFF setting disables RCM.

MODEM OFF

Enables or disables the modem. The default is OFF
(modem enabled).

RPD DIS

Enables or disables remote poweroff. The default is
OFF (remote poweroff enabled).

SET DEF

Sets the RCM to the factory defaults. The default is
OFF (reset to defaults disabled).

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Uses of the Switchpack
You can use the RCM switchpack to change the RCM operating mode or disable the
RCM altogether. The following are conditions when you might want to change the
factory settings.
•

Switch 1 (EN RCM)—Set this switch to OFF (disable) if you want to reset the
baud rate of the COM1 port to a value other than the system default of 9600. You
must disable RCM to select a baud rate other than 9600.

•

Switch 2 (MODEM OFF)—Set this switch to ON (disable) if you want to prevent
the use of the RCM for monitoring a system remotely. RCM commands can still
be run from the local serial console terminal.

•

Switch 3 (RPD DIS). Set this switch to ON (disable) if you want to disable the
poweroff command. With poweroff disabled, the monitored system cannot be
powered down from the RCM.

•

Switch 4 (SET DEF). Set this switch to ON (enable) if you want to reset the
RCM to the factory settings. See the section “Resetting the RCM to Factory
Defaults.”

Changing a Switch Setting
The RCM switches are numbered on the system board. The default positions are
shown in Figure C-3. To change a switch setting:
1.

Turn off the system.

Unplug the AC power cords.
NOTE: If you do not unplug the power cords, the new setting will not take effect
when you power up the system.

Remove the system covers. See Section 6.3.

Locate the RCM switchpack on the system board and change the switch setting as
desired.

Replace the system covers and plug in the power cords.

Power up the system to the SRM console prompt and type the escape sequence to
enter RCM command mode, if desired.

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Resetting the RCM to Factory Defaults
You can reset the RCM to factory settings, if desired. You would need to do this if
you forgot the escape sequence for the RCM. Follow the steps below.
1.

Turn off the system.

Unplug the AC power cords.
NOTE: If you do not unplug the power cords, the reset will not take effect when
you power up the system.

Remove the system covers. See Section 6.3.

Locate the RCM switchpack on the system board, and set switch 4 to ON.

Replace the system covers and plug in the power cords.

Power up the system to the SRM console prompt.
Powering up with switch 4 set to ON resets the escape sequence, password, and
modem enable states to the factory defaults.

Power down the system, unplug the AC power cords, and remove the system
covers.

Set switch 4 to OFF.

Replace the system covers and plug in the power cords.

10. Power up the system to the SRM console prompt, and type the default escape
sequence to invoke RCM command mode:
^]^]RCM
11. Reset the modem password. Reset the escape sequence, if desired, as well as any
other states.

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C.6 Troubleshooting Guide
Table C-4 is a list of possible causes and suggested solutions for symptoms you
might see.

Table C-4 RCM Troubleshooting
Symptom

Possible Cause