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AH-8603D-MC

January 1979

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Document:	CZDQAD0 DQ11 BASIC LOGIC TEST PART 1 JAN 1979 bw
Order Number:	AH-8603D-MC
Revision:	000
Pages:	95
Original Filename:	CZDQAD0__DQ11__BASIC_LOGIC_TEST_PART_1__AH-8603D-MC__JAN_1979_gray.pdf

OCR Text

BASIC LOGIC TEST PARTi

CZDQADO

AH-8603D-MC

JAN 1979

Eflflumu

MADE IN USA

Imom MACY11 30A(1052) 19=JuL-78 08:30 PAGE 2
C2DQAD.P1

SEQ 0001

27=JUN=-78 08:52

IDENTIFICATION

PRODUCT CODE:

AC=8601D-MC

PRODUCT NAME
:

CZDQADO BLT PRT

DATE :

JUNE 1978

MAINTAINER:

DIAGNOSTIC GROUP

THE

INFORMATION IN THIS DOCUMENT

IS SUBJECT

TO CHANGE WITHOUT

NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION. DIGITAL EQUIPMENT CORPORATION ASSUMES
NO RESPONSIBILITY FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMENT.
NO RESPONSIBILITY IS ASSUMED FOR THE USE OR RELIABILITY OF
SOF TWARE ON EQUIPMENT THAT IS NOT SUPPLIED BY DIGITAL OR ITS
AFFILIATED COMPANIES.

((C)

1974, 1978 BY DIGITAL EQUIPMENT CORPORATION

FOLLOWING ARE

DIGITAL
DEC

TRADEMARKS OF

PDP
DECUS

DIGITAL

UNIBUS
DECTAPE

EQUIPMENT

CORPORATION:

MAS SBUS

CZDQA

MACY11_30A(1052)

CZDQAD.P11
L

19-JuL-78

27-JUN-78 08:52

08:30

PAGE 3

SEQ 0002

ABSTRACT

THE FUNCTION OF THE DQ11 DIAGNOSTICS ARE TO
VERIFY THAT THE OPTION OPERATES ACCORDING
TO SPECIFICATIONS.

CURRENTLY THERE ARE SEVEN OFF LINE DIAGNOSTICS THAT ARE
TO BE RUN IN SEQUENCE

TO INSURE

INSURING THAT

THAT

IF AN

ERROR SHOULD OCCUR IT WILL BE DETECTED
AN EARLY

STAGE AND

DIAGNOSIS OF ERROR WILL BE IMMEDIATE TO PROBLEM
NOTE:
ADDITIONAL DIAGNOSTICS MAY BE ADDED IN THE
THE

SEVEN DIAGNOSTICS ARE:

CZDQA [REV]

NOAVN
S W

2. CZDQB [REV]
. CZDQC [REV]
(ZDQD [REV]
CZDQE [REV]
. CZDQF [REV]
. (ZDQH [REV]
THERE

2.1

FUTURE.

BASIS R/W TEST #1

BASIC R/W TEST #2
BASIC NPR AND INTERUPT TEST
RECEIVER TRANSMITTER EXERCISER TEST
MISC. RX AND TX TESTS. PLUS BCC TESTS.
CHARACTER DETECT TESTS.
CHARACTER LENGTH AND INTERRUPT TESTS.

IS ALSO AN ONLINE

CZDQO [REV]

TEST

ONLINE TEST.

TO BE DISCUSED LATER.

(ITEP OVERLAY)

AND A PARAMETER INPUT PROGRAM IS AVAILABLE
1. CZDOG [REV]
DQ11 TRIAL PROGRAM (PARAMETER

REQUIREMENTS

INPUT)

EQUIPMENT
ANY PDP11 FAMILY CPU (WITH MINIMUM 8K MEMORY)=W]TH
OR WITHOUT A HARDWARE SWITCH REGISTER (LOC. 177570)

38?1 33 (OR EQUILIVALENT)

SYNC MODEM (ONLY REQUIRED FOR ONLINE

2.2

TEST)

STORAGE
PROGRAM WILL LOAD AND RUN

IN 8K OF MEMORY.
LOCATION 1400 THRU 1600 ARE ESPECIALLY TO

BE _NOTED AND TO BE UNTOUCHED BY CPERATOR
AFTER DQ11 TRIAL PROGRAM HAS BEEN EXECUTED.

OR AFTER THE "AUTO SIZING'' HAS BEEN DONE.

. 4

LOADING PROCEEDURE

ME THOD
ALL PROGRAMS ARE

IN ABSOLUTE FORMAT AND

CZDQA
MACYN
O0A(1052)
19-JuL-78
CZDQAD.P11
27=-JUN-78 08:52

08:30

PAGE 4

SEQ 0003

ARE LOADED USING THE ABSOLUTE LOADER.

ABSOLUTE LOADER STARTING ADDRESS

MEMORY
SIZE

4K
8K
12K
16K

17
37
57
7

20K
24K
28K

117
137
157

3.1.1

LOAD THE ADDRESS OF ABS.

3.1.2

THEN START

STARTING PROCEEDURE

A.
B.

+500

LOADER

(LOC.Xxx500)

LOAD LOC. 200
:
SET SWR TO ZERQ FOR "AUTO SIZING'' OR LEAVE
LEAVE SWR BIT 7=1 TO USE EXISTING PARAMETERS SET UP
BY DA11 TRIAL PROGRAM OR A PREVIOUSLY RUN D@11 DIAGNOSTIC

THAT USED THE '‘AUTO SIZING'.
***+REFER TO SECTION 4.1 FOR SOFTWARE SWITCH REGISTER OPERATION
AND OPTIONS.*#w*
_
NOTE
: THE SOF TWARE SWITCH REGISTER IS LOCATED AT LOC.176
SOF TWARE DISPLAY REGISTER IS LOCATED AT LOC.174

C.THEN START

THE PROGRAM WILL

TYPE MAINDEC NAME AND PROGRAM NAME

THIS WAS THE FIRST START UP OF

THE FOLLOWING:

THE PROGRAM)

AND ALSC

"MAP OF DQ11 STATUS'
1400
1402
1404
1406

160010
152300
160020
150310

THE ABOVE IS ONLY AN EXAMPLE
!
THIS WOULD INDICATE THE STATUS TABLE STARTING AT ADD.

1400 IN THE PROGRAM. THE STATUS TABLE MUST BE VERIFIED BY THE
USER IF AUTO SIZING IS DONE.
FOR INFORMATION OF STATUS
TABLE SEE SECTION 8.4 FOR HELP.

*#**]F THE SOF TWARE SWITCH REGISTER IS SELECTED THEN THE FOLLOWING
WILL BE TYPED AFTER THE PROGRAM IDENTIFIES IVSELF:
SWR=XXXXXX NEW=
(REFER TO SECTION 4.1 FOR OPERATOR'S OPTION) ##«
NOTE:IF USING THE SOF TWARE SWITCH REGISTER WHEN A HARDWARE
SWITCH REGISTER IS AVAILABLE THE PROGRAM WILL NOT
TYPE OUT

THE

TITLE.

CZDQA

MACY11_30A(1052)

CZDQAD.P11

19-JuL-78

27=JUN-78 08:52

08:30

PAGE 5

SEQ 0004

THE PROGRAM WILL TYPE 'R’
AND PROCEED TO RUN THE DIAGNOSTIC
4.1

CONTROL SWITCH SETTINGS

IF THE DIAGNOSTIC IS RUN ON A CPU WITHOUT A SWITCH
REGISTER THEN A SOF TWARE SWITCH REGISTER IS USED WHICH ALLOWS
THE USER THE SAME SWITCH OPTIONS AS THE HARDWARE SWITCH REGISTER.

THE HARDWARE SWITCH REGISTER DOES NOT EXIST OR IF ONE DOES

AND IT CONTAINS ALL ONES (177777)
REGISTER (LOC. 176) IS USED.

THEN THE SOF TWARE SWITCH

:
CONTROL
THIS PROGRAM ALSO SUPPORTS THE DYNAMIC LOADING OF THE SOF TWARE SWITCH
REGISTER (LOC. 176) FROM THE TTY. THIS CAN BE ACCOMPLISHED BY
DOING THE FOLLOWING:

TYPE

LOC.

CONTROL G <*G>;

THIS WILL ALLOW THE

TTY TO ENTER DATA INTO

176 AT SELECTED POINTS WITHIN THE PROGRAM.

2) THE MACHINE WILL THEN TYPE: SWR=XXXXXXNEW= (XXXXXX IS THE OCTAL CONTENTS
OF

THE SOF TWARE SWITCH REGISTER.)

3 AFTER THE
OF

'°'NEW='' HAS BEEN TYPED THEN THE OPERATOR CAN DO ONE
THE FOLLOWING AT THE TTY:

TYPE A NUMBER TO BE LOADED INTO LOC.

176 FOLLOWED BY A <(CR>.

(ONLY NUMBERS BETWEEN O-7 WILL BE ACCEPTED AND ONLY & NUMBERS
WILL BE ALLOWED)

IF A <CR> IS THE FIRST KEY DEPRESSED THE SOF TWARE SWITCH

IF A CONTROL U <*U> IS DEPRESSED THEN THE PROGRAM WIL!
BACK TO STEP 2.

SET: HALT ON ERROR

3
2

SET:
SET:

O
09
08
07
06
05
04
03
02
01
00

CHANGED.

SET:

SET:
SET:
SET:
SET:
SET:
SET:
SET:
SET:
SET:
SET:
SET:

LOOP ON CURRENT TEST

INHIBIT ERROR PRINT OUT
INHIBIT TYPE OUT/BELL ON ERROR.

INHIBIT ITERATIONS

ESCAPE TO NEXT TEST
LOOP WITH CURRENT DATA
CATCH ERROR AND LOOP ON IT
USE PREVIOUS STATUS TABLE. CLR=DO AUTO SIZE.

LOCK ON SELECTED TEST

RESTART PROGRAM AT SELECTED TEST
RESELECT DQ11'S DESIRED A(TI.€,

SEND YOU

CZDQA
MalY11 30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN~-78 08:52
6.1.2

08:30

PAGE 6

SEQ 0005

SWITCH REGISTER RESTRICTIONS

Sw 00

RESELECT DQ11'S DESIRED ACTIVE,
PLEASE NOTE THAT A MESSAGE

IS TYPED

OUT FOR SWITCH REGISTER BEING EQUAL TO DQ11'S
ACTIVE. THIS MEANS IF THE SYSTEM HAS
FOUR DA11S; BITS 00,01,02,03 WILL

BE SET IN_LOC 'DQACTV'". USING THIS

SWITCH ALTERS THAT LOCATION; THEREFORE
IF FOUR DQT1S ARE IN THE SYSTEM
#*«DQ NOT**% SET SWITCHS GREATER THAN

Sw 03 IN THE UP POSITION. THIS WOULD BE

A FATAL ERROR.

DO NOT SELECT MORE ACTIVE

DQ11S THAN HAS BEEN GIVEN INFORMATION

ABOUT IN TRIAL PROGRAM.

COnmD>

LOAD ADDRESS 200
START WITH SW_00=1

PROGRAM WILL TYPE MESSAGE
CONTINUE THE BINARY
NUMBER OF DQ11S DESIRED ACTIVE

EXAMPLE: 1=1 DQ11; 3=_

DQ11;

7=3 DO11;

17=4 DQ11 37=5 DQ11 ETC,

NUMBER (IF VALID) WILL BE IN DATA LIGHTS (EXCLUDING 11/05,
CONTINUE WITH ANY OTHER SWITCH SETTINGS DESIRED.

-m

:
ME THOD

SW 01

IT IS STRONGLY SUGGESTED THAT

AT LEAST ONE PASS HAS BEEN MADE

BEFORE TRYING TO SELECT A TEST

THAT IS NOT IN THE ORDER OF SEQUENCE
THE REASON BEING IS THAT THE
PROGRAM HAS TO CLEAR AREAS AND SET

UP PARAMETERS. ALSO WHEN A TEST IS
SELECTED ALWAYS START AT THE VERY
BEGINNING OF THAT TEST.

SW 09

LOOP ON CURRENT DATA:

THIS SWITCH WILL ONLY WORK

THE REASON BEING THAT MOST

TESTS

CALL ''SCOP1'" IS IN THAT TEST.

DEAL WITH BLOCKS OF DIFFERENT DATA
TO BE

SENT OR RECEIVED ALL AT ONCE

THUS IN BLOCK DATA; ONE PATTERN CANN'T BE SINGLED OUT.

SWITCH REGISTER PRIORITYS

ERROR SWITCHES
NS W) —

SW
SW
SW
SW
SW

««**HLT

(ERROR)

.
.
.
.

SCOPE

12
13
15
08
10

SWITCHES

DELETE PRINT QUT/BELL ON ERROR.
DELETE ERROR PRINTOUT.
HALT ON THE ERROR.
GOTO BEGINNING OF THE TEST.
GOTO NEXT TEST ON ERROR.
ROUTINE

SUPPORTS <“G> OPERATION®»*+

11/04,

11/34)

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

08:30

PAGE 7

SW 09 (IF ENABLED BY ''SCOP1'")

Sw 11

SEQ 0006

**x*xSCOPE ROUTINE WILL SUPPORT <*G> OPERATION*x*x
4.2

STARTING ADDRESS

STARTING ADDRESS IS AT 000200

THERE ARE NO OTHER STARTING ADDRESSES
FOR THE DQ11 DIAGNOSTICS PREVIOUSLY MENTIONED

NOTE:

IF ADDRESS 000042 IS NON-ZERO

THE PROGRAM ASSUMES IT

IS UNDER

ACT11 OR DDP CONTROL AND WILL ACT ACCORDINGLY
AFTER ~ALL* AVAILABLE DQ11°'S ARE TESTED
THE PROGRAM WILL RETURN TO 'DDPZ2'' OR "‘ACT=-11"".
OPERATING PROCEDURE
WHEN PROGRAM IS INITIALLY STARTED MESSAGES AS DESCRIBED IN SECTION
FOUR WILL BE PRINTED.

AND PROGRAM WILL BEGIN RUNNING THE
DIAGNOSTIC

5.2

PROGRAM AND/OR OPERATOR ACTION

THE

TYPICAL APPROACH SHOULD BE

HALT ON ERROR (VIA SW 15=1)
WHEN EVER AN ERROR OCCURS

Lo
3.

CLEAR SW 15
SET SW 14: (LOOP ON THIS TEST)

THE

SET SwW 13:

(INHIBIT ERROR PRINT OUT)

TEST NUMBER AND PC WILL BE

POSSIBILY AN ERROR MESSAGE

TYPED OUT AND

(THIS DEPENDS ON THE

TEST)

TO GIVE THE OPERATOR AN IDEA AS TO THE SOURCE OF THE
PROBLEM. IF IT IS NECESSARY TO KNOW MORE INFORMATION

CONCERNING THE ERROR REPORT;

FOR

LOOK IN THE LISTING

THAT TEST NUMBER WHICH WAS

TYPED QUT

AND THEN NOTE THE PC OF THE ERROR REPORT
THIS WAY THE EXACT FUNCTIONING OF THE TEST
CAN BE INTERPEDITED

ERRORS
AS DESCRIBED PREVIOUSLY THERE WILL ALWAY BL
A TEST NUMBER AND PC TYPED OUT AT THE TIME OF

ERROR (PROVIDING SW 13=0 AND SwW 12=0).

IN MOST CASES ADDITIONAL

INFORMATION WILL BE SUPPLIED THE THE ERROR MESSAGE
lglg‘l‘g; IS TO GIVE THE OPERATOR AN INDICATION OF THE

€.2

ERROR RECOVERY

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

08:30

PAGE 8

SEQ 0007

[F FOR_SOME REASON THE DQ11 SHOULD

"HANG THE BUS'' (GAIN CONTROL OF BUS SO THAT
CONSOLE MANUAL FUNCTIONS ARE INHMIBITED) AN INIT
OR POWER DOWN/UP IS NECESSARY FOR OPERATOR
TO REGAIN CONTROL OF

CPU.

THIS SHOULD HAPPEN; LOOK IN LOCATION

“TSTNO'* (ADDRESS 1226JFOR THE NUMBER OF THE TEST THAT

gsgogLMING AT THE TIME OF THE CATASTROPHIC

IN THIS WAY THE OPERATOR WILL HAVE AN IDEA AS TO
WHAT THE DQ11 WAS DOING AT THE TIME OF THE ERROR.

6.3

wxx+HALT RECOVERY WHEN USING SOF TWARE SWITCH REGISTERw» »#
IF

THE
THE

THE SOF TWARE SWITCH REGISTER IS TO BE CHANGED AFTER A HALT

THE OPERATOR IS REQUIRED TO TYPE A <*G> BEFORE DEPRESSING CONTINUE.
FOLLOWING WILL BE TYPED:

SWR=XXXXXX

NEW=

(REFER TO SECTION 4.1

FOR OPERATOR OPTION)

RESTRICTIONS

STARTING RESTRICTIONS
SEE SECTION 4.

(PLEASE)

OPERATING RESTRICTIONS
DQ11 TRIAL PROGRAM MUST BE RUN PRIOR TO THE
FIRST AND ONLY THE FIRST RUNNING OF ANY DQ11
NOTE:
IF NO PROGRAM OTHER THAN
A

DIAGNOSTIC

DQ11 DIAGNOSTIC WAS LOADED AFTER DQ11 TR.AL OR
IF CORE MEMORY HAS NOT BEEN CHANGED;OR IF THERE
IS NO DQ11 CONFIGURATION CHANGES; THE
DQ11 TRIAL PROGRAM NEED NEVER BE RUN AGAIN.

HOWEVER IF ANY OF THE ABOVE HAVE BEEN VIOLATED
THE DQ11 TRIAL PROGRAM MUST BE RUN AGAIN
BEFORE RUNNING THE DIAGNOSTICS
NOTE: AN ALTERNATIVE TO THE ABOVE IS ATTEMPTING

T?;H'%g (S)IZING" WHEN PROGRAM IS INITIALLY STARTED

MISCELLANEOUS
EXECUTION TIME
PASS COMPLETE

WHEN THE DIAGNOSTIC HAS COMPLETED

A PASS

THE FOLLOWING IS AN EXAMPLE

THE PRINT OUT TO BE EXPECTED.

END PASS A(-8601D-MC CSR:
NOTE:

160000 VEC:

300 PASSES: 000001

THE NUMBERS FOR (SR AND VEC ARE
NOT NECESSARILY THE VALUES FOR THE DEVICE

ERRORS:

000000

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

08:30

PAGE 9

SEQ 0008

THEY ARE ONLY FOR THIS EXAMPLE.

8.3

(MINI MONITOR)

THE VERY FIRST "TEST'' (TST1)

IS *«NOT+ A TEST OF THE DQ11 HARDWARE
IT IS A MINI-MONITOR USED TO CYCLE DQ11
SYSTEM THROUGH THE DIAGNOSTIC.

8.4

IN THE

KEY LOCATIONS
RETURN (1214)

(1216)

TSTNO

(1226)

RUN

(1304)

DQCROO-DQCR17

CONTAINS THE ADDRESS WHERE PROGRAM WILL
RETURN WHEN ITERATION COUNT IS REACHED

OR IF LOOP ON TEST IS ASSERTED.
CONTAINS THE ADDRESS OF THE NEXT TEST
TO BE PEFORMED.

CONTAINS THE NUMBER OF
BEING PEFORMED.

THE TEST NOW

THE BIT IN "RUN'' ALWAYS POINTS ONE

PAST THE DQ11 CURRENTLY BEING TESTED.
:
EXAMPLE
(RUN) 130470000000001000000
MEANS THAT DQ11 NO.0S IS THE DQ11 NOW
RUNNING.

DQSTO0-DQST17
(1400)=(1476)

DQACTYV (1500)

THESE LOCATIONS CONTAIN THE

INFORMATION

NEEDED TO TEST UP TO 16 (DECIMAL) DQ11S
SEQUENTIALY. THEY CONTAIN THE CSR,VECTCR
AND STATUS CONCERNING THE CONFIGURATION
OF EACH DQ11.

EACH BIT SET IN THIS LOCATION INDICATES
THAT

THE ASSOCIATED DQ11

WILL BE

TESTED

IN TURN.
:
EXAMPLE
(DQACTV) 1500/0000000000011111
MEANS THAT DQ11 NO. 00,01,02.03,04

WILL BE TESTED.

EXAMPLE :
(DQACTV) 1500/0000000000010001
MEANS THAT DQ11 NO. 00,04

DOCSR

(1506)

DQSTAT (1510)

BIT 15

BIT 14

BIT
BIT
BIT
BIT
BIT

13
12
11
10
09

WILL BE TESTED.

CONTAINS THE RECEIVER CSR OF THE
CURRENT DQ11 UNDER TEST.
CONTAINS THE STATUS OF THE CURRENT
DQ11 UNDER TEST.
SET:
TWO SYNC CHARS/ONE SYNC CHAR
SET:
TEST JUMPER INSTALLED/NOT INSTALLED
SET:
B8 OPTION INSTALLED/NOT INSTALLED
SET:
BA OPTION INSTALLED/NOT INSTALLED
SET:
ACTIVE ON FIRST NON-SYNC/ACTIVE AFTER NO. OF SYNC
SET:
AB OPTION INSTALLCD/NOT INSTALLED
SET:
ODD VRC/EVEN VRC

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P1
27=JUN-78 08:52

08:30

BIT 00-08

PAGE 10

SEQ 0009

VECTOR "A"" OF DEVICE

8.5

w=x* METHOD OF AUTO SIZING #x«

8.5.1

FINDING THE

CONTROL STATUS REGISTER.

WHEN LOOKING FOR THE CSR IT IS NECESSARY TO TAKE CARE
THAT WHEN A CSR IS FOUND THAT

IS INDEED A DQ11.

IS THE METHOD OF MY MADNESS FOR THIS ROUTINE.

THAT

AN ATTEMPT TO CLEAR THE MISC. REGISTER IS TRIED
IF A TIME-OUT TRAP OCCURES POINTERS ARE UPDATED
AND ATTEMPTED AGAIN. IF NO TIME-OUT; THE RECEIVER "ACTIVE BIT"" (BIT 12)
IS SET AND A +COMPARE* FOR BOTH SYNC1 AND SYNC 2 IS DONE

THE MISC.

A DQ11.

8.5.2

THE

THEY ARE

THERE

INFORMATION IS STORED AWAY.

THIS

ONE SYNC BIT OR TwWO?
SINCE TOO MUCH HARDWARE MUST BE TURNED ON TO SENSE THE

PRESENTS OF ONE

SYNC OR TWO. THE PROGRAM ASSUMES TWO SYNC
CHARS. NOTE: THIS ASSUMPTION MAY BE ALTERED AFTER AUTO SIZING
BY ALTERING BIT 15 IN APPRIOATE DQSTXX: LOCATION.

8.5.3

'BB'' OPTION INSTALLED?
TO SENSE FOR THE 'BB'' OPTION THE PROGRAM SELECTS THE
CHARACTER DET. REGISTER AND THE LOADS IN ALL 1°'S; IF

ANY ONE OR COMBINATION OF

IS ASSUMED TO EXIST.

8.5.4

BITS ARE SET

THE BB OPTION

"'AB'' OPTION INSTALLED?
TO SENSE FOR THE ''AB'' OPTION THE PROGRAM SELECTS THE

POLYNOMIAL REGISTER AND WRITES ALL 1°'S INTO IT; IF ANY
ONE OR COMBINATION OF BITS ARE SET THE AB OPTION IS ASSUMED
TO EXIST.

8.5.5

"BA"' OPTION INSTALLED?
TO SENSE FOR "BA'" OPTION REQUEST TO SEND AND DATA TERMINAL
SET; IF EITHER ONE OR BOTH ARE SET THE PROGRAM
ASSUMES THE BA OPTION EXISTES
READY ARE

8.5.6

JUMPER ON END OF

CABLE? »**NOTE:CZDQE ONLY***

THE PROGRAM CHECKS TO SEE

IF EITHER OR BOTH CLEAR T0

SEND
AND CARRIER ARE SET; IF SO THE PROGRAM ASSUMES THE
TEST JUMPER IS ON THE END OF THE CABLE.

8.5.7

ACTIVE ON FIRST NON-SYNC?

SINCE _TOO MUCH HARDWARE MUST BE TURNED ON TO SENSE FOR
WHEN THE DQ11 GOES ACTIVE THE PROGRAM ASSUMES ‘‘ACTIVE
ON FIRST NON-SYNC''. NOTE: THIS CAN BE CHANGED BY ALTERING

BIT 11

IN THE APPRIOATE DQSTXX: AFTER AUTC SIZING

CZDQA

MACY11_30A(1052) 8125JUL-78

CZDQAD.P11

8.5.8

27=-JUN-78 0

08:30

PAGE 11

SET FOR ODD OR EVEN PARITY?
AS ABOVE TOO MUCH HARDWARE IS NEED TO SENSE WHICH PARITY
WAS SELECTED.SO THE PROGRAM ASSEMES ODD PARITY.
NOTE: THIS CAN BE CHANGED BY ALTERING BIT 9 IN APPRIOATE DQSTXX:

8.5.9

LOCATION.

AFTER AUTO SIZING

FINDING THE VECTOR.

THE PROGRAM SETS ‘PRIMARY DONE'',"'SECONDAY DONE'‘, AND ‘‘INTERUPT ENABLE''
AND LOOKS FOR AN INTERUPT. IF IT INTERUPTS IT IS PICKED

UP AND STORED AWAY. IF NO INTERUPT OCCURES THE PROGRAM
ASSUMES VECTOR =300. THIS PROBLEM WILL BE FIXED IN ONE
OF THE DIAGNOSTICS AND ~AUTO SIZING* SHOULD BE REDONE 'O
GET THE CORRECT VECTOR.

PROGRAM DESCRIPTION

CONTAINED WITHIN LISTING
10.

LISTING
FOLLOWING

SEQ 0010

CZDQA
MACY11
30A(1052)
19-JUL-78
CZDQAD.P11
27-JUN-78 08:52

08:30

PAGE 12

SEQ 0011

gg%

.ENABLE AMA

524
ggg

; CZDQAD0/<377>/DQ11 STATIC LOGIC TEST=PART 1
*COPYRIGHT 1975, DIGITAL EQUIPMENT CORP., MAYNARD, MASS. 01754

527
528

REVISED 16-DEC-76 BY R. BLACK
:
)SUPPORTS SOF TWARE SWITCH REGISTER

g%g

§37
532

a)ggppogrs THE DYNAMIC LOADING OF THE SOF TWARE SWITCH REGISTER
TM
: STARTING PROCEDURE
:LOAD PROGRAM

5§33

*LOAD ADDRESS 000200

ggg

:AND THEN RESUME TESTING

534
535
536
537

*PRESS START
.
“PROGRAM WILL TYPE ‘'CZDQADO/<377>/D@11 STATIC LOGIC TEST-PART 1°*
:PROGRAM WILL TYPE 'R'* TO INDICATE THAT TESTING HAS STARTED
*AT THE END OF A PASS, PROGRAM WILL TYPE PASS COMPLETE MESSAGE

540

;

gfi%

543
544
545
546
547
548
549
550
551
552
553

554

555
556
557
558

:SWITCH REGISTER OFPTIONS
100000
040000

020000

010000
004000
002000
001000
000400

000100
000040
000020

000010

000004
000002
000001

SW15=100000
SW14=40000
SW13=20000
SW12=10000
SW11=4000
SW10=2000
SW09=1000
SW08=400
SW06=100
SW05=40
SW04=20

:=1,HALT ON ERROR
2=1.LOOP ON CURRENT TEST
*=1.INHIBIT ERROR TYPEOQUT
:=1.DELETE TYPEOUT/BELL ON ERROR.
*=1_INHIBIT ITERATIONS
*=1.ESCAPE TO NEXT TEST ON ERROR
*=1.L00P WITH CURRENT DATA
*=1.L00P ON ERROR

SW02=4
SW01=2
SW00=1

:LOCK ON TEST SELECT
*RESTART PROGRAM AT SELECTED TEST
*RESELECT DQ11 DESIRED ACTIVE
;NOTE: THIS MUST NOT EXCEED ORIGINAL COUNT

SW03=10

CZDQA
MACY11_30A(1052)
19-JuL-78
CZPQAD. P11
27=JUN-78 08:52

M1
08:30 PAGE 13
GENERAL DEF INATIONS AND EQUIVALENCIES

SEQ 0012

;REGISTER DEFINITIONS

000000
000001
000002

RO=20
R1=11
RQ=X2

:GENERAL REGISTER
:GENERAL REGISTER
:GENERAL REGISTER

000004
000005
000006
000007

R4=14
RS=15
SP=16
PC=7

:GENERAL REGISTER
:GENERAL REGISTER
:PROCESSOR STACK POINTER
:PROGRAM COUNTER

000003

R3=13

:GENERAL REGISTER

:LOCATION EQUIVALENCIES
177570
177570

177776

001200

DSWR=
177570
DLIGHTS=177570
PS=177776

STACK=1200

;HARDWARE SWITCH REGISTER LOC.
:HARDWARE DISPLAY REGISTER LOC.

:PROCESSOR STATUS WORD

:START OF PROCESSOR STACK

; INSTRUCTION DEF INITIONS
005746
005726
010046
012600
024646
022626

PUSHISP=5746
POP1SP=5726
PUSHRO=10046
POPR0=12600 ~
PUSHOSP=24646
POP2SP=22626

100000
040006
020000
010000

B1715=100000
BI714=40000
BI713=20000

004000
002000
001000
000400
000200
000100
000040
000020
000010
000004
000002
000001

.EQUIV

;DECREMENT PROCESSOR STACK 1 WORD
:INCREMENT PROCESSOR STACK 1 WORD
:SAVE RO ON STACK
:RESTORE RO FROM STACK
:DECREMENT STACK TWICE
:INCREMENT STACK TWICE

EMT,HLT :BASIC DEFINITION OF ERROR CALL

BIT12=10000

BIT11=4000
BI710=2000

BI79=1000
BI78=400
BIT7=200
BIT6=100
BIT5=40
BIT4=20
BIT3=10
BIT2=4
BIT1=2
BITO=1

;DQ11 OPTIONAL DEF INITIONS
002000
004000
010000
020000
040000

ABB] T=2000
ACTBIT=4000
BABIT=10000
8881T7=20000
JUMBI T=40000

(ZDQA

MACY11_30A(1052)

(ZDQAD.P11

615
615

19-JuL-78

27=JUN-78 08:52

001000
100000

2128

08:30

PAGE 14

GENERAL DEFINATIONS AND EQUIVALENCIES

0opDBIT=1000
SYNBIT=100000
:DQ11

SECONDARY REGISTER DEF INATIONS

621
622
623
624
625
626
627

000000
000001
000002
000003
000004
000005
000006

RXBA.P=0
RXWC.P=1
TXBA.P=2
TXWC.P=3
RXBA. S=4
RXWC.S=5
TXBA.S=6

TXWC.S=7

: TRANSMITTER WORD COUNT SECONDARY.

630

000010

CHARDT=10

s CHARACTER DETECT REGISTER.

634
635
636

000014
000015
000016

SEQ.=14
RX.B(CC=15
TX.B((=16

; SEQUENCE REGISTER.
;RECEIVER BCC REGISTER.
: TRANSMITTER BCC REGISTER.

2228

631
632
633

637

000007

000011
000012
000013

SYNC.=11
MISC.=12
TX.MUX=13

000017

POLY.=17

;RECEIVER BUS ADDRESS PRIMARY.
;RECEIVER WORD COUNT PRIMARY.
s TRANSMITTER BUS ADDRESS PRIMARY.
: TRANSMITTER BUS ADDRESS PRIMARY.
;RECEIVER BUS ADDRESS SECONDARY.
;RECEIVER WORD COUNT SECONDARY.
:TRANSMITTER BUS ADDRESS SECONDARY.

:SYNC REGISTER.
;MISCELLANEOUS REGISTER.
; TRANSMITTER MUX REGISTER.

sPOLYNOMIAL REGISTER.

SEQ 0013

MA(CY11
CZDQA
CZDQAD.P1

(1052)

19-JuL-78

-JUN-78 08:52

08:30

000024
016164
000340
015634
000340
015602
000340
000046

.=24

.=46
.=52

022021

s TRAPCATCAER FOR ILLEGAL

s STANDARD INTERRUPT VECTORS

.PFAIL
340
LHLT
340
. TRPSRV
340

;POWER FAIL HANDLER
sSERVICE AT LEVEL 7
;ERROR HANDLER
;SERVICE AT LEVEL 7
;GENERAL HANDLER DISPATCH SERVICE
;SERVICE AT LEVEL 7

LOGICAL

;ACT HOOKS

sTO TAKE THE PC FROM THE STACK AND US IT AS THE VECTOR ADDRESS

.=56

VECMAP:

000004

1%:

MOV
MOV

R1,(RO)+
#46,(R1)+

;START FILLING THE VECTOR AREA
UITH .+2; 10T
(

R1.,#1000
1%
#6S ,an20
DQACTV, TEMP1
TEMP1
5%
PS

;IS ALL FLOATING VECTOR AREA DONE
BR IF NOT ALL DONE
;SET FOR IOT TRAP BY DQ11
sGET THE ACTIVE DQ11 S
.'ARE YOU ACTIVE.. DQ11
:IF CARRY CLEAR.. NO MORE DQ11S
;CLEAR PS

#340,a-2(R2)

;TRY AND SET PRI/SEC DONE AND IE

CMP

020127
101771
012737
013737
006037
103023
005037

001000

177776

CMP
BLOS
MOV
MOV
ROR
BCC
CLR

012772

000340

MOV

005722

105200
001376
112712

005722
000761

051612
042712
022626
012716

000207
000174

000000

002000

000146
001500
001244

000300

000007

TSt

INCB
BNE

3%:
4%:

000142

5%:

MOVB

51
BR

(RO)+,(R1)+

(R2)+

RO
M

#300, (R2)

(R2)+
2%

BIS
BIC
CMP
MOV

(SP),(R2)
#7,(R2)
(SP)+,(SP)+
#3%,(SP)

RTS

RTI

lPDATE THE POINTERS

;PUT POINTER TO STATUS TABLE
DELAY ........
DELAY

NO INTERUPT ASSUME 300 FIX IN TEST C

;UPDATE POINTERS
.'GO DO IT AGAIN

;ENTERD BY IOT TRAP BY DQ11
;CLEAR UNWANTED BITS
;POP I0OT JUNK OFF STACK
sSET RETURN PC ON STACK

:GC HOME.

ALL SIZING IS DONE

;xx*xSOF TWARE SWITCH REGISTER*
%%«

=174

DISPREG:
SWREG:

;PROGRAM START

000200

INTERRUPTS

.WORD 0
;THIS ROUTINE TRIES TO FORCE THE RECEIVER TO INTERUPT
sTO ITS VECTOR WHERE IT WILL PICK UP THE STATUS LOCATION
;FOR ITS NEW PC; AND PICK UP AN IOT INSTRUCTION FOR ITS
JNEW PS. WHEN THE NEW PC IS FETCHED AN IOT INSTRUCTION IS
JEXECUTED, TRAPPING TO LOCATION 20 WHERE A ROUTINE IS EXECUTED

000056
010120
012721

TRAPCATCHER FOR UNEXPECTED INTERUPTS

000000

014362
000052
000000

PAGE 15

.=200

;SOF TWARE DISPLAY REGISTER
.‘SOF TWARE SWITCH REGISTER

SEQ 0014

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN~78 08:52

ggg

698

699
700

701
702
703
704
705
706

707
708

709
710
711
712

000200
000220
000224

000137

000220
012702
005022

000226
000232
000234
000240
000244
000250

022702
001374
005037
012702
012701
012737

000270
000274
000302
000304

012711
022761
001071
010122

000256
000264

112761
005061

713
714

000
000312

052712
005011

716

000322

012761

719

000336

052712

715

717
718

720

721

000314

000330
000334

000342

001402

000364

052712

000376
000404
000406
000412
000420
000422
000426
000432
000436
000440
000442
000446
000452
000456

032761
001402
052712
032761
001402
052712
052712
052712
005722
005011
005061
005061
005061
005061

740
7641
742
743
744

000462
000466
000472
000476

000500

001504
001400
160000
000614

000012
000006

012761

005237
062701
022701
001267

005037

020000

177777

000002

001504
000010
164000

747
748

000512
000516

013701
010137

001504
001276

750
751

000524
000530

006137
005237

001500
001500

749

000522

000241

#-1,6(R1)

SWRITE INTO CHAR DET REG

BIS

#BBBIT, (R2)

“SET FOR BB OPTION

MOV

#-1_6(R1)

BIT
BEQ
BIS
BIT
BEQ
BIS
BIS
BIS
ST
CLR
CLR
CLR
CLR
CLR

001500

001504

MOV

2%:

#10,5(R1)

6(R1)
.+6

#17.5(R1)

6(R1)
+6

#ABBIT, (R2)

#1400,2(R1)

#1400.2(R1)
+6
#BABIT, (R2)
#30000.2(R1)
+6
#JUMBIT,(R2)
#ACTBIT.(R2)
#ODDBIT.(R2)
(R2)+
(R1)
2(R1)
2(R1)
4(R1)
6(R1)

:SEL CHAR DET REGISTER

;WAS THE REGISTER WRITTEN?
*APPERENTLY NO BB OPTION.

*SEL POLYNO. REGISTER

*WRITE POLYNO.REGISTER
*WAS REG WRITTEN??

*BR IF NO AB OPTION
:SET FOR AB OPTION

*TRY TO SET .DTR. .RS.
:DID ANY OF THEM SET
:BR IF NO BA OPTION
*SET FOR BA OPTION

:DID .CS. .CO. SET
*BR IF NO JUMPER
+SET FOR JUMPER
:-SET FOR ACTIVE ON FIRST NON-SYNC
-SET FOR ODD VRC.......
*POP POINTER
*CLEAR RCSR
*CLEAR TCSR
*CLEAR AGAIN
*CLEAR ERROR REG
*CLEAR SEC REG

INC
ADD
CMP
BNE

DQNUM
#10.R1
#164000,R1
1%

*UPDATE NUMBER OF DQ11S
:UFDATE CSR POINTER BY 10 (8)
*HAVE ALL FLOATING ADDRESSES BEEN CHECKED??
*BR IF NOT ALL DONE

TST

DONUM

*WERE ANY DQ11S FOUND

CLR

BEQ

3$:

“TRY AND SET RX ACTIVE
:LOOK FOR SYNC 1 AND SYNC 2
*THIS IS NOT A D@11 IF I BRANCH
*NOW THIS IS A DQ11 =-STORE CSR

-SET FOR TWO SYNC CHARS
*CLEAR DQ ACTIVE BIT

BIS

000002
000002
000004
00000&

m (R2)+

:TRY AND SEL MISC REGISTER
“TRY AND CLEAR MISC REG

#SYNBIT,(R2)
(R1)

040000
004000
001000

#12.5(R1)
6(R1)

*ALL TABLE DONE
:BR IF MORE TO GO
:SET NUMBER OF DQ11S TO 0
*SET TABLE POINTER
:GET FIRST FLOATING ADDRESS
*SET FOR TIME OUT TRAP--NO DEVICE--

BIS
CLR

BEQ

010000
030000

;CLEAR ALL STATUS TABLE
‘DO CLEAR

#10000, (R1)
w3oooo 6(R1)

MOVB

000002

#1400,R2
(R2) +

MOV
cMP
BNE
MOV

MOVB
CLR

SEQ 0015

:GO TO START OF PROGRAM

#1512.R2
.6
DANUM
#1400 ,R2
#160000,R1
¥

TST
BEQ

000006
000002

001400

.START

TMMP
BNE
CLR
MOV
MOV
MOV

MOVB

000005

001400

005737
001434

18%:

00000%

000504

000510

000005

745

746

000004
000006

002000

000362

.=220

001512

000006

012761

724

726
727
728
729
730
731
732
733
734
735
736
737
738
739

CSRMAP: MOV
CLR

005761

000350

000370

001400

000017

000356

725

JMP

112761

722

723

001512

112761

005761
001402

08:30 PAGE 16
ROUTINES USED FOR AUTO SIZING.

DQACTV

*ZERO ACTIVE DQ11S

*HEY BUDDY. NO DQ11S FOUND IN SYSTEM

MOV
MOV

DQGNUM,R1
R1, SAVNUM

*SAVE NUMBER OF DQ11S
*SAVE NUMBER FOR ACT11

ROL
INC

DSACTV
DOACTV

A ACTIVE ADDRE
SS
SET BIT

cLC

:CLEAR CARRY

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN-78 08:52

768
769
770
771
772
773
776
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802

803
804

805
806

807

000776
012716

001000
001006

1
005377
042101

001022
001030
001036
001044

044524
044507
052123
020124

001014

001200
001202
001204
001206
001210
001212

030461

000004
001502
000022

012702
012700
012701
000137
104402
01€525
005000

000606
000610
000612
700614
000620

#6, N

DQACTV
SSVACT

c1406R2
#300, RO
#302 ,R1
VECMAP

A ¥

000466

RTI

050504
050504
040524
047514
042524
051101
000

001200

.=1200

177570
177570
177560
177562
177564
177566

SWR:
LIGHTS:
TKCSR:
TKDBR:
TPCSR:
TPDBR:

JASCIZ

#2%, (SP)

SEQ 0016
;DEC NUMBER OF DQ11S
:BR IF MORE TO GO
:RESET TIME OUT VECTOR
s SAVE ACTIVE

:SET 10T TRAP PRIO: TO 7
sSET TABLE POINTER
sSET VECTOR START
;SET VECTOR+2 START
;GO FIND THE VECTORS

s TYPE MESSAGE

;1 DIDN'T FIND ANY DQ11S. DON'T USE AUTO SIZE.

sHOW CAN I TEST NO DQ11S
sDON'T LET OPR HIT CONT. SwW
;ENTERED BY TIME OUT TRAP
;GO HOME.

<377><12>/CIDQAD0/<377>/DQ11 STATIC LOGIC TEST=PART 1/<377>

s INDIRECT POINTERS
177570
177570
177560
177562
177564
177566

sSWITCH REGISTER POINTER
;DISPLAY REGISTER POINTER
sTELETYPE KEYBOARD CONTROL REGISTER
sTELETYPE KEYBOARD DATA BUFFER
:TELEPRINTER CONTROL REGISTER
;TELEPRINTER DATA BUFFER

;PROGRAM (ONTROL PARAMETERS

001214
001216
001220
001222
001224
001226
001230
001232
001234

000000
000000
000000
000003
000000
000000
000000
000000
000000

RETURN:

NEXT:
LOCK:
ICOUNT:
:
LPCNT
TSTNO:
PASCNT:

:
ERRCNT
LSTERR:

OOODOOWOOO

767

000562
000566
000572
000576
000602

005301
001371
012737
013737
012737

:SCOPE ADDRESS FOR LOOP ON TEST
sADDRESS OF NEXT TEST TO BE EXECUTED
sADDRESS FOR _LOCK ON CURRENT DATA
sNUMBER OF ITERATIONS THAT CURRENT TEST WILL BE EXECUTED
sNUMBER OF ITEREATIONS COMPLETED
sNUMBER OF TEST IN PROGRESS
sNUMBER OF PASSES COMPLETED
s TOTAL NUMBER OF ERRORS
<PC OF LAST ERROR CALL

: PROGRAM VARIABLES

757
758
759
760
761
76%
763
764
765
766

000534
000536
000540
000546
000554

001236
001240
001242
001244
001246

002000
000000
000000
000000
000000

CHART:

CHARZ:

(HARS:
TEMP1:

TEMP?2:

jelelelele

752
753
754
755
756

08:30 PAGE 17
ROUTINES USED FOR AUTO SIZING.

: TEMPORARY STORAGE
; TEMPORARY STORAGE

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN-78 08:52
808
809
810
811
812

813
814
815
816
817
818
819
820
821
822
823

001250
001252
001254
001256
001260

001262
001264
001266
001270
001272
001274
001276
001300
001302
001304
001306

000000
000000
000000
000000
000000

000000
000000
000000
000000
000000
000000
000000
000001
000000
000000
000000

08:30 PAGE 18
PROGRAM PARAMETERS, VARIABLES, AND TRAP CALLS.
TEMP3:
TEMP4:
TEMPS:
SAVRO:
SAVR1:

SAVR2:
SAVR3:
SAVRS4:
SAVRS:
SAVSP:
SAVPC:
SAVNUM:
CREAM:
RUNFLG:
RUN:
RUNCNT:

0
O
0
0
0

0
0
0O
0
0
O
0
_BLKW
O
0
O

: TEMPORARY STORAGE
; TEMPORARY STORAGE
: TEMPORARY STORAGE
;RO STORAGE
;R1 STORAGE

;R2 STORAGE
:R3 STORAGE
;R4 STORAGE
;RS STORAGE
;STACK PCINTER STORAGE
;sPROGRAM COUNTER STORAGE
1

SEQ 0017

CZDQA
MACY11_30A(1052)
9-JuL-78
CZDQAD.P11
27-JUN-78 08:52

08:30

PAGE 19

SEQ 0018

PROGRAM PARAMETERS, VARIABLES, AND TRAP CALLS.

8888

b
— d nd

W =2O

e
clh i

8888

WWWW

;PROGRAM CONTROL FLAGS

000000

INIFLG:
STFLG:
ERRFLG:
gekgLG:

.BYTE
.BYTE
.BYTE

0
O
0

.BYTE

sPROGRAM INITIALIZATION FLAG
sTEST START FLAG
sERROR OCCURED FLAG

sLOCK ON CURRENT TEST FLAG

sDEFINITIONS FOR TRAP SUBROUTINE CALLS
sPOINTERS TO SUBROUTINES CAN BE FOUND
;IN THE TABLE IMMEDIATLY FOLLOWING THE DEFINITIONS

001314

001316

001320
001322
001324

001326

001332

001334

001336
001340

001346

AR AR AR AR AR R AR AR
AR AR AR AR

017220

104414
016262
104415
016336

AR AR A AR AR AR

AR AR AR AR AR AR A AR AR

AR AR

AR A AR R AR

hkhhh

AR AR AR AR AR AR RN RNk

;CALL TO SCOPE LOOP AND ITERATION HANDLER

SCOPT=TRA§E§:$

sCALL TO LOOP ON CURRENT DATA HANDLER

TYPE=TRA?;$PE

sCALL TO TELETYPE OUTPUT ROUTINE

INSTR:TR@?&%TR

sCALL TO ASCII STRING INPUT ROUTINE

INSTER=T??Z§?ER

;CALL

PARAM=TRAP+5

sCALL TO NUMERICAL DATA INPUT ROUTINE

RESO5=TRAP+7

;CALL TO REGISTER RESTORE ROUTINE

SAVOS=TR§§2§3:

001330

001344

.TRPTAB:
SCOPE=TRAP+0

001314

001342

TO INPUT ERROR HANDLER

;CALL TC REGISTER SAVE ROUTINE

CONVRT=T%S§2€§T

;CALL TO DATA OUTPUT ROUTINE

CNVRT=TRAP+11

;CALL

TO DATA OUTPUT ROUNTINE WITHOUT CR/LF.

MSTCLR=T6§§¥E%R

;CALL TO ISSUE MASTER CLEAR

MEMCLR:T?:EEEER

sCALL TO CLEAR ALL SCRATCH PAD MEMORIES

CKSUR=TR?€;;3R

;CALL

CNTLU=TR?€&}EU

sCALL TO ALLOW LOADING OF

TO ALLOW SWREG TO BE LOADED FROM TTY

SWREG FROM TTY

:tfitttttttttttfitfi.tt""tt"tfi.ti'ltttlt'tfi.tittltfi"l'it..'t"t't'tt
AR

;DQ1T

001350
001352
001354
001356

001362

DQRVEC:
DORLVL:
DQTVEC:
DATLVL:
DCRCSR:
DQRCSH:

Q
0
O
O
0
0

A AR R

A AR A

AR AR AR

AR AR AR R AR AR AR AR AR AR AR R AR AR

VECTOR AND REGISTER INDIRECT POINTERS

;POINTER
;POINTER
;POINTER
sPOINTER
;POINTER
;POINTER

TO
TO
TO
TO
TO
TO

DQ11
DQ11
DQ11
DQ11
DQ11
HIGH

RECEIVER INTERRUPT VECTOR
RECEIVER INTERRUPT SERVICE PS
TRANSMITTER INTERRUPT VECTOR
TRANSMITTER INTERRUPT SERVICE PS
RECEIVER CONTROL REGISTER
BYTE OF DQ11 RECEIVER CONTROL REGISTER

CZDQA
MACY11_30A(1052)
19-JuL~-78
:
CZDQAD.P11
27=JUN-78 08:52

880
881

883
884
885
886
887
888
889
890

881364
1366
001370
001372
001374

000000
000000
000000
000000
000000

08:30

PROGRAM PARAMETERS,

DQTCSR:
DQERR:
DQREG:
DQSEC:
DQSECH:

0
0
0

.=1400
DQCROO:
DQSTO0:
DQCRO1:
DQSTO1:
DQCRO2:
DQSTO2:
DQCRO3:

sPOINTER TO HIGH BYTE OF ERROR REGISTER

sPOINTER TO DQ11 SECONDARY REGISTER
;POINTER TO HIGH BYTE OF DQ11 SECONDARY REGISTER

STATUS TABLE AND ADDRESS ASSIGNMENTS

BLKW
BLKW
BLkW
BLKW
BLKW
BLKW «
BLKW
DQSTO3: BLKW
DQCRO4: BLKW
DQSTO4: BLKW
DQCROS: BLKW
DQSTOS: BLkW
DQCRO6: BLkW
DQSTO6: BLKW
DQCRO7: BLKW
DQSTO7: .BLKw
DQCR10: BLKW
DQST10: BLKW
DOCR11: BLKW
DQST11: BLKW
DQCR12: .BLKW
DQST12: BLKW
DQCR13: BLKW
DAST13: .BLKW
DQCR14: BLKW
DQST14: BLKW
DQCR15: .BLKW
DQST15: BLKW
DQCR16: BLKW
DQST16: BLKW
DQCR17: BLKW
DQST17: BLKW
DQACTV: BLKW
SAVACT: BLKW
DQNUM:
BLKW
DQCSR:
BLKW
DQSTAT: BLKW

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

;CONTROL STATUS REGISTER FOR DEVICE NO: 00
;VECTOR AND CONFIGURATION STATUS FOR DEVICE
;CONTROL STATUS REGISTER FOR DEVICE NO: 01
;VECTOR AND CONFIGURATION STATUS FOR DEVICE
;CONTROL STATUS REGISTER FOR DEVICE NO: 02
;VECTOR AND CONFIGURATION STATUS FOR DEVICE
s CONTROL STATUS REGISTER FOR DEVICE NO: 03
sVECTOR AND CONFIGURATION STATUS FOR DEVICE
;CONTROL STATUS REGISTER FOR DEVICE NO: 04
;VECTOR AND CONFIGURATION STATUS FOR DEVICE
;CONTROL STATUS REGISTER FOR DEVICE NO: 05
;VECTOR AND CONFIGURATION STATUS FOR DEVICE
;CONTROL STATUS REGISTER FOR DEVICE NO: 06
:VECTOR AND CONFIGURATION STATUS FOR DEVICE
;CONTROL STATUS REGISTER FOR DEVICE NO: 07
;VECTOR AND CONFIGURATION STATUS FOR DEVICE
;CONTROL STATUS REGISTER FOR DEVICE NO: 10
:VECTOR AND CONFIGURATION STATUS FOR DEVICE
;CONTROL STATUS REGISTER FOR DEVICE NO: 11
sVECTOR AND CONFIGURATION STATUS FOR DEVICE
;CONTROL STATUS REGISTER FOR DEVICE NO: 12
;VECTOR AND CONFIGURATION STATUS FOR DEVICE

1
1
1
1
1
1
1
1
1
1
1
1
1

13
;CONTROL STATUS REGISTER FOR DEVICE NO: 14
;VECTOR AND CONFIGURATION STATUS FOR DEVICE NO: 14
;CONTROL STATUS REGISTER FOR DEVICE NO: 15
:VECTOR AND CONFIGURATION STATUS FOR DEVICE NO: 15
:CONTROL STATUS REGISTER FOR DEVICE NO: 16
sVECTOR AND CONFIGURATION STATUS FOR DEVICE NO: 16
sCONTROL STATUS REGISTER FOR DEVICE NO: 17
sVECTOR AND CONFIGURATION STATUS FOR DEVICE NO: 17
sHOLD ACTIVE BITS FOR TESTING
:SAVE NUMBER OF ACTIVE DQ11S
;OCTAL NUMBER OF TOTAL NUMBER OD DQi1S
sCSR OF DQT1 UNDER TEST
;VECTOR AND CONFIGURATION STATUS OF DQ11 UNDER TEST

1
1

NO: 00

NO: 01
NO: 02

NO: 03
NO: 04
NO: 05
NO: 06
NO: 07

NO:

s CONTROL STATUS REGISTER FOR DEVICE NO: 13
;VECTOR AND CONFIGURATION STATUS FOR DEVICE NO:

sPROGRAM INITIALIZATION

sLOCK OUT INTERRUPTS
sSET UP PROCESSOR STACK

;SET UP POWER FAIL VECTOR

s CLEAR PROGRAM CONTROL FLAGS AND COUNTS
sTYPE

SEQ 0019

VARIABLES, AND TRAP CALLS.

sPOINTER TO DQ11 TRANSMITTER CONTROL REGISTER
;POINTER TO DQ11 ERROR REGISTER

;DQ11

001400

PAGE 20

TIT.E MESSAGE

000024
001276

#64$, s

000006
000004

001200
001202

;CLEAR START FLAG
;CLEAR PASS COUNT
:CLEAR ERROR FLAG
;CLEAR ERROR COUNT
;CLEAR LAST ERROR POINTER
sSET UP FOR TEST 1
sSET_UP FOR POWER FAIL BEFORE

#.START ,RETURN

;TESTING STARTS
sMOV HARDWARE SWR TO SWR

sMOV DISPLAY LIGHTS TO LIGHTS
s SAVE VECTORS

w6, (
YA -<sp>

64%:

65%:
668%:

;SET UP FOR TIMEOUT

#-1 dSUR

;REFERENCE HARDWARE

(SP)+, (SP)+

sADJUST STACK
sPOINT TO SOF TWARE SWITCH REG
sPOINT TO SOFT DISPLAY REG
sRESTORE VECTORS

658"
66$

#SWREG, SWR

#DISPREG,L IGHTS
(SP)
+, a4
(SP)+. a6

001310

001200

000220
017012
001400

BN
67
soxxwxxxTHE NEXT 4 LINES OF
TSTB
INIFLG
12%
BNE
TYPE
JMTITLE
coms
INIFLG
#SWREG,
SWR

67%

67%:

aSWR
+6

PC, CSRMAP

177252

001244
001246

000002

001244

000001

177160

. XHEAD
#1400, TEMP1

ATEMPT
, TEMP?
.+16

#2.,TEMP1
12%:

#5w00, aSWR
ik

RO
177140

001502

SEQ@ 0020

;LOCK OUT INTERRUPTS
:SET UP STACK
;SET UP POWER FAIL VECTOR

#STACK,SP
#.PFAIL ,a#24

DQNUM, SAVNUM
STFLG
PASCNT
ERRFLG
RUNFLG
#1400, CREAM
ERRCNT
LSTERR
#1,TSTNO

061300

177232

104414

#340,PS

000004
177326

177570

001000
001310
000176

027737

.START: MOV

2
N €3§§ ssssssssoss
FUSEENEERNE ¥
-

177776

#DSWR
, SWR
#DLIGHTS LIGHTS

012737
012637
012637
005737
001014

000
032777
001424
104402
016733
005000
000000

001200
001202

001402
000407
022626
012737

105737

08:30 PAGE 21
PROGRAM INITIALIZATION AND START UP.

001226
001214

012737
012737
013746
013746
012737
022777

012737

—>

012737
012706
012737
013737

1?-JUL-78

Vi owvn

CZDQA
MACY11_30A(1052)
CZDQAD.P11
27-JUN-78

aSwR,SAVA(T

SWITCH REGISTER

2UNDER MONITOR

CODE MOVED

TO SOLVE PRA2757 (JUNE

78)%axsax

sHAS INITIALIZATION BEEN PERFORMED?

;IF YES, BR

sTYPE

TITLE MESSAGE

.IF NOT SET FLAG AND INIT

. IS SWREG USED

CZDQA
MACY11 30A(1052)
19-JuL=-78
CZDQAD.P11
27-JUN~78 08:52
992
993
994
995
996
997

002042
002044
002046
002050
002052
002054

000776
017737

999
1000
1001
1002
1003

002066
002070
002072
002076
002102

000000
104414
012700
012701
010120

1005

002106

022021

998

1004

1006

}885

002062

002104

002110

002114

101404
104402
016574

013700

177120

001500

9000300
000302

001372

=2
@SWR, DQACTV

1$:

HAL
T
CKSWR
MOV
MOV
MOV

#300.R0
#302.R1
R1, (RO)+

CMP

(RO)+, (R1)+

CLR

0010C0

CMP

BNE

002116
002124

012737
012706

002130
002134
002136
002140
002146
002150
002154
002162
002170
002172

005737
001040
104414
032777
001411
104402
012737
012737
000406
013737

1024

002206

032777

1025
1026
1027
1028
1029
1030
1031
1032
1033

1034

1035
1036
}855

1039
1040
1041
1042
1043

1064
1045

1046
1047

DQACTV,RO

(R1)+

#1000.,R0

JTEST START AND RESTART

1013
1014
1015
1016
1017
1018
1019
1020
1021
1022

1023

MOV

SEQ 0021

118

MOV

}8(1)3

1011
1012

BLOS
TYPE
MERR3
HAL
T
BR

11%:

2%:

005021

022700

08:30 PAGE 22
PROGRAM INITIALIZATION AND START UP.

002200

002214
002216
002220
002222
002224
002226
002230
002232
002233

002234

002236
002244
002250

013737

001410
104403
016620
104405
002254
014160
001214
001
001

000403

012737
104402
000177

000340
001200

177776

000042

.BEGIN: MOV
MOV

000004

177032

016632
000240
000240

014446
014450

014544

014446

18$:

TST
BNE
CKSWR
BIT
BEQ
TYPE
MOV
MOV
BR
MOV

000002

176764

2%:

BIT

014546

014450

MOV

BYTE

002254
016522
176740

001214

3%:
4$:

#340,PS
#STACK , SP

;LOCK OUT INTERRUPTS
*SET UP STACK

ans 2
3s

;1S PROGRAM UNDER MONITOR CONTROL

#BIT2,aSWR
1%
,MLOCK
#NOP, TTST
ANOP . TTST+2
2%
BRW,TTST

BRX.TTST+2

#swW01,aSWR

BEQ
33
INSTR
MTSTPC
PARAM
TST1
TLAST
#RE TURN
1
1

MOV
TYPE
e ¢ {np

#TST1,RETURN
MR
SRE TURN

:CHECK FOR <G>
:CHECK FOR LOCK ON TEST

;SET UP TO LOCK

;LOCK NOT SELECTED., SET UP FOR NORMAL SCOPE LOOP

“IF SWO1=1, GET STARTING PC

;START AT TEST 1
*TYPE R
*START TESTING

:-ttitt'tttttttitttttttt’tt'ittttt.tttttttttQtttttttttttt'ttttntt"ttt

002254
002262
002270
002276

002302
002304

002312
002320

012737
012737
012737
105737

001010
012737

012737
105137

000001
002644
002644
001302

001226
001214
001216

000001

001304

000020
001302

001306

T7ST1:

MOV
MOV
MOV
TSTB

BNE
MOV

MOV
COMB

#1,TSTNO
#TST2,RE TURN
#TST2
. NEXT
RUNFLG

;IS THIS MY FIRST TIME HERF?

#74. RUNCNT
RUNFLG

:SET FOR MAX OF
“SET RUN FLAG

1%
#8170, RUN

:BR IF FLAG IS SET
*SET RUN POINTER,

16 DQ11'S PER SYSTEM

CZDQA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN~78 08:52
1048
1049
1050
1051
1052

002324
002332
002334
002340
002342

033737
001032
005737
001423
000257

001304

1054
1055
1056
1057

001500

002350
002356
002362
002364

062737
005337
001360
012737

000004
001306

001300

000020

001306

1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072

002400
002406
002410
002412
002414
002416
002420
002422
002426
002434
002442
002450
002456
002464

012737
000746
704402
016525
000000
000776
000257
006137
017737
062737
017737
062737
013737
013737

000001

001304

001304
176646
000002
176632
000002
001506
001510

1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1085
1087
1088
1089
1090
}835

002500
002506
002514
002522
002530
002536
002544
002552
002556
002564
002572
002600
002606
002614
002620
002626
002632
002640

013737
062737
013737
062737
013737
062737
013737
005237
013737
062737
013737
062737
013737
005237
013737
005237
013737
005237

001350
000002
001352
000002
001354
000002
001360
001362
001360
000002
001364
000002
001366
001370
001370
001372
001372
001374

1073

002372

002472

012737

042737

1$:

BIT
BNE
TST
BEQ
cCC

001500

1053 002344 006137 001304

1058

001400

001300

3%:
001506
001300
001510
001300
001360
001350

001350

#1400, CREAM

MOV
ADD
MOV
ADD
MOV
ADD
MOV
INC
MOV
ADD
MOV
ADD
MOV
INC
MOV
INC
MOV
INC

001364
001364
001366

0071366
001379
001372
001374

#4, CREAM
RUNCNT
1%
#16. ,RUNCNT

#1,RUN
1%

=2
RUN
@CREAM,DQCSR
#2,CREAM
oCREAM,DQSTAT
#2,CREAM
DQCSR,DQRCSR
DOSTAT,DQRVEC

#177007 ,DQRVE C

DQRVEC,DQRLVL
#2,DORLVL
DQRLVL ,DQTVEC

#2,DQTVEC
DQTVEC,DQTLVL
#2.DOTLVL

DQRCSR,
DQRC SH
DQRCSH
DQRCSR,DQTCSR
#2,DQTCSR
DQTCSR.DQERR

#2 .DOERR
DQERR, DQREG
DOREG
DQREG, DQSEC

DQSEC
DOSEC,DQSECH

DQSECH

SEQ 0022

;FIND AN ACTIVE DQ11 TO TEST.
:BR IF 1 FOUND ONE TO TEST.
*FIND OUT IF THERE ARE NO D@11 ACTIVE.
:BR TO FATAL ERROR. WHY AM | HERE IF NO ACTIVE DQ11°'S$???
:CLEAR ALL THE CONDITION CODES OF CPU

“UPDATE
RUN POINTER

:UPDATE ADDRESS POINTER.
:DEC NUMBER OF TIMES I LOOKED AT ACTIVE.
:BR AND KEEP LOOKING.
:START RESTORING MY POINTERS.

*RESTORE

ADDRESS POINTER

*RESTORE RUN POINTER.
*KEEP ON TESTING.
*ALLERT OPERATOR OF FATAL ERROR
*NO DQ11 ACTIVE. WHY AM | HERE???
:YOU MUST RELOAD DQ11 DIAGNOSTIC!!
*STICK HERE ON CONT.
:CLEAR CPU COND. CODES
*UPDATE RUN. ACTIVE DQ11 FOUND.
:PLACE ADDRESSS OF DQ11 AT DQCSR
“UPDATE ADDRESS POINTER
;PLACE STATUS OF DQi1 AT DQSTAT
*UPDATE ADDRESS POINTER

;GENERATE ADDRESS OF RECEIVER INTERRUPT SERVICE PS
;GENERATE ADDRESS OF TRANSMITTER INTERRUPT VECTOR
;GENERATE ADDRESS

TRANSMITTER INTERRUPT SERVICE PS

;GENERATE ADDRESS OF HIGH BYTE
:GENERATE ADDRESS OF TRANSMITTER CONTROL REGISTER
;GENERATE ADDRESS OF ERROR REGISTER

;GENERATE ADDRESS OF HIGH BYTE OF ERROR REGISTER
;GENERATE ADDRESS OF SECONDARY REGISTER
:GENERATE ADDRESS OF HIGH BYTE

;ADDRESS SELECTOR TEST
*ADDRESS RECEIVER CONTROL REGISTER

}832

:VERIFY THAT RECEIVER CONTROL REGISTER RESPONDS TO ADDRESSING

1097

1(”8

TEST 2

.'ttttQttttttt'ttttttttt'tttttttt'lttt'ttttIttt".lttttttit't'ttt'tt't

002644
002652

012737
012737

1101

002660

012737

000002
002730
002706

1103

002674

013705

001360

1102

MOV

BIC

001352
001352
001354
001354
001356
001356
001362

1093
1094

1099
1100

RUN

MOV
BR
TYPE
MERR2
HALT
BR
cce
ROL
MOV
ADD
MOV
ADD
MOV
MOV

RUN,DQACTV
38
DQACTV
2%

ROL

ADD
DEC
BNE
MOV

2%:

177007

08:30 PAGE 23
PROGRAM INITIALIZATION AND START UP.

002666

012737

000340

001226
001216
000004

000006

TST2:

MOV
MOV

MOV

#2,TSTNO
#TST3 NEXT
218,344

;SET UP TO RETURN FROM

DQRCSR,RS

:GET ADDRESS OF RECEIVER CONTROL REGISTER

#3270, 46

*BUS ERROR TRAP

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN-78 08:52
1104

1
1
1
1

1
1

1
1
1
1
1
1
1
1

1
1

.4-J—LJ-J—M&-J—LM-J_hJnhd-J—hfl;:;?g—fl—hfl-fl—hfl-fl—hfl-fl—hfl—d—LJ—J—?G—J—MJ—J—MJ—MJ-J—LJ—J—LJ—LJ
VWV NNNNWNWNES NN NN
WWWWWWNWNWNW
IS LASTAS [aST)S
Ty ST\
ettt
o

(%)

002700

002704
002706

002710
002714
002722
002726

005777

000401
104000

012706
012737
005037
104400

08:30 PAGE 24
BASIC DQ11 ADDRESSING TESTS.

176454

18:
001200
000006
000006

000004

TST

aDQRCSR

MOV
MOV
CLR
SCOPE

#STACK,SP
#6, N
b

BR
HLT

2%:
3%:

SEQ 0023
sADDRESS RECEIVER CONTROL REGISTER

2%
0

sNO TRAP, REGISTER RESPONDED
:RECEIVER CONTROL REGISTER DID NOT

sRESPOND TO ADDRESSING

:RESTORE STACK
sRESTORE TRAPCATCHER

;CHECK FOR ITERATIONS, LOOP

sADDRESS SELECTOR TEST
sADDRESS TRANSMITTER CONTROL REGISTER
;VERIFY THAT TRANSMITTER CONTROL REGISTER RESPONDS TO ADDRESSING
3

TEST 3

002730
002736
002744

012737
012737
012737

000003
003014
002772

002760

013705

001364

002770
002772

000401
104000

002774
003000
003006

012706
012737
005037

002752
002764

003012

012737
005777

104400

000340

001226
001216
000004

R A

7TST3:

000006

AR AR A

000004

TR AR AR AR AR

MOV

DQTCSR,RS

*GET ADDRESS OF TRANSMITTER CONTROL REGISTER

2$
0

:NC TRAP, REGISTER RESPONDED
*TRANSMITTER CONTROL REGISTER DID NOT

aDQTLSR

MOV
MOV
CLR

AR R

;SET UP TO RETURN FROM

#340, a6

28:

A A AR A A AR AR AR AR AR

#3, TSTNO
#TST4 NEXT
13, a6

BR
HLT

1%:

MOV
MOV
MOV

MOV

176374

001200
000006
000006

:ADDRESS TRANSMITTER CONTROL REGISTER

*RESPOND TO ADDRESSING

#STACK, SP
26, 4
b

SCOPE

:BUS ERROR TRAP

*RESTORE STACK
*RESTORE TRAPCATCHER

:CHECK FOR ITERATIONS, LOOP

sADDRESS SELECTOR TEST
sADDRESS ERROR REGISTER

;VERIFY THAT ERROR REGISTER RESPONDS TO ADDRESSING
;

TEST 4

003014
003022
003030

012737
012737
012737

000004
003100
003056

003044

013705

001366

003054

000401

003060
003064
003072

012706
012737
005037

003036
003050

003056

003076

012737

005777

000340

001226
001216
000004

000006

001200
000006
000006

000004

A AR

A A

A AR

#4,TSTNO
#TSTS NEXT
18,

MOV

DQERR,RS

#340,an6

TST

aDQERR

18:

HLT

2%:

MOV
MOV
CLR

3$:

A AR A AR R R AR AR AR AR AR AR AR AR AR AR RR AR A AR AR AR

MOV
MOV
MOV

MOV

176312

104000

104400

TST4:

SCOPE

;SET UP TO RETURN FROM

*BUS ERROR TRAP

:GET ADDRESS OF ERROR REGISTER

:ADDRESS ERROR REGISTER

*NO TRAP, REGISTER RESPONDED

*ERROR REGISTER DID NOT

#STACK , SP
26, 4
b

*HESPOND TO ADDRESSING
*RESTORE STACK
*RESTORE TRAPCATCHER

;CHECK FOR ITERATIONS. LOOP

;ADDRESS SELECTOR TFST
sADDRESS SECONDARY REGISTER
;VERIFY THAT SECONDARY REGISTER RESPONDS TO ADDRESSING
:

003100

012737

000005

001226

TESYT S

CARR AR AR AR AR AR

7STS:

MOV

RR,.

SRR

AR R R AR R AR

#5,TSTNO

RN AR AR AR RANR RN R RN PR RN

RN R R

1
1
1
1
1
1

1
1

1
1
1
’

1
1

—

b
D
e
D D
D
D D
D
D D
D
D
D
D
)

A AR A AR A A

AR AR A AR AR A AR AR AR AR AR AR R AR R AR R AR AR AR AR

#100,aDQTCSR

012777

000200

176144

MOV

#200,aDQERR

012777

000400

176142

012705
017704
013703
020504
001401
104001
006305

000040

#400,aDQSEC

#40,R5
aDQRCSR,R4

176120

001360

DQRCSR,R3
R5,R4
1%
1

176104

077400
000002

176062
170000

2%:

000002

sREAD RECEIVER CONTROL REGISTER
:SET UP ADDRESS OF RECEIVER CONTROL REGISTER
HASIRECEIVER COTROL REGISTER ADDRESSED

;BR

sREGISTER ADDRESSING ERROR

RS ‘R
38

176042

:WITH BITS
;JLOAD TRANSMITTER CONTROL
JREGISTER WITH BITé
;LOAD ERROR REGISTER
:WITH BIT7
.LOAD SECONDARY REGISTER
JWITH BIT8
sFIRST EXPECTED DATA

RS
aDQERR, R4
#2.,R3

3%:

;LOAD RECEIVER CONTROL REGISTER

BUSSITRAcggITTER CONTROL REGISTER ADDRESSED

#170000, R4

000002

RS
aDQTCSR,R4
#77400,R4
#2,R3
RS.R&

012777

TST6:

MOV

001226
001216
176150

1
1
1
1
1

000006
003364
000040

000100

012737
012737
012777

176152

sCHECK FOR ITERATIONS, LOOP

#6,TSTNO
#TST7 NEXT
#40,3DQRCSR

:RESTORE STACK
sRESTORE TRAPCATCHER

TEST 6
R

3%:

#STACK,SP

#6, b
awé

MOV
MOV
MOV

VIS WN=O

)

2%
0

sNUMBER AND VERIFY THAT THE CORRECT REGISTER
;WAS ADDRESSED

;GET ADDRESS OF SECONDARY REGISTER
sADDRESS SECONDARY REGISTER
sNO TRAP, REGISTER RESPONDED
: SECONDARY REGISTER DID NOT
:RESPOND TO ADDRESSING

;LOAD EACH PRIMARY REGISTER WITH A DIFFERENT

) d D

DQSEC,R5

aDQSEC

MOV
MOV
CLR
SCOPE

SEQ 0024

sSET UP TO RETURN FROM
;BUS ERROR TRAP

#340, a6

2%:

;PRIMARY REGISTER ADDRESSING TEST

d e

#TST6, NEXT
218 ans

) e

001216
000004

1
1
1

) e

D e

003164
003142
000340
001372
176232

001200
000006
000006

]

012737

08:30 PAGE 25
BASIC DQ17 ADDRESSING TESTS.

1%:

e e

003106

—

)

S LS LNV
NN |

—_

D -3

CESEEEEREE 2EIRTRC223E RRRERV2BIFINARNANIITEIGIRER 2

CZDQA
MACY11_30A(1052)
19=JuL-78
CZDQAD.P11
27=JUN-78 08:52

1
RS
R4
aDQSEC
#2,R3
R5.R4
1

:NEXT EXPECTED DATA

:READ TRANSMITTER CONTROL REGISTER

:CLEAR UNWANTED BITS
sUPDATE ADDRESS OF EXPECTED REGISTER

sNEXT EXPECTED DATA
:READ ERROR REGISTER
sCLEAR UNWANTED BITS

:UPDATE EXPECTED REGISTER ADDRESS

:WAS ERROR REGISTER ADDRESSED
:BR IF _GOOD
sREGISTER ADDRESSING ERROR

sNEXT EXPECTED DATA

:READ SECONDARY REGISTER

sUPDATE EXPECTED REGISTER ADDRESS

:WAS SECONDARY REGISTER ADDRESSED

:BR_IF_GOOD

sREGISTER ADDRESSING ERROR

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN-78 08:52

1216
1217
1218
1219
1220

003342
003346
003352
003356
003362

005077
005077
005077
005077
104400

176012
176012
176010
1176010

08:30 PAGE 26
BASIC DQ11 ADDRESSING TESTS.

4$:

5%:

CLR
CLR
CLR
CLR
SCOPE

aDQRCSR
aDQTCSR
aDQERR
aDQSEC

SEQ 0025

;CLEAR
;CLEAR
;CLEAR
;CLEAR
;CHECK

SEL
SEL
SEL
SEL
FOR

0
2
4
6
ITERATIONS, LOOP

CZDQA
MACYT 30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN-78 08:52

1221
1222
1223

J 1226
1228

1229

1230
1231
1232
1233
1234

:CLEAR BIT1, VERIFY BIT1 WAS CLEARED

:
003364

012737

000007

013703

001360

003372

012737

003404

012705

003400

003440

001226

00121€

TST7:

AR AR

MOV

000002

010513

AR AR AR AR AR AR AN AR AR ARRARRARRNARARRARR
R AR AR

#7 .TSTNO

#TST10,NEXT

DQRCSR,R3

MoV

#BIT1,RS

MOV

R5, (R3)

1237
1238
1239
1240
1241

003414
003416
003420
003422

020504
001401
104002
040513

CMP
BEQ
HLT
BIC

R5,R4
1%
2
R5.(R3)

1243
1244
1245
1246
1247
}gzg

003424

003426

011304

MOV

CLR

003430
003432
003434
003436

020504
001401
104002
104400

CMP
BEQ
HLT
SCOPE

R5.R4
2%
2

1%:

005005

2%:

1250
1251

;

1255

1257

1258
1259

003440

003446

012737

000010

003514

013703

001360

1260

003460

012705

000010

1262

003464

010513

1263

1264

1265
1266
1267

1268

1269

1270
1271
1272
1273
1274
1275
1276

TEST 10

003454

1261

(R3) ,R4

: (R4)=ACTUAL DATA

;IN RECEIVER CONTROL REGISTER

sARE EXPECTED AND RECEIVED VALUFS THE SAME ?
sRECEIVER CONTROL REGISTER DATA ERROR
:CLEAR BITS SET
sIN RECEIVER CONTROL REGISTER
sREAD RECEIVER CONTROL REGISTER
: (RS)=EXPECTED CONTENTS
:OF RECEIVER CONTROL REGISTER, 0

;WAS RECEIVER CONTROL CLEARED

sRECEIVER CONTROL REGISTER DATA ERROR
sCHECK FOR ITERATIONS, LOOP

;CLEAR BIT3, VERIFY BIT3 WAS CLEARED

1254

1256

(R3) ,R4

;LOAD R3 WITH ADDRESS
;OF RECEIVER CONTROL REGISTER
RECEIVER CONTROL REGISTER WILL
;BE SET TO BIT1
;LOAD RECEIVER CONTROL

sRECEIVER CONTROL REGISTER READ/WRITE TEST
;SET BIT3, VERIFY BIT3 WAS SET

}Sg%

MOV

1242

MOV

011304

1236

003410

; VST V

003412

1235

SEQ 0026

sRECEIVER CONTROL REGISTER READ/WRITE TEST
;SET BIT1,
VERIFY BIT1 WAS SET

1227

08:30 PAGE 27
BASIC RECEIVER READ/WRITE TESTS.

001226

001216

TST10:

KRR

R AR AR AR AR

AR R RN R AR

MOV

#10,TSTNO

MOV

DQRCSR,R3

MoV
MOV

#BI1T3,R5

MOV

RS,

;LOAD RECEIVER CONTROL

(R3)

MOV

003470
003472
003474
003476

020504
001401
104002
040513

cMP
BEQ
HLT
BIC

RS, (R3)

003500
003502

011304
005005

MOV
(LR

(R3) .R4
RS

003504

020504

001401
104002
104400

CMP

;LOAD R3 WITH ADDRESS
;OF RECEIVER CONTROL REGISTER
RECEIVER CONTROL REGISTER WILL

011304

003506
003510
003512

RRARRRARRRARRRAA AR

#TST11,NEXT

003466

1$:

ARRR AR

BEQ
HLT

(R%) R4

R5.R4
1%
2

RS ,R4

2%
é

;BE SET TO BIT3

: (R4)=ACTUAL DATA

sIN RECEIVER CONTROL' REGISTER
JARE EXPECTED AND RECEIVED VALUES THE SAME ?
sJRECEIVER CONTROL REGISTER DATA ERROR
;CLEAR BITS SET

:IN RECEIVER CONTROL REGISTER

:READ RECEIVER CONTROL REGISTER
s (R5)=EXPECTED CONTENTS
:OF RECEIVER CONTROL REGISTER, O
;WAS RECEIVER CONTROL CLEARED
;RECEIVER CONTROL REGISTER DATA ERROR
sCHECK FOR ITERATIONS, LOOP

CZDQA
MACYN 30A(1052)08 1?5JUL-78
CZDQAD.P11
27=JUN=7

08:30 PAGE 2 8
BASIC RECEIVER READ/WRITE TESTS.

SEQ 0027

;RECEIVER CONTROL REGISTER READ/WRITE TEST

“SET BIT4,

VERIFY BIT4 WAS SET

*CLEAR BIT4, VERIFY BIT4 WAS CLEARED
:

TEST 11

t.Qtt't'tt'ti"'tt.ttt"t".ttfi't.tQtt'ifittt'fit"."tt'ttiQQ."Q.Q'Q

TST11:

MoV
MOV

#11,TSTNO
#TST12 NEXT

MOV

#BIT4,RS

:LOAD R3 WITH ADDRESS
;OF RECEIVER CONTROL REGISTER
*RECEIVER CONTROL REGISTER WILL

010513
011304

MOV

RS, (R3)

:LOAD RECEIVER CONTROL

020504
001401

ggz

§2.R4

:IN RECEIVER CONTROL REGISTER
:ARE EXPECTED AND RECEIVED VALUES THE SAME 2

HLT
BIC

2
RS, (R3)

:RECEIVER CONTROL REGISTER DATA ERROR
:CLEAR BITS SET

011304
005005

MOV
CLR

(R3) R4
RS

:READ RECEIVER CONTROL REGISTER
: (RS)=EXPECTED CONTENTS

020504
001401

ggg

gg.a4

:OF RECEIVER CONTROL REGISTER, 0
:WAS RECEIVER CONTROL CLEARED

HLT

;RECEIVER CONTROL REGISTER DATA ERROR

012737
012737
013703

000011
003570
001360

012705

000020

001 226
001 216

MOV

104002

040513

1%:

104002
104400

2%:

SCOPE

: (R4)=ACTUAL DATA

:IN RECEIVER CONTROL REGISTER

:CHECK FOR ITERATIONS, LOOP

:SET BITS, VERIFY BITS WAS SET
*CLEAR BITS, VERIFY BITS WAS CLEARED

i
D il

e
b

TEST 12

b end

012705

000040

MOV

#BITS RS

010513
011304

MOV

RS,

020504
001401

g?g

qg.n4

:IN RECEIVER CONTROL REGISTER
;ARE EXPECTED AND RECEIVED VALUES THE SAME 2

HLT
BIC

2
RS, (R3)

;RECEIVER CONTROL REGISTER DATA ERROR
:CLEAR BITS SET

MOV
CLR

(R3) R4
RS

:READ RECEIVER CONTROL REGISTER
*(RS)=EXPECTED CONTENTS

égg

gg,aa

HLT

D ek

001360

;'ttttttttttitttttttttt"tt'itttt'tt*tt'ttfi!tttttttttttttttfittt'ttitt

MOV
MOV

il il ncld il il

D il il i

D il il ol

D il il

WWWWWWWWWW

(RS) R4

*BE SET TO BIT4

012737
012737
013703

000012

TST12:

1$:

—
R

MoV

MOV

) i

N WNWWWWNW
WW
Y]

DQRCSR.R3

;RECEIVER CONTROL REGISTER READ/WRITE TEST

D il il

D i i i e

) i

) i i

sl i

i wih i

R 3SR a3 SESAASR
R AR R AR L 4

1285

2%:

SCOPE

#12,TSTNO

#TST13, NEXT
DQRCSR.R3

(R3)

(R%) .R4

;:LOAD R3 WITH ADDRESS

:OF RECEIVER CONTROL REGISTER

*RECEIVER CONTROL REGISTER WILL

*BE SET TO BITS

:LOAD RECEIVER CONTROL

:(R4)=ACTUAL DATA

:IN RECEIVER CONTROL REGISTER

:OF RECEIVER CONTROL REGISTER, 0

*WAS RECEIVER CONTROL CLEARED

:RECEIVER CONTROL REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

CZDQA
MACY11_30A(1052)
19-JUL-78
CZDQAD.P11
27=JUN-78 0 8:52

W
~

*CLEAR BIT6, VERIFY BIT6 WAS CLEARED

=S5O

;

TEST 13

.'tttttttttttttittttt*ttt'ttttttttfittttt.ttttt"ttt“tttt.fittt'."t."'

012737
012737
013703

000013
003720
001360

012705

000100

001226
001216

TST13:

NNNNNNNNN

EEREREREE

#13,TSTNO
#TST14 NEXT
DQRCSR.R3

:LOAD R3 WITH ADDRESS

MOV

#B1T6,RS

*RECEIVER CONTROL REGISTER WILL

MOV

RS, (R3)

:OF RECEIVER CONTROL REGISTER

*BE SET TO BIT6

MOV

020504

ggz

§;.R4

<IN RECEIVER CONTROL REGISTER
:ARE EXPECTED AND RECEIVED VALUES THE SAME ?

HLT
BIC

2
RS, (R3)

;RECEIVER CONTROL REGISTER DATA ERROR
*CLEAR BITS SET

MOV
CLR

(R3) R4
RS

*READ RECEIVER CONTROL REGISTER
*(RS)=EXPECTED CONTENTS

ggg

gg,aa

1%:

(R3) ,R4

HLT

2%:

:LOAD RECEIVER CONTROL

* (R4)=ACTUAL DATA

:IN RECEIVER CONTROL REGISTER

*OF RECEIVER CONTROL REGISTER, 0
‘WAS RECEIVER CONTROL CLEARED

:RECEIVER CONTROL REGISTER DATA ERROR

SCOPE

:CHECK FOR ITERATIONS, LOOP

;RECEIVER CONTROL REGISTER READ/WRITE TEST
*SET BIT7, VERIFY BIT7 WAS SET
*CLEAR BIT7, VERIFY BIT7 WAS CLEARED

D D D e

D
e e e D e e D e D e
W WWWWWWWWW

MoV
MOV
MOV

010513
011304

;

TEST

"tt'tt*itfittt'tttt*ttttttttt'ttfitttttfittt'titttttttit'tttitttttfit'*t'

012737
012737
013703

000014
003774
001360

012705

000200

001226
001216

TsT14:

mov
MOV

#14,TSTNO
#CKRB0 ,NEXT

DORCSR.R3

:LOAD R3 WITH ADDRESS

MOV

#B1T7.RS

*RECEIVER CONTROL REGISTER WILL

MOV

RS, (R3)

5?8

gi.n4

*IN RECEIVER CONTROL REGISTER
:ARE EXPECTED AND RECEIVED VALUES THE SAME 2

HLT
BIC

2
RS, (R3)

;RECEIVER CONTROL REGISTER DATA ERROR
:CLEAR BITS SET

MOV
CLR

(R3) R4
RS

ggg

gg,nc

HLT

MOV

010513
011304

MOV

020504
001401
1$:

(R%) ,R4

e e

SEQ 0028

;RECEIVER CONTROL REGISTER READ/WRITE TEST
*SET BIT6, VERIFY BITé WAS SET

D D e

D D D

d e

D d D ) e

D D

R= S 00 UGN R AR = SO0 NN

D d d

JHIIIRIIEELRERERE §3&&&&&&&&&fffiffififlfflflwg

—

WWW

1333
1334
1335
1336

—

08: 30 PAGE 29
BASIC RECEIVER READ/WRITE TESTS.

SCOPE

*OF RECEIVER CONTROL REGISTER

‘BE SET TO BIT7

:LOAD RECEIVER CONTROL

(R4)=ACTUAL DATA

*IN RECEIVER CONTROL REGISTER

*READ RECEIVER CONTROL REGISTER
*(RS)=EXPECTED CONTENTS

:OF RECEIVER CONTROL REGISTER, 0
:WAS RECEIVER CONTROL CLEARED

;RECEIVER CONTROL REGISTER DATA ERROR

*CHECK FOR ITERATIONS, LOOP

CZDQA
MACY11_30A(10 52)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

032737
001530

020000

08: 30

001510

PAGE 30

SEQ 0029

BASIC RECEIVER READ/WRITE TESTS.

CkBBO:

BIT
BEQ

#BBBIT,DQSTAT
CONT.O

;RECEIVER CONTROL REGISTER READ/WRITE TEST
;SET BIT8, VERIFY BIT8 WAS SET
;CLEAR BIT8, VERIFY BIT8 WAS CLEARED
;

TEST 15

TST15:

MOV
MOV

#15,TSTNO
#TST16 NEXT

012705

MOV

#BIT8.RS

;LOAD R3 WITH ADDRESS
:OF RECEIVER CONTROL REGISTER
*RECEIVER CONTROL REGISTER WILL

010513
011304

MOV

RS, (R3)

:LOAD RECEIVER CONTROL

ggg

q;.n4

012737
012737
013703

A A

MOV

(R3) R4

HLT

1%:

2%:

AR AR R AR A AR AR AR AR AR

DQRCSR.R3

MOV

020504
001401

RS, (R3)

MOV
CLR

(R3) R4
RS

ggg

Sg.nc

HL i

SCOPE

RA AR AR R AR AR

*BE SET TO BITS

:(R4)=ACTUAL DATA

<IN RECEIVER CONTROL REGISTER
;ARE EXPECTED AND RECEIVED VALUES THE SAME ?

BIC

A AR

;RECEIVER CONTROL REGISTER DATA ERROR

:CLEAR BITS SET

<IN RECEIVER CONTROL REGISTER

*READ RECEIVER CONTROL REGISTER
: (RS)=EXPECTED CONTENTS

“OF RECEIVER CONTROL REGISTER. 0
*WAS RECEIVER CONTROL CLEARED

;RECEIVER CONTROL REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

sRECEIVER CONTROL REGISTER READ/WRITE TEST
;SET BIT9, VERIFY BIT9 WAS SET
;CLEAR BIT9, VERIFY BIT9 WAS CLEARED
.

TEST 16

MoV

ss
222323323323222322222 33

#16,TSTNO

012705

MOV

#BIT9.RS

010513
011304

MOV

RS,

020504
001401

5?8

fii'R‘

HLT
BIC

2
RS, (R3)

011204
005005

MOV
CLR

020504
001401

g?g

(R3) ,R4
RS
=
gfi'R4

B2 ER RRER R : o

g8 &

XX NS arvo &R

TST16:

012737
012737
013703

104002

040513

MOV
MOV

MOV

1$:

#TST17 NEXT
DQRCSR.R3

:LOAD R3 WITH ADDRESS

*RECEIVER CONTROL REGISTER WILL

:OF RECEIVER CONTROL REGISTER

*BE SET TO BIT9

(R3)

*LOAD RECEIVER CONTROL

(RS) ,R4

*(R4)=ACTUAL DATA

:IN RECEIVER CONTROL REGISTER

:ARE EXPECTED AND RECEIVED VALUES THE SAME

)

;RECEIVER CONTROL REGISTER DATA ERROR
*CLEAR BITS SET

s IN RECEIVER CONTROL REGISTER
sREAD RECEIVER CONTROL REGISTER

: (RS)=EXPECTED CONTENTS
;OF RECEIVER CONTROL REGISTER, O

;WAS RECEIVER CONTROL CLEARED

CZDQA
MACY11_30A(105 2)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

004130
004132

08: 30

104002
104400

PAGE 31

SEQ 0030

BASIC RECEIVER READ/WRITE TESTS.
HLT

28:

SCOPE

;RECEIVER CONTROL REGISTER DATA ERROR

*CHECK FOR ITERATIONS, LOOP

;RECEIVER CONTROL REGISTER READ/WRITE TEST
*SET BIiT10,

VERIFY BIT10 WAS SET

*CLEAR BIT10, VERIFY BIT10 WAS CLEARED
:

TEST 17

"ttt'tttfittttttttt**tttttt*tttitfitittittttfit'fi.ttflfi"t'titttt’Qttt*t*

012737
012737
013703

000017
004210
001360

012705

002000

001226
001216

TsT17:

MoV
MOV

MOV

#17,TSTNO
#TST20,NEXT

DOQRCSR.R3

:LOAD R3 WITH ADDRZSS

*OF RECEIVER CONTROL REGISTER

MOV

#8IT10,RS

010513
011304

MOV

RS, (R3)

020504

ggg

$2,R4

*IN RECEIVER CONTROL REGISTER
:ARE EXPECTED AND RECEIVED VALUES THE SAME 2

HLT
BIC

2
RS, (R3)

;RECEIVER CONTROL REGISTER DATA ERROR
*CLEAR BITS SET

MOV
CLR

(R3) ,R4
RS

g?g

gg.RA

MOV

1$:

(R3) R4

HLT

2%:

:RECEIVER CONTROL REGISTER WILL

*BE SET TO BIT10

*LOAD RECEIVER CONTROL

* (R4)=ACTUAL DATA

:IN RECEIVER CONTROL REGISTER

*READ RECEIVER CONTROL REGISTER
*(R5)=EXPECTED CONTENTS

*OF RECEIVER CONTROL REGISTER, 0
‘WAS RECEIVER CONTROL CLEARED
;RECEIVER CONTROL REGISTER DATA ERROR

SCOPE

*CHECK FOR ITERATIONS, LOOP

;RECEIVER CONTROL REGISTER READ/WRITE TEST
*SET BIT11, VERIFY BIT11 WAS SET
*CLEAR BIT11, VERIFY BIT11 WAS CLEARED
;
" LA

TEST 20
A

012737
012737
013703

000020
001360

MOV
MOV

012705

004000

TsT20:

010513
011304

MoV

1$:

222323 2332323233333 32323222322222223223222222222223;

#TST21 ,NEXT
DORCSR.R3

:LOAD R3 WITH ADDRESS

MOV

#81T11.RS

*RECEIVER CONTROL REGISTER WILL

MOV

RS,

MOV

020504

#20,TSTNO

(R3)

(R3) ,R4

:OF RECEIVER CONTROL REGISTER

*BE SET 10 BIT11

:LOAD RECEIVER CONTROL

:(R4)=ACTUAL DATA

g?g

§2.R4

*IN RECEIVER CONTROL REGISTER
:ARE EXPECTED AND RECEIVED VALUES THE SAME ?

HLT
BIC

2
RS, (R3)

;RECEIVER CONTROL REGISTER DATA ERROR
*CLEAR BITS SET

MOV
CIR

(R3) ,R4
RS

g?g

gi,n4

*IN RECEIVER CONTROL REGISTER

*READ RECEIVER CONTROL REGISTER
*(RS)=EXPECTED CONTENTS

*OF RECEIVER CONTROL REGISTER, 0
‘WAS RECEIVER CONTROL

CLEARED

CZDQA
MACY11_30A(10 52)
19-JyuL-78
CZDQAD.P11
27=JUN-78 08:52

004260
004262
004264

*N#}QXFAU“AU“A%’ \flU“hUHAUTSUHAVHAUHAU“flUNAU“hJ“hU“fl
NN n

SEQ 0031

BASIC RECEIVER READ/WRITE TESTS.

104002
104400

HLT

28:
SCOPE
CONT.O:

*SET BIT12,

;RECEIVER CONTROL REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

VERIFY BIT12 WAS SET

*CLEAR BIT12, VERIFY BIT12 WAS CLEARED

N Y S YUY YO YO T YO S G S Y
vivivviaoawvivaiunau
N YO S
R
R S
S
I
T

e R
i
et
e
R
AR AR AR AL Y, 1Y, ]
Vi
SN
W
o VB WN=O0VONO
NS WN=0O0

PAGE 32

:RECEIVER CONTROL REGISTER READ/WRITE TEST

=
BIFNRUKLEZRIR VIS W mflg_ha_a_ha_ha_ha—figsrj
VNN
WO
~

1501
1502
1503
1504
1505
1506

08: 30

TEST 2

:lttt!tt*tttt'ttttfi&*ttttt'ttttttttttttttitfittt'tt.ttttt'tt't*ttttfi't

012737
012737
013703

000021
004340
001360

001226
001216

TsT21:

MoV

MOV
MOV

#21,TSTNO

#CHKBA1 ,NEXT
DQRCSR,R3

;LOAD R3 WITH ADDRESS

MOV

#BIT12.RS

:OF RECEIVER CONTROL REGISTER
*RECEIVER CONTROL REGISTER WILL

010513
011304

MOV

RS,

*LOAD RECEIVER CONTROL

020504
001401

ggg

qg.na

*IN RECEIVER CONTROL REGISTER
:ARE EXPECTED AND RECEIVED VALUES THE SAME 2

HLT
BIC

2
RS, (R3)

;RECEIVER CONTROL REGISTER DATA ERROR
*CLEAR BITS SET

MOV
CLR

(R3) ,R4
RS

ggg

gg.RA

‘WAS RECEIVER CONTROL CLEARED

HLT

;RECEIVER CONTROL REGISTER DATA ERROR

012705

010000

MOV

1%:

2%:

SCOPE

(R3)

(R3) ,R4

*BE SET TO BIT12

: (R4)=ACTUAL DATA

*IN RECEIVER CONTROL REGISTER

*READ RECEIVER CONTROL REGISTER
*(RS)=EXPECTED CONTENTS

*OF RECEIVER CONTROL REGISTER, 0

*CHECK FOR ITERATIONS, LOOP

;IF DATASET CONTROL OPTION IS INSTALLED,

STEST 22 AND TEST 23 WILL BE EXECUTED

032737
001454

010000

001510

(HKkBA1: BIT
BEQ

#BABIT,DQSTAT

TST24

;RECEIVER CONTROL REGISTER READ/WRITE TEST

*SET BIT13, VERIFY BIT13 WAS SET
*CLEAR BIT13, VERIFY BIT'3 WAS CLEARED
TEST 22

;.t'h't'tt'.ti'fitfiitttt"'!"tfi!Q.tt..tt..fitfifit.tt...t..'."""Q't.'

004350
004356
004364

012737
012737
013703

000022
004424
001360

004370

012705

020000

004374
004376

010513
011304

004400
004402
004404

020504
001401

104002

00 12 2 6
12 6
]

Ts122:

MoV

#22.TSTNO

MOV

#TST23, NEXT
DORCSR.R3

;LOAD R3 WITH ADDRESS

MOV

#8iT13.RS

*RECEIVER CONTROL REGISTER WILL

MOV

RS,

(R%) R4

*(R4)=ACTUAL DATA

é?g

?g,qa

:ARE

HLT

;RECEIVER CONTROL REGISTER DATA ERROR

MOV

(R3)

*OF RECEIVER CONTROL REGISTER

*BE SET TO BIT13

*LOAD RECEIVER CONTROL

:IN RECEIVER CONTROL REGISTER

EXPECTED AND RECEIVED VALUES THE

SAME

LA L

004406

040513

004410
004412

004414
004416
004420
004422

1%:

RS, (R3)

;CLEAR BITS SET

011304
005005

MOV
CLR

(R3) ,R4
RS

; (R5)=EXPECTED CONTENTS

020504
001401

ggg

gg.R4

;OF RECEIVER CONTROL REGISTER, O
;WAS RECEIVER CONTROL CLEARED

HLT

JRECEIVER CONTROL REGISTER DATA ERROR

2%:

SCOPE

s IN RECEIVER CONTROL REGISTER
sREAD RECEIVER CONTROL REGISTER

;CHECK FOR ITERATIONS, LOOP

i i

;RECEIVER CONTROL REGISTER READ/WRITE TEST
;SET BIT14, VERIFY BIT14 WAS SET

) i

:CLEAR BITi4, VERIFY BIT14 WAS CLEARED
TEST 23

004424
004432
004440

012737
012737
013703

001360

004444

012705

040000

004450
004452

“ST23:

MOV

sl eI
2322222323222 23

#23,TSTNO

#TST24 NEXT
DORCSR.R3

MOV

#BIT14,RS

010513
011304

MOV

RS,

004454
004456

020504
001401

g?g

fig.na

<IN RECEIVER CONTROL REGISTER
:ARE EXPECTED AND RECEIVED VALUES THE SAME 2

004462

040513

HLT
BIC

2
RS, (R3)

;RECEIVER CONTROL REGISTER DATA ERROR
:CLEAR BITS SET

004464
004466

011304
005005

MOV
CLR

(R3) R4
RS

*READ RECEIVER CONTROL REGISTER
“(RS)=EXPECTED CONTENTS

004470
004472
004474
004476

020504
001401

ggg

gg,qa

:WAS RECEIVER CONTROL CLEARED

HLT

;RECEIVER CONTROL REGISTER DATA ERROR

104002

MOV

1%:

2%:

SCOPE

D e

viuawviuvnoaviunioawn

D e

vivioavioaown

(¥,]

D i

MOV
MOV

D i

001226
001216

ARttt

d cd i

000023
004500

D D i

SEQ 0032

BIC

08: 30
PAGE 33
BASIC RECEIVER READ/WRITE TESTS.

O OO
4
~
QRIR W
S 3
’\’—‘8 B8 BRRERLRE0o SENPRNRRL

D i

i e

v
i

CZDQA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

(R3)

(R3) ,R4

:LOAD R3 WITH ADDRESS

:OF RECEIVER CONTROL REGISTER

*RECEIVER CONTROL REGISTER WILL

‘BE SET TO BIT14

:LOAD RECEIVER CONTROL

: (R4)=ACTUAL DATA

*IN RECEIVER CONTROL REGISTER

“OF RECEIVER CONTROL REGISTER, 0

“CHECK FOR ITERATIONS, LOOP

;RECEIVER CONTROL REGISTER READ/WRITE TEST

“SET BIT1S, VERIFY BIT15 WAS SET
*CLEAR BIT15. VERIFY BIT'S WAS CLEARED

1598

TEST 24
"'tttt.'Q't.fititt'tt'fi""""Qt'tt'.lt'tittt"....""...".Q"".Q.

004500

004514

012737
012737
013703

004520

012705

MOV

#8IT15.RS

*RECEIVER CONTROL REGISTER WILL

004524
004526

010513
011304

MOV

RS,

:LOAD RECEIVER CONTROL

004530
004532
004534

020504
001401

cMP
BEQ
HLT

RS.R4
12
2

104002

TST24:

MOV

#24, TSTNO

MOV
MOV

#TST25 NEXT
DORCSR.R3

:LOAD R3 WITH ADDRESS

MOV

(R3)

(R$) ,R4

:OF RECEIVER CONTROL REGISTER

‘BE SET TO BIT1S

:(R4)=ACTUAL DATA

*IN RECEIVER CONTROL REGISTER

:ARE EXPECTED AND RECEIVED VALUES THE SAME
JRECEIVER CONTROL REGISTER DATA ERKOR

CZDQA
MACY11_30A(1052)
19=-JuL-78
CZDQAD.P11
27=JUN~-78 08:52
1613

004536

040513

1615

004540

011304

1614

1616

1617
1618

004542

005005

004544

020504

1620
1621

004550
004552

104002
104400

1619

004546

08:30 PAGE 34
BASIC RECEIVER READ/WRITE TESTS.
1%:

001401

2%:

BIC

RS, (R3)

MoV

(R3) ,R4

CLR

CMP

RS .R4

BEQ

HLT
SCOPE

SEQ 0033
;CLEAR BITS SET

s IN RECEIVER CONTROL REGISTER

sREAD RECEIVER CONTROL REGISTER
; (RS)=EXPECTED CONTENTS

;OF RECEIVER CONTROL REGISTER, 0O
;WAS RECEIVER CONTROL CLEARED

JRECEIVER CONTROL REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

(ZDQA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN~78 08:52

08:30

PAGE 35

SEQ 0034

BASIC TRANSMITTER READ/WRITE TESTS.
; TRANSM]

ITER CONTROL REGISTER READ/WRITE

“SET BIT3, VERIFY BIT3 WAS SET

TEST

*CLEAR BIT3, VERIFY BIT3 WAS CLEARED
;:

012737

000025

013703

001360

012737

004640

001226

001216

ST &

Q'Qt'.tt'tt"t.t't‘.'lt"t.t.tQ'Q'Qt'ttt."...t."fit.'t'.t"t.Qt'ttt

TST25:

MOV

#25,TSTNO

MOV

#CKBAT ,NEXT
DQRCSR.R3

:LOAD R3 WITH ADDRESS

MOV

:OF

TRANSMIITER CONTROL REGISTER

012702

001400

MOV

#1400,R2

012705

000010

MOV

#B1T3,RS

*LOAD R2 WITH 1400
:TO CLEAR UNWANTED BITS
*TRANSMI ITER CONTROL REGISTER WILL

010513

MOV

RS, (R3)

:LOAD TRANSMIITER CONTROL

040204

BIC

R2.R4

:IN TRANSMIITER CONTROL REGISTER

HLT
BIC

3
RS, (R3)

011304
040204
005005

MOV
BIC
CLR

(R3) R4
R2.R4
RS

020504
001401
104003

CMP
BEQ
HLT

RS ,R4
2%
3

:TRANSMIITER CONTROL REGISTER DATA ERROR
*CLEAR BITS SET
:IN TRANSMIITER CONTROL REGISTER
*READ TRANSMIITER CONTROL REGISTER
*CLEAR UNWANTED BITS
:(RS)=EXPECTED CONTENTS
:OF TRANSMIITER CONTROL REGISTER, 0
*WAS TRANSMIITER CONTROL CLEARED

BIT
BEQ

#BABIT,DQSTAT
CONT.1

011304

MOV

88(1)28'1'

g?;

104003
040513

1044

032737
001432

1$:

010000

001510

2%:

CkBAl1:

SCOPE

(R%) R4

72.:@4

*BE SET 10 BIT3

“(R4)=ACTUAL DATA

*CLEAR UNWANTED BITS

:ARE EXPECTED AND RECEIVED VALUES THE SAME 2

;TRANSMIITER CONTROL REGISTER DATA ERROR

“CHECK FOR ITERATIONS, LOOP

;TRANSMITTER CONTROL REGISTER READ/WRITE

“SET BIT4,

VERIFY BIT4 WAS SET

TEST

*CLEAR BIT4, VERIFY BIT4 WAS CLEARED
TEST 26
t"'tttttt'tttt.ttttttt't'tt.!t'ttttttttttttttttt""l'ttt"'t.tt"t

012737
012737
013703

000026
004734
001364

001226
001216

T1ST26:

MOV
MOV
MOV

#26.,TSTNO
#1ST27 NEXT
DQTCSR.R3

012702

001400

MOV

#1400,R2

012705

000020

MOV

#BIT4 RS

:LOAD R3 WITH ADDRESS

:OF

TRANSMITTER CONTROL REGISTER

*LOAD R2 WITH 1400

:TO CLEAR UNWANTED BITS

011304

MOV

RS, (R3)

*TRANSMITTER CONTROL REGISTER WILL
*BE SET TO BIT4
:LOAD TRANSMITTER CONTROL

040204
85?28?

BIC
5?8

R2.R4
$§,n4

*CLEAR UNWANTED BITS
:ARE EXPECTED AND RECEIVED VALUES THE SAME 2

104003

HLT

:TRANSMITTER CONTROL REGISTER DATA ERROR

010513

(R%) .R4

: (R4)=ACTUAL DATA

:IN TRANSMITTER CONTROL REGISTER

CZDQA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN~-78 08:52
1678
1679
1680

004714

040513

1681
1682

004716
004720
004722

1684
1685

004724
004726

1683
1686
1687

;ggg

004730
004732

004734

1%:

BIC

RS, (R3)

011304
040204
005005

MOV
BIC
CLR

(R3) R4
R2.R4
RS

020504
001401

CMP
BEQ

RS.R4
2%

104003
104400

2%:

CONT.1:

1690
1691
1694

1699
1700
1701
1702

1703
1704

1705

1706
1707
1708
1709

1710
1711
1712
1713
1714

1715

1716

1717

1718
1719

};5?

;

TEST 27

004734
004742

012737
012737

000027
005020

004750

013703

001364

004754

012702

001400

004760

012705

000040

004764

010513

004766

040204
020504
001401
104003
040513

005002
005004
005006

011304
040204
005005

005010

005016

TST27:

1%:

020504

001401
104003

104400

*CLEAR UNWANTED BITS
: (RS)=EXPECTED CONTENTS

:OF TRANSMITTER CONTROL REGISTER, 0
:WAS TRANSMITTER CONTROL CLEARED

:TRANSMITTER CONTROL REGISTER DATA ERROR
:CHECK FOR ITERATIONS, LOOP

AR AR AR AR AR A AR R AR R AR AR AR AR R RN A RRARA RN AR

#27 ,TSTNO
#TST30,NEXT

DQTCSR.R3

:LOAD R3 WITH ADDRESS

MOV

#1400,R2

MOV

#BIT5.RS

MOV

RS,

:LOAD R2 WITH 1400
:TO CLEAR UNWANTED BITS
“TRANSMITTER CONTROL REGISTER WILL
*BE SET TO BITS
:LOAD TRANSMITTER CONTROL

(R3)

(R3) ,R4

BIC
CMP
BEQ
HLT
BIC

R2.R4
RS.R4
1%
3
RS, (R3)

MOV
BIC
CLR

(R3) R4
R2.R4
RS

CMP

RS.R4

BEQ
HLT

28%:

SCOPE

2%
“

:OF

TRANSMITTER CONTROL REGISTER

: (R4)=ACTUAL DATA

:IN TRANSMITTER CONTROL REGISTER
:CLEAR UNWANTED BITS
;ARE EXPECTED AND RECEIVED VALUES THE SAME
:TRANSMITTER CONTROL REGISTER DATA ERROR
:CLEAR BITS SET
:IN TRANSMITTER CONTROL REGISTER
:READ TRANSMITTER CONTROL REGISTER

*CLEAR UNWANTED BITS
: (RS)=EXPECTED CONTENTS
:OF TRANSMITTER CONTROL REGISTER, 0
:WAS TRANSMITTER CONTROL CLEARED
;TRANSMITTER CONTROL REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

;TRANSMITTER CONTROL REGISTER READ/WRITE TEST
*SET BIT6, VERIFY BIT6 WAS SET

*CLEAR BIT6, VERIFY BIT6 WAS CLEARED

1726

1727

TEST 30

".tttt.ttttfitttttttlt.ttttttttwttQ.tttt.tttttttttttttt'tttttttt.t't'l

005020

005026

012737

000030

012737

0051064

1730

005034

013703

001364

1732
1733

005040

012702

001400

1731

AR AR

MOV

};gg

1728

A AR

MOV
MOV

MOV

011304

004770
004772
004774
004776
005000

005012
005014

001226
001216

1722
1723

1729

;CLEAR BITS SET
:IN TRANSMITTER CONTROL REGISTER
:READ TRANSMITTER CONTROL REGISTER

;CLEAR BITS, VERIFY BITS5 WAS CLEARED

1695

1698

HLT
SCOPE

SEQ 0035

;TRANSMITTER CONTROL REGISTER READ/WRITE TEST
SSET BITS, VERIFY BITS WAS SET

}gg_g’

1696
1697

08:30 PAGE 36
BASIC TRANSMITTER READ/WRITE TESTS.

001226

001216

7ST30:

MOV

#30,TSTNO

MOV

DQTCSR.R3

MOV

#TST31 NEXT

#:700,R2

:LOAP R3 WITH ADDRESS

sOF TRANSMITTER CONTROL REGISTER

*LOAD R2 WITH 1400
“TO CLEAR UNWANTED BITS

CZDQA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN-78 08:52

1734
1735
173

1737

1738
1739

1740
1741
1742
17643
1744

1745

1746
1747
1748
1749
1750
1751

};gg

005044

012705

005050

010513

005052
005054
005056
005060
005062
005064

005066

000100

011304

040204
020504
001401
104003
040513

1774
1775
1776

1777

1778
1779
1780
1781

1782

1783

};gg

011304

MOV

(R%) ,R4

R2.R4
RS.R4
1%
3
RS, (R3)

(R3) ,Ré4

BIC
CLR

R2,R&
RS

005074
005076
005100
005102

020504
001401
104003
104400

CMP
BEQ
HLT
SCOPE

RS.R&
2%
3

2%:

SEQ 0036

:TRANSMITTER CONTROL REGISTER WILL
*BE SET TO BITé
:LOAD TRANSMITTER CONTROL

: (R4)=ACTUAL DATA

:IN TRANSMITTER CONTROL REGISTER
*CLEAR UNWANTED BITS

:ARE EXPECTED AND RECEIVED VALUES THE SAME

:TRANSMITTER CONTROL REGISTER DATA ERROR
:CLEAR BITS SET
<IN TRANSMITTER CONTROL REGISTER

*READ TRANSMITTER CONTROL REGISTER

*CLEAR UNWANTED BITS
:(RS)=EXPECTED CONTENTS
:OF TRANSMITTER CONTROL REGISTER, 0
*WAS TRANSMITTER CONTROL CLEARED
;TRANSMITTER CONTROL REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

:TRANSMITTER CONTROL REGISTER READ/WRITE TEST
“SET BIT7, VERIFY BIT7 WAS SET

SFUEAR BIT7, VERIFY BIT7 WAS CLEARED

TEST 31

tttt'tttttttt.tttt.t.i'tttttit.tt.ttt.fitlttttl".tttt.t'ttt'ttt.ttti

005104
005112
005120

012737
012737
013703

000031
005170
001364

005124

012702

005130

012705

005134

010513

005140
005142
005144
005146
005150

040204
020504
001401
104003
040513

005136

005152

005154
005156

005160

TST31:

MOV
MOV
MOV

#31,TSTNO
#CHKRA2 ,NEXT
DQTCSR,R3

001400

MOV

#1400,R2

000200

MOV

#BIT7.RS

MOV

RS,

011304

MOV

1$:

011304

020504

001401

005166

104400

BIC
CMP
BEQ
HLT
BIC

MOV

040204
005005

005162

005164

001226
001216

104003

2%:

(R3)

(R3) R4

R2.R4
RS.R4
1%
3
RS, (R3)

(R3) ,Ré4

BIC
CLR

R2.R4
RS

cMP

RS ,R&

HLT

BEQ

1786
};gg
1789

RS, (R3)

040204
005005

1759

1772
1773

MOV

005070
005072

1758

1770
1771

#B1T6,RS

BIC
CMP
BEQ
HLT
BIC

};gg

1769

MOV

1754
1755

1760
1761
1762
1763
1764
1765
1766
1767
1768

08:30 PAGE 37
BASIC TRANSMITTER READ/WRITE TESTS.

SCOPE

:LOAD R3 WITH ADDRESS
:OF TRANSMITTER CONTROL REGISTER
*LOAD R2 WITH 1400
:TO CLEAR UNWANTED BITS
“TRANSMITTER CONTROL REGISTER WILL
*BE SET TO BIT7
:LOAD TRANSMITTER CONTROL

: (R4)=ACTUAL DATA

:IN TRANSMITTER CONTROL REGISTER
:CLEAR UNWANTED BITS

:ARE EXPECTED AND RECEIVED VALUES THE SAME 2

:TRANSMITTER CONTROL REGISTER DATA ERROR
:CLEAR BITS SET
*IN TRANSMITTER CONTROL REGISTER

*READ TRANSMITTER CONTROL REGISTER

*CLEAR UNWANTED BITS
:(RS)=EXPECTED CONTENTS
:OF TRANSMITTER CONTROL REGISTER, 0
*WAS TRANSMITTER CONTROL CLEARED

:TRANSMITTER CONTROL REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

:I1F DATASET CONTROL OPTION IS INSTALLED,
STEST 32 AND TEST 33 WILL BE EXECUTED
005170

032737

010000

001510

(HKBA2: BIT

#BAB]T,DQSTAT

19-JuL-78
CZDQA
MACY11_30A(1052)
CZDQAD.P11
27-JUN-78 0 8:52

005176
005200

001002
000137

cd
i
s

JMP

.+6
CHKBA3

;SET BIT8 IN TRANSMITER CONTROL REGISTER

;CLEAR BITS8
;VERIFY THAT BIT8,BIT 10 AND BIT11 WERE CLEARED
;]
TR

000032
005366
001364
000400

TN %
AR A A A AR AR

TST32:

MOV

052705

#TST33, NEXT

#2,3DQSEC
aDASEC
aDQSEC

005524

001510

#JL1!281
T.DQSTAT

006000
100000

#BIT10+BIT11,RS

#BIT15,RS

020504

R5.R4
1%

174044

1%:

BIC

174040

3
#8178, (R3)

#12,aDQREG
#2.3DQSEC
aDASEC
aDQSEC
PC ,DELAY

(R%) .R4
0?1715 R4
R5.R4

HLT

2%:

AR ARk

#32,TSTNO

RS, (R3)
#12,3DQREG

174120
174114

040000

AR A AR A A AR AR R AR AR A AR A A AR AR AR AR AR AR AR

DQTCSR.R3
#RIT8,RS

000012
000002

WN=O

b cncd
e
e
b

VNN

BNE

;VERIFY THAT BIT8,BIT 10 AND BIT11 ARE SET

BRBED

e ad

SEQ 0037

BASIC TRANSMITTER READ/WRITE TESTS.

005626

VIEN (NN —

00 0o G0 0o 0o O 0O O 00 0o

. B

PAGE 38

sTRANSMITTER CONTROL REGISTER READ/WRITE TEST

ZRSRORAS IR 3

1790
1791

08: 30

SCOPE

;ADDRESS OF TRANSMITTER CONTROL REGISTER

:(R5)=BIT8
;LOAD TRANSMITTER CONTROL REGISTER
:TRY TO SEL MISC REGISTER
sTRY TO SET AUTO/STEP

sCLOCK UP!!
;CLOCK DN!!
;DELAY FOR REAL CABLE.
sREAD TRANSMITTER CONTROL REGISTER
;IS TEST JUMPER INSTALLED
;BR IF NO_JUMPER

;EXPECT BIT8,3IT 10 AND BIT11

;ADJUST EXPECTED RESULTS.
;FOR DATA SET INTR
JARE EXPECTED AND RECEIVED DATA THE SAME ?
;TRANSMITTER CONTROL REGISTER DATA ERROR

;CLEAR BIT8

:TRY AND SELECT THE MISC REG
:TRY AND SET AUTO/STEP TO STEP

sSET CLOCK UP!
: _ CLOCK DOWN!
;DELAY.
sREAD TRANSMITTER CONTROL REGISTER
;IGNORE BIT 15 FOR NOW.
JEXPECT 0

:WAS TRANSMITTER CONTROL REGISTER CLEARED
:BR IF GOOD
s TRANSMITTER CONTROL REGISTER DATA ERROR
:CHECK FOR ITERATIONS, LOOP

s TRANSMITTER CONTROL REGISTER READ/WRITE

sSET BIT9 IN TRANSMITER CONTROL REGISTER

TEST

;VERIFY THAT BIT9,BIT12 AND BIT13 ARE SET
.CLEAR BI 9

sVERIFY THAT BIT9,BIT12 AND BIT13 WERE CLEARED

;

TEST 33

888

§§x§

't"tttt'tt't..t't.ttti't't'Q'.".!ttt'tfiti'fit'ttt.i..tttti.t.tt.tti

001226
001216

TsT33:

Moy
MOV
MOV
MOV

#33,TSTNO

#TST34 NEXT
DCTCSR,R3

#B1T9,RS

;ADDRESS OF TRANSMITTER CONTROL REGISTER
;(RS)=BIT9

CZDQA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN-78 08:52
1846
1847

005412
005414

010513
004737

005524

1849

005422

032737

040000

1848

1850
1851

1852

1853

005420

005430
005432

005436

011304

001404
052705

052705

1854
1855
1856

005442
005444
005446

020504
001401
104003

1858
1859

005454
005462

112777
012777

1857

1860
1861
1862

1863
1864

1865
1866
1867
1868
1869
1870
1871
1872
1873
1874

}g;g

005450

005470
005474
005500

005504
005506

005512
005514
005516
005520
005522
005524
005526
005530
005532

005534

005536

005277
005377

173676
173672

004737

005005
020504
001401
104003
104400
010046
005000
105200
100376

000012
000002

173706
173702

1%:

100000

2%:
DELAY:

012600

1884

RTS

005540

005546

005554

012737

000034

013703

001364

012737

005005
005013
005013
011304
001401
104003
052705

1893

005602

011304

005600

010513

189%
1895
1896
1897
1898

005604
005606
005610
005612
005614

020504
001401
104003
005005
010513

1900

005620

001401

1901

#BIT15,R5

;ADJUST EXPECTED RESULTS.

;FOR DATA SET INTR

RS.R4
1%
3

*ARE EXPECTED
AND RECEIVED DATA THE SAME ?
JTRANSMITTER CONTROL REGISTER DATA ERROR

*CLEAR BIT9

#12,3DOREG
#2,aDQSEC

:TRY AND SELECT THE MISC REG
;TRY AND SET AUTO/STEP TO STEP
sSET CLOCK UP!
¢
CLOCK DOWN!
*DELAY.

PC,DELAY

(R3) Ré4
#BI1T15,R4

JREAD TRANSMITTER CONTROL REGISTER
:IGNORE BIT 15 FOR NOW.

RS
35 R%
2$
3

*EXPECT 0
sWAS TRANSMITTER CONTROL REGISTER CLEARED
*BR IF GOOD
;TRANSMITTER CONTROL REGISTER DATA ERROR
*CHECK FOR ITERATIONS, LOOP
;SAVE RO ON THE STACK
+ZERO RO
:DELAY...
*DONE YET?

RO,-(SP)
RO
RO
=2
(SP)+,R0
PC

*RESTORE RO

*RETURN.

JSET BIT 15 VERIFY SET; CLEAR BIT 15 VERIFY CLEARED.

005560
005562
005564
005566
005570
005572
005574

1899

CLR
CMP
BEQ
HLT
SCOPE
MOV
CLR
INB
BPL

:IS TEST JUMPER INSTALLED

JREAD WRITE TEST OF BIT 15 OF TRANSMITTER CSR.

1885
1886
1887
1888
1889
1890
1891

1892

*BR IF NO JUMPER
:EXPECT BIT9,BIT12 AND BIT13

aDQSEC
aDQSEC

MOV

000207

+12
#BI1T12+BI1T13,RS

INC
DEC

JSR

:LOAD TRANSMITTER CONTROL REGISTER
*DELAY FOR REAL CABLE.

“READ TRANSMITTER CONTROL REGISTER

#BIT9, (R3)

MOV
BIC

SEQ 0038

(RS) ,R4

BIC

MOVB
MOV

005524

1880

1882

#JUMBI
T ,DQSTAT

cMP
BEQ
HLT

}g;g

1883

BIT

BIS

1877

1881

RS, (R3)
PC,DELAY

BEQ
BIS

100000

001000

MOV
JSR

MOV

001510

030000

042713

011304
042704

08:30 PAGE 39
BASIC TRANSMITTER READ/WRITE TESTS.

005616

005622

011304

104003

005626

100000

001226
001216

TEST W%

tttt'tttttttttttttttttttttttttittfittittttttttttttttttttt'ttttttttttt

TST34:

MOV

MOV
MOV

1%:

2%:

#34, TSTNO

#CHKBA3
, NEXT
DQTCSR,R3

CLR
CLR
CLR
MOV
BEQ
HLT
IS

RS
(R3)
(R3)
(R3) R4
1%
3
#BIT15,RS

MOV

(R%) R4

MOV

RS,R4
2%
3
RS
RS, (R3)

BEQ

)

HLT

:CLR TX CSR

;DO IT AGAIN.
*READ TX CSR

:TX CSR NO ZERO.
*SET EXPECETD.

RS, (R3)

CMP
BEQ
HLT
CLR
MOV

MOV

:GET TX CSR

(R3) R4

:SET BIT 15

“READ CSR.

*EXPECTED=RECEIVED?
:

;TRANSMITTER DATA ERROR.
*SET EXPECETD
*CLEAR BIT 15

*READ CSR

:TX CSR NOT ZERO

19-JuL-78
27=-JUN-78 08:52

MACY11_30A(1052)

CZDQA

2832

| CZDQAD.P11
1

005624

08: 30

SCOPE

104400

;1F DATASET CONTROL OPTION IS NOT INSTALLED,

sTEST 35 WILL BE EXECUTED

032737
001017

\0\00082‘0000000 [}

1
1
E

)

001510

#BABIT,DQSTAT
TST36

CHKBA3: BIT
BNE

;EQUAL TO ZERO.

TEST 35

.".***.’*...*..*'***'..*""'..l..'.'.."..*.*'*""*.'...'...'.'*Qfi..

000J35
005674
001364

001226
001216

TST35:

MOV
MOV
MOV

#35,TSTNO
#TST36 ,NEXT
DQTCSR,R3

CLR
MOV
MOV

177400

HLT

1%:

R5
#177400, (R3)
(R3) R4

;LOAD REG
sSET EXPECTED.
;SET UPPER BYTE TO ALL 1°'S
;READ IT BACK.

;TRANSMITTER CSR NOT ZERO.

BEQ

010000

;IF DATASET CONTROL OPTION IS NOT INSTALLED,
:THE WHOLE UPPER BYTE OF THE TX CSR SHOULD BF

N NN
&~ W
=

005626
005634

So® NOWNESWN=O

SEQ 0039

BASIC TRANSMITTER READ/WRITE TESTS.

1
1
1
1

PAGE 40

SCOPE

;ERROR REGISTER READ/WRITE TEST

;SET BITO, VERIFY BITO AND BIT15 WERE SET
;CLEAR BITO, VERIFY BITO AND BIT15 WERE CLEARED
;

TEST 36

.-Qtttttttttttttttttttttttttttttttfittttttfifit*tttt*tttttitttt!t't* Ahkhhk

000036
005764
001366

]

1
1
1
1
1
1
1
1

NOWNSB

3393398

SRERRRRRRRRRR

W =0V
W =

1940

001226
001216

TST36:

MOV

#36,TSTNO

MOV

DQERR,R3

MOV

RS, (R3)

:LOAD R3 WITH ADDRESS
:OF ERROR REGISTER
:LOAD R2 WITH 60000
:TO CLEAR UNWANTED BITS
;ERROR REGISTER WILL
;BE SET TO BITO
;
D E RROR
*LOA

BIS
BIC

#BIT15,RS
RZ.R4

*IN ERROR REGISTER
“EXPECT BIT15 TO BE SET ALSO
;CLEAR UNMWANTED BITS

HLT
BIC

4
RS, (R3)

;ERROR REGISTER DATA ERROR
;sCLEAR BITS SET

MOV
BIC
CLR

(R3) ,R4
R2,R4
RS

HLT

012702

060000

MOV

012705

000001

MoV

010513
011304

052705

MOV
100000

é?g

1%:

#TST37 NEXT

MOV

#60000,R2
#B1T0,RS

(R%) ,R4

?2,R4

*(R4)=ACTUAL DATA

:ARE EXPECTED AND RECEIVED VALUES THE SAME ?

;IN ERROR REGISTER
JREAD ERROR REGISTER
sCLEAR UNMWANTED BITS
s (RS)=EXPECTED CONTENTS
:OF ERROR REGISTER, 0
:WAS ERROR CLEARED

;ERROR REGISTER DATA ERROR

(1052)

19-JuL~78

~JUN=78 08:52

08:30

104400

PAGE
41

SEQ 0040

ERROR REGISTER READ/WRITE TESTS.

28:

SCOPE

2
o RER
000
FoREREE

MACY11
CZDQA
CZDQAD.P11

:CHECK FOR ITERATIONS, LOOP

;ERROR REGISTER READ/WRITE TEST
*SET BIT1,
VERIFY BIT1 AND BIT15
WERE SET

d e

*CLEAR BIT1, VERIFY BIT1 AND BIT15 WERE CLEARED

)

000037

013703

001366

012702

060000

MOV

#60000,R2

012705

000002

MOV

#8IT1,RS

MOV

RS, (R3)

BIS
BIC
cMP
BEQ

#BIT15,RS
R2.R%
RS.R&
1%
4
RS, (R3)

;ERROR REGISTER DATA ERROR
*CLEAR BITS SET

011304
040204
005005

MOV
BIC
CLR

(R3) ,R4
R2,R&
RS

*READ ERROR REGISTER
*CLEAR UNWANTED BITS
*(RS)=EXPECTED CONTENTS

020504
001401

cMP
BEQ

RS,R4
2%

D
)
)
—

001216

TST37:

010513

011304

052705
040204
020504
001401

MOV

#37,TSTNO

MOV

DQERR.R3

3232323323322 333232323232 323323232322332222322223222323

012737

012737 006054

001226

BN W

2233332233233 2333233332333

MOV

MOV
100000

104
040513

HLT
BIC

1%:

104004
104400

HLT
SCOPE

2%:

#TST40 NEXT

(RS) R4

;LOAD R3 WITH ADDRESS
“OF ERROR REGISTER
*LOAD R2 WITH 60000
:TO CLEAR UNWANTED BITS
*ERROR REGISTER WILL

*BE SET TO BIT1
*LOAD ERROR

*(R4)=ACTUAL DATA

*IN ERROR REGISTER
“EXPECT BIT1S TO BE SET ALSO

*CLEAR UNWANTED BITS
*ARE EXPECTED AND RECEIVED VALUES THE SAME ?

*IN ERROR REGISTER

*OF ERROR REGISTER, 0
*WAS ERROR CLEARED

;:ERROR REGISTER DATA ERROR
“CHECK FOR ITERATIONS, LOOP

:ERROR REGISTER READ/WRITE TEST

“SET BIT2, VERIFY BIT2 AND BIT15 WERE SET
*CLEAR BIT2, VERIFY BIT2 AND BIT15 WERE CLEARED
TEST 40

2006
2008

Saro &R

5588 &8 &

.'ttttttt*ttttttttfittttttttt'ttttfttttittttfititttt*tt*t*ttttitttfittttt

012737
012737
013703

000040
0067144
001366

012702
012705

MOV
MOV
MOV

#40,TSTNO
#TST41 NEXT
DQERR,R3

:LOAD R3 WITH ADDRESS

060000

MOV

#60000,R2

:LOAD R2 WITH 60000

000004

MOV

#BIT2,RS

MOV

RS, (R3)

BIS
BIC
CMP
BEQ

#BIT15,RS
R2,R4
R R4
1%

010513

011304

052705
040204
020504
001401

26
16

TsT40:

MOV
100000

(R3) .R4

*OF ERROR REGISTER

*TO CLEAR UNWANTED BITS
*ERROR REGISTER WILL

*BE SET TO BIT?
*LOAD ERROR

: (R4)=ACTUAL DATA

*IN ERROR REGISTER
*EXPECT BIT1S TO BE SET ALSO

*CLEAR UNWANTED BITS
:ARE EXPECTED AND RECEIVED VALUES ThHE SAME 2

CZDQA
MACY11 30A(1052)
19-JuL=-78
CZDQAD.P11
27=JUN-78 08:52

2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
gggé

006122
006124

104004
040513

0061%8
0061
006132
006134
006136
006140
006142

C 4
08:30 PAGE 42
ERROR REGISTER READ/WRITE TESTS.

HLT
BIC

RS.(RS)

011304
040204
005005

MoV
BIC
CLR

(R3) R4
R2,R4
RS

020504
001401
104004
104400

CMP
BEQ
HLT
SCOPE

RS.R4
2%
4

1%:

2%:

2026
2027

;

2031

2034
2035
2036
2037
2038
2039
2040

2041

2042
2043

2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
gggg

TEST 41

Qtttttttttttt'tttttttittt'ttttt!ttttt*tfitttttttttttttttttfi'lttttttt'

006144

012737

000041

006152

012737

006234

006164

012702

006170

012705

006174

010513

006200

052705

006160

006176

013703

001226

TST41:

040204
020504
001401
104004
040513

006216
006220
006222
006224
006226
0062
006232

060000

MoV

#60000,R2

000010

MoV

#B1T3.RS

MoV

RS, (R3)

:LOAD R3 WITH ADDRESS
;OF ERROR REGISTER
:LOAD R2 WITH 60000
:TO CLEAR UNWANTED BITS
;ERROR REGISTER WILL
:BE SET TO BIT3
:LOAD ERROR

BIS

#BIT15,RS

:IN ERROR REGISTER
:EXPECT BIT15 TO BE SET ALSO

MOV

MOV
100000

(R3) ,R4

R2.R4
RS,R4
1$
4
RS, (R3)

011304
040204
005005

MOV
BIC
CLR

(R3) R4
R2.R4
RS

020504
001401
104004
104400

cMP
BEQ
HLT
SCOPE

RS.R4
2%
4

1$:

2%:

: (R4)=ACTUAL DATA

;CLEAR UNWANTED BITS
;ARE EXPECTED AND RECEIVED VALUES THE SAME ?
;ERROR REGISTER DATA ERROR
;CLEAR BITS SET
:IN ERROR REGISTER
;READ ERROR REGISTER
:CLEAR UNWANTED BITS
;(RS)=EXPECTED CONTENTS
:OF ERROR REGISTER, 0
:WAS ERROR CLEARED
;ERROR REGISTER DATA ERROR
:CHECK FOR ITERATIONS, LOOP

:ERROR REGISTER READ/WRITE TEST

:SET BIT4, VERIFY BIT4 AND BIT15 WERE SET

2061

;CLEAR BIT4, VERIFY BIT4 AND BIT15 WERE CLEARED

2063

TEST 42

2%‘

2067
2068
2069

DQERR,R3

BIC
CMP
BEQ
HLT
BIC

2060

2065

#41,TSTNO

#TST42 NEXT

011304

006204
006206
006210
006212
006214

MOV

001366

001216

2059

2066

:ERROR REGISTER DATA ERROR
:CHECK FOR ITERATIONS, LOOP

;CLEAR BIT3, VERIFY BIT3 AND BIT15 WERE CLEARED

2030
2032

:ERROR REGISTER DATA ERROR
;CLEAR BITS SET
;IN ERROR REGISTER
*READ ERROR REGISTER
;CLEAR UNWANTED BITS
; (RS)=EXPECTED CONTENTS
*OF ERROR REGISTER, 0
“WAS ERROR CLEARED

:ERROR REGISTER READ/WRITE TEST
;SET BIT3, VERIFY BIT3 AND BIT15 WERE SET

5853

2033

SEQ 0041

ttttttttttttttttttfitttttttt'tttttQtttttttltfitttttltttttttttttitttttt

006234

012737

000042

013703

001366

012702

060000

006242

012737

006254

006250

006324

001226

001216

TST42:

MOV

#642,TSTNO

MOV

#TST43 NEXT

MOV

#60000,R2

MOV

DOERR,R3

:LOAD R3 WITH ADDRESS
;OF ERROR REGISTER
:LOAD R2 WITH 60000

MACYN
A(1052)
19-JuL-78
CZDQA
CZDQAD.P11
27=JUN=78 08:52

006260

012705

000020

010573
0113ue
052705
040204
020504
001401

100000

RORSIRIRR
W

AR
N WY

N-AOON\IOUN\WN—'OS ~N

d
)

D e

PV NV NL NV NNV

D
D

NLNL NN NLNL AL

) e
=

#8174 RS

MOV

RS, (R3)

#BIT15,RS
R2.R4
RS R4
1%

040513

BIC

RS, (R3)

011304
040204
005005

MOV
BIC
CLR

(R3) ,Ré4
R2 R
RS

020504
001401

CMP
BEQ

RS ,R4
2%

HLT

HLT
SCOPE

SEQ 0042

;TO CLEAR UNWANTED BITS
;ERROR REGISTER WILL
;BE SET TO BIT4
;LOAD ERROR

(RS) R4

BIS
BIC
cMP
BEQ

104004
104400

— el e

MOV
MOV

104004

POV

08:30 PAGE 43
ERROR REGISTER READ/WRITE TESTS.

; (R4)=ACTUAL DATA

:IN ERROR REGISTER

;EXPECT BIT15 TO BE SET ALSO

sCLEAR UNWANTED BITS
JARE EXPECTED AND RECEIVED VALUES THE SAME ?

;ERROR REGISTER DATA ERROR
sCLEAR BITS SET
:IN ERROR REGISTER
;READ ERROR REGISTER
sCLEAR _UNWANTED BITS

; (RS5)=EXPECTED CONTENTS
;OF ERROR REGISTER, 0

;WAS ERROR CLEARED

;ERROR REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

;:ERROR REGISTER READ/WRITE TEST
*SET BITS, VERIFY BITS AND BIT1 5 WERE SET
*CLEAR BITS, VERIFY BITS AND BI T15 WERE CLEARED
TEST 43
SRR AR AR A AR R A AR AR AR AR AR

012737
012737
013703

000043
006414
001366

012702
012705

901401

04004
040513

MOV

#TST44 NEXT
DQERR,R3

060000

MOV

#60000,R2

000040

MOV

#BITS,RS

MOV

RS,

BIS
BIC
CMP
BEQ

#BIT15,RS
R2,R4
RS ‘R4
1%

MOV
100000

(R3)

(R3) ,R4

HLT

MOV
BIC
CLR

(R3) ,Ré4
R2,R4
RS

cMP
BEQ

RS,R4
2%

BIC

HLT

AR AARARAAARAREA AR

AR AR R A ARk hhn

#43,TSTNO

MOV
MOV

010513
011304

052705
040204
020504

001226
001216

RS, (R3)

SCOPE

JERROR REGISTER READ/WRITE TEST

;LOAD R3 WITH ADDRESS
;OF ERROR REGISTER
;LOAD R2 WITH 60000
;TO CLEAR UNWANTED BITS
;ERROR _REGISTER WILL

;BE SET TO BITS
;LOAD ERROR

: (R4)=ACTUAL DATA

;IN ERROR REGISTER
;EXPECT BIT15 TO BE SET ALSO
sCLEAR UNWANTED BITS
JARE EXPECTED AND RECEIVED VALUES THE SAME ?
;ERROR REGISTER DATA ERROR
;CLEAR BITS SET
;IN ERROR REGISTER
sREAD ERROR REGISTER
sCLEAR UNWANTED BITS

: (R5)=EXPECTED CONTENTS
;OF ERROR REGISTER, 0O

;WAS ERROR CLEARED

;ERROR REGISTER DATA ERROR
sCHECK FOR ITERATIONS, LOOP

CZDQA

MACY11_30A(1052)

CZDQAD.P11

19-JuL-78
27=JUN-78 08:52

2126

;CLEAR BIT6, VERIFY BIT6 AND BIT15 WERE CLEARED

2129

2130

2140

2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
g}gg

TEST 44

'-tttttttttttttlttittttt'ttttttttttttttQtttttttt!tttttt..ttttttt'tt't'

006414
006422
006430

012737
012737
013703

000044
006504
001366

006434

012702

006440

012705

006444

010513

006446

001226
001216

TST44:

MOV
MOV
MOV

#44, TSTNO
#TST4LS NEXT
DQERR,R3

060000

MOV

#60000,R2

000100

MOV

#IT6.RS

MOV

RS, (R3)

011304

006450
006454
006456
006460
006462
006464

052705
040204
020504
001401
104004
040513

006466
006470
006472

006474
006476
006500
006502

MOV
100000

#BIT15,RS
R2,R4
RS.R4
1%
4
RS, (R3)

011304
040204
005005

MOV
BIC
CLR

(R3) ,R4
R2,R4
RS

020504
001401
104C04
104400

CMP
BEQ
HLT
SCOPE

RS .R4
2%
4

1%:

2%:

;

2163

2173

2174
2175
2176
2177
2178
2179
2180
2181

:ERROR REGISTER DATA ERROR
:CLEAR BITS SET
:IN ERROR REGISTER
:READ ERROR REGISTER
*CLEAR UNWANTED BITS
: (R5)=EXPECTED CONTENTS
:OF ERROR REGISTER, 0
:WAS ERROR CLEARED
:ERROR REGISTER DATA ERROR
:CHECK FOR ITERATIONS, LOOP

;CLEAR BIT7, VERIFY BIT7 AND BIT15 WERE CLEARED

2162

2171
2172

: (R4)=ACTUAL DATA

:IN ERROR REGISTER
:EXPECT BIT15 TO BE SET ALSO
:CLEAR UNWANTED BITS
;ARE EXPECTED AND RECEIVED VALUES THE SAME ?

:ERROR REGISTER READ/WRITE TEST
:SET BIT7, VERIFY BIT7 AND BIT15 WERE SET

S}g?

2170

:LOAD R3 WITH ADDRESS
:OF ERROR REGISTER
:LOAD R2 WITH 60000
:TO CLEAR UNWANTED BITS
:ERROR REGISTER WILL
*BE SET TO BIT6
:LOAD ERROR

(R%) ,R4

BIS
BIC
cMP
BEQ
HLT
BIC

2158
2159

2164
2165
2166
2167
2168
2169

SEQ 0043

:SET BIT6, VERIFY BIT6 AND BIT1S WERE SET

S}gg

2131
2132
2133
2134
2135
2136
2137
2138
2139

08:30 PAGE 44
ERROR REGISTER READ/WRITE TESTS.

TEST 45

:tttttttttttttttttttttttt'tttttttttttt!ttttttt'tttttttttttttttttt"'.

006504
006512
006520

012737
012737
013703

000045
006574
001366

006524

012702

006530

012705

006534

010513

006536

011304

006540
006544
006546
006550
006552
006554

052705
040204
020504
001401
104004
040513

001226
001216

TST145:

MOV
MOV
MOV

#45,TSTNO
#TST46 NEXT
DQERR,R3

060000

MOV

#60000,R2

000200

MOV

#BIT7.RS

MOV

RS, (R3)

MOV
100000

1%:

BIS
BIC
CMP
BFQ
HLT
BIC

:LOAD R3 WITH ADDRESS
:OF ERROR REGISTER
:LOAD R2 WITH 60000
:TO CLEAR UNWANTED BITS
:ERROR REGISTER WILL

*BE SET TO BIT?7
:LOAD ERROR

(R%) ,R4

#BIT15,RS
R2,R4
RS R4
1%
4
R>.(R3)

:(R4)=ACTUAL DATA

:IN ERROR REGISTER
:EXPECT BIT1S TO BE SET ALSO
:CLEAR UNWANTED BITS
;ARE EXPECTED AND RECEIVED VALUES THE SAME ?
*

:ERROR REGISTER DATA ERROR
:CLEAR BITS SET
:IN ERROR REGISTER

006556

D oD o

LN SIS LS S SN TS TSN N ST, 8]

BSRSREC2LBBIRRR i

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN=-78 08:52

08:30

MOV

005005

CLR

0460204

)
D

104400

SEQ 0044

ERROR REGISTER READ/WRITE TESTS.

011304

020504
001401
104004

PAGE 45

2%:

(R3) R4

BIC

R2,R4

CMP
BEQ
HLT

RS,R4
2%

b o

SCOPE

sREAD ERROR REGISTER

:CLEAR _UNWANTED BITS
: (RS)=EXPECTED CONTENTS
;OF ERROR REGISTER, 0
;WAS ERROR CLEARED
;ERROR REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

:ERROR REGISTER READ/WRITE TEST

D cod

*SET BIT8, VERIFY BIT8 WAS SET
*CLEAR BIT8, VERIFY BIT8 WAS CLEARED

;

TEST 46

ttttt'ttttt'tt*ttttttttt'tttttttttttfitttt't""tttt.'tt'ttttttt't'tt

[NSLASLASTSTAS

2199

012737
012737
013703

000046
006660
001366

012702
012705

001226
001216

TST46:

MOV
MOV
MOV

#46,TSTNO
#TST47 NEXT
DQERR,R3

060000

MOV

#60000,R2

000400

MOV

#B1T8,RS

010513

MOV

RS,

040204
020504
001401
104004
040513

BIC
CMP
BEQ
HLT
BIC

R2.R4
RS.R4
1%
4
RS, (R3)

011304
040204
005005

MOV
BIC
CLR

(R3) .R4
R2.Ré
RS

020504
001401
104004
104400

CMP
BEQ

RS R4
2%
4

011304

MOV

1%:

HLT
SCOPE

2%:

(R3)

(R%) R4

;LOAD R3 WITH ADDRESS
;OF ERROR REGISTER
;LOAD R2 WITH 60000

:TO CLEAR UNWANTED BITS

sERROR _REGISTER WILL
;BE SET TO BIT8
*LOAD ERROR
s (R4)=ACTUAL DATA

s IN_ERROR REGISTER
;CLEAR UNWANTED BITS
JARE EXPECTED AND RECEIVED VALUES THE SAME ?

;ERROR REGISTER DATA ERROR
sCLEAR BITS SET
:IN ERROR REGISTER
sREAD ERROR REGISTER
sCLEAR UNWANTED BITS

: (RS)=EXPECTED CONTENTS
:OF ERROR REGISTER, 0
;WAS ERROR CLcARED

;ERROR REGISTER DATA ERROR
sCHECK FOR ITERATIONS, LOOP

;:ERROR REGISTER READ/WRITE TEST
:SET BIT9, VERIFY BIT9 WAS SET
“CLEAR BIT9, VERIFY BITS WAS CLEARED

;

006660
006666
006674

012737
012737
013703

006744
001366

006700

012702

006704

012705

006710

010513

000047

001226
001216

TEST 47

.'tttittttt‘fii"t!.'tfit't"ifittfitt'.'t.tt'ttt"‘t'tt.'tt.'ttt""ttt

TST47:

MOV

#47,TSTNO

MOV
MOV

#T5750 NEXT
DQERR,R3

060000

MOV

#60000,R2

(01000

MOV

#B1T9,RS

;ERROR REGISTER WILL

MOV

RS, (R3)

;LOAD ERROR

;LOAD R3 WITH ADDRESS
;OF ERROR REGISTER

;LOAD R2 WITH 60000
;TO CLEAR UNWANTED BITS

;BE SET TO BIT9

CZDQA
MACY11_30A(1052)
19-JuL=-78
CZDQAD.P11
27=JUN-78 08:52

006712

08:30
PAGE 46
ERROR REGISTER READ/WRITE TESTS.

011304

1%:

2%:

SEQ 0045

MOV

(R3) R4

BIC

ggz

R2.R4

qg.n4

*IN ERROR REGISTER
:CLEAR UNWANTED BITS
:ARE EXPECTED AND RECEIVED VALUES THE SAME ?

HLT
BIC

4
RS, (R3)

;ERROR REGISTER DATA ERROR
:CLEAR BITS SET

MOV
BIC
(LR

(R3) R4
R2,R&
RS

+(RS)=EXPECTED CONTENTS

ggg

g;.na

*OF ERROR REGISTER, 0
:WAS ERROR CLEARED

HLT

;ERROR REGISTER DATA ERROR

SCOPE

: (R6)=ACTUAL DATA

*IN ERROR REGISTER
*READ ERROR REGISTER
*CLEAR UNWANTED BITS

*CHECK FOR ITERATIONS. LOOP

;ERROR REGISTER READ/WRITE TEST
*SET BIT10, VERIFY BIT10 WAS SET
*CLEAR BIT10, VERIFY BIT10 WAS CLEARED

TEST W

’-Qttt'ittt'ttt'ttttttttttttttttttQtQttttQtttQtttttttt't.tt.tfi'.ttttt'

012737
012737
013703

000050
007030
001366

012702
012705

001226
001216

TST50:

MOV
MOV
MOV

#50,TSTNO
#TSTST NEXT
DQERR,R3

060000

MOV

#60000,R2

*LOAD R2 WITH 60000

002000

MOV

#81T10.RS

:ERROR REGISTER WILL

010513
011304

MOV

RS,

040204
020504
001401
104004

BIC

R2.R4

“CLEAR UNWANTED BITS

HLT
BIC

4
RS, (R3)

;ERROR REGISTER DATA ERROR
*CLEAR BITS SET

MOV
BIC
CLR

(R3) ,R4
R2,R4
RS

*READ ERROR REGISTER
*CLEAR UNWANTED BITS
: (RS)=EXPECTED CONTENTS

é?g

gg,n4

‘WAS ERROR CLEARED

HLT

;ERROR REGISTER DATA ERROR

MOV

1%:

2%:

:TO CLEAR UNWANTED BITS

*BE SET TO BIT10

(R3)

*LOAD ERROR

(R3) R4

ggg

040513

:LOAD R3 WITH ADDRESS

:OF ERROR REGISTER

:(R4)=ACTUAL DATA

*IN ERROR REGISTER

?2.R4

SCOPE

:ARE EXPECTED AND RECEIVED VALUES THE SAME 2

:IN ERROR REGISTER

:OF ERROR REGISTER, 0

*CHECK FOR ITERATIONS. LOOP

:ERROR REGISTER READ/WRITE TEST
“SET BIT11,
VERIFY BIT11 WAS SET

“CLEAR BITi1, VERIFY BIT11 WAS CLEARED
TEST 51

2293

007030

012737

000051

001226

sl
i il

AL A

TSTS1:

MoV

#51,TSTNO

223233223222223222223223:

19-JuL=-78
CZDQA
MACY11 30A(1052)
CZDQAD.P11
27=JUN-78 08:52

007036
007044

012737
013703

007114
001366

007050

012702

007054

012705

007060
007062

010513
011304

007064
007066

08:30

001216

PAGE 47

SEQ 0046

ERROR REGISTER READ/WRITE TESTS.
MOV
MOV

#TSTS52 NEXT

060000

MOV

#60000,R2

004000

MOV

#BIT11,RS

;LOAD R2 WITH 60000
;TO CLEAR UNWANTED BITS
;ERROR REGISTER WILL

MOV
MOV

RS, (R3)

;LOAD ERROR

BIC
CMP
BEQ
HLT
BIC

R2.R4
RS R4

MOV

BIC
CLR
CMP

BEQ
HLT

SCOPE

DQERR,R3

(R$) ,R4

RS, (R3)
(R3) ,R4
R2.R4
RS

R5.R%
2%

;LOAD R3 WITH ADDRESS

;OF ERROR REGISTER

BE SET TO BIT1

; (R4)=ACTUAL DATA
:IN_ERROR REGISTER
;CLEAR UNWANTED BITS
JARE EXPECTED AND RECEIVED VALUES THE SAME ?
;ERROR REGISTER DATA ERROR
;CLEAR BITS SET
;IN ERROR REGISTER
sREAD ERROR REGISTER
;CLEAR _UNWANTED BITS
: (R5)=EXPECTED CONTENTS

:OF ERROR REGISTER, 0
;WAS ERROR CLEARED

;ERROR REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

08:30 PAGE 48
SECONDARY REGISTER ADDRESSING TESTS

SEQ 0047

:IF CHARACTER DETECT AND BCC OPTIONS ARE OR ARE NOT
s INSTALLED, TEST 52 WILL BE EXECUTED

PRGOS RRRRRRRRR

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

s SECONDARY REGISTER ADDRESSING TEST

AT NN

TEST W

;t.Qtttttttttttt'tt.ttttttt"QQQ"&"'QQ'QQ'Q&.Q'.'ttt'tttttt'ittti.'

000052
007240
007202
0000 10
020016

001226
001216

TsT52:

001220

MOV
MOV
MOV
MOV
MOV

CLR

1$:

*FIRST SECONDARY REGISTER=0

MOVB
MOV
INC
DEC

R3,aDAREG
R5.aDQSEC
R3
RO

*SELECTED SECONDARY REGISTER
:LOAD SECONDARY REGISTER
:ADDRESS OF NEXT SECONDARY REGISTER
“CONTINUE IF NOT DONE

MOV

#DATAB,R1

:GET POINTER TO ADDRESSS TEST DATA

aDQSEC ,Ré4

*READ SECONDARY REGISTER

BNE
MOV

CLR
MOVB

2%:

MOV

000002

*GET DATA TO BE LOADE

1%
#10,R0

R3
R3,aDQREG

*FIRST SECONDARY REGISTER TO BE CHECKED
*SELECT SECONDARY REGISTER

(R1) RS

:GET TEST DATA

RS R4
3$

SCOP1
INC

:CHECK FOR LOOP ON CURENT ADDRESS
*UPDATE ADDRESS

*CONTINUE IF NOT DONE

ADD

gfig
4%:

(R1)+,RS

CMP
BEQ
HLT

3$:

:GET POINTER TO ADDRESS TEST DATA

MOV

2335

#52,TSTNO
#OPT1, NEXT
#2%,L0CK
#10.R0
#DATAB,R1

“CHECK DATA

: SECONDARY REGISTER ADDRESSING ERROR

#2.R1

:UPDATE REGISTER DATA POINTER

SCOPE

;CHECK FOR ITERATIONS, LOOP

:IF CHARACTER DETECT OPTION IS INSTALLED.

:TEST 53 WILL BE EXECUTED

832737

020000

001510

012737
000177

007554

001214

1005

171732

oPT1:

BIT
BNE

MOV
JMP

#8881T,DQSTAT
.+14

#0PT2X ,RE TURN
aRE TURN

:SECONDARY REGISTER ADDRESSING TEST
TEST 53
-2

3838

—_

IASLAS [\
Ny —N
oo

000053
007406
007350

TST53:

elelelele]

(=]

007262
007270
OO;276
007304
007310
007314
007316

mjinugsunvnu
8

.'Q.tt"t.t"'tt.'fiut"i"""'t.fl I A

020016
1%:

MoV

#53,TSTNO

MOV
MOV

#2%,L0CK
#13. R0

MOV

SRR 222222220223 23323323223223332232322]

#EOPTT NEXT

MOV

#DATAB,R1

:GET POINTER TO ADDRESS TEST DATA

MOV

(R1)+,RS

*GET DATA TO BE

CLR

:FIRST SECONDARY REGISTER=0
LOADE

CZDQA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:

08:30 PAGE 49
SECONDARY REGISTER ADDRESSING TESTS
MOVB
MOV

2%:

R3,aDQREG
RS.aDQSEC
R3
RO

sSELECTED SECONDARY REGISTER
sLOAD SECONDARY REGISTER
sADDRESS OF NEXT SECONDARY REGISTER
;CONTINUE IF NOT DONE

1%
#13. RO
#DATAB,R1
R3
R3,aDAREG
aDASEC R4

MOVB

;GET POINTER TO ADDRESSS TEST DATA
;FIRST SECONDARY REGISTER TO BE CHECKED
sSELECT _SECONDARY REGISTER
sREAD SECONDARY REGISTER
;GET TEST DATA
s CHECK DATA

(R1) .RS

RS RS

SCOP1

3%:

; SECONDARY REGISTER ADDRESSING ERROR
sCHECK FOR LOOP ON CURENT ADDRESS
sUPDATE ADDRESS
;UPDATE REGISTER DATA POINTER
sCONTINUE IF NOT DONE

#2,R1

002000

001510

007554

001214

171564

EOPTT:

SCOPE

SEQ 0048

#A?BIT.DQSTAT

sCHECK FOR ITERATIONS, LOOP

#OPT2X,RE TURN
@RE TURN

;IF

CHARACTER DETECT AND BCC OPTIONS ARE

:EXECUTE TEST 54

INSTALLED,

; SECONDARY REGISTER ADDRESSING TEST
TEST 54

OOOO0O

37
37
701

110377

000054
007554
007516
000020

001226
001216
1220
-

020016

17 1676

1%:

171674

000020
020016
171646
171644

TSTS4

2%:

AR A A A A AR R

MOV
MOV
MOV
Y
MOV

CLR
MOV
MOVR
MOV
INC
DEC
BNE
MOV
MOV
CLR

MOVB
MOV
MOV
CMP

BEQ

3%:

HLT

SCOP1

R AR

A A

R AR AR AR A AR AR AR R AR AR AR AR AR

AR AR AR AR AR

#54 ,TSTNO
#TSTS5 NEXT
#2%,L0CK
#DATAB ,R1

;GET POINTER TO ADDRESS TEST DATA
;FIRST SECONDARY REGISTER=0
:GET DATA TO BE LOADE
sSELECTED SECONDARY REGISTER
;LOAD SECONDARY REGISTER
;ADDRESS OF NEXT SECONDARY REGISTER
;CONTINUE IF NOT DONE

;FIRST SECONDARY REGISTER TO BE

R3
(R1)+,R5
R3,aDQREG
gS.SDOSEC

R3.,aDQREG
aDASEC R4

(R1) RS

RS R4
38’
<

;GET POINTER TO ADDRESSS TEST DATA

sSELECT SECONDARY REGISTER
sREAD SECONDARY REGISTER
;GET TEST DATA
. CHECK DATA

CHECKED

: SECONDARY REGISTER ADDRESSING ERROR
;CHECK FOR LOOP ON CURENT ADDRESS

19-JuL-78
CZDQA
MACYT1_30A(1052)
CZDQAD.Pi1
27=-JUN-78 08:52

2630
2631
2432
2433
%2%2

007540
007542
007546
007550
007552

005203
062701
005300
001362
104400

08:30
PAGE 50
SECONDARY REGISTER ADDRESSING TESTS

000002

INC

BNE

ADD
DEC

4%:

SCOPE

#2.R1
RO

SEQ 0049

;UPDATE ADDRESS
sUPDATE REGISTER DATA POINTER
;CONTINUE IF NOT DONE
;CHECK FOR ITERATIONS, LOOP

CZDQA
MACY11 _30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN=78 08:52

007554

SEQ 0050

OPT2X:

;SECONDARY REGISTER READ/WRITE TEST
sSET BITO IN SYNC REGISTER
JVERIFY THAT BITO WAS SET

;CLEAR BITO

JVERIFY THAT BITO WAS CLEARED

;

TEST 55

'Q"".Q..Qt'*'.."*"""*'l’*iifi"Qfi.Qfi'..".'..."'"Q".'.'Q*.."Q'

001
001

000055
007644
000011

TST55:

171570

1544
1540

171556

1%:

#11,R3

QDD?ESS OF SECONDARY REGISTER

MOvB
MOV

R3,aDOREG
#MITO,RS

JSELECT SYNC REGISTER
;(RS)=BITO

MOV

aDASEC R4

;SYNC REGISTER
;s (RG)=ACTUAL DATA IN

CMP

RS.R%

RS5,aDQSEC

BEQ
HLT
BIC
MOV

1%
6
RS,aDQSEC
aDQSEC R4

CMP
BEQ

RS.R4
2%

CLR

HLT

2%:

#55,TSTNO

lTST56.NEXT

MOV

171562

MOV

000001

SCOPE

: SET BITO IN

;SYNC REGISTER
ARE EXPECTED AND RECEIVED DATA THE SAME ?

BR IF GOOD
;SECONDARY REGISTER DATA ERROR
;CLEAR BITO
:READ SYNC REGISTER

JEXPECT SYNC REGISTER
;TO CONTAIN O
ARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR IF GOOD

- SECONDARY REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

;SECONDARY REGISTER READ/WRITE TEST
JSET BIT1 IN SYNC REGISTER
JVERIFY THAT BIT1 WAS SET
sCLEAR BIT1
JVERIFY THAT S8IT1 WAS CLEARED
;

TEST 56

(e e 8

nOrY

000056
007734
000011

.'.."'..'..Q.*""‘."."""'......'"Q.Q...".'..'."'.fi.t."'.'.'.

TSTS6:

#56,TSTNO
#TSTS7 .NEXT
#11,R3

gDD?ESS OF SECONDARY REGISTER

000002
171472

MOVB
MOV
MOV

R3,aDQREG
#BIT1,RS
RS,aDQSEC

JSELECT SYNC REGISTER
;(RS)=BIT1
SET BIT1 IN

171466

MOV

aDGSEC,R4

CMP
BEQ

RS R4
i 3

MOV
MOV
MOV

171500

2436
2437
2438
2439
2440
2441
2442
2443
2644
2445
2446

08:30 PAGE 51
SYNC REGISTER READ/WRITE TESTS.

1454
1450

1%:

HLT

BIC

MOV
(LR

:SYNC REGISTER

;(R4)=ACTUAL DATA IN

JSYNC REGISTER
*ARE EXPECTED AND RECEIVED DATA THE SAME 2
*BR IF GOOD

SECONDARY REGISTER DATA ERROR

RS ,aDQSEC

;CLEAR BIT

JEXPECT SYNC REGISTER

acSEC R4

*READ SYNC REGISTER

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

M4
08:30 PAGE 52
SYNC REGISTER READ/WRITE TESTS.

020504
001401

CMP
BEQ

104006
104400

HLT

2%:

SCOPE

SEQ 0051
:TO _CONTAIN O
ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
: SECONDARY REGISTER DATA ERRCR
sCHECK FOR ITERATIONS, LOOP

RS R4
2%

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT2 IN SYNC REGISTER
;VERIFY THAT BIT2 WAS SET
;CLEAR BIT?
JVERIFY THAT BIT2 WAS CLEARED
;

000057
010024
000011

001226
001216

TEST 57

AR AR AR AR A AR AR AR AR AR R AR RN

TSTS57:

MOV
MOV
MOV

171410

MOVB

000004

AR AR R AR RN

#57 ,TSTNO
#TST60 NEXT

#11,R3

R3,aDQREG

AR AR

AR AR AR AR AR ARk

:egggess OF SECONDARY REGISTER
sSELECT SYNC REGISTER

171402

MOV

#MIT2 RS

: (R5)=BIT?2

171376

MOV

aDQSEC R4

CMP
BEQ

RS.R4
1%

: (R4)=ACTUAL DATA IN
sSYNC _REGISTER
:ARE EXPECTED AND RECZIVED DATA THE SAME ?
:BR IF
; SECONDARY REGISTER DATA ERROR

71364
71360

HLT

1%:

2%:

RS5,aDQSEC

BIC
MOV
CLR

R5,aDQSEC
aDQSEC R4
RS

CMP
BEQ
HLT

RS,.Ré4
2%

SCOPE

;SET BIT2 IN
sSYNC REGISTER

;CLEAR BIT2

:READ SYNC REGISTER

sEXPECT SYNC REGISTER

:TO CONTAIN O
AREIEXPECTED RECEIVED DATA THE SAME ?
:BR

s SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT3 IN SYNC REGISTER
;VERIFY THAT BIT3 WAS SET
;CLEAR BIT3
JVERIFY THAT BIT3 WAS CLEARED
;

010024
010032
010040
010044
010050
010054

010060
010064
010066

000060

010114
000011

001226

TST60:

MOV

#60,TSTNO

MOV
MOV

fiTST61.NEXT
#11,R3

171320

MOVB

R3,aDQREG

171312

MOV

RS ,aDQSEC

MOV

aDQSEC R4

CMP
BEQ

R”.R4
1%

000010

171306

001216

TEST 60

.tttt’tittttttfittfi't.ttttt"ttttfittt'ttttttifittfitt.tttt'.tt'tt'fifi"'

MOV

#BIT3,RS

gDD?ESS OF SECONDARY REGISTER

sSELECT SYNC REGISTER
;(R5)=BIT3

:SET BIT3 IN

sSYNC REGISTER

: (R4)=ACTUAL DATA IN

sSYNC REGISTER
sARE EXPECTED AND RECEIVED DATA THE SAMF 2
:BR IF GOOD

19-JuL-78 08:30 PAGE 53

MACY11_30A(1052)
CZDQA
27-JUN-78 08:52
CZDQAD.P11
104006

040577
017704
005005

SEQ 0052

SYNC REGISTER READ/WRITE TESTS.

171270

HLT

SECONDARY REGISTER DATA ERROR

MOV

aDQSEC R4

READ SYNC REGISTER

CLR

CMP

020504
001401

104006
104400

BEQ
HLT

SCOPE

2%:

CLEAR BIT3

RS,aDQSEC

BIC

1%:

171274

EXPECT SYNC REGISTER

RS .,R4

ARE EXPECTED AND RECEIVED DATA THE SAME ?

:TO CONTAIN O

2%
6

BR IF GOOD
:SECONDARY REGISTER DATA ERROR

CHECK FOR ITERATIONS, LOOP

:SECONDARY REGISTER READ/WRITE TEST
SET BIT4 IN SYNC REGISTER

VERIFY THAT BIT4 WAS SET
CLEAR BIT4
VERIFY THAT BIT4 WAS CLEARED
;

TEST 61

SRR

010134
010140
010144

010150

010154

010172
010174
010176
010200
010202

012737
012737
012703

000061

110377
012705
010577

171230
000020
171222

017704
020504
001401
104006
040577
017704
005005

001226

010204 001216

RAR AR

TST61:

000011

171216

MOV

AR AR

MOV

1%:

020504
001401

RRARRAR AR

AR AR RR

R AR AR

RACRR

#61,TSTNO

#TST62 ,NEXT

#11,R3

gDD?ESS OF SECONDARY REGISTER

MOVB
MOV
MOV

R3,aDQREG
#IT4 RS
RS.,aDQSEC

:SELECT SYNC REGISTER
:(R5)=BIT4
:SET BIT4 IN

MOV

aDQSEC,R4

; (R4)=ACTUAL DATA IN

CMP

RS .R4

HLT
BIC
MOV
CLR

6
RS.aDQSEC
aDQSEC,R4
RS

;SECONDARY REGISTER DATA ERROR
CLEAR BIT4
READ SYNC REGISTER
EXPECT SYNC REGISTER

CMP

RS5.R4

ARE EXPECTED AND RECEIVED DATA THE SAME ?

BEQ
HLT

SCOPE

2%:

MOV

BEQ

171204
171200

2%
6

;SYNC REGISTER

SYNC REGISTER

ARE EXPECTED AND RECEIVED DATA THE SAME ?
BR IF GOOD

;TO CONTAIN O

BR IF GOOD
:SECONDARY REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

:SECONDARY REGISTER READ/WRITE TEST
“SET BITS IN SYNC REGISTER
VERIFY THAT BITS WAS SET
;CLEAR BITS
VERIFY THAT BITS WAS CLEARED
;

TEST 62

.'.‘."‘."...Q.‘....'..."'.'.".'.""'........'..'.'......'.fi..'..'.

000062
010274

000011

171140

000040
171132

001226
001216

TST62:

MOV
MOV

MOV

MOVR

MOV
MOV

#6.,TSTNO
#TSTO3 NEXT

#11,R3

gDD?ESS OF SECONDARY REGISTER

R3,aDOREG

%ECT
SYNC REGISTER

‘BITS RS

iDQSEC

ET 8175 IN
:SVN( REGISTER

(1052)
19-JuL-78
MACY11
| CZDQAD.P1
2 ~JUN=
08:52

010270
010272

MOV

aDQSEC R4

cMP
BEQ

R5.R4
1%
6
R5,aDQSEC

HLT
BIC
MOV

1$:

—-

104006

040577
017704
005005

anld

020504
001401

010244

08:30 PAGE 54
SYNC REGISTER READ/WRITE TESTS.

171126

017704

-l

010240

CLR

020504
001401

104006
104400

CMP
BEQ
HLT

2%:

ggOSEC.R4

R5.R4
2%

SEQ 0053
; (R4)=ACTUAL DATA IN

sSYNC REGISTER
gf
EXPECTED AND RECEIVED DATA THE SAME ?
IF GOOD
;SECONDARY REGISTER DATA ERROR
;CLEAR BITS

:READ SYNC REGISTER

sEXPECT SYNC REGISTER
;TO CONTAIN O

:ARE EXPECTED AND RECEIVED DATA THE SAME ?

AR IF GOOD

s SECONDARY REGISTER DATA ERROR
sCHECK FOR ITERATIONS, LOOP

SCOPE

; SECONDARY REGISTER READ/WRITE TEST

;SET BIT6 IN SYNC REGISTER
;VERIFY THAT BIT6 WAS SET

;CLEAR BIT6

;VERIFY THAT BI76 WAS CLEARED

;

TEST 63

010274
010302
010310

012737
012737
012703

010314
010320
010324

012705
010577

000100
171042

010330

017704

171036

010334
010336
010340

020504
001401

010352
010354

104006

040577
017704
005005

001226
001216

TST63

171050

110377

000063
010364
000011

—_—

SRIRRRISEZCRDORRRERE

CZDQA

1024
1020

1%:

A A

A AR

MOV

104006
104400

2%:

A AR AR AR R R R AR A AR AR AR R AR AR AR AR R AR R AR R AR

AR AR AR

ARk

#63,TSTNO

MOV
MOV

#TST64

MOvB
MOV
MOV

R3,3DOREG
#BIT6,RS
RS.,aDQSEC

MoV

aDQSEC R4

CMP
BEQ
HLT
BIC
MOV

R5,Ré4
1%
6
R5,aDQSEC
R4
aDQSEC
R5

CMP
BEQ
HLT

R5.Ré

:TO CONTAIN O
sARE EXPECTED AND RECEIVED DATA THE SAME ?

*SECONDARY REGISTER DATA ERROR

CLR

020504
001401

A AR

SCOPE

;ADDRESS OF SECONDARY REGISTER
s SYNC
sSELECT SYNC REGISTER
: (R5)=BIT6

;SET BIT6 IN

:SYNC REGISTER
; (R4)=ACTUAL DATA IN
sSYNC REGISTER
sARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
; SECONDARY REGISTER DATA ERROR

;CLEAR BITé6
:READ SYNC REGISTER
SEXPECT SYNC REGISTER
BR IF GOOD

*CHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT7 IN SYNC REGISTER
;VERIFY THAT BIT7 WAS SET

;CLEAR BI 17
JVERIFY THAT BIT7 WAS CLEARED
.

TEST 64

QtttttiQtttttt'ttttt'tttt'it"ttt.'iQ.tt‘t"Q'Qtt"t"ttit.'tifi*"t'

000064
010454
000011

001226
001216

TST64

MOV

MOV
MOV

#64,TSTNO

#TST65 NEXT

#.7,R3

;ADDRESS OF SECONDARY REGISTER

s SYNC

CZDQA
MACY11
A(1052)
19-JuL-78
CZDQAD.P11
27= UN-78 08:52
110377
012705
010577

170760
000200

017704
020504
001401
104006
040577
017704
005005

08:30 PAGE 55
SYNC REGISTER READ/WRITE TESTS.

MOvB

R3,aDAREG

sSELECT SYNC REGISTER

RS, aDASEC

:SET BIT7 IN
:SYNC REGISTER
: (R6)=ACTUAL DATA IN
:SYNC REGISTER
:ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD

170752

MOV

#B1T7,RS

170746

MOV

aDQSEC R4

CMP
BEQ

R5.R4
1%

170734
170730

HLT
BIC
MOV

i$:

CLR

CMP

020504
001401

BEQ

104006
104400

HLT

’%:

SEQ 0054

: (R5)=BIT7

6
R5,aDQSEC
aDQSEC R4

: SECONDARY REGISTER DATA ERROR
;CLEAR BIT7
:READ SYNC REGISTER

SEXPECT SYNC REGISTER

;TO CONTAIN

R5.R4

: ARE EXPECTED AND RECEIVED DATA THE SAME ?

:BR IF GOOD

- SECONDARY REGISTER DATA ERROR

SCOPE

sCHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT8 IN SYNC REGISTER
;VERIFY THAT BIT8 WAS SET
;CLEAR BIT8

;VERIFY THAT BIT8 WAS CLEARED
TEST 65

170670

170662

010510

170656

OTM

010474
010500
010504

Qa4

000065
010544
000011

010454
010462
010470

010534
010536
010540
010542

AR AR

MOV
MOV
MOV

MOVB

MOV

010514

010532

TST65:

1%:

2%:

#65,TSTNO

AR A AR AR R AR AR R AR R AR AR AR R AR AR AR AR AR R

gDDgESS OF SECONDARY REGISTER

R3,aDQREG

sSELECT SYNC REGISTER

#BI1T8,RS

;(R5)=BIT8

R5,aDQSEC

:SET BIT8 IN

MOV

aDQSEC R4

; (R4)=ACTUAL DATA IN

CMP

R5.R4

HLT
BIC
MOV

6
R5,aDQSEC
aDQSEC R4

CLR

CMP
BEQ

R5.Ré
2%

HLT

#TST66 ,NEXT
#11,R3

MOV

BEQ

170644
170640

A A AR AR

SCOPE

:SYNC REGISTER
sSYNC REGISTER

:ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR
TF GOOD

: SECONDARY REGISTER DATA ERROR
;CLEAR BIT8
:READ SYNC REGISTER

JEXPECT SYNC REGISTER
:TO CONTAIN O
sARE EXPECTED AND RECEIVED DATA THE SAME ?

:BR IF GOOD

: SECONDARY REGISTER DATA ERROR

;CHECK FOR ITERATIONS, LOOP

; SECONDARY REGISTER READ/WRITE TEST

;SET BIT9 IN SYNC REGISTER
;VERIFY THAT BIT9 WAS SET
;CLEAR BIT9

;VERIFY THAT BIT9 WAS CLEARED

;

TEST 66

"t'tttt!fil""tt'l"ttttt"""'l.tttttt!!'t.t'ttfitt'tt‘ti.fi'.fit"t"t

CZDQA
MACY11
(1052)
19-JuL-78
CZDQAD.P11
2 ~JUN-78 08:52

010544
010552
010560

012737
Q12737
012703

010564
010570
010574

012705
010577

010600

017704

010604

020504
001401

110377

104006

040577
017704
005005

000066
010634
000011

08:30 PAGE 56
SYNC REGISTER READ/WRITE TESTS.

001226
001216

TST66:

SEQ 0055

MOV

#66,TSTNO

MOV

#11,R3

gDDFEESS OF SECONDARY REGISTER

001000
170572

170600

MOvVB
MOV
MOV

R3,aDOREG
#BI1T9 RS
R5.,aDQSEC

sSELECT SYNC REGISTER
: (R5)=BIT9
:SET BIT9 IN

170566

MOV

aDQSEC R4

CMP

R5,R4

: (R4)=ACTUAL DATA IN
:SYNC REGISTER
:ARE EXPECTED AND RECEIVED DATA THE SAME ?

R5,aDQSEC
aDQSEC R4

;CLEAR BIT9
:READ SYNC REGISTER

170554
170550

1$:

MOV

BEQ
HLT

1%
6

CLR

BIC
MOv

020504
001401

CMP

BEQ

104006
104400

HLT

2%:

#TST67 NEXT

:SYNC REGISTER

:BR
IF GOOD
; SECONDARY REGISTER DATA ERROR
;EXPECT SYNC REGISTER
:TO CONTAIN O

R5.R4

:ARE EXPECTED AND RECEIVED DATA THE SAME ?

:BR IF GOOD

s SECONDARY REGISTER DATA ERROR

SCOPE

sCHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT10 IN SYNC REGISTER

;VERIFY THAT BIT10 WAS SET

;CLEAR BIT10

;VERIFY THAT BIT10 WAS CLEARED
;

TEST 67

tt't'*ttt""fifitt"i'fi"'tt'fi.‘.'l'.i."".tfifit'.t'.'t.fit'tt"'fitfi"

012737
012737
012703
110377

000067
010724
000011

001226
001216

TS167:

#TST70 NEXT
#11,R3

002000
170502

170510

MOVB
MOV
MOV

R3,aDQREG
#31T10,RS
R5,aDQSEC

017704

170476

MOV

aDQSEC R4

CMP

R5.R4

HLT
BIC

6
R5,aDQSEC

CLR

CMP

R5.R4

104

010714
010716
010720
010722

#67 ,TSTNO

012705
010577

020504
001401

010712

MoV

MOV
MOV

040577
017704
005005

BEQ

170464
170460

1%:

020504
001401

104006
104400

MOV

BEQ

2%:

HLT

éDDFc?ESS OF SECONDARY REGISTER

sSELECT SYNC REGISTER
: (R5)=BIT10
:SET BIT10 IN
sSYNC REGISTER
; (R&)=ACTUAL DATA IN

sSYNC REGISTER

:ARE EXPECTED AND RECEIVED DATA THE SAME 2

:BR IF GOOD

: SECONDARY REGISTER DATA ERROR
;CLEAR BIT10

aDQSEC,R4

:READ SYNC REGISTER

JEXPECT SYNC REGISTER

:TO CONTAIN O

;ARE EXPECTED AND RECEIVED DATA THE SAME ?

:BR IF GOOD

: SECONDARY REGISTER DATA ERROR

SCOPE

:CHECK FOR ITERATIONS, LOOP

; SECONDARY REGISTER READ/WRITE TEST

;SET BIT11

IN SYNC REGISTER

JVERIFY TeAT BIT11

;CLEAR BIT11

WAS SET

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 0 8:52

SEQ 0056

;VERIFY THAT BIT11 WAS CLEARED

;

TEST 70

R R

010724
010732
010740

000070
011014
000011

001226
001216

TST70:

AR A

MoV

MOV
MOV

AR AR AR AR AR AR AR A AR AR A AR AR AR R

#11,R3

gDDgESS OF SECONDARY REGISTER

sSELECT SYNC REGISTER
;(RS)=BITN

MOV
MOV

R3,aDQREG
#8I1T11,RS
R5,aDQSEC

010760

MOV

aDQSEC
R4

CMP
BEQ
HLT

R5.Ré
1%
6
RS5,aDQSEC

MOvB

010764
010766
010770
010772
010776
011002

170374
170370

011004
011006
011010
011012

BIC

MOV
CLR
CMP
BEQ
HLT

2%:

AR R AR AR AR R RN

#70,TSTNO

#TST71 NEXT

010744
010750
010754

:SET BIT11 IN
:SYNC REGISTER

; (R4)=ACTUAL DATA IN

:SYNC REGISTER
:ARE EXPECTED AND RECEIVED DATA THE SAME

:BR IF GOOD
s SECONDARY REGISTER DATA ERROR

;CLEAR BITN

aDQSEC R4

:READ SYNC REGISTER

JEXPECT SYNC REGISTER
;TO CONTAIN O
JARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR IF GOOD
s SECONDARY REGISTER DATA ERROR

R5.Ré

SCOPE

;CHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT12 IN SYNC REGISTER
;VERIFY THAT BIT12 WAS SET
;CLFAR BIT12
;VERIFY THAT BIT12 WAS CLEARED
TEST 71
SRR AR A

011014
011022
011030

012737
012737
012703

000071
011104
000011

011034
011040
011044

012705
010577

110377

011050

017704

011054
011056
011060
011062
011066
011072

020504
001401

011074
011076
011100
011102

IST71:

A AR R

A AR AR A AR R

170330
010000
170322

MOVB
MOV
MoV

R3,aDQREG
#BIT12,RS
R5,aDQSEC

170316

MOV

aDQSEC,R4

CMP
BEQ

R5.R4
1%
6
RS ,aDQSEC
aDGSEC R4
RS

0304
0300

1%:

HLT
BIC
MOV

CLR

029504
001401

104006
104400

A AR AR

#71,TSTNO
#TST72 NEXT

104006
040577
017704
005005

001226
001216

MOV
MOV
MOV

2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826

08:30 PAGE 57
SYNC REGISTER READ/WRITE TESTS.

2%:

CMP
BFQ
HLT

SCOPE

R5.R4

A AR AR R AARRA AR AR AR

AR AR AR

AR AR

:gegfiESS OF SECONDARY REGISTER
sSELECT SYNC REGISTER
;(RS)=BIT12

;SET BIT12 IN
:SYNC REGISTER

; (R4)=ACTUAL DATA IN
sSYNC REGISTER
:ARE EXPECTED AND RECEIVED DATA THE SAME
;BR _IF GOOD
s SECONDARY REGISTER DATA ERROR

:CLEAR BIT12

:READ SYNC REGISTER

;EXPECT SYNC REGISTER

:TO _CONTAIN O
ARE EXPECTED AND RECEIVED DATA THE SAME
:BR IF GOOD
; SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

CZDQA
MACY11 30A(10S52)
19-JuL-78
CZDQAD.P11
27=JUN=78 08:52

F
5
08:30 PAGE 58
SYNC REGISTER READ/WRITE TESTS.

SEQ 0057

s SECONDARY REGISTER READ/WRITE TEST

SET BIT13 IN SYNC REGISTER
VERIFY THAT BIT13 WAS SET

:CLEAR BIT13
;VERIFY THAT BIT13 WAS CLEARED
;

TEST 72

NSEX REKEER & RER SRR

—

000072
011174
000011

_—
-

tst72:

170240

020000
170232

017704

_
_——d e
T =)

104006

020504
001401

RI
TM

mov
MOV

170226

170214
170210

1%:

104006
104400

#11,R3

ng?ESS OF SECONDARY REGISTER

MOVB
MOV

R3,aDQREG
#MIT13,RS

sSELECT SYNC REGISTER
;(R5)=BIT13

MOV

aDQSEC,R4

CMP
BEQ
HLT

RS,R4
1%

RS,aDQSEC

BIC

RS,aDQSEC

CMP
BEQ

RS.R4
P 3

MOV
CLR

HLT

2$:

#72,TSTNO
'TST73.NEXT

MOV

020504
001401

040577
017704
005005

—_—
P

001226
001216

aDQSEC R4
RS

SCOPE

SSET BIT13 IN

sSYNC REGISTER

; (R4)=ACTUAL DATA IN
;SYNC REGISTER

ARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR IF GOOD
s SECONDARY REGISTER DATA ERROR

;CLEAR BIT13

:READ SYNC REGISTER
JEXPECT SYNC REGISTER
;TO CONTAIN O
ARE EXPECTED AND RECEIVED DATA THE SAME ?
BR IF GOOD
; SECONDARY REGISTER DATA ERROR

;sCHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT14 IN SYNC REGISTER
;VERIFY THAT BIT14 WAS SET
;CLEAR BIT14
;VERIFY THAT BIT14 WAS CLEARED

110377
012705
010577

017704

000073
011264
000011

—_

012737
012737
012703

rony

S =
SO
O
=20

TEST 73
*fiQ.tt‘."'.*'."t"""'"'Q'tfi‘.Q'i.*'fi.fi“.".fi" 2222332222222

o
—

[elelele N elelelelsls]
—
D D
—_—
D
D

—_
——d e

OO0
— o b

OOoOo
—
—d D
— D

Ts173:

104006

020504

#73,TSTNO

MOV
MOV

’TST?4,NEXT
#11,R3

:GBR?ESS OF SECONDARY REGISTER

170150
040000
170142

MOVB
MOV
MOV

R3,aDQREG
#B1T14,RS
RS,aDQSEC

JSELECT SYNC REGISTER
;(R5)=BIT14
;SET BIT14 IN

170136

MOV

aDQSEC,R4

(MP

RS5,R4

020504
001401

049577
017704
005005

mMov

BEQ
HLT

BIC
MOV

CLR

(MP

1%
6

RS,aDQSEC
aDQSEC ,R4

RS,Ré

sSYNC REGISTER

2 (R4)=ACTUAL DATA IN

sSYNC REGISTER

:ARE EXPECTED AND RECEIVED DATA THE SAME 2

;BR IF GOOD
;SECONDARY REGISTER DATA ERROR

;CLEAR BIT14
:READ SYNC REGISTER

JEXPECT SYNC REGISTER

;TO CONTAIN O

JARE EXPECTED AND RECEIVED DATA THE

SAME

CZDQA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27=-JUN-78 08:52

2884
2885
5339

011256
011260
011262

001401
104006
104400

BEQ
HLT
SCOPE

2%:

2888
2889

JVERIFY THAT BIT1S WAS CLEARED

2894

2895

011264
011272
011300

012737
012737
012703

000074
011354
000011

2900
2901
2902

011304
011310
011314

110377
012705
010577

2904

011320

017704

2906
2907
2908
2909
2910
2911

011324
011326
011330
011332
011336
011342

020504
001401
104006
040577
017704
005005

2913
2914
2915

011344
011346
011350

020504
001401
104006

2916

TEST 74

.".Qt'.'t'...'t..'fi.tttt"t"QQQ"QQ’.QQ.Q'!Q...Q'..ttt't'tt."...'it

289
2897
%ggg

2912

;BR [F GOOD
s SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

JVERIFY THAT BIT15 WAS SET
;CLEAR BIT1S

2892
2893

2905

2%
6

SEQ 0058

;SECONDARY REGISTER READ/WRITE TEST
sSET BIT1S IN SYNC REGISTER

2890
2891

2903

08:30 PAGE 59
SYNC REGI TER READ/WRITE TESTS.

011352

104400

MOV
MOV
MOv

#74,TSTNO
#TST7S NEXT
#11,R3

:gly)gngSS OF SECONDARY REGISTER

170060
100000
170052

MOVB
MOV
MOV

R3,aDQREG
#MIT15,RS
RS ,aDQSEC

sSELECT SYNC REGISTER
;(RS)=BIT1S
;SET BIT1S IN

170046

MOV

aDQSEC R4

;s (R4)=ACTUAL DATA IN

CMP
BEQ
HLT
BIC
MOV
CLR

RS.R4
1%
6
RS,aDQSEC
aDQSEC R4
RS

JARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR IF GOOD
;SECONDARY REGISTER DATA ERROR
;CLEAR BIT1S
JREAD SYNC REGISTER
JEXPECT SYNC REGISTER

CMP
BEQ
HLT

RS ,R4
2%
6

sARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR IF GOOD
. SECONDARY REGISTER DATA ERROR
JCHECK FOR ITERATIONS, LOOP

170034
170030

001226
001216

T1ST74:

1%:

2%:

SCOPE

sSYNC REGISTER

;SYNC REGISTER

;TO CONTAIN O

CZDQA
MACY11 30A(1052)
19=JuL=78
CZDQAD.P1
27=JUN-78 08:52

2917
18

*SET BITO IN MISCELLANEOUS REGISTER

2920
2921

*VERIFY THAT BITO WAS SET
*CLEAR BITO

53%

;VERIFY THAT BITO WAS CLEARED

2924

29
2927

011354
011362

01137C

2931

011400

011374

012737
012737

012703

110377

000075
011444

000012

001226
001216

TEST 75

'tt.Qtt.ttttt't'ttttttt""ttttt.'tttQt"ttttttttt'.tfi.ttttt'.ttt"t

TST75:

MOV
MOV

MOV

167770

MOVR

#75,TSTNO
#1776 NEXT

#12,R3

R3,aDQREG

011404

012705

010577

000001

MOV

#BI1TO, RS

293%

011410

017704

167756

MOV

@aDQSEC,R4

293

011414

020504

CMP

RS.R4

011426

017704

2935

2937
2938
2939

011416
011420
011422

291
2942
2943
2944
2945
ggzg

011432

2940

2928
2929
2932
2933

011434
011436
011440
011442

001401
104006
040577
005005

167762

MOV

167744

1%:

167740

020504
001401
104006
104400

2971
2972

:(RS)=BITO

*SET BITO IN
*MISCELLANEOUS REGISTER

:(R4)=ACTUAL DATA IN

sMISCELLANEOUS REGISTER

JARE EXPECTED AND RECEIVED DATA THE SAME ?

1%
6
RS,aDQSEC

:BR IF GOOD
;SECONDARY REGISTER DATA ERROR
:CLEAR BITO

(LR

;EXPECT MISCELLANEOUS REGISTER
:TO CONTAIN O
“ARE EXPECTED AND RECEIVED DATA THE SAME ?
*BR IF GOOD
;SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

CMP
BEQ
HLT
SCOPE

@aDQSEC R4
RS,R4
2%
6

*READ MISCELLANEOUS REGISTER

;SECONDARY REGISTER READ/WRITE TEST
;SET BIT1 IN MISCELLANEOUS REGISTER
;VERIFY THAT BIT1 WAS SET
:CLEAR BIT1
;VERIFY THAT BIT1 WAS CLEARED
:

2955

2970

RS,aDQSEC

;ADDRESS OF SECONDARY REGISTER
sMISCELLANEOUS
sSELECT MISCELLANEOUS REGISTER

BEQ
HLT
BIC

MOV

2%:

2948
2949
2950
2951
2952
2953
2954
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969

SEQ 0059

;SECONDARY REGISTER READ/WRITE TEST

2925

08:30 PAGE 60
MISCELLANEOUS REGISTER READ/WRITE TESTS.

TEST 76

tt'ttttQttttttttttttttt'tttttttttttfittttttt'tltttfitt'titttttttt'tttt

011444
011452
011460

012737
012737
012703

000076
01153&¢
000012

011464
011470
011474

110377
012705
010577

011500

017704

011504
011506
011510
011512

020504
001401
104006
040577

011522

005005

011516

017704

MOV
MOV
MOV

#76,TSTNO
#TST77 NEXT
#12,R3

167700
000002
167672

MOVB
MOV
MoV

R3,aDQREG
#B1T1,RS
RS,aDQSEC

167666

MoV

aDQSEC,R4

167654

CMP
BEQ
HLT
BIC

RS.R4
1%
6
RS,aDQSEC

CLR

167650

001226
001216

TST76:

1$:

MOV

aDQSEC R4

;ADDRESS OF SECONDARY REGISTER
:MI SCELLANEOUS
;SELECT MISCELLANEOUS REGISTER
:(RS)=BIT1
*SET BIT1 IN
*MISCELLANEOUS REGISTER
*(R4)=ACTUAL DATA IN
;MISCELLANEOUS REGISTER
JARE EXPECTED AND RECEIVED DATA THE SAME °
;BR IF GOOD
SECONDARY REGISTER DATA ERROR
*CLEAR BIT

*READ HISCELLANEOUS REGISTER

*EXPECT MISCELLANEOUS REGISTER
:TO CONTAIN O

CZDQA

MACY11_30A(1052)

CZDQAD.P11

2973
2974
2975
276

011526
011526
011530
011532

19-JuL-78

08:30

27-JUN~78 08:52

2986

2987
2988
2989
2990
2991
2992
2993
299,
2995
299
2997
2998

020504
001401
104006
104400

;

011534

012737

011542
011550

012737
012703

011554
011560
011564

110377
012705
010577

011570

017704

011574
011576
011600

020504
001401
104006

011606
011612

017704
005005

011614
011616
011620
011622

020504
001401
104006
104400

040577

000077
011624
000012

001226

001216

RS.P4
2%
B

;ARE EXPECTED AND RECEIVED DATA THE SAME ?
BR IF GOOD
*SECONDARY REGISTER DATA ERROR
*CHECK FOR ITERATIONS, LOOP

TEST 77

t.ttt'ttl'tfi'..t"tt't.i""tttfit.'tQQt'.'.t"'.'t'..'..'Q'Q.i"""

7ST77:

MOV

#77,TSTNO

MOV
MOV

#157100,NEXT
#12,R3

167610
000010
167602

MOVB
MOV
MOV

R3,aDOREG
#3173 RS
RS,aDASEC

167576

MoV

aDQSEC, R4

P
BEQ
HLT

RS, R4
18
6

MOV
CLR

aDASEC ,Ra
RS

P
BEQ
LT

RS R4
2%

167564

18:

167560

2%:

BIC

RS,@DQSEC

SCOPE

;ADDRESS OF SECONDARY REGISTER
*MISCELLANEOUS
*SELECT MISCELLANEOUS REGISTER
*(RS)=BIT3
*SET BIT3 IN
*MISCELLANEOUS REGISTER
*(R4)=ACTUAL DATA IN
*MISCELLANEOUS REGISTER
*ARE EXPECTED AND RECEIVED DATA THE SAME 2
‘BR IF GOOD
*SECONDARY REGISTER DATA ERROR

*CLEAR BIT3

*READ MISCELLANEOUS REGISTER
*EXPECT MISCELLANEOUS REGISTER
*TO CONTAIN 0
ARE EXPECTED AND RECEIVED DATA THE SAME 2
BR IF GOOD
*SECONDARY REGISTER DATA ERROR
*CHECK FOR ITERATIONS, LOOP

: SECONDARY REGISTER READ/WRITE TEST

3009
3010
3011

*SET BIT6 IN MISCELLANEOUS REGISTER
*VERIFY THAT BIT6 WAS SET
*CLEAR BIT6

3012

*VERIFY THAT BIT6 WAS CLEARED

3014

TEST 100

3015

3019
3020
3021
3002
3023
3024
3025
3006
3027
3028

(M
BEQ
HLT
SCOPE

28:

3008

3016
3017
3018

SEQ 0060

: SECONDARY REGISTER READ/WRITE TEST
*SET BIT3 IN MISCELLANEOUS REGISTER
*VERIFY THAT BIT3 WAS SET
*CLEAR BIT3
*VERIFY THAT BIT3 WAS CLEARED

2999 011602
3000
3001
3002
3003
3004
3005
3006

MISCELLANEOUS REGISTER READ/WRITE TESTS.

2978
2979
2980
2981
2982
2983
2984
2985

PAGE 61

'"it"t'Q"tt.fi.tfi'tQi'i't'i'tflfifitfi"'.fitlt'.Qt'..t"..."'t."'.".

011624
011632
011640

012737
012737
012703

000100
011714
000012

001226
001216

011646
011650
011654

110377
012705
010577

167520
000100
167512

MOVB
MOV
MOV

R3,aDOREG
#BT6.RS
RS,aDASEC

011660

017704

167506

MOV

aDQSEC ,R4

011664
011666
011670

020504
001401
104006

P
BEQ
HLT

RS,R4
13
6

‘

TST100: MOV
MOV
MOV

#100.TSTNO
#TSTI0T,NEXT
#12.R3

;ADDRESS OF SECONDARY REGISTER
*MISCELLANEOUS
*SELECT MISCELLANEOUS REGISTER
*(RS)=BIT6
*SET BIT6 IN
MISCELLANEOUS REGISTER
*(R4)=ACTUAL DATA IN
MISCELLANEOUS REGISTER
:ARE EXPECTED AND RECEIVED DATA THE SAME 2
‘BR IF GOOD
*SECONDARY REGISTER DATA ERROR

011672
011676
011702

040577
017704
005005

011704
011706
011710
011712

020504
001401
104006
104400

08:30 PAGE 62
MISCELLANEOUS REGISTER READ/WRITE TESTS.

167474
167470

1$:

2%:

SEQ 0061

BIC
MOV
CLR

R5,aDQSEC
aDQSEC,R4
RS

;CLEAR BIT6
cREAD MISCELLANEOUS REGISTER
'EgPE&T‘T:{’S“CSLLMWS REGISTER

CMP
BEQ
HLT
SCOPE

R5.R4
2%
6

s ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR
IF GOOD
SECGDARY REGISTER DATA ERROR
:CHECK FOR ITERATIONS, LOOP

; SECONDARY REGISTER READ/WRITE TEST

;SET BIT7 IN MISCELLANEOUS REGISTER
;VERIFY THAT BIT7 WAS SET
;CLEAR BIT7

;VERIFY THAT BIT7 WAS CLEARED
TEST 101

t.'.tt'l"t't'*tfifi""'.""ifi't'i'fi‘.it.fiit'.fit.'tlt'tt'ti"'..fi"'

011714

012737

000101

001226

011730

012703

011734
011740
011744

110377
012705
010577

167430
000200
167422

MOVB
MOV
MOV

R3,aDQREG
#8177 ,RS
RS5.,aDQSEC

011750

0177046

167416

MOV

aDQSEC R4

011754
011756

020504
001401

CMP
BEQ

R5.R4
1%

;ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD

011762
011766
011772

040577
017704
005005

BIC
MOV
(LR

RS ,aDQSEC
aDQSEC RS
RS

;CLEAR BIT7
:READ MISCELLANEOUS REGISTER
'gnggrg{acsuAfiEws REGISTER

011774
011776
012000
C12002

020504
001401
104006
104400

R5.R4
2%
6

JARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR _IF GOOD
; SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

MOV

006

167404
167400

MOV

#101,TSTNO

012004

000012

001216

TST101:

012737

011722

BEEEE Stsistetetetotetats)
S ooN o SRR L BT R LR B8 BEBELLEELS
B QP P DA BE Ch B B LB BEEBEEEB8E
G Ay |

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

1%:

2%:

HLT

CMP
BEQ
HLT
SCOPE

#TST102 ,NEXT
#12,R3

sADDRESS OF SECONDARY REGISTER

sMISCELLANEOUS
sSELECT MISCELLANEOUS REGISTER
:(R5)=BIT7
;SET BIT7 IN
sMISCELLANEOUS REGISTER
; (R4)=ACTUAL DATA IN
sMISCELLANEOUS REGISTER

; SECONDARY REGISTER DATA ERROR

; SECONDARY REGISTER READ/WRITE TEST

;SET BIT8 IN MISCELLANEOUS REGISTER
;VERIFY THAT BIT8 WAS SET
*CLEAR BIT8
:VERIFY THAT BIT8 WAS CLEARED
:

TEST 102

t'tttttt'tttttttttttttttttttttttt!tttQtttttttt'ttttittt'ttt'tttttttt

012004

012012

012020

012024

012030

012737

012737
012703

119377

000102

012074

000012

167340

001226

001216

TST102: MOV

MOV
MOV

MOVB

#102, TSTNO

#T5T103,NEXT

#12.R3

R3,aDOREG

012034

012705

010577

000400

MOV

#I1T8.RS

012040

017704

167326

MOV

@DQSE

167332

MOV

RS, aDASEC
R4

;ADDRESS OF SECONDARY REGISTER
*MISCELLANEOUS
:SELECT MISCELLANEOUS REGISTER

*(RS)=BIT8

“SET BIT8 IN
*MISCELLANEOUS REGISTER
*(R&)=ACTUAL DATA IN

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

3085

08: 30

040577
017704
005005

cMP
BEQ

167314
167310

HLT
BIC
MOV

1$:

CLR

020504
001401
012072

cMP
BEQ

104006
104400

SEQ 0062

MISCELLANEOUS REGISTER READ/WRITE TESTS.

020504
001401

104006

PAGE 63

HLT

2%:

SCOPE

sMISCELLANEOUS REGISTER
sARE EXPECTED AND RECEIVED DATA THE SAME ?

R5.R4
1%

;BR IF GOOD

6
RS ,aDQSEC
aDQSEC,R4

s SECONDARY REGISTER DATA ERROR
;CLEAR BITS8
sREAD MISCELLANEOUS REGISTER

JEXPECT MISCELLANEOUS REGISTER

:TO _CONTAIN O

R5.R4
2%

sARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD

:SECONDARY REGISTER DATA ERROR

;CHECK FOR ITERATIONS, LOOP

;SECONDARY REGISTER READ/WRITE TEST

sSET BIT9 IN MISCELLANEOUS REGISTER
sVERIFY THAT BIT9 WAS SET
;CLEAR BIT9
;VERIFY THAT BIT9 WAS CLEARED
;s

TEST 103

AR R AR

A A AR A A AR AR A AR AR A AR AR R AR AR

000103
012164
000012

012114
012120
012124

110377

012705
010577

167250
001000
167242

MOvVB
MOV
MOV

#81T9,R5
R5,aDQSEC

R3,aDQREG

sMISCELLANEOUS
sSELECT MISCELLANEOUS REGISTER

017704

167236

MOV

aDQSEC R4

: (R4)=ACTUAL DATA IN

CMP
BEQ

R5.Ré
1%

sARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD

001226
001216

TST103: MoV

MOV
MOV

—

)

OO0O

020504
001401

b
ok =

W) =

<><fig~vgfln&dvuv-AELOOD~q AN

AR A AR

012737
012737
012703

OO0O0O0

o»ooowo«vmwm—nosg
)

D ch
b

e e

i
D
b
D
)

b b

) —d

D -l

b acd ad

NN nornororRONON L e

B WWWINWWIWWIWWN

N NN N

il
— vl

NN AN N N

012074
012102
012110

N NN NN WNINWWWNWW WWWWWWWWWWWWW

AR R A

104006

040577
017704
005005

167224
167220

1$:

104006
104400

2%:

#TST104 NEXT
#12 ,R3

sADDRESS OF SECONDARY REGISTER

: (R5)=BIT9
;SET BIT9 IN

sMISCELLANEOUS REGISTER

HLT
BIC
MOV

6
RS ,aDQSEC
aDQSEC R4

; SECONDARY REGISTER DATA ERROR
;CLEAR BIT9
sREAD MISCELLANEOUS REGISTER

CMP
BEQ
HLT
SCOPE

R5.R4
2%
6

sARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR IF GOOD
; SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

CLR

020504
001401

#103, TSTNO

SEXPECT MISCELLANEOUS REGISTER

:TO CONTAIN O

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT10 IN MISCELLANEOUS REGISTER
sVERIFY THAT BIT10 WAS SET

;CLEAR BIT10
;VERIFY THAT BIT10 WAS CLEARED

;

TEST 104

:tttttttttttttittt.tfitit"t't't't'ttttt'tfiltttt't.ttit"tt't.'ttti'lt

012164
012172
012200
012204

012737
012737
012703
110377

000104

001226
001216

TST104: MOV

MOV

#104,

TSTNO

#TST105 ,NEXT

MOV

#12.R3

;ADDRESS OF

SECONDARY REGISTER

MOVB

R3,aDOREG

*SELECT MISCELLANEOUS REGISTER

*MISCELLANEOUS

3141
3142
3143
3144

012210
012214

012705
010577

002000
167152

MOV
MOV

#BIT10,RS
R5,aDQSEC

012220

017704

167146

MOV

aDQSEC R4

012224
012226
012230
012232
012236
012242

020504
1401
104006
040577
017704
005005

cMP
BEQ
HLT
BIC
MOV
(LR

R5.R4
1%
6
R5,aDQSEC
aDQSEC R4
R5

012244
012246
012250
012252

020504
001401
104006
104400

CMP
BEQ
HLT
SCOPE

R5.R4
2%
6

o
v
3
RV Mo A AP
A

69
3170

KRRV
28 BBIRRRII2E

167134
167130

1%:

2%:

;(R5)=BIT10
;SET BIT10_IN
sMISCELLANEOUS REGISTER
s (R4)=ACTUAL DATA IN
sMISCELLANEOUS REGISTER
sARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
s SECONDARY REGISTER DATA ERROR
;CLEAR BIT10
:READ MISCELLANEOUS REGISTER
'géPESLTR{SCSLLANEOUS REGISTER
sARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
; SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

IVERIFY THAT BIT11 WAS CLEARED

TEST 105

.'tt'tttfi'*'t.t't*"itttt't'.'ttttttt'ttttt.'t'!t.'t'ttifi""fiQQ*.OQ"

012254
012262
012270

012737
012737
012703

000105
012344
000012

00122¢
001216

012274
012300
012304

110377
012705
010577

167070
004000
16706¢

MOVAR
MOV
MOV

R3,aDQREG
#81T11,RS
R5,aDQSEC

012310

017704

167056

MOV

aDQSEC R4

012314
012316
012320
012322
012326
012332

020504
001401
104006
040577
017704
005005

TST105: MOV
MOV
MOV

CMP
BEQ
HLT
BIC
MOV
(LR

R5.R4
1%
6
RS ,aDQSEC
aDQSEC R4
RS

012334
012336
012340
012342

020504
001401
104006
104400

CMP
BEQ
HLT
SCOPE

RS.R4
2%
6

‘
167044
167040

1%:

2%:

#105,TSTNO
HTST106,NEXT
#12,R3

sADDRESS OF SECONDARY REGISTER
sMISCELLANEOUS
sSELECT MISCELLANEOUS REGISTER

;(R5)=BITN
;SET BIT11_IN
sMISCELLANEOUS REGISTER
: (R4)=ACTUAL DATA IN
sMISCELLANEOUS REGISTER
JARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
: SECONDARY REGISTER DATA ERROR
;CLEAR BIT11
:READ MISCELLANEOUS REGISTER
:;gPEgLT2{£C8LLANEOUS REGISTER
;ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
s SECONDARY REGISTER DATA ERROR
sCHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

JSET BIT15 IN MISCELLANECUS REGISTER
;VERIFY THAT BIT15 WAS SET
;CLEAR BIT1S
sVERIFY THAT BIT15 WAS CLEARED
TEST 106

d e
—

SEQ 0063

:SECONDARY REGISTER READ/WRITE TEST
:SET BIT11 IN MISCELLANEOUS REGISTER
VERIFY THAT BIT11 WAS SET
:CLEAR BIT11

d e

W N NN N NN N AN

b =

N NN N NN

3171
3172
3173
3174
3175
3176
3177
3178
3179

08:30 PAGE 64
MISCELLANEOUS REGISTER READ/WRITE TESTS.

) DN
et i ST T N

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P1
27=JUN-78
08:52

AR AL e

012344

012737

000106

001226

TST106: MOV

#106,TSTNO

S 222222222222
22222222

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN=78 08:52

& SORSIss 8

3197
3198

OIS WN=O

012737
012703

012434
000012

110377
012705
010577

167000
100000
166772

MOvB
MOV
MOV

#31T15,RS

017704

166766

MOV

aDQSEC R4

cMP
BEQ

R5.R4

001216

MOV
MOV

020504
001401

3207

KKK

m S5
08:30 PAGE 65
MISCELLANEOUS REGISTER READ/WRITE TESTS.

104006

040577
017704
005005

166754
166750

1%:

020504
001401
012432

104006
104400

2%:

#CHKABT NEXT

#12,R3

R3,aDOREG

RS, aDQSEC

HLT
BIC
MOV
CLR

6
RS5,aDQSEC

(MP
BEQ
HLT
SCOPE

RS.R4

ggQSEC.RL

SEQ 0064

;ADDRESS OF SECONDARY REGISTER
:MISCELLANEOUS
sSELECT MISCELLANEOUS REGISTER

:
(R5)=BIT15
:SET BIT15 IN

:MISCELLANEOUS REGISTER
: (R)=ACTUAL DATA IN
sMISCELLANEOUS REGISTER
sARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
- SECONDARY REGISTER DATA ERROR

:CLEAR BIT15
:READ MISCELLANEOUS REGISTER
JEXPECT MISCELLANEOUS REGISTER

:TO CONTAIN O

:ARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR IF GOOD
; SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

CZDQA

MACY11

I CZDQAD.P11

30A(1052)

27-JUN-78

19-JuL-78

08:52

08:30

3217

:IF BCC OPTION IS INSTALLED

:TESTS 107 THRU 126 WILL BE EXECUTED

012434
012442
012444

032737
001002
000137

002000

001510

014250

CHKAB1: BIT
BNE
JNP

#ABBIT ,DQSTAT
TST107
.EOP

3200

; SECONDARY REGISTER READ/WRITE TEST

3226
3227

*VERIFY THAT BITO WAS SET
:CLEAR BITO

:SET BITO IN BCC POLYNOMIAL REGISTER

gggg

*VERIFY THAT BITO WAS CLEARED

3230
3231

3232
3233
3234

3235
3236

SEQ 0065

POLYNOMIAL REGISTER READ/WRITE TESTS.

gs}g

3220
3221
gggg

PAGE 66

3237

012450
012456
012464

012470

012474

012737
012737
012703

110377

012705

3238 012500 010577
3239

3240
3241
3242
3243

3244

3245
3246
3247

3248
3249
3250
3251
gggg

012504

017704

012510
012512

020504
001401

012516
012522
012526

040577
017704
005005

012530
012532
01253&
012536

020504
001401
104006
104400

012514

104006

000107
012540
:

000017

001226
001216

TST107: MOV
MOV

#17 ,R3

166674

MOVB

R3,aDOREG

166666

MOV

RS,aDASEC

000001

MOV

166662

166650
166644

1%:

2%:

3260

3261

3064
3065
266
3267
3268
2269
3270
3271
3272

#BI1TO,RS

MOV

aDQSEC,R4

CMP
BEQ

RS.R&
1%

HLT

cMP
BEQ
HLT
SCOPE

RS.R4
28
4

BIC
MOV
CLR

;ADDRESS OF SECONDARY REGISTER

*BCC POLYNOMIAL
“SELECT BCC POLYNOMIAL REGISTER

*(RS)=BITO

*SET BITO IN

*BCC POLYNOMIAL REGISTER

:(R4)=ACTUAL DATA IN
:BCC POLYNOMIAL REGISTER
:ARE EXPECTED AND RECEIVED DATA THE SAME ?
*BR IF GOOD

*SECONDARY REGISTER DATA ERROR

RS,aDQSEC
aDQSEC R4
RS

*CLEAR BITO
*READ BCC POLYNOMIAL REGISTER
*EXPECT BCC POLYNOMIAL REGISTER

*TO CONTAIN
0

:ARE EXPECTED AND RECEIVED DATA THE SAME ?
*BR IF GOOD
:SECONDARY REGISTER DATA ERROR
:CHECK FOR ITERATIONS, LOOP

;SECONDARY REGISTER READ/WRITE TEST
:SET BIT1 IN BCC POLYNOMIAL REGISTER
*VERIFY THAT BIT1 WAS SET
:CLEAR BIT1

%523
62

#107,TSTNO
#TST110,NEXT

MOV

3254
3255
3256
3257

3263

TEST 107

tttttttttttttttttttttttttttttttttttttiittttttttttttttt*ttt'ttttttttt

:VERIFY THAT BIT1 WAS CLEARED

TEST 110

tttttttttttttttttttttttttt!ttttttttttttQttttt!Qtttttttitttttttttt.ti

012540

012737

000110

012546

012737

012630

012560
012564
012570

110377
012705
010577

012574

017704

012600

020504

012554

012703

000017

001226

001216

TST110: MOV

MOV

#110,TSTNO

#TST117,NEXT

MOV

#17.R3

166604
000002
166576

MOVB
MOV
MOV

R3,aDOREG
#BIT1,RS
RS, aDASEC

166572

MOV

aDQSEC R4

(MP

RS,Ré

;ADDRESS OF SECONDARY REGISTER
*BCC POLYNOMIAL

“SELECT acc POLYNOMIAL REGISTER
S (RS)=BIT1
“SET BIT1 IN
*BCC POLYNOMIAL REGISTER
*(R4)=ACTUAL DATA IN
:BCC POLYNOMIAL REGISTER
JARE EXPECTED AND RECEIVED DATA THE SAME ?

CZDQA
MACYN
(1052)
19=JuL=78
CZDQAD.P11
27-JUN-78
08:52

73 01
74
75
;9 o 521
44 012616

001401

012620

020504

012626

104006

ggg

104

040577
017704
005005

B 6
08:30 PAGE 67
POLYNOMIAL REGISTER READ/WRITE TESTS.

BEQ

166560
166554

HLT

1%:

BIC
MOV
CLR
4, o

0126%2 001401

012626

BEQ

104400

HLT

28:

SCOPE

SEQ 0066

:BR IF GOOD

RS,aDQSEC
@DASEC R4
RS

*CLEAR BIT1
*READ BCC POLYNOMIAL REGISTER
;fig‘%z gumunm REGISTER

RS.R4

28
‘

* SECONDARY nscxsrsa DATA ERROR

*ARE EXPECTED AND RECEIVED DATA THE SAME ?

*BR IF GOOD

*SECONDARY REGISTER DATA ERROR

“CHECK FOR ITERATIONS, LOOP

3284

:SECONDARY REGISTER READ/WRITE TEST

3288

:VERIFY THAT BIT2 WAS CLEARED

gao
3087

SVERIFY
THAT BIT2 WAS SET
*CLEAR BIT2

:SET BIT2 IN BCC POLYNOMIAL REGISTER

3289

3290

3291

3292

012630

012737

000111

3293
3294

012636
012644

012737
012703

012720
000017

3296

012650

110377

166514

3295

3297
3298

TESY 1%

tQttQ..t"'tt.t.t't"tt't"t't.t0'QtttttttQt'ttttt.t.t'tQt'ttt'."'t

001226

001216

TSH‘H MOV

#111,TSTNO

MOV
MOV

#TST112 NEXT
#17.R3

MOVB

R3,aDOREG

012656
012660

012705
010577

000004
166506

MOV
MOV

#BI1T2,RS
RS,aDASEC

3300

012664

017704

166502

MOV

aDQSEC R4

3302

012670

020504

cTMMP

RS.R4

HLT
BIC
MOV

;.
RS,aDQSEC
aDASEC, R4

CMP

RS,R4

3299

3301

3303

3304
3305
3306

3307

3308

3309

3310
3311
ggg

012672

001401

012674
012676
012702

104006
040577
017704

012710

020504

012706

012712
012714
012716

005005

BEQ

166470
166464

1$:

CLR

001401
104006
104400

BEQ
HLT
SCOPE

2%:

3314,

;

012720
012726

012737
012737

3324

012734

012703

336

012740

110377

3305

3327
3328

*SELECT BCC POLYNOMIAL REGISTER

*(RS)=BIT2
SSET BIT2 IN

*BCC POLYNOMIAL REGISTER
*(R4)=ACTUAL DATA IN

*BCC POLYNOMIAL REGISTER

:ARE EXPECTED AND RECEIVED DATA THE SAME ?

*BR IF GOOD

“EXPECT BCC POLYNOMIAL REGISTER

2%
6

*SECONDARY REGISTER DATA ERROR
*CLEAR BIT2
*READ BCC POLYNOMIAL REGISTER

*TO CONTAIN 0

*ARE EXPECTED AND RECEIVED DATA THE SAME ?

:BR IF GOOD
s SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

;SET BIT3 IN BCC POLYNOMIAL REGISTER
SVERIFY THAT BIT3 WAS SET
;CLEAR BIT3
JVERIFY THAT BIT3 WAS CLEARED

3320

3322
3323

;BCC POLYNOMIAL

; SECONDARY REGISTER READ/WRITE TEST

2315
3316
3317
g}g
3321

;ADDRESS OF SECONDARY REGISTER

012744
012750

012705
010577

000112
013010

000017
166424

000010
166416

001226
001216

TEST 112

t'tttt!ttfitttfitttaltt'ttt'tttttfit'ttttttt'ttttttttttttt'tttttttttti'

TsT112:

nov

#112,TSTNO
#1ST113, NEXT

MOVB

R3,aDQREG

MOV
MOV
MOV

#17 ,R3

#27T3,RS
RS .aDASEC

;ADDRESS OF SECONDARY REGISTER

*BCC POLYNOMIAL

*SELECT BCC POLYNOMIAL REGISTER

*(RS)=BIT3
“SET BIT3 IN

—

CZDQA
MACYN
(1052)
19=JuL=78
CZDQAD.P11
27=JUN~78
08:52

012754

017704

012764

012776

005005

339 013000
340 013002

020504
001401

g‘a

104400

335
g}e

3338
3341

012766
012772

013006

104006

040577
017704

166412

166400
166374

1$:

104006

2%:

3350

3352

3353
3354

3355

3356

3357
3358

aDQSEC R4

cTMMP
BEQ

RS.R4
1%

HLT

:(RG)=ACTUAL DATA IN

:BCC POLYNOMIAL REGISTER

:ARE EXPECTED AND RECEIVED DATA THE SAME ?
*BR IF GOOD

:SECONDARY REGISTER DATA ERROR

<EXPECT BCC POLYNOMIAL REGISTER

RS.R4
2%

*ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD

RS,aDQSEC
aDQSEC R4

(MP
BEQ
SCOPE

:BCC POLYNOMIAL REGISTER

BI~
MOV

HLT

SEQ 0067

‘

:CLEAR BIT3
*READ BCC POLYNOMIAL REGISTER

*TO CONTAIN O

:SECONDARY REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

;SECONDARY REGISTER READ/WRITE TEST
:SET BIT4 IN BCC POLYNOMIAL REGISTER
SVERIFY THAT BIT4 WAS SET
*CLEAR BIT4

%fig

MOV

CLR

3344
3345
3346
3347
3351

—

08:30 PAGE 68
POLYNOMIAL REGISTER READ/WRITE TESTS.

3% 012760 020504
33 012762 001401

g %4

—

013010

013016
01302¢

013030

012737

012737
012703

1°0377

000113

013100

000017

001226

001216

:VERIFY THAT BIT4 WAS CLEARED

TEST 113

'ttt'Qitttttttttttttt'tttt"tt.wt'QQtQttttttttttttttttttttttttttt"t

TSr113: Mov

MOV

166334

MOVB

#113,TSTNO

#TST114 ,NEXT
#17.R3

R3,aDQREG

;ADDRESS OF SECONDARY REGISTER

*BCC POLYNOMIAL

“SELECT BCC POLYNOMIAL REGISTER

013034
013040

012705
010577

000020
166326

MOV
MOV

#BI1T4 RS
RS,aDASEC

3360

013044

017704

166322

MOV

aDQSEC R4

:(R4)=ACTUAL DATA IN

3362

013050

020504

CMP

RS, R4

:ARE EXPECTED AND RECEIVED DATA THE SAME ?

013056
013062

040577
017704

3359

3361

3363
3364

013052
013054

3367

013066

3365
3366

3368

001401
104006
005005

3369

013070

020504

g;%

013076

104400

3370
3371

013072
013074

166310
166304

1$:

2%:

3380

3384

CLR

BIC
MOV
BEQ
HLT

SCOPE

RS.,aDQSEC
aDQSEC,R4

RS,R4
2%
6

:BCC POLYNOMIAL REGISTER

:BR IF GOOD
:SECONDARY REGISTER DATA ERROR

*CLEAR BIT4
*READ BCC POLYNOMIAL REGISTER

“EXPECT BCC POLYNOMIAL REGISTER

:TO CONTAIN 0

*ARE EXPECTED AND RECEIVED DATA THE SAME ?

:BR IF GOOD
*SECONDARY REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

:SECONDARY REGISTER READ/WRITE TEST
*SET BITS IN BCC POLYNOMIAL REGISTER
:VERIFY THAT BITS WAS SET
“CLEAR BITS
sVERIFY THAT BITS WAS CLEARED
;

3381

382

1%
6

CMP

001401
104006

3374
3375
3376
3377
gg;g

3353

BEQ
HLT

2 (RS)=BIT4
*SET BIT4 IN

TEST 114

tt'ttttitt'ttttttttttttttttfitttttt'tttttttttttt'ttttttttlttttttt!ttt

013100

012737

013114

012703

013106

012737

000114

013170

000017

001226

001216

7ST114: MOV

MOV

#114,TSTNO

#7ST115 NEXT

#17.R3

;ADDRESS OF SECONDARY REGISTER

(ZDQA
(1052)
MACY11
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

08:30 PAGE 69
POLYNOMIAL REGISTER READ/WRITE TESTS.

166244

R3,aDQREG

166236

MOvB
MOV
MOV

#BITS5,R5

166232

MoV

aDQSEC R4

CMP
BEQ
HLT
BIC
MOV
CLR

R5.R4
1%
6

cMP
BEQ
HLT
SCOPE

R5.R4

200040

1%:

2%:

R5,aDQSEC

aDQSEC R4
RS

SEQ 0068
;BCC_POLYNOMIAL

SE ECT
BgC POLYNOMIAL REGISTER
:SEY BITS IN

;BCC POLYNOMIAL REGISTER

: (R4)=ACTUAL DATA IN

sBCC POLYNOMIAL REGISTER
:ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
: SECONDARY REGISTER DATA ERROR

;CLEAR BITS
:READ BCC POLYNOMIAL REGISTER

;EXPECT BCC POLYNOMIAL REGISTER
:TO CONTAIN O
:ARE EXPECTED AND RECEIVED DATA THE SAME ?

:BR IF GOOD

s SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST
;SET BIT6 IN BCC POLYNOMIAL REGISTER
;VERIFY THAT BIT6 WAS SET

;CLEAR BIT6
;VERIFY THAT BIT6 WAS CLEARED
TEST 115

t'tttt'fitttt.tttt.ttt'ti""fi'tt'QQt'.tttttQttttQ'Qt..t't't""'tt"

013170
013176
013204

012737
012737
012703

000115
013260
000017

013210
013214
013220

110377
012705
010577

013224

017704

TST115:

nov
MOV

#115,TSTNO
#TST116,NEXT
#17 ,R3

;ADDRESS OF SECONDARY REGISTER

166154
000100
166146

MOVB
MOV
MOV

R3,aDQREG
#BI1T6,R5
R5,3DQSEC

sSELECT BCC POLYNOMIAL REGISTER
: (R5)=BITé6
;SET BIT6 IN

166142

MOV

aDQSEC,R4

: (R4)=ACTUAL DATA IN

CMP
BEQ
HLT
BIC
MOV
CLR

R5.R4
1%
6

104006

040577
017704
005005

020504
001401

21
2

FRERRRR W R KRR RRRRRRRRRRRRR
SVBLEUR 7 SR
RARN NS o®IG
N~ A—O

3409

1%:

020504
001401

104006
104400

CMP

BEQ
HLT

2%:

SCOPE

RS5,aDQSEC
aDQSEC R4
RS

R5.R4
2%

;BCC_POLYNOMIAL

:BCC POLYNOMIAL REGISTER

;BCC POLYNOMIAL REGISTER
JARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR
IF GOOD
s SECONDARY REGISTER DATA ERROR

;CLEAR BIT6
:READ BCC POLYNOMIAL REGISTER

;EXPECT BCC POLYNOMIAL REGISTER
:TO CONTAIN O
:ARE EXPECTED AND RECEIVED DATA THE SAME ?

:BR IF GOOD

: SECONDARY REGISTER DATA ERROR
:CHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT7 IN BCC_POLYNOMIAL REGISTER
;VERIFY THAT BIT7 WAS SET
;CLEAR BIT7
;VERIFY THAT BIT7 WAS CLEARED
TEST

116

———

I CZDQA

19-JuL-78
MACY11
(1052)
CZDQAD.P11
2 =~JUN-78 08:52

08:30

346461

A A

SEQ 0069

A RN

#TST117 NEXT

#17,R3

MOvB

013310

R5,aDQSEC

013314

MOV

aDQSEC R4

CMP
BEQ
HLT

RS R4
1%
6
R5,aDQSEC
aDQSEC R4
RS

BIC

MOV
CLR

;SET BIT7 IN

:BCC POLYNOMIAL REGISTER
s (RG)=ACTUAL DATA IN
:BCC POLYNOMIAL REGISTER
sARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
- SECONDARY REGISTER DATA ERROR

:CLEAR BIT?
:READ BCC POLYNOMIAL REGISTER

sEXPECT BCC POLYNOMIAL REGISTER

:TO CONTAIN O
:ARE EXPECTED AND RECEIVED DATA THE SAME

R5.R4

CMP
BEQ
HLT

2%:

AR AR R AR RS

ADDRESS OF SEEODARY REGISTER

R3,aDQREG
#BIT7,R5

MOV
MOV

1%:

R AR AR AR AR AR RN AR

#116,TSTNO

MOV
MOV

SCOPE

2%
6

:BR IF GOOD
; SECONDARY REGISTER DATA ERROR
:CHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT8 IN BCC POLYNOMIAL REGISTER
;VERIFY THAT BIT8 WAS SET
;CLEAR BITS8

;VERIFY THAT BIT8 WAS CLEARED
;
R

TEST 117
AR

A AR AR A AR A AR

000017

013370
013374
013400

165774
000400
1€5766

MOVB
MOV
MOV

R3,aDQREG

013404

165762

MOV

aDQSEC R4

CMP
BEQ
HLT
BIC
MOV
CLR

R5.R4
1%
6
RS5,aDQSEC
ggOSEC R4

(MP
BEQ

R5.R4

000117
013440

001226
001216

TST117: Mov
MOV
MOV

RERR

5750
5744

[
ga—y

FRRE XNarm o

999 o
RRRRY ®

013350
013356
013364

2228

RRRRRRRRR

tsT116: mov

| £

POLYNOMIAL REGISTER READ/WRITE TESTS.
SRR

%45

333 AV
St 4S5EEK

PAGE 70

1%:

2%:

HLT

SCOPE

#117,TSTNO
#TST120,NEXT
#17 ,R3
#BI1T8 RS
R5,aDQSEC

AR A AR AR AR AR AR AR

AR R

AR RN A A AR AR AR

;ADDRESS OF SECONDARY REGISTER
;BCC POLYNOMIAL
sSELECT BCC POLYNOMIAL REGISTER

;(RS)=BIT8

;SET BIT8 IN

;BCC POLYNOMIAL REGISTER
; (R4)=ACTUAL DATA IN
;BCC POLYNOMIAL REGISTER

;ARE EXPECTED AND RECEIVED DATA THE

;BR _IF GOOD
; SECONDARY REGISTER DATA ERROR

;CLEAR BITS8
:READ BCC POLYNOMIAL REGISTER

SAME

SEXPECT BCC POLYNOMIAL REGISTER
:TO CONTAIN O
:ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR _IF GOOD
; SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BITS N BCC POLYNOMIAL REGISTER
;VERIFY THAT BIT9 WAS SET

CZDQA
MACY11 _30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

F
6
08:30 PAGE 71
POLYNOMIAL REGISTER READ/WRITE TESTS.

SEQ 0070

;CLEAR BITY
;VERIFY THAT BIT9 WAS CLEARED
;

TEST 120

tt"t‘itfi"t."tt.....Q'i""..‘t.t".t.tttt.it't'...'.ttt."'.'t..t

TST120: mov

#120, TSTNO

#TSTI21 NEXT

MOV
MOV

#17.R3

MOV
MoV

R3,aDAREG
#BIT9, RS
RS,aDASEC

*SELECT BCC POLYNOMIAL REGISTER
*(RS)=BIT9
:SET BIT9 IN

MOV

aDASEC . R4

*(R4)=ACTUAL DATA IN

CMP
BEQ
HLT

RS,R4
18
‘

*ARE EXPECTED AND RECEIVED DATA THE SAME ?
*BR IF GOOD
*SECONDARY REGISTER DATA ERROR

aDASEC,Ré

“READ BCC POLYNOMIAL REGISTER

RS.R4
2%

*BR IF GOOD

1%:

:BCC POLYNOMIAL REGISTER

:CLEAR BIT9

CMP
BEQ

2%$:

“BCC POLYNOMIAL REGISTER

RS,aDQSEC

BIC

MOV
CLR

013520
013522
013524
013526

HLT

*EXPECT BCC POLYNOMIAL REGISTER
:TC CONTAIN 0
:ARE EXPECTED AND RECEIVED DATA THE SAME ?
; SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

SCOPE

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT10 IN BCC POLYNUMIAL REGISTER
;VERIFY THAT BIT10 WAS SET
;CLEAR BIT10
;VERIFY THAT BIT10 WAS CLEARED
;

ST I

SRR R AR A A A

000121

013620
000017

001226
001216

AR A AR A A A A

TST121: MOV
MOV
MOV

165614

—2 3 2
e
e

1%:

020504
001401

104006
104400

MOV

aDQSEC R4
1%

MOV
CLR

6
RS ,aDQSEC
aDQSEC ,Ré
RS

(MP

R5.Ré

BIC

BEQ

’%:

#17 ,R3

R3,aDQREG
#81T10,RS
R5.,aDQSEC

HLT

SCOPE

AR AR R A A AR AR AR R AR AR AR AR R AR AR AR

#121,TSTNO
#TST122 NEXT

MOVB
MOV
MOV

CMP
BEQ

WWWWWWWW
vivvvonavinawn

MOVB

013512
013516

;ADDRESS OF SECONDARY REGISTER
*BCC POLYNOMIAL

AR AR AR AR

sADDRESS OF SECONDARY REGISTER
sBCC_POLYNOMIAL
sSELECT BCC POLYNOMIAL REGISTER

:(R5)=BIT10

;SET BIT10 IN

;BCC POLYNOMIAL REGISTER

; (R4)=ACTUAL DATA IN
;BCC POLYNOMIAL REGISTER
;ARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR _IF GOOD
; SECONDARY REGISTER DATA ERROR

:CLEAR BIT10

*READ BCC POLYNOMIAL REGISTER
JEXPECT BCC POLYNOMIAL REGISTER
;TO CONTAIN O
JARE EXPECTED AND RECEIVED DATA THE SAME 2
:BR IF GOOD
s SECONDARY REGISTER DATA ERROR
JCHECK FOR ITERATIONS, LOOP

| cz0A
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

08:30 PAGE 72
POLYNOMIAL REGISTER READ/WRITE TESTS.

SEQ 0071

s SECONDARY REGISTER READ/WRITE TEST
;SET BIT11 IN BCC POLYNOMIAL REGISTER
;VERIFY THAT BIT11 WAS SET
;CLEAR BITN

sVERIFY THAT BIT11 WAS CLEARED

TEST 122
ttttt'.tgtitt.QQt'tt.i't"'tttit'.tt..t.t't"t..t.t.tfittt..."'i.tt.

TsT122: MOV

MOV

#17.R3

MOVB

R3,aDOREG

MOV

RS,aDQSEC

#BIT11,RS

MOV

aDQSEC R4

CMP
BEQ

RS ,R4
1%

HLT
BIC
MOV

CLR

CMP
BEQ
2%:

#TSTI23, NEXT

MOV
MOV

1%:

#122,TSTNO

HLT

.
RS,aDOSEC
aDASEC,R4

RS.R4
2%

SCOPE

:ADDRESS OF SECONDARY REGISTER
*BCC POLYNOMIAL
*SELECT BCC POLYNOMIAL REGISTER
< (RS)=BIT11

SSET BIT11 IN
:BCC POLYNOMIAL REGISTER
: (R4)=ACTUAL DATA IN

:BCC POLYNOMIAL REGISTER

:ARE EXPECTED AND RECEIVED DATA THE SAME ?
*BR IF GOOD

:SECONDARY REGISTER DATA ERROR
:CLEAR BIT11
*READ BCC POLYNOMIAL REGISTER

*EXPECT BCC POLYNOMIAL REGISTER

*TO CONTAIN O

“ARE EXPECTED AND RECEIVED DATA THE SAME ?
*BR IF GOOD

*SECONDARY REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

s SECONDARY REGISTER READ/WRITE TEST

;SET BIT12 IN BCC_POLYNOMIAL REGISTER
;VERIFY THAT BIT12 WAS SET
;CLEAR BIT12
;VERIFY THAT BIT12 WAS CLEARED
:

TEST 123

b
-b

ronY

00012
014000
000017

'.'tt't'.tt.tt.'tt".t""'tQttfi"tttfit'.'!t!.'t.t..t.'t...t'..tt.t'

1ST123: MOV

165434

010000
165426

165422

165410

165404

'$:

#123,TSTNO

MOV
MOV

#TST124 NEXT
#17 ,R3

MOVB
MoV
MOV

R3,aDQREG
#BIT12,RS
RS5.,aDQSEC

MOV

aDQSEC R4

CMP

RS5,R4

HLT

BEQ

BIC
MOv

(LR

RS ,aDQSEC
aDQSEC R4
.

sADDRESS OF SECONDARY REGISTER
:BCC_POLYNOMIAL
sSELECT BCC POLYNOMIAL REGISTER
:(R5)=BIT12

;SET BIT12 IN

;BCC POLYNOMIAL REGISTER
: (R4)=ACTUAL DATA IN
;BCC POLYNOMIAL REGISTER

sARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR
IF GOOD

; SECONDARY REGISTER DATA ERROR

;CLEAR BIT1?
:READ BCC POLYNOMIAL REGISTER

JEXPECT BCC POLYNOMIAL REGISTER

;TO CONTAIN O

00O NN N S NN
=

RRRREEEEEEEEES28

CZDQA
MACY11
(1052)
19=JuL-78
CZDQAD.P11
08:52
27= JUN=-78

3625

013770
013772
013774
013776

H 6
08:30 PAGE 73
POLYNOMIAL REGISTER READ/WRITE TESTS.

020504
001401

MP
BEQ

104006

104400

2%:

HLT

SCOPE

RS.R4
2%

SEQ 0072

;ARE EXPECTED AND RECEIVED DATA THE SAME ?
*BR
IF GOOD

*SECONDARY REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

:SECONDARY REGISTER READ/WRITE TEST

:SET BIT13 IN BCC POLYNOMIAL REGISTER
SVERIFY THAT BIT13 WAS SET

*CLEAR BIT13
:VERIFY THAT BIT13 WAS CLEARED
;

012737

014014

012737
012703

110377

000124

014070

000017

001226

001216

TEST 124

tttt.l'tltt'.ttttt..ttt't"tttQtttt..ttt...t.ltt'Qtt'l'tt"'..t't'tt

1ST124: MOV

MOV

#124,TSTNO

#TST125 NEXT
#17.R3

014020
014024
014030

012705
010577

020000
165336

165344

MOVB

R3,aDQREG

014034

017704

165332

MOV

aDQSEC R4

014040
014042
014044
014046
014052
014056

020504

TMMP

RS,R4

CMP
BEQ

RS,R4
2%

001401
104006
040577
017704
005005

MOV
MOV

165320
165314

1$:

020504
001401

104006

104400

2%:

BEQ
HLT
BIC
MOV
CLR

HLT

#MIT13,.RS5
RS,aDQASEC

1%
6
RS, aDQSEC
aDASEC ,R&
RS

SCOPE

;ADDRESS OF SECONDARY REGISTER
*BCC POLYNOMIAL

*SELECT BCC POLYNOMIAL REGISTER

*(RS)=BIT13
“SET BIT13 IN

:BCC POLYNOMIAL REGISTER
: (R4)=ACTUAL DATA IN

:BCC POLYNOMIAL REGISTER

:ARE EXPECTED AND RECEIVED DATA THE SAME 2

*BR IF GOOD
:SECONDARY REGISTER DATA ERROR
*CLEAR BIT13
*READ BCC POLYNOMIAL REGISTER
SEXPECT BCC POLYNOMIAL REGISTER

*TO CONTAIN
0

*ARE EXPECTED AND RECEIVED DATA THE SAME ?
‘BR IF GOOD
*SECONDARY REGISTER DATA ERROR

:CHECK FOR ITERATIONS, LOOP

;SECONDARY REGISTER READ/WRITE TEST
:SET BIT14 IN BCC POLYNOMIAL REGISTER
SVERIFY THAT BIT14 WAS SET

*CLEAR BIT14

*VERIFY THAT BIT14 WAS CLEARED
TEST 125
:ttttttttt'lt'.ttt.tttt"'tttttttttt'tttQtt"t.ttttttttfit.'tttttt'tt.

012737

014070
014076
014104

012703

014110
014114
014120

012705
010577

040000
165246

165254

MOVB

MOV
MOV

#5714 RS
RS, aDQSEC

014124

017704

165242

MOV

aDQSEC R4

*(RS)=BIT14
*SET BIT14 IN
:BCC POLYNOMIAL REGISTER
:(R4)=ACTUAL DATA IN

014130
014132
014134

020504
001401
104006

(MP
BEQ
HLT

RS, R4
13
:

:BCC POLYNOMIAL REGISTER
:ARE EXPECTED AND RECEIVED DATA THE SAME 2
*BR IF GOOD
:SECONDARY REGISTER DATA ERROR

012737
110377

000125

014160

000017

001226

001216

TST125: MOV

MOV

#125, TSTNO

#1ST126 ,NEXT
#17.R3

R3,aDQREG

;ADDRESS OF SECONDARY REGISTER
*BCC POLYNOMIAL

*SELECT BCC POLYNOMIAL REGISTER

e
e e

CZDQA
MACYN 30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

3665
3666
3667

014136
014142
014146

040577
017704
005005

3669
3670
3671
332;%

014150
014152
014154
014156

020504
001401
104006
104400

3668

165230
165224

18:

2%:

3674
3675
3676
3677

3682

;

014160

012737

000126

3684

014166

014174

012737

014250

3686
3687
3688

014200
014204
014210

110377
012705
010577

014214

017704

3692
3693
3694
3695
3696
3697

014220
014222
014224
014226
014232
014236

020504
001401
104006
040577
0177064
005005

3699
3700
3701
3702

014240
014242
014244
C14246

020504
001401
104006
104400

3685

3689
3690
3691

3698

R5,aDQSEC
aDQSEC,R4
RS

CMP
BEQ
HLT
SCOPE

R5.R4
2%
6

;CLEAR BIT14
:READ BCC POLYNOMIAL REGISTER
EXPECT BCC POLYNOMIAL REGISTER

:TO CONTAIN O

:ARE EXPECTED AND RECEIVED DATA THE SAME ?
:BR IF GOOD
s SECONDARY REGISTER DATA ERROR
sCHECK FOR ITERATIONS, LOOP

;VERIFY THAT BIT15 WAS CLEARED

3680
3683

BIC
MOV
CLR

SEQ 0073

s SECONDARY REGISTER READ/WRITE TEST
;SET BIT15 IN BCC POLYNOMIAL REGISTER
;VERIFY THAT BIT15 WAS SET
;CLEAR BIT15

332;3

08: 30 PAGE 74
POLYNOMIAL RECISTER READ/WRITE TESTS.

012703

001226

TEST 126

AR AR AR AR AR AR A AR AR AR AR AR AR AR AR AR AR AR

TST126: MOV

#126,TSTNO

AR RARRAARARR AR AR AR AR

MOV

#.50P NEXT

#17,RS

;ADDRESS OF SECONDARY REGISTER

165164
100000
165156

MOVB
MOV
MOV

R3,aDQREG
#BIT15,RS
R5,aDQSEC

sSELECT BCC POLYNOMIAL REGISTER
:(R5)=BIT15
;SET BIT15 IN

165152

MOV

aDQSEC R4

CMP
BEQ
HLT
BIC
MOV
(LR

RS.R4
1%
6
RS5,aDQSEC
aDQSEC RS
RS

CMP
BEQ
HLT
SCOPE

RS.R4
2%
6

000017

165140
165134

001216

MOV

18:

‘’$:

:BCC_POLYNOMIAL

;BCC POLYNOMIAL REGISTER
; (R4)=ACTUAL DATA IN
;BCC POLYNOMIAL REGISTER

JARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR _IF GOOD
s SECONDARY REGISTER DATA ERROR
:CLEAR BIT15
:READ BCC POLYNOMIAL REGISTER
SEXPECT BCC POLYNOMIAL REGISTER

:TO CONTAIN O

:ARE EXPECTED AND RECEIVED DATA THE SAME ?
;BR IF GOOD
- SECONDARY REGISTER DATA ERROR
;CHECK FOR ITERATIONS, LOOP

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

08:30 PAGE 75
POLYNOMIAL REGISTER READ/WRITE TESTS.

3703

SEQ 0074

;END OF PASS
sTYPE NAME OF TEST

JUPDATE PASS COUNT
sCHECK FOR EXIT TO ACT=11
.
:RESTART TEST

3710
3711
3712

014250
014254
014260

005037
005037
005237
104402

001234
001372
001230

.EOP:

CLR

CLR
INC

TYPE

LSTERR
ERRFLG

PASCNT

;CLEAR LAST ERROR PC
;CLEAR ERROR FLAG
;UPDATE PASS COUNT

PASC
,aL NT
IGHTS

;DISPLAY PASS COUNT

MEPASS

TYPE
MCSRX
CNVRT
XCSR
TYPE

MVECX
CNVRT

XVEC
TYPE
MPASSX

CNVRT
XPASS
TYPE
MERRX
CNVRT
XERR
MOV
DEC

164644

BNE

001276

LOGICAL:

3744
3745

014374
014402

012737
000137

002254
002254

3747

014410

006

002

3750

014416

003

002

3753

014424

006

002

3756

014432

006

002

001214

MOV
MOV
BEQ
RESET

JSR
NOP

NOP
NOP
RESTRT: CKSWR
MOV
#MP
XCSR:

XVEC:
XPASS:
XERR:

.BYTE

?ORCSR

?ORVEC

SAVNUM
RESTRT
DQNUM, SAVNUM

a4l ,R1
RESTRT

PC.(R1)

#TST1,RETURN
TST1

6.2
3,2

BYTE

6.2

BYTE

6.2

7ASCNT

ERRCNT

;CHECK FOR ACT=11 OR DDP

:IF NOT,

CONTINUE

TESTING

CZDQA
MACY11 30A(1052)
19-JuL=-78
CZDQAD.P11
27-JUN-78 08:52

K 6
08:30 PAGE 76
GENERAL UTILITIES (TYPE OUT,ERROR,SCOPE.ETC.)

g?,gg

;SCOPE LOOP AND INTERATION HANDLER

3761
§7

014436
014440

3764
3765

014450
014452

763

104414
032777

014446

001407

3766
3767
3768

014456
014460
014464

100027
017700
000412

3770

0144746

001006

3769
3771

014466

000432
105777

014476

005237

001224

014516

005037

3776
3777
3778

014522
014530
014536

012737
013737
013716

3780
ggg}

014544
014546

001407
000432

3779

014542

023737
001012
105037

000002

.SCOPE: CKSWR
BIT

TTST:

164522
004000

014502
014510
014512

164532

164526

032777

3772
3773
3774
3775

040000

001224

164504

002000
001216
001214

001222
001214

3788

g;gg

3$:

MOV
MOV
MOV

BRW:
BRX :

1407
432

014550
014552
014560

104414
032777
001402

014566

000002

014562

013716

010546

3795
3796

014576
014604

062766
005737

001000

164420

001220

014572

017605

000002

.SCOP1: CKSWR
BIT
BEQ

1%:

000002

010000

164360

001004

014620

001024

014624

100014

014632
014634

100375
012777

3806
3807

014646
014650

100375
012777

000012

3809
3810
3811
3812

014662
014664
014670
014672

100375
112577
001345
012605

164322

014612

3800

014622

3802

014626

3801

3803
3804
3805

3808

333}2

014642

014656

014674

032777

.TYPE:

000002
016260

014610

3799

RTI

3s
aTKCSR

38
aTKDBR,RO
2%

#SW11,aSWR

LPCNT

LPCNT, 1COUNT
3s
ERRFLG
LPCNT

#2000,
I COUNT
NEXT
,RE TURN
RETURN, (SP)

MOV
RTI

#5W09, aSWR
1%

LOCK, (SP)

:TELETYPE OUTPUT ROUT INE

014570

3798

CLR

#B1T14,aSWR

;CHECK FOR FREEZE ON CURRENT DATA

3793

3797

BIT

BNE

2%:

%;3}

3794

BPL
MOV
Bk

(MP
BNE
CLRB

gg{s‘

3785
3786
3787

B
TSTB

INC

001222

001312
001224

1%:

BEQ

105715

105777

000002

1%:

164356

164342
164326

ADD
TST

BNE
BIT

3008:

000015

MOV

BNE

TSTB

BPL

TSTB

RS,=(SP)

@2(SP) RS
#2,2(SP)
SRDSW

300%

#SW12,3SWR

(RS)

aTPCSR

164350

BPL
MOV

=4
#15,aTPDBR

164334

BPL
MOV

b
#12,3TPDBR

BPL
MOVR
BNE
MOV

2%
(RS) +,aTPDBR
1%
(SP)+,R5

TSTR

2%:

TSTB

RT]

aTPCSR

aTP(SR

SEQ 0075

CZDQA
19-JuL~-78
MACY1T
CZDQAD.P11
27=JUN-78 08:52

08:30 PAGE 77
GENERAL UTILITIES (TYPE OUT,ERROR,SCOPE,ETC.)

3815

sASCII STRING INPUT ROUTINE
014676
014700
014702
014710

MOV
000004
000002

R4 ,=(SP)
@4 (SP)
, .MSG
#2,4(SP)

MOV

# INBUF ,R4

TSTB

aTKCSR
1$
@TKDBR, (R&)

TYPE

017052
000007

MOV

164246

BPL

164242

MOvB

000200
000025
016440

R3,-(SP)

MOV
MOV
ADD

#7 ,R3

BI(B
CMPB
BNE

#200, (R4)
(R4) 425
200%

BR
C(MPB

. INST1
(R4)+,#15

TYPE ,MCRLF

000015

BEQ

164210
164204

@TKDBR,aTPDBR

BPL
DEC
BNE

2%
R3
1%

MOV

R4 ,-(SP)

TSTB

TYPE
MQM
TST

016260

BEQ

016440

INSTR

MOVB

@TPCSR

INSTG

a#RDSW

400%

TYPE ,MCRLF

MOV

MOV
RTI

.INST1

(SP)
+ ,R4

(SP)+,R3

39A%
wviwvnwnuononawng

R 5 & WWWWW
NNNNN VIONON

NWNNO
&

PoS
Pl

N —=PNONY
=

]

by
2

WNININY
— —

-2 -2 =

R
R

—

(IV IV IV IV IV [V IV

elelelelelelele)

015076

b ad aubd ad

b ad

O==000000
-

b wsd

s CONVERT ASCII STRING TO OCTAL
: MOV
MOV

MOV
MOV
MOV
MOV
MOVB
MOVB
MOV
MOV

CMPB

BEQ
(MPB
BLT
(MPB

R5,=(SP)
R4 ,=(SP)

4(SP) ,RS
(R5)+,LOLIM
(R5)+ HILIM
(R5)+,DEVADR
(R5)+,LOBITS
(R5)
+ ,ADRCNT
sg.é(SP)
# INBUF
R4

#15, (R4)

PARERR
(R4) ,#60
PARERR
(R4) 467

JIS IT <*G>

SEQ 0076

CZDQA
MACY11 30A(1052)
19=JuL-78
CZDQAD.P11
27-JUN-78 08:52

M6
08:30 PAGE 78
GENERAL UTILITIES (TYPE OUT,ERROR,SCOPE,ETC.)

3871
3872

015134
015136

003012
142714

000060

BGT
BICB

PARERR
#60, (R4)

3874

015144

122714

000015

CMPB

#15, (R4)

3876
3877
3878

015152
015154
015156

006305
006305
006305

ASL
ASL
ASL

RS
RS
RS

3880

015162

122714

3873
3875

3879

3881
3882
3883
3884

3885

015142

015150

015160

152405

001414

000760

015166
015170
015174

001003
005737
001023

015200

000742

015176

BISB
BEQ
BR

000015

PARERR: CMPB

016260

104404

1208:

3889

3890
3891
3892
3893

ssggts.

015202

015206
015210
015214
015216

015222

020537

101365
020537
103762
133705

001357

015224
015230
015232

013704
010524
062705

3902

015242

001372

3904

3905
3906
3907
3908
3909

gg%)

015254

BLO
BITB

PARERR
LOBITS,RS

]
015260

BNE

015236

105337

015256

1%:

000002

015261

PARERR

DEVADR R4
RS, (R4)+
#2 ,R5

BNE

DECB

012604

PARTI:

015250
015252
015254
015256
015260

000002
000000
000000
000000
000000

RTI
LoLim:
0
HILIM:
0
DEVADR: 0
LOBITS: 0

015246

012605

015261

MOV

ADRCNT

(SP) +,Ré

(SP)+,RS

ADRCNT=LOBITS+1
:SAVE PC OF TEST THAT FAILED AND RO-RS
000004

3918

015270

010537

001270

gggg

015320

3926

;1S CK3WR ROUTINE BEING USED

PARERR
RS,LOLIM

MOV
MOV
ADD

015244

016637

3919
3920
3921
3922
3923

;1S FIRST CHARACTER A <CR>

PARAM1
RS,HILIM

BHI
CMP

015252

015262

gg}?

INSTER

B8R

1208
SHRDSW
PART|

LIMITS: CMP

%31%
gg}g

#15, (R4)

:STORE NUMBER AT SPECIFIED ADDRESS

3898
3899
3900
3903

BNE
TST
BNE

LIMITS

sTEST TO SEE IF NUMBER IS WITHIN LIMITS

333367

3901

(R4&S+,RS

015274
015300
015304
015310
015314

010437
010337
010237
019137
010037
000002

001266
001264
001262
001260
001256

001274

.SAVOS: MOV

4(SP) ,SAVPC

;SAVE RO-RS

SV05:

MoV

MOV
MOV
MOV
MOV
MOV
RTI

RS, SAVRS

R4, SAVR4
R3,SAVR3
R2,SAVR2
R1,SAVR1
RO, SAVRO

;RESTORE RO=-RS

SEQ 0077

CZDQA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

3927
3928

015322

%3%‘5‘

015352

3929 015326
3930 015332
3931 015336
3932 015342
3933 015346

013700

013701
013702
013703
013704
013705
000002

N 6
08:30 PAGE 79
GENERAL UTILITIES (TYPE OUT,ERROR,SCOPE,.ETC.)

001256

.RESOS: MOV

001260
001262
001264
001266
001270

%g%g
3938
3939
3940

3941
3042
3943
3944
3945
3946
3947
3048

3949
3950

3951
3952

3953

3954
3955

3956

3957

104402
016440
010046

000012
017114
000002
015574

015426
015432

013137
013704

015600
015600

015442
015446

012700
010403

015454

062703

015416
015422
015436

015450

112137
112137

015576

042703

177770

3963

015472

000241

3065

015476

005305

3971
3972
3973
3974

3975

3976
3977
3978
3979

2080
3981
3982

015464

015470
015474

015500
015502
015506
015510

015514

015516
015522
015526
015530

015534

015536
015540
015542
015544

015550
015552
015560

110320
000241

R1,=(SP)
R3,=(SP)
R&.=(SP)
RS .=(SP)
@12(SP) ,R1
TEMP, TEMP3
#2,12(SP)
(R1)+,WRDCNT

2%:

MOV
MOV

@(R1)+,BINWRD
BINWRD
. R4

3$:

MOV
MOV

#TEMP,RO
R4 ,R3

ADD

#060,R3

1%:

017114

000060

114023
105337

001374

105737
001405
112723
105337

001373

105013
104402
017156
005337

oo13§2
013737
012605

MOVB
MOVB

MOVB

BIC

MOVB
cLC

006004

001362
012703

015577

000040
015577

5% :
6%

015574

001250

017114

#177770.R3
R3,(RO)+

ROR

BNE
MOV

38
#MDATA ,R3

BNE

DEC

4%:

CHRCNT.RS

CcLC

015576

(R1)+.CHRCNT
(R1)+.SPACNT

ROR
CLC

017156

RO, =(SP)

MOV
MOV
MOV
MOV
MOV
MOV
ADD
MOV

001250
000012

015576
015577

113705

000241

3970

TYPE
MCRLF
.CNVRT: MOV

010146
010346
010446
010546
017601
013737
062766
012137

015466

3068
3969

.CONVR:

015362
015364
015366
015370
015372
015376
015404
015412

3961

3966
3967

015354
015356
015360

015460
015462

3064

RT]

SAVRO,R0

SAVR1.R1
SAVR2.R2
SAVR3.R3
SAVRS
.R
SAVRS RS

;CONVERT OCTAL NUMBER TO ASCII AND OUTPUT TO TELEPRINTER

3958
3059

3060

MOV
MOV
MOV
MOV
MOV

SEQ 0078

MOVB
DECB

TSTB
BEQ
MOVEB
DECB

BNE

-(RO),(R3)+
CHRCNT

SPACNT
6$
#040, (R3)+
SPACNT

CLRB
TYPE
MDATA
DEC

WRDCNT

MOV

(SP)+ RS

BNE
MOV

(R®)

1%
TCMP3, TEMP

(1052)

000000

WRDCNT:
CHRCNT:

(SP)+ R4
(SP)+ R3
(SP)+ R1
(SP)+ RO

TEEPEEE

—d

:TRAP DISPATCH SERVICE
sARGUMENT OF TRAP IS EXTRACTED
;AND USED AS OFFSET 7O OBTAIN POINTER
;TO SELECTED SUBROUTINE

.TRPSR: MOv

000002
000000

TRPOK
:

177001

001314
000000

SUB
MOV

ASL
BIC
ADD
MOV
JMP

(SP) ,=(SP)

;GET PC OF RETURN

(SP)
#177001, (SP)
#.TRPTAB, (SP)
a(SP), (SP)
a(SP)+

sMULTIPLY TRAP ARG BY 2
;CLEAR UNWANTED BITS
sPOINTER TO SUBROUTINE ADDRESS
s SUBROUTINE ADDRESS

#2,(SP)
a(SP), (SP)

IS FER

;ERROR HANDLER

g_.

3 gR3 2R SRR

NRY
I

D e

e e

d e

d
e e
e

D o

Vi i v
~N

jelelelelelelelelelelalelelelelelelelelelels)

+1
SPACNT=CHRCNT

BINWRD

g e

23444g
X

(elelelelelelsle)

PAGE 80
RAL UTILITIES (TYPE OUT,ERROR,SCOPE
ETC.)

MOV
MOV
MOV
fl%}f

GENE

08:30

OO0

19-JuL-78

—W

562
564

vivvwvawvaiwvanaoa

e
Blelelelelelele)
3
=
—_— D
D
—

2;9‘“0;‘ 08:52

29229229

SERERSSTIYSI LSS

laln

¢’i

CKSWR

010000

BIT

#5W12,aSWR

163336

TSTB

aTPCSR

MOVB

#207,aTPDBR

BNE
CMP
BEQ
MOV
CLRB

HALTS
(SP) ,LSTERR
1%
(SP) ,LSTERR
ERRFLG

000207
020000

BEQ
BPL

163310

xBX:

001234

001234
001312

1%:

000002

BIT

SAVOS

XBX

#5W1%5, aSWR

MOV
SUB

(SP) RS
#2 RS

ASL

Ré

MOV
ADD

BIC
ADD
MOV
MOV
MOV

(RS) .R4

(RS) ,R4

#177001,R4
# .ERRTAB
R4

(R4)
+ ,ERRMSG
(R4)
+ ,DATAHD
(R<) ,DATABP

TSTB

ERRFLG

TST

DATABP
TYPDAT

BEQ
TYPMSG:

XBX

BNE

TYPE

TYPMSG

:=PC OF TRAP
;GET TRP

:GC TO SUBROUTINE

SEQ 0079

CZDQA
MACYN
9
CZDQAD.P11
27=JUN~-

4039
4040
4041
404
404
4044
4045
40#9
4047

4048
4049
4050

4051
4052
4053

4056

4055
4056
4057

4058
4059
4060
4061
4062

4063

4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
40764
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
409

015776
016000
016002
16004
16006
81601g
01601
016014
016022

)

19=JuL~-78
08:52
:

08:30 PAGE 81
ETC.)
GENE RAL UTILITIES (TYPE OUT,ERROR,SCOPE

016156

XTSTN
TYPE

MERRP(C
CNVRT

ERTABO
TYPE

177777

016032

0160%8
0160
016032

MCRLF
MOVB
TST
BEQ

001312

TYPE

#-1_ERRFLG
ERRMSG
WRKO.FM

ERRMSG: 0

016034
016034
016040

016044

016044
016046
016052

016056

WRKO.FM:

TST

BEQ

016042

TYPE

016054
016056
016060

DATAHD: 0
TYPDAT:

TST

BEQ
CONVRT

DATAHD

TYPDAT

DATABP

RESREG

DATABP: 0

016062
016066

163112

016072
016076
016100
016102
016104
016110
016116
016120
016126
016130
016136
016142
016146
016150
016152
016154
016156
016160
016162

000002

016070

RESREG: RESOS
HALTS:

TST

aSWR

PUSHRO
MOV

2(SP) ,RO

POPRO
CKSWR
INC
BIT
BNE
BIT
BEQ

ERRCNT
#SWO8,aSWR
1%
#SW10,aSWR
2%

HALT

EXITER:
163062
163052

001214

1%:

2%:

ERTABO:
XTSTN:

MOV
MOV
JMP

RTI

1
BYTE
SAVP(
1

BYTE

TSTNO

EXITER

NEXT
,RE TURN
#STACK ,SP
@RETURN

6.2

3,2

JENTER HERE ON POWER FAILURE

016164
016164
016172
016174

016176

000024

PFAIL:

MOV
gsLT

#RCSTART 24

;SET UP FOR POWER UP TRAP
JHALT ON POWER DOWN NORMAL

sPROCESSOR WILL TRAP HERE WHEN POWER IS RESTORED
016176
016176

012737

016164

000024

RESTAR:

MOV

#.PFAIL,24

;SET UP FOR POWER FAILURE

SEQ 0080

e
D cd
)

08:30

MOV
CLR

INC
BNE
TYPE

MPFAIL
CNVRT
PFTAB

001312
001234

CLR
CLR

104412
104413
000177 162742
1
003
002
001226

GENERAL UTILITIES (TYPE OUT,ERROR,SCOPE.ETC.)

mgrog 001200
00 og 017114
005237 017114
001375
10440
01644
104411
01625
005037
005037

PAGE 82

PFTAS:

BYTE

#STACK,SP
TEMP
TEMP
b

ERRFLG
LSTERR

MSTCLR
MEMCLR
JMP
ARE TURN
1

3,2
TSTNO

—

Bomwo\nbu«\:—aos &<

:SFHEEScs#ch REGISTER ROUTINE. CHECKS FOR “G TO ALLOW CHANGING
*LOCATIONS USED:

000000
005737

RDSW:
000042

1042
022737 000176 001200
1036
105777 162700
100033
017737 162674 014720

042737

122737

001021

104402

005137
104402
104411
104403

104405

177600

000007

.CKSWR: TST

014720

016410

104402

005037

000002
000001
006
000176

.WORD

BNE
CMP
BNE
TSTB
BPL
MOV

ouT
#SWREG, SWR
ouT
oTKCSR
ouT
aTKDBR, .MSG

(MPB

#7,.MSG

BIC

014720

BNE

#177600..MSG

ouf

TYPE ,$CNTG

016260

LCNTLU: COM

016414
016402
016423

SRDSW

TYPE
, SMSWR
CNVRT
, SWREGC
INSTR
. SMNEW

SARM

177777

000176

PRk

0 OB S S

PR
R RN
AN
- i
i i ch D

R o o O O

N R—
b i

)

—

)

) i

RO RO
FERGROERER
RSS~sO

—

[clelolelolololololololololete] o

CZDQA
MACYN
(1\.;5)
19-JuL-78
CZDQAD.P11
27-JUN-78
08:52

177777

001
016440

.BYTE

016260

SWREG

0,1
TYPE ,MCRLF

ouT:

CLR

SHRDSW

RTI
SWREGC: 1
BYTE 6.2
SWREG

002

057377
051777

000107
051127

020075

$CNTG:
S$MSWR:

.ASCIZ
.ASCIZ

<377>/%G/
<377>/SWR= /

040

047040

053505

SMNEW:

.ASCIZ

020075
016434

000

.EVEN

NEW= /

:SOFTWARE SWITCH REGISTER PRESENT
*NO, GET OUT

JYES,WAIT FOR

*READY, GET CHARACTER
*AND STRIP OFF

:THE GARBAGE

YIS IT A <*G>

SEQ 0081

08:52

016434

000077

MQM :

LASCIZ

051127
062514
051505
04044g
05212
04211

MPFAIL:

.ASCIZ

<377>/PWR FAILED. RESTART AT TEST /

MEPASS:

.ASCIZ

<377>/END PASS CZDQA

MR:

LASCIZ

.ASCIZ

<377>/R/
<377>/PROGRAM INDICATES NO DEVICES PRESENT./

MERR3:

_ASCIZ

<377>/INSUFFICIENT DATA!/

MTSTPC:

.ASCIZ

<377>/TEST PC=~/

MLOCK:

.ASCIZ

<377>/L0CK ON SELECTED TEST/

MCSRX:

.ASCIZ

MVECX:

.ASCIZ

/VEC:

MPASSX:

.ASCIZ

/PASSES:

MERRX:

.ASCIZ

/ERRORS:

MISTN:

_ASCIZ

<377><377> /TEST NO:

MNEW:

LASCIZ

<377>/SET SWITCH REG TO DQ11'S DESIRED ACTIVE./

—_

08:30

PAGE 83

GENERAL UTILITIES (TYPE OUT,ERROR,SCOPE,ETC.)

MCRLF:

MERRZ:

.ASCIZ

<377>

—

RRS

N =NO

S2 88
SRRRR
NI ER

R&a O‘N—'OMMBg3

19-JuL-78

VSN

—

) d

d d

)

D i

D e

)

) e

)

D e

AR S T1

S328 ; 3 REERRR &8 %rafir£§m&m:§§~ & 2%

eolelelele] jelelelelelelelelelelelelelalelelelelelelelelelelelelelele]

CZDQA
MACYN
CZDQAD.P11
27=JUN=

MERRPC:
XHEAD:

.ASCIZ

.EVEN
XSTATQ: 2
BYTE

/CSR:

PC:

<377>/MAP OF DQ11 STATUS/<377>

SEQ 0082

CZDQA

MACYN

CZDQAD.P11
4207

4209

017046

017050

(1052)

27=JUN-78

08:52

006

002

001246

4210
2%‘]'1

4213
4214

4215

6216
4217

19-JuL-78

08:30

PAGE 84

GENERAL UTILITIES (TYPE OUT,ERROR,SCOPE ,ETC.)
BYTE

.EVEN

TEMP?2

6,2

;BUFFERS FOR INPUT=QUTPUT
017052

017114
017156

000000
017114
000000

017156
000000

INBUF:
.=. 460

TEMP:

.=.+40
MDATA:

O
O

SEQ 0083

(Z0an

mACY11, (1035)19-0UL-78

CZDQAD.P11
4219
4ggd
4221

017220
017222

000002
000002

017226
017261
017316
017356
017421
017446
017503
017534
017560
017621

042101
120
042502
051124
105
051777
123
051377
042777
377

08:30

PAGE 85

051505
040515
053111
046523
051117
047117
047117
051511
041505
042520

EMO:
EM1:
EM2:
EM3:
EM&:
EMS:
EMé:
DHO:
DH1
DH2: =~

RTI
RT]
:TABLE OF ERROR MESSAGES AND ERROR DATA POINTERS

.ASCIZ
_ASCIZ
.ASCIZ
ASCIZ
ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
'ASCIZ
ASCIZ

4222
4223
4226

4225
4226
4227
4228
4229
4230
4231
4232

4233
423
4235

4236

4237
4238

4239
4240
4241
4242

4243

017670
017672
017674

017676
017700
017702
017704
017706
017710
017712
017714

017716
017720
017722
017724

017726
017730

017732
017734
017736
017740

017742
017744

017224
017534
017750

000000
017503
017621
017774
017446
017621

017774

4247

017750

000001

4249
4250
4251
4252

017754
017756
017760
017762

001270
000003
006
001270

4254

017766

001266

017772
017774
017776
0
020002
020004
020006

001264
000004
_ 006
001270
006
001266
006

4253

4255

4256
4257
4258
4259
4260
4261
4262

017764

017770

DTO
EMI
DH1
DT1
EM2
DH1
DT1
EM3
DH1
DT1
EM&
DH1
DT
0
0
0
EM6
DH2
DT2
EMS
DH2

017756
017421
017560
017756

017746

4248 017752

ERRTAB : EMO

017261
017560
017756
017316
017560
017756
017356
017560

006

DT2

000

TABLES FOR ERROR MESSAGES.
MEMCLR:
-MSTCLR:

051104
044522
062503
047101
051122
041505
041505
043505
050130
054105

DTO:

.BYTE

6,0

SAVRS
3
6,4
SAVRS

004

pT1:
BYTE

004

BYTE

6,4

000

.BYTE

6,0

004

DT2:
BYTE

004

BYTE

004

BYTE

SAVR4

SAVR3
&
6,4
SAVRS
6,4
SAVR4
6,4

/ADDRESS SELECT ERROR=TIMEOUT/
/PRIMARY REG ADDRESSING ERROR/
/RECEIVER CONTROL REG DATA £noon.’
/TRANSMITTER CONTROL REG DATA ERROR/
/gnaon REG DATA ERROR/
<377>/SECONDARY REG ADDRESS ERROR/
/SECONDARY REG DATA ERROR/
<377>/REGISTER ADDRESSED/
<377>/EXPECTED RECEIVED REG ADDRESS/
<377>/EXPECTED RECEIVED SEC ADR
SEC REG/

SEQ 0084

CZDQA
MACY11 ;omo
)
19—Ju-7a
CZDQAD.P11
2

4263

020010

001372

020014

001264

4268
4269
& 70
4271
4272
4273
4274
4275
4276
4277
4278

020016
020020
020022
020024
020026
020030
020032
02003¢
020036
020040
020042

000000
010421
o§1042
031463
042104
052525
063146
073567
104210
114631
005212

4280
4281
4282

020046
020050
020052

146314

4265

22229

4279

4283

4284

020012

020044

020054

002

177777

000001

000

H
08:30 PAGE 86
TABLES FOR ERROR MESSAGES.

BYTE

DASEC

2.0

SAVR3

:DATA TABLE FOR SECONDARY REGISTER ADDRESSING TEST

DATAB:

0
10421
1042
1463
42104
50525
63146
73567
104210
114631
5212

146314
0
0

JEND

177777

SEQ 0085

CZDQA
MACYN
(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78
08:52

ABEIT =
ACTBIT=
ADRCNT=
| BABIT =
88BIT =
BINWRD

002000
004000
015261
010000
020000
015600

6104
6114
3862+
6124
o134
3951«

724
7352
3901+
728
719
395

BIT11 = 004000

S94r

1486

FBITO = 000001
BIT1
= 000002
BIT10 = 002000
| BIT12
BIT13
BIT14
BIT15
BITZ2
BITS
BIT4
BITS
BIT6

BIT7
BIT8

= 010000
= 020000
= 040000
= 100000

=
=
=
=
=
=
=
=

000004
000010
000020
000040
000100

000200
000400

605#
604k
595#

5934
592#
591#
590#
2142

6034
6024
6014
6004
599

598#
S97#

104
1232
1458

1515
1549
1577
1605
2175
1016
1260
1288
1316
1344

1372
1402

BIT9
BRW
BRX
CHARDT=
CHAR1
CHARZ

001000
014544
014546
000010
001236
001240

596#
1022
1023
6304
8034
804#

1430
37804
37814

CHKAB1
CHKBA1
CHKBAZ2

012434
340
005170

3197
1512
1761

32204
15364
17894

3949«
1630
1369
864#
8664
8584
1390
1655
8564
8204
69
L6
2331
4031~
4030+
LOOON
1810
3860+
42218
L2214

3953
16544
1389
990
972
3717
15034
1688#
980
944
975
42708
2340
4034
4052
L2708
1825
3898
4223
4226

CHAR3

CHKBA3

001242

005626

CHRCNT 015576
CKBAT
004640
CkBBO
003774
CKSWR = 104414
CNTLU = 104415
CNVRT = 104411
CONT.0 004264
CONT.1
004734
CONVRT= 104410
CREAM
001300
CSRMAP 000220
DATAA = 114631
DATAB
020016
DATABP 016056
DATAHD 016044
DATT
= 125252
DELAY
005524
DEVADR 015256
DHO
017534
DH1
017560

DHZ
017621
DISPRE 000174
DLIGHT= 177570

805#

1791

42214
6
5754

1883

4241
969
951

08:30 PAGE 88
CROSS REFERENCE TABLE == USER SYMBOLS

2394
39104
1536
1389
3991#
1939
197¢
1814
1814
1851

1851
2871
1815
2901

SEQ 0086

3220
1654
2358

1789

1907

2451
2481
2267

2931
2961
2751

3237
3267
3141

299

2811
5241
57
1827
3201

2781

3597
3627
3762
1852
3687

3537
3567

1864

1891

2991
3357
3387
3021
3051
2691
2721

3327
3417

3447
3081
31

3477
3507

1944

1977

2005
1635
1669
1702
1734

2511
2038
2071
2104
2137

1845

1857

3297
2541
2571
2601
2631
2661
2203
2235

3969«

3989

3990

1000

1015

3743

3761

3785

4008

4067

3721

3725

3729

4038

4042

4101

4132

4058
1054

1058+

1067

1068«

1069

1070+

L271R
2371
4056
40554
L271m
1847
39084

4L272r
2380
4059

4273
2412

L2T4R
2421

L27SA
Lc68a

L2768

4277

42728
1862

4LO73M
18704

L2748

4275

Lo76R

L2778

4229
6244

6232

4235

1766
1804

1907#

2170
1820

2010

L2784

2043

2076

2109

CZDQA
MACY11_320A(1052)
19-JuL-78
CZDQAD.P11
27/=JUN-78 08:52
DQACTV
DQCROO
DQCRO1
DOCRO%
DQCRO3
DQCRO4
DAQCROS
DQCRO6
DQCRO7
DAQCR10
DACR11
DQCR12
DAQCR13
DACR14
DQCR1S
DQCR16
DQCR17
DQCSR
DQERR

001500
001400
001404
001410
001414
001420
001424
001430
001434
001440
001444
001450
001454
001460
001464
001470
001474
001506
001366

DANUM
DQRCSH
DQRCSR

001504
001362
001360

DQREG

001370

DQRLVL
DQRVEC
DQSEC

001352
001350
001372

DQSECH
DQSTAT
DASTO0
DQSTO1

DASTOZ2
DQSTO3
DQSTO04
DASTOS
DQSTO6
DQSTO7

001374
001510
001402
001406

001412
001416
001422
001426
001432
001436

670
8914
8934
8954
8974
8994
901#
9034
905#
9074
9094
914
9134
9154
9174
9154
9214
9264
8814
2067
703«
8794
878#
1314
8824

2450%
2840%
3236+
3626%

8754
8744
8834

2662+
2754
2849+
2940
3052«
3144
3245+
3336
3448«
3540
3635«

8844
9274
8924
8944

896#
8984
9004
9024
044
9064

08:30 PAGE 89
CROSS REFERENCE TABLE == USER SYMBOLS

744

750

1067+«
1084

1071
1085+

2100

740
1080
1071~
1342
1086

2480%
2870*
3266+
3656%
1074+«
1072«
1088+

2759+
2850
2962+
3054
3149«
3246
3358+«
3545+
3636
1090+
1069+

2133

745
1081«
1080
1370
1087«

2510
2900+
3296+
3686+

751

1086

755

1048

1050

2231

2263

2295

1204

1218+

1935

1968

2001

2034

1082
1400
1088

1103
1428
1806+

1104
1456
1821=

1182«
1484
1858+

1191
1513
2334%

1192
1547
2342+

1216
1575
2374«

1230
1603
2382%

1258
1631
2415+

1286
3748
2423+

939

1186

998

2199

9254

1144

997+

2166
747

1143

9234

SEQ 0087

3734

2540+
2930%
3326*

2570+
2960
3356+

2600*
2990+
3386%

2630%
3020«
3416%

1075«
1073«
1089

1076
1074
1090

3751
1163

1164

1188+

1211

1219«

1807+

1808+

1809+

1822+

2669+
2760
2872+

2670
2782«
2874
2969+
3060
3172«
3270
3365«
3456
3568«
3660

2692+
2784
2879«
2970
3082«
3174
3275«
3366
3478+«
3570
3665

269
2789+
2880
2992+«
3084
3179«
3276
3388+
3480
3575«
3666

2699+
2790
2902«
2994
3089~
3180
3298«
3390
3485«
3576
3688+

2700
2812+«
2
2999«
3090
3202+

2722«
2814
2909+
3000
3112«

2729«
2820
2932+
3024
3119«
3210
3328«

2730
2842«

2752+
2844
2939+

3395+
3486
3598+«
3690

3508«
3600
3695+

2724
2819«
2910
3022«
3114
3209«
3306
3418~
3510
3605+

1389

1536

1654

1789

1812

1849

3059«
3150
3268«
3360
3455«
3546
3658+«
1091+
1072

2660*
3050+
3446*

2690%
3080*
3476

3305«

2720+«
3110«
3506%

1907

2750+
3140+
3536%

3515«

4263
2358

2780*
3170«
3566*

2810+
3200+
3596+

3029+
3120
3238+
3330
3425«
3516
3628+

3142+
3240
3335+
3426
3538+
30

239

3220

(1052)
CZDQA
MACYN
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

DAsST10
DQST11
DAST1
DAST1
DQST14
DAST1S
DAST16
DQST17

001466

9204

9224

880#

1803

EOPT1
ERRCNT
ERRFLG

ICOUNT
INBUF
INIFLG
INSTER= 104404
INSTR = 104403

INSTR2

JUMBIT= 040000
LIGHTS
LIMITS
LOBITS
LOCK
LOGICA
LOKFLG
LOLIM
LPCNT
LSTERR
MCSRX
MDATA
MEMCLR=
MEPASS
MERRPC
MERRX
MERRZ

MERR3

016661
01
1
0
0
0
O

1078+«
1076«
950

1079+
1077«

7984

945«

2394

942*

4029

4047

4062
4015

L0674
40614

4043
016062

1083

Lo47n
4230
4245
4222
4225
4228
4231
4234
4243
4240

8294

ERTABO

1082«

1844

4224
4227
(242
42218
42218
L2218
42218
L2218
L2218
42218

2368

ERRMSG

MCRLF

SEQ 0088

164
9184

877#
8764
5744

HILIM

908#
9104
9124
9144

DQTCSR

EXITER
HALTS

08:30 PAGE 90
CROSS REFERENCE TABLE == USER SYMBOLS

3859«

40774

1884

423%6

3757

4068+

3711x

40504

39074

3823
8274
8484
8464
3834
6144

3865
966
3884
1026
38494
731

42134
969«

3875
3861«

38894
3893

7834

7934

652
8304
3858

7954
7994
3831
3716
3967
862#

3714

3772

951~

1812

960

39094

3910

3775%
4016

762
994

1062
41694

41854

4032

4046*

4103~

42504

4019~

1849

39064
3772
3710+«
3939

41984

1197

3731«

3891
3771«

3847
4179
3978
4106
41584

1184«

4133

2410«

946+

1124

3776+

2369

4041

3728

3774»

2329x

37384

1123

1078

4233
L2574

3889

7944

1084

1918

42174

L1624

4045

3788

4018+

4139

4104+

L1524

1217+

1665

1698

1730

1762

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27=JUN-78 08:52

08:30 PAGE 9
CROSS REFERENCE TABLE == USER SYMBOLS
-

SEQ 0089

MISC. = 000012
MLOCK
016632

MNEW

016733

MPASSX
MPFAIL
MQM

016675
016442
016434

MTITLE
MISTN
MTSTPC
MVECX
NEXT

001000
016717
016620
016667
001216

MR
016522
MSTCLR= 104412

oDDBIT=
OPT1
OPT2X
ouT

1140*
1512+
1934»

2368«
2777%
3167+
3563+

001000
007240
007554
016374

1160+
1546+
1967+
2409+

1181+

1285+
1664*

1574
2000+
2447

2807+
3197«
3593«

2837+
3233«
3623+

3892

3894

1341+
1729+

2099«
2537«
2927+
3323«
3777

1369+
1761+

2165+
2597*
2987+
3383+

2198+
2627+
3017+

3777+

3778

3413+

41404

PARAM = 104405
PARAM1
015106

3890
3754

1011+

924LH

819#
3914+
3923«

41164

4130

4140»

1035+

1037

1041+

1053«
1057+
1047+

1059~

1066+

3732+

3734

2360+

2361

2396+

2397

3744~

CZDQA
MACY11_30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN-78 08:52

1760+

4208

4096+
977«

4097~
978

42154
982+

g
oo

2556
2946
3342

3006
3402

4074

4095

991
a1

997

1016

1024

3762

3769

1180
1573«
1999«

1228~
1601+
2032+

1256+
1629+

1284~
1663+

13 12 *
16 96 *
21 31 *

1340+
1728+
2164+

4206

3981

3825
3827

4123

3805
3807+

3808
3810«

1368+

3981«

1040+
1426+
1842+

1099+
1454«
1882«

W-

3835

544n
5434
6164
6314
3946
670+
8074
808#
809K
8104
7844
7854
1030
7864
7874
40004
7964

1304
1687
2123

4009

5454

SWi4
= 040000
Sw15 = 100000
SYNBIT= 100000
SYNC. = 000011
TEMP
017114
TEMP1
001244
TEMP2
001246
TEMP3
001250
TEMPG
001252
TEMPS
001254
TKCSR
001204
TKDBR
001206
TLAST = 014160
TPCSR
001210
TPDBR
001212
TRPOK
015614
TSTNO
001226

5524
55714
5504
5,94
5484
54,74
5464

4144

WN=2N

SW13

= 000040
= 000100
= 000400
= 001000
= 002000
= 004000
= 010000
= 020000

4137

PoW
o

SW0S
SW06
SWO8
SW09
SW10
SW11
SW12

973
4069

W—=0

6914
4132
5574
5564
5554
5544
5534

979
4061

3786

SWREG
SWREGC
SW00 =
SW01
=
SW02 =
SW03 =
SW04 =

2526
2916
3312
3702

PNON)
= —
=N
— 00\

1869
2285
2706
3096
3492

84on
6344
3950+
5774
8284
39184
7824

000176
016402
000001
000002
000004
000010
000020

1276
1653
90

1446

SCOP1 = 104401
SEQ.
= 000014
SPACNT= 015577
STACK = 001200
STFLG
001311
SVOS
015270
SWR
001200

SEQ 0090

3922+

—y

SCOPE = 104400

8124
81
8144
8154
8164
8174
8524
840#

001260
001262
001264
001266
001270
001272
104406

Own—=

SAVR]
SAVR?
SAVR3
SAVRG
SAVRS
SAVSP
SAVOS =

M7
08:30 PAGE 92
CROSS REFERENCE TABLE == USER SYMBOLS

2065+

2098+

)

CZDGA
MACY11 30A(1052)
19-JuL-78
CZDQAD.P11
27-JUN~-78 08:52

TST1
TST1I0
TST100
TST101
TST102
TST103
TST104
TST105
TST106
TST107

TST11
TST110
TST111
TST112
TST113
TST114
TST11S
TST116

002254
003440
011624
011774
012004
012074
012164
012254
012344
012450

003514
012540
012630
012720

013010
013100
013170
013260
TST117 013350
TST12
003570
TST120 013440
TST121
013530
TST122 013620
| TST123 013710
TST124
014000
TST125
014070
TST126 014160
TST127= sxnsnx |J
TST13
003644
TST14
003720
TST15
004004
TST16
004060
TST17
004134
TST2
002644
TST20
004210
TST21
004264
1ST22
004350
TST23
004424
TST24

TST2S
1ST26
TST27
TST3
TST30
TST31
1ST32
TST33
1ST3
1ST35
1ST36
1ST37
1ST14

004500

004554
004650
004734
002730
005020
005104
005204
005366
005540
0056
005674

005764
003014

2197+
2626
3016
3612«

1029
1229
2987
3017
3047
3077
2107
3137
3167
3221

1257
3233
3263
3293

3323
3353
3383
3413

3443
1285
3473
3503
3533
3563

3593
3623
3653
3222
1313
1341
13984
1399
1427
1041
1455
1483
15454

2229+
2656+
3046+
3442«

1035
12564
307164
30464
30764
31064
31364
31664
31964
32324

10408

34724
13124
35024
35324
35624
35904
36224
36524
3682#
3683
13404
13684

14264
14544
1042
14824
15114

15734

1602
16634
1664
1100
1697
1729
18014
1802
1843
19164
1908

16294

1934
1120

2261+
686+
076*
3472«

12844
32624
32924
3322#
33524
33824
34124
34404

1546

1537

1574

3704

10994

16014

16964
1119#
17284
17604

18424

18824

1917

08:30 PAGE 93
CROSS REFERENCE TABLE == USER SYMBOLS

19664
11308

19334

2293x
716%
106*
3502«
3744

2327x
746%
136%
3532«
3745

2367+
776%
166*
3562«

2408%
2806%
3196%
3592+

SEQ 0091

44bx
2836+
3232«
3622+

2476%
%866'
262
3652+

2506%
896*
292*
3682+

2536%
2926*
3322«
4082

2566%
2956%
3350«
4110

2596+
2986+
3380+

MACY

27=JUN- 08:52

006292

i,
e

8%
s

18
1

C%.P‘H

)

19-JuL~-78

08:30

PAGE 94
CROSS REFERENCE TABLE == USER SYMBOLS

15140

TST45
1ST4

TST
TST53

14
o
gg‘

7114
007

TST54

0074

TST55

4084

0075

409

L4068

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