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AH-8545D-MC

October 1985

128 pages

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Document:	CZDMCD0 DMC11 DMC11 BSC W-R UPROC OCT 1985 bw
Order Number:	AH-8545D-MC
Revision:	000
Pages:	128
Original Filename:	CZDMCD0__DMC11__DMC11_BSC_W-R_UPROC__AH-8545D-MC__OCT_1985_gray.pdf

OCR Text

DMC11 BSC WR UPROC ~

CZDMCDO

AH-8545D-MC

10F1 OCT 1985

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MADE IN USA

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MACRO V04.00

27-JUN-85 13:16:37 PAGE 1

.REM

SEQ 1

[

IDENTIFICATION
PRODUCT CODE:

AC-8544D-MC

PRODUCT NAME:

CZDMCDO DMC11 BSC W/R UPROC

DATE:

17-JUN-1985

MAINTAINER:

MK NAC SOFTWARE ENGINEERING

AUTHOR:

BRUCE LUHRS

THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT

NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION.
DIGITAL EQUIPMENT CORPORATION ASSUMES
NO RESPONSIBILITY FOR ANY ERRORS THAT MAY APPEAR IN THIS
DOCUMENT.
NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF
SOFTWARE
ON
EQUIPMENT THAT IS NOT SUPPLIED BY DIGITAL OR
ITS
AFFILIATED

COMPANIES

1978,

1985 BY DIGITAL EQUIPMENT CORPORATION

MACRO v04.00

= -

COV®IPTVID
N

czomC

SEQ 2

27-JUN-85 13:16:37 PAGE 2

ABSTRACT
THE FUNCTION OF THE DMC11 DIAGNOSTICS IS TO
VERIFY
THAT
THE
OPTION
OPERATES ACCORDING TO SPECIFICATIONS.
THE DIAGNOSTICS
VERFIY THAT THERE ARE NO MALFUNCTIONS AND THE
ALL
OPERATIONS
OF THE DMC11 ARE CORRECT IN ITS ENVIRONMENT.
PARAMETERS MUST BE SET UP TO

ALERT

THE

DIAGNOSTICS

THE

DMC11
CONFIGURATION.
THESE
PARAMETERS ARE CONTAINED IN THE
STATUS
TABLE
AND
ARE GENERATED
IN
TWO
WAYS:
1)
MANUAL
INPUT - THE
OPERATOR
ANSWERS QUESTIONS.
2) AUTOSIZING - THE
PROGRAM DETERMINES THE PARAMETERS AUTOMATICALLY.
CZDMC TESTS THE DMC11 MICRO-PROCESSOR (M8200-YA OR
M8200-YB).
IT
PERFORMS
WRITE/READ
TESTS
ON
THE DMC UNIBUS REGISTERS,
CHECKS THE MICRO-PROCESSOR OPERATION, CHECKS OUT MAIN MEMORY,

SCRATCH

PAD

MEMORY,

AND NPR OPERATION.

THE ALU FUNCTIONS AS WELL AS INTERRUPTS

CZDMC PERFORMS NO TESTS ON THE

LINE

UNIT

OR
ANY CROM DEPENDENT TESTS.
IT DOES NOT REQUIRE A LINE UNIT
TO RUN.
NOTE:
THIS DIAGNOSTIC WILL RUN ON A
KMC11
(M8204),
HOWEVER
IT
IS
NOT
ADVISED
THAT THIS DIAGNOSTIC BE USED TO
CHECK A KMC11, RATHER YOU SHOULD CHECK A KMC11 WITH THE KMC11
DIAGNOSTIC PACKAGE.
CURRENTLY THERE ARE FIVE OFF LINE DIAGNOSTICS THAT ARE
TO
BE
RUN 1IN SEQUENCE
TO
INSURE THAT IF AN ERROR SHOULD OCCUR IT
WILL BE DETECTED AT AN EARLY STAGE.

NOTE:

ADDITIONAL DIAGNOSTICS MAY BE ADDED IN THE FUTURE.

THE FIVE DIAGNOSTICS ARE:

1.
2.
3.
4.
5.

CZDMC
CZOME
DZDMF
DZDMG
DZDMH

[REV]
[REV)
[REV]
[REV]
[REV]

BASIC W/R AND MICRO-PROCESSOR TESTS
DDCMP MODE LINE UNIT TESTS
BITSTUFF LINE UNIT TESTS
JUMP AND CROM TESTS
FREE-RUNNING TESTS (HEAT TEST TAPE)

REQUIREMENTS
EQUIPMENT
ANY PDP11 FAMILY CPU (EXCEPT AN LSI-11) WITH MINIMUM 8K MEMORY
ASR 33 (OR EQUILIVALENT)
DMC11-AR (M8200-YA) OR A DMC11-AL (MB200-YB)

CZoMC
O® IOV
N -

MACRO V04.00

SEQ 3

27-JUN-85 13:16:37 PAGE 3

2.2

STORAGE
PROGRAM WILL USE

BOOTSTRAP

LOADER

ALL

RESIDE.

MEMORY

EXCEPT

WHERE

LOCATIONS 1500 THRU 1640;

ABL

AND

CONTAIN

THE “STATUS TABLE” INFORMATION WHICH IS GENERATED AT START
OF
DIAGNOSTICS
BY
MANUAL
INPUT
(QUESTIONS)
OR
AUTOMATICALLY

(AUTO-SIZING).
THIS AREA IS AN OVERLAY AREA AND SHOULD NOT BE
ALTERED BY THE OPERATOR.

LOADING PROCEDURE
METHOD
ALL PROGRAMS ARE IN ABSOLUTE FORMAT AND ARE LOADED
USING
THE
ABSOLUTE LOADER.
NOTE: IF THE DIAGNOSTICS ARE ON A MEDIA SUCH

" AS DISK ,MAGTAPE,DECTAPE, OR
FOSI“TFE
MEDIA.

MONITOR

WHICH

HAS

CASSETTE;
BEEN

INSTRUCTIONS

PROVIDED ON THAT SPECIFIC

ABSOLUTE LOADER STARTING ADDRESS %500
MEMORY

& SIZE

4K
8K

12K

17
37
57

20K

117

16K

24K
28K

137
157

3.1.1

PLACE ADDRESS OF ABS LOADER INTO SWITCH REGISTER.
(ALSO PLACE ‘HALT' SW UP)

3.1.2

DEPRESS 'LOAD ADDRESS’

3.1.3

DEPRESS ’'START KEY' ON CONSOLE AND RELEASE (PROGRAM SHOULD NOW
BE LOADING INTO CPU)

KEY ON CONSOLE AND RELEASE.

—

CZoMC

MACRO V04.00

VR IRV DN -

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SEQ 4

27-JUN-85 13:16:37 PAGE 4

STARTING PROCEDURE
A.
B.
C.

SET SWITCH REGISTER TO 000200
DEPRESS ‘LOAD ADDRESS' KEY AND RELEASE
SET SWR TO ZERD FOR 'AUTO SIZING' OR SWR BITO=1 FOR MANUAL
INPUT (QUESTIONS) OR SWR BIT7=1 TO USE EXISTING PARAMETERS
SET UP BY A PREVIOUS
START
OR
A
PREVIOUSLY
RUN
DMC11
DIAGNOSTIC.
DEPRESS 'START KEY’' AND RELEASE.
THE
PROGRAM
WILL
TYPE
MAINDEC NAME AND PROGRAM NAME (IF THIS WAS THE FIRST START
UP OF THE PROGRAM) AND ALSO THE FOLLOWING:
MAP OF DMC11 STATUS

CSR

STAT1

001500 160010 145310
01510 160020 145320

STAT2

STAT3

177777
177777

000000
000000

THE PROGRAM WILL TYPE ‘R’ AND PROCEED TO RUN
THE
DIAGNOSTIC.
THE
ABOVE IS ONLY AN EXAMPLE.
THIS WOULD INDICATE THE STATUS
TABLE STARTING AT ADD.
1500 IN THE PROGRAM.
IN THIS
EXAMPLE
THE
TABLE CONTAINS THE INFORMATION AND STATUS OF TWO DMC11'S.
THE STATUS TABLE MUST BE VERIFIED BY THE USER IF
AUTO
SIZING
EESLPDOIE.
FOR INFORMATION OF STATUS TABLE SEE SECTION 8.4 FOR

IF THE DIAGNOSTIC WAS STARTED WITH

PARAMETER

INPUT

THEN

THE

SW00=1

INDICATING

MANUAL

FOLLOWING SHOWS AN EXAMPLE OF THE

QUESTIONS ASKED AND SOME EXAMPLE ANSMWERS:

HOW MANY DMC11'S TO BE TESTED?1
01

CSR ADDRESS?160010
VECTOR ADDRESS?310
BR PRIORITY LEVEL?
(4,5,6,7)?5
DOES MICRO-PROCESSOR HAVE CRAM? (Y OR N)N
WHICH LINE UNIT?
1IF NONE TYPE “N”,
IF M8201
MB202 TYPE “2*?1
IS THE LOOP BACK CONNECTOR ON?Y
SWITCH PAC®1 (DDCMP LINE®)?377
SWITCH PACé2 (BM873 BOOT ADD)?377

TYPE

“1”,

FOLLOWING THE QUESTIONS THE STATUS MAP
IS PRINTED OUT
AS
DESCRIBED ABOVE,
THE
INFORMATION IN THE MAP REFLECTS THE
ANSWERS TO THE QUESTIONS.
IF THE DIAGNOSTIC WAS STARTED
WITH
SW00=0 AND SWO7=0 (AUTO-SIZING) THEN NO QUESTIONS ARE ASKED
AND ONLY THE STATUS-MAP IS PRINTED
OUT.
IF
AUTO-SIZING
IS

USED

THE

STATUS

INFORMATION

MUST BE VERIFIED TO BE CORRECT

(MATCH THE HARDWARE).
IF IT DOES NOT MATCH THE HARDWARE THE
%gfigglc MUST BE RESTARTED WITH SWO00=1 AND THE QUESTIONS

SEQ
5

27-JUN-85 13:16:37 PAGE 4-1

CONTROL SWITCH SETTINGS

[

SW 15 SET:
SW 14 SET:
SW 13 SET:
SET:
SET:
SET:
SET:
SET:
SET:

82R&RG 8388sk n

4.1

PeReee £

58
59
60
61
62
63
64
65
66
67
68
69
70
Fi
72
73
74
75
76
77
78
79
80
81
82
83
84
85

MACRO V04.00

CeeEPR

CZoMC

SET:

SET:
SET:
SET:
SET:
SET:
SET:

HALT ON ERROR
LOOP ON CURRENT TEST
INHIBIT ERROR PRINT OUT
INHIBIT TYPE OUT/ABELL ON ERROR.
INHIBIT ITERATIONS.
(QUICK PASS)
ESCAPE TO NEXT TEST ON ERROR
LOOP WITH CURRENT DATA
CATCH ERROR AND LOOP ON IT
USE PREVIOUS STATUS TABLE.

HALT IN

ROMCLK

ROUTINE

BEFORE

CLOCKING

MICRO-PROCESSOR
RESERVED
RESERVED
RESELECT DMC11'S DESIRED ACTIVE
LOCK ON SELECTED TEST
RESTART PROGRAM AT SELECTED TEST
BUILD NEW STATUS TABLE FROM QUESTIONS.
(IF SW07=0
AND
SWO0=0
A
NEW
STATUS
TABLE
IS
BUILT BY
AUTO-SIZING)

SWITCH 06 AND 08-15 ARE DYNAMIC AND CAN BE CHANGED
AS
NEEDED
WHILE THE DIAGNOSTIC IS RUNNING.
SWITCHES 00-03 AND SWITCH 07

325@5;;;%%. AND ARE USED ONLY ON STARTING

RESTARTING

THE

CZoMC
VRNOWVD
LN -

MACRO vV04.00

SEQ 6

27-JUN-85 13:16:37 PAGE 5

4.1.2

SHITCH REGISTER OPTIONS (AT START UP)

SW 01

RESTART PROGRAM AT
SELECTED
TEST.
IT
IS
STRONGLY
SUGGESTED
THAT AT LEAST ONE PASS HAS BEEN MADE BEFORE

TRYING TO SELECT A TEST, THE REASON BEING IS THAT

THE

PROGRAM
HAS
TO
CLEAR
AREAS
AND SET UP PARAMETERS.
WHEN THIS SWITCH IS USED THE DIAGNOSTIC WILL ASK
TEST
NO.?
ANSMER BY TYPING THE NUMBER OF THE TEST DESIRED
?E‘g'[CARRIGE RETURN TO BEGIN EXECUTION AT THE
SELECTED

Sk 02

LOCK ON SELECTED TEST.
THIS
SWITCH
WHEN
USED
WITH
SWO1
WILL CAUSE THE PROGRAM TO CONSTANTLY LOOP ON THE

SELECTED TEST.
HITTING ANY KEY ON
THE
CONSOLE
WILL
LET
IT
ADVANCE TO THE NEXT TEST AND LOOP UNTIL A KEY
IS HIT AGAIN.
IF
SWO2=0 WHEN SWO1
IS
USED.
THE
PROGRAM
WILL
BEGIN AT THE SELECTED TEST AND CONTINUE
NORMAL OPERATIONS.

SW 03

RESELECT DMC11'S DESIRED ACTIVE.
PLEASE NOTE
THAT
A
MESSAGE
IS
TYPED OUT FOR SETTING THE SWITCH REGISTER
EQUAL TO DMC11'S ACTIVE.
THIS MEANS IF THE SYSTEM HAS

FOUR

DMC11S;

BITS

00,01,02,03

WILL

BE SET IN LOC

'DMACTV'
FROM
THE
SWITCH REGISTER.
USING
THIS
SWITCH(SWOO)
ALTERS
THAT
LOCATION; THEREFORE IF FOUR
DMC11S ARE IN THE SYSTEM ##+D0 NOT+s+
SET SWITCHS
GREATER
THAN SW 03 IN THE UP POSITION.
THIS WOULD BE
A FATAL ERROR.
DO NOT SELECT MORE ACTIVE DMC11S
THAN
THERE IS INFORMATION ON IN THE STATUS TABLE.

METHOD
: A:
8:
€:
D:

€:
F:

LOAD ADDRESS 200
START WITH SW 00=1

PROGRAM WILL TYPE MESSAGE
SET A SWITCH FOR EACH DMC DESIRED ACTIVE.
EXAMPLE:
IF YOU HAVE 4 DMC'S BUT ONLY WANT TO
RUN THE FIRST AND THE LAST SET SWR BITS O AND
3 = 1.
PRESS CONTINUE
NUMBER (IF
VALID)
WILL
BE
IN DATA LIGHTS
(EXCLUDING 11/05)

SET WITH ANY OTHER

PRESS CONTINUE.

SWITCH

SETTINGS

DESIRED.

SEQ
7

27-JUN-85 13:16:37 PAGE 6

4.1.3

DYNAMIC SWITCHES
ERROR SWITCHES

M&?‘ND‘

MACRO V04.00
VR NOVEWN
-

CZDMC

SW
SW
SW
SW
SW

12
13
15
08
10

DELETE PRINT OUT/BELL ON ERROR.
DELETE ERROR PRINTOUT.
HALT ON THE ERROR.
GOTO BEGINNING OF THE TEST(ON ERROR).
GOTO NEXT TEST(ON ERROR).

SCOPE SWITCHES
1.

SWo06

SW09

3.
4.
4.2

SWi1
SWi14

HALT
IN
ROMCLK
ROUTINE
BEFORE
CLOCKING
MICRO-PROCESSOR
INSTRUCTION.
THIS
ALLOWS
THE
OPERATOR TO SCOPE A MICRO-PROCESSOR INSTRUCTION IN
THE
STATIC
STATE
BEFORE
IT
IS
CLOCKED.
HIT
CONTINUE TO RESUME RUNNING.
(IF ENABLED BY 'SCOP1’') ON AN ERROR;
IF AN ‘s’ IS
PRINTED
1IN FRONT OF THE TEST NO.
(EX.
&TEST NO.
10
)
SWO9
IS
INCORPORATED
IN THAT
TEST
AND
THEREFORE
SWO09 IS USUALLY THE BEST SWITCH FOR THE
SCOPE LOOP (SW14=0, SW10=0, SW09=1,
SW08=0).
1IF
SW09
IS
NOT ENABELED;
AND THERE IS A HARD ERROR

(CONSTANT);
SWO8 IS BEST.
(SW14=1,0,
SW10=0,
SW09=0, SWO08=1).
FOR INTERMITTEMT ERRORS;
SWi4=1
WILL LOOP ON TEST
REGUARDLESS
OF
ERROR
OR NOT
ERROR.
(SW14=1, SW10=0, SW09=0, SW08=1,0)
INHIBIT INTERATIONS.
LOOP ON CURRENT TEST.

STARTING ADDRESS

STARTING ADDRESS IS AT 000200

THERE

ADDRESSES FOR THE DMC11 DIAGNOSTICS.
NOTE:

ARE

OTHER

STARTING

(SEE SECTION 4.0)

IF ADDRESS 000042 IS NON-ZERO THE PROGRAM ASSUMES
IT
IS
UNDER
ACTi1I
OR
XXDP
CONTROL
AND MWILL
ACT
ACCORDINGLY AFTER ALL AVAILABLE DMC11‘'S ARE TESTED THE
PROGRAM WILL RETURN TO ‘XXDP’' OR 'ACT-11'.

OPERATING PROCEDURE

WHEN PROGRAM IS INITIALLY STARTED MESSAGES AS DESCRIBED IN
SECTION 4.0 WILL BE PRINTED, AND PROGRAM WILL BEGIN RUNNING
THE DIAGNOSTIC

CZomMC

SEQ
&

27-JUN-85 13:16:37 PAGE 7

PROGRAM AND/OR OPERATOR ACTION

THE TYPICAL APPROACH SHOULD BE

3
2.
3.
4.

n 5 et e e ph e e e e
o

OCNO“.NN“OODQOMOGNO‘

MACRO V04.00

HALT ON ERROR (VIA SW 15=1) WHEN EVER AN ERROR OCCURS.
CLEAR SW 15.
SET S4 14:
(LOOP ON THIS TEST)
SET SW 13:
(INHIBIT ERROR PRINT OUT)

THE TEST NUMBER AND PC WILL BE
TYPED
OUT
AND
POSSIBILY
AN
ERROR MESSAGE (THIS DEPENDS ON THE TEST) TO GIVE THE OPERATOR
AN IDEA AS TO THE SOURCE OF THE PROBLEM.
IF IT
IS
NECESSARY

TO KNOW MORE INFORMATION CONCERNING THE ERROR REPORT;
LOOK IN
THE LISTING FOR THAT TEST NUMBER WHICH WAS TYPED OUT AND
THEN
NOTE THE PC OF THE ERROR REPORT THIS WAY THE EXACT FUNCTION OF
THE TEST CAN BE DETERMINED.

ERRORS
AS DESCRIBED PREVIOUSLY THERE WILL ALWAYS BE A TEST NUMBER AND
PC TYPED OUT AT THE TIME OF AN ERROR (PROVIDING SW 13=0 AND SW
12=0).
IN MOST CASES ADDITIONAL INFORMATION WILL BE
SUPPLIED
%&Tg"g‘i ERROR MESSAGE TO GIVE THE OPERATOR AN INDICATION OF
6.2

ERROR RECOVERY
IF FOR SOME REASON THE
DMC1i
SHOULD
'HANG
THE BUS'
(GAIN
CONTROL OF BUS SO THAT CONSOLE MANUAL FUNCTIONS ARE INHIBITED)
AN INIT OR POMER DOWN/UP IS NECESSARY FOR OPERATOR
TO REGAIN
CONTROL OF CPU.
IF
THIS
SHOULD HAPPEN;
LOOK IN LOCATION
‘TSTNO' (ADDRESS 1226)FOR THE NUMBER
OF
THE
TEST
THAT
WAS
RUNNING AT
THE
TIME OF THE CATASTROPHIC ERROR.
IN THIS WAY
THE OPERATOR WILL HAVE AN IDEA AS TO WHAT THE DMC11 WAS DOING
AT THE TIME OF THE ERROR.
RESTRICTIONS

STARTING RESTRICTIONS

SEE SECTION 4.
(PLEASE)
STATUS TABLE SHOULD BE VERIFIED REGUARDLESS OF HOW PROGRAM WAS
STARTED.
ALSO IT IS IMPORTANT TO USE THIS LISTING ALONG WITH
%&fgfinnm PRINTED
ON THE TTY
TO COMPLETLY ISOLATE

MACRO V04.00
VRN
VID N -

CZoMC

SEQ 9

27-JUN-85 13:16:37 PAGE 8

7.2

OPERATING RESTRICTIONS
THE FIRST TIME A DMC11 DIAGNOSTIC IS LOADED INTO CORE AND RUN
THE STATUS TABLE MUST BE SET UP.
THIS IS DONE BY MANUAL INPUT
(SW00=1) OR BY AUTOSIZING
(SWO0=0
AND
SWO07=0).
THEREAFTER
HOWEVER
THE
STATUS
TABLE
NEED
NOT
BE SETUP BY SUBSEQUENT
RESTARTS OR EVEN LOADING THE NEXT DMC DIAGNOSTIC
BECAUSE
THE
STATUS
TABLE
IS
OVERLAYED.
THE
CURRENT PARAMETERS IN THE
STATUS TABLE ARE USED WHEN SWO7=1 ON START UP.

7.3

HARDWARE CONFIGURATION RESTRICTIONS

DMC11(MB8200)- JUMPER W1 MUST BE IN, AND SWITCH 7 OF
BE IN THE OFF POSITION.

E76

MUST

KMC(M8204)- JUMPER W1 MUST BE IN.
MISCELLANEOUS
EXECUTION TIME

ALL DMC1i DEVICE DIAGNOSTICS WILL GIVE AN '‘END
PASS’'
MESSAGE
(PROVIDING NO ERRORS
AND SW12=0)
WITHIN 4 MINS.
THIS IS
ASSUMING SWil=1 (DELETE ITERATIONS) IS SET TO GIVE THE FASTEST
POSSIBLE EXECUTION.
THE ACTUAL EXECUTION TIME DEPENDS GREATLY
‘S’Y‘S;’EEH PDP11 CPU CONFIGURATION AND THE AMOUNT OF MEMORY IN THE
8.2

PASS COMPLETE

NOTE:
EVERY TIME THE PROGRAM IS STARTED;
THE TESTS WILL RUN
AS
IF
SWi1l
(DELETE
ITERATIONS)
WAS UP
(=1).
THIS IS TO
'VERIFY NO HARD ERRORS' AS SOON AS
POSSIBLE.
THEREFORE
THE

FIRST

PASS

-EACH

TIME

PROGRAM IS STARTED- WILL BE A ‘QUICK

PASS' UNTIL ALL DMC11'S
IN SYSTEM ARE TESTED.
WHEN THE
DIAGNOSTIC HAS COMPLETED A PASS THE FOLLOWING IS AN EXAMPLE OF
THE PRINT OUT TO BE EXPECTED.

END PASS CZDMC CSR:
ERRORS:
000000
NOTE:

175000 VEC:

0300 PASSES:

000001

THE PASS COUNT AND ERROR COUNTS ARE CUMMULITIVE FOR
EACH DMC11 THAT IS RUNNING, AND ARE SET TO ZERO ONLY
WHEN THE DIAGNOSTIC IS STARTED.
THEREFORE
AFTER
AN
OVERNIGHT RUN FOR EXAMPLE, THE TOTAL PASSES AND ERRORS

FOR EACH DMC11 SINCE THE DIAGNOSTIC

REFLECTED IN PASSES:

AND ERRORS:.

WAS

STARTED

ARE

CZOMC
VR NOVD
NN -

MACRO V04.00

SEQ 10

27-JUN-85 13:16:37 PAGE 9

8.4

KEY LOCATIONS

8.4A

RETURN (1214)

CONTAINS THE ADDRESS WHERE PROGRAM WILL RETURN
WHEN
ITERATION COUNT IS REACHED OR IF LOOP ON
TEST IS ASSERTED.

(1216)

CONTAINS THE ADDRESS OF THE NEXT
PEFORMED
.

TSTNO

(1226)

RUN

(1316)

CONTAINS THE NUMBER

PEFORMED
.

THE BIT IN '‘RUN’'

THE

TEST

NOW

BEING

THE

DMC11

ALWAYS POINTS

CURRENTLY
BEING
TESTED.
EXAMPLE:
1302/0000000001000000 MEANS THAT
DMC11
IS THE DMC11 NOW RUNNING.

(RUN)
NO.06

DMCROO-DMCR17
DMSTO0-DMST17

(1500)-(1640)

THESE LOCATIONS CONTAIN THE INFORMATION NEEDED
TO TEST UP TO 16 (DECIMAL) DMC11S SEQUENTIALY.
THEY
CONTAIN
THE
CSR,VECTOR
AND
STATUS
CONCERNING THE CONFIGURATION OF EACH DMC11.

DMACTV (1306)

EACH BIT SET IN THIS LOCATION INDICATES
THAT
THE
ASSOCIATED
DMC11 WILL BE TESTED IN TURN.
EXAMPLE:
(DMACTV) 1276/0000000000011111 MEANS
THAT DMC11 NO.
00,01,02,03,04 WILL BE TESTED.
EXAMPLE:
(DMACTV) 1276/0000000000010001 MEANS
THAT DMC11 NO.
00,04 WILL BE TESTED.

DMCSR

gg’s{}ufls THE CSR OF THE

(1404)

*'STATUS TABLE'

CURRENT

DMC11

UNDER

(1500-1640)

THE TABLE IS FILLED BY AUTO SIZING OR BY THE MANUAL
PARAMETER
INPUT (QUESTIONS) AS DESCRIBED PREVIOUSLY.
ALSO IF DESIRED BY
USER;
THE LOCATIONS MAY BE ALTERED BY HAND
(TOGGLED IN)
TO

SUIT THE SPECIFIC CONFIGURATION.

THE EXAMPLE STATUS MAP SHOWN BELOW CONTAINS
INFORMATION FOR
TWO DMC11°'S.
THE
TABLE
CAN CONTAIN UP
TO
16
DMC11'S.
g#ioums THE MAP IS A DESCRIPTION OF THE BITS FOR EACH MAP
(8

MAP OF DMC11 STATUS
-------------------

CSR

STAT1

001510 160020 016320

STAT2

STAT3

000000

CZDMC

MACRO V04.00

SEQ 11

27-JUN-85 13:16:37 PAGE 9-1

59
60

EACH MAP ENTRY CONTAINS
~
INFORMATION
FOR
1
DMCil.

THE

FIRST

THE

WORDS

IS.

wORDS
WHICH
CONTAIN
THE
STATUS
THE PC SHOWS WHERE IN CORE MEMORY

DMC’'S STATUS IS IN LOCATIONS,

63
64
52

THE

1500,

EXAMPLE

1502,

CSR:

CONTAINS DMC11 CSR ADDRESS

STAT1:

BITS 00-08 IS DMCi1 VECTOR ADDRESS
BIT15=1 MICRO-PROCESSOR HAS CRAM

BIT15=0 MICRO-PROCESSOR HAS CROM

BIT14=1 TURNAROUND CONNECTOR IS ON

BIT13=0 LINE UNIT IS AN M8201

FIRST

THE

BIT14=0 NO TURNAROUND CONNECTOR

BIT13=1 LINE UNIT IS AN M8202

;;I

THE

SECOND DMC STATUS IS LOCATED AT 1510, 1512,
1514,
AND
1516.
THE
INFORMATION
CONTAINED IN EACH 4 WORD ENTRY IS DEFINED AS
FOLLOWS:

6
67
68
69
70

ABOVE

1504, AND 1506.

BITS 09-11 IS DMC1i1 BR PRIORITY LEVEL

STAT2:

LOW BYTE IS SWITCH PAC#1 (DDCMP LINE NUMBER)

STAT3:

BITO=1 RUN FREE RUNNING TESTS ON KMCi1

HIGH BYTE IS SWITCH PAC#2 (BM873 BOOT ADD)

BIT1=0 DMC11-AR (LOW SPEED)

L
b*

BIT12=1 NO LINE UNIT

BITi=1 DMC11-AL (HIGH SPEED)

e ————————————————

MACRO V04.00
VRNV
D NN -

CZOMC

SEQ 12

27-JUN-85 13:16:37 PAGE 10

8.5

METHOD OF AUTO SIZING

8.5.1

FINDING THE CONTROL STATUS REGISTER.

THE AUTO-SIZING ROUTINE FINDS A DMC11 AS FOLLOWS:
IT
STARTS
AT ADDRESS 160000 AND TESTS ALL ADDRESS IN INCREMENTS OF 10 UP
TO AND INCLUDING ADDRESS 167760.
IF THE ADDRESS DOES NOT TIME
OUT,
THE FOLLOWING IS DONE, THE FIRST CROM ADDRESS IS WRITTEN
TO A 125252 THEN IT IS READ BACK.
IF
IT
CONTAINS A
-1
OR
125252
OR 626 OR
16520 A DMCi1 OR KMC1i1 HAS BEEN FOUND, IF
NOT, THE ADDRESS IS UPDATED BY 10 AND THE SEARCH CONTINUES.
A
-1
INDICATES A DMC11 WITH NO CROM, A 125252 INDICATES A KMC11
WITH CRAM, A 626 INDICATES A DMC11-AL AND A 16520 INDICATES
A

DMC11-AR.

FURTHER

TESTS

ARE

PERFORMED

THIS

POINT TO

DETERMINE
WHICH
LINE
UNIT,
IF
ANY,
IS
INSTALLED,
IF
A
LOOP-BACK CONNECTOR
IS INSTALLED AND VARIOUS SWITCH SETTINGS
ON THE LINE UNIT.
THIS
IS
WHY
THE
STATUS
TABLE
MUST
BE
VERIFIED BY
THE USER AND IF ANY OF THE INFORMATION DOES NOT
AGREE WITH THE HARDWARE THE DIAGNOSTIC MUST BE
RESTARTED
AND
THE
QUESTIONS
MUST
BE
ANSWERED.
ALL DMC11'S IN THE SYSTEM
WILL BE FOUND BY THE AUTO-SIZER.
IF IT DOES NOT FIND A
DMC11
THE DIAGNOSTIC MUST BE RESTARTED AND THE QUESTIONS ANSWERED.

8.5.2

FINDING THE VECTOR AND BR LEVEL
THE

VECTOR

AREA

(ADDRESS

300-776)

FILLED

WITH

THE

INSTRUCTION IOT
AND
‘.+2'
(NEXT
ADDRESS).
THE PROCESSOR
STATUS IS STARTED AT 7 AND THE DMC IS PROGRAMMED TO INTERRUPT.
THE PS
IS LOWERED BY 1 UNTIL THE OMC INTERRUPTS, A DELAY IS

MADE AND IF NO INTERUPT OCCURES AT PS LEVEL 3

(BECAUSE

BAD DMC11) THE PROGRAM ASSUMES VECTOR ADDRESS 300 AT BR LEVEL
S AND THE PROBLEM SHOULD BE FIXED IN THE DIAGNOSTIC.
ONCE THE
PROBLEM IS FIXED;
THE PROGRAM SHOULD BE RE-SETUP AGAIN TO GET
CORRECT VECTOR.
IF AN INTERUPT OCCURED;
THE ADDRESS TO WHICH
THE DMC11
INTERUPTED
TO
IS PICKED
UP AND REPORTED AS THE
VECTOR.
NOTE:
IF THE VECTOR REPORTED IS NOT THE VECTOR SET
UP BY
YOU;
THERE IS A PROBLEM AND AUTO SIZING SHOULD NOT BE
8.6

SOFTWARE SWITCH REGISTER
IF THE DIAGNOSTIC IS RUN ON AN 11/04 OR OTHER CPU MWITHOUT
A
SWITCH REGISTER THEN A SOFTWARE SWITCH REGISTER IS USED TO
ALLOW USER THE SAME SWITCH OPTIONS
AS
DESCRIBED PREVIOUSLY.
IF
THE HARDWARE SWITCH REGISTER DOES NOT EXIST OR IF ONE DOES
AND IT
CONTAINS
ALL
ONES
(177777)
THIS
SOFTWARE
SWITCH
REGISTER IS USED.

CONTROL:
TO OBTAIN CONTROL AT ANY ALLOWABLE TIME DURING EXECUTION OF
THE DIAGNOSTIC
THE
OPERATOR
TYPES
A CTRL G ON THE CONSOLE
TERMINAL KEYBOARD.
AS SOON AS THE CTRL G IS RECOGNIZED,
BY
THE DIAGNOSTIC, THE FOLLOWING MESSAGE WILL BE DISPLAYED:

CZOMC

59
60
61

62
63

65
66
67
68
69
70

71
72
73

74
75
76
77
78
79

MACRO V04.00

SEQ 13

27-JUN-85 13:16:37 PAGE 10-1

SHR=XXXXXX NEW?
WHERE XXXXXX IS THE CURRENT CONTENTS OF
THE
SOFTWARE
SWITCH
REGISTER
IN
OCTAL.
THE
SOFTWARE CONTROL ROUTINE WILL THEN
AWAIT OPERATOR ACTION.
AT WHICH TIME THE OPERATOR IS REQUIRED
TO
TYPE
ONE
OR_ MORE OF THE LEGAL CHARACTERS:
1) 0 - 7, 2)
LINE FEED(<LF>), 3) CARRIAGE
RETURN(<CR>),
OR
4)
CONTROL-U
(CTRL U).
NO CHECK
IS
MADE
FOR LEGALITY.
IF THE INPUT
CHARACTER IS NOT A <LF>, <CR>, OR CTRL U IT IS ASSUMED
TO
BE
AN OCTAL DIGIT.

TO CHANGE THE CONTENTS OF THE SSR THE
OPERATOR
SIMPLY
TYPES
THE NEW DESIRED VALUE
IN OCTAL - LEADING ZEROS NEED NOT BE
TYPED.
AND TERMINATES THE INPUT STRING WITH A
<CR>
OR
<LF>
DEPENDING
ON THE
PROGRAM ACTION DESIRED AS DESCRIBED BELOW.
THE INPUT VALUE WILL BE TRUNCATED TO THE LAST 6 DIGITS
TYPED.
AT
LEAST_ ONE
DIGIT
MUST BE TYPED ON ANY GIVEN INPUT STRING
PRIOR TO THE TERMINATOR BEFORE A CHANGE TO THE SSR WILL OCCUR.
WHEN THE INPUT STRING IS TERMINATED WITH A <CR> THE DIAGNOSTIC
WILL
CONTINUE
EXECUTION FROM THE
POINT
AT
WHICH
IT WAS
INTERRUPTED.
IF A <CR> IS THE ONLY THING
TYPED
THE PROGRAM
WILL CONTINUE WITHOUT CHANGING THE SSR.
THE <LF> DIFFERS FROM

THE Eglsb Z(BKY) RESTARTING THE PROGRAM AS IF IT WERE RESTARTED

IF A CTRL U IS TYPED AT ANY POINT IN THE INPUT STRING PRIOR TO
THE
TERMINATOR
THE
INPUT
VALUE WILL BE DISREGARDED AND THE
PROMPT DISPLAYED (SWR = XXXXXX NEW?).

TO SET THE SSR FOR
THE
STARTING SWITCHES,
FIRST LOAD
DIAGNOSTIC, TK:N HIT CTRL G, THEN START THE DIAGNOSTIC.

THE

SEQ 14

CZOMC
MACRO v04.00 27-JUN-85 13:16:37 PAGE 17
INTRODUCTION TO DMC11 DIAGNOSCTIC

1683

s8AC-8544C-MC
CZDMC-DO BASIC DMC11 CONTROLLER TEST
+#COPYRIGHT 1976,1978, DIGITAL EQUIPMENT CORP., MAYNARD, MASS. 01754
sSTARTING PROCEDURE

;LOAD PROGRAM
sLOAD ADDRESS 000200
:SWR=0 AUTOSIZE DMC11
;SW07=1 USE CURRENT DMC11 PARAMETERS
:SW00=1 INPUT NEW DMC11 PARAMETERS
sPRESS START
sPROGRAM WILL TYPE “AC-8544C-MC
CZDMC-DO BASIC DMC11 CONTROLLER TEST*
sPROGRAM WILL TYPE STATUS MAP
;PROGRAM WILL TYPE “R” TO INDICATE THAT TESTING HAS STARTED
sAT THE END OF A PASS, PROGRAM WILL TYPE PASS COMPLETE MESSAGE
sAND THEN RESUME TESTING
sSUBSEQUENT RESTARTS WILL NOT TYPE PROGRAM TITLE

sSWITCH REGISTER OPTIONS
i

|
|

ot ko

AL
P
PR

100000
040000

SW15=100000

:=1,HALT ON ERROR

010000
004000
002000
001000
000400
000200

SW13=20000

SW12=10000

:=1,INHIBIT ERROR TYPEOUT

+=1.DELETE TYPEOUT/BELL ON ERROR.

SW10=2000
SW09=1000
SW08=400
SW07=200

+=1,ESCAPE TO NEXT TEST ON ERROR
+=1,LO0P WITH CURRENT DATA
+=1,LO0P ON ERROR
+=1,USE CURRENT DMC11 PARAMETERS,

020000

000100

000040
000020
000010
000004
000002
000001

SW14=40000
SW11=4000

gfi'igo

SW04=20
SW03=10

SW02=4
SW01=2
SW00=1

3=1,LO0OP ON CURRENT TEST
+=1,INHIBIT ITERATIONS

-0,AUTOSIZE DMC11

i=1, HALT BEFORE CLOCKING MICRO-PROCESSOR INSTRUCTION
sRESELECT DMC11'S TO BE TESTED (ACTIVE)

;LOCK ON TEST SELECT
sRESTART PROGRAM AT SELECTED TEST
;INPUT DMC11 PARAMETERS

SEQ 15

CZOMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 18
GENERAL DEFINATIONS AND EQUIVALENCIES
0

sREGISTER DEFINITIONS

RO>%0
R1=%1
R2=42
R3-%3
R4 =44

R5=%5
SP=%6
PC=%7

;GENERAL REGISTER
sGENERAL REGISTER
sGENERAL REGISTER
sGENERAL REGISTER
;GENERAL REGISTER
sGENERAL REGISTER
;PROCESSOR STACK POINTER

;PROGRAM COUNTER

sLOCATION EQUIVALENCIES
177776
001200

PS=177776

STACK=1200

;PROCESSOR STATUS WORD

sSTART OF PROCESSOR STACK

sINSTRUCTION DEFINITIONS
005746
005726
010046
012600
024646
022626

PUSH1SP=5746
POP1SP=5726
PUSHRO=10046
POPRO=12600

sDECREMENT PROCESSOR STACK 1 WORD
s INCREMENT PROCESSORP STACK 1 WORD
sSAVE RO ON STACK
sRESTORE RO FROM STACK

POP25P=22626

sINCREMENT STACK TWICE

PUSH25P=24646

sBIT DEFINITIONS
100000
040000
020000
010000
004000
002000
001000
000400
000200
000100
000040
000020
000010
000004
000002
000001

B8I715=100000
BIT14=40000
BIT13=20000
B8IT12=10000
81711=4000
81710=2000
8179=1000
B8IT8-400
BIT7=200
BIT6=100
BIT5=40
BIT4=20
BIT3=10
BIT2=4
BIT1=2
BITO=1

;DECREMENT STACK TWICE

—mey

SEQ 16

CZoMC

MACRO V04.00
27-JUN-85 13:16:37 PAGE 19
TRAPCATCHER FOR UNEXPECTED INTERUPTS

$3:8888344
8808800500840
88288
0 0500000000tt
88888
t bt88848
bbbttt hattbins
8

sTRAPCATCHER FOR ILLEGAL INTERRUPTS

;THE STANDARD "TRAP CATCHER” IS PLACED

sBETWEEN ADDRESS O TO ADDRESS 776.
;IT LOOKS LIKE “PC+2 HALT".

$:88888488848848484888588 8584805500000kttt hbtb bbb bbbbib

bbb bbbt bhig

.=0

;STANDARD INTERRUPT VECTORS

000052

000024
005336
000340
004750
000340
004716
000340
000040
000000
000000
000000
003522
000052
000000

000174
000176

000174
000000
000000

000200

000200
000137

002002

001000
001016

001000
377
103

012
132

000024

000030
000032
000036
000040
0C0042
000044
000046

001200

.=24

“*

;
-

.PFAIL

;POWER FAIL HANDLER

340
LHLT
340
. TRPSRV
340

sSERVICE AT LEVEL 7
;ERROR HANDLER
;SERVICE AT LEVEL 7
sGENERAL HANDLER DISPATCH SERVICE
;SERVICE AT LEVEL 7

:SAVE FOR ACT-11 OR XXDP

0
0

:RETURN ADDRESS IF UNDER ACT-11 OR XXDP
sSAVE FOR ACT-11 OR XXDP

;ACT-11 PROGRAM CHARACTERISTICS

$ENDAD

;FOR USE WITH ACT-11 OR XXDP

.=174

DISPREG:0
SWREG:
.=200

101
104

.=1000
MTITLE:

:SOFTWARE DISPLAY REGISTER

;SOFTWARE SWITCH REGISTER

JMP

.START

.ASCII
.ASCIZ

<377><12>/AC-8544C-MC/<377>
/CZDMC-DO BASIC DMC11 CONTROLLER TEST/<377>

;GO TO START OF PROGRAM

.=1200

sINDIRECT POINTERS TO SWITCH REGISTER AND LIGHT DISPLAY
001200
001202

177570
177570

DISPLAY:177570

SKR:

177570

SEQ 17

CZOMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 20
PROGRAM PARAMETERS, VARIABLES, AND TRAP CALLS.

sINDIRECT POINTERS TO TELETYPE VECTORS AND REGISiERS
001204
001206
001210
001212

177560
177562
177564
177566

TKCSR:
TKDBR:
TPCSR:
TPDBR:

177560
177562
177564
177566

:TELETYPE KEYBOARD CONTROL REGISTER
;sTELETYPE KEYBOARD DATA BUFFER
; TELEPRINTER CONTROL REGISTER
s TELEPRINTER DATA BUFFER

001214
001216
001220
001222
001224
001226
001230
001232
001234

000003
000000
000000
000000

RETURN:
NEXT:
LOCK :
ICOUNT:
LPCNT:
TSTNO:

PASCNT :

ERRCNT :
LSTERR:

[~ X-X-T-T-X
F-¥- ¥

;PROGRAM CONTROL PARAMETERS
:SCOPE ADDRESS FOR LOOP ON TEST
;ADDRESS OF NEXT TEST TO BE EXECUTED
sADDRESS FOR LOCK ON CURRENT DATA
:NUMBER OF ITERATIONS THAT CURRENT TEST WILL BE EXECUTED
:NUMBER OF ITEREATIONS COMPLETED
:NUMBER OF TEST IN PROGRESS
sNUMBER OF PASSES COMPLETED
;TOTAL NUMBER OF ERRORS
;PC OF LAST ERROR CALL

001236
001240
001242
001244
001246
001250
001252
001254
001256
001260
001262
001264
001266
001270
001272
001274
001276
001300
001302
001304
001306
001310
001312
001314
001316
001320
001322

;b- e

STRTSM:
STAT:.
CLKX:

MASKX:

000000

TEMP1:
TEMP2:
TEMP3:
TEMP4;
TEMPS:
SAVRO:
SAVR1:
SAVR2:
SAVR3:
SAVRA4 :
SAVRS:
SAVSP:
SAVPC:
ZERO:
ONE:
MEMLIM:
DMACTV:

DMNUM:
SAVACT :

000000

001472
001676

(-l o X-E-T-F-F-~1-F-Y-F-Y-F-X-Y-T-Y-F-¥-¥.)

;PROGRAM VARIABLES

BLKW 1
.BLKW 1
.BLKMW 1

SAVNUM: 6BLKU 1
RUN:
.EVEN
CREAM:
DM.MAP-6
MILK:
CNT.MAP-4

:SWITCHES AT START OF PROGRAM
;DM STATUS WORD STORAGE
: TEMPORARY STORAGE

;sTEMPORARY STORAGE
; TEMPORARY STORAGE
s TEMPORARY STORAGE
: TEMPORARY STORAGE
;RO STORAGE
;R1 STORAGE
:R2 STORAGE
;R3 STORAGE
;R4 STORAGE
;RS STORAGE
sSTACK POINTER STORAGE
;PROGRAM COUNTER. STORAGE
sHIGHEST LOCATION FOR NPR'S
:DMC11'S SELECTED ACTIVE.
sOCTAL NUMBER OF DMC11'S.
;ORIGINAL ACTV DEVICES
sWORKABLE NUMBER
;POINTER TO RUNNING DEVICE.
;TABLE POINTER.
s TABLE POINTER

CZOMC

MACRO V04.00

PROGRAM PARAMETERS,

SEQ 18

27-JUN-85 13:16:37 PAGE 21

VARIABLES, AND TRAP CALLS.

;PROGRAM CONTROL FLAGS

001324
001325
001326
001327

000
000
000
000

INIFLG:
ERRFLG:
LOKFLG:
QV.FLG:
p—

.BYTE
.BYTE
.BYTE
.BYTE

O
O
O
0

;PROGRAM INITIALIZATION FLAG
;ERROR OCCURED FLAG
;:LOCK ON CURRENT TEST FLAG
;QUICK VERIFY FLAG.

;ON FIRST PASS OF EACH DMC11 ITERATIONS WILL BE SUPPRESSED.

;:DEFINITIONS FOR TRAP SUBROUTINE CALLS
;POINTERS TO SUBROUTINES CAN BE FOUND

;IN THE TABLE IMMEDIATLY FOLLOWING THE DEFINITIONS
PR T
PP PP PP PP PP
PP,
' ------------------------------------------------------------

--------

001330

.TRPTAB:

104400

SCOPE=TRAP+0

:CALL TO SCOPE LOOP AND ITERATION HANDLER

104401

SCOP1=TRAP+1

sCALL TO LOOP ON CURRENT DATA HANDLER

104402

TYPE=TRAP+2

sCALL TO TELETYPE OUTPUT ROUTINE

104403

INSTR=TRAP+3

;CALL TO ASCII STRING INPUT ROUTINE

104404

INSTER=TRAP+4

;CALL TO INPUT ERROR HANDLER

104405

PARAM=TRAP -5

;CALL TO NUMERICAL DATA INPUT ROUTINE

104406

SAVOS=TRAP +6

;CALL TO REGISTER SAVE ROUTINE

104407

RESOS5=TRAP+7

;CALL TO REGISTER RESTORE ROUTINE

104410

CONVRT=TRAP+ 10

sCALL TO DATA OUTPUT ROUTINE

104411

CNVRT=TRAP.11

;CALL TO DATA OUTPUT ROUNTINE WITHOUT CR/LF.

104412

MSTCLR=TRAP+12

sCALL TO ISUE A MASTER CLEAR

104413

DELAY=TRAP+13

sCALL TO DELAY

104414

ROMCLK=TRAP+ 14

sCALL TO CLOCK ROM ONCE

104415

DATACLK=TRAP +15

;:CALL TO CLK DATA

104416

TIMER=TRAP+16

sCALL TO DELAY A CLOCK TICK

001330

003576

001332

003736

0C1334

003766

001336

004050

001340

004154

001342

004174

001344

004374

001346

004434

001350

004466

001352

004472

001354

005466

001356

005436

001360

005504

001362

005552

001364

005616

.SCOPE
.SCOP1

.TYPE
.INSTR

.INSTER

.PARAM
.SAVOS

.RESOS

.CONVRT

.CNVRT

.MSTCLR

.DELAY
-ROMCLK

.DATACLK

. TIMER

18858844408

8848 0058848040454
0 005050000454 40 00400kt ddbitibiiibbttids

SEQ 19

CZDMC
MACRO V04.00 27-JUN-B5 13:16:37 PAGE 22
PROGRAM PARAMETERS, VARIABLES, AND TRAP CALLS.

sDMC11 CONTROL INDICATORS FOR CURRENT DMC11 UNDER TEST
001366
001370
001372

STAT1:
STAT2:
STAT3:

O
0O
0

;DMC11 VECTOR AND REGISTER INDIRECT POINTERS
001374
001376
001400
001402
001404
001406
001410
001412
001414

DMRVEC:
DMRLVL:
DMTVEC:
DMTLVL:
DMCSR:
DMCSRH:
DMCTL:
DMPO4:
DMPO6:

O
O
O
O
O
0
O
O
O

;POINTER
sPOINTER
;POINTER
sPOINTER
;POINTER
sPOINTER
;POINTER
sPOINTER
;POINTER

TO
TO
TO
TO
TO
TO
TO
TO
TO

DMC11
DMC11
DMC11
DMC11
DMC11
DMC11
DMC11
DMC11
DMC11

RECEIVER INTERRUPT VECTOR
RECEIVER INTERRUPT SERVICE PS
TRANSMITTER INTERRUPT VECTOR
TRANSMITTER INTERRUPT SERVICE PS
CONTROL STATUS REGISTER
CONTROL STATUS REGISTER HIGH BYTE.
CONTOL OUT REGISTER
PORT REGISTER(CSEL &)
PORT REGISTER(SEL 6)

;TEMP STORAGE
; ...........

0C1416

001460

TEMP:
.=,+40

sDMC11 STATUS TABLE AND ADDRESS ASSIGNMENTS

001500
001500
001502
001504
001506

001500

.=1500
DM.MAP:

DMCROO:
DMS100:
DMS200:
DMS300:

.BLKW
.BLKW
.BLKW
.BLKW

1
1
1
1

sCONTROL STATUS REGISTER FOR DMC11 NUMBER 00
;VECTOR FOR DMC11 NUMBER 00
;DDCMP LINE® FOR DMC11 NUMBER 00
s3RD STATUS WORD

001510
001512
001514
001516

DMCRO1:
DMS101:
DMS201:
DMS301:

.BLKW
.BLKW
.BLKW
.BLKW

1
1
1
1

sCONTROL STATUS REGISTER FOR DMC11 NUMBER 01
;VECTOR FOR DMC11 NUMBER 01
;DDCMP LINE® FOR DMC11 NUMBER 01
;3RD STATUS WORD

001520
001522

DMCRO2:
DMS102:

.BLKW
.BLKN

1
1

;CONTROL STATUS REGISTER FOR DMC11 NUMBER 02
;VECTOR FOR DMC11 NUMBER 02

001526

DMS302:

.BLKW

s3RD STATUS WORD

.BLKW
.BLKNW
.BLKW
.BLKN

1
1
1
1

;sCONTROL STATUS REGISTER FOR DMC11 NUMBER 03
;VECTOR FOR DMC11 NUMBER 03
;DDCMP LINE# FOR DMC11 NUMBER 03
:3RD STATUS WORD

.BLKW

;sCONTROL STATUS REGISTER FOR DMC1i NUMBER 04

;DDCMP LINE® FOR DMC11 NUMBER 04
:3RD STATUS WORD

DMS202:

.BLKW

001530
001532
001534
001536

DMCRO3:
DMS103:
DMS203:
DMS303:

001540
001542
001544
001546

DMCRO4:

DIIS104:

.BLKW

.BLKW
.BLKW

1
1

001550

DMCROS:

.BLKW

DMS204:
DMS304:

;:DDCMP LINE® FOR DMC11 NUMBER 02

;VECTOR FOR DMC11 NUMBER 04

;CONTROL STATUS REGISTER FOR DMC11i NUMBER 05

MACRO V04.00

DMCRO7 : .BLKW

.BLKW

.BLKuW

001572
001574
001576

DMS107: .BLKW
DMS207: .BLKW
DMS307: .BLKMW

001600

DMCR10: .BLKMW

001604
001606

DMS210: .BLKW
DMS310: .BLKW

001610
001612
001614
001616

DMCR11: .BLKW
DMS111: .BLKW

001620
001622

DMCR12: .BLKW
DMS112: .BLKW

001602

DMS110: .BLKW

;CONTROL STATUS REGISTER FOR DMC11 NUMBER 06
;VECTOR FOR DMC11 NUMBER 06
;DDCMP LINE® FOR DMC11 NUMBER 06
:3RD STATUS WORD

;CONTROL STATUS REGISTER FOR DMC11 NUMBER 07
;VECTOR FOR DMC11 NUMBER 07

;DDCMP LINE# FOR DMC11 NUMBER 07
:3RD STATUS WORD
sCONTROL STATUS REGISTER FOR DMC11 NUMBER 10
;VECTOR FOR DMC11 NUMBER 10
;DDCMP LINE# FOR DMC11 NUMBER 10
:3RD STATUS WORD

;CONTROL STATUS REGISTER FOR DMC11 NUMBER 11
;VECTOR FOR DMC11 NUMBER 11
;DDCMP LINE® FOR DMC11 NUMBER 11
:3RD STATUS WORD
sCONTROL STATUS REGISTER FOR DMC11 NUMBER 12
:VECTOR FOR DMC11 NUMBER 12

sCONTROL STATUS REGISTER FOR DMC11 NUMBER 13
;VECTOR FOR DMC11 NUMBER 13
;DDCMP LINE® FOR DMC11 NUMBER 13

DMS212: .BLKW
DMS312: .BLKW

001630
001632
001634
001636

DMCR13:
DMS113:
DMS213:
DMS313:

001640
001642
001644
001646

DMCR14 :
DMS114: .BLKW
DMS214: .BLKW
DMS314: .BLKW

001650
001652
001654
001656

DMCR15:
DMS115:
DMS215:
DMS315:

-BLKW

sCONTROL STATUS REGISTER FOR DMC11 NUMBER 15
;VECTOR FOR DMC11 NUMBER 15
;ODCMP LINE® FOR DMC11 NUMBER 15
:3RD STATUS WORD

001660
001662
001664
001666

DMCR16: .BLKW
DMS116:
DMS216: .BLKW
DMS316: .BLKW

sCONTROL STATUS REGISTER FOR DMC11 NUMBER 16
sVECTOR FOR DMC11 NUMBER 16
sDOCMP LINE4 FOR DMC11 NUMBER 16
+3RD STATUS WORD

001670

DMCR17:

001676

DMS317: .BLKW

001672
001674

001700

.BLKW
.BLKW
.BLKNW
.BLKW

.BLKW
.BLKW
.BLKW

DMS117: .BLKW
DMS217: .BLKW
000000

DM.END: 000000

o o

001624
001626

.BLKW
.BLKW

;VECTOR FOR DMC11 NUMBER 05
;DDCMP LINE® FOR DMC11 NUMBER 05
:3RD STATUS WORD

o oe

DMS211:
DMS311:

O PA

001570

.BLKW
.BLKW

S O e

DMCRO6 .
DMS106:
DMS206 :
DMS306 :

T TlT

001560
001562
001564
001566

T o
o

001556

DMS105: .BLKuW
DMS205 : .BLKW
DMS305: .BLKW

001552
001554

VARIABLES, AND TRAP CALLS.

e S

PROGRAM PARAMETERS,

SEQ 20

27-JUN-85 13:16:37 PAGE 22-1

el
B

CZOMC

:DDCMP LINE® FOR DMC11 NUMBER 12
:3RD STATUS WORD

:3RD STATUS WORD

:CONTROL STATUS REGISTER FOR DMC11 NUMBER 14
sVECTOR FOR DMC11 NUMBER 14
;:DDCMP LINE® FOR DMC11 NUMBER 14
;3RD STATUS WORD

sCONTROL STATUS REGISTER FOR DMC11 NUMBER 17
sVECTOR FOR DMC11 NUMBER 17
;DDCMP LINE® FOR DMC11 NUMBER 17
+3RD STATUS WORD

SEQ 21

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 23
PROGRAM PARAMETERS, VARIABLES, AND TRAP CALLS.

sDMC11 PASS COUNT AND ERROR COUNT TABLE
CNT.MAP:

oo
©©0

;PASS COUNT FOR DMC11 NUMBER 01
;ERROR COUNT FOR DMC11 NUMBER 01

001712
001714

ERCTO2:

PACTO2:

©©0

;PASS COUNT FOR DMC11 NUMBER 02

001716
001720

PACTO3:
ERCTO3:

;PASS COUNT FOR DMC11 NUMBER 03
;ERROR COUNT FOR DMC11 NUMBER 03

001722
001724

PACTO4 :

ERCTO4:

;PASS COUNT FOR DMC11 NUMBER 04
:ERROR COUNT FOR DMC11 NUMBER 04

001730

001726

PACTOS:
ERCTOS:

;PASS COUNT FOR DMC11 NUMBER 05
;ERROR COUNT FOR DMC11 NUMBER 05

0C1732
001734

PACTO06:
ERCTO06:

;PASS COUNT FOR DMC11 NUMBER 06
:ERROR COUNT FOR DMC1i NUMBER 06

001736
001740

PACTO7:

ERCTO7:

sPASS COUNT FOR DMC11 NUMBER 07

001742
001744

PACT10:
ERCT10:

sPASS COUNT FOR DMC11 NUMBER 10
;ERROR COUNT FOR DMC11 NUMBER 10

001746
001750

PACT11:

sPASS COUNT FOR DMC11 NUMBER 11
sERROR COUNT FOR DMC11 NUMBER 11

001752
001754

PACT12:

;PASS COUNT FOR DMC11 NUMBER 12
;ERROR COUNT FOR DMC11 NUMBER 12

001756
001760

PACT13:

;PASS COUNT FOR DMC11 NUMBER 13
;ERROR COUNT FOR DMC11 NUMBER 13

001762
001764

PACT14:

sPASS COUNT FOR DMC11 NUMBER 14
sERROR COUNT FOR DMC11 NUMBER 14

001766
001770

PACT15:

©O0

PACTO1:

;PASS COUNT FOR DMC11 NUMBER 00
;ERROR COUNT FOR DMC11 NUMBER 00

sPASS COUNT FOR DMC11 NUMBER 15
;ERROR COUNT FOR DMC11 NUMBER 15

001772
001774

PACT16:
ERCT16:

PACTOO:

:PASS COUNT FOR DMC11 NUMBER 16

001776
002000

PACT17:

001702
001702
001704

sPASS COUNT FOR DMC11 NUMBER 17
sERROR COUNT FOR DMC11 NUMBER 17

001706
001710

ERCTO0:

ERCTO1:

ERCT11:
ERCT12:

ERCT13:

ERCT14:
ERCT1S5:

ERCT17:

;ERROR COUNT FOR DMC11 NUMBER 02

;ERROR COUNT FOR DMC11 NUMBER 07

sERROR COUNT FOR DMC11 NUMBER 16

CZOMC

MACRO V04.00

PROGRAM PARAMETERS,

SEQ 22

27-JUN-85 13:16:37 PAGE 24

VARIABLES, AND TRAP CALLS.

.REM

FORMAT OF STATUS TABLE
-

€

$§

I
R}

€

CSR

e
I
——

I
I
Is*sIs
- .

I+
I

I
=1I
I

=+»1I
ST ¢

STAT1

STAT2

-----------------------

5
At
D

&%
£
-2
&
X
TRy TEPE TR
NS S
T
AT S
R
AROE GG
s

SRR
I

= M
SR

X
O

CSR:

CONTAINS DMC11 CSR ADDRESS

STATL:

BITS 00-08 IS DMC11 VECTOR ADDRESS
BIT15=1 MICRO-PROCESSOR HAS CRAM
B8IT15=0 MICRO-PROCESSOR HAS CROM
BIT14=1 ?22? TURNAROUND CONNECTOR IS ON
BIT14=0 NO TURNAROUND CONNECTOR
BIT13=0 LINE UNIT IS AN M8201
BIT13=1 LINE UNIT IS AN M8202
BIT12=1 NO LINE UNIT

STAT3

BITS 09-11 IS DMC11 BR PRIORITY LEVEL

STAT2:

LOW BYTE IS SWITCH PAC#1 (DDCMP LINE NUMBER)
HIGH BYTE IS SWITCH PACé2 (BM873 BOOT ADD)

STAT3:

BITO=1 DO FREE RUNNING TESTS ON KMC
(MUST BE SET 7O A ONE MANUALLY [PROGRAM DZDMI ONLY))
KMC MUST HAVE MICRO-CODE WRITTEN FROM RUNNING
DZDMG TEST 2 FIRST
BITi=1 DMCi1-AL LOCAL HIGH SPEED MICRO-CODE
BIT1=0 DMC11-AR REMOTE LOW SPEED MICRO-CODE

SEQ 23

MACRO v04.00
27-JUN-85 13:16:37 PAGE 25
CZoMC
PROGRAM INITIALIZATION AND START UP.

;PROGRAM INITIALIZATION
sLOCK OUT INTERRUPTS
;SET UP PROCESSOR STACK
sSET UP POWER FAIL VECTOR
;CLEAR PROGRAM CONTROL FLAGS AND COUNTS
;sTYPE TITLE MESSAGE

012737
012706
012737
013737
005037
105037
105037
012737
012737
012737
012700
005020
022700

001374
005037
012737
012737
013746
013746
012737
012737
012737
022777
001402
000407
022626
012737
012737
012637
012637

105737
001006
022737
001402
104402
004737
017737
005737
001402
005037
032737
001012
105737
100007
005737
001006
104402
000000

000340
001200
005336
001310
010016
001325
001327
001470
001676
100000
001702

177776
000024
001314

001320
001322
001316

002002
001234
000001
002002

000006
000004
002166
177570
177570
177777

000176
000174
000004
000006
001324

001226
001214

001202
001200

177020

001202
001200

003522
001000
007606
176734
000042

001236
000001
001236

001306
007154

.START: MOV
MOV
MOV
MOV
CLR
CLRB
CLRB
MOV
MOV
MOV
MOV
23%:
CLR
cMP
BNE
CLR
MOV
MOV

001236

64:
74:

MOV
MOV
MOV
MOV
MOV
CHP
BEQ
BR
CHP
MOV
MOV
MOV
MOV
TS78
BNE
CHP
BEQ
TYPE
JSR
MOV
TST
BEQ

CLR
817
BNE

1578
BPL
18T
8NE
TYPE,
HALT

#340,PS
#STACK,SP
#.PFAIL, 8424

;LOCK OUT INTERRUPTS
:SET UP STACK
:SET UP POWER FAIL VECTOR
;SAVE NUMBER OF DEVICES IN SYSTEM.
;CLEAR SOFT TYPEOUT FLAG

DMNUM, SAVNUM
SWFLG
ERRFLG
;:CLEAR ERROR FLAG
QV.FLG
:ZERO QUICK VERIFY FLAG
#DM.MAP-10,CREAM;GET MAP POINTER.
#CNT.MAP-4 ,MILK ;GET PASS COUNT MAP POINTER
#B8IT15,RUN
;POINT POINTER TO FIRST DEVICE.
#CNT .MAP RO
;PASS COUNT POINTER TO RO
(RO)«
;CLEAR TABLE
#CNT .MAP+100,R0O ;DONE YET?
23$
;KEEP GOING
LSTERR
;CLEAR LAST ERROR POINTER
#1,TSTNO
;SET UP FOR TEST 1
@.START,RETURN
sSET UP FOR POWER FAIL BEFORE
806, -(SP)

sTESTING STARTS
sSAVE CURRENT VECTORS

964,804
:SET UP FOR TIMEOUT
2177570,
SWR
;SET SWR TO HARD SWR ADDRESS
#177570,DISPLAY :SET DISPLAY TO HARD SWR ADDRESS
#-1,8SUWR
;REFERENCE HARDWARE SWITCH REGISTER
68+2
:IF = -1 USE SOFT SWR ANYWAY
7%
+IF IT EXISTS AND NOT = -1 USE HARD SWR
(SP)+,(SP)+
sADJUST STACK
OSWREG, SWR
;POINTER TO SOFT SWR
#DISPREG,DISPLAY ;POINTER TO SOFT DISPLAY REG

(SP)+,804
(SP)+,806
INIFLG
208
@3ENDAD, 8042
204
JMTITLE
PC,CKSHR
SSWR ,STRTSW
342
.46
STRTSW
#SUH00,STRTSW
174
STRTSW

17%
DMACTY
16
NOACT

;RESTORE VECTORS

;HAS INITIALIZATION BEEN PERFORMED
sBR IF YES

+IF ACT-11 AUTOMATIC MODE, DON'T TYPE ID

;TYPE TITLE MESSAGE
;CHECK FOR SOFT SWR
sSTORE STARTING SWITCHES
:IS IT RUNNING IN AUTO MODE?
;B8R IF NO
sIF YES, CLEAR SWITCHES
;IF SWOO=1, QUESTIONS ARE ASKED.
:BR IF SWO0O=1
;8IT7=127
sBR IF SW07=0
:ARE ANY DEVICES SELECTED?
;BR IF YES
;NO DEVICES SELECTED.
;STOP THE SHOM

SEQ 24

CZOMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 25-1
PROGRAM INITIALIZATION AND START UP.

002314
002316
002322
002326
002330
002334
002336
002344
002346
002350
002354
00236C
002364
002370
002374
002376
002402
002406
002412
002414
002416
002420

000776
004737
105737
001410
105737
100431
032737
001403
000424

005137
104402
012704

010437
012437
001411
012437
012437
012437
104410
007454
000762
012700

010512
001324

17s:
16%:

001236
000006

001236

001324
006224
001500
001246
001250

21%:
245%:
Ss:

001252
001254
001256

001500

1%:

BR
JSR
TST8
BEQ

1518
BMI
BIT
BEQ
BR
COM
TYPE
MOV
MOV
MOV
BEQ
MOV
MOV
MOV

CONVRT
XSTATQ
BR
MOV

-2
;DISQUALIFY CONTINUE SWITCH
PC,AUTO.SIZE
;GO DO THE AUTO SIZE
INIFLG
;FIRST TIME?
218
;BR IF YES
STRTSH
;IF USING SAME PARAMETERS DONT TYPE MAP
1s
#BIT1!BIT2,STRTSW;IS TEST NO. OR LOCK SELECTED
244
;IF NO THEN TYPE STATUS
1s
:IF YES DO NOT TYPE STATUS
INIFLG
:SET FLAG

«XHEAD

#0M.MAP,R4

R4, TEMP1

(l:‘)o.TEPPZ
1

(R4)+,TEMP3
(R4)+,TEMP4
(R4)+,TEMPS
14
#DM.MAP,RO

s TYPE HEADER
:SET POINTER
:SET ADDRESS
:SET CSR
:ALL DONE IF ZERO
:SET STAT1

:SET STAT2
sSET STAT3
:TYPE OUT STATUS MAP
:

;RO POINTS TO STATUS TABLE

i
LT T T T
P PP
T P PP TP PPTPes

::#AUTO SIZE TEST
+3#THIS TEST VERIFYS THAT THE DMC11S AND/OR KMC11S ARE AT THE CORRECT FLOATING
+ s #*ADDRESSES FOR YOUR SYSTEM. IF THIS TEST FAILS, IT IS NOT A HARDWARE ERROR.
+s#CHECK THE ADDRESSES OF ALL FLOATING DEVICES (DJ,DH,DQ,DU,DUP,LK,DMC,DZ,KMC).
13¢IF THERE ARE NO OTHER FLOATING DEVICES BEFORE THE DMC11, THE FIRST
:;#DMC11 ADDRESS IS 760070, KMC11i IS 760110. NO DEVICE SHOULD EVER BE AT
+ s *ADDRESS 760000. THIS TEST MAY REQUIRE 2 OR MORE ATTEMPTS TO GET THE
+ s SRIGHT ADDRESSES. AFTER YOU HAVE CHANGED THE ADDRESS TO WHAT IT TOLD
+3%YOU THE FIRST TIME, IT MAY COME BACK AND TELL YOU A DIFFERENT ADDRESS
53oTHE NEXT TIME YOU RUN IT. PLEASE HAVE PATIENCE, THE FINAL ADDRESS
IS:ILL g)CMRECT (AS LONG AS ALL DEVICES IN FRONT OF THE DMC'S ARE
; s sCORRE
.

$3580888484888885248808488888
0804888888400 80808000000 kR0 00 Rttt sd bbb it

002424
002430
002434
002440
002444
002446
002452
002454
002456
002460
002466
002470
002472

002502
002510

002512
002514

013746
013746
005037
005037

000004
000006

MOV
MOV
CLR

001252

CLR

011037
001564
005705
001005
032760
001061

001404

032760
001454
012737
005705
001003
012703
000402

100000

000002

002674

000004

100000

CLR
AUSTRT: MOV
BEQ
15T
BNE
BIT
BNE
BR
1s:
BIT
BEQ
2s%:
MOV
TST
BNE
MOV
BR

806
TEMP3
R5

(RO),DMCSR
AUDONE
RS

13
#81IT15,2(R0)
SKIP
24
#B1715,2(RO)
SKIP
ONODEV
, 804
RS
38
#6,R3

:SAVE LOC 4
sSAVE LOC 6
;CLEAR VEC.2
;CLEAR FLAG

;R5=0=DMC, RS=-1=KMC

sGET NEXT DMC CSR
sBR IF DONE
;OMC OR KMC?
sBR IF KMC
sCHECK FOR DMC CSR
;SKIP IF NOT DMC
sITS A DMC SO CONTINUE
;CHECK FOR KMC CSR
;SKIP IF NOT KMC
:SET UP FOR TIMEOUT

sDMC OR KMC?
:BR IF KMC
;R3 IS COUNT OF DEVICES BEFORE DMC

;GO ON

SEQ 25

MACRO V04.00
27-JUN-85 13:16:37 PAGE 25-2
CZoMC
PROGRAM INITIALIZATION AND START UP.

002522
002526
002532
002536

012703

012702
012701
005711
111204
060401

3s:
43

000010
003010
160010

FLOAT:

002700
003022

FY:

BIT

100000

BNE

100000

14:
2%:

001404
000010

000010
001404

000010
000010
001404

SKIP:

003022

003022
NODEV:
001252

002700

1777177
001262

002762
002764

MOV
MoV
MOV
18T
MOVB
ADD
INC
BIC
18T
BNE
MOV
MOV
TST
BNE

18T
cMP
BEQ

ADD
BR
ADD
MOV
BEQ
BR
ADD
ADD
MOV

BEQ
MOV
BR
CcHPB

RTI
TST
BNE
TYPE

CONERR
MOV
CNVRT
ERRPC

001276

001252

BR
BIT
BEQ

1$:

#10,R3
SDEVTAB.R2
#160010,R1

(R1)
(R2) R4

R4,R1
R1
R4 ,R1
R3
FLOAT
9ERR, 804
R1,XLOC
RS
1s

#8IT15,2(RO)
SKIP
2%
#81IT15,2(RO)
SKIP
(R1)
R1,DMCSR
0K
#10,R1

#10,R0

(RO),DMCSR
AUDONE

FY
#10,R0
10, XLOC

(RO) ,DMCSR
AUDONE
XLOC,R1

(R2)+,-(R3)

TEMP3
13
#ERR , SAVPC

;R3 IS COUNT OF DEVICES BEFORE KMC
;R2 IS DEVICE TABLE PONTER
;START WITH ADDRESS 160010
sCHECK ADDRESS IN R1
:%: fi TIMEOUT, GET NEXT ADDRESS
:

;ANY MORE DEVICES TO CHECK FOR?
:BR IF YES
;0K ONLY DMC'S ARE LEFT, SET UP FOR TIMEOUT
:+SAVE FIRST DMC/KMC ADDRESS
;DMC OR KMC?
sBR IF KMC
;CHECK FOR DMC CSR
;SKIP IF NOT DMC

;ITS A DMC SO CONTINUE
;CHECK FOR KMC CSR

;SKIP IF NOT KMC

;CHECK DMC ADDRESS

;D0ES IT MATCH

:BR IF YES

;:GET NEXT DMC ADDRESS
;00 IT AGAIN
;SKIP TO NEXT CSR IN TABLE
;GET NEXT CSR
:BR IF DONE
;ELSE CONTINUE
:SKIP TO NEXT DMC CSR
;UPDATE EXPECTED DMC/KMC ADDRESS
;GET NEXT DMC/KMC CSR
;:BR IF DONE
:GET EXPECTED DMC/KMC ADDRESS
;CONTINUVE
sON TIMEOUT, INC R2, DEC R3
sRETURN
;CHECK FLAG IF = 0 TYPE HEADER
:SKIP HEADER
sTYPEOUT HEADER MESSAGE
;CONFIGURATION ERROR!!!!
sSAVE PC FOR TYPEOUT
;TYPE OUT ERROR PC
:

s TYPE REST OF HEADER
9-1,TEMP3
R1,SAVR1

]

sSET FLAG SO IT ONLY GETS TYPED ONCE
$SAVE R1 FOR TYPEOUT

RS
34

sTYPZ CSR VALUES
;DMC OR KMC ?
;1BR IF KMC

s CONTINUVE

(SP)+,(SP)+

sADJUST STACK

SEQ 26

czomnc
MACRO V04.00 27-JUN-85 13:16:37 PAGE 25-3
PROGRAM INITIALIZATION AND START UP.

000000
005705
001005
012705
012700
000602
012637
012637
032737
001422
104402
005000

027737
101404
104402
000776

002

:BR TO GET OUT

CONTAB: 2

6.4
6,2

.EVEN

XLOC:

SNaNSNNNNN ~

DEVTAB:

177777
001500
000006
000004
000010

1$:
001236

#SWO3, STRTSH
34

006144

176104

001312

SSWR ,SAVACT
2

+MERR3

006005

017737

176064
001306

012700
012701
010120
005021
022021
022700
001372

000300

013700

ERRPC:

000727
000001
006
001276
000002
006
003022
006
001404
007
017
007
007
007
007
007
007
007

R £

002766
002770
002772
002774
002776

001306

SSWR ,DMACTV
DMACTV,RO
4300, RO
#302,R1

000302

(R1)e
(RO)+,(R1)»

001000

;DJ
;:DH
;:DQ
)
;DUP
;LK
;OMC
;02

sKMC

;DMC?
38R IF KMC AND ALL DONE
;SET RS TO -1 (KMC)
sRESET RO TO START OF TABLE
;G0 DO KMC'S
;RESTORE LOC 6
;RESTORE LOC 4
:SELECT SPECIFIC DEVICES??
:BR IF NO.
;:TYPE THE MESSAGE.
;ZERO DATA LIGHTS
sWAIT FOR USER TO TELL WHAT DEVICES TO RUN
+IS THE NUMBER VALID?
sBR IF NUMBER IS OK.

sTELL USER OF INVALID NUMBER.
;STOP EVERY THING.
sRESTART THE PROGRAM AGAIN.
:GET NEW DEVICE PATTERN
;SHOW THE USER WHAT HE SELECTED.
sCONTINUE DYNAMIC SWITCHES.
:PREPARE TO CLEAR THE FLOATING
sVECTOR AREA. 300-776
:START PUTTING “PCe+2 - HALT"

sIN VECTOR AREA.

;:POP POINTERS
sALL DONE??
:BR IF NO.

sTEST START AND RESTART
003152

003176

012706
013746
013746
005000
012737
005037

001200

.BEGIN: MOV
MOV
MOV
CLR
MoV
CLR

OSTACK
, SP
806, -(SP)
RO

sSET UP STACK
sSAVE LOC 6
sSAVE LOC 4
sSTARY AT O
sSET UP FOR TIME OUT
:70 AUTOSIZE MEMORY

SEQ 27

CzomC

001374
162700
010037

012637
012637
000413
022626
162700
162700
022700
001361
012700
000756
012737
032737
001411
104402
012737
012737
000406
013737
013737
012737
032737
001002
104402
000177

007776
001304
000004
000006

7%:

2%:

000004
007776
030000
037400

000340
000004

177776
001236

006043
000240
000240

003612
003614

003730
003732
010060
000002

003612
003614
001214
001236

005755
175630

10%:

1s:

3s:

43:

Ss:

65:

157776

A52223333RR3%33308 32333873

005720
022700

003202
003204
003210
003212
003216
003222
003226
003232
003234
003236
003242

MACRO V04.00
27-JUN-85 13:16:37 PAGE 25-4
PROGRAM INITIALIZATION AND START UP.

TYPE

(RO)0157776 ,.R0O
63
#7776,R0
RO ,MEMLIM

:BR IF NO

7%
#37400,R0
7%
2340,PS
SITZ. STRTSW

(SP).,304
(SP)+,806
103
(SP)+,(SP)«
#4 ,RO
#7776.R0
©30000,R0

+MLOCK

@NOP,TTST

ONOP ,TTST.2
3
BRMW, TTST
BRX,TTST+2
#CYCLE ,RETURN
#SW01,STRTSH
S$
MR
SRETURN

;CHECK ADDRESS IN RO
:IS IT AT LEAST 28K
;SAVE 2K FOR MONITORS
;STORE MEMORY LIMIT
sRESTORE LOC 4
;RESTORE LOC 6
sCONTINUVE
;ADJUST STACK
sGET LAST GOOD ADDRESS
;SAVE 2K FOR MONITORS
;IS IT 8K?
;BR IF NO
;IF 8K DON'T SAVE 2K

;LOCK OUT INTERRUPTS
;CHECK FOR LOCK ON TEST
sBR IF NO LOCK DESIRED.
sTYPE LOCK SELECTED.
;ADJUST SCOPE ROUTINE.
sSET UP TO LOCK
sCONTINUE ALONG.
;PREPARE NORMAL SCOPE ROUTINE
;LOCK NOT SELECTED, SET UP FOR NORMAL SCOPE LOOP
sSTART AT “CYCLE” FIND WHICH DEVICE TO TEST
:IS TEST NO. SELECTED?
:BR IF YES
:TYPE R
:START TESTING

MACRO V04.00
CzomC
END OF PASS ROUTINE

SEQ 28

27-JUN-85 13:16:37 PAGE 26

;END OF PASS
sTYPE NAME OF TEST
sUPDATE PASS COUNT
sCHECK FOR EXIT TO ACT-11

sRESTART TEST
003364
003366
003372
003376
003402
003410
003414
003420
003424
003430
003434
003440

003444
003450
003454

]

003460
003464

0C3470

0C3474
003476
003504
003512
003516
003520
003522
003522
003524
003526
003530
003532
003534
003542
003546

003550

003552

003554
003556
003560
003562
003564
003566
003570
003572
003574

000005
001234
005037
105037 001325
005237
001230
013777
001230
005733
104402
104402 006072
104411 003546
006100
104402
003554
104411
104402 006106
104411 003562
104402. 006117
003570
104411
013700 001322
013720 001230
001232
013720
005337 001314
001017
112737 000377
013737 001310
013701
000042
001406
000005

004711
000240
000240
000240
000240
012737
000137
000001

010060

006
001404
000001

002

006

002

006

002

004
001374
000001

001230
000001

001232

.EOP:

175570

001327
001314

SENDAD
:

001214

BEQ
RESET

JSR
NOP
NOP
NOP
NOP
RESTRT: MOV
JMP
XCSR:

XVEC:

002

RESET
CLR
CLRB
INC
MOV
TYPE
TYPE
CNVRT
TYPE
CNVRT
TYPE
CNVRT
TYPE
CNVRT
MOV
MOV
MOV
DEC
BNE
MOVB
MOV
MOV

XPASS:

XERR
:

1
.BYTE

gflCSR

LSTERR
ERRFLG
PASCNT
PASCNT ,8DISPLAY
MEPASS

»MCSRX
.XCSR
+MVECX
«XVEC

+MPASSX
+XPASS

+MERRX
. XERR

MILK,RO
PASCNT,(RO)+
ERRCNT,(RO)«

SAVNUM
RESTRT
#377,QV.FLG
DMNUM, SAVNUM
3942, ,R1
RFSTRT

WORLD CLEAN AGAIN.

;CLEAR LAST ERROR PC
;CLEAR ERROR FLAG
;UPDATE PASS COUNT
;DISPLAY PASS COUNT
;TYPE END PASS
;:TYPE CSR
;SHOW IT
;TYPE VECTOR
;SHOW IT
;sTYPE PASSES
;SHOMW IT
;sTYPE ERRORS
;SHOW IT
;GET POINTER TO PASS COUNT
;STORE PASS COUNT FOR THIS DMC11
;STORE ERROR COUNT FOR THIS DMC11
;ARE ALL DEVICES TESTED?
:BR IF NO.
;SET THE QUICK VERIFY FLAG.
;RESTORE THE COUNT
;CHECK FOR ACT-11 OR DDP
sIF NOT, CONTINUE TESTING
;STOP THE SHOW--CLEAR THE WORLD

PC,(R1)

9CYCLE ,RETURN
CYCLE
6,2

.BYTE
gflRVEC

4,2

.BYTE

6.2

PASCNT
1
.BYTE
ERRCNT

:MAKE THE

6.2

;SCOPE LOOP AND INTERATION HANDLER
003576
003602
003604

004737
010016
032777

007606
040000

175370

.SCOPE: JSR
MOV
BIT

PC,CKSWR
RO,(SP)
#81IT714,35WR

;:CKECK FOR SOFT SWR
sSAVE RO ON THE STACK
:“LOOP ON THIS TEST”?

SEQ 29

CZDMC
MACRO VO4.00 27-JUN-85 13:16:37 PAGE 26-1
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

003612
003614
003616
003622
003624
003630
003632
003640
003642
003646
003650
003654
003662

001407
000437
005737
001434
005037
000415
032777
001011
105737
001406
005237
023737
101414

003670
003674
003700
003706
003714
003716
003720
003724
003730
0C3732
003734

005037
005037
012737
013737
011600
022626
013701
000177
001407
000437
000000

TIST:
003734
003734
004000

175342

15:

001327
001224
001224

001222

003664 105037 001325
001224
001220
000020
001216

2s:
001222
001214

3s:

001404
175264

]

BRW:
BRX:
DONE:

BEQ
BR
ST
BEQ
CLR
BR
BIT
BNE
1578
BEQ
INC
cHP
BLOS

1s
33
DONE
33
DONE
2%

:;BR IF NO.
;GOTO 3

;WAS TKCSR DONE SET?

;BR IF NO (LOCKED ON TEST)
;YES, CLEAR FLAG
;GO TO NEXT TEST
;DELETE ITERATION?
(QUICK PASS)
;BR IF YES
;sHAVE PASSES BEECOMPLETED?
;BR IF QUICK PASS.
sUPDATE ITERATION COUNTER
sARE ALL ITERATIONS DONE??
;BR IF NOT YET
;PREPARE FOR NEW TEST
;START ICOUNTER AT O

4SH11,8SWR

LPCNT
%:CNT.ICOUNT

CLRB

ERRFLG
LPCNT
LOCK
€20, ICOUNT
NEXT ,RETURN

CLR
CLR
MOV
MOV
MOV
POP2SP
HOV
JHP
1407
437
O

(IF LOCK SWO1=1; THIS LOC =240)
(IF LOCK SWO1=1; THIS LOC =240)

;RESET ITERATIONS
;:GET NEXT TEST
:POP RO OFF OF THE STACK
sFAKE AN "RTI"
:R1 CONTAINS BASE DMC ADDRESS
:GO DO THE TEST

(SP).RO

DMCSR,R1
SRETURN

sCHECK FOR FREEZE ON CURRENT DATA
003736
003742
003750
003752
003756
003760
003764

004737
032777
001405
005737
001402
013716
000002

007606
001000

175232

001220
001220

.SCOP1: JSR
BIT
BEQ
18T
BEQ
MOV
1$:
RTI

PC,CKSWR
@SW09, SWR
1s

;CHECK FOR SOFT SHWR
;IS SW09=1(SET)?
:BR IF NOT SET.

LOCK
1s
LOCK,(SP)

;GOTO THE ADDRESS IN LOCK.
;GO BACK.

s TELETYPE OUTPUT ROUTINE
003766
003770
003774

010546
017605
062766

004006
004010
004016
004020
004022
004024
004030
004034
004036
004042
004044
004046

001004
032777
001012
105715
100002
104402
105777
100375
112577
001357
012605
000002

000002
000002

004002 005737 010016
010000

.TYPE:

000002

4s:

175164
18:

005672
175154

2s:

175150
3s:

MOV
MOV
ADD

RS5,-(SP)
82(SP),R5
92,2(5P)
SWFLG
1s
#5012, 3SHR
3s

BNE
BIT
BNE
1518
BPL
TYPE
1518
8PL
MOVB
BNE
MOV
RTI
ittt

5?5)0.3TPDBR
(SP)+,R5
b

sSAVE RS ON THE STACK.
;GET ADDRESS OF MESSAGE.
:POP OVER ADDRESS.
sSOFT SWR MESSAGE?
sIF YES TYPE IT OUT REGARDLESS OF SWi12
sINHIBIT ALL PRINT QUT??
:BR IF NO PRINT OUT WANTED (SW12=1)
;IS NUMBER MINUS? (MSB=1(BIT7))

:BR IF NUMBER IS PLUS
;TYPE A CR/LF!
:TTY READY?
sBR IF NO.
;PRINT CURRENT CHAR.
;IF NOT ZERO KEEP PRINTING!
;END OF OUTPUT. RESTORE RS
;G0 HOME
-

SEQ 30

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 26-2
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

004050
004052
004054
004062
004070
004072
004074
004100
004104
004110
004112
004116
004122
004126
004130
004134
004136
004144
004146

010346
010446
017637
062766
104402
000000
012704
012703
105777
100375
117714
142714
122427
001417
105777
100375
017777

005303
001356
012604
012603
104402
010346
010446
000741
012604
012603
000002

.INSTR: MOV

000004
000002

004072
000004

007502
000007
175074

175070

000200
000015

175044

005666

2%:

175046

R3,-(SP)
R4,-(SP)
84(SP), .MSG
#2,4(SP)

MOV
MOV

#INBUF ,R4
#7.R3

INSTL: "I"YPE
MSG:
1$:

175054

MOV
MOV
ADD

7578

STKCSR

MOVB
BICB
CMPB

8TKDBR, (R4)
#200,(R4)
(R4)+,215

BPL

BEQ
1578

BPL
MOV
DEC
BNE
MOV
MOV
.INSTE: TYPE
MOV
MOV

BR
INSTR2: MOV

;SAVE R3 ON STACK
;SAVE R4 ON STACK

INSTR2
@TPCSR

24
S8TKDBR,8TPDBR
R3
1s
(SP)+,R4
(SP)+,R3
.MQM
R3,-(SP)
R4,-(SP)
.INST1

(SP)+,R4
(SP)+,R3

;RESTORE R4
;:RESTORE R3

sCONVERT ASCII STRING TO OCTAL
010546
010446
016605
012537
012537
012537
112537
112537

010566

005005
012704
122714
001420
121427
002415
121427
003012
142714
152405
122714

001406

006305
006305

006305

.PARAM: MOV

004364
004366
004370
004372
004373
000004

007502
000015
000060

000067

000015

MOV
MOV
MOV
MOV
MOV
MOVe
MOV
MOV
PARAM1 : CLR
MOV

CMPB

1¢:

RS5,-(SP)
R4,-(SP)
4(SP),RS
(R5)-,LOLIM
(R5)+ ,HILIM
(RS5)+,DEVADR
(RS)+,LOBITS
(R5)+,ADRCNT
R5,4(SP)
RS
#INBUF ,R4

#15,(R4)

BEQ
CMPB

PARERR
(R4),#60

BGT

PARERR

ASL

BLT
CMPB

B8ICB
BISB
CMPB
BEQ
ASL
ASL

PARERR
(R4),467

#60,(R4)
(R4)+,R5
#15,(R4)
LIMITS
RS
RS

SEQ 31

CZDMC
MACRO VO4.00 27-JUN-85 13:16:37 PAGE 26-3
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)
004306
004310
004312

000760
104404
000750

PARAM1

PARERR : INSTER

;TEST TO SEE IF NUMBER IS WITHIN LIMITS
004314
004320
004322
004326
004330
004334

020537
101373
020537
103770
133705
001365

004366

LIMITS: CHp

R5,HILIM

004364

cHP

R5,LOLIM

BIT8

LOBITS,RS

BHI

BLO

004372

BNE

PARERR

PARERR
PARERR

;STORE NUMBER AT SPECIFIED ADDRESS
004336
004342

004344
004350
004354
004356
004360

0C4362
004364
004366
004370
004372

013704
010524

062705
105337
001372
012604
012605

004370

1s:

000002
004373

MOV
MOV
ADD
DECB

BNE
MOV
MOV

000002
000000
000000
000000
000000

LOLIM:
HILIM:
DEVADR:
LOBITS:

004373

RTI
O
O
0
O

DEVADR,R4
R5,(R4).
#2,RS
ADRCNT

1s
(SP)+,.R4
(SP)+,.RS5

ADRCNT=LOBITS~1
sSAVE PC OF TEST THAT FAILED AND RO-RS

004374

016637

000004

001276

.SAVOS: MOV

4(SP),SAVPC

:SAVE R7 (PC)

;SAVE RO-RS

004402
004406
004412
004416
004422
004426

010537
010437
010337
010237
010137
010037

001272
001270
001266
001264

SV0S:

MOV
MOV

MOV
MOV
MOV
MOV

001260

RTI

RS, SAVRS
R4 ,SAVRS

R3,SAVR3
R2,SAVR2
R1,SAVR1
RO, SAVRO

:SAVE RS
sSAVE R4
;SAVE R3
:SAVE R2
;SAVE R1
:SAVE RO
sLEAVE.

sRESTORE RO-RS

004434
004440

013700
013701

004450
004454
004460

013703
013704
013705

004444

013702

001260
001264
001266
001270
001272

.RESOS:

MOV
MOV
MOV
MOV
MOV

MoV

RTI

SAVRO, RO
SAVR1,R1
SAVR2,R2
SAVR3,R3

SAVR4 R4

SAVRS,RS

;:RESTORE RO
sRESTORE R1
sRESTORE R2
sRESTORE R3

sRESTORE R4

sRESTORE RS

sLEAVE

sCONVERT OCTAL NUMBER TO ASCII AND OUTPUT TO TELEPRINTER

SEQ 32

CZOMC
MACRO v04.00 27-JUN-85 13:16:37 PAGE 26-4
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

004466
004472
004474
004476

104402
010046
010146
010346
010446
010546
017601
062766
012137

112137
112137
013137
122737
001003
042737
013704
113705
012700
010403
042703
062703
110320
000241
006004
000241
006004
000241
006004
005305
001362
012703
114023
105337
001374
105737
001405
112723
105337
001373
105013
104402
005337
001313
012605

005672

000012
000002
004710
004712
004713
004714
000003

177400
004714
004712
001416
177770
000060

.CONVR: TYPE
.CNVRT: MOV

000012

1¢:

MOVB

2%:

MOV

3s:

MOV

004712
004714

LMCRLF

RO, -(SP)
R1,-(SP)
R3,-(SP)
R4,-(SP)
RS5,-(5P)
812(SP),R1
#2,12(SP)

(R1)+,UWRDCNT
(R1)+,CHRCNT
(R1)+,SPACNT
8(R1)+ ,BINWRD
g.CI'RCNT
#177400,BINWRD

BINWRD ,R4
CHRCNT RS
4TEMP,RO

R4 ,R3

#177770,R3
€060,R3
R3,.(RO)+
R4
R4

RS
007544

004712

3
OMDATA,R3

-(RO),(R3).
CHRCNT

004713

007544
004710

012604

012603

012601
012600

sTRAP DISPATCH SERVICE

SEQ 33

CZOMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 26-5
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

sARGUMENT OF TRAP IS EXTRACTED
sAND USED AS OFFSET TO OBTAIN POINTER
;TO SELECTED SUBROUTINE
004716
004720
004724
004730
004732
004736
004742
004746

Ollfil&m

162716
017616
006316
042716
062716
017616
000136

004737
032777
001406
105777
100003
112777
032777
001105
021637
001404
011637
105037
104406
011605

162705

011504
006304
061504
042704
062704
012437
012437
011437

105737
001403
005737
001040
104402
104402
005737
001402
104402
104402
104411

104402
104411

104402

112737
005737
001402

.TRPSR: MOV
SUB
MOV
TRPOK:
BIC

177001

001330
000000

007606
010000

#2,(SP)
8(SP),(SP)
(SP)
#177001,(SP)

#.TRPTAB,(SP)

a(SsP),(SP)
(SP)+

174212
174174

#207,8TPDBR
#5W13,85WR
HALTS

XBX:

{ 2’) LSTERR

(SP),LSTERR

ERRFLG

1s:

(SP),RS

000002

#2,.R5

(R5).R4
R4

(RS).R4

R4
#177001,R4
@.ERRTAB,R4

177001
036362
005172
005204
005216
001325

(R4)+,ERRMSG
(R4)+,DATAHD
(R4) ,DATABP
ERRFLG

005216

DATABP

TYPMSG

005672
005672
001220
006142
006130
005330
006217
005322
005672
177777
005172

;:CLEAR UNWANTED BITS
;POINTER TO SUBROUTINE ADDRESS
:SUBROUTINE ADDRESS
;GO0 TO SUBROUTINE

;BELL ON ERROR?
;:BR IF NO BELL
:TTY READY.

001234
001234
001325

:=PC OF TRAP
:GET TRP
sMULTIPLY TRAP ARG BY 2

;CHECK FOR SOFT SWR

174220

174220
000207
020000

:GET PC OF RETURN

TYPDAT

+MCRLF
+MCRLF

TYPMSG

;DON'T WAIT IF TTY NOT READY.
;PUSH A BELL AT THE TTY.
;DELETE ERROR PRINT OUT?
;BR IF NO PRINT OUT WANTED.
;WAS THIS ERROR FOUND LAST TIME?
:BR IF YES
;RECORD BEING HERE
sPREPARE HEADER
;SAVE ALL PROC REGISTERS
;GET THE PC OF ERROR
;:GET ADDRESS OF TRAP CALL
;GET HLT INSTRUCTION
sMULT BY TWO
;DOUBLE IT
sMULT AGAIN
sCLEAR JUNK
sGET POINTER
sGET ERROR MESSAGE
sGET DATA HEADRER
sGET DATA TABLE
;sTYPE HEADREER
;:BR IF YES
;DOES DATA TABLE EXIST?
sBR IF YES.

sSHOW IT

s TYPE PC.

001325

TYPE

18T

;SHOW IT
;GIVE A CR/LF
;NO MORE HEADER UNLESS NO DATA TABLE.
;IS THERE AN ERROR MESSAGE?
;:BR IF NO.

SEQ 34

MACRO V04.00 27-JUN-85 13:16:37 PAGE 26-6
CZonc
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

005170
005172
005174
005174
005200

104402
000000
005737
001402
104402
000000
005737
001402
104410
000000
104407
022737
001403
005777

100005

010046

016600
000000
012600
005237
032777
001007
032777
001411
013737
012706
013701
000177
000002
000001
006
001276
000001
003
001226

012737
000000
000777

005204

005216

003522

000042

173744
000002
001232
000400

173716

002000

173706

001216
001200
001404
173674

001214

002

TYPE
ERRMSG: 0
WRKD.FM:
ST
BEQ
TYPE
DATAHD : 0
TYPDAT: TST
BEQ
gONVRT
DATABP:
RESREG: RESOS
HALTS:
CcHP
BEQ
TST
BPL
1s:
PUSHRO
MOV
HALT
POPRO
EXITER: INC
BIT
BNE

BIT
BEQ
MOV
1s:
MOV
MOV
JMP
RTI
28:
ERTABO: 1
.BYTE
iAVPC
XTSTN:
.BYTE
TSTNO

;sTYPE

;

DATAHD
TYPDAT

DATABP
RESREG

ERROR MESSAGE

;DATA HEADER?
;BR IF NO
;sTYPE
:
DATA HEADER
;:DATA TABLE?
;BR IF NO.
; SHOW

DATA TABLE

#$ENDAD, 3442

;sRESTORE PROC REGISTERS
;IF ACT-11 AUTOMATIC MODE, HALT!!

2(SP),RO

;HALT ON ERROR?
;:BR IF NO HALT ON ERROR
;SAVE RO
;SHOW ERROR PC IN DATA LIGHTS

ERRCNT
:S‘:HOO « 3SWR

gum. SSWR
NEXT ,RETURN
#STACK,SP
DMCSR,R1
SRETURN

sHALT

;GET RO
;UPDATE ERROR COUNT
;GOTO TOP OF TEST?
;BR IF YES
;GOTO NEXT TEST?

;BR IF NO

;SET FOR NEXT TEST
;RESET SP
;sSET UP R1
;GOTO SPECIFIED TEST
;RETURN

6.2

3,2

;ENTER HERE ON POWER FAILURE

005350

000024

.PFAIL:

MOV
HALT
BR

#RESTART,24

:SET UP FOR POWER UP TRAP
;HALT ON POWER DOWN NORMAL

sPROCESSOR WILL TRAP HERE WHEN POWER IS RESTORED
005350
005350
005356
005362
005366
005372
005376
005400
005404
005410

012737
012706
013701
005037
005237
001375
104402
104411
105037

005336
001200
001404
001416
001416

005675
005430
001325

000024

RESTAR:

MOV
MOV
MOV
CLR

#.PFAIL,24
SP
#STACK,
R1
DMCSR,
TEMP

BNE
TYPE
CNVRT
CLRB

LPFTAB
ERRFLG

INC

TEMP
.-4

JMPFAIL

sSET UP FOR POWER FAILURE
sRESET THE STACK POINTER
sRESTORE R1
sREADY FOR TIMMER
sPLUS ONE TO THE TIMER!
;BR IF MORE TO GO
s TYPE THE MESSAGE
;TELL WHAT TEST TO RETURN TO.
_sSTART CLEAN

SEQ 35

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 26-7
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)
005414
005420
005422
005424
005430

005037
005011
104412
000177
000001

005434

001226

005432

001234
173564

003

002

005436
005444
005446

012777
104414
121111

000020

005450
005452
005454
005462
005464

104414
121224
032777
001772
000002

005436

005450

005466
005466
005474
005502

005504

005504
005512
005516
005522
005530
005532
005534
005542
005550

005552

005552
005556
005562
005570
005576
005604
005610
005612
005614

173746

000020

173730

152777
142777
000002

000100
000300

173712
173704

152777
013677
062746
032777
001401
000000
152777
142777
000002

000002
173676
000002
000100

173674

000003
000007

173644
173636

001416
000002
000020
173610
000020
001416

005616
005616
005622

013637
062746

001416
000002

005626
005630
005632
005640

104414
021364
032777
001772

005642
005644

104414
021364

005642

.BYTE

.DELAY:

18:

013637
062746
152777
027777
142777
005337
001364
000002

005626

PFTAB:

.MSTCLR:

.ROMCLK:

173452
1$:

LSTERR
(R1)
SRETURN

173616
173606
173602

1$:

1s:
173552

2%:

;CLEAR MAINT BITS
;START CLEAN UP OF DEVICE
;START DOING THAT TEST AGAIN.

TSTNO
MOV
ROMCLK
121111

ROMCLK
121224
BIT
BEQ
RTI

#20,87MP04

#BI74.%20MP04
14

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;POKE CLOCK DELAY BIT
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;PORT4_IBUS#+11
;IS CLOCK BIT SET?
;BR IF NO

BISB
BICB
RTI

#8176, 3DMCSRH
;SET MASTER CLEAR
#BIT6!BIT7,8DMCSRH
;:CLEAR MASTER CLEAR AND RUN

BISB
MOV
ADD
BIT
BEQ
HALT
BISB
BICB
RTI

#8IT1,80MCSRH
8(SP
)+ ,8DMPO6

sRETURN

;SET ROMI
;LOAD INSTRUCTION IN SEL6
sADJUST STACK
:&;:HOG.OSIR
sHALT IF SW06 =1
:BR IF SWO6 =0
sHALT BEFORE CLOCKING INSTRUCTION
©8IT1:BITO,8DMCSRH ;CLOCK INSTRUCTION
#BIT2!BIT1!BITO,8CMCSRH
;CLEAR ROMO, ROMI, STEP

MOV
8(SP)+,TEMP
ADD
BISB
#81T74,80MCSRH
CcMP
SDMCSR, 8DMCSR
BICB
#8174, 80MCSRH
DEC
BNE
RTI
.BLKW 1

.TIMER:

".......l..

3,2

.DATACLK:

34:

000002

CLR
CLR
MSTCLR
JMP
1

MOV
ADD
ROMCLK
021364
BIT
BEQ
ROMCLK
021364

8(SP)+,TEMP
#2,-(SP)

¢2,80MPO4
1s

;PUT TICK COUNT IN TEMP
sADJUST STACK
:SET STEP LV
sWASTE TIME
sCLEAR STEP LU
sDEC TICK COUNT
:BR IF NOT DONE
sRETURN

sMOVE COUNT TO TEMP

+ADJUST STACK

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;PORT4_IBUS+ REG11

;IS PGM CLOCK BIT CLEAR?
sBR IF YES

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

;PORT4 _IBUS+ REG11

SEQ 36

MACRO V04.00
27-JUN-85 13:16:37 PAGE 26-8
CZpMC
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

005646
005654
005656
005662
005664

032777
001372
005337
001361
000002

005666
005672
005675
005733
005755
005760
006005
006031
006043
006072
006100
006106
006117
006130
006142
006144
006217
006224
006263

040
015
377
377
377
377
377
377
377
103
126
120
105
124
052
377
120
212
377
212
377
377
377
377
377
377

006322
006374
006450
006510
006526
006547
006606
006704

377

007016
007054
007114
007154
007205
007215
007223
007277
007320
007330
007340

377
377
377
377
377
116
377
377
040
040
377

007454
007456
007460
007462
007464
007466
007470
007472
007474
007476
007500

000005
006
001246
006
001250
006
001252
006
001254
006
001256

000002

BIT
BNE
DEC
BNE
RTI

#2,3DMP04

MaM:

.ASCIZ

MPFAIL:

.ASCIZ

<377>/PUR FAILED.

173536

001416

040
012
120
105

122
116
111
124
114
123
105
101
122
105
000
123

103

040
040
055

110
103
126
102

111
127

123
123
111
116

012

377
105
050
050
104

003

077

127
116

117
116
105
117
122
103
123
122
123

105

072

055
117
123
105
122
106
110

127

127
123
117
123
127
104
104
113
115

MCRLF:

MEPASS:
MR:
MERR2:
MERR3:
MTSTPC:
MLOCK:
MCSRX:
MVECX:
MPASSX:
MERRX:
MTSTN:
MASTEK:
MNEW:
MERRPC:
XHEAD:

NUM:

CSR:

VEC:

PRIO:
CRAM:
MODU:
LINE:

BM:
CONN:
NOACT:
SWMES:
SWMESL1:
CONERR:
CNERR:
DMCM:

KMCM:
SPEED:

.ASCIZ

.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCII
.ASCII
.ASCII
.ASCIZ

.ASCIZ
.ASCIZ

.ASCIZ

.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ

.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ

.ASCIZ
.ASCIZ

.EVEN
XSTATQ: 5

.BYTE

003

003
003
002

.EVEN

TEMP1
.BYTE
TEMP2
.BYTE
TEMP3
.BYTE
TEMP4
.BYTE
TEMPS

;IS PGM CLOCK BIT SET?

:BR IF YES

;BR_IF NOT DONE

TEMP

;:DEC COUNT
sRETURN

<15>¢<12>

RESTART AT TEST /

<377>/END PASS CZDMC
7/
<377>/R/
<377>/N0 DEVICES PRESENT./

<377>/INSUFFICIENT
<377>/TEST PC-/

DATA!/

<377>/L0OCK ON SELECTED TEST/

/CSR: /
/VEC: /
/PASSES: /
/ERRORS: /
/TEST NO: /
/%/

;SZ'D;SET SWITCH REG TO DMC11'S DESIRED ACTIVE./

<212>/

€IT?>»/

<212>/

MAP OF DMC11 STATUS/
cccccccncscccmccee-

<377>/--=---<377>/HOW MANY DMC11'S TO BE TESTED?/
<377>/CSR ADDRESS?/
<377>/VECTOR ADDRESS?/

<377>/BR PRIORITY LEVEL?

(4,5,6,7)72/

<377>/IF DMC HAS CRAM (M8204) TYPE "Y”, IF CROM (M8200) TYPE “N” 2/
<377>/WHICH LINE UNIT? IF NONE TYPE "N". IF M8201 TYPE 1", IF M8202 TYPE "2
<377>/SHITCH PAC#1 (DDCMP LINE #)72/
<377>/SHITCH PAC#2 (BM873 BOOT ADD)?/
<377>/71S THE LOOP BACK CONNECTOR ON?/
<377>/NO DEVICES ARE SELECTED/
<377><12>/5UR= /
/NEM? /
€377><377>/DMC11 FOUND AT NON-STANDARD ADDRESS
«377>/EXPECTED FOUND/
/7 (DMC) /

/ (KMC) /

PC:

«377>/DMC11-AR(REMOTE,LOW SPEED) OR DMC11-AL(LOCAL
,HIGH SPEED) TYPE “R” OR ”

6,3

6,3
6,3
6.2

SEQ 37

CZDMC
MACRO v04.00
27-JUN-85 13:16:37 PAGE 26-9
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

sBUFFERS FOR INPUT-OUTPUT
007502
007544

000000

INBUF:

000000

MDATA:

007544

.=.+40

007606

.=.+40

;ROUTINE USED TO CHANGE SOFTWARE SWITCH

;REGISTER USING THE CONSOLE TERMINAL
50

007606

022737

007614
007616
007622
007624
007632
007640
007642
007650
007652
0C7654
007656
007660
007666
007670
007674

001077
105777
100003
012737
022777
001404
022777
001061
010246
010346
010446
012737
005002
012704
104402

007702
007704
007710
007714
007720
007722
007726
‘007730
007734
007736

010052
104402
004737
022703
001424
022703
001416
022703
001754
022703

007744
007746
007752
007754
007756
007760
007762
007764

005004
042703
006302
006302
006302
050302
000752
012766

007774
007776
010002
010006

001002
010277
005037
012604

007700

007742

007772

010010
010012
010014

104411

001762

005704

012603
012602
000207

000176

001202

171362

177777
000007

003734
171346

000207

171336

177777

010016

177777
007205

CKSWR:

CMP

SOFTSW
CKSWR3: TYPE
CKSWR4: JSR
cMP
BEQ
cHP
BEQ
CMP
BEQ
cMP

000012
000025
000007

BEQ

177770

171200
010016

BNE
TST8
BPL
MOV
2%:
CHMP
BEQ
CMP
BNE
1%:
MOV
MOV
MOV
MOV
CKSWR1: CLR
MOV
TYPE

CKSWR2: CNVRT

007215
010020
000015

002002

000006

45:

S$:

6$:

CLR
8IC
ASL
ASL
ASL
8IS
BR
MOV
TST

BNE
MOV
CLR
MOV

MOV
MOV
CKSWRS: RTS

o
e
5
i

#SWREG, SWR

CKSWRS
STKCSR
2%
#-1,DONE
#7,8TKDBR
13
#207,8TKDBR
CKSWRS
R2,-(SP)
R3,-(SP)
R4,-(SP)
#-1,SWFLG
R2
®-1,R4
+SWMES
+SWMES1
PC . INCHAR
15,R3
54
#12.R3

#25.R3
CKSWR1
#7.R3
CKSWR4
R4
#177770,R3
R2
R2
R2
R3,R2
CKSWR4
@.START,6(SP)
R4
64
R2,8SHR
SWFLG
(SP)+,R4
(SP)+,R3
(SP)+,R2
PC

;IS THE SOFT SWR BEING USED?

:BR IF NO
;IS DONE SET?
;GO ON IF NOT SET
:IF DONE SET, SET FLAG
sWAS CTRL G TYPED? (7 BIT ASCII)
:BR IF YES
sWAS CTRL G TYPED? (8 BIT ASCII)
:BR IF NO
:STORE R2
sSTORE R3
sSTORE R4
:SET SOFT TYPE OUT FLAG
sCLEAR NEW SWR CONTENTS
:SET FLAG TO ALL ONES
:TYPE “SWR= *
s TYPE OUT PRESENT CONTENTS

;OF SOFT SWITCH REGISTER
;TYPE “NEW? *
;GET RESPONSE
:WAS IT A CR?
;:BR IF YES
sWAS IT A LF?
;:BR IF YES
sWAS IT CTRL V?
:BR IF YES(START OVER)
+IF CNTL G GET NEXT CHAR

+IT MUST BE A DIGIT SO CLR FLAG
sONLY 0-7 ARE LEGAL SO MASK OFF BITS
sSHIFT R2 3 TIMES
sADD LAST DIGIT
:GET NEXT CHARACTER
;LF WAS TYPED SO GO TO START
:IS FLAG CLEAR?

;IF NOT DON'T CHANGE SOFT SWR
sIF YES THEN WRITE NEW CONTENTS TO SOFT SWR
;CLEAR TYPEQUT FLAG
sRESTORE R4
sRESTORE R3
;RESTORE R2
:RETURN

SEQ 38

CZoMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 26-10
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)
010016
010020
010024
010026
010032
010036
010040
010044
010050

105777
100375
017703
105777
100375
010377
042703

010052
010054
010056

000001

000207

000176

171160
171154
171152

171146
000200

002

SWFLG:

INCHAR:

TSTB
BPL
MOV
TST8

BPL
MOV
BIC

RTS

SOFTSW: 1
.BYTE
SWREG

ar:csa_

STKDBR,R3
n:csa

R3.8TPDBR

#8IT7,R3
PC

6,2

SEQ 39

CZDOMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

sROUTINE USED TO “CYCLE” THROUGH UP TO 16 DMC11'S
;THIS ROUTINE SETS UP THE CONTROL ADDRESS FOR THE DIAGNOSTIC
sAND RUNS THE SPECIFIED DMC11’'S.
THIS ROUTINE #MUST#
;BE RUN FIRST BEFORE ENTERING THE DIAGNOSTIC FOR THE
sSETUP NECESSARY.
;

010060 005737
010064 -001004
010066
104402
010072 000000
010074 000776
010076 000241
010100 006137
010104
005537
010110 062737
010116
062737
010124 022737
010132
001006
010134 012737
010142 012737
010150 033737
010156 001747
010160 013700
010164 013702
010170 012037
010174 011037
010200 042737
010206 012037
010212 012037
010216 012037
010222 012237
010226 012237
010232 012700
010236 013737
010244 005237
010250 013737
010256 005237
010262 013737

010270
010274
010302

060037
013737
060037

010306
010314
010320
010332
010340

013737
060037
013737
060037
013737
060037

010344
010352

032737
001450

010354
010360

005737
001045

010354

001306

CYCLE:

007154

001316
001316

1%:

000010
001700

001322
001320
001320

001500
001702
001316

001320
001322
001306

24:

001320
001322

001404
001374
177000
001366
001370
001372

001374

001230
001232

001404
001406
001406
001410
001410
001412
001412
001414

001374
001376
001376
001400
001400
001402

001406
001410

001412
001414
001376

001400
001402

001236

43:

DMACTV

TYPE
HALT
BR
CLC
ROL
ADC

+NOACT

RUN
RUN

BIT

SDM.MAP , CREAM
SCNT .MAP ,MILK
RUN,DMACTYV

sRESET ADDRESS POINTER.
;RESET PASS COUNT POINTER
sIS THIS ONE ACTIVE?

MOV

MILK,R2

3sGET PASS COUNT POINTER

BNE

ADD
ADD
CMP
BNE
MOV
MOV

BEQ
MOV

.-2

sARE ANY DMC11'S TO BE TESTED?

iBR IF OK.

sNO DMC11'S SELECTED!!
:STOP THE SHOM.
;DISQUALIFY CONT. SW.
;CLEAR PROC. CARRY BIT.
sUPDATE POINTER
;CATCH CARRY FROM RUN
sUPDATE POINTER
;UPDATE ADDRESS POINTER.

94 ,MILK
10, CREAM
#DM.MAP+200, CREAM
24
;KEEP GOING; NOT ALL TESTED FOR.

1
CREAM, RO

sBR IF NO
:GET ADDRESS POINTER

MOV
MOV
B8IC
MOV
MOV
MOV
MOV
MOV
MOV
MOV
INC
MoV
INC
MOV
ADD
MOV
ADD

(RO)+,DMCSR
(RO) ,DMRVEC
#177000,DMRVEC
(RO)+,STAT1
(RO)+,STAT2
(RO)+,STAT3
(R2)+,PASCNT
(R2)+,ERRCNT
#2,R0
DMCSR,DMCSRH
DMCSRH
DMCSRH ,DMCTL
DMCTL
- DMCTL
, OMPO4
RO ,DMPO4
DMPO4
, DMPO6
RO ,DMPO6

sLOAD SYSTEM CTRL. REG
sLOAD VECTOR
;CLEAR UNWANTED BITS
sLOAD STAT1
;LOAD STAT2
sLOAD STAT3
sLOAD PASS COUNT
;LOAD ERROR COUNT
:SAVE CORE THIS WAY!

MOV
ADD
MOV
ADD
MOV
ADD

OMRVEC.DMRLVL
RO,
VL
DMRLVL ,.DMTVEC
RO ,DMTVEC
DMTVEC,DMTLVL
RO,DMTLVL

;PTY LVL
:
;TX VEC
s
;TX LVL

BIT
BEQ

#SHO01, STRTSH
78

sIS TEST NO. SELECTED
sBR IF NO

157

aodae

sRUNNING IN AUTO MODE?

BNE

iBR IF YES

SEQ 40

CZOMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-1
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)
010362
010366
010370
010372
010374
010376
010400

104402
104403
006130
104405
000001
001000
001226

005672

010404
010410
010412
010414
010416
010424
010426
010434
010436
010442
010446
010454
010456
010460
010464
010466

012700
022710
012737
001020
023760
001014
022760
001010
010037
104402
042737
000412
005720
020027
001351
104402

012320

010402
010403

000
001

010472

000730

010474
010502

012737
013701
000177

010506

TYPE

.BYTE
.BYTE
5%:

001226

000002

001226

000004

001214
005755
000002

001236

6%:

033776
005666
012320
001404

001214

170502

7%:
8s:

INSTR
MTSTN
PARAM
1
1000
TSTNO
0
1
MOV
cMP
MOV
BNE
cHpP
BNE
cMP
BNE
MOV
TYPE
BIC
BR
TST
cMP
BNE
TYPE
BR

MOV
MOV
JHMP

JMCRLF

#TST1,RO
(PC)+,(RO)
(PC)+,a8(PC)63
;gTNQ.Z(RO)

:IST'Q.‘(RO)
RO ,RETURN
MR
@SWO01,STRTSW
83

(RO)»

sGET TEST NO.

;CMP FIRST WORD TO 12737
sBR IF NOT SAME
sDOES TSTNO MATCH?
:BR IF NO
sIS LAST WORD 0K?

:BR IF NO
sIT IS A LEGAL TEST SO DO IT

:POP RO
;AT END YET?
:BR IF NO
:YES ILLEGAL TEST NO.

RO,&TLAST-10
5%
.MQM
4%

sTRY AGAIN

@TST1,RETURN
DMCSR,R1
SRETURN

sPREPARE RETURN ADDRESS
;R1 = BASE DMC11 ADDRESS
;GO START TESTING.

sROUTINE USED TO “AUTO SIZE” THE DMCi1
;CSR AND VECTOR.
THE CSR MAY BE ANY WHERE IN THE FLOATING
sNOTE:
ADDRESS
RANGE (160000:164000)
;
:
H

AND THE VECTOR MAY BE ANY WHERE IN THE
FLOATING VECTOR RANGE (300:770)

010512
010512
010514
010520
010522
010526
010530
010534
010540
010544
010552
010554
010560
010566
010570
010572
010574

000005
012702
005022
022702

001374
005037

012702
005037
032737
001002
000137
012737
104403
006450
104405
000001

001500
001700
001310
001500
001306
000001

001236

011252
000001

001256

AUTO.SIZE:
RESET
CSRMAP: MOV
18:
CLR
cHe
BNE
CLR
MOV
CLR
BIT
BNE
JMP
MOV
INSTR
NUM

PARAM
1

#DM.MAP,R2
(R2)+
#0M.END,R2
13
DMNUM
SDM.MAP,R2
DMACTYV
#5H00, STRTSW
.+6
78
#1,TEMPS

;INSURE A BUS INIT.
;sLOAD MAP POINTER.
;ZERO ENTIRE MAP
sALL DONE?
sBR IF NO
:SET OCTAL NUMBER OF DMC11'S TO O
sR2 POINTS TO DMC MAP
;CLEAR ACTIVE
sQUESTIONS?
sBR IF YES
;IF NO SKIP QUESTIONS
sSTART WITH 1

——

—

SEQ 41

MACRO v04.00
27-JUN-85 13:16:37 PAGE 27-2
CZ0MC
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

010576
010600
010602
010603
010604
010612
010616
010620
010622
010626
010630
010632
10634
010636
010640
010642
010643
010644
010650
010652
010654
010656
010660
010662
010664
010665
010666
010672
010674
010676
010702
010706
010710
010714
010716
010722
010724
010726
010730
010734
010736
010740
010742
010744
010746
010750
010752
010756
010762
010764
010770
010772
010774
010776
011000
011002
011004

000020
001252
000
001
013737
104402
104410
012002
005237
104403
006510
104405
160000
164000
001254
000
001
013722
104403
006526
104405
000000
000776
001254
000
001
013712

104402

006547
004737
022703
101014
022703
103411
012704
006303
005304
001375
042703
050312
000403
104402
005666
000752
104402
006606
004737

022703
001427
022703
001403
104402
005666
000763
104402
007340
004737

001252

005672

001310

12%:

16.
TEMP3
.BYTE
.BYTE
MOV
TYPE

CONVRT

WHICH
INC

001256

INSTR
CSR

TEMP3, DMNUM

MCRLF

;DMNUM = HOW MANY
:TYPE WHICH DMC IS BEING DONE
sTEMPS IS WHICH DMC

TEMPS

PARAM

160000
164000

TEMPS

.BYTE
.BYTE
MOV
INSTR
VEC

001254

TEMP4, (R2)+

sSTORE CSR IN MAP

PARAM

0
776
TEMP4

001254

10s:

012266
000024

.BYTE
.BYTE
MOV

TYPE
PRIO
JSR

CcHP
BHI
cMP
BLO
MOV
ASL
DEC
BNE
8IC
BIS
BR

000027
000011

170777

TYPE

MaM
BR

TYPE

CRAM
JSR
cMP
BEQ
CHP
BEQ

012266
000131

000116

TYPE
MQM

40%:

012266

TEMP4, (R2)

sSTORE VECTOR IN MAP

PC,INTTY

sASK WHAT BR LEVEL
sGET RESPONSE

924 ,R3

;BR IF GREATER THAN 7
;R4 = NUMBER OF SHIFTS
:SHIFT R3 LEFT
.-4
9170777,R3
R3,(R2)

sDEC SHIFT COUNT

;:BR IF NOT DONE
:BIC UNWANTED BITS
;PUT BR LEVEL IN STATUS MAP
sCONTINVE

10¢

sRESPONSE IS OUT OF LIMITS
:TRY AGAIN

PC,INTTY

;DOES DMC HAVE CRAM?
:GET REFLY

#131,R3
9s
¢116,R3
408

SPEED
JSR

PC,INTTY

TYPE

;

:BR IF LESS THAN 4

;YES
;NO
sNOT

A YOR N

sTYPE *2*

sASK AGAIN

sDMC11-AR OR DMC11-AL?

:GET RESPONSE

SEQ 42

CZOMC
MACRO v04.00 27-JUN-85 13:16:37 PAGE 27-3
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)
011010
011014
011016
011022
011024
011026
011030
011032
011040
011042
011046
011050
011052
011056
011062
011064
011070
011072
011076
011100
011102
011104
011106
011112
011114
011116
011122
011124
011126
011132
011136
011140
011144
011146
011150

011152

011154

011160

011162
011166
011166

011170
011172
011174

011176
011200
011202
011203
011204
011210
011212
011214
011216
011220
011222
011224
011225

022703 000122
001414
022703
000114
001403
104402
005666
000763
052762
000002
000402
052712
100000
104402
006704
004737
012266
022703
000021
001417
022703
000022
001412
022703
000116
001403
104402
005666
000760
052722 010000
022222
000447
052712
020000
104402
007114
004737
012266
022703
000131
001406
022703
000116
001406
104402
005666

000763

000004

41s:
9s:
165:

32%:
31s:
304:

CcHP
BEQ
cMP
BEQ
TYPE
MaM
BR
BIS
BR
BIS
TYPE
MODU
JSR
CMP
BEQ
CMP
BEQ
CMP
BEQ
TYPE
MQM
BR
BIS
CHP
BR
BIS
TYPE
CONN
JSR
cMP
BEQ
CHMP
BEQ
TYPE
MQM

052722

040000

17s%:

BIS

042722

040000

18s:
19s:

BIC

000402

104403
007016
104405
000000

000377
001254
000
001
113722

104403
007054
104405

000000
000377
001254

000
001

001254

€122,R3

;IS IT R

40%
#81IT1,4(R2)
16%
#B81IT15,(R2)

:TRY AGAIN

16$
€114 ,R3
41

PC,INTTY
@21,R3

:BR IF REMOTE
315 IT L
;:BR IF LOCAL

;SET BIT1 IN STAT3
s CONTINVE
:SET BIT 15 IF CRAM

;ASK WHICH LINE UNIT

sGET REPLY

’uln

30%

#22,R3

31¢
#116,.R3
328
16$
#BIT12,(R2)+
(R2)+,(R2)+
33$
#8IT13,(R2)

PC,INTTY

#131,R3
173
#116.R3
18¢

30¢
#B81IT14,(R2)+
194
9BIT14,(R2)-

3n2u

‘MNM

:IF NOT A 1,2 OR N TYPE »2*
;TRY AGIAN
;SET BIT 12 IN STAT2 IF NO LU
;POP OVER STAT2 AND STAT3
sSET BIT 13 IN STAT2 IF M8202
;ASK IF LOOP-BACK IS ON

;:GET REPLY

;N
;IF NOT Y OR N TYPE "2~
sTRY AGAIN
;sTURNAROUND IS CONNECTED

sNO TURNAROUND

INSTR
LINE
PARAM
0

377
TEMP4
.BYTE
.BYTE
MovB

INSTR
8M
PARAM

0
377
TEMP4
.BYTE
.BYTE

TEMP4,(R2)

sSTORE SWITCH PAC IN MAP

SEQ 43

CZOMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-4
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)

011226
011232

011234
011240
011242
011246
011252
011256
011264
011266
011270

011272
011276

011302
011304

113722
005722

005337
001402
000137
000137
012701
012737
005011

005711
001172
005061
005761

001165
012711

001254

001252

33s:

010612
011702
160000
011774

34%:
7%:

000006
000006

000004

100000

000002

005061
012761
052711
022761
001004
052762
000431
012711
012761
012711
012711
022761
001411
022761
001410
022761
001404
000516
052762

011430
011432

010122
012711

001000

011450

052711

000400

011454
011462
011466
011474
011476
011502
011504
011512
011514
011520
011522
011530
011532
011540
011546
011552
011560

005061
012761
012761
052711
122761
001003

000006

001000
100430
001400
002000
016472

000006

016461

000006

177777

000006

000002

000006

000004
122113

021264
000400
000377

000006

000006
000006

000004

052712
000436
032761
001403

010000

032761
001023

000010

000004

000100
122113
000400
021264
000400

000004
000006

052712
000427
012761
012761
052711
012761
052711

000002

2%:

DEC
BEQ
JMP
JMP
MOV
MOV
CLR
TST
BNE
CLR
TST

002000
000004
125252
020000
125252

011310
011314
011322
011326
011334
011336
011344
011346
011352
011360
011364
011370
011376
011400
011406
011410
011416
011420
011422

011436
011442

000004

MOVB
TST

000004

060000

000006

TEMP4,(R2)+
(R2)+

TEMP3
34
12%
13$
#160000,R1
263,804
(R1)
(R1)
3s
6(R1)
6(R1)

;STORE SWITCH PAC IN MAP
;POP OVER STAT3

;DEC DMC COUNT
;:BR IF DONE
;JUMP IF NOT
; CONTINUE
;SET FOR FIRST ADDRESS TO BE TESTED
:SET FOR NON-EXISTANT DEVICE TIME OUT
;CLEAR SELO

:IF DMC11 DMCSR S/B 0
:IF NO DEV ; TRAP TO 4. IF NO BIT 8 THEN NO DMC11
:CLEAR SEL6
:IF DMC11 THEN DMRIC S/B =0!

BNE
3$
;:BR _IF NOT DMC11
MOV
#B8IT10,(R1)
:SET ROMO
CLR
4(R1)
;:CLEAR SEL4
MOV
#125252,6(R1)
;;WRITE THIS TO SEL6
BIS
#81713,(R1)
sWRITE IT!
cMP
#125252,4(R1)
;WAS IT WRITTEN?
BNE
21¢
:IF NO IT IS NOT CRAM
BIS
#BIT15,2(R2)
;SET BIT15 IF CRAM
BR
224
21%:
MOV
#8IT9,(R1)
;SET ROMI
MOV
#100430,6(R1)
;PUT INSTRUCTION IN SEL6
MOV
#B8IT9!BIT8,(R1) ;CLOCK INSTRUCTION (MICRO PROC PC TO 0)
MOV
#8IT10,(R1)
:SET ROMO
cMP
#016472,6(R1)
;IS IT LOCAL CROM?
BEQ
234
:BR IF YES
CMP
#016461,6(R1)
;IS IT REMOTE CROM?
BEQ
224
:BR IF YES
CHMP
¢-1,6(R1)
;NO CROM?
BEQ
224
:BR IF YES
BR
3
;NOT A DMC
23%:
BIS
#BIT1,6(R2)
;SET BIT 1 IN STAT3
;AT THIS POINT IT IS ASSUMED THAT R1 HOLDS A DMC1i CSR ADDRESS.
22%:
MOV
R1,(R2)+
:STORE CSR IN CORE TABLE.
15s:
MOV
#8IT79,(R1)
;CLEAR LINE UNIT LOOP
CLR
4(R1)
;:CLEAR PORT4
MOV
9#122113,6(R1)
;LOAD INSTRUCTION (CLR DTR)
BIS
#8178,(R1)
sCLOCK INSTRUCTION
MOV
9021264 ,6(R1)
;LOAD INSTRUCTION
BIS
#B8178,(R1)
;CLOCK INSTRUCTION
CMPB
#377,.4(R1)
sIS IT ALL ONES?
BNE
.+10
sBR IF NO
BIS
#81IT712,(R2)
;IF YES, NO LINE UNIT, SET STATUS BIT
BR
20%
BIT
#81IT1,4(R1)
sIS SWITCH A ONE?
BEQ
.+10
:BR IF M8201
BIS
#BIT13:81IT714,(R2) ;MB8202 ASSUME CONNECTOR
BR
204
3CONNECTOR ON)
BIT
#BIT73,4(R1)
;IS MRDY SET
BNE
204
;BR IF M8201 NO CONNECTOR (ON LINE)
MOV
#B8176,4(R1)
;LOAD PORT4
MOV
#122113,6(R1)
;LOAD INSTRUCTION
BIS
MOV
BIS

981I78,(R1)
#021264,6(R1)
#B8178,(R1)

;CLOCK INSTRUCTIONCSET DTR)
;LOAD INSTRUCTION
;CLOCK INSTRUCTIONCREAD MODEM REG)

SEQ 44

CZoMC
MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-5
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)
011564
011572
011574
011600
011602
011610
011614
011620
011626
011632
011636
011640
011642
011646
011654
011656
011660
011664
011670
011674
011676
011702
011706
011712
011714
011720
011724
011726
011732
011736
011740
011742
011750

032761
001402
052712
005722
012761
012711
156122
012761
012711
156122
005722
005011
005237
022737
001412
005011
005061
062701
022701
001402
000137
005037
005737
001423
013701
010137
000241
006137
005237
005301

011756
011762
011766
011770
011772
011774
012000

001371
012737
013737
000137
104402
005000
000000
000776
012716
000002

012002
012004
012006

000001
002
001256

012010
012016
012020
012026
012034
012040
012044
012050
012052
012056
012060
012064

032737
001114
012737
012737
012702
012700
012701
010120
012721
022021
020127
101

000010

000004

040000
021324

001400

000004
021344
001400

000004

001310
000020

001310

3s:

000006
000010
164000

145:

011264
001306
001310

13s:

001310
001314

4s:

001306
001306
000006
001306
012010
005760

000004
001312
5s:

011664

6%:
WHICH:

002

001236

000340
012202
001500
000300
000302

000022
000020

001000

CLR

TST
BEQ
MOV
MOV
CLC
ROL
INC
DEC
BNE
MOV
MOV
JMP
TYPE
CLR
HALT
BR
MOV
RTI
1

.BYTE

TEMPS

000001

000004

BIT
BEQ
BIS
18T
MOV
MOV
BISB
MOV
MOV
BISB
TST
CLR
INC
cMp
BEQ
CLR
CLR
ADD
cMP
BEQ
JMP

VECMAP: BIT
BNE
MOV
MOV
MOV
MOV
MOV
1$:
MOV
MOV
cHp
cMP
BLOS

#BIT3,4(R1)
20$
#81I714,(R2)
(R2)+
9021324,6(R1)
#8IT9!BIT8,(R1)
4(R1),(R2)+
#021344,6(R1)
#8IT8!BIT9,(R1)
4(R1),(R2)+
(R2)+

(R1)

DMNUM

20, DMNUM

13$
(R1)
6(R1)

#10,R1
#164000,R1

13
24
DMACTV
DMNUM
S5
DMNUM,
R1
R1,SAVNUM
DMACTV
DMACTV
R1
48
96,804

DMACTV,SAVACT
VECMAP
+MERR2
RO
.=2
#14$,(SP)

;IS MRDY SET NOW?
:BR_IF NO CONNECTOR
:SET STATUS BIT FOR CONNECTOR
;POP POINTER
;PUT INSTRUCTION IN PORT6
;PORT4
LU 15
;STORE DDCMP LINE # IN TABLE
;PORT6_INSTRUCTION
;CLOCK INSTR.
;STORE BM873 ADD IN TABLE
;POP OVER STAT3
;CLEAR ROMI
;UPDATE DEVICE COUNTER
sARE MAX. NO. OF DEV FOUND?
:YES DON'T LOOK FOR ANY MORE.
;CLEAR BIT 10
;CLEAR SEL 6

;UPDATE CSR POINTER ADDRESS
;:BR IF DONE
:JUMP IF NOT

:WERE ANY DMC11’'S FOUND AT ALL?
:ERROR AUTO SIZER FOUND NO DMC11'S IN THIS SYS.
:SAVE NUMBER OF DEVICES
:GENERATE ACTIVE REGISTER OF DEVICES.
:SET THE BIT

;:BR IF MORE TO GENERATE
sRESTORE TRAP VECTOR
sSAVE ACTIVE REGISTER
;GO FIND THE VECTOR NOW.
sNOTIFY OPR THAT NO DMC11‘'S FOUND.
sMAKE DATA LIGHTS ZERO
:STOP THE SHOMW
;DISABLE CONT. SW.
;ENTERED BY NON-EXISTANT TIME-OUT.
sRETURN TO MAINSTREAM

2.2
;?UOO.STRTSH

#340,8022
&44%,8620

#DM.MAP,R2

#300,R0
#302,R1
R1,(RO)+

(RO)+,(R1).

g%.oxooo

sSET IOT TRAP PRIO TO 7
:SET I0T TRAP VECTOR
sSET SOFTWARE POINTER
sFLOATING VECTORS START HERE.
;PC OF IOT INSTR.
sSTART FILLING VECTOR AREA
sWITH .+2; I0T
;ADD 2 TO RO sR1
;BR IF MORE TO FILL

SEQ 45

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-6
GENERAL UTILITIES (TYPEOUT, ERROR, SCOPE, ETC)
012066
012074
012100
012102
012106
012114
012116
012124
012130
012136
012142
012144

012146
012152
012154
012162
012164
012172
012174

013737
006037
103063
012704
016437
011201
012761
012711
012761
012711
105200
001376
162704
001404

016437

012230
012234
012240
012242
012246
012250

000767
052762
005011
062702
000735
051662
042762
016405
006305
006305
006305
006305
042705
050562
022626
012716
000002
000207

012252
012254
012256
012260
012262
012264

000000
000000
000200
000240
000300
000340

012266
012272
012274
012300

105777
100375
017703
105777
100375
010377
042703
000207

012200

012202
012206
012214
012220
012222
012224
012226

012304

012306

012312
012316

001306
001246
000012

001246

012252

177776

000200
001000
121111
001400

000004

2%:

000006
7%:

000002

012252

177776

005300

000002

000010
000002
000007
012254

000002

6%:
34:
4%:

170777
000002
012172
5%:

166712
166706
166704
166700
000240

HOV
ROR
BCC
MOV
MOV
MOV
MOV
MOV
MOV
MOV
INCB
BNE
SuB
BEQ
MOV
BR
BIS
CLR
ADD
BR
BIS
BIC
MOV
ASL
ASL
ASL
ASL
BIC
BIS

CMP
MOV
RTI
RTS

DMACTV,TEMP1
TEMP1
5%
#12,R4

BRLVL(R4),PS
(R2),.R1

#200,4(R1)
#8I79,(R1)
#121111,6(R1)
#B8IT9:!8BIT78,(R1)
RO
-2
#2,R4
64
BRLVL(R4),PS
74
#5300,2(R2)

;STORE TEMPORALLY
;:BRING OUT A BIT
;BR IF ALL DONE
;R4 IS INDEX REGISTER
:SET PS TO 7

2%
(SP),2(R2)
#7,2(R2)
BRLVL+2(R4),RS5
RS
R5
RS

:SET ROMI
;PUT INSTRUCTION IN PORT6
sFORCE AN INTERRUPT
:STALL
sFOR TIME TO INTERUPT
;GET NEXT LOMEST PS LEVEL
;BR IF R4 = 0
;MOVE NEXT LOWER LEVEL IN PS
sBR TO DELAY
:NO_INTERUPT ASSUME 300 AT LEVEL S AND FIX DMC11 LATER
;CLEAR ROMI
;POP SOFTWARE POINTER
;KEEP GOING
sGET VECTOR ADDRESS
sCLEAR JUNK
;GET BR LEVEL OF DMC11
sSHIFT LEVEL 4 PLACES
:TO THE LEFT FOR THE
:STATUS TABLE

RS,2(R2)
(SP)+,(SP)+
3%,(SP)

;:CLEAR UNWANTED BITS
;PUT BR LEVEL IN STATUS TABLE
;POP IOT JUNK OFF STACK
:SET FOR RETURN

sALL DONE ‘WITH "AUTO SIZING”

(R1)

#10,R2

RS
#170777,R5

BRLVL
:

0
0
200
240
300
340

sLEVEL 0O
sLEVEL 0
sLEVEL 4
sLEVEL S
;LEVEL 6
sLEVEL 7

INTTY:

1518
BPL
MOV
TST8
BPL
MOV
BIC
RTS

nzcsn

sWAIT FOR DONE

STKDBR,R3

.sPUT CHAR IN R3

GT:CSR

R3,8TPDBR

Pognmns.ns

sWAIT UNTIL PRINTER IS READY

;ECHO CHAR
sMASK OFF LOWER CASE
sRETURN

shkbhkdbibsdbbbihibbbsbsbbis

TEST

stssssstbbbsbbtisbsssibinss

;#VERIFY THAT REFERENCING UNIBUS DEVICE REGISTERS
;#DOES NOT CAUSE A TIME OUT TRAP

L LT
Y P Y Y
PV Py YV ryye

SEQ 46

CZOMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-7
OMC11 UNIBUS REGISTER TESTS

TEST 1

012320
012326
012334

012737
012737
012737

000001
012426
012366

012342
012346
012352
012360
012366
012370
012372
012374
012400
012402
012404
012412
012416
012420
012422
012424

013701
012700
012737
012737
005711
000240
104401
062701
005300
001371

001404

012737

005037
104400
011602
104001
000002

001226
001216
001220

012420
000340

TST1:

#1,TSTNO

MOV

@TST2,NEXT

MOV
MOV
MOV
MOV
ST
NOP
SCOP1
ADD
DEC
BNE
MOV
CLR
SCOPE
MOV
EMT
RTI

DMCSR,R1
#4,RO
#2%,4
#340,6
(R1)

MOV

1s:

000002

000006
000006

MOV

000004

2%:

#1%,L0CK

#2.R1
RO
1s
6.4
6
(sP),.R2
1

;R1 CONTAINS BASE DMC11 ADDRESS
;R1 CONTAINS BASE DMC11 ADDRESS
;4 REGISTERS TO BE TESTED
sSET UP TIMEOUT TRAP
;LEVEL 7

;REFERENCE DEVICE REGISTER
;SW09=1?
sNEXT REGISTER
;DEC REGISTER COUNT
;:BR IF NOT LAST REGISTER
;RESTORE LOC 4
;RESTORE LOC 6
;SCOPE THIS TEST
;GET PC OF TRAP
: TIME-OUT ERROR

jkbbdkihhbhhbbbhhhkbhbhhbthh

TEST

;*VERIFY THAT RUN CAN BE CLEARED

012426
012434

012737
012737

012442
012444
012446
012450
012452
012454

005011
005005
011104
001401
104002
104400

000002
012456

001226
001216

TST12:

MOV
MOV

#2,TSTNO
#TST3, NEXT

CLR

(R1)

CLR

1$:

MOV
BEQ
EMT
SCOPE

(R1),R4
1s
2

sdsddhbbdddbhbbbbhbhbbhdhbdds
T

YT YT

Ty T

TP rrrwpyey

;R1 CONTAINS BASE DMC11 ADDRESS
;:CLEAR DMCSR
sCLEAR "EXPECTED"

;PUT DMCSR IN “FOUND"
;BR IF CLEARED
;ERROR DMCSR NOT CLEARED
;SCOPE THIS TEST

jhhdhkbbitssssdibdsbtdititt

TEST

3 stssbdsbsssssdsbdbbbbsbbdss

+#UNIBUS REGISTER WORD DUAL ADDRESSING TEST
;#LOAD ALL REGISTERS WITH INCREMENTING PATTERN
+#READ BACK ALL REGISTERS TO VERIFY CORRECT ADDRESSING

R
P
Ty Y e

TEST 3

' --------------

012456
012464
012472

012737
012737
012737

012500
012502
012506

104412
012700
005011

000003
012606
012506
000001

001226
001216
001220

TS713:

1$:

MOV

93,TSTNO

MOV

#1¢,L0CK

MSTCLR
MOV
CLR

#1,R0
(R1)

MOV

#TST4,NEXT
;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sSTART PATTERN AT 1
;CLEAR REGISTER

SEQ 47

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-8
OMC11 UNIBUS REGISTER TESTS

012510 010005
012512 010011
012514 011104
012516 020504
012520 001401
012522
104002
012524
104401
012526 005721
012530 005200
012532 022700
012536 001363
012540 013701
012544 012700
012550 012737
012556 010005
012560 011104
012562 020504
012564 001401
012566
104002
012570
104401
012572 005721
012574
005200
012576
022700
012602
001365
012604
104400

MOV
MOV
MOV
cHP

RO,RS
RO,(R1)
(R1).R4
R5.R4

EMT
SCoP1
TST
INC
CHP
BNE
MOV
MOV
MOV
MOV

BEQ

2%:

000005
001404
000001
012556

001220

3s:

4%:

(R1)RO
#5,R0
1s
DMCSR,R1
#1,R0
#3$,L0CK
RO,RS5
(R1),.R4
R5,.R4
4%
2

MOV
CHP
BEQ
EMT
SCOP1
TST

(R1)+

INC
cHP
BNE
SCOPE

000005

RO
#5,R0
3

;PUT DATA IN “EXPECTED"
sWRITE DMC REGISTER WITH PATTERN
;READ DMC REGISTER INTO “FOUND”
:IS DATA CORRECT
:BR IF YES
;DATA ERROR
:SW09=1?

sNEXT REGISTER

s INCREMENT DATA PATTERN

;LAST REGISTER?
;:BR IF NO
;:BASE DMC11 ADDRESS TO R1
;RESTART PATTERN AT 1
;NEW SCOP1
;PUT DATA IN "EXPECTED”
;READ DMC REGISTER INTO “FOUND*
;IS DATA CORRECT
;:BR IF YES
;DUAL ADDRESSING ERROR
:SW09=1?
:NEXT REGISTER
s INCREMENT PATTEFN
;LAST REGISTER?
:BR IF NO
+SCOPE THIS TEST

shkbkdtbbbtdbddbbthbbhhbdbhhds

TEST

stdddddbsbtdbbhhbbhbdbbisss

;#CONTROL STATUS REGISTER WRITE/READ TEST
s#SET BITO, VERIFY BITO WAS SET
;*CLEAR BITO, VERIFY BITO WAS CLEARED

;
012606
012614
012622
012630
012632
012636
012642
012644
012646
012650
012652
012654
012656

012737
012737
012737
104412
013701
012705
010511
011104
020504
001401
104002
104401
012737

012670
012672
012674
012676
012700
012702

005005
011104
001402
104002
104401
104400

012664

042711

000004
012704
012632

001226
001216
001220

001404
000001

012664
000001

TST4:

1s:

001220

24:
38:

TT
P P P
e rpw P wrrrer

TEST 4

MOV
MOV
MOV
MSTCLR
MOV
MOV
MOV
MOV
CHP
BEQ
EMT
SCOP1
MOV
BIC

CLR
MOV
BEQ
EMT
SCOoP1
SCOPE

94 ,TSTNO
#TSTS,NEXT
#14,L0CK
DMCSR,R1
#B8IT0,RS
RS.(R1)
(R1),R4
RS.R4
24
2
;
#3$,L0CK

#BITO,(R1)

RS
(R1),R4
44
2

sMASTER CLEAR DMC11
;PUT REGISTER ADDRESS IN R1
;PUT DATA IN "EXPECTED"

;WRITE BIT O
;READ CONTROL STATUS REGISTER
:IS DATA CORRECT
:BR IF YES
;:DATA ERROR
:SWO09 UP?
;NEW SCOP1
;:CLEAR BIT O

;:CLEAR "EXPECTED”
sREAD CONTROL STATUS REGISTER

:BR IF ZERO
sDATA ERROR BITO NOT CLEARED
:SW09 UP?
:SCOPE THIS TEST

SEQ 48

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-9
DMC11 UNIBUS REGISTER TESTS
jdbskbttttsbbsbbtitdtdtbtiss

TEST

ssssdssssdntbbtbsbsbbdhbidtds

;#CONTROL STATUS REGISTER WRITE/READ TEST
;#SET BIT1, VERIFY BIT1 WAS SET
;#CLEAR BIT1, VERIFY BIT1 WAS CLEARED

PP PP

TEST S

‘ --------------

012704
012712
012720
012726
012730
012734
012740
012742
012744
012746
012750
012752
012754
012762
012766
012770
012772
012774
012776
013000

012737
012737
012737
104412
013701
012705
010511
011104
020504
001401
104002
104401
012737
042711
005005
011104
001402
104002
104401
104400

013002
012730

001226
001216
001220

001404
000002

012762
000002

TST5:

14:

MOV
MOV
MOV
MSTCLR
MOV

2%:

3s:

4%:

DMCSR,R1

sMASTER CLEAR DMC11
;PUT REGISTER ADDRESS IN R1

MOV

#BIT1,R5

;PUT DATA IN "EXPECTED”

MOV
CHp
BEQ
EMT
SCOP1
MOV
BIC
CLR
MOV
BEQ
EMT
SCOP1
SCOPE

(R1),R4
R5,R4
2%
2

;READ CONTROL STATUS REGISTER
;IS DATA CORRECT
:BR IF YES
:DATA ERROR
;SW09 UP?
:NEW SCOP1
;CLEAR BIT 1
;CLEAR "EXPECTED”
;READ CONTROL STATUS REGISTER
:BR _IF ZERO
;:DATA ERROR BIT1 NOT CLEARED
:SW09 UP?
:SCOPE THIS TEST

MOV

001220

#5,TSTNO
#TST6,NEXT
#1$,L0CK

R5,(R1)

#3$,L0CK
#8IT1,(R1)
RS
(R1).R4
4%
2

;WRITE BIT 1

jhbbdddhbhdbbbbbthdbhtidsnit

TEST

sktdtsadidbbbsddbtsbbibbsns

;#CONTROL STATUS REGISTER WRITE/READ TEST
+#SET BIT2, VERIFY BIT2 WAS SET
;#CLEAR BIT2, VERIFY BIT2 WAS CLEARED

P
PP PP PP PP PP PPTrey

TEST 6

:+
'

013002
013010
013016
013024
013026
013032

013036
013040
013042
013044
013046
013050
013052
013060
013064
013066
013070
013072
013074

012737
012737
012737
104412
013701
012705
010511
011104

000006
013100
013026

001226 " T876:
001216
001220

001404
000004

14:

020504

001401
104002
104401
012737
042711
005005
011104
001402
104002
104401

013060
000004

001220

2%:

3s:

..............

MOV

MOV
MOV
MSTCLR
MOV
MOV
MOV
MOV
CHP
BEQ
EMT
SCOP1
MOV

8IC
CLR

MOV
BEQ
EMT
SCoP1

#6,TSTNO

ATST7 ,NEXT
@1$,L0CK
DMCSR,R1
#BIT2,R5
RS,(R1)
(R1),R4
R5.R4
23
2

434,L0CK

#8IT72,(R1)
RS
(R1),R4
4%
2

;MASTER CLEAR DMC11
sPUT REGISTER ADDRESS IN R1
;PUT DATA IN "EXPECTED”
sWRITE BIT 2
sREAD CONTROL STATUS REGISTER
+IS DATA CORRECT
sBR IF YES
;DATA ERROR
$SW09 UP?
sNEW SCOP1

;CLEAR BIT 2
sCLEAR “EXPECTED”

sREAD CONTROL STATUS REGISTER
:BR IF ZERO
;DATA ERROR BIT2 NOT CLEARED
;SW09 UP?

SEQ 49

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-10
DMC11 UNIBUS REGISTER TESTS
013076

104400

4%:

SCOPE

;SCOPE THIS TEST

idsddibbkbbhbkibhbbtibdbdits

TEST

sssssssstbssbtsssbdtssstsss

;#CONTROL STATUS REGISTER MWRITE/READ TEST
;#SET BITS, VERIFY BITS WAS SET
;#CLEAR BITS, VERIFY BITS WAS CLEARED

013100
013106
013114
013122
013124
013130
013134
013136
013140
013142
013144
013146
013150
013156
013162
013164
013166
013170
013172
013174

012737
012737
012737
104412
013701
012705
010511
011104
020504
001401
104002
104401
012737
042711
005005
011104
001402
104002
104401
104400

000007
013176
013124

001226
001216
001220

001404
000040

T577:

1s:

MOV
MOV
MOV
MSTCLR
MOV

013156
000040

001220

3s:

4%
:

#7,TSTNO
#TST10,NEXT
#1%,L0CK

T LI

TrTrrrrryIYIYIY

DMCSR,R1

sMASTER CLEAR DMC11
;PUT REGISTER ADDRESS IN R1

MOV
MOV

RS,(R1)
(R1),R4

sWRITE BIT S
sREAD CONTROL STATUS REGISTER

EMT

:DATA ERROR

MOV
CMP
BEQ

2%:

#B8ITS5,R5

R5,R4
24

SCOP1

MOV

#34$,L0CK

BIC
CLR
MOV
BEQ
EMT
SCoP1
SCOPE

#BITS, (R1)
RS
(R1),R4
43
2

;PUT DATA IN “EXPECTED"”

3IS DATA CORRECT
1BR IF YES
:SW09 UP?

sNEW SCOP1

:CLEAR BIT 5
sCLEAR "EXPECTED"
;READ CONTROL STATUS REGISTER
:BR IF ZERO
;DATA ERROR BITS NOT CLEARED
;SHO9 UP?
;SCOPE THIS TEST

shbkbbdbbbdbtbbbdidbttiiisss

TEST

stssbbsdbstsssbbbsdbdbtsdtsd

;#CONTROL STATUS REGISTER WRITE/READ TEST
:#SET BIT6, VERIFY BIT6 WAS SET
;#CLEAR BIT6, VERIFY BIT6 WAS CLEARED

:
013176
013204
013212

013220

013222
013226
013232
013234
013236
013240
013242
013244
013246
013254
013260
013262

012737
012737
012737
104412
013701
012705
010511
011104
020504
001401
104002
104401
012737
042711
005005
011104

000010
013274
013222

001226
001216

001220

001404
000100

013254
000100

TST10:

1$:

001220

28:

3s:

TP
PP PPy TP PP PreR

TEST 10

MOV
MOV
MOV
MSTCLR
MOV

MOV

MOV
MOV
CMP
BEQ
EMT
SCOP1
MOV
BIC
CLR
MOV

€10, TSTNO
@TST11 ,NEXT
#13,L0CK

DMCSR,R1

4B8IT6,RS

RS,(R1)
(R1).R4
R5,R4
2
2

3$,L0CK
#8176,(R1)
RS~
(R1),R4

sMASTER CLEAR DMC11
sPUT REGISTER ADDRESS IN R1

sPUT DATA IN “EXPECTED”

sWRITE BIT 6
sREAD CONTROL STATUS REGISTER
+IS DATA CORRECT
:BR IF YES
sDATA ERROR
:SW09 UP?
sNEW SCOP1

sCLEAR BIT 6
:CLEAR “EXPECTED"
;READ CONTROL STATUS REGISTER

SEQ 50

CZDMC
MACRO vV04.00
27-JUN-85 13:16:37 PAGE 27-11
DMC11 UNIBUS REGISTER TESTS
013264

001402

013270
013272

104401
104400

013266

BEQ
EMT

104002

4%:

43
2

SCoP1
SCOPE

;:BR IF ZERO
;DATA ERROR BIT6 NOT CLEARED

:SWO09 UP?
;SCOPE THIS TEST

idsdttbbdbbbbbibsbbtbhtinsss

TEST

stsssssssssssstitsbtsssssss

;#CONTROL STATUS REGISTER WRITE/READ TEST
;#SET BIT7, VERIFY BIT7 WAS SET
;#CLEAR BIT7, VERIFY BIT7 WAS CLEARED

013274
013302
013310
013316
013320
013324
013330
013332
013334
013336
013340
013342
013344
013352
013356
013360
013362
013364
013366
013370

012737 000011
012737 013372
012737
013320
104412 .
001404
013701
000200
012705
010511
011104
020504
001401
104002
104401
012737 013352
000200
042711
005005
011104
001402
104002
104401
104400

001226
001216
001220

TST11:

18:

2%:
3s:

4s:

VPP

PP PPPPereRs

TEST 11

MOV
MOV
MOV
MSTCLR
MOV
MOV
MOV
MOV

#11,TSTNO
#TST12,NEXT
#14,L0CK

DMCSR,R1
®BIT7,RS
R5,(R1)
(R1).R4

CcMP

001220

R5,R4

BEQ
EMT
SCOP1
MOV
BIC
CLR
MOV
BEQ
EMT
SCOP1

2%
2

€3$,L0CK
#BIT7,(R1)
RS
(R1).R4
43
2

SCOPE

sMASTER CLEAR DMC11
;PUT REGISTER ADDRESS IN R1
;PUT DATA IN “EXPECTED”
;WRITE BIT 7
;READ CONTROL STATUS REGISTER

:IS DATA CORRECT

:BR IF YES
;:DATA ERROR
:SWO09 UP?
;NEW SCOP1
;:CLEAR BIT 7
;CLEAR "EXPECTED”
sREAD CONTROL STATUS REGISTER
:BR IF ZERO
:DATA ERROR BIT7 NOT CLEARED
:SW09 ULP?

:SCOPE THIS TEST

jhtsdbssbbddbtbibbsttstitsds

TEST

sstststssssdsssdsssisssssas

;#CONTROL STATUS REGISTER WRITE/READ TEST
s#SET BIT9, VERIFY BIT9 WAS SET
+#CLEAR BIT9, VERIFY BIT9 WAS CLEARED

$i80A08008000 0000400400000

TEST 12

s
§

013372
013400

013406
013414
013416
013422
013426
013430
013432
013434
013436
013440
013442

012737
012737
012737
104412
013701
012705
010511
011104
020504
001401
104002
104401
012737

000012
013470
013416

001226
001216
001220

001404
001000

013450

TsT12:

1$:

001220

2%:

08 000000000000 000000000000000404

MOV
MOV
MOV
MSTCLR
MoV
MOV
MOV
MOV
CMP
BEQ
EMT
SCoP1
MOV

#12,TSTNO
#TST13,NEXT
18,L0CK
DMCSR,R1
#BIT9,R5
RS,(R1)
(R1),R4

RS.R4
2%
2

#34,L0CK

sMASTER CLEAR DMC11
sPUT REGISTER ADDRESS IN R1
+PUT DATA IN “EXPECTED”
sWRITE BIT 9
;READ CONTROL STATUS REGISTER
+1S DATA CORRECT
sBR _IF YES
;DATA ERROR
1SW09 UP?
sNEW SCOP1

aEE—-

SEQ S1

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-12
DMC11 UNIBUS REGISTER TESTS
013450
013454
013456
013460
013462
013464
013466

042711
005005
011104
001402
104002
104401
104400

BIC
CLR
MOV
BEQ

001000

#8IT79,(R1)
RS
(R1).R4
43

EMT

4s:

SCoP1

;CLEAR BIT 9
;CLEAR "EXPECTED"
;READ CONTROL STATUS REGISTER
:BR IF ZERO
‘
;DATA ERROR BIT9 NOT CLEARED

:SWO9 UP?

SCOPE

sSCOPE THIS TEST

;884848880

sststtbtdtts

TEST

stssssssdsssstsdttsdstdisss

;#CONTROL STATUS REGISTER WRITE/READ TEST
s#SET BIT11, VERIFY BIT11 WAS SET
;sCLEAR BIT11, VERIFY BIT11 WAS CLEARED

012737
012737
012737
104412
013701
012705
010511
011104

000013
013566
013514
001404
004000

013546

013546
013552
013554
013556
013560
013562
013564

001226
001216
001220

001220

TST13:

MOV
MOV
MOV

#13,TSTNO
OTST14 ,NEXT
#14,L0CK

1%:

MOV
MOV
MOV
MOV
cHP
BEQ
EMT
SCOP1
MOV

DMCSR,R1
#BIT11,RS
R5,(R1)
(R1),R4
R5,R4
2%
2

sPUT REGISTER ADDRESS IN R1
;PUT DATA IN "EXPECTED"”
sWRITE BIT 11
;READ CONTROL STATUS REGISTER
+IS DATA CORRECT

#34,L0CK

sNEW SCOP1

CLR
MOV
BEQ

RS
(R1).Re
4%

sCLEAR "EXPECTED”
sREAD CONTROL STATUS REGISTER
;B8R _IF ZERO

2%:

3%:

MSTCLR

BIC

EMT
4%

TrYyryreers

TEST 13

s
013470
013476
013504
013512
013514
013520
013524
013526
013530
013532
013534
013536
013540

SCoP1
SCOPE

#IT11,(R1)

sMASTER CLEAR DMC11

:BR IF YES

:DATA ERROR

:SWO9 UP?

:CLEAR BIT 11

sDATA ERROR BIT11 NOT CLEARED

1SWO9 LP?
sSCOPE THIS TEST

(8848804000008 00000008000008

TEST

14 sssssss80080s08800008080040

+#CONTROL STATUS REGISTER WRITE/READ TEST
s#SET BIT12, VERIFY BIT12 MWAS SET
s#CLEAR BIT12, VERIFY BIT12 WAS CLEARED

§18888888888888480550084888485408488004840848888000000000080880888

;
013566
013574
013602
013610
013612
013616
013622
013624
013626
013630

012737
012737
012737
104412
013701
012705
010511
011104
020504
001401

000014
013664
013612
001404
010000

001226
001216
001220

TST14:

18:

TEST 14

MOV
MOV
MoV
MSTCLR
MOV
MOV

DMCSR,R1
#81IT12,.R5

sPUT REGISTER ADDRESS IN R1
sPUT DATA IN "EXPECTED”

MOV
CMP
BEQ

(R1).R4
RS,.R4
28

sREAD CONTROL STATUS REGISTER
sIS DATA CORRECT
:BR IF YES

MOV

#14,TSTNO
OTST1S,NEXT
#14,L0CK

RS,(R1)

sMASTER CLEAR DMC11

sWRITE BIT 12

SEQ 52

CZDOMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-13
DMC11 UNIBUS REGISTER TESTS

013632
013634
013636
013644
013650
013652
013654
013656
013660
013662

104002
104401
012737
042711
005005
011104
001402
104002
104401
104400

013644
010000

001220

2%:
3s:

4%:

EMT
SCoP1
MOV
BIC
CLR
MOV
BEQ
EMT
SCoP1

#3%,L0CK

#81I712.(R1)

RS
(R1).R4
43
2

SCOPE

;DATA ERROR
:SHO09 UP?
sNEW SCOP1
;CLEAR BIT 12
sCLEAR "EXPECTED"”
sREAD CONTROL STATUS REGISTER
:BR_IF ZERO
sDATA ERROR BIT12 NOT CLEARED
:SW09 LP?

sSCOPE THIS TEST

jh4b84ssss0b0ss0hbstsbtbbtds

TEST

ssssssssssssstsssssssssssss

sCONTROL OUT REGISTER WRITE/READ TEST
+#SET BITO, VERIFY BITO WAS SET
s#CLEAR BITO, VERIFY BITO WAS CLEARED

$:8 8 8

013664
013672
013700
013706
013710
013714
013720
013722
013724
013726
013730
013732
013734
013742

012737
012737
012737

104412
013701
012705
010511

000015

013762

013710

001226
001216
001220

001410
000001

TST15:

1s:

011104

0888500805888 40 0008400888
s0004kt
0004000t 00 bt
tt
kit

MOV
Muy
MOV
MSTCLR
MOV
MOV
MOV
MOV
CMP

BEQ

013742
000001

013746
013750

EMT
SCOP1
MOV
BIC

001220

013752
013754
013756
013760

4%:

CLR
MOV
BEQ
EMT
SCOP1
SCOPE

#15, TSTNO
#TST16,NEXT
#14,L0CK
DMCTL,R1
#8IT0,.RS
R5,(R1)
(R1).R4
RS.R4

#34,L0CK
#8170,(R1)

RS
(R1).R4
44
2

sMASTER CLEAR DMC11
sPUT REGISTER ADDRECSS IN R1
sPUT DATA IN “EXPECTED”
sWRITE BIT O
sREAD CONTROL OUT REGISTER
+IS DATA CORRECT

1BR_IF YES

:DATA ERROR
1SWO9 UP?
+NEW SCOP1
1CLEAR BIT O

sCLEAR "EXPECTED"
sREAD CONTROL OUT REGISTER
18R _IF ZERO
sDATA ERROR BITO NOT CLEARED
1SHO9 LP?
sSCOPE THIS TEST

1888888804080000000048008808 TEST

16 s8sssssss00080000008800080s8

ssCONTROL OUT REGISTER WRITE/READ TEST
s¢SET BITL, VERIFY BIT1 WAS SET
s#CLEAR BIT1, VERIFY BIT1 WAS CLEARED

1:08888680888884608880888848404888480884000084040888840808480000808888

TEST 16

.--. ------ L

013762
013770
013776
014006
014012
014016

012737
012737
012737
104412
013701
012705

010511

000016

014060
014006

001410

001226
001216
001220

TST16:

18:

HOV
MOV
MOV
MSTCLR

MOV
MOV
MOV

€16, TSTNO
STST17 ,NEXT
#14,L0CK
DMCTL,R1
#BIT1.R5
RS.(R1)

sMASTER CLEAR DMC11

sPUT REGISTER ADDRESS IN R1
sPUT DATA IN “EXPECTED”
sWRITE BIT 1

CZOMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-14

SEQ 53

OMC11 UNIBUS REGISTER TESTS
014020

014022

014024
014026
014030
014032
014040
014044
014046
014050
014052
014054
014056

011104

MOV

001401
104002
104401
012737
042711
005005
011104
001402
104002
104401
104400

BEQ
EMT
SCoP1
MOV
8I1C
CLR
MOV
BEQ
EMT
SCoP1
SCOPE

020504

cHp

014040
000002

001220

2%:
3s:

43:

(R1),.R4

sREAD CONTROL OUT REGISTER

2%
2

:BR IF YES
sDATA ERROR
:SW09 UP?
sNEW SCOP1
sCLEAR BIT 1
;CLEAR "EXPECTED”
sREAD CONTROL OUT REGISTER
:BR IF ZERO
;DATA ERROR BIT1 NOT CLEARED
:SHO09 LUP?
:SCOPE THIS TEST

R5.R4

#3%,L0CK
#8IT1,(R1)

RS
(R1),R4
43
2

sIS DATA CORRECT

;8688484880000 000000000d040%

TEST

sssstttsbssttdsbsbbtbthidss

0 000800400k

0 00ttt bbdb bbbt bbdbhbbbhtd

s#CONTROL OUT REGISTER WRITE/READ TEST
;#SET BIT2, VERIFY BIT2 WAS SET
;#CLEAR BIT2, VERIFY BIT2 WAS CLEARED
$:88848858 2542888400885

TESTY 17

s
014060

014066
014074
014102
014104
014110

014114
014116
014120
014122
014124
014126
014130
014136
014142
014144
014146
014150
014152
014154

012737

012737
012737
104412
013701
012705

010511
011104
020504
001401
104002
104401
012737
042711
005005
011104
001402
104002
104401
104400

000017

014156
014104

001226

001216
001220

001410
000004

014136
000004

TST17:

1s:

001220

2s:
3s:

4s:

MOV

MOV
MOV
MSTCLR
MOV
MOV

MOV
MOV
cMP
BEQ
EMT
SCOP1

MoV
BIC
CLR
MOV
BEQ
EMT
SCoP1
SCOPE

#17,TSTNO

#TST20,NEXT
@18,L0CK

DMCTL ,R1
#BIT2,R5
RS.(R1)
(R1).R4
RS,R4
2%
2
#34,L0CK
#8172,(R1)
RS
(R1).R4
4%
2

sMASTER CLEAR DMC11
;PUT REGISTER ADDRESS IN R1
;PUT DATA IN “EXPECTED”
sWRITE BIT 2
;READ CONTROL OUT REGISTER
;IS DATA CORRECT
sBR IF YES
sDATA ERROR
:SWO09 UP?
;NEW SCOP1
;:CLEAR BIT 2
;CLEAR "EXPECTED"
;READ CONTROL OUT REGISTER
:BR IF ZERO
;DATA ERROR BIT2 NOT CLEARED
:SWO9 UP?
sSCOPE THIS TEST

jhekbbttsbstidbbnttbssbatasd

TEST

sttststsdittsbisdtdddssbdind

;#CONTROL OUT REGISTER WRITE/READ TEST
;#SET BIT6, VERIFY BIT6 WAS SET
;#CLEAR BIT6, VERIFY BIT6 WAS CLEARED

$:8088884 5480804400480 5 000000000400 000000000000t kddbbbbbdbidbtin

;

TEST 20

‘ ..............

014156
014164
014172
014200

012737
012737
012737
104412

000020
014254
014202

001226
001216
001220

TST20:

MOV
MOV
MOV
MSTCLR

#20, TSTNO
#TST21 ,NEXT
@1$,L0CK

sMASTER CLEAR DMC11

SEQ 54

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-15
DMC11 UNIBUS REGISTER TESTS

014202
014206
014212
014214
014216
014220
014222
014224
014226
014234
014240
014242
014244
014246

014250
014252

013701
012705
010511
011104
020504
001401
104002
104401
012737
042711
005005
011104
001402
104002

001410
000100

014234
000100

1s:

001220

104401
104400

2%:
3s:

4s:

MOV
MOV
MOV
MOV
CMP
BEQ
EMT
SCoP1
MOV
BIC
CLR
MOV
BEQ
EMT

SCOP1
SCOPE

DMCTL,P1
#B8176.R5
R5,(R1)
(R1).R4
R5.R4
23
2
#3$,L0CK
#8176,(R1)
RS
(R1),R4
43
2

;PUT REGISTER ADDRESS IN R1
;PUT DATA IN “EXPECTED"
;WRITE BIT 6
;READ CONTROL OUT REGISTER
;IS DATA CORRECT
:BR IF YES
;:DATA ERROR
:SHO09 UP?
;NEW SCOP1
:CLEAR BIT 6
;:CLEAR "EXPECTED"
;READ CONTROL OUT REGISTER
;:BR IF ZERO
;DATA ERROR BIT6 NOT CLEARED

:SW09 LP?
:SCOPE THIS TEST

4888484004000 00000000000008 TEST 21 sstsssssssstsssssbbsbisssss
s#CONTROL OUT REGISTER WRITE/READ TEST
;¢SET BIT7, VERIFY BIT7 WAS SET
;#CLEAR BIT7, VERIFY BIT7 WAS CLEARED

TEST 21

014254

014262
014270
014276
014300
014304

014310

014312
014314
014316
014320
014322
014324
014332
014336
014340
014342
014344
014346
014350

012737

012737
012737
104412
013701
012705

010511

011104
020504
001401
104002
104401
012737
042711
005005
011104
001402
104002
104401
104400

000021

014352
014300

001226

1216
001220

001410
000200

014332
000200

TST21:

1s:

2%:
3s:

4s:

P Y

MOV

MOV
MOV
MSTCLR
MOV
MOV

MOV
cHP
BEQ
EMT
SCOP1
MOV
8IC
CLR
MOV
BEQ
EMT
SCOP1
SCOPE

9TST22 ,NEXT
@18,L0CK

OMCTL,R1
#BIT7,.RS

sMASTER CLEAR DMC11
;PUT REGISTER ADDRESS IN R1
;PUT DATA IN “EXPECTED"”

R5,(R1)

sWRITE BIT 7

(R1).R4
RS.R4
24
2
@3s,L0Cx
#BIT7,(R1)
RS
(R1).R4
43
2

sREAD CONTROL OUT REGISTER
;IS DATA CORRECT
:BR IF YES
;DATA ERROR
:SWO9 UP?
sNEW SCOP1
;:CLEAR BIT 7
sCLEAR "EXPECTED”
sREAD CONTROL OUT REGISTER
:BR IF ZERO
;DATA ERROR BIT7 NOT CLEARED
:SWO09 UP?
3SCOPE THIS TEST
TEST 22

ssdsssisdstidddbdbbbddtini

;#CONTROL OUT REGISTER WRITE/READ TEST
;#SET BIT12, VERIFY BIT12 MAS SET
;#CLEAR BIT12, VERIFY BIT12 WAS CLEARED

350848848808 0804483884804455400048 0000000000000

TEST 22

s
014352

012737

000022

001226

T5T22:

TV P PPPUPUPpe

#21,TSTNO

408 8Assbbtsttbbtttstttstts

‘

T Y

--------------

MOV

001220

--------------

MOV

#22,TSTNO

00400000040040

SEQ 55

MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-16
CzZomMC
OMC11 UNIBUS REGISTER TESTS

014360
014366
014374
014376
014402
014406
014410
014412
014414
014416
014420
014422
014430
014434
014436

012737
012737
104412
013701
012705
010511
011104
020504
001401
104002
104401
012737
042711
005005
011104

014440

001402

014444
014446

104401
104400

014442

014450
014376

001216
001220

001410
010000

014430
010000

1%:

001220

2%:
3s:

MOV
MOV
MSTCLR
MOV
MOV
MOV
MOV
cHpP
BEQ
EMT
SCOP1
MOV
BIC
CLR
MOV

BEQ

104002

EMT

4s:

9TST23 ,NEXT
€1%,L0CK
DMCTL,.R1
#81IT12,RS5
RS5,(R1)
(R1).R4
R5,.R4
2%
2
#3$,L0CK
#B8IT12,(R1)
RS
(R1).R4

4%
2

SCoP1
SCOPE

sMASTER CLEAR DMC11
sPUT REGISTER ADDRESS IN R1

;PUT DATA IN "EXPECTED”
sWRITE BIT 12

;READ CONTROL OUT REGISTER

:IS DATA CORRECT
;BR IF YES
;DATA ERROR
;SWO09 UP?
sNEW SCOP1
;CLEAR BIT 12
;CLEAR "EXPECTED"

;READ CONTROL OUT REGISTER

;BR IF ZERO

;:DATA ERROR BIT12 NOT CLEARED

:SW09 UP?
;SCOPE THIS TEST

kbbbt tbtddbtdtdibbntits

TEST

sstsbtbbbdbdbsbibsbbdsbddss

;#CONTROL OUT REGISTER WRITE/READ TEST
;#SET BIT13, VERIFY BIT13 WAS SET
;#CLEAR BIT13, VERIFY BIT13 WAS CLEARED

:
014450

014456
014464

000023

012737
012737

014546
014474

014474
014500

013701
012705

001410
020000

014506
014510

011104
020504

014472

014504

014512
014514
014516
014520
014526
014532

014534
014536

014540

012737

014542
014544

104412

010511

001401
104002
104401

012737
042711
005005
011104
001402
104002
104401
104400

014526
020000

001226

001216
001220

TST23:

1$:

2%:
3s:

4%:

T rTTITTIIY

TEST 23

MOV

#23,TSTNO

MOV
MOV

#TST24 ,NEXT
#1%,L0CK

MOV
MOV

DMCTL,R1
#8IT13,R5

MOV
cHp

(R1),R4
R5,.R4

MSTCLR

MOV

001220

BEQ
EMT
SCOP1

MOV
BIC
CLR
MOV
BEQ
EMT
SCOoP1
SCOPE

sMASTER CLEAR DMC11

;PUT REGISTER ADDRESS IN R1
;PUT DATA IN “EXPECTED"

RS,(R1)

sWRITE BIT 13

2%
2

;BR IF YES
;DATA ERROR
3SWO09 LUP?

#3$,L0CK
#BIT13,.(R1)
RS
(R1).R4
4%
2

sREAD CONTROL OUT REGISTER
3IS DATA CORRECT

sNEW SCOP1
sCLEAR BIT 13
;CLEAR "EXPECTED"
;:READ CONTROL OUT REGISTER
;BR IF ZERO
;:DATA ERROR BIT13 NOT CLEARED
;SW09 UP?
+SCOPE THIS TEST

shddsbbbdbbbbbbdbibbdbnbidss

TEST

;#PORT4 REGISTER WRITE/READ TEST
;#FLOAT A ONE THROUGH PORT4 REGISTER
:#FLOAT A ZERO THROUGH PORT4 REGISTER

sstsdissbtbdsbdbibbbdidddiss

srhddbdbbdbkbhbbbhkibbibbbhbbbbbbbbbibddbbhbdbhbhbibdbibdbibdbbia

SEQ 56

CZoMC
MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-17
DMC11 UNIBUS REGISTER TESTS

TEST 24

;s
-

014546
014554
014562
014570
014572
014576
014602

014602
014604
014606
014610
014612
014614
014616
014620
014622
014624
014626
014634
014640
014640
014642
014644
014646
014650
014652
014654
014656
014660
014662
014664
014666
014670

012737
012737
012737
104412
013701
012700

010005
010511
011104
020504
001401
104002
104401
000241
006100
001366
012737
012700

000024
014672
014602

001226
001216
001220

001412
000001

T1S724:

645
:

65%:

014640
000001

001220
665:

005100
010005
010511
011104
020504
001401
104002
104401
005100
000241
006100
001364
104400

MOV
MOV
MOV
MSTCLR
MOV
MOV

RO
64
#66% ,L0CK
#1,RO

CoM
MOV
MOV
MOV

RO
RO,RS
R5,(R1)
(R1).R4

EMT
SCOP1
CoM

ROL

CLC

BNE
SCOPE

;MASTER CLEAR DMC11
;PUT REGISTER ADDRESS IN R1
;START WITH BITO

DMPO4,R1
#1.R0

MOV
MOV
MOV
CHP
BEQ
EMT
SCoP1
CLC
ROL
BNE
MOV
MOV

cMP
BEQ

67%:

#24,TSTNO
#TST25 ,NEXT
#64$,L0CK

RO,RS
R5,(R1)
(R1),R4
R5.R4
65¢
2

;PUT "EXPECTED” IN RS
;WRITE PORT4 REGISTER
;READ PORT4 REGISTER
;COMPARE EXPECTED AND FOUND
;:BR IF OK
:WRITE/READ ERROR
;LOOP TO 64$% IF SW09=1
;CLEAR CARRY
;SHIFT TO NEXT BIT

;:BR IF NOT DONE YET?
;:NEW SCOP1
:START WITH BITO

;CHANGE TO A FLOATING ZERO
;PUT "EXPECTED” IN RS
;WRITE PORT4 REGISTER
;READ PORT4 REGISTER
;COMPARE EXPECTED AND FOUND
;:BR IF OK
sWRITE/READ ERROR
;LOOP TO 66% IF SW09=1
;CHANGE BACK TO A FLOATING ONE
;CLEAR CARRY
;SHIFT TO NEXT BIT
:BR IF NOT DONE YET?
:SCOPE THIS TEST

R5,R4
67$

664

shbkbhbsdhbbbhbbdbassibntsss

TEST

s#PORT6 REGISTER WRITE/READ TEST

sissssbnssibbdiisddidbbibds

;#FLOAT A ONE THROUGH PORT6 REGISTER

;#FLOAT A ZERO THROUGH PORT6 REGISTER

PR Lt
2
T

3
014672
014700
014706
014714
014716
014722
014726
014726
014730
014732
014734
014736

012737
012737
012737
104412
013701
012700
010005
010511
011104
020504
001401

000025
015016
014726

001414
000001

001226
001216
001220

TST25:

644:

MOV

MOV
CMP
BEQ

TP YT TS TT I I I T

VEST 25

MOV
MOV
MOV
MSTCLR
MOV
MOV

MOV

425, TSTNO
#TST26 ,NEXT
9643 ,L0CK

DMPO6,R1
#1,R0

RO,RS

R5,(R1)

(R1).R4
RS,R4
65¢

sMASTER CLEAR DMC11
;PUT REGISTER ADDRESS IN R1
:START WITH BITO

;PUT “EXPECTED” IN RS
sWRITE PORT6 REGISTER
;READ PORT6 REGISTER
;COMPARE EXPECTED AND FOUND
;BR IF OK

SEQ 57

MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-18
CZoMC
DMC11 UNIBUS REGISTER TESTS

014740
014742
014744
014746
014750
014752
014760
014764
014764
014766
014770
014772
014774
014776
015000

015002
015004
015006
015010
015012
015014

104002
104401
000241
006100
001366
012737
012700

65%:

014764
000001

001220

005100
010005
010511
011104
020504
001401
104002
104401
005100
000241
006100
001364
104400

67%:

EMT

SCoP1
CLC
ROL
BNE
MOV
MOV
CoM
MOV
MOV
MOV
cMP
BEQ
EMT
SCoP1
CcoM
CLC
ROL
BNE

SCOPE

RO
644
#66%,L0CK
#1.RO

RO
RO,RS
R5,(R1)

(R1),.R4

R5,R4
67%
2
RO
RO
664

;WRITE/READ ERROR
;LOOP TO 64% IF SW09=1
:CLEAR CARRY
;SHIFT TO NEXT BIT
;BR IF NOT DONE YET?
;NEW SCOP1
:START WITH BITO
;CHANGE TO A FLOATING ZERO
;PUT "EXPECTED” IN RS
;WRITE PORT6 REGISTER
;READ PORT6 REGISTER
;COMPARE EXPECTED AND FOUND
;BR IF OK
sWRITE/READ ERROR
;LOOP TO 66% IF SW09=1
sCHANGE BACK TO A FLOATING ONE

;CLEAR
sSHIFT
:BR IF
:SCOPE

shbdthbbbbtbbbbbbibb
bbbttt
bi

CARRY
TO NEXT BIT
NOT DONE YET?
THIS TEST

TEST

sdsdsssbsbbbbhbdhbitbdbhsss

;#UNIBUS REGISTER BYTE DUAL ADDRESSING TEST
;#LOAD ALL REGISTERS WITH INCREMENTING PATTERN
+#READ BACK ALL REGISTERS TO VERIFY CORRECT ADDRESSING

P
PP PPrerPr.

TEST 26

' --------------

015016
015024
015032

012737
012737
012737

015040
015042
015046
015050
015052
015054
015056
015060
015062
015064
015066
015070
015072
015076
015100
015104
015110
015116
015120
015122
015124
015126

104412
012700
105011
110005
110011
111104
020504
001401
104002
104401
105721
005200
022700
001363
013701
012700
012737
110005
111104
020504
001401
104002

000026
015146
015046

001226
001216
001220

000001

TST26:

1$:

MOV
MOV
MOV

426, TSTNO
#TST27 ,NEXT
#14,L0CK

MSTCLR
MoV
CLRB
MOVB
MOVB

1,R0
(R1)
RO,RS
RO,(R1)

BEQ
EMT

2%
2

MOoVB
CHMP

2%:

000011
001404
000001
015116

001220

3s:

(R1).R4
KS,R4

SCoP1
1518
INC
CMP
BNE
MOV
MOV
MOV
MOVB
MOVB

(R1)+
RO
#11,R0
1
DMCSR,R1
#1,R0
#3$,L0CK
RO,RS
(R1),R4

BEQ
EMT

4%
2

cHpP

R5,R4

:R1 CONTAINS BASE DMC11 ADDRESS
;:MASTER CLEAR DMC11
;START PATTERN AT 1
;CLEAR REGISTER
;PUT DATA IN "EXPECTED"
sWRITE DMC REGISTER WITH PATTERN
;READ DMC REGISTER INTO "FOUND"
;IS DATA CORRECT
sBR IF YES
;DATA ERROR
:SH09=17?
sNEXT REGISTER
;INCREMENT DATA PATTERN
;LAST REGISTER?
;BR IF NO
:BASE DMC11 ADDRESS TO R1
sRESTART PATTERN AT 1
;NEW SCOP1
;PUT DATA IN "EXPECTED"
;READ DMC REGISTER INTO “FOUND*
sIS DATA CORRECT
sBR IF YES
;DUAL ADDRESSING ERROR

SEQ 58

CZDMC
MACRO v04.00 27-JUN-85 13:16:37 PAGE 27-19
DMC11 UNIBUS REGISTER TESTS
015130
015132
015134
015136
015142
- 015144

104401
105721
005200
022700
001365
104400

4%:

000011

SCOP1
1518
INC
cHP
BNE
SCOPE

;SW09=17?
sNEXT REGISTER
s INCREMENT PATTERN
;LAST REGISTER?
;BR IF NO
;SCOPE THIS TEST

(R1)+
RO
#11,R0
3s

shskdhbbsbbbbbdibtihbdhbbiis

TEST

#sssdsbbbdhbbbhhhbbbbhbbsss

s#*MAINTENANCE INSTRUCTION REGISTER TEST
;#VERIFY THAT THE MAINT IR CAN BE WRITTEN TO ALL ZEROS'
s#AND ALL ONES‘. VERIFY THAT IT IS CLEARED ON A BUS RESET.

LTI

015146
015154
015162

012737
012737
012737

015170
015172
015176
015200
015204
015210
015212
015214
15216
015220
015226
015232
015236
015242
015244

104412
012711
005005
010561
016104
020504
001401
104023
104401
012737
012705
010561
016104
020504
001401
104023
104401
012737
005005
000005
012711
016104

015246
015250
015252

015260

015262
015264
015270
015274

015276

015300
015302
015304

020504

001401
104023
104401
104400

000027

015306
015200

001226
001216
001220

18127:

000006

015232

177777

015262
003000
000006

MOV
MOV
MOV
MSTCLR
MOV

003000
1%:

001220

2%:

3s:

001220

4%:

S$:

64:

T T

ITrITrIrYTYYYTYTM

TEST 27

s
§

CLR
MOV
MOV
CHMP
BEQ
EMT
SCOP1
MOV
MOV
MOV
MOV
cHP
BEQ
EMT
SCOP1
MOV
CLR
RESET
MOV
MOV

CMP
BEQ
EMT
SCOP1
SCOPE

#27,TSTNO
#TST30,NEXT
#14,L0CK

;R1 CONTAINS BASE DMC11 ADDRESS
:MASTER CLEAR DMC11
#BIT9!BIT10,(R1) ;SEL6 IS NOW THE IR

RS
RS,6(R1)
6(R1),R4
R5,R4
2%
23

:PUT "EXPECTED” IN RS
;:CLEAR THE IR
;:READ THE IR
;IS IT CLEARED?
:BR IF YES

:ERROR IR IS NOT CLEAR

;1.OOP TO 1¢ IF SW09=1
sNEW SCOP1
;PUT “EXPECTED” IN RS
;WRITE ALL ONES TO THE IR
sREAD THE IR
:I5 IT ALL ONES?
:BR IF YES
;ERROR IR IS NOT = ALL ONES
;LOOP TO 3§ IF SW09=1
#54,L0CK
:NEW SCOP1
e
sPUT "EXPECTED” IN RS
1BUS RESET
#B8IT9:BIT10,(R1) ;SEL6 IS IR
6(R1),R4
;READ THE IR

#3$,L0CK
#-1,R5
RS,6(R1)
6(R1),.R4
RS,.R4
43
23

RS,R4
6%
23

:IS IT CLEARED?
;BR IF YES
;ERROR, IR IS NOT CLEARED
;LOOP TO S$¢ IF SW09=1
:SCOPE THIS TEST

jtsdsbbkdbktdstdbbsbhdbdstiiss

TEST

30 ssddisdssbssddbidbditdisbis

s*MAINTENANCE INSTRUCTION REGISTER TEST
;#VERIFY THAT THE MAINT IR CAN BE WRITTEN TO ALL ZEROS'
i#AND ALL ONES‘'. VERIFY THAT IT IS CLEARED ON A MASTER RESET.

Py Py

Py Y

SEQ 59

CZDMC
MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-20
DMC11 UNIBUS REGISTER TESTS

015306
015314
015322

012737
012737
012737

015330
015332
015336
015340
015344
015350
015352
015354
015356
015360
015366
015372
015376
015402
015404
015406
015410
015412
015420
015422
015426
015432
015436
015440
015442
015444
015446

104412

012711
005005
010561
016104
020504
001401
104023
104401
012737
012705
010561
016104
020504
001401
104023
104401
012737
005005
052711
012711
016104
020504
001401
104023
104401
104400

000030
015450
015340

001226
001216
001220

TS730:

003000
000006
000006

15:

2%:

015372
177777
000006
000006

001220

015422

001220

3s:

040000
003000
000006

4s:

5s:

6%:

MOV
MOV
MOV

#30,TSTNO
#TST31,NEXT
#1%,L0CK

MSTCLR
MOV
CLR
MOV

;MASTER CLEAR DMC11
OBIT9'BIT10 (R1) ;SEL6 IS NOW THE IR
;PUT "EXPECTED" IN RS
RS 6(R1)
:CLEAR THE IR

MOV

CHMP
BEQ
EMT
SCOP1
MOV
MOV
MOV
MOV
cMP
BEQ
EMT
SCOP1
MOV
CLR
BIS
MOV
MOV
cHpP
BEQ
EMT
SCoP1
SCOPE

6(R1),R4
R5,R4
2%
23

;R1 CONTAINS BASE DMC11 ADDRESS

;:READ THE IR

sIS IT CLEARED?
;:BR IF YES
;ERROR IR IS NOT CLEAR
;LOOP TO 1¢ IF SWO09=1
#3%,L0CK
sNEW SCOP1
#-1,R5
;PUT "EXPECTED” IN RS
R5,6(R1)
;WRITE ALL ONES TO THE IR
6(R1),.R4
;READ THE IR
R5,.R4
;IS IT ALL ONES?
a3
:BR IF YES
23
;ERROR IR IS NOT = ALL ONES
;LOOP TO 3¢ IF SW09=1
#54,L0CK
sNEW SCOP1
RS
;PUT “EXPECTED” IN RS
#8IT714,(R1)
sMASTER CLEAR
#8IT9!BIT10,(R1) ;SEL6 IS IR
6(R1),R4
;:READ THE IR
RS,.R4
;IS IT CLEARED?
63
:BR IF YES
23
;ERROR, IR IS NOT CLEARED
;LOOP TO 5¢ IF SW09=1
:SCOPE THIS TEST

shtbksdbbbbtdibtsitbbbbbittss

TEST

ssdbikbbdbhdsbbbbdbsbtihdds

s#sMICRO PROCESSOR TEST
+#LOAD DMPO6 WITH A MICRO-PROCESSOR INSTRUCTION, CLOCK IT
s#VERIFY INSTRUCTION EXECUTED PROPERLY
:#INSTRUCTION SHOULD MOVE IBUS*4 TO IBUS+5, IBUS#4 IS ALL 1'S
s#AND IBUSs5 IS ALL 0'S. RESULT SHOULD BE ALL 1'S IN SEL4

PRI

s
015450

012737
012737

015464
015466
015474
015500
015506
015512
015514
015520
015524
015526
015530

104412
012761
012711
012761
052711
000240
012705
016104
020504
001401

015456

104003

000031
015534
000377
001000

121105

001400

1777177
000004

001226

001216

TS731:

P TR

MOV
MOV

275732 ,NEXT

#377,4(R1)
#B8179,(R1)
#121105,6(R1)

MOV
MOV
CMP
BEQ

#-1,R5
4(R1),.R4
R5.R4
13

EMT

TP ST

I TTT

#31,TSTNO

MOV
MOV
MOV
BIS

TEST 31

MSTCLR

000006

9BIT8!BIT9,(R1)

sR1 CONTAINS BASE DMC11 ADDRESS

sMASTER CLEAR DMC11

sPORT4 HI-BYTE=0'S LO-BYTE=1'S
:SET ROMI
;INSTRUCTION TO PORT6

;CLK INTSRUCTION, MOVE IBUS#4 TO IBUS+S
;

sPUT "EXPECTED” IN RS
sPUT “FOUND” INTO R4
;IS DATA CORRECT
sBR IF YES
;ERROR

SEQ 60

CZOMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-21
DOMC11 MICRO PROCESSOR IBUSs TESTS
015532

104400

1%:

SCOPE

:SCOPE THIS TEST

shbhsbstbbbbsbbitbbbdttibiis

TEST

stdbbdbtbbbbhbdsbbsbssbsbis

s#MICRO PROCESSOR IBUS# REGISTER WRITE/READ TEST
s#FLOAT A 1 THROUGH IBUS# REGISTER 0

;#FLOAT A 0 THROUGH IBUS# REGISTER 0O
R

015534
015542
015550

012737
012737
012737

015556
015560
015564
015570
015570
015574
015602
015604
015606
015610
015612
015614
015620
015624
015626
015630
015632
015634
015636
015640
015642
015650
015654
015656
015656
015662
015670
015672
015674
015676
015700
015702
015706
015712
015714
015716
015720
015722
015724
015726
015730
015732

104412
012702
012700
010061
042761
104414
121100
104414
121005
010005
042705
116104
120504
001401
104004
104401
000241
106100
001353
012737
012700
005100

010061
042761
104414
121100
104414

121005
010005
042705
116104
120504
001401
104004
104401
005100
000241
106100
001351
104400

000032
015734
015570

001226
001216
001220

000000
000001

TST32:

645%:

000004
000030

000030
000005

65%:

015656
000001
000004
000030

001220
694
:
67%:
000004

000930
000005

MoV
MOV
MOV

#32, TSTNO
#TST33,NEXT
0643 ,L0CK

MSTCLR
MOV
MOV

#0,R2
#1.RO

MOV
RO,4(R1)
BIC
#30,4(R1)
ROMCLK
121100:0
ROMCLK
121005!<0+20>
MOV
RO,RS
BIC
#30,R5
MOVB
S(R1),.R4
CMPB
RS,R4
654
BEQ
EMT
&
SCOP1
cLC
ROLB
RO
BNE
64%
MOV
9674 ,L0OCK
MOV
@1,RO

comM

MOV
RO,4(R1)
BIC
#30,4(R1)
ROMCLK
121100:0
ROMCLK
121005:<0+20>
MOV
RO.R5
BIC
#30,R5
MOVB
S(R1),R4

CHPB

68¢4:

BEQ
EMT
SCoP1
COM
CLC
ROLB
BNE
SCOPE

RS,R4
68$
&

RO
RO
69$

PP PP PP PP,

:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;SAVE _REGISTER ADDRESS FOR TYPEOUT
;START WITH BIT 0

;PUT PATTERN INTO PORT4
;CLEAR UNWANTED BITS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS# REGISTER O
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS* REGISTER 0O
;:PUT EXPECTED IN RS
;CLEAR UNMWANTED BITS
;PUT "FOUND” INTO R4
;DATA CORRECT?
:BR IF YES
;ERROR

:SW09=17?

;sCLEAR CARRY
;SHIFT BIT IN RO

;IF RO=0 THEN DONE
;:NEW SCOP1
;START WITH BIT O
;CHANGE TO FLOATING ZERO

;PUT PATTERN INTO PORT4
;CLEAR UNWANTED BITS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
MOV DATA TO IBUS* REGISTER 0
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS* REGISTER O
;PUT EXPECTED IN RS
;CLEAR UNWANTED BITS
;PUT "FOUND” INTO R4
;DATA CORRECT?
:1BR IF YES
;ERROR
:SW09=17
sCHANGE TO FLOATING 1
;CLEAR CARRY
;SHIFT BIT IN RO
;IF RO=0 THEN DONE
;sSCOPE THIS TEST

SEQ 61

CZOMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-22
DMC11 MICRO PROCESSOR IBUSs TESTS
26
jhsttd st dbdbdbdbdtsithtsts

TEST

sstsbdbsstnstddbbddbdbsssss

;#MICRO PROCESSOR IBUS# REGISTER WRITE/READ TEST
;#FLOAT A 1 THROUGH IBUS* REGISTER 2

;#FLOAT A O THROUGH IBUS#* REGISTER 2
PRI

;

TR R

TTTTTTTTTITTII
T,
I

TEST 33

frramsancasmane

015734

012737

000033

015750

012737

015770

015756
015760
gg;l%

104412
012702
012700

015770
015774
016002
016004
016006
016010
016012
016014
016020
016024

010061
042761
104414
121102
104414
121045
010005
042705
116104
120504

015742

016026
016030
016032
016034

016036
016040
016042
016050
8{&55:

016056

012737

001401
104004
104401
000241
106100
001353
012737
012700
005100
010061

016062

042761

016072

121102

016070

104414

016074
016076
016100
016102
016106
016112
016114

104414
121045
010005
042705
116104
120504
001401

016120
016122
016124
016126

104401
005100
000241
106100

016116

016130
- 016132

104004

001351
104400

016134

001226

001216

001220

000002
000001
000004
000070

TST33:

65%:

000004

000070

#33, TSTNO

MOV

#6435 ,L0CK

#TST34 ,NEXT

MSTCLR
MOV
MOV

#2,.R2
#1,.RO

MOV
RO,4(R1)
BIC
#70,4(R1)
ROMCLK
121100!2
ROMCLK
121005!<2420>
MOV
RO,RS
BIC
#70,RS
MOVB
S(R1).R4
CcMPB
R5.R4

000004

000070
000005

016056
000001

MOV

001220
gg:
000004

BEQ
EMT
SCoP1
CLC
ROLB
BNE
MOV
MOV
COM

65$%
4

RO
644
#67% ,LOCK
#1,RO
RO

MOV

RO,4(R1)

8IC

ROMCLK

#70,4(R1)

121100!2

000070
000205

688:

:R1 CONTAINS BASE DMC11 ADDRESS
;sMASTER CLEAR DMC11
;SAVE REGISTER ADDRESS FOR TYPEOUT
;START WITH BIT O
;PUT PATTERN INTO PORT4
;CLEAR UNWANTED BITS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOV DATA TO IBUS#* REGISTER 2
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS*+ REGISTER 2
;PUT EXPECTED IN RS
sCLEAR UNWANTED BITS
;PUT "FOUND” INTO R4
;DATA CORRECT?

;:BR IF YES
;ERROR
;SW09=17
;CLEAR CARRY
sSHIFT BIT IN RO
:IF RO=0 THEN DONE
sNEW SCOP1
;START WITH BIT O
;sCHANGE TO FLOATING ZERO
;PUT PATTERN INTO PORT4

;CLEAR UNWANTED BITS

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOV DATA TO IBUS# REGISTER 2

ROMCLK
1210051<2420>
MOV
RO,.RS
BIC
#70,RS
MOVB
S(R1).R4
CHMPB
R5,R4
BEQ
684

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS*+ REGISTER 2
;PUT EXPECTED IN RS
;CLEAR UNWANTED BITS
;PUT "FOUND” INTO R4
;DATA CORRECT?
sBR IF YES

SCoP1
COM
CLC
ROLB

;SW09=17
sCHANGE TO FLOATING 1
sCLEAR CARRY
sSHIFT BIT IN RO

EMT

BNE
SCOPE

RO
RO
69¢

;ERROR

sIF RO=0 THEN DONE
:SCOPE THIS TEST

CZDMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-23

DMC11 MICRO PROCESSOR IBUSs TESTS

shbbsbbbbbdbdbshtddiibdhstts

TEST

sisddddbbdbbbbhbbbbbbbbsbds

;#MICRO PROCESSOR IBUS# REGISTER WRITE/READ TEST

;#FLOAT A 1 THROUGH IBUS# REGISTER 4

;#FLOAT A O THROUGH IBUS# REGISTER 4

R L
TY T TT I
I TTrrT YTM

016134
016142

016150

012737
012737
012737

016156

104412

000034
016310

016170

016160
8{:{%

012702
012700

000004
000001

016170
016174
016176
016200
016202
016204
016206
016212
016214
016216
016220
016222
016224
016226
016230
016236
gi:gg

010061
104414
121104
104414
121105
010005
116104
120504
001401
104004
104401
000241
106100
001360
012737
012700
005100

000004

016244
016250
016252
016254
016256
016260
016262
016266
016270
016272
016274
016276
016300
016302
016304
016306

010061
104414
121104
104414
121105
010005
116104
120504
001401
104004
104401
005100
000241
106100
001356
104400

001226
001216
001220

TST34:

MOV
MOV

MOV

MSTCLR

000005

65%:

016244
000001

TEST 34

001220

g;:

000004

000005

68$:

MOV
MOV

#34,TSTNO
#TST35,NEXT

#64%,L0CK
#4,R2
#1,R0

;:R1 CONTAINS BASE DMC11 ADDRESS
;MASTER CLEAR DMC11

:SAVE REGISTER ADDRESS FOR TYPEOUT
;START WITH BIT 0

MOV
RO,4(R1)
ROMCLK
1211004
ROMCLK
121005!<4420>
MOV
RO,R5
MOVB
S(R1),R4
CMPB
RS,R4
BEQ
654
EMT
4
SCOP1
CLC
ROLB
RO
BNE
644
MOV
9674 ,L0CK
MOV
#1,R0
coM
RO

;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS+ REGISTER 4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS#+ REGISTER 4
;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4
;DATA CORRECT?
:BR IF YES
;ERROR
iSW09=17?
;CLEAR CARRY
sSHIFT BIT IN RO
;IF RO=0 THEN DONE
;NEW SCOP1
sSTART WITH BIT O
;CHANGE TO FLOATING ZERO

MOV
RO,4(R1)
ROMCLK
121100:4
ROMCLK
121005<4+20>
MOV
RO,RS
MOVB
S(R1).R4
CHMPB
RS,R4
BEQ
684
EMT
&
SCOP1
CoM
RO
CLC
ROLB
RO
BNE
694
SCOPE

:PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOV DATA TO IBUS* REGISTER 4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:READ FROM IBUS# REGISTER 4
:PUT EXPECTED IN RS
;PUT “FOUND” INTO R4
;DATA CORRECT?
iBR IF YES
$ERROR
1SW09=1?
sCHANGE TO FLOATING 1
sCLEAR CARRY
+SHIFT BIT IN RO
:IF RO=0 THEN DONE
sSCOPE THIS TEST

shbbdbbbbbdbbtbsdidtsbbitss

TEST 35 sssissssssibssssssdsdssdsiis

;#MICRO PROCESSOR IBUS#+ REGISTER WRITE/READ TEST
;#FLOAT A 1 THROUGH IBUS# REGISTER S
;#FLOAT A O THROUGH IBUS# REGISTER 5

SEQ 63

CZOMC
MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-24
DMC11 MICRO PROCESSOR IBUSs TESTS
L

012737
012737
012737

016332

104412
012702
012700

016334
016340
016344
016344
010061
016350
104414
016352
121105
016354
104414
016356
121125
016360 010005
016362
116104
016366
120504
016370
001401
016372
104004
016374
104401
016376
000241
016400
106100
016402
001360
016404 012737
016412
012700
016416 005100
016420
016420
010061
016424
104414
016426
121105
016430
104414
016432
121125
016434
010005
016436
116104
016442
120504
016444 001401
016446
104004
016450
104401
016452 005100
016454 000241
016456
106100
016460
001356
016462
104400

000035
016464
016344

001226
001216
001220

000005
000001

TST35:

645:

000004

22T iy

MOV
MOV
MOV

#35,TSTNO
#TST36 ,NEXT
#64% ,L0CK

MSTCLR
MOV
MOV

#5,.R2
#1.RO

000005

MOV
RO,4(R1)
ROMCLK
121100!5
ROMCLK
121005!<5420>
MOV
RO,RS
MOVB
S(R1),R4

016420
000001

BEQ
EMT
SCOP1
CcLC
ROLB
BNE
MOV
MOV

CcCMPB

65%:

000004

001220

694:
67%:

comM

RS5,.R4

65$
4

684:

T TITITIIIIIIII

RO
64
9674 ,LOCK
#1.R0

MOV
RO,4(R1)
ROMCLK
121100!5

EMT
SCOP1

COoM

ROLB

CcLC

BNE
SCOPE

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;SAVE REGISTER ADDRESS FOR TYPEOUT
:START WITH BIT O
;PUT PATTERN INTO PORT4
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS#+ REGISTER S
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:READ FROM IBUS* REGISTER S
;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4
;DATA CORRECT?
:BR IF YES
:ERROR

:SW09=17?

ROMCLK
121005!<5420>
MOV
RO,.RS
MOVB
S(R1),.R4
CMPB
RS,R4
BEQ
68

000005

TEST 35

;
016310
016316
016324

;CLEAR CARRY
sSHIFT BIT IN RO
:IF RO=0 THEN DONE
;NEW SCOP1
;START WITH BIT 0
;CHANGE TO FLOATING ZERO

;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOV DATA TO IBUS+ REGISTER S
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

;READ FROM IBUS* REGISTER S
sPUT EXPECTED IN RS
sPUT “FOUND” INTO R4
:DATA CORRECT?
1BR IF YES
;ERROR
$SW09=17
sCHANGE TO FLOATING 1
sCLEAR CARRY
sSHIFT BIT IN RO
:IF RO=0 THEN DONE
sSCOPE THIS TEST

R8s bbdddissdbbisdtbisns

TEST 36

sstssstssssdstbdtsdtddnsiss

+*MICRO PROCESSOR IBUS+ REGISTER WRITE/READ TEST

:#FLOAT A 1 THROUGH IBUS+ REGISTER 10

s#FLOAT A O THROUGH IBUS+ REGISTER 10
+#THE NPR RQ BIT (BIT 0) IS MASKED DURING THIS TEST
L

IY YT

SEQ 64

CZDMC
MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-25
DMC11 MICRO PROCESSOR IBUSs TESTS
016464

012737
012737
012737

016506
016510
016514
016520
016520
016524
016532
016534

104412
012702
012700

016472
016500

016536
016540
016542
016544
016550
016554
016556
016560
016562
016564
016566
016570
016572
016600
016604
016606
016606
016612
016620
016622
016624
016626

016630
016632
016636

016642
016644
016646

016650
016652
016654
016656
016660
016662

010061
042761
104414
121110
104414

121205
010005
042705
116104
120504
001401
104004
104401
000241
106100
001353
012737
012700
005100
010061
042761
104414
121110

104414
121205
010005
042705
116104
120504
001401
104004
104401
005100
000241
106100
001351
104400

000036
016664
016520

001226
001216
001220

64%:

000004

001220
694:

67%:

000141

MOV
MOV

#10,R2
#1.RO

MOV

RO,4(R1)

MOV

RO,RS5

MOVB
CMPB
BEQ
EMT

S(R1),R4
R5,R4
65%
4

ROLB
BNE
MOV
MOV
coM

RO
64$
#67%,L0CK
#1,R0
RO

MOV

RO,4(R1)

MOV
B8IC
MOVB
CHPB
BEQ
EMT

RO,R5
9141,R5
S(R1),.R4
RS,R4
684
4

COoM

ROLB

BIC

654%:

000141

000004

936, TSTNO
#TST37,NEXT
2645 ,L0CK

BIC
©141,4(R1)
ROMCLK
121100:10
ROMCLK
121005!<10+20>

000141
000005

016606
000001

MOV
MOV
MOV
MSTCLR

000010
000001
000004
000141

T5736:

SCOP1
CLC

#141,RS5

BIC
#141,4(R1)
ROMCLK
121100:10
ROMCLK
121005!<10220>

SCOP1

cLC

BNE

SCOPE

69$

iR1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
:SAVE REGISTER ADDRESS FOR TYPEOUT
;START WITH BIT O
;PUT PATTERN INTO PORT4
;CLEAR UNMANTED BITS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOV DATA TO IBUS* REGISTER 10
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS* REGISTER 10
;PUT EXPECTED IN RS

;CLEAR UNWANTED BITS
;PUT "FOUND” INTO R4
;DATA CORRECT?
:BR IF YES
;ERROR

:SWO09=17?

sCLEAR CARRY
;SHIFT BIT IN RO
;IF RO=0 THEN DONE
sNEW SCOP1
sSTART WITH BIT O
;CHANGE TO FLOATING ZERO

;PUT PATTERN INTO PORT4
sCLEAR UNWANTED BITS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOV DATA TO IBUS+ REGISTER 10
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

sREAD FROM IBUS+ REGISTER 10

sPUT EXPECTED IN RS
sCLEAR UNWANTED BITS
sPUT "FOUND” INTO R4
sDATA CORRECT?
+BR IF YES
:ERROR
iSW09=17
sCHANGE TO FLOATING 1
1CLEAR CARRY
sSHIFT BIT IN RO
sIF RO=0 THEN DONE
sSCOPE THIS TEST

$8888444080008040804848004088

TEST

sstssdsssssstssssssssssssss

ssMICRO PROCESSOR IBUSs REGISTER WRITE/READ TEST
#sFLOAT A 1 THROUGH IBUSs REGISTER 11
;#FLOAT A O THROUGH IBUSs REGISTER 11
ssTHE BR RQ BIT, PGM CLOCK BIT, FORCE POMWER FAIL BIT
+#(BITS 7,4,1) ARE ALL MASKED DURING THIS TEST

$i0888844008000540
005808084450 8488885000805840000848040808888048

TEST 37

SEQ 65

CZoMC
MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-26
DMC11 MICRO PROCESSOR IBUSs TESTS

016664
016672
016700

012737
012737
012737

000037
017104
016720

016706
104412
016710 012702 000011
016714
012700 000001
016720
016720 010061
000004
016724
042761
000262
016732
104414
016734
121111
016736
104414
016740
121225
016742 010005
016744 042705 000262
016750 052705
016754
116104
016760 052704
000020
016764
120504
016766 001401
016770
104004
016772
104401
016774 000241
016776
106100
017000 001347
017002 012737 017016
017010 012700 000001
017014 005100
017016
017016 010061 000004
017022 042761 000262
017030 104414 017032
121111
017034 104414
017036
121225
017040 010005
017042 042705 000262
017046 052705 000020
017052 116104
052704 000020
017062
120504
017064 001401
017066 104004
017070 104401

001226
001216
001220

TST37:

644:

000004

005100
000241
106100
001345
104400

#37,TSTNO
#TST40,NEXT
9644 ,L0CK

MSTCLR
MOV
MOV

#11,R2
#1.RO

654:

001220

694:

674%:

sMASTER CLEAR DMC11
;SAVE REGISTER ADDRESS FOR TYPEOUT
sSTART WITH BIT O
;PUT PATTERN INTO PORT4
sCLEAR UNWANTED BITS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
+MOV DATA TO IBUS#+ REGISTER 11
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS+ REGISTER 11
;PUT EXPECTED IN RS
;CLEAR UNMWANTED BITS
+ADD THESE BITS
;PUT "FOUND” INTO R4

CHMPB
BEQ

:DATA CORRECT?
1BR IF YES

EMT

SCOP1
CLC
ROLB
BNE
MOV
MOV
coM

#20,R4

RS,R4
654

RO
644
9674 ,L0CK
1,RO
RO

sADD THIS BIT

sERROR

:SW09=1?
sCLEAR CARRY
sSHIFT BIT IN RO
:IF RO=0 THEN DONE
sNEW SCOP1
sSTART WITH BIT O
tCHANGE TO FLOATING ZERO

MOV
RO,4(R1)
BIC
9262,4(R1)
ROMCLK
12110011
ROMCLK
121005¢<11420>
MOV
RO,RS
8IC
#262,RS
8IS
#20,RS
MOVE
S(R1),.R4
81S
#20,R4

sPUT PATTERN INTO PORT4
sCLEAR UNWANTED BITS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
+MOV DATA TO IBUSs REGISTER 11
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sREAD FROM IBUS* REGISTER 11
1PUT EXPECTED IN RS
$CLEAR UNWANTED BITS
sADD THESE BITS
sPUT "FOUND” INTO R4
sADD THIS BIT

BEQ
EMT
SCOP1
COM
CcLC
ROLB
BNE
SCOPE

sBR IF YES
sERROR
1SW09=17
sCHANGE TO FLOATING 1
sCLEAR CARRY
sSHIFT BIT IN RO
+IF RO=0 THEN DONE
1SCOPE THIS TEST

CMPB

68¢:

;R1 CONTAINS BASE DMC11 ADDRESS

MOV
RO,4(R1)
BIC
#262,4(R1)
ROMCLK
121100!11
ROMCLK
121005!<11+20>
MOV
RO,R5
BIC
9262 ,R5
BIS
420,R5
MOVB
S(R1),R4
BIS

017056

017072
017074
017076
017100
017102

MoV
MOV
MOV

RS,.R4

684
4

RO
RO
694

1DATA CORRECT?

169858848082840880880048888068 TEST 40 8680888080800 88004800080000s8

ssMICRO PROCESSOR IBUS REGISTER MRITE/READ TEST
:oFLOAT A 1 THROUGH IBUS REGISTER O
3sFLOAT A O THROUGH IBUS REGISTER O

SEQ 66

CZoMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-27
DMC11 MICRO PROCESSOR IBUS TESTS
3:808084888488880808288888808888 8240288880208ktt

TEST &0

;
R

017104
017112
017120

012737
012737
012737

017126
017130
017134
017140
017140
017144
017146
017150
017152

104412
012702
012700

017154

017156
017162
017164
017166
017170
017172
017174
017176
017200
017206
017212
017214
017214
017220
017222
017224
017226
017230
017232
017236
017240
017242
017244

017246
017250

017252
017254
017256

010061
104414
122100
104414
021005
010005
116104

120504

000040
017260
017140

001226
001216
001220

000000
000001

7T1S740:

000004

000005

001401

104005
104401
000241
106100
001360
012737
012700
005100
010061
104414
122100
104414

021005
010005
116104
120504
001401
104005
1044901
005100

65%:

017214
000001

001220
69%:
67%:

000004

000005

68%:

000241
106100
001356
104400

bbdbbbttbbtbta

s i

MOV

9643 ,L0CK

MSTCLR
MOV
MOV

#0.R2
#1.R0O

MOV

OTST41 ,NEXT

MOV
RO,4(R1)
ROMCLK
12210010
ROMCLK
210051 <0220>
MOV
RO,R5
MOVB
S(R1).R4
cMPB
RS,.R4
BEQ
65
EMT
S
SCOP1

CLC
ROLB
BNE
MOV
MOV
coM

RO
643
8674 ,L0CK
#1.R0
RO

MOV
RO,4(R1)
ROMCLK
122100:0
ROMCLK
21005 <0+20>
MOV
RO,RS
MOVB
S(R1).R4
cMP8
RS.R4
BEQ
68
EMT
S
SCoP1
coM
RO
CLC
ROLB
RO
BNE
69
SCOPE

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
:SAVE REGISTER ADDRESS FOR TYPEOUT
:START WITH BIT O
;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
MOV DATA TO IBUS REGISTER O
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER 0
;PUT EXPECTED IN RS

sPUT “FOUND” INTO R4
;sDATA CORRECT?
;BR IF YES

sERROR
;SH09=1?

;CLEAR CARRY
;SHIFT BIT IN RO
;IF RO=0 THEN DONE
sNEW SCOP1
sSTART WITH BIT O
;CHANGE TO FLOATING ZERO

;PUT PATTERN INTO PORT4
;sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER O
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER 0
:PUT EXPECTED IN RS
;PUT "FOUND” INTO R4
;DATA CORRECT?
;BR IF YES

;ERROR

:5W09=12
sCHANGE TO FLOATING 1
sCLEAR CARRY
sSHIFT BIT IN RO
;IF RO=0 THEN DONE
sSCOPE THIS TEST

8888480408040 000000000000480

TEST

ststassiddttddidtddddbdddis

;#MICRO PROCESSOR IBUS REGISTER WRITE/READ TEST
:#FLOAT A 1 THROUGH IBUS REGISTER 1
;#FLOAT A 0 THROUGH IBUS REGISTER 1
Ji08

:
017260

012737

000041

001226

TST41:

80040044000 08004040 0588000000880 0 0000500000000 0400000000440

TEST 41
#41,TSTNO

—

R—

SEQ 67

MACRO V04.00
C2oMC
27-JUN-85 13:16:37 PAGE 27-28
OMCi1 MICRO PROCESSOR IBUS TESTS

17266
017274

012737
012737

017302
017304
017310
017314
017314
017320
017322
017324
017326
017330
017332
017336
017340
017342
017344
017346
017350
017352
017354
017362
017366
017370
017370
017374
017376
017400
017402
017404
017406
017412
017414
017416
017420
017422
017424
017426
017430
017432

104412
012702
012700
010061
104414
122101
104414

021025
010005
116104
120504
001401
104005
104401
000241
106100
001360
012737
012700
005100
010061
104414
122101
104414
021025
010005
116104
120504
001401
104005
104401
005100
000241
106100
001356
104400

017434
017314

001216
001220

MOV
MOV
MSTCLR

MOV

000001
000001

MOV

000004

000005

65%:

000001

001220
69%:

67%:

000004

000005

:R1 CONTAINS BASE DMC11 ADDRESS

#1.R2
1,R0

MOV
RO,4(R1)
ROMCLK
1221001
ROMCLK
210051 <1420>
MOV
RO,RS
MOVB
S5(R1),R4
cMPB
R5,R4
BEQ
65$
EMT
5
SCoP1

CLC

ROLB

017370

8TST42 ,NEXT
9643 ,L0CK

BNE
MOV
MOV
com

64
#674,L0CK
21.R0
RO

MOV
R0,4(R1)
ROMCLK
122100°1
ROMCLK
21005!<1420>
MOV
RO,RS
MOVB
S(R1).R4

cMPB

RS,.R4

BEQ

683

SCOP1
coM
CLC

EMT

ROLB

BNE
SCOPE

69¢

sMASTER CLEAR DMC11

:SAVE REGISTER ADDRESS FOR TYPECUT
sSTART WITH BIT O

;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOV DATA TO IBUS REGISTER 1
¢NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER 1
;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4
;sDATA CORRECT?
;:BR IF YES
;ERROR
;SW09=1?
;CLEAR CARRY
:SHIFT BIT IN RO
;IF RO=0 THEN DONE
;:NEW SCOP1

;START WITH BIT O

;CHANGE TO FLOATING ZERO

;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER 1
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sREAD FROM IBUS REGISTER 1
;PUT EXPECTED IN RS
;:PUT “FOUND” INTO R4
sDATA CORRECT?
:BR IF YES

;ERROR

sSW09=17?
sCHANGE TO FLOATING 1
;CLEAR CARRY
;SHIFT BIT IN RO
;IF RO=0 THEN DONE
;SCOPE THIS TEST

;88080000 d0bttbandbdittiiis

TEST

stsesididtdddsbtddddestssss

;#MICRO PROCESSOR IBUS REGISTER WRITE/READ TEST
;#FLOAT A 1 THROUGH IBUS REGISTER 2
;#FLOAT A O THROUGH IBUS REGISTER 2

$:008888884408408458240450884800048
0080000000000
000R0a0bkdtttd

017434
017442
017450

012737
012737
012737

000042
017610
017470

017456
017460

104412
012702

000002

001226
001216
001220

TST42:

MOV
MOV
MOV

#42,TSTNO
#TST43,NEXT
#6453 ,L0CK

MOV

#2,R2

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
+SAVE REGISTER ADDRESS FOR TYPEOUT

czomMC

MACRO v04.00 27-JUN-85 13:16:37 PAGE 27-29

OMC11 MICRO PROCESSOR IBUS TESTS
017464
017470
017470
017474
017476
017500
017502
017504
017506

012700

000001

010061
104414
122102
104414
021045
010005
116104

000004

017514

001401

017512

017516
017520
017522

106100
001360
012737
012700

017544
017550
017552
017554
017556
017560
017562
017566
017570
017572

010061
104414
122102
104414
021045
010005
116104
120504
001401

005100

017574
017576

104005
104401
005100

017602
017604
017606

106100
001356
104400

017600

000005

MOV

65%:

017544
000001

001220

69s$:
67%:

000004

000005

68%:

000241

#1,.RO

;START WITH BIT O

MOV
RO,4(R1)
ROMCLK
12210022
ROMCLK
21005!<2420>
MOV
RO,.R5
MOVB
S(R1).R4

CMPB

R5.R4

EMT
SCoP1
CLC

BEQ

104005
104401
000241

017524
017526
017530
017536

017542
017544

120504

645%:

ROLB
BNE
MOV
MOV

CoM

654

;BR IF YES

RO
644
#67%,L0CK
#1.RO

MOV
RO,4(R1)
ROMCLK
122100:2
ROMCLK
21005 <2+20>
MOV
RO,RS
MOVB
S(R1),R4
CMPB
R5,R4
BEQ
68%
EMT
5

SCoP1
CcoM

CLC

ROLB
BNE
SCOPE

;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER 2
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER 2
;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4
;DATA CORRECT?

;ERROR
:SW09=1?
;CLEAR CARRY

;SHIFT BIT IN RO
:IF RO=0 THEN DONE
sNEW SCOP1

;START WITH BIT 0
;CHANGE TO FLOATING ZERO
;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER 2
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:READ FROM IBUS REGISTER 2
;PUT EXPECTED IN RS
:PUT “FOUND” INTO R4
;DATA CORRECT?
;:BR IF YES
;ERROR

:SW09=17?
sCHANGE TO FLOATING 1
;:CLEAR CARRY

RO
69¢

;SHIFT BIT IN RO
:IF RO=0 THEN DONE
sSCOPE THIS TEST

;488 ss bbb bbsbtbbittttttiins

TEST

sissstdtibsshbbisshbbdddbis

;#MICRO PROCESSOR IBUS REGISTER WRITE/READ TEST
;+FLOAT A 1 THROUGH IBUS REGISTER 3
s#FLOAT A O THROUGH IBUS REGISTER 3
$:8 8484058 8

;

858080 kk ARttt it ittt

ittt bdbibbbdb bbb bhihibhind

TEST 43

‘ --------------

017610
017616
017624

012737
012737
012737

017632
017634
017640

104412
012702
012700

017644
017650
017652

010061
104414
122103

017644

000043
017764
017644

000003
000001
000004

001226
001216
001220

TST43:

64%:

MOV
MOV
MOV

MSTCLR
MOV
MOV

#43,TSTNO
#7S744 ,NEXT
#6453 ,L0CK

#3,R2
#1,R0

MOV
RO,4(R1)
ROMCLK
122100!3

sR1 CONTAINS BASE DMC11 ADDRESS
;MASTER CLEAR DMC11
sSAVE REGISTER ADDRESS FOR TYPEOUT
;START WITH BIT O

;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER 3

SEQ 69

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-30
OMC11 MICRO PROCESSOR IBUS TESTS
017654
017656
017660
017662
017666
017670

104414
021065
010005
116104
120504
001401

017674
017676
017700
017702
017704
017712

104401
000241
106100
001360
012737
012700

017672

017716

017720
017720
017724
017726
017730
017732
017734
017736
017742
017744
017746
017750
017752
017754
017756
017760
017762

ROMCLK
21005 <3420>
MOV
RO,RS5
MOVB
S(R1).R4
cMPB
R5.R4
BEQ
65%

000005

104005

005100
010061
104414
122103
104414
021065
010005
116104
120504
001401
104005
104401
005100
000241
106100
001356
104400

65%:

017720
000001

001220

695:
67%:

000004

000005

68%:

EMT

SCoP1
CLC
ROLB
BNE
MOV
MOV

coM

RO
64%
#67%,L0CK
#1,R0

MOV
RO,4(R1)
ROMCLK
122100!3
ROMCLK
21005!<3420>
MOV
RO,RS
MOVB
S(R1),.R4
CMPB
R5,R4
BEQ
68$
EMT
5
SCOP1
CoM
RO
CLC
ROLB
RO
BNE
694
SCOPE

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER 3
;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4

;DATA CORRECT?
;BR IF YES

;ERRCR
:SH09=1?

;CLEAR CARRY
sSHIFT BIT IN RO
;IF RO=0 THEN DONE
sNEW SCOP1
;START WITH BIT O
;CHANGE TO FLOATING ZERO

;PUT PATTERN INTO PORT4

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER 3

;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER 3
;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4
:DATA CORRECT?
:BR IF YES
;ERROR
:SW09=17?
;CHANGE TO FLOATING 1
;:CLEAR CARRY
;SHIFT BIT IN RO
;IF RO=0 THEN DONE
:SCOPE THIS TEST

shdbbbbdbsbtbbhbbhibbhibiits

TEST

stsddsdbbsbbhsbsbbsbbsddds

;#MICRO PROCESSOR IBUS REGISTER WRITE/READ TEST
:#FLOAT A 1 THROUGH IBUS REGISTER 4

:#FLOAT A 0 THROUGH IBUS REGISTER 4

LT
y
T
P
P T PP PP PePP T ees

;

TEST 44

‘ --------------

017764
017772
020000

012737
012737
012737

020006
020010
020014
020020
020020
020024
020026
020030
020032
020034
020036
020042

104412
012702
012700
010061
104414
122104
104414
021105
010005
116104
120504

000044
020140
020020
000004
000001
000004

000005

001226
001216
001220

TST44:

64%:

MOV
MOV
MOV

#44,TSTNO
4TST4S5,NEXT
%644 ,L0CK

MSTCLR
MOV
MOV

&4 ,R2
#1,RO

MOV
RO,4(R1)
ROMCLK
1221004
ROMCLK
21005!<4+20>
MOV
RO,RS
MOVB
S(R1),R4
cMPB
R5,R4

sR1 CONTAINS BASE DMC11 ADDRESS

sMASTER CLEAR DMC11
:SAVE REGISTER ADDRESS FOR TYPEOUT
:START WITH BIT O
;PUT PATTERN INTO PORT4

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER 4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER 4
;PUT EXPECTED IN RS
;PUT "FOUND” INTO R4
sDATA CORRECT?

J———

SEQ 70

MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-31
CZDMC
OMC11 MICRO PROCESSOR IBUS TESTS

020044
020046
020050

020052
020054
020056

020060
020066
020072

020074
020074
020100
020102
020104
020106
020110
020112
020116
020120
020122
020124
020126
020130
020132
020134
020136

001401
104005
104401
000241
106100
001260

012737

012700

005100
010061
104414
122104
104414
021105
010005
116104
120504
001401
104005
104401
005100
000241
106100
001356
104400

65%:

020074
000001

001220
69%:
67%:

000004

000005

BEQ
EMT
SCoP1
CcLC
ROLB
BNE
MOV
MOV

comM

RO
64%
#67% ,L0CK
#1,RO

68$

EMT

COoM

SCOP1

CLC
ROLB
BNE
SCOPE

:BR IF YES
;ERROR

;SH09=1?

MOV
RO,4(R1)
ROMCLK
122100:4
ROMCLK
21005! <420>
MOV
RO,R5
MOVB
S5(R1).R4
CMPB
R5,R4

BEQ

68$:

65%
5

RO
69$

;CLEAR CARRY
;SHIFT BIT IN RO
;IF RO=0 THEN DONE
sNEW SCOP1
sSTART WITH BIT 0O
;CHANGE TO FLOATING ZERO

;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
MOV DATA TO IBUS REGISTER 4
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER 4
;PUT EXPECTED IN RS

;PUT

“FOUND” INTO R4

;DATA CORRECT?
;BR IF YES
;ERROR
:SW09=17

;CHANGE TO FLOATING 1
;CLEAR CARRY
;SHIFT BIT IN RO
;:IF RO=0 THEN DONE
;:SCOPE THIS TEST

shsbdbhsbdidbbhbbihbbbbiihis

TEST

sadssktthbbdbbbbbhhhbdhdhhs

;#MICRO PROCESSOR IBUS REGISTER WRITE/READ TEST

;#FLOAT A 1 THROUGH IBUS REGISTER S5
;#FLOAT A 0 THROUGH IBUS REGISTER 5

P
PP TP P
TP,

TEST 45

: ..............

020140
020146

012737
012737
012737

020162
020164
020170
020174
020174
020200
020202
020204
020206
020210
020212
020216

104412
012702
012700

020154

020220
020222
020224
020226
020230

010061
104414
122105

104414
021125
010005
116104
120504
001401
104005
104401
000241
106100

000045
020314
020174

000005
000001
000004

001226
001216
01220

TSTAS:

644:

000005

65%:

MOV
MOV
MOV

MSTCLR
MOV
MOV

45, TSTNO
@TST46,NEXT
#64$,L0CK

95.R2
91.RO

MOV
RO,4(R1)
ROMCLK
12210015
ROMCLK
210051 <5420>
MOV
RO,RS
MOVB
S(R1),R4
CMPB
RS,R4
BEQ
65%
EMT
S
SCOP1
CcLC
ROLB
RO

;R1 CONTAINS BASE DMC11 ADDRESS

;MASTER CLEAR DMC11

:SAVE REGISTER ADDRESS FOR TYPEOUT
sSTART WITH BIT O
;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER S
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER S5
;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4

;DATA CORRECT?

;BR IF YES
;ERROR

:SW09=1?
sCLEAR CARRY
;SHIFT BIT IN RO

SEQ 71

MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-32
CZDMC
DMC11 MICRO PROCESSOR IBUS TESTS

020232

020234
020242
020246
020250
020250
020254

020256
020260
020262
020264
020266
020272
020274
020276
020300
020302
020304
020306
020310
020312

001360
012737
012700
005100
010061
104414
122105
104414
021125
010005
116104

120504
001401
104005
104401
005100
000241
106100
001356

020250
000001

001220
69%:
67%:

000004

000005

68%:

644
#67$,L0CK
#1.R0

MOV
MOV
CoM

MOV
RO,4(R1)
ROMCLK
122100!5
ROMCLK
21005! <5%20>
MOV
RO,R5
MOVB
S(R1).R4

CMPB
BEQ
EMT
SCOP1
COM
CcLC

R5,R4
68$
5
RO

ROLB

BNE
SCOPE

104400

69¢

:IF RO=0 THEN DONE
;NEW SCOP1
;START WITH BIT 0
;CHANGE TO FLOATING ZERO

;PUT PATTERN INTO PORT4
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER S
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sREAD FROM IBUS REGISTER S

;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4

;:DATA CORRECT?
:BR IF YES
;ERROR
:SH09=1?
sCHANGE TO FLOATING 1
;CLEAR CARRY
sSHIFT BIT IN RO

;IF RO=0 THEN DONE

:SCOPE THIS TEST

shhbbkbbbbbbbbtbbhhhbhbdhsiis

TEST

sstrbsskbdbbhtbbbtbsbbbbbbdds

:#MICRO PROCESSOR IBUS REGISTER WRITE/READ TEST
:#FLOAT A 1 THROUGH IBUS REGISTER 6
+#FLOATA O THROUGH IBUS REGISTER 6

LTI

TEST 46

PP rPrerrrres

' ..............

020314
020322
020330

012737
012737
012737

020336
020340
020344
020350
020350
020354
020356
020360
020362
020364

104412
012702
012700

020366
020372

020374
020376
020400

020402
020404
020406
020410

020416
020422
020424

000046
020470
020350

001226
001216
001220

000006
000001

644:

010061
104414
122106
104414

021145
010005
116104
120504
001401
104005

MOV
MOV
MOV

946, TSTNO
#TST47 ,NEXT
9644 ,L0CK

MSTCLR
MOV
MOV

#6,R2
#1.RO

MOV

RO,4(R1)

ROMCLK
1221006
ROMCLK

000005

104401
000241

106100
001360
012737
012700
005100

TST46:

65%:

21005!<6420>
MOV
RO,RS
MOVB
S(R1).R4
CMPB
R5,.R4
BEQ
65¢
EMT
S
SCOP1
CLC
ROLB

020424
000001

001220

69¢:
67$:

BNE
MOV
MOV
CoM

64%
2674 ,L0CK
#1,R0
RO

sR1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
:SAVE REGISTER ADDRESS FOR TYPEOUT
;START WITH BIT O
;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
MOV DATA TO IBUS REGISTER 6
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER 6
;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4
;:DATA CORRECT?

;BR IF YES

;ERROR
;SW09=17?
;CLEAR CARRY
sSHIFT BIT IN RO
;IF RO=0 THEN DONE
sNEW SCOP1
;START WITH BIT O
;CHANGE TO FLOATING ZERO

CZOMC

SEQ

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-33

DMC11 MICRO PROCESSOR IBUS TESTS

020424
020430
020432
020434
020436
020440
020442
020446
020450
020452
020454
020456
020460

020462
020464
020466

010061
104414
122106
104414
021145
010005
116104
120504
001401
104005
104401
005100
000241

000004

000005

68%:

106100
001356

MOV
RO,.4(R1)
ROMCLK
12210016
ROMCLK
21005!<6+20>
MOV
RO,RS
MOVB
S(R1).R4
CMPB
R5,R4
BEQ
68%
EMT
5
SCOP1
CoM
RO
CLC

;PUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO IBUS REGISTER 6
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:READ FROM IBUS REGISTER 6
sPUT EXPECTED IN RS
;PUT “FOUND” INTO R4
;DATA CORRECT?
;BR IF YES
;ERROR
:SW09=1?
;CHANGE TO FLOATING 1
;CLEAR CARRY

SCOPE

:SCOPE THIS TEST

ROLB
BNE

104400

RO
694

;SHIFT BIT IN RO
:IF RO=0 THEN DONE

shkkdhbhhbbbbhhbhbdhhhihinhs TEST 47 sbhhkhshhbbbbdhbbbbsdhhsbss

:#*MICRO PROCESSOR IBUS REGISTER WRITE/READ TEST

;#FLOAT A 1 THROUGH IBUS REGISTER 7

;#FLOAT A O THROUGH IBUS REGISTER 7

;

TEST 47

rrrwws

3 --------------

020470
020476

020504

012737

000047
020644
020524

020512
020514

104412
012702

000007

gggggg

012700

000001

020524
020530

010061
104414

000004

020536
020540
020542
020546
020550
020552
020554
020556
020560
020562
020564
020572

ggg‘szg

021165
010005
116104
120504
001401
104005
104401
000241
106100
001360
012737
012700
005100

020600
020604
020606
020610
020612

010061
104414
122107
104414
021165

020532
020534

012737
012737

001226
001216
001220

TST47:

MOV
MOV
MOV

MSTCLR
MOV
MOV

MOV
ROMCLK

122107
104414

#47,TSTNO
#TST50,NEXT

9644 ,L0CK

#7,R2

#1.R0

RO,4(R1)

1221007
ROMCLK
-

000005

65%:

020600
000001
000004

001220

g;:

.
;R1 CONTAINS BASE DMC11 ADDRESS
:MASTER CLEAR DMC11
sSAVE REGISTER ADDRESS FOR TYPEC.T
sSTART WITH BIT O

sPUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

;MOV DATA TO IBUS REGISTER 7
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

21005¢ <7+20>
MOV
RO.RS
MOVB
S(R1).R4
CMPB
R5,R4
BEQ
654
EMT
S
SCOP1
cLC
ROLB
RO
BNE
64%
MOV
#6748 ,L0CK
MOV
#1.R0

;READ FROM IBUS REGISTER 7
sPUT EXPECTED IN RS
;PUT "FOUND” INTO R4
;DATA CORRECT?
sBR IF YES
;ERROR
1SW09=17
sCLEAR CARRY
$SHIFT BIT IN RO
+IF RO=0 THEN DONE
sNEW SCOP1
:START WITH BIT O
;CHANGE TO FLOATING ZERO

MOV
RO,4(R1)
ROMCLK
122100!7
ROMCLK
21005!<7420>

sPUT PATTERN INTO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOV DATA TO IBUS REGISTER 7
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sREAD FROM IBUS REGISTER 7

com

. 72

SEQ 73

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-34
OMC11 MICRO PROCESSOR IBUS TESTS

020614
020616
020622

020624

020626

020630
020632
020634
020636

020640
020642

010005
116104

120504
001401
104005
104401
005100
000241
106100
001356
104400

000005

68%:

MOV
MOVB
CMPB
BEQ
EMT
SCOP1
CoM
CLC
ROLB
BNE
SCOPE

RO,RS
S5(R1),R4
R5,.R4
684
5

;PUT EXPECTED IN RS
;PUT “FOUND” INTO R4
;DATA CORRECT?
;BR IF YES
;ERROR
;SW09=1?
;CHANGE TO FLOATING 1
;CLEAR CARRY
;SHIFT BIT IN RO
;IF RO=0 THEN DONE
;SCOPE THIS TEST

RO
RO
69%

iddbbssbdbdhbhhbibihbtitiis

TEST

sdssbsbddbbbsbbbbbbbsbbibss

;#*MICRO PROCESSOR IBUS DUAL ADDRESS TEST
;*WRITE ALL IBUS REGISTERS WITH INCREMENTING PATTERN
:#READ ALL IBUS REGISTERS TO VERIFY CORRECT ADDRESSING

R
A
PP

TEST 50

‘ --------------

020644
020652
020660

012737
012737
012737

020666
020670
020674
020676
020700
020704
020712
020716
020720
020722
020724

104412
012700
005002
010203
010061
042737
050337
104414
122100
006303
006303
006303
006303
042737
050337
104414
021005
010005
116104
120504
001401
104005

020726
020730
020732
020740

020744

020746
020750
020752
020756
020760
020762
020764
020766
020770

020772
020776

021000
021006
021012
021014
021016

000050
021072
020676

001226
001216
001220

000001

000004
000017
020720

1$:

020720
5%:

000360
020746

020746

6%:
000005

MOV
MOV
MOV
MSTCLR
MOV
CLR
MOV
MOV
BIC
BIS
ROMCLK
122100
ASL
ASL
ASL
ASL
8IC
BIS
ROMCLK
21005
MOV
MOVB

CHMPB

104401

005200
005202
022702
001337
012737
012700
005002
005003
042737

TST50:

28:

000010

021016
000001

001220

000360

021032

38:

BEQ
EMT
SCOP1
INC
INC
cMP
BNE
MOV
MOV
CLR
CLR
BIC

@50, TSTNO
#TSTS1,NEXT
#14$,L0CK
#1,RO
R2
R2,R3
RO,4(R1)
#17,5%

R3,5$

R3
R3
R3
R3
#360,6¢
R3,6%
RO,RS5
S(R1).R4

RS.R4
24
5

RO
R2

#7+1,R2

1s
#3$,L0CK
#1.RO
R2
R3
#360,7%

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;START WITH A ONE
;R2 CONTAINS ADDRESS OF REGISTER
;R3=REGISTER ADDRESS
;WRITE DATA TO PORT4
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE DATA TO IBUS REGISTER
:SHIFT ADDRESS
:4 TIMES TO GET
;IT 70 BITS 4-7
;OF NEXT INSTRUCTION

;CLEAR ADDRESS FIELD
sADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;READ FROM IBUS REGISTER
;PUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
;IS DATA CORRECT?

;BR IF YES
sDATA ERROR
1SW09=17?
s INCREMENT PATTERN
s INCREMENT REGISTER ADDRESS

;LAST ADDRESS DONE?

;BR IF NO
sNEW SCOP1
sRESTART PATTERN TO 1
sRESTART AT ADDRESS 0
sRESTART AT ADDRESS 0
sCLEAR ADDRESS FIELD OF INSTRUCTION

SEQ 74

CZDMC
MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-35
DMC11 MICRO PROCESSOR IBUS TESTS
021024
021030

021032
021034
021036
021042
021044
021046
021050
021052
021054
021056
021062
0210€6
021070

050337
104414
021005
010005
116104
120504
001401
104005
104401
005200
005202
062703
022702
001353
104400

021032
7%:

000005

4%:

000020
000010

BIS
ROMCLK
21005
MOV
MOVB
CcMPB
BEQ
EMT
SCOP1
INC
INC
ADD
CHP
BNE
SCOPE

R3,7$

;ADD ADDRESS TO INSTRUCTION
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:READ FROM IBUS REGISTER
;PUT "EXPECTED" IN RS
;PUT “FOUND” IN RS

RO,RS
S5(R1).R4
R5,.R4

RO
R2
#20,R3
#7+1,R2
3s

;:DATA CORRECT?
:BR IF YES
;:DUAL ADDRESSING ERROR
:SW09=1?
; INCREMENT PATTERN
;NEXT ADDRESS
;ADD 1 TO ADDRESS IN R3(SHIFTED 4 TIMES)

;LAST ADDRESS DONE?

;BR IF NO
:SCOPE THIS TEST

jhhkbbbbbhbihbhbhbbhbbihbhibia

TEST

;*MICRO PROCESSOR BR REGISTER TEST
s#FLOAT A 1 THROUGH THE BR

stsshsbbdbsdsbbbdbbbbbdbdss

;#FLOAT A 0 THROUGH THE BR

R
Y
PP PP PP,

:
G

021072
021100
021106

012737
012737
012737

021114
021116
021122
021122
021126
021130
021132
021134
021136
021140
021144
021146
021150
021152
021154
021156
021160
021162
021170
021174
021176
021176
021202
021204
021206
021210
021212
021214

104412
012700

000001

010061

000004

104414
120500
104414
061225
010005
116104
120504
001401
104006
104401
000241
106100
001360
012737
012700
005100
010061
104414
120500
104414
061225

010005
116104

000051
021242
021122

001226
001216
001220

TST51:

644:

000005

65¢%:

021176
000001

000004

000005

001220

69$:
67%:

TEST 51
i

MOV

#51,TSTNO

MOV
MoV

#TSTS52,NEXT
#64$,L0CK

MSTCLR
MOV

#1,RO

MOV
ROMCLK
120500
ROMCLK
061225
MOV
MOVB
CMPB
BEQ
EMT
SCOP1
CLC
ROLB
BNE
MOV
MOV
coM
MOV
ROMCLK
120500
ROMCLK
061225
MOV
MOVB

RO,4(R1)

RO,RS
S5(R1).R4

R5,.R4
654
6

;R1 CONTAINS BASE DMC11 ADDRESS
:MASTER CLEAR DMC11
;START PATTERN WITH BITO
;WRITE PATTERN IN PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE DATA TO THE BR REGISTER
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE BR TO PORT S
;PUT "EXPECTED” IN RS
:PUT "FOUND” IN R4
:DATA CORRECT?
:BR IF YES
;DATA ERROR

:CLEAR CARRY
sSHIFT BIT IN RO
;DONE IF RO=0
sNEW SCOP1
+START PATTERN WITH BITO
;CHANGE TO FLOATING ZERO

RO,4(R1)

;WRITE PATTERN IN PORT4

RO
644
@674,L0CK

#1,R0

RO,R5
S(R1).R4

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE DATA TO THE BR REGISTER
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE BR TO PORT S5
sPUT "EXPECTED" IN RS
;PUT “FOUND”" IN R4

SEQ 75

CZDMC
MACRO V04.00
27-JUN-85 13:16:37 PAGE 27-36
DMC11 MICRO PROCESSOR IBUS TESTS

021220

021222

021224
021226
021230
021232
021234
021236
021240

120504

CMPB

104006
104401
005100
000241
106100
001356
104400

EMT
SCOP1
CcoM
CLC
ROLB
BNE
SCOPE

001401

BEQ

685:

R5.R4

;DATA CORRECT?

;DATA ERROR

68¢

RO
69%

;BR IF YES

;CHANGE BACK TO A ONE
;CLEAR CARRY

;SHIFT BIT IN RO
;DONE IF RO=0
;SCOPE THIS TEST

jhbkdbkbhhkihkbbbhbhbibbhbbhttsds

TEST

;#SCRATCH PAD TEST

shbhhbhdrbbbbbhbhhsbbbhbhds

;#FLOAT A 1 THROUGH EACH SCRATCH PAD LOCATION

;#FLOAT

A O THROUGH EACH SCRATCH PAD LOCATION

;

TEST S2

Ll Ll

, --------------

021242
021250
021256

012737
012737
012737

021264

104412

021266
021270
021274
021302
021306
021312
021314
021316
021324
021330
021332

021334
021336
021340
021342
021346

021350

005002
012700
042737
050237
010061
104414
123100
042737
050237
104414
040600

104414
061225
010005
116104
120504

104007
104401
000241
106100
001344
012737
012700
005100

021416
021420

104414
123100

021422
021430

021434

001226
001216
001220

TSTS52:

000001
000017
021314
000004
x
000017
021332

021314

021332

64%:

65%:

66%:

000005

CLR
MOV
BIC
BIS
MOV
ROMCLK
123100
BIC
BIS
ROMCLK
040600

ROMCLK
061225
MOV
MOVB
cMPB
BEQ

67%:

021400
000001

001220

042737
050237
010061

000017
021420
000004

021420

042737
050237

000017
021436

021436

104414

MOV
MOV
MOV

MSTCLR

001401

021352
021354
021356
021360
021362
021364
021372
021376
021400
021406
021412

000052
021510
021274

73%:
69%:

708:

EMT
SCOP1
CLC
ROLB
BNE
MOV
MOV
COM

BIC
BIS
MOV
ROMCLK
123100
BIC
BIS

ROMCLK

#52, TSTNO
#TSTS3 ,NEXT
#64$ ,L0CK

R2
#1,RO
917,654
R2,65$

RO,4(R1)
#17,66%
R2,66%

RO,RS
S(R1),R4
RS,R4
674
7
RO
644
#69% ,LOCK
#1,.R0
RO
#17,70%
R2,70$
RO,4(R1)
217,714
R2,71%

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC1i1

;START AT ADDRESS ZERO
:START WITH BITO
;:CLEAR ADDRESS FIELD OF INSTRUCTION
;+ADD ADDRESS TO INSTRUCTION

:WRITE PATTERN TO PORT4
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:WRITE SCRATCH PADCADDRESS IN R2)
:CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV SP TO BR
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORTS
;PUT “EXPECTED” IN RS
;PUT "FOUND” IN R4
:DATA CORRECT
+BR IF YES
;DATA ERROR
:SW09=17
;CLEAR CARRY
;SHIFT BIT IN RO
sDONE IF RO=0
;NEW SCOP1
;START WITH BITO
;CHANGE TO FLOATING ZERO
sCLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
;WRITE PATTERN TO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;WRITE SCRATCH PAD(ADDRESS IN R2)

sCLEAR ADDRESS FIELD OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

CZDMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-37

7
sl

DMC11 SCRATCH PAD TESTS

021436

040600

021446
021452

116104
120504

021440 104414
021442 061225
021444 010005

718:

000005

021460

021464

104401

728:

005100

RO,RS

BEQ
EMT

72%
7

:BR IF YES
:DATA ERROR

SCOP1

ROLB

INC

cLC

021470 001342
021472 012700 000001

BNE
MOV

021476

106100

005202

021500 022702 000020
021504 001273
. 021506 104400

S(R1).R4
RS,R4

coM

000241

021466

;MOV SP TO BR

:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE BR TO PORTS
;PUT "EXPECTED” IN RS

MOVB
CMPB

021454 001401
021456 104007

021462

040600

ROMCLK
061225
MOV

CMP
BNE
SCOPE

;PUT “FOUND” IN R4
:DATA CORRECT
:1SW09=17

;CHANGE BACK TO A ONE

;CLEAR CARRY

;SHIFT BIT IN RO

738
#1,RO

#20,R2
64$

;:DONE IF RO=0
;RESTART AT BIT 0
;sNEXT SP ADDRESS

;LAST ADDRESS?
:BR IF NO
:SCOPE THIS TEST

jhhkbhbsibihbnhhhbdbibbbdtik

TEST

ssssbtdbbsbsbsbsbsssdsddsss

;#SCRATCH PAD DUAL ADDRESSING TEST
:#WRITE AN INCREMENTING PATTERN IN ALL SP LOCATIONS
+#READ ALL SP LOCATIONS TO VERIFY CORRECT ADDRESSING

R
PP P Y P PPP PP PR

:
021510
021516
021524

012737

021532
021534
021540
021542
021544
021552
021556
021562
021564

104412
012700
005003
010302
042737
050237
010061
104414
123100

021566

021574
021600
021602
021604
021606
021610
021612
021616
021620
021622
021624
021626
021630
021632
021636

012737
012737

042737

050237
104414
060600
104414
061225
010005
116104
120504
001401
104007
104401
005200
005203
022703
001341

000053
021732
021542

001226
001216

TSTS3:

001220

000001
000017
021564
000004

021564

000017

021602

1$:

2%:

38:

000005

4s:
000020

TEST 53

MOV
MOV
MOV

MSTCLR
MOV
CLR
MOV
8IC
BIS
MOV
ROMCLK
123100
BIC

BIS
ROMCLK
60600
ROMCLK
61225
MOV
MOVB
CMPB
BEQ
EMT
SCOP1
INC
INC
CcMP
BNE

53, TSTNO
#TST54 ,NEXT
#14,L0CK

#1,R0
R3
R3,R2
017,23
R2,2%
RO,4(R1)
917,3%

R2,3%

RO,.RS
S(R1),R4

R5.R4
45
7

RO
R3
#20,R3
13

sR1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sSTART WITH A 1
:ADDRESS 0
;MOVE ADDRESS TO R2
:CLEAR ADDRESS FIELD
;ADD ADDRESS TO INSTRUCTION
sWRITE PATTERN TO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

sWRITE SPC(ADDRESS IN R2)

;CLEAR ADDRESS FIELD OF INSTRUCTION

+ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOV SP TO BR
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOV BR TO PORTS
sPUT "EXPECTED” IN RS
;PUT “FOUND” IN R4
sDATA CORRECT?
:BR IF YES
sDATA ERROR
:SW09=0
sINCREMENT PATTERN
sNEXT ADDRESS
sLAST ADDRESS DONE?
;BR IF NO

CZDMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-38

e 77

DMC11 SCRATCH PAD TESTS

021640
021646
021652
021654
021656

021664
021670

012737
012700
005003
010302
042737

021672

050237
104414
060600

021676
021700
021702
021706
021710

061225
010005
116104
120504
001401

021714
021716

104401
005200

021674

021712

021720

021722
021726
o 021730

021654
000001

001220

000017

021672

6$:

104414

005203

BIS
ROMCLK

000005

7%:

;:NEW SCOP1
;RESTART PATTERN AT 1
;RESTART AT ADDRESS ZERO
;PUT ADDRESS IN R2
;CLEAR ADDRESS FIELD OF INSTRUCTION

R2,6%

;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV SP TO BR

ROMCLK

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

;MOV BR TO PORTS
;PUT "EXPECTED” IN RS
;PUT “FOUND” IN R4
;DATA CORRECT?
;BR IF YES

;SW09=1?
;sINCREMENT PATTERN

RO,.RS
S(R1).R4
RS.R4

EMT

SCOP1
INC
INC

000020

#54,L0CK
#1,.RO
R3
R3,.R2
217,64

60600
61225
MOV
MOVB
CMPB
BEQ

104007

022703
001352
104400

Ss:

MOV
MOV
CLR
MOV
BIC

cMP
BNE
SCOPE

#20,.R3
5%

;SP ADDRESSING ERROR

;sNEXT ADDRESS

;LAST ADDRESS DONE?
;BR IF NO
;SCOPE THIS TEST

jha8s
bbbttt
bbbdb
tisbbhiiiiss

TEST

ssbsssbkddbbbbsdsbbdbidddss

;#INTERRUPT TEST
;#TEST THAT DEVICE CAN INTERRUPT TO VECTOR A

;

TEST S4

T TTTTTTTITTTryTYYYTMY

' ..............

021732
021740

012737
012737

021746

000005

021750
021752

005011
004537

000054
022026

021764
021772
022000

012737
012761
104414

000340
000200

022004

005037

177776

022002

022010

022012
022014
022016
022020
o 022024

121111

000240

104010
000403
104011
012706
104400

MOV
MOV

CLR
JSR

034642

022020
022016

340

TSTS4:

RESET

021756
021760

021762

001226
001216

340

001200

38
24

177776
000004

1$:

.BYTE

(R1)
RS,SETVEC

340,340

MOV
MOV
ROMCLK

#340,PS
9200,4(R1)

CLR

EMT
BR
EMT
MOV
SCOPE

10
43
11
#STACK ,SP

121111
NOP

2%:
3%:
4%

#54,TSTNO
#TSTSS ,NEXT

sR1 CONTAINS BASE DMC11 ADDRESS
;:BUS RESET

;CLEAR RUN
:SET UP VECTORS
$ XX0
i XX4

sLEVEL 7

sPS = LEVEL 7
;WRITE PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

:SET BR RQ IN IBUS+ REG 11
;ALLOW INTERRUPT

sNO INTERRUPT
;WRONG VECTOR
sRESET STACK
;SCOPE THIS TEST

;88 dsss b sistsdtisdatsdsssds TEST 55 sstssisssssssdsstssditdstns

:*INTERRUPT TEST
s#TEST THAT DEVICE CAN INTERRUPT TO VECTOR B

$i808000 0000880000000
AR00000 004000004400 00000000004004040

‘

CZOMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-39

DMC11 INTERRUPT TESTS

022026
022034

012737
012737

022042
022044

104412
004537

022050
022052

022110
022112

022056
022064
022072
022074
022076
022102
022104
022106
022110
022112
o 022116

012737
012761
104414
121111
005037
000240
104010
000403
104011
012706
104400

022054

340

000055
022120

001226
001216

TST55:

034642

340

000340
000300

TEST S5

#55,TSTNO
#TST56 ,NEXT

MSTCLR
JSR

RS,SETVEC

.BYTE

340,340

24
38

177776
000004

1%:

177776

24:
3%:
4s:

001200

MOV
MOV

MOV
MOV
ROMCLK
121111
CLR
NOP
EMT
BR
EMT
MOV
SCOPE

#340,PS
#300,4(R1)
PS

10
44
11
#STACK,SP

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
:SET UP VECTORS
: XX0
: XX4

sLEVEL 7

:PS = LEVEL 7
:WRITE PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:SET BR RQ IN IBUS* REG 11
sALLOW INTERRUPT
;
iNO INTERRUPT

;WRONG VECTOR
sRESET STACK
:SCOPE THIS TEST

;24bdddbssbsts
bt dbtbdddiddss

TEST

sassssssssstsssssdsssssssss

ssPRIORITY INTERRUPT TESTS
+#SET PS TO ALL BR LEVELS EQUAL OR GREATER THAN
s#THE DMC11 LEVEL,VERIFY THAT DMC11i DOES NOT INTERRUPT

022120

012737

022134
022136
022142
022146
022152
022154
022156
022160
022162

104412
012702
010237
013700
006200
006200
006200
006200
042700

022126

022166
022172
022174

022176

022200
022206
022210
022212
022216
022220
022222
022224
022230
022232

012737

004537
022234
022234

340

012761
104414
121111
010237
000240
020002
001403
162702
000770
104400

000056

022240

001226

001216

TSTS6:

177437

034642

340

177776

TEST S6

T Tl

MOV

MOV
MSTCLR
MOV
MOV
MOV
ASR
ASR
ASR
ASR
8IC

000340
177776
001366

000200

;

000004

4$:

Sé:

000040
18:

L L

rryryyrrrrrrrw

#56, TSTNO

#TSTS7,NEXT

JSR

#340,R2
R2,.PS
STAT1,.RO
RO
RO
RO
RO
#177437,R0
RS,SETVEC

.BYTE

340,340

24
24

MOV
#200,4(R1)
ROMCLK
121111
MOV
- R2,PS
NOP
cHe
RO,R2
BEQ
14
SUB
#40,R2
BR
5S¢
SCOPE

sR1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sPUT LEVEL 7 IN R2
+SET PRIORITY TO 7
1GET BR LEVEL OF DMC11
$+SHIFT RO 4 TIMES
:TO GET PROPER LEVEL
sCLEAR UNWANTED BITS

$SET UP VECTORS
sA VECTOR
;8 VECTOR

1PRIORITY 7

sLOAD PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sSET BR REQUEST
sPUT LEVEL IN R2 IN PS

sIS PRESENT PS LEVEL = TO DMC LEVEL
sBR IF YES
sNO GET NEXT LOWER LEVEL IN R2
sAND CONTINUE WITH TEST
;SCOPE TMIS TEST

SEQ 79

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-40
czomMC
OMCL1 INTERRUPT TESTS

022234
022236

104020
000002

28:

EMT

RTI

;ERROR UNEXPECTED INTERRUPT

8845884800800 0000000800244¢

TEST

sstissssssssssdttsttsssdtss

;¢PRIORITY INTERRUPT TESTS
s#SET PS TO ALL BR LEVELS LESS THAN THE DMC11 LEVEL

ssVERIFY THAT THE DMC11 WILL INTERRUPT

5:8888888448888885508588
004000000
808888
0 0000000000
804000
0 00044

TEST 57

;

022240
022246

012737
012737

022254

104412
012702
010237
013700
006200
006200
006200
006200
042700
010002
162702
004537
022366

022256
022262
022266
0z2272
022274
022276
022300
022302
022306
022310
022314
022320
022322
022324
022326
022334
022336
022340
022344
022346
022350
022354
022356
022362
022364
022366
022372
022374
022376
022402

022374
340
012761
104414

121111
010237
000240
104010
022702
001403
162702
000761
104400
012716
000002
104011
012716
000002

000057
022404

001226
001216

TST57:

#57,TSTNO

#7ST60,NEXT

000340
177776
001366

9340,R2
R2,PS

STAT1,RO

RO
RO
RO
RO
#177437,R0

177437
000040
034642

340
000200

000004

4s:

177776

S$:

000140

6%:

000040
1$:
2%:

022350

3s:

022350

BIC
RO,R2
MOV
suB
#40,R2
R5,5ETVEC
JSR
2%
3s
.BYTE
340,340
#200,4(R1)
MoV
ROMCLK 121111
R2,PS
MOV
NOP
EMT
10
#140,R2
cHP
EEQ
14
940, ,R2
SuB
43
BR
SCOPE
MOV
#63,(SP)

RTI

EMT
MOV
RTI

11
963 ,(SP)

:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
:PUT LEVEL 7 IN R2
:SET PRIORITY TO 7
;GET BR LEVEL OF DMC11
sSHIFT RO 4 TIMES
:TO GET PROPER LEVEL

sCLEAR UNWANTED BITS
sPUT DMC LEVEL IN R2
:GET NEXT LOMWER LEVEL IN R2
sSET UP VECTORS
sA VECTOR
;8 VECTOR
sPRIORITY 7
;LOAD PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:SET BR REQUEST
sPUT LEVEL IN R2 IN PS
;ERROR, NO INTERRUPT
:IS IT DOWN TO LEVEL 3 YET?
s YES,DMC DID NOT INTERUPT, ERROR
;PUT NEXT LOWER LEVEL IN R2
sCONTINUE TEST
:SCOPE THIS TEST
sSET UP FOR RTI
sERROR, WRONG VECTOR
sSET UP FOR RTI

25k bbb bdindbtbittsbtiis

TEST

ssstdsbssbdbbbbbbbbsbbdttis

saNPR TEST
;#TEST OF DATO, 1 WORD FROM UPROC TO 11 MEMORY

R
P
P
T P Y YT Y I T

TEST 60

:
ol

022404
022412

012737
012737

000060
022510

001226
001216

TST60:

evedanasrns

MOV
MOV

#60, TSTNO
#75T61 ,NEXT

CZOMC
MACRO v04.00
OMC11 NPR TESTS
022420
022422
022424
022430

022434
022436
022440
022442
022444
022450
022456

022460
022462

022464
022470
022474
022476
022500

022502
022504
022506

000005
005011
005061
004537
000000

RESET
CLR
CLR
JSR

034664

0
-1
3s
2%

177777

022506
022504
005037
012761
104414
121110
000240
012705
013704
020504
001401
104012
104400
000000
000000

SEQ 80

27-JUN-85 13:16:37 PAGE 27-41

022504
000021

CLR
MOV
ROMCLK
121110
NOP
MOV
MOV

000004

177777
022504

4s:
2%:

3s:

cMP
BEQ
EMT
SCOPE
0
0

(R1)

4(R1)
R5,NPRSET

;:R1 CONTAINS BASE DMC11 ADDRESS
:BUS RESET
;:CLEAR RUN

;CLR PORT4
:SET UP IBUS REG 0-7

:IN DATA
;0UT DATA
:IN BA
;0UT BA

#21,4(R1)

;:CLEAR 23

;WRITE PORT4

;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304

:SET NPR BITS IN IBUS+ REG 11
#-1,RS
2% .R4
RS.R4
43
12

;PUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
;DATA CORRECT?
:BR IF YES
;ERROR NPR FAILED

;SCOPE THIS TEST
;0UT BA
:IN BA

jhbddbbbttsbdbbitbititdstsss

;"’R TEST

012737
012737

022524
022526
022532
022536
022540
022542
022544
022546
022554
022562
022564
022566
022570
022574
022576
022600
022602
022604
022610
022612

104412
005061
004537
000000

022614

022616
022620

177777
022622
022620
012737
012761
104414
121110
000240
012705
104414
021004
104414
021025
016104
020504
001401
104012
104400
000000

000061
022624

001226
001216

TSTé1:

1 WORD FROM 11 MEMORY TO UPROC
2400800040850 0000k td bt tbtt bt bbbt

177777
000001

022622

000004

TEST 61

MOV
MOV

#61,TSTNO
#TST62 ,NEXT
4(R1)
RS ,NPRSET

9-1,38
#1,4(R1)

kgéilo

177777

MOV
ROMCLK
021004

ROMCLK
021025
MOV
CMP

000004

BEQ

4s:
2%:

bbbt ibtdts

--------------

MSTCLR
CLR
JSR
0
-1
3
28
MOV
MOV
ROMCLK

000004
034664

stssbsssbtttssbdbbbbbtbdats

s4TEST OF DATI,

;
022516

$:08848884828080

‘

022510

TEST

EMT
SCOPE
0

;R1 CONTAINS BASE DMC11 ADDRESS

sMASTER CLEAR DMC11
;CLR PORT4
;:SET UP IBUS REG 0-7
;sIN DATA
;OUT DATA
:IN BA
;0UT BA
;PUT DATA IN 3
sWRITE PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

;SET NPR BITS IN IBUS= REG 11

#-1,RS

4(R1),R4
R5.R4
4%
12

;PUT “EXPECTED” IN RS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:MOVE IN DATA LOW BYTE TO PORT4

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE IN DATA HIGH BYTE TO PORTS
;PUT "FOUND” IN R4
;DATA CORRECT?

:BR IF YES

;ERROR NPR FAILED
sSCOPE THIS TEST
;0UT BA

CZOMC
MACRO V04.00
DMCI1 NPR TESTS
022622

SEQ 81

27-JUN-85 13:16:37 PAGE 27-82

000000

3#:

;IN BA

;88858485400 0000000d00dssss

{eNPR_TEST
;#TEST OF DATOB,
3288888848885

TEST

sttstsdtsbbbssbsssttbtdbsss

1 BYTE FROM UPROC TO 11 MEMORY

485050000

bkttt dkdb bbbt bbb bbb bbb b

bbb

bbbhit

TEST 62

;

i
Bica
AR

022624
022632

012737
012737

022640
022642
022646
022652
022654
022656
022660
022662
022666
022674
022676

104412
005061
004537
000000
177777
022724
022723
005037
012761
104414
121110

022702
022706
022712
022714
022716
022720
022722
022724

012705
013708
020504
001401
104012
104400
000000
000000

022700 000240

000062
022726

001226
001216

TST62:

MSTCLR
CLR
JSR
0
-4
38
2s.1
LR
MOV
ROMCLK
121110

000004
034664

022722
000221

MOV
MOV

000004

NOP

177400
022722

as:
20:
:

MOV
MOV
CHP
BEQ
e
SCOPE
0
0

962,TSTNO
#TST63.NEXT
4(R1)
RS,NPRSET

:0UT BA
28
8221,4(R1)

@177400.RS
23.R4
RS.R4
43
12

;R1 CONTAINS BASE DMC11 ADDRESS
;MASTER CLEAR DMC11
;CLR PORT4
;SET UP IBUS REG 0-7
;IN DATA
;0UT DATA
;IN BA

;:CLEAR 2%
;WRITE PORT4
:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:SET NPR BITS IN IBUS# REG 11

;PUT "EXPECTED” IN RS
;PUT "FOUND” IN R4
;DATA CORRECT?
:BR IF YES
;ERROR NPR FAILED
;SCOPE THIS TEST
;0UT BA
;IN BA

itbsbsds bbbt itbbbsdtds

TEST

sssssbstdsdbhtnsbbbsbbbsdss

s4TEST OF EA BITS 16 AND 17
:#D0 A DATO TO AN ADDRESS USING OUT BA BITS 16 AND 17
s#VERIFY CORRECT RESULTS

(i8558 080000000k b k0t bt kbbb bbbbbbbb kbbbt bbb bbb bhbhbhbi i

TEST 63

:
’

022726
022738

012737
012737

022742
022744
022752

104412
013737
013737

022764
022766
022770
022772
022778
023002
023004

000000
125252
000000
000000
012761
104414
121111

022760

004537

000063
023068

001412
001412

038664

000014

001226
001216

TST63:

000004

..............

MOV
MOV

MSTCLR
MOV
MOV

022772
022770

JSR

20
1¥:

bh ke

0
125252
9
0
MOV
ROMCLK
121111

963,TSTND
oTSTed,NEXT

DHPOS,1
DMPO4,2s

RS,NPRSET

#18,4(R1)

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;USE SEL4 FOR ADDRESS
sUSE SEL4 FOR ADDRESS
;LOAD BA AND DATA
;IN DATA
;0UT DATA
:IN BA
;0UT BA
;LOAD SEL 4 WITH OUT BA16 AND 17
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sSET OUTBA 16 AND 17

CZDMC
MACRO V04.00
DMC11 NPR TESTS

023006
023014
023022
023026
023032
023034
023040
023042
023044
023046
023050
023054
023056
023060
023062

012761
012761
012711
052711
000240
012705
104414
021044
104414
021065
016104
020504
001401
104012
104400

SEQ 82

27-JUN-85 13:16:37 PAGE 27-43

000021
121110
003000
000400

000004
000006

121110

000004

3s:

MOV
MOV
MOV
BIS
NOP
MOV
ROMCLK
021044
ROMCLX
021065
MOV
CMP
BEQ
EMT
SCOPE

#21,4(R1)
;LOAD SEL4
£121110,6(R1)
;PUT INSTRUCTION IN SEL6
#BIT9!BIT10,(R1);SET CROMI AND CROMO!!
#8178,.(R1)
;CLOCK IT!
;WAIT FOR NPR
#121110,R5
;PUT “EXPECTED” IN RS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE OUT DATA LB TO SEL4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE OUT DATA HB TO SELS
4(R1),R4
;PUT “FOUND" IN R4
R5,.R4
;CORRECT RESULTS ?
38
;:BR IF YES
12
;ERROR BA 16 AND 17 FAILED
;SCOPE THIS TEST

idddbdbbbbibddtbbbbdhbhidits

TEST

sssbbhbbhbbhkihkhsbhbbbbhbhbiss

;#TEST OF EA BITS 16 AND 17
;#D0 A DATI USING IN BA BITS 16 AND 17
;#VERIFY CORRECT RESULTS

023064
023072

012737
012737

023100
023102
023110
023116
023122
023124
023126
023130
023132
023140
023146

104412
013737
013737
004537
000000
125252
000000
000000
012761
012761
012711

023152
023156
023160
023164
023166
023170
023172
023174
023200
023202
023204
023206

052711
000240
012705
104414
021004
104414
021025
016104
020504
001401
104012
104400

000064
023210

001412
001412
034664

000015
121110
003000
000400

001226
001216

TST64:

023130
023126

000004
000006

2%:
1¢:

121110

000004

3s:

;

TEST 64

T T

T TTTTTITTT T

yryews

MOV
MOV :

#64,TSTNO
#TST65,NEXT

BIS
NOP
MOV
ROMCLK
021004
ROMCLK
021025
MOV
cHP
BEQ
EMT
SCOPE

:R1 CONTAINS BASE DMC11 ADDRESS
;sMASTER CLEAR DMC11
DMP0O4,1¢
;USE SEL4 FOR ADDRESS
DMP04,24
;USE SEL4 FOR ADDRESS
RS ,NPRSET
;LOAD BA AND DATA
sIN DATA
;0UT DATA
;IN BA
;0UT BA
#15,4(R1)
;LOAD SEL4
#121110,6(R1)
sPUT INSTRUCTION IN SEL6
#BIT9!BIT10,(R1);SET CROMI AND CROMO!!
#BIT8,(R1)
sCLOCK IT!
;WAIT FOR NPR
#121110.R5
;PUT “EXPECTED” IN RS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE IN DATA LB TO SEL4
;sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE IN DATA HB TO SELS
4(R1).R4
;PUT “FOUND” IN R4
R5.R4
;CORRECT RESULTS ?
3s
;BR IF YES
12
sERROR BA 16 AND 17 FAILED
;SCOPE THIS TEST

;
MSTCLR
MOV
MOV
JSR
0
125252
0
0
MOV
MOV
MOV

shkhkbbbsbbhtbtstbsiisibdhtsr

TEST

skkbshbbhtddbkbshhdbdsbhiiss

:#NPR NON-EXISTENT MEMORY TEST
;D0 A DATO TO A NON-EXISTENT ADDRESS
;#VERIFY THAT THE NON-EXISTENT BIT SET IN IBUS REG 11

CZOMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-44

OMC11 NPR TESTS

012737

023216

012737

023224
023226
023232
023234
023236
023240
023242
023250
023252
023254

104412
004537
000000
000000
177320
177320
012761
104414
121111
012761

023262
023264
023266
023270
023272
023274
023300

023304
023310
023312
023314

P 023316

104414
121110
000240
104414
121225
012705
116104

042704
020504
001401
104012

000065

023320

001226

001216

TST6S5:

000014

000004

000021

000004

ROMCLK
121110
NOP
ROMCLK
121225
MOV
MOVB

000001
000005
177776

104400

MOV

MOV
MSTCLR
JSR
0
0
177320
177320
MOV
ROMCLK
121111
MOV

034664

1s:

TS Tt

TEST 65

;
023210

BIC
CMP
BEQ
EMT
SCOPE

#65,TSTNO

#TST66 ,NEXT

R5,NPRSET

#14,4(R1)
#21,4(R1)

#1.RS
S(R1).R4
#177776,R4
R5.R4
1$
12

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;sLOAD IBUS REGISTERS 0-7
;IN DATA
;0UT DATA
;IN BA
;0UT BA
:SET OUT BA BITS 16+17 IN PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;SET OUTBA 16 AND 17
;SET NPR REQUEST BITS IN PORT4

;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV IBUS* 4 TO IBUS* 10
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOV IBUS#11 TO IBUS#5
;PUT “EXPECTED” IN RS
;PUT "FOUND” IN R4

;CLEAR UNMWANTED BITS
;:DATA CORRECT?
;BR IF YES
;ERROR NON-EXISTENT MEM BIT FAILED TO SET

:SCOPE THIS TEST

shbkdbbbbtbbdnbkbbhihihktbtttk

TEST

Rsridsrbsbbbbbdbbbbddbbhbtdk

;#NPR NON-EXISTENT MEMORY TEST
;#D0 A DATI FROM A NON-EXISTENT ADDRESS
:#VERIFY THAT THE NON-EXISTENT BIT SET IN IBUS REG 11

sihdkbbd
kbbbt hbbthbhkibhb
bddb
bk
bhbhbh
dbib
bbbk bk hhhdhkbhik
bb

TEST 66

;
‘

023320

012737

023326

012737

023334

104412

023336

004537

023346
023350
023352
023356
023360
023362
023370
023372
023374
023376

177320
177320
005061
104414
121111
012761
104414
121110
000240
104414

023342
023344

023400

000000
000000

121225

000066

023426

001226

001216

MOV

MOV
MSTCLR

034664

JSR

0
0

177320
177320

000004
000015

TST66:

..............

000004

CLR
ROMCLK
121111
MOV
ROMCLK
121110
NOP
ROMCLK
121225

#66, TSTNO

#TST67 ,NEXT

RS ,NPRSET

4(R1)
#15,4(R1)

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;LOAD IBUS REGISTERS 0-7
;IN DATA
;0UT DATA

;IN BA
;0UT BA

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;CLEAR NON-EXISTENT BIT
:SET NPR REQUEST BITS IN PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV IBUS* 4 TO IBUS* 10
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV IBUS#11 TO IBUS#S

—p—

CZDMC
MACRO vV04.00
DMC11 NPR TESTS
023402
023406
023412
023416
023420

023422
023424

012705
116104
042704
020504
001401
104012
104400

SEQ 84

27-JUN-85 13:16:37 PAGE 27-45

000001
000005
177776

MOV
MOVB

BIC

1%:

cHp
BEQ
EMT
SCOPE

#1.R5
S(R1),R4

;PUT “EXPECTED” IN RS
;PUT "FOUND” IN R4

R5,R4
1
12

;DATA CORRECT?
:BR IF YES
;ERROR NON-EXISTENT MEM BIT FAILED TO SET
:SCOPE THIS TEST

#177776,.R4

;CLEAR UNWANTED BITS

jhdbsbdbdsbhbbkhhbhitdhhbdbns

;#NPR TEST

TEST

sbdbdbbhhbbbhsbsbbbbbbbodds

;#USING DATO, NPR A BINARY COUNT (0-377 )

;#*FROM MICRO-PROCESSOR TO ALL

AVAILABLE MEMORY

L
P
PP
PP

TEST 67

;
f

023426
023434
023442

012737
012737
012737

023450

104412
005037
005000
012702

036566

010037
010237
032702

023514
023520
000001

023452
023456
023460
023464
023464

023470
023474
023500

023502

023506
023512
023514
023516
023520
023522
023524
023532,
023534
023536
023540
023542
023544
023546
023550
023552
023554
023556
023562
023566

023570
023572
023574
023576
023602
023604

001402
000337
004537
000000
000000
000000
000000
105012
012761
104414
121110
000240
010005
111204
120504
001401
104021
104401
005200
042700
005737
001402
005700
001412
005202
023702
001330
012702

000067
000003
023624

001226
001222
001216

T5767:

023622
1s:

023514
034664
2%:
4s:

000221

000004

g
A

MOV
MOV
MOV

MSTCLR
CLR
CLR
MOV

54
RO
#CORMAX
, R2

MOV
MOV
BIT
BEQ
SWAB
gSR

RO,.2$
R2,4%
#BITO0,R2
.46
24
RS,NPRSET

0
0
0

CLR8B

177400
023622

001304
036566

;LOAD DATA
;LOAD BA
;IS BA 0DD?
;BR IF NO
;IF ODD PUT DATA IN HI-BYTE
;LOAD NPR REGISTERS
:IN DATA
;0UT DATA
:IN BA
;0UT BA
;CLEAR MEMORY LOCATION
;LOAD PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;D0 THE NPR

#221.4(R1)

MOV
MOVB
CMPB
BEQ
EMT
SCOP1
INC
BIC

RO,RS
(R2),R4
RS.R4
3s
21

;PUT "EXPECTED” IN RS
sPUT “FOUND” IN R4
:IS DATA CORRECT?
:BR IF YES
sERROR, DATA INCORRECT

RO
#177400,R0

BEQ
ST
BEQ
INC
CMP
BNE

6%
RO
7%
R2
MEMLIM,R2
1

sNEXT CHARACTER
sUSE ONLY LOW BYTE
;HAS MAX MEMORY BEEN REACHED YET?
sBR IF NO
;DONE PATTERN?
;BR IF YES
sINC BA
;REACHED MEMORY LIMIT YET?
sBR IF NOT
sRESTART BA AT FIRST ADDRESS

18T

6$:

(R2)

;R1 CONTAINS BASE DMC11 ADDRESS
;MASTER CLEAR DMC11
:START FLAG AT 0
;DATA
;ADDRESS

MOV
ROMCLK
121110

NOP

3s:

#67, TSTNO
#3,ICOUNT
#TST70,NEXT

MOV

]

#CORMAX,R2

MACRO V04.00
CZOMC
DMC11 NPR TESTS

023610
023616
023620
023622

012737
000722
104400
000000

SEQ 85

27-JUN-85 13:16:37 PAGE 27-46

177777

HOV

023622
7%:

Ss:

#-1,5¢

BR 1%

SCOPE

:SET FLAG TO END TEST AT END OF DATA PATTERN
:CONTINUE

:SCOPE THIS TEST

;THIS LOCATION IS A FLAG,

IT STARTS AT O,

;AND IS SET TO -1 WHEN LAST MEMORY ADDRESS
;IS USED, TEST IS THEN ENDED WHEN PATTERN IS FINISHED

shtbsbbbbssbsbbittbstitistns

TEST

;sMAIN MEMORY TEST
;#FLOAT A 1

ssssstdsbsbbbnbtssbsstbobss

THROUGH ALL MAIN MEMORY LOCATIONS

L
P P PP TP
T PP

TEST 70

;s
023624
023632

012737
012737
012737

023646
023650
023652
023656

104412
005002
012700
042737
050237
104414
010000
010061
104414
122500
104414
040620
104414
061225
010005
116104
120504
001401
104013
104401
000241
106100
001347
005202
022702
001341
104400

023640

023664

023670
023672
023674
023700
023702
023704

023706
023710
023712
023714
023716
023722
023724
023726
023730
023732
023734
023736

023740

023742

023746
023750

000070
023752
023656

000001
000377
023672

001226
001216
001220

023672

7ST70:

1%:

65%:
66%:

000004

MOV
MOV
MOV

#70,TSTNO
#TST71 ,NEXT
654 ,L0CK

MSTCLR
CLR
MOV
BIC

67$:

#377,66%

BIS
ROMCLK
010000
MOV
ROMCLK

122500
ROMCLK
040620
ROMCLK
61225
MoV
MOVB
CcMPB

000005

R2
#1,RO

BEQ
EMT

SCoP1
CLC
ROLB

R2,66%

RO,4(R1)

- 67¢
13

BNE
INC
CHP
BNE
SCOPE

000400

RO,RS
S(R1),R4
R5,R4

654
R2
#400,R2
1s

:R1 CONTAINS BASE DMC11 ADDRESS

;MASTER CLEAR DMC11
sSTART WITH ADDRESS 0
:START WITH BIT 0

;CLEAR ADDRESS FIELD OF INSTRUCTION

;ADD ADDRESS TO INSTRUCTION
:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR WITH ADDRESS IN R2
;WRITE PATTERN IN PORT4
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304

;MOVE PORT4 TO MEMORY
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE MEMORY TO BR
sNEXT WORD IS INSTRUCTION, .OMCLK PC=5304
sMOVE BR TO PORTS
;PUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
;DATA CORRECT?
:BR IF YES
;:DATA ERROR

:SW09=17?
;CLEAR CARRY
sSHIFT BIT IN RO
:DONE IF RO=0
;NEXT ADDRESS
;LAST ADDRESS
;BR IF NO
sSCOPE THIS TEST

jhtddidbtbitbhbbdtstbbbbtiss

TEST

saksbdddddbbdbdbbtbbdbdbsddn

:*MAIN MEMORY TEST
+#FLOAT A O THROUGH ALL MAIN MEMORY LOCATIONS

T T
Yy Y Y
Y YTy IT

y . TERF 7%
Ro

023752
023760

012737
012737

000071
024104

001226
001216
et

TST71:

MOV
MOV

mia b

#71,7TSTNO
#TST72 ,NEXT

CZDMC
MACRO V04.C0
27-JUN-85 13:16:37 PAGE 27-47
DMC11 MAIN MEMORY TESTS

023766

012737

023774
023776
024000
024004
024006
024014
024020
024022
024024
024030
024032
024034
024036
024040
024042
024044
024046
024052
024054
024056
024060
024062
024064
024066
024070
024072

104412
005002
012700
005100
042737
050237

000377
024022

010000
010061

000004

024074
024100
024102

104414

104414
122500
104414
040620
104414
061225
010005
116104
120504
001401
104013
104401
005100
000241
106100
001345
005202
022702
001337
104400

024006

001220

000001

MOV

18:

024022

6454:
65%:
665:

MSTCLR
CLR
MOV
CoM
BIC
BIS
ROMCLK
010000
MOV
ROMCLK
122500
ROMCLK
040620
ROMCLK
61225

000005

#65%,L0CK

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;START WITH ADDRESS 0
;START WITH BIT O
;CHANGE TO FLOATING 0
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR WITH ADDRESS IN R2
;WRITE PATTERN IN PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE PORT4 TO MEMORY
:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE MEMORY TO BR
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE BR TO PORTS
;PUT "EXPECTED” IN RS

#1.RO
RO
#377,66%
R2,66%

RO,4(R1)

RO,RS

S(R1),.R4
RS,R4
67%

:PUT “FOUND” IN R4

;DATA CORRECT?
:BR IF YES
:DATA ERROR
:SW09=17?
;CHANGE TO FLOATING 1
;CLEAR CARRY
sSHIFT BIT IN RO
:DONE IF RO=0
;NEXT ADDRESS
;LAST ADDRESS
:BR IF NO
:SCOPE THIS TEST

67%:

000400

SCOPE

RO
644
R2
#400,R2
1s

jhtdbbssbisibbibbbbhbbbbbssss

TEST

ssssssssssidsdssssdsdnnisss

;#MAIN MEMORY DUAL ADDRESSING TEST
+#LOAD EACH MEMORY LOCATION WITH ITS OWN ADDRESS
;#READ BACK EACH LOCATION TO VERIFY CORRECT ADDRESSING

LRI

:
024104
024112
024120

012737
012737
012737

024126
024130
024132
024140
024144
024146
024150
024154

104412
005002
042737
050237
104414
0100C0
010261
104414
122500
104414
040620
104414

024156
024160

024162
024164

000072
024304
024132

001226
001216
001220

157172

000377
024146

024146

1$:

000004

T Ry

YT T T

T TITrrTrYTTMTY

TEST 72
972, TSTNO

9TST73,NEXT

#18,L0CK

2$:

R2
#377,2%

R2,2%

R2,4(R1)

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
+START AT ADDRESS 0
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE PORT4 TO MEMORY
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE MEMORY TO THE BR
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

SEQ 87

CZDMC
MACRO v04.900
27-JUN-85 13:16:37 PAGE 27-48
DMC11 MAIN MEMORY TESTS

024246
024250
024252
024254
024256

061225
010205
116104
120504
001401
104013
104401
005202
022702
001346
012737
005002
042737
050237
104414
010000
104414
040620
104414
061225
010205
116104

024274
024300
024302

001401
104013
104401
005202
022702
001352
104400

024166
024170

024172
024176
024200
024202
024204
024206
024210
024214
024216
024224
024226
024234

024240

024242

024244

024262
024264
024266
024270
024272

120504

61225
MOV
MOVB

CHMPB

3s:
000400

024226

001220

000377
024242

024242

4%:

Ss:

000005

6%:

000400

BEQ
EMT

SCOP1
INC
CcMP
BNE
MOV
CLR
BIC
8IS

R2,R5
S(R1).R4
R5.R4
13

;:SW09=17?

ROMCLK
010000
ROMCLK
040620
ROMCLK

61225
MOV
MOVB
CMPB
BEQ
EMT
SCOP1
INC
CMP
BNE
SCOPE

;MOV BR TO PORTS
;PUT "EXPECTED” IN RS
;PUT "FOUND” IN R4
;:DATA CORRECT?
;BR IF YES
;:DATA ERROR

R2,R5

S(R1),R4
R5,R4
6%
13
R2
#400,R2
4%

;NEXT ADDRESS
;LAST ADDRESS
;BR IF NO
;NEW SCOPE 1
;RESTART AT ADDRESS 0
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD THE MAR
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE MEMORY TO THE BR
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOV BR TO PORTS
;PUT "EXPECTED” IN RS
;PUT “FOUND” IN R4
;DATA CORRECT?
:BR IF YES
;ADDRESSING ERROR
:SW09=1?
;:NEXT ADDRESS
;IS IT THE LAST
.

;BR IF NO

;SCOPE THIS TEST

shkbbbbdbdbbbbbbbbbtthbtbddht

;#MAR TEST

TEST

sddsddddbddshbbsbbshsdbddds

;#PERFORM DUAL ADDRESSING TEST
:#USING MAR AUTO-INC FEATURE

jidkddbbdktdbbhbbbb kbbbt bdhiib

024304
024312

012737
012737

024320
024322
024324
024326
024330
024336
024340
024342
024344
024350
024352
024354
024356
024362

104412
005002
104414
010000
032737
001402
104414
004000
010261
104414
136500
005202
022702
001370

000073
024440

001226
001216

TST73:

000004

000400

001366

#BIT15,STATL
.+6

1s:

ki bbbk

#73,TSTNO
2TST74 ,NEXT

100000

bbb bbbk nbhbkhdhhbdihb

R2,4(R1)
R2
#400,R2
1s

:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
:START WITH A ZERO
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;:DMC?
:BR IF YES
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMAR HI _ O (KMC ONLY)
sWRITE DATA TO PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MEM AUTO-INC MAR
;INCREMENT DATA
;DONE YET?
;BR IF NO

CZOMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-49

€0 8 8

DMC11 MAIN MEMORY TESTS

024364
024366
024370
024372
024400
024402
024404
024406
024406
024410
024412
024414
024420
024422

024424

024426

024430
024434

72 024436

005002
104414
010000
032737

001402
104414

100000

001366

004000

005202

022702
001364

000004

3s:

000400

104400

4000

;RESTART WITH A ZERO
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
:DMC?
:BR IF YES
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MAR HI _ 0 (KMC ONLY)

ROMCLK

:NEXT WORD IS INSTRUCTION,

BEQ
ROMCLK

2%:

104414

055224
010205
016104
120504
001401
104014

CLR
ROMCLK
010000
BIT

#BIT15,STAT1
.+6

055224
MOV
MOV
CMPB
BEQ
EMT

R2,RS5
4(R1),.R4
R5,R4
3

;:MOVE MEM TO PORT4
;PUT “EXPECTED” IN RS
;PUT "FOUND” IN R4
;:DATA CORRECT?
:BR IF YES
:MAR ERROR

cMpP
BNE

#400,R2
2%

;:DONE YET?
;BR IF NO

INC

SCOPE

ROMCLK PC=5304

:NEXT ADDRESS

:SCOPE THIS TEST

ihdbkkbhbbhkhbbhbhhdhkbhdbhik

TEST

sashdbddbdhbbbbbbbbsbbbsdtd

s#ALU C BIT TEST
:*TEST THAT AN ADD OF 377 AND 377 WILL SET THE C BIT

LRSI

;

TEST 74

‘

024440
024446
024454

012737
012737
012737

024462
024464
024470
024472
024476

104412
004737
024542
004737
024542

024500
024500

024502
024504
024506
024510

024512
024514
024516
024520
024524
024530
024532
024534
024536
024540
024542

024545
024550

104414
010000
104414
054400
104414
040421
104414
061224
012705
016104
120504
001401
104015
104401
104400
377
000
000

000074
024552
024500

001226
001216
001220

TST74:

034726
034762

1%:

000001
000004

2%:
000

000
000

000

TDATA:

.EVEN

e Ty
Y TP T T T T T TITrTryrTYY

--------------

MOV
MOV
MOV
MSTCLR
JSR
TDATA
JSR
TDATA

474, TSTNO
9TST75,NEXT
#1$,L0CK

:R1 CONTAINS BASE DMC11 ADDRESS

PC,MEMLD
PC,SPLD

sMASTER CLEAR DMC11
;LOAD MAINMEM DATA
;:POINTER TO DATA
sLOAD SP DATA
;POINTER TO DATA

ROMCLK
sNEXT WORD IS INSTRUCTION,
010000
;MAR_O
ROMCLK
sNEXT WORD IS INSTRUCTION,
054400¢<0420>
:ADD 377 AND 377, TO SET C
ROMCLK
sNEXT WORD IS INSTRUCTION,
040401 :<1220>
sADD O AND O AND THE C BIT
ROMCLK
sNEXT WORD IS INSTRUCTION,
61224
sPUT RESULTS IN PORT4
MOV
#1,RS
:PUT "EXPECTED” IN RS
MOV
4(R1),R4
;PUT “FOUND” IN R4
CHMPB
R5,R4
;DATA CORRECT?
8EQ
23
+BR IF YES
EMT
15
sERROR C BIT NOT SET
SCOP1
;SW09=1?
SCOPE
sSCOPE THIS TEST
.BYTE
-1,0,0,0,0,0,0,0

ROMCLK PC=5304
ROMCLK PC=5304
BIT
ROMCLK PC=5304
ROMCLK PC=5304

P—_————

CZDMC
MACRO V04.00
DMC11 ALU TESTS

SEQ 89

27-JUN-85 13:16:37 PAGE 27-50

73
shsksbsbibbddbbidbbidkbtdtds

TEST

ssssdsdtsbbbbddbbbbbsbbsnisd

;#ALU TEST
;#TEST OF ALU FUNCTION SEL B WITH C BIT CLEARED
;#ALU FUNCTION (B)
CODE=11
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
s#PERFORM THE FUNCTION, VERIFY THE RESULTS

024552
024560
024566

012737
012737
012737

024574
024576
024600
024604
024610
024612
024616
024620
024624
024632
024636

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
104414
040620
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400
000
377
125

024640

024642

024650
024654
024656
024660
024662
024664
024666
024672
024674
024676
024700
024702
024704
024706
024712
024714
024716
024721

024724

000075
024726
024620

001226
001216
001220

TST75:

HEE

;

TEST 75

LR 2t 2

MOV
MOV
MOV
MSTCLR

CLR
MOV
JSR
MEMDAT
JSR

024716
034726
034762

035026
000017
024640
000017
024656

024640

024656

1s:

28:

3s:

000004

000010

377
125
252

#75,TSTNO
#TST76 ,NEXT
#1$,L0CK

RO
#58,R2
PC,MEMLD
PC,SPLD

SPDAT
JSR
BIC
BIS
ROMCLK
010000
BIC
BIS

817,38
RO,3$

MOVB

4(R1),.R4

PC.CLRC
#17,2%
RO,28

ROMCLK
040400!<11420>
ROMCLK
61224
MOVB
(R2).RS

CMPB
BEQ
EMT
SCoP1
INC
INC
CHP
BNE
SCOPE
.BYTE

RS.R4
43
15

Y Y

TSI

LT TrIITIIIT Y

;R1 CONTAINS BASE DMC11 ADDRESS

;MASTER CLEAR DMC11

;:MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP

;POINTER TO DATA
;CLEAR C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:LOAD MAR
;:CLEAR ADDRESS OF INSTRUCTION
sADD ADDRESS TGO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;BR _ SEL B
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4
;PUT “EXPECTED" IN RS

;PUT “FOUND” IN R4

;DATA CORRECT?
:BR IF YES
;ALU ERROR
;SW09=1?
R2
;NEXT DATA
RO
:NEXT ADDRESS
#10,R0
;DONE YET?
1s
sBR IF NO
:SCOPE THIS TEST
0,-1,0,-1,125,252,125,252

74
shbddsbidtdhdbbsdhbdssdsstss

TEST

sssststsddssdsdbsisissddstis

:#ALU TEST
;#TEST OF ALU FUNCTION SEL A WITH C BIT CLEARED
s#ALU FUNCTION (A)
CODE=10
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
ssPERFORM THE FUNCTION, VERIFY THE RESULTS

CZDMC
MACRO V04.00
DMC11 ALV TESTS

024726
024734
024742

012737
012737
012737

024750
024752

104412
005000

024754
024760

000076
025102
024774

012702
004737

025072
034726

024766
024772
024774
025000
025006
025012
025014
025016
025024
025030
025032
025034
025036
025040
025042
025046
025050
025052
025054
025056
025060
025062
025066
025070

004737
035062
004737
042737
050037
104414
010000
042737
050037
104414
040600
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400

034762

025075

024764

025072

025100

035052

000
252

SEQ 90

27-JUN-85 13:16:37 PAGE 27-51

035026
000017
025014
000017
025032

001226
001216
001220

15776:

025014

025032

15:

2%:

000004

4%:

000010

125
252

rrr

MOV
MOV
MOV

MSTCLR
CLR
MOV
JSR
MEMDAT

34:

000

377
125

S5¢:

R Ty Y

T Tttt Ty

e m-—--

976, TSTNO
#TST77 ,NEXT
#1$,L0CK

;R1 CONTAINS BASE DMC11 ADDRESS

sMASTER CLEAR DMC11
sMEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA

RO
#54,R2
PC,MEMLD

JSR
SPDAT

PC,SPLD

BIC

217,2%

JSR

PC,CLRC

BIS
ROMCLK
010000

RO,2¢

BIC

217,34

MOVB
CMPB
BEQ
EMT
SCoP1
INC
INC
CMP
BNE
SCOPE

4(R1).R4
RS.R4
44
15

BIS
RO,3¢
ROMCLK
040400!<10420>
ROMCLK
61224
MOVB
(R2) .R5

R2
RO
#10,R0
1s

;LOAD 8 WORDS OF SP
;POINTER TO DATA

;:CLEAR C BIT!

;CLEAR ADDRESS FIELD OF INSTRUCTION

;ADD ADDRESS TO INSTRUCTION
¢NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:LOAD MAR
3CLEAR ADDRESS OF INSTRUCTION

sADD ADDRESS TO INSTRUCTION
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
tBR _ SEL A
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE BR TO PORT4
;PUT "EXPECTED” IN RS

;PUT “FOUND” IN R4
;DATA CORRECT?
:BR IF YES
;ALU ERROR
iSH09=1?
sNEXT DATA
sNEXT ADDRESS
;:DONE YET?
s8R IF NO
;SCOPE THIS TEST

.EVEN

;68880 asbbbitbisttsidsssssts

TEST

sssssssssssssssstsssidssssss

ssALU TEST
;#TEST OF ALU FUNCTION A OR NOTB MITH C BIT CLEARED
s#ALU FUNCTION (A OR NOTB)
CODE=12
+sLOAD MAIN MEM AND SP WITH 8 WORDS OF DATA

s#PERFORM THE FUNCTION, VERIFY THE RESULTS

§I88884054000408400800088050040000408448008408000000040800080048

:
025102
025110
025116

012737
012737
012737

000077
025256
025150

001226
001216
001220

1ST177:

MOV
MOV

MOV

TEST 77

977, TSTNO
#TST100, NEXT

@14,L0CK

sR1 CONTAINS BASE DMC11 ADDRESS

CZDMC
MACRO V04.00
DMC11 ALU TESTS

025124
025126
025130
025134
025140
025142
025146
025150
025154
025162
025166
025170
025172
025200

025204
025206
025210
025212
025214
025216
025222
025224
025226
025230
025232
025234
025236
025242
025244
025251

025254

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037

104414
040640
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400
377

252

SEQ 91

27-JUN-85 13:16:37 PAGE 27-52

025246
034726
034762
035026
000017
025170
000017
025206

025170

025206

1%:

2%:

3%:

000004

4s:
000010

377

MSTCLR
CLR
RO
MOV
#5%,.R2
JSR
PC ,MEMLD
MEMDAT
JSR
PC,SPLD
SPDAT
JSR
PC.CLRC
BIC
#17,2¢
BIS
RO,2$
ROMCLK
010000
BIC
17,3
BIS
RO,3$
ROMCLK
040400!<12+20>
ROMCLK
61224
MOVB
(R2),R5
MOVB
4(R1).R4
CMPB
R5,.R4
BEQ
4%
EMT
15
SCoP1
INC
R2
INC
RO
cHpP
#10,R0
BNE
1
SCOPE

sMASTER CLEAR DMC11
;MEM + SP ADDRESS
;POINTER TO CORRECT DATA
:LOAD 8 WORDS OF MAIN MEMORY
;:POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
;CLEAR C BIT!
sCLEAR ADDRESS FIELD OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:LOAD MAR
;:CLEAR ADDRESS OF INSTRUCTION
:ADD ADDRESS TO INSTRUCTION
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;BR _ A OR NOTB
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE BR TO PORT4
iPUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
sDATA CORRECT?
:BR IF YES
sALU ERROR
:1SH09=17
sNEXT DATA
sNEXT ADDRESS
:DONE YET?
:BR IF NO
:SCOPE THIS TEST

125
.EVEN

(688248888008 00000000080004

TEST

100

s2sssssdsdsddsdsdsssssdsnts

s¢ALU TEST
:~TEST OF ALU FUNCTION A AND B WITH C BIT CLEARED
38ALU FUNCTION (A AND B)
CODE=13

ssLOAD MAIN MEM AND SP WITH 8 WORDS OF DATA

ssPERFORM THE FUNCTION, VERIFY THE RESULTS

$:908808888845888848845484844880488888820884000884840808808880000004

TEST 100

' ..............

1
i

025256
025264

012737
012737

025300

104412

025272
025302

025304
025310
025314
025316
025322
025324

012737
005000

012702
004737
035052
004737
035062
004737

000100
025432
025324

001226
001216
001220

TST100: MOV
MoV
MOV

MSTCLR
CLR

025422
034726
034762
035026

18:

€100,TSTNO
STST101, NEXT
#14,L0CK

MOV
#58,R2
JSR
PC,.MEMLD
MEMDAT
JSR
PC.SPLD
SPDAT
JSR
PC,.CLRC

sR1 CONTAINS BASE DMC11 ADDRESS

sMASTER CLEAR DMC11

sMEM + SP ADDRESS

sPOINTER TO CORRECT DATA
sLOAD 8 WORDS OF MAIN MEMORY
sPOINTER TO DATA
sLOAD 8 WORDS OF SP
sPOINTER TO DATA
sCLEAR C BIT!

CZOMC

SEQ

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-53

OMCL1 AU TESTS

025330
025336

042737
050037

025344
025346
025354
025360
025362

010000
042737
050037
104414
040660

025342

025364
025366
025370
025372

104414

104414
061224
111205
116104

025376
025400
025402
025404
025406
025410
025412
025416
025420

120504
001401
104015
104401
005202
005200
022700
001342
104400

025425
025430

377
000

000017
025344

000017
025362

025344

025362

BIC
8IS

2%:

3s:

000004

43:
000010

125
252

ROMCLK

017,23
RO,2$

;CLEAR ADDRESS FIELD OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

010000
BIC
017,38
BIS
RO,3s
ROMCLK
0404002<13+20>

sLOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:BR _ A AND B

ROMCLK
61224
MOVB
MOVB

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4
;PUT "EXPECTED” IN RS
;PUT “FOUND” IN R4

CMPB
BEQ
EMT
SCoP1
INC
INC
cHp
BNE
SCOPE

(R2),RS
4(R1),R4
R5,R4
43
15

R2
RO
@10,R0
1s

;:DATA CORRECT?
:BR IF YES
sALU ERROR
:SH09=1?
sNEXT DATA
sNEXT ADDRESS
;DONE YET?
;BR IF NO
;SCOPE THIS TEST

000
.EVEN

shsbbsbsdiistbbbbidbsdbbsiss

TEST

101

ssssssssssstssdbbstidbnsins

;#ALU TEST
s#TEST OF ALU FUNCTION A OR B WITH C BIT CLEARED
s#ALU FUNCTION (A OR B)
CODE=14
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

$:858084
808088800040
0844
0 004
8000
0000000ttt
4000
tttiittttitb
00
tids

;
025432
025440
025446

012737
012737
012737

025454
025456
025460

104412
005000
012702

025464
025470
025472
025476
025500
025504
025512
025516
025520
025522
025530
025534
025536

004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
104414
040700

000101
025606
025500

001226
001216
001220

TST101: MOV
MOV
MOV

MSTCLR
CLR
MOV

025576
034726
034762

035026
000017
025520
000017
025536

TEST 101

025520

025536

1s:

2%:
:

3s:

#101,TSTNO
#TST102,NEXT
#1$,L0CK

RO
95%,R2
PC,MEMLD

JSR
MEMDAT
JSR
PC,.SPLD
SPDAT
JSR
PC,.CLRC
BIC
®17,28%
BIS
RO,2%
ROMCLK
010000
BIC
817,38
BIS
RO,3$
ROMCLK
040400!<14420>

sR1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sMEM + SP ADDRESS
sPOINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
sPOINTER TO DATA
;LOAD 8 WORDS OF SP
sPOINTER TO DATA
sCLEAR C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;BR _ AOR B

" 9R

T——

——

CZDMC

SEQ

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-54

OMC11 ALV TESTS

025540
025542
025544
025546
025552
025554
025556

104414
061224
111205
116104
120504
001401
104015

025562
025564

005202
005200

025560

000004

104401

4s:

025566
025572

000010

025574

022700
001342
104400

025601
025604

377
377

125
252

ROMCLK
61224
MOVB
MOVB
CMPB
BEQ
EMT
SCOP1
INC
INC
cMP
BNE

(R2),.RS
4(R1),R4
R5,.R4
43
15

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE BR TO PORT4
;PUT "EXPECTED” IN RS
;PUT "FOUND" IN R4
sDATA CORRECT?
;BR IF YES
;ALU ERROR

R2
RO

:NEXT ADDRESS

sNEXT DATA

#10,R0
1

SCOPE

:SW09=1?

;DONE YET?
;:BR IF NO
:SCOPE THIS TEST

377
.EVEN

shdksdbitb
bttt dddbddhbhi
dd
ts

TEST

102

sssdbbshbbbbbbbbddbndbbbbds

:#ALU TEST
s#TEST OF ALU FUNCTION A XOR B WITH C BIT CLEARED
s#ALU FUNCTION (A XOR B)
CODE=15
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;*PERFORM THE FUNCTION, VERIFY THE RESULTS

s
025606

012737

025630

104412

025614
025622

025632
025634
025640
025644
025646
025652
025654
025660
025666
025672
025674
025676
025704
025710
025712
025714
025716
025720
025722
025726
025730
025732
025734

012737
012737

005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
104414
040720
104414
061224
111205
116104
120504
001401
104015
104401

000102

025762
025654

001226

001216
001220

TST102:

034762
035026
000017
025674

000017
025712

025674

025712

1s:

2%:

3s:

000004

43:

Pty

TSI

ITIITT

TEST 102

MOV

MOV
MOV

MSTCLR

025752
034726

#102,TSTNO

#TST103,NEXT
#1$,L0CK

CLR
RO
MOV
@53 ,R2
JSR
PC,MEMLD
MEMDAT
JSR
PC,SPLD
SPDAT
JSR
PC,CLRC
81C
#17,2%
BIS
RO,2%
ROMCLK
010000
BIC
817,34
BIS
RO,3$
ROMCLK
040400!<15420>
ROMCLK
61224
Move
(R2),RS5
MOVB
4(R1),R4
CMPB
R5.R4
BEQ
43
EMT
15
SCOP1

:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11

:MEM + SP ADDRESS
sPOINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
sPOINTER TO DATA
;LOAD 8 WORDS OF SP
:POINTER TO DATA
sCLEAR C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sLOAD MAR
sCLEAR ADDRESS OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sBR _ A XOR B
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4
sPUT "EXPECTED” IN RS
;PUT “FOUND” IN R4
;DATA CORRECT?
;BR IF YES
sALU ERROR
:SW09=1?

y 93

CZOMC
MACRO V04.00
DMC11 ALU TESTS
025736
025740
025742
025746

000010

025750

005202
005200
022700
001342
104400

025760

377

000

025752
025755

000
000

SEQ 94

27-JUN-85 13:16:37 PAGE 27-55

377
000

377
377

S¢:

INC
INC
cMP
BNE
SCOPE

R2
RO
#10,R0
1s

.BYTE

:NEXT DATA
sNEXT ADDRESS
;DONE YET?
;BR IF NO

;SCOPE THIS TEST

0,-1,-1,0,0,-1,-1,0

.EVEN

ibdbbbddbdbbbdtbibbbbhhhbhis

TEST

103

sbdsshbbbbdbbbbbbbbbibbbdbs

:#ALU TEST
;#TEST OF ALU FUNCTION ADD WITH C BIT CLEARED
s#ALU FUNCTION (A PLUS B)
CODE=00
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

025762
025770
025776

012737
012737
012737

026004
026006
026010
026014
026020
026022
026026
026030
026034
026042
026046
026050
026052
026060
026064
026066
026070
026072
026074
026076
026102
026104
026106
026110

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
104414
040400
104414
061224
111205
116104
120504
001401
104015
104401

026112
026114
026116

026122
026124

026126
026131
026134

000103
026136
026030

034762
035026
000017
026050
000017
026066

026050

026066

1s:

2%:

3s:

000004

4%:

000010

000
376
377

377
252
124

377
377

LR R

TEST 103

TST103: MOV
MOV
MOV

026126
034726

005202
005200
022700

001342
104400

001226
001216
001220

5Ss:

.BYTE

T TTrTTTITIYIYIII]Y

#103,TSTNO
#TST104 ,NEXT
#14,L0CK

MSTCLR
CLR
RO
MOV
#5¢ ,R2
JSR
PC,MEMLD
MEMDAT
JSR
PC,SPLD
SPDAT
JSR
PC,CLRC
BIC
817,28
BIS
RO,2$
ROMCLK
010000
8IC
#17,3$
BIS
RO,3$
ROMCLK
040400!<00+20>
ROMCLK
61224
MOVB
(R2).RS
MoV
4(R1).R4
CcMPB
R5.R4
BEQ
4%
EMT
15
SCOP1

INC
INC
cHp
BNE
SCOPE

R2
RO
#10,R0
1s

;R1 CONTAINS BASE DMC11 ADDRESS
:MASTER CLEAR DMC11
:MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
sPOINTER TO DATA
:LOAD 8 WORDS OF SP
;POINTER TO DATA
<CLEAR C BIT!

;:CLEAR ADDRESS FIELD OF INSTRUCTION

;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:LOAD MAR

sCLEAR ADDRESS OF INSTRUCTT(M
sADD ADDRESS TO INSTRUCTIGM
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;BR _ ADD
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE BR TO PORT4
;PUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
;:DATA CORRECT?
;BR IF YES
sALU ERROR
:SH09=1?

sNEXT DATA
sNEXT ADDRESS
;DONE YET?

;BR IF NO
:SCOPE THIS TEST

0,-1,-1,376,252,-1,-1,124

CZDMC

SEQ

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-56

DMC11 ALU TESTS

.EVEN

itthbdbtisdbtbhbhbdhihiiiist

TEST

104

ssssitssnssbbbbbnbbdbbbbdas

;#ALU TEST
;#TEST OF ALU FUNCTION 2A W/C WITH C BIT CLEARED
;#ALU FUNCTION (A PLUS A PLUS C)
CODE=6
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#*PERFORM THE FUNCTION, VERIFY THE RESULTS

;
026136
026144
026152

012737
012737
012737

026160
026162
026164
026170
026174
026176
026202
026204
026210
026216
026222
026224
026226
026234

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037

026240
026242
026244
026246
026250
026252
026256
026260
026262
026264
026266
026270
026272
026276
026300

104414
040540
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400

026305
026310

376
124

026302

000

000104
026312
026204

001226
001216
001220

034762

000017
026242

026224

026242

1s:

2%:

3s:

000004

4$:
000010

000

252
124

376

252

5%:

TEST 104

TST104: MOV
MOV
MOV

026302
034726

035026
000017
026224

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR
BIC
BIS
ROMCLK
010000
BIC
BIS

#104,TSTNO
#TST105,NEXT
#1$,L0CK

;:R1 CONTAINS BASE DMC11 ADDRESS

RO
#5%,R2
PC,MEMLD
PC,SPLD
PC,CLRC
#17,2¢
RO,2$

#17,3%
RO,3$

ROMCLK
040400!<6+20>
ROMCLK
61224
MOVB
(R2),RS
MOVB
4(R1),R4
CMPB
R5,.R4
BEQ
43
EMT
15
SCOP1
INC
R2
INC
RO
CcHP
#10.RO
BNE
1s
SCOPE

.BYTE

;MASTER CLEAR DMC11
:MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
:POINTER TO DATA
;LOAD 8 WORDS OF SP
;sPOINTER TO DATA
;CLEAR C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:BR _ 2A W/C
sNEXT WORD IS INSTRUCTION, RL!ICLK PC=5304
:MOVE BR TO PORT4
:PUT "EXPECTED” IN RS
;PUT "FOUND” IN R4
sDATA CORRECT?
;BR IF YES
;:ALU ERROR
:SW09=1?
:NEXT DATA
sNEXT ADDRESS
;DONE YET?
;BR IF NO
:SCOPE THIS TEST

0,0,376,376,252,252,124,124

.EVEN
shdbkdhbbdbbitbbbbbbhitibss

TEST

105

ssdsdbtdhbddbdbsbbbdbbhssnd

;#ALU TEST
;#TEST OF ALU FUNCTION SUB WITH C BIT CLEARED
;#ALU FUNCTION (A-8B)
CODE=16
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA

9
.-

T Ty

CZDMC
MACRO V04.00
DMC11 ALU TESTS

SEQ 96

27-JUN-85 13:16:37 PAGE 27-57

s#PERFORM THE FUNCTION, VERIFY THE RESULTS

PR
P PP PP PP TP PP

TEST 105

;
S

026312
026320
026326

012737
012737
012737

026334
026336
026340
026344
026350
026352
026356
026360
026364
026372
026376
026400
026402
026410
026414
026416
026420
026422
026424
026426

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
104414

026432
026434
026436

026440
026442
026444
026446
026452
026454
026456
026461
026464

000105
026466
026360

001226
001216
001220

034762

000017
026416

026400

026416

104414
061224
111205
116104
120504
001401
104015
104401
005202

005200

022700
001342
104400
000
000
125

1s:

2%:

3s:

040740

#105,TSTNO
#TST106,NEXT
#1$,L0CK

;R1 CONTAINS BASE DMC11 ADDRESS

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR
BIC
BIS
ROMCLK
010000
BIC
BIS
ROMCLK

4%:

000010
377
253

5%:

sMASTER CLEAR DMC11
;MEM + SP ADDRESS
;sPOINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
;CLEAR C BIT!
;:CLEAR ADDRESS FIELD OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION
:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

RO
#5%,R2
PC,MEMLD

PC,SPLD
PC,CLRC
#17,2%
RO,2¢

#17,3$
RO,3$

040400!<16%20>

ROMCLK
61224
MOVB

:BR _ SuB

+NEXT WORD IS INSTRUCTION,
;MOVE BR TO PORT4
:PUT “EXPECTED” IN RS

(R2),R5

MOve

000004

001
000
000

TST105: MOV
MOV
MOV

026456
034726

035026
000017
026400

4(R1),.R4

CHPB
BEQ
EMT
SCoP1
INC
INC
cMP
BNE
SCOPE
.BYTE

;PUT “FOUND” IN R4

R5,R4
43
15

:DATA CORRECT?
:BR IF YES
;ALU ERROR
:SW09=1?
R2
;:NEXT DATA
RO
;NEXT ADDRESS
#10,R0
;:DONE YET?
1s
;BR IF NO
:SCOPE THIS TEST
0,1,-1,0,0,253,125,0

.EVEN

shbddsdsbhbbbbbbbbbdbtttstds

TEST

106

shsdsdsdbbbstbdibbdbbbhhhia

s#ALU TEST
s#TEST OF ALU FUNCTION ADD W/C WITH C BIT CLEARED
;#ALU FUNCTION (A PLUS B PLUS C)
CODE=01
s#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
+#PERFORM THE FUNCTION, VERIFY THE RESULTS
HEE

TEST 106

026466
026474
026502

012737
012737
012737

000106
026642
026534

ROMCLK PC=5304

001226
001216
001220

TST106: MOV
MOV
MoV

2 T

#106,TSTNO
#TST107,NEXT
#1$,L0CK

TRy Ry

T TT I TITT

CZDMC
MACRO V04.00
DMC11 ALU TESTS
026510
026512
026514
026520
026524
026526
026532
026534
026540
026546
026552
026554
026556
026564
026570

026572
026574
026576
026600
026602
026606
026610
026612
026614

026616
026620
026622
026626

026630
026632

026635
026640

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
104414

026632
034726

034762
035026
000017
026554

000017
026572

026554

026572

040420
104414

061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400
000

376
377

SEQ 97

27-JUN-85 13:16:37 PAGE 27-58

18:

2s:

3s:

000004

as:

000010

377

252
124

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR
BIC
BIS
ROMCLK
010000
BIC
BIS
ROMCLK

377

Ss:

RO
#5%,R2
PC.MEMLD

;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
:CLEAR C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
:CLEAR ADDRESS OF INSTRUCTION
:ADD ADDRESS TO INSTRUCTION
:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304

PC.SPLD
PC,CLRC
217,23
RO,2$

217,38
RO,3$

040400 <01%20>
ROMCLK
61224
MOVB
(R2).RS
MOVB
4(R1),R4
CMPB
RS,R4
BEQ
'Y
EMT
15

:BR _ ADD W/C
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4
:PUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
:DATA CORRECT?
:BR IF YES
;:ALU ERROR

INC
INC
CMP

R2
RO
#10 70

;NEXT DATA
:NEXT ADDRESS
;DONE YET?

SCOPE
.BYTE

:SCOPE THIS TEST
0,-1,-1,376,252,-1,-1,124

SCOP1

BNE

377

;R1 CONTAINS BASE DMC11 ADDRESS
;MASTER CLEAR DMC11
:MEM + SP ADDRESS

1SW09=12

:BR IF NO

.EVEN

shbbssbidnsbbbbbsbssiitsdiss

;#ALU TEST

TEST

107

sssssssssdsdbddsnsdississss

+#TEST OF ALU FUNCTION SUB W/C WITH C BIT CLEARED
s#ALU FUNCTION (A-8-C)
CODE=2
:#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
+#PERFORM THE FUNCTION, VERIFY THE RESULTS
R

026642
026650
026656

012737
012737
012737

026664
026666
026670
026674
026700
026702
026706

104412
005000
012702
004737
035052
004737
035062

000107
027016
026710

027006
034726
034762

001226
001216
001220

TR T R E

TEST 107

s
’

LT e

..............

TST107: MOV
MOV
MoV

MSTCLR
CLR
MoV
JSR
MEMDAT
JSR
SPDAT

#107,TSTNO
#TST110, NEXT
#1%,L0CK

RO
#5%,R2
PC,MEMLD
PC,SPLD

;R1 CONTAINS BASE DMC11 ADDRESS

sMASTER CLEAR DMC11
sMEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
sPOINTER TO DATA
:LOAD 8 WORDS OF SP
sPOINTER TO DATA
-

vy rey

CZDMC

SEQ

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-59

DMC11 ALU TESTS

026710
026714
026722
026726
026730
026732
026740

004737
042737
050037
104414
010000
042737
050037

026746

040440

026752

061224

026744

026750

026754
026756
026762

104414

111205
116104
120504

001401
104015

026772

005202

026746

005200
022700
001342
104400

027011
027014

377
124

377

1s:

2%:

3s:

JSR
BIC
BIS
ROMCLK
010000
BIC
BIS

ROMCLK

4%:
000010

000
377
377

376

252

5%:

;CLEAR C BIT!
:CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TC INSTRUCTION

17,3
RO,3¢

;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sBR _ SUB W/C

ROMCLK

MOVB
MOVB
CMPB

000004

PC,CLRC
#17,2%
RO,2¢

040400!<2420>

61224

104401

026774
026776
027002
027004

027006

000017
026746

026730

104414

026764
026766

026770

035026
000017
026730

43
15

INC

INC
cMP
BNE
SCOPE

.BYTE

:MOVE BR TO PORT4

(R2).R5
4(R1),R4
R5,R4

BEQ
EMT

SCOP1

:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304

;PUT "EXPECTED” IN RS
;PUT "FOUND” IN R4
:DATA CORRECT?
:BR IF YES
sALU ERROR

:SW09=1?

sNEXT DATA

RO
#10,RO
1s

sNEXT ADDRESS
:DONE YET?
:BR IF NO
;SCOPE THIS TEST

-1,0,376,-1,-1,252,124,-1

.EVEN

jhhkbb
bbb
dbbbhs
bbhdbnbtints

TEST

110

sssdtsddssssbbbbtbbdstsddds

;#ALU TEST
s#TEST OF ALU FUNCTION INC A WITH C BIT CLEARED
s#ALU FUNCTION (A PLUS 1)
CODE=3
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

BRI

;

T T

rrTTrrTYrYYYTMY

TEST 110

‘ ..............

027016
027024
027032

012737
012737
012737

027040

104412

027042

005000

000110
027172
027064

012702
004737

027162
034726

027056
027062
027064
027070
027076
027102
027104
027106
027114

004737
035062
004737
042737
050037
104414
010000
042737
050037

034762

027120

035052

104414

TST110: MOV
MOV
MOV

MSTCLR

027044
027050

027054

001226
001216
001220

035026
000017
027104
000017
027122

CLR

027122

18:

2%:

MOV
JSR

454 ,R2
PC.MEMLD

JSR
SPDAT
JSR
BIC
BIS
ROMCLK
010000
BIC
BIS

PC,SPLD

MEMDAT

027104

#110,TSTNO
@TST111,NEXT
@1%,L0CK

ROMCLK

PC,CLRC
#17,2%
RO,2¢
#17,3%
RO,3$

:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sMEM + SP ADDRESS
;POINTER TO CORRECT DATA
;sLOAD 8 WORDS OF MAIN MEMORY
sPOINTER TO DATA
:LOAD 8 WORDS OF SP
;POINTER TO DATA
;CLEAR C BIT!

sCLEAR ADDRESS FIELD OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

’ 98

CZDMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-60

DMC11 ALV TESTS

027122
027124
027126
027130
027132
027136
027140
027142
027144
027146
027150
027152
027156
027160

040460
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400

027165

000

027162
027170

3s:

000004

4s:
000010

001

253

126

000
126

5s%:

0404001 <3+20>
ROMCLK
61224
MOVB
(R2),RS5
MOVB
4(R1).R4
CcMPB
R5,.R4
BEQ
4%
EMT
15
SCorP1
INC
R2
INC
RO
CMP
#10,R0
BNE
1s
SCOPE

.BYTE

;BR _ INC A
:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:MOVE BR TO PORT4
;PUT "EXPECTED” IN RS
;PUT “FOUND" IN R4
;DATA CORRECT?
;:BR IF YES
:ALU ERROR
:SW09=1?
;NEXT DATA
;NEXT ADDRESS
;:DONE YET?
;:BR IF NO
:SCOPE THIS TEST

1,1,0,0,126,126,253,253

.EVEN

ihdkkdbhhbhihhhnhkhhkhbihhhhhhd

TEST

11]

ssdbsbbbhbsbbbbbbsbbdbddhts

;#ALU TEST
;#TEST OF ALU FUNCTION 2A WITH C BIT CLEARED
;#ALU FUNCTION (A PLUS A)
CODE=5
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

s
027172
027200

012737
012737

027214
027216
027220
027224
027230
027232
027236
027240

104412
005000
012702
004737
035052
004737
035062
004737

027256
027260
027262
027270

104414
010000
042737
050037

027276
027300
027302
027304
027306
027312
027314
027316

040520
104414
061224
111205
116104
120504
001401
104015

027206

027244
027252

027274

012737

042737
050037

104414

000111
027346

027240

001226
001216

001220

MOV

1¢:

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR

2%:

ROMCLK
010000

034762

000017
027276

027260

027276

3s:

000004

TTTTTTITTT T

Ty Yyvorrees

TEST 111

TSTiii: MOV
MOV

027336
034726

035026
000017
027260

#111,TSTNO
#TST112,NEXT

#1¢,L0CK

RO
#5%,R2
PC,MEMLD
1
PC,SPLD

BIC
BIS

PC,CLRC
$17,2%
RO,2%

BIC
BIS

#17,38
RO,3$

ROMCLK

0404001 <5420>
ROMCLK
61224
MOVB
(R2),R5
Movs
4(R1),R4
CcMPB
RS.R4
BEQ
44
EMT
15

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;MEM « SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
;CLEAR C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION

:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304

sBR _ 2A
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE BR TO PORT4
;PUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
:DATA CORRECT?
sBR IF YES
;ALU ERROR

MACRO V04.00
CZDMC
DMC11 ALU TESTS

027320
027322
027324
027326
027332
027334
027336
027341
027344

104401
005202
005200
022700
001342
104400
00C
376
124

SEQ 100

27-JUN-85 13:16:37 PAGE 27-61

45:

000010
000
252
124

376
252

S5$:

SCoP1
INC
INC
CHP
BNE
SCOPE
.BYTE

R2
RO
#10,R0
1s

;SW09=17?
;NEXT DATA
;NEXT ADDRESS
;DONE YET?
;BR IF NO

;SCOPE THIS TEST

0,0,376,376,252,252,124,124

.EVEN

jhbkkhbihbbhbhbbbibbbbbdhbhd

;*ALU TEST

TEST

112

sbsbsbdtsssbbbtbtsttbbibsss

:#TEST OF ALU FUNCTION A PLUS C WITH C BIT CLEARED

;#ALU FUNCTION (A PLUS C)
CODE=4
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS
R

;

TEST 112

PP P PP IPTPPe,

; ..............

027346
027354
027362

012737
012737
012737

027370

104412
005000
012702
004737

027372
027374
027400
027404
027406
027412
027414
027420
027426
027432
027434
027436
027444
027450
027452
027454
027456
027460
027462
027466
027470
027472
027474
027476
027500
027502
027506
027510
027512
027515

035052
004737
035062
004737
042737
050037
104414

010000

042737
050037
104414
040500
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400
000
377

000112

027522
027414

001226
001216
001220

TST112: MOV
MOV
MOV

027512
034726

034762

035026

000017

027434

000017

027452

027434

027452

1s:

2%:

3¢:

000004

4%:

BIS
ROMCLK

377
125

RO
#5$,R2
PC,MEMLD

PC,SPLD
PC,CLRC
217,24
RO,2$

017,38
RO,3¢

040400!<4420>
ROMCLK
61224
MOVB
(R2),R5
MOVB
4(R1),R4

CMPB
BEQ
EMT
SCOP1
INC
INC

R2
RO

BNE

cHMP

000010
000
125

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR
BIC
BIS
ROMCLK
010000
8IC

#112,TSTNO
#TST113,NEXT
#1$,L0CK

SCOPE
.BYTE

RS,R4
43
15

#10,R0

;:R1 CONTAINS BASE DMC11 ADDRESS
;MASTER CLEAR DMC11
;MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
;CLEAR C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

:BR _ A PLUS C
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4
;PUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
;DATA CORRECT?
;BR IF YES
;ALU ERROR
;SW09=17?
sNEXT DATA
sNEXT ADDRESS
;sDONE YET?
sBR IF NO
;SCOPE THIS TEST

CZPMC
MACRO V04,00
OMC11 ALU TESTS

027520

252

SEQ 101

27-JUN-85 13:16:37 PAGE 27-62

252

.EVEN

shbbbsbidbbtdtbhbbbtidhitins

TEST

113

sesnsssssbsbsssttsbshtstss

;#ALU TEST
s#TEST OF ALU FUNCTION 2'S COMP SUB WITH C BIT CLEARED
;#ALU FUNCTION (A-B-1)
CODE=17
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

;
027522
027530
027336

012737
012737
012737

027544
027546

104412
005000

027550
027554

027560
027562
027566

027570
027574
027602

027606
027610

027612
027620

027624
027626
027630

027632
027634
027636
027642

027644
027646
027650

027652
027654
027656

042737
050037

104414
040760
104414
061224
111205
116104
120504

001226
001216
001220

034762
035026
000017
027610
000017
027626

027610

027626

4s:

377

000

377
124

24:

000004

000010

027671
027674

1s:

3s:

005202
005200
022700

001342
104400

TST113: MOV
MOV
MOV

027666
034726

377
377

376

252

5%:

PP PP,

TEST 113

MSTCLR
CLR

001401
104015
104401

027662
027664

027666

012702
004737
035052
004737
035062
004737
042737
050037
104414
010000

000113
027676
027570

MOV
JSR
MEMDAT
JSR
SPDAT
JSR
BIC
BIS
ROMCLK
010000
BIC
BIS

#113,TSTNO
#TST114,NEXT
#13,L0CK

;R1 CONTAINS BASE DMC11 ADDRESS
RO
#5%,R2
PC,MEMLD

PC,SPLD
PC,CLRC
€17,24
RO,2¢
#17,3$
RO,3$

ROMCLK
040400!<17420>
ROMCLK

61224
MOVB
MOVB
CMPB
BEQ
EMT
SCoP1
INC
INC
cMpP
BNE
SCOPE

.BYTE

(R2),R5
4(R1),R4
R5,R4
43
15
Re
RO
#10,R0

;MASTER CLEAR DMC11
:MEM + SP ADDRESS

;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;:POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
;CLEAR C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
:ADD ADDRESS TO INSTRUCTION
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION

:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:BR _ 2'S COMP SUB
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE BR TO PORT4
;PUT "EXPECTED” IN RS
;PUT “FOUND" IN R4
sDATA CORRECT?

iBR IF YES
;ALU ERROR
:SW09=1?

:NEXT DATA
sNEXT ADDRESS
;DONE YET?

:BR IF NO
;SCOPE THIS TEST

-1,0,376,-1,-1,252,124,-1

.EVEN

shbsibdbdbbdbdibbibbdnttsins

TEST

114

ssssssissssnsissttddsddtsns

s%ALU TEST
;#TEST OF ALU FUNCTION DEC A WITH C BIT CLEARED
;%ALU FUNCTION (A-1)
CODE=7

CZOMC
MACRO V04.00
DMC11 ALU TESTS

SEQ 102

27-JUN-85 13:16:37 PAGE 27-63

;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS
B
PP PP PP PP

TEST 114

;
027676
027704
027712

012737
012737
012737

027720
027722

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
104414
040560
104414
061224
111205
116104

027724
027730
027734
027736
027742
027744
027750
027756
027762
027764
027766
027774
030000
030002
030004
030006
030010
030012
030016
030020
030022
030024
030026
030030
030032
030036
030040
030042
030045
030050

120504
001401
104015

104401
005202
005200
022700
001342

104400
377
376
251

000114
030052
027744

001226
001216
001220

TST114: MOV
MOV

MOV

#114 ,TSTNO
#TST115,NEXT

#1%,L0CK

MSTCLR

030042
034726

034762
035026
000017
027764

000017
030002

027764

030002

1s:

2%:

3s:

000004

4%:

000010
377
124
251

376

124

S5%:

CLR
RO
MOV
#54,R2
JSR
PC,MEMLD
MEMDAT
JSR
PC,SPLD
SPDAT
JSR
PC,CLRC
BIC
917,28
BIS
RO,2$
ROMCLK
010000
BIC
#17,3¢
BIS
RO,3$
ROMCLK
040400!<720>
ROMCLK
61224
MOVB
(R2),RS
MOVB
4(R1),R4

CMPB
BEQ
EMT
SCOP1
INC
INC
CHP
BNE
SCOPE
.BYTE

R5,R4
4%
15

iR1 CONTAINS BASE DMC11 ADDRESS

;MASTER CLEAR DMC11

;MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
;CLEAR C BIT!
:CLEAR ADDRESS FIELD OF INSTRUCTION
:ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:BR _ DEC A
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE BR TO PORT4
;PUT “EXPECTED” IN RS
;PUT "FOUND” IN R4

;DATA CORRECT?
:BR IF YES

sALU ERROR

:SW09=17
sNEXT DATA
sNEXT ADDRESS
;:DONE YET?
:BR IF NO
:SCOPE THIS TEST
-1,-1,376,376,124,124,251,251

R2
RO
€10,R0
1s

.EVEN

sjtdhdbdbbbsbsbdiinsbibtdtndd

;#ALU TEST

TEST

115 sesssssssdssssnddsssdbddans

+#TEST OF ALU FUNCTION SEL 8 WITH C BIT SET
;#ALU FUNCTION (8B)
CODE=11
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
+#PERFORM THE FUNCTION, VERIFY THE RESULTS

JiASARARAAAR0ASARAAARERA0
AR08 000000000480000000800008800804

TEST 115

Fhavnmmsdwmdws

030052
030060

012737
012737

000115
030226

001226
001216

TST11S: MOV
MOV

#115,TSTNO
OTST116,NEXT

CZDMC
MACRO V04.00
DMC11 ALV TESTS
030066

012737

030074
030076
030100
030104
030110
030112

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737

030116
030120
030124

030132
030136
030140
030142
030150
030154
030156

030160
030162
030164
030166
030172
030174
030176
030200
030202
030204
030206
030212
030214
030216
030221
030224

050037
104414
040620
104414
061224
111205
116104

120504
001401
104015

104401
005202
005200
022700
001342
104400
000
377
125

SEQ 103

27-JUN-85 13:16:37 PAGE 27-64

030120

001220

MOV

030216
034726
034762
035040
000017
030140

000017
030156

030140

030156

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT

PC,SPLD

JSR

PC,SETC
RO,2$

2%:

BIS
ROMCLK
010000

BIC

BIC
BIS

000004

43
:

000010
5%:

#17,2%

917,38
RO,3$

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sMEM + SP ADDRESS

;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
sPOINTER TO DATA
;SET C BIT!

;CLEAR ADDRESS FIELD OF INSTRUCTION

;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION

ROMCLK
040400!<11420>
ROMCLK

:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:BR _ SEL B
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

MOVB

;PUT “EXPECTED” IN RS

61224

000
252

RO
#5%,R2
PC,MEMLD

1%:

3s:

377
125
252

#1s,L0CK

MOvVB
CMPB
BEQ
EMT
SCoP1
INC
INC
CHP
BNE
SCOPE
.BYTE

(R2),R5

4(R1),.R4
RS,R4
43
15
R2
RO
#10,R0
1%

;MOVE BR TO PORT4

:PUT “FOUND” IN R4
;:DATA CORRECT?
:BR IF YES
;ALU ERROR
:SW09=17
sNEXT DATA
sNEXT ADDRESS
:DONE YET?
:BR IF NO
:SCOPE THIS TEST

0,-1,0,-1,125,252,125,252

.EVEN

i88884s8 00005000000 000058

TEST

116

2ssssastssssssssdtssisasitss

ssALU TEST
;#TEST OF ALU FUNCTION SEL A WITH C BIT SET
ssALU FUNCTION (A)
CODE=10
:+sLOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
+#PERFORM THE FUNCTION, VERIFY THE RESULTS

118888804008

s+
030226
030234
030242

012737
012737
012737

030250
030252
030254
030260
030264
030266

104412
005000
012702
004737
035052
004737

000116
030402
030274

030372
034726
034762

001226
001216
001220

0400 8488048004040 88088048800000000000000000800000004

TEST 116

TST116: MOV

MOV
MOV

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR

#116,TSTNO
@TST117,NEXT
#14,L0CK
RO
58 ,R2
PC ,MEMLD

PC,SPLD

:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sMEM + SP ADDRESS
sPOINTER TO CORRECT DATA
sLOAD 8 WORDS OF MAIN MEMORY
sPOINTER TO DATA
;LOAD 8 WORDS OF SP

CZOMC
MACRO V04.00
DMC11 ALV TESTS
030272
030274
030300
030306
030312
030314
030316
030324
030330
030332
030334
030336
030340
030342
030346
030350
030352
030354

030356
030360
030362
030366
030370
030372
030375
030400

035062
004737
042737
050037
104414
010000
042737

050037

104414
040600
104414
061224

111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400
000
377
252

SEQ 104

27-JUN-85 13:16:37 PAGE 27-65

035040
000017
030314
000017
030332

030314

030332

1$:

SPDAT
JSR

2%:

BIS
ROMCLK
010000

3s:

BIC

000010

000
125
252

377
125

S5%:

217,24

RO.2$

#17,3%

;POINTER TO DATA
sSET C BIT!

;:CLEAR ADDRESS FIELD OF INSTRUCTION

sADD ADDRESS TO INSTRUCTION
:NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
:CLEAR ADDRESS OF INSTRUCTION

BIS
RO,3$
ROMCLK
040400!<10+20>
ROMCLK
61224

;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:BR _ SEL A
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:MOVE BR TO PORTA

MOVB
CMPB
BEQ
EMT
SCoP1
INC
INC
CHMP
BNE
SCOPE

;PUT “FOUND” IN R4
:DATA CORRECT?
:BR IF YES
;ALU ERROR
1SK09=17?
:NEXT DATA
:NEXT ADDRESS
;DONE YET?
18R IF NO
;SCOPE THIS TEST

43:

PC,SETC

.BYTE

(R2),RS

4(R1).R4
RS,.R4
43
15
R2
RO
#10,R0
1s

;PUT "EXPECTED” IN RS

0,0,-1,-1,125,125,252,252

.EVEN

j888dsbbbisdtdissinissssssns

TEST

117

stssssssssssssssssssdsdsdns

;#ALU TEST
saTEST OF ALU FUNCTION A OR NOTB WITH C BIT SET
s#ALU FUNCTION (A OR NOTB)
CODE=12
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
ssPERFORM THE FUNCTION, VERIFY THE RESULTS

§:88885848488848448084888480088058888848828888848508800000000000044

TEST 117

' ..............

012737
012737
012737
104412
005000
012702
004737
035052

004737
035062
004737

042737
050037
104414
010000
042737
050037

000117
030556
030450

001226
001216
001220

TST117: MOV

MOV
MOV

18:

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR

RO,2¢

2%:

8IS
ROMCLK
010000
BIS

RO,3¢

030546
034726
034762

035040
000017
030470
000017

030470

#117,7TSTNO
#TST120, NEXT
#14,L0CK

BIC

8IC

RO
#58,R2
PC . MEMLD

PC.SPLD

PC,SETC
17,28

07,3

sR1 CONTAINS BASE DMC11 ADDRESS

sMASTER CLEAR DMC11
sMEM + SP ADDRESS
sPOINTER TO CORRECT DATA
:LOAD 8 WORDS OF MAIN MEMORY
sPOINTER TO DATA
sLOAD 8 WORDS OF SP
sPOINTER TO DATA
+SET C BIT!

sCLEAR ADDRESS FIELD OF INSTRUCTION

+ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sLOAD MAR
:CLEAR ADDRESS OF INSTRUCTION

sADD ADDRESS TO INSTRUCTION

CIOMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-66

i Ko

DMC11 ALU TESTS
030504
030506
030510
030512
030514
030516
030522
030524
030526
030530
030532

104414
040640
104414
061224
111205
116104
120504
001401
104015
104401
005202

030534
030536
030542
030544

005200
022700
001342
104400

030551
030554

377
252

3s:

000004

INC
cMpP
BNE
SCOPE

000010

377
377

ROMCLK
040400:<12+20>
ROMCLK
61224
MOVB
(R2).R5
MOVB
4(R1),.R4
CcMPB
R5.R4
BEQ
43
EMT
15
SCoP1
INC
R2

RO
€10,R0O
1s

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
s:BR _ A OR NOTB
)
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE BR TO PORT4
;PUT "EXPECTED” IN RS
sPUT “FOUND” IN R4
;DATA CORRECT?
;BR IF YES
;ALU ERROR
:SW09=1?
sNEXT DATA

sNEXT ADDRESS
;DONE YET?
;:BR IF NO
;SCOPE THIS TEST

125
.EVEN

shshsbbbtbbtbbdbbbtbtissstbds

TEST

120

stsssdbdtsdssbsbdddbbdsbdss

;#ALU TEST
ssTEST OF ALU FUNCTION A AND B WITH C BIT SET
s#ALU FUNCTION (A AND B)
CODE=13
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS
:858 8 8 48

;
030556
030564
030572

012737
012737
012737

030600
030602
030604
030610
030614
030616
030622
030624

104412
005000
012702
004737
035052
004737
035062
004737

030630
030636

030642
030644
030646

030654
030660
030662
030664
030666
030670
030672
030676
03070C

042737
050037

104414
010000
042737
050037
104414
040660
104414
061224
111205
116104
120504
001401

000120
030732
030624

001226
001216
001220

034762

000017
030662

030644

030662

1s:

2s:

3s:

000004

TEST 120

TST120: MOV
MOV
MOV

030722
034726

035040
000017
030644

880404002040 00 0040000 kd bbbttt dthbb bbbttt bbtibibhbhis

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR
BIC
BIS

ROMCLK
010000
BIC

2120,TSTNO
#TST121 ,NEXT
#13,L0CK

RO
#58,.R2
PC.MEMLD
PC.SPLD
PC,SETC
917,28
RO,2$

£17,38
BIS
RO,3$
ROMCLK
040400:<13420>
ROMCLK
61224
MOVB
(R2).,RS
MOVB
4(R1),R4
CMPS
R5.R4
BEQ
4s

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sMEM + SP ADDRESS
;:POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
;SET C BIT!

sCLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION

+NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
s;BR _ A AND B
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4
;PUT "EXPECTED" IN RS
;PUT “FOUND” IN R4
;sDATA CORRECT?
;BR IF YES

CIOMC
MACPO VO04.00
DMC11 ALV TESTS
030702
030704
030706
030710

030712
030716

030720
030722
030725
020730

104015
104401
005202
005200

022700
001342
104400
000
377
000

SEQ 106

27-JUN-8S 13:16:37 PAGE 27-67

4s:

000010
000
125
252

EMT
SCoP1
INC
INC

cMpP
BNE
000
000

Ss:

SCOPE
.BYTe

15
R2
RO

€10,R0
1s

;ALU ERROR
:SWC9=17?
;sNEXT DATA

sNEXT ADDRESS

;DONE YET?
;BR IF NO

;SCOPE THIS TEST

0,0,0,-1,125,0,0,252

.EVEN

;84
bbbt 440
bbtddtbbtbittiis
0

TEST

12]

stsdsbbhsbbbbbissbdbbhdtsss

;#ALU TEST
;#TEST OF ALU FUNCTION A OR B WITH C BIT SET
;#ALU FUNCTION (A OR B)
CODE=14
;¢LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA

;#PERFORM THE FUNCTION,

VERIFY

THE RESULTS

3:60588484
800000
88080
b0tsbbbbbbb
88808
ibibibtbbbt28858
ittt thihhiids

TEST 121

;
’

020732
030740
030746

012737
012737
012737

030754
030756
030760
030764
030770
030772
0320776
031000
031004
031012
031016
031020
031022
031030
031034
031036
031040
031042
031044
031046
031052
031054
031056
031060
031062
031064
031066
031072
031074
031076

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
1044124
040700
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400
000

000121
031106
031000

001226
001216
001220

TSTi21: MOV
MOV
MOV

031076

034726
034762

035040
000017
031020
000017
031036

031020

031036

1s:

2%:

3s:

000004

000010
377

377

--------------

Ss:

£121,TSTNO
#T5T122 ,NEXT
#18,L0CK

:R1 CONTAINS BASE DMC11 ADDRESS
MSTCLR
sMASTER CLEAR DMC11
CLR
RO
:MEM +» SP ADDRESS
MOV
#5%,.R2
;sPOINTER TO CORRECT DATA
JSR
PC,.MEMLD
;LOAD 8 WORDS OF MAIN MEMORY
MEMDAT
;PCINTER TO DATA
JSR
PC,.SPLD
;:LOAD 8 WORDS OF SP
SPDAT
:POINTER TO DATA
JSR
PC,SETC
:SET C BIT!
BIC
#17,2%
sCLEAR ADDRESS FIELD OF INSTRUCTION
BIS
RO,2%
;ADD ADDRESS TO INSTRUCTION
ROMCLK
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
010000
;LOAD MAR
BIC
217,38
sCLEAR ADDRESS OF INSTRUCTION
BIS
RO,3s
;ADD ADDRESS TO INSTRUCTION
ROMCLK
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
040400!<14220>
;BR _
AOR B
ROMCLK
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
61224
sMOVE BR TO PORT4
MOVB
(R2),RS
;PUT “EXPECTED” IN RS
MOVB
4(R1),R4
;sPUT “FOUND” IN R4
CMPB
R5.R4
sDATA CORRECT?
BEQ
4%
;BR IF YES
EMT
15
sALU ERROR
SCoP1
:SW09=1?
INC
R2
sNEXT DATA
INC
RO
;NEXT ADDRESS
cMpP
#10,R0
;DONE YET?
BNE
1s
sBR IF NO
SCOPE
;SCOPE THIS TEST
.BYTE
0,-1,-1,-1,125,-1,-1,252

CZDMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-68

E
7
-

OMC11 ALV TESTS

031101
031104

377
377

125
252

377
.EVEN

itbbtbbbdbbtbbittbdtbtittdids

TEST

122

sttt sskbbbbbtbbbbsdtbbbts

;#ALU TEST
;#TEST OF ALU FUNCTION A XOR B WITH C BIT SET
;#ALU FUNCTION (A XOR B)
CODE=15
;+«LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
s#PERFORM THE FUNCTION, VERIFY THE RESULTS

031106
031114
031122

012737
012737
012737

031130
031132
031134
021140
021144
031146

104412
005000
012702
004737
035052
004737

031252
034726

042737

035040
000017
031174

031152
031154

035062
004737

031166
031172

050037
104414

031160

031174
031176
031204
031210
031212
031214
031216

031220
031222
031226
031230
031232
031234
031236
031240
031242
031246
031230
031252
031255
031260
95

010000
042737
050037
104414
040720
104414
061224

111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400
000
000
377

000122
031262
031154

001226
001216
001220

;

TEST 122

T TryryTTTYIY

#122,TSTNO
#TST123,NEXT
#1$,L0CK

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
RO
sMEM + SP ADDRESS
#5%,R2
;POINTER TO CORRECT DATA
PC,MEMLD
;LOAD 8 WORDS OF MAIN MEMORY
;:POINTER TO DATA
PC,SPLD
;LOAD 8 WORDS OF SP
SPDAT
;POINTER TO DATA
JSR
PC,SETC
sSET C BIT!
BIC
#17,2¢
:CLEAR ADDRESS FIELD OF INSTRUCTION
BIS
RO,2¢
;ADD ADDRESS TO INSTRUCTION
ROMCLK
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
010000
;LOAD MAR
BIC
#17,38
;:CLEAR ADDRESS OF INSTRUCTION
BIS
RO,3s$
;ADD ADDRESS TO INSTRUCTION
ROMCLK
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
040400!<15+20>
;BR _ A XOR B
ROMCLK
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
61224
:MOVE BR TO PORT4
MOVB
(R2),R5
;PUT “EXPECTED” IN RS
MOVB
4(R1),.R4
;PUT “FOUND” IN R4
CMPB
R5,R4
;DATA CORRECT?
BEQ
4%
:BR IF YES
EMT
15
:ALU ERROR
sCorP1
:SH09=1?
INC
R2
sNEXT DATA
INC
RO
sNEXT ADDRESS
CcMP
#10,R0
;DONE YET?
BNE
1s
;:BR IF NO
SCOPE
;SCOPE THIS TEST
.BYTE
0,-1,-1,0,0,-1,-1,0

031174

031212

1s:

2%:

000004

4%:
000010
377
377

Ss:
.EVEN

kbl bbbbbddbdkdhdsbbdiknsss

TEST

123

stsssssdddddbbbddbibsdisiss

;#ALU TEST
;#TEST OF ALU FUNCTION ADD WITH C BIT SET

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR

3s:

377
000
000

TST122: MOV
MOV
MOV

034762

000017
031212

MACRO V04.00
CZDMC
DMC11 ALU TESTS

SEQ 108

27-JUN-85 13:16:37 PAGE 27-69

ssALU FUNCTION (A PLUS B)
CODE=00
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA

;#PERFORM THE FUNCTION,
$:8888358885

;
031262
031270
031276

012737
012737
012737

031304
031306

104412
005000

031310
031314

031320
031322

031326
031330
021334
031342
031346
031350
031352
031360
031364
031366
031370
031372
031374
031376
031402
031404
031406
031410
031412
031414
031416
031422
031424

031426
031431

031434

012702
004737

035052
004737

035062
004737
042737
050037
104414
010000
042737
050037
104414
040400
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400

000
376
377

000123
031436
031330

001226
001216
001220

034762

035040
000017
031350
000017
031366

031350

031366

18:

2%:

3s:

000004

4%:

000010

377
252

124

377
377

5s:

THE RESULTS

b0 kk bbbt

hh bk bbbt

bh bbbkt bbb bid

TEST 123

TST123: MOV
MOV
MOV

031426
034726

VERIFY

585558054500

#123,TSTNO
#T57124 ,NEXT
#1s,L0CK

,
:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;:MEM + SP ADDRESS

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR

PC,SPLD

.BYTE

0,-1,-1,376,252,-1,-1,124

RO
#5%,R2
PC,MEMLD

SPDAT
JSR
PC,SETC
BIC
#17,2%
BIS
RO,2$
ROMCLK
010000
BIC
217,38
BIS
RO,3$
ROMCLK
0404001 <00+20>
ROMCLK
61224
MOVB
(R2) ,RS
MOVB
4(R1),R4
CMPB
RS,R4
BEQ
43
EMT
15
SCoP1
INC
R2
INC
RO
cMpP
#10,R0
BNE
1s
SCOPE

;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP

;POINTER TO DATA
:SET C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:BR _ ADD
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4
;PUT “EXPECTED” IN RS
;PUT "FOUND” IN R4
;:DATA CORRECT?
:BR IF YES
;ALU ERROR
:SH09=1?
sNEXT DATA
;sNEXT ADDRESS
;DONE YET?
;BR IF NO
sSCOPE THIS TEST

.EVEN

shbhbbdbhbdbbhbbhbbhbibbbtbhbts

TEST

124

sssddbdssdbsbbbbhhbbbbsbdhd

;#ALU TEST
;#TEST OF ALU FUNCTION 2A W/C WITH C BIT SET
s#ALU FUNCTION (A PLUS A PLUS C)
CODE=6
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

P
T T YT YT T

;
031436

012737

000124

001226

TST124: MO

TEST 124
#124,TSTNO

CZLmMC
MACRO v04.00
DMC11 ALV TESTS
031444
031452

012737
012737

031460
031462
031464
031470
031474
031476
031502
031504
031510
031516

104412
005000
012702
004737
035052

031522
031524

031526
031534
031540

031542
031544
031546
031550
031552
031556
031560
031562
031564
031566
031570
031572
031576
031600
031602
031605
031610

004737
035062
004737

042737

050037
104414
010000
042737
050037
104414
040540
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400
001
377
125

SEQ 109

27-JUN-85 13:16:37 PAGE 27-70

031612
031504

001216
001220

MOV
MOV

031602
034726

034762
035040
000017
031524
000017
031542

031524

031542

1s%:

2%:

3s:

000004

43:

001
253
125

MSTCLR
CLR
RO
MOV
#5%,.R2
JSR
PC,MEMLD
MEMDAT
JSR
PC,SPLD
SPLAT
JSR
PC,SETC
BIC
217,23
BIS
RO,2%
ROMCLK
010000
BIC
#17,3%
BIS
RO,3$
ROMCLK
040400!<6420>
ROMCLK
61224
MOVB
(R2),RS
MOVB
4(R1).R4
CMPB
R5.R4
4%
BEQ
EMT
15
SCoP1
INC
R2
INC
RO

CcMP

000010

377
253

5s%:

#TST125,NEXT
#13%,L0CK

BNE
SCOPE
.BYTE

#10,R0
1s

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
;SET C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sBR _ 2A W/C
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4

;PUT “EXPECTED” IN RS
;PUT "FOUND” IN R4
;DATA CORRECT?
:BR IF YES
;ALU ERROR
;SW09=17?
;NEXT DATA
;:NEXT ADDRESS
;DONE YET?
;BR IF NO
;SCOPE THIS TEST

.EVEN

shbsbsdbbbbtdbbbdtddsbtdbiis

TEST

125

ssdstsdbsbddsdbhbhdbbbibdss

s#ALU TEST
;#TEST OF ALU FUNCTION SUB WITH C BIT SET
:#ALU FUNCTION (A-B)
CODE=16
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

Y PP

TEST 125

’ ---------------

031612
031620
031626

012737
012737
012737

031634
031636
031640
031644
031650

104412
005000
012702
004737
035052

000125
031766
031660

031756
034726

001226
001216
001220

TST125: MOV

MOV

#125,TSTNO

#T5T7126 ,NEXT

MOV

#14,L0CK

MSTCLR
CLR
MOV
JSR
MEMDAT

RO
#5¢,R2
PC,MEMLD

;:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA

e verey

CZDMC

E
gl

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-71

DMC11 ALU TESTS
031652

031656

031660
031664
03167z
031676
031700
031702

031710
031714
031716
031720

031722

031724
031726
031732

004737

034762

004737
042737
050037
104414
010000
042737

035040
000017
031700

035062

050037
104414
040740
104414

000017,
031716

031716

1s:

24:

PC,SETC
#17,2%
RO,2$

sSET C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION

61224

000004

022700
001342
104400

000010

031764

125

000

104401

000
000

JSR
BIC
BIS
ROMCLK
010000
BIC

MOVB
MOVB
CMPB

001401
104015
005202
005200

;LOAD 8 WORDS OF SP

#17,3%
BIS
RO,3$
ROMCLK
040400!<16+20>
ROMCLK

061224

111205
116104
120504

PC,SPLD

SPDAT

3s:

031734
031736
031740
031742
031744
031746
031752
031754

031756
031761

031700

JSR

4%:

001
000

377
253

(R2),RS
4(R1).R4
R5,R4

;ADD ADDRESS TO INSTRUCTION
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;BR _ SuB
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4

;PUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
;DATA CORRECT?

BEQ
EMT

43
15

INC
INC

R2
RO

.BYTE

0,1,-1,0,0,253,125,0

SCOP1
CcMP
BNE
SCOPE

5s:

;POINTER TO DATA

;:BR IF YES
;:ALU ERROR

:SW09=1?

#10,R0
1

;NEXT DATA
;NEXT ADDRESS

;:DONE YET?
.iBR IF NO
:SCOPE THIS TEST

.EVEN

shbbdsbkdbbibbsbbitiitnidits

TEST

126

sissbshsssssbdbdbddbdbhihbss

;#ALU TEST
s#TEST OF ALU FUNCTION ADD W/C WITH C BIT SET
s#ALU FUNCTION CA PLUS B PLUS C)
CODE=01
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;*PERFORM THE FUNCTION, VERIFY THE RESULTS

;

T T

ITTT Ty rrrvrrrwrwrwrres

TEST 126

‘ ..............

031766
031774
032002

012737
012737
012737

032010
032012
032014
032020
032024
032026
032032
032034
032040
032046
032052
032054

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000

032056

042737

000126
032142
032034

001226
001216
001220

TST126: MOV
MOV
MOV

032132
034726

—

034762
035040
000017
032054

032054

000017

032072

1$:

2%:

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR
BIC
BIS
ROMCLK
010000
BIC

€126,TSTNO
#TST127,NEXT
#14,L0CK

RO
#5%,R2
PC.MEMLD
PC,SPLD
PC,SETC
#17,2¢
RO,2$
#17,3¢

:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;MEM + SP ADDRESS
sPOINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
:SET C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCT
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION

CZDMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-72

paken

DMC11 ALV TESTS
032064
032070

032072

032074

050037
104414

040420
061224

032102
032106
032110

116104
120504
001401

032112
032114

032116

3s:

104414

032076

032100

032072

111205

45:

005202

005200
022700
001342

000010

032135

377

253

032140

104400
001
000

000
125

000

5%:

;BR _ ADD W/C

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

(R2),RS5

MOVB
CHMPB
BEQ

104015
104401

;ADD ADDRESS TO INSTRUCTION
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304

ROMCLK

MOVB

000004

RO,3s

040400!<01420>
61224

032120
032122
032126

032130
032132

BIS
ROMCLK

EMT
SCoP1
INC
INC
CMP
BNE
SCOPE
.BYTE

;:MOVE BR TO PORT4

;PUT "EXPECTED” IN RS

4(R1),.R4
R5,.R4
43

sPUT “FOUND” IN R4
;DATA CORRECT?
;BR IF YES

;NEXT DATA

RO
#10,R0
1s

:ALU ERROR
;SW09=1?

:NEXT ADDRESS
;DONE YET?
;:BR IF NO
:SCOPE THIS TEST
1,0,0,-1,253,0,0,125

.EVEN

ihhkkbksdbbbbhbbbddhbbdibhbhid

TEST

127

sstbsddbbbhdhbbhbhbbbhdbdhs

;#ALU TEST
;#TEST OF ALU FUNCTION SUB W/C WITH C BIT SET
;#ALU FUNCTION (A-B-C)
CODE=2
:#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
s#PERFORM THE FUNCTION, VERIFY THE RESULTS

;

Rty

Y Y

TS T

ITTTITITIYrY

TEST 127

‘ ..............

032142

012737

032156

012737

032150

032164
032166
032170
032174
032200
032202
032206
032210
032214
032222
032226
032230
032232
032240

032244
032246
032250
032252
032254
032256
032262

012737
104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737

050037

104414
040440
104414
061224
111205
116104
120504

000127

001226

TST127: MOV

032210

001220

MOV

032316

001216

MOV

032306
034726
034762
035040
000017
032230
000017
032246

032230

032246

1s:

2%:

BIS

3s:

000004

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR
BIC
BIS
ROMCLK
010000
BIC

#127,TSTNO

#TST130, NEXT

#14,L0CK
RO
#58,.R2
PC,MEMLD
PC,SPLD
PC,SETC
217,28
RO,2%
#17,38
RO,3$

ROMCLK
040400 <2420>
ROMCLK
61224
MOVB
(R2),R5
MOVB
4(R1).R4
CcMPB
R5.R4

;:R1 CONTAINS BASE DMC1i ADDRESS
:MASTER CLEAR DMC11i
;MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;:LOAD 8 WORDS OF SP
;POINTER TO DATA
$SET C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;sLOAD MAR
sCLEAR ADDRESS OF INSTRUCTION

;ADD ADDRESS TO INSTRUCTION

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sBR _ SUB W/C
;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE BR TO PORT4
sPUT “EXPECTED” IN RS
sPUT “FOUND” IN R4
;DATA CORRECT?

CZDMC
MACRO V04.00
DMC11 ALV TESTS

032264
032266
032270
032272

001401
104015
104401
005202

032274
032276
032302

005200
022700
001342

000010

032306

000

001

032304

032311
032314

104400

000
125

SEQ 112

27-JUN-85 13:16:37 PAGE 27-73

000
000

377

253

Ss:

BEQ
EMT
SCoP1
INC

43
15

:BR IF YES
;ALU ERROR
;SH09=17
;NEXT DATA

INC
CHP
BNE

RO
#10,RO
1s

.BYTE

9,1,-1,0,0,253,125,0

SCOPE

;NEXT ADDRESS
;DONE YET?
:BR IF NO
;SCOPE THIS TEST

.EVEN

100

jhbkddbdbbdbbhdhbhkdhbdbhhhik

TEST

130

sskbnbbbbbbbbhbbhbbbbhhbbss

;#ALU TEST
;#TEST OF ALU FUNCTION INC A WITH C BIT SET
;#ALU FUNCTION (A PLUS 1)
CODE=3
;*LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA

;#PERFORM THE FUNCTION, VERIFY THE RESULTS
R

032316
032324
032332

012737
012737
012737

032340
032342
032344
032350
032354
032356
032362
032364
032370
032376
032402
032404
032406
032414
032420
032422
032424
032426
032430
032432
032436
032440
032442
032444
032446
032450
032452

104412
005000
012702
004737
035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
104414
040460
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700

032456
032460

001342
104400

000130
032472
032364

001226
001216
001220

034762
035040
000017
032404
000017
032422

032404

032422

1s:

2%:

3s:

000004

43
000010

TTITIITTTITITIY Y

--------------

TST130: MOV
MOV
MOV

032462
034726

TEST 130

;
z

R T

#130,TSTNO
#TST131,NEXT
#1$,L0CK

MSTCLR
CLR
RO
MOV
#5%,.R2
JSR
PC.MEMLD
MEMDAT
JSR
PC,SPLD
SPDAT
JSR
PC,SETC
BIC
#17,2%
BIS
RO,.2%
ROMCLK
010000
BIC
£17,3¢
8IS
RO,3$
ROMCLK
040400 <3420>
ROMCLK
61224
MOVB
(R2).RS
MOVB
4(R1),R4
CMPB
RS,R4
BEQ
4a$
EMT
15
SCoP1
INC
R2
INC
RO
CMP
#10,R0

BNE
SCOPE

;:R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
;MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;:LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
;SET C BIT!
sCLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;:CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sBR _ INC A
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE BR TO PORT4
;PUT “EXPECTED” IN RS
;PUT “FOUND” IN R4
;DATA CORRECT?
1BR IF YES
;ALU ERROR
;SW09=17?
sNEXT DATA
;NEXT ADDRESS
;DONE YET?
;BR IF NO
;SCOPE THIS TEST

CZDMC
MACRO V04.00
DMC11 ALU TESTS
032462
032465
032470

001
000
253

SEQ 113

27-JUN-85 13:16:37 PAGE 27-74

001
126
253

000
126

Ss:

.BYTE

1,1,0,0,126,126,253,253

.EVEN

101

shbdbbbbsbbbdbtbbttbbtbbdids

TEST

131

stsssssdssbhbbbbbbsbsdtbbss

;#ALU TEST
s#TEST OF ALU FUNCTION 2A WITH C BIT SET
;#ALU FUNCTION (A PLUS A)
CODE=5
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

P
P P PP PP,

;

TEST 131

ey
e

032472

012737
012737

032514
032516
032520
032524
032530
032532
032536
032540
032544
032552
032556
032560
032562
032570
032574
032576
032600
032602
032604

104412
005000
012702
004737
035052
004737
035062
004737
742737
.0037
104414
010000
042737
050037
104414
040520
104414
061224
111205

032606
032612
032614
032616
032620

032622
032624

032626
032632
032634
032636
032641
032644
102

012737

032500
032506

000131

032646
032540

TST131:

000017
032576

000004

022700
001342
104400
000
376
124

000010

032560

032576

2s:

sADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:LOAD MAR

38:

BIS
RO,3$
ROMCLK
040400 <5420>

:ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
BR _ 2A
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE BR TO PORT4

BIC

ROMCLK
61224
MOVB
MOVB
CMPB

376
252

sR1 CONTAINS BASE DMC11 ADDRESS

BIS
RO,2s
ROMCLK
010000

4%:

000
252
124

#131,TSTNO
#TST132, NEXT
#1$,L0CK

1%:

034762
035040
000017
032560

MOV
MOV
MOV

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR
SPDAT
JSR

032636
034726

116104
120504
001401
104015
104401

005202
005200

001226
001216
001220

S5$:

BEQ
EMT
SCOP1
INC
INC
cHP
BNE
SCOPE
.BYTE

RO
#53,R2
PC.MEMLD
PC.SPLD

PC,SETC
017,28

017,38

(R2),RS
4(R1),R4
RS,R4

43
15

R2
RO
#10,R0
1

sMASTER CLEAR DMC11
iMEM + SP ADDRESS
:POINTER TO CORRECT DATA
:LOAD 8 WORDS OF MAIN MEMORY
:POINTER TO DATA
:LOAD 8 WORDS OF SP
:POINTER TO DATA
:SET C BIT!

:CLEAR ADDRESS FIELD OF INSTRUCTION

;CLEAR ADDRESS OF INSTRUCTION

iPUT “EXPECTED” IN RS
sPUT “FOUND* IN R4
sDATA CORRECT?

iBR IF YES
sALU ERROR
15W09=1?
sNEXT DATA
sNEXT ADDRESS
:DONE_YET?
:BR IF NO
:SCOPE THIS TEST

0,0,376,376,252,252,124,124

.EVEN
jdkdddbddsbkbbbsbtbissbsdis

;#ALU TEST

hoe

TEST

132

ssssssstsbdbdbbbbbbbsbbbins

CZOMC

SEQ

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-75

OMC11 ALU TESTS

;#TEST OF ALU FUNCTION A PLUS C WITH C BIT SET
;#ALU FUNCTION (A PLUS C)
CODE=4
;#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

PR
P PP PPN

;
032646

012737
012737

032670

104412

032672

032674
032/00
032704
032706
032712
032714

032720
032726

032732
032734

032736

032744
032750
032752
032754
032756
032760
032762
032766
032770
032772
032774
032776
033000
033002
033006
033010
033012
033015
033020
103

012737

032654
032662

005000

012702
004737
035052
004737
035062
004737

042737
050037

104414
010000

042737

050037
104414
040500
104414
061224
111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400
001
000
253

000132

033022
032714

001226

001216
001220

TEST 132

TST132: MOV

#132,TSTNO

MOV
MOV

#TST133,NEXT
#1%,L0CK

MSTCLR
CLR

033012
034726

1%:

MOV
JSR
MEMDAT
JSR
SPDAT
JSR

2%:

ROMCLK
010000

034762
035040
000017
032734
000017

032752

032734

032752

3s:

000004

4s:
000010
001

126

253

000

126

5¢:

;R1 CONTAINS BASE DMC11 ADDRESS
;MASTER CLEAR DMC11
;MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;:LOAD 8 WORDS OF SP
;POINTER TO DATA
:SET C BIT!
:CLEAR ADDRESS FIELD OF INSTRUCTION
sADD ADDRESS TO INSTRUCTION

#5%,R2
PC,MEMLD
PC,SPLD
PC,SETC
917,24
RO,2$

BIC
BIS
BIC

;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR

#17,3%

;CLEAR ADDRESS OF INSTRUCTION

BIS
RO,3$
sADD ADDRESS TO INSTRUCTION
ROMCLK
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
040400!<4+20>
;BR _ A PLUS C
ROMCLK
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
61224
;MOVE BR TO PORT4
MOVB
(R2),RS
;PUT “EXPECTED” IN RS
MOVB
4(R1),R4
:PUT “FOUND” IN R4
CMPB
RS,R4
:DATA CORRECT?
BEQ
44
:BR IF YES
EMT
15
:ALU ERROR
SCOP1
:SW09=1?
INC
R2
sNEXT DATA
INC
RO
sNEXT ADDRESS
CMP
#10,R0
;DONE YET?
BNE
1s
:BR IF NO
SCOPE
:SCOPE THIS TEST
.BYTE
1,1.,0,0,126,126,253,253

.EVEN
;hhdbbdbbbdbiddtddtsdbidbtss

TEST

133

2issssssddbssdbsbbdtbdtsdtssd

;#ALU TEST
+#TEST OF ALU FUNCTION 2'S COMP SUB WITH C BIT SET
:#ALU FUNCTION (A-B-1)
CODE=17
:#LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS
RS

TEST 133

PRy

YYYTTITITIY ]

.5 114

CZOMC

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-76

and

DMC11 ALU TESTS

033022
033030
033036

012737
012737
012737

033044
033046
033050
033054
033060
033062

104412
005000
012702
004737
035052
004737

033066
033070
033074
033102
033106
033110

033112
033120

033124
033126
033130
033132
033134
033136
033142
033144
033146
033150
033152
033154
033156
033162

033164
033166

033171
033174

035062
004737
042737
050037
104414
010000

042737
050037

104414
040760
104414

000133
033176
033070

001226
001216
001220

TST133: MOV
MOV
MOV

MSTCLR
CLR
MOV
JSR
MEMDAT
JSR

033166
034726
034762

035040
000017
033110
000017
033126

033110

033126

1%:

24:

3s:

061224

111205
116104
120504
001401
104015
104401
005202
005200
022700
001342
104400

377

377
124

000004

43:

000010

000
377
377

€133,TSTNO
#TST134 ,NEXT
£1$,L0CK

376

252

5%:

SPDAT
JSR
BIC
BIS
ROMCLK
010000

BIC
BIS

RO
#5% ,R2
PC,.MEMLD
PC,SPLD

PC,SETC
#17,2%
RO,2%
#17,3%
RO,3$

ROMCLK
040400!<17420>
ROMCLK
61224
MOVB
(R2),RS
MOVB
4(R1),.R4
CMPB
R5.R4
BEQ
4%
EMT
15
SCOP1
INC
R2
INC
RO
CHP
#10,R0
BNE
1s

SCOPE
.BYTE

;:R1 CONTAINS BASE DMC11 ADDRESS
;:MASTER CLEAR DMC11
:MEM + SP ADDRESS
;POINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY
;POINTER TO DATA
;LOAD 8 WORDS OF SP

;POINTER TO DATA
;SET C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION

;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:BR _ 2'S COMP SuB
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4
;PUT “EXPECTED” IN RS
:PUT “FOUND” IN R4
;:DATA CORRECT?
:BR IF YES
:ALU ERROR
:SW09=17?
sNEXT DATA
sNEXT ADDRESS
:DONE YET?
;:BR IF NO

;SCOPE THIS TEST
-1,0,376,-1,-1,252,124,-1

.EVEN

104

iSasssbbbbbbsbsttbtttbiitiis

TEST

134

ssssdsssssssdssssssiststsdss

s#ALU TEST
s#TEST OF ALU FUNCTION DEC A WITH C BIT SET
:#ALU FUNCTION (A-1)
CODE=7
:4LOAD MAIN MEM AND SP WITH 8 WORDS OF DATA
;#PERFORM THE FUNCTION, VERIFY THE RESULTS

$:88888588 058004808882 8408848 8588088800448 0 0440000000000 00R400404

s
0

033176

012737

033220
033222
033224
033230

104412
005000
012702
004737

033204
033212

012737
012737

000134

033352
033244

033342
034726

001226

001216
001220

TEST 134
o

TST134: MOV

MOV
MOV

MSTCLR
CLR
MOV
JSR

9134 ,TSTNO

#TST135,NEXT
#1%,L0CK
RO

454 ,R2
PC,MEMLD

sR1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sMEM » SP ADDRESS
sPOINTER TO CORRECT DATA
;LOAD 8 WORDS OF MAIN MEMORY

s v —— — e — J

CZDMC
MACRO V04.00
DMC11 ALV TESTS

033234
033236
033242
033244
033250
033256
033262
033264
033266
033274

033300

033302
033304

033306
033310
033312
033316
033320
033322
033324
033326
033330
033332
033336
033340
033342

033345

033350

035052
004737
035062
004737
042737
050037
104414
010000
042737
050037
104414
040560
104414
061224
111205

116104
120504
001401
104015
104401
005202
005200

022700

001342
104400
377
376
251

SEQ 116

27-JUN-85 13:16:37 PAGE 27-77

034762
035040
000017
033264

000017
033302

033264

033302

1s:

2%:

3s:

000004

4%:

251

B8IC

BIS
ROMCLK

376
124

5%:

PC,SPLD
PC,SETC

#17,2%

RO,2$

010000
BIC
#17,38
BIS
RO,3$
ROMCLK
040400!<7+20>
ROMCLK
61224
MOVB
(R2),RS5
MOVB
4(R1).R4
CMPB
R5,R4
BEQ
4%
EMT
15
SCOP1
INC
R2
INC
RO

CcHP

000010

377
124

MEMDAT
JSR
SPDAT
JSR

BNE
SCOPE
.BYTE

#10,R0
1s

sPOINTER TO DATA
;LOAD 8 WORDS OF SP
;POINTER TO DATA
:SET C BIT!
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;LOAD MAR
;CLEAR ADDRESS OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;BR _ DEC A
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOVE BR TO PORT4
;PUT "EXPECTED” IN RS
;PUT "FOUND” IN R4
;DATA CORRECT?

:BR IF YES
:ALU ERROR
:SW09=1?
:NEXT DATA
sNEXT ADDRESS
;DONE YET?
:BR IF NO
:SCOPE THIS TEST

-1,-1,376,376,124,124,251,251

.EVEN

105

jhbdssdsbbdbsdbtddtisttsddss

TEST

135

ssssssstsssssdsassssdsssdssd

;#TEST OF PROGRAM CLOCK BIT
3#D0 A MASTER CLEAR, WRITE THE PROGRAM CLOCK BIT TO A ONE,
+#VERIFY THAT IT CLEARS, AND THEN SETS SOME TIME LATER

033352

012737
012737

033366

104412
005037
005037
012702
012761
152761
012761
152761
012761
152761
142761
016104
005005
120504
001401

033360
033370

033374
033400
033404
033412
033420
033426
033434

033442
033450
033456
033462
033464

033466

000135
033544

001226
001216

001416
001246
000011
121111
000003
121224
000003

000001

000001
000001

;

TEST 135

TST135: MOV
MOV

1¢:

MSTCLR
CLR
CLR
MOV
MOV
BISB
MOV
8ISB
MOV
BISB
81CB
MOV
CLR
CMPB
BEQ

#135,TSTNO
@TST136,NEXT
TEMP

TEMPL
€11,R2
#20,4(R1)
#8IT1,1(R1)

#121111,6(R1)

Y YT T Y

;R1 CONTAINS BASE DMC11 ADDRESS
sMASTER CLEAR DMC11
sPREPARE FOR
sDELAY
sSAVE FOR TYPEOUT
;LOAD PORT 4

:SET ROMI

sSEL6 _ INSTRUCTION
#BIT1!81I70,1(R1);SET CLOCK BIT
#121224,6(R1)
sLOAD NEXT INSTRUCTION

#B8IT1!BIT0,1(R1);READ CLOCK BIT
#8IT1!8IT0,1(R1);CLEAR MAINT BITS
4(R1).R4
sPUT “FOUND” IN R4
RS
sPUT “EXPECTED” IN RS
RS.R4
:IS PGM CLOCK CLEAR?
2

TV Prey

CZOMC
MACRO V04.00
DMC11 ALV TESTS

106

033470
033472
033472
033474
033476
033504
033506
033514
033520
033526
033530
033534
033540
033542

104016

104414
121224
122761
001416
062737
005537

022737
001361
012705
016104
104016
104400

SEQ 117

27-JUN-85 13:16:37 PAGE 27-78

2%:

000020
000001
001246

001416
001246

000020
3s:

EMT

ROMCLK
121224
CHPB
BEQ
ADD
ADC
CcHP
BNE
MOV
MOV
EMT
SCOPE

;ERROR, PGM CLOCK IS NOT CLEAR

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;PORT4 _LU11
;IS PGM CLOCK SET?
:BR IF YES
s INCREMENT DELAY
s INCREMENT DELAY
;IS DELAY DONE
:BR IF NO
;PUT "EXPECTED” IN RS
sPUT “FOUND” IN R4
;ERROR PGM CLOCK NOT SET
:SCOPE THIS TEST

#20,4(R1)
3s
#1,TEMP
TEMP1

96, TEMP1

24
920,R5
4(R1).R4
16

jhdbdkbbbbsssbtdtsdbtsiitits

TEST

136

sssssnsssssssssdtssssssssss

:#FORCE POMWER FAIL TEST
+#SET FORCE POWER FAIL BIT VERIFY THAT PROCESSOR TRAPS TO 24
:#GOING DOWN AND COMING UP. VERIFY ALSO THAT BUS INIT WAS
s#BLOCKED FROM GETTING TO THE DMC DURING THS POWER FAIL
s#THIS TEST MAY HANG ON SOME PROCESSORS IF AN M9301 IS PRESENT.
:#TO AVOID HANGING SW02 (POWER ON REBOOT ENABLE) ON THE M9301
+#MUST BE IN THE OFF POSITION. THIS TEST WILL ALSO FAIL IF THE
;#CPU POMER FAIL VECTOR IS SET TO ANY LOCATION OTHER THAN 24.
s#IF THIS TEST HANGS OR FAILS DUE TO EITHER REASON ABOVE THE

;#FOLLOWING PATCH MAY BE INSTALLED TO SKIP THIS TEST:

LOC 33362

Fi8 480 040

s
033544
033552

012737
012737

033560
033562
033566
033572

104412
005037
013746
012737
012761
012711
012761
012711
005237
001375
104017
000426
012737
010637
000000
000000
013706
022626
012637
022737
001406

033600

033606
033612
033620
033624
033630
033632
033634
033636

000136
033766
001416
000024
033636

001226
001216

TST136: MOV

MOV

MSTCLR
CLR
MOV
MOV

033652

000024

13:

#136,TSTNO
#TST137,NEXT

sR1 CONTAINS BASE DMC11 ADDRESS

+MASTER CLEAR DMC11
sPREPARE FOR DELAY
;STORE POWER FAIL ADDRESS
+SET UP FOR FORCE POWER FAIL

INC
BNE

sLOAD PORT4
+SET ROMI
;LOAD INSTRUCTION
;CLOCK INSTRUCTION
sWAIT FOR POWER FAIL
18R _IF DELAY NOT DONE

MOV
MOV

033,0024
SP,24

sPOMER UP ADDRESS
1STORE STACK

MOV
POP2SP
MOV

2¢,5P

BEQ

gfl

033654
033652

00 004000000000 004440

TEMP
8024,-(SP)
14,0024
#2,4(R1)
#8179,(R1)
€121111,6(R1)
#8I79:81I78,(R1)
TEMP
53

MOV
MOV
MOV
MOV

001000
121111
001400
001416

S8 33736

0000004005008

TEST 136

000024

WAS 33544

0008080000000 04

rLT

CcHP

(SP)+,0024
O.PFAIL,8024

sERROR, NO POMER FAIL

sHWAIT FOR POMER UP SEQUENCE

sRESTORE STACK
sPOP STACK TWICE
sRESTORE TRUE POMER FAIL ADDRESS
+IS IT CORRECT?
iBR IF YES

——

R S TR AS T R

CZOMC
MACRO VO4.00
OMC11 ALU TESTS
033676
033700
033706
033712
033716
033720
033724
033726
073730
033732

107

104017
012737
012706
005737
001407
012701

005000
005300
001276
005301
001373
013701
012711
012705

033734
033736
033742
033746
033752
033756
033760
033762

016104
020504
001401
104025

033764

104400

SEQ 118

27-JUN-85 13:16:37 PAGE 27-79

005336
001200
000042

000024

EM7
MOV
MOV
157

17
@.PFAIL,3024
#STACK ,SP
8042

MOV

€140, R1

BEQ

000140

CLR
DEC
BNE
DEC
BNE
MOV
MOV
MoV

001404
003000
121111
000004

MOV
cHP
BEQ
EMT

;ERROR, STACK IS INCORRECT
sRESTORE TRUE POWER FAIL ADDRESS
sRESTORE STACK
s CHECK FOR ACT-11 OR DDP

RO
; DELAY TO WAIT FOR RKOS TO BECOME
RO
;s READY AFTER POMWER FAIL
8s
R1
€3
DMCSR,R1
sRESTORE ADDRESS. R1 CLOBBERED ON 11/84 PWRFAIL
#BIT9!BIT10,(R1);SEL6 = MAINT IR
#121111,R5
;RS = EXPECTED

4(R1),R4
RS5.R4
.+4
25

SCOPE

;R4 = FOUND
sMAINT IR SHOULD = 12111
:BR IF 0K
:IF = O THEN BUS INIT WAS
sNOT BLOCKED FROM CLEARING
sTHE DMC-11

;SCOPE THIS TEST

8844854404004 00000000050028

;#MICRO-PROCESSOR NOISE TEST

TEST

137

sesssssidssbbbbbbbbbbbbbddss

s#WRITE ALL ZERO'S THEN ALL ONE‘'S THEN A DATA PATTERN

:#T0 THE IBUS+ AND IBUS REGISTERS AND TO THE SP AND MAIN MEM
s#THEN GO BACK AND READ THE DATA PATERNS TO VERIFY THAT
s#READING AND WRITING OF OTHER LOCATIONS AND REGISTERS
s#DID NOT CHANGE THE DATA.
$:80888

s
033766
033774

012737
012737

034002
034004
034006
034014

104412
005002
042737
156237
116261
104414
121100
005202
022702
001361
005002
042737
042737
042737
050237
050237
050237
105061
104414
122100

034022
034030
034032
034034
034036
034042
034044
034046
034054
034062
034070
034074

034100
034104
034110
034112

000137
003364

000017
034626
034634

001226
001216

034032
034032
000004

MOV

1s:

000005

000017
034112
034124
034134
000004

034112
034124
034134

MSTCLR
CLR
BIC

217,28

iR1 CONTAINS BASE DMC11 ADDRESS

sMASTER CLEAR DMC11
;R2 IS INDEX REGISTER

;CLEAR ADDRESS FIELD

B8ISB
MOVB
ROMCLK
121100
INC
CcHP
BNE
CLR

R2
#5,R2
1s
R2

;ADD IBUS+ REG ADDRESS TO INSTRUCTION
;LOAD PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sWRITE IBUS+ REGISTER
sINC INDEX REGISTER
;:DONE YET?
;B8R IF NO
sR2 IS IBUS REGISTER ADDRESS

BIS

R2,4%

sADD IBUS REG ADDRESS TO INSTRUCTION

CLRB
ROMCLK
122100

4(R1)

sCLEAR PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sWRITE O TO IBUS REG

BIC
BIC
BIC

BIS
BIS

4s:

bbbkt ibbhhhihk

TEST 137

TST137: MOV

2s:

000017
000017

5044804554050 0880 0800000000 kd kbbb bd bbb

308(R2),2¢
313(R2),4(R1)

217.4%
#17,58
217,63

R2,5%
R2,6%

sCLEAR ADDRESS FIELD OF INSTRUCTIONS

MACRO V04.00
CZ0MC
DMC11 ALV TESTS

034114
034122
034124
034126
034132
034134
034136
034140
034144
034146
034150
034156
034164
034172
034176
034202
034206
034212
034214
034216
034224
034226
024230
034234

034236
034240

034242
034246
034250
034252
034254

034256
034262
034264
034266
034274
034276
034300
034304
034306
034310
034312
034316

112761
104414
122100
110261
104414
122100
005202
022702
001340
005002
042737
042737
042737
050237
050237
050237
105061
104414
123100
112761
104414
123100
110261
104414

123100
005202

022702
001340
005002
104414
010000

105061
104414
122500
112761
104414
122500
110261
104414
136500
005202
022702
001357

SEQ 119

27-JUN-85 13:16:37 PAGE 27-80

000377

000004

Ss:

000004

6%:
000010
000017
000017
000017
034214
034226
034236
000004
000377

034214
034226
034236

000004

7s:

8s:
9s:

000004

10s:
000020

000004
000377

11s:
000004

000004

000400

MOVB
ROMCLK
122100
MOVB
ROMCLK
122100
INC
cMP
BNE
CLR
BIC
8IC

BIC
BIS
BIS
BIS
CLRB
ROMCLK
123100
MOVB
ROMCLK

#377.4(R1)

R2.4(R1)

17,98
#17,10%
R2,8$
R2,9$
R2,10$
4(R1)

#377,4(R1)

123100

MOVB
ROMCLK
123100
INC
CcMP
BNE
CLR
ROMCLK
010000
CLRB
ROMCLK
122500
Move
ROMCLK
122500
MOVB
ROMCLK
136500
INC
cHpP
BNE

R2,4(R1)

£20,R2
7%
R2

4(R1)

#377,4(R1)

R2,4(R1)

#400,R2
118

;LOAD PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;WRITE ALL ONES TO IBUS REG
;LOAD PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;WRITE ITS OWN ADDRESS TO IBUS REG
sNEXT ADDRESS
:DONE YET?
:BR IF NO
;START AT SP ADDRESS 0
;CLEAR ADDRESS FIELD

;ADD ADDRESS TO INSTRUCTION

;CLEAR PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK
;WRITE ZERO TO SP
;:LOAD PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK
sWRITE ALL ONES TO SP
;LOAD PORTA
sNEXT WCRD IS INSTRUCTION, ROMCLK
;WRITE SP ADDRESS TO ITSELF
sNEXT SP ADDRESS
;DONE YET?
:BR IF NO
;R2 = MAIN MEM ADDRESS
‘:E:T HgRD IS INSTRUCTION, ROMCLK
H

PC=5304

PC=5304
PC=5304

PC=5304

;CLEAR PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;WRITE ZEROS TO MEM
;LOAD PORT4
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sWRITE ONES TO MEM
;LOAD PORTS

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;WRITE TO MEM IT OWN ADDRESS
;NEXT MEM ADDRESS
;DONE YET?
:BR IF NO

;NOW GO BACK AND READ EVERYTHING
034320
034322
034324
034332
034334
034336
034340
034342
034350
034354
034356

104414
010000
032737
001402
104414
004000
005000
042737
116002
010203

006303

100000

001366

000360
034626

034400

123%:

ROMCLK
010000
BIT
BEQ
ROMCLK
4000
CLR
BIC
MOV
MOV
ASL

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304

#BIT15,STAT1
.+6
RO
360,133

30$(RO),R2
R2,R3
R3

sMAR_O

;:DMC?
sBR IF YES
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMAR HI _ O (KMC ONLY)
;RO IS INDEX REGISTER
;CLEAR ADDRESS FIELD
;R2 = IBUS+ ADDRESS
;PUT IBUS+ ADDRESS IN R3
;SHIFT ADDRESS TOC BITS 4-7

CZOMC
MACRO V04.00
DMC11 ALV TESTS
034360
034362
034364
034366
034372

034376
034400
034402

034406
034410
034412
034414
034416
034422
034424

034426
034434
034436
034440
024442
034444
034446
034452
024454
034456
034460
034464
034466

034470
034472
034474
034500
034502
034504
034512
034516
034520
034522
034524
034526
034530
034534
034536
034540
034542
034544
034550
034552
034554
034556
034560
034566
034570
034572
034574
034576
034600

006303
006303
006303
050337 034400
034634
116005
104414
121004
016104
000004
120504
001401
104004
005200
022700
000005
001347
005002
042737
000360
010203
006303
006303
006303
006303
050337 034456
010205
104414
021004
000004
016104

120504
001401
104005
005202

022702
001352
005002
042737
050237

104414
040600
010205
104414

061224
016104
120504
001401
104007
005202
022702
001355

005002
104414
010000
032737

001402

ASL
ASL
ASL

13s:

034456

14s:

15s:

000010
000017
034520

034520

16%:
17s:

000004

000020

100000

001366

104414

004000
010205
104414
055224

SEQ 120

27-JUN-85 13:16:37 PAGE 27-81

18§:

BIS
MOVB
ROMCLK
121004
MOV
CMPB
BEQ
EMT
INC
cMP
BNE
CLR
BIC
MOV
ASL
ASL
ASL
ASL
BIS
MOV
ROMCLK
021004
MOV
CMPB
BEQ
EMT
INC

cMP
BNE
CLR
BIC
BIS
ROMCLK
040600
MOV
ROMCLK
061224
MOV
CMPB
BEQ
EMT
INC
CMP
BNE
CLR
ROMCLK
010000
BIT
BEQ
ROMCLK

R3
R3
R3
R3,13s
31$(RO).R5

RO
#5,R0
12%
R2
#360,15$
R2,R3
R3
R3
R3
R3
R3,15$
R2,.R5

#10,R2
14

MOV
ROMCLK
055224

4(R1).R4
R5,.R4
.+4
7

#20,R2

164
R2

#BIT15,S5TATL

R2,R5

"EXPECTED”

;R4 =

"FOUND"”

;IBUS CONTENTS 0K?
;:BR IF YES
;IBUS DATA ERROR
:NEXT IBUS REGISTER
;DONE YET?
:BR IF NO
;R2 = SP ADDRESS

;CLEAR ADRESS FIELD OF INSTRUCTION

R2,R5

4000

;RS =

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;PORT4 _ IBUS REG

S
R2

.+6

“FOUND*

;ADD ADDRESS TO INSTUCTION

4(R1).R4
R5.R4
.+4

#17,17¢

;R4 =

;IBUS# CONTENTS OK?
:BR IF YES
;IBUS* DATA ERROR
;INC COUNTER
;DONE YET?
;BR IF NO
;R2 = IBUS REG ADDRESS
;CLEAR ADDRESS FIELD OF INSTRUCTION
;:R3 = IBUS ADDRESS
;SHIFT ADDRESS TO BITS 4-7

R2,17¢

"EXPECTED”

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;PORT4 _ IBUS* REGISTER

4(R1),R4
R5.R4
.+4

;ADL ADDRESS TO INSTRUCTION

;RS =

;ADD ADDRESS TO INSTRUCTION
S:EXT ggflb IS INSTRUCTION, ROMCLK PC=5304

iBR

;RS = "EXPECTED”

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:PORT4 _ BR

;R4 =

"FOUND"

:SP CONTENTS 0K?

sBR IF YES

;SP DATA ERROR
;sNEXT SP LOCATION
;sDONE YET?
;:BR IF NO
;R2 = MEMORY ADDRESS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMAR _ O
;DMC?
sBR IF YES
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMAR HI _ O (KMC ONLY)

;RS = “EXPECTED”

;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;PORT4 _ MAIN MEM

CZDMC
MACRO V04.00
OMC11 ALU TESTS

034602
034606
034610
034612
034614
034616
034622
034624

034626
034631
034634
034637
110
i11
112
113
114
115 034642
116
117
118 034642
119 034646
120 034652
121 034656
122 034662
123
124
125 034664
126

127
128
129 034664
130 034666
131 034670
132 034674
133 034702
134 034706
135 034710
136 034712
137 034714
138 034720
139 034722

140 034724
141
142
143 034726
144
145
146
147 034726
148 034730
149 034734
150 034740
151 034742
152 034744

016104
120504
001401
104013
005202
022702
001364
104400

SEQ 121

27-JUN-85 13:16:37 PAGE 27-82

000004

MOV
CMPB
BEQ
EMT
INC
cMP
BNE
SCOPE

000400

000
005

002
010

003

30s:

001
006

003
010

004

313:

.EVEN

4(R1),.R4
RS5.R4
.+4

13
R2

#400,R2
18¢

.BYTE

0,2,3,5,10

.BYTE

1,3.4,6,10

iR4 =

"FOUND”

sMAIN MEM CONTENTS OK?
;:BR IF YES
;MAIN MEM DATA ERROR
sNEXT MEM ADDRESS
:DONE YET?
;BR IF NO

;SCOPE THIS TEST

.EVEN

s SUBROUTINES
S

SETVEC
012577
012577
112577
112577
000205

: sTHIS SUBROUTINE LOADS THE VECTORS AND VECTOR LEVELS

144526
144526
144520
144520

MOV
MOV
MOVB
MOvVB
RTS

NPRSET :

010246
005002
112561
042737
050237
104414
122100
005202
022702
001363
012602
000205

000004
000017
034710

034710

1$:

2s:
000010

MEMLD:

013605
062746
012704
104414
010000
112577

000002
000010
144442

1$:

(R5)+,8DMRVEC
(R5)+,8DMTVEC
(R5)+,8DMRLVL
(R5)+,8DMTLVL

:LOAD BASE VECTOR
;LOAD VECTOR + 2
;LOAD VECTOR + 4
;LOAD VECTOR + 6
sRETURN

s THIS SUBROUTINE LOADS IBUS REGISTERS 0-7
sWITH NPR INFORMATION (INBA, OUTBA, OUT DATA)
MOV
CLR
Move
BIC
BIS
ROMCLK
122100
INC
CcMP
BNE
MOV
RTS

R2,-(SP)
R2
(RS)+,4(R1)
#17,2%
R2,2%
R2

O%O.RZ
1

(SP)+,R2
R5

sSAVE R2
;START AT IBUS REG 0O
;LOAD PORT4
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE PORT4 TO IBUS REG
sNEXT ADDRESS
sALL DONE?
;BR IF NO

;RESTORE R2
sRETURN

; THIS SUBROUTINE LOADS THE FIRST 8 LOCATIONS OF MAIN
MOV
ADD
MOV
ROMCLK
010000
Move

RS .
8(SP)+
#10,.R4

(R5)+,3DMPO4

;PUT POINTER TO DATA IN RS
sADJUST STACK
;D0 8 LOADS
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMAR < 0
;LOAD PORTS

CZDMC
MACRO V04.00
DMC11 ALV TESTS
153 034750
154 034752
155 034754
156 034756
157 034760

158

104414

ROMCLK
136500
DEC
BNE
RTS

136500
005304
001372

000207

159
162 034762
163
164

165
166 034762
167 034764
168 034770
169 034772
170 034776
171 035004
172 035010
173 035012
174 035014

175 035016
176 035022
177 035024
178
179
180 035026
181
182
183 035026
184 035030
185 035032
186 035034
187 035036
188
189
190 035040
191
192
193 035040
194 035042
195 035044
196 035046
197 035050
198
199
200 035052
035055
035060
201 035062
035065
035070
202
207 035072
208 035137
209 035201
210 035227
€1l 03527

SPLD:

013605
062746
005004
112577
042737

050437
104414
123100
005204
022704

001363
000207

000002
144414
000017
035012

035012

1s:

2%:

000010

CLRC:
104414
010000
104414
040400
000207

104414

377
125
252

000
377
252

125
252

377
377
377
377
377

125
125
115
115
102

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;MOV DATA TO MEM, AUTO INC MAR
;DECREMENT COUNT
;BR IF NOT DONE
;RETURN

;THIS SUBROUTINE LOADS THE FIRST 8 SCRATCH PAD
MOV
ADD
CLR
MOVB
BIC
BIS
ROMCLK
123100
INC
cMpP
BNE
RTS

8(sP)+ RS

#2,-(SP)
R4
(R5)+,3DMP0O4
#17,2%
R4,2%

R4
#10,R4
1s

;PUT POINTER TO DATA IN RS
sADJUST STACK
;START AT SP ADDRESS 0
;LOAD PORT4 WITH DATA
;CLEAR ADDRESS FIELD OF INSTRUCTION
;ADD ADDRESS TO INSTRUCTION
sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
sMOVE DATA TO SP
s INCREMENT COUNT
;DONE YET?

;:BR IF NO
;RETURN

;THIS SUBROUTINE CLEARS THE MICRO PROCESSOR C BIT
s”E:TOUORD IS INSTRUCTION, ROMCLK PC=5304
iMAR_

;NEXT WORD IS INSTRUCTION, ROMCLK PC=5304
;:CLEAR C BIT
sRETURN

s THIS SUBROUTINE SETS THE MICRO PROCESSOR C BIT
ROMCLK
010003
ROMCLK
0404031 <0+20>
RTS
PC

010003
104414
040403
000207

125

R4
13
PC

ROMCLK
010000
ROMCLK
040400!<0420>
RTS
PC

SETC:

000
377

SEQ 122

27-JUN-85 13:16:37 PAGE 27-83

taggTSHORD IS INSTRUCTION, ROMCLK PC=5304
;

sNEXT WORD IS INSTRUCTION, ROMCLK PC=5304
:SET C BIT

:RETURN

000

.BYTE

377
125

.BYTE

0,0.-1,-1,125,125,252,252

116
116
111

.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
-ASCI1Z

<377>/UNIBUS REGISTER ADDRESSING TIME-OUT/
<377>/UNIBUS REGISTER WRITE, READ TEST/
<377>/MICRO PROCESSOR TEST/
<377>/MICRO PROCESSOR WRITE, READ TEST/
<377>/8R REGISTER TEST/

252

111
122

CZDMC
MACRO V04.00
DMC11 ALU TESTS
212 035313
213 035335
214 035371
215 035435
216 035447
217 035471
218 035503
219 035515
220 035541
221 035571
222 035617
223 035652
224 035721
225
226 035760

227 036021
228 036057
229 036100
230 036142
231 036203
232
233
234 036240
235 036242
236 036244
237 036246
238 036250
239 036252
240 036254
241 036256
242 036260
243 036262
244 036264
245 036266
246 036270
247 036272
248 036274
249 036276
250 036300
251 036302
252 036304
253 036306
254 036310
255 036312
256 036314
257 036316
258 036320
259 036322
260 036324
261 036326
262 036330
263 036332
264 036334
265 036336
266 036340
267 036342
268 036344

377
377

123
104
104
116
115
115
101
120
106
125
104
115
120

103
105
105
120
101
101
114
122
117
116
115
101
117

EM6:
EM7:
EM10:
EM11:
EMi2:
EM13:
EM14:
EMIS:
EM16:
EM17:
EM20:
EM21:
EM22:

.ASCIZ
-ASCIZ
.ASCI1Z
.ASCI1Z
.ASCIZ
-ASCIZ
-ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ

377
377
377
377
377
377

122
105
105
105
105
105

105
130
130
130
130
130

DH1:
DH2:
DH3:
DH4:
DHS:
DH6:
.EVEN

.ASCIZ

377
377
377
377
377
377
377
377
377
377
377

000002
006
001262
006
001264
000003
006
001272
006
001270
006
001262
000002
006
001272
006
001270
000003
003
001272
003
001270
002
001264
000003
003
001272
003
001270
006
001264
000002
003
001272
003

SEQ 123

27-JUN-85 13:16:37 PAGE 27-84

015

DT1:

002

004

DT2:

004

002
004

DT3:

002

007

DT4:

011

002
007

DTS:

007
002

007

002

DT6:

.ASCIZ

.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ

2
.BYTE
SAVR1
.BYTE
SAVR2
3
.BYTE
SAVRS
.BYTE
SAVR4
.BYTE
SAVR1
2
.BYTE
SAVRS
.BYTE
SAVR4
3
.BYTE
SAVRS
.BYTE
SAVR4
.BYTE
SAVR2
3
.BYTE
SAVRS
.BYTE
SAVR4
.BYTE
SAVR2
2
.BYTE
SAVRS
.BYTE

<377>/SCRATCH PAD TEST/
<377>/DEVICE FAILED TO INTERRUPT/
<377>/DEVICE INTERRUPTED TO WRONG VECTOR/
<377>/NPR TEST/
<377>/MAIN MEMORY TEST/
<377>/MAR TEST/
<377>/ALU TEST/

<377>/PROGRAM CLOCK TEST/

<377>/FORCE POWER FAIL ERROR/

<377>/UNEXPECTED INTERRUPT/
<377>/DMC11 CONFIGURATION ERROR/
<377>/MAINTENANCE INSTRUCTION REGISTER TEST/

<377>/POMER FAIL

<377>/REGISTER
<377>/EXPECTED
<377>/EXPECTED
<377>/EXPECTED
<377>/EXPECTED
<377>/EXPECTED

6,15
6.2
6.4

6.2
6.4
6,2

3.7

3,11
2.2
3,7
3,7
6,2

3.7
3.2

INITIALIZE

FOUND
FOUND/
FOUND
FOUND
FOUND

FAILURE/

TRAPPED FROM/
REGISTER/
IBUS* REGISTER/
IBUS REGISTER/
ADDRESS/

CZDMC
MACRO V04.00
DMC11 ALU TESTS
269 036346

001270

270 036350 000002
271 036352
006
272 036354
001262
273 036356
006
274 036360 001404
275 036362
276 036362 000000
277 036364
000000
278 036366 000000
279 036370 035072
280 036372
035760
281 036374 036240
282 036376 035137
283 036400 036021
284 036402 036252
285 036404 035201
286 036406 036057
287 036410 036270
288 036412 035227
289 036414
036100
290 036416 036302
291 036420 035227
292 036422 036142
293 036424 036302
294 036426 035271
295 036430 036057
296 036432 036336
297 036434 035313
298 036436 036203
299 036440 036320
300 036442 035335
301 036444 000000
302 036446 000000
303 036450 035371
304 036452 000000
305 036454 000000
306 036456 035435
307 036460 036057
308 036462 036270
309 036464 035447
310 036466 036203
311 036470 036320
312 036472 035471
313 036474 036203
314 036476 036320
315 036500 035503
316 036502 036057
317 036504 036336
318 036506 035515
319 036510 036100
320 036512 036302
321 036514 035541
322 036516 000000
323 036520 000000
324 036522 035571
325 036524 000000

SEQ 124

27-JUN-85 13:16:37 PAGE 27-85

DT7:
002
.ERRTAB:

SAVR4
2
.BYTE
SAVR1
.BYTE
DMCSR

0
0
0
EM1
DH1
DT1
EM2
DH2
D12
EM3
DH3
DT3
EM4
DH4
DT4
EM4
DH5
DT4
EMS
DH3
DT6
EM6
DH6
DTS
EM7
0
0
EM10
0
0
EM11

DH3
DT3
EM12
DH6
DTS
EM13
DH6
DTS5
EM14
DH3
D16
EM15
DH4
DT4
EM16

6.4

6.2

;EMT

;EMT
sEMT

;EMT
SEMT
:EMT
;EMT

SEMT

:EMT

sEMT

SEMT

:EMT

sEMT

0
0

sEMT

;EMT

EM17

CZOMC
MACRO V04.00
DMC11 ALV TESTS

326 036526
327 036530
328 036532

329 036534
330 036536
331 036540
332 036542
333 036544

334 036546
335 036550
336 036552
337 036554
338 036556
339 036560
340 036562
341 036564
342
343
344 036566
349

000000
035435
036203

EM11
DH6
DTS
EM20
DH3
D77
EM21
DH3
DT3
EM20
0
0
EM22
DH3
DT3

036320
035617
036057
036350
035652

036057
036270
035617
000000
000000
035721
036057
036270

000001

SEQ 125

27-JUN-85 13:16:37 PAGE 27-86

.EVEN
:
CORMAX
.END

21
22

SEMT

;EMT

CZDMC

SEQ

MACRO V04.00 27-JUN-85 13:16:37 PAGE 27-87

SYMBOL TABLE

ADRCNT= 004373
AUDONE 003024

AUSTRT
AUTO.S
BINWRD

002446
010512
004714

BITO
= 000001
BITL
= 000002
BIT10 = 002000
BIT1i1 = 004000
BIT12 = 010000
BIT13 = 020000
BIT14 = 040000
BIT1i5 = 100000
BIT2
= 000004
BIT3
= 000010
BIT4
= 000020
BIT5S
= 000040
BIT6
= 000100
BIT7
= 000200
BIT8
= 000400
BIT9
= 001000

DH5
DH6

DISPLA
DISPRE
DMACTV

DMCH
DMCROO

DMCRO1
DMCRO2
DMCRO3
DMCRO4
DMCRO5
DMCRO6
DMCRO7
DMCR10
DMCR11
DHMCR12
DMCR13
DMCR14
DMCR15
DMCR16

036142
036203

001200
000174
001306

007320
001500
001510
001520
001530
001540
001550
001560
001570
001600
001610
001620
001630
001640
001650
001660

DMS213
DMS214

DMS215
DMS216
DMS217

001634
001644

001654
001664
001674

ERCTO6
ERCTO7

ERCT10
ERCT11
ERCT12

001734
001740

001744
001750
001754

DMS300
DMS301
DMS302
DMS303
DMS304
DMS305
DMS306
DMS307
DMS310
DMS311
DMS312
DMS313
DMS314
DMS315
DMS316
DMS317

001616
001626
001636
001646
001656
001666
001676

ERCT13 001760
ERCT14 001764
ERCT1S
001770
ERCT16 001774
ERCT17 002000
ERR
002700
ERRCNT
001232
ERRFLG 001325
ERRMSG 005172
ERRPC
002770
ERTABO 005322
EXIT
= 000205
EXITER 005252
FLOAT
002536
FY
002566
HALTS
005222

DMTVEC

001400

ICOUNT

DONE
DT1
D12
DT3
DT4
DT5
DT6

003734
036240
036252
036270
036302
036320
036336

INIFLG
INSTER=
INSTR =
INSTR2
INTTY
KMCM
LIMITS

001506
001516

001526
001536
001546
001556
001566
001576
001606

007054

DMCR17

001670

DMTLVL

BRW
BRX

0C3730
003732

DMCSRH
DMCTL

001406
001410

DM.END
DM.MAP

CLKX
CLRC

001242
035026

CONN

007114

DMS110

CRAM

006606

DMS114

001642

EM2

035137

MCSRX

006072

CSR

006510

DMS116

001662

EM21

035652

MEMDAT

035052

DH1
DH2
DH3
. DH4

035760
036021
036057
036100

BRLVL

CHRCNT
CKSWR
CKSWR1
CKSWR2
CKSWR3
CKSWR4
CKSWRS

CNERR
CNT.MA
CNVRT =
CONERR

012252

004712
007606
007666
007700
007704
007710
010014

007277
001702
104411
007223

CONTAB 002776
CONVRT= 104410
CORMAX 036566

CREAM

CSRMAP
CYCLE
DATABP
DATACL=
DATAHD
DELAY =
DEVADR
DEVTAB

r-b-—

001320

010514
010060
005216
104415
005204
104413
004370
003010

DMCSR

DMNUM
DMPO4
DMPO6
DMRLVL
DMRVEC
DMS100
DMS101

DMS102
DMS103

001404

001310
001412
001414
001376
001374
001502
001512

001522
001532

D17
EM1

001402

001700
001500

036350
035072

HILIM

004366

INBUF
INCHAR

007502
010020

LINE
LOBITS

007016
004372

DMS104
DMS105
DMS106
DMS107

001542
001552
001562
001572

EM10
EM11
EM12
EM13

035371
035435
035447
035471

LOCK
LOKFLG
LOLIM
LPCNT

DMS111
DMS112
DMS113

001612
001622
001632

EM15
EM16
EM17

035515
035541
035571

MASKX
MASTEK
MCRLF

DMS115

DMS117
DMS200
DMS201
DMS202
DMS203
DMS204
DMS205
DMS206

DMS207
DMS210
DMS211
DMS212

001602

001652
001672
001504
001514
001524
001534
001544
001554
001564

001574
001604
001614
001624

EM14

EM20
EM22
EM3
EM4
EMS
EM6
EM7
ERCTO0
ERCTO1

ERCTO2
ERCTO3
ERCT04
ERCTOS

035503

035617

035721
035201
035227
035271
035313
035335
001704
001710

001714
001720
001724
001730

LSTERR

MDATA

MEMLD
MEMLIM
MEPASS
MERRPC
MERRX
MERR2
MERR3
MILK

MLOCK
MNEW
MODU
MPASSX

001222

001324
104404
104403
004166
012266
007330
004314

001220
001326
004364
001224

001234

MPFAIL
MQaM

005675
005666

MTITLE
MTSTN

001000
006130

0K
ONE
PACTO0
PACTO1
PACT02
PACTO3
PACTO4

002646
001302
001702
001706

MR
005755
MRESET= 004000
MSTCLR= 104412

MTSTPC
MVECX
NEXT
NOACT
NODEV
NPRSET
NUM

006031
006100
001216
007154
002674
034664
006450

001712
001716
001722

PACTOS

001726

PACTO6

001732

PACTO7
PACT10

001736
001742

PACT11
PACT12
PACT13
PACT14
PACT15S
PACT16
PACT17

001746
001752
001756
001762
001766
001772
001776

PARAM = 104405
PARAM1 004234
PARBIT=
PARERR
PASCNT
PERFOR=

PFTAB

040000
004310
001230
004537

005430

001244
006142
005672

POPRO = 012600
POP1SP= 005726
POP2SP= 022626

007544

034726
001304
005733
006217
006117
005760
006005
001322

006043
006144
006704
006106

PRIO

006547

= 177776

PUSHRO= 010046

PUSH1S=
PUSH2S=
QV.FLG
RESREG
RESTAR
RESTRT
RESOS =
RETURN

005746
024646
001327
005220
005350
003534
104407
001214

ROMCLK= 104414
RUN
001316
SAVACT 001312
SAVNUM 001314

. 126

CZOMC
MACRO V04.00
SYMBOL TABLE
SAVPC
SAVRO
SAVRL
SAVR2
SAVR3
SAVR4

SAVRS

001276
001260
001262
001264
001266
001270

SWii
SWi2
SWi3
SWi4
SWi5
TDATA

001272

TEMP

SAVSP
001274
SAVOS = 104406
SCOPE = 104400

TEMPL
TEMP2
TEMP3

SCOP1 = 104401

SETC

SETVEC

SKIP

SOFTSW
SPACNT=
SPDAT
SPEED

SPLD

TEMP4

035040

TEMPS

034642

=
=
=
=
=

004000
010000
020000
040000
100000
024542

TST122
TST123
TST124
TST125
TST126
TST127

031106
031262
031436
031612
031766
032142

TST43
1ST44
TST45
TST46
TST47
TST5

017610
017764
020140
020314
020470
012704

WRKO.F
XBX
XCSR
XERR
XHEAD
XLOC

005174
005000
003546
003570
006224
003022

001246
001250
001252

TST130
TST131
TST132

032316
032472
032646

TSTS1
TST52
TSTS3

021072
021242
021510

XSTATQ
XTSTN
XVEC

033176

TSTSS

007454
005330
003554
001300

033544

TSTS7

001416

001254

001256

TIMER = 104416

002632

TKCSR

010052
004713
035062
007340

SEQ 127

27-JUN-85 13:16:37 PAGE 27-88

001204

TST13

013470

TST133

033022

TST135

033352

TST134
TST136

TSTSO

TSTS6

022120

SENDAD

013002
022404
022510
022624

$S
=
$Y
=
.BEGIN
.CNVRT

000141
000017

.DATAC

005552

TST137
TST14
TST15S
TST16

033766
013566
013664
013762

1576
TST60
TST61
TST62

TSTNO

TST2

012426

TST64

013176
025256

TST21
TST22

014254
014352

025762

TST25

STAT

001240

7571

012320

STAT3
STRTSW

0C1372
001236

TST101
TST102

025432
025606

TST104
TST105
TST106

026136
026312
026466

TST26
TST27
TST3

015016
015146
012456

TST72
TST73
TST74

013274
027016
027172
027346
027522
027676
030052
030226
030402
013372
030556
030732

TST31
TST32
TST33
TST34
TST35
TST36
TST37
TST4
TST40
TST41
TST42

015450
015534
015734
016134
016310
016464
016664
012606
017104
017260
017434

TST76
024726
TST77
025102
TTST
003612
TWOSYN= 010000
TYPDAT
005206
TYPE
= 104402
TYPMSG 005106
VEC
006526
VECMAP 012010
WHICH
012002
WRDCNT
004710

STATL
STAT2

001366
001370

SV05

004402

SWR

001202

SWFLG
SWMES
SWMES1

7ST10
TST100

TST103

010016
007205
007215

TST107

SWREG
000176
SWO0
= 000001
SWO01
= 000002
SW02
= 000004
SWO3
= 000010
SW04
= 000020
SWO5
= 000040
SWo6
= 000100
SWO07
= 000200
SWO08
= 000400
SW09
= 001000
SW10
= 002000
.

ABS.

TST11
TST110
TST111
TST112
TST113
TST114
TST115
TST116
TST117
TST12
TST120
TST121

036566

000000

ERRORS DETECTED:

026642

000
O

001

VIRTUAL MEMORY USED:
53760 WORDS
( 210 PAGES)
DYNAMIC MEMORY AVAILABLE FOR
71 PAGES
CZDMCD.BIN,CZDMCD. SEQ=CZDMCD.P11

TST23
TST24

TST30

014156
014450
014546

014672

015306

TST63

022240

004730

TST20

014060

022026

TRPOK

001226

003562

021732

034762

STACK = 001200

XPASS

TST54

TKDBR
001206
TLAST = 033766
TPCSR
001210
TPDBR
001212

TST17

020644

TST65S
TST66
TST67
TST7
TST70

TST71

TST7S

022726

023064

023210

023320
023426
013100
023624

023752

024104
024304
024440

024552

ZERO

$CRAP = 177777
$N

.CONVR

.DELAY
.EOP
.ERRTA
LHLT
.INSTE

.INSTR
.INST1
.MSG
.MSTCL

.PARAM

.PFAIL
.RESOS5
.ROMCL
.SAVOS
.SCOPE
.SCOP1
.START
.TIMER
.TRPSR
.TRPTA
.TYPE

003522

= 000137

003152
004472

004466

005436

003364
036362

004750
004154

004050

004070
004072
005466

004174

005336
004434
005504
004374
003576
003736
002002
005616
004716
001330
003766