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AH-8529H-MC

October 1987

132 pages

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Document:	CZDLDH0 KD11-Z,DL11-W DL11-W-1144 MFM SLU OCT 1981 bw
Order Number:	AH-8529H-MC
Revision:	000
Pages:	132
Original Filename:	CZDLDH0__KD11-Z,DL11-W__DL11-W-1144_MFM_SLU__AH-8529H-MC__OCT_1981_gray.pdf

OCR Text

R e

p—

'
(CZ0LDHO DLTT=W 11744 MFM SLU

NNS—‘—‘—‘—J“‘
s il=Od 000 IO N
N =00
N N - W

C7-Ju.-81

15:03

B8
2

PAGE

SEQUENCE

Wn -

]

MACRO M1113

.REM

IDENTIFICATION
PRODUCT

CODE:

AC=852CH=-MC(

PRODUCT NAME:

(CZDLDHO DL11-wW/1144 MFM SLU

DATE (REATED:

JuLY,

MAINTAINER:

DIAGNOSTIC ENGINEERING

AIJTHOR :

DAN CASALETTO

REVISED BY:

DAN MILLEVILLE

THE

INFORMATION

1981

THIS DOCUMENT

SUBJECT

TO (HANGE WITHOUT

NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION. DIGITAL EQUIPMENT CORPORATION ASSUMES
NO RESPONSIB'LITY FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMENT.
NO RESPONSIBILITY IS ASSUMED FOR THE USE OR RELIABILITY OF
SOF TWARE ON EQUIPMENT THAT IS NOT SUPPLIED BY DIGITAL OR ITS
AFFILIATED COMPANEIS.

1975,

FOLLOWNG ARE

DIGITAL
DEC

(C)

1981 BY DIGITAL EQUIPMENT CORPORATION

TRADEMARKS OF

PDP

PECUS

DIGITAL

UNIBUS

DECTAPE

EQUIPMENT

CORPCRATION:

MAS SBUS

' CZDLDHO DL1T=W 11/44 MFM SLU

MACRO M1113

07-JuL-81 15:03

¢
PAGE 3

;

SEQUENCE

HISTCRY SECTION

CZDLDDO WAS RELEASED OCT 79
THE

FOLLOWING CHANGES WERE MADE.

;+~

IN THE
1.

USE

COMMENT FIELD:
THE MFPT

ALL

CHANGES ARF

INSTRUCTION,AND

THE

INDICATED

CPU IS A 11/44:

(T)(E)ShrlgT PERFORM READER ENABLE AND RECEIVER ACTIVE

IF ERROR FLAGS TESTS AND BREAK TESTS ARE
ENABLED ,PERFORM THESE TESTS ONLY FOR THE SLU
AT 176500.PERFORM THESE TESTS FOR THE CONSOLE SLU

IF BITO3 OF SWR IS ADDITIONALLY SET.

(. WHILE IN MAINTENANCE MODE DO NOT WRITE AND READ
A “P OR AN ASCII 220. THIS WILL FORCE THE CONSOLE
INTO *CONSOLE MODE'.

IN THE CLOCK REPEATABILITY TEST, ALLOW FOR A
TOLERANCE OF 2 BETWEEN CLOCK COUNTS. THIS IS TO
ALLOW ENOUGH TOLERANCE WHEN MOS MEMORY IS USED
AND REFRESH CYCLES ARE OCCURING.

2. BECAUSE 11/44
SLU INTERRUPT REQUESTS ARE DEPENDANT ON A MFM CLOCK
ENOUGH TIME MUST BE GIVEN FOR THEM TO OCCUR. THEREFORE, ALL TESTS
ASSOCIATED WITH XMIT & RECEIVE INTERRUPTS SHOULD HAVE
A MINIMUM OF 4 NOP'S ACTING AS WAIT FOR INTERRUPT.

IT WAS FOUND THAT A*

ATTACHED TUS8 WwOULD BE ACTIVATID

BY THE DIAGNOSTIC,/nND,AS A RESULT,CHARACTERS WOULD BE
SENT TO THE RECEIVER BUFFER.
THIS WOULD CAUSE SOME TESTS TO FAIL. THEREFORE TO INHIBIT

ANY COMMUNICATION TO THE TUS8 FROM THE DIAGNOSTIC:
A.Ezgflligl??égTEMNCE MODE

IN ALL

TESTS THAT WRITE

B.IN ALL TESTS THAT WITE TO XMITTER AND BEFORE | EAVING
TEST:

DELAY ENOUGH TIME

;T:I}S:IGHT BE

TO ALLOW ANY CHARACTERS

IN THE PROCESS OF BEING XMITTED TO

C.DISABLE MAINTENANCE MODE FOR PURPOSE OF ERROR PRINTING
ONLY TO THE SLU WHICH THE TERMIi<AL IS ATTACHED.

IT WAS FOUND THAT UPON POWERUP ANv WITH THE

TUS8 ATTACHED,

CHARACTERS WOULD BE SENT TO THE RECEIVER FROM THE TUS8.

SOME RECEIVER TESTS WOULD FAIL DUE TO THIS. THEREFORE,
ON ALL TESTS THAT PERFORM RFCEIVER TESTS AND FOLLOWING
MAINTENANCE MODE BEING ENABLED,DELAY ENOUGH TIME TO ALLOW
TO ALLOW ANY CHARACTERS

THAT MIGHT BE

BEING RECEIVED TO FINISH.

IN THE

PROCESS OF

5. ADD SOFTWARE THAT WILL IMPLEMENT AUTO INITIATION OF
11744 T/A CONSOLE TEST VIA WRAF CABLE FROM TUS8 TO CANSOLE

—_—

S—

CZDLDHO DL11=w 11/44 MFM SLU
9%

MACRO M1113

—

R—

07-JuL=81 15:03

D 1
PAGE 3-1

SEQUENCE

PORIS. IT IS SELECTED BY SWR BITO2 AND [S PERFORMED
ONLY AFTER ALL

SLUS ARE

TESTED.

- CZDLDHO DL11=W 11/44 MFM SLU

MACRO M1113

07-JuL=-81

15:03

3
PAGE &

SEQUENCE

C(ZDLDEO WAS RELEASED JuL 80
1.

PROGRAM WAS (CHANGED TO WORK WITH VECTORS GREATER THAN 377.

CZDLDFO WAS RELEASED OCT 80

NEo3®
SR

OO~ (0

iy Sl
ol
il
il
il
il
il

IN TESTS 17 THROUGH 22 THE CLOCK DONE FLAG CAN GET SET
BETWEEN THE TIME THAT IT IS CLEARED (BIC) AND THE TIME THAT
INTERRUPTING IS ENABLED (BIS).
THE (BIC-BIS) COMBINATION
WAS CHANGED TO A (MOV) INSTRUCTION TO SET INTERRUPT ENABLE
AND CLEAR DONE FLAG ALL WITH ONE INSTRUCTION.

N.‘"‘ -l — o

iy il

IN TEST 20, 3 (NOP)'S WERE ADDED BEFORE ERROR +47 TO ALLOW

SUFFICIENT TIME BETWEEN CLOCK FLAG AND CLOCK INTERRUPT.

IN TEST 23,

THE COUNT DIFFERENCE ALLOWED WAS CHANGED ON

11/744'S ONLY FROM 2 TO 3.

TEST 45 HAD SEVERAL PROBLEMS.

PROGRAM CAN KICK OUT OF

DELAY WAS ADDED.

DE!LAY LOOF PREMATURELY.

B. ERROR +113 DID NOT PRINT.

A FIXED

A RESET WAS ADDED IMMEDIATELY

BEFORE THE ERROR CALL TO BFEAK
C. CLKCNT WAS NOT INITIALIZED.

THE MAINTENANCE WRAPAROUND.

CZDLDGO WAS RELEASED APR 81
1.

THE LINE CLOCK SYNCHRONIZING PROBLEM, WHICH WAS CORRZCTED RY
PATCH ORIGINALLY IN CZDLDD, WAS REMOVED IN THE NEW REVISION.

ggggEEgRE.

BRYERRNK
S

i
D e e e e
s

129

TEST 20 NOW CONTAINS THE PATCH TO CORRECT THIS

2. RANDOM “Q'S READ ON ANY INPUT MODE WILL BE IGNORED.
3.
»>

WAS A PROBLEM WITH CERTAIN SYSTEM HOOKUPS.

THE $SCOPE AND $ERROR ROUTINES NOW CHECK FOR BIT O OF
CPU ERROR REGISTER BEING SET (POWER MONITOR BIT).

THIS
THE

~€ZDLDHO WAS RELEASED JUL 81
1.

IN TEST 36, THE "‘CLR @RBUF'' INSTRUCTION WAS CHANGED TO
"“TST QRBUF' BECAUSE AN 11/24 DOES ONLY A WRITE, AND THE
PUAPOSE OF THAT INSTRUCTION I THAT POSITION WAS 70 80 A

TR~

| CZDLDHO DL11=W 11/44 MFM SLU
140
141
143

;

07-JuUL-81
GENERAL

15:03

THIS DIAGNOSTIC
THE

Bl —

TEST

TO VERIFY

DL11-Ww SERIAL LINE/REAL

11/44

THE OPERATION OF

THE

TIME CLOCK INTERFACE

MULTIFUNCTION MODULE

THE PROGRAM WIlIL RUN WITHOUT ANY SPECIAL TEST FIXTURES BY DEFAULT.
HOWEVER, THE FO_LOWING OPTIONAL TESTING IS PROVIDED:

000 NN

TEST TO VERIFY XMIT AND RECEIVE OF THE UARTS WITH
A WRAP CABLE. THE UART UNDER TEST IS LOOPED BACK ON

ITSELF. THIS IS SELECTED VIA CPERATIONAL SWITCH SETTING
BIT 7, AND IS APPLICABLE TO THE DL11W AND 11/44 MFM.

2. AUTOMATIC INITIATION OF THE T/A CONSOLE TEST OF THE 11/44
MFM. THE TU58 PORTS ARE LOOPED TO THE CONSOLE PORTS

D
d
s
D
e
e

IS A LCGIC

FOLLOWING MODULES:

VIV
AN N NN

D e

SEQUENCE

INFORMATION

PAGE 5

1. 1

(o]

144
145
146
147

MACRO M1113

THIS IS SELECTED VIA OPERATIONAL SWITCH SETTING BIT 2
AND IS APPLICABLE TC 11/44 MFM ONLY.
(SEE CKKFBAQ FOR T/A CONSOLE TEST EXPLANATION)

THIS DIAGNOSTIC OPERATES ON THE

CONSOLE

SERIAL

LINE

AND CLOCK

AS WELL AS UP TO FIFTEEN(15) ADDITIONAL IDENTICALLY CONFIGURED
SERIAL LINE INTERFACES. THE DEFAULT ADDRESSES ARE:

CONSOLE - 177560
177546

INTERFACES

SERIAL LINE
CLOCK

B. OTHER SERIAL LINE - 776500

FIRST SERIAL LINE ADDRESS
OF 15 CONSECUTIVE SERIAL
LINE ADDRESSES

THE PROGRAM IS DE%IGNED TO RUN ON ANY PDP=11 WITH 8K OF MEMORY

. IT CAN BE RUN UNDER XXDP,APT, AND ACT MONITORS,
~AND ON PROCESSORS WITH NO HARDWARE SWITCH REGISTER,
SOF TWARE SWITCH REGISTER = LOCATION 176
gggEGPFAILURE

NOTE:

1.2

IS SUPPORTED FOR SYSTEMS WITH CORE MEMORY OR BATTERY

THIS DIAGNOSTIC WITH TH= SWR = 000020
(CLOCK TESTS ONLY) SHOULD BE USED ON SWITCHLESS CPU'S
TO TEST KW=11L LINE CLOCK MODULES.

SYSTEM REQUIREMENTS

STANDARD 11 FAMILY(COMPUTER WITH A CONSOLE OUTPUT DEVICE
AND 8K OF MEMORY.

——

e —————

CZDLDHO DL11=w=11/44 MFM SLU
|

ettt

MACRO M1113

197
198

07=JUL=81 15:03

g 1

PAGE 5-1

SEQUENCE

:
OPTIONAL
1.L00P CABLE FOR UART LOOP BACK ON [TSELF

2.WRAP CABLE FOR 11/44 MFM T/E TESTING

<00
201
20¢
203

(SEE DWG. #7016942 WRAP AROUND CABLE
AND SECTION 5.0 OF THIS DOCUMENT)

1.2.2

STORAGE
THE

PROGRAM USES 5K WORDS OF

MEMORY

o0
OV ~NOWN
S NrY

nrorororoNIrONONL
M) nony
N)ed b a2
=D TM{

CZDLDHO DL11=W 11744 MFM SLU

MACRO M1113
1.3

07-JuL-81

15:03

PAGE 6

SEQUENCE

ASSUMPT ICNS
A,

IF THE UNIT UNDER TEST (UUT) IS THE CONSOLE , THE PROGRAM WILL
ASSUME THE REAL TIME CLOCK (RTC) IS ENABLED AND WILL TEST IT

UNLESS THE TESTS ARE DISABLED BY BIT6 OF
B.

THE UUT

FOR THE

IS NOT

THE CONSOLE,

THE RTC

THE SWR.

IS NOT

TESTED FOR THAT DEVICE.

DL11-W:

THE PROGRAM WILL ASSUME

221

THE ERROR FLAG BITS AND THE BREAK FUNCTION

OF THE DL11-W ARE DISABLED AND WILL NOT TEST THESE FUNCTIONS
UNLESS ENABLED BY BIT10 (FOR ERROR FLAGS) AND BIT8 (FOR BREAK)
OF THE SWR. THE DEFAULT CHARACTER SIZE IS 8 BITS (SEE PARA 2.3.2).
FOR THE

11/44:

THE PROGRAM ASSUMES THAT THE ERROR FLAG BITS AND THE
BREAK FUNCTION ARE DISABLED, AND WILL NOT TEST THESE FUNCTIONS
HOWEVER, IF BIT 10 (FOR ERROR FLAGS) AND BIT 08 (FOR BREAK)
OF SWR ARE SET, THEN ERROR FLAGS AND BREAK TESTS ARE PERFORMED
FOR THE TU58 SLU ONLY. IF BITO3 OF SWR IS ALSO
SET THEN THESE TESTS WILL BE ENABLcD FOR THE CONSOLE.
READER ENABLE

AND RECEIVER ACTIVE

?Sfi(??SNQERFORMED SINCE THE

2.0

TESTS

11/44 MFM DOES NCT IMPLEMENT THESE

OPERATING INSTRUCTIONS

2.1

USE STANDARD PROCEDURE FOR PDP-11 ABSOLUTE BINARY FORMATTED TAPES.

2.2

STARTING PROCEDURE

LOAD THE SWITCH REGISTER WITH SETTING
NOTE:

USING A CPU WITHOUT HARDWARE

SWITCH REGISTER

SOF TWARE SWITCH REGISTER LOCATION = 176.

(FOR A 11/44 (PU USE MFM CONSOLE FOR DEPOSITING
SWITCH REGISTER. TYPE “P TO ENTER CONSOLE)

START AT 200.
AFTER CHECKING THE TRANSMITTER, THE PROGRAM WILL PRINT ITS IDENTIFICATION
AND REPORT THE NUMBER OF DEVICES UNDER TEST (NUMBER IS OCTAL).

;figgRP?g§¥ IS PRINTED AFTER A FULL PASS HAS BEEN MADE ON ALL DEVICES

START AT 204.

et eNOTEnnwn

THE "ECHO'' TEST WILL BE EXECUTED. AN ''*'' IS PRINTED AT THE
BEGINNING OF THE TEST. THE ECHO TEST READS A (HARACTER FROM

——————————

L
——

|
| CZDLDHO DL11=Ww 11/44 MFM SLU

266
267
268
269
270
271
QI
=
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292

MACRO M1113

(07-JuL=-81

15:03

1
I
PAGE 6-1

SEQUENCE

THE TERMINAL ,WRJTES THAT CHARACTER TO THE TERMINAL AND
REPORTS ANY ERROR FLAGS SET IN THE RECEIVER BUFFER.

A CONTROL=C HALTS THE TEST AND PRINTS ‘'STOP'® AT THE
CONTINUING RESTARTS THE ECHO TEST.

START AT 210.

~<e

TERMINAL

wxk aNOTE*ww»

THE TERMINAL OUTPUT TEST WILL BE EXECUTED. DEPRESSING ANY CHARACTER
AT THE TERMINAL, HALTS THE TEST. CONTINUING RESTARTS THE TEST.
THE TEST OUTPUTS 32 CHARACTERS ON A LINE AND REPEATS THE
PATTERN EVERY THREE LINES. THE PATTERN IS AS FOLLOWS

(OCTAL

CODE 040 =-=> 377):

CHSAR

(OCTAL

(Y x+,=. /0123456789 : <=>?

RABCDEF GHI JKLMNOPQRS TUVWXYZE\]*_

(100 ==> 137)

*ABCDEF GHI JKLMNOPQRS TUVWXYZ

THIS BOTTOM LINE

DOES NOT HAVE

COULD BE

LOWER CASE:

THE

FOLLOWING

CODE)

(040 ==> 077)
(140 ==> 177)
IF

@ABCDEF GHIJKLMNOPQRSTUVWXYZ [\

THE

[LOWER CASE ALPHAJ

TERMINAL

[UPPER CASE ALPHA]

s xkNOTExwnn

THE

TESTING ON TERMINIALS OTHER THAN THE CONSOLE

FOR TESTS B OR

C,SEE

SECTION 2.3.4.

AND 2.3.5.

IS DESIRED

THIS DOCUMENT.

nn"

;;‘0

————
e

——

CZDLDKO DL11=w 11744 MFM SLU

298

07-JuL-81

15:03

)
)
)
i
D
)
—

PAGE 7

SEQUENCE

2.3

OPERATING PROCEDURE

2.3.1

OPERATIONAL SWITCH SETTINGS
THE

DIAGNOSTIC WILL

CHECK FOR EXISTENCE OF

SWITCH

REGISTER AT 177570.
IF NO
SWITCH REGISTER IS AVAILABLE THE PROGRAM
WILL AUTOMATICALLY USE THE
CONTENTS OF LOCATION
176 AS THE SOFTWARE SWITCH REGISTER. THE USER SHOULD
SET THIS LOCATION BEFORE STARTING THE PROGRAM. IF A
HARDWARE SWITCH IS AVAILABLE AND A SOF TWARE SWR(LOC. 176)
DESIRED,LOAD ALL 1'S INTO LOCATION 177570.(ALL SWITCHES
UP IF PHYSICAL SWITCHES ARE AVAILABLE)

299
300
N
302
303
304
305

CONO
VNS WN=O

294
295
<96
297

WWWWWWWWW

‘
;
!
;

MACRO M1113

BIT15
BIT14

= HALT ON ERROR
- LOOP ON PRESENT TEST

BIT13

= INHIBIT ERROR TYPEOUT

BIT12
BIT1
BIT10

= UNUSED
= UNUSED
= ENABLE ERROR FLAGS TESTS

BITO09

- LOOP ON ERROR

BITO8

= ENABLE BREAK FUNCTION TESTS

BIT06
BITOS
BIT04
BITO3

=
=
=
=

BITO2

ONLY IF BIT10 OR BITO8 IS SET.)
=11/744 MFM OPTION: SELECT AUTO INITIATION
OF T/A CONSOLE TEST VIA WRAP CABLE

BITO7

- ENABLE DATA TEST THROUGH LOOP-BACK CONNECTOR

INHIBIT RTC TESTS (ALLOW ONLY SLU TESTS)
ALLOW MANUAL SETTING OF '‘SDEVM'' (DEVICE MAP)
INHIBIT SLU TESTS (ALLOW ONLY LINE CLOCK TESTS)
FOR 11/44 MFM: ENABLE BOTH °'BREAK TESTS' AND 'ERROR FLAG
TESTS'

FOR THE

CONSOLE

SLU.

(THIS BIT

IS VALID

FOR DL11-W:

IF THE SOF TWARE SWITCH REGISTER IS USED(LOC. 176) THEN
BUILT INTO THE PROGRAM IS THE ABILITY TO DYNAMICALLY CHANGE THE
CONTENTS OF SWREG DURING PROGRAM EXECUTION. BY STRIKING “G

(CNTL G) ON CONSOLE TTY THE OPERATOR SETS A REQUEST FLAG TO CHANGE
THE CONTENTS OF SWREG, WHICH IS PROCESSED IN KEY AREAS OF THE PROGRAM

CODE

(IE) ERROR ROUTINES, AFTER HALTS END OF PASS, AND OTHER

APPLICABLE AREAS.

BECAUSE

TYPEOUTS AT

TIME

THE

SERIAL LINE,
THAT

THE

THIS DIAGNOSTIC USES

CONTROL=-G SHOULD BE

THE MAINTENANCE BIT

ISSUED DURING PROGRAM

IS SURE

TO BE

CLEAR.

IF A CONTROL=G IS DETECTED, UPON EXECUTION THE CONTENTS OF THE SWREG ARE
DUMPED IN OCTAL ON THE CONSOLE TTY AND ANY CHANGES ARE REQUESTED
(1E)
POSSIBLE

RESPONSES ARE:

SWR=XXXXXX

NEW=

(o]

—

MACRO M1113

07-JUL=-81

15:03

PAGE 7-1

<CR>

SEQUENCE
IF NO CHANGES ARE

6 DIGITS 0-7

TO BE MADE

TO REPRESENT IN OCTAL THE NEW SWITCH REGISTER

VALUE

*uU

;LAST DIGIT FOLLOWED BY <CR>.

TO ALLOW REENTERING VALUE IF ERROR IS COMMITTED

KEYING

IN SWREG VALUE.

FOR 11/44 (PU:

SINCE THE 11/44 HAS A HARDWARE SWITCH REGISTER LOADED BY THE MFM CONSOLE

THEN THE DIAGNOSTIC SHOULD ALWAYS FIND EXISTENCE OF 177570.
WHEN OPERATING ON THE 11/44 CPU, DYNAMIC CHANGING OF SWREG(177570)
PROGRAM EXECUTION CAN BE ACEOMPLISHED BY USING
TME MFM CONSOLE. TYPING “P<CR> ON THE CONSOLE TTY WILL ENTER THE

CONSOLE.

THIS IS CONSIDERED ‘‘CONSOLE MODE''.

TO EXAMINE

SWREG TYPE

SW<CR>

TO THE

CONSOLE PROMPT.

DURING

TO LOAD THE

SWREG TYPE ' D SW DATA<CR> ' WHERE 'DATA'' IS AN OCTAL NUMBER.
IN ORDER FCR THE DIAGNOSTIC TO TYPE TO THE TTY IT IS NECESSARY
TO HAVE

THE

11/44 MFM IN 'PROGRAM 1/0 MODE'‘.

THIS CAN BE ACCOMPL ISHED

BY TYPING ' C<CR> ' TO THE CONSOLE PROMPT. THEREFORE, WHEN CONSOLE
USE IS COMPLETED, PLACE THE MFM IN ‘'PROGRAM 1/0 MODE''.
BECAUSE THIS DIAGNOSTIC USES THE MAINTENANCE BIT, “P WILL

NOT BE ACKNOWLEDGED DURING THESE
DURING PROGRAM TYPEOUTS. AT THIS
WILL BE CLEARED.

TESTS.THEREFORE, ISSUE “P
TIME THE MAINTENANCE BIT

:CZDLDHO DL1T=W 11/44 MFM SLU

CZDLDHO DL11=w 11/44 MFM SLU

375
376
377
378
379
380
381
382
383
384
385
386
387

MACRO M1113
2.5.2

07-JuL-81 15:03

PAGE 8

SEQUENCE

SETTING BITS PER CHARACTER
THIS PROGRAM DEFAULTS TO TESTING 8 BITS PER CHARACTER.

SERIAL LINE IS SET FOR 5-=>7 BITS PER CHARACTER, SET THE
MEMORY LOCATION '‘SUSWR'' AS FOLLOWS:
CHAR. SIZE
(# OF BITS)
8

)
5

THE

"SUSWR'" CONTENTS
(OCTAL)

(BINARY)

100000000

400

001000000
000100000

100
40

010000000

200

"SUSWR'' IS USED IN THE DATA PATH TESTS TO LIMIT THE BINARY
ggg?;LTE§LEPATTERN TO THE NUMBER OF BITS SELECTED ON THE

2.5.3

RUNNING UNDER APT

THE APT MAILBOX IS LOCATED AT LOCATION 500, TO ALLOW ADDITIONAL SERIAL
LINE VECTOR ASSIGNMENTS TO THE 400 AREA OF MEMORY.
FOR DL11W:

THE DEFAULT EXECUTION TIMES PROVIDED($TSTM,Z$PASTM) ARE FOR EXECUTION
WITH AN 11/34 PROCESSOR, CORE MEMORY , AND 110 BAUD.
FOR 11/44:

THE EXECUTION TIMES PROVIDED IN THE APT SCRIPT THAT FCOLLOWS AND

IN SECT. 2.4 ARE FOR EXECUTION WITH A 11/44 PROCESSOR,
16K CORE MEMORY, AND 300 BAUD.
1.

CACHE,

THE FOLLOWING IS A PROGRAM LOAD FILE USED BY APT:
TABLE 'A' IS USED FOR APT DUMP MODE AND RUN TIME MODES.

TWO SLU'S ARE TESTED.(SSWREG BIT05=1 AND $SDEVM=3)
A SLU AT 177560(DEFAULT CONSOLE SLU) AND AT 176500

(BASE ADDRESS CODE).
THE ERROR FLAG AND BREAK TESTS ARE SELECTED FOR THE SLU
AT 176500(TUS8 SLU IN MFG.)
($SWREG BIT 10 AND 8 =1)

C. THE

'ENABLE DATA TEST THROUGH LOOP-BACK CONNECTOR' TEST
IS ENABLED TO ALLOW TEST 44 TO EXECUTE (SSWREG BIT 7 =1).

2. E TABLE 'B' IS USED FOR APT Qv.
IT ACCOMPLISHES WHAT E TABLE ‘A’
DOES, WITHOUT THE ENABLE DATA TEST THROUGH THE LOOPBACK CONNECTOR, BUT

ADDITIONALLY IT SUPPRESSES ALL TYPEOUTS TO THE TERMINAL (SENVM=240) AND

SELECTS AUTO TESTING OF T/A CONSOLE TEST VIA WRAP CABLE ($SWREG BIT02=1).
1ST PASS
RUN TIME

LONGEST
TEST TIME

ADD
I T JONAL
RUN TIME

| CZDLDHO DL11=W 11/44 MFM SLU
432
433
434
435
436
437
438
439
440

461
442
443

44h

445

446
W47

448
449
450
451
452
453
454
455
456

MACRO M1113

07-JUL=-81 15:03

PAGE 8-1

SEQUENCE

E TABLES
A

SWITCH REGISTER 1

002640

002404

SWITCH REGISTER 2

000400
00/0000
000700000000
000700000000
000700000000
000700000000

000400
0070000
000700000000
000700000000
000700000000
000700000000

E~MODE /S=MODE
(SENVM/SENV)

($SWREG)

CPU TYPE/OPTIONS
MEMORY MAP CODE 1
MEMORY MAP (CODE 2

MEMORY MAP CODE 3
MEMORY MAP CODE 4

BUS PRIORITY/INTERRUPT 1
BUS PRIORITY/INTERRUPT 2
BUS ADDRESS CODE
DEVICE MAP CODE
($DEVM)
CTLR.

CTLR.

SPECIFIC WORD 1
SPEC IFIC WORD 2

2007000

176500

2407001

000003

000000
000000

]

| CZDLDHO DL11=W 11/44 MFM SLU
|

457

458

MACRC M1113
2.3.4

SEQUENCE

THE OPERATOR MUST SUPPLY THE PROGRAM WITH THE

CORRECT ADDRESSES BY INSERTING THEM AT THE TAG LABELED ''CRCSR'':
CRCSR:
CRBUF:
CTCSR:
CTBUF:
CRVECT:
CRPSW:
CTVECT:
CTPSW:

464
465
466

467
468

478
479
480
481
482
483
484
485

RUN WITH ALTERNATE CONSOLE ADDRESS

THAN 60,

463

473
474
475
476
477

PAGE 9

TO USE A CONSOLE ADDRESS OTHER THAN 177560, OR VECTOR OTHER

459
460
461
462

469
470
7
472

07-JuL-81 15:03

2.3.5

ADDRESS
ADDRESS
ADCRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS

OF
OF
OF
OF
OF
OF
OF
OF

RECEIVER RCSR
RECCIVER BUFFER
TRANSMITTER CSR
TRANSMITTER BUFFER
RECEIVER VECTOR
ASSOCIAED PSW
TRANSMITTER VECTOR
ASSOCIATED PSW

TESTING ADDITIONAL SERIAL LINES

THIS PROGRAM WILL SUPPORT TESTING OF MULTIPLE SLU'S. IT REQUIRES
THE ADDRESS OF THE FIRST ADDITIONAL RCSR (STORED AT ‘‘$BASE'’) AND

ITS INTERRUPT VECTOR (STORED AT “'SVECT1'"); AND WILL BE ABLE

TO ADDRESS ANY SLU STARTING AT

15 CONSECUTIVE DEVICES.

EXAMPLE :

THE

$BASE:

$VECT1:

THE PROGRAM WILL BE ABLE

SPECIFIED BASE ADDRESS UP TO

776500
300

TO TEST

THE

CONSOLE PLUS ANY

ADDITIONAL DL11-W SLU'S WITH!N THE RANGE 776500 ==> 776660

$BASE AND SVECT1 DEFAULT TO 77650C AND 300 RESPECTIVELY.
THE PROGRAM ASSOCIATES UNIT NUME:RS TO DEVICES AS FOLLOWS:
(NUMBERS IN PARENTHESIS ARE OCTAL)

UNIT# O ==>
UNIT# 1 ==>
UNIT# 2 ==>
UNIT# 3 -=>

UNIT# & -->
.

UNIT#15 ==>

(ONSOLE [ADDRESS STORED AT ‘'(RCSR'‘]
BASE ADPMRESS STORED AT ‘'SBASE'’
:
ASSOCIAVED BASE VECTOR ’STORE‘D AT"'SVECTT"'
BASE ADDRESS + (10)
BASE VECTOR + (10)
BASE ADDRESS + (20)
BASE VECTOR + (20)
BASE ADDRESS + (30)
BASE VECTOR + (30)

BASE ADDRESS + (160)
BASE VECTOR + (160)

CZDLDHC DL1T=w 11/44 MFM SLU

MACRO M1113

509
510
2};

R LR

518

516

519
520
gg;

PAGE 10

D A T |

P UNIT

! UNET

—————eccceea.

csisevesess! UNIT

semansetnant

! UNIT

CONGORE:

A BIT MAP CAN BE ENTERED AT "SDEVM'' PRIOR TO STARTING THE PROGRAM
SETTING BITS OF THE SWR INHIBITS THE SELF-SIZING AND DEVICE MAP
GENERATION,AND USES THE VALUE STORED

252

EXAMPLE :

525
526
ggg

SWR = 000040
$BASE:
776500
$SVECT1: 300

2%3

$DEVM:

531

THE PROGRAM WILL

532
533
534

SEQUENCE

STARTING AT LOCATION 200 AND HAVING BIT5 OF SWR CLEAR, THE PROGRAM WILL SELF
SIZE THE NUMBER OF DEVICES (STARTING AT THE BAS ADDRESS) AND
STORE A BIT MAP AT "'SDEVM'' (DEVICE MAP) TO INDICATE WHICH UNIT NUMBERS
ARE PRESENT AND WILL BE TESTED:

S08

513

07-JuL=-81 15:03

BY THE OPERATOR.

[BINARY

0 000 000 000 100 0001

[BINARY = 0 000 000 GOO 001 0111
TEST -

UNIT# O = CONSOLE
UNIT# 1 = 776500 ;
UNITH 3 = 776520 ;

300
320

————

CZDLDHO DL1T1=w 11/44 MFM SLU

MATRO M1113

2.4

07-JuUL-81 15:03

¢ 2
PAGE 11

SEQUENCE

EXECUTION TIMES =
FOR DL11=W: (110 BAUD)
LONGEST SUBTEST TIME
PASS

TIME

ADDITIONAL DEVICES
FOR 11/44:

(300 BAUD)

LONGEST SUBTEST TIME

PASS TIME
ADDITIONAL

DEVICES

50 SECONDS
60 SECPNDS
55 SECONDS/DEVICE
50 SECONDS
60 SECONDS
55 SECONDS/DEVICE

| CZDLDHO DL11=W 11/44 MFM SLU

MACRC M1113
3.0

07-JuL-81

D_2
PAGE 12

15:03

SEQUENCE

ERROR REPORTING

IF A ROUTINE FAILS AND THE INHIBIT ERROR TYPEOUT (BIT13) OF THE SWR

IS NOT SET, A PRINTOUT RESULTS IN THE FORM:
"'(SOME ASCII MESSAGE)"’
TEST#
ERR PC
RCSR
XXXXXX
XXXXXX
XXXXXX

CANY APPLICABLE DAT HEADINGS]
[ANY APPLICABLE DATA]

NOTE: "RCSR'' 1S DEPENDENT ON THE FAILURE
€ THEREFORE COULD BE TCSR,RBUF,TBUF
,OR LKS
WHERE ““XXXXXX'' IS AN OCTAL NUMBER.

THIS ERROR PRINTOUT OCCURS PROVIDED

WOULD NOT HINDER THE TYPEQUT.

THE ERROR THAT EXISTS

IN CASES WHERE

IT IS NOT POSSIBLE

TO PRINT AN ERROR MESSAGE (I.E. FATAL CONSOLE TRANSMITTER
FAILURES), A HALT OCCURS AND THE PC CAN BE EXAMINED BY THE OPERATOR
TO FIND

THE

ERROR

INFORMATION IN THE PROGRAM LISTING.

NOTE: FOR SOF TWARE SWITCH OPERATION. THE SWITCH REGISTER CAN
BE CHANGED BY TYPING A& CONTROL-G AT THE CONSOLE DURING ERROR PRINTOUTS.
AFTER CONTTNUING FROM THE ERROR HALT THE OLD SWR CONTENTS
IS DISPLAYED AND THE NEW CONTENTS CAN BE ENTERED.
IF ERROR HALTS ARE DISABLED, THE CONTROL-G RESPONSE OCCURS
IMMEDIATELY FOLLOWING THE TYPEOUT.

IF THE CPU THIS DIAGNOSTIC WILL BE RUN ON DOES NOT HAVE A CPU ERROR
REGISTER (ADDRESS 17777766), THE FOLLOWING SECTION DOES NOT APPLY,
SINCE THE ROUTINES MENTIONED PLANS FOR THAT POSSIBLITY.
IF AN ERROR SHOULD OCCUR WHEN CHECKING THE POWER MONITOR BIT IN THE

SCOPE ROUTINE, THE ERROR WILL BE CALLED FROM THAT ROUTINE.
IF THE
BIT BECOMES SET AFTER THE SCOPE ROUTINE, AND AN ERROR OCCURS FOR ANY
REASON, *TWO* ERRORS WILL CALL.
THE PCWER MONITOR BIT ERROR WILL CALL
FIRST, THEN THE ERROR TO BE CALLED WILL CALL.
IT IS A DEFINIIC POSSI-

BILITY THAT THE ERROR WAS CAUSED BY THE POWER SUPPLY(S) THAT WERE OUT
OF SPECIFICATION, AND REPAIR SHOULD BE EXECUTED BEFORE RELYING ON THE
RESULTS OF

THE

FAILURE.

—

—e—

—_——

————————

—————————

—

{

| CZDLDHO DL11=w 11/44 MFM SLU

585
586

587

‘

23(1)

L . B
58S

07-JuL=81

15:03

PAGE 13

SEQUENCE

4.0

SUBRCUTINE ABSTRACTS

4.1

TRAPCATCHER

592
593
23?

THIS IS A SERIES OF INSTRUCTIONS STARTING AT LOCATION O DESIGNED TO
DETECT AND ISOLATE UNEXPECTED TRAPS TO THE TRAP AND INTERRUPT VECTOR
AREA OF MEMORY.

596

EACH VECTOR ENTRANCE ADDRESS IS LOADED WITH THE ADDRESS OF THE NEXT

567
598
283

LOCATION. THE NEXT LOCATION IS LOADED WITH A BREAK POINT TRAP (000003).
THUS AN ILLEGAL TRAP OR INTERRUPT CAUSES A TRAP THROUGH THE BPT VECTOR(14)
WHICH POINTS TO THE ''CATCH'' ROUTINE.

601

THE "'CATCH'' ROUTINE REPORTS THE PC THAT CAUSED THE ORIGINAL

602
603
604
605
606

28;

616
617

618
6;8

TRAP AND

THE LOCATION OF THE TRAP VECTOR (IF UNDER APT, AN ERROR IS INDICATED TO APT).
AFTER REPORTING THE ERROR THE PROGRAM HALTS. THE PROGRAM MUST BE RESTARTED
AT THIS POINT.
&.2

609

610
611
612
613
2}%

i
,’

MACRO M1113

e ey

WRPSW

THIS ROUTINE IS USED TO WRITE THE PSW BY POPPING VALUES FROM THE

STACK. THIS METHOD IS USED TO BE
PROCESSORS.
4.3

COMPATIBLE WITH ALL

FAMILY

SCOPE

THIS ROUTINE CALL IS PLACED BETWEEN EACH SUBTEST. IT RECORDS THE STARTING
ADDRESS OF EACH SUBTEST AS IT IS BEING ENTERED AND UPDATES THE

TEST NUMBER. IF A SCOPE LOOP IS REQUESTEL, IT WILL JUMP TO THE START OF
SUBTEST AT WHICH THE SCOPE LOOP IS REQUESTED.

THE

——

!
| CZDLDHO DL11=W 11/44 MFM SLU
!
r

|
[

623

ggg

MACRO M1113

07-JuUL=81

4.4

ERROR

15:03

PAGE

SEQUENCE

626

THIS ROUTINE CALL

628
629

AND AS A POINTER INTO THE ERROR TABLE . THIS ROUTINE REPORTS ERRORS
TO APT USING ''SAPTYPE'' AND TYPCS ERROR REPORTS TO THE CONSOLE

627
630

USING ‘'SERRTYPE'".

4.5

636

$POWER

THIS ROUTINE SAVES ALL GENERAL REGISTERS DURING POWER=-DOWN

637

AND RESTORES THEM AT POWER-UP.

ggg

"POWER’* IS PRINTED AT

640

2‘4}

4.6

643
b
645
64

IF A POWER FAILURE OCCURS

CONSOLE AFTER POWER

IS RESTORED.

CKSWR

THIS ROUTINE CALL IS USED TO DETECT THE RECEPTION OF A CONTROL=G
CONSOLE. THE CALL USES ''SREAD'' TO PERFORM THE CONTROL=G
SEQUENCE OF DISPLAYING THE CONTENTS OF THE SOF TWARE SWITCH REGISTER
AND THE ENTERING THE NEW CONTENTS FROM THE TERMINAL.

648

5.0
R

AUTOMATIC INITIATION OF 11/44 T/A CONSOLE TEST
VIA WRAP CABLE
s Phectute
oo SR
L

654

PURPOSE:

655

THE

T/E(OR T/A)

BY MANUALLY

656
657
658
659

CONSOLE

TEST CAN BE

IMPLEMENTED

TYPING T/E(OR T/A) ON THE KEYBOARD

OF THE TERMINAL WHEN IN CONSOLE MODE. IN ORDER TO
IMPLEMENT THIS TEST IN AN AUTOMATIC WAY IN MANUFACTURING
WHILE UNDER APT, THE USE OF A WRAP CABLE FROM
THE TUS8 TO THE CONSOLE CAN BE USED ALLOWING THIS

660
661
662
663
664
665
666

DIAGNOSTIC TO ISSUE THE *T/A® COMMAND TO THE CONSOLE.
THE DIAGNOSTIC WILL ISSUE THE APPROPRIATE SEQUENCE
OF COMMANDS TO THE CONSOLE VIA THE WRAP CABLE WHEN
BITO2 OF SWR =1. THE DIAGNOSTIC WILL THEN MONITOR
THE EXPECTED RESPONSE FROM THE CONSOLE VIA THE WRAP
CABLE AND HALT IF THERE IS AN ERROR. THE T/A TEST
IS DONE ONLY AFTER ALL SLUS ARE TESTED. IF T/A IS SUCCESSFUL

ggg

"END PASS'

669

IS PRINTED AND THE DIAGNOSTIC STARTS AGAIN.

FIGURE 1 SHOWS THE PROPER WRAP CABLE SETUP AND

670
671
672
673

REQUIREMENTS FOR AUTOMATICALLY INITIATING T/A FROM THE
THE DIAGNOSTIC.NOTICE THAT THIS ARRANGEMENT ALLOWS
FOR THE TERMINAL TO MONITOR ALL COMMUNICATION FROM
THE CONSOLE OUTPUT DURING EXECUTION OF THE DIAGNOSTIC

g;g
676

THE

FROM THE

645

1S PLACED WHEREEVER AN ERROR REPORT

IS DESIRED. THE LOWER BYTE OF THIS CALL IS USED AS THE ERROR NUMBER

631
632
633

650
A

IN *WRAP MODE'".

TYPEOUT EXAMPLES

677

g oy

€79

1. WITH THE CONFIGURATION OF FIGURE 1 AND "WRAP MODE'* SELECTED

678

——

—

e
———————————————————

;(ZDLDHO DL11=w 11/44 MFM SLU

;

680

681

685

|
|

MACRO M1113

Q07=JuL=81 15:03

PAGE 14-1

SEQUENCE

THE PROGRAM MAY BE LOADED BY APT, IF "E TABLE B' OF SECTION

2.3.3 WERE USED WITH THE EXCEPTION OF ALLOWING TYPEQUTS ($SENVM=200)

682

THE FOLLOWING WOULD BE SEEN ON THE LOCAL TERMINAL:

CZDLDHO DL11-W/1144 MFM SLU

686
687

ggg

;

690

02 DEVICES UNDER TEST
CONSOLE

“p

>>>T/A

CONSOLE=TESTR

691
692

END PASS “P
CONSOLE

ggz

>>>T/A

695

CONSOLE=-TESTR

696

END PASS *P

233

>>>T/A

697

CONSOLE

700

CONSOLE=-TESTR

;85

END PASS “P

;82

...

DESCRIPTION: REFERING TO THE . BOVE PRINTOUTS:

705

706

THE DIAGNOSTIC IS LOADED WITH THE

TITLE BEING PRINTED.

B. TWO SLU DEVICES(CONSOLE,TUS8) ARE SPECIFIED

707
708

(. BOTH SLUS ARE TESTED COMPLETELY. AT THIS POINT
THE THE DIAGNOSTIC ISSUES “P TO THE WRAP CABLE.

709

THE CONSOLE ENTERS CONSOLE MODE AND

710

THE

“P TYPED ON THE

TERMINAL

IS THE MFM CONSOLE ECHO.

(4}

D. THE CONSOLE PERFORMS ITS OWN SELF TEST BY TYPING

713

E. THE DJAGNOSTIC THEN ISSUES T/A AND THE TERMINAL

712

714

7158

716

717
718
719
720
721

*CONSOLE® FOLLOWED BY >>>, THE CONSOLE PROMPT.

SHOWS

THE

CONSOLE

ECHO OF

THIS.

F. THE MFM THEN PERFORMS THE T/A TEST SHOWN BY THE TERMINAL
TYPING

"CONSOLE-TESTB'.THE

*B* IN THIS TYPEQUT,AND
THE TEST A SUCCESS. THE
INDICATING A SUCCESSFUL
THE DJAGNOSTIC CONTINUES
DIAGNOSTIC.

DIAGNOSTIC LOOKS FOR THE

WHEN FOUND , CONSIDERS
DIAGNOSTIC WILL TYPE END PASS
PASS OF THE DIAGNOSTIC.
WITH FURTHER PASSES OF THE

—————————

(ZDLDHO DL11=w 11744 MFEM SLU
723
724

725

726

727

728
729
730

6}
732
733
734
735

736
737
738
739
740
741

MACRO M1113

07-JuL-81 15:03

PAGE 15

SEQUENCE

'"E TABLE B' OF 2.3.3 WERE USED WITH TYPEOUTS SUPPRESSED

($ENVM=240)
NOTICED:

AS STATED,

THEN THE FOLLOWING TYPEOUTS WOULD BE

CONSOLE

>>>T/A

CONSOLE=TESTB*P
CONSOLE

>>>T/A

CONSOLE=TESTB*P
CONSOLE

>>>T/A

CONSOLE=TESTB*P ..... ETC.

—

————

|
]

i (ZDLDHO DL1T=w 11/44 MFM SLU

MACRO M1113

07-JuL=-81

15:03

PAGE 16

SEQUENCE

FIG.

1= WRAPAROUND CONFIGURATION = AUTO INITIATION OF
11744 T/A CONSOLE TEST

743
744

7465
746

747
748

749

RRRARR TR

750
751
752

AARR AT ARRAAAAARRARAAR

AARAAAAAAARAAARRARAAAR
AT R

WRAP AROUND CABLE

TUS8

753
754
755
756
757

CONSOLE
OUT"’UT

IM"UT

OUT"UY

tecmcccaa

S1/

3
:

tom——

\ §3

SWITCH

THIS ALLOWS

WHEN THE

THE USE OF

THE

TTY KEYBOARD

TERMINAL WITH THE

CONSOLE

SWTICH IS IN "WRAP'' MODE CONTACTS ARE
S1-C1 CLOSED

$1-C2 OPEN
S2-C3 CLOSED

THIS

TU58 PORT TO COMMUNICATE WITH THE

DONE WITH A DPDT

TO MONITOR

IS ALL

BEFORE

S1-C1 IS OPEN
S3-C3 IS OPEN

THE

TTY

IN "NORMAL'' MODE CONTACTS ARE:
S1-C2 IS CLOSED

THIS ALLOWS

THE

;

+(C2

TTY PRINTER
WHEN THE

ceccccccccccccccccccccceaen- +

783
784
785

TTY PORT

IN‘l’UT

758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
79
780
781
782

THE

CONSOLE

CONSOLE PORT AND FOR

OUTPUT

SWITCH

THIS TEST CAN BE RUN THE CONSOLE UART,TTY,TUS8 MUST BE AT

THE SAME BAUD RATE. THE CONSOLE AND TU58 UART,AND THE TTY SHOULD BE
SET UP WITH THE SAME STOP BIT SETTING,
WITH PARITY INHIBITED AND WITH A WORD LENGTH OF 7 OR 8 BITS
FOR MORE

INFORMATION SEE

CABLE DRAWING NUMBER:

TM~

LA A

THE MFM PRINTS AND

7016942
A

THE WRAP AROUND

SRR

MACRO M1113

07-JuL=-81

AT AT AT

15:03

AT AT AT A7

J_2

PAGE 17

A0 AT AT AT AT AL A7 A0

SEQUENCE
A0 AT A7

A0 A0 A7 &7

A0 AF AT A7

A0 A0 A7 A0 &0 47

&7 47

AT AT AT AT AL AT AT AL AT AT &Y AY AT AT A0 AV AT AY A AT AT A0 AY AV AT A0 AV AT AT AV AT AT &Y AY &)

crawwnnkrnnnnnnwnwwwnwnrt

-...l.....-.-Q...!........-.-.'.a.....c.

| CZDLDHO DL11=W 11/44 MFM SLU

PFRAOR

*axtadannddnhhhhkrentn

.$ERROR IS THE ERROR HANDLER
ARGUMENTS:
1)

ADRESS ==

IF NON-BLANK=ADDRESS OF

TYPEOUTS,

NOTE :

INSTR ==

INSTR2 ==

INOTE:
;

USER ERROR ROUTINE

IF BLANK AND SW13 IS USED TO INHIBIT ERROR
THE PC OF

THE ‘ERROR'' WILL BE

IF SW13 IS USED TO INHIBIT ERROR

TYPED.

TYPEOUTS A "'CR'' AND "'LF'' WILL ALWAYS
BE THE LAST THING TYPED AND IS PROVIDED
BY THIS ROUTINE

IF NON-BLANK WILL BE THE FIRST INSTRUCTION
OF THE ROUTINE
(EXAMPLE OF USE
<<MOV R1,SAVR1>>
NOTE:
INSTR CAN BE A MACRO ].E. <<SAVE <R1,R2,.R3,.R&>>>)

IF NON-BLANK WILL REPLACE THE LAST INSTRUCTION (RTI).

REFER TO ARGUMENT 2 (INSTR) FOR AN EXAMPLE OF USE.
BE SURE TO PROVIDE AN RTI FOR EXITING THE ROUTINE.

THIS ROUTINE IS CONDITIONALLY ASSEMBLED BY $SWR
FOR SW09,SW10,SwW13,8SW15

*SW09=1 LOOP ON ERROR

*SW10=1 BELL ON ERROR
*SW13=1 INHIBIT ERROR TYPEOUTS
‘SW15=1 HALT ON ERROR

Enourmfs REQUIRED:

‘)
A

TYPE AN ASCIZ STRING (.S$TYPE) DEPENDING ON $SWR

AASSRSt
RRRd Rl

AL AT AT AT AT A0 A0 A0 A0 A7 A7 &Y AY AV A0 AV AT AV AV A0 AV A0 AV AV AL AT AT A AT AT AT AT AT AY A
AT AT

AT AT AT AT

AT A

A7 &Y AF AF

Jexnnnnnnnnnnnnnnenrs

AV AT AY AF

GERRTYP

A0 A

AT &Y SF

A0 A

AV AY AY AV A Y

wnmnnnnnsnnnsnsnnnnn

:.$ERRTYP IS USED TO REPORT ERRORS

2ITS INTENDED USE IS TO BE IN CONJUCTION WITH .SERROR

*ARGUMENTS:
35!

IF BLANK ALL DATA IN THE "DATA TABLE''(DT) ARE ASSUMED T0

BE OCTAL NUMBERS AND ARE TYPED AS SUCH.

IF NON-BLANK THE 'DT'* CAN CONTAIN BOTH OCTAL AND DEC IMAL

NUMBERS WITH THE "DATA FORMAT''(DF) INDICATING HOW EACH
NUMBER IS TO BE TYPED. THE 'DF'' MUST BE A BYTE DATA STRING

CZDLDHO DL11=w 11744 MFM SLU

MACRO M1113
3

1267

1268

269

1270
1271 .
1272
1273
1274
1275
1276
1277
. 1278
1279

K_2
PAGE 17-1

SEQUENCE

WITH "'0'" FOR OCTAL AND '"1'' FOR DECIMAL.

éROUTlNES REQUIRED:
51)
.STYPOCT
22)
.STYPDEC

TYPE AN OCTAL NUMBER
TYPE A DECIMAL NUMBER (ONLY NEEDED IF "'A"" IS NON=BLANK).

sNOTES:

1280
1281

THIS ROUTINE PROVIDES AN AUTOMATIC ‘'CARRIAGE RETURN=-LINE FEED'

)

TWO(2) SPACES ARE TYPED AFTER EACH NUMBER FOR 'DT'".

‘EXAMPLE OF USE WITH .SERROR

1282
1283
1284
1285
1286
1287
1288
1377
1381
1385
i389
1390
1397
1398
1404

.$ERROR $ERRTYP
.SERRTYP

;:$ERRTYP IS ENTRY POINT OF .S$ERRTYP

;."DT'" CONTAINS OCTAL AND DECIMAL NUMBERS

:tttt'.'tt"'..!".it't"""'fifitQQQ'..Q"'..".'.'.‘Q

1414
1426
1427
1428
1429
1430
1431

07-JuL=-81 15:03

«MCALL

NEWTST,SSNEWTEST,.STYPE,.$TYPOC,.$TRAP

.MCALL
.MCALL

.SAPTHDR,.$APTBLS,.$ACT11
.$CMTAG,.SEOP, .SREAD

.MCALL

1432
1433

.MCALL

.SBTTL

- 001100
104000

000004

000011
000012
000015
000200

177776
177776
177774
177772
177570
177570

000000
000001

.SETUP,STARS,PUSH,POP,SETUP,
.EQUIV
.EQUAT

BASIC DEFINITIONS:

;*INITIAL ADDRESS OF THE STACK POINTER wxx 1700 wwe
STACK=
1100
ERROR=EMT
SCOPE=]0T

;*MISCELLANEOUS DEF INITIONS

HT=

LF=
CR=
CRLF=
PS=

::CODE FOR HORIZONTAL TAB

;§57;g

::PROCESSOR STATUS WORD

12
15
200

::CODE FOR LINE FEED
::CODE FOR CARRIAGE RETURN
::CODE FOR CARRIAGE RETURN=LINE FEED

STKLMT= 177774
177772
DSWR=
177570
DDISP=
177570

::STACK LIMIT REGISTER
::PROGRAM INTERRUPT REQUEST REGISTER
; ;HARDWARE SWITCH REGISTER
*HARDWARE DISPLAY REGISTER

R1=

: :GENERAL REGISTER

PIRQ=

: *GENERAL PURPOSE REGISTER DEF INITIONS
RO=
%0
: ;GENERAL REGISTER
21

CZDLDHO DL11=W 11/44 MFM SLU

BASIC DEF INITIONS

000002
000003

MACRO M1113

07-JuUL-81

15:03

L_2

PAGE 17-2

SEQUENCE

R2=
R3=

%2
%3

s sGENERAL REGISTER
; sGENERAL REGISTER

RS=

s sGENERAL REGISTER

R4 =

R6=

R7=

Y 44

PC=

SP=

s sGENERAL REGISTER

;*PRIORITY LEVEL

PRO=
PR1=
PR2=
PR3=
PR4=
“ PRS=

; sGENERAL REGISTER

0
40
100
140
200
240

s sSTACK POINTER

s sPROGRAM COUNTER

DEFINITIONS

;sPRIORITY
;sPRIORITY
;:PRIORITY
::PRIORITY
;sPRIORITY
::PRIORITY

LEVEL
LEVEL
LEVEL
LEVEL
LEVEL
LEVEL

O
1
2
3
4
S

PR6=
300
;sPRIORITY LEVEL 6
PR7=
340
;;PRIORITY LEVEL 7
;*"'SWITCH REGISTER'' SWITCH DEFINITICONS
SW15=
100000
Swl4=
40000
Swi3=
20000
Swi2=
10000
SWil=
4000
SW10=
2000
Sw09=
1000
SW08=
400
Sw07=
200
SW06=
100
SW05=
40
SW04=
20
Sw03=
10
SW02=
4
Sw01=
2
SW00=
1
°
SW9=SwW09
SW8=Sw08
SW7=SwW07
SW6=SW06
SW5=SW05
SW4=SW04

Sw3=Sw03
SW2=Sw0?2

SW1=Sw01
SW0=SW00

;*DATA BIT DEFINITIONS

BIT1S=
BIT14=
BIT13=
BIT12=

BIT11=
BIT10=
BIT09=
BIT08=
BIT07=
BITO6=
BITOS=
BITO4=

100000
40000
20000
10000

4000
2000
1000

400
200
100
40
20

(BITOO TO BIT15)

—

C(ZDLDHO DL11=w 11/44 MFM SLU

BASIC DEFINITIONS

MACRO M1113 07-JuL-81 15:03 PAGE 17-§
M

BIT03=
BIT02=
BITO1=
BITOO=

10
4
2
1

BIT9=BIT09
BIT8=BITOR
BIT7=BITQ7
BIT6=BIT06
BIT5=BITOS
BIT4=BIT04
BIT3=BIT03
BIT2=BIT02

SEQUENCE

BIT1=B1T01
BITO=3IT00

;*BASIC "'CPU'" TRAP VECTOR ADDRESSES

ERRVEC= 4
RESVEC= 10
TBITVEC=14
TRTVEC= 14
BPTVEC= 14

;:TIME OUT AND OTHER ERRORS
..RESERVED AND ILLEGAL INSTRUCTIONS
' BIT
::TRACE TRAP
; ;BREAKPOINT TRAP (BPT)

PWRVEC= 24

; ;POWER FAIL

IOTVEC= 20

;s INPUT/0OUTPUT TRAP (IOT) =«SCOPE**

EMTVEC= 30

..EMULATOR TRAP (EMT) **ERROR*#

TRAPVE (=34
TKVEC=
60

1434
1435
1436
1437
1438
1439

1448
1456
1457
1458 000014
1459 000016
1460
1461
1462 000042
1463
1464

TPVEC=
64
PIROVEC=a?gT ,

ABASE=

AVECT1=
AUSWR=
$TN=
$SWR=

1440
1441
1442
1443
1444
1445
1446
1447

::"'TRAP''TRAP
;:TTY KEYBOARD VECTOR

BPT=

2 TTY PRINTER VECTOR
; ;PROGRAM INTERRUPT REQUEST VECTOR

176500

300
400
1
161000

000003

RR AR R

AR R RN RN R

THROUGH 14

AR R

AR RN

(BPT TRAP)

AR AR RR RN RN RN RN RO NR

s*ALL UNUSED LOCATIONS FROM 4-776 CONTAIN A '‘.+2,BPT''
s*SEQUENCE TO CATCH ILLEGAL TRAPS & INTERRUPPTS
s*LOCATION O CONTAINS O TO CATCH IMPROPERLY LOADED VECTORS
000014
014520
000340

=14
.WORD
.WORD

CATC(CH
340

000042
000000

o=
.WORD

42
0

1466

1467
1468
1469 000174
1470 000176
1471

AR R

;THIS IS THE COMMAND FOR A TRAP

000174

DISPREG: .WORD
SWREG:
.WORD

174

0
0

;THE BPT TRAP VECTOR POINTS TO THE
:
ILLEGAL TRAP HANDLER '‘CATCH''

CZDLDHO DL11=w 11/44 MFM SLU

BASIC DEFINITIONS

1472

1473 000200
1476 000204

1475 0002°C

000137
000137

000137

003046
017600

020020

MACRO M1113

07-JuL=-81
.=200

JMP
JMP

JMP

15:03

START
ECHO
OUTTST

N_2
PAGE 17-4

SEQUENCE

;DO INTERFACE TEST
;DO ECHO TEST
;DO OUTPUT TEST TC TERMINAL

| CZDLDHO DL11=w 11744 MFM SLU
BASIC DEF INITIONS

1477

1478

00050

MACRO M1113

07-JuL=-81 15:03

LSBTTL

PAGE 18

SEQUENCE

500

ACT11 HOOKS

".".'.'......'t.....'.'.'Q""'Q'.'Q.t'..'...."."'.'.'.Q".'..'

000500
000046
000046 82)‘63?3
000052 000000
000500

*HOOKS REQUIRED BY ACT11

$SVPC=.
=46
segng
'WORD 0
.=$SVP(

:SAVE PC
::1)SET LOC.46 TO ADDRESS OF SENDAD IN .SEOP
::2)SET LOC.52 TO ZERO
;s RESTORE PC

CZDLDHO DL11=w 11/44 MFM SLU
APT PARAMETER BLOCK

MACRO M1113

07-JuL-81 15:03

.SBTTL

1480

c 3
PAGE 19

SEQUENCE

APT PARAMETER BLOCK

::tt"ttt""t"'fittt'!Q'Q""l.ttt""t"iQ.'i"t"""t"t'.".

;SET LOCATIONS 24 AND 44 AS REQUIRED FOR APT

;:'it't'tttt't.tt'ttitt""'t.'tttt"t't..i'.t.t.*'fii"ttt"ti".

000024
000044

000500
000024
000200
000044
000500
000500

2 sSAVE CURRENT LOCATION
;:SET POWER FAIL TO POINT TO START OF PROGRAM
::FOR APT START UP
:sPOINT TO APT INDIRECT ADDRESS PNTR.
::POINT

TO APT HEADER BLOCK

JsRESET LOCATION COUNTER

2233223322233 3232332322223 2222232332

2222222222222

Rttt

)

SETUP APT PARAMETER BLOCK AS DEFINED IN THE APT-PDP11 DIAGNOSTIC

000500
000500
000502
000504
000506
000510
0C0512

00000C
001066
000060
000055
000030

;INTERFACE SPEC.
SAPTHD.
$HIBTS: .WORD
0
;;TWO HIGH BITS OF 18 BIT MAILBOX ADDR.
$MAIL
;;ADDRESS OF APT MAILBOX (BITS 0-15)
$MBADR: .WORD
50
;:RUN TIM OF LONGEST TEST
$TSTM:
.WORD
$PASTM: .WORD
60
;;RUN TIME IN SECS. OF 1ST PASS ON 1 UNIT (QUICK VERIFY)
55
;;ADDITIONAL RUN TIME (SECS) OF A PASS FOR EACH ADDITIONAL UNIT
SUNITM: .WORD
SETEND-SMAIL/2 ;;LENGTH MAILBOX-ETABLE (WORDS)
.WORD

—

CZDLDHO DL11=w 11744 MFM SLU

COMMON TAGS

MACRO M1113

07-JuL-81

SBTTL

1482

A232

COMMON TAGS

$TSTNM:
$ERFLG:
$ICNT:
$LPADR:
$LPERR:
$ERTTL:
$ITEMB:
$ERMAX:
$ERRPC:
$GDADR:
$BDADR:
$GDDAT:
$BDDAT:

.WORD
.BYTE
.BYTE
.WORD
.WORD
.WORD
.WORD
.BYTE
.BYTE
.WORD
.WORD
.WORD
.WORD
.WORD

.WORD
.BYTE
.BYTE
.WORD
.WORD
SWR:
DISPLAY: .WORD

$AUTOB:
$INTAG:

$TKS:
$TKB:
$TPS:
$TPB:

$NULL:
$FILLS:
$FILLC:
$TPFLG:

000

$CRLF:
SLF

RRRRRR

d )

177560
177562
177564
177566

COMMON TAGS

;sCONTAINS THE TEST NUMBER
; sCONTAINS ERROR FLAG
:;CONTAINS SUBTEST ITERATION COUNT
:;CONTAINS SCOPE LOOP ADDRESS
2 sCONTAINS SCOPE RETURN FOR ERRORS

:;CONTAINS
;s CONTAINS
: ;CONTAINS
; sCONTAINS
;s CONTAINS
; sCONTAINS
;s CONTAINS

TOTAL ERRORS DETECTED

ITEM CONTROL BYTE

MAX. ERRORS PER TEST
PC OF LAST ERROR INSTRUCTION
ADDRESS COF 'GOOD® DATA
ADDRESS OF 'BAD' DATA
'GOOD* DATA

;;CONTAINS 'BAD' DATA
: ;RESERVED==NOT TO BE USED

; ;AUTOMATIC MODE INDICATOR
;: INTERRUPT MODE INDICATOR

; ;ADDRESS OF SWITCH REGISTER
; ;ADDRESS OF DISPLAY REGISTER
;. TTY KBD STATUS

DDISP

;. TTY KBD BUFFER

;:TTY PRINTER STATUS REG. ADDRESS
;:TTY PRINTER BUFFER REG.

ADDRESS

2 sCONTAINS NULL CHARACTER FOR FILLS
2 sCONTAINS # OF FILLER CHARACTERS REQUIRED

.BYTE
.BYTE
.BYTE
.BYTE

;2 INSERT FILL CHARS. AFTER A "LINE FEED''

;2 'TERMINAL AVAILABLE'' FLAG (BIT<07>=0=YES)

; sESCAPE ON ERROR ADDRESS
2 ;QUESTION MARK
; ;CARRIAGE RETURN
;sLINE FEED

S$ESCAPE:
0
$QUES:
.AS(TI]

012

222222202

::START OF

€
o

$CMTAG:

o eolelolololeololeloleblelelolelelelsls)

001000

SEQUENCE

CONTAINS VARIOUS COMMON STORAGE LOCATIONS

;*USED IN THE PROGRAM.
=1000

001002
001003
001006
001010
001012
001014
001015
001016
001020
001022
001024
0C1026
001030
001032
001034
001035
001036
001040
001042
001044
001046
001050
001052
001054
001055
001056
001057
001060
001062
001063
001064

D 3
PAGE 21

3333302222232 2222222222222

:*THIS TABLE

001000-

15:03

.ASCII
LASCIZ

2232222322222
22222
R
R0ttt
d)

SBTTL

APT MAILBOX-ETABLE

't'tfi"itfi't'ttttt't""t".tt"fi'tQ't.lt'.ttttt.tttt'.t""t't

000000
000000
000000
000000
000000
000000
000000

00000
000400

.EVEN
:
$MAIL
$MSGTY:
$FATAL:
$TESTN:

$PASS:
$DEVCT:
$UNIT:
$MSGAD:
$MSGLG:

.WORD
.WORD
.WORD

.WORD
.WORD
.WORD
.WORD
.WORD

$ETABLE:
$ENV:
.BYTE

$ENVM:
$SWREG:
$USWR:

_BYTE
.WORD

.WORD

AMSGTY
AFATAL
ATESTN
APASS
ADEVCT
AUNIT

AMSGAD
AMSGL
G
AENV
AENVM
ASWREG
AUSWR

s sAPT MAILBOX
; ;MESSAGE TYPE CODE
;;FATAL ERROR NUMBER
::TEST NUMBER
; ;PASS COUNT
;sDEVICE COUNT
;2170 UNIT NUMBER
2 sMESSAGE ADDRESS
s sMESSAGE LENGTH
;;APT ENVIRONMENT TABLE

s ;ENVIRONMENT BYTE
: ;ENVIRONMENT MODE BITS
:;APT SWITCH REGISTER
:;USER SWITCHES

iCZDLDHO DL11=W 11744 MFM SLU

, APT MAILBOX~E TABLE

!
}
'

001114

00000C

MACRO M1113

07-JUL=-81 15:03

$CPUOP:
i
i
;e
o

.WORD

$MAMS1:
$MTYP1:

.BYTE
.BYTE

AMAMS]
AMTYP1

.WORD

AMADR1

== (HIGH BYTE)
MEM.TYPE BYTE
900 NSEC CORE=001
300 NSEC BIPOLAR=002
500 NSEC MOS=003
;;HIGH ADDRESS,BLK#1
;:HIGH ADDRESS.M.S. BYTE
;:MEM.TYPE,BLKA2
;;MEM.LAST ADDRESS,BLK#2
;:HIGH ADDRESS,M.S.BYTE
::MEM.TYPE ,BLKA3
;:MEM.LAST ADDRESS,BLK#3

i
i

ACPUOP

E 3

PAGE 21-1

;.CPU TYPE,OPTIONS
BITS 15-11=CPU TYPE
11/04=01,11/05=02,11/20=03,11/40=04,11/45=05
11/70=06,PDQ=07,0=10
BIT 10=REAL TIME CLOCK

BIT
BIT

9=FLOATING POINT PROCESSOR
8=MEMORY MANAGEMENT

001116
001117

000
000

001120

000000

e
g
:'
:
SMADR1:

001122
001123
001124
001126
0C1127
001130

000
000
000000
000
000
000000

SMAMSZ:
$MTYP2:
$MADRZ:
$MAMS3:
SMTYP3:
$MADR3:

.BYTE
.BYTE
.WORD
.BYTE
.BYTE
.WORD

AMAMS?
AMTYPZ2
AMADRZ
AMAMS3
AMTYP3
AMADR3

001134
001136
001140
001142
001144

000000
000300
000000
176500
000000

$MADR4:
SVECT1:
$VECT2:
$BASE:
$DEVM:

.WORD
.WORD
.WORD
.WORD
_WORD

AMADR4 ; ;MEM.LAST ADDRESS,BLK#4
AVECT1
::INTERRUPT VECTORA1,BUS PRIORITYA1
AVECT2 ;;INTERRUPT VECTORA#2BUS PRIORITY#?2
ABASE
;;BASE ADDRESS OF EQUIPMENT UNDER TEST
ADEVM
;;DEVICE MAP

001132
001133

001146

000
000

$MAMSS:
$MTYP4:

SETEND:

.BYTE
.BYTE

SEQUENCE

;;HIGH ADDRESS,M.S. BYTE
;;MEM. TYPE ,BLKA1

MEM.LAST ADDR.=3 BYTES,THIS WORD AND LOW OF '‘TYPE'' ABOVE

AMAMS4
;;HIGH ADDRESS M.S.BYTE
AMTYP4 ; :MEM.TYPE ,BLKA#4

Cem
e
s =y

ERROR POINTER TABLE

{

|
|

]

T
e

CZDLDHO DL11=w 11744 MFM SLU

MACRO M1113

07-JuL=-81 15:03

.SBTTL

F_3

PAGE 22

ERROR POINTER TABLE

;*THIS TABLE CONTAINS THE
;*THE

SEQUENCE

INFORMATION FOR EACH tRROR THAT CAN OCCUR.

INFORMATION IS OBTAINED BY USING THE

INDEX NUMBER FOUND

;*LOCATION SITEMB. THIS NUMBER INDICATES WHICH ITEM IN THE TABLE IS PERTINENT.
;*NCTE1:
IF S$ITEMB IS O THE ONLY PERTINENT DATA IS (SERRPC).
;*NOTE2:

$ERRTB:

001146

1483 001146

.$ERRTB:

EACH ITEM IN THE TABLE CONTAINS 4 POINTERS EXPLAINED AS FOLLOWS:

;;POINTS TO THC ERROR MESSAGE

:;POINTS TO THE DATA HEADER

;;POINTS TO THE DATA FORMAT

1484 001146
1485 001150

020104
024265

;4gg 001154

000000

1489 001156

020130

EM2

:"'CAN _NOT ACCESS TBUF''

1491 0C1162
}235 001164

025056
000000

DT2
0

;STESTN,SERRPC,
TBUF

1494 001166
1495 001170

020154
024265

EM3
DH1

}235 001174

000000

1486 001152

025046

EM1
DH1

:;POINTS TO THE DATA

DT1
0

:"'CAN _NOT ACCESS TCSR''
:"'TEST# ERR PC
T(SR"

;STESTN,SERRPC,
TCSR

1496 001172

1499
1500
1501
;ggg

024312

025046

DHZ

DT1

;"'TESTA ERR PC

TBUF''

;"'TCSR DONE NOT CLEARED WITH TBUF
:"'TEST# ERR PC
TCSR'
;BTESTN,SERRPC,TCSR

001176
001200
00102
001204

020221
024265
025046
000000

EM&
DH1
DT1
0

:"'TCSR DONE NOT SET''
:"'TEST# ERR PC
T(SR'
;STESTN,SERRPC,T(SR

1504 001206

020243

EMS

;TCSR DONE NOT SET WITH RESET

}28; 001214

000000

1505 001210
1506 001212

024265
025046

DH1
pT?

:"'TEST# ERR PC
TC(SR"
;STESTN,SERRPC,
TCSR

1509 001216

020300

EM6

:"'CAN NOT ACCESS RCSR''

1511 001222
1512 021224

025066
000000

DT6
0

:STESTN,SERRPC
,RCSR

1510 001220

024337

DH6

FuLL"'

;"'TEST# ERR PC

R(SR"

e
——

1490 001160

;uYg/lE.L MiM SLU

MACRO M1113

07-JuL=81 15:03

G 3
PAGE 23

SEQUENCE

26
30
32

020324
024364
025076

EM?
DH?
D17

;"'CAN NOT ACCESS RBUF''
;"'TESTA ERR PC RBUF''
;STESTN,SERRPC
,RBUF

36
001240
001242

020350
024411
025106

EM10
DH10
DT10

;"'CAN NOT ACCESS LKS''
:"'TEST# ERR PC LKS''
;$TESTN,SERRPC,LKS

001246
001250
001252

020373
024265
025046

EM11
DH1
DT

;"BITO OF TCSR NOT CLEAR AFTER RESET''
;"'TEST# ERR PC
TCSR
JSTESTN,$ERRPC,TCSR

001256
0012€)
001262

020436
024265
025046

EM12
DH1
DT1

:"'CAN NOT SET BITO OF TCSR''
;"'TESTA ERR PC
T(CSR"
;STESTN,SERRPC,TCSR

001266
001270

020467
024265

EM13
DH1

:"'CAN NOT CLEAR BITO OF TCSR''
;"'TEST# ERR PC
TCSR"

001276
001300
001302

020522
024265
025046

EM14
DH1
DT1

;"RESET DID NOT CLEAR BITO Of
;"'TEST# ERR PC
T(CSR"
JSTESTN,$ERRP(C,TCSR

00130¢
001310
001312
001314

020563
024265
025046
000000

EM15
DH1
DT
0

;'BIT2 OF TCSR NOT CLEAR AFTER RESET"
;"'TEST# ERR PC
T(SR"
;STESTN,SERRPC,TCSR

001316
001320
001322
001324

020626
024265
025046
000000

EM16
DH1
DT
0

;"'CAN NOT SET BIT2 OF TCSR''
;"'TESTA# ERR PC
T(CSR"
JSTESTN,SERRPC,TCSR

001326
001330
001232

020657
024265
025046
000000

EM17
DH1
DT1
0

;"'CAN NOT CLEAR BITZ2 OF T(SR'
J"'TEST# ERR PC
T(SR"'
JSTESTN,SERRPC,TCSR

001244

001254

001264

001272
001274

001304

000000

(25046
000000

000000

DT
0

JS$TESTN,SERRPC,TCSR

T(SR''

!(ZDLDHO DL1T=W 11/44 MFM SLU
ERROR POINTER TABLE

!
!

MACRO M1113 07-JuUL=81 15:03 PAGE 24

SEQUENCE

1557 001336

020712

EM20

;'RESET DID NOT CLEAR BIT2 OF

1562 001346
1563 001350
1564 001352

020753
024265
025046

EM21
DH1
DT

;"BIT6 OF TCSR NOT CLEAR AFTER RESETZ2
;"'TESTA ERR PC
T(SR"
sSTESTN,SERRPC,TCSR

1567 001356

021016

EM2?2

J"XMIT INTERRUPT WITH PRIORITY 7°'

}g;? 001364

000600

1558 001340
1559 001342
;gg? 001344

;222 001354

1568 001360
1569 001362

024265
025046
000000

DH1
DT
0

000000

024265
025046

DH1
DT1

;"'TEST# ERR PC
T(SR"
;STESTN,$SERRPC,TCSR

;"'TESTA ERR PC
T(SR"
;STESTN,SERRPC,TCSR

‘

1572 001366
1573 001370
1574 001372

021053
024265
025046

EMS3
DH1
DT

;"'CAN NOT SET BIT6 OF T(CSR''
;"'TESTA ERR PC
T(SR"
;STESTN,SERRPC,TCSR

1577 001376
1578 001400
1579 001402

021104
024265
025046

EM24
DH1
DT1

;"'CAN NOT CLEAR BIT6 OF
;"'TESTA ERR PC
TCSR"
;STESTN,SERRPC,TCSR

1582 001406

021137

EM25S

;"RESET DID NOT CLEAR BIT6 OF

}ggz 001414

000000

;2;2 001374

}gg? 001404

1583 001410
1584 001412

000000

024265
025046

1587 001416
1588 001420
1589 001422

021200
024337
025066

1592 001426

021243

1594 001432

DH1
DT

T(SR''

TCSR''

;"'TESTA ERR PC
T(SR"
;STESTN,SERRPC,T(CSR

T(SR''

EM26
DH6
DT6

;"BIT6 OF RCSR NOT CLEAR AFTER RESET"'
;'TESTA ERR PC
RCSR"
sSTESTN,SERRPC
,R(SR

EM27

;"RCVR INTERRUPT WITH PRIORITY

025066

DT6

sSTESTN,SERRPC
,RCSR

1597 001436

021302

EmM30

;"'CAN NOT SET BIT6 OF RCSR''

1599 001442
1600 001444

025066
000000

DT6
0

;STESTN,SERRP(C
,R(SR

;gg? 001424

1593 001430

}ggz 001434

1598 001440

000000

024337

000000
024337

0
:

DH6

;"'TESTA ERR PC

J"'TEST# ERR PC

RCSR"'

R(SR"

7*'

p—

| CZDLDHO DL11=W 11/44 MFM SLU
|

| ERROR POINTER TABLE
1601

001446

8 8388 8 g

D
P

1464

1466

~
~

Vownbum—‘og 2

D
D
e
e
e

1602 001450
1603 001452
1604 001454
1605
1606 001456
1607 001460

—

oococororrOr
OO

1472

1474

1476

001500

1618 001502
1619 001504

021332
024337
025066
000000

1640
1641
1642
1643
1644

001546
001550
001552
001554

(07-JuL=81

EmM31
DHé
DT6

15:03

PAGE 25

SEQUENCE

;"'CAN NOT (CLEAR BIT6 OF RCSR''
J"'TESTA# ERR PC RC(SR"
;STESTN,$ERRPC
,RCSR

021366
024237
025066
000000

EM32

021434
024411
025106
000000

EM33

;"BITé OF LKS NOT CLEAR AFTER RESET''
;"'TEST# ERR PC LKS''
;$TESTN,SERRPC,LKS

021476
024411
025106
000000

EM34
DH10
DT10
0

;"'LKS INTERRUPT WITH PRIORITY 7*'
;'TESTA ERR PC LKS''
;STESTN,SERRPC,LKS

021534

EM35
DH10

:"'CAN NOT SET BIT6 OF LKS''
:"'TEST# ERR PC LKS''
:$STESTN,SERRPC,LKS

024411
025106
000000

1629 001524
1630
1631 001526
1632 001530
1633 001532
1634 001534
1635
1636 001536
1637 001540
1638 001542
1639 001544

MACRO M1113

DH6
D16
0

DH10
DT10
0

DT10
0

;"'CAN NOT CLEAR BIT6é OF R{SR WITH RESETZ2
;"'TEST~ ERR PC R(SR''
;STESTN,SERRPC
,RCSR

021564
024411
025106
000000

EM36
DH10
DT10
0

021616
024411
025106
000000

EM37
DH10
DT10
0

021656
024435
025116
000000

EM4O
DH&40
DT40
0

;" DUAL ADDRESSING ERROR''
BAD'*
J"'TEST# ERR PC GOOD
,
$BD( SR
;STESTN,SERRPC,$GDADR

021704
024411
025106
000000

EM4T
DH10
DT10
0

;"BIT7 OF LKS NOT SET AFTER RESETZ2

:"'CAN NOT CLEAR BIT6 OF LKS''

;"'TESTA ERR PC

LKS''

;$TESTN,SERRPC,LKS

;"RESET DID NOT CLEAR BIT6 OF LKS''

;"'TESTA ERR PC

LKS''

;STESTN,SERRPC,LKS

J'TEST# ERR PC

LKS''

JSTESTN,SERRPC
,LKS

——

CZDLDHO DL11=w 11/44 MFM SLU

ERROR POINTER TABLE

MACRO M1113

07-JuL-81

15:C3

PAGF 26

SEQUENCE

;"'CAN NOT CLEAR BIT7 OF LKS"'
;"'TESTA ERR PC LKS"'

1645 001556
1646 001560
1647 001562
1648 001564
1649
1650 001566
1651 001570
1652 001572
1653 001574

021744
024411
025106
000000

EML2
DH10

021776
024411
025106
000000

EM&3

1655 001576
1656 001600
1657 001602
1658 001604

022027
024411
025106
000000

EM4S
DH10
DT10

1660
1661
1662
1663

001606
001610
001612
001614

022063
024411
025106

EM4S

000000

DH10
DT10
0

;"'TESTA ERR PC
LKS''
;STESTN,SERRPC,LKS

1665 001616

1666 001620
1667 001622
1668 001624

022120
024411
025106
000000

EM46
DH10
DT10
0

:"RTC _INTERRUPT DID NOT OCCUR''
;"'TESTA ERR PC LKS''
;STESTN,SERRPC,LKS

1670
1671
1672
1673

001626
001630
001632
001634

022120
024411
025106
000000

EM47
DH10
DT10
0

:"RTC _INTERRUPT DID NOT OCCUR''
;"'TESTA ERR PC LKS''

1675 001636
1676 001640
1677 001642
1678 001644

022154
024411
025106
000000

EM50
DH10
DT10
0

:'RTC DOUBLE INTERRUPT''
;"'TESTA ERR PC LKS''

1680 001646
1681 001650

022201
024411
025106
000000

EMS1
DH10
DT10
0

:'RESET DID NOT CLEAR RTC INTERRUPT''
;"'TESTH ERR PC LKS''
;STESTN,SERRPC,LKS

022231
024411
025106
000000

EMS2
DH10
DT10
0

;"'TEST# ERR PC
LKS''
sSTESTN,SERRPC,LKS

pT10

DH10
DT10
0

;STESTN,SERRPC,LKS

;'BIT7 OF LKS DOES NOT SET''
;"'TESTA ERR PC LKS''

;STESTN,SERRPC,LKS

;"RTC INTERRUPT AT PRIORITY 7'
;"'TESTA ERR PC LKS''
;STESTN,SERRPC,LKS

;"RTC _INTERRUPTS WHEN DISABLED''

sSTESTN,SERRPC,LKS

JSTESTN,SERRPC,LKS

:"RTC _INTERRUPT DID NOT CLEAR WITH BIT7 OF LkS"

————
e

——

| CZDLDHO DL 1=w 11744 MFM SLU
ERROR POINTER TABLE
1689 001666

1690 001670
1691 001672

1692 001674

1693
1694 001676
1695 001700
1696 001702

1697 001704
1698

02230¢€
024471
025130
000000
022332
024265
025046
000000

MACRO M1113

07-JuL=-81

EM53
DH53
DT53
0

EM54

DH1
DT
0

15:03

K_3

SEQUENCE

PAGE 27

J"'TESTH ERR PC

LKS

CNT1

CNT2"

sSTESTN,SERRPC,LKS ,FIRST,SECND

;"XMIT INTERRUPTS WHEN DISABLED''
;"'TESTA ERR PC TCSR"
;STESTN,SERRPC,TCSR

1699 001706
1700 001710
1701 001712

EMSS
DH

1702 001714

022470
024265
025046
000000

"XMIT DID NOT INTERRUPT''
;"'TESTA ERR PC TCSR''
;S$TESTN,SERRPC,TCSR

1704 001716
1705 001720
1706 001722
1707 001724

022370
024265
025046
000000

EMS56
DH1
DT
0

;"XMIT INTERRUPT AT PRIORITY 7'
;"'TESTA ERR PC TCSR"'

001726
001730
001732
001734

022426
024265
025046
000000

EMS7

"XMIT INTERRUPTS WITH ENABLE CLEAR''
;"'TEST# ERR PC TCSR"

001736

001740
001742

EM60

001744

022470
024265
025046
000000

;"XMIT DID NOT INTERRUPT'
;"'TESTA ERR PC TCSR"
sSTESTN,SERRPC,TCSR

001746
001750
001752
001754

022517
024265
025046
000000

EMET
DH1
DT1
0

J"XMIT RE-INTERRUPTED''
;"'TESTA ERR PC
TCSR"
;STESTN,SERRPC,TCSR

001756
001760
001762
27 001764

022543
024265
025046
000000

DH1
DT1

EME2

;"LOADING TBUF DID NOT CLEAR INTERRUPT"'
;"'TESTA ERR PC TCSR"

1729 001766
1730 001770
1731 001772
1732 001774

022610
024337
025066
000000

T e
B

NN
n

NN NN

[« 4V SWN=00VONO
NS WN-=00

1708

oT1
0

DH1
DT1

DH1
DT1
0

EM63

DH6
DT6

;STESTN,SERRPC,TCSR

:"RCVR ACTIVE NOT SET''
;"'TESTA ERR PC R(CSR"
JSTESTN,SERRPC
,RCSR

CZDLDHO DL11=W 11/44 MFM SLU
ERROR POINTER TABLE
NN~IN

1733 001776
1734 002000
1735 002002
1736 002004
1737

1738 002006
1739 002010
1740 002012
1741 002014
1742
1743 002016
1744 002020
1745 002022
1746 002024
1747
1748 002026
1749 002030
1750 002032
1751 002034
1752
17 53 002036
754 002040
1 755 002042
1 756 002044
1 757
758 002046
759 002050
1 760 002052
1 761 002054
762
|

)

;

1
1
1 768 002066
1 769 002070
1 770 002072
1771 002074
1772

1773 002076
1774 002100
1775 002102
1776 002104

MACRO M1113

07-JuL=81

022634
024337
025066
000000

EM64
DH6

022660
024337
025066
000000

EM6S

022726
024337
025066
000000

EM66

DH6
DT6

022764
024337
025066
000000

DH6
DT6

023027
024337
025066
000000
023074
024337
025066
000000
023243
024337
025066
000000

023136
024337
025066
000000
023174
024337
025066
000000

DT6

DH6
DT6

EME?

EM70

DH6
DT6

EM71
DH6
DT6

EM72

DH6
DT6
0

15:03

PAGE 28

SEQUENCE

;'RECEIVER DONE NEVER SET"'
;"'TESTA ERR PC RCSR''
;STESTN,$SERRPC
,RCSR

;'RCVR ACTIVE NOT CLEARED WITH DONE SET?2
;"'TEST# ERR PC RCSR"
;STESTN,SERRPC
,RCSR

;"RESET DID NOT CLEAR RCVR DONE'’
;"'TESTA ERR PC RCSR"
;STESTN,$SERRPC
,RCSR

:"RDR ENABLE SET DID NOT CLEAR RCVR DONE''
;"'TESTA ERR PC RCSR"
;STESTN, SERRPC ,RCSR

:"READING RBUF DID NOT CLEAR RCVR DONE''
;"'TEST# ERR PC RCSR''
,RCSR
;STESTN,SERRPC

:"RCVR INTERRUPTS WITH ENABLE CLEAR''
;"'TESTA ERR PC
RCSR"
sSTESTN,SERRPC
,RCSR

:"RCVR DID NOT INTERRUPT"'
;"'TESTA ERR PC RCSR"
;STESTN,$SERRPC
,RCSR

EM73

:"RCVR INTERRUPTS AT PRIORITY 7'

EM74

;"RCVR INTERRUPT REQUEST PASSED WITH ENABLE CLEAR''

DH6
DT6
0

;"'TESTA ERR PC
RCSR"
;STESTN,SERRPC
,RCSR

J"'TESTA ERR PC

RCSR"

RPC
;STESTN,$SER,RCSR

CZDLDHO DL11-W 11/44 MFM SLU

ERROR POINTER TABLE

MACRO M1113

07-JuL-81

15:03

M3
PAGE 29

SEQUENCE

1777 002106
1778 002110
1779 002112
1780 002114
1781 002116
1782 002120
1783 002122

023242
024337
025066
000000
023272
024337
025066

EM75
DH6
DT6
0
EM76
DH6
DT6

:'RCVR DID NOT INTERRUPT''
;"'TESTA ERR PC RCSR'"'
,RCSR
;STESTN,SERRPC

1786 002126
1787 002130
1788 002132

023316
024337
025066

EM77
DH6
DT6

:'READING RBUF DID NOT CLEAR INTERRUPT''
;"'TESTA ERR PC RCSR"

1791 002136
1792 002140
1793 002142
1794 002144
1795
1796
1797 002146
1798 002150
1799 002152

023363
024337
025066
000000

EM100
DH6
DT6
0

:'RESET DID NOT CLEAR RCVR INTERRUPT''
;"'TEST# ERR PC RCSR'
,RCSR
sSTESTN,SERRPC

023426
024337
025066

EM101
DH6
DT6

;"""OR" FLAG DID NOT SET"

1802 002156
1803 002160
1804 002162
1805 002164

023454
024337
025066
000000

EM102
DH6
DT6
0

:"""ERROR' NOT SET WITH 'OR' FLAG'

1808 002172

025144

DT103

;"BREAK DID NOT TRANSMIT ALL ZEROES''
;"'TESTA ERR PC RCSR DATA"
,RCSR, $BDDAT
;STESTN,SERRPC

EM104
DH6
DT6

;"BREAK DID NOT SET FRAMING ERROR''
;"'TESTA ERR PC RCSR''
,RCSR
;STESTN,$ERRPC
:"DATA COMPARE ERROR''
;"'TESTA ERR PC
RCSR
GOOD

};gg 002124

};88 002134

}gg? 002154

1806 002166
1807 002170

}g?g 002174

000000

023513
024536

000000

EM103
DH103

1811 0.~ 76
1812 002200
1813 002202

023551
024337
025066

000000

1816 002206
1817 002210
1818 002212
1819 00214

023606
024573
025156
000000

EM105
DH105
DT105
0

}g;g

2204

;'RECEIVER RE-INTERRUPTED"'
;"'TESTA ERR PC RCSR''
;STESTH,$ERRPC
,RCSR

;$TESTN,SERRPC
,RCSR

;STESTN,SERRPC
,RCSR

:"'TESTA ERR PC

RCSR''

,RCSR
;STESTN,SERRPC

s$TESTN,$ERRPC ,RCSR,GD,BD

BAD'

CZDLDHO DL11=W 11/44 MFM SLU

ERROR POINTER TABLE

1820 002216
1821 002220

MACRO M1113

07-JuL=-81

15:03

EM106
DH105

;"'LOOP-BACK DATA COMPARE ERROR''
;"'TESTH ERR PC RCSR
GOOoD
BAD"’

023666
024337
025066

EM107

;"'TIMEOUT IN EXERCISER TEST''
;"'TEST# ERR PC RCSR''
,RCSR
sSTESTN,SERRPC

8T105

sS$TESTN,$SERRPC ,RCSR,GD,BD

DH6

5 002266

1846 002270
1847 002272
1848 002274
1849
1850 002276

1857 002312
1858 002314
1859
1860 002316
1861 002320
1862 002322
1863 002324

023720
024637
025172

;"'INCORRECT RECEIVE COUNT
;"'TESTA ERR PC RCSR
TRANS
RCV''
;$TESTN,SERRPC ,RCSR,XMTCNT ,RCVCNT

023750
024573
025156
000"*)

:"DATA COMPARE ERROR IN EXERCISER'’
;"'TESTA# ERR PC RCSR
GOOD

024010
024703
025206
000000

;"'TRAP CATCHER''
J''TESTA
ERR PC

024025
024411
025106
000000

:'NO CLK INTERRUPT IN EXERCISER''

000000

BADI L}

;$TESTN,SERRPC ,RCSR,GD,BD

OLDPC

TRAP ADR''

:"'TEST#
ERR PC
LKS'
:$TESTN,SERRPC,LKS

024063
024337
025066
000000

EM114

DH6
DT6

;"""ERROR' NOT SET WITH 'FR'
:"'TESTH ERR PC
RCSR'’
:$TESTN, SERRPC ,RCSR

024122
024337
025066
000000

EM11S

JRCV ACTVIE NOT CLEAR WITH INIT

024161

EM116
DH6

FLAG'

2"'TESTA ERR PC RCSR''
RPC
,RCSR
;S$TESTN,SER

DH6
DT6

024337
025066

DT6

sRCV ACTIVE WITHOUT ‘'START'' BIT
:"'TESTA ERR PC RCSR''
PC
,RCSR
;STESTN,SERR

024220

EM117

sRDR ENABLE NOT CLEAR WITH RCV ACTIVE

000000

024337
025066

DH6
DT6
0

000000

346
1876 002412

RCSR

J$TESTN,$ERRPC ,RCSR,OLDPC ,BDVECT

000000
000000
000000
000000

:"'TESTA ERR PC
RCSR''
;STESTN,SERRPC
,RCSR

:STORAGE LOCATIONS

FIRST:

LOC1:
LOC2:
SAVEQ:

SAVLOC:
:
ENDSTK

. WORD
.WORD
.WORD
.WORD

.BLKW

—NVOOOO
on

35 0022406

SEQUENCE

023631
024573
025156
000000

000000

002244

N3
PAGE 30

:TIMER LOOP COUNTER
:TIMER LOOP COUNTER

:STORAGE FOR LOCATIONS
:THAT

T/E USES

:JIMS SPECIAL STACK (WRAP AROUND)

CZDLDHO DL11=wW 11/44 MFM SLU

ERROR POINTER TABLE

1877 002432
1878 002434
1879 002436
1880 002440
1881 002442
1882 002444
1883 002446
1884 002450
1885 002452
1886 002454
1887 002564
1888 002566
1889 002610
1890
1891
1892 002616

1893 002620
1894 002622
1895

MACRO M1113

00000C
000000
000000
000000
00CJ00
000000
000000
000000
000000
020
136

124

000
120

057

000
101

07-JuL-81 15:03 PAGE 30-1

JIMSTK:
SAVEPS:
OLDSUM:
RCVCNT:
XMTCNT:
CLKCNT:
STPSW:
SRPSW:
SCPSW:
BUF :
CNTLP:
PROMPT:
TA:

.WORD
.WORD
,WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.BLKW
.ASCIZ
.ASCII
LASCIZ
.EVEN
.WORD

000000
000020
000000

SECND:
OLDPC:
BDVECT:

000000
000000

CTSTFL:
TMP1:

.WORD
.WORD

000000
000000
000000
000000
000000
000000
000000
000000

RCSR:
RBUF:
TCSR:
TBUF:
RVECT:
RPSW:
TVECT:
TPSW:

.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD

.WORD
.WORD

0
0

SEQUENCE
;SAVE PSW AREA

;CHECKSUM STORAGE

0
0
0
0
0

44
<20>
/*P/<0><CR><LF>/CONSOLE/<CR><LF>/>>>/<377>
$T/AS<CRO<LF>

0
0
0

1896
1897
1898

1899
1900 002624
1901 002626

1902 002630
1903 002632
}ggg

1906 002634
1907 002636
1908
1909
1910
1911
1912

002640
002642
002644
002646
002650

}g}g 002652

000000
000000

}g;g
1917 002654
1918 002656
1919 002660
1920 002662
1921 002664
1922 002666

1923 002670
}ggg 002672
1926
1927 002674
1928 002676

}3%8 002700

1931 002702
1932 002742
1933 003002

0
;CONSLE UNDER TEST FLAG
0
:TEMP LOCATION FOR TABLE OFFSETS
TMP2:
.WORD
0
;TEMP LOCATION FOR DEVICE COUNT
TMP3:
.WORD
0
JLOCATION FOR DEVICE MAP BIT TEST MASK
;REGISTER AND VECTOR ADDRESSES FOR THE DL=11W UNDER TEST

0
0
0
0
0
0
0
0

s CONSOLE REGIS TER AND VECTOR ADDRESSES FOR THE DL=11w
177560
177562
177564
177566
000060
000062
000064

000066

sADDRESS OF RECEIVER COMMAND/STATUS REGISTER
;ADDRESS OF RECEIVER BUFFER
sADDRESS OF TRANSMITTER COMMAND/STATUS REGISTER
;ADDRESS OF TRANSMITTER BUFFER
;JRECEIVER INTERRUPT VECTOR

CRCSR:
177560
CRBUF:
177562
CTCSR:
177564
CTBUF:
177566
CRVECT: 60
CRPSW:
62

CTVECT: 64
CTPSW:
66

:TRANSMITTER INTERRUPT VECTOR

000102

JREAL TIME CLO (K REGISTER AND VECTOR ADDRESSES
LKS:
.WORD
177546
RTCVT:
.WORD
100
RTCPSW: .WORD
102

000000

ADRTBL: .BLKW
VCTTBL: .BLKW
FLAG44: .WORD

177546
000100

20
20
0

CZDLDHO DL11=W 1.744 MFM SLU

ERROR POINTER TABLE

1934 003004
1935 003006
1936 003010

}ggg 003012

MACRO M1113

17650C
176502
176504

07-JuL-81 15:03

TURCSR: .WORD
TURBUF: .WORD
TUTCSR: .WORD

176506

TUTBUF:

1939

132?

.WORD

PAGE 30-2

SEQUENCE

176500
176502
176504

176506

;SUBROUTINE TO GENERATE DEVICE ADDRESS TABLE

1942 003014
1943 003020
1944 003024

012702
013700
010001

1946 003032

010022

1945 003026

002702
001142

062701

000170

1948 003040
1949 003042
1950 003044

062700

020001
003773
000207

000010

1954 003046
1955 003052

005037
005037

001070
001066

1957 003062

005037

002624

1959 003072

005037

1947 003034
1951

1956 003056

1958 003066
1960 003076
1961 003102
1962 003106

1963 003110

1964 003116
}ggg 003124

005037

005037
005037
005737
001003

012737

012737
012737

DEVADR: MOV
MOV
MOV
1%:

001100

003002
001112

000400
000006
000003

001112

000004
000006

1967

1$%:
.SBTTL

012706
005026
022706
001374
012706

001000

003152
003160

012737
012737

015374
000340

000020
000022

003174
003202
003210
003216
003224
003232
003240
003244
003252
003260

012737
012737
012737
012737
012737
013737
005037
112737
012737
012737

000340
017522
000340
015212
000340
014356
001060
000001
003252
003260

000032
000034
000036
000024
000026
014350

003266

012737

013746

001040
001000

014544

000004

#10,R0
RO,R1
1%
PC

;POINT R1 TO LAST DEVICE ADDRESS
;POINT RO TO NEXT DEVICE ADDRESS

;FINISHED GENERATING TABLE?
;BR, IF LAST DEVICE ADDRESS NOT LOADED

CLR
CLR

$FATAL
$MSGTYP

s CLEAR ERROR NO.
;CLEAR MESSAGE TYPE

CLR

CTSTFL

;CLEAR CONSOLE UNDER TEST FLAG

S$TESTN

;CLEAR TEST NO.

CLR

S$DEVCT

CLR
TST
BNE

FLAG44
SUSWR
1%

;*~ CLEAR 11/44 (PU FLAG
;1S SUSWR LOADED?
:BR IF YES

HE, N
#3,a46

:INITIALIZE TIMEOUT VECTORS TO TRAP
:
CATCHER ROUTINE

CLR

MOV

MOV
MOV

SUNIT

#6400, SUSWR

INITIALIZE

sCLEAR DEVICE COUNT
;CLEAR UNIT NUMBER

;ELSE, DEFAULT TO $USWR=400

THE COMMON TAGS

;;CLEAR THE COMMON TAGS ($CMTAG) AREA

003132
003136
003140
003144
003146

003166

sMOVE DEVICE ADDRESS TO TABLE

ADD

CLR

001076

RO, (R2)+

#170,R1

CMP
BLE
RTS

001072

;POINT R2 TO THE DEVICE ADDRESS TABLE
;LOAD BASE DEVICE ADDRESS IN RO
3

ADD

MOV

START:

#ADRTBL ,R2
$BASE ,RO
RO,R1

000030

001015
001006
001010

MOV
CLR
CMP
BNE
MoV

#$CMTAG,R6
;:FIRST LOCATION TO BE CLEARED
(R6) +
;s CLEAR MEMCRY LOCATION
#SWR,R6 ; ;DONE?
-6
;:LOOP BACK IF NO
#1000, SP
;:SETUP THE STACK POINTER

MOV

#SERROR , #EMTVE C ::EMT VECTOR FOR ERROR ROUTINE

;:INITIALIZE A FEW VECTORS
MOV
#$SCOPE ,a#10TVEC ..IOT VECTOR FOR SCOPE ROUTINE
MoV
#340, a4 10TVEC+2 ;:LEVEL 7

MOV
MOV
MOV
Mov
MoV
MoV
CLR
MOvB
MOV
MOV

#340,NEMTVEC+2 ;LEVEL 7
#STRAP ,a#TRAPVEC ;;TRAP_VECTOR FOR TRAP CALLS
#340,a#TRAPVEC+2;LEVEL 7
#$PWRDN ,a#PWRVEC ;;POWER_FAILURE VECTOR
#340 ,a#PWRVEC+2 ;;LEVEL 7
SENDCT,SEOPCT
;;SETUP END~OF -PROGRAM COUNTER
$ESCAPE
;:CLEAR THE ESCAPE ON ERROR ADDRESS
#1,SERMAX
;;ALLOW ONE ERROR PER TEST
#..SLPADR
..INITIALIZE THE LOOP ADDRESS FOR SCOPE
#.,SLPERR
:SETUP THE ERROR LOOP ADDRESS

::SIZE FOR A HARDWARE SWITCH REGISTER. IF NOT FOUND OR IT IS
;.EQUAL TO A '=1"", SETUP FOR A SOFTWARE SWITCH REGISTER.
MOV

@HERRVEC,-(SP)

~;;SAVE ERROR VECTOR

—

| CZDLDHO DL11=W 11744 MFM SLU
INITIALIZE THE COMMON TAGS

003272
003300
003306
003314
003322

012737
012737
012737
022777
001012

003324
003326
003332

000403
012716
000002

000004
001040
001042
175516

003334

648 :

003334
003342
003350
003354
003360

012737
012737
012637
005037
132737

000176
000174
000004
001074
000200

001040
001042

003370
003376

012737

001110

003366

1968

003326
177570
177570
177777

MACRO M1113

001403

65%:

07-JuL-81

15:03

—————

PAGE 30-3

MOV
MOV
MOV
CMP
BNE

#64$ ,Q¥ERRVEC
#DSWR, SWR
#DDISP,DISPLAY
#-1,aSWR
66%

BR
MOV
RTI

65%
#65%, (SP)

BEQ

67%

SEQUENCE

;;SET UP ERROR VECTOR
;:SETUP FOR A HARDWARE SWICH REGISTER
;;AND A HARDWARE DISPLAY REGISTER
::TRY TO REFERENCE HARDWARE SWR
s sBRANCH IF NO TIMEOUT TRAP OCCURRED
;:AND THE HARDWARE SWR IS NOT = =1
s sBRANCH IF NO TIMEOUT
::SET UP FOR TRAP RETURN

001107

MOV
MOV
MoV
CLR
BITB

#SWREG, SWR
:;POINT TO SOF TWARE SWR
#D1SPREG,DISPLAY
(SP)+,a#ERRVEC
;;RESTORE ERROR VECTOR
$PASS
;s CLEAR PASS COUNT
#APTSIZE ,$ENVM ;;TEST USER SIZE UNDER APT

001040

MOV

#SSWREG, SWR

668%:

67%:

}g?g

;s YES,USE NON-APT SWITCH

;:NO,USE APT SWITCH REGISTER

;SIZE FOR 11/44 CPU

1971 003376
1972 003402
1973
1974
1975
1976

—

003410
003412
003416
003420

1977 003426
1978 003430
1979 003434
1980 003436
1981 003442

1982 003450
1983 003452

1984 003456
1985 003462

013746
012737

000007
122700
001007
052737

000403
012716

000010
003430

000001

000137
132737

004620
000001

001106

132737

000200

001107
175330

001056

032777
001052

000040

1992
1993
1994
1995
1996
1997

003512
003516
003522
003526
003532
003540

004737
005037
005037
013703
012737
013700

003014
002630
001144
000004
003562
001142

1999 003550

005710

2000 003552
2001 003556
2002 003562
2003 003566
2004 003572
2005 003576
2006 003602
2007 003604

062700

005237
005237
012706
006337
162700
023700
003762
013700

175370

11%:

002624

1988 003500

1998 003544

10%:

000010
000020

001404

1989 003502
}% 003510

003002

003436

1986 003470

1987 003472

MFPT
CMPB
BNE
BIS

000001

012637
032777
001404

005237

MOV
MOV

000010

000160

001144
002630
001000
001144
000010
001142
002654

INIT:

BR
MOV
RTI
MOV
BIT

BEQ
INC
JMP

BITB

SIZE:

000004

3$:

4%:

#1,RO
11%
#1,NF LAGLS

118%
#118%,(SP)

(SP)+,a#10
#B1T4 ,aSWR
INIT
CTSTFL

ID
#BITO, SENV

BEQ

MANL

BNE

APTSZD

BITB

MANL:

a#10,-(SP)
#10%,a#10

BIT
BNE

#BIT7,SENVM
#BITS5,aSWR
APTSZD

;%% SAVE VECTOR
;** SET UP FOR TRAP
J*x
;**
s**
;%%

WHAT CPU??
ARE WE A 11/44
NO GO RESET VECTOR
YES SET FLAG

;%% SKIP RTI
s*x SET STACK RETURN
s** RETURN
;** RESTORE VECTOR
sTEST CLOCK ONLY?

:BR_IF NOT
JELSE, SET CONSOLE TEST FLAG TO ENABLE CLOCK TESTS
"
AND JUMP TO TYPE PROGRAM ID

:CHECK IF ON APT
:BR IF NOT APT

;DID APT SIZE
:BR,

IF APT SIZED

;WAS ''SDEVM'' MANUALLY SET?
;IF YES, SKIP SELF=SIZING

JSR
CLR
CLR
MOV
MOV
MOv

PC,DEVADR
TMP2
$DEVM
44 ,R3
#4S , N4
$B8ASE RO

sGENERATE DEVICE ADDRESS TABLE
sCLR TEMP LOCATION TO KEEP DEVICE COUNT
;CLEAR DEVICE MAP
sSAVE TIMEOUT VECTOR
;SET TIMEOUT POINTER
;LOAD BASE ADDRESS

TST

(RO)

;CHECK FOR DEVICE EXISTANCE

ADD

INC
INC
MOV
ASL
Su3
CMP
BLE
Mov

#160,R0

$DEVM
TMP2
#1000,SP
$DEVM
#10,R0
$BASE RO
3%
CRCSR,RO

sPOINT RO TO UNIT #15

(UNITA#0=CONSOLE)

sINDICATE DEVICE EXISTANCE IN DEVICE MAP
s INCREMENT DEVICE COUNT
JRESET STACK POINTER
sADJUST DEVICE MAP FOR NEXT UNIT CHECK
;POINT RO TO NEXT DEVICE NUMBER
sFINISHED SIZING?
;BR, IF BASE ADDRESS HAS NOT BEEN CHECKED
;LOAD CONSOLE DEVICE ADDRESS

| CZDLDHO DL11-4 11744 MFM SLU
| INITIALIZE THE COMMON TAGS

|
.

2008 003610

2009 003616
2010 003620
2011 003624
2012 003630
2013
2014 003634
2015
2016 003636
2017 003642
2018 003646
2019 003650
2020 003652
2021 003656
2022 003660
2023 003662
2024 003664
2025

-2028 003670
2029 003674
2030 003700
2031 003704
2032 003706
2033 003712
2034 003714
2035 003720
2036 003722

012737
005710
005237
005237
010337

003630

MACRO M1113 07-JuL=-81 15:03 PAGE 50-4
000004

001144
002630
000004

Moy
TST
INC

5%:

000415
005037
013702
005702

002630
001144

005237
006302
001401
000771
004737

002630

100002

INC
MOV
BR

VCTADR

;BR TO GENERATE VECTOR ADDRESS TABLE

TMP2
$DEVM,R2
R2
1%
TMP2
R2

;CLEAR TEMP LOCATION TO KEEP DEVICE CNT
sMOVE DEVICE MAP TO R2

CLR
MOV
TSTDVM: TST
BPL

003014

DVADT:

INC

ASL

BEQ
BR
JSR

DVADT

TSTDVM
PC.DEVADR

;SET UP TIMEOUT POINTER

(RO)
SDEVM
TMP2
R3,a#4

APTSZD:

1%:

#5%,an6

SEQUENCE

sTEST

FOR CONSOLE EXISTANCE

;INDICATE CONSOLE EXISTANCE IN DEVICE MAP
s INCREMENT DEVICE COUNT
JRESTORE

TIMEOUT VECTOR

;TEST MSB OF

:BR,

DEVICE MAP

IF MSB IS ZERO

s INCREMENT DEVICE COUNT,

IF MSB=1

*SHIFT NEXT BIT INTO MSB POSITION

:BR, IF NO OTHER BITS ARE SET IN SDEVM
;CONTINUE CHECKING SDEVM, IF MORE BITS SET
;GENERATE DEVICE ADDRESS TABLE

;GENERATE VECTOR ADDRESS TABLE
012702
013700
042700
010001
062701
010022
062700

002742
001136
177000

000170

000010

VCTADR: MOV
MOV
BIC
MOV

#VCTTBL,R2
Q#SVECTT,RO
#177000,R0
RO,R1

1$:

RO, (R2)+
#10,RO

ADD

MOV
ADD

CMP
BLE

#170,R1
RO,R1
1%

JGET LOCATION OF VECTOR TABLE
; COPY BASE VECTOR

:CLEAR UPPER BITS

;POINT R1 TO LAST DEVICE VECTOR
sPUT VECTOR ADDRESS IN TABLE
sPOINT RO TO NEXT VECTOR ADDRESS

;FINISHED GENERATING VECTOR TABLE?
:BR, IF LAST VECTOR IS NOT LOADED

:MOVE DEVICE COUNT INTO DEVICE COUNT MESSAGE

MOV

002630

SHIFT:

204
2047 003744
2048 003746

2049 003750
2050 003752
2051 003754
2052 003760
2053 003762
2054 003766
2055 003770
2056
2057
2058 003774
2059 004002
2060 004006
2061 004014
2062 004016
2063 004020
2064 004024

025016

052737

000002
002626
000001
002624
002654

ASL

ROLB

ADD
SWAS
BIT
BEQ
MOV

000020

010137

R1
RO
RO
RO
RO

ROLB
ASL
ROLB

000060

002632

BEGIN:

001144

BIS
CLR
BIT

BNE
TCONS:

TMP2,R0

CLR
SWAB
ASL
ASL
ASL

INC

MOV

RI1
RO
R1
#60,R1
R1

#B1T4,R1
SHIFT

R1,M2A

;COPY DEVICE COUNT INTO RO

CLEAR AUXILARY REGISTER

PUT DEVICE COUNT IN UPPER BYTE OF RO
MOVE MSB OF COUNT INTO

:MSB OF RO
:PUT MSB OF COUNT INTO CARRY
JMOVE MSB OF COUNT INTO R1
JMOVE NEXT BIT TO CARRY
JMOVE INTO R1
:MOVE LAST BIT OF DIGIT
;INTO R1
;CONVERT DIGIT TO ASCII

;MOVE DIGIT TO UPPER BYTE
;HAVE BOTH DIGITS BEEN MOVED TO R1?
*BR, IF NOT

MOVE DEVICE COUNT TO OUTPUT MESSAGE

TSTDEV

;3 T UP BIT MASK TO TEST $DEVM FOR DEVICES EXCEPT CONSOLE
; CL EAR LOCATION TO STORE TABLE OFFSETS
;1S CONSOLE TO BE TESTED?
;BR . IF CONSOLE IS TO BE TESTED
., TO TEST OTHER DEVICES

#CRCSR,RO

;SET

#BIT1,TMP3
TTMP1
#8170, $DEVM

TCONS

CTSTFL

N?ICATE CONSOLE UNDER TEST

UP CONSOLE DEVICE ADDRESSES

DLDHO DL11-w 11744 MFM SLU
ITIALIZE THE COMMON TAGS

—a

oo
O SO0y

—

228528 $88E38EE

wviwn S bl\r
fOSNVONNVSO

2065 004030

012701
012021
022701
002374
000137

002634

033737
001010
006337
062737
005237
000764

002632

005237
006337
013702
062737

001100
002632
002626
000002
002702
002634

016200
012701
010021
062700
030027
001372

016200
010021
062700
030027
001372
000137

MACRO M1113

07-JuL=-81

1%:

002652
004172

001100

000002
000006

002742
000002
000006
004172

MOV
MOV
CMP
BGE

JMP

001144

002626

15:03

PAGE 30-5

#RCSR,R1
(RO)+,(R1)+
#TPSW,R1
1%

SEQUENCE

sPOINT R1 TO UUT ADDRESS TABLE
s TRANSFER CONSOLE ADDRESSES
sFINISHED TRANSFER?

;BR, IF NOT
;GO TEST CONSOLE INTERFACE

;PREPARE ADDRESSES AND VECTORS F OR WUT

TSTDEV: BIT
BNE
ASL
ADD
INC

;CHECK TO SEE IF DEVICE IS TO BE TESTED
;BR, IF YES

TMP3, SDEVM
SETADR
TMP3
#2,TMP1
SUNIT
TSTDEV

SETADR:

INC
ASL
MOV
ADD

SUNIT
TMP3
TMP1 ,R2
#2,TMP1

sUPDATE UNIT NUMBER
;UPDATE DEVICE MAP TEST MASK

002626
ADR:

s INCREMENT TABLE INDEX
s INCREMENT UNIT NUMBER
;GO TEST NEXT BIT OF DEVICE MAP

;MOVE TABLE OFFSET TO R2
sUPDATE TABLE OFFSET FOR NEXT DEVICE
;PUT UUT ADDRESS INTO RO
;POINT R1 TO STORAGE AREA FOR UUT ADDRESSES

MOV
MOV
MOV
ADD

ADRTBL
(R2) ,RO
#RCSR,R1
RO, (R1)+
#2,RO

BNE

ADR

; TRANSFER UUT ADDRESS
sPOINT TO NEXT UUT REGISTER
sF INISHED TRANSFER?
:BR, IF NOT

MOV
MOV
ADD
BIT
BNE
JMP

VCTTBL
(R2) ,RO
RO, (R1)+

s TRANSFER UUT

BIT

VECT:

JSHIFT MASK TO CHECK NEXT $DEVM BIT

RO, 46

#2,R0O

RO, #6
VECT
TST1

;PUT UUT VECTOR INTO RO
VECTORS

sPOINT TO NEXT VECTOR
;FINISHED TRANSFER?
:BR, IF NOT
;GO TEST DEVICE

TO ACTIVE

TABLE

AREA

(ZDLDHO DL11=w 11/44 MFM SLU
TEST

TEST

ABILITY

MACRO M1113 07-JUL=-81 15:03 PAGE §1

TO REFERENCE

SEQUENCE

TCSR

2096

LSBTTL

TEST # 1 -« TEST ABILITY TO REFERENCE TCSR

.-'-tttntt.'t'l'tttttt'ttttt""t.'tttt'!'ttfit'ttttttt...tttt..""

;*TEST

TEST ABILITY

TO REFERENCE

TCSR

.';Q.t't'.""ttl'ttttt."'t.'QQQQQQQlttt'tttttt't.ttt't'.t't't't'

004172
2097 004174
2098 004200

000004
013703
012737

000004
004214

2102 004214
2103 004216

022626
005737

002624

2105 004224
2106 004226
2107 004230
004230
004234
08 00423¢

104001
000404

099 004206
5}8? 004212

2104 004222

0C4240

005777
000412

001002

004737
000001
000000

010337

176426

015714

000004

1ST1:
000004

SCOPE
MOV
MOV

a#é R3
#8084

;SAVE TIMEOUT VECTOR
JSET Ul TIMEOUT VECTOR

cMP
TST

(SP)+,(SP)+
CTSTFL

JRESTORE SP AFTER TIMEOUT
JCHECK IF DEVICE IS CONSOLE

ERROR
BR

+1
4%

:REPORT ERROR TO APT & TTY
;BR TO END OF TEST

JSR
1
HALT

PC,3ATYS

TST
BR

1%:

BNE
2%:
3%:

L$:

MOV

aTCSR
4%

R3,a#44

JREFERENCE THE XMIT COMMAND/STATUS REG.
; GO TO END OF TEST

:IF YES, SKIP ERROR TYPEOUT

::ONLY REPORT A FATAL ERROR
::THE ERROR NUMBER (FROM APT LIST)

JRESTORE TIMEOUT VECTOR

' CZDLDHO DL11=w 11/44 MFM SLU
MACRO M1113
TEST & 2 < TEST ABILITY TO REFERENCE TBUF
2113

07-JuL=-81 15:03

.SBTTL

PAGE 32

SEQUENCE

TEST # 2 = TEST ABILITY TO REFERENCE TBUF

.'.'Q."Q.t.t".t't!'t"..""Q.'.""....".Qt'.t"'.".Q't.'..t'.

STEST 2

TEST ABILITY TO REFERENCE

TBUF

.'.’".'t"'.t""'...'.'"'."'*"Q.'.'...".'Q'.'Q..t't".ttt...'

006244
2114 004246
2115 004252
2116 004260
S}}; 004264

000004
013703
012737
005777
000412

2119 004266
2120 004270
2121 004274
2122 004276
2123 004300
2124 004302
004302
004306
2125 004310
2126 004312

022626
005737
001002
104002
000404

004737
000002
000000
010237

000004
004266
176356

002624

015714
000004

t§12:

scoPE
MOV
MOV
ST
BR

a6 ,R3
#1S.
A1BUF
4$

;SAVE TIMEOUT VECTOR
:SET UM TIMEOUT VECTOR
:REFERENCE THE XMIT BUFFER
:GO TO END OF
TEST

18:

CMP
TST
BNE
ERROR
BR

(SP)+,(SP)+
CTSTFL
2%
+2
4$

;RESTORE SP AFTER TIMEOUT
*CHECK IF DEVICE IS CONSOLE
:IF YES, SKIP ERROR TYPEOUT
:REPORT ERROR TO APT & TTY
‘BR TO END OF TEST

JSR
2
HAL
T
MOV

PC,SATY4

000004

2%:
3%:
L$:

R3, 44

:;ONLY REPORT A FATAL ERROR
:*THE ERROR NUMBER (FROM APT LIST)
;RESTORE

TIMEOUT VECTOR

r——

SR—

—

c——————————————————————

|
' CZDLDHO DLY11=wW 11/44 MFM SLU

' TEST # 3 = TEST

|
!

MACRO M1113

THAT BIT2(MAINT, BIT)

2127

—
e

—

07-JuUL-81 15:03
SET & RESET

SBTTL

I_4&
PAGE 33

SEQUENCE

TEST # 3 = TEST THAT BIT2(MAINT. BIT)

CAN BF SET & RESET

;.-tttttttttttt'ttt.ttt't""..tt.t"t.'tt!tttQ.t""'t"ttt't."'

;*TEST 3

|
s
|
,

CAN BE

TEST THAT BIT2(MAINT. BIT)

CAN BE SET & RESET

.-:'tttt't"t't'!tlt...t't'Qttt.tt."tt'ttt'ttt.tt"tt"tttt'ttttt

004316
2128 004320
2129 004322
51%9 004330

000004
000005
032777
001411

2132 004332
2133 004336
2134 004340
g;gz 004342

005737
001002
104015
000404

002624

2137 004344
004344
004350
gggg 004352

004737
000015
000000

015714

2140 004354
2141 004362
S12§ 004370

052777
032777
001001

000004
000004

gng 004372

104016

2146 004374
2147 004402

042777
032777

000004
000004

2150 004412
2151 004416

005737
001002

002624

2153 004422
2154 004424
004424

000404

S}zg 004410

2152 004420

001411

TS73:

000004

176310

1%:
2%:

176256
176250

176236
176230

4$:

5%:

004430
S}gg 004432

015714

2157 004434
2158 004442
2159 004444
g}g? 004452

052777
000005
032777
001404

000004

176176

000004

176166

2162 004454
2163 004462

042777
104020

000C04

176156

2166 004464

000240

#31T2,aTCSR
3%

TST
BNE
ERROR
BR

CTSTFL
1%
+15
3%

JSR
15
HALT

PC,SATY4

BIS
BIT
BNE

#BIT2,aTCSR
#BIT2,aTCSR
43

:SET BIT2 OF TCSR
:TEST FOR BIT2 SET
:BR IF SET

ERROR

+16

:BIT2 OF TCSR WILL NOT SET

BIC
BIT

#BIT2,aTCSR
#BIT2,aTCSR
7%

:CLEAR BIT2 OF TCSR
:TEST BIT2 CLEAR

:BR IF

TST
BNE
ERROR
BR

CTSTFL
5%

:CHECK IF DEVICE IS CONSOLE
:I1F YES, SKIP ERROR TYPEOUT

JSR
17
HAL T

PC,3ATY4

::ONLY REPORT A FATAL ERROR
::THE ERROR NUMBER (FROM APT LIST)
:BITO OF TCSR WILL NOT CLEAR

BIS
RESET
1T
BEQ

#BIT2,aTCSR

:SET BIT2 OF TCSR
:CLEAR BIT2 WITH RESET
;TEST FOR BIT2 CLEAR
:** |F CLEAR, GO TO NEXT TEST

BIC
ERROR

#B]T2,aTCSR
+20

BEQ

104017

004737
000017
000000

5}2@

3%:

SCOPE
RESET
BIT
BEQ

6%:
7%:

108:

NOP

+17

;CLEAR EVERYTHING
;TEST TOR BIT2 OF TCSR CLEAR
:BR IF CLEAR
;CHECK IF DEVICE IS CONSOLE
:1F YES, SKIP ERROR TYPEOUT
:BIT2 OF TCSR NOT CLEAR AFTER RESET

::ONLY REPORT A FATAL ERROR
::THE ERROR NUMBER (FROM APT LIST)

CLEAR

#BIT2,aTCSR
108

:CLEAR BIT2, TO PRINT ERROR

:RESET DID NOT CLEAR BIT2 OF TCSR
-

| CZDLDHO DL11=W 11744 MFM SLU

MACRO M1113

TEST # 4 - TEST THAT TCSR BIT7(DONE)

07-JUL=-81 15:03

CLEARS WHEN XBUF

2167

.SBTTL

IS LOADE

J 4
PAGE 34

SEQUENCE

TEST # & = TEST THAT TCSR BIT7(DONE)

SRR

S*TEST &

CLEARS WHEN XBUF

IS LOADED

2222 2222220222232
2222
]

TEST THAT TCSR BIT7(DONE)

CLEARS WHEN XBUF

IS LOADED

NN
88
ro oo

NES
oro
no

002624

wgdgogwgm

D
D
D —d
e
D

100014

000004

176142

7814

BPL

176122

1$:

015714

c$:
176060

4%:

002624
000004

176056

5%:

015714

+3
3%

JSR

PC,$ATY4

;;ONLY REPORT A FATAL ERROR
;s THE ERROR NUMBER (FROM APT LIST)
;TCSR "DONE'‘ NOT CLEARED WITH TBUF FULL
;CLEAR TIMER
;CHECK FOR XMIT DOME
;IF DONE SETS, BR TO END OF TEST
s INCREMENT TIMER
;BR IF TIMER NOT DONE

CTSTFL

;CHECK IF DEVICE IS CONSOLE

HALT
CLR
TST8B
BMI

BNE
BIC

5%
#B1T2,aCTCSR

ERRCR
BR

+4
ID

JSR

PC,$ATY4

#BIT2,aCTCSR

023737

000042

000046

CMP
BEQ

L2, akL6
6%
$PASS
6%
$DEVCT
6%

TST

s*x% WITH TERMINAL.

;:TCSR "DONE'' DOES NOT SET
;BR TO END OF TEST
;;ONLY REPORT A FATAL ERROR
;:THE ERROR NUMBER (FROM APT LIST)

;** DISABLE MAINTENANCE MODE FOR
;** CONSOLE TO ALLOW FOR COMMUNICATION

BIC

BNE

;%= DISABLE MAINTENANCE MODE FOR
s** CONSOLE TO ALLOW FOR COMMUNICATION

;** BR TO NEXT TEST,

176032

TST

sCHECK IF DEVICE IS CONSOLE
;IF YES, SKIP ERROR TYPEOUT
;** DISABLE MAINTENANCE MODE FOR
;** CONSOLE TO ALLOW FOR COMMUNICATION
s** WITH TERMINAL.
;DONE NOT CLEARED WITH TBUF FULL
:BR TO END OF TEST

ENDB?7

000004

001076

s
FIRST TEST TJ FAIL
;FILL DOUBLE BUFFER
s CHECK DONE
:BR IF CLEAR

ERROR
BR

CTSTFL

042777

001074

sFILL SECOND BUFFER, BECAUSE REFRESH (OULD CAUSE

#B1T2,aCTCSR

HALT

000427

2204 004626
2205 004634
2206 004636
2207 004642
2208 004644
2209 004650

aTBUF
aTCSR

;** ENABLE MAINT. WRAP
;LOAD ABUF
s CHECK DONE
:BR IF CLEAR

TST
BNE
BIC

TST

000405

2202 004620
2203 004620

aTBUF
aTCSR

INC
BNE

104004

004737

TSTB

005200
001373

005737
001005
042777

BPL

CLR

104003

100417

#RIT2 ,QTCSR

TSTB

000404

004737
000003
000000
005000
105777

SCOPE
BIS
CLR

s*~ AND SKIP THE TYPEOUT THAT FOLLOWS
;**
BECAUSE OF THIS FAILURE

222

v Rl
Voo

005737
001005
042777

O O O O 00 0o 0o Qo 0o

176140
176132

176126
176120

2181 004536
2182 004540
2183 004542
004542

—

100021

000004

005077
105777

2179 004526
2180 004530

rorororROrRORONRONONO
N

000004
052777
005077
105777

JFFNINIIDS

D
i
i
e
i
i

b —

~ NNNNNN VYV
oo

~n oo
NN NON

':'t'itttt.tlt"Qtttitt.t"'ttt'.t'.t.t.'.".'t'tit't.t.i'tfi.."Q

;** WITH TERMINAL.

;UNDER ACT11?
:IF YES, SKIP IDENT. TYPEOUT
;IS THIS THE FIRST PASS?
sIF NOT BR TO NEXT TEST & SKIP THE IDENTIFICATION TYPEQUTS
2IS THIS THE FIRST SUBPASS?

;IF NOT, BRTO NEXT TEST

CZDLDHO DL11=W 11/44 MFM SLU

MACRO M1113

TEST # 4 = TEST THAT TCSR BIT7(DONE)

2210 004652
2211 004654
2212 004656
2213 004660
2214 004662
2215 004670
2216 004672
2217 004676
2218 004676
004700
004704
004706
004710
004712

07-JuL=-81 15:03

CLEARS WHEN XBUF

005000
012701
005300
001376
005301
001374

PAGE

SEQUENCE
;TYPE PROGRAM INDENTIFICATION

TYPE

104401

024754
104401
025014
032777
001402
000137

IS LOADE

;TYPE NUMBER OF DEVICES UNDER TEST

000020

005536
000002

1764150

68:

ENDB7:
40%:

#BIT4 ,aSWR

;CLOCK TEST ONLY?

ENDB7

;** BR IF NOT

RO
#2.R1
RO
40%
R1
«0%

;%% DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS

TCLOCK

sELSE, JUMP TO TEST CLOCK
;%% THAT MIGHT BE

IN THE PROCESS OF BEING

;** TRANSMITTED TO FINISH BEFORE MAINTENANCE

;** WRAP FOR THE UART UNDER TEST

IS DISABLED.

s*% THIS WILL INHIBIT ANY COMMUNICATION
;%% TO HARDWARE MEDIA SUCH AS TUS8 THAT MIGHT
;%% BE ATTACHED TO UART UNDER TEST.

(ZDLUHO DL11=W 11744 MFM SLU

MACRO M1113

07-JUL-81 15:03

TEST # 5 = TEST THAT TCSR "DONE'' SETS WITH RESET

2219

LSBTTL

;*TEST 5

2220 004716

2221 004724
2222 004730
2223 004734
2224 004736
2225 004742
2226 004744
2227 004746
Sg%g 004752

000004

052777

005077
105777
100375
005077
000240
000005
105777
100401

%%g(‘) 004754

104005

2232 004756
2233
2234

000240

000004

175712
175704

175714

SCOPE

175700
175666

BIS

CLR
TSTB
BPL
CLR
NOP
RESET
TSTB
BMI]
ERROR

10%:

SEQUENCE

AR AR AR

RNARRRA

AR ARNR AR AR

RRARR AR AR RN

TEST THAT TCSR "DONE’' SETS WITH RESET

1ST5:
1%:

PAGE 35

TEST # 5 = TEST THAT TCSR "DONE'' SETS WITH RESET

PIREREARRERRAARRR AR AR

004714

—

NOP

#RIT2,aTCSR
aTBUF
al{SR
1%
aTBUF

;** ENABLE MAINT. WRAP
sLOAD TRANSMIT BUFFER
JWAIT FOR DONE
;LOAD SECOND BUFFER

aTCSR

;CLEAR DONE WITH RESET
;CHECK FOR DONE SET

+5.

;TCSR 'DONE’' DOES NOT SET WITH RESET

10%

;** BR TO NEXT TEST IF DONE SET

CZDLDHO DL11=w 11/44 MFM SLU

MACRO M1113

TEST # € = TEST ABILITY TO ACCESS RCSR

07-JuL-81 15:03

.SBTTL

2235

PAGE 36

SEQUENCE

TEST # 6 = TEST ABILITY TO ACCESS RCSR

2222332233323

S*TEST 6

3233322222202

222222

2222222203222

2RR0222R2 ]

TEST ABILITY TO ACCESS RCSR

':!'ttt‘t"tt.tltt*ttfi""'t't..'t'.t.fi'!tt""t.'fiit"t.'tt'.'it

000004

013703
012737
005777
000402
2241 005002
2242 005004
2243 005006

000004
005002
175634

022626

104006

010337

T§T6:
000004

1%:

000004

2%:

SCOPE

MOV
MOV
ST
BR

CMP
ERROR

MOV

;SAVE TIMEOUT VECTOR
;SET UM TIMEOUT VECTOR

sACCESS RCSR

;BR TO END OF TEST
(SP)+, (SP)+

+6
R3,a#44

JRESTORE SP AFTER TIMEOUT

s CAN NOT ACCESS RCSR
JRESTORE TIMEOUT VECTOR

CZDLDHO DL11=W 11/44 MFM SLU

MACRO M1113

TEST # 7 < TEST ABILITY TO ACCESS RBUF

2244

07-JuL-81

N_&
PAGE 37

SEQUENCE

TEST # 7 = TEST ABILITY TO ACCESS RBUF

.SBTTL
S

15:03

A AR A A AR A A A AR A AR

S*TEST 7

AR AR AR AR AR AR

AR AR

AR AR AR AR

TEST ABILITY TO ACCESS RBUF

AL AAALLAttt
ittt iRl
i ittt ittt
ittt td )

005012
2245 005014
2246 005020
2247 005026
2248 005032
2249
2250 005034
2251 005036
2252 005040

000004
013703
012737
005777

000402

000004
005034
175604

022626

104007
010337

T§17:
000004

ST
BR

1%:

000004

SCOPE

MOV
MOV

2%:

CMP
ERROR

MOV

¥4 R3

1S, ans
aRBUF

(SP)+,(SP)+
+7

R3,a#44

sSAVE TIMEOUT VECTOR

sSET UM TIMEOUT VECTOR
sACCESS RBUF
:BR TO END OF TEST
sRESTORE SP AFTER TIMEOUT
s CAN NOT ACCESS RBUF
sRESTORE TIMEOUT VECTOR

MACRO M1113 07-JuL-81 15:03 PAGE 38
CZDLDHO DL11=W 11/44 MFM SLU
TEST # 10 = TEST THAT BITO(BREAK BIT) CAN BE SET & CLEARED & R

LSBTTL

2253

SEQUENCE

TEST # 10 = TEST THAT SITO(BREAK BIT) CAN BE SET & CLEARED & RESET

2232333232333

TRTEST 10

3322322222222

222 2222

222222

2Rt

)

TEST THAT BITO(BREAK BIT) CAN BE SET & CLEARED & RESET

':t'tt'ti'tttt'ltt't't.""'.t"tQ'Qt.l..t""".".'.'Qt"."'..

005044
2254 005046
2255 005054
2256 005056
2257 005064

000004
032777
001475
032737
001407
005737

2260 005072
2261 005074
2262
2263 005102
2264
2265 005104
2266 005106
2267 005114
2268 005116
2269 005122
2270 005124
2271 005126
2272 005130
005130
005134
2273 005136
2274
2275 005140
2276 005146
2277 005154
2278
2279 005156
2 280
2281 005160
2282 005166
2283 005174
2284 005176
2285 005202
2286 005204
2287 005206
2288 005210
00510
005214
2289 005216
2 290
2291 005220
2292 005226
2293 005230
2294 005236
2295 005240
2296 005246
2297 005250

001404
032777

000400

173764

000001

003002

7§7T10:

002624

000010

173736

001462

000005
032777
001411
005737
001002
104011
000404

000001

175524

9%:

002624

004737
000011
000000

015714

052777
032777
001001

000001
000001

SCOPE
BIT
BEQ
BIT
BEQ
TST

2%:
175472
175464

3%:

104012

;1S BREAK FUNCTION ENABLED?

9%
CTSTFL

sxx

sx%x

108
#BITO,FLAGSLS

BEQ
BIT

#B1T03,aSWR

BEQ

108

RESET

BIT
BEQ
TST

1%:

#R]1T8,aSWR

BNE
ERROR
BR

JSR
1
HALT

#B1T0,aTCSR
3%
CTSTFL
1%
+11
3%

PC,$ATYS

#BITO,aTCSR
#81T70,aTCSR

. k&

;CLEAR EVERYTHING

;CHECK BITO OF TCSR CLEAR
;BR IF CLEAR
;BITO WAS NOT CLEAR AFTER RESET
;;ONLY REPORT A FATAL ERROR
;s THE ERROR NUMBER (FROM APT LIST)

;SET BITO IN TCSR

;CLEAR BITO OF TCSR
;TEST BITO OF TCSR

052777
000005

000001

175412

000001

175402

#31T7T0,aTCSR

000001

175372

#31T0,aTCSR

;glro.arcsn
CTSTFL
5%
+13
7%

PC,SATY4

#31T70,aTCSR
108

108
:

Mk LSST BE PERFORMED

#BITO,aTCSR

6%:
7%:

;#% THIS IS THE CONSOLE SLU.SHOULD THE BREAK

;BITO OF TCSR WILL NOT SET

015714

5%:

IS THIS THE CONSOLE

+12

004737
000013
000000

002624

;** YES THIS IS 11/44.
;xx SLU

;TEST BITO OF
;BR IF SET

000001
000001

(%:

;x% [S THIS A 11/44

IF NOT

042777
032777
001411
005737
001002
104013
000404

175452
175444

;*% BR TO NEXT TEST,

+14

TCSR

;BITO OF TCSR WILL NOT CLEAR
;;ONLY REPORT A FATAL ERROR
;s THE ERROR NUMBER (FROM APT LIST)

;SET BITO IN TCSR
:CLEAR BITO WITH RESET
;TEST BITO CLEAR

;** BR IF CLEAR
;CLEAR BITO, TO PRINT ERROR
JRESET DID NOT CLEAR BITO OF TCSR

53
TM -

MACRO M1113 07-JuL=-81 15:03
TEST THAT BIi6(XMIT INT EN) CAN BE SET & RESET

| zDLD
C
NO 1 =W 11744 MFM SLU

TEST »

2298

.SBTTL

C 5
PAGE 39

SEQUENCE

TEST # 11 = TEST THAT BIT6(XMIT INT EN)

CAN BE SET & RESET

:;'t.'t"tt.t'ttttit't.Q't"t'tQ'Qt'ttt'i't."'t'."'t"t't.t'...

J*TEST N

TEST THAT BIT6(XMIT INT EN)

CAN BE SET & RESET

::tt'ttltlttt'.ttt"tt't'it'.ttt*"""Qt.'.t't.'.fi."Ql""tt"'

005252
2299 005254
2300 005256
2301 005262
2302 005270
2303 005274
2304 005276
2305 005304
2306 005306
09

000004
000005
017703
012777
004737
000340
032777
001404

175366

005312
014502

‘175360

000100

175334

SCOPE
RESET

aTVECT,R3

#18,aTVECT
PC,WRPSW

.WORD

104021

000402

022626

2314 005316
2315 005324
2%16 005332
231
2318 005334
2319
2320
2321 005336
2322 005344
2323 005352
2324 005354

052777
032777
001001

1%:

104022

2%:

000100
000100

104023

042777
032777
001401
104024

000100
000100

052777
000005
032777
001401

000100

175254

000100

175244

175274
175266

3%:

4%:

104025

010377

175244

340

#BIT6,aTCSR

2%
+21

2310 005312
2311 005314

2330 005374
2331
2332 005376
2333
2334 005400

IsTit:

5%:

(SP)+,(SP)+

+22
BIS

#BIT6,aTCSR

§§1T6.STCSR

ERROR

+23

BIC
BIT
BEQ
ERROR

#BIT6,aTCSR
#BIT6,aTCSR

+24

BIS

#BIT6,aTCSR

BIT
BEQ

#BIT6,aTCSR

ERROR

+25

MOV

R3,aTVECT

RESET

:CLEAR EVERYTHING
sSAVE AMIT VECTOR

;SET UP INTERRUPT VECTOR FOR ERROR REPORT

;SET PSW TO PRIORITY=7

;TEST BIT6 OF TCSR
;BR IF ZERO
;BIT6 IN TCSR NOT CLEAR AFTER RESET
JRESTORE

SP AFTER

INTCRRUPT

;XMIT INTERRUPT OCCURRED

PRIO=7

;SET BIT6 OF TCSR
;TEST BIT6 OF TCSR
;BR, IF SET

;CANNOT SET BIT6 OF TCSR
;CLEAR BIT6 OF TCSR

;TEST BIT6 OF

:BR IF CLEAR

TCSR

s CANNOT CLEAR BIT6 OF TCSR

;SET BIT6 OF TCSR
sCLEAR BIT6 WITH RESET
;sTEST BIT6 OF TCSR
:BR IF CLEAR
s CANNOT CLEAR BIT6 OF TCSR WITH RESET
JRESTORE XMIT VECTOR

CZDLDHO DL11=wW 11/44 MFM SLU

MACRO M1113

07-JUL-81

TEST # 12 = TEST THAT BIT6 OF RCSR CAN BE SET & RESET

LSBTTL

2335

2358 005470
2359 005476
2360 005504
2361
2362 005506
2363
2364
2365 005510
2366 005516
2367 005520
2368 005526
2369
2370 005530
2371
2372 005532
2373 005536

005444
014502

175222

000100

175176

AR R RARARAARAARRNAAARARA
AR AR

TEST THAT BIT6 OF RCSR CAN BE SET & RESET
2R

SCOPE

RESET
MOV
MOV
JSR

@RVECT ,R3

#18,3RVECT
PC,WRPSW

.WORD

340

#BIT6,aRCSR

104026

BIT
BEQ
ERROR

000402

B8R

CMP
ERROR

+27

BIS
BIT

#B1T6,aRCSR
g?JTb.aRCSR

ERROR

+30

BIC
BIT

#BI1T6,aRCSR
Z?ITé,aRCSR

ERROR

+31

BIS
RESET

#BIT6,IRCSR

022626

1%:

104027

052777
032777
001001

000100
000100

2%:

BNE

104030

042777
032777
001401

000100
000100

3%:

BEQ

104031

052777
000005
032777
001401

000100

175116

000100

175106

(%:

104032

010377
012737

175106

000012

001002

5%:

TCLOCK:

SEQUENCE

TEST # 12 - TEST THAT BIT6 OF RCSR CAN BE SET & RESET

i2 2222222222222

TST12:

175230

D 5
PAGE 40

AR AR AR AR AR A AR AR AR

;*TEST 12
005404
2336 005406
2337 005410
2338 005414
2339 005422
2340 005426
2341 005430
2342 005436
2343 005440
2344
2345 005442
2346
2347 005444
2348 005446
2349
2350
2351 005450
2352 005456
2353 005464
2354
2355 005466

15:03

2%
+2¢

(SP)+,(SP)+

222

20222

;CLEAR EVERYTHING
sSAVE RECEIVE VECTOR
sSET UP INTERRUPT VECTOR FOR ERROR REPORT
;SET PSW TO PRIORITY=7

;TEST BIT6 OF RCSR
;BIT6 OF RCSR NOT CLEAR AFTER RESET

JRESTORE SP AFTER INTERRUPT
sRCVR INTERRUPT WITH PRIORITY=7

BEQ

BIT

#BIT6,aRCSR
5%

ERROR

+32

MOV

R3,aRVECT

MOV

#12,8TSTNM

;SET BIT6 OF RCSR
JTEST BIT6 OF RCSR

;BR,

SET

s CANNOT SET BIT6 OF RCSR

;CLEAR BIT6 OF RCSR
;TEST BIT6 OF

:BR,

IF CLEAR

RCSR

s CANNOT CLEAR BIT6 OF RCSR

;SET BIT6 OF RCSR
;CLEAR BIT60F RCSR WITH RESET
sTEST BIT6 CF

:BR, IF CLEAR

RCSR

;CANNOT CLEAR BIT6 OF RCSR WITH RESET
JRESTORE

RECEIVE

VECTOR

JADJUST TEST NUMBER TO (NEXT TEST = 1)

——

CZDLDHO DL11=W 11/44 MFM SLU

——

MACRO M1113

TEST # 13 = TEST ABILITY TO ACCESS LKS

2374

——

07-JuUL=81 15:03

LSBTTL

————

PAGE 41

SEQUENCE

TEST # 13 - TEST ABILITY TO ACCESS LKS

J*TEST 13

TEST ABILITY TO ACCESS LKS

L R
T e T Y

005544
2375 005546
005552
005554
005562
2376 005564
2377 005570
2378 005576
S%gg 005602

000004
005737
001420
032777
001014
013703
012737
005777
000402

2381 005604
S%g% 005606

022626
104010

2384 005610

010337

002624
000100

173256

000004
005604
175072

000004

TST13:

SCOPE
TST
BEQ
BIT
BNE
MOV
MOV
TST
BR

CTSTFL
TST14
#BIT6,aSWR
TST14
a#4 ,R3
#1844
alLKS
2%

;1S CONSOLE UNDER TEST?
;IF NO7, SKIP THIS TEST
JARE LINE CLOCK TESTS INHIBITED?
;IF YES, SKIP THIS TEST
sSAVE TIMEOUT VECTOR
;SET UP TIMEOUT VECTOR
sACCESS LKS
JNO TIMEOUT = BR TO END OF TEST

1%:

CMP
ERROKk

(SP)+,(SP)+
+10

JRESTORE SP AFTER TIMEOUT
;CAN NOT ACCESS LKS

2%:

MOV

R3,a44

JRESTORE

TIMEOUT VECTOR

-——

—

———

——

‘

| CZDLDHO DL1T=w 11/44 MFM SLU

' TEST # 14 = TEST THAT BIT6 OF

MACRO M1113

07-JuL=81 15:03

LKS CAN BE SET & RESET

2386

F.S

PAGE 42

SEQUENCE

.SBTTL

TEST # 14 = TEST THAT BIT6 OF LKS (AN BE SET & RESET

J*TEST

.':'.t.t'!""t.lt't..""t"'t't'tttlttQttt'tttt't'tttitt.ttttt"

'-:t'tttttt"".'t"tttt""".t"t't"..t'it"t"ttt"ttttt."t"

005614

2387 005616
|
005622
|
005624
|
005632
|

|
|

000004

005737
001460
032777
001054

2388 005634

000005

2390 005642
2391 005650
2392 005654
2393 005656
239 005664
2395 005666
239
2337 005670

012777
004737
000340
032777
001404
104033

2389 005636

2399 005672
2400 005674

v 4!

017703

TST14:

002624
000100

175034

173206

005672
014502

175026

000100

175010

1$:

THAT BIT6 OF

CTSTFL
TST15
#8176, aSWR
1ST15

;1S CONSOLE UNDER TEST?
:IF NOT, SKIP THIS TEST
;ARE LINE CLOCK TESTS INHIBITED?
:1F YES, SKIP THIS TEST

MOV
JSR

aRTCVT,R3

;SAVE LINE CLOCK VECTOR

BIT
BEG
ERROR

#18,ARTCVT
PC,WRPSW
WORD
340
#BIT6,8LKS
2%
+33

CMP
ERROR

(SP)+,(SP)+
+34

BIS
BIT
NE

#BIT6,ALKS
#BIT6,aLKS
3%

:3ET BIT6 OF LKS
;TEST BIT6 OF LKS
:BR IF SET

ERROR

¢35

:CANNOT SET BIT6 OF LKS

BIC

#BIT6,ALKS

:CLEAR BIT6 OF LKS

BEQ
ERROR

4%
+36

[

2403 005676
2604 005704
2405 005712

052777
032777
001001

2407 005714

104035

2410 005716

042777

2412 005732
2413 005734
2414
2415 005736

001401
104036

505
2411

005724

2416 005744

2417 005746
2418 005754

032777

000100

174770
174762

174750
174742

052777

000100

174730

032777
001401

000100

174720

000005

2420 005756

104037

2422 005760

010377

242 1

000100
000100

174712

2%:

3$:

48:

5%:

LKS (AN BE SET & RESET

TST
BEQ
BIT
BNE
RESET

MOV

000402

022626
104034

SCOPE

TEST

BIT

#BIT6,ALKS

:SET UP INTERRUPT VECTOR FOR ERROR REPORT
;SET PSW TO PRIORITY 7
;TEST BIT6 OF LKS
;BIT6 OF LKS NOT CLEAR AFTER RESET

;RESTORE SP AFTER INTERRUPT

:LKS INTERRUPT WITH PRIORITY=7

:TEST BIT6 OF

BIS

#BIT6,LKS

;CANNOT CLEAR BIT6 OF LKS
;SET BIT6 OF LKS

BIT
BEQ

#BIT6,aLKS
5%

;TEST BIT6 OF LKS
:BR IF CLEAR

ERROR

+37

MOV

R3,aRTCVT

RESET

:CLEAR BIT6 OF

; CANNOT

LKS WITH RESET

CLEAR BIT6 OF

LKS WITH RESET

JRESTORE LINE CLOCK VECTOR

MACRO M1113 07-JuL=-81
CZDLDHO DL11=w 11/44 MFM SLU
TEST # 15 = TEST FOR DUAL ADDRESSING OF REGISTERS
2623

.SBTTL

000004
000006

000002
000020

173012

002674

001020

002634

001020
001022

001020
001022
001020

iiii222223 2222222222220
222222
022
R
Rl 2]

001022

172722

000100
000100
001024

001024

172712
172702

2222222222222 2222222222t
R
Rl d )

SCOPE
MOV
MOV

MOV
MOV
RESET
MOV

BIT
BEQ

MOV
BR
MOV

V01022

3%:

TEST

FOR DUAL

a#é R3

6. R4
2.8 NG

#340,a46

#3171,RO
:gxra.asun

LKS,$GDADR
2%

RCSR,$GDADR

$GDADR, $BDADR
RO, $BDADR
ggDADR.‘BDADR
RO, $BDADR

@$8DADR, $GDDAT
#B176,a%$BDADR

#B176,3a8GDADR
6%
ggDDAT.B$BDADR

172674
(%:

5%:

(SP)+,(SP)+

RO
RO

6%:

000004
000006

7%:

TEST # 15 = TEST FOR DUAL ADDRESSING OF REGISTERS

15115

006130
000340

SEQUENCE

LeTEST 15
005764
2624 005766
2425 005772
2426 005776
2427 006004
2428 006012
2429 006014
2430 006020
2431 006026
2432 006030
2433 006036
2434 006040
2435 006046
2436 006054
2437 006060
2438 006066
2439 006070
2440 006074
2441 006102
2442 006110
2443 006116
2444 006120
2445 006126
2446 006130
2447 006132
2448 006134
2449 006136
2450 006140
2451
2452 006142
2453
2454
2455
2456 006144
2457 006150

G_5
PAGE 43

15:03

+40

ADDRESSING OF

REGISTERS

;SAVE TIMEOUT VECTOR
;SAVE

TIMEOUT PSW

;SET UP TIMEOUT VECTOR
;KEEP PRIO=7
s CLEAR EVERYTHING
sSET UP BIT MASK
sCLOCK TEST ONLY?
;BR IF NOT

;ELSE, MOVE GOOD LKS ADDRESS INTO $GDADR

;MOVE GOOD RCSR ADDRESS INTO $GDADR
;MOVE GOOD ADDRESS INTO TEST ADDRESS LOCATION
;CREATE BAD ADDRESS BY COMPLEMENTING ONE BIT
;ARE ADDRESSES IDENTICAL?
;IF NOT,

TEST THIS ADDRESS

JELSE, BIT SET THIS BIT POSITION TO GENERATE BAD ADDRESS
;SAVE CONTENTS OF BAD ADDRESS IF IT EXISTS
;SET BIT6 USING BAD ADDRESS
JCHECK TO SEE IF GOOD ADDRESS CONTAINS BIT6
;BR IF

SET ===> ERROR

;RESTORE ANY MEMORY LOCATION THAT WAS ALTERED
JBR TO CONTINUE TEST
;RESTORE SP AFTER TIMEOUT
JSHIFT BIT MASK TO NEXT POSITION
;COMPLEMENTED ALL BITS FROM 1 - 7?
;sBR, IF NOT.
;BR TO NEXT TEST

:DUAL ADDRESSING ERROR
:$BDADR = DUAL ADDRESS
:$GDADR = GOOD ADDRESS

R3, and

R4, o460

JRESTORE TIMEOUT VECTOR
JRESTORE TIMEOUT PSW

229¢
330

—

—t—

—

———

—

CZOLDHO DL1T=W 11/44 MFM SLU

—

MACRO M1113

07-JuL=81 15:03

| TEST # 16 = TEST THAT BIT7 OF LKS SETS & (AN BE CLEARED
|

2458

LSBTTL

PAGE 44

SEQUENCE

TEST # 16 = TEST THAT BIT7 OF LKS SETS & CAN BE CLEARED

:.‘"".'.........'...'.""""..'Q.'....'.Q'..."".'..".."."

TTEST 16

|
006154
2459 006156
|
006162

000004
005737
001437

006172
2460 006174
2461 006176
2462 006202

001033
000005
105777
100401

TEST THAT BIT7 OF LKS SETS & CAN BE CLEARED

.'.'.'."..'.'....'.'.Q.."'Q""QQ.'Q'.'""..'.'.'..'..".""".

006164

032777

2464 006204

104041

2466 006206
2467 006214
2468 006222
2469 006224
2470 006232
271 006240

042777
032777
001410
042777
032777
001401

273 006262

104042

2475 006244

005000

24,78 006254
2479 006256

005200
001373

2476 006246
2477 006252

105777
100403

002624
.

000100

T§7116:

172646

174472

174460
174452

000200
000200

174442
174434

174422

CTSTFL
15717

;1S CONSOLE UNDER TEST?
:1F NOT, SKIP THIS TEST

TST17

aLKS
23

(1F YES, SKIP THIS TEST
:CLEAR EVERYTHING & SET BIT7 OF LKS
*TEST FOR BIT7 OF LKS
iBRIF SET

ERROR

+41

;BIT7 OF LKS DID NOT SET WITH RESET

BIC
BIT
BEQ
BIC
BIT
BEQ

#3177,8LKS
#BIT7,3LKS
3
#B1T7,3LKS
#B177,3LKS
38

:CLEAR BIT7 OF LKS
:TEST BIT7 OF LKS

ERROR

+42

:CAN NOT CLEAR BIT7 OF LKS

CLR

:CLEAR TIMER

INC
BNE

RO
CONT

: INCREMENT TIMER
:CONTINUE UNTIL TIME EXPIRES

BIT
18:

000200
000200

SCOPE
TST
BEQ

28:

38:

(ONT:

BNE
RESET
1STR
BM]

TSTB
BM]

#B1T6,SWR

aLKS
15717

*ARE LINE CLOCK TESTS INMIBITED?

;TRY ONE MORE TIME BECAUSE THE (LOCK
:
MAY WAVE SET IMMEDIATELY AFTER THE FIRST CLEAR

:TEST FOR BIT7 OF LKS
:BR, IF SET

2481 006260

104043

ERROR

+43

;BIT7 OF LKS DOES NOT SET

' CZDLDHO DL11=w 11744 MFM SLU

MACRO M1113

07-JuL-81 15:03

| TEST & 17 = TEST THAT THE REAL TIME CLOCK INTERRUPTS PROPERLY

PAGE 45

SEQUENCE

]

2482

LSBTTL

;*TEST 17

l
g
|
{
‘

TEST # 17 - TEST THAT THE REAL TIME CLOCK INTERRUPTS PROPERLY

.'.'t".Q..."".'t.".'..""".....'...l.'.'..."..'..'.'.'Q"."

TEST THAT THE REAL TIME CLOCK INTERRUPTS PROPERLY

."-"Q'.t."t'"l."'..'"t'"'.'Q...'QQ'Q'.....'...Qt'."".'.".

006262
2483 006264
006270
006272
006300
2484 006302
2485 006306

2486 006310
2487 006314
2488 006320
2489 006326
2490 006334

2491 006340
2492 006346

2493 006352
2494 006354
2495 006360
2696 006366
2497 006372
2498 006374
ggg 006376

000004
005737
001514
032777
001110
004737
000340

014502

SCOPE
TST
BEQ
BIT
BNE
JSR

017703
017704
012777
012777

174362
174360
006400
000340

MOV
MOV
MOV
MOV

012777
105777

000100
174322

174326

174314
000100
174302

174306

005077

100375
005077
012777
105777
100375
000240
000402

2501 006400
Sggg 006402

022626
104044

2504 006404

005077

2507 006422
2508 006424
2509 006430
2510 006432
2511 006434
Sg}% 006436

000240

2505 006410
2506 006416

012777
004737
105777
100375
000240
000240
000402

2514 006440

022626

2517 006444
2518 006452
2519 006460

012777
042777
052777

Sg]lg 006442

2520 006466
2521 006472
525% 006474
2524 006476

2525 006500
2526 006502
2527 006504
2528 006512
2529 006516

TST17:

002624

000100

174334

172540

174350
174344

104046
000401
022626
042777
010377
010477

1%:

2%:

3%:
174264
006440
014502

174260

174244

006502
000200
000100
174202

000100
174160
174156

174224
174214
174206

174162

8PL
CLR
MOV
TSTB
BPL
NOP
BR

aLKS

;CLEAR DONE FLAG AND

@RTCVT,R3
aRT(PSW, R4
#38,ARTCVT
#340,aRTCPSW

;SAVE LINE CLOCK VECTOR
;SAVE LINE CLOCK PSW VECTOR
sSET RTC INTERRUPT VECTOR TO ERROR REPORT
;KEEP PRIORITY AT 7

#BIT6,aLKS
alLKS

sSET CLOCK INTERRUPT ENABLE
sWAIT FOR RTC DONE (INTERRUPT REQUEST)

1%
alLKS
#BI1T6,aLKS
alLKS
2%
4%

;CLEAR DONE FLAG AND
sSET CLOCK INTERRUPT ENABLE
;WAIT FOR RTC DONE(INTERRUPT REQUEST)
;GIVE TIME FOR ANY INTERRUPTS
;BR, IF NO INTERRUPT OCCURS

+44

(SP)+,(SP)+

JRESTORE SP AFTER INTERRUPT
sRTC INTERRUPTS AT PRIORITY 7

4%:

CLR
MOV
JSR

aLKS

;DISABLE RTC INTERRUPTS & CLEAR DONE

20%:

TSTB
BPL
NOP
NOP
BR

68:
7%:

8%:
9%:

(MP

;IS CONSOLE UNDER TEST?
;IF NO7, SKIP THIS TEST
JARE LINE CLOCK TESTS INHIBITED?
;IF YES, SKIP THIS TEST
:SET PSW TO PRIORITY 7

ERROR

5%:

104045

105777
100375
000240

CLR

MOV
TSTB

CTSTFL
TST20
#BIT6,aSWR
TST20
PC,WRPSW
WORD
340

CMP

#5% ,ARTCVT
PC,WRPSW
.WORD
alLKS
208

240

sSET RTC INTERRUPT VECTOR FOR ERROR
;CHANGE PSW TO PRIORITY 5

;WAIT FOR DONE (INTERRUPT REQUEST)

;GIVE TIME FOR ANY INTERRUPT
;GIVE TIME FOR ANY INTERRUPT
;IF NO INTERRUPT = BR TO CONTINUE TEST

ERROR

+45

(SP)+,(SP)+

JRESTORE SP AFTER INTERRUPT

MOV
BIC
BIS

#8% ,aRTCVT
#B177,3LKS
#BI1T6,aLKS

sPOINT RTC VECTOR TO END OF TEST
;CLEAR CLOCK DONE FLAG
JALLOW INTERRUPTS

TSTB
BPL
NOP

ERROR
BR
CMP
BIC
MOV
MOV

aLKS
7%

+46
9%
(SP)+,(SP)+
#BIT6,aLKS
R3,aRTCVT
R4 ,aRTCPSW

JRTC INTERRUPTS WITH INTERRUPTS DISABLED

;WAIT FOR RTC DONE

;GIVE TIME FOR INTERRUPT
JRTC INTERRUPT DID NOT OCCUR

sBRANCH OVER STACK CORRECTION
JRESTORE SP AFTER INTERRUPT
;DISABLE INTERRUPTS
JRESTORE LINE CLOCK VECTOR
JRESTORE LINE CLOCK PSW VECTOR

[

CZDLDHO DL11=W 11/44 MFM SLU

TEST # 20 = TEST RTC FOR DOUBLE

MACRO M1113
INTERRUPTS

2530

07-JuL-81

SBTTL
A

15:03

J 5
PAGE 46

SEQUENCE

TEST # 20 = TEST RTC FOR DOUBLE

INTERRUPTS

ii22222222222222
2222222
22 2R
Rt Rl d )

S*TEST 20

TEST RTC FOR DOUBLE

INTFRRUPTS

':'t"'.Q'tt.*'l'.t."t""".'t"..'.'Q...'.".ttt't'."t""."

006522
2531 006524
006530
006532
006540
2532 006542
2533 006544
2534 006550
2535 006554
2536 006562
2537 006570
2538 006574
2539 006576
2540 006602
2541 006610
2542 006614
2543 006616
2544 006622
2545 006630
2546 006634
2547 006636
2548 006640

18§120:

002624
000100
174126
174124

014502
174072

000100
174060

174052

000100

174040

006676
014502

172300

SCOPE
TST
BEQ
BIT
BNE

RESET

PC,WRPSW

240

174064

174044

174020

aLKS
#BIT6,aLKS
aLKS
1%
aLKS
#BIT6,aLKS

1%:

2%:

alLKS

+47
4%
(SP)+,(SP)+
#5% ,aRTCVT

3%:

4%:

PC,WRPSW

240

022626

104050

042777
010377
010477

aRTCVT,R3

R4
aRTCPSW,
#38 ,aRTCVT
#340,aRTCPSW

74114
74110

000402

2564
2565 006702
2566 006710
2567 006714

CTSTFL
TST121
#BIT6,aSWR
TsT21

000100

173762
173760

173764

6%:

sIF NO7, SKIP THIS TEST
JARE LINE CLOCK TESTS INHIBITED?

;IF YES, SKIP THIS TEST

:CLEAR EVERYTHING
sSAVE LINE CLOCK VECTOR

sSAVE LINE CLOCK PSW VECTOR

sSET UP RTC INTERRUPT VECTOR
;DISALLOW INTERRUPTS AFTER THE INTERRUPT

;SET PRIORITY TO 5

;CLEAR DONE FLAG AND
sSET CLOCK INTERRUPT ENABLE

sWAIT FOR DONE

sBRANCH BACK IF NOT DONE
;CLEAR DONE FLAG AND
sSET CLOCK INTERRUPT ENABLE
;WAIT FOR DONE

;BRANCH BACK IF NOT DONE
;GIVE TIME FOR ANY INTERRUPT
;GIVE TIME FOR ANY INTERRUPT
sRTC INTERRUPT DID NOT OCCUR
;BRANCH OVER STACK CORRECTION
JRESTORE SP AFTER INTERRUPT
;POINT RTC VECTOR TO ERROR REPORT

;SET PSW TO PRIORITY 5

;GIVE SOME TIME FOR AN INTERRUPT
;GIVE SOME TIME FOR AN INTERRUPT
;GIVE SOME TIME FOR AN INTERRUPT
;GIVE SOME TIME FOR AN INTERRUPT
sNO INTERRUPT = BR TO END OF TEST

(SP)+,(SP)+

JRESTORE SP AFTER INTERRUPT
s INTERRUPT SEQUENCE DID NOT CLEAR
s INTERRUPT REQUEST

#BIT6,aLKS
R3,aRTCVT

;DISABLE CLOCK INTERRUPTS

+50
BIC

;IS CONSOLE UNDER TEST?

R4 ,aRTCPSW

JRESTORE LINE CLOCK VECTCR

JRESTORE LINE CLOCK PSw VECTOR

CZDLDHO DL11=w 11/44 MFM SLU
TEST # 21 = TEST

THAT RTC

MACRO M1113

K_5

07-JuL-81 15:03

PAGE 47

INTERRUPT CLEARS WITH RESET

2568

J3BTTL

SEQUENCE

TEST # 21 = TEST THAT RTC INTERRUPT CLEARS WITH RESET

:.‘.'.'.......'.Q.'Q.""""".""...".'..".""'.""..""'.

THTEST 21

TEST

THAT RTC

INTERRUPT CLEARS WITH RESET

;"'.Q'Q.Q'.'.'..'......"'."Q.— 2332223222323 232232232323232223232232222323 22}

006720
2569 006722
006726

000004
005737
001452

006736
2570 006740
2571 006744
2572 006746
2573 006752
2574 006760
2575 006764
2576 006772
2577 006776
2578 007000
2579 007004
2580 007012
2581 007016
2582 007020

001046
004737
000340
017703
012777
005077
012777
105777
100375
005077
012777
105777
100375
000240

2584 007024

004737
000240
000240
042777
000402

T§121:

002624

006730 032777 000100 172102

2583 007022

2585 007030
2586 007032
2587 007034
2588 007042
2590 007044
2591 007046
2592
2593 007050

000005

173670
000100
173656

BNE
JSR

173716
173702

173662

18:

2s:

000100

173622

MOV
MOV
CLR
MOV
TSTB
BPL
CLR
MOV
TSTB
BPL
NOP

RESET

014502

022626
104051

010377

BIT

014502
173724
007044
173710
000100
173676

SCOPE
TST
BEW

JSR

CTSTFL
15722

;1S CONSOLE UNDER TEST?
:IF NOT, SKIP THIS TEST

15122
PC,WRPSW
.WORD ~ 340
SRTCVT,R3
#38,aRTCVT
ALk S
#B176,aLKS
@LKS
8
aLKS
#B1T6,8LKS
@LKS
28

*1F YES, SKIP THIS TEST
:SET PRIORITY TO 7

#B31T6,aSWR

PC,WRPSW
LWORD
240

ARE LINE CLOCK TESTS INMIBITED?
;SAVE LINE CLOCK VECTOR
:POINT RTC VECTOR TO ERROR REPORT
:CLEAR DONE FLAG AND
*SET CLOCK INTERRUPT ENABLE
‘WAIT FOR DONE (INTERRUPT REQUEST)
;CLEAR DONE FLAG AND
*SET CLOCK INTERRUPT ENABLE
*WAIT FOR DONE (INTERRUPT REQUEST)
:GIVE TIME FOR ANY INTERRUPT
*CLEAR PENDING INTERRUPT WITH RESET
:SET PRIORITY TO S

NOP
BIC
BR

#B1T6,aLKS
4$

:GIVE TIME FOR ANY INTERRURT
:DISALLOW INTERRUPTS
:BR TO END OF TEST

38:

cMP
ERROR

(SP)+,(SP)+
+51

;RESTORE SP AFTER INTERRUPT
*RESET DID NOT CLEAR INTERRUPT

4%:

MOV

R3,aRTCVT

JRESTORE LINE CLOCK VECTOR

173632

MACRO M1113

07-JUL-81 15:03

TEST # 22 = TEST THAT RTC INTERRUPT CLEARS BY CLEARING BIT7 OF
2594

SBTTL

L 5
PAGE 48

SEQUENCE

TEST # 22 = TEST THAT RTC INTERRUPT CLEARS BY CLEARING BIT? OF LKS

:.'ttt""fi."t""fi'.t'""'.t'fififi.*"fi!.*.tt'*fi'..""'tfi.'t't't

TRTEST 22

TEST THAT RTC INTERRUPT CLEARS BY CLEARING BIT7 OF LKS

;:'t*tt't!...fi.t'tttt.'""'i'.Q'.'fi'."t."'..t"'.'l"."'t.'t.t

007054
2595 007056
007062
0070645
007072
2596 007074
2597 007100
2598 007102
2599 007106
2600 007114

000004
005737
001457
032777
001053
004737
000340
017703
012777
005077

2602 007126
2603 007132
2604 007134
2605 007120
2606 0C7146
2607 007152
2608 007154
2609 007156
2610 007164
2611 007170
2612 007172
2613 007174
2614 007202

105777
100375
005077
012777
105777
100375
000240
042777
004737
000240
000240
042777
000402

2617 007204
2618 007206

022626
104052

2620 007210
2621 007214
2622 007220

010377
004737
000340

f§722:

002624
000100

171746

014502

173570
007204
173554

173546

173534
000100
173522

173526

173542

000200
014502
-

173510

000100

173472

173462
014502

MOV
MOV
CLR

173562

2601 007120 012777 000100

SCOPE
TST
BEQ
BIT
BNE
JSR

1$:

2%:

MOV

TSTB
BPL
CLR
MOV
TSTB
BPL
NOP
BIC
JSR
NOP
BIC
BR

CTSTFL
15723
#B1T6,aSWR
15723
PC,WRPSW
.WORD
340
ARTCVT,R3
#3$,aRTCVT
ALk S

;1S CONSOLE UNDER TEST?
:IF NOT, SKIP THIS TEST
*ARE LINE CLOCK TESTS INHIBITED?
*IF YES, SKIP THIS TEST
:SET PRIORITY TO 7

aLKS
1$
aLKS
#B1T6,8LKS
aLKS
2%

*WAIT FOR DONE (INTERRUPT REQUEST)

#B8176,aLKS

#BIT7,ALKS
PC, WRPSW
.WORD
240

;SAVE LINE CLOCK VECTOR
:POINT RTC VECTOR TO ERROR REPORT
:CLEAR DONE FLAG AND

*SET CLOCK INTERRUPT ENABLE

;CLEAR DONE FLAG AND
*SET CLOCK INTERRUPT ENABLE
‘WAIT FOR DONE (INTERRUPT REQUEST)
:GIVE TIME FOR ANY INTERRUPT
:CLEAR DONE & INTERRUPT
*ALLOW INTERRUPTS

#B1T6,aLKS
4$

:GIVE TIME FOR ANY INTERRUPT
:DISALLOW INTERRUPTS
‘BR TO END OF TEST

38:

cMP
ERROR

(SP)+,(SP)+
+52

;RESTORE SP AFTER INTERRUPT
:CLEARING BIT7 OF LKS DID NOT CLEAR INTERRUPT

4$:

MOV
JSR
.WORD

R3,@RTCVT
PC . WRPSW
340

;RESTORE LINE CLOCK VECTOR
*RESTORE PRIORITY TO 7

—e—

CZDLDHO DL11=W 11/44 MFM SLU

MACRO M1113

TEST # 23 < TEST CLOCK REPEATABILITY

2623

07-JuUL-81 15:03

.SBTTL

PAGE 49

SEQUENCE

TEST # 23 - TEST CLOCK REPEATABILITY

::t."ttfi."."t""...""t'..t.itt.'.!i't't'...l.t.t.ttt".'.'.

S*TEST 23

TEST CLOCK REPEATABILITY

:;"ttt.t.'.'t"t.ttt.t""'t't'.Q".t.t.'."""t"ttt..'ttt'."

007222
2624 007224
007230
007232
007240
gggg 007242

005737
001467
032777
001063
042777

2627 007250
2628 007252
2629 007256
2630 007260
2631 007264
2632 007270
2633 007272
2634 007276

005000
012701
005002
005077
105777
100375
005077
105777

2636 007304
2637 007306
2638 007312
2639 007314
2640 007316
2641 007320
2642 007322
2643 007326
2644 007330
2645 007334

005202
005077
005200
001370
005201
001003
010237
000753
013701
160201

2647 007340
2648 007342

005401
032737

000001

2650 007352
2651
2652 007356
2653 007360
gggg 007364

020127

000002

000402
020127
003403

000001

2656 007366

010237

002616

2659 007374
2660 007402
2661 007404

032777
001402
000137

000020

2635 0C7302

100003

15123:

002624
000100

171600

000100

173424

177777

1%:

173410
173404

28:

173376
173372

38:

gggg 007372

104053

CTSTFL
TST24
#BIT6,aSWR
TST24
#BIT6,aLKS

;1S CONSOLE UNDER TEST?
*IF NOT, SKIP THIS TEST
“ARE LINE CLOCK TESTS INMIBITED?
“IF YES, SKIP THIS TEST
*DISALLOW INTERRUPTS

CLR
MOV
CLR
CLR
TSTB
BPL
CLR
TSTB

RO
#-1,R1
R2
aLKS
@LKS
2s
aLKS
aLKS

:CLEAR A TIMER
“SET A FLAG INDICATING FIRST PASS THRU THIS LOOP
:CLEAR CLOCK COUNTER
*CLEAR DONE
*SYNC ON DONE

R2
aLKS
RO
3s
R1
CMPARE
R2,FIRST
1%
FIRST,R1
R2,R1

*IF DONE, INCREMENT CLOCK COUNT
*CLEAR DONE
* INCREMENT TIMER
*BR IF TIME REMAINS
*INCREMENT LOOP PASS FLAG
*BR IF TWO PASSES HAVE BEEN MADE
*IF NOT, STORE FIRST CLOCK COUNT
:DO LOOP AGAIN
*RECALL FIRST CLOCK COUNT
1 ALCULATE DIFFERENCE OF TWO COUNTS

BPL

INC
CLR
48:
INC
BNE
INC
BNE
MOV
BR
CMPARE: MOV
SUB

173362

002336
002336

2646 007336 100001

2649 007350 001403

scope
ST
BEQ
BIT
BNE
BIC

BPL

014326

003002

TOLER:

6$:
7%:

5%:

TOLER

*BR IF NOT , TO INCREMENT TIMER

:IF POSITIVE,SKIP NEGATION OF DIFFERENCE

NEG
R1
BIT #BITO,FLAG44

“MAKE DIFFERENCE A POSITIVE NUMBER
iax IS THIS A 11/44

CMP

R1,42

BR 7%
CMP
BLE

‘e YES: COMPARE DIFFERENCE WITH DESIRED
;++ TOLERANCE OF 2

R1,41
5%

;COHPARE DIFFERENCE WITH DESIRED TOLFRANCE
‘BR, IF LOWER/EQUAL TO TOLERANCE

MOV

R2,SECND

:STORE SECOND COUNT

BIT

#B1T4,aSWR
TST24
$EOP

;CLOCK TESTS ONLY?
:BR IF NOT
“ELSE, JUMP TO END OF PASS ROUTINE

BEQ 6%

ERROR

171436

:CLEAR DONE
*IS CLOCK DONE?

BEQ
JMP

+53%

pew

*CLOCK REPEATABILITY ERROR

CZDLDHO DL11=W 11/44 MFM SLU
TEST # 24 = TEST

THAT

XMIT

MACRO M1113

07-JuL-81

INTERRUPTS ONLY WHEN ENABLED

2662

.SBTTL

15:03

N 5§
PAGE 50

SEQUENCE

TEST # 24 = TEST THAT XMIT INTERRUPTS ONLY WHEN ENABLED

':'Q.Q.tt"'..ttt..'t""tttt.'.."..t‘QQ.....t."'.....Q.QQQQQ'Q

;*TEST 24

TEST THAT XMIT INTERRUPTS ONLY WHEN ENABLED

;:ttttttttttQtt!titttt'titttttttttt.ttttttt.t't.."t.t......t.'tt

007410
2663 007412
2664 007420
2665 007424

2666 007432
2667 007436
2668 007440

2669 007444
2670 007446
2671
2672 007450
2673 007452
2674
2675 007454
2676 007462
2677 0C7470
2678 007472
2679 007474
2680 007476
2681 007500
2682 007502
2683 007504
2684 007506
2685 007514

000004
042777
017703
012777
105777
100375

004737
000140
000402

000100

173220

007450

173216

173224

173202

1%:

014502

104054

007504
000100

SCOPE

BIC
MOV
MOV

égTB
L

JSR

022626

012777
052777

TST24:

173166

173150

173124

#RIT6,aTCSR
aTVECT,R3
#2% ,aTVECT
?;CSR

PC,WRPSW

;WAIT FOR DONE

;SET PSW TO PRIORITY 3

.WORD
3%

2%:

CMP
ERROR

(SP)+,(SP)+
+54

JRESTORE SP AFTER INTERRUPT

3%:

MOV
BIS

#68 ,ATVECT
#BIT6,aTCSR

JSET XMIT VECTOR TO END OF
sENABLE INTERRUPTS

ERROR
BR

+55
5%

BIC
MOV

#BIT6,aTCSR
R3,aTVECT

NOP
NOP
NOP
NOP

4%:

5%:

CMP

140

sCLEAR TRANSMIT INTERRUPT ENABLE
;SAVE AMIT VECTOR
JPOINT XMIT VECTOR TO ERROR REPORT

(SP)+,(SP)+

JXMIT INTERRUPTS WITH INTERRUPT ENABLE CLEAR
JALLOW
s TIME
JFOR
s INTERRUPT

TEST

JXMIT DID NOT INTERRUPT
;BRANCH OVER STACK CORRECTION
JRESTORE SP AFTER INTERRUPT

;DISABLE INTERRUPTS
JRESTORE XMIT VECTOR

(ZDLDHO DL11=W 11/44 MFM SLU
TEST # 25 < TEST THAT XMIT

MACRC M1113

07-JuL-81 15:03

INTERRUPTS DO NOT OCCUR WHEN DISABL

2¢86

LSBTTL

B 6
PAGE 51

SEQUENCE

TEST # 25 = TEST THAT XMIT INTERRUPTS DO NOT OCCUR WHEN DISABLED

.':'.Q"."..'.'Q..Q'....'Q."'...'..Q'QQ."'QQ.Q.Q'Q..""'..'Q.'

S*TEST 25

TEST THAT XMIT INTERRUPTS DO NOT OCCUR WHEN DISABLED

.'"."'t"t'.'t'.t.Q.t""""'.t‘.."t...'."'."....'Q.'Q.'Q"'.

007520
2687 007522
2688 007530
2689 007534
2690 007536
2691 007542
2692 007550
2693 007554
2694 007556
2695 007564
2696 007566
2697 007570
2698 007572
5988 007574

000004
042777
004737
000340
017703
012777
105777
100375
052777
000240
000240
000240
000240
000402

000100
014502

173110

173106
007576
173064

173100

000100

173054

2701 007576 022626
2702 007600
2703

2705 007610 012777
2706 007616 004737
2707 007622 000140
2708 007624 000240
2709 007626. 000240
2710 007630 000240
2711 007632 000240
5;}5 007634 000402
2714 007636
2715 007640

022626
104057

2717 007642

010377

2716

18:

2%:

104056

2704 007602 042777

T§125:

000100

007636
014502

173030

173032

3$:

SCOPE
BIC
JSR
MOV
MOV
TSTB
BPL
BIS
NOP
NOP
NOP
NOP
BR

cMP

;SAVE XMIT VECTOR
:POINT XMIT VECTOR TO ERROR REPORT
‘WAIT FOR DONE

(SP)+,(SP)+

;RESTORE SP AFTER INTERRUPT

+56

BIC

#B31T6,aTCSR

MOV
JSR

;:DISABLE INTERRUPTS
:SET PSW TO PRIORITY 7

;ENABLE INTERRUPT
:ALLOW
:TIME
:FOR
* INTERRUPT
:CONTINUE TEST

ERROR

NOP
NOP
NOP
NOP
BR

173002

#RIT6,ATCSR
PC,wRPSW
.WORD ~ 340
STVECT,R3
#2$,TVECT
@TCSR
1$
#B1T6,aTCSR

#4$,TVECT
PC, WRPSW
.WORD
140

;XMIT INTERRUPTS AT FRIORITY=7

:CLEAR INTERRUPT ENABLE

:POINT XMIT VECTOR TO ERROR REPORT
:3ET PSW TO PRIORITY 3
;ALLOW
TIME
*FOR
: INTERRUPT
‘BR TO END OF

TEST-NO INTERRUPT

48:

cMP
ERROR

(SP)+, (SP)+
+57

;RESTORE SP AFTER INTERRUPT

MOV

R3,TVECT

*RESTORE XMIT VECTOR

;XMIT

INTERRUPT OCCURES WITH BIT6 CLEAR

CZDLDHO DL11=W 11/44 MFM SLU

MACRO M1113

TEST # 26 = TEST TRANSMITTER FOR DOUBLE

07-JuL=-81 15:03

INTERRUPTS

.SBTTL

2718

.6
PAGE 52

SEQUENCE

TEST # 26 - TEST TRANSMITTER FOR DOUBLE INTERRUPTS

2332223232222

LRTEST 26

3222222222222

3222222322222

TEST TRANSMITTER FOR DOUBLE

222

RRRRRRldd)

INTERRUPTS

':tilt't""ttt"Q.iQQ"".QQt'Q'it"t.'..t'.".".fi.tt".".'Qt.

007646
2719 007650
2720 007656
2721 007662
2722 007666
2723 007674
2724 007702
2725 007706
2726 007710
2727 007714
2728 007716
2729 007724
2730 007726
2731 007730
2732 007732
2733
2734 007734
2735 007736
2736 007740
2737 007742
2738 007750
2739 007754
2740 007756
2741 007760
2742 007762
2743 007764
2744 007766
2745 007774
2746
2747 007776
2748 010000
2749
2750 010002
2751 010006
2752

000100

172762

007740
000340
014502

172750

172766
172764

172754

012777
004737
000140
000240
000240
000240
000240
042777
000402

007776
014502

000100

022626
172642
172640

#RIT6,ATCSR
aTVECT,R3
R4
aTPSW,
#28 . aTVECT

JSR

PC.,WRPSW

ISTB

BPL
BIS

NOP
NOP
NOP
NOP

2%:
25%:

ERROR
BR
CMP
MOV

JSR
LWORD

NOP
NOP
NOP
NOP

172644

BIC
BR
48:

104061

010377
010477

172714

172700

SCOPE
BIC
MOV
MOV
MOV

MOV
1%:

172724

000100

1$726:

5% :

#340,aTPSW
.WORD

QTCSR

140

1$
#BIT6,aTCSR

;CLEAR INTERRUPT ENABLE
sSAVE AMIT VECTOR
sSAVE XMIT PSW VECTOR
sSET UP XMIT VECTOR
;SET PIO 7 AFTER INTERRUPT
;SET PSW TO PRIORITY 3
:WAIT FOR DONE

JENABLE INTERRUPTS
JALLOW

; TIME
;FOR

;s INTERRUPT

+60
25%
(SP)+, (SP)+
#4$,TVECT
PC,WRPSW
140

sXMIT INTERRUPT DID NOT OCCUR
;BRANCH OVER STACK CORRECTION INTERRUPT
JRESTORE SP AFTER INTERRUPT
sPOINT XMIT VECTOR TO_ERROR

;SET PSW TO PRIORITY 3

;sALLOW
s TIME

;FOR

#BIT6,ATCSR
5%

; INTERRUPT

;DISABLE INTERRUPTS
;BR TO END OF TEST

ERROR

+61

(SP)+,(SP)+

JRESTORE

MOV

R3,3TVECT

;XMIT RE=INTERRUPTED
JRESTORE XMIT VECTOR

CMP

MOV

R4 ,QTPSW

JRESTORE

SP AFTER

INTERRUPT

XMIT PSW VECTOR

CZDLDHO DL11=W 11744 MFM SLU
TEST # 27 < TEST THAT XMIT

MACRO M1113

07-JUL-81 15:03

INTERRUPT CLEARS WITH LOADING TBUF

2753

.SBTTL

D_ 6
PAGE 53

SEQUENCE

TEST # 27 = TEST THAT XMIT INTERRUPT CLEARS WITH LOADING TBUF

:.'Qt"t'it"'..t".t'!."t"*.'t'fitt'..QQ.t.'.t"t.i"t.t'.."t't

I*TEST 27

TEST THAT XMIT INTERRUPT CLEARS WITH LOADING TBUF

.';Q.'t".Q't.i'"'!.'Q.""'..t'...t"'ttt..."'ti'i"""'t't".

010012
2754 010014
2755 010022
2756 010026
2757 010030
2758 010034
2759 010042
2760 010050
2761 010056
2762 010062
2763 010066
2764 010070
2765 010074
2766 010100
2767 010102
2768 010104
2769 010106
2770 010110
2771 010112
g;;g 010120

000004
042777
004737
000340
017703
012777
052777
052777
005077
105777
100375
005077
004737
000140
000240
000240
000240
000240
042777
000405

2774 010122
2775 010124

022626
042777

2776 010132
2777
g;;g 010134

104062
010377

2780 010140
010142
010146
010150
010152
010154

005007
012701
005300
001376
005301
001374

000100
014502
172614
010122
000004
000100
172560
172552

172616

T§127:

172606
172570
172562
18:

172546
014502

000100

172520

000004

172526

172510
000002

SCOPE
BIC
JSR
MOV
MOV
BIS
BIS
CLR
TSTB
BPL
CLR
JSR
NOP
NOP
NOP
NOP
BIC
BR

3%:

40%:

#RIT6,ATCSR
PC, WRPSW
.WORD
340
ATVECT,R3
#2$,TVECT
#B172,3TCSR
#B1T6,aTCSR
ATRUF
@TCSR
1$
ATRUF
PC,WRPSW
.WORD
140

#BIT6,aTCSR
3$

CMP
BIC

(SP)+, (SP)+
#BIT2.aCTCSR

ERROR

+62

MOV

R3,QTVECT

CLR
MOV
DEC
BNE
DEC
BNE

RO
#2,R1
RO
40%
R1
40%

;:DISABLE INTERRUPTS
:SET PSW TO PRIORITY 7
;SAVE XMIT VECTOR
:POINT XMIT VECTOR TO ERROR
;x* ENABLE MAINT. WRAP
:ENABLE INTERRUPTS
:LOAD TBUF
:WAIT FOR DONE (INTERRUPT)
;FILL SECOND BUFFER TO PESET INT.
:ALLOW INTERRUPTS

;ALLOW
STIME
:FOR
: INTERRUPT
:DISABLE INTERRUPTS
:BR TO END OF TEST
;RESTORE SP AFTER INTERRUPT
:#=» DISABLE MAINTENANCE MODE FOR
s%** CONSOLE TO ALLOW FOR COMMUNICATION
;** WITH TERMINAL.
'
;LOADING TBUF DID NOT CLEAR INTERRUPT.
;RESTORE XMIT VECTOR
s**
;**
s%**
;**
s**
;**
;**

DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
THAT MIGHT BE IN THE PROCESS OF BEING
TRANSMITTED TO FINISH BEFORE MAINTENANCE
WRAP FOR THE UART UNDER TEST IS DISABLED.
THIS WILL INHIBIT ANY COMMUNICATION
TO HARDWARE MEDIA SUCH AS TU58 THAT MIGHT
BE ATTACHED TO UART UNDER TEST.

—

| CZDLDHO DL11=W 11/44 MFM SLU
TEST # 30 = TEST

MACRO M1113

07-JuUL=-81 15:03

THAT RCVR ACTIVE & DONE SET & CLEAR

2781

SBTTL
S

'TEST 30

010156

000004

2782 010160

032737

000001

003002

2785 010172
2786 010200
010202

052777
005000
012701

000004

172440

010206
010212
010214
010216
010220
2787 010222
2788 010224

105777
005300
001374
005301
001372
005000
005077

172424

2790 010236
2791 010240
2792 010242
2793 010244

001006
005200
001372
042777

2783 010166
2784 010170

2789 010230

001067
000005

032777

172412

42%:

172376

000004

172406

WACTv:

SCOPE

#RITO,FLAGSL4

BIS
CLR
MoV

#BIT2,aTCSR
RO
#2,R1

TSTB
DEC
BNE
DEC
BNE
CLR
CLR

aRBUF
RO
42%
R1
42%
RO
aTBUF

BIT

BNE
INC
BNE
BIC

222222222222

R d

TEST THAT RCVR ACTIVE & DONE SET & CLEAR

RCVDON

#8I1T11,3RCSR

2%
RO
WACTV
#BIT2,aCTCSR

779

222322222220222
R R 2R dd Rl Rl d)

JEw

iy
;CLEAR EVERYTHING

sSET MAINTENANCE WRAP
s** DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
;#% THAT MIGHT BE IN THE PROCESS OF BEING
s** RECEIVED TO FINISH AFTER MAINTENANCE
;** WRAP FOR THE UART UNDER TEST

;** READ TO CLEAR DONE
oo
i
§ve
g
;CLEAR A TIMER
:LOAD TRANSMIT BUFFER

IS ENABLED.

;TEST RCVR ACTIVE BIT

:BR IF SET
s INCREMENT TIMER IF NOT SET
;CONTINUE WAIT IF TIME REMAINS
:#x DISABLE MAINTENANCE MODE FOR
;%% CONSOLE TO ALLOW FOR COMMUNICATION
s** WITH TERMINAL.

S;gz 010252

104063

2797 010254
010254
010256
010262
010264
010266

005000
012701
005300
001376
005301

2798 010272

000005

010270

032777

%%g% 010304

104115

2804 010306
2805 010310

005000
052777

2807 010322
2808 010324
2809 010326
Sg}? 010334

005200
001374
033777
001404

588? 010302

2806 010316

2812 010336

2813 010344

2%:
000002

40%:

001374

2799 010274

2814

SEQUENCE

2232222232233

BIT

BNE
RESET

000002

004000

2323232232

2232223322233 3232322222222

TST30

TEST # 30 - TEST THAT RCVR ACTIVE €& DONE SET & CLEAR

2222323323233

PAGE 54

001401

062700

042777

104116

ERROR

+63

sRCVR ACTIVE DID NOT SET WHILE RECEIVING

CLR
MOV
DEC
BNE
DEC

RO
#2.R1
RO
40%
R1

;*x
;*x
s**
;**x
s**

BNE

004000

000004

000000

RESET

172332

172322

004000

172300

000004

172314

WwT:

i#% TO HARDWARE MEDIA SUCH AS TUS8 THAT MIGHT
;%% BE ATTACHED TO UART UNDER TEST.

BIT

#BI1T11,aRCSR

;VERIFY "'INIT'" CLEARS RCV ACTIVE

ERROR

+115

sINIT DID NOT CLEAR RCV ACTIVE

CLR
BIS

RO
#BIT2,aTCSR

;CLEAR A TIMER
sSET MAINTENANCE WRAP

INC
BNE
BIT
BEQ

RO
WT
BIT11,aRCSR
RCVDON

;VERIFY RCV ACTIVE STILL CLEAR
;BR IF CLEAR

BEQ

3%:

40%

DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
THAT MIGHT BE IN THE PROCESS OF BEING
TRANSMITTED TO FINISH BEFORE MAINTENANCE
WRAP FOR THE UART UNDER TEST IS DISABLED.
THIS WILL INHIBIT ANY COMMUNICATION

ADD

BIC

ERROR

#0,R0O

#BIT2,aCTCSR

+116

;WAIT AT LEAST ONE BIT TIME

;** DISABLE MAINTENANCE MODE FOR
s** CONSOLE

TO ALLOW FOR COMMUNICATICN

i#x WITH TERMINAL
.

*RCV ACTIVE WITHOUT *‘START'' BIT

———

——e

| CZDLDMO DL11=W 11744 MFM SLU

MACRO M1113

07-JuL=81

'TEST # 30 = TEST THAT RCVR ACTIVE & DONE SET & CLEAR

15:03

PAGE 54~1

SEQUENCE

|
|

2815 010346
2816 010354
2817 010356
2818 010362
2819 010366
2820 010370
2821 010372
2822 010374

052777
005000
005077
105777

2823 010402

104064

2826 010404
2827 010412
2828 010414
2829 010422
2830 010424

032737
001010
032777
001404
042777

2831 010432
2832
2833
2834 010434
2835 010436
2836 010442
2837
2838 010444

104065

2839 010452
2840
2841
2842 010454
2843 (010454

100406

005200
001373
042777

000005

000004

172264

172260
172246

000004

RCVDON: BIS

CLR

:
WDONE

172256

000001

003002

004000

172212

5%:

000004

105777
001404

172172

042777

000004

6%:

172206

104066

042777

000004

172176

7%:

CLR

TSTB

B8MI
INC
BNE
BIC

#BIT2,aTCSR

RO
aTBUF
aR(SR

RO
WDONE

#3172,aCTCSR

ERROR

+64

BIT
BNE
BIT
BEQ
BIC

ggITO.FLA644

#31T11,aRCSR
6%
#BIT2,aCTCSR

ERROR

+65

RESET
TSTB

BEQ

aR(SR
7%

BIC

#BIT2 ,aCTCSR

ERROR

+66

BIC

#BIT2,aCTCSR

;SET MAINTENCE WRAP
JCLEAR TIMER
:LOAD TRANSMIT BUFFER
;CHECK FOR RECEIVER DONE
;BR, IF DONE
;INCREMENT TIMER, IF NOT DONE
JCONTINUE WAIT IF TIME REMAINS
;= DISABLE MAINTENANCE MODE FOR
;** CONSOLE TO ALLOW FOR COMMUNICATION
s*x WITH TERMINAL.

sRECEIVER DONE NEVER SET
pen

1174422

#* DO NOT EXECUTE THIS SECTION
:CHECK FOR RCVR ACTIVE CLEAR
:BR, IF CLEAR
:*= DISABLE MAINTENANCE MODE FOR
:** CONSOLE TO ALLOW FOR COMMUNICATION
ixx WITH TERMINAL.

;sRCVR ACTIVE DID NOT CLEAR WITH RCVR DONE
;CLEAR DONE WITH RESET
sCHECK FOR DONE CLEAR
;** DISABLE MAINTENANCE MODE FOR
;** CONSOLE TO ALLOW FOR COMMUNICATION
;** WITH TERMINAL.

JRESET DID NOT CLEAR RCVR DONE
;** DISABLE MAINTENANCE MODE FOR
;** CONSOLE TO ALLOW FOR COMMUNICATION
s** WITH TERMINAL.

' CZDLDHO DL11=w 11/44 MFM SLU

| TEST # 31

= TEST

MACRO M1113

THAT READING RBUF

CLEARS RECEIVER DONE

2844

.SBTTL

TEST # 31 = TEST THAT READING RBUF (LFARS RECEIVER DONE

;*TEST 31

010462

000004

2845 010464

000005

2847 010474

005000

SEQUENCE

TEST THAT READING RBUF CLEARS RECEIVER DONE

.-;'Q.'Qt"'t't.'tfitt'ttt"'t.t.t'tt"tt'.t"'ttt...'t.ttt..t.'Q't

G 6
PAGE 55

:"t..'t't!t.tttl"..tttt"'.'t'tt."tt...'QQ.tt".t'.."'t'.""'

07-JuL-81 15:03

B4 010466
010476
010502

TST31:

052777

000004

012701

000002

105777

172130

010506 005300

010510 001374
010512 005301
010514 001372

2848 010516
2849 010522
2850 010526

005077
105777
100375

172120
172106

2852 010534

042777

0000C&4

2853
2854
2855
2856
2857
2858

010542
010546
010550

105777
001401
104070

172066

010552

000240

2851 010530 017700 172102

172144

SCOPE

RESET

BIS

#31T2,aTCSR

MOV

#2,R1

CLR

428:

18:
172116

;SET MAINTENANCE WRAP

;** DELAY ENOUGH TIME TO ALLOW ANY CHARA(TERS

;** THAT MIGHT BE IN THE PROCESS OF BEING

s** RECEIVED TO FINISH AFTER MAINTENANCE
;** WRAP FOR THE UART UNDER TEST IS ENABLED.
“xx READ TO CLEAR DONE

T1STB

@RBUF

BNE
DE(
BNE

42%
R1
423

MOV

aRBUF ,RO

:READ RECEIVE BUFFER

TSTB
BEQ
ERROR

aR(SR
108
+70

DEC

CLR
TSTB
8PL

BIC

108:

;CLEAR EVERYTHING

NOP

aTBUF
@RCSR
1%

#BIT2,aCTCSR

Pew

en
Pew

*LOAD TRANSMITTER
*WAIT FOR RECEIVER DONE

;x* DISABLE MAINTENANCE MODE FOR
s** CONSOLE TO ALLOW FOR COMMUNICATION
;*= WITH TERMINAL.
;CHECK FOR RECEIVE DONE CLEAR
;** BR, IF CLEAR TO NEXT TEST
;READING RBUF DID NOT CLEAR RCVR DONE

| CZDLDHO DL11=w 11/44 MFM SLU
TEST # 32 = TEST

|
|

THAT RDR ENABLE

MACRO M1113

2859

LSBTTL

010554
2860 010556

000004
032737

000001

003002

2863 010570
2864 010576

052777
052777

000001
000004

172036
172034

001044
000005

005000
012701

010612
010616
010620
010622
010624
2866 010626
2867 010632
2868 010636
2869 010640
gg;? 010646

105777
005300
001374
005301
001372
005077
105777
100375
032777
001401

%g;% 010650

104117

2874 010652
2875 010660
2876 010664

052777
105777
001404

2878 010674

104067

2880 010676

000240

2877 010666

2879

SEQUENCE

TEST # 32 = TEST THAT RDR ENABLE CLEARS RECEIVER DONE FLAG

;*TEST 32

2865 010604
010606

H 6
PAGE 56

PR T
T T T R
T T P

;

2861 010564
2862 010566

15:03

CLEARS RECEIVER DONE FLAG

]
i
.
i

07-JjuL=-81

042777

1S132:

42%:

172010
171776

1$:
171766

000001
171750

171754

000004

171764

2%:

108:

#RITO,FLAGSLS

sev 11744 27

BIS
BIS

#B1T0,aRCSR
#3]T2,aTCSR

;SET RDR ENABLE
sSET MAINTENANCE WRAP

CLR
MOV

172020

TEST THAT RDR ENABLE CLEARS RECEIVER DONE FLAG

SCOPE
BIT

BNE
RESET

000002

000001

108

RO
#2,R1

s*+ YES DO NOT EXECUTE THIS TEST
;CLEAR EVERYTHING
s** DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
;** THAT MIGHT BE IN THE PROCESS OF BEING
;** RECEIVED TO FINISH AFTER MAINTENANCE
;** WRAP FOR THE UART UNDER TEST IS ENABLED.

TSTB
DEC
BNE
DEC
BNE
CLR
TSTB
BPL
BIT
BEQ

aRBUF
RO
42%
R1
42%
aTBUF
aR(SR
%
#81T0,aRCSR
2%

;** READ TO CLEAR DONE
g oe
see
s
goe
;LOAD TRANSMITTER
;WAIT FOR RECEIVER DONE

ERROR

+117

;RDR ENABLE NOT CLEARED WITH RCV ACTIVE

BIS
TSTB
BEQ

#B1T0,aRCSR
aR(SR
108

;CLEAR DONE BY SETTING RDR ENABLE
sCHECK FOR DONE CLEAR
;** BR, IF CLEAR TO NEXT TEST

BIC

#BIT2,aCTCSR

ERROR

+67

NOP

sVERIFY RCV ACTIVE CLEARED RDR ENABLE
;BR IF CLEAR

;**» DISABLE MAINTENANCE MODE FOR
s** CONSOLE TO ALLOW FOR COMMUNICATION
s*~ WITH TERMINAL.

;SETTING RDR ENABLE

DID NOT

CLEAR RCVR DONE

| CZDLDHO DL11=W 11/44 MFM SLU

MACRO M1113

07-JuL-81 15:03

| TEST # 33 = TEST THAT RCVR INTERRUPTS ONLY WHEN ENABLED

LSBTTL

2881

105777

005300
001374
005301
001372
017703
012777
004737
000140
005077
105777
100375

042777

TEST # 33 = TEST THAT RCVR INTERRUPTS ONLY WHEN ENABLED

71672
011010
014502

000004

d§gdd

NNN
—(N
Ss00N0O

p—

NNN

1%:

171642

2%:

(¥,
Te

171604

—_—

000004

3%:

:QQ

140

#BIT2,aCTCSR

#4% ,ARVECT

#31T6,aRCSR

#81T2,aCTCSR
+72

1544
1562

4%:

5%:

TO CLEAR DONE

:t'

(SP)+,(SP)+
+71

011060
000100

READ

SRk

#B1T2,aCTCSR

171652

THAT MIGHT BE IN THE PROCESS OF BEING
RECEIVED TO FINISH AFTER MAINTENANCE
WRAP FOR THE UART UNDER TEST IS ENABLED.

* w N

#2% ,ARVECT
PC ,WRPSW
aTBUF
aRCSR
1%

;DISABLE TRANSMIT INTERRUPTS
;DISABLE RECEIVER INTERRUPTS
sSET MAINTENANCE WRAP
s** DELAY ENOUGH TIME TO ALLOW ANY CHARA(CTERS
;#*
;#«
;**
;*«

aRBUF
RO

.WORD

—

lh i
b

i
e

il
b

b cid
b

-l

eolelelelelelefele

b
b
b
b
=

aud

171542

2913 011076

010377

000100
000004

olelelele]

RO
#2,R1

104072
000401
022626
042777
042777

#RIT6,aTCSR
#B176,aRCSR
#B1T2,aTCSR

aRVECT ,R3

171664

104071

012777
052777
000240
000240
000240
000240
042777

SCOPE
BIC
BIC
BIS
CLR

R1
42%

171650
171636

022626

nN=O

42%:

RRRRFIC 8=
o‘b'\)o&of\) oo

042777

THAT RCVR INTERRUPTS ONLY WHEN ENABLED

42%

2896 011010
2897 011010

15133:

MoV

171700

TEST

2222222222222 2222202222202
22220222222 2202 RRRRdd]

000002

2894 011006

000405

000100
000100
000004

010732
010736
010740
010742
010744
2886 010746
2887 010752
2888 010760
2889 010764
2890 010766
010772
2892 010776
2893 011000

000004
042777
042777
052777
005000
012701

—

010700
2882 010702
2883 010710
2884 010716
2885 010724
010726

b
aul =B

SEQUENCE

AR AR AR AR AR ARRARAA AR AARARAAARAAAAARARRAARARAAAARAR
AR

TRTEST 33

¥YY L

I_6
PAGE 57

(SP)+,(SP)+

#BIT6,aRCSR
#81T2,aCTCSR
R3,aRVE(CT

sSAVE RECEIVE VECTOR
sPOINT RCV VECTOR TO ERROR REPORT
;SET PSW TO PRIORITY 3
- ;SEND A CHARACTER

;WAIT FOR RECEIVER DONE

;%= DISABLE MAINTENANCE MODE FOR
;** CONSOLE TO ALLOW FOR COMMUNICATION
;** WITH TERMINAL.

;CONTINUE TEST

s*x DISABLE MAINTENANCE MODE FOR
s** CONSOLE TO ALLOW FOR COMMUNICATION
s** WITH TERMINAL.

JRESTORE SP AFTER INTERRUPT

JRECEIVER INTERRPUTS WITH INT.

ENABLE

sPOINT RCV VECTOR TO END OF TEST
sENABLE RCV INTERRUPTS
;** GIVE ANY INTERRUPTS TIME
s** GIVE ANY INTERRUPTS TIME
;** GIVE ANY INTERRUPTS TIME
;** GIVE ANY INTERRUPTS TIME
s** DISABLE MAINTENANCE MODE FOR
;** CONSOLE TO ALLOW FOR COMMUNICATION
s** WITH TERMINAL.
JRCVR DID NOT INTERRUPT
;BRANCH OVER STACK CORRECTION
JRESTORE SP AFTER INTERRUPT
;DISABLE INTERRUPTS
;*~ DISABLE MAINTENANCE MODE FOR
;** CONSOLE TO ALLOW FOR COMMUNICATION
s*~ WITH TERMINAL.

JRESTORE RECEIVE VECTOR

CLEAR

—

J 6
MACRO M1113 07-JuL-81 15:03 PAGE 58
TEST # 34 - TEST THAT RCVR INTERRUPTS DO NOT OCCUR WHEN DISABL

i CZDLDKO DL11=W 11/44 MFM SLY
2914

SBYTL
S

TEST # 34 - TEST THAT RCVR INTERRUPTS DO NOT OCCUR WHEN DISABLED

Aii22 2222222222222
2R
2202222022
]

MOV
MOV
BIS
CLR
MOV

-1

171524
011216
000004

SCOPE

000002

A AR

#2$ ,3RVECT

#B172,3TCSR

RO
#2 ,R1

sPOINT RCVR VECTOR TO ERROR REPORT
sSET MAINTENANCE WRAP
* k%

* k&

O~ NVO

ad wd

rornorororRONON)

SRANIEVELRNEEN

. k%

105777
100375

:
(2%

171470

167666
171452
171440

052777
000240
000240
000240
000240
000405

000100

042777

000004

aRBUF
RO
42%
Ri

* RN

c kW

*xk
2

:TEST FOR XMIT READY

a TBUF
aR(SR
1%
#BIT6,aRCSR

1%:

171430

;LOOP IF NOT
;SEND A CHARACTER
;WAIT FOR RECEIVER DONE

;ENABLE INTERRUPTS
*kw

]

* k%

171434

#BIT2,aCTCSR

*hkw

*hR

022626

(SP)+,(SP)+

104073

000004

000100
011266
014502

1376
1400

042777
012777
004737
000140
000240
000240
042777

+73
-

2935 011224
2936 011226

3%:

#B1T6,aRCSR

#4% ,ARVECT
PC,WRPSW

.WORD

171374

BIC

GIVE
GIVE
GIVE
GIVE

TIME
TIME
TIME
TIME

;CONTINUE TEST

2%:

DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
THAT MIGHT BE IN THE PROCESS OF BEING
RECEIVED TO FINISH AFTER MAINTENANCE
WRAP FOR THE UART UNDER TEST IS ENABLED.
READ TO CLEAR DONE

. W

42%
a$TPS
6%

6%:

;SAVE RECEIVE VECTOR

SRR

105777
005300
001374
005301
001372
105777
100375
005077

RAAARA AR AR AR

;CLEAR EVERYTHING
;SET PSW TO PRIORITY 7

RESET

JSR

014502

000004
000005
004737
000340
017703
012777
052777
005000
012701

TST34

FRESRRERS

TEST THAT RCVR INTERRUPTS DO NOT OCCUR WHEN DISABLED

AR AR AR A AR AR A AR AR R AR

—

) cd

)

) —d

) - cnd wd

[elelelel=lols
oo
— -l
) - i d

=0V~

3= -

'TEST 34

0833V
V3
NN-J—‘—._‘—J

SEQUENCE

140

#BIT2,aCTCSR

FOR
FOR
FOR
FOR

INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT

DISABLE MAINTENANCE MODE FOR
CONSOLE TO ALLOW FOR COMMUNICATION
WITH TERMINAL.

sRESTORE SP AFTER INTERRUPT

;RCVR INTERRUPTS AT PRIORITY 7
;CLEAR INTERRUPT ENABLE
sPOINT RCVR VECTOR TO_ERROR REPORT

;SET PSW TO PRIORITY 3

;GIVE TIME FOR ANY INTERRUPT
GIVE TIME FOR ANY INTERRUPT
* DISABLE MAINTENANCE MODE FOR

CONSOLE TO ALLOW FOR COMMUNICATION
WITH TERMINAL.
:BR TO END OF TEST, IF NO INTERRUPT
tt

000405

042777

000004

171364

4%:

BIC

#B1T2,aCTCSR

* kR

022626
104074

010377

171340

5%:

CMP
ERROR

5;2)*.(5P)+

MOV

R3,aRVECT

DISABLE MAINTENANCE MODE FOR
CONSOLE TO ALLOW FOR COMMUNICATION

*hw WITH
TERMINAL
.
JRESTORE SP AFTER INTERRUPT
.

sRCVR INTERRUPT REQUEST PASSED WITH BIT6 (LEAR
JRESTORE RECEIVE VECTOR

CZDLDHO DL11=W 11/44 MFM SLU

MACRO M1113

TEST # 35 = TEST RECEIVER FOR DOUBLE

07-JuL=-81 15:03

INTERRUPTS

.SBTTL

2953

PAGE 59

SEQUENCE

TEST # 35 = TEST RECEIVER FOR DOUBLE INTERRUPTS

it i 2232222222222
2222
2R
R
RRR R Rl d )]

T*TEST 35

2967 011412
2968 011420
2969 011422
2970 011424
2971 011426
2972
2973 011430
2974 011432
2975 011434
2976 011436
2977 011444
2978 011450
2979 011452
2980 011454
81 011456
2982 011460
2983 011462
2984 011470
2985 011474
5339 011500

052777
000240
000240
000240
000240

2988 011502
2989 011504
2990
2991 011506

022626
104076

104075
000401
022626
012777
004737
000140
000240
000240
000240
000240
042777
010377
010477
000402

010377

#340, aRPSW
PC,WRPSW

140
.WORD
#BIT2,aTCSR

171270

RO
#2.R1

000002

aRBUF
RO
42%
R1
42%
aTBUF
?RC SR
$

428:

171244
171232

18:

000004

171246

000100

171214

#BIT2,aCTCSR
#B1T6,aRCSR

+75

011502
014502

000100
171150
171146

171200

28:

(SP)+,(SP)+
#3% ,aRVECT

25%:

PC ,WRPSW

140

171144

#BIT6,aRCSR
R3,aRVECT

R4 ,QRPSW
4%

38:

171132

25%

48:

ERROR

(SP)+,(SP)+
+76

MOV

R3,aRVECT

sSAVE RECEIVE PSW VECTOR

sPOINT RCV VECTOR_TO CONTINUE

TEST

;SET PRIORITY TO 7 AFTER INTERRUPT
;SET PSW TO PRIORITY 3
sSET MAINTENANCE WRAP

;*% DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
;*«
;*«
;**
;**

005301
001372
005077
105777
100375
042777

#2% ,QRVECT

171316
171312

171254

INTERRUPTS

;CLEAR EVERYTHING
sSAVE RECEIVE VECTOR

011366
011370
2963 011372
2964 011376
2965 011402
2966 011404

000004

@RVECT,R3
R4
aRPSW,

»
»

105777
005300
001374

171330
171326
011434
000340
014502

011356
011362
011364

7§135:

5
017703
017704
012777
012777
004737
000140
052777
005000
012701

011304

2954 011306
2955 011310
2956 011314
2957 011320
2958 011326
2959 011334
2960 011340
2961 011342
2962 011350
011352

TEST RECEIVER FOR DOUBLE

iii2223222222222
R dd R
RRdRRdRddRdd )

THAT MIGHT BE IN THE PROCESS OF BEING
RECEIVED TO FINISH AFTER MAINTENANCE
WRAP FOR THE UART UNDER TEST IS ENABLED.
READ TO CLEAR DONE

* kR

;SEND A CHARACTER

;WAIT FOR RCVR DONE

s** DISABLE MAINTENANCE MODE FOR
s** CONSOLE TO ALLOW FOR COMMUNICATION
s** WITH TERMINAL.
;ENABLE RCV INTERRUPTS
s** GIVE SOME TIME
;** GIVE SOME TIME
;** GIVE SOME TIME
;** GIVE SOME TIME
sRCVR INTERRUPT DID NOT OCCUR
;BRANCH OVER STACK CORRECTION
JRESTORE SP AFTER INTERRUPT
sPOINT RCV VECTOR TO ERROR REPORT

JRESET PSW TO PRIORITY 3
;** GIVE SOME TIME
;** GIVE SOME TIME
;** GIVE SOME TIME
;** GIVE SOME TIME
sCLEAR INTERRUPT ENABLE

;RESTORE RECEIVE VECTOR

JRESTORE RECEIVE PSW VECTOR
;BR TO END OF TEST
JRESTORE SP AFTER INTERRUPT

;RECEIVER RE=INTERRUPTED
JRESTORE RECEIVE VECTOR

CZDLDHO DL11-w 11/44 MFM SLU

MACRO M1113

07-JuL-81 15:03

TEST # 36 - TEST THAT RCVR INTERRUPT CLEARS BY READING RBUF

.SBTTL

992

S*TEST 36
AR

2996 011524
2997 011530
2998 011536
2999 011544
3000 011552
011554

011560
011564

011566

011570
011572
3001 011574

3002 011600
3003 011604

000004
000005
004737
000340

017703
012777
052777

052777
005000
012701
105777
005300

TST36:

014502

171114
011646
000100
000004

171066

171052

42%:

001374

005301
001372
005077

171042

3004 011606

000004

3005 011614

005777

171016

004737
000140
000240
000240
000240
000240
042777
000402

3015 011646
338}9 011650

022626
104077

3018 011652

010377

171030

1%:

171044

014502

000100

170766

AR AR

SCOPE
RESET
JSR

AR AR AR A AR

AR AR AR AR

PC,wWRPSW
.WORD
340

MOV
MOV
BIS

aRVECT ,R3
#2% ,aRVECT
#B1T6,aRCSR

TSTB
DEC

aRBUF
RO

#BIT2,aTCSR
RO
#2,R1

BNE

42%

TSTB
BPL

BIC

aRCSR
1%
#BIT2,aCTCSR

TST

aRBUF

DEC
BNE
CLR

JSR

AR AR AR AR AR

AR AR

TEST THAT RCVR INTERRUPT CLEARS BY READING RBUF

AR AR A A AR AR AR AR AR

BIS
CLR
MOV

000002

105777
100375
042777

3006 011620
3007 011624
3008 011626
3009 011630
3010 011632
3011 011634
3012 011636
338}2 011644

171106
171070

SEQUENCE

TEST # 36 - TEST THAT RCVR INTERRUPT CLEARS BY READING RBUF

AR AR AR AR AR AR AR AR

011512
2993 011514
2994 011516
2995 011522

L 6
PAGE 60

R1
42%
aTBUF

PC,WRPSW
.WORD
140

A AR

;CLEAR EVERYTHING

;SET PGW PRIORITY TO 7

;SAVE RECEIVE VECTOR
sPOINT RCV VECTOR TO ERROR REPORT
;SET RCVR _INTERRUPT ENABLE

;SET MAINTENANCE WRAP
;** DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
;*% THAT MIGHT BE IN THE PROCESS OF BEING
s** RECEIVED TO FINISH AFTER MAINTENANCE
s** WRAP FOR THE UART UNDER TEST IS ENABLED.
;** READ TO CLEAR DONE
" e
"
"Lneny
goe
;SEND A CHARACTER
;WAIT FOR DONE (INTERRUPT)

;*% DISABLE MAINTENANCE MODE FOR
s** CONSOLE TO ALLOW FOR COMMUNICATION
s** WITH TERMINAL.

JREAD RBUF TO CLEAR PENDING INTERRPUT

;SET PSW TO PRIORITY 3

NOP
NOP
NOP
NOP
BIC
BR

#BI1T6,aRCSR
3%

2%:

CMP
ERROR

(SP)+,(SP)+
+77

JRESTORE SP AFTER INTERRUPT
sREADING RBUF DID NOT CLEAR INTERRUPT

3%:

MOV

R3,aRVECF

;RESTORE RECEIVE VECTOR

170770

;%% ALLOW TIME FOR ANY ERRONEOUS
s*x ALLOW TIME FOR ANY ERRONEOUS
s** ALLOW TIME FOR ANY ERRONEOUS
s*x ALLOW TIME FOR ANY ERRONEOUS
sNO INTERRUPT=CLEAR INT. ENABLE

;DPM00Z2

INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT

CZDLDHO DL11=wW 11/44 MFM SLU

MACRO M1113

TEST # 37 = TEST THAT RESET CLEARS RECEIVE

3019

07-JUL-81 15:03

INTERRUPT

.SBTTL

PAGE 61

SEQUENCE

TEST # 37 = TEST THAT RESET CLEARS RECEIVE INTERRUPT

::"'tQ"*.'fi.l’t!.'fi'.."""filfi"i..t.'.t.'.'..Qfi.'fi'."."'."'

S*TEST 37

TEST THAT RESET CLEARS RECEIVE INTERRUPT

.' "tt"'Q'...."t.*'*Q"'."'.."Q..'..."'l’"'tt'i!."Q."'Q"'.Q

011656
3020 011660

3021 011662
3022 011666
3023 011670
3024 011676

000004
000005

T§137:

004737
000340
017703
012777

014502
170750
012004

170742

JSR

052777
005000
012701

000004

170722

3025 011702 052777 000100 170724

3026 011710
3027 011716
011720

011724

011730

105777

005300

SCOPE
RESET

BIS
CLR
MOV

#BIT2.3TCSR
RO
#2,R1

BIS

000002

170706

MOV
MOV

PC,WRPSW
.WORD ~ 340
ARVECT,R3
#2$ ,aRVECT

42%:

TSTB

aRBUF
42%

DEC

011732

001374

BNE

011736
3028 011740
3029 011746
3030 011752
3031 011754

001372
012777
105777
100375
000005

BNE
MoV
TSTB
BPL
RESET

011734

3032 011756

3033 011762
3034 011764
3035 011766
3036 011770
3037 011772
\3038 011774
3039 012002

3042 012004
3043 012006
3044

3045 012010

005301

004737

000140
000240
000240
000240
000240
042777
000402

DEC

000377
170662

1%:

014502

000100

022626
104100

010377

170674

170630

JSR

NOP
NOP
NOP
NOP
8IC
BR

170632

#B8176,3RCSR

;CLEAR EVERYTHING

*SET PSW TO PRIORITY 7
;SAVE RECEIVE VECTOR
*POINT RCV VECTOR TO ERROR REPORT

*SET RCV INTERRUPT ENABLE

*SET MAINTENANCE WRAP
*x* DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
ixx THAT MIGHT BE IN THE PROCESS OF BEING
;*% RECEIVED TO FINISH AFTER MAINTENANCE
;** WRAP FOR THE UART UNDER TEST

;** READ TO CLEAR DONE

gos

' i

428
#377 ,aTBUF
aRCSR
1%

PC,WRPSW
.WORD

IS ENABLED.

140

o
;SEND AN ALL 1'S CHARACTER
;WAIT FOR RCV DONE
;CLEAR RCV INTERRUPT & RBUF

;SET PSW TO PRIORITY 3

;%% ALLOW TIME FOR AN ERRONEOUS
s** ALLOW TIME FOR AN ERRONEOUS
;** ALLOW TIME FOR AN ERRONEOUS
s*% ALLOW TIME FOR AN ERRONEOUS
sNO INTERRUPT-CLEAR INT. ENABLE
;CONTINUE TEST

#B1T6,aRCSR

INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT

2%:

CMP
ERROR

(SP)+,(SP)+
+100

sRESTORE SP AFTER INTERRUPT
JRESET DID NOT CLEAR RCVR INTERRUPT

3%:

MOV

"R3,3RVECT

JRESTORE RECEIVE VECTOR

TEST # 40 - TEST THAT THE "OR'' ERROR & 'ERROR'' CAN BE SET

A A AR A A AR AR AR AT

001404
032777

3056 012052
3057 012054
3058 012056
3059 012064
012066

167014

000001

003002

002624
000010

166766

001452
000004

012701

TST40:

170554

9%:

000002

SCOPE
BIT
BEQ
BIT
BEQ

#RIT10,aSWR
TST41

#BITO,FLAG4LS

TST

9%
CTSTFL

BEQ
BIT

#B1T03,aSWR

BEQ
RESET
BIS

MOV

TST41

#BIT2,aTCSR

RO
#2,R1

NO
;ES THIS IS 11/44.
NO

ERROR TEST BE PERFORMED
NO

42%

000003

#3,R0
aTBUF
aTCSR

170524
170516

042777

000004

aRBUF
RO
42%
R1

2%
RO
1%
#BIT2,aCTCSR

170522

*hn
*h%

]

—
—h b

—_—
) -

#BI1T14 ,aRBUF
3%
+101

170460

#B1T15,aRBUF

+102

4%:

—

100000

—
) — —

LNLNLV LV

(elelelelelele BN elels]

VLN

~N
~N

040000

000002

408:

DEC

#2,R1
RO
40%
R1
40%

WRAP FOR THE UART UNDER TEST
READ TO CLEAR DONE

IS ENABLED.

* kR

sSET CHARACTER COUNT TO SEND 3 CHAR.
;LOAD TRANSMIT BUFFER
sWAIT FOR TRANSMIT DONE

;DECREMENT CHARACTER COUNT
:BR IF ALL CHARACTERS NOT TRANSMITTED
. kK

:tt

170472

DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
THAT MIGHT BE IN THE PROCESS OF BEING
RECEIVED TO FINISH AFTER MAINTENANCE

* k%

:tt

032777

IS THE CONSOLE SLU.SHOULD THE OVERRUN

»
»

TSTB

THIS

IS THIS THE CONSOLE

>
»

005300

42%:

:CLEAR EVERYTHING
sSET MAINTENANCE WRAP

* kR

170540

AR AR AR AR

;IS THIS TEST ENABLED
JIF NO7 _ENABLED, BR TO NEXT TEST
%*
IS THIS A 11744

]

105777

AR AR AR

3053 012042
3054 012044
3055

3052

002000

R AR AR

% 22
% %2

000004
032777
001465
032737
001407
005737

A AR AR A AR AR AR A AR AR R AR R AR

R I R TR

012014
3047 012016
3048 012024
3049 012026
3050 012034
3051 012036

AR AR R AR A AR AR AR

TEST THAT THE 'OR'' ERROR & 'ERROR'' CAN BE SET

%
%
%
%

S*TEST 40

» %
%

SEQUENCE

.SBTTL

N 6
PAGE 62

DISABLE MAINTENANCE MODE FOR
CONSOLE TO ALLOW FOR COMMUNICATION
WITH TERMINAL.

;TEST FOR ''OR'' ERROR FLAG
:BR, IF SET

:"OR"* ERROR FLAG DID NOT SET
sTEST "ERROR'' FLAG

:BR, IF SET

:"ERROR'* FLAG DID NOT SET WITH "OR'* FLAG
*kk

* kK
*R%

* kR
*hR

* kW

* kK

DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS

THAT MIGHT BE IN THE PROCESS OF BE ING
TRANSMITTED TO FINISH BEFORE MAINTENANCE
WRAP FOR THE UART UNDER TEST IS DISABLED.
THIS WILL INHIBIT ANY COMMUNICATION
TO HARDWARE MEDIA SUCH AS TUS8 THAT MIGHT
BE ATTACHED TO UART UNDER TEST.

—————————————

§ -

D L 1=W 11744 MFM SLU
MACRO M1113 07-JuL=-81 15:03
40
TEST THAT THE "OR'' ERROR & 'ERROR'' CAN BE SET

THAT BREAK TRANSMITS ALL ZEROES

TEST # 41 = TEST THAT BREAK TRANSMITS ALL ZEROES

012256
012262
012264
012266
012270
3092 012272

3093 012300
3094 012304
3095 012306
3096 012312
3097 012320
3098 012322
3099 012330
3100 012332
3101 012334
3102
3103 012336
3104 012344

BEQ
BIT

#B1T03,aSWR

;BR

000010

166602

001466
000004

012701

000002

105777

170354

005300
001374
005301
001372
012777
105777
100375
005077
052777
005000
117737
100411

177777
170330
170324

170370

9%:

RESET

000001

170320

170306

001026

000001
000004

170306

1%:

TSTB

#=1,3TBUF
aR(SR
1%

2%:

MOVB

CONT41:

000001
000004

IF NOT ENABLED

NO
YES THIS IS 11/44. IS THIS THE CONSOLE
SLU
NO
THIS IS THE CONSOLE SLU.SHOULD THE BREAK
LSST BE PERFORMED

;CLEAR EVERYTHING
;SET MAINTENANCE WRAP
s*+ DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
;** THAT MIGHT BE IN THE PROCESS OF BEING
;*x RECEIVED TO FINISH AFTER MAINTENANCE
;** WRAP FOR THE UART UNDER TEST IS ENABLED.
;** READ TO CLEAR DONE

*hw
* kR

L2]
:tt

;TRANSMIT ALL ONES TO RCVR
JWAIT FOR RCVR DONE

;CLEAR A TIMER

aRCSR, $BDDAT
CONT41
RO
2%

aRBUF

3%
#B1T0,aTCSR
#BIT2,aCTCSR

170250
170262

TEST,

IS THIS A 11744

+103
170256

TO NEXT

;CLEAR DONE (LEAVING ALL ONES IN RBUF)

#81T0,aTCSR
#BIT2,aCTCSR

170274

)

aRBUF

lngO.aTCSR

104103

105777
001407
042777
042777

#BIT2,aTCSR

aRBUF
RO
42%
R1
42%

005200
001372

042777
042777

TST42

RO
#2 ,R1
42%:

170342

001404
032777

TST

R 0

;1S BREAK .FUNCTION TEST ENABLED?

002624

#RIT8,aSWR
TST42
#BITO,FLAG44
9%
CTSTFL

003002

SCOPE
BIT
BEQ
BIT
BEQ

000001

TST41:

166630

000400

2222222223222 2222220222222

000004
032777
001501
032737
001407
005737

2332222322222

012200
3079 0122C2
3080 012210
3081 012212
3082 012220
3083 012222
3084
3085 012226
3086 012230
3087
3088 012236
3089 012240
3090 012242
3091 012250
012252

TEST THAT BREAK TRANSMITS ALL ZEROES

2232333223222

S*TEST 41

3232222220222 22222202222
iRt
RdRd sl ]

'l-n»ntng

(SR 2222222222222

SEQUENCE

.SBTTL

3078

8.7
PAGE 63

= TEST

07-JuL-81 15:03

TEST # 41

MACRO M1113

CZDLDHO DL11=W 11/44 MFM SLU

: TRANSMIT BREAK

;WAIT FOR RCVR DONE

:BR IF DONE
;IF NOT, INCREMENT TIMER
;BR IF TIME REMAINS
:CLEAR BREAK BIT
;** DISABLE MAINTENANCE MODE FOR
s** CONSOLE TO ALLOW FOR COMMUNICATION
s** WITH TERMINAL.
;BREAK DID NOT TRANSMIT ANYTHING

;CHECK RECEIVE BUFFER FOR ZERO
;BR, IF ZERO
;CLEAR BREAK BIT
;** DISABLE MAINTENANCE MODE FOR
s** CONSOLE TO ALLOW FOR COMMUNICATION
s** WITH TERMINAL.

104103

042777
042777

000001
000004

170232
170244

3%:

BIC

+103

;BREAK DID NOT TRANSMIT ALL ZEROES

#B110,aTCSR
#BIT2 ,aCTCSR

;CLEAR BREAK BIT
s** DISABLE MAINTENANCE MODE FOR
s** CONSOLE TO ALLOW FOR COMMUNICATION
;** WITH TERMINAL.

CZDLDHO DL11=W 11744 MFM SLU

MACRO M1113

07-JUL-81 15:03

TEST # 42 = TEST THAT 'FR'' ERROR CAN BE SET DURING BREAK

3116

.SBTTL

PAGE 64

SEQUENCE

TEST # 42 - TEST THAT 'fFR'' ERROR CAN BE SET DURING BREAK

: .-ttt'ttt.tt't!ttttttt"tttttttt'tttittt.titttttttttttttttttt"tt

s*TEST 42

TEST THAT "'FR'' ERROR CAN BE SET DURING BREAK

; ;ttttt.tt'tttttttttttttt"ttttt'tt'tttttttfittt't*ttt.ttt't'ltt't

012414

000004

3117 012416
3118 012424
3119 012426
3120 012434

032777
001464
032777
001460

3122 012444
%}22 012446

001407
005737

3121 012436

032737

002000

166414

000400

166404

000001

003002

001404
032777

3128 012462
3129 012464
3130 012466
3131 012474

001445
000005
052777
005000
012701

000002

012502
012506
012510
012512
012514
3132 012516
3133 012524
3134 012530
3135 012534
3136 012536
3137 012544

105777
005300
001374
005301
001372
052777
005077
105777
100375
042777
042777

170130

3138 012552

032777

3141 012562
3142

104104

012476

g}%g 012560

001001

3143 012564
%}22 012572

032777
001001

3146 012574

104114

3147
3148 012576

000010

000004

166356

170144

SCOPE

BIT
BEQ
BIT
BEQ

#RIT10,3SWR
TST43
#B1T8,aSWR
TST43

;1S THE ''TEST ERROR FLAGS'' BIT SET
:BR TO NEXT TEST, IF NOT SET
;1S BREAK FUNCTION ENABLED
:BR TO NEXT TEST, IF NOT SET

BEQ
TST

9%
CTSTFL

s*x NO
e gfa THIS IS 11/44.

BEQ
BIT

9%
#R1T03,aSWR

BEQ
RESET
BIS
CLR

TST43

s*% NO
;%% THIS IS THE CONSOLE SLU.SHOULD THE FRAME
:*%x ERROR TEST BE PERFORMED
s** NO
;CLEAR EVERYTHING
;SET MAINTENANCE WRAP
:*x DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
:+* THAT MIGHT BE IN THE PROCESS OF BEING
;%% RECEIVED TO FINISH AFTER MAINTENANCE

BIT

002624

3125 012452
3126 012454
3127

TST42:

9%:

MOV

#BIT2,aTCSR
RO
#2.R1
aRBUF
RO
42%
R1
42%
#81T0,aTCSR
aTBUF
aRCSR
1%
#B1T0,aTCSR
#BIT2,aCTCSR

000001
170112
170100

170114

000001
000004

170074
170106

TSTB
DEC
BNE
DEC
BNE
BIS
CLR
TSTB
BPL
BIC
BIC

020000

170056

BIT

#B]1T13,aRBUF

ERROR

+104

BIT
BNE

#81T15,aRBUF
3%

ERROR

+114

100000

42%:

#81T0,FLAGSLS

1%:

170044

BNE

2%:

3%:

sxx [S THIS A 11744
21

IS THIS THE CONSOLE

:*= WRAP FOR THE UART UNDER TEST

IS ENABLED.

;*x READ TO CLEAR DONE
ML
Jaw
ok
Jx%
:SEND BREAK
:TRANSMIT A CHARACTER TO TIME BREAK
:WAIT FOR RCVR DONE
:CLEAR BREAK BIT
:x* DISABLE MAINTENANCE MODE FOR

;*» CONSOLE TO ALLOW FOR COMMUNICATION
% WITH TERMINAL.

;CHECK FOR FRAMING ERROR FLAG

;BR,

IF SET

;BREAK DID NOT SET FRAMING ERROR

:TEST '‘ERROR' FLAG
DR, IF SEV

:"ERROR'' FLAG DID NOT SET WITH "OR'' FLAG

wno

LDHO DL11=W 11/44 MFM SLU

MACRO M1113

07-JuL-81 15:03

T # 43 - TEST DATA PATH FROM XMIT TO REC USING MAINT WRAP

3149

.SBTTL
e

D 7
PAGE 65

SEQUENCE

TEST # 43 - TEST DATA PATH FROM XMIT TO REC USING MAINT WRAP

S*TEST 43

2Rt

222220

022002

2220

)

TEST DATA PATH FROM XMIT TO REC USING MAINT WRAP

a2 i 22222222222ttt
222 222 R
22222200 22

78743

000004
000005
052777

005000
012701

000004

SCOPE
RESET
BIS

170030

CLR
MOV

000002

#BI1T2,aTCSR

S¢L EAR EVERYTHING
;SE T MAINTENANCE WRAP

s TRANSMIT A GINARY COUNT PATTERN = UP

;TO THE BIT POSITION INDICATED BY THE
;CONTENTS OF LOCATION ‘‘SUSWR''
;tt

#2 ,R1

»
*

012576
3150
3151 012600
3152 012602
3153
3154
3155
3156 012610
012612

*h
R

000001

000020

000220

—_

12652
12654

5%:
2%:

167754

12666
12672
12674

3169 012700
3170 012704
3171 012706
3172 012710
3173 012712
3174 012714
3175 012716
3176 012722
3177 012726

003002

1%:

167742

167736
001112

TSTB

#BITO,FLAG4LS
5%

#20,R1
1%
#220,R1
1$
R1,aTBUF
aR(SR

2%
aRBUF ,R2
,R1
a#BUSWR

R1.R2

sCL EAR REGISTER FOR TEST DATA
.
.
; INCREMENT THE TEST DATA

;tt

* kR

. k%

M2]

;BR,

S wWro

IF NON-(C OMPARE

STE ST XMIT DATA FOR ZERO
010237
042777

001024
001026
000004

3%:
167724

R1,$GDDAT
R2,$BDDAT

#81T72,aCTCSR

:BR, IF FINISHED
sCONTINUE IF NOT
2S7 ORE THE EXPECTED DATA
;87 ORE RECEIVED DATA

:tt

104105

042777

+105

000004

167714

#BIT2 ,aCTCSR

DISABLE MAINTENANCE MODE FOR
CONSOLE TO ALLOW FOR COMMUNICATION

WITH TERMINAL.

;DATA COMPARE DATA
- hw

c kR

WNWW

DO NOT XMIT 220

. GE T RECEIVED CHARACTER
sCL EAR LOWEST UNUSED DATA BIT POSITITON IN TEST DATA
; COMPARE DATA

CHECK
FOR CONT=P IN TEST DATA
DO NOT XMIT “P

‘WAIT FOR RECEIVER DONE

* R

8
8
18

TEST ALL DATA

*XMIT A CHARACTER

;tt

11744 CPU

;tt

3178 012734
3179
3180 012736
3181 012736

RECEIVED TO FINISH AFTER MAINTENANCE
WRAP FOR THE UART UNDER TEST IS ENABLED.
READ TO CLEAR DONE

=
»

»
%
%
»

DEC
BNE
DEC
BNE
CLR
INCB
BIT

»
%

005300

42%:

170014

SevavLn.

105777

nony

012616
012622
012624
012626
012630
012632
(olelelelelelelole]

ooconrOrONONOMNNYIN
SEAEARRARZLESHS

cld

WWWWWWWWWWWW

DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
THAT MIGHT BE IN THE PROCESS OF BEING

DISABLE MAINTENANCE MODE FOR
CONSOLE TO ALLOW FOR COMMUNICATION

WITH TERMINAL.

CZDLDHO DL11=w 11/44 MFM SLU

MACRO M1113

07-JuL-81 15:03

TEST # 44 - TEST DATA PATHS USING LOOP-BACK CONNECTOR

.SBTTL

3185

SEQUENCE

TEST # 44 - TEST DATA PATHS USING LOOP-BACK CONNECTOR

‘:"t't".t.'tt"t".'.'Q"""Q'.Q!'.'l.fit.'.Q'Q"QQ"'.'.Q"QQ.

S*TEST 44

TEST DATA PATHS USING LOOP-BACK CONNECTOR

;:Qt"Q"'Q".'l.l'Qi."'""l..t'..'."'."."..'.'Q'QQ".'."'Q

E 7
PAGE 66

000004
032777
001442
000005
005001

000200

166064

TST44:

SCOPE

BIT
BEQ

#RIT7,aSWR
15745

CLR

RESET

;1S THIS TEST ENABLED
*BR, [T NOT

*CLEAR EVERYTHING

“CLEAR REGISTER FOR TEST DATA

*TRANSMIT A BINARY COUNT PATTERN = UP

“TO THE BIT POSITION INDICATED BY THE
105201

032737
001404
023727

3201 013016
3202 013020
3203 013022
3204
3205 013024
3206
3207 013026
3208 013032
3209 013036
3210 013040
3211 013042
3212 013044
3213 013046
3214 013050
3215 013054
3216
3217 013060

000001

003002

002634

177560

1$:

167632

167616

2%:

104064

017702
043701
020102
001003

105701
001406
000745
010137

010237
104106

167604

001112

INCB

BIT
BEQ
CMP

#BITO.FLAG4L
5%
RCSR, #177560

MOV

R1,aTBUF

TSTB
BM]
INC
BNE

@RCSR
38
RO
2%

BEQ

CLR

4%:

TST45

*CONTENTS OF LOCATION '‘SUSWR''
*INCREMENT THE

TEST DATA

:11/44 CPU
:TEST ALL DATA
1S THIS 11/44 CONSOLE TERMINAL SLJ?

*YES, SKIP THIS TEST
SXMIT A CHARACTER

*CLEAR A TIMER

*WAIT FOR RECEIVER DONE
*BR IF DONE
*INCREMENT TIMER IF NOT
*BR IF TIME REMAINS

ERROR

+64

;RECEIVER DONE NOT SET

MOV
BIC
CMP
BNE

aRBUF ,R2
SUSWR,R1
R1.R2
4%

:GET RECEIVED CHARACTER
*CLEAR LOWEST UNUSED DATA BIT POSITITON IN TEST DATA
:COMPARE DATA
*BR, IF NON-COMPARE

BEQ

TST45

‘BR, IF FINISHED

TSTB

001024
001026

MOV

R1,$GDDAT

ERROR

+106

MOV

R2.$RDDAT

“TEST XMIT DATA FOR ZERO

*CONTINUE

IF NOT

*STORE EXPECTED DATA

*STORE RECEIVED DATA

:DATA COMPARE ERROR USING LOOP-BACK CONNECTOR

————

CgDLDHO DL11=w 11/44 MFM SLU

MACRO M1113

07-JuL=81 15:03

}T ST # 45 = TEST DL11=w LOGIC BY EXERCISING THE XMIT,REC, & CL
',

3218

LSBTTL

PAGE 67

SEQUENCE

TEST # 45 = TEST DL11=W LOGIC BY EXERCISING THE XMIT ,REC, & CLOCK

:"t.'Q't"t.t.t'QQQtt"Q"t"'tt".'tttl..'tt.'.'t.t""tQ.ti".'

TeTEST 45

|
|

TEST DL11-W LOGIC BY EXERCISING THE XMIT,REC, & CLOCK

:".ttt'QQ'.QtQ.'tt't..'"".Q"ttI.tttt'tt."'.'.ttl't..'t"t.t't

013062
3219 013064
3220 013066

3221 013072

000004
000005
005037

004737

3222 013076 000340

3223 013100
3224 013104
3225 013110
3226 013114

017703
017704
017705
017737

3231 013152
3232 013160
3233 013166

012777
012777
005737

3227 013122
3228 013130
2229 013136
30 013144

3234 013172

32§5 013174
2236 013202
3237 013204
3238 013212
3239 013220
3240 013226
3241 013224
013236

017737
017737
012777
012777

001415

T$745:
002444

014502
167544
167534
167562
167532

167520
167544
013542
000200

013614
000200
002624

002446
002450
002452
167504
167500
167464
167460

000100

165636

013630
000300
000100
000004

167464
167460
167446
167404

013242
013246
013250
013252
013254
3242 013256
2243 013264
3244 013272
3245 013276
3246 013302
3247 0713304
3248 01330§
3249 013312
3250 013316
3251 013322
3252
3253 013324
3254 013326
3255 013330
3256 013334
3257 013340
3258 013342
3259 01335C
gggg 013352

105777
005300
001374
005301
001372
052777
052777
005037
005037
005001
005000
012702
005077
004737
000140

1673570

3262 013354

104107

000240
000240
062700
062700
001371

032777
001402

MOV
MOV
MOV
MOV

STVECT,R3
ARVECT . R4
aRTCVT RS
aTPSW,STPSW

MOV
MOV
TST

#RCV,aRVECT
#200,aRPSW
CTSTFL

BEQ

000002

TSTB
DEC
BNE
DEC
BNE
BIS
BIS
CLR
CLR
CLR
CLR
MOV
CLR
JSR

2%:

NOP
NOP
ADD
ADD
BNE

167354
167342

000000
000001

167270

BIT
BNE
MOV
MOV
BIS
BIS
CLR
MOV

42%:

002454
167324
014502

000100

PC,WRPSW

MOV
MOV
MOV
MOV

1%:

CLKCNT

JSR

LWORD

032777
001011
012777
012777
052777
(052777
005000
012701

000100
000100
002442
002440

SCOPE
RESET
CLR

BIT
BEQ
RESET
ERROR

340

aRPSW, SRPSW
aRTCPSW,SCPSW
AXMIT,aTVECT
#200,aTPSW

1%
#B]T6,aSWR
1$
#CLK,aRTCVT
#300.aRTCPSW
#BITé,ALKS
#BIT2,aTCSR
RO
#2,R1

aRBUF
RO
42%
R1
42%
#BIT6,aTCSR
#B1T6,aRCSR
XMTCNT
RCVCNT
R1
RO
#BUF ,R2
o TBUF
PC,wRPSW
LWORD
140

#0,R0
#1,R0
28
#BI1T6,aTCSR
3%
+107

:CLEAR EVERYTHING
JINITIALIZE CLOCK COUNT TO ZERO

:SET PRIORITY TO 7
:SAVE
*SAVE
;SAVE
;SAVE

XMIT VECTOR

RECEIVE VECTOR
CLOCK VECTOR
XMIT PSW VECTOR
;SAVE RECEIVE PSW VECTOR
;SAVE CLOCK PSW VECTOR
:POINT TRANSMIT VECTOR TO TRANSMIT ROUTINE
;NO MULTIPLE INTERUPTS ALLOWED
:POINT RECEIVE VFECTOR TO RECEIVE ROUTINE
JNO MULT INTERUPTS
;1S CONSOLE UNDER TEST?
;IF NOT SKIP CLOCK SET UP
;IF YES, ARE CLOCK TEST DISABLED?
*IF YES. SKIP CLOCK SET UP
;POINT VECTOR TO CLOCK INTERRUPT ROUTINE
:NO MULT INTERUPTS
*ENABLE CLOCK INTERRUPTS
;SET MAINTENANCE WRAP
:xx DELAY ENOUGH TIME TO ALLOW ANY CHARACTERS
;** THAT MIGHT BE IN THE PROCESS OF BEING
;** RECEIVED TO FINISH AFTER MAINTENANCE
;** WRAP FOR THE UART UNDER TEST

IS ENABLED.

;xx READ TO CLEAR DONE
P
Pew
iwn
e
;ENABLE TRANSMIT INTERRUPTS
:ENABLE RECEIVE INTERRUPTS
;CLEAR XMIT INTERRUPT COUNTER
;CLEAR RCV INTERRUPT COUNTER
;CLEAR A REGISTER FOR TEST DATA USE
*CLEAR TIMER
:POINT R2 TO RECEIVE DATA STORAGE
:SEND FIRST CHARACTER
:SET PSW TO PRIORITY 3
;WAIT FOR INTERRUPTS
*STALL

*STALL
;ADD INSTRUCTIONS ARE USED TO LENGTHEN LOOP TIME
:
TO COVER THE SLOWEST BAUD RATE ON THE FASTEST CPU

JFINISHED ENTIRE TRANSMISSION
;BR, IF INTERRPUTS ARE DISABLED (FINISHED)
*CLEAR EVERYTHING
;TRANSMIT

INTERRUPT TIMEOUT

IN MAIN. DATA TEST

G_7

CZDLDKO DL1T=W 11/44 MFM SLU
MACRO M1113 07-JUL=-81 15:03 PAGE 67-1
' TEST # 45 = TEST DL11-w LOGIC BY EXERCISING THE XMIT,REC, & CL

023737
001402
000005

3304 013530
3305 013536

—d —d —d
e
-l vl

Role(R NTe SV PN WELN]

3307 013542

002442

002440

3%:

XMTCNT ,RCVCNT
43

;COMPARE THE NUMBER OF
:BR, IF EQUAL
;CLEAR EVERYTHING

ERROR

+110

JRECEIVER DID NOT GET FULL TRANSMISSION
:
IF RCVCNT=0, NO DATA RECEIVED

005737
001411

(%:

002624
000100

165432

002444

5%:

002454

TST

CTSTFL
5%
#BIT6,aSWR

TST
BNE
RESET
ERROR

CLKCNT

BEQ
BIT
BNE

RESET

003002

000020
8%:

014037
010137

001026
001024

6%:

010377
010477
010577
013777
013777
013777
000137

167144
167134
167162

7%:

002442

XMIT:

005237
105201
032737
001403
122701

001770
032701
001404
042777
000402
110177
005000
000002

003002

XCONT:
XRET:

MOvVB
CLR

RTI

;11744 CPU?

;STORE BAD DATA FOR ERROR REPORT
;STORE GOOD DATA FOR ERROR REPORT
;DATA COMPARE ERROR IN EXERCISER

R3,aTVECT

SJRESTORE XMIT VECTOR
sRESTORE RECEIVE VECTOR
sRESTORE CLOCK VECTOR
sRESTORE XMIT PSW VECTOR
JRESTORE RECEIVE PSW VECTOR
sJRESTORE CLOCK PSW VECTOR
;GOTO NEXT TEST

#B1T6,aTCSR

s INCREMENT XMIT INTERRUPT COUNTER
s INCREMENT TEST DATA
;11744 CPU
sTEST ALL DATA
;CHECK DATA FOR “P
;DO NOT XMIT “P
;SEND DATA PATTERN FROM 00 --> 37
:BR, IF MORE DATA TO BE SENT
;CLEAR XMIT INTERRUPT ENABLE

R1,aTBUF
RO

;SEND NEW CHARACTER
:CLEAR TIMER

#20,R1
1%
#8I1T5,R1
XCONT

167036

;CLEAR EVERYTHING
;LOAD RECEIVED DATA POINTER TO RO
;SET UP REGISTER FOR COMPARISON
;COMPARE XMIT & RCV DATA
:BR, IF NOT EQUAL
s INCREMENT COMPARE DATA

- (R0)
, $BDDAT
R1, $GDDAT
111

#B1TO,FLAGLS
2%

2%:

THEN (XMTCNT=RCVCNT)

comP
7%

gTTCNT

1%:

IF RCVCNT=?,

; _ EQUALS THE NO, OF INTERRUPTS LOST.
;1S CONCOLE UNDER TEST?
sIF NOT, SKIP CLOCK COUNT CHECK
:IF YES, ARE CLOCK TESTS DISABLED?
;IF _YES, SKIP CLOCK COUNT CHECK
sCHECK FOR AT LESST ONE CLOCK INTERRUPT
;BR IF INTERRUPTS OCCURRED
;CLEAR MAINTENANCE WRAPAROUND
;NO CLOCK INTERRUPTS IN EXERCISER

JYES, SKIP
;SKIP 20 DATA IF 11/44
:SKIP 20
sFINISHED CHECKING RECEIVED DATA?
:BR, IF NOT FINISHED
:BR TO END OF TEST

R5,aRTCVT
STPSW,aTPSW
SRPSW,aRPSW
SCPSW,aRT(CPSW
ENDEV

000040

167032

#B8UF ,RO

R4 ,aRVECT

000020

000100

+113

#BI1TS,R1

002446
002450
002452
014272

000001

6%
R1
#BITO,FLAG4LS
8%
#20,R1
9%

9%:

000040

R1
(RO)+,R1

COMP:

000001

INTERRUPTS

(MP
BEQ

RESET

104110

106111

N WWNWWIWWWN
ININWWWWINW

3263
3264 013356
3265 013364
3266 013366
3267
3268 013370
3269
3270
3271
3272 013372
3273 013376
3274 013400
3275 013406
3276 013410
3277 013414
3278 013416
3279 013420
3280
3281 013422
3282 013424
3283 013430
3284 013432
3285 013434
3286 013436
3287 013440
3288 013446
3289 013450

SEQUENCE

XRET

JRETURN, WITHOUT SENDING ANY MORE

:RETURN

DATA

pm
s

i CZDLDHO

DL1T1=w 11/44 MFM SLU

MACRO M1113

07-JUL=-81 15:03

TEST # 45 = TEST DL11=w LOGIC BY EXERCISING THE XMIT,REC, & CL

3320

3321 013614
3322 013620
3323 013624
g%gg 013626

017722
005237
005000
000002

167016
002440

RCV:

3326 013630
3327 013634

005237
000002

002444

CLK:

H_7

PAGE 67-2

SEQUENCE

MOV
INC
CLR
RTI

@RBUF , (R2) +
RCVCNT
RO

;STORE RECEIVED DATA
s INCREMENT RCV INTERRUPT COUNTER
;CLEAR TIMER
sRETURN

INC

CLKCNT

s INCRENMENT CLOCK INTERRUPT COUNT
sRETURN

RTI

~
' CZDLDHO DL11=w 11/44 MFM SLU

MACRO M1113

;TESY # 46 = TEST CONSOLE WITH WRAP ARQUND

3328

07-JuL-81

LSBTTL
R

J*TEST 46

7329

;g%?

013636

3332

3333
3334
3335
3336
3337
3338

000004

AR AR AR R AR AR AR AR R

TST46:
IR

176500

176502
176504
176506
003014
025222

SEQUENCE

TEST # 46 - TEST CONSOLE WITH WRAP AROUND

g
PAGE 69

15:03

TEST

AR AR R AR AR AR AN R AR R IR R AR

RN AR AR AR R

CONSOLE WITH WRAP AROUND

AR AR AR AR AR AR AR

SCOPE

R AR AR AR AR R A AR R AR

AR AR AN AR AR AR RN AN AR AR AR

R AR AR R R AR AR AR AR AR R

WRAPAROUND TESTING= AUTO INITIATION OF

RCSR58 = 176500

RBUFS58
TCSR58
TBUF58
BGNADD
ENDADD

=
=
=
=
=

176502
176504
176506
DEVADR
ENDADR

RRR AR

A AR AR R

R AR

AR R R AR AR

T/A CONSOLE TEST

3339

3342

2 THIS TEST PUTS COMMANDS OUT OVER THE SERIAL LINE WHICH IS WRAPPED

3345

3 CONTROL P IS SEND TO GET THE CONSOLE'S ATTENTION AND THEN

g%g%

; AND RESTORED AFTER TEST WITH ANOTHER CHECKSUM CALCULATION

g%zg

; MAIN LINE TEST

; AROUND TO THE CONSOLE AND RECEIVES THE RESPONSES

ggzz

3346
3347
3348
3349
3350
3351

3354
3355
3356

; T/A(A FOR APT) IS SENT.
SINCE THE CPU IS HALTED DURING THE TESTING
; THE PROGRAM CAN NOT SEE THE CHARS RETURNING, THUS THE PROGRAM WILL
; SIT IN A LOOP WAITING FOR A 'B'' TO BE PRINTED BY THE CONSOLE AS A
; SIGNAL TO APT THAT THE TESTING IS DONE. ALSO SINCE THE TESTING
; INVOLES WRITTING TO THE CPU'S MEMORY A CHECKSUM IS CALCULATED AND THE
; MEMORY TO BE USED INSIDE THIS PROGRAMS SPACE IS SAVE BEFORE TESTING

:---nnn-ttttttna-ttttttttt'tt.ttntntttttttt.tn.ttttnntttt-t.qtt.tnn-t--n--

3357 013640
%ggg C13646

032777
001451

000004

1€5172

3360 013650
3361 013656
%gg% 013664

013737
012737
012706

177776
000340
002432

002434
177776

3364 013670
%%22 013674

005037
012737

002340
000100

BIT
BEQ

#B1T72,aSWR
10%

sRUN THIS TEST ONLY IF
;SW BIT 2 IS ON

MOV
MOV
MOV

PSW, SAVEPS
#340,PSW
#JIMSTK,SP

;SAVE OLD PSwW
;PUT IN NOW PSW
;USE MY STACK (SO NO CLOBER)

CLR
MOV

LOC1
#100,L0C2

;TIMING LOOP COUNTERS

%%gg 013702

004537

014202

JSR

RS,SAVETE

;SAVE LOCATIONS T/A WRITES

3369 013706
gg;? 013712

004537
010437

014010
002436

JSR
MOV

RS, CHKSUM
R4 ,0LDSUM

;s CALCULATE CHECKSUM
;SAVE OLD CHECKSUM

3372 013716
%g;g 013722

(012700
004537

002564
014030

MOV
JSR

#CNTLP,R)
RS,PUTLIN

;SEND OUT CONTROL P

3375 013726
%g;g 013732

012700
004537

002566
014062

MOV
JSR

#PROMPT ,RO
RS,GETLIN

JGET CRLF CONSOLE>>>

3378 013736
3379 013742

012700
004537

002610
014030

MOV
JSR

#TA RO
RS,PUTLIN

;SEND OUT T/A<CRLF>

002342

WRAP:

[

| CZDLDHO DL11=w 11/44 MFM SLU

MACRO M1113

| TEST # 46 < TEST CONSOLE WITH WRAP AROUND
3381 013746

3382
3383 013752
3384
3385 013756
3386 013762
3387 013766
3388 013770
3389 013772
3390 013776
3391 014004
3392
3393
3394
3395
3396
3397
3398

(07-JuL=-81

15:03

J 7
PAGE 69-1

SEQUENCE

004537

014126

JSR

R5,.GETB

;GET THE A FROM ''-TESTB''

004537

014236

JSR

RS ,RESTTE

JRESTORE LOCATIONS

004537
020437
001401
000000
012706
013737
000137

014010

JSR

RS, CHKSUM

JRECALCULATE

002436
001000
002434
014326

177776

R4 ,OLDSUM

CMP
BEQ
HALT
MOV
MOV
JMP

108:

T/A WRITES

CHECKSUM

108

JRETURN THEIR SP

#1000,SP

SAVEPS ,PSW
$EOP

;RETURN PSW

;BR TO END OF PASS ROUTINE

:!.t"tt'tfittti."t'*t"""'.t..fittt.tt'.t"Qttttt.'tttt"'t"t'.'.'Q."Q

ROUTINE

TO CALCULATE

CHECKSUM ON PROGRAM

INPUT CONDITIONS
BGNADD
ENDADD

ADDRESS TO START CHECK SUM (INCLUSIVE)
ADDRESS TO END CHECK SUM (EXCLUSIVE)

* OUTPUT CONDITIONS

REG4 = CHECK SUM

Ry RRRRRRRRRRRRE
B aa g aaa—
55 NNV
N=OVONOWVNEWN-=O

A AR A A A AR AR A AR AR R AN AR AR R AR R AR R A AR R AR AR AR AR RN PR

014010
014014
014016
014020
014024
014026

RRRRRRRR

5
3426 014030
3427 014032
3428 014034
3429 014040
30 014046

012700
005004
062004
022700
001374
000205

003014
025222

CHKSUM:

MOV

1%:

ADD

AR AR

AR R

;GET STARTING ADDRESS
JRESET SUM
:ADD WORD TO SUM
:CHECK FOR END
;IF NOT DONE LOOP
;DONE RETURN

#BGNADD ,RO

(RO)+,R4
#ENDADD ,RO
1%
RS

:t"ttttttlttt't'ttttt'iit'itQ'filtt't't.ti.'tttitt'tt.'t'fit.tt'tfi"Qtttt'.

THIS ROUTINE

OUTPUTS

TO THE

THE ADDRESS IN REGO UNTIL

SERIAL

LINE

_CHARS

IT HITS A <377>

STARTING AT

AL EES RSS20
2R
AR R0t 222 R
2222022
2222022

112001

PUTLIN:

014162
000200

176504

1%:

176506

014030

10%:

MOVB

BEQ
JSR
BIT
BEQ
MOVB
JMP
RTS

(RO) +,R1
10%
RSiTIMER

#BI1T7,TCSRS8
1%
R1,7TBUF58

PUTLIN

;GET DATA
;END OF DATA
;PROVIDE FOR TIMOUT
sTEST FOR XMIT READY
sWAIT FOR XMIT READY
;OUTPUT CHAR

sREPETE

sRETURN

:"t.t'.".t.'.tt.lt.t't".t't!'t.ttl'"'t'tfifiiti.'.'t'.'t"tt't.t'tt'l.t'

: THIS ROUTINE INPUTS A CHARS FROM THE SERIAL LINF AND COMPARES

|
CZDLDHO DL11=W 11/44 MFM SLU
TEST # 46 = TEST

MACRO M1113

CONSOLE WITH WRAP AROUND

07-JuUL=-81 15:03

K
7
PAGE 69-2

SEQUENCE

%lgg

: IT WITH THE EXPECTED VALUES POINTED TO BY REGO UNTIL NULL<00>

3“0
3441
3442

EQ't.t'tt'tt'tt't"tttit"t"tttt'tQtttQtQQttt't't'.tttttt.ttttt'tt'ttt.tt

3443 014062

112001

3444 014064
3445 014066
3446 014070
3447 014072

105201
001416
105301
004537

3449 014104

001772

3448 014076

3450 0714106

032737

113702

3451 014112

042702

3453 014120

001760

3455 014124
3456
3457

000205

3452 014116
3454 014122

120102

GETLIN:
014162

000200

176500

1%:

176502

MOVR

R1
10%
R1
RS, TIMER

BEQ

BIT

MOVB

000200

10%:

:GET EXPECTED CHAR
:IF NULL EXIT
:PROVIDE FOR TIMOUT

#B1T7,RCSRS8

:TEST FOR REC READY

:WAIT FOR REC READY

RBUF 58,R2

BIC

#BIT7 ,R2

:STRIP PARITY

BEQ

GETLIN

:SAME GET MORE

CMPB

000000

(RO)+,R1

INC3
BEQ
DECB
JSR

HALT
RTS

R1,R2

;

:ARE THEY THE SAME
JNOT SAME HALT

:RLTURN

3‘58

:tttttt'tttttttttttttttttt'tt'tttttttttttttttttfit.tt'ttt'ttttt"tttttttttt

3460

: THIS ROUTIME TNPUTS (HARS UNTIL IT GETS THE CHAR 'B'"’

3463

Ettttt'tttttitttt'tttttt"ttttttt'ttttttttttttttttttttttttttttttttttt"ttt

3459

3322;

: AND THEN RETURNS

3464
3465
3466 014126

004537

3468 014140
3469 014142

001772
113702

3471 014152

122702

3467 014132

3470 014146

3472 014156
332;2 014160

032737

042702
001363

014162

000200

176500

GETB:

JSR

GETB
RBUFS8,R2

:NOT DONE YET

BIC

#BIT7.R2

:STRIP PARITY

GETB

:NOT 'B'' REPETE

000102

CMPB

BNE

RTS

3475

;OUT TIMING LOOP OUT

#BIT7,RCSRS8

176502

000205

RS, TIMER

BIT

BEQ
MOVB

000200

#102 ,R2
RS

:TEST OFR REC READY
.

;CHECK FOR 'B'’

:WAS 'B'' RETURN

:tt'ttt'fittttttttttttttt"ttttttttttttttttttttttttttttttttttttttttt'ttt'tt

3476

34,77
34,78

: THIS ROUTINE IS USED AS A TIME OUT FEATURE
: WHEN THE TIMING LOOPS BOTH REACH 0 THIS ROUTINE WILL

3481
3482
3483
3484 014162

Etttttttttttttt.ttttt'tt'tttttttttttttttttttttttttttttQttttttttttttfitttttt

332;3

; CAUSE A HALT

3487 014174

005337
001004
005337
001001

gzgg 01420C

000205

3485 014166
3486 014170

3488 014176
3491

349?

3493

3494

000000

002340

TIMER:

002342
10%:

DEC
BNE
DEC

BNE

LOC
108
LOC?2
10%

RTS

HALT

;DECREMPNT TIMING LOOPS

:IF ZERO THIS ROUTINE
;EXECUTED R3 TIMES

;ttttttttttttttttttttttttttttttttttttttttIttttt!ttttttt'ttttt'tttt"'t't.t

: THIS ROUTINE SAVES THE LOCATIONS WRITTEN BY THE'T/A CONSOLE TEST

CZDLDHO DL11=W 11/44 MFM SLU

MACRO M1113

TEST # 46 = TEST CONSOLE WITH WRAP AROUND

15:03

L 7
PAGE 69-3

:"ttt"t.t't"'.fi'.!t'Q""Qfi'fifi.'.'.itt"Qt.'t'.'t."'.'.i.'t'.tt.'t""

013737
012702
012701
011221
000241
006102
020227
100772

000000
000002
002346

002344

:
SAVETE
1%:

#2.R2

#SAVLOC ,R1

MOV
MOV

(R2),(R1)+

025222

000205

AAE 2222222222002

THIS ROUTINE RESTORES
AL EEE

013737
012702

002344

000000

RESTTE:

1%:

025222

;SAVE LOCATION 0
sSET-UP INDIRECT PNTER
;SET UP STORAGE LOC. PNTER
;GET WORD AND SAVE

0, SAVED

MOV
MOV

;DONT ROT IN ANY BITS

;SET NEXT ADDRESS
;SEE IF AT END
sNO REPETE

R2
R2 ,#ENDADD
1%
RS
S

014236
014244
3517
3518 014250
3519 014254
3520 014256
3521 014260
3522 014262
3523 014266
3524 014270

SEQUENCE

; SO THEY MAY BE RESTORED LATER

3495
96

3499 014202
3500 014210
3501 014214
3502 014220
3503 014222
3504 014224
3505 014226
3506 014232
3507 014234

07-JuL=-81

SRR

MOV
MOV
MOV
MOV

THE

2222220223222

3222322332

SAVED LOCATIONS THAT T/A WRITES

2222222222222

SAVEQ.0

#2,R2
#SAVLOC ,R1
(R1)+,(R2)

R2
R2 ,#ENDADD
1%
RS

222222

222222222

INTO

222

22220

sSET UP INDIRECT PNTER
;SET UP STORAGE LOC. PNTER
;GET WORD AND RESTORE
;DONT ROT IN ANY B'TS
sSET NEXT ADDRESS

;SEE IF AT END
:NO REPETE

A
CZDLDHO DL11=w 11/44 MFM SLU

MACRO M1113

TEST # 46 = TEST CONSOLE WITH WRAP AROUND

3525
3526 014272
3527 014276
3528 014302
3529 014310
3530 014312
3531 014316
3532 014322

001002
001076
002630

013640
002624
004050

07-JuL-81 15:03

ENDEV:

001076
NOEOP:

M7
PAGE 70

SEQUENCE

;END OF DEV%CE PASS ROUT INE
$TSTNM
;CLEAR TEST NO. COUNT FOR SCOPE ROUTINE
$DEVCT
s INCREMENT DEVICE COUNTER
TMP2, SDEVCT
;ALL DEVICES TESTED

CLR
INC
CMP
BNE
JMP
CLR
JMP

NOEOP
WRAP
CTSTFL

TSTDEV

;BR,

IF NO

;EXECUTE WRAP AROUND AFTER ALL DEVICES
;CLEAR CONSOLE UNDER TEST FLAG
;GO TEST NEXT DEVICE

CZDLDHO DL11=W
| |44 MFM SLU
END OF PASS RQJT!

MACRO M1113

3534

07-JuL-81 15:03

SBTTL
SRR

N 7
PAGE 71

SEQUENCE

END OF PASS RCUTINE

AR AR AR AR AR AR AR A AR AR AR AR RAAA AR AR AN

AAANRAANRARAA AR

'INCREMENT THE PASS NUMBER ($PASS)
;*IF THERES A HONIYOR GO TO IT

014326
014326
014330
014334
014340
014346
014350
014352
014354
014356
014360
014362
014366
014372
014374
014376
014400
014402
014404

3 THERE ISN'T JUMP TO GOAGIN
$eoP
001002
001074

100000

SCOPE

001074

CLR
INC

$STSTAM
$PASS

::ZERO THE TEST NUMBER
INCREMENT THE PASS NUMBER

BGT

$DOAGN

::YES

,ENDMG

::TYPE "END PASS''

BIC
DEC
$EOPCT: .WORD
MOV
$SENDCT: .WORD
S$EOPCT
TYPE

014416

000042

nooooo $PASS
(PC)
1
(PC)+,a(PC)+
1

$GET42: MOV
BEQ

a#62 RO
$DOAGN

$ENDAD:

PC, (RO)

RESET

JSR

NOP

014406
014406
014410
014412

377

000

3535 014416

012

105

$DOAGN:
$RTNAD:

$ENULL:
ENDMG:

::DON'T ALLOW A NEG. NUMBER
::LOOP?
;sRESTORE COUNTER

::GET MONITOK ADDRESS
S:BRANCH IF NO MONITOR
*:CLEAR THE WORLD

::GO TO MONITOR

: :SAVE ROOM
2FOR

NOP

SIACTN

JMP

APC)+

: ;RETURN

.?cgs

-1,-1.,0

JsNULL CHARACTER STRING

.ASCIZ

<CR><LF>/END PASS /

.WORD

GOAGIN

CZDLDHO DL11=W 11/44 MFM SLU

END OF PASS ROUTINE

MACRO M1113

07-JuL-81 15:03

GOAGIN:
1%:

3537 014432
3538 014434
3539 014436
3540 014440
3541 014442
3542 014446
3543 014452
3544 014460
3545 014462
3546 014466
3547
3548 014472
3549 014476
3550
3551 014502
2552 014504
3553 014512
3554 014516

000002
001076
000001

ADD
CLR

002630

CMP
BNE

000002
000002

000002

=(SP)
(SP)

1%
#2,SP
$DEVCT
#1,TMP2

SEQUENCE

;CLEAR ANOTHER LOCATION ON STACK
s INCREMENT STACK LOCATION
:TAKE UP SOME MORE TIME

;BRANCH BACK UNTIL ZERO AGAIN

sCLEAN THE LOCATION OFF THE STACK
sCLEAR DEVICE COUNT
;1S THCRE ONLY ONE DEVICE UNDER TEST?
IF NOT

MOV
JMP

RSTRT
#1000,
SP
TST1

;BR,

RSTRT:

CLR
JMP

SUNIT
BEGIN

;CLEAR UNIT NUMBER

WRPSW:

MOV
MOV
ADD
RTI

(SP) ,=(SP)

:COPY RETURN PC
sMOVE NEW PSW TO STACK
sADJUST JSR RETURN OVER PRIORITY REQUESTED

001000
004172
001100
003774

CLR
INC
NOP
BNE

B 8
PAGE 72

@2(SP) ,2(SP)

#2,(SP)

sRESET STACK POINTER

;GO DO ANOTHER PASS

;POP RETURN PC & NEW PSW

INE TO REPORT UNEXPECTED OR ERRONEOUS TRAPS OR INTERRUPTS
s SUBROUT
3558 014520
3559 014522
3560 014526
3561 014532
3562 014540
3563
3564 014542

012600

162700

010037
016637
104112

000000

000004
002622
000002

CAT(CH:

002620

(SP)+,R0
#4 ,R0

RO,BDVECT
2(SP) ,0LDPC
+112

;GET ADDRESS OF TRAP VECTOR + 4
sADJUST TO POINT TO TRAP ADDRESS
;STORE TRAP OR INTERRUPT ADDRESS
;GET PC WHERE TRAP OR INTERRUPT OCCURRED
;REPORT ERROR
;PROGRAM MUST BE RESTARTED AT

THIS POINT

CZDLDHO DL11=W 11/44 MFM SLU
END OF PASS ROUTINE

MACRO M1113

3566
3567
3568
3569
3570
3571
3572
3573

c.8
PAGE 73

07-JuL=-81 15:03

RRRARA AR

;*THIS ROUTINE WILL

SEQUENCE

AR AR AR RNRRR RN

ARRANRRNANRRNR AR RRRRRAARRRA RS

INCREMENT THE ERROR FLAG AND THE ERROR COUNT,

;*SAVE THE ERROR ITEM NUMBER AND ADDRESS OF THE ERROR CALL
s*AND GO TO SERRTYP ON ERROR

s*THE SWITCH OPTIONS PROVIDED BY THIS ROUTINE ARE:

;*SW15=1
;*SW13=1
:*SW09=1
;*CALL
. %

HALT ON ERROR
INHIBIT ERROR TYPEOUTS
LOOP IN ERROR

ERROR

INCB
BEQ

$ERFLG
7$
$TSTNM,aDISPLAY
S$ERTTL
(SP) ,$ERRPC
#2,$ERRPC
@$ERRPC,$ITEMB

; ;ERROR=EMT AND N=ERROR ITEM NUMBER

::.tt*.t*tt'Qt*ttttttQ""Q"tit.t'l"tfifittttfl't'tt.ttti.'t't..ti

3579 014544
3580 014544
3581 014550
3582 014552
3583 014560
3584 014564
3585 014570
3586 014576
3587 014604
3588 014612
3589 014614
3590 014620
3591 014624
3592 014624
3593 014632
3594 014634
3595 014642
3596 014646
3597 014647
3598 014650
3599 014652

105237

001775

$ERROR:
7%:

001003
001002
001012

020000

164262

164226

000001

001106

001014
015714

014646

022737
001001
000000
000002

164146

000042

PC,$ERRTYP

.SCRLF

$ITEMB,21$%

PC,$ATY4

0
0
22%

6%:

HALT
RTI

s INCREMENT ERROR COUNT
:GET ADDRESS OF ERROR INSTRUCTION

;STRIP AND SAVE THE ERROR ITEM CODE

sSKIP TYPEOUT IF SET

:SKIP TYPEOUTS
;GO TO USER ERROR ROUTINE
JRUNNING

IN APT MODE

sNO, SKIP APT ERROR REPORT
;SET ITEM NUMBER AS ERROR NUMBER
;REPORT FATAL ERROR TO APT

#SEND
, a#42
AD

;ACT=11

#BI1T09,aSWR

5%:

*DISPLAY TEST NUMBER AND ERROR FLAG

$LPERR, (SP)
$ESCAPE
5%
$ESCAPE, (SP)

3%:

;:DON'T LET FLAG GO TO ZERO

;APT ERROR LOOP
sHALT ON ERROR
;SKIP IF CONTINUE
;HALT ON ERROR!
;TEST FOR CHANGE IN SOF T-SWR
;LOOP ON ERROR SWITCH SET?
:BR IF NO
;FUDGE RETURN FOR LOOPING
;CHECK FOR AN ESCAPE ADDRESS
;BR IF NONE
;FUDGE RETURN ADDRESS FOR ESCAPE

aSWR

4%:

001060

#BIT13,aSWR
208

zAPTENV.SENV
$

22%:
2%:

001010
001060

014376

c0%:

MOV
SuB
MOVB
BIT
BNE
JSR
TYPE

21%:

164162

001402
013716

INC

001016
001014

014726
001063

001000

MOV

;SET THE ERROR FLAG

AUTO-ACCEPT?

;BR IF NO
;YES
;RETURN

CZDLDHO DL11=W 11/44 MFM SLU

END OF

PASS ROUTINE

MACRO M1113

3617
3618

07-JuL-81

.SBTTL
IR

15:03

D 8
PAGE 74

SEQUENCE

ERROR MESSAGE TYPEOUT ROUTINE
RRRARRAR AR AR AR AR AR AR RR

AR RRARRRRRRRRRRRARRRRRRREARRRRA
AR

;*THIS ROUTINE USES THE ''ITEM CONTROL BYTE'' (SITEMB)

TO DETERMINE WHICH

;*ERROR IS TO BE REPORTED. IT THEN OBTAINS, FROM THE 'ERROR TABLE'' ($ERRTB),
;*AND REPORTS THE APPROPRIATE INFORMATION CONCERNING THE ERROR.
014726
014726
014732
014734
014736

104401

001063

010046
005000

014742

001004

153700

001014

014744

013746

001016

0147250
014752
014754
014760
014762
014766
014770
014772
014774
014776
015000
015004
015010
015012
015014
015016
015022
015026
015030

$ERRTYP:

000177

:SAVE RO
::PICKUP THE ITEM INDEX

MOV

$ERRPC,~(SP)

;sSAVE $ERRPC FOR TYPEOUT
. sERROR ADDRESS
;:G0 TYPE=--OCTAL ASCIICALL DIGITS)
;sGET OuT
;1S THIS THE POWER MONITOR BIT CALL

1%:

015076
100%:

001146
015014
000000
104401

12037
001404
104401

000000
104401
011000
001004
012600
104401

001063

005710
001770
104401

(RO)+,4%
5%

4%:

5%:

(RO) ,RO
7$
(SP)+,R0

.SCRLF

. SCRLF

000771
040

::PICKUP 'ERROR MESSAGE'' POINTER
;:SKIP TYPEOUT IF NC POINTER
;:TYPE THE 'ERROR MESSAGE''
::"ERROR MESSAGE'' ?OINTER GOES HERE
;2"'CARRIAGE RETURN'' & 'LINE FEED''
::PICKUP 'DATA HEADER'' POINTER
;:SKIP TYPEOUT IF 0
::TYPE THE 'DATA HEADER''

::'DATA HEADER'' POINTER GOES HERE
;:"'CARRIAGE RETURN'' & "LINE FEED''
;:PICKUP 'DATA TABLE'' POINTER
;G0 TYPE THE DATA
:;RESTORE RO

:2"'CARRIAGE RETURN'' & "LINE FEED''

2 JRETURN

a(R0O)+,-(SP)

::SAVE @(RO)+ FOR TYPEOUT
::G0 TYPE--OCTAL ASCIICALL DIGITS)
..IS THERE ANOTHER NUMBER?

o8
7$

:BR _IF NO
,,TYPE TWO(2) SPACES
.LOOP

040

000
015176
127
123

PFECDH:

?POWER MONITOR BIT WAS FOUND SET?
?TESTNO
ERR PC
CPUERR?

015674

PFECDT:

$TESTN,SERRPC, CPSAVE,OQ

015076
015106
015146

015106
124

015146
117
105

015176

007072

001016

120

::ADJUST THE INDEX SO THAT IT WILL
‘e
WORK FOR THE ERROR TABLE

(RO)

015072

::TWO(2) SPACES

8%:

PFECWS:

PFECEM,PFECDH,
PFECDT ,PFECDF

PFECEM: .

DPM001

;:FORM TABLE POINTER

3%:

104402

THE ERROR

R
#$ERRTB,RO

7%:

013046

;c.TYPE THE PC OF

1108

2%:

6%:

;:IF ITEM NUMBER IS ZERO, JUST

:BRANCH IF NOT
; DPMOO1
:MOVE ADDRS OF PWR MUNITOR BIT ERR TO RO:DPMOO1
;BRANCH TO CALL THE ERROR
:DPMOO1

(RO)+,2%
3%

110%:

001063
015032

:.'TARRIAGE RETURN'' & "LINE FEED'’

RO,=(SP)
RO
A#$ITEMB,RO
1%

104402

000434

000207

015072

.SCRLF

T/PE
MOV
CLR
BISB
BNE

CZDLDHO DL11=w 11/44 MFM SLU

ERROR MESSAGE TYPEOUT ROUTINE

%19 015206

00C

000

MACRO M1113 07-JUL-81 15:03 PAGE ;4-1
000

PFECDF:

.BYTE

0,0,0,0

SEQUENCE

——y

[

| CZDLDHO DLT1T1=W 11744 MFM SLU

| FRROR MESSAGE TYPEOUT ROUTINE
|

L
g

MACRO M1113

3621

3622

07-JuUL=81 15:03

.SBTTL

F 8

PAGE 75

SEQUENCE

POWER DOWN AND UP ROUTINES

3623

.'"tl""t'i.Q."'.Ql"..""..'...."Q'...t.'.'.t.".."..."""'

3625

:.'""'!".‘.'..t"'...."'.fi.'."..'Q.Q."'fi'Q.Q".Q".".'.'.Qt

3624

3606 015212
3627 015020
3628 015226
3629 015230
3630 015232
3631 015234
3632 015236
3633 015240

3634 015242
3635 015246
2636 015252
3637 015260
3638 015262
3639
3640

;*POWER DOWN ROUTINE

012737
012737
010046
010146
010246
010346

010446
010546
017746
010637
012737
000000
000776

015356
000340

163572
015362
015264

000024
000026

MOV
MOV
MOV
MOV
MOV
HALT
BR

000024

3641

ASILLUP,@#PWRVEC ;SET FOR FAST UP
#340,@#PWRVEC+ ;PRIO:;
RO.=(SP)
*PUSH RO ON STACK
R1.=(SP)
:PUSH R1 ON STACK
R2.=(SP)
:PUSH R2 ON STACK
R3.=(SP)
:PUSH R3 ON STACK
R&.=(SP)
*PUSH
RS.=(SP)
*PUSH
ASWR, = (SP)
*PUSH
SP,$SAVR6
SAVE
#$PWRUP ,@#PWRVEC ;SET
=2

R4 ON STACK
RS ON STACK
@SWR ON STACK
SP
UP VECTOR

;HANG UP

:"ltt't"QQt.t..'t**t""""".t.t"".fi""'fi"".t"'fi.ttt."'

3642

:*POWER UP ROUTINE

%43

> I 2222232323232 2223233232323232323232232322323223232222222222222223222

3644 015264
3645 015272
3646 015276
3647 015302

012737
013706
012677
012605

3649 015306
3650 015310
3651 015312
3652 015314
3653 015316
3654 015324
3655 015332
3656 015336
3657 015342

012603
012602
012601
012600
012737
012737
005037
005237
001375

015356
015362
163536

000024

3648 015304 012604

3658 015344
3659 015346
3660 015350
3661 015354
3662 015356
3663 015260
3664 015362
3665 015364

$PWRDN: MOV
MOV
MOV
MOV
MOV
MOV

104401
015364
013716
000002
000000
000776
000000
015

$PWRUP: MOV
MOV
MOV
MOV

MOV

015212
000340
015362
015362

000024
000026
18:

012

TYPE
.WORD
MOV
RTI
$ILLUP: HALT
BR
$SAVRG: 0
$POWER: .ASCIZ

$PWRMG:

001006

120

MOV
MOV
MOV
MOV
MOV
MOV
CLR
INC
BNE

222222222 2 24

#SILLUP,@#PWRVEC ;SET FOR FAST DOWN
$SAVRG, SP
;GET SP
(SP)+,aSWR
:POP STACK INTO @SwR
(SP)+.RS

(SP)+.Ré&

:POP STACK INTO Ré4

(SP)+.R3
:POP STACK INTO R3
(SP)+.R2
1POP STACK INTO R2
(SP)+.R1
:POP STACK INTO R1
(SP)+.RO
*POP STACK INTO RO
ASPWRDN,a#PWRVEC ;SET UP THE POWER DOWN VECTOR
4340, @#PWRVEC+2 :PRIO:7
$SAVRG
*WAIT LOOP FOR THE TTY
$SAVRE
:WAIT FOR THE INC
13
:OF WORD
SPOWER
$LPADR, (SP)
=2

<15><12>'POMER'’

:REPORT THE POWER FAILURE
POWER FAIL MESSAGE POINTER
:CHOCOLATE FUDGE RETURN TO BEGINNING OF
RETURN TO THERE
:THE POWER UP SEQUENCE WAS STARTED
: BEFORE THE POWER DOWN WAS COMPLETE
:PUT THE SP HERE

TEST

————————————

| CZDLDHO DL11=w 11/44 MFM SLU

| POWER DOWN AND UP ROUTINES

MACRO M1113

3668

3669

——————————

07-JuL=-81 15:03

.SBTTL

PAGE 76

SEQUENCE

SCOPE HANDLER ROUTINE

".'Q'Qtt'.Qtttttttt"tt"t't'ttt.itttt'tQQt't'tt'tttt".t.t'."t'.

:*THIS ROUTINE CONTROLS THE LOOPING OF

SUBTESTS.

IT WILL

INCREMENT

:*AND LOAD THE TEST NUMBER(STSTNM) INTO THE DISPLAY REG.(DISPLAY<7:0>)
:«AND LOAD THE ERROR FLAG (SERFLG) INTO DISPLAY<15:08>
:*THE

SWITCH OPTIONS PROVIDED BY

seSWi4=1

LOOP ON TEST

LOOP ON ERROR

:*SW09=1
s*CALL

015374
015374
015376
015404

104406
032777
001125

015406

000416

015410
015414

013746
012737

000004
01543&

015426

012637

000004

022626
012637
000462

000004

015422

015432

015434
015436
015442
015444
015444
015452
015454

015460

015462

015466
015474
015502
015510
015512
015520

015524

005737
000474

$SCOPE:
040000

177060

013746

000004

013737
032737
001423
042737
017746

042777

000004

015674

177777

015542

177766
000001

015674
015674

000001
163314

177766

001000

900%$:

163306

015560

005227

177777

20008:

012637
105737
001412
032777
001404
013737
000420

000004
001003

9108:
2001%:

015564

015566
015572
015576
015600
015606
015610
015616

000403

001002

001000

163232

001010

001006

FOR

THE

XOR

MOV

(SP)+,a#ERRVEC

4177060

TESTERA##AA

::1F RUNNING ON THE ‘XOR'' TESTER CHANGE

::THIS INSTRUCTION TO A 'NOP'' (NOP=240)
;:SAVE THE CONTENTS OF
::SET FOR TIMEOUT

THE ERROR VECTOR

::TIME OUT ON XOR?

;:RESTORE THE ERROR VECTOR

$SVLAD

::GO TO THE NEXT TEST

900%

*BRANCH IF NOT

:DPMOO1

#19998% .4

:SET VECTOR TO LOCATION BELOW

:DPMO01

MOV

4,~(SP)

MOV
BIT
BEQ
BIC
MOV

177766,CPSAVE
#B1T00,CPSAVE
2000%
#81T00,177766
asSwR, - (SP)

:MOVE CPU ERR REG VALUE TO LOC FOR TST
:SEE IF THE POWER MONITOR BIT IS ON
:BRANCH TO CONTINUE ROUTINE IF CLEAR
:CLEAR THE BIT FOUND TO BE SET
:SAVE SWR VALUE

:DPMOO1
:DPMO01
:DPMOO1
:DPMOO1
:DPMOO1

+177
(SP)+,aSWR
2000%
(SP)+,(SP)+
#-1,CPSAVE
20008+2

:CALL SPECIAL POWER FAIL BIT ERROR CALL
;RESTORE SWR TO ORIGINAL VALUE
:BRANCH OVER TIMEOUT SECTION
:CLEAN UP THE STACK AFTER TIMEOUT
:MOVE -1 TO (PSAVE - NO CPU ERR REG
:INCREMENT 1ST TIME THROUGH LOCATION

;DPMOO1
:DPMOO1
:DPMOO1
:DPMO01
:DPM0O1
:DPMOO1

#=-1

:TEST FOR 1ST TIME THROUGH

:DPMOO1

MOV

BIC

163300
015674

CODE

;:TEST
FOR CHANGE IN SOF T=SWR
::LOOP ON PRESENT TEST?
::YES IF SW14=1

CMP
(SP)+,(SP)+
::CLEAR THE STACK AFTER A TIME OUT
MOV
(SP)+,@#ERRVEC
;:RESTORE THE ERROR VECTOR
BR
7%
::LOOP ON THE PRESENT TEST
6$: ; ###AREND OF CODE FOR THE XOR TESTERAAA#H
2%:
CMP
#-1,CPSAVE
:SEE IF TIMEOUT WAS PREVIOUSLY RECORDED ;DPMOO1
BEQ
2001$
*BRANCH AROUND ROUTINE IF SO
*DPMOO1
INC
#-1
:TEST FOR 1ST TIME THROUGH
:DPMOO1

104177
012677
000407
022626
012737
005237

177777
015562

#31T14,aSWR
$OVER

QHERRVEC,-(SP)
#5$ , S4ERRVEC

BNE

000004

::SCOPE=]0T

MOV
MOV

015532
015534
015540
015542
015544
015552

015556

CKSWR
BIT
BNE

$XTSTR: BR

177777

012737

1$:

SCOPE

;MBsaRSTART OF

022737
001447
005227

001005

163434

THIS ROUTINE ARE:

19998:

7%:

EMT
MOV
BR
CMP
MOV
INC
BR

INC

BNE

MOV
TSTB
BEQ
BIT
BEQ
MOV
BR

#81709,35WR

910%

2001$

(SP)+,4
$ERFLG
$SVLAD
#81709,aSWR
48
$LPERR, $LPADR
$OVER

:SAVE TIMEOUT VECTOR AT 4

:DPMO01

:DON'T ALLOW LOOP ON ERROR ON THIS ERROR:DPMOO1

:BRANCH OVER 1ST TIME THROUGH TEST

:BRANCH IF NOT

;RESTORE LOCATION 4
::HAS AN ERROR OCCURRED?
::BR IF NO
:LOOP ON ERROR?
s IF NO
..SET LOOP ADDRESS TO LAST SCOPE

:DPMOO1

:DPMO01
:DPMO01

—_——

| CZDLDMO DL11=W 11744 MFM SLU
| SCOPE HANDLER ROUT INE
|

015620
015624
015630
015636
015642
015646
015652
015660
015666
015672
3670

015674

MACRO M1113

001003
001006
001010

001072

07-JuL=-81 15:03

A ¥
$SVLAD:

CLRB
INCB
mMovBe
MOV
MOV

001015
163154

CLR

MCVB
$OVER:
MOV
MOV
RTI
:
CPSAVE .WORD

H 8
PAGE 76-1

;:ZERO_THE ERROR FLAG
;s COUNT TEST NUMBERS
s:SET TEST NUMBER''IN APT MAILBOX
;:SAVE SCOPE LOOP ADDRESS
;s SAVE ERROR LOOP ADDRESS
;;CLEAR THE ESCAPE FROM ERROR ADDRESS
#1,3ERMAX
2;ONLY ALLOW ONE(1) ERROR ON NEXT TEST
Y
$TSTNM,aDISPLA
;;DISPLAY TEST NUMBER
$LPADR, (SP)
;;FUDGE RETURN ADDRESS
;;FIXES PS
0
;LOCATION TO SAVE (PU ERR REG CONTENTS

SEQUENCE

$SERFLG
$TSTNM
STSTNM, STESTN
(SP) ,$LPADR
(SP) ,$LPERR
$ESCAPE

:DPMOO1

[res———

——————————

—

e———————

CZDLDHO DL11=w 11/44 MFM SLU
' SCOPE HANDLER ROUT INE

MACRO M1113

07-JuL-81 15:03

1_8

PAGE 77

SEQUENCE

3“67%

.'.'".'Q".".'.".'..""""".".'.'...'...""'."".Q.."' [ 3

%75

.'.'."'.'..'Q...'....".""."'.'Q'."t.t."."Q....."""'Q.".

3674

"SBTTL

376

3677 015676 112737 000001

379 015712 000403

3678 0157064

112737

000001

3680 0157164
3681 015722
3682 015722
3683 015704
3684 015726
3685 015732
3686 015734
2687 015742
3688 015744
3689 015752
3690 015754
3691 015760
3692 015766
3693 015772
369, 015774
3695 016000
3696 016002

112737

000001

010046
010146
105737
001450
122737
001031
132737
001425
017600
062766
005737
001375
010037
105720
001376

3698 016010
3699 016012
3700 016016
3701 016024
3702 016026
3703 016034

006200
010037
012737
000413
017637
062766

3705 016046

004737

3706 016052 000000

016144

3707 016054
3708 016054
3709 016060
3710 016062
3711 016066
3712 016070
3713 015074
3714 016076
3715 016104
3716 016110
3717 016116
3718 016122
3719 016126
3720 016132
3721 016134
3722 016136
3723 016140
3724 016141
g;gz 016142

105737
001413
005737
001410
005737
001375
017637
005237
062766
105037
105037
105037
012601
012600
000207
000
000
000

016142

3707
3728

000200

016142 $ATY1:
016140

$ATY3:

016142

$ATY4:
SATYC:

016740
000001

001106

000100

001107

000004
000002
001066

000004

001102

18:
2%:

3697 016004 163700 001102

3704 016042

013746

001066

000004
000002

016052
000004

38:

#1,8FFLG

#71.SMFLG

$ATYC

#1,$FFLG

:TO ONLY REPORT FATAL ERROR

MOV
MOV
TSTB
BEQ
CMPB
BNE
BITB
BEQ
MOV
ADD
TST
BNE
MOV
1STB
BNE

RO, =(SP)
R1.=(SP)
SMFLG
5%
WAPTENV.SENV
3%
WAPTSPOOL,SENVM
3
34 (SP) RO
#2.4(SP)
$MSGTYPE
1%
RO, SMSGAD
(RO)+
28

:PUSH RO ON STACK
*PUSH R1 ON STACK
“SHOULD TYPE A MESSAGE?
*1F NOT: BR
-OPERATING UNDER APT?
*IF NOT: BR
:SHOULD SPOOL MESSAGE?
*1F NOT: BR
*GET MESSAGE ADDRESS
BUMP RETURN ADDRESS
-SEE IF DONE W/ LAST XMISSION?
SIF NOT: WAIT
*PUT ADDRESS IN MAILBOX
“FIND END OF MESSAGE

ASR
MOV
MOV
BR
MOV
ADD

RO
RO, SMSGLGT
#4 . SMSGTYPE
5%
24 (SP) .48
#2.4(SP)

*GET MESSAGE LENGTH IN WORDS
“PUT LENGTH IN MAILBOX
“TELL APT TO TAKE MESSAGE

JSR

WORD

PC,$TYPE

;CALL TYPE MACRO

TSTB
BEQ
TST
BEQ
T1ST
BNE
MOV
INC
ADD
CLRB
CLRB
CLRB
MOV
MOV
RTS
.BYTE
.BYTE
.BYTE

S$FFLG
128
$ENV
128
$MSGTYPE
1%
34 (SP) ,$FATAL
$MSGTYPE
#2.4(SP)
S$FFLG
SLFLG
SMFLG
(SP)+,R1
(SP)+,R0
PC
0
0
0

:SHOULD REPCRT FATAL ERROR?
“1F NOT: BR
JRUNNING UNDER APT?
*IF NOT: BR
*FINISHED LAST MESSAGE?
“IF NOT: WAIT
:GET ERROR #
;TELL APT TO TAKE ERROR
BUMP RETURN ADDRESS
"CLEAR FATAL FLAG
*CLEAR LOG FLAG
*CLEAR MESSAGE FLAG
*POP STACK INTO R1
;POP STACK INTO R1
“RETURN

MOVB
MOVB

MOV

4$:

5
108:

001106
001066

000004
001066
000002
016142
016141
016140

MOVB

SUB

001104
000004

177776

APT COMMUNICATIONS ROUTINE

11%:

001070
000004

12%:

SMFLG:
SLFLG:
$FFLG:

.EVEN

APT51ZE=200

$MSGAD , RO

179776.=(SP)

;TO REPORT FATAL ERROR
70 TYPE A MESSAGE

-SUB START OF MESSAGE

:PUT MSG ADDR IN JSR LINKAGE
BUMP RETURN ADDRESS

:-PUSH 177776 ON STACK

:L0G FLAG
"FATAL FLAG

CZDLDHO DL11=w 11/44 MFM SLU
APT

COMMUNICATIONS ROUTINE

3729
3730
7N
3732

000001
000100
000040

MACRO M1113

07-JuL=81 15:03

APTENV=001
APTSPOOL =100
APTCSUP=040

J_8
PAGE 77<1

SEQUENCE

100

K 8
PAGE 78

(ZDLDHO DL11=W 11/44 MFM SLU
APT

COMMUNICATIONS ROUTINE

MACRO M1113

3734

07-JuL-81 15:03

.SBTTL

3735

TYPE ROUTINE

IRRRRRRARRRRRAR AR

AN AR

SEQUENCE

ARR AR

RN RAR AR AR

RRRRRARRRRRA

s*ROUTINE TO TYPE ASCIZ MESSAGE. MESSAGE MUST TERMINATE WITH A O BYTE.
;*THE ROUTINE WILL INSERT A NUMBER OF NULL CHARACTERS AFTER A LINE FEED.
SNULL CONTAINS THE CHARACTER TO BE USED AS THE FILLER CHARACTER.
:*NOTE1:
$FILLS CONTAINS THE NUMBER OF FILLER CHARACTERS REQUIRED.
:*NOTE2:
$FILLC CONTAINS THE CHARACTER TO FILL AFTER.
:*NOTE3:
v

s*CALL

i) USING A TRAP INSTRUCTION
;*

:*OR
*

016144
016150
016152
016154
016156
016160
016164
016172
016174
016202
016204
016210
016214
016216
016224

105737
100002
000000

000002
000001

001106

000100

001107

015704
000040

;:MESADR IS FIRST ADDRESS OF AN ASCIZ STRING

$TPFLG
1%

;:1S THERE A TERMINAL?
::BR IF YES

TYPE

TSTB

BPL
HALT

;;HALT HERE IF NO TERMINAL

;s LEAVE
::SAVE RO
@2(SP) ,RO
:2GET ADDRESS OF ASCIZ STRING
#AfiTENV.SENV
;JRUNNING IN APT MODE
62
:3NO,GO CHECK FOR APT CONSOLE
#APTSPOOL
, SENVM 2 :SPOOL MESSAGE TO APT
62%
:2NO,GO CHECK FOR CONSOLE
RO,61%
;:SETUP MESSAGE ADDRESS FOR APT
SC.SATYS
;:SPOOL MESSAGE TO APT
; sMESSAGE ADDRESS
#APTCSUP, SENVM
s sAPT CONSOLE SUPPRESSED
60%
::YES,SKIP TYPE OUT
3%

RO,=(SP)

1%:

MoV

61%:
62%:

.WORD

2%:

MOVB

60%:
3%:

ADD

(RO)+,-(SP)
4%
(SP)+
(SP)+ ,R0O

#2,(SP)

;;PUSH CHARACTER TO BE TYPED ONTO STACK
:2BR IF IT ISN'T THE TERMINATOR
::IF TERMINATOR POP IT OFF THE STACK
:;RESTORE RO
:2ADJUST RETURN PC

000011

#HT, (SP)

sRETURN
2
;JBRANCH IF <HT>

000200

#CRLF, (SP)

; ;BRANCH IF NOT <CRLF>

5%
+
(SP)

016504

$CHARCNT

016356
001056

PC,$TYPEC
$FILLC,(SP)+

013746

001054

105366

000001

002770
004737
105337
000770

001107

.MESADR

ME SADR

016214

000002

016312
016316
016320
016324
016330

$TYPE:

001057

TYPE

016356
016504

6$:
7%:

CMPB
DECB
DECB

JHORIZONTAL

2%
$NULL ,=(SP)
1(SP)

PC,$TYPEC
$CHARCNT

TAB PROCESSOR

;:POP <CR><LF> EQUIV
;:TYPE A CR AND LF
;s CLEAR CHARACTER COUNT
::GET NEXT CHARACTER
;GO TYPE THIS CHARACTER
..IS IT TIME FOR FILLER CHARS.?
:1F NO GO GET NEXT CHAR.

:GET # OF FILLER CHARS. NEEDED

..AND THE NULL CHAR.

;DOES A NULL NEED TO BE TYPED?
::BR IF NO--GO POP THE NULL OFF OF STACK
2:G0 TYPE A NULL
::DO NOT COUNT AS A COUNT
::LOOP

101

CZDLDHO DL11=W 11/44 MFM SLU
TYPE ROUTINE

016332

11271¢€

000040
016356
000007

105777

162462

017746
042716

162456
177600

100022

122716
001012

000023

105777
100375
117716

162436

042716
122716

001366

MACRO M1113
8%:

016504

001420

9%:

$TYPEC:

MOVB
JSR
BITB
BNE
TST
B

162432
177600
000021
102%:

10%:

162414

000015

016504
000002

1%:

CMPB
BEQ

INCB
$CHARCNT
: . WORD
$TYPEX: RTS

3736

a$TKS
108
a$TKB,~(SP)
#177600, (SP)

;;CHAR IN KYBD BUFFER?
F:BR IF NOT
::GET CHAR
::STRIP EXTRANEOUS BITS
:JWAS CHAR XOFF

SBTTL
A2

;:BR IF NOT

a$TKS
101$
a$TKB, (SP)
#177600, (SP)
#$XON, (SP)
1018

;:WAIT FOR CHAR

(SP)+

J:FIX STACK

a$TPS
108

;:WAIT UNTIL PRINTER IS READY

2(SP) ,a$TPB

000002

000012

s ;REPLACE TAB WITH SPACE
;:TYPE A SPACE
;sBRANCH IF NOT AT
;. TAB STOP
;.POP SPACE OFF STACK
;2GET NEXT CHARACTER

$TYPEX

162376

000002

SEQUENCE

#' ,(SP)
PC,STYPEC
#7 ,$CHARCNT
9%
(SP)+

2(SP) ,#$XON

000021

000002

L 8
PAGE 78-1

#SXOFF
, (SP)
102%

101¢:

005726
105777
100375
126627

07-JuL-81 15:03

#CR,2(SP)
1%
$CHARCNT
$TYPEX
#LF ,2(SP)
$1YPEX
(PC)+

;:GET CHAR
J:STRIP IT
JsWAS IT XON?
;:BR IF NOT

;1S CHARACTER A RANDOM XON?
: ;BRANCH IF YES
;;LOAD CHAR TO BE TYPED INTO DATA REG.
::1S CHARACTER A CARRIAGE RETURN?
s sBRANCH IF NO
::g;?;—CLEAR CHARACTER COUNT

HJDOO1

;MJDOO1

s RANQO1
*RANOO1

::1S CHARACTER A LINE FEED?
:;BRANCH IF YES
;;COUNT THE CHARACTER
;sCHARACTER COUNT STORAGE

BINARY TO OCTAL (ASCII) AND TYPE

i32222223222222t
2222
Rt ddRRRR R R d ]

:*THIS ROUTINE IS USED TO CHANGE A 16-BIT BINARY NUMBER TO A 6-DIGIT
:#OCTAL (ASCII) NUMBER AND TYPE IT
:«$TYPOS---ENTER HERE TO SETUP SUPPRESS ZEROS AND NUMBER OF DIGITS TO TYPE

'CALL
MOV
:'
%
TYPOS

ze
3%

N
M

*
»

NN,

‘t

.BYTE
BYTE

,
- (SP)
NUM

;;NUMBER TO BE TYPED
;;CALL FOR TYPEOUT
;:N=1 TO 6 FOR NUMBER OF DIGITS TO TYPE
:2M=1 0R 0
::1=TYPE LEADING ZEROS
::0=SUPPRESS LEADING ZEROS

*$TYPON----ENTER HERE TO TYPE OUT WITH THE SAME PARAMETERS AS THE LAST

;*$TYPOS OR $TYPOC

s*CALL:
o
MOV
I *
TYPON
. %

(SP}
NU-M,

;:NUMBER TO BE TYPED
::CALL FOR TYPEOUT

L «$TYPOC---ENTER HERE FOR TYPEOUT OF A 16 BIT NUMBER

102

CZDLDHO DL11=W 11/44 MFM SLU
BINARY TO OCTAL (ASCII) AND TYPE

MACRO M1113

07-JuL-81 15:03

:*CALL:

016510
016514
016522

“x

000001

016733

000001
€ 70006
000005

016733
016735
016732

016735
000002

MOV

TYPOC

$TYPOS: MOV

MOVB
MOVB
ADD
BR
$TYPOC: MOVB
MOVB
S$TYPON: MOVB
MOV
MOV

MOV
MOVB

016735
000006

016734
016733
000012
1%:

016734

MOV
ROL

016732

7%:

6$:
000002

000004
8%:

3737

ROL
ROL

DECB
BPL

$OCNT:
$OFILL:
$OMODE:

BNE
ST
BEQ
INC

BIS
BIS
MOVB

TYPE
DECB
BGT

:sNUMBER TO BE TYPED
;s CALL FOR TYPEOUT
; ;PICKUP THE MODE
;:LOAD ZERO FILL SWITCH
; sNUMBER OF DIGITS TO TYPE
s sADJUST RETURN ADDRESS

RS,~(SP)
$OMODE+1.Ré4

12(SP) .RS
R3

;sSUBTRACT IT FOR MAX. ALLOWED
;sSAVE IT FOR USE
;sGET THE ZERO FILL SWITCH
;sPICKUP THE INPUT NUMBER
;sCLEAR THE OUTPUT WORD

33
RS

::G0 DO MSB
;sFORM THIS DIGIT

R&,=(SP)

R5
RS

R5,R3
R3

$OMODE
7%

#177770.R3
R4
5%
R

#'0,R3
#' .R3
R3,8%
,8%
$OCNT
$

BLT
INC
BR
MOV
MOV
MOV
MOV
MOV

6%
R4
2$
(SP)+,RS
(SP)+.R&4
(SP)+.R3
2(SP)
.4 (SP)
(SP)+. (SP)

.BYTE

.BYTE
.BYTE
.WORD

0
0
0

RTI

SEQUENCE

;:SET THE ZERO FILL SWITCH
;:SET FOR SIX(6) DIGITS
;:SET THE ITERATION COUNT
;:SAVE R3
::SAVE R4
:.SAVE RS
:2GET THE NUMBER OF DIGITS TO TYPE

3%:

1(SP).SOFILL
(SP)+.SOMODE+1
#2, (SP)
$TYPON
#1,80FILL
#6.SOMODE
+1
#5.SOCNT
R3,=(SP)

ROL

MOV
CLR
BR
ROL

4%:

(SP) ,=(SP)

R4
#6 R4
R&.SOMODE
SOFILL.R&

BIC

000060
000040
01673C
016730

= (SP)
NUM,

NEG
ADD
MOVB
MOVB

!
2$

177770

m 8
PAGE 78-2

;;ROTATE MSB INTO 'C"'

;:GET LSB OF THIS DIGIT
;2:TYPE

THIS DIGIT?

;:BR IF NO

;2GET RID OF JUNK
;2TEST FOR O
; :SUPPRESS THIS 0?
;:BR IF YES

;:DON'T SUPPRESS ANYMORE 0°'S

;sMAKE THIS DIGIT ASCII
;sMAKE ASCII IF NOT ALREADY
;2SAVE FOR TYPING
;:G0 TYPE THIS DIGIT
;2COUNT BY 1
;:BR IF MORE TO DO
;:BR IF DONE

;s INSURE LAST DIGIT ISN'T A BLANK
;:G0 DO THE LAST DIGIT
:;RESTORE RS
;sRESTORE R4
:2RESTORE R3
;:SET THE STACK FOR RETURNING
2 sRETURN

;2STORAGE FOR ASCII DIGIT
;:TERMINATOR FOR TYPE ROUTINE
;sOCTAL DIGIT COUNTER
;:ZERO FILL SWITCH
;sNUMBER OF DIGITS TO TYPE

103

CZDLDHO DL11=w 11/44 MFM SLU

BINARY TO OCTAL

(ASCII) AND TYPE

MACRO M1113

3739
3740

07-JuL-81 15:03

N 8
PAGE 79

.SBTTL

TTY INPUT ROUTINE

.ENABL

LSB

SEQUENCE

t'.fi'tt'.'.‘."...*".""'..'.'."...."....'."Q"'.."'Q'Q..

tttt.t'ttt".ll..Q""'t".t'."..'.'.QQ.".Q..'.Q..t.."""..

;*SOF TWARE SWITCH REGISTER CHANGE ROUTINE.

s*ROUTINE

IS ENTERED FROM THE

;*SERVICE THE TEST FOR CHANGE

016736

022737

000176

001040

BNE

TSTB

BPL
MOVB

162066
177600
000007

BIC

000001

017473
017500
000176
01751
162010

737

016356
000060
000067

000060
000002

.SCNTLG

BIC
CMP

#-C177.(SP)
(SP) 425

108:

161706

15%

TYPE

SAUTOB,#1

-(SP)
=(SP)
a$TKS

000015

000100

BEQ

CLR
CLR
TSTB

208:

012777

#-C177.,(SP)

#7.(SP)+
15$

19%:

000004

017130
017136
017140

15%
@$TKB,=(SP)

. SMSWR
SWREG,~-(SP)

017466
000006

000001

asrxs

TYPE
MOV
TYPOC

98 :

161730

15%

$GTSWR:

162004

000002
000006
001063
001035

#SWREG, SWR

CMP
BNE

CMPB

7$:

177600
000025

AND WILL

IN SOF TWARE SWITCH REGISTER TRAP CALL

: *WHEN OPERATING IN TTY FLAG MODE.

$CKSWR: CMP

162072

001034

TRAP HANDLER,

118:
14%:

16%

TYPE

BPL
MOVB
BNE

TYPE

. SMNEW

7$
@$TKB,=-(SP)
108

LSCNTLU

ADD
BR

#6,SP
19%

TST

4 (SP)

CMP
BNE

BEQ
MOV

ADD
TYPE

CMPB

(SP) ,#15
16%

11$
2(SP) ,aSWR
#6,SP
. SCRLF

SINTAG al

BNE
MOV

15%
#100,3$7TKS

JSR

PC,STYPEC

RTI

CMP
BLT
CMP
BGT
8IC

(SP) ,#60
18%
(SP) ,#67
18%
#60, (SP) +

BEQ

17%

TST

ASL
ASL
ASL

2(SP)
(SP)
(SP)
(SP)

;:1S THE SOFT-SWR SELECTED?
2 sBRANCH IF NO
::CHAR THERE?

;:1F NO, DON'T WAIT AROUND
::SAVE THE CHAR
::STRIP=OFF THE ASCII
2:1S IT A CONTROL G?
;:NO, RETURN TO USER
;sARE WE RUNNING IN AUTO-MODE?
: ;BRANCH IF YES
;;ECHO THE CONTROL=-G (“G)
:sTYPE CURRENT CONTENTS
:.SAVE SWREG FOR TYPEOUT
;.GO TYPE--OCTAL ASCII(ALL DIGITS)
;;PROMPT FOR NEW SWR
;sCLEAR COUNTER
;sTHE NEW SWR

;:CHAR THERE?
:2IF NOT TRY AGAIN
;:PICK UP (CHAR

JJMAKE IT 7-BIT ASCII
;21S IT A CONTROL=U?
s ;BRANCH IF NOT
;:YES, ECHO CONTROL=-U (*UV)
;s IGNORE PREVIOUS INPUT
::LET'S TRY IT AGAIN
;IS IT A <CR>?
2 JBRANCH IF NO
..YES IS IT THE FIRST CHAR?
BRANCH IF YES

..SAVE NEW SWR
;:CLEAR UP STACK
;2ECHO <CR> AND <LF>
;JRE=-ENABLE TTY KBD INTERRUPTS?
;;BRANCH IF NOT
::RE-E::BLE TTY KBD INTERRUPTS

;F YES
..BRANCH
..BRANCH IF YES
::STRIP=QOFF ASCII
2:1S THIS THE FIRST CHAR
s ;BRANCH IF YES
::NO, SHIFT PRESENT
CHAR OVER TO MAKE
;:
ROOM FOR NEW ONE.
;.

104

INPUT ROUTINE

017200
017204
017210
017212
017216

00526€
056616
000707
104401

000720

000002
177776

17%:

001062

18%:

07-JuL-81 15:03
INC
BIS
BR

.DSABL

TYPE
BR

LS8

B 9
PAGE 79-1

SEQUENCE

;;KEEP COUNT OF CHAR
;sSET IN NEW CHAR
;sGET THE NEXT ONE

2(SP)
-2(SP), (SP)
7%
$QUES

J2TYPE ?7<CR><LF>

208

s sSIMULATE CONTROL=-U

::ttt.tt*'t'*'ttit'.tt'tt't"'tt.ttt'flu't"'t't"'tt'tt'i'tt'tt"

;*THIS ROUTINE WILL INPUT A SINGLE CHARACTER FROM THE TTY

000004
161610

000002

161604
177600

000004
000004
000023

000004

000140

000004

000175

000040

000004

1%
@$TKB,4 (SP)

BNE

#°C177.(SP)

CMP
BEQ
CMP
BLT

4 (SP)
, #SXON
1%

CMP

RTI

AR R

BIC

BGT
BIC

4%:

#AC<177>.4(SP)
L(SP) 423
a$TKS

CMP
BNE
BR

3%:

@$TKS

TSTB

BPL
MOVB

000021

BPL
MOVB

BIC
CMP

161552
177600

000004

(SP) ,=(SP)
4(SP),2(SP)

TSTB

2%:

161556

MOV
MOV

2%
@$TKB,=-(SP)
(SP)+ 421
2%
1%

;RANOO1
:RANOO1

;JBRANCH IF YES

4(SP) ,#140
4$

4(SP) ,#175
4%
#40,4 (SP)

AR A AR A AR AR A AR AR AR

;:PUSH DOWN THE PC
;:SAVE THE PS
JIWAIT FOR
;sA CHARACTER
JJREAD THE TTY
;:GET RID OF JUNK IF ANY
;:IS IT A CONTROL=-S?
; sBRANCH IF NO
;iWAIT FOR A CHARACTER
;;LOOP UNTIL ITS THERE
;:GET CHARACTER
J;MAKE IT 7-BIT ASCII
2218 IT A CONTROL=-Q?
;sIF NOT DISCARD IT
;.YES, RESUME
::1S IT A RANDOM XON?

017220
017222
017230
017234
017236
017244

;:INPUT A SINGLE CHARACTER FROM THE TTY
;:CHARACTER IS ON THE STACK
;:WITH PARITY BIT STRIPPED OFF

RDCHR
RETURN HERE

. %

s*CALL:

::1S IT UPPER CASE?
;;BRANCH IF YES
;21S IT A SPECIAL CHAR?
;sBRANCH IF YES
;sMAKE IT UPPER CASE
;:G0 BACK TO USER

R A AR AR AR A AR AR AR AR AR AR AR AR

AR AR

;*THIS ROUTINE WILL INPUT A STRING FROM THE TTY

s*CALL:
:'
:t

RDLIN
RETURN HERE

017250
017352
017356
017362

017456
017466

017364

017366
017370
017374
017376
017402
017404
017410
017414
017420
017422

$RDLIN: MOV
1%:
MOV
2%:
CMP
BLOS

RDCHR

000177

10%:

001062

4%:

017454
017454
000015

3%:

177777

R3,=(SP)
H#STTYIN,R3
H#STTYIN+8.
,R3
4%

MOvVB
CMPB
BNE

(SP)+, (R3)
#177,(R3)
3%

TYPE

MOvVB
TYPE

CMPB
BNE
CLRB

. SQUES

(R3),9%
.93

#15,(R3)+
2%
-1(R3)

;2INPUT A STRING FROM THE TTY
2 ;ADDRESS OF FIRST CHARACTER WILL BE gN THE STACK
;s TERMINATOR WILL BE A BYTE OF ALL O
;:SAVE R3
;:GET ADDRESS
s sBUFFER FULL?
;:BR IF YES
;:G0 READ ONE CHARACTER FROM THE TTY
;:GET CHARACTER
::1S IT A RUBOUT
J:SKIP IF NOT

22TYPE A *?°

;sCLEAR THE BUFFER AND LOOP
;ECHO THE CHARACTER
:;CHECK FOR RETURN
;:LOOP IF NOT RETURN

;;CLEAR RETURN (THE 15)

105

—_——

TTY

MACRO M1113

—————————
a—
—
—
T .o~

CZDLDHO DL11=W 11/44 MFM SLU

CZDLDHO DL11=W 11/44 MFM SLU
TTY

INPUT ROUTINE

3741

017426
017432
017434
017436
017444
017452
017454
017455
017456
017466
017473
017500
017511

104401
012603
011646
016666
012766
000002
000
000
136
136
015
040

MACRO M1113

001064
000004
017456

125
107
012
040

000002
000004

015
015
123
116

07-JuL-81 15:03

TYPE
MOV
MOV
MOV
MOV
RTI
9%:
.BYTE
.BYTE
$TTYIN: .BLKB
S$CNTLU: .ASCIZ
SCNTLG: .ASCIZ
$MSWR:
ASCIZ
SMNEW:
.ASCIZ

.SLF
(SP)+,R3

(SP) ,=(SP)
4(SP) ,2(SP)
#STTYIN,4(SP)

0
0
8'

/2U/<15><12>
/2G/<15><12>
<15><12>/SWR =
/

SEQUENCE

PAGE 79-2

NEW =

;:TYPE A LINE FEED

;sRESTCRE R3

..ADJUST THE STACK AND PUT ADDRESS OF THE
FIRST ASCII CHARACTER ON IT
‘e

: ;RETURN
;STORAGE FOR ASCII CHAR.
;s TERMINATOR

TC TYPE

:RESERVE 8 BYTES FOR TTY INPUT
;;CONTROL 'V
;sCONTROL ''G"'

106

CZDLDHO DL11=Ww 11/44 MFM SLU
TTY

INPUT ROUTINE

MACRO M1113

3743
3744
3745

07-JuL-81 15:03

.SBTTL

D 9
PAGE 80

SEQUENCE

107

TRAP DECODER

AR RN AR RN AR RN AN AN AR AR A ARAR AR AR AR AR AR AN RRRANAACRRRRRRRRAARR

;*THIS ROUTINE WILL PICKUP THE LOWER BYTE OF

THE '‘TRAP'' INSTRUCTION

s*AND USE I7 TO INDEX THROUGH THE TRAP TABLE FOR THE STARTING ADDRESS
;*0F THE DESIRED ROUTINE. THEN USING TIIE ADDRESS OBTAINED IT WILL
;*GO TO THAT ROUTINE.

017522
017524
017530
017532
017534
017536
017542

010046
016600
005740

000002

006300
016000
000200

017556

017544
017546
017554

011646
016666
000002

000004

$TRAP:

111000

MOV
MOV
TST
MOVB

RO,=(SP)
2(SP) ,RO
-(RO)
(RO) ,RO

;:SAVE RO
;:GET TRAP ADDRESS
;;BACKUP BY 2
;:GET RIGHT BYTE OF TRAP

(SP) ,=(SP)

;:MOVE

ASL
RO
;;POSITION FOR INDEXING
MOV
$TRPAD (RO) ,RO
;s INDEX TO TABLE
RTS
RO
;:G0 TO ROUTINE
::THIS IS USE TO HANDLE THE '‘GETPRI'' MACRO

000002

$TRAPZ2: MOV

MOV

.SBTTL

4(SP) ,2(SP)

RTI
TRAP TABLE

THE PC DOWN

::MOVE THE PSW DOWN

;sRESTORE

THE PSW

;*THIS TABLE CONTAINS THE STARTING ADDRESSES OF THE ROUTINES CALLED

;*BY THE ''TRAP'' INSTRUCTION.

3746

017556
017560
017562
017564
017566
017570
017572
017574
017576

017544
016144
016534
016510
016550
017006
016736
017220
017350

ROUT INE

$TRPAD:

.WORD
$TRAP?
$TYPE
;;CALL=TYPE
$TYPOC
;;CALL=TYPOC
$TYPOS
;;CALL=TYPOS
$TYPON
;.CALL=TYPON
$GTSWR
;;CALL=GTSWR
$CKSWR
;;CALL=CKSWR
$RDCHR ;; CALL=RDCHR
$RDLIN
;;CALL=RDLIN

TRAP+1(104401)
TTY TYPEOUT ROUTINE
TRAP+2(104402)
TYPE OCTAL NUMBER (WITH LEADING ZEROS)
TRAP+3(104403)
TYPE OCTAL NUMBER (NO LEADING ZEROS)
TRAP+4(104404)
TYPE OCTAL NUMBER (AS PER LAST CALL)
TRAP+5(104405)
GET SOFT-SWR SETTING
TRAP+6(104406)
TEST FOR CHANGE IN SOF T-SWR
TRAP+7(104407)
TTY TYPEIN CHARACTER ROUTINE
TRAP+10(104410) TTY TYPEIN STRING ROUTINE

CHO TEST

SEQUENCE

ECHO TEST

;*THIS ROUTINE WILL ECHO ANY CHARACTER TYPED

;*AT THE CONSOLE
s*THE TEST IS HALTED BY TYPING A CONTROL=-C
s*TEST CAN BE RESTARTED AFTER HALTING BY JUST CONTINUING
a

2223323223232

ECHO:

000052

163052

163034
163026

163036

163040

2%:

010000

017724

RESET

MOVB
TSTB
BPL
MOVB
MOV
BPL
BIS
BIT
BEQ
JSR

3%:
017724
4%:

MPAR

5%:

000200
000003
017724

— —

—

COOO

b
b

117

123

dld

R1.RO

:TRANSMIT PROMPT ''s''
JWAIT FOR INPUT

;ECHO INPUT

;sSTORE INPUT
:BR IF "ERROR'NOT SET
:SET PARITY ERROR TEST MASK
;sCHECK
FOR PARITY ERROR FLAG
;BR IF NOT SET
;REPORT PARITY ERROR

JTEST FOR FRAMING ERKOR FLAG

:SHIFT MASK TO TEST 'OR'' FLAG
;TEST FOR OVERFLOW ERROR

JS:

PC ,MSG

;REPORT OVERFLOW ERROR

BIC

#81T77.RO

:CLEAR ANY PARITY BIT

BNE

;BR IF NOT

CMP

WAIT:

#3,R0

PC ,MSG
cCHO

;BR IF NOT SET

:WAS INPUT CONTROL=C

:REPORT PROGRAM STOP

JEND OF

TEST HALT

JAFTER END OF

TEST HALT

PRESS CONTINUE TO RESTART ECHO TEST

a(SP)+,R0O

;PICK UP MESSAGE POINTER

TSTB
BPL

aCTCSR
WAIT

JWAIT FOR XMIT DONE

BNE

WAIT

JASCIZ
LASCIZ

<CR><LF>/PARITY/
<CR><LF>/FRAMING/

ADD

JASCIZ
.ASCIZ

#2,-(SP)

]

;CLEAR EVERYTHING

R1
R1.RO

MOV

MOR :
MSTOP:

iRl

ASL
BIT

MSG:

MPAR :
MFR:

:BR IF NOT SET
;REPSORT FRAMING ERROR

RTS

106

220

4%
PC ,MSG

MOVB
TSTB

120

BEQ
J?:

JSR

162716

—

112077
105710
001371
000207

RS LANLV,N)

105777
100375

PC ,MSG

:SHIFT MASK TO TEST "fR'' FLAG

MSTOP
HALT

000002
162722

#'* CTBUF
aCRCSR
2%
@CRBUF ,a(C TBUF
@CRBUF ,RO
5%
#IT12.R1
R1.RO
33

BIT

013600

22222202002

ASL

BEQ

017724

—

3794 017750
3795
3796 017752
3797 017763
3798 017775
3799 020010

E 9
PAGE 81

R L
T
T

wviwvon

3786
3787 017724
3788 017726
3789 017732
3790 017736
3791 017740
3792 017744
3793 017746

07-JuL-81 15:03
.SBTTL

3748
3749
3750
3751
3752
3753
3754
3755 017600
3756 017600
3757 017602
3758 017610
3759 017614
3760 017616
3761 017624
3762 017630
3763 017632
3764 017636
3765 017640
3766 017642
3767 017646
3768 017650
3769 017652
3770 017654
3771 017656
3772 017662
3773 017664
3774 017666
3775 017670
3776 017672
3777 017676
3778 017700
3779 017704
3780 017710
3781 017712
3782 017716
3783 017720
3784 017722
3785

OQCO

MACRO M1113

IDLDHO DL11=wW 11744 MFM SLU

;ADJUST RETURN PC

(RO) +,aC TBUF
(RO)

:SEND CHARACTER
;1S THIS END OF MESSAGE?

;RETURN

;BR IF NOT

<CR><LF>/0OVERFLOW/
<CR><LF>/STOP/

108

——

| CZDLDHO DL11=w 11/44 MFM SLU
(ECHO TEST

07-JuL=-81

3801
3802

15:03

F
9
PAGE 82

SEQUENCE

.EVEN

.SBTTL

TERMINAL OUTPUT

TEST

:;'Q'Qt.'..Q.'t't"."t"'".Q'."."...t"tt.t..'t'tttt'.'t.'..l

;*THIS ROUTINE WILL OUTPUT ALL WRITABLE

;*THE OCTAL CODE 040 ==> 377
;%32 CHARACTERS ARE PRINTED ON EACH LINE

NN —

;*THE

PATTERN IS REPEATED EVERY

(HARACTERS

FOR

THE

THREE LINES

3 25

8
8
e

::'QI'.Q.Q"Q"..'Q't""""'Q.'Q.'..t't...'.'flt..'.""'ttt.."

2 o
3

WR
= [@Xs) OOV

a8 g EELEEEE

MACRO M1113

012701
012700
105777

000040
000040

010177

162620

100375

105201

005300
001370
004737

3824
3825 020054 "001063
105777
3826 020056
3827 020062
3828 020064
3829 020070
3830 020072
3831
3832 020074
005077
3833 020100 000000
3834 020102
000746

162624

OUTTST: MOV
1%:
MOV
TSTB
2%:
BPL
MOV

INCB
DEC
BNE
JSR

017724

$CRLF

162572

TSTB

000200

3%:

;WAIT FOR DONE

PC,MSG

aCRCSR

;ANY CHARACTER RECEIVED?

RO
2%

3%
#8177 ,R1
QUTTST

(LR

a(RBUF

OuTTST

HALT

;LOAD FIRST WRITABLE (HARACTER
;LOAD CHAR COUNT PER LINE

s TRANSMIT A CHARACTER
; INCREMENT CHARACTER CODE
;DECREMENT CHAR COUNT
;BR IF LINE NOT COMPLETE
;SSUE CR,LINE FEED

Ri,aCTBUF
R1

BMI
BIT
BNE

162556

#40,R1
#40,R0
aCTCSR

:BR IF

YES

;BR IF

YES

;FINISHED ONE PASS OF WRITABLE (HARACTERS?

s IF NOT WRITE NEXT LINE

;CLEAR RECEIVER

;STOP TEST

sRESTART

TEST

CONTINUED

109

—

- ETATTRTITTITITITAITTIOTITITITITEITITI
VI MY AcA

3855 021016
3856 021053
3857 021104
3858 021137
3859 021200
3860 021243
3861 021302
3862 021333
3863 021366
3864 021434
3865 021476
3866 021534
3867 021564
3868 021616
3869 021656
3870 021704
3871 021744
3872 021776
3873 022027
3874 022063
3875 022120
3876 022120
3877 022154
3878 022<01
3879 022231
3880 022306
3881 022332
3882 022370
3883 022426
3884 022470
3885 022470
3886 022517
3887 022543
3888 022610
3889 022634
3890 022660
3891 022726
3892 022764

103
103
124

101
101
103

116
116
123

124
124
103
103
103
102
103
103
122
102
103
103
122
102
130
103
103
122
102
122
103
103
103
102
114
103
103
122
104
102
103
102
122
122

103
103
101
101
101
111
101
101
105
11
101
101
105
111
115
101
101
105
11
103
101
101
101
111
113
101
101
105
125
11
101
m
124
124

123
123
116
116
116
124
116
116
123
1264
116
116
123
126
111
116
116
123
126
126
116
116
116
124
123
116
116
123
101
126
116
1264
103
103

122
122
122
122
103
130
130
130

124
124
105
124
114
115
115
115

103
103
123
103
117
111
111
111

130
130
114
122
122
122
122
122

115
115
117
103
103
103
105
104

111
111
101
126
126
126
123
122

EMI1:
EMZ:
EM3:

EMé:
EMS:
EM6:
EM7:
EM10:
EM11:
EM12:
EM13:
EM14:
EM15:
EM16:
EM17:
EM20:
EM21:
EM22:
EM23:
EM24:
EM25:
EM26:
EM27:
EM30:
EM31:
EM32:
EM33:
EM34:
EM35:
EM36:
EM37:
EM40:
EM41:
EM42:
EM43:
EM44:
EM45:
EM47:
EM46:
EM50:
EMS51:
EM52:
EM53:
EM54:
EM56:
EM57:
EMSS:
EM60:
EM61:
EM62:
EM63:
EM64:
EM65:
EM66:
EM67:

15:03

G.9

PAGE 83

.ASCIZ
LASCIZ
.ASCIZ
.ASCIZ
LASCIZ
.ASCIZ
.ASCIZ
._ASCIZ
_ASCIZ
_ASCIZ
_ASCIZ
_ASCIZ
_ASCIZ
.ASCIZ
_ASCIZ
.ASCIZ
_ASCIZ

/CAN NOT ACCESS TCSR/
/CAN NOT ACCESS TBUF/
/TCSR DONE NOT CLEARED WITH TBUF FULL/
/TCSR DONE NOT SET/
/TCSR DONE NOT SET WITiI RESET/
/CAN NOT ACCESS RCSR/
/CAN NOT ACCESS RBUF/
/CAN NOT ACCESS LKS/
/BITO OF TCSR NOT CLEAR AFTER RESET/
/CAN NOT SET BITO OF TCSR/
/CAN NOT CLEAR BITO OF TCSR/
/RESET DID NOT CLEAR BITO OF TCSR/
/BIT2 OF TCSR NOT CLEAR AFTER RESET/
/CAN NOT SET BIT2 OF TCSR/
/CAN NOT CLEAR BIT2 OF TCSR/
/RESET DID NOT CLEAR BIT2 OF TCSR/
/BITé OF TCSR NOT CLEAR AFTER RESET/

ASCIZ
_ASCIZ
.ASCIZ

/BIT7 OF LKS DOES NOT SET/
/RTC INTERRUPT AT PRIORITY 7/
/RTC INTERRUPTS WHEN DISABLED/

.ASCIZ
_ASCIZ
_ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
_ASCIZ
.ASCIZ
_ASCIZ
.ASCIZ
_ASCIZ
.ASCIZ
_ASCIZ
.ASCIZ
ASCIZ
_ASCIZ

/XMIT INTERRUPT AT PRIORITY 7/
/CAN NOT SET BIT6 OF TCSR/
/CAN NOT CLEAR BIT6 OF TCSR/
/RESET DID NOT CLEAR BIT6 OF TCSR/
/BIT6 OF RCSR NOT CLEAR AFTER RESET/
/RCVR INTERRUPT WITH PRIORITY 7/
/CAN NOT SET BITé OF RCSR/
/CAN NOT CLEAR BIT6 OF RCSR/
/CAN NOT CLEAR BIT6 OF RCSR WITH RESET/
/BIT6 OF LKS NOT CLEAR AFTER RESET/
/LKS INTERRUPT WITH PRIORITY 7/
/CAN NOT SET BIT6 OF LKS/
/CAN NOT CLEAR BIT6 OF LKS/
/RESET DID NOT CLEAR BIT6 OF LKS/
/DUAL ADDRESSING ERROR/
/BIT6 OF LKS NOT SET AFTER RESET/
/CAN_NOT CLEAR BIT7 OF LKS/

ASCIZ
.ASCIZ
_ASCIZ
.ASCIZ
.ASCIZ
_ASCIZ
.ASCIZ
.ASCIZ

/RTC INTERRUPT DID NOT OCCUR/
/RTC DOUBLE INTERRUPT/
/RESET DID NOT INTERRUPT/
/RTC INTERRUPT DID NOT CLEAR WITH BIT7 OF LKS/
/CLOCK REPEATABILITY/
/XMIT INTERRUPTS WHEN DISABLED/
/XMIT INTERRUPTS AT PRIORITY 7/
/XMIT INTERRUPTS WITH ENABLE CLEAR/

.ASCIZ
_ASCIZ
.ASCIZ
_ASCIZ
.ASCIZ
.ASCIZ
.ASCIZ
,ASCIZ

/XMIT DID NOT INTERRUPT/
/XMIT RE-INTERRUPTED/
/LOADING TBUF DID NOT CLEAR INTERRUPT/
/RCVR ACTIVE NOT SET/
/RCVR DONE NEVER SET/
/RCVR ACTIVE NOT CLEARED WITH DONE SET/
/RESET DID NOT CLEAR RCVR DONE/
/RDR ENABLE DID NOT CLEAR RCVR DONE/

SEQUENCE

110

3836
3837
3838 020104
3839 020130
3840 020154
3841 020221
3842 020243
3843 020300
3844 020324
3845 020350
3846 020373
3847 020436
3848 020467
3849 020522
3850 020563
3851 020626
3852 020657
3853 020712
3854 020753

07-JuL-81

!
i
!

MACRO M1113

- CZDLDHO DL11=w 11/44 MFM SLU
TERMINAL OUTPUT TEST

| CZDLDHO DL11=W 11744 MFM SLU
TEST

H 9
PAGE 83-1

07-JuL-81 15:03

SEQUENCE

3936 025046

No Xeo Yo Yo

wid

Mo No e
e
e
(e N

i
s

i
b

b
i

cnld
s
o

i e
o

i
anid

il
i

o
ld

3947 025222
3948
3949

394

jolele]
o0
88888888888

3932 025014
39%2 025016

onrn

>33 eeeeEEEEEIEEED>

/RCV ACTIVE WITHOUT ''START'' BIT/

/RDR ENABLE NOT CLEAR WITH RCV ACTIVE/

.AS
.AS
.AS

/TESTA

ERR PC

ERROR#
ERR PC
ERR PC
ERR PC

/TESTA

/TESTRA

/TESTA
/1ESTA#
/TESTA
/TEST#

ERR PC

ERR PC
ERR
ERR
ERR
ERR

PC
PC
PC
PC

TC(CSR/
TBUF/
RCSR/
RBUF/
LKS/

GOOD

BAD/

RCSR
RCSR
RC(SR
RCSR

DATA/
GOOD
TRANS
OLDPC

LKS

CNT1

(NT2/
BAD/

RCV/
TRAP ADR/

M2:
M2A:

DT1:
DT2:

$TESTN,SERRPC,
TCSR, 0
STESTN. SERRPC . TBUF . 0
STESTN.$ERRPC .RCSR. 0
$TESTN. SERRPC .RBUF .0

002634
002634
002634
002634

DT7:
DT10:
DT40:
DTS53:
DT103:
DT105:
DT110:
DT112:

ENDADR:

.WORD
.WORD
.WORD

. WORD
. WORD
.WORD
. WORD
-WORD

/INCORRECT RECEIVE COUNT/

/DATA COMPARE ERROR IN EXERCISER/
/TRAP CATCHER/
/NO CLK INTERRUPT IN EXERCISER/
/'ERROR'’ NOT SET WITH 'FR'' FLAG/
/RCV ACTIVE NOT CLEAR WITH INIT/

040

DT6:

il cidli s

/RCVR DID NOT INTERRUPT/
/RCVR RE=INTERRUPTED/
/READING RBUF DID NOT CLEAR INTERRUPT/
/RESET DID NOT CLEAR RCVR INTERRUPT/
/'OR' FLAG DID NOT SET/
/"ERROR' NOT SET WITH 'OR' FLAG/
/BREAK DID NOT XMIT ALL ZEROES/
/BREAK DID NOT SET °'FR' ERRCR/
/DATA COMPARE ERROR/
/LOOP-BACK DATA COMPARE ERROR/
/TIMEOUT IN EXERCISER TEST/

<CR><LF>?CZDLDHO DL11-W 11/44 MFM SLU?

002640
002642
002634
002636
002674
001020
002674

INT RQST PASSED WITH ENABLE CLEAR/

> >>

wunmom
LWunmunhuvumhunomhobmhunmouunmoomnuvonmonouoom
nwnnhunn
alalalalzaizalsliaslialzialalalalslialislslalalalalalalaliala B alalale]

DH103:
DH105:
DH110:
DH112:

/RCVR

/TESTA
/TESTA
/TESTA
/TESTA

DH1:
DH2:
DH6:
DH7:
DH10:
DH4O0:
DH53:

/RCVR INTERRUPTS AT PRIORITY 7/

>>>>>

EM117:

il el

)

NDNNVO
ONONON—

) il il il
D i il el O

b i

i ol i

) i i il

PNV
ONO = =NOOMNVNRCNONNY
NORONNO =S LWV NVTINNVW-=0NOfF

i il
il

b e

POV
WWWWANWWWWWW

EM116:

-AS

/READING RBUF DID NOT CLEAR RCVR DONE/
/RCVR INTERRUPTS WITH ENABLE CLEAR/

M1:

012

EM70:
EM71:
EM73:
EM74:
EM72:
EM75:
EM76:
EM77:
EM100:
EM101:
EM102:
EM103:
EM104:
EM105:
EM106:
EM107:
EM110:
EM111:
EM112:
EM113:
EM114:
EM115:

d
o

WWWWDN
WWANNN =N = N=NONVNNIWUNWNWWN

i
b
il
il
el
il
ol
-l
3
—2 )~
—
2
—3

OOoOOoOC

)
il
il
i
il
il
il
b
i
il
wild
b

S
NNV

i
i

OO00O0O—=NO===0NNO—-=000O0

oo
NN NN

105

elelelelelelelelele
e

3930 024754

lelelelolelelalals) O
(VI
IV IV IV LV VIV VB

3918 024265
3919 024312
3920 024337
3921 024364
3922 024411
3923 024435
3924 024471
3925 024536
3926 024573
3927 024637
3928 024703

- i i il il i i il il il
N NNV
W~ S8
SSSSS

024063
024122
024161
024220

O
-

3913
3914
3915
3916

il cailh il i

il i

)

NNV =NVO
=N —=000 &~

3893 023027
3894 023074
3895 023136
3896 023174
3897 023243
3898 023243
3899 023272
3900 023316
3901 023363

rnororenrno

TERMINAL OUTPUT

MACRO M1113

DEVICES UNDER TEST

$TESTN. SERRPC .LKS.0

$TESTN. SERRPC . SGDADR, $8DADR , 0
STESTN. SERRPC .LKS,F IRST,SECND.0
$TESTN.SERRPC
.RCSR, $8DDAT, 0
$TESTN.SERRPC .RCSR.$GDDAT . $SBDDAT,0
STESTN. SERRPC .RCSR. XMTCNT .RCVCNT .0

$TESTN. SERRPC .RCSR.OLDPC.BDVECT,

CEND ADDRESS FOR CHECKSUM AND SAVE
‘OF WRAP AROUND CONSOLE TEST

AREA

r—

CZDLDHO DL11=w 11/44 MFM SLU
TERMINAL

3950

QUTPUT

TEST

000001

MACRO M1113 07-JuL=-87 15:03 PAGE 53-2
.END

SEQUENCE

112

ADDW13= 000000

BIT07 = 000200

DISPRE

000174

EM36

021564

= 000012

ADDW11= 000000
ADDW12= 000000

ADDW14= 000000
ADDW15= 000000
ADDW2 = 000000
ADDW3 = 000000
ADDW4 = 000000
ADDWS = 000000
ADDW6 = 000000
ADDW7 = 000000
ADDW8 = 000000
ADDWS = 0C0000
ADEVCT= 000000

ADEVM = 000000
ADR
004132
ADRTBL 002702
AENV = 000000
AENVM = 000000
AFATAL= 000000
AMADR1= 000000

AMADRZ= 000000
AMADR3= 000000
AMADR4= 000000
AMAMS
1= 000000
AMAMS?2= 000000
AMAMS 3= 000000
AMAMS4= 000000
AMSGAD= 000000
AMSGLG= 000000
AMSGTY= 000000
AMTYP1= 000000
AMTYP2= 000000
AMTYP3= 000000
AMTYP4= 000000

BITO5 = 000040
BITO6 = 000100
BITO8 = 000400
BITO9 = 001000
BIT1 = 000002
BIT10 = 002000
BIT11 = 004000
BIT12 = 010000
BIT13 = 020000
BIT14 = 040000
BIT15 = 100000
BIT2 = 000004
BIT3 = 000010
BIT4
BITS
BITé
BIT7

BIT8

= 000020
= 000040
=
1
= 000200
= 000400
= 001000

BIT9
BPT
= 000003
BPTVEC= 000014
BUF
002454
CATCH
014520
CHKSUM 014010
CKSWR = 104406

CLK
CLKCNT
CMPARE
CNTLP
CoMP

013630
002444
007330
002564
013432

DH1

024265

APASS = 000C00
APRIOR=
APTCSU= 000040
APTENV= 000001
APTSI1Z= 000200
APTSPO= 000100
APTSZD 003636
ASWREG= 000000
ATESTN= 000000
AUNIT = 000000
AUSWR = 000400
AVECT1= 000300

CONT
006246
CONT41
012354
CPSAVE 015674
CR
= 000015
CRBUF
002656
CRCSR
002654
CRLF
= 000200
CRPSW
00
CRVECT 002664
CTBUF
002662
CTCSR
002660
CTPSW
002672
CTISTFL
002624
CTVECT 002670
DDISP = 177570
DEVADR 003014

BDVECT
BEGIN

DH10
DH103

AVECT2= 000000

002622
003774

024411
024536

DH7
DISPLA

024364
001042

DSWR = 177570
DT1
025046
DT10
025106
DT103
025144
DT105
025156
DT110
025172
DT112
025206
DT2
025056
DT40
025116
DT53
025130
DT6
025066
DT7
DVADT
ECHO
EMTVEC=

025076
003664
017600
000030

EM10
EM100
EM107
EM102
EM103
EM104
EM105

020350
23363
023426
023454
023513
023551
023606

EM1

EM106
EM107
EM1
EM110
EM111

EM112
EM113
EM114
EM115
EM116
EM117
EM12
EM13
EM14
EM15
EM16
EM17
EM2
EM20
EM21
EM22
EM23

EM24
EM25

020104

023631
023666
020373
023720
023750

024010
024025
024063
024122
024161
024220
020436
020467
020522
020563
020626
020657
020130
020712
020753
021016
021053

021104
021137

EM34
EM35

EM37
EMé
EM4O
EM&1
EM&2
EM43
EM&4
EM&S
EM&6
EM47
EM5
EM50
EM51
EM52
EM53

EMS54

EMS55
EM56
EMS57
EM6
EM60
EM61
EM62

EM63
EM64
EM65
EM66
EM67

EM7
EM70
EM71
EM72
EM73
EM74
EM75
EM76
EM77
ENDADD=
ENDADR
ENDB7
ENDEV
ENDMG
ENDSTK
ERROR =

021476
021534

I0TVEC= 000020
JIMSTK 002432

021616
020221
021656
021704
021744
021776
022027
022063
022120
022120
020243

LKS
002674
LOC1
002340
Loce
002342
MANL
003502
MFPT = 000007
MFR
017763
MOR
017775
MPAR
017752
MSG
017724
mMSTOP
020010
M1
024754

022332

OLDSUM

022154
022201
022231
022306
022470
022370
022426
020300
022470
022517
022543

022610
022634
022660
022726
022764

M2
M2A
NOEOP
OLDPC

025014
025016
014316
002620

OUTTST
PFECDF
PFECDH
PFECDT
PFECEM
PFECWS
PIRQ =

020020
015206
015146
015176
015106
015076
177772

002436

PIRQVE= 000240
PROMPT 002566
PRO
=
PR1
=
PRZ
= 000100

020324
023027
023074
023243
023136
023174
023243
023272
023316
025222
025222
004676
014272
014416
002412
104000

PR3
=
PR4
=
PRS
=
PR6
=
PR7?
=
PS
=
PSW
=
PUTLIN
PWRVEC=
RBUF
RBUF 58=
RCSR
RCSRS8=
RCV
RCVCNT
RCVDON

002336
003002

RDLIN = 104410
RESTTE 014236

ERRVEC= 000004

FIRST
FLAG44

000140
000200
000240
000300
340
177776
177776
014030
000024
002636
176502
002634
176500
013614
002440
010346

RDCHR = 104407

mam

D
INIT

014126
014062
014432
104405
= 000011
004620
003462

GETB
GETLIN
GOAGIN
GTSWR =

AlDAMD

021200
021243
020154
021302
021333
021366
021434

ALk

EM26
EM27
EM3
EM30
EM31
EM32
EM33

LMD

024573
024637
024703
024312
024435
024471
024337

DH105
DH110
DH112
DH2
DH40
DH53
DHé

BGNADD= 003014
BITO = 000001
BITO0 = 000001
81701 = 000002
BIT02 = 000004
BITO3 = 000010
BIT04 = 000020

ABASE = 176500
ACDW1 = 000000
ACDWZ2 = 000000
ACPUOP= 000000
ADDWO = 000000
ADDW1 = 000000
ADDW10= 000000

113

SEQUENCE

J_9

PAGE 83-3

07-JuL-81 15:03

SYMBOL TABLE

MACRO M1113

CZDLDHO DL11=w 11744 MFM SLU

SCPSW
SECND
SETADR
SHIFT
SIZE
SRPSW
STACK =
START
STKLMT=
STPSW

002452
002616
004100
003740
003512
002450
001100
003046
177774
002446

002630
002632
007342
TPSW
002652
TPVEC = 000064
TRAPVE= 000034
TRTVEC= 000014
TSTDEV
004050
TSTDVM
003646
TST1
004172
TST10
005044
TST1
005252
TST12
005404
TST13
005544
TST14
005614
TST15
005764
TST16
006154
006262
TST17
TST2
004244
TST20
522
TST21
006720
TST22
007054
TST23
007222
TST24
007410
TST25
007520
TST26
007646
TS127
010012
TST3
004316
TST30
010156
TST31
010462
TST32
010554
TST33
010700
TST34
011102
TST35
011304
TST36
011512
TST37
011656
TST4
004466
TST40
012014
TST41
012200
TST42
012414
TST43
012576
TST44
012744
TST4S
013062
TST46
013636

TMP2
TMP3
TOLER

SCOPE = 000004

SWR
001040
SWREG
000176
SWw0
= 000001
SW00 = 000001

Sw01
Sw02
Sw03
Sw04
SW05
Swoé6
Sw07
Sw08
Sw09
Sw1
SW10
SW11
Swi2
Sw13
SW14
Sw15
Sw2
Sw3
Swé
SW5
Sw6
Sw7
Sw8
Sw9

= 000002
= 000004
= 000010
= 000020
= 000040
= 000100
= 000200
= 000400
= 001000
= 000002
= 002000
= 004000
= 010000
= 020000
= 040000
= 100000
= 000004
= 000010
= 000020
= 000040
= 000100
= 000200
= 000400
= 001000

TA
002610
TBITVE= 000014

. ABS.

025224
000000
ERRORS DETECTED:

000
001

$MADR3
$MADR4

016732
016734
015660

s
LMD LMD
AL
AL

001046
001044
7
001052
001057
001C50
017522

$TKB
$TKS
=
$IN
$TPB
$TPFLG
$TPS
$TRAP

001074
000506
015364
015212
015346
015264
001062
017220
017350
000010

$PASS
$PASTM
$POWER
$PWRDN
$PWRMG
$PWRUP
SQUES
$RDCHR
SRDLIN
$RDSZ =

002434
014202
002344
002346

001003
001015
014544
001016
001146
014726
001012
001060
001106
001146
001070
016142
001056
001055
001020
001024
014366
017006
000500

SAVEPS
SAVETE
SAVEQO
SAVLOC

TCSR58= 176504
TIMER
014162
TKVEC = 000060
TMP1
002626

S$ERFLG
$ERMAX
$ERROR
$SERRPC
$ERRTB
S$ERRTY
SERTTL
$ESCAP
$ETABL
$ETEND
SFATAL
$FFLG
SFILLC
$FILLS
$GDADR
$GDDAT
$GET42
$GTSWR
$HIBTS
$ICNT
$ILLUP
$INTAG
SITEMB
SLF
SLFLG
$LPADR
SLPERR
$MADR1
$MADR2

005536
004020
002640

004714
004760
1817
005012
TURBUF 003006
TURCSR 003004
TUTBUF
003012
TUTCSR 003010
TVECT
002650
TYPE = 104401
TYPOC = 104402
TYPON = 104404
TYPOS = 104403
VCTADR 003670
002742
VCTTBL
004152
VECT
010230
WACTV
WAIT
017732
WDONE
010362
WRAP
0713640
014502
WRPSW
wT
010316
XCONT
013604
013542
XMIT
XMTCNT
002442
XRET
013610
$APTHD 000500
$SATY(C
015722
$ATY1
015676
$SATY3
015704
$SATYS
015714
$AUTOB 001034
$BASE
001142
$8DADR 001022
$BDDAT 001026
$CHARC 016504
$CKSWR 016736
$CMTAG
$CM3 =
$CNTLG
$CNTLU
$CPUOP
$CRLF
$DEVCT
$DEVM
$DOAGN
$ENDAD
SENDCT
SENULL
SENV
SENVM
$EOP
S$EOPCT
TSTé

TCLOCK
TCONS
TCSR

RTCPSW 002700
RTCVT
002676
RVECT
002644
R6
=%000006
R7
=%000007

TSTS

114

002642

TBUF 58= 176506

SEQUENCE

TBUF

K.
9
PAGE 83-4

RESVEC= 000010
RPSW
002646
RSTRT
014472

SYMBOL TABLE

07-JuL-81 15:03

MACRO M1113

CZDLDHO DL11=W 11744 MFM SLU

CZDLDHO DL11=W 11/44 MFM SLU
SYMBOL TASLE

MACRO M1113

07-JuL-81 15:03

VIRTUAL MEMORY USED:
40488 WORDS
( 159 PAGES)
DYNAMIC MEMORY:
20034 WORDS
( 77 PAGES)
ELAPSED TIME:
00:17:06
CZDLDH.BIN,CZDLDH/CR/=SP/NL
: TOC=CZDLDH.MLB/ML,CZDLDH.P11

PAGE 83-5

SEQUENCE

115

SEQUENCE

116
vO1

CREF

PAGE 1

21-1482

oth

21-1482

]
oAN 1N ]

21-1482

0o Co(o ]

&N N

b wad b

b ab b

ADDW13

21-1482
21-1482
21-1482
21-1482
rorn0

ADDWO
ADDW1
ADDW10
ADDW11
ADDW12

REFERENCES

#17-1435

ACPUOP

ON 7-JUL-81 AT 15:10

SYMBOL CROSS REFERENCE
SYMBOL
AL
176500
ABASE
ACDW
ACDW2

MACRO

CREATED BY

CZDLDH

ADDW14

ADDW15
ADDW2
ADDW3

nnun

#77-3731
73-3592
30-1967
77-3688

30-1988
21-1482
21-1482
21-1482

30-2083

..n_a_n_.n_a_n_a

ol
culd i
b b b

USLSTS
LN TN TN N )

21-1482
21-1482
30-2088
30-1942
21-1482
21-1482
21-1482
21-1482
21-1482

#77-3728
#77-3730

30-1990
21-1482
21-1482
21-1482

#77-3729

78-3735
#30-2016

78-3735

000400
001000
000003
000014

b aud wub abd

63-3114

67-3309

38-2261

62-3054

63-3086

73-3603
43-2429
64-3117
54-2799

76-3669

54-2809

54-2828

33-2141
34-2203
54-2822
57-2893

33-2146
35-2220
54-2830
57-2897
60-2999
64-3130

33-2147
53-2759
54-2838
57-2907
60-3004
64-3137

43-2430

49-2659

39-2321
40-2365

39-2322
40-2367
42~2417

76-3669

54-2826

56-2860

38-2281
56-2863
64-3121

38-2282
56-2869
64-3132

33-2159

33-2162
54-2793
25-2852
58-2934
62-3066
65-3181

64-3126

50-2663
53-2754
59-2967
67-3243
30-1987
69-3448
38-2254

#17-1440
#17-1433

42-2415
45-2527
48-2595

50-2676
53-2760
59-2983
67-3258

44-2466

69-3451
63-3079

44-2469

64-3119

69-3470

46-2531

51-2694
57-2883
61-3025

48-2605
51-2704
57-2902
61-3038

442470

45-2518

48-2601

81-3778

82-3828

39-2329

42-2387
43-2442
46-2544
48-2613

52-2719
57-2911
67-3235

48-2609

40-2341
42-2393
442459
46-2565
49-2624
52-2728
58-2927

67-3239

66-3186

IAIAIAIA .atNniaTMM

TM
T -

42-2410
45-2495
47-2579

39-2327
41-2375
43-2441
46-2540

ek —as

30-2053
67-3291
39-2314
40-2358

55-2846
58-2920
62-3058
65-3177

59-2966

63-3115

54-2785

ek ek ek

e
b

30-1981
30-1989
39-2304
40-2352

54-2815
57-2884
59-2961
63-3110

33-2157
53-2775
54-2843
57-2912
61-3026
65-3152

b e

=
=
=
=

63-3109

63-3096
67-3287

49-2648

aul

‘J\JVV?VVV

69-3357

42-2404
45-2491
47-2575

BIT8
BIT9
BPT
BPTVEC

38-2276

38-2266

76-3669
64-3143
33-2140
34-2193

= 000100

= 000200

38-2275

38-2256

30-2060
38-2295
63-3081
66-3194

73-3587

= 000010
= 000020
= 000040

BIT7

[ W
e B

83-3946

R ANAAMMen

21-1482

BIT6

21-1482
21-1482

#30-1894
#30-2058
#69-3336

000001
000002
000004
000010
000020
000040
000100
000200
000400
001000
000002
C02000
004000
010000
020000
040000
100000
000004

PAGE 2

117
SEQUENCE
CREF
vO1

BIT3
BIT4
BITS

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

REFERENCES
#17-14 37
#17-1436

BITOO
BITO1
BITO2
BITO3
BITO4
31105
BITO6
BITO7
BITOB
BITO9
BIT1
BIT1I0
BIT11
BIT12
BIT13
BIT14
BIT1S
BIT2

ON 7-JuL-81 AT 15:10

bkl o

SYMBOL CROSS REFERENCE
SYMBOL
VALUE
AUSWR
= 000400
AVECT1
= 000300
AVECT2
=
BDVECT
002622
BEGIN
003774
BGNADD = 003014
BITO
= 000001

MACRO

CREATED BY

CZDLDH

CREATED BY

SYMBOL CROSS REFERENCE
SYMBOL
VALUE

BUF
CATCH
CHKSUM

002454
014520
014010

CKSWR
CLK
CLKCNT
CMPARE

= 104406
013630
002444
007330

compP

013432

CNTLP
CONT

MACRO

ON 7-JuUL-81 AT 15:10

REFERENCES
#30-1886

67-3282

69-3385

#69-3410
#80-3745

*67-3220

67=3276

*67-3326

76=3669
30-1888

*76-3665
30-1888

76=3669
30-1889

78-3735

#72-3558

73-3602

76-3669
#67-3326

67-3237

002564

#30-1882
49-2641
#30-1887

006246

#46=2476

#49-2644

#67-3284

69-3372
67-3292

63-3099

#63-3107

81-3798

81-3799
81-3760
30-2007

CONT4
CPSAVE
CR

012354
015674
= 000015

CRBUF
CRCSR
CRLF
CRPSW
CRVECT
CTBUF
CTCSR

002656
002654
= 000200
002666
002664
002662
002660

#30-1918
#30-1917
#17-1433
#30-1922
#30-1921
#30-1920
#30-1919

CTPSW
CTSTFL

002672
002624

#30-1924
#30-1900

CTVECT
DDISP
DEVADR
DH1

002670
= 177570
003014
024265

DH10

024411

DH103
DH105
DH110
DH112
DH2
DH40
DHS3
DH6

024536
024573
024637
024703
024312
0c4435
024471
024337

DH7
DISPLA
DISPRE
DSWR
DT1

024364
001042
000174
= 177570
025046

74-3618
#17-1433

54-2838
58-2944
65-3177

34-2191

47-2569
#30-1923
#17-1433

#30-1942

22-1485
23-1549
27-17)0
23-1519
26-1656
29-1807
29-1817
30-1831
30-1841
22-1490
25-1637
27-1690
22-1510
28-1744
29-1787
30-1866
23-1514

#21-1482
#17-1469
#17-1433

22-1486

B8 10

SEQUENCE
118
vO1
CREF

67-3248

17-1458

69-3369

PAGE 3

44=2475

*76-3669
71-3535

#76-3669

78-3735

83-3930
81-3761
30-2064

83-3932
82-3832
81-3758

81-3757
34-2180
564-2843
58-2948
65-3181

81-3760
34-2193
55-2852
59-2966
81-3789

81-3791
34-2203
56-2877
60-3004
82-3817

82-3819
53-2775
57-2893
62-3066

*30-1957
38-2258
4£8-2595

*30-1983
38-2268
49-2624

*30-2063
38-2284
62-3051

31-2103
41-2375
63-3083

32-2120
42-2387

21-1482
30-1992
22-1495
23-1554
27-1705
25-1612
26=1661

30-1967
30-2024

22-1500
24-1558
27=1710
25-1617
26-1666

69-3336
22-1505
24=-1563
27=1715
25-1622
26=1671

23-1524
24-1568
27-1720
25-1627
26=1676

23-1529
24-1573
27-1725
25-1632
26-1681

#83-3918

30-1821
#83-3927
#83-3928

30-1836

#83-3926

24-1588
28-1749
29-1792

24-1593
28-1754
29-1798

24-1598
28-1759
29-1803

25-1602
28-1764
29-1812

#83-3921
*30-1967

*30-1967

73-3582

76-3669

30-1967
22-1501

22-1506

23-1525

#83-3925

#83-3919
#83-3923
#83-3924

#83-3920

30-1967
21-1482
22-1496

31-3796

81-3797

54-2822
57-2912
63-3115

54-2830
58-2934
64-3137

82-3826

54-2793
57-2897
63-3104

33-2132

442459

45-2483
67-3272

33-2150

34-2178
46-2531
*70-3531

24-1578

23-1534

23-1539
24-1583

23-1544
27-1695

25-1642
26-1686

26=1646
30-1846

#83-3922

25=1607
28-1769
30-1826

27-1730
28-1774
30-1851

28-1734
29-1778
30-1856

28-1739
29-1782
30-1861

23-1530

23-1535

23-1540

23-1545

64-3123

67-3233

26=1651

CZDLDH

CREATED BY

SYMBOL CROSS REFERENCE
SYMBOL
VALUE

DT10

025106

DT103
DT105
DT110
DT112

025144
025156
028172
025206

DT40

025116

DT?2

D153

D16

025056

025130
025066

D17
DVADT
ECHO
EMTVEC
EM1
EM10

025076
003664
017600
= 000030
020104
020350

EM116

024161

EM100
EM101
EM102
EM103
EM104
EM105
EM106
EM107
EM11
EM110
EM111
EM112
EM113
EM114
EM115

EM117
EM12
EM13
EM14
EM15

EVMi6

EM17
EM2
EM20
EM21
EM22
EM23
EM24
EM25
EM26

023363
023426
023454
023513
023551
023606
023631
2
020373
023720
023750
024010
024025
024063
024122

MACRO

ON 7-JuUL-81 AT 15:10

REFERENCES

23-1550
27-1701
23-1520
26=1657
29-1808
29-1818

25-1638
27-1691
22=1511
28-1745
29-1788
30-1867
23-1515
30-2022
22-1484
23-1518
29-1791
29-1797
29-1802
29-1806
29-1811
29-1816
30-1820
30-1825
23-1523
30-1830
30-1835
30-1840
30-18.5
30-1850

024220
020436
020467
020522
0<0563

020626

020657
020130
020712
020753
021016
021053
021104
021137
021200

*30-1967

#83-3838
#83-3845
#83-2901
#83-3902
#83-3903
#83-3%04
#83-3905
#83-3906
#83-3907
#83-3908
#83-3846
#83-3909
#83-3910
#83-3911
#83-3912
#83-3913
#83-3914
#83-3915
#83-3916
#83-3847
#83-3848
#83-3849
#83-3850
#83-3851

#83-3852

24-1582
24-1587

#83-3839
#83-3853
#83-3854
#83-3855
#83-3856
#83-3857
#83-3858
#83-3859

c10

119
SEQUENCE
vO1
CREF

241564
27-1716
25-1623
26-1672

30-1832
30-1842
22-149

17=-1474
#17-1433

PAGE 4

30-1837

#83-3944

24=15%94
28-1755
29-1799

24=1599
28-1760
29-1804

81-3784
*30-1967

24-1569
24-1574
27=1721
27=1726
25-1628 251653
26=1677
26-1682

25-1603
28-1765
29-1813

25-1608
28-1770
30-1827

24=1579

24-1584

27-1696

25-1643
26-1687

26=1647
30-1847

#83-3940

27-1731
28-1775
30-1852

28-1735
29-1779
30-1857

28-1740
29-1783
30-1862

#83-3936

26=1652

CZDLDH

CREATED BY

SYMBOL CROSS REFERENCE
SYMBOL

EM27
EM3
EM30
EM31
EM32
EM33
EM34
EM35
EM36
EM37
EMé
EM4O0
EM&1
EM&2
EM43
EMLS
EM&S
EM4LE
EM47
EMS
EM50
EMS]
EMS?2
EMS3
EMS4
EM55
EM56
EMS?7
EM6

EM60
EM61

EM62
EME3
EM64
EMES
EM66
EME7
EM7
EM70
EM71
EM72
EM73
EM74
EM75
EM76
EM77
ENDADD
ENDADR
ENDB7
ENDEV
ENDMG
ENDSTK

VALUE

021243
020154
021302
021333
021366
021434
021476
021534
021564
021616
020221
021656
021704
021744
021776
022027
022063
022120
022120
020243
022154
022201
022231
022306
022332
022470
022370
022426
020300

022470
022517

022543
022610
022634
022660
022726
022764
020324
023027
023074
023243
0<3136
023174
023243
023272
023316
025222
025222
004676
014272
014416
002412

MACRO

ON 7-JuL-81 AT 15:10

REFERENCES

#83-3860
#83-3840
#83-3861
#83-3862
#83-3863
#83-3864
#83-3865
#83-3866
#83-3867
#83-3868
#83-3841
#83-3869
#83-3870
#83-3871
#83-3872
#83-3873
#83-3874
#83-3876
#83-3875
#83-3842
#83-3877
#83-3878
#83-3879
#83-3880
#83-3581
#83-3884
#83-3882
#83-3883
#83-3843

27-1724
27-1729
28-1733
28-1738
28-1743
28-1748
23-1513
28-1753
28-1758
28-1763
28-1768
28-1773
29-1777
29-1781
29-1786
#69-3337
69-3337
34-2198
67-3305
71-3534
#30-1876

#83-3887
#83-3888
#83-3889
#83-3890
#83-3891
#83-3892
#83-3844
#83-3893
#83-3894
#83-3897
#83-3895
#83-3896
#83-3898
#83-3899
#83-3900
69-3413
#83-3947
34-2215
#70-3526
#71-3535

27-1714
27-1719

PAGE 5

SEQUENCE

CREF

24=1592
22=-1494
24=1597
25-1601
25-1606
25-1611
25-1616
25-1621
25-1626
25-1631
22-1499
25-1636
25-1641
26-1645
26-1650
26-1655
26-1660
26-1665
26-1670
22-1504
26-1675
26-1680
26-1685
27-1689
27-1694
27-1699
27-1704
27-1709
22-1509

D10

120

V01

#83-3885
#83-3886

69-3505
#34-2217

69-3522

CZDLDH

CREATED BY

SYMBOL CROSS REFERENCE
SYMBOL
VALUE
104000
ERROR

ERRVEC
FIRST

FLAGGSL

000004
002336
003002

GETB
GETLIN
GNS

014126
014062

GOAGIN
GTSWR

014432

KRR AER

104405

JIMSTK
LF

000011
004620
003462
000020
002432
000012

LKS

002674

INIT
IOTVEC

MACRO

ON 7=JUL-81 AT 15:10

REFERENCES

#17-1433

352230
39-2318
42-2395
45-2502
50-2681
54-2823
58-2950

64=3141
72=-3562
#17-1433
#30-1871
#30-1933

63-3081
69-3381
69-3376
80-3745
80-3745
71-3534

#80-3745
#17-1433

30-1984
30-1982

#17-1433
#30-1877
#17-1433

81-3798

#30-1927

43-2432
45-2492
45-2527
L7-2575
48-2604
49-2634
#30-1872
#30-1873

PFECDF
PFECDH

015206
015146

51=2702
54-2831
59-2973
64-3146

59-2989
65-3178

30-1967

*30-1967

*30-1960
64-3121
#69-3466
80-3745
80-3745

*30-1976
65-3159
69-3468
69-3453
80-3745
80-3745

78-3735

#72-3537

34-2187

#30-1985

*30-1967
69-3362
30-1388
81-3799
41-2378
442461
£5-2494
46-2539
47-2576
48-2605
49-2637

*69-3364
*69-3365

30-1986

#30-1989

81-3772
81-3777
81-3767
81-3766
81-3782
34-2211
34-2213
*30-2055

#81-3797
#81-3798
#81-3796

#17-1434

70-3529
#30-1893
#30-1879
17=1475
74-3618
74-3618

33-2134
38-2270

42-24600
45-2515

#69-3443

E 10

121
SEQUENCE
vO1
CREF

31-2105
36-2242
39-2324

*49-2642

PAGE 6

L49-2644

34-2195

33-2144
38-2279

54=2795
57-2899
62-3074
67-3268

34-2181
39-2306
40-2370
44-2473
49-2657
54-2802
57-2908
63-3105
67-3279

*76-3669

692648

67-3287

54-2782
67-3309

54-2826

56-2860

62-3049

80-3745
80-3745

80-3745

71-3535

78-3735

81-3796

81-3797

42-2410
44-2470
4£5-2508
462544

4£8-2609

42-2404
64-2469
45-2504
462543
4£7-2580
48-2613

42-2411
442476
45-2518
46-2545
48-2600
49-2630

42-2415
45-2490
45-2519
46-2565
4£8-2601
49-2631

42-2417
45-2649
45-2520
472574
48-2602
49-2633

#81-2787

82-3823

40-2343
42-2413
46-2549

40-2348
42-2420
46-2562

52-2748
56-2872
61-3043
66-3217

33-2152
38-2286
40-2355
43-2452
47-2591
53-2776
56-2878
62-3069
67-3262

*30-1967
83-3942
38-2256
66=-3194
69-3472

763669

522734
55-2855
60-3016
66-3205

80-3745
80-3745

41-2382
442481

50-2673
54-2813
58-2936
63-3112
67-3297

*30-1967
30-1888
83-3930

30-1889
83-3932

42-2393
442466
45-2495
46-2540
47-2578

42-2403

67-3239
*€9-3484
*69-3486

83-3940

4£8-2606

44-2467
45-2496
46-2541
47-2579

81-3771

81-3776

81-3781

*69-3370

833946
69-3386
82-3829

82-383¢4

#82-3815
#74-3618
#74-3618

44-2464
£8-2618

34-2194
39-2311

#34-2202

83-3942

47-2587
49-2625

30-1973

#81-3799
#83-3930
#83-3932
#83-3933
#70-3531
*72-3561

33-2163
38-2296
40-2362

r———

CREATED BY

CZDLDH

SYMBOL CROSS REFERENCE
SYMBOL
VAL UE

177772

o
&H
o

PIRQVE

015176
015106
015076

PFECDT
PFECEM
PFECWS
PIRG

PROMPT
PRO
PR1

ON 7Z=JuUL=81 AT 15:10

REFERENCES
#74-3618
764-3618
#76-3618
764-3618
#764-3618
74-3618
#17-1433

#17-1433

PAGE 7

SEQUENCE
122
vO1
CREF

69-3375

PR2
PR3

MACRO

PR4

PRS
PR6

PR7
PS

17=-1433

002634

69-3360
69-3379
*30-1967
37=-2247
60~-3005
64-3138
69-2450
30-2065

176500

55-2653
57-2911
60-3012
66=3200
69-3448

PSW

PUTLIN
PWRVE
C

RBUF

RBUF S8

RCSR

RCSRS8

176502

013614
002440
010346

104407
104410

014236

40-2367

60-3002
66-3196
#69-3332
67-3231
#30-1880

542783

#67-3321

*67-3245
54-2810

79-3740

#80-3745

69-3383
#17-1433
#30-1911

#69-3516

#80-37
.5

RESVEC
RPSW
RSTRT
RTCPSW

RCV
RCVCNT
RCVDON
RDCHR
RDL IN
RESTTE

002646
014472
002700

72-3544
#30-1929

#72-3548
45-2487

RTCVT

002676

#30-1928

42-2389
46-2535

58-2919
60=2997

#17-1433
#17-1433
#30-1878

R7
SAVEPS
SAVETE
SAVLOC

46-2533

48-2620
#30-1910

RVECT

SAVEOQ

67-3304

69-3367

002346

#30-1874

#30-1875

59-2956

*69-3361

*69-3390

*»30-1967
54-2786
61-3027
64-3143
69-3469
30-2084

*75-3626
55-2847
62-3059
65-3156

*75-3627

36-2238

40-2341

56-2863
58-2925
61-3025

56-2867
58-2927
61-3029
83-3938

56-2869

58-2938
61-3038
83-3943

67-3264

»67=3322

83-3945

59-2958

59-2985

67-3227

67-3232

67-3303

45-2489

45-2529

46-2534

46-2536

42-2390

42-2422

45-2486

40-2338

40-2372

57-2886
59-2957
61-3045

#69-3426

43-2434

67-3243
69-3467
#54-2815

46=-2552
67-3237

67-3225
4£0-2337
58-2939
60-3018
*30-1967

58-2952
61-3023
*30-1967

*69-3360

6£9-3390

*69-3499
6€9-3501

69-3516
69-3518

#69-3499

69-3432

54-2789

46-2566
67-3301

59=2955
61-3024
30-1967

55-2851
62-3067
65-3168

54=2799

47-2572

*75-3636
56-2865

*75-3644

40-2351

40-2352
564-2818
56-2875

*75-3653
58-2921

*75-3654

63-3095
67-3321

63-3107
83-3939

40-2358
54-2828
57-2883

40-2359
54-2835
57-2891
60-2998
65-3166

46-2567

6€7-3228

67-3238

45-2488

47-2573

45-2505
472593

65-2517
48-2598

45-7528
48-2599

57-2887
59-2976
67-3224

57-2901
59-2984
67-3231

57-2913
59-2991

58-2918
60-2996

62-3072
66-3207
54-2809
56-2874
59-2964
63-3093
83-3944

57-2885
63-3091
67-3241

59-2967
63-3098
83-3945

59-2983
64-3134
83-3946

67-3300

59-2962

—
e

| CZDLDH

;

CREATED BY

SYMBOL CROSS REFERENCE
SYMBOL

| SCOPE
f
|

VALUE

= 000004

MACRO

ON 7=JUL=-81

REFERENCES

#17-1433
39-2298
48-2594

AT 15:10

31=-2096
40=-2335
49-2623

352219
442458
53=2753

36-2235
45-2482
54=2781

37=2244
46-2530
55-2844

38-2253
47-2568
56-¢859

38-2261
49-2624
66-3186

67-3302
+30-1967
41-2375
49-2659
67-3235

30-1967
42-2387
62-3047
67-3274

=30-1967
43-2430
62-3054
69-3357

+30-1967
44<2459
63-3079
73-3587

30-1981
45-2483
63-3086
73-3599

30-1989
46-2531
64=-3117
73-3603

34-2214
47-2569
64-3119
75=3634

30=-1967

79=3740

35-2221

35=2224

002452
002616
004100
003740
003512
002450
= 001100
003046

STPSW
SWR

00c4s6
001040

#30-1883
#21-1482

+67-3226
30=-1967

75=364€

76=3669

177774

#17-1470

= 000002

#17-1433

= 000001
= 000001

Sw02
SWO3
SW04
Sw0S
SWo6
W07
Sw08

=
=
=
=
=
=
=

SwW12

= 010000

SW09
Sw1
SW10
Sw11
Sw13

38-2254
48-2595
64=-3126

000176

SwO
Sw00
SW01

#17-1433

=
=
=
=

000004
000010
000020
000040
000100
000200
000400

001000
000002
002000
004000

= 020000

#17-1433
#17-1433
#17-1433
#17-1433
#17-1433
#17-1433
#17-1433
#17-1433
#17-1433

#17-1433
#17-1433
#17-1433
#17-1432

#17-1433
#17-1433

Swé
SW5

= 0C0020
=
0

#17-1433
#17-1433

Swéb

Sw7
Sw8

SW9
TA

TBITVE
TBUF

= 000100
= 000200
= 000400

= 001000

002610

= 000014

002642

58-2914
67-3218
+67-3228
*49-2656
#30-2079
30-2054

59-2953
69-3328
67=-3304
83-3942

=67-3227

67-3303

60-2992
71=-3534

61-3019

62-3046

63-3078

64-3116

65-3149

#30-1954

76=3669

76=3665

76=3669

79-3740

17-1433
17-1433

17-1433
17-1433
17-1433
17-1433
17-1433
17-1433
17-1433

17-1433

#17-1433

= 040000
= 100000

z
= 000010

32-2113
41-2374
50=2662

#17-1433

Swi1é
SW15

SwWe
SwW3

SEQUENCE
123
CREF
vO01

342167
43-2423
52-2718

| SCPSW
SECND
SETADR
SHIFT
SIZE
| SRPSW
STACK
START

G 10

33-2127
42-2386
51=-2686

57-2881
66-3185
#30-1885
#30-1892
30-2073
#30-2045
#30-1992
#30-1884
#17-1433
17-1473

STKLMT

PAGE 8

#17-1433
#17-1433
#17-1433

#17-1433
#17-143%

#17-1433

#30-1889

69-3378

#30-1909

32=2116

#17-1433

54-2817
63-3092

55-2848
64-3133

34-2169

56-2866
65-3165

342174

57=-2890
66-3198

58=2924
67-3249

59-2963
67-3317

53=2761

60-3001
83-3937

53=2764

61-3028

54-2788

62-3061

————

CZDLDH

——————
i

—

CREATED BY

SYMBOL CROSS REFERENCE
SYMBOL
TBUFS8
TCLOCK
TCONS

VALUE
=

| TCSR
!

————————

MACRO

———

ON 7=JuL=-81 AT 15:10

REFERENCES
#69-3335
+69-3431
34-2216
#40-2373
30-2061
#30-2063

PAGE 9
124
SEQUENCE
CREF
vO1

H 10

#30-1908
33-2162
38-2275
39-2315

31-2099
34-2168
38-2276
39-2321

33-2129
34-2170
38-2281
39-2322

33-2140
34=2175
38-2282
39-2327

33-2141
34-2186
38-2291
392329

33-2146
35=2220
38-2293
50-2663

33-2147
35=2222
38-2295
50-2666

33-2157
35-2227
39-2304
50=2676

33-2159
38-2266
39-2314
50-2684

53=2759
57-2882
63-3096

53=2760
57-2884
63-3103

53-2762
58-2920
63-3109

53=2771
592961
63-3114

54=2785
60-299%
64-3130

54-2805
61-3026
64-3132

54-2815
62-3058
64-3136

55-2846
62-3062
65-3152

56-2864
63-3090
67=-3240

TCSRS8

#69-3334

69-3429

#69-3484

TTMMP?

#30-1902

*30-2016

*30-2020

30-2040

70-3528

72-3543

52=2751

67-3226

67-3230

67-3302

51-2687

67=-3242

TIMER
TKVEC
TMP1
TMP3

TOLER
TPSW
TPVEC

TRAPVE
TRTVEC
TSTDEV
TSTDWM
ST
1ST10

= 000064

= 000034
= 000014
004050
003646
004172
005044

69-3466

*30-2059

+30-2075

#20-1903

«30-2058

30-2072

49-2646
#30-1913
#17-1433

#17-1433
#17-1433
30-2062
#30-2018
30-2069
#38-2253

ST
TST32
1ST33
TST34
1S735
15736

TST37

=30-2074

+30-2080

52=2721

522723

+30-1967

#30-2072

#31-2096

72=354¢€

41-2375
42-2387

#42-2386
#43-2423

44-24 )59

44-2459

442477

45-2483

007054

47-2569

47=2569

007410
007520
0C7646
010012
004316
010156

49-2624
#51-2686
#52-2718
#53-2753
#33-2127
#54-2781

49-2624

005252

#39-2298

#64-2458

TST24
1ST2S
TST26
1S127
7ST3
TST30

*30-2082

*30-2011

«30-1967

005614
005764

006262
004244
006522

006720
007222

010462
010554
010700
011102
011304

011512

01165¢

#32-2112
46-2531

48-2595

#55-2844
#56-2859
#57-2881
#58-2914
#59-2953%
#60-2952
#61-3019

#L5-2482

#46-2530

46-2531

#47-2568

48-2595

#49-2623

#48-2594

49-2660

52=2719

30-2081

+30-2001

70-353%2

006154

1S123

WL59-2648
30-2067

83-3936

30-2077

TST16

TST22

+30-1993

51=-2704

30-2023
30-2095

#40-2335
#61-2374

67-3315

69-3447

005404
005¢44

TST17
1S12
T1ST20

67-3258

51=-2694

69-3428
#17-1433
#30-1901

TST12
TST13
TST14
TST1S

51-2692

#50-2662

522726

52-2728

52=2744

53-2754

| CZDLDH

(REATED BY

| SYMBOL

CROSS REFERENCE

SYMBOL
[TST4

MACRO

ON 7=JuL=81 AT 15:10

REFERENCES
#34-2167

#62-3046

TST40
TST4T
TST42
TST43
TST44

TST4S
TST46

PAGE

110

125
SEQUENCE
vO1
CREF

62-3056
63-3088
64-3120

#64-3116

64-3128

#65-3149

66-32197

66-3212

#67-3218

39-2300
51-2705
67-3223
34-2212

39-2301
51=2717
67-3229

39-2334
52=2720
67-3299

#63-3078

1ST1S

1ST6

#37-2244
#30-1935S
#30-1934
#30-1937
#30-1936
#30-1912

1817

TURBUF
TURCSR
TUTBUF

TUTCSR
TVECT

51-2691
53-2778
34-2210

TYPE

TYPOC
TYPON

TYPOS

VCTADR
VCTTBL
VECT

WACTV
WAIT

WRAP
WRPSW

wT
XCONT
XMIT
XMTCNT
XRET

$APTHD
$ASTAT
SATY(
$ATY1

104402
104404
104403

003670
002742
004152
010230
017732
010362
013640
014502

010316
013604
013542
002442

013610
000500
LA R 2

$ATY3
$ATYSL

015722
015676
015704
015714

$AUTOB
$BASE
$8DADR
$8DDAT
$CHARC

001034
001142
001022
001026
016504

74-3618
79-3740
74-3618

#80-3745
#80-3745

30-2014

#30-1932
#30-2091
#54-2789
#81-3789
#54-2818
#69-3357

39-2302

48-2596

53-2755
61-3032

#54-2806

50-2664
52=2722

50-2665
52-2737

50-2675
52-2750

50-2685
53-2757

51-2690
53-2758

73-3590
78-3735
79=3740
#80-3745

764-3618
78-3736
79-3740

74-3618

764-3618
79-3740

74-3618
79-3740

45-2506

58-2940
#72-3551

46-2537
51-2706
59-2977

46-2553
52-2724
60-2994

472570

58-2916
67-3250

45-2484
50=-2668

52-2738
60-3006

47-2584
53-2755
61-3021

*67-3244

67-3264

»67-3307

83-3945

32-2124

33-2137

33-2154

34-2183

34-2196

38-2272

38-2288

32-2124

33-2137

33-2154

34-2183

34-2196

38-2272

38-2288

73-3595

79-3740

79=3740

79-3740

*43-2435

*43-2436

43-243%7

*43-2439

43-2440

43-2441

43-2444

83-3941

+78-3735

78-3735

«78-3735

#78-3735

74=-3618
79-3740
74-2618

#30-2028

30-2028
30-2094
54=2792
81-3790
54-2821
70-3530
40-2339
4£8-2610

57-2888
67-3221
54-2808

67-3314
67-3229

#67-3317
#67-3307

67-3316

#67-3318
#19-1480

#30-1881

19-1480

31-2107

77-3679
#77-3677
#77-3678

31-2107

#77-3680
#21-1482
#21-1482
#21-1482
#21-1482
*78-3735

#77-3681

78-3735

30-1943

*63-3098

71-3534
75-3658
79=3740
79-3740

79-3740
#80-3745

30=-2090

81-3793
42-2391
48-2621

30-1997

*65-3176

30-2005

*66-3215

51-2688
59-2959

*67-3295

83-3943

83-3944

CREATED BY
CROSS REFERENCE
VALUE

MACRO

ON 7-JuL-81 AT 15:10

REFERENCES

PAGE 11
SEQUENCE
126
CREF
V01

016736
001000
= 000000
017473
017466
001114
001063

#79-3740
#21-1482
#21-1482
79-3740
79-3740
#21-1482
#21-1482

80-3745
30-1967
21-148¢2
#79-3740
#79-3740

80-3745
30-19¢7

73-3590

74-3618

001076
001144
014406
014376
014356
014412
001106
001107
014326
014350
001003
001015

#21-1482
#21-1482
71-3534
18-1478
30-1967
#71-3534
#21-1482
#21-1482
49-2661
*30-1967
#21-1482
#21-1482

+30-1958
+30-1994
71-3534
#71-3534
#71-3534

+30-2000
#71-3534
73-3610

014544
001016

001146
014726
001012
001060
001106
001146
001070
016142
001056
001055
001020
001024
014366
017006
000500
001004
015356
001035
0C1014
001064
016141
001006
001010
001120
001124
001130
001134
001066
001116

79-3740

30-1967
#21-1482
83-3939
#22-1482
73-3589
#21-1482
#21-1482
#21-1482
19-1480
#21-1482
*77-3677
#21-1482
#21-1482
#21-1432
#21-1482
#71-3534
#79-3740
#19-1480
#21-1482
75-3626
#21-1482
#21-1482
#21-1482
*77-3718
#21-1482
#21-1482
#21-1482
#21-1482
#21-1482
#21-1482
16-1480
#21-1482

79-3740

30-1985
30-1967
69-3391
#71-3534
+73-3580
*30-1967
#73-3579
+73-3584
83-3940
74-3618
#74-3618
+73-3583
+30-1967
#21-1482
*30-1954
«77-3680
78-3735
78-3735

30-1967

74-3618

78-3735

34-2208

+70-3527
+30-2003

70-3528
*30-2010

*72-3542

30-2060

30-2072

73-3592
30-1987
#71-3534
71-3534
76-3669
*76-3669

77-3686
77-3688

77=3710
78-3735

78-3735
78-3735

76-3669
76-3669

*76-3669
76=3669

76-3669

#73-3585
83-3941

73-3586
83-3942

83-3943

74-3618

83-3936

73-3606

73-3608

*76-3669

*77-3717
78-3735

#77-3725

43-2435
+65-3175

43-2437
*66-3214

*67-3296

43=2442

83-3941
83-3944

78-3735

79-3740
74-3618
79-3740

79-3740

75=-3660
73-3605

*76-3669
76-3669

*76-3669
*76-3669

76-3669
76-3669

#21-1482

30-1967

76-3669

78-3735

79-3740

*43-2432
*43-2440

+77-3714
77-3708
78-3735
78-3735
*43-2434
43-2444

80-3745

75-3644
79-3740
+73-3586

#75-3662
79-3740
73-3594

78-3735
#77-3724
*30-1967
*30-1967

19-1480

J 10

82-3825

74-3618

30-2017

83-3944

83-3945

76-3669
76-3669

83-3937
83-3946

76-3669

78-3735

83-3938

CREATED BY

CZDLDH

SYMBOL CROSS REFERENCE
VAL UE

001122
001126
001132
000502

016140
01751
001102
001104
001066
017500

SMSGTY
SMTYP1
SMTYP2

SMTYP3

SMTYP4
$NULL
SNWTST

001117
001123
001127
001133
001054
= 000001

MACRO

ON 7=JuL=-81 AT 15:10

SEQUENCE

REFERENCES

#21-1482
#21-1482
#21-1482
#19-1480

«77-3678
79-3740
#21-1482
#21-1482
#21-1482
79=3740

77-3684
#79-3740
«77-3694
+77-3699
+30-1955
#79-3740

«77-3719

77-3692

«77-3700

#21-1482
#30-2096

78-3735
30-2096

78-3735
#31-2096

78-3735
*31-2113

#462-2423

42-2423

#43-2423

#21-1482
#21-1482
#21-1482
#21-1482

#33-2167
#36-2244
#39-2335
#45-2530
#48-2623
#51-2718
#54-2844
#57-2914
#60-3019
#63-3116

33-2167
36=2244
39-2335

45-2530
48-2623
51-2718
54=-2844
57-2914
60-3019
63-3116

77-3712

*77-3715

#68-3328

31-2113
34-2219
37-2253
40-2374
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#32-2113
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=78-3736

*x78-3736

#78-3736

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71-3534

79-3740

79-5740

79-3740

#75-3655

+75-3656

#75-3664

#17-1465
17=1465
30-1967

17=1465
#17-1465
30-1967

#17-1465

17-1465
30-1967
30-1967

#17-1465

#34=2167
W37-2244
#40-2335

#34-2219
W37-2253
#440-2374

w46-2530
wL9-2623
#52-2718
#55-2844
#58-2914
#61-3019
#64-3116

#46-2568
#49-2662
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#55-2859
#58-2953
#61-3046
#64-3149

66-3218
+78-3736
«78-3736
76-3669
+30-1967

015272
015346
015264
001062
017220

75-3659
30-1967
#75-3659
75-3636
#21-1482
#79-3740

#75-3665
#75-3626

75-3653

#75-3644
78-3735
80-3745

78-3735
80-3745

017350

#79-3740

80-3745

= 000010
014410

#79-3740
#71-3534

79-3740

015362
015374
= 000137

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30-1967
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17-1465
30-1967

75-3645
#76-3669
17=1465
#17-1465
30-1967

000506
015364

=
=

ARRRER

fARRAN

EERRRR
KERRRE

#19-1480

80-3745

#77-3723%

77=3697

#66-3218
»78-3736
«78-3736
76-3669
#21-1482

016732
016734
015660
001074

PAGE 12
127
vO1
CREF

#67-3218
#78-3736
78-3736
#76-3669
34=2206

#43-2458

#32-2127
#35-2235
#38-2298
#41-2386
#44-2482
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32-2127
35-2235
38-2298
41-2386

44-2482
47-259
50-2686
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56-2881
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#33-2127
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17-1465

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71-3534

80-3745
80-3745

76-3669

79-3740

30-1967
30-1967

30-1967

r__'_._ —

CZDLDH

CREATED BY

SYMBOL CROSS REFERENCE
VALUE
= 177777

SYMBOL
$STUP

$SVLAD
$SVPC

$SWR

015624
000500

161000

MACRO

ON 7-JUL-81 AT 15:10

REFERENCES
#17-1465
#17-1465
#17-1465
#17-1465
76-3669
76=-3669
#18-1478
18-1478
#17-1439
21-1482

31-2096
40-2335
49-2623
58-2914
67-3218

76=-3669

$SWREG
$SWRMK
$TESTN

001110
000000
001072

$TKB

001046

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001044

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76=-3669
#21-1482
76=-3669
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83-3941

#21-1482
79-3740
#21-1482
79-3740
#17-1438
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41-2386
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32-2113
412374
50-2652
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69-3328
76-3669
76~=3669

30-1967
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83-3942

78-3735
79-3740
78-3735
79-3740

30-2096
33-2167

$TPB

$TPFLG
$TPS
$TRAP

$TRAP2
$TRP

001052
001057
001050
017522
017544
000011

$TRPAD
$TSTM
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017556
000504
001002

$TTYIN
$TYPBN
$TYPDS
$TYPE

017456
AR ARN

L2222
4

016144

17-1465

#17-1465
#17-1465

17-1465
17-1465

#17-1465
#17-1465

17=1465
17-1465

21-1482
33-2127
4£2-2386
51-2686
60-2992
71-3534

21-1482
34-2167
43-2423
52-2718
61-3019

30-1967
35-2219
44-2458
53-2753
62-3046

30-1967
36-2235
45-2482
54-2781
63-3078
71-3534

30-1967
37-2244
46-2530
55-2844
64-3116
71-3534
76-3669
76-3669

30-1967

30-1967
39-2298

17=1465
#76-3669

76-3669
76-3669

71-3534
76=3669
76-3669

76-3618

«76-3669

78-3735

83-3943
78-3735
79-3740
31-209¢

34-2167
37-2244
40-2335

52-2718
55-2844

#51-2686
#54-2781
#57-2881

58-2914

61-3019
64-3116
67-3218
78-3735
78-3735
78-3735

#80-3745

80-3745
80-3745
80-3745
80-3745
80-3745

L 10

128
SEQUENCE
VvOI
CREF

#42-2386
442482
47-2568
#49-2623

46-253148-2623

PAGE 13

80-3745
80-3745

71-3534
76-3669
76-3669

76-3669
76-3669

83-3938

83-3939

83-3940

78-3735

79-3740

78-3735

79-3740

#31-2096
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#37-2244
#40-2335
42-2387

31-2113
34-2219
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32-2113

#32-2113
#35-2219
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41-2374
#43-2423
45-2530
48-2594
#50-2662
#53-2753
#56-2859
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#62-3046
#65-3149
#69-3328

32-2127
35-2235
38-2298

33-2127
36-2235
39-2298
41-2375

45-2482

#47-2568
49-2624
#52-2718
#55-2844
#58-2914
#61-3019
#64-3116
#67-3218

78-3735
78-3735
78-3735

80-3745
80-3745
80-3745

*4(0-2373
42-2423
#45-2482
47-2569
49-2662

52-2753
55-2859
58-2953
61-3046
64-3149
68-3328

69-3328

#41-2374
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46-2530
#48-2594

65-3185

44-2458
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48-2595
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57-2881
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66-3185

78-3735

80-3745

80-3745
80-3745

80-3745
80-3745
80-3745

80-3745
80-3745
80-3745
80-3745

#80-3745

80-3745
80-3745
80-3745

#80-3745

80-3745
80-3745

#80-3745

80-3745

#80-3745

76-3669

*76-3669

76-3669

#80-3745

80-3745

#80-3745

*70-3526

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73-3582

79-3740

*40-2373
76-3669
79-3740

79-3740

#79-3740

77-3705

#78-3735

80-3745

80-3745
80-3745

76-3669
76-3669

66-3185

83-3937
83-3946

80-3745
80-3745

#21-1482
76-3669

65-3149
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482594
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83-3936
83-3945
78-3735

#80-3745

76-3669

47-2568
56-2859

83-3944

80-3745
80-3745
80-3745

#19-1480

76-3669

38-2253

CZDLDH

CREATED BY

SYMBOL CROSS REFERENCE
SYMBOL
VALUE
STYPEC
$TYPEX
$TYPOC
$TYPON
$TYPOS

MACRO

ON 7-JUL-81 AT 15:1OS

REF ERENCES

m10

129
EQUENCE
CREF
vO1

78-3735
78-3735

#78-3735
#78-3735

79-3740

*30-2076

*30-2079

*72-3548

*30-1963

65-3169

66-3208

78-3735

79-3740

71-3534
»78-3736

78-3736

#78-3736

78-37

5
*30-1959

30-19%1
30-2029
78-3735

#19-1480

PAGE

19-1480

80-3745
80-3745

CZDLDH

CREATED BY

MACRO

MACRO CROSS REFERENCE
MACRO NAME
REFERENgES

CLKTST
COMMEN
CTESTS
DISMNT

#17-137

#17-1433
#17-1386
#17-1399

54-2843

ENDCOM
ENDPAS
ESCAPE
GETPRI
GE TSWR
T
MUL
NEWTST

ON 7=JuL-81 AT 15:1OSE

#41-2375
#40-2373

34-2180
55-2852
60-3004

#17-1433

39-2335

REPORT
SETPR]
SETTRA
SETUP
SKIP
SLASH
SPACE
STARS

$$CMRE
SSCMTM
$$FSCA

W45-2483

#46-2531

34-2193
56-2877
62-3066

34-2203
57-2893
63-3104

53-2775
57-2897
63-3110

54=2793
57-2907
63-3112

#47-2569

#48-2595

#469-2624

542822
58-2934
65-3177

54-2830
58-2944
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55-2847
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31-2113

41-2386

32-2127

42-2423

33-2167

43-2458

34-2219

44-2482
54-2844

64-3149

35-2235
45-2530
55-2859
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36-2244

46-2568

51-2718
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52-2753
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56-2865
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57-2885

58-2921

59-2962

60-3000

61-3027

53-2781
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56-2881
66-3218

#33-2137

#33-2154

#34-2183

#34-2196

#38-2272

#38-2288

#17-1433

80-3745

80-3745
30-1967

80-3745

#17-1433
#17-1433

17=1444

19-1480

21-1482
34-2167
39-2298
442458
49-2623
54-2781
59-2953
64-3116

21-1482
35-2219
40-2335
45-2482

31-2096
36-2235

#80-3745
#17-1433
#17-1433
#17-1433
#17-1433
#17-1433
#17-1433
#17-1433
#17-1405
#17-1371
#20-1482
#20-1482
#17-1433

30-2096
40-2374
50-2686
60-3019

#32-2124

51-2686
56-2859
61-32019
66-3185
75-3625

XMTDLY
$CLKTS

#46-2459

#31-2107

41-2374
46-2530

TYPBIN
TYPDEC
TYPNAM
TYPNUM
TYPOCS
TYPOCT
TYPTXT

#42-2387

54-2838
58-2948

#71-3534

POP
PUSH
RECDLY

SWRSU
TRMTRP

PAGE 15

QUENCE
130
vO1
CREF

32-2113
37-2244
42-2386
47-2568
52-2718
57-2881
62-3046
75-3641
79-3740

18-1478

32-2113
37-2244

42-2386
47-2568

43-2423
48-2594

75-3643

76-3669

52-2718
57-2881
62-3046
67-3218

79-3740
#30-1967

#30-1967

74-3618

79-3740

#34-2218

#53-2780
42-2387

#54-2797

41-2375

33-2127
38-2253

80-3745

44-2459

81-3754

34-2167
39-2298
44-2458
49-2623
54-2781
59-2953
64-3116
71-3534
77-2675
82-3807

46-2531

47-2569

53-2753
58-2914
63-3078
69-3328
81-3749

#62-3077

45-2483

73-3567
78-3735

68-3328
62-3059

21-1482
35-2219

40-2335

79-3740

82-3813

48-2595

37-2253

47-2594
57-2914

49-2624

CZDLDK

CREATED BY

MACRO

ON 7=JUL-81 AT 15:10

MACRO CROSS REFERENCE
MACRO NAME

SENEWT

$ESET
$$SETTM
$$SKIP
.EGUAT

REFERENCES

#17-1428
38-2298
48-2623
58-2953

.EQUIV

#80-3745
#30-1967
#17-1433
#17-1432
#17-1391

.SETUP

17-1433
#17-1429

LBACTT

.$APTB
.SAPTH
.SCMTA
.SEOP
.$ERRO
.SERRT
.SREAD
.$SCOP
.STRAP
.STYPE
.$TYPO

17-1433

#17-1430
#17-1430
#17-1430
#17-1431
#17-1431
#17-844
#17-1289
#17-1431
#17-1025
#17-1428
#17-1428
#17-1428

#17-1433
39-2335
49-2662
59-2992
#80-3745
#30-1967

#17-1433
#17-1429
I

17-1433

17-1433
#17-1465

18-1478

#21-1482
#19-1480
#20-1482
71-3534
#74-3618
79-3740
76-3669
#80-3745
78-3735
#78-3736

PAGE 16
SEQUENCE 131
CREF
vO1

B 11

30-2096
40-2374
50-2686
60-3019
w80-374S

31-2113
41-2386
51-2718
61-3046
#80-3745

32-2127
42-2423
52-2753
62-3078
#80-3745

33-2167
43-2458
53-2781
63-3116
#80-3745

34-2219
44-2482
54=-2844
64-3149

w80-3745

35-2235
45-2530
55-2859
65-3185
#80-3745

36=2244
46-2568
56-2881
66-3218
#80-3745

37-2253
47-2594
57=2914
68-3328

17-1433
17-1433

17-1433
17-143%2

17-1433
17-1433

17-1433

#21-1482

17-1433