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Document:	ADV11-A, KWV11-A, AAV11-A, DRV11 User's Manual
Order Number:	EK-ADV11-OP
Revision:	002
Pages:	96
Original Filename:

OCR Text

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EK-ADV11-OP-002

ADV11-A, KWV11-A,
AAV11-A, DRV11
user's manual

digital equipment corporation e maynard, massachusetts

st Edition, July 1976
2nd Printing (Rev) November 1976
3rd Printing (Rev) April 1977

The material in this mannal is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION

1.1
1.2

GENERAL
. . . .
e e e e e
e
e
REFERENCES
. . . . . . . . . .
o oo e

CHAPTER 2

ADV11-A ANALOG-TO-DIGITAL CONVERTER

2.1

GENERAL DESCRIPTION
. . . . . . .
e e et e e e e e e e e
SPECIFICATIONS
. . . . . . . .. ... .... [
Electrical . . . . . . . .
e e e e e e e e e e e e e e
Coding
. ... ... e
e e e e e e e e e e e e e e e e
e e
e
Performance
...
. . e
e e e e
e e e e e e e e e e e e e e e

2-1
2-1
2-1
2-2
2-2

Test Signals
. . ... . . ..
Power Requirements . . . .
FUNCTIONAL DESCRIPTION .
Channel Selection
. . . . .

2-3
2-3
2-3
24

2.2

2.2.1
2.2.2
2.2.3

224
2.2.5

2.2.6
2.3

2.3.1
2.3.2

2.3.3

2.3.4
24

2.4.1
2.4.1.1
24.1.2
2.4.2

2.4.2.1
24.2.2

2.4.2.3

2.4.3

Timing

. . . . . o

A/D Conversion

e e

..
. .
. .
. .

e e e

e eI

... e
e e e e e e e e e e
e
. . . . .. ..o
. . . .
e i e d e e e e
. . .
e
e
e e e

Interface Functions

. . . . . . ... ... e

2.4.3.2

2.5.3

External and Clock Starts
Mode Control . . . . . .
Vector and Address Selection
PROGRAMMING . . . .
e o
Control/Status Register (CSR)
Data Buffer Register (DBR)
.
Programming Example . . . .

CHAPTER 3

KWV11-A PROGRAMMABLE REAL-TIME CLOCK

3.1

GENERAL DESCRIPTION . . . . .. ...
. e
e e e e e e e e e e
SPECIFICATIONS
. . . .
e e e e e e e e d e e
e
e
Clock . . . . .
e
e e e e e e e e e
e
Input and Output Signals
. . . . . e
e e e e e e e
Input Signals
. . . ... . .. ..o 0oL PO
Output Signals = . . . . . . . . . ...
o Lo
Power Requirements (from LSI-11 Bus Power Supply) . . . . ...

2.5

2.5.1
2.5.2

3.2

3.2.1
3.2.2

3.2.2.1
3.2.2.2
3.2.2.3

2-6

Control . . . . ... . .... e
e e e 2-6
USER INTERFACING
. . . . .
e
e
e
e e e e e s s s e e e e 2-6
Analog Inputs
. . . . . . . . L 2-6
Single-Ended Mode . . . . . . . . . ... e
e e e 2-6
Quasi-Differential Mode
. . . . . . . .. ..o o000 - 2-7
Avoiding Spurious Signals
. . . . . . . .. e
e e e e e e e e e e 2-9
Twisted Pair Input Lines
. . . . . . . ... .. .. ... . 2-9
Shielded Input Lines
. . . . .. .. ... ... e e e e e . 2-11
Allowing for Input Settling with High Source Impedance
. . . . . 2-11
Connections
. . . . . . . . ..o e e e e e e e e e e 2-11

Distribution Panel

2.4.4

2-3

. . . . . SR e 2-4

2.4.3.1
2.4.3.3

1-1
1-1

. . . . . . . . .. ... ... J

.
.
.
e
.
.
.

. . . . . .. e e L.
. . . .o
e e e e
. . . . . . . . ... e e
e e e e e e e e e e s
e e e e
. . . . . . . . .. . .. ... ...
. . . . . ... ... ... e
e e
. . . . ... 000000

2-11

2-11
2-12
2-12
2-14
2-14
2-16
2-17

3-1
3-1
3-1
3-1
3-2
3-3
3-3

CONTENTS (Cont)

3.3

FUNCTIONAL DESCRIPTION

3.3.1

Bus Control

3.3.2

Control/Status Register

3.3.3

Mode Control

.. e

e e e

.
e

oo,

e e

. .

3.3.3.1

‘Mode O (Single Interval)

3.3.3.2

Mode 1 (Repeated Interval)

...,

. .

... ... ... ..

....

. .

....

. . . .

3.3.33

Mode 2 (External Event Timing)

3.3.3.4

Mode 3 (External Event Timing from Zero Base)

3.3.3.5

Flag Overrun

. .

...

. . .

. . . . . . . . . . ... .. P

3.3.4

Oscillator, Divider, Rate Control Chain

3.3.5

Buffer/Preset and Counter Registers

3.3.6

Schmitt Triggers

3.4

. . . . . . . . . . . . . . .. ...

. . .

. .

. ee

. . . . . . . . . . . . . . .. ...

...

CONNECTORS, SWITCHES, AND CONTROLS

. .

...

3.4.1

40-Pin Connector

3.4.2

FAST ON Connectors (Clock Overflow and ST1 OQutputs)

3.4.3

Selector Switches (Address, Vector, and Slope/Reference Level)

. . . .

. . .

....

e
.

. .

. . .

3.4.3.1

Address Selection

. .

3.4.3.2

Vector Selection

. .

. .. e e

3.4.3.3
3.5

. . .

...

Slope and Reference Level Selector Switches and Controls
PROGRAMMING

3.51

CSR Bit Assignments

3.5.2

Buffer/Preset Register (BPR)

3.5.3

Normal Control Sequences

Mode O (Single Interval)

Mode1 (Repeated Interval)

. .

. .. .

. .

Mode 2 (External Event Timing)

Mode 3 (External Event Timing from Zero Base)
Programming Example

. . .

. . . . .

...
... .. e

CHAPTER 4

AAV11-A DIGITAL-TO-ANALOG CONVERTER

4.1

GENERAL DESCRIPTION

4.2

SPECIFICATIONS

4.3

FUNCTIONAL DESCRIPTION
Bus Control

4.3.2

Control Logic

4.3.3

DACs O, 1,and 2

4.3.4
4.4

DAC3

.
.

. .

. . .

...

. .

...

. . . . . .

o
.... e
. .

....

...

. .

. . ...

. . . . .. ...
.
e

e e

e,
e

e e

. .

. . . . . .

CONNECTORS, SWITCHES, AND CONTROLS

. .

4.4.2

Address Switches

. .

Mode/Level Selector

Jumpers

. .

e e

4.5.1

Ground Connections

4.5.2

Twisting

. .

...
.. ... e

. . .

...

... e
e

. . . . . . . . . ... ...

INTERFACING TO OUTPUT DEVICES
.

...

40-Pin Connector

4.5

. .

4.4.1

4.4.3

...

3.5.34

4.3.1

. . . . . . . . . . . ... .. .....

3.5.3.3

. .

. . . . . . . . . . . . . . .. ... ....
.

3.5.3.2

. . . . . . . . . . .. ... o

3.5.3.1

3.5.4

. . .

.
e

. .
e

.
e

. .

...

....

CONTENTS (Cont)
Page

4.5.3
4.5.4
4.6

Shielding . . . . . . . . .o
e
Drive Capability . . . . . . . o . o v o
e e e
e
e
e
e
e
e
e
s
e
e
h
e
e
e
e
o
o
.
.
.
PROGRAMMING

CHAPTER 5

DRV11 PARALLEL LINE UNIT

5.1

GENERAL DESCRIPTION

5.2

5.2.1
5.2.2
5.2.3
5.3
5.3.1
532
5.3.3
- 534
5.3.5
5.3.6

. . . . . o o o e e e e

JUMPER-SELECTED ADDRESSING AND VECTORS

e h e e e e e e

e e

. . . . ... ... ..

4-7
4-7
4-7

5-1

. . . . . . e e e e e e e e e e e e e e e e e e e e e e 5-1
Locations
e 5-2
e e e e e e
Addressing . . . . . . .o e
e e 5-2
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
o
VeEeCtOTS . v . e
5-3
........
INTERFACING TO THE USER’S DEVICE ..........
5-3.
e
e
e
e
e
e
e e e e e e e
General . . . . . .
o oo 5-3
Output Data Interface . . . . . . . . . . .
Input Data Interface . . . . . . . . . . .o 5-5
e .. 55
. . . . . .. ... «. ... .... e v
Request Flags
e 5-6
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
.
.
.
.
.
.
.
.
Initialization
NEW DATA READY and DATA TRANSMITTED Pulse
e e e e e e e e e
. . . . . .« . o
Width Modification

e e

5-6

6.1
6.2
6.2.1
6.2.1.1
6.2.1.2
6.2.1.3
6.2.1.4
6.2.1.5

o o oo o e h i e e e e
MAINTENANCE PHILOSOPHY ... . . . . .
ADV11-A ANALOG-TO-DIGITAL CONVERTER . . . . . . .. ... ...
Installation . . . . . . . e e e e e e e e e e e e e e e e e e e e e
e e e e e e e e e e e R
Location . . . . . . .
Address and Vector Selection . . . . . . . . .. ... oo
e e e
Board Insertion . . . . . . . . . . . oo o0 o oo e
e e e e e e e e e e e e
Test Connector . . . . . .. e
ShieldS . . . . . o o e e e e e e e e e e e e e e e e

6-1
6-1
6-1
oo |
6-1
6-1
6-1
6-1

6.2.1.7
6.2.2
6.2.2.1
6.2.2.2
6.2.2.3
6.2.3
6.2.4
6.2.5
6.3
6.3.1
6.3.1.1

. . . . . . . . . . . . .. e T e e e e 6-2
Final Connections
. . . . . . .« o o oo e 6-2
ADV11-A Circuitry
ADV11-A Analog Power Supply = . . . . . .. .. ... 6-2
ADV11-A A/D Conversion Circuit - . . . . . . . . . . .. ... .. 6-4
v v v v .... .. 68
The Vernier DAC . . . . . . . . . .
. ... ... . 68
DVADA-A)
(MAINDEC-11Test
Performance
ADV11-A
e e 6-10
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
o
.
.
Maintenance . . . . .
e e e 6-10
e
e
e
e
Calibration . . . . . . . o o oo e
KWV11-A REAL TIME CLOCK ........................ 6-10
6710
e e e e e e e
e
" Installation . . . . . e e e e e
e e e e e e e e e e e e e e e e 6-10
Location . . . . . . o

54
54.1
54.2
5.4.3
5.4.4

e e
PROGRAMMING . . . o o e e e e e e e e e e e e e e e e e e
Addressing . . . . .. S
. . . . . . .. Lo oo
Interrupt Vectors
e
e
e
Word FOrmats . .ov v v o e e e e e e e e e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
i
o
o
/O TIMINg . . . . .

CHAPTER 6

ADV11-A, KWV11-A, and AAV11-A MAINTENANCE

6.2.1.6

ACCEPLANCE

. v v v e e e

e e e e e ee

5-6
5-6
5-7
5-7
5-7

6-2

CONTENTS (Cont)
Page

6.3.1.2

Address and Vector Selection

6.3.1.3

Board Insertion

6.3.1.4

Test Connections

6.3.1.5

Acceptance

6.3.2

Final Connections

6.3.3

KWVI11-A Circuitry

.
.

. . . .

. ..

..., 6-10

6-10

...

6-10

. .

... 6-10

6-11

KWV11-A Diagnostic (MAINDEC-11-DVKWA-A-D)

6.4
6.4.1

...

... ..

.. 6-11

6-11
. .. ... ... 6-11

. . . . .

...,

6-11

..o,

6-11

. .

..o, 6-11

6.4.1.1

Location

6.4.1.2

Address Selection.

6.4.1.3

Board Insertion

6.4.1.4

Test Connectors

6.4.1.5

Acceptance Test

6.4.2

Final Connections

6.4.3

Mode/Level Selection

6.4.4

AAVI11-A Circuitry

... 6-11

. . ... 6-11
.

. . . . . . .| e

.. e

e e e

e 6-11

e e e 6-11

. . . . . . . ... 6-12
. .

. .

6-12

6.4.4.1

AAV11-A Analog Power Supply

6.4.42

Digital-to-Analog Circuits

.................. 6-12
.

. . .

6.4.5

AAV11-A Diagnostic Test (MAINDEC-11-DVAAA-A)

6.4.6

Maintenance

6.4.7

Calibration

AAV11-A DIGITAL-TO-ANALOG CONVERTER
Installation

.. 6-10

Maintenance

...

6.3.5

...

. .

6.3.4

...

. .

... 6-14

. .

. .. ..

.. 6-14

L 6-14

. .

... 6-16

ILLUSTRATIONS
Figure No.

Title

Page

2-1

ADV11-A Functional Block Diagram

2-2

Single-Ended Input Referenced to User’s Ground

2-3

Floating ADV11-A Input Signals .

. . . . . . . . . .
.

. .

. .. . .. ....

. . .. ..

. .. e

e e

...

2-5

...

2-7

2-8

2-9

2-4

Single-Ended Versus True Differential Input Modes

2-5

ADV1I1-A Quasi-Differential Mode

. . . . . .

2-6

ADV11-A Connectors and Switches

. . . . . .. . ... ... .. ...... 2-12

2-7

ADV11-A 40-Pin Connector Pin Assignments

2-8

H322 Distribution Panel

. . . . .

Module Jumpers

ADV11-A Address and Vector Switches

2-11

ADV11-A Control/Status Register (CSR)

2-12

ADV11-A Data Buffer Register(DBR)

3-1

KWV11-A Connectors, Switches, and Controls

3-2

KWV11-A Real-Time Clock Block Diagram

. .

(Rocker or Slide Switches)

...

. ... ...

.. ... ... ... .. 2-10

. . . . . . . . . . . .. .. .. 2-13

. .

.. .

. . . . ... ... ... 2-13

2-10

. .

L e, 2-14

. . . . . . . . . . ., 2-15

. . . . . . . . . .. . . ... ... 2-16
. . . . .. .. .. .. e e 2-16
.

. . .
. ...

.. . . ... ..

3-2

.. .. ... ... ...

. .

3-4

ILLUSTRATIONS (Cont)
Title

Figure No.

Page

3-3

Connecting External User-Supplied Slope and Level Controls

3-4

40-Pin Connector Pin Assignments

. . . . . . . ..

3-5
3-6
3-7

KWV11-A Slope/Reference Level Selector Switches and Controls

3-8

KWV11-A Slope Selection

CSR Bit Assignments

4-1

AAV11-A Block Diagram

AAV11-A Connectors, Switches, and Controls

. . . . . . . . . . . .. .. ...

3-6

3-7

KWV11-A CSR Address Switches (Set for 170420)

. . . . . P

3-7

KWV11-A Vector Address Switches (Set for 000440)

. . . . .. . . ... ..

3-8

. . . . . . . . . . . .

. . . . . . . . . . .

. o i

. . . . . .

v i

3-9

e 3-10

e i e e e e e e e e e e e e 3-13

. . . . . . . . . . . e

4-3

. . . . . . . . .. ... ...

4-4

. . . . . . . . . . . . . .. ...

4-5

4-3

40-Pin Connector Pin Assignments

4-4

AAV1T-A Address Decoding

4-5

5-3

AAV11-A Address Switches (Set for 17044n) . . . . . . . . . . . ... ...
Connection to Oscilloscope with Differential Input . . . . . . . . . .. . ..
DRVI11 Parallel Line Unit - . . . . . . . . . . . . . . . . . .o
DRV11 Jumper Locations . . . . . . . . . . . . . .o
DRV11 Device Address
. . . . ...
.. e
e e e ee
e e

4-6
4-7
5-1
5-2
5-3

5-4

DRV11 Vector Address

. . . . .. ... .... S

5-3

5-5

5-6

J1 or J2 Connector Pin Locations . . . . . . . . . . . . .. ... ... ...
DRVI11 Word Formats
. . . . . . . . . . . . e

5-4
5-7

4-6

5-1
5-2

. . . . . . . . o . e 4-6

5-7

DRV11 Interface Signal Sequence

6-1

Battery-Operated Potentiometer Box for ADV11-A A/ D Converter

6-2

Analog Power Supply Block Diagram

6-3

DC-DC Converter Signals

e e

6-4

Basic Positive Voltage Doubler
. . . . . . . . . . . . ... ...
ADV11-A A/D Conversion Circuit Block Diagram
. . . . . ... ... ...
A/D During Sample
. . . . . . . . ... [
A/D During Conversion
. . . . . . . . . i e
e e e e e e e e e e
2 Node During Conversion
. . . . . . . . o v v v v v b e e e e e e e
ADV11-A Troubleshooting Procedure . . . . . . . . . .. ... .. .....

6-4
6-5
6-5
6-6
6-7
6-9

6-5
6-6
6-7

6-8
6-9

. . . . . . . . . . . .. .

... ... .. 5-10

......

. . . . . . . . . ... ... ...,

. . . . . . . v v i i i

6-3
6-3

6-10

AAV11-A Troubleshooting Procedure . . . . . . . . . .. ... ... .. .. 615

6-11

Floatingthe DVM

. . . . . . . . . . . .

e e

e e e

e e 6-16

TABLES

Title

Table No.

3-1

KWV11-A CSR Bit Definitions

3-2

CSR Bit Settings for Mode O, Single Interval
. . . .
CSR Bit Settings for Mode 1, Repeated Interval . . .
CSR Bit Settings for Mode 2, External Event Timing
AAV11-A Digital-to-Analog Conversions
. . . . . .

3-3
3-4

4-1
5-1
5-2

Page

. . . .. . . P 3-11
.
.
.
.

.
.
.
.

. . .. ... ... 3-14
. . . . . ... .. 3-15
. . . . . ... .. 3-16
. o o
0.
4-8

DRV11 Input and Output SignalPins . . . . . . . . . . .. ... ... ..
Word Formats . . . . . . . . ...
oL e ..

Vil

5-5
5-8

TABLES (Cont)
Table No.

6-1
6-2

6-3

6-4

Title

Page

ADV11-A Voltage/Current/Bit Relationships . . . . . . . . ... .. .. .. 6-8
Jumper Configurations for Bipolar Operation . . . . . . .. . ... ... .. 6-12
- Jumper Configurations for Unipolar Operation . . . . . . . . PR 6-13
AAV11-A Input Code/Output Voltage Relationships . . . . . . .. .. . .. 6-13

viii

CHAPTER 1
INTRODUCTION

iI.1

GENERAL

This manual contains information necessary for the operation, installation, and maintenance of the

family of real-time analog and digital I/O devices which DEC provides as options for the LSI-11

Processor, i.e., the ADVI11-A Analog-to-Digital Converter, the KWVI11-A Real-Time Clock, the

AAVI11-A Digital-to-Analog Converter, and the DRV11 Parallel Line Interface. Operating information for each device is provided in a chapter specific to that device which includes functional descrip-

tion, specifications, theory of operation, and programming background. Installation and maintenance
information is provided for all units in Chapter 6.

All members of the LSI-11 real-time I1/O family are designed to interface between the processor and
analog or digital signals in the world external to the processor. All devices are configured on one quad
or double-height board designed to mount in an LSI-11 backplane or expander box and to receive
power from LSI-11 supplies. All communicate with the LSI-11 bus and receive interrupt priority as a
function of their location in the backplane. Finally, all have facilities to permit users to assign device
addresses, and where appropriate, interrupt vector locations.
A number of recommendations are made in this text regarding specific interfacing configurations and
general good practice. However, no specific interfacing claims are made over and above those
expressed in the general specifications for each module. The responsibility for connecting DEC modules to external equipment rests ultimately with the user.
1.2

REFERENCES

Microcomputer Handbook (EB-06583 76 09/53)
[SI-1] Bus Specification

1-1

CHAPTER 2

ADV11-A ANALOG-TO-DIGITAL CONVERTER

2.1

GENERAL DESCRIPTION

The ADVI11-A is a 12-bit successive-approximation analog-to-digital converter with built-in multiplexer and sample-and-hold for use on the LSI-11 bus. The multiplexer section accommodates 16
single-ended or 8 quasi-differential inputs, and the converter section utilizes a patented auto-zeroing
design that measures the sampled signal with respect to the offset of its own internal circuitry and thus effectively cancels out its own offset error contributions to the measurement.

A /D conversions are initiated either by program command, clock overflow, or external events as
determined by program control of the ADV11-A’s Control /Status Register (CSR). The clock overflow
command is supplied by the KWV11-A clock option. External event inputs may originate directly
from user equipment or from the Schmitt trigger output on the KWV1i-A clock. Digital A/D conversion data is routed through a buffer register to the LSI-11 for programmed transfer into memory.
This buffering optimizes the throughput rate of the converter by allowing data from one conversion to
be transferred to the processor after a subsequent conversion begins.
A vernier offset digital-to-analog converter is included in the ADV11-A’s analog circuitry to facilitate
very accurate program-controlled trimming of the A/D’s offset. Three test signals - two dc levels and
one blpolar triangular waveform
- are available for use on any channel input. The triangular wave can
be usedin conjunction with diagnostic software and the vernier DAC to produce extremely thorough
and precise analog testing.
2.2

SPECIFICATIONS

2.2.1

Electrical (@ 25° C unless otherwise specified)

Inputs

Analog Input Protection

Fusible resistor guaranteed to open at +£85 V within 6.25 secV to +15 V at the
onds. Guaranteed not to open from -20
input. Overload affects no components other than the fusible
resistor on the overloaded channel; no other channels are
affected.

Logic Input Protection
Analog Input
Full Scale Range (FSR)

Fusible resistor guaranteed to open at £ 25 V within 6.25 sec-

onds. Guaranteed not to open from -3 V to +8 V at the input.
10.24 V bipolar (-5.12 V to +5.12 V)

Enpfiflis (Cont)
Analog Input

100 M2, minimum

Dynamic Resistance

2.2.2

(/Vin/ < 5.12 V)
Analog Input Bias Current
(/Vin/ < 5.12 V)

50 nA, maximum

Logic Input Voltages

Low = 0.0 to +0.7 V: high = +2 V to +5 V

Logic Input Currents

Low = -6.8 mA at 0 V in.; high = +1.3 mA at +5 V in

Logic Input Rise/Fall Time

400 ns, maximum

Coding

A/D Converter
Resolution

12 bits, binary weighted

Format

Parallel offset binary, right justified

Input Voltage

+FS-1 LSB

0
-FS

Output Code

4000
0

(FS=5.12V;1LSB = 2.5mV)
Vernier D/A

Resolution

-8 bits, binary weighted

Format

Offset binary encoded
Input Code

Approximate Offset Voltage

377

+2.5A/D LSB (+6.4 mV)
0
-2.5A/D LSB (-6.4 mV)

200
0
2.2.3

Performance

Gain Error

Adjustable to zero

Oftfset Error

Adjustable to zero

Dufferential Linearity

No skipped states; no states wider than 2 LSB. 99% of state-

widths + 1/2 LSB
Integral Linearity

+1 LSB, maximum non-linearity (referenced to end points)

2-2

~ Performance (Cont)

Temperature Coefficients

Gain = 6 ppm per degree C

Noise

Module = 0.4 LSB rms; 2 LSB peak
System = 1/2 LSB rms; 2 LSB peak

Warm-Up Time
2.2.4

Linearity = 2 ppm of full-scale range per degree C
Offset = 7.5 ppm of full-scale range per degree C

5 minutes, maximum

Timing

External Start

Low level pulse, 50 ns minimum to 10 us maximum; conversion

starts on leading edge

Synchronization

OtoT

Conversion Time

16T
(T = clock period = 2.14 us + 6%)

Transition Interval*

Ous £ 12%

Sample and Hold

Aperture Delay = 200 ns
Aperture Uncertainty = 2 ns

2.2.5

Test Signals

The ADV11-A provides three output voltages for test purposes:
1.

Positive dc level, +4.4 V (£15%)

Negative dc level, -4.4 V (£15%)

Triangular wave, 15 Hz nominal (£ 15%)

2.2.6

Environmental (Ref: DEC STD 102, class B)

2.2.7

Power Requirements

+5 Vdc £5% @2.0 A, maximum
+12 Vdc £3% @450 mA, maximum
2.3

FUNCTIONAL DESCRIPTION

The ADV1I1-A performs its function in seven successive steps:
1.

It enables the specified channel.

It samples 1 of 16 single-ended (or 1 of 8 differential) analog input channels specified by the
control program long enough to acquire a reliable internal reference equivalent.

It accepts a command to perform an A/D conversion.

It holds the sampled reference equivalent during 12 successive interrogation intervals.

*Reacquisition interval between end of conversion or channel change and start of new conversion.

2-3

When the least significant bit has been resolved in the Successive Approximation Register

(SAR), the ADV11-A transfers the contents of the now-filled SAR to the DATA Buffer
Register (DBR) where that data can be accessed by the processor.
6.

It informs.the processor that conversion data is available.

It reacquires and tracks the programmed channel.

These steps are implemented in the ADV11-A by components that can be grouped together in four
functional categories:
1.

Channel selection

A/D conversion

Processor/ADV11-A interface

Control logic that coordinates the above steps with respect to one another and to the needs
of the processor.

These categories are discussed below.
2.3.1

Channel Selection
.
Channel selection is accomplished under program control by two 8-channel multiplexers and is a

function of the data asserted in bits 8 through 11 of the Control /Status Register (CSR). Each of the 16
analog input channels is routed to the single output channel through a MOS field-effect transistor
which acts as a normally-open switch. During the sample interval, the data pattern in CSR bits 8
through 11 selects one of these transistors and causes it to change from a condition of nearly infinite
resistance (1 G{l or more) to one of very low resistance (1000 © or less). Since in the selected state the
transistor conducts current within the £5.12 V limits equally well in both directions, it now functions
as a closed switch, effectively routing to the output line whatever analog signal is connected to its
input.

2.3.2

A/D Conversion

A/D conversions can be initiated in three ways: under program control, on overflow from the
KWVII-A Real-Time Clock, or on external input. When a conversion is completed or the control
program writes a multiplexer address into the CSR, the control logic initiates the Transition Interval a delay of about 9 us to allow the multiplexer adequate selection and settling time and to permit a valid
representation of the signal level to be established in the sample circuit. If no A/D Start signal has
occurred by the time the Transition Interval has elapsed, the sample circuit merely follows the signal
transmitted to 1t through the selected multiplexer channel and waits for an A /D Start signal. When an
A /D Start signal occurs - or at the end of the Transition Interval if A /D Start was previously generated by the writing of the CSR GO bit - the sample and hold circuits are switched to hold, sustaining
the sampled level for the next step. The multiplexer output is then set to its hold condition, i.e., to
ground if the single-ended (S.E.) input is set low for single-ended measurement, to the second differental input (return line) if the S.E. input is not set low. Note that if an external or clock start signal occurs
during the Transition Interval, conversion starts immediately without waiting for the Transition Interval to be completed. Bit 15 of the CSR (AD ERROR) is set, however, and an interrupt is generated if
bit 14 (error interrupt enable) is set — alerting the program that conversions are occurring too fast and
are consequently liable to be in error.

2-4

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Under normal conditions, it is not until the Transition Interval is complete that the measurement
process is begun. The Successive Approximation Register (SAR) is cycled through 13 states by the
clock. In the first state its output code involves only the most significant bit (MSB) of the 12-bit SAR

word. This output code causes the feedback digital-to-analog converter (DAC) to generate an output

equivalent to that produced by the hold circuits in response to a sample voltage of 0. The DAC output
is summed with that produced by the hold circuits and with that coming from the grounded multiplexer output (single-ended mode) or from the second differential input (quasi-differential mode). If
the current from the summing node is negative, the first approximation was too low, and the comparator signals the SAR to maintain the state of bit 11 and repeat the process with bit 10. If the current
from the summing node is positive, the first approximation was too high and the SAR changes the
state of bit 11 before cycling into the second approximation. This process continues until all 12 bits in
the word have been set, tested, and if necessary, changed. The 13th state (end of conversion, or EOC)
indicates that the measurement is complete and that the SAR now contains an offset binary equivalent
of the sampled voltage and may therefore be transfered to the processor. EOC causes the sample and
hold circuits to return to the sample mode and to reset the SAR, preventing further SAR activity until
the occurrence of the next hold condition,

Note that because the reference point against which the sample voltage is compared is at the output of
the multiplexer itself rather than internal to the sample and hold circuits, all offset voltages generated
by the intervening circuits are common to both sample and hold conditions and are therefore cancelled
out of any measurement. In single-ended mode, grounding the multiplexer output (and thereby establishing this reference point) is identified as auto-zeroing the converter.

2.3.3

Interface Functions

In addition to stopping the SAR clock and reestablishing the sample mode, the end-of-conversion
signal also initiates the process that causes the SAR data to be transferred to the processor. Since this
operation takes a finite amount of time which would interfere with subsequent measuring operations,
the SAR data is first transferred to a holding device, the Data Buffer Register (DBR), where it will
remain until the processor can be notified to read the conversion data for processing. In the meantime,
the channel selection and A /D conversion circuits can begin the next measurement as dictated by
Control/Status Register (CSR) bit conditions controlled by the processor.

Included in the ADV11-A interface is an extension of the DBR designed to accept 8-bit write information from the BUS DATA/ADDRESS lines. This buffer permits programmed setting of the Vernier
DAC (see Paragraph 6.2.2.3). Also included are transceivers that connect the bi-directional BUS
DATA lines to the LSI-11 Bus DATA/ADDRESS lines. Associated with these transceivers are switches that permit assigning device and vector addresses to any given ADVI11-A.

2.3.4

Control

As the above discussion suggests, a large number of signals must be precisely orchestrated each time
the ADV11-A executes a conversion. The control logic contains an assortment of gates, latches, readonly memories, and timing circuits designed to assure that multiplexer channels are properly selected,
sample durations are of adequate length, conversions are not initiated during uncompleted previous
conversions, etc. In general, this logic precludes the need for the user to attend to any but the most-

elementary details of the conversion process, e.g., making necessary connections to the system and
writing control programs that make appropriate use of the CSR.

2.4
2.4.1

USER INTERFACING
Analog Inputs

2.4.1.1 Single-Ended Mode* - Single-ended analog input signals for the ADVVI11-A may be of two
types, grounded and floating. A grounded input is one whose level is referenced to the ground of the
instrument that is producing it, as illustrated in Figure 2-2. Since the instrument may be located at a
*The ADV11-A is factory-set for differential mode. Single-ended mode must be selected as described in Paragraph 2.4.3.3.
2-6

distance from the computer, there may be some voltage difference between the instrument ground and
the computer ground. The voltage seen by the ADV11-A will be the sum of the undesired ground
difference voltage and the desired instrument signal voltage. In cases where such differences are
encountered, they can be minimized by plugging the instrument into an ac outlet as close as possible to
that providing power to the computer. Do not run a wire from user’s ground to the ADV1 1-A analog
ground. Such a wire can cause ground loop currents which affect results not only on the input channel
'

in question, but also on other channels.

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11- 4166

Figure 2-2

Single-Ended Input Referenced to User’s Ground

A floating input is one whose signal voltage is developed with respect to a point not connected to

ground, as illustrated in Figure 2-3. The identifying characteristic of a floating source is that connecting the signal return to the ADV11-A ground does not result in a current path between the
|

ADV11-A ground and the instrument ground.

Note that the return of a floating input must be connected to one of the ADV11-A’s analog ground
terminals (see Figure 2-3). Ground points may be shared among channels, as illustrated by the batterypowered sources in Figure 2-3.

2.4.1.2 Quasi-Differential Mode - The “quasi” prefix in “quasi-differential” can best be explained in
the context of a preliminary review of true differential operation. A true differential input involves two
signal lines connected to a differential amplifier in such a way that the output of the device is a function
of the instantaneous difference between the voltages on the two signal lines. One advantage of such a
configuration is illustrated in Figure 2-4.

Figure 2-4(a) assumes a single-ended generating device that produces a signal, Vs, with respect to its
ground and is situated sufficiently far from the receiving device for a significant noise voltage, Vp, to be
developed in the power distribution ground lines. The result is that, at any given instant, the differential amplifier in the receiving device sees both the signal voltage and the noise voltage. Its output, Vo, 18
a function of Vg + V, and is in error with respect to V; alone.
2-7

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A AN

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Floating ADV11-A Input Signals

Figure 2-4(b) illustrates the same device connected in true differential mode. The same noise voltage
exists in the power distribution ground system, but this time the generating device ground is connected
directly to the negative input of the receiving differential amplifier. Since the instantaneous noise
voltage is common to both the + and the - inputs, it is cancelled out of the final amplifier output. V,

now provides a valid representation of Vg alone.

Figure 2-5 illustrates the ADV11-A operating in the quasi-differential mode.

The major contrast between true differential operation as described above and the operation of the
ADVI11-A in differential mode is that in the latter, the two sides of the signal are not simultaneously
input to a differential amplifier. Rather, their difference is established by a sequential operation that

first samples the voltage at one of the two inputs and then, holding this value fixed, in effect subtracts
from 1t the voltage at the second input. For near dc conditions, this procedure produces a result like
that of true differential operation - that is, the output is a function of the difference between the two
input voltages, and common mode voltages are cancelled out. But, since there is a significant time
lapse between taking the sample and completing the final approximation, a possibility for error is
introduced by the ADV11-A that increases as a function of common mode signal frequency. The result

2-8

is that the common mode rejection ratio, while essentially infinite at dc, rolls off for ac signals, and is
about 40 dB at 60 Hz line frequency. In addition, since the holding action of the sample-and-hold
circuit is only in effect on the first (non-inverting, signal) input but not on the second (inverting,
return) input, the voltage rate of change on the second input should be kept below 25 mV /ms. This is
the slope that results in a quarter-LSB change during the conversion interval. Such a rate of change
corresponds to 125 mV. peak-to-peak at 60 Hz line frequency. This dynamic response difference
hetween the two inputs requires us to distinguish the ADV11-A’s differential mode from true differen-

tial operation. Hence the term ‘‘quasi-differential.”

GENERATING

RECEIVING DEVICE

DEVICE

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11- 4168

Figure 2-4
2.4.2

Single-Ended Versus True Differential Input Modes

Avoiding Spurious Signals

As a preliminary step, confirm that the computer power supply groundis connected to power lme
(earth) ground. If continuity checks reveal no such connection, attach a length of 12-gauge wire
between the power supply ground and a convenient point associated with earth ground. (All DECLAB
11/03 systems are provided with this connection at the factory.)

2.4.2.1 Twisted Pair Input Lines — The effects of magnetic coupling on the input signals may be
reduced for floating single-ended
or differential inputs by twisting the signal and return lines in the
input cable. If the inductive pickup voltages of the two leads match, the net effect seen at the ADVI11-A
input is zero. Use of twisted pairs has no effect with a single-ended non-floating signal (referenced to
ground at the instrument end).

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2.4.2.2 Shielded Input Lines — The effects of electrostatic coupling on the input signals may be reduced by shielding the signal wires. This is especially important if the instrument or transducer has high
source impedance. To prevent the shield from carrying current and thus developing ground loop
voltages within the ADV11-A, connect it to ground at the instrument end only.

2.4.2.3 Allowing for Input Settling with High Source Impedance — All solid-state multiplexers inject a
small amount of charge into their input lines when changing channels, causing a transient error voltage
that is discharged by the input signal’s source impedance. The ADV11-A shares this characteristic, and
also injects a small charge into the selected input line at the end of each conversion when the auto-zero
switch is turned off (see Paragraph 2.3.2). After any channel change and after any conversion, the
ADV11-A’s control logic allows a 9 us interval (identified as the Transition Interval) during which
conversions cannot start without generating error conditions. Normally, this is sufficient time for the
input transient to settle out. However, more time may be needed when the multiplexer is switching into
an input channel with high source 1mpedance particularly when large amounts of shunt capacitance

exist in the interconnecting cables. Source impedance/cable shunt capacuance products greater than 1

us should be avoided whenever conversions are to be made at maximum rate with less than 1/2 LSB
error. This means that cable shunt capacitance for a 1000 © source should not exceed 1000 pF (10* X
1079 = 107%), that shunt capacitance for a 100 Q source should not exceed 0.01 uF (102 X 1078 = 107°),
etc. Assuming twisted pair cable capacitance of 50 pF/foot, these constraints translate into a maximum run of 20 feet from a 1000-Q source, 200 feet from a 100-{ source, etc. Note that these values are
consistent with good practlce for avmdmg noise pickup in long cable runs. Note also that settling
errors can be eliminated byincreasing the time between conversions or incorporating a software delay
between channel changes and program start commands.
2.43

Connections

Figure 2-6 illustrates the location of user connectors and switches on the component side of the

ADV11-A board.

Analog input signals are input to the ADV11-A through the 40-pin.connector Pin assignments for the
connector are shownin Flgure 2-7. The proper Berg-to-Berg cableis the RCO8R; the proper Berg to

prepared open-ended cableis the BCO4Z (See Malntenance chapter for further information. )

2.4.3.1 Distribution Panel Flgure 2 8 shows an H322 Dlstrlbutlon Panel thatis connected on the
rear to the ADV11-A Berg connector and on the front provides easily identifiable and conveniently
accessible barrier strip connections for user apparatus. Each H322 accommodates two ADV11-As or
one ADV11-A and one other single-connector device. The ADV11-A is shipped with decal sets that
specifically identify ADV11-A inputs and outputs. Note that the H323-B Potentiometer Box may rnot
be used with the ADV11-A. (See Maintenance chapter for appropriate potentiometer box eireuit.}

2.4.3.2 External and Clock Starts- The external start signal line, pin B of the Berg connector or TAB

S (see Figures 2-6 and 2-7), is a TTL-compatible input that presents five unit loads (8.0 mA) to any
|
|
- driving output. Conversions start on the high-to-low transitions of this signal.

In most cases, the external start signal will be produced by a grounded (non-floating) pulse generator
- or logic circuitry locatedin a grounded instrument. The return path for the External Start signal will be
through the power line ground system. For this reason, ground differences between source and com- puter should be minimized to prevent spurious start pulses due to ground noise. In no case should a
separate return line be run between grounded source and the computer ground Only with floating
devices should return lines be run between source logic ground and logic ground pins on the ADV11-A
Berg connector. External devices that require buffering can be interfaced to the ADV11-A through
Schmitt Trigger 1 of the KWV11-A clock (ST1). Connectionis made by means of a DEC 7010771 type
jumper (Figure 2-9) to TAB S (Figure 2-6) of the ADV11-A.

SINGLE-ENDED
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11-4322

ADV11-A Connectors and Switches

Conversions that must be initiated in consequence of time intervals or on every nth external event may
be triggered from the KWV11-A through a DEC 7010771 type jumper connected from the clock
output tab (CLK) to the ADV11-A clock overflow tab (C).

2.4.3.3 Mode Control - The ADV11-A is equipped with jumper lugs (see Figure 2-6) that permit
changing operating mode from quasi-differential (no connection) to single-ended (jumper installed).
The single-ended mode can also be selected by connecting Berg connector pin C to logic ground. This
alternative is provided to permit convenient external mode selection in installations that require fre“quent alternation between one mode and the other.

2.4.4 Vector and Address Selection - Device and vector addresses are assigned to the ADV11-A by
means of two switch packs (S2 and S1, Figure 2-6). S2is a pack containing 10 single-pole/single-throw
switches, numbered 1-10, that communicate with data lines BDAL 2-11. Assuming BDAL lines 12-15
to be set by the processor to 1, S1 permits assigning any address between 170000 and 177774. The
recommended address for the ADVII -A Status Registeris 170400, set as illustrated in Figure 2-10(a).
The Data Buffer Register automatically receives the next even address following that ass1gned to the
CSR.

- 2-12

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Figure 2-7

8201

Figure 2-8

H322 Distribution Panel

The A/D done interrupt vector address is set by means of S1, an 8-switch pack of which only six
switches are utilized. These switches communicate with BDAL lines 3 through 8 and can be set in
increments of 10s. The error interrupt vector automatically receives an address :that is four locations
higher than the A/D done interrupt vector whose recommended address is 000400 [see Figure 2-10(b)].

2-13

M-0599

Figure 2-9
2.5

Module Jumpers

PROGRAMMING

2.5.1

Control/Status Register (CSR)
The significance of the CSR bits is defined below:

Bit 15:
A/D ERROR (Read/Write) - The A/D ERROR may be program set or cleared and is cleared
by the processor INITIALIZE. It is set by any of the following conditions:

Attempting an external or clock start during the transition interval (see Paragraph

Attempting any start during a conversion in progress

Failing to read the result of a previous conversion before the end of the current conversion.

2.3.2)

Bit i4: ERROR INTERRUPT ENABLE (Read/Write) - When set, enables a program interrupt
upon
an error condition (A/D ERROR). Interrupt is generated whenever bits 14 and 15 are set, regardless

of which was set first.
Bits 13-12: Not used.

Bits 11-8: MULTIPLEXER ADDRESS (Read/Write) - Contain the number
of the current analog
input channel being addressed.

Bit 07:

A/D DONE (Read) - Set at the completion of a conversion when the data buffer is updated.

Cleared when the data buffer is read and by the processor INITIALIZE. If enabled interrupts are
requested simultaneously by both bits 07 and 15, bit 07 has the higher priority.

2-14

Bit 06: DONE INTERRUPT ENABLE (Read/Write) - When set, enables a program interrupt at the
completion of a conversion (A/D DONE). Interrupt is generated when bit 07 and bit 06 are both set,
regardless of sequence.

Bit 05: CLOCK START ENABLE (Read/ Write) - When set, enables conversions to be initiated by an
overflow from the clock option.

Bit 04: EXTERNAL START ENABLE (Read/Write) - When set, enables conversions to be initiated

by an external signal or through a Schmitt trigger from the clock option.

Bit 03: ID ENABLE (Read/ Write) - When set, causes bit 12 of the Data Buffer Register to be loaded

to a | at the end of any conversion.

Bit 02: MAINTENANCE (Read/ Write) - Loads, when set, all bits of the converted data output equal
to Multiplexer Address LSB (bit 08) at the completion of the next conversion. Cleared by the processor
INITIALIZE. Used for “all 0s” and “all 1s” tests of A/D conversion logic.

Bit 01: Not used.

Bit 00:

of the
A/D START (Read/ Write) - Initiates a conversion when set. Cleared at the completion

conversion and by the processor INITIALIZE.

OCTAL EQUIVALENT

dL L CSR ADDRESS
L E R

BB
0

1
BOARD

SWITCH (S2)

FEENEENEEN
03

04 05

I
10

11 " 12

BOARD

<—— HANDLE
:

FINGERS ~

—

CSR ADDRESS

Iololo

(SET FOR 170400)

—A e

—A

olo‘o

oIolt

SWITCH

—

OCTAL EQUIVALENT

o]olo

OJE?TG'\%_LUE

ololo

[TTTITLT

(TT

VECTOR

HEREERE

02'03

Trrrrrrir
04

05'06

08'09

'12

i
13

ion
DA

*SWITCHES NOT CONNECTED

b. VECTOR ADDRESS SWITCH (SET FOR

000400)
1-4171

Figure 2-10

ADV11-A Address and Vector Switches (Rocker or Slide Switches)
2-15

;

MSB

—

ERR

LSB

NOT USED

MUX ADDRESS

DONE
INT ENA

READ/WRITE

EX
START
ENA

MAINT

AD
START

ERR

CLK

INT ENA

DONE

START
ENA

ENA

NOT USED

11-434t

Figure 2-11

ADV11-A Control/Status Register (CSR)

VERNIER D/A (WRITE)
A

“MsB
15

\___Y__/&

09S

0]3)

MSB

LSB
03

LS8
|

CONVERTED DATA (READ)
11-4312

Figure 2-12

ADV11-A Data Buffer Register (DBR)

2.5.2 Data Buffer Register (DBR)
The DBRis actually two separate registers — one read only, the other write only.

Read Only (Cleared at processor initialize)

Bits 15-13: Not used. Should read as 0.
Bit 12: ID (Read) - When ID ENABLE (blt 03) of the CSR has been set, DBR bit 12 will be
loaded to a 1 at the end of conversion.
Bits 11-00: CONVERTED DATA (Read) - These bits contain the results of the last A/D
conversion.

Write Only (Set to 200s at processor initialize)
Bits 15-08: Not used.

Bits 07-00: VERNIER D/A (Write)- These bits provide a programmed offset to the converted
value (scaled.-1 D/A LSB
= 1/50 A/D LSB). The hardware initializes this value to 200 (mldrange) Values greater than 200; make the input voltage appear more positive.

2-16

2.5.3 Programming Example
Read 100s A/D conversions from channel 0 into locations 4000s-41765 and halt.

START:

LOOPs

CLR

@ADSR

yCLEAR

MOV

$#4000,R0

INC
TSTR

RADSK
AADSR

s SET UP FIRST ADDRESS
s START A/D CONVERSION
gCHECK DONE FLAG

A/D

BPL

LOOP

sWAIT

INC

@RADSR

) START

MOV

@ADBR, (RO) ¢+

s PLACE

UNTIL

s FROM

BNE

RO, #4200
LOOP

CONVERTED
BRUFFER

A/D

ADSR?

170400

ADBR?

170402

s END

AND
FOR
100

sCHECK

§JHAVE

BEEN

gNQO,

HALT

FLAG

SET

NEXT CONVERSTION#

s LOCATION
s LOCATION
CMP

STATUS

GET

VALUE
INTO MEMORY

SET UP NEXT
TRANSFER#
CONVERSIONS

DONE

CONVERSION

s DONE

sA/D

STATUS

ADDRESS

jA/D

BUFFER

ADDRESS

START

*Starting a subsequent conversion before moving data from a previous conversion is to be recommended only
with systems equipped with non-processor memory refresh, as provided in the REV11 options. Without this

capability, data will be lost occasionally by CPU memory refresh intervening between the INC and MOV conimands. In general, non-processor memory refresh is essential to realizing the full potential of the ADVI11-A.

2-17

CHAPTER 3

KWV11-A PROGRAMMABLE REAL-TIME CLOCK

3.1

GENERAL DESCRIPTION

The KWV11-A is a programmable clock/counter combination that provides a variety of means for
determining time intervals or counting events. It can be used to generate interrupts to the LSI-11

processor at predetermined intervals, to synchronize the processor to external events, or to measure

time intervals or establish programmed ratios between input and output events. It can also be used to
start the ADV11-A Analog-to-Digital Converter either by clock counter overflow or by the firing of a
Schmitt trigger.

The clock counter has a resolution of 16 bits and can be driven from any of five internal crystalcontrolled frequencies (100 Hz to 1 MHz), from a line frequency input or from a Schmitt trigger fired
by an external input. The KWVI11-A can be operated in any of four programmable modes: single
interval, repeated interval, external event timing, and external event timing from zero base.
The KWV11-A includes two Schmitt triggers, each with integral slope and level controls. The Schmitt
triggers permit the user to start the clock, initiate A/D conversions, or generate program interrupts in
response to external events.

The physical structure of the KWV11-A is illustrated in Figure 3-1. The unit is contained on one quad
size module whose fingers interface to the LSI-11 Bus. User interfacing for the Schmitt triggers and

clock overflow signals is accomplished by means of a multi-pin connector (J1). FAST ON connectors
(CLK, ST1) are provided to permit direct and simple connections of clock overflow and Schmitt
trigger outputs to corresponding terminals on the ADV11-A A/D Converter. Switch packs permit
selecting CSR (Control/Status Register) address, interrupt vector address, and Schmitt trigger slope
18 and R19) permit setting Schmitt trigger levels. Proviand level conditions. Screwdriver controls (R
J1 for external user-provided slope switches and level
connector
multi-pin
the
via
sion is also made
|

controls.

3.2
3.2.1

SPECIFICATIONS (@ 25° C unless otherwise specified)
Clock

Oscillator Accuracy

Range

0.01%

Base frequency (10 MHz) divided into five selectable rates

(1 MHz, 100 kHz, 10 kHz, 1 kHz, 100 Hz); line frequency;
Schmitt trigger 1 input

3.2.2

Input and Output Signals

All inputs and outputs are TTL compatible unless otherwise specified.

3-1

CLK STt

©Ri18

©Rr19

BIT 11

BIT 2

—

BIT 8

ADDRESS

SWITCHES

BIT
3
~

i
Figure 3-1

3.2.2.1
1.

VECTOR
SWITCHES

11-4318

KWYVI11-A Connectors, Switches, and Contrals

Input Signals

ST1 IN (Schmitt Trigger 1 Input)
Input Range
(maximum limits)
Assertion Level

-30Vto +30V

Origin

User device

Response Time

Depends upon input waveform and amplitude; typically
600 ns with TTL logic input

Hysteresis

Approximately 0.5 V, positive and negative

Characteristics

Single-ended input; 100 k2 impedance to ground

Depends upon position of slope reference selector switch
and level control; triggering range, -12 V to +12 V

ST2 IN (Schmitt Trigger 2 Input)

Same description as ST1 IN
3-2

3.2.2.2

OQOutput Signals

CLK OV (Clock Overflow)
Asserted Level

Low

Destination

User device or ADV11-A

Duration

Approximately 500 ns

Characteristics

TTL open-collector driver with 470 @ pull-up to +5 V
Maximum source current from output through load to

ground when output is high (= 2.4 V): 5 mA

Maximum sink current from external source voltage
through load to output when output is low (<0.8 V): 8 mA
2.

STI1 Out (Schmitt Trigger 1 Output)
Same description as CLK OV

ST2 OUT (Schmitt Trigger 2 Output)
Same description as CLK OV

3.2.2.3

Environmental (ref: DEC STD 102, class C)

3.2.2.4 Power Requirements (from LSI-11 Bus Power Supply)
+5V
1.75 A typical
+12V
10 mA typical

3.3
3.3.1

FUNCTIONAL DESCRIPTION
Bus Control

Figure 3-2 illustrates the KWV11-A in block diagram form.

The logic associated with the bus control block maintains proper communications protocol between
the processor bus and the KWV11-A. This logic generates and monitors the bus signals involved
during interrupts and data transfers between the processor and the KWV11-A. It permits the KWVI11A to recognize when it is being addressed by the processor (address defined by the Address Switch
Pack), to prescribe the location in memory pointing to the starting addresses of interrupt service
routines (by means of the Vector Address Switch Pack), to input control data from the processor, and
to output data to the processor.
|

Interrupts can be enabled for both counter overflow and operation of ST2. Since each of these conditions raises a flag bit in the Control/Status Register, and since separate interrupt vectors exist for each
condition, the conditions may be distinguished either by vectors or by testing flag bits.
3.3.2

Control/Status Register

The Control/Status Register (CSR) provides a means for the processor to control the operation of the
KWV11-A and to derive information about its operating condition. Bits are provided for enabling

interrupts, mode selection, maintenance operations, starting the counter, and overflow and Schmitt
trigger event monitoring. (See Figure 3-9 and Table 3-1.)
3-3

’

BUS

CONTROL
BUFFER
PRESET

S;};\'CT}SH

(BPR)

BPR 15-0

COUNTER | |

RDAB 15-0

CLK OV L

VECTOR H|

SWITCH

o
‘

VECTOR | &

ADDRESS | +
BUS DATA/

IRE:
|

ADDRESS

sTeL

LINES

BIRQ L, BINIT L

- BIAKO L, BIAKI |_
2]

ST2 FLAG H

CLK OV

ADDRESS &

BSYNC L, BDOUT

TIMING CONTROL

BEVNT L

| |

BRPLY

CSR 5-3
‘

’

| MHZ

100 KHZ

::'>*

VYSTLIN $<ST LEV 1

§4_3T LEV 2

(1)

10 KHz

KHZ

100 HZ
|

SCHMITT TRIGGERS

(J1)

TTsT2.IN

" _—_>

1oMHZ [ DIVIDER LI> CONTROL ['sel cLk H
‘

0sC

BWBT L, BDIN L,

_—]

(CSR)

CSR 15~0

SLEAR AL

*:‘—i

| REGISTER

INTERRUPT CONTROL f=
.

STATUS

CONTROL

{\;\\j’
'

MODE [

CLR LD

CONTROL /

BBS7 L

‘

BDAL 15-0 L

ST SLOPE 1

E\v‘ ST SLOPE 2

__J

sTiouT L | YWY

—0
1)

ST1

ST2 OUT L HH
ST H

sT2 L _

* MISCELLANEOUS

lshllgfiitsgl_ CONTROL

1-4174

Figure 3-2
3.3.3

KWV1I1-A Real-Time Clock Block Diagram

Mode Control

Logic circuitry associated with the mode control-block permits KWV11-A operation in four dlfferent

modes as specified by bits 2-1 of the CSR.
3.3.3.1

Mode 0 (Smgle Interval)
When the GO bitis set in this mode either by the processor or by a Schmitt Trigger 2 event, the counter

is loaded from the Buffer/Preset Register (which has previously been loaded with the 2’s complement
of the number of counts desired before overflow). Once loaded, the counter will increment at the
selected rate until it overflows. Overflow clears the GO bit, sets the Overflow Flag, and interrupts the
processor if that function has been enabled. If interrupt has not been enabled, the KW V11-A waits for
processor intervention.
- 3.3.3.2 Mode 1 (Repeated Interval)
When the GO bitis set in this mode, the counter is loaded from the Buffer /Preset Register (BPR) and

is then incremented to overflow as for Mode 0. In Mode 1, however, overflow does not clear the GO
bit; instead, it causes the counter to be reloaded from the BPR, raises the Overflow Flag, initiates an
interrupt sequence if the CSR Interrupt on Overflow bit is set, and causes the count to be continued
with-no loss of data.

3.3.3.3

Mode 2 (External Event Timing)

When the GO bit is set in this mode, the counter is set to 0 and then incremented at the selected rate as

long as the GO bit remains set. An external signal to Schmitt Trigger 2 (ST2) causes the current

contents of the counter to be loaded into the BPR while the counter continues to run. At the same time
the ST2 Flag is set and, if Interrupt 2 is enabled, an interrupt is generated, thus permitting the program
to read the value held in"the BPR.

The counter continues to run after the ST2 event and also continues to run after overflow. Interrupt on
Overflow may be enabled to alert the program to the overflow condition.
3.3.3.4

Mode 3 (External Event Timing from Zero Base)

Operation in Mode 3 is identical to that in Mode 2 except that the counter is zeroed each time an ST2
event loads its contents into the BPR.

3.3.3.5

Flag Overrun

In all modes, if a second overflow occurs before the Overflow Flagis reset (i.e., before a prior event is
serviced by the processor), or if ST 2 fires when the ST 2 flagis already set, the Flag Overrun bitis set.

3.3.4

Oscillator, Divider, Rate Control Chain

The circuitry associated with these blocks provides the time base that is fed to the counter. The
KWVI11-A permits eight clock conditions to be specified by bits 5-3 of the CSR: STOP, 1 MHz,
100 kHz, 10 kHz, 1 kHz, 100 Hz, an external time base applied to ST1, and line frequency (50 or 60
Hz) picked up from bus line BEVNT. External periodic or aperiodic pulses may be applied to ST1 and
counted, provided they meet the criteria in Paragraphs 3.2 and 3.3.6.

3.3.5

Buffer/Preset and Counter Registers

The Buffer/Preset Register is a word-oriented, 16-bit read/write register that can be loaded either
under program control or from the counter. In Modes 2 and 3, the firing of ST2 causes the BPR to be
loaded with the contents of the counter. The BPR cannot be loaded by the program in these modes as
long as the GO bit 1s set.

The counter is a 16-bit internal reglster acce531ble only by way of the BPR; in Modes 2 and 3 it can be
read indirectly through the BPR.
3.3.6

Schmitt Triggers

Both Schmitt triggers are equipped with switches to permit selecting slope direction (+ or -) and
threshold reference level (TTL or -12V to +12V continuously variable). Each Schmitt trigger is also
equipped with a screwdriver-operated potentiometer to permit setting the variable threshold level.
‘Switch-pack and potentiometer terminals are all brought to multiple connector J1 to permlt attachment of external user-provided slope and level controls. (See Figure 3-3.)
The two Schmitt triggers are usedin somewhat different ways:

STI - Performs as an external time base input or external input for aperiodic signals to be
counted. Outputs both to ST1 FAST ON connector to provide external start signals to ADV11-A
and, through rate control circuitry, to permit selection as input to the counter. Max1mum frequency varies as a function of input waveform.

ST2 — When the ST2 GO ENABLE bit is set, firing ST2 in any mode sets the GO bit and initiates
counter action, causes the ST2 Flag to be asserted, and generates an interrupt if that function is
enabled. When the GO bit is set in Modes 2 and
3, firing ST2 causes the Buffer/Preset Register to
be loaded from the counter, the ST2 Flag to be set, and an interrupt to be generated if enabled.

TTTETE

e®

EXT. ST1
&

LEVEL POT

(5- 20K)

EXT, ST2 &

. L

LEVEL POT 3

(5 - 20K)

—— NN OR PP

(BOTH ARE GND.)

EXTERNAL

SLOPE 1
SWITCH

———0/

S2
)

EXTERNAL

‘

SLOPE 2

SWITCH

00—

—)

)

—e

BOARD

HANDLE

OFF

ON
OFF
OFF
OFF
|
UNUSED

BOARD
FINIERS

NOTE
:
For proper operation of external

level controls, both R18 and R19

on KWVii-A

board

must be set to approximate mid
- point of

rotation, and

the S2 switches musi be set as shown.
11- 4337

Figure 3-3

Connecting External User-Supplied Slope and Level Controls

3.4

CONNECTORS, SWITCHES, AND CONTROLS
Figure 3-1 illustrates the location of user connectors, switches, and controls on the component side of
the KWV1I-A board.

3.4.1
40-Pin Connector
Figure 3-4 illustrates the 40-pin connector pin assignments for user inputs and outputs. These pins may
be connected to the optional H322 Distribution Panel* (see Paragraph 2.4.3.1) for convenient external
user access. The proper Berg-to-Berg cableis the BCO8R. The proper Berg to prepared open-ended

cableis the BCO4Z.
3.4.2

KFAST ON Connectors (Clock Overflow and ST1 Outputs)
Two FAST ON connector tabs labeled CLK and ST1 are situated in the upper--right corner of the
KWYVI11-A board (see Figure 3- I). These tabs are electricallyin parallel with pins RR (CLK OV L) and

Uu (STI OUT L) on the 40-pin connector and are intended to facilitate connections by means of
modulejumpers (shownin Figure 2-9) to the clock overflow and external start inputs on the ADV11-A
(see Paragrapgh 2.4.3).
3.4.3

Selector Switches (Address, Vector, and Slope/Reference Level)

Figure 3-1 identifies three switch packs (S1, S2, and S3) that the KWV11-A provides to facilitate the

selection of CSR address, vector address, and slope/reference level conditions for Schmitt Triggers 1
and 2.
*The KWV11-A is shipped with decals which permit permanent identification of signal lines associated with H322 terminals.

3-6

B
D

C
E

—

Kl
5
——EL————O

o0—4-—poT2
o
N POT 1

YUl

+3V

o—o»4 ¥

o—0
%X __

—t0

CcC

_E_E__o
HH

O-

FF
JJ

PP} -

L —p—o0

T7T

CLK OV L

'--L

O—1—— ST
2 IN

ST 10UT L—E-L-’———o
|

o—— R SLOPE 2
0———1-— SLOPE |

LS BN

ST20UT

S S
—S————O

H
—t>0

\'AY

ST1IN

h
n-4175

BOARD SIDE

Figure 3-4

40-Pin Connector Pin Assignments

3.4.3.1 Address Selection - Switch Pack S1 contains 10 single-pole/single-throw switches that communicat~ with data lines BDAL 11-2. The KWV11-A reads the BDAL lines only in response to BBS7
which the processor asserts only for an address of 160000 or higher. For this reason, and because the
KWV11-A transceivers are hard wired to respond only when BDAL bit 12 is set to 1, S1 permits
assigning the CSR any address ending in 0 or 4 between 1700005 and 177774s. The recommended
address for the KWV11-A CSR is 170420, set as illustrated in Figure 3-5. The BPR automatically
receives the next even address following that assigned to the CSR.
1

-0

OCTAL EQUIVALENT

LOGICAL
.

0 #/ ///

?// /// ////

/// //

S
S1

;

HER
15

Ll
10

09 08

Tl
07

<«+—— BOARD HANDLE

BDAL BIT

NIRRT
.

05 04

03 02

‘

B0OARD FINGERS —=
NOTE:

1. Switches. may be of either
rocker or slide variety.

Figure 3-5

"-4176

KWVI11-A CSR Address Switches (Set for 170420)
3-7

3.4.3.2

Vector Selection - The clock overflow interrupt vector address is set by means of S3, a 7switch pack of which only six switches are utilized. These switches communicate with BDAL lines 8-3
and can be set in increments of 10s. The ST2 interrupt vector automatically receives an address that is
four locations higher than the clock overflow interrupt vector whose recommended address is 0000440

(see Figure 3-6).

i oolo’o

o,ol0‘1|olo1l

,
i

OCTAL EQUIVALENT

BIT VALUE

[

]LOG'CA'-

72 W o) A B3

T
13

12 " {1t

LT T
10

[

T T
07

<—— BOARD HANDLE

T T
04

T T esanes
,

POSITION

BOARD

FINGERS

—»

NOTE

Switches may be of either
rocker or slide variety.

Figure 3-6

11-4177

KWVI1I1-A Vector Address Switches (Set for 000440)

3.4.3.3 Slope and Reference Level Selector Switches and Controls (See Figure 3-7) - Slope and refer‘ence level selection for ST1 and ST2 are accomplished by means of S2, a 7-switch pack of which only
‘switches 1-6 are used. Two reference modes are selectable for each Schmitt trigger — one that picks a
fixed level appropriate to TTL logic, and one that picks a variable level that permits setting the ST
threshold to any point between -12 and +12 V.

NOTE

User should take care that both TTL and variable
switches for either Schmitt trigger are not on simul-

taneously. This condition will do no damage to components, but produces unpredictable reference levels.
Note also that if no signal is connected to a Schmitt
trigger input, both threshold switches for that ST
should be open for noise immunity. Alternatively,
ST1 IN and ST2 IN can be grounded externally.

Slope selection is accomplished by separate switches for ST1 and ST2, respectively. When the related
~switch is on, the firing point effectively occurs on the positive slope of the input waveform. When the
switch is off, the firing point occurs on the negative slope. (See Figure 3-8.)
3.5

3.5.1

PROGRAMMING

CSR Bit Assignments

CSR bit assignments are identified in Figure 3-9 and defined in Table 3-1.

OFF

"\ ON

TTL REFERENCE

(J1-N)

(J1-L)

o o

VARIABLE REFERENCE
[

R18 2

V
<>

RI9Y

l ST LEVEL1

BOARD HANDLE

I ST LEVEL 2
ST SLOPE 1{J1-T)

o o—

ST SLOPE 2(J1-R)

NOT USED

BOARD FINGERS

}
11-4178

Figure 3-7

3.5.2

KWV1I-A Slope/Reference Level Selector Switches and Controls

Buffer/Preset Register (BPR)

The BPRis a 16-bit, word-oriented, read/write register. Any attempt to write a byte into this register
will result in a whole word being written. In Modes 0 and 1 the program may load it with the 2’s
complement of the number of counts desired before overflow. In Modes 2 and 3 it permlts indirect
reading of the clock counter.
:
—

3.5.3 ‘_ ‘Normal Control Sequences

3.53.1 Mode 0 (Single Interval) - Control code for operation in Mode 0 must support the following
sequence:

Control program writes desired count (2’s com:plement) into BPR (see Paragraph 3.3.95).

Program writes control codeinto Control/Status Register as 1nd1eatedin Table 3-2.

If GO bitis set high, KWVll A responds by loadmg the 16-bit counter (see Paragraph 3.3.5)
from the BPR and enabling the counter; if GO bitis set low and ST2 GO ENABLE bitis set
high, KWV11-A waits for ST2 event, then sets the GO bit and loads and enables the

counter.

5.
6.

Counter increments until overflow, then halts (GO bit is cleared)

KWVI1I1-A raises Overflow Flag andissues interrupt if the CSR'INT OV bitis set; if inter-

rupt is not enabled, KWVH A waits for program intervention.

Program responds to interrupt or intervenes in consequence of other criteria (e.g., testing the
Overflow Flag or the A/D Done Flag if overflow was used to start an A/D cenversion).
Program reads the CSR, clears the Overflow Flag, and if no counting or mode changes are
required, sets the GO b1t or the ST2 GO ENABLE bit to reenter the sequence at step 3.

3-9

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~Table 3-1 " KWV11:A CSR Bit Definitions

Remarks

Set By/C]eared By

Bit

Set by the firing of Schmitt Trlgger | Must be clearéd after servicing an.

15 ST2 Flag

2 or the setting of the MAINT ST2 |* 'ST2 interrupt to enable further
interrupts. When cleared, any
bitin any mode while the GO bit or

Read /Write to 0

pending ST2 interrupt request will

the ST2 GO ENABLE bit 1s set.
Cleared under program control.
Also cleared at the “1”-going transition of the GO bit unless the ST2
GO ENABLE bit has previously
‘been set.
Set and
~control.

14 INT 2
(INTERRUPT

cleared

under

be cancelled. If enabled interrupts
are requested at the same time by

bits 07 and 15, bit 07 has the higher
priority.

When set, the assertion of ST2 Flag
will cause an interrupt. If set while
ST2 Flag is set, an interrupt 1s
initiated. When cleared, any pending ST2 interrupt request will be

program

ON ST2).
Read /Write

cancelled.

trol. Also cleared at the

661’9

When set, the assertion of ST2 Flag

~ Set and cleared under program con-

13 ST2 GO
ENABLE

will set the GO bit and clear the
ST2 GO ENABLE bit.

-going

transition of the GO bit.

Read/Write

Set when an overflow occurs and
the Overflow Flagis still set from a
previous occurrence, or when ST2
fires and the ST2 Flag is already
set. Cleared under program control
and at the *“1”’-going transition of

12 FOR

(FLAG OVERRUN)
Read/Write

This bit provides the programmer
with an indication that the hard-

ware is being asked to operate at a

speed higher than 1s compatlble

with the software.

the GO bit.

11 DIO
(DISABLE
INTERNAL

Set and ‘cleared ‘under program
control.

OSCILLATOR)

For maintenance purposes, this bit
inhibits the internal crystal
oscillator from incrementing the
clock counter. Used in conjunction
with bit 10 below.

Read /Write

10 MAINT OSC
Write Only

‘Set under program control. Clear-

ing is not required. Always read as
a

660.9’

For maintenance purposes, setting
this bit high simulates one cycle of
the internal 10 MHz crystal
oscillator used to increment the
clock counter.

9 MAINT ST2
Write Only

Set under program control. Clearing is not required. Always read as

G‘O 99

Setting this bit simulates the firing
- of Schmitt Trigger 2. All functions
~‘initiated by ST2 can be exercised
~under program control by using
this bit.

- 3-11

TTHETE

Table 3-1

KWV11-A CSR Bit Definitions (Cont)

Bit

Set By/Cleared By

Remarks

8 MAINT ST1

Set under program contro'l..‘Clear- |

Setting this bit simulates thelfiring

Write Only

ing is not required. Always read as
a *'0."”
,

of ST1. All functions initiated by
ST1 can be exercised under program control by using this bit.

7 OVFLO FLAG
Read/Write to 0

Set each time the counter overflows. Cleared under program control and at the *1”’-going transition
of the GO bit.

6 is set, bit 7 set will initiate an
~If bit

interrupt. Bit 7 must be cleared
after the interrupt has been serviced
to enable further overflow interrupts. If cleared while an overflow
“interrupt request to the processor is
pending, the request is cancelled. If
enabled interrupts are requested at
the same time by bits 07 and 15, bit
07 has the higher priornty.

6 INTOV

(INTERRUPT ON
OVERFLOW)

program

When this bit is set, the assertion of
OVFLO Flag will generate an interrupt. Interrupt is also generated if
bit 6 is set while OVFLO Flag is set.
If cleared while an overflow interrupt request to the processor is
pending the request is cancelled.

Set and cleared under program

These bits select clock counting rate

Set and
control.

cleared

under

Read ‘Write

5:3 RATE

control.

Read ‘Write

5 4

0
0O
1
1
0
0
1
1

0
1
0
1
O
1
0
1

0O
0
0O
O
1
1
1
1
2:1 MODE

Set

and

cleared under program

control. Read/Write

Read/Write

Set and cleared under program control. Also cleared when the counter
overflows in Mode 0.

3-12

Rate

STOP
I1MH:z
100 kHz
10kHz
1kHz
100 Hz
STI
Line(50/60 Hz)
2

ModeO:

Mode I:

0
1|

1
O
1

Mode2:
Mode 3:
0 GO

Or source.

Setting this bit initiates counter
action as determined by the rate
and mode bits. In Modes 1, 2, and 3
it remains set until cleared. In
Mode O it clears itself when counter
overflow occurs. Clearing bit 0
zeroes and inhibits the counter.

FLG

INT 2

MAINT

DIO

ST2
GO ENA

ST2

FOR

MAINT
0sC

RATE
2

OVFLO
FLG

ST2

MAINT
ST1

INT OV

MODE

RATE
0

MODE

RATE

11-4310

'Figfire 3-9 CSR Bit Assignments
3.5.3.2

Mode 1 (Repeated Interval) - Control code for operation in Mode 1 must support the follow-

Ing sequence:

Control program writes desired count (2’s complement) into the BPR.

Program writes control code into CSR as indicated in Table 3-3.

If GO bit is set high, KW\[{U;‘-A responds by loading the 16-bit counter from the BPR and

enabling the counter; if GO bit is set low and ST2 GO ENABLE bit is set high, KWVI1-A

waits for ST2 event, then sets the GO bit and loads and enables the counter.
4.

5
6.

Counter increments until overflow.

KWVI1I1-A reloads counter from the BPR, reenables the counter, raises the Overflow Fla‘g in

the CSR, and issues interrupt to the processor if interrupt is enabled.

If second overflow occurs before first is serviced (i.e., if Overflow Flag is still high when next
overflow occurs), KWVI11-A Flag Overrun (FOR) bit in the CSR is set high to alert pro|

gram that data has been lost.

Program responds to interrupt or intervenes in consequence of other criteria. Program reads
CSR, clears the Overflow Flag, and if no counting or mode changes are required, sets the
GO bit or the ST2.GO ENABLE bit to reenter the sequence at step 3.

3.5.3.3 Mode 2 (External Event Timing) - Control code for operation in Mode 2 must support the
following sequence:

Program writes control code into CSR as indicated in Table 3-4.

KWVI1I-A responds by incrementing the counter (zeroed when the GO bit was cleared) at

the selected rate until the GO bit is set to 0.

ST2 pulse loads current counter contents into BPR, sets the ST2 Flag, and generatés inter-

rupt if INT 2 is enabled.

4..

Overflow sets OVFLO FLG high and, if INT OV bit is high, generates interrupt.

Counter continues to increment until processor sets GO bit to 0.

Normally, program enables INT 2 and/or INT OV bits, permitting the processor to synchronize its

operations with the external ST2 events and prevent loss of data by reinitializing the process after step |

-3-13

Table 3-2

CSR
Name

Bit No.
15

CSR Bit Settings for Mode 0, Single Interval

~ Bit Condition
as Written by
Processor

ST2 FLG

Remarks
Will be set to 1 on ST2 event. Cleared

by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.
14

INT 2

Set to | by program if interrupt on
ST2 event is desired.

ST2 GO ENA

Set to 1 by program if GO is to be set

by external signal to ST2. Cleared by
leading edge of GO bit assertion.
12

FOR

(0)

11 |

DIO

MAINT OSC

MAINT ST2

| MAINTSTI |

OVFLOFLG

Will be set to 1 by counter overflow.

Always cleared by leading edge of GO
bit assertion.
6

INT OV

RATE 2

RATE |

RATEO

MODE

Set by program to 0.

MODEO

- Set by program to 0.

2
1

|
|

Set to 1 by program for interrupt on
counter overflow.
|

See Table 3-1.

Set by program to 1 unless ST2 GO

ENA 1s set; remains 1 until written to
0 by program. Cleared when counter
overflows.
x = 0or 1, depending on user requirements.
(0) = Automatically cleared by GO bit assertion.

3-14

Table 3-3

CSR
Name

Bit No.

CSR Bit Settings for Mode 1, Repeated Interval
Bit Condition
as Written by
Processor

ST2 FLG

Remarks

Will be set to 1 on ST2 event. Cleared
by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.

INT 2

Set to 1 by program if interrupt on

ST2 event is desired.
13

ST2 GO ENA

Set to 1 by program if GO is to be set

by external signal to ST2. Cleared by
leading edge of GO bit assertion.
12

FOR

(0)

DIO

MAINT OSC

MAINT ST2

MAINT ST1

OVFLOFLG

(0)

Will be set to 1 by counter overflow.

Always cleared by leading edge of GO
bit assertion.

INT OV

Set to 1 by program for interrupt on

counter overflow.
5

RATE 2

RATE |

RATEO

MODE 1

MODEO0

See Table 3-1.

Set by program to ;.

Same as for Mode 0, except that bit is

not cleared when counter overflows.

(0)

0 or 1, depending on user requirements.
Automatically cleared by GO bit assertion.

Table 3-4

Bit No.

CSR
Name

IST2
‘

CSR Bit Settings for Mode 2, External Event Timing
Bit Condition
as Written by
Processor

FLG

Remarks

Will be set to 1 on ST2 event. Cleared
by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.

INT 2

ST2 GO ENA

FOR

(0)

DIO

MAINT OSC

MAINTST2

MAINT ST

OVFLOFLG

(0)

Set to 1 by program if interrupt on

ST2 event is desired.

Set to 1 by program if GO is to be set

by external signal to ST2. Cleared by
leading edge of GO bit assertion.

Will be set to 1 by counter overflow.

Always cleared by leading edge of GO
bit assertion.

INT OV

RATE 2

RATE 1

RATEO

MODE 1

MODE0

Set to 1 by program for interrupt on

counter overflow.

See Table 3-1.

Set by program to 2s.

Set by program to 1 unless ST2 GO

ENA is set; remains 1 until written to
0 by program. Cleared when counter
overflows.

x = 0or 1, depending on user requirements.
(0) = Automatically cleared by GO bit assertion.

3-16

3.5.3.4 Mode 3 (External Event Timing from Zero Base) - Operation is identical to that in Mode 2
except that counter is zeroed after ST2 pulse. Counter continues to increment until GO bit is set to 0.

Note that the interval between two ST2 events may be measured directly in Mode 2 or 3 with processor

assistance if the CSR ST2 GO ENABLE and Interrupt 2 bits are set before the first ¢évent and the GO
bit is left clear. Urider these conditions, the first ST2 event will set the GO bit (and thus start the
counting process) and simultaneously issue an interrupt. If the interrupt service routine now clears the
ST2 Flag bit, the next ST2 event will cause the BPR to be loaded from the counter in the normal Mode
2 fashion. The choice of Mode 2 or Mode 3 for such measurements will depend on whether or not an
ongoing accumulation of time after the second event is required by the application. If such an accumulation is necessary, Mode 2 is appropriate since the counter is not zeroed after ST2 events.
3.5.4

Programming Example

Record point in double-precision timeframe for each ST2 event following GO. Program makes use of a
32-bit counter, the low order bits of which are taken directly from the KWV11-A (KWBPR) and the
high order bits of which are taken from a software counter (HICNT) that is incremented with each
KWBPR overflow.

MTPS
MOV

$ST28RV,

@ST2VEC

MOV

$8200,@5T2PSW

JCLEAR PS8W
g LOAD 8T2 VECTOR
JADDR

MOV

$OVSRV,

MQV

@OVVEC

$200,@0VPSW

§SET

PSW

JALL

SUBSEQUENT

g INTERRUPT

FOR

872

(DISABLE

JINTERRUPTS)
y LOAD OV VECTOR

9 ADDR

g SET

PSW

FOR QV

g INTERRUPT (DISABLE
jALL SUBSEQUENT
g INTERRUPTS)

RQ
'

MOV

$BUFFER,

CLKGO}

MOV

#340115,@KWCSR

COUNT

WAIT

OVSRV:

BIT
BEG

MODE

INT S8T2

INTO

KWCSK

gAND

gBY

OVFLO

EN,

ST2

9IS FOR BIT SET?
gNO, CONTINUE

#100000,@KWCSR
29

gNO, CONTINUE

FURSRY

@KWNBPR

MOV

H1CHLT, (RO)+

MOV

@KWBPRs (PO)+

BIC

i1MHZ,

EN,

810000, 8KWCSR
COUNT

TST

BPL

sDEPOSIT

,INT GV

jFOR INTERRUPT

BIT
BEQ

JMP

JSET UP POINTER TU
sBEGINNING OF
jBUFFER AREA

2§

$100000,RKWCSR

JYES, SERVICE FLAG
sOVEKRUN CONDITIQWN
3 LS §T2 FLAG SET?

gDILD ST2 QOCCUR BEFOQORE QV?Y

sNO,

s YES,

BRANCH

SERVICE S8T2 FIlRST

s ACKNOWLEDGE ST2
§OCCURRENCE

(example continued on next page)

INC

HICKNT

$ INCKEASE

1
BEQ

BIC

MSB

CUOUNT

ENDSRV

s BRANCH

$200,RKWCSR

sCAUSES OVERFLUwW
s ACKNOWLEDGE 0OV

RTI

sCLEAR
gAiND

INCREASE

BIT

RETURN

MAILN

s FPROGRAM
ST2SRV

MOV

HICNT, (RO)+

JGET

MOV

RKWBPR, (RO)+

JGEYT LS8

BIC

$1000G0, @KWCSR

JACKNOWLEDGE

RT1

JAND

§
FORSRYV

MSBE

FROM

RETURN

s TOC

COUNT

ST2
TO

MALN

PRUGKFAM

JEVENTS

SOF1

FROM HARD COUNT

OCCURRING

FAST

FOR

CURRENT
.

§SERVICE

@
[]

ENDSKEV
S

132 BIT QVERFLOW
s OCCURRED

KwCSE:

170320

KWBPR:

170422

OVFVEC:

440

ST2VEC?

444

HICinT:

BUFFER?

e BLKW

XXXX

s XXXXsLENGTH OF
sBUFFER

RESULT

CHAPTER 4
AAV11-A DIGITAL-TO-ANALOG CONVERTER

4.1

GENERAL DESCRIPTION
The AAVI1I1-A is a 4-channel digital-to-analog converter module for use on the bus of the LSI-11
processor. The unit is made up of control and interfacing circuitry, four D/A converters, a dc-dc
converter to provide power to the analog circuits, and a voltage reference. Each channel provides 12
bits of resolution. Each has its own holding register which can be separately addressed and can be
written and read in either-word or byte format. In addition, bits 0-3 of the fourth holding register are
brought to the I/O connector for use as a 4-bit digital output register.

Jumpers permit manual selection of voltage range and operating mode (bipolar or unipolar).

4.2

SPECIFICATIONS (@ 25° C unless otherwise specified)

Number of D/A Converters
Digital Input

12 bits (binary encoded for unipolar mode, offset binary

encoded for bipolar mode)
Digital Storage

Read-write, word or byte operable, single buffered

Analog Output Voltage Range
(jumper selected)
Digital Output Characteristics
(DAC 3 Holding Register

+2.56 V, £5.12 V, £10.24 V bipolar; 0 V to +5.12 V, 0 V to
+10.24 V unipolar
Source: 5.2 mA @ 24V
Sink: 16 mA @ 04V

Bits 3:0)

Resolution

1 part in 4096

Warm-Up Time

5 minutes minimum

Gain Accuracy

Adjustable (factory-set for bipolar £5.12 V; selection of other

ranges may require recalibration)

Gain Temperature Coefficient

10 ppm per degree C, maximum

Offset Temperature Coefficient

20 ppm of full scale range per degree C, maximum

Linearity

+ 1/2 LSB maximum non-linearity

Differential Linearity

+ 1/2 LSB, monotonic

Output Impedance

1 @ maximum at DAC output; 4 @ maximum at end of BCO8R

8 ft cable

4-1

Drive Capability

+ 5 mA maximum per converter

Slewing Speed

5 V/us

Rise and Settling Time

4 us; 8 us with 5000 pF load in parallel with 1k Q

(to 0.1% of final value)

Power Consumption
(from LSI-11 bus power supply)

5V5% @ 1.5A,12V@04 A

Environmental

Ref: DEC STD 102, class C

‘Packaging

One quad module

Bus Loading

1 bus load

4.3 FUNCTIO‘VAL DESCRIPTION

Figure 4-1 illustrates the AAV11-A in block dlagram form.
4.3.1

Bus Control

The logic associated with the bus control section maintains proper communications protocol between

the processor LSI-11

bus and the AAVI11-A. This logic generates and monitors the bus signals

involved during data transfers between the processor and the AAV11-A, permitting the AAV11-A to
recognize when it is being addressed by the processor (address defined by setting on the Address

Switch Pack), to accept input data from the processor, and to output data to the processor.
4.3.2

Control Logic

The AAVI1-A has no Control/ Status Register. The four digital-to-analog converters continually generate voltages at their outputs that reflect whatever digital values have most recently been written into

their respective holding registers. The role of the control logic
is to make the necessary discriminations
between requests to change the state of the holding registers (i.e., to write into the holding registers),
and requests to put the holding register contents onto the BD lines where they can be plcked up

through the transceivers by the processor.
4.3.3

DAGCs
0, 1, and
2
Digital-to-analog conversion functions afé performedin each of the four AAV11 A channels by identi-

cal circuits:

A holding register which stores the digital value output by the processor

A digital-to-analog converter (DAC) proper which generates a current that is a function of
the holding register value and of the mode/level jumper conditions

o
4.3.4

An amplifier that translates the current into a proportional voltage, provides a low output
impedance for the channel, and permits adjustment of signal offset.

DAC3

DAC 3 is identical to DACs 0, 1 and 2 except that Holding Register bits 0-3 are routed to the I /O

connector as well as to the DAC. Thls arrangement permits these bits to be routed to external equip-

ment that requires binary control signals at programmable intervals. Control data in these bit positions affects any 12-bit D/A conversion that they coincide with, but since they involve the least
significant bits of the word, the worst-case error is less than 0.5%. Consequently, DAC 3 can be used as
a 12-bit DAC or as an 8-bit DAC plus four output bits for CRT Intensify, Store, Non-Store, Erase,
etc.

4-2

av3yJva¢ e7

_1o910=1filél__
_ _ _ q _ , " HLINI

TOH1INOD

»YMOvd€H_—%e.w.b._m\\nw\0M/\71«3AS“3.7\m\1\o_[tnoeovao|
.

-— 434 A0} +

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wesdel(q YoId V-11AVY [-p 2Insid

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4-3

4.4 CONNECTORS, SWITCHES, AND CONTROLS
|
Figure 4-2 illustrates the location of user connectors, switches, and controls located on the component
side of the AAV11-A board.

DACO

(OFFFET)

(GAlN)(OFFSET)

DAC O
[o

DAC

DAC 1
W3

DAC2

DAC3

(GAIN)(GAIN) (OFFSET)

R37 (GAIN)
R49 (OFFSET)

DAC 2

WI0

wi2

DAC 3

wif

Wi8

W15

]

Ommmml)

Oumssnczl)

Omummpanl)

Cumasl) Oronnac=d)

Ommncesl) Omumocml)

Cummemd

Oomac) O

)

Wiz

wid

W17

Wi6
J

MODE /LEVEL STRAPS

N
BIT

BIT3

[
(ADDRESS)

[
Figure 4-2

11-4319

AAV11-A Connectors, Switches, and Controls

4.4.1
40-Pin Connector
Figure 4-3 illustrates the 40-pin connector pin assignments for user outputs. These pins may be con-

nected to the optional H322 Distribution Panel* (see Paragraph 2.4.3.1) for convenient external user
access. The proper cable for this purpose is the BCO8R. Also available is a Berg to prepared openended cable, the BC04Z.
Either a VR14 or VR17 CRT may be interfaced to the H322 via a user-created cable terminating in a
24-pin Amphenol, or equivalent, male plug (DEC #12-03466-00). A user-created cable may be connected to other types of CRT systems using a 25-pin connector such as a male DB25P type plug (DEC
#12-05886-00).

* The AAV1I1-A is shipped with decals which permit permanent identification of signal lines associated with H322 terminals.

4-4

TTHETE

—

o—

——

P
——

o—
|

—t—0

N x |< |4 |=m |2 r-lc.l"nlolm

Ji
A

o—1 g7 30uT
o—1F a7 2 out

—+— o

DAC 1 HQ GND — o

o—1 a1y out

_DAC
2 HQ. GND —
o DAC 3 HQ oND -]
o

o—{* giroouT
o———" pac 3 00T

-5V TEST —4 &

o—1"R pac 2 out

+15v TEST —2f o

o—4"T pac 1 ouT

DAC 0°HQ :6ND —— o6

o— 1YY pac 0 ouT |

BOARD SIDE

”

11-4314

Figure 4-3 40-Pin Connector Pin AssignméntS'
RN

The BC04Z signal lines may be connected.to user-selected pins on a male or female connector. A

female 25 pin connector of the-DB25S type (DEC #12-09326-00) may
be used for general purposes. A
male 25-pin connector of the DB25P type (DEC #12-05886-00) will interface several popular CRT
systems to the AAV11. Either a VR14 or VR17 CRT may be interfaced by means of a 24-pin Amphenol, or equivalent, male plug (DEC #12-03466-00) to the BCO4Z. Both the AAV11 and selected CRT
must be set up and adjusted for electrical compatibility. The CRT manual should define appropriate
connector pins for each AAV11 signal line. Appropriate software will be necessary to control a CRT.
4.4.2

Address Switches

4-2 identifies the location of S1, a switch pack containing 10 single-pole single-throw switches (1
Figure
unused) which, when set, transmit 0 logic levels to the compare inputs of the transceivers. Whenever

the AAV11-A sees BBS7 transmit a logical 1 (indicating that the processor has placed an I/O device
address on the bus), the transceivers compare the pattern created by the switches with that appearing
on Bus Data/Address (BDAL) lines 3-11. If the patterns match, the processor is addressing the
AAV11-A, and the latter prepares to load the DAC holding register identified by decoding bits 1 and 2
of the address word as defined in Figure 4-4.

—‘

Since the AAV11-A makes the comparison only in response to BBS7 (which the processor sets to 1
only in response to an address of 160000 or higher) when address line BD12 = 1, S1 permits assigning
the four DACs any contiguous set of four even word addresses between 170000 and 177770. The
recommended setting for S1 on the first AAV11-A is 170440, illustrated in Figure 4-5. Since LSI-11 bus
address assignments for the AAV11-A extend from 170440 to 170476, up to four AAVI11-As can be
accommodated on the same processor.

AAVii-A
15

ADDRESS WORD

,08

, 05

DAC

no =

ADDRESS

DAC

, 02

no = O: WORD OR LOW BYTE
1:HIGH BYTE

MODE

170440

WORD OR LOW BYTE

170441

HIGH BYTE

170442

WORD OR LOW BYTE

170443

HIGH BYTE

170444

WORD OR LOW BYTE

170445

HIGH BYTE

170446

WORD OR LOW

170447

HIGH BYTE

BYTE
11-4313

Figure 4-4
E

AAVI11-A Address Decoding
o

r_l\ OCTAL EQUIVALENT

B80ARD HANODLE

omunc2Cc

T N
[

Ne
I o]
T
N
[ [ N

wno

£ 3 53 353 K8 3 62 K 6 2 O A e

BOARD

(TT I T T

T T IT T T T

00 01 02 03 04 05 Q6 O7 08 09 10 #1 '12

FINGERS

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Figure 4-5

AAV11-A Address Switches (set for 17044n)

4.4.3 Mode/Level Selector Jumpers
As shipped from the factory, the AAV11-A is set for bipolar operation between -5.12 and +5.12 V.
Unipolar operation and operatlon with other voltage ranges can be achieved by proper changesin the
mode/level jumpers (illustrated in Figure 4-2). See AAV11-A Installation and Service chapter for
details.

4.5

INTERFACING TO OUTPUT DEVICES

4.5.1
Ground Connections
Analog output devices such as oscilloscopes may be either grounded or floatlng If the osc1lloscopeis
grounded, either through its power plug or through contact between its chassis and a grounded cabinet, the oscilloscope ground should not be connected to any of the AAV11-A ground pins. Doing so
may result in a ground loop which will adversely affect scope control results as well as any ADV11-A
operations. If the oscilloscope is floating, its ground should be connected to the AAV11-A logic
ground, pins L, N, R, or T of the Berg connector. Note that the foregoing assumes that the computer
power supply ground is connected to power line (earth) ground. If continuity checks reveal no such
connection, attach a length of 12-gauge wire between the power supply ground and a convenient point
associated w1th earth ground.
—

4-6

Oscilloscope X and Y inputs may be either differential or single-ended. Differential inputs should be
driven as in Figure 4-6.

AAVII-A

‘

OSCILLOSCOPE

X OUT (PIN VV)

ANALOG GROUND (PIN UU)

t).l

N~ s

X _IN

R
\_/'

X_RETURN

Y IN

<
£

O
O

Y OUT (PIN TT)

ANALOG GROUND (PIN H H)

Y _RETURN

11-4523

Figure 4-6 Connection to Oscilloscope with Differential Input
When oscilloscopes with single-ended inputs are involved, the AAV11-A analog grounds (pins UU

and HH) are not used. Return path for X and Y signal currents is through ground for a grounded
oscilloscope or through logic ground (pins L, N, R, or T) for a floating oscilloscope. Since the

grounded, single-ended oscilloscope sees an input voltage which is the sum of the AAV11-A output
and the ground difference voltage between the oscilloscope and the AAV11-A, noise and line frequency errors may be minimized by plugging the scope into an ac socket as close as possible to the computer. Running single-ended scopes in a floating configuration will eliminate noise and line frequency
errors which are due to ground voltage differences.
4.5.2

Twisting

The effect of magnetic coupling into the scope input lines can be minimized for a differential-input
scope by running the AAV11-A output and its return line in a twisted pair. No benefit is derived from
a twisted pair with a single-ended scope input.

4.5.3

Shielding

The effect of electrostatic coupling into the scope input lines can be minimized by shielding the input
lines from AAV11-A to the scope. The shield should be connected to ground at one end only. Ground

ing the shield at both ends may result in a ground loop which will adversely affect scope control results
and any ADVI11-A A/D operations.

4.5.4

Drive Capability

Careful selection of cabling is essential. The D/A outputs are capable of driving a maximum of 5000

pF Output impedance is 1 ohm. Output current limit is 5 mA.
4.6

PROGRAMMING

All four DAC holding registers are automatically set to zero on system initialization. This produces
~5.12 V at the DAC outputs when the mode/level jumpers are connected as delivered from the factory.
Any holding register value remains in effect until changed by the processor in response to a program
instruction. Coding to the D/A converters is offset binary for bipolar operation and straight binary for
unipolar operation. Offset binary defines 0 as maximum negative voltage, mid-point (i.e., 4000 for the
12-bit AAV11-A) as 0 V, and all 1s (7777s) as maximum positive voltage. These relationships are
illustrated in Table 4-1.

Table 4-1

AAV11-A Digital-to-Analog Conversions*

Bipolar
Input Code | £2.56 V

(octal)
0000
0001
3777
4000
4001
77777

Unipolar

+5.12V

+10.24V | 0Vito+5.12V | 0Vto +10.24V

(volts)

—2.56

—35.12
—5.1175

—10.24
—10.235

+0.0

—2.55875

+0.00125

+0.025

—0.00125
0.0

—0.0025
0.0

—0.005
0.0

| +2.55875
+2.56

+0.00125
+2.55875

+0.0025
+35.1175

+0.005
+10.235

+2.56125
+5.11875

+5.1175
+5.12
+5.1225
+ 10.2375

(volts)

* Offset binary for bipolar, straight binary for unipolar operating modes. Conversions may be made between 2’s
complement signed binary and offset binary numbers by subtracting 4000; from the 2’s complement number

(or adding 40005 to the offset binary number) and using only the low order 12 bits of the result.
T

Note that in all ranges, actual maximum positive voltage output is 1 LSB less than nominal maximum positive
output.

CHAPTER 5
DRV11 PARALLEL LINE UNIT

5.1

GENERAL DESCRIPTION

The DRV11 is a general-purpose interface unit used for connecting parallel-line TTL or DTL devices

to the LSI-11 bus over up to 25 feet of cable. It permits program-controlled data transfers at rates up to
44K words per second (with optimized programming) and provides LSI-11 bus interface and control
logic for interrupt processing and vector generation. Data is handled by 16 diode-clamped input lines
and 16 latched output lines. Device address is user-assigned and Control/Status Registers (CSR) and
Data Registers are compatible with PDP-11 software routines.

BDALO - 15L

BDAL O-15 L

>
ADDRESS
AND I/0

BWTBT L

gch)fiTLL

g?fi%l{_

DRCSR

]

L
gg%c"
BDAL O-15 L

Losic

INT ENB B

g%fi%t

g
?'

INTERRUPT
>

INT ENB A

BIRQ L

o
>

BDAL O-15 L

CSRI
NEW DATA RDY

A INIT

’

B INIT
|

TO /FROM

USER
~ DEVICE
LOGIC

O B

CONTROL |

LOGIC

REQ A

‘

out 0-15 [ |

DROUTBUF

DRINBUF

CSRO

DATA TRANS

IN 0-15

S——

cp-1808

Figure 5-1
5.2

DRV11 Parallel Line Unit

JUMPER-SELECTED ADDRESSING AND VECTORS

5.2.1 Locations

Jumpers for device address and vector selection are prov1ded on the DRV11 as shownin Flgure 5-2.
Jumpers are installed at the factory for address 167770 (DRCSR) and vectors 300 (interrupt A) and
304 (interrupt B). These can be cut or removed by the user to program the module for his system
application, as described in the following paragraphs.
|
|

5-1

[

e vpER ]

VECTOR JUMPERS

.ve|
v7
L - _=_

JUMPERS ||
ADDR
F ADDRESS
As |
| a3
AlL

: fig
| A7

L AR8—

Al2 |

__ _ _ _ _

Loy
SL2
.,8L
SLt
OPTIONAL EXTERNAL

CAPACITOR
(SEE PARA.53.6)

[

M7941 ETCH REV. C

Figure 5-2

cP-1809

DRYVI11 Jumper Locations

5.2.2

Addressing
Jumpers involved with addressing include A3 through A12. Only address bits 03 through 12 are programmed byjumpers for DRV11 addressing, producing the 16-bit address word shownin Figure 5-3.
The appropriate jumpers are removed to produce logical 1 bits; jumpers are installed to produce
logical O bits.

5.2.3 Vectors
Jumpers involved with vector addressing include V3 through V7. Only vector bits 03 through 07 are
programmed by the jumpers for DRV11 vector addressing, producing the 16-bit word shown in Figure
5-4. The appropriate jumpers are removed to produce logical 1 bits; jumpers are installed to produce
logical O bits.

5-2

8857 L

—_

}

l
0

—

[

)

O=low
byte (0O-7)

—

BYTE SELECT

1= high byte(8-15)

00X
= DRCSR

ADDRESS JUMPERS:

0% L DROVIBUF

INSTALLED =0

Figure 5-3

DRYVI11 Device Address

[

I
i~

>
N

Tol

VECTOR

JUMPERS:

L (DRCSR-15)

REQUESTING DEVICE

0:=REQ
A

1 =REQ
B

INSTALLED=0
REMOVED

Figure 5-4

5.3

CP-1745

DRVI1 Vector Address

INTERFACING TO THE USER’S DEVICE

5.3.1

General
Interfacing the DRVI11 to the user’s device is via the two board-mounted H854 40-pin male connectors. Pins are located as shown in Figure 5-5. Signal pin assignments for input interface J2 (connector no. 2) and output interface J1 (connector no. 1) are listed in Table 5-1. The proper Berg-to-Berg
cable is a BCO8R. The proper Berg to open-ended cable is a BC04Z. Connection to the DRVI11 can be
made through the H322 Distribution Panel (see Figure 2-8). This unit is provided with decals, which

when applied according to instructions on the decal sheet, identify the H322 screw terminals with
respect to the associated pins on the DRV11 Berg connectors (A, B, UU, VV, etc.). Space is provided
on the decal for specific user identification. Note that DRV11/H322 terminal relationships assumed
by the decal sheet rest on connection of the BCO8R cable so that stamped labels on female cable ends
match embossed labels on male connectors - A/B to A/B, UU/VV to UU/VV. This normally means
‘that any “‘this side up” labels face away from the board on which the male connector is mounted.

Each BC04Z cable from a DRV11 may be terminated in a female 25-pin connector such as a DB25S

type (DEC #12-09326-00) socket. The user may assign the signal and ground lines from the BC04Z to
- specific connector pins. User apparatus may be connected into the socket by means of a male 25-pin
connector such as a DB25P type plug (DEC #12-05886-00).

5.3.2
Output Data Interface
The output interface is the 16-bit buffer DROUTBUF. It can be either loaded or read under program
control. When DROUTBUF is loaded by the CPU, the NEW DATA READY H 300 ns pulse is

generated to inform the user’s device of the data transfer. In order to allow data to settle on the
interface cable, the trailing edge of this positive-going pulse should be used to strobe the data into the
user’s device. The system initialize signal (BINIT L) clears DROUTBUF. When an output line is set to
logical 1, the TTL output is high (= 2.7 V); when an output is set to logical 0, the TTL output is low
(£ 0.5V).

|
5-3

H854
CONNECTOR

H856 CONNECTOR

(SHOWN WITH
CABLE

INSTALLED)

t1-3294

Figure 5-5

J1 or J2 Connector Pin Locations

All output signals are TTL levels capable of driving five unit loads (8 mA sink** @ 0.5 V, 400 uA
source*** @ 2.7 V) except for the following:

NEW DATA READY
= 10 unit loads

=16 mA sink** @ 0.4 V, 400 uA
|

source*** @ 24 V

INIT (Initialize)* = 10 unit loads/connector

DATA TRANSMITTED
= 30 unit loads

=48 mA sink** @
source*** @ 2.7V

0.4

*Common signal on both connectors.

** Sink refers to current from external +5 V supply through load to output line when output is low.
***Source refers to current from output line through load to ground when output is high.

5-4

Table 5-1

DRYV11 Input and Output Signal Pins*

Inputs

Outputs

Signal

Connector]

Signal

INOO

12|

OUT00

Connector | Pin

INO1

OUTO1

INO2

H. E

OuUTO02

INO3

OuUTO03

INO4

OuUTO04

INOS

OUTO0S

INO6

OUTO06

INO7

CcC

OuUTO7

INO8

OUTO8

INO9

ouTO09

IN10

A4/

OUT10

IN11

OUTI11

IN12

OUTI12

IN13

OUT13

IN14

OuT14

IN15

OUTI1S

REQA

NEW DATARDY*

REQB

DATA TRANS*

J2
J2

C
K

INIT

J1
J1

DD
P

INIT

RR, NN

CSRO
CSRI1

*Pulse signals, approximately 300-ns wide. Width can be changed by user.

5.3.3

Input Data Interface

The input interface is the 16-bit DR}NBUF read-only register, comprising gated bus drivers that
transfer data from the user’s device onto the LSI-11 bus under program control. DRINBUFis not
Lapable of storing data; hence the user must keep input data on the IN lines until read by the LSI-11

microprocessor. When it has read the data, the DRV11 generates a positive-going 300-ns DATA

TRANSMITTED H pulse which informs the user’s device that the data has been accepted. The trail- ing edge of the pulse indicates that the input transfer has been completed.
All input and request signals are one standard TTL unit load; inputs are protected by diode clamps to
ground and +5 V. A +2.7 V to +5 V input is read as logical 1; 0 V to 0.5 V as logical 0.
5.3.4

Request Flags

Two signal lines (REQ A H and REQ B H) can be asserted by the user’s device as flags in the DRCSR
word. REQ B is available via connector no. 2 and can be read in DRCSR bit 15. REQ A is available
via connector no. 1; it can be read in DRCSR bit 7. Two DRCSR interrupt enable bits, INT ENB A
(bit 6) and INT ENB B (bit 5), allow automatic generation of an interrupt request when their respective REQ A or REQ B signals are asserted. Once the user’s request signal has been asserted (logical 0 to
logical 1 transition), it must remain asserted until the CPU completes interrupt processing. At this
time, DATA TRANSMITTED or NEW DATA READY signals (see Paragraphs 5.3.2 and 5.3.3) can
be used to cancel the request. Note that Request A has a higher priority than Request B, and that each
of the interrupt enable bits can be set or reset under program control.
* Ground pins for connector J1: J, M, S, V, Y, CC, EE, KK, MM, PP, SS, UU. Connector J2: J, L, R, T, X, AA, DD, JJ,
MM, PP, SS, UU.

5-5

5.3.5 Initialization
The BINIT L processor-generated initialize signal is apphed to DRVI1 circuits for interface logic
initialization. It is also available to the user’s circuits via connectors J1 and J2 as follows:

Connector / Pin

Signal
AINITH
BINIT H
BINIT H

J1/P
J2/RR
J2/NN

An active BINIT L signal will clear the following: DROUTBUF data; DRCSR bits 6, 5, 1, 0: bits 16
and 7 (when the maintenance cableis connected) and Interrupt Request and Interrupt Acknowledge
flip-flops.

5.3.6

NEW DATA READY and DATA TRANSMITTED Pulse Width Modification

An optional capacitor can be added by the user to the DRV11 module to extend the pulse width of
both the NEW DATA READY and DATA TRANSMITTED pulses. The module without external
capacitance (as shipped) will produce 300 ns pulses. The capacitor can be addedin the location shown
in Figure 5-2 to produce the approximate pulse widths listed below.

Optional External

Approximate
Pulse Width (ns)

Capacitance (pF)
None

300

1200

5.4
5.4.1

1800

500
600

6000

1200

PROGRAMMING
Addressing

Addresses for the DRV11 can range from 160000 through 17777X5. The lcast significant three bits
address the desired DRV11 register as follows:
Address*

Device Register

1 XXXXO0
1 XXXX2

DRCSR
DROUTBUF

1XXXX4

DRINBUF

Addresses 177560-177566 are reserved for the console device and should not be used for DRV11
addressing. The following address assignments are normally used:
First DRV11
DRCSR =167770

DROUTBUF = 167772
DRINBUF = 167774

Second DRVI11
167760 to 167764
Third DRVI11
167750 to 167754

*Address 1XXXX6 will not produce a response from the DRV11.

5-6

Second DRV11
167760 to 167764

Third DRV11
167750 to 167754
5.4.2

Interrupt Vectors

Two interrupt vectors are jumper-selectedin the range of 0 through 37X;. The least significant three
bits identify the interrupting function.

000xx0

000xx4

InterruptA

Interrupt B

Vectors 60 and 64 are reserved for the console device and should not be used for DRV11 vectors.
5.4.3

Word Formats

The three word formats associated with the DRV 11 are shown in Figure 5-6 and are described in Table
5-2.

5.4.4

1/0 Timing

1/0 transfers through the DRV11 occur as illustrated in Figure 5-7.

DRCSR

]

REQUEST B

INTENBB

REQUEST A |

(READ ONLY) | (READ/WRITE)

(READ ONLY)

INT ENB A

DROUT

CSRO

(READ/WRITE)

(READ / WRITE)

CSRI

(READ/WRITE)

DATA OUT

15
DRINBUF

(READ/WRITE)

DATA IN

‘

Figure 5-6

(READ ONLY)

DRV11 Word Formats

5-7

CP-1746

Table 5-2 Word F orinats
Word

Bit(s)

Function

DRCSR

REQUEST B — This bit is under control of the user’s
device and may be used to initiate an interrupt sequence or to generate a flag that may be tested by the
program.

When used as an interrupt request, it is asserted by
the external device and initiates an interrupt provided

the INT ENB B bit (bit 05) is also set. When used as a

flag, this bit can be read by the program to monitor external device status.

When the maintenance cable is used, the state of this
bit is dependent on the state of CSR1 (bit 01). This
permits checking interface operation by loading a 0 or

1 into CSR1 and then verifying that REQUEST B is

the same value.
Read-only bit. Cleared by INIT when in maintenance
mode.

14-08
07

Not used. Read as 0.

REQUEST A — Performs the same function as REQUEST B (bit 15) except that an interrupt is generated
only if INT ENB A (bit 06) is alsoset.

When the maintenance cable is used, the state of RE
QUEST A is identical to that of CSRO (bit 00).
Read-only bit. Cleared by INIT when in maintenance
mode.

INT ENB A — Interrupt enable bit. When set, allows
an interrupt request to be generated, provided REQUEST A (bit07) becomes set.

Can be loaded or read by the program (read/write
bit). Cleared by BINIT.

035

04-02

INT ENB B — Interrupt enable bit. When set, allows
an interrupt sequence to be initiated, provided REQUEST B (bit 15) becomes set.

Not used. Read as 0.

Can be loaded or read by the program (read/write
bit). Cleared by INIT.

Table 5-2
Word

Bit(s)

DRCSR

Word Formats (Cont)
Function

CSR1 — This bit can be loaded or read (under program control) and can be used for a user-defined com-

mand to the device (appears only on Connector No. 1).

When the maintenancecableisused, setting or clearing
~this bit causes an identical state in bit 15 (REQUEST
B). This permits checking operation of b1t 15 which
cannot be loaded by the program.

—

Can be loaded or read by the program (read/write
bit). Cleared by INIT.

CSRO
— Performs the same functions as CSR1 (blt 01)' o
but appears only on Connector No. 2.
“When the maintenance cable is used, the state of this
bit controls the state of bit 07 (REQUEST
A).

Read/write bit. Cleared by INIT.
DROUTBUF

Output Data Buffer - Contains a full 16-bit word or
one or two §-bit bytes ngh Byte = 15-8; Low Byte
= 7-0.

| Loading is accomplished-under a program?'contro]led
DATO or DATOB bus cycle. It can be read under a
~

DRINBUF

15-00

program-controlled DATI cycle.

Input Data Buffer — Contains a full 16-bit word or

one or two 8-bit bytes. The entire 16-bit word is read
under a program-controlled DATI bus cycle.

5-9

_Sdata=1>

DRINBUF

CIN@D: IN15 > are set /reset by the

user; the data must remain stoble until
trailing edge of DATA TRANSMITTED

{data=1>
N\

{data=0>

s e

cres

D CIDD oETh CGIND CIOED GOUID WDUD GGG GSNDy CMIID

oEm emD CTms

DD Sl G

{data=0>
S

e0ITD R e

.
11 when the
Pulsed by DRV
11/ 03 reads data from the DRV

— TRAILING EDGE

READ DATA FROM BUFFER—
REQUEST B

——D—
—— — —

2300 ns

DATA TRANSMITTED

WAIT FOR A RESPONSE TO
THE INTERRUPT REQUEST

Set by user when ready to transmit new
data to the 11/03; reset by user upon
trailing edge of DATA TRANSMITTED

DRCSR

Interrupt Enable B
{bit 5
Set by user to allow interrupt-driven
data transfer.

DRCSR

{ bit 15>Request B flag

)

Indicates state of REQUEST A line.
11-4588

{data=1)

T ————— \\
T—==mEsEmsms

OoROYTBUF

{OUTOD: OUT15) are set/reset
11 under control of
by the DRV

{data=@>

the 11/03

f
|
|

{data= 0>

S——————————

2300ns

NEW DATA READY

Pulsed by DRVI1 when the

11/ 03 writes data to the DRV i1
.

WRITE DATA 70 BUFFER —
)

So——
i
t—
——

—

——

—

——

—

{ bit 6> Interrupt Enable A
Set by user to allow interrupt-driven
data transfer.

—

DRCSR

aw——

w—) ——

Set by user when ready for new data
from 11/03; reset by user upon
trailing edge of NEW DATA READY

WAIT FOR A RESPONSE TO
THE INTERRUPT REQUEST

—

REQUEST A

—TR'AILlNG EDGE, DATA STABLE

DRCSR

. { bit 7> Request A flag.
Indicates state:of REQUEST A line.
11-4589

Figure 5-7

DRYVI11 Interface Signal Sequence

5-10

CHAPTER 6

ADV11-A, KWV11-A, and AAV11-A MAINTENANCE

6.1

MAINTENANCE PHILOSOPHY

Digital logic circuitry in the ADV11-A, KWV11-A, AAV11-A, and DRV11 is to be repaired in the
normal manner. Analog circuitry, however, is to be repaired only at the factory. If any analog failures
occur in the field, modules are to be board-swapped and returned to the factory for repair. Installations performed by DEC include installation of DEC-supplied equipment only. The customer 1is
responsible for wiring from his equipment to the H322 Distribution Panel or to the end of the DECsupplied cable.

6.2
6.2.1

ADVI11-A ANALOG-TO-DIGITAL CONVERTER
Installation

6.2.1.1 Location - The ADV11-A is a single-module option which interfaces to an LSI-11 or PDP11/03 through one of the quad locations in the LSI-11 backplane or in an expander box. Within the
constraints imposed by the LSI-11 bus structure (refer to the LSI-11, Microcomputer Handbook - EB06583 76 09/53) the unit may be mounted in any available location and will operate within specifications, regardless of proximity to the progessor, memory, or other DEC options. Where circumstances
permit, however, analog performance may be improved beyond specification levels by installing the
unit away from the processor, memory modules, or other noise-producing options. Note that priority
transfer requires that no empty unstrapped locations exist in the backplane between the processor and
any device that communicates with it.

6.2.1.2 Address and Vector Selection — Select and set CSR and Vector addresses as indicated in Paragraph 2.4.3.4. Note that where more than one ADV11-A is involved, CSR addresses must be four
locations apart (e.g., 170400, 170404, 170410, etc.). Vector addresses must be 10g locations apart (e.g.,
000400, 000410, 000420, etc.). Remember to reinstall any covers removed from switch packs S1 and S2.
6.2.1.3 Board Insertion — Select a quad location, and making sure that the keyed edge connector
matches the physical configuration of the terminal block, apply firm pressure alternately to the extractor handles near the opposite corners of the board until it is squarely and fully seated in the connector.

6.2.1.4 Test Connector — Do not insert I/O cables into the Berg connector at this point. Instead,
insert the 7012894 test connector, which establishes the conditions required by the ADVII
Wraparound Test - that is, all channel inputs are grounded except 1, 2, 3, and 17, with internally~ generated +4.5 V signal on channel 1, -4.5 V signal on channel 2, ramp signal on channel 3, and
provision for external reference voltage on channel 17.

6.2.1.5 Shields - Install the 1700021-02 electromagnetic shields on both sides of the ADV11-A.
Shields are insulated on both sides and physically separate the ADV11-A from adjacent modules but
are not electrically connected to the system.

6-1

6.2.1.6

Acceptance - Conduct an acceptance test as specified in A-SP-ADV11A.

6.2.1.7

Final Connections

Cables

Remove the 7012894 test connector and install the BCO8R cable (ADV11-A to H322 Distribution
Panel) or the BC04Z cable (ADV11-A to user devices) in the ADV11-A Berg connector. Connect
BCO8R at both ends so that the stamped labels on the female cable ends match the embossed labels on
the male connectors - A/B to A/B, UU/VV to UU/VV. This normally means that any “‘this side up”
labels face away from the bodrd on which the male connector is mounted.
- NOTE
The BCOS8R cable is symmetrically wired but for several reasons is unsymmetrically labeled. That is,
wires identified as A and B on one end are identified
as UU and VV on the other end.

To simplify system relationships, the H322 PC
board compensates for this inversion on the PC
board that distributes Berg connector signals to front
panel screw terminals. For this reason, the user can
connect both ends of the BCO8R according to the
labels, A/B to A/B and UU/VV to UU/VYV. So connected, signals from the ADV11-A will properly
appear at front panel terminals which have been
labeled according to the instructions on the ADV11A decal sheet. Each BC04Z cable from an ADV11-A
may be terminated in a female 25-pin connector such

as a DB25S type (DEC 12-09326-00) socket. The

user may.assign the signal and ground lines from the
BC04Z to specific connector pins. User apparatus
may be connected to the socket by means of a male
25-pin connector such as a DB25P type plug (DEC
12-05886-00).

If KWVI1I1-A is present, connect Faston terminals, as described in Paragraph 2.4.3.2.
Manual Voltage Control

Applications which require variable dc voltages to be applied to one or more channels of the ADV11A can be implemented by the circuit illustrated in Figure 6-1. Note that the H323-B Potentiometer Box
may not be used with the ADV11-A.
6.2.2

ADVI11-A Circuitry

The digital interface and control logic of the ADV11-A conforms in general to standard DEC practices
and should be understandable to qualified technicians who have access to ADV11-A print sets and are
familiar with overall ADV11-A functions as described in Chapter 2. Since the analog power supply
and the A /D conversion sections involve some nonstandard circuits, they are discussed below.

6.2.2.1

ADVI11-A Analog Power Supply

General

The £15 V power for the analog circuits is derived from a dc-dc converter which consists of three basic
sections: a 12 V power switch, positive and negative voltage doubler diode-capacitor banks, and a dual.
tracking voltage regulator. Output jumpers (W1 and W2) are provided to permit removing the load for
troubleshooting purposes.
6-2

!'
|

—

o—

’ L]

AAA
\AA/

_._._._..._.._.r_.._l..'a..,_.__'

]
|

IN759A ;
12V fi:

|'
|
|

|
.

Ve9V

(MINIMUM)

22 L
WF
b

CH.

I
|

]

A/Diinput

K$4. to A/D input |

5K:§A‘io A/D input |

1o
5K§L“*
|

]

—
oV —_—
(MINIMUM) T
Vg+

‘

/7 7

______ J...__L.,Lv.._.__l.

AVAVAV

RET

NOTE:

Value of Rin kilohms can be calculated as follows:
Vg -6

2.5 (N+2)
Where

N = Number of channel

(1)
pots.

Current drain from battery in milliamps when R is
selected with equation (1) can be calculated as
follows:

Toot= 2.5 (N+2)mA

(2)
11-4487

Figure 6-1

Battery-Operated Potentiometer Box for ADV11-A A /D Converter
TP3

POSITIVE

VOLTAGE

SWA

+ 15V

DOUBLER

DUAL

VOLTAGE

ggfigg:

REGULATOR

SW B ——

TP2

)

NEGATIVE

VOLTAGE

- 15V

DOUBLER

Figure 6-2 Analog Power Supply Block Diagram
,

Power Switch

switch and provide a0 V to
Transistors Q15 and Q16 constitute the output stage of the 12 V powersignals,
and which drives the
B
SW
+12 V switching signal, which is derived from the SW A and
on faster than they
turn
switches
r
transisto
voltage doubler diode-capacitor banks. Since saturated
at the same time.
on
never
are
Q16
and
S
Q1
that
turn off, an idle is included (see Figure 6-3) to ensure
Voltage Doublers

6-4) and a charge
_ The basic voltage doubler consists of a charge transfer stage (D and C4 in Figure
charges to V C,
V,
0
at
is
output
switch
power
the
When
6-3).
Figure
storage stage (Dp and Cp in
charge is
Vpa (+11.3 V). When the power switch output goes to +12 V, D, is reverse-biased and
Dp and
asing
transferred from Ca to Cp. The power switch output then returns to 0 V, reverse-bi
recharging Ca - Da. The voltage on Cp builds up to approximately +12 V - Vpa +12 V - Vpp.
6-3

CLOCK H

SW A L

]

- T

|
|

B L
SW

+12V

POWER
SWITCH
OUTPUT

= IDLE-TIME

1o = SWITCH ON TIME

11-4479

DC-DC Converter Signals

Figure 6-3

(]

POWER

SWITCH
OUTPUT

> Vour

AY!

Vin= +12V

;\CB

+12V
Qv
11-4480

Figure 6-4

Basic Positive Voltage Doubler

The negative voltage doubler operates in a similar manner and consists of two basic doubler circuits in
cascade with an additional input negative voltage generating stage (D26 and C47).
|

Dual Voltage Regulator

The dual voltage regulator comprlses an LM325N (ESO) tracking regulator and power boosters (Q17
and Q18). Output current limit sensing is provided by R60 and R61. This stage regulates the outputs
from the doubler circuits-to provide the £15 V of analog power required by the various analog circuits.

6.2.2.2 ADVI1I-A A / D Conversion Circuit- The ADV11-A A/D converter circuit utilizes 4 patented
auto-zeroing, successive approx1mat10n technique. The basic components of this circuit are illustrated
in Figure 6- 5.

Analog Multlplexer

The analog multiplexer consists of two 8-channel, single-ended multiplexer ICs (E47 and E48) whose
outputs are connected together, thus forming a 16-channel multiplexer. During sample, when no conversion is in process, the addressed multiplexer channelis on. During hold, two conditions are possible. If single-ended (SE) mode is picked, all channels of the multiplexer are off and the auto-zero
switch is on. If SE mode is not picked, the negative 51de of the selected quasn-dlfferentlai pair is
selected.

6-4

J1-INPUTS

AY
/1

VOLT.

REF,

bos

16 — CHANNEL
ANALOG

EsH

SAMPLE ~-AND-HOLD

MUX

12-BIT

lE?

SWITCH

ADZC

4
L A

AUTO - ZERO

FEEDBACK

AAA

NODE

FEEDBACK
PREAMPLIFIER

—&
>~

FEEDBACK

SIGNAL

SWITCH

—Q
HOLD

8-8BIT
VERNIER
D/A

SUCCESSIVE

APPROXIMATION
REGISTER

DATA
BUFFER

COMPARATOR

(SAR)
11-4481

Figure 6-5 ADVI11-A A/D Conversion Circuit Block Diagram
Auto-Zero

During sample, the feedback signal switch (QS5, Q6, Q8, Q9, Q10, and Q11) connects the output of the
feedback preamplifier (Q2 - Q4) to the input of the sample-and-hold (Q13, E31, C67), thus completing
the amplifier feedback path and allowing the sample-and-hold to track the analog input (see Figure 66).

NODE

EsH

FEEDBACK D/A

Eos2

VERNIER D/A

¥ PREAMP, SIGNAL SWITCH

AND SAMPLE-AND-HOLD

11-4482

Figure 6-6

A/D During Sample

6-5

TIEHE

Summing currents into the Y node:
., - E

E, +E
0S1
=1

E.,
0s2 . _SH

-E

0S2

(1)

-1,

Eos; is the offset of the input buffer amplifier (E49) and Eps; is the offset of the feedback

preamplifier.

/ When a conversion is initiated, the feedback signal switch disconnects the output of the feedback
preamplifier from the input of the sample-and-hold, thus storing the signal, and connects the preamplifier output to the comparator (Q7 and Q12) input. Next, the A/D input, E;, is either switched to
the negative channel or is grounded through the auto-zero switch, E44, depending upon whether or not
single-ended operation was selected.
|
At the completion of the conversion, the 3~ node is ideally equal to Egg,’ (see Figure 6-7).

Esn'

E ost

/"\ +

;::1:::::::>~—__

<:R

Rop

4‘""'7

NODE

‘YL

COMP

Eosa’

l
1,

FEEDBACK D/A

VERNI!ER D/A

Figure 6-7

11-4483

A /D During Conversion

Again summing currents into the 3_ node:

)

D'=E1'+E051 - Eosz'+' ESH"Eosz '_ Iv'f
RD

Where I, * is the feedback D/A current at the completion of the LSB interrogation.
Subtracting equation (2) from equation (1):

e
ID—ID’=El i -(Iy -1, +EOSI‘EOSI _Eos "Eos2'+ Egy EI

6-6

R.//R,

Note that since the offset due to the input buffer is the same in both cases,
E

os1 ~EBosi “Egg; -F
Rp
Rp

Eps2 - EQsy is controlled by R1S5 by forcing an offset shift in the feedback preamplifier and is used to

null the offsg; caused by the sample-and-hold pedestal (Esy - EsH'). Note also that the conversion is
not dependent upon the magnitude of EQg), but upon the forced shift. Therefore:

I -1p’

_ E, -E/°

- Uy-1y)

Rp
If no vernier offset is programmed, Iy = Iy’,

and:

-1, = -

| '

A /D Conversion

The 12-bit feedback D/A (E46) is initialized to 4000s.

)

Ip = 1/2Tpgp = I1gp

(5)

During conversion, each bit of the feedback D/A is interrogated in sequence by the SAR (E39),
starting with the MSB. At the end of each interrogation interval, the decision of the comparator to
accept or reject that bit is clocked into the SAR where this decision is held. A positive voltage on the >

node will cause the comparator to reject a bit. Because of the overall negative feedback, this process
will cause the > node to work its way toward null (Figure 6-8). After the LSB interrogation, the

contents of the SAR are transferred to the Data Buffer register.

CLOCK

Es
4

+CLAMP

—

REJECT
ov

‘!

———

- CLAMP

comp

/
0}

\__/__
|

MSB

{
LSB
11-4484

F‘igure 6-8

> Node During Conversion
6-7

Since

=0 (@ code =7777)
I,'min
D
and

max = A

I (@ code
= 0000),

equations (4) and (5) permit voltage/current conversions to be derived as illustrated in Table 6-1.

Table 6-1 ADV11-A Voltage/Current/Bit Relationships
I ’

Code

1/2 (1 'SR )

3777‘

Iosg=1sn

0000

ID -1 ’

T I sp
“1/2 (Irgg)

E, -El ’

-k LSB
“1/2 (Epgp)

6.2.2.3 The Vernier DAC - The Vernier DAC is a digital-to-analog converter packaged in a single
chip serving to provide programmable small increment offsets to the summing node of the A/D converter. It has been included in the ADV11-A circuit primarily to facilitate automatic testing of the
module and is used by the diagnostic routines in the measurement of noise, offset error, and interchannel settling error. The Vernier DAC is controlled through bits 07:00 of the Data Buffer register
(write-only), accepting 8-bit offset binary code to produce positive and negative full scale offsets of 2.5
A/D LSBs.

- 6.2.3 ADVI11-A Performance Test MAINDEC-11-DVADA-A)
This diagnostic package permits complete testing of all functional aspects of the ADVII-A. It is
divided into four major routines which are described below. Refer to diagnostic listing MAINDEC-11“DVADA-A for run instructions.

Wraparound Routine - consists
consecutively:

of four subtests which can

be run individually

Analog Test - checks all channels and their outputs to ascertain whether or not multiplexing and gross conversion functions are working.

Noise Test — determines whether or not the amount and distribution of short-term
noise within the A /D converter is within limits.

Interchannel Settling Test - Determines whether or not the A/D converter can recover
from measurements at opposite extremes within specified times (switches aiternately
between channels 1 and 2 - 1.e., between +4.5 V and -4.5 V).

Differential Linearity and Relative Accuracy Test — makes multiple randomized measurements of ramp signal on channel 2 to determine, within 0.01 LSB, the width of the
voltage band corresponding to each of the 4094 finite width states.

Calibration Routine — works interactively with operator to facilitate precise calibration of
A/D. Requires precision voltage source.

6-8

\—/

START

RUN LOGIC

TEST

RUN WRAP-

TROUBLESHOOT

AROUND

AND REPAIR

ROUTINE

LOGIC

_YES /L

\\PASS/, B

)

DONE®

ANALOG

ISOLATE

PROBLEM

LOGIC
A

CHECK +5V

TROUBLESHOOT

& +12v

AND REPAIR

POWER SUPPLY

LOGIC

NO W
1/////:£T\\\\\\. YES
?g; UfsTVP(‘)S"‘

CHECK ANALOG
P
POWER SUPPLY

12y

ANALOG

YES

P.S. O.K.

TROUBLESHOOT

BOARD

AND REPAIR

SWAP

ANALOG P.S.

*Calibration routine can be run at
this point if precision voltage

source (EDC VS-11N or equivalent)
is available.
11-4485

Figure 6-9

ADVI1I-A Troubleshooting Procedure

Print Values routine — works interactively with operator to execute, and if desired, print out
results of conversions on selected channels.

6.2.4

Logic Test Routine - consists of 23 subtests that run sequentially without operator intervention and check status register read/write operation, initialize conditions, A/D done flag
setting and clearing, error flag setting, interrupt functions, etc.
Maintenance

In general, both routine maintenance and specific troubleshooting efforts will follow the flow defined
in Figure 6-9. Preventive maintenance will consist of removing airborne dust accumulations, checking
the power supply levels whenever new devices are added to the system, and running diagnostics whenever performance confirmation is.desired.
6.2.5 Calibration (Requires Precision Voltage Source - EDC VS-11N or Equivalent)
With test connector installed in ADV11-A Berg socket, connect the floating reference voltage to the
two clip-terminated leads (channel 17). Then, run the Calibration Routine and follow the step-by-step
instructions it issues. The program will specify reference voltage settings and indicate when offset and
gain potentiometers (identified in Figure 2-6) should be adjusted.
6.3

KWVI11-A REAL TIME CLOCK

6.3.1

6.3.1.1

Installation

Location - The KWVI11-A is a single-modul¢ option which interfaces to an LSI-11 through

one of the quad locations in the LSI-11 backplane or in an expander box. Within the constraints
imposed by the LSI-11 bus structure (refer to the Microcomputer Handbook - EB-06583 76 09/53), the
unit may be mounted in any available location. Note that LSI-11 priority transfer requires that no
empty unstrapped locations exist between the processor and the last device connected to the LSI-11
bus.
6.3.1.2

Address and Vector Selection - Select and set CSR and Vector Addresses as indicated in

Paragraphs 3.4.3.1 and 3.4.3.2. Note that where more than one KWV11-A is connected to the same
bus, CSR addresses must be four locations apart (e.g., 170420, 170424, 170430, etc.). Vector addresses
for multlple KWV11-As must be 105 locations apart (e.g., 000440, 000450, 000460, etc.). Remember to

reinstall any covers on switch packs S1 and S3.

6.3.1.3 Board Insertion — Select a quad location, and making sure that the KWV11-A board is oriented so that the keyed edge connector matches the physical configuration of the terminal block, apply
firm pressure alternately to the extractor handles near the opposite corners of the board until it is
squarely and fully seated in the connector.

6.3.1.4 Test Connections - Do not connect user equipment to Berg connector J1 at this time. Diagnostic [/O signal tests will require jumpers between specified pins on JI.
6.3.1.5
6.3.2

Acceptance — Conduct an acceptance test as specified in A-SP-KWV11-A-3.
Final Connections

Install FAST ON connectors between CLK/ST1 tabs and ADV11-A tabs as required. Install the
BCO8R cable (KWVI11-A to H322 Distribution Panel) or BC04Z cable (KWVI11-A to user devices)
between the Berg connector (J1) and the appropriate terminus. Connect the BCO8R at both ends so
that the stamped labels on the female cable ends match the embossed labels on the male connectors A/Bto A/B, UU/VV to UU/VV. This normally means that any *“‘this side up” labels face away from
the board on which the male connector is mounted. (See Note in Paragraph 6.2.1.7.)

6-10

6.3.3 KWVI11-A Circuitry
The digital logic of the KWV11-A conforms in general to standard DEC practices and should be
understandable to qualified technicians who have access to KWV11-A print sets and are familiar with
KWVI11-A functions as described in Chapter 3.

6.3.4

KWV11-A Diagnostic MAINDEC-11-DVKWA-A-D)

6.3.5

Maintenance

The KWVI11-A diagnostic is divided into two main routines, the first designed to test logic functions
on up to four KWV11-A modules, the second to test selected module I/O functions, ST1, ST2, and
clock overflow. Refer to diagnostic listing MAINDEC-11-DVKWA-A-D for run instructions.
Preventive maintenance consists of removing airborne dust accumulations, checking that power supply levels remain within specifications whenever new devices are added to a system, and running

diagnostics whenever performance confirmation is desired.
6.4 AAV11-A DIGITAL-TO-ANALOG CONVERTER
6.4.1

Installation

6.4.1.1 Location - The AAV11-A is a single-module option which interfaces to an LSI-11 or PDP11/03 through one of the quad locations in the LSI-11 backplane or in an expander box. Within the
constraints imposed by the LSI-11 bus structure (refer to the Microcomputer Handbook — EB-06583 76
09/53) the unit may be mounted in any available location and will operate within specifications,
regardless of proximity to the processor, memory, or other DEC options. Where circumstances permit,
however, analog performance may be improved beyond specification levels by installing the unit away
from the processor, memory modules, or other noise-producing options. Note that priority transfer
requires that no empty unstrapped locations éxist in the backplane between the processor and any
device that communicates with it.

6.4.1.2 Address Selection - Select and set address as indicated in Paragraph 4.4.2. Note that the least
significant three bits of the address word are reserved for software addressing of the four digital-toanalog converters (DACs) and are therefore not selectable on the switch pack. For this reason, if
several AAVI11-As are installed on a system, they must be assigned addresses that are 10s locations
apart.

6.4.1.3 Board Insertion — Select a quad location on the connector block, and making sure that the
AAV1I1-A board is oriented so that the keyed edge connector matches the physical configuration of the
connector block, apply firm pressure alternately to the extractor handles near the opposite corners of
the board until it is squarely and fully seated in the connector block.
6.4.1.4 Test Connectors — If AAV11-A signals are to be routed to the H322 Distribution Panel,
connection may be made to that unit at this time (see Paragraph 6.4.2). Otherwise, leave the Berg
connector empty to allow for monitoring AAV11-A output signals in the next step.

6.4.1.5

Acceptance Test - Conduct an acceptance test as described in the AAV11-A Manufacturing

and Field Acceptance Procedure (A-SP-AAV11-A-3).
L}

6.4.2

Final Connections

Install the BCO8R cable (AAV11-A to H322 Distribution Panel) or BC04Z cable (AAV11-A to user
devices) between Berg connector (J1) and the appropriate terminus. Connect BCO8R at both ends so
that the stamped labels on the female connectors match the embossed labels on the male connectors A/BtoA/B,UU/VV to UU/VV. This normally means that any “this side up’’ labels face away from
the board on which the male connector is mounted. (See Note in Paragraph 6.2.1.7.)

6-11

" 6.4.3

Mode/Level Selection

As shipped from the factory, the AAV11-A is set for bipolar operation between -5:12 V and +5.12 V.
Unipolar operation and operation in other voltage ranges can be achieved by proper changes in
mode/level jumpers (illustrated in Figure 4-2). Table 6-2 indicates jumper configurations for all bipolar voltage ranges; Table 6-3.indicates those for all unipolar ranges. Note that each of the four DACs
on any given AAV11-A may be set for a different mode/level condition. Note also that any change
from the factory settings may require recalibration of the DAC involved (see Paragraph 6.4.7).

Table 6-2

Jumper Configurations for Bipolar Operation
+5.12V

+10.24V

OUT

OUT
IN
IN

OUT
OouT
IN

IN
OUT
IN
IN

IN
OoUT
OuUT
IN

OUT
IN
OouUT
IN

IN
OoUT
IN
IN

IN
OUT
OuT
IN

OouT
IN
ouT
IN

IN
OouT
IN
IN

IN
OUT
OouUT
IN

OouUT
IN
OouUT
IN

+2.56 V
DAC1

W4
W5
W6
DAC?2

W7
W8
W9
W10

DAC3

Wil
W12
W13
W14

DACA4

W15
W16
W17
W18

IN
OouUT
IN

6.4.4 AAV11-A Circuitry

The digital interface and control logic of the AAV11-A conforms in general to standard DEC practices
and should be understandable to qualified technicians who have access to AAV11-A print sets and are
familiar with overall AAV!1-A functions as described in Chapter 4. The analog power supply and the
digital-to-analog circuitry, however, make use of techniques and components with which DEC technicians may not be familiar. Since the analog power supply and the D/A conversion sections involve
some non-standard circuits, they are discussed below.

6.4.4.1

AAV11-A Analog Power Supply

General (see Figure 6-1)

The £15 V power for the analog circuits is derived from a dc-dc converter which consists of three basic
sections: a 12'V power switch, positive and negative voltage doubler diode-capacitor banks, and a dual

tracking voltage regulator.

Table 6-3

Jumper Configurations for Unipolar Operation
0V-+4512V

0V-+10.24V

DAC1

W5
W6

OUT

IN
OouUT
IN
OuUT

IN
OouT
OouT
ouT

IN
OuUT
IN
OuUT

IN
OuUT
OUT
ouT

IN
OuT
IN
OuUT

IN
OuT
OouT
OouT

IN
OouUT

OuUT
OouT

DAC2

W7
W8
W9
W10
DAC3

Wil
W12
W13
Wwl14
DAC4

W15
W16
W17
W18

Table 6-4

AAV11-A Input Code/Output Voltage Relationships

Input Code |

Unipolar

Bipolar

0000
4000

’
ov
1/2 FS
+FS-1/2LSB

-FS
oV
+FS-1/2LSB

7777

Power Switch

Transistors Q2 and Q3 constitute the output stage of the 12 V power switch and providea 0 V to +12
V switching signal, which is derived from the SW A and SW B signals, and which drives the voltage
doubler diode-capacitor banks. Since saturated transistor switches turn on faster than they turn off, an

idle time is included (see Figure 6-2) to ensure that Q2 and Q3 are never on at the same time,

Voltage Doublers

The basic voltage doubler consists of a charge transfer stage (Dy and Cp in Figure 6-3) and a charge
storage stage (Dp and Cp in Figure 6-3). When the power switch output is at 0 V, C, charges to Vi Vpa (+11.3 V) through D . When the power switch output goes to +12 V, Dy is reverse-biased and
charge is transferred from Cy to Cp through Dg. The power switch output then returns to 0 V, reversebiasing Dy and recharging Cp through D4. The voltage on Cg builds up to approximately +12 V -

EmmL

Vpa 12V - Vpg (+22 V).

The negative voltage doubler operates in a similar manner and consists of two basic doubler circuits in
~cascade with an additional input negative voltage generating stage (D21/22 and C42/43).
Dual Voltage Regulator

The dual voltage regulator comprlses an LM325N (E38) tracking regulator and power boosters (Q4

and Q5). Output current-limit sensing is provided by R57 and R58. This stage regulates the cutputs
from the doubler circuits to provide the
15V of analog power required by the various analog circuits.
6.4.4.2

Digital-to-Analog Circuits - The analog sections of the AAV11-A consist of four 12-bit D/A

converters (each contained on- one 24-pin chip), four 2505 operational amplifiers, and a +10 V preci-

sion reference source.

Each D /A converter (DAC) contains the necesary circuits to generate a 0-2 mA output current and to
modify that current as a function of the 12 input data bits. A 1-LSB change in the data register
corresponds to a change of | part in 4096 of the full scale output, approximately 1/2 uA.
The output of the DAC is fed into a 2505 operational amplifier which converts the drive current into a

voltage output. The feedback from the output of the amplifier is passed through the selected feedback

resistors. The interconnections between these resistors, determined by the mode/range straps illustrated in Figure 4-2, determine the operating mode (unipolar or bipolar) and voltage range of the DAC
In question.

Gain and offset of each DAC are controlled through the externally-adjustable potentiometers (see
Figure 4-2).

6.4.5

AAVI11-A Diagnostic Test MAINDEC-11-DVAAA-A)

The AAVI1I1-A Diagnostic Test
is divided into four routines. Each is briefly described below.

Logic Tests (starting address 200) - exercises and monitors behavior of interface and con-

trol logic of all DACs on all AAV11-Asin a system. Checks that DAC holding registers can
be loaded, cleared, and modified without error.

Ramp Loop (starting address: 204) - reiteratively increments the holding register for each

DAC to produce full-scale ramp voltages successively at the output of each DAC. Permits

confirmation by oscilloscope of DAC linearity, settling time, and channel isolation.

Static Calibration Loop (starting address: 210)— permits operator to input control data to
all DACs and monitor resulting output conditions. Run with a precision DVM as output
monitor, the Static Calibration Loop permits calibration of gain and offset of each DAC.

Dynamic Calibration Loop (starting address: 214) - reiteratively switches each DAC
between maximum and minimum output conditions. Facilitates checking DAC response
and recovery characteristics as well as amplifier slew rates.

6.4.6 Maintenance
‘
In general, both routine maintenance and specific troubleshootmg efforts will follow the flow defined

in Figure 6-10. Since the diagnostic program has no way of evaluating AAV11-A analog performance,
pass or failure of all but the logic tests depends on the judgment of the operator. Refer to the AAV11A Manufacturing and Field Acceptance Procedure (A-SP-AAV11-A-3) for applicable criteria.
Preventive maintenance consists of removing airborne dust accumulations, checking that power supply levels remain within specifications whenever new devices are added to a system, and running
dlagnosmcs whenever performance confirmationis desired.

6-14

TESTS

b ASS

YES

RUN LOGIC

RUN

RAMP

LooP

PASS*

TROUBLESHOOT

AND REPAIR

LOGIC

YES

CHECK +5V

& +12V
POWER SUPPLY

+5V/+12V

YES

S OK
TMN\_P

READJUST

CHECK ANALOG

P.S. FOR +5V

POWER SUPPLY

OR +12V

RUN STATIC

CALIBRATION
LOOP

ANALOG

YES

P.S. 0.K.

PASS*®

'
BOARD

YES

SWAP

RUN DYNAMIC

IMPROPER

CALIBRATION

TM\

YES

LOOP

TROUBLESHOOT
AND REPAIR

CALIBRATE

ANALOG P.S.

*See AAV11-A Field Acceptance
Procedure for applicable criteria.

Figure 6-10

11-4486

AAVII-A Troubleshooting Procedure

6-15

6.4.7

Calibration

Prepare the system to permit access to signal line(s) and calibration potentiometers of DAC(s) to be

calibrated. Connect DVM of appropriate precision (note that 1 LSB on +£2.56 V bipolar or 0 -5.12 V
unipolar = 1.25 mV) to output of DAC to be measured. Float the DVM as illustrated in Figure 6-11.
Take care to connect DVM common lead to HQ ground associated with the DAC in question. Then
proceed as follows:

Load DAC holding register with 0000.

Adjust offset potentiometer (see Figure 4-2) for DVM rgading appr.opriatéto selected
mode/level condition (see Table 4-1).

Load DAC holding register with 7777.

Adjust gain potentiometer for DVM reading appropriate to selected mode/level condition
(see Table 4-1).
5.

Load DAC holding register with 4000.

Check DVM for reading appropriate to selected mode/level condition (see Table 4-1).

Step 6 should produce a reading accurate to 1-1/2 LSB.

I —\
|
\
1S5V

POWER

| "/

DVM

DACn AAVII-A

ouT

DAC RET

e
11 —4525

Figure 6-11

Floating the DVM

6.5 DRV11 PARALLEL LINE INTERFACE

Refer to the Microcomputer Handbook (EB-06583 76 09/53).

6-16

GLOSSARY OF A/D TERMS

Absolute Accuracy

The analog error, expressed as a percentage of full scale, referenced to the National Bureau of Standards voit.
Acquisition Time

The time duration between the giving of the sample command and the point when the output remains within a
specitied error band around the input value.
Aperture Delay Time

The time elapsed between the hold command and the point at which the sampling switch 1s completely open.
Aperture Uncertainty

The variation in aperture delay time for a particular sample-and-hold.

Common Mode Rejection (CMR)
The ability of a differential amplifier to reject noise common to both inputs. Common mode rejection is
expressed as a ratio, the Common Mode Rejection Ratio (CMRR). A differential amplifier with a CMRR of 80
dB (10,000:1) would have an output voltage of 0.5 mV if both inputs were 5 V (5 V/80 dB).
Crosstalk

The amount of signal coupled to the output as a percentage of input signal applied to all off channels.
Differential Inputs ( True)

Two external signals applied to the input circuitry of
an A/D system whereby the first is subtracted from the
second. The difference is applied to the A/D system. This is generally used with twisted pair wiring to reduce
noise pickup.

Example

(V+) - (V-)
i

[Vi + V(1) noise] - [V, + V(3,) noisc].

[V, - V,] + [V(y)noise - V(,) noise]

For twisted pair wiring:

V(, ) noise = V(,) noise
V=V, -V,
08-1236

TEIL

GLOSSARY-1

Differential Inputs ( Psuedo)

This method of inputting is similar to true differential inputting except that the negative input to the A/D system
is common to the other inputs.

Differential Linearity

The maximum deviation of an actual stated width from its theoretical value for any code over the full range of

the converter. A differential linearity of £1/2 LSB means that the width of each code over the range of the
converter is 1| LSB +1/2 LSB. Missing codes in an A/D converter occur when the output code skips a digit. This
happens when the differential linearity is worse than £1 LSB.
Drift

Drift is a function of the temperature coefficients of the components. It is the major contributor to gain and

offset error.
Gain Error

The error, expressed as a percentage, by which the actual full scale range differs from the theoretical full scale
range. This error i1s adjustable to zero.

Gain Temperature Coefficient

This is the amount of gain that changes with a chcmgein temperature. This may be expressed in ppm/°® C or
°
C/LSB at full scale. If an A/D has a gain temperature coefficient of 20° C/LSB at F.S., the A/D converted value
will be off by | LSB at full scale if the temperature rises 20° C above 25° C.
Input Bias Current

The amount of current that flows into the selected A/D channel from the source.
Input Impedance (dc)

The resistance seen at the input to an A/D system.
Linearity

Linearity is defined as the maximum deviation from a straight line drawn between the end points of the converter
transfer function. Linearity may be expressed as a percentage of full scale or as a fraction of an LSB.
Multiplexer

The multiplexeris a set of switches that permits analog data from different sources (chdnnels) to be supplied to
the sample-and-hold (or A/D converter) individually.
Multiplexer Settling Time

The maxnmum time required to reach a specified error band around the input value when switching chdnnels
Offset Error

The error by which the transfer function fails to pass through the origin. This is usually adjustable to zero.
Quantization Error

Quantization error is defined as the basic uncertainty associated with digitizing an analog signal, due to the finite
resolution of an A /D converter. An ideal converter has a maximum quantization error of £1/2 LSB.
Quasi-Differential
Like true differential operation (see Differential Inputs) in that measurement is made of the difference between
an input and a return line, Unlike true differential, however, in that measurement is not made at one instant in

time, but rather throughout the variation of the conversion.
Relative Accuracy

This is defined as the input to output error as a fraction of full scaie with gain and offset errors adjusted to zero.
Relative accuracy is dependent on linearity.
GLOSSARY-2

Resolution

The resolution of an A/D converter is defined as the smallest analog change that can be distinguished. Resolution is the analog value of the least significant bit.

Resolution =

Full scale

Least significant bit

For example, if a system requires a weight measurement range of 2540 1b, measured to the nearest 3 Ib,

Resolution = 233-9- = 847 code combinations
The closest standard A /D converter resolution available is 10-bits binary. A binary resolution of 10-bits selected.
The new resolution for this channel is recalculated for 10 bits.

1 LSB (least significant bit) =

Full scale range _ 2540

=2.51b

Sample-and-Hold

In order
to ensure that input voltage does not change during a conversion, a sample-and-hold is required. Ifthe
change during a conversion cycle is less than 1/2 LSB, then a sample-and-hold circuit is not required.
Example

Conversion Speed = 20 us

Full Scale Input Range (FSR), where w .., =27 (BW)

Converter Resolution = 10 bits
LSB Value = .01 V/bit
1/2 LSB = 0.005V

Maximum slew = 0.005 V /20 usec = 250 uV /usec =250 V /sec
(Rate required for no sample-and-hold)

fore;, =1/2 (FSR)sin w't

then de/dt = (1/2)w (FSR) cos wt
~lde/dt Imax =(1/2)co_,, (FSR) = (BW) (FSR), where Wax =27 (BW)

or 250 V/sec = 1 (BW) (FSR)

BW =250 V/sec /m(10.24 V) =7.77 Hz

Slew Rate

The capability of the output of an analog circuit to change its voltage in a given period of time. If the slew rate is
7 V /usec, the analog circuit output will change seven volts in one usec.

GLOSSARY-3

Successive Approximation

A method that is used to transform the analog signal to a digital number.

ANALOG INPUT ::D COMPARATOR

LOGIC

CONTROL

D/A

'CONVERTER.

A/D

A/D CONVERTED VALUE

VALUE
08-1238

An analog signal 1s compared to a logic generated signal. The logic always supplies a half range signal initially.
For example, the full scale input to an

Try*

A /D .converter system is 10 V and the input to the system is 7 V.

New Logic Voltage
o

Is the Input

A/D

Greater Than

Buffer

Decision

A/D

New Voltage

Bits

Value

Yes

Add +5 =45

1000000

25V

5+25V

Do nothing

1000000
1010000

125V

5+1.25V

Yes

Add 1.25=6.25

625V

6.25+.625V

Yes

Add .625 =6.875

1011000

3125V

6.875+ 3125V

Do nothing

1011000

15625V

6.875+.1562V

Do nothing

1011000

078125V

6.875 +.078125V

Yes

Add .078175

1011001

*This is a 7-bit A/D
1011001 = 7 Vin 10 V full scale range.

10
9

5 | YES
4

hEsRe] |

—

3 |—

‘

08-1239

GLOSSARY-4

Throughput Speed

The Nyquist sampling theorem states that a minimum of two samples per cycle are required to completely
recover continuous signals in a noiseless environment. In typical instrumentation systems noise does exist and

from 5-10 samples per cycle are required.

For applications with dc and very low frequency signals, sample rate is usually a sub-multiple of the powerline
frequency to provide essentially infinite rejection of these frequencies.

The minimum sampling speed required is the number of samples per cycle multiplied by the highest frequency
component of the data. For time multiplexed systems, the speed requirement of the A/D converter is dependent
on system throughput speed. System conversion speed is determined from data bandwidth, the number of channels. and the sampling factor by:

System throughput = (N) (n) (B.W.) samples/second
n = number of channels

where

N = number of samples/cycle (sampling factor)

B.W. = largest bandwidth of any channel
Example

Channel 1 bandwidth 100 Hz
Channel 2 bandwidth 200 Hz
Channel 3 bandwidth 250 Hz

throughput = 10 X 3 (250) = 7500 sample/second
N = 10

n =3

BW = 250 Hz

The A /D throughput is comprised of the following:
Multiplexer settling time

Sample & Hold settling time
A /D conversion speed
A /D recovery time

Computer acquisition time (Software)

GLOSSARY-5

Reader’s Comments
ADV11-A, KWV11-A, AAVI1-A,
DRV11 USER’S MANUAL
FK-ADV11-OP-002

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EK-ADV11-0P-CN1

ADV11l-A,

KWV11l-a,

AAV11-A,

Errata

Please
make
the
User's

DRV1l

Under

the
following
changes to
Manual
(document
no.

(See
pg

2-11

ILLUSTRATIONS,

Figure

2-8a

H3220

Figure

Paragraph

add

Figure

2-8a

below.)

2.4.3.1

should

2-8

provides
screw

shows

the

rear

easily

shows

used

for

the

accommodates

for

H322
to

user

H3220

two

single-connector

Figure

Panel

Distribution

the

ADV11-A

and

purpose.

ADV11-As

one

Panel

Berg

that

connector

and

concurrently

apparatus

Distribution

same

2-8:

read:

identifiable

terminals

2-8a

after

Distribution

connected

Manual

Sheet

EK-ADV11-0P-002).

Pg vi

User's

the

Panel,

Each

Figure

which

can

H322

ADV11-A

accessible

front.

and

H3220

one

other

device.
The ADV11-A is shipped with
a
decal set (appropriate for the
H3220 distribution panel)
that specifically identifies
ADV11-A inputs and outputs.

Note

that

with

the

appropriate

Add

H323-B

ADV11-A,.

Potentiometer

(See

potentiometer

Figure

2-8a,

Figure

2-8a

H3220

box

Box

may

Maintenance
circuit.)

Distribution

Panel

not

used

chapter

for

pg 3-6

Paragraph 3.4.1, second sentence should read:

These
H3220

pins may be
Distribution

convenient

external

connected to the optional H322 or
Panel* (see Paragraph 2.4.3.1) for
user

access.

The footnote at the bottom of the page should read:

*The KWV1l-A is shipped with decals that permit permanent
identification of signal 1lines associated with H3220
terminals.

4-4

Paragraph 4.4;1, second sentence should read:
These
H3320

pins may be connected to the optional H322 or
Distribution Panel* (see Paragraph 2.4.3.1) for

convenient external user

access.

The footnote at the bottom of the page should read:

#The AAV11-A is shipped with decals that permit permanent
identification of signal 1lines associated with H3220
terminals.

5-3

Paragraph 5.3.1, sixth and seventh sentence should read:

Connection to the DRV1l can be made through the H322 or

and 2-8a).
applied
when
This unit is provided with decals, which,
H3220
the
y
identif
to the H3220 Distribution Panel,
of
pins
ted
associa
screw terminals with respect to the

H3220

Distribution

Panel

(see

2-8

Figures

the DRV1l Berg connectors (A, B, UU, VV, etc.)

Ninth sentence should

read:

terminal
and DRV11/H3220
DRV11/H322
that
Note
rest on
sheet
decal
the
by
relationships assumed
on
labels
stamped
that
so
cable
BCO8R
the
of
connection

female

cable

ends

1labels

embossed

match

connectors aA/B to A/B, UU/VV to UU/VV.
pg 6-1

male

Paragraph 6.1, last sentence should read:

The customer is responsible for the wiring from his/her
equipment to the H322 and/or H3220 Distribution Panel or
to the end of the Digital-supplied cable.

pPg 5-2

Paragraph 6.2.1.7, first sentence should read:
Remove the 7012894 test connector and install the BCO8R
cable (ANDV11-A to H322 or H3220 Distribution Panel) or
the BCN4Z cable (ADV11-A to user devices) in the ADV11-A
Berg connector.

Pg 6-2

the

NOTE,

should

read:

simplify

the

first

sentence

the

second

paragraph

system

relationships,

the

H322

H3320

Distribution Panel compensates for this inversion on the
PC' board
that
distributes
Berg
connector
signals
to

front
pg

6-10

panel

Paragraph

screw

6.3.2,

Install
the
Distribution
devices)

6-11

Paragraph

unit
pg

6A-11

BCO8R
Panel)

Install

Berg

first

signals

this

Paragraph

should

read:

cable
(KWV11-A
to
H322
or
H3220
or
BC04Z
cable
(KWV1l-A
to
user
the

Distribution

sentence

connector

(J1)

and

the

terminus.

6.4.1.4,

If AAV11-A

H3220

second

between

appropriate
pg

terminals.

time.

6.4.2,

are

sentence

Panel,

(See

first

routed

connection

Paragraph
sentence

the

BCO8R

cable

Distribution

Panel)

devices)
between
the
appropriate terminus.

should

Berg

the

may

H322

the

made

the

6.4.2.)

should

(AAV11-A

BC04Z

read:

cable

read:

H322

(AAV11l-A

connector

(J1)

H3220

wuser

and

the

i BB

LRI

dlilgliltiall

pR——

digital equipment corporation