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EK-ADV11-OP-001

July 1976

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Document:	ADV11-A, KWV11-A, AAV11-A, DRV11 User's Manual
Order Number:	EK-ADV11-OP
Revision:	001
Pages:	88
Original Filename:

OCR Text

EK-ADV11-OP-001

digital equipment corporation - maynard, massachusetts

]

1st Edition, July 1976

2nd Printing (Rev) November 1976

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

RSTS

DIGITAL

TYPESET-8

DECsystem-10

DECSYSTEM-20

MASSBUS

PDP

TYPESET-11
UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION

1.1

GENERAL

. . . .

REFERENCES

. . . . . .

1-1
e e e

CHAPTER 2

ADVI11-A ANALOG-TO-DIGITAL CONVERTER

2.1

GENERAL DESCRIPTION

2.2

SPECIFICATIONS

2.2.1

Electrical

2.2.3

2.2.5

. . . . .. T

~TestSignals
-

. .

PowerRequirements

Channel Selection

A/D Conversion

2.3.3

Interface Functions
Control

. . .. ... ...

2.4.1

Analog Inputs

2-3

. . . . . .

. . . . . .. EENEE

Quasi-Differential Mode

~Twisted Pair Input Lines
Shielded Input Lines

2432

External and Clock Starts

2.5
2.5.1

2.5.2
2.5.3

2-6

S R

R A R e e e e e

... .. e

Mode Control

K L I

...... A

e e e e

e e e

2-6

2-6
2-7

2-9

. .. .. 2-11

S 0 U

£ N

=1 |

e T

e 6
e e e a e e e
2-11
. . . . . . .. ... .. . .. .. ... . 2-11

. . . . . .T

Vector and Address Selection

T Ry PE

T TSR

e e e e e

2-12

. . . . ... ... .. ... ... . ... 2-12

PROGRAMMING
. ... ... ... ....... 2
Control/Status Register (CSR) . . . . . . . . .. . . ... . ... .. . 2-14

- Data Buffer Register (DBR)
Programming Example

. . . . .. ... ... ... ...

. ... ...
. .. R

3.1

GENERAL DESCRIPTION
SPECIFICATIONS

. . . . . .. ... ..... i

‘Clock . .......... e
Input and Output Signals

3.2.2.1

Input Signals

Output Signals

e eT

e e

.. ... 2-16

S S

. . . . . .

3.2.2.2
0 3.2.23

. . . . . . . .. ... ... ... .. ..

KWV11-A PROGRAMMABLE REAL-TIME CLOCK

3.2.2

2-6

CHAPTER 3
3.2

2-6

. . . . ... ... ERPE VE

Distribution Panel

2.4.4

2-4

Allowing for Input Settlmg wn:h Hngh Sau:rce Impedance
Connections

2-4

s e e e e e e e

. . . . . .. . ... ... ... . ....
2-9
. . . . . . . . ... ... ..... 2 |

2.4.3.1

2433

T L s s e e e e e e e e

. . . . . .. ...

2422
243

. . . . . ..

242.1
2423

2-3

. . . . ...
. .. B

Avoiding Spurious Signals

2-2

. . . . . . oo oot

. . . ... .. PN

Single-Ended Mode

2-1

2-2

2-3

. . . . . .. . .. ... ...... T

USER INTERFACING

2.4.2

N R

. . . .. ... ... Y

24.1.2

FUNCTIONAL DESCRIPTION

2.3.1

24.1.1

2-1

s s 241

... ............ R

2.3.2

234

T D e e e e e e e e e

e e e e e s

Coding

224
2.2.6

. . . . .

1-1

s e e e e e e
. . .. ... ... ... ...... G
L
e e e e
Performance
. . . . . . . . . ...
Timing
. .. ... ..
... ... ....... e
e e e e e e e e e

2.2.2

2.3

C e e e e e e

e e

2-17

e e e e e e e .

e e e e e e e

. . . . . . ... ... ... ... ... ...
. . . . ... .. ...

. . . . . .. .. .. ... .. ...
Power Requirements (from LSI-11 Bus Power Supply)

3-1
3-1

3-1
3-1
3-2

...

3-3

. ...
. ..

3-3

CONTENTS (Cont)
Page

3.3

FUNCTIONAL DESCRIPTION
Bus Control

»*

3.3.2

Control/Status Register

3.3.3

Mode Control

lllllllllllllllllll

ttttt

vvvvv

»*

- )

flflflflflfl

..................

bbbbb

3.3.3.2

Mode 1 (Repeated Interval)

3.3.3.3

Mode 2 (External Event Timing)

3.3.3.4

Mode 3 (External Event Timing from Zero Base)

3.3.3.5

Flag Overrun

nnnnn

3.3.3.1

Mode 0 (Single Interval)

. . . . . ... .. ... ...

. . . . .

3.3.5

Buffer/Preset and Counter Registers

3.3.6

Schmitt Triggers

ttttt

lllll

CONNECTORS, SWITCHES, AND CONTROLS

lllll

40-Pin Connector

3.4.2

FAST ON Connectors (Clock Overflow and ST1 OQutputs)

343

Selector Switches (Address, Vector and Slope/Refemnce Level)

UUUUUUUUUUUUUUUUUUUUUU

. . .

3.4.3.1

Address Selection

3.4.3.2

Vector Selection

3.4.3.3

Slope and Reference Level Selector Switches and Controls
PROGRAMMING

. . . . . . .

CSR Bit Assignments

. . . . . . . . . .. ... ... ...,

3.5.3

Normal Control Sequences

. . . . . . ... . .

.. ....

. . . . . . . .. . . .. .. ....

3.5.3.1

Mode O (Single Interval)

3.5.3.2

Mode 1 (Repeated Interval)

3.5.3.3

Mode 2 (External Event Timing)

3.5.3.4

Mode 3 (External Event Tlmmg from Zero Base)

3.5.4

Programming Example

bbbbbbbbbbbbbbbbb

. . . . . . .. e

CHAPTER 4

AAV11-A DIGITAL TO-ANALOG CONVERTER

4.1

GENERAL DESCRIPTION

4.2

SPECIFICATIONS

4.3

FUNCTIONAL DESCRIPTION

»*

wwwww

‘‘‘‘‘

flflflflfl

mmmmm

iiiii

wwwww

ttttt

mmmmm

wwwww

lllll

vvvvv

4.3.3

DACsO,1,and2

434

DAC 3

»*

... ... .. e
-

lllll

e e e e s
»

CONNECTORS, SWITCHES, AND CONTROLS

UUUUU

iiiii

44.2

Address Switches . . . . . .. . . .. L.

443

Mode/Level Selector

Jumpers

wwwwwwwwwwwwwwwww

INTERFACING TO OUTPUT DEVICES
Ground Connections

4.5.2

Twisting

nnnnn

wwwwwwwwwwwwwwwwwwwwwww

40-Pin Connector

4.5.1

QQQQQ

nnnnnnnnn

44.1

4.5

vvvvv

hhhhh

Control Logic

4.4

uuuuu

llllllllllllllllllllllllll

4.3.2

»*

. . . . . . v v i i e e e e e e e e e e

llllllllllllllllllllllllllll

3-4
3-4

- 3-5
3-5

3-5

3-5
3-6
3-6
3-6

lllllllllllllllllll

Bus Control

. . . . .

lllllllllllllllllllllll

4.3.1

e e e e

vvvvvvvvvvvvv

UUUUU

iiiii

flflflflflflflflflflflflflflflflflflflflflflflflflflflfl

- Buffer/Preset Register (BPR)

3-3

mmmmm

lllll

wwwwwwwwwwwwwwwwwwwww

3.5.2

3-3

nnnnn

3.4.1

3.5.1

lllll

nnnnn

Oscillator, Divider, Rate Control Chain

3.5

DDDDD

wwwww

3.3.4

3.4

»»»»»

""""

wwwww

*****

3-7
3-8

3-8

3-8
3-9

3-9
3-9
3-13

3-13

3-17
3-17

CONTENTS (Cont)
Page
4.5.3

454

Shielding

. . . . . e e e

Drive Capability

PROGRAMMING . . . . . .

CHAPTER 5

DRV11 PARALLEL LINE UNIT

5.1

GENERAL DESCRIPTION

5.2.1

Locations

e
e

e e

Addressing

Vectors

e e e e

4-7

e e e

4-7

s e e

4-7

it i i et
e it

5-1

e e

s e
|

. . . .. . . . @ i

. . . ... ... ... - 5-1

e 5-1

. . . . . . . ... . ... ... e e e e e e e e e e e e

. . . . . . . ...K

INTERFACING TO THE USER’S DEVICE
General

e e e

. . . ... e

5.2.3

5.3.1

JUMPER-SELECTED ADDRESSING AND VECTORS

5.2.2
5.3

e e

. . . . .. .. .. EP

4.6

5.2

e e e e e e e

... .............

. . . . ... .. ....... e

e e e e e e e e e e e e

5-3

5-5

5.3.2

Output Data Interface

. . . . . .T

5.3.3

Input Data Interface

. . .. .. .. .. et

5.3.4

Request Flags

5.3.5

Initialization

5.3.6

NEW DATA READY and DATA TRANSMITTED Pulse
Width Modification
. . . . .. ... ... .. ... ... .. .....

b h e e e e e e e e e

. . . . . . . . . . . . e 55
. . . . . . . . . . .

...

5.4.2

5-6
5-7

5.4.3

Word Formats

5-7

5.4.4

I/OTiming

CHAPTER 6

. . . . . . .

. .

e e e e e e e e

. .. ......... e e miee
e e o re e e e e e e

5-7

ADV11-A, KWV11-A, AAV11-A, and DRV11 MAINTENANCE

6.1

MAINTENANCE PHILOSOPHY

6.2

ADVI11-A ANALOG-TO-DIGITAL CONVERTER

6.2.1

5-6

AAAIesSing . . . . . s
e e
e e e e
e
e
Interrupt Vectors . . . . . e e P
.

e e n e m

5-6

5.4.1

... ....... e e e e M e

e e

5.4

PROGRAMMING

5-2

e .. 52

Installation

. . . . . . . . . . . . . . .

... ....

6-1

. . . . .. .. ... ...

6-1

. . . . . . . . . . ... ..

6-1

6.2.1.1

Location

6.2.1.2

Address and Vector Selection

6-1

6.2.1.3

Board Insertion . . . . . . .. .. ETTRUNE P T e e e e e e e e

6-1

6.2.14

Test Connector

6.2.1.5

Shields -~

6.2.1.6

Acceptance

6.2.1.7

Final Connections

6.2.2

. . . . . . . . .

e e e

. . . .. . ... i

. . . . .. ... .. .... A

. . . . ... .... e

e e e e e e

ADVI11-A Circuitry

ADV11-A A/D Conversion Circuit
The Vermnier DAC

6-2
6-2

. . . . .. ... ........

. . . . . . . . . . . .

i i i i it i e

6.2.3

ADV11-A Performance Test (MAINDECWI 1~DVADA~A)
Maintenance

6.3.1

6.3.1.1

e e e e e e e - 6-2

PSR T

6.2.4

Calibration

6-1
6-1

. . . . . . ...
.. T

6.2.2.2
6.2.2.3

6.2.5

6-2

. . . . . . ...
. e

ADV11-A Analog Power Supply

. . .. . . .. T A
. . . . . .S

e e e eS

6-1

e e e e e e e

. . . ..
.. PP
T DRt b o

6.2.2.1

6.3

e e e e e
e e e e e

6-4

6-8

........

6-8

ol e e i e e e e e e e 6-10
Te

e e e e e e e 6-10

KWV11-A REALTIMECLOCK . .. .. ... ........ e
e e e 6-10
Installation . . . . . . ... . .. .. .. ... ... e
e 4 e e e e e 6-10
Location

. . . . . . . . . . .

e e e e

e e e e 6-10

CONTENTS (Cont)
Page

6.3.1.2

Address and Vector Selection

6.3.1.3

Board Insertion

6.3.1.4

Test Connections

6.3.1.5

Acceptance

6.3.2

. . . . . .e
e
e s e e
e e e W 6-10
. . . . . . . . . . ... 6-10
. . . . . ... ... e

W e i e e e e e e e 6-10
e e, 6-10

. . . . . ... L

Final Connections

. . . .. e

e eR

6.3.3

KWV1I1-A Circuitry

6.34

KWV11-A Diagnostic (MAINDEC-11-DVKWA-A-D)

6.3.5

Maintenance

6.4

6.4.1

. . . . . . . . .

. . . . . . . . . .

e T 6-10

6-11

. .. .. ...
... 6-11
e

AAV11-A DIGITAL-TO-ANALOG CONVERTER
Installation

e e

e, 6-11

.............. 6-11

. . . . . . . . . . ... 6-11

6.4.1.1

Location

6.4.1.2

Address Selection.

. . . . . . . . . .. e 6-11

. . . . . . .. ... Lo Lo 6-11

6.4.1.3

Board Insertion

6.4.1.4

Test Connectors

. . . . . . . . . .. 6-11

Acceptance Test

. . . . . . . . . . ...

6.4.1.5

6.4.2

6.4.3
6.4.4

Final Connections

. .

. . . . .. .. ..o L 6-11

. . . . .. .. e

Mode/Level Selection

- AAV11-A Circuitry

. . . . . . . . . ... 6-12

. . . . . . . . ... S 6-12

6.4.4.1

AAV11-A Analog Power Supply

6.4.4.2

Digital-to-Analog Circuits

. . . .. . .. ... ... .... 6-12

. . . . . . . . . . . ... ... .... . 6-14

6.4.5

AAV11-A Diagnostic Test (MAINDEC-11-DVAAA-A)

6.4.6

Maintenance

6.4.7

Calibration

6.5

. 6-11

e e e e e P 6-11

. . . . . . . . ..

. . ...
.. .. 6-14

e e e

e 6-14

. . . . . . . . . .., 6-16

DRVI11 PARALLEL LINE INTERFACE

. . . .. .

... ... ...... 6-16

ILLUSTRATIONS
Figure No.

Title

Page

ADV11-A Functional Block Diagram

. . . . .. . .

.. ... .. .....

2-5/

2-2

Single-Ended Input Referenced to User’sGround

. . . . . . . ... .. ...

2-7

2-3

Floating ADV11-AInput Signals . . . . . . . ... ... ...... e

2-8

2-4

Single-Ended Versus True Differential Input Modes

2-9

2-5

ADV11-A Quasi-Differential Mode

. . . . . . . .. ... .. ... ... .. 2-10

- 2-6

ADV11-A Connectors and Switches

. . . . . . . .. .. ... ... ..... 2-12

2-7

ADV11-A 40-Pin Connector Pin Assxgnments

2-8

H322 Distribution Panel

2-9

Module Jumpers

ADV11-A Address and Vector Switches

341
3-2

................. 2-13

. . . . . . . . . . . . .. .. ... ... 2-13

2-10

2-11
2-12

. . . . . . ... ... ..

. . . .. .. ... ... L e e

e e e e e e e e

e .. 2-14

(Rocker or Slide Switches)
. ..
. . .. S
ADV11-A Control/Status Register (CSR)
. . . . . . . ..

2-15
... ... .... 2-16

ADV11-A Data Buffer Register (DBR)
. . . .. P
L
2-16
KWV11-A Connectors, Switches,and Controls
. . . .. ... ...
.. ...
3-2
KWV11-A Real-Time Clock Block Diagram
. . . .. ... .. ... .....
34

ILLUSTRATIONS (Cont)
“Title

- Figure No.

Page

3-3

Connecting External Usethupphw Smpe and Lavel Contmls

40-Pin Connector Pin Assignments

3-5

KWV11-A CSR Address Switches (Set for 17“2‘)

. . . . . .. ...e

.........
e

e e

3-6

3-7
3-7

3-6

KWV11-A Vector Address Switches (Set for000440) . . . . ... ... ... - 3-8

3-7

KWV11-A Slope/Reference Level Selector Switches and Controls

3-8

. . . . . .

3-9

4-2

KWVI11-A Slope Selection . . . . . . . . .. ... o0 3-10
CSR Bit Assignments
. . . . . . . . . . ...
oo e 3-13
AAV11-A Block Diagram
. . . . . . . . .. .. ... L. 4-3
AAV11-A Connectors, Switches, and Controls
. . . . . . . . . . ... ... 4-4

4-3

40-Pin Connector Pin Assignments

4-4

AAV11-A Address Decoding

L. Lo

4-6

4-5

4-6

AAV11-A Address Switches (Set for17044n) . . . . . . . . .. . ... ...
Connection to Oscilloscope with Differential Input . . . . . . . . . .. ...

5-1

DRVI11 Parallel Line Unit

. . . . . ... .. .. ...............

5-1

5-2

DRVI11 Jumper Locations

. . . . . . . . . . . ...

5-3

DRV11 Device Address

. . . . . . . o o i i i

5-4

DRVI11 Vector Address

. . . . . . . .« o i i i i e e e

5-5

J1 or J2 Connector Pin Locations

5-6

DRVI11 Word Formats

39
4-1

. . . . . . . .. e

. . . . . . . . . . . .

e e e e e e e e e

i i

4-7

Lo e

5-2

e e e e e e e e e e e e

5-3

e e e e

. . . . . . . . . . . ... ... ... ...

. . . . . . . . .«

4-5

e e e e e e

e e e e

5-4
5-7

. . . . . . . . . .. .. ... .. ..... 5-10
Battery-Operated Potentiometer Box for ADV11-A A/D Converter . . . . .. 6-3
6-3
Analog Power Supply Block Diagram
. . . . . .. .. ... ... ......
6-4
DC-DC Converter Signals
. . . . . . . .. .. ... ... e
e e e e e
DRV11 Interface Signal Sequence

6-1
6-2
6-3

oo oo,

6-4

ADV11-A A/D Conversion Circuit Block Diagram

. . . . .. ... ... ..

6-5

e e e e e e e e e e e

6-5

Basic Positive Voltage Doubler

. . . . . . . . . . ..

6-6

A/DDuring Sample

6-7

A/D During Conversion

. . . . . . ..

6-8

2 Node During Conversion

6-9
6-10
6-11

ADV11-A Troubleshooting Procedure

. . . . . . . e

AAV11-A Troubleshooting Procedure
Floatingthe DVM

e e

6-6

e e e

6-7

. . . . . . . . . .. e e e e e e e e e e e e
e e e e e e e e e e

6-9
. . . . . . . . . . .. ... ... ... 6-15
. . . . . . . . . . . ... ... ....

. . . . . . . . . . .«

e i e

e e e

e e e 6-16

TABLES
Title

Table No.

Page

4-1
5-1

KWV11-A CSR Bit Definitions
. . . . . . .. ... ... ... .......
CSR Bit Settings for Mode O, Single Interval
. . . . . . . ... .. .. ...
CSR Bit Settings for Mode 1, Repeated Interval . . . . . . .. .. .. ....
CSR Bit Settings for Mode 2, External Event Timing
. . . . . . . . ... ..
AAV11-A Digital-to-Analog Conversions
. . . . . . . . . . ... ... ...
DRV11 Input and Output SignalPins . . . . . . . ...
. e
e e e e

5-2

Word Formats

3-1

3-2
3-3
3-4

. . . . . . . . . . . . . . . ee

e e e e e e

3-11

3-14
3-15
3-16
4-8

5-8

- TABLES (Cont)
Table No.

Title

6-1

ADV11-A Voltage/Current/Bit Relationships

6-2

Jumper Configurations for Bipolar Operation

6-3

Jumper Configurations for Unipolar Operation

. . . . ... ... ... ... .
. . . . . ... ...

Page
6-8

... ... 6-12

. . . . ..
... ... ... 6-13
AAV11-A Input Code/Output Voltage Relationships
. . . . .. . ... ... 6-13

viii

CHAPTER 1
INTRODUCTION

1.1

GENERAL

This manual contains information necessary for the operation, installation, and maintenance of the
family of real-time analog and digital I/O devices which DEC provides as options for the LSI-11
Processor, i.e., the ADV11-A Analog-to-Digital Converter, the KWV11-A Real-Time Clock, the
AAVI11-A Digital-to-Analog Converter, and the DRV11 Parallel Line Interface. Operating information for each device is provided in a chapter specific to that device which includes functional descrip-

tion, specifications, theory of operation, and programming background. Installation and maintenance
information is provided for all units in Chapter 6.

All members of the LSI-11 real-time 1/O family are designed to interface between the processor and
analog or digital signals in the world external to the processor. All devices are configured on one quad
or double-height board designed to mount in an LSI-11 backplane or expander box and to receive
power from LSI-11 supplies. All communicate with the LSI-11 bus and receive interrupt priority as a
function of their location in the backplane. Finally, all have facilities to permit users to assign device
addresses, and where appropriate, interrupt vector locations.

A number of recommendations are made in this text regarding specific interfacing configurations and
general good practice. However, no specific interfacing claims are made over and above those
expressed in the general specifications for each module. The responsibility for connecting DEC modules to external equipment rests ultimately with the user.
1.2

o
o

REFERENCES

Microcomputer Handbook ( EB-06583 76 09/53)
[ SI-11 Bus Specification

' CHAPTER 2

2.1 GENERAL DESCRIPTION
The ADVI1I1-A is a 12-bit successive-approximation analog-to-digital converter with built-in multiplexer and sample-and-hold for use on the LSI-11 bus. The multiplexer section accommodates 16
single-ended or 8 quasi-differential inputs, and the converter section utilizes a patented auto-zeroing

design that measures the sampled signal with respect to the offset ofits own internal cmrcuxtry and thus
effectively cancels out its own offset error. cantrnbutwns to the measurement.
A/D conversions are initiated either by program command, clock overflow, or external events as
determined by program control ofthe ADV11-A’s Control/Status Regnster (CSR). The clock overflow
command is supplied by the KWV11-A clock option. External event inputs may originate directly

from user equipment or from the Schmitt trigger output on the KWV11-A clock. Digital A/D con-

version datais routed through a buffer register to the LSI-11 for programmed transfer into memory.
This buffering optimizes the throughput rate of the converter by allowing data from one conversion to
be transferred to the processor after a subsequent conversion begins.
A vernier offset digital-to-analog converter is includedin the ADV11-A’s analog circuitry to facilitate
very accurate program-controlled trimming of the A/D’s offset. Three test signals- two dc levels and

one bipolar triangular waveform
- are available for use on any channel input. The triangular wave can
be usedin conjunction with diagnostic softwaw and the vernier DAC to produce extremely thorough
and precise analog testing.
2.2

;

SPECIFICATIONS

2.2.1

Electrical (@Ta = +10° C to +60° C)

Inputs

Analog Input Pratectidn |

Logic Input Protection

Analog Input

_ Full Scale Range (FSR)

" Fusible resistor guaranteed to open at £85 V within 6.25 sec-

onds. Guaranteed not to open from -20 V to +15 V at the
input. Overload affects no components other than the fusible
resistor on the overloaded channel; no other channels are
affected.

Fusible ri:r:sii.@:;t;(:‘a»t"i “g:uaranwcd toopenat £ 25V within 6.25 sec-

~onds. Guaranteed not to open from -3 V to +8 V at the input.

10.24 V bipolar (-5;12 Vito +5.12 V)

Inputs (Cont)
Analog Input
Dynamic Resistance
(/Vin/ < 5.12 V)
Analog Input Bias Current
-

100 MQ, minimum

50 nA, maximum

(/Vin/ £ 5.12 V)

Logic Input Voltages

2.2 2

Low = 0.0to +0.7 V; high = +2 Vto +5 V

Logic Input Currents

Low = -6.8 mA at 0 V in.; high = +1.3 mA at +5 V in

Logic Input Rise/Fall Time

400 ns, maximum

Codmg

A/D mem'ter |
Resolutmn

12 bits, binary weighted

‘Format

Parallel offsat‘ binary, right justified
~

Output Code

Input Voltage

+FS-1 LSB

(FS=5.12V;1LSB = 2.5mV)
‘Vermer D / A

Resolutmn

8 bits, binary weighted

Format

Offset binary encoded
Input Code
377
200

0
223

Approximate Offset Voltage
+2.5A/D LSB (+6.4 mV)
o

-25A/DLSB(-6.4 mV)

Performance ~

Gain Error

Adjustable to zero

Offset Error

Adjustable to zero

- Differential Linearity

No skipped states; no states wider than 2 LSB. 99% of statewidths + 1/2 LSB |

Integral Linearity

+1 LSB, maximum non-linearity (referenced to end paintS)

Performance ( Cont)
Temperature Coefficients

Gain = 6 ppm per degree C
Linearity = 2 ppm of full-scale range per degree C
Offset =7.5 ppm of full scalerange / degree C

Noise

Module = 1/3 LSB rms; 1 LSB peak
System = 1/2 LSB rms; 1.5 LSB peak -

Warm-Up Time

5 minutes, maximum

2.2.4

Timing

External Start

Low level pulse, 50 ns minimum to 10 us maximum; conversion

starts on leading edge

Synchronization

OtoT

Conversion Time

16T
(T = clock period = 2 us)

Transition Interval
(reacquisition interval
‘between end of conversion
or channel change and start
of new 'conwmi@na) "
|

9 us

2.2.5

Test Signals

The ADVl 1-Aprowdes three output. Wltagea fm' test purpams
1.

Positive dc level, +4.4 V (£15%)

Negative dc level, -4.4 V (£15%)

Triangular wave, 15 Hz nammal(:kl.‘i%)

2.26 Pawer Reqmmmnm
+5 Vdc £5% @2.0 A, maximum

~
14

+12 Vdc +3% ‘450 mA, maxnmum Sl
2.3

FUNCTIONAL DESCRIP’I‘IUN

The ADVI 1-A perfmms itsfunctmmin swcn sucwsswe steps
I.

It enables the spmfiad «chamml

2.
~

It samples 1 of 16 single-ended(ar 1 of8 mffuremml)analogmpm channels spmficd by the
control pmgmmhmg enwhm awqmm a wlmblw mmmal wfwmnca equivalent.

It accepts a command to perform an A/D conversion.

It holds the sampled reference equivalent during 12 successive interrogation intervals.

When the least significant bit has been resolved in the Successive Approximation Register
(SAR), the ADV11-A transfers the contents of the now-filled SAR to the Data Buffer Register (DBR) where it can be accessed by the processor.
|

It informs the processor that conversion data is available.

It reacquires and tracks the programmed channel.

These steps are impleme\nted in the ADV1 l;A by componcnts that can be grouped together in four
functional categories:

;

Channel selection

A/D conversion

Processor/ADVI11-A interface

Control logic that coordinates the above steps with respect to one another and to the needs
of the processor.

These categories are discussed below.
2.3.1
Channel Selection
et
Channel selection is accomplished under program control by two 8-channel multiplexers
and is a
function of the data asserted in bits 8 through 11 of the Control/Status Register (CSR). Each of the 16
analog input channels is routed to the single output channel through a MOS field-effect transistor
which acts as a normally-open switch. During the sample interval, the data pattern in CSR bits 8
through 11 selects one of these transistors and causes it to change from a condition of nearly infinite
resistance (1 G2 or more) to one of very low resistance (1000 Q or less). Since in the selected state the
transistor conducts current within the +£5.12 V limits equally well in both directions, it now functions
as a closed switch, effectively routing to the output line whatever analog signal is connected to its
input.

2.3.2 A/D Conversion
|
A/D conversions can be initiated in three ways: under program control, on overflow from the
KWVI11-A Real-Time Clock, or on external input. When a conversion is completed or the control
program writes a multiplexer address into the CSR, the control logic initiates the Transition Interval a delay of about 9 us to allow the multiplexer adequate selection and settling time and to permit a valid
representation of the signal level to be established in the sample circuit. If no A /D Start signal has
occurred by the time the Transition Interval has elapsed, the sample circuit merely follows the signal
transmitted to it through the selected multiplexer channel and waits for an A /D Start signal. When an
A/D Start signal occurs - or at the end of the Transition Interval if A/D Start was previously generated by the writing of the CSR GO bit - the sample and hold circuits
are switched to hold, sustaining
the sampled level for the next step. The multiplexer output is then set to its hold condition, i.e., to
ground if the single-ended (S.E.) input is set low for single-ended measurement, to the second differental input (return line) if the S.E. input is not set low. Note that if an external
or clock start signal occurs

during the Transition Interyal, conversion starts immediately without waiting for the Transition Inter-

val to be completed. Bit 15 of the CSR (AD ERROR) is set, however,
and an interrupis
t generated if
bit 14 (error interrupt enable) is set
- alerting the program that conversions are occurring too fast and
are consequently liable to be in error. ..

2-4

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Under normal conditions, it is not until the Transition Interval is complete that the measurement
process is begun. The Successive Approximation Register (SAR) is cycled through 13 states by the
clock. In thefirst state its output code involves only the most significant bit (MSB) of the 12-bit SAR
word. This output code causes the feedback digital-to-analog converter (DAC) to generate an output
equivalent to that produced by the hold circuits in response to a sample voltage of 0. The DAC output
is summed with that produced by the hold circuits and with that coming from the grounded multiplexer output (single-ended mode) or from the second differential input (quasi-differential mode). If
the current from the summing node is negative, the first approximation was too low, and the com-

—"y,

parator signals the SAR to maintain the state of bit 11 and repeat the process with bit 10. If the current

from the summing node is positive, the first approximation was too high and the SAR changes the
state of bit 11 before cycling into the second approximation. This process continues until all 12 bits in
the word have been set, tested, and if necessary, changed. The 13th state (end of conversion, or EOC)
indicates that the measurement is complete and that the SAR now contains an offset binary equivalent
of the sampled voltage and may therefore be transfered to the processor. EOC causes the sample and
hold circuits to return to the sample mode and to reset the SAR, preventing further SAR activity until
the occurrence of the next hold condition.
|
|
:

Note that because the reference point against which the sample voltage is compared
is at the output of
the multiplexer itself rather than internal to the sample and hold circuits, all offset voltages generated

by the intervening circuits are common to both sample and hold conditions and are therefore cancelled

out of any measurement. In single-ended mode, grounding the multiplexer output (and thereby establishing this reference point) is identified as auto-zeroing the converter.

2.3.3
Interface Functions
|
|
|
In addition to stopping the SAR clock and reestablishing the sample mode, the end-of-conversion
signal also initiates the process that causes the SAR data to be transferred to the processor. Since this
operation takes a finite amount of time which would interfere with subsequent measuring operations,
the SAR data is first transferred to a holding device, the Data Buffer Register (DBR), where it will
remain until the processor can be notified to read the conversion data for processing. In the meantime,

the channel selection and A/D conversion circuits
can begin the next measurement as dictated by

Control/Status Register (CSR) bit conditions controlled by the processor.

‘

Included in the ADV11-A interface
is an extension of the DBR designed to accept 8-bit write information from the BUS DATA /ADDRESS lines. This buffer permits programmed setting of the Vernier
DAC (see Paragraph 6.2.2.3). Also included are transceivers that connect the bi-directional BUS
DATA lines to the LSI-11 Bus DATA/ADDRESS lines. Associated with these transceivers are switches that permit assigning device and vector addresses to any given ADV11-A.
2.3.4 Control
.
|
o
o
As the above discussion suggests, a large number of signals must be precisely orchestrated each time

the ADV11-A executes a conversion. The control logic contains an assortment of gates, latches, readonly memories, and timing circuits designed to assure that multiplexer channels are properly selected,
sample durations are of adequate length, conversions are not initiated during uncompleted previous
conversions, etc. In general, this logic precludes the need for the user to attend to any but the mostelementary details of the conversion process, e.g., making necessary connections to the system and
writing control programs that make appropriate use of the CSR.

2.4 USER INTERFACING

2.4.1 Anal ’ g ~§Inputs :
2.4.1.1 Single-Ended Mode* - Single;mdcgi analog input signals for the ADVV11-A may be of two

types, grounded and floating. A grounded input is one whose level is referenced to the ground of the
instrument that is producing it, as illustrated in Figure 2-2. Since the instrument may be located at a

*The ADV11-A is factory-set for differential mode. Single-ended mode must be selected as described in Paragraph 2.4.3.3.
2-6

t ground and
distance from the computer, there may be some voltage difference between the instrumen
ground
undesired
the
of
sum
the
be
will
A
ADV11the computer ground. The voltage seen by the
s are
difference
such
where
cases
In
voltage.
difference voltage and the desired instrument signal
to
possible
as
close
as
outlet
ac
an
into
t
encountered, they can be minimized by plugging the instrumen
analog
ADV11-A
the
to
ground
user’s
from
wire
a
that providing power to the computer. Do not run
ground. Such a wire can cause ground loop currents which affect results not only on the input channel
in question, but also on other channels.

- ADV11-A

'l y

AAA—

A——

VOLTAG |
's SOURCE VOLTAGE
ER'S
mse:n

SIGNAL

|
|
l

)

Wpl? TN

|
|
|

)

—0

MUX

ADVit-A
GROUND

|
l

—
-

USER'S

e —— ] = e

GROUND

i~
-

COMPUTER
GROUND

1~ 4166

Figure 2-2 Single-Ended Input Referenced to User’s Ground

A floating input is one whose signal voltage is developed with respect to a point not connected to
ground, as illustrated in Figure 2-3. The identifying characteristic of a floating source is that connecting the signal return to the ADV11-A ground does not result in a current path between the
|

ADV11-A ground and the instrument ground.

Note that the return of a floating input must be connected to one of the ADV11-A’s analog ground
terminals (see Figure 2-3). Ground points may be shared among channels, as illustrated by the batterypowered sources in Figure 2-3.

explained in
2.4.1.2 Quasi-Differential Mode - The “quasi” prefix in “quasi-differential” can best be involves
two
input
l
differentia
true
A
operation.
l
differentia
true
the context of a preliminary review of
function
a
is
device
the
of
output
the
that
way
a
such
in
amplifier
l
signal lines connected to a differentia
of the instantaneous difference between the voltages on the two signal lines. One advantage of such a
t

‘configuration is illustrated in Figure 2-4.

Figure 2-4(a) assumes a single-ended generating device that produces a signal, Vs, with respect to its
ground and is situated sufficiently far from the rec iving device for a significant noise voltage, Vp, to be
‘developed in the power distribution ground lines. The result is that, at any given instant, the differential amplifier in the receiving device sees both the signal voltage and the noise voltage. Its output, Vo, is
a function of Vg + V; and is in error with respect to Vs alone.
2-7

| FLOATING SOURCE

SIGNAL -.
RETURN
X

BATTERY POWERED

SOURGE

{c%n 00
CHAN O1

I CHAN 02
J CHAN 03
' CHAN 04
‘ CHAN 05

LOwW

MU X

| cHaN 06

i
—

FY.Y

I CHAN O7
2

RETURN
SIGNAL

'CHAN%O

'CHAN 1|

1 -

| cHan 12

| cHa1n3
|

| cHAN
14

INSTRUMENT WITH

ISOLATION TRANS- |
FORMER AND

g CHAN
16

| cHan
17

s |sieNaL
.
»

‘\/

Pil

RETURN
,*,
HQ GROUND

R
o o

lCHANTfi

FLOATING SECONDARY|

HIGH
MuUX

——-L

)

ANALOG

GROUND

COMPUTER =
GROUND
-

11SVAC

it-4167

Figure 2-3

Floating ADV11-A Input Signals

Figure 2-4(b) illustrates the same device connected in true differential mode.
The same noise voltage

exists in the power distribution ground system, but this time the generatin
g device ground is connected
directly to the negative input of the receiving differential amplifier. Since
the instantaneous noise
voltage is common to both the + and the - inputs, it is cancelled out of the
final amplifier output. V,
now provides a valid representation of V; alone.
i
et
Sl

Figure 2-5 illustrates the ADV11-A operating in the quasi-differential mode.
The major contrast between true differential operation as described above and the operation
of the
ADVI11-A in differential mode is that in the latter, the two sides of the signal
are not simultaneously
input to a differential amplifier. Rather, their difference is established by a sequential
operation that
first samples the voltage at one of the two inputs and then, holding this value fixed, in effect
subtracts
from it the voltage at the second input. For near dc conditions, this procedure produces
a result like
that of true differential operation - that is, the output is a function of the difference between
the two
input voltages, and common mode voltages are cancelled out. But, since there is a significant
time
lapse between taking the sample and completing the final approximation, a
‘possibility for error is
introduced by the ADV11-A that increases as a function of common mode signal frequency.
The result

2-8

is that the common mode rejection ratio, while essentially infinite at dc, rolls off for ac signals, and is
about 40 dB at 60 Hz line frequency. In addition, since the holding action of the sample-and-hold
circuit is only in effect on the first (non-inverting, signal) input but not on the second (inverting,
return) input, the voltage rate of change on the second input should be kept below 25 mV /ms. This is
the slope that results in a quarter-LSB change during the conversion interval. Such a rate of change
corresponds to 125 mV peak-to-peak at 60 Hz line frequency. This dynamic response difference
between the two inputs requires us to distinguish the ADV11-A’s differential mode from true differential operation. Hence the term ‘“‘quasi-differential.”

GE?«JERATWG

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Ll

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a. SINGLE-ENDED MODE
GENERATING

DEVICE

(VO=Vi+V,)

1
l

l
|
I

—

b. TRUE DIFFERENTIAL MODE (Vs = V4 + Vq- Vp)
11~ 4168

Figuré 2-4 Single-Ended Versus True Differential Input Modes
2.4.2

Avoiding Spurious Signals

As a preliminary step, confirm that the computer power supply ground is connected to power line
(earth) ground. If continuity checks reveal no such connection, attach a length of 12-gauge wire
between the power supply ground and a convenient point associated with earth ground.

2.4.2.1 Twisted Pair Input Lines - The effects of magnetic coupling on the input signals may be
reduced for floating single-ended or differential inputs by twisting the signal and return lines in the
input cable. If the inductive pickup voltages of the two leads match, the net effect seen at the ADV11-A
input is zero. Use of twisted pairs has no effect with a single-ended non-floating signal (referenced to
ground at the instrument end).

f—mlvSl‘”"—N—J—wys———3 F19NvS8010N
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2.4.2.2 Shielded lnwut Linm The effects ofelectrostatic coupling on the input signals may be reduced by st ielding
t
|wires. Thisis especially important if tk e instrument or transducer has high
source ammaum Tw pwwm the shield from carrying current and thus developing ground loop
voltages within the ADVI 1-A, connect it to gruund at the instrument end only.

2.4.2.3 Allowing for Ii,iutSettling with Hig
npedance - Allsolid-state multiplexers inject a
small amount of chargeinto their input lm s t 'Whenchangmg ahanmls, causing a transient error voltage

thatis discharged by the input signal’s source impedance. The ADV11-A shares this characteristic, and
alsoinjects a small charge into the selected input line at the end of each conversion when the auto-zero
swnwhis turned off (see Paragraph 2.3.2). After any channel change and after any conversion, the
ADV11-A’s control logic allows a 9 us interval (identified as the Transition Interval) during which
conversions cannot start without generating error conditions. Normally, thisis sufficient time for the
input transient to settle out. However, more time may be needed when the multiplexeris switching into
an mpm channel with hxgh source impedance, particularly when large amounts of shunt capacitance
exist in the interconnecting cables. Source impedance/cable shunt capacitance products greater than 1
us should be avoided whenever conversions are to be made at maximum rate with less than 1/2 LSB
error. This means that cable shunt capacitance for a 1000 2 source should not exceed 1000 pF (10% X
107 = 107%), that shunt capacitance for a 100 Q source should not exceed 0.01 uF (102 X 1078 = 107),
etc. Assuming twistedpair cable capacitance of 50 pF/foot, these constraints translate into a maximum run of 20 feet from a1000-Q source, 200 feet from a 100-Q source, etc. Note that these values are
consistent with good practice for avoiding noise pickup in long cable runs. Note also that settling
errors can be eliminated by increasing the time between conversions or incorporating a software delay
between channel changes and program start commands.

2.4.3

Connections

Figure 2-6 illustrates the location of user connectors and switches on the component side of the

ADVI11-A board.

Analog input signals are input to the ADV11-A through the 40~pm connector. Pm aamgnmmm for the
connector are shownin Figure 2-7. le proper Berg-to-Berg cabl
O8R; the prop:

prepared open-ended cableis the BCO4Z. (See Maintenance chapmr for further mfomatwn )

2.43.1 Distribution Panel - Figure 2-8 shows an H322 Distribution Panel thatis connected on the
rear to the ADV11-A Berg connector and on the front provides easily identifiable and conveniently
accesmbm barrier strip connections fm user apparatua Each H322 accommodates two ADV11-As or
one

ADV11-A

and one

other

single-connector device. The A’,, Vi1-A ms’_,nép«, with decal sets that

specxfiaamy 1dm1ttfy ADV11-A mputs andwtputs Note

3-B Potentiometer Box may not

be used with the ADV11-A. (See Maintenance chaptm' for appmpmwpotentiometer box circuit.)

2.4.3.2

ExternalandClock Starts- The external start signal line, pin B of the Berg connector or TAB

S (see Figures 2-6 and2-7),is a TTL-compatible input thatpresents five unit loads (8.C0 mA) to any
drwmg output. Conversmns stamon thehigl "i‘wwalow tmnmmm of thwmgnal
In most cases, the external start signal will be produced by a grounded(non-»flaatmg) pulfie generator

or lagw cnrcmtry lmatedin a groundwd mmumem Thoz
return path_fmtheExwmal
Start mgnal will be

puwr smum be mnmm ad wpf { ~ j ‘em a& mm sMart‘fi‘i: ;jyt;laf''dwuw’gmmf nmIn m case thul‘1a
cen

grounded source and flw computer ground.Only with floating

groundani«_immcgr mndpmn on the AbVl 1~»A

jumper (anum 2-9) w AB S (Fmgum 2-6) Qf the ADVI lmA

2-11

SINGLE-ENDED
JUMPER LUGS

—ADORESS

SWITCHES _

e
="

wwz«sm/‘ \Gm BITH
ADJ

VEC:TOR

—
-

(Ex‘r&:mm.

swiITCHES-

smm)

Figure 26 , ADV 11-A Connectors and Switches
Convemmns that must be nmtmtedin c@nscquence of tmw mtervals m cm cvery mh axtemal ewm may
be triggered from the KWV11-A through a DEC 7010771type Jumper mmmcwd fmmthe clock

output tab (CLK)to the ADVH A clock overflow tab (C)

2.43.3 Mode Control -The ADVI11-A is equipped with jumper lugs (see Figure2-6) that permit
changmg operating moda from quammdxfferentml (no cmnmtwn) to mnglammdad (jumper installed).
The single-ended modecan also be selected by connecting Berg connector pin C to logic ground. This
alternativeis provided to permit convenient external mode sclectmnin mstallatmns that requlm frequem alternatmn between one mode and the other.
~
o
il
"

2.4.4 Vectm aml Address Selecmn Devxce and vactm addre&w&are asm md to the ADV11-A by
means of two switch packs.(S2andS,Fagure 2«-6)S2iisapack wnmmmg 10 single-pole/single-throw

switches, numbered 1-10,that

to be set by the pmwsm

communic

data

lines

BDA!

ssuming

BDAL lines 12-15

o 1, S1. permns assigning any addm&s ;.twwn, 170000 and 177774. The

recommendedaddress forthe ADV11-AStatusRegisteris 170400,

set as illustratedin Figure 2-10(a).

Th(;{Dam BuffarRemstcr auton aucally receives the next evenaddressfallawmgthatassxgmdtothe

2-12

LOGIC 6ND =

|
EXT START L

RAMP

ANALOG GND ‘g,

~ 4.5V

CH 17

~CH 07

CH X7

- CH 15

-CH 05

CH X5

-+ 4,5y

ANALOG GND ¢

CH14

-CH

CH X4

CH O7

+CH

CH 07

CH 06

+CH

CH 06

CHO5

+CH 05

CH 05

4CH 04

CH 04

o—%

cHo4

o—4>2

CH13

-CH 03

CH X3

o——4——CH12

-CHO2

-CH

CH X1

-CH

——4+—o0

f——

~CH11

o——F—=—

CH X0

+——CH 03

+CH 03

CH 03

- 18V TEST

}—— CH 02

+CH 02

CH 02

+15Vv TEST

CH O1

+CH Of

CH O1

CH OO

+CH 00

CH 00

SINGLE

DIFFERENTIAL

CH 10

ENDED

H322

NOMENCLATURE

BOARD SIDE
-1 TO

Figure 2-7

ADV1I-A 10-Pin Connector Pin Assignments

Figure 2~8 H3

Distribution Panel

‘means of S1, an 8-switch pack of which only six
e with IDAL lines 3 through 8 and can be set in

,‘_lly’ wcwww an addmm thatis;fam lcmatxms

i TM

M-0599

Figure 2-9
2.5

Module Jumpers

PROGRAMMING

Bit 14: ERROR INTERRUPT ENABLE ( Read/ Write)-When set, enables a program interrupt upon
an error condition (A/D ERROR) Interruptis gcnerated whenevcr bits 14 and 15 are set, regardless

of which was set first.
Bits 13-12: Not used.

Bits 11-8:

MULTIPLEXERADDRESS ( Rmd/ Wme’) Ccmtam thcnumber M me current anal»g

input channel bemg addmmed

Bit 07 A/D DONE(R
M Set at the mmletmn af a conversion whwthe dat‘ m: ffer is flpdamd

Cleared when the data bufferis read and by the processor INITIALIZE. If enabled interrupts are
requested simultaneously by both bits 07 and 15, bit 07 has the higher priority.

2-14

When set, enables a program interrupt at the
Bit 06: DONE INTERRUPT ENABLE (Read/Write)is- generat
ed when bit 07 and bit 06 are both set,
completion of a conversion (A /D DONE). Interrupt
|
regardless of sequence.

Bit 05: CLOCK START ENABLE (Read/ Write) - When set, enables conversions to be initiated by an
|

overflow from the clock option.

set, enables conversions to be initiated
Bit 04: EXTERNAL START ENABLE (Read/Write) - When
the clock option.

by an external signal or through a Schmitt trigger from

Bit 03: ID ENABLE (Read/Write) - When set, causes bit 12 of the Data Buffer Register to be loaded

to a 1 at the end of any conversion.

converted data output equal
Bit 02: MAINTENANCE (Read/ Write) - Loads, when set, all bits of the on.
Cleared by the processor
conversi
next
the
of
on
to Multiplexer Address LSB (bit 08) at the completi
ion logic.
INITIALIZE. Used for “all 0s” and “all 1s” tests of A/D convers

;

Bit 01: Not used.

Bit 00: A/D START (Read/ Write) - Initiates a conversion when set. Cleared at the completion of the
conversion and by the processor INITIALIZE.
0

OCTAL EQUIVALENT

oJofoltt]t]"]airvaue
i

CSR ADDRESS
SWITCH (52)

of lof Lo

;

‘amu BIT

10 1111 "¢12 133 141 5
07 08 09 10
00 Of 02 03 04 O 5'066 O7

BOARD

" HANDLE

POSITION

a. CSR ADDRESS SWITCH (SET FOR 170400)

;

BOARD

FINGERS
|

O OCTAL EQUIVALENT
0
0
4
0
0
e e
e

[0[0!0

oJoJofo]&wvatue

0!0]0

VECTOR

SWITCH (S1)

|
Ll

‘

00 O1 02'03 04 05 06 O7 08 09 10 11 12 13 14 {5

BOAL BIT

POSITION

*sWITCHES NOT CONNECTED

b. VECTOR ADDRESS SWITCH (SET FOR 000400)

114171

Figure 2-10 ADVI11-A Address and Vector Switches (Rocker or Slide Switches)
2-15

MSB |

LSB

ERR

NOT USED

]

—

MUX ADDRESS
READ/WRITE

DONE
INT ENA

ERR
INT ENA

AD
DONE

EX
START
ENA

CLK
START
~

MAINT

ID
ENA

ENA

AD
START

NOT USED

H-431¢

Figure 2-11

ADV1I-A Control/Status Register (CSR)

VERNIER D/A {WRITE)

|
15

“mMsB
T

, 08

MSB

LSB
06

, 05

, 02

—

LS8 ,

CONVERTED DATA (READ)
1i-4312

Figure 2-12

ADVI11-A Data Buffer Register (DBR)

2.5.2 Data Buffer Register (DBR)
The DBR is actually two separate registers - one
read

only, the other write only.

Read Only (Cleared at processor initialize)
Bits 15-13: Not used. Should read as 0.

Bit 12: ID (Read) - When ID ENABLE (bit 03)
of the CSR has been set, DBR bit 12 will be
loaded to a 1 at the end of conversion.

~ Bits 11-00: CONVERTED DATA (Read) - These bits contai

n the results of the last A/D

conversion.

Write Only (Set to 200; at processor initialize)

Bits 15-08: Not used.

Bits 07-00: VERNIER D/A (Write) - These bits provid

e a programmed offset to the converted

value (scaled 1 D/A LSB = 1/50 A/D LSB). The
hardware initializes this value to 200 (midrange). Values greater than 200; make the input voltage
appear more positive.

2-16

2.5.3

Programming Example

Read 100 A/D conversions from channel 0 into locations 4000s-4176s and halt.
START:

LOOPT

CLR

AADSR

JCLEAR A/D STATUS REGISTER

MOV

#4000, RO

ySET

AADSR
LOOP
QADSR

JCHECK DONE FLAG
$WAIT UNTIL FLAG SET
) START NEXT CONVEFSION#

INC

TSTR
BPL
INC
MOV

UP FIRST

@ADSK

@ADBR, (RO)+

yPLACE CONVERTED
gFROM A/D RUFFER

s LOCATION
CMP

ADSR?

ADBR1

VALUE
INTQ MEMORY

AKD SET UP

s LOCATION FOR TRANSFER#

RO, #4200

sCHECK
sHAVE

BNE

ADDRESS

s START A/D CONVERSTON

LOOP

sNO,

IF 100 CONVERSIONS

BEEN

DONE

GET NEXT CONVERSION

HALT

;s DONE

170400

sA/D STATUS REGISTER ADDRESS

170402

+END

sA/D

START

BUFFER

ADCRESS

*Starting a subsequent conversion before moving data from a previous conversion is to be recommended only

~with systems equipped with non-processor memory refresh, as provided in the REV11 options. Without this

capability, data will be lost occasionally by CPU memory refresh intervening between the INC and MOV commands. In general, non-processor memory refresh is essential to realizing the full potential of the ADV11-A.

2-17

CHAPTER 3

KWV11-A PROGRAMMABLE REAL-TIME CLOCK

3.1

GENERAL DESCRIPTION

The KWV11-A is a programmable clock/counter combination that provides a variety of means for
determining time intervals or counting events. It can be used to generate interrupts to the LSI-11

processor at predetermined intervals, to synchronize the processor to external events, or to measure
time intervals or establish programmed ratios between input and output events. It can also be used to
start the ADV11-A Analog-to-Digital Converter either by clock counter overflow or by the firing of a
Schmitt trigger.

The clock counter has a resolution of 16 bits and can be driven from any of five internal crystalcontrolled frequencies (100 Hz to 1 MHz), from a line frequency input or from a Schmitt trigger fired
by an external input., The KWV11-A can be operated in any of four programmable modes: single
interval, repeated interval, external event timing, and external event timing from zero base.
The KWV11-A includes two Schmitt triggers, each with integral slope and level controls. The Schmitt
triggers permit the user to start the clock, initiateA /D conversions, or generate program interrupts in
|

response to external events.

The physical structure of the KWV11-A is illustrated in Figure 3-1. The unit is contained on one quad
size module whose fingers interface to the LSI-11 Bus. User interfacing for the Schmitt triggers and
clock overflow signals is accomplished by means of a multi-pin connector (J1). FAST ON connectors
(CLK. STI1) are provided to permit direct and simple connections of clock overflow and Schmitt
trigger outputs to corresponding terminals on the ADVI1-A A/D Converter. Switch packs permit
selecting CSR (Control/Status Register) address, interrupt vector address, and Schmitt trigger slope
and level conditions. Screwdriver controls (R18 and R19) permit setting Schmitt trigger levels. Provision is also made via the multi-pin connector J1 for external user-provided slope switches and level
3.2
3.2.1

controls.

SPECIFICATIONS
Clock

0.01%

Accuracy

Range

‘Base frequency (10 MHz) divided into five selectable rates

(1 MHz, 100 kHz, 10 kHz, 1 kHz, 100 Hz); line frequency;
Schmitt trigger 1 input

3.2.2

Input and Output Signals

All inputs and outputs are TTL compatible unless otherwise specified.

21N

==
S2

CLK ST1

o 1]

BIT 1

BIT

beosssmommmsmsonend

ADDRESS

SWITCHES

‘

BITS

BIT 3
VECTOR
SWITCHES

J
Figure 3-1

3.2.2.1

t11-4318

KWVII-A Connectors, Switches, and Controls

Input Signals

I. “STI lN(SchmittTrigger'l Input)
Input Range
(maximum limits)
Assertion Level

-30 Vto +30V

Depends upon position of slope reference selector switch
and level control; triggering range, -12 Vto +12 V

Origin

User device

Response Time

Depends upon input waveform and amplitude; typically
600 ns with TTL logic input

Hysteresis

Approximately 0.5 V, positive and negative

Characteristics

Single-ended input; 100 kQ impedance to ground

ST2 IN (Schmitt Trigger 2 Input)
Same description as ST1 IN

3-2

3.2.2.2

Output Signals

CLK OV (Clock Overflow)

Asserted Level

Destination

Low

USer device or ADVI1I-AApproximately 500 ns

Duration

Characteristics

TTL dpcnwcollectm driver with 470 pull-up to+5V
Maximum source current frorri output through load to

ground when output is high (= 2.4 V). 5 mA

Maximum sink current from external source voltage
through load to output when output is low (<0.8 V): 8 mA
2.

ST1 Out (Schmitt Trigger 1 Output)

Same description as CLK oV

ST2 OUT (Schmitt Trigger 2 Output)
Same description as CLK OV |

3.2.2.3 Power Requirements (from LSI-11 Bus Power Supply)
+5V
+12V

3.3
3.3.1

1.75 A typical
10 mA typical

FUNCTIONAL DESCRIPTION
Bus Control

Figure 3-2 illustrates the KWV11-A in block diagram form.

The logic associated with the bus control block maintains proper communications protocol between
the processor bus and the KWVI11-A. This logic generates and monitors the bus signals involved

during interrupts and data transfers between the processor and the KWV11-A. It permits the KWV11A to recognize when it is being addressed by the processor (address defined by the Address Switch
Pack), to prescribe the location in memory pointing to the starting addresses of interrupt service
to input control data from the processor, and
routines (by means of the Vector Address Switch Pack),
|

to output data to the processor.

Interrupts can be enabled for both counter overflow and operation of ST2. Since each of these conditions raises a flag bit in the Control/Status Register, and since separate interrupt vectors exist for each
condition, the conditions may be distinguished either by vectors or by testing flag bits.
3.3.2

Control/Status Register

“

The Control/Status Register (CSR) provides a means for the processor to control the operation of the
KWV11-A and to derive information about its operating condition. Bits are provided for enabling
interrupts, mode selection, maintenance operations, starting the counter, and overflow and Schmitt
trigger event monitoring. (See Figure 3-9 and Table 3-1.)

3-3

BUS CONTROL
|

sxsgfu-———’\,
|

L
.

-—W
ADDRESS

PACK

—

-~/

“

sT2L
‘

BWBT L, BOIN L

ADDRESS &

_—l

CSR 15-9

BRPLY

“‘

o CLK OV

osc

1oMHz | DIVIDER
!

| MRz
100 KHZ

CONTROL

I'sel CLK H

10 KHZ
1

;

SCHMITT TRIGGERS | |

vV STIIN

}

BEVNT L

P
ST1

%:s*r LEV 1

ST1 oUT L | Y

S gST LEV 2

ST2 OUT L HH

(J1)

KHZ

100 HZ

C(;fi}’ggfll.

————— DATE

:"'> *

CSR 5-3

ST2 FLAG H

BSYNC L, BDOUT

BEVNT L

::>n

TIMING CONTROL

(J1)

(CSR)

CONTROL/
STATUS
| REGISTER

INTERRUPT CONTROL

RR
<

' CLK

‘

v \<

BIAKO L, BIAKI L

CLR LD

~1+

BBS7 L

COUNTER ||

ADDRESS LINES

BPR 15-0

BIRQ L, BINIT L

)

CLK OV L

BUS
DATA/
|
BDAL 15-0 L

BPR

ADDRESS

(

&
VECTOR

RDAB 15-0

VECTOR H| SWITCH

—1

BUFFER

PRESET

gj’”

$
T

S )3T2 t N

WST SLLOPE

p\f

Figure 3-2

8T1

sT2 L _

ST SLOPE 2

.
;

* MISCELLANEOUS
INTERNAL

CONTROL

SIGNALS

KWVI11-A Real-Time Clock Block Diagram

3.3.3 Mode Control
Logic circuitry associated with the mode control block permits KWV11-A operation in four different
modes as specified by bits 2-1 of the CSR.
|
'
|
-

3.3.3.1

Mode 0 (Single Interval)

When the GO bit is set in this mode either by the processor or by a Schmitt Trigger 2 event, the

counter

processor intervention.

is loaded from the Buffer/Preset Register (which has previously been loaded with the 2’s complement
of the number of counts desired before overflow). Once loaded, the counter will increment
at the
selected rate until it overflows. Overflow clears the GO bit, sets the Overflow Flag, and interrupts
the
processor if that function has been enabled. If interrupt has not been enabled, the KWV11-A
waits for
-

3.3.3.2 Mode 1 (Repeated Interval)
When the GO bit is set in this mode, the counter is loaded from the Buffer/Preset Register
(BPR) and
is then incremented to overflow
as for Mode
0. In Mode 1, however, overflow does not clear the GO
bit; instead, it causes the counter to be reloaded from the BPR, raises the Overflow Flag, initiates
an

interrupt sequence if the CSR Interrupt on Overflow bit is set, and causes the count to be continued

with no loss of data.

3.3.3.3

Mode 2 (External Event Timing)

When the GO bit is set in this mode, the counter is set to 0 and then incremented at the selected rate as
long as the GO bit remains set. An external signal to Schmitt Trigger 2 (ST2) causes the current
contents of the counter to be loaded into the BPR while the counter continues to run. At the same time
the ST2 Flag is set and, if Interrupt 2 is enabled, an interrupt is generated, thus permitting the program
|

to read the value held in the BPR.

The counter continues to run after the ST2 event and also continues to run after overflow. Interrupt on
Overflow may be enabled to alert the program to the overflow condition.
3.3.3.4

Mode 3 (External Event Timing from Zero Base)

Operation in Mode 3 is identical to that in Mode 2 except that the counter is zeroed each time an ST2
event loads its contents into the BPR.
3.3.3.5

Flag Overrun

In all modes, if a second overflow occurs before the Overflow Flag is reset (i.c., before a prior event is
serviced by the processor), or if ST 2 fires when the ST 2 flag is already set, the Flag Overrun bit is set.

3.3.4

Oscillator, Divider, Rate Control Chain

The circuitry associated with these blocks provides the time base that is fed to the counter. The
KWVI11-A permits eight clock conditions to be specified by bits 5-3 of the CSR: STOP, 1 MHz,
100 kHz, 10 kHz, 1 kHz, 100 Hz, an external time base applied to ST1, and line frequency (50 or 60
Hz) picked up from bus line BEVNT. External periodic or aperiodic pulses may be applied to ST1 and
counted, provided they meet the criteria in Paragraphs 3.2 and 3.3.6.

3.3.5

Buffer/Preset and Counter Registers

The Buffer/Preset Register is a word-oriented, 16-bit read/write register that can be loaded either
under program control or from the counter. In Modes 2 and 3, the firing of ST2 causes the BPR to be
loaded with the contents of the counter. The BPR cannot be loaded by the program in these modes as
long as the GO bit is set.

The counter is a 16-bit internal register accessible only by way of the BPR; in Modes 2 and 3 it can be
read indirectly through the BPR.

3.3.6

Schmitt Triggers

Both Schmitt triggers are equipped with switches to permit selecting slope direction (+ or -) and
threshold reference level (TTL or -12V to +12V continuously variable). Each Schmitt trigger is also
equipped with a screwdriver-operated potentiometer to permit setting the variable threshold level.
to multiple connector J1 to permit attachSwitch-pack and potentiometer terminals are all brought
ment of external user-provided slope and level controls. (See Figure 3-3.)

‘

The two Schmitt triggers are used in somewhat different ways:

STI - Performs as an external time base input or external input for aperiodic signals to be
counted. Outputs both to STI FAST ON connector to provide external start signals to ADV11-A
and, through rate control circuitry, to permit selection as input to the counter. Maximum frequency varies as a function of input waveform.

ST2 - When the ST2 GO ENABLE bit is set, firing ST2 in any mode sets the GO bit and initiates
an interrupt if that function is
to be asserted, and generates
the ST2 Flag
counter action, causes
the Buffer/Preset Register to
causes
ST2
firing
3,
and
2
Modes
the GO bit is set in
enabled. When
be generated if enabled.
to
interrupt
an
and
set,
be
to
Flag
ST2
the
be loaded from the counter,

3-5

EXT ST1 $

LEVEL POT 2

(5~ 20K)

EXT ST2 §

LEVEL POT 2

.iL

(5 - 20K)

OR PP

(BOTH ARE GND.)
,

EXTERNAL

SLOPE 1
SWITCH
L
EXTERNAL
SLOPE 2
SWITCH
o0

BOARD

HANDLE

OFF

ON
OFF

OFF
OFF

‘

UNUSED

BOARD

”“‘IERS

NOTE :

For proper operation of external level controls, both RI8 and R19
on KWV1i-A

board

must be set to approximate mid
- point of

rotation, and the S2 switches must be set as shown.

~w 4337

‘

Figure 3-3 Connecting External User-Supplied Slope and Level Controls

3.4

CONNECTORS, SWITCHES, AND CONTROLS

Figure 3-1 illustrates the location of user connectors, switches, and controls on the component side of
the KWVI1I-A board.

3.4.1

40-Pin Connector

Figure 3-4 illustrates the 40-pin connector pin assignments for user inputs and outputs. These pins may
be connected to the optional H322 Distribution Panel* (see Paragraph 2.4.3.1) for convenient external
user access. The proper Berg-to-Berg cable is the BCOSR. The proper Berg to prepared open-ended
cable is the BC04Z.

3.4.2
FAST ON Connectors (Clock Overflow and ST1 Outputs)
|
Two FAST ON connector tabs labeled CLK and ST1 are situated in the upper-right corner
of the
KWVI1-A board (see Figure 3-1). These tabs are electrically in parallel with pins RR (CLK OV L) and
UU (ST1 OUT L) on the 40-pin connector and are intended to facilitate connections by means of
module jumpers (shown in Figure 2-9)
to the clock overflow and external start inputs on the ADV11-A
(see Paragrapgh 2.4.3).
|
o
|

343

Selector Switches (Address, Vector, and Slope/Reference Level)

Figure 3-1 identifies three switch packs (S1, S2, and S3) that the KWV11-A provides to facilitate the
selection of CSR address, vector address, and slope/reference
level conditions for Schmitt Triggers 1
and 2.
|
|
|
|
*The KWV11-A is shipped with decals which permit permanent identification of signal lines associated with H322

3-6

terminals.

o
o-

+3v

o
o
o

L
o
N_
o
o—®

__potT2
poT 1
siore 2

A
M
Pl

Ll
o
EEl

o
o

0o
Fe

s
WM
AA

‘

sLoPE 1

o
-

)

B
D

Al o
L o

1111

—-cLKovL

ST 20UT L

ST 2 IN

VWosTiIN

ST 10UT L —
F

1"-4175%

BOARD SIDE

40-Pin Connector Pin Assignments

Figure 3-4

3.4.3.1 Address Selection — Switch Pack S1 contains 10 single-pole/single-throw switches that communicate with data lines BDAL 11-2. The KWV11-A reads the BDAL lines only in response to BBS7
which the processor asserts only for an address of 160000 or higher. For this reason, and because the
KWVI1-A transceivers are hard wired to respond only when BDAL bit 12 is set to 1, S1 permits
assigning the CSR any address ending in 0 or 4 between 170000s and 177774s. The recommended
address for the KWVI1-A CSR is 170420, set as illustrated in Figure 3-5. The BPR automatically
receives the next even address following that assigned to the CSR.
4

A4
i

OCTAL EQUIVALENT

sl %

;

[T L

15'14 13

L L

12 '11

[

«—— BOARD HANDLE
,

[ 1 |eesiion

10 09 08 07 06 05 04 03 02 O1 00

'BOARD FINGERS ——

NOTE:
1. Switches may be of either
rocker or slide variety.

Figure 3-5

1-41T6

KWV11-A CSR Address Switches (Set for 170420)
3-7

3.4.3.2
Vector Selection - The clock overflow interrupt vector address is set by means of S3, a 7switch pack of which only six switches are utilized. These switches communicate with BDAL lines 8-3
and can be set in increments of 10s. The ST2 interrupt vector automatically receives an address that is

four locations higher than the clock overflow interrupt vector whose recommended address is 0000440

(see Figure 3-6).

o)
r""*"'w

0
A

"5 I

4
A

N¢

4
A

0
A

OCTAL EQUIVALENT
TM%

ofofofofefofo]rfofofrTooloTo o]koeicar,
LOGICAL

Fls

L1l
15

<+—— BOARD HANDLE

LT
10

| s3

T
07

T
06

T
04

T
03

T e

BDAL BIT
POSITION

BOARD FINGERS

-——

NOTE

Switches may be of either
rocker or slide variety.

Figure 3-6

11-4177

KWVI1I1-A Vector Address Switches (Set for 000440)

3.4.3.3 Slope and Reference Level Selector Switches and Controls (See Figure 3-7) - Slope and refer~ence level selection for ST1 and ST2 are accomplished by means of S2, a 7-switch pack of which only
switches 1-6 are used. Two reference modes are selectable for each Schmitt trigger — one that picks a
fixed level appropriate to TTL logic, and one that picks a variable level that permits setting the ST
threshold to any point between -12 and +12 V.
|
,

NOTE

User should take care that both TTL and variable
switches for either Schmitt trigger are not on simultaneously. This condition will do no damage to com-

ponents, but produces unpredictable reference levels.
Note also that if no signal is connected to a Schmitt

trigger input, both threshold switches for that ST
should be open for noise immunity. Alternatively,
ST1 IN and ST2 IN can be grounded externally.

Slope selection is accomplished by separate switches for ST1 and ST2, respectively. When the related

switch is on, the firing point effectively occurs on the positive slope of the input waveform. When the
switch is off, the firing point occurs on the negative slope. (See Figure 3-8.)

3.5

PROGRAMMING

3.5.1 CSR Bit Assignments
CSR bit assignments are identified in Figure 3-9 and defined in Tablc 3-1.

3-8

owwc____r_é__\ou

TTL REFERENCE

(J1-N)
(J1-1)

} ST LEVEL 1

1 ST LEVEL 2

VARIABLE REFERENCE

[

R18 ge— R19 3
1

14—

BOARD HANDLE

ST SLOPE 1(J1-T)

ST SLOPE 2(J1-R) BOARD FINGERS
NOT USED

HW-4178

Figure 3-7 KWV11-A Slope/Reference Level Selector Switches and Controls
Buffer/Preset Register (BPR)

3.5.2

The BPR is a 16-bit, word-oriented, read/write register. Any attempt to write a byte into this register
will result in a whole word being written. In Modes 0 and 1 the program may load it with the 2’s
complement of the number of counts desired before overflow. In Modes 2 and 3 it permits indirect
reading of the clock counter.

Normal Control Sequences

3.5.3

3.5.3.1 Mode 0 (Single Interval) - Control code for operation in Mode 0 must support the following
sequence:

Control program writes desired count (2’s complement) into BPR (see Paragraph 3.3.5).

Program writes control code into Control/Status Register as indicated in Table 3-2.

If GO bit is set high, KWV11-A responds by loading the 16-bit counter (see Paragraph 3.3.5)
from the BPR and enabling the counter; if GO bit is set low and ST2 GO ENABLE bit is set
high, KWV11-A waits for ST2 event, then sets the GO bit and loads and enables the
counter.

5.
6.

Counter increments until overflow, then halts (GO bit is cleared)

KWVI1I1-A raises Overflow Flag and issues interrupt if the CSR INT OV bit is set; if inter-

rupt is not enabled, KWV11-A waits for program intervention.

Program responds to interrupt or intervenes in consequence of other criteria (¢.g., testing the
w used to start an A/D conversion).
was
Overflow Flag or the A/D Done Flag if overflo
Program reads the CSR, clears the Overflow Flag, and if no counting or mode changes are
required, sets the GO bit or the ST2 GO ENABLE bit to reenter the sequence at step 3.

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Table 3-1 KWV11-A CSR Bit Definitions
15 ST2 Flag

Read/Write to 0

Remarks

Set By /Cleared By

Bit

of Schmitt Trigger
' Set by the firing

2 or the setting of the MAINT ST2
- bit in any mode while the GO bit or
the ST2 GO ENABLE bit is set.
Cleared under program control.
Also cleared at the “1”’-going tran-

sition of the GO bit unless the ST2

- GO ENABLE bit has previously
~

14 INT 2

(INTERRUPT
ON ST2)

been set.

Set and cleared under program
control.

When set, the assertion of ST2 Flag
will cause an interrupt. If set while

ST2 Flag is set, an interrupt is
initiated. When cleared, any pending ST2 interrupt request will be
cancelled.

Read /Write

13 ST2 GO
ENABLE

Must be cleared after servicing an
ST2 interrupt to enable further
interrupts. When cleared, any
pending ST2 interrupt request will
~ be cancelled. If enabled interrupts
are requested at the same time by
| bits 07 and 135, bit 07 has the higher
~ priority.

Set and cleared under program con~ trol. Also cleared at the “1’’-going
- transition of the GO bit.

When set, the assertion of .ST2 Flag

will set the GO bit and clear the
ST2 GO ENABLE bit.

Read/Write

12 FOR

(FLAG OVERRUN)

- Set when an overflow occurs and

Read /Write

~
11 DIO
(DISABLE
INTERNAL

the Overflow Flag is still set from a
previous occurrence, or when ST2
fires and the ST2 Flag is already
set. Cleared under program control
and
at the ‘“1”-going transition of

This bit provides the programmer
with an indication that the hardware is being asked to operate at a
speed higher than is compatible
with the software.

the GO bit.
Set and
control.

cleared

under

program

OSCILLATOR)

For maintenance purposes, this bit
inhibits the internal crystal
oscillator from incrementing the
clock counter. Used in conjunction
with bit 10 below.

Read /Write
10 MAINT OSC

Set under program control. Clear-

ing is not required. Always read as

Write Only

9 MAINT ST2

Write Ofily |

‘MO.‘!!‘

Set under program control. Clearing is not required. Always read as
a0

3-11

For maintenance purposes, setting
this bit high simulates one cycle of
the internal 10 MHz crystal
oscillator used to increment the
clock counter.

Setting this bit simulates the firing

~of Schmitt Trigger 2. All functions
initiated by ST2 can be exercised
under program control by using
this bit.

Table 3-1

KWVI11-A CSR Bit Definitions (Cont)

Bit

- Set By/Cleared By

Remarks

8 MAINT STI

Set under program control. Clearing is not required. Always read as
a “0.”

Setting this bit simulates the firing
of ST1. All functions initiated by
ST1 can be exercised under program control by using this bit.

Set each time the counter overflows. Cleared under pmgram control and at the *“1”’-going trans:tlonw
of the GO bit.

If bit 6 is set, bit 7 set will initiate an
interrupt. Bit 7 must be cleared
after the interrupt has been serviced
“to enable further overflow interrupts. If cleared while an overflow
interrupt request to the processor is
pending, the request is cancelled. If
enabled interrupts are requested at
the same time by bits 07 and 15, bit
07 has the higher priority.

Set and
control.

When this bit is set, the assertion of
OVFLO Flag will generate an interrupt. Interrupt is also generated if
bit 6 is set while OVFLO Flag is set.
If cleared while an overflow inter-

Write Only

7 OVFLO FLAG

Read/Write to 0

6 INTOV
(INTERRUPT ON
OVERFLOW)

cleared

under

program

Read/Write

rupt

request

the

processor

pending the request is cancelled.
5:3 RATE

Set and
control.

cleared

under

These bits select clock counting rate

program

or source.

Read/Write

Rate

0
0
1
1

0
1
0
1
0
1
0

STOP
IMHz
100 kHz
10 kHz
1kHz
100 Hz
STI

Line (50/60 Hz)

0
O
1
1
2:1 MODE

Read/Write

0 GO

Read/Write

Set and cleared
' comml

undcr

program

‘Set and cleared under program control. Also cleared when the counter
overflows in Mode 0.

3-12

Mode0:

Mode I:
Mode2:
Mode 3:

0
1
1

1
O
1

Setting this bit initiates counter

~action as determined by the rate
and mode bits. In Modes 1, 2, and 3
it remains set until cleared. In
Mode 0 it clears itself when counter
overflow occurs. Clearing bit 0
zeroes and inhibits the counter.

4 § 14

12) 11

'
ST2
FLG

INT 2

sT2
GO ENA

MAINT
ST2

FOR

09 |} 08

MAINT
0sC

OVFLO
MAINT

FLG

ST1

03 , 02

NI
|

RATE

INT OV

RATE

RATE
0

MODE
A

GO
11-4310

Figure 3-9

CSR Bit Assignments

3.5.3.2 Mode 1 (Repeated Interval) - Control code for operation in Mode | must support the following sequence:

Control program writes desired count (2’s complement) into the BPR.
Program writes control code into CSR as indicated in Table 3-3.

If GO bit is set high, KWV11-A responds by loading the 16-bit counter from the BPR and
enabling the counter; if GO bit is set low and ST2 GO ENABLE bit is set high, KWV11-A
waits for ST2 event, then sets the GO bit and loads and enables the counter.
Counter increments until overflow.

KWV11-A reloads counter from the BPR, reenables the counter, raises the Overflow Flag in

the CSR, and issues interrupt to the processor if interrupt is enabled.

If second overflow occurs before first is serviced (i.e., if Overflow Flag is still high when next
overflow occurs), KWV11-A Flag Overrun (FOR) bit in the CSR is set high to alert pro-

gram that data has been lost.

Program responds to interrupt or intervenes in consequence of other criteria. Program reads

CSR, clears the Overflow Flag, and if no counting or mode changes are required, sets the
GO bit or the ST2 GO ENABLE bit to reenter the sequence at step 3.

3.5.3.3 Mode 2 (External Event Timing) - Control code for operation in Mode 2 must support the
following sequence:

Program writes control code into CSR as indicated in Table 3-4.
2.

KWV11-A responds by incrementing the counter (zeroed when the GO bit was cleared) at

the selected rate until the GO bit is set to 0.

ST2 pulse loads current counter contents into BPR, sets the ST2 Flag, and generates interrupt if INT 2 is enabled.

Overflow sets OVFLO FLG high and, if INT OV bit is high, generates interrupt.

Counter continues to increment until processor sets GO bit to 0.

Normally, program enables INT 2 and/or INT OV bits, permitting the processor to synchronize its
operations with the external ST2 events and prevent loss of data by reinitializing the process after step
4.

3-13

Table 3-2
|

CSR

Bit No.

Name

CSR Bit Settings for Mode 0, Single Interval
Bit Condition

as Written by
Processor

Remarks

‘Will be set to 1 on ST2 event. Cleared

ST2FLG

by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.

| INT2

Set to 1 by program if interrupt on

ST2 event is desired.

ST2 GO ENA

FOR

(0)

11 | DIO

MAINT OSC

MAINTST2

| MAINTSTI

‘OVFLOFLG

Set to 1 by program if GO is to be set
by external signal to ST2. Cleared by
leading edge of GO bit assertion.

(0)]

Will be set to 1 by counter overflow.,

Always cleared by leading edge of GO
bit assertion.
6

INTOV

Set to 1 by program for interrupt on

RATE?2

RATE |

RATEO

MODE 1

Set by program to 0.

MODEDO0

Set by program to 0.

Set by program to 1 unless ST2 GO
ENA is set; remains | until written to
0 by program. Cleared when counter
overflows.

(0)

counter overflow.

See Table 3-1.

0 or 1, depending on user requirements.
Automatically cleared by GO bit assertion.

3-14

Table 3-3

CSR

Name

Bit No.

CSR Bit Settings for Mode 1, Repeated Interval

Bit Condition

as Written by

| ST2FLG

Remarks

Processor

Will be set to 1 on ST2 event. Cleared

by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.

Set to | by program if interrupt on

INT 2

ST2 GO ENA
3

FOR

(0)

DIO

MAINT OSC

MAINTST2

MAINT ST

OVFLOFLG
‘

INT OV

RATE 2

RATE |

RATEO

MODE |

MODE 0

ST2 event is desired.

Set to 1 by program if GO is to be set
by external signal to ST2. Cleared by
leading edge of GO bit assertion.

Will be set to 1 by counter overflow.
Always cleared by leading edge of GO
bit assertion.

Set to 1 by program for interrupt on

counter overflow.

See Table 3-1.

Set by program to ls.

Same as for Mode 0, except that bit is
not cleared when counter overflows.

x = 0 or 1, depending on user requirements.

0) = A utomatically cleaémd by GO bit assertion.

3-15

Table 3-4

CSR
Name

Bit No.

1S
v

CSR Bit Settings
for Mode 2, External Event Timing
Bit Condition
as Written by
Processor

[ST2FLG

<
Remarks

Will be set to 1 on ST2 event. Cleared

by leading edge of GO bit assertion

except when ST2 GO ENA has previously been set.
14

INT2

ST2 GO ENA

Set to 1 by program if interrupt on
ST2 event is desired.

Set to 1 by program if GO is to be set

by external signal to ST2. Cleared by

leading edge of GO bit assertion.
12

FOR

(0)

DIO

MAINT OSC

MAINTST2

MAINTSTI

OVFLOFLG

(0)

Will be set to 1 by counter overflow.

Always cleared by leading edge of GO
bit assertion.

INT OV

Set to 1 by program for interrupt on

counter overflow.

RATE 2

RATE I

RATEO

MODE 1|

MODEDO0

|GO

See Table 3-1.

Set by program to 2;.

Set by program to 1 unless ST2 GO
ENA is set; remains 1 until written to
0 by program. Cleared when counter

overflows.

x = Qor 1, depending on user requirements.
(0) = Automatically cleared by GO bit assertion.

3-16

3.5.3.4 Mode 3 (External Event Timing from Zero Base) - Operation is identical to that in Mode 2
except that counter is zeroed after ST2 pulse. Counter continues to increment until GO bit is set to 0.
Note that the interval between two ST2 events may be measured directly in Mode 2 or 3 with processor
assistance if the CSR ST2 GO ENABLE and Interrupt 2 bits are set before the first event and the GO
bit is left clear. Under these conditions, the first ST2 event will set the GO bit (and thus start the
counting process) and simultaneously issue an interrupt. If the interrupt service routine now clears the
ST2 Flag bit, the next ST2 event will cause the BPR to be loaded from the counter in the normal Mode

2 fashion. The choice of Mode 2 or Mode 3 for such measurements will depend on whether or not an
ongoing accumulation of time after the second event is required by the application. If such an accumulation is necessary, Mode 2 is appropriate since the counter is not zeroed after ST2 events.

3.5.4

Programming Example

Record point in double-precision timeframe for each ST2 event following GO. Program makes use of a
32-bit counter, the low order bits of which are taken directly from the KWVI11-A (KWBPR) and the
high order bits of which are taken from a software counter (HICNT) that is incremented with each
KWBPR overflow.

MTPS

MOV

#ST28RV,

@ST2VEC

$#200,@8T2PSW

Mav

#OVSRV, @UVVEC

MOV

$200,00VPSW

sCLEAR P8W

) LOAD 8T2 VECTOR

s ADDR

y)SET UP PSW FOR 872

$ INTERRUPT (DISABLE
JALL SUBSEQUENT
) INTERRUPTS)

s LOAD OV VECTOR
) ADDR

s SET UP PSW FOR 0OV
g INTERRUPT (DISABLE
gALL SUBSEQUENT
§ INTERRUPTS)

]

MOV

SBUFFER,

CLKGU

MOV

#40115,@KWCSR

COUNT:

WAIT
BIT
BEG

)SET

UP POINTER TO

$BEGINNING OF

sBUFFER AREA

sDEPOSIT 1MHZ, MOVE 2,

QINT oV EN' INT 3T2
JAND GO INTO KWCSR

EN:

gFOR INTERRUPT

g8Y

#10000,@KWCSR
CUOUNT

OVFLO

S8T2

11S FQR BIT SET?
§ND, CONTINUE

#100000,@KWCSR

1 YES, SERVICE FLAG
JOVEKRUN CONDITION
3 (S S12 FLAG SET?

TST
BPL
MOV

eKWNBPR
28
HICKT, (RO)+

sDIL ST2 OCCUR BEFORE (V7
gNO, BRANCH
§ YES, SERVICE ST2 FIRST

MOV

@KWBPR, (PO)+

JMP

OVSRV:

BIT

BEQ

BIC

FURSRY
28

¥100000,@KWCSR

gNO,

CONTINUE

s ACKNUWLEDGE ST2
§OCCURRENCE

(example continued on next page)
3-17

HICHT

BEQ

ENDSRV

sBRANCHh

BRIC

$200,@KwCSK

s ACKNOWLEDGE
0OV

RTI
ST2S8RV:

JINCKEASE MSB BY

INC

MOV

MUV

BIC

COUNT

|
JF

INCREASE

sCAUSES OVERFLUw

sCLeAR
JAND

BIT

KRETURN

TUO

MAILIN

$ FROGRAM
HICNT, (RU)+

$GET

RKWBPR, (RO)+

MSp

FROM

sGE1

LSE

FROM

#100
s0G0
@KWCSR

RTI

sACKNUWLEDGE

JALND

KETURN

SOF1 COUNT

HARVD COUNT
ST2

MALNMN

sPRUGKFAM

FORSRY?

JEVELTS

1TCL

OCCURRING
BAST FOR CURKENT

§SERKVICE
]
]

ENDSKHVE

332 B1T QVERFLOW
JUCCURRED

]

KwCSF:
KWBPR:
QVFVEC:

ST2VEC?
HICinT¢
BUFFER?S

]

1703720
170422
440

444
0

LK w

XXXX

P XXXXBLENGTH
FBUFFER

RESULT

CHAPTER 4

AAV11-A DIGITAL-TO-ANALOG CONVERTER

4.1

GENERAL DESCRIPTION

The AAV1I-A is a 4-channel digital-to-analog converter module for use on the bus of the LSI-11
processor. The unit is made up of control and interfacing circuitry, four D/A converters, a dc-dc
converter to provide power to the analog circuits, and a voltage reference. Each channel provides 12
bits of resolution. Each has its own holding register which can be separately addressed and can be
written and read in either word or byte format. In addition, bits 0-3 of the fourth holding register are
as a 4-bit digital output register.
brought to the 1/O connector for use

Jumpers permit manual selection of voltage range and oparating mode (bipolar or unipolar).
4.2

SPECIFICATIONS

Number of D/A Converters

Digital Input |

‘12 bits (binary encoded for unipolar mode, offset binary

encoded for bipolar mode)

Digital Storage

Read-write, word or byte operable, single buffered
+2.56 V, £5.12 V, £10.24 V bipolar; 0 V to +5.12 V, 0 V to

Analog Output Voltage Range

+10.24 V unipolar
Source: 5.2 mA @ 24V
Sink: 16 mA @ 04V

(jumper selected)
Digital Output Characteristics
(DAC 3 Holding Register

Bits 3:0)

Resolution

1 part in 4096

Warm-Up Time

5 minutcs‘mifinimum

Gain Accuracy

ranges may require recalibration)

- 10 ppm per degree C, maximum

Offset Temperature Coefficient

10 ppm of full scale range per d;egree C, maximum

£ 1/2 LSB maximum non-linearity

Differential Linearity
Output Impedance

Adjustable (fact;orywsc“t_fmbipolgr +5.12 V; selection of other

Gain Temperature Coefficient

Linearity

+ 1/2 LSB, monotonic
1 @ maximum at DAC output; 4 Q@ maximum at end of BCO8R

8 ft cable

4-1

Drive Capability

+ 5 mA maximum per converter

Slewing Speed

5 V/us

Rise and Settling Time
(to 0.1% of final value)

4 us: 8 us with 5000 pF load in parallel with 1k Q

Power Consumption
(from LSI-11 bus power supply)

SV5% @ 1.5A,12V@04 A
|

Packaging

One quad module

Bus Loading

| bus load

4.3 FUNCTIONAL DESCRIPTION
Figure 4-1 illustrates the AAV1 I-A in block diagram form.
4.3.1
Bus Control
B
The logic associated with the bus control section maintains proper communications protocol between
the processor LSI-11 bus and the AAV11-A. This logic generates and monitors the bus signals
involved during data transfers between the processor and the AAV11-A, permitting the AAV11-A to
recognize when it is being addressed by the processor (address defined by setting on the Address
Switch Pack), to accept input data from the processor, and to output data to the processor.
4.3.2 Control Logic
The AAVI11-A has no Control/Status Register. The four digital-to-analog converters continually generate voltages at their outputs that reflect whatever digital values have most recently been written into
their respective holding registers. The role of the control logic is to make the necessary discriminations
between requests to change the state of the holding registers (i.e., to write into the holding registers),
and requests to put the holding register contents onto the BD lines where they can be picked up
through the transceivers by the processor.

43.3

DACs 0,1, and 2

Digital-to-analog conversion functions are performed in each of the four AAV11-A channels by identical circuits:
|
|
|
|
o
*

A holding register which stores the digital value output by the processor

A digital-to-analog converter (DAC) proper which generates a current that is a function of
the holding register value and of the mode/level jumper conditions

An amplifier that translates the current into a proportional voltage, provides a low output
impedance for the channel, and permits adjustment of signal offset.

4.3.4 DAC3
DAC 3 is identical to DACs 0, 1, and 2 except that Holding Register bits 0-3 are routed to the I /O
connector as well as to the DAC. This arrangement permits these bits to be routed to external equipment that requires binary control signals at programmable intervals. Control data in these bit positions affects any 12-bit D/A conversion that they coincide with, but since they involve the least
significant bits of the word, the worst-case error is less than 0.5%. Consequently, DAC 3 can be used as
a 12-bit DAC or as an 8-bit DAC plus four output bits for CRT Intensify, Store, Non-Store, Erase,

etc.

!LINXHamNI7an3REACLEi

eTyv Ty r———7

V|hc|~|OMNIy7iaHvE3OyZvooOvvauamu€m7||4mm'_m_,u«.mb7ioo_.lwZJn4oco|voale*
30§ (NIv9)S ASL- AGH+

* 431S1934

a1 A

Nauw7vsazn

1@0*v0a

H _

Ye.

wesdelq YOI|F V-11AVY [-p 2Indig

4-3

.
M

4.4

CONNECTORS, SWITCHES, AND CONTROLS

Figure 4-2 illustrates the location of user connectors, switches, and controls located on the component
side of the AAV11-A board.
S

DACQ

DAC1

DAC2

DAC3

1 0

——1

R46

(OFFFET)

\R34 /N
RA47

/NN
R35 R36
R48

\ R37 (GAIN)

(GAIN) (OFFSET)

DAC O

DAC

WI0_

~ "

W5 -

(GAIN)(GAIN) (OFFSET)

'R49 (OFFSET)

DAC 2

DAC 3

Wi2 WH_

Wi8_ Wi5_

W7 WI6

MODE /LEVEL STRAPS

(ADDRESS)

11-4319

Figure 4-2

AAV11-A Connectors, Switches, and Controls

4.4.1
40-Pin Connector
e
|
Figure 4-3 illustrates the 40-pin connector pin assignments for user outputs. These pins may be con-

nected to the optional H322 Distribution Panel* (see Paragraph 2.4.3.1) for convenient external user

access. The proper cable for this purpose is the BCO8R. Also available is a Berg to prepared openended cable, the BC04Z.
S
L
|
|

Either a VR14 or VR17 CRT may be interfaced to the H322 via a user-created cable terminating in a

24-pin Amphenol, or equivalent, male plug (DEC #12-03466-00). A user-created cable may be con-

nected to other types of CRT systems using
a 25-pin connector such as a male DB25P type plug (DEC

#12-05886-00).

* The AAVII-A is shipped with decals which permit permanent identification of signal lines associated with H322 terminals.

4-4

|
j<«

tfl-—c

& |r
I« |3
€
N IX
@D
@

o
o
L
L "

r
r~

f
-

0
0

-15v TEST — 4 o
+15V TEST m%mmmo
DAC O HQ GND M%M

DAC 3 HQ GND MM
.

DAC 2 HQ 6ND <} o

-n
w

_HH

DAC1 HQ GND

_EE

_cc.

BIT 3 0UT
BIT 2 OUT
BIT 1 OUT

BIT O OUT
DAC

3 OuT

DAC 2 OUT
DAC

1 OUT

DAC O OUT

BOARD SIDE
1-4314

Figure 4-3

40-Pin Connector Pin Assignments

The BCO04Z signal lines may be connected to user-selected pins on a male or female connector. A
female 25 pin connector of the DB25S type (DEC #12-09326-00) may be used for general purposes. A
male 25-pin connector of the DB25P type (DEC #12-05886-00) will interface several popular CRT
systems to the AAVI11. Either a VR14 or VR17 CRT may be interfaced by means of a 24-pin Amphenol, or equivalent, male plug (DEC #12-03466-00) to the BCO4Z. Both the AAV11 and selected CRT
must be set up and adjusted for electrical compatibility. The CRT manual should define appropriate
connector pins for each AAV11 signal line. Appropriate software will be necessary to control a CRT.
4.4.2

Address Switches

Figure 4-2 identifies the location of S1, a switch pack containing 10 single-pole single-throw switches (1
unused) which, when set, transmit 0 logic levels to the compare inputs of the transceivers. Whenever
the AAV11-A sees BBS7 transmit a logical 1 (indicating that the processor has placed an 1/O device
address on the bus), the transceivers compare the pattern created by the switches with that appearing
on Bus Data/Address (BDAL) lines 3-11. If the patterns match, the processor is addressing the
AAV11-A, and the latter prepares to load the DAC holding register identified by decoding bits 1 and 2
|
|
of the address word as defined in Figure 4-4.

Since the AAV11-A makes the comparison only in response
to BBS7 (which the processor sets to 1
only in response to an address of 160000 or higher) when address line BD12 = 1, S1 permits assigning
the four DACs any contiguous set of four even word addresses between 170000 and 177770. The
recommended setting for S1 onthe first AAV11-A is 170440, illustrated in Figure 4-5. Since LSI-11 bus
address assignments for the AAV11-A extend from 170440 to 170476, up to four AAV11-As can be
accommodated on the same processor.

AAV1ii-A

{

no = O:

WORD OR LOW

BYTE

DAC

ADDRESS WORD

06,605

nop =1:HIGH BYTE

ADDRESS

DAC

MODE

170440

)

WORD OR LOW BYTE

170441

HIGH BYTE

170442

WORD OR LOW BYTE

170443

HIGH BYTE

170444

WORD OR LOW BYTE

170445

HIGH BYTE

170446

WORD OR LOW BYTE

170447

HIGH BYTE
11-4313

Figure 4-4
N

AAVI11-A Address Decoding

l"["[“ 010!' ololz 0]010 'l’!*
|

OCTAL EQUIVALENT

BIT VALUE

LOGICAL

BOARD HANDLE

U
N
U
S
E
D

BOARD

L.L1 LT

00
01 02

07 08

T T
12

FINGERS

T T ]esake
{4

Figure 4-5

H-4172

AAVI11-A Address Switches (set for 17044n)

4.4.3

Mode/Level Selector Jumpers
|
As shipped from the factory, the AAVI11-A is set for bipolar operation between -5.12 and +5.12 V.
Unipolar operation and operation with other voltage ranges can be achieved by proper changes in the
mode/level jumpers (illustrated in Figure 4-2). See AAV11-A Installation and Service chapter for

details.
4.5

INTERFACING TO OUTPUT DEVICES

4.5.1
Ground Connections
|
Analog output devices such as oscilloscopes may be either grounded or floating. If the oscilloscope is
grounded, either through its power plug or through contact between its chassis and a grounded cabinet, the oscilloscope ground should not be connected to any of the AAV11-A ground pins. Doing so

may result in a ground loop which will adversely affect scope control results as well as any ADV11-A

operations. If the oscilloscope is floating, its ground should be connected to the AAV11-A logic
ground, pins L, N, R, or T of the Berg connector. Note that the foregoing assumes that the computer
power supply ground is connected to power line (earth) ground. If continuity checks reveal no such
connection, attach a length of 12-gauge wire between the power supply ground and
a convenient point
associated with earth ground.

4-6

Oscilloscope X and Y inputs may be either differential or single-ended. Differential inputs should be
driven as in Figure 4-6.

OSCILLOSCOPE

AAVII-A
‘
—

;'”fl;

X OUT (PIN VV)

‘

ANALOG GROUND (PIN UU)

RIS
MM/

X RETURN

fah

Y IN

)

X _IN

Y QUT (PIN TT)

ANALOG GROUND (PIN H H)
f

i
i
L
N

e
an
L

,
Y RETURN

.
‘

1-a4523

Figure 4-6 Connection to Oscilloscope with Differential Input
When oscilloscopes with single-ended inputs are involved, the AAV11-A analog grounds (pins UU
and HH) are not used. Return path for X and Y signal currents is through ground for a grounded
oscilloscope or through logic ground (pins L, N, R, or T) for a floating oscilloscope. Since the
grounded, single-ended oscilloscope sees an input voltage which is the sum of the AAV11-A output
and the ground difference voltage between the oscilloscope and the AAV11-A, noise and line frequency errors may be minimized by plugging the scope into an ac socket as close as possible to the computer. Running single-ended scopes in a floating configuration will eliminate noise and line frequency
errors which are due to ground voltage differences.
4.5.2

Twisting

The effect of magnetic coupling into the scope input lines can be minimized for a differential-input
scope by running the AAV11-A output and its return line in a twisted pair. No benefit is derived from
a twisted pair with a single-ended scope input.

4.5.3

Shielding

The effect of electrostatic coupling into the scope input lines can be minimized by shielding the input
lines from AAV11-A to the scope. The shield should be connected to ground at one end only. Ground
ing the shield at both ends may result in a ground loop which will adversely affect scope control results
and any ADV11-A A/D operations.

4.5.4

Drive Capability

Careful selection of cabling is essential. The D/A outputs are capable of driving a maximum of 5000
pF. Output impedance is | ohm. Output current limit is 5 mA.

4.6

PROGRAMMING

All four DAC holding registers are automatically set to zero on system initialization. This produces
~5.12 V at the DAC outputs when the mode/level jumpers are connected as delivered from the factory.
Any holding register value remains in effect until changed by the processor in response to a program
instruction. Coding to the D/A converters is offset binary for bipolar operation and straight binary for
unipolar operation. Offset binary defines 0 as maximum negative voltage, mid-point (i.e., 40005 for the
12-bit AAVI11-A) as 0 V, and all 1s (7777s) as maximum positive voltage. These relationships are
illustrated in Table 4-1.

Table 4-1 AAV11-A Digital-to-Analog Conversions*
Bipolar
Input Code | £2.56 V

+5.12V

Unipolar

(volts)

+10.24V | 0Vito+5.12V |
(volts)
(volts)

0Vto +10.24 V

0000
0001

—2.56
—2.55875

3777
4000

—0.00125
0.0
|
+0.00125
+2.55875

-5.12
=5.1175 -

—10.24
—10.235

+0.0
+0.00125

—0.005
0.0
+0.005
+10.235

+2.55875
+2.56
+2.56125

+0.0
+0.025

(octal)

4001
7777+

—0.0025
0.0
+0.0025
+5.1175

(volts)

+5.1175
+5.12
+5.1225

+5.11875

+10.2375

* Offset binary for bipolar, straight binary for unipolar dperating modes. Conversions may be made between
complement signed binary and offset binary numbers by subtracting 40005

2’s

from the 2’s complement number

(or adding 40005 to the offset binary number) and using only the low order

12 bits of the result.

t Note that in all rangés, actual maximum positive voltage output is | LSB less than nominal maximum positive
output.

CHAPTER 5

DRV11 PARALLEL LINE UNIT

5.1

GENERAL DESCRIPTION

The DRVI11 is a general-purpose interface unit used for connecting parallel-line TTL or DTL devices
to the LSI-11 bus over up to 25 feet of cable. It permits program-controlled data transfers at rates up to
90K words per second and provides LSI-11 bus interface and control logic for interrupt processing and
vector generation. Data is handled by 16 diode-clamped input lines and 16 latched output lines. Device
address is user-assigned and Control/Status Registers (CSR) and Data Registers are compatible with
PDP-11 software routines.

BIAKT L

BDALO-1SL

oeen

—t

1
.
»

P e|

L
BSYNC
BDAL 0-15 L

fifi%flffg
CONTROL

BWTET L
BRPLY L

—

“Losic

;

CsR1

RDY
NEW ADATA
INIT

)

—
|

/FROM
TO
USER
DEVICE
LOGIC

REQ B

DATA TRANS

IN 0-15 a

ORINBUF lr_.

\; BDAL O-15 L

J2
J2

B INIT

BINITL

)

REQ A

INTERRUPT

BIRQ L

OUT 0-15

ol DROUTBUE

BDALO —15L

cp-1808

Figure 5-1

5.2.1

Locations

DRV11 Parallel Line Unit

Jumpers for device address and vector selection are provided on the DRV11 as shown in Figure 5-2.
Jumpers are installed at the factory for address 167770 (DRCSR) and vectors 300 (interrupt A) and
304 (interrupt B). These can be cut or removed by the user to program the module for his system
application, as described in the following paragraphs.

)

il
[ ecTor sumpers

VECTOR JUMPERS

!
|

3
7

V7]

— —

PP
; gg

—— A9
ald

—7

ADDRESS JUMPERS

&7..........

Atz

LATM

”

M7941 ETCH REV. C

Figure 5-2

:
|

SLi
.., SL2
om0

OPTIONAL EXTERNAL
CAPACITOR
(SEE PARA.5.3.6)

CP-1809

DRVI11 Jumper Locations

5.2.2 Addressing
|
Jumpers involved with addressing include A3 through A12. Only address bits
03 through 12 are programmed by jumpers for DRV 11 addressing, producing the 16-bit address
word shown in Figure 5-3.
The appropriate jumpers are removed to produce logical 1 bits; jumpers
are installed to produce
logical O bits.
,
5
|
e
ST
5.2.3 Vectors
|
a
|
|
h
~
i
~
Jumpers involved with vector addressing include
V3 through V7. Only vector bits 03 through 07 are
programmed by the jumpers for DRV11 vector addressing, producing the

16-bit word shown in Figure

5-4. The appropriate jumpers are removed to produce logical 1 bits: jumpers
are installed to produce
logical 0 bits.

5-2

%?(S& L
~

o
<

‘

=
¢

‘

o
<«

®
<

~
«

)
<

<
<

"
e

P
‘
ADDRESS JUMPERS:

O=low byte
(0 -7)

00X = DRCSR

01X = DROUTBUF
10X = DRIN BUF
b
41X -

NO RES ct:??i

INSTALLED =0

REMOVED =1

Figure 5-3

DRVI11 Device Address

||
S

5.3
5.3.1

||
g2

VECTOR JUMPERS:

INSTALLED=0
REMOVED =1

Figure 5-4

1=BYTE
highSELECT
byte(8-15)

2
a

REQUESTIN

0:REQ A

VICE

1 =REQB

LP-174%

DRVI11 Vector Address

INTERFACING TO THE USER’S DEVICE
General

Interfacing the DRVI1 to the user’s device is via the two board-mounted H854 40-pin male connectors. Pins are located as shown in Figure 5-5. Signal pin assignments for input interface J2 (connector no. 2) and output interface J1 (connector no. 1) are listed in Table 5-1. The proper Berg-to-Berg
cable is a BCO8R. The proper Berg to open-ended cable is a BCO4Z. Connection to the DRVi1 can be
made through the H322 Distribution Panel (see Figure 2-8). This unit is provided with decals, which
when applied according to instructions on the decal sheet, identify the H322 screw terminals with
respect to the associated pins on the DRV11 Berg connectors (A, B, UU, VYV, etc.). Space is provided
on the decal for specific user identification. Note that DRV11/H322 terminal relationships assumed
by the decal sheet rest on connection of the BCO8R cable so that stamped labels on female cable ends
match embossed labels on male connectors - A/B to A/B, UU/VV to UU/VV. This normally means
that any “this side up”’ labels face away from the board on which the male connector is mounted.
Each BC04Z cable from a DRV11 may be terminated in a female 25-pin connector such as a DB25S
type (DEC #12-09326-00) socket. The user may assign the signal and ground lines from the BC04Z to
specific connector pins. User apparatus may be connected into the socket by means of a male 25-pin
connector such as a DB25P type plug (DEC #12-05886-00).
5.3.2

Output Data Interface

The output interface is the 16-bit buffer DROUTBUF. It can be either loaded or read under program
control. When DROUTBUF is loaded by the CPU, the NEW DATA READY H 300 ns pulse is
generated to inform the user’s device of the data transfer. In order to allow data to settle on the
interface cable, the trailing edge of this positive-going pulse should be used to strobe the data into the
user’s device. The system initialize signal (BINIT L) clears DROUTBUF. When an output line is set to
logi(c):asl :/, the TTL output is high (2 2.7 V); when an output is set to logical 0, the TTL output is low
(£

05V)
5-3

H854

CONNECTOR

HB56 CONNECTOR

(SHOWN WITH
CABLE

INSTALLED)

11-3294

Figure 5-5

J1 or J2 Connector Pin Locations

All output signals are TTL levels capable of dnvmg five unit loads (8 mA sink** @ 0.5V, 400 A

source*** @ 2.7 V) except for the following:

NEW DATA READY
= 10 unit loads
|
INIT (Initialize)* = 10 unit loads/connector

DATA TRANSMITTE
= 30 unit loads
D
"

16 mA sink** @ 04 V, 400 uA
source*** @ 2.4 V

- =48
E

mA smk""" @ 04

murcc”"‘@Z?V

*Comman mgnal on both cmnnectms

IR
** Sink refers to current from external +5 V supply through laad to @utput lme when mutput is low.

***Source refers to current from output line through load to ground when output is high.

5-4

Table 5-1

DRVI11 Input and Output Signal Pins*

Inputs

~ Signal

_Connector] Pin

INOO
INO1
INO2

12
J2
J2

| TT
| LL
| H.E

| BB

INO3

IN4

INOS

INO6
INO7

INO8
INO9
INIO
IN1T

IN12

|HH

OUTO0S

outes

|y
|W
|V

| Connector | Pin

S
J1
1N
|
N

OUTO3

OUT04

n
J2
12

Outputs

OUT00
ouUTO1
OUTO02
|

| EE
| CC

ignal

J2
J2

OUTO06
OUTO07

OUT09
| OUTIO
OUT11

JI.

R
B
B
S
S R
I

R
T

X
/
[AA

Jj2
2

| P
|N

OUTI15

I1|m

REQA
REQB

J1
2.

| LL
|8

NEW DATARDY*
DATA TRANS*
CSRO
CSR1

J1
12
12

\'A%
|C
|K

INIT

| RR,NN

IN13
IN14

IN15

OUTI12

J1
J1

C
K
NN

OuUT13
OUTI14

J1.
J1

INIT

|BB

|FF
HH

*Pulse signalS, approximately 300-ns wide* Width can be‘changad by user.
5.3.3

Input Data Interface

The input interface is the 16-bit DRINBUF read-only register, comprising gated bus drivers that
transfer data from the user’s device onto the LSI-11 bus under program control. DRINBUF is not
capable of storing data; hence the user must keep input data on the IN lines until read by the LSI-11
microprocessor. When it has read the data, the DRVI11 generates a positive-going 300-ns DATA
TRANSMITTED H pulse which informs the user’s device that the data has been accepted. The trailing edge of the pulse indicates that the input transfer has been completed.
All input and request signals are one standard TTL unit load; inputs are protected by diode clamps to
ground and +5 V. A +2.7 V to +5 V input is read as logical 1; 0 V to 0.5 V as logical 0.
5.3.4

Request Flags

Two signal lines (REQ A H and REQ B H) can be asserted by the user’s device as flags in the DRCSR
word. REQ B is available via connector no. 2 and can be read in DRCSR bit 15. REQ A is available
via connector no. 1; it can be read in DRCSR bit 7. Two DRCSR interrupt enable bits, INT ENB A
(bit 6) and INT ENB B (bit 5), allow automatic generation of an interrupt request when their respective REQ A or REQ B signals are asserted. Once the user’s request signal has been asserted (logical 0 to
logical 1 transition), it must remain asserted until the CPU completes interrupt processing. At this
time, DATA TRANSMITTED or NEW DATA READY signals (see Paragraphs 5.3.2 and 5.3.3) can
be used to cancel the request. Note that Request A has a higher priority than Request B, and that each
of the interrupt enable bits can be set or reset under program control.

* Ground pins for connector J1: J, M, S, V, Y, CC, EE, KK, MM, PP, SS, UU. Connector J2: J, L, R, T, X, AA, DD, JJ,
MM, PP, SS, UU.

5-5

5.3.5 Initialization
The BINIT L processor-generated initialize signal is applied toDRV11 circuits for interface logic
initialization. It is also avallable to the user’s circuits via connectors J1 and J2 as follows
Connector/Pin
J1/P

Sngnal
AINITH

J2/RR

BINIT H

J2/NN

BINITH

An active BINIT L signal will clear the following: DROUTBUF data; DRCSR bits 6, 5, 1, 0; bits 16
and 7 (when the maintenance cableis connected); and Intcrrupt Request and Interrupt Acknowledge
flip-flops.
5.3.6 NEW DATA READY and DATA TRANSMITTED Pulse Width Modification
An optional capacitor can be added by the user to the DRV11 module to extend the pulse width of
both the NEW DATA READY and DATA TRANSMITTED pulses. The module without external
capacitance (as shipped) will produce 300 ns pulses. The capacitor can be addedin the location shown
in Figure 5-2 to pmduce the approximate pulse widths listed below.

Optional External
Capacitance (pF)
None
1200
1800

Approximate
Pulse Width (ns)
300
500
600

6000

1200

5.4 PROGRAMMING
5.4.1
Addressing
Addresses for the DRVI11 can range from 160000 thmugh 17777)(3 The least significant three bits
address the desired DRV11 register as follows:

Address*

Device Register

IXXXX0

IXXXX2

DRCSR

DROUTBUF
DRINBUF

IXXXX4

Addresses 177560-177566 are reserved for the console device and should not be used for DRVI11
addressing. The following address assignments are normally used:

First DRV11
DRCSR =167770
DROUTBUF = 167772
DRINBUF = 167774

Second DRVI1

1167760 to 167764

Third DRV11

167750 to 167754

*Address IXXXX6 will not produce a response from the DRVII. |

5-6

Second DRV11
167760 to 167764
Third DRVIl
167750 to 167754

‘

Interrupt Vectors

5.4.2

Two interrupt vectors are jumper-select: ed in the range of 0 through 37Xs. The least significant three
bits identify the interrupting function.

Iénterrupt A

000xx0

Interrupt B

000xx4

Vectors 60 and 64 are reserved for the console device and should not be used for DRV11 vectors.
Word Formats

5,43

The three word formats associated with the DRV 11 are shown
in Figure 5-6 and are described in Table
5-2.

FERITUER

TS 7

1/0 Timing

54.4

I/0 transfers through the DRV11 occur as illustrated in Figure 5-7.

(READ ONLY)

JTee

(READ/ WRITE)

BUF

CSRI

mswmm?g"

(READ mcm ]:gu-::wwmm

(READ / WRITE)

15
DROUT

REQUEST A | INTENBB

REQUEST 8

DATA OUT

(READ/WRITE)

15
DRINBUF

DATA IN

(READ ONLY)

Figure 5-6

DRVI11 Word Formats

5-7

CP-1746

Table 5-2
Word

Bit(s)

DRCSR

Word Formats
Function

REQUEST B — This bit is under control of the user’s

device and may be used to initiate an interrupt sequence or to generate a flag that may be tested by the
program.

When used as an interrupt request, it is asserted by
the external device and initiates an interrupt provided

the INT ENB B bit (bit 05) is also set. When used as a
flag, this bit can be read by the program to monitor external device status.
When the maintenance cable is used, the state of this

bit is dependent
on the state
of CSR1 (bit 01). This
permits checking interface operation by loading a 0 or

1 into CSR1 and then verifying that REQUEST Bis

the same value.
Read-only bit. Cleared by INIT when in maintenance
mode.

14-08

Not used. Read as 0.

REQUEST A — Performs the same function as RE-

QUEST B (bit 15) except that an interruptis generated
onlyif INT ENB A (bit 06)is also set.
When the maintenance cableis used, the state of RE-

QUEST A is identical to that of CSRO (bit 00).
Read-only bxt Cleared by INIT whenin maintenance
mode.
INT ENB A — Interrupt enable bit. When set, allows

an interrupt request to be generated, provided REQUEST A (bit07) becomes set.
Can be loaded or read by the program (read/write

bit). Cleared by BINIT.

04-02

- INT ENB B — Interrupt enable bit. When

set, allows
an interrupt sequence to be initiated, provided REQUEST B (bit 15) becomes set.

Notused. Read asO.

Can be loaded or read by the program (read/write
bit). Cleared by INIT.

5-8

Table 5-2

Word Formats (Cont)

Word

Bit(s)

Function

DRCSR

" CSR1 — This bit can be loaded or read (under pro-

gram control) and can be used for a user-defined command to the device (appears only on Connector No. 1).

When the maintenancecable isused, setting or clearing

| this bit causes an identical state in bit 15 (REQUEST
| B). This permits checking operation of bit 15 which
cannot be loaded by the program.

Can be loaded or read by the program (read/write
bit). Cleared by INIT.

CSRO — Performs the same functions as CSR1 (bit 01)
but appears only on Connector No. 2.

When the maintenance cable is used, the state of this
of bit 07 (REQUEST A).
bit controls the state
Read/write bit. Cleared by INIT.

DROUTBUF

15-00

Output Data Buffer - Contains a full 16-bit word or
one or two 8-bit bytes: High Byte = 15-8; Low Byte
= 7-0.

Loading is accomplished under a program-controlled
DATO or DATOB bus cycle. It can be read under a
program-controlled DATI cycle.

DRINBUF

15-00

Input Data Buffer — Contains a full 16-bit word or
one or two 8-bit bytes. The entire 16-bit word is read
under a program-controlled DATI bus cycle.

Sdata=1>

DRINBUF

{data=1)
LY

CINOD: IN15 ) are set /reset by the

{data=0)> ,

user, the daota must remain stoble until
trailing edge of DATA TRANSMITTED

‘s\” —— e

{data=@)

DATA TRANSMITTED
i

Pulsed by DRV
11 when the
11703 reads dato from the DRV

READ DATA FROM BUFFER

TF?ML!NG EDGE

REQUEST B

Set by user when rmdy to transmit new

WAIT FOR A RESPONSE TO

data to the 11 /03
; reset by user upon
trailing edge of DATA TRANSMITTED

"THE INTERRUPT REQUEST

DRCSR

<{bit 5> interrupt Enable B

Set by user to allow interrupt-driven

data transfer.

]
I

DRCSR

|
|

< bit I5)Request B flag

Indicates state of REQUEST A line.

i11-4588

{data=1>

DROUTBUF

T e
ey

CNRR

WERORS

<OUTOD: OUT 15) are set/reset
by the DRV
11 under control of
the 11/03

{data=1)

|
|
I

NEW DATA READY

2300ns
|
|
|
|

Pulsed by DRVI1 wh&nkthe

11/ 03 writes data to the DRV
{1

f
WRITE DATA TO BUFFER
—

-wmfm.me EDGE, DATA STABLE

REQUEST A

Set by user when ready for new data
from 11/03,; reset by user upon
trailing

edge of NEW DATA READY

WAIT FOR A RESPONSE TO

THE INTERRUPT REQUEST

< bit 6> Interrupt Enable A
Set by user to allow interrupt-driven
data transfer.

DRCSR

]

;

DRCSR

< bit 7> Request A flag

Indicates state of REQUEST A line.
11-4589

Figure 5-7

DRVI11 Interface Signal Sequence

5-10

CHAPTER 6

ADV11-A, KWV11-A, AAV11-A, and DRV11 MAINTENANCE
6.1

MAINTENANCE PHILOSOPHY

Digital logic circuitry in the ADV11-A, KWV11-A, AAV11-A, and DRVI11 is to be repaired in the
normal manner. Analog circuitry, however, is to be repaired only at the factory. If any analog failures
occur in the field, modules are to be board-swapped and returned to the factory for repair. Installations performed by DEC include installation of DEC-supplied equipment only. The customer is
responsible for wiring from his equipment to the H322 Distribution Panel or to the end of the DEC-

supplied cable.

6.2 ADV11-A ANALOG-TO-DIGITAL CONVERTER

6.2.1 Installation

6.2.1.1 Location - The ADV1I-A is a single-module option which interfaces to an LSI-11 or PDP11/03 through one of the quad locations in the LSI-11 backplane or in an expander box. Within the
constraints imposed by the LSI-11 bus structure (refer to the LSI-11, Microcomputer Handbook - EB06583 76 09/53) the unit may be mounted in any available location and will operate within specifications, regardless of proximity to the processor, memory, or other DEC options. Where circumstances
ce be improved beyond specification levels by installing the
permit, however, analog performanmay
or other noise-producing options. Note that priority
modules,
memory
processor,
the
unit away from
exist in the backplane between the processor and
locations
unstrapped
empty
no
that
transfer requires
any device that communicates with it.

6.2.1.2 Address and Vector Selection - Select and set CSR and Vector addresses as indicated in Paragraph 2.4.3.4. Note that where more than one ADV11-A is involved, CSR addresses must be four
locations apart (e.g., 170400, 170404, 170410, etc.). Vector addresses must be 10 locations apart (e.g.,

000400, 000410, 000420, etc.). Remember to reinstall any covers removed from switch packs S1 and S2.

6.2.1.3 Board Insertion - Select a quad location, and making sure that the keyed edge connector
matches the physical configuration of the terminal block, apply firm pressure alternately to the extracin the connector.
tor handles near the opposite corners of the board until it is squarely and fully seated

6.2.1.4 Test Connector - Do not insert /O cables into the Berg connector at this point. Instead,
insert the 7012894 test connector, which establishes the conditions required by the ADVII
Wraparound Test - that is, all channel inputs are grounded except 1, 2, 3, and 17, with internallygenerated +4.5 V signal on channel 1, -4.5 V signal on channel 2, ramp signal on channel 3, and
|

provision for external reference voltage on channel 17.

6.2.1.5 Shields - Install the 1700021-02 electromagnetic shields on both sides of the ADVI11-A.
Shields are insulated on both sides and physically separate the ADV11-A from adjacent modules but
|

are not electrically connected to the system.

6-1

6.2.1.6

Acceptance - Conduct an acceptance test as specified in A-SP-ADVI1I1A.

6.2.1.7

Final Connections

Cables
Remove the 7012894 test connector and install the BCO8R cable (ADV11-A to H322 Distribution
Panel) or the BC04Z cable (ADV11-A to user devices) in the ADV11-A Berg connector. Connect
BCO8R at both ends so that the stamped labels on the female cable ends match the embossed labels on
the male connectors - A/B to A/B, UU/VV to UU/VV. This normally means that any *this side up”
labels face away from the board on which the male connector is mounted.
NOTE
The BCOSR cable is symmetrically wired but for several reasons is unsymmetrically labeled. That is,
~wires identified as A and B on one end are identified
as UU and VV on the other end.
|
|
|

To simplify system relationships, the H322 PC

board compensates for this inversion on the PC

board that distributes Berg connector signals to front
panel screw terminals. For this reason, the user can
connect both ends of the BCO8R according to the
labels, A/B to A/B and UU/VV to UU/VV. So connected, signals from the ADV11-A will properly
appear at front panel terminals which have been
labeled according to the instructions on the ADV11A decal sheet. Each BC04Z cable from an ADV11-A
may be terminated in a female 25-pin connector such
~as a DB2SS type (DEC 12-09326-00) socket. The
user may assign the signal and ground lines from the
BCO04Z to specific connector pins. User apparatus
may be connected to the socket by means of a male
25-pin connector such as a DB25P type plug (DEC
12-05886-00).

If KWVI11-A is present, connect Faston terminals, as described in Paragraph 2.4.3.2.
Manual Voltage Control
)
|
|
|
Applications which require variable dc voltages to be applied to one or more channels of the ADV11A can be implemented by the circuit illustrated in Figure 6-1. Note that the H323-B Potentiometer Box
may not be used with the ADV11-A.
|
|
6.2.2 ADV11-A Circuitry
~
|
|
,
The digital interface and control logic of the ADV11-A conforms in general to standard DEC practices
and should be understandable to qualified technicians who have access to ADV11-A print sets and are

familiar with overall ADV11-A functions as described in Chapter 2. Since the analog power supply

and the A/D conversion sections involve some nonstandard circuits, they are discussed below.

6.2.2.1

ADVI11-A Analog Power Supply

General
|
|
'
e
LR
1HN
|
|
- The £15 V power for the analog circuits is derived from a dc-dc converter which consists of three basic
sections: a 12 V power switch, positive and negative voltage doubler diode-capacitor banks, and a dual
tracking voltage regulator. Output jumpers (W1 and W2) are provided to permit removing the load for
troubleshooting purposes.
6-2

a—

; 3

“': S

Q“‘:Q

o
x
———

—
UA

5K S« A/D input

-_—
9V
(MINIMUM) 7

<10
A/D input

.......L.

Vg~

1o A/D input

r—“wwmw*mq&

jov B

%
Fi

IN759A

(MINIMUM)

)

\“:

%fi*‘_-“““”“

Ve+

‘sf‘s

b - 33
b9
k-

\
[

[

mmwmmmmu‘-mm

CH. RET.

:
NOTE

Value of Rin kilohms can be calculated as follows:

2.5(N+2)

(1)

Where N = Number of channel

pots.

Current drain from battery in milliomps when R is
selected with equation (1) can be calculated as
follows:

Ipor= 2.5 (N +2) mA

(2)
11-4487

Figure 6-1

Battery-Operated Potentiometer Box for ADV11-A A/D Converter

‘J

POSITIVE

DOUBLER

SW A

VOLTAGE

‘

+ 15V
Wi

DUAL

TP3

VOLTAGE

REGULATOR

Figure 6-2

|
1

NecaTIVE
VOLTAGE

DpousLER

—

TP2

~ 15V

Analog Power Supply Block Diagram

Power Switch

Transistors Q15 and Q16 constitute the output stage of the 12 V power switch and provide a0 V to
+12 V switching signal, which is derived from the SW A and SW B signals, and which drives the
voltage doubler diode-capacitor banks. Since saturated transistor switches turn on faster than they
turn off, an idle is included (see Figure 6-3) to ensure that Q15 and Q16 are never on at the same time.
Voltage Doublers

The basic voltage doubler consists of a charge transfer stage (D and C, in Figure 6-4) and a charge
storage stage (Dp and Cp in Figure 6-3). When the power switch output is at 0 V, C4 charges to Vpy V, D, is reverse-biased and charge is
Vpa (+11.3 V). When the power switch output goes to +12

tranferred from C, to Cg. The power switch output then returns to 0 V, reverse-biasing Dy and
recharging C5 - D. The voltage on Cg builds up to approximately +12 V - Vp, +12 V - Vpp.
6-3

swat_‘

+12V '—‘—'—'"'l—_

POWER

L___,

SWITCH
OUTPUT

’l

wai

MfifiWmlUL

CLOCK H

|DLE-TIME

t> = SWITCH ON TIME
11-4479

Figure 6-3

DC-DC Converter Signals

SWITCH
- QUTPUT

+12V

[_]

‘

> Vout
T~ Cpg

)

hY|
s

POWER

VinE F12V

"1-4480

‘s Figure 6-4

Basic Positive Voltage Doubler

The negative voltage doubler operates in a similarvmannér and consists of two basic doubler circuits

cascade with an additional input negative voltage generating stage (D26 and C47).

Dual Voltage Regulator
The dual voltage regulator comprises an LM325N (E50) tracking regulator and power
boosters (Q17
and Q18). Output current limit sensing is provided by R60 and R61. This stage regulates
the outputs
from the doubler circuits to provide the £ 15 V of analog power required by the various
analog circuits.
-

6.2.2.2 ADVI11-A A/D Conversion Circuit - The ADV11-A A/D converter
circuit utilizes a patented
auto-zeroing, successive approximation technique. The basic components of this
circuit are illustrated

in Figure 6-5.

Analog Multiplexer
The analog multiplexer consists of two 8-channel, single-ended multiplexer ICs (E47 and
E48) whose
- outputs are connected together, thus forming a 16-channel multiplex
er. During sample, when no conversion is in process, the addressed multiplexer channel is on. During hold, two conditions are pos-

sible. If single-ended (SE) mode is picked, all channels of the multiplexer are off and the auto-zero

switch is on. If SE mode is not picked, the negative side of the selected quasi-diff

selected.

6-4

;

erential pair is

JI-INPUTS l

)

+ Esn

16 -CHANNEL

ANALOG
MUX

NODE

SAMPLE -AND-HOLD
.

12-BIT
FEESEACK

, /

anzc —=Q)

‘5 FEEDBACK

AUTO-ZERO

“switch

PREAMPLIFIER

\Y%

'Q@

;

—ead)

'FEEDBACK
SWITCH

SIGNAL

HOLD

8-BIT
VERNIER
D/A

DATA

SUCCESSIVE

APPROXIMATION

BUFFER

(SAR)

COMPARATOR

H-4481

Figure 6-5

ADVI11-A A/D Conversion Circuit Block Diagram

Auto-Zero

During sample, the feedback signal switch (QS5, Q6, Q8, Q9, Q10, and Q11) connects the output of the
feedback preamplifier (Q2 - Q4) to the input of the sample-and-hold (Q13, E51, C67), thus completing
the amplifier feedback path and allowing the sample-and-hold to track the analog input (see Figure 66).

Eos
3

‘

NODE

.
+

FEEDBACK D/A

()fiasa
d

VERNIER D/A

% PREAMP, SIGNAL SWITCH

AND SAMPLE-AND-HOLD

Figure 6-6

A/D During Sample

6-5

Summing currents into the 3 node:
I, =

+E. ., - E
OS1~
~0S2

E.,

-E
“SH ~ ~0S2

(1)

Eps; is the offset of the input buffer amplifier (E49) and Epg, is the offset of the feedback
preamplifier.
|
When a conversion is initiated, the feedback signal switch disconnects the output of the feedback
preamplifier from the input of the sample-and-hold, thus storing the signal, and connects the preamplifier output to the comparator (Q7 and Q12) input. Next, the A/D input, E;, is either switched to
the negative channel or is grounded through the auto-zero switch, E44, depending upon whether or not
single-ended operation was selected.
~

At the completion of the conversion, the 3~ node is ideally equal to Eqg, (see Figure 6-7).

Eos1

/\ +
_/

AAA,
Rp

NODE

It;

FEEDBACK D/A

COMP

IV‘

VERNIER D/A

This block comprises the preamplifier,
the signal switch,and the sample
-~ and - hold.
11 -4483

Figure 6-7

A /D During Conversion

Again summing currents into the }_ node:
E."+E
'~ E
"
E
|
0Sl1
082 +
SH
[.'=
D

082 - Iv ’

()

Subtracting equation (2) from equation (1):

,ID“ID’ ~.=.:..-E1, E, -(Iy-1,) +E081”Eo:51 mEosszosz + Esy - Egy
_

R.//R,

)
3

Note that since the offset due to the input buffer is the same in both cases,
Eos) - Eos
\D

is equal to zero. Eqggy - Eosy' is controlled by R15 by forcing an offset shift in the feedback preamplifier and is used to null the offset caused by the sample-and-hold pedestal (Esy - Egy’). Notealso

that the conversion is not dependant upon the magnitude of Eqggy, but upon the forced shift.

Therefore:

- (y-1yY

-Ip'=

and:

| (4)

ID - ID
A /D Conversion

The 12-bit feedback D/A (E46) is initialized to 4000s.
Ip =1/21gge =Iigp

During conversion, each bit of the feedback D/A is interrogated in sequence by the SAR (E39),
. starting with the MSB. At the end of each interrogation interval, the decision of the comparator to
accept or reject that bit is clocked into the SAR where this decision is held. A positive voltage on the 3 _
node will cause the comparator to reject a bit. Because of the overall negative feedback, this process
will cause the 3 node to work its way toward null (Figure 6-8). After the LSB interrogation, the
|

contents of the SAR are transferred to the Data Buffer register.

CLOCK

l t ‘

f l

+CLAMP Jm
3

REJECT

prem——
|

~ CLAMP

i1-4484

Figure 6-8

> Node During Conversion

6-7

Since
Ip min =0

and

Ip max = Igggr - I g,
equations (4) and (5) permit voltage/current conversions to be derived as illustrated in Table 6-1.

Table 6-1
L

ADV11-A Voltage/Current/Bit Relationships

Code

-1’

E,-E/’

77717

1/2

1/2 (Ipgg
)

3777

-1

-E; g

Tpsr=Tp

0000

~1/2 (Ipgg)

~1/2 (Epgg )

Ipgg =11 5p)

1/2 (Eggp-Egp)

6.2.2.3 The Vernier DAC - The Vernier DAC is a digital-to-analog converter packaged in a single
chip serving to provide programmable small increment offsets to the summing node of the A/D con-

verter. It has been included in the ADVI11-A circuit primarily to facilitate automatic testing of the
module and is used
by the diagnostic routines in the measurement of noise, offset error, and interchannel settling error. The Vernier DAC is controlled through bits 07:00 of the Data Buffer register
(write-only), accepting 8-bit offset binary code to produce positive and negative full scale offsets of 2.5
A/D LSBs.
~
|
,
|

6.2.3 ADV11-A Performance Test (MAINDEC-11-DVADA-A)
|
|
|
This diagnostic package permits complete testing of all functional aspects of the ADV11-A.
It is
divided into four major routines which are described below. Refer to diagnostic listing MAINDEC11DVADA-A for run instructions.
1.

Wraparound Routine - consists of four subtests which can be run individuall
y or
consecutively:
a.

Analog Test - checks all channels and their outputs to ascertain whether or not multiplexing and gross conversion functions are working.

Noise Test - determines whether or not the amount and distribution of short-term
noise within the A/D converter is within limits.

Interchannel Settling Test - Determines whether or not the A/D converter can recover
from measurements at opposite extremes within specified times (switches alternately
between channels 1 and 2 - i.e., between +4.5 V and -4.5 V).

Differential Linearity and Relative Accuracy Test - makes multiple randomized measurements of ramp signal
on channel 2 to determine, within 0.01 LSB, the width of the
voltage band corresponding to each of the 4094 finite width states.

Calibration Routine - works interactively with operator to facilitate precise calibration
of
A/D. Requires precision voltage source.
|

6-8

\_/

START

(>g

RUN LOGIC

PASS

AROUND

DOM

€ )

LOGIC

B \Mm/ )

ANALOG

(

AND REPAIR

ROUTINE

ISOLATE

PROBLEM

LOGIC

CHECK +8V
& +12V

POWER SUPPLY

ADJUST P.S.

FOR +5V OR
+12v

TROUBLESHOOT
AND REPAIR

mm..m; PS.

*Calibration routine can be run at
this point if precision voltage

source {(EDC VS-11N or equivalent)
is available.
11-4485

- Figure 6-9

ADV11-A Troubleshooting Procedure

6-9

Print Values routine - works interactively with operator to execute, and if desired, print out
results of conversions on selected channels.

Logic Test Routine - consists of 23 subtests that run sequentially without operator intervention and check status register read/write operation, initialize conditions, A/D done flag
setting and clearing, error flag setting, interrupt functions, etc.

6.2.4 Maintenance
|
In general, both routine maintenance and specific troubleshooting efforts will follow the flow defined
in Figure 6-9. Preventive maintenance will consist of removing airborne dust accumulations, checking
the power supply levels whenever new devices are added to the system, and running diagnostics whenever performance confirmation is desired.

6.2.5 Calibration (Requires Precision Voltage Source - EDC VS-11N or Equivalent)
With test connector installed in ADV11-A Berg socket, connect the floating reference voltage to the
two clip-terminated leads (channel 17). Then, run the Calibration Routine and follow the step-by-step
instructions it issues. The program will specify reference voltage settings and indicate when offset and
gain potentiometers (identified in Figure 2-6) should be adjusted.

6.3

KWVI11-A REAL TIME CLOCK

6.3.1

Installation

6.3.1.1
Location - The KWVI11-A is a single-module option which interfaces to an LSI-11 through
one of the quad locations
in the LSI-11 backplane or in an expander box. Within the constraints
imposed by the LSI-11 bus structure (refer to the Microcomputer Handbook - EB-06583 76 09/53), the
unit may be mounted in any available location. Note that LSI-11 priority transfer requires that no
empty unstrapped locations exist between the processor and the last device connected to the LSI-11

bus.

6.3.1.2 Address and Vector Selection - Select and set CSR and Vector Addresses
as indicated in
Paragraphs 3.4.3.1 and 3.4.3.2. Note that where more than one KWV11A is connected to the same
bus, CSR addresses must be four locations apart (e.g., 170420, 170424, 170430, etc.).
Vector addresses
for multiple KWV11-As must be 103 locations apart (e.g., 000440, 000450, 000460,
etc.). Remember to
reinstall any covers on switch packs S1 and S3.
6.3.1.3 Board Insertion - Select a quad location, and making sure that the KWV11-A board is oriented so that the keyed edge connector matches the physical configuration of the terminal block, apply
firm pressure alternately to the extractor handles near the opposite corners of the board until
it is
squarely and fully seated in the connector.

6.3.1.4

Test Connections - Do not connect user equipment to Berg connector J1 at this time. Diag-

nostic I/0O signal tests will require jumpers between specified pins on J1.
6.3.1.5

Acceptance - Conduct an acceptance test as specified in A-SP-KWV11-A-3.

6.3.2 Final Connections
|
|
Install FAST ON connectors between CLK/ST1 tabs and ADV11-A tabs as required. Install the
BCO8R cable (KWV11-A to H322 Distribution Panel) or BC04Z cable (KWV11-A to user devices)
between the Berg connector (J1) and the appropriate terminus. Connect the BCOSR at both ends so
that the stamped labels on the female cable ends match the embossed labels on the male connectors A/Bto A/B, UU/VV to UU/VV. This normally means that any “this side up” labels face away from
the board on which the male connector is mounted. (See Note in Paragraph 6.2.1.7.)

6-10

6.3.3

KWYV11-A Circuitry

The digital logic of the KWV11-A conforms in general to standard DEC practices and should be
understandable to qualified technicians who have access to KWVI11-A print sets and are familiar with
KWV11-A functions as described in Chapter 3.

6.3.4

KWV11-A Diagnostic (MAINDEC-11-DVKWA-A-D)

6.3.5

Maintenance

The KWV11-A diagnostic is divided into two main routines, the first designed to test logic functions
on up to four KWV11-A modules, the second to test selected module I/O functions, ST1, ST2, and
clock overflow. Refer to diagnostic listing MAINDEC-11-DVKWA-A-D for run instructions.
-

Preventive maintenance consists of removing airborne dust accumulations, checking that power supply levels remain within specifications whenever new devices are added to a system, and running
|
diagnostics whenever performance confirmation is desired.

6.4 AAV11-A DIGITAL-TO-ANALOG CONVERTER
6.4.1

Installation

6.4.1.1 Location - The AAV11-A is a single-module option which interfaces to an LSI-11 or PDP11/03 through one of the quad locations in the LSI-11 backplane or in an expander box. Within the
constraints imposed by the LSI-11 bus structure (refer to the Microcomputer Handbook - EB-06583 76
09/53) the unit may be mounted in any available location and will operate within specifications,
regardless of proximity to the processor, memory, or other DEC options. Where circumstances permit,
however, analog performance may be improved beyond specification levels by installing the unit away
from the processor, memory modules, or other noise-producing options. Note that priority transfer
requires that no empty unstrapped locations exist in the backplane between the processor and any
device that communicates with it.

6.4.1.2 Address Selection - Select and set address as indicated in Paragraph 4.4.2. Note that the least
significant three bits of the address word are reserved for software addressing of the four digital-toanalog converters (DACs) and are therefore not selectable on the switch pack. For this reason, if
several AAV11-As are installed on a system, they must be assigned addresses that are 10g locations
apart.

6.4.1.3 Board Insertion — Select a quad location on the connector block, and making sure that the
AAV11-A board is oriented so that the keyed edge connector matches the physical configuration of the
connector block, apply firm pressure alternately to the extractor handles near the opposite corners of
the board until it is squarely and fully seated in the connector block.

6.4.1.4 Test Connectors — If AAV11-A signals are to be routed to the H322 Distribution Panel,
connection may be made to that unit at this time (see Paragraph 6.4.2). Otherwise, leave the Berg
connector empty to allow for monitoring AAV11-A output signals in the next step.

6.4.1.5 Acceptance Test - Conduct an acceptance test as described in the AAV11-A Manufacturing

“and Field Acceptance Procedure (A-SP-AAV11-A-3).
6.4.2

Final Connections

Install the BCOSR cable (AAV11-A to H322 Distribution Panel) or BCO4Z cable (AAV11-A to user
devices) between Berg connector (J1) and the appropriate terminus. Connect BCO8R at both ends so
that the stamped labels on the female connectors match the embossed labels on the male connectors -

A/Bto A/B, UU/VV to UU/VV. This normally means that any “this side up” labels face away from
the board on which the male connector is mounted. (See Note in Paragraph 6.2.1.7.)

6-11

6.4.3 Mode/Level Selection
o
As shipped from the factory, the AAV11-A is set for bipolar operatio
n between -5.12 V and +5.12 V.
Unipolar operation and operation in other voltage ranges can be achieved
by proper changes in
mode/level jumpers (illustrated in Figure 4-2). Table 6-2 indicates
jumper configurations for all bipolar voltage ranges; Table 6-3 indicates those for all unipolar ranges. Note
that each of the four DACs
on any given AAV11-A may be set for a different mode/level condition
. Note also that any change
from the factory settings may require recalibration of the DAC involved
(see Paragraph 6.4.7).

Table 6-2

Jumper Configurations for Bipolar Operation

+2.56 V
DAC
1
W3

+5.12V

OUT
IN
IN

W5
W6

DAC2

£10.24V

OUT

OUT
OUT
IN

"IN
OUT
IN

OUT

w9
W10

IN
IN

OUT
IN

DAC3
Wil
W12
W13
W14

|
IN
OUT
IN
"IN

IN
OUT
OUT
IN

OUT
IN
OUT
IN

|
OUT

DAC4
wis
W16
W17
W18

OUT

|
OUT
IN
IN

OUT
OUT
IN

6.4.4 AAV11-A Circuitry

IN
OUT
IN

The digital interface and control logic of the AAV11-A confor
ms in general to standard DEC practices
and should be understandable to qualified technicians who have
access to AAV11-A print sets and are
familiar with overall AAV11-A functions as described in Chapte
r 4. The analog power supply and the
digital-to-analog circuitry, however, make use of techniques and
components with which DEC technicians may not be familiar. Since the analog power supply and
the D/A conversion sections involve

some non-standard circuits, they are discussed below.

6.4.4.1

AAVI11-A Analog Power Supply

General ’(see Figure 6-’1) Ly

NI -

The
15 V power for the analog circuits is derived from a dc-dc converte
r which consists of three basic
sections: a 12 V power switch, positive and negative voltage doubler
diode-capacitor banks, and a dual

tracking voltage regulator.

6-12

- Table 6-3 Jumper Configurations for Uni polar Operation
OV-+512V | 0V-+1024V
IN

OouT
OUuT
OuT

OouT

IN
OuUT

OUT
OuUT
OUT

OouT
OUT

OouT

-~ OuUT

W17
T

OouT

Table 6-4 AAV11-A Input Code/Output Voltage Relationship
Input Code

| -Fs

7777

4FS-1/2LSB |

Bipolar

Unipolar

0000
4000

Power Switch

1/2 FS

+FS-1/2LSB

+12
Transistors Q2 and Q3 constitute the output stage of the 12 V power switch and providea 0 Vto
voltage
the
drives
which
and
signals,
B
SW
and
A
SW
the
from
V switching signal, which is derived
doubler diode-capacitor banks. Since saturated transistor switches turn on faster than they turn off, an
idle time is included (see Figure 6-2) to ensure that Q2 and Q3 are never on at the same time.

of a charge transfer stage (D and C, in Figure 6-3) and a charge
The basic voltage doubler consists

power switch output is at 0 V, C, charges to VN storage stage (Dg and Cp in Figure 6-3). When the
output goes to + 12 V, D, is reverse-biased and
switch
power
the
When
D,.
through
V)
Vpa (+11.3
switch output then returns to 0 V, reversepower
The
Dy.
is transferred from C, to Cp through
charge
ately +12 V on Cp builds up to approxim
biasing Dp and recharging C, through D4. The voltage

Vpa +12V - Vpp (+22 V).

6-13

The negative voltage doubler operates in a similar manner and consists of two basic doubler circuits
in
cascade with an additional input negative voltage generating stage (D21/22 and C42/43).

Dual Voltage Regulator
|
The dual voltage regulator comprises an LM325N (E38) tracking regulator and power boosters
(Q4
and QS5). Output current limit sensing is provided by R57 and R58. This stage regulates the outputs
from the doubler circuits to provide the & 15V of analog power required by the various analog circuits.
6.4.4.2 Digital-to-Analog Circuits - The analog sections of the AAV11-A consist of four 12-bit
D/A
converters (each contained on one 24-pin chip), four 2505 operational amplifiers, and a +10 V precision reference source.

Each D/A converter (DAC) contains the necesary circuits to generate a 0-2 mA output current and to
modify that current as a function of the 12 input data bits. A 1-LSB change in the data register
‘corresponds to a change of 1 part in 4096 of the full scale output, approximately 1 /2 uA.
The output of the DAC is fed into a 2505 operational amplifier which converts the drive current
into a
voltage output. The feedback from the output of the amplifier is passed through the selected feedback
resistors. The interconnections between these resistors, determined by the mode/range straps
illustrated in Figure 4-2, determine the operating mode (unipolar or bipolar) and voltage range of the
DAC
in question.

Gain and offset of each DAC are controlled through the externally-adjustable potentiometers
(see
Figure 4-2).
6.4.5 AAVI11-A Diagnostic Test MAINDEC-11-DVAAA-A)
The AAVI11-A Diagnostic Test is divided into four routines. Each is briefly described
below.
I.

Logic Tests (starting address: 200) - exercises and monitors behavior of interface and control logic of all DACs on all AAV11-As in a system. Checks that DAC holding registers can
be loaded, cleared, and modified without error.

Ramp Loop (starting address: 204) - reiteratively increments the holding register for
each
DAC to produce full-scale ramp voltages successively at the output of each DAC. Permits
confirmation by oscilloscope of DAC linearity, settling time, and channel isolation.

Static Calibration Loop (starting address: 210) - permits operator to input control data
to
all DACs and monitor resulting output conditions. Run with a precision DVM as output
monitor, the Static Calibration Loop permits calibration of gain and offset of each DAC,

Dynamic Calibration Loop (starting address: 214) - reiteratively switches
each DAC

between maximum and minimum output conditions. Facilitates checking DAC response
‘and recovery characteristics as well as amplifier slew rates.
6.4.6 Maintenance
~
In general, both routine maintenance and specific troubleshooting efforts will follow the flow defined
in Figure 6-10. Since the diagnostic program has no way of evaluating AAV11-A analog performance,
pass or failure of all but the logic tests depends on the judgment
of the operator. Refer to the AAV11-

‘A Manufacturing and Field Acceptance Procedure (A-SP-AAV1 1-A-3) for applicable criteria.

Preventive maintenance consists of removing airborne dust accumulations, checking
that power supply levels remain within specifications whenever new devices are added to
a system, and running
diagnositics whenever performance confirmation is desired.
|

6-14

TESTS

TROUBLESHOOT

; 4

AND REPAIR
LOGIC

CHECK +5V

+12v

rowersueeLy |

+BV/+12V

YES

P.S. OK

READJUST

P.S. FOR +5V

OR +12V

CHECK ANALOG
POWER SUPPLY

—

RUN STATIC
CALIBRATION
Loor

I
PASS*

YES

RUN DYNAMIC

CALIBRATION
LOOP

l CALIBRATE

TROUBLESHOOT
AND REPAIR
ANALOG PS.

=
*See AAV11-A Field Acceptance
Procedure for applicable criteria.

Figure 6-10 AAV11-A Troubleshooting Procedure

11-4486

6.4.7

Calibration
|
Prepare the system to permit access to signal line(s)
and calibration potentiometers of DAC(s) to be
calibrated. Connect DVM of appropriate precisi
on (note that 1 LSB on +2.56 V bipolar or 0-5.1
2 V
unipolar = 1.25 mV) to output of DAC to be measur
ed. Float the DVM as illustrated in Figure 6-11.
Take care to connect DVM common lead to
HQ ground associated with the DAC in question. Then
proceed as follows:
l.

Load DAC holding register with 0000.

Adjust offset potentiometer (see Figure 4-2) for DVM reading
mode/level condition (see Table 4-1).

appropriate to selected

Load DAC holding register with 7777.
Adjust gain potentiometer for DVM reading appropriate to
selected mode/level condition
(see Table 4-1).
|
5.

Load DAC holding register with 4000.

Check DVM for reading appropriate to selected mode/l

evel condition (see Table 4-1).

Step 6 should produce a reading accurate to 1-1/2 LSB.

1SV POWER

]

DVM

+ I

-l

gfi"

AAV11-A

DAC RET
B!
-452%

Figure 6-11

6.5

Floating the DVM

DRVI11 PARALLEL LINE INTERFACE

Refer to the Microcomputer Handbook ( EB-06583 76 09/53).

6-16

Absolute Accuracy

The analog error, expressed as a percentage of full scale, referenced to the National Bureau of Standards volt.
~

Acquisition Time

The time duration between the giving of the sample command and the point when the output remains within a
«

specified error band around the input value.

Aperture Delay Time

The time elapsed between the hold command and the point at which the sampling switch is completely open.
Aperture Uncertainty

The variation in aperture delay time for a particular sample-and-hold.
Common Mode Rejection (CMR)

The ability of a differential amplifier to reject noise common to both inputs. Common mode rejection is
expressed as a ratio, the Common Mode Rejection Ratio (CMRR). A differential amplifier with a CMRR of 80
dB (10,000:1) would have an output voltage of 0.5 mV if both inputs were 5 V (5 V/80 dB).

| ,

Crosstalk

TREET

The amount of signal coupled to the output as a percentage of input signal applied to all off channels.
Differential Inputs (True)

;

Two external signals applied to the input circuitry of an A/D system whereby the first is subtracted from the
second. The difference is applied to the A/D system. This is generally used with twisted pair wiring to reduce
noise pickup.
Example

V=V

V, = (VH- (V)
= [V, + V(1) noise] - [V, + V(3) noise]

= [Vi-V,]+ [V(x)miw - V(z)' noise] ’
For twisted pair wiring:

V“

V(, ) noise = V(,) noise
Vo=V, -V,

| Vyg)NOISE

o8 -1236

Differential Inputs ( Psuedo)
This method of inputting is similar to true differential inputting except that the negative input to

is common to the other inputs.

the A /D system

Differential Linearity
The maximum deviation of an actual stated width from its theoretical value for any code over the

full range of
the converter. A differential linearity of £1/2 LSB means that the width of each code over the range of
the
converteris | LSB +1/2 LSB. Missing codes in an A/D converter occur when the output code skips a digit.
This
happens when the differential linearity is worse than +1 LSB.

Drift

Drift is a function of the temperature coefficients of the components. It is the major contributor
to gain and

offset error.
Gain Error

The error, expressed as a percentage, by which the actual full scale range differs from the theoretical
range. This error is adjustable to zero.

full scale
~

Gain Temperature Coefficient
~
This is the amount of gain that changes with a change in temperature. This may be expressed

C/LSB at full scale. If an A/D has a gain temperature coefficient of 20° C/LSB at F.S., the A /D
will be off by 1 LSB at full scale if the temperature rises 20° C above 25° C.

in ppm/° C or °
converted value

Input Bias Current

The amount of current that flows into the selected A /D channel from the source.
Input Impedance (dc)

The resistance seen at the input to an A

/D system.

Linearity
|
~
|
|
Linearity is defined as the maximum deviation from a straight line drawn between the end points of

transfer function. Linearity may be expressed as a percentage of full scale or as a fraction of

the converter

an LSB.

Multiplexer
The multiplexer is a set of switches that permits analog data from different sources (channels)

the sample-and-hold (or A /D converter) individually.

Multiplexer Settling Time
The maximum time required to reach a specified error band around the input value

to be supplied to

when switching channels.

Offset Error

The error by which the transfer function fails to pass through the origin. This is usually adjustable

to zero.

Quantization Error
|
Quantization error is defined as the basic uncertainty associated with digitizing an analog

signal, due to the finite
resolution of an A/D converter. An ideal converter has a maximum quantization error of
+1 /2 LSB.

Quasi-Differential
A
Like true differential operation (see Differential Inputs) in that measurement is

|
made of the difference between

an input and a return line. Unlike true differential, however, in that measurem
ent is not made at one instant in
time, but rather throughout the variation of the conversion.
Relative A ccuracy
,
This is defined as the input to output error as a fraction of full scale with gain
Relative accuracy is dependent on linearity.

GLOSSARY-2

and offset errors adjusted to zero.

Resolution

The resolution of an A/D converter is defined as the smallest analog change that can be distinguished. Resolution is the analog value of the least significant bit.

Resolution =

Full scale

Least significant bit

For example, if a system requires a weight measurement range of 2540 1b, measured to the nearest 3 1b,
Resolution =

2540

= 847 code combinations

The closest standard A /D converter resolution available is 10-bits binary. A binary resolution of 10-bits selected.
The new resolution for this channel is recalculated for 10 bits.

1 LSB (least significant bit) = Full scale range _ 2_?,,?,9, =251b
Sample-and-Hold

to ensure that input voltage does not change during a conversion, a sample-and-hold is required. If the
In order
change during a conversion cycle is less than 1/2 LSB, then a sample-and-hold circuit is not required.
Example

Conversion Speed = 20 us
“Full Scale Input Range (FSR) = 10.24 V
Converter Resolution = 10 bits
LSB Value = .01 V/bit
1/2 LSB = 0.005 V

Maximum slew = 0.005 V/20 usec = 250 uV/usec =250 V /sec

(Rate required for no sample-and-hold)

fore,, = 1/2(FSR)sin wt

Woay =2 TP (BW)

then de/dt = (1/2)w (FSR) cos w t

~.\de/dt Imax =(1/2)w
., (FSR) = (BW) (FSR)
or 250 V/sec =n (BW) (FSR)
BW = 250 V/sec /m (10.24 V) =7.77 Hz

Slew Rate

The capability of the output of an analog circuit to change its voltage in a given period of time. If the slew rate is
7 V /usec, the analog circuit output will change seven volts in one usec.

Successive Approximation

A method that is used to transform the analog signal to a digital number.

ANALOG INPUT :D COMPARATOR

LOGIC

CONTROL

D/7A

CONVERTER
o

" A/D CONVERTED VALUE

A/D

VALUE
ca-1238

An analog signal is compared to a logic generated signal. The logic always supplies a half range signal initially.

For example, the full scale input to an A/D converter system is 10 V and the input to the system is 7 V.

Try*

New Logic Voltage

Is the Input

A/D

Greater Than

Buffer

New Voltage

Bits

Value

Decision

A/D

Yes

25V

Add +5=+5

5425V

Do nothing

1.25V

5+1.25V

Yes

625V

Add 1.25 =6.25

6.25+.625V

Yes

3125V

Add .625 =6.875

6.875+ .3125V

1011000

Do nothing

1011000

1000000

1000000
1010000

A5625V

6.875 +.1562 V

078125V

Do nothing

6.875 +.078125V

1011000

Yes

Add .078175

1011001

*This is a 7-bit

A/D

1011001 = 7 Vin 10 V full scale range.

°r
NO
NO No
|
TGvEsfves]
|
[ves
s

|_YES

4 -

3 -

08~-1239

GLOSSARY+4

Throughput Speed

The Nyquist sampling theorem states that a minimum of two samples per cycle are required to completely
recover continuous signals in a noiseless environment. In typical instrumentation systems noise does exist and
from 5-10 samples per cycle are required.

of the powerline
For applications with dc and very low frequency signals, sample rate is usually a sub-multiple

frequency to provide essentially infinite rejection of these frequencies.

The minimum sampling speed required is the number of samples per cycle multiplied by the highest frequency
component of the data. For time multiplexed systems, the speed requirement of the A/D converter is dependent
on system throughput speed. System conversion speed is determined from data bandwidth, the number of channels, and the sampling factor by:

System throughput = (N) (n) (B.W.) samples/second
n = number of channels

where N = number of samples/cycle (sampling factor)
B.W. = largest bandwidth of any channel
Example

Channel 1 bandwidth 100 Hz
Channel 2 bandwidth 200 Hz
Channel 3 bandwidth 250 Hz

throughput = 10 X 3 (250) = 7500 sample/second
N =10

n=3

Hz
BW = 250

The A/D throughput is comprised of the following:
Multiplexer settling time
Sample & Hold settling time
A /D conversion speed
A /D recovery time

Computer acquisition time (Software)

GLOSSARY-5

R R R
S

]

ADV11-A, KWV11-A, AAV11-A, DRV11 USER’S MANUAL

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