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Document:	AD11-K Analog to Digital Converter User Manual
Order Number:	EK-AD11K-OP
Revision:	002
Pages:	32
Original Filename:

OCR Text

AD11-K

analog to digital converter
user manual

dlifgliltiall

EK-AD11K-OP-002

AD11-K

analog to digital converter
user manual

digital equipment corporation - maynard, massachusetts

1st Edition, March 1976

1st Edition (Rev), October 1977

The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL
DEC
PDP
DECUS
UNIBUS

DECsystem-10

DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS

OMNIBUS
0S/8
RSTS
RSX
IAS

CONTENTS

CHAPTER 1

DESCRIPTION

1.1

GENERAL DESCRIPTION

1.2

FUNCTIONAL DESCRIPTION

1.3

A/D CONVERTER SPECIFICATIONS

1.4

PACKAGING

1.5

POWER REQUIREMENTS

1.6

UNIBUS LOADING

CHAPTER 2

USER INTERFACING

. . . . . .

e e e e e e e e e e e e e

e e e e e e s e e

. . . . . . . . . .

. . . .

e e e e

e e

. . . .

e e

CONNECTION

H322 DISTRIBUTION PANEL

2.3

SINGLE-ENDED AND PSEUDO-DIFFERENTIAL INPUTTING

2.4

SINGLE-ENDED ANALOG INPUTS
Floating Inputs

e e e e s e e e e s e

2.1

24.2

2.2

Grounded Inputs

e e e e

. . . . . . . e
e e e e,

. . . . . .

2.4.1

e e

e it i e,

e e e e e e e e e e e e e e e e e e e

. . . . . . . . . .

. . . . . . .

e e e

. . . . . . . . .

. . . . . . . . . . . .

. . ... ... ......
e

e s e e e e
e e e

e e

. . . . . .. . .. ...

e e e e e

2.5

TRUE DIFFERENTIAL INPUTTING

2.6

TWISTED PAIRINPUT

2.7

SHIELDED INPUT

2.8

INPUT SETTLING WITH HIGH SOURCE INPEDANCE

EXTERNAL STARTS

2.10

JUMPERS

. . . e
e e
e e

. . . . . . e
e

. . . . . . .

...

e e e e e e e e e e e e

e e e e e e e e e e e e e e e

. . . .. ... ... .......

. . . . . .

2.11

SWITCHES

2.12

OVERFLOW OR EXTERNAL START CONNECTION

CHAPTER 3

PROGRAMMING

e e e

e e e e

.. ... .. ... .. .......

3.1

3.2

PRIORITY LEVEL

. . . . . e
e

3.3

REGISTERS

o e

. . . o

3.3.1

Status Register

3.3.2

A/D Buffer Register

3.3.3
3.4

DAC Buffer

. . . . . . . . . .

. . ... ... ... . .. . ... ... ...,

. e

. . . . . . . .. . .

. . . . . . e
e

PROGRAMMING EXAMPLE

. . . . . . . .

. e

GLOSSARY OF A/D TERMS

ILLUSTRATIONS

Figure No.

Title

1-1

ADI11-K Block Diagram

1-2

Single-Ended Input

1-3

. . . . . . . . . .. .

. . . . . . . ..
e
Pseudo-Differential Input
. . . . . . .. ..

1-4

True Differential Input

2-1

H322 Distribution Panel

2-2

AD11-K Input Referenced to User’sGround

2-3

Floating AD11-K Input Signals

. . . . . . . . . . . .

. . . . . . . . . .. ... ..

. . . . . .. .. .. .. ... ... ......

. . . . . ... ... .. .. ... ... . .. .. .. ...

ILLUSTRATIONS (Cont)
Title

Figure No.

Page

2-4

AOO09 Module

. . . .

e e e e e e e e e e e e e e e e

2-5

Module Jumpers

. . . . . .

2-6

Tab Connections

. . . . . . . .t

3-1

A/D Status Register Format

. . . . . . . . . . . . .. ... ..

3-1

3-2

A/D Buffer Register Format

. . . . . . . . . . . . . . . ..

3-2

3-3

DAC Buffer Register Format

. . . . . . . .. .. ... ...

..o,

3-3

e e e e

e e e e e e e e e e e

e e

2-6

e e

2-7

2-9

TABLES

Title

Table No.
2-1

Channel Selection

2-2

Channel Pair Selection

2-3

AOO09 Jumper Descriptions

2-4

A009 Input Range Jumpers

Page

. .. .... S 2-3
. . . . . . . . . o

e e e e e e

e e e e e

e e

. . . . . . . .. ..o
. . . . . . . . .

2-5

Address Line Selection

. . . . . . . . .

2-6

Vector Line Selection

. . . . . . . . . L L

3-1

AD11-K Status Register Bit Descriptions

. .

e e

e e e e e e e e e e
e

2-5
2-8

2-8

e e e e e

e e e e e e e e e e e

AD11-K ANALOG TO DIGITAL CONVERTER
USER MANUAL

&
%

J
I3

MA-1749

AD11-K Module

CHAPTER 1
DESCRIPTION

1.1 GENERAL DESCRIPTION
The ADI11-K, Analog-to-Digital (A /D) Converter, enables the user to sample analog data at specified rates and
to store the equivalent digital value for subsequent processing. The basic subsystem consists of an input multiplexer (switch-selectable between 16-channel single-ended or 8-channel differential), sample-and-hold circuitry,
and a 12-bit A/D converter. By changing jumpers, the analog inputs can be made bipolar or unipolar. The inputs
over all ranges are over-voltage protected. The AD11-K has built-in self test circuitry when used in conjunction
with the G5036 wrap-around module. A £8 V ramp circuit and £2 V 8-bit D/A converter are used to test the

A /D converter and are also available for user use. A block diagram of the AD11-K is shown in Figure 1-1.
1.2

FUNCTIONAL DESCRIPTION

The ADI11-K is a 12-bit successive approximation converter where the data is right-justified in offset binary. It is
controlled by the A /D Status Register.
An A/D conversion may be initiated in any of three ways:

Under program control, on overflow from a real-

time clock, or on an external input. These methods give the system the flexibility to serve in most applications
requiring data acquisition.
The user can switch-select operation in single-ended or differential mode. In single-ended mode, up to 16 singleended (Figure 1-2) or pseudo-differential (Figure 1-3) channels of analog input can be selected. In true differen-

tial mode, up to eight differential channels of analog input can be selected (Figure 1-4). The input channel is
selected by the status register. Input voltage range can be changed from the standard setup of £5 Vto £5.12V,
+10V, £10.24 V, 0 to 10 V or 0 to 10.24 V by configuring jumpers on the module.
When a conversion is complete, a flag is set and, if the A/D interrupt is enabled, the processor will interrupt

(vector) to the proper subroutine for data manipulation. The user can run in the interrupt mode or wait to see the

A /D done flag.
The multichannel throughput rate is 50 kHz using a PDP-11/10 computer (start conversion to memory). Since
the converted value is held in a buffer register, a second conversion can be started before the results of the first
conversion are read, thus achieving high throughput.

The digital-to-analog converter (DAC) has no control logic, so software must provide the proper settling delay
(approximately 30 usec). The DAC is an 8-bit converter with an 8-bit buffer register. The D/A output range is
+2 V. Normally, the DAC is used for maintenance to test the A/D converter via the G5036 wrap-around
module; however, the output is made available for the user.

1-1

BUS
INTERRUPT

CLOCK START
TAB

BR-BG
INTR

A/D

BUFFER

+ CONTROL
INPUT CHAN (00:17)

DATA BUS

TAG

MULTIPLEXER

D(15:00)

STATUS
REGISTER

READ
STATUS

READ
BUFFER

LOAD
STATUS

ADDRESS

SELECT

LOAD

DC 70 DC

REFERENCE

CONVERTER

VOLTAGE

+5V

INPUT/OUTPUT CONNECTOR

EXT A/D START

BUFFER

DAC

BUFFER

DAC

[CONTROL

A(17:00)

Cc(1:0)
MSYN
SSYN

RAMP

GENERATOR

11-4118

Figure 1-1

ADI11-K Block Diagram

SWITCH POSITION

AD1-K

1= SINGLE

| cHaN 00

1= PSEUDO DIFFERENTIAL

J CHAN 02
lCHAN 04
CHAN 06

CHAN 10

INSTRUMENT

GROUNDED USER

L GROUND

INSTRUMENT

ENDED

2-5=TRUE DIFFERENTIAL
EVEN

MUX

CHAN 12

14
| cHAN

l CHAN 16

~.’

I CHAN Ot
l CHAN 03
CHAN

CHAN 07
FLOATING

CHAN 1f

USER

INSTRUMENT

> TWISTED PAl R

AAA

(OR)

0DD

MUX

Q4 ——

CHAN 13

CHAN 15
CHAN 17

IRETURN

| Ha srounp
|

ANALOG

COMPUTER
|

HIGH QUALITY

GROUND

.- ]
H-4111

Figure 1-2

Single-Ended Input

AD11-K
SWITCH POSITION
1= SINGLE ENDED

| cHaN 00

1= PSEUDO DIFFERENTIAL

2-5= TRUE DIFFERENTIAL

! CHAN 02

ICHAN 04

J CHAN 06
CHAN 10

EVEN

MUX

CHAN 12

14
| CHAN

I CHAN 16

]

> TWISTED PAI R
\ g

~u’

ICHAN o]
CHAN

CHAN 11

lpROUND

INSTRUMENT

CHAN 07
INSTRUMENT

GROUNDED USER

l CHAN 03
4

oDD
MU X

CHAN 13
CHAN 15

CHAN 17

| ReTurN
|

lHQ GROUND

|
|

)¢

)

ANALOG

HIGH QUALITY

|
COMPUTER
GROUND

GROUND

1n-419%

Figure 1-3

Pseudo-Differential Input

1-3

1= SINGLE

{ cHaAN 00

rCHAN 02
| cHan 04
! CHAN 06
CHAN 10

SWITCH POSITION
ENDED

1= PSEUDO DIFFERENTIAL

2-5=TRUE

DIFFERENTIAL

EVEN
MUX

CHAN 12

| cHAN 14

l CHAN 16

> TWISTED PAIR

| chan o

J CHAN 03
CHAN 05

GROUNDED
USER

CHAN 07

-l' INSTRUMENT

CHAN 11

GROUND

INSTRUMENT

oDD
MUX

CHAN 13

CHAN 15
CHAN 17

DO NOT USE

lRETURN
|

luo GROUND

ANALOG
HIGH QUALITY

COMPUTER _l_
GROUND

GROUND

Figure 1-4

1.3

True Differential Input

A/D CONVERTER SPECIFICATIONS

General

12-bit A/D converter with sample-and-hold

0.025% of full scale

Accuracy at 25° C

16 (single-ended or pseudo-differential)

Number of channels

8-true differential
SPC - Quad module
Program - Compatible with LPS11
Pin - Compatible with AR11 at Berg connector (H854)

Warm-up time

Uses H322 panel
|
Uses same wrap-around module
64 (single-ended or pseudo-differential)
32 (true differential)
Controlled by programmed instructions,
clock counter overflow, or external input
Parallel, 12-bit, right justified, offset binary,
double buffered
Five minutes

Power

+5 Vdc at 3.5 A (max)

Expansion capabilities
Control

Output Format

Accuracy

0.025% full scale

Relative accuracy (linearity)

No shipped states, no states wider than 2

Differential linearity guaranteed

LSB

99% of states + 1/2 LSB

1-4

Stability
Gain temperature coefficient
Linearity temperature coefficient
Offset temperature coefficient

12 ppm/° C, 20° C/LSB at full scale
3 ppmof F.S./° C, 81° C/LSB
10 ppm of F.S./° C, 24° C/LSB

Recommended calibration interval (two adjustments)

6 months

Repeatability
Rms Noise (0)

1/2 LSB (max)

Inputs

Bias current

10 na (max)

Input impedance

10 megohms (min)

Input Voltage Range

10 pF (max) OFF channel
100 pF (max) ON channel
Standard setup:
5V

Optional Setup:

+5.12 V, £10 V, £10.24

V,0tol0Vor0Oto 10.24 V

Resolution

12 bits (1 part in 4096)

Signal Dynamics

Throughput time

22 usec (includes interchannel settling and

Inter-channel settling error

A /D conversion)
1 LSB (max)

Crosstalk

80 dB down at 1 kHz

Differential CMRR

(15 OFF channels into one ON channel)
70 dB (dc to 1 kHz)

Small signal bandwidth

500 kHz typical

Slew rate limit

Sample-and-hold aperture

200 nsec typ, delay from external start

/usec

165nsec typ, delay from clock overflow

20 nsec max, delay uncertainty
1.4

PACKAGING

The AD11-K is a single quad-size module (A009) which mounts in a PDP-11 SPC slot. The RFIshields included
with this option should be mounted on each side of the A009 module. These shields do not require a Unibus slot.
To minimize computer noise within the analog circuitry, it is recommended that the AD11-K be mounted so that

at least one slot adjacent to each side of the A0O0O9 module is left empty, or so that the A0O09 module is the last
module on the bus assembly with adjacent slots left empty.
1.5

POWER REQUIREMENTS

The ADI11-K module (A009) only uses +5 Vdc at 3.5 A max. A dc to dc converter package, powered by the +5
Vdc, is used to supply £15 Vdc to the analog portions of the module.
1.6

UNIBUS LOADING

All Unibus lines are one unit load, except data lines 03 through 08, which are two unit loads.

1-5

CHAPTER 2

USER INTERFACING

2.1

CONNECTION

Input signals are interfaced to the AD11-K by a 40-pin I/O connector (H854) located in the upper right corner of
the A0OO9 module. The 40-pin I/O connector can take a standard BCO8R cable or a user-made cable terminated
with an H856 40-pin I/O connector. The pin assignments are shown below:

2.2

Signal

Channel 0

VvV

Channel 1

Channel 2

Channel 3

Channel 4

Channel §

Channel 6

Channel 7

Channel 10

Channel 11

Channel 12

Channel 13

Channel 14

Channel 15

Channel 16

Channel 17

External A /D Start

DAC Output

H.Q. Ground

KK,EE, AA, W

Return

Y,CC, HH, MM

Computer Ground

P,S

Ramp Output

H322 DISTRIBUTION PANEL

Figure 2-1 shows an H322 distribution panel. A decal set for the AD11-K identifies each terminal of the H322 to
be connected to the AO0O9 module. Persons who want to use the H322 distribution panel can order these options
together under the AD11-KT option designation, which consists of an H322, AD11-K, and one BCO8R cable

eight feet (243.84 cm) long.
2.3

SINGLE-ENDED AND PSEUDO-DIFFERENTIAL INPUTTING

Setting switch S1 to the 1 position will allow the AD11-K to operate in either single-ended or pseudo-differential
input (Figures 1-2 and 1-3). The only difference between single-ended and pseudo-differential is that in singleended the analog input is referenced to ground (Paragraphs 2.4.1 and 2.4.2), and in pseudo-differential the

analog input is referenced to a common return (Figure 1-3). This permits advantages of differential input in
situations where all the signals share a single ground line. The channel selection is shown in Table 2-1.

2-1

LOGE GRD

RETLIHN

SETURN

s cor
BEOND

B8
F

AT OHOE
YR

MA-1905

Figure 2-1

H322 Distribution Panel

2-2

Table 2-1

Channel Selection

Status Register Mux Selection

2.4
2.4.1

Input Channel Code

Pin Connection

0
0

0
1

00
01

\A"
TT

0
0
0
0
0

0
0
1
1
1

1
1
0
0
1

0
1
0
1
0

02
03
04
05
06

RR
NN
LL
JJ
FF

SINGLE-ENDED ANALOG INPUTS
Grounded Inputs

Two types of analog signals may be used as AD11-K inputs - grounded and floating. A grounded signal level is

referenced to the ground of the instrument that is producing the signal (Figure 2-2). Since the instrument may be
located some distance from the computer, there may be some voltage difference between the instrument ground

and the computer ground. The voltage seen by the AD11-K single-ended input is the sum of this unwanted
ground difference voltage and the desired signal voltage.
In cases where the input voltage is referenced to the user’s ground, a wire should not be run from the user’s
ground to the AD11-K analog ground; this could cause undesirable ground loop currents which affect results not

only on the input channel in question, but also on other channels. The ground difference should be minimized by
plugging the instrument into an ac socket as close to the computer as possible.

CGREEEED

TGEEEED

I USER INSTRUMENT

USER'S

VOLTAGE

\./

SOURCE

V SIGNAL

—l

|
|

USER'S
=

COMPUTER
=

GROUND

GROUND
11-4110

Figure 2-2

ADI11-K Input Referenced to User’s Ground

2-3

2.4.2

Floating Inputs

A floating signal voltage is measured with respect to a point that is not connected to ground. Examples of this

type of analog input are shown in Figure 2-3.
The return line of a floating signal must be connected to one of the AD11-K analog input grounds (Paragraph

2.1). Although there are only four analog input grounds for the 16 analog channels, these grounds may be shared

among channels. The identifying characteristic of a floating source is that connecting the signal return to the
AD11-K ground does not result in a current path between the AD11-K ground and the instrument ground.

AD11-K
FLOATING SOURCE

SIGNAL -

RETURN *

BATTERY POWERED

1= SINGLE ENDED

CHAN 00

2 = DIFFERENTIAL

! CHAN 02

| chan o4
! CHAN 06
.
| can 10
I chan 12

|
EVEN

MUX

| cHAN 14
|

SOURCE

CHAN 16

COMPUTER

_ |siGNAL -,
—

GROUND

1__[RETURN X

SIGNAL -

RETURN

| chan o1

| chan o3

| cHan os
CHAN 07

INSTRUMENT WITH

| CHAN 1

ISOLATION TRANS-

| CHAN 13

FLOATING SECONDARY

__¢ CHAN 15

FORMER AND

”l

0DD

MUX

_] CHAN 17

1 _|RETURN
2.

-l

SWITCH POSITION

|SIGNAL .

J RETURN

HQ GROUND
l

ANALOG

GROUND

11-4112

HHSVAC |

Figure 2-3

2.5

Floating AD11-K Input Signals

TRUE DIFFERENTIAL INPUTTING

Setting switch S1 to position 2, 3, 4 or 5 will electrically pair input lines for true differential input operation
(Figure 1-3). The least significant bit of the channel selection (Status register bit 08) is ignored. The channel pair

selection is shown in Table 2-2.

2-4

Table 2-2

Channel Pair Selection

Status Register Mux Selection

2.6

0
0
0

0
0
|

0
|
0

X
X
X

New Channel Code

Input Channel Pair

Pin Connection

00
02
04

01
03
05

vv
RR
LL

TT
NN
J1J

TWISTED PAIR INPUT

The affects of magnetic coupling on the input signals may be reduced for floating or differential inputs by
twisting the signal and return lines in the input cable. If the inductive pickup voltages of the two leads match, the

net effect seen at the AD11-K input is zero. Twisted pairs have no affect with a single-ended, non-floating signal
(referenced to ground at the instrument end).
2.7

SHIELDED INPUT

The affects of electrostatic coupling on the input signals may be reduced by shielding the signal wires. This is
especially important if the instrument or transducer has high source impedance. The shield should be connected

to ground at one end of the cable only so that it does not carry any current.
2.8

INPUT SETTLING WITH HIGH SOURCE IMPEDANCE

All solid-state multiplexers have the unavoidable side affect of injecting a small amount of charge into their input
lines when changing channels, causing a transient error voltage which is discharged by the input signal’s source

impedance.

When starting a conversion, a 10 usec interval is allowed for the AD11-K multiplexer and sample-and-hold to
settle to the correct value of the newly-selected channel before the conversion begins. Normally, this is sufficient

time for the input transient to settle out; however, more time may be needed when switching into an input
channel with high source impedance. It may be necessary to either reduce the signal’s source impedance or preset
the multiplexer channel and provide a software delay before starting the conversion.
2.9

EXTERNAL STARTS

The external start signal line, pin U of the 40-pin 1/O connector (H854) or TAB?2, is a TTL-compatible input
which sees two TTL unit loads (3.2 mA). Conversions start on the high to low transition of this signal.
In most cases, the source of the external start signal is a grounded (non-floating) signal generator or logic

circuitry located in a grounded instrument. Like the analog input signal, the return path for the External Start
signal is through the grounds, and a separate return wire should not be run. The ground difference between the

signal source and the computer should be minimized to prevent spurious start pulses due to ground noise.
In the case of a floating pulse generator only, the pulse generator’s logic ground should be connected to the
AD11-K’s logic ground pins of the I/O connector.

When the AD11-K is used with the KW11-K programmable real-time clock, the output of Schmitt trigger one of
the KW11-K is available at a FAST-ON TAB (also possessed by the AD11-K). By using a DEC 7010771 type
jumper (Figure 2-4), the KW11-K’s Schmitt trigger one output can be jumpered to the AD11-K’s External Start
input within the central processor cabinet.
2.10

JUMPERS

The ADI11-K is equipped with solder jumpers (Figure 2-5) which may be changed by the user. The jumper

functions and identifications are listed in Table 2-3. The jumper configuration must be set up for +£5 V or £5.12
V input range when testing with the wrap-around module. Input range jumper setup is as shown in Table 2-4.

1/0

CONNECTORS

TPPQ BTAB 2
J1 ::?v

A/D CONVERTER PACKAGE
-15V

+15V

WIA

HQ GNDQ@ |0 |

wi1B
S

TM W2A
W2B

w2
4

2 1 5

DC-DC

CONVERTER

0\13_0

PRIORITY

NOTE:

CONNECTOR

W1,wW2 and W3 are factory machine inserted.

11-4119

Figure 2-4

A009 Module

2-6

Figure 2-5

Module Jumpers

Table 2-3
A009 Jumper Descriptions
Jumper ID (See Figure 2-4)

Description

W1 — Factory Installed

Provides 5 V Input

WI1A — User Installed

Provides 5 V Input

W1 B — User Installed

Provides 10 V Input

W2 — Factory Installed

Provides Bipolar Input

W2A — User Installed

Provides Bipolar Input

W2B — User Installed

Provides Unipolar Input

W3 — Factory Installed

NPR — Removed only if PDP-11/20 or 11/15
without a KH11 option

W4 — User Installed

+5.12V,%10.24 V, or 0 > +10.24 V Input

Table 2-4
A009 Input Range Jumpers
Jumper

Input Range

5 V Bipolar

10V

Oto+10V

512V

10.24V

Bipolar

Unipolar

Bipolar

Wi1*

Out

WI1A

Out

WiB

Out

W2*

Out

W2A
W2B

Out
Out

Out
In

Out
Out

Out

*Once W1 and W2 are removed, they are not to be re-installed. These jumpers are paralleled by jumpers W1A
and W2A respectively.

2.11

SWITCHES

A double pole switch (Figure 2-4) is provided for switching between single-ended and differential input con-

figurations. When S1 is in position 2, 3, 4 or 5, the AD11-K is in true differential configuration and when S1 is in

position 1, the AD11-K is in single-ended or pseudo-differential configuration. Single pole/single throw switches
in switch packs are used to change the register and vector addressing (Paragraph 3.1) of the AD11-K. The switch
identification for the address lines and vector lines is shown in Tables 2-5 and 2-6, respectively. Register address
lines are switched on for a logical 0; vector address lines are switched on for a logical 1.

2-8

Table 2-5

Table 2-6

Address Line Selection

Vector Line Selection

Switch

2.12

Address Line

Switch

Vector Line

Not Selectable

AlS

S3-1

Not Selectable

Al4

S3-2

Not Selectable

Al3

S3-3

S2-10

Al2

S3-4

S2-9

All

S3-5

S2-8

AlO

S3-6

S2-7

A09

S2-6

AO8

S2-5

AO07

S2-4

AO6

S2-3

A0S

S2-2

A04

S2-1

AO3

S3-8

AO02

Not Selectable

AO1

Not Selectable

AO00

OVERFLOW OR EXTERNAL START CONNECTION

Two FAST-ON TABS are available on the A009 for inputting signals from the KW11-K programmable real-

time clock option. The KW11-K (M7025) also has two FAST-ON TABS (Figure 2-6) for outputting two signals
- A Overflow and Schmitt trigger one. These signals can be jumpered between the A009 and M 7025 models by
using DEC 7010771 type jumpers (included with the AD11-K). This allows for signal connection within the
processor cabinet and does not interfere with the regular

1/O connector on each module. TAB 1 of the KW11-K

is A Overflow and is re-named A Event Out. This can be jumpered to TAB 1 of the AD11-K, which is called KW

Overflow.
TAB 2 of the KW11-K is Schmitt Trigger one. This can be jumpered to TAB 2 of the AD11-K, which is called
External Start.

TAB 2 I

TAB 1

EXT

START

KW OVERFLOW

ST!

OUT

EVENT T

OUT

AD11-K

TAB 2

ITAB |

KW11-K
11-4109

Figure 2-6

Tab Connections

2-9

CHAPTER 3

PROGRAMMING

3.1

REGISTER AND VECTOR ADDRESSING
Register and vector addresses are configured prior to shipment in standard configurations, but may be changed
by means of switches on the AO0O9 module. Paragraph 2.11 describes the procedure for changing the register and

vector addresses.

The ADI11-K has a floating address to allow the use of more than one AD11-K in a system, or to avoid any

device address conflict with other options. The register address is selected by switches on the A0O09 module
representing address lines A 12 through A02. The standard register addresses selected for the AD11-K are:

170400

R/W - Status register

170402

Write - Loads DAC buffer register
Read - Reads A /D buffer register

The vector address is selected by switches on the A009 module representing vector lines (Unibus “D’’ Lines) D08
through DO03. The standard vector address selected for the AD11-K is 340s.
3.2

PRIORITY LEVEL

The A009 is normally shipped with a priority level configuration of BR6; this level may be changed by replacing
the priority connector for another level.
3.3
3.3.1

REGISTERS
Status Register

The A /D Status register is illustrated in Figure 3-1 and described in Table 3-1.
15

NOT
USED

ERROR
FLAG

MUX 04

MUX 05
\

MUX 02

MUX 03
~

MUX 00

MUX O1
-~/

INTR
ENABLE

DONE FLAG

CLOCK

OVERFLOW

A/D Status Register Format

3-1

EXT START
ENABLE

ENABLE

MULTIPLEXER CHANNEL

Figure 3-1

A/D
START

—~

NOT USED

/
- 117

Table 3-1
AD11-K Status Register Bit Descriptions
Bit

Name

ERROR FLAG (R/W)

Description

This bit sets when:

1. A second A/D conversion ends before data from

the previous A/D conversion is read.

2. A second A/D start is initiated before the first conversion is complete.

Defines which A/D input channel of the multiplexer is

Mux Channel (R/W)

13—8

to be sampled.

Sets upon completion of an A/D conversion. Cleared by

DONE FLAG (R)

hardware when the A/D interrupt bus cycle is completed
or when the buffer register is read.

INTERRUPT ENABLE (R/W)

When a conversion is completed, the done flag will cause
an interrupt if this bit is set.
Permits overflow from KW11-K Real-Time Clock to

OVERFLOW ENABLE (R/W)

cause an A/D start. This allows channel sampling at precisely timed intervals independent of software. Data

may then be read by testing the A/D done flag or by
enabling the interrupt.

3.3.2

EXTERNAL START ENABLE (R/W)

Permits an external event to initiate an A/D conversion.

A/D Start (R/W)

Starts an A/D conversion. Cleared at end of conversion.

A/D Buffer Register

The A/D Buffer register is a read only register. It furnishes the 12-bit converted value, formatted in 12-bit right-

justified offset binary after an A /D conversion is complted (Figure 3-2).
12-BIT

INPUT

RESULTS

t5v

(OCTAL)
oorrrv

+5.12V

+4.9976V | +5.1175V

VOLTAGE RANGE

+10.24V

+i10v

0 -10V

+9.9951V | +10.235V | +9.9976V

004000

000000

-5.0V

-5.120V

-10.0v | -10.240V

RESOLUTION | 2.44MV

2.5MV

4 .88MV

5.0MV

0-10.24V
|[+10.2375V

+ 5.0V

+5.12V

2.44MV

2.5MV

a) A/D RANGE CHART

——

VAN

DATA

UNUSED
b) A/D

BUFFER

Figure 3-2

/D Buffer Register Format

3-2

3.3.3

DAC Buffer

The DAC Bulffer is a write only register. It is a 8-bit register which holds the digital value to be converted to an

analog signal (Figure 3-3).

8-BIT

INPUT

OUTPUT

(OCTAL)

RANGE

000377

+1.860V

000200

000000

-1.875V

RESOLUTION
a) DAC

14.64mvV
RANGE CHART

UNUSED

DATA

NOTE:

b) DAC

ONE LSB =19.4mV

1-413

Figure 3-3

3.4

DAC Buffer Register

Format

PROGRAMMING EXAMPLE

Read 64,9 (1005) A/D conversions from channel 0 into locations 40005 — 41765 and halt.
R0O=%0

START:

LOOP:

CLR

@ADSR

MOV

;CLEAR A/D STATUS REGISTER

#4000,R0

;SET UP FIRST ADDRESS

INC

@ADSR

;START A/D CONVERSION ON CHANNEL 0

TSTB

@ADSR

.CHECK DONE FLAG

BPL

LOOP

WAIT UNTIL FLAG SET

INC

@ADSR

SSTART NEXT CONVERSION

MOV

@ADBR,(ROQ)+

;PLACE CONVERTED VALUE FROM A/D
;BUFFER INTO CORE LOCATION AND SET UP

NEXT CORE LOCATION FOR TRANSFER
CMP

RO,#4200

CHECK |IF 64. CONVERSIONS HAVE BEEN

BNE

LOOP

;NO, GET NEXT CONVERSION

;:DONE
HALT

;DONE

ADSR:

170400

;A/D STATUS REGISTER ADDRESS

ADBR:

170402

;A/D BUFFER REGISTER ADDRESS

.END

START

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