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AH-8445C-MC

January 1979

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Document:	CZDHAC0 DH11 STATIC LOGIC TEST JAN 1979 bw
Order Number:	AH-8445C-MC
Revision:	000
Pages:	94
Original Filename:	CZDHAC0__DH11__STATIC_LOGIC_TEST__AH-8445C-MC__JAN_1979_gray.pdf

OCR Text

STATIC LOGIC TEST

CZDHACO

AH-8445C-MC

JAN 1979

FICHE1 OF
1

MADE
IN USA

!fl:fluafl

-REM

SEQ 0001

IDENTIFICATION

THE

PRODUCT CODE:

AC-B444(C-MC

PRODUCT NAME:

(ZDHACO DH11

DATE:

MAY 1978

MAINTAINER:

DIAGNOSTIC GROUP

AUTHOR :

MICHAEL DAVIS

INFORMATION IN THIS DOCUMENT

STATIC

1S SUBJECT

LOGIC

TEST

TO CHANGE WITHOUT

NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION.
DIGITAL EQUIPMENT CORPORATION ASSUMES
&WSIBIL”Y FOR ANY ERRORS THAT MAY APPEAR IN THIS

DIGITAL EQUIPMENT CORPORATION ASSUMES NO RESPONSIBILITY
FOR THE USE OR RELIABILITY OF ITS
THAT IS NOT SUPPLIED BY DIGITAL.

SOFTWARE ON EQUIPMENT

1978 BY DIGIFAL EQUIPMENT CORPORATION,

MAYNARD, MASSACHUSETTS.

THE FOLLOWING ARE

DIGITAL
DEC

TRADEMARKS OF DIGITAL EQUIPMENT CORPORATION

PDP

DE CUS

UNIBUS

DECTAFE

MASSBUS

ABSTRACT
THE DM11

STATIC LOGIC TEST IS DESIGNED TO PROVIDE A MEANS

FOR TESTING THE

CORRECT FUNCTION OF ALL READ/WRITE BITS

IN THE FOLLOWING DH11 REGISTERS:

DH11 SYSTEM CONTROL REGISTER
DH11 LINE PARAMETER REGISTER
DH11 BREAK CONTROL REGISTER
DH11 SILO STATUS REGISTER
IN ADDITION,

TESTS ARE PROVIDED TO CHECK THE FUNCTION

OF THOSE BITS THAT ARE READ ONLY IN MAINTENANCE MODE.
ALSO PROVIDED ARE TESTS OF REGISTER ADDRESSABILITY,
AND OF THE FUNCTION OF MASTER CLEAR.
THE DIAGNOSTIC HAS BEEN WRITTEN SO THAT

THE

TESTING

OF EACH FUNCTION IS CONTAINED IN AN INDIVIDUAL
TEST LOOP.

SEQ 0002

REQUIREMENTS

2.1

EQUIPMENT

SEQ 0003

PDF=11 FAMILY STANDARD COMPUTER WITH EKW OF MEMORY

ASR-33 TELETYPE OR EQUIVALENT
DH11 ASYNCHRONOUS MULTIPLEXER
DM11 MAINTENANCE CARD INSTALLED
2.2

STORAGE
THE PROGRAM LOADS INTO 8Kkw OF MEMORY
LOADING PROCEDURE
THE

STANDART PROCEDURE

IS TO BE USED
4.

STARTING PROCEDURE

6.1

CONTROL

4.1.1

AFTER PROGRAM LOAD

FOR LOADING ABSOLUTE BINARY

TAPES

SWITCH SETTINGS

(INITIAL

PROGRAM START)

ALL CONSOLE SWITCHES DOWN
&.1.2

TO MODIFY DEVICE VECTOR AND CONTROL REGISTER ADDRESSES
AFTER PROGRAM RESTART

SW00=1
4.1.3

TO START PROGRAM AT SELECTED TEST AFTER PROGRAM RESTART

SWO1=1
4.2

STARTING ADDRESS
THE STARTING ADDRESS FOR ALL
THE RESTART ADDRESS FOR ALL
THE

STARTING ADDRESS

TESTS
TESTS

IS 000200
I

0002000

TO ENTER A SELECTED

TEST

IS 000200

PROGRAM AND/OR OPERATOR ACTION

WA
N

INITIAL PROGRAM START
LOAD PROGRAM INTO MEMORY

LOAD ADDRESS 000200

CLEAR CONSOLE SWITCHES

PRESS START
THE PROGRAM WILL TYPE ‘DH11 STATIC LOGIC TE?T"
AND WILL THEN TYPE 'VECTOR ADDRESS-"' AND WAIT FOR AN

INPUT FROM THE TELETYPE KEYBOARD.

4.3 (CONT'D)

SEQ 0004

4.3.1.6 TYPE IN THE ADDRESS OF THE RECEIVER INTERRUPT VECTOR
FOR THE DH11

NOTE:

TO BE

TESTED FOLLOWED BY <CARRIAGE RETURN>

WORDS IN ANGLE BRACKETS,
THE

I.E. <CARRIAGE RETURN> MEAN THAT

TELETYPE KEY WITH THE NAMED FUNCTION SHOULD BE STRUCK

IF AN_INCORRECT ADDRESS IS ENTERED, THE PROGRAM

WILL TYPE "' AND WILL REPEAT THE SECOND MESSAGE
OF 4.3.1.5

4.3.1.7 THE PROGRAM WILL TYPE ‘‘CONTROL REGISTER ADDRESS-

AND WAIT FOR AN INPUT FROM THE TELETYPE KEYBOARD

4.3.1.8 TYPE IN THE ADDRESS OF THE SYSTEM CONTROL REGISTER OF
DH11 TO BE TESTED FOLLOWED BY <CARRIAGE RETURN>
IF AN INCORRECT ADDRESS IS TYPED,

THE PROGRM WILL

7" AND WILL THEN REPEAT THE MESSAGE
OF 4.3.1.7

THE

TYPE

PERFORM 4.3.1.2 T0 4.3.1.5

THE PROGRAM WILL TYPE "DH11 STATIC LOGIC TEST''
AND WILL THEN CONTINUE AS DESCRIBED IN 4.3.1.9

PROGRAM RESTART WITH SW00=1
HWN
=

WWWW

}NWWW

SWiTCHES DOWN

LOAD ADDRESS 000200
SET SW01=1

PRESS START

THE PROGRAM WILL PERFORM AS DESCRIBED

IN 4.3.7.5

70 4.3.1.9

PROGRAM RESTART WITH SWO1=1
S NN
=

WWWW

PP
aP o
N

T 2 F 2P I

N =

PROGRAM RESTART WITH ALL

HEe

4.3.1.9 THE PROGRAM WILL TYPE 'R'* TO INDICATE YHAT IT IS
ABOUT TO START TESTING, AND THEN TESTING WILL BESIN

LOAD ADDRESS 000200
SET SW01=1

PRESS START
THE PROGRAM WILL

TYPE ‘DH11 3STATIC LOGIC TEST''
AND WILL THEN TYPE 'TEST PC-'" AND WILL WAIT FOR AN INPUT
FROM THE TELETYPE KEYBOARD

4.3.4.5 TYPE IN THE ADDRESS OF THE TEST AT WHICH THE PROGRAM IS TO
BE STARTED FOLLOWED BY <CARRIAGE RETURN>
fl

4£.3.4.6 THE PROGRAM WILL TYPE R TO INDICATE THAT IT HAS STARTED
AND WILL START TESTING AT THE SELECTED TEST.

NOTE:

CARE MUST BE TAKEN WHEN THS FEATURE
THERE

NOTE:

IS USED,

SINCE

IS NO PROTECTI(N AGAINST SELECTING AN ADDRESS THAT

IN THE MIDDLE OF
A TEST

IF IT IS DESIRED TO LOOP ON THE TEST THAT IS SELECTED
SET SW14=1 BEFORE ENTERING THE TEST ADDRESS

OPERATING PROCEDURE

5.1

SEQ 0005

OPERATIONAL SWITCH SETTINGS

SW15=1, HALT ON ERROR

SW14=1, LOOP ON CURRENT TEST

.
.
SW10=1,
SW09=1,
SW01=1,
SW00=1,

SUPPRESS ERROR TYPEOUT
INHIBIT ITERATIONS
ESCAPE TO NEXT TEST ON ERROR
FREEZE VARIABLE PARAMETER IN CURRENT TEST
START PROGRAM AT SELECTED TEST
CHANGE PARAMETERS AT PROGRAM RESTART

5.2

SUBROUTINE ABSTRACTS

5.2.1

TRAPCATCHER

(LOCATIONS 000000-000776)

NDe

ONO
V-

oror

THIS ROUTINE IS USED TO INTERCEPT UNEXPECTED INTERRUPTS
AND TRAPS.
THE AREA FROM 000000-000776 IS LOADED
WITH THE FOLLOWING SEQUENCE

IF AN UNEXPECTED INTERRUPT OR TRAP OCCURS, THE PROGRAM
WILL HALT WITH THE PC 2 GREATER THAN THE ADDRESS TO
WHICH THE PROGRAM TRAPPED.

THE PROCESSOR STACK MAY

BE EXAMINED TO DETERMINE WHERE
TRAP OR INTERRUPT OCCURED.

5.2.8

START

THE PROGRAM WAS WHEN THE

(PROGRAM INITIALIZATION)

THIS ROUTINE INITIALIZES ALl. PROGRAM FLAGS AND COUNTERS,
TYPES THE PROGRAM TITLE MESSAGE, AND INPUTS THE VECTOR
AND CONTROL REGISTER ADDRESSES OF THE DH11 TO BE TESTED.

BEGIN

(PROGRAM START AND RESTART)

THIS RQJTINE

IS ENTERED IMMEDIATLY AFTER °''START"'

AND EACH TIME
A PROGRAM PASS HAS BEEN COMPLETED.

THE ROUTINE SETS UP THE PROCESSOR STACK AND STATUS WORD
AND THEN TRANSFERS CONTROL TO THE TEST AT WHICH
TESTING WILL BEGIN.
IF SWO!=0 WHEN THIS ROUTINE IS ENTERD
TESTING WILL START AT T1 (TEST 1).
IF Sw01=1
THIS ROUTINE IS ENTERED, TESTING WILL START AT THE PC

ENTERED FROM THE

TELETYPE KEYBOARD.

5.2.4

EOP

(END OF PASS)

SEQ 0006

THIS ROUTINE IS ENTERED ONCE PER PASS AFTER ALL TESTS
HAVE BEEN COMPLETED.
THIS ROUTINE TYPES THE MAINDEC
IDENTIFICATION CODE OF THE PROGRAM, CLEARS ERROR FLAGS
AND UPDATES THE PASS COUNT.
IF THE PROGRAM WAS LOADED
UNDER ACT11 OR DDP, THE ROUTINE CHECKS FOR RETURN TO
THE ACTT1 OR DDP MONITOR.
IF THE PROGRAM IS NOT UNDER
MONITOR CONTROL, THE ROUTINE TRANSFERS TO BEGIN.

5.2.5

SCOPER

(SCOPE LOOP AND ITERATION HANDLER)

THIS ROUTINE IS ENTERED EACH TIME A TEST IS COMPLETED.
THE ROUTINE CHECKS FOR THE FOLLOWING UPON ENTRY

IF SW10=1, THE ROUTINE WILL TRANSFER TO THE NEXT TEST
IN SEQUENCE, AFTER CLEARING ERROR FLAGS.

IF SW11=1, THE ROUTINE WILL TRANSFER TO THE NEXT TEST
SEQUENCE, AFTER CLEARING ERROR FLAGS.
() IF SW14=1, THE ROUTINE WILL LOOP ON THE CURRENT TEST
REGARDLESS OF THE ITERATION COUNT.
IF NONE OF THE ABOVE IS TRUE, THE ROUTINE WILL ADD 1

TO THE COUNT OF TEST ITERATIONS, AND COMPARE THIS VALUE
TO THE NUMBER OF ITERATIONS THAT SHOULD BE PERFORMED.

IF THESE NUMBERS ARE EQUAL,

THE ROUTINE WILL TRANSFER

TO THE NEXT TEST IN SEQUENCE.
THE THE NUMBERS ARE NOT
EQUAL, THE TEST CURRENTLY IN PROGRESS WILL BE REPEATED.

5.2.6

SCOPTR

(FREEZE ON CURRENT DATA)

THE CALL TO THIS ROUTINE FOLLOWS IMMEDIATLY AFTER THE
THE CALL TO THE ERROR HANDLER IN THOSE TESTS THAT HAVE

VARIABLE PARAMETERS.
THOSE

THIS ROUTINE

IS ALWAYS ENTERED IN

TESTS, WHETHER OR NOT AN ERROR OCCURS.

IF SW09=1, THE ROUTINE WILL TRANSFER CONTROL BACK TO THE

TEST AT A POINT WHICH WILL ALLOW REPEATING THE FUNCTION

UNDER TEST CONTINUOUSLY WITH THE SAME DATA.
IF THIS
OPTION IS SELECTED, THE ROUTINE ''SCOPER'' IS NEVER ENTERFD

AND ITERATION COUNTS WILL NOT BE UPDATED.

S.2.7

ERRORS

(ERROR HANDLER)

SEQ 0007

THIS ROUTINE IS ENTERED UPON ERROR DETECTION ONLY.
WITH ALL CONSOLE SWITCHES DOWN, THE ROUTINE PROCEDES AS FOLLOWS:
A) THE PC OF THE INSTRUCTION rmr CALLED THE ERROR HANDLER

IS ACCESSED THRU THE STACK, AND THEN THE EMT INSTRUCTION
ITSELF IS FETCHED.
THE 8 LSB OF THE EMT
INSTRUCTION ARE THE ERROR CODE.
THIS CODE IS
USED TO ACCESS A TABLE OF ERROR MESSAGES AND ERROR

DATA STORAGE LOCATIONS.
IF THE TEST THAT FAILED DID NOT FAIL PREVIOUSLY
DURING THIS PASS,
A COMPLETE ERROR REPORT 1S MADE
IF THE TEST THAT FAILED FAILED MOR THAT ONCE DURING
THE CURRENT PASS,

IS TYPED.

ONLY THE DATA RELATING TO THE FAILUER

IF SWi3=1, NO ERROR TYPEOUT IS MADE.

THE ROUTINE NOW CHECKS FOR HALT ON ERROR.

THE PROGRAM WILL HALT WITH THE PC OF
THE ERROR ROUTINE IN RO.
IF SW15=0,

NOT HALT,

BUT WILL CHECK FOR ESCAPE TO NEXT TEST.

D) IF sw10=0, THE ROUTINE WILL RETURN
TO THE

IF SW15=1

THE CALL TO
THE PROGRAM WILL

TEST

IN PROGRESS.

SW10=1,

THE ROUTINE WILL

ABORT THE CURRENT TEST, AND TRANSFER TO THE NEXT
TEST

5.2.8

TRPSRV

IN SEQUENCE,

THRU THE ROUTINE ''SCOPER'".

(TRAP DECODE AND DISPATCH)

THIS ROUTINE DECODES THE 8 LSB OF THE TRAP INSTRUCTION
THAT CAUSED TH PROGRAM INTERRUPT, AND TRANSFERS CONTROL
TO THE ROUTINE THRU THE TABLE ‘‘TRPTAB'' USING THE 8 LSB
OF THE TRAP INSTRUCTION AS
AN OFFSET TO THE POINTER TO
THE ROUTINE

TO BE

ENTERED.

5.3

PROGRAM AND OR OPERATOR ACTION

5.3.1

PROGRAM START WITH ALL SWITCHES DOWN

SEQ 0008

5.3.1.1 REFER TO SECTIONS 4.3.1 AND 4.3.2 FOR INITIAL PROGRAM
BEHAVIOR.

5.3.1.2 AFTER 'R'' HAS BEEN TYPED BY THE PROGRAM, TEST EXECUTION

WILL BEGIN.
EACH TEST WILL BE REPEATED A SELECTED NUMBER
OF ITERATIONS (SEE LISTING FOR EXACT NUMBER FOR EACH TEST)
AND THEN THE PROGRAM WILL PROCEED TO THE NEXT TEST.

5.5.1.3 WHEN ALL ITERATIONS HAVE BEEN COMPLETED, THE PROGRAM
WILL TYPE '‘CZDHA=C'' AND THEN RESTART TESTING AT TEST 1
(LOCATION T1

IN THE PROGRAM).

5.3.1.4 IF AN ERROR OCCURS, THE PROGRAM WILL TYPE AN APPROPRIATE
ERROR MESSAGE, AND THEN CONTINUE

5.3.2

THE TEST

PROGRAM START WITH SW00=1
THE PROGRAM WILL PERFORM AS DESCRIBED

5.3.3

IN PROGRESS.

iIN 4.3.1

AND 5.3.1

PROGRAM START WITH Sw01=1

5.3.3.1 REFER TO SECTION 4.3.4 FOR INITIAL PROGRAM BEHAVIOR
$.5.3.2 TEST EXECUTION WILL START AT THE ADDRESS SPECIFIED
AND WILL CONTINUE AS DESCRIBED

IN 5.3.1.2

5.3.3.3 AFTER “'CZDHA-C'' HAS BEEN TYPED, THE PROGRAM WILL
RESUME

5.3.4

TESTING AT

TEST 1

PROGRAM OPERATION WITH SW15=1

SAME AS 5.3.1, EXCEPT THAT IN THE CASE OF AN ERROR,

THE PROGRAM WILL HALT AFTER THE ERROR TYPEOUT, AND
THE PC+2 OF THE CALL TO THE ERROR ROUTINE WILL BE
DISPLAYED IN RO.

$.3.9

PROGRAM OPERATION WITH SW13=1

SAME AS 5.3.1 EXCEPT THAT NO ERROR TYPEOUTS WILL OCCUR

5.3.6

PROGRAM OPERATION WITH SW11=1

cS)NAfi AS 5.3.1 EXCEPT THAT EACH TEST WILL BE REPEATED ONCE
5.3.7

PROGRAM OPERATION WITH SW10=1

SAME AS 5.3.1, EXCEPT THAT IN THE CASE OF AN ERROR

THE CURRENT TEST WILL BE ABORTED, AND THE PROGRAM
WILL PROCEED TO THE NEXT TEST IN SEQUENCE.

(CONT'D)

5.3.8

PROGRAM OPERATIOM WITH SW14=1, OR SW09=1

SEQ 0009

THESE FUNCTIONS ARE NORMALLY USED FOR TROUBLE SHr ,TING.

SEE SECTION 6.3 FOR THEIR USE.
ERRORS

6.1

ERROR HALTS
THE ERROR MESSAGE

IS AS FOLLOWS

PC+2

FORMAT FOR ALL ERROR TYPEOUTS

ME SSAGE
HEADER (IF APPLICABLE)
DATA
(IF APPLICABLE)

WHERE
PC+2 IS THE ADDRESS OF

THE CALL TO THE ERROR HANDLER + 2
MESSAGE IS AN ASCII MESSAGE DESCRIBING (BRIEFLY) THE FAILURE
HEADER IS A DESCRIPTION OF THE DATA TO FOLLOW
DATA IS OCTAL INFORMATION RELATING TO THE CAUSE OF THE FAILURE
IF THE SAME ERROR OCCURS IN A GIVEN TEST ON THE SAME
PASS, AND

IF DATA IS ASSOCIATED WITH THAT ERROR,

DATA IS TYPE ON SUCCEEDING ERROR TYPEOUTS

ONLY

IF NO DATA IS ASSOCIATED WITH THE ERROR
THE COMPLETE ERROR MESSAGE IS TYPED.

6.1.1

ERROR DESCRIPTIONS

SEE LISTING FOR DETAILS OF ERRORS

6.2

j6.2.1

ERROR RECOVERY

SW15=0
IF

6.2.2

THE PROGRAM IS RUN WITH SW15=0, NO OPERATOT ACTION IS

REQUIRED TO CONTINUE

SW15=1
IF

TESTING

THE PROGRAM IS RUN WITH SW15=1,

TO CONTINUE

TESTING

AFTER THE PROGRAM HAS HALTED, PRESS THE PROCESSOR

CONSOLE CONTINUE SWITCH

6.3

SCOPE LOOPING

6.3.1

TO SCOPE ON A SPECIFIC TEST, SET SW14=1 AND SW13=1
THIS WILL CAUSE THE PROGRAM TO CONTINUOUSLY LOOP ON THE
SAME TEST, AND WILL CAUSE ALL ERROR TYPEOUTS TO BE INHIBITED

6.3.2

TO SCOPE ON A SPECIFIC VALUE OF A PARAMETER WITHIN

A TEST, SET SW09=1 TO FREEZE THE DATA
(SEE LISTING FOR THOSE TESTS THAT INCORPORATE

THIS FEATURE)

(CONT'D)

SEQ 0010

PROGRAM START TO SCOPE LOOP ON SELECTED TEST

PERFORM SECTION 4.3.4 WITH SW14=1
RESTRICTIONS

STARTING
THE DH11

TEST CARD MUST BE

INSTALLED

RUNNING

NONE
MISCELLANEOUS

8.1

EXECUTION TIME
THE TIME FOR ONE PASS OF THE
TYPEOUT OF CZDHA-C TO END OF

PROGRAM (END OF
TYPEOUT OF (ZDHA-C)

IS GIVEN FOR VARIOUS PROCESSORS IN THE

PROCESSOR

PDP-11/05,10
PDP-11/20
PDP-11/40
PDP-11/45

TIME

TABLE BELOW

PROGRAM DESCRIPTION

SEQ 0011

THIS PROGRAM IS A LOW LEVEL TEST OF DH11
REGISTERS.

CONTROL

THE PROGRAM BEGINS BY CHECKING THE ADDRESSABILITY OF

EACH DH11 REGISTER WITHOUT CONCERN FOR ANY DATA CONTENT.

THE PURPOSE OF THESE TESTS IS TO VERFIY THAT THE ADDRESS
SELECTORS FOR THE VARIOUS REGISTERS ARE FUNCTIONING.
THE NEXT SET OF

TESTS VERIFIES THAT EACH DH11

CAN BE MASTER CLEARED, AFTER ALL READ/WRITE BITS HAVE
BEEN SET TO 1.
THIS TEST DOES NOT VERIFY THAT ALL
BITS HAVE BEEN SET, ONLY THAT THEY HAVE BEEN CLEARED.
THE _NEXT GROUP OF

TESTS EXERCISES EACH READ/WRITE BIT

IN THE DH11 SYSTEM CONTROL REGISTER, IN BOTH NORMAL AND

MAINTENANCE MODES OF OPERATION.
IN NORMAL MODE, EACH
READ/WRITE BIT IS SET AND CLEARED, AND READ ONLY BITS
ARE CHECKED FOR READ ONLY FUNCTION.

IN MAINTENANCE MODE, THE BITS THAT ARE

READ ONLY IN NORMAL MODE ARE CHECKED FOR READ/WRITE OPERATION.
THE NEXT GROUP OF

TESTS CHECKS EACH READ/WRITE BIT

OF THE DH11 LINE PARAMATER REGISTER, BREAK CONTROL REGISTER
AND SILO STATUS REGISTER FOR READ/WRITE CAPABILITY. EACH
BIT OF EACH REGISTER IS CHECKED IN AN INDIVIDUAL TEST LOOP.
THE NEXT GROUP OF TESTS CHECKS CLEARING OF A SINGLE
BIT IN EACH OF THE LINE PARAMETER, BREAK CONTROL AND
gélfOT(S)T?TUS REGISTERS WITH ALL OTHER READ/WRITE BITS
THE FINAL TWO TESTS VERIFY THAT A MOVE BYTE TO ONE BYTE
OF THE SYSTEM CONTROL REGISTER DOES NOT AFFECT THE OTHER BYTE
OF THE SYSTEM CONTROL REGISTER.

AFTER ALL

TESTS HAVE BEEN COMPLETED,

THE PROGRAM TYPES

"'CZDHA-C'" AND RESTARTS THE SEQUENCE OF TESTING JUST DESCRIBED.

10.

L|ISTING

CZDHA-C MACY11 30A(1052)

23-AUG-78
15-MAY-78 10:02

NN8
N=0O
VO NONSHWN=OV0ONA
NI WA =

CZDHAC.P1T

14:40

PAGE 2

;DH11 STATIC LOGIC_TEST
;COPYRIGHT 1972,1978, DIGITAL EQUIPMENT CORP., MAYNARD, MASS. 01754
s STARTING PROCEDURE
;L OAD PROGRAM

:LOAD ADDRESS 000200

:PRESS START
:PROGRAM WILL TYPE DH11

STATIC LOGIC TEST
:PROGRAM WILL TYPE ‘VECTOR ADDRESS:TYPE_IN THE_ADDRESS OF THE RECEIVER INTERRUPT VECTOR
:FOR THE DH11 TO BE TESTED, FOLLOWED BY <CARRIAGE RETURN>

1
1
1
1
1
1
1
1
1

23
24
25

:PROGRAM WILL TYPE ‘‘CONTROL REGISTER ADDRESS='
:TYPE_IN THE_ADDRESS OF

;AT THE END OF A PASS, PROGRAM WILL

AND THEN RESUM TESTING

100000

000100

000020

000004

32
34

36
%g

TYPE ** CZDHA=C
'

;SWITCH REGISTER OPTIONS

29
30

THE SYSTEM CONTROL REGISTER

:FOR THE DH11 TO BE, TESTED, FOLLOWED BY <CARRIAGE RETURN>
:PROGRAM WILL TYPE ‘R"" TO INDICATE THAT TESTING WAS STARTED

040000
020000
010000
004000
002000

SEQ 0012

001000
000400

000040
000010

000002
000001

SW15=100000
SW14=40000
SW13=20000

SW12=10000
SW11=4000
SW10=2000
Sw09=1000
Sw08=400

SwW06=100
SW05=40
SW04=20
SW03=10
SW02=4

Sw01=2
Sw00=1

:=1,HALT ON ERROR
:=1,L00P _ON CURRENT TEST
;=1,INHIBIT ERROR TYPEOUT
;=1,INHIBIT ITERATIONS
:=1,ESCAPE TO NEXT TEST ON ERROR
:=1.L00P WITH CURRENT DATA

sRESTART PROGRAM AT SELECTED TEST
sRESELECT VECTOR AND CONTROL REGISTER
sADDRESS AFTER PROGRAM RESTART

CZDHA-C MACY11 30A(1052)

CZDHAC.P11

15-MAY-78

23-AUG-78

10:02

14:40

PAGE 3

SEQ 0013

2‘12

sREGISTER DEF INITIONS

43
44
45
4“6

000000
000001
000002
000003

RO=%0
R1=X1
RZ=I§
R3=X

48
49
g?

000005
002006
000007

R5=%5
SP=%6
PC=%7

000004

sGENERAL REGISTER

:PROCESSOR STACK POINTER
;PROGRAM COUNTER

;LOCATION EQUIVALENCIES
_

177570

SWR=177570

177570

LIGHTS=177570.

177776

PS=177776

021360

s CONSOLE SWITCH REGISTER

:PDP=11/45 DISPLAY REGISTER

;PROCESSOR STATUS WORD

STACK=EWC(D*200: START OF PROCESSOR STACK

61
62

sGENERAL REGISTER

s INSTRUCTION DEFINITIONS

005746
005726
010046

PUSH1SP=5746
POP1SP=5726
PUSHRO0=10046

sSAVE RO ON STACK

024646

PUSH2SP=24646

;DECREMENT STACK TWICE

[

66
gg
69

71
72
73

012600

POPR0=12600

022626

010000

004000

B1T15=100000

BIT14=40000
B81713=20000

B81T12=10000

B1T11=4000

002000

B81710=2000

000400

B81T708=400

000100

BIT06=100

81
82
83
84

000020
000010
000004
000002

BI1T04=20
BIT03=10
BIT02=4
BIT01=2

001000

000200
000040

000001

sRESTORE RO FROM STACK

POP2SP=22626
s INCREMENT STACK TWICE
LEQUIV EMT_HLT- BASIC DEFINITION OF ERROR CALL

100000

040000
020000

sDECREMENT PROCESSOR STACK 1 WORD
+ INCREMENT PROCESSOR STACK 1 WORD

BIT09=1000

BIT07=200

BIT05=40

BIT00=1

sGENERAL REGISTER

R&4=%4

g%
54

sGENERAL REGISTER

:GENERAL REGISTER
sGENERAL REGISTER

5 orvpin ol L
CZOMA=C MACY11

86
87
88
89
90
91
%

93
9
95
9%
97
98
%
100
101
102
103
106
105
106
107
108
109
110
111
112
113
114
115

000000
000002
000004
000006
900010

000000
000002
000000
000006
000000
000012

14:40

.=0

PAGE 4

.#2
i
i

HALT

121

AL T

122

000100

000102

000104

000026

000072
000000
000076

000102

000000

000106

123 000106 000000

124
125

126

127
128
129
130
131
132
133
13%
135
136
137
138
139
120
141

000110
000112

000114

000116
000120
000122
000124
000126
000130
000132
000134
000136
000140
000142
000144
000146
000150
000152

000112
000000

000116

000000
000122
000000
000126
000000
000132
000000
000136
000000
000142
000000
000146
000000
000152
000000

;UNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
UNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
[UNEXPECTED TRAP TO. THIS LOCAT ION

119 000076 000000

120

000022

:TRAPCATCAER FOR ILLEGAL INTERRUPTS

000000
000032
000000
000036
000000
000042
000000
000046
000000
000052
000000
000056
000000
000062
000000
000066
000000

000070
000072
000074

000000
000016
000000

10:02

23-AUG-78

AL T
.42
HAL T
o
HAL T
.42
HAL T
42
HALT
42
HALT
.42
HALT
42
AL T
.42
AL T
.42
HALT
.42
HALT
.42
HALT

116
117
118

000012
000014
000016
000020
000022
000026
000026
000030
000032
000034
000036
000040
000042
000044
000046
000050
000052
000054
000056
000060
000062
000064
000066

30A(1052)

TEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
TEXAMINE STACK TC FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
TEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION

TEXAMINE STACK TO FIND CAUSE
UNEXPECTED TRAP TO THIS LOCATION
*EXAMINE STACK TO FIND CAUSE
*UNEXPECTED TRAP TO THIS LOCATION
*EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION

"EXAMINE STACK TO FIND CAUSE
SUNEXPEZTED TRAP TO THIS LOCATION
*EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
TEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
TEXAMINE STACK TO FIND CAUSE
*UNEXPECTED TRAP TO THIS LOCATION
"EXAMINE STACK TO FIND CAUSE

42
AL T
42

*UNEXPECTED TRAP TO THIS LOCATION
*EXAMINE STACK TO FIND CAUSE
*UNEXPECTED TRAP TO THIS LOCATION

*UNEXPECTED TRAP TO THIS LOCATION

SUNEXPECTED TRAP TO THIS LOCATION

42
AL T

SUNEXPECTED TRAP TO THIS LOCATION
*EXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION

TEXAMINE STACK TO FIND CAUSE

HALT
.40

HALT
.42
HALT
40
FALT
2
HAL T
A
HAL T
+2
HALT
+2
HALT
.42
HALT

"EXAMINE STACK TO FIND CAUSE

*EXAMINE STACK TO FIND CAUSE
TEXAMINE STACK TO FIND CAUSE
*UNEXPECTED TRAP TO THIS LOCATION
*EXAMINE STACK TO FIND CAUSE
*UNEXPECTED TRAP TO THIS LOCATION
TEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
*EXAMINE STACK TO FIND CAUSE
*UNEXPECTED TRAP TO THIS LOCATION
"EXAMINE STACK TO FIND CAUSE
*UNEXPECTED TRAP TO THIS LOCATION
"EXAMINE STACK TO FIND CAUSE

*UNEXPECTED TRAP TO THIS LOCATION

*UNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE

SEQ 0014

CZDHA=C MACY11 30A(1052)
23-AUG-78
10:02
CZDHAC.P1
15-MAY-

000166

000172

000176
000000

YRS Y
T
T

JUNEXPECTED TRAP TO THIS LOCATION

;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
EXMI'f STACK TO FIND CAUSE

UNEXPECTED TRAP TO THIS LOCATION

EXMIM STACK TO FIND CAUSE
;UNEXPECTED TRAP TO THIS LOCATION
:EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TC FIND CAUSE
;UNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
;UNEXPECTED TRAP TO THIS LOCATION

D
D —d

D —d

SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION

000000
000312
000000
000316
(00000
000322
002000
000326
000000
000332
000000

;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE

SUNEXPECTED TRAP TO THIS LOCATION

:EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE

:EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION

) —d —d —d

CRERE

SEQ 0015

:EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
"JUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE

D
D —d
)
D
d
d
b e
—

PAGE S

000162

S Y

2B BB IR RRRT 2B IS I NANYITEIEAR GRZBEBIENRUR2EGEIE H

144

000156

14:40

000342

000346
000352
000356
000362

000372
000376
000402
000406
000412

14:40

PAGE 6
.42

HALT

.42

HALT

HALT
HALT
HALT

HALT

HALT
HALT
HALT

.42

HALT

.42

HALT
+

219

000336

g
3

b o
b
)
b
b
b
b
D

ONONSWN=O

NN
NN NN

CESEEE
T

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P1
15-MAY=7 10:02

SEQ 0016
SUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
;UNEXPECTED TRAP TO THIS LOCATION
:EXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE

;UNEXPECTED TRAP TO THIS LOCATION
:EXAMINE STACK TC FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATICN
SEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION

:EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO TH"5 LOCATION
sEXAMINE STACK TO FINC CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION

sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
:EXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION

;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
UNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE

23 AP RERIFIIVIININIIERLFEXARLEIILIAY

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P1
15-MAY-78
1

000516

000522
000526

000532
000536
000542
000546

000552

000556
000562

000566
000572

000576
000602
000606
000612

000616

000622
000626

000632

14:40

PAGE 7

SEQ 0017

sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TC FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION

:EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION

;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE

sUNEXPECTED TRAP TO THIS LOCATION
:EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
;UNEXPECTED TRAP TO THIS LOCATION
"EXAMINE STACK TO FIND CAUSE
LUNEXPECTED TRAP TO THIS LOCATION
:EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION

;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE

pety

SEERRIRRRKE

b culh

s el cilh

WWWWWWWWW W

CZDHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC.PN

000674

000676
000000
000702
000000
000706
000000
000712
000000
000716
000000
000722
000000
000726
000000
000732
000000
000736
000000
000742
000000
000746
000000
000752
000000
000756
000000
000762
000000
000766
000000
000772
000000
000776
000000

14:40

PAGE 8

HALT

o«

HALT
HALT

HALT

T
HAL

HAL
T

.+2

HALT
HALT
HALT

SEQ 0018

JUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TC FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION

:EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

4
345
346
U7
348
349
350
351
352
353

000024
000026
000030
32
34
000036

355

000200

SEQ 0019

000024
017752
000340
016616
000
017020
000340
00

000167

PFAIL

;POWER FAIL HANDLER

340

ERRORS

;SERVICE AT LEVEL 7
:ERROR HANDLER

TRPSRV

;GENERAL HANDLER DISPATCH SERVICE

340

000574

.=200

:SERVICE AT LEVEL 7

340

JMP

;SERVICE AT LEVEL 7

START

;GO TO START OF PROGRAM

;DEFINITIONS FOR TRAP SUBROUTINE CALLS
;POINTERS TO SUBROUTINES CAN BE FOUND STARTING

;AT LOCATION '‘TRPTAB''

363
364
365

104400
104401
104402

SCOPE=TRAP+Y
TYPE=TRAP+Y

OCTASC=TRAP+Y
INSTR=TRAP+Y
INSTER=TRAP+Y
PARAM=TRAP+Y
SAVO5P=TRAP+Y
RESO5=TRAP+Y
SCOPE1=TRAP+Y

104403

367

104404

104405

369

375

PAGE 9
s STANDARD INTERRUPT VECTORS

357
358
359
360
361
362

370
371
372
373
374

14:40

104406

000046
000052

104407
104410
000046
016464
000052
040000

LOGI CAL

=52

40000

sSCOPE LOOP AND ITERATION HANDLER

;TELETYPE OUTPUT ROUT INE

sOCTAL TO ASCII CONVERSION
s INPUT ASCII STRING
sSTRING INPUT ERROR

;CONVERT STRING TO OCTAL, CHECK LIMITS

;SAVE RO-R5, PC
;RESTORE RO-R5
;CHECK FOR FREEZE ON CURRENT DATA

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=-78 10:02

g;;

14:40

001000

PAGE 10

.=1000

378
379
380
381
382
383
385

387
388
389
390
391
392
293
394
395
396
397

;PROGRAM INITIALIZATION
:LOCK OUT INTERRUPTS
:SET UP PROCESSOR STACK
*SET UP POWER FAIL VECTOR
*CLEAR PROGRAM FLAGS AND COUNTS
*TYPE TITLE MESSAGE
001000
001006
001012
001020
001024
001030
001034
001040
001044
001050
001054

001056

012767
012706
012737
005067
005067
005067
005067
005067
104401
005767
001001

000404

000340
021360
017752
016722
016656
016654
016644
016640
020116
016670

398

001060

032767

000001

400
401

001070
001074

012701
012702

000300
000302

403
404

001104
001106

010211
005012

399

402

405

406

407

408

409
410
411
412
413
414

415

416
417
418
419
420

421
422
423
424
425
426
427
428
429
431

SEQ 0020

001066

001100

001110

001112

001445

012703

020127

001122
001124
001126
001130
001132
001134

104403
020153
104405
000300
000770
017674

001137
001140
001142
001144
001146

004
104403
020175
104405
000000

001136

001150
001152
001154
001155
001156
001164
001170
001174
001176

START:

000024

176502

000004

VEC1:

001371

BIT

BEQ

BEGIN

1$:

MOV
CLR

R2. (R1)
(R2)

MOV

ADD

CMP

BNE

BYTE

016506

VEC2

#SWO00, SWR

#300.R1
#302.R2

001000

016506
016502
016550

#340,PS
#STACK , SP
#PF A IL . a4
STFLG
PASCNT
ERRCNT
ERRFLG
ERRFLG
JMTITLE
INIFLG
VECT

MOV
MOV-

ADD

003

177776
017652
007
010
016767
005267
005767
001002
005167

MOV
MOV
MOV
CLR
CLR
CLR
CLR
CLR
TYPE
TST
BNE

VEC2:

060301

060302

001114

001120

176770

BYTE
BYTE

016542

INSTR
MVECTOR
PARAM
300
770
DHRVE (

#4 RS

R3,R1

; IF suoo- GET NEW VECTOR
SAND
C

:RESTORE TRAPCATCHER
*IN FLOATING VECTOR AREA

R3.R2

R1 #1000

: INPUT ADDRESS OF DEVICE VECTOR
*MESSAGE 'VECTOR ADDRESS-'"
:CONVERT STRING TO OCTAL
SLOW LIMIT
SHIGH LIMIT
*LOCATIONS TO BE FILLED

»uaenor LOCATIONS

&
INSTR
MRE GAD
PARAM
0

177776
DHS’R
7
10
MOV
INC
ST
BNE
coM

;LOCK OUT INTERRUPTS
“SET UP PROCESSOR STACK
*SET UP POWER FAIL TRAP
“CLEAR TEST START FLAG
*CLEAR PASS COUNT
*CLEAR ERROR COUNT
:CLEAR ERROR FLAG
*CLEAR LAST ERROR PC
STYPE TITLE MESSAGE
:CHECK INITIALIZATION FLAG
<IF NOT 0, CHECK SWITCHES
*FOR REINITIALIZATION

DHSSR, DHSLR
DHSLR
INIFLG
BEGIN
INIFLG

;PROGRAM START

:LSB MASK
: INPUT ADDRESS OF DEVICE (SR
*MESSAGE ‘‘'CONTROL REGISTER ADDRESS='"
*CONVERT STRING TO OCTAL
SLOW LIMIT
SHIGH LIMIT
*LOCATIONS TO BE FILLED
NUHBER OF LOCATIONS
-LSB MASK
ssr UP ADDRESS OF SILO
*STATUS REGISTER HIGH BYTE
“IF INITIALIZATION FLAG
*15 CLEARED
SSET IT

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=78 10:02

14:40

PAGE 11

32
434
435
436
437
438
439
440
441
42
43

444
445
446
447
448
449
450
451
452

SEQ 0021

;CHECK FOR PROGRAM START AT SELECTED ADDRESS
001202
001210
001214
001222
001206
001226
001230
001232
001234
001236

001240
0012641
001262
001244
001252
001256
001260
001264
001270

012767
019706
032767
001410
104403
020343
104405
000000
017500
017712

001
001
000410
012767
005767
001004
005167
104401
000177

000340
021360
000002

176566

BEGIN:

176346

BYTE
BYTE
001274
016470

016462
020337
016416

016440

1$:

28:
3%:

MOV
MOV
BIT
BEQ_
INSTR
MTSTPC
PARAM
0
17500
RETRN

1
]
BR
MOV
ST
BNE
oM
TYPE
JMP

#340,PS
WSTACK,SP
#SW0T,SWR
18

28
#T1,RETRN
STFLG
38
STLG
MR
aRETRN

:LOCK OUT INTERRUPTS
:SET_UP PROCESSOR STACK
:1F_sw01=1
:GET PC FOR PROGRAM START
:GET PC
o
:MESSAGE *TEST PC
:CONVERT STRING TO OCTAL

;NORMAL START, TEST
1
:1F LOOPING, BYPASS TYPEOUT
:TYPE "R'* TO INDICATE START
;START TESTING

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

453
454
455
456
Z.gg

012767
012767
012767
012737
012737
005777

466

001336

000406

468 001340

016705

016306

469

001344

471

001346

012716

001354

473
476
2;2

001354
001362
001366

012737
005037
104400

000006
000006

470

472

001352

104000

000340
000100
001346
001340
000340
016314

000002

PAGE 12

SEQ 0022

:DH11 SYSTEM CONTROL REGISTER ADDRESSING TEST
:VERIFY THAT DH11 SYSTEM CONTROL REGISTER RESPONDS TO ADDRESSING
:IF DH11 SYSTEM CONTROL REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP
*WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.

459 001274
460 001302
461 001310
462 001316
463 001326
":.2‘% 001332

467

14:40

176474
016410
016376
000004
000006

000004

T1:

MOV
MOV
MOV
MOV
MOV
ST

#340,PS
#7100, I COUNT
#28 ,ESCAPE
1S ans
#3640, an6
aDHSCR

:DISABLE ALL INTERRUPTS
*SET UP FOR 100 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
“SET UP TIME OUT TRAP

B8R

:NO TRAP, REGISTER RESPONDS

1$:

MOV

DHSCR,RS

*REGISTER DID NOT RESPOND

28:

MOV

#3$, (SP)

3$:

MOV
CLR
SCOPE

"6, N6
anb

HLT
RTI

;ADDRESS gfgé}ssgsren CONTROL

*TO ADDRESSING

*TIME OUT TRAP, DH11 SYSTEM CONTROL
*REGISTER DID NOT RESPOND

*SET UP TO RETURN FROM TRAP
:

*RETURN FROM TRAP

:RESTORE TRAP CATCHER
*CHECK FOR ITERATIONS, LOOP

477

:DH11 NEXT RECEIVED CHARACTER REGISTER ADDRESSING TEST

479

ADDRESSING
*IF DH11 NEXT RECEIVED CHARACTER REGISTER DOES NOT RESPOND. A BUSS
ERROR TRAP

478

:VERIFY THAT DH11 NEXT RECEIVED CHARACTER REGISTER RESPONDS TO

41'3(1)

‘WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.

482
483
484
485
486
2%

001370
001376
001404
001412
001420
001426

012767
012767
012767
012737
012737
005777

489

001432

000406

491

001434

016705

016214

001442

012716

001450

012737

000006

490
492
493

001440

495

001446

497

001456

496

233

001462

104000

000002

005037

104400

000340
000100
001442
001434
000340
016222

000006

5GO
501
502

5582

505 001464
506 001472
507 001500
508 001506

176400
016314
016302
000004
000006

000004

T2:

MOV
MOV
MOV
MOV
MOV
ST

#340,PS
#100, 1 COUNT
#2$ ,ESCAPE
1S s
#340, w6
ADHNRC

:ADDRESS ggé} neExr RECEIVED CHARACTER

:NO TRAP, REGISTER RESPONDS

1$:

MOV

DHARC ,RS

*REGISTER DID NOT RESPOND

2%:

MOV

#38, (SP)

*SET UP TO RETURN FROM TRAP

3$:

MOV

000340
000100
001536
001530

RT]

CLR

SCOPE

176304
016220
016206
000004

*TO ADDRESSING

STIME OUT TRAP. DH11 NEXT RECEIVED CHARACTER
*REGISTER DID NOT RESPOND

*RETURN FROM TRAP

;RESTORE TRAP CATCHER

*CHECK FOR ITERATIONS, LOOP

:DH 11 LINE PARAMETER REGISTER ADDRESSING TEST
SVERIFY THAT DH 11 LINE PARAMETER REGISTER RESPONDS TO ADDRESSING
:IF DH 11 LINE PARAMETER REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP

012767
012767
012767
012737

HLT

:DISABLE ALL INTERRUPTS
*SET UP FOR 100 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*SET UP TIME OUT TRAP

:WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.

T3:

MOV
MOV
MOV
MOV

#340,PS
#100. 1 COUNT
#2%, ESCAPE
218 and

:DISABLE ALL INTERRUPTS
*SET UP FOR 100
ITERATIONS
“SET UP TO ESCAPE TO NEXT TEST
*SET UP TIME OUT TRAP

CZDHA=C MACY11 30A(1052) 02(3)5%78
CZDHAC.P11
15-MAY-78 1

509 001514
g}? 001522

012737 000340
005777 016130

512

001526

000406

§14

001530

016705

016122

517 001536 012716

001544

519 001544

012737

000006

gg}

104400

513

515
516

001534

518

001542

520

001552

001556

104000

000002

005037

000006

14:40

000006

000004

PAGE 13

SEQ 0023

MOV
ST

#340, 46
aDHLPR

;ADDRESS gfum;}eku PARAME TER

;NO TRAP,

1%:

MOV

DHLPR,RS

*REGISTER DID NOT RESPOND

2s.

MOV

#38, (SP)

3$:

MOV

"6, NG

HLT

RTI

CLR

SCOPE

:TO ADDRESSING

STIME OUT TRAP, DH 11 LINE PARAMETER
*REGISTER DID NOT RESPOND

*SET UP TO RETURN FROM TRAP
*RETURN FROM TRAP

:RESTORE TRAP CATCHER

*CHECK FOR ITERATIONS, LOOP

5§23

:DH11 BUS ADDRESS REGISTER ADDRESSING TEST

ggg

‘WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.

524
525

:VERIFY THAT DH11 BUS ADDRESS REGISTER RESPONDS TO ADDRESSING
:1F DH11 BUS ADDRESS REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP

528
529
530
531
532
g_;’z

001560 012767
001566 012767
001574 012767
001602 012737
001610 012737
001616 005777

535

001622

000406

537 001624

016705

016030

540

001632

012716

001640

012737

000006

536

538
539

001630

541

001636

543

001646

542

sszzs.

001652

104000

000002

005037

104400

000340
000100
001632
001624
000340
016036

000006

176210
016124
016112
000004
000006

000004

Té:

MOV
MOV
MOV
MOV
MOV
ST

#340,PS
:
#100, 1 COUNT
#2$ ,ESCAPE
21 s
#340, a6
aDHBA

:DISABLE ALL INTERRUPTS
*SET UP FOR 100 ITERATIONS
“SET UP TO ESCAPE TO NEXT TEST
*SET UP TIME OUT TRAP

B8R

:NO TRAP, REGISTER RESPONDS

1$:

MOV
HLT

DHBA RS

28:

MOV

#38, (SP)

3$:

MOV

w6, MG

RTI

CLR

SCOPE

546
547
548

012767
012767
012767
012737
012737
005777

558

001716

000406

560 001720

015705

015736

1$:

MOV
HLT

012716

001734

28:

MOV

#>%, (SP)

561

001724

563

001726

564

*TO ADDRESSING

;REGISTER DID NOT RESPOND

;TIME OUT TRAP, DH11 BUS ADDRESS
*REGISTER DID NOT RESPOND

*SET UP TO RETURN FROM TRAP
*RETURN FROM TRAP

;RESTORE TRAP CATCHER

:CHECK FOR ITERATIONS, LOOP

:WILL OCCUR, AND AN ERROP MESSAGE WILL BE TYPED.

§51 001654
552 001662
553 001670
554 001676
§55 001704
ggg 001712

562

;ADDRESS 2’;‘&}5?‘5’3 ADDRESS

:DH11 BYTE COUNT REGISTER ADDRESSING TEST
*VERIFY THAT DH11 BYTE COUNT REGISTER RESPONDS TO ADDRESSING
:IF DH11 BYTE COUNT REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP

Ssgg

559

001732

104000

000002

000340
000100
001726
001720
000340
015744

176114
016030
016016
000004
000006

T5:

MOV
MOV
MOV
MOV
MOV
ST

#340,PS
#100, I COUNT
#28 ,ESCAPE
18 ans
#340, a6
abHB(

;DISABLE ALL INTERRUPTS
*SET UP FOR 10
ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*SET UP TIME OUT TRAP

B8R

:NO TRAP,

RTI

DHBC RS

:ADDRESS giué}s?gs COUNT

-TO ADDRESS ING

;REGISTER DID NOT RESPOND

;TIME OUT TRAP, DH11 BYTE COUNT

*REGISTER DID NOT RESPOND

*SET UP TO RETURN FROM TRAP
*RETURN FROM TRAP

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78
10:02

565

566

ssgg

001734

001742

001746

012737 000006

005037

104400

000006

14:40

000004

3$:

581

002012

000406

583

002014

016705

586

002020

104000

012716

002030

588 002030
589 002036
gg? 002042

012737
005037
104400

000006
000006

002026

000002

176020
015734
015722
000004
000006

015646

002022

587

#6, N4
b

:RESTORE TRAP CATCHER

*CHECK FOR ITERATIONS, LOOP

:IF DH11 BREAK CONTROL REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP
:WILL OCCUR. AND AN ERROR MESSAGE WILL BE TYPED.

§74 001750 012767 000340
575 001756 012767 000100
576 001764 012767 002022
§77 001772 012737 002014
578 002000 012737 000340
ggg 002006 005777 015654

585

CLR

SEQ 0024

:DH11 BREAK CONTROL REGISTER ADDRESSING TEST
*VERIFY THAT DH11 BREAK CONTROL REGISTER RESPONDS TO ADDRESSING

571
g;g

584

MOV
SCOPE

569
570

582

PAGE 14

T6:

1$:

000004

MOV
MOV
MOV
MOV
MOV
ST

#340,PS
#100, 1 COUNT
m ESCAPE
1S s
#340,a46
aDHBCR

B8R

MOV

DHBCR.RS

HLT

28:

MOV

#38, (SP)

3$:

MOV
CLR
SCOPE

n6, NG
Y73

RTI

:DISABLE ALL INTERRUPTS
*SET UP FOR 100 ITERATIONS
“SET UP TO ESCAPE TO NEXT TEST
*SET UP TIME OUT TRAP
:ADDRESS 32(1; }s?gsm CONTROL

:NO TRAP, REGISTER RESPONDS

“TO ADDRESSING

nscxsrsn DID NOT RESPOND

TIME OUT TRAP, DH11 BREAK CONTROL

*REGISTER DID NOT RESPOND

*SET UP TO RETURN FROM TRAP

*RETURN FROM TRAP

;RESTORE TRAP CATCHER
*CHECK FOR ITERATIONS, LOOP

5§92

;BUS ACTIVE REGISTER ADDRESSING TEST

59¢,

*IF BUS ACTIVE REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP

593

:VERIFY THAT BUS ACTIVE REGISTER RESPONDS TO ADDRESSING

‘WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.

597
598
599
600
601
g(o)%

002044 012767 000340
002052 012767 000100
002060 012767 002116
002066 012737 002110
002076 012737 000340
002102 005777 015556

604

002106

000406

606

002110

016705

605

607

608

002114

104000

015550

609

002116

012716

002124

611
612
g}z

002126
002132
002136

012737
005037
104400

000006
000006

610

002122

000002

175724
015640
015626
000004
000006

17:

1$:

000004

#340,PS
#100. 1 COUNT
#2$ ,ESCAPE
218 ans
#3400, ax6
aDHBAR

B8R

MOV

DHBAR RS

HLT

28:

MOV

#38,(SP)

3$:

MOV
CLR
SCOPE

#6, NG
a#b

615
616
617
2}3
620

MOV
MOV
MOV
MOV
MOV
ST

RTI

:DISABLE ALL INTERRUPTS
*SET UP FOR 100 ITERATIONS
“SET UP TO ESCAPE TO NEXT TEST
*SET UP TIME OUT TRAP
;ADDRESS 2‘5’212%{"‘

:NO TRAP, REGISTER RESPONDS

*TO ADDRESSING

*REGISTER DID NOT RESPOND

*TIME OUT TRAP, BUS ACTIVE

*REGISTER DID NOT RESPOND

*SET UP TO RETURN FROM TRAP

*RETURN FROM TRAP

;RESTORE TRAP CATCHER
*CHECK FOR ITERATIONS, LOOP

;SILO STATUS REGISTER ADDRESSING TEST
:VERIFY THAT SILO STATUS REGISTER RESPONDS TO ADDRESSING

:JF SILO STATUS REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP
*WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.
002140

012767

000340

175630

T10:

MOV

#340,PS

:DISABLE ALL INTERRUPTS

CZDHA-C MACY11 30A(1052)

CZDHAC.P11

23-AUG-78

15-MAY=78

10:02

ooo1og
002212
002204
000340
015466

14:40

SEQ 0025

621
622
623
624
g%g

002146
0021564
002162
002170
002176

012767
012767
012737
012737
005777

627

002202

000406

629 002204

016705

015460

1%:

MOV
HLT

2s:

MOV

#3$, (SP)

3$:

MOV

#5, N6

628
630

002210

csg

002212

012716

002220

636

002220

012737

000006

631
633

635

002216

(002226

002232

104000

000002
005037

104400

000006

015544
015532
000004
000006

PAGE 15

000004

638

654

002234

012767

012767
012767
012777

002264
002272

052777
017704

002276

002300

175534

004000
002312
173777

015450
015436
015366

004000
015354

015360

T11:

MOV

MOV
MOV
MOV

:TIME OUT TRAP, SILO STATUS

*REGISTER DID NOT RESPOND

*SET UP TO RETURN FROM TRAP
*RETURN FROM TRAP

:RESTORE TRAP CATCHER

:CHECK FOR ITERATIONS, LOOP

#340,PS

#4000, 1COUNT
#1$,ESCAPE
#178777 ,aDHSCR

001404

BEQ

002304

016703

002312

104400

002310

000340

657

104005

01°

42
1$:

CLR

MOV

DHSCR,R3

HLT

SCOPE

:DISABLE ALL INTERRUPTS

:SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
.-%11;;;;;'1 CONTROL REGISTER
:ISSUE MASTER CLEAR
:(R6)=ACTUAL DATA IN

:SYSTEM CONTROL REGISTER
:VERIFY THAT SYSTEM CONTROL REGISTER
:WAS CLEARED
: (RS)=EXPECTED DATA IN

:SYSTEM CONTROL REGISTER, 0

:GET REGISTER ADDRESS

:MASTER CLEAR FAILED

:CHECK FOR ITERATIONS, LOOP

661

JMASTER CLEAR TEST

ggg

:VERIFY THAT LINE PARAMETER WAS CLEARED

662
663

*SET LINE PARAMETER REGISTER TO 'CDATA'
*ISSUE MASTER CLEAR

666

002314

671

002344

667
668
2678

672

673
674
675
676

:REGISTER DID NOT RESPOND

005704
005005

223

CLR

#BIT11,aDHSCR
aDHSCR . R4

002302

658

RTI

:NO TRAP,

*TO ADDRESSING

DHSSR,RS

BIS
MOV

655

656

sADDRESS gé%?s%aws

JVERIFY THAT SYSTEM CONTROL WAS CLEARED

645 002242
646 002250
22; 002256
651
652
653

:SET UP FOR 100 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
:SET UP TIME OUT TRAP

:MASTER CLEAR TEST
:SET SYSTEM CONTROL REGISTER TO °'CDATA®
:ISSUE MASTER CLEAR

g‘o‘g

649
650

#100, I COUNT
#2$ ,ESCAPE
S an
#340,a#6
aDHSSR

SCOPE

639
640
641
644

MOV
MOV
MOV
MOV
ST

002322
002330
002336

012767

012767
012767
012777
052777

000340

175454

004000
09;3;;
177777

015370
015356
015312

004000

015300

T12:

MOV

MOV
MOV
MOV

:DISABLE ALL INTERRUPTS

#4000, 1COUNT
s ;;gme
#177777
,aDHLPR

:SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
;;511”7 7pmren REGISTER

MOV

aDHLPR .R4

#81T11,aDHSCR

*ISSUE MASTER CLEAR

005704

001404

BEQ

:LINE PARAMETER REGISTER
:VERIFY THAT LINE PARAMETER REGISTER
;WAS CLEARED

002352

017704

002356

002360

015300

BIS

#340,PS

:(R4)=ACTUAL DATA IN

CZDHA=C MACY11 30A(1052)

CZDHAC.P1

002362

005005

679

002364

016703

gg;

002372

104400

680

14:40

15-MAY-78 10:02

677

678

23-AUG-78

002370

104005

015266

1$:

683
684
685
002374

012767

000340

690
235

002410
002416

693
694
696
697

698

002402

175374

#18
#177777

:SET UP TO ESCAPE TO NEXT TEST
:gsr#a;m CONTROL REGISTER

015220

BiS
MOV

#8I1T11,3DHSCR
aDHBCR R4

;1SSUE MASTER CLEAR
;(R4)=ACTUAL DATA IN

005704

TST

Ré

BEQ

:VERIFY THAT BREAK CONTROL REGISTER
;WAS CLEARED

002424
002432

052777
017704

004000
015230

002436

002444

016703

77?)2

002452

104400

002450

T13:

005005

104005

015216
1$:

705
706
707
002454

012767

000340

71¢

002470

012767

002536

002462

002476

012767
012777

015230

100077

015164

002504

002512

052777
017704

004000
015152

718

002516

042704

077700

721

72
724

725
;229

728
729
730
731
732

002522

002524

005704

001404

002526

005005

530

016703

002534
002536

104005
104400

175314

004000

715
716

72%

#4000, 1 COUNT

_ESCAPE
,aDHBCR

CLR

MOV

DHBCR,R3

HLT

SCOPE

;SET UP FOR 4

INTERRUPTS

ITERATIONS

;BREAK CONTROL REGISTER
. (RS)=EXPECTED DATA IN

:BREAK CONTROL REGISTER, 0

:GET REGISTER ADDRESS

;MASTER CLEAR FAILED

;CHECK FOR ITERATIONS, LOOP

JVERIFY THAT SILO STATUS WAS CLEARED

710

719

MOV

;MASTER CLEAR TEST
sSET SILO STATUS REGISTER TO °'CDATA®
;1SSUE MASTER CLEAR

720

JCHECK FOR ITERATIONS, LOOP

MOV
MOV

002452
177777

701

717

:GET REGISTER ADDRESS

JMASTER CLEAR FAILED

015276
015242

012767
012777

001404

;LINE PARAMETER REGISTER, 0

;DISABLE ALL

015310

002440

711

DHLPR,R3

: (RS)=EXPECTED DATA IN

#340,PS

004000

002442

702

MOV

SCOPE

MOV

012767

699

700

sVERIFY THAT BREAK CONTROL WAS CLEARED

688

695

SEQ 0026

CLR
HLT

:MASTER CLEAR TEST
;SET BREAK CONTROL REGISTER TO °‘CDATA'
:1SSUE MASTER CLEAR

689

PAGE 16

T14:

015216

MOV

1%:

#B1T11,3DHSCR

:ISSUE MASTER CLEAR

MOV

aDHSSR R4

BIC

#77700,R4

BEQ

sSET UP TO ESCAPE TO NEXT TEST

#100077,3DHSSR

TST

015134

#18 ESCAPE

mov :

BIS

:DISABLE ALL INTERRUPTS

#4000, 1COUNT

MOV

015140

#340,PS

MOV

Ré

CLR

MOV

DHSSR,R3

HLT
SCOPE

:SET UP FOR 4000 ITERATIONS
:§5713&97surus REGISTER

:(R4)=ACTUAL DATA IN

;SILO STATUS REGISTER

;CLEAR UNWANTED BITS

;VERIFY THAT SILO STATUS REGISTER

:WAS CLEARED

: (RS)=EXPECTED DATA IN

:SILO STATUS REGISTER, 0
:GET REGISTER ADDRESS

:MASTER CLEAR FAILED
;CHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
JSET LINE SELECT BIT O IN SYSTEM CONTROL REGISTER
JVERIFY THAT LINE SELECT BIT 0 WAS SET
JCLEAR LIwE SELECT BIT 0
JVERITY THAT LINE SELECT BIT O WAS CLEARED

CZDHA=C MACY11 30A(105 )102(3)5%78
CIDMAC.P11
15-MAY-

733
73,

002540

012767

000340

757

002562

016703

015064

739
7640

002572
002576

022713
001404

000001

14:40

175230

;gz 885546 012767 004000 015144
556 012767 002624 015132
738 002566 012713

741

T15:

PAGE 17

MOV

MOV
MOV

MOV

000001

MOV

000001

MOV

CMP
BEQ

SEQ 0027

#340,PS

:DISABLE ALL

DHSCR ,R3

sPUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3

#4000, 1COUNT
#28 ESCAPE
#1100, (R3)

#8I1T00, (R3)
1%

002600

012705

002604

011304

MOV

(R3) ,R4

002606

104001

HLT

7648
749
750

002610
002614
002616

042713
001403
005005

BIC
BEQ
CLR

#BIT00, (R3)
2%
RS

752

002620

011304

MOV

(R3) R4

754

002622

104001

HLT

7729

002624

104400

742
743
7644
745
746
747

751

753
755

000001

1%:

2%:

758
759

#ITO00,RS

“SET LINE SELECT ZIT 0

JVERIFY THAT LINE SELECT BIT 0O WAS SET
;(RS)= EXPECTED VALUE

;IN SYSTEM CONTROL REGISTER
;LINE SELECT BIT 0
;(R4)=ACTUAL DATA IN
*SYSTEM CONTROL REGISTER
;SYSTEM CONTROL REGISTER
JWRITE/READ ERROR
JCLEAR LINE SELECT BIT O

: (RS)=EXPECTED DATA IN

;SYSTEM CONTROL REGISTER, O
J(R4)=ACTUAL DATA IN

;SYSTEM CONTROL REGISTER

:SYSTEM CONTROL REGISTER
JWRITE/READ ERROR

SCOPE

JCHECK FOR ITERATIONS, LOOP

JSYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
JSET LINE SELECT BIT 1 IN SYSTEM CONTROL REGISTER

760

JVERIFY THAT LINE SELECT BIT 1 WAS SET

;g%

sVERITY THAT LINE SELECT BIT 1 WAS CLEARED

761

sCLEAR LINE SELECT BIT 1

764

002626

012767

000340

766
767

002642
002650

012767
016703

002712
014776

765

768

769
770

002634

002654

002660
002664

012767

012713

022713
001404

004000

175142

015056

T1i6:

015044

MOV

#340,PS

;DISABLE ALL INTERRUPTS

MOV
MOV

#2% ,ESCAPE
DHSCR,R3

JSET UP TO ESCAPE TO NEXT TEST
sPUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3

MOV

#4006.ICOLNT

MOV

081701.(!?3)

JSET LINE SELECT BIT 1

000002

MOV

#BITO1,RS

; (RS)= EXPECTED VALUE

CMP
BEQ

#BI1T01, (R3)
1%

002666

012705

774

002672

011304

MOV

(R3) ,R4

776

002674

104001

HLT

002676

042713

BIC

#81T01, (R3)

775

177

778

000002

1$:

779
780

002702
002704

001403
005005

782

002706

011304

MOV

(R3) R4

78,

002710

104001

HLT

7739

002712

104400

781

783

785

788

;SET UP FOR 4000 ITERATIONS

000002

771

772
773

INTERRUPTS

*SET UP FOR 4000
ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST

2%:

BEQ
CLR

SCOPE

2%
RS

JVERIFY THAT LINE SELECT BIT 1 WAS SET

sIN SYSTEM CONTROL REGISTER
sLINE SELECT BIT 1
;s (R4)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER

;SYSTEM CONTROL REGISTER

JWRITE/READ ERROR

*CLEAR LINE SELECT BIT 1
; (RS)=EXPECTED DATA IN

JSYSTEM CONTROL REGISTER, O
; (R4)=ACTUAL DATA IN

JSYSTEM CONTROL REGISTER

*SYSTEM CONTROL REGISTER

;WRITE/READ ERROR

*CHECK FOR ITERATIONS, LOOP

JSYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)

CZDHA-C MACY11 30A(1052)

CZDHAC.PN

23-AUG-78
10:02

14:40

15-MAY-78

824
825
826
827

828
829
83C
831
83%

SEQ 0028

;SET LINE SELECT BIT 2 IN SYSTEM CONTROL REGISTER
*VERIFY THAT LINE SELECT BIT 2 WAS SET
*CLEAR LINE SELECT BIT 2
012767
012767

001404

000340
004000
003000
014710
000004
000004

175054
014770
014756

T17:

MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, 1COUNT
#28 ESCAPE
DHSCR,R3
#B1T02, (R3)

;:DISABLE ALL INTERRUPTS
*SET UP FOR 4000
ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
“SET LINE SELECT BIT 2

MOV

#BITO2,RS

:(RS)= EXPECTED VALUE

g?;

finoz.(ns)

*VERIFY THAT LINE SELECT BIT 2 WAS SET

002754

012705

002760

011304

MOV

(R3) R4

002762

104001

HLT

002764
002770
002772

042713
001403
005005

gég

gxroz.m)

CLR

: (RS)=EXPECTED DATA IN

002714
002722

SVERITY THAT LINE SELECT BIT 2 WAS CLEARED

b =
b
e

e {e Pt

§OQQ

N ele BN AV

WN=O

00 00 00 00 0o 00 00

R
R R

a4
792
793

PAGE 18

011304

MOV

(R3) R4

*SYSTEM CONTROL REGISTER, 0

*(R&)=ACTUAL DATA IN

002776

104001

HLT

*SYSTEM CONTROL REGISTER

003000

104400

000004

1%:

’%:

SCOPE

*IN SYSTEM CONTROL
*LINE SELECT BIT

*(R6)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER

*SYSTEM CONTROL REGISTER
*WRITE/READ ERROR

*CLEAR LINE SELECT BIT 2

*SYSTEM CONTROL REGISTER
*WRITE/READ ERROR

*CHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NOR4AL MODE)

*SET LINE SELECT BIT 3 IN SYSTEM CONTROL REGISTER
*VERIFY THAT LINE SELECT BIT 3 WAS SET
*CLEAR LINE SELECT BIT 3
SVERITY THAT LINE SELECT BIT 3 WAS CLEARED
003002
003010
003016
003026

003030
003034

003040
003042

012767
012767
012767
016703

000340
004

012713
022713
001404
012705

1764766

014702
014670

T120:

MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, 1 COUNT
#2%,ESCAPE
DHSCR,R3
#BIT03, (R3)

;:DISABLE ALL INTERRUPTS
*SET UP FOR 4000
ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
:SET LINE SELECT BIT 3

MOV

#BIT03,RS

:(RS)= EXPECTED VALUE

ggg

:gnos.m)

*VERIFY THAT LINE SELECT BIT 3 WAS SET

sIN SYSTEM CONT
REGISTER
sLINE SELECT BIT
: (R4)=ACTUAL DATA IN
;SYSTEM CONTROL REGISTER

003046

011304

MOV

(R3) R4

00305C

104001

HLT

003052

042713

gég

52”03.0?3)

;WRITE/READ ERROR
;CLEAR LINE SELECT BIT 3

3060

005005

(LR

; (RS)=EXPECTED DATA IN

842

003062

011304

MOV

(R3) ,R4

844

003004

104001

HLT

839 %3056 001403

000010

sSYSTEM CONTROL REGISTER

sSYSTEM CONTROL REGISTER, 0
s (R4)=ACTUAL DATA IN
sSYSTEM CONTROL REGISTER
sSYSTEM CONTROL REGISTER

CZDHA-C MACY11

CZDHAC.P1T
846

003066

30A(1052)

23-AUG-78

15-MAY-78 10:02

14:40

28:

104400

PAGE 19

SEQ 0029
;WRITE/READ ERROR

SCOPE

*CHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
:SET MEMORY EXTENSION BIT O IN SYSTEM CONTROL REGISTER

*VERIFY THAT MEMORY EXTENSION BIT O WAS SET

*CLEAR MEMORY EXTENSION BIT 0
*VERITY THAT MEMORY EXTENSION BIT 0 WAS CLEARED
54
855

003070
003076

012767
012767

ggg

003122

022713

000020
000020

861

003130

012705

000020

864

003134

868

000340
004000

174700

T21:

MOV

#340,PS

;:DISABLE ALL

INTERRUPTS

MOV
MOV
MOV
MOV

#4000, 1COUNT
#23 ESCAPE
DHSCR,R3
#BIT04, (R3)

MOV

#BITO04,RS

011304

MOV

(R3) R4

003136

104001

HLT

“SYSTEM CONTROL REGISTER

003140

042713

Ség

ggnoe.um

:CLEAR MEMORY EXTENSION BIT 0

CLR

: (RS)=EXPECTED DATA IN

MOV

(R3) .R4

HLT

154

% 534

014614

014602

geng

000020

18:

2%:

finouas)

SCOPE

*SET UP FOR 4000
ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
*SET MEMORY EXTENSION BIT 0

“VERIFY THAT MEMORY EXTENSION BIT O WAS SET

: (RS)= EXPECTED VALUE

“IN SYSTEM CONTROL REGISTER
*MEMORY EXTENSION BIT 0

*(R4)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER
*WRITE/READ ERROR

*SYSTEM CONTROL REGISTER, 0

*(R&)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER

*WRITE/READ ERROR

*CHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
*SET MEMORY EXTENSION BIT 1 IN SYSTEM CONTROL REGISTER
:VERIFY THAT MEMORY EXTENSION BIT 1 WAS SET
:CLEAR MEMORY EXTENSION BIT 1
*VERITY THAT MEMORY EXTENSION BIT 1 WAS CLEARED
003156

012767

000340
004000

174612

014526
014514

T22:

MOV

:DISABLE ALL INTERRUPTS

finos,mv

*VERIFY THAT MEMORY EXTENSION BIT 1 WAS SET

#4000, 1COUNT
#2% ,ESCAPE
DHSCR,R3
#81705, (R3)

MOV

#BITOS,RS

*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
*SET MEMORY EXTENSION BIT 1

;(RS)= EXPECTED VALUE

003216

012705

003222

011304

MOV

(R3) R4

003224

104001

HLT

003226

042713
001403
005005

gég

#BITO05, (R3)

*CLEAR MEMORY EXTENSION BIT 1

: (RS)=EXPECTED DATA IN

891

S3BIRIS

003234

000040

#340,PS

MOV
MOV
MOV
MOV

000040

1$:

“IN SYSTEM CONTROL REGISTER
*MEMORY EXTENSION BIT 1

*(R4)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER

*WRITE/READ ERROR

CZDHA=C MACY11 30A(105§)

CZDHAC.P11
901

15-MAY=-78

23-AUG-78

10:02

14:40

PAGE 20

SEQ 0030

902

003236

011304

MOV

(R3) R4

904

003240

104001

HLT

003242

104400

903
905

28:

908
909

920

:VERITY THAT RECEIVER INTERRUPT ENABLE WAS CLEARED
003244

012767

003252
003260
003266
003272
003276
003302

000340

012767
012767
016703
012713
022713

004000
003330
014360
000100
000100
000100

001404

174524

014440
014426

T123:

MOV

#340.PS

#4000, 1COUNT
#2$ ESCAPE
DHSCR,R3
#1706, (R3)
#BIT06. (R3)

“SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
:PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
*SET RECEIVER INTERRUPT ENABLE
*VERIFY THAT RECEIVER INTERRUPT ENABLE WAS SET

MOV

#B]1T06,RS

:(RS)= EXPECTED VALUE
*(R4)=ACTUAL DATA IN

BEQ

012705

924

003310

011304

MOV

(R3) ,Ré4

003312

104001

HLT

003314

042713

BIC

#BITO06, (R3)

928

929
930
931

932

933
93%
935

ggg

000100

1%:

003320
003322

001403
005005

003324

011304

MOV

(R3) ,Ré4

003326

104001

HLT

003330

104400

2%:

938

940
91

950

003332

003340
00336
003354
003360
003364

003370

003372

954

003376

956

003400

955

SCOPE

:CLEAR RECEIVER INTERRUPT ENABLE

: (RS)=EXPECTED DATA IN
:SYSTEM CONTROL REGISTER, 0

:(R4)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER
“WRITE/READ ERROR

:CHECK FOR ITERATIONS, LOOP

SVERITY THAT MAINTENANCE MODE WAS CLEARED

951

952
953

2%
RS

*SYSTEM CONTROL REGISTER
:SYSTEM CONTROL REGISTER
*WRITE/READ [ RROR

*CLEAR MAINTENANCE MODE

%5
%6
%7
%8
%9

BEQ
CLR

“IN SYSTEM CONTROL REGISTER
*RECEIVER INTERRUPT ENABLE

:SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
:SET MAINTENANCE MODE IN SYSTEM CONTROL REGISTER
*VERIFY THAT MAINTENANCE MODE WAS SET

939

9%4

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV
MOV
cMP

003304

925
926
927

:WRITE/READ ERROR

:CHECK FOR ITERATIONS, LOOP

921

922
923

*SYSTEM CONTROL REGISTER

:VERIFY THAT RECZIVER INTERRUPT ENABLE WAS SET
:CLEAR RECEIVER INTERRUPT ENABLE

915
916
917
918
919

:(R4)=ACTUAL DATA IN

:SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
;SET RECEIVER INTERRUPT ENABLE IN SYSTEM CONTROL REGISTER

910
911

914

SCOPE

:SYSTEM CONTROL REGISTER, 0

012767

000340

012767
012767
016703
012713
022713

0040C0
003416
014272
001000
001000

012705

001000

174436

014352
014340

T24:

MOV

#340.PS

MOV
MOV
MOV
MOV
cTMP

#4000, TCOUNT
#2% ESCAPE
DHSCR,R3
#1709, (R3)
#8;709. (R3)

MOV

#81T09,RS

011304

MOV

(R3) R4

104001

HLT

001404

BEQ

:DISABLE ALL INTERRUPTS

:SET UP FOR 4000 ITERATIONS
“SET UP TO ESCAPE TO NEXT TEST
:PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
*SET MAINTENANCE MODE
*VERIFY THAT MAINTENANCE MODE WAS SET

:(RS)= EXPECTED VALUE

“IN SYSTEM CONTROL REGISTER
“MAINTENANCE MODE
*(R4)=ACTUAL DATA IN
*SYSTEM CONTROL REGISTER
;SYSTEM CONTROL REGISTER

CZDHA-C MACY11 30A(105 2)
23-AUG-78
CZDHAC.PN
15-MAY=78 10:02

14:40

PAGE 21

1%:

BIC

5%1 709, (R3)

CLR

003412

MOV

(R3) ,R4

003414

HLT

003402
003406
003410

001000

003416

2%:

BEQ

SEQ 0031
;WRITE/READ ERROR

s CLEAR MAINTENANCE MODE

; (RS)=EXPECTED DATA IN

sSYSTEM CONTROL REGISTER, 0
: (R6)=ACTUAL DATA IN
sSYSTEM CONTROL REGISTER

;SYSTEM CONTROL REGISTER

sWRITE/READ ERROR
;CHECK FOR ITERATIONS, LOOP

SCOPE

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
;SET SILO OVERFLOW INTERRUPT ENABLE IN SYSTEM CONTROL REGISTER
:VERIFY THAT SILO OVERFLOW INTERRUPT ENABLE WAS SET
sCLEAR SILO OVERFLOW INTERRUPT ENABLE
;VERITY THAT SILO OVERFLOW INTERRUPT ENABLE WAS CLEARED

MOV
MOV
MOV
MOV
MOV
CMP

#340,PS
#4000, 1COUNT
#2% ,ESCAPE
DHSCR,R3
#BIT12,(R3)
131112.0:3)

:DISABLE ALL INTERRUPTS
*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
*SET SILO OVERFLOW INTERRUPT ENABLE
*VERIFY THAT SILO OVERFLOW INTERRUPT ENABLE WAS

MOV

#BIT12,RS

011304

MOV

(R3) ,R4

104001

HLT

;(R5)= EXPECTED VALUE
:IN SYSTEM CONTROL REGISTER
:SILO OVERFLOW INTERRUPT ENABLE
: (R4)=ACTUAL DATA IN
sSYSTEM CONTROL REGISTER

gég

521712.(!23)

;CLEAR SILO OVERFLOW INTERRUPT ENABLE

CLR

: (R5)=EXPECTED DATA IN

011304

MOV

(R3) ,R4

104001

HLT

012767
012767
012767
016703
012713
022713
001404
012705

042713
001403
005005

104400

000340
004000
003504
014204
010000
010000

176350

014264
014252

T125:

010000

1%:

2%:

SCOPE

:SYSTEM CONTROL REGISTER
;WRITE/READ ERROR

;SYSTEM CONTROL REGISTER, 0
; (R4)=ACTUAL DATA IN
sSYSTEM CONTROL REGISTER

sSYSTEM CONTROL REGISTER
;WRITE/READ ERROR

;CHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
sSET TRANSMITTER INTERRUPT ENABLE

IN SYSTEM CONTROL REGISTER

—_

MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, 1COUNT
#2$ ESCAPE
DHSCR,R3
#BIT15,(R3)

;DISABLE ALL INTERRUPTS
*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
*SET TRANSMITTER INTERRUPT ENABLE

MOV

#2'T13.RS

:(RS)= EXPECTED VALUE

gz;

nN—O

o
97 4

1004

jeolelelelele)

;VERIFY THAT TRANSMITTER INTERRUPT ENABLE WAS SET
;CLEAR TRANSMITTER INTERRUPT ENABLE
;VERITY THAT TRANSMITTER INTERRUPT ENABLE WAS CLEARED

fims.um

*VERIFY THAT TRANSMITTER INTERRUPT ENABLE WAS SE

*IN SYSTEM CONTROL REGISTER

I CZOHA-C MACY1? 30A(1052) 23-AUG-78 14:40 PAGE 22
VOOV
W

Y
~

- —

)

WN=O

)

SERSRR
Vi
g

D e

(eoleleolelelels]

CZDHAC.P1

15-MAY-78 10:02

SEQ 0032

003552

011304

MOV

(R3) ,Ré4

003554

104001

HLT

003556
003562
003564

042713
001403
005005

gég

gms,(ns)

CLR

003566

011304

MOV

(R3) R4

003570

104001

HLT

003572

104400

020000

1%:

2%:

SCOPE

;TRANSMITTER INTERRUPT ENABLE

*(R4)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER

*SYSTEM CONTROL REGISTER
*WRITE/READ ERROR

*CLEAR TRANSMITTER INTERRUPT ENABLE

: (RS)=EXPECTED DATA IN
*SYSTEM CONTROL REGISTER, 0

*(R4)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER

*WRITE/READ ERROR

*CHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
*SET TRANSMITTER DONE IN SYSTEM CONTROL REGISTER
*VERIFY THAT TRANSMITTER DONE WAS SET
*CLEAR TRANSMITTER DONE
*VERITY THAT TRANSMITTER DONE WAS CLEARED
012767
012767

1037

003616

016703

1039

003626

022713

014030
100000
100000

1041

003634

012705

100000

000340
004008
003660

174174
014110
014076

127:

MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, 1 COUNT
#28 . ESCAPE
DHSCR,R3
#1715, (R3)

fi;ms.ms)

*VEFIFY THAT TRANSMITTER DONE WAS SET

MOV

#BIT15.RS

:(RS)= EXPECTED VALUE

011304

MOV

(R3) R4

003642

104001

003640

042713
001403
005005

100000

1%:

gég

gms.my

CLR

003654

011304

MOV

(R3) R4

003650
003652

104001

HLT

003660

104400

2%:

:DISABLE ALL INTERRUPTS
“SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
*SET TRANSMITTER DONE

5?5

IS
&

—

ZIEERERERS unngpnu“nunAV\

olelolelelolelele]

W =O Voo~V

003574
003602

D —D

34
835

SCOPE

*IN SYSTEM CONTROL REGISTER

*TRANSMITTER DONE

*(R6)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER

*WRITE/READ ERROR

*CLEAR TRANSMITTER DONE

: (RS)=EXPECTED DATA IN

*SYSTEM CONTROL REGISTER, 0

*(R&)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER

*WRITE/READ ERROR

*CHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
*VERIFY THAT CHARACTER AVAILABLE IS READ ONLY IN NORMAL MODE
003662
00367C
003676
003704
003712
003716

01 767
01
01 767
01 777
005777
00

000340

004000

003734
000200

013734

0
O

MOV
MOV
MOV
MOV

#350,PS
#4000, 1COUNT
#1$,ESCAPE
#B1707.aDHSCR

Er;?é

?g.u.scn

:DISABLE ALL INTERRUPTS
*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
SATTEMPT TO WRITE
*CHARACTER AVAILABLE IN

*SYSTEM CONTROL REGISTER
‘WAS CHARACTER AVAILABLE

SET

CZDHA=C MACY11 30A(1055)102(3)5AUG-78
CZDHAC.P11
15-MAY-7
1069
1070
1071
1072
1073
1074
1075
1076

003720

005005

003722

017704

013724

003726

016703

013720

005734

104400

003732

104001

003736

012767

000340

083
084
085
086
087
088

003752
003760

012767
012777

004010
000400

003766
003772
003774

005777
001406
005005

013660

003776

017704

004002
004006

016703
104007

004010

104400

081

012767

004000

SEQ 0033

(LR

MOV

@DHSCR,Ré4

MOV

DHSCR.R3
1

SCOPE

U
O

:VERIFY THAT CLEAR

174032

013746

T31:

013734
013664

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV

#1S,ESCAPE
#BIT08,3DHSCR

:SET UP TO ESCAPE TO NEXT TEST
ATTEMPT TO WRITE
:CLEAR NON EXISTANT MEMORY N
:SYSTEM CONTROL REGISTER
:WAS CLEAR
NON EXISTANT MEMORY SET

#4000, 1COUNT

@DHSCR
1%
RS

013650

MOV

@DHSCR.R4

013644

MOV
WT

DHSCR,R3
1

1$:

012767

000340

004026
004034

012767
012777

004064
002000
013604

005005

004052

017704

004056
004062

016703
104001

004064

104400

173756

T132:

013672

e R
e

: (RS)=EXPECTED DATA
:IN SYSTEM CONTROL REGISTER, 0
: (R)=ACTUAL DATA IN SYSTEM
:CONTROL REGISTER
:ADDRESS OF SYSTEM CONTROL REGISTER
:SYSTEM CONTROL REGISTER
WRITE/READ ERROR

013660
013610

MOV

#340,P5

sDISABLE ALL INTERRUPTS

MOV
MOV

#18 ESCAPE
#81T710,aDHSCR

sSET _UP TO ESCAPE TO NEXT TEST
;ATTEMPT TO WRITE
sNON EXISTANT MEMORY IN

MOV

TST
BEQ

#4000, 1 COUNT

aDHSCR
1%

CLR

013574

MOV

aDHSCR R4

013570

MOV
HLT

DHSCR,R3
1

004000

005777
001406

oAl

004042
004046

012767

004020

004012

JOE W

WO WO

B
s e
T
e

SCOPE

SET UP FOR 4000 ITERATIONS

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
;VERIFY THAT NON EXISTANT MEMORY IS READ ONLY IN NORMAL MODE

1%:

sSET UP FOR 4000 ITERATIONS
sSYSTEM CONTROL REGISTER

sWAS NON EXISTANT MEMORY SET

; (R5)=EXPECTED DATA
sIN SYSTEM CONTROL REGISTER, 0
: (R4)=ACTUAL DATA IN SYSTEM

;CONTROL REGISTER
sADDRESS OF SYSTEM CONTROL REGISTER
;SYSTEM CONTROL REGISTER
;WRITE/READ ERROR

SCOPE

sSYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
;VERIFY THAT MASTER CLEAR IS READ ONLY IN NORMAL MODE

004066

012767

000340

23
24

004102
004110

012767
012777

004140
004000

NON EXISTANT MEMORY IS READ ONLY IN NORMAL MODE

MOV

ST
BEQ
(LR

B i e L T P
—
eoleleoleolelels]
SoBIr
AR A0
BBIRIRAC2S

089
090
091
092
093
09
095
096
097
098
099

; (RS)=EXPECTED DATA
:IN SYSTEM CONTROL REGISTER, 0
: (R4)=ACTUAL DATA IN SYSTEM
:CONTROL REGISTER
:ADDRESS OF SYSTEM CONTROL REGISTER
SYSTEM CONTROL REGISTER
WRITE/READ ERROR

:SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)

003744

PAGE 23

HLT

1079

1$:

1078

082

14:40

004074

012767

004000

173702

013616

013604
013534

T133:

MOV

#340,PS

sDISABLE ALL INTCRRUPTS

MOV
MOV

#.% ESCAPE
#31T11,aDHSCR

;SET UP TO ESCAPE TO NEXT TEST
JATTEMPT TO WRITE

MOV

#4000, 1 COUNT

2SET UP FOR 4000 ITERATIONS

CZDHA-C MACY1

CZDHAC.P11
1125
1126

1127

004116

30A(1052)102(3)§AUG-78

15-MAY-78
005777

14:40

013530

PAGE 24

SEQ 0034
,

aDHSCR

1128
1129

004122
004124

001406
005005

1131

004126

017704

013520

MOV

aDHSCR, R4

1133

004132

016703

01354

MOV

DHSCR,R3

004140

104400

1130
1132

113

1135

”%9

004736

104007

BEQ
CLR

HLT

1$:

1138

1142
1143
1144
1145

1146

1147

1148

1149
1150

SCOPE

004142

004150
004156
004164
004172

004176

012767

012767
012767
012777
005777

001406

000340

004000
(%214
040000

173626

013542
013530
013460

~34:

013454

MOV

MOV
MOV
MOV

#340,PS

#4000, 1 COUNT
#1$ ,ESCAPE
#81714,aDHSCR

aDHSCR

CLR

BEQ

005005

1151

004202

017704

013444

MOV

aDHSCR R4

1153

004206

016703

013440

MOV

DHSCR,R3

004214

104400

1154
1155
1156
1157
1158
1159

: (RS)=EXPECTED DATA

004212

104007

HLT

1$:

1160

:(R4)=ACTUAL DATA IN SYSTEM

*CONTROL REGISTER

“ADDRESS OF SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER

*WRITE/READ ERROR

;DISABLE ALL

INTERRUPTS

“SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
SATTEMPT TO WRITE
*SILO OVERFLOW IN

“SYSTEM CONTROL REGISTER
:WAS SILO OVERFLOW SET

: (RS)=EXPECTED DATA
“IN SYSTEM CONTROL REGISTER, 0

“(R4)=ACTUAL DATA IN SYSTEM
*CONTROL REGISTER

*ADDRESS OF SYSTEM CONTROL REGISTER

*SYSTEM CONTROL REGISTER
*WRITE/READ ERROR

SCOPE
:SYSTEM CONTROL REGISTER WRITE/READ TEST (MAINTENANCE MODE)
*SET MAINTENANCE MODE
:SET CHARACTER AVAILABLE IN SYSTEM CONTROL REGISTER

SVERIFY THAT CHARACTER AVAILABLE WAS SET

1161

*CLEAR MAINTENANCE MODE

1162

SVERIFY THAT CHARACTER AVAILABLE CANNOT BE CLEARED

1164

:CLEAR CHARACTER AVAILABLE

1163

*SET MAINTENANCE MODE

”gg

1167

1168
1169
1170
1171
1172
1173
1174
1175

*VERIFY THAT CHARACTER AVAILABLE WAS CLEARED

004216

012767

004224
004232
004240
004244
004250
004254

012767
012767
016703
012713
052713
022713

004260

001404

1176

004262

012705

1179

004266

011304

1177
1178

1180

)

*IN SYSTEM CONTROL REGI.TER, 0

:VERIFY THAT SILO OVERFLOW IS READ ONLY IN NORMAL MODE

004200

1152

*WAS MASTER CLEAR SET

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)

Hzg

1141

1%
RS

;MASTER CLEAR IN
*SYSTEM CONTROL REGISTER

000340

004000
004344
013406
001000
000200
001200

001200

173552

013466
013454

7135:

MOV

#340,PS

MOV
MOV
MOV
MOV
BIS
CTMP

#4000, 1COUNT
#38 _ESCAPE
DHSCR ,R3
#1709, (R3)
#B]T07. (R3)
#8;T09+B1T07, (R3)

BEQ

;DISABLE ALL INTERRUPTS

*SE1 U® FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
:PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
:SET MAINTENANCE MODE
*SET CHARACTER AVAILABLE
*VERIFY THAT CHARACTER AVAILABLE
*AND MAINTENANCE MODE ARE SET

MOV

#B]1TO9+BITO7,RS : (RS)=EXPECTED DATA

MOV

(R?) R4

;IN SYSTEM CONTROL REGISTER
“MAINTENANCE MODE AND CHARACTER AVAILABLE

:(R4)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER

004270

104001

004272
004276
004302
004306
004310

042713
042713
022713

14:40

012705

BIC
BlC
CMP
BEQ

MOV

#B1709, (R3)
#81707, (R3)
#BIT07, (R3)
2%
#BI1T07 RS

004314

104001

HLT

004316
004322
004326

052713
042713
022713

001000

BIS
BIC
mP

#BI1T09, (R3)
#BIT07, (R3)
#81T09, (R3)

%i’i?

001404

001000

BEQ
MOV

3s
#BIT09,RS

004340

011304

MOV

(R3) ,R4

004342

102001

HLT

004344

104400

012705

1%:

2%:

001000

38:

b s

;SYSTEM CONTROL REGISTER

;WRITE/READ ERROR

cCLEAR MAINTENANCE MODE

SATTEMPT TO CLEAR CHARACTER AVAILABLE

sCHARACTER AVAILABLE SHOULD BE SET

; (RS)=EXPECTED DATA IN
:SYSTEM CONTROL REGISTER
:CHARACTER AVAILABLE
:SYSTEM CONTROL REGISTER
:WRITE/READ ERROR
:SET MAINTENANCE MODE
:CLEAR CHARACTER AVAILABLE
SEXPECT ONLY MAINTENANCE
:MODE TO BE SET
: (R5)=EXPECTED DATA IN
;SYSTEM CONTROL REGISTER,
sMAINTENANCE MODE BIT
: (R4)=ACTUAL DATA IN
sSYSTEM CONTROL REGISTER
;SYSTEM CONTROL REGISTER

;WRITE/READ ERROR
SCOPE
28 HECK FOR ITERATIONS, LOOP
;SYSTEM CONTROL REGISTER WRITE/READ TEST (MAINTENANCE MODE)
sSET MAINTENANCE MODE

:SET NON_EXISTANT MEMORY IN SYSTEM CONTROL REGISTER
sVERIFY THAT NON EXISTANT MEMORY WAS SET
;CLEAR MAINTENANCE MODE
sVERIFY THAT NON EXISTANT MEMORY CANNOT BE CLEARED
sSET MAINTENANCE MODE
;CLEAR NON EXISTANT MEMORY
;VERIFY THAT NON EXISTANT MEMORY WAS CLEARED

d —d
) e

i
i

e wd

il cd i

e
—

i o

SEQ 0035

HLT

D i

INSIASLAS ST LN LS LN LN 1N [N TN

PAGE 25
;

D i

i i

D i

D i
B

D i D i i i i
s
JEP N
O
O
Y

putrd

3 VONOWVEWN=O CHEEEEEEEE ERIRIREC2EBBIRRRER oo

) D i D sl i i D D e
G
R
G
——Y

CZDHA-C MACY11 30A(1052)
23-AuG-78
15-MAY-78 10:02
CZDHAC.P1

004346

000340

004362
004370
004374

016703
012713

004474
013256
001000

004404

022713

003000

004410
004412

001404
012705

003000

004416

011304

MOV

(R3) .R4

004420

104001

HLT

;

BIC
BIC

#B1709, (R3)
#1710, (R3)

004354

001000

002000
004440

012705

002000

173422

013336
013324

r36:

#340,PS

#4000, 1COUNT

#3$ ESCAPE

DHSCR ,R3

#1709, (R3)

#1710, (R3)

#B1T09+81710, (R3)
1%

;DISABLE ALL INTERRUPTS
sSET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
sPUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
sSET MAINTENANCE MODE
sSET NON EXISTANT MEMORY
sVERIFY THAT NON EXISTANT MEMORY
sAND MAINTENANCE MODE ARE SET

#BI1TO9+BIT10,RS s (RS)=EXPECTED DATA

1%:

8EQ
MOV

#81710, (R3)

2%
#C'T10,RS

sIN SYSTEM CONTROL REGISTER
sMAINTENANCE MODE AND NON EXISTANT MEMORY
: (RG)=ACTUAL DATA IN
sSYSTEM CONTROL REGISTER
sSYSTEM CONTROL REGISTER
sWRITE/READ ERROR
;CLEAR MAINTENANCE MODE
SATTEMPT TO CLEAR NON EXISTANT MEMORY

sNON EXISTANT MEMORY SHOULD BE SET

: (R5)=EXPECTED DATA IN
;SYSTEM CONTROL REGISTER

CZDHA-C MACY11

CZDHAC.P11

30A(1052)

1237
1238

004444

104001

1240
1241
1242

004446
004452
004456

052713
042713
022713

0046462

001404

1239

1243
1264

1245

1246
1247

1248

1249
1250
1251

1252
1253

004464

004470

3-AUG-78

15-MAY=78 10:02

14:40

001000
002000
001000

012705

2%:

004472

004474

104400

1254

MOV

(R3) ,R4

HLT

004476
004504
004512
004520
004524

1269
1271

012767
012767
012767
016703
012713

000340
004000
004624
013126
001000

004534

022713

041000

004540

001404

004530

052713

1272

004542

012705

1275

173272
013206
013174

T37:

040000

MOV
MOV
MOV
MOV
MOV

#340,PS
#4090, 1 COUNT
#38 ESCAPE
DHSCR,R3
#B1T09, (R3)

(MP

#BIT09+BIT14, (R3)

BEQ

BIS

041000

#BIT14, (R3)

MOV

(R3) ,Ré4

004550

104001

HLT

1279

004552

042713

BIC

#81109, (R3)

004556

004562
004566

042713

022713
001403

1283

004570

012705

1286

004574

104001

1288

004576

052713

1290

004606

022713

1292

006612

00140~

1289

1291

004602

042713

001000

040000

1%:

040000

001000

040000

001000

2%:

*SET SILO OVERFLOW

*VERIFY THAT SILO OVERFLOW

sAND MAINTENANCE MODE ARE SET

;IN SYSTEM CONTROL REGISTER
JMAINTENANCE MODE AND SILO OVERFLOW

; (R4)=ACTUAL DATA IN

;SYSTEM CONTROL REGISTER
:SYSTEM CONTROL REGISTER

;WRITE/READ ERROR

:CLEAR MAINTENANCE MODE

BIC

#BIT14, (R3)

MOV

#BIT14 RS

HLT

:SYSTEM CONTROL REGISTER

BIS

#81109, (R3)

:SET MAINTENANCE MODE

cMP

#81109, (R3)

EXPECT ONLY MAINTENANCE

BEQ

MP
BEQ

040000

;DISABLE ALL INTERRUPTS
:SET UP FOR 4000 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
;SET MAINTENANCE MODE

#BI1T09+BIT14,RS : (RS)=EXPECTED DATA

011304

1287

; (R4)=ACTUAL DATA IN

;SYSTEM CONTROL REGISTER
:SYSTEM CONTROL REGISTER
JWRITE/READ ERROR

MOV

004546

1284
1285

;SYSTEM CONTROL REGISTER,
MAINTENANCE MODE BIT

SCOPE
:CHECK FOR ITERATIONS., LOOP
;SYSTEM CONTROL REGISTER WRITE/READ TEST (MAINTENANCE MODE)

1276
1277

1281
1282

; (RS)=EXPECTED DATA IN

JVERIFY THAT SILO OVERFLOW WAS CLEARED

1263
1264
1265
1266
1267

1280

;CLEAR SILO OVERFLOW

}2225

1278

;MODE TO BE SET

:CLEAR MAINTENANCE MODE
;VERIFY THAT SILO OVERFLOW CANNOT BE CLEARED
;SET MAINTENANCE MODE

1260

#BI1T09,RS

;SET MAINTENANCE MODE
*CLEAR NON EXISTANT MEMORY
EXPECT ONLY MAINTENANCE

JVERIFY THAT SILO OVERFLOW WAS SET

1257
1258
1259

1273
1274

#81709, (R3)
#81710, (R3)
#B1T09, (R3)

sNON CXISTANT MEMORY
“SYSTEM CONTROL REGISTER
*WRITE/READ
ERROR

*SET SILO OVERFLOW IN SYSTEM CONTROL REGISTER

1256

1270

BIS
BIC
cMP

SEQ 0036

*SET MAINTENANCE MODE

1255

1268

MOV

3$:

HLT

BEQ

001000

011304 °

o
104001

PAGE 26

BIC

#1114, (R3)
28

#1714, (RY)

;ATTEMPT TO CLEAR SILO OVERFLOW

;SILO OVERFLOW SHOULD BE SET

; (RS)=EXPECTED DATA IN

:SYSTEM CONTROL REGISTER
:SILO OVERFLOW

JWRITE/READ ERROR

;CLEAR SILO OVERFLOW

:MODE TO BE SET

CZDHA-C MACY11

004614

30A(1052)

23-AUG-78

15-MAY-78 10:02
012705

001000

D ) D D d D d D D i

318

319

D el D D D i

321

322

gRg

323
324
325

004620 011304

MOV

(R3) R4

004622

104001

HLT

0046264

104400

38:

012767

000340

004656
004662
004666
004670
004672
004674

016703
012705
010513
011304
020504
001401

012774
000001 °

004700

040513

004704

005704

004676

004702

004706

004710
004712
004714

173142

013056
013044
012774

104002

T40:

1%:

011304

001402

) D ) D e
D ) e
e
D e

339

D e

340
341
34;

:CHECK FOR ITERATIONS, LOOP

MOV
MOV
MOV

005005
104002
104400

2%:

#340,PS

;DISABLE ALL INTERRUPTS

#4000, 1COUNT
#2$ ESCAPE
#81T11,3DHSCR

*SET UP FOR 4000 ITERATIONS
“SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

:LINE PARAMETER REGISTER ERROR

MOV
MOV
MOV
MOV
CMP
BEQ

DHLPR,R3
#1.RS
RS’ (R3)
(R$) ,R4
RS,R&
18

BIC

RS, (R3)

*CLEAR BIT 0

TST

Ré

“WAS BIT 0 CLEAR<D

CLR
HLT
SCOPE

RS
2

HLT

MOV

(R%) ,R4

“SET UP POINTER TO LINE PARAMETER
*BIT O WILL BE SET IN LINE PARAMETER
SSET BIT 0
:GET CONTENTS OF LINE PARAMETER
*WAS BIT O SET

*READ CONTENTS ©f LINE PARAMETER

:LINE PARAMETER REGISTER ERROR

SVERIFY THAT BIT 1 WAS CLEARED

004716

004726
004732
004740
004746
004752

004756

004760
004762
004764

26
347
348

004774
004776
005000

:SYSTEM CONTROL REGISTER
:SYSTEM CONTROL REGISTER
:WRITE/READ ERROR -

:VERIFY THAT BIT 1 WAS SET
*CLEAR BIT 1

004766
004770

—

: (R4)=ACTUAL DATA IN

sLINE PARAMETER REGISTER DATA TEST
sSET BIT 1 IN LINE PARAMETER T0 1

343
34

345

MOV

BEQ

i%}

33
335
33
337
338

SCOPE

: (R5)=EXPECTED DATA IN
;SYSTEM CONTROL REGISTER,
sMAINTENANCE MODE BIT

;LINE PARAMETER REGISTER DATA TEST
sSET BIT O IN LINE PARAMETER TO 1
;VERIFY THAT BIT 0 WAS SET
*CLEAR BIT 0
SVERIFY THAT BIT O WAS CLEARED

329
330
333

#BITO09,RS

004634 012767 004000
3iv 006642 012767 004714
311 004650 012777 004000

312
313
314
315
316
317

14:40 PRAGE 27

MOV

) ) D d D e e e

D d D D e

D e e e

BRSRIRERESYPIFYY3

CZDHAC.PI

004772

012767

012767
012767
012777
016703
012705
010513

000340

004000
005004
004000
012704
000002

173052

012766
012754
012704

T41:

011304

005704
001402
005005

1$:

#340,PS

:DISABLE ALL INTERRUPTS

#4000, 1COUNT
#28 ,ESCAPE
#8171, 3DHSCR
DHLPR,R3
#2 RS

*SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
:BIT 1 WILL BE SET IN LINE PARAMETER

MOV
CMP
BEQ

(R%) R4
RS.R4
1%

:GET CONTENTS OF LINE PARAMETER
:WAS BIT 1 SET

MOV-

011304
020504
001401
10400
04051

MOV

MOV
MOV
MOV
MOV
MOV

RS.(R3)

“SET BIT 1

HLT
BIC

2
RS, (R3)

:LINE PARAMETER REGISTER ERROR
*CLEAR BIT 1

ST
BEQ
CLR

R4
2:
RS

“WAS BIT 1 CLEARED

MOV

(R%) ,R4

:READ CONTENTS OF LINE PARAMETER

SEQ 0037

CZDHA=C MACY11 30A(10 52)
23-AUG-78
CZDHAC.P1T
15-MAY-78 10:02

005002
005004

14 :40

104002
104400

2$:

PAGE 28

HLT

SCOPE

SEQ 0038
2

sLINE PARAMETER REGISTER ERROR

sLINE PARAMETER REGISTER DATA TEST

72762

(olele

000340
004000
005074
004000
012614
000004

2676

T42:

614

2%:

?g.m

DHLPR,R3
#4 RS
RS, (R3)
(R$) R4

*SET UP POINTER TO LINE PARAMETER
*BIT 2 WILL BE SET IN LINE PARAMETER
*SET BIT 2
:GET CONTENTS OF LINE PARAMETER

HLT

:LINE PARAMETER REGISTER ERROR

MOV

(R%) ,R4

BIC

RS, (R3)

TST

CLR

HLT
SCOPE

2%
2

*WAS BIT 2 SET
“CLEAR BIT 2

SREAD CONTENTS OF LINE PARAMETER

*WAS BIT 2 CLEARED

:LINE PARAMETER REGISTER ERROR

) D

;VERIFY THAT BIT & WAS SET
;CLEAR BIT &

) D
D
) e
)
D
)
D e

ggg

:DISABLE ALL INTERRUPTS
*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

sLINE PARAMETER REGISTER DATA TEST
sSET BIT & IN LINE PARAMETER TO 1
:VERIFY THAT BIT & WAS CLEARED

000340
004000
005164
0049200

012524

172672

012606
012574
012524

T43:

000020

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, 1 COUNT
#28 ,ESCAPE
#B81711,aDHSCR
DHLPR,R3
#20,RS
RS, (R3)
(R$) .R4

;:DISABLE ALL INTERRUPTS
*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
*BIT 4 WILL BE SET IN LINE PARAMETER
*SET BIT 4
:GET CONTENTS OF LINE PARAMETER

HLT

:LINE PARAMETER REGISTER ERROR

MOV

(R$) ,R4

:READ CONTENTS OF LINE PARAMETER

5?0’

e
d —d d D

#340,PS
#4000, 1 COUNT
#28 ,ESCAPE
#B81717, aDHSCR

BEQ

1%:

BIC

2%:

l;g.m.

RS, (R3)

CLR

BEQ

b
—

MOV
MOV
MOV
MOV

MOV
MOV
MOV
MOV
1%:

) D D

) D D d d D d D D d D d D

SEREFIRINLRELUBRRRBEIINY S SNSSEELETEERES

D e

;SET BIT 2 IN LINE PARAMETER TO 1
sVERIFY THAT BIT 2 WAS SET
;CLEAR BIT 2
;VERIFY THAT BIT 2 WAS CLEARED

HLT

SCOPE

2$
2

‘WAS BIT & SET
*CLEAR BIT 4

*WAS BIT 4 CLEARED

:LINE PARAMETER REGISTER ERROR

sLINE PARAMETER REGISTER DATA TEST

sSET BIT - IN LINE PARAMETER TO 1
;VERIFY THAT BIT 5 WAS SET

CZDHA-C MACY1 30A(10; )

CZDHAC.P11

15-MAY-78

23-AUG-78

10:02

14:40

1405

:VERIFY THAT BIT 5 WAS CLEARED

1408

005166

1418
1419

005236
005240

1409 0051764
1410 005202
1411 005210
1:.1% 005216
1413
005222
1414
005226
1415 005230
1416 005232
1417 005234

012767

012767
012767
012777
016703
012705
010513
011304
020504
001401

005242

011304

1423

005250

005005

005244
005246

005252
005254

000340

004000
005254
004000
012434
000040

172602

T44:

012516
012504
012434

104002
040513

1620

1424
;252

1%:

005704
001402

MOV

MOV
MOV
MOV
MOV
MOV
MOV
MOV
cTMP
BEQ
HLT
BIC

28:

#340,PS

#4000, 1 COUNT
#2% ESCAPE
#B81717,aDHSCR
DHLPR R3
#40,RS
RS, (R3)
(R$) R4
RS.R&4
1%

;:DISABLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
*BIT S WILL BE SET IN LINE PARAMETER
“SET BIT S
*GET CONTENTS OF LINE PARAMETER
*WAS BIT 5 SET

2
RS, (R3)

:LINE PARAMETER REGISTER ERROR
*CLEAR BIT §

ST
BEQ

R4
2$

*WAS BIT 5 CLEARED

HLT
SCOPE

MOV
CLR

104002
104400

(R%) ,R4

:READ CONTENTS OF LINE PARAMETER
:LINE PARAMETER REGISTER ERROR

1427
1428

;LINE PARAMETER REGISTER DATA TEST
:SET BIT 6 IN LINE PARAMETER TO 1

1430

*CLEAR BIT 6

1429

*VERIFY THAT BIT 6 WAS SET

}2_;}

SEQ 0039

:CLEAR BIT §

}28?

1621
1422

PAGE 29

JVERIFY THAT BIT 6 WAS CLEARED

1433

005256

1443
1444

005326
005330

1446

005334

1434 005264
1435 005272
1436 005300
1437 005306
1438 005312
1439 005316
1440 005320
16441 005322
1442 005326
1445

1447

1448

005332

005336

005340

012767

012767
012767
012777
016703
012705
010513
011304
020504
003407
104002
040513

011304

005704

001402

005005

000340

004000
005344
004000
012344
000100

172512

T45:

012426
012414
012344

18:

MOV

MOV
MOV
MOV
MOV
MOV
MOV
MOV
cTMP
BEQ
HLT
BIC

MOV

#340,PS

#4000, 1COUNT
#2$ ESCAPE
#81711,aDHSCR
DHLPR,R3
#100,RS
RS, {R3)
(R$) .R4
RS,R4
1%
2
RS, (R3)

(R%) R4

CLR
HLT
SCOPE

RS
2

BEQ

:DISABLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
“MASTER CLEAR INTERFACE
.
*SET UP POINTER TO LINE PARAMETER
*BIT 6 WILL BE SET IN LINE PARAMETER
*SET BIT 6
*GET CONTENTS OF LINE PARAMETER
*WAS BIT 6 SET
;LINE PARAMETER REGISTER ERROR
*CLEAR BIT 6

:READ CONTENTS OF LINE PARAMETER
:WAS BIT 6 CLEARED

:LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
sSET BIT 7 IN LINE PARAMETER TO 1
:VERIFY THAT BIT 7 WAS SET
;CLEAR BIT 7
sVERIFY THAT BIT 7 WAS CLEARED

MOV
MOV
MOV

#340,PS
#5700, 1COUNT
#2%,ESCAPE

:DISABLE ALL INTERRUPTS
*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST

CZDHA=C MACY11 30A(1052)
p)
23-AUG-78
CZDHAC.P1T
15-MAY=78 10:02

012777

004000
012254
000200

012254

PAGE 30
MOV
MOV

MOV
MOV

MOV

ggg
1%:

) i oh

SRS

14661

14:40

b aad

2%:

HLT

A AT

b asd

012767
012767

000340
004000
005524
004000
012164
000400

1 72332
0
012234
0

T47:

:LINE PARAMETER REGISTER ERROR

Ré

*WAS BIT 7 CLEARED

;LINE PARAMETER REGISTER ERWOR

MOV
BEQ
CLR
HLT

SCOPE

(R$) R4

2$
RS

MOV

#340,PS

MOV

#2$ ESCAPE

MOV
MOV
MOV
MOV
MOV

2%:

*CLEAR BIT 7

*READ CONTENTS OF LINE PARAMETER

#4000, 1 COUNT

#81711,aDHSCR
DHLPR,R3
#400,RS
RS, (R3)

:DISABLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS

:SET UP TO ESCAPE TO NEXT TEST

*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
*BIT 10 WILL BE SET IN LINE PARAMETER
*SET BIT 10

ggg

72,R4

(R$) R4

:GET CONTENTS OF LINE PARAMETER

HLT
BIC

2
RS,

:LINE PARAMETER REGISTER ERROR
*CLEAR BIT 10

*WAS BIT 10 CLEARED

:LINE PARAMETER REGISTER ERROR

MOV
HLT
SCOPE

(R3)

(R%) ,RG

2%
RS

*WAS BIT 10 SET

:READ CONTENTS OF LINE PARAMETER

sLINE PARAMETER REGISTER DATA TEST
sSET BIT 11 IN LINE PARAMETER TO 1
;VERIFY THAT BIT 11 WAS SET
;CLEAR BIT 11
;VERIFY THAT BIT 11 WAS CLEARED

—

—lN

<
~

242

elelelelelelelele]

&
BIBAR R
oS WO

D
)
d
D
D
d

*WAS BIT 7 SET

RS, (R3)

MOV

A4l

(I IV IV IV IV IV,

*GET CONTENTS OF LINE PARAMETER

§2.R4

*BIT 7 WILL BE SET IN LINE PARAMETZR
*SET BIT

;SET BIT 10 IN LINE PARAMETER TO 1

1500
01

—d e

(R%) R4

#200,RS
RS, (R3)

BIC

BEQ
CLR

)

;MASTER CLEAR INTERFACE
“SET UP POINTER TO LINE PARAMETER

;VERIFY THAT BIT 10 WAS SET
;CLEAR BIT 10
;VERIFY THAT BIT 10 WAS CLEARED

1%:

#BIT11,3DHSCR
DHLPR,R3

;LINE PARAMETER REGISTER DATA TEST

1489

—

SEQ 0040

T50:

MOV

#340,PS

MOV

#4000, 1 COUNT

MOV
MOV

RS, (R$)
(R%) R4

MOV
MOV
MOV
MOV

(MP

:D!SABLE ALL INTERRUPTS

:SET UP FOR 4000 ITERATIONS

#2% ,ESCAPE
#81711,aDHSCR
DHLPR,R3
#1000 RS

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
SSET UP POINTER TO LINE PARAMETER
:BIT 11 WILL BE SET IN LINE PARAMETER

RS R

“WAS BIT 11 SET

SSET BIT 11
:GET CONTENTS OF LINE PARAMETER

LEZR VR RRUN NS o

14:40

005574
005576
00 5600
005602
005604
005606
005610
005612
005614

PAGE 31
18
2
RS, (R3)

:LINE PARAMETER REGISTER ERROR
*CLEAR BIT 11

*WAS BIT 11

MOV
BEQ
CLR
HLT

SCOPE

SVERIFY THAT BIT 12

000340
004
005704
004
012004
002000

172152

PARAMETER TO 1

WAS SET

#340.PS

;:DISABLE ALL INTERRUPTS

MOV

#2% ESCAPE

“SET UP TO ESCAPE TO NEXT TEST

DHLPR,R3
#2000 ;RS

*SET UP POINTER TO LINE PARAMETER
;BIT 12 WILL BE SET IN LINE PARAMETER

MOV

MCV
MOV

MOV
MOV

#4000, 1COUNT
#1717, 3DHSCR

*SET UP FOR 4000 ITERATIONS
*MASTER CLEAR INTERFACE

RS, (R%)
(R$) R4

;SET BIT 12
*GET CONTENTS OF LINE PARAMETER

HLT

;LINE PARAMETER REGISTER ERROR

MOV

(R3) ,R4

EEG

343 &

;LINE PARAMETER REGISTER ERROR

MOV

D e

nN=0O

CLEARED

*CLEAR BIT 12
*VERIFY THAT BIT 12 WAS CLEARED

BEQ
CLR
HLT
SCOPE

?g.Ré

RS, (R3)

R4,

2$
RS
2

‘WAS BIT 12 SET

“CLEAR BIT 12

*READ CONTENTS OF LINE PARAMETER

*WAS BIT 12 CLEARED

:LINE PARAMETER REGISTER ERROR

005774

004000
011714
004000

——
N
— )

000340
004000

\l\l\lg
=&
oY

sLINE PARAMETER REGISTER DATA TEST
;SET BIT 13 IN LINE PARAMETER TO 1
;VERIFY THAT BIT 13 WAS SET
;CLEAR BIT 13
;VERIFY THAT BIT 13 WAS CLEARED
(= le e

D e P LD D D
D D e D
AN
A T A Y il ]
LY Al I A
AV AV L LY,
L L
b b b L b P

:READ CONTENTS OF LINE PARAMETER

23
RS
2

:SET BIT 12 IN LINE

TST

$) R4

:LINE PARAMETER REGISTER DATA TEST

BIC

SEQ 0041

HLT
BIC

BEQ

D D D

D D )

EEEEREREE ML
S 38 S 82 3 BURR RN

D D d D d D D

D e

D D D ) D D d s D o

D-

i iV
a

| CZDHA-C MACY11 30A(1052)
23-AUG=78
CZDHAC.P11
15-MAY=~7 10:02

MOV

#340.PS

#4000, 1COUNT

:DISABLE ALL INTERRUPTS

:SET UP FOR 4000 ITERATIONS

MOV
MOv
MOV
MOV

#2$ ESCAPE
#BIT11,@DHSCR
DHLPR.R3
#4000,R5

:SET_UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE
:SET UP POINTER TO LINE PARAMETER
:BIT 13 WILL BE SET IN LINE PARAMETER

MOV

(R5),R4

R3.RG

:GET CONTENTS OF LINE PARAMETER

HLT

:LINE PARAMETER REGISTER ERROR

MoV

(R%) R4

MOV

BIC

BEQ

RS, (R3)

RS5,(R3)

;SET BIT 13

:WAS BIT 13 SET
:CLEAR BIT 13

:READ CONTENTS OF LINE PARAMETER

;WAS BIT 13 CLEARED

CZDHA-C MACY11 30A(1052)

CZDHAC.P11
1573
1574

;g;g

005770
005772

005774

23-AUG-78

15-MAY-78 10:02

14:40

005005
104002

104400

28:

1577
1578
1579
1580
005776

012767

1593
1594

006046
006050

104002
040513

1596
1597
1598
1599

006054
006056
006060
006062

005704
001402
005005
104002

?6‘8?

006052

006064

000340

004000
004000
011624
010000

171772

011706
011674
011624

7T153:

1$:

011304

104400

28:

1602
1603

1604

1617
1618

006134
006136

1627

1628

HLT
BIC

2
RS, (R3)

;LINE PARAMETER REGISTER ERROR
*CLEAR BIT 14

ST
BEQ
CLR
HLT

Ré
2%
RS
2

*WAS BIT 14 CLEARED

MOV

SCOPE

:DISABLE A'L

INTERRUPTS

#4000, I COUNT
#28 ESCAPE
#81T11,aDHSCR
DHLPR,R3
#10000,RS
RS, (R3)
(R$) R4
RS,R%
18

*SET UP FOK 4000
ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
:BIT 14 WILL BE SET IN LINE PARAMETER
;SET BIT 14
:GET CONTENTS OF LINE PARAMETER
*WAS BIT 14 SET

(R%) R4

*READ CONTENTS OF LINE PARAMETER

:LINE PARAMETER REGISTER ERROR

:VERIFY THAT BIT 15 WAS CLEARED

006066

1621
1622
1623
1624
;232

#340,PS

JVERIFY THAT BIT 15 WAS SET

1608

1620

MOV

MOV
MOV
MOV
MOV
MOV
MOV
MOV
cTMP
BEQ

*CLEAR BIT 15

}?.89

1619

:LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
:SET BIT 15 IN LINE PARAMETER TO 1

1605

1609
1610
1611
1612
1613
1614
1615
1616

SCOPE

RS
2

:VERIFY THAT BIT 14 WAS CLEARED

1584 006004 012767
1585 006012 012767
1586 006020 012777
1587 006026 016703
1588 006032 012705
1589 006036 010513
1590 006040 011304
1591 006042 020504
1592 006044 001401
1595

CLR
HLT

SEQ 0042

;LINE PARAMETER REGISTER DATA TEST
*SET BIT 14 IN LINE PARAMETER TO 1
*VERIFY THAT BIT 14 WAS SET
*CLEAR BIT 14

Psg}
1583

PAGE 32

006074
006102
006110
006116
006122
006126
006130
006132
006140

006142

006144
006146
006150
006152
006154

012767

012767
012767
012777
016703
012705
010513
011304
020504

001401
104002

040513

011304

005704
001402
005005
104002
104400

000340

004000
006154
004000
011534
020000

171702

011616
011604
071534

TS54:

1$:

i
2%:

MOV

#340,PS

:DISABLE ALL

INTERRUPTS

MOV
MOV
MOV
MOV
MOV
MOV
MOV
CMP

#4000, 1 COUNT
#2$ ESCAPE
#81711,aDHSCR
DHLPR ,R3
#20000,RS
RS, (R3)
(R%) R4
RS R4

:SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
:BIT 15 WILL BE SET IN LINE PARAMETER
:SET BIT 15
*GET CONTENTS OF LINE PARAMETER
*WAS BIT 15 SET

BIC

RS,

*CLEAR BIT 15

ST
BEQ
CLR
HLT
SCOPE

R4
2%
RS
2

BEQ
HLT

MOV

1%
2

(R3)

(R3) ,R4

:LINE PARAMETER REGISTER ERROR

*READ CONTENTS OF LINE PARAMETER

*WAS BIT 15 CLEARED

:LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
JSET BIT 16 IN LINE PARAMETER TO 1

CZDHA-C MACY11 30A(1052) 02(3)-AUG-78

CZDHAC.PIN

15-MAY-78 10:02

14:40

1629
1630
1634
1635
163
1637
1638
1639
1640
1641

SVERIFY THAT BIT 16 WAS CLEARED
006156

006164
006172
006200

006212
006216
006220
006222

012767

012767
012767
012777
016703
012705
010513
011304
020504

1642
1643
1644

006224
006226
006230

001401
104002
040513

1646
1647
1648
1649

006234
006236
006240
006242

005704
001402
005005
104002

1645

;ggg)

006232

006244

000340

004000
006244
004000
011444
040000

171612

011526
011514
011444

T155:

1$:

011304

104400

2%:

1652
1653

1663

006246

012767

006254
006262
006270
006276

012767
012767
012777
016703

006306
006310
006312

010513
011304
020504

006302

C€12705

006314
006316
006320

001401
104002
040513

1671
1672
1673
1674

006324
006326
006330
006332

005704
001402
005005
104002

112;2

MOV

TST
BEQ
CLR
HLT

SCOPE

#4000, 1 COUNT
#2% ,ESCAPE
#81711,3DHSCR
DHLPR,R3
#40000,RS
RS, (R3)
(R$) R4
RS.R4
13
2
RS, (R3)

(R%) ,R4

R4
2
RS
2

:DISABLE ALL INTERRUPTS

“SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
;BIT 16 WILL BE SET IN LINE PARAMETER
:SET BIT 16
<GET CONTENTS OF LINE PARAMETER
“WAS BIT 16 SET
;LINE PARAMETER REGISTER ERROR
:CLEAR BIT 16

*READ CONTENTS OF LINE PARAMETER
*WAS BIT 16 CLEARED

;LINE PARAMETER REGISTER ERROR

:VERIFY THAT BIT 17 WAS CLEARED

1667
1668
1669

1670

BEQ
HLT
BIC

#340,PS

:CLEAR BIT 17

}22‘7’

1664
1665
1666

MOV
MOV
MOV
MOV
MOV
MOV
MOV
cTMP

JVERIFY THAT BIT 17 WAS SET

1655

1659
1660
1661
1662

MOV

;LINE PARAMETER REGISTER DATA TEST
:SET BIT 17 IN LINE PARAMETER TO 1

1654

1658

SEQ 0043

;VERIFY THAT BIT 16 WAS SET
:CLEAR BIT 16

}g:;g

1633

PAGE 33

006322

006334

000340

004000
006334
004000
011354

171522

011436
011424
011354

T56:

100000

MOV

011304

104400

2%:

:DISABLE ALL INTERRUPTS

#4000, 1 COUNT
#2$ ESCAPE
#81711,aDHSCR
DHLPR,R3

*SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER

MOV
MOV
CMP

RS, (R3)
(R%) R4
RS.R4

sSET BIT 17
:GET CONTENTS OF LINE PARAMETER
*WAS BIT 17 SET

MOV

1%:

#340,PS

MOV
MOV
MOV
MOV

BEQ
HLT
BIC

MOV

ST
BEQ
CLR
HLT

SCOPE

#100060.RS

1%
2
RS, (R3)

(R3) R4

R4
2%
RS
2

;BIT 17 WILL BE SET IN LINE PARAMETER

:LINE PARAMETER REGISTER ERROR
*CLEAR BIT 17

*READ CONTENTS OF LINE PARAMETER
*WAS BIT 17 CLEARED

:LINE PARAMETER REGISTER ERROR

1677

:BREAK CONTROL REGISTER DATA TEST

1679
1680

SVERIFY THAT BIT 0 WAS SET
“CLEAR BIT 0

1678

*SET BIT 0 IN BREAK CONTROL TO 1

}g}

1683

1684

;VERIFY THAT BIT 0 WAS CLEARED

00633

006344

012767

000340

004000

171432

011346

157:

MOV

#2'0,PS

#4000, 1 COUNT

:DISABLE ALL

INTERRUPTS

*SET UP FOR 4000 ITERATIONS

CZDHA=C MACY11
(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78
10:02
1685

006352

012767

14:40

006424

PAGE 34
MOV

SEQ 0044
#2% , ESCAPE

:SET UP TO ESCAPE TO NEXT TEST

1686

006360

012777

004000

MOV

#1717 ,aDHSCR

:MASTER CLEAR INTERFACE

1688
1689

006372
006376

012705
010513

000001

MOV
MOV

#1.RS
RS (R3)

*BIT 0 WILL BE SET IN BREAK CONTROL
“SET BIT 0

CMP
BEQ
HLT
BIC

RS,R&
1%
3
RS, (R3)

*WAS BIT O SET

ST
BEQ
CLR
HLT
SCOPE

R4
2%
RS
z

1687

1690

006366

006400

016703

011274

011304

MOV

1691
1692
1693
169

006402
006404
006406
006410

1696
1697
1698
1699
1700
1701
1702
1703
1704
1705

006414
006416
006420
006422
006424

1708

006426

012767

000340

1710
1711
1712
1713
1714

006442
006450
006456
006462
906466

012767
012777
016703
012705
010513

006514
004000
011204
000002

1716
1717
1718
1719

006472
006474
006476
006500

020504
001401
104003
040513

1721
1722
1723
1724
;;gg

006504
006506
006510
006512
006514

005704
001402
005005
104003
104400

1695

006412

MOV

020504
001401
104003
040513

011304

005704
001402
005005
104003
104400

2% :

1715

1720

(R%) R4

“GET CONTENTS OF BREAK CONTROL
;BREAK CONTROL REGISTER ERROR
:CLEAR BIT 0

“READ CONTENTS OF BREAK CONTROL
*WAS BIT 0 CLEARED

:BREAK CONTROL REGISTER ERROR

*CLEAR BIT 1

;VERIFY THAT BIT 1 WAS CLEARED

006434

006470

006502

012767

004000

171342

011256

T60:

011244
011174

011304

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV
MOV
MOV

#2% ,ESCAPE
#81711,aDHSCR
DHBCR,R3
#2.RS
RS (R3)

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
*BIT 1 WILL BE SET IN BREAK CONTROL
*SET BIT 1

CMP
BEQ
HLT
BIC

RS.R4
1%
3
RS, (R3)

‘WAS BIT 1

TST
BEQ
CLR
HLT
SCOPE

Ré
2%
RS
3

MOV

1$:

011304

2%:

1727
1728
1729
1730

MOV

#4000, 1 COUNT

(R3) R4

(R3) ,R4

*SET UP FOR 4000 ITERATIONS

*GET CONTENTS OF BREAK CONTROL
SET

:BREAK CONTROL REGISTER ERROR
:CLEAR BIT 1

:READ CONTENTS OF BREAK CONTROL

*WAS BIT 1 CLEARED

;BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
:SET BIT 2 IN BREAK CONTROL TO 1
*VERIFY THAT BIT 2 WAS SET
“CLEAR BIT 2

};%}

SVERIFY THAT BIT 2 WAS CLEARED

1733

006516

012767

1735
1736
1737
1738
1739
1740

006532
006540
006546
006552
006556
006560

012767
012777
016703
012705
010513
0113

1734

(R$) .R4

*SET UP POINTER TO BREAK CONTROL

:BREAK CONTROL REGISTER DATA TEST
*SET BIT 1 IN BREAK CONTROL TO 1
SVERIFY THAT BIT 1 WAS SET

};89

1709

MOV

DHBCR,R3

006524

012767

000340

004000

006604
004000
011114
000004

171252

011166
011154
011104

T61:

MOV

MOV
MOV
MOV
MOV
MOV
MOV

#350,PS

#4000, 1COUNT

#2$ ,ESCAPE
#8IT11,aDHS(R
DHBCR,R3
#4 RS
R>.(R3)
(R3) ,R4

:DISABLE ALL

*SET UP FOR 4000

INTERRUPTS

ITERATIONS

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
*BIT 2 WILL BE SET IN BREAK CONTROL
SSET BIT 2
*GET CONTENTS OF BREAK CONTROL

CZDHA=C MACY11 30A(10;2)10285AUG-78
CZDHAC.P11
15-MAY-78
17641
1742
1743
1744

006562
006564
006566
006570

1746
1747
1748
1749

006574
006576
006600
006602

1745

};;9

006572

006604

14:40

PAGE 35

1$:

P
BLQ
HLT
BIC

RS,R4
1%
3
RS, (R3)

TST
BEQ
CLR
HLT

Ré
2$
RS
3

020504
001401
104003
040513

011304

005704
001402
005005
104003

104400

28:

MOV

SCOPE

SEQ 0045

(R$) R4

:WAS BIT 2 SET
:BREAK CONTROL REGISTER ERROR
:CLEAR BIT 2

*READ CONTENTS OF BREAK CONTROL
“WAS BIT 2 CLEARED

;BREAK CONTROL REGISTER ERROR

1752
1753

;BREAK CONTROL REGISTER DATA TEST
:SET BIT 3 IN BREAK CONTROL TO 1

1755

*CLEAR BIT 3

1754,

*VERIFY THAT BIT 3 WAS SET

};gg

SVERIFY THAT BIT 3 WAS CLEARED

1758

006606

012767

000340

1760
1761

006622
006630

012767
012777

006674
004000

1759

006614

012767

1762

006636

016703

1764

006646

010513

1763

006642

012705

004000

011024

171162

011076

T62:

011064
011014

MOV

#340,PS

:DISABLE
ALL INTERRUPTS

MOV
MOV

#2$ ,ESCAPE
#81711,aDHSCR

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

MOV

000010

#4000, 1 COUNT

DHBCR ,R3

“SET UP FOR 4000 ITERATIONS

*SET UP POINTER TO BREAK CONTROL

MOV

#10.RS

(R%) R4

*GET CONTENTS OF BREAX CONTROL

MOV

RS, (R3)

:BIT 3 WILL BE SET IN BREAK CONTROL

*SET BIT 3

1765

006650

011304

MOV

1767
1768
1769

006654
006656
006660

001401
104003
040513

BEQ
HLT
BIC

1%
3
RS, (R3)

:BREAK CONTROL REGISTER ERROR
*CLEAR BIT 3

1771

006664

R&4

*WAS BIT 3 CLEARED

1766

1770

1772
1773
1774
;;;2

006652

020504

006662

011304

006666
006670
006672
006674

001402
005005
104003
104400

CMP

1%:

005704

2%:

1777
1778
1779
1780
006676

012767

1785
1786

006712
006720

012767
012777

1788

006732

012705

1790

006740

1792

006744

1789
1791

0067064

006726

006736
006742

1793
1794

006746
006750

1796

006754

1795

2$
RS
z

*READ CONTENTS OF BREAK CONTROL

:BREAK CONTROL REGISTER ERROR

JVERIFY THAT BIT 4 WAS CLEARED

1783

1787

BEQ
CLR
HLT
SCOPE

(R%) ,R4

*WAS BIT 3 SET

:BREAK CONTROL REGISTER DATA TEST
“SET BIT 4 IN BREAK CONTROL TO 1
*VERIFY THAT BIT & WAS SET
*CLEAR BIT 4

1784

MOV

RS.R&

006752

000340

012767

004000

016703

010734

006764
004000

171072

011006

T163:

010774
010724

MOV

MOV
MOV

MOV

000020

#340,PS

#4000, 1 COUNT

#2% ESCAPE
#81711,aDHSCR

DHBCR ,R3

:DISABLE ALL INTERRUPTS

“SET UP FOR 4000 ITERATIONS

“SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

*SET UP POINTER TO BREAK CONTROL

MOV

#20.R5

‘BIT 4 WILL BE SET IN BREAK CONTROL

011304

MOV

(R$) R4

:GET CONTENTS OF BREAK CONTROL

001401

BEQ

010513

MOV

020504
104003
040513

011304

005704

1$:

RS, (R3)

CMP

RS.R4

HLT
BIC

3
RS,

MOV

(R3)

n%) R4

“SET BIT 4

‘WAS BIT & SET

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 4

;READ CONTENTS OF BREAK CONTROL

*WAS BIT 4 CLEARED

14:40

BEEERBIEREINY

CZDHA=C MACY11 30A(10 52)
23-AUG-78
CZDHAC.P1
15-MAY-78 1 0:02

D D

2%:

e
D D
D
D

VONOVIBWN=O

D
D i
D

b
b e

SEREERERRE

1%:

=
VIS W

2%:

ettt

;:DISABLE ALL INTERRUPTS

MOV
MOV

#23 ,ESCAPE
#B]T17,3DHSCR

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

#4000, 1 COUNT

DHBCR R3

*SET UP FOR 4000 ITERATIONS

*SET UP POINTER TO BREAK CONTROL

MOV

#40.R5

:BIT 5 WILL BE SET IN BREAK CONTROL

MOV

(R$) R4

*GET CONTENTS OF BREAK CONTROL

RS, (R3)

“SET BIT §

8?8

?g.Rk

HLT
BIC

3
RS, (R3)

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT §

TST

R&4

*WAS BIT 5 CLEARED

MOV
BEQ
CLR
HLT

SCOPE

(R%) R4

2%
RS
3

*WAS BIT S SET

*READ CONTENTS OF BREAK CONTROL
:BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
<SET BIT 6 IN BREAK CONTROL TO 1
sVERIFY THAT BIT 6 WAS SET
;CLEAR BIT 6
;VERIFY THAT BIT 6 WAS CLEARED
000340
004000
007144
004000
010554
000100

170712

T65:

MOV

MOV
MOV

MOV

010544

MOV
MOV

1%:

“SET UP FOR 4000 ITERATIONS

#8I1T11,aDHSCR

:MASTER CLEAR INTERFACE

#2$ ,ESCAPE

égg

§2,R4

HLT

:DISABLE ALL INTERRUPTS

#4000, 1 COUNT

MOV

(R%) R4

:SET UP TO ESCAPE TO NEXT TEST

“SET UP POINTER TO BREAK CONTROL
*BIT 6 WILL BE SET IN BREAK CONTROL

*SET BIT 6

*GET CONTENTS OF BREAK CONTROL
*WAS BIT 6 SET

:BREAK CONTROL REGISTER ERROR

(R%) ,R4

*READ CONTENTS OF BREAK CONTROL

BIC

RS, (R3)

TST

WAS BIT 6 CLEARED

:BREAK CONTROL REGISTER ERROR

MOV

BEQ
CLR

2%:

#340,PS

DHBCR.R3
#100,RS
RS, (R3)

MOV

)
V2) NV

oong

#340,PS

MOV

;BREAK CONTROL REGISTER ERROR

MOV

010644
000040

D D

T64:

- b

b e

00 00 00 0o 0O Oo OO 00 00 00

000340
004
007054

D
D
D e
)

SCOPE

2%
RS
3

:VERIFY THAT SIT S WAS CLEARED

D
—

=D
e
b
e
e
D e

BEQ
CLR
HLT

SEQ 0046

sBREAK CONTROL REGISTER DATA TEST
;SET BIT 5 IN BREAK CONTROL TO 1
;VERIFY THAT BIT 5 WAS SET
*CLEAR BIT §

D
D d D
e

RER RPRE SREEEEEs 0o
W

PAGE 36

HLT
SCOPE

2%
RS

*CLEAR BIT 6

;BREAK CONTROL REGISTER DATA TEST

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P1T
15-MAY-78 10:02

14:40

PAGE 37

SEQ 0047

;SET BIT 7 IN BREAK CONTROL TO 1
;VERIFY THAT BIT 7 WAS SET
;CLEAR BIT 7
;VERIFY THAT BIT 7 WAS CLEARED

000340
004000
007234
004000
010464
000200

T66:

#340,PS

#4000, 1COUNT

#28 ESCAPE

#B8]711,aDHSCR
DHBCR,R3

#200,RS

RS, (R3)

(R$) R4

RS R
1%

SrrEraEEee
(o]
000000
NINNSN

BRSO R8BSR
SR REREREREET R PR R EZEEREREE

* ]

012767
012767
012767
012777

RS,
TST

2%:

BEQ
CLR
HLT

SCOPE

(R3)

(§3>,R4

;DISABLE ALL INTERRUPTS
sSET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
sMASTER CLEAR INTERFACE
sSET UP POINTER TO BREAK CONTROL
;BIT 7 WILL BE SET IN BREAK CONTROL
;SET BIT 7
;GET CONTENTS OF BREAK CONTROL
;WAS BIT 7 SET
;BREAK CONTROL REGISTER ERROR
;CLEAR BIT 7

sREAD CONTENTS OF BREAK CONTROL

;WAS BIT 7 CLEARED

;BREAK CONTROL REGISTER ERROR

sBREAK CONTROL REGISTER DATA TEST
sSET BIT 10 IN BREAK CONTROL TO 1
;VERIFY THAT BIT 10 WAS SET
;CLEAR BIT 10
;VERIFY THAT BIT 10 WAS (LEARED
012767
012767
012767

000340
004000
007324
004000
010374
000400

170532
010446
010434
010364

T67:

#340,PS

(k%) R4

;DISABLE ALL INTERRUPTS
sSET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
sMASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL
;BIT 10 WILL BE SET IN BREAK CONTROL
;SET BIT 10
;GET CONTENTS OF BREAK CONTROL

sBREAK CONTROL REGISTER ERROR

#4000,
1 COUNT

#2$ ESCAPE

#81717,aDHSCR
DHBCR,R3

#400,RS

RS, (R3)
RS.R4
1$

1%:

BIC

RS, (R3)

(R%),R4

2%:

;WAS BIT 10 SET

:CLEAR BIT 10
JREAD CONTENTS OF BREAK CONTROL
;WAS BIT 10 CLEARED
;BREAK CONTROL REGISTER ERROR

SCOPE

sBREAK CONTROL REGISTER DATA TEST
sSET BIT 11 IN BREAK CONTROL TO 1
;VERIFY THAT BIT 11 WAS SET
;CLEAR BIT 11
;VERIFY THAT BIT 11 WAS CLEARED
007326

012767

000340

170442

T170:

MOV

#340,PS

;DISABLE ALL

INTERRUPTS

CZDHA-C MACY1 30A(105g)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

1909
1910
1911
191;
19
1914
1915
1916

007334
007342
007350
007356
7362
007366
007370
007372

1917
1918
1919

007374
007376
007400

1921
1922
1923
1924

007404
007406
007410
007412

1920 007402

;ggg

007414

012767
012767
012777

016703
012705
010513
011304
020504

004000
007414
004000

010304
001000

14:40

010356
010344
010274

001401
104003
040513

011304

104400

28:

1927
1928

007416

1942
1943

007464
007466

007424
007432
007440
007446
007452
007456
007460
007462

012767

012767
012767
012777
016703
012705
010513
011304
020504

040513

19%6 007474
1947 ~ 007476
198 007500
1949 007502

005704
001402
005005
104003

007472

007504

000340

004000
007504
004000
010214
002000

170352

010266
010254
010204

001401
104003

007470

;355?

T71:

1%:

011304

104400

2%:

1952

ST
BEQ
CLR
HLT

(R$) R4

Ré
2$
RS

*READ CONTENTS OF BREAK CONTROL

“WAS BIT 11 CLEARED

;BREAK CONTROL REGISTER ERROR

SCOPE

MOV

#340,PS

MOV
MOV
MOV
MOV
MOV
MOV
MOV
cTMP

#4000, 1COUNT
#28 ,ESCAPE
#81711,aDHSCR
DHBCR,R3
#2000 RS
RS, (R$)
(R$) R4
RS.R%

BIC

RS,

ST
BEQ
CLR
HLT

R4
2s
RS

BEQ
HLT

MOV

1%
3

(R3)

(R$) R4

SCOPE

:DISABLE ALL INTERRUPTS

“SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
;BIT 12 WILL BE SET IN BREAK CONTROL
;SET BIT 12
“GET CONTENTS OF BREAK CONTROL
*WAS BIT 12 SET
;BREAK CONTROL REGISTER ERROR
:CLEAR BIT 12

*READ CONTENTS OF BREAK CONTROL

*WAS BIT 12 CLEARED

;BREAK CONTROL REGISTER ERROR

*SET BIT 13 IN BREAK CONTROL TO 1
SVERIFY THAT BIT 13 WAS SET

1955

“CLEAR BIT 13

1958

007506

012767

1964

007546

010513

1959
1960
1961
1962
1963

MOV

:BREAK CONTROL REGISTER ERROR
*CLEAR BIT 11

;BREAK CONTROL REGISTER DATA TEST

1953
1954

}%9

1%
3
RS, (R3)

*SET UP POINTER TO BREAK CONTROL
:BIT 11 WILL BE SET IN BREAK CONTROL
;SET BIT 11
:GET CONTENTS OF BREAK CONTROL
“WAS BIT 11 SET

JVERIFY THAT BIT 12 WAS CLEARED

1933

1945

BEQ
HLT
BIC

DHBCR,R3
#1000 RS
RS, (RS)
(R%) R4
RS,Ré

:SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

:VERIFY THAT BIT 12 WAS SET
*CLEAR BIT 12

13%}

1944

#4000, I COUNT
#2$ ESCAPE
#81717,aDHSCR

;BREAK CONTROL REGISTER DATA TEST
*SET BIT 12 IN BREAK CONTROL TO 1

1929
1930

1934
1935
1936
1937
1938
1939
1940
1941

SEQ 0048

MOV
MOV
MOV

MOV
MOV
MOV
MOV
CMP
1%:

005704
001402
005005
104003

PAGE 38

007514
007522
007530
007536
007542

012767
012767
012777
016703
012705

“VERIFY THAT BIT 13 WAS CLEARED

000340

004000
007574
004000
010124
004000

170262

010176
010164
010114

T172:

MOV

MO\
MOV
MOV
MOV
MOV
MOV

#340,PS

;:DISABLE ALL INTERRUPTS

RS. (R%)

:SET BIT 13

#4000, 1COUNT
#28 _ESCAPE
#8]711,aDHSCR
CR,R3
#5900 RS

*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
:BIT 13 WILL BE SET IN BREAK CONTROL

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

1965
1966

007550
007552

1967
1968
1969

007556
007556
007560

1971
1972
1973
1974

007564
007566
007570
007572

1970

;g;g

007562

007574

14:40

011304
020504

MOV
CMP

001401
104003
040513

1$:

011304

005704
001402
005005
104003

104400

28:

1977
1978
1979
1980

1995

1996
1997
1998
1999

2283?

(R3) R4
RS,R4

BEQ
HLT
BIC

1%
%
RS, (R3)

TST
BEQ
CLR
HLT

R
2$
RS
z

MOV

SCOPE

(R$) R4

;GET CONTENTS OF BREAK CONTROL
‘WAS BIT 13 SET
;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 13

*READ CONTENTS OF BREAK CONTROL
*WAS BIT 13 CLEARED

;BREAK CONTROL REGISTER ERROR

*VERIFY THAT BIT 14 WAS CLEARED
007576

1984 0076064
1985 007612
1986 007620
1987 007626
1988 007632
1989 007636
1990 007640
1991 007642

1992
1993
1994

SEQ 0049

;BREAK CONTROL REGISTER DATA TEST
*SET BIT 14 IN BREAK CONTROL TO 1
*VERIFY THAT BIT 14 WAS SET
*CLEAR BIT 14

}gg;

1983

PAGE 39

012767

012767
012767
012777
016703
012705
010513
011304
020504

007644
007646
007650

001401
104003
040513

007654
007656
007660
007662

005704
001402
005005
104003

007652

007664

000340

004000
007664
004000
010034
010000

170172

010106
010074
010024

T73:

:
1%:

011304

104400

2%:

MOV

MOV
MOV
MOV
MOV
MOV
MOV
MOV
CMP
BEQ
HLT
BIC

MOV
ST
BEQ
CLR
HLT

SCOPE

#340,PS

#4000, I COUNT
#2$ ,ESCAPE
#81711,aDHSCR
DHBCR,R3
#10000,RS
RS, (R3)
(R$) R4
RS,R%
1$
z
RS . (R3)

(R%) R4

R4
2
RS
5

:DISABLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL
:BIT 14 WILL BE SET IN BREAK CONTROL
;SET BIT 14
:GET CONTENTS OF BREAK CONTROL
‘WAS BIT 14 SET
;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 14

*READ CONTENTS OF BREAK CONTROL
*WAS BIT 14 CLEARED

;BREAK CONTROL REGISTER ERROR

200

;BREAK CONTROL REGISTER DATA TEST

204

JVERIFY THAT BIT 15 WAS SET

203

*SET BIT 15 IN BREAK CONTROL TO 1

2005

22889

*CLEAR BIT 15

2008

007666

012767

2014

007726

010513

2017
2018
2019

007734
007736
007740

2009 007674
2010 007702
2011 007710
2012 007716
2013 007722

2015
2016

2020

007730
007732

007742

000340

012767 004000
012767 007754
012777 004000
016703 007744
012705 020000

170102

010016
010004
007734

T74:

011304
020504

001401
104003
040513

011304

*VERIFY THAT BIT 15 WAS CLEARED

MOV

#340,PS

MOV

RS, (R3S

MOV
MOV
MOV
MOV
MOV
MOV
CMP

18:

BEQ
HLT
BIC

MOV

:DISABLE ALL INTERRUPTS

#4000, 1 COUNT
#2$ ,ESCAPE
#81711,aDHSCR
DHBCR,R3
#20000 ,RS

*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
:egr 15 WILL BE SET IN BREAK CONTROL

(R$) R4
RS.R&

*GET CONTENTS OF BREAK CONTROL
‘WAS BIT 15 SET

1%
3
R>, (R3)

(R%) R4

;SET BIT 1

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 15

*READ CONTENTS OF BREAK CONTROL

CZDHA=C MACY11

CZDHAC.P11
2021

2022

2023
2024

228222

007744

007746

007750
007752

007754

30A(1052)102(3)5AUG-78

15-MAY-78

14:40

005704

001402

005005
104003

104400

28:

007756

012767

012767
012767
012777
016703
012705

2039 010016 010513
2040 010020 011304
2041 010022 020504

2042
2043
2044

010026
010026
010030

2046
2047
2048
2049

010034
010036
010040
010042

010032

010044

000340

004000
010044
004000
007654
040000

170012

007726
007714
007644

T75:

001401
104003
040513

1$:

011304

005704
001402
005005
104003

104400

28:

010046

2067
2068
2069

010114
010116
010120

2071
2072

010124
010126

005704
001402

010132

104003

2059 010054
2060 010062
2061 010070
2062 010076
2063 010102
2064 010106
2065 010110
2066 010112

2075

;BREAK CONTROL REGISTER ERROR

SCOPE

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV
MOV
MOV

#4000, 1COUNT
#2$ ESCAPE
#81711,aDHSCR
DHBCR,R3
#40000 RS

*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
:BIT 16 WILL BE SET IN BREAK CONTROL

BEQ
HLT
BIC

1%
3
RS, (R3)

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 16

MOV
ST
BEQ
CLR
HLT

SCOPE

RS, (R3S
(R$) R4
RS,R%
(R3) R4

;SET BIT 16
*GET CONTENTS OF BREAK CONTROL
“WAS BIT 16 SET

*READ CONTENTS OF BREAK CONTROL

Ré
2
RS
3

‘WAS BIT 16 CLEARED

;BREAK CONTROL REGISTER ERROR

:VERIFY THAT BIT 17 WAS CLEARED

2058

2073

RS
B

;BREAK CONTROL REGISTER DATA TEST
“SET BIT 17 IN BREAK CONTROL TO 1
*VERIFY THAT BIT 17 WAS SET
*CLEAR BIT 17

zzggg

2074

CLR
HLT

MOV
MOV
CMP

2052
2053
2054
2055

2070

;WAS BIT 15 CLEARED

:VERIFY THAT BIT 16 WAS CLEARED

007764
2035 007772
2036 010000
2037 010006
2038 010012

583?

;BREAK CONTROL REGISTER DATA TEST
:SET BIT 16 IN BREAK CONTROL TO 1
:VERIFY THAT BIT 16 WAS SET
*CLEAR BIT 16

228_;,}

2045

SEQ 0050

BEQ

2027
2028
2029
2030
2033

PAGE 40

010122
010130
010134

012767

012767
012767
012777
016703
012705
010513
011304
020504
001401
104003
040513

011304

000340

004000
010134
004000
007564
100000

167722

007636
007624
007554

T76:

1$:

005005

104400

MOV

MOV
MOV
MOV
MOV
MOV
MOV
MOV
cMP
BEQ
HLT
BIC

MOV

#4000, 1 COUNT
#2$ ESCAPE
#8]1711,aDHSCR
DHBCR,R3
#100000.RS
RS, (R3)
(R$) R4
RS.R4
1%
3
RS, (R3)
R
2$

HLT

SCOPE

:DISABLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
;BIT 17 WILL BE SET IN BREAK CONTROL
;SET BIT 17
*GET CONTENTS OF BREAK CONTROL
‘WAS BIT 17 SET
;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 17

(R%) R4

TST
BEQ

CLR

2%:

#340,PS

:READ CONTENTS OF BREAK CONTROL

“WAS BIT 17 CLEARED
.

;BREAK CONTROL REGISTER ERROR

CZDHA=C MACY11 30A(10;2)1 23-AUG-78

CZDHAC.P11

15-MAY=78

10:02

14:40

PAGE 41

2077
2078
2079
2080
2081

;SILO STATUS REGISTER DATA TEST
:SET BIT 0 IN SILO STATUS TO 1
SVERIFY THAT BIT O WAS SET
*CLEAR BIT 0
*VERIFY THAT BIT 0 WAS CLEARED

2083

010136

012767

000340

2085
2086
2087
2088
2089

010152
010160
010166
010172
010176

012767
012777
016703
012705
010513

010234
004000
007476
000001

010202

042704

000700

2084

2090
2091

2092

010144

010200

010206

012767

011304

020504

2093
2096
2095

010210
010212
010214

001401
104004
040513

2097
2098
2099
2100
2101

010220
010224
010226
010230
010232

042704
005704
001402
005005
104004

2096

5%8%

010216

010234

011304

004000

167632

007546

T77:

067534
007464

000700

104400

28:

012767

000340

2112
2113
2114
2115
2116

010252
010260
010266
010272
010276

012767
012777
016703
012705
010513

010334
004000
007376
000002

010244

012767

2117
2118

010300
010302

011304
042704

2120

010310

001401

010306

020504

2121
2122

010312
010314

104004
040513

2124
2125
2126
2127
2128

010320
010324
010326
010330
010332

042704
005704
001402
005005
104004

g;gg
2131
2132

:DISABLE
ALL INTERRUPTS

MOV
MOV
MOV
MOV
MOV

#2$ ,ESCAPE
#81711,aDHSCR
DHSSR,R3
#1.RS
RS . (R3)

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
“SET UP POINTER TO SILO STATUS
:BIT 0 WILL BE SET IN SILO STATUS
*SET BIT 0

BIC

#700.R4

BEQ
HLT
BIC

18
4
RS, (R3)

BIC
ST
BEQ
CLR
HLT

#700.R4
R4
2$
RS
.
4

MOV

SCOPE

#4000, 1 COUNT

(R$) R4

RS.R&

(R3) ,R4

“SET UP FOR 4000 ITERATIONS

:GET CONTENTS OF SILO STATUS

:CLEAR UNWANTED BITS

;WAS BIT O SET

:SILO STATUS REGISTER ERROR
*CLEAR BIT 0

*READ CONTENTS OF SILO STATUS

;CLEAR UNWANTED BITS
;WAS BIT O CLEARED

:SILO STATUS REGISTER ERROR

;SILO STATUS REGISTER DATA TEST
:SET BIT 1 IN SILO STATUS TO 1
:VERIFY THAT BIT 1 WAS SET
*CLEAR BIT 1
*VERIFY THAT BIT 1 WAS CLEARED
010236

2123

#340,PS

MOV

CMP

1%:

2110

2119

MOV

2104
2105
2106
2107
g}gg

2111

SEQ 0051

010316

010334

011304

104400

004000

167532

007446

T100:

007434
007364

000700

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV
MOV
MOV

#2$ ESCAPE
#81711,aDHSCR
DHSSR,R3
#2.RS
RS’ (R3)

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO SILO STATUS
*BIT 1 WILL BE SET IN SILO STATUS
“SET BIT 1

MOV

MOV
BIC

(R%) ,R4
#700.R4

BEQ

CMP

1$:
000700

#4000, 1 COUNT

RS,R&

HLT
BIC

4
RS, (R3)

BIC
TST
BEQ
CLR
HLT

#700.R4
R4
2%
RS
4

MOV

SCOPE

(R%) R4

“SET UP FOR 4000 ITERATIONS

*GET CONTENTS OF SILO STATUS
;CLEAR UNWANTED BITS
;WAS BIT 1 SET

:SILO STATUS REGISTER ERROR
:CLEAR BIT 1

*READ CONTENTS OF SILO STATUS

:CLEAR UNWANTED BITS
:WAS BIT 1 CLEARED

;SILO STATUS REGISTER DATA TEST
:SET BIT 2 IN SILO STATUS TO 1

:SILO STATUS REGISTER ERROR

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P1115-MAY-78 10:02

14:40

PAGE 42

&
SEQ 0052

2133

:VERIFY THAT BIT 2 WAS SET

%}_;‘2

;VERIFY THAT BIT 2 WAS CLEARED

2134

*CLEAR BIT 2

2137

010336

2145
2146
2147
2148
2149
2152
2153
2154
2155

2138
2139
2140
2141
2142
2143
2144

012767

000340

010402
010406
010410
010412
010414

042704
020504
001401
104004
040513

000700

010624
010426
010430
010432

005704
001402
005005
104004

010344
010352
010360
010366
010372
010376
010400

012767
012767
012777
016703
012705
010513
011304

2150 010416 011304
2151 010420 042704

5};9 010434

004000
010434
004000
007276
000004

167432

007346
007334
007264

T101:

.
i$:

:
000700

104400

2%:

MOV

MOV
MOV
MOV
MOV
MOV
MOV
MOV
BIC
CMP
BEQ
HLT
BIC

MOV
BIC
ST
BEQ
CLR
HLT

SCOPE

#340,PS

#5000, 1COUNT
#2$ ESCAPE
#B81711,aDHSCR
DHSSR,R3
#4 RS
RS (R3)
(R%) ,R4
#700.R4
RS, R4
1%
4
RS, (R3)

:DISABLE ALL INTERRUPTS

“SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
“MASTER CLEAR INTERFACE
*SET UP POINTER TO SILO STATUS
:BIT 2 WILL BE SET IN SILO STATUS
*SET BIT 2
*GET CONTENTS OF SILO STATUS

;CLEAR UNWANTED BITS
:WAS BIT 2 SET

- ;SILO STATUS REGISTER ERROR
*CLEAR BIT 2

(R$) R4
#700.Ré4

*READ CONTENTS OF SILO STATUS
;CLEAR UNWANTED BITS

R4
2$
RS
4

:WAS BIT 2 CLEARED

;SILO STATUS REGISTER ERROR

2158

;SILO STATUS REGISTER DATA TEST

2160

*VERIFY THAT BIT 3 WAS SET

2159

*SET BIT 3 IN SILO STATUS TO 1

2161

:CLEAR BIT 3

5}2%

:VERIFY THAT BIT 3 WAS CLEARED

2164

010436

012767

000340

2172

010502

042704

000700

2165
2166
2167
2168
2169
2170
2171
2173

2174
2175
2176

2177
21;8

2179
2180
2181
2182

5;32
2185

2186
2187
2188

010444
010452
010460
010466
010472
010476
010500
010506

010510
010512
010514

010516
010520

010524
010526
010530
010532

010534

012767 004000
012767 010534
012777 004000
016703 007176
012705 000010
010513
011304
020504

001401
104004
040513

011304
042704

005704
001402
005005
104004

104400

167332

007246
007234
007164

T1102:

MOV

MOV
MOV
MOV
MOV
MOV
MOV
MOV
BIC

#700 R4

BEQ
HLT
BIC

13
A
RS, (R3)

ST
BEQ
CLR
HLT

Ré
2%
RS
4

cMP

1%:

000700

28:

#340,PS

#4000,
1COUNT
#28 ESC
#8171, aDHSCR
DHSSR,R3
#10,RS
RS, (R3)
(R%) ,R4

MOV
BIC

SCOPE

RS.R4

(RS, R4
#700.Ré4

;:DISABLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO SILO STATUS
:BIT 3 WILL BE SET IN SILO STATUS
“SET BIT 3
*GET CONTENTS OF SILO STATUS

:CLEAR UNWANTED BITS

:WAS BIT 3 SET

:SILO STATUS REGISTER ERROR
:CLEAR BIT 3

*READ CONTENTS OF SILO STATUS
;CLEAR UNWANTED BITS
;WAS BIT 3 CLEARED

;SILO STATUS REGISTER ERROR

;SILO STATUS REGISTER DATA TEST

“SET BIT &4 IN SILO STATUS TO 1
SVERIFY TrAT BIT 4 WAS SET
“CLEAR BIT 4

CZDHA=C MACY11 30A(1052)

CZDHAC.P11

23-AUG-78

15-MAY-78 10:02

14:40

PAGE 43

g}sg

:VERIFY THAT BIT & WAS CLEARED

191

010536

2193

010552 012767 010634

192

%191.
195

010544

012767

010560
010566

012777
016703

2197
2198
2199

010576
010600
010602

010513
011304
042704

2201
220§
2203

010610
010612
010614

001401
104004
040513

2205

010620

042704

2199 010572

012705

2200 010606 020504

2204

2206
2207
2208
2209

5519

010616

010624
010626
010630
010632

010634

011304

005704
001402
005005
104004

000340

167232

004000

007146

004000
007076
000020

007064

T103:

007134

000700

2233
223,
2235
2236

gggg
2239
2240
2241
2242
2243

:DISABLE ALL

MOV

#2$ ESCAPE

*SET UP TO ESCAPE TO NEXT TEST

1%:

000700

104400

28:

#4000, 1 COUNT

:SET UP FOR 4000

INTERRUPTS

ITERATIONS

MOV
MOV

#B8]717,aDHSCR
DHSSR,R3

MOV
MOV
BIC

RS, (R3)
(R$) R4
#700.R4

*SET BIT 4
*GET CONTENTS OF SILO STATUS
;CLEAR UNWANTED B;TS

BEQ
HLT
BIC

1%
4
RS, (R3)

:SILO STATUS REGISTER ERROR
*CLEAR BIT &

BIC

#700.R4

MOV
ST
BEQ
CLR
HLT

SCOPE

#20,RS

RS,R&

(R3) R4

Ré
2$
RS
4

“MASTER CLEAR INTERFACE
*SET UP POINTER TO SILO STATUS

*BIT & WILL BE SET IN SILO STATUS

:WAS BIT & SET

*READ CONTENTS OF SILO STATUS

;CLEAR UNWANTED BITS

;WAS BIT 4 CLEARED
;SILO STATUS REGISTER ERROR

;SILO STATUS REGISTER DATA TEST
“SET BIT S IN SILO STATUS TO 1
*VERIFY THAT BIT 5 WAS SET
*CLEAR BIT §

*VERIFY THAT BIT 5 WAS CLEARED
010636

219
010644
2220 010652
2221 010660
2222 010666
2223 010672
2224 010676
2225 010700
2226 010702
2227 010706

2231
2232

#340,PS

cTMP

5«3}9

2228
2229
2230

MOV

2212
2213
2214
2215
218

SEQ 0053

010710
010712
010714

010716
010720

010724
010726
010730
010732

010734

012767

012767
012767
012777
016703
012705
010513
011304
042704
020504

000340

004000
010734
004000
006776
000040

005704
001402
005005
104004

104400

T104:

000700

001401
104004
040513

011304
042704

167132

007046
007034
006764

1$:

000700

2%:

MOV

MOV
MOV
MOV
MOV
MOV
MOV
MOV
BIC
cMP

#340,PS

#4000, 1 COUNT
#2$ ESCAPE
#81717,aDHSCR
DHSSR,R3
#40,RS
RS, (R3)
(R%) ,R4
#700.R4
RS.R4

BEQ
HLT
BIC

1%
4
RS, (R3)

ST
BEQ
CLR
HLT

R
2$
RS
4

MOV
BIC

SCOPE

(R%) ,R4
#700.Ré4

:DISASLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO SILO STATUS
:BIT S WILL BE SET IN SILO STATUS
*SET BIT §
*GET CONTENTS OF SILO STATUS
:CLEAR UNWANTED BITS
:WAS BIT 5 SET
:SILO STATUS REGISTER ERROR
*CLEAR BIT 5

*READ CONTENTS OF SILO STATUS
;CLEAR UNWANTED BITS

;SILO STATUS REGISTER DATA TEST
*SET BIT 17 IN SILO STATUS TO 1
*VERIFY THAT BIT 17 WAS SET
*CLEAR BIT 17
“VERIFY TrAT BIT 17 WAS CLEARED

;WAS BIT 5 CLEARED

;SILO STATUS REGISTER ERROR

| CZDHA-C MACY11 30AC1052)

23-AUG-78

CZDHAC.P11

15-MAY-78

10:02

2265
2266
2247
2248
2249
2830

010736
010744
010752
Q10760
010766
0107z

012767
012767
012767
012777
016703
012705

000340
004000
011036
004000
006676
100000

2252
253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265

Q11000
011002
011006
011010
011012
011014
011016
011020
011024
011026
011030
011032
011034

2266
2267
2068
2269
2270
2271
2272
2273
2274
2275
2276
2277

010776

010513

011
042704
020504
001401
104004
040513
011304
042704
005704
001402
005005
104004
104400

14: 40

167032
006746
006734
006664

PAGE 44

T105:

MoV

#340 PS

MOV

#2$ ESCAPE

MOV

DHSSR,R3

MOV

000700

:MASTER CLEAR INTERFACE

#100000 RS
RS, (R3)

(R$) ,R4

4
RS,

BIC

#700.R4

2%:

#B8]711,aDHSCR

HLT
BIC

BEQ
CLR
HLT

SCOPE

INTERRUPTS

“SET UP FOR 4000

#700.R4

MOV

;:DISABLE ALL

#4000, 1 COUNT

BIC

5?8
1%:

SEQ 0054

?2.R4

(R3)

(R%) ,R4

2$
RS
4

ITERATIONS

“SET UP TO ESCAPE TO NEXT TEST

“SET UP POINTER TO SILO STATUS

;BIT 17 WILL BE SET IN SILO STATUS

;SET BIT 1

*GET CONTENTS OF SILO STATUS

:CLEAR UNWANTED BITS

:WAS BIT 17 SET
:SILO STATUS REGISTER ERROR
“CLEAR BIT 17

*READ CONTENTS OF SILO STATUS

;CLEAR UNWANTED BITS

:WAS BIT 17 CLEARED

:SILO STATUS REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
“CLEAR BIT 0
*VERIFY THAT BIT 0 WAS CLEARED
*RESTORE BIT 0
*VERIFY THAT BIT O WAS SET

228

011036
011044
011052
011060
011066
011072

012767
012767
012767
012777
016703
012705

000340
004000
011140
004000
006564
177766

2280

011076

012713

2282
2283
2284
2285
2286
2287
2288
2289
2290
2291

011102
011106
011110
011112
011114
011116
011122
011126
011130
011132

042713
011304
020504
001401
104002
052713
011304
022704
001403
012705

2293
229
2295
22%
2297
2098
2299
2300

011136
011140

104002
104400

166732
006646
006634
006564

T106:

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV
MOV

#2$ ,ESCAPE
#81711,aDHSCR
DHLPR,R3
#177766 RS

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO LINE PARAMETER
: (RS)=EXPECTED DATA

177767

MOV

#177767, (R3)

*SET ALL READ/WRITE BITS

000001

BIC

#1,

g?g

?2,R4

HLT
BIS

2
#1,

000001

MOV

1$:

177767

MOV
CMP

BEQ
MOV

177767
-

g%éps

#4000, 1 COUNT

(R3)

(R3) R4
(R3)

(R3) ,R4
#177767 R4
2$
#177767.RS
2

*SET UP FOR 4000 ITERATIONS

*IN LINE PARAMETER REGISTER, 177766
*IN LINE PARAMETER REGISTER

;CLEAR BIT 0

;GET CONTENTS OF LINE PARAMETER

*WAS BIT 0 CLEARED

:LINE PARAMETER REGISTER ERROR
SSET BIT'0

;WAS BIT O SET
; (RS)=EXPECTED DATA IN

*LINE PARAMETER REGISTER, 177767

*LINE PARAMETER REGISTER ERROR

sLINE PARAMETER REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
;CLEAR BIT 1
JVERIFY TrAT BIT 1 WAS CLEARED
;RESTORE BIT 1

CZDHA=C MACY11 30A(1052)10285AUG-78
CZDHAC.P1
15-MAY-78

14:40

PAGE 45

SEQ 0055

2301
2302
2303
2304
2305
2306
2307
gggg

011142
011150
011156
011164
011172
011176

012767
012767
012767
012777
016703
012705

000340
004000
011244
004000
006460
177765

gg}?

011202

012713

177767

#177767, (R3)

2312
2313
2314
2315
2316
2317
2318
2319
2320
%%5%

011206
011212
011214
011216
011220
011222
011226
011230
011234
011236

042713
011304
020504
001401
104002
052713
011304
022704
001403
(C12705

000002

#2, (R3)

2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
Sggg

011242
011244

104002
104400

;VERIFY THAT BIT 1 WAS SET
166626
006542
006530
006460

T107:

#340,PS

:DISABLE ALL INTERRUPTS

#28 ESCAPE

aaxf11.§ouscn

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

#177765.RS

: (RS)=EXPECTED DATA

#4000,
1 COUNT

*SET UP FOR 4000 ITERATIONS

DHLPR R

(R$) R4

RS,R&
1%

000002

#2, (R3)

177767

(R$) R4
#177767
R4

177767

#177767
,RS

:SET UP POINTER TO LINE PARAMETER

*IN LINE PARAMETER REGISTER, 177765
“SET ALL READ/WRITE BITS
*IN LINE PARAMETER REGISTER
;CLEAR BIT 1
:GET CONTENTS OF LINE PARAMETER
*WAS BIT 1 CLEARED
;LINE PARAMETER REGISTER ERROR
;SET BIT 1
;WAS BIT 1 SET

2%:

: (RS)=EXPECTED DATA IN
;LINE PARAMETER REGISTER, 177767

HLT
SCOPE

;LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S

;CLEAR BIT 2
;VERIFY THAT BIT 2 WAS (LEARED
;RESTORE BIT 2
;VERIFY THAT BIT 2 WAS SET
011246

011254
011262
011270
011276
C11302

012767

012767
012767
012777
016703
012705

000340

004000
011350
004000
006354
177763

166522
006436
006424
006354

#340,PS

T110:

#4000,
1 COUNT

#2$,ESCAPE
#B1711,aDHSCR

DHLPR,R3

#177763.RS

ggzg

011306

012713

177767

#177767, (R3)

2342
2343
2344
2345
2346
2347
2348
2349
2350
%%g}

011312
011316
011320
011322
011324
011326
011332
011334
011340
011342

042713
011304
020504
001401
104002
052713
011304
022704
001403
012705

000004

#4,(R3)

2353
sggg

011346
011350

104002
104400

(RS) R4

RS.R4
1%

000004

1%:

#4,

(R3)

177767

(R%) R4
#177767
R4

177767

#177767
,R5

2%:

HLT
SCOPE

;DISABLE ALL INTERRUPTS

:SET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
sMASTER CLEAR INTERFACE
;SET UP POINTER TO LINE PARAMETER
; (R5)=EXPECTED DATA
;IN_LINE PARAMETER REGISTER, 177763
sSET ALL READ/WRITE BITS
: IN_LINE PARAMETER REGISTER
;CLEAR BIT 2
;GET CONTENTS OF LINE PARAMETER
;WAS BIT 2 CLEARED
;LINE PARAMETER REGISTER ERROR
;SET BIT 2

;WAS BIT 2 SET

; (RS)=EXPECTED DATA IN

;LINE PARAMETER REGISTER,

177767

sLINE PARAMETER REGISTER ERROR

sLINE PARAMETER REGISTER DATA TEST

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

2%57
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369

14:40

PAGE 46

SEQ 0056

EgEgAaLgI§EQD/URITE BITS IN LINE PARAMETER REGISTER TO 1S

*VERIFY THAT BIT 4 WAS CLEARED
*RESTORE BIT 4
*VERIFY THAT BIT &4 WAS SET
011352
011360
011366
011374
011402
011406

012767
012767
012767
012777
016703
012705

2376
2377
2378
2379

0N
011432
011436
011440

104002
052713
011304
022704

2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2600
2401
2402
2403
26404
2605
26406
2607
2408
2409
2410
2411

011446

012705

011452
011454

104002
104400

000340
004000
011454
004000
006250
177747

166416

Ak R

MOV

:DISABLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS

MOV
MOV

#81711,aDHSCR
DHLPR,R3

“MASTER CLEAR INTERFACE
SET UP POINTER TO LINE PARAMETER

177767

MOV

#177767, (R3)

000020

BIC

#20, (R3)

*IN LINE PARAMETER REGISTER, 177747
*SET ALL READ/WRITE BITS
“IN LINE PARAMETER REGISTER
*CLEAR BIT 4

g?z

72,R4

*WAS BIT 4 CLEARED

:LINE PARAMETER REGISTER ERROR

(R3) ,R%
#177767 R4

;WAS BIT & SET

000020

MOV

#340.PS

#4000, 1 COUNT

MOV

1%:

177767

HLT

BIS

MOV
CMP

BEQ
MOV

177767

’%:

g%épf

#2$ ,ESCAPE

#177747 RS

(R3S ,R&

#20, (R3)

:SET UP TO ESCAPE TO NEXT TEST

: (RS)=EXPECTED DATA

*GET CONTENTS OF LINE PARAMETER

*SET BIT 4

2
#177767 .RS

: (RS)=EXPECTED DATA IN

*LINE PARAMETER REGISTER ERROR

*LINE PARAMETER REGISTER, 177767

;LINE PARAMETER REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
;CLEAR BIT 5

;VERIFY THAT BIT 5 WAS CLEARED
;RESTORE BIT 5
;VERIFY THAT BIT 5 WAS SET
011456
(011464
011472
011500
011506
011512

012767
012767
012767
012777
016703
012705

011516
011522
011526
011530
011532
011534
011536
011542
011544
011550
011552

000340
004000

T112:

011560

004000
006144

MOV

#340,PS

;:DISABLE ALL INTERRUPTS

MOV

#2%, ESCAPE

*SET UP TO ESCAPE TO NEXT TEST

MOV

#4000, 1 COUNT

177727

MOV

#177727.RS

012713

177767

MOV

#177767. (R3)

042713
011304
020504
001401
104002
052713
011304
022704
001403
012705

000040

BIC

#40, (R3)

égg

qg.n4

000040
177767
177767

MOV

1%:

HLI

(R3S ,R&4

BIS

#40, (R3)

CMP
BEQ
MOV

#177967 R4
2%
8177767 .KS

MOV

(P3R4

*SET UP FOR 4000 ITERATIONS
.

: (RS)=EXPECTED DATA

LINE

PARAMETER

*IN LINE PARAMETER REGISTER, 177727
*SET ALL READ/WRITE BITS
*IN LINE PARAMETER REGISTER
*CLEAR BIT §

:GET CONTENTS OF LINE PARAMETER
‘WAS BIT 5 CLEARED

;LINE PARAMETER REGISTER ERROR

*SET BIT 5

;WAS BIT 5 SET
: (RS)=EXPECTED DATA IN
;LINE PARAMETER REGISTER,

177767

CZDHA=-C MACY1 3OA(‘|0;2)1 23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

2413

gz;g

011556

011560

14:40

104002

104400

PAGE 47

2%:

2416
2417
2418
2419
2420

011562

012767

000340

2625
2626

011576
011604

012767
012777

011664
004000

011616

012705

177667

2628

2429
26430
2431
2632

2433
243
26435
2636
2437
2438

2439

2640
2441
2442
2643
5???

011570

011612

012767

016703

011622

012713

011626
011632
011634
011636
011640
011642
011646

042713
011304
020504
001401
104002
052713
011304

011654
011656

001403
012705

011662

104002

011650

011664

022704

004000

006040

166206

006122

T113:

006110
006040

)
177767

000100

1$:

177767

104400

2%:

:LINE PARAMETER REGISTER ERROR

#2$ ,ESCAPE
#81717,aDHSCR

#4000, 1 COUNT

DHLPR,R3

MOV

#177667 RS

MOV

#177767. (R3)

BIC
MOV
CMP
BEQ
HLT
BIS
MOV

#100, (R3)
(R3) .R4
RS.R%
1%
2
#100, (R3)
(R3) ‘R4

HLT

SCOPE

#177767 R4
2$
#177767.RS

:DISABLE ALL INTERRUPTS

“SET UP FOR 4000 ITERATIONS

“SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

SET UP POINTER TO LINE PARAMETER

; (RS)=EXPECTED DATA

*IN LINE PARAMETER REGISTER, 177667
*SET ALL READ/WRITE BITS
*IN LINE PARAMETER REGISTER
*CLEAR BIT 6

“GET CONTENTS OF LINE PARAMETER
‘WAS BIT 6 (LEARED
:LINE PARAMETER REGISTER ERROR
*SET BIT 6

;WAS BIT 6 SET
: (RS)=EXP:CTED DATA IN

*LINE PARAMETER REGISTER, 177767
*LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
*CLEAR BIT 7
*VERIFY THAT BIT 7 WAS CLEARED
*RESTORE BIT 7

JVERIFY THAT BIT 7 WAS SET
011666

012767

000340

2455
2456
2457
2458
2459

011702
011710
011716
011722

012767
012777
016703
012705

011770
004000
005734
177567

011726

012713

011732
011736
011740
011742

011746

011674

2666

011744

2468

011752

2467

MOV
MOV

CMP

177767

2453

2461
2462
2463
2464
2465

#340,PS

MOV

BEQ
MOV

Sfig}

2460

MOV

2446
2447
2448
2449
2450

2454

*VERIFY THAT BIT 6 WAS SET

2423

2627

SCOPE

:LINE PARAMETER REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
*CLEAR BIT 6
*VERIFY THAT BIT 6 WAS CLEARED
*RESTORE BIT 6

Sfi%}

2624

HLT

SEQ 0057

MOV

#340,PS

;:DISABLE ALL INTERRUPTS

MOV
MOV
MOV
MOV

#2$ ,ESCAPE
#81T11,3DHSCR
DHLPR,R3
#177567 RS

177767

MOV

#177767., (R3)

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
;SET UP POINTER TO LINE PARAMETER
; (RS)=EXPECTED DATA
*IN LINE PARAMETER REGISTER, 177567

042713
011304
020504
001401

000200

BIC
MOV
CMP
BFQ

#200, (R3)
(R3) .R4
RS.R4
1%

052713

000200

012767

104002

011304

004000

166102

006016

T114:

006004
005734

18:

MOV

HLT

BIS

MOV

#4000, 1 COUNT

#2700, (R3)
(R3) ‘R4

*SET UP FOR 4000 ITERATIONS

*SET ALL READ/WRITE BITS

*IN LINE PARAMETER REGISTER
*CLEAR BIT 7
“GET CONTENTS OF LINE PARAMETER
*WAS BIT 7 CLEARED
:LINE PARAMETER REGISTER ERROR

“SET BIT 7

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=7810:02
2669
2470
2471
247
2473

%23’5’

011754
011760
011762

001403
012705

0117266

104002

011770

022704

14:40

PAGE 48

177767

104400

2%:

2476
2477
2478
2479
2480
011772

012767

000340

2485

012006

012767

012074

2487

2488

#177767 R4

:WAS BIT 7 SET

HLT

: (RS)=EXPECTED DATA IN
:LINE PARAMETER REGISTER, 177767
:LINE PARAMETER REGISTER ERROR

SCOPE

2%
#177767 .RS

:VERIFY THAT BIT 10 WAS SET

2483

2486

cMP
BEQ
MOV

;LINE PARAMETER REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
:CLEAR BIT 10
:VERIFY THAT BIT 10 WAS CLEARED
:RESTORE BIT 10

gzg;

2484

SEQ 0058

012000
012014

012767
012777

005712

004000

005630

012022

016703

005630

012026

012705

165776

004000

T115:

005700

MOV

#340,PS

;:DISABLE ALL INTERRUPTS

MOV

#2$ ,ESCAPE

:SET UP TO ESCAPE TO NEXT TEST

MOV
MOV

MOV

177367

#4000, 1 COUNT
#81711,3DHSCR
DHLPR,R3

MOV

#177367.RS

2489
2490
2691
2492
2493
2494
2495
2496
2497
2498

012032

012713

177767

MOV

#177767, (R3)

012036
012042
012044
012046
012050
012052
012056

042713
011304
020504
001401
104002
052713
011304

000400

BIC
MOV
CMP
BEQ
HLT
BIS
MOV

#400, (R3)
(R3) .R&
RS,R4
1%
2
#400, (R3)
(R3) .R4

2500
2501

012064
012066

001403
012705

BEQ
MOV

2s
#177767.RS

HLT

2499

2502

2503

gggg

012060

012072

012074

022704

000400

1%:

177767

CMP

177767

104002

104400

2%:

2506
2507
2508
2509
2510

012076

012767

000340

2515

012112

012767

012200

0121064

012120

012767

012777

2517

012126

016703

2520
2521
2522

012136

012713

012142
012146
012150

042713
011304
020504

2518
2519

2523
2524

:SET UP POINTER TO LINE PARAMETER

: (RS)=EXPECTED DATA

*IN LINE PARAMETER REGISTER, 177367
*SET ALL READ/WRITE BITS
:IN LINE PARAMETER REGISTER
:CLEAR BIT 10
;GET CONTENTS OF LINE PARAMETER
:WAS BIT 10 CLEARED
;LINE PARAMETER REGISTER ERROR
:SET BIT 10

;WAS BIT 10 SET
: (RS)=EXPECTED DATA IN

*LINE PARAMETER REGISTER, 177767

SLINE PARAMETER REGISTER ERROR

JVERIFY THAT BIT 11 WAS SET

2513

2516

:MASTER CLEAR INTERFACE

:LINE PARAMETER REGISTER DATA TEST
_
;SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER .J 1S
:CLEAR BIT 11
SVERIFY THAT BIT 11 WAS CLEARED
:RESTORE BIT 11

Sg}}

2514

SCOPE

#177767 R4

:SET UP FOR 4000 ITERATIONS

012132

012705

165672

004000

005606

004000

005524

176767

005574

T116:

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV

#2$ ESCAPE

:SET UP TO ESCAPE TO NEXT TEST

MOV
MOV

MOV

#4000, 1 COUNT
#81711,aDHSCR
DHLPR,R3

MOV

#176767 RS

177767

MOV

#177767. (R3)

001000

BIC
MOV
CMP

41000 (R3)
(R2) R4
RS, ac

:SET UP FOR 4000 ITERATIONS
:MASTER CLEAR INTERFACE

:SET UP POINTER TO LINE PARAME TER

: (RS)=EXPECTED DATA
*IN LINE PARAMETER REGISTER, 176767
*SET ALL READ/WRITE BITS
<IN LINE PARAHETER REGISTER
‘CLEAR BIT 1

cer CONTENTS OF LINE PARAMETER
WAS BIT 11 CLEARED

CZDHA-C MACY1T 30A(1052)10285AUG-78
CZDHAC.P11
15-MAY-78

2525
2526
2527
2528

012152
012154
012156
012162

2530
2531
2532
2533
gggg

012170
012172

2529

012164

012176
012200

001401
104002
052713
011304

022704

001403
012705

14:40

901000

PAGE 49

1%:

177767

BEQ
MOV

177767

104002
104400

2%:

2536
2537
2538
2539
2540
012202

012767

000340

2545
2546
2547
2548
2549
2550
2551

012216
0122264
012232
012236

012767
012777
016703
012705

012304
004000
005420
175767

012210

012242

012246

012767

012274
012276

012302

012304

T117:

005470
005420

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV
MOV

#2% ,ESCAPE
#81711,aDHSCR
DHLPR,R3
#175767.RS

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
;SET UP POINTER TO LINE PARAMETER
: (RS)=EXPECTED DATA
“IN LINE PARAMETER REGISTER, 175767
*SET ALL READ/WRITE BITS
:IN LINE PARAMETER REGISTER

MOV

#4000, 1 COUNT

002000

BIC

#2000, (R3)

052713

002000

BIS

#2000, (R3)

022704

177767

CMP

011304

012270

165566

005502

042713

012266

012262

004000

#177767. (R3)

2558

: (RS)=EXPECTED DATA IN
:LINE PARAMETER REGISTER, 177767
:LINE PARAMETER REGISTER ERROR

MOV

011304
027504
001401
104002

2560
2561
2562
2563

:WAS BIT 11 SET

2%
#177767 RS

177767

012252
012254
012256
012260

2559

#177767 R4

012713

2553
2554
2555
2556

2557

;LINE PARAMETER REGISTER ERROR
SSET BIT 11

;VERIFY THAT BIT 12 WAS SET

2543

2552

HLT
SCOPE

1%
2
#1000, (R3)
(R3) R4

;LINE PARAMETER REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 15
“CLEAR BIT 12
SVERIFY THAT BIT 12 WAS CLEARED
*RESTORE BIT 12

55525

2544

BEQ
HLT
BIS
MOV

SEQ 0059

001403
012705

177767

104002

104400

2%:

MOV
cMP
BEQ
HLT
MOV

(R3) R4
RS,Ré
1%
2
(R3) R4

*SET UP FOR 4000 ITERATIONS

:CLEAR BIT 12

:GET CONTENTS OF LINE PARAMETER
*WAS BIT 12 CLEARED
:LINE PARAMETER REGISTER ERROR

SSET BIT 12

BEQ
MOV

#177767 R4

28
#177767.RS

;WAS BIT 12 SET

HLT

: (RS)=EXPECTED DATA IN
*LINE PARAMETER REGISTER, 177767
SLINE PARAMETER REGISTER ERROR

SCOPE

2566
2567
2568

:LINE PARAMETER REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
:(LEAR BIT 13

2570
gg;}

*RESTORE BIT 13
SVERIFY THAT BIT 13 WAS SET

2569

JVERIFY THAT BIT 13 WAS CLEARED

2573

012306

012767

000340

2575
2576
2577

012322
012330
012336

012767
012777
016703

012410
004000
005314

2574

2578

2579
2580

012314

012342

012346

012767
012705

012713

004000

173767
177767

165462

005376
005364
005314

T120:

MOV

#350,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV

#2% ESCAPE
#8171, aDHSCR
DHLPR,R3

“SET UP TO ESCAPE TO NFXT TEST
:MASTER CLEAR INTERFACE
:SET UP POINTER TO LINE PARAME TER

MOV

MOV
MOV

#4000, 1 COUNT
#173767.RS

#177767, (R3)

*SET UP FOR 4000 ITERATIONS
: (RS)=EXPECTED DATA

“IN LINE PARAMETER REGISTER, 173767
*SET ALL READ/WRITE

BITS

CZDHA=C MACY1 '.'»0A(10;2)1 23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

2581

2582

012352

042713

2584

012360

020504

012366

052713

004000

2583

012356

2585
2586

012362
012364

2588

012372

2587

011304

001401
104002

011304

012374

022704

177767

2591

012402

012705

177767

012406
0126410

104002
104400

2592
2593
gggg

012400

001403

PAGE 50

004000

2589

2590

14:40

#4000, (R3)

TMMP

RS,R&

BIS

#4000, (R3)

CMP

#177767 R4

;WAS BIT 13 SET

MOV

#177767 .RS

: (RS)=EXPECTED DATA IN

HLT
SCOPE

BEQ
HLT

MOV
BEQ

2%:

:IN LINE PARAMETER REGISTER

BIC

MOV

1%:

SEQ 0060

:CLEAR BIT 13

(R3) R4

“GET CONTENTS OF LINE PARAMETER

1%
2

;LINE PARAMETER REGISTER ERROR

(R3) R4

*WAS BIT 13 CLEARED
:SET BIT 13

:LINE PARAMETER REGISTER, 177767
*LINE PARAMETER REGISTER ERROR

2596

;LINE PARAMETER REGISTER DATA TEST

2600

*RESTORE BIT 14

2597
2598
2599

:SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
*CLEAR BIT 14
SVERIFY THAT BIT 14 WAS CLEARED

523}

:VERIFY THAT BIT 14 WAS SET

2603

012412

012767

000340

2605
2606
2607
2608
2609

012426
012434
012442
012446

012767
012777
016703
012705

012514
004000
005210
167767

2604

2610

012420

012767

004000

165356

005272

T121:

005260
005210

MOV

#340,PS

;:DISABLE ALL INTERRUPTS

#2% . ESCAPE
#81T11,aDHSCR
DHLPR,R3
#167767.RS

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO LINE PARAMETER
: (RS)=EXPECTED DATA
“IN LINE PARAMETER REGISTER, 167767

MOV

#4000, 1 COUNT

MOV
MOV
MOV
MOV

*SET UP FOR 4000 ITERATIONS

2611
2612
2613
2614
2615
2616
2617
2618

012452

012713

177767

MOV

#177767., (R3)

012456
012462
012464
012466
012470
012472
012476

042713
011304
020504
001401
104002
052713
011304

010000

BIC
MOV
CMP
BEQ
HLT
BIS
MOV

#10000, (R3)
(R3) ,Ré
RS, R4
1%
2
#10000, (R3)
(R3) R4

2620
2621

012504
012506

001403
012705

BEQ
MOV

2s
#177767 RS

: (RS)=EXPECTED DATA IN

2623

012512

104002

HLT

*LINE PARAMETER REGISTER ERROR

2619

2622

012500

012514

022704

010000

1%:

177767

CMP

177767

104400

2% :

2626
2627
2628
2629
2630

263,
2635
2636

:LINE PARAMETER REGISTER ERROR
SSET BIT 14

;WAS BIT 14 SET

*LINE PARAMETER REGISTER, 177767

;LINE PARAMETER REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
*CLEAR BIT 15
SVERIFY THAT BIT 15 WAS CLEARED
*RESTORE BIT 15

52%}
2633

SCOPE

#177767 R4

*SET ALL READ/WRITE BITS

“IN LINE PARAMETER REGISTER
*CLEAR BIT 14
:GET CONTENTS OF LINE PARAMETER
*WAS BIT 14 CLEARED

JVERIFY THAT BIT 15 WAS SET
012516

012524
012532
012540

012767

012767
012767
012777

000340

004000
012620
004000

165252

005166
005754
005104

T122:

MOV

MOV
MOV
MOV

#340,PS

#4000, 1 COUNT
#2% ESCAPE
#1717, aDHSCR

:DISABLE ALL INTERRUPTS

“SET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

CZDHA=C MACY11 30A(1052)
23-ALG-78
CZDHAC.P11
15-MAY=-78 1 0:02

2637

14:40

PAGE 51

012546

016703

005104

MOV

#157767.RS

012556

012713

177767

MOV

#177767, (R3)

012562
012566

042713
011304

020000

BIC
MOV

#20000, (R3)
(R3) ,Ré

2645
2646

012572
012574

001401
104002

BEQ
HLT

1%
2

2648

012602

011304

2650
2651
2652
2653

012610
012612

2638

2639
2640
2641
2642
2643

2644

2647

2649

222§§’

012552

012570

012576

012604

012616

012620

012705

157767

020504

CMP

052713

020000

022704

177767

001403
012705

1$:

177767

104002

104400

2%:

DHLPR,R3

ns RS,

BIS

#20000, (R3)

CMP

#177767 R4

MOV
BEQ
MOV

(R3) R4

2$
#177767 RS

HLT

SCOPE

:SET UP POINTER TO LINE PARAMETER

: (RS)=EXPECTED DATA

*IN LINE PARAMETER REGISTER 157767
:SET ALL READ/WRITE BITS
:IN LINE PARAMETER REGISTER
*CLEAR BIT 15
*GET CONTENTS OF LINE PARAMETER

*WAS BIT 15 CLEARED

:LINE PARAMETER REGISTER ERROR

*SET BIT 15

:WAS BIT 15 SET
: (RS)=EXPECTED DATA IN
*LINE PARAMETER REGISTER, 177767
*LINE PARAMETER REGISTER ERROR

2656

;LINE PARAMETER REGISTER DATA TEST

2658
2659
2660

*CLEAR BIT 16
*VERIFY THAT BIT 16 WAS CLEARED
*RESTORE BIT 16

2657

:SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S

JVERIFY THAT BIT 16 WAS SET

2663

012622

012767

000340

2665
2666

012636
012644

012767
012777

012724
004000

012705

137767

2664

2667
|

SEQ 0061

2668

2669
2670
2671

2672

012630

012767

012652

016703

012662

012713

042713

012656

012666

2673
2676
2675
2676
2677
2678

01267°
012674
012676
012700
012702
012706

011304
020504
001401
104002
052713
011304

2680
2681
2682
2683

012714
012716

001403
012705

2679

gggg

2686
2687

2688

2689
2690

2691

012710
012722

012724

022704

104002
104400

004000

005000

165146

005062

T123:

005050
005000

MOV

#340,PS

;:DISABLE ALL INTERRUPTS

MOV
MOV

#2$ ,ESCAPE
#81717,aDHSCR

-ssr UP TO ESCAPE TO NEXT TEST
MASTER CLEAR INTERFACE

MOV

#4000, 1 COUNT

DHLPR,R3

MOV

#137767.R5

177767

MOV

#177767. (R3)

040000

BIC

#40000, (R3)

040000

1$:

177767

MOV
CMP
BEQ
HLT
BIS
MOV

cTMP

BEQ
MOV

177767
28:

(R3) R
RS R4
1%
2
#40000, (R3)
(R3) ,Ré&

#177767 R4
2
#177767 RS

HLT

SCOPE

*SET UP FOR 4000 ITERATIONS

SET UP POINTER TO LINE PARAMETER

: (RS)=EXPECTED DATA

“IN LINE PARAMETER REGISTER, 137767
*SET ALL READ/WRITE BITS
“IN LINE PARAMETER REGISTER

*CLEAR BIT 16

*GET CONTENTS OF LINE PARAMETER
‘WAS BIT 16 CLEARED
:LINE PARAMETER REGISTER ERROR
*SET BIT 16

;WAS BIT 16 SET
: (RS)=EXPECTED DATA IN
*LINE PARAMETER REGISTER, 177767
*LINE PARAMETER REGISTER ERROR

:LINE PARAMETER REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S

*CLEAR BIT17
*VERIFY THAT BIT 17 WAS CLEARED
*RESTORE BIT17
SVERIFY TrAT BIT 17 WAS SET

CZDHA-C MACY11 30A(1052)

CZDHAC.P11

23-AUG-78

15-MAY-78 10:02

14:40

2693

012726

012767

000340

165042

2695

012742

012767

013030

004744

2697

012756

016703

269 012736 012767 004000 004756
269

012750

2698 012762

2699
2700
2701
2702
2703
2704
2705
2706
2707
2708

2709

2710
2711
2712
2713

g;}g

PAGE 52

T124:

MOV

:DISABLE ALL INTERRUPTS

#2$ ESCAPE

*SET UP TO ESCAPE TO NEXT TEST

#4000, 1COUNT

MOV

#B1711,3DHSCR

012777

004000

012705

077767

MOV

004674

#340 PS

MOV

004674

SEQ 0062

MOY

177767

MOV

#177767, (R3)

012772
012776
013000
013002
013004
013006
013012

042713
011304
020504
001401
104002
052713
011304

100000

BIC
MOV
cTMP
BEQ
HLT
BIS
MOV

#100000, (R3)
(R3) R4
RS.R&
13
2
#100000, (R3)
(R3) ,Ré4

013020
013022

001403
012705

BEQ
MOV

2$
#177767 ,RS

013014

013026

013030

022704

177767

CMP

177767

104002

104400

2%:

2716
2717
2718
2719
2720

2725
2726
2727

013046
013054
013062

012767
012777
016703

013134
004000
004600

013072

012713

177777

MOV

#177777.(R3)

013076

042713

000001

BIC

#1,

273%
2735
2736

013104
013106
013110

020504
001401
104003

CMP
BEQ
HLT

RS R4
1%
3

2738

013116

011304

2740
2741
2742

013126
013126

001403
012705

013132

013134

104003

013040

013066

013102

013112

012767

012705

011304

004000

000001

2739 013120 022704

177777

104400

164736

004652

T125:

004640
004570

MOV

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

#177776 RS

BIS

MOV
BEQ
MOV

28:

#2$ ESCAPE
#81711,3DHSCR
DHBCR ,R3

MOV

CMP

177777

:DISABLE ALL INTERRUPTS

#4000, 1 COUNT

MOV
1$:

#340,PS

MOV

MOV
MOV
MOV

177776

052713

2743

: (RS)=EXPECTED DATA IN
*LINE PARAMETER REGISTER, 177767
*LINE PARAMETER REGISTER ERROR

;VERIFY THAT BIT 0 WAS SET
000340

2737

:WAS BIT 17 SET

SCOPE

012767

2733

:LINE PARAMETER REGISTER ERROR
“SET BIT 17

HLT

013032

2728

“IN LINE PARAMETER REGISTER, 77767
*SET ALL READ/WRITE BITS
*IN LINE PARAMETER REGISTER
*CLEAR BIT 17
*GET CONTENTS OF LINE PARAMETER
“WAS BIT 17 CLEARED

8177767 .R4

2723

2729
2730
2731
2732

: (RS)=EXPECTED DATA

;BREAK CONTROL REGISTER DATA TEST
*SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
*CLEAR BIT 0
*VERIFY THAT BIT O WAS CLEARED
*RESTORE BIT 0

5;22}

2726

SET UP POINTER TO LINE PARAMETER

#77767 RS

012713

1$:

*MASTER CLEAR INTERFACE

DHLPR ,R3

012766

100000

*SET UP FOR 4000 ITERATIONS

(R3)

(R%) ,R4

#1,(R3)

(RS) R4

#1777277 R4

2$
#177777 RS

HLT

SCOPE

“SET UP FOR 4000 ITERATIONS

;: (RS)=EXPECTED DATA

:IN BREAK CONTROL REGISTER, 177776
*SET ALL READ/WRITE BITS
*IN BREAK CONTROL REGISTER
;CLEAR BIT 0

;GET CONTENTS OF BREAK CONTROL
*WAS BIT O CLEARED

;BREAK CONTROL REGISTER ERROR
;SET BIT'0

;WAS BIT O SET
: (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
*BREAK CONTROL REGISTER ERROR

2746

:BREAK CONTROL REGISTER DATA TEST

2748

*CLEAR BIT 1

2747

“SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S

CZDHA-C MACY11 30A(1052)
23-AUG=78
CZDHAC.P11
15-MAY=78 10:02

14:40

PAGE 53

2749
2750

;VERIFY THAT BIT 1 WAS CLEARED
*RESTORE BIT 1

%;g}

:VERIFY THAT BIT 1 WAS SET

2753

013136

012767

000340

2755

013152

012767

013240

013166

016703

013176

012713

013202

042713

2764
2765
2766
2767

013210
013212
013214
013216

020504
001401
104003
052713

2769
2770
2771
2772
2773
g;;;

013224
013230
013232

2756

013144

012767

2756 013160 012777
2757

2758

2759

2760

2761
2762

2763

2768

013172

013206

013222

013236
013240

012705

011304

022704
001403
012705

004000

164632

004546

T126:

004534

; (RS)=EXPECTED DATA

177777

MOV

#177777., (R3)

000002

BIC

#2,(R3)

000002

cMP
BEQ
HLT
- BIS

RS,R&
1%
3
#2, (R3)

MOV

1$:

177777
177777

104002
104400

2%:

012767

013344

2800
2801
2802
2803
2804

(R%) R4

(R3)5R4

CMP
BEQ
MOV

#177%77 R4
2$
#177777 .RS

HLT
SCOPE

:SET UP POINTER TO BREAK CONTROL

:IN BREAK CONTROL REGISTER, 177775

*SET ALL READ/WRITE BITS

<IN BREAK CONTROL REGISTER
:CLEAR BIT 1

:GET CONTENTS OF BREAK CONTROL
*WAS BIT 1 CLEARED

;BREAK CONTROL REGISTER ERROR
;SET BIT 1
;WAS BIT 1 SET
: (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
:BREAK CONTROL REGISTZR ERROR

JVERIFY THAT BIT 2 WAS SET

013256

2798
2799

MOV

DHBCR,R3

:BREAK CONTROL REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
*CLEAR BIT 2
*VERIFY THAT BIT 2 WAS CLEARED
*RESTORE BIT 2

2785

279%
2795
2796
2797

:SET UP TO ESCAPE TO NEXT TEST

#177775.RS

000340

2793

:SET UP FOR 4000 ITERATIONS

MOV

012767

2789
2790
2791
2792

#2$ ,ESCAPE

MOV

177775

013242

2788

MOV

:DISABLE ALL INTERRUPTS

#4000, 1 COUNT

:MASTER CLEAR INTERFACE

2783

2786

#340,PS

MOV

S;g}

2787

MOV

#B81711,3DHSCR

004474

004464

2776
2777
2778
2779
2780

2784

SEQ 0063

013250

012767

013264

012777

013276

012705

013272

016703

164526

004000

004442

004000

004360

004370

T127:

004430

MOV

#340,PS

:DISABLE ALL

MOV

#28 ESCAPE

:SET UP TO ESCAPE TO NEXT TEST

MOV

DHBCR ,R3

MOV

MCV

177773

#4000, 1 COUNT

MOV

#177773.RS

: (RS)=EXPECTED DATA

177777

MOV

#177777.(R3)

013306

042713

000004

BIC

#4, (R3)

013314
013316
013320
013322

020504
001401
104003
052713

000004

CMP
BEQ
HLT
BIS

RS R4
1%
3
¥4, (R3)

BEQ
MOV

2s
#177777 RS

o133§8
013330

011304
022704

07333
013336

001403
012705

013342
013344

104003
104400

MOV

1$:

177777
177777

28"

ITERATIONS

:MASTER CLEAR INTERFACE

012713

011304

INTERRUPTS

#8171, 3DHSCR

013302

013312

*SET UP FOR 4000

MOV
CMP

HLT
SCOPE

(RS) R4

(RS) R4
8177777 R4

:SET UP POINTER TO BREAK CONTROL

:IN BREAK CONTROL REGISTER, 177773
:SET ALL READ/WRITE BITS
:IN BREAK CONTROL REGISTER
;CLEAR BIT 2

:GET CONTENTS OF BREAK CONTROL

:WAS BIT 2 CLEARED

:BREAK CONTROL REGISTER ERROR
;SET BIT 2

;WAS BIT 2 SET
: (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
:BREAK CONTROL REGISTER ERROR

CZDHA=C MACY11
30A(1052). 23-AUG-78
CZDHAC.P11
15-mAY-78 10:02

2805
2806
2807
2808
2809

14:40

PAGE 54

10
2311

za1§ 013346 012767 000340 164422 T130:
2814 013356

;BREAK CONTROL REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
*CLEAR BIT 3
:VERIFY THAT BIT 3 WAS CLEARED

*RESTORE BIT 3
*VERIFY THAT BIT 3 WAS SET

MOV

#340 PS

:DISABLE ALL INTERRUPTS

MOV

#2$ ESCAPE

“SET UP TO ESCAPE TO NEXT TEST

004336

MOV

2819 013370 012777 004000 004254

MOV

2815

01%3%2

2817

013376

012767 004000
012767

013450

016703

004264

2820 013406 012713

2821
2&5

013412

042713

2824
2825

013420
013422

020504
001401

2818

2819

2823

013402

013416

012705

011304

2826

013

2828

013432

011304

013440
013442

001403
012705

2827

2829

2830
2831
2832
2833

5&':3"5’

013426

013434

013446

013450

104003

004324

MOV

177767

SEQ 0064

#4000, 1COUNT

“SET UP FOR 4000 ITERATIONS

#B81711,aDHSCR

*MASTER CLEAR INTERFACE

DHBCR,R3

-SET UP POINTER TO BREAK CONTROL

MOV

#177767.RS

177777

MOV

#177777.(R3)

000010

BIC

#10, (R3)

P
BEQ

RS.R%
1%

*WAS BIT 3 CLEARED

BIS

#10, (R3)

“SET BIT 3

cTMP

8177777 R4

052713

000010

022704

177777

MOV

1$:

177777

104003

104400

28:

HLT

MOV

+IN BREAK CONTROL REGISTER, 177767

*SET ALL READ/WRITE BITS

+IN BREAK CONTROL REGISTER
*CLEAR BIT 3

(R3) .R%

*GET CONTENTS OF BREAK CONTROL

(R3J ,R%

BEQ
MOV

2$
#177777.RS

HLT

SCOPE

; (RS)=EXPECTED DATA

sBREAK CONTROL REGISTER ERROR

:WAS BIT 3 SET
: (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
sBREAK CONTROL REGISTER ERROR

2836
2837
2838
2839

;BREAK CONTROL REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
*CLEAR BIT 4
*VERIFY THAT BIT 4 WAS CLEARED

5&}

:VERIFY THAT BIT 4 WAS SET

2840

*RESTORE BIT 4

2843

013452

012767

000340

2845

013466

012767

013554

2844

013460

2846 013474
2847 013502
2848

2849
2850
2851
2852

2853

2854
2855
2856
2857

2858
2859

013506

012767
012777
016703
012705

164316

004000

004232

004000
004160

004150

T131:

0046220

177757

MOV

#340,PS

;:DISABLE ALL INTERRUPTS

MOV

#28 ESCAPE

:SET UP TO ESCAPE TO NEXT TEST

MOV

#4000, 1 COUNT

MOV
MOV

#81711,aDHSCR
DHBCR,R3

MOV

#177757.RS

013512

012713

177777

MOV

#177777, (R3)

013516

042713

000020

BIC

#20, (R3)

013524
013526
013530
013532

020504
001401
104003
052713

000020

CMP
BEQ
HLT
BIS

RS.R4
1%
3
#20, (R3)

013522

013536
013540

011304

011304
022704

177777

MOV

1$:

MOV
(MP

(R35 .R&

(R3) ,R%
g;’????.R4

*SET UP FOR 4000 ITERATIONS

*MASTER
CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

: (RS)=EXPECTED DATA

:IN BREAK CONTROL REGISTER, 177757
*SET ALL READ/WRITE BITS
*IN BREAK CONTROL REGISTER
*CLEAR BIT 4

:GET CONTENTS OF BREAK CONTROL

‘WAS BIT 4 CLEARED

;BREAK CONTROL REGISTER ERROR
*SET BIT 4

:WAS BIT & SET

CZDHA=C MACY11 30A(105g)10285AUG-78
CZDHAC.P11
15-MAY=7

2861
286%
2863

gggg

013546

012705

013552

104003

013554

14:40

PAGE 55

177777

104400

2s:

2866
2867
2868
2869
2870
013556

012767

000340

2875
2876

013572
013600

012767
012777

013660
004000

012705

177737

2878

#177777 RS

HLT

SCOPE

013564

013606

013612

012767

016703

004000

004054

164212

004126

T132:

004114
004044

MOV

#340,PS

;:DISABLE ALL INTERRUPTS

MOV
MOV

#28 ,ESCAPE
#81T11,aDHSCR

:SET UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE

MOV

#4000, 1 COUNT

DHBCR,R3

MOV

#177757.RS

2879
2880
2881
2882

013616

012713

177777

MOV

#177777. (R3)

013622

042713

000040

BIC

#40, (R3)

2884
2885
2886
2887
2888

013630
013632
013634
013636
013642

020504
001401
104003
052713
011304

CMP
BEQ
HLT
BIS
MOV

RS,R4
1%
3
#40, (R3)
(R3) ,R&

2890

013650

001403

BEQ

2883

013626

2889 013644

2891

2892
2893

gggg

013652

013656

013660

011304

MOV

000040

022704

177777

012705

177777

1$:

CMP

MOV

104003

104400

2%:

2896
2897
2898
2899
2900

013662

012767

000340

2905
2906
2907

013676
013704
013712

012767
012777
016703

013764
004000
003750

2908

2911

291;

013670
013716

012767

012705

HLT

SCOPE

;GET CONTENTS OF BREAK CONTROL
*WAS BIT S CLEARED

:BREAK CONTROL REGISTER ERROR
*SET BIT §

;WAS BIT 5 SET

: (RS)=EXPECTED DATA IN

;BREAK CONTROL REGISTER, 177777
:BREAK CONTROL REGISTER ERROR

004000

177677

164106

004022

004010
003740

T133:

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV

#28 ESCAPE
#81T11,3DHSCR
DHBCR,R3

:SET UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAX CONTROL

MOV
MOV

#4000, 1 COUNT
#177677.RS

:SET UP FOR 4000 ITERATIONS

: (RS)=EXPECTED DATA

013722

012713

177777

MOV

#177777.(R3)

013;§S

042713

000100

BIC

#100, (R3)

*CLEAR BIT 6

CMP

RS,R4

013

011304

2915

013736

001401

2916

#177777..R5

:IN BREAK CONTROL REGISTER, 177737
:SET ALL READ/WRITE BITS
:IN BREAK CONTROL REGISTER
:CLEAR BIT S

:IN BREAK CONTROL REGISTER, 177677
:SET ALL READ/WRITE BITS

531

#177777 R4

:SET UP POINTER TO BREAK CONTROL

: (RS)=EXPECTED DATA

JVERIFY THAT BIT 6 WAS SET

2903

2909
2910

(R3) ,R&4

:SET UP FOR 4000 ITERATIONS

;BREAK CONTROL REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
:CLEAR BIT 6
:VERIFY THAT BIT 6 WAS CLEARED
*RESTORE BIT 6

538}

2904

: (RS)=EXPECTED DATA IN
;BREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

:VERIFY THAT BIT 5 WAS SET

2873

2877

MOV

:BREAK CONTROL REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
:CLEAR BIT 5
:VERIFY THAT BIT S WAS CLEARED
:RESTORE BIT §

gg;;

2874

SEQ 0065

013734

013740

020504

104003

MOV

BEQ
HLT

(R3) R4

:IN BREAK CONTROL REGISTER

:GET CONTENTS OF BREAK CONTROL

:WAS BIT 6 CLEARED

:BREAK CONTROL REGISTER ERROR

CZDHA=C MACY11
(1052)
23-AUG-78
CZDHAC.PT
15-MAY-7 10:02

PAGE 56

18:

BIS

#100, (R3)

:SET BIT 6

177777

523

51 7777 R4

:WAS BIT 6 SET

177777

MOV

#177777 RS

: (RS)=EXPECTED DATA IN

HLT

*BREAK CONTROL REGISTER ERROR

000100

013742
013746
013750
013754
013756
013762
013764

2%:

MOV

SCOPE

SEQ 0066
(R3) ‘R4

:BREAK CONTROL REGISTER, 177777

;BREAK CONTROL REGISTER DATA TEST
;gngaLb,§ego/uaxre BITS IN BREAK CONTROL REGISTER TO 1§

*VERIFY THAT 917 7 WAS CLEARED
*RESTORE BIT

*VERIFY THAT BIT 7 WAS SET
013766
013774
014002

000340

004000

014070
004000

014010

014016
014022

012705

014026

012713

014032

003644

164002

003716

001403
012705

T134:

003704
003634

MOV

MOV
MOV

MOV

177577

#340,PS

;:DISABLE ALL INTERRUPTS

#23 ESCAPE
#1717 ,3DHSCR

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

#4000, 1 COUNT

DHBCR,R3

*SET UP FOR 4000 ITERATIONS

SET UP POINTER TO BREAK CONTROL

MOV

#177577.RS

177777

MOV

#177777. (R3)

000200

BIC
MOV
ggg

#200, (R3)
(R3) .R4
fig.na

*IN BREAK CONTROL REGISTER
*CLEAR BIT 7
*GET CONTENTS OF BREAK CONTROL
*WAS BIT 7 CLEARED

;BREAK CONTROL REGISTER ERROR

000200

1$:

177777

HLT

177777

2%:

: (RS)=EXPECTED DATA

*IN BREAK CONTROL REGISTER, 177577
:SET ALL READ/WRITE BITS

BIS
MOV

#200, (R3)
(R3) ‘R4

5177777'R‘

;VAS BIT 7 SET

MOV

#177777 .RS

HLT

: (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
*BREAK CONTROL REGISTER ERROR

8?8

104003
104400

SCOPE

*SET BIT 7

;BREAK CONTROL REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S

~&8N

Sy
— o
O
~N

jelelele)

*CLEAR BIT 10
*VERIFY THAT BIT 10 WAS CLEARED
*RESTORE BIT 10
*VERIFY THAT BIT 10 WAS SET

014122
014126

012767
012767
012767
012777
016703
012705

014132

014136

—_

14:40

000340

004000

014174
004000
003540

163676

003612

003600
003530

T135:

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV

#23 ,ESCAPE
#B1717,aDHSCR
DHBCR,R3

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

MOV

#4000, 1 COUNT

*SET UP FOR 4000 ITERATIONS

177377

MOV

#177377 RS

s (RS)=EXPECTED DATA

012713

177777

MOV

#177777. (R3)

“SET ALL READ/WRITE BITS

042713

000400

BIC

#400, (R3)

*CLEAR BIT 10

:IN BREAK CONTROL REGISTER, 177377
*IN BREAK CONTROL REGISTER

NN FREFSE

—

) e

)

[elelelelelelelelels] o

POl
SN o o X oF aF a7 o He
b o
—_— 2
— ) e e e e
NN
v
He
S

CZDHA=C MACY11 30A(1052)
23-AUG=-78
10:02
CZDHAC.P1
15-MAY-

14:40

;

000400

PAGE 57

1%:

177777

2%:

MOV
MP
BEQ
HLT

BIS

MOV
WP
BEQ
MOV

SEQ 0067
(R3) R4
R5.R4
13

sGET CONTENTS OF BREAK CONTROL
;WAS BIT 10 CLEARED

#4600, (R3)

sBRcAK CONTROL REGISTER ERROR
;SET BIT 10

177777
R4

;WAS BIT 10 SET

(R3) ‘R4

#177777 RS

HLT

SCOPE

; (RS)=EXPECTED DATA IN

sBREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

sBREAK CONTROL REGISTER DATA TEST
:EEEASLEI?E??/UUYE BITS IN BREAK CONTROL REGISTER TO 1S
;VERIFY THAT BIT 11 WAS CLEARED
;RESTORE BIT 11
;VERIFY THAT BIT 11 WAS SET
000340
004000
014300
004000

014232

012767
012767
012767
012777
016703
012705

014236

014242

RSRR L

014176

MOV
MOV
MOV
MOV

#2$ ESCAPE
#B1T11,3DHSCR

176777

MOV

#176777.RS

012713

177777

MOV

#177777,(R3)

042713
011304

001000

BIC

#1000, (R3)

3007

003434

163572
003506
003474
003424

001000

Ti36:

MOV

\Pddddd

014272

012705

014276
014300

104400

177777

MOV
(MP
BEQ
HLT

BIS

MOV
CMP
BEQ

MOV

104003

2%:

#340,PS

#4000, 1COUNT
DHBCR,R3

(R3) R4

RS.,R4
1%

;DISABLE ALL INTERRUPTS
;SET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
sMASTER CLEAR INTERFACE
:SET_UP POINTER TO BREAK CONTROL
: (RS)=EXPECTED DATA
s IN BREAK CONTROL REGISTER, 176777
sSET ALL READ/WRITE BITS
s IN_BREAK CONTROL REGISTER
;CLEAR BIT 11
;GET CONTENTS OF BREAK CONTROL
;WAS BIT 11 CLEARED

#1000, (R3)

;BREAK CONTROL REGISTER ERROR
;SET BIT 11

#177777
R4

;WAS BIT 11 SET

#177777 RS

: (R5)=EXPECTED DATA IN
;BREAK CONTROL REGISTER, 177777

(R3) R4

HLT

sBREAK CONTROL REGISTER ERROR

SCOPE

;BREAK CONTROL REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S

;CLEAR BIT 12
;VERIFY THAT BIT 12 WAS CLEARED
JRESTORE BIT 12
sVERIFY THAT BIT 12 WAS SET
000340
004000
014404
004000

003330

175777

163466
00340
003370
003320

T137:

MOV
MOV
MOV
MOV

#340 PS

MOV

#1757%7
RS

MOV

#4000, 1COUNT
#2% ESCAPE

#81T11,aDHSCR
Dr'8CR,R3

;DISABLE ALL INTERRUPTS
;SET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
JMASTER CLEAR INTERFACE
;SET _UP POINTER TO BREAK CONTROL
: (RS)=EXPECTED DATA

E%DHA-C MACY11 30A(10 52)
23-AUG-78
DHAC PN
15-MAY-78 1 0:02

014342

012713

14:40

PAGE 58

177777

MoV

#177777,(R3)

002000

RIC
MOV

#2000, (R3)
(R3) R4

002000

014376

012705

014402
014404

104003
104400

SEQ 0068

1%:

BEQ
HLT

BIS
MOV

§2.R£

z
#2000, (R3)
(R3) R4

177777

528

177777

MOV

2%
#177777 RS

g%SPE

2%:

#177777 .R4

s IN BREAK CONTROL REGISTER, 175777

sSET _ALL READ/WRITE BITS
s IN_ BREAK CONTROL REGISTER
sCLEAR BIT 12
;GET CONTENTS OF BREAK CONTROL
;WAS BIT 12 CLEARED
;BREAK CONTROL REGISTER ERROR
*SET BIT 12

;WAS BIT 12 SET
; (RS)=EXPECTED DATA IN

;BREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

sBREAK CONTROL REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S

;CLEAR BIT 13
;VERIFY THAT BIT 13 WAS CLEARED
;RESTORE BIT 13
;VERIFY THAT BIT 13 WAS SET
014406
014414
014422
014430
014436
014442

012767
012767
012767
012777
016703
012705

000340
004000
014510
004000
003224
173777

014446

012713

T1140:

MOV

#81T11,aDHSCR

MOV
MOV

104003
104400

sMASTER CLEAR INTERFACE

;SET _UP POINTER TO BREAK CONTROL
; (RS)=EXPECTED DATA
s IN BREAK CONTROL REGISTER, 173777

MOV

#177777,(R3)

004000

BIC
MOV

#4000, (R3)
(R3) ,R4

§§.R4

;CLEAR BIT 13
;GET CONTENTS OF BREAK CONTROL
*WAS BIT 13 CLEARED

;BREAK CONTROL REGISTER ERROR

#177777 R4

;WAS BIT 13 SET
: (R5)=EXPECTED DATA IN
;BREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

1%:

HLT

BIS
MOV

#4000, (R3)
(R3) R4

MOV

2%
#177777 ,RS

g%gpf

g?g

177777

2%:

sSET ALL READ/WRITE BITS
s IN BREAK CONTROL REGISTER

*SET BIT 13

;BREAK CONTROL REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
;CLEAR BIT 14
sVERIFY THAT BIT 14 WAS CLEARED
;RESTORE BIT 14
;VERIFY THAT BIT 14 WAS SET
MOV

MOV

#2'0,PS

#4000, 1COUNT

;'g SABLE

;

L INTERRUPTS

014506
014510

DHBCR,R3

177777

012705

#2$ ,ESCAPE

;DISABLE ALL INTERRUPTS
;SET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST

#173777
RS

ggg

014502

#340,PS

#4000,
1 COUNT

MOV

004000

gERES

MOV

014452
014456

163362

003276
003264
003214

4000 ITERATIONS

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

14:40

PAGE 59

3085 014526 012767 014614 003160

MOV

3087
3088

MOV
MOV

3086

014534

012777

004000

3089
3090
3091

014552

012713

3093
3096
3095
3096
3097
3098

014562
014564
014566
014570
014572
014576

014556

042713

011304
020504
001401
04003
052713
011304

014604
014606

001403
012705

014612
014614

104003
104400

3092

3099

3100
3101
3102
3103
%}8?

014542
014546

014600

016703
012705

022704

#177777.(R3)

010000

BIC

#10000, (R3)

010000

1%:

177777
177777

3115
3116

014632
014640

012767
012777

014720
004000

3136
3137
3138
3139
3140

BEQ
MOV

2$
#177777 RS

<IN BREAK CONTROL REGISTER, 167777
:SET ALL READ/WRITE BITS
+IN BREAK CONTROL REGISTER

*CLEAR BIT 14

<GET CONTENTS OF BREAK CONTROL
*WAS BIT 14 CLEARED
JBREAK CONTROL REGISTER ERROR
*SET BIT 14

#177777 .R4

;WAS BIT 14 SET
; (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

HLT
SCOPE

:VERIFY THAT BIT 15 WAS SET
000340

3130
3131
3132
3133
§;§§

(R3) .Ré
RS,R4
1%
3
#10000, (R3)
(R3) ,Ré

*MASTER CLEAR INTERFACE

;BREAK CONTROL REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
:CLEAR BIT 15
JVERIFY THAT BIT 15 WAS CLEARED
*RESTORE BIT 15
012767

3129

MOV
CMP
BEQ
HLT
BIS
MOV

CMP

2%:

014616

3119
3120
3121
3122
3123
3124
3125
3126
3127
3128

-SET UP POINTER TO BREAK CONTROL
; (RS)=EXPECTED DATA

MOV

3113

2118

DHBCR,R3
2167777 RS

177777

%H%

3117

:SET UP TO ESCAPE TO NEXT TEST

#81711,3DHSCR

3106
3107
3108
3109
3110

3114

#2% ESCAPE

MOV

003120
167777

003110

SEQ 0069

014624

012767

004000

163152

003066

T142:

003054
003004

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV

#2$ ESCAPE
#81711,aDHSCR

:SET UP TO ESCAPE TO NEXT TEST
“MASTER CLEAR INTERFACE

MOV

#157777.RS

: (RS)=EXPECTED DATA

MOV

:SET UP FOR 4000 ITERATIONS

014646

016703

003014

014656

012713

177777

MOV

#177777.(R3)

014662
014666
014670
014672
014674
014676
014702

042713
011304
020504
001401
104003
052713
011304

020000

BIC
MOV
C
BEQ
HLT
BIS
MOV

#20000, (R3)
(R3) R4
RS.R4
1%
3
#20000, (R3)
(R3) ,Ré

014710
014712

001403
012705

BEQ
MOV

#177777 .R4

2$
#177777 RS

:WAS BIT 15 SET

014716
014720

104003
104400

HLT
SCOPE

: (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

014652

014706

012705

022704

MOV

#4006.1COUN7

157777

020000

1%:

177777

CMP

177777

2%:

DHBCR,R3

:SET UP POINTER TO BREAK CONTROL

:IN BREAK CONTROL REGISTER, 157777
*SET ALL READ/WRITE BITS
*IN BREAK CONTROL REGISTER
*CLEAR BIT 15
sGET CONTENTS OF BREAK CONTROL
*WAS BIT 15 CLEARED

;BREAK CONTROL REGISTER ERROR
:SET BIT 15

;BREAK CONTROL REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
*CLEAR BIT 16
*VERIFY TrAT BIT 16 WAS CLEARED

*RESTORE BIT 16

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=78 10:02

14:40

PAGE 60

g}zg

SEQ 0070

;VERIFY THAT BIT 16 WAS SET

3143

014722

012767

3145
3146
3147

014736
014744
014752

012767
012777
016703

014762

012713

177777

MOV

#177777.(R3)

014766
014772
014774
014776
015000
015002
015006

042713
011304
020504
001401
104003
052713
011304

040000

BIC
MOV
CMP
BEQ
HLT
BIS
MOV

#40000, (R3)
(R3) .Ré
RS,R4
18
z
#40000, (R3)
(R3) ,Ré

3144

3148

3149
3150
3151
3152
3153
3154
3155
3156
3157
3158

3159

3160
3161
3162
3165
g;gg

014730
014756

015010

015014
015016
015022
015024

000340

012767

004000

012705

137777

022704

001403
012705

015024
004000
002710

163046

002762

T143:

002750
002700

040000

177777

104003
104400

2%:

000340

3175
3176
3177

015042
015050
015056

012767
012777
016703

015130
004000
002604

015066

015072
015076

3189

3190
3191
3192
3193
g}gg

3196

:SET UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

#137777 RS

#177777 R4

2%
#177777.R5

HLT
SCOPE

:SET UP FOR 4000 ITERATIONS
; (RS)=EXPECTED DATA

;IN BREAK CONTROL REGISTER, 137777
:SET ALL READ/WRITE BITS
:IN BREAK CONTROL REGISTER
:CLEAR BIT 16
:GET CONTENTS OF BREAK CONTROL
:WAS BIT 16 CLEARED
:BREAK CONTROL REGISTER ERROR
:SET BIT 16

;WAS BIT 16 SET
: (RS)=EXPECTED DATA IN
:BREAK CONTROL REGISTER, 177777
*BREAK CONTROL REGISTER ERROR

:VERIFY THAT BIT 17 WAS SET
012767

3184
3185
3186
3187
3188

#28 ,ESCAPE
#81T11,aDHSCR
DHBCR,R3

#4000, 1 COUNT

;BREAK CONTROL REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
:CLEAR BIT 17
:VERIFY THAT BIT 17 WAS CLEARED
*RESTORE BIT 17
015026

3182
3183

MOV
MOV
MOV

CMP

177777

3173

3178

:DISABLE ALL INTERRUPTS

BEQ
MOV

§};}

3179
3180
3181

#340,PS

MOV

3166
3167
2168
3169
3170

31764

MOV

015034

(015062

015100
015102
015104
015106
015112

015114

015120
015122
015126
015130

MOV

#340,PS

:DISABLE-ALL INTERRUPTS

077777

MOV
MOV
MOV

MOV

#28 ,ESCAPE
#81T11,aDHSCR
DHBCR,R3

:SET UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

012713

177777

MOV

#177777.(R3)

042713
011304

100000

BIC
MOV

#100000, (R3)
(R3) .R&4

012767
012705

020504
001401
104003
052713
011304

022704

001403
012705
104003
104400

004000

100000

162742

002656

T144:

002644
002574

1%:

177777

MOV

2%:

877777 .RS

:SET UP FOR 4000 ITERATIONS
: (RS)=EXPECTED DATA

:IN BREAK CONTROL REGISTER, 77777
:SET ALL READ/WRITE BITS
<IN BREAK CONTROL REGISTER

:CLEAR BIT 17
*GET CONTENTS OF BREAK CONTROL

CMP
BEQ
HLT
BIS
MOV

RS,R4
1%
3
#100000, (R3)
(R3) ,Rb4

BEQ
MOV

8177777 R4

2%
#177777.RS

:WAS BIT 17 SET

HLT
SCOPE

; (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
:BREAK CONTROL REGISTER ERROR

(MP

177777

#4000, 1 COUNT

;SILO STATUS REGISTER DATA TEST

*WAS BIT 17 CLEARED

:BREAK CONTROL REGISTER ERROR
:SET BIT 17

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=78 10:02

14:40
\

PAGE 61

SEQ 0071

3197

;SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S

3199
3200

*VERIFY THAT BIT 0 WAS CLEARED
*RESTORE BIT 0

3198

*CLEAR BIT 0

JVERIFY THAT BIT O WAS SET

3203

015132

012767

000340

3205
3206
3207

015146
015154
015162

012767
012777
016703

015244
004000
002502

015172

012713
042713

3206

3208

2209
3210
211
3212

3213
214

3215
3216
3217
3218

3219
3220

3221

3222
3223
3224
3225
gggg

015140
015166

015176

015202
015

015210
015212
015214
015216

012767
012705

011304
042704

020504
001401
104004
052713

015222
0152264

011304
042704

015234
015236

001403
012705

015230
015242
015244

022704

MOV

#340,PS

MOV
MOV
MOV

#28 ESCAPE
#81T11,3DHSCR
DHSSR,R3

100077

MOV

#100077. (R3)

000001

BIC

#1,

CMP
BEQ
HLT
BIS

RS ,R4
1%
A
#1.(R3)

cMP

#100077 ,Ré4

004000

162636

002552

T145:

002540
002470

100076

MOV

MOV
BIC

077700
000001

1$:

077700

MOV
BIC

100077

BEQ
MOV

100077

104004
104400

2%:

3228
3229
3230
3231
3232

015246

012767

000340

3237
3238
3239

015262
015270
015276

012767
012777
016703

015360
004000
002366

3243
3244
3245

015306

3247

3240

3246

2248
3249
3250

3251
3252

“SET UP FOR 4000 ITERATIONS

#CLRBIT,RS

; (RS)=EXPECTED DATA

(R3)

(R%) R4
#77700 R4

(R3) R4
#77700 R4

“SET UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE
SET UP POINTER TO SILO STATUS
*IN SILO STATUS REGISTER, CLRBIT
:SET ALL READ/WRITE BITS
*IN SILO STATUS REGISTER
;CLEAR BIT 0

:GET CONTENTS OF SILO STATUS
*CLEAR UNWANTED BITS
*WAS BIT O CLEARED

:SILO STATUS REGISTER ERROR
SSET BIT'0

:CLEAR UNWANTED BITS

“WAS BIT O SET

2$
#100077 RS

; (RS)=EXPECTED DATA IN
*SILO STATUS REGISTER, 100077
*SILO STATUS REGISTER ERROR

:VERIFY THAT BIT 1 WAS SET

3235

3241
3242

HLT
SCOPE

;DISABLE ALL INTERRUPTS

#4000, 1 COUNT

;SILO STATUS REGISTER DPATA TEST
:SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S
*CLEAR BIT 1
SVERIFY THAT BIT 1 WAS CLEARED
*RESTORE BIT 1

%5;2

3036

MOV

#340,PS

;:DISABLE ALL INTERRUPTS

100075

MOV
MOV
MOV

MOV

#2% ESCAPE
#1717, aDHSCR
DHSSR,R3

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
sSET UP POINTER TO SILO STATUS

012713

100077

MOV

#100077, (R3)

*IN SILO STATUS REGISTER, CLRBIT
“SET ALL READ/WRITE BITS

015312
015316

042713
011304

000002

BIC
MOV

#2, (R3)
(R%) k&

015324

020504

(MP

RS ,R&

015254

015302

015320

015326
015330
015332

015336
015340

012767

012705

042704

001401
104004
052713

011304
042704

004000

162522

002436

T146:

002424
002354

077700

000002

077700

MOV

BIC

1$:

BEQ
HLT
BIS

MOV
Bl

#4000, 1 COUNT

#CLRBIT.RS
:

#77700. R4

L3
4
#2,(R3)

(n® R
#77700 R4

“SET UP FOR 4000 ITERATIONS

: (RS)=EXPECTED DATA

*IN SILO STATUS REGISTER

SCLEAR BIT 1
:GET CONTENTS OF SILO STATUS

*CLEAR UNWANTED 3]TS

‘WAS BIT 1

CLEARED

:SILO STATUS REGISTER FRROR
SSET BITTY

;CLEAR UNWANTED B]TS

CZDHA=C MACY11 30A(10;2)10285AUG-78
CZDHAC.P1
15-MAY-78

3
012705
360

14:40

PAGE 62

100077

SEQ 0072
5100077.R4

;WAS BIT 1 SET

MOV

#100077 ,R5

s (RS)=EXPECTED DATA IN

HLT
SCOPE

;SILO STATUS REGISTER ERROR

(MP
BEQ

100077

104004

104400

2%:

;SILO STATUS REGISTER, 100077

;SILO STATUS REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S

;CLEAR BIT 2
;VERIFY THAT BIT 2 WAS CLEARED

;RESTORE BIT 2

;VERIFY THAT BIT 2 WAS SET

015422

012767
012767
012767
012777
016703
012705

000340
004000
015474
004000
002252
100073

012713

100077

015426
015432
015434
015440
015442
015444
015446
015452
015454
015460
015464
015466

012705

015472
C15474

104004
104400

104004

162406

002322
002310
002240

T147:

#340.PS

;:DISABLE ALL INTERRUPTS

#2$ ESCAPE

“SET UP TO ESCAPE TO NEXT TEST

#CLRBIT.RS

: (RS)=EXPECTED DATA

#100077, (R3)

“SET ALL READ/WRITE BITS
*IN SILO STATUS REGISTER

#4000, 1 COUNT

*SET UP FOR 4000 ITERATIONS

#1711, aDHSCR
DHSSR,R3

000004

#4,

077700

#77700,R4

(R3)

(R%) R4

“MASTER CLEAR INTERFACE
:SET UP POINTER TO SILO STATUS
“IN SILO STATUS REGISTER, CLRBIT

;CLEAR BIT 2

:GET CONTENTS OF SILO STATUS

*CLEAR UNWANTED BITS

7;.R4

000004

4
#4 . (R3)

1%:

*WAS BIT 2 CLEARED

;SILO STATUS REGISTER ERROR
;SET BIT 2

077700

(R3) ,R4
#77700 R4

5100077.R4

“WAS BIT 2 SET

100077

#100077 RS

: (RS)=EXPECTED DATA IN

:SILO STATUS REGISTER ERROR

100077

2%:

HLT
SCOPE

;CLEAR UNWANTED BITS

:SILO STATUS REGISTER, 100077

sSILO STATUS REGISTER DATA TEST

sSET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S
;CLEAR BIT 3
;VERIFY THAT BIT 3 WAS CLEARED

;RESTORE BIT 3

777
703

004000
002136
100067

—

000340

767

2 ¥
2
£

e
B
-

(elelelelele]
O

;VERIFY THAT BIT 3 WAS SET
004000
015610

162272

002206
002174

002124

T150:

#340 PS

;DISABLE ALL

#23% ESCAPE

;SET UP TO ESCAPE TO NEXT TEST

#4000, 1 COUNT
#31T11,aDHSCR

DHSSR,R3

INTERRUPTS

;SET UP FOR 4000 ITERATIONS

;MASTER CLEAR INTERFACE

:SET UP POINTER TO SILO STATUS

#CLRBIT,RS

; (RS)=EXPECTED DATA

100077

#100077, (R3)

;SET ALL READ/WRITE BITS

000010

#10, (R3)

;CLEAR BIT

sIN SILO STATUS REGISTER, CLRBIT

sIN SILO STATUS REGISTER
3

———

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

3309

3310

3311
3312
2313
3314

3315
3316
3317
3318

3319

3320
3321
gggg

015546

015550

015554
015556
015560
015562

011304

042704

020504
001401
104004
052713

077700
100077

015602

012705

100077

015606

015610

MOV

BIC

000010

011304
042704
022704

001403

PAGE 63

077700

015566
015570
015574
015600

14:40

———

1%:

CMP
BEQ
HLT
-BIS

MOV
BIC
CMP

BEQ

104004

104400

2%:

3324,

(R3) ,R4

;GET CONTENTS OF SILO STATUS

RS,R4
1%
4
#10, (R3)

*WAS BIT 3 CLEARED

#77700,R4

(R3) R
#77700 R4
#100077 R4
2$

#100077.,RS

HLT

015612

012767

000340

3333
333
3335
333
3337
3338
3339
330
331

015626
015636
015642
015646

012767
012777
016703
012705

015724
004000
002022
100057

015652

012713

100077

MOV

#100077. (R3)

015656
015662

042713
011304

000020

BIC
MOV

#20, (R3)
(R3) R4

333
334,
3345
336
3347

015670
015672
015674
015676
015702

020504
001401
104004
052713
011304

cMP
BEQ
HLT
BIS
MOV

RS,R4
1%
4
#20, (R3)
(R3J ,R%

335C
3351
3352
3353

015714
015716

BEQ

HLT

3348
3349

gggg

015620

015664

015704
015710

015722

015724

012767

042704

004000

T151:

002060
002010

077700

3364

:SILO STATUS REGISTER ERROR
“SET BIT 3

:CLEAR UNWANTED BITS
‘WAS BIT 3 SET

; (RS)=EXPECTED DATA IN

:SILO STATUS REGISTER, 100077
*SILO STATUS REGISTER ERROR

077700
100077

012705

100077

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV
MOV

#2$ ESCAPE
#81711,aDHSCR
DHSSR,R3
#CLRBIT.RS

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO SILO STATUS
: (RS)=EXPECTED DATA
“IN SILO STATUS REGISTER, CLRBIT
*SET ALL READ/WRITE BITS
*IN SILO STATUS REGISTER
*CLEAR BIT 4
*GET CONTENTS OF SILO STATUS

MOV

BIC

000920

042704
022704

001403

162156

002072

1$:

BIC
CMP
MOV

104004

104400

2%:

3356
3357
3358
3359
3360
g;g;

3363

*CLEAR UNWANTED BITS

:SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S
*CLEAR BIT 4
*VERIFY THAT BIT 4 WAS CLEARED
*RESTORE BIT 4
SVERIFY THAT BIT 4 WAS SET

3331

3342

Zung

;SILO STATUS REGISTER DATA TEST

3325
3326
3357
3328
gggg

3332

SEQ 0073

MOV
SCOPE

SCOPE

#4000, 1 COUNT

#77700 R4

“SET UP FOR 4000 ITERATIONS

*CLEAR UNWANTED BITS
‘WAS BIT 4 CLEARED

;SILO STATUS REGISTER ERROR
“SET BIT 4

#77700 R4
#100077 R4

:CLEAR UNWANTED BITS
‘WAS BIT & SET

#100077 RS

: (RS)=EXPECTED DATA IN
*SILO STATUS REGISTER, 100077
*SILO STATUS REGISTER ERROR

:SILO STATUS REGISTER DATA TEST
*SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S
*CLEAR BIT §
SVERIFY THAT BIT 5 WAS CLEARED
*RESTORE BIT §
SVERIFY THAT BIT 5 WAS SET

015726

015734

012767

000340

004000

162042

001756

T1152:

MOV

#2'0,PS

#4000, 1COUNT

:DISABLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

3365
336
337

3368

14:40

PAGE 64

015742
015750
015756

012767
012777
016703

016040
004000
001706

100037

MOV

#CLRBIT,RS

015762

012705

001744
001674

MOV
MOV
MOV

SEQ 0074

#2$ ESCAPE
#81711,aDHSCR
DHSSR,R3

:SET UP TO ESCAPE TO NEXT TEST
‘MASTER CLEAR INTERFACE
-SET UP POINTER TO SILO STATUS

: (RS)=EXPECTED DATA

3369
3370
3371
3372
3373

015766

012713

100077

MOV

#100077. (R3)

015772
015776

042713
011304

000040

BIC
MOV

#40, (R3)
(R3J ,R&

3375
3376
3377
3378

016004
016006
016010
016012

020504
001401
104004
052713

000040

cMP
BEQ
HLT
BIS

RS,R4
1%
4
#40, (R3)

3380
3381

016020
016026

042704
022704

077700
100077

BIC
cMP
BEQ
MOV

#77700,R4
#100077 ,R4

2$
#100077,RS

;CLEAR UNWANTED BITS
‘WAS BIT S SET

HLT

: (RS)=EXPECTED DATA IN
:SILO STATUS REGISTER, 100077
*SILO STATUS REGISTER ERROR

3374

3379

3382
3383
3384
3385

%3339

016000

042704

016016

011304

016030
016032

001403
012705

016036

016040

077700

BIC

1$:

100077

104004

104400

2%:

3388
3389
3390
3391
3392

MOV

SCOPE

#77700 R4

012767

000340

3397
3398
3399
3400
2401
3402

016056
016064
016072
016076

012767
012777
016703
012705

016154
004000
001572
000077

016102

012713

100077

MOV

#2$ ,ESCAPE
#81711,aDHSCR
DHSSR,R3
#CLRBIT.RS
§
#100077, (R3)

3404

016106

042713

100000

BIC

#100000, (R3)

%06

0161164

042704

077700

BIC

#77700,R4

3407
34,08
3409
3410
3411

2412
3413

214
3415
316
217
2418

;SILO STATUS REGISTER ERROR
SSET BIT 5

:VERIFY THAT BIT 17 WAS SET
016042

3405

“WAS BIT 5 CLEARED

(R3) ,R&4

3395

24,03

*CLEAR UNWANTED BITS

:SILO STATUS REGISTER DATA TEST
*SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 15
*CLEAR BIT 17
*VERIFY THAT BIT 17 WAS CLEARED
*RESTORE BIT 17

%3:3.

339

*IN SILO STATUS REGISTER, CLRBIT
*SET ALL READ/WRITE BITS
“IN SILO STATUS REGISTER
:CLEAR BIT S
“GET CONTENTS OF SILO STATUS

016050

012767

016112

011304

016120
016122
016124
016126
016132

020504
001401
104004
052713
011304

016144
016146

001403
012705

016136
016140

016152
016154

042704
022704

104004
104400

004000

100000

161726

001642

T153:

001630
001560

MOV

MOV
MOV
MOV
MOV

MOV

1$:

077700
100077

2%:

(R3) R4

CMP
BEQ
HLT
IS
MOV

RS,R&
1%
4
#100000, (R3)
(R3) ,R4

BEQ
MOV

28
#100077.RS

BIC
CMP

100077

#340,PS

#4000, I COUNT

HLT
SCOPE

:DISABLE ALL INTERRUPTS

“SET UP FOR 4000 ITERATIONS

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO SILO STATUS
; (RS)=EXPECTED DATA
:IN SILO STATUS REGISTER, CLRBIT
*SET ALL READ/WR.TE BITS

*IN SILO STATUS REGISTER
*CLEAR BIT 17

*GET CONTENTS OF SILO STATUS

*CLEAR UNWANTED BITS
*WAS BIT 17 CLEARED

;SILO STATUS REGISTER ERROR
*SET BIT 17

#77700 R4
#100077 ,Ré

:CLEAR UNWANTED BITS
“WAS BIT 17 SET

: (RS)=EXPECTED DATA IN
*SILO STATUS REGISTER, 100077
*SILO STATUS REGISTER ERROR

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P1T
15-MAY-78 10:02

14:40

PAGE 65

3419

3420
3421
3422
3423
3424
3425
3426
332%%
3429

3430
3431

sSYSTEM CONTROL REGISTER MOVE-BYTE TEST (PART 1)
s ISSUE A MASTER CLEAR
MVE A BYTE TO SET INTERRUPT ENABLE BITS
IN UPPER BYTE OF SYSTEM CONTROL
.VERIFY
BITS SET CORRECTLY
sMOVE A BYTE TO SET INTERRUPT ENABLE BIT
:
IN LOWER BYTE OF SYSTEM CONTROL
;VERIFY UPPER BYTE WAS NOT AFFECTED
016156

016162
016170

012706

012767
012767

021360

000340
016300

161606
001516

004000

001440

T154:

3432 016176 012767 004000 001514
3433

016204

052777

3435
3436

016216
016220

005203
112713

3438
3439
3440
3441
3442
3443
3444

016224
016232
016234
016240
016244
016246
016250

3434

3437

3445

016212

016703

022777
001406
012705
017704
104001
000414
112777

001434

001420

030000
001406
000100

001374

3450
3322}

016272

016276
016300

017704

104001
104400

2%:

001354

99%:

016302
016306
016314

012706
012767
012767

021360
000340
016424

3466
3467

016330
016336

052777
016703

004000
001310

001314

000017

001300

000017

001272

161462
001372

3465 016322 012767 004000 001370

3471
3472
3473

3474

#8IT17, DHSCR

:ISSUE MASTER CLEAR

INC
MOvVB

R3
#60,

UPPER BYTE
SET INTERRUPT ENABLE BITS

CMP
BEQ
MOV
MoV
HLT
BR
MOVB

#BIT13+81T12,aDHSCR
:VERIFY BITS SET CORRECTLY
2%
:BRANCH IF 0K
#BIT13+8IT12,R5;(R5)=REGISTER EXPECTED DATA
aDHSCR, R4
: (R&)=REGISTER ACTUAL DATA
1
:BITS DID NOT SET CORRECTLY
99%
:BRANCH TO SCOPE
#BI1T06, ADHSCR SET INTERRUPT ENABLE BIT

0340

04006

DHSCR,

PS
ESCAPE

sSET UP STACK

cLOCK OUT INTERRUPTS
SET UP TO ESCAPE TO NEXT TEST

ICOUNT ;SET UP FOR 4000 ITERATIONS

(R3)

(RS)'SYSTEH CONTROL REGISTER ADDRESS
:IN UPPER BYTE OF SYSTEM CONTROL

CMP
BEQ
MOV

LOWER BYTE OF SYSTEM CONTROL
dBIT13+BIT12+BIT66NWHSCR
;VERIFY BITS SET CORRECTLY
99%
0K
#BIT13*BIT12081766
RS H IF
: (R5)=REGISTER
EXPECTED DATA

HLT
SCOPE

aDHSCR, R4

: (R4)=REGISTER ACTUAL DATA

:UPPER BYTE WAS AFFECTED?
:CHECK FOR ITERATIONS,LOOP

;SYSTEM CONTROL REGISTER MOVE-BYTE TEST (PART 2)
; 1SSUE MASTER CLEAR
KJVE A BYTE TO SET LINE SELECT BITS
IN LOWER BYTE OF SYSTEM CONTROL
.VERIFY BITS SET CORRECTLY
sJMOVE A BYTE TO SET THE MAINTENANCE BIT
:
IN UPPER BYTE OF SYSTEM CONTROL
;VERIFY LOWER BYTE WAS NOT AFFECTED

3462
3463
3464

3470

BIS

MoV

3453
3454
3455
3456
3457
3458
3459
w

3468
3469

#STACK, SP

MOV

000060

030000

MOV
MOV
MOV

MOV

3446 016256 022777 030100 001366
3447 016264 001405
3448 016266 012705 030100
3449

SEQ 0075

016342
016344

016352
016360
016362

016366

005203
112777
022777
001406
012705

017704

000017
001260

T155:

MoV
MOV
MOV

#STACK, SP
#3 0.,
PS
ESCAPE

;SET UP STACK
sLOCK OUT INTERRUPTS
;SET UP TO ESCAPE TO NEXT TEST

#81T11, BDHSCR
DH3CR, R3

:ISSUE MASTER CLEAR
(RS)‘SYSTEH CONTROL REGISTER ADDRESS

MOV

04006

ICOUNT :SET UP FOR 4000 ITERATIONS

INC
MOVB

R3
#7,

aDHSCR

BIS
MOV

(MP
BEQ
MOV

MOV

#17,
2%
k7

@DHSCR

RS
aDHSCR, Ré&

UPPER BYTE
SET LINE SELECT BITS

:IN LOWER BYTE OF SYSTEM CONTROL
:VERIFY BITS SET CORRECTLY
:BRANCH IF 0K
; (RS)=REGISTER EXPECTED DATA

: (R4O=REGISTER ACTUAL DATA

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.PN
15-MAY-78 10:02

3475
3476
gz%

016372
016374
016376

104001
000413
112713

3479
3480
3481
3482
3483
3484
3485
3486

016402
016410
016412
016416
016422
016424

022777
001405
012705
017704
104001
104400

14:40

PAGE 66

2%:

HLT
BR
mMovB

1
99%
we,

99%:

cMP
BEQ
MOV
MOV
HLT
SCOPE

#1017,
Q@DHSCR
998
#1017,
RS
@DHSCR, R4
1

000002
001017

001242

001017
001230

3487
3488
3489
3490

3495
3496
3497
3498
3499
3500
3501
3502
3503

3505
gggg

3514
3515
3516
3517
3518
3519
3520
3521
3522
3523

524
3525
3526
3527
gggg

3530

:SET MAINTENANCE BIT
IN UPPER BYTE OF SYSTEM CONTROL
VERIFV BITS SET CORRECTLY
BRANCH IF oK
: (R5)=REG ISTER EXPECTED DATA
: (R&)=REGISTER ACTUAL DATA

:LOWER BY TE WAS AFFECTED?
sCHECK FCR ITERATIONS,LOOP

sRESTART TEST
016426
016430

016432
016436
016442
016446
016454
016460
016462
016464

016466
016470
016472
016474

104401
020325
005067
005067
005267
016767
013701
001405

004711
000240
000240
000240
000167

EOP:

001312
001242
001240
001234
000042

161114

LOGICAL:

TYPE
MEPASS
CLR
CLR
INC
MOV
MOV
BEQ
RESET

NOP
NOP
NOP
RESTRT: JMP

162502

3508
gg?g
3511
3512
3513

(R3)

;BITS DID NOT SET CORRECTLY
:BRANCH T 0 SCOPE

;END OF PASS
;TYPE NAME OF TEST
;UPDATE PASS COUNT
sCHECK FOR EXIT TO ACT-11

%g}

3493
3494

SEQ 0076

;TYPE NAME OF

LAST
ERRFLG
PASCNT
PASCNT
L IGHTS
a6 ,R1
RESTRT
JSR

:CLEAR LAST ERROR PC

:CLEAR ERROR FLAG

;UPDATE PASS COUNT
:DISPLAY PASS COUNT
sCHECK FOR ACT-11 OR DDP
sIF NOT, CONTINUE TESTING

PC,(R1)

BEGIN

sCHECK FOR LOOP ON CURRENT TEST
sCHECK FOR ITERATION SUPPRESSION
016500
016506
016510

032767
001030
032767

016516
016520
016526
016530
016534
016542
016544
016550
016554
016560

001021
032767
001
005267
026767
1007
005067
005067
011667
000002

016566
016570
016574
016576

000002
005767
001745
000762

016562

016716

002000

161062

SCOPER: BIT
BNE
1$%:
BIT
BNE
BIT
BNE
INC
CMP

#SW10, SWR
4%
#SW14,SWR
3%
#SW11,SWR
2%
LPCNT
LPCNT , ICOUNT

040000

161052

004000

161042

001166
001162

001156

001152
001130
001132

2%:

LPCNT
ERRFLG
(SP) ,RETRN

001124

3%:

001110

BNE
CLR
CLR
MOV
RTI

MOV

RTI
TST
BEQ
BR

TEST

RETRN, (SP)

ERRFLG
1%
2%

sCHECK FOR FREEZE ON CURRENT DATA

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=78 10:02

3531
3532
3533

353,

gggg

016600
016606

016610
016614

032767
001402

016716
000002

001000

14:40

160762

001102

SCOPIR: BIT
BEQ
18:

gg_;’g
016616

3541
3542

01% 021667 001116
01
001404

3544
3545

016640
016644

3543

3546
3547
3548

016624

016646
016650
016654

011605
162705
011504

3555
3556
3557

016702
016706
016710

3559
3560

3561

001051

011667

016656
016660
016662

3558

032767

016634

3549
3550
3551

3552
3553
3554

016666
016672
016676

005067
104406

006304
042704

062704
012467
011467

005767
001403
005767

016714

001007

016722

012767

016740

001402

016716
016720

104402
017012

3562
3563
3564

016730
016732
016734

3566
3567
3568
3569

016742
016744
016746
016750

104402
000000
104407
005767

016756

010046

016764
016766
016770
016774
017002

000000
012600
005267
032767
001402

017010
017012

000002
000001

3565

3570
3571

3572

3573
3574
3575
3576
3577

3578

3579
3580

3581

3582

3583

MOV
RTI

SEQ 0077

#SW09, SWR
1%

FREEZ1, (SP)

:ERROR HANDLER

3539

3540

PAGE 67

016754

016760

017004

017014

017016

104401
000000
005767

100005

016600

020000

ERRORS: BIT

#SW13,SWR

MP
BEQ

(SP) ,LAST
18

BNE

001110

MOV

001040

1%:

000002
177001

020436
000034
000042
000030

000001

CLR
SAVOSP

MOV
SUB
MOV

TYPMSG: OCTASC
ERTABO

006

002

TYPDAT

#1,ERRFLG

BEQ

RESREG

8PL

EXITER

MOV

2(SP) ,RO

160614

000704

#ERRTAB
R4
(R4)+,ERRMSG
(R&) ,DATABP

MOV

OCTASC
DATABP: 0
RESREG: RESOS
HALTS:
TST

PUSHRO

160566

(RS) R4

ERRFLG
TYPMSG
DATABP

000004

000714
002000

(SP) ,RS
#2 RS

TST
BEQ
ST

TYPE
ERRMSG: 0
TYPDAT: TST

000002

(SP) ,LAST

ERRFLG

R
R4
#177901
R4

BNE

000754

HALTS

ASL
ASL
BIC

ADD
MOV
MOV

000776

016716
017742

160744

HALT
POPRO
EXITER: INC
BIT
BEQ

MOV

1%:
RT]
ERTABO:
1

.BYTE

“avP(

DATABP

SWR

ERRCNT
#SW10, SWR
1%

ESCAPE
, (SP)

6.2

3584,

:TRAP DISPATCH SERVICE

3586

;TO SELECTED SUBROUTINE

3585

*ARGUMENT OF TRAP IS EXTRACTED

*AND USED AS OFFSET TO OBTAIN POINTER

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

3587
3588

017020

011646

;

017032
017034
017040
017044
017050

006316
042716
062716
017616
000136

177001
020356
000000

14:40

TRPSRV: MOV

339 017056 015616 990006

017605
062716
105777

017072
017074
017076
017102

001001
000002
112577
000767

1$:

000546

2%:

017667
062716

000000
000002

012704
012703
105777
100375
117714
142714
122427
001413
117777
105777
100375

020400

017200
017202
017204

020231
000745
000002

(SP)

*MULTIPLY TRAP ARG BY 2

#TRPTAB. (SP)
a(SP), (SP)
a(SP)+

*POINTER TO SUBROUTINE ADDRESS
*SUBROUTINE ADDRESS
*GO TO SUBROUTINE

BIC

#177001, (SP)

ASL

TYPER:

MOV

a(SP) RS

ADD

#2,(SP)

BPL
TSTB
BNE

1$
(RS)
28

TSTB

RTI

MOVB

B8R

QTPCSR

(RS)+,aTPDBR

104401

000006

INSTRG: MOV
ADD
INSTR1: TYPE

MSG:

000504

1$:

000500
000200
000015

000462
000456

0
MOV

MOV

TSTB

8PL

MOVB

BICB
CMPB
000464

BEQ

MOVB
28:
TSTB
BPL
DEC
BNE
INSTRE: TYPE
MOM

B8R

INSTR2: RTI

a(SP) ,MSG
#2,(SP)
# INBUF ,R4

#7.R3

@TKCSR

QTKDBR, (R4)

#200, (R4)
(R4)+,415

INSTRS

@TKDBR,aTPDBR
QTPCSR
2$
R3
1%

INSTR1
-

N
8

01160
01256
01256
01256
11256
11256
01051
500

W
wnonn s

:CONVERT ASCII STRING TO OCTAL

3639
3640
n

:GET PC OF RETURN

#2,(5P)
a($P), (sP)

ADD
MOV
JMP

000000
000002
000560

017106
017112
017116
017120
017122
017126
017132
017136
017140
017144
017150
017154
017156
017164
017170

017206
017210
017214
017220
017226
017230

3637

(SP) ,=(SP)

SuB
MOV

;ASCII STRING INPUT ROUTINE

3630
3631
3632
3633
3634
3635

017052
017056
017062

VIO NININI NNV

3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625

TRPOK:

SEQ 0078

STELETYPE OUTPUT ROUTINE

3501
3592
3593
59,
3595
3506
3597
3598
3599
3600
3601

PAGE 68

PARAMS: MOV

MOV

(RS5)+,LOLIM

MOV

(RS)+_HILIM

MOVB
MOVB
MOV

(R5)+.LOBITS
(R5)+.ADRCNT
R, (SP)

MOV

PARAM1:

(SP) RS

CLR

(R5) +.DEVADR

+=PC OF TRAP
*GET TRP

*CLEAR UNWANTED BITS

rczom-c
MACY11 15-MaY-78
gomom 10:02
23-AUG-78 14:40 PAGE 69
CZDHAC.P11
3

3647

3648

3649

017240

012704

017250

0014

017256

002415

017264

003012

017272

152405

0172644

017252

017260

020400

122714

000015

121427

000060

121427

000067

142714

000060

3650

017

365
3653

017%:6 122714 000015
017
001406

3651

3654

017302

006305
006305

3658

104404

3657

017310
017312

2659 017314

000760

000750

33223

017336

3665
3666
3667

017324
017330
017332

101373

020567
103770
136705

001365

017340
017344

016704
010524

3676

017356

001372

3685

017346
017352
017360
017362
017364
017366
017370

062705
105367

017372
017374

104401
020235

3691
3692

017412
017416

112167
112167

3693
2694
3695

369
3697
3698

PARERR

(R4) 467

#60, (R4)

(R&S+.RS

CMPB #15, (R4)
BEQ
LIMITS
ASL

INSTER

RS
RS

PARAM1

JTEST TO SEE IF NUMBER IS WITHIN LIMITS

LIMITS: CMP

RS,HILIM

P
BLO
BITB

RS,LOLIM
PARERR
LOBITS,RS

BHI

000032
000032

017376
017402
017406

000022
000002
000013

000002
000000
000000
000000
000000
017371

3686
3687

3688
3689
3690

BGT

BNE

PARERR

sSTORE NUMBER AT SPECIFIED ADDRESS

3672
3673
3677
3678
3679
3680
3681
36836823

(R4) 460

PARERR

BISB

332;(1)

3674
3675

#15, (R&)

BLT

BICB

PARERR:

366532 017316 020567 000042
017322

PARERR

ASL
ASL

3661

3664

BEQ

CMPB

006305

3655 017
3656 017

# INBUF R4

CMPB

SEQ 0079

MOV

1%:

017422
017426

013167
016704

000120
000114

017436
017442

012700
010403

017444

042703

ADD
DECB

BNE

DEVADR
, R4
RS, (R4)+

#2.R5
ADRCNT

;CONVERT OCTAL NUMBER TO ASCII AND OUTPUT TO TELEPRINTER

000000
000002
000130

116705

MOV
MOV

RT]
LoLiM:
0
HILIM:
0
DEVADR: 0
LOBITS: 0
ADRCNT=LOB]ITS+1

017601
062716
012167

017432

1$:

000126
000123
000106

020412
177770

OCTASN: TYPE
MCRLF

MOV
ADD
MOV

a(SP) ,R1
#2,(SP)
(R1)+,WRDCNT

2%:

MOV
MOV

a(R1)+,BINWRD
BINWRD
. R4

MOV
MOV

#TEMP,
RO
R4 .R3

1$:

MOVB
MOVB

MOVB

BIC

(Ri)+.CHRCNT
(R1)+.SPACNT

CHRCNT.RS

#177770.R3

| CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P1
15-MAY-78 10:02

3699
700
701

703

3705
3707
3708
710

3723
3724

017450

017454
017456
017460
017462
017464
017466
017470
017474
017476
017502
017504

062703

110320
006204
04
005305
001365
012703
114023
105367
001374

PAGE 70

SEQ 0080

000260
ASR

ASR
ASR

020424

4$:

000042

105767

000035

2723

000240
000023

R4
R&

DEC
BNE
MOV

RS
33
#MDATA ,R3

TSTB

SPACNT

MOvB
DECB
BNE

=(R0),(R3)+
CHRCNT
4%

5%:

MOVB
DECB

6$
#240, (R3)+
g:ACNT

6%:

CLRB

(R3)

DEC

WRDCNT
1%

WRDCNT: O
CHRCNT: 0
SPACNT=CHRCNT+1
BINWRD: 0

017546

sSAVE PC OF TEST THAT FAILED AND RO-RS
3728

017550

016667

000164

SVO5P:

MOV

4(SP) ,SAVPC

:SAVE RO-RS
3732
%;gz

017556
017562

010567
010467

3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749

017606

000002

017610
017614
017620
017624
017630
017634
017640

016700
016701
016702
016703
016704
016705

3754

017652

000154
000146
000140
000132
000124
000116

Sv05:

MoV

RS, SAVRS

MOV
MoV
MOV
MOV

R3,SAVR3
R2,SAVR?
R1,SAVR1
RO, SAVRO

MOV

R4, SAVR4

;RESTORE RO-RS5

ISRVRKS

14:40

RSO5:

MoV
MOV
MOV
MOV
MOV
z?y

SAVRO,RO
SAVR1,R1
SAVRZ ,R2
SAVR3,R3
SAVR4 R4
SAVRS RS

s INDIRECT POINTERS
TKCSR:
TKDBR:
TPCSR:
TPDBR:
DHSCR:

177560
177562

177564
177566
O

(105
)

15-MAY-

23-AUG-78

14:40 PAGE 71

000000
000000

DHNRC:
DHLPR:

000000
000000
000000
000000
000000
000000

DHBC:
DHBAR:
DHBCR:
DHSSR:
DHSLR:
DHRVEC:

000000
000000

DHTVEC:
DHTLVL:

000000

DHBA:

000000

017750

017752

DHRLVL :

000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

ERRFLG:
PASCNT:
ERRCNT:
RETRN:
ESCAPE:
FREEZ1:
ICOUNT:
LPCNT:
SAVRO:
SAVR1:
SAVR2:
SAVR3:
SAVRS:
SAVRS:
SAVSP:
SAVPC:
INIFLG:
STFLG:
LAST:

010046
010146
010246
010346
010446
010546
016746
010667
012767

PFAIL:

000000

SEQ 0081

(=lelelelelelelelelsleles)

CZDHA-C MCYH

CZDHAC.PI

;PROGRAM VARIABLES
;ERROR FLAG
sPASS COUNT
sERROR COUNT
:SCOPE RETURN ADDRESS FOR TEST LOOPING
;ADDRESS FOR ERROR ESCAPE
sDATA LOOPING RETURN ADDRESS
s ITERATION COUNT FOR TEST IN PROGRESS
sNUMBER OF ITERATICNS THIS TEST
;RO SAVE AREA
;R1 SAVE AREA
;R2 SAVE AREA

;R3 SAVE ARE

;R4 SAVE AREA

:R5 SAVE AREA

;STACK POINTER SAVE AREA
sCALLING ROUTINE SAVE AREA
;PROGRAM INITIALIZATION FLAG

;PROGRAM START FLAG

:LAST ERROR PC
;ENTER HERE ON POWER FAILURE
RO,=(SP)
R1,-(SP)
R2.=(SP)

;SAVE RO-R5 ON PROCESSOR STACK

R3,-(SP)
R4 ,=-(SP)

160032
177742
020010

R5.,=(SP)
264 ,-(SP)
SP,SAVSP

160020

#RESTART .24

000777

:SAVE STACK POINTER
:SET_UP FOR POWER UP TRAP
sHALT ON POWER DOWN NORMAL

sPROCESSOR WILL TRAP HERE WHEN POWER IS RESTORED
016706
012605
012604
012603
012602
012601

177724

RESTAR:

SAVSP,SP
(SP)+,RS
(SP)
+ R4
(SP)+ ,R3
(2P)+,R2
+ ,R1
(SP)

sRESTORE STACK POINTER

;RESTORE RO-R5

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78
10:02

3811
381§
3813
38164
3815

020026
0%88%2
0
020044
020050

3818
3819
3820
3821
3822
3823
3824
3825

020062
020064
020066
020070
020072
020076
020102
020106
020110
020114
020116

104402
020106
104401
020240
005067
005067
000177
000001
000006
017712
005015
020061

3832
33

020153

3836
3837

gglb
17

3827
3828
3829

3842
3843
3844
3845

3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
gggg

020054
020060

012600
012767
012767
0127
005067

005267
001375

PAGE 72

MoV
MoV
MOV
MOV
CLR

157766
157732

000332

INC
BNE

SEQ 0082

(SP)+,R0
#PFAIL ,24
#340,PS
#STACK,
SP
TEMP

;SET UP FOR POWER FAILURE

TEMP
.~

042012

030510

OCTASC
PF TAB
TYPE
MPFAIL
CLR
CLR
JMP
PFTAB:
1
6,2
RETRN
MTITLE: .ASCIZ

015

053012

000
041505

MVECTO:

.ASCIZ

<15><12>/VECTOR ADDRESS=-/

020175

015

041412

047117

MREGAD:

.ASCIZ

<15><12>/CONTROL REGISTER ADDRESS-/

020231
020235
020240
020246
020254
020262
020270

040
015
020040
020122
051125
047522
051040

037440
000012
047520
0405
026105
051107
051505

000

MQM:
MCRLF:
MPFAIL:

CASCIZ
.ASCIZ
.ASCIZ

2/
<15><12>
/ POWER FAILURE, PROGRAM RESTART AT TEST IN PROGRESS/

MEPASS:

.ASCIZ

<15><12>/(ZDHA=C/

MR:
MTSTPC:

LASCIZ
.ASCIZ

<15><12>/R/
<15><12>/TEST PC=/

020276
020
020312
020
020325
0203
020337
020343
020350

052122
042524
020116
042522
5
040510
020124

%ggg

3861
3862
3863
3864
3865
3866

017752
000340
021360
000336

14:40

177606
177646
177604
000002

040440
052123
051120
051523
041412
041455
051012
052012
041520

042527
046111
050040
046501
040524
020124
044440
043517
000
042132
000
000
051505
000055

ERRFLG
LAST
aRETRN

<15><12><12>/DH11 STATIC LOGIC TEST /<15><12>

;TABLE OF FOINTERS FOR TRAP DECODING

020356
020360
020362
020364
020366
020370

016500
017052
017372
017104
017176
017206

TRPTAB: SCOPER
TYPER
OCTASN
INSTRG
INSTRE
PARAMS

CZDHA=-C MACY1 30A(1052)1028§AUG-78
CZDHAC.P11
15-MAY-78

3867
3868
gggg

020372
020374
020376

14:40

PAGE 73

017550
017610
016600

SVO5P
RSO5
SCOP1R

%g;}

3873
3874
3875
3876
3877
%g;g

;BUFFERS FOR INPUT=QUTPUT

020400
020412
020424

000000
020412
000000
020424
000000
020436

INBUF:
.=.+10
TEMP:
.=.+10
MDATA:
.=.+10

%gg?
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895

3897
3898
3900
3901
3902
3903
3905
3907
3908

3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922

SEQ 0083

0
O
0

s TABLE OF POINTERS TO ERROR MESSAGES AND DATA
020436
020436
020440
020442
020444
020446
020450
020452
020454
020456
020460
020462
020464
020466
020474
020502
020510
020516
020524
020530
020536
544
020552
020560

020565
020572

020617
020624
020632
020640
020654

020676
020704
020706
020714

020466
021134
020530
021142
020617
021142
020706
021142
020774
021142
021060
021142
042522
051105
047040
051505
005015
051505
054523
041440
046117
051511
051105

015
020040
041505
116
040520
042524
044507
0426440
005015
0
0
029103
042101
000123
051102
047503

ERRTAB:

044507
040
052117
047520
042101
000123
0521
047117
051040
042524
047522

052123
042111
051040
042116
051104

EMO:

EM1:

042412
020040
020040

046505
051124
043505
020122
122
050130
051040
020040

047111
040522
122
052123
051122
054105
020040
020040
051104

020105
042515
042522
051105
051117
020120
042522
020040
051505

EM2:

040505
052116

020113
047522

EM3:

EMO
DTO
EM1
DT1
EM2
DT
EM3
DT1
EM4
DT1
EMS
DT1
.ASCII

/REGISTER DID NCT RESPOND/

LASCIZ

<15><12>/ADDRESS/

LASCI1

/SYSTEM CONTROL REGISTER ERROR/

LASCIZ

<15><12>/EXP

LASCII

/LINE PARAMETER REGISTER ERROR/

LASCIZ

<15><12>/EXP

LASCII

/ZPEAK CONTROL REGISTER ERROR/

REC

ADDRESS/

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHA P11
15-MAY-78
1 :0

14 :40

PAGE 74

044507

020114

042440
020120
042522
020040
051505
051440

020123
052123
051122

JASCIZ

REER KRS

and s
ol
b

wN—Jd

021102

051104

000

051105
051101
051117
020120
042522
020040
051505

<15><12>/EXP

REC

ADDRESS/

EM4 :

020120
042522
020040
051505

wd ol

SEQ 0084

EMS:

.EVEN
DTO
BYTE

002

DT1:
BYTE

002

BYTE

000

BYTE

LASCII

/SILO STATUS REGISTER ERROR/

JASCIZ

<15><12>/EXP

LASCII

/MASTER CLEAR ERROR/

JASCIZ

1553125 /EXP

1
6,0

SAVRS
3
6,2
SAVRS
6.2
SAVR4
6.0

SAVR3

ENDCOD: O
.END

REC

ADDRESS/

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

ADRCNT= 017371
BEGIN
001202
BINWRD 017546
BITC
= 000020

3640
399
3693«
13014
16264

3675+«
428
3694
13264
16514
19764

20014

BITCLR= 000077

22054

22954

BITX

13014
16264
19514

19514

= 000000

BITOO = 000001
BITO1 = 000002
BITO2 =
BITO3 = 000010
BITO4 = 000020
BITO5 = 000040
BITO6 = 000100
BITO7 = 000200
BITO8 = 000400
BITO9 = 001000

BIT10 = 002000

BIT11

= 004000

2295
20854
30754
854
844
834
824
814
804
794
784
77#
764

1221

75#

74H
1486
1811

2140
2516
BIT12 = C10000

BIT13 = 020000

BIT14 =
BIT15 =
CBIT
=
CCRBIT=

040000
100000
000020
077777

CHRCNT 017544
CLRBIT= 000077

DATABP
DEVADR
DHBA
DHBAR
DHB(
DHBCR

016744
017366
017660
(017664
017662
017666

3302

734

72#

714
704
13014
22650

20554
3691
22054
20554
30454
33234
3554+
3638+

602
556
579
1887

14:40 PAGE 76
CROSS REFERENCE TABLE == USER SYMBOLS

36824
4348
37244
13514
16764

SEQ 0085

3506
13764
17014

14014
17264
20514

14264
17514
20764

14514
17764
21034

14764
18014
21304

15014
18
21574

15264
18514
2184w

15514
18764
22114

15764
19014

16014
19264
22654

2325

2355

238B5A

2415H

2445K

2475K

25054

2535#

25654

25954

26254

13264
16514
19764

13514
16764
20014

13764
17014
20264

14014
17264
20514

14264
17514
20764

14514
17764
21034

14764
18014
21304

15014
18264
21574

15264
18514
2184k

15514
18764
22114

15764

16014

19014

738
768
798
828
858
888
918
1064
1084
948

739
769
799
829
859
389
919
1172

741
771
801
831
861
891
921
1173

748
778
808
838
868
898
928
1176

25954
29854
33874

26254
30154
3419#

19264
22654

3444
1184

3446
1185

3448
1187

1193

2325k
27154
31054

1224

1104

649
1511
1836

2167
2546
2936
3334
978
1008
1144
1038
16764
22954
26854
3695
22954
26854
30754
3336
3557
3672
537
606
560
583
1912

23554
27458
31354

949

1231

1220

671
1536
1861

2194
2576

3366
979

1009

1268
1039
20764
2325

31954
3708«
23254
2715
31054
33554
64
36804
37574
37594
37584
691+
1937

2385
2775K
31654

951

24158
2B0SA
31954

2L4SH
2B354
3227

2475
2B654
32594

25054
28954
32914

25354
29254
33234

25654
29554
33554

26554
30454

1240

958

1171

1173

1176

1183

1192

1194

1197

1219

1242

1245

1267

1269

1272

1279

1288

1290

1293

693
1561
1886

715
1586
1911

131
1636
1961

1336
1661
1986

1361
1686
2011

1386

1411

1436

1461

1711
2036

1736
2061

1761
2086

1786
2113

3446

3448

1283

1289

1221

1224

2221
2606
2996
3398
981
101
1269
1041
22654
23554
32278
37224
23554
2745K
31354
3368
35674

2248
2636
3026
3433
988
1018
1272
1048
27154
23BSH
3259
3723
23854
27754
31654
33874

694
1962

701
1987

1232

1124
1611
1936

2276

3056
3466

1233

2306
2696
3086

3438

3440

1280

1281

3438

1235

2336
2726
3116

1241

2366
2756
3146

2396
2786
3176

2426
2816
3206

2456
2846
3238

2486
2876
3270

3440

3446

2445

475K

25054

2535H

25654

25954

26254

24154
2B0SAH
31954
3400

24454
28354
3208

24754
2B6SH
32278

25054
28954
3240

25354
29254
32594

25654
29554
3272

25954
29854
32914

26254
30154
3304

1687
2012

1712
2037

1737
2062

1762
2727

1787
2757

1812
2787

1837
2817

1862

31954
24154

32914

33234

33554

3448

33874

2847

2937
669+

2967
67

2997
679

2457

2487

2517

2547

2577

1123+

1510«
1835«

HILIM

ICOUNT

484>
796%
1143«
1535«
1860+

3892

3771#
3496*

3521«

507x
826+
1169«
1560+«
1885+«

530«
856+
1217+
1585+
1910+

2166%
2545«
2935+«
3333«
3570
3534
3540

2193x
2575«
2965+
3365«
35754
37744
35654

2220
2605+
2995«
3397«

765+
1122+

795«
1142+

825+
1168+

3637+
460

1509+

3
483«

36794
506+

1534«

1559«

3526

3544+

576+
916+
1310+
1635+

3555

599

946+
1335+
1660+
1985+

2247%
2635«
3025«
3431w

2305+
2695+
3085+
3578

2335+
2725+
3115+
37734

529+

575+
915+
1309+

598+
945+

855«
1216+

1584+

1634+

1334~
1659«

3561+

37694

S3% 3
»

3822+

668+
1036+
1410+
1735+

2060+
2425+
2815+
3205+

689+
1062+

1434+
1759

711+
1082+
1459+
1784»

350

3552
3560
461>
766%

3575+«
392«
35634
35394
38824
35804

3890

34934
390«
391«
3553«

39504
3888
38954
39014
39114
39214
39314
39414
39604

2249

3399

rnow

713
3303

2636%
3026+
3433«
3482

37624
629
3271

2606*
2996x
3398+
3479

2140*
2516%
2906
3302+
3469+

426*
625
3239

2576+
2966%
3366
3474

425+
425
3207
37664
37654
884
886
3883
3885
3887
3889
3891

2546%
2936%
3334«
3471

649

647
917
1104*
1218
1586+«
1911«
2248«

468
887
1093
1170
1561«
1886+
2221x

2427

37634
464
857
109
1153
1536«
1861«
2194x

1487

1612

414
422
827
1087
1151
1511«
1836+
2167%

3893
57

EXITER
FREEZ1
HALTS

37554

158

OH=O

37644

1562

» »

487

1537

1512

H=2N

017702
017700

2907
514

017672
017670

2877
510

SEQ 0086

J\—awuog
H =N &

017654
017676
017674
017652

CROSS REFERENCE TABLE == USER SYMBOLS

DHNRC
DHRL VL
DHRVE
C
DHSCR

017656

PAGE 77

n
o
o -]

DHLPR

14:40

WWINNUN)
= = b b —a
W—=OO
—OwWm
o
WNN

CZDHA=C MACY1 30A(1052)
23-AUG-78
15-MAY-78
CZDHAC.P11
1 0:02

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

INBUF

020400

1834«
2165+
2544
2934+
3332+
3615
394
3674

INIFLG 017744
INSTER= 104404
INSTR = 104403
INSTRE
017176
INSTRG 017104
INSTR1
017116
INSTR2 017204
LAST
017750
LIGHTS= 177570
LIMITS 017316
LOBITS 017370
LOGICA 016464
LOLIM
017362
LPCNT
017722
MCRLF
020235
MDATA
020424
MEPASS 020325

36284
36114
36134
3622
3495«
554
3653
3639«
373
3636~
3517«
3687
3706
3494

MSG

3611

MPFAIL
MM
MR
MREGAD

020240
020231
020337
020175

MTITLE
MTSTPC

020116
020343

1859+
2192+
2574+
%964'
364+
3643
427
3658

409
3865
3864
3630
36314
3541
3498+
36634
3667
35024
3665
3518
38434
3717
38534

020153

393
439
41?’

38444
38424
38554
38374
36144
38284
38564
38334

OCTASC= 104402
OCTASN 017372

365#
36864

3559
3863

017120

zVECTO

PARAM =
PARAMS
PARAM1
PARERR
PASCNT
PFAIL
PFTAB
POPRO =

104405
017206
017236
017312
017706
017752
020106
012600

POP1SP= 005726
POP2SP= 022626
PS

= 177776

3821
3629
451
418

36354
36420
3645
389+
348
3819
64k

411
3866
3659
3647
3497«
387
38254
3574

S64

385+

6o
664

688+
1061+
1433«

1758+

PUSHRO= 010046
PUSH1S= 005746
PUSH2S= 024646

2083+
2453%
2843+
5235+

634
614
654

710«
1081+
1458+

1783+

2110+
2483+
2873+
3267+
3571

14:40 PAGE 78
CROSS REFERENCE TABLE == USER SYMBOLS
1884+

1909+

219+
604 *
§994'
396+
387
629«

246+
34
3
o

37854

617

438

3543«

37874

36814

3682

36784
3520«

37764

1934+

274+
664 *
054«
65+

1959+

*
694 *
*
518

1984r

334«
724*
114+
37754

SEQ 0087
2009+
2364%
754%
144«

2034*
2394*
2784x
3174«

2059%

2424%
2814%
3204+

2084*

2111x

620+

644+

2454%
2844
3236

2484+
2874«
3268+

2138«

2514+
2904+
3300+

3823+

38774

3566

3818

419

440

3649
3498
37914

.
36584
37704
3812

434+

459+

734
1101«
1483«

1808+

2137+
2513«
2003+
3299+

764
1121
1508«

1833+

2164~
2543x
2933x
3331

3664

482+

794+
1141+«
1533«

1558+

2191x
2573x
2963«
3363+

3666

505+

824+
1167«
1558+

1883«

2218+
2603+
2993«
3395«

3668

528+

854~
1215+
1583«

1908+

2245+
2633*
3023«
3430

551«

884+
1263«
1608+

1933«

2273«
2663%
3053«
3463+

574x

914+
1308+
1633+

1958+«

2303%
2693x
3083+
3813«

597«

944 *
1333+
1658+

1983+

2333x
2723«
3113x

974+
1358+
1683*

2008+

2363+
2753«
3143+

1004+
1383+
1708+

2033+

J393n
2783«
3173«

666+

1034+
1408+
1733

2058+

423
JB13e
3203

3868
3728«
3741
3742
3743
3744
3745
3746
3798«
3545
475

SAVR3
SAVRG
SAVRS
SAVSP
SAVOSP=

017732
017734
017736
017740
104406

SCOPE = 104400

SCOPER 016500
SCOPE1= 104410
SCOPIR 01

SPACNT= 017545
STACK = 021360

START
001
STFLG
017746
SV05
017556
SVOSP
017550
SWR
= 177570
SW00 = 000001

Sw01
SW02
Sw03
SW04
SW05
Swoé6
SW08
Sw09
SWw10
SW11
Swi2

Sw13

= 000002
= 000004
= 000010
= 000020
= 000040
= 000100
= 000400
= 001000
= 002000
= 004000
= 010000

= 020000

SW14 = 040000
Sw15 = 100000
TEMP
020412
TKCSR
017642

TKDBR
TPCSR
TPDBR
TRPOK
TRPSRV

017644
017646
017650
017032
017020

756
1116
1500
1825

447

3522+

3524

786
1136
1525
1850

2156
2183
2534
2564
2924
2954
3322
3354
35114
3861
3714
35324
3869
3692«
3710
S7#
386
3854
355
388«
448
37324
3867
37284
S4u
398
374
398
364
436
354
344
334 34
314
304
29%
3532
3511
8%
3515
27#
264
3539
25#
24
3513
234
3696
3815+
2617
27504
3619
3623
3601
3624
3606+
3623«
35914
352
3588#

37724

017742
017724

443

3827

2294
2684
3074

2624
3014
3418

37234
3429

3824

3462

2814

3513

3515

2894
3290

37864
3511

2576

38754

VOO

37414
3582
3737«
3736
3735«
2734«
3733«
3732«
37834
3694
3634

RS 53N

017610

NNo
s

35684
38054
35064
3568

SEQ 0088

~OO~§§\Ao~

3565
3799
3500
3704

SAVPC
SAVRO

RSOS5

wVinD

016746

020010
016474
104407
017712

—_—

RESREG

RESTAR
RESTRT
RESOS =
RETRN

14:40 PAGE 79
CROSS REFERENCE TABLE == USER SYMBOLS

own

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P1
15-MAY-78 1 0:02

3532

3539

3569

3576

CZDHA=C MACY1 30A(1052)

CZDHAC.P1

;{PHSG

016716

110
1100
1101
1102
1103
T104
1105
1106
1107
18}
T110
T
1112
1113
T114
T115
1116
1117
T12
1120

002140
010236
010336
010436
010536
010636
010736
011036
011142
002234
011246
011352
011456
011562
on
011772
012076
012202
002314
12

1126
1127
T13
1130
T131
1132
T133
T134
T135
1136
1137
T14

013136
013242
002374
013346
013452
013556
013662
013766
014072
014176
014302
002454

T144
T145
T146
1147
T15
1150
T151
1152
T153

015026
015132
015246
015362
002540
015476
015612
015726
016042

001274

15-MAY-78

23-AUG-78
1 :0

14:40 PAGE 80
CROSS REFERENCE TABLE == USER SYMBOLS

38614
35644
393
3862
35594
45

651

3493

3562

3613

3628

SEQ 0089

3686

3716

3820

’
CZDHA=C MACY11 30A('|0;2)1 23-AUG-78
CZDHAC.P11
15-MAY-78 10:02
1156
1155

016156
016302

Té
T2
120

2626
001370
3002

123

00324

17
121
122

124

125

126
127

002714

003070
003156

003332

3420

34294
34620

7648
7944
L824
84N
8544
8844

914

bkt

974M

003506
003574

10044
10344

00
003736
004012
004066
004142
004216
004346
004476

10614
10814
11014
11214
11414
11674
12154
12634

001464

T4
40
41
%2

001560
004626
004716
005

5284
13084
13334
13584

T4
145
T46
47

005166
005256
005346
005436

14084
14334
14584
14834

150
151
152
153

005526
005616
005706
005776

15084
15334
15584
15834

155
156
157
16

006156
006246
0063
001750

161

006516

16334
16584
16834
S74M
17084

130
131
132
133
3%
135
136
137

154

T60

162
63

T6h

165
166
167
17

170
171

172
173
7%
175

005076

001654

006426

006676

006766

007056
007146
007236
002044

007326
007416

007506
007576
007666
007756

5054

13834

5514

16084

17334

17584
17834

18084

18334
18584
18834
5974
15084
19334

19584
19834
20084
20334

m7
14:40 PAGE 81
CROSS REFERENCE TABLE =- USER SYMBOLS

SEQ 0090

14:40

96
122
148
174
200
226
252
278
304
30

8274
1034
11704
1408
15614
1733
18864
2058
22214
2423
26064
2813
2
3203
33984
3684
98
124
150
176
202

228
254
280
306
32

EERBRYS

= 021162

2036#
2218
23964
2603
27864
2993
31764
3395
3674

5084

Noon)

= 000011

31954
505
647h
824
10074
1167
13864
1558
17114
1883

SEQ 0091

TELRSRE

W
W

N PONININD)
= = b b b

N 7

010046
010136
001060
001070
017542
000000
000000
000154

PAGE 82

CROSS REFERENCE TABLE == USER SYMBOLS

O NWVW =000 NN—=

176
177
VEC1
VEC2
WRDCNT
X
=
XBIT
=
XN
=

23-AUG-78

QUERQUIEE LR
3
228 =8

CZDHA-C MACY11 30A(1052)
15-MAY-78
CZDHAC.P11

CZDHA=C MACY11 gOA(1OS )
23-AUG-78
CZDHAC.P11
15-MAY-78
10:02

CODEM
HLT

3764
I
6
99¢

REGTS?7
RGADRS
TRPDEF
TS

1277
1468
1649

1286
1474
1668

2018
2209

2024
2229

2043
2236

2436
2653
2886
3103
3345
453
453
4S3%
4S3
453

1651

2026

1676

2051

1701

2076

2068
2263

1868

2473
270%
292
3156
3385
7
1097
1253

1351

1726

2103

2325

4534

476

499

522

2685
3135

»
1
794
1215

.ENDCO
.EOP
ERROR

%
#
4

ERRTA
.HEADE
.INSTR
MSG
.OCTAS
.PARAM
PFAIL
POINT
.RESRE

1#
14
1#
1#
1#
1%
1#
1#
1%

. SCOPE
.SCOP1

i*
14

START

TRPDE

SYMBO

1157
638
1301

466
2683
2916
3133
3377
757
1077
1205
660
1326

<049
2256

2295

BUFFE

SETVE

2443
2676
2893
3126
3353
727
1057

1849

538
836
1054
1318
1499
1693

2265

2423
2873
3331
#

. SAVRE

1843

515
814
1046
129g
149
1674

4538

1633

.CATCH

492
806
1024

1250
1449
1643

1824

REGTS1
REGT
REGTS
REGTSS
REGTS6

425
469
784
1016

2715
3165
363
459
824
1263

1658
2033

2453
2903
3363
3870
86

3960

3536

3879
3828
3632
3788
3748
3739

3725

344

3507
3529
376
358

2745
3195

364
482
854
1308

1683
2058

2483
33
3395

2775
3227
365
505
884
1333

1708
2083

2513
2963

14:40 PAGE 84
CROSS REFERENCE TABLE == MACRO NAMES

1874

561
844
1974
1324
1518
1699

1
1343
1524
1718

2074
2286

2094
3293

1893

584

1895

2496
2713
2946
3163
3409
817
117

2505
27
§9S
186
3417
847
1137

704
1376

1401

1426

2130

2157

2184

2805
3259

2835
3291

2865
3323

1751

2355
545

366
528
914
1358

1733
2110

2543
2993

1776

2385

568

367
551
944
1383

1758
2137

2573
3023

szg
274
§976
193
3442
877

607
874
1114
1349
1543
1724

1918

5101
312

253
2766
3
217
3450
907

1451

1801

1826

2415

2445

591

614

368
574
974
1408

1783
2164

2603
3053

2211

2895
3355
369
597

1004
1433

1808
2191

2633
3083

SEQ 0092

ggg

1134
1368
1549
1743

1154
1374
1568
1749

2121
5323

5128
342

1924

556
5773
3225
3475
937

1476
1851

2238

2475

2925
3387

1943

256
5593
1
3249
3483

19%
1
373
59
82?
3281

997

1027

754

1¢
141
15
1793

12
14624
19;3
1

12
144
1324
1818

1974

2175
383

1g~
3

1993
182
402

1999
20;
41

8
313

321

1926

1951

1576

1601

1976

2001

2505

2535

2565

2595

2625

2655

2955
371

1061
1483

1858
2245

2693
3143

2985

666

1081
1508

1883
2273

2723
3173

1551

746

1901

644

2663
3113

1949
14§
35
ssg
80
36
3257

1526

1876

370

183
2218

1393
1574
1768

702
934
1190
1399
1593
1774

1501

620

1034
145

380
56
1181

3015

688

1101
1533

1908
2303

2753
3203

3045

710

3075

734

1626

3105

764

1121

1141

1167

1558

1583

1608

1933
2333

2783
3235

1958
2363

2813
3267

1983
2393

2843
3299

CZDHA-C MCV‘I‘I
CZDHAC.P11
. TRPSR
.TRPTA
. TYPER
.VARIA
. ABS.

(‘IO )

23-AUG~78

c 8
14:40 PAGE 85
CROSS REFERENCE TABLE == MACRO NAMES

1#
3583
#
3858
1w
359
‘w3767
021162

ERRORS DETECTED:

000
O©

CZDHAC .BIN, CZDHAC.LST/CRF
/SOL/NL : TOC=C ZDHAC . SML , CZDHAC .P11

RUN-TIME: 8 13 1 SECONDS

RUN-TIME RATIO: 101/24=4.2
CORE USED:
11k
(21 PAGES)

SEQ 0093