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AH-8445C-MC

January 1979

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Document:	CZDHAC0 DH11 STATIC LOGIC TEST JAN 1979 bw
Order Number:	AH-8445C-MC
Revision:	000
Pages:	94
Original Filename:	CZDHAC0__DH11__STATIC_LOGIC_TEST__AH-8445C-MC__JAN_1979_bw.pdf

OCR Text

STATIC LOGIC TEST

CZDHACO

AH-8445C-MC

JAN 1979

FICHE1 OF
1

MADE
IN USA

!fl:fluafl

.REM

SEQ 0001

[DENTIFJCATION

THE

PRODUCT

CODE
:

AC-B444(-MC

PRODUCT

NAME:

(ZDHACO DH11

STATIC

DATE:

MAY 1978

MAINTAINER:

DIAGNOSTIC GROUP

AUTHGOR :

MICHAEL DAVIS

INFORMATION IN THIS DOCUMENT

1S SUBJECT

LOGIC

TEST

TO CHANGE W] THOUT

NOTICE AND SHOULD NOT BE CONSTRUED AS A COMM]ITMENT BY DIGITAL
EQUIPMENT CORPORATION.
DIGITAL EQUIPMENT CORPORATION ASSUMES
%C(RE’ES:?JSIBIUTY FOR ANY ERRORS THAT MAY APPEAR IN THIS

DIGITAL EQUIPMENT CORPORATION ASSUMES NO RESPONSIBILITY
FOR THE USE OR RELIABILITY OF ITS SOF TWARE ON EQUIPMENT
THAT

IS NOT

SUPPLIED Br

(C)

1972,

DIGITAL.

1978 BY DIGITAL EQUIPMENT CORPORATION,

MAYNARD, MASSACHUSETTS.

THE FOLLOWING ARE
DIGITAL
o8

TRACEMARKS OF DIGITAL EQUIPMENT (ORPORATION

PDP

DECUS

UNIBUS

DECTAFE

MASSBUS

ABSTRA(T
THE

DH11

SEQ 0002
STATIC

LOGIC

TEST

IS DESIGNED

FOR TESTING THE CORRECT FUNCTION OF
IN THE FOLLOWING DH11 REGISTERS:

DH*Y

SYSTEM CONTROL REGISTER

DH11

LINE PARAMETER REGISTER

TO PROVIDE

A MEANS

ALL READ/WRITE BI'S

DHY1 BREAK (ONTROL REGISTER
DH11

S1LO STATUS REGISTER

IN ADDITION, TESTS ARE PROVIDED TO CHECK THE FUNCTION
OF THOSE BITS THAT ARE READ ONLY IN MAINTENANCE MODE.
ALSO PROVIDED ARE TESTS OF REGISTER ADDRESSABILITY,
AND OF THE FUNCTION OF MASTER CLEAR.
THE

DIAGNOSTIC HAS BEEN WRITTEN 50 THAT

EACH FUNCTION IS CONTAINED

TEST

LOOP.

THE

TESTING

IN AN IND]VIDUAL

REQUIREMENTS

SEQ 0003

EQUIPMENT

~no

PDF=11 FAMILY STANDARD (OMPUTER WITH kW OF MEMORY
ASR-33 TELETYPE OR EQUIVALENT
DH11 ASYNCHRONOUS MULTIPLEXER
DM11 MAINTENANCE CARD INSTALLED
STORAGE
THE

PROGRAM LOADS

INTO 8kw COF

MEMORY

LOADING PROCEDURE
THE

STANDART

PROCEDURE

fOR

IS TO BE USED

LOADING ABSOLUTE

BINARY

TAPES

STARTING PROCEDURE
CONTROL

SWITCH SETTINGS

AFTER PROGRAM LOAD

ALL

CONSOLE

TO MODIFY

(INITIAL

PROGRAM START)

SWITCHES DOWN

DEVICE

VECTOR AND

AFTER PROGRAM RESTART

CONTROL

SW00-1
TO START

PROGRAM AT

SELECTED

TEST

FOR ALL

TESTS

AFTER PROGRAM RESTART

SWO1=1
STARTING ADDRESS
THE

STARTING ADDRESS

THE RESTART ADDRESS FOR ALL

.
W

THE
2T o

0002000

TO ENTER A SELECTED

TEST

1S 000200

VSN ANN) =

)
d
—

INITIAL PROGRAM START

—d

—

.
W

2F L

FROGRAM AND/OR OPERATOR ACTION

. L]
.
.
.
WWIWWW
. L]
.
L]

[P SN A

STARTING ADDRESS

TESTS

IS 000200

LOAD PROGRAM INTO MEMORY

LOAD ADDRESS 000200
CLEAR CONSOLE

SWITCHES

PRESS START
THE PROGRAM WILL

TYPE

'DH11

STATIC

LOGIC

TEST

AND WILL THEN TYPE ‘VECTOR ADDRESS-'' AND WAIT FOR AN
INPUT FROM THE TELETYPE KEFYBOARD.

(.3

(CONT'D)

4« 3.7.6 TYPE
FOR

NOTE:

SEQ 0004
IN THE ADDRESS OF

THE

WORDS
THE

DH11

TO BE

THE RECEIVER INTERRUPT VE(CTOR

TESTED FOLLOWED BY <CARRIAGE RETURN>

IN ANGLE BRACKETS,

TELETYPE

I.E.

<CARRIAGE RETURN> MEAN THAT

KEY WITH THE NAMED FUNCTION SHOULD BE

STRUCK

IF AN _INCORRECT ADDRESS IS ENTERED, THE PROGRAM
WILL TYPE """ AND WILL REPEAT THE SECOND MESSAGE
OF 4.3.1.5

6¢.3.7.7 THE PROGRAM WILL TYPE '‘CONTROL REGISTER ADDRESSAND WAIT FOR AN INPUT FROM THE TELETYPE KEYBOARD

6¢.3.1.8 TYPE
DH11

IN THE ADDRESS OF THE SYSTEM CONTROL REGISTER OF
TO BE TESTED FOLLOWED BY <CARRIAGE RETURN>

[F AN INCORRECT ADDRESS IS TYPED, THE PROGRAM WILL
"7'" AND WILL THEN REPEAT THE MESSAGE OF 4.3.1.7

THE

TYPE

64.3.1.9 THE PROGRAM WILL TYPE 'R'' TO INDICATE THAT IT IS
ABOUT TO START TESTING, AND THEN TESTING WIiLlL BF3IN
4.3.2

PROGRAM RESTART WITH ALL

4£.3.2.1

PERFORM 4.3.1.2 T0 4.3.1.5

4.3.2.2 THE PROGRAM WILL
AND WILL

SWiTCHFS DOWN

TYPE ‘DH11

THEN CONTINUE

STATIC

AS DESCRIBED

LOGIC

4.3.3

PROGRAM RESTART WITH SW00=1

4.3.3.1
4.3.3.2
4«.3.3.3
4.3.3.4

LOAD ADDRESS 000200
SET SWO1-1
PRESS START
THE PROGRAM WILL PERFORM AS DESCRIBED

4.3.4

PROGRAM RESTART WITH SWO'

4.3.4.1 LOAD ADDRESS 000200
6.3.4.2 SET SWO1=1
4.3.4.3 PRESS START
4.5.6.4

THE PROGRAM WILL

AND WILL

FROM THE

TYPE

TEST"'

IN 4.3.1.9

IN 4.3.°.5

70 4.3.1.9

‘DH11

STATIC

LOGIC

TEST"

THEN TYPE °'‘TEST PC-'* AND WILL WAIT FOR AN INPUT

TELETYPE

KEYBOARD

4.3.4.5 TYPE IN THE ADDRESS OF THE TEST AT WHICH THE PROGRAM IS TO
BE LTARTED FOLLOWED BY <CARRIAGE RETURN>
4£.3.4.5

THE PROGRAM WILL TYPE R TO INDICATE THAT IT HAS
AND WILL START TESTING AT THE SELECTED TEST.

NOTE:

CARE MUST BE
THERE

IS
NOTF :

TAKEN WHEN THS FEATURE

IS NO PROTECTION AGAINST

IN THE MIDDLE OF A TEST

IS USED,

STARTED

SINCE

SELECTING AN ADDRESS

THAT

If IT IS DESIRED TO LOOP ON THE TEST THAT [S SELECTED
SET SW14 1 BEFORE ENTERING THE TEST ADDRESS

OPERATING PROCEDURE

€

Hon
nn

OPERATIONAL SWITCH SETTINGS
%1%

5.1

SEQ 0005

HALT ON ERROR

—

1. LOOP ON CURRENT TEST
SW13=1, SUPPRESS ERROR TYPEOUT

SW11=1,
SW10=1,
SWO9=1,
SW01=1,
SWO0=1,

INHIBIT ITERATIONS
ESCAPE TO NEXT TEST ON ERROR
FREEZE VARIABLE PARAMETER IN CURRENT TEST
START PROGRAM AT SELECTED TEST
CHANGE PARAMETERS AT PROGRAM RESTART

5.2

SUBROUT INE

5.2.1

TRAPCAT(CHER
THIS

ABSTRACTS

ROUTINE

(LOCATIONS 000000-000776)
IS

USED

INTERCEPT

UNEXPECTED

IS LOADED

QoM

AND TRAPS.
THE AREA FROM 000000-000776
WITH THE FOLLOWING SEQUENCE

INTERRUPTS

776

IF AN UNEXPECTED INTERRUPT OR TRAP OCCURS, THE PROGRAM
WILL HALT WITH THE PC 2 GREATER THAN THE ADDRESS TO
WHICH

THE

PROGRAM

TRAPPED.

THE

BE EXAMINED TO DETERMINE WHERE
TRAP OR INTERRUPT OCCURED.

5.2.2

START

THE

BESIN

INITIALIZES ALl

PROGRAM

AND CONTROL

5.2.3

STA(K MAY

PROGRAM WAS WHEN

THE

(PROGRAM INITIALIZATION)

THIS ROUTINE
TY2ES

PROCESSOR

THE

TITLE

PROGRAM FLAGS AND

MESSAGE,

AND

THE

COUNTERS,

INPUTS

TH'

DH11

TO BE

VECTOR

TESTED.

(PROGRAM START AND RESTART)

THIS ROUTINE

IS ENTERED

IMMEDIATLY AFTER °‘‘START''

AND EACH TIME A PROGRAM PASS HAS BEEN COMPLETED.
THE

ROUTINE

SETS UP

THE

TESTING WILL BEGIN.

PROCESSOR STACK AND

AND THEN TRANSFERS CONTROL

TO THE

STATUS WORD

TEST AT WHICH

SWO1-0 WHEN

THIS ROUTINE

ENTERD

TESTING WILL START AT T1 (TEST 1).
[IF SW01=1 WHEN
THIS ROUTINE IS ENTERED, TESTING WILL START AT THE P(
ENTERED FROM THE TELETYPE KEYBOARD.

5.2.4

gEoP

(END OF PASS)

SEQ 0006

THIS ROUTINE IS ENTERED ONCE PER PASS AFTER ALL TESTS
HAVE BEEN COMPLETED.
THIS ROUTINE TYPES THE MAINDEC
IDENTIFICATION CODE OF THE PROGRAM, CLEARS ERROR FLAGS
AND UPDATES THE PASS COUNT.
IF THE PROGRAM WAS LOADED
UNDER ACT11 OR DDP, THE ROUTINE CHECKS FOR RETURN TO
THE ACT11 OR DDP MONITOR.
IF THE PROGRAM IS NOT UNDER
MONITOR CONTROL, THE ROUTINE TRANSFERS TO BEGIN.

5.2.5

SCOPER

(SCOPE LOOP AND ITERATION HANDLER)

THIS ROUTINE IS ENTERED EACH TIME A TEST IS COMPLETED.
THE ROUTINE CHECKS FOR THE FOLLOWING UPON ENTRY

8)
()

IF SW10=1, THE ROUTINE WILL TRANSFER TO THE NEXT TEST
IN SEQUENCE, AFTER CLEARING ERROR FLAGS.
IF 7.1=1, THE ROUTINE WILL TRANSFER TO THE NEXT TEST
SEQUENCE, AFTER CLEARING ERROR FLAGS.
IF SW14=1, THE ROUTINE WILL LOOP ON THE CURRENT TEST
REGARDLESS OF THE ITERATION COUNT.

IF NONE OF THE ABOVE IS TAuk, THE ROUTINE WILL ADL 1
TO THE COUNT OF TEST ITERATIONS, AND COMPARE THIS VALUE
TO THE NUMBER OF ITERATIONS THAT SHOULD BE PERFORMED.

THESE NUMBERS ARE EQUAL,

TO THE NEXT

EQUAL,

5.2.6

THE

TEST

THE ROUTINE WILL

IN SEQUENCE.

CURRENTLY

THE

TRANSFER

THE NUMBERS ARE

NOT

IN PROGRtSS WILL BE REPEATED.

SCOPTIR

(FREEZE ON CURRENT DATA)

THE
THE

TO THIS ROUTINE FOLLOWS IMMEDIATLY AFTER THE
TO THE ERROR HANDLER IN THOSE TESTS THAT HAVE

CALL
CALL

VARIABLE PARAMETERS.
THOSE

TESTS,

IF SW09=1,

THIS ROUTINE

IS ALWAYS ENTERED

WHETHER OR NOT AN ERROR OCCURS.

THE ROUTINE WILL

TRANSFER CONTROL BACK TO THE

TEST AT A POINT WHICH WILL ALLOW REPEATING THE

FUNCTION

UNDER TEST CONTINUOUSLY WITH THE SAME DATA.
[F TH]S
OPTION IS SELECTED, THF ROUTINE '‘SCOPER'' IS NEVER ENTERFD

AND

ITERATION COUNTS WILL

NOT BE

JPDATED.

s.2.7

ERRORS

(ERROR HANDLER)

SEQ 0007

THIS ROUTINE IS ENTERED UPON ERROR DETECTION ONLY.
WITH ALL CONSOLE SWITCHES DOWN, THE ROUTINE PROCEDES AS FOLLOWS:
A) THE PC OF THE INSTRUCTION THAT CALLED THE ERROR HANDLER

IS ACCESSED THRU THE STACK, AND THEN THE EMT INSTRUCTION
ITSELF IS FETCHED.
THE 8 LSB OF THE EMT
INSTRUCTION ARE THE ERROR CODE.
THIS CODE IS
USED TO ACCESS A TABLE OF ERROR MESSAGES AND ERROR

B8)

5.2.8

DATA STORAGE LOCATIONS.
IF THE TEST THAT FAILED DID NOT FAIL PREVIOUSLY
DURING THIS PASS.
A COMPLETE ERROR REPORT IS MADE
IF THE TEST THAT FAILED FAILED MOR THAT ONCE DURING
THE

CURRENT PASS,

THE
THE
THE

ROUTINE NOW CHECKS FOR HALT ON ERROR.
IF SW15=1
PROGRAM WILL HAL:
JITH THE PC OF THE CALL TO
ERROR ROUTINE IN RC.
IF Sw15=0, THE PROGRAM WILL

IS TYPED.

NOT HALT,

ONLY

IF SWi3=1

BUT WILL

THE

DATA RELATING TO THE

NO ERROR TYPEOUT IS MADE.

CMECK FOR ESCAPE

IF sw10=0. THE ROUTINE WILL RETURN

TO NEXT

FAILUER

TEST.

TO THE TEST IN PROGRESS.
IF Sw10=1. THE ROUTINE WILL
ABORT THE CURRENT TEST, AND TRANSFER TO THE NEXT
TEST IN SEQUENCE, THRU THE ROUTINE '‘SCOPEP''.

TRPSRV

(TRAP DECODE AND DISPATC(H)

THIS ROUTINE

DECODES

THE

8 LSB OF

THE

TRAP

INSTRUCTION

THAT CAUSED TH PROGRAM INTERRUPT, AND TRANSFERS CONTROL
TO THE ROUTINE THRU THE TABLE '‘TRPTAB'' USING THE 8 .SB
Of THE TRAP INSTRUCTION AS
AN UFFSET TO THE PQOINTER TO
THE

ROUTINE

TO BE

ENTERED.

5.3

PROGRAM AND OR OPERATOR ACTION

5.3.1

PROGRAM START WITH ALL

SEQ 0008

SWITCHES DOWN

5.3.1.1 REFER TO SECTIONS 4.3.1 AND 4.3.2 FOR INITIAL PROGRAM
BEHAVIOR.

5.3.1.2 AFTER 'R'' HAS BEEN TYPED BY THE PROGRAM,

TEST EXECUTION

WILL BEGIN.
EACH TEST WILL BE REPEATED A SELECTED NUMBER
OF ITERATIONS (SEE LISTING FOR EXACT NUMBER FOR EACH TEST)
AND THEN THE PROGRAM WILL PROCEED TO THE NEXT TEST.

5.3.1.3 WHEN ALL ITERATIONS HAVE BEEN COMPLETED, THE PROGRAM
WILL TYPE "‘CZDHA=('' AND THEN RESTART TESTING AT TEST 1
(LOCATION T1

IN THE PROGRAM).

5.3.1.4 IF AN ERROR OCCURS,
ERROR MESSAGE,

5.3.2

AND

THE PROGRAM WILL
THEN CONTINUE THE

TYPE AN APPROPRIATE
TEST IN PROGRESS.

PROGRAM START WITH Sw00=1

THE

PROGRAM WILL PERFORM AS DESCRIBED

5.3.3

PROGRAM START WITH Sw01=1

5.3.3.1

REFER

TO SECTION 4.3.4

FOR

INITIAL

iN 4.3.7

AND

5.3.1

PROGRAM BEHAVIOR

5.3.3.2 TEST EXECUTION WILL START AT THE ADDRESS SPECIFIED
AND WILL

CONTINUE AS DESCRIBED

5.3.3.3 AFTER ''CZDHA-C'' HAS BEEN TYPED,
RESUME

5.3.4

TESTING AT

TEST

PROGRAM OPERATION WITH

IN 5.3.1.2

THE PROGRAM WILL

SW*5=1

SAME AS 5.3.1, EXCEPT THAT IN THE CASE OF AN ERROR,

THE PROGRAM WilL HALT AFTER THE ERROR TYPEOUT. AND
THE PC+2 OF THE CALL TO THE ERROR ROUTINE WILL BE
DISPLAYED IN RO.

5.3.5

PROGRAM OPERATION WITH SW13=1

SAME AS 5.3.1 EXCEPT THAT NO ERROR TYPEOUTS WILL OCCUR
5.3.6

PROGRAM OPERATION WITH SW11=1

Szrs AS 5.3.1

5.3.7

EXCEPT THAT EA(CH TEST WILL BE REPEATED ONCE

PROGRAM OPERATION WITH SW10=1

SAME AS 5.3.1, EXCEPT THAT

[N THE CASE OF AN ERROR

THE CURRENT TEST WILL BE ABORTED, AND THE PROGRAM
WiLl PROCEED TG THE NEXT TEST IN SEQUENCE.

(Vo)

5.3.8

(CONT'D)

SEQ 0009

PROGRAM OPERATIOM WITH
THESE

FUNCTIONS ARE

SW14=1,

SW09=1

NORMALLY USED FOR

SEE SECTION 6.3 FOR THEIR USE.

TROUBLE

SHr ,TING.

ERRORS
ERROR HALTS
THE

ERROR MESSAGE

IS AS FOLLOWS
PC+2

FORMAT

FOR ALL

ERROR

TYPEOUTS

ME SSAGE
HEADER (IF APPLICABLE)
DATA
(IF APPLICABLE)

WHERE
PC+2 IS THE ADDRESS OF THE CALL "O THE ERROR HANDLER + 2
MESSAGE IS AN ASCI] MESSAGE DESCRIBING (BRIEFLY) THE FAILURE
HEADER IS A DESCRIPTION OF THE DATA TO FOLLOW
DATA IS OCTAL INFORMATION RELATING TO THE CAUSE OF THE FAILURE

THE

SAME ERPOR OCCURS IN A GIVEN TEST ON THE SAME

PASS, AND IF
DATA IS TYPE

DATA IS ASSOCIATED WITH THAT ERROR,
ON SUCCEEDING ERROR TYPEOUTS

ONLY

IF _NO DATA IS ASSOCIATED WITH THE ERROR

THE

6.1.1

COMPLETE

ERROR MESSAGE

TYPED.

ERROR DESCRIPTIONS

SEE LISTING FOR DETAILS OF

6.2

ERKOR RECOVERY

6.2.1

SW15=0
IF

6.2.2

THE PROGRAM IS RUN WITH SW15-0, NO OPERATO~ ACTION IS

REQUIRED

SW15-1
IF

ERRORS

TO CONTINUE

TESTING

THE PROGRAM IS QUN WITH SW15=1,

AFTER THE PROGRAM HAS HALTED,
CONSOLE CONTINUE SWITCH

PRESS

TO CONTINUE

TESTING

THE PROCESSOR

SCOPE LOOPING

TO SCOPE ON A SPECIFIC
THIS WILL

SAME

CAUSE

TEST,

SET SW14=1

AND SW13 1

THE PROGRAM TO CONTINUOUSLY LOOP ON

TEST, AND WILL CAUSE ALL ERROR TYPEQUTS TO BE

TO SCOPE ON A SPECIFIC

VALUE

A TEST, SET SW09=1 TO FREEZE
(SEE LISTING FOR THOSE TESTS

THE

INHIBITED

A PARAMETER WITHIN

THE DATA
THAT [NCORPORATE

THIS FEATURE)

(CONT'D)

SEQ 0010

PROGRAM START

TO SCOPE

LOOP ON SELECTED

TEST

PERFORM SECTION 4.3.4 WITH SW14=1
RESTRICTIONS

STARTING
THE

DH11

TEST

CARD MUST BE

INSTALLED

RUNNING

NONE
MISCELLANEOUS

EXECUTION TIME

IS GIVEN FOR VARIOUS PROCESSORS
PROCESSOR

PDP-11/05,10
PDP=-11/20

PDP-11/40

PDP-11/45

TIME

IN THE

TABLE BELOW

PROGRAM DESCRIPTION

THIS PROGRAM IS A LOW LEVEL
REGISTERS.

SEQ 001
TEST OF DH11

CONTROL

THE PROGRAM BEGINS BY CHECKING THE ADDRESSABILITY OF

EACH DH11

THE PURPQSE OF THESE TESTS IS TO VERFIY THAT THE ADDRESS
SELECTORS FOR THE VARIOUS REGISTERS ARE FUNCTIONING.
THE NEXT

SET OF

TESTS VERIFIES

THAT EACH DH11

CAN BE MASTER CLEARED, AFTER ALL READ/WRITE BITS HAVE
BEEN SET TO 1,
THIS TEST DOES NOT VERIFY THAT ALL
BITS HAVE BEEN SET, ONLY THAT THEY HAVE BEEN CLEARED.
THE _NEXT GROUP OF

IN THE DH11

TESTS EXEnCISES EACH READ/WRITE BIT

SYSTEM CONTROL REGISTER,

IN BOTH NORMAL AND

MAINTENANCE MODES OF OPERATION.
IN NORMAL MODE, EA(CH
READ/WRITE BIT IS SET AND CLEARED, AND READ ONLY BITS
ARE CHECKED FOR READ ONLY FUNCTION.

IN MAINTENANCE MODE, THE BITS THAT ARE
READ ONLY IN NORMAL MODE ARE CHECKED FOR READ/WRITE OPERATION.
THE NEXT GROUP OF

THE DH11

TESTS CHECKS EACH READ/WRITE BIT

LINE PARAMATER REGISTER, BREAK CONTROL REGISTER

AND SILO STATUS REGISTER FOR READ/WRITE CAPABILITY. EACH
BIT OF EACH REGISTER IS CHECKED IN AN INDIVIDUAL TEST LOOP.

THE NEXT GROUP OF TESTS CHECKS CLEARING OF A SINGLE
BIT IN EACH OF THE LINE PARAMETER, BREAK CONTROL AND
gé%OTST?TUS REGISTERS WITH ALL OTHER READ/WRITE BITS
THE FINAL TWO TESTS VERIFY THAT A MOVE BYTE TO ONE BYTE
OF THE SYSTEM CONTROL REGISTER DOES NOT AFFECT THE OTHER BYTE
OF THE SYSTEM CONTROL REGISTER.
AFTER ALL

TESTS HAVE BEEN COMPLETED,

THE

"'CZDHA-C'' AND RESTARTS THE SEQUENCE OF

10.

LISTING

PROGRAM TYPES

TESTING JUST DESCRIBED.

CZDHA-C MACY11 30A(1052)
23-AUG~78
CZDHAC.P11
15-MAY-78 10:02

14:40

PAGE 2

SEQ 0012

sDH11 STATIC LOGIC_TEST
: COPYRIGHT 1972,1978, DIGITAL EQUIPMENT CORP., MAYNARD, MASS. 01754

2
3
4

5
6
7
8
9
10
1"
12
13
14
15
16
17
18
19

20
21
22
23
24
25

2’8

29
30
3
32
33
34
35
36
37
38

s STARTING PROCEDURE
;LOAD PROGRAM
;LOAD ADDRESS 000200

;PRESS START

sPROGRAM WILL TYPE DH11 STATIC LOGIC TEST

;PROGRAM
;TYPE IN
;FOR THE
;PROGRAM
;TYPE

WILL TYPE ‘VECTOR ADDRESS-''
THE ADDRESS OF THE RECEIVER INTERRUPT VECTOR
DH11 TO BE TESTED, FOLLOWED BY <CARRIAGE RETURN>
WILL TYPE ‘'CONTROL REGISTER ADDRESS-"'

IN THE ADDRESS OF

THE

SYSTEM CONTROL REGISTER

;FOR THE DH11 TO BE TESTED, FOLLOWED BY <CARRIAGE RETURN>

;PROGRAM WILL TYPE 'R’
;AT THE END OF

A PASS,

SAND THEN RESUM TESTING

TO INDICATE THAT TESTING HAS STARTED

PROGRAM WILL

TYPE '’ CZDHA-L

;SWITCH REGISTER OPTIONS

100000

040000
020000
010000
004000

002000

001000
000400
000100
000040
000020
000010
000004
000002
000001

SwW15=100000

:=1,HALT ON ERROR

SW13=20000
SW12=10000

;=1,INHIBIT ERROR TYPEOUT

SW14=40000

Sw11=4000
SW10=2000

SW0%=1000
Sw08=400
SW06=100
SW05=40
SW04=20
SwW03=10
SW02=¢4
SW01=2
Sw00=1

;=1,L00P ON CURRENT TEST

;=1,INHIBIT ITERATIONS
:=1,ESCAPE TO NEXT TEST ON ERROR

;-1,L00F WITH CURRENT DATA

JRESTART PROGRAM AT SELECTED TEST
JRESELECT VECTOR AND CONTROL REGISTER
;ADDRESS AFTER PROGRAM RESTART

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

14:40

PAGE 3

SEQ 0013

JREGISTER DEF INITIONS

000000

RO=X0

;GENERAL REGISTER

45
46
47
48

000002
000003
000004
000005

R2=%2
R3=%3
R4=24
R5=%5

sGENERAL
+GENERAL
;GENERAL
sGENERAL

000007

PC=%7

000001

002006

2%
54
55
56
gg

69
70
71

72
73
74

75
76
77
78

8C
81
82
83
84
85

SP=%6

sGENERAL REGISTER

sPROCESSOR STACK POINTER

:PROGRAM COUNTER

sLOCATION EQUIVALENCIES
177570
177570
177776
021360

28
61
62
63
64
65
66
gg

R1=%1

SWR=177570
;CONSOLE SWITCH REGISTER
LIGHTS=177570
;PDP-11/45 DISPLAY REGISTER
PS=177776
sPROCESSOR STATUS WORD
STACK=ENDCOD+200;
START OF PROCESSOR STA(CK

SINSTRUCTION DEFINITIONS
005746
005726
010046
012600
024646
022626

100000

040000

PUSH1SP=5746
POP1SP=5726
PUSHR0=10046
POPR0O=12600
PUSHZ2SP=24646
POP2SP=22626
.EQUIV EMT,HLT
T15=1000OO

81T14=40000

020000
010000

B1713=20000
BIT12=10000

002000
001000
000400
000200

BI710=2000
BIT709=1000
BI108=400
BIT07=200

004000

000100

000040
000020
000010
000004
000002
000001

BI1T11=4000

BIT06=100

BIT05=40
BIT04=20
BIT03=10
BIT02=4
BITO01-?
BIT00-1

sDECREMENT PROCESSOR STACK 1 WORD
s INCREMENT PROCESSOR STACK 1 WORD
;SAVE RO ON STACK
sRESTORE RO FROM STA(K
;DECREMENT STACK TWICE
s INCREMENT STACK TWICE
;BASIC DEFINITION OF ERROR CALL

(ZDHA-C MACY11

CZDHAC.P1I
86
87
88
89
90

000C00
000002
000004

9%
97
98
99

000020
000022
000024
000026

91
92
93
9%
95

000006
000010
000012
000014
000016

100
101
102

000030
000032
000034

106

000040

108
109

000050
000052

103

105
106
107
110
111
112

113
114
115

116
117
118
119
120

121

122

000036

30A(1052)

000000
000002
000C00
000006

000000
000012
000000
000016
000000

000022
000000
000026
000000
000032
000000
000036

000000

000042

000042
000044
000046

000000
000046
000000

000054
000056
000060

000056
000000
000062

000062
000064
000066

000070
000072
000074
000076
000100

000102

000104

28‘&)6*’8

15-MAY-78 10:02

000052
000000

14:40

. 0

PAGE

SEQ 0014

;TraP(ATCAEF FOR ILLEGAL INTERRUPTS
.+
HAL T
.+2

HALT
. ¢2
HAL T
.42
HAL T

.+
HALT
.2
HALT
.¥2
HALT
.+
HALT
.42

SUNEXPECTED TRAP TO THIS LOCATION
SJEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION

SEXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TC FIND CAUSE

SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCAT.ON
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION

SEXAMINE STACK TO FIND CAUSE

JUNEXPECTED TRAP TO THIS LOCATION

HALT
.42
HALT
.+2
HALT

;EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE

.+2
HALT
.+2

SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE

JUNEXPECTED TRAP TO THIS LOCATION

000000
000066
000000

HALT
.+2
HALT

000000

HAL 7

SEXAMINE STACK TO FIND CAUSE

000072
000000
000076
000000
000102

000106

.+2
HALT
.2
HALT
.42
.42

;EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION

JUNEXPECTED TRAP TO THIS LOCATION

123

000106

000000

HALT

JEXAMINE STACK TO FIND CAUSE

125
126
127

000112
000114
000116

000000
000116
000000

HAL T
R4
HALT

;EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE

000000
000126
000000
000132
000000
000136
000000
000142
002000

HAL T
4
HALT
.42
HA_T
.42
HA_T
.2
HAL T

JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION

HAL T

;EXAMINE

126

128

129
130
131
132
133
134
135
136
137

138
139
140
141

000110

000120

000122
000124
000126
000130
000132
000134
000136
000140
000142

000144
000146
000150

000152

006112

000122

000146
000000
000152
000000

4
HAL T
.2

JUNEXPECTED TRAP TO THIS LOCATION

SJEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE

JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
STACK

TO FIND CAUSE

gow\lo«mbwr\)—-o
W)
—

'Y
W
W
W
D QU
S
N S
N

O\ OO\

T S

NN UM NN NNV

CZDHA=-C MACY11 30A(1052)
23-AUG-78
CZDRAC.P11
15-MAY-78 1 0:02

164

CRIRECLBBRIRRRETRE

—

) e

) ed

b ed —d e

ved

)

b aed —ed

) ad

D —

179

000156
000000
000162
000000
000166
000000
000172
000000
000176
000000
000202
000000
000206
000000
000212
000000
000216
000000
000222
000000
000226
000000
000232
000000
000236
000000
000242
000000
000246
000000
000252
000000
000256
000000

14:40

PAGE S
.42

HALT

.42

HALT

.42

HALT

.+2

HALT

.42
HALT

.42

HALT

.42

HALT

.42

HALT

.42

HALT

.42

HALT

.42

HALT

.42

HALT

.42

SEQ 0015

JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
:UNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TC FIND CAUSE
UNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SJEXAMINE STACK TO FIND CAUSE
UNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
UNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO F' D CAUSE
JUNEXPECTED TRAP TC (HIS LOCATION

SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE >TACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE

CZDHA-C MACY11 30A(1052)
23~AUG-78
CZDHAC.P11
15-MAY=-78 10:02

000336

000000
000342
000000

NN
NN NN

b d_d2-2
-

O~NONE WO

207

219

000346
000000
000352
000000
000356
000000
000362
000000
000000
000372
000000
000376
000000
000402
000000
000000
000412
000000
000416

000422
000000
000426
000000
000432
000000
000000
000442
000000
000446
000000
000452
000000
00056
000000
000462
000000

000000
000472
000000
000476
000000
000502
002000
000506
000000
000512
000000

164:40

PAGE 6

.42

HALT

.42

HALT

SEQ 0016

SJUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
sUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TC FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATICN
JEXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
UNEXPECTED TRAP TO T+'°

LOCATION

JEXAMINE STACK TO FIN' _AUSE
JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SJEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SJEXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

254
255
256

000514
000516

258

000524

000516
000000
000522
000000
000526
000000
000532
000000
000536
000000
000542
000000
000546
000000
000552
000000
000556
000000
000562
000000
000566
000000
000572
000000
000576
000000
000602
000000
000606
000000
000612
000000
000616
000000
000622
000000
000626
000000

14:40

PAGE 7
.42

SEQ 0017

JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TC FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
EXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAF TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
;UNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
EXAMINE STACK TO FIND CAUSE

JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
SEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION

;EXAMINE STACK TO FIND CAUSE

CZDHA-C MACY11 30A(1052)
2(3)-AUG-78
CZDHAC.P11
15-MAY-78 10:02

310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343

000674
000676
000700
000702
000704
000706
000710
000712
000714
000716
000720
000722
000724
000726
000730
000732
000734
000736
000740
000742
000744
000746
000750
000752
000754
000756
000760
000762
000764
000766
000770
000772
000774
000776

000676
000000
000702
000000
000706
000000
000712

000000
000716
000000
000722
000000
000726
000000
000732
000000
000736
000000
000742
000000
000746
000000
000752
000000
000756
000000
000762
000000
000766
000000
000772
000000
000776
000000

164:40

PAGE 8

.42
HALT
.+
HALT
.¥2
HALT
.+
HALT
.+
HALT
4
HALT
.+
HALT
4
HALT
.42
HALT
.42
HALT
.42
HALT
.+
HALT
.2
HALT
.42
HALT
.42
HALT
.2
HALT
.42
HALT

SEQ 0018
JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION

JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TC FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
;UNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
SUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
sEXAMINE STACK TO FIND CAUSE
SJUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
;EXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
SJEXAMINE STACK TO FIND CAUSE
JUNEXPECTED TRAP TO THIS LOCATION
JEXAMINE STACK TO FIND CAUSE

CZDHA-C MACY11 30A(1052)
28-AUG-78
CIDHAC.P11
15-MAY-78 10:02

34
345
36
347
348
349
350

354

355

356
357
358
359
360
361
362
363
364

14:40

PAGE 9

SEQ 0019

s STANDARD [NTERRUPT VECTORS

000024
000026
000030

000200

000024
017752
000340
016616

000200

000167

PFAIL

;POWER FAIL HANDLER

ERRORS

;ERROR HANDLER

TRPSRV

;GENERAL HANDLER DISPATCH SERVICE

340

;SERVICE AT LEVEL 7

340

.~200

sSERVICE AT LEVEL 7

340
JMP

JSERVICE AT LEVEL 7
START

;GO YO START OF

JDEFINITIONS FOR TRAP SUBROUTINF (CALLS
;POINTERS

TO SUBROUTINES CAN BE

;AT LOCATION 'TRPTAB"'

104400
104401

365
366
367
368
369
370

37
372
%;2

000046

375

000052

104402
104403
104404
104405
104406
104407
104410
000046
016464
000052
040000

SCOPE=TRAP+Y

TYPE=TRAP+Y
OCTASC=TRAP+Y

<0000

;SCOPE LOOP AND

ITERATION HANDLER

;TELETYPE OUTPUT ROUTINE
JOCTAL TO ASCII CONVERSION

S INPUT ASCII STRING
;STRING INPUT ERROR

SAVO5P=TRAP+Y

;SAVE RO~R5, PC

RESQOS5=TRAP+Y
LOG] CAL
=52

STARTING

INSTR=TRAP+Y
INSTER=TRAP+Y

PARAM=TRAP+Y

.746

FOUND

PROGRAM

SCOPET=TRAP+Y

;CONVERT

STRING TO OCTAL,

;RESTORE RO-R5

CHE.K LIMITS

JCHECK FOR FREEZE ON CURRENT DATA

CZDHA-C MACYT 30A(10;2)
23-AUG-78
CZDHAC.P11
15-MAY=78 10:02

ggg

14:40

001000

PAGE 10

.=1000

378
379
280
381
382

;PROGRAM INITIALIZATION
SLOCK OUT INTERRUPTS
*SET UP PROCESSOR STACK
*SET UP POWER FAIL VECTOR
:CLEAR PROGRAM FLAGS AND COUNTS

ggz

385
386
387
288
389
390
391
392
293
394
295
396
397

*TYPE TITLE MESSAGE

001000
001006
001012
001020
001024
001030
001034
001040
001044
001050
001054

001056

012767
012706
012737
005067
005067
005067
005067
005067
104401
005767
001001

000404

000340
021360
017752
016722
016656
016654
016644
016640
020116
016670

398

001060

032767

000001

400
401

001070
001074

012701
012702

000300
000302

399

402

403
404
405
406
407
408
409
410
411
412
413
614
415
416
417
418
419
420
421

422

423
426
425
426
427
428

429
431

SEQ 0020

001066

001100

001104
001106
001110
001112
001114
001120
001122
001126
001126
001130
001132
001134
001136
001137
001140
001142
001144
001146
001150

001152

001154
001155
001156
001164
001170
001174

001176

001445

012703

010211
005012
060301
060302
020127
001371
104403
020153
104405
000300
000770
017674
003
004
104403
020175
104405
000000
177776

176770
000024

176502

005167

VEC1:
VEC2:

000004

1$:

001000

.BYTE
BYTE

017652

007
010
016767
(005267
005767
001002

START:

016506
016502
016550

016506

BYTE
BYTE

016542

MOV
MOV
MOV
CLR
CLR
CLR
CLR
CLR
TYPE
TST
BNE

BIT

VEC2

#SWO00, SWR

BEQ

BEGIN

MOV

#4 RS

MOV
MOV

MOV
CLR
ADD
ADD
CMP
BNE
INSTR
MVECTOR
PARAM
300
770
DHRVE C
3
&
INSTR
MRE GAD
PARAM
0
177776

#300.R1
#302 R2

R2. (R1)
(R2)
R3.R1
R3.R2
R1 #1000
1%

7
10
MOV
INC
ST
BNE

;LOCK OUT INTERRUPTS
*SET UP PROCESSOR STACK
SSET UP POWER FAIL TRAP
“CLEAR TEST START FLAG
*CLEAR PASS COUNT
;CLEAR ERROR COUNT
:CLEAR ERROR FLAG
:CLEAR LAST ERROR PC
STYPE TITLE MESSAGE
sCHECK INITIALIZATION FLAG
“IF NOT 0, CHECK SWITCHES
“FOR REINITIALIZATION

;IF SW00=1, GET NEW VECTOR
JAND (SR

:RESTORE TRAPCATCHER
cIN FLOATING VECTOR AREA

: INPUT ADDRESS OF DEVICE VECTOR
*MESSAGE 'VECTOR ADDRESS-'"

;CONVERT STRING TO OCTAL
SLOW LIMIT
SHIGH
LIMmIT
*LOCATIONS TO BE FILLED
*NUMBER OF LOCATIONS
:LSB MASK
*INPUT ADDRESS OF DEVICE CSR
‘MESSAGE '‘CONTROL REGISTER ADDRESS-''
*CONVERT STRING TO OCTAL
SLOW LIMIT
SHIGH LIMIT

DHS’.R

COM

‘

#340,PS
#STACK, SP
#PF L .24
STFLG
PASCNT
ERRCNT
ERRFLG
ERRFLG
CMTITLE
INIFLG
VEC?

*LOCATIONS TO BE FILLED

DHSSR,DHSLR
DHSLR
INIFLG
BEGIN

INIFLG

:PROGRAM START

*NUMBER OF LOCATIONS
1LSB MASK
*SET UP ADDRESS OF SILO
*STATUS REGISTER HIGH BYTE
SIF INITIALIZATION FLAG
*15 CLEARED

SSET

CZDHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC.P11

14 :40

PAGE

SEQ 0021

;CHECK FOR PROGRAM START AT SELECTED ADDRESS
012767

000340
021360
000002

176566

BEGIN:

176346

MOV
MOV

BIT
BEQ
INSTR

#340,PS

#STACK,
SP

12U01.SUR

MTSTPC
PARAM

;LOCK OUT INTERRUPTS
JSET UP PROCESSOR STACK

JIF SWO1=1
;GET PC FOR PROGRAM START
JGET PC
JMESSAGE '‘TEST PC''
;CONVERT STRING TO OCTAL

17500

BYTE
BYTE

001274
016470

016462
020337
016416

016440

1%:

RETRN

1
1
BR

MOV
TSTY

BNF
2%:

(OM

TYPE

IMP

#T1,RETRN

STFLG

STFLG
MR
aRETRN

;JNORMAL START, TEST 1
;IF LOOPING, BYPASS TYPEOUT

JTYPE "R'" TO INDICATE START
;START

TESTING

CZDHA-C MACY11

CZDHAC.P11

30A(1052)
23-AUG-78
15-MAY-78 10:02

14 :40

PAGE 12

;DH11

SEQ 0022
SYSTEM CONTROL REGISTER ADDRESSING TEST

;VERIFY THAT DH11

;IF DH11

SYSTEM CONTROL REGISTER RESPONDS TO ADDRESSING

SYSTEM CONTROL REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP

:WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.

001274
001302
001310
001316
001324
001332

012767
012767
012767
012737
012737
005777

001336

000406

001340
001344

016705

001346
001352
001354
001362
001366

104000

012716
000002
012737
005037
104400

000340

016314

176474

016410
016376
000004
000006

016306

000004

MOV
MOV
MOV

#340,PS
#100, ICOUNT
#28 ESCAPE

;DISABLE ALL INTERRUPTS
;SET UP FOR 100 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST

MOV
TST

#3640, a6
aDHSCR

:ADDRESS DH11 SYSTEM CONTROL

;NO TRAP, REGISTER RESPONDS

MOV

DHSCR,RS

MOV

1%:

001354
000006
000006

T1:

#1S an

HLT

;REGISTER

*TO ADDRESSING

*REGISTER DID NOT RESPOND

)

2%:

MOV

#3$, (SP)

3%:

MOV

86, a4

RTI

CLR
SCOPE

SSET UP TIME OUT TRAP

“TIME OUT TRAP, DH11

SYSTEM CONTROL

*REGISTER DID NOT RESPOND

*SET UP TO RETURN FROM TRAP

*RETURN FROM TRAP

:RESTORE TRAP CATCHER
“CHECK FOR ITERATIONS, LOOP

;DH11 NEXT RECEIVED CHARACTER REGISTER ADDRESSING TEST
;VERIFY THAT DH11 NEXT RECEIVED CHARACTER REGISTER RESPONDS TO ADDRESSING
;IF DH11 NEXT RECEIVED CHARACTER REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP
;WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.
012767
012767
012767
012737
012737
005777

000340
000160

016222

176400
016314
016302
000004
000006

T2:

MOV

MOV
MOV
MOV
MOV

;DISABLE ALL INTERRUPTS

aDHNR(

;ADDRESS DH11

#100, 1 COUNT
#2% ESCAPE
#18 a4
#3460, 346

TST

000406

#340,PS

016705

016214

1%:

MOV
HLT

DHNRC RS
0

012716
000002
012737
005037
104400

001450

2%:

MOV

#3%,(SP)

104000

000006
000006

000004

3¢

RTI
MOV

;DH

NEXT RECEIVED CHARACTER

cREGISTER

;NO TRAP, REGISTER RESPONDS

:TO ADDRESSING

SREGISTER DID NOT RESPOND
;TIME OUT TRAP. DH11 NEXT RECEIVED (HARACTER

JREGISTER DID NOT RESPOND

JSET UP TO RETURN FROM TRAP

JRETURN FROM TRAP

6, 46

(LR
SCOPE

JSET UP FOR 100 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
JSET UP TIME OUT TRAP

JRESTORE TRAP CATCHER
;CHECK FOR ITERATIONS, LOOP

11 LINE PARAMETER REGISTER ADDRESSING TEST

JVERIFY

THAT DH

MOV
MOV
MOV

#340,PS
#100, ICOUNT
# S, ESCAPE

LINE PARAMETER REGISTER RESPONDS TO ADDRESSING

J1F DH
11 LINE PARAMETER REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP
:WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.

000340
000100
001536

001530

176304

016220
016206
000004

T3:

MOV

18 ,an¢

sDISABLE ALL INTERRUPTS
2SET UP FOR 100 ITERATIONS
SSET UP TO ESCAPE TO NEXT TEST

JSET UP TIME OUT TRAP

CZDHA~-C MACY11

CZDHAC.P11

30A(1052)

23-AUG-78

15-MAY-78 10:02

509
§]|§|)

001514
001522

012737
005777

512

001526

000406

001530
001534

016705
104000

016122

001536
001542
001544
001552
001556

012716
000002
012737
005037
104400

001544

513
516
515
516
517
518
519
520
gg}

000340
016130

000006
000006

14:40

000006

000004

sADDRESS 8?61;19!.?1%5 PARAME TER

:NO TRAP, REGISTER RESPONDS

1%:

MOV
HLT

DHLPR,RS
0

2%.

MOV
RTI
MOV
CLR
SCOPE

438, (SP)

3%:

012767
012767
012767
012737
012737
005777

535

001622

000406

537
538
539
50
541
542
543
SSzlSo

001624
001630

016705
104000

016030

001632
001636
001640
001646
001652

012716
000002
012737
005037
104400

001640

000340
000100
001632
001624
000340
016036

000006
000006

176210
016124
016112
000004
000006

000004

T4:

MOV
MOV
MOV
MOV
MOV
TST

#340,PS
#100, 1COUNT
#2$% ,ESCAPE
#1S N
#340,a46
aDHBA

;DISABLE ALL INTERRUPTS
JSET UP FOR 100 [TERATIONS
JSET UP TO ESCAPE TO NEXT TEST
;SET UP TIME OUT TRAP

sNO TRAP, REGISTER RESPONDS

1%:

MOV
HLT

DHBA RS
0

2%:

MOV
RTI
MOV
CLR
SCOPE

#3%,(SP)

3%:

546

sREGISTER

: TO ADDRESSING

JREGISTER DID NOT RESPOND
;TIME OUT TRAP, DH11 BUS ADDRESS
JREGISTER DID NOT RESPOND
sSET UP TO RETURN FROM TRAP
JRETURN FROM TRAP
JRESTORE TRAP CATCHER
;CHECK FOR ITERATIONS, LOOP

;VERIFY THAT DH11 BYTE COUNT REGISTER RESPONDS TO ADDRESSING
;1F DH11 BYTE COUNT REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP
;WILL OCCUR, AND AN ERROP MESSAGE WILL BE TYPED.

551
552
553
554

001654
001662
001670
001676

012767
012767
012767
012737

556

001712

005777

001716

000406

001720
001724

015705
104000

015736

001726
001732

012716
000002

001734

%63
564

w6, I
a6

;ADDRESS DH11 BUS ADDRESS

;DH11 BYTE COUNT REGISTER ADDRESSING TEST

547
548
g‘s'g

562

SRESTORE TRAP CATCHER
sCHECK FOR ITERATIONS, LOOP

;WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.
001560
001566
001574
001602
001610
001616

557
558
559
560
561

H6, NG
L)

:TO ADDRESSING
:REGISTER DID NOT RESPOND
;TIME OUT TRAP, DH
11 LINE PARAMETER
JREGISTER DID NOT RESPOND
sSET UP TO RETURN FROM TRAP
JRETURN FROM TRAP

;DH11 BUS ADDRESS REGISTER ADDRESSING TEST
;VERIFY THAT DH11 BUS ADDRESS REGISTER RESPONDS TO ADDRESSING
:1F DH11 BUS ADDRESS REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP

528
529
530
531
532
533

555

SEQ 0023
#340,a46
aDHLPR

ggg

536

MOV
TST

523
524
525

534

PAGE

001704

012737

000340
000100
001726
001720

000340

015744

176114
016030
016016
000004

715:

000006

MOV
MOV
MOV
MOV

#340,PS
#100, ICOUNT
#28 £ SCAPE
#13 o

sDISABLE ALL INTERRUPTS
JSET UP FOR 100 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
;SET UP TIME OUT TRAP

aDHB(

;ADDRESS DH11 BYTE COUNT

MOV

#3640, an6

B8R

1%:

MOV
HLT

DHBC RS
0

2%:

MOV
RTI

#2%,(SP)

Ter

SREGISTER
.'M) TRAP, REGISTER RESPONDS
TO ADDRESSING
REGISTER DID NOT RESPOND
TIME QUT TRAP, DH11 BYTE COUNT

:REGISTER DID NOT RESPOND

sSET UP TO RETURN FROM TRAP
:RETURN FROM TRAP

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

565
566
ggg

001734
001742
001746

012737
005037
104400

000006
000006

14:40

000004

3$:

569
570
571
g;g
001750
001756
001764
001772

012767
012767
012767
012737

ggg

002006

005777

581
582
583
584
585
586
587
S88
589

002012

000406

002014
002020

016705
104000

015646

002022
002026
002030
002036

012716
000002
012737

002030

gg?

002000

002042

012737

005037

104400

000340
000100
002022
002014

000340
015654

000006
000006

176020
015734
015722
000004

T6:

000006

603
604
605
606
607
608
609
610
611
612

g};’

000004

;DISABLE ALL INTERRUPTS
;SET UP FOR 100 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
:SET UP TIME OUT TRAP

TST

aDHB(R

;ADDRESS g?é}s?EEAK CONTROL

#3460, a6
3s

MOV
HLT

DHBCR,RS
0

2%:

MOV
RTI
MOV
CLR

#38,(SP)

3$:

SCOPE

N6, N6
W6

;NO TRAP, REGISTER RESPONDS
:TO ADDRESSING
;REGISTER DID NOT RESPOND
;TIME OUT TRAP, DH11 BREAK CONTROL
:REGISTER DID NOT RESPOND
:SET UP TO RETURN FROM TRAP
JRETURN FROM TRAP
:RESTORE TRAP CATCHER

;CHECK FOR ITERATIONS, LOOP

;BUS ACTIVE REGISTER ADDRESSING TEST
;VERIFY THAT BUS ACTIVE REGISTER RESPONDS TO ADDRESSING
;IF BUS ACTIVE REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP

;WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.

002044
002052
002060
002066

012767
012767
012767
012737

000340
000100
002116
002110

002074
002102

012737
005777

002106

0004606

002110
002114

016705
104000

015550

002116
002122
002124
002132

012716
000002
012737
005037

002124

002136

104400

000340
015556

000006
000006

175724
015640
015626
000004

17:

000006

000004

MOV
MOV
MOV
MOV

MOV
TST

#340,PS
#100, ICOUNT
#2$. ESCAPE
#18, anl

#340, a6
aDHBAR

1¢:

MOV
HLT

DHRAR RS
0

2%:

MOV
RT]
MOV
CLR

#3%,(SP)

3$:

SCOPE

615
616
617

H6, MG
b

;DISABLE ALL INTERRUPTS
:SET UP FOR 100 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
;SET UP TIME OUT TRAP

;ADDRESS BUS ACTIVE

;REGISTER
;:NO TRAP, REGISTER RESPONDS
:TO ADDRESSING
:REGISTER DID NOT RESPOND
;TIME OUT TRAP, BUS ACTIVE
;REGISTER DID NOT RESPOND
:SET UP TO RETURN FROM TRAP
:RETURN FROM TRAP

:RESTORE TRAP CATCHER

;CHECK FOR ITERATIONS, LOOP

:SILO STATUS REGISTER ADDRESSING TEST
JVERIFY THAT SILO STATUS REGISTER RESPONDS TO ADDRESSING
JJF SILO STATUS REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP

2}8
620

;RESTORE TRAP CATCHER
;CHECK FOR ITERATIONS, LOOP

#340,PS
#100, 1COUNT
#28 ,ESCAPE
S ar

ggg

601
602

46,44
w6

MOV
MOV
MOV
MOV

MOV

592
593
594

597
598
599
600

MOV
CLR
SCOPE

SEQ 0024

;DH11 BREAK CONTROL REGISTER ADDRESSING TEST
JVERIFY THAT DH11 BREAK CONTROL REGISTER RESPONDS TO ADDRESSING
;IF DH11 BREAK CONTROL REGISTER DOES NOT RESPOND, A BUSS ERROR TRAP
;WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.

574
575
576
577

578

PAGE 14

;WILL OCCUR, AND AN ERROR MESSAGE WILL BE TYPED.
002140

012767

000340

175630

T110:

MOV

#340,PS

;DISABLE ALL

INTERRUPTS

CZDHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC.P11

002146

012767
012767
012737
012737
005777

000100

14 140

015544
015532
000004
000006

PAGE 15

MOV
MOV
MOV

#100, ICOUNT
#2$ ,ESCAPE
M aré

sSET UP FOR 100 ITERATIONS
cSET UP TO ESCAPE TO NEXT TEST
sSET UP TIME OUT TRAP

TST

aDHSSR

;ADDRESS SILO STATUS

B8R

MOV

000406

SEQ 0025

#3460, a6

016705

015460

1$:

MOV
HLT

DHSSR,RS
0

012716
000002
012737
005037
104400

002220

2%:

MOV

#38,(SP)

3s:

MOV
CLR

#6, a6
av6

104000

000006
000006

000004

RT1]

SCOPE

sREGISTER
;NO TRAP, REGISTER RESPONDS
:TO ADDRESSING
JREGISTER DID NOT RESPOND
;TIME OUT TRAP, SILO STATUS
JREGISTER DID NOT RESPOND
sSET UP TO RETURN FROM TRAP
JRETURN FROM TRAP
JRESTORE TRAP CATCHER
;CHECK FOR ITERATIONS, LOOP

sMASTER CLEAR TEST
sSET SYSTEM CONTROL REGISTER TO 'CDATA'
s ISSUE MASTER CLEAR
;VERIFY THAT SYSTEM CONTPOL WAS CLEARED
002234
002242
002250
002256

012767
012767
012767
012777

000340
004000
002312
173777

175534
015450
015436
015366

002264
002272

052777

004000
015354

015360

017704

Ti:

MOV

#340.PS

MOV

#4000,
1 COUNT

MOV

#178777 ,aDHSCR

MOV

#18 _ESCAPE

BIS
MOV

#1T11,a8DHSCR
aDHSCR
R4

002276

005704

TST

Ré

002300
002302

001404
005005

BEQ
CLR

1%
RS

002304
002310
002312

016703

MOV
HLT
SCOPE

DHSCR,R3
5

2
1%:

;DISABLE ALL INTERRUPTS

;SET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
JSET SYSTEM CONTROL REGISTER
;10 173777

. ISSUE MASTER CLEAR

; (R4)=ACTUAL DATA IN

;SYSTEM CONTROL REGISTER
;VERIFY THAT SYSTEM CONTROL REGISTER

;WAS CLEARED

s (R5)=EXPECTED DATA IN

;SYSTEM CONTROL REGISTER,

:GET REGISTER ADDRESS

JMASTER CLEAR FAILED

;CHECK FOR ITERATIONS, LOOP

;sMASTER CLEAR TEST
;SET LINE PARAMETER REGISTER TO 'CDATA’
s ISSUE MASTER CLEAR
;VERIFY THAT LINE PARAMETER WAS CLEARED
012767
012767
012767
012777

000340
004000
002372
177777

052777
017704

004000
015300

175454

015370
015356
015312

T12:

MOV

#340,PS

MOV

#1$ ESCAPE

MOV

#4000,
T COUNT

;DISABLE ALL INTERRUPTS

MOV

aDHLPR R4

#81T11,3DHSCR

;SET UP FOR 4000 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
;SET LINE PARAMETER REGISTER
;10177777
;ISSUE MASTER CLEAR

005704

;LINE PARAMETER REGISTER
;VERIFY THAT LINE PARAMETER REGISTER

001404

BEQ

015300

MOV
8IS

#177777.aDHLPR

s (R4)=ACTUAL DATA IN

;WAS (LEARED

CZDHA-C MACY11 30A(1052)
23~AUG-78
P
CZDHAC.P11
15-MAY-78 10:02

677
678
679
680
23;

002362

005005

002364
002370
002372

016703
104005
104400

14:40

015266

1$:

683
684
685

002374

012767

000340

690

002410

012767

002452

693

694
695
696
697
698
699
700
701
702
;82

CLR

MOV
HLT
SCOPE

DHLPR,R3
5

:(RS)=EXPECTED DATA IN
;JLINE PARAMETER REGISTER, 0

:GET REGISTER ADDRESS
:MASTER CLEAR FAILED
JCHECK FOR ITERATIONS, LOOP

;VERIFY THAT BREAK CONTROL WAS CLEARED

688

235

SEQ 0026

:MASTER CLEAR TEST
;SET BREAK CONTROL REGISTER TO 'CDATA®
:ISSUE MASTER CLEAR

ggg

689

PAGE 16

002402

002416

012767

012777

002424

052777

002436

175374

004000

015310

177777

015242

015276

MOV

#340,PS

MOV

#18 ESCAPE

MOV

#177777 .9DHBCR
#81T11,80HSCR

005704

TST

Ré

002440
002442

0014064
005005

BEQ
CLR

13
RS

002444
002450
002452

016703
104005
104400

MOV
HLT
SCOPE

DHBCR,R3
S

017704

015230

015220

#4000, 1COUNT

BiS

002432

004000

T13:

MOV

015216

1%:

705

aDHBCR, R4

;DISABLE ALL INTERRUPTS

:SET UP FOR 4000 ITERATIONS

:SET UP TO ESCAPE TO NEXT TEST

;§5719§;9§ fONTROL REGISTER
:ISSUE MASTER CLEAR

;(RG)=ACTUAL DATA IN
:BREAK CONTROL REGISTER
;VERIFY THAT BREAK CONTROL REGISTER
;WAS CLEARED

. (RS)=EXPECTED DATA IN
;BREAK CONTROL REGISTER, 0
:GET REGISTER ADDRESS
:MASTER CLEAR FAILED
;CHECK FOR ITERATIONS., LOOP

:MASTER CLEAR TEST

706

JSET SILO STATUS REGISTER TO °*CDATA®

;83

JVERIFY THAT SILO STATUS WAS CLEARED

707

:ISSUE MASTER CLEAR

710

002454

012767

71¢

002470

012767

711

;}2
715
716
717

002462

002476

000340

012767

004000

012777

100077

002536

015216

015140

002504
002512

052777
017704

004000
015152

718

002516

042704

077700

721

002524

001404

719
720

722

723
724

725

;59
728
729
730
731
732

002522

005704

002526

005005

002530

016703

002536

106400

00253%

104005

175314

015230

T14:

MOV

#340 PS

;DISABLE ALL

#18 ESCAPE

:SET UP TO ESCAPE TO NEXT TEST

BIS
MOV

#8IT11,aDHSCR
aDHSSR R4

BIC

#77700,R4

:ISSUE MASTER CLEAR
; (R4)=ACTUAL DATA IN
:SILO STATUS REGISTER
;CLEAR UNWANTED BITS
;VERIFY THAT SILO STATUS REGISTER

BEQ

MOV

#4000, TCOUNT

MOV

#100077 ,aDHSSR

MOV

015164

TST

015134

1%:

CLR

MOV

DHSSR,R3

HLT

SCOPE

INTERRUPTS

:SET UP FOR 4000 ITERATIONS

:¥8T186597STATUS REGISTER

;WAS CLEARED
:(RS)=EXPECTED DATA IN

:SILO STATUS REGISTER, 0
:GET REGISTER ADDRESS

;MASTER CLEAR FAILED

;CHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
JSET LINE SELECT BIT O IN SYSTEM CONTROL REGISTER
SVERIFY THAT LINE SELECT BIT O WAS SET
JCLEAR LI SELECT BIT 0
;VERITY THAT LINE SELECT BIT O WAS CLEARED

CZOHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC P11

002540

0
0

7
1

14:40

PAGE 17

SEQ 0027
#340.PS

T15:

:gxroo,(ns)

;DISABLE ALL INTERRUPTS
;SET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
sPUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
sSET LINE SELECT ZIT 0
;VERIFY THAT LINE SELECT BIT O WAS SET

#31T00,RS

;(R5)= EXPECTED VALUE

(R3) ,R4

; (R4)=ACTUAL DATA IN

#5000, 1COUNT

#28 ESCAPE

DHSERR3

#1700, (R3)

011304
104001

042713
001403
005005

:SYSTEM CONTROL REGISTER
;SYSTEM CONTROL REGISTER

000001

#B1T00, (R3)

BIC
BEQ
CLR

’$
R5

011304

MoV

(R3) ,R4

104001

HLT

104400

2%:

sIN SYSTEM CONTROL REGISTER
sLINE SELECT BIT O

sWRITE/READ ERROR

sCLEAR LINE SELECT BIT O
s (RS)=EXPECTED DATA IN

sSYSTEM CONTROL REGISTER, 0
s (R4)=ACTUAL DATA IN

sSYSTEM CONTROL REGISTER
;SYSTEM CONTROL REGISTER

JWRITE/READ ERROR

SCOPE

;CHECK FOR ITERATIONS, LOOP

JSYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
;SET LINE SELECT BIT 1 IN SYSTEM CONTROL REGISTER
;VERIFY THAT LINE SELECT BIT 1 WAS SET
;CLEAR LINE SELECT BIT 1

;VERITY THAT LINE SELECT BIT 1 WAS CLEARED
012767
012767
012767

000340

MOV
MOV

#340,PS

#4000, 1COUNT

#2$ ESCAPE

DHSCR.R3
#BIT07, (R3)
121ro1.<n3)

012705

#81T01,RS

;DISABLE ALL INTERRUPTS

JSET UP FOR 4000 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
;PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
;SET LINE SELECT BIT 1
;VERIFY THAT LINE SELECT BIT 1 WAS SET

;(R5)= EXPECTED VALUE
¢IN SYSTEM CONTROL REGISTER

sLINE SELECT 8I7 1

011304

MOV

(R3) ,R4

104001

HLT

Blc
BEQ
CLR

#1701, (R3)
2%

;(RS)=EXPECTED DATA IN

011304

MOV

(R3) ,R4

104001

HLT

: (R4)=ACTUAL DATA IN
;SYSTEM CONTROL REGISTER

042713
001403
005005

104400

000002

1%:

2%:

SCOPE
JSYSTEM (ONTROL

: (R4)=ACTUAL DATA IN

;SYSTEM CONTROL REGISTER
sSYSTEM CONTROL REGISTER

JWRITE/READ ERROR
;CLEAR LINE SELECT BIT 1

;SYSTEM CONTROL REGISTER, 0

;SYSTEM CONTROL REGISTER
SWRITE/READ ERROR
;CHECK FOR ITERATIONS, LOOP
REGISTER WRITE/READ

TEST

(NORMAL MODE)

(ZDHA-C MACY 11 30A(1052)
23-AUG-78
15-MAY~-78 10:02
CZDHAC.P11

14:40

PAGE 18

SEQ 0028

;SET LINE SELECT BIT 2 IN SYSTEM CONTROL REGISTER
*VERIFY THAT LINE SELECT BIT 2 WAS SET

*CLEAR LINE SELECT BIT 2
SVERITY THAT LINE SELECT BIT 2 WAS CLEARED

002752
002754

012767
012767
012767
016703
012713
022713
001404
012705

002760

000340
004000
003000
014710
000004
000004

175054

014770
014756

T17:

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV

#2S ESCAPE
DHSCR,R3

*SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3

121T02.(R3)

SVERIFY THAT LINE SELECT BIT 2 WAS SET

MOV
MOV

ggg

000004

#4000, 1 COUNT
#BIT02, (R3)

“SET UP FOR 4000 ITERATIONS

“SET LINE SELECT BIT 2

MOV

#BIT02,RS

011304

MOV

(R3) .Ré4

002762

104001

HLT

002764
002770
002772

042713
001403
005005

gég

§§1r02.<ns>

CLR

; (RS)=EXPECTED DATA IN

002774

011304

MOV

(R3) .R4

*(RG)=ACTUAL DATA IN

002776

104001

HLT

J03000

104400

000004

1%:

’$:

SCOPE

:(RS)= EXPECTED VALUE

*IN SYSTEM CONTROL REGISTER
‘LINE SELECT BIT 2

*(RG)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER

*WRITE/READ ERROR

‘CLEAR LINE SELECT BIT 2

*SYSTEM CONTROL REGISTER, O

'SYSTEM CONTROL REGISTER

*SYSTEM CONTROL REGISTER
‘WRITE/READ ERROR
*CHECK FOR ITFRATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST

(NOR-AL MODE)

*SET LINE SELECT BIT 3 IN SYSTEM CONTROL REGISTER
*VERIFY THAT LINE SELECT BIT 3 WAS SET
*CLEAR LINE SELECT BIT 3
*VERITY THAT LINE SELECT BIT 3 WAS CLEARED
012767
012767
012767
016703
012713
022713
001404
012705

000340
004000
003066
014622
000010
000010

174766

014702
014670

T20:

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV

#2%ESCAPE
DHSCR,R3

*SET UP TO ESCAPE TO NEXT TEST
*PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3

ggg

1§xros.<ns>

SVERIFY THAT LINE SELECT BIT 3 WAS SET

MOV

000010

#4000, 1COUNT

#1705, (R3)

*SET UP FOR 4000 ITERATIONS

*SET LINE SELECT BIT 3

MOV

#31T03,RS

011304

MOV

(R3) R4

104001

HLT

gég

521r03.<93>

CLR

; (RS)=EXPECTED DATA IN
*(R&)=ACTUAL DATA IN

042713
001403
005005

000010

S ¥

003062

011304

MOV

(R3) R4

003004

104001

HLT

;(RS)= EXPECTED VALUE

*IN SYSTEM CONTROL REGISTER
*LINE SELECT BIT 3
*(R4)=ACTUAL DATATM IN

*SYSTEM CONTROL REGISTER
"SYSTEM CONTROL REGISTER

‘WRITE/READ ERROR

*CLEAR LINE SELECT BIT 3

*SYSTEM CONTROL REGISTER, 0
*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

846

003066

14:40

104400

2%:

PAGE 19

SEQ 0029
;sWRITE/READ ERROR

SCOPE

cCHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
;SET MEMORY EXTENSION BIT O IN SYSTEM CONTROL REGISTER
;VERIFY THAT MEMORY EXTENSION BIT 0 WAS SET

;CLEAR MEMORY EXTENSION BIT 0
;VERITY THAT MEMORY EXTENSION BIT O WAS CLEARED
854
855
856
857
858
859

003070
003076
003104
003112
003116
003122

012767
012767
012767
016703
012713
022713

000340
004000
003154
(014534
000020
000020

861

003130

012705

000020

864

003134

011304

MOV

(R3) R4

866

003136

104001

HLT

868
869
870

003140
003144
003146

042713
001403
005005

8IC
BEQ
CLR

" 1704, (RR)

sIN SYSTEM CONTROL REGISTER
sMEMORY EXTENSION BIT 0
; (R6)=ACTUAL DATA IN
cSYSTEM CONTROL REGISTER
;SYSTEM CONTROL REGISTER
;WRITE/READ ERROR
;CLEAR MEMORY EXTENSION BIT 0

s (RS)=EXPECTED DATA IN

872

003150

011304

MOV

(R 3) R4

; (R4)=ACTUAL DATA IN

874

002152

104001

HLT

876

003154

104400

000020

174700

014614

T121:

014602

1%:

°2%:

MOV
MOV
MOV
MCV
MOV
e
BEQ
MOV

#340,PS

#4000, 1 COUNT

#23$ ESCAPE

DHSCR,R3
#1704, (R3)
#3 1704, (R3)
1%
#8 I1TO4 RS

DISABLE ALL INTERRUPTS
;SET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
;PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
;SET MEMORY EXTENSION BIT 0
;VERIFY THAT MEMORY EXTENSION BIT O WAS SET

:(RS)= EXPECTED VALUE

;SYSTEM CONTROL REGISTER,

;SYSTEM CONTROL REGISTER
JSYSTEM CONTROL REGISTER

JWRITE/READ ERROR

SCOPE

JCHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
;SET MEMORY EXTENSION BIT 1 IN SYSTEM CONTROL REGISTER
;VERIFY THAT MEMORY EXTENSION BIT 1 WAS SET
;CLEAR MEMORY EXTENSION BIT 1
SVERITY THAT MEMORY EXTENSION BIT 1 WAS CLEARED
884
885
88¢
887
888
889
890
891

003156
003164
003172
003200
003204
003210
003214
003216

012767
012767
012767
016703
012713
022713
001404
012705

000340
004000
003242
014446
000040
000040
000040

#340,PS

;DISABLE ALL INTERRUPTS

#2$ ESCAPE

;SET UP TO ESCAPE TO NEXT TEST
;PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
sSET MEMORY EXTENSION BIT 1
;VERIFY THAT MEMORY EXTENSION BIT 1 WAS SET

MOV
MOV
MOV
MOV
MOV
cMP
BEQ
MOV

1%
3 ITO5.RS

#4000, 1COUNT
DHSCR.R3

#1705, (R3)

#B1T105, (R3)

003222

011334

MOV

(R 3) R4

003224

104001

HLT

898
899
900

003226
003232
003234

042713
001403
005005

BIC
BEQ
(LR

1705, (R3)

000040

;SET UP FOR 4000 ITERATIONS

:(RS5)= EXPECTED VALUE

sIN SYSTEM CONTROL REGISTER
;MEMORY EXTENSION BIT 1
s (R4)=ACTUAL DATA

sSYSTEM (ONTROL REGISTER

sSYSTEM CONTROL REGISTER
;WRITE/READ ERROR
;CLEAR MEMORY EXTENSION BIT 1
J(RS)=EXPECTED DATA IN

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC .P11
15-MAY=78 10:02
901
902
903
904
905
389

14:40

011304

MOV

(R3) ,R4

003240

104001

HLT

003242

104400

28:

003244

012767

000340

916
917
918

003260
003266
003272

012767
016703
012713

003330
014360
000300

003302
003304

001404
012705

003310

931
932
933
93
935
ggg

SCHECK FOR ITERATIONS, LOOP

SVERITY THAT RECEIVER INTERRUPT ENABLE WAS CLEARED

914

930

MOV

#340,PS

MOV
MOV
MOV

#28 ESCAPE
DHSCR,R3
#MIT06. (R3)

BEQ
MOV

18
#BIT06,RS

011304

MOV

(R3) ,R4

003312

104001

HLT

003314
003320

042713
001403

BIC
BEQ

#B1T06, (R3)
2%

003252

012767

003276

022713

003322

004000

174524

014440

T123:

014426

000100

MOV
CMP

000100

000°0C

1%:

005C0S

CLR

#4000, 1COUNT
#MBIT06. (R3)

003324

011304

MOV

(R3) ,R4

003326

104001

HLT

003330

104400

2%:

SCOPE

:DISABLE ALL

INTERRUPTS

“SET UP FOR 4000 ITERATIONS

:SET UP TO ESCAPE TO NEXT TEST
:PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
*SET RECEIVER INTERRUPT ENABLE

*VERIFY THAT RECEIVER INTERRUPT ENABLE WAS SET

:(RS)= EXPECTED VALUE
*IN SYSTEM CONTROL REGISTER
*RECEIVER INTERRUPT ENABLE
S (RG)=ACTUAL DATA IN
*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER
‘WRITE/READ [ RROR
:CLEAR RECEIVER INTERRUPT ENABLE

; (RS)=EXPECTED DATA IN
*SYSTEM CONTROL REGISTER, 0
:(R&)=ACTUAL DATA IN
SSYSTEM CONTROL REGISTER
SSYSTEM CONTROL REGISTER
*WRI1E/READ ERROR
"CHECK FOR ITERATIONS, LOOP

938
939
340

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
*SET MAINTENANCE MODE IN SYSTEM CONTROL REGISTER
SVERIFY THAT MAINTENANCE MODE WAS SET

gz%

SVERITY THAT MAINTENANCE MODE WAS CLEARED

9,1

944

%6
9%7

*CLEAR MAINTENANCE MODE

003332

012767

000340

003346
003354

012767
016703

003416
014272

003340

012713

003370

001404

003364

951
952
953
954

003372

956

012767

003360

950

SVERIFY THAT RECEIVER INTERRUPT ENABLE WAS SET
{CLEAR RECEIVER INTERRUPT ENABLE

g1%

920
921
922
923
924
925
926
927
928
929

SCOPE

;SYSTEM CONTROL REGISTER,
:(RG)=ACTUAL DATA IN
“SYSTEM CONTROL REGISTER
“SYSTEM CONTROL REGISTER
:WRITE/READ ERROR

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
:SET RECEIVER INTFRRUPT ENABLE IN SYSTEM CONTROL REGISTER

910
911

919

SEQ 0030

003236

908
909

915

PAGE 20

003376
00300

022713

012705
011304
.

104001

00400

001000
001000

001000

174436

014352
014340

T124:

MOV

#340 ,PS

:DISABLE ALL

MOV
MOV

#28 ESCAPE
DHSCR,R3

$PUT ADDRESS OF

#8:709. (R3)

*VERIFY THAT MAINTENANCE MODE WAS SET

MOV

#B]T09,RS

MOV

(R3) R4

:(RS)= EXPECTED VALUE
SIN SYSTEM CONTROL REGISTER
*MAINTENANCE MODE
; (R4)=ACTUAL DATA IN

MOV

#4000, TCOUNT

MOV

#MIT09, (R3)

8EOQ

cTMP

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

*SET UP TO ESCAPE

TO NEXT

TEST

SYSTEM CONTROL REGISTER

*SET MAINTENANCE MODE

;SYSTEM

CONTROL

JSYSTEM CONTROL REGISTER

IN R3

CZDHA-C MACYT? J0A(1052)
23-AUG-78
78
CZDHAC.P11
15-MAY-78
10:02

14:40

PAGE 21

1$:

8IC
BEQ

#31709, (R3)
2%

SEQ 0031

958
959
960

003402
003406
003410

005005

962

003412

011304

MOV

(R3) ,R4

964

003414

104001

HLT

00341¢

104400

042713
001403

001000

CLR

2%:

JWRITE/READ ERROR

;CLEAR MAINTENANCE MODE

s (RS)=EXPECTED DATA IN
;SYSTEM CONTROL REGISTER, O
*(R4)=ACTUAL DATA IN
;SYSTEM CONTROL REGISTER
;SYSTEM CONTROL REGISTER
sWRITE/READ ERROR

SCOPE

sCHECK FOR ITERATIONS, LOOP

JSYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
sSET SILO OVERFLOW INTERRUPT ENABLE IN SYSTEM CONTROL REGISTER
;VERIFY THAT SILO OVERFLOW INTERRUPT ENABLE WAS SET
sCLEAR SILO OVERFLOW INTERRUPT ENABLE
;VERITY THAT SILO OVERFLOW INTERRUPT ENABLE WAS CLEARED
012767

000340

MOV

#340,PS

;DISABLE ALL INTERRUPTS

012767
016703

003504
014204

MOV
MOV

#28 ESCAPE
DHSCR,R3

cSET UP TO ESCAPE TO NEXT TEST
;PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3

010000

g‘E'U;

:gIT‘IZ.(RS)

;VERIFY THAT SILO OVERFLOW INTERRUPT ENABLE WAS

010000

MOV

#81T12,RS

011304

MOV

(R3) ,R4

;(R5)= EXPECTED VALUE
;IN SYSTEM CONTROL REGISTER
;SILO OVERFLOW INTERRUPT ENABLE
s (R4)=ACTUAL DATA IN

HLT

sSYSTEM CONTROL REGISTER

BI(

#BIT12,(R3)

sCLEAR SILO OVERFLOW INTERRUPT ENABLE

CLR

; (RS)=EXPECTED DATA IN

012767
012713

8(2)?22){3‘
012705

004000

174350

(14264

T125:

014252

010000

MOV
MOV

#4000, 1 COUNT

#1712, (R3)

003466

104001

988
289
990

003470
003474
003476

042713

001403

992

003500

011304

MOV

(R3) R4

99¢

03502

104001

HLT

996

003504

104400

010000

1%:

005005

2%:

BEQ

SCOPE

sSET SILO OVERFLOW INTERRUPT ENABLE

cSYSTEM CONTROL REGISTER
;WRITE/READ ERROR

;SYSTEM CONTROL REGISTER, 0
; (R4)=ACTUAL DATA IN

;SYSTEM CONTROL REGISTER
sSYSTEM CONTROL REGISTER
SJWRITE/READ ERROR

;CHECK FOR ITERATIONS, LOOP

JSYSTEM CONTROL REGISTER WRITE/READ TEST

(NORMAL MODE)

;SET TRANSMITTER INTERRUPT ENABLE IN SYSTEM (CONTROL REGISTER
;VERIFY THAT TRANSMITTER INTERRUPT ENABLE WAS SET

;CLEAR TRANSMITTER INTERRUPT ENABLE

S
&

JVERITY THAT

012767

004000

012713

020000

£>

[0,

88%?2(1)2
Ml

000340

012767
012767
016703

b oy

elole

CESEERESERN

986

;SET UP FOR 4000 ITERATIONS

012705

003572
014116
020000
020000

174262

014176
014164

Tco:

TRANSMITTER INTERRUPT ENABLE WAS CLEARED

MOV

#340 PS

;DISABLE ALL INTERRUPTS

MOV
MOV

#2$ ,ESCAPE
DHSCR R3

;SET UP TO ESCAPE TO NEXT TEST
;PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3

MOV

#4500, 1COUNT

MOV

#1715, (R3)

MOV

4C!T73,RS

g;lg

:’21113.(!?3)

;SET UP FOR 4000 ITERATIONS

;SET TRANSMITTER INTERRUPT ENABLE

;VERIFY THAT TRANSMITTER INTERRUPT ENABLE WAS SE
2 (RS)= EXPECTED VALUE
JIN SYSTEM CONTROL REGISTER

CZOHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02
1013
1014
1015
1016

1017
1018
1019
1020
1021
1022
1023
1024
1025
}859

14:40

011304

MOV

(R3) R4

003554

104001

HLT

003556
003562

0462713
001403

BIC
BEQ

#BIT13, (R3)
2$

020000

1%:

003564

005005

CLR

003566

011304

MOV

(R3) ,R4

003570

104001

HLT

003572

104400

003574

012767

000340

1036
1037

003610
003616

012767
016703

003660
014030

003602

003622

012767

012713

1039
1060
10641

003626
003632
003634

022713
001404
012705

1043
1044

003640

1046

003642

1047
1048
1049

1050
1051
1052
1053
1054
1055
}829

003644
003650

004000

174174

014110

T127:

014076

100000

1062

1063

1064

1065
1066
}067

068

; (RS)=EXPECTED DATA IN
*SYSTEM CONTROL REGISTER, 0
1 (R4)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER

*SYSTEM CONTROL REGISTER
*WRITE/FEAD ERROR
*CHECK FOR ITERATIONS, LOOP

MOV

#340,PS

:DISABLE ALL

MOV
MOV

#28 ESCAPE
DHSCR,R3

SSET UP TO ESCAPE TO NEXT TEST
:PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3

MOV

100000

#4000, 1COUNT

#1715, (R3)

CTMP
BEQ
MOV

MIT15°(R3)
18
#MIT15 RS

011304

MOV

(R3) ,R4

104001

BIC
BEQ
CLR

#IT15, (R3)
2$

100000

003652

042713
001403
005005

003654

011304

MOV

(R3) ,R4

003656

104001

HLT

003660

106400

100000

2%:

1058
}823
1061

*WRITE/READ ERROR
:CLEAR TRANSMITTER INTERRUPT ENABLE

*VERITY THAT TRANSMITTER DONE WAS CLEARED

1034

1045

SCOPE

*SYSTEM CONTROL REGISTER

*CLEAR TRANSMITTER DONE

}8§§

1042

: TRANSMITTER INTERRUPT ENABLE
1 (R4)=ACTUAL DATA IN
*SYSTEM CONTROL REGISTER

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
*SET TRANSMITTER DONE IN SYSTEM CONTROL REGISTER
:VERIFY THAT TRANSMITTER DONE WAS SET

1031

1038

SEQ 0032

003552

1028
1029
1030

1035

PAGE 22

SCOPE

INTERRUPTS

“SET UP FOR 4000 ITERATIONS

*SET TRANSMITTER DONE

SVEFIFY THAT TRANSMITTER DONE WAS SET

:(R5)= EXPECTED VALUE
SIN SYSTEM CONTROL REGISTER
STRANSMITTER DONE

$(RG)=ACTUAL DATA IN

*SYSTEM CONTROL REGISTER

*WRITE/READ ERROR
:CLEAR TRANSMITTER DONE

: (RS)=EXPECTED DATA IN
*SYSTEM CONTROL REGISTER, 0
< (RG)=ACTUAL DATA IN
*SYSTEM CONTROL REGISTER
“SYSTEM CONTROL REGISTER
‘WRITE/READ ERROR
TCHECK FOR ITERATIONS, LOOP

:SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
:VERIFY THAT CHARACTER AVAILABLE IS READ ONLY IN NORMAL MODE
003662

012767

003676

012767

00367C

003704

003712
003716

000340

174106

012767

004000

014022

012777

000200

013740

005777
001406

013734

003734

014010

7130:

MOV

#350,PS

MOV

#4000, ICOUNT

MOV

#B1707.,3DHSCR

ST
BEQ

ac 4SCR
1%

MOV

#1$ _ESCAPE

:DISABLE ALL

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

“SET UP TO ESCAPE TO NEXT TEST

CATTEMPT TO WRITE

*CHARACTER AVAILABLE IN
“SYSTEM CONTROL REGISTER
*WAS CHARACTER AVAJLABLE SET

CZDHA-C MACY11 30A(105¢2)
23-AUG-78
CZDHAC. P11
15-MAY-78 10:02

003720

005005

003722

017704

003725
003732

016703

005734

104400

104001

14:40

PAGE 23

SEQ 0033

CLR

s (R5)=EXPECTED DATA

013724

MOV

@DHSCR,R4

s (R4)=ACTUAL DATA IN SYSTEM

013720

MOV
HLT

DHSCR,R3

1%:

SCOPE

;IN SYSTEM CONTROL REGISTER, O
;CONTROL REGISTER

;ADDRESS OF SYSTEM CONTROL REGISTEK

;SYSTEM CONTROL REGISTER

JWRITE/READ ERROR

003736
003744
003752
003760

012767
012767
012767
012777

000340
004000
004010
000400

003766
003772
003774

005777
001406
005005

013660

003776

017704

004002
004006

016703

004010

104400

104001

131:

TST

) =D
)
e
D
d
h e
d e

)

D e

#1$,ESCAPE

:SET UP TO ESCAPE

#8]1 708, aDHSCR
?guscn

“SET UP FOR 4000 ITERATIONS

*ATTEMPT TO WRITE

TO NEXT TEST

*CLEAR NON EXISTANT MEMORY [N
"SYSTEM CONTROL REGISTER
*WAS CLEAR

NON EXISTANT MEMORY SET

013650

MOV

aDHSCR, R4

*(R4)=ACTUAL DATA IN SYSTEM

013644

MOV

DHS R,R3

HUT

1%:

SCOPE

“IN SYSTEM CONTROL REGISTER. O
*CONTROL REGISTER

*ADDRESS OF SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER

JWRITE/READ ERROR

JSYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
JVERIFY THAT NON EXISTANT MEMORY IS READ ONLY IN NORMAL MODE

012767
012767
012767

173756
013672
013660
013610

012777

132:

) e

D e e = ) e d b b ) —

e S
O
S O
N
B WN=2O0 ONO
NS WN=O

;DISABLE ALL INTERRUPTS

; (RS)=EXPECTED DATA

005777
001406
005005

013604

017704

016703
104001

MOV
MOV
MOV
MOV
TST

#340,P5

:DISABLE ALL

#1S ESCAPE

:SET UP TO ESCAPE

#4000, 1COUNT

#M1T10,3DHSCR
?gHSCR

INTERRUPTS

*SET UP FOR 4000 ITERATIONS
TO NEXT

CATTEMPT TO WRITE
JNON EXISTANT MEMORY IN
sSYSTEM CONTROL REGISTER
sWAS NON EXISTANT MEMORY

TEST

SET

BEQ
(LR

; (RS)=EXPECTED DATA

01357¢

MOV

aDHSCR R4

. (R4)=ACTUAL DATA [N SYSTEM

013570

MOV

DHSCR,R3

104400

HLT

1%:

SCOPE

;IN SYSTEM CONTROL REGISTER, O
;CONTROL REGISTER
;ADDRESS OF SYSTEM CONTROL REGISTER
;SYSTEM CONTROL REGISTER

JWRITE/READ ERROR

JSYSTEM CONTROL REGISTER WRITE/READ

D
) ed
d
d
—

#340,PS

#4000, 1COUNT

— e d D e D med D

[AN1,81,¥1, ¥, ¥ P

MOV
MOV
MOV
MOV

8EQ
CLR

)

e e D e ) e

B8IRFRICSS EERFRFEREF &

) D e ed e D D d D d )

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
NON EXISTANT MEMORY IS READ ONLY IN NORMAL MODE
;VERIFY THAT CLEAR

TEST

(NORMAL MODE)

JVERIFY THAT MASTER CLEAR IS READ ONLY [N NORMAL MODE

000340
004000
004140
004000

MoV
MOV
MOV
MOV

#340,PS

;DISABLE ALL

INTLRRUPTS

#4000, 1COUNT

*SET UP FOR 4000 ITERATIONS

#1717, 8DHSCR

TATTEMPT TO WRITE

43¢ ESCAPF

*SET UP TO ESCAPE

TO NEXT

TEST

PAGE 24

SEQ 0034

[V,]

14:40

—

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P1N
15-MAY-78 10:02
1126
1127

1128
1129

1130
1131
1132
1133
1134

1135
;}%9

004116

005777

004122
004724

001406
005005

004126

017704

004132
004736

016703
104001

004140

104400

TST

aDHSCR

JMASTER CLEAR IN
;SYSTEM CONTROL REGISTER
;WAS MASTER CLEAR SET

BEQ
CLR

1%
RS

s (R5)=EXPECTED DATA

013520

MOV

aDHSCR, R4

0135

MOV
HLT

DHSCR,R3
1

213530

1%:

1138
}}Zg
1141

1162

1143

1144

1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160

004142

004150

004156

012767

012767
012767

000340

173626

004000

013542

013460

(%214

004164

012777

040000

004172
004176
004200

005777
001406
005005

013454

004202

017704

004206
004212

016703
104001

004274

104400

34:

(13530

MOV

013444

MOV

aDHSCR, RS

013440

MOV
HLT

DHSCR,R3
1

1%:

;WRITE/READ ERROR

;DISABLE ALL

INTERRUPTS

sSET UP FOR 4000 ITERATIONS
JSET UP TO ESCAPE

TO NEXT TEST

SATTEMPT TO WRITE

;SILO OVERFLOW IN
;SYSTEM CONTROL REGISTER
;WAS SILO OVERFLOW SET

; (R5)=EXPECTED DATA
sIN SYSTEM CONTROL REGISTER, O
;(RG)=ACTUAL DATS IN SYSTEM
;CONTROL REGISTER
;ADDRESS OF SYSTEM CONTROL REGISTER
sSYSTEM (ONTROL REGISTER

;WRITE/READ ERROR
SCOPE
JSYSTEM CONTROL REGISTER WRITE/READ TEST (MAINTENANCE MODE)
;SET MAINTENANCE MODE
sSET CHARACTER AVAILABIE IN SYSTEM CONTROL REGISTER
;VERIFY THAT CHARACTER AVAILABLE WAS SET
;CLEAR MAINTENANCE MODE

JVERIFY THAT CHARACTER AVAILABLE CANNOT BE CLEARED
;SET MAINTENANCE MODE
;CLEAR CHARACTER AVAILABLE

;VERIFY THAT CHARACTER AVAILABLE WAS CLEARED

012767

000340

1169
1170

004232
004240

012767
016703

004344
013406

1176
1177
1178
1179
1180

#1% ESCAPE

aDHSCR
1%
RS

004216

1174
1175

#4000, 1 COUNT

TST
BEQ
CLR

1167

1173

#340,PS

#B1T14 ,aDHSCR

}}22

1172

MOV

1162
1163
1164

1171

;SYSTEM CONTROL REGISTER

;SYSTEM CONTROL REGISTER WRITE/READ TEST (NORMAL MODE)
;VERIFY THAT SILO OVERFLOW IS READ ONLY IN NORMAL MODE

1161

1168

SCOPE

;IN SYSTEM CONTROL REGI. ER, O
s (R4)=ACTUAL DATA IN SYSTEM
;CONTROL REGISTER
;ADDRESS OF SYSTEM CONTROL REGISTER

004224

004244

004250

004254

012767
012713

052713

022713

004260
004262

001404
012705

004266

011304

004000
001000

000200

001200
001200

173552

013466
013454

T135:

MOV

#340,PS

;DISABLE ALL

#38 ESCAPE
DHSCR,R3

;SET UP TO ESCAPF TO NEXT TEST
;PUT ADDRESS OF SYSTEM CONTROL REGISTER

MOV

#4000, 1COUNT

MOV

#1709, (R3)

(MP

#3;T709+81707, (R3)

MOV
MOV

8IS

#1107, (R3)

INTERRUPTS

;SE1 P FOR 4000 ITERATIONS

sSET MAINTENANCE MODE

IN R3

;SET CHARACTER AVAILABLE

;VERIFY THAT CHARACTER AVAILABLE

BEQ
MOv

JAND MAINTENANCE MODE ARE SET
1%
#ITC9+BITO7
RS ; (RS)-EXPECTED DATA
sIN SYSTEM CONTROL REGISTER

MOV

(") R4

JMAINTENANCE MODE AND CHARACTER AVAILABLC
; (R4)=ACTUAL DATA IN
;SYSTEM CONTROL REGISTER

W)
—

0000 00

004270

104001

004272
004276
004302
004 306
004310

042713
042713
022713

001403
012705

004314

104001

14:40

PAGE 25

SEQ 0035

HLT

BIC

#BIT109, (R3)

#81707,(R3)
#81707, (R3)

000200

MOV

#81T07,RS

HLT

BIS
BIC
P

#31709, (R3)
#81707, (R3)
#1709, (R3)

BEQ
MOV

SMODE TO BE SET

#BIT09.RS

s (R5)=EXPECTED DATA IN

011304

MOV

(R3) ,R4

: (RG)=ACTUAL DATA IN

102001

HLT

d
D

d oD

D e

052713
042713
022713

2%:

001000

3%:

104400

D e

WWR)
—

d e

— e

001404
012705

001000
000200
001000

WSO

d
D e

d e
b

= OV

d
e
—ed e

;WRITE/READ ERROR
cCLEAR MAINTENANCE MODE

Bi(
ggg

SCOPE

SATTEMPT TO CLEAR CHARACTER AVAILABLE
s CHARACTER AVAILABLE SHOULD BE SET
; (R5)=EXPECTED DATA IN

sSYSTEM CONTROL REGISTER
s CHARACTER AVAILABLE

sSYSTEM CONTROL REGISTER
sWRITE/READ ERROR

sSET MAINTENANCE MODE
sCLEAR CHARACTER AVAILABLE
cEXPECT ONLY MAINTENANCE

;SYSTEM CONTROL REGISTER,
sMAINTENANCE MODE BIT
sSYSTEM CONTROL REGISTER

;SYSTEM CONTROL REGISTER
;WRITE/READ ERROR
;CHECK FOR ITERATIONS, LOOP

;SYSTEM CONTROL REGISTER WRITE/READ TEST (MAINTENANCE MODE)
;SET MAINTENANCE MODE
JSET NON EXISTANT MEMORY IN SYSTEM CONTROL REGISTER
;VERIFY THAT NON EXISTANT MEMORY WAS SET
;CLEAR MAINTENANCE MODE

;VERIFY THAT NON EXISTANT MEMORY CANNOT BE CLEARED
;SET MAINTENANCE MODE
sCLEAR NON EXISTANT MEMORY
JVERIFY THAT NON EXISTANT MEMORY WAS CLEARED

)

D e

)

AONLAINLALNLALNIALNLNL
PV

sSYSTEM CONTROL REGISTER

201000
900200
000200

d e

d o

D o o

S FIRIISZE SLREREV28BRIRRE

D —

CZOHA=C MACY11 30A(1052)
23-AuG-78
15-MAY-78 10:0?
CZDHAC. P11

004 346
004354
004362
004370
004374
004404
004410
004412

012767
012767
012767
016703
012713
052713
022713

001404
012705

136:

MOV
MOV
MOV
MOV
MOV

;DISABLE ALL INTERRUPTS
SSET UP FOR 4000 ITERATIONS
SSET UP TO ESCAPE TO NEXT TEST
:PUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
*SET MAINTENANCE MODE

#81T09+BIT10, (R3}

SVERIFY THAT NON EXISTANT MEMORY

BIS

#1710, (R3)

CMP

003000

#340,PS
#4000, 1COUNT
#3$ _ESCAPE
DHSCR.R3
#81709, (R3)

#BITO9+BIT10,RS ;(RS)=EXPECTED DATA

011304

MOV

(R3) ,R4

004420

104001

HLT

004422
004426
004432

042713
042713
022713
001403
012705

8IC
BIC
g?z

#31709,(R3)
#1710, (R3)
#81T10, (R3)
2%
#2'T10,RS

004440

002000

1%:

SAND MAINTENANCE MODE ARE SET

MOV

004416

001000
002000
002000

SSET NON EXISTANT MEMORY

MOV

sIN SYSTEM CONTROL REGISTER
sMAINTENANCE MODE AND NON EXISTANT MEMORY
s (R4)=ACTUAL DATA IN

sSYSTEM CONTROL REGISTER
sSYSTEM CONTROL REGISTER

;WRITE/READ ERROR

;CLEAR MAINTENANCE MODE
SJATTEMPT TO CLEAR NON EXISTANT MEMORY
sNON EXISTANT MEMORY SHOULD BE SET
; (RS)=EXPECTED DATA IN

;SYSTEM CONTROL REGISTER

CZOHA=C MACY11

CZDHAC.PIN
1237
1238
1239
1260
1241
1242
1243
1244
1245
1246
1247
12648
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262

004444

052713
042713
022713

901000
002000
001000

004462
004464

001404
012705

001000

004470

011304

004472

104001

004474

104400

004476

1266

004520

1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282

1283

1284
1285

1286
1287
1288

1289
1290
1291
1292

004504
004512

004524
004530
004534

004540
004542

14:40

104001

004446
004452
004456

1263

1264
1265

30A(1052)
23-AUG-78
15-MAY-78 10:02

2%:

3%:

137:

016703
012713
052713
022713
001404
012705

JNON (XISTANT MEMORY

BIS
BIC

#1709, (R3)
#81710, (R3)

BEQ
MOV

#81T709, (R3)
3¢

JEXPECT ONLY MAINTENANCE
;MODE TO BE SET

#31T09,RS

; (RS)=EXPECTED DATA IN

MOV

(R3) ,R4

HLT

. SYSTEM CONTROL REGISTER

MOV
MOV
MOV
MOV
MOV

#340,PS
#4090, 1COUNT
#38_ESCAPE
DHSCR,R3
#1709, (rR3)

CMP

#BIT09+81T14, (R3)

#IT14. (R3)

(R3) ,R4

004550

104001

HLT

004552
004556
004562
004566
004570

042713
042713
022713
001403
012705

BIC
8IC

#81109, R3)
#mIT14, sg;

004574

104001

004576
004602
004606

052713
062713

c22713%

004612

00140

001000

’%:

sPUT ADDRESS OF SYSTEM CONTROL REGISTER IN R3
sSET MAINTENANCE MODE
sSET SILO OVERFLOW

*VERIFY THAT SILO OVERFLOW

sIN SYSTEM CONTROL REGISTER
MAINTENANCE MODE AND SILO OVERFLOW

MOV

001000

;DISABLE ALL INTERRUPTS
*SET UP FOR 4000 ITERATIONS
SSET UP TO ESCAPE TO NEXT TEST

MOV

011304

040000

;SYSTEM CONTROL REGISTER,
sMAINTENANCE MODE BIT
; (R4)=ACTUAL DATA IN
sSYSTEM CONTROL REGISTER

SAND MAINTENANCE MODE ARE SET
1%
#BITO9+BIT14
RS ; (R5)=EXPECTED DATA

004546

1¢:

sCLEAR NON EXISTANT MEMORY

:SYSTEM CONTROL REGISTER WRITE/READ TEST (MAINTENANCE MODE)
;SET MAINTENANCE MODE
JSET SILO OVERFLOW IN SYSTEM CONTROL REGISTER
;VERIFY THAT SILO OVERFLOW WAS SET
s CLEAR MAINTENANCE MODE
;VERIFY THAT SILO OVERFLOW CANNOT BE CLEARED
s SET MAINTENANCE MODE
;CLEAR SILO OVERFLOW
;VERIFY THAT SILO OVERFLOW WAS CLEARED

001000
040000
040000

JWRITE/RE,D ERROR
sSET MAINTCNANCE MODE

;SYSTEM CONTROL REGISTER
;WRITE/READ ERROR
;CHECK FOR ITERATIONS, LOOP

SCOPE

BIS

041000

SEQ 0036

HLT

012767
012767
012767

PAGE 26

:(R4)=ACTUAL DATA IN

sSYSTEM CONTROL REGISTER
sSYSTEM CONTROL REGISTER

;WRITE/READ ERROR

sCLEAR MAINTENANCE MODE

;ATTEMPT TO CLEAR SILO OVERFLOw

;SILO OVERFLOW SHOULD BE SET

cMP
BEQ
MOV

#MIT14
2%
MmIT4,

HLT

;SYSTEM CONTROL REGISTER

8IS
BI(

#1709, (R3)
#1714, (R3)

JSET MAINTENANCE MODE
;CLEAR SILO OVERFLOW

(MP
BEQ

#1109, (R3)
3

;(RS)=EXPECTED DATA IN
sSYSTEM CONTROL REGISTER
sSILO_OVERFLOW

;WRITE/READ ERROR

JEXPECT ONLY MAINTENANCE
;MODE TO BE SET

CZDHA-C MACY 30A(1052)10285AUG-78
CZDHAC.P11
15-MAY-78
1293
1294
1295
1296
1297
1298
1299

1%8?

004614

012705

004620

14:40

001000

#B1T09,RS

011306

MOV

(R3) R4

0046622

104001

HLT

004624

104400

1510

1311

1312
1313

1314

1315

004626

004634

006642

004650

012767

012777

016763
012705

004670

011304

004666

1321
1322

004704
004706

;ggg

012767

004656
006662

006672
004674
004676
004700

1323
1324,

010513

173142

004000

013056

004000

012774

004714

012774
000001

011304

004710
004712

005005
104002

T40:

013044

MOV

MOV
MOV

1%:

005704
001402

104400

2%:

012767

000340

1335

004732

012767

005004

004746
004752
004756

016703
012705
010513

012704
000002

004726

004740

004760

1361
1342
1343
1344

004762
004764
004766
004770

1346
1347
1348

004774
004776
005000

1345

#28 ESCAPE

#8I1T17,aDHSCR

MOV
CMP
BEQ
HLT
BIC

RS.Ré
1%
2
RS, (R3)

TST
8EQ

R4
2%

MOV

CLR
HLT
SCOPE

(R$) R4

(R$) .R4

RS
2

:DISABLE ALL

INTERRUPTS

“SET UP FOR 4000 ITERATIONS
SSET UP TO ESCAPE

TO NEXT TEST

‘MASTER CLEAR INTERFACE

“SET UP POINTER TO LINE PARAMETER
“BIT 0 WILL BE SET IN LINE PARAMETER

SSET BIT 0

*GET CONTENTS OF LINE PARAMETER
“WAS BIT O SET

;LINE PARAMETER REGISTER ERROR
*CLEAR BIT 0

SREAD CONTENTS " LINE PARAMETER
‘WAS BIT 0 CLEAR.D

;LINE PARAMETER REGISTER ERROR
TEST

SSET BIT 1 IN LINE PARAMETER 10 1
SVERIFY THAT BIT 1 WAS SET
SCLEAR BIT 1
SVERIFY THAT BIT 1 WAS CLEARED

004716

1340

#4000, 1COUNT

:LINE PARAMETER REGISTER DATA

1333

1337
1338
1339

#340,PS

DHLPR,R3
#1.RS
RS (R3)

MOV

1328
1329
1330
}ggg

1336

MOV

020504
001401
104002
040513

004702

004714

000340

1327

133

:CHECK FOR ITERATIONS, LOOP

:VERIFY THAT BIT 0 WAS CLEARED

1316
1317
1318
1319

1320

SCOPE

; (RS)=EXPECTED DATA IN
*SYSTEM CONTROL REGISTER,
*MAINTENANCE MODE BIT
*(R4)=ACTUAL DATA IN
*SYSTEM CONTROL REGISTER
*SYSTEM CONTROL REGISTER
SWRITE/READ ERROR

:LINE PARAMETER REGISTER DATA TEST
SSET BIT O IN LINE PARAMETER TO 1
*VERIFY THAT BIT 0 WAS SET
*CLEAR BIT 0

}ggg

1309

SEQ 0037

MOV

1302
1303
1304
1305
1308

PRAGE 27

004772

012767

012777

173052

004000

012766

004000

012704

T41:

012754

011304

005704
001402
005005

#4000, 1COUNT

MOV

#IT11,80HSCR

:DISABLE ALL INTERRUPTS

SSET UP FOR 4000 ITERATIONS

#2% . ESCAPE

:SET UP TO ESCAPE TO NEXT TEST

MOV
MOV
MOV

DHLPR,R3
#2.RS
RS (R3)

SSET UP POINTER TO LINE PARAMETER
“BIT 1 WILL BE SET IN LINE PARAMETER
SSET BIT 1

P
BEQ
HLT
BIC

RS.Ré
1%
2
RS, (R3)

ST
BEQ
CLR

R4
2s
RS

MOV

1%:

#340 PS

MOV

011304

020504
001401
104002
040513

MOV

(R$) R4

*MASTER CLEAR INTERFACE

*GET CONTENTS OF LINE PARAMETER
‘WAS BIT 1

SET

;LINE PARAMETER REGISTER ERROR
SCLEAR BIT 1

:READ CONTENTS OF LINE PARAMETER

*WAS BIT

CLEARED

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

1349
;ggQ

005002
005004

14:40

104002
104400

2s:

1352
1353
1354
1355
005006

012767

000340

1360
1361
1362
1363
1364

005022
005030
005036
005042
005046

012767
012777
016703
012705
010513

005074
004000
012614
000004

1366

005052

020504

005014

005050

012767

005054
005056
005060

001401
104002
040513

1371
1372
1373
1374,
gggg

005064
005066
005070
005072
005074

005704
001402
005005
104002
104400

005062

004000

172762

012676

T42:

012664
012614

011304

1367
1368
1369

1370

011304

012767

1385
1386

005112
005120

012767
012777

1388

005132

005104

004000

005126

016703

012524

005136

010513

005140

012705

#28 ,ESCAPE
#8IT11,3DHSCR
DHLPR.R3
#4 RS
RS, (R3)

“SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
‘BIT 2 WILL BE SET IN LINE PARAMETER
“SET BIT 2

RS, R4

‘WAS BIT 2 SET

(R$) R4

1%:

BEQ
HLT
BIC

1%
2
RS, (]3)

2$:

ST
BEQ
CLR
HLT
SCOPE

R4
2%
RS
2

020504
001401
104002
040513

1396
1397
1398
1399
;289

005154
005156
005160
005162
005164

005704
001402
005005
104002
104400

005152

005164
004000

172672

012606

T43:

012574
012524

MOV

011304

MOV

MOV
MOV

MOV

000020

MOV
MOV

011304

005142
005144
005146
005150

1402
1403
1404

000340

012767

1391
1392
1393
139,

1395

MOV
MOV
MOV
MOV
MOV

(R3) ,R4

SSET UP FOR 4000 ITERATIONS

<GET CONTENTS OF LINE PARAMETER
:LINE PARAMETER REGISTER ERROR
*CLEAR BIT 2

*READ CONTENTS OF LINE PARAMETER
‘WAS BIT 2 CLEARED

;LINE PARAMETER REGISTER ERROR

SVERIFY THAT BIT & WAS CLEARED

005076

1390

;DISABLE ALL INTERRUPTS

#4000, 1 COUNT

;LINE PARAMETER REGISTER DATA TEST
SSET BIT & IN LINE PARAMETER TO 1
SVERIFY THAT BIT 4 WAS SET
*CLEAR BIT 4

1383

1389

#340,PS

MOV

CMP

}%g;

1387

;LINE PARAMETER REGISTER ERROR

MOV

1377
1378
1379
1380

1384

SVERIFY THAT BIT 2 WAS CLEARED

1358

1365

HLT
SCOPE

SEQ 0038

;LINE PARAMETER REGISTER DATA TEST
*SET BIT 2 IN LINE PARAMETER TO 1
SVERIFY THAT BIT 2 WAS SET
*CLEAR BIT 2

}ggg

1359

PAGE 28

MOV

#3640 ,PS

:DISABLE ALL INTERRUPTS

#28 _ESCAPE
#BIT11,aDHSCR
DHLPR ,R3

SSET UP TO ESCAPE TG NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER

RS,

SSET BIT 4

#4000, 1COUNT

#20 RS

(R3)

(R$) R4

P
BEQ
HLT
BIC

RS.R&
18
2
RS, (R3)

2%:

ST
BEQ
CLR
HLT
SCOPE

R4
2%
RS
2

MOV

(R%) ,R4

SSET UP FOR 4000 ITERATIONS

:BIT 4 WILL BE SET IN LINE PARAMETER

*GET CONTENTS OF LINE PARAMETER
‘WAS BIT & SET

:LINE PARAMETER REGISTER ERROR
*CLEAR BIT 4

*READ CONTENTS OF LINE PARAMETER

‘WAS BIT 4 CLEARED

:LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
*SET BIT - IN LINE PARAMETER TQ 1
JVERIFY THAT BIT 5 WAS SE”

CZDHA-C MACY11 30A(1052)
23-AUG-78
P
CZDHAC.P11
15-MAY-78 10:02

14 :40

PAGE 29

SEQ 0039

3
N—l—l—d-&—l—l—l—l-‘—l

012767
012767
012767
012777
016703
012705
010513
011304
020504
001401

OVBNC
N WO

)
d e
)
D rd

d
d
b
)

N N

—

Y N

;CLEAR BIT §
‘VERIFY THAT BIT 5 WAS CLEARED
000340

005254
004000
012434
000040

MOV

104002
104400

2%:

#2$ ESCAPE
#81711,aDHSCR
DHLPR R3

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
“SET UP POINTER TO LINE PARAMETER

RS, (R3)

‘SET BIT S

MOV

#40,RS

MOV

1%:

;DISABLE ALL

#4000, 1COUNT

CMP
BEQ

104002

#340,PS

MOV

MOV
MOV
MOV

MOV

040513
011304
005704
001402
005005

14621

Téh:

(R$) .RG

RS.Ré
1%

qLT
8IC

2
RS,

MOV
BEQ
CLR
HLT
SCOPE

(R3)

(R$) R4

2
RS
2

INTERRUPTS

*SET UP FOR 4000 ITERATIONS

‘BIT S WILL BE SET IN LINE PARAMETER
*GET CONTENTS OF LINE PARAMETER
*WAS BIT S SET

;LINE PARAMETER REGISTER ERROR
*CLEAR BIT §

*READ CONTENTS OF LINE PARAMETER

*WAS BIT 5 CLEARED

;LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
*SET BIT 6 IN LINE PARAMETER TO 1
*VERIFY THAT BIT 6 WAS SET

*CLEAR BIT 6
*VERIFY THAT BIT 6 WAS CLEARED
012767
012767

000340
004000
005344
004000
0123244
00C 100

T45:

MOV

#340,PS

:DISABLE ALL

MOV
MOV
MOV
MOV
MOV

#28 ESCAPE
#81717,aDHSCR
DHLPR,R3
#100,RS
RS, (R3)

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
‘BIT 6 WILL BE SFT IN LINE PARAMETER
“SET BIT 6

CMP
BEQ

RS, R4
18

*WAS BIT 6 SET

MOV

MOV
1%:

(R$) R4

INTERRUPTS

*SET UP FOR 4000 ITERATIONS

*GET CONTENTS OF LINE PARAMETER

HLT
BIC

2
RS,

TST

*WAS BIT 6 CLEARED

HLT

:LINF PARAMETER REGISTER ERROR

MOV
BEQ
CLR

2%:

#4000, 1COUNT

SCOPE

(R3)

(R$) R4

2
RS

;LINE PARAMETER REGISTER ERROR
*CLEAR BIT 6

*READ CONTENTS OF LINE PARAMETER

;LINE PARAMETER REGISTER DATA TEST

*SET BIT 7 IN LINE PARAMETER TQ 1
“VERIFY THAT BIT 7 WAS SET
:CLEAR BIT 7
*VERIFY THAT BIT 7 WAS CLEARED

1455
1456
1459
1460

005346
005354
005362

T46:

MOV

#340 PS

:DISABLE ALL

MOV

#2$ . ESCAPE

*SET UP TO ESCAPE TO NEXT TEST

MOV

#5700, TCOUNT

INTERRUPTS

“SET UP FOR 4000 ITERATIONS

CZDHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-~78 10:02
CZDHAC.P11

005370
005376
005402
005406
005410
005412
005414
005416
005420
005422

012777
016703
012705
010513
011304

004000
012254
000200

14 :40

012254

PAGE 30

MOV
MOV
MOV
MOV

#81T11,3DHSCR
DHLPR,R3
#200,RS
RS, (R3)

;MASTER CLEAR INTERFACE
*SET UP POINTER TO LINE PARAMETER
‘BIT 7 WILL BE SET IN LINE PARAMETTMR
“SET BIT 7

cTMP

RS.Ré

‘WAS BIT 7 SET

HLT
BIC
MOV

2
RS, (R3)
(R%) ,R4

MOV
BEQ

1%:

TST

2%:

SEQ 0040

BEQ
CLR
HLT
SCOPE

(R$) R4

SGET CONTENTS OF LINE PARAMETER
;LINE PARAMETER REGISTER ERROR
‘CLEAR BIT 7

*READ CONTENTS OF LINE PARAMETER

‘WAS BIT 7 CLEARED

:LINE PARAMETER REGISTER ERAOR

2%
RS

;LINE PARAMETER REGISTER DATA TEST
JSET BIT 10 IN LINE PARAMETER T0 1
;VERIFY THAT BIT 10 WAS SET
;CLEAR BIT 10
JVERIFY THAT BIT 10 WAS CLEARED
012767
012767
012767
012777
016703
012705

000340
004000
005524
004000
012164
000400

172332
012246
012234
012164

T47:

MOV

#340,PS

;DISABLE ALL

MOV
MOV
MOV
MOV

#81711,aDHSCR
DHLPR,R3
#400,RS
RS, (R3)

*MASTER CLEAR INTERFACE
“SET UP POINTER TO LINE PARAMETER
*BIT 10 WILL BE SET IN LINE PARAMETER
:SET BIT 10

CMP

RS RS

MOV
MOV

MOV
1%:

*GET CONTENTS OF LINE PARAMETER

BEQ
HLT
BIC

1%
2
RS, (R3)

:LINE PARAMETER REGISTER ERROR
*CLEAR BIT 10

*WAS BIT 10 CLEARED

;LINE

MOV

[elelolelelalelele]

~
OIS NN —O

S T
X
[

HLT

SCOPE

(R%) .R4

2$
RS

*WAS BIT 10 SET

:READ CONTENTS OF LINE PARAMETER
PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
sSET BIT 11 IN LINE PARAMETER TO 1
;VERIFY THAT BIT 11 WAS SET
;CLEAR BIT 11
;VERIFY THAT BIT 11 WAS CLEARED

1505
NN
WA NN VIV

INTERRUPTS

*SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST

(R$) R4

BEQ
CLR

2%:

#5000, 1 COUNT
#2$ ,ESCAPE

000340
004000
005614
004000
012074
001000

172242
012156
012144
012074

150:

MOV

MOV
MOV

#340,PS

#4300, 1COUNT

#28 ESCAPE

:DISABLE ALL

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

*SET UP TO ESCAPE TO NEXT TEST

MOV
MOV
MOV

#81717,aDHSCR
DHLPR,R3
#1000 RS

*MASTER CLEAR INTERFACE
SSET UP POINTER TO LINE PARAMETER
:BIT 11 WILL BE SET IN LINE PARAMETER

(MP

RS RS,

‘WAS BIT 11 SET

MOV
MOV

RS, (R$)
(~%) R4

LSET BIT 11
SCET CONTENTS OF LINE PARAMETER

[ala]
NN
p=4

DHA-C MACY11 30A(1052)
23-AUG-78
HAC.P11
15-MAY=78 10:02

1517
1518
1519

005574
005576
005600

1521
1522
1523
1524

005604
005606
005610
005612

1520

;ggg

14:40

001401
104002
040513

005602

011304

005614

104400

005704
001402
005005
104002

28 :

1527

005616

012767

000340

1535
1536
1537
1538

005632
005640
005646
005652

012767
012777
016703
012705

005704
004000
012004
002000

005662
005664
005666
005670
005672
005674
005676
005700
005702
005704

020504
001401
104002
040513
011304
005704
001402
005005
104002
104400

005624

005656
005660

012767

010513
011304

004000

172152

~S1:

012054
012004

1$:

2%:

R
23
RS
2

SCOPE

$) R

‘READ CONTENTS OF LINE PARAMETER
*WAS BIT 11

CLEARED

:LINE PARAMETER REGISTER ERROR

MOV

#340,PS

:DISABLE ALL

#2$ ESCAPE
#8]T11,aDHSCR
DHLPR,R3
#2000 RS

SSET UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE
“SET UP POINTER TO LINE PARAMETER
;BIT 12 WILL BE SET IN LINE PARAMETER

MOV

#4000, 1COUNT

MOV
MOV

RS, (R%)
(R$) R4

M
BEQ
HLT
BIC
MOV
TST
BEQ
CLR
HLT
SCOPE

RS,Ré
1%
2
RS, (R3)
(R3) ,R4
R4
2%
RS
2

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

;SET BIT 12
SGET CONTENTS OF LINE PARAMETER
‘WAS BIT 12 SET

;LINE PARAMETER REGISTER ERROR
*CLEAR BIT 12
*READ CONTENTS OF LINE PARAMETER
*WAS BIT 12 CLEARED

:LINE PARAMETER REGISTER ERROR

;JVERIFY THAT BIT 13 WAS CLEARED

1558

005706

012767

000340

1560
1561
1562
1563

005722
005730
005736
005742

012767
012777
016703
012705

$05774
004000
011714
004000

1565
1566
1567
1568
1569

005750
005752
005754
005756
005760

011304
020504
001401
104002
040513

15721
1572

005764
005766

005704
001402

1570

ST
BEQ
(LR
HLT

MOV

:LINE PARAMETER REGISTER ERROR
*CLEAR BIT 11

:LINE PARAMETER REGISTER DATA TEST
:SET B!T 13 IN LINE PARAMETER TO 1
SVERIFY THAT BJT 13 WAS SET
*CLEAR BIT 13

}ggg

1564

18
2
RS, (R3)

MOV
MOV
MCV
MOV

1552
1553
1554
1555

1559

BEQ
HLT
BIC

:VERIFY THAT BIT 12 WAS CLEARED

1533

1541
1542
1543
1544
1545
1546
1547
1548
1549
;ggg

SEQ D041

SSET BIT 12 IN LINE PARAMETER T0O 1
SVERIFY THAT BIT 12 wAS SET
SCLEAR BIT 12

}2%}

1539
1540

:LINE PARAMETER REGISTER DATA TEST

1528
1529
1530

1534

PAGE

005714

005746

005762

012767

010513

011304

004000

172062

011776

T152:

011764
011714

MOV

;:DISABLE ALL

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

MOV
MOV
MOV
MOV

#2$ ,ESCAPE
#BIT11,aDHSCR
DHLPR.R3
#4000 .R5

*SET UP TO ESCAPE TO NEXT TEST
SMASTER CLEAR INTERFACE
SSET UP POINTER TO LINE PARAMETER
;BIT 13 WILL BE SET IN LINE PARAMETER

MOV
cMP
BEQ
HLT
BIC

(R3) R4
RS,R4
1%
2
RS, (R3)

:GET CONTENTS OF LINE PARAMETER
‘WAS BIT 13 SET

TST
BEQ

R&
2%

‘WAS BIT 13 CLEARED

MOV

1%:

#340,PS

#4000, 1COUNT

MOV

RS (R3)

(R$) R4

;SET BIT 13

;LINE PARAMETER REGISTER ERROR
SCLEAR BIT 13

*READ CONTENTS OF LINE PARAMETER

CZDHA-C MACY11 30A(1052)
285AUG-78
CZDHAC.P11
15-MAY-78 10

1573
1574

1575
1576
1577

1578
1579
1580
1581
1582
1583
1584
1585

1586
1587
1588

005770
005772
005774

005005
104002

14:40

PAGE 32

SEQ 0042
CLR

2%:

104400

HLT

SCOPE

SSET BIT 16 IN LINE PARAMETER T0 1
*VERIFY THAT BIT 14 WAS SET
*CLEAR BIT 14
*VERIFY THAT BIT 14 WAS CLEARED
005776
006012
006020
006026
006032

012767
012767
012767
012777
016703
012705

000340
004000
006064
004000
011624
010000

T53:

MOV

*SET UP TO ESCAPE TO NEXT TEST

#817T11,3DHSCR

MOV
MOV

SSET UP Fw 4000 ITERATIONS

‘MASTER CLEAR INTERFACE

DHLPR R3

YSET UP POINTER TO LINE PARAMETER

RS,

SSET BIT 14

#10000,R5S
(R3}

(R3) R4

:BIT 14 WILL BE SET IN LINE PARAMETER

“GET CONTENTS OF LINE PARAMETER

C?fi
B
HLT
BIC

$§.R4

TST

“WAS BIT

HLT
SCOPE

:LINE PARAMETER REGISTER ERROR

MOV

RS,

(R3)

(R3) .R4

2$
RS

“WAS BIT 14 SET

:LINE PARAMETER REGISTER ERROR

“CLEAR BIT 14

SREAD CONTENTS OF LINE PARAMETER
14

CLEARED

:LINE PARAMETER REGISTER DATA TEST
*SET BIT 15 IN LINE PARAMETER TO 1
*VERIFY THAT BIT 15 WAS SET
*CLEAR BIT 15

1603
1604
1605
1606

1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628

#2$ ESCAPE

MOV

BEQ
CLR
1601
1602

:DISABLE A'. INTERRUPTS

#4000, TCOUNT

MOV

’%:

#340,PS

MOV

1%:

1615
1676

;LINE PARAMETER REGISTER ERROR

:LINE PARAMETER REGISTER DATA TEST

MOV

1607
1608
1609
1610
1611
1612
1613
1614

*VERIFY THAT BIT 15 WAS CLZARED
006066
006074
C06102
006110
006116
006122
006126
006130
006132
006134
006136
006140

006142
006144
006146
006150
006152
006154

012767
012767
012767
012777
016703
012705
010513
011304
020504
001401
104002
040513

011304
005704
001402
005005
104002
104400

000340
004000
006154
004000
011534
020000

154:

MOV

#340,PS

:DISABLE ALL

MOV
MOV
MOV

#2$ ESCAPE
#81711,aDHSCR
DHLPR ,R3

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
“SET UP POINTER TO LINE PARAMETER

MOV

RS,

;SET BIT 15

MOV

MOV
MOV

1%:

#4000, 1 COUNT

#20000.RS
(R3)

INTERRUPTS

*SET UP FOR 4000 ITERATIONS

:BIT 15 WILL BE SET IN LINE PARAMETER

g?g

?2,R4

(R$) R4

*GET CONTENTS OF LINE PARAMETER

HLT

;LINE

BIC

MOV
ST

BEQ
CLR
HLT
SCOPE

RS,

(R3)

(R$) R4

2%
RS
2

‘WAS BIT

15 SET

PARAMETER REGiSTER ERROR

*CLEAR BIT 15

*READ CONTENTS OF LINE PARAMETER
*WAS BIT

CLEARED

;LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
;SET BIT 16 IN LINE PARAMETER TO 1

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P1?
15-MAY=78 10:02

14:40

1629
1639

SVERIFY THAT BIT 16 WAS CLEARED

1633

006156

012767

000340

1635

006172

012767

006244

1636

1637

006164

006200

006222

020504

1662

006224

1643

006226

1645

006232

16646
1647
1648
1649
?ggg

012777

016703

006212
006216
006220

1644

012767

006206

1638
1639
1660

1641

006230

006234
006236
006240
006242
006244

012705
010513
011304

171612

004000

011526

004000

011444

T55:

011514

1660

cTMP

104002

040513

011304

005704
001402
005005
104002
104400

006246

006254

006262

012767

012767
012767

000340

011436

011354

006334

006302

C12705

100000

006276
006306

006310

016703

010513

006312
006314
006316
006320

020504
001401
104002
040513

1671
1672
1673
1674
;2;2

006324
006326
006330
006332
006334

005704
001402
005005
104002
104400

#0000, RS
RS, (R3)
(R$) R4

RS,R&4

;BIT 16 WILL BE SET IN LINE PARAMETER
;SET BIT 16
SGET CONTENTS OF LINE PARAMETER
‘WAS BIT 16 SET

;LINE PARAMETER REGISTER ERROR

DHLPR,R3

RS,

2%:

ST
BEQ
CLR
HLT
SCOPE

R4
2%
RS
2

011354

T156:

011424

(R3)

(R3).R4

SSET UP TO ESCAPE TO NEXT TEST

SSET UP POINTER TO LINE PARAMETER

:CLEAR BIT 16

*READ CONTENTS OF LINE PARAMETER
‘WAS BIT 16 CLEARED

;LINE PARAMETER REGISTER ERROR

MOV

#340,PS

:DISABLE ALL

MOV

#28 ESCAPE

SSET UP TO ESCAPE

MOV

#B8IT11,aDHSCR

MOV

#100000.RS

MOV

011304

#4000, 1COUNT

MOV
MOV

DHLPR,R3

RS,

(R3)

(R%) R4

1%:

CMP
BEQ
HLT
BIC

RS.Ré
1%
2
RS, (R3)

2% :

TST
BEQ
CLR
pLT
SCOPE

R4
2%
RS
2

1677
1678
1679
1680

MOV

(Rg),Ré

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

TO NEXT TEST

*MASTER CLEAR INTERFACE

JSET UP POINTER TO LINE PARAMETER

;BIT 17 WILL BE SET IN LINE PARAMETFR

;SET BIT 17

SGET CONTENTS OF LINE PARAMETER

‘WAS BIT 17 SET

;LINE PARAMETER REGISTER ERROR
*CLEAR BIT 17

JREAD CONTENTS OF LINE PARAMETER
*WAS BIT 17 CLEARED

;LINE PARAMETER REGiSTER ERROR

:BREAK CONTROL REGISTER DATA TEST
*SET BIT O IN BREAK CONTROL T0O 1
*VERIFY THAT BIT 0 wAS SET
*CLEAR BIT 0

1681

1684

*MASTER CLEAR INTERFACE

BIC

011304

1666
1667
1668
1669

006322

171522

004000

1663

1682
1683

#8]1T11,8DHSCR

MOV

INTERRUPTS

“SET UP FOR 4000 ITERATIONS

:VERIFY THAT BIT 17 WAS CLEARED

004000

1670

HLT

;:DISABLE ALL

#4000, 1COUNT

;LINE PARAMETER REGISTER DATA TEST
JSET BIT 17 IN LINE PARAMETER TO 1
JVERIFY THAT BIT 17 WAS SET
JCLEAR BIT 17

012777

1665

#2% ESCAPE

BEQ

006270

1664

MOV

MOV
MOV
MOV

001401

1661

1662

#340,PS

MOV

040000

}229

1659

MOV

1652
1653
1654
1655

1658

SEQ J043

;VERIFY THAT BIT 16 WAS SET
‘CLEAR BIT 16

}g%;

1634

PAGE 33

006336

006344

012767

000340

004000

171432

011346

1°7:

SVERIFY

THAT BIT 0 WAS CLEARED

MOV

#'0,PS

MOV

#4000, 1 COUNT

;DISABLE ALL

INTERRUPTS

;SET UP FOR 4000 ITERATIONS

CZOHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC .P11
15-MAY-78 10:02
1685

006352

012767

006424

012705

000001

1686
1687

006360
006366

012777
016703

1689

006376

010513

1688

1690

1691
1692

006372

006400

006402
006404

1693
1694

006406
006410

1696
1697
1698
1699

006414
006416
006420
006422

1695

?;8?

006412

006424

004000
911274

14:40

011334

011264

PAGE 34
MOV

#28 ESCAPE

;SET UP TO ESCAPE

MOV

#1.RS

*BIT 0 WILL BE SET

(R$) RS

*GET CONTENTS OF BREAK CONTROL

3
RS,

;BREAK CONTROL REGISTER ERROR
:CLEAR BIT 0

MOV
MOV
MOV

011304

MOV

020504
001401

CTMP
BEQ

104003
040513

‘s

011304

005704
001402
005005
104003

104400

2%:

SEQ 0044

HLT
BIC

MOV

TST
BEQ
CLR
HLT

SCOPE

#81717,aDHSCR
DHBCR,R3
RS’

(R3)

RS, R4
1%

(R3)

(R$) R4

R4
2%
RS
3

‘SET BIT 0

*READ CONTENTS OF BREAK CONTROL
‘WAS BIT 0 CLEARED

;BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
*SET BIT 1 IN BREAK CONTROL TO 1

1705

SCLEAR BIT 1

SVERIFY THAT BIT 1 WAS SET

};89

:VERIFY THAT BIT 1 WwAS CLEARED

1708

006426

012767

1710
1711
1712
1713
1714

006442
006450
006456
006462
006466

012767
012777
016703
012705
010513

1709

1715

1716
1717
1718
1719
1720
1721
1722

1723
1724

;;gg

006436

006470

006472
006474
006476
006500
006502
006504
006506

006510
006512

006514

012767

000340

T60:

004000

006514
004000
011204
000002

011304

MOV

020504
001401
104003
040513
011304
005704
001402

Is:

005005
104003

1735
1736
1737

1738
1739

1740

cMP
BEQ
HLT
BIC
MOV
TST
BEQ
CLR
HLT

104400

#340,PS

#4000, I COUNT

#2% . ESCAPE
#1711, aDHSCR
DHBCR,R3
#2.R5
RS’ (R3)

(R3) R4

RS,Ré
1%
3
RS. (R3)
(R3) ,R4
R4
2$

RS
3

:DISABLE ALL

INTERRUPTS

*SET UP FOR 4000 ITERATIONS
SSET UP TO ESCAPE

TO NEXT TEST

*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
*BIT 1 WILL BE SET IN BREAK CONTROL
SSET BIT 1

“GET CONTENTS OF BREAK CONTROL
*WAS BIT 1

SET

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 1
‘READ CONTENTS OF BREAK CONTROL
*WAS BIT 1 CLEARED
:BREAK CONTROL REGISTER ERROR

SCOPE

;BREAK CONTROL REGISTER DATA TEST

1728
1729
1730
4;;}

173,

MOV

MOV
MOV
MOV
MOV
MOV

1727

1733

IN BREAK CONTROL

‘WAS BIT 0 SET

1702
1703

1704,

TO NEXT TEST

SMASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL

*SET BIT 2 IN BREAK CONTROL TO 1
SVERIFY THAT BIT 2 WAS SET
*CLEAR BIT 2
"VERIFY THAT BIT 2 WAS CLEARED
006516

006524

006532
006540
006546
006552
006556

006560

012767

012767
012767
012777
016703

012705
010513

011304

000340

004000
006604
0046000
011114
000004

171252

011166
011154
011104

T61:

MOV

MOV
MOV
MOV

#340,PS

;DISABLE ALL

INTERRUPTS

#4000, 1 COUNT

*SET UP FOR 4000 ITERATIONS

¥4 RS
R> - (R3)

‘BIT 2 WILL SE SET
SSET BIT 2

#2$ ,ESCAPE
#81717,aDHSCR
DHBCR,R3
(R3) R4

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
SSET UP POINTER TO BREAN CONTROL

*GET

IN BREAK CONTROL

CONTENTS OF BREAK CONTROL

CZDHA-C MACY11 30A(1052)
28-AUG-78
CZDHAC.P11
15-MAY-78 10:02
17641
1762
17643
1764

1745

1746
1747
1748
1749

;;g?

006562
006564
006566

020504
001401
104003

006570

040513

006574
006576
006600
006602

005704
001402
005005
104003

006572

006604

14:40

1%:

011304

104400

28:

1752
1753
1754
1755

WP
b1Q
HLT

RS, R4
1%

;WAS BIT 2 SET

BIC

RS,

*CLEAR BIT 2

TST
BEQ
CLR
HLT

R4
2%
RS
3

MOV

SCOPE

006606

012767

000340

1760
1761
1762

006622
006630
006636

012767
012777
016703

006674
004000
011024

1764

006646

010513

006614

006642

012767

012705

004000

171162

011076

167:

011064
011014

000010

#2% ESCAPE
#B1T11,8DHSCR
DHBCR R3

SSET UP TO ESCAPE TO NEXT TEST
‘MASTER CLEAR INTERFACE
SSET UP POINTER TO BREAK CONTROL

MOV

1767
1768
1769

006654
006656
006660

001401
104003
040513

1771
1772

006664
006666

006652

006662

006670
006672

0066764

020504

1¢:

011304

005704
001402

005005
1046003

104400

0% :

1777

1785
1786

1787

1788

1789

006676

006704

006712
006720

012767

006726

012767
012777
016703

006736

010513

0Ccrwé
006744

020504
001401

006732

006740

1793
1794

006746
006750

1796

006754

1795

‘BIT 3 WILL BE SET IN BREAK CONTROL

(R3)

SSET BIT 3

CMP

(R$) .R4

RS.R&

*GET CONTENTS OF BREAK CONTROL

BEQ
HLT
BIC

1%
3
RS, (R3)

;BREAK CONTROL REGISTER ERROR
;CLEAR BIT 3

ST
BEQ

R4
2%

MOV
CLR
HLT

SCOPE

‘WAS BIT 3 SET

(R$) R4

‘READ CONTENTS OF BREAK CONTROL

*WAS BIT 3 CLEARED

RS
3

;BREAK CONTROL REGISTER ERROR

*VERIFY THAT BIT &4 WAS CLEARED

1790

1791
1792

RS,

INTERRUPTS

*SET UP FOR 4000 ITERATIONS

#10.R5

*SET BIT & IN BREAK CONTROL
SVERIFY THAT BIT & WAS SET
*CLEAR BIT 4

};g;

1784

#4000, 1COUNT

:BREAK CONTROL

1778
1779
1780

1783

;BREAK CONTROL REGISTER ERROR

MOV
MOV
MOV

MOV

;;;2

*READ CONTENTS OF BREAK CONTROL

‘WAS BIT 2 CLEARED

;DISABLE ALL

011304

1773
1774

(RS) ,R4

#340,PS

MOV

006650

1770

;BREAK. CONTROL REGISTER ERROR

(R3)

MOV

1765

1766

SVERIFY THAT BIT 3 WAS CLEARED

1758

1763

SEQ 0045

;BREAK CONTROL REGISTER DATA TEST
SSET BIT 3 IN BREAK CONTROL TO 1
SVERIFY THAT BIT 3 WAS SET
*CLEAR BIT 3

};gg

1759

PAGE 35

006752

012705

000360

004000
006764
004000
010734

171072

011006

163:

010774
010724

000020

011304

005704

;:DISABLE ALL

#2% ESCAPE
#81T11,3DHSCR
DHBCR ,R3

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL

INTERRUPTS

MOV

#20.R5

‘BIT & WILL BE SET IN BREAK CONTROL

MOV

(R$) ,R4

:GET CONTENTS OF BREAK CONTROL

HLT
BIC

3
RS,

:BREAK CONTROL REGISTER ERROR
*CLEAR BIT 4

TST

Ré

MOV

P
BEQ

1$:

#340,PS

#4000, 1COUNT

MOV
MOV
MOV

011304

104003
040513

MOV

RS,

(R3)

RS.RG
ik

(R3)

(A% LR

*SET UP FOR 4000 ITERATIONS

“SET BIT 4

‘WAS BIT & SET

*READ CONTENTS OF BREAK CONTROL
“WwAS BIT & CLEARED

CZDOHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC .P11
15-MAY-78 10:02

1797
1798
1799

;gg9

006756
006760
006762

006764

14:40

001402
005005
104003

104400

2$:

1802
1803
1804
1805
006766

012767

000340

1810
1811
1812

007002
007010
007016

012767
012777
016703

007054
004000
010644

i813

006774

007022

012767

012705

007026

010513

1816
1817
1818
1819

007032
007034
007036
007040

020504
001401
104003
040513

"821

007044

005704

1815

1820

1822
1823
1824

;ggg

007030

007042

007046
007050
007052

007054

004000

171002

010716

Té4:

010704
010634

000040

011304

1835

1837
1838
1839

1840

1841
1842
1843
1844
1845
1846
1847
1848
1849
1850

1852

;DISABLE ALL

MOV
MOV
MOV

#28 ESCAPE
#1711 ,3DHSCR
DHBCR,R3

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL

MOV

1%:

011304

001402
005005
104003

104400

28:

#4000, 1COUNT

#40.RS
RS,

BEQ
CLR
HLT

SSET BIT 5

(R$) .RG

RS,Ré
1%
3
RS, (R3)

MOV

:BIT S WILL BE SET IN BREAK CONTROL

(R3)

CMP
BEQ
HLT
BIC

INTERRUPTS

*SET UP FOR 4000 ITERATIONS

*GET CONTENTS OF BREAK CONTROL
‘WAS BIT S SET

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 5

(R3) R4

:READ CONTENTS OF BREAK CONTROL
“WwAS BIT 5 CLEARED

2$
RS
2

;BREAK CONTROL REGISTER ERROR

SCOPE
;BREAK CONTROL REGISTER DATA TEST

*SET BIT 6 IN BREAK CONTROL
‘VERIFY THAT BIT 6 WAS SET
‘CLEAR BIT 4

}ggg

1836

#340,PS

MOV

1828
1829
1830

183%

;BREAK CONTROL REGISTER ERROR

MOV

1827

1833

2$
RS
3

SVERIFY THAT SIT S WAS CLEARED

1808

1814

BEQ
CLR
HLT
SCOPE

SEQ 0046

:BREAK CONTROL REGISTER DATA TEST
*SET BIT 5 IN BREAK CONTROL TO 1
SVERIFY THAT BIT S WwAS SET
:CLEAR BIT 5

1389

1809

PAGE 36

TO 1

VERIFY THAT BIT 6 WAS CLEARED

007056

007064

007072

007100

007106
007112
007116

007120

007122
007124
007126
007130
007132
007134
007136
007140
007142
007144

012767

012777

016703
012705
010513

000340

170712

004000

010626

004000

010544

007144

010554
000100

T65:

070614

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

MOV

#8]1T11,3DHSCR

“MASTER CLEAR INTERFACE

MOV

2% :

:DISABLE ALL

#4000, 1 COUNT

MOV
MOV
MOV

1$:

#340,PS

MOV

011304

020504
001401
104003
040513
071304
005704
001402
005005
104003
104400

MOV

CMP
BEQ
HLT
BIC
MOV
ST
8EQ
CLR
HUT
SCOPE

#2$ ESCAPE

*SET UP TO ESCAPE

TO NEXT TEST

DHBCR,R3
#100,RS
RS, (R3)

*SET UP POINTER TO BREAK CONTROL
SBIT 6 WILL BE SET IN BREAK CONTROL
SSET BIT 6

RS.RS
1%
3
RS, (R3)
(R5) R4
R4
2%
RS
3

*WAS BIT 6 SET

(R3) R4

SGET CONTENTS OF BREAX CONTROL

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 6
SREAD CONTENTS OF BREAK CONTROL
‘WAS BIT & CLEARED

:BREAK (ONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA "EST

CZOHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=78 10:02

14:40

1853
1854
1855

SVERIFY THAT BiT 7 WAS CLEARED

1858

007146

012767

000340

1860
1861
1862
1863
1864

007162
007170
007176
007202
007206

012767
012777
016703
012705
010513

007234
004000
010464
000200

007154

1865

007210

1868

007216

1870

007222

1866
1867
1869

1871
1872
1873
1874

; g;g

007212
007214

007220

007224
007226
007230
007232

007234

012767

004000

170622

010536

T66:

010524
010454

011304

104003

040513

011304

005704
001402
005005
104003

104400

2%:

007236
007244
007252
007260
007266
007272
007276

012767
012767
012767
012777
016703
012705
010513

1891
1892
1893
1894

007302
007304
007306
007310

020504
001401
104003
040513

189
1897
1898
1899

007314
007316
007320
007322

005704
001402
005005
104003

007300

007312

007324

000340
004000
007324
004000
010374
000400

170532
010446
010434
010364

T167:

011304

MOV
MOV
MOV
MOV
MOV

#28 ESCAPE
#8]711,aDHSCR
DHBCR,R3
#200,RS
RS, (R3)

*SET UP TO ESCAPE TO NEXT TEST
SMASTER CLEAR INTERFACE
SSET UP POINTER TO BREAK CONTROL
:BIT 7 WILL BE SET IN BREAK CONTROL
SSET BIT 7

cTMP
BEQ

RS.RS
1%

‘WAS BIT 7 SET

BIC

RS,

*CLEAR BIT 7

TST
BEQ
CLR
HLT

R4
2%
RS
3

HLT

MOV

(R$) .RG

(R3)

(R$).R4

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

SGET CONTENTS OF BREAK CONTROL

;BREAK CONTROL REGISTER ERROR

*READ CONTENTS OF BREAK CONTROL
*WAS BIT 7 CLEARED
;BREAK CONTROL

SCOPE

MOV
MOV
MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, ] COUNT
#28 . ESCAPE
#BIT11,aDHSCR
DHBCR.R3
#400,RS
RS, (R3)

cMP
BEQ
HLT
BIC

RS,R4
1%
3
RS, (R3)

ST
BEQ
CLR
HLT

Ré
2%
RS
3

MOV

1%:

011304

106400

2 :

1902
1903
1904
1905

MOV

SCOPE

(k%) R4

(R3) R4

:DISABLE ALL INTERRUPTS
SSET UP FOR 4000 ITERATIONS
SSET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
:BIT 10 WILL Bt SET IN BREAK CONTROL
*SET BIT 10

:GET CONTENTS OF BREAK CONTRO!
“WAS BIT 10 SET

;:BREAK CONTROL REGISTER ERROR
*CLEAR BIT 10

*READ CONTENTS OF BREAK CONTROL
*WAS BIT 10 CLEARED

;BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
*SET BIT 11 IN BREAK CONTROL 10 1
SVERIFY THAT BIT 11 WAS SET
SCLEAR B]T M

4389

1908

:DISABLE ALL

#4000, 1COUNT

SVERIFY THAT BIT 10 WAS ZLEARED

1883
1884
1885
1886
1887
1888
1889

;gg?

#340,PS

MOV

;BREAK CONTROL REGISTER DATA TEST
“SET BIT 10 IN BREAK CONTROL TO 1
SVERIFY THAT BIT 10 WAS SET
SCLEAR BIT 10

}ggg

1895

MOV

020504
001401

1877
1878
1879
1880

1890

SEQ 0047

;SET BIT 7 IN BREAK CONTROL TO 1
SVERIFY THAT BIT 7 WAS SET
‘CLEAR BIT 7

}ggg

1859

PAGE 37

SVERIFY THAT BIT 11 WAS CLEARED
007326

012767

000340

170442

T170:

MOV

#340,PS

:DISABLE ALL

INTERRUPTS

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

1909
1910
1911

007334
007342
007350

012767
012767
012777

1912

007356

016703

1914
1915

007
007370

010513
011304

1917
1918
1919

007374
007376
007400

001407
104003
040513

1921
1922
1923
1924
;ggg

007404
007406
007410
007412
007414

005704
001402
005005
104003
104450

1913

1916

1920

007362

007372

007402

012705

004000
007414
004000

010304

14:40

010356
010344
010274

MOV
MOV
MOV
MOV

001000

020504

011304

012767

000340

1935
1936
1937

0076432
0076440
007646

012767
012777
016703

007504
0046000
010214

007424

007452

012767

012705

1939
1940

007456
007460

1942
1943
1944

007464
007466
007470

001401
104003
040513

1946
1947
1948
1949
1329

007474
007476
007500
007502
007504

005704
001402
005005
104003
104400

007462

007472

010513
011304

004000

RS, (R$)
(R$) R4

SET BIT 11
SGET CONTENTS OF BREAK CONTROL

RS.R&

’%:

ST
BEQ
CLR
HLT
SCOPE

170352

01026€

T171:

010254
010204

MOV

1%
3
RS, (R3)

(R%) R4

R4
2$
RS
3

MOV

;BIT 11 WILL BE SET

IN BREAK CONTROL

‘WAS BIT 11 SET

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT M

*READ CONTENTS OF BREAK CONTROL
“WAS BIT 11

CLEARED

;BREAK CONTROL REGISTER ERROR

011304

:DISABLE ALL INTERRUPTS

#28 ESCAPE
#B1711,3DHSCR
DHBCR,R3

#2000 .RS

:SET UP TO ESCAPE TO NEXT TEST
‘MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
;BIT 12 WILL BE SET IN BREAK CONTROL

RS.Ré

‘WAS BIT 12 SET

#4000, 1COUNT

MOV

TMMP

MOV
MOV

020504

#340,PS

MOV

MOV
MOV
MOV

002000

RS, (R$)
(R$) .R4

1%:

BEQ
ALT
BIC

1%
3
RS, (R3)

2$:

ST
BEQ
CLR
HLT
SCOPE

R4
2s
RS
3

MOV

(R$) R4

*SET UP FOR 4000 ITERATIONS

;SET BIT 12
*GET CONTENTS OF BREAK CONTROL

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 12

*READ CONTENTS OF BREAK CONTROL

‘WAS BIT 12 CLEARED

;BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
SSET BIT 13 IN BREAK CONTROL TO 1
SVERIFY THAT BIT 13 WAS SET
“CLEAR BIT 13
*VERIFY THAT BIT 13 WAS CLEARED

1958

007506

012767

000340

1960
1961
1962
1963

007522
007530
00753
007542

012767
012777
016703
012705

007574
004000
010124
004000

1964

:SET UP POINTER TO BREAK CONTROL

cTMMP

1%:

1952
1953
1954
1955
}329

1959

DHBCR,R3

*VERIFY THAT BIT 12 WAS CLEARED

007416

1945

;SET UP FOR 4000 ITERATIONS
“SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE

;BREAK CONTROL REGISTER DATA TEST
SSET BIT 12 IN BREAK CONTROL TO 1
SVERIFY THAT BIT 12 WAS SET
*CLEAR BIT 12

1933

1941

#4000, ICOUNT
#28 ESCAPE
#8711, 3DHSCR
#1000 RS

BEQ
HLT
BIC

}gg}

1938

SEQ 0048

MOV

MOV
MOV

1927
1928
1929
1930

1934

PAGE 38

007514

007546

012767

010513

004000

170262

010176
010164
010114

172:

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MO\

#4000, 1COUNT

SSET UP FOR 40CGO ITERATIONS

MOV

KS. (RS

SSET BIT 13

MOV
MOV
MOV
MOV

#28 ESCAPE
#81711,3DHSCR
DHRCR,R3
#7900 RS

SSET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO BREAK CONTROL
;BIT 13 WILL BE SET IN BREAK CONTROL

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=-78 10:02
1965
1966
1967
1968
1969

007550
007552
007554
007556
007560

1971
1972
1973
1974

007564
007566
007570
007572

1970

;g;g

007562

0075764

14:40

PAGE 39

1%:

MOV
CMP
BEQ
HLT
BIC

(R3) R4
RS.R4
1%
3
RS, (R3)

TST
BEQ
CLR
HLT

R4
2$
RS
3

011304
020504
001401
104003
040513

011304

005704
001402
005005
104003

104400

2%:

1977
1978
1979
1980

007576

012767

000340

1985
1986
1987

007612
007620
007626

012767
012777
016703

007664
004000
010034

1989

1990
1991

1992
1993
1994
1995
1996
1997
1998

1999

588?

007604

012767

004000

170172

010106

173:

010074
010024

MOV
MOV
MOV

#2%,5SCAPE
#BIT11,aDHSCR
DHBCR,R3

SSET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

RS,

;SET BIT 14

011304

MCV

007644
007646
007650
007652
007654
007656
007660

001401
104003
040513
011304
005704
001402
005005

BEQ
HLT
BIC
MOV
TST
BEQ
CLR

007664

104400

007642

007662

010000

MOV
MOV

020504

CMP

1%:

104003

2%:

HLT

SCOPE

#4000, 1COUNT

#10000,RS
(R3)

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

;BIT 14 WILL BE SET IN BREAK CONTROL

(R$) R4

:GET CONTENTS OF BREAK CONTROL

1%
3
RS, (R3)
(R3) ,R4
R4
2%
RS

;:BREAK CONTROL REGISTER ERROR
SCLEAR BIT 14
SREAD CONTENTS OF BREAK CONTROL
*WAS BIT 14 CLEARED

RS,Ré

‘WAS BIT 14 SET

;BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
*SET BIT 'S IN BREAK CONTROL TO 1
JVERIFY THAT BIT 15 WAS SET
:CLEAR BIT 15

SVERIFY THAT BIT 15 WAS CLEARED

007666

012767

000340

2010
2011
2012

007702
007710
007716

012767
012777
016703

007754
004000
007744

007732
007734
007736
007740

020504
001401
104003
040513

2020

:BREAK CONTROL REGISTER ERROR

;:DISABLE ALL

007640

010513

2008

2016
2017
2018
2019

*WAS BIT 13 CLEARED

#340,PS

MOV

012705

5889

2013
2014
2015

SREAD CONTENTS OF BREAK CONTROL

MOV

007632

007636

20
2C 3
LA
2005

2009

:BREAK CONTROL REGISTER ERROR
*CLEAR BIT 13

‘VERIFY THAT BIT 14 WAS CLEARED

1983

1988

SCOPE

(R$) ,R4

;GET CONTENTS OF BREAK CONTROL
‘WAS BIT 13 SET

;BREAK CONTROL REGISTER DATA TEST
*SET BIT 14 IN BREAK CONTROL TO 1
SVERIFY THAT BIT 14 WAS SET
*CLEAR BIT 14

}gg;

1984

MOV

SEQ 0049

007674

007722
007726
007730

007742

012767

012705
010513
011304

011304

004000

170102

010016

T174:

010004
007734

020000

MOV

#340,PS

;DISABLE ALL INTERRUPTS

MOV
MOV
MOV

#2$ ESCAPE
#81717,aDHSCR
DHBCR,R3

*SET UP TO ESCAPE TO NEXT TEST
‘MASTER CLEAR INTERFACE
SSET UP POINTER TO BREAK CONTROL

CMP
BEQ
HLT
BIC

RS.Ré
1%
3
R>, (R3)

MOV

MOV
MOV
MOV

MOV

#4000, 1COUNT

#20000 RS
RS, (R3S
(R$) .R4

(R$) R4

SSET UP FOR 4000 ITERATIONS

:BIT 15 WILL BE SET IN BREAK CONTROL
;SET BIT 15
*GET CONTENTS OF BREAK CONTKOL
‘WAS BIT 15 SET

;BREAK CONTROL REGISTER ERROR
*CLEAR BIT 1§

:READ CONTENTS OF BREAK CONTROL

CZDHA-C MACYT 30A(1052)10285AUG-78
15-MAY-78
CZDHAC.P11

2021

007744
007746
007750
007752
007754

14:40

PAGE 40

SEQ 0050

005704

TST

2%:

BEQ
CLR
HLT

SCOPE

JWAS BIT 15 CLEARED

2%
RS
3

;BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
sSET BIT 16 IN BREAK CONTROL TO 1
;VERIFY THAT BIT 16 WAS SET
;CLEAR BIT 16
;VERIFY THAT BIT 16 WAS CLEARED
012767
012767
012767
012777
016703
012705
010513
011304
020504
001401
104003
040513
011304
005704
001402
005005
104003

000340

170012
007726
007714
007644

175:

MOV

#340,PS

MOV

#2$ ESCAPE

MOV
MOV
MOV

#40000,RS
RS, (R3)

g?g

§2,R4

‘WAS BIT 16 SET

HLT

MOV

MOV
1%:

104400

2%:

;DISABLE ALL INTERRUPTS

JSET UP FOR 4000 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
JMASTER CLEAR INTERFACE
sSET UP POINTER TO BREAK CONTROL
;BIT 16 WILL BE SET IN BREAK CONTROL
JSET BIT 16

MOV

040000

#5000,
1 COUNT

#8]1T11,3DHSCR

DHBCR,R3
(R$) R4

BIC

RS,

TST

MoV
BEQ
CLR
HLT
SCOPE

“GET CONTENTS GF BREAK CONTROL
JBREAK CONTROL REGISTER ERROR

(R3)

;CLEAR BIT 16

(R$),R4

JREAD CONTENTS OF BREAK CONTROL

;WAS BIT

2%
RS
3

16 CLEARED

;BREAK CONTROL REGISTER ERROR

sBREAK CONTROL REGISTER DATA TEST

000340
004000
010134
004000
007564

167722

007636
007624
007554

T76:

100000

MOV

#340,PS

MOV
MOV
MOV

#2% ,ESCAPE
#81711,aDHSCR
DHBCR,R3

MOV

1%:

#4000, 1COUNT

MOV

#100000,RS

MOV

(R$) R4

MOV

[

012767
012767
012767
012777
016703
012705

g\NNWNNNN—‘
b —d =2
OO‘#NOO‘&NO&

SaaL3a3533350

S35 335335335353530

lelelolelalolelelolelels]

jelelelelelalelolelolels]

JSET BIT 17 IN BREAK CONTROL TO 1
;VERIFY THAT BIT 17 WAS SET
;CLEAR BIT 17
;VERIFY THAT BIT 17 WAS CLEARED

RS,

(R3)

cTMP
BEQ
HLT
BIC

RS, R4
1%
3
R5,(R3)

TST

HLT
SCOPE

MOV

BEQ
CLR

;SET UP
;SET UP
sMASTER
;SET UP

FOR 4000 ITERATIONS
TO ESCAPE TO NEXT TEST
CLEAR INTERFACE
POINTER TO BREAK CONTROL
;BIT 17 WILL BE SET IN BREAK CONTROL
JSET BIT 17

:GET CONTENTS OF BREAK CONTROL

‘WAS BIT 17 SET

;BREAK CONTROL REGISTER ERROR

*CLEAR BIT 17
JREAD CONTENTS OF BREAK CONTROL

(R$) ,R4

2%
RS

;DISABLE ALL INTERRUPTS

JWAS BIT

17 CLEARED

sBREAK CONTROL REGISTER ERROR

CZDHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC.P11

14:40

PAGE 41

SEQ 0051

sSILO STATUS REGISTER DATA TEST
;SET BIT O IN SILO STATUS TO 1
;VERIFY THAT BIT O WAS SET

;CLEAR BIT O

;VERIFY THAT BIT O WAS CLEARED
012767
012767
012767
012777

167632

007546
067534
007464

177:

$3%%

1%:

000700

MOV
MOV
MOV
MOV
MOV

#2$ ,ESCAPE
#BI1T11,aDHSCR
DHSSR,R3
#1.RS
RS’ (R3)

BIC

#700 R4

CMP
BEQ
HLT
BIC
MoV
BIC

2%:

;DISABLE ALL INTERRUPTS

#4000,
1 COUNT

(R$) RS

RS.R4
1%
4
RS, (R3)
(R3) ,R4
#700,R4

TST

Ré&

HLT
SCOPE

8EQ
CLR

2%
RS

JSET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST

sMASTER CLEAR INTERFACE

:SET UP POINTER TO SILO STATUS

;BIT O WILL BC SET IN SILO STATUS
JSET BIT O

;GET CONTENTS OF SILO STATUS
sCLEAR UNWANTED BITS

JWAS BIT 0 SET

:SILO STATUS REGISTER ERROR

;CLEAR BIT O
sREAD CONTENTS OF SILO STATUS
s CLEAR UNWANTED BITS
;WAS BIT O CLEARED
2SILO STATUS REGISTER ERROR

;SILO STATUS REGISTER DATA TEST
;SET BIT 1 IN SILO STATUS TO 1

;VERIFY THAT BIT 1 WAS SET
;CLEAR BIT 1

;VERIFY THAT BIT 1 WAS CLEARED

012767
012767
012767
012777
016703
012705

167532
007446
007434
007364

T100:

000700
NN

QSIS TN LS TN TN I NTANT N TN ST NN TN LAV AN T NT N 1S 1O T N1, N T8

#340,PS

MOV

000700

2097

MOV

1%:

000700

MOV

#340,PS

MOV
MOV
MOV

#28 ,ESCAPE
#81T11,aDHSCR
DHSSR,R3

MP
BEQ

RS,R4
1%

MOV

HLT

MOV

(R$) R4

BIC
TST

8EQ
CLR

2%:

#4000, 1COUNT

HLT
SCOPE

RS,
R4

(R3)

;DISABLE ALL INTERRUPTS

JSET UP FOR 4000 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
;JMASTER CLEAR INTERFACE
sSET UP POINTER TO SILO STATUS
;BIT 1 WILL BE SET IN SILO STATUS
;SET BIT 1
;GET CONTENTS OF SILO STATUS
;CLEAR UNWANTED BITS
sWAS BIT 1 SET
;SILO STATUS REGISTER ERROR
JCLEAR BIT 1
;READ CONTENTS OF SILO STATUS
. CLEAR UNWANTED BITS

2%
RS
4

sSILO STAT JS REGISTER DATA TEST

sSET BIT 2 IN SILO STATUS 10 1

;WAS BIT 1

CLEARED

;SILO STATUS REGISTER ERROR

CZDHA-CPMACY11 30A(10;2)1 23-AUG-78
CZDHAC.P11
15-MAY-78
10:02

14:40

PAGE 42

2133
2134
%}%2

;VERIFY THAT BIT 2 WAS SET
:CLEAR BIT 2
JVERIFY THAT BIT 2 WAS CLEARED

2137

010336

012767

000340

2139
2140
2141
2142
2143

010352
010360
010366
010372
010376

012767
012777
016703
012705
010513

010434
004000
007276
000004

042704
020504
Q01401
104004
040513

000700

042704
005704
001402
005005
104004
104400

000700

2138

2144

010344

010400

2145
2146
2147
2148
2149

010602
0104606
010410
010412
010414

2151
2152
2153
2154
2155
5;29

010420
010626
010426
010430
010432
010434

2150

SEQ 0052

010416

012767

011304

004000

167432

007346

T101:

007334
007264

MOV

#340,PS

:DISABLE
ALL INTERRUPTS

MOV
MOV
MOV
MOV
MOV

#28 ESCAPE
#8IT11,aDHSCR
DHSSR,R3
#4 RS
RS (R3)

*SET UP TO ESCAPE TO NEXT TEST
SMASTER CLEAR INTERFACE
:SET UP POINTER TO SILO STATUS
*BIT 2 WILL BE SET IN SILO STATUS
SSET BT 2

MOV

#4000, 1 COUNT

(R$) R4

sSET UP FOR 4000 ITERATIONS

*GET CONTENTS OF SILO STATUS

#700,R4
RS ,Ré
1$
4
RS, (R3)

;CLEAR UNWANTED BITS
:WAS BIT 2 SET

BIC
CMP
BEQ
HLT
BIC

#700.R4
R4
2%
RS
4

:CLEAR UNWANTED BITS
;WAS BIT 2 CLEARED

2% :

BIC
ST
BEQ
CLR
HLT
SCOPE

2158

MoV

(Rg).R4

;SILO STATUS REGISTER ERROR
:CLEAR BIT 2

;READ CONTENTS OF SILO STATUS

;SILO STATUS REGISTER ERROR

;SILO STATUS REGISTER DATA TEST

2159

SSET BIT 3 IN SILO STATUS TO 1

S}‘g%

JVERIFY THAT BIT 3 WAS CLEARED

2160
2161

SVERIFY THAT BIT 3 WAS SET
SCLEAR BIT 3

2164

010436

012767

000340

2166
2167
2168

0106452
010660
010466

012767
012777
016703

010534
004000
007176

2170

010476

010513

2165

2169

2171

010644

010472

010500

2172
2173
2174
2175
2176

010502
010506
010510
010512
010514

2178

010520

2177

2179

2180
2181
2182
5}32
2185
2186
2187
2188

010516
010524

010526
010530
0710532
010534

012767
012705

011304

004000

000700

042704

000700

005704

001402
005005
104004
104400

T1102:

007234
007164

000010

042704
020504
001401
104004
040513

011304

167332

007246

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV

#2% ,ESCAPE
#8IT11,aDHSCR
DHSSR,R3

*SET UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE
SSET UP POINTER TO SILO STATUS

MOV

RS, (R3)

SSET BIT 3

MOV
MOV

MOV

1%:

:SET UP FOR 4000 ITERATIONS

#10,RS

(R$).R4

:BIT 3 WILL BE SET IN SILO STATUS

*GET CONTENTS OF SILO STATUS

BIC
CMP
BEQ
HLT
BIC

#700,R4
RS.R4
1%
4
RS, (R3)

:CLEAR UNWANTED BITS
;WAS BIT 3 SET

BIC

#700.R4

;CLEAR UNWANTED BITS

MOV
TST
BEQ

2%:

#4000, 1COUNT

CLR
HLT
SCOPE

(RS, .R4

R4
2%

;SILO STATUS REGISTER ERROR
:CLEAR BIT 3

RS
4

;SILO STATUS REGISTER DATA TEST
SSET BIT & IN SILO STATUS TO 1
SVERIFY TrAT BIT & WAS SET
‘CLEAR BIT &

*READ CONTENTS OF SILO STATUS
;WAS BIT 3 CLEARED
;SILO STATUS REGISTER ERROR

CZOHA=-C MACY11 30A(1052) 028EAUG-78
CZDHAC .P11
15-MAY-78 10:

14:40

PAGE 43

S;gg

;VERIFY THAT BIT 4 WAS CLEARED

2191

010536

012767

000340

2193

010552

012767

010634

2192

2194

2195

2196

2197

2198

010544

010560

010566

010572

010576

010600

012767

012777
016703

012705

010513

011304

007146

004000

007064

007076

042704
020504
001401
104004
040513

000700

2205
2206
2207
2208
2209
5519

010620
010624
010626
010630
010632
010634

042704
005704
001402
005005
104004
104400

000700

011304

T1103:

007134

012767

000340

2220
2221
2222

010652
010660
010666

012767
012777
016703

010734
004000
006776

2224

010676

010513

2226
2227
2228
2229
223C

010702
010706
010710
010712
010714

042704
020504
001401
104004
040513

000700

2232
2233
2234
2235
2236

010720
010724
010726
010730
010732

042704
005704
001402
005005
104004

000700

2231

55%;

2239
2240
2241
2042
2043

*SET UP FOR 4000 ITERATIONS

*SET UP TO ESCAPE TO NEXT TEST

#MIT11,DHSCR

*MASTER CLEAR INTERFACE

MOV

#20,RS

:BIT & WILL BE SET IN SILO STATUS

MOV

(R$) .R4

DHSSR ,R3

ZSET UP POINTER TO SILO STATUS

RS, (R3)

‘SET BIT 4

*GET CONTENTS OF SILO STATUS

#700.R4
RS.R4
13
A
RS, (R3)

;CLEAR UNWANTED B;TS
:WAS BIT & SET

BIC
CMP
BEQ
HLT
BIC

#700.R4
R4
2
RS
4

;CLEAR UNWANTED BITS
:WAS BIT 4 CLEARED

2%:

BIC
ST
BEQ
CLR
HLT
SCOPE

MOV

(R$).R4

;SILO STATUS REGISTER ERROR
*CLEAR BIT 4

*READ CONTENTS OF SILO STATUS

:SILO STATUS REGISTER ERROR

*VERIFY THAT BIT S WAS CLEARED
010636

2225

#2$ ESCAPE

:DISABLE
ALL INTERRUPTS

#4000, 1 COUNT

:SILO STATUS REGISTER DATA TEST
:SET BIT 5 IN SILO STATUS TO 1
*VERIFY TRAT BIT S5 WAS SET
*CLEAR BIT 5

2218

2223

MOV

%3}9

2219

#340,PS

MOV

2212
2213
2214
2215
[4

MOV

ACY,

000020

010602
010606
010610
010612
010614

010616

167232

004000

2199
2200
2201
2202
2203

2204

SEQ 0053

010644

010672

0107200

010716

010734

012767
012705

011304

104400

004000

167132

007046

T104:

007034
006764

000040

MOV

#340,PS

MOV
MOV
MOV

#2$ ESCAPE
#81711,3DHSCR
DHSSR,R3

MOV

RS, (R3)

MOV

MOV
MOV

1$:

:DISASLE ALL INTERRUPTS

#5000, 1COUNT

“SET UP FOR 4000 ITERATIONS

#40.R5

:BIT S WILL BE SET IN SILO STATUS

(R$) R4

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
*SET UP POINTER TO SILO STATUS

‘SET BIT §

SGET CONTENTS OF SILO STATUS

BIC
cMP
BEQ
HLT
BIC

#700.R4
RS.R4
18
A
RS, (R3)

:CLEAR UNWANTED BITS
;WAS BIT 5 SET

BIC
TST
BEQ
CLR
HLT

#700.R%
R4
2$
RS
4

:CLEAR UNWANTED BITS
:WAS BIT 5 CLEARED

MOV

SCOPE

(R%) R4

;SILO STATUS REGISTER ERROR
‘CLEARBIT 5

;SILO STATUS REGISTER DATA TEST
“SET BIT 17 IN SILO STATUS TO 1
*VERIFY THAT BIT 17 WAS SET
*CLEAR BIT 17
SVERIFY Tr:AT BIT 17 WAS CLEARED

‘READ CONTENTS OF SILO STATUS

;SILO STATUS REGISTER ERROR

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=-78 10:02

22645

010736

012767

000340

2266

010744

012767

004000

2250

010772

012705

100000

2267
2248
22649
2251

2252

010752
010760
010766
010776

011000

012767
012777
016703
010513

011304

011034
004000
006676

2253
22564
2255
2256
2257

011002
011006
011010
011012
011016

042704
020504
001401
104004
04053

000700

2259
2260
2261
2262
2263

011020
011026
011026
011030
011032

042704
005704
001402
005005
104004

000700

2258

gggg

011016

011034

011304

14:40

167032

006746

PAGE 44

T105:

006734
006664

104400

2% :

011036
011044
011052
011060
011066
011072

012767
012767
012767
012777
016703
012705

000340
004000
011140
004000
006564
177766

011076

012713

011102

042713

2284
2285
2286
2287

011110
011112
011114
011116

020504
001401
104002
052713

2296

2297
2298
2299
2300

#28 ESCAPE
#B1711,aDHSCR
DHSSR,R3

MOV

RS, (R3)

“SET UP FOR 4000 ITERATIONS

*SET UP TO ESCAPE TO NEXT TEST
IMASTER CLEAR INTERFACE
“SET UP POINTER TO SILO STATUS

#100000.RS
(R$) R4

;8IT 17 WILL BE SET IN SILO STATUS

;SET BIT 17

:GET CONTENTS OF SILO STATUS

BIC
TMP
BEQ
HLT
BIC

#700.R6
RS.RS
1%
4
RS, (R3)

:CLEAR UNWANTED BITS
;WAS BIT 17 SET

BIC
ST
BEQ
CLR
HLT

#700.R4
R4
2%
RS
4

:CLEAR UNWANTED BITS
SWAS BIT 17 CLEARED

MOV

SCOPE

(R$) ,R4

;SILO STATUS REGISTER ERROR
“CLEAR BIT 17

*READ CONTENTS OF SILO STATUS

:SILO STATUS REGISTER ERROR

;JVERIFY THAT BIT O WAS SET

2273
2276
2275
2276
2277
2278
2279
2280
2281
2282

2290
2291
2292
2293
Sggg

MOV
MOV
MOV

:DISABLE ALL INTERRUPTS

#4000, ICOUNT

;LINE PARAMETER REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
:CLEAR BIT 0
*VERIFY THAT BIT O WAS CLEARED
*RESTORE BIT 0

gg;}

2288
2289

#340 PS

MOV

2266
2267
2268
2269
2270

2283

MOV

1%:

SEQ 0054

011106

011122
011126

011130
011132
011136
011140

011304

011304
022704

001403
012705
104002
104400

166732
006646
006634
006564

T106:

MOV
MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, I COUNT
#28 ,ESCAPE
#81711,aDHSCR
DHLPR,R3
2177766 RS

177767

MOV

#177767. (R3)

000001

BIC

#1,

000001

CMP
BEQ
HLT
8IS

RS.RG
1%
2
#1. (R3)

MOV

1%:

177767
177767
2%:

MOV
CMP

(R3)

(Rg),Ré

(R3) R4
8177767 R4

BEQ
MOV

2%
#177767.RS

HLT
SCOPE

:DISABLE ALL INTERRUPTS
:SET UP FOR 4000 ITERATIONS
$SET UP TO ESCAPE TO NEXT TEST
‘MASTER CLEAR INTERFACE
SSET UP POINTER TO LINE PARAMETER
; (RS)=EXPECTED DATA
*IN LINE PARAMETER REGISTER, 177766
*SET ALL READ/WRITE BITS
*IN LINE PARAMETER REGISTER
;CLEAR BIT 0

JGET CONTENTS OF LINE PARAMETER
*WAS BIT O CLEARED

:LINE PARAMETER REGISTER ERROR
SSET BIT 0

;WAS BIT O SET
; (RS)=EXPECTED DATA IN
‘LINE PARAMETER REGISTER, 177767
‘LINE PARAMETER REGISTER ERROR

;LINF PARAMETER REGISTER DATA TEST

SSET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
*CLEAR BIT 1
SVERIFY TrAT BIT 1 WAS CLEARED
JRESTORE BIT 1

CZDHA-CPMACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

14:40

PAGE 45

5%85

;VERIFY THAT BIT 1 WAS SET

2303

011142

012767

2305
2306
2307

011156
011164
011172

012767
012777
016703

2304

2308

2309
2310
2311
2312

2313

011150
011176

011202
011206

011212

004000

012705

177765

006530
006460

$SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
;SET UP POINTER TO LINE PARAMETER

MOV

#177765.RS

*SET UP FOR 4000 ITERATIONS
; (RS)=EXPECTED DATA

SIN LINE PARAMETER REGISTER.
SSET ALL READ/WRITE BITS
“IN LINE PARAMETER REGISTER
;CLEAR BIT 1

177765

#2,(R3)

020504
001401
104002
052713

000002

CMP
BEQ
HLT
BIS

RS.R4
1%
2
#2, (R3)

022704

177767

cTMMP

#177767 R4

;WAS BIT 1 SET

177767

MOV

#177767 RS

HLT

:(RS)=EXPECTED DATA IN
*LINE PARAMETER REGISTER, 177767
:LINE PARAMETER REGISTER ERROR

104002

011226

011304

011234

001403

MOV

BEQ

104400

28:

2326
2327
2328
2329

SCOPE

(R$) .R4

(R$) R4

:GET CONTENTS OF LINE PARAMETER
‘WAS BIT 1 CLEARED

;LINE PARAMETER REGISTER ERROR
;SET BIT 1

;LINE PARAMETER REGISTER DATA TEST
JSET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
*CLEAR BIT 2
‘VERIFY THAT BIT 2 WAS (_EARED

2330
5%%;

‘RESTORE BIT 2
JVERIFY THAT BIT 2 WAS SET

2333

011246

012767

000340

2335
2336
2337
2338
2339
2340
2341
2342

011262
011270
011276
(11302

012767
012777
016703
012705

011350
004000
006354
177763

011254

012767

004000

166522

006436

T110:

006424
006354

MOV

#340,PS

MOV
MOV
MOV
MOV

#28 _ESCAPE
#B1T11,3DHSCR
DHLPR,R3
#177763.R5

MOV

#4000, 1COUNT

011306

012713

177767

MOV

#177767, (R3)

011312

042713

000004

BIC

#4,

011320

020504

CMP

RS, R4

23%3

011316

2345
236
2347

011322
011324
011326

2356

#28 ESCAPE
#MIT11,3DHSCR
DHLPR R3

BIC

011242

2350
2351
2352
2353
2354

MOV
MOV
MOV

000002

C12705

238
2349

:DISABLE ALL INTERRUPTS

#4000, 1COUNT

042713

011304

011236

2344

#340,PS

#177767, (R3)

2321
2322
2323

233,

MOV

011230

011244

T107:

177767

2319

§§§§

011244
004000
006460

166626

006542

012713

011216
011216
011220
011222

2320

200340

012767

2314
2315
2316
2317

2318

SEQ 0055

011332
011334

011304

001401
104002
052713

011304
022704

011340
011342

001403
012705

011346
011350

104002
104400

000004

MOV

1%:

177767
177767
28:

(R3)

(R$) R4

BEQ
HLT
BIS

1%
2
#4, (R3)

BEQ
MOV

2%
#177767 RS

HLT
SCOPE

MOV
CMP

(R3) ,R4
8177767 R4

;DISABLE ALL INTERRUPTS

*SET UP FOR 4000 ITERATIONS

SSET UP TO ESCAPE TO NEXT TEST
‘MASTER CLEAR INTERFACE
JSET UP POINTER TO LINE PARAMETER
: (RS)=EXPECTED DATA
*IN LINE PARAMETER REGISTER, 177763
*SET ALL READ/WRITE BITS
SIN LINE PARAMETER REGISTER
;CLEAR BIT 2

:GET CONTENTS OF LINE PARAMETER

‘WAS BIT 2 CLEARED

JLINE PARAMETER REGISTER ERROR
SSET BIT 2

:WAS BIT 2 SET
: (RS)=EXPECTED DATA IN
*LINE PARAMETER REGISTER, 177767
*LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST

CZDHA-C MACY1 30A(1052)1028§AUG-78
CZOHAC.P11
15-MAY-78

14:40

PAGE 46

2357
2358
2359
2360
%%g

;SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
:CLEAR BT 4
:VERIFY THAT BIT 4 WAS CLEARED
:RESTORE BIT 4
:VERIFY THAT BIT &4 WAS SET

2363

011352

012767

000340

2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378

011366
011374
011402
011406

012767
012777
016703
012705

011454
004000
006250
177747

011412

012713

011416
011422
011424
011426
011430
011432
011436

042713
011304
020504
001401
104002
052713
011304

2364

2379

2380
2381
2382
2383
2380

011360

011440
011444
011446

011452
011454

012767

022704

001403
012705

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV
MOV

#2$ ESCAPE
#BIT17,@DHSCR
DHLPR,R3
#177747.RS

17776

MOV

#177767.(R3)

000020

BIC
MOV
(M
BEQ
HLT
BIS
MOV

#20,(R3)
(R3J,R&
RS.RG
1%
2
#20,(R3)
(R3S R4

:SET UP TO ESCAPE TO NEXT TEST
;MASTER CLEAR INTERFACE
;SET_UP POINTER TO LINE PARAMETER
; (RS)=EXPECTED DATA
:IN_LINE PARAMETER REGISTER, 177747
:SET ALL READ/WRITE BITS
:IN LINE PARAMETER REGISTER
:CLEAR BIT 4
:GET CONTENTS OF LINE PARAMETER
:WAS BIT 4 CLEARED

BEQ
MOV

28
#177767
RS

004000

166416

006332

T111:

006320
006250

000020

1s:

177767
177767

104002
104400

>$:

H177767.Ré

HLT
SCOPE

011456

012767

000340

2395
2396
2397

011472
011500
011506

012767
012777
016703

011560
004000
006144

(011464

011512

012767

012705

004000

166312

006226

T112:

;WAS BIT 4 SET
: (RS)=EXPECTED DATA IN
:LINE PARAMETER REGISTER, 177767
:LINE PARAMETER REGISTER ERROR

006214
006144

177727

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV

428 ESCAPE
#BITT1, @DHSCR
DHLPR,R3

:SET UP TO ESCAPE TO NEXT TEST
:MASTER CLEAR INTERFACE
;SET_UP POINTER TO LINE PARAMETER

MOV

#4000, 1COUNT

#177787.RS

2400
2401
2402
2603
2604
2605
2406
2607

011516

012713

177767

MOV

#177767,(R3)

011522
011526
011530
011532
011534
011536

042713
011304
020504
001401
104002
052713

000040

BIC
MOV
(M
gFQ
HLL
BIS

#40,(R3)
(R3),R&
RS.R&
18
2
#40 (R3)

2609
2610

011544
011550

022704
007403

177767

(MP
BEQ

#177767,Ré
2%

26411

:LINE_PARAMETER REGISTER ERROR
:SET BIT 4

:VERIFY THAT BIT 5 WAS SET

2393

2408

:SET UP FOR 4000 ITERATIONS

:CLEAR BIT 5
:VERIFY THAT BIT 5 WAS CLEARED
;RESTORE BIT §

2391

2398

#4000, 1COUNT

;LINE PARAMETER REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S

2388
2389
2390

2399

MOV

2386
2387

2394

SEQ 0056

011542

011304

011552

012705

000040

177767

1$:

MOV

(3
,R&

KT77767
KS

:SET UP FOR 4000 ITERATIONS

; (RS)=EXPECTED DATA

:IN_LINE PARAMETER REGISTER, 177727

:SET ALL READ/WRITE BITS
:IN LINE PARAMETER REGISTER
:CLEAR BIT S
:GET CONTENTS OF LINE PARAMETER
:WAS BIT 5 CLEARED

:LINE_PARAMETER REGISTER ERROR
:SET BIT S
;WAS BIT S SET
: (RS)=EXPECTED DATA IN

;LINE PARAMETER REGISTER,

177767

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78
10:02

2413
gz}g

011556
011560

14:40

104002
104400

PAGE 47

2%:

2616
2617
2418
2419
2420

012767
012767

011622

012713

2633
2434
2435
2436
2437
2438

011626
011632
011634
011636
011640
011642
011646

042713
011304
020504
001401
104002
052713
011304

2640
2441

011654
011656

001403
012705

011662

104002

2439

2642
2443

gzzg

011576
011604
011612
011616

011650

011664

012767
012777
016703
012705

022704

000340
004000

011664
004000
006040
177667
)
177767

166206
006122
006110
006040

T113:

000100

1%:

177767

#340,PS
#6000, ICOUNT

MOV

#177767, (R3)

BIC
MOV
CMP
BEQ
HLT
BIS
MOV

#100, (R3)
(R3) R4
RS.R4
1%
2
#100, (R3)
(R3) ,R4

CMP

BEQ
MOV

177767

104400

2%:

HLT

SCOPE

#2$ ,ESCAPE
#8IT11,3DHSCR
DHLPR,R3
#177667 ,RS

#177767 R4
2%
#177767 RS

:DISABLE ALL INTERRUPTS
;SET UP FOR 4000 ITERATIONS

;SET UP TO ESCAPE TO NEXT TEST
;MASTER CLEAR INTERFACE
:SET UP POINTER TO LINE PARAMETER
; (RS)=EXPECTED DATA
]
JIN LINE PARAMETER REGISTER, 177667
:SET ALL READ/WRITE BITS
;IN LINE PARAMETER REGISTER
;CLEAR BIT 6

;GET CONTENTS OF LINE PARAMETER
;WAS BIT 6 (LEARED
:LINE PAAMETER REGISTER ERROR
:SET BIT 6

:WAS BIT 6 SET
:(RS)=EXP-CTED DATA IN

:LINE PARAMETER REGISTER, 177767
;LINE PARAMETER REGISTER ERROR

;LINE PARAMETER REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
:CLEAR BIT 7
IVERIFY THAT BIT 7 WAS CLEARED
;RESTORE BIT 7

522}

2467
2468

MoV
MOV

MOV
MOV
MOV
MOV

2446
2447
2648
2449
2450

2653
2454
2455
2456
2457
2458
2459
2660
2461
2662
2663
2464
2665
2666

:LINE PARAMETER REGISTER ERROR

JVERIFY THAT BIT 6 WAS SET
011562
011570

2425
2426
2627
2428
2429
2630
2431
2432

:LINE PARAMETER REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
;CLEAR BIT 6
JVERIFY THAT BIT 6 WAS CLEARED
:RESTORE BIT 6

525;

2423
2424

HLT
SCOPE

SEQ 0057

;VERIFY THAT BIT 7 WAS SET
011666
011674
011702
011710
011716
011722

012767
012767
012767
012777
016703
012705

000340
004000
011770
004000
005734
177567

011726

012713

011732
011736
011740
011742
011744
011746
011752

042713
011304
020504
001401
104002
052713
011304

MOV
MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, I COUNT
#2% ESCAPE
#81T11,aDHSCR
DHLPR,R3
#177567 RS

177767

MOV

#177767. (R3)

000200

BIC
MOV
CMP
BFQ
HLT
BIS
MOV

#4200, (R3)
(R3) ,R4
RS.R4
1%
2
#2290, (R3)
(R3) R4

000200

166102
006016
006004
005734

T114:

:DISABLE ALL INTERRUPTS
;SET UP FOR 4000 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
JMASTER CLEAR INTERFACE
:SET UP POINTER TO LINE PARAMETER
;(RS)=EXPECTED DATA
s IN LINE PARAMETER REGISTER, 177567
;SET ALL READ/WRITE BITS
;IN LINE PARAMETER REGISTER
;CLEAR BIT 7
:GET CONTENTS OF LINE PARAMETER
:WAS BIT 7 CLEARED
;LINE PARAMETER REGISTER ERROR

;SET BIT 7

CZOHA~C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC.P11

2469
¢470
2471
2472
2473
2474
2475
2476
2677
2678

011754
011760
01176¢

022704
001403
012705

011766
011770

104002

14:40

PAGE 48

177767

104400

2%:

SEQ 0058

CTMP
BEQ
MOV

#177767 R4
2
#177767.RS

;WAS BIT 7 SET

HLT

"LINE PARAMETER REGISTER ERROR

SCOPE

: (RS)=EXPECTED DATA IN

*LINE PARAMETER REGISTER, 177767

;LINE PARAMETER REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S

*CLEAR BIT 10
SVERIFY THAT BIT 10 WAS CLEARED

2479

2480
2481

*RESTORE BIT 10

*VERIFY THAT BIT 10 WAS SET

012026

012767
012767
012767
012777
016703
012705

000349
004000
012074
004000
005630
177367

012032

012713

012036
012042
012044
012046
012050
012052

042713
011304

011772

165776

0057"2

T11S:

005700

005630

MOV

#28 ESCAPE

MOV

#4000, 1 COUNT

#81711,30DHSCR

DHLPR,R3
#177367.RS

177767

MOV

8177767, (R3)

000400

BIC
MOV

#400, (R3)
(R3) ‘R4

é?fi
1%

177767

012072
012074

#340,PS

MOV
MOV
MOV

000400

012705

MOV

177767

104002
104400

HLT

;DISABLE ALL

INTERRUPTS

*SET UP FOR 4000 ITERATIONS

“SET UP TO ESCAPE TO NEXT TEST

*MASTER CLEAR INTERFACE

JSET UP POINTER TO LINE PARAMETER
; (RS)=EXPECTED DATA

“IN LINE PARAMETER REGISTER, 177367
“SET ALL READ/WRITE BITS

*IN LINE PARAMETER REGISTER

*CLEAR BIT 10
*GET CONTENTS OF LINE PARAMETER

?2,R4

‘WAS BIT 10 CLEARED

JLINE PARAMETER REGISTER ERROR

BIS

#400, (R3)

*SET BIT

2177767 R4

;WAS BIT 10 SET

MOV

(R3) ‘R4

BEQ
MOV

2%
#177767 RS

HLT

SCOPE

:(RS)=EXPECTED DATA IN

*LINE PARAMETER REGISTER, 177767

‘LINE PARAMETER REGISTER ERROR

:LINE PARAMETER REGISTER DATA TEST
*SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER
*CLEAR BIT 11
*VERIFY THAT BIT 11 WAS CLEARED
*RESTORE BIT

)
—
Y
g
[

[aSLANTANT
N TN 15 0)
Payarargirit
@ )

olelelelele]

;VERIFY THAT BIT

012142

012146

012150

000340

165672

T116:

J 1S

WAS SET

MOV

#340,PS

:DISABLE ALL

176767

MOV
MOV
MOV
MOV

#28 . ESCAPE
#81711,3DHSCR
DHLPR,R3
176767 RS

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
;SET UP POINTER TO LINE PARAMETER
J(RS)=EXPECTED DATA

177767

MOv

#177767,(R3)

001000

BI(
MOv
C(MP

#1000, (R3)
n?) R4
R5,RS

005606

005574
005524

MOV

#4000, 1COUNT

INTERRUPTS

“SET UP FOR 4000 ITERATIONS

JIN LINE PARAMETER REGISTER, 176767
JSET ALL READ/WRITE BITS
;IN LINE PARAMETER REGISTER
;CLEAR R'Y 11
JGET C(ONTENTS OF _INE PARAMETER
JWAS BIT 11 CLEARED

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

2525
2526
2527

012152
012154
012156

2529

012164

2528

2530
2531
2532
2533

gggg

001401
104002
052713

101000

022704

177767

012162

011304

012170
012172

001403
012705

012176

012200

14:40

PAGE 49

1%:

BEQ
HLT
BIS

1%
2
#1000, (R3)

;LINE PARAMETER REGISTER ERROR
SSET BIT 11

CMP

177767 R4

;WAS BIT 11 SET

MOV

BEQ
MOV

177767

104002

104400

2%:

SEQ 0059

(R3) R4

23
#177767 .RS

HLT

SCOPE

; (RS)=EXPECTED DATA IN
:LINE PARAMETER REGISTER, 177767
*LINE PARAMETER REGISTER ERROR

2536
2537

;LINE PARAMETER REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S

5225

:VERIFY THAT BIT 12 WAS SET

2538
2539
2540

*CLEAR BIT 12
*VERIFY THAT BIT 12 WAS CLEARED
*RESTORE BIT 12

2543

012202

012767

000340

2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558

012216
012224
012232
01223%

012767
012777
016703
012705

012304
004000
005420
175767

012242

012713

012246
012252
012254
012256
012260
012262
012266

042713
011304
027504
001401
104002
052713
011304

2560

012274

25644

2559

012210

012767

004000

#340,PS

:DISABLE ALL INTERRUPTS

#2%.ESCAPE
#1711 ,aDHSCR
DHLPR,R3
#175767.RS

SSET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
SSET UP POINTER TO LINE PARAMETER
; (RS)=EXPECTED DATA
“IN LINE PARAMETER REGISTER, 175767
*SET ALL READ/WRITE BITS
*IN LINE PARAMETER REGISTER
:CLEAR BIT 12
*GET CONTENTS OF LINE PARAMETER
‘WAS BIT 12 CLEARED

177767

MOV

#177767, (R3)

002000

BIC
MOV
(M
BEQ
HLT
BIS
MOV

#2000, (R3)
(R3) R4
RS,R&
1%
2
#2000, (R3)
(R3’ R4

005470
005420

002000

177767

2561

012276

012705

177767

2563
322?

012302
012306

104002
04400

MOV
MOV
MOV
MOV

CMP

#177767 R4

MOV

#177767.R5S

BEQ

2% :

2566
2567
2568
2569
2570

HLT
SCOPE

*SET UP FOR 4000 ITERATIONS

:LINE PARAMETER REGISTER ERROR
SSET BIT 12

:WAS BIT 12 SET

: (RS)=EXPECTED DATA IN

SLINE PARAMETER REGISTER,

177767

SLINE PARAMETER REGISTER ERROR

:LINE PARAMETER REGISTER DATA TEST
*SET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
JLLEAR BIT 13
;VERIFY THAT BIT 13 WAS CLEARED
JRESTORE BIT 13

52;}

JVERIFY THAT BIT 13 WAS SE~

2573

012306

012767

000340

2575
2576
2577
2578
2579
2580

012322
012330
01233
012342

012767
012777
016703
012705

012410
004000
005314
173767

0123%6

012713

25764

MOV

#4000, 1COUNT

022704

2562

T117:

MOV

012270

001403

165566

005502

012314

012767

004000

1777¢7

165462

005376
005364
005314

T120:

MOV

#3.0,PS

;DISABLE ALL

MOV
MOV
MOV
MOV

#2% ESCAPE
#M]T11,aDHSCR
DHLPR,R3
#173767 RS

JSET UP TO ESCAPE TO NFXT TEST
;JMASTER CLEAR INTERFACE
;SET UP POINTER TO LINE PARAMETER
:(RS)=EXPECTED DATA
JIN LINE PARAMETER REGISTER, 173767
:SET ALL READ/WRITE BITS

MOV

04006.ICOUNT

#177767,(R3)

INTERRUPTS

JSET UP FOR 4000 ITERATIONS

CIDHA=-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC.P11

2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2596
2595
2596
2597
2598
2599

2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2015
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628

2629
2630
2631
2632
2633
2634
2635
2636

012352
012356
012360
012362
012364
012366
012372
012374
012400
012402

012705

012406
012410

1064002
104400

042713
011304
020504
001401

14:40

PAGE S0

004000

8IC
MOV

;CLEAR BIT 13
JGET CONTENTS OF LINE PARAMETER

JLINE PARAMETER REGISTER ERROR

CMP

gl???b?,Ré

JWAS BIT 13 SET

MOV

#177767.RS

; (RS)=EXPECTED DATA IN

HLT

*LINE PARAMETER REGISTER ERROR

HLT

BIS
MOV

177767
177767

2%:

;IN_LINE PARAMETER REGISTER

#4000, (R3)
(R3) ,R4

ggg
004000

SEQ 0060

?g.R4

#4000, (R3)
(R3) R4

JWAS BIT 13 CLEARED
JSET BIT 13

‘LINE PARAMETER REGISTER, 177767

sLINE PARAMETER REGISTER DATA TEST

JSET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
;CLEAR BIT 14
JVERIFY THAT BIT 14 WAS CLEARED

JRESTORE BIT 14
SVERITY THAT BIT 4 WAS SET
012412
012420
012426
012434
012442
012446

012767
012767
012767
012777
016703
012705

000340
004000
012514
004000
005210

012452

012713

177767

MOV

177767, (R3)

012456
012462
012464
012466
012470
012472
(12476
012500
012504
012506

042713

010000

BIC

#10000, (R3)

é?fi

22,q4

‘WAS BIT

:LINE PARAMETER REGISTER ERROR

012512
012514

165356
005272
005260
00521¢C

T121:

#4000, 1COUNT

MOV

DHLPR ,R3

MOV

177767
177767

104002

104400

2%:

#340,PS

MOV

MOV
MOV

167767

010000

012705

MOV

HLT

#2$ ESCAPE
#31717,aDHSCR
8167767
RS

(R3) RS,

BIS

#10000, (R3)

cMP

#177767 R4

MOV

(R3) RS,

MOV

2%
177767 RS

g%éPE

;DISABLE ALL INTERRUPTS
;SET UP FOR 4000 ITERATIONS
JSET UP TO ESCAPE TO NEXT TEST
JMASTER CLEAR INTERFACE
;SET UP POINTER TO LINE PARAMETER
J(R5)=EXPECTED DATA

;IN LINE PARAMETER REGISTER, 167767
sSET ALL READ/WRITE BITS
;IN_LINE PARAMETER REGISTER
*CLEAR BIT 14

SGET CONTENTS OF LINE PARAMETER
14

CLEARED

SSET BIT 14

;WAS BIT 14 SET
; (RS)=EXPECTED DATA IN

JLINE PARAMETER REGISTER, 177767
JLINE PARAMETER REGISTER ERROR

JLINE PARAMETER REGISTER DATA TEST
JSET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TU 1S
JCLEAR BIT 15

JVERIFY THAT BIT 75 WAS (LEARED
JRESTORE BIT 15

JVERIFY THAT BIT 15 WAS SET

(12516
012524
(12532
012540

165252

012620
004000

005166
005154
0051C4

T122:

MOV

#340,PS

MOV

#2¢ ESCAPE

MOV

#4000, 1COUNT

#81717.aDHSCR

;DISABLE ALL

INTERRUPTS

JSET UP FOR 4000 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
JMASTER CLEAR INTERFACE

CZOHA-C MACY11 30A(1052)
23-ALG-78
CZDHAC.P11
15-MAY-78 10:02

14:40

PAGE

SEQ 0061

012546
012552

01€703
012705

005104

157767

MOV
MOV

DHLPR,R3
#157767°RS

012556

012713

177767

MOV

#177767. (R3)

012562
012566
012570
012572
012574
012576

042713
011304

020000

BIC
MOV
CMP

#20000, (R3)
(R3) R
RS R4

BIS
MOV

#20000, (R3)
(R3) ,Ré

BEQ
MOV

2$
#177767.RS

020000

*%:

CMP

177767

012612

012705

012616
012620

104002
104400

BEQ
HLT

177767

2%:

1%
2

#177767
.R4

:SET UP POINTER TO LINE PARAMETER
: (RS)=EXPECTED DATA
:IN_LINE PARAMETER REGISTER, 157767

:SET ALL READ/WRITE BITS
;IN_LINE PARAMETER REGISTER
;CLEAR BIT 15
;GET CONTENTS OF LINE PARAMETER

JWAS BIT 15 CLEARED

;LINE PARAMETER REGISTER ERROR
JSET BIT 15

JWAS BIT 15 SET
s (RS)=EXPECTED DATA IN
JLINE PARAMETER REGISTER,

HLT

177767

;LINE PARAMETER REGISTER ERROR

SCOPE

;LINE PARAMETER REGISTER DATA TEST
JSET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S
;CLEAR BIT 16
JVERIFY THAT BIT 16 WAS CLEARED

JRESTORE BIT

;VERIFY THAT BIT 16 WAS SET

012622
012630
012636
012644
012652
012656

000340
004000
012724
004000
005000

165146

T123:

MOV

#340,PS

;DISABLE ALL INTERRUPTS

#2$. ESCAPE
#1717, aDHSCR
DHLPR,R3
#137767.R5

JSET UP TO ESCAPE TO NEXT TEST

137767

MOV
MOV
MOV
MOV

005062
005050
005000

MOV

#4000, 1COUNT

012662

012713

177767

MOV

#177767. (R3)

012666

040000

BIC
MOV

#40000, (R3)
(R3) .Ré

012716

042713
011304
020504
001401
104002
052713
011304
022704
001403
012705

012722
012724

104002
104400

01267
012674
012676

040000

1%:

177767

CMP
BEQ
HLT

BIS
MOV

cTMP

BEQ
MOV

177767

2%:

RS RS,
1%
2

c4oooo (RX)
(R3)

#177767 R4
28
#177767.RS

;SET UP FOR 4000 ITERATIONS

JMASTER CLEAR INTERFACE
;SET UP POINTER TO LINE PARAMETER
;(RS)=EXPECTED DATA
;IN _LINE PARAMETER REGISTER,

JWAS BIT 16 CLEARED

sLINE PARAMETER REGISTER ERROR
JSET BIT 16
JWAS BIT

16 SET

s (RS)=EXPECTED DATA [N

JLINE PARAMETER REGISTER, 177767
JLINE PARAMETER REGISTER ERROR

HLT
SCOPE

;LINE PARAMETER REGISTER DATA TEST
JSET ALL READ/WRITE BITS IN LINE PARAMETER REGISTER TO 1S

:CLEAR BIT 17

VERIFY

THAT BIT

:RESTORE BIT 17

SVERIFY TrAT BIT

137767

sSET ALL READ/WRITE BITS
;IN_LINE PARAMETER REGISTER
;CLEAR BIT 16
sGET CONTENTS OF L INE PARAMETER

)

17 WAS CLEARED

17 wAS SET

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

2693

012726

012767

012742
012750
012756

012767
012777
016703

269

012736

2698

012762

2695
2696
2697
2699
2700
2701
2702
2703
2704
2705
2706

013004

2708

013012

2707

2709

2710
2711
2712
2713
S;}é

000340

012767

004000

012705

077767

013030
004000
004674

14:40

165042

004756

PAGE S2

T124:

004744
004674

SEQ 0067

MOV

#3460 PS

;:DISABLE ALL INTERRUPTS

MOV
MOV
MOY

#2$ ESCAPE
#B1T11,3DHSCR
DHLPR,R3

“SET UP TO ESCAPE TO NEXT TEST
“MASTER CLEAR INTERFACE
;SET UP POINTER TO LINE PARAMETER

MOV
MOV

#4000, 1COUNT

SSET UP FOR 4000 ITERATIONS

#77767 RS

: (RS)=EXPECTED DATA

SIN LINE PARAMETER REGISTER, 77767
*SET ALL READ/WRITE BITS
SIN LINE PARAMETER REGISTER
*CLEAR BIT 17
SGET CONTENTS OF LINE PARAMETER
*WAS BIT 17 CLEARED

012766

012713

177767

MOV

#177767. (R3)

012772
012776
013000
013002

042713
011304
020504
001401

100000

BIC
MOV
CMP
BEQ

#100000, (R3)
(R3) R4
RS,R4
1%

013006

052713

100000

BIS

#100000., (R3)

013014

022704

177767

CMP

#177%67.R4

;WAS BIT 17 SET

: (RS)=EXPECTED DATA IN
*LINE PARAMETER REGISTER, 177767
;LINE PARAMETER REGISTER ERROR

104002

011304

013020
013022

001403
012705

013026
013030

104002
104400

HLT

MOV
BEQ
MOV

177767
2%:

HLT
SCOPE

:LINE PARAMETER REGISTER ERROR

“SET BIT 17

(R3) R4

2$
#177767 RS

2716
2717
2718

;BREAK CONTROL REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
‘CLEAR BIT 0

2720

*RESTORE BIT 0

2719

*VERIFY

S?%}

2723
2726
2725
2726
2727

JVERIFY THAT BIT 0 WAS SET
013032
013040
013046
0130564
013062

012767
012767
012767
012777
016703

000340
004000
013134
004000
004600

012713

177777

013076

042713

000001

273
2735
2736
2737

013106
013106
013110
013112

020504
001401
104003
052713

000001

2739

013120

022704

177777

2728

2729
2730
2731
2732

2733

2738

2760
2741
2742

2743

g;zg

2746
2747
2748

THAT BIT 0 WAS CLEARED

013066

013102

013116

013126
013126

013132
01313¢

012705

011304

001403
012705

104003

104400

164736
004652
004640
004570

T125:

177776

MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, 1 COUNT
#2$ ESCAPE
#1711, aDHSCR
DHBCR,R3

MOV

#177777. (R3)

BIC

#1,

M
BEQ
HLT
BIS

RS, R4
1%
3
#1, (R3)

cMP

#177777 R4

MOV

MOV
1%:

MOV
BEQ
MOV

177777
2% :

HLT

SCOPE

177776 RS
(R3)

(R3) R4

(R$) R4

23
#177777.RS

:DISABLE ALL INTERRUPTS
*SET UP FOR 4000 ITERATIONS
“SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
;SET UP POINTER TO BREAK CONTROL

; (RS)=EXPECTED DATA

<IN BREAK CONTROL REGISTER,
:SET ALL READ/WRITE BITS
*IN BREAK CONTROL REGISTER
;CLEAR BIT 0

177776

;GET CONTENTS OF BREAK CONTROL
‘WAS BIT O CLEARED

;BREAK CONTROL REGISTER ERROR
;SET BIT 0

;WAS BIT 0 SET
; (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
*BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
*SET ALL nEAD/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
CILEAR BIT 1

CZDHA-C MACY
T 30A(1052)
28-AUG-78
15-MAY-78 10:02
CZDHAC.P11

14:40

PAGE 53

2749
2750

SEQ 0063

JVERIFY THAT BIT 1 WAS CLEARED

NN NNIN

[elelelelele]

;RESTORE BIT 1
JVERIFY THAT BIT 1 WAS SET

013232

042713
011304
020504
001401
104003
052713
011304
022704
001403
012705

013236
013240

1040902
104400

012713

SLLL0

000340
004000
013240
004000
0044 74

233535305

012767
012767
012767
012777
016703
012705

164632

T126:

MOV

#340 ,PS

;DISABLE ALL INTERRUPTS

MOV

#5000, 1COUNT

*SET UP FOR 4000 ITERATIONS

MOV

#8I1T11,aDHSCR

*MASTER CLEAR INTERFACE

MOV

#177775.RS

: (RS)=EXPECTED DATA

177777

MOV

#177777. (R3)

000002

BIC

#2, (R3)

ggg

§2,R4

HLT
BIS

3
#2,(R3)

g?fi

8177577 R4

004546
004534
004464

MOV

177775

MOV

000002

1%:

177777

2%:

MOV

#28 ESCAPE

SSET UP TO ESCAPE TO NEXT TEST

DHBCR R3

(R$) R

(R3)5R4

MOV

2%
#177777 RS

g%ng

;SET UP POINTER TO BREAK CONTROL

*IN BREAK CONTROL REGISTER,
“SET ALL READ/WRITE BITS

177775

*IN BREAK CONTROL REGISTER

;CLEAR BIT 1

:GET CONTENTS OF BREAK CONTROL

‘WAS BIT 1

CLEARED

;BREAK CONTROL REGISTER ERROR
;SET BIT 1
;WAS BIT

SET

;(RS)=EXPECTED DATA IN

;BREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTeR ERROR

;BREAK CONTROL REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
;CLEAR BIT 2
;VERIFY THAT BIT 2 WAS CLEARED

JRESTORE BIT 2

;VERIFY THAT BIT 2 WAS SET

013242
013250
013256
013264
013272
013276

012767
012767
012767
012777
016703
012705

177773

013302

012713
042713

164526

004442
004430
004360

r1127:

MLV
MOV

#MIT11,aDHSCR
DHBCR,R3

#177773.RS

177777

MOV

#177777.(R®)

000004

BIC

ggg

?2,R4

MOV

1%:

177777

104003
104400

#340,PS
#6000, ] COUNT
#2% _ESCAPE

MOV

000004

012705

MOV
MOV
MOV

177777

HLT

(K3)

(R$) R4

*MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

; (RS)=EXPECTED DATA

:IN BREAK CONTROL REGISTER, 177773

$SET ALL READ/WRITE BITS
IN BREAK CONTROL REGISTER
;CLEAR BIT 2

;GET CONTENTS OF BREAK CONTROL

‘WAS BIT 2 CLEARED

;BREAK CONTROL REGISTER ERROR

BIS

¥4,

5?8

#177777 R4

;WAS BIT 2 SET

MOV

¥177777 RS

;(R5)=EXPECTED DATA IN

HLT

MOV

(R3)

;DISABLE ALL INTERRUPTS
SSET UP FOR 4000 ITERATIONS
*SET UP TO ESCAPE TO NEXT TEST

(R$) R4

SSET BIT 2

;BREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

CZDHA-CPT?CY11 30A(1052)
23-AUG-78
CZDHAC
15-MAY-78 10:02

2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817

14:40

PAGE 54

SEQ 0064

;BREAK CONTROL REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S

;CLEAR BIT 3

;VERIFY THAT BIT 3 WAS CLEARED

;RESTORE BIT 3

;VERIFY THAT BIT 3 WAS SET

012767
012767
012767
012777
016703
012705

000340
004000
013450
004000
004264

012713

1664422

004336
004324
004254

T1130:

MOV

#340,PS

MOV
MOV

#28 ESCAPE
#81711,30HSCR

MOV

177767

#4000,
1 COUNT

DHBCR,R3

;DISABLE ALL INTERRUPTS

JSET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
sMASTER CLEAR INTERFACE
:SET _UP POINTER TO BREAK CONTROL

MOV

#177767 ,RS

177777

MOV

#177777,(R3)

042713
011304
020504
001401

000010

BIC
MOV

#10, (R3)
(R3) ,R4

qg.n4

*WAS BIT 3 CLEARED

052713
011304
022704
001403
012705

000010

g?g

3
#10, (R3)
(R3) ,R&

:BREAK CONTROL REGISTER ERROR
“SET BIT 3

1727777

HLT
BIS
MOV

177777

MOV

2%
#177777 ,R5

g%aPE

104003

ggg
1%:

104003
104400

Pt ¥

#177777 R4

; (R5)=EXPECTED DATA
s IN BREAK CONTROL REGISTER, 177767
sSET ALL READ/WRITE BITS
s IN BREAK CONTROL REGISTER
;CLEAR BIT 3
;GET CONTENTS OF BREAK CONTROL

;WAS BIT 3 SET
; (RS)=EXPECTED DATA IN

;BREAK CONTROL REGISTER, 177777

sBREAK CONTROL REGISTER ERROR

sBREAK CONIROL REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
;CLEAR BIT 4

SVERIFY THAT BIT & WAS CLEARED

SRESTORE BIT 4
;VERIFY THAT BIT 4 WAS SET

013512
013516

012767
012767
012767
012777
016703
012705

000340

012713

164316

004232
004220
004150

T131:

MOV

#340,PS

MOV
MOV

#2$
. ESCAPE
#81717,3DHSCR

MOV

DHBCR ,R3

MOV

#177787
RS

177777

MOV

#177777.(R3)

000020

8IC
MOV

#20,(R3)
(13) R4

177757

g?g

000020

013544

#4000, 1COUNT

177777

1%:

HLT

BIS
MOV

CMP

;DISABLE ALL INTERRUPTS

;SET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
JMASTER CLEAR INTERFACE
;SET UP POINTER TO BREAK CONTROL
s (RS)=EXPECTED DATA
s IN BREAK CONTROL REGISTER, 177757
JSET ALL READ/WRITE BITS
s IN BREAK CONTROL REGISTER
;CLEAR BIT 4
sGET CONTENTS OF BREAK CONTROL

?;,R4

cWAS BIT 4 CLEARED

;BREAK CONTROL REGISTER ERROR

5;77777,R4

;WAS BIT &4 SET

#20, (R3)
(R3) R4

JSET BIT 4

CZDHA-CPHACYH 30A(1052)
285AUG-78
CZDHAC.P11
15-MAY-78 10

2861

013546

012705

2863
gggg

013552
013554

104003
104400

2862

14:40

PAGE 55

177777
2$:

2866
2867
2868
2869
2870

SEQ 0065

MOV

#177777.RS

; (RS)=EXPECTED DATA IN

HLT
SCOPE

;BREAK CONTROL REGISTER ERROR

:BREAK CONTROL REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
:CLEAR BIT 5
SVERIFY THAT BIT S WAS CLEARED
*RESTORE BIT §

gg;}

SVERIFY THAT BIT 5 WAS SET

2873

013556

012767

000340

2875
2876
2877

013572
013600
013606

012767
012777
010703

013660
004000
004054

2879
2880

013616

012713

177777

MOV

#177777.(R3)

2882
2883
2884
2885
2886
2887

013622
013626
013630
013632
013634
013636

042713
011304
020504
001401
1046003
052713

000040

BIC
MOV
CMP
BEQ
ALT
BIS

#40, (R3)
(R3) ,R4
RS,R4
1%
3
#40, (R3)

2889
2890
2891

‘013644
013650
013652

022704
001403
012705

177777

cMP
BEQ
MOV

#177777 R4
2
#177777.R5

013656
013660

104003
104400

HLT
SCOPE

2874

2878

2881

2888

2892
2893
533?

013564

013612

013642

012767

012705

011304

004000

164212

004126

T132:

004114
u04044

177737

000040

1%:

177777
2% :

2900

012767

000340

2905
2906
2907

013676
0137204
013712

012767
012777
016703

013764
004000
003750

2914

2915
2916

MOV
MOV
MOV

#28 ,ESCAPE
#81T11,aDHSCR
DHBCR,R3

:SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

MOV

8177757 RS

(R3) ,R&

:SET UP FOR 4000 ITERATIONS
; (RS)=EXPECTED DATA

*IN BREAK CONTROL REGISTER, 177737
*SET ALL READ/WRITE BITS
>IN BREAK CONTROL REGISTER

:CLEAR BIT S
:GET CONTENTS OF BREAK CONTROL
*WAS BIT S CLEARED
;BREAK CONTROL REGISTER ERROR
“SET BIT 5

;WAS BIT 5 SET
; (RS)=EXPECTED DATA IN
:BREAK CONTROL REGISTER, 177777
:BREAK CONTROL REGISTER ERROR

:VERIFY THAT BIT 6 WAS SET

013662

2913

;DISABLE ALL INTERRUPTS

#4000, 1COUNT

:RESTORE BIT 6

2903

2909
2910
291
2912

#340,PS

MOV

;BREAK CONTROL REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
SCLEAR BIT 6
*VERIFY THAT BIT 6 WAS CLEARED

22%}

2908

MOV

2896
2897
2898
2899

2904

:BREAK CONTROL REGISTER, 177777

013670

013716

012767

012705

004000

177677

164106

004022

004010
003740

T133:

MOV

#340,PS

;DISABLE ALL INTERRUPTS

MOV
MOV
MOV

#2$ .ESCAPE
#8IT11,aDHSCR
DHBCR,R3

:SET UP TO ESCAPE TO NEXT TEST
SMASTER CLEAR INTERFACE
;SET UP POINTER TO BREAF

MOV

#4000, 1COUNT

#177677.RS

013722

012713

177777

MOV

#177777. (R3)

013726
013732

042713
011304

000100

BIC
MOV

#100, (R3)
(R3) .R4

013734

013736
013740

020504

001401
104003

BEQ
ALT

RS.Ré

12
3

SSET UP FOR 4000 ITERATIONS

: (RS)=EXPECTED
DATA

CONTROL

~IN BREAK CONTROL REGISTER, 177677
SSET ALL READ/WRITE BITS
“IN BREAK CONTROL REGISTER
:CLEAR BIT 6

*GET CONTENTS OF BREAK CONTROL
‘WAS BIT 6 CLEARED

;BREAK CONTROL REGISTER ERROR

CZOHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=7 8 10:02

013742
013746
013750
013754

052713
011304
022704
001403

013756

012705

013762
013764

104003
104400

14:40

PAGE 56

1%:

BIS
MOV

000100

SEQ 0066

#100, (R3)
(R3) ‘R4

177777

ggz

#77777 R4

177777

MOV

177777 RS

g%aPE

2%:

;SET BIT 6

;WAS BIT 6 SET
; (RS)=EXPECTED DATA IN

;BREAK CONTROL REGISTER, 177777

;BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
JSET ALL READ/WRITE BITS IN BREAK (ONTROL REGISTER TO 1S

JCLEAR BIT 7

;VERIFY THAT BIT 7 WAS CLEARED

JRESTORE BIT 7

;VERIFY THAT BIT 7 WAS SET

013766
013774
016002

012767
012767
012767

014010
016016
014022

012777
016703
012705

000340
004000
014070
004000
003644
177577

014026

012713

177777

MOV

#177277. (R3)

014032
014036
014040
014042
0146044
014046
014052
014054
014060
014062

042713
011304
020504
001401
104003
052713
011304
022704
001403
012705

000200

BIC
MOV

#200, (R3)
(R3) .R4

014066
14070

104003
104400

164002

003716
003704
003634

“134:

MOV

#340,PS

:DISABLE ALL INTERRUPTS

MOV
MOV
MOV

#23 . ESCAPE
#1717 ,3DHSCR
DHBCR,R3

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
JSET UP POINTER TO BREAK CONTROL

MOV
MOV

#4000, 1COUNT
177577 .RS

“SET UP FOR 4000 ITERATIONS
; (RS)=EXPECTED DATA

*IN BREAK CONTROL REGISTER,
*SET ALL READ/WRITE BITS
*IN BREAK CONTROL REGISTER

177577

‘CLEAR BIT 7
SGET CONTENTS OF BREAK CONTROL

g?z

?g,RA

*WAS BIT 7 CLEARED

ggg

3
#200, (R3)
(R3) ‘R4

;BREAK CONTROL REGISTER ERROR
“SET BIT 7

177777

HLT
BIS
MOV

177777

MOV

2%
8177777 RS

g%épf

000200

1%:

2%:

#177777 R4

;'AS BIT 7 SET
; (RS)=EXPECTED DATA IN

JBREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

—

163676

n)—
~J
NRSRSN

b
ek ok
e
b

Pl S S Y
= O

leolelolele

JBREAK CONTROL REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN BREAK (ONTROL REGISTER TO 1S
;CLEAR BIT 10
;VERIFY THAT BIT 10 WAS CLEARED
JRESTORE BIT 10
;VERIFY THAY BIT 10 WAS SET

003540

003612
003600
003530

T135:

MOV

#340.PS

:DISABLE ALL INTERRUPTS

MOV

#23 ESCAPE

:SET_UP TO ESCAPE TO NEXT TEST

MOV

#4000, 1COUNT

:SET UP FOR 4000 ITERATIONS

MOV
MOV

#BIT11,aDHS(R
DHBCR,R3

#177377,RS

: (RS)=EXPECTED DATA

MOV

:MASTER CLEAR INTERFACE
:SET_UP POINTER TO BREAK CONTROL

014126

012705

014132

012713

177777

MOV

#177777,(R3)

:SET ALL READ/WRITE BITS

014136

042713

000400

BIC

400, (R3)

:CLEAR BIT

177377

:IN_BREAK CONTROL REGISTER,

:IN BREAK CONTROL REGISTER
10

177377

CZDHA-C MACY11 30A(10 52)
23-AUG-78
15-MAY-78 10:02
CZDHAC.P11

0141642
014144
014146
014150
014152
014156
014160
014164
014166

012705

0146172
014174

104003
104400

14 :40

PAGE

304

020504
001401

00C-00

18:

1777277

177777

2%:

SEQ 0067
MOV
(M
BEQ
HLT

8IS
MOV

(R3) ,R4
R5.R4
13

;B AK CONTROL REGISTER ERROR
;SET BIT 10

177977
R4

JWAS BIT 10 SET

#400, (R3)
(R3) ‘R4

cMP
BEQ
MOV

#177777.RS

HLT

SCOPE

sGET CONTENTS OF BREAK CONTROL
JWAS BIT 10 CLEARED

;(RS)=EXPECTED DATA IN

;BREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

JBREAK CONTROL REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
;CLEAR BIT 1N
VERIFY THAT BIT 11 WAS CLEARED
JRESTORE BIT 11
;VERIFY THAT BIT 11 WAS SET
0146176
014204
014212
014220
014226
014232

T136:

MOV

#340 PS

;DISABLE ALL INTERRUPTS

MOV
MOV
MOV

#28 ESCAPE
#I711,3DHSCR
DHBCR,R3

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
;SET UP POINTER TO BREAK CONTROL

MOV

#4000, 1COUNT

MOV

#176777.RS

*SET UP FOR 4000 ITERATIONS

; (RS)=EXPECTED DATA

:IN BREAK CONTROL REGISTER,

012713

177777

MOV

#177777. (R3)

014242
014246
014250
014252
014254
014256
014262
014264
014270
014272

042713

001000

BIC

#1000, (R3)

*IN BREAK CONTROL REGISTER
:CLEAR BIT N

é?g

$2,R4

*WAS BIT 11

012705

014276
014300

104400

011304

MOV

001000

1$:

HLT

104003

2$:

CLEARED

;BREAK CONTROL REGISTER ERROR

#1000, (R3)

SSET BIT

#177777 R4

;WAS BIT 11 SET

BEQ
MOV

177777

HLT

SCOPE

(R3) ,R4

2$
#177777.RS
3

176777

*GET CONTENTS OF BREAK CONTROL

BIS

MOV

177777

(R3) R4

*SET ALL READ/WRITE BITS

: (RS)=EXPECTED DATA IN

:BREAK CONTKOL REGISTER, 177777
*BREAK CONTROL REGISTER ERROR

&WN—‘—‘O
S ONON

b
b
b
b

P S¥ S Y
SR
NN
N WNNN

;BREAK CONTROL REGISTER DATA TEST
:SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
*CLEAR BIT 12
SVERIFY THAT BIT 12 WAS CLEARED
*RESTORE BJT 12
SVERIFY THAT BIT 12 WAS SET

—

3028

163572

003506
003474
003424

014236

lolelelelele]

SISttt
V00NN
WN—=O 85

3007

000340
004000
014300
004000
003434
176777

000340
004000
014404
004000
003330
175777

163466

003402
003370
003320

T137:

MOV

#340,PS

;DISABLE ALL

MOV
MOV
MOV

#2% ESCAPE
#81T11,aDHSCR
Dr'3CR,R3

SSET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

MOV
MOV

#4000, 1 COUNT

#1757%7
RS

INTERRUPTS

*SET UP FOR 4000 ITERATIONS

; (RS)=EXPECTED DATA

CZDHA-CPMACY11 30A(1052)1 23-AUG-78
CZDHAC.P11
15-MAY-78
10:02

3029
3030
3031
3032
3033
3034
2035
3036
3037
3038

3039

2040
3041
3042
3043
;82?

14:40

PAGE 58

3058

2059
3060
3061
3062
3063

3064
3065
3066
3067
3068

3069
307C
3071
3072

3073

%8;?

012713

177777

MOV

#177777,(R®)

01436
014352
014356
014356
014360
014362
014366

042713
011304
020504
001401
104003
052713
011304

002000

PIC
MOV
P
BEQ
HLT
BIS
MOV

#2000, (R3)
(R3) R4
RS.R4
1%
3
#2000, (R3)
(R3) R4

BEQ
MOV

#177777 R4

2s
#177777.RS

;WAS BIT 12 SET

HLT
SCOPE

; (RS)=EXPECTED DATA IN
*BREAK CONTROL REGISTER, 177777
*BREAK CONTROL REGISTER ERROR

014370

022704

014374
014376

001403
012705

014402
014404

1046003
104400

002000

1%:

177777

CMP

177777
2% :

;BREAK CONTROL REGISTER ERROR
SSET BIT 12

;BREAK CONTROL REGISTER DATA TEST
*SET ALL READ/WRITE BITS IN BREAK CONTROL REGISTER TO 1S
*CLEAR BIT 13
SVERIFY THAT BIT 13 WAS CLEARED
*RESTORE BIT 13
SVERIFY THAT BIT 13 WAS SET

014406
014414
014422
014430
014436

012767
012767
012767
012777
016703

000340
004000
014510
004000
003224

014446

012713

014452
014456
016460
014462
014464
014466
014472

062713
011304
020504
001401
104003
052713
011304

014442

014474

014500
014502

014506

014510

012705

022704

001403
012705

163362
003276
003264
003214

T140:

MOV
MOV
MOV
MOV
MOV

#340,PS
#4000, 1 COUNT
#2% ESCAPE
#81711,aDHSCR
DHBCR,R3

177777

MOV

#177777.(R3)

004000

BIC
MOV
CMP
BEQ
HLT
BIS
MOV

#4000, (R3)
(R3) ,R4
RS ,Ré
1%
3
#4000, (R3)
(R3) R4

BEQ
MOV

2$
#177777 RS

HLT

173777

MOV

004000

1%:

177777

cMP

177777

104003

104400

2% :

3076
3077

SCOPE

#173777 RS

8177777 R4

;DISABLE ALL INTERRUPTS
*SET UP FOR 4000 ITERATIONS
:SET UP TO ESCAPE TO NEXT TEST
‘MASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

: (RS)=EXPECTED DATA

*IN BREAK CONTROL REGISTER, 173777
*SET ALL READ/WRITE BITS
*IN BREAK CONTROL REGISTER
$CLEAR BIT 13
*GET CONTENTS OF BREAK CONTROL

*WAS BIT 13 CLEARED

;BREAK CONTROL REGISTER ERROR
‘SET BIT 13

;WAS BIT 13 SET
: (RS)=EXPECTED DATA IN
:BREAK CONTROL REGISTER,

177777

;BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
:SET ALL RCAD/WRITE BITS IN BREAK CONTROL REGISTER TO 1S

3078
3079
3080
308;
3083

:IN BREAK CONTROL REGISTER, 175777
:SET ALL READ/WRITE BITS
*IN BREAK CONTROL REGISTER
*CLEAR BIT 12
:GET CONTENTS OF BREAK CONTROL
“WAS BIT 12 CLEARED

0164342

2046
3047
3048
3049
3050
gggg

3053
3054
3055
3056
3057

SEQ 0068

*CLEAR BIT 14
SVERIFY THAT BIT 14 WAS CLEARED
*RESTORE BIT 14
SVERIFY THAT BIT 14 WAS SET

014512

014520

012767

000340

004000

163256

003172

T141:

MOV

#2/0,PS

#4000, 1COUNT

:DISABLE ALL

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

CZDHA-C MACY11 30A(1052)
23~AUG-78
CZDHAC.P11
15-MAY-78 10:02
3085

014526

012767

014614

3086
3087

01453&
014542

012777
016703

004000
903120

%83?

014552

012713

3092
3093
3096
3095
3096
3097
3098

014556
014562
014564
014566
014570
014572
014576

042713
011304
020504
001401
1046003
052713
011304

3100

014606

gggg

3099

014546

012705

PAGE 59
SEQ 0069

003160

MOV

003110

MOV
MOV

167777

177777

MOV

#177777.(R3)

010000

BIC
MOV
CMP
BEQ
HLT
BIS
MOV

#10000, (R3)
(R3) R4
RS.R4
1%
3
#10000, (R3)
(R3) R4

010000

177777

%}8}

014606

012705

177777

2103
g;gg

014612
014614

1%:

104003
104400

2%:

%}89

014616

0146246
014632

016640
014646

012767

012767
012767

012777
016703

0164652

g}s?

014656

3122
3123
3124
3125
3126
3127
3128

014662
014666
014670
014672
014674
014676
014702

3130
%}%}

014710
014712

001403
012705

3133

014716

104003

g}gg

177777.RS

;CLEAR BIT 14
cGET CONTENTS OF BREAK CONTROL

JWAS BIT 14 CLEARED

;BREAK CONTROL REGISTER ERROR

JSET BIT 14

;WAS BIT 14 SET

s (RS)=EXPECTED DATA IN

;BREAK CONTROL REGISTER, 177777
;BREAK CONTROL REGISTER ERROR

HLT
SCOPE

VERIFY THAT BIT 15 WAS SET

g;}g

3129

MOV

s (RS)=EXPECTED DATA
;IN BREAK CONTROL REGISTER, 167777
;SET ALL READ/WRITE BITS
s IN BREAK CONTROL REGISTER

;SET ALL READ/WRITE BITS IN BREAK (ONTROL REGISTER TO 1S
*CLEAR BIT 15
SVERIFY THAT BIT 15 WAS CLEARED
:RESTORE BIT 15

%}}5

3116
3117

2177977
R4

JMASTER CLEAR INTERFACE
:SET _UP POINTER TO BREAK CONTROL

;BREAK CONTROL REGISTER DATA TEST

2108
2109
3110

3114
2115

BEQ

;SET UP TO ESCAPE TO NEXT TEST

#M]T11,8DHSCR
DHBCR,R3

28167777 .RS

022704

3113

#28 ESCAPE

MOV

014600

001403

14:40

014704

014720

012705

000340

004000
014720
004000
003014

163152

003066
003054

T142:

003004

MOV

MOV
MOV
MOV
MOV

#340,PS

MOV

#157777 RS

012713

177777

MOV

#177777.(R3)

042713
011304
020504
001401
104003
052713
011304

020000

BIC
MOV
¢
8EQ
HLT
BIS
MOV

#20000, (R3)
(R3) ,R4
RS.R4
1%
3
#20000, (R3)
(R3) R,

BEQ
MOV

’s
#177777 RS

022704

1046400

1$:

177777

CMP

177777
2%:

;SET UP FOR 4000 ITERATIONS

sSET UP TO ESCAPE TO NEXT TEST
JMASTER CLEAR INTERFACE
:SET _UP POINTER TO BREAK CONTROL

#81T11,aDHSCR
DHBCR,R3

157777

020000

;DISABLE ALL INTERRUPTS

#4000,
I COUNT
#28 ESCAPE

; (R5)=EXPECTED DATA

;IN BREAK CONTROL REGISTER, 157777
;SET ALL READ/WRITE BITS
;IN BREAK CONTROL REGISTER
;CLEAR BIT 15
;GET CONTENTS OF BREAK CONTROL

JWAS BIT 15 CLEARED

;BREAK CONTROL REGISTER ERROR

;SET BIT 15

28177777
R4

JWAS BIT

; (RS)=EXPECTED DATA IN
;BREAK CONTROL REGISTER,

HLT

177777

;BREAK CONTROL REGISTER ERROR

SCOPE

%}%9

;BREAK CONTROL REGISTER DATA TEST

3138
3139
3140

SCLEAR BIT 16
SVERIFY Tr:AT BIT 16 WAS CLEARED
:RESTORE BIT 16

sSET ALL READ/WRITE BITS

15 SET

IN BREAK CONTROL REGISTER

TO 1S

CZDHA-C MACY11 30A(10;2)10285AUG-78
CZDHAC.P11
15-MAY-78

14:40

PAGE 60
SEQ 0070

;VERIFY THAT BIT 16 WAS SET
3143
3144
3145
3146
3147
3148

014722
014730
014736
014744
014752
014756

012767
012767
012767
012777
016703
012705

000340
004000
015024
040"
002
v
137777

3150

014762

012713

177777

#177777,(R3)

3152
3153
3154
3155

014766
014772
014774
014776

042713
011304
020504
001401

040000

#40000, (R3)

163046
02762

T143:

#28 ESCAPE

#B1T11,aDHSCR
DHBCR,R3

#137777.RS

(R3) R4

012705

3165
3164

015022
015024

104003
104400

J (RS)=EXPECTED DATA

;IN BREAK CONTROL REGISTER, 137777
;SET ALL READ/WRITE BITS
s IN BREAK CONTROL REGISTER
;CLEAR BIT 16
sGET CONTENTS OF BREAK CONTROL

BIS

#40000, (R3)

JSET BIT 16

(MP
BEQ

2177777
R4

MOV

2%:

JSET UP FOR 4000 ITERATIONS
sSET UP TO ESCAPE TO NEXT TEST
sMASTER CLEAR INTERFACE
:SET UP POINTER TO BREAK CONTROL

;WAS BIT

MOV

177777

;DISABLE ALL INTERRUPTS

R5,R4
1%

HLT

177777

015016

#4000, 1COUNT

002750
002700

040000

3161

#340 PS

(R3) R4

#177777..RS

HLT
SCOPE

16 CLEARED

;BREAK CONTROL REGISTER ERROR
JWAS BIT

16 SET

;(RS)=EXFECTED DATA IN
;BREAK CONTROL REGISTER,

177777

;BREAK CONTROL REGISTER ERROR

;BREAK CONTROL REGISTER DATA TEST
sSET ALL READ/WRITE BITS IN BREAK (ONTROL REGISTER TO 1S

;CLEAR BIT 17
SVERIFY THAT BIT 17 WAS (LEARED
JRESTORE BIT 17
;VERIFY THAT BIT 17 WAS SET
3173
3174
3175
3176
3177
3178

015026
015034
015042
015050
015056
(15062

012767
012767
012767
012777
016703
012705

3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192

015066

3193
3194
3195

3196

162742

MOV
MOV

#340,PS

077777

MOV
MOV
MOV

#81711,aDHSCR
DHBCR,R3

012713

177777

MoV

#177777. (R3)

015072
015076
015100
015102
015104
015106
015112
015114
015120
015122

042713
011304
020504
001401
104003
052713
011304
022704
001403
012705

100000

81C
MOV
(MP
BEQ

#100000, (R3)
(R3) .R4
RS.R4

BIS

#100000, (R3)
(R3) ,R4

015126
015130

104003
104400

002656
002644
002574

100000

T144:

MOV

1¢:

HLT

MoV

177777

(MP
BEQ
MOV

177777

’%:

HLT
SCOPE

#4000,
1 COUNT

#28 ESCAPE

#77777
RS

;DISABLE-ALL INTERRUPTS
;SET UP FOR 4000 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
JMASTER CLEAR INTERFACE
:SET_UP POINTER TO BREAK CONTROL

;(R5)=EXPECTED DATA
; IN BREAK CONTROL REGISTER, 77777

;SET ALL READ/WRITE BITS
;IN BREAK CONTROL REGISTER

;CLEAR BIT 17
JGET CONTENTS OF BREAK CONTROL
;WAS BIT 17 (LEARED

JBREAK CONTROL REGISTER ERROR

177777 .84

JWAS BIT 17 SET

£177777.RS

;(RS)=EXPECTED DATA N
;BREAK CONTROL REGISTER,

2s
3

;SILO STATUS REGISTER DATA TEST

JSET BIT 17

177777

JBREAK CONTROL REGISTER ERROR

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC. P
P
15-MAY-78 10:02

14:40

PAGE 61

3197
3198
3199
3200

;SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S
*CLEAR BIT 0
SVERIFY THAT BIT O wAS CLEARED
*RESTORE BIT 0

VERIFY THAT BIT O WAS SET

3203

015132

012767

000340

305
3206
3207
3208
3209
210
3211
3212

015146
015154
015162
015166

012767
012777
016703
012705

015244
004000
002502
100076

015172

012713

015176

0462713

304

015140

3213
3214

015202
015206

3217
18

015214
015216

3215
3216

3219
3220
3221

015210
015212

015222
015226
015230

3222
3223

015234
015236

3025
gggg

015242
015244

012767

011304
042704

020504
001401

104004
052713

011304
042704
022704

001403
012705

MOV

#340,PS

MOV
MOV
MOV
MOV

#2% ESCAPE
#81717,80HSCR
DHSSR,R3
#CLRBIT.RS

100077

MOV

#100077. (R3)

000001

BIC

#1,

(MP
BEQ

RS,R4
1%

004000

162636

002552

T145:

062540
002470

077700

000001

077700
100077

104004
104400

2%:

MOV
BIC
cMP

HLT
SCOPE

#5000, 1COUNT

(R3)

(R$) R4
#77700,R4
4
#1.(R3)

(RS) ,R4
#77700 R4
#100077 R4

:DISABLE ALL INTERRUPTS

*SET UP FOR 4000 [TERATIONS

*SET UP TO ESCAPE TO NEXT TEST
‘MASTER CLEAR INTERFACE
SSET UP POINTER TO SILO STATUS
: (RS)=EXPECTED DATA
“IN SILO STATUS REGISTER, CLRBIT
SSET ALL READ/WRITE BITS
YIN SILO STATUS REGISTER
;CLEAR BIT 0

;GET CONTENTS OF SILO STATUS
*CLEAR UNWANTED BITS
‘WAS BIT 0 CLEARED

;SILO STATUS REGISTER ERROR
SSET BIT'0

;CLEAR UNWANTED BITS
*WAS BIT O SET

2%
#100077 RS

; (RS)=EXPECTED DATA IN
:SILO STATUS REGISTER,

*SILO STATUS REGISTER ERROR

:VERIFY THAT BIT 1 WAS SET
0152646

012767

000340

3237

015062

012767

015360

016703
012705

002366
100075

015256

015270
015276
015302

012767

012777

162522

004000

002436

004000

002354

T146:

002426

MOV

#340,PS

;DISABLE ALL

#28 ESCAPE

SSET UP TO ESCAPE TO NEXT TEST

MOV

#4000, 1COUNT

MOV

#7171, DHSCR

MOV

MOV
MOV

DHSSR,R3
#CLRBIT.RS

INTERRUPTS

“SET UP FOR 4000 ITERATIONS

*MASTER CLEAR INTERFACE

SSET UP POINTER TO SILO STATUS
: (RS)=EXPECTED DATA
“IN SILO STATUS REGISTER, CLRBIT
*SET ALL READ/WRITE BITS

3243
3244
3545

015306

012713

100077

MOV

#100077, (R3)

015312
015316

042713
011304

000002

BIC
MOV

#2 (R3)
(R%) R&

JCLEAR BIT 1
;GET CONTENTS OF

3247
3248
3249
3250

015324
015326
015330
015332

020504
001401
104004
052713

(MP
BEQ
HLT
BIS

RS ,R&
i3
4
22, (R3)

‘WAS BIT 1

3246

3251
3252

100077

;SILO STATUS REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S
*CLEAR BIT *
JVERIFY THAT BIT 1 WAS CLEARED
*RESTORE BIT 1

3235

3239
3240
3241
3242

HLT
BIS

BEQ
MOV

100077

%5%2

3238

MOV

MOV
BIC

3228
3229
3230
3231
3232

3236

SEQ 0071

015320

015336
015340

042704

011304
042704

077700

000002

07770C

BIC

MOV
Bl

#77700,R4

(8 R
277700 .R¢

“IN SILO STATUS REGISTER

SILO STATUS

:C_EAR UNWANTED "3]TS
CLEARED

;SILO STATUS REGISTER ERROR
ssEv it

;CLEAR UNWANTED BITS

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MaY-78 10:02

3253
3254
3255
3256
3257

3”523

015344
015350
015352

022704
001403
012705

015356

1046004

015360

14:40

PAGE 62

SEQ 0072

100077
100077

1046400

2%:

2260
3261
3262
3263
3264
015362
015370
015376
015404
015412
015416

012767
012767
012767
012777
016703
012705

000340
004000
015474
004000
002252
100073

015422

012713

3278

015434

015426

#340,PS
#4000, ] COUNT
#28 ESCAPE
#8IT11,3DHSCR
DHSSR.R3
#CLRBIT,RS

100077

MOV

#100077, (R3)

042713

000004

BIC

#4,

042704

077700

BIC

#77700,R4

BEO
HLT
BIS

1%
4
#4, (R3)

BIC

#77700,Ré

015432

011304

3279

015440

020504

3280
3281
3282

015442
015444
015446

001401
104004
052713

000004

3284

015454

042704

077700

3286
3287
3088
3089

015464
015466

001403
012705

100077

015452

015460

015472

C15474

011304
022704

162406
002322
002370
002240

T147:

MOV

CMP

1%:

100077

MOV
CMP

104004

104400

2% :

3292

: (RS)=EXPECTED DATA IN
*SILO STATUS REGISTER, 100077
*SILO STATUS REGISTER ERROR

(R3)

(R$) ,RG

;DISABLE ALL INTERRUPTS
SSET UP FOR 4000 ITERATIONS
SSET UP TO ESCAPE TO NEXT TEST
SMASTER CLEAR INTERFACE
;SET UP POINTER TO SILO STATUS
; (RS)=EXPECTED DATA
SIN SILO STATUS REGISTER, CLRBIT
“SET ALL READ/WRITE BITS
“IN SILO STATUS REGISTER
;CLEAR BIT 2

:GET CONTENTS OF SILO STATUS
:CLEAR UNWANTED BITS

RS.,Ré4

(R3)
R4

“WAS BIT 2 CLEARED

:SILO STATUS REGISTER ERROR
SSET BIT 2
;CLEAR UNWANTED BITS

BEQ
MOV

#100077 R4

2%
#100077 RS

‘wAS BIT 2 SET

HLT

; (RS)=EXPECTED DATA IN
$SILO STATUS REGISTER, 100077
*SILO STATUS REGISTER ERROR

SCOPE

;SILO STATUS REGISTER DATA TEST

3293

*SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S

394,

*CLEAR BIT 3

3295

SVERIFY THAT BIT 3 WAS CLEARED

:RESTORE BIT 3
IVERIFY THAT BIT 3 WAS SET

%Sgg
3299

015476

012767

000340

3301
3302
2303
306
3305
306
3307
3308

015512
015520
015526
015532

012767
012777
016703
012705

015610
004000
002136
100067

015536

012713

015542

042713

3300

SCOPE

MOV
MOV
MOV
MOV
MOV
MOV

3277

HLT

;WAS BIT 1 SET

JVERIFY THAT BIT 2 WAS SET

3267
3268
269
3270
3271
3272
3073
3274
3275
3276

3285

#100077 R4
2s
#100077,RS

:SILO STATUS REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S
ICLEAR BIT 2
SVERIFY THAT BIT 2 WAS CLEARED
*RESTORE BIT 2

%Sgg

2283

(MP
BEQ
MOV

015506

012767

MOV

#340,PS

:DISABLE ALL

MOV
MOV
MOV
MOV

#23 . ESCAPE
#BIT11,aDHSIR
DHSSR,R3
#CLRBIT,RS

100077

MOV

2100077, (R3)

000010

BIT

#10, (R3;

*SET UP TO ESCAPE TO NEXT TEST
*MASTER CLEAR INTERFACE
;SET UP POINTER TO SILO 5TATUS
: (RS)=EXPECTED DATA
$IN SILO STATUS REGISTER, CLRBIT
SSET ALL READ/WRITE BITS
“IN SILO STATUS REGISTER
*CLEAR BIT 3

004000

162272

002206
002174
002124

T150:

MOV

#4000, 1COUNT

INTERRUPTS

SSET UP FOR 4000 ITERATIONS

8\1\1
S5O 80~O~\nmuu\
nNOONSOON

[0 3¥,1%,] VYOI

D
e
d
D

(V. V) Vi

ole] [olelololelolale

CZDHA-C MACY11 30A(1052)
28-AUG-78
CZDHAC PN
15-MAY-78 10:02

011304
042704
020504
001401
106004

015606
015610

104004
104400

—

pd —

015602

052713
011304
042704
022704
001403
012705

14:40

PAGE 63
MOV

000010

;GET CONTENTS OF SILO STATUS

ggg

?2'“‘

*WAS BIT 3 CLEARED

HLT

;SILO STATUS REGISTER ERROR

815
MOV

BIC

077700

SEQ 0073

(R3) ,R&4

BIC

077700

#77700.R4
#10, (R3)
(R3) ,R&

#77700 R4

100077

5?8

10077

MOV

2%
#100077 ,RS

g%ng

2%:

#100077 R4

*CLEAR UNWANTED BITS

SSET BIT 3

:CLEAR UNWANTED BITS

‘WAS BIT 3 SET

;(RS)=EXPECTED DATA IN
2SILO 5TATUS REGISTER, 100077

;SILO STATUS REGISTER ERROR

;SILO STATUS REGISTER DATA TEST
;SET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 1S
JCLEAR BIT &
JVERIFY THAT BIT 4 WAS (LEARED
JRESTORE BIT 4
JVERIFY THAT BIT &4 WAS SET

015612
015620
015626
015634
015642
015646

012767
012767
012767
012777
016703
012705

0003490
004000
015724
004000
002022
100057

015652

012713

015656
015662
015664

042713
011304
042704
020504
001401
104004

052713
011304
042704
022704
001403
012705

162156

T151:

MOV
MOV
MoV
MOV
MOV
MoV

#340,PS
#4000, 1 COUNT
#2% ,ESCAPE
#81T11,aDHSCR

100077

MOV

#100077, (R3)

000020

RIC

#20, (R3)

BIC

277700 ,R¢
?2,R4

‘WAS BIT & CLEARED

HLT

;SILO STATUS REGISTER ERROR

BIC

#77700,R4

;CLEAR UNWANTED BITS

MOV

2%
#100077,RS

s (R5)=EXPECTED DATA IN

g%BPE

;SILO STATUS REGISTER ERROR

002072
002060
00201C

MOV

077700

5?8

000020

1%:

077700

BIS
MOV

g?fi

100077

104004
1046400

2%:

DHSSR,R3
#CLRBIT RS

(R3) .R&

#20, (R3)
(R3) ,R&

#100077 ,R4

;DISABLE ALL INTERRUPTS
JSET UP FOR 4000 ITERATIONS
;SET UP TO ESCAPE TO NEXT TEST
JMAZTER CLEAR INTERFACE

;SET UP POINTER TO SILO STATUS
; (RS)=EXPECTED DATA

;IN_SILO STATUS REGISTER, CLRBIT
JSET ALL READ/WRITE BITS

;IN SILO STATUS REGISTER

SCLEAR BIT 4

*GET CONTENTS OF SILO STATUS

*CLEAR UNWANTED BITS

SSET BIT 4

*WAS BIT & SET

;SILO STATUS REGISTER, 100077

;SILO STATUS REGISTER DATA TEST
JSET ALL RLAD/WRITE BITS IN SILO STATUS REGISTER TO 1S
JCLEAR BIT 5
JVERIFY THAT BIT 5 WAS CLEARED

Jur gy

—

JRESTORE BIT 5
JVERIFY THAT BIT 5 WAS SET
2767
2767

000340
004000

162042
001756

T52:

MOV

#>'0,PS

#4000, 1COUNT

;lS> SABLE ALL INTERRUPTS

ISET UP FOR 4000

ITERATIONS

CZDHA-CPHACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY=78 10:02

3365
3366
3367
3368
3369
3370
3371
3372
3373

015742
015750
015756
015762

012767
012777
016703
012705

016040
004000
001706
100037

015766

012713

015772
015776

042713
011304

3376
3377
3378
3379

016006
016010
016012
016016

001401
104004
052713
011304

3382
3383
3384
3385
gggg

016030
016032

3374
3375

3380
2381

016000
016006

016020
016026

016036
016040

042704
020504

042704
022704

001403
012705

14:40

PAGE 64

001744
001674

MOV
MOV
MOV
MOV

#2$ ESCAPE
#81771,8DHSCR
DHSSR,R3
#CLRBIT.RS

100077

MOV

#100077. (R3)

000040

BIC
MOV

#40, (R3)
(R3) ,R&

BEQ
HLT
BIS
MOV

1%
A
#40, (R3)
(R3) ,R%

077700

BIC
CMP

000040

077700
100077

BIC
CMP

100077

104004
104400

2%:

3288
3389
3390
3391
3392

%%32

3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405

SEQ 0074

#77700,R4
RS5,R&4

;SILO STATUS REGISTER ERROR
*SET BIT 5

BEQ
MOV

2$
#100077,RS

;CLEAR UNWANTED BITS
‘WAS BIT S SFT

HLT
SCOPE

: (RS)=EXPECTED DATA IN
;SILO STATUS REGISTER, 100077
;SILO STATUS REGISTER ERROR

;SILO STATUS REGISTER DATA TEST
JSET ALL READ/WRITE BITS IN SILO STATUS REGISTER TO 13
‘CLEAR BIT 17
JVERIFY THAT BIT 17 WAS CLEARED
JRESTORE BIT 17

JVERIFY THAT BIT 17 WAS SET

012767
012767
012767
012777
016703
012705

000340
004000
016154
004000
001572
000077

C16102

012713

100077

MOV

#340,PS
#4000, ICOUNT
#2% ,ESCAPE
#]T11,aDHSCR
DHSSR,R3
#CLRBIT.RS
)
#100077.(R3%)

016106
016112

042713
011304

100000

BIC
MOV

#100000, (R3)
(R3) R4

34,07
34,08
3409
34,10
3411

016120
016122
016124
016126
016132

020504
001401
104004
052713
011304

3214
3415
3416
3417
34,18

016144
016146

3412
3413

SCLEAR UNWANTED BITS
‘WAS BIT 5 CLEARED

#77700,R4
#100077 ,R4

016042
016050
016056
016064
016072
016076

;SET UP TO ESCAPE TO NEXT TEST
“MASTER CLEAR INTERFACE
sSET UP POINTER TO SILO STATUS
; (RS)=EXPECTED DATA
SIN SILO STATUS REGISTER, CLRBIT
“SET ALL READ/WRITE BITS
“IN SILO STATUS REGISTER
:CLEAR BIT §
*GET CONTENTS OF SILO STATUS

016114

016136
016140

016152
016154

042704

042704
022704

001403
012705

104004
104400

161726
001642
001630
001560

T153:

077700

100000

MOV
MOV
MOV
MOyV
MOV
MOV

8IC

1%:

077700
100077

RS.R4
13
4
#100000, (R3)
(R3) R4

8EQ
MOV

2s
#100077 RS

8IC
MP

100077
2s:

077760.R4

TM
BEQ
HLT
els
MOV

HLT
SCOPE

;DISABLE ALL INTERRUPTS
JSET UP FOR 4000 ITERATIONS
JSET UP TO ESCAPE TO NEXT TEST
JMASTER CLEAR INTERFACE
JSET UP POINTER TO SILO STATUS
: (RS)=EXPECTED DATA
$IN SILO STATUS REGISTER, CLRBIT
;SET ALL READ/WR.TE BITS
*IN SILO STATUS REGISTER
:CLEAR BIT 17
JGET CONTENTS OF SILO STATUS

;CLEAR UNWANTED BITS
*WAS BIT 17 CLEARED

;SILO STATUS REGISTER ERROR
*SET BIT 17

#77700 R4
#150077 R4

;CLEAR UNWANTED BITS
‘WAS BIT 17 SET

: (RS)=EXPECTED DATA IN
*SILO STATUS REGISTER, 100077
;SILO STATUS REGISTER ERROR

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY~-78 10:02

14:40

PAGE 65

19
3420
3421
3422
3423
3424
3425
3426

:SYSTEM CONTROL REGISTER MOVE-BYTE TEST (PART 1)
:ISSUE A MASTER CLEAR
MOVE A BYTE TO SET INTERRUPT ENABLE BITS
IN UPPER BYTE OF SYSTEM CONTROL
.VERIFY BITS SET CORRECTLY
:MOVE A BYTE TO SET INTERRUPT ENABLE BIT
:
IN LOWER BYTE OF SYSTEM CONTROL

gzsg

;VERIFY UPPER BYTE WAS NOT AFFECTED

3429
3430
3431

016156
016162
016170

012706
012767
012767

021360
000340
016300

161606
001516

3433

016206

052777

004000

001440

T154:

3432 016176 012767 004000 001514

3434
335
3436
3437
3438
3439
3440
341
3642
3443
3444
3445

016212
016216
016220

016703
005203
112713

001434

022777
001406
012705
017704
1046001
000414
112777

030000

000100

001374

346

016256

022777

0320100

001366

3448

016266

012705

030100

gzgg

016300

104400

3449
3450

016264

016272
016276

001405
017704
104001

001420

030000
001406
2%:

3465

3468
%69
3470
3471
3472
3473
3474

:ISSUE MASTER CLEAR

MOV
INC
MOVB

DHSCR,
R3
#60,

CMP
BEQ
MOV
MOV
HLT
BR
MOVR

MOV
HLT

SCOPE

(RS)
=SYSTEM CONTROL REGISTER ADDRESS
UPPER BYTE
(R3)
ser INTERRUPT ENABLE BITS
:IN UPPER BYTE OF SYSTEM CONTROL
#BIT13+81T12,aDHSCR
SVERIFY BITS SET CORRECTLY
2%
:BRANCH IF Ok
#MBIT13+BIT12,RS : (RS)=REGISTER EXPECTED DATA
aDHSCR, R&
:(RG)=REGISTER ACTUAL DATA
1
:BITS DID NOT SET CORRECTLY
99
:BRANCH TO SCOPE
#81T06, aDHSCR
ssr INTERRUPT ENABLE BIT
IN LOWER BYTE OF SYSTEM CONTROL

cexr13+e1r12+elrbb @DHSCR

:VERIFY BITS SET CORRECTLY

BRANCH IF OK

aDHSCR, R&
1

: (R4)=REGISTER ACTUAL DATA
SUPPER BYTE WAS AFFECTED?

~31113+8111a+e1rbb RS

;(RS)=REGISTER EXPECTED DATA

:CHECK FOR ITERATIONS,LOOP

;SYSTEM CONTROL REGISTER MOVE-BYTE TEST
;1SSUE MASTER CLEAR
JMOVE A BYTE TO SET LINE SELECT BITS
;
IN LOWER BYTE OF SYSTEM CONTROL
JVERIFY BITS SET CORRECTLY
JMOVE A BYTE TO SET THE MAINTENANCE BIT
:
IN UPPER BYTE OF SYSTEM CONTROL

gzgg

3466
3467

#BIT17, IDHSCR

ICOUNT ;SET UP FOR 4000 ITERATIONS

MOV

99% :

;SET UP STACK
;LOCK OUT INTERRUPTS
;SET UP TO ESCAPE TO NEXT TEST

04006

CMP

001354

#STACK, SP
0340
PS
ESCAPE

MOV

BEQ

3453
3454
3455
3456
2457
3458
3459

3462
363

MOV
MOV
MOV

BIS

000060

016224
016232
016234
016240
016264
016246
016250

3447

SEQ 0075

(PART 2)

;VERIFY LOWER BYTE WAS NOT AFFECTED

016302
016306
016314

012706
012767
012767

021360
000340
016424

016330
016336

052777
016703

004000
001310

016322

01632
016344
016352
016360
016362
016366

012767
005203
112777

022777
001406
012705
017704

161462
001372

T155:

MoV
MOV
MOV

004000

001370

MOV

000017

001300

INC
MOVR

000017

001272

000017
001260

001314

BIS
MOV

(MP
BEQ
MOV
MOV

#STACK, SP
#340,
PS
#99%
ESCAPE

#4000,

ICOUNT

R3
7,

aDHSCR

#1711, QaDHSCR
DH3CR, R3

7,
@DHSCR
2%
87,
RS
aDHSCR, R4

;SET UP STACK
:LOCK OUT INTERRUPTS
;SET UP TO ESCAPE TO NEXT TEST

:SET
UP FOR 4000 ITERATIONS

:ISSUE MASTER CLEAR
(R3)=SYSTEM CONTROL REGISTER ADDRESS

UPPER BYTE
ser LINE SELECT BITS
;IN LOWER BYTE OF SYSTEM CONTROL
:VERIFY BITS SET CORRECTLY
:BRANCH IF 0K
:(RS)=REGISTER EXPECTED DATA
; (R4O=REGISTER ACTUAL DATA

CZOHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

3475
3476
3477
3478
3479
3480
381
3482
3483
gzgé

016372
016374
016376

104001
000413
112713

016402
016410
016412
016416
016422

022777
001405
012705
017704
104001
104400

016424

14:40

PAGE 66

2s:

HLT
BR
MOVB

]
99%
"2,

99%:

cMP
BEQ
MOV
MOV
HLT
SCOPE

#1017,
QDHSCR
99%
#1017,
RS
aDHSCR, R&
1

000002
001017

001242

001017
001230

3486
3487
3488
3489
3490
016426
016430
016432
016436
016442
016446

104401
020325
005067
005067
005267
016767

3500
3501

016460
016462

001405
000005

3502

016454

016464

016466
016470
016472
016474

013701

EOP:

001312
001242
001240
001236

000042

161114

004711

000240
000240
000240
000167

BEQ
RESET

NOP
NOP
NOP
RESTRT: JMP

162502

:TYPE NAME OF

;CLEAR LAST ERROR PC
;CLEAR ERROR FLAG
:UPDATE PASS COUNT
:DISPLAY PASS COUNT

RESTRT

:1F NOT, CONTINUE TESTING

W62, R1

JSR

;CHECK FOR ACT-11 OR DDP

PC,(R1)

BEGIN

:CHECK FOR ITERATION SUPPRESSION
016500
016506
016510
016516
016520
016526
016530
016534
016542
016544
016550
016554
016560
016562
016566
016570
016574
016576

032767
001030
032767
001021
032767
001006
005267
026767
001007
005067
005067
011667

000002
016716
000002
005767
001745
000762

002000

161062

040000

161052

004000

161042

001166
001162

001156

001152
001130
001132
001124
001110

SCOPER: BIT
BNE
1%:
8IT
BNE
BIT
BNE
INC
CMP
BNE
2%:
CLR
(LR
MOV
RT]
3%:
MOV
RT]
A
TST
BEQ
BR

TEST

LAST
ERRFLG
PASCNT
PASCNT ,LIGHTS

;CHECK FOR 'OOP ON CURRENT TEST

§§99

3530

TYPE
MEPASS
CLR
CLR
INC
MOV

MOV

L OGICAL :

3508

3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
%ggg

;CHECK FCR ITERATIONS,LOOP

;RESTART TEST

3493
3494
3495
3496
3497
3498

3503
3504
3505
gggg

(R3)

:BITS DID NOT SET CORRECTLY
*BRANCH TO SCOPE
ser MAINTENANCE BIT
IN UPPER BYTE OF SYSTEM CONTROL
venlrv BITS SET CORRECTLY
*BRANCH IF OK
: (RS)=REGISTER EXPECTED DATA
;(RG)=REGISTER ACTUAL DATA
;LOWER BYTE WAS AFFECTED?

JEND OF PASS
:TYPE NAME OF TEST
:UPDATE PASS COUNT
JCHECK FOR EXIT TO ACT-1

gzg;

3499

SEQ 0076

#SW10, SWR
48
#SW14,SWR
3s
#SW11,SWR
2%
LPCNT
LPCNT, ICOUNT
3%
LPCNT
ERRFLG
(SP) ,RETRN
RETRN, (SP)
ERRFLG
1%
2%

s(HECK FOR FREEZE ON CURRENT DATA

CZDHA-C MACY11 30A(1052) 0285AUG~78
CZDHAC.P11
15-mMAY-78

3532
3533
3536
3535

016600
016606
016610
016614

032767
001402
016716
000002

001000

14:40

160762

001102

PAGE 67

SCOP1R: BIT
BEQ
MOV
1$:
RTI

SEQ 0077
#SW09, SWR
1%
FREEZ1, (SP)

;ERROR HANDLER

3539

016616

032767

020000

3541

016626

021667

01116

3543
3544

016634
016640

011667
005067

001110
001040

3547

016650

162705

160744

ERRORS: BIT

000002

3551
3552
3553
3554
3555

016662
016666
016672
016676
016702

042704
062704
012467
011467
005767

177001
020436
000034
000042
000776

3557

016710

005767

000030

016722

012767

000001

3564

016734

000000
005767

000004

3568
3569

016750

005767

016760

016600
000000

000002

3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586

016770
016774
017002
017004
017010
017012
01701«
017016

005267
032767
001402
016716
000002
000001
006
017742

000714
002000
000704

oce

(SP) ,RS

BIC

#177901,Ré4

TST
BEQ
ST
BNE

OCTASC

ERTABO

MOV
TYPE

ERRMSG: 0

160566

HALTS
(SP) ,LAST
18
(SP) ,LAST
ERRFLG

#2 RS
(RS) _R4

MOV

000754

#SW13, SWR

SUB
MOV
ADD
MOV

160614

3572

SAVOSP

MOV
ASL
ASL

TYPMSG:

3561

BNE
CMP
BEQ
MOV
CLR

TYPDAT:

TST

HALTS:

TST

R4
R4

#ERRTAB
R4
(R4) +,ERRMSG

(RG) ,DATABP

ERRFLG
TYPMSG
DATABP
TYPDAT

#1,ERRFLG
DATARP

BEQ
OCTASC
DATABP: 0
RESREG: RESOS

RESREG

8P
PUSHRO
MOV
T
HAL
POPRO
EXITER: INC

EXITER

eIt

1%:

ERTABO:

BEQ
MOV
RT]

.BYTE
“avPe

SWR

2(SP) .RO
ERRCNT

#SW10, SWR

1%
ESCAPE
, (SP)

6,2

:TRAP DISPAT(CH SERVICE

;ARGUMENT OF TRAP IS EXTRACTED
JAND USED AS OFFSET TO OBTAIN POINTER

2TO SELECTED SUBROUT INE

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

3587
588
3589
3590
3591
3592
3593
3594
gggg

017020
017022
017026
017032
017034
017040
017044
017050

011646
162716
017616
006316
042716
062716
017616
000136

14:40

_
000002
000000

PAGE 68

TRPSRV: MOV
SUB
MOV
TRPOK:
ASL
BIC
ADD
MOV
JMP

177001
020356
000000

gggg

3599
3600
3601
3602
3603
3604
3605
3606

gggg

017052
017056
017062
017066
017070
017072
017074
017076

017102

017605
062716
105777
100375
105715
001001
000002
112577

000767

000000
000002
000560

1$:

000546

2%:

TYPER:

017104
017112
017116
017120
017122
017126
017132
017136
017140
017144
017150

017667
062716
104401
000000
012704
012703
105777
100375
117714
142714
122427

000007

3623
3624

017156
017164

117777
105777

000462
000456

3626
3627
3628
3629
3630
gggg

017154

017170

017172
017174
017176
017200
017202
017204

001413

100375

000000
000002

000006

020400
000504

000500
000200
000015

005303
001356
104401
020231
000745
000002

000464

INSTRG: MOV
ADD
INSTR1: TYPE
MSG:
0
MOV
MOV
1$:
TSTB
8PL
MOVB
BICB
CMPB

BEQ

2%:

MOVB
TSTB

B8PL

DEC
BNE
INSTRE: TYPE
MOM
BR
INSTR2: RTI

332%2
3635
3636
3637
2638
339
3640
3641
3642

MOV
ADD
TSTB
8PL
TSTB
BNE
RTI
MOVB

a(SP) RS
#2,(SP)
@TPCSR
1%
(RS)
2$

(RS)+,aTPDBR
1%

;ASCII STRING INPUT ROUTINE

3611
3612
3613
3614
3615
3616
3617
3618
3619
2620
3621

3625

(SP) ,=-(SP)
#2,(SP)
a(SP), (SP)
(SP)
#177001, (SP)
#TRPTAB. (SP)
a(sP), (SP)
a(sP)+

;TELETYPE QUTPUT ROUTINE

ggqg

3622

SEQ 0078

a(SP) ,MSG
42, (SP)

# INBUF ,R4

#7.R3

QTKCSR
1%
STKDBR, (R4)
#200, (R4)
(RG)+, 415

INSTR?

aTKDBR,aTPDBR
RTPCSR

R3
1%

INSTR1

;CONVERT ASC!I STRING TO OCTAL
017206
017210
017214
017220
017226
017230
017234
017236

011605
012567
012567
012567
112567
112567
010516
005005

000146
000144
000142
000140
000135

PARAMS: MOV
MOV
MOV
MOV
MOVB
MOVB
MOV
PARAMT: CLR

(SF) RS
(RS)+,LOLIM
(R5)+_RILIM
(R5) +.DEVADR
(R5)+.LOBITS
(R5)+.ADRCNT
R, (SP)
R5

;GET PC OF RETURN
;=PC OF TRAP
:GET TRP
sMULTIPLY TRAP ARG BY 2
sCLEAR UNWANTED BITS
;POINTER TO SUBROUTINE ADDRESS
s SUBROUTINE ADDRESS
;GO TO SUBROUTINE

CZDHA-C MACY11 30A(1052)
23§AUG-78
15-MaY-78 10:0
CZDHAC.PIN

0172640
0172644
017250
017252
017256
017260

012704
1227146
001420
12
00
12

14:40

PAGE 69

020400
000015
000060

MOV

cMPB

1$:

000067

017312
017314

020567
101373
020567
103770
136705
001365

(R4
) ,#60

BLT

PARERR

BGT

PARERR

(RG) ,#67

#60, (R&4)

BIS8

(R4)+,RS

(MP8

#15,(R4)

B8R

BEQ
ASL
ASL
ASL

PARERR:

LIMITS
RS
RS
RS

INSTER

JTEST

017316
017322
017324
017330
017332
017336

PARERR

CMP8

BICB

000015

104404
000750

# INBUF R4

#15, (R)

cMPB

000060
714

BEQ

SEQ 0079

000042

LIMITS:

000032
000032

PARAM1
TO SEE

CMP
BH]
cMP
BLO
BITB
BNE

NUMBER

1S WITHIN LIMITS

RS ,HILIM
PARERR
RS,LOLIM
PARERR
LOBITS,RS
PARERR

;STORE NUMBER AT SPECIFIED ADDRESS
017340

016704

000022

017346

062705

000002

017344

017352
017356
017360
017362

017364
017366
017370

010524

105367
001372
000002
000000

1%:

000013

LOLIM:

000000
000000
000000

HILIM:

DEVADR:
LOBITS:

MOV
MOV
ADD
DECB
eNE
RTI

DEVADR R4
RS.(R4)+
#2 RS
ADRCNT
1%

0
0

ADRCNT=L0BITS+1

sCONVERT OCTAL NUMBER TO ASCII AND OUTPUT TO TELEPRINTER
017372

017412
017416
017422
017426
017432
017436
017442
017444

104401

0
112167
112167
013167
016704
116705
012700
010403
042703

OCTASN:

000126
000123
000120
000114
000106
020412
177770

1%:

2%:
3¢

TYPE
MCRLF

MOV
ADD

3(SP) .R1
#2. (SP)

MOVB

(R7)+.CHRCNT

MOV

MOVB
MOV
MOV
MOVB

MOV

8I(

(R1)+,WRDCNT

(R1)+.SPACNT
8(R1)+,BINWRD

BINWRD. R4
CHRCNT.RS

nem RO

:177770 R3

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

017450
017454
017456
017460
017462
017464
017466
017470
017474
017476
017502
017504
017510

062703

14:40

PAGE 70

000260

ADD
MOVB
ASR
ASR
ASR

020424

4%:

000042

000240
000023

5%:
6%

000004
WRDCNT:

017544

#260,R3
R3,(R0O)+

R4
R4
R4

DEC
BNE
MOV

RS
33
#MDATA ,R3

DECB

CHRCNT

MOVB

B8NE

000035

SEQ 0080

TSTB
BEQ
MOVB
DECB
BNE

=(R0O),(R3)+

(LRB

SPACNT
63
#240, (R3)+
SPACNT
5%
(R3)

DEC
BNE

WRDCNT
18

TYPE
MDATA

RTI
O

CHRCNT: 0
SPACNT=CHRCNT
+1
BINWRD: O

017546

;SAVE PC OF TEST THAT FAILED AND RO-RS
017550

016667

000004

000164

SVOSP:

MOV

4(SP),SAVPL

;SAVE RO-RS

017556

010567

000154
000146
000140
000132
000124
000116

Sv05:

MOV
MOV
MOV
MOV
MOV
S?Y

RS, SAVRS
R4, SAVR4
R3,SAVR3
R2.SAVR?2
R1,SAVR1
RO, SAVRO

JRESTORE RO-RS
017610
017614
017620
017624
017630
017634
017640

017642
017644
017646
017650
017652

016705
000002
177560

000000

000110
000106
000104
000102
000100
000076

RSOS:

MOV
MOV
MOV
MOV
MOV
g?y

SAVRO R0
SAVR1,R1
SAVR? ,R2
SAVR3,R3
SAVR4 R4
SAVRS ,RS

JINDIRECT POINTERS
TKCSR:
TKDBR:
TPCSR:
TPDBR:

DHSCR:

177560
177562
177564
177566

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-mMAY-78 10:02

14:40

PAGE 71

SEQ 0081

3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766

017654
017656
017660
017662
017664
017666
017670
017672
017674
017676
017700
017702

000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

DHNRC:
DHLPR:
DHBA:
DHBC:
DHBAR:
DHBCR:
DHSSR:
DHSLR:
DHRVEC:
DHRLVL:
DHTVEC:
DHTLVL:

0
O
0
0
0
0
0
0
0
0
0
O

3769
3770
3771
3772
3773

017704
017706
017710
017712
017714

000000
000000
000000
000000
000000

ERRFLG:
PASCNT:
ERRCNT:
RETRN:
ESCAPE:

0
O
0
O
0

3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788

017720
017722
017724
017726
017730
017732
017734
017736
017740
017742
017744
017746
017750

000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000

ICOUNT:
LPCNT:
SAVRO:
SAVR1:
SAVRZ:
SAVR3:
SAVR4:
SAVRS:
SAVSP:
SAVPC:
INIFLG:
STFLG:
LAST:

O
;ITERATION COUNT FOR TEST IN PROGRESS
O
;NUMBER OF ITERATICNS THIS TEST
0
;RO SAVE AREA
0
;R1 SAVE AREA
0
;R2 SAVE AREA
0
;R3 SAVE ARE
0
;R4 SAVE AREA
O
;RS SAVE AREA
0
;STACK PJINTER SAVE AREA
0
:CALLING ROUTINE SAVE AREA
0
;PROGRAM INITIALIZATION FLAG
0
;PROGRAM START FLAG
O
;LAST ERROR PC
:ENTER HERE ON POWER FAILURE

3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
;gg;

017752
017754
017756
017760
017762
017764
017766
017772
017776
020004
020006

010046
010146
010246
010346
010446
010546
016746
010667
012767
000000
000777

PHAIL:

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
HALT
BR

g;gg

3774

017716

000000

FREEZ1:

160032
177742
020010

3803
3805
3806
3807
3808
3809
3810

160020

;PROGRAM VARIABLES

:ERROR FLAG
:PASS COUNT
:ERROR COUNT
.SCOPE RETURN ADDRESS FOR TEST LOOPING
;ADDRESS FOR ERROR ESCAPE

;DATA LOOPING RETURN ADDRESS

RO,-(SP)
R1,-(SP)
RZ,=-(SP)
R3,~(SP)
R4 ,~(SP)
R5,=(SP)
26,-(SP)
SP,SAVSP
WRESTART, 24

;SAVE RO-R5 ON PROCESSOR STACK

:SAVE STACK POINTER
;SET UP FOR POWER UP TRAP
;HALT ON POWER DOWN NORMAL

;PROCESSOR WILL TRAP HERE WHEN POWER IS RESTORED
020010
020014
020016
020020
020022
020024

016706
012605
012604
012603
012602
012601

177724

RESTAR: MOV
MOV
MOV
MOV
MOV
MOV

SAVSP, SP
(SP)+,R5
(SP)+ R4
(SP)+,R3
(2P)+ R
(SP)+,R1

JRESTORE STACK POINTER
;RESTORE RO-R5

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

3811
3812
3813
3814

3815
3816
3817

3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833

020026
020030
020036
020044

020050
020054
020060

012600
012767
012767
012706

005067
005267
001375

017752
000340
021360

14:40

MOV
MOV
MOV
MOV

000336
000332

CLR
INC
BNE

3835

104402
020106
104401
020240
005067
005067
000177
000001
000006
017712
005015
020061
041511
041511
020124
015
047524
051104

042012
052123
046040
052040
005015
053012
020122
051505

030510
052101
043517
051505
000
041505
042101
026523

3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
%ggg

020175
020202
020210
020216
020224
020231
020235
020240
020246
020254
020262
020270
020276
020304
020312
020320
020325
02CG332
020337
020343
020350

15
051124
043505
020122
051505
040
015
020040
020122
051125
047522
051040
052122
040524
020116
042522
15
040510
015
015
020124

041412
046117
051511
042101
026523
037440
000012
047520
040506
026105
051107
051505
040440
052123
051120
051523
041412
041455
051012
052012
041520

047117
051040
042524
051104
000
000

3865
3866

SEQ 0082

157766
157732

020062
020064
020066
020070
020072
020076
020102
020106
020110
020114
020116
020124
020132
020140
020146
020153
020160
858}92

3859
3860
3861
3862
3863

PAGE 72

177606
177646
177604
000002

042527
046111
050040
046501
040524
020124
044440
043517
000
042132
000
000
051505
000055

(SP)+,R0O
#PFAIL ,24

;JSET UP FOR POWER FAILURE

#340,PS

#STACK,
SP
TEMP
TEMP

.~4

OCTASC
PFTAB
TYPE
MPFAIL
CLR
CLR
JMP
PFTAB:
1
6,2
RETRN
MTITLE: .ASCIZ

ERRFLG
LAST
aRETRN

MVECTO:

.ASCIZ

<15><12>/VECTOR ADDRESS-/

MREGAD:

.ASCIZ

<15><12>/CONTROL

MaMm:
MCRLF:
MPFAIL:

LASCIZ
.ASCIZ
.ASCIZ

/%
<15><12>
/
POWER FAILURE,

MEPASS:

.ASCI?Z

<15><12>/C2DHA~(C/

MR:
MTSTPC:

LASCIZ
.ASCIZ

<15><12>/R/
<15><12>/TEST PC-/

<15><12><12>/DH11

STATIC LOGIC TEST /<15><12>

PROGRAM RESTART AT

;TABLE OF FOINTERS FOR TRAP DECODING

020356
020360
020362
020364
020366
020370

016500
017052
017372
017104
017176
017206

TRPTAB:

SCOPER
TYPER
OCTASN
INSTRG
INSTRE
PARAMS

TEST

IN PROGRESS/

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

3867

020372
020374
020376

14:40

PAGE 73

SEQ 0083

SVO5P

017550
017610
016600

RSO5
SCOP1R

;BUFFERS FOR INPUT-QUTPUT
020400
020412
020424

000000
020412
000000
020424
000000
020436

;TABLE OF POINTERS TO ERROR MESSAGES AND DATA
EMO
DTO
EM1
DT1
EM?
DT
EM3

DT1
EMS
DT

044507
042040
052117
047520

052123
042111

EMO:

EMS
DT
LASCII

/REGISTER DID NCT

LASCIZ

<15><12>/ADDRESS/

LASCII

/SYSTEM CONTROL

LASCIZ

<15><12>/EXP

LASCII

/LINE

LASCIZ

<15><12>/EXP

LAST]]

/iCPEAK CONTROL

RESPOND/

051040

042116
051104
046505
051124
043505
020122
122
050130
051040
020040
042522

EM1:

EMC:

REC

ADDRESS/

PARAMETER REGISTER ERROR/

ke C

ADDRESS/

051104
040505
052116

CZDHA-CPT?CY11 30A(1052)
23-AUG-78
CZDHAC
15-MAY-78 10:02

3923
3924

020722

020114
052123
051122

017732

000000
00000°

PAGE

SEQ 0084

044507
042440

051104

020120
042522
020040
051505

047574
052524
044507
042640

051440
020123
052123
051122

054105
020049
020040
051104

020120
042522
020040
051505

052123
042514
051122
054105
020040
020040
051104

051105
051101
051117
020120
042522
020040
051505

000

006
017736
006
017734
006

14 :40

00¢
002
000

EMS :

.EVEN
DTO:
BYTE

DT1:

BYTE

JASCIZ

<15><12>/EXP

LASCI]

/SILO STATUS REGISTER ERROR/

JASCI2

<15><12>/EXP

LASCI]

/MASTER

LASCIZ

15><12>/EXP

1
6,0
SAVRS

6,2
SAVRS
BYTE
6.2
SAVR4
RYTE
6,0
SAVR?
ENDCOD: O
.END

REC

ADDRESS/

CLEAR ERROR/

REC

ADDRESS/

CZDHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC.P11

017371
001202
017546
000020

BITCLR- 000077
BITX

BITO0
BIT01
BIT02
BITO03
BITO4
BITOS
BITO6
BIT07
BITOB
BITO9

000000

=
=
=
=
=
=
=

000001
000002
000004
000010
000020
000040
000100
000200
000400
001000

81710 = 002000
BIT11 - 004000

BIT12

10000

BIT14
BIT15
sIT
CCRBIT

040000
100000
000020
077777

CHRCNT
CLRBIT

017544
000077

DATABP
DEVADR
DHBA
DHBAR
DHB(
DHBCR

(016744
017366
017660
(17664
017662
017666

BIT13 = 020000

3640«
399
3693~
13014

3675+
428
3694
13264

22954

23254

16264
19514

1651#
19764

26854
30754
220654
26554
30454
13014

27154
31054
22954
26854
30754
13264

22954
26854
50754
854
84H
834
824
814
804

23254
27154
31054
738
768
798
828
858
888

16264
19514

794
78%

7784
7
1221

75#

746K

1486
1811

16514
1976w

CROSS REFERENCE TABLE -- USER SYMBOLS

SEQ 0085

14264
17514

20764
24454
28354
32274
24154
28054
31954
14264
17514

20764
24454
28354
32274

918
1064
1084
948
1224
1104

649

1511
1836

2140
2516
2906
3302

2167
2546
2936
3334

22654
26554
3691«
22654
26554
30454
33234
3554«
3638«
533
602
556
579
1887

22954
26854
3695
22954
26854
30754
3336
3557
3672
537
606
560
583
1912

73K
72#
714
70#
13014

PAGE 76

978
008
1144
1038
16764

1737
2062

1762

2727

25354

25954

26254

2535+
29254
32594

25954
29854
32914

26254
3015#
3304

1787

2757

o —

ADRCNT=
BEGIN
BINWRD
BITC
=

14:40

CZDHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC.P11

DHNRC
DHRLVL
DHRVE
C
DHSCR

017656
017654
017676
017674
017652

017672
017670

017702
017700
021134

020774
021060
021160
016426
017710
017704
016732
016616
020436
017012
017714

EXITER
FREEZ
HALTS

HILIM

ICOUNT

2877
510

2907
514

2057

2487

1512

<87

37648

1087
1151
1517%
1836+

1091
1153
1536«
1867+

3893

57
3493
390%
391«
3553
350
3550
3560
461%
766%
1123+
1510%
1835+

2166%
2545%
2935+
3333+
3570
353
3540
3637+
460+
765+

1122+

1509»

2967
672
1587

2547

491

3763
4k

2167+
2546%
2936
3334+
171
425+
625
3207
3766
37654
88,
886
3883
3885
3887
3889
3891

2937

1537

(14
622

827

PAGE

CROSS REFERENCE TABLE -- USER SYMBOLS
2997
679
1612

3027

2577

3057

3177

1337
1662

1437

2637

649+
947

857

1107
1266
1611«
1936+

2194
2576w
2966+
3366w
3474
426w
625
3239

2276+
2666+
3056+
3434
37544
716

3335

39504
3888
38954
39014
39114
39214
39314

37604

1462

2367

2397

737
1071
1133
1436+
1761+

767
1073
1144

1461+
1786+

2086
2456+
2846+
3238+
3466

2113«

2876+
3270+
3467

2195

2222

690«
1063+
1435+

712+
1083+
1460+
1785+
2112«

2486+

3894

39414
39604

3575
392
35634
3539w
38824
35804
484w
796
1143+
1535+
1860+

2193+
575+
2965+
3365+
35754
3774k
35694
3663
483«
795w

1142+

1534w

37714
3496~

507~
826+

1169+

1560+
1885+

3521«

3526

3544

553
886+

576+
916+
1310+
1635+
1960«

1265+
1610+
1935+

2220+
2605+
2995~
3397«

2275
2665+
3055~
3464+

2305+
2695+
3085+
3578

36794
506+
825+
168+

552#
885+
P64

915+
1309

—

DHLPR

14:40

559+

1609+

575+

1634+

3555

3561+

37654

3822+

646+

668+
1036+
1410+
1735+

1006+
1385+
1710+

621
1359

1684

1760+

2035
2395+
2785+
3175+

2060+~
2425+
2815«
3205+

2085+«
2455«
2845+
3237+

645~
1005+
1384
1709+«

1035«
1409+
1734

667+

689+
1062+
1434
1759~

2485+
2875«
3269+

711+
1082+

1450

1784+

736+
1103+
1485+
1810+

2139«
2515+
3301«

735¢
1102+
1484+
1809~

CZDHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC.P11

1834

INBUF
INIFLG
INSTER=
INSTR =
INSTRE
INSTRG
INSTR1

INSTR?

LAST
LIGHTS=
LIMITS
LOBITS
LOGICA
LOLIM
LPCNTY

MCRLF
MDATA

MEPASS

MPFAIL
MM
MR
MRE GAD
MSG
MTITLE
MTSTPC
MVECTO
N

020400
017744
104404
104403

017176
017104
017116
017204
017750
177570

017316
017370
016464
017362
017722
020235
020424
020325
020240
020231
020337
020175
017120
020716
020343

3495+«

Sou
3653
3639+

373
3636
3517«

3687
3706
3494
3821
3629

1884+

2219+
2604+

2996+

3396+
38734

1909+
2246+
2634+
3024+
3432+

429+

37854

617

438

3543+

37874

36814

3682

36784
3520+

372764

TABLE =~=- USER SYMBOLS

1934«

2074w
2664
3054+
3465+

1959+

1984«

2304+
2694+
3084+
3518

2334+
2724
3114~
37754

3666

3668

505+

528+
854+

SEQ 0087

2009+
2364+
2754«
3144

2034*
2394
2784«
3174

2059+
2424+
2814«
3204+

2084«
2454+
2844+
3236+

2138+
2514+
2904+
3300+

3823+

38774

451

020153
000001

OCTAS(C= 104402
OCTASN
017372

104405
017206
017236
017312
017706
PFAIL
017752
PFTAB
020106
POPRO
012600
POP1SP- 005726
POP2SP= 022626
PARAM PARAMS
PARAM1
PARERR
PASCNT

2165+
2544
2934+
3332«
3615
394
3674
3664
36284
26114
36134
3622

14:40
PAGE 78
CRCSS REFERENCE

177776

PUSHRO- 010046
PUSH1S-~ 005746
PUSHZS 024646

3566
419

3649
3498
37914

434
734
1101«
1483«
1808+

2137+
2513
2903+
3299+

3664

824+

1167+
1558+
1883«

2218+
2603+
2993+
3395+«

1215+
1583«
1908~

2245+
2633
3023+
3430

551«
884«

1263+
1608+
1933«

2273«
2663
3053«
3463

S74x

914«
1308+
1633+
1958«

2303«
2693+
3083+
3813«

666
1034+
1408+
1733«

2058+
2423+
2813+
3203+

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78 10:02

RESREG

016746

RESTAR
RESTRT

020010
016474

RETRN
RSOS

017712
017610

RESOS = 104407
SAVPC
SAVRO
SAVR1
SAVRZ
SAVR3
SAVRG
SAVRS
SAVSP
SAVOSP=

SCOPE

- 104400

SCOPER
SCOPE1=
SCOP1IR
SPACNT=
STACK =
START

STFLG
Sv05
SVOSP
SWR
Sw00

017742
017724
017726
017730
017732
017734
017736
017740
104406

016500
104410
01
017545
021360
001000

017746
017556
017550

= 177570
= 000001

SwO1
SwO2
Sw03
SWO4
SWO05
Sw06
SW08
Sw09

=
=
=
=
=
=
=

Sw13
SW14
W15

= 020000
= 040000
= 100000

SW10
SW11
Swi12

TEMP
TKCSR
TKDBR
TPCSR
TPDBR
TRPOK
TRPSRvV

000002
000004
000010
000020
000040
000100
000400
001000

= 002000
= 004000
= 010000

020412
017642
017644
017646
017650
017032
017020

14:40
PAGE 79
CROSS REFERENCE

3565
3799
3500
3704

35684
3805#
35064
3568

37414
3582
3737«
3736+
3735«
2736+
3733«
3732«
37834

3868
3728+
3741
3742
3743
3744
3745
3746
3798+

756
1116
1500
1825

786
1136
1525
1850

443

3694
3634

2156
2534
2924
3322
35114
3714
35324
3692«

S7#4

355

388+«

37324
37c8%
544
374
364
3S#
b1X
334

447~

3522+

TABLE == USER SYMBOLS

3524

37724

3824

SEQ 0088

3827

3545
475

2183
2564
2954
3354
3861

2474
3258

3869
3710

386

3854

3462

2814

3513

3515

448

3867
398
398
436

324

304
2%
28
274
264
25
244
23
3696
2617
3619
3601
3606

3815+«
27504
3623
3624
3623«

352

35884

3591

3532
3511
351§

2576

3539
3513
3816+

37514
37524
3753

38754

3532

3539

3569

3576

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MaY-78 10
TRPTAB
TYPDAT
TYPE
=
TYPER

TYPMSG
mn
110

7100
1101
1102
1103
7104
1105
1106
1107
TM
T110

020356
016734
104401
017052

01671¢
001274
002140

1116
1117
112
7120
1121
1122
7123
7124
1125
1126
1127
713
1130
1131
1132
7133
T134
7135
T136
T137
T14
1140

010236
010336
010436
010536
010636
010736
011036
011142
002234
011246
011352
011456
011562
011666
011772
012076
012202
002314
012306
012412
012516
012622
012726
013032
013136
013242
002374
013346
013452
013556
013662
013766
014072
014176
014302
002454
014406

7143
T144
7145
T146
1147

014722
015026
015132
015246
015362

N
1112

1113
1114
1115

T15

002540

14:40
PAGE 80
CROSS REFERENCE

38614
35644
393
3862
35594
4594

651

3493

TABLE =-- USER SYMBOLS

3562

3613

3628

SEQ 0089

3686

3716

3820

CZDHA-C MACY11 30A(1052)
23-AUG-78
15-MAY-78 10:02
CZDHAC .P11

143
144
145
166
47
15
150
151
152
153
154
155
156
157
T6
160
161
162
63
164

165
66
167
17

003244
003332
003420
003506
003574
001464
003662
003736
004012
004066

004162
004216
004346
004476
001560
004626
004716

005006

005076
005166
005256
005346
005436
001654
005526
005616
005706
005776
006156
006246
006336
001750
006426
006516
006606
006676

006766

007056
007146
007236
002044

170
171
172

007326
007416
007506

174
175

007666
007756

173

007576

WV‘NN—'—'—'—-'O?
= b d ed b
TXTS < L4423 33 SXTELLTYLRY AN
RN

142

002626
002714
001370
003002
003070
003156

34294
34620

OO\ WSS 8 S SN
NN
O 00 VHANO N0 NN O OWWNINONION =000

116"
17
T2
120
121
122
123
124
125
126
127
13
130
131
132
133
13,
135
136
137
T4
60
141

016156
016302

ANS
Y

1156
1155

7834

14:40
PAGE 81
CROSS REFERENCE

m7
TABLE =-- USER SYMBOLS

SEQ 0090

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDKAC.P11
15-MAY-78 10:02
176
177
VEC]

N 7
14:40 PAGE 82
CROSS REFERENCE TABLE =-- USER SYMBOLS

010046
010136
001060

20584
2083#
395

WRDCNT
017542
X
= 000000
XBIT
= 000000

3690
14
13014

3718+«

37214

16764

20764

22654

27154

31954

597

6004

620

6234

644

6474

VEC2

001070

= 000154

397

7374

8
5
114
83
408

2333
29164
2723
29064
3113
\

= 000011

= 021162

874
112
138
164

190

216

3984
4004

459

764

1833
19864
2164

4624

7674

18364
2008
21674

482

794

1858
20114
2191

4854

7974

18614
2033
21944

505

824

18864
2058
22218

2423
26064
2813
2996#
3203
3684

2363
25464
2753
29364
3143

23664
2573
27564
2963
31660

2393
25764
2783
29664
3173

2394
2603
27864
2993
31764

363

3644

3654

3664

3674

168

170

172

166

192

218

90
116
142
194

220

92
118
144
196

222

94
120
146
198

224

8274

883
2034
2218

23364
2543
27264
2933
31164
88
114
140

5084

666

96
122
148
174

200

226

98
124
150

176

202

228

SEQ 0091

528

664
854

3
o4
1908
20614
2245

5314

551

5544

574

5774

884

8874

914

9174

688

6914

061
2184
433
5864
1758

1064#
1263
14364
1608
17614

8574

710

1081
2664
458
16114
1783

24264
2633
28164
3023
32064

19114
2083
22484

2453
26364
2843
30264
3235

1933
2084
2273

19364
2110
22764

3694

3704

3714

3724

100
126
152
178

204

230

102
128
154
180

206

232

264564
2663
28464
3053
32384
104
130
156
182

208

2483
26664
2873
30564
3267
1
132
158
184

210

236

7134

10844
1308
164614
1633
17864

734

1101
13114
1483
16364
1808

1958
21134
2303

19614
2137
23064

108
134
160

110
136
162

212

214

24864
2693
28764
3083
32704

186

238

2513
26964
2903
3084
3299

188

240

CZDHA-C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-mMaY-78 10:02

CODEMI

HLT

REGTST
REGTSZ
REGTS3

REGTSS
REGTS6

REGTS?7
RGADRS
TRPDEF
TS

.BUFFE
.CATCH
.ENDCO
.EOP
.ERROR
.ERRTA
.HEADE
.INSTR
.MSG
.OCTAS
.PARAM
PFAIL
.POINT
.RESRE
. SAVRE
. SCOPE

.SCOP1
.SETVE
.START
.SYMBO
. TRPDE

3764

6C7H

776
994
1250
1449
1643
1824
2018

425

469

492

2209

784
1016
1277
1468
1649
1843
2024

2229

806
1024
1286
1474
1668
1849
2043

2886
3103
3345

3126
3453

515

2236

2256

836
1054
1318
16499
1693
1874
206

3133
3377

3156
3385

727
1057
1157

757
1077
1205

787
1097
1253

1651

1676

1701

1726

2026

638
1301

2051

660
1326

794
1215
1633

2008
2423
2873
337

14
14
#
14
1%
14
14
14
14
#
14
1#
1w
1
1w
Y J

14
»
1»
1Y4
14

824
1263
1658

2033
2453
2903
3363

3870
86
3960
3486
3536
3879

3608
3828
3683
3632
3788
3748
3739
3725
3507

3529
344
376
20
358

854
1308
1683

2058
2483
2933
3395

522

365
505

884
1333
1708

2083
2513
2963

702

2263

2286

3163
3409

3186
3417

3193
3442

3217
3450

3225
3475

3249
3483

937

1651

1476

817
117

2805
3259

364
482

680

934
1190
1399
1593
1774
1968
215

2775
3227

499

363
459

658

926
1181
1393
1574
1768
1949
2148

2745
3195

476

»
1»

630

904
1154
1374
1568
1749
1943
2128

2130

453

2715
3165

607

896
1134
1368
1549
1743
1924
2121

2103

2325

584

874
1114
1349
1543
1724
1918
2101

2076

2295

561

SEQ 0092

866
1094
1343
1524
1718
189,
2094

704
1376

2265

844
1074
1324
1518
1699
1893
2074

682
1351

4534

2685
3135

538

814
1046
1298
1493
1674
1868
c049

4S3a
453
453

4«53
453

14:40
PAGE 84
CROSS REFERENCE TABLE =-- MACRO NAMES

1751

2355
545

366
528

914
1358
1733

2110
2543
2993

847
1137

2293

877

2316

907

2383

2406

2413

3257

3281

3066
3289

3313

3321

967

997

1027

1501

1526
1901

1926

1951

1976

2001

2475

2505

2535

2565

2595

2625

2655

370
620

371
644

2157

2184

221

2238

2835
3291

2865
3323

2895
3355

2925
3387

2385

568

367
551

944
1383
1758

2137
2573
3023

2415
591

368
574

974
1408
1783

2164
2603
3053

1826

2445
614

369
597

1004
1433
1808

2191
2633
3083

754

2376

2323

1426
1801

746

964
1229
1624
1618
1799
1993
2182

14601

1776

725

956
102
1418
1599
1793
1974
2175

1851

1034
1458
1833

2218
2663
3113

2346

1876

2955

1061
1483
1858

2245
2693
3143

2353

2985

666

1081
1508
1883

2273
2723
3173

1551

3015

688

1576

3045

710

1601

3075

734

986
1238
1443
1624
1818
1999
2202

1626

3105

764

110

1121

1141

1167

1533
1908

1558
1933
2333

1583
1958
2363

1608
1983

2303
2755
3203

2783
3235

2813
3267

2393
2843
3299

CZDHA=C MACY11 30A(1052)
23-AUG-78
CZDHAC.P11
15-MAY-78
10:02
.TRPSR
.TRPTA
.TYPER
.VARIA

1#
14
1w
‘e

3583
3858
3596
3767

. ABS.

021162

000

ERRORS DETECTED:

CZDHAC .BIN, CZDHAC.LST/CRF
/SOL/NL : TOC=C ZDHAC . SML , CZDHAC .P11

RUN-TIME: 8 13 1 SECONDS

RUN-TIME RATIO: 101/2424.2
CORE USED:
11k
(21 PAGES)

14:40 PAGE 85
CROSS REFERENCE TABLE -- MACRO NAMES

SEQ 0093