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AH-T002B-MC

September 1982

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Document:	CVCDAB0 MDE-T-11 MEM SIM DIAG AH-T002B-MC SEP 1982 bw
Order Number:	AH-T002B-MC
Revision:	000
Pages:	149
Original Filename:	CVCDAB0__MDE-T-11__MEM_SIM_DIAG__AH-T002B-MC__SEP_1982_gray.pdf

OCR Text

B MC,

it
s QIEIHRN

MA
IN
DE
USA

—

‘

USER DOCUMENTATION
MACY11 30A(1052)
| CVCDAB.P11
17=JUN=-82 11:26

17-JUN-82

PAGE
1

SEQ 0001

.REM &
IDENTIF ICATION

;

PRODUCT CODE:

AC=T000B=MC

;

PRODUCT NAME:

CVCDABC MDE/T=11 MEM SIM DIAG

PRODUCT DATE:

OCTOBER 1982

MAINTAINER:

DIAGNOSTIC ENGINEERING

THE INFORMATION IN THIS DOCUMENT IS
AND

SHOULD

SUBJECT

CHANGE WITHOUT

NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL

EQUIPMENT CORPORATION.

DIGITAL EQUIPMENT CORPORATION ASSUMES NO

RESPONSIBILITY FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMENT.

NO RESPONSIBILITY IS ASSUMED
FOR
SOFTWARE ON EQUIPMENT THAT IS NOT

AFFILIATED COMPANIES.

THE

USE

SUPPLIED

RELIABILITY

DIGITAL

THE FOLLOWING ARE

DIGITAL
DEC

TRADEMARKS OF DIGITAL EQUIPMENT CORPORATION:
PDP

DECUS

—

12:02

NOTICE

UNIBUS
DECTAPE

MASSBUS

OR ITS

H?C:Veg‘l 30A(1052) 17-JuN-82 12:02 PAGES

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SEQ 0002

REVISION HISTORY

REVISION
A

DATE
SEPTEMBER 1981

OCTOBER 1982

REASONS

FIRST RELEASE

DOCUMENTATION CHANGE

USER DOCUMENTATION

17-JUN-82 11:26

WVSHNWN=O
NOWVMS
W =0

DD
D

TABLE OF CONTENTS

GENERAL INFORMATION
PROGRAM ABSTRACT

SYSTEM REQUIREMENTS

RELATED DOCUMENTS AND STANDARDS
DIAGNOSTIC HIERARCHY PREREQUISITES
ASSUMPTIONS

OPERATING INSTRUCTIONS
COMMANDS
SWITCHES

FLAGS
HARDWARE QUESTIONS
SOF TWARE QUESTIONS

EXTENDED P-TABLE DIALOGUE

QUICK STARTUP PROCEDURE

O
©

DEVICE INFORMATION TABLES

TEST SUMMARIES

PERFORMANCE AND PROGRESS REPORTS

ERROR INFORMATION

CVCDAB.P11

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CVCDAB.P11

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1.0

GENERAL INFORMATION

1.1

PROGRAM ABSTRACT

12:02

E
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SEQ 0004

THE MDE/T=11 MEMORY SIMULATOR DIAGNOSTIC WILL TEST ALL THE LOGIC ON THE

MEMORY SIMULATOR MODULE EXCEPT THAT LOGIC PERTAINING TO THE SYSTEM
BUS.
THE DIAGNOSTIC WILL TEST ALL BITS IN CONTROL REGISTER 0, CONTROL REGISTER 2, CONTROL REGISTER 4, AND CONTROL REGISTER 6.
THE
DIAGNOSTIC WILL TEST THE 1K BY 4 MAP PROTECTION RAM'S AND ASSOCIATED
LOGIC, MODULE SELECT RAM O, MODULE SELECT RAM 1, AND THE FOUR 4K BY
16 MEMORY SIMULATOR RAM'S.
THE DIAGNOSTIC IS CAPABLE OF TESTING ONE
TO EIGHT MEMORY SIMULATOR MODULES SEQUENTIALLY.

IN ORDER TO TEST THE SYSTEM BUS LOGIC, ANOTHER DIAGNOSTIC MUST BE
USED. THIS OTHER DIAGNOSTIC, VIA THE STATE ANALYZER MODULE AND THE

TARGET EMULATOR MODULE, WILL TEST THE SYSTEM BUS LOGIC ON THE MEMORY SIMULATOR MODULE.
THIS DIAGNOSTIC HAS BEEN WRITTEN FOR USE WITH THE DIAGNOSTIC
RUNTIME SERVICES SOFTWARE (SUPERVISOR).
THESE SERVICES PROVIDE
THE INTERFACE TO THE OPERATOR AND TO THE SOF TWARE ENVIRONMENT.
THIS PROGRAM CAN BE USED WITH XXDP+, ACT, APT, SLIDE AND PAPER
TAPE.
FOR A COMPLETE DESCRIPTION OF THE RUNTIME SERVICES, REFER
TO THE XXDP+ USER'S MANUAL.
THERE IS A BRIEF DESCRIPTION OF
THE RUNTIME SERVICES IN SECTION 2 OF THIS DOCUMENT.

NOTE:

1 .2
1

2
3

5
6.
&

8.
1.3

THIS PROGRAM HAS NOT BEEN TESTED IN THE APT ENVIRONMENT, HOWEVER,
THE APT INTERFACE HAS BEEN PROVIDED IN THE DIAGNOSTIC.

SYSTEM REQUIREMENTS
LSI=11 OR EQUIVALENT TYPE CPU WITH Q-BUS

MINIMUM OF 16K WORDS OF MEMORY

CONSOLE TERMINAL AND CONTROLLER
MDE/T=11 BACKPLANE AND CABLES
MEMORY SIMULATOR MODULE(S) (M8740)
MXV11 MODULE AND MDE/T-11 ROMS
STORAGE DEVICE WITH CONTROLLER (OPTIONAL)

XXDP+ MEDIA FOR STORAGE DEVICE (OPTIONAL)
RELATED DOCUMENTS AND STANDARDS

CHQUS? XXDP+ USER'S MANUAL (THE '*?*' IN CHQUS INDICATES THE REVISION
LEVEL OF THE DOCUMENT. AT THE TIME THIS PROGRAM WAS WRITTEN, THE
REVISION LEVEL WAS "E'’.

1.4

DIAGNOSTIC HIERARCY PREREQUISITES

ALL HARDWARE THAT IS SPECIFIED IN SECTION 1.2 OF

MUST BE OPERATIONAL AND FREE OF ALL FAULTS.

1.5

ASSUMPTIONS

2.0

OPERATING INSTRUCTIONS

THIS DOCUMENT

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THIS SECTION CONTAINS A BRIEF DESCRIPTION OF THE RUNTIME SERVICES.
FOR DETAILED INFORMATION, REFER TO THE XXDP+ USER'S MANUAL (CHQUS).

2.1

COMMANDS

THERE ARE ELEVEN LEGAL COMMANDS FOR THE DIAGNOSTIC RUNTIME SERVICES
(SUPERVISOR).
THIS SECTION LISTS THE COMMANDS AND GIVES A VERY
BRIEF DESCRIPTION OF THEM.
THE XXDP+ USER'S MANUAL HAS MORE DETAILS.

COMMAND
START

EFFECT
START THE DIAGNOSTIC FROM AN INITIAL STATE

RESTART

START THE DIAGNOSTIC WITHOUT INITIALIZING

PROCEED

CONTINUE FROM AN ERROR HALT

CONT INUE

EXIT
ADD

DROP
PRINT
DISPLAY
FLAGS

ZFLAGS

CONTINUE AT TEST THAT WAS INTERRUPTED (AFTER “C)

RETURN TO XXDP+ MONITOR (XXDP+ OPERATION ONLY!)
ACTIVATE A UNIT FOR TESTING (ALL UNITS ARE
CONSIDERED TO BE ACTIVE AT START TIME
DEACTIVATE A UNIT
PRINT STATISTICAL INFORMATION (IF IMPLEMENTED

BY THE DIAGNOSTIC = SECTION 4.0)

TYPE A LIST OF ALL DEVICE INFORMATION
TYPE THE STATE OF ALL FLAGS

(SEE SECTION 2.3)

CLEAR ALL FLAGS (SEE SECTION 2.3)

A COMMAND CAN BE RECOGNIZED BY THE FIRST THREE CHARACTERS.
YOU MAY, FOR EXAMPLE, TYPE ''STA'" INSTEAD OF '‘START'',

2.2

SWITCHES

THERE ARE SEVERAL SWITCHES WHICH ARE USED TO MODIFY SUPERVISOR OPERATiON.
THESE SWITCHES ARE APPENDED TO THE LEGAL COMMANDS.
ALL OF THE LEGAL

SWITCHES ARE TABULATED BELOW WITH A BRIEF DESCRIPTION OF EACH,
IN THE DESCRIPTIONS BELOW, A DECIMAL NUMBER IS DESIGNATED BY “DDDDD'.
SWITCH

EFFECT

/TESTS:LIST

EXECUTE ONLY THOSE TESTS SPECIFIED IN

/PASS :DDDDD

/FLAGS:FLGS

THE LIST.
LIST IS A STRING OF TEST
NUMBERS, FOR EXAMPLE - /TESTS:1:5:7-10.
THIS LIST WILL CAUSE TESTS 1,5,7.8,9,10 TO

BE RUN.
ALL OTHER TESTS WILL NOT BE RUN.
EXECUTE DDDDD PASSES (DDDDD = 1 TO 64000)
SET SPECIFIED FLAGS.

IN SECTION 2.3.

FLAGS ARE DESCRIBED

/EOP:DDDDD

REPORT END OF PASS MESSAGE AFTER EVERY

JUNITS:LIST

TEST/ADD/DROP ONLY THOSE UNITS SPECIFIED

DDDDD PASSES ONLY.

(DDDDD = 1

TO 64000)

IN THE LIST.
LIST EXAMPLE = /UNITS:0:5:10-12
USE UNITS 0,5,10,11,12 (UNIT NUMBERS = 0-63)

EXAMPLE OF SWITCH USAGE:

START/TESTS:1-5/PASS:1000/E0P:
100

[

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THE EFFECT OF THIS COMMAND WILL BE:

EXECUTED,

G
PAGE 6
1)

SEQ 00C6

TESTS 1 THRQUGH 5 WILL BE

2) ALL UNITS WILL TESTED 1000 TIMES AND 3) THE END OF

PASS MESSAGES WILL BE PRINTED AFTER EACH 100 PASSES ONLY.
SWITCH CAN BE_RECOGNIZED BY THE FIRST THREE CHARACTERS.
FOR EXAMPLE, TYPE '‘/TES:1-5'" INSTEAD OF '‘/TESTS:1-5",

YOU MAY,

BELOW IS A TABLE THAT SPECIFIES WHICH SWITCHES CAN BE USED BY EACH
COMMAND.
TESTS

START

RESTART

CONT INUE

PASS

PROCEED

FLAGS

EOP

UNITS

€ 3¢ > >x

X
X
X

DROP
ADD

X
X

DISPLAY

FLAGS

2FLAGS
EXIT

FLAGS ARE USED TO SET UP CERTAIN OPERATIONAL PARAMETERS SUCH AS

LOOPING ON ERROR.

ALL FLAGS ARE CLEARED AT STARTUP AND REMAIN

CLEARED UNTIL EXPLICITLY SET USING THE FLAGS SWITCH.
FLAGS
ARE ALSO CLEARED AFTER A START COMMAND UNLESS SET USING THE

FLAG SWITCH.
THE ZFLAGS COMMAND MAY ALSO BE USED TO CLEAR
ALL FLAGS.
WITH THE EXCEPTION OF THE START AND ZFLAGS COMMANDS,
NO COMMANDS AFFECT THE STATE OF THE FLAGS;
THEY REMAIN SET OR

CLEARED AS SPECIFIED BY THE LAST FLAG SWITCH.
FLAG

EFFECT

HOE

HALT ON ERROR = CONTROL IS RETURNED TO
RUNTIME SERVICES COMMAND MODE

LOE
IER*
IBE*
IXE*
PRI
PNT

LOOP ON ERROR
INHIBIT ALL ERROR REPORTS
INHIBIT ALL ERROR REPORTS EXCEPT
FIRST LEVEL

(FIRST LEVEL CONTAINS

ERROR TYPE, NUMBER, PC, TEST AND UNIT)
INHIBIT EXTENDED ERROR REPORTS (THOSE
CALLED BY PRINTX MACRO'S)

DIRECT MESSAGES TO LINE PRINTER
PRINT TEST NUMBER AS TEST EXECUTES

BOE
UAM
ISR

‘BELL'' ON ERROR
UNATTENDED MODE (NO MANUAL INTERVENTION)
INHIBIT STATISTICAL REPORTS (DOES NOT

IDR

STATISTICAL REPORTING)
INHIBIT PROGRAM DROPPING OF UNITS

ADR

Lor

APPLY TO DIAGNOSTICS WHICH DO NOT SUPPORT
EXECUTE AUTODROP CODE

LOOP ON TEST

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EXECUTE EVALUATION (ON DIAGNOSTICS WHICH
HAVE EVALUATION SUPPORT)

*ERROR MESSAGES ARE DESCRIBED IN SECTION 3.1
SEE THE XXDP+ USER'S MANUAL FOR MORE DETAILS ON FLAGS.
YOU MAY
SPECIFY MORE THAN ONE FLAG WITH THE FLAG SWITCH.
FOR EXAMPLE,

TO CAUSE THE PROGRAM TO LOOP ON ERROR, INHIBIT ERROR REPORTS
AND TYPE A "BELL'' ON ERROR, YOU MAY USE THE FOLLOWING STRING:
/FLAGS:LOE:IER:BOE

2.4

HARDWARE QUESTIONS

WHEN A DIAGNOSTIC IS STARTED, THE RUNTIME SERVICES WILL PROMPT
THE USER FOR HARDWARE INFORMATION BY TYPING '‘CHANGE WW (L) ?*'

YOU MUST ANSWER '‘Y'' AFTER A START COMMAND UNLESS THE HARDWARE
INFORMATION HAS BEEN ‘‘PRELOADED'’' USING THE SETUP UTILITY (SEE
CHAPTER 6 OF THE XXDP+ USER'S MANUAL).
WHEN YOU ANSWER THIS
QUESTION WITH A *'v*', THE RUNTIME SERVICES WILL ASK FOR THE NUMBER
OF UNITS (IN DECIMAL).
VYOU WILL THEN BE ASKED THE FOLLOWING
QUESTIONS FOR EACH UNIT.

CSR ADDRESS:
DEVICE NUMBER:

2.5

SOFTWARE QUESTIONS

AFTER YOU HAVE ANSWERED THE HARDWARE QUESTIONS OR AFTER A RESTART
OR CONTINUE COMMAND, THE RUNTIME SERVICES WILL ASK FOR SOF TWARE
PARAMETERS.
THESE PARAMETERS WILL GOVERN SOME DIAGNOSTIC SPECIFIC

OPERATION MODES.
YOU WILL BE PROMPTED BY ‘‘CHANGE SWw (L ?**
IF YOU WISH TO CHANGE ANY PARAMETERS, ANSWER BY TYPING
*'Y*'.,
THE SOFTWARE QUESTIONS AND THE DEFAULT VALUES ARE DESCRIBED
IN THE NEXT PARAGRAPH(S).
THERE ARE NO SOFTWARE QUESTIONS IN THIS PROGRAM.,

2.6

EXTENDED P-TABLE DIALOGUE

WHEN YOU ANSWER THE HARDWARE QUESTIONS, YOU ARE BUILDING ENTRIES

IN A TABLE THAT DESCRIBES THE DEVICES UNDER TEST.

THE SIMPLEST

WAY TO BUILD THIS TABLE IS TO ANSWER ALL QUESTIONS FOR EACH

UNIT TO BE TESTED.

IF YOU HAVE A MULTIPLEXED DEVICE SUCH AS

A MASS STORAGE CONTROLLER WITH SEVERAL DRIVES OR A COMMUNICATION

DEVICE WITH SEVERAL LINES, THIS BECOMES TEDIOUS SINCE MOST OF
THE ANSWERS ARE REPETITIOUS.
TO ILLUSTRATE A MORE EFFICIENT METHOD,

A FICTIONAL DEVICE, THE XY11.

SUPPOSE YOU ARE TEST I NG

SUPPOSE THIS DEVICE CONSISTS OF

A CONTROL MODULE WITH EIGHT UNITS (SUB-DEVICES) ATTACHED TO IT
THESE UNITS ARE DESCRIBED BY THE OCTAL NUMBERS 0 THROUGH 7.
THERE

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IS ONE HARDWARE PARAHETER THAT CAN VARY AMONG UNITS CALLED THE

Q-FACTOR.
THIS Q=FACTOR MAY BE 0 OR1. BELOW IS A SIMPLE WAY
TO BUILD A TABLE FOk ONE XY11 WITH EIGHT UNITS.

# UNITS (D) ?

B8<(R>

UNIT 1
CSR ADDRESS (0) ?
160000<CR>
SUB-DEVICE # (0) ? 0<CR>

Q=FACTOR (0) 0 ?

1<CR>

UNIT 2
CSR ADDRESS (0) ?
160000<CR>
1<CR>
SUB-DEVICE # (0) ?
Q=FACTOR (0)

0<CR>

UNIT 3
CSR ADDRESS (0) ?
160000<CR>
SUB-DEVICE # (0) ? 2<CR>
Q-FACTOR (0) 0 ?

<(R>

UNIT &
CSR ADDRESS (0) ?
160000<CR>
SUB-DEVICE # (0) ?
3<CR>
Q-FACTOR (0) 0 ?

<(R-

UNIT 5
CSR ADDRESS (0) ?

160000<CR>
SUB-DEVICE # (0) ?
&<(R>
Q=FACTOR (0) 0 ?
<(CR>

UNIT 6
CSR ADDRESS (0) ?
160000<CR>
SUB-DEVICE # (0) ?
5<CR>

Q-FACTOR (0) 0 ?

<(CR>

UNIT 7

CSR ADDRESS (0) ?
160000<CR>
SUB-DEVICE # (0) ? 6<CR>
Q=FACTOR (0) 0 ?
1<CR>

UNIT 8
CSR ADDRESS (0)
160000<CR>
SUB-DEVICE # (0) ?
7<CR>
Q-FACTOR (0)

<(R>

NOTICE THAT THE DEFAULT VALUE FOR THE Q-FACTOR CHANGES WHEN A
NON-DEFAULT RESPONSE IS GIVEN.

MULTIPLE UNITS!

BE CAREFUL WHEN SPECIFYING

AS YOU CAN SEE FROM THE ABOVE EXAMPLE, THE HARDWARE PARAMETERS
DO MOT VARY SIGNIFICANTLY FROM UNIT TO UNIT.
THE PROCEDURE SHOWN 1S
NOT VERY EFFICIENT.
THE RUNTIME SERVICES CAN TAKE MULTIPLE UNIT SPECIF
IFICA T IONS HOWEVER.
LET'S BUILD THE SAME TABLE USING THE MULTIPLE SPECIFICATION

SEQ 0008

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FEATURE.

# UNITS (D) ?

B8<(R>

UNIT 1
CSR ADDRESS (0) ?
160000<CR>
SUB-DEVICE # (0) ? 0,1<(CR>
Q=FACTOR (0) 0 ?
1,0<CR>

UNIT 3

CSR ADDRESS (0) ?
160000<CR>
SUB-DEVICE # (0) ? 2-5¢<(R>
Q=FACTOR (0) 0 ? O<CR>

UNIT 7

CSR ADDRESS (0) ?
160000<CR>
SUB-DEVICE # (0) ? 6,7<(R>
Q=FACTOR (0) 0 ?
1<CR>
AS YOU CAN SEE IN THE ABOVE DIALOGUE, THE RUNTIME SERVICES WILL

BUILD AS MANY ENTRIES AS IT CAN WITH THE INFORMATION GIVEN IN ANY
ONE PASS THROUGH THE QUESTIONS.
IN THE FIRST PASS, TWO ENTRIES
ARE BUILT SINCE TWO SUB-DEVICES AND Q-FACTORS WERE SPECIFIED.
THE
SERVICES ASSUME THAT THE CSR ADDRESS IS 160000 FOR BOTH SINCE IT

WAS SPECIFIED ONLY ONCE.

BUILT.

IN THE SECOND PASS,

FOUR ENTRIES WERE

THIS IS BECAUSE FOUR SUB-DEVICES WERE SPECIFIED.

THE

"'="* CONSTRUCT TELLS THE RUNTIME SERVICES TO INCREMENT THE DATA

FROM THE FIRST NUMBER TO THE SECOND.

2, 3, 4 AND 5 WERE SPECIFIED.

IN THIS CASE, SUB-DEVICES

(IF THE SUB-DEVICE WERE SPECIFIED

BY ADDRESSES, THE INCREMENT WOULD BE BY 2 SINCE ADDRESSES MUST
BE ON AN EVEN BOUNDARY.)
THE CSR ADDRESSES AND Q-FACTORS FOR
THE FOUR ENTRIES ARE ASSUMED TO BE 160000 AND O RESPECTIVELY

SINCE THEY WERE ONLY SPECIFIED ONCE.
SPECIFIED IN THE THIRD PASS.

THE LAST TWO UNITS ARE

THE WHOLE PROCESS COULD HAVE BEEN ACCOMPLISHED IN ONE PASS AS
SHOWN BELOW.
# UNITS (D)

B8<CR>

UNIT 1

CSR ADDRESS (0) ?
160000<CR>
SUB-DEVICE # (0) ?
0-7<CR>
Q@-FACTOR (0) 0 ?
0,1,0,...1,1<CR>
AS YOU CAN SEE FROM THIS EXAMPLE, NULL REPLIES (COMMAS ENCLOSING
A NULL FIELD) TELL THE RUNTIME SERVICES TO REPEAT THE LAST REPLY.

2.7 QUICK START-UP PROCEDURE

(XXDP+)

TO START=UP THIS PROGRAM:

1. BOOT XXDP+

2. ANSWER ANY QUESTIONS ASKED AND GIVE THE DATE.

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3. TYPE "R NAME'', WHERE NAME IS THE WAME OF THE BIN OR BIC
FILE FOR THIS PROGRAM

&. TYPE "'START''

5. ANSWER THE '‘CHANGE HW'' QUESTION WITH "'v*'
6. ANSWER ALL THE HARDWARE QUESTIONS
7. ANSWER THE "'CHANGE SW'' QUESTION WITH ‘W'
WHEN YOU FOLLOW THIS PROCELURE YOU WILL BE USING ONLY THE
DEFAULTS FOR FLAGS AND SOF TWARE PARAMETERS.
THESE DEFAULTS
ARE DESCRIBED IN SECTIONS 2.3 AND 2.5.

3.0 ERROR INFORMATION

* 2.1 TYPES OF ERROR MESSAGES
THERE ARE THREE LEVELS OF ERROR MESSAGES THAT MAY BE ISSUED BY
A DIAGNOSTIC: GENERAL, BASIC AND EXTENDED.
GENERAL ERROR MESSAGES
ARE ALWAYS PRINTED UNLESS THE ''IER'' FLAG IS SET (SECTION 2.3).
THE GENERAL ERROR MESSAGE IS OF THE FORM:

NAME
TYPE
NUMBER
ERROR MESSAGE

ON UNIT NUMBER

+WHERE.; NAME = DIAGNOSTIC NAME
TYPE

= ERROR TYPE

(SYS FATAL,

NUMBER = ERROR NUMBER

TST NUMBER PC:XXXXXX

DEV FATAL, HARD OR SOFT)

UNIT NUMBER = 0 = N (N IS LAST UNIT IN PTABLE)

TST NUMBER = TEST AND SUBTEST WHERE ERROR OCCURRED
PC:XXXXXX = ADDRESS OF ERROR MESSAGE CALL

BASIC ERROR MESSAGES ARE MESSAGES THAT CONTAIN SOME ADDITIONAL
INFORMATION ABOUT THE ERROR.
THESE ARE ALWAYS PRINTED UNLESS
THE ''IER'' OR '‘IBE'*' FLAGS ARE SET (SECTION 2.3).
THESE MESSAGES
ARE PRINTED AFTER THE ASSOCIATED GENERAL MESSAGE.

EXTENDED ERROR MESSAGES CONTAIN SUPPLEMENTARY ERROR INFORMATION
SUCH AS REGISTER CONTENTS OR GOOD/BAD DATA.
THESE ARE ALWAYS
PRINTED UNLESS THE °'‘IER'', “'IBE'' OR ''IXE'' FLAGS ARE SET (SECTION 2.3).

THESE MESSAGES ARE PRINTED AFTER THE ASSOCIATED GENERAL ERROR
MESSAGE AND ANY ASSOCIATED BASIC ERROR MESSAGES.

3.2 SPECIFIC ERROR MESSAGES
THE ERROR PRINTOUTS WILL USE THE FOLLOWING WORDS TO INDICATE ERROR

INFORMATION. A DESCRIPTION OF THE WORDS PRINTED OUT ARE AS FOLLOWS:
REG:
LOAD:
READ:

ONE OF THE MEMORY SIMULATOR MODULE'S CONTROL REGISTERS
DATA THAT WAS LOADED INTO THE CONTROL REGISTER
DATA THAT WAS READ FROM THE CONTROL REGISTER

MASK :

BITS IN THE CONTROL REGISTER THAT ARE NOT CHECKED

BAD:

DATA 'READ'‘ FROM THE CONTROL REGISTER WITH THE ‘MASK'’

GOOD:

EXPECTED CONTROL REGISTER DATA

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XXXXXX:

SEQ 0011

BITS CLEARED

SIX OCTAL DIGITS INDICATING THE DATA FOR THE ABOVE WORDS

THERE ARE FOUR ERROR NUMBERS ASSOCIATED WITH THIS DIAGNOSTIC.
NUMBERS AND THEIR MEANINGS ARE DESCRIBED BELOW:

ERROR
ERROR
ERROR
ERROR

NUMBER 1
NUMBER %
NUMBER
NUMBER 4

=~
=
=
=

ERROR
ERROR
ERROR
ERROR

DETECTED
DETECTED
DETECTED
DETECTED

CHECKING
CHECKING
CHECKING
CHECKING

CONTROL
CONTROL
CONTROL
CONTROL

THE ERROR

0
2
4
6

EXAMPLES OF EACH TYPE OF CONTROL REGISTER ERROR PRINTOUT ARE SHOWN BELOW:
*+ CONTROL REGISTER O ERROR MESSAGES *+
CVCDA DVC FTL ERR 00001 ON UNIT 00 TST 001 SUB 000 PC: XXXXXX

CONTROL REG 0 ERROR

LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX
THE ABOVE ERROR PRINTOUT IS GIVEN WHEN THE PROGRAM IS CHECKING CONTROL

REGISTER O AND NO OTHER CONTROL REGISTER INFORMATION IS NEEDED TO
DETERMINE THE FAULT. IF MORE CONTROL REGISTER INFORMATION IS NEEDED IN

BEIER:%N%?SELHE FAULT OF CONTROL REGISTER O, THE FOLLOWING ERROR REPORT

CVCDA DVC FTL ERR 00001 ON UNIT 00 TST 014 SUB 000 PC: XXXXXX

MAP PROTECT LOGIC ERROR

CONTROL REG 0 ERROR
= LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX
REG 2 = LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX

REG 4 = LOAD: XXXXXX READ: XXXXXX
REG 6 = LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX

IN THE ABOVE ERROR, REFER TO THE LINE INDICATING 'REG 0 ='" FOR CONTROL
REGISTER O ERROR INFORMATION.
THE REMAINING CONTROL REGISTER INFORMATION IS GIVEN TO INDICATE WHAT WAS LOADED INTO THOSE CONTROL REGISTERS
PREVIOUS TO THE ERROR.
THIS IS DONE TO AID THE USER IN DETERMINING THE
FAULT ON ERRORS WHICH NEED PREVIOUS CONTROL REGISTER SETUP.

THE ‘BAD''

INFORMATION FOR CONTROL REGISTERS OTHER THEN CONTROL REGISTER O SHOULD

EQUAL THE

'‘GOOD'' INFORMATION.

THE ‘BAD'* INFORMATION IS PROVIDED IN CASE

THE USER_PROCEEDS FROM AN ERROR, IN WHICH CASE, THE ‘BAD'‘ INFORMATION
MAY AID THE USER IF ANOTHER CONTROL REGISTER HAD FAILED.
THE ERROR

MESSAGE

‘MAP PROTECTION LOGIC ERROR'' INDICATES THE AREA OF LOGIC BEING

TESTED WHEN THE ERROR WAS DETECTED.

TIME OUT ERROR ADDRESSING CONTROL REG 0

THE ABOVE ERROR PRINTOUT IS GIVEN WHEN THE PROGRAM IS TRYING TO
ADDRESS CONTROL REGISTER O AND CAN'T.
THE PROGRAM THEN JUMPS
TO TIME OUT VECTOR #4.

*+ CONTROL REGISTER 2 ERROR MESSAGES ++
CDCDA DVC FTL ERRogOOOZ ON UNIT 00 TST 004 SuB 000 PC: XXi<XX

CONTROL REG 2 ERR

LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX

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THE ABOVE ERROR PRINTOUT IS GIVEN WHEN T HE PROGRAM IS CHECKING CONTROL

REGISTER 2 AND NO OTHER CONTROL REGISTER INFORMATION IS NEEDED TO
DETERMINE THE FAULT. IF MORE CONTROL REG I STER_INFORMATION IS NEEDED IN
DETERMINING THE FAULT OF CONTROL REGISTE R 2, THE FOLLOWING ERROR REPORT
WILL BE GIVEN.

CVCDA DVC FTL ERR 00002 ON UNIT 00 TST 014 SUB 000 PC: XXXXXX

MAP PROTS&E LOGIC ERROR

CONTROL
2 ERROR
REG 0 = LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX
REG 2 = LOAD: XXXXXX RCAD: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX

REG 4 = LOAD: XXXXXX READ: XXXXXX
REG 6 = LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX

IN THE ABOVE ERROR, REFER TO THE LINE INDICATING 'REG 2 ='' FOR CONTROL
REGISTER 2 ERROR INFORMATION.
THE REMAINING CONTROL REGISTER INFORMA=TION IS GIVEN TO INDICATE WHAT WAS LOADED INTO THOSE CONTROL REGISTERS

PREVIOUS TO THE ERROR.
THIS IS DONE TO AID THE USER IN DETERMINING THE
FAULT ON ERRORS WHICH NEED PREVIOUS CONTROL REGISTER SETUP. THE 'BAD''

INFORMATION FOR CONTROL REGISTERS OTHER THEN CONTROL REGISTER 2 SHOULD

EQUAL THE ''GOOD'' INFORMATION.

THE ‘BAD‘'’ INFORMATION IS PROVIDED IN CASE

THE USER PROCEEDS FROM AN ERROR, IN WHICH CASE, THE 'BAD'' INFORMATION
MAY AID THE USER IF ANOTHER CONTROL REGISTER HAD FAILED.
THE ERROR

MESSAGE ‘MAP PROTECTION LOGIC ERROR'* INDICATES THE AREA OF LOGIC BEING
TESTED WHEN THE ERROR WAS DETECTED.

TIME OUT ERROR ADDRESSING CONTROL REG 2
THE ABOVE ERROR PRINTOUT IS GIVEN WHEN THE PROGRAM IS TRYING TO
ADDRESS CONTROL REGISTER 2 AND CAN'T.
THE PROGRAM THEN JUMPS
TO TIME OUT VECTOR #4.

** CONTROL REGISTER & ERROR MESSAGE +*

CVCDA DVC FTL ERR 00003 ON UNIT 00 TST 006 SUB 000 PC: XXXXXX
CONTROL REG & ERROR
LOAD: XXXXXX READ: XXXXXX
ALL SIXTEEN BITS OF CONTROL REGISTER 4 ARE READ/WRITE BITS, THEREFORE,
ONLY TWO WORDS ARE NEEDED TO REPORT AN ERROR. THESE WORDS INDICATE THE
DATA THAT WAS LOADED INTO CONTROL REGISTER 4 AND DATA THAT WAS READ
FROM CONTROL REGISTER 4.

TIME OUT ERROR ADDRESSING CONTROL REG 4
THE ABOVE ERROR PRINTOUT IS GIVEN WHEN THE PROGRAM IS TRYING TO
ADDRECS CONTROL REGISTER & AND CAN'T.
THE PROGRAM THEN JUMPS
TO TIME OUT VECTOR #4.

*+ C(ONTROL REGISTER 6 ERROR MESSAGE ++

CVCDA DVC FTL ERR 00004 ON UNIT 00 TST 011 SuB 000 PC: XXXXXX
ERROR TYPE MESSAGE (SEE BELOW)
CONTROL REG 6 ERROR
REG 0 = LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX

SEQ 0012

REG 2

REG &
REG 6

17-JUN-82

12:02

PAGE 13

SEQ 0013

LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX
LOAD: XXXXXX READ: XXXXXX
LOAD: XXXXXX READ: XXXXXX MASK: XXXXXX GOOD: XXXXXX BAD: XXXXXX

IN THE_ABOVE ERROR, REFER TO THE LINE INDICATING 'REG 6 ="' FOR CONTROL

REGIS TER 6 ERROR INFORMATION.
THE REMAINING CONTROL REGISTER INFORMATl ON IS GIVEN TO INDICATE WAS WAS LOADED INTO THOSE REGISTERS PREVIOUS
10 THE ERROR,
THIS IS DONE TO AID THE USER IN DETERMINING THE FAULT

ON_ERRORS WHICH NEED PREVIOUS CONTROL REGISTER SETUP.
THE 'BAD'' INFORMATION FOR CONTROL REGISTERS OTHER THEN CONTROL REGISTER 6 SHOULD EQUAL
THE “'GOOD’* INFORMATION.
"
THE ERROR TYPE MESSAGE IN THE ABOVE ERROR REFURT WILL BE ONE OF THOSE
LISTED BELOW.
THESE MESSAGES ARE REPORTED TO HELP THE USER IDENTIFY
THE AREA OF LOGIC BEING TESTED IN WHICH THE ERROR WAS DETECTED.

ERROR TYPE MESSAGES ARE AS FOLLOWS:

THESE

DATA ERROR IN MAP PROTECTION RAM
ADDRESS SHORT IN MAP PROTECTION RAM
MAP PROTECT LOGIC ERROR
DATA ERROR IN MODULE SELECT RAM 0
DATA ERROR IN MODULE SELECT RAM 1
CHIP ENABLE ERROR = MODULE SELECT RAMS
MODULE SELECT RAM ADDRESSING ERROR
DATA ERROR IN MEMORY SIMULATOR RAM
CHIP ENABLE ERROR = MEMORY SIMULATOR RAM
4.0 PERFORMANCE AND PROGRESS REPORTS
AT THE END OF EACH PASS, THE PASS COUNT IS GIVEN ALONG WITH THE
TOTAL NUMBER OF ERRORS REPORTED SINCE THE DIAGNOSTIC WAS STARTED.

THE "EOP'' SWITCH CAN BE USED TO CONTROL HOW OF TEN THE END
OF PASS MESSAGE IS PRINTED.
SECTION 2.2 DESCRIBES SWITCHES.

5.0 DEVICE INFORMATION TABLES
CONTROL REGISTER 0 (163010)
15

IDH

BIT 15 = 1 READ DEVICE TYPE IN BITS 15-8. MEMORY
SIMULATOR DEVICE TYPE EQUALS 1 (400)

BIT 15 = 0 READ DEVICE NUMBER INTO BITS 11-8,

BITS 11-8 ARE USED TO SELECT THE DEVICE NUMBER OF

(K H
WRV H
RDV H

w
TMm

OVO
-

-2 —a

THE MEMORY SIMULATOR. THESE BITS MUST BE EQUAL TO
THE SETTING OF SWITCHES DEV 3, DEV 2, DEV 1 AND DEV 0.

WHWVON

USER DOCUMENTATION
??C;Z1 30A(1052)
17-JUN-82
CVCDAB.P1

8BIT H

CLOCK HIGH (R/W)
WRITE VIOLATION (READ ONLY)
READ VIOLATION (READ ONLY)

BIT 3 =18 BIT MODE. BIT 3 = 0 16 BIT MODE (R/W)

USER DOCUMENTAT
ION

CvCDAB.P11

MACY11 30A(1052)

17-JUN-82 11:26

MP H

CTSH

RSTH

17-JUN-82

12:02

PAGE 14

2
SEQ 0014 |

MAP PROTECT SELECT (R/W)

BIT 1

=1 MEMORY ACCESS FROM SYSTEM BUS. BIT 1 = 0

MEMORY ACCE‘S FROM LSI=11 BUS (R/W)
BIT O =1 RESET READ/WRITE VIOLATION F/F'S (R/W)

CONTROL REGISTER 2 (163012)
15-8

BITS 15-8 ARE NOT AVAILABLE IN CONTROL REGISTER 2

7
6

MSBRK W MEMORY SIMULATOR BREAK (READ ONLY)
WREN H MAP PROTECT RAM SIGNAL WRE W (READ ONLY)

UNUSED

ESRH

MAP PROTECT RAM SIGNAL MPIN H (READ ONLY)

BITS 3 AND 2 ARE USED

TO SELECT THE MEMORY SIMULATOR

RAM, MAP PROTECT RAM AND THE MODULE SELECT RAMS

3
2
1
0

BIT 3 = 0BIT
BIT 3 =0BIT
BIT 3 =1BIT
BIT 3 =18BIT
MSEL1 H (R/W)
MSELO H (R/W)

S = 0
2 =1
2 =0
2 =1

SELECT MEMORY SIMULATOR RAM
SELECT MODULE SELECT MEMORY 0
SELECT MAP PROTECT MEMORY
SELECT MODULE SELECT MEMORY 1

MSAD17 H MEMORY SIMULATOR ADDRESS 17 (R/W)

MSAD16 H MEMORY SIMULATOR ADDRESS 16 (R/W)

CONTROL REGISTER & (163014)
15

MSAD15 W MEMORY SIMULATOR ADDRESS 15 (R/W)

13
12

MSAD13 H MEMORY SIMULATOR ADDRESS 13 (R/W)
MSAD12 H MEMORY SIMULATOR ADDRESS 12 (R/W)

11
10

9
8
7
6
5

MSAD14 H MEMORY SIMULATOR ADDRESS 14 (R/W)

MSAD11 H MEMORY SIMULATOR ADDRESS 11 (R/W)
MSAD10 H MEMORY SIMULATOR ADDRESS 10 (R/W)

MSAD9 H
MSADS8 H
MSAD7 H
MSAD6 H
MSAD5S H

MEMORY
MEMORY
MEMORY
MEMORY
MEMORY

ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS

9 (R/W)
9 (R/W)
(R/%)
g (R/W)
(R/W)

MSAD3 H
MSAD2 H

MEMORY SIMULATOR ADDRESS
MEMORY SIMULATOR ADDRESS

3 (R/W)
2 (R/W)

MSADSG H

MSAD1 H

3
2
0O

MSADO H

SIMULATOR
SIMULATOR
SIMULATOR
SIMULATOR
SIMULATOR

MEMORY SIMULATOR ADDRESS
MEMORY SIMULATOR ADDRESS

MEMORY SIMULATOR ADDRESS

& (R/W)
1

(R/W)

0 (R/W)

CONTROL REGISTER 6 (163016)
WHEN THE MAP PROTECTION RAM IS SELECTED VIA CONTROL REGISTER 2,
THE FOLLOWING BITS ARE LOADED INTO OR READ FROM THE MAP PROTEC=TION RAMS VIA CONTROL REGISTER 6.

3
2

MUTB H
RDE H

MPINH

WREH

USER DOCUMENTATION
MACY11 30A(1052)
17-JUN-82 11:26
CV(DAB.P11

17-JUN-82

12:02

PAGE 15

WHEN MODULE SELECT RAM 0 OR 1 IS SELECTED VIA CONTROL REGISTER 2,
THE FOLLOWING BITS ARE LOADED INTO OR READ FROM MODULE SELECT

RAMS 0 OR 1 VIA CONTROL REGISTER 6.

3
2

EN3H
EN2H

ENOH

ENIH

WHEN THE MEMORY SIMULATOR RAMS ARE SELECTED VIA CONTROL REGISTER 2,
ALL 16 BITS ARE LOADED INTO AND READ FROM THE SIMULATOR MEMORY RAMS
VIA CONTROL REGISTER 6.

6.0 TEST SUMMARIES
TEST 1:
THIS TEST WILL CHECK THAT THE MEMORY SIMULATOR CAN BE SELECTED AND

INITIALIZED TO A KNOWN STATE.
THIS TEST WILL BE EXECUTED AT THE
BEGINNING OF EVERY TEST THAT FOLLOWS.
THE TEST WILL LOAD THE DEVICE
NUMBER INTO CONTROL REGISTER O AND CHECK THAT THE DEVICE NUMBER CAN
BE READ BACK CORRECTLY.
THE R/W BITS IN THE LOW BYTE ARE CHECKED TO
BE CLEARED.
THE READ ONLY BITS, WRV H AND RDV H, ARE NOT CHECKED. THE
TEST WILL LOAD THE DEVICE NUMBER AND THE SIGNAL I/D H INTO CONTROL

REGISTER O AND CHECK THAT THE DEVICE TYPE AND THE R/W BITS IN THE LOW
BYTE CAN BE READ BACK CORRECTLY.
THE TEST WILL THEN LOAD THE DEVICE
NUMBER AND THE SIGNAL RST H (RST H WILL CLEAR RDV AND WRV FLIP-FLOPS)
INTO CONTROL REGISTER O AND CHECK THAT THE DEVICE NUMBER AND THE
SIGNAL RST H ARE SET IN CONTROL REGISTER 0. THE OTHER R/W BITS AND THE

READ ONLY BITS (RDV H AND WRV H) ARE CHECKED TO BE CLEARED IN CONTROL

THE LAST PART OF REGISTER O TEST WILL BE TO CLEAR THE SIGNAL

RST H IN CONTROL REGISTER O AND CHECK THAT THE SIGNAL RST H WAS CLEARED

IN CONTROL REGISTER 0. THE OTHER BITS ARE CHECKED NOT _TO HAVE CHANGED.

THE TEST WILL CLEAR THE READ/WRITE BITS MSEL1 H, MSEL2 H, MSAD17 H, AND
MSAD16 H IN CONTROL REGISTER 2 AND CHECK THAT THESE BITS ARE CLEARED BY
READING CONTROL REGISTER 2.
THE TEST WILL ALSO CLEAR ALL MSAD BITS IN
CONTROL REGISTER & AND CHECK THAT ALL THE BITS WERE CLEARED.

TEST 2:
THIS TEST WILL CHECK CONTROL REGISTER O WITH BASIC PATTERNS.
&
NS.
THE TEST
WILL CHECK THAT THE R/W BITS RST H, CTS H, MP H, 8 BIT H AND (K H CAN

BE SET _AND CLEARED. THE READ ONLY BITS RDV H AND WRV H WILL BE CHECKED
TO BE ZERO WHEN THE SIGNAL RST H IS SET TO A ONE.
THE FOLLOWING TEST
PATTERNS WILL BE USED TO CHECK CONTROL REGISTER 0:
1. SET ALL R/W BITS TO A ONE

2. SET ALL R/W BITS TO A ZERO
3. SET RST H, MP H AND CK H TO EQL 1. SET CTS H + 8 BIT H EQL 0.
4. SET CTS H + 8 BIT H EQL 1. SET RST H, MP H, + CK H EOL 0.

TEST 3:
THIS TEST WILL CHECK THE READ/WRITE BITS IN CONTROL REGISTER 0 USING
A BINARY COUNT PATTERN., THE READ ONLY BITS WILL NOT BE CHECKED WHEN
THE SIGNAL RST H IS A ZERO, HOWEVER, WHEN RST H IS SET TO A ONE, THE

SEQ 0015

USER DOCUMENTATION
MACY11 30A(1052)
17=JUN-82 11:26
CvCDAB.P11

17-JUN-82

12:02

PAGE 16

2
SEQ 0016

READ ONLY BITS WILL BE CHECKED TO BE ZERO.

TEST &:
THIS TEST WILL CHECK THE READ/WRITE BITS IN CONTROL REGISTER 2 USING
BASIC PATTERNS.
THIS TEST WILL CHECK THAT THE SIGNALS MSAD16 H, MSAD17 H

MSELO H, AND MSEL1 H CAN BE SET AND CLEARED IN CONTROL REGISTER 2.
READ ONLY BITS ESR H, WREN H, AND MSBRK H ARE

THE

IGNORED DURING THIS TEST

ALONG WITH THE UNDEFINED BITS IN CONTROL REGISTER 2.

USED DURING THIS TEST ARE AS FOLLOWS:
1. SET ALL R/W BITS TO A ONE

2. SET ALL R/W BITS TO A ZERO
3. SET MSAD16 H + MSELO H EQL 1. SET MSAD17 H +

THE TEST PATTERNS

MSEL1 H EQL 0.

4. SET MSAD17 H + MSELY H EQL 1. SET MSAD16 H + MSELO W EQL 0.
TEST §:
THIS TEST WILL CHECK THE READ/WRITE BITS IN CONTROL REGISTER 2 USING
A BINARY COUNT PATTERN. THE BITS BEING TESTED ARE MSAD16 H, MSAD17 H,

MSELO H AND MSEL1 H.

THE READ ONLY BITS, ESR H, WREN H, MSBRK H, AND

THE UNDEFINED BITS, ARE IGNORED DURING THIS TEST.

TEST 6:
THIS TEST WILL CHECK ALL BITHE R/W BITS IN CONTROL REGISTER 4 USING

BASIC PATTERNS. ALL SIXTEEN BITS IN CONTROL REGISTER 4 ARE READ/

WRITE BITS. THESE BITS ARE CALLED MSAD15 H TO MSADO H. THE TEST
PATTERNS USED TO TEST CONTROL REGISTER & ARE AS FOLLOWS:

1. SET ALL BITS TO A ONE.

2. SET ALL BITS TO A ZERO
TEST 7:
THIS TEST WILL CHECX ALL THE R/W BITS IN CUNTROL REGISTER 4 USING
AN ALTERNATING ONES AND ZEROES PATTERN AND AN ALTERNATING ZEROES AND

ONES PATTERN.

TO EACH OTHER.

THIS TEST CHECKS THAT NO ADJACENT BITS ARE SHORTED
THE TEST PATTERNS USED ARE AS FOLLOWS:

1. LOAD CONTROL REGISTER 4 WITH 125252

2. LOAD CONTROL REGISTER & WITH 052525
TEST 8:

THIS TEST WILL CHECK THE LOW BYTE OF CONTROL REGISTER & USING A

BINARY COUNT PATTERN.
THE HIGH BYTE OF CONTROL REGISTER 4 WILL BE
CHECKED TO BE CLEARED DURING THIS TEST.
TEST 9:
THIS TEST WILL CHECK THE HIGH BYTE OF CONTROL REGISTER & USING A
BINARY COUNT PATTERN. THE LOW BYTE OF CONTROL REGISTER & WILL BE
CHECKED TO BE CLEARED DURING THIS TEST.

TEST 10:
THIS TEST WILL CHECK THAT THE SIGNAL MSBRK W IN CONTROL REGISTER 2

CAN BE SET TO A O WHEN THE SIGNALS RST H AND MP H ARE SET TO A ONE

. USER DOCUMENTATION
. CVCDAB.P11

MACY11 30A(1052)
17=JuN-82 11:26

17-JUN-82

IN CONTROL REGISTER O.

12:02

E.2

PAGE 17

SETTING THE SIGNAL RST W WILL PRESET THE

RDV AND WRV FLIP=FLOP'S, SUCH THAT, THE SIGNAL BRK L WILL BE MIGH.
THE SIGNAL MP H WILL ALLOW THE SIGNAL BRK L AS A HIGH TO BE INVERTED,

GENERATING THE SIGNAL MSBRK H AS A

LOW. THE SIGNAL MSBRK W AS A LOW

WILL BE READ INTO CONTROL REGISTER 2 AS A ZERO. THE TEST WILL THEN
CLEAR THE SIGNAL RST H IN CONTROL REGISTER O ANC CHECK THE SIGNAL
MSBRK H IN CONTROL REGISTER 2 TO REMAIN A ZERO.
TEST 11:
THIS TEST WILL CHECK EACH ADDRESS OF

THE 1K BY 4 MAP PROTECTION RAM

WITH A DATA PATTERN OF ALL ONES AND THEN ALL ZEROES. THE TEST WILL
SELECT AND INITIALIZE THE MEMORY SIMULATOR MODULE AS DESCRIBED IN
TEST 1. THE TEST WILL SET THE SIGNAL MSEL1 H IN CONTROL REGISTER 2
WHICH WILL CAUSE THE SIGNAL SMPM L TO BE ASSERTED ON A WRITE OR READ
TO CONTROL REGISTER 6. THE TEST WILL THEN SELECT THE MEMORY SIMULATOR
ADDRESS BY LOADING THE ADDRESS INTO CONTROL REGISTER & BITS 15-8 AND

CONTROL REGISTER 2 BITS 1 AND 0. THE TEST WILL THEN WRITE ALL ONES

INTO THE MAP PROTECTION RAM VIA CONTROL REGISTER 6 AND THEN READ THE

RAM LOCATICN BACK VIA CONTROL REGISTER 6. THE RAM BITS MUTB H, MPIN H,
WRE H, AND RDE H WILL BE CHECKED FOR ALL ONES. THE TEST WILL THEN
WRITE THE LOCATION ADDRESSED BY CONTROL REGISTER 2 AND 4 WITH A DATA
PATTERN OF ALL ZEORES. THE TEST WILL READ THE LOCATION AND CHECK THAT
ALL THE RAM BITS WERE READ BACK AS ZEROES.
THE TEST WILL THEN IMNCRE=MENT THE ADDRESS TO THE NEXT LOCATION AND REPEAT THE TEST SEQUENCE

UNTILL ALL ADDRESSES OF THE 1K BY & MAP PROTECTION RAM HAVE BEEN
TESTED WITH ALL ONES AND ZEROES.

TEST 12:
THIS TEST WILL CHECK THE 1K BY & MAP PROTECTION RAM USING AN
ALTERNATING ONES AND ZEROES PATTERN AND AN ALTERNATING ZEROES AND
ONES PATTERN.
THE TEST WILL ALSO CHECK THAT THE MAP PROTECT BITS
MPIN H AND WRE H CAN BE READ BACK INTO CONTROL REGISTER 2 AS SIGNALS
ESR H AND WREN H RESPECTIVELY.
THE SIGNAL MSBRK H IN CONTROL REGISTER

2 WILL BE CHECKED TO BE 0 DURING THIS TEST.

THE TEST WILL SET THE SIGNALS RST H AND MP H IN CONTROL REGISTER 0.
THE TEST WILL THEN READ CONTROL REGISTER O AND CHECK THAT THE SIGNALS

CTS H, 8 BIT H, RDV H, AND WRV H ARE ZERO AND THAT RST H AND MP H ARE

ONES. THE TEST WILL THEN CLEAR THE SIGNAL RST H AND CHECK THAT RST H

WAS THE ONLY BIT THAT CLEARED IN CONTROL REGISTER 0. THE TEST WILL
THEN SET THE SIGNAL MSEL1 H TO A ONE IN CONTROL REGISTER 2. CONTROL

REGISTER 2 BITS MSAD17 H AND MSAD16 H WILL BE SET TO A ONE OR ZERO
DEPENDING UPON THE ADDRESS TO BE TESTED. THE TEST WILL THEN READ CONTROL
REGISTER 2 CHECKING THAT THE BITS WERE {OADED CORRECTLY AND THAT THE
SIGNAL MSBRK H IS A ZERO. MSBRK H IS READ BACK AS A RESULT OF THE
SIGNAL MP H BEING ASSERTED IN CONTROL REGISTER 0. THE SIGNAL MSEL1 H

BEING SET AND THE SIGNAL MSELO H BEING CLEARED WILL CAUSE THE SIGNAL
SMPM L TO BE ASSERTED Of A WRITE OR READ TO CONTROL REISTER 6. THE

SIGNAL SMPM L BEING ASSERTED WILL ENABLE THE 1K BY 4 MAP PROTECTION
RAMS TO BE WRITTEN OR READ.
THE TEST WILL NOW LOAD THE REMAINING
PART OF THE 18 BIT MEMORY SIMULATOR ADDRESS INTO CONTROL REGISTER
4 BITS 15-8 AND CHECK THAT CONTROL REGISTER 4 WAS LOADED CORRECTLY.
THE TEST WILL NOW \TMITE THE LOCATION SELECTED WITH ONES IN BITS
MPIN H AND RDE H AND ZEROES IN BITS WRE H AND MUTB H. THIS IS DONE

SEQ 0017

USER DOCUMENTATION
??C5;1 30A(1052)
17=JUN-82
CVCDAB.P11

17-JUN-82

12:02

F 2
PAGE 18

SEQ@ 0018

VIA WRITING TO CONTROL REGISTER 6 WHICH WILL ASSERT THE SIGNAL SMPM L.
THE SIGNAL SMPM L BEING ASSERTED WILL ENABLE THE MAP PROTECTION RAM
TO BE WRITTEN OR READ. THE PROGRAM WILL READ BACK THE LOCATION WRITTEN
VIA CONTROL REGISTER 6 AND CHECK THE DATA TO BE CORRECT. THE TEST WILL
THEN READ CONTROL REGISTER 2 AND CHECK THAT BIT ESR H IS SET TO A ONE
AND BIT WREN H IS SET TO A O. THESE BITS ARE ENABLED INTO CONTROL
REGISTER 2 VIA THE SIGNAL MP H IN CONTROL REGISTER 0.
THE TEST WILL
NOW WRITE THE MAP PROTECTION RAM BITS WRE H AND MUTB H WITH ONES AND
BITS MPIN H AND RDE H WITH ZEROES. THE TEST WILL READ THE RAM LOCATION
VIA CONTROL REGISTER 6 AND CHECK THAT THE CORRECT PATTERN WAS READ
BACK.
THE TEST WILL THEN READ CONTROL REGISTER 2 AND CHECK THAT THE
BIT WREN H IS SET TO A ONE AND BIT ESR H IS SET TO A 2ERO.
THIS
TEST SEQUENCE WILL BE REPEATED FOR EACH ADDRESS OF THE 1K BY & MAP
PROTECTION RAM,

TEST 13:
THIS TEST WILL CHECK THE MAP PROTECTION RAM FOR ADDRESS SHORTS. THIS
TEST WILL CHECK THAT WRITING A LOCATION IN THE MAP PROTECTION RAM
WILL NOT WRITE ANOTHER LOCATION IN THE RAM. THE TEST WILL FILL THE
MAP PROTECTION RAM WITH ALL ZEROES CHECKING EACH LOCATION TO BE ZERO
AS IT IS WRITTEN.
THE TEST WILL THEN RESET THE ADDRESS POINTER TO
THE FIRST LOCATION OF THE RAM AND DO THE FOLLOWING STEPS:
1. READ THE LOCATION AND CHECK IT TO BE ZERO

2. WRITE THE LOCATION WITH ALL ONES AND CHECK IT TO BE ALL ONES
3. INCREMENT ADDRESS POINTER TO NEXT ADDRESS OF RAM
4. REPEAT STEPS 1-3 UNTIL ALL LOCATIONS HAVE BEEN CHECKED

TEST 14:
THIS TEST WILL CHECK THAT THE WRV FLIP-FLOP CAN BE SET VIA THE SIGNALS
WRE H AND (K H.
THE TEST WILL CHECK THAT THE WRV FLIP-FLOP, ONCE SET,

CAN NOT BE CLOCKED TO A ZERO BY CHANGING THE STATE OF WRE H AND CLOCKING
THE SIGNAL CK H AGAIN.
THE TEST WILL CHECK THAT THE WRV FLIP-FLOP CAN
BE CLEARED WHEN THE SIGNAL RST H IS PULSED.
THE TEST WILL ALSO CHECK
THAT THE SIGNAL MSBRK H CAN BE SET TO A ONE
THE WRV FLIP-FLOP BEING SET AND CLEARED.

AND ZERO AS A RESULT OF

TEST 15:
THIS TEST WILL CHECK THAT THE RDV FLIP-FLOP CAN BE SET VIA THE SIGNALS
RDE H AND CK H.
THE TEST WILL CHECK THAT THE RDV FLIP-FLOP, ONCE SET,
CAN NOT BE CLOCKED TO A ZERO BY CHANGING THE STATE OF RDE H AND CLOCKING
THE SIGNAL CK H AGAIN.
THE TEST WILL CHECK THAT THE RDV FLIP=FLOP CAXN
BE CLEARED WHEN THE SIGNAL RST H IS PULSED.
THE TEST WILL ALSO CHECK
THAT THE SIGNAL MSBRK H CAN BE SET TO A ONE
AND ZERO AS A RESULT OF
THE RDV FLIP-FLOP BEING SET AND CLEARED.

TEST 16:
THIS TEST WILL CHECK THAT THE RDV AND WRV FLIP-FLOPS CAN BE CLEARED
WHEN THE SIGNAL RST H IS ASSERTED. THE TEST WILL SET THE RDV AND WRV
FLIP=FLOP'S VIA THE SIGNALS WRE H, RDE H AND CK H.
THE SIGNALS WRE H
AND RDE H ARE OUTPUTS OF THE MAP PROTECTION RAM. THE SIGNAL CK W IS IN

CONTROL REGISTER 0.

THE SIGNAL CK H IS USED TO CLOCK THE SIGNALS

WRE H AND RDE H INTO THE WRV AND RDV FLIP-FLOP'S RESPECTIVELY.

THE

HACVAI 30A(1052) 17-JUN-82 12:02 PAGE ?9 2

USER DOCUMENTATION
17-JUN-82 11:2
CvCDAB.P1

SIGNALS WRE W AND RDE H SET TO A ZERO WILL CAUSE THE WRV AND RDV FLIP-

FLOPS TO BE SET WHEN THE SIGNAL CK H IS TOGGLED IN CONTROL REGISTER 0.
THE TEST WILL THEN READ CONTROL REGISTER O AND CHECK THAT THE SIGNALS
ROV H AND WRV H ARE SET. THE TEST WILL THEN SET THE SIGNAL RST H IN

CONTROL REGISTER O AND CHECK CHECK THAT THE SIGNALS WRV H AND RDV W
CLEARED.
THE SIGNAL MSBRK H WILL ALSO BE CHECKED DURING THIS TEST
TO BE SET WHEN THE WRV AND RDV FLIP=FLOP'S ARE SET AND CLEARED WHEN
THE RDV AND WRV FLIP=FLOPS ARE CLEARED.

TEST 17:
THIS TEST WILL CHECK MODULE SELECT RAM 0. A BINARY COUNT PATTERN

WILL BE LOADED INTO EACH ADDRESS OF MODULE SELECT RAM 0. FOR EACH
PATTERN LOADED,
THE TEST WILL CHECK FOR THE APPROPRIATE ENABLES ON

THE OUTPUT OF THE RAM. IF MORE THEN ONE BIT IS SET ON THE INPUT TO

THE RAM, ONLY ONE BIT WILL BE SET ON THE OUTPUT OF THE RAM. A ONE

IN_THE LOW ORDER BITS OF THE RAM WILL FORCE THE HIGH ORDER BITS TO

A ZERO.
MODULE SELECT RAM 0 IS SELECTED BY SETTING THE SIGNAL
MSELO H TO A ONE AND MSEL1 H TO A ZERO IN CONTROL REGISTER 2. WHEN
A WRITE OR READ IS ISSUED TO CONTROL REGISTER 6, THE SIGNAL SMDSO L

IS ASSERTED WHICH SELECT MODULE SELECT RAM 0.

TEST 18:
THIS TEST WILL CHECK MODULE SELECT RAM 1. A BINARY COUNT PATTERN
WILL BE LOADED INTO EACH ADDRESS OF MODULE SELECT RAM 1. FOR EACH
PATTERN LOADED, THE TEST WILL CHECK FOR THE APPROPRIATE ENABLES ON
THE OUTPUT OF THE RAM.
IF MORE THEN ONE BIT IS SET ON THE INPUT TO
THE RAM, ONLY ONE BIT WILL BE SET ON THE OUTPUT OF THE RAM. A ONE

IN_THE LOW ORDER BITS OF THE RAM WILL FORCE THE HIGH ORDER BITS TD

A ZERO. MODULE SELECT RAM 1 IS SELECTED BY SETTING THE SIGNALS MSELO H
AND MSEL1 H TO A ONE IN CONTROL REGISTER 2 AND THEN DOING A WRITE OR
READ TO CONTROL REGISTER 6 WHICH WILL CAUSE THE SIGNAL SMDS1 L TO BE

ASSERTED. THE SIGNAL SMDS1 L WILL ENABLE MODULE SELECT RAM 1 TO BE
gng;EN OR READ. MSAD BITS 17 AND 16 ARE USED TO ADDRESS MODULE SELECT

TEST 19:
THIS TEST WILL CHECK THAT MODULE SELECT RAM O AND 1 ARE ACTUALLY

SELECTED WHEN THE SIGNALS MSELO H AND MSEL1 H ARE SET TO SELECT THE
RAM'S.
THE TEST WILL SELECT MODULE SELECT RAM O, ADDRESS 0, AND
WRITE A DATA PATTERN OF 1 INTO THE RAM LOCATION. THE TEST WILL THEN
SELECT MODULE SELECT RAM 1, ADDRESS O, AND WRITE A DATA PATTERN OF
10 INTO THE RAM LOCATION. THE TEST WILL THEN RESELECT MODULE SELECT
RAM 0 AND CHECK THE PATTERN TO BE 1. THE TEST WILL THEN SELECT MODULE
SELECT RAM 1 AND CHECK THE DATA PATTERN TO BE 10.
TEST 20:
THIS TEST WILL CHECK THAT EACH ADDRESS IN MODULE SELECT RAM 0 CAN

BE _ADDRESSED CORRECTLY.

THIS IS DONE BY WRITING A SPECIFIC DATA

PATTERN INTO THE RAM AND THEN READING THE RAM CHECKING THAT NO

LOCATIONS CHANGED.

THE DATA PATTERNS LOADED INTO THE RAM, STARTING

AT THE LOWEST ADDRESS ARE AS FOLLOWS:

10,4,2,1,0,1,10,4.

SEQ 0019

USER DOCUMENTATION
MACY11 30A(1052)
CVCDAB.P11
17-JUN-82 11:26

17-JUN-82

12:02

H 2
PAGE 20

SEQ 0020

TEST 21:
THIS TEST WILL CHECK THAT EACH ADDRESS IN MODULE SELECT RAM 1 CAN

BE_ADDRESSED CORRECTLY. THIS IS DONE BY WRITING A SPECIFIC DATA
PATTERN INTO THE RAM AND THEN READING THE RAM CHE"KING THAT NO

LOCATIONS CHANGED. THE DATA PATTERNS LOADED INTO THE RAM, STARTING
AT THE LOWEST ADDRESS ARE AS FOLLOWS: 1, 2, 4, AND 10.

TEST 22:
THIS TEST WILL CHECK THAT ALL _MEMORY SIMULATOR RAM'S CAN BE WRITTEN

AND READ WITH DATA PATTERNS 125252 AND 052525. THIS TEST CHECKS THAT

ALL BITS IN THE RAM LOCATION CAN BE WRITTEN TO A ONE AND ZERO AND THAT
NO ADJACENT BITS ARE SHORTED TOGETHER. THIS TEST IS EXECUTED IN 16 BIT
MODE.
THIS TEST DOES NOT CHECK FOR INTERNAL ADDRESS SHORTS, ADDRESS
DROP OUT, CR THAT THE CORRECT MEMORY SIMULATOR RAM IS SELECTED. ALL
16K WORDS OF MEMORY SIMULATOR RAM ARE CHECKED WITH THE ALTERNATING
ONES AND ZEROES PATTERN AND ALTERNATING ZEROES AND ONES PATTERN.

TEST 23:
THIS TEST WILL CHECK THAT EACH 4K MEMORY SIMULATOR RAM IS SELECTED BY
WRITING A DIFFERENT DATA PATTERN INTO ADDRESS ZERO OF EACH RAM. THE
TEST WILL _THEN READ ADDRESS ZERO OF EACH RAM CHECKING THE DATA PATTERN
TO BE THAT WHICH WAS WRITTEN PREVIOUSLY. IF A DATA ERROR OCCURS DURING
THE RE-READING OF THE RAM'S, THE RAM SELECT LOGIC IS PROBABLY AT FAULT.
THE DATA PATTERNS WRITTEN INTO THE MEMORY SIMULATOR RAM'S 0, 1, 2, AND 3

ARE 11111, 22222, 33333, AND 44444 RESPECTIVELY.
TEST 24:

THIS TEST WILL CHECK THAT EACH ADDRESS OF THE MEMORY SIMULATOR RAM

CAN BE ADDRESSED CORRECTLY AND THAT NO ADDRESSES ARE SHORTED TOGETHER.

TO DO THIS, THE PROGRAM WRITES EACH LOCATION OF THE MEMORY SIMULATOR
RAM WITH DATA EQUAL TO THE ADDRESS OF THE LOCATION. AS EACH LOCATION

IS WRITTEN, THE PROGRAM READS THE LOCATION AND CHECKS THE DATA TO BE
EQUAL TO THE ADDRESS.
WHEN ALL MEMORY SIMULATOR RAM LOCATIONS HAVE
BEEN WRITTEN, THE PROGRAM WILL RE-READ THE RAMS CHECKING THAT ALL
LOCATIONS CONTAIN AS DATA THEIR ADDRESS. THE PROGRAM WILL THEN RESET

THE POINTER TO THE BEGINNING ADDRESS OF THE RAM'S AND DD THE FOLLOWING:

1. READ THE LOCATION AND CHECK IT TOCONTAIN ITS ADDRESS

2. WRITE THE LOCATION WITH THE ONE'S COMPLEMENT OF THE ADDRESS AND
CHECK THAT THE ONE'S COMPLEMENT CAN BE READ BACK.
3. REPEAT STEPS 1 AND 2 FOR EACH ADDRESS OF THE RAM'S

THE TEST WILL THEN RESET THE POINTER TO THE BEGINNING ADDRESS OF THE
RAM AND CHECK EACH LOCATION TO CONTAIN THE ONE'S COMPLEMENT OF ITS ADDRESS.

TEST 25:
THIS TEST WILL WRITE THE MEMORY SIMULATOR RAM'S WITH A COMPLEMENTING

DATA PATTERN. THE INITIAL DATA PATTERN WILL BE 125252,

EACH CONSEC-

ATIVE LOCATION WILL CONTAIN THE COMPLEMENTED DATA OF THE PREVIOUS

LOCATION (I1.E. 125252,052525,125252....ETC.). THE ADDRESSES TO THE

MEMORY SIMULATOR RAMS WILL BE LOADED AS ODD ADDRESSES. THIS IS DONE

TO INSURE THAT ODD ADDRESSES IN 16 BIT MODE DO NOT DISABLE THE
WRITING OR READING OF THE LOW BYTE OF THE MEMORY SIMULATOR RAM. AFTER

MACY11 30A(1052) 17-JUN-82 12:02 PAGE 51 2

USER DOCUMENTATION
CVCDAB.P11
17-JUN-82 11:26

ALL THE RAM LOCATIONS HAVE BEEN WRITTEN WITH THE COMPLEMENTING DATA

PATTERN,

THE TEST WILL REREAD THE MEMORY SIMULATOR RAMS USING EVEN

32?¥E§£ES AND CHECKING THAT THE RAM®'S CONTAIN THE COMPLEMENTING DATA
TEST 26:

THIS TEST WILL WRITE INTO AND READ FROM THE MEMORY SIMULATOR RAMS

USING THE 'MOVB' INSTRUCTION.
THIS TEST IS DONE IN 16 BIT MODE. THE
PURPOSE OF THIS TEST IS TO CHECK THAT WHEN WRITING THE LOW BYTE OF AN

ADDRESS, THE HIGH BYTE IS NOT EFFECTED, AND WHEN WRITING THE HIGH BYTE
?SL:gugDDRESS. THE LOW BYTE IS NOT EFFECTED. THE TEST SEQUENCE IS AS

OO?NOU‘&W

1. WRITE THE ADDRESS TO BE TESTED INTO CONTROL REGISTER &
2. WRITE THE MODULE SELECT RAMS TO ENABLE THE MEMORY SIMULATOR
«
«
.
«
«

WRITE AND CHECK LOW BYTE FOR DATA PATTERN OF 125
WRITE AND CHECK HIGH BYTE FOR DATA PATTERN OF 252
READ LOCATION AND CHECK WORD FOR DATA PATTERN OF 125125
WRITE AND CHECK LOW BYTE FOR DATA PATTERN OF 252
READ LOCATION AND CHECK WORD FOR DATA PATTERN OF 125252
WRITE AND CHECK HIGH BYTE FOR DATA PATTERN OF 125
READ LOCATION AND CHECK WORD FOR DATA PATTERN OF 052652
10. REPEAT STEPS 1-9 FOR ADDRESS O OF EACH MEMORY SIMULATOR RAM
TEST 27:
THIS TEST WILL CHECK THAT THE MEMORY SIMULATOR RAMS CAN BE WRITTEN
AND READ IN 8 BIT MODE. ADDRESS O OF EACH MEMORY SIMULATOR RAM WILL

BE TESTED IN 8 BIT MODE. THIS TEST WILL CHECK 8 BIT MODE AS FOLLOWS:
. SET MEMORY SIMULATOR TO 16 BIT MODE

—

2. LOAD ADDRESS O OF MEMORY SIMULATOR RAM SELECTED
3. WRITE DATA PATTERN 125252 INTO RAM AND CHECK THE DATA PATTERN

SET _MEMORY SIMULATOR TO 8 BIT MODE
WRITE DATA PATTERN 031463 INTO RAM + CHECK LOW BYTE FOR 063
SET MEMORY SIMULATOR TO 16 BIT MODE
READ DATA FROM MEMORY SIMULATOR RAM AND CHECK DATA TO BE 125063
SET MEMORY SIMULATOR TO 8 BIT MODE
LOAD ADDRESS 1 OF MEMORY SIMULATOR RAM SELECTED
WRITE DATA PATTERN 146314 INTO RAM + CHECK HIGH BYTE FOR 146000
SET MEMORY SIMULATOR TO 16 BIT MODE
READ DATA FROM MEMORY SIMULATOR RAM AND CHECK DATA TO BE 146063

REPEAT STEPS 1-12 FOR ADDRESS O OF EACH MEMORY SIMULATGR RAM

TEST 28:
THIS TEST WILL CHECK THAT INIT L CAN CLEAR THE LOW BYTE OF CONTROL
REGISTER O, AND THAT INIT H CAN PRESET THE WRV AND RDV FLIP-FLOPS.
THIS IS DONE BY CLEARING(1) RDV AND WRV FLIP-FLOPS AND THEN

ISSUING A BRESET INSTRUCTION WHICH SHOULD PRESET(0) THE RDV AND

THE WRV FLIP-FLOPS.

THEN ALL ONES ARE LOADED INTO THE LOW BYTE

OF REGISTER O AND A BRESET INSTRUCTION IS AGAIN ISSUED WHICH
SHOULD CLEAR THE LOW BYTE OF REGISTER 0.‘

SEQ 0021

PROGRAM HEADER AND TABLES
17-JUN-82

CVCDAB.P11

1101
1102
1103
}}8?
1106

.ENABL
LENABL
.DSABL
"

002000
002000

ABS
AMA
GBL
s

2000

BGNMOD
s
; THE PROGRAM HEADER IS THE INTERFACE BETWEEN
s THE DIAGNOSTIC PROGRAM AND THE SUPERVISOR.

1107

002000

POINTER BGNSETUP

1110

002000

HEADER

1112
1113
1114

002000
002001
002002

1116
1117
1118
1119
1120
1121
1122
1123
1126
1125
1126
1127

002004
002005
002006
002007
002010
002010
002011
002011
002012
002012
002014
002014

000074

1129

002016

021426

i
1111

1115

1128
1130
1131

1132
1133
1134
1135
1136
1137
1138
1139
1140
1141

114%
1143
1144
1145
1146
1147

SEQ 0022

+TITLE PROGRAM HEADER AND TABLES
.SBTTL PROGRAM HEADER

1
1094

1095
1096
1097
1098
1099
1100

11:26

MACY11 30A(1052) 17-JUN-82 12:05 PAGE 22

002000

002003

002016

002020
002020
002022
002022
002024
002024
002026
002026

002030
002030
002032
002032
002034
002034
002036
002036
002040
002040

103
126
103

LSNAME : :

104

101
000
000
000
102

060
000001

000000
002216
000000
021530

000000

000000
000000

000000
002124

(CVCDA,B,0,60.,0,PRI07

LASCII /7¢C/
LASCII /7v/
.ASCII1 /C/

:DIAGNOSTIC NAME

X
\

LASCII 7D/

LSREV::

LSDEPO: :
LSUNIT::

LSTIML::

LSHPCP: :
LSSPCP::
LSHPTP: :

LSSPTP::
LSLADP::

LSSTA::
L$CO::

LSDTYP::
LSAPT::
LSDTP::

LASCII /A7
.BYTE
0
BYTE
0
BYTE
0
LASCII

/8/

LASCII

70/

.WORD

TSPTHV

.WORD

60.

.WORD

LSHARD

LWORD

LSHW

WORD

.WORD

LSLAST

LWORD

.WORD

WORD

.WORD

JREVISION LEVEL

;0
JNUMBER OF UNITS

:LONGEST TEST TIME

:POINTER TO H.W. QUES.
sPOINTER TO S.W. QUES.
sPTR. TO DEF. H.W. PTABLE

sPTR. TO S.W. PTABLE
sDIAG. END ADDRESS

JRESERVED FOR APT STATS

sDIAGNOSTIC TYPE
;APT EXPANSION

sPTR. TO DISPATCH TABLE
LSDISPATCH

PROGRAM HEADER AND TABLES

CvCDAB.P

1148
1149
1150
1151
115%
1153
1154
1155
1156
1157
- 1158

00%045
002042
002044
002044
002046
002046
002050
002050
002051
002052
002052

1160
1161
116%
1163

002056
002056
002060
002060

%1159

002054

1164

00206%

1166
1167
1168
1169
1170
1171
1172

002064
002064
002066
002066
002070
002070
002072

1176
1175
1176
1177
1178
1179
1180
1181
1182
1183
11846
1185

002074
002074
002076
002076
002100
002100
002102
002102
002104
002104
002106
002106

1187
1188
1189
1190
1191
1192
1193
1194
;}gg

002110
002112
002112
002114
002114
002116
002116
002120
002120

1165

1173

1186

002062

002072

002110

17=JUN-B82 11:26
000340

000000
000000
003
003

000000

000000
000000
002314

000000

000000
000000

000000

002326
104035

000000

005570
005750

005746
005562
000000

000000

MACY11

30A(1052)

17-JUN-82

PROGRAM HEADER

LSPRIO::
LSENVI]::

LSEXP1::
LSMREV::

LSEF::
LSSPC::

LSDEVP::

LSREPP: :
LSEXP4::
LSEXPS::
LSAUT::

L$DUT::

LSLUN::
LSDESP::

LSLOAD::
LSETP::

LSICP::
L$CCP::
LSACP::

LSPRT::
LSTEST::

LSDLY::
LSHIME::

.WORD

PRIO7

.WORD

WORD

12:02

PAGE 23

sDIAGNOSTIC RUN PRIORITY
sFLAGS DESCRIBE HOW IT WAS SETUP

JEXPANSION WORD

WORD

:SVC REV AND EDIT #
CSREVISION
CSEDIT
sDIAG. EVENT FLAGS
O

WORD

.WORD

LSDVTYP

WORD

.WORD

WORD

.WORD

WORD

.WORD

LSDESC

EMT

ESLOAD

LWORD

.WORD

LSINIT

.WORD

LSCLEAN

.WORD

LSAUTO

.WORD

LSPROT

LWORD

.BYTE
.BYTE

WORD

s POINTER TO DEVICE TYPE LIST

:PTR. TO REPORT CODE

sPTR. TO ADD UNIT CODE

sPTR. TO DROP UNIT CODE

sLUN FOR EXERCISERS TO FILL
sPOINTER TO DIAG. DESCRIPTION

sGENERATE SPECIAL AUTOLOAD EMT
JPOINTER TO ERRTBL

sPTR. TO INIT CODE
sPTR. TO CLEAN-UP CODE
:PTR. TO AUTO CODE

sPTR. TO PROTECT TABLE
:TEST NUMBER

JDELAY COUNT
sPTR. TO HIGH MEM

SEQ 0023

PROGRAM HEADER AND TABLES
CVCDAB.P11

17=JUN-82 11:26

MACY11 30A(1052) 17-JUN-82 12:05 2PAGE 24
DISPATCH TABLE

197

.SBTTL

1199

14e

}285

1198

1%00

DISPATCH TABLE

s THE DISPATCH TABLE CONTAINS THE STARTING ADDRESS OF EACH TEST.

1203

1204 005122

IT 1S USED BY THE SUPERVISOR TO DISPATCH TO EACH TEST.

DISPATCH 28.

1205
1206
1207

002122
002124
002124

000034
006014

.WORD
LSDISPATCH::
WORD

1209

002130

006, 2<

WORD

1211
121§
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1253
1229
1230
1231
1232

002134
002136
002140
002142
002144
002146
002150
002152
002154
002156
002160
002162
002164
002166
002170
002172
002174
002176
002200
002202
002204
002206

006524
006602
006666
006754
007024
007070
007166
007366
007742
010332
011210
012066
012574
013012
013206
013552
014062
014316
014706
015354
016236
016710

1208 005126 006022
1210 002132

1233
}ggg

002210
002212

006342

017652
020624

28
T1

"WORD

-WORD
"WORD
"WORD
"WORD
"WORD
"WORD
"WORD
"WORD
"WORD
"WORD
"WORD
WORD
.WORD
"WORD
"WORD
"WORD
"WORD
.WORD
"WORD
"WORD
"WORD
"WORD

"WORD
"WORD

TS
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
122
T23
T2%
T25
T26

T27
T28

SEQ 0024

PROGRAM HEADER AND TABLES

CvCDAB.P11

17-JUN-82 11:26

MACY11 30A(1052)

17-JUN-82

n2
12&02 PAGE 25

DEFAULT HARDWARE P-TABL
+SBTTL

SEQ 0025

DEFAULT HARDWARE P-TABLE

144

THE DEFAULT HARDWARE P-TABLE CONTAINS DEFAULT VALUES OF
THE TEST-DEVICE PARAMETERS.
THE STRUCTURE OF THIS TABLE

: IS IDENTICAL TO THE STRUCTURE OF THE HARDWARE P-TABLES,
: AND IS USED AS A "‘TEMPLATE'' FOR BUILDING THE P-TABLES.

000002

LSHW::

BGNHW

DFPTBL

.WORD
LWORD

163010
O

.WORD

L10000~L$HW/2

DFPTBL::

163010
000000

L10000:
.SBTTL

sCSR ADDRESS
sDEVICE SELECTION NUMBER

ENDHW
SOFTWARE P-TABLE

<+
+

THE SOFTWARE TABLE CONTAINS VARIOUS DATA USED BY THE
PROGRAM AS OPERATIONAL PARAMETERS.
THESE PARAMETERS ARE
i;Tngz ?}HSSSEHBLY TIME AND MAY BE VARIED BY THE OPERATOR

BGNSW

LSSW::

.WORD

SFPTBL::

L10001:

ENDSW

ENDMOD

SFPTBL

L10001-L$SW/2

GLOBAL AREAS

MACY11 304(1052)

| CVCDAB.P11

17=JUN-82 11:26

1276
}%;;
1279
1280
1281

1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
}g}g

SEQ 0026

s
; THE GLOBAL EQUATES SECTION CONTAINS PROGRAM EQUATES THAT
: ARE USED IN MORE THAN ONE TEST.

002224

EQUALS

: BIT DIFINITIONS
100000
040000

020000
010000
004000
002000
001000
000400
000200
000100
000040
000020
000010
000004
000002
001
001000
000400
000200
000100
000040
000020
090010
. 00004
05002

000001

BIT15== 100000
BIT14== 40000

BIT13==
8IT12==
BIT11==
BIT10==
8IT09==
BIT08==
BIT07==
BIT06==
BITOS==
BIT04==
8IT03==
BIT02==
BITO01==
BIT00==

20000
10000
4000
2000
1000
400
200
100
40
20
10
4
2
1

BIT9==
BIT8==
BIT7==
BITé==
BITS==
BIT4==
BIT3==
BIT2==
BIT1==

BIT09
BIT08
BITO07
BIT06
BITO0S
BITO04
BIT03
BIT0?
BITO1

BIT0==

BIT00

: EVENT FLAG DEFINITIONS

}%5}

1329
1330
1331

BGNMOD

1320

1323
1324
1325
1326
}gg;

PAGE 26

SOF TWARE P=-TABLE

002224

}%3?

1292
1293

12:02

.TITLE GLOBAL AREAS
.SBTTL GLOBAL EQUATES SECTION

1282
1283
}532
1286
1287
1288
1289

17=JUN=-B82

000040
000037
000036
000035
000034

EF32:EF17 RESERVED FOR SUPERVISOR TO PROGRAM COMMUNICATION

EF.START==
EF .RESTART==
EF.CONTINUE==
EF .NEW==
EF .PWR==

32.
31.
30.
29.
28.

:
.
; PRIORITY LEVEL DEFINI"IONS
:

:
:
:
s
:

START COMMAND WAS ISSUED
RESTART COMMAND WAS ISSUED
CONTINUE COMMAND WAS ISSUED
A NEW PASS HAS BEEN STARTED
A POWER=-FAIL/POWER-UP OCCURRED
>

MACY11 30A( 1052)
17=JUN-B82 11:2 6

000340
00

17-JUN=-82 12:02 PAGE 27
GLOBAL EQUATES SECTION
PRI0O7==
FRI06==
PRIQS==
PRIO4==
PRIO3==
PRIOZ2==
PRIOT==
PRI0OO==

D e

AN AAN AN R R R R R R R R R R NN
W
A AN A
2gEgERs
\l‘\l“l‘\l‘\l‘\l‘\l‘\l‘(‘l\l‘\l‘:‘! :‘:3;5&;:
\NN-‘gOONO\hwa—lOO
NO N a;::‘!i‘!:‘!
WN=O VRNV
WN=O VRN NS WN—=OY BUNARNS

GLOBAL AREAS
CVCDAB.P11

SEQ 0027

340
300
540
20
14
100

40
0

:OPERATOR FLAG BITS

EvL==

D e

LOT==
ADR==
IDU==
ISR==
UAM==
BOE=

e e

PNT==
PR]==

IXE==
IBE==

d e

I1ER==

10600
2000

4000
10000

20000

40000
100000

LOE==
HOE==

10
20
40
100
200
400

100000

IDH==

BITI15

:BITS 14=12 WILL READ BACK AS 0
;MS DEVICE TYPE EQUALS 400 (BIT8=1)

004000
002000
001000
00

OO
00O
— —
IXTo=
nnxx
nnun

‘BITS 11-8

sBITS 11-8 ARE USED TO SELECT THE
sDEVICE NUMBER TO ASSERT THE SIGNAL
sDEVE L. WHEN SELECTING MS THESE BITS
sMUST = THE SETTING OF DEV 3 - DEV 0

;BIT 7 UNUSED (ALWAYS READ AS A 0)

d
e
e
e
e
D e
d e
d
e
—

;BIT15=1 READ DEVICE TYPE IN 15-8

:BIT15=0 READ DEVICE NUMBER INTO

cd e e

D e

*MEMORY SIMULATOR CONTROL REGISTER 0

000100
000040
000020
000010
000004
000002

:C OCK HIGH
sWRAITE VIOLATION (READ ONLY)
sREAD VIOLATION (READ ONLY)
sSELECT MS AS 8 BIT MODE NOT 16
sMAP PROTECT SELECT
;BIT1=1 MEM ACCESS FROM LSI-11 BUS

;BIT1=0 MEM ACCESS FROM SYSTEM BUS
sRESET MEMORY SIMULATOR MODULE

000001

*MEMORY SIMULATOR CONTROL REGISTER 2

MACY1 30A(1052)
17-JUN-82 11:26

17=JUN-82
12:02 PAGE 28
GLOBAL EQUATES SECTION

SEQ 0028

;BITS 15-8 ARE UNUSED BITS
200
000040

MSBRKH==B]T7
WRENH== BIT6

ESRH==

BITS

sMEMORY SIMULATOR BREAK (READ ONLY)
sWRITE ENABLE (READ ONLY)
*ENABLE SIMULATOR RAM

;BIT & IS UNUSED (ALWAYS READ AS A 0)

000010

MSEL1== BIT3
MSELO== BIT?

000002
000001

sMEMORY SELECTS

MSEL1=0 MSEL 0=0 = SELECT SIMULATOR MEMORY = SSM L
MSEL1=0 MSEL 0=1 = SELECT MODULE SELECT MEMORY 0 - SMDSO L
MSEL1=1 MSELO=0 = SELECT MAP PROTECT MEMORY - SMPM
L

MSEL1=1 MSEL 0=1 = SELECT MODULE SELECT MEMORY 1 - SHDS1 L

MSAD17==B]T1

MSAD16==BIT0

sMS ADDRESS 17
+MS ADDRESS 16

MSAD15==8]
MSAD14==8]
MSAD13==8]
MSAD12==8]
MSAD11==8]

;MS ADDRESS 1
:MS ADDRESS 1
:MS ADDRESS 1
;MS ADDRESS 1
MS ADDRESS 1
MS ADDRESS 1
MS ADDRESS 9
MS ADDRESS 8
;MS ADDRESS Z
:MS ADDRESS
:MS ADDRESS 5
;MS ADDRESS 4
:MS ADDRESS 3
;MS ADDRESS 2
sMS ADDRESS 1
:MS ADDRESS 0

O=NWwWHwW

:MEMORY SIMULATOR CONTROL REGISTER &

:<L ssssiini

—

GLOBAL AREAS

CV(DAB.P11

MEMORY SIMULATOR MAP PROTECT BITS = CONTROL REGISTER 6
000001
000002
002004
000010

MPINN== BITO
WREN==
BIT1
RDEN==
BIT

MUTBH== BIT

sMAPPED INTO MEMORY SIMULATOR
sWRITE ENABLED SIMULATOR MEMORY
sREAD ENABLED SIMULATOR MEMORY
:

.SBTTL

SEQ 0029

GLOBAL DATA SECTION

: THE GLOBAL DATA SECTION CONTAINS DATA THAT ARE USED
: IN MORE THAN ONE TEST.

ERRTBL
.WORD
-WORD
.WORD
.WORD

:
ERRMSG:
ERRBLK::

[=l=l=le)

LSERRTBL
ERRTYP::
:
ERRNBR:

* GLOBAL DATA FOR MEMORY SIMULATOR
.WORD
.WORD
- WORL
.WORD

——auw

sCONTROL
sCONTROL
sCONTROL
sCONTROL

IDDEV:: .WORD
UNITNB:: .WORD
IDTYPE:: -WORD

OO0

;MEMORY SIMULATOR DEVICE # (11-2)

ROLOAD:: -WORD
:
ROGOOD:
::
ROMASK
ROREAD::
:
ROBAD:

OO0O0O0O0

REGO::
REG2::

R2LOAD::
R2GOOD::
R2MASK
::
R2READ::
R2BAD::

*MEMORY SIMULATOR DEVICE TYPE (15-8)
sWORD LOADED INTO REGISTER 0

OO0O00O0

sWORD LOADED INTO REGISTER 2
sEXPECTED REGISTER 2
;REGISTER 2 MASK WORD
sACTUAL REG 2 READ
sREG 2 READ MINUS R2MASK BITS

R4LOAD:
:
R4READ::

OO0

sEXPECTED REG 0
sREGISTER 0 MASK WORD
sACTUAL REG 0 READ
sREG 0 READ MINUS ROMASK BITS

;WORD LOADED INTO REGISTER 4
;WORD READ OUT OF REGISTER &

R6LOAD:
:
R6GOOD::

OO0OO000

REG4::
REG6::

sWORD LOADED INTO REGISTER 6
sEXPECTED REGISTER 6
sREGSITER 6 "ASK WORD
sACTUAL REGISTER 6 READ
;REG 6 READ MINUS MASK WORD

17-JUN-82 1 1:26

17=JUN-B82
12: 02 PAGE 29
GLOBAL DATA SECTION

1437

MACY11 30 A(1052)

GLOBAL AREAS
| CVCDAB.P11

GLOBAL AREAS
CVCDAB.P11

MACY11_30A(1052)

17-JUN-82 11:26

17=JUN-82 12:02 PAGE 30
GLOBAL TEXT SECTION

1485
1486
1487
1488
1489
1490

.SBTTL

SEQ 0030

GLOBAL TEXT SECTION

144

: THE GLOBAL TEXT SEC TION CONTAINS FORMAT STATEMENTS,
; MESSAGES, AND AS CIl INFORMATION THAT ARE USED IN

: MORE THAN ONE TE ST.

1491

: NAMES OF DEVICES SUPPORTED BY PROGRAM
I

042115
030461
002326

027505
000

026524

DEVIYP

LSDVTYP::
LASCIZ

<MDE/T=11>
XMDE/T-11%

spgsc.

002350

042515
051440
052101
040511
002356

054522

DESCRIPT

"".ASCIZ /MEMORY SIMULATOR DIAG./
.EVEN

:ASCII MESSAGES USED BY ERROR CALLS

—3

B md md

D d b end =3

)

e
e
A

: TEST DESCRIPTION

.ASCIZ

/DATA ERROR IN MAP PROTECTION RAM/

/ADDRESS SHORT IN MAP PROTECTION wAM/

MSGMPL::.ASCIZ

/MAP PROTECT LOGIC ERROR/

MSGMDO:
: .ASCIZ

/DATA ERROR IN MODULE SELECT RAM 0/

104

—_N=O
S N—=wn

Pl
o0

2 D

b e
Vi

b ed e

D ek =S md e

)

MSGMPS::.ASCIZ

N
=WNO
Y\
\
b
N=NO
NN
—

MSGMP::

VNSNS
NOOANN
— e SN
OCONMNMVO
WWVON)
=

b il e

e ed

)

—

042440
044440
020120
041505
051040

1582
1583
1584

1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1295
1998

WVINSN
-

o
OHNMN—-=NO o

VSN

OO0O0O0O

=S VNOOWN
NS OOOWNN=O

V= &
[y
OWNN
b

MSGMD1::.ASCIZ

/DATA ERROR IN MODULE SELECT RAM 1/

MSGMDC::.ASCIZ

/CHIP ENABLE ERROR = MODULE SELECT RAM'S/

MSGMDA:: .ASCIZ

/MODULE SELECT RAM ADDRESSING ERROR/

MSGMSR::.ASCIZ

/DATA ERROR IN MEMORY SIMULATOR RAM/

MSGMSC::.ASCIZ

/CHIP ENABLE ERROR = MEMORY SIMULATOR RAM/

N
&~
r

o
s

—y

o
N
o

-t NN

000

040522

prd

020122

&H
v

1581

003040

3
o
N
~N
~

1580

viviwvwnawawnwn

1573
1574
1575
1576
1577
}g;g

17-JUN-82 12:02 PAGE 31
GLOBAL TEXT SECTION

OO0
OO0O0O0O0OD
RRRR
GRRGR N

&
ONVN§NN—IN
R
S

o
~

N
o

030040

L=4
»
RRIRGRREA

066582

(=]
~

S
&

8
N

W
W

002550

v
w

1541

MACY11 30A(1052)
17=JUN-82 11:26

o
Y

GLOBAL AREAS
CVCDAB.P11

.EVEN
:
s FORMAT STATEMENTS USED IN PRINT CALLS

003046
003054

003070
003076
0031064
003112
003120
003126
0031346
003142

003150
003156
003164
003172
003200

040445

047522
020107
047522

040445

047522

020107
047522
040445
047522
020107

047522
040445
047522
020107
047522

047503
020114
020060
022522

047503

0201146

S
022522
047503
020114
020064

022522
047503
0201146
020066
022522

052116

EMSGRO::.ASCIZ

/XACONTROL REG 0 ERRORIN/

052116
042522
051105
000116
052116
042522
051105
000116
052116
042522
051105
000116

EMSGR2::.ASCIZ

/XACONTROL REG 2 ERRORIN/

EMSGR4::.ASCIZ

/XACONTROL REG 4 ERRORIN/

EMSGR6::.ASCIZ

/XACONTROL REG 6 ERRORIN/

042522
051105
000116

SEQ 0031

GLOBAL AREAS
CVCDAB.P11
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611

1612
1613

1614
1615
1616
1617
1618
1619

1620
1621
1622
1623
1624
1625
1626
1627

1628
1629
1630
1631
1632
1633
1636
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645

1646

1647
1648
1649
1650
1651

003206
003214
003220
003226
003232
003240
003246
003252
003256
3264
003272
3300
003314
003322
003330
3336
003344
003352
003360
003363
003370
003376
3404
003412
003417
003426
003432
003440
003446
003454

003462
003470
003473
003500
003506
003514
003522
0035
003536
003544
003547
003554
003562
003570
003576
3604
003612
003620

MACYT 30?(1252)
17=JUN-82 11:2
040445
036440
040445
036440
040445
036440
040445
036440
&5
020072
030523
042101
022466
040515

042522
000040
042522
000040
042522
000040
042522
000040
067514
047445
040445
02007%
030523
045523

047445

022466

030523
035104
047045
045
035104
051445

040445
022440
000
046101
022440
022461

040445
020072

040505
033117
5
020105
051105
2101
044523
047117

051040
047045
045
020105
051105
042101
044523
047117
051040
047045
045
020105
051105
042101
044523
047117
051040
047045
003624

047507
047445

035104
047045
052101
052517
047522
051104
043516
051126

043505
000
052101
052517
047522
051104
043516
0511264
043505
000
052101
052517
047522
051104
043516
051126
043505
000

17-JUNEEZ 12:02 PAGE 32
OBAL TEXT SECTION

SEQ 0032

030107

REGOEQ::.ASCIZ

/%AREGO = /

031107

REG2EQ::.ASCIZ

/%AREG2 = /

032107

REG4EQ::.ASCIZ

/%AREGL = /

033107

REGGEQ::.ASCIZ

/%AREGS = /

042101
022466
042522
047445
040445
020072
030523
042117
022466
040502
033117

FRMTRO::.ASCIZ

/ZALOAD: XO06XS1XAREAD: X06%S1XAMASK: 306XS1X3AGOOD: X06XS13ABAD: 063N/

040517
033117
051101
022440
000
046511
020124
020122
051505
041440
046117

FRMTRG::.ASCIZ

/ZALOAD: X06XS1XAREAD: X06IN/

MSGTMO::.ASCIZ

/XATIME OUT ERROR ADDRESSING CONTROL REG OIN/

046511
020124
020122
051505
041440
046117
031040

MSGTM2::.ASCIZ

/XATIME OUT ERROR ADDRESSING CONTROL REG 23N/

046511
020124
020122
051505
041440
046117
032040

MSGTM4::.ASCIZ

/XATIME OUT ERROR ADDRESSING CONTROL REG &4IN/

030040

.EVEN

GLOBAL AREAS
CVCDAB.P11

MACY11 30A(1052)
17-JUN=-82 11:26

1652

.SBTTL

163

; (BASIC) AND PRINTX (EXTENDED) CALLS ARE USED TO CALL PRINT SERVICE:.

1659
1660
1661

003624

1663

003624

1665

003630

166§ 003624

ROEROR: :

003624

012746

1666
1667
1668

003634
003636
003640

010600
104414
062706

1670

003644

003646

1676

1677

1678

}2;8

003674

003700
003702

003704

MOV

013746

002256

MOV

013746

012746

010600
104415

062706

000001

000006

003076
000001

1698

003732

ROGOOD, = (SP)

ROMASK. =(SP)

ROREAD. = (SP)

ROLOAD ,=(SP)

MOV

SP.RO

ADD

#6,-(SP)
CSPNTX

#16,SP

ENDMSG

BGNMSG

R2EROR

000004

PRINT8
MOV
MOV
MOV
TRAP
ADD

W#EMSGR2
#EMSGR2, = (SP)
#1,-(SP)
SP,RO
CSPNTB
#,SP

013746

002274

MOV

013746
013746
013746

002270
002272
002264

MOV
MOV
MOV

R2EROR::

013746

1703
1704
1705

003756
003762
003766

012746
012746
010600

003770
003772

ROBAD, = (SP)

(SMSG

003736

1706
1707

lFRHTRO ROLOAD ROREAD ,ROMASK ,ROGOOD ,ROBAD

TRAP

1699

003742
003746
003752

SP,RO
CSPNTB
#4,SP

#FRMTR0, - (SP)

TRAP

L10002:

104423

#EMSGRO,
= (SP)

MOV

000016

012746
012746
010600
104414
062706

1700
1701
1702

MOV

003256

003712
003712
003712
003712
003716
003722
003724
003726

003732

MOV

002252

1689
1690
1691
1692
1693
169
1695
1696

1697

MOV

002260

003710
003710

003710

PRINTX

002254

1681
1682
1683
1684
1685
1686

}235

#1,-(SP)

002262

013746

003670

MOV

013746

003660

1675

#EMSGRO

000004

1673

003664

PRINTB

MOV
TRAP
ADD

012746

013746

1676

ROEROR

MOV

003650
003654

BGNMSG

003046

1671

1672

GLOBAL ERROR REPORT SECTION

: THE GLOBAL ERROR REPORT SECTION CONTAINS MESSAGE PRINTING AREAS
s USED BY MORE THAN TEST TO OUTPUT ADDITIONAL ERROR INFORMATION.
PRINTB

}ggz

1669

144

1655
1656

1664

17-JUN-82 12:02 PAGE 33
GLOBAL ERROR REPORT SECTION

104415
062706

002266
003256
000006
000016

PRINTX

OFRHTRO RZLOAD R2READ ,R2MASK ,R2GO0D ,R2BAD
R2BAD,- (SP)

MOV

nzeooo.-(sp)

MOV
MOV
MOV

:runrnb -(SP)
#6,-(SP}
sp.ao

TRAP
ADD

SK.=(SP)
a READ. =(SP)
R2LOAD ,=(SP)

CSPNTX
#16,SP

SEQ 0033

MACY11 30A(1052)
17-JUN-821 1:26

GLOBAL AREAS

S
W

&»H

sooon

28'\”\!
SESNN
N
NS

fa222
d
b
-

g2
S
S

g
w

<
N

CSMSG

BGNMSG

R4EROR

g;.;ést
CSPNTB

#6,5P
#FRMTRG ,R4LOAD , R4READ
R4READ
, = (SP)

R4LOAD . =(SP)

SERMTRG , = (SP)
#3,-(SP)

000010

L10004:

003156
000001

#10,SP

TRAP

CSMSG

BGNMSG

ALINFO

PRINTB

#EMSGR6
#EMSGR6 ,~(SP)
#1,-(SP)

ENDMSG

SP.RO
CSPNTB

#4,SP
PC,PRNTAL

L10005:

W NN

NN = = -2

RRZIZR RERRRRIARRER

D
i
b
e
b e
b
e
b e
b
e e
— e

SP,RO
CSPNTX

ADD

000004
004242

CSMSG
ALROIN

ALROIN::

#EMSGRO
#EMSGRO, = (SP)

003046
000001

#1,-(SP)

000004
004242

L10006:

ALR2IN::

003076
000001

SEQ 0034

#EMSGRS
#EMSGRS , = (SP)

002300
002276
003363
0¢0003

104423

012746
012746

TRAP

003126
000001

ALINFO::

ié

SEVERRURS
-0

&~ ~

NNOWW
NN

—=00000

—b

R4EROR::

NS
WN =0 VR NO VS WN=0O

PNINIPONOPININININ)
b b b
e
e o i

104423

ENDMSG

L10003:

e e

D e

e e o o

D e

NNNNNNNNNNNNNNNNNSN NNNNNNNNNNNNNNY

CVCDAB.P11

17=JUN-82
12:02 PAGE 34
GLOBAL ERROR REPORT SECTION

JSR
ENDMSG
TRAP

CSMSG

BGNMSG

ALR2IN

PRINTB

#EMSGR
#EMSGR

Mov
MOV
MOV

#1,-(SP}
SP_RO

=(SP)

;GO PRINT ALL THE REGiSTERS

GLOBAL AREAS
CVCDAB.P1T

1764

1765
1766

1767
1768

004140

004142
004146
00415
00415

MACY11 30?(1052)

17-JUN~82 11:26

104414

062709
004737

};93

0064152

1721
1772

004154
004754

1774

004154

012746

1776

004164

010600

1773

1775

1777
1778
1779
1780

004134

004160

004166
004170
004174
004174

104423

104414
062706

003417

L10010:

004176
004176

1786
1787
1788

004176
004202
004206

012746
012746
010600

003473
000001

1790
1791
1792

004212
004216
004216

062706

000004

1795
1796
1797

004220
004220
004220

1799

004224

R2TM::

1789 oo:.sw 104414

1798

1800

0046216

012746

004230

010600

1801
woi
1803
1804

004232
34,
004240
004240

1807

00424

1811
mi

004254
004256

}&;

0046240

1808 004242
1809 004246
1810 004252
1813

1814
1815
mg
1817
1818
1819

R4TM::

004220

004

006262
004 63
004272
004276
004302

004306

012746

104414
062706

003547

012746
012746
010600

L10012:

104415
062706

000004

013746
013746
013746
013746
013746

002262
002254
002256
002260
oogzsz

012746

003256

BGNMSG

ROTM

PRINTB

#MSGTMO

MOV

#,-(SP)

TRAP

(C$MSG

BGNMSG

R2TM

PRINTEB

#MSGT

MOV
MOV
MOV

MSGTM = (SP)
#1,-(SP)

ADD
ENDMSG

#6,5P

TRAP

(SMSG

BGNMSG

R&TM

PRINTB

#MSGTMé

MOV

#1,-(SP)

TRAP

CSPNTB
#,SP

TRAP

PRNTAL
: :PRINTX

;60 PRINT ALL THE REGISTERS

SP,RO

CSPNTB
#%,5P

ENDMSG

SEQ 0035

MSGTMO, = (SP)

TRAP
ADD
ENDMSG

MOV

000004

003206
000001

($MSG

MOV

000001

104423

TRAP

ENDMSG

TRAP

L10011:

104423

#,SP
PC.PRNTAL

MOV

000004

104423

CSPNTB

ADD
JSR

MOV

000001

1783
1784

}7732

TRAP

ROTM::

012746

PAGE 35

GLOBAL ERROR REPORT SECTION

L10007:

006174

004176

12:02

000004
004242

};g}

1785

17=JUN-82

SP.RO

(SPNTB

#MSGTMG = (SP)

SP.RO

(SMSG
#REGOEQ

MOV
MOV
MOV

#REGOEQ, = (SP)
#,-(SP}
SP.RO

PRINTX

#FRMT,ROREAD
RO,RO
, ROMASK ,ROGOOD
LOAD
, ROBAD

MOV

#FRMTRO,
= (SP)

TRAP
ADD

MOV
MOV
MOV
MOV
MOV

CSPNTX
#6,SP

ROBAD,
= (SP)
ROGOOD, =(SP)
ROMASK . =(SP)
ROREAD
. =(SP)
ROLOAD ;= (SP)

| GLOBAL AREAS
CVCDAB.P11

1820 004312
1821 004316
1& 004320

1
1824

MACY11 S0AC1052) 17-JUN-82 12:02 _PAGE 36

17-JUN-82 1

012746
010600
104415

004322
004326

062706

1826 004332
1827 004336

012746
010600

w%g

004342

ool.sag
004352
oo:.gzg
004
004766
0043572
004376

000006
000016

004340

1830

004346

1831
m%
183
1834
1835
1836
1837

#6,=(SP)
SP_RO
CSPNTX

000001

MOV
MOV

#,-(SP)
SP,RO

062706

000004

ADD

#4,5P

013746
013746
013746
013746
013746
012746
012746

002274
002266
002270
002272
002264
003256
000006

MOV
MOV
MOV
MOV
MOV
MOV
MOV

R2BAD,
= (SP)
R2G0OOD , = (SP)
R2MASK ,=(SP)
R2READ,=(SP)
R2LOAD . =(SP)
#FRMTR0, = (SP)
#6,~(SP)

MOV
MOV
MOV

#REG4LED,=(SP)
#1,-(SP)
SP,RO

104415

004402
404
004406
004412

010600
104415
062706

1845
1846
1847

004424
004426
004432

104415
062706

412
004416
004422

MOV
MOV
TRAP

#16,SP
#REG2EQ

1838
1839
1840
1841

w.g
1843
1844

GLOBAL ERROR REPORT SECTION

ADD
PRINTX

1825 ooug 012746 003220

1828

K 3

012746
012746
010600

000016

003232
000001
000004

MOV

TRAP

PRINTX

MOV
TRAP
ADD
PRINTX

TRAP
ADD
PRINTX

#REG2EQ,~(SP)
CSPNTX

#FRMTRO,R2LOAD ,R2READ,R2MASK ,R2GOOD , R2BAD

SP.RO
CSPNTX
#16,SP
#REG4EQ

CSPNTX
#6,SP
#FRMTR&,R4LOAD,R4READ

1848
1849
1850
1851
1852

004432
004436
004442
004446
004452

013746
013746
012746
012746
010600

002300
002276
003363
000003

MOV
MOV
MOV
MOV
MOV

R4READ,
= (SP)
R4LOAD . =(SP)
#FRMTRG , = {SP)
#3,-(SP)
SP,RO

1854
1855

004456
004462

062706

000010

012746
012746
010600

003244
000001

ADD
PRINTX

#10,SP
#REG6EQ

1853

1856
1857
1858

1859
1860
1861

004454

0046462
004466
004472

004474
004476
004502

104415

TRAP

MOV
MOV
MOV

CSPNTX

#REGOEQ,
= (SP)
#1,=(SP)
SP.RO

104415
062706

000004

004502
004506
004512
004516
004522

013746
013746
013746
013746
013746

002312
002304
002306
002310
002302

MOV
MOV
MOV
MOV
MOV

R6BAD, = (SP)
R6GOOD
, = (SP)
R6MASK
, = (SP)
RG6READ ,=(SP)
R6LOAD ,=(SP)

1868 004532
1869 004536

012746
010600

000006

MOV
MOV

#6,-(SP)
SP.RO

mg
1863
1864
1865
1866

1867 ooasge 012746 003256

1870
1871
}gg

004540
004542
004546

104415
062706
000207

000016

TRAP
ADD
PRINTX

MOV

TRAP
ADD
RTS

CSPNTX
#4,5P
#FRMT,R6READ,
RO,R6
R6MASK , LOAD
R6GOOD , R6BAD

#FRMTRO, - (SP)
CSPNTX
#16,SP
PC

SEQ 0036

MACY11 30A(1052)
17=JUN-82 11:26

GLOBAL AREAS
CVCDAB.P11

.SBTTL

SEQ 0037

GLOBAL SUBROUTINES SECTION

144

: THE GLOBAL SUBROUTINES SECTION CONTAINS THE SUBROUTINES
: THAT ARE USED IN MORE THAN ONE TEST.

d e

=
VW

s FUNCTIONAL DESCRIPTION:
:
SUBROUTINE TO....SELECT AND INITIALIZE MEMORY SIMULATOR
: INPUTS:
H
LOCATION IDDEV CONTAINS USER DEFINED DEVICE NUMBER IN BITS 11-8

e e

: IMPLICIT INPUTS:
OUTPUTS:
ROLOAD CONTAINS USER DEFINED UNIT NUMBER IN BITS 11-8
ROMASK CONTAINS CONTROL REGISTER 0 MASK WORD (000000)
R2LOAD CONTAINS ALL 0°'S IN R/W BITS MSEL1 H, MSEL2 H, MSAD17 H, MSAD16 H
R2MASK CONTAINS CONTROL REGISTER 2 MASK WORD (177760)
R4LOAD CONTAINS ALL ZEROES IN R/W BITS MSAD 15:0

23zsaae

D e

144

e e

SSSsstsg3ssasssesagsnies
A L
WN =00V NYNO NS WN=O
NOoONwn &% 88822232 §OO CELE

1874
1875
1876
1877
1878
1879

17-JUN-82 12:02 PAGE 37
GLOBAL SUBROUTINES SECTION

: IMPLICIT OUTPUTS:

SUBORDINATE ROUTINES USED:

TO LOAD,
TO LOAD,
TO LOAD,
TO LOAD,

READ
READ
READ
READ

AND
AND
AND
AND

COMPARE
COMPARE
COMPARE
COMAPRE

) D e ek wd

A TRTR TR

D wd

)

LDRDRO ROUTINE
LDRDOR ROUTINE
LDRDR2 ROUTINE
LDRDR4 ROUTINE

FUNCTIONAL SIDE EFFECTS:
MEMORY SIMULATOR SELECTED

CONTROL REGISTER LOW BYTE EQUALS 0
CONTROL REGISTER 2 R/W BITS CLEARED (MSEL1.MSEL2.MSAD17 AND MSAD16)

CONTROL REGISTER 4 R/W BITS CLEARED (MSAD 15:0)

nNDNNO
O

wvivaunwn
wviviunan

2282

VRNV

—

00O
NN

b ek

b wd

d d

CALLING SEQUENCE:
JSR PC,INITMS

104404

012746

000340

INITMS : :BGNSEG
TRAP
SETVEC

MOV

C$BSEG

#4,41$,#PR] ?7
#PR107,-(SP

sROUTINE TO INIT MS MODULE

:SETUP VECTOR

GLOBAL AREAS
CVCDAB.P11

1930 004556

1931
mg
1933

}ggg

004562
004566
004572

004576

MACYT 30?(5252)

17~JUN-82 1

012746

012746
012746
10443

062706

17=JUN-82

12:02

PAGE 38

GLOBAL SUBROUTINES SECTION

004676

MOV

000010

ADD

000004
000003

MOV
MOV
TRAP

}ggg

SEQ 0038

”$,=(SP)

#4,=(SP)
#3.<(SP)
CSSVEC

#10,5P

;LOAD DEVICE NUMBER INTO REGISTER O AND CHECK IT

1938 004600
1939 004506

013737
012737

002244
000060

002252
002256

MOV
MOV

IDDEV,ROLOAD
#RDVH | WRVH, ROMASK

:GET USER DEFINED DEVICE NUMBER
*SETUP TO MASK READ ONLY BITS

mg
1943
1944

004630
004636
004644

017737
013737
043737
001414

ROGOOD , ROBAD

*READ REGISTER CONTENTS BACK
:COPY REG O READ TO ALLOW MASKING
:CLEAR UNWANTED BITS GF REG 0

004660

MOV
MOV
BIC
CMP

@REGO, ROREAD
ROREAD , ROBAD
ROMASK . ROBAD

1946

175400 002260
002260 oozzes
002256 00226
002254 002262

:COMPARE EXPECTED WITH THAT READ

ERRDF
TRAP

1, ,ROEROR
CSERDF

:DEVICE # OR LB NOT = EXPECTED

1940
1941

1945

1947
1948

004614
004622

004652 023737

00466,
004662

1949
1950
1951
1952
1953

004664
004666
004670
004672
004672

1955
1956
1957

004676
004700
004702

1954

1958

1959
1960

1961

1962

013737
013777

004674

004702

004704
004706

004710

004712

}9’%

004716
004720
004720

004720

002254
175404

MOV
MOV

BEQ

104455
000007
000000
003624
104406

000406

005726
005726

1$:

104455

000001
000000

10443€

28:

000004

100008:

104405

}ggg
004722
004722
004724

1975
1976
1977

004740
004744
004746

004737
001404

1979
1980
1981
1982
1983
;3345

004750
004752
004754
004756
004756
004756

000001
000000
003624

1978

1
O
ROEROR

ST
ST
ERRDF

(SP)+
(SP)+
1, ,ROTM

CSCLP1

B8R

TRAP

CSERDF

ROTM

MOV

#4 R0

TRAP

CSESEG

TRAP
ENDSEG

:IF COMPARE WAS GOOD THEN CONT

;BRANCH AROUND TIME OUT ERROR

:CLEAN
UP STACK
:CLEAN UP STACK
:TIME OUT ERROR REG 0

1
O

"WORD

CLRVEC

:PUT DATA LOADED INTO EXPECTED
*WRITE WORD TO REG 0

;CLEAR VECTOR

CSCVEC

:READ DEVICE TYPE IN REGISTER 0

1971
1972
1973

1974

ROLOAD , ROGOOD
ROLOAD , aRE GO

WORD
WORD
.WORD
CKLOOP
TRAP

LWORD
WORD

004154

1963 004712 012700

1084
1965
1966

oozzsg
002252

004732

004746

104404
052737

013737

100000

002250

005354

002252

002254

($BSEG
#1DH, ROLOAD

:SETUP TO READ DEVICE TYPE

JSR
BEQ
ERRDF

PC,LDRDOR
3$
1, ,ROEROR

:LOAD, READ AND COMPARE REG 0
:IF EQUAL THEN DEVICE TYPE COMPARED
:DEVICE TYPE NOT EQUAL EXPECTED

WORD
JWORD
.WORD
ENDSEG

1
0
ROEROR

TRAP

CSESEG

MOV

104455

104405

BGNSEG
TRAP
BIS

TRAP

38:

10001s:

IDTYPE ,ROGOOD

CS$ERDF

:SETUP EXPECTED DATA

GLOBAL AREAS
CVCDAB.P11

MACY11 30A(1052)
17-JUN-8 2 11:26

17-JUN-82 12:02 PAGE 39
GLOBAL SUBROUTINES SECTION

1986
1987
1988
1989
1990
1991
199
199

3
SEQ 0039

sSET SIGNAL RSTH TO 0 WRV AND RDV F/F'S = 0 SIGNAL I/D H
TRAP
MOV
BIS
BIC
JSR
BEQ
ERRDF

C$BSEG
IDDEV,ROLOAD
#RSTH,ROLOAD
#WRVH | RDVH, ROMASK
PC,LDRDRO
48
1, ,ROEROR

JWORD
WORD
"WORD
ENDSEG

1
O
ROEROR

TRAP

CSESEG

TRAP

4$:
10002%:

CSERDF

:GOT USER DEFINED DEVICE NUMBER
sSET BIT TO ISSUE SIGNAL RST H

*CLEAR READ ONLY BITS RDVH + WRV W
:GO ISSUE SIGNAL RST H TO 0 WRV + RDV
*IF OK THEN CONTINUE
*RSTH NOT SET OR RDV OR WRV F/F*S SET

;CLEAR SIGNAL RST H TO CHECK THAT RDV + WRV REMAIN A ZERO
104404

042737
004737
001404

000001
005346

002252

104455
000001
000000
003624

5$:
10003$:

104405

BGNSEG
TRAF
BIC
JSR
BEQ
ERRDF
TRAP
JWORD
WORD
"WORD
ENDSEG
TRAP

C$BSEG

#RSTH,ROLOAD

;SETUP TO CLEAR RSTH BIT IN REG 0

5%
1, ,ROEROR

*IF OK THEN CONTINUE
:RDV OR WRV STILL SET OR RST W SET

PC,LDRDRO

CSERDF
1
O
ROEROR

*LOAD, READ AND COMPARE REG 0

CSESEG

sCLEAR THE _SIGNALS MSEL1 H, MSEL2 H, MSAD17 H AND MSAD16 H IN CONTROL
SREGISTER 2 AND CHECK THAT THESE SIGNALS CLEARED BY READING CONTROL
JREGISTER 2 BACK AGAIN.
BGNSEG

104404

012746

TRAP

000340

002270

001414

002266

MOV

#3,-(SP)

ADD

#10,SP

TRAP

000010

005162

#4,46S,#PRI07
#PRI07 ,=(SP)
#6$,=(SP)

MOV

000003

002274

C$BSEG

SETVEC
MoV
MOV

CLR
MoV
MOV
MoV
MOV
MOV

BIC
CMP
BEQ

sSETUP VECTOR

#4 ,=(SP)
CSSVEC

R2LOAD
#1777460,R2MASK
R2LOAD,R2G00D

R2LOAD ,aREG2
aREG2 ,R2READ

R2READ ,R2BAD
R2MASK , R2BAD
R2GOOD ,R2BAD
78

sSETUP TO CLEAR R/W BITS
s IGNORE READ ONLY AND UNUSED BITS

sPUT DATA TO BE LOADED INTO EXPECTED
sWRITE BITS INTO REGISTER 2
sREAD REGISTER 2 BACK

:COPY DATA READ
sCLEAR UNWANTED BITS IN REG 2
sCHECK IF EXP EQUALS ACTUAL
s IF LOADED OK THEN CONTINUE

GLOBAL AREAS
CVCDAB.P11

MACY11 30A(1052)
17--JUN-B8221 11:26

17=JUN=-82

12:02

« RDF

104455

ThAP

3g3888s8scsse

000002

NN
PIPNININD
b b b b

0052064

PAGE 40

GLOBAL SUBROUTINES SECTION

Esthor"

00371?

R2EROR

104406
000406
005726
005726

;SCLP!
$
(SP)+
(SP)+

6%:

2,.R2TM

Sisaor

104455

000002
070000
004176
012700
104436

7$:

000004

«WORD
CLRVEC
MOV
TRAP

10004$:

104405

ENDSEG
TRAP

SEQ 0040

JREGISIER 2 NOT EQUAL TO 0

sBRANCH AROUND TIME OUT ERROR
sCLEAN UP STACK
sCLEAN UP STACK

sTIME OUT ERROR REG 2

R2TM
#4
#6 RO

sCLEAR VECTOR

CSCVEC

CSESEG

sCLEAR MSAD BITS 15:0 IN CONTROL REGISTER 4 AND CHECK THAT THESE BITS
sARE CLEAR BY READING BACK CONTROL REGISTER 4.
104404

012746

C$BSEG

#4,488 ,APRI07
#PRI07,-(SP)
#8$,-(SM)
#4,-(SP)
#3,-(SP)

000340
005320
000004
000003
000010
002276
002276
174746
002276

;SETUP VECTOR

CSSVEC

#10,5P
R4LOAD
R4LOAD
, 3REG4
SREG4 ,R4READ

174752
002300
002300

82LOAD.R4READ
3, ,R4EROR

§iERor

sSETUP TO CLEAR ALL MSAD BITS
sWRITE WORD INTO REGISTER 4
sREAD WORD BACK FROM REGISTER &
s COMPARE WORD LOADED WITH READ
sIF LOADED OK THEN CONTINUE
sREGISTER & NOT EQUAL TO ZERO

R4EROR
104406
000406
005726
005726

CSCLP1
9%

104455

gisaor

012700

R4TM
a4
#4 R0

(SP)+
(SP)+

3, ,R4TM

000003
000000
004220

sBRANCH AROUND TIME OUT ERROR
sCLEAN UP STACK
sCLEAN UP STACK
sTIME OUT ERROR REG 4

000004

9%:

sCLEAR VECTOR

d —D D

WA LA LS LN LN LN TN LS LN TN LS OIS TN IS TS DSOS US DSOS TN TN N TN TN TN LV ON DN OV DN N NN NN LN LN TNT NI ST NT NN N TN

GLOBAL AREAS
CVCDAB.P11

MACY11 30 A(1052)
17-JUN-82
1:26

17=JUN-82

104436
100058:

000207

CSCVEC

TRAP
RTS

CSESEG
PC

SEQ 0041

sRETURN BACK TO TEST

AND COMPARE CONTENTS OF REGISTER 0

:CONDITION CODES ARE SET ON EXIT AS RESULT OF THE '‘CMP" INSTRUCTION.

D d e o

002254

LDRDRO: :MOV
LDRDOR: : MOV
READRO: :MOV

ROLOAD ,ROGOOD
ROLOAD,3REGO
@REGO,ROREAD

BIC
CMP

ROMASK ,ROBAD
ROGCOD ,ROBAD

D e

MOV

RTS

sPUT DATA LOADED INTO EXPECTED
JWRITE WORD TO REGISTER 0
sREAD REGISTER CONTENTS BACK

ROREAD , ROBAD

sCOPY REG O RE/D TO ALLOW MASKING

SEXIT WITH CONDITION CODES SET

sROUTINE TO LOAD, READ,

sCLEAR UNWANTEP BITS OF REG 0
s COMPARE EXFSCTED WITH THAT READ

AND COMPARE CONTENTS OF REGISTER 2.

D oD

:CONDITION CODES ARE SET ON EXIT AS RESULT OF ''CMP'‘ INSTRUCTION

D o

LDRDR2: :MOV
LDRD2R: :MOV

D ed o

READRZ: :MOV
MoV
8IC
CMP

RTS

R2LOAD,R2G00D
R2LOAD ,3REG2

@REG2,R2READ
R2READ ,R2BAD
RZMASK ,R2BAD
R2GOOD ,R2BAD
PC

sPUT DATA TO BE LOADED INTO EXPECTED
sWRITE BITS INTO REGISTER 2

sREAD REGISTER 2 BACK
:COPY DATA READ
sCLEAR UNWANTED BITS IN REG 2
sCHECK IF EXP EQUALS ACTUAL

SEXIT WITH CONDITION CODES SET

sROUTINE TO LOAD, READ AND COMPARE CONTENTS OF REGISTER 4.
sCONDITION CODES ARE SET ON EXET AS RESULT OF ‘'‘CMP'* INSTRUCTION.

W
=

d md md =D

TRAP
NDSEG

sROUTINE TO LOAD, READ,

013777
017737
023737
000207

PAGE 41

GLOBAL SUBROUTINES SECTION

104405

LDRDRS : :MOV

READRS : :MOV
CMP
RTS

R4LOAD,3REGS

SREG4 ,R4READ
R4LOAD ,REREAD
PC

sWRITE WORD INTO REGISTER 4
sREAD WORD BACK FROM REGISTER 4

s COMPARE WORD LOADED WITH READ

sRETURN WITH CONDITION CODES SET

sROUTINE TO LOAD, READ AND COMPARE CONTENTS OF CONTROL REGISTER 6
;CONDITION CODES ARE SET ON EXIT AS RESULT OF ‘‘CMP'* INSTRUCTION.

VS WN=O O

d =D
d
b e
d
d
b e
b

12:02

013737
013777
017737
013737
043737
023737
000207

LDRDR6 : :MOV

R6LOAD ,R6GOOD

sCOPY DATA TO BE LOADED

READRG : :MOV

SREG6,ROREAD

sREAD THE WORD BACK

8IC
CMP

RGMASK , R6BAD
R6GOOD , R6BAD

LDRD6R : :MOV

Mov
RTS

ENDMOD

R6LOAD ,3REG6

RG6READ ,R6BAD
PC

;WRITE WORD INTO REGISTER 6

:COPY DATA READ

sMASK OUT UNWANTCD BITS
s COMPARE DATA LOADED WITH DATA READ
sEXIT WITH CONDTION CODES SET

MISCELLANEOUS SECTIONS MACY11
CVCDAB.P11
17=JUN-82 11:26

2147
%}23
2150
2151
2152
2153

17-JUN-82
12:02
PAGE 42
GLOBAL SUBROUTINES SECTION

.TITLE MISCELLANEOUS SECTIONS
.SBTTL REPORT CODING SECTION
005554

BGNMOD
J4e
: THE REPQFT CODING SECTION CONTAINS THE

%}gg

2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
%};?

30A(1052)

s "PRINTS''

005554
005554
005554

005554
005556

LSRPT::

CALLS THAT GENERATE STATISTICAL REPORTS.

BGNRPT

EXIT

000167
000000

LWORD
LWORD

RPT

JSJMP
L10013-2-.

.EVEN

005560
005560
005560

104425

2172
2173

L10013:

.SBTTL

2174

ENDRPT
TRAP

CSRPT

PROTECTION TABLE

144

2175
2176
2177
2178
2179
g}g?

s THIS TABLE IS USED BY THE RUNTIME SERVICES
;s TO PROTECT THE LOAD MEDIA.
.005562
005562

2182
2183
g}gg

005562
005564
005566

2186
2187

005570

LSPROT: :

177777
177777
177777

BGNPROT
-1
-1
-1
ENDPROT

JOFFSET INTO P-TABLE FOR CSR ADDRESS
sOFFSET INTO P-TABLE FOR MASSBUS ADDRESS
JOFFSET INTO P-TABLE FOR DRIVE NUMBER

SEQ 0042

MISCELLANEOUS SECTIONS

MACY11 30A(1052)
17-JUN-82
12:02
:
INITIALIZE SECTION
17-JUN-82 11:26

—

SRS
oo
28 8RIRAREC283S
0

oUSTSUSUS VLSS NN VTN

CVCDAB.P11

D e

.SBTTL

E_4
PAGE 43

SEQ 0043

INITIALIZE SECTION

8
v

LSINIT::

012700
104447
103410

~
o

005570
005574

g
W

b i o

s THE INITIALIZE SECTION CONTAINS THE CODING THAT IS PERFORMED
: AT THE BEGINNING OF EACH PASS.

005600
005600
005604

012700
104447

005606

103404

2208
2209

005610
005614

012700
1046447

2211

005616

103001

2213

005620

104433

2215
2216

005622
005626

012700
104447

2218
2219

103003
012737

2221
2222

005630
005632
005640
005640
005644

2226
2225

005646
005650

103431
005237

2227
2228
2229

005654
005660
885662

013700
104442
010005

2203
2206

012700
104447

000040

BGNINIT
READEF

MOV

#EF.START

TRAP
CSREFG
gggnPLerss
READEF

000037

MOV

#EF.PWR

TRAP

CSREFG

2s:

000035

BRESET
TRAP

READEF
MOV
TRAP

002246

000036

3s:

MOV
READEF
MOV

4$:

002246

INC

CSREFG

5$:

002245

100400

:IF NOT GO CHECK IF CONTINUE

;SETUP TO INIT UNIT NUMBER
;CHECK IF CONTINUE

RO,RS

MOV
CLR
MOV

#REGO,R1
R2
(RS), (R1)

:1F YES THEN EXIT

;INC TO NEW UNIT NUMBER
sGET DEVICE INFORMATION

CSGPHRD

;GO TRY ANOTHER UNIT

sADDRESS OF MS DEVICE ADDRESS TABLE
sCLEAR OFFSET TO ADD TO TABLE ADDRESS
:GET ADDRESS AND SAVE

ADD

R2,(R1)+

;ADD OFFSET TO ADDRESS

CMP
BNE

#10,R2
5$

sCHECK IF DONE LOADING TABLE
:GO UPDATE NEXT ADDRESS

MOVB

(RS) , IDDEV+1

ST
CLR

002250

MOV

}zg

000010

:SEE IF A NEW PASS

#-1,UNITNB
#EF.CONTINUE
#EF .CONTINUE
RO

gggonPLezg

002234

:IF MOT CHECK IN CONTINUE
JINITIALIZE THE SYSTEM TO A KNOWN STATE

MOV

TRAP

;SEE IF RECOVERING FROM A POWER FAIL

UNITNB
UN]TNB,RS
UNITNB,RO

GPHARD

:BRANCH IF RESTART

#EF .NEW
#EF .NEW,RO

TRAP
CSREFG
gggnPLsrgs

002246

CSRESET

8?5“""‘;5

17277277

:SEE IF A RESTART COMMAND

#EF .PWR RO

S?EO"PLEEE
1$:

;BRANCH IF START COMMAND

#EF .RESTART
RO

READEF

MOV

#EF.RESTART

TRAP
CSREFG
gggflptergs

000034

:SEE IF A START COMMAND

#EF.START
RO

MOV

(RS)+
IDDEV

#IDH!SIGBH, IDTYPE

:UPDATE OFFSET BY 2

©+

JUPDATE THE POINTER
sCLEAR OUT DEVICE NUMBER

:GET THE MS DEVICE NUMBER

sSETUP MS DEVICE TYPE

SETPRI
MOV

#PRIO?
#PR107,RO

EXIT

TRAP

104432
000002

TRAP
.WORD

SEQ 0044

sRAISE PROCESSOR PRIORITY

C$SPRI

wvi—

104441

6$:

000340

OMt
O
-4

012700

F &
PAGE 44

r~eyes

MISCELLANEOUS SECTIONS HAC;A1 30A(1052)
17=JUN=-82 12:02
CVCDAB. P31
17=JUN-82 11:
INITIALIZE SECTION

.EVEN

L10015:

1044611

TRAP

CSINIT

AUTODROP SECTION

+
+

.SBTTL

ENDINIT

THIS CODE IS EXECUTED IMMEDIATELY AFTER THE INITIALIZE CODE IF
THE
"'ADR’'' FLAG WAS SET.
THE UNIT(S) UNDER TEST ARE CHECKED TO
SEE IF THEY WILL RESPOND.
THOSE THAT DON'T ARE IMMEDIATELY
DROPPED FROM TESTING.

005746
005746
005746
005746
005746

LSAUTO::

L10016:

104461

.SBTTL

BGNAUTO

ENDAUTO
TRAP

CSAUTO

CLEANUP CODING SECTION

. té

: THE CLEANUP CODING SECTION CONTAINS THE CODING THAT IS PERFORMED

AFTER THE HARDWARE TESTS HAVE BEEN PERFORMED.

005750
005750
005750

013777

002244

174256

005756
005764

012777
012777

000000
000000

174252
174246

005772
005772
005774

104432

000002

BGNCLN
LSCLEAN::
MOV

IDDEV,3REGO

MOV
MOV

#0,8REG2
#0,3REGS

EXIT

TRAP

LWORD

.EVEN

005776

ENDCLN

CLN

CSEXIT

L10017-.

sCLEAR CONTROL REGISTER O EXCEPT

sFOR DEVICE NUMBER

:CLEAR REGISTER 2
:CLEAR REGISTER &

[

. MISCELLANEOUS SECTIONS

| CVCDAB.P11

2300

53381

2 §

005776

17-JUN-82 11:26

104412

L10017:

006000
006000
006000
006200
006002

zgls
2319
2320
2321

006004

gg‘

006004

LSDU::

DU
JSJUMP
L10020-2-.

.EVEN

104453

L10C20:
.SBTTL

2326
2327
5328
3;3

ENDDU
TRAP

(CSDU

ADD UNIT SECTION

I
; THE ADD=UNIT SECTION CONTAINS ANY CODE THE PROGRAMMER WISHES
:
TO BE EXECUTED IN CONJUNCTION WITH THE ADDING OF A UNIT BACK

5331

2!3;
2333
Si;‘

006006
006006

2%30
§d3

006006
006010

! $3%
$335 006006

000167
000000

006012

00601

333

006014

TO THE TEST CYCLE.

LSAU::

;:g
it:. 00601
©m

CSCLEAN

BGNDU

EXIT
.WORD
.WORD

000167
000000

2325

TRAP

.SBTTL DROP UNIT SECTION

2308

345

G 4

PAGE 45

: THE DROP-UNIT SECTION CONTAINS THE CODING THAT CAUSES A DEVICE
: TO NO LONGER BE TESTED.

2325 006004

12:02

CLEANUP CODING SECTION

2309
2310
2311
2312
2313
2314
2315
gg:g

17-JUN=-82

2305

2306
2307

MACY11 30A(1052)

104452

EXIT

WORD
WORD

.EVEN
ENDAU
L10021:
TRAP

ENDMOD

JSJMP
L10021=2-.

(SAU

SEQ 0045

. WARDWARE TESTS

CvCDAB.P11

i
MACY11 30A(1052)

17-JUN-82 11:26

17-JUN-82

12:02

PAGE 46

ADD UNIT SECTION

%gg?

+TITLE HARDWARE TESTS

%gg;

.SBTTL

2354

533

006014

SEQ 0046

TEST 1: SELECT AND INITIALIZZ MEMORY SIMULATOR
BGNMOD

144

2357
2358
2359

¢ TEST TO CHECK THAT THE MEMORY SIMULATOR CAN BE SELECTED AND INITIALIZED
¢ TO A KNOWN STATE. THIS TEST WILL BE EXECUTED AT THE BEGINNING OF EVERY
; TEST TO PUT THE MODULE IN A KNOWN STATE.
THE TEST WILL LOAD THE DEVICE

236%

: READ ONLY BITS, WRV H AND RDV H, ARE NOT CHECKED. THE TEST WILL LOAD THE

2360
2361

s NUMBER INTO REGISTER O AND CHECK THAT THE DEVICE NUMBER CAN BE READ BACK
: CORRECTLY. THE R/W BITS IN THE LOW BYTE ARE CHECKED TO BE CLEARED. THE

236
2364
2365
2366
2367
2368
2369

s
¢
¢
:
:
:
¢

DEVICE NUMBER AND THE SIGNAL I/D H INTO REGISTER O AND CHECK THAT THE
DEVICE TYPE AND THE R/W BITS IN THE LOW BYTE CAN BE READ BACK CORRECTLY.
THE TEST WILL THEN LOAD THE DEVICE NUMBER AND THE SIGNAL RST H (CLEAR
READ AND WRITE VIOLATION FLIP=FLOPS) INTO REGISTER O AND CHECK THAT THE
DEVICE NUMBER AND THE SIGNAL RST H ARE SET IN REGISTER 0. THE OTHER READ
WRITE BITS AND THE READ ONLY BITS (WRVH AND RDVH) ARE CHECKED TO BE
CLEARED. THE LAST PART OF THIS TEST WILL BE TO CLEAR THE SIGNAL RST M

: IN REGISTER O AND CHECK THAT REGISTER O IS READ BACK CORRECTLY.

gg;?

2372
2373
2374
2375
2376
%g;;

006014
006014
006014

2379
2380
2381
2382
2383
53332

006020
006020
006020

004737

104401

004550

T::

L10022:

BGNTST
JSR

PC,INITMS

ENDTST
TRAP

CSETST

SINITIALIZE THE MEMORY SIMULATOR

HARDWARE TESTS

CVCDAB.P11

MACY11_30A(1052)

17-JUN-82 11:26

17=JUN-82
12:02 PAGE 47
TEST 2: CONTROL REG O TEST (1°S, 0°'S, 1°'S + 0°S, 0°'S + 1'S)

+
Ea

.SBTTL TEST 2: CONTROL REG O TEST (1'S, 0°'S, 1°'S + 0°'S, 0°'S + 1'S)
TEST TO CHECK CONTROL REGISTER 0.

BITS RST W, CTS H, MP H, 8 BIT H,

THIS TEST WILL CHECK THAT THE READ/WRITE
AND CK H, CAN BE SET AND CLEARED.
THIS

IS A BASIC TEST OF THE READ/WRITE BITS. THE READ ONLY BITS RDV H AND WRV H
WILL BE CHECKED TO BE CLEARED WHEN THE SIGNAL RST W IS ASSERTED,OTHERWISE,
THOSE BITS WILL BE IGNORED.
THE TEST PATTERNS USED ARE AS FOLLOWS:
1. SET ALL R/W BITS TO A 1 AND THEN A 0
BGNTST
..

—

2. SET R/W BITS TO ALTERNATING 1°S + 0°'S AND THEN 0°S + 1°'S

004550

JSR

12.1:

PC,INITMS

sSELECT AND INITIALIZE MEM SIM

BGNSUB
TRAP

csasus

BI T H AND CK H CAN BE SET TO 1
sCHECK THE RST H, CTS H, MP H, 8 8I
sRDV H AND WRV H WILL BE CHECKE P TO BE 0

BGNSEG

000117
000060
005346

TRAP

002252
002256

C$BSEG

#RSTH!CTSH!MPH!BIT8H!CKH,ROLOAD ;SET ALL R/W BITS TO 1
#RDVH !WRVH ,ROMASK
sCLEAR MASK BITS FOR RDV AND WRYV
PC.LDRDRO
:GO LOAD, READ AND COMPARE REG 0

1$
1, ,ROEROR

O -

CSERDF

sIF LOAD EQUALS READ - CONTINUE

sR/W BITS NOT ALL SET

. WORD
1$:
ENDSEG
100008
:
TRAP

ROEROR

CSESEG

sCHECK THAT ALL R/W BITS CAN BE CLE ARED
sRDV AND WRV ARE IGNORED DURING THIS SUB TEST

PNONIND
b b i e b

OO0~ NOO

SEERRZEEE

104404
105037

052737
004737
001404

002252
000060
005346

002256

104405

sCLEAR ALL R/W BITS TO BE LOADED
sSETUP TO IGNORE RDV AND WRV BITS
:GO LOAD, READ AND COMPARE REG 0

sALL R/W BITS NOT O

.ROEROR

gienor

104455
000001

003624

#RDVH
! WRVH, ROMASK
PC,LDRDRO

2%:
10001$:

ROEROR

CSESEG

sIF ALL R/W BITS ARE 0 = CONT

SEQ 0047

| WARDWARE TESTS

CVCDAB.P11
442
443

0061
0061

?zzg

006122

446

006124

2647
223

006124
006124

WACY11 3omosz>

17-JUN=-82

11:26

17=JUN=82

12:02

PAGE 48

TEST 2: CONTROL REG O TEST (1°'S, 0°S, 1°S + 0°'S, 0°'S + 1°'S)

L10024:

104403

12.2:

104402

ENDSUB

TRAP

(CSESUB

BGNSUB

TRAP

($BSUB

g‘(zgg

;CHECK THAT ALTERNATING BITS IN REG O CAN BE SET AND CLEARED

;CHECK THAT CTS W AND 8 BIT H ARE O WHEN RST H, MP H AND CK H ARE 1

,22‘

JRDV H AND WRV H ARE CHECKED TO BE 0

2455
2456
2457

006126
006126
006130

104404
112737

000105

2459

006144

004737

005346

002252

2458 006136 042737 000060 002256
2460
2461

2462

006150
006152

001404

006154

000001

2465
2466
2667
gzgg

006160
006162
oomgg
006162

003624

2464

.WORD

38:
100008:

104405

2477

006202

104404
112737

000012

004737

005346

006174

052737 000060

006206

001404

2479 006210

2481

3&5’2 000001

2483

006216

003624

2485
2239

006 58
006220

104405

2484 ooogzo

2489

006

2492
2493
523’;

006224
006224
006224

gzg?

3s
.ROEROR

*IF OK THEN CONTINUE
*A BIT IS SHORTED TC ANOTHER

cisaor
o

TRAP

CSESEG

BGNSEG
TRAP
MOVB

002252

002256

) mo READ AND COMPARE REG 0

ROEROR

104403
104401

-WORD

L10025:

L10023:

:GO LOAD, READ AND COMPARE REG 0

l.s

.WORD

100018
:

PC,LDRDRO

BEQ

TRAP

48:

;SETUP BITS TO LOAD

#RDVH | WRVH , ROMASK

ERRDF

000000

(SBSEG
#CTSH'BIT8H,ROLOAD

BIS

J3R

2480 006210 104455

488

:SETUP TO CHECK RDV AND WRV

-WORD

.WORD
ENDSEG

;SETUP BITS TO LOAD

#RDVH ! WRVH , ROMASK

;CHECK THAT RST H, MP H, AND CK H ARE O WHEN CTS H AND 8 BIT W ARE 1
*RDV H AND WRV H ARE IGNORED
006164
006164
006166

PC,LDRDRO

TRAP

006156 000000

2473
2676
2475

2478

JSR

BEQ
ERRDF

2470
52;5

2676

(S$BSEG
#RSTH'MPH!CKH,ROLOAD

BIC

006152 104455

2463

BGNSEG
TRAP
MOVB

.WORD

ENDSEG
TRAP

.ROEROR

cimr

ROEROR
CSESEG

ENDSUB
TRAP

(CSESUB

ENDTST
TRAP

CSETST

:SETUP TO IGNORE RDV AND WRV

:IF OK THEN CONTINUE

*A BIT IS SHORTED TO ANOTHER

SEQ 0048

HARDWARE TESTS MACY11 30A(1052)
17=JUN-82 11:26
CVCDAB.P11

K &
17=JUN=-82 12:02 PAGE 49
TEST 3: CONTROL REG O TEST USING A BINARY COUNT

26496
2497
2498
2499
2500
2501
250
250
2504
2505

TEST TO CHECK CONTROL REGISTER 0.
THIS TEST WILL CHECK THE SIGNALS RST W,
CTS
H MP H, 8 BIT H, AND CK H USING A BINARY COUNT PATTERN.
THE READ ONLY

BITS RDV H AND WRV H “WILL BE CHECKED FOR A O WHEN THE SIGNAL RST H IS SET,
OTHERWISE, THE TWO SIGNALS WILL BE IGNORED.

006246

2515 %%64

2516
2517

006270
006272

2521
2522
2523
25264
2525
2526
2527
2528
2529
2530
2531
253§
2533
2534
5235

006300
00630
00630
00630

—

ROLOAD

C$BSEG

00225
00225

#RDVH'!WRVH, ROMASK
OgSTH.ROLOAD

002256

#RDVH !WRVH, ROMASK

2$:

;g.LDRDRO

cisnor

,ROEROR

e o
2520 882%76
006304
006310
006316
006320
006326
006330
006336
006340
006340
006340

PC,INITMS

—

JSR

F+3) 006560
251%

BGNTST

004737

52 105037

2508

+SBTTL TEST 3: CONTROL REG O TEST USING A BINARY COUNT

sSELECT MS AND lNlTlA%l% E 1l T
sSET LOW BYTE OF REG
00

sSETUP TO IGNORE RDV H AND WRV
H
sCHECK IF SIGNAL RST H WILL BE SE?
¢IF NOT THEN IGNORE RDV H AND WRV H
sSETUP TO CHECK RDYV H AND WRV H
:GO LOAD, READ AND CHECK REGISTER 0
sIF LOADED OK THEN CONTINUE
sREGISTER 0 NOT EQUAL EXPECTED

3s:

10000$:

ROEROR

CSESEG

002252
720020

r02252

000100

002252

:gxu.ROLono

000100

002252

#CKH,ROLOAD
1$

ROLOAD

:glt‘.ROLOAD

4(S:

L10026:

CSETST

sUPDATE TEST PATTERN BY 1
sCHECK IF LOW R/W BITS DONE
sIF _NOT LOAD NEXT BIT
sCHECK IF 2ND PORTION DONE
sIF _YES THEN END OF TEST
sSETUP TO DO 2ND PORTION OF TEST
;D0 BINARY COUNT AGAIN WITH CK H SET

SEQ 0049

HARDWARE TESTS

CVCDAB.P11

MACY11 _30A(1052)

17=JUN-82 11:26

17-JuN-82

12:02

PAGE 50

TEST &: CONTROL REG 2 TEST (1°'S, 0'S, 1°S + 0'S, 0°'S + 1'S)

SEQ 0050

«SBTTL TEST &: CONTROL REG 2 TEST (1'S, 0'S, 1'S + 0'S, 0°'S + 1'S)

539

2541
29.;

: THE SIGNALS MSAD16 W, MSAD17 W, MSELO M AND MSEL1 M CAN BE SET AND CLEARED
: IN REGISTER 2.
THE READ ONLY SIGNALS ESR M, WREN H, AND MSBRK H ARE IG~-

544,

: TEST OF THE READ/WRITE BITS.

&»H
o

§g§z

;

:
:

2548
2549
2550
2551

00634
00634
006342

2554
2555
gggg

006354
006354
006354

004737

006346 012737

004550

177740

14::

002270

JSR

006356

2563

006360 012737 000017 002264

;SELECT AND INIT MEM SIM

:SETUP REG 2 MASK WORD

BGNSUB
TRAP

006356

104404

006366
006372
006374
006374
006376
006400
006402
006404
006404
006404

004737
001404

BGNSEG
TRAP

005414

104455
000002
000000
003712
104405

18:
100008:

2575
gg;g

($BSUB

C$BSEG

MOV

#MSAD16 !MSAD17!MSELO'MSEL1,R2LOAD ;SETUP BITS TO LOAD

TRAP

CSESEG

JSR
BEQ
ERRDF
TRAP
LWORD
WORD
.WORD
ENDSEG

PC,LDRDR2
1$
2..R2EROR
CS$ERDF
2
O
R2EROR

;GO LOAD, READ AND COMPARE REG 2
*IF ALL ONES THEN CONTINUE
2A BIT(S) FAILED TO SET

sCHECK THAT MSAD16 H, MSAD17 H, MSELO H, MSEL1 H CAN BE CLEARED. THE
:REMAINING BITS ARE IGNORED DURING THIS TEST.

2578
2579

006406
006406

104404

BGNSEG
TRAP

2582

006420

001404

BEQ

2584

0064622

104455

TRAP

2580 006410 005037 002264
2581 006414 004737 005414
2585
2586
2587
2588
2589
2590
2591
2592

#177740,R2MASK

:THE REMAINING BITS ARE IGNORED BY THIS TEST

2561

2583

PC,INITMS

;CHECK THAT MSAD16 H, MSAD17 W, MSELO H, AND MSEL1 W CAN BE SET TO 1.

gggg

2564
2565
2566
2567
2568
2569
2570
2571
2572
52;2

BGNTST

MOV
T4.1:

104402

THIS IS A BASIC

THE TEST PATTERNS USED ARE AS FOLLOWS:

1. SET ALL R/W BITS TO A 1 AND THEN A 0
2. SET R/W BITS TO ALTERNATING 1°'S + 0°S AND THEN 0°'S + 1°'S

2558

2562

THIS TEST WILL CHECK THAT

: NORED DURING THIS TEST ALONG WITH OTHER UNDEFINED BITS.

2545
ggz

ggg

TEST TO CHECK CONTROL REGISTER 2 READ/WRITE BITS.

006422
006424
006426
006430
006432
006432
006432
006434
006434

000002
000000
003712

104405

28:
10001$:
L10030:

($BSEG

CLR
JSR

R2LOAD
PC.,LDRDR2

:SETUP BITS TO LOAD TO 0
:GO LOAD, READ AND COMPARE REG 2

ERRDF

2, ,R2EROK

‘A BIT(S) FAILED TO ZERO

C$ERDF

LWORD
WORD
"WORD
ENDSEG

2
O
R2EROR

TRAP
ENDSUB

CSESEG

*IF ALL ZERO THEN CONT

HARDWARE TESTS MACY11_30A(1052)
17=JUN-82 11:26
CVCDAB.P11

006434
006436
006436
006436

&
12:02 PAGE 51
TEST &: CONTROL REG 2 TEST (1°'S, 0'S, 1'S + 0'S, 0'S + 1'S)

17=JUN-82

104403

TRAP

T4.2:

104402

CSESUB

BGNSUB
TRAP

csasus

CHECK THAT ALTERNATING BITS IN REG 2 CAN BE SET AND CLEARED.
CHECK THAT MSAD17 H AND MSEL1 H ARE 0 WHEN MSAD16 H AND MSELO H

ARE SET TO A ONE.

000005
005414

BGNSEG
TRAP
MOV

002264

JSR
BEQ
ERRDF

TRAP

1$:
10000$:

C$BSEG
#MSAD16'MSELO,R2LOAD
PC,LDRDR?
1s
LR2EROR

ci
ERDF

JWORD
WORD
.WORD
ENDSEG

2
0
R2EROR

TRAP

CSESEG

;SETUP BITS TO LOAD INTO REG 2
:GO LOAD, READ, AND COMPARE REG 2
*IF OK THEN CONTINUE
*ALTERNATING 1'S AND 0°'S FAILED

sCHECK THAT MSAD16 H AND MSELO H ARE 0 WHEN MSAD17 H AND MSEL1 H

:ARE SET TO A ONE

104404

012737
004
001406

000012
005414

002264

104405

104403
104401

($BSEG
#MSAD17!MSEL1,R2LOAD

TRAP

cienor

JSR
BEQ
ERRDF

104455
000002

000000
003712

BGNSEG
TRAP
MOV

2%:

10001$:

L10031:
L10027:

PC,LDRDR2
2
.R2EROR

WORD
JWORD
.WORD
ENDSEG

2
0

TRAP

CSESEG

TRAP

CSESUB

TRAP

(SETST

ENDSUB
ENDTST

R2EROR

;SETUP BITS TO LOAD

:GO LOAD, READ, AND COMPARE REG 2
:IF EQUAL THEN CONT
:ALTERNATING 0°S AND 1°S

SEQ 0051

HARDWARE TESTS

CvCDAB.P11

MACY11 30A(5252)
17-JUN-82
1

17=JUN=-82 12:02 PAGE 52
TEST 5: CONTROL REG 2 TEST USING A BINARY COUNT

SEQ 0052

.SBTTL TEST 5: CONTROL REG 2 TEST USING A BINARY COUNT
14

: TEST TO CHECK CONTROL REGISTER 2 READ/WRITE BITS.

THIS TEST WILL CHECK THE

SIGNALS MSAD16 H, MSAD17 H, MSELO H, AND MSEL2 W USING A BINARY COUNT PATTERN.

THE READ ONLY BITS (ESR M, WREN W, AND MSBRK H) AND THE UNUSED BITS WILL BE
XGNORED DURING THIS TEST.

004550
0
177760

BGNTST
JSR

MOV
002270

18:

005414

CLR
MOV

BGNSEG
TRAP

002264

;GO LOAD, READ AND COMPARE REG 2

TRAP

cisnor

:DATA LOADED NOT EQL EXPECTED

104401

.WORD
WORD
.WORD
ENDSEG
TRAP

INC

001363

L10032:

($BSEG

:SET PATTERN INITIALLY TO 0
*SETUP REG 2 MASK WORD

PC,LDRDR2

ERRDF

100008:

R2LOA
o
#177740,R2MASK

sSELECT AND INIT MEMORY SIM

sSETUP TEST COUNTER

JSR

BEQ

28:

PC xnxrns

#20.R

LR2EROR

:IF COMPARED OK THEN CONT

2
0
R2EROR
(SESEG

R2LOAD

DEC
BNE
ENDTST

R1
1$

TRAP

CSETST

:UPDATE THE TEST PATTERN

*DECREMENT THE TEST COUNTER
:IF NOT O THEN DO NEXT PATTERN

HARDWARE TESTS

CVCDAB.P11

MAC 1 30A(10$2)
17=Jun-82 11:26

17=JUN-82
12:02 PAGE 53
TEST 6: CONTROL REG & TEST (1'S AND THEN 0'S)

3676

SEQ 0053

«SBTTL TEST 6: CONTROL REG & TEST (1°'S AND THEN 0'S)

67
678
79

144

s YEST TO CHECK CONTROL REGISTER 4 BY LOADING ALL ONES INTO REGISTER &4 AND
¢ CHECKING THAT ALL ONES WERE LOADED INTO REGI STER & BY READING REGISTER 4.

THE TEST WILL THEN LOAD ALL ZEROES INTO REGI STER

; IEROES WERE LOADED BY READING THE REGISTER.

004737

T6::

004550

& AND CHECK THAT ALL

BGNTST
JSR

PC.INITMS

sSELECT AND INIT MEM SIMULATOR

BGNSEG
177777
005462

002276

TRAP
MOV
JSR

($BSEG
#=1,R4LOAD
PC,LDRDR

TRAP

LRGEROR
cienor

BEQ

ERRDF

§§a

g 83 SRR
g
pddp

sSET MSAD BITS 15 THROUGH 0 TO A 1

00008

.WORD
-WORD
.WORD
ENDSEG

o
R4EROR

TRAP

(SESEG

sSETUP TO 'OAD ALL ONES INTO REG 4
sLOAD, RE/) AND COMPARE REG 4
sIF ALL ONES THEN CONT
sFAILED TO LOAD ALL ONES

sSET MSAD BITS 15 THROUGH 0 TO A 0

HEh

006636
006636
006640
006644
006650
006652
006652
006654
006656

BGNSEG
TRAP
CLR
JSR

002276
005462

BEQ
ERRDF

TRAP

006662

2%:
104405
104401

10001$:

L10033:

($BSEG

R4LOAD
PC.LDRDRG
28
LRGEROR

cfenor

WORD
WORD
.WORD
ENDSEG

3
O
R4EROR

TRAP

CSESEG

TRAP

CSETST

ENDTS

sSETUP TO LOAD ALL ZEROES INTO REG 4
sLOAD, READ AND COMPARE RES 4
sIF ALL ZEORES THEN CONT
sREGISTER 4 NOT ALL 0°'S

[
[

HARDWARE TESTS

CVCDAB.P11

MACYT 30A(1052)
17=JUN-82 11:26

17=JUN-82 12:02 PAGE 54
TEST 7: CONTROL REG & TEST (1°S + 0'S, AND 0°'S + 1'S)

.SBTTL TEST 7: CONTROL REG & TEST (1'S + 0°'S, AND 0°'S + 1°S)
s+

: TEST TO CHECK CONTROL REGISTER 4 BY LOADING ALTERNATING ONES AND ZEROES AND
:

004737

THEN ZEROES AND ONES.

T7::

004550

CHECKS THAT ADJACENT BITS ARE NOT SHORED TOGETHER.

BGNTST
JSR

PC,INITMS

sSELECT AND INIT MS

sLOAD REGISTER & WITH 125252 PATTERN
104404

012737
004737
001404

BGNSEG

125252

005462

TRAP

002276

#125252 ,R4LOAD
PC.LDRDR4

sSETUP PATTERN TO LOAD
sLOAD, READ AND COMPARE REGISTER 4

ERRDF

3, R‘EROR

sPATTERN READ NEQ 125252

.WORD
.WORD
.WORD
ENDSEG

3
0
R4EROR

TRAP

CSESEG

BEQ

TRAP

00008

104405

C$BSEG

MOV
JSR

18’

CSE

s IF PATTERN OK THEN CONTINUE

;LOAD REGISTER & WITH 052525 PATTERN
104404

012737
004737
001404
104455
000003
000000
004000
104405
104401

BGNSEG

052525
005462

TRAP

002276

#052525 ,R4LOAD
PC.LDRDR4
2%
3, ,R4EROR

LWORD
WORD
.WORD
ENDSEG

3
0
R&4EROR

TRAP

CSESEG

TRAP

CSETST

TRAP

2$:

10001$:

L10034:

C$BSEG

MoV
JSR
BEQ
ERRDF

ENDTST

CSERDF

sSETUP FATTERN TO LOAD
sLOAD, READ AND COMPARE REGISTER 4
sIF PATTERN OK THEN CONT
sPATTERN READ NEQ 052525

SEQ 0054

HARDWARE TESTS MACY11 30A(1052)
CVCDAB.P11
17=JUN-82 11:26

17=JUN-82
12:02
PAGE 55
TEST 8: CONTROL REG & TEST ON LOW BYTE USING BINARY COUNT

5;93

.SBTTL TEST 8: CONTROL REG 4 TEST ON LOW BYTE USING BINARY COUNT

2771
%;;g

144
: TEST TO CHECK LOW BYTE OF CONTROL REGISTER 4 USING A BINARY COUNT PATTERN

2774
2775
2776
2777
2778
2779
2780
2781

006754
006754
006754
006760
006764
006764
006766

2783

006774

2782

006772

004737
005037

004550
002276

104404
004737

005462

001404

18::

‘

1$:

006776
007000
007002

007004
007004
007004
007006
007012
007020
007022
007022
007022

ERRDF

TRAP

000003
000000
004000
104405
005237
032737
001761
104401

JSR
CLR
BGNSEG
TRAP
JSR

BEQ

2784 006774 104455

2785
2786
2787
2788
2789
2790
2791
2792
2793
279
2795
2796

BGNTST

28:
100008:
002276
000400

002276
L10035:

PC, INITMS
R4LOAD

;SELECT AND INIT MEM SIM
:SET PATTERN INITIALLY TO 0

($BSEG
PC,LDRDRG

:LOAD, READ AND COMPARE PATTERN

LR4EROR

:PATTERN LOADED NEQ PATTERN READ

cieaor

.WORD
WORD
.WORD
ENDSEG

3
0
R4EROR

TRAP
INC
BIT
BEQ
ENDTST

CSESEG
R4LOAD
#BIT8,R4LOAD
1$

TRAP

CSETST

*IF PATTERN OK THEN CONT

;UPDATE THE PATTERN BY 1
*CHECK IF DONE
+IF NOT THEN LOAD NEXT PATTERN

SEQ 0055

HARDWARE TESTS

CVCDAB.P1T

MACYN 30A(1052)

17-JUN-82 11:26

17-JUN-82
12 02 PAGE 56
9 : CONTROL REG & TEST HIGH BYTE USING BINARY COUNT
TEST

.SBTTL TEST 9: CONTROL REG & TEST HIGH BYTE USING BINARY COUNT
144

: TEST TO CHECK HIGH BYTE OF CONTROL REGISTER 4 USING A BINARY COUNT PATTERN

004737
005037

007034

104404

004550
002276

18:

005462

JSR
CLR
BGNSEG

007052

004000

. WORD
ENDSEG

2819
2820
gg%}

007054
007056
007064

104405
062737
001363

2824

007066

104401

:
38

b
—

LY
oo 0o

2816

JSR
BEQ
ERRDF

§§\fig 22

007024
007030

BGNTST

3
N

2806
2807

19::

TRAP

. WORD

2%:

:
100008

000400

002276

L10036:

PC,INITMS

R4LOAD

C$BSEG

PC,LDRDRé

cienor
3

LRGEROR

.WORD

0
R4EROR

TRAP
ADD

CSESEG
quIB~RGLOAD

TRAP

CSETST

BNE
ENDTST

sSELECT AND INIT MEM SIM
sSET PATTERN INITIALLY TO 0
sLOAD, READ AND COMPARE PATTERN
sIF PATTERN OK THEN CONT

sPATTERN LOADED NEQ PATTERN READ

sUPDATE THE DATA PATTERN
sIF NOT O THEN GO LOAD DATA PATTERN

SEQ 0056

HARDWARE TESTS

CVCDAB.P11

MACY11

30?(5252)

17=JUN=82 1

17=JUN=-82

12:02

PAGE 57

TEST 10: CHECK SIGNAL MSBRK H TO BE O IN CONTROL REG 2.

SEQ 0057

gggg

.SBTTL TEST 10: CHECK SIGNAL MSBRK H TO BE 0 IN CONTROL REG 2.

2828
2829
28
2831
2832
2833

e
: TEST TO CHECK THAT THE SIGNAL MSBRK H IN CONTROL REGISTER 2 CAN BE SET
: TO A O WHEN THE SIGNALS RST H AND MP H ARE ASSERTED IN CONTROL REGISTER 0.
: SETTING THE SIGNAL RST H WILL PRESET THE RDV AND WRV FLIP=-FLOP'S SUCH
: THAT THE SIGNAL BRK L WILL BE HIGH.
THE SIGNAL MP M WILL ALLOW THE
: SIGNAL BRK L AS A HIGH TO BE INVERTED, GENERATING THE SIGNAL MSBRK M AS

gggg

: 2EROES CHECKING THE SIGNAL MSBRK M TO BE A 0.

2834

2837
2838
2839
2840
2841
ggg

: A LOW OR ZERO.

007070
007070
007070
007074
007074

004737

T10::

004550

104404

2844

007076
007104
007112
007116
007120

052737
042737
004737
0061405

2853
2854
2855

007122
007124
007126

000001
000000
003624

007130

104406

007120

007130

000005
000060
005346

002252
002256

104455

sSELECT AND INIT THE MEMORY SIMULATOR

($BSEG

#RSTH!MPH,ROLOAD
#RDVH'WRVH ,ROMASK
PC,LDRDRO
1$
1, ,ROEROR

LWORD
WORD
.WORD

1
0
ROEROR

TRAP

CSCLP

CKLOOP

CHECK

CSERDF

:SETUP TO SET RST H AND MP H TO 1
JSETUP TO CHECK RDV AND WRY BITS
:GO LOAD, REAL AND CHECK REG 0
SIF OK THEN CONTINUE
*REGISTER 0 NOT EQULA EXPECTED

;LOAD ALL ZEROES INTO CONTROL REGISTER 2 AND CHECK THAT ALL ZEROES
*WERE LOADED AND THAT THE SIGNAL MSBRK M IS A 0.

2862
2863

007132 005037 002264
007136 012737 177540 002270

2865

007150 001404

007144

2866

007152

2868
2869
2870
2871
2872
2873
2874
2875
2876

007154
007156
007160
007162
0071
007162
007164
007164
007164

2867

PC,INITMS

8IS
BIC
JSR
BEQ
ERRDF

TRAP

2859
ggg?

2864

JSR
BGNSEG
TRAP

:THE SIGNALS RDV AND WRV TO BE A 0 AS THE RESULT OF RST M BEING SET.

2847
2848
2849
2850
2851

2856
%gg;

BGNTST

sSET THE SIGNAL RST H AND MP H TO A 1 IN CONTROL REGISTER 0.

g&g

2852

THE TEST WILL THEN LOAD AND READ CONTROL REGISTER 2 WITH

007152

004737

18:

005414

104405

104401

R2LOAD
#177540, R2MASK

;SETUP TO LOAD ALL ZEROES
:SETUP REG 2 MASK WORD

BEQ

:1F REG 2 OK THEN CONT

JSR

ERRDF

104455

000002
000000
003712

CLR
MOV
TRAP

28:
100008:
L10037:

PC,LDRDR2
2, ,R2EROR

CSERDF

WORD
WORD
.WORD
ENDSEG

2
O
R2EROR

TRAP
ENDTST

CSESEG

TRAP

CSETST

:GO LOAD,

READ AND CHECK REG 2

:REG 2 NOT EQUAL EXPECTED

HARDWARE TESTS MACY11_30A (1052)
17-JUN-82 11:2
CVCDAB.P11
:26

17=JUN=-82
12:02 PAGE 5 8
TE ST 17: CHECK 1K BY & MAP PROTECT RAM WITH 1'S AND THEN 0°'S

«SBTTL TEST 11: CHECK 1K BY & MAP PROTECT RAM WITH 1°S AND THEN 0°S
* 4*

TEST TO CHECK THE 1K BY & MAP PROTECT RAM WITH A PATTERN OF ALL ONES AND
THEN ALL ZEROES.
THE TEST WILL SELECT AND INITIALIZE THE MEMORY SIMULATOR.
THE TEST WILL SET THE SIGNAL MSEL1 H IN CONTROL REGISTER 2 WHICH WILL

SET THE SIGNAL SMPM L WHEN A WRITE TO REGISTER 6 IS ISSUED.
THE TEST WILL
THEN SELECT THE MEMORY SIMULATOR ADDRESS BY LOADING THE ADDRESS INTO
CONTROL REGISTER & BITS 15-8 AND CONTROL REGISTER 2 BITS 1-0.
THE TEST

WILL THEN WRITE ALL ONES INTO THE MAP PROTECTION RAM VIA REC'STER 6 AND
THEN READ THE RAM LOCATION BACK VIA CONTROL REGISTER 6.
THE RAM BITS

MUTB H, MPIN H,

WRE H, AND RDE H WILL BE CHECKED FOR ALL ONES. THE TEST

WILL THEN WRITE, READ AND CHECK THE LOCATION FOR ALL ZEROES. THE TEST

WILL THEN SEQUENCE TO THE NEXT ADDRESS AND REPEAT THE SAME TEST PATTERNS

UNTIL ALL ADDRESSES WAVE BEEN CHECKED.

004737
005001
005002

004550

1$:

104404

BGNTST

JSR

CLR
CLR

BGNSEG
TRAP

PC,INITMS
R1
02

;SELECT AND INIT MEMORY SIMULATOR

*CLEAR BITS 15-8 MSAD ADDRESS COUNTER
*CLEAR BITS 17-16 MSAD ADDRESS COUNTER

CS$BSEG

sSET SIGNAL MSEL1 H TO A 1 AND MSAD BITS 17 OR 16 TOA 1 OR 0 IN
sCONTROL REGISTER 2
000010
002264
177740
005414

002264

MOV

#MSEL1,R2LOAD

:SETUP TO SET MSEL1 BIT TO A 1

002270

MOV

#177740,R2MASK

:SETUP TO IGNORE REG 2 SITS 15-5

BEQ
ERRDF

28
2, ,R2EROR

BIS

JSR

TRAP

o ch wd

WNN=O

RIETRVERRGNZS
83883388338883838388888%3

2907

cd o

VRNV

e o

WORD
WORD
.WORD
CKLOOP

b o

TRAP

2933

R2 R;LOAo

PC,LDRDR2

CS$ERDF

sSETUP MSAD BITS 17 AND 16

:GO LOAD, READ AND COMPARE REG 2

:IF LOADED OK THEN CONTINUE
:REGISTER 2 FAILED TO LOAD CORRECTLY

2
O
R2EROR
CSCLP1

;LOAD MSAD BITS 15-8 INTO CONTROL REGISTER &
002276
005462

2$:

MOV
JSR

BEQ
ERRDF

TRAP

WORD
LWORD
.WORD

CKLOOP
TRAP

R1,R4LOAD
PC.LDRDR4

3$
3, ,R4EROR

C$ERDF

:SETUP BITS TO LOAD
:GO LOAD, READ AND COMPARE REG &

:IF REGISTER 4 CORRECT THEN CONT
:REGISTER & NOT EQUAL EXPECTED

3
O
R4EROR
(CSCLP1

sSET BITS MUTB H, MPINH, WRE H, RDE H TO A 1 IN LOCATION ADDRESSED

SEQ 0058

CVCDAB.P11

17=JUN-82
12:02 PAGE 59
TEST 11: CHECK 1K BY & MAP PROTECT RAM WITH 1'S AND THEN 0°'S

5338
36

s8Y CONTROL REGISTER 2 AND 4. THE SIGNAL SMPM L WILL BE ASSERTED
sON THE WRITE/READ TO REGISTER 6
177760
000017
005506

0023
00230

3s:

MOV
MOV
JSR

BEQ
ERRDF
TRAP

CKLOOP
TRAP

#177760,RE6MASK

SETUP REG 6 MASK WORD

2&,LDRDR6

;GO LOAD, READ AND COMPARE REGISTER 6

#MUTBH ! MPINH! WREH ! RDEH, R6LOAD

4 ,MSGM
AL INFO
P

C$ERDF

:IF DATA'OK THEN CONTINUE
sMAP PROTECTION RAM DATA ERROR

MSGMP
ALINFO

CSCLPI

JWRITE THE SAME LOCATION WITH ALL THE BITS SET TO A 0
4$:

¥SyfEIE

FAR

002302
005506

CLR
JSR
BEQ
ERRDF
TRAP

5%:

100008
:

2961

R6LOAD
PC.LDRDR6

& ,MSGMP
, AL INFO

Eisnor

.WORD
«WORD
. WORD
ENDSEG

MSGMP
ALINFO

TRAP

CSESEG

000400

qQSADB.R1

000001
000004

#MSAD16,R2
#MSELO,R2
1$

L10040:

CSETST

sSETUP ALL BITS TO BE LOADED AS A 0
:GO LOAD,READ AND COMPARE REG 6
:IF _OK THEN CONTINUE
;DATA ERROR MAP PROTECTION RAM

sUPDATE MSAD BITS 15-8 BY 1
sIF NOT O THEN DO NEXT ADDRESS
sUPDATE MSAD BITS 16 AND 17
sCHECK IF DONE
:IF NOT DONE DO RANGE OF ADDRESSES

—

MACY1 30A(5052)

17-JUN-82
1

SEQ 0059

| HARDWARE TESTS

CVCDAB.P11

30A(1052)

17=JUN-82 11:26

223;%
2974

17=JUN-82

13:02

m;s 60

TEST 12: CHECK

= —y

MACY11

1K BY & MAP PROTECT RAM (1°'S + 0°S, AND 0°'S + 1°'S).

«SBTTL TEST 12: CHECK 1K BY & MAP PROTECT RAM (1°'S + 0°S, AND 0°'S + 1°'S).

2975
2976
2977
2978

s TEST TO CHECK THE 1K BY & MAP PROTZCT RAM USING AN ALTERNATING ONES AND
; ZEROES PATTERN AND AN ALTERNATING ZEROES AND GNES PATTERN. THE TEST WILL
: ALSO CHECK THAT THE MAP PROTECT ZITS MPIN H AND WRE H CAN BE READ BACK
: INTO CONTROL REGISTER 2 AS SIGNALS ESR H AND WREN W RESPECTIVELY. THE

2981

: THE TEST WI'L SELECT AND INITIALIZE THE MEMORY SIMULATOR.

2984
2985
2986
2987

:
:
2
:

2990
2991
2992
2993
2994
2995
2996
2997
2998
2999

: THE TEST WILL THEN SET 1HE SIGNAL MSEL1 W TO A ONE IN CONTROL REGISTER 2
s ALONG WITH THE BITS MSAD17 H AND MSAD 16 H. THE TWO ADDRESS BITS MSAD17
: AND MSAD16 WILL BE SET TO A ONE OR O DEPENDING UPON THE ADDRESS TO BE
; TESTED. THE TEST WILL THEN READ CONTROL REGISTER 2 AND CHECK THAT THE
: BITS WERE LOADED CORRECTLY. THE SIGNAL MSBRK W WILL BE CHECKED FOR A 0.
: THE SIGNAL MSBRK M IS READ BACK AS A RESULT OF MP H BEING SET AND THE
; SIGNAL RST H CLEARING THE RDV AND WRV FLIP-FLOPS. THE SIGNAL MSEL1 W
; BEING ASSERTED ON A READ OR WRITE TO CONTROL REGISTER 6 WILL CAUSE THE
: SIGNAL SMPM L TO BE ASSERTED WHICH ENABLES THE MAP PROTECT RAM TO BE
: WRITTEN OR READ.

22379

: SIGNAL MSBRK H IN CONTROL REGISTER 2 WILL BE CHECKED FOR A 0.

2233%

; SECTION WILL BE REPEATED FOR EACH ADDRESS OF THE 1K BY & MAP PROTECT RAM.

22389

3001
3002
3003

THE FOLLOWING

THE TEST WILL SET THE SIGNALS RST H AND MP W IN CONTROL REGISTER 0. THE
THE TEST WILL THCN READ REGISTER O AND CHECK THAT SIGNALS CTS H, 8 BIT H,
RDV H AND WRV H ARE O AND THAT RST H AND MP H ARE A ONE. THE TEST WILL
THEN CLEAR THE SIGNA. RST H AND CHECK THAT RST H WAS THE ONLY BIT THAT

: CHANGED IN CONTROL RESISTER 0.

: THE TEST WILL NOW SELECT THE REMAINING PART OF THE 18 BIT MEMORY
; SIMULATOR ADDRESS BY LOADING THE ADDRESS INTO CONTROL REGISTER & BITS
: 15-8, AND CHECKING THAT THE ADDRESSS LOADED CORRECTLY BY READING BACK

36”8?

: REGISTER 2.

3006
3007
3008
3009
3010

: THE TEST WILL THEN WRITE THE LOCATION SELECTED WITH ONES IN BITS MPIN W
s AND RDE H AND 2EROES IN BITS WRE W AND MUTB H. THIS IS DONE VIA WRITING
: TO CONTROL REGISTER 6 WHICH WILL ASSERT THE SIGNAL SMPM L. THE SIGNAL
: SMPM L ENABLES THE MAP PROTECT RAM TO BE WRITTEN OR READ. THE PROGRAM
; WILL READ BACK THE BITS LOADED BY READING BACK CONTROL REGISTER 6. THE

3013
3014

: THE TEST WILL THEN READ CONTROL REGISTER 2 AND CHECK THAT BIT ESR H
s IS SET TO A ONE AND THAT BIT WREN H IS SET TO A 0. THESE BITS ARE

3017
3018

: THE TEST WILL THEN WRITE ONES IN BITS WRE H AND MUTB W, AND ZEROES INTO
: BITS MPIN H AND RDE H. THE TEST WILL THEN READ AND COMPARE THE LOCATION

3021

: THE TEST WILL THEN READ CONTROL REGISTER 2 AND CHECK THAT THE BIT WREN W

3385?

: THE TEST WILL THEN BE REPEATED UNTIL ALL ADDRESSES WAVE BEEN VERIFIED.

338}5

338}‘5,

33853
3333%

5827 007366

: LOCATION WILL BE COMPARED FOR CORRECT DATA.

; ENASLED BY THE SIGNAL MP H.

: FOR THE CORRECT CONTENTS.

s IS SET TO A ONE AND BIT ESR H IS SET TO A 0.

’

BGNTST

SEQ 0060

————

HARDWARE TESTS

007366

g
00

004737
005001

007374

005002

007376
007376

106404

TEST 1

Te::

004550

JSR

PC,INITHS

CLR

1$:

:02 PAGE 61
: CHECK 1K BY & MAP PROTECT RAM (1°'S + 0°'S, AND 0°'S + 1°S).

BGNSEG

TRAP

sSELECT AND INIT MEMORY SIMULATOR

:CLEAR BITS 15-8 MSAD ADDRESS COUNTER
:CLEAR BITS 17-16 MSAD ADDRESS COUNTER

($BSEG

sSET SIGNALS RST H AND MP
H IN CONTROL REGISTER 0.

:THESE BITS WILL NOT BE CHECKED UNTIL THE RAM LOCAT
sWRITTEN AND TESTED.
052737
042737

000005
000060
005346

sRST W WILL PRESET THE RDV AND WRV FLIP-FLOPS.
THE S
:WILL ALLOW THE MAP PROTECTION RAM BITS MPIN H AND WR
READ INTO CONTROL REGISTER 2 AS ESR H AND WREN H R

Ne—
—¢
<
TMm
F

17=JUN-82

-~
e

CVCDAB.P11

MACY1 30“;252)
17=JunN-82
1

WARDWARE TESTS

8IS

#RSTH!MPH
,ROL OAD

sSETUP TO SET RST H AND MP W

JSR

PC.LDRDRO

;6O LOAD READ AND CHECK REG 0

,ROEROR

*REGISTER 0 NOT EQULA EXPECTED

8IC

BEQ

ERRDF

TRAP

.WORD

.WORD
.WORD

CKLOOP
TRAP

#RDVH ! WRVH , ROM: SK

cienor

;SETUP TO CHECK RDV AND WRV FOR A 0

:IF OK_THEN GO CLEAR SIGNAL RST M

o
ROEROR
CSCLP1

——

8 =33 EEELLLLEESE
ANAN=S g EERERERRE

;CLEAR BIT RST H IN CONTORL REGISTER 0. RDV AND WRV SHOULD NOT
s CHANGE DURING THIS TEST.

000001
005346

002252

2%:

8IC

#RSTH,ROLOAD

sSETUP TO CLEAR BIT RST H

JSR

PC.LDRDRO

:GO LOAD, READ AND CHECK REG 0

TRAP

cieaor

*REGISTER 0 NOT EQUAL EXPECTED

BEQ

ERRDF
.WORD

-WORD
-WORD
CKLOOP
TRAP

LROEROR

:IF OK_THEN CONTINUE

o
ROEROR
CSCLPY

sSET SIGNAL MSEL1
H TO A 1 AND MSAD BITS 17 OR 16 TOA 1 OR 0 IN
sCONTROL REGISTER 2

000010
002264
177540
005414

002264

002270

3%:

MOV
BIS

#MSEL1,R2LOAD
R2,R2LOAD

;SETUP TO SET MSEL1 BIT TO A 1
:SETUP MSAD BITS 17 AND 16

PC,LDRDR2

;GO LOAD, READ AND COMPARE REG 2

ciinor

*REGISTER 2 FAILED TO LOAD CORRECTLY

MOV

#177540,R2MASK

BEQ

JSR

TRAP

ERRDF

LR2EROR

WORD
JWORD
.WORD

2
0
R2EROR

TRAP

cscLP1

CKLOOP

;SETUP TO IGNORE REG 2 BITS 15-8 6-5

:IF _LOADED OK THEN CONTINUE

SEQ 0061

HARDWARE TESTS

MACY11

17=JUN-82 12:02 PAGE 62
TEST 12: CHECK 1K BY & MAP PROTECT RAM (1°'S + 0°S, AND 0°'S + 1'S).

30A(1052)

17-JUN-82 1 11:26

;LOAD MSAD BITS 15-8 INTO CONTROL REGISTER &
A ¥

;SETUP BITS TO LOAD

BEQ
ERRDF

5$
3, ,R4EROR

:1F REGISTER 4 CORRECT THEN CONT
*REGISTER 4 NOT EQUAL EXPECTED

PC . LDRDRS

gienor

:GO LOAD, READ AND COMPARE REG &

O
R4EROR
CSCLP1

sSET BITS MPIN H AND RDE H TO A 1 - SET BITS WRE H AND MUTB H TO A 0.

sTHESE BITS ARE SET IN LOCATION ADDRESSED BY CONTROL REGISTER 2 AND &.

.;*E‘Elg{g#klé SMPM L WILL BE ASSERTED ON A WRITE OR READ OF CONTROL

177760

002306

000005
005506

002302

5$:

b
D
b
o) =D
b e
d
b

;SETUP REG 6 MASK WORD

BEQ

*IF DATA OK THEN CONTINUE

TRAP

CSERDF

000140 002270

000040 002266
005430 _

#MPINH'RDEH,R6LOAD
PC,LDRDR6
& ,MSGMP,ALINFO

;G0 LOAD, READ AND COMPARE REGISTER 6
:MAP PROTECTION RAM DATA ERROR

&
MSGMP
ALINFO
CSCLP1

sSETUP TO READ REGISTER 2 WITH REGISTER O BIT MP H SET TO A 1 TO
sALLOW MPIN H AND WRE H TO BE READ AS BITS ESR H AND WREN H

/‘

6$:

#177760,R6MASK

MOV
JSR

WORD
"WORD
"WORD
CKLOOP
TRAP

BIC
8IS
JSR
BEQ

ERRDF

#ESRH ! WRENH, R2MASK
#ESRH,R2GO0D
PC ,READR2
78
2,MSGMPL ,ALR2IN

.WORD
"WORD

MSGMPL

CKLOOP
TRAP

CSCLP1

D e

TRAP

.WORD

CSERDF

:SETUP TO CHECK ESR H AND WREN W
:SETUP EXPECTED BIT TO BE SET (MPIN W)
:GO READ AND CHECK REGISTER 2
2IF BIT ESR H SET THEN CONTINUE
*REG 2 NOT EQUAL EXPECTED

ALR2IN

sWRITE THE SAME LOCATION WITH WRE H AND MUTB H SET TO A 1 AND
sMPIN H AND RED H SSET TO A O

D e

W
v

p=4
o

b md =
ey
b e
2

MOV

ERRDF

D e o ed e

SEYRNRUKLEERNRRRUN
NS sa I nr 2o 38 IRFRAR2S

R1,R4LOAD

JSR

.WORD
WORD
.WORD
CKLOOP
TRAP

LN WA N N N N NN N N N N W W W W W N NN N WIN N N W W W W W WL (NN
WIW W W N

MOV

TRAP

EFE R

~NO W

| CVCDAB.P11

002302

7%:

MOV
JSR

#WREH ' MUTBH, R6LOAD
PC,LDRDR6

BEQ
ERRDF

8s
&, MSGMP,AL INFO

WORD
.WORD

&
MSGMP

TRAP

CS$ERDF

sSET WRE H AND MUTB H TO A 1
:GO LOAD,READ AND COMPARE REG 6

*IF OK THEN CONTINUE
:DATA ERROR MAP PROTECTION RAM

SEQ 0062

[ HARDW

TESTS MACYN 30A(1052)

- CVCDAB.P11

17-JUN-82 11:26

140 - 007660

3142 £07662

17=JuN-82
1
TEST 1

004052

:02
:

PAGE 63

CHECK 1K fiY & MAP PROTECT RAM (1°S + 0°'S, AND 0°'S + 1°'S).

.WORD
CKLOU#
TRAP

104406

L INFO
cscLP

sSETUP TO CHECK THAT MAP PROTECTION BIT WRE W WILL SET THE SIGNAL

042737

000160

00
5566

8s:

007664

-a-o-a_._._..a...d_h-a_a—..‘—o-l-.-n—.-n-b:
o
oo
VTV
AW S O

awgazwg-SOONO\nwa-flocafl

WWWWWW

:WREN W IN CONTROL REGISTER 2 WHEN MP W BIT IS SET.

9%:

100008
:

007720

062701

000400

007726
007732

062702
032702

000001
000004

8IC
8IS
JSR

#ESRH
! WRENH,R2G00D
#WRENH ,R2GO0D
;&.READI

ERRDF

2 MSGMPL ,ALR2IN

.WORD
+WORD
.WORD
ENDSEG

2
MSGMPL
ALR2IN

TRAP

CSESEG

ADD

#MSADS ,R1

ADD

#MSAD16,R2

BEQ
ENDTST

BNE

BIT
L10041:

TRAP

[ SERDF

#MSELO, R2
CSETST

sCLEAR BOTH EXPECTED BITS

sSETUP TO EXPECT WREN H BIT TO BE SET
;GO READ AND CHECK REGISTER 2
:IF OK THEN CONTINUE
:REGISTER 2 NOT EQUAL EXPECTED

sUPDATE MSAD BITS 15-8 BY 1
s1IF NOT O THEN DO NEXT ADDRESS
sUPDATE MSAD BITS 16 AND 17
sCHECK IF DONE
sIF NOT DO NEXT RANGE OF ADDRESSES

SEQ 0063

HARDWARE TESTS

CVCDAB.P11

MACYN 30?(}252)

17-JUN<-82 1

17=JUN=-82

12:02

PAGE 64

TEST 13: CHECK 1K BY 4 MAP PROTECT RAM FOR ADDRESS SHORTS.

}93

.SBTTL TEST 13: CHECK 1K BY & MAP PROTECT RAM FOR ADDRESS SHORTS.

3In
3172

144
: TEST TO CHECK THE 1K BY 4 MAP PROTECTION RAM FOR ADDRESS SHORTS.

3173

: LOCATION IN THE MAP PROTECTION RAM.

3175
3176
3177

: ADDRESS OF THE MAP PROTECTION RAM.

3180
3181
318%
3183
3184
3185
3186
3187
3188
3189
3190
3191

007742
007742
007742
007746
007746
007746
007750
007752
007754
007754

3194
3195

007756
007764

012737
050237

000010
002264

3197
3198
3199

007776
010002
010004

004737
001405

005414

3201
3202
3203
3204
%582

010006
010010
010012
010014
010014

004737

T13::

004550

T13.1:

104402
005001
005002

18:

104404

g}gg

BGNTST
JSR
BGNSUB

PC.INITMS

:SELECT AND INIT THE MEMORY SIMULATOR

TRAP
($BSUB
CLR
R1
;CLEAR MSAD ADDRESS BITS 15-0
CLR
R2
*CLEAR MSAD ADDRESS BITS 17-16
BGNSEG
TRAP
C$BSEG
;SET SIGNAL MSEL1 H TO A 1 AND MSAD BITS 17 AND/OR 16 TO A 1 OR 0 IN

:CONTROL REGISTER 2

007770

010004

012737

177740

002264

002270

MOV
BIS

#MSEL1,R2LOAD
R2,R2LOAD

;SETUP TO SET MSEL1 BIT TO A 1
*ADD STATE OF MSAD BITS 17 AND 16

JSR
BEQ
ERRDF

PC,LDRDR2
28
2, ,R2EROR

:G0 LOAD, READ AND COMPARE REG 2
*IF OK THEN CONT
*REG 2 FAILED TO LOAD CORRECTLY

MOV

104455

TRAP

000002
000000
003712

.WORD
WORD
.WORD
CKLOOP
TRAP

104406

g%g;

#177740,R2MASK
CSERDF

:SETUP TO IGNORE REG 2 BITS 15-5

O
R2EROR
CSCLPI

;LOAD MSAD BITS 15-8 INTO CONTROL REGISTER 2

3209
3210
3211
3212

010016
010022
010026
010030

010137
004737
001405

3214
3215
3216
3217
gg}g

010032
010034
010036
010040
010040

000003
000000
004000

3213

THE TEST WILL FILL THE MAP PROTECTION

: RAM WITH ALL ZEROES. THE TEST WILL THEN RESET THE ADDRESS POINTER TO THE
: FIRST ADDRESS, CHECK THE LOCATION TO BE ZERO, WRITE ONES INTO THE LOCATION,
: AND THEN READ AND CHECK THE LOCATION FOR ONES.
THIS TEST IS REPEATED FOR EACH

g};g

3200

THIS TEST

; WILL CHECK THAT WRITING A LOCATION DOES NOT EFFECT THE CONTENTS OF ANOTHER

174

3196

SEQ 0064

010030

002276
005462

28:

104455

104406

MOV
JSR
BEQ
ERRDF

R1,R4LOAD
PC . LDRDR4
3$
3, ,R4EROR

.WORD
WORD
-WORD
CKLOOP
TRAP

3
O
R4EROR

TRAP

CSERDF

;SETUP ADDRESS BITS TO LGAD
:G0 LOAD, READ AND COMPARE REG 4
:1F LOADED OK THEN CONT
*REGISTER 4 FAILED TO LOAD CORRECTLY

CSCLP1

3220

;SET BITS MUTB H, MPIN H, WRE H,

AND RDE H TO A 0 IN LOCATION

§S§§
32264 010042 012737 177760 002306 3$:

MoV

sSETUP REGISTER 6 MASK WORD

3221

;ADDRESSED BY CONTROL REGISTER 2 AND 4.

THE SIGNAL SMPM L WILL BE

*ASSERTED ON A WRITE AND READ TO CONTROL REGISTER 6.
#177760,R6MASK

HARDWARE TESTS

MACY11 30?(5252)

CVCDAB.P11

17=JUN=82 1

S
6

005037
004737

010050
010056

010060

01%8

3230
3231
323;
3233
323,
3235

010064
010066
010070
010072
010072
010072

3237

010100

001404

3229 01

3236

48:
100008:

3238 010102
gzso 010106

062702
032702

000001
000004

3254
3255
3256

010124
010124

CLR
JSR

000004
002356
004052

000400

001325

001720

TEST 13: CHECK 1K BY & MAP PROTECT RAM FOR ADDRESS SHORTS.

104455

104405

PAGE 65

TRAP

CSERDF

MORD
.WORD
.WORD
ENDSEG
TRAP

L10043:

113.2:

104402
005001
005002

gg_gg

&4 ,MSGMP,AL INFO

‘

18:

104404

CSESEG

#MSADS ,R1

;UPDATE MSAD BITS 15-8 TO NEXT ADDRESS

ADD
BIT

#MSAD16,R2
#MSELO,R2

:UPDATE ADDRESS BITS 16 AND 17
:CHECK IF ALL ADDRESSES DONE

TRAP

C$ESUB

BEQ
ENDSUB

BGNSUB

1$
1$

:IF NOT DO NEXT ADDRESS RANGE

TRAP
($BSUB
CLR
R1
;RESET THE ADDRESS POINTERS
CLR
R2
:
sTHE FOLLOWING PORTION OF THE TEST WILL CHECK FOR ADDRESS SHORTS
:IN THE MAP PROTECTION RAM BY READING THE LOCATION FOR 0'S, WHICH
sWERE PREVIOUSLY WRITTEN IN ABOVE SUBTST, AND THEN WRITING AND

BGNSEG
TRAP
($BSEG
;SET SIGNAL MSEL1 H TO A ONE AND MSAD BITS 17 OR 16 TO A 1 OR 0 IN

002264

MOV

#MSEL1,R2LOAD

3261

002270

MOV

0177760.R2HASK

010134

050237

002264

3262
3263
3264
3265
3266
3267
3268
3269
gg;?

010146
010152
010154
010154
010156
010160
010162
010164
010164

004737
001405

005414

010140

012737

177740

8IS

JSR
BEQ
ERRDF
TRAP
WORD
WORD
-WORD
CKLOOP
PP

104455
000002
000000
003712
104406

g%;%

3278

:IF NOT O THEN CONTINUE

JCONTROL REGISTER 2

3260

3279
3280

*MAP PROTECTION RAM DATA ERROR

&
MSGMP
ALINFO

3259 010126 012737 000010

3275
3276
3277

*IF ALL 0'S THEN CONTINUE

:CHECKING THE LOCATION FOR ONES.

ggg;

3274

;SET WORD TO LOAD TO 0
:GO LOAD, READ AND COMPARE REG 6

ADD

BNE

104403

R6LOAD
PC,LDRDR6

BEQ

ERRDF

062701

010112
010114
010114
070114
010116
010116
010116
010120
010122

12:02

002302
005506

010074

240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251

17-JUN-82

;SETUP TO SET MSEL1 H TO A 1

R2,R2LOAD

*SETUP BITS MSAD 17-16

PC,LDRDR2
28
2..R2EROR
CS$ERDF
2
0
R2EROR

;GO LOAD, READ AND COMPARE REG 2
*IF LOADED OK THEN CONTINUE
JREGISTER 2 FAILED TO LOAD CORRECTLY

JSETUP REGISTER 2 MASK WORD

CSCLPT

JLOAD MSAD BITS 15-8 INTO CONTROL REGISTER &

010166 010137 002276
010172
010176
010200

004737
001405

010202
010204

000003
000000

010200

104455

005462

28:

MOV

JSR
BEQ
ERRDF

TRAP

LWORD
WORD

R1,R4LOAD

PC.,.LDRDR4
3$
3, ,R4EROR

CS$ERDF

3
O

;SETUP ADDRESS BITS 15-8

;GO0 LOAD, READ AND COMPARE REGISTER &
:1F OK THEN CONTINUE
*REGISTER 4 NOT EQUAL EXPECTED

SEQ 0065

HARDWARE TESTS

CVCDAB.P11

MACY11

30A‘1052)

17-JUN-82
1 1:26

010206
010210
010210

17-JUN-82

0064000

:02

PAGE 66

: CHECK 1K BY & MAP PROTECT RAM FOR ADDRESS SHORTS.

.WORD
CKLOOP
TRAP

104406

R4EROR
CSCLPT

;SETUP TO READ MAP PROTECTION RAM FOR ZEROES WHICH WERE WRITTEN IN

:THE PREVIOUS SUBTST.

IF AN ERROR OCCURS, THEN WRITING A PREVIOUS

sINTERNAL TO RAM CHIP.

THE SIGNAL SMPM L WILL BE ASSFRTED DURING

:LOCATION CHANGED THE LOCATION BEING READ. THIS ERROR IS PROBABLY

177760

OO0O0O0O0O0O0OOOOO0O

:A READ OF REGISTER 6

d o

002302
002304
005522

cd o

o
N

3%:

MOV
CLR
CLR

#177760,R6MASK
R6LOAD
R6GOOD

BEQ
ERRDF

48
& ,MSGMPS,AL INFO

MORD
.WORD
.WORD
ENDSEG

&
MSGMPS
ALINFO

TRAP

CSESEG

BGNSEG
TRAP

(S$BSEG

JSR

TRAP

o
—d

OO0
WINWWWWNWN
W WNNW
'NNWWWWWWWWN

002306

104404

PC ,READRG

CSERDF

;SETUP REG 6 MASK WORD
:SETUP DATA PATTERN THAT WAS LOADED
:SETUP EXPECTED DATA PATTERN

:GO READ REG 6 AND CHECK DATA FOR 0'S

:IF ALL ZEROES THEN CONTINUE
:ADDRESS SHORT IN MAP PROTECTION RAM

sTHE FOLLWOING SECTION OF CODE WILL WRITE THE LOCATION JUST READ WITH

ONES AND THEN READ AND CHECK THE LOCATION FOR ONFS.
IF THERF |S
AN INTERNAL ADDRESS SHORT IN THE RAM THIS WILL CAUSE ANOTHER LOCATION
:TO BE WRITTEN AT THE SAME TIME.

010252

012737

000017

177760
005506

MoV

#MUTBH !MPINH!WREH!RDEH,R6LOAD ;SET Ab&RBlTS TO ONES

JSR

PC.,LDRDR6

MOV

BEQ

000001
000004

:IF ALL ONES THEN CONT

4 nscnr ALINFO

.WORD
-WORD
.WORD
ENDSEG

nscnp
ALINFO

TRAP

CSESEG

:GO LOAD, READ AND COMPARE REG 6

:DATA ERROR IN MAP PROTECTION RAM

ADD
BNE
ADD

#MSADS ,R1
1%
#MSAD16,R2

;UPDATE MSAD ADDRESS 15-8
*1F NOT O THEN DO NEXT ADDRESS
*UPDATE ADDRESS BITS 17-16

BEQ
ENDSUB

SIF DOT DO NEXT MIGHER RANGE

BIT

#MSELO, R2

TRAP

CSESUB

TRAP

CSETST

ENDTST
104401

;SETUP MASK

ERRDF

TRAP

000400

#177760,R6MASK

:CHECK IF DONE

SEQ 0066

HARDWARE TESTS

CVCDAB.P11

NN NN N W N N NN

3
3381
338%
3383
3384
3385
3386
3387
3388
3389
3390

SEQ 0067

TEST TO CHECK THAT THE WRV FLIP-FLOP CAN BE SET VIA THE SIGNALS WRE H AND (K H.
THE TEST WILL CHECK THAT THE WRV FLIP-FLOP, ONCE SET, CAN NOT BE CLOCKED TO A

ZERO BY CHANGING THE STATE OF WRE W AND (LOCKING T HE SIGNAL CK H AGAIN.

THE

TEST WILL CHECK THAT THE WRV FLIP-FLOP CAN BE CLEARED WHEN THE SIGNAL RST M

IS PULSED.
THE TEST WILL ALSO CHECK TMAT THE SI GNAL MSBRK H CAN BE SET TO A
ONE AND ZERO AS A RESULT OF THE WRY FLIP-FLOP BE ING SET AND CLEARED.

010332
010332
010332
010336
010336

004737

010340
010344

105037
052737

010360
010364

004737
001405

T14::

004550

104404

BGNTST

JSR
BGNSEG
TRAP

PC,INITMS

CLR8
BIS
BIC
JSR
BEQ
ERRDF

ROLOAD
#RSTH'MPH, ROL OAD
#WRVH | RDVH, ROMASK
PC,LDRDRO
1$
1, ,ROEROR

WORD
WORD
.WORD
CKLOOP
TRAP

1
O
ROEROR

sSELECT AND INIT THE MEMORY SIMULATOR

($BSEG

sSET SIGNALS RST H AND MP H IN CONTROL REGISTER O.
THE SIGNAL RST M
sWILL PRESET THE RDV AND WRV FLIP-FLOP'S TO A 1. THE SIGNAL MP W
sWILL ALLOW THE MAP PROTECTION RAM BITS MPIN H AND WRE H TO BE READ
sINTO CONTROL REGISTER 2 ALONG WITH THE SIGNAL BRK L.
THE SIGNALS
:MPIN "f WRE H, AND BRK L WILL BE READ AS ESR H, WREN H AND MSBRK W
:IN CONTROL REGISTER 2.

002252
000005
000060
005346

002252
002256

TRAP

g
%

goiuianay
30 NOWSWN—-=OV 333 S

3352
3353
3354
3355
3356
3357
3358
3%23
3
3361
3362

17=JUN=-82 12:02 PAGE 67
TEST 14: CHECK WRV F/F TO SET (0) ¢ CLEAR (1) VIA WRE H,CK H ¢ RST H

3350
3351

_30A(1052)

17=JUN-82 11:26

+SBTTL TEST 14: CHECK WRV F/F TO SET (0) + CLEAR (1) VIA WRE H,CK H ¢ RST H

o Vi

WW W

%335
336
3337
3%38
3339
3340
3341
334
334
34
34
346
3347
3348
3349

MACY11

CS$ERDF

;CLEAR LOWER BYTE OF REG 0 FOR LOOPING
SSETUP TO SET RST H AND MP H
:SETUP TO CHECK WRV AND RDV F/F
:GO LOAD, READ AND CHECK REG 0
:IF OK THEN CONTINUE
*REGISTER O NOT EQUAL EXPECTED

CSCLPI

sCLEAR SIGNAL RST H IN CONTROL REGISTER O, RDV AND WRV BITS SHOULD NOT
sCHANGE STATE IN CONTROL REGISTER 0.
010400
010406
010412
010414
010414
010416
010450
010422
010424
010424

042737
004737
001405

000001
005346

002252

1%:

BIC
JSR
BEQ
ERRDF

#RSTH,ROLOAD
PC,LDRDRO
28
1, ,ROEROR

LWORD
WORD
.WORD

1
O
ROEROR

TRAP

104455
1

003624

CKLOOP
TRAP

104406

C$ERDF

;SETUP TO CLEAR RST W IN REG 0
:G0 LOAD, READ AND CHECK REG 0
*IF EQUAL THEN CONTINUE
*REGISTER NOT EQUAL EXPECTED

CSCLPY

sSET SIGNAL MSEL1 H TO A ONE AND MSAD BITS 17 AND 16 TO A 0. THE
sSIGNAL MSBRK H SHOULD BE A 0 DURING THIS TEST
010426
01
010442

012737
012737
004737

000010
177540
005414

002264
002270

28%:

MOV

MOV
JSR

#MSEL1,R2LOAD

sSETUP TO SET MSEL1 H TO A 1

PC.LDRDR2

;GO LOAD, READ AND CHECK REG 2

#177540 ,R2MASK

sSETUP TO READ MSBRK H AND LOWER 5 BITS

b e

ood

d —D

HARDWARE TESTS MACY11 30A (1052)
17-JUN-82 11:26
CVCDAB.P11

17=JUN=B2
12:02 PAGE 68
TEST 14: CHECK WRV F/F TO SET (0) + CLEAR (1) VIA WRE H.CK H + RST W

001405

BEQ
ERRDF

3s
2, ,R2EROR

JWORD
JWORD
.WORD

TRAP

104455

000002
000000
003712

CKLOOP
TRAP

104406

CSERDF

;1F OK THEN CONTINUE
*REG 2 NOT EQUAL EXPECTED

R2EROR
CSCLPY

:LOAD MSAD BIT 15 THROUGH 8 TO A 0 TO SELECT ADDRESS 0
002276
005462

3s:

TRAP

CSERDF

.WORD
WORD
.WORD

D e

CKLOOP
TRAP

48
3, ,R4ERCR

;SETUP TO SET ALL BITS TO 0
+GO LOAD,READ AND CHECK REG &
:IF NO ERRORS THEN CONTINUE

*REGISTER 4 NOT ALL ZEROES

3
0
R4EROR
CSCLP1

sSET BITS MPIN H, RDE H AND MUTB H TO A ONE AND BIT WRE H TO A 0.
sWRE H ON A 0 WILL SET THE WRV FLIP-FLOP WHEN BIT CK H IS TOGGLED
:IN CONTROL REGISTER 0.

000015
177760
005506

—

FEREEE

R4LOAD
PC,LDRDRG

BEQ
ERRDF

3407

PR IIIIIIIIIIIIIIIIIIIIIISII
IS'S
SURVERRUKZEERVRXRRENY
NNNNNNNNNg VWO NV WN=O 3

CLR
JSR

002302
002306

4$:

MoV
MOV
JSR
BEQ
ERRDF
TRAP

#MPINH!RDEH!MUTBH,R6LOAD ;SETUP TO LOAD THE MAP PROTECT RAM

#177760, R6MASK

:SETUP REGISTER 6 MASK WORD

:OF COMPARED OK THEN CONTINUE

PC.,LDRDR6

& ,MSGMP
AL INFO

Eieaor

:GO LOAD,READ AND CHECK REGISTER 6

*MAP PROTECT RAM DATA ERROR

MSGMP
ALINFO

010540

CSCLPY

sCHECK CONTROL REGISTER O TO MAKE SURE THAT NO CHANGES OCCURED.
010542

005362

5%:

JSR
BEQ
ERRDF
TRAP

PC,READRO

;READ AND CHECK REGISTER 0

1,MSGMPL
, ALROIN

*REGISTER 0 CHANGED STATES

gieaor

:IF OK THEN CONTINUE

MSGMPL

CKLOOP
TRAP

ALROIN
CSCLPY

sSETUP TO READ CONTROL REGISTER 2 WITH MP H SET TO A 1 IN CONTROL
sREGISTER O TO ALLOW MPIN H, WRE H AND BRK L TO BE READ INTO

:CONTROL REGISTER 2 AS BITS ESR W, WREN W, AND MSBRK H.

042737
052737

000140
000040

BIC
BIS

#ESRH!WRENH
, R2ZMASK
#ESRH,R2GOOD

sCLEAR BITS TO BE CHECKED
sSETUP EXPECTED MAP PROTECT BIT

SEQ 0068

HARDWARE TESTS

CVCDAB.P11

MACY11

30A(1052)

005430

17=JUN-82 11:26

47
48
49

010573
010602
010604

004737
001405

3451
y.sg
3453
3456
figz

010606
010610
010612
010614
010614

ooooog
00246
004126

3,50

010604

17-JUN-82

104455

3465

3466
3467
34,68
3469
332;?

104406

010616

010624
010632
010636
010640

010640

010642
010644
010646
010650
010650

052737

052737
004737
001405

000140

000100
005354

002254

002252

7$:

104455

000001
00 463
004100

3477

010672

001405

010660
010666
010674

042737
004737

000100

000100
005354

002254

002252

8$:

34,80

010676

000001

34,82
34,83
s"ig‘s'

010702
010704
010704

004100

TRAP

CSERDF

#CKH . ROLOAD
PC,LDRDOR
8s
1,MSGMPL ,ALROIN

:SETUP EXPECTED DATA

:SETUP BIT TO BE LOADED
:GO LOAD, READ AND CHECK REG 0
*IF OK THEN CONTINUE
:WRV F/F PROBABLY NOT SET (0)

1
MSGMPL
ALROIN
CS$CLP1

BIC

#CKH,ROGOOD

;CLEAR CKH IN EXPECTED BITS

BEQ

*IF OK THEN CONTINUE

BIC
JSR

.WORD

010700 002463

-WORD

.WORD
CKLOOP
TRAP

104406

#CKH.ROLOAD
PC,LDRPOR

nscm.mom

:SETUP TO CLEAR BIT CK W IN REG 0
:G0 CLEAR, LOAD AND CHECK REG O
*REG 0 NOT EQUAL EXPECTED

nscm

ALROIN
CSCLP1

;CHECK THAT SIGNAL MSBRK W IS SET TO A 1 IN CONTROL REGISTER 2

3,88 010706

052737 000240

3490

001405

34,89

010714

3491

010722

501
502

THE WRV F/F SHOULD BE SET (0) AND THE RDV F/F SHOULD BE CLEARED (1).

#CKH!WRVH,ROGOOD

TRAP

33'2%9

3499
3500

CSCLP1

8IS

8IS
JSR
BEQ
ERRDF

ERRDF

3479 010674 104455

3493
3496
3495
3496
3323;

CSERDF

;GO READ REGISTER 2 AND CHECK IT
:IF OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

;CLEAR THE SIGNAL CK H IN CONTROL REGISTER 0. NO OTHER BITS SHOULD CHANGE.

042737

3492

2
MSGMPL
ALR2IN

LWORD
.WORD
.WORD
CKLOOP
TRAP

104406

010652

3481

WORD
.WORD
.WORD
CKLOOP
TRAP
:F/F'S.

3474

34,78

PC,READR2
78
2,MSGMPL ,ALR2IN

SEQ 0069

;SET SIGNAL CK H IN CONTROL REGISTER 0 TO CLOCK THE WRV AND RDV

332;%
3475
3476

JSR
BEQ
ERRDF

TRAP

agg

3461
345;
3463
3464

PAGE 69

TEST 14: CHECK WRV F/F TO SET (0) + CLEAR (1) VIA WRE H,CK H + RST H

3457

3460

12:02

010720
010722

010724
010726
010730
010732
010732

004737

104455

ooooog
00246
004126
104406

005430

002266

9%:

BIS

JSR

#MSBRKH ' ESRH,R2G0OD

;SETUP EXPECTED BITS IN REGISTER 2

PC,READR2

:GO READ REGISTER 2 AND CHECK IT

ERRDF

2,MSGMPL,ALR2IN

:MSBRK H PROBABLY NOT SET VIA BRK L BEING LOW

WORD
-WORD
.WORD
CKLOOP
TRAP

2
MSGMPL
ALR2IN

BEQ

TRAP

10§

CSERDF

*IF OK THEN CONTINUE

CSCLP1

;THE FOLLOWING SECTION WILL CHECK THAT THE WRV FLIP=FLOP CAN NOT
:BE CLEARED (1) BY TRYING TO CLOCK A ONE INTO IT. ONCE THE WRV FLIP=

:FLOP IS SET (0), IT IS LATCHED TO THAT STATE UNTIL A PULSE IS ISSUED
:ON THE SIGNALS RST M OR INIT H.

HARDWARE TESTS

CVCDAB.P11

3503
S04
505

010736
010742

3507

010750

506

3508

3509
3510
3511
3512
%533

010746

010750

010752
010754
010756
010760
010760

MACY11

30A(1252)

012737
004737

000017
005506

17=JUN=-82 11:2

001405

17=JUN=-82

3518

3519

3520

3521
3522
3523
3524
gggg

002302

108:

010762

010766
010770

010770

010772
010774
010776
011000
011000

ERRDF

& ,MSGMP,AL INFO

104455

WORD
.WORD
.WORD
CKLOOP
TRAP

&
MSGMP
ALINFO

TRAP

000004
002356
004052

104406

11§

CS$ERDF

*IF ALL ONES THEN CONTINUE

*MAP PROTECT RAM DATA ERROR

CSCLP1

004737

001405

005362

118:

JSR

BEQ

ERRDF

104455

TRAP

000001
002463
004100

JWORD
.WORD
.WORD
CKLOOP
TRAP

104406

PC ,READRO

12$

1,MSGMPL ,ALROIN

CSERDF

:GO READ AND CHECK REGISTER 0

*IF NO CHANGES THEN CONTINUE
*REGISTER O CHANGED STATE

1
MSGMPL
ALROIN
CSCLPY

sCHECK CONTROL REGISTER 2 TO HAVE ESR M, WREN H AND MSBRK H SET TO 1
011002
011010

353§

011016

353,
3535
3536
3537
%ggg

#MPINH'WREH
'RDEH !'MUTBH,R6LOAD ;SETUP TO SET ALL RAM BITS TO 1
PC,LDRDRG
:GO LOAD, READ AND CHECK RAM

011014

011016

011020
011022
011024
011026
011026

052737
004737

001405

000340
005430

002266

12%:

BIS
JSR

#ESRH'WRENH 'MSBRKH,R2GOOD :ADD WREN M TO EXPECTED DATA
PC ,READR2
;GO READ AND CHECK REGISTER 2

ERRDF

2,MSGMPL ,ALR2IN

BEQ

104455

TRAP

000002
002463
004126

.WORD
"WORD
.WORD
CKLOOP
TRAP

104406

13§

CSERDF

:IF NO ERRORS THEN CONTINUE

*REGISTER 2 NOT EQUAL EXPECTED

MSGMPL
ALR2IN
cs$cLP

3540
3541

sSET THE SIGNAL CK H TO THE HIGH STATE TO CLOCK THE WRV AND RDV FLIP=;FLOPS.
THE WRV FLIP-FLOP SHOULD REMAIN SET (0) AS A RESULT OF IT BEING

igz‘

;UNLESS IT WAS BEEN PRESET BY A PULSE ON THE SIGNALS RST M OR INIT M.

354

sSET ALREADY.

3545

011030

052737

000100

3547
3548

011044
011050

004737
001405

005354

3546

011036

3549

01105

3551
3ss§
3553
3554
gggz

011054
011056
011060
011065
011062

3550

ggg;

SEQ 0070

;CHECK THAT CONTROL REGISTER O DID NOT CHANGE STATE.

3529
3530

3533

MOV
JSR

BEQ

!3'?'»%;

3531

PAGE 70

TEST 14: CHECK WRV F/F TO SET (0) ¢ CLEAR (1) VIA WRE H.CK H + RST W

gg}g
3517

12:02

011052

052737

104455

1
002463
004100
104406

000100

002252
002254

13%:

THE WRV FiI"=FLOP, ONCE SET, CAN NOT BE CLOCKED AGAIN

BIS

#CKH, ROLOAD

JSR
BEQ

PC,LDRDOR
14$

BIS

ERRDF

TRAP

LWORD
"WORD
.WORD
CKLOOP
TRAP

:SETUP TO SET SIGNAL CK H TO WIGM STATE

#CKH . ROGOOD

sEXPECT CK W TO BE SET IN CONTROL REG 0

1,MSGMPL ,ALROIN

*WRV F/F CLEARED (1) AFTER BEING LATCHED

CS$ERDF

:GO LOAD, READ AND CHECK CONTROL REG 0
*IF OK THEN CONTINUE

1
MSGMPL
ALROIN
CSCLPY

;READ CONTROL REG 2 TO CHECK THAT ESR H, WREN H AND MSBRK W ARE STILL SET (1).

HARDWARE TESTS

CVCDAB.P11

MACY11

30?(5252)

17-JUN~82 1

gsso

004737

005430

560

011064

011070

3561

011072

3563
3564
3565
566
;gg;

011074
011076
011100
011102
011102

3562

011072

001405

17-JUN-82

12:02

148:

104455

3576

011120

3578
3579
3580
3581
gg

011122
071126
011126
011130
011130

ooooog
00246
004126
104406

112737

004737

011116

001405

011120

104455

000005
005346

002252

158:

3588

011144

001405

011140

011146

011150
011152
011156
011156
011156

004737

000001

005346

002252

168:

2
MSGMPL
ALR2IN
CSCLP1

MOVB
JSR

#RSTH'MPH,ROLOAD
PC,LDRDRO

:GO LOAD, READ AND CHECK CONTROL RE(, 0

ERRDF

1,MSGMPL ,ALROIN

*WRV F/F PROBABLY NOT CLEARED BY RST H

168

CSERDF

;SET RST H AND CLEAR CK H

+IF LOADED OK THEN CONTINUE

1
MSGMPL
ALROIN
CS$CLP1

BIC

#RSTH,ROLOAD

BEQ

17§

JSR

ERRDF

104455

TRAP

000001
002463
004100

LWORD
-WORD
.WORD
CKLOOP
TRAP

104406

3597

;SETUP TO CLEAR RST HW

PC,LDRDRO

:GO LOAD, READ AND CHECK CONTROL REG 0

1,MSGMPL ,ALROIN

:CONTROL REG 0 NOT EQUAL EXPECTED

CSERDF

<IF LOADED OK THEN CONTINUE

1
MSGMPL
ALROIN
CSCLP1

;CHECK CONTROL REGISTER 2 TO MAKE SURE THAT THE SIGNAL MSBRK W WENT TO

ggg

:A ZERO AS A RESULT OF THE WRV AND RDV FLIP-FLOPS BEING PRESET BY RST H.

3600

011150

042737

3602

011172

001404

3606

WORD
.WORD
.WORD
CKLOOP
TRAP

CS$ERDF

*1F OK THEN CONTINUE

;CLEAR THE SIGNAL RST H IN CONTROL REGISTER 0

042737

3603

*REGISTER 2 NOT EQUAL EXPECTED

WORD
.WORD
.WORD
CKLOOP
TRAP

104406

011132

3601

2,MSGMPL ,ALR2IN

TRAP

000001
002463
004100

3586

3591
3592
3593
359,
gggg

ERRDF

BEQ

gggg

3590

;READ AND CHECK CONTROL REGISTER 2

15§

:SET IN ITS PRESET STATE (1).

011106
011112

3589

PC ,READR?

;CLEAR THE SIGNAL CK W AND SET THE SIGNAL RST W IN CONTROL REGISTER 0.
;SETTING THE SIGNAL RST H TO A ONE WILL CAUSE THE WRV FLIP-FLOP TO BE

3573
3576

3587

JSR

BEQ

TRAP

gg;;

3577

TEST 14: CHECK WRV F/F TO SET (0) ¢ CLEAR (1) VIA WRE H,CK H + RST H

3569
3570

3575

PAGE 71

011166

011174

0111764

004737

005430

002266

17$:

104455

3605
3606
3607
3608
3609
3610
3611

011176
011200
011202
011204
011204
011204
031206

ooooog
00246
004126

332}‘

011206

104401

mg 011206

000200

104405

BIC

#MSBRKH , R2GOOD

:CLEAR MSBRK H IN EXPECTED DATA

BEQ

18§

:IF MSBRK H EQUALS A O THEN CONTINUE

JSR

ERRDF

2 ,MSGMPL ,ALR2IN

WORD
.WORD
.WORD
ENDSEG

2
MSGMPL
ALR2IN

TRAP
ENDTST

CSESEG

TRAP

CSETST

TRAP

188:
100008:

L10045:

PC ,READR2

CSERDF

:READ AND CHECK CONTROL REGISTER 2

:CONTROL REGISTER 2 NOT EQUAL EXPECTED

SEQ 0071

‘ HARDWARE TESTS MCV“lz}??(;gsz) 17=JUN=-82 12:02 PAGE 72
| CVCDAB.P11

17-JUN-8

TEST 15: CHECK RDV F/F TO SET (0) + CLEAR (1) VIA RDE H, CK H + RST W

gg}g

.SBTTL

3617

TEST 15: CHECK RDV F/F TO SET (0) + CLEAR (1) VIA RDE W, CK H ¢ RST H

14e

3618
3619

; TEST TO CHECK THAT THE RDV FLIP-FLOP CAN BE SET VIA RDE W AND CK H. THE TEST
; WILL CHECK THAT THE RDV FLIP-FLOP, ONCE SET, CAN NOT BE CLOCKED TO A ZERO BY

3621

; CHECK THAT THE RDV FLIP-FLOP CAN BE CLEARED WHEN THE SIGNAL RST M IS PULSED.

3630

: CHANGING THE STATE OF RDE W AND CLOCKING THE SIGNAL CK M AGAIN.

362

: THE TEST WILL ALSO CHECK THAT THE SIGNAL MSBRK W CAN BE SET TO A ONE AND ZERO

3325‘

3625
3626
3627
3628
3629
3630

3631
3632
3633
3634
3635

: AS A RESULT OF THE RDV FLIP-FLOP BEING SET AND CLEARED.
011210
011210
011210
011214
011214

004737

T15::

004550

104404

011216

105037

002252

3641
36462
3643

011236
011242
011244

004737
001405

005346

3645
3646
3647
3648
332153

011246
011250
011252
011254
011254

000001
000000
003624

3639 011222 052737 000005
3640 011230 042737 000060
011244

CLRB

002252
002256

104455

104406

011256

042737

011272

104455

011264
011270
011272

004737
001405

003624

3663

011302

104406

011302

000001

005346

002252

1%:

PC.LDRDRO
18
1, ,ROEROR

:GO LOAD, READ AND CHECK REG 0
:IF OK THEN CONTINUE
*REGISTER 0 NOT EQUAL EXPECTED

TRAP

CSERDF

sSETUP TO SET RST H AND MP H
:SETUP TO CHECK WRV AND RDV F/F

1
O
ROEROR
CSCLPY

BIC

#RSTH,ROLOAD

TRAP

CSERDF

JSR
BEQ
ERRDF

PC,LDRDRO
2
1, ,ROEROR

WORD
JWORD
.WORD

1
0
ROEROR

TRAP

CSCLPY

CKLOOP

3665

sLETUP TO CLEAR RST H IN REG 0

:GO LOAD, READ AND CHECK REG 0
:IF EQUAL THEN CONTINUE
sREGISTER NOT EQUAL EXPECTED

;SET SIGNAL MSELT M TO A ONE AND MSAD BITS 17 AND 16 TO A 0. THE

3&“2‘7’

;SIGNAL MSBRK M SHOULD BE A 0 DURING THIS TEST

3668 011304
70

;CLEAR LOWER BYTE OF REG 0 FOR LOOPING

:CHANGE STATE IN CONTROL REGISTER 0.

011274
011276
011300

§2‘°

ROLOAD

;CLEAR SIGNAL RST W IN CONTROL REGISTER 0, RDV AND WRV BITS SHOULD NOT

3659
3660
3661

sso;

;SELECT AND INIT THE MEMORY SIMULATOR

(S$BSEG

#RSTH!MPH, ROLOAD
#WRVH ! RDVH, ROMASK

LWORD
LWORD
.WORD
CKLOOP
TRAP

33235

3658

PC,INITMS

BIS
BIC

JSR
BEQ
ERRDF

3651

3655
3656
3657

JSR
BGNSEG
TRAP

:IN CONTROL REGISTER 2.

3638

3654

BGNTST

;SET SIGNALS RST H AND MP H IN CONTROL REGISTER 0. THE SIGNAL RST W
:WILL PRESET THE RDV AND WRV FLIP-FLOP'S TO A 1. THE SIGNAL MP W
sWILL ALLOW THE MAP PROTECTION RAM BITS MPIN H AND WRE W TO BE READ
;INTO CONTROL REGISTER 2 ALONG WITH THE SIGNAL BRK L. THE SIGNALS
;MPIN H, WRE H, AND BRK L WILL BE READ AS CSR H, WREN H AND MSBRK M

33239

3644

THE TEST WILL

011312

011320

012737 000010 002264
012737
004737

177540

005414

002270

2%:

MOV

MOV
JSR

#MSEL1,R2LOAD

#177540, R2MASK
PC,LDRDR2

:SETUP TO SET MSEL1 H TO A 1

;SETUP TO READ MSBRK H AND LOWER S BITS

:GO LOAD, READ AND CHECK REG 2

SEQ 0072

[
o
| WARDWARE TESTS MACY11 30?(5252)
| CVCDAB.P11
7

BEQ

omgg 104455

TRAP

011326

011330

375
3676
3677
332;8

011332
011334
011336
011336

000002

000000
003712

104406

368! 1:

sug 011340 005037
3683
3684,
3685

011344
011350
011352

004737
001405

3687
3688
3689

011354
011356
011360

000003
004000

011362

104406

3686

TEST 15: CHECK RDV F/F TO SET (0) ¢ CLEAR (1) VIA RDE H, CK H + RST W

om%l. 001405

17-JUN~82 1

MRS
= N
12:02 PAGE 73

17-JUN-82

011352

3690 omos

002276

3s:

005462

104455

ERRDF

WORD

,R2EROR

CSERDF

WORD
.WORD
CKLOOP
TRAP

O
R2EROR

CLR

R4LOAD

:1F OK THEN CONTINUE

*RZG 2 NOT EQUAL EXPECTED

CSCLPY

:LOAD MSAD BIT 15 THROUGH 8 TO A 0 TO SELECT ADDRESS 0

JSR
BEQ
ERRDF

TRAP

PC.LDRDRS
48
3, ,R4EROR

CSERDF

LWORD
WMORD
.WORD

3
0
R4EROR

TRAP

CS$CLP1

CKLOOP

;SETUP TO SET ALL BITS TO 0

:GO LOAD,READ AND CHECK REG 4
:1F NO ERRORS THEN CONTINUE
*REGISTER & NOT ALL ZEROES

369
3694

;SET BITS MPIN H, WRE H AND MUTB H TO A ONE AND BIT RDE H TO A 0.
:RDE H ON A O WILL SET THE RDV FLIP-FLOP WHEN BIT CK W IS TOGGLED

3697 011364 Gi2737 000013 002302 4$:
3698 011372 012737 177760 002306

MOV
MOV

3702

TRAP

33232

3699
3700
3701

3703
3706
3705
3706
;;8;

:IN CONTROL REGISTER 0.

011400
011404
011406

004737
001405

011410
011412
011414
011416
011416

000004
002356
004052

011406

005506

104455

WORD
-WORD
.WORD
CKLOOP
TRAP

104406

%‘1’3
3711 011420 004737 005362
3712
3713

011424
011426

001405

3715
3716
3717
3718
g;;g

011430
011432
011434
011436
011436

000001
002463
004100

3714

011426

58:

104455

CSERDF

:GO LOAD,READ AND CHECK REGISTER 6
:OF COMPARED OK THEN CONTINUE
*MAP PROTECT RAM DATA ERROR

&
MSGMP
ALINFO
CSCLP1

PC,READRO
6$
1,MSGMPL,ALROIN

CSERDF

;READ AND CHECK REGISTER 0
*IF OK THEN CONTINUE
*REGISTER 0 CHANGED STATES

MSGMPL
ALROIN
CSCLP1

;SETUP TO READ CONTROL REGISTER 2 WITH MP H SET TO A 1 IN CONTROL
:REGISTER 0 TO ALLOW MPIN H, WRE H AND BRK L TO BE READ INTO

;g‘

725

JSR
BEQ
ERRDF

.WORD
.WORD
-WORD
CKLOOP
TRAP

104406

PC,LDRDR6
58
& ,MSGMP,AL INFO

;CHECK CONTROL REGISTER 0 TO MAKE SURE THAT NO CHANGES OCCLi.:D.

TRAP

3721
grzg

3726

JSR
BEQ
ERRDF

#MPINH'WREH 'MUTBH,R6LOAD ;SETUP TO LOAD THE MAP PROTECT RAM
#177760,R6MASK
:SETUP REGISTER 6 MASK WORD

sCONTROL REGISTER 2 AS BITS ESR H, WREN H, AND MSBRK M.

011440

011446

042737
052737

000140
000140

002270
002266

6$:

BIC

BIS

#ESRH'WRENH, R2MASK
#ESRH{ WRENH.R2GOOD

:CLEAR BITS TO BE CHECKED

*SETUP EXPECTED MAP PROTECT BIT

SEQ 0073

—_—————— e ——————
e m—

—_—

" WPSDWARE TESTS MACY11 so?(sgsz)
| CVCDAB.P11

L3727

011454

17-JUN~82 1

004737

3728
.
1

011460
011423

001405

3731

011464

3730

011462

011466
011470

00246
004126

g;gz

011472

104406

011472

TEST 15:

005430

052737

000120

3742
3743
37244

011510
011514
011516

004737
001405

005354

011502

011516

011520
011522
011524
011526
011526

002254

052737 000100 002252

78%:

104455

042737
042737
004737
001405

3760
3761
3762
3763
g;gls.

011554
011556
011560
011565
011562

000001
002463
004100

011552

000100
000100
005354

002254
002252

8S$:

104455

MORD

CSERDF

.WORD
.WORD

MSGMPL
ALR2IN

TRAP

CSCLP1

THE RDV F/F

SHOULD BE SET (0) AND THE WRV F/F SHOULD BE CLEARED (1}.

BIS

#CKH'RDVH,ROG00D

:SETUP EXPECTED DATA

JSR
BEQ
ERRDF

PC,LDRDOR
ut
1,MSGMPL,ALROIN

:GO LOAD, READ AND CHECK REG 0
“TF OK THEN CONTINUE
:RDV F/F PROBABLY NOT SET (0)

8IS

#CKH_,ROLOAD

sSETUP BIT TO BE LOADED

CSERDF

1
MSGMPL
ALROIN
CSCLP1

BIC
BIC
JSR
BEQ
ERRDF

#CKH,ROGOOD
#CKH . ROLOAD
PC,LDRDOR
98
1,MSGMPL ,ALROIN

LWORD
-WORD
.WORD
CKLOOP
TRAP

1
MSGMPL
ALROIN

104406

;CLEAR CKH IN EXPECTED BITS
:SETUP TO CLEAR BIT CK H IN REG 0
:GO CLEAR, LOAD AND CHECK REG 0
:IF OK THEN CONTINUE
*REG 0 NOT EQUAL EXPECTED

CSERDF

CSCLP1

;CHECK THAT SIGNAL MSBRK H IS SET TO A 1 IN CONTROL REGISTER 2

3768
3769

011564
011572

3771

011600

3773
3774
3775
3776
g;;;

011602
011604
011606
011610
011610

782

;IF OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

TRAP

g;gg

781

78
2,MSGMPL ,ALR2IN

SEQ 0074

;CLEAR THE SIGNAL CK H IN CONTROL REG 0. NO OTHER BITS SHOULD CHANGE STATF.
011530
011536
011544
011550
011552

3779
3780

BEQ
ERRDF

WORD
.WORD
.WORD
CKLOOP
TRAP

104406

3756
3755
3756
3757
3758

3772

VIA RDE H, CK H + RST M

:GO READ REGISTER 2 AND CHECK IT

TRAP

000001
002463
004100

g;g%

3770

¢ CLEAR (1)

;SET SIGNAL CK H IN CONTROL REGISTER 0 TO CLOCK THE WRV AND RDV

011476

3759

(0)

PC,READR2

:F/F'S.

740

3745

TO SET

JSR

CKLOOP

3;;3

3746
3747
3748
3749
g;gg

CHECK RDV F/F

TRAP

3737

37641

17=JUN-82 12:02 PAGE 74

104455

gr
733

373,

————————
e

011576

011600

052737
004737

001405

104455

ooooog
00246
004126
104406

000340
005430

002266

9$:

8IS
JSR

#MSBRKH 'WRENH'ESRH,R2G0O0D ;SETUP EXPECTED BITS IN REGISTER 2
PC ,READR?
;GO READ REGISTER 2 AND CHECK IT

ERRDF

2,MSGMPL ,ALR2IN

MORD
.WORD
.WORD
CKLOOP
TRAP

2
MSGMPL
ALR2IN

BEQ

TRAP

10§

CSERDF

:IF OK THEN CONTINUE

:MSBRK W PROBABLY NOT SET VIA BRK L BEING LOW

CSCLP1

;THE FOLLOWING SECTION WILL CHECK THAT THE RDV FLIP=-FLOP CAN NOT BE
;CLEARED (1) BY TRYING TO CLOCK A ONE INTO IT. ONCE THE RDV FLIP-FLOP

;1S SET (0),

IT IS LATCHED TO THAT STATE UNTIL A PULSE IS ISSUED ON THE

*SIGNAL RST'H OR INIT .

.[ HARDWARE TESTS
|

CVCDAB.P11

MACYN

30?(3252)

17-JUN-82 1

3783
3784

012737

000017

785

011612

011620

004737

786 ouesl. 001405

3787

011626

3789
3790
3791
3792
3773‘

011630
011632
011634
011636
011636

005506

17=JUN-82

002302

10$:

MOV

#MPINH'WREH
'RDEH 'MUTBH,R6LOAD :SETUP TO SET ALL RAM BITS TO 1

BEQ

11§
& MSGMP,AL INFO
CS$ERDF

JSR

ERRDF

TRAP

000004
002356
004052

MORD
.WORD
.WORD
CKLOOP
TRAP

104406

%7732

PC,LDRDR6

011640

3799

011646

011644

011646

004737

001405

005362

118:

104455

3801
3802
3803
3804
3805

011650
011652
011654
011656
011656

000001
002463
004100

;GO LOAD, READ AND CHECK RAM

:IF ALL ONES THEN CONTINUE

*MAP PROTECT RAM DATA ERROR

&
MSGMP
ALINFO
(SCLP1

3810

011666

004737

3812
3813
3814
3815
3816
3817
333}3

011674
011674
011676
011700
011702
011704
011704

JSR

PC ,READRO

;GO READ AND CHECK REGISTER 0

ERRDF

1,MSGMPL ,ALROIN

*REGISTER O CHANGED STATE

BEQ

TRAP

104406

12§

CS$ERDF

*IF NO CHANGES THEN CONTINUE

JWORD
.WORD
.WORD
CKLOOP
TRAP

1
MSGMPL
ALROIN

JSR

PC ,READR?

;GO READ AND CHECK REGISTER 2

ERRDF 2,MSGMPL ,ALR2IN
TRAP
CSERDF
.WORD
2
-WORD
MSGMPL
.WORD
ALR2IN
CKLOOP
TRAP
CSCLP1

*REGISTER 2 NOT EQUAL EXPECTED

CSCLPI

.',ao:rE
3809!! 011660 052737 000340 002266 128:

;CHECK CONTROL REGISTER 2 TO HAVE ESR W, WREN H AND MSBRK H SET TO 1
BIS
#ESRH'WRENH 'MSBRKH,R2GOOD ;SETUP EXPECTED DATA

3811

BEQ

011672

001405

005430

104455
000002
002463
004126
104406

13§

:IF NO ERRORS THEN CONTINUE

3820

sSET THE SIGNAL CX H TO THE HIGH STATE TO CLOCK THE WRV AND RDV FLIP=-

3az§

;SET ALREADY.

3821

;FLOPS.

%‘

011706

052737

000100

011722

004737

005354

3830

3831
sasg
3833
383,
333;2

THE RDV FLIP=-FLOP SHOULD REMAIN SET (0) AS A RESULT OF IT BEING
THE RDV FLIP-FLOP, ONCE SET, CAN NOT BE CLOCKED AGAIN

;UNLESS IT HAS BEEN PRESET BY A PULSE ON THE SIGNALS RST M OR INIT H.

3825

3826

SEQ 0075

:CHECK THAT CONTROL REGISTER O DID NOT CHANGE STATE.

3797

3800

PAGE 75

TEST 15: CHECK RDV F/F TO SET (0) + CLEAR (1) VIA RDE M, CK M + RST M

3788 omgg 104455

3798

12:02

011714

011730

011732
011734
011736
011740
011740

052737
104455

000001
002463
004100
104406

000100

002252

002254

138:

BIS

#CKH,ROLOAD

;SETUP TO SET SIGNAL CK H TO WIGH STATE

JSR

PC,LDRDOR

:GO LOAD, READ AND CHECK CONTROL REG 0

BIS

TRAP

LWORD
-WORD
"WORD
CKLOOP
TRAP

#CKH_ROGOOD

:EXPECT CK W TO BE SET IN CONTROL REG 0

CSERDF

1
MSGMPL
ALROIN
CSCLP1

;READ CONTROL REG 2 TO CHECK THAT ESR M, WREN H AND MSBRK W ARE STILL SET TO 1°S

| WARDWARE TESTS MACY11 somosz)
CVCDAB.P11

3842

3843
384e
3845
3846
33%

011762

17=JUN~82

11:26

004737

005430

011746

001405

011750

104455

011750

011752
011754
011756
011760
011760

17=JUN=-82 12:02 PAGE 76
148:

3856

011776

ooooog
00246
004126
104406

011774

011776

012000
012002
012004
012006
012006

112737
004737

001405

000005
005346

002252

158:

ERRDF

2,MSGMPL,ALR2IN

*REGISTER 2 NOT EQUAL EXPECTED

MORD
"WORD
.WORD
CKLOOP
TRAP

2
MSGMPL
ALR2IN

CSERDF

:IF OK THEN CONTINUE

CSCLP1

MOVB
JSR

#RSTH'MPH,ROLOAD
PC,LDRDRO

;SET RST H AND CLEAR CK W
:G0 LOAD, READ AND CHECK CONTROL REG 0

“RRDF

1.MSGMPL ,ALR0IN

RDV F/F PROBABLY NOT CLEARED BY RST H

4EQ

104455

1%AP

000001
002463
004100

.WORD
.WORD
"WCRD
CKLOOP
TRAP

104406

38643“5

168

CSERDF

:IF LOADED OK THEN CONTINUE

MSGMPL
ALROIN
CSCLPY

;CLEAR THE SIGNAL RST H IN CONTROL REGISTER 0

3866
3867

012010
012016

3869
3870
3871
3872
3873
3874
g;g

012024
012024
012026
012030
012032
012034
012034

012022

042737
004737

001405

000001
005346

002252

168:

BIC
JSR

BEQ

#RSTH,ROLOAD
PC,LDRDRO

17§

ERRDF 1,MSGMPL ,ALROIN
TRAP
CSERDF
WORD
1
"WORD
MSGMPL
.WORD
ALROIN
CKLOOP
TRAP
CSCLP1

104455
000001
002463
004100
104406

3877

:SETUP TO CLEAR RST M
:GO LOAD, READ AND CHECK CONTROL REG 0

+IF LOADED OK THEN CONTINUE

:CONTROL REG O NOT EQUAL EXPECTED

;CHECK CONTROL REGISTER 2 TO MAKE SURE THAT THE SIGNAL MSBRK W WENT TO

333;3

:A ZERO AS A RESULT OF THE WRV AND RDV FLIP-FLOPS BEING PRESET BY RST H.

3880

012036

3883

012052

3884

am AND CHECK comoc. REGISTER 2

15¢

:SET IN ITS PRESET STATE (1).

011762
011770

3881
mg

PC ,READR2

;CLEAR THE SIGNAL CK M AND SET THE SIGNAL RST W IN CONTROL REGISTER 0.
;SETTING THE SIGNAL RST H TO A ONE WILL CAUSE THE RDV FLIP-FLOP TO BE

3853
3856

3857

JSR

BEQ

TRAP

3331

3858
3859
3860
3861
%g

TEST 15: CHECK RDV F/F TO SET (0) + CLEAR (1) VIA RDE M, CK M + RST H

3849
3850
3855

042737

012044
012050

004737
001404

012052

104455

3885

012054

3887
3888
3889
3890
3891
3892
33332

012060
012062
012062
012062
012064
012064
012064

3886 012056

000200

005430

002266

178:

104401

ERRDF

nscm.mzm

.WORD

002463
104405

#MSBRKH, R2GOOD

JSR
BEQ

TRAP

000002

004126

BIC

188:
100008:

L10046:

PC ,READR?2
ai

-WORD

nsafl

TRAP
ENDTST

CSESEG

TRAP

CSETST

.WORD
ENDSEG

ALR2IN

:CLEAR MSBRK H IN EXPECTED DATA

:READ AND CHECK CONTROL REGISTER 2
:IF MSBRK H EQUALS A O THEN CONTINUE

:CONTROL REGISTER 2 NOT EQUAL EXPECTED

SEQ 0076

HARDWARE TESTS MACYN 30?(1252)
CVCDAB.P11
17=JUN=82 11:2

)

17=JUN-82
12:02 PAGE 77
TEST 16: CHECK THAT SIGNAL RST W WILL CLEAR RDV ¢ WRV 7/F'S

gggz

.SBTTL TEST 16: CHECK THAT SIGNAL RST H WILL CLEAR RDV + WRV F/F°S

3897

14e

3898
3899
900

: TEST TO CHECK THAT THE RDV AND WRV FLIP=FLOPS CAN BE SET VIA THE SIGNALS
: WRE M, RDE H, AND CK H. THE TEST WILL CHECK THAT THE SIGNAL RST W WILL
: CLEAR THE RDV AND WRV FLIP-FLOPS.
THE SIGNAL MSBRK WILL BE CHECKED TO BE

390
390
3904
3905
2906
3907
3908

: FLIP=FLOPS ARE CLEARED.
R

901

;3?3

: A ONE WHEN THE RDV AND WRV FLIP=FLOPS ARE SET AND CHECKED FOR A O WHEN THE

012066
012066
012066
012072
012072

004737

T16::

004550

104404

3911
3912
3913
3914
3915
;3}9

3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
gg%g

012074
012100
012106
012114
012120
012122
012122
012124
012126
012130
012132
012132

105037
052737
042737
004737
001405

002252
000005
000060
005346

CLRB
BIS
BIC
JSR
BEQ
ERRDF
TRAP
LWORD
WORD
.WORD
CKLOOP
TRAP

002252
002256

104455
000001
000000
003624
104406

PC,INITMS

/
sSELECT AND INIT ;HE MEMORY SIMULATOR

($BSEG

ROLOAD
#RSTH!MPH,ROLOAD
#WRVH | RDVH, ROMASK
PC,LDRDRO
1$
1, ,ROEROR
CSERDF
1
0
ROEROR

;CLEAR LOWER BYTE OF REG 0 FOR LOOPING
:SETUP TO SET RST H AND MP H
:SETUP TO CHECK WRV AND RDV F/F
:GO LOAD, READ AND CHECK REG 0
:IF OK THEN CONTINUE
:REGISTER 0 NOT EQUAL EXPEC ED

CSCLP1

;CLEAR SIGNAL RST W IN CONTROL REGISTER 0, RDV AND WRV BITS SHOULD NOT

gggg

sCHANGE STATE IN CONTROL REGISTER 0.

3934
3935
3936
3937

012134
012142
012146
012150

042737
004737
001405

3939
3940
3941
3942
334“

012152
012154
012156
012160
012160

000001
000000
003624

012150

000001
005346

002252

18$:

104455

BIC
JSR
BEQ
ERRDF

#RSTH,ROLOAD
PC,LDRDRO
2
1, ,ROEROR

LWORD
WORD
.WORD
CKLOOP
TRAP

1
0
ROEROR

TRAP

104406

3945

CSERDF

;SETUP TO CLEAR RST W IN REG 0
:GO LOAD, READ AND CHECK REG 0
:1F EQUAL THEN CONTINUE
*REGISTER NOT EQUAL EXPECTED

CSCLP?

;SET SIGNAL MSEL1 W TO A ONE AND MSAD BITS 17 AND 16 TO A 0. THE

?329

;SIGNAL MSBRK W SHOULD BE A 0 DURING THIS TEST

3948

012162

012737

000010

3950

012176

004737

005414

3949

JSR
BGNSEG
TRAP

;SET SIGNALS RST H AND MP W IN CONTROL REGISTZR 0.
THE SIGNAL RST M
;WILL PRESET THE RDV AND WRV FLIP-FLOP'S TO A 0.
THE SIGNAL MP M
;WILL ALLOW THE MAP PROTECTION RAM BITS MPIN H AND WRE H TO BE READ
:INTO CONTROL REGISTER 2 ALONG WITH THE SIGNAL BRK L.
THE SIGNALS
:MPIN H, WRE H, AND BRK L WILL BE READ AS ESR H, WREN H AND MSBRK W
+IN CONTROL REGISTER 2.

3931

3938

BGNTST

012170

012737

177540

002264

002270

2$:

MOV

cns;§1 R2LOAD

JSR

PC,LDRDR2

MOV

#177540, RIMASK

:SETUP TO SET MSEL1 H TO A 1

:SETUP TO READ MSBRK H AND LOWER 5 BITS
:GO LOAD, READ AND CHECK REG 2

SEQ 0077

HARDWARE TESTS

CVCDAB.P11

MACY1 30A(1052)
17-JUN-82 11:26

17=JUN=-82
12:02 PAGE 7¥
TEST 16: CHECK THAT SIGNAL RST M WILL CLEAR RDV ¢ WRV F/F'S

001405

BEQ
ERRDF

104455
000002
000000
003712

TRAP

ciéno;

~WORD
"WORD
CKLOOP

o
R2EROR

.WORD

104406

TRAP

R2EROR

;1F OK THEN CONTINUE
*REG 2 NOT EQUAL EXPECTED

CSCLP1

;LOAD MSAD BIT 15 THROUGH 8 TO A 0 TO SELECT ADDRESS 0
e

CLR
JSR

BEQ
ERRDF

TRAP

.WORD
-WORD
"WORD
CKLOOP
TRAP

R4LOAD
PC LDRDR4
s
,RGEROR

cienor

;SETUP TO SET ALL BITS TO O
*GO LOAD,READ AND CHECK REG 4

*IF NO ERRORS THEN CONTINUE
*REGISTER 4 NOT ALL ZEROES

o
R4EROR
CSCLP1

sSET BITS MPIN H AND MUTB H TO A ONE AND BITS WRE H AND RDE H TO
sA 0.
RDE H AND WRE H ON A 0 WILL SET THE RDV AND WRV FLIP=-FLOPS WHEN
;THE SIGNAL CK H IS TOGGLED IN CONTROL REGISTER 0.

012737
012737
004/ 37
001405

002302
002306

4§:

MoV

#MPINH
' MUTBH, R6LOAD

:SETUP TO LOAD THE MAP PROTECT RAM

JSR

PC,LDRDRG

:GO LOAD,READ AND CHECK REGISTER 6

ERRDF

& ,MSGMP,AL INFO

*MAP PROTECT RAM DATA ERROR

WORD
.WORD
.WORD
CKLOOP
TRAP

&
MSGMP
ALINFO

MOV
BEQ

TRAP

104455
000004
002356
004052
104406

#177760,R6MASK
58

CSERDF

SSETUP Resxsrsn 6 MASK WORD

:OF COMPARED OK THEN CONTINUE

CSCLP1

;CHECK CONTROL REGISTER O TO MAKE SURE THAT NO CHANGES OCCURED.
004737
001405

JSR
BEQ
ERRDF
TRAP

LWORD
"WORD
"WORD
CKLOOP
TRAP

PC,READRO
6$
1,MSGMPL ,ALROIN
CS$ERDF

;READ AND CHECK REGISTER 0

:16 OK THEN CONTINUE
*REGISTER 0 CHANGED STATES

1
MSGMPL
ALROIN
CSCLP'

sSETUP TO READ CONTROL REGISTER 2 WITH MP H SET TO A 1

IN CONTROL

:REGISTER 0 TO ALLOW MPIN W, WRE H AND BRK
L TO BE READ INTO

sCONTROL REGISTER 2 AS BITS ESR H, WRFN H, ANO MSBRK H.

002270
002266

68:

BIC

BIS

#ESRH'!WRENH ,R2MASK
#ESRH,R2G00D

sCLEAR BITS TO BE CHECKED

sSETUP EXPECTED MAP PROTECT BIT

SEQ 0078

HARDWARE TESTS MACY11 SOA(IOSZ)
CVCDAB.P11
17=JUN-82 11:26

4007

4008

012332

012336

4009

012340

4011
4012
4013
4014
28}2

012342
012344
012346
012350
012350

4010

015340

004737

001405

17=JUN=-82
12:02 PAGE 79
TEST 16: CHECK THAT SIGNAL RST W WILL CLEAR RDV ¢ WRV F/F'S

005430

104455

104406

052737
052737
004737
001405

4026

012376

012374

104455

012400

002463

012402
012404
012404

000160
000100
005354

002254
002252

78:

.WORD

004100

.WORD
CKLOOP
TRAP

104406

:IF OK THEN CONTINUE

nscan
ALR2IN
CSCLP1

THE RDV AND WRV FLIP=FLOPS SHOLUD BE SET TO A 1.

#CKH'RDVH'WRVH,ROGOOD
#CKH,ROLOAD
PC,LDRDOR
8s
1,MSGMPL,ALROIN

CSERDF

;SETUP EXPECTED DATA
*SETUP BIT TO BE LOADED
:GO LOAD, READ AND CHECK REG 0
:IF OK THEN CONTINUE
*REGISTER 0 NOT EQUAL EXPECTED

MSGMPL

ALROIN
CSCLP1

;CLEAR THE SIGNAL CK H IN CONTROL REGISTER 0. NO OTHER BITS SHOULD

:CHANGE STATE.

4035
4036
4037

012406
012414
012422

042737
042737
004737

4039

012430

4041
4042
4043

012432
012434
012436

000001
002463
004100

2822

012440

104406

4038 012426 001405

000100
000100
005354

002254
002252

8S$:

012440

BIC
BIC
JSR

BEQ

ERRDF

4040 012430 104455

TRAP

#CKH,ROGOOD
#CKH. ROLOAD
PC,LDRDOR

HSGHPL.ALROIN

.WORD
-WORD
-WORD

nscan
ALROIN

TRAP

CSCLP1

CKLOOP

282;

;CLEAR CKH IN EXPECTED BITS
:SETUP TO CLEAR BIT CK H IN REG 0
:GO0 CLEAR, LOAD AND CHECK REG 0

:IF OK THEN CONTINUE

*REG 0 NOT EQUAL EXPECTED

;CHECK THAT SIGNAL MSBRK M IS SET TO A 1 IN CONTROL REGISTER 2

4049
4050

012442
012450

4052

012456

4054
4055
4056
4057
28?3

012460
012462
012464
012466
012466

4060
4061

BIS
BIS
JSR
BEQ
ERROF

WORD

28;{

4053

*REGISTER 2 NOT EQUAL EXPECTED

TREZ

4032

4051

2 HSGHPL ALR2IN

sFLIP=FLOPS.
012352
012360
012366
(12372
012374

4044

ERRDF

78’

;SET SIGNAL CK H IN CONTROL REGISTER 0 TO CLOCK THE WRV AND RDV

4020
4021
4022
4023
4024

4028
4099
28%?

;G0 READ necxsrsn 2 AND CHECK IT

.WORD
-WORD
.WORD
CKLOOP
TRAP

28}3

4027

PC,READR2

TRAP

ooooog
00246
004:76

4017

4025

JSR

BEQ

012454

012456

052737
004737

001405
104455

oooooi
00246
004126

104406

000240
005430

002266

9$:

BIS
JSR

#MSBRKH ' ESRH,R2G0OD
PC,READR?

ERRDF

2,MSGMPL ,ALR2IN

.WORD
.WORD
-WORD
CKLOOP
TRAP

2
MSGMPL
ALR2IN

BEQ

TRAP

10§

CSERDF

;SETUP EXPECTED BIT IN REGISTER 2
:GO READ REGISTER 2 AND CHECK IT

*IF OK THEN CONTINUE

*REGISTER 2 NOT EQUAL EXPECTED

CSCLP1

;THE FOLLOWING SECTION WILL CHECK THAT THE SIGANL RST W WILL CLEAR
STHE RDV AND WRV FLIP=-FLOPS.

SEQ 0079

HARDWARE TESTS

30A(;2$2)

052737
004737

000005
005346

.
o~
O

17-JUN-82
1

pury

(=leleleleleleTe] o

CVCDAB.P11

MACY11

104455

000001
002463
004100

104406

17-JUN-82 12:02 PAGE 80
TEST 16: CHECK THAT SIGNAL RST H WILL CLEAR RDV + WRV F/F'S

002252

10$:

BIS
JSR

#RSTH!MPH ,ROLOAD
PC,LDRDRO

;SETUP TO SET THE SIGNAL RST W
.GO LOAD, READ AND CHECK REG 0

ERRDF

1,MSGMPL,ALROIN

aov AND WRV PROBABLY NOT CLEARED

BEQ

TRAP

WORD
"WORD
.WORD

CKLOOP
TRAP

11$

CSERDF

IF REG 0 OK THEN CONTINUE

MSGMPL
ALROIN
CSCLP1

R A2

Be R

]

OO0O0O0O0O0O0O0O00

;CLEAR THE SIGNAL RST H IN CONTROL REGISTER 0

042737
004737
001405

104455

BIC
JSR

#RSTH,ROLOAD
PC,LDRDRO

;SETUP TO CLEAR SIGNAL RST W
16O LOAD,READ AND CHECK REG 0

ERRDF

1,MSGMPL,ALROIN

*REGISTER O NET EQUAL EXPECTED

BEQ

rsszb

C$ERDF

.WORD

1
MSGMPL

CKLOOP
TRAP

CSCLP1

.WORD

104406

12§

:IF OK THEN CONTINUE

ALROIN

;READ REGISTER 2 AND CHECK THAT THE SIGNAL MSBRK W WENT T0 A 0
042737
004737
001404

104455

BIC
JSR

#MSBRKH , R2GOOD
PC ,READR2

;CLEAR EXPECTED BIT IN REG 2
:GO READ AND CHECK REGISTER 2

ERRDF

2,MSGMPL,ALR2IN

*REGISTER 2 NOT EQUAL EXPECTED

BEQ

TRAP

WORD

13$

CSERDF

.WORD

MSGMPL

TRAP

CSESEG

TRAP

CSETST

-WORD
ENDSEG
ENDTST

ALR2IN

:1F OK THEN CONTINUE

SEQ 0080

HARDWARE TESTS

CVCDAB.P11

MACY11

30A(1052)

17=JUN=-82 11:26

17-JUN-82

12:02

PAGE 81

TEST 17: CHECK MODULE SELECT RAM 0 USING A BINARY COUNT

2}82

.SBTTL TEST 17: CHECK MODULE SELECT RAM 0 USING A BINARY COUNT

6106

14e

4107
4108
4109
4110

; TEST TO CHECK MODULE SELECT RAM 0. A BINARY COUNT PATTERN WILL BE LOADED
: INTO EACH ADDRESS OF THE MODULE SELECT RAM 0.
FOR EACH PATTERN LOADED THE
; TEST WILL CHECK FOR THE APPROPRIATE ENABLES ON THE OUTPUT OF THE RAM. IF
: MORE THEN ONE BIT IS SET ON THE INPUT TO THE RAM, ONLY ONE BIT WILL BE SET ON

PRRE

: THE OUTPUT OF THE RAM. A ONE IN THE LEAST SIGNIFICANT BIT OF THE RAM WILL

411;

: FORCE THE REMAINING MORE SIGNIFICANT BITS TO A ZERO. MODULE SELECT RAM O

2}}2

; ASSERT THE SIGNAL SMDSO L. THE SIGNAL SMDSO L WILL SELECT MODULE SELECT RAM 0.

41
6114

: 1S SELECTED BY SETTING THE SIGNAL MSELO H TO 1 AND MSEL1 H TO A O IN CONTROL
: REGISTER 2 AND THEN DOING A WRITE OR READ TO CONTROL REGISTER 6 WHICH WILL

6117
4118
4119
4120
4121

012574
012574
012574
012600

4124

012604

2}55

2}52

012602

012604

004737
005001

117::

004550

005002

1$:

104404

012606
012614
012622
012626
012630

012737
012737
004737
001405

4138
4139
4140
4141

012632
012634
012636
012640

000002
000000
003712

012630

012640

000004
177740
005414

002264
002270

104455

104406

010137
004737
001405

4152

012656

000003

4158
4159

*SET DATA PATTERN INITIALLY TO 0

($BSEG

#MSELO,R2LOAD
#177740,R2MASK
PC,LDRDR2
28"
2, ,RZEROR

WORD
WORD
.WORD
CKLOOP

2
O
R2EROR

CS$ERDF

sSETUP TO SET MSELO H TO A 1
:SETUP MASK WORD TO IGNORE BITS 15-5
:GO LOAD, READ AND CHECK REG 2
:IF LOADED OK THEN CONTINUE
:REG 2 NOT EQUAL EXPECTED DATA

CSCLPI

;MSAD BITS 15-13 SELECT MODULE SELECT RAM O ADDRESSES.

012642
012646
012652
012654

2};9

;SELECT AND INIT THE MEMORY SIMULATOR
:CLEAR MSAD BITS 15-13

;SET MSAD BITS 15-13 IN CONTROL REGISTER 4 TO THE ADDRESS TO BE TESTED.

4147
4148
4149
4150

4153

MOV
MOV
JSR
BEQ
ERRDF

TRAP

2}22

4154
4155

TRAP

4144

4151

BGNSEG

PC,INITMS
R1

;SET SIGNAL MSELO H TO A ONE AND SIGNALS MSEL1 H, MSAD16 H AND MSAD17 H
:TO A O IN CONTROL REGISTER 2. THE SIGNAL MSELO H ON A 1 WILL CAUSE
sTHE SIGNAL SMDSO L TO BE ASSERTED ON A WRITE OR READ TO REGISTER 6.
;THE SIGNAL SMDSO L WILL SELECT MODULE SELECT RAM 0.

4132
6133
4136
4135
4136

2}25

JSR
CLR

CLR

6127
4128
4129
215?

4137

BGNTST

012654

012660
012662
012664
012664

104455

000000
004000
104406

002276
005462

28:

MOV
JSR
BEQ
ERRDF

R1,R4LOAD
PC . LDRDRS
3$
3, ,R4EROR

WORD

TRAP

CS$ERDF

WORD

O
R4EROR

TRAP

CSCLP1

-WORD
CKLOOP

;SETUP BITS TO BE LOADED
:G0 LOAD, READ AND CHECK REGISTER &
:IF LOADED OK THEN CONTINUE
:REGISTER & NOT EQUAL EXPECTED DATA

:THE FOLLOWING TEST WILL WRITE THE &

BIT DATA PATTERN INTO THE RAM

:LOCATION ADDRESSED BY MSAD BITS 15-13, AND CHECK THAT THE CORRECT

SEQ 0081

HARDWARE TESTS MACY1 30A(1052)
17-JuN-82
CVCDAB.P11
1 1:26

17-JUN-82
1
TEST 1

:02

PAGE 82

CHECK MODULE SELECT RAM 0 USING A BINARY COUNT

;PATTERN IS READ BACK.

ON A WRITE OR READ COMMAND TO CONTROL
REGISTER 6 WITH THE SIGNAL MSELO W A 1 AND SIGNAL MSEL1 W A 0,

SEQ 0082

THE

280000

N
N

177760

002302

002306

3$:

#BIT3!BIT2!BIT1,R3
4(S:

63
gglf1.fl3

5$:

#B8IT3!BIT2,R3
63
#B8IT2,R3
63
#BIT3,R3

6$:

R3 R6GOOD

;g.LDRD6R

4 nscnoo ALINFO

sSETUP REGISTER 6 MASK WORD
:SETUP DATA PATTERN TO BE LOADED
:COPY DATA TO BE LOADED

CHECK IF BIT 0 IS SET

sIF NOT GO CHECK BIT 1
:CLEAR MOST SIGNIFICANT BITS
:GO DO THE TEST
sCHECK IF BIT 1 IS SET

:IF NOT THEN GO CHECK CHECK BIT 2
sCLEAR MORE SIGNIFICANT BITS

;GO START THE TEST
:CHECK IF BIT 2 IS SET

:IF NOT THE GO DO THE TFST
sCLEAR MOST SIGNIFICANT bIT
sSAVE EXPECTED PATTERN
;GO LOAD, READ, AND CHECK REG 6
:IF DATA OK THEN CONTINUE
;DATA ERROR IN MODULE SELECT RAM 0

HSGHDO
ALINFO

7%:

10000$-

e
d e
b d

d e

00000

#177760,REMASK

Rs RgLOAD

02170.R3

000001

O0O00O00O0

D
e e
D D

OO0 OO0O0O0O0O0O0O0O0O0O00O0O0O0O0O000

;SIGNAL SMDSO L WILL BE ASSERTED WHICH WILL SELECT MODULE SELECT RAM 0.

000020

CSESEG
R2

sUPDATE DATA PATTERN BY 1
sCHECK IF DONE
s IF NOT THEN DO NEXT PATTERN
sRESET PATTERN TO 0

#MSAD13,R1
18

sUPDATE MODULE SELECT RAM ADDRESS BY 1
:IF NOT DONE REPEAT THE TEST

#20,R2

020000

L10050:

CSETST

HWARDWARE TESTS

' CVCDAB.P11

MACY11

30&(1052)

17-JUN=-82 11:26

17=JUN=-82

420

:
:
;
;
:
:
:
:
;

4213

TEST TO CHECK MODULE SELECT RAM 1.
A BINARY COUNT PATTERN WILL BE LOADED 1~ro
EACH ADDRESS OF THE MODULE SELECT RAM 1.
FOR EACH PATTERN LOADED, THE TEST
WILL CHECK FOR THE APPROPRIATE ENABLES ON THE OUPUT OF THE RAM.
IF MORE THEN
ONE BIT IS SET ON THE INPUT TO THE RAM, ONLY ONE BIT WILL BE SET ON THE
OUTPUT OF THE RAM,
A ONE IN THE LEAST SIGNIFICANT BITS OF THE RAM WILL
FORCE THE MORE SIGNIFICANT BITS TO ZEROES.
MODULE SELECT RAM 1 IS SELECTED
av SETTING THE SIGNALS MSELO W AND MSELT M TO A ONE IN CONTROL REGISTER 2
AND THEN DOING A WRITE OR READ O CONTROL REGISTER 6 WHICH WILL Assenr THE
SIGNAL SMDS1 L. THE SIGNAL SMDS1 L WILL ENABLE MODULE SELECT RAM
1 TO BE

: WRITTEN
OR READ. MSAD BITS 17 AND 16 WILL BE USED TO ADDRESS THE MODULE

4214

: SELECT RAM 1.

4216
4217
4218
4219

013012
013012
013012

004737

2555

013022

005002

013016

013024
013024

012701

T18::

004550

000014

18:

10440%

013026

010137

002264

423,
4235
4236

013040
013044
013046

004737
001405

005414

4238
4239
4240
4241
252

013050
013052
013054
013056
013056

000002
000000
003712

013032

012737

177740

CLR

2SET DATA PATTERN INITIALLY TO O

BGNSEG
TRAP

#MSELO!'MSELT,RY

:SETUP BITS FOR CONTROL REGISTER 2

(S$BSEG

:SETUP ADDRESS + SET MSELO AND MSEL1 =

PC,LDRDR2
zs
LR2EROR

:GO LOAD, READ AND CHECK REGISTER 2
:IF LOADED OK THEN CONTINUE
sREGISTER 2 NOT EQUAL EXPECTED

#177740,R2MASK

TRAD

cienor

.WJORD
. JORD
.WORD
CKLOOP
TRAP

104406

R1,R2LOAD

MOV

JSR
BEQ
ERRDF

4244

:SETUP REGISTER 2 MASK WORD

o
R2EROR

CSCLP1

:THE FOLLOWING TEST WILL WRITE THE & BIT DATA PATTERN INTO THE RAM

4245
4246
447
2523

:LOCATION ADDRESSED BY MSAD BITS 17 AND 16, AND CHECK THAT THE
;CORRECT PATTERN IS READ BACK.
ON A WRITE OR READ COMMAND TO
;CONTROL REGISTER 6 WITH THE SIGNALS MSELO H AND MSEL1 W SET TO A 1.
sTHE SIGNAL SMDS1 L WILL BE ASSERTED TO ENABLE MODULE SELECT RAM 1.

4250

013060

4252

013072

425,

;SELECT AND INIT THE MEMORY SIMULATOR

MOV

002270

4237 013046 104455

4255
4256

PC,INITMS

:RAM 1,

4232

4253

JSR

;SET SIGNAL MSELO H AND MSEL1 H TO A ONE AND MSAD BITS 17 AND 1
:TO THE ADDRESS TO BE TESTED.
THE SIGNALS MSELO H AND MSEL1 W WILL
;CAUSE THE SIGNAL SMDS1 L TO BE ASSERTED ON A WRITE OR READ TO
;CONTROL REGISTER 6.
THE SIGNAL SMDS1 L WILL ENABLE MOCDULE SELECT

zg?

4251

BGNTST

MOV

4226
4227
4228
4339

4233

.SBTTL TEST 18: CHECK MODULE SELECT RAM 1 USING A BINARY COUNT

4204
4205
4206
4207
4208
4209
4210
6211
4212

4223
2552

PAGE 83

TEST 18: CHECK MODULE SELECT RAM 1 USING A BINARY COUNT

2;8%

4220

12:02

012737

177760

013066

010237

002302

013074

032703

000001

042703
000413

000016

013100

013102
013106

010203
001403

002306

2$%:

MOV

#177760,R6MASK

;SETUP REGISTER 6 MASK WORD

MOV

R2,R6LOAD

BIT

#81T0,R3

“CHECK IF BIT 0 ISS

BIC
B8R

#BIT3!'BIT2!BIT1,R3
58

SIF YES = O MOST SIGNIFICANT BITS
GO LOAD THE DATA PATTERN

MOV
BEQ

R2.R3
3s

:SETUP PATTERN TO BE LOADED

:COPY DATA PATTERN vo se LOADED

+IF NOT GO CHECK anr 1

SEQ 0083

HARDWARE TESTS

CVCDAB.P11

4257
4258
4259
4260
4261

&2
4263
4264
4265

4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284

013110
013114
013113
0131%
013124

MACY11 30 A(1052)

17=JUN-82 1 1:26

032703

38:

000014

013130
013132
013136
013142

013146
013150
013150
013152
013154
013156
013160
013160
013160
013162
013164
013170
013172
013174
013176
013202
013204
013204
013204

000002

000004

4$:

000010
002304
005¢14

5%:

BIT
BEQ
BIC

#8IT1,R3
4
#BIT3!BIT2,R3

BIT
BEQ
BIC

#BIT2,R3
58
IT3.R3

BEQ
ERRDF

6S
& ,MSGMD1,ALINFO

WORD
"WORD
.WORD
ENDSEG

&
MSGMD1
ALINFO

B8R

MOV
JSR

TRAP

6$:

10000$:

000020

104401

17-JUN-82 12:0? PACE 84
TEST 18: CHECK MODULE SELECT RAM 1 USING A BINARY COUNT

L10051:

TRAP

R3,R6G00D
PC.LDRD6R

CSERDF

(CSESEG

INC
CMP
BNE
CLR
INC
BIT

R2
#20,R2
1$
R2
R1
#BIT4 R

TRAP

CSETST

BEQ
ENDTST

sCHECK IF BIT 1 IS SET
sIF NOT THEN CHECK BIT 2
sIF YES = 0 MOST SIGNIFICANT BITS
:GO_LOAD THE DATA PATTERN
sCHECK IF BIT 2 IS SET
sIF NOT GO LOAD THE DATA PATTERN

sCLEAR MOST SIGNIFICANT BITS
sSAVE EXPECTED DATA PATTERN
;GO LOAD, READ AND CHECK DATA
sIF DATA OK THEN CONTINUE
;DATA ERROR IN MODULE SELECT RAM 1

sUPDATE THE DATA PATTERN
sCHECK IF BINARY COUNT DONE
sIF NOT LOAD NEXT PATTERN
sOTHERWISE CLEAR DATA PATTERN
sUPDATE MSAD BITS 17 AND 16
sCHECK IF DONE

sIF NOT THEN CHECK NEXT ADDRESS

SEQ 0084

HARDWARE TESTS

CVCDAB.P11

MACY11

30?(1252)

17-JUN~82 11:2

17=-JUN-82

12:02

PAGE 85

TEST 19: CHECK MODULE SELECT RAM 0 + 1 CHIP SELECT LOGIC

:ggg

LSBTTL TEST 19: CHECK MODULE SELECT RAM 0 ¢ 1 CHIP SELECT LOGIC

(288

14e

4289
4290

; TEST TO CHECK THAT MODULE SELECT RAM O AND 1 ARE ACTUALLY SELECTED WHEN
: THE SIGNALS MSELO H AND MSELT M ARE SET TO SELECT THEM. THE TEST WILL

429
429
4294
4295
4296

; IT. THE TEST WILL THEN SELECT MODULE SELECT RAM 1, ADDRESS 0, AND WRITE A DATA
; PATTERN OF 10 INTO IT. THE TEST WILL THEN RESELECT MODULE SELECT RAM O AND
: CHECK THE PATTERN TO BE 1 AND THEN SELECT MODULE SELECT RAM 1 AND CHECK THE
: PATTERN TO BE 10.
oo

4291

4297
«298

6%38
2301

4302
233843

; SELECT MODULE SELECT RAM 0,

013206

013206
013206
013212

013212

004737

T19::

004550

BGNTST

JSR
BGNSEG

104404

ADDRESS O, AND WRITE A DATA PATTERN OF 1 INTO

TRAP

PC,INITMS

sSELECT AND INIT MEMORY SIMULATOR

($BSEG

4305

;SET SIGNAL MSELO H TO A ONE AND SIGNALS MSEL1 H, MSAD17 H AND

l‘.soa

:T0 CgNTROL REGISTER 6.

4306
4307

:MSAD16 H TO A ZERO IN CONTROL REGISTER 2. THE SIGNAL MSELO H ON A
;ONE WILL CAUSE THE SIGNAL SMDSO L TO BE ASSERTED ON A WRITE OR READ

4310

4311 013214 012737 000006 002264
4312 013222 012737 177740 002270

MOV
MOV

4316

TRAP

4313
4314
4315

013230
013234
013236

004737
001405

4317
4318
4319
4320

013240
013242
013244
013246

000002
000000
003712

gg;

013236

013246

005414

JSR
BEQ
ERRDF

104455

.WORD
.WORD
-WORD
CKLOOP

104406

TRAP

4323

4327
4328

4331
4332
4333
433,
3;2

CSERDF

:GO LOAD, READ AND CHECK REGISTER 2
+IF LOADED OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED DATA

2
O
R2EROR

CSCLP1

;BITS 15-13 SELECT MODULE SELECT RAM 0 ADDRESSES.

013250

005037

013254
013260

004737
001405

013262

104455

4329 01326%
4330

PC,LDRDR2
18
2, ,R2EROR

:SETUP TO SET MSELO H TO A 1
:SETUP REGISTER 2 MASK WORD

;CLEAR CONTROL REGISTER & TO SET MODULE SELECT ADDRESSES TO 0. MSAD

ggg

4326

#MSELO,R2LOAD
#177740,R2MASK

THE SIGNAL SMDSO L WILL SELECT MODULE SELECT

013264
013266
013270
013272
013272

002276

18:

005462

CLR

R4LOAD

;SETUP TO CLEAR MSAD BITS 15-0

ERRDF

3, ,R4EROR

*REGISTER 4 NOT EQUAL EXPECTED DATA

JSR
BEQ

TRAP

000003
000000
004000

.WORD
JWORD
.WORD
CKLOOP
TRAP

104406

PC,LDRDRG
28

CS$ERDF

:GO LDAD, READN AND CHECK REGISTER &
*IF LOADED OK THEN CONTINUE

3
0
R4EROR

CSCLP1

4337

;WRITE DATA PATTERN OF 1 INTO MODULE SELECT RAM 0. ON A WRITE OR READ

2;23

;THE SIGNAL SMDSO L SHOULD BE ASSERTED TO SELECT MODULE SELECT RAM 0.

4338

4341

:TO CONTROL REGISTER 6 WITH THE SIGNALS MSELO H A 1 AND MSELT H A 0

013274

012737

177760

002306

2$%:

MOV

#177760,R6MASK

sSETUP REGISTER 6 MASK WORD

SEQ 0C85

HARDWARE TESTS

MACYN

30A(3252)

CVCDAB.P11

17-JUN-82
1

434§
“
6346
6345
6346
4347
4348
4349
4350
4351
435
435
6354
4355
4356
4357
4358
4359
4360
4361
636%
6363
4364
4365
4366
4367
4368
4369
4370
3N
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
438;
4383
4386
4385
4386
4387
4388
4389
4390
4391
4392
4393
6396
4395
4396
4397

012737
004737
001405

013302
013310
013314
013316
013316
013320
013322
013326
013326
013326

000002
005506

17-JUN=-82
12:02 PAGE 86
TEST 19: CHECK MODULE SELECT RAM 0 + 1 CHIP SELECT LOGIC

002302

MOV

#B81T1,R6LOAD

sSETUP DATA PATTERN OF 1

BEQ
ERRDF

3s
& ,MSGMDO,AL INFO

:IF DATA OK THEN CONTINUE
:DATA ERROR IN MODULE SELECT RAM 0

WORD
.WORD
.WORD
CKLOOP
TRAP

&
MSGMDO
ALINFO

JSR

TRAP

104455
000004
002513
004052
104406

PC.LDRDR6

CSERDF

:GO LOAD, READ AND CHECK RAM

CSCLPI

sSET SIGNALS MSELO H AND MSEL1 H TO A ONE AND MSAD BITS 17 AND 16
sTO A O TO SELECT ADDRESS 0. THE SIGNALS SE%
0O H AND MSEL1 H BEING
sSET WILL CAUSE THE SIGNAL SMDS1 L TO BE AS RTED D ON A WRITE OR
L WILL ENABLE MODULE
sREAD TO CONTROL REGISTER 6. THE SIGNAL SMDS 1L
sSELECT RAM 1.,
013330
013336
013342
013344
013344

013346
013350
013352
013354
013354

012737
004737
001405

000014
005414

002264

3$:

MOV
JSR

BEQ

ERRDF

TRAP

1046455
000002
000000
003712

.WORD

-WURD
.WOKD

CKLOOP
TRAP

104406

#MSELO!MSEL1,R2LCAD
PC.LDRDR2

LR2EROR

cienor

sSETUP MODULE SELECT BITS AND ADDRESS
:GO LOAD, READ AND CHECK REG 2

sIF LOADED OK THEN CONT

*REG 2 NOT EQUAL EXPECTED DATA

o
R2EROR
CSCLPI

sWRITE DATA PATTERN OF 10 INTO MODULE SELECT RAM 1. ON A WRITE OR

sREAD TO CONTROL REGISTER 6 WITH THE SIGNALS MSELO H AND MSEL1 W

:gi;.’THE SIGNAL SMDST L SHOULD BE ASSERTED TO SELECT MODE SELECT

013356
013364
013370
013372
013372
0133764
013376
013400
013402
013402

012737
004737
001405

000010
005506

002302

4S:

MoV

#8173,R6LOAD

sSET DATA PATTERN TO 10

BEQ
ERRDF

5%
&, MSGMD1,ALINFO

:IF DATA OK THEN CONTINUE
:DATA ERROR IN MODULE SELECT RAM 1

MORD
.WORD
.WORD
CKLOOP

&
MSGMD1
ALINFO

JSR

TRAP

104455
000004
002555
004052
104406

TRAP

PC.LDRDR6

CSERDF

;GO LOAD, READ AND CHECK DATA

CSCLP1

sRESELECT MODULE SELECT RAM 0 BY SETTING MSELO H TO A ONE AND
IMSELT H TO A O IN CONTROL REGISTER 2.

013404
013412
013416
013420
013420
013422
013424
0134;6
013430

012737
004737
001405

104455

003712

000004
005414

002264

58$:

MOV
JSR

#MSELO,R2LOAD
PC.LDRDR

BEQ

.WORD
-WORD
.WORD

R2EROR

ERRDF

TRAP

R2EROR

ciéaor

sSETUP TO CLEAR BIT MSEL1 H
:GO LOAD, READ AND CHECK REG 2

sIF LOADED OK THEN CONTINUE

:REG 2 NOT EQUAL EXPECTED DATA

SEQ 0086

| WARDWARE TESTS MACY11 somosz)
CVCDAB.P11
17-JUN=-82 11:26

393

013430

17=JUN-82 12:02 PAGE 87
TEST 19: CHECK MODULE SELECT RAM 0 + 1 CHIP SELECT LOGIC

104406

TRAP

4400

mo MODULE SELECT RAM 0 BY READING CONTROL REGISTER 6. ISSUING

4401
440

READ COMMAND WHEN MSELO M IS SET AND MSEL1 H IS CLEARED WILL
ASSERI’ THE SIGNAL SMDSO L. THE SIGNAL SMDSO L BEING ASSERTED WILL
*SELECT MODULE SELECT RAM 0.

22&

4405

013432

012737

000000

4407
4408
4409

omt.g
013452
013454

004737
001405

00552

411
412
4413
4614
4615
we?

013456
013460
013462
013464
013464

000004
002617
004052

002302

4406 013440 013737 oozsog 002304

4610

013454

6$:

104455

013466

4424

104406

013502

013474
013500

012737

004737
001405

000014

005414

002264

7%:

013504
013506
013510
013512

013512

000002
000000
003712

104406

:GO READ AND CHECK RAM LOCATION
:IF DATA OK THEN CONT
:PROBABLY CHIP ENABLE ERROR = MODULE

LWORD
.WORD
.WORD
CKLOOP
TRAP

&
MSGMDC
ALINFO

R6LOAD , R6GOOD
CSERDF

CSCLPY

:SETUP EXPECTED DATA PATTERN

sSELECT RAM

MOV

#MSELO!MSELT,R2LOAD

JSR
BEQ

PC,LDRDR2
as

.WORD
HORD
.WORD
CKLOOP

0
R2EROR

LR2EROR
cimr

:SETUP BITS TO BE LOADED

:GO LOAD, READ AND CHECK REG 2
:IF LOADED OK THEN CONT

*REGISTER 2 NOT EQUAL EXPECTED

CSCLP1

;READ MODULE SELECT RAM 1 BY READING CONTROL REGISTER 6. ISSUING

:A READ COMMAND TO CONTROL REGISTER 6 WITH MSELO M AND MSEL1 W SET

4434

:WILL ASSERT THE SIGNAL SMDST L. THIS SIGNAL BEING ASSERTED WILL

232

:SELECT MODULE SELECT RAM 1.

4437

013514

012737

000010

4639
4640
46461

0135
013534
013536

004737
001404

00552

4443
44kl
444S

013540
0135642
013544

000004
002617
004052

002302

4438 ous% 013737 oozsog 002304
073536

013546

013546
013546
013550

104405

fi.gg

013550

104401

01355(

8$%:

104455

464?
4448
4449
4450

PC.READRG
78
& ,MSGMDC,ALINFO

TRAP

4433

4446

JSR
BEQ
ERRDF

MOV

TRAP

4432

4662

:SETUP PREVIOUSLY LOADED DATA

ERRDF

4425 013502 104455

22?')

#81T1,R6LOAD

nssnscr MODULE SELECT RAM 1 BY SETTING SIGNALS MSELO W AND MSEL1 M
:TO A ONE IN COTROL REGISTER 2.

4421

4426
4427
4428
4429

MOV

TRAP

4418
2233

4622
4423

CSCLPY

MOV

#8173 ,R6LOAD

:SETUP PREVIOUSLY LOADED DATA

JSR
BEQ
ERRDF

PC .READRG
9
& _MSGMDC ,ALINFO

260 READ AND CHECK THE CATA
$IF DATA OK THEN CONT
JPROBABLY CHIP ENABLE ERROR

WORD
.WORD
.WORD

&
MSGMDC
ALINFO

TRAP
ENDTST

CSESEG

TRAP

(SETST

MOV

TRAP

98:

100008:

L10052:

ENDSEG

R6LOAD , R6GOOD
CSERDF

:SETUP EXPECTED DATA

SEQ 0087

17-,UN~-82
12:02 PAGE 88
TEST 20: CHECK EACH ADDRESS IN MOD SEL RAM 0 TO BE ADDRESSED

kS
>

.SBTTL TEST 20: CHMECK EACH ADDRESS IN MOD SEL RAM 0 TO BE ADDRESSED
TEST TO CHECK THAT EACH ADDRESS IN MODULE SELECT RAM 0 CAN BE ADDRESSED
CORRECTLY. THIS IS DONE BY WRITING A SPECIFIC PATTERN INTO THE RAM AND THEN
READING THE RAM CHECKING THAT NO LOCATIONS CHANGED.
THE PATTERNS LOADED

INTO THE RM&SYMHNG AT THE LOWEST ADDRESS, ARE AS FOLLOWS: 10, 04, 02, 01,

004550

BGNTST
JSR
CLR

PC,INITMS
R1

BGNSEG
TRAP

($BSEG

CLR

1%:

sSELECT AND INIT THE MEMORY SIMULATOR
:CLEAR WORKING MSAD BITS

*CLEAR OFFSET TO DATA TABLE

012737

000004
177740
005414

002264

002270

MOV

cns;so R2LOAD

sSETUP TO SET MSELO W TO A 1

JSR
BEQ
ERRDF

PC.LDRDR?
28
2, ,R2EROR

:GO LOAD,READ AND CHECK REG 2
*IF LOADED OK THEN CONTINUE
:REGISTER 2 NOT EQUAL EXPECTED

MOV

TRAP

oo ~NO

ESEES

e
e e o ch e o

COO0O0O0O0O0O0O0O00

;SET SIGNAL MSELO M TO A ONE, AND SIGNALS MSEL1 H, MSAD17 H AND MSAD16 M
:TO A ZERO IN CONTROL REGISTER 2.

.WORD

LWORD
.WORD

(KLOOP
TRAP

#1777460,R2MASK
CS$ERDF

sSETUP REGISTER 2 MASK WORD

O
R2EROR
CSCLPY

sSET MSAD BITS 15-13 I% CONTROL REGISTER 4 TO THE ADDRESS TO BE
sTESTED. MSAD BITS 15-13 ARE USED TO SELECT MODULE SELECT RAM 0

SRR
RS

*ADDRESSES.

§§§&fi£fi8§8

Sssescsee2

2s:

MoV

R1,R4LOAD

:SETUP BITS TO BE LOADED

BEQ
ERRDF

:1F LOADED OK THEN CONTINUE
*REGISTER & NOT EQUAL EXPECTED

JSR

TRAP

.WORD

WORD

noNO

HARDWARE TESTS MACY11 _30A(1052)
17-JUN-82 11:26
CVCDAB L1

‘WORD
(KLOOP
TRAP

PC . LDRDRG

LRGEROR

Sisaor

:GO LOAD, READ AND CHECK REGISTER &

R4EROR
CSCLPY

sTHE FOLLOWING SECTION OF CODE WILL WRITE THE DATA PATTERN INTO RAM
sAND CHECK THAT THE CORRECT PATTERN WAS WRITTEN. ON A WRITE OR READ
sCOMMAND TO CONTROL REGISTER 6 WITH SIGNAL MSELO W SET AND MSEL1 W
:SLEASED. THE SIGNAL SMDSO L WILL BE ASSERTED TO SELECT MODULE SELECY
013644

016237

014040

002302

3s:

MOV

MSRODT (R2) ,R6LOAD

sGET DATA PATTERN FROM TABLE

SEQ 0088

HARDWARE TESTS MACY1 30’(5252)
CVCDAB.P11
17-JUN~82 1

4509 013652 012737

4510
4511
4512

013660
013664
013666

004737
001404

4514
4515
4516
4517
4518
4519
4520

013670
013672
0136764
013676
013676
013676
013700

000004
002513
004052

225

013706 001325

4513

4521

013666

013702

4524

013710

4527

013714

2252

2253

013712

013714

177760

005506

17-JUN=-82
12:02 PAGE 89
TEST 20: CHECK EACH ADDRESS IN MOD SEL RAM O TO BE ADDRESSED

002306

MOV

104455

104405
005722

062701

020000

005002
58:

104404

013716

4536

013732

gz%

013724
013730

013732

01373
013736
013740
013742
013742

012737

004737
001405

000006
005414

002264

:IF NOT O THEN DO NEXT ADDRESS

#MSAD13,R1

CLR

BGNSEG

TRAP

:UPDATE MODULE SELECT RAM 0 ADDRESS
;RESET WORKING MSAD ADDRESSES TO 0

*CLEAR OFFSET POINTER TO DATA TABLE

($BSEG

JSR
BEQ

ERRDF

104455

TRAP

000002
000000
003712

.WORD
WORD
.WORD
CKLOOP
TRAP

104406

#MSELO, R2LOAD
PC,LDRDR2
gs

LR2EROR

CSERDF

:SETUP TO SET MSELO H TO A 1

GO LOAD, READ AND CHECK REG 2
*1F LOADED OK THEN CONTINUE

*REGISTER 2 NOT EQUAL EXPECTED

2
0
R2EROR

CSCLP1

;SET MSAD BITS 15-13 IN CONTROL REGISTER 4 TO THE ADDRESS TO BE CHECKED.

45646 013744
4547
4548
4549

013750
013754
013756

4551
4552
4553
4554

013760
013762
013764
013766

ggg

;UPDATE OFFSET POINTER TO DATA TABLE

ADD

MOV

2§2§

4550

CSESEG
(R2) +

:MSAD16 H. THESE BITS ARE "N CONTROL REGISTER 2.

4533

4538
4539
4540
45641

TRAP
ST

CSERDF

GO LOAD,READ AND CHECK RAM LOCATION
*IF OK THEN CONTINUE
:DATA ERROR IN MODULE SELECT RAM 0

;SET SIGNAL MSELO H TO A ONE AND CLEAR SIGNALS MSEL1 W, MSAD17 H AND

23%3

4537

&
MSGMDO
ALINFO

CLR

4530

453%
4535

MORD
.WORD
.WORD
ENDSEG

BNE

005001

:SETUP REGISTER 6 MASK WORD

PC,LDRDRG
48
& ,MSGMDO,AL INFO

TRAP

48:
100008:

#177760, REMASK

JSR
BEQ
ERRDF

013756

013766

010137 002276
004737
001405

68:

005462

104455

MOV

JSR
BEQ
ERRDF

TRAP

000003
000000
004000

LWORD
WORD
.WORD
CKLOOP

104406

TRAP

R1,R4LOAD
PC . LDRDR4
78
3, ,R4EROR

CS$ERDF

;SETUP BITS TO BE LOADED

:GO LOAD, READ AND CHECK REGISTER 4
:1F LOADED OK THEN CONTINUE
*REGISTER 4 NOT EQUAL EXPECTED

3
0
R4EROR

CSCLPY

4557
4558
4559

;THE FOLLOWING SECTION WILL VALIDATE THAT THE DATA WRITTEN IN THE
;BEGINNING OF THIS TEST REMAINS UNCHANGED. IF AN ERROR OCCURS, THE
:PROBLEM IS PROBABLY INTERNAL TO THE RAM CHIP.
ON A READ COMMAND

ggg

:THE SIGNAL SMDSO L WILL BE ASSERTED TO SELECT MODULE SELECT RAM 0.

4560

4563
4564

:TO CONTROL REGISTER 6 WITH THE SIGNAL MSELO H SET AND MSEL1 W CLEARED,

013770
013776

016237
013737

014040
002302

002302
002304

7$:

MOV
MOV

MSRODT (R2) ,R6LOAD
R6LOAD , R6GOOD

;SETUP PREVIOUSLY LOADED DATA
*SETUP EXPECTED DATA

SEQ 0089

4565
4566
6567
4568
4569
4570
4571
4572
4573
4574

014004
014010
014012
014012
014014
014016
014020
01402
01402
01402

004737
001404

n7
17-JUN-82 12:02 PAGE 90
TEST 20: CHECK EACH ADDRESS IN MOD SEL RAM 0 TO BE ADDRESSED

005522

JSR
BEQ
ERRDF

104455
000004

TRAP

002667
004052

005722
062701
001330

10001$:

4590

014056

4592

014060

4593
4594

014060
014060

& ,MSGMD
AL INFO
A,

Eisnor

(R2)+
#MSAD13,R1
5$
TST
CSEXIT

020000

L1C053:

L10053-.
MSRODT:

;GO READ AND CHECK RAM LOCATION
sIF DATA OK THEN CONTINUE
sMODULE SELECT ADDRESSING ERROR

CSESEG

104432
000022

000010

MSGMDA
ALINFO

8%:

104405

PC,READRG

.WORD
.WORD
«WORD
.WORD
«WORD
«WORD
.WORD

HARDWARE TESTS MACY11 30A(1052)
17-JUN-82 11:26
CVCDAB.P11

ENDTST
TRAP

CSETST

sUPDATE OFFSET POINTER TO DATA TABLE
sUPDATE MODULE SELECT ADDRESS
s IF NOT DONE CHECK NEXT ADDRESS

SEQ 0090

HARDWARE TESTS

CVCDAB.P11

MACY11_30A(1052)
17-JUN-82 1 1:26

17-JUN-82 12:02 PAGE 9
TEST 21: CHECK EACH ADDRESS IN MOD SEL RAM 1 TO BE ADDRESSED

SEQ 0091

.SBTTL TEST 21: CHECK EACH ADDRESS IN MOD SEL RAM 1 TO BE ADDRESSED
‘e

TEST TO CHECK THAT EACH ADDRESS IN MODULE SELECT RAM 1 CAN BE ADDRESSED

¢ CORRECTLY.
THIS IS DONE BY WRITING A SPECIFIC PATTERN INTO THE RAM AND THEN
: READING THE RAM CHECKING THAT NO CHANGES OCCURED. THE PATTERN LOADED INTO
THE RAM, STARTING AT THE LOWEST ADDRESS, ARE AS FOLLOWS: 01, 02, 04,

4607
4608
4609

4612

014
014

014
014
014072

004737
012701
005002

014074

104404

T21::

004550
000014

1$:

10.

BGNTST
JSR
MOV
CLR

PC,INITMS
#MSELO!MSEL1,R1
R2

BGNSEG
TRAP

C$BSEG

sSELECT AND INIT THE MEMORY SIMULATOR
sSETUP BITS FOR CONTROL REGISTER 2
sCLEAR OFFSET POINTER TO DATA TABLE

sSET_SIGNALS MSELO H AND MSELT1 H TO A ONE, SET SIGNALS MSAD 17 AND 16

:TO THE ADDRESS TO BE TESTED.

4617

4618
4619
4620
4621
4622
4623
4624

014076

014102
014110
014114
014116
014116
014120
014122

4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645

014130
014136
014144
014150
014152
014152
014154
014156
014160
014162
014162
014162

4647
4648
4649
4650

014164
014166
014170
014174

4646

014126
014126
014126

010137

012737
004737
001405

002264
177740
005414

MOV

002270

PC,LDRDR2
2
2, .R2EROR

:GO LOAD, READ AND CHECK REGISIER 2
:IF LOADED OK THEN CONTINUE
:REGISTER 2 NOT EQUAL EXPECTED DATA

TRAP

CSERDF

.WORD
JWORD

.WORD

CKLOOP
TRAP

104406

;SETUP BITS TO BE LOADED

#177740,R2MASK

JSR
BEQ
ERRDF

104455
000002
0000
003712

R1,R2L0AD

MOV

*SETUP REGISTER 2 MASK WORD

2
O

R2EROR
CSCLP1

;THE FOLLOWING SECTION WILL WRITE THE DATA PATTERN INTO THE RAM AND
sCHECK THAT THE CORRECT PATTERN WAS WRITTEN. ON A WRITE OR READ COMMAND

:TO CONTROL REGISTER 6 WITH SIGNALS MSELO H AND MSEL1 W SET TO A CNE.

sTHE SIGNAL SMDS! L WILL BE ASSERTED TO SELECT MODULE SELECT RAM 1.

016237
012737
004737
001404

014304
177760
005506

104455
000004
002555
004052

2%:

MOV
MoV
JSR

3s:

100008:

000020

MSRIDT(R2) ,R6LOAD
#177760,R6MASK
PC.LDRDR6

BEQ
ERRDF

& ,MSGMD1,ALINFC

.WORD
.WORD

&
MSGMD1

TRAP

104405

005722
005201
032701
001737

002302
002306

.WORD

ENDSEG

CSERDF

CSESEG

TST
INC

(R2)+
R1
#BIT4,R1

BIT

:1IF DATA OK THEN GO DO NEXT LOCATION
;DATA ERROR IN MODULE SELECT RAM 1

ALINFO

TRAP

BEQ

sGET DATA PATTERN TO BE WRITTEW
sSETUP MASK WORD FOR REGISTER 6
:GO LOAD, READ AND CHECK RAM LOCATION

sUPDATE THE OFFSET POINTER TO DATA TABLE
sUPDATE MSAD BITS

sCHECK IF RAM COMPLETELY WRITTEN
:IF NOT THEN DO NEXT LOCATION

-—-

HARDWARE TESTS MACYN 30?(5252)
CVCDAB.P11
17=JUN=32 1

4652

014176
014202

005002

4655
22%9

016%06
014204

104404

222‘

012701

————
e ———
e

17=JUN=-82
12:02 PAGE 92
TEST 21: CHECK EACH ADDRESS IN MOD SEL RAM 1

000014
4s:

C$BSEG

sRESET BITS FOR CONTROL REGISTER 2

JCLEAR OFFSET POINTER TO DATA TABLE

:TO THE ADDRESS TO BE TESTED.

4661
466§
4663
4664

014206
014312
014216
014220

010137
004737
001405

4666
4667
4668
4669
22;?

0146222
014224
014226
014230
014230

000002

014220

002264
005414

104455

MOV
JSR
BEQ
ERRDF

R1,R2LOAD
PC,LDRDR2
1
2, ,R2EROR

WORD
WORD
.WORD
CKLOOP
TRAP

2
O
RZEROR

TRAP

003712

104406

4672
4673
4674
4675

CSERDF

:SETUP BITS TO BE LOADED
2GO LOAD, READ AND CHECK REGISTER 2
:IF LOADED OK THEN CONTINUE
JREGISTER 2 NOT EQUAL EXPECTED

CS$CLP

sTHE FOLLOWING SECTION WILL VALIDATE THAT THE DATA WRITTEN IN THE
sBEGINNING OF THIS TEST REMAINS UNCHANGED. IF AN ERROR OCCURS, THE
;PROBLEM IS PROBABLY INTERNAL TO THE RAM CHIP.
ON A READ COMMAND
sTO CONTROL REGISTER 6 WITH THE SIGNALS MSELO W AND MSEL1 H SET TO

22;9

A 1, THE SIGNAL SMDS1 L WILL BE ASSERTED TO SELECT MODULE SELECT RAM 1.

4678
4679
4680
4681
4682

014232
0146240
014246
014252
014254

016237
013737
004737
001404

4684
4685
4686
4687
4688
2233

014256
014260
014262
014264
014264
014264

000004
002555
004052

4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702

014266
014270
014272
016%76
014300
014300
014302
014304
014306
014310
014312
014314

005722
005201
032701
001742

4703
4704

BGNSEG
TRAP

TO BE ADDRESSED

sSET SIGNALS MSELO H AND MSEL1 H TO A ONE. SET MSAD BITS 17 AND 16

2228

4683

#MSELO!'MSEL1,R1

CLR

4658

4665

MoV

— ———
e

014254

014314
014314

014304
002305
00552

002302
002304

S%:

104455

104401

MSR1DT(R2) .R6LOAD
R6LOAD ,R6GOOD
PC,READRG
6$
& ,MSGMD1,ALINFO

LWORD
.WORD
.WORD
ENDSEG

&
MSGMD1
ALINFO

TRAP

CSESEG

TRAP

6$:
10001$:

104405

104432
000012
000001
000002
000004
000010

MOV
MOV
JSR
BEQ
ERRDF

000020

ST
INC
BIT
BEQ
EXIT
TRAP
.WORD
MSR1DT: .WORD
WORD
WORD
.WORD
ENDTST

L10054:

TRAP

CSERDF

(R2)+
R1
#8IT4 R
43
ST
CSEXIT
L10054~.
1
2
&
10

CSETST

:SFTUP DATA PRFVIOUSLY WRITTEN
:SETUP EXPECTED DATA PATTERN
;GO READ THE RAM LOCATION
:1F DATA OK THEN CONTINUE
:MODULE SELECT RAM 1 ADDRESSING ERROR

s INCREMENT OFFSET POINTER TO DATA TABLE
sUPDATE MSAD BITS 17 AND 16
sCHECK IF DONE
:IF NOT CHECK NEXT ADDRESS

-9

SEQ 0092

HARDWARE TESTS MACY11_30A(1052)
CVCDAB.P11
:
17=JUN-8 2 11:26

17-JUN-82

12:02

TE ST 22:

PAGE 93

CHECK MEM SIM RAM'S WITH 1°S + 0°'S, AND 0°'S + 1°S.

oS BTTL TEST 22: CHECK MEM SIM RAM'S WITH 1°'S + 0'S, AND 0°'S + 1°S.
* 4+

TEST TO CHECK THAT A&L MEMORY SIMULATOR RAM'S CAN BE WRITTEN AND READ WITH

DATA PATTERN'S 125252

AND 052525. THIS TEST CHECKS THAT ALL BITS CAN BE

WRITTEN TO A ONE AND ZERO AND THAT NO ADJACENT BITS ARE SHORTED TO EACH OTHER.
THIS TEST IS EXECUTED IN 16 BIT MODE.
THIS TEST, HOWEVER, DOES NOT CHECK FOR

INTERNAL ADDRESS SHORTS, ADDRESS BIT DROP OUT, OR THAT THE CORRECT RAM IS

SELECTED.
NOTE:

THE TEST THAT FOLLOW THIS TEST WILL PERFORM THE ABOVE CHECKS.

2ND 4K OF RAM - ADDRESSES 020000 - 037777
SRD 4K OF RAM - ADDRESSES 040000 - 057777

PO
= =

OO000O0

4TH 4K OF RAM - ADDRESSES 060000 - 077777

004737
005037
012701

004550
002276
000001

1$:

104404

BGNTST
JSR
CLR
MOV

PC,INITMS
R4LOAD
#81T0,R1

BGNSEG
TRAP

C$BSEG

;SELECT AND INIT MEMORY SIMULATOR
*SET 1ST ADDRESS TO BE TESTED TO 0
:SETUP DATA FOR MODULE SELECT RAM 0

;SET SIGNAL MSELO H TO A ONE AND CLEAR SIGNALS MSEL1 H, MSAD17 H AND
:MSAD16 H IN CONTROL REGISTER 2. MSELO H ON A ONE AND MSEL1 H ON
:A ZERO WILL CAUSE THE SIGNAL SMDSO L TO BE ASSERTED ON A WRITE OR
:READOCOHHAND TO CONTROL REGISTER 6. SMDSO L WILL SELECT MODULE SELECT
002264

MOV

#MSELO,R2LOAD

:SETUP BITS TO BE LOADED

JSR
BEQ
ERRDF

PC.LDRDR?
28
2, .R2EROR

:GO LOAD,READ AND CHECK REG 2
:IF LOADED OK THEN CONT
*REGISTER 2 NOT EQUAL EXPECTED

MOV

002270

b el

000004
177740
005414

d ed oD

TRAP

#177740,R2MASK
CSERDF

WORD
WORD
.WORD

2
O
R2EROR

TRAP

CS$CLP1

CKLOOP

:SETUP REGISTER 2 MASK WORD

;LOAD THE ADDRESS TO BE TESTED INTO CONTROL REGISTER 4. THE ADDRESS
:WILL APPEAR ON MSAD BITS 15-0 WHICH IS THE OUTPUT OF CONTROL REGISTER &

004737
001405
104455

000003

005462

2%:

JSR
BEQ
ERRDF
TRAP

WORD

PC,LDRDR4

g
3, ,RLTROR
(SERDF

;G0 LOAD,READ AND CHECK REGISTER &

*IF LOADED OK THEN CONTINUE
*REGISTER 4 NOT EQUAL EXPECTED

SEQ 0093

HARDWARE TESTS

CVCDAB.P11

30A(1252)

17=JUN=82 11:2

4762
4763
4764
4765
4766
4767
4768
4769
4770
477
4772
4773

014410

010137

002302

4775
4776
4777

014422
014426
014430

004737
001405

005506

4779
4780
4781
4782
4783

014432
014434
014436
014440
014440

000004
002513
004052

4774

4778

4784
4785
4786
4787
4788

014402
014406
014406
014406

MACY11

000000
004000

LWORD
.WORD
CKLOOP

104406

TRAP

SEQ 0094

O
R4EROR
CSCLP1

;WRITE THE DATA PATTERN INTO MODULE SELECT RAM O AND CHECK THAT IS WAS
sWRITTEN CORRECTLY. THE DATA PATTERNS THAT WILL BE WRITTEN ARE 1, 2, 4,

:10.

THESE PATTERNS WILL ENABLE THE SIGNALS ENO H, EN1 H, EN2 H, AND

;EN3 H RESPECTIVELY. THESE SIGNALS ARE USED TO SELECT MEMORY SIMULATGR
¢MEMORY WHEN THE SIGNAL SSM L IS ASSERTED LATER ON IN THE TEST.

014414

014430

012737

177760

MOV

002306

MOV

104455

R1,R6LOAD

#177760,R6MASK

JSR
BEQ
ERRDF

PC,LDRDRé
48
4 ,MSGMDO,AL INFO

WORD
.WORD
.WORD
CKLOOP
TRAP

&
MSGMDO
ALINFO

TRAP

104406

CSERDF

sGET THE PATTERN TO BE LOADED
sSETUP REGISTER 6 MASK WORD
:GO LOAD, READ AND CHECK RAM 0
sIF OK _THEN CONTINUE
sDATA ERROR IN MODULE SELECT RAM 0

CSCLP1

sSET SIGNALS MSELO H AND MSEL1 H TO A ONE AND SIGNALS MSAD17 H AND MSAD16 H
:TO A ZERO IN CONTROL REGISTER 2. MSELO H AND MSEL1 H ON A ONE, WILL
;CAUSE THE SIGNAL SMDS1 L TC BE ASSERTED ON A WRITE OR READ TO CONTROL
;REGISTER 6. SMDS1 L WILL SELECT MODULE SELECT RAM 1. MSAD BITS 17 AND 16
;ON A ZERO WILL SELECT ADDRESS O OF MODULE SELECT RAM 1.

4791
4792
4793
4796

014442
014450
014456
014456

012737
004737
001405

4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812

014460
014462
014464
014466
014466

000002
000000
003712

4814
4815
4816
4817

014514
014516
014520
014522

4795 014456

4813

17-JUN=-82 12:02 PAGE 94
TEST 22: CHECK MEM SIM RAM'S WITH 1°S + 0°'S, AND 0°'S + 1°S.

000014
005414

002264

4$:

104455

MOV
JSR
BEQ
ERRDF

TRAP

.WORD
WORD
-WORD
CKLOOP
TRAP

104406

#MSELO!MSEL1,R2LOAD
PC,LDRDR2
13
2, ,R2EROR

CSERDF

sSETUP BITS TO BE LOADED
;GO LOAD, READ AND CHECK REGISTER 2
sIF LOADED OK THEN CONTINUE
sREGISTER 2 NOT EQUAL EXPECTED

O
R2EROR
CSCLP1

sWRITE THE DATA PATTERN INTO MODULE SELECT RAM 1 AND CHECK THAT THE
sPATTERN WAS LOADED CORRECTLY. A DATA PATTERN OF ALL ONES WILL BE

SWRITTEN, HOWEVER, WHEN THE LOCATION IS READ BACK, A DATA PATTERN
sEQUAL TO ONE WILL BE READ. SETTING THE LEAST SIGNIFICANT BIT IN
:THE DATA PATTERN WILL FORCE THE MORE SIGNIFICANT BITS TO ZERO.

014470
014476
014506

014510

014512

012737
012737
004737
001404

000017
000001
005514

002302
002304

5$:

BEQ

ERRDF

104455

0000
002555
052

MOV
MOV
JSR

TRAP

68:

WORD
-WORD
.WORD
ENDSEG

#BIT3!BIT2!BIT1!BITO,R6LOAD ;GET DATA PATTERN TO BE LOADED
#81T0,R6GOOD
sSETUP EXPECTED DATA PATTERN
PC,LDRD6R
:GO LOAD ,READ AND CHECK RAM 1
6
sIF DATA OK THEN CONTINUE
& ,MSGMD1,ALINFO
:DATA ERROR IN MUDULE SELECT RAM 1

CSERDF

&
MSGMD1
ALINFO

HARDWARE TESTS MACY11 30?(5252)
CVCDAB.P11
17=JUN=-82 1

4818
23}3

014522
014522

104405

23512 0145264

012702

4823
23545.

104404

014530
014530

17-JUN=-82
12:02 PAGE 95
TEST 22: CHECK MEM SIM RAM'S WITH 1°S + 0°S, AND 0°S + 1°S.

100008:

010000
78:

4826

TRAP

CSESEG

MOV

#4096. ,R2

BGNSEG
TRAP

($BSEG

;SETUP 4K WORD COUNTER TO DO 1 RAM

;CLEAR BITS MSELO W, MSEL1 W, MSAD17 M AND MSAD16 W IN CONTROL REGISTER

4827

:2. MSELO H AND MSEL1 M ON A ZERO WILL CAUSE THE SIGNAL SSM L TO BE

4830

;SIMULATOR RAM SELECTED. THE SIMULATOR MEMORY IS SELECTED VIA THE

4828
4829

:ASSERTED ON A WRITE OR READ TO CONTROL REGISTER 6. ON A WRITE OR READ
:TO CONTROL REGISTER 6, DATA WILL BE WRITTEN OR READ FROM THE MEMORY

23;3

*MODULE SELECT RAM'S (0 AND 1).

4833
4834
4835
4836

014532
014536
014542
014544

005037
004737
001405

4838
4839
4840
4841
2%

014546
014550
014552
014554
014554

000002
000000
003712

4837

014544

002264
005414

104455

104406

014556
014562
014564

004737
001405

4850
4851
4852
4853
ggg

014566
014570
014572
014574
014574

000003
000000
004000

014564

005462

8s:

104455

104406

014576
014604

012737
005037

4864

014614

001405

4873

JSR
BEQ
ERRDF

PC,LDRDRG
98
3, ,R4EROR

.WORD
WORD
.WORD
CKLOOP
TRAP

3
0
R4EROR

CSERDF

;GO LOAD,READ AND CHECK REGISTER 4
:1F LOADED OK THEN CONTINUE
*REGISTER 4 NOT EQUAL EXPECTED

CSCLPY

:SIMULATOR RAM TO BE WRITTEN OR READ.

4861
4

4867
4868
4869
4870
23;}

CSCLP1

;LOAD DATA PETTERN 125252 INTO MEMORY SIMULATOR RAM. ON A WRITE OR
;READ TO CONTROL REGISTER 6, Th. SIGNAL SSM L WILL BE ASSERTED. THIS
;SIGNAL WILL ENABLE BOTH MODULE SELECT RAMS AND ENABLE THE MEMORY

2323

4866

2
0
R2EROR

TRAP

4856
4857
4858

4865

JWORD
WORD
"WORD
CKLOOP
TRAP

CSERDF

;SETUP TO CLEAR REGISTER 2
:GO LOAD, REAP «ND CHECK REG 2
*IF LOADED OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

:LOAD MEMORY SIMULATOR ADDRESS TO BE TESTED INTO CONTROL REGISTER &

4846
4847
4848

4863

R2LOAD
PC,LDRDR2
13
2, ,R2EROR

TRAP

231;3

4849

CLR
JSR
BEQ
ENRDF

014610
014616

014616

014620
014622
014624
014626
014626

004737

104455

000004
002732
004052

104406

125252
002306

005506

002302

9%:

MOV
CLR

#125252,R6LOAD
RGMASK

BEQ

108

JSR

PC,LDRDR6

ERRDF

& MSGMSR,ALINFO

WORD
.WORD
-WORD
CKLOOP

&
MSGMSR
ALINFO

TRAP

CSERDF

;SETUP DATA PATTERN TO BE LOADED
:SETUP TO CMECK ALL 16 BITS OF RAM

:GO LOAD, READ AND CHECK RAM LOCATION

:IF DATAOK THEN GO COMPLEMENT IT

:DATA ERROR IN MEMORY S!MULATOR RAM

(S$CLPY

sLOAD DATA PATTERN 052525 INTO SAME MEMCRY SIMULATOR RAM LOCATION

SEQ 0095

HARDWARE TESTS MACY11 30A(1052)
CVCDAB.P11
17-JUN-82 11:26

2g;g
4876

4877

;AND CHECK THAT IT WAS LOADED CORRECTLY
014630

014636

012737

004737

4878 014642 001404
4879 014644
4880 014644 104455

4881
4882
4883
4884
4885

4‘.%

014646
014650
014652
014654
014654

014654

052525

005506

002302

000004
002732
004052

233

104405

014656
014664

014666

062737
005302

000002

001320

DR6

11!
MSGMSR, AL INFO
cimr

WORD
.WORD
.WORD
ENDSEG

&
MSGMSR
ALINFO

TRAP

CSESEG

:SETUP DATA PATTERN TO BE LOADED

:GO LOAD, READ AND CHECK RAM LOCATICN

+IF DATA OK THEN CONTINUE

:DATA ERROR IN MEMORY SIMULATOR RAM

002276

ADD
DEC

#2 ,R4LOAD
R2

:UPDATE ADDRESS BY 2
:DECREMENT 2K WORD COUNTER

:IF NOT DONE DO NEXT ADDRESS

sSELECT RAM 0 ON NEXT PASS OF THIS TEST

014670

006301

4899

014672

032701

000020

4901

014700

000137

014332

4904

BEQ
ERRDF
TRAP

noszszs R6LOAD

;UPDATE MODULE SELECT RAM ENABLE BITS TO BE LOADED INTO MODULE

4897

6902
4903

JSR

BNE

2332

4900

MOV

;UPDATE MEMORY SIMULATOR ADDRESS TO NEXT ADDRESS TO BE LOADED

489

4898

108:

11$:
100018
:

zggg
4890
4891

17-JUN-82
12:02
PAGE 96
TEST 22: CHECK MEM SIM RAM'S WITH 1°'S + 0°'S, AND 0°S + 1°S.

014676

014704
014704
014704

001002

104401

ASL

BIT

#B8IT4,R1

JMP

TRAP

CSETST

BNE

12%:
ENDTST
L10055:

128

:MOVE MODULE SELECT RAM O DATA PATTERN

SLEFT TO ENABLE NEXT MEMORY SIMULATOR RAM

:CHECK IF ALL RAMS HAVE BEEN TESTED
:IF YES THEN EXIT THE TEST
:OTHERWISE DO NEXT RAM

SEQ 0096

| WARDWARE TESTS

| CVCDAB.P11

MACY.1

30A(3252)

17=JUN-82
1

17-JUN-82

1 :02 PAGE 97
TEST 23: CHECK MEM SIM RAM'S CHIP SELECT LOGIC

+
*

.SBTTL TEST 23: CHECK MEM SIM RAM'S CHIP SELECT LOGI(
THIS TEST WILL CHECK THAT EACH MEMORY SIMULATOR RAM IS SELECTED BY WRITING
A DIFFERENT PATTERN INTO LOCATION O OF EACH RAM, THE TEST WILL THEN READ

LOCATION O OF EACH RAM CHECKING THE DATA PATTERN TO BE THAT WHICH WAS

WRITTEN PREVIOUSLY. IF
A DATA ERROR OCCURS DURING THE RE-READING OF THE
RAM'S, THE RAM SELECT LOGIC IS PROBABLY AT FAULT. THE DATA PATTERNS HRIYYEN
INTO MEMORY SIMULATOR RAM'S 0, 1% 2, AND 3 ARE 11111, 22222, 33333,
44444 RESPECTIVELY.
NOTE:

014706
014706
014706

004737

004550

014712
014716
014722

005037
012701
012702

002276
000001
o1

014726
014726

104404

T23::

1$:

WHEN AN ERROR OCCURS, THE INFORMATION PROVIDED IN CONTROL REGISTER &
INDICATES THE ADDRESS BEING TESTED AND THE RAM BEING SELECTED.
THE
TABLE BELOUOINgzfiATES THE 4K RAM SELECTED
Fg; THE ADDRESSES IN ERROR.
1ST &
ADDRESSES 000000 - 017
2ND 4K OF RAM
ADDRESSES 020000 - 037777
3RD 4K OF RAM
ADDRESSES 040000 - 057777
4TH 4K OF RAM
ADDRESSES 060000 - 077777

BGNTST
JSR

PC,INITMS

sSELECT AND INIT MEMORY SIMULATOR

CLR
MoV
MOV

R4LOAD

sSET 1ST ADDRESS TO BE TESTED T0 0
sSETUP DATA FOR MODULE SELECT RAM 0
sSETUP DATA PATTERN FOR MEM SIM RAM 0

BGNSEG
TRAP

#8IT0,R1

#11111,R2
C$BSEG

sSET SIGNAL MSELO H TO A ONE AND CLEAR SIGNALS MSEL1 H, MSAD17 H AND
:MSAD16 H IN CONTROL REGISTER 2. MSELO H ON A ONE AND MSEL1 H ON
¢A ZERO WILL CAUSE THE SIGNAL SMDSO L TO BE ASSERTED ON A WRITE OR

000004
177740
005414

002264
002270

MOV

cieaor

14756

#MSELO,R2LOAD

#177740, RIMASK
PC,LDRDR?2
2s

&~
~

OOOOOSOOOOO

RE;DOCOHHAND TO CONTROL REGISTER 6.

000000
003712

LR2EROR

;SETUP BITS TO BE LOADED
sSETUP REGISTER 2 MASK WORD
:GO LOAD,READ AND CHECK REG 2
:IF LOADED OK THEN CONT
sREGISTER 2 NOT EQUAL EXPECTED

CKLOOP

104406

TRAP

R2EROR

cscLP1

sLOAD THE ADDRESS TO BC
4960
4961

SMDSO L WILL SELECT MODULE SELEC!

[ESTED INTO CONTROL REGISTER &. THE ADDRESS

:WILL APPEAR ON MSAD BITS 15-0 WHICH
I
IS THE OUTPUT OF CONTROL REGISTER &
:THE ADDRESSES TO BE TESTED ARE 000000, 020000, 040000, AND 060000.

014764

004737

005462

2%:

JSR

PC.LDRDR4

:GO LOAD,READ AND CHECK REGISTER &

SEQ 0097

p——

m—

——

. HARDWARE TESTS

. CVCDAB.P11

i
|

496
&

4965

014770
014772
014772

MACY11 30A(1052)
17=JUN-821 1:26

17=JUN=-82
12:02 PAGE 98
TEST 23: CHECK MEM SIM RAM'S CHIP SELECT LOGIC

001405

BEQ

104455

TRAP

gisaor

ERRDF

000003
000000
004000

.WORD
WORD
.WORD
CKLOOP
TRAP

104406

LRGEROR

:1F LOADED OK THEN CONTINUE

*REGISTER 4 NOT EQUAL EXPECTED

O
R4EROR
CSCLPI

;WRITE THE DATA PATTERN INTO MODULE SELECT RAM O AND CHECK THAT IT WAS
sWRITTEN CORRECTLY. THE DATA PATTERNS THAT WILL BE WRITTEN ARE 1, 2, &,
:10, THESE PATTERNS WILL ENABLE THE SIGNALS ENO H, EN1 H, EN2 H, AND

sEN3 H RESPECTIVELY. THESE SIGNALS ARE USED TO SELECT MEMORY SIMULATOR
sMEMORY WHEN THE SIGNAL SSM L IS ASSERTED LATER ON IN THE TEST.
002302

177760

005506

MOV

002306

JSR
BEQ
ERRDF

TRAP

WORD
.WORD
.WORD
CKLOOP

TRAP

R1,R6LOAD

:GET THE PATTERN TO BE LOADED

PC.LDRDRG
4
& ,MSGMDO,AL INFO

:GO LOAD, READ AND CHECK RAM 0
:IF OK THEN CONTINUE
:DATA ERROR IN MODULE SELECT RAM 0

#177760,R6MASK
CSERDF

:SETUP REGISTER 6 MASK WORD

&
MSGMDO
ALINFO
CSCLP1

;SET SIGNALS MSELO H AND MSEL1 H TO A ONE AND SIGNALS MSAD17 H AND MSAD16 H
:TO A ZERO IN CONTROL REGISTER 2. MSELO H AND MSELT H ON A ONE. WILL
;CAUSE THE SIGNAL SMDS1 L TO BE ASSERTED ON A WRITE OR READ TO CONTROL
;REGISTER 6. SMDS1 L WILL SELECT MODULE SELECT RAM 1. MSAD BITS 17 AND 16
;ON A ZERO WILL SELECT ADDRESS O OF MODULE SELECT RAM 1.
012737
004737
001405

000014
005414

002264

4S$:

MOV
JSR

BEQ
ERRDF

TRAP

104455
000002
000000
003712

WORD
WORD
.WORD
CKLOOP

104406

TRAP

#MSELO!MSEL1,R2LOAD
PC,LDRDR2

58
2, ,R2EROR

C$ERDF

;SETUP BITS TO BE LOADED
:GO LOAD, READ AND CHECK REGISTER 2
+IF LOADED OK THEN CON:INUE
:REGISTER 2 NOT EQUAL EXPECTED

2
O
R2EROR
CSCLP1

sWRITE THE DATA PATTERN INTO MODULE SELECT RAM 1 AND CHECK THAT THE
sPATTERN WAS LOADED CORRECTLY. A DATA PATTERN OF ALL ONES WILL BE

—

OCOO00O0O0

SWRITTEN, HOWEVER, WHEN THE LOCATION IS READ BACK, A DATA PATTERN
sEQUAL TO ONE WILL BE READ. SETTING THE LEAST SIGNIFICANT BIT IN
sTHE DATA PATTERN WILL FORCE THE MORE SIGNIFICANT BITS TO ZERO.
000017
000001
005514

002302
002304

58%:

MOV
MOV
JSR
BEQ
ERRDF

TRAP

#81T3!BIT2!BIT1!BITO,R6LOAD ;GET DATA PATTERN TO BE LOADED
#8170,R6GOOD
sSETUP EXPECTED DATA PATTERN
PC.LDRD6R
;GO LOAD,READ AND CHECK RAM 1
63
:IF DATA OK THEN CONTINUE
& _MSGMD1,ALINFO
:DATA ERROR IN MODULE SELECT RAM 1

CS$ERDF

SEQ 0098

HARDWARE TESTS MACYN 30?(1052)
CVCDAB.P1T
17-JUN=-82 11:26

5018
5019
5020
5021
ggzg

015110
015112
015114
015116
015116

000004
002555
004052

MORD
.WORD
-WORD
CKLOOP
TRAP

104406

5024
5025
5026
5027
5028

5032
5033
503,

5025

5036
5037
5038
5039
g&?

015120 005037 002264
015124
015130
015132

015132

015134
015136
015140
015142
015142

004737
001405

68:

005414

104455

JSR
BEQ
ERRDF
MORD
WORD
.WORD
CKLOOP
TRAP

000000
003712

104406

R2LOAD

PC.LDRDR2
7$
2, ,R2EROR

CSERDF

:SETUP TO CLEAR REGISTER 2

:G0 LOAD, READ AND CHECK REG 2
*IF LOADED OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

O
R2EROR

CSCLP1

:LOAD DATA PATTERN INTO MEMORY SIMULATOR RAM AND CHECK THAT THE CORRECT
;PATTERN WAS LOADED. THE SIGNAL SSM L WILL BE ASSERTED. THIS SIGNAL
;WILL ENABLE BOTH MODULE SELECT RAMS AND ENABLE THE MEMORY SIMULATOR RAM
:TO BE WRITTEN OR READ.

5047 015144 010237 002302
5048 015150 005037 002306
5049
5050
5051

015154
015160
015162

004737
001404

5053
5054
5055
5056
5057
gggs

015164
015166
015170
015172
015172
015172

000004
002732
004052

5060

015174

006301

soog

015204

062702

015162

015176

78:

005506

104455

5067 015222
gggg 015226

MOV
CLR

8s:
100008:

104405

062737 020000

PC,LDRDR6
8s
& ,MSGMSR,ALINFO

MORD
.WORD
.WORD
ENDSEG

&
MSGMSR
ALINFO

TRAP

CSESEG

011111

ASL

002276

005037 002276
012702 011111

5070
gg;;

CSERDF

:SETUP DATA PATTERN TO BE LOADED
*SET MASK WORD TO 0

:GO LOAD, READ AND CHECK RAM LOCATION
:IF DATA OK THEN CONT iNUE
:DATA ERROR IN MEMORY SIMULATOR RAM

;UPDATE MODULE SELECT RAM 0°'S DATA

#1111.R2

SUPDATE DATA PATTERN FOR NEXT RAM

ADD

#MSAD 13, R4LOAD

8IT
BNE
JMP

#8174 R
98
1

SCHECK IF ALL & RAM'S WRITTEN
*IF YES THEN GU READ THEM AGAIN
:G0 WRITE ADDRESS O GF NEXT RAM

R4LOAD
#11111,R2

;RESET ADDRESS TO ADDRESS 0
SRESET DATA PATTERN

ADD

98:

R2,R6LOAD
RGMASK

JSR
BEQ
ERRDF

TRAP

5063 015210 032701 000020
5064 015214 001002
gggg 015216 000137 014726

5073

CLR

TRAP

2&42

5061

CSCLPI

*MODULE SELECT RAM'S (0 AND 1).

5042
5043
5044

5052

&
MSGMD1
ALINFO

;CLEAR BITS MSELO H, MSEL1 H, MSAD17 H AND MSAD16 W IN CONTROL REGISTER
:2. MSELO M AND MSEL1 H ON A ZERO WILL CAUSE THE SIGNAL SSM L TO BE
;ASSERTED GN A WRITE OR READ TO CONTROL REGISTER 6. ON A WRITE OR READ
:TO CONTROL REGISTER 6, DATA WILL BE WRITTEN OR READ FROM THE MEMORY
;SIMULATOR RAM SELECTED. THE SIMULATOR MEMORY IS SELECTED VIA THE

33233

5031

17-JUN=-82
12:02 PAGE 99
TEST 23: CHECK MEM SIM RAM'S CHIP SELECT LOGIC

CLR
MOV

*UPDATE ADDRESS TO ADDRESS O OF NEXT RAM

;THE FOLLOWING SECTION OF CODE WILL READ ADDRESS O OF EACH RAM AND

;CHECK THAT THE DATA PATTERNS WRITTEN PREVIOUSLY REMAIN UNCHANGED.

015232

108:

BGNSEG

SEQ 0099

HARDWARE TESTS

CVCDAB.P11

33;'5'

015232

MACY11 30A(1052)

17=JUN~-82 11:26

17-JUN-82

12:02

PAGE 100

TEST 23: CHECK MEM SIM RAM'S CHIP SELECT LOGIC

104404

TRAP

SEQ 0100

($BSEG

5076

;CLEAR BITS MSELO W, MSEL1
H, MSAD17 H AND MSAD 16 M IN CONTROL REGISTER

5078
g%

*ASSERTED ON A READ COMMAND TO CONTROL REGISTER 6. THE su;m SSM L
:WILL ENABLE THE SIMULATOR RAM MEMORY'S TO BE READ.

5077

MSELO H AND MSEL1 H ON A ZERO WILL CAUSE THE SIGNAL SSML TO BE

5081
5082

015234
015240

5084

015246

5083

015244

005037
004737

001405

002264
005414

CLR
JSR

BEQ

ERRDF

5085 015246 104455

5086

015250

5088
5089
ggg?

015254
015256
015256

5087 015252

000002

003712

ggg%
015260

5096

015266

5098

015270

000003

5100
5101
g}gg

015274
015276
015276

004000

015264

004737

001405

005462

118:

5097 015266 104455
104406

sREGISTER 2 NOT EQUAL EXPECTED

CSCLP1

PC,LDRDRG

ERRDF

TRAP

cimr

-WORD

12§

,R4EROR

;G0 LOAD,

READ AND CHECK REGISTER 4

*IF LOADED OK THEN CONTINUE

*REGISTER 4 NOT EQUAL EXPECTED

R4EROR
CSCLPI

;READ MEMORY SIMULATOR RAM AND CHECK THAT THE DATA PREVIOUSLY WRITTEN

g}os

5189 015300 010237 002302

5108 015304 013737 002302
5109 015312 005037 002306
5110

015316

5112

015324

015322
015324

004737

001404

015326
015330
015332
015334
015334
015334

000004
002775
004052

§121

015336

062702

5123
5124
5125
ggg

015350
015352
015352
015352

100330

015342

002304

128:

005522

104401

MOV

R2,R6LOAD

JSR

PC ,READRG

MOV
CLR

138:
10001$:
011111

020000

002276

:SETUP EXPECTED DATA
:CLEAR THE MASK WORD

13§

*IF DATA OK THEN CONTINUE

*READ AND CHECK RAM LOCATION

& ,MSGMSC,ALINFO

WORD
"WORD
.WORD
ENDSEG

&
MSGMSC
ALINFO

TRAP

CSESEG

ADD

#11111,R2

;UPDATE DATA PATTERN

BPL
ENDTST

108

:G0 CHECK NEXT ADDRESS IF NOT DPSNE

ADD

L10056:

:SETUP DATA PREVIOUSLY WRITTEN

R6LOAD , R6GOOD
RGMASK

ERRDF

TRAP

104405

062737

:DID NOT CHANGE.

BEQ

104455

5114
5115
5116
5117
5118
;}53

512§

+IF LOADED OK THEN CONTINUE

R2EROR

JSR

BEQ

.WORD
CKLOOP
TRAP

5104

5113

.WORD

5099 015272 000000

5111

-WORD

;CLEAR ALL BITS IN CONTROL REGISTER 2
:G0 LOAD, READ AND CHECK REGISTER 2

;LOAD ADDRESS O OF THE RAM TO BE TESTED INTO CONTROL REGISTER 4.

5094

5095

.R2EROR

cimr

"WORD
CKLOOP
TRAP

104406

11£

TRAP

.WORD

000000

R2LOAD
PC,LDRDR2

TRAP

CSERDF

#MSAD13,R4LOAD
CSETST

:CHIP ENABLE ERROR = MEM SIM RAM

*UPDATE ADDRESS TO O OF NEXT RAM

. HARDWARE TESTS
CVCDAB.P11

17=JUN-82 11:26

17-JUN-82

SEQ 0101

+
*

LB SR IS GRELSE RIS ar IRy

«SBTTL TEST 24: CHECK EACH ADDRESS OF MEM SIM RAM TO BE ADDRESSED

i i i i i T AV A VA A VA AN

PAGE 101

) il

TEST TO CHECK THAT EACH ADDRESS OF THE MEMORY SIMULATOR CAN BE ADDRESSED

CORRECTLY AND THAT NO ADDRESSES ARE SHORTED TOGETHER. TO DO THIS,

THE

PROGRAM WRITES EACH LOCATION OF THE MEMORY SIMULATOR RAM WITH DATA EQUAL

) D

) e

) D e

TO THE_ADDRESS OF THE LOCATION, AS EACH LOCATION IS WRITTEN THE PROGRAM
READS THE LOCATION AND CHECKS THAT THE LOCATION IS WRITTEN CORRECTLY. WHEN
ALL MEMORY SIMULATOR R2TM LOCATIONS HAVE BEEN WRITTEN, THE PROGRAM WILL REREAD THME RAMS CHECKING THAT ALL LOCATIONS CONTAIN AS DATA THEIR ADDRESS.
THE PROGRAM WILL THEN RESET THE POINTER TO THE BEGINNING ADDRESS OF THE
RAM'S AND DO THE FOLLOWING:
1. READ THE LOCATION AND CHECK THAT IT CONTAINS ITS ADDRESS

D D il

2. WRITE THE LOCATION WITH THE ONE'S COMPLEMENT OF THE ADDRESS AND CHECK
THAT THE ONES COMPLEMENT CAN BE READ BACK

3. REPEAT STEPS ONE AND TWO FOR EACH ADDRESS OF THE RAM.

d wd

THE TEST WILL THEN RESET THE ADDRESS POINTER TO THE BEGINNING ADDRESS OF

239&2?2 CHECK EACH LOCATION OF THE RAM TO CONTAIN THE ONES COMPLEMENT OF

THE

ITS

NOTE:

159
1
161
162
}
165

}

QRRROR LB SR IRV AU

i anaiianain
Vi
i
it it i

1
1
1
1
}

015354
015354
015354
015360
015364
015370

015370

004737
005037
012701

T24::

004550
002276
000001

18:

104404

JSR
CLR
MOV
BGNSEG

TRAP

PC, INITMS
R4LOAD
#81T0,R1

;SELECT AND INIT MEMORY SIMULATOR
:SET 1ST ADDRESS TO BE TESTED TO 0
:SETUP DATA FOR MODULE SELECT RAM 0

($BSEG

:MSAD16 H IN CONTROL REGISTER 2. MSELO H ON A ONE AND MSEL1 H ON
;A ZERO WILL CAUSE THE SIGNAL SMDSO L TO BE ASSERTED ON A WRITE OR
:READOCOHHAND TO CONTROL REGISTER 6. SMDSO L WILL SELECT MODULE SELECT

015372

012737

000004

176

015406

004737

005414

178

015414

180
181
182
183

015416
015420
015422
015424

179

BGNTST

;SET SIGNAL MSELO W TO A ONE AND CLEAR SIGNALS MSEL1 H. MSAD17 H AND

174

177

INFORMATION PROVIDED IN CONTROL REGISTER &

4TH 4K OF RAM - ADDRESSES 060000 - 077777

169
170
};}

175

THE

2ND 4K OF RAM - ADDRESSES 020000 - 037777
3RD 4K OF RAM - ADDRESSES 040000 - 057777

168

173

WHEN AN ERROR OCCURS,

INDICATES THE ADDRESS BE!NG TESTED AND THE RAM BEING SELECTED.
THE
TABLE BELOW INDICATES THE 4K RAM SFLECTED _FOR THE ADDRESSES IN ERROR.
1ST 4K OF RAM - ADDRESSES 00000y - 017777

—

i i

)

D e

12:02

TEST 24: CHECK EACH ADDRESS OF MEM SIM RAM TO BE ADDRESSED

g}gs

VIVIT A

MACY11 30A(1052)

015400
015412

015414

012737
001405

104455

000002
000000
003712

177740

002264

002270

MOV

#MSELO,R2LOAD

:SETUP BITS TO BE LOADED

PC,LDRDR?

:G0 LOAD,READ AND CHECK REG 2

MOV

#177740,R2ZMASK

BEQ
ERRDF

28
2, ,R2EROR

JSR

TRAP

WORD
WORD
.WORD
CKLOOP

CSERDF

2
0
R2EROR

:SETUP REGISTER 2 MASK WORD

:1F LOADED OK THEN CONT
:REGISTER 2 NOT EQUAL EXPECTED

HARDWARE TESTS

015424

MACY11_30 A(1052)

17-JUN-82

1:26

17-JUN-82 12:02 PAGE 102
TEST 24: CHECK EACH ADDRESS OF MEM SIM RAM TO B ADDRESSED

104406

TRAP

C$CLPT

333z,

) o)
b
D e
— e

vivvwvivvuaviviaa

d =D

;LOAD THE ADDRESS TO BE TESTED INTO CONTROL REGISTER 4. THE ADDRESS
;WILL APPEAR ON MSAD BITS 150 WHICH IS THE OUTPUT OF CONTROL REGISTER &
OCOO0O0O0O0O0O00

S8RBIRRREC2EBRIRARR

VI VIV

NN Nt ed b b D e e e
(=1~}
N —

b D b ed =D D

TV T ATV VWA

CVCDAB.P11

004737
001405

005462

JSR

BEQ
ERRDF

TRAP

104455
000003
000000
004000

WORD
WORD
.WORD

CKLOOP
TRAP

104406

PC,LDRDR

3$
3, ,R4EROR

CSERDF

;GO LOAD,READ AND CHECK REGISTER &

+IF LOADED OK THEN CONTINUE
*REGISTER 4 NOT EQUAL EXPECTED

3
O
R4EROR
CSCLP1

;WRITE THE DATA PATTERN INTO MODULE SELECT RAM O AND CHECK THAT IS WAS

sWRITTEN CORRECTLY. THE DATA PATTERNS THAT WILL BE WRITTEN ARE 1, 2, 4,
:10. THESE PATTERNS WILL ENABLE THE SIGNALS ENO H, EN1 H, EN2 H, AND
sEN3 H RESPECTIVELY. THESE SIGNALS ARE USED TO SELECT MEMORY SIMULATOR
¢MEMORY WHEN THE SIGNAL SSM L IS ASSERTED LATER ON IN THE TEST.

5203
010137
012737
004737
001405

002302

177760

005506

MOV

002306

PC,LDRDR6

:GO LOAD, READ AND CHECK RAM 0

BEQ
ERRDF

4
4 ,MSGMDO,AL INFO

WORD
.WORD
.WORD
CKLOOP

&
MSGMDO
ALINFO

TRAP

104406

:GET THE PATTERN TO BE LOADED

#177760, R6MASK

JSR

104455
000004
002513
004052

R1,R6LOAD

MOV

TRAP

CS$ERDF

:SETUP REGISTER 6 MASK WORD

:IF OK THEN CONTINUE
:DATA ERROR IN MODULE SELECT RAM 0

CSCLP1

NONINIAD
= it b

d wd
i
b o
h
i
e

KRR
SRR

ViAWV AW WY
VIV

OO0O0O0O0O0OCOO0O0

;SET SIGNALS MSELO H AND MSELT H TO A ONE AND SIGNALS MSAD17 H AND MSAD16 H
:TO A ZERO IN CONTROL REGISTER 2. MSELO H AND MSEL1 H ON A ONE, WILL
;CAUSE THE SIGNAL SMDS1 L TO BE ASSERTED ON A WRITE OR READ TO CONTROL
;REGISTER 6. SMDS1 L WILL SELECT MODULE SELECT RAM 1. MSAD BITS 17 AND 16
sON A ZERO WILL SELECT ADDRESS O OF MODULE SELECT RAM 1.
012737
004737
001405
1046455
000002
000000

003712

104406

000014
005414

002264

4$:

Mov
JSR
BEQ
ERRDF

#MSELO!MSELT,R2LOAD
PC,LDRDR2
58
2, ,R2EROR

WORD
WORD
.WORD

2
0
R2EROR

TRAP

CKLOOP
TRAP

CSERDF

sSETUP BITS TO BE LOADED
:GO LOAD, READ AND CHECK REGISTER 2
:IF LOADED OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

CSCLPY

sWRITE THE DATA PATTERN INTO MODULE SELECT RAM 1 AND CHECK THAT THE
sPATTERN WAS LOADED CORRECTLY.

A DATA PATTERN OF ALL ONES WILL BE

;WRITTEN, HOWEVER, WHEN THE LOCATION IS READ BACK, A DATA PATTERN
sEQUAL TO ONE WILL BE READ. SETTING THE LEAST SIGNIFICANT BIT IN

sTHE DATA PATTERN WILL FORCE THE MORE SIGNIFICANT BITS TO ZERO.

SEQ@ 0102

HARDWARE TESTS MACY11 30A(1OS2)
CVCDAB.P11
17=-JuN-82
11:26

5240

015526

012737

000017

§242

015542

004737

005514

€344

015550

§246
5247
5248
5249
5250
2521

015552
015554
015556
015560
015560
015560

000004
002555
004052

ggg‘

~M5562

012702

§255
gggg

015566
015566

104404

17=JUN-82
12:02 PAGE 103
TEST 24: (“ECK EACH ADDRESS OF MEM SIM RAM TO BE ADDRESSED

002302

§241 015534 012737 000001 002304
5243

5245

015546

015550

001404

S8:

#8170, R6GOOD

;SETUP EXPECTED
DATA PATTERN

BEQ

:IF DATA OK THEN CONTINUE

TRAP

JSR

ERRDF

104455
68:
100008:

104405
010000

78:

#B1T3!8112!81T1!81T0,R6LOAD :GET DATA PATTERN TO BE LOADED

MOV

PC,LORDGR

& nscno1 LALINFO

.WORD
.WORD
.WORD
ENDSEG

nscno'
ALINFO

TRAP

CSESEG

MOV

#4096. ,R2

BGNSEG
TRAP

($BSEG

:GO LOAD,READ AND CHECK RAM 1
:DATA ERROR IN MUDULE SELECT RAM 1

;SETUP 4K WORD COUNTER TO DO 1 RAM

5258

:CLEAR BITS MSELO W, MSEL1 H, MSAD17 H AND MSAD16 H IN CONTROL aecxsren

5260
5261
5262

:ASSERTED ON A WRITE OR READ TO CONTROL REGISTER 6. ON A WRITE OR READ
;TO CONTROL REGISTER 6, DATA WILL BE WRITTEN OR READ FROM THE MEMORY
*SIMULATOR RAM SELECTED. THE SIHULATOR MEMORY 1S SELECTED VIA THE

5259

:2. MSELO H AND MSEL1 H ON A ZERO WILL CAUSE THE SIGNAL SSM L TO BE

gggz

*MODULE SELECT RAM'S (0 AND 1)

5265
5266
5267
5268

015570
015574
015600
015602

005037
004737
001405

5270
5271
5272
5273
gs;g

015604
015606
015610
015612
015612

000002
000000
003712

002264
005414

5269 015602 104455

015614

5280

015622

104406

015620

004737

001405

005462

8s:

2
O
R2EROR

015624
015626
015630
015632
015632

JSR

BEQ

ERRDF

5281 015622 104455

TRAP

000003
000000
004000

.WORD
JWORD
-WORD
CKLOOP
TRAP

104406

5288
5289
5290
gggt

5293
5294
5295

WORD
WORD
.WORD
CKLOOP
TRAP

cisaor

:SETUP TO CLEAR REGISTER 2
:GO LOAD, READ AND CHECK REG 2
:IF LOADED OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

CSCLP1

;LOAD MEMORY SIMULATOR ADDRESS TO BE TESTED INTO CONTROL REGISTER &

5278

5282
5283
5284
5285
gggg

R2L0AD
PC,LDRDR2
as
LR2EROR

TRAP

g%;g

5279

CLR
JSR
BEQ
ERRDF

PC,LDRDR

LRGEROR

cisnor

:GO LOAD,READ AND CHECK REGISTER 4

*IF LOADED OK THEN CONTINUE

*REGISTER 4 NOT EQUAL EXPECTED

3
O
R4EROR
CSCLP1

;LOAD DATA PATTERN EQUAL TO ADDRESS INTO MEMORY SIMULATOR RAM. ON A
;WRITE OR READ TO CONTROL REGISTER 6, THE SIGNAL SSM L WILL BE ASSERTED.
;THIS SIGNAL WILL ENABLE BOTH MODULE SELECT RAMS AND ENABLE THE MEMORY
:SIMULATOR RAM TO BE WRITTEN OR READ.

015634
015642
015646

013737
005037
004737

002276
002306
005506

002302

9%:

MOV
CLR
JSR

R4LOAD , R6LOAD
RGMASK
PC,LDRDR6

:SETUP DATA PATTERN TO BE LOADED
:SETUP TO CHECK ALL 16 BITS OF RAM
;GO LOAD, READ AND CHECK RAM LOCATION

SEQ 0103

HARDWARE TESTS

MACY11 30?(;252)

CVCDAB.P11

17-JUN=-82 1

5296
sgg;

015652
015654

001404

%g
5
5301
ssog
5303
§§6'§

015656
o1sesg
015662
015664
015664
015664

000004
00273
00405

015654

17-JUN-82

104455

5315
5316
5317
5318
gggg

108:
10001$:

104405

015666
015674
015676

062737
005302
001333

000002

002276

015700

006301

015702
015706
015710

032701
001002
000137

5326
g;gg

015720
C15720

104404

#2 .R4LOAD
R2
78

;UPDATE ADDRESS BY 2
*DECREMENT 2K WORD COUNTER
:1F NOT DONE DO NEXT ADDRESS

:SELECT RAM O ON NEXT PASS OF THIS TEST

000020
015370

002276

ASL

BIT
BNE
JMP

#BIT4.R1
118
1$

11$:

CLR

R4LOAD

128:

BGNSEG
TRAP

($BSEG

5329

:MOVE MODULE SELECT RAM O DATA PATTERN
SLEFT TO ENABLE NEXT MEMORY SIMULATOR RAM
:CHECK IF ALL RAMS HAVE BEEN TESTED
:IF YES THEN EXIT THE TEST
*OTHERWISE DO NEXT RAM

;RESET THE ADDRESS TO 0

;LOAD THE ADDRESS TO BE CHECKED INTO CONTROL REGISTER 4. THE MODULE

g;g?

:SELECT RAMS HAVE BEEN INITIALIZED PREVIOUSLY.

§332

015722

533,

015730

015726
015730

015732
015734
015736
015740
015740

004737

001405

005462

JSR

PC,LDRDRG

;GO LOAD, READ AND CHECK REGISTER &

ERRDF

3, .R4EROR

*REGISTER 4 NOT EQUAL EXPECTED.

WORD
WORD
-WORD
CKLOOP
TRAP

3
O
R4EROR

BEQ

104455

TRAP

000003
000000
004000
104406

5342

13§

CSERDF

+IF LOADED OK THEN CONTINUE

CSCLP1

;READ THE MEMORY SIMULATOR RAM AND CHECK THAT THE ADDRESS CONTAINS ITS

*ADDRESS AS DATA.

5345
5346
53,7
5348

015742
015750
015756
015762

5350

015770

5351

CSESEG

;AND CHECK THAT EACH ADDRESS OF THE RAM CONTAINS AS DATA ITS ADDRESS.
005037

5349

TRAP

CSERDF

;THE FOLLOWING SECTION OF CODE WILL READ THE MEMORY SIMULATOR RAMS
015714

2322

&
MSGMSR
ALINFO

:1F DATA OK THEN GO COMPLEMENT IT
:DATA ERROR IN MEMORY SIMULATOR RAM

;UPDATE MODULE SELECT RAM ENABLE BITS TO BE LOADED INTO MODULE

g;gg

5336
5337
5338
5339
gsszg

JMORD
.WORD
.WORD
ENDSEG

ADD
DEC
BNE

g%g%

5335

108
&, MSGMSR,AL INFO

;UPDATE MEMORY SIMULATOR ADDRESS TO NEXT ADDRESS TO BE LOADED

5321

5333

BEQ
ERRDF

TRAP

§312

?%%2

PAGE 104

TEST 24: CHECK EACH ADDRESS OF MEM SIM RAM TO BE ADDRESSED

gggg
5308
5309
gg}?

12:02

013737
013737
005037
004737

015766

001404

015770

104455

002276
002302
002306
005522

002302
002304

13$:

MOV
MOV
CLR
JSR

R4LOAD , R6LOAD
R6LOAD , R6GOOD
RGMASK
PC ,READRG

ERRDF

&4 ,MSGMSR,ALINFO

BEQ

TRAP

14§

CS$ERDF

;SETUP DATA THAT WAS PREVIOUSLY WRITTEN
*SETUP EXPECTED DATA
*SET REGISTER 6 MASK TO ZERO
:GO READ AND CHECK THE RAM LOCATION

:IF DATA EQUALS ADDRESS THEN CONTINUE
:DATA ERROR IN MEMORY SIMULATOR RAM

SEQ 0104

HARDWARE TESTS MACY11_30A(1052)
CVCDAB.P11
17=JUN-8 21 1:26

535
535

000004
00273
00405

MORD

148:
100028:

104405

016002
016010

062737
100343

000002

002276

.WORD
.WORD
ENDSEG

MSGMSR
ALINFO

TRAP

CSESEG

ADD

#2 ,R4LOAD

8PL

12§

;UPDATE THE ADDRESS TO THE NEXT LOCATION

:IF NOT DONE CHECK NEXT ADDRESS

sTHE FOLLOWING SECTION OF CODE WILL READ THE CONTENTS OF A LOCATION
sCHECKING THAT THE CONTENTS EQUALS THE ADDRESS. THE TEST WILL THEN
;WRITE THE ONES COMPLEMENT OF THE ADDRESS INTO THE LOCATION AND CHECK
:THAT THE LOCATION WAS WRITTEN CORRECTLY.
016012

005037

016016
016016

104404

002276

CLR
158:

BGNSEG
TRAP

R4LOAD

sRESET THE ADDRESS TO APDRESS 0

C$BSEG

:LOAD THE ADDRESS TO BE TESTED INTO CONTROL REGISTER &
004737
001405

005462

JSR

PC,LDRDR4

;G0 LOAD, READ, AND CHECK REGISTER &

ERRDF

3, ,R4EROR

*REGISTER 4 NOT EQUAL EXPECTED

BEQ

104455
000003
000000
004000

TRAP

.WORD
WORD

"WORD
CKLOOP
TRAP

104406

16$

CSERDF

:IF LOADED OK THEN CONTINUE

O
R4EROR
CSCLP1

sREAD THE LOCATION CHECKING THAT THE DATA STORED IN LUCATION EQUALS
sTHE ADDRESS OF THE LCCATION
013737

002276
002302
005522

002302
002304

16$:

Mov

R4LOAD,R6LOAD

JSR

PC,READR6

MOov

BEQ

R6LOAD ,R6GOOD

17§

ERRDF

&4 ,MSGMSR,ALINFO

WORD
.WORD
.WORD
CKLOOP
TRAP

&
MSGMSR
ALINFO

TRAP

CSERDF

:GET THE ADDRESS

sSETUP FOR EXPECTED DATA

:GO READ AND CHECK THE DATA

:IF ADDRESS EQUALS DATA THEN CONT

:ADDRESS SHORT OR DATA NEQ EXPECTED

CSCLP1

—

b —a

055'\)8'\)5

— e

b =D

;WRITE THE COMPLEMENT OF THE ADDRESS IN THE LOCATION ADDRESSED.
=lelelelelale)

S WN=00

SNININSNCY

AV LV LV IV IV IV 1V IV, ]VIV IV IV IV IV IV IV, IV,

VO VOV~

\fl\fl\fl\fl&\fl\fl\fl\lflfl\fl\fl
S
Re
R R R bt oy g F Pt = P Ii wwwwwgELEEREL 33

WWWWWW
ViV

015772

17-JUN-82 12:02 PAGE 105
TEST 24: CHECK EACH ADDRESS OF MEM SIM RAM TO BE ADDRESSED

002276
002302
005506

002302

17%:

MOV
COM
JSR

R4LOAD , R6LOAD
R6LOAD
PC,LDRDRé

:GET THE ADDRESS
:COMPLEMENT IT
:GO LOAD, READ AND CHECK RAM

ERRDF

4 MSGMSR, AL INFO

:DATA ERROR IN MEMORY SIMULATOR RAM

WORD

BEQ

TRAP

18§

CS$ERDF

SIF DATA'OK THEN CONTINUE

SEQ 0105

HARDWARE TESTS MACYN 30?(‘1?252)
CVCDAB.P11
17=JUN=82 1

5408

016120

002732

§409
5410
56411

016122
016124
016124

004052

016124

104405

5414

016126

062737

gz}g

gz}z

016134

17-JUN-82
12:02
PAGE 106
TEST 24: CHECK EACH ADDRESS OF MEM SIM RAM TO BE ADDRESSED

100330

188:
10003$:

000002

002276

016136

005037

54622
gzgz

016142
016142

104404

002276

19$:

§2gg
016144

5429

016152

016150

016152

016154
016156
016160
016162
016162

004737

001405

005462

15§

CLR

R4LOAD

BGNSEG
TRAP

($BSEG

000003
000000
004000

208

TRAP

CSERDF

JWORD
WORD
.WORD
CKLOOP
TRAP

104406

PC,LDRDRG

BEQ

ERRDF

104455

;UPDATE THE TEST ADDRESS BY 2

:IF NOT DONE GO DO NEXT ADDRESS

;RESET THE ADDDRESS POINTER TO 0

3, ,R4EROR

;GO LOAD, READ AND CHECK REGISTER 4

+IF LOADED OK THEN CONTINUE

*REGISTER 4 NOT EQUAL EXPECTED

3
0
R4EROR
CSCLP1

;READ THE MEMORY SIMULATER RAM AND CHECK THAT THE ADDRESS CONTAINS

ggg

;1TS COMPLEMENT AS DATA

5440
5441
5442
5443

016164
016172
016176
016206

5445

016212

5447
5448
5449
5450
5451
5452

016214
016216
016220

gzgz

016222
016222

104405

5455

016224

062737

5457
5458
5459

016234
016234
016234

5456

#2 ,R4LOAD

JSR

5437

5446

ADD

;LOAD ADDRESS TO BE TESTED INTO CONTROL REGISTER &

5427

5444

CSESEG

;CHECKING THAT EACH ADDRESS CONTAINS ITS ONES COMPLEMENT AS DATA

22%?

5431
5432
5433
5434
gzg

TRAP

;THE FOLLOWING SECTION OF CODE WILL READ THE MEMORY SIMULATOR RAM'S

gz;g

5430

MSGMSR
ALINFO

BPL

§417

5428

.WORD

.WORD
ENDSEG

016210

016212

013737
005137
013737
004737

001404

002276
002302
002302
005522

002302
002304

104455

21$:

104401

R4LOAD , R6LOAD
R6LOAD
R6LOAD , R6GOOD
PC ,READRG

:GET THE ADDRESS
:SET IT TO ITS ONES COMPLEMENT
*SETUP EXPECTED DATA
:GO READ AND CHEK THE RAM LOCATION

ERRDF

& ,MSGMSR,AL INFO

:LOCATION NOT EQUAL TO ITS ONES COMP

MWORD
.WORD
.WORD

&
MSGMSR
ALINFO

TRAP

000004
002732
004052

100343

MOV
COM
MOV
JSR

BEQ

016222

016232

20$:

100048:

000002

002276

CSERDF

ENDSEG

TRAP

CSESEG

ADD

#2 ,R4LOAD

BPL
L10057:

21%

ENDTST
TRAP

19§

CSETST

:IF DATA OK THEN CONTINUE

JOR AN ADDRESS SHORT IN RAM

:UPDATE THE ADDRESS TO BE TESTED

:GO DO NEXT ADDRESS

SEQ 0106

HARDWARE TESTS

CVCDAB.P11

MACY1

30?(;252)

17=JUN=82 1

17-JUN-82

12:02

PAGE 107

TEST 25: CHECK THAT WORDS ARE WRITTEN IN SIM RAM ON ODD ADDRESS

SEQ 0107

gzg;

.SBTTL TEST 25: CHECK THAT WORDS ARE WRITTEN IN SIM RAM ON ODD ADDRESS

5463
5464
5465

144
: THE FOLLOWING TEST WILL WRITE THE MEMORY SIMULATOR RAM'S WITH A COMPLEMENTING
s DATA PATTERN. THE INITIAL DATA PATTERN WILL BE 125252. EACH CONSECATIVE

5467

: 125252,

5466

; LOCATION
WILL CONTAIN THE COMPLEMENTED DATA OF THE PREVIOUS LOCATION (I.E.

5468

052525, 125252 .... ETC). THE ADDRESSES TO THE MEMORY SIMULATOR RAMS

: WILL SE LOADED AS ODD ADDRESSES. THIS TEST IS DONE TO INSURE THAT ODD ADDRESSES

5469
5470
5471
5472
5473

:
:
:
;
:

IN 16 BIT MODE DO NOT DISABLE THE WRITING OR READING OF THE LOW BYTE OF THE
MEMORY SIMULATOR RAM. AFTER ALL THE RAM'S HAVE BEEN LOADED WITH THE COMPLE=MENTING DATA PATTERN, THE TEST WILL REREAD THE MEMORY SIMULATOR RAMS USING
EVEN ADDRESSES AND CHECKING THAT THE RAM'S CONTAIN THE COMPLEMENTING DATA
PATTERN

5474,

;

5476

;

WHEN AN ERROR OCCURS, THE INFORMATION PROVIDED IN CONTROL REGISTER 4

5478
5479
5480
5481

;
;
:
3

TABLE BELOW INDICATES THE 4K RAM SELECTED FOR THE ADDRESSES IN ERROR.
1ST 4K OF RAM = ADDRESSES 000000 - 017777
2ND 4K OF RAM = ADDRESSES 020000 - 037777
3RD 4K OF RAM = ADDRESSES 040000 - 057777

5484

5475

2 NOTE:

54,77

gzgg

5485
5486
5487
5488
5489
5490

016236
016236
016236
016242
016250

004737
012737
012701

5493
gzgg

016260
016260

104404

2235

016256

012703

004550
000001
000001

125::
002276

125252

INDICATES THE ADDRESS BEING TESTED AND THE RAM BEING SELECTED.

4TH 4K OF RAM - ADDRESSES 060000 - 077777

BGNTST
JSR
MoV
MOV

PC,INITMS
#8I1T0,R4LOAD
#BITO R1

BGNSEG
TRAP

($BSEG

MOV
18:

THE

#125252 .83

;SELECT AND INIT MEMORY SIMULATOR
sSET 1ST ADDRESS TO BE (ESTED TO 1
:SETUP DATA FOR MODULE SELECT RAM 0

:INIT DATA PATTERN TO 125252

5496

;SET SIGNAL MSELO W TO A ONE AND CLEAR SIGNALS MSEL1 W, MSAD17 H AND

ggg?

:RAM 0.

5497
5498
5499

:MSAD16 H IN CONTROL REGISTER 2. MSELO H ON A ONE AND MSEL1 H ON
;A 2ERO WILL CAUSE THE SIGNAL SMDSO L TO BE ASSERTED ON A WRITE OR
:READ COMMAND TO CONTROL REGISTER 6. SMDSO L WILL SELECT MODULE SELECT

§502

016242

012737

000006

5504
5505
5506

016556
016302
016304

004737
001405

005414

5503

5507

5508
5509
5510
5511
gg;;
5514

gg;g

016270
016304

016306
016310
016312
016314
016314

012737
104455

003712
104406

177740

002264

002270

MOV

#MSELO,R2LOAD

:SETUP BITS TO BE LOADED

JSR
BEQ
ERRDF

PC,LDRDR2
gs
LR2EROR

:GO LOAD,READ AND CHECK REG 2
+IF LOADED OK THEN CONT
:REGISTER 2 NOT EQUAL EXPECTED

MOV

TRAP

.WORD
WORD
.WORD
CKLOOP
TRAP

#1777460, R2MASK
C$ERDF

:SETUP REGISTER 2 MASK WORD

2
O
R2EROR
CSCLP1

;LOAD THE ADDRESS TO BE TESTED INTO CONTROL REGISTER 4. THE ADDRESS

:WILL APPEAR ON MSAD BITS 15-0 WHICH IS THE OUTPUT OF CONTROL REGISTER &

—

———————
e
e

———

£NARDUARE TESTS MACYN 30?(5252) 17-JUN-82 12:02 PAGE 108
CVCDAB.P11
17=-JUN~-82 1
TEST 25: CHECK THAT WORDS ARE WRITTEN IN SIM RAM ON ODD ADDRESS
|

5517
§518
§519

016316
016322
016324

004737
001405

§521
55 g
§523

016326
016330
016332

000003
000000
004000

§520

5524
g;gg

016324

016334
016334

005462

28:

104455

010137

002302

5535
5536
5537

016350
016354
016356

004737
001405

005506

5539
5540

016360
016362

000004
002513

016342

016356

012737

177760

002306

3s:

104455

.WORD
.WORD

.WORD

CKLOOP
TRAP

104406

5555

5556
5557
5558
5559
gggg

016370

016376
016402
016404

016406

016406
016410
016412
016414
016414

012737

004737
001405

000014

005414

002264

4$:

104455

000002
000000
003712

PC,LDRDRG
48
& ,MSGMDO,AL INFO

:GO LOAD, READ AND CHECK RAM 0
:IF OK THEN CONTINUE
:DATA ERROR IN MODULE SELECT RAM 0

C$ERDF

:SETUP REGISTER 6 MASK WORD

&
MSGMDO

ALINFO
CSCLP1

MOV

#MSELO!'MSEL1,R2L0OAD

TRAP

CSERDF

JSR
BEQ
ERRDF
WORD
WORD
.W0?D
CKLOOP
TRAP

106406

PC,LDRDR2
58
2, ,R2EROR

;SETUP BITS TO BE LOADED

:GO LOAD, READ AND CHECK REGISTER 2
*IF LOADED OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

2
O
R2EROR
CSCLP1

;WRITE THE DATA ¥ATTERN INTO MODULE SELECT RAM 1 AND CHECK THAT THE
:PATTERN WAS LUADED CORRECTLY. A DATA PATTERN OF ALL ONES WILL BE
:WRITTEN, HOWEVER, WHEN THE LOCATION IS READ BACK, A DATA PATTERN
:EQUAL TO ONE WILL BE READ. SETTING THE LEAST SIGNIFICANT BIT IN

gggg

;THE DATA PATTERN WILL FORCE THE MORE SIGNIFICANT BITS TO ZERO.

5568

016416

012737

000017

55720

016432

004737

005514

5571
5572

:GET THE PATTERN TO BE LOADED

:ON A ZERO WILL SELECT ADDRESS O OF MODULE SELECT RAM 1.

5562
5563
5564
5565

5569

R1,R6LOAD

#177760,R6MASK

;SET SIGNALS MSELO H AND MSELT H TO A ONE AND SIGNALS MSAD17 H AND MSADI6 H
:TO A ZERO IN CONTROL REGISTER 2. MSELO H AND MSEL1 H ON A ONE. WILL
;CAUSE THE SIGNAL SMDS1 L TO BE ASSERTED ON A WRITE OR READ TO CONTROL
;REGISTER 6. SMDS1 L WILL SELECT MODULE SELECT RAM 1. MSAD BITS 17 AND 16

gggg
5552
5553
5554

MOV

TRAP

016364 004052

016366
016366

MOV

JSR
BEQ
ERRDF

5545
5546
5547
5548

§551

CSCLP1

;MEMORY WHEN THE SIGNAL SSM L IS ASSERTED LATER ON IN THE TEST.
016336

5542
ggzz

O
R4EROR

gisnor

:GO LOAD,READ AND CHECK REGISTER 4
*IF LOADED OK THEN CONTINUE
*REGISTER 4 NOT EQUAL EXPECTED

;WRITE THE DATA PATTERN INTO MODULE SELECT RAM O AND CHECK THAT IS WAS
:WRITTEN CORRECTLY. THE DATA PATTERNS THAT WILL BE WRITTEN ARE 1, 2, 4,
:10,
THESE PATTERNS WILL ENABLE THE SIGNALS ENO W, ENT H, EN2 H. AND
;EN3 M RESPECTIVELY. THESE SIGNALS ARE USED TO SELECT MEMORY SIMULATOR

§537

5541

.WORD
WORD
.WORD

CKLOOP
TRAP

104406

gggg

5538

PC,LDRDRS
3s
3, ,R4EROR

TRAP

§527
5508
§529
§530

5536

JSR
BEQ
ERRDF

016454

016436
016440

012737

001404

000001

002302

002304

5$:

MOV

#8IT3'BIT2!'BIT1'BITO,R6LOAD ;GET DATA PATTERN TO BE LOADED

JSR

PC,LDRDG6R

MOV
BEQ
ERRDF

#8170,R6GOO0D

;SETUP EXPECTED DATA PATTERN

6$
&,MSGMD1,ALINFO

*IF DATA'OK THEN CONTINUE
:DATA ERROR IN MUDULE SELECT RAM 1

:GO LOAD,READ AND CHECK RAM 1

SEQ 0108

rotnps gy

HARDWARE TESTS

CVCDAB.P11

5573

§5764
§575
5576
§577
5578

016440

MACY11

17-JUN-82

12:02

016450

104405

§§g12 016452

012702

§583
gggg

104404

PAGE 109

TEST 25: CHECK THAT WORDS ARE WRITTEN IN SIM RAM ON ODD ADDRESS

104455

000004
002555
004052

016456
016456

30A(1052)

17-JUN-82 11:26

016442
016444
016446
016450
016450

gg;g

mispmailiienatsnses

68:
100008:

010000
78:

TRAP
MORD
.WORD
.WORD
ENDSEG

&
MSGMD1
ALINFO

CSERDF

TRAP

CSESEG

MOV

#6096. ,R2

BGNSEG
TRAP

($BSEG

;SETUP 4K WORD COUNTER TO DO 1 RAM

5586

;CLEAR BITS MSELO H, MSEL1H, MSAD17 H AND MSAD16 H IN CONTROL REGlStER

5588
5589
5590

:ASSERTED ON A WRITE OR READ TO CONTROL REGISTER 6. ON A ums on READ
;TO CONTROL REGISTER 6, DATA WILL BE WRITTEN OR READ FROM THE MEMORY
*SIMULATOR RAM SELECTED. me swwoa MEMORY IS SELECTED VIA THE

5587

+2. MSELO H AND MSEL1 H ON A ZERO WILL CAUSE THE SIGNAL SSML TO BE

ggg;

§593

5594
5595
5596
5597
5598
5599
5600
5601
g&g

*MODULE SELECT RAM'S (0 AND
1

016460

016464
016470
016472
016472
016474
016476
016500
016502
016502

005037

004737
001405

002264

CLR

005414

JSR
BEQ
ERRDF
TRAP
LWORD
WORD
.WORD
CKLOOP
TRAP

104455
000002
000000
003712
104406

gggg
5606
5607

5608

5610

5612
5613
gg}g

016504
016510

004737
001405

016514

000003

016520
016522
016522

004000

016512

005462

8s:

016516

JSR
BEQ

ERRDF

TRAP

.WORD

000000

-WORD

.WORD
CKLOOP
TRAP

104406

5616
5617
5618
gg;g

:SETUP TO CLEAR REGISTER 2

:GO LOAD, READ AND CHECK REG 2
*IF LOADED OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

CSCLP1

PC,LDRDR4
9s

LR4EROR

cienor

;GO LOAD,READ AND CHECK REGISTER 4
*IF LOADED OK THEN CONTINUE

*REGISTER 4 NOT EQUAL EXPECTED

R4EROR
CSCLP1

;LOAD DATA PATTERN 125252 OR 052525 INTO MEMORY SIMULATOR RAM. ON A
;WRITE OR READ TO CONTROL REGISTER 6, THE SIGNAL SSM L WILL BE ASSERTED.
;THIS SIGNAL WILL ENABLE BOTH MODULE SELECT RAMS AND ENABLE THE MEMORY
:SIMULATOR RAM TO BE WRITTEN OR READ.

5621
5622

016524
016530

010337 002302
005037 002306

5624

016540

001404

5623

PC,LDRDR2
13
2, ,R2EROR
CSERDF
2
O
R2EROR

;LOAD MEMORY SIMULATOR ADDRESS TO BE TESTED INTO CONTROL REGISTER &

5609 016512 104455

5611

R2LOAD

016534

01654

5627

016544

5626 016542

004737

106455

000004

5628 016546 002732

005506

98:

MOV
CLR

R3,R6LOAD
ROGMASK

;SETUP DATA PATTERN TO BE LOADED
:SETUP TO CHECK ALL 16 BITS OF RAM

BEQ

10§

:1F DATAOK THEN GO COMPLEMENT IT

JSR

ERRDF

TRAP

.WORD

-WORD

PC,LDRDR6
& nscnsa ALINFO

nscnsa

:GO LOAD, READ AND CHECK RAM LOCATION
:DATA ERROR IN MEMORY SIMULATOR RAM

SEQ 0109

| HARDWARE TESTS MACY11 30A(1052)
CvCDAB.P1

S6§3
56
5631
56
56

016550
016555
01655
016552

5637
5638
5639
5640
5641
Sb‘%
564
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
gggg

016554
016556
016564
016566

383
5636

5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671

17-JUN-82 11:26

17=-JuN-82

1 :02
PAGE 110
TEST 25: CHECK THAT WORDS ARE WRITTEN IN SIM RAM ON ODD ADDRESS

004052

.UORg

ALINFO

TRAP

CSESEG

108:
t'.LSEG
10001$:

104405

;UPDATE MEMORY SIMULATOR ADDRESS TO NEXT ADDRESS TO BE LOADED
s COMPLEMENT THE DATA PATTERN FOR NEXT LOAD TO RAM
005103
062737
00530
00133

000002

CoM

002276

ADD
DEC

BNE

#2 ,R4LOAD
R2

s COMPLEMENT THE DATA

sUPDATE ADDRESS BY 2
sDECREMENT 2K WORD COUNTER

:IF NOT DONE DO NEXT ADDRESS

sUPDATE MODULE SELECT RAM ENABLE BITS TO BE LOADED INTO MODULE
sSELECT RAM O ON NEXT PASS OF THIS TEST
016570

016572
016576
016600

006301
)
032701
001002
000137

000020
016260

ASL

sMOVE MODULE SELECT RAM O DATA PATTERN

BIT
BNE
JMP

#BITL ,R1
11$
1$

;OTHERWISE DO NEXT RAM

sLEFT TO ENABLE NEXT MEMORY SIMULATOR RAM
sCHECK IF ALL RAMS HAVE BEEN TESTED
sIF YES THEN EXIT THE TEST

sTHE FOLLOWING SECTION OF CODE WILL READ THE MEMORY SIMULATOR RAMS
sAND CHECK EACH ADDRESS TO CONTAIN EITHER 125252 OR 052525.
016604
016610

005037
012703

016614
016614

104404

002276
125252

118:

CLR
Mov

128:

BGNSEG
TRAP

R4LOAD
#125252,R3

sRESET THE ADDRESS T0 0
sRESET THE INITIAL DATA PATTERN

C$BSEG

;LOAD THE ADDRESS TO BE CHECKED INTO CONTROL REGISTER 4. THE MODULE
sSELECT RAMS HAVE BEEN INITIALIZED PREVIOUSLY.

016616
016622
016624
016624
016626
016630
016032
016634
016634

004737
001405
104455
000003
000000
004000
104406

005462

JSR

PC,LDRDRS

:GO LOAD, READ AND CHECK REGISTER 4

TRAP

ciERor

*REGISTER 4 NOT EQUAL EXPECTED.

-WORD
.WORD

o
R4EROR

BEQ

ERRDF
.WORD

CKLOOP
TRAP

13§

LRGEROR

CSCLP1

+IF LOAPED OK THEN CONTINUE

SEQ@ 0110

HARDWARE TESTS

CVCDAB.P11

MACY11

SOA(;OSZ)

17-Jun-82
1

17=JUN-82 1 :02 PAGE 111
TEST 25: CHECK THAT WORDS ARE WRITTEN IN SIM RAM ON ODD ADDRESS

seirsigecis

002;05
002302
002306
005522

002304

138:

d o
o
o
e

-~
~N

- b

14$:
10002$:

016672

000002

104401

MOV
MOV
CLR

JSR
BEQ
ERRDF

anh

o [=lelelelelelolaletoTel

sREAD THE MEMORY SIMULATOR RAM AND CHECK THE COMPLEMENTING DATA PATTERN

TRAP
-WORD
.WORD
. WORD
ENDSEG

TRAP

CoM

002276

ADD

BPL

L10060:

R3,R6LOAD

R6LOAD , R6GOOD
R6MASK
PC ,READRG

14$

&4 MSGMSR,
AL INFO

Eieaor

*SETUP EXPECTED DATA
*SET REGISTER 6 MASK TO ZERO
+GO READ AND CHECK THE RAM LOCATION

+IF DATA EQUALS ADDRESS THEN CONTINUE
:DATA ERROR IN MEMORY SIMULATOR RAM

MSGMSR
ALINFO

CSESEG
R3

#2 ,RG4LOAD

12$

ENDTST
TRAP

;SETUP DATA THAT WAS PREVIOUSLY WRITTEN

CSETST

;COMPLEMENT THE DATA PATTERN
:UPDATE THE ADDRESS TO THE NEXT LOCATION

:IF NOT DONE CHECK NEXT ADDRESS

SEQ@ 011"

' MARDWARE TESTS
| CVCDAB.P11

MACY11_30 A(1052)
17-JUN-8 21 1:26

——

1 7-JUN-82 12:02 PAGE 112
TE ST 26: CHECK MEM SIM RAM'S USING "MOVB'' INSTRUCTION

SEQ 0112

+SBTTL TEST 26: CHECK MEM SIM RAM'S USING 'MOVB'’' INSTRUCTION
4

THE FOLLOWING TEST WILL WRITE INTO AND READ FROM THE MEMORY SIMULATOR RAMS

USING THE 'MOVB"' INSTRUCTION. THIS TEST IS DONE IN 16 BIT MODE. THE PURPOSE
OF THIS TEST IS TO CHECK THAT WHEN WRITING TTHE LOW BYTE OF AN ADDRESS, THE

—

NO NS WA —

HIGH BYTE IS NOT AFFECTEC, AND WHEN WRITING THE HIGH BYTE OF AN ADDRESS, THE
LOW BYTE IS NOT AFFECTED., THE TEST SEQUENCE IS AS FOLLOWS:
WRITE THE ADDRESS TO BE TESTED IN CONTROL REGISTER &
WRITE THE MODULE SELECT RAM'S TO ENABLE THE MEMORY SIMULATOR
WRITE AND CHECK LOW BYTE FOR DATA PATTERN OF 125
WRITE AND CHECK HIGH BYTE FOR DATA PATTERN OF 252
READ LOCATION AND CHECK WORD FOR DATA PATTERN OF 125125
WRITE AND CHECK LOW BYTE FOR DATA PATTERN OF 252
READ LOCATION AND CHECK WORD FOR DATA PATTERN OF 125252
WRITE AND CHECK HIGH BYTE FOR DATA PATTERN OF 125

NOTE:

READ LOCATION AND CHECK WORD FOR DATA PATTERN OF 052652
REPEAT STEPS 1-9 FCR ADDRESS O OF EACH MEMORY SIMULATOR RAM

WHEN AN ERROR OCCURS,

THE INFORMATION PROVIDED IN CONTROL REGISTER &

INDICATES THE ADDRESS BEING TESTED AND THE RAM BEING SELECTED.

THE

TABLE BELOW INDICATES THE 4K RAM SELECTED FOR THE ADDRESSES IN ERROR.

1ST 4K OF RAM - ADDRESSES 000000 - 017777

2ND 4K OF RAM - ADDRESSES 020000 - 037777
SRD 4K OF RAM - ADDRESSES 040000 - 057777
4TH 4K OF RAM - ADDRESSES 060000 - 077777

016710
016710
016710
016714
016720

004737
005037
012701

016724
016724

104404

T2 6::

004550
002276
000001

BGNTST
JSR
CLR

MoV
1$:

BGNSEG
TRAP

PC,INITMS
R4LOAD

#81T0,.R1

sSELECT AND INIT MEMORY SIMULATOR
sSET 1ST ADDRESS TO BE TESTED 70 0

sSETUP DATA FOR MODULE SELECT RAM 0

C$BSEG

sSET SIGNAL MSELO H TO A
sMSAD16 H IN CONTROL REGISTER
sA ZFRO WILL CAUSE THE SI
0
:READOCOHHAND TO CONTROL REGISTER 6. SMDS
000004
177740
005414

575

016760

002264
002270

MOV

JHSE%O R2LOAD

:SETUP B

323

pg.Loaoaz

:GO LOAD

ERRDF
TRAP

R2EROR
CS$ERDF

*REGIST

.WORD

RZEROR

TRAP

CscLP

MOV

#1777460, R2MASK

s$TO

LOADED

SSETUP REGISTER 2 MASK WORD

HARDWARE TESTS MACYN 30?(3252)
17-JUN-82 1
CVCDAB.P1T

17-JUN-82

12:02

PAGE 113

TEST 26: CHECK MEM SIM RAM'S USING “MOVB'' INSTRUCTION

sLOAD THE ADDRESS TO BE TESTED INTO CONTROL REGISTER 4. THE ADDRESS
sWILL APPEAR ON MSAD BITS 15-0 WHICH IS THE OUTPUT OF CONTROL REGISTER 4
004737
001405

005462

28:

JSR

BEQ

ERRDF

104455

000003
000000
004000

,RGEROR

TRAP

gienor

WORD
.WORD

O
R4EROR

.WORD

CKLOOP
TRAP

104406

PC,LDRDRG

;G0 LOAD,READ AND CHECK REGISTER 4

+1F LOADED OK THEN CONTINUE

*REGISTER 4 NOT EQUAL EXPECTED

CSCLPI

sWRITE THE DATA PATTERN INTO MODULE SELECT RAM O AND CHECK THAT IS WAS
;WRITTEN CORRECTLY. THE DATA PATTERNS THAT WILL BE WRITTEN ARE 1, 2, &,
:10. THESE PATTERNS WILL ENABLE THE SIGNALS ENO H, EN1 H, EN2 H, AND

;EN3 H RESPECTIVELY. THESE SIGNALS ARE USED TO SELECT MEMORY SIMULATOR

¢MEMORY WHEN THE SIGNAL SSM L IS ASSERTED LATER ON IN THE TEST.
010137
012737
004737
001405

002302
177760
005506

R1,R6LOAD

:GET THE PATTERN TO BE LOADED

JSR

PC,LDRDR6

:GO LOAD, READ AND CHECK RAM 0

004052

104406

#177760,R6MASK

BEQ
ERRDF

4
& ,MSGMDO,AL INFO

WORD
"WORD
.WORD
CKLOOP
TRAP

&
MSGMDO
ALINFO

TRAP

104455
000004
002513

017032
017032

MOV

002306

CSERDF

:SETUP REGISTER 6 MASK WORD

+IF OK THEN CONTINUE
:DATA ERROR IN MODULE SELECT RAM 0

CSCLP1

sSET SIGNALS MSELO H AND MSEL1 H TO A ONE AND SIGNALS MSAD17 H AND MSAD16 H
:TO A ZERO IN CONTROL REGISTER 2. MSELO H AND MSEL1 H ON A ONE, WILL
;CAUSE THE SIGNAL SMDS1 L TO BE ASSERTED ON A WRITE OR READ TO CONTROL
;REGISTER 6. SMDS1 L WILL SELECT MODULE SELECT RAM 1. MSAD BITS 17 AND 16
:ON A 2ERO WILL SELECT ADDRESS O OF MODULE SELECT RAM 1.
012737
004737
001405

000014
005414

002264

4$:

MOV
JSR

000002
000000
003712

2, ,R2EROR

*REGISTER 2 NOT EQUAL EXPECTED

(13

TRAP

CSERDF

WORD
JWORD
.WORD
CKLOOP

104406

;SETUP BITS TO BE LOADED
:GO LOAD, READ AND CHECK REGISTER 2

BEQ

ERRDF

104455

#MSELO!MSEL1,R2LOAD
PC,LDRDR2

TRAP

:IF LOADED OK THEN CONTINUE

2
0
R2EROR
CSCLP1

;WRITE THE DATA PATTERN INTO MODULE SELECT RAM 1 AND CHECK THAT THE

sPATTERN WAS LOADED CORRECTLY. A DATA PATTERN OF ALL ONES WILL BE

;WRITTEN,

HOWEVER, WHEN THE LOCATION IS READ RACK, A DATA PATTERN

:EGUAL TO ONE WILL BE READ. SETTING THE LEAST SIGNIFICANT BIT IN

:THE DATA PATTERN WILL FORCE THE MORE SIGNIFICANT BITS TO ZERO.

017062

012737

000017

002302

5%:

MOV

#B1T3!BIT2!BIT1!BITO,R6LOAD ;GET DATA PATTERN TO BE LOADED

SEQ 0113

HARDWARE TESTS

CvCDAB.P11

MACYN

30A(5052)

012737
004737
001405

000001
005514

17-JUN-82
1

17-JUN-82 12:02 PAGE 114
TEST 26: CHECK MEM SIM RAM'S USING ‘MOVB'' INSTRUCTION

002304

Mov
JSR

BEQ

TRAP

ERRDF

104455
000004
002555
004052

.WORD

-WORD

"WORD
CKLOOP
TRAP

104406

#8170,R6G00D
PC.LDRD6R

nscno1 LALINFO

sSETUP EXPECTED DATA PATTERN
:GO LOAD,READ AND CHECK RAM 1

:IF DATA OK THEN CONTINUE

:DATA ERROR IN MUDULE SELECT RAM 1

HSGHDI

ALINFO
CSCLPI

sCLEAR BITS MSELO H, MSEL®
n, M>AC!? H AND MSAD16 H IN CONTROL REGISTER

;2. MSELO H AND MSE(| W ON A ZERO WILL CAUSE THE SIGNAL SSM L TO BE

:ASSERTED ON A WxITE OR READ TO CONTROL REGISTER 6. ON A WRITE OR READ
:TO CONTROL REGISTER 6, DATA WILL BE WRITTEN OR READ FROM THE MEMORY
:SIMULATOR RAM SELECTED. THE SIHULAFOR MEMORY IS SELECTED VIA THE

;MODULE SELECT RAM'S (0 AND
1

017116
017122
017126
017130
017130
017132
017134
017136
017140
017140
017140

104405

017142

013705

017146
017146

104404

002264
005414

6$:

CLR
JSR
BEQ
ERRDF

R2LOAD
PC.LDRDR2
73
LR2EROR

WORD
WORD
.WORD
ENDSEG

2
O
R2EROR

TRAP

CSESEG

MoV

REG6,R5

BGNSEG
TRAP

C$BSEG

TRAP

7%:
10000$:

002242

ciERor

sSETUP TO CLEAR REGISTER 2
:GO LOAD, READ AND CHECK REG 2
sIF LOADED OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

sPUT THE ADDRESS OF CONTROL REGISTER

INTO RS

sWRITE DATA PATTERN OF 125 INTO LOW BYTE OF MEMORY SIMULATOR ADDRESS
017150

CLR
MOV
MOV
CLR
MOVB

RGMASK
#125,R6LOAD
R6LOAD,R6GOOD
RGREAD
R6LOAD, (RS)

:CLEAR REGISTER 6 MASK WORD
*SETUP BYTE TO BE LOADED
:SETUP EXPECTED DATA PATTERN
:CLEAR DATA TO BE READ (HIGH BYTE)
;WRITE LOW BYTE INTO MEM SIM RAM

MOV

RGREAD,R6BAD

:COPY DATA FOR POSSIBLE ERROR REPORT

BEQ
ERRDF

98
&, MSGMSR,AL INFO

MOVB

CMP

TRAP

.WORD
+WORD
«WORD
CKLOOP
TRAP

(RS),R6READ

R6GOOD , R6BAD

zisnor

*READ THE LOW BYTE BACK FROM RAM

:CHECK BYTE WRITTEN AGAINST WORD READ

:IF LOW BYTE OK THEN CONTINUE
:DATA ERROR READING LOW BYTE OF RAM

MSGMSR
ALINFO

C$CLPY

;WRITE DATA PATTERN OF 252 INTO HIGH BYTE OF MEMORY SIMULATOR ADDRESS

SEQ 0114

HARDWARE TESTS

17-JUN-82 11:26

012737

002310
002304

98:

MOV
MOV

#252,R6LOAD
R6LOAD,R6GOOD

ooooo1

CLR
MOVB

002312

MOV

RGREAD, R6BAD

BEQ
ERRDF

108
& ,MSGMSR,ALINFO

WORD
.WORD
.WORD
CKLOOP
TRAP

&
MSGMSR
ALINFO

002310

MOVB

002312

CMP

TRAP

1 NTa)

023737

b b b
- et

276

17=JUN=-82 12:02 PAGE 115
TEST 26: CHECK MEM SIM RAM'S USING ‘MOVB'* INSTRUCTION

005302
002304
00

(o X W

) =D e
D
d
d
d
D d e
d
D
—d

[+ ]

NNNNN NNNNNNNNNN
WUIWWW
NN

[=leleleleToTo) OCO0O0O00O0O0O0

geege

CVCDAB.P11

MACYN 30A(10$2)

:SETUP DATA PATTERN TO BE LOADED
*SETUP EXPECTED DATA

R6READ

:CLEAR DATA WORD TO BE READ

1(RS),R6READ

sREAD HIGH BYTE BACK FROM RAM

R6GOOD,1(RS)

R6GOOD , R6BAD
C$ERDF

:WRITE HIGH BYTE INTO MEM SIM RAM

:COPY DATA FOR POSSIBLE ERROR REPORT

*CHECK BYTE WRITTEN AGAINST BYTE READ
:IF HIGH BYTE OK THEN CONTINUE
:DATA ERROR READING HWIGH BYTE OF RAM

CSCLP1

;READ THE RAM LOCATION AS A WORD CHECKING THAT THE LOW AND HIGH BYTE
;WERE WRITTEN INTO THE CORRECT BYTE. THE WORD SHOULD BE 125125 IF THE

:BYTES WERE WRITTEN CORRECTLY

017320

002302

002303
002304

108:

MOV

#125,R6LOAD

;SETUP LOW BYTE THAT WAS WRITTEN

JSR

PC ,READRG

:GO READ AND CHECK RAM LOCATION AS WORD

é‘nscnsa.ktxuro

:DATA ERROR = BYTE OPERATION FAILED

MOVB
MOV

BEQ

;::gr

.WORD
-WORD
.WORD
CKLOOP
TRAP

#252.R6LOAD+1
R6LOAD,R6GOOD

*SETUP HIGH BYTE THAT WAS WRITTEN
:SETUP EXPECTED DATA PATTERN

*IF LOW AND HIGH BYTE OK THEN CONTINUE

nsensn
ALINFO
CSCLPY

;WRITE DATA PATTERN OF 252 INTO LOW BYTE OF MEM ORY SIMULATOR ADDRESS
012737
013737
005037

000252

002302
02304

11$:

MOV
MOV

LR
MOVE
MOVB

002312
002312

MOV
cMP
BEQ
ERRDF

TRAP

.WORD
-WORD
.WORD
CKLOOP
TRAP

#252 .R6LOAD
R6LOAD , R6GOOD

RGREAD
R6LOAD, (RS)
(RS),R6READ

RGREAD , R6BAD
nscooo R6BAD
128
& nscnsa.ALxufo

cie

;SETUP DATA TO BE LOADED
:SETUP EXPECTED DATA PATTERN

:CLEAR DATA WORD TO BE READ
:WRITE LOW BYTE INTO RAM LOCATION

*READ LOW BYTE BA(¥ FROM RAM LOCATION
:COPY DATA READ FOR POSSIBLE ERROR

:CHECK BYTE WRITTEN AGAINST BYTE READ
<IF DATA BYTE OK THEN CONTINUE
:DATA ERROR READING LOW BYTE OF RAM

nscnsa
ALINFO
CSCLP1

;READ RAM LOCATION AS * WORD CHECKING THE DATA PATTERN TC BE 125252
7
7

000252
000252

002302
002303

128:

MOV
MOVB

csss.aétqu
52.R6LOAD+1

:BYTE WHICH WAS JUST LOADED
:BYTE THAT WAS PREVIOUSLY WRITTEN

SEQ 0115

| WARDUARE TESTS _WACY11 30A\1osé)
(VCDAB.P11

€922
§923

017456
012464

§925

01747

5924

§926

§927
5928
5929
5930
gg§1

017470
017472

017474
017476
017500
017502
017502

17-JUN-82 11:26

013737
004737

001405

oogsog
00552

17-JUN-82

12:02

002304

104455

104406

017504

012737

000125

5939

017532

116537

000001

017512
017520
0175264

013737
005037
113765

5940

017540

013737

sSETUP EXPECTED DATA PATTERN
:GO READ AND CHECK RAM LOC AS A WORD

ERRDF

& ,MSGMSR,AL INFO

:WRITING LOW BYTE CHANGED HIGH BYTE

MORD
JWORD
.WORD
CKLOOP
TRAP

&
MSGMSR
ALINFO

5942
5943

017554
017556

001405

§945
5946
5947
5948
§3‘§8

017560
017562
017564
017566
017566

000004
002732
004052

002302
002310
002302
002310

002302

002304

13$:

MOV

13§

CS$ERDF

*1F DATA OK THEN CONTINUE

CSCLP1

000001
00231

MOV

RG6READ,R6BAD

BEQ
ERRDF

148
& nscnsa ALINFO

002310

MOVB

CMP

5944

TRAP

017556

#125,R6LOAD

MOV
CLR
MOVB

5941 017546 023737 002304 00231
104455

.WORD
-WORD
.WORD
CKLOOP
TRAP

104406

ggg;

R6LOAD,R6GO0D
RGREAD
R6LOAD,1(RS)

1(RS),R6READ

nmwmw
ci

:SETUP DATA PATTERN TO BE LOADED

*SETUP EXPECTED DATA
:CLEAR DATA WORD TO BE READ
sWRITE HIGH BYTE INTO RAM LOCATION

*READ HIGH BYTE BACK FROM RAM LOCATION
:COPY DATA READ FOR POSSIBLE ERROR

:CHECK BYTE WRITTEN AGAINST BYTE READ
:IF HIGH BYTE OK THEN CONTINUE
:DATA ERROR READING HIGH BYTE

nscnsn
ALINFO

CSCLP1

;READ RAM LOCATION CHECKING DATA PATTERN TO BE 052652

§953
59564
5955
5956

017570
017576
017604
017612

5958

017620

5960
5961
5962
5963
5964
gggg

017622
017624
017626
017630
017630
017630

000004
002732
004052

5967
5968

017632
017634

006301
062737

020000

5970
5971
5972
5973
gg;g

017644

000137

016724

5959

INSTRUCTION

sWRITE DATA PATTERN OF 125 INTO HIGH BYTE OF MEMORY SIMULATOR ADDRESS

§935

5957

‘MOVB'*

R6LOAD , R6GOOD
pg READRG

TRAP

000004
002732
004052

S—

MOV
JSR

BEQ

§?,§,,
5936
§937
5938

PAGE 116

TEST 26: CHECK MEM SIM RAM'S USING

017616

017620

5969 017642
017650
017650
017650

012737
112737
013737
004737

001404

000252
000125
002302
005522

002302
002303
002304

14$:

:SETUP LOW BYTE THAT WAS WRITTEN
:SETUP HIGH BYTE THAT WAS WRITTEN
:SETUP EXPECTED WORD TO BE READ
:GO READ RAM LOCATION AS A WORD

ERRDF

& ,MSGMSR,ALINFO

:WRITING HIGH BYTE CHANGED LOW BYTE

WORD
-WORD
.WORD
ENDSEG

&
MSGMSR
ALINFO

TRAP

CSESEG

ASL
ADD

R1
#MSAD13,R4LOAD

;UPDATE MODULE SELECT RAM 0 DATA
:UPDATE ADDRESS TO O OF NEXT RAM

JMP

:RETURN TO WRITE MODULE SELECT RAM AND
:MEMORY SIMULATOR ADDRESS

TRAP

15$:
100018
:

104405

104401

#252 ,R6LOAD
#125.R6LOAD+1
R6LOAD,R6GOOD
PC ,READRG

BEQ

104455

100402

MOV
MOVB
MOV
JSR

002276

BM]

16$:
ENDTST
L10061:
TRAP

15§

CSERDF

168

CSETST

:IF DATA OK THEN CONTINUE

:IF ADDRESS O OF EACH RAM DONE - EXIT

SEQ 0116

HARDWARE TESTS MACY11 30?(5252)
17-JUN-821
CvCDAB.P11

17=JUN=-82

12:02 PAGE 117
TEST 27: CHECK MEM SIM RAM'S IN 8 BIT MODE

.SBTTL TEST 27: CHECK MEM SIM RAM'S IN 8 BIT MODE
144

THE FOLLOWING TEST WILL CHECK THAT THE MEMORY SIMULATOR RAM CAN BE WRITTEN

sesssss 222828

S WN=O
OV NONWVISS W

6011

017652
017652
017652
017656
017662

004737
005037
012701

017666
017666

104404

N—OOOO.NOMbw

—

T27::

004550
002276
000001

WRITE DATA PATTERN 125252 INTO RAM AND CHECK THE DATA PATTERN
SET _MEMORY SIMULATOR TTO 8 BIT MODE
WRITE DATA PATTERN 031463 INTO RAM + CHECK LOW BYTE FOR DATA UF Ju3
SET MEMORY SIMULATOR TO 16 BIT MODE
READ DATA FROM MEMORY SIMULATOR CHECKING WORD TO BE 125063
SET MEMORY SIMULATOR TO 8 S!T MODE
LOAD ADDRESS 1 OF MEMORY SIMULATOR RAM SELECTED
WRITE DATA PATTERN 146314 INTO RAM + CHECK HWIGH BYTE FOR DATA OF 146000
SET MEMORY SIMULATOR TO 16 BIT MODE
READ DATA FROM MEMORY SIMULATOR CHECKING WORD TO BE 146063

— kb

IN 8 BIT MODE. THIS TEST WILL CHECK 8 BIT MODE AS FOLLOWS:
1. SET MEMORY SiMULATOR TO 16 BIT MODE
LOAD ADDRESS 0_OF MEMORY SIMULATOR RAM SELECTED

4
o

e B0 0000 90 909090 %0900 9099, %9090%;:99%9%;,8%;,8,09,

: AND READ IN 8 BIT MODE. ADDRESS O OF EACH MEMORY SIMULATOR RAM WILL BE TESTED

WHEN AN ERROR OCCURS, THE INFORMATION PROVIDED IN CONTROL REGISTER &
INDICATES THE ADDRESS BEING TESTED AND THE RAM BEING SELECTED.
THE
TABLE BELOW INDICATES THE 4K RAM SELECTED FOR THE ADDRESSES IN ERROR.
1ST 4K OF RAM
ADDRESSES 000000 - 017777
ADDRESSES 020000 - 037777
2ND 4K OF RAM
3RD 4K OF RAM
ADDRESSES 040000 - 057777
4TH 4K OF RAM
ADDRESSES 060000 - 077777

BGNTST
JSR
CLR

MoV

1$:

BGNSEG
TRAP

PC,INITMS
R4LOAD

#BITO.R1

sSELECT AND INIT MEMORY SIMULATOR
sSET 1ST ADDRESS TO BE TESTED 10 0
sSETUP DATA FOR MODULE SELECT RAM 0

C$BSEG

sSET SIGNAL MSELO H TO A ONE AND CLEAR SIGNALS MSEL1 W, MSAD17 H AND
sMSAD16 H IN CONTROL REGISTER 2. MSELO H ON A ONE AND MSEL1 H ON
¢A ZERO WILL CAUSE THE SIGNAL SMDSO L TO BE ASSERTED ON A WRITE OR
:RE:DOCOHHAND TO CONTROL REGISTER 6. SMDSO L WILL SELECT MODULE SELECY

012737

104455
000002
000000

000004
177740
005414

002264
002270

Mov

#MSELO,R2LOAD

l177746.32flASK

sg.toaoa

2. .R2EROR

CSERDF

1003712

?
0
R2EROR

104406

cscLP1

sSETUP BITS TO BE LOADED
sSETUP REGISTER 2 MASK WORD
:GO LOAD,READ AND CHECK REG 2
:1F LOADED OK THEN CONT
sREGISTER 2 NOT EQUAL EXPECTED

SEQ@ 0117

HARDWARE TESTS MACY11 30A(1052)
17-JUN-82 1 1:26
CVCDAB.P11

17-JUN-82
12:02 PAGE 118
TEST 27: CHECK MEM SIM RAM'S IN 8 BIT MODE

603
603

;LOAD THE ADDRESS TO BE TESTED INTO CONTROL REGISTER 4. THE ADDRESS
sWILL APPEAR ON MSAD BITS 15-0 WHICH IS THE OUTPUT OF CONTROL REGISTER 4
017724
017730

004737
001495

005462

2%:

PC,LDRDR

ERRDF

TRAP

104455

000003

017742
017742

JSR

BEQ

000000
004000

LWORD
WORD
.WORD

O
R4EROR

TRAP

CSCLPI

*REGISTER 4 NOT EQUAL EXPECTED

CKLOOP

104406

LRGEROR

C$ERDF

;G0 LOAD,READ AND CHECK REGISTER 4

*IF LOADED OK THEN CONTINUE

sWRITE THE DATA PATTERN INTO MODULE SELECT RAM O AND CHECK THAT iS WAS
sWRITTEN CORRECTLY. THE DATA PATTERNS THAT WILL BE WRITTEN ARE 1, 2, &,

:10,

THESE PATTERNS WILL ENABLE THE SIGNALS ENO H, EN1 H, EN2 H, AND

:EN3 W RESPECTIVELY. THESE SIGNALS ARE USED TO SELECT MEMORY SIMULATOR
¢MEMORY WHEN THE SIGNAL SSM L IS ASSERTED LATER ON IN THE TEST.

017744
017750

010137
012737

002302
177760
005506

MOV

002306

:GET THE PATTERN TO BE LOADED

PC,LDRDR6
48

:GO LOAD, READ AND CHECK RAM 0
+IF OK THEN CONTINUE

#177760,R6MASK

ERRDF

& ,MSGMDO,AL INFO

JSR
BEQ

TRAP

CSERDF

MORD
.WORD
.WORD
CKLOOP
TRAP

017774

R1,R6LOAD

MOV

;SETUP REGISTER 6 MASK WORD

:DATA ERROR IN MODULE SELECT RAM 0

&
MSGMDO

ALINFO

CSCLP1

;SET SIGNALS MSELO M AND MSEL1 H TO A ONE AND SIGNALS MSAD17 H AND MSAD16 W
:TO A ZERO IN CONTROL REGISTER 2. MSELO M AND MSEL1 H ON A ONE. WILL

;CAUSE THE SIGNAL SMDS1 L TO BE ASSERTED ON A WRITE OR READ TO CONTROL
;REGISTER 6. SMDS1 L WILL SELECT MODULE SELECT RAM 1. MSAD BITS 17 AND 16
:ON A 2ERO WILL SELECT ADDRESS O OF MODULE SELECT RAM 1.
017776
020004

012737
004737
001405

000014
005414

002264

4$:

104455

000002
000000
003712

MOV

#MSELO!MSELT,R2LOAD

TRAP

C$ERDF

JSR
BEQ
ERRDF

PC,LDRDR2
58
2, ,R2EROR

.WORD

JWORD
.WORD

:G0 LOAD, READ AND CHECK REGISTER 2
:1F LOADED OK THEN CONTINUE
:REGISTER 2 NOT EQUAL EXPECTED

O
R2EROR

CKLOOP
TRAP

104406

:SETUP BITS TO BE LOADED

CSCLP1

;WRITE THE DATA PATTERN INTO MODULE SELECT RAM 1 AND CHECK THAT THE

sPATTERN WAS LOADED CORRECTLY. A DATA PATTERN OF ALL ONES WILL BE

JWRITTEN,

HOWEVER, WHEN THE LOCATION IS READ BACK, A DATA PATTERN

:EQUAL TO ONE WILL BE READ. SETTING THE LEAST SIGNIFICANT BIT IN

sTHE DATA PATTERN WILL FORCE THE MORE SIGNIFICANT BITS TO ZERO.

020024

012737

000017

002302

5%:

MOV

#BIT3!BIT2!BIT1!BITO,R6LOAD ;GET DATA PATTERN TO BE LOADED

SEQ 0118

HARDWARE TESTS

CVCDAB.P11

MACY11

30A(5g52)

012737
004737
001405

000001
00551

17-JUN-82
1

17=JUN=82 12:02 PAGE 119
TEST 27: CHECK MEM SIM RAM'S IN 8 BIT MODE

002304

MOV

#B170,R6GOOD

;SETUP EXPECTED DATA PATTERN

BEQ
ERRDF

6$
& ,MSGMD1,ALINFO

:IF DATA OK THEN CONTINUE
:DATA ERROR IN MUDULE SELECT RAM 1

JSR

TRAP

104455
000004
002555
004052

WORD
.WORD
.WORD

CKLOOP
TRAP

104406

SEQ 0119

PC,LDRD6R

CSERDF .

:GO LOAD,READ AND CHECK RAM 1

&
MSGMD1
ALINFO
CSCLP1

;CLEAR BITS MSELO W, MSEL1
H, MSAD17 H AND MSAD16 W IN CONTROL REGISTER

+2. MSELO H AND MSEL1 W ON A ZERO WILL CAUSE THE SIGNAL SSM L TO BE

*ASSERTED ON A WRITE OR READ TO CONTROL REGISTER 6. ON A WRITE OR READ
:TO CONTROL REGISTER 6, DATA WILL BE WRITTEN OR READ FROM THE MEMORY

:SIMULATOR RAM SELECTED. tus stULAroa MEMORY IS SELECTED VIA THE
*MODULE SELECT RAM'S (0 AND
1
005037
004737
001404

= OV NOWVSWN=O

104455

020102

104405

020104
020104

104404

CLR
JSR
BEQ
ERRDF

R2LOAD
PC,LDRDR2
78

LWORD
‘WORD
.WORD

2
0
R2EROR

TRAP

000002
000000
003712

b b

d —d —d

b b cd o o o e

d
D
b
b

b e

68:

78:
ENDSEG
10000%:
TRAP

8s:

OO o

b p

6109

002264
005414

BGNSEG
TRAP

2, ,R2EROR
CSERDF

:SETUP TO CLEAR REGISTER 2
:GO LOAD, READ AND CHECK REG 2
*IF LOADED OK THEN CONTINUE
*REGISTER 2 NOT EQUAL EXPECTED

CSESEG
($BSEG

;SET MEMORY SIMULATOR TO 16 BIT MODE
000010
005346

002252

BIC
JSR

#81T8H,ROLOAD
PC,LDRDRO

ERRDF

.ROEROR

BEQ

TRAP

WORD

WORD
"WORD

CKLOOP
TRAP

cieaor

;SETUP TO CLEAR 8 BIT MODE IF SET
:GO LOAD, READ AND CHECK REG 0

*IF LOADED OK THEN CONTINUE

*REGISTER 0 NOT EQUAL EXPECTED

0
ROEROR
CS$CLPY

;LOAD THE ADDRESS TO BE TESTED INTO CONTROL REGISTER &
000001
005462

002276

9%:

BIC

#B1T0,R4LOAD

;CLEAR ODD ADDRESS BIT IF SET

BEQ

loi

SIF LOADED OK THEN CONTINUE

JSR

TRAP

ERRDF

020156

.WORD
-WORD
.WORD

PC,LDRDRG

S!Enor

LRGEROR

RkEROR

:GO LOAD,

READ AND cuecx REGISTER &

*REGISTER 4 NOT EOUAL EXPECTED

[

| HARDWARE TESTS MACY11 30A(1052)
CVvCDAB.P11

6144
6145

020160
020160

17-JUN-8 2 11:26

17-JUN-82 12:02 PAGE 120

TEST 27: CHECK MEM SIM RAM'S IN 8 BIT MODE
CKLOOP
TRAP

104406

CSCLPT

sWRITE DATA PATTERN OF 125252 INTO MEMORY SIMULATOR RAM ADDRESSES
;8Y CONTROL REGISTER &
020162

002302

108:

CLR
MOV

RGMASK
#125252 ,R6LOAD

;CLEAR REGISTER 6 MASK WORD
:SETUP WORD TO BE LOADED

BEQ

11§

:IF DATA OK THEN CONTINUE

JSR

ERRDF

& ,MSGMSR,ALINFO

MORD
.WORD

&
MSGMSR
ALINFO

TRAP

.WORD
CKLOOP
TRAP

020212

PC,LDRDRG

CSERLF

:GO LOAD, READ AND CHECK RAM LOCATION

:DATA ERROR IN MEMORY SIMULATOR RAM

CSCLP1

sSET MEMORY SIMULATOR TO 8 BIT MODE
020214

000010
005346

002252

118:

8IS

#81T8H,ROLOAD

sSETUP TO SET 8 BIT MODE

BEQ

12§

+IF LOADED OK THEN CONTINUE

JSR

ERRDF

TRAP

WORD
WORD
-WORD

CKLOOP
TRAP

PC,LDRDRO

,ROEROR

CSERDF

:GO LOAD, READ AND CHECK REGISTER 0

*REGISTER 0 NOT EQUAL EXPECTED

1
O
ROEROR
CSCLP1

sWRITE DATA PATTERN OF 031463 INTO MEMORY SIMULATOR RAM. ONLY THE
;LOW BYTE 063 SHOULD BE WRITTEN WHEN THE ADDRESS SELECTED IS EVEN.
031463
000063

177400

005514

002302
002304
002306

12%:

MOV
MOV

#31463,R6LOAD
#63,R6G00D

ERRDF

& ,MSGMSR,ALINFO

WORD
.WORD
.WORD
CKLOOP
TRAP

&
MSGMSR
ALINFD

MOV
JSR
BEQ

TRAP

#177400, REMASK
PC,LDRD6R
13§
CS$ERDF

CSCLP1

:SETUP BITS TO BE WRITTEN
:SETUP EXPECTED DATA TO BE READ

:SETUP TO IGNORE HIGH BYTE ON READ
:GGO LOAD, READ AND CHECK LOW BYTE
:IF LOW BYTE OK THEN CONTINUE

:8 BIT MODE FAILED TO WRITE OR READ

;LOW BYTE OF MEMORY SIMULATOR RAM

;RFSET MEMORY SIMULATOR TO 16 BIT MODE
000010
(05346

020322

002252

13%:

BIC
JSR

#81T8H,ROLOAD
PC,LDRDRO

sSETUP TO CLEAR 8 BIT MODE
:GO LOAD, READ AND CHECK REGISTER 0

ERRDF

*REGISTER O NOT EQUAL EXPECTED

BEQ

TRAP

14$

.ROEROR

siéaor

:1F LOADED OK THEN CONTINUE

SEQ 0120

—

HARDWARE TESTS

CVCDAB.P11

6200
6201
6202
gggz

020324
020326
020330
020330

MACY11

30A(1252)

17=JUN=82 11:2

17=JUN-82

0060000
003624
104406

125063

6210 020346

005037

002306

6212

001405

002302

6209 020340 013737 002302 002304
6211

020352

6213

020360

6215
6216
6217
6218
gg;g

020362
020364
020366
020370
020370

020356

020360

004737

14$:

005522

104406

6225

020404

001405

020400
020406

020406

020410
020412
020414
020416
020416

004737

000010

005346

002252

158:

104455

000001
000000
003624

6239

020432

001405

020426

020434

020436
020440
020442
020444
020444

004737

000001

005462

002276

168:

104455

6254

6255

& ,MSGMSR,ALINFO

WORD
.WORD
.WORD
CKLOOP
TRAP

&
MSGMSR
ALINFO

CSERDF

:GO READ AND CHECK 16 BIT WORD

*IF DATA OK THEN CONTINUE

8 BIT MOD® CHANGED WIGH BYTE

CSCLP1

BIS

#81T8H,ROLOAD

;SETUP TO SET 8 BIT MODE

BEQ

168

*IF LOADED OK THEN CONTINUE

JSR

PC,LDRDRO
1, ,ROEROR

CSERDF

:GO LOAD, READ AND CHECK REG 0
*REGISTER 0 NOT EQUAL EXPECTED

1
0
ROEROR
CSCLP1

BIS

#BITO,R4LOAD

BEQ

17$

JSR

104406

PC,LDRDR4

ERRDF

3, ,R4EROR

.WORD
WORD
.WORD
CKLOOP
TRAP

3
0
R4EROR

TRAP

000003
000000
004000

6248
6252
6253

15§

:0DD ADDRESS

052737

6251

PC ,READRG

*SETUP EXPECTED DATA

;SET THE MEMORY SIMULATOR ADDRESS IN CONTROL REGGISTER & TO AN
020420

222'33

R6LOAD , R6GOOD

ERRDF

LWORD
WORD
-WORD
CKLOOP
TRAP

104406

6237
6241

:SETUP TO CHMECK ALL 16 BITS

TRAP

222;2

62642
6243
62446
6245
22229

ROGMASK

ERRDF

6234

6240

CLR

MOV

;RESET MEMORY SIMULATOR TO 8 BIT MODE

052737

6238

;SETUP PREVIOUS LOADED BITS

TRAP

000004
002732
004052

020372

6231
25%

#125063,R6LOAD

JSR

104455

6223

6226
6229

MOV

BEQ

62%5

6227

CSCLPI

:BYTE WAS CHANGED DURING 8 BIT MODE.
012737

6226

0
ROEROR

;READ ADDRESS O OF MEMORY SIMULATOR RAM CHECKING THAT ONLY THE LOW

020332

6224

PAGE 121

WMORD
.WORD
CKLOOP
TRAP

6289

6214

1_0

TEST 27: CHECK MEM SIM RAM'S IN 8 BIT MODE

6208

12:02

———

C$ERDF

:SETUP TO SET AN ODD ADDRESS

:GO LOAD, READ AND CHECK REGISTER &

*IF LOADED OK THEN CONTINUE

*REGISTER 4 NOT EQULA EXPECTED

CSCLP1

;WRITE DATA PATTERN OF 146314 INTO MEMORY SIMULATOR RAM, ONLY THE
020446

012737

146314

020470

004737

005514

002302

020456 012737 146000 002304
020462 012737 000377 002306

020474

001405

178:

;HIGH BYTE, 314, SHOULD BE WRITTEN WHEN THE ADDRESS IS ODD.

MOV

#146314 ,R6LOAD

:SETUP DATA TO BE LOADED

JSR

PC,LDRD6R

:GO LOAD, READ AND CHECK *iGH BYTE

MOV
MOV
BEQ

#146000,R6G00D
#377 .R6MASK
18§

*SETUP EXPECTED DATA
:SETUP MASK TO IGNORE LOW BYTE

:IF HIGH BYTE OK THEN CONJ INUE

SEQ 0121

| HARDWARE TESTS

CVCDAB.P11

6256

6257

58
6259
6260
6261
2§6§
622‘

020476

020500
020502
020504
020506
020506

MACYN

30?(}252)

17-JUN=82 1

17=JUN-82

12:02

104455

020510
020516

6270

020524

6272
6273
6274
6275
222;9

000004
002732
004052
104406

020522
020524

020526
020530
020532
020534
020534

042737
004737

001405
104455

000001
000000
003624

000010
005346

002252

18%:

6286

020564

6288
6289
6290
6291
6292
6293

020566
020570
020572

000004
002732
004052

020576
020602
020602
020602

042737

012737
013737
005037
004737

6298
eggg

020606
020614

062737
10040

6301
6302

0206
0206

020562

001404

020564

104455

CSCLP1

sFAILED TO WRITE HIGH BYTE INTO MEMORY

;SIMULATOR RAM IN 8 BIT MODE

BIC
JSR

#81T8H,ROLOAD
PC,LDRDRO

:SETUP TO CLEAR 8 BIT MODE
:GO LOAD, READ AND CHECK REGISTER 0

ERRDF

1, ,ROEROR

*REGISTER 0 NOT EQUAL EXPECTED DATA

TRAP

LWORD
WORD
.WORD
CKLOOP
TRAP

020616

146063
002302
0023
00552

002302
002304

000137

020622 104401

198:

19§

CSERDF

:IF LOADED OK THEN CONTINUE

1
0
ROEROR
CSCLP1

MOV
MOV
CLR
JSR

#146063,R6LOAD
R6LOAD , R6GOOD
ROMASK
PC ,READR6

ERRDF

&,MSGMSR,ALINFO

WORD
.WORD
.WORD

&
MSGMSR
ALINFO

BIC
ENDSEG

#81T0,R4LOAD

TRAP

CSESEG

BEQ

TRAP

000001

002276

208:
10001$:

104405

629;7! 020604 006301
6303

&
MSGMSR
ALINFO

CSERDF

;READ ADDRESS O AND 1 OF MEMORY SIMULATOR RAM CHECKING THAT ONLY THE
:HIGH BYTE WAS CHANGED DURING A WRITE OPERATION IN 8 BIT MODE
020536
020544
020552
020556

JWORD
"WORD
.WORD
CKLOOP
TRAP

BEQ

104406

6281
6282
6283
6284

6287

& ,MSGMSR,ALINFO

TRAP

6278
222373

6285

ERRDF

;RESET THE MEMORY SIMULATOR TO 16 BIT MODE

6267
6268

6271

TEST 27: CHECK MEM SIM RAM'S IN 8 BIT MODE

2522

6269

PAGE 122

020000

017666

ASL

002276

ADD
BM]
218:
110062

JMP

ENDTST

" IRAP

20§

CSERDF

;SETUP THE DATA PREVIOUSLY WRITTEN
:SETUP EXPECTED DATA
*SETUP TO READ ALL BITS
:GO READ AND CHECK 16 BIT WORD

+IF DATA OK THEN CONTINUE

:WRITING HIGH BYTE IN 8 BIT MODE CHANGED

:LOW BYTE OF DATA
*RESET ADDRESS TO BE LOADED TO 0

;UPDATE MODULE SELECT RAM O DATA PATTERN

:G0 SETUP FOR NEXT MEMORY SIMULATOR RAM

#MSAD13,R4LOAD
218

CSETST

:UPDATE ADDRESS TO NEXT MEM SIM RAM
:1F DONE - THEN EXIT

SEQ 0122

HARDWARE TESTS

CVCDAB.P11

MACY11

_30A(1052)

17-JUN-82

17-JUN-82 11:26

12:02

PAGE 123

TEST 28: CHECK THAT INIT L CLEARS REG O AND INIT H PRESETS RDV AND WRV

2338'3

.SBTTL TEST 28: CHECK THAT INIT L CLEARS REG O AND INIT M PRESETS RDV AND WRV

6306
6307

1ee
;THE FOLLOWING TEST WILL CHECK THAT INIT L CAN CLEAR THE LOW BYTE OF CONTROL

6310
6311

*WHICH SHOULD PRESET(0) RDV AND WRV F/F'S.
THEN ALL ONES ARE LOADED INTO
;THE LOW BYTE OF REGISTER O AND A BRESET INSTRUCTION IS AGAIN ISSUED WHICH

6308
6309

;REGISTER 0O, AND THAT INIT H CAN PRESET THE WRV AND RDV F/F'S. THIS IS
:DONE BY CLEARING(1) RDV AND WRV F/F'S AND THEN ISSUING A BRESET INSTRUCTION

gg}g

:SHOULD CLEAR THE LOW BYTE OF REGISTER 0.

6314
6315
6316
gm

020624
020624
020624

6319
6320
ggg;

020630
020630
020630

004737

128::

004550

128.1:

104402

gg{
020632
020632
020634
020642
020646
020650

6332
6333
6334
6335
6336
6337
6338
6339
6340

020652
020654
020656
020660
020660
020662
020670
020674
020676

000001
000000
003624

6342
6343
6344
6345
23329

020700
020702
020704
020706
020706

000001
000000
003624

6341

JSR

PC,INITMS

;SELECT AND INITIALIZE MEM SIM

BGNSUB
TRAP

($BSUB

;SET SIGNAL RST H TO A ONE, AND THEN TO A ZERO

6325
6326
6327
6328
6329
6330

6331

BGNTST

020650

020676

104404
112737
004737
001405

000001
005346

BGNSEG
TRAP
MOVB
JSR
BEQ
ERRDF

002252

104455

104406
042737
004737
001405

TRAP

000001
005346

104455

002252

1$:

104406

WORD
JWORD
-WORD
CKLOOP
TRAP
BIC
JSR
BEQ
ERRDF

TRAP

.WORD
JWORD
.WORD
CKLOOP
TRAP

($BSEG
#RSTH,ROLOAD
PC,LDRDRO
1$
1, ,ROEROR

CS$ERDF

;SET UP TO SET RST H IN REG 0
:GO LOAD, READ AND CHECK REG 0
*IF OK THEN CONTINUE
:REGISTER NOT EQUAL EXPECTED

1
0
ROEROR
CSCLP1
#RSTH,ROLOAD
PC,LDRDRO
28
1, ,ROEROR

CSERDF

:SET UP TO CLEAR RST H IN REG 0
:GO LOAD, READ AND CHECK REG 0
*IF OK THEN CONTINUE
*REGISTER NOT EQUAL EXPECTED

1
0
ROEROR
CSCLP1

2%‘,,3

;SET SIGNAL MSEL1 H TO A ONE AND MSAD BITS 17 AND 16 TO A ZERO.

6350 020710 012737 000010 002264 2$:
6351 020716 012737 177740 002270

MOV
MOV

6355

TRAP

6352
6353
6354

0207264
020730
020732

004737
001405

6356
6357
6358
6359

020734
020736
020740
020742

000002
000000
003712

020732

104455

005414

JSR
BEQ
ERRDF

WORD
WORD
.WORD
CKLOOP

#MSEL1,R2LOAD
#177740,RIMASK
PC,LDRDR2
3s
2, ,R2EROR

CSERDF

2
0
R2EROR

;SET UP TO SET MSEL1 H TO A ONE
:SET UP TO READ LOWER 4 BITS

:GO LOAD, READ AND CHECK REG 2
:1F OKAY THEN CONTINUE
*REG 2 NOT EQUAL EXPECTED

SEQ 0123

RN
T
'HARDHARE
TESTS
MACYTN
30?(%52)
17=JUN=-82
12:02 PAGE 124
CVCDAB.P11
17-JUN-82"1
TEST 28: CHECK THAT INIT L CLEARS REG O AND INIT W PRESETS RDV AND WRV
23329

020742

104406

TRAP

233?3
6364
6365

:LOAD MSAD BIT 15 THROUGH 8 TO A 0 TO SELECT ADDRESS 0

6367

020744
020750
020754
020756

005037
004737
001405

6369

020760

000003

6268 020756

6370
6371
6372
gg;z

CSCLPY

020762
020764
020766
020766

00227
00546

38:

104455

CLR
JSR
BEQ
ERRDF

TRAP

.WORD

000000
004000

WORD
.WORD
CKLOOP
TRAP

106406

6375
6376
gg;:

R4LOAD
PC,LDRDRS
4
3, ,R4EROR

gitnor

O
R4EROR
CSCLPI

;SET BITS MPIN W AND MUTB H TO A ONE, AND WRE H AND RDE W TO A ZERO.
SWRE M AND RDE W ON A 2ERO WILL CLEAR(1) THE WRV AND THE RDV FLIP;FLOPS, WHEN BIT CK W IS TOGGLED IN CONTROL REGISTER 0.

6379
6380
6381
esa;

020770
020776
021006
021010

012737 000011 oossoz 48:
012737 177760 002306
004737 005506
001405

mov
mov
JSR
BEQ

n;mwm.mw
8177760 ,R6MASK
PC.LDRDRG
5$

6384

021012

104455

TRAP

CSERDF

638

6385
6386
6387
6388
gggg

02101

021014
021016
021020
0.102
021022

6396

104406

021026
021032

052737
052737

000160
000100

021040 004737 005354

6400
6401

021050
021052

6403

021056

fios

021056

104405

6409
6410

021060
021060

104404

6404

24‘8.2
6411

oossu
002252

S$:

JMAP PROTECT RAM DATA ERROR

&
MSGWP
ALINFO
CSCLPY

021

021070 012746

SCKM'WRVM'RDVH, ROGOOD
<M
_ROLOAD

B0
ERRDF
map

of
1 _MSGAPL ALROIN
ceror

NORD
WORD

10564 004100

021056

8ls
s

JSR

000001
002463

68:

100008:

.WORD

ENDSEG

;SET UP EXPECTED DATA
*SET UP BIT TO BE LOADED

:GO LOAD, READ AND CHECK REG 0

IF OK THEN CONTINUE

:WRV F/F OR ROV F/F PROBABLY NOT SET(0)

1
MSGMPL

ALRO'N

TRAP

(SESEG

BGNSEG
TRAP

($8SEG

;ISSUE A BRESET INSTRUCTION. BOTH RDV AND WRV FLIP-FLOPS SHOULD BE SET

wg 021
104433
6413
021064
6414 051066 012746 000340
6415

& MSGMP
AL INFO

;SET UP TO LOAD THE MAP PROTECT RAM
:SET UP REG 6 MASK WORD
:GO LOAD, READ AND CHECK REG 6
SIF OK THEN CONTINUE

;SET SIGNAL CK M IN CONTROL REGISTER O TO CLOCK THE WRV AND RDV F/F'S
;B0TH F/F'S SHOULD BE CLEAR(Y)

6397 02104 001404
6398
021046
6399 8510‘6 104455

640

ERRDF
WORD
.WORD
JWORD
(kL 00P
TRAP

00235
00405

6391
83
639
6395

;SET UP TO SET ALL BITS TO 0
:GO LOAD, READ AND CHECK REG 4
:IF NO ERRORS THEN CONTINUE
*REGISTER 4 NOT ALL ZEROS

021136

BRESET

TRAP
cm;;r
SETVEC #4,478,0PR107
MOV
#PR107 .~ (SP)
mov

#78,-(5P)

;PRESET THE RDV AND WRV F/F'S

SEQ 0124

————

———

_—

—

—_———
e

| HWARDWARE TESTS MACYN 30A(1252) 17-JUN-82 12:02 PAGE 125
CVCDAB.P11

6416
6417

17<JUN=82 11:2

110

TEST 28: CHECK THAT INIT L CLEARS REG O AND INIT W PRESETS RDV AND WRV

021076 012746 000004
021100 012746 000003

MOV
MOV

#6,~(SP)
#3,-(SP)

6419 0 nog oeirog 000010

ADD

#10,SP

MOVB

IDDEV+1,1(RS)

6418

021104

10443

6420

021112

01370

6421

021116

113765

64 g 021126 000240
u.s

021126

6425

021132

oossy.

002245

TRAP

MOV

000001

NOP

CLRVEC

6426 021126 012700 000004

MOV

2‘;,%‘7’ 021134

B8R

104436

TRAP

000420

CSSVEC

REGO, RS

:SAVE ADDRESS OF REG 0

;RELEASE TIMEOUT VECTOR

#4 RO

CSCVEC

*SAVE ID NUMBER

;1F NO DEVICE TIMEOUT THEN CONTINUE

6428

;A DEVICE TIMEOUT OCCURED WHICH INDICATES THAT THERE IS NO DEVICE 0

6431

:DOES A READ/MODIFY WRITE.

:IN THE SYSTEM, THEREFORE, THE MEMORY SIMULATOR WAS TO BE RESELECTED
:BY DOING A “MOV WORD'' OPERATION. A ‘MOVBTM OPERATION PERFORMED ABOVE

gg%

6434
6435
6436

021136
021140
021142

005726
005726

021146

104436

78:

ST
ST
CLRVEC

(SP)+
(SP)+
#%

;CLEAN UP THE STACK FROM TIMEOUT
:
:RELEASE DEVICE TIMEOUT VECTOR

TRAP

;SETUP TO LOAD ALL ZEORES (RESULT OF INIT)
*RESELECT THE DEVICE AFTER “‘INIT'*
+1F LOADED OK THEN CONTINUE
S“INIT'* FAILED TO O RDV OR WRV F/F'S

6437 021142 012700 000004

MOV

6439
6440
6441
6442

CLRB
JSR
BEQ
ERRDF

CSCVEC
ROLOAD
PC,LDRDRO
98
1, ,ROEROR

LWORD

6443

6444

021150
021154
021160
02116

105037
004737
001417

021164

000001

021162

002252
005346

104455

6445
6446
6447
6448

021166
021170
021172
021172

6451
6452
6453
6456

021176
021202
021206
021210

105037
004737
001404

6456
6457
6458
6459
6460
6461

021212
021214
021216
021220
021220
021220

000001
000000
003624

6463
gzgg

021222
021222

6466
6467
2,,”23

021224
021224
021224

TRAP

000000
003624

WORD
.WORD
CKLOOP
TRAP

104406

gzgg 021174 000411

6455

021210

mg 021222

6470
6471

THEREFORE, IF THERE IS NO DEVICE O IN THE

:SYSTEM, A DEVICE TIMEOUT WILL OCCUR TO ADDRESS 4.

002254
005362

8s:

104455

104405
104403

104402

L10064:

128.2:

CSERDF

O
ROEROR
CSCLPI

B8R

;G0 TO END OF SEGMENT IF NO LOOPING

CLR8
JSR
BEQ
ERRDF

ROGOOD
PC,READRO
98
1, ,ROEROR

;CLEAR LOWER BYTE OF EXPECTED DATA
:GO READ AND CHECK REG 0
:IF OK THEN CONTINUE
*REGISTER 0 NOT EQUAL EXPECTED

WORD
WORD
.WORD
ENDSEG

1
0
ROEROR

TRAP

CSESEG

TRAP

CSESUB

TRAP

98:
10001$:

#4 RO

ENDSUB

CSERDF

BGNSUB

TRAP

($BSUB

;CHECK THAT RST M, CTS W, MP W, 8 BIT H AND CK H CAN BE SET TO 1.
:RDV H AND WRV H WILL BE CHECKED TO BE 0.

SEQ 0125

HARDWARE TESTS

CVCDAB.P11
7

647

MACY11_30A(1052)
17=JUN-8 21 1:26

021226
021226

J 10

17-JUN-82
12:02 PAGE 126
TEST 28: CHECK THAT INIT L CLEARS REG O AND INIT H PRESETS RDV AND WRV

BGNSEG
TRAP

002252

#RSTH!CTSH!MPH!BIT8H'! CKH,ROLOAD ;SET ALL R/W BITS TO 1
PC,LDRDRO
:GO LOAD, READ AND COMPARE REG 0
1$
*IF OK THEN CONTINUE

TRAP

CS$ERDF

ERRDF

1$:
100008:

021254

($BSEG

BIS
JSR
BEQ

,ROEROR

WORD
WORD
.WORD
ENDSEG

1
O
ROEROR

TRAP

CSESEG

;ISSUE A BRESET INSTRUCTION.
021256

BGNSEG

104404

TRAP

104433

BRESET
TRAP

012746
012746

MOV

SETVEC

000001

:CLEAR THE LOW BYTE OF REG 0

CSRESET

MOV
MOV
MOV
ADD

#10,SP

;SETUP INCASE OF DEVICE TIMEOUT

CSSVEC

MOV
:gxa

REGO,RS
IDDEV+1,1(RS)

:SAVE ADDRESS OF REG 0
*SAVE ID NUMBER

CLRVEC
MOV

#4
#4 RO

:RELEASE TIMEOUT VECTOR

B8R

:NO DEVICE TIMEOUT = CONTINUE

TRAP

021332

THE R/W BITS SHOULD THEN BE ZEROS.

($BSEG

#4,428,#PR107
#PR107.~(SP)
#28,-(5P)
#4,~(SP)
#3.-(SP)

TRAP

:R/W BITS NOT ALL SET

CSCVEC

;A DEVCICE TIMEOUT OCCURED WHICH INDICATES THAT THERE IS NO DEVICE #0
:IN THE SYSTEM, THERFORE, THE MEMORY SIMULATOR WAS TO BE RESELECTED BY
:DOING A "MOV WORD'' OPERATION. A ‘'MOVB'' OPERATION PERFORMED ABOVE DOES
:A READ/MODIFY WRITE.
THERFORE, IF THERE IS NO DEVICE #0 IN THE SYSTEM,
:A DEVICE TIMEOUT WILL OCCUR TO ADDRESS &.
28:

002252
005346

CLRVEC
MOV

#%
#4 RO

CLRB
JSR
BEQ
ERRDF

ROLOAD
PC.LDRDRO
s
1, .ROEROR

WORD
WORD
.WORD

1
0
ROEROR

TRAP

021
021370

(SP)+

:CLEAN UP THE STACK FROM TIMEOUT

(SP)+

*RELEASE TIMEOUT VECTOR

CSCVEC

;SETUP TO LOAD ALL ZEROES
:GO LOAD, READ AND CHECK REG 0
*IF LOADED OK THEN CONTINUE
*REGISTER 0 NOT EQUAL EXPECTED

CS$ERDF

SEQ 0126

| WARDWARE TESTS MACY11 S0AC1052)
CVCDAB.P11

17=JuN-82 11:26

17-JUN-82 12:02 PAGE 127

TEST 28: CMECK THAT INIT L CLEARS REG O AND INIT M PRESETS ROV AND WRV

6528 ogmo 104406

021372

000411

6531

02137

1oso§r

6534

021406

6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546

021410
021412
021414
021416
021416
021416
021420
0214
021420
021422
021422

6548

021224

6532
6533

6535

TRA®

°°2§2'5

021400 004737 005
021404 001404
021406

3s:

104405
104403

6547 0214,52 104401

CSCLPI

‘8

;CONTINUE IF NO LOOPING

CLRB

ROGOOD

;CLEAR LOWER BYTE OF EXPECTED

*REG 0 NOT EQUAL TO EXPECTED

JSR
BEQ

PC,READRO
8

TRAP

CSERDF

ERRDF

104455

000001
ooo}ggo
003624

K 10

.8:
100018:
L10065:
L10063:

,ROEROR

JNORD
WORD
«
ENDSEG

1
0
ROEROR

TRAP
ENDSUB

CSESEG

TRAP

(SESUB

TRAP

ENDMOD

CSETST

:GO READ AND CHECK REG 0
:IF OK THEN CONTINUE

SEQ 0127

PARAMETER CODING

CVCDAB.P11

MACY11

17=JUN-82 11:26

30A(1052)

17-JUN-82

12:02

TEST 28: CHECK THAT INIT L CLEARS REG O AND INIT W PRESETS RDV AND WRV

8349

.TITLE PARAMETER CODING

6351

.SBTTL

021424
P

~NOo~

eew

;
:

6558
6559
6560

6566
6567
6568
2293

: WITH THE OPERATOR.

Joe
021424
021424
021426

000011

LSHARD::

:HARDWARE P-TABLE QUESTIONS
:

gg;%

6574

6591
659
659
6594
6595
96
6597
6598
6599
6600
6601
6602

BGNHRD
.WORD L10066~LSHARD/2

6571

6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588
6589
6590

THE HARDWARE PARAMETER CODING SECTION CONTAINS MACROS
THAT ARE USED BY THE SUPERVISOR TO BUILD P=TABLES.
THE

: MACROS ARE NOT EXECUTED AS MACHINE INSTRUCTIONS BUT ARE
: INTERPRETED BY THE SUPERVISOR AS DATA STRUCTURES.
THE
: MACROS ALLOW THE SUPERVISOR TO ESTABLISH COMMUNICATIONS

6561

6562
6563
6564
6565

HARDWARE PARAMETER CODING SECTION

BGNMOD

wvwh

6553
6554
6555

L 10

PAGE 128

:
021426
021426
021430
021432
021434
021436
021436
021440
021442
021444
021446

.
000031
021450
000000
177777

001032
021464
177777
000000
000017

021450

L10066:

ASK FOR CDS MEMORY SIMULATOR CSR ADDRESS

ASK FOR CDS MEMORY SIMULATOR DEVICE NUMBER

GPRMA
.WORD
.WORD
.WORD
WORD
GPRMD
.WORD
.WORD
WORD
WORD
LWORD

MSG1,0,0,0,177777,YES
TSCODE
MSG1
TSLOLIM
TSHILIM
MSG2,2,0,177777,0,000017,YES
TSCODE
MSG2
177777
TSLOLIM
TSHILIM

ENDHRD
.EVEN

H
:HARDWARE P-TABLE MESSAGES
3

021450
021456
021464
021472
021500

051503
051104
042506
047040
000122

020122
051505
044526
046525

042101
000123
042503
042502

MSG1:

.ASCIZ

/CSR ADDRESS/

MSG2:

.ASCIZ

/DEVICE 1'"JMBER/

.EVEN
.SBTTL

SOFTWARE PARAMETER CODING SECTION

SEQ 0128

17-JUN=-82 11:26

PARAMETER CODING

CVCDAB.P11

S W00 CONOWVIS W=D

SRR 388222222 g

6605
6606
6607

MACY11 30A(1052)

mn10
17-JUN-82 12:02
PAGE
129
SOF TWARE PARAMETER CODING SECTION

PAGE 12

SEQ 0129

iee

: THE _SOF TWARE PARAMETER CODING SECTION CONTAINS MACROS

THAT ARE USED BY THE SUPERVISOR TO BUILD P-TABLES.

THE

MACROS ARE NOT EXECUTED AS MACHINE INSTRUCTIONS BUT ARE

: INTERPRETED BY THE SUPERVISOR AS DATA STRUCTURES.

THE

MACROS ALLOW THE SUPERVISOR TO ESTABLISH COMMUNICATIONS
WITH THE OPERATOR.

021502

000000

LSSOFT:

BGNSFT
.WORD L10067-L$SOFT/2

.EVEN

021504

021504
021504
021504

L10067:
000010

SPAT(CH::

021524
021524
021526
021530
021530

021540
000004

LSLAST::

021530
000000
000002

163010
000000

021540

.BLkW

LASTAD
.EVEN
.WORD TSFREE
.WORD TSSIZE
ENDMOD
BGNSETUP
BGNPTAB

L10070:

L10072:
000001

ENDSFT
.EVEN

.END

LWORD
.WORD

0
L10072-./2-1

.WORD
WORD

ENDPTAB

ENDSETUP

163010

PARAMETER CODING

MACY11

ADR
= 000020 G
ALINFO 004052 G

13454

CVCDAB.P11

17-JUN-82 11:26

ALROIN

004100 G

ALR2IN

004126 G

ASSEMB= 000010
BITO '= 000001 G

BIT00 = 000001
BITO1 = 000002
BIT02 = 000004
BITO3 = 000010
BIT04 = 000020
BITOS = 000040
BIT06 = 000100
81107 = 000200
BITO8 = 000400
BITO9 = 001000
BIT1
= 000002

G
G
G
G
G
G
G
G
G
G
G

BIT10 = 002000 G
BIT11 = 004000 G
BIT12 = 010000 G

BIT13 = 020000 G
BIT14 = 040000 G
BIT15 = 100000 G
BIT2 = 000004 G
BIT3

= 000010 G

BIT4
BITS
BIT6
BIT7
BIT8
BIT8H
BIT9
BOE
CKH

= 000020 G
= 000040 G
= 000100 G
= 000200 G
= 000400 G
= 000010 G
= 001000 G
= 000400 G
= 00C10C G

CTSH = 000002 G
CSAU_ = 000052
CSAUTO= 000061
C$BRK = 000022
C$BSEG= 000004

17338
4185

4883
5576
6095
17460
3860

1759

4013
1094
1318#
5163
6136
1307#
1306#
13054
13044
1303#
1302#
13014
1300#
1299#
1298
13174
5240
12974
12964
12954
12944
12934
1292#
13164
5240
13154
4808
13144
13134
1312
13114
13104
13794
13094
13494
13764
3754
13814
10944
10944
10944
10944

2579
3190

4734

C$B8SuUB= 000002

5844
10944

30A(1052)

17-JUN-82

N_10

PAGE 131

CROSS REFERENCE TABLE == USER SYMBOLS

2945
4271
4985
5629
6158
3437
3873

2958
4349
5020
5685
3187
468
3997

4056

4096

1383

3126

12:02

3m
4382

3140
4413

3232
4445

3300
4516

SEQ@ 0130

5248
5879
6387
3580
4083

3320
457

3425
4642

351
4686

3705
4781

379N
4816

3985
4869

3593
6402

377

3748

3762

3803

3833

3607

3733

3775

3816

3845

3887

5055
5782
3217
482
4028

5116
5817
6260
3523
4043

5213
5861
6290
3553
4070

1406

1427

1433

4167

4253

4731

4808

4809

4933

6010

5012
6087

5013
6088

1405
5809
1417
1416

1426
6087

1434

4169

4255

4257

4342

4405

4808

5012

1425
6087
1424
5568
2527
1422
1421

1435

4169

4173

4175

4255

4259

4261

4808

5012

1436
5809
4280

4169
6087
4649

- 4173

677

4255

4259

4263

4375

4437

4693

4899

5063

5317

5647

2792
6123

2820
6164

6194

6223

6267

6475

3460

3461

3474

3475

3545

3546

3740

3741

2510
2902
4612

2562
3034
4656

3155

2457

2529

2531

4020

4021

4035

4036

6394

6395

6475

1927
2605
3255

1972
2622
3306

1989
2657
3350

2007
2691
3630

2025
707
909

2068
2737
4125

2410
2753
4224

2428
2780
4303

2456
2809
4470

2474
2842
4528

6119
2448

6326
2556

6410
2597

6474
3186

6490
3246

6321

6468

4824

6013
2404

4937

5074

5166

5568

3565

5256

5569

5327

5732

5370

5809

5423

5810

5409
5947

2411

3826
6475

5490

3536

5395
5929

1412
1398
5809
1397
5240
1423
1393
1392
1420
1419
2475
1418

3825
2475

5489

3495

5354
5914

5240
6237
1318
1317
1316
1315
1314
1313
1312
1311
1310
1309
1381
5568
1370
1369
1415
1414
1413
1362
1380
5568
1379
5012
1378
1377
1376
1391
1372
2411
1371
3755
2411
2346
2275

5241
6292

3453

5301
5896

5494

5584

5449
5962

5658

5541
6060

5735

PARAMETER CODING

CVCDAB.P11

CSCEFG= 000045
00006
00001
000635
00000&

CSCLCK=
CSCLEA=
C$CLOS=
CSCLPT=

MACY11

17-JUN-82 11:26

3128
34720
3691
3875

5382
5801
6132
6350
1094#
10944
10944
1094#
10944
109#
1094#
2480
¢85
3150
3436
3646
3830

CSESUB= 000003
CSETST= 000001

CSEXIT= 000032
CSGETB= 000026
CSGETw= 000027
CSGMAN= 000043

12:02

PAGE 132

CROSS REFERENCE TABLE == USER SYMBOLS

SEQ 0131

2301
1053

2048

2087

257

4156
4SS5
5004

4262
4627
5022

4321
4670
5040

4335
4752
5090

3142
34
3707
3929

5397
5819
6145
6373
1964

2323
1156
1948
2518
gler

3200
3450
3658
3842

40u0

4053

4964

4982

4363
4639

CSERHR= 000056
CSERRO= 000060
CSERSF= 000054
CSERSO= 000057
CSESCA= 000010
CSESEG= 000005

17-JUN-82

10944

10944
109#
1094#
109¢r

41642
4540
4987

CSCVEC= 000036
CSDCLN= 000044
£$DODU= 000051
CSDRPT= 000024
CSDU = 000053
CSEDIT= 000003
CSERDF= 000055

30A(1052)

5245
5538
5832
6110
6331
10944
1094#
10944
10944
10944
10944
2590
3235
4819
5965
10960
1%k
3336
5974
1094¢
10944
1094#

3205
BT
3719
3943

5435
5863
6160

3218
B3
3735
3958

3270
P
3750
3971

2o31

4351
4765
5102

4368
4783
5184

4384
4800
5197

3283
B
3764
3987

3398
3e2
380
4030

5602
5949
6232

5614
6031
6246

4398
4B42
5215

3067
3411
Bes
818
4045

3427
ele
3835
4058

3439
e
3847
4072

5671
6044
6262

4415
4854
5232

5766
6079
6336

o758
3108
339
577
788
3996

oree
3123
06
3590
3800
4010

2462

2813
%17
3422
3604
3813
4025
4346
4622
4950

6505

6518

1958

1978

1996

2012

2043

2053

208

44BO
4795

4182
4495
4813

42
4513
4837

4268
4537
4849

4316

4330

5192

5446
5779
6057
6257
6535

5210

2610
gz
3265
3492
3702
3884

2627
955
3278
3508
3714
392

2661
M8
3297
3520
3730
3938

2696
ez
33
3533
3745
3953

271
o8
366
3550
3759
39

74
Joo1
3378
356
377
982

4080

4098

4137

4151

5269
5555
5858
6127
6341

5281
5573
5876
6140
6355

5017

5298
5597
5893
6155
6368

5035

5335
5609
5911
6168
6384

5052

5351
5626
5906
6184
6399

5085

5377
5666
5944
6198
6443

5392
5682
5959
6214
6455

5406
5748
6026
6227
6479

5430
5761
6039
6241
6523

1967
2616
3303

1984
2633
3323

2002

2018

2062

2101

2422

2440

2468

5119
6405
2593
2335

5251
6461
2636
2630

4999

5058
6295
2490
oL

3893
6547
2293

4410
4747

2667
3610

4425
4760

2702
3890

4102

4199

4580

4696

4442
4778

2718
4099

5304
6485
3243
2678

4284

2748
4189

5357
6541
3331
2721

4451

5097

5113

55
78
3862
4085

5753
6
6276

6438

2584
g6
3229
3479
3686
3870

3113

4500
4969
5340

4067
4393
4683

3613
6303
2250

4430
4871
S274

3096

4485
4955
5286

4379
4665

4886
6116
2644
g38.

6425

2567
13
3213
3465
3673
3857

5560
5931
6219

3053

3383
e
3793
4015

2057

6528

5543
5916
6203

3369
B
3777
3999

5512
5881
6173
6448
2098

6389

5525
5898
6189

2918

5179

4550
4

4568
4880

5784
6097
6346

S227

5507
5796
6074
6271

5530
5814
6287

2526

2573

2766
4274

2790
4448

2819
4519

2873
4574

2961
4645

$158
4689

6464
767

6544
2196

297

$126

5459

563

5412

459

5453

4704

5579

4904

5632

5688

5838

PARAMETER CODING

CvCDAB.P11

CSREVI= 000003
CSRFLA= 000021
CSRPT = 000025
CSSEFG= 000046
CS$SPRI= 000041
CSSVEC= 000037
C$TPRI= 000013
DFPTBL 002216 6
DIAGMC= 000000
EF .CON= 000036 G
EF .NEW= 000035 G

EF .PWR= 000034 G
EF .RES= 000037 G
EF.STA= 000040 G
EMSGRO 003046 G
EMSGR2 003076 G
EMSGRG (003126 G
EMSGR6 003156 ©
ERRBLK 002232 G
ERRMSG 002230 G
ERRNBR 002226 G
ERRTYP 002224 G
ESRH = 000040 G
B
G
ESEND = 002100
ESLOAD= 000035

003256 G
003363 G
000015
000020

F$BGN = 000040

30A(1052)

10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944

2228

17=JUN-82 11:26

CSGPHR= 000042
CSGPLO= 000030
CSGPRI= 000040
CSINIT= 000011
CSINLP= 000020
CSMANI= 000050
CSMEM = 000031
CSMSG = 000023
CSOPEN= 000034
CSPNTB= 000014
CSPNTF= 000017
CSPNTS= 000016
CSPNTX= 000015
C$QI0 = 000377
CSRDBU= 000007
CSREFG= 000047
CSRESE= 000033

FRMTRO
FRMTRG
FSAU =
FSAUTO=

MACY11

10944
10944

10944
10944
10944
10944
10944

12484
1094
13254
13264
13274
13244
13234
1581#
15854
15894
1593»
14504
144694
14484
14474
13930

17-JUN-82

12:02

PAGE 133

CROSS REFERENCE TABLE == USER SYMBOLS

SEQ 0132

2258

1687

1710

1730

1743

1756

1769

1781

1793

1805

1667

1695

1718

1738

1751

1764

1777

1789

1801

1678

1706

1726

1811

1822

1828

1839

1845

1853

1859

1870

2199
2213

2204
6412

2209
6492

2216

2222

2031

2074

6418

6498

3119

3147

3445

3446

3488

3529

3725

3726

3768

3809

4005

1703
1850
2345
2274

1819

1836

1867

1281
2007

106%
ZgZ

1690
2068

1713
3146

1733
2151

1746
5158

1759
5164

1772
2180

1784
2196

1796
2250

Nd
3%0

Wil
612

1155

2170
2246
1933

2221
2215
2208
2203
2198
1664
1692
1715
1735

zazg

1748
1761

134

10944
1094#

16054
16174
10944
10944

1094#
1927

2270
2610
2562

e
3255

1179

1675
1723
2334
2270

1101
1972

2285
24;8
2579

W%
;306

1276
1989

2293
5443
592

G
5330

23n
5447
596

i
%33§

2317
2456
5605

B
%347

2334
gk?‘
622

340
429
635

2349
5493
638

G
639

355
2506
651

e
630

376
2510
2657

ye
3892

2383
5534
672

G
3906

2399
5550
685

p@
3909

2403
2555
2691

892
4101

]

. PARAMETER CODING
MACY1 1 30A(1052)
17-JUN-82 12:02 PAGE 134
| CVCDAB.P1T
17=JUN-82 11:26
CROSS REFERENCE TABLE == USER SYMBOLS
6119
4593

FSCLEA= 000007
FSDU
= 000016
FSEND = 000041

5125
5729
ggzz

4125
4606

SlgO
5735
6474

4198
4612

10944
10944
109+

2285
2311
1101

2300
2322
1276

2293
2423
2536
2638
2765
2875
3242
3627

2302
2441
2536
2640
2766
2877
3244
3891

2315
2443
2550
2651
2768
2896
3245
3892

1968

4275
4606
5120

FSHARD= 000004

FSHW =
000013
FSINIT= 000006
FSJMP = 000050
F$MOD = 000000
FSMSG = 000011
FS$PROT=
FSPWR =
FSRPT =
F$SEG =

000021
000017
000012
0000C3

F$SOF
T= 000005
FSSRV = 000010
F$SUB = 000002
FS$SW = 000014
FSTEST= 000001

GSCNTO= 000200
GSDELM= 000372
GSDISP= 000003

5633
6304
6548
10944

10944
1094#
10944
1094
10944

1772

10944
10944
10944
1094#

2610
2589
2753
3234
4224
4818
5370
5964

1985

4283
4646
5125

5689
6316
6549
6565
1246
2196
2162
1101
1662

1780

5166
5844
6490

2003

4285
4690
5127

4224
4696

1281

1688

2324
2445
2555
2668
2776
2962
3304
3894

<38
2647
2574
2672
2791
2969
3324
3906

525
507
6543

2019

5327
6007
6546

2743

5370
6013
6549

1711

2102

4299
4728

5423
6119
6554

1731

2146

4303
4734

5458
6302
6565

1744

2151

4450
4824

5487
6316
6616

1757

2162

4464
4903

5494
6320
6635

1770

217

4470
4929

5584
6326
6637

1782

2250

4528
4937

5658
6410
6638

1794

2259

4580
5074

5695
6463
6644

1806

2276

2347
2469
2591
2674
2795
297
3330
4100

2349
2487
2592
2685
2797
3058
3332
4101

2355
2489
2594
2703
805
159
3333
4103

2376
291
2596
2719
820
166
3335
4119

2383
2493
2617
2720
2823
3168
3347
4190

2385
2495
2634
2722
2825
3182
3611
4198

2399
2506
2635
2731
2839
3185
3612
4200

2403
2525
2637
2749
2874
3236
3614
4218

5839
6463
6635

5966
6465
6637

5973
6467
6638

5975
6486
6644

6007
6542
6646

6117
6543

6296
6545

6302
6546

6549

6554

6635

1742

1746

1755

1759

1768

2017

2025

2061

2068

2100

5729
6462
6625

2293
1281
1690

2315
2146
1709

2338
2151
1713

4580
2349
1729

2355

2428
2615
2780
330
430
4885
5423
6115

1972
2439
2622
2789
3306
4447
4937
5452
6119

1983
2456
2632
2809
3322
4470
5057
5494
6294

1989
2467
2657
§818
350
4518
5074
5578
6326

2001

2474
2666
842
609
4528
5118
5584
6404

2007

2485
2691
5872
630
4573
5136
5631
6410

2510
701
902
889
6612
5250
5658
6460

2523
2707
%960
909
4644
5256
5687
6474

256
4
034
4098
465
530
5735
6484

257;
§73
157
4125
4688
5357
5837
6490

2579
%7&7
190
4188
4734
5356
5844
6540

5695
6320
6554
6590
1255
2257
2250
1276
1686

1784

2187

2158
1927

2169
1966

1792

4449
4703
252

4283
4703

4299
4696
5160
5697
6406
6592

2180

2421
2605
2763
3255
4273
4824
5611
6013

4218
4656

SEQ 0133

1796

4450
4705
5305

1804

4452
4728
5358

4464
4820
56413

4520
4887
5454

4575
4903
5458

4580
4905
5460

4593
4929
5487

4595
5059
5580

10944
10944
10944

6616

6623

2404

2443

2448

2489

2556

2592

2597

2635

3186

3242

3246

3330

10944
10944

1267
2377

1273
2383

2400

2493
%806

507
823

2840

2551
2875

638

2652
2969

672

686

720

4283
5488

4300
5695

6321
§73

33
4465
5973
1094#
10944
1094#

6463
766

348
4593
6008

6468

61
460
6302

6543
795

628
4703
6317

89
472
6546

907
4903

4101

41%0
5125

897

4198
5161

6219
5458

166

183
4450

PARAMETER CODING

CVCDAB.P11

17-JUN-82 11:26

GSEXCP= 000400
GSHILI= 000002
G$LOL1= 000001
= 000000
G‘OFFS- 000400
GSOFSI= 000376
GSPRMA= 000001
GSPRMD= 000002
GSPRML= 000000
GSRADA= 000140
GSRADB= 000000
GSRADD= 000040
GSRADL= 000120
GSRADO= 000020
GSXFER= 000004
GSYES = 000010
HELP = 000000

HOE
IBE_

= 100000 G
= 010000 G

lDDEV
IDH
IDTVPE
IDU
=
IER_
=
INITMS

002246 G
100000 G
002250 6
000040 G
020000 G
004550 G

ISR
= 000100 G
IXE
= 004000 G
ISAU_ = 000041
ISAUTO= 000041
ISCLN = 000041
ISOU = 000041
ISHRD = 000041
ISINIT= 000041
ISMOD = 000041
ISMSG = 000041
ISPROT=
ISPTAB=
ISPWR =
ISRPT =
ISSEG =

000040
000041
000041
000041
000041

HACV11

1094#
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
10944
1092
1650
21478
23514
1356#
1353#

14614
1362
14634
13464
13544
19264
3183
5730
13474
13524
10948
10948
10944
10944
65654
10944
109644
10944
17728
10944
10944
10944
10944
10960

2376
25104
2651
776
0344
36114
4299
4728
52564
56584

30A(1052)

17-JUN-82

E.N

PAGE 135

CROSS REFERENCE TABLE == USER SYMBOLS

6576
6576
6576
6581

6581
6581

6576

6581

6576
1094
1652

6581
1109
1681

2160
2373

12:02

2165
2374

SEQ 0134

1197
1885
2188

1236
1890
2248

1253
1893
2253

1271
1901
2272

12764
1904
2291

2379

2380

6548

6550

6587

1279
1911
2296

6603

1287
1918
2313

6619

1444
1922
2318

1502
1924
2336

6626

629

1925

1938
1973
1974

1990
2243
2243+

2261%

2242«

2286

6421

6501

2377
3348
6008

2400
3628
6317

2507
3907

2551
4120

2652
4219

2686
4300

2732
4465

2777
4607

2806
4729

2840
4930

2897
5161

3029
5488

23344
22704
22854
23114
65924
21964
11014
16624
17824
21804
66384

23474
22764
2293
23244

22594
12814
16904
17944

21464
17114
17964

21514
1713
18064

2349@
17310

23554
17338

65494
1744k

65544
17468

66354
17578

1759

1770#

6644N

21584
19274
2399
25254
26574
7804
159#
3627
43034
L7340
53054
56894

21714
19684
2403
2550
6684
914
182
36304
4449
4850‘
53274
5729

19724
26104
255
2685
805
5
38914
4464
4824
53584
57354

19854
24234
5624
6914
809#
1904
906
L4708
4BB7F
S3704
5839

19894
2428
S74m
7034
g& o#
2364
39094
45204
4929
S413@
5844w

20034
2441M
25798
27074
5339
45
41004
6558’
49374
54234
59664

20074
2447
25914
2719
584 ¥
2554
4119
45754
50594
54544
6007

20194
24564
2596
2731
%g?&‘
04
41254
4606
50744
5487
6013

20254
24698
26054
27378
§g96
06#
41908
46128
5120
54944
6117¢

20634
2474m
26178
2749%
902#
3244
4218
L6468
5160
55804
6119#

2250
12764
16884
1784w

2302#

2487
2622#
275
#
34
4224m
4L6S6H
51664
S5584#

2102#

2634k
7654
33504
42754
5252#

563
6316

PARAMETER CODING

CVCDAB.P11

30A(1052)

6320
10944
66164
10944
10944
25944
31854

63264
66374
66254

6406H
6638

64104
66464

6462¥

6467

6474h

64BOX

64904

65424

%376
3964
32424
4728

399
6354
244w

4929

24034
26374
32454
5160

26434
2651
33304
5487

2445K
685
332
5729

2447H
2731
3347
6007

2489%
776
627
6316

24914
2805
3906
63204

2506
2839
4119
64634

2550
2896
4218
64654

25554
3028
4299
64678

2592#
3182
4464
65434

109644
2555
Q7768
31664
39064
4580
S160#
6320

23764

23834

23854

23994

2403

2447

24934

24954

25064

2534

17-JUN-82 11:26

ISSETU= 000041
ISSFT = 000041
ISSRV = 000041
I1$suB = 000041

gggg'

ISTST = 000041

JSJMP = 000167
LDRDRO 005346 G

LDROR2

005414 6

LDRDRSG

005462 G

LDRDR6

005506 G

LDRDOR 005354 G
LDRD2R 005422 G
LDRD6R 005514 G
LOE
= 040000 G
LorT
=
106
LSACP
002110 G
LSAPT
002036 G
LSAU
G
LSAUT
002070 G
LSAUTO 005746 G
LSCCP
002106 G
LSCLEA 005750 G
L$CO
002032 G
LSDEPO 002011 G
LSDESC 002326 G
LSDESP 002076 G
LSDEVP 002060 G
LSDISP 002124 G
LSOLY
002116 G
LSOTP
002040 G
LSDTYP 002034 6
LSDU
G
LSDOUT
002072 G
LSOVTY 002314 6
LSEF
002052 G

F.1

MACY11

1094¢
1993

2596
27954
31684
41004
45934
54584
6467

2162
2009

17-JUN-82

26384
27978
31824
41034
45954
54604
65464

2315
2107»
3641

26404
28054
3185
L1194
L606H
54878
6548#

2338
2413
3655

3587
6268
2564
6134
4947
6023
2693
4148
5517
2939
23;2

6328
2581
4234

6338
2607
4313

2709
4327
5606
2952
2?23

1975
21194
21384
13554
13444
11864
11444
2334n
11704
1187
11844
1185
11404
11224
1177
11764
1162#
1147
11924
11464
11424
23114
11724
1163
1157#

21084
4179

22854
15064

12064

14974

PAGE 136

CROSS REFERENCE TABLE == USER SYMBOLS

3574
6224
2118»
3950
4834
5829
2129%
3963
5427
21374
g;;g

22704

12:02

SEQ 0135

2536

36144
4299%
49054
60074

2731k
29694
36274
4L4SOR
49294
6302

27664
29714
38924
4452
51254
63044

25504
27684
3028#
38944
4464w
5127
63164

2849
4064

3045
4077

3059
6124

3361
6165

3375
6195

3197
4619
5552

3262
4662
5594

3390
[
5745

3670
4792
5793

26514
28234
3245
41988
4696
56954

2672k
8254
3334
42004
L7034
56974

2674
2839
33354
G218
47054
57294

2685
§g750
478
42B3N
4728F
5973

2720@
28774
36128
4L28BSH
49034
S9754

2631
3854

2459
3867

2477
3921

2515
3935

4360

6476
2658
4390

6520
2864
4422

4477

2739
449
566
3105
2;;?

6352
2755
4547
5758
134
4863

3075
4534
5504

2781
4757
6036
3226
4877

2810
4846
6137
3314
4979

2923
496°
6238
3419
5049

3088
5094
6365
3505
5207

3210
5189

3275
5278

3403
5332

5374

3699
5295

3785
5403

3979
5535

4343
5623

3462

3476

3547

3742

3756

3827

4022

4037

6396

4265

4810

5014

5242

5570

5811

6089

6181

6254

4996
6071

5032
6107

6440

2722

5176

5224

PARAMETER CODING

MACY11

LSENVI
LSERRT
LSETP
LSEXP1
LSEXP4
LSEXPS
LSHARD
LSHIME
LSHPCP
LSHPTP
LSHW
LSICP
LSINIT
LSLADP
LSLAST
LSLOAD
LSLUN
LSMREV
L
LSPRIO
LSPROT
LSPRT
LSREPP
LSREV
LSRPT
LSSOFT
LSSPC
LSSPCP
LSSPTP
LSSTA
LSSW
LSTEST
LSTIML
LSUNIT
L10000
L10001
L10002
L10003
L10004
L10005
10006
L10007
L10010
L10011
L10012
L10013
L10015
L10016
L10017
L10020
L10021
L10022
L10023
L10024
L10025
L10026

1150#
14464
11804
1152#
11664
1168#
1129
11944
1128#
11324
1133
11824
1183
11364
1137
11784
11744
11544
11114
1148#
1189
1188#
11644
11204
2158#
6616
11604
11304
11344
11384
1267
11904
11264
11244
1246
1267
16864
17094
17294
17424
17554
17684
17804
17924
1804#
2163
2251
22744
2294
2316
2339
2383#
24934
24430
248
25344

CVCDAB.P11

17-JUN-82 11:26

002044 G
002224 G
002102 G
005046 G
002064 G
002066 G
021426 G
002120 G
002013 G
002022 G
002216 G
002104 G
005570 G
0020;6 G
021530 G
002100 G
002074 G
002050 G
002000 G
002042 G
005562 G
002112 6
002062 G
002010 G
005554 G
021504 G
002056 G
002020 G
002024 G
002030
G
002224 G
002114 G
002014 G
002012 G
002222
002224
003710
003776
004050
004076
004124
004152
004174
(Ou4216
004240
005560
005744
005746
005776
004
006012
20
006224
006122
006222
340

30A(1052)

17-JUN-82

65664

1246

12474

2196#

21804

66174

12684

12554
12734

21694
22574
2300#
23224
23454

6.1n

PAGE 137

CROSS REFERENCE TABLE == USER SYMBOLS

6565

66334

12:02

6646

SEQ 0136

PARAMETEKR CODING

MACY11

L10027 0065%2
L10030 0064
L10031 006520
L100
0066
L1003
L10034 006752
L10035 007022
L10036 007
L10037 007164
L10040 007
L10041
007740
L10042 010330
L10043 010114
L10044 010326
L10045 011206
L10046 012064
L10047 012572
L10050 013010
L10051
013204
L10052
013550
L10053
014060
L10054 014314
L10055 014704
L10056 015352
L10057 016234
L10060 016706
L10061
017650
L1006
20622
L10063
021422
L10064 021222
L10065 021420
L10066 021450
L10067 021504
L10070 021534
L10072 021540
= 000004 G

2638#
25924
26354
26724
27204
27664
27954
28234
28754
29694
31664
33334
32424
3330#
36124
3892#
41014
41984
42834
46504
4581
4697
49034
5125#
54584
56954
59734
6302#
65464
64634
6543#
6565
6616
66404
6639
13804

MSAD13= 020000 G
MSAD14= 040000 G
MSAD15= 100000 G
MSAD16= 000001 G
MSAD17= 000002 G
MSAD2 = 000004 G
MSAD3 = 000010 G
MSAD4 = 000020 G
MSADS = 000040 G
MSAD6 = 000100 G
MSAD7 = 000200 G
MSAD8 = 000400 G
MSAD9 = 001000 6
MSBRKH= 000200 G

16144
14134
14124
14064
14054
14254
14244
14234
14224
1651'
14204
14194
14184
13914

CVCDAB.P11

MPINH = 000001
MSADO = 000001
MSAD1 = 000002
MSAD10= 002000
MSAD11= 004000
MSAD12= 010000

17-JUN-82 11:26

G
G
G
G
G
G

14334
14274
14264
14174
14164
14154

30A(1052)

17-JUN-82

12:02

H 1

PAGE 138

CROSS REFERENCE TABLE == USER SYMBOLS

SEQ 0137

45934
47034

65914
66244
66444
2411
2938

2457
3104

2847
3312

3043
34617

3359
3504

3573
3697

3639
3784

4195

4521

4577

5061

5122

5968

6298

2563
2563

260
262

2965

3162

3238

3326

2963

3160

3236

3324

3488

3529

3600

3768

3809

3880

4049

3853
3977

4089

3919
6379

4063

6475

PARAMETER CODING

30A(1052)

MSELO = 000004

1598#
g;;g

25?3
232¥

2606
2898

296
465

3163
4742

3239
479N

3327
4945

4132
4995

4220
5174

4311
5223

4359
5502

4389
5551

441
5743

MSEL1 = 000010 G

2563
4652

2907
4995

307
522

3194
5551

3259
5792

3388
6070

3668
6350

3948

6220

4359

441

4570
4412
4184
4270
2944
3125

2623
4791

(2230
4348
4381
957
154

4515
4641
3110
3436

4780
4685
3139
3452

4984
4815
3231
3467

5212
5019
3319
3481

5540
5247
3424
3494

5781
5575
3510
3522

6059
3816
3704
3535

6094
3790
3552

3984
3564

3579

15614

3299
5115
4868

4882

5054

5300

6186

6216

6259

6289

5684

5860

5878

1774
1786
1798
6597#
659
4563
4678

6157

5628

16224
16304
1638¢
6577
6582
4508
4634

5961

45834
4698#

3133
1095

3312
12764

3417
1278

3504
21478

3697
2149

3784
2350

3977
23514

6379
2353

6549

65504

6552

1196
1124

6631

1929
1766
3104
1992

2027
18074
3312
2412

2070

2245

6414

6494

2630

2458

2476

25N

2514

2848

3044

3360

3640

3120
4050

149
4090

3489

3797

991

g‘SZ

6532
3601

3727

3769

3810

3839

3881

5443

5679

5890

5923

CvCDAB.P1

17=JUN-82 11:26

MSGMDA
MSGMDC
MSGMDO
MSGMD1
MSGMP
MSGMPL

002667 G
002617 G
002513 G
002555 G
002356 G
002463 G

13974
4608
15554
15488
15364
15420
15184
15314

MSGMPS
MSGMSC

002417 G
002775 G

15240
15674

MSGMSR

002732 G

MSGTMO
MSGTM2
MSGTM4
MSG1
MS
MSRODT
MSRIDT

003417 G
003473 G
003547 G
021450
021464
014040
014304

MUTBH = 000010 G
ONEF IL= 000001
0$APTS= 000000
0$AU = 000000
0$BGNR= 000000
0$BGNS= 000000
0os$OU = 000000
OSERRT= 000000
OSGNSW= 000000
OS$POIN= 000001
0$SETU= 000001
PNT
= 001000 G
PRI
= 002000 G
PRIOO = 000000 G
PRIO1 = 000040 G
PRIO2 = 000100 G
PRIO3 = 000140 G
PRI04 = 000200 G
PRIOS = 000240 G
PRIO6 = 000300 G
PRIO7 = 000340 G
PRNTAL 004242 G
RDEH = 000004 G
ROVH = 000020 G

READRO

0053%5 9

3592
3886

5895

14364
1
1094#
1094#
1094#
1094#
10944
1094#
10944
10944
10944
13504
13514
13394
1338#
13374
13364
13354
1334#
13334
1149
1740
14354
1378¢

3740
21094

3606
3996

5913

2938
1092#
1138
1170
1164
1130
1172
1180
1134
11084
1108¢

1332¢
175
2938
1939

39;0
3431

17=JUN-82

12:02

MACY11

PAGE 139

CROSS REFERENCE TABLE == USER SYMBOLS

3716
4012

5928

4020
gSt?

3732
4027

5946

394
11

3747
4042

3417

3761
4055

5353

3504

3774
4069
5394

3784

SEQ 0138

3802
4082
5408

3815
4095

5448

READR2

005430

READR4

READR6

005470 G
005522 6

%;ggl

Z%??

zggz

4439

4565

4680

5110

5348

5389

REGO

002234 G

14564

1941+«

1942

2108+

2109

2232

2286+

6420

6500

21204
4007
21304

530

559

3832
6401

3844

3859

3872

PARAMETER CODING

CVCDAB.P11

REGOEQ
RE
REG2EQ
REG4
REG4EQ

MACY11 30A(1052)

17-JUN-82 11:26

003206 G
00%236 G

15974
14574

003220 G
002240 G
003232 6

1599+
1458%
16014

REGGEQ 003244 6
RSTH = 000001 G

16034
1383

ROBAD
ROEROR

002262 G
003624 G

1469
166;0

ROGOOD

002254 6

ROLOAD

002252 G

ROMASK

002256 G

REG6

ROREAD

ROTM
R2BAD

R2EROR

002242

002260 G

004154 G
002274 G

003712 6

1459%

3639

1808
2036+

12:02

CROSS REFERENCE TABLE == USER SYMBOLS

2120

2288+

2078

2129«

2130

2289+

1856
1991

2139

5840

%008

2tn

457

%512

1670
1951

1814
1981

1943+
1999

1944+
015

1945
5619

2110«
2437

2111+
2465

2112
2483

1974+

2107+«

2112

1941

1973«

2138+

3654

3381
6458
1671
4020+
1674
2457+«
3374+
3866+

14674

1672

3647
6482
1815
4035+
1818
2475+
3461%
3918+
1816

3866

3661
6526
1940«
6394+
1938«
2508+
3475+
3919+
1939«

6475

3573

3586

2521

2855

6274

3051

6334

3065

6344

3460

3474

3546

3740«

3754+

1991«

2008+

2107

2108

2411+

6327

526+
573+
4021+

527
586
4036

2529
3638+
4063+

2531+
3639+
4076

2847+
3654+
6123+

3043+
3741«
6164

3058+
3755«
6194+

3358+
3825+
6223+

1944

1992«

2612«

2430+

2458+

2476

2511+

2514e

1990«

6201

6230

2109«

2110

6
4798

046

1831
2570

2038+
2587

2039+
2613

2040
2630

2121«
2664

2122«
2870

2123
2916

3081

3203

3268

3396

4B40

4953

5002

5038

5088

5182

5230

5272

5510

5558

5600

5751

1832

2035+

2040

2118«

2123

3119«

3147+

3148+

3446+

3488+

3529+

2033«

035

2036

5118

2119

2563+

2580+

2606*

2623+

2654+

16904

1673

1961
1698

1817

1942«

002264 G

R2MASK

002270 6

14714
2668+
6132«
4945+
6021+

170
2862+
4232+
4995+
6070+

1835
2907+
4311«
5031«
6106+

2908+
4359+
5081+
6350+

R2READ
R2TM
R4EROR

002272 G
004176 G
004000 G

3261+
4966

3389+
5175+

3445+
5503«

3669+
5744+

3600+

14732

14744
17844
17134

3689
5380
14778
2791+

4491+

002302 6

6171

6337

3374

927
6538
1945
6451
1940
2512
3545+
3534

6531«

6130

4076

3359

1943

1772
14754

R2LOAD

R6LOAD

941

4063

3058

3920+

1699

002300 G
004520 G
002312 G
002304 6

934

3043

3640+

14728

R4READ
R4TM
R6BAD
R6GOOD

919

2847

3360

1468

3044

853

002266 G

002276 G

SEQ@ 0139

2119«

R2GOOD

R4LOAD

J "

PAGE 140

2037

182
2077«
184

336
6446
14664
3826
14654
2629
3359+
3853«
2848r

17-JUN-82

5359«
3968+
1478¢
17964
14840
14814
5108+
5889+
14804

3726+

1700

1701
2056
2085

3969
5433
1722
2792

4546

5367«
6009+
1721
2095
186
186
5241+
5903+«
1866

3768+

3880*

4006%

072«
4389%
5174+

2034

1834

2037«

2699

2715

183

4154
5523
1849
2807«

4730+

5387
6136+
1848
140
137«
366
5908

2137

3809+

4333
5612
2076+
2820+

4890+

5401
6237+
2078«

2141+
2145
5388+
59%2'

2138

4049+

4089+

3073«
4421+
5223«

194+
4475+
5265+

3195+
4533%
5502«

2039

2122

2552+

2038

21200

2121

2761

2787

3725+
6022¢

2745

3949+
6351«

4005+

2655+

4476

2816

2929

3094

3216

685%
614
§131
274+

5614+
6292+
2079

5420+
6298+
2130«

5440
6364+
2131

516
293
5442+
5936+

5854+
4178+
5569+
5941

5855
4264+
5677«
5955+

2938+

2951«

3104+

3074+

4312«

4763
604
129
209+

5067+

2909+

3388+
4742+
5743«

4233+

4553
57
079
087+

5061+

2863+

3260~
4661%
5593«

4133+

4498
5669
2077
29;5'

4932+

3259+
4617+
5551«

4967
6244
2692«
3402+

100
6371
2708«
3682+

5455+

5489+

5638+

5872«
4L406%
5810+
gogg-

5873
443Br
5850+
179+

5122«

133+

5162+

225+

5195

2738+

3668+
4791+
5792«
3118+

4618+

3281

5284
2754+

3196+

4743+

5338
2778+

3962+

4147+

4326+

5731+

529

5308+

5654+

5691+

5907«
4564+
S855
6209+

5908
4679+
5868+
6%5 *

5940+
4809+
5870
6282+

3292+

3948+
4833«
5828+

3312+

5324+

17«

5345

5941
5013+
5873

3504+

%os1369258125798‘1”905‘1‘7
OW2Z“GM0S7N“OWMAON“fiGW=f6l7S0“2P3247“678&073“26W%962375M%“"190H2153765N8n"52830~i5~

NO0Wslfi
O V= e e e = == == O =
R

SVCINS= 000000

—
—
O~ NN~
OM-ONM 3NN— —
——————
ONN
ON
0N—F
ON N-~
N0NM

002310 G

k=3

(OSABDIUoNvM

g— —-— g —=oOMN~ ONON
-

———ONMWNON Diet

0NITWAN

R6READ

OO NTWVW

002306
G

ONMWNOO
TNMI3TNWOMODVO O

ROMASK

———
——OO0\— WM

17-JUN-82 11:26

MACY11 30A(1052)

O ~ OM
NN
M——————
OONITNO

CVCDAB.P11

O(0(=
VoOOVOMIV~WON=3OF03OOvO( OONeNGOONOeNN0NIeINWWONNOOMNOONNN0ONOe=NMNMev0OOFMONOONONOTOO NCOOINNA=I(NWNNNO2O(=MN2—NNN==OOVNOONOMIO=MO7—=OMINONMOTN=NNNMANOVNIMeO~PRE=OOeN ==eNNV=MAe0OOTF=Ne0N=ON=OO7=M=N=M9Ne77IWO7VONT=VO—”~=NN=1=NPeggegegg=egi-D
eee
=~ONPONMOMOMeTNN —NIWVMoel=doalCOb=IToaNO= M=eT=OWV7NOOe NeN= -goggT
TN OMO—

W(YVVNWNONOgO—SNMRAP]NYY,IIYOMVVOMTgWANNoTOT0NINnVUVOVIITTOONTMONINTTSONSSMeOO=(MTVV0T0NINMOO0ee3eTeGTOINNROe3ROOONMeeTTTM0OWOOOAOeNeNSSVMeOBOOeTAM~GNRWgUMTT0TONSADTMeeTeWT0NI2O0S=eCNT\O3MOO=e0TevvvGImMTM8VWe=OO©eT©0=teOoOPe0V.NTNNNlvON0ONoOe0oeOOOeeWNON0NoMeOUNelUIMNOoNooMIYelllNTPMOSoo0T©O-OOFlANllOOVCPOeTNNO=SOOS0T0PNVSlONLeVSI(OO0WNNoT0ADrOOl0DTO(ONINNNOXNM.o0IToNoO=SNTkllUlT0v—eNMooC=OOlO0ovNeoOe=XlONleUO1OWoeoNNIklmlvM1OoeoNeeNOllelMO1=IoVooM=lWllST0O1OIoAroolNNl0lOToLoL=Te~lvol0oe=Dlka—VrAUOOMNAVmIV—NaeaV0O1 =~NV=lQdEbO=LaL0MTIONKtlOkadeskgolegdladel—Ll
OO3TOMOO—OeNOOMANeIPNeD~TMWNNINVTINNONNNOO=M=VNP=O0=M7=M=INOTON=N= MP T~—-—
PARAMETER CODING

17=JUN-82
12:02 PAGE 141
CROSS REFERENCE TABLE == USER SYMBOLS

SEQ 0140

oSeRteg

| PARAMETER CODING

CVCDAB.P1

MACY11

30A(1052)

093
n
2210
2224
2 Sg
232
2416
2438
2466
249
2536
2580
2606
2630
2664
2702
2737
2760
2788
2820
28
2916
2944
2971
3065
3093
3124
3152
3200
3219
3256
3283
3319
3366
3394
3422
3440
3470
3496
3523
3552
3578

094
198
221
2225
5 58
24
2417
2640
2468
2494
2556
2584
2610
2631
2665
2703
2738
2761
2790
2824
2869
2917
2945
3034
3066
3094
3125
3153
3201
3229
3265
3284
3320
3367
3395
3423
3450
3471
3497
3524
3553
3579
3605
3647
3675
3703
3730
3751
3777
3804
3833
3859
3885
927
955
3983

17-JUN-82 11:26

3646
3674
3702
3720
3750
3776
3803
3832
3858
3884
3926
3954
3982

17-JUN-82

12:02

PAGE 142

CROSS REFERENCE TABLE == USER SYMBOLS

095
199
1;
g
9
38
2418
2441
2469
2495
2557
2585
2611
2633
2667
2707
2742
2762
2791
2825
2870
2918
2946
3035
3067
3095
3126
3154
3202
3230
3266
3297
3321
3368
3396
3424
3451
3479
3498
3525
3554
3580
3606
3648
3676
3704
3731
3759
3778
3805
3834
3860
3886
3928
3956
3984

096
00
13
;8
2275
S 39
419
2444
2474
510
562
586
2612
2634
2668
270
274
2764
2796
2842
287
2919
2947
3048
3068
3096
3127
3155
3203
3231
3267
3298
3323
3369
3397
3425
3452
3480
3508
3526
3555
3581
3607
3649
3677
3705
3732
3760
3788
3806
3835
3861
3887
3929
3957
3985

097
201
14
9
6
360
620
445
475
311
2563
2587
2613
263
267
2712
2744
2765
2797
2843
2873
2926
2948
3049
3078
3097
3128
3156
3204
3232
3268
3299
3324
3370
3398
3426
3453
3481
3509
3533
536
3582
3608
3650
367
3706
3733
3761
3789
3817
383
3862
3888
3930
3958
3986

5098
20
31
30
93
2 42
242
2448
2480
2518
2567
2588
2614
2637
2674
27113
2745
2767
2809
2852
2874
2927
2955
3050
3079
3108
3129
3158
3205
3233
3269
3300
3331
3378
3399
3427
3454
3482
3510
534
3562
3583
3610
3658
3679
3707
3734
3762
3790
3814
384
386
3890
3938
959
987

2099
2203
2216
2231
2;94
2347
2423
2449
2481
2519
2568
2590
2616
2639
2691
2714
2746
2768
2810
2853
2876
2928
2956
3051
3080
3109
3137
3159
3206
3235
3270
3301
3332
3379
3406
3428
3455
3483
351
3535
3563
3590
3611
3659
3686
3708
3735
3763
3TM
3815
3843
3870
2891
939
3966
3988

SEQ 0141

101

204

217
2232
2§9S
84
4%8
24 g
248
2520
2569
2591
2617
2640
2692
2715
2748
2780
2813
2854
2877
2929
2957
3052
3081
3110
3138
3167
3213
3236
32N
3303
3334

3380
3407
3434
3456
3484
3512
3536
3564
3591
3613
3660
3687
3714
3736
3764
3792
3816
3844
38N
3893
3940
3967
3994

2102

%205

18
45
01
385
2629
2457
2483
2521
2570
2593
2622
2657
2696
2716
2749
2781
2814
2855
2902
2930
2958
305
3082
3
3139
3168
3214
3243
3278
3304
3335
338

408
3435
3465
3485
3513
3537
3565
3592
3614
3661
3688
3715
3745
3765
3793
3817
3845
3872
3894
3941
3968
3995

2162
2206
2219
2246
2302
2404
2634
2462
2484
2522
2571
25%
2623
2658
2697
2718
2753
2784
2815
2856
2903
2931
2959
3054
3083
3112
3140
3186
3215
3244
3279
306
3350
3382
3409
3436
3466
3492
3514
3538
3566
3593
3630
3662
3689
3716
3746
3772
794
818
3846
3873
3909
3942
3969

2163
2207
2221
2247
2315
2405
2435
2463
2486
25264
2573
2597
2627
2661
2698
2719
2754
2785
2816
2857
2913
2932
2961
3062
3084
3113
3141
3187
3216
32646
3280
3307
3351
3383
3410
3437
3467
3493
3520
3539
3567
359
3631
3663
3690
37117
3747
3773
3800
3819
847
3874
3910
943
3970
997

164

208

222
2250
2316
2410
2436
2464
2487
2525
2574
2598
2628
2662
2699
2721
2758
2786
2817
2858
2914
2942
2962
306
3091
3114
3142
3190
3217
3247
3281
3317
3364

3384
34M
3438
3468
3494
3521
3550
3568
3595
3644
3664
369
3Nn8
3748
3774
3801
3830
384
3875
3924
3944
3971
3998

2170
2209
2223
2251
2317
a24mn
2437
2465
2490
2535
2579
2605
2629
2663
700
2722
2759
2787
2819
2867
2915
2943
2970
3064
309
3123
3143
3191
3218
3255
3282
3318
3365
3393
3412
3439
3469
3495
3522
3551
3577
3596
3645
3673
3692
3719
3749
3775

38%
3857
3876
3925
3953
3972
3939

PARAMETER CODING

CVCDAB.P11

MACY11

17-JUN-82 11:26

4030
4057
4083
4125
4155
4225
6%74
4330
4352
4384

30A(1052)

4010

4031
4058
4084
4126
4156
4237
4275
4331
4363
4385

17-JUN-82

12:02

PAGE 143

CROSS REFERENCE TABLE == USER SYMBOLS

40N

4040
4059
4085
4137
4157
4238
4284
4332
4364
4393

4012

4041
4067
4086
4138
4182
4239
4285
4333
4365
4394

4013

4042
4068
4093
4139
4183
4240
4303
4334
4366
4395

4014

4043
4069
4094
4140
4184
4241
4304
4335
4367
4396

4015

4044
4070
4095
6141
4185
4242
4316
4336
4368
4397

SEQ 0142

4016
4045
4071
4096
4142
4182
4%4
4317
4346
4369
4398

4025

4046
4072
4097
4143
4189
4268
6318
4347
4379
4399

4026

4053
4073
4099
4151
4190
4269
4319
4348
4380
4410

4027

4054
4080
4100
4152
4199
4270
4320
4349
4381
4411

4028

4055
4081
410
415
4200
4271
4321
4350
4382
4412

4029

4056
4082
4103
4154
4224
4272
4322
4351
4383
4413

4414
4445
4485
4517
4551
4580

4415
4446
4486
4519
4552
4581

4416
4448
4495
4520
4553
4582

4425
4449
4498
4528
4554
4594

4426
4451
4497
4529
4555
4595

4427
4452
4498
4537
4556
4612

4428
4470
4499
4538
4568
4613

4429
447
4500
4539
4569
4622

4430
4480
4501
4540
4570
4623

4631
4481
4513
4541
4571
4624

Lb42
4482
4514
4542
4572
4625

4443
4483
4515
4543
4574
4626

basd
4484
4516
4550
4575
4627

5019
5053
5090
5117
5185
5215
5249
5282
5327
5355
5393
5423
5450
5513

5020
5054
5091
5119
5192
5216
5251
S§83
5 58
5357
5394
5424
5453
5520

5021
5055
5097
5120
5193
5227
5252
5284
5335
5358
5395
5430
5454
5521

5022
5056
5098
5126
5194
5228
5256
5285
5336
5370
5396
5431
5459
5522

5023
5058
5099
5127
5195
5229
5257
5286
5337
5371
5397
5432
5460
5523

5035
5059
5100
5166
5196
5230
5269
5587
5338
5377
5398
5433
5494
5524

5036
5074
5101
5167
5197
5231
5270
S§98
5339
5378
5406
5434
5495
5525

5037
5075
5102
5179
5198
5232
5271
5299
5340
5379
5407
5435
5507
5526

5038
5085
5103
5180
5210
5233
5272
5300
5341
5380
5408
5436
5508
5538

5039
5086
5113
5181
21
5245
5273
5301
5351
5381
5409
5446
5509
5539

5040
5087
5114
5182
5212
5246
5274
5302
5352
5382
5410
5447
5510
5540

5041
5088
5115
5183
5213
5247
5275
5304
5353
5383
5412
5448
5511
5541

5052
5089
5116
5184
5214
5248
5281
530
5354
5392
5413
5449
5512
5542

5543
5577
5610
5658
5686
5754
5784
5818
5859
5893
5917
5949
6026
6045
6079

5544
5579
5611
5659
5688
5761
5785
5819
5860
5894
5926
5950
6027
6057
6080

5555
5580
5612
5666
5689
5762
5796
5820
5861
5895
5927
5959
6028
6058
6092

5556
5584
5613
5667
569
576
5797
5832
5862
5896
5928
5960
6029
6059
6093

5557
5585
5614
5668
3697
5764
5798
5833
5863
5897
5929
5961
6030
6060
6094

5558
5597
5615
3669
5735
5765
5799
5834
5864
5898
5930
5962
6031
6061
6095

5559
5598
5626
5670
5736
5766
5800
5835
5876
5899
5931
5963
6035
606
6096

5560
5599
5627
5671
5748
5767
5801
5836
5877
5911
5932
5965
6039
6063
6097

5561
5600
5628
5672
5749
5779
5802
5838
5878
5912
5944
5966
6040
6074
6098

5573
5601
5629
5682
5750
5780
5814
5839
5879
5913
5945
5974
6041
6075
6110

5574
5602
5630
5683
5751
5781
5815
5844
5880
5914
5946
5975
6042
6076
6111

5575
5603
5632
5
5752
5782
5816
5845
5881
5915
5947
6013
6043
6077
6112

5576
5633
5753
5783
5817
5858
5
5916
5948
6014
6044
6078
6113

PARAMETER CODING

CVCDAB.P11

MACY1

17=JUN-82 11:26

6114
6141
6168
6190
6219
6245
6%74
6321
6343
6369
6399
6416
6445
6465
6491
6517

CROSS REFERENCE TABLE == USER SYMBOLS

61
614
6169
6198
6220
6246
6275
6322
6344
6370
6400
6417
6446
6468
6492
6518

6117
6143
6170
6199
6227
6247
6276
26
6345
6371
6401
6418
6447
6469
6493
6519

6630

6321
1255

6631
2404
6467
1256

SEQ 0143

6119
6144
6171
6200
6228
6257
6277
6327
6346
6372
6402
6419
6448
6474
6494
6523

6120
6145
6172
6201
6229
6258
6287
6331
6347
6373
6403
6420
6449
6475
6495
6524

6127
€14
617
6202
6230
6259
658
633
6355
6374
6405
6424
6455
6479
6496
6525

6128
6155
6174
6203
6231
6260
6289
6333
6356
6384
6406
6425
6456
6480
6497
6526

6129
6156
6184
650‘
6232
6261
6290
6334
6357
6385
6410
6426
6457
6481
6498
6527

6130
6157
6185
6214
6233
6262
6%91
6335
6358
6386
6411
6437
6458
6482
6499
6528

6131
6158
6186
6515
6241
6263
6§9S
6336
6359
6387
6412
6438
6459
6483
6500
6529

6132
6159
6187
631
624
6271
6296
6337
6360
6388
6413
6439
6461
6485
6504
6535

6133
6160
6188
6217
6243
6272
6303
6341
6361
6389
6414
6443
6462
6486
6505
6536

6140
6161
6189
18
6244
6273
6304
6342
6368
6390
6415
6444
6464
6490
6506
6537

6632

6633
2448

6638
2555

6639
2556

6640
2596

2597

3185

3186

3245

3246

1274

1686

1687

1709

1710

1729

1730

1742

1743

SVCTAG= 000000

6624
10944
6320
1094#

SVCTST= 000000

10944

2376

2377

2399

2400

2506

2507

2550

2551

2651

2652

2685

2686

S$1 SyM= 010000

10944

12564

12744

16874

17104

17304

17434

17564

17694

17814

17934

18054

1927#

63034

63264

64104

64LO4LH

6474H

64904

65928

66254

16704
1752
1825¢

1679
17614
1829

1692
1765
1831#

1696
17744
1840

1698#
1778
18424

svcsus= 000000

T$ARGC= 000006

1112
1707
17864

2403

11134
17154
1790

11144
1719
17984

2447

6468
1273

11154
17214
1802

11164
1727
1808#

11174
17354
1812

64
9
144

1668
1748¢
1823

PARAMETER CODING

CVCDAB.P11

T$SCODE= 001032
TSERRN= 000001

MACY11

17-JUN-B2 11:26

1846

30A(1052)

17-JUN-82

18484

1854

25194
58680
201#
34514
36594
8434

25684
9144
2144
4664
3674w
38584

65814
19494

041N

L0544

L0GBH

LO66N

LOBLH

G364
49654
52468

G3BON
49834
52704

19594

L394K
50004
52824

18564

1862

1871

19974

20134

044n

20544

20834

20934

24174

4LOBIN

4094N

4138

41524

4183

423

42698

L3178

L74BR

4L°6IN

4L779F

L7968

4B14M

4LB3BN

4BSON

4B67#

2338¢

2340

1979%

25854
59570
2304
364804
36874
3871

LLTIN
50184
52994

65764
2162¢

6580
2164

65814
22504

6586
22934

ISHILI= 000017
TSLAST= 000001

65764
10947

6579
66314

65814
6637

6585

TSLSYM= 010000

1094#

1256

1274

TSLOLI= 000000

TSLTNO= 000034
TSNEST= 177777

T$NSO = 000000
TSNS1 = (00005

6631
10944

65764

2258
2673

66464

6578

2275
2721

65814

6584

2301
2767

2323
2796

1687

26114
59430
26
34934
3734
38854

L4L26M
50364
53364

23154

1710

2346
2824

26284
29564
32794
35094
3715k
39254

L44L3N
50534
53524

2317

1730

2384
2876

6624
0494
2984
35214
37314
39394

L4BTR
50864
S378

1743

2444
2970

4102

4199

4284

4451

4594

«704

4904

66344
109644

11014

12464

12554

12674

12734

12764

21514
2334
2L48BN
25624
26574
27638
28754
32420
36304
Q2730
LO12M
50574
36234
58374
04w
65654
11014

21584
23454
20568
2572m
666#
27668
8974
2464
894
42838
LOLLA
50744
5452
5844H
64104
65904
1272

21694
23494
24678
2579
26724
27778
9024
2554
38924
L3004
L6S6M
51184
54584
5964
6460#
164
12814

1755
1989¢

1759
2001

6544

17294
19274

12464

2257
2507#

6547

17334
19664

125

22708
2534

6592
17420
19724

1267
1768
20074

2274
25514

SEQ 0144

1860

TSEXCP= 000000
TSFLAG= 000040

YSFREE= 021540
TSGMAN= 000000

B 12

PAGE 145

CROSS REFERENCE TABLE == USER SYMBOLS

65764
10944

24B1M
28534
3153#
34354
366454
38314

12:02

6625
176468
19834

21804
23554
2474M
25894
26864
2780
9604
3024
39074
L3034
L6BBN
51254
548BN
59734
64330
214g
127
1772#
2017

22854
2638

17554
19894

21874
2377
2485
25924
26914
27894
9694
3064
9094
L4478
47038
51614
5494w
60084
64
66354
2151

1662
1780
SOSS'

3 g
26524

17598
20014

1768¢
20074

%6970
0634
33184
3534w
37464
3954w

4496

5098#
53934

1756

2490
3167

5126

12814

1772¢
20174

§7130
0794
33654
35514
37604
39674

4S14M

S1144
54074

45808

1769

2494
3243

5459
16624

1780
20254

7430
0924
33794
5634
77
3983

453BN
S1804
S4314

24354

759
1094
3944
35784
37894
39954

7854
1244
34074
35914
38014
40114

4SS1H

4569%

51934
S447#

43318

2170

52284
55214

46964

1781

2535
3331

5696
16864

17844
20614

1793

2593
3334

6303

6464

17094

17134

17928
20684

17964
21004

2285#
24218
25234
26324
2732
28234
31834
33504
4L1BBN
4S2BF
4BBSH
S3274
S6874
6302¢
654

56954
6317#
65464

23114
24394
25514
26388
27478
%8420
1904
3612¢
42198
4S93@
49304
S3704
57304
63214
65494

2349
1686
17840
2061

23554
16904
1792
0630

6549
1709
17964
2100

65544
1713
1804
2158#

35
1729
19278
5169

17338
1966
51800

1742
1972¢
2187

377»
2766

2639
3893

5974

2274
24108
25104
26228
2720
§S1BI
1664
33484
L1254
4S1BE
4B24N
53034
S658¢
62944
65404

5345
7328

46238

1805

S2114
5508

2270
2404
25074
26154
27178
28094
31574
33334
L1204
4470
4LBIBN
52564
S631
61194
640X

2334#
2720

43474

49514

22578
G008
4938
6054
27078
8064
0344
33304
41014
L46SH
4L734M
52504
5584w
61154
64B4H

32
6864

28144
31384
34234
36054
38144
40264

4BBIEF

21964
2383w
248N
25974
27014
7954
0294
33224
4L098F
LASOR
4729
51664
5578
60134
6474M

53113
672

24634

24284
2534w
26354
27378
284
31864
36094
419BF
4S738
490
53564

383
2777k

24008
2795

1504#
21464

23224
24434
Q%<
2652#
27534
2872#
32344
362
4224#
4607#
49374
S411#

5735#
63264
65544
17464

1983
21964

2493
2806#

PARAMETER CODING

CVCDAB.P11

T$NS2 = 000002

TSNS3 = 000003
TSPCNT=
T$PTAB=
T$PTHV=
T$PTNU=
T$SAVL=
T$SEGL=

000000
010071
000001
000001
177777
177777

T$SEKO= 010001

30A(1052)

2823
39074

28404
4101
49304
6590

2875
41204
5125
66164

28974
4198
51310
6623

2969
42194
5458

3029»
4283
54884

3166
43004
5695

3183¢
4450
57304

3333
L4658
5973

3348
4593
6008

3612
46074
6302

3628¢
4703
63174

27074
2960
4125
4688
53274
5837
2421
26228
6484

%717
0344
4188
47340
5356
S844N
24288
2632
64904

7374
157
4224m
4818
53704
5964
2439
31904
6540

5510‘

747
3186#
4273
4824m
541
60134
24564
3234

2523

255

2592

25978

2635

26578

2666

17=JUN-82 11:26

4903
65654
404K
2701
2902¢
4098
46564
5303
57354
26104
2615
6474k

66374
66384
1125
10947
10944
10944

20254
24678
2591
27074
28
3236
39094

45180
4820
52564
55784
5966
647N
1927

2443

6638#
6641
66464
66414

19274

20614
2469
6054
778
2820
32554
4098¢

4520
4B24N
53034
5580
60134
64LBLN
1

17-JUN-82

12:02

2448N

2489

19664

2063
2474
26154
2719
2842N
33024
4100

4528@
4BBSH
5305
55844
61154
6486
1972#

1968

20684
24854
2617
27378
28724
3304
41254

4573@
4BB7?
53274
56314
6117
64904
1983

2439
26228
789
3064
G647
49374

245
263
809+
3322
44704
5057

60134

6115

61194

T$SIZE= 000004
T$SUBN= 000002

6632
10940

TSTAGL= 177777
TSTAGN= 010073

LL64n
10944
10944

28054

66464
23764

28394
12660

7534
245
L3030
4885
54234
6115
2467
32554

76
2464
4447
4937%
5452
61194
4748
302

SEQ 0145

57800
330
44704
5057
54944
6294
2485
33064

3892
47294
6546
2691#

789
3504
4518
5074#
5578
63214
25628
3322

8094
3609
45288
5118
55844
6463
2572
63264

2818
6304
4573
5166#
5631
64688
25798
6404

8420
3889
46128
5250
5658¢
6543
2589
64104

;872
9094
4644
52564
5687

20014

2003

20074

2017#

2019

47344
52504
5454
5844k
64608

32344
3891
4470
4B18#
5252
54944
59644
6462

2100

24104

26054
6460

6646

26284
2615
§7800
30
430
4885
564234

PAGE 146

CROSS REFERENCE TABLE == USER SYMBOLS

2421
26054
2763
3255#
6273
48244
561

TSTEMP= 000000

¢ 12

MACY11

19724

21004
2487
26224
27478
2874
33064
4188¢

4575
49374
535
563
61198
65404
1989#

1983#

2102
25104
2632%
2749
29024
3322¢
4190

L6128
5057%
5358
56584
62944
6542
2001

1985

24104
25234
2634
27534
29604
3324
4224M

19894

24214
2525
56570
7634
2962
33504
42738

4646
50744
54114
5689
63264

46564
51184
5413
57354
6404

L6BBF
5120
54234
58374
6406

20074

2017

20254

2061

2474k
2666
58623
3609
4528
5118

2485
26914
2872
36304
4573
5166#

25104
2701
29024
3889
L6128

6294

63264

6404

64104

3994

24034

24474

5064

25504

47288

4929%

51604

54878

5729

28964

12674

54944

30284

16620

5578

1824

16904

5584r

1854

17134

24288
2572¢
2668
7804
157#
3611
L3038

L644N
5055
53704
56874
6296

)
26578
2818
33504
4518
5074

5452

2423
25628
26664
2765
30344
36094
4275

5631

32454

17338

2523
7078
2960
9094
4644
52564

25628
2717
3034#
4098
46564
5303

6460

6474

5554

5964

26514

63168

63208

17598

17728

5658»

3478

60074
17468

5687

36274

57354

064

24394
2574
6914
7894
159
36304
L447H

4690
51664
54528
5839
64108
8¢

2441
25794
27014
2791
31908
38894
4449

2572
7378
157
41254
4688
5327

25798
2747
3190#
4188
47344
5356

6540

26854

27314

5837

41198
64674

1784R

58444

24564
25894
2703

2589
2753
3234
4224#
4B18
53704

27764

L218¢

42994

22704
2686
L1208
6L6BF

22854
2732m
L2198
65654

23114
2777h
L3004
66164

2334w
2B06H
L465H
66374

23778
28404
4607
66388

24004
28974
4729
66394

§4040
30294
49308

448N
1834
51614

25078
31864
5488¢

17964

25514
32464
57304

2158#

63174

21964
26524
9078
63214

12204
12334
17924

15510
12340
1804

1 %2‘
12354
19664

12234
15550
19834

12244
12730
20014

12;50
12764
20174

12264
16864
20614

1227#
1709
21004

12154

122
17294
21464

12164

12174

1218¢

1219#

21804
SO7TH
12074

12084

1%090

12104

12114

12126

12134

12144

15290
17428
2162#

12304
17554
2163

12314
1768¢
21694

25564
33484

1232#
1780#
2187#

PARAMETER CODING

CvCDAB.P

30A(1052)

22504

2251

22578

2274k

22934

2294

23004

2315#

7954

8184

28234

gl? N

28754

9604

29694

53034
6294n
66234

S3564
63024
66354

3245

3478

17-JUN-82 11:26

7894

3224
LO47H

48854
TSTEST= 000034
TSTSTM= 177777

330#
L4504

S6874
65434

3#
56954
65464

28054

28394

10944

LL6Lm
1094#
1756

1845
1984

23764

LO06K
1667
1764

1853
1989

17-JUN-82

12:02

D12

MACY11

PAGE 147

CROSS REFERENCE TABLE == USER SYMBOLS

3334
4518

36094
45734

3612¢
45804

SB3I7H
65494

5964M
65764

59734
65814

5250
61154
65904

28964

30284

3182¢

3185

5057¢

23994

4728F
1678
1769

1859
1996

51184

51254

2403

2447

49294
1687

51604
1695

1777

1870
2002

1781

1927
2007

2062
2216
2410
2486
2590
2667
2758
2857
2970
3128
3235
3331

2068
2222
2416
2490
2593
2673
2764
2867
303«
3137
3243
3334

2074
2228
2422
2494
2597
2691
2767
2873
3048
3142
3246
3350

2082
2246
2428
2510
2605
696
2780
2876
3053
3152
3255
3364

2087
2250
2434
2518
2610
2702
2784
2902
3062
3158
3265
3369

4849
4987

4854
4999
5113
5551
5370
5494
5605

4866
5004

4871
5017

4880
5022

510
524
5357
5459
5597
5748
5858
965
6110
6198
6295
689
6468

575

5863
5974
6112
620

6303
63
6474

5119
5556
5377
5507
5609
5761
5872
601
6119
6516
6321
6405
6479

5126
5269
5382
5512
5614
5766
5881
6056
6127
6;19
6326
6410
6485

5166
5274
5 98
55
5626
5779
5893
6031
613;
bii
6331
6412
6490

3%89#
4S8

8924
45938

25064

25504

54874
1706

57294
1710

1793

1789

1933
2012

1948
2018

SEQ 0146

40984
L644N

231
1578

41014
4L6BBE

224
31664

4L1BB¥
4L696H

S4114
6404H

54524
64608

26514

60074
1718

63164
1726

6320
1730

1801

1805

1811

555

1953
2025

36274

1958
2031

39064

1964
2043

2092
2258
2440
2524
2616
2707
2790
2913
3067
3167
3270
3378

2098
2275
2444
2535
2622
2712
2796
2918
3078
3186
3278
3383

2101
2293
2448
2556
2627
2718
2809
2926
3083
3190
3283
3393

2170
2301
2456
256%
263
2721
2813
2931
3091
3200
3297
3398

2199
2323
2462
2567
2636
2737
2819
2942
3096
3205
3303
3406

4886
5035

4904
5040

4937
505

4950
5058

4955
5074

5179
5281
5397
5525
3632
5784
5898
6039
6140
6%;2
6336
6418
6492

5184
5286
5406
5538
5658
5796
9N
6044
6145
6;41
6341
6425
6498

519
5298
541
554
5666
5801
5919
605
6155
6246
6346
6438
6505

5197
5304
5423
5555
5671
5814
5926
6062
6160
6;57
6355
6443
6518

5210
5327
5430
5560
5682
5819
5931
6074
6168
6262
6360
644
652

23384
2534m
32344

4L198F
4697

2339
25724
32424

23454
gsgz:
33024

54584
64634

42738
47034

5578#¢
64BLx

4L283#
4B18#

26854

27314

27764

7
1738

6634
1743

1751

L119F
1822

1967
2048

2204
2346
2468
2573
2639
2742
2824
2947
3108
3213
3306
3411

5085
5215
5335
5435
5573
5688

5832

5944
6079
6173
6271

6368

6528

L2188
1828

1972
2053

2209
2384
2474
2579
2657
2748

56314
65404

42994
1839

1978
2059

2955
3113
3218
3317

2213
2404
2480
2584
2661
2753
2852
2961
3123
3229
3323

4969
5090

4982
5097

S%g?
5340
5446
5579
5696
5838
5949
6092
61
6276
6373
6461
6535

5232
5351
5453
5584
5735
5844
5959
6097
6189
6287
6384
6464
6541

E 12

. PARAMETER CODING
MACY11 30A(1052)
17=JUN-82
12:02 PAGE 148
CVCDAB.P11
17-JUN-82 11:26
CROSS REFERENCE TABLE == USER SYMBOLS
T$TSTS= 000001

T$SAU = 010021
T$SAUT= 010016

TSSCLE= 010017

T$SDAT= 010072

6544

6547

3183#
57304

348#
60084

28#
63174

2293

2300

2315
6591
1255
2250
1686
17844
6646

2322

6640

66414

10944

2334#
22704

22854

66398

3774

2338
2274

6644

400#

S074

25514

SEQ 0147

9074

41204

L2194

2652

2686w

27324

27774

4607H

4729

49304

28404

28974

302

1709
17964

1713
1804

1729

17338

1742

17464

1755

1759

1768

1772#

43004

44654

28064

51614

54884

2345

T$SDU =
TSSHAR=
T$SHW =
TSSINI=
TSSMSG=

010020
010066
010000
010015
010012

T$SPC =
T$SPRO=
T$SPTA=
T$SRPT=
T$$SEG=

000001
010014
010071
010013
010001

2311y
65654
12464
21964
1662#
1780
66374
2180#
66374
21
}9

T$$SOF= 010067
T$$SUB= 010065

66164
264044

6624
2443

24484

2489

25564

2592

25974

2635

31864

3242

32464

3330

63214

T$$SW = 010001
TSSTES= 010063

1267#
2377x
7

1273
2383
27778

26004
2795

2493
28064

25074
2823

2534
28404

25514
2875

2638
2897#

26528

2672
3029«

26864
3166

2720
3183+

27324
3333

T
110
T

112
T13
T13.1
T13.2
T14
T15
T16
117
T18
119

12
2.1
12.2
120
121
122
123

006014 G
007070 G
007166 G

007366 G
007742 G
007746
010116
010332 G
011210 6
012066 G
012574 6
013012 G
013206 G

006022 6
006026
006124
013552 G
014062 G
014316 6
014706 6

6463

3348¢
4580
57304
1207
1216
1217

1218
1219
31854
32454
1220
1221
122§
122
1224
1225

1208
24034
24478
1226
1227
1528
1229

64688

3612
4593
5973

23764
28354
28964

3028#
3182+
33474
36274

41194

42184
42994
23994

L4640

46
67%80

49294

2257
16904

1792

6543

284
46074
6008#

3892
4696
6302

39074
4703
63178

4101
4729
6546

4120
4903

4198
49304

4219%
5125

4283
51614

43004
5458

4450
5488¢

44654
5695

MACY 11

PARAMETER CODING

CVCDAB.P1

124
125

17-JUN-82 11:26

015354 G
016236 G

126
127

128
T28.1
128.2

0206%4 G
020630
021224

123;
123
1%3‘
63204
64674

T4
16.1
14.2

006342 G
006354
0064

1210
25554
25964

TS5

76
17
T8
9
UAM

UNITNB

006%26 G

1211

G
G
G
G
G

1212
1213
1214
1215
1348#

002246 G

14624

WREH
= 000002 G
WRENH = 000100 G
WRVH = 000040 G

XSALWA=
X$FALS=
X$OFFS=
X$TRUE=
SPATCH
.
=

000000
000040
000400
000020
021504 6
021540

021540

"8S.

ERRORS DETECTED:

SEQ 0148

1209

006524 G

006602
006666
006754
007024
= 000200

F 12
17-JUN-82
12:02 PAGE 149
CROSS REFERENCE TABLE == USER SYMBOLS

1230
1231

016710 G
017652 G

30A(1052)

14340
13924
}zzgl

3809
2848

4005

3044

3360

3460

4581

4697

66274

6639

10944
10944
10944
10944

66264
1098#
6646

15004

1511

16484

2163

000
O

CVCDAB.0BJ,CVCDAB.SEQ/CRF
: SYM/SOL/NL : TOC=SVC/M!_,CVCDAB.P11
RUN-TIME: 44 40 3 SECONDS

RUN-TIME RATIO: 378/88=4.2
CORE USED:
(31 PAGES)
16K

2251

2294

2316

2339