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Document:	MS11-E J MOS Memory User's Manual
Order Number:	EK-MS11E-OP
Revision:	001
Pages:	22
Original Filename:	EK-MS11E-OP-001_Oct76.pdf

OCR Text

MS11-E-J MOS memory
user’'s manual

alilaliltlall I

EK-MS11E-OP-001

MS11-E-J MOS memory
user’'s manual

digital equipment corporation - maynard, massachusetts

1st Edition, October 1976

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this
manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

MASSBUS

DECCOMM

PDP

DECsystem-10

RSTS
TYPESET-8
TYPESET-11

DECSYSTEM-20
DECtape
DECUS
DIGITAL

UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION

CHAPTER 2

INSTALLATION

2.1

GENERAL

JUMPER VERIFICATION

. .. ... .................

2-1

2.3

SWITCH ARRANGEMENT

. . ... .................

2-1

VOLTAGECHECK

2.5

BACKPLANE INSTALLATION

2.6

DIAGNOSTICCHECK

. ... ... .. .. . ... . . . . . .

... ..... .. ... ...

2-1

... ......

2-1

... ... ..............

2-3

. .. .. ... .................

ILLUSTRATION

Figure No.

2-1

Title

MS11-F Module

Page
22

TABLES
Table No.

Title

1-1

Significant System Specifications

1-2

MS11 Options

. . .. ... ... ... ... ...

2-1

Module Jumper Installation

. . .. ... ... ............

2-2

MS11 DC Voltage Tolerances

. . . . . . ... ... ... ......

2-3

MS11 Memory Pinouts

iii

CHAPTER 1
INTRODUCTION

The MS11-E - MS11-J (referred to herein as MS11)
memories

comprise

group

MOS

semi-con-

ductor, random-access memories that are designed

The use of MOS memory circuits provides advantages (both economical and operational) not available with core memory systems. The cost-per-bit

to be used with the PDP-11 Unibus. Each memory

for MOS memories is low and, unlike core mem-

assumes the role of a slave device to the PDP-11

ory, this cost remains approximately constant with

processor or to any peripheral device that is desig-

size.

nated bus master. The group provides storage for

16- or

18-bit data words (two parity bits are in-

cluded in the 18-bit word), with capacity ranging
from 4096 (4K) words to 16,384 (16K) words in 4K
blocks. An MS11 memory can be assigned adjacent
4K blocks of addresses anywhere within the 124K
Unibus address space. A special feature of the 16K

MSI1

allows the assignment of part of the 1/0

page to memory, although this can be done only

for processors without memory management. Table
1-1

lists the significant specifications of an

MSI11

system.

tive

readouts;

consequently,

the

write-after-read

cycle time associated with core memory is eliminated.
such

Furthermore,
as

those

used

with
in

dynamic
the

MSII,

MOS

devices

power

con-

sumption is much lower than with core memory.

The disadvantage of MOS storage volatility (i.e.,
data is not retained when power is lost) is compensated

for

the

availability

of battery-sup-

ported power supplies that enable data retention

The logic components

of an

MSI]

memory are

mounted on a single hex printed circuit board; the
module has DEC designation M7847. The storage
elements are 4096 X

1-bit, N-channel, MOS mem-

ory

devices.

Unlike core, MOS memory provides non-destruc-

row

of these

devices

for as long as several hours. The MS11 is designed

for a special low-power mode to maximize the effectiveness of battery-powered operation.

mounted on a module for each 4K block of ad-

Because the data storage element is a capacitor in

dresses that is assigned to the memory; e.g., a 16K

the MOS storage device, all memory locations in

memory has 4 rows of 18 devices, an 8K memory

the MOS memory must be periodically refreshed so

has but 2 rows of devices. Table 1-2 lists the avail-

that the data remains valid. The controller on the

able MS11 options and the respective bit and word

memory module includes the logic and timing cir-

capacities.

cuits to carry out the periodic refreshing operation.

Table 1-1

Significant System Specifications

Characteristic

Specification

Storage Capacity

4096 (4K) to 16,384 (16K) words, in 4K blocks

Data Word Length

16 data bits, 2 parity bits

Maximum Access Time (ns)
Normal Operation

550

Refresh Conflict*

1250

Maximum Cycle Time (ns)
Normal Operation

700

Refresh Conflict*

1400

Refresh Cycle Rate

One cycle every 25 us (typical); maximum of one
cycle every 22.5 us

Maximum Power Consumption (watts)

Idle

700 ns Cycle

MS11-E

12.3

23.5

MSI11-F

13.0

MSI11-H
MSI11-]

243

13.8
14.5

25.8

Maximum Current Drain (mA)

25.0

Idle

700 ns Cycle

1500

MSI11-E
+5 Vde

BB+5 Vdc

500

+15 Vdc

800

-15 Vde

100

1500

MS11-F
+5 Vdc

BB+5 Vdc

500

+15 Vde

100

850

-15 Vde

100

1500

MS11-H
+5 Vdc

BB+5 Vdc

500

+15 Vde

150

900

-15 Vdc

100

1500

MS11-J
+5 Vdc

BB+5 Vde

500

+15 Vdc

200

950

-15 Vde

100

*A characteristic of dynamic MOS memory devices is that they must be cycled periodically to ensure data validity. These cycles are

known as refresh cycles and the controller on these memory modules has all the logic and timing circuits necessary to ensure that
these cycles are performed.

Should a processor or NPR request (MSYN) come during a refresh cycle, it is held up until the refresh

cycle is completed and then processed.

The Refresh Conflict time is the maximum amount of time that a normal cycle may be held

up by a refresh cycle. The amount of time lost to bus masters because of refresh is dependent on the bus activity. For a system that
uses the bus at a maximum rate (700 ns cycles) the loss of memory availability is less than 3 percent.

bus cycle every 1.4 us, the loss of availability is typically less than 3/4 percent.

For a system with an average

Table 1-2
MS11 Options

Option

Word Bit

Data Word

Designation

Length

Capacity

MS11-E

MS11-EP

MS11-F

MS11-FP

MS11-H

12K

MS11-HP

12K

MS11-J

16K

MS11-JP

16K

NOTE

18-bit words include two parity bits; an M7850 Parity
Control module must be used with the parity options.

CHAPTER 2
INSTALLATION

2.1

2.3

GENERAL

SWITCH ARRANGEMENT

wires relating to the number of memory chip banks

The MSI1 Memory is assigned Unibus address
space by the arrangement of switches A - E. The
switches must be arranged by the user before the

are in

place. Next, certain switches must be ar-

memory is installed.*

ranged

Installation of the MSI11 is relatively simple. First,

the user should verify that factory-installed jumper

assign

Unibus

address

space

the

MSI11. The backplane should then be checked to ensure that the required dc voltages are available. Fi-

2.4

nally, the module is inserted into the backplane and

Before the module is inserted in the backplane,
check the backplane to ensure that the required dc
voltages are present and within tolerance. The dc

a diagnostic check is carried out to assure correct

operation.

These

procedures

are discussed

VOLTAGE CHECK

voltages are listed in Table 2-2; Table 2-3 lists the

fully in following paragraphs.

MSI1 pin-outs.

All four dc voltages must be supplied for system operation. If data retention is desired when the ac
power is removed, the +5 Vdc supply can be pow-

Figure 2-1 shows the MS!1 module (an 8K mem-

ory is illustrated). The array of chips is located in
the upper-right quarter of the board. At the leftcenter of the board are eyelets W1
which

appropriate jumpers

are

ered down and the other supplies maintained.

- W6, into

inserted.

the

lower-right of the eyelets is the DIP switch (E111)
which is configured according to the MS11 address

Table 2-1

Module Jumper Installation

assignment. E111 has eight individual contacts that
may be identified by numbers or letters on the

Memory

switch; however, the contacts are identified by et-

Desi

sgnation |

ched letters A — J on the printed circuit board (this
notation is followed throughout the text and in the

MS11-E/EP
MS11-F/FP
MS11.-H/HP
MS11-J/JP

logic drawings).

2.2

JUMPER VERIFICATION

The

MSI1

Memory

is shipped with

4K
8K
12K
16K

factory in-

Eyele:) P&;irs Connected
Yy

Jumpers

'N3wWa WiW2 W5-W6
X

X
X

Table 2-2

stalled jumpers appropriate for the memory size.

MS11 DC Voltage Tolerances

The user should check the module to ensure that

the correct jumpers are in place. Table 2-1 lists the

DC Voltage

memories by size and indicates the jumpers that are

installed for each.

Memory

A 16K memory will normally op-

Minimum

Maximum

4.75

5.25

erate with switch H closed, in addition to the in-

+15

14.50

16.50

stalled jumpers; however,

-15
BB+5

-16.50
4.75

~13.50
5.25

a 16K memory installed

in a 32K PDP-11 requires special consideration.*

*Refer to Paragraph 4.2 of MS11-E-J MOS Memory Maintenance Manual (EK-MS 11E-MM-001).

2-1

Figure 2-1

MSI11-F Module

2-2

Table 2-3
MS11 Memory Pinouts

]

GND

| Do2

| Dot

| BB+S

| D4

| D03

| INT

| PAR

GND

c | D00 | GND

| TP

SSYN | DET

| Do6

| Dos

| TP

LO
H

| Do

| D07

| A0l

| AcO

]

DI0

| D09

| A03

| A02

D12

| D11

| Ao5

| A4

pi4

| D13

| A07

| AO6

]
| TP

DI5 | A0S | AO8 | TP

A1l

| Al10

A13

| AI2

+15

Al5

| Al4

-15

A17

| A6

GND

GND | 1

GND |

SSYN | co

MSYN

;

|GND

| GND

GND

*Points marked by ] are tied together to provide grant continuity on backpiane.

2.5

trol module is to be used with the MS11, it must be

BACKPLANE INSTALLATION

When the dc voitages have been verified, insert the

installed in the same backplane; the M7850 can oc-

MSI11 into the Unibus backplane. Presently, three

cupy any of the backplane slots that are available

backplanes can be used with the MSI11, although

to the MS11.

other backplanes may become available; these three
are DDI11-C, DDI11-D, and DDI11-P. The DD11-C
is a 4-slot backplane; the MS11 can be inserted into

2.6

slot 2 or slot 3. The DD11-D is a 9-slot backplane;

When the memory is connected to the Unibus, run

slots 2 - 8 can be used for the MS11. The DDI11-P

the

is another 9-slot backplane, which is used with the

memory is operable. If a problem arises, follow the

PDP-11/04 or PDP-11/34. If an M7850 Parity Con-

instructions in the diagnostic.

2-3

DIAGNOSTIC CHECK
MSI1

diagnostic

program

verify that

the

APPENDIX A

MS11 SWITCH SETTINGS

Table A-1 first lists the 31 addresses that can be as-

signed as the starting address on the MS11 module.
Listed next is the number of Unibus addresses below the MSI11 starting address; e.g., there are 8096

(8K)

Unibus

addresses

below

starting

address

0400005. Finally, the third column lists the switch
settings that will produce the desired address assignment. The MSI1 ending address is automatically determined by the starting address and the memory

size. Table A-2 shows how switches H, J, and

must be arranged for normal operation and when
1/0 page space is assigned to the MS11.

Table A-1

[

/)‘

Switch Settings for MS11 Starting Addresses

MS11 Starting Address

Unibus Addresses Below

Switch Selection

(Octal)

Starting Address

(Switch OFF = Logic 1)
A[B|C|DIJE

000000

]l1]lo0

111

lol1

040000

]l1]ol]l1

060000

12K

100000

16K -

140000

24K

28K

120000

20K

160000

[

200000

CEF e el
[3]
P

020000

]o0of]o

1|1

lolo

1) PR— T

|11

{ol1

T T

I T

220000

36K

jol1

240000

40K

t]Jolol1

260000

44K

300000

‘Qg% —~——!

320000

340000
360000

400000

{ololo

1]l0]0lo0o

ofl1

{11

56K

|11

1]o0

60K

|t1t]lo

64K T

ol1]1]0

420000

68K

440000

72K

460000

500000

76K

]lo]o

8OK—~—~—""">"

lo]o

520000

84K ~

olo

|11

540000

8K~

|11

|o0

ojlol1]|o0

560000

92K -~

600000

~ 96Koe

620000

100K

"+—~0

—~

olo

[ 1]

640000

104K

olo

660000

108K

olo

700000

112K

ololojolo

720000

116K

1114111

740000

120K

111111

NOTE

Switch contacts are open when switch is in OFF position

A-2

Table A-2

Switch Settings for I/O Page Operation
Memory Size Determination
Switch

Memory Option

MS11-E/EP, MS11-F/FP,

OFF

MS11-J/JP, Normal Use

OFF

MS11-J/JP, Lower 2K of I/O

OFF

MS11-H/HP

page assigned to memory*

MS11-J/JP, Lower 3K of 1/O
page assigned to memory*

*Set switches A through E for a starting address of
100000s .
NOTE

Switch contacts are open when switch is in OFF position.

A-3

Reader’s Comments

USER'S MANUAL

MS11-E-J MOS MEMORY

EK-MS11E-OP-001

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