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EK-LSIFS-SV-PRE

August 1981

610 pages

Original

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Document:	LSI-11 Systems Service Manual
Order Number:	EK-LSIFS-SV
Revision:	PRE
Pages:	610
Original Filename:	LSI-11_Systems_Service_Manual_Aug81.pdf

OCR Text

lSI-11 Systems
Service Manual

FOR INTERNAL USE ONLY

Preliminary, April 1978
1st Edition, March 1979
1st Edition (Rev), September 1979
2nd Edition, November 1980
3rd Edition, August 1981

Digital Equipment Corporation
All Rights Reserve.d

The material in this manual is for informational purposes and
is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for
any errors which may appear in this manual.
Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation:
DIGITAL
DEC
PDP
DECUS
UNIBUS
DECLAB

DECsystem-10
DECSYSTEM-20
DIBOL
EduSystem
VAX
VMS

3/82/14

MASS BUS
OMNIBUS
OS/8
RSTS
RSX
lAS
MINC-11

CONTENTS
SYSTEMS CONFIGURATIONS
GENERAL CONFIGURATION RULES
GENERAL CONFIGURATION RULES ................................................. 3
Backplanes ........................................................................... 3
Configuring Single Backplane Systems ................................ 3
Configuring Multiple Backplane
Systems ................................................................................4
Power Supplies ..................................................................... 4
Possible Problems Installing the
70-08612 or BC03Y-XX Cables ............................................. 7
Possible Problems Installing BC05L. ..................................... 7
MEMORY ..........................................................................................8
Memory Refreshing Rules ..................................................... 8
DMA Refresh Configuration .................................................. 8
Configuration Examples .................................... , ................... 9
REFRESH CONFIGURATION PROCEDURE ..................................... 13

PDP-11V03 AND PDP-11T03 SYSTEMS
PDP-11 V03 ..................................................................................... 23
Modules Included in the Basic System ............................... 27
PDP-11 V03-A/E Module Utilization .................................... 28
PDP-11 V03-F IH Module Utilization .................................... 30
PDP-11 T03 ......................................................................................31
Modules Included in the Basic System ............................... 34
Module Utilization ...............................................................35

PDP-11T03-L AND PDP-11V03-L SYSTEMS
PDP-11 T03-L ..................................................................................37
PDP-11 T03-L Operator Switch Panel ............................................. 38
RLO 1 Disk Drives ............................................................................41
PDP-11 V03-L ..................................................................................42
11 V03-L System (LE, LH, and LJ) ................................................... 46
'11 V03-L Early Systems (LA, LC, and LD) ...................................... .4 7

PDP-11V23 AND PDP-11T23 SYSTEMS
PDP-11 V23 SYSTEM ...................................................................... 51
PDP-11 V23 Operator Switch Panel .................................... 52
PDP-11T23 SYSTEM .......................................................................61
PDP-11 T23 Operator Switch PaneL .................................... 62
RLO 1 Disk Drives ................................................ ,............... 64
iii

CONTENTS (CONT)
COMMERCIAL SYSTEMS
0322 ...............................................................................................69
Modules Included in the Basic System ............................... 73
Optional Modules for Recommended
Expansion ........................................................................... 75
0324 ...............................................................................................80
Modules Included in the Basic System ............................... 83
Optional Modules for Recommended
Expansion ...........................................................................84
0325 ...............................................................................................90
Modules Included in the Basic System ............................... 92
D333C .............................................................................................93
Compatible Options ............................................................ 94
D335C .............................................................................................95
Modules Included in the Basic System ............................... 95
D336C .............................................................................................97
Modules Included in the Basic System ............................... 98
TELEPHONE COMPANY SYSTEM
CC1A PDP-11V03 SYSTEM .......................................................... 101
CC# 1A Diagnostic Check List ..................................................... 102
LABORATORY SYSTEMS
PDP-11 L03 .................................................................................... 123
Modules Included in the Basic
System .............................................................................. 128
Additional Modules Included
in Optional Systems ......................................................... 129
Module Utilization Notes ................................................... 130
PDP-11/03-BASED MINC/DECLAB-11/MINC SYSTEMS
MODULAR INSTRUMENTATION COMPUTER (MINC) .................... 135
System-Level Diagnostics ................................................ 141
DECLAB-11/MNC SySTEM .......................................................... 144
System-Level Diagnostics ................................................ 148
Modules in the Basic System ............................................ 149
PDP-11/23-BASED MINC/DECLAB-11 /MINC SYSTEMS
MINC ............................................................................................. 155
Systo,n-Level Diagnostics ................................................ 161
Modules in the Basic System ............................................ 162
iv

CONTENTS (CONT)
DECLAB-11/MNC PDP-11 /23-BASED SySTEM ........................... 166
System-Level Diagnostics ............................................... ,169
Modules Included
in the Basic PDP-11/23 System ....................................... 172

CPU/OPTIONS
GENERAL MODULE INFORMATION ........................................................ 179
AO 12 ADV 11-A ANALOG-TO-DIGIT AL CONVERTER ................................. 180
A6001 AAV11-A DIGITAL-TO-ANALOG CONVERTER ............................... 185
BA 11-M ..................................................................................................... 190
BA 11-N ......................................................................................................202
DLV11-KA EIA TO 20 MA CONVERTER .................................................... 223
G653/H223 MMV 11-A CORE RAM MEMORy ........................................... 229
H780 POWER SUPPLIES .......................................................................... 232
M7264-XX LSI-11 PROCESSOR MODULES ............................................. 237
M7269 BUS INTERFACE FOR RKV11-D
DISK DRIVE CONTROLLER ....................................................................... 250
M7270 LSI-11 /2 PROCESSOR MODEL DESIGNATIONS .......................... 266
M7940 DLV11 SERIAL LINE UNIT ............................................................. 270
M7941 DRV11 PARALLEL LINE UNIT ........................................................ 280
M7942 MRV 11-AA READ-ONLY MEMORy ............................................... 286
M7944 MSV 11-B READ/WRITE MEMORY ................................................ 290
M7946 RXV11 FLOPPY DISK INTERFACE ................................................ 293
M7948 DRV 11-P FOUNDATION MODULE ................................................. 302
M7949 LAV11 PRINTER INTERFACE ........................................................ 315

CONTENTS (CONT)
M7950 DRV 11-B GENERAL PURPOSE DMA INTERFACE ......................... 320
M7951 DUV 11-DA SYNCHRONOUS SERIAL LINE INTERFACE .............. 324
M7952 KWV 11-A PROGRAMMABLE REAL TIME CLOCK ......................... 336
M7954 IBV11-A LSI-11/INSTRUMENT BUS INTERFACE ......................... 346
M7955 MSV 11-C MOS READ/WRITE MEMORY ....................................... 352
M7957 DZV 11 ASYNCHRONOUS MULTIPLEXER ..................................... 357
M8012 BDV11 BUS TERMINATOR, BOOTSTRAP,
AND DIAGNOSTIC ROM ............................................................................ 368
M80 13, M80 14 RLV 11 CONTROLLER ...................................................... 384
M8016 .......................................................................................................397
M80 17 DL V 11-E ASYNCHRONOUS SERIAL LINE INTERFACE ............... .402
M80 18 KUV 11-AA WRITABLE CONTROL STORE ..................................... 415
M8021 MRV 11-BA UV PROM-RAM ........................................................... 420
M8027 LPV 11 LP05/LA 180 INTERFACE MODULE ................................... 430
M8028 DL V 11-F ASYNCHRONOUS SERIAL LINE INTERFACE .............. .437
M8029 RXV21 FLOPPY DISK CONTROLLER ........................................... 450
M8043 DL V 11-J SERIAL LINE UNIT ......................................................... .464
M8044/45 MSV11-D, -E MOS READ/WRITE MEMORY ........................... .487
M8047 MXV11-AA/AC MULTIFUNCTION MODULE .................................. 493
M8048 MRV 11-C READ-ONLY MEMORY (ROM) MODULE ..................... 517
M8049 DRV 11-J GENERAL PURPOSE PARALLEL
LINE INTERFACE ......................................................................................529
M8186 KDF 11-AX 11/23 MiCROCOMPUTER ........................................... 543
M9400-XX REV 11, TEV 11, AND BCV 1X .................................................... 555
vi

CONTENTS (CONT)
RK05 .........................................................................................................565

RLO 1/RL02 ...............................................................................................571
RX01 .........................................................................................................575
RX02 ......................................................................................................... 578
APPENDIX A ............................................................................................. 583
APPENDIX B ..............................................................................................601

vii

SYSTEMS CONFIGURATIONS

GENERAL CONFIGURATION RULES

GENERAL CONFIGURATION RULES
The rules and considerations discussed in this section apply to all LSI-11
systems. Refer to subsequent sections for requirements peculiar to specific systems.

Backplanes
LSI-11 systems can be divided into two types: those that use only one
backplane, and those that have multiple backplanes. Single backplane systems are viewed as lumped capacitance. Multiple backplane systems are
regarded as transmission line systems. The characteristics of the two
types differ enough to require separate sets of configuration rules. The
rules are given in terms of power consumption, dc bus loading, and ac bus
loading. DC loading is a measure of the leakage current a module's bus
signal lines draw when high (undriven). One dc load is nominally 105 JlA.
AC loading is a measure of the capacitance a module adds to the bus signal lines. One ac load is 9.35 pF. Backplanes also add ac loading to the
bus. The power consumption, dc loading, and ac loading is listed for each
module in the "CPU/Options" section.

Configuring Single Backplane Systems
1.

The bus can support up to 20 ac loads before additional termination is
required. The processor has on-board termination for one end of the
bus, and after 20 ac loads, the other end of the bus must be terminated
with 120 Q.

A terminated bus can support up to 35 ac loads.

The bus can support up to 20 dc loads.

The bus signal lines on the backplane can be up to 35.6 cm (14 in)
long.

The preceding rules apply only to single backplane systems. The bus cannot be extended off the backplane in any way. If it is, the system is considered a multiple backplane system.
3

Configuring Multiple Backplane Systems
1. a. Up to three backplanes may be connected together.

b. The signal lines on each backplane can be up to 25.4 cm (10 in) long.
2.

Each backplane can have up to 20 ac loads. Unused ac loads from one
backplane may not be added to another backplane if the second backplane loading will exceed 20 ac loads. It is desirable to load backplanes equally or with the highest ac loads in the first and second
backplanes.

Total dc loading of all three backplanes combined can be up to 20
loads.

Both ends of the transmission line should be terminated with 120 Q.
This means that the first backplane should have impedance of 120 Q,
and the last backplane should have a termination of 120 Q.

5. a. The cable connecting the first two backplanes should be at least 1.83
meters (6 ft) long.
b. The cable connecting the second backplane to the third backplane
must be at least 1.22 m (4 ft) longer or shorter than the cable connecting the first and second backplanes.
c. The combined length of the cables should not exceed 4.88 m (16 ft).
d. The cables used must have a characteristic impedance of 120 Q.

Power Supplies
The "CPU / Options" section lists the typical power requirements for each
module. For reliable operation, the sum of all typical current requirements
should be less than 70 percent of the maximum rated current of the power
supply. Refer to the appropriate power supply section for voltage and current ratings.

MASTER

SUPPLY

t--_ _ _ _ _+-_____--1 DCOK
M94()()'YE

70-08612-6A

(2) BC05L-06

M9401

SLAVE

SUPPLY
TEV11

M94()().YB
MR-0759

A Typical System Configuration Using BA 11-M Boxes
Showing Cables Needed for Expansion

NOTE
Expander boxes are normally shipped with W1 installed. This
enables the slave power supply to be powered up and down
without being cabled to the master supply. For system applications, however, it Is recommended that W1 be removed. This
will ensure that the slave supply does not power up unexpectedly if the cable Is loosened.
Business Products systems (0322 and 0324) do not use a POP11/03-J slave console. The two power supplies are connected
by a cable (DEC part number (PN) 70-13371-00). No slave
board is needed. In a standalone device, such as the RKV11-0
disk drive controller, the W1 jumper must be installed and is
not removed if it Is added to a system.

LSI-llCPU

t-------+-----t 0 0

r-__________+-__________~DCOK

GGa

MASTER
SUPPLY

M9400-YE

(2) BC05L-06

BCV1B-061

BC03Y-16

~----~~--~----------~--~

M9401

SLAVE 1
SUPPLY
M9400-YD

BCV1A-l0--1r-____

L-~ (~2-)-B-CO- 5L- -l-0- ~ ~
__

M9401
SLAVE 2
SUPPLY
TEVll

M9400-YB

~--------~----------~--~~~--~

NOTE:
THE TWO (2) BC05L-XX CABLE LENGTHS BETWEEN
THE FIRST AND SECOND BOX SHOULD DIFFER
FROM THE BC05L-XX CABLE LENGTHS BETWEEN
THE SECOND AND THIRD BOX BY AT LEAST FOUR
FEET BECAUSE OF LSI-ll BUS REFLECTIONS.

Typical System Configuration Using Three BA 11-M Boxes
Showing Cables Needed for Expansion

Master /Slave Interface Cables
Length
10.2 cm
15 cm
22.9 cm
27.5 cm
35.6 cm
45.7 cm
124 cm
61.0cm
1.83 m
3.05 m

DECPN
(4 in)
(6 in)
(9 in)
(11 in)
(14 in)
(18 in)
(49 in)
(2 ft)
(6 ft)
(10ft)

70-08612-00
70-08612-0F
70-08612-0K
70-08612-0M
70-08612-1 B
70-08612-1 F
70-08612-4A
70-08612-02
70-08612-6A
70-08612-10

Possible Problems Installing the 70-08612 or BC03Y-XX Cables
On a two box system, connect the remote sockets on the master console
and the slave console with a 70-08612-XX cable.
NOTE
Some of the 70-08612 cables have been found with a connector on backwards. If the DCOK LED on the slave box does
not come on when the master Is turned on, the cable may be
reversed.
If RT-11's clock does not update, the 70-08612 cable may be
In upside down. The cable should be connected pin 1 to pin 1.
The red line should be on the left of both J2 connectors.
Possible Problems Installing BC05L
Some BC05L-XX cables may have the "This Side Up" stickers on the
wrong side of one end. The cables should be connected as follows.
•

M9400-YE or YO pin AA (J 1)
to
BC05L-XX pin 1

•

BC05L-XX pin 1
to
M9401 pin AA (J1)

The pin markings on the BC05L cables are on the connector. The cables
should be flat when run around the POP-11 /03 cable trays, and not twisted.
If the BC05L-XX is plugged in upside down, the bus OCOK line is grounded.
The processor will not power up with this condition. Reverse the cables and
try again.
7

MEMORY
Memory Refresh'ng Rules
All dynamic MOS RAM must be refreshed. Neither CORE RAM nor
ROM / PROM memories need refreshing. Refreshing is available by three
means: processor microcode, Direct Memory Access (DMA), and self-refreshing memory modules.
Processor Microcode Refresh - With processor microcode refresh, the
processor must be strapped to enable the microcode refresh, and the memory module farthest from the processor on the bus must be configured to
reply to refresh cycles. All other memory modules, including memory on the
processor board itself, must have memory reply disabled. If only the 4K of
RAM on the processor is being used, then that RAM must be strapped to
respond to reply.
NOTE
Only quad-sized processor modules have microcode refresh
capabilities. Double-sized processor modules do not. With
double-sized processors, either DMA refresh or self-refreshing
memory must be used.
DMA Refreshing - The REV 11-A or REV 11-C modules may be used to provide DMA memory refreshing. When using the REV11 to refresh memory,
the REV 11 refresh capability must be enabled via a strap on the REV 11
board, and the processor microcode refreshing must be disabled. The memory module farthest from the REV 11 should have reply to refresh enabled. If
a quad-sized processor module with on-board RAM is used, usually that
RAM will be the one strapped to reply to the refresh because it will be the
farthest from the REV 11 option.
DMA memory refreshing can be done by a customer's own module if that
module makes sufficient memory accesses within the required time.
Self-Refreshing Memory - Self-refreshing memory does not use the bus to
accomplish refreshing; therefore, no memory module need be strapped to
reply to a memory refresh cycle.
Self-refreshing memory can be combined with nonself-refreshing memory
on the same bus; however, when this is done, other refreshing techniques
similar to processor microcode or DMA must be used to refresh the conventional memory. If an MSV 11-C is used with a KD 11-F or an MSV 11-8,
configure the MSV 11-C for external refresh.
DMA Refresh Configuration
In systems that use a REV 11-C for refresh and a TEV 11 for bus termination,
the REV 11-C should be placed immediately after the memory modules.
8

ORV 11-B or RKV 11-0 modules should follow the REV 11-C in order to be
lower in OMA priority.
Systems that use a REV 11-A for both refresh and termination must have it
in the last slot.
No open slots are permitted between the processor and the far-end bus terminator. The OMA and interrupt priority scheme is indicated in the following
figure. The arrow indicates decreasing priority.

PROCESSOR
2

I
I
I
I

,r
I
3
4

I
I

TERMINATOR _

MR-0761

Q-Q Backplanes OMA / Interrupt Priority Scheme

Configuration Examples
If an LSI-11 system must be configured with memories other than the
MSV 11-CO, try to use one of the following engineering-approved examples.

Ex. 1

M7264-0, -AB, -BB CPU
M7944 MSVll-B 4K MEMORY

M7940DLV11 SLU

M7944 MSVll-B 4K MEMORY

M9400-YA REVll-A
BOOT/TERMINATOR

MR-0798

In this type of configuration, use the M9400 (REV 11) to perform refresh operations.
9

Jumpers would be as follows.
M7264

M7944
M9400-YA

W4
W9
W10
W4
W2

IN
OUT
OUT
IN (both modules)
IN

Ex. 2

Disable CPU controlled refresh.
Enable reply from CPU memory.
Enable CPU reply during refresh.
Disable reply during refresh.
Enable DMA refresh.

M7264-0. -AB. -BB CPU
M7955-YD MSV11-CD 16K MEMORY
M9400-YA REV11-A
BOOT/TERMINATOR

M7944 MSV 11-B 4K MEMOR Y

MR-0799

In this type of configuration, use REV 11 to control refresh operations.
Jumpers would be as follows.
M7264

M7955
M9400-YA

W4
W9
W10
W7
W6
W2

IN
OUT
OUT
OUT
IN
IN

Ex.3

Disable internal refresh.
Disable reply during refresh.

M7264-YA. -YB CPU
M7955-YD MSV11-CD 16K MEMORY
M9400-YA REV11-A
BOOT/TERMINATOR

M7944 MSV11-B 4K MEMORY

MR-0800

In this type of configuration, use REV 11.
Jumpers would be as follows.
M7264

M7955
M7944
M9400-YA

W4
W9
W10
W7
W6
W4
W2

IN
IN
OUT
OUT
OUT
IN
IN

Disable CPU refresh.
Disable reply from CPU memory.
This is a "don't care" (if W9 is in).
Disable internal refresh.
Enable reply during refresh.
Disable reply during refresh.
Enable DMA refresh.
10

Ex.4

M7264-0. ·AB. ·BB CPU
M7955-YD MSV11·CD 16K MEMORY

MA·0801

In this type of configuration, use CPU refresh.
Jumpers would be as follows.
W4
W9
W10
W7
W6

M7264

M7955

Enable CPU refresh.
Enable reply from CPU memory.
Disable CPU reply during refresh.
Disable internal refresh.
Enable reply during refresh.

OUT
OUT
IN
OUT
OUT

Ex.5

M7264·0. ·AB • .aB CPU
M8018 KEV11·WA WCS
M7t55-YD MSV11-CD 16K MEMORY

........

M7944 MSV11·B 4K MEMORY

M9400·YE BUS JUMPER

BCV1B

M9401 BUS JUMPER

M94()()'YC BOOT/TERMINATOR

M7952 KWV11-A REAL TIME CLOCK
M7950 DRV11·B DMA INTERFACE
M7940 DLV11 SLU

M94()()'YD BUS JUMPER

BCV1A

M8028 DLV11·F SLU

M9401 BUS JUMPER
M7962 RCV' 1-0

~~~~RFACE

M94()()'YB

~~~~~NATOR

MA·0802

In this type of configuration, use the REV11-C (M9400-YC) to provide refresh.
Jumpers would be as follows.
M7264

M7955
M7944
M9400-YC

W4
W9
W10
W7
W6
W4
W2

IN
OUT
OUT
OUT
IN
IN
IN

Disable CPU controlled refresh.
Enable reply from CPU memory.
Enable CPU reply during refresh.
Disable internal refresh.
Disable reply during refresh.
Disable reply during refresh.
Enable DMA refresh.

Do not use any configuration with DMA devices between the CPU and a
REV 11 performing DMA refresh.
The BDV 11 (M80 12) is always at end of the bus.
The preferred order of modules in systems is:
CPU
WCS
Memory
DMA refresh
Real time clock
INT fastest

1
slowest
DMA fastest

slowest
Program transfer (ROMs, D / As, etc.)
Terminator

REFRESH CONFIGURATION PROCEDURE
Is this CPU a KD 11-H (M7264-Y A)?
YES

! !
2

Go to step 6

Does the system contain an MSV 11-8 (M7944) memory?
YES

•

The CPU should have jumpers W10 and W4 installed.

•

If the system has a REV 11-A (M9400-Y A) or a REV 11-C
(M9400-YC), jumper W2 should be removed.

•

If the system has MSV 11-CD (M7955) memories, jumpers
W6 and W7 should be installed in the MSV 11-CD.

•

If the system has:
MSV11-DA M8044-YA
MSV11-D8 M8044-Y8
MSV 11-DC M8044-YC
or
MSV 11-DD M8044-YD
there are no refresh configuration requirements for this
module.

Does the system contain a DMA device other than the REV 11-A
(M7900-YA) or a REV11-C (M9400-YC), such as an RKV11-D (M7969)
or DRV 11-8 (M7950)?
YES

•

Does the system contain a REV 11-A (M9400-Y A) or
REV 11-C (M9400-YC)?

YES

Is the CPU a DI80L processor (40-pin chip with 2
dies)?

YES

•

1
•

You cannot configure this system without
a REV11.

The CPU (M7264-YA) should control refresh;
jumper W4 removed and W10 installed.

•

The MSV 11-B (M7944) farthest from the CPU will
reply; jumper W4 removed.

•

All other MSV11-B memories should have W4 installed.

•

If the system has MSV 11-CO (M7955) memories,
jumpers W6 and W7 should be installed.

•

If the system has:
MSV 11-0A M8044-Y A
MSV11-0B M8044-YB
MSV11-0C M8044-YC
or
MSV 11-00 M8044-YO
there are no refresh configuration requirements
for this module.

•

The REV11-A (M9400-YA) or REV11-C (M9400-YC)
should control refresh; jumper W2 on the M9400 should
be installed.

•

The MSV 11-B (M7944) farthest from the REV 11 should
reply to refresh; W4 removed.

•

All other MSV11-B memories should have W4 installed.

•

The CPU should not control refresh; jumpers W4 and
W10 installed.

•

If the system has MSV 11-CO (M7955) memories, jumpers
W6 and W7 should be installed.

•

If the system has:
MSV 11-0A M8044-Y A
MSV 11-0B M8044-YB

MSV 11-DC M8044-YC
or
MSV11-DD M8044-YD

there are no refresh configuration requirements for this
module.

Does the system contain a REV 11-C (M9400-YC)?

YES

•

The REV 11-C (M9400-YC) should control refresh; W2 installed.

•

The MSV 11-B (M7944) farthest from the REV 11 should
reply to refresh; jumper W4 removed.

•

All other MSV 11-B (M7944) memories should have W4 installed.

•

There should not be a DMA device placed between the
CPU and REV11-C (M9400-YC).

•

If the system has MSV 11-CD (M7955) memories, jumpers
W6 and W7 should be installed.

•

If the system has:
MSV 11-DA M8044-Y A
MSV11-DB M8044-YB
MSV 11-DC M8044-YC
or
MSV 11-DD M8044-YD
there are no refresh configuration requirements for this
module.

Is the CPU a DIBOL processor (40-pin chip with 2 dies)?

YES

•

1
•

You cannot configure refresh on a system without a
REV11-C.

The CPU (M7264-Y A) must control refresh; jumper W 10 installed and W4 removed.

•

If a REV11-A (M9400-YA) is present, its refresh must be disabled. This means jumper W2 must be removed.

•

The MSV 11-8 (M7944) farthest from the CPU should respond to
refresh; jumper W4 removed.

•

All other MSV 11-8s (M7944) should have W4 installed.

•

If the system has MSV 11-CO (M7955) memories, jumpers W6
and W7 should be installed.

•

If the system has:
MSV 11-0A M8044-Y A
MSV11-08 M8044-Y8
MSV 11-0C M8044-YC
or
MSV 11-00 M8044-YO
there are no refresh configuration requirements for this module.

FROM 1,5
6

Does the system contain a REV 11-A (M9400- Y A) or REV 11-C (M9400YC)?
YES

Is the CPU a 0180L CPU (40-pin chip with 2 dies)?

YES

•

You cannot configure this system without a
REV11.

1
•

Does the system contain an MSV 11-8 (M7944)?

YES

•

The CPU (M7264) must control refresh and reply
to refresh; jumpers W4 and W10 removed.

•

The MSV 11-8 (M7944) farthest from the CPU
should reply to refresh; jumper W4 removed.

•

All other MSV 11-88 (M7944) should have jumper
W4 installed.

•

If the system has:
MSV11-DA M8044-YA
MSV11-DB M8044-YB
MSV11-DC M8044-YC
or
MSV 11-DD M8044-YD
there are no refresh configuration requirements
for this module.

•

The CPU must control refresh; jumper W4 removed and
W10 installed.

•

The MSV 11-B (M7944) farthest from the CPU should reply to refresh; jumper 4 removed.

•

All other system MSV 11-Bs (M7944) should have jumper
W4 installed.

•

If the system has MSV 11-CD (M7955) memories, jumpers
W6 and W7 should be installed.

•

If the system has:
MSV11-DA M8044-YA
MSV11-DB M8044-YB
MSV11-DC M8044-YC
or
MSV 11-DD M8044-YD
there are no refresh configuration requirements for this
module.

7 Does the system contain a DMA device other than that of the REV 11-A
(M9400-Y A) or a REV 11-C (M9400-YC), such as RKV 11-B (M7969) or
DRV11-B (M7950)?
YES

•

YES

Does the system contain MSV 11-B (M7944) memory?
NO

•

The REV 11-Y A (M9400-Y A) or REV 11-C (M9400YC) should control refresh; jumper W2 installed.

•

The CPU should reply to refresh; jumper W4 installed and W10 removed.

•

All MSV11-B (M7944) memories should have jumper W4 installed.

•

If the system has MSV 11-CO (M955) memories,
jumpers W6 and W7 should be installed.
If the system has:
MSV 11-0A M8044-Y A
MSV 11-0B M8044-YB
MSV11-0C M8044-YC
or
MSV11-00 M8044-YO
there are no refresh configuration requirements
for this module.

•

The REV 11-A (M9400-Y A) or' REV 11-C (M9400-YC)
should control refresh; jumper W2 installed.

•

The MSV 11-B (M7944) farthest from the REV 11-A
(M9400-Y A) or REV 11-C (M9400-YC) should reply to refresh; jumper W4 removed.

•

The CPU should not reply to refresh; jumper W4 installed
and W10 installed.

•

All remaining MSV11-B memories should have W4 installed.

•

If the system has MSV 11-CO (M7955) memories, jumpers
W6 and W7 should be installed.

•

If the system has:
MSV11-0A M8044-YA
MSV11-0B M8044-YB
MSV 11-0C M8044-YC
or
MSV 11-00 M8044-YO
there are no refresh configuration requirements for this
module.

•

Does the system contain a REV 11-C (M9400-YC)?
YES

+
•

Is the CPU a OIBOL processor (40-pin chip with 2 dies)?

YES

•

You cannot configure this system without a
REV11.

1
•

Does the system contain MSV 11-B (M7944) memory?

YES

••

The CPU (M7264) should control refresh and reply; jumpers W4 and W10 removed.

•

If the system has a REV11-A (M9400-YA); jumper
W2 should be removed.

•

If the system has MSV 11-CO (M7955) memories,
jumpers W6 and W7 should be installed.

•

If the system has:
MSV11-0A M8044-YA
MSV 11-0B M8044-YB
MSV 11-0C M8044-YC
or
MSV 11-00 M8044-YO
there are no refresh configuration requirements
for this module.

•

The CPU (M7264) should control refresh; jumper W4.

•

The MSV 11-B (M7944) farthest from the CPU should reply to refresh; jumper W4 removed.

•

All remaining MSV11-Bs (M7944) should have jumper W4
installed.

•

If the system has a REV11-A (M9400-YA), jumper W2
should be removed.

•

If the system has MSV 11-CO (M7955) memories, jumpers
W6 and W7 should be installed.
19

•

If the system has:
MSV 11-0A M8044-Y A
MSV 11-0B M8044-YB
MSV 11-0C M8044-YC
or
MSV 11-00 M8044-YO
there are no refresh configuration requirements for this
module.

Does the system have MSV 11-B (M7944) memory?
YES

•

The REV11-C (M9400-YC) should control refresh; jumper
W2 installed.

•

The CPU (M7264) should reply to refresh; jumper W 10 removed and W4 installed.

•

If the system has MSV 11-CO (M7955) memories, jumpers
W6 and W7 should be installed.

•

If the system has:
MSV 11-0A M8044-Y A
MSV 11-0B M8044-YB
MSV 11-0C M8044-YC
or
MSV 11-00 M8044-YO
there are no refresh configuration requirements for this
module.

10 Is the CPU an M7264-EB, -FB, -HB, or -JB?
YES

•

The REV 11-C (M9400-YC) should control refresh; jumper
W2 installed.

•

The CPU should reply to refresh; jumper W10 removed
and W4 installed.

•

All MSV11-B (M7944) memories should have jumper W4
installed.

•

If the system has MSV 11-CO (M7955) memories, jumpers
W6 and W7 should be installed.

•

If the system has:
MSV11-0A M8044-YA
MSV11-0B M8044-YB
MSV 11-0C M8044-YC
or
MSV 11-00 M8044-YO
there are no refresh configuration requirements for this
module.

•

The REV 11-C (M9400- YC) should control refresh; jumper W2 installed.

•

The MSV 11-B (M7944) farthest from the REV 11-C should reply
to refresh; jumper W4 removed.

•

All other MSV 11-Bs (M7944) should have jumper W4 installed.

•

The CPU should have jumpers W4 and W10 installed.

•

If the system has MSV 11-CO (M7955) memories, jumpers W6
and W7 should be installed.

•

If the system has:
MSV 11-0A M8044-Y A
MSV11-0B M8044-YB
MSV 11-0C M8044- YC
or
MSV11-33 M8044-YO
there are no refresh configuration requirements for this module.

PDP-11V03

PDP-11V03 AND PDP-11T03 SYSTEMS

PDP-11V03
The PDP-11V03 includes a PDP-11 /03 computer, an RX01 dual floppy disk
drive, and either a VT52 DECscope or an LA36 DECwriter II. Early models
have 8K of memory, while later models have 16K. All models are configured
to boot on power-up and halt on BREAK. The figures and tables that follow
describe the models, specifications, and components.

llV03 CABINET

MR-0835

PDP-11 V03-E / H

PDP-11V03

IIIIIIIIII:!::::::
1111111I11:111111111:11111!11
11111111::1111111111
11111111
11111111
1111111111:11111111
1111111::::1111111:::111111111
11111111111111111
11111111

VT52 DECSCOPE

llV03 CABINET
MA-0836

PDP-11 V03-A / F

r®i

AC LINE
(J15V,20A,
230V,lOAI

MATE-N-LOK
CONNECTOR

c==:J~c==:J~c::=::J~ -------~

Fr=====0

BN52B-7F FROM VT52
OR
BC05F-15 FROM LA36

MR-0837

PDP-11V03
LA36

VT52

8K
words

EA
ED

AA
AD

16K
words

HA
HB
HC

FA
FB
FC

PDP-11 V03 System Model Designations

8K System Component Model Designations
PDP-11 V03 System Model Designations
System
Requirements

Input Power (V)

115

230

115

230

Frequency (Hz)

PDP-11 /03 Computer

LA36
VT52

RXV11
(RX01 Floppy
with Interface)

H984 (Cabinet)

PDP-11V03
16K System Component Model Designations

PDP-11V03 System Model Designations
System
Requirements

Input Power (V)

115

230

115

230

115

Frequency (Hz)

POP-11 /03 Computer

LA36
VT52

RXV11
(RXO 1 Floppy
with Interface)

H984 (Cabinet)

115V

POWER
CONNECTOR

50/60 Hz
RECEPTACLE

wi I
GJ)

o
@

NEMA #5-15P
DEC # 90-08938

5-15R
12·05351

CPU
CABINET

50Hz

230 V

PLUG

RECEPTACLE

~
~c::::I

NEMA #6·15P
DEC # 90-08853

LA36

VT52

CPU
CABINET

6·15R
12·11204

LA36

VT52

AMPERAGE
TYPICAL
MAXIMUM

9.6
10.8

2.0

1.0

4.7
5.3

1.0

0.5

WATTAGE
TYPICAL
MAXIMUM

800
940

160

118
118

820
960

160

300

118
118

BTU/HOUR
TYPICAL
MAXIMUM

2730
3210

550
1020

400
400

2800
3280

550
1020

400

81.6 Kg
1180 Ib,)

46.3 Kg
11021bs)

20.0 Kg
144lbs)

81.6 Kg
11801bs)

46.3 Kg
11021bB)

20.0 Kg
144 lb.)

WEIGHT

400

MR·0838

Specifications
26

PDP-11V03
Modules Included in the Basic System
Processor
KD11-F (M7264) in PDP-11V03-A/E
Resident memory addressed as bank 0
CPU refresh disabled
Powers up to 173000
KD11-R (M7264-YA) in PDP-11V03-F/H
No resident memory
CPU refresh disabled
Powers up to 173000

Memory
MSV 11-B (M7944) in PDP-11 V03-A I E
4K RAM
Refreshed by REV 11-A
Addressed as bank 1
MSV 11-CD (M7955-YO) in PDP-11 V03-F I H
16K RAM
Internal refresh
Addresses start at bank 0
Part of the KD 11-R processor option

Serial Line Interface
DL V 11 (M7940)
Device address 177560
Vector 60
300 baud in PDP-11V03-E/H (LA36)
9600 baud in PDP-11 V03-A I F (VT52)
20 rnA active transmitter and active receiver
One stop bit, eight data bits, no parity
Framing error (BREAK) asserts BHAL T

PDP-11V03
Floppy Disk Interface
RXV 11 (M7946)
First device address (disk 0) 177170
First vector 264
Second device address (disk 1) 177150
Second vector 270

Bootstrap I Diagnostic ITermlnator
REV11-A (M9400-YA)
Bootstrap enabled
Diagnostics enabled
Refresh enabled in PDP-11 V03-A / E
Refresh disabled in PDP-11 V03-F / H
120 g terminator

PDP-11V03-A/E Module Utilization
A

CD
0
®
®
NOTE:

®
0
®
CD

M7264 PROCESSOR (KD11-F)
M7944 (MSVll-B)

M7940 (DLVll)

M7946 FLOPPY CONTROL (RXV11)

M9400-YA (REVll-A)
EMPTY

EMPTY
CIRCLED NUMBERS (DTHROUGH
INTERRUPT PRIORITY SEQUENCE.

® REFER TO DMA AND

Basic 8K System

CD
@

M7264 PROCESSOR (KDll-F)
M7944 4K MEMORY (MSVll-B)

M7944 4K MEMORY (MSVll-B)

CD
0)

M7940 SERIAL LINE UNIT (DLV11)
M7944 4K MEMORY (MSVll-B)
®
®
M9400-YA BOOT/TERMINATOR (REVll-A)
M7946 FLOPPY DISK CONTROLLER (RXV11) (})
®
NOTE: CIRCLED NUMBERS (j) THROUGH ® REFER TO
DMA AND INTERRUPT PRIORITY SEQUENCE.
MA·0939

16K System

PDP-11V03

CD
0
®

CPu (KDllF)
M7946 FLOPPY (RXVll)

M7944 4K RAM (MSVll-B)

M7940 SLU (DLVll)

M7944 4K RAM (MSVll-B)

(j)

JUMPER/CABLE
TERMINATOR
OPTION
(BCVl B-XX)

M7944 4K RAM (MSVll-B)

@ M9400-YA DIAGNOSTIC/BOOT (REVll-A)
EXPANDER BOX
NOTE:

CIRCLED NUMBERS
THROUGH
INTERRUPT PRIORITY SEQUENCE.

@ REFER TO DMA AND
11-3720

One-User 28K System

CD
®
®

CPU (KDllF) + EIS/FIS (KEVll)
M7940 SLU (DLV11)

M7946 FLOPPY (RXV11)

M7940 SLU (DLV11)

M7940SLU (DLV11)

JUMPE R/CAB LE
TERMINATOR
OPTION
BCVl B-XX

ill
®
®

M7940SLU (DLV11)

(j)

M7944 4K RAM (MSVll-B)

M7944 4K RAM (MSV11-B)

M9400-YA DIAGNOSTIC/BOOT (REV11-A)

M79444K RAM (MSVll-B)

EXPANDER BOX
NOTE:

THROUGH
CIRCLED NUMBERS
INTERRUPT PRIORITY SEQUENCE.

@ REFER TO DMA AND
11- 3719

Four-User 28K System with EIS / FIS

PDP-11V03
PDP-11V03-F/H Module Utilization

(M7264-YA)

CD
0

CD
®
M7946 FLOPPY DISK CONTROLLER (RXV11) ® 3
+

KDll-R PROCESSOR

(M7955-YD)

® M7940 SERIAL LINE UNIT (DLVll)
SPARE
®
NOTE:

M9400-YA BOOT/TERMLINATOR (REV11-A) 0

CIRCLED NUMBERS (DTHROUGH
INTERRUPT PRIORITY SEQUENCE.

@ REFER TO DMA AND
MR·0840

Basic 16K System

CD
0
®

(M7264-YA)

KDll-R PROCESSOR

(M7955·YD)

M7955-YD 16K MEMORY (MSV11-CD)

~ / / / / / / / / / / / / /~ / / / / ;ij1M7946 FLOPPY DISK CONTROLLER (RXV11)0 4

)

BCV1 B-XX JUMPER/CABLE
TERMINATOR OPTION

(

v////////////////////.;:

M7940 SERIAL LINE UNIT (DLV11)

@ M9400-YA BOOT/TERMINATOR (REV11-A)
SPARE
@
SPARE
@

M7940 SERIAL LINE UNIT (DLV11)

NOTE:

SPARE
SPARE

@
@
@
@ 4

CIRCLED NUMBERS
THROUGH
REFER TO DMA
AND INTERRUPT PRIORITY SEQUENCE.

Two-User 28K System

MA-591B

PDP-11T03
PDP-11T03
The PDP-11T03 comprises a PDP-11 /03 computer, two RK05 disk drives,
and an LA36 DECwriter II. The basic system includes 16K of memory. The
system may be ordered without the LA36. A" models are configured to boot
on power-up and halt on BREAK. The figures and tables that follow describe
the models, specifications, and components.

SYSTEM CONTROL SWITCHES
RK05J DISK DRIVE
(REMOVABLE DISK CARTRIDGES)

RK05F
DISK DRIVE
(FIXED DISK)

B61 POWER
CONTROLLER

LA36
DECwriter"
TERMINAL

PDP-11T03

AC LINE SWITCH
AND FUSE

TERMINAL CONNECTOR

MR-0140

PDP-11T03
System Component Model Designations
PDP-11 T03 System Model Designation
System
Requirements

Input Power
(V)

115

230

115

230

115

230

115

230

Frequency
(Hz)

PDP-11/03
Computer

LA36

RKV11-D

RK05

Specifications
LA36

CPU CABINET
PLUG

POWER
CONNECTORS
115V
50/60 HZ

RECEPTACLE

@o o@
NEMA # L5.3OP
DEC # 12·11193

L5·30R
12·11194

@o o@

y
230 V
50/60 HZ

IJ y

NEMA # L6-2OP
DEC # 12·11192

L620R
1211191

PLUG

RECEPTACLE

wll
©

@Uw

NEMA #5·15P
DEC #90-08938

5-15R
12·05351

Cd
--

c:::::Jt::::I

NEMA # 6-15P
DEC # 90-08853

6-15R
12·11204

WATTS

860

300

BTU/HOUR

2940

1020

WEIGHT

294.8 KG

46.4

(850 LBSt

(102 LBst

MR·0764

PDP-11T03
Modules Included in the Basic System
Processor
KD11-S (M7264-YA)
No resident memory
KEV 11 EIS / FIS option included
CPU refresh disabled
Powers up to 173000

Memory
MSV11-CD (M7955-YD)
16K RAM
Internal refresh
Addresses start at bank 0
The memory is part of the KD 11-R processor option

Serial Line Interface
DL V 11 (M7940)
Device address 177560
Vector 60
300 baud
20 rnA active transmitter and active receiver
One stop bit, eight data bits, no parity
Framing error (BREAK) asserts BHAL T

Disk Drive Interface
RKV 11-D (M7269 plus box)
First device address (drive 0/ 1) 177170
First vector 264
Second device address (drive 2) 177150
Second vector 270

PDP-11T03
Bootstrap I Diagnostic ITerminator
REV11-A (M9400-YA)
Bootstrap enabled
Diagnostics enabled
Refresh disabled
120 Q terminator
Module Utilization

D
M7264-YA CPU (KD11-R)
AND ARITHMETIC OPTION (KEV11)

KD11-S
PROCESSOR

M7955-YD 16K MEMORY (MSV11-CD)

M7940SERIAL LINE UNIT (DLV11)

M7269 BUS INTERFACE

SPARE

M9400-YA BOOT/TERMINATOR (REV11-A)

NOTE: CIRCLED NUMBERS
THROUGH
INTERRUPT PRIORITY SEQUENCE·

® REFER TO DMA AND

Basic 16K System
M9400-YE
A

M7940 SERIAL LINE UNIT (DLV11)
M9400-YA BOOT/TERMINATOR

M7940 SERIAL LINE UNIT (DLV11)

(REV11-A)

SPARE

SPARE
M9401

THROUGH
NOTE: CIRCLED NUMBERS
INTERRUPT PRIORITY SEQUENCE.

@ REFER TO DMA AND

Two-User Expanded 28K System
35

@
@
@
@

2
3
4

PDP-11T03-L

PDP-11T03-L AND PDP-11V03-L SYSTEMS

PDP-11 T03-L
The PDP-11T03-L is a general purpose computer system that can be used
for developing and executing programs in a variety of applications. RT-11
software provides a single user foreground and background system; it can
support a real time application job execution in the foreground and an interactive or batch program development job in the background. RT-11 is also
available for a single job configuration.
The PDP-11 T03-L system consists of the following equipment.
PDP-11 /03-LC (115 Vac) or PDP-11 /03-LD (230 Vac) minicomputer with:
KD 1 '1-H microcomputer plus 16K words (32K bytes) of MOS memory
(MSV11-CD)
BA 11-NC (-ND) box with an H9273 backplane and an H786 power supply
BDV11-AA bootstrap/diagnostic/terminator and ROM option.
MSV 11-CD configured as an additional 12K words (24K bytes) of MOS
memory
KEV 11 Extended Instruction Set / Floating Point Instruction Set (EIS / FIS)
RLV11 disk controller
RLO 1 five-megabyte dual disk drive units and cartridges
DL V 11-F serial line unit
H9612-AC cabinet
Power controller
871-A
871-B
871-C

110 V
220V
110 V

12 A
8A
16 A

50/60 Hz
50/60 Hz
50/60 Hz
37

PDP-11T03-L
In addition to the preceding items, one RT -11 system software kit and one
RLOP + diagnostic kit are shipped with the system.
The following optional terminals are available for the system.
LA36 OECwriter
VT52 OECscope (with or without copier)
VT100 Alphanumeric Video Terminal
PDP-11T03-L Operator Switch Panel
Communication between the user and the processor is provided by switches on the front panel of the POP-11 /03-L or by the terminal connected to
the system. The operator switch panel contains three switches: AUX
ON/OFF, HALT, and RESTART. The functions and positions of the switches
are as follows.
Switch

Position

Function

AUX ON / OFF

OFF

As configured at the factory, this switch,
when turned off, removes ac power to the
system.

As configured at the factory, it turns on
ac power. If the automatic bootstrap is
selected and the HALT switch is up, the
system boots.

Up (Enable)

This enables the processor to run.

Down (HALT)

This halts the processor, which responds
to console OOT commands. Refer to the
Microcomputer Processor Handbook, EB18451-20, for OOT instructions.

RESTART
(Momentary
Switch)

When this switch is activated, the processor carries out a power-up sequence.
As shipped, the system presents the
bootstrap dialog as:

HALT

RESTART

28
START?
The HALT switch must be up (enable).

PDP-11T03-L
The switch panel also contains two indicators that provide the following information.
LED

Condition

Indication

PWR OK

This LED lights when the proper dc output voltages are being generated by the
H786 power supply.

RUN

This LED lights when the processor is in
the run state. It goes out when the processor is not executing instructions.

----.:::~~c:::-CARTRIDGE ACCESS DOOR

_-+-11-- RLOI DISK DRIVE

11/03-L
MICROCOMPUTER

--+-1t-- RLOI DISK DRIVE

STABI LlZE R FOOT

PDP-11 T03-L Computer System

PDP-11T03-L

CIRCUIT
BREAKER
FROM DLVll
FROM DRIVE 0
BOTTOM
DRIVE 0
PWR CORD

BC06R FROM RLVll
FROM PWR
CONTROL (Jl)
TO DRIVE 0 TOP
TOP
BOTTOM
(TERMINATOR)
DRIVE 1
PWR CORD

C-:7'7----~f.i!...-LCI RCUIT
BREAKER
EXPANDER BOX
(IF REQUIRED)
TO J2 ON 11/03-L
FRONT PANEL

MONITOR
LAMP

FROM RLOl
DRIVE 1

AC CI RCU I T -+--tH--::=!I~loH1
BREAKER

PDP-11T03-L (Rear Panel Removed)

PDP-11T03-L
LED
INDICATORS

SPARE

PWR OK RUN

RESTART

CONTROL
SWITCHES

HALT

AUX OFF

Front Panel Switches and Indicators

RL01 Disk Drives
The RLO 1 disk drive is a random access mass storage device with a removable, top-loading disk cartridge. Access to the disk is provided by a lift-up
cover. The RL01 has four indicators on its front panel. Their functions are
as follows.
Indicator

Function

LOAD
(Push Button)

Lights to indicate that the spindle has stopped and a
cartridge may be loaded.

UNIT SELECT
(READY)

Lights to indicate that drive 0 or 1 is ready to read,
write, or receive controller commands.

FAULT

Lights to indicate that a drive error condition exists.

WRITE PROT
(Push Button)

Lights to indicate that the cartridge currently
mounted is protected from having data written on it.

PDP-11V03-L

LOAD

UNIT SE[.ECT
(READY)

MR·1860

RL01 Disk Drive (Front View)

PDP-11V03-L
The PDP-11 V03-L includes a PDP-11 /03-L computer and an RX02 dual
floppy disk system. The system also has 64K bytes or 32K words of RAM
memory. Earlier systems have 32K bytes or 16K words of RAM memory that
is expandable to 32K words. The system has the following optional terminals.
LA36 DECwriter
VT52 DECscope
VT 100 DECscope
The figures and tables that follow describe the models, specifications, and
components.

PDP-11V03-L

lolGITAL IIV03-L

Idigital PDP III03-q

[(~ ©J©J~) ))
Idigital RX021

ill
PDP-11 V03-L System

PDP-11V03-L

POWER
SUPPLY

BA11-N BACKPLANE
AND MODULES

---+--++-i-PDP 11/03-L

....--+-+--+-t-R X02

_-++-+--+~::~~SION
OF REQUIRED)

POWER CORD

PDP-11 V03-L System (Backpanel Removed)

PDP-11V03-L

LOCAL POWER

POWER CONTROLLER
RECEPTACLE

PLUG
871·A

871·A
115V 15A
5O/60HZ

@
o

©••

NEMA#5·15P
DEC # 90·08938

5·20R
12·12265

871-B

871·B
230V 10A
50/60HZ

8--

Cd
c:::I c:::I

NEMA#6·15P
DEC # 90·08853

6·15R
12·11204·01

871-C

871·C
115V 20A
50/60HZ

@
o
I?

NEMA#5·20R
12·12265
MA·24011

Power Connectors

PDP-11V03-L
16K System Components
System
Requirements

Models
LC

Input Power (V)

115

230

Frequency (Hz)

POP-11 /03-L Computer -LC

-LC

-LO

RX02 Floppy Disk

-BA

-BC

-BO

Power Controller

871-A

871-B

32K System Components
System
Requirements

Models
LH

Input Power (V)

115

230

Frequency (Hz)

POP-11 /03-L Computer -LK

-LK

-LL

RX02 FloppyDisk

-BA

-BC

-BO

Power Controller

871-A

871-B

11V03-L System (LE, LH, and LJ)
The POP-11 V03-L system consists of the following equipment.
A POP-11 /03LK-LL microcomputer consisting of:
K011-HA (M7270)

a microcomputer board

MSV 11-00 (M80440)

a 32K word RAM

BA 11-N

a mounting box with an H9273 backplane
and an H786 power supply

BOV11-A

a bootstrap / diagnostic / terminator with
expandable ROM space for the user
(M8012-YA).
46

PDP-11V03-L
KEV11

A chip, mounted on the KD 11-H microcomputer, that provides the system with the Extended Instruction Set (EIS)
and Floating Point Instruction Set (FIS) features.

RXV21

The RX02 floppy disk controller module (M8029) interfaces the RX02 disk to the LSI-11 bus.

DLV11-J

The asynchronous four-channel line interface module
(M8043) interfaces the terminal to the LSI-11 bus.

RX02

The dual floppy disk system.

H9610

The cabinet in which the hardware is mounted.

871

The primary power controller for the 11 V03-L system.

Floppy Disks

The operational and diagnostic software programs are
stored on floppy disks and are shipped as part of the system.

11V03-L Early Systems (LA, LC, and LD)
The PDP-11 V03-L system consists of the following equipment.
A PDP-11 /03LC-LD microcomputer consisting of:
KD11-R

a KD11-H (M7264-YC) microcomputer
board and a MSV 11-CD (M7955) 16K MOS
memory board

SA 11-N

a mounting box with an H9273 backplane
and an H786 power supply

SDV11-A

a bootstrap/diagnostic/terminator with
expandable ROM space for the user
(M8012-YA).

KEV 11

A chip mounted on the KD 11-H microcomputer that provides the system with the Extended Instruction Set (EIS) and
Floating Point Instruction Set (FIS) features.

RXV21

The RX02 floppy disk controller module (M8029) interfaces the RX02 disk to the LSI-11 bus.

DL V 11-F

The asynchronous line interface module (M8028) interfaces the terminal to the LSI-11 bus.

RX02

The dual floppy disk system.
47

PDP-11V03-L
H9610

The cabinet in which the hardware is mounted.

871

The primary power controller for the 11 V03-L system.

Floppy Disks

The operational and diagnostic software programs are
stored on floppy disks and are shipped as part of the system.

C/O BUS (FOR
INTERCONNECTING)

Q-BUS
A

KDll-R
{
MICRO
COMPUTER

KDll-H(M7264-YC)

(3)

MSVll-CD (M7955)

RXV21 (M8029)

DLVll-F (M80281

CD
®
®

BDVll-AA (M8012-YA)

NOTE: CIRCLED NUMBERS CDTHROUGH
REFER TO THE DMA PRIORITY
SEQUENCE AND THE PHYSICAL INTERRUPT PRIORITY ON EACH OF THE
INDIVIDUAL INTERRUPT LEVELS.
MR-2022

PDP-11 V03-LA, -LC, and -LD Configuration

PDP-11V03-L

Q-BUS

C/D BUS
(FOR INTERCONNECTING)

M7270 CPU (KDll-HA)
AND OPTION (KEVll)

EMPTY

M8044D 32K MEMORY
(MSVll-DD)

EMPTY

® M8029 RX021NTERFACE (RXV21)

EMPTY

0M8043 SERIAL LINE UNIT (DLV11-J)

EMPTY

OPTION 5

EMPTY

OPTION 6

EMPTY

(2)

OPTION 7

EMPTY

OPTION 8

EMPTY

M8012-YA BOOTSTRAP/DIAGNOSTIC/TERMINATOR (BDVll-AA)

NOTE: CIRCLED NUMBERS (DTHROUGH
REFER TO THE DMA PRIORITY
SEQUENCE AND THE PHYSICAL INTERRUPT PRIORITY ON EACH OF THE
INDIVIDUAL LEVELS.
MR-2407

PDP-11 V03-LE, -LH, and -LJ Backplane Configuration

PDP-11 V03-L
Q-BUS

C/D BUS
(FOR INTERCONNECTING)

(1)

KD 11-HA (M7270)

EMPTY

®
®
0

MSV11-DD (MB044D)

EMPTY

RXV21 (MB029)

EMPTY

DLV11-J (MB043)

EMPTY

®
®
CD
®
M9400-YE

OPTION 5
OPTION 6
OPTION 7
OPTION 8

LLLLLLLL

LLLA

L..::

EMPTY

~ BCV1 B-XX JUMPER/CABLE

BC05L-XX

TERMINATOR OPTION

M9401 --...V

EMPTY

OPTION 11

@
@

OPTION 12

@
@

OPTION 14
OPTION 15

OPTION 16

@
@

OPTION 17

OPTION 13

BDV11-AA DIAGNOSTIC/BOOTSTRAP/TERMINATOR

THROUGH
REFER TO THE DMA PRIORITY
NOTE: CIRCLED NUMBERS
SEQUENCE AND THE PHYSICAL INTERRUPT PRIORITY ON EACH OF THE
INDIVIDUAL INTERRUPT LEVELS.
MR-2408

PDP-11 V03-LE, -LH, and -LJ System Expansion

PDP-11V23

PDP-11V23 AND PDP-11T23 SYSTEMS

PDP-11V23 SYSTEM
The PDP-11 V23 is a general purpose computer system that can be used for
developing and executing programs for a variety of applications.
Optional hardware and software is available for applications such as highlevel language program development support, foreground / background real
time support, multiprogramming, and the ability to monitor and control
equipment.
The PDP-11 V23 can support a real time application job execution in the
foreground and an interactive or batch program development in the background. RT-11 is also available for a single job configuration. The PDP11 V23 system contains the following equipment.
A PDP-11 /23 minicomputer with:
KDF 11-AA microprocessor module (M8186) contained on a doubleheight module
MSV 11-DD (M8044D) two double-height modules with 128K bytes of
MOS RAM (on two modules) expandable to 256K bytes (four modules)
BA 11-N mounting box with an H9273 backplane, an H786 power supply, and H403-A ac input box and a front bezel panel (54-12985)
BDV 11-AA bootstrap / diagnostic / terminator with
ROM option (M80 12-VA).

expandable user

DL V 11-J

Asynchronous four-channel serial line interface unit (M8043).
(Must be CS revision "E" or higher.)

RXV21

The RX02 floppy disk controller module (M8029) interfaces the
RX02 to the LSI-11 bus. (Must be at CS revision "E 1" or higher.)

RX02

The dual drive floppy disk system.

H9610

Free-standing 76.8 cm (30 in) high cabinet.
51

PDP-11V23
Power controller
871-A •
871-8
871-C·

120Vac 12A
230 Vac
8A
120 Vac 20 A

50/60 Hz (early 120 Vac systems)
50/60 Hz
50/60 Hz (later 120 Vac systems)

In addition to the preceding configuration, the following items are shipped
with the PDP-11 V23 system.
RT -11 system software package
DYDP + diagnostic kit
Floppy disk set. Disks contain the RT -11 operating system software
and DYDP diagnostic programs.
Option terminals available for the system configuration include the following.
LA38 DECwriter IV
LA 120 DECwriter III
VT100 Alphanumeric Video Terminal

PDP-11 V23 Operator Switch Panel
Three control switches on the front of the PDP-11 123 provide a communication link between the operator and the microcomputer system.
The switches labeled AUX ONIOFF, HALT, and RESTART provide power,
stop, and bootstrap control for the PDP-11 123. The switch functions are
defined as follows.
Switch

Position

Function

AUX ON I OFF

OFF

In the normal factory configuration, turning this switch off removes ac power from
the system.

In the normal factory configuration, turning this switch on applies ac power to the
system. If the HALT switch is up, the system is automatically booted.

• Systems built before April 1980 use 871-A power controllers. Systems
built after April 1980 use 871-C power controllers.

PDP-11V23
HALT

RESTART

Up (Enable)

This switch enables the processor to run.

Down (HALT)

The HALT switch, when down, halts the
processor, which responds to console
OOT commands. Refer to the Microcomputer Processor Handbook, EB18451-20, for OOT instructions.

RESTART
(Momentary
Switch)

When this switch is activated, and when
the HALT switch is up, the processor carries out a power-up sequence and displays the bootstrap dialog as:
28*
START?

HMHH3.tJ

• The BOV 11 software automatically sizes the available memory in the system and prints the number 28. The 28 is the present limit for the BOV 11
ROM software. The actual available memory maximum is 124K words. The
user should be aware of the actual memory and not depend on the printout. The memory-sizing software will be updated and eventually print out
the actual memory size up to the addressing limit of the CPU.
53

PDP-11V23

BAll-N
BOX

KDFll-AA (M8186)

EMPTY

MSVll-DD (M8044D)

EMPTY

MSVll-DD (M8044D)

EMPTY

RXV21 (M8029) •

EMPTY

DLVll-J (M8043)**

M9400-YE

-a

OPTION
///L//L/LJ///LL~

EMPTY

i4--- BCVl B-XX JUMPER/CABLE

BC05L-XX

TERMINATOR OPTION
M9401 _17/

11
BAll-N
EXPANSION BOX

OPTION

OPTION
OPTION

17
M9400-YD

/////////////~

BA11-M
BOX

'NOTE:
•• NOTE:

j4-BCV1A-XX JUMPER/CABLE
TERMINATOR OPTION

BC05L-XX

M9401

EMPTY

OPTION

//////

1(22

103

BDV11-AA (M8012-YA)

MUST BE AT CS REVISION 'El' OR HIGHER
MUST BE AT CS REVISION 'E' OR HIGHER

NOTE: CIRCLED NUMBERS G)THROUGH
REFER TO THE DMA PRIORITY
SEQUENCE AND THE PHYSICAL INTERRUPT PRIORITY ON EACH OF THE
INDIVIDUAL INTERRUPT LEVELS

PDP-11 V23 System Expansion Example

PDP-11V23
The PDP-11 /23 front switch panel also contains two indicators that provide
the following information.

LED

Function

PWR OK

Illuminated when the proper dc output voltages are being generated by the microcomputer system.

RUN

Illuminated when the processor is operating; turned off when
the processor is not executing instructions.

The following is an expanded PDP-11 V23 configuration example using both
the BA 11-N and BA 11-M boxes.

LED
INDICATORS

SPARE

RESTART

PWR OK RUN

CONTROL
SWITCHES

HALT

ON
AUX OFF

MR 4891

Front Panel Switches and Indicators

PDP-11V23

POWER
SUPPLY

BA11-N BACKPLANE
AND MODULES

-----t---+l-t-PDP 11/23

----+-r-+~~RX02

EXPANSION

--++--t--t- SPACE
(I F REQUI RED)

POWER CORD

PDP-11 V23 with Backpanel Removed

PDP-11V23

CIRCUIT
BREAKER

REMOTE POWER
SWITCH

A.C. POWER
MONITOR

~----POWERCORD

Power Controller (Rear View)

"
115 VAC/230 VAC
SWITCH

POWER
CONNECTOR

FUSE

PDP-11 /23 Microcomputer (Rear View)

REMOTE POWER
CONNECTORS

PDP-11V23

C/D BUS
(FOR INTERCONNECTING)

Q-BUS
A

KDFll-AA (M8l86)

(3)

MSVll-DD (M8044D)

0
®

RXV2l (M8029) *

DLV11-J (M8043) **

1------

®
®

8
BDVll-AA (M8012-YA)

*NOTE:

MUST BE AT CS REVISION 'El' OR HIGHER

**NOTE:

MUST BE AT CS REVISION 'E' OR HIGHER

NOTE: CIRCLED NUMBERS G)THROUGH
REFER TO THE DMA PRIORITY
SEQUENCE AND THE PHYSICAL INTERRUPT PRIORITY ON EACH OF THE
INDIVIDUAL INTERRUPT LEVELS.
MR4873

PDP-11 V23 Module Configuration

PDP-11V23

BAll-N
BOX

KDFll-AA (M8186)

MSVll-DD (M8044D)

RXV21 (M8029) *

DRVll-J (M8049)

DLVll-J (M8043) **

1(8

M9400-YD --.~////////////////~
:.-- BCV1A-XX JUMPER CABLE
TERMINATOR OPTION

BC05L-XX

M9401
BAll-M
BOX

--+~/////////////// ~

---

(12

(15

16)

BDVll-AA (M8012-YA)

*NOTE:

MUST BE AT CS REVISION 'E l' OR HIGHER

**NOTE:

MUST BE AT CS REVISION 'E' OR HIGHER

NOTE: CIRCLED NUMBERS
THROUGH
REFER TO THE DMA PRIORITY
SEQUENCE AND THE PHYSICAL INTERRUPT PRIORITY ON EACH OF THE
INDIVIDUAL INTERRUPT LEVELS.
MR-4875

PDP-11 V23 Expansion Example

PDP-11V23
POWER CONTROLLER

LOCAL POWER

RECEPTACLE

PLUG

87l-A
l15V l5A
50/60HZ

,,
©

87l-A

@
o [>

NEMA # 5-l5P
DEC # 90-08938

5-20R
12-12265

871-B

871-B
230V lOA
50/60HZ

==
~

NEMA # 6-l5P
DEC # 90-08853

6-15R
12-11204-01

871-C

871-C
115V 20A
50/60HZ

-,
©

HUBBELL # 5366-C
DEC # 12-15183

@
o [?

NEMA # 5-20R
12-12265
MR-2405

System Requirements

Model
AC

Input Power (V)
Frequency
Current
PDP-11 V23 Computer
RX02 Floppy Disk
Power Controller

120
60
12
AA
BA
871-A •
or
871-C

120
50
12
AA
BC
871-A •
or
871-C

AD
240
50
8
AB
BD
871-B

• Systems built before April 1980 use 871-A power controllers. Systems after April 1980 use 871-C power controllers.
60

PDP-11T23
PDP-11T23 SYSTEM
The PDP-11 T23 is a general purpose computer system that can be used for
developing and executing programs for a variety of applications.
Optional hardware and software are available for applications such as highlevel language program development, foreground Ibackground real time
support, multiprogramming, and equipment monitoring and control capability.
PDP-11 T23 can support a single user with a foreground I background system. It can support a real time application job execution in the foreground
and an interactive or batch program development in the background. RT -11
is also available for a single job configuration.
The PDP-11T23 system contains the following equipment.
A PDP-11 123 minicomputer with:
KDF 11-AA microprocessor module (M8186) contained on a doubleheight module
MSV 11-DD (M8044D) two double-height modules with 128K bytes of
MOS RAM (on two modules) expandable to 256K bytes (four modules)
BA 11-N mounting box with an H9273 backplane, an H786 power supply, and H403-A ac input box and a front bezel panel
BDV 11-AA bootstrap I diagnostic I terminator with
ROM option (M80 12-Y A).

expandable user

DL V 11-J

Asynchronous four-channel serial line interface unit (M8043).
(Must be at CS revision "E" or higher.)

RLO 1

Five-megabyte dual disk drive units and cartridges

H9612

105 cm (42 in) high cabinet

Power controller
871-A •
871-B
871-C·

120 Vac
230 Vac
120 Vac

12 A
8A
16 A

50/60 Hz
50/60 Hz
50/60 Hz

In addition to the preceding configuration, the following items are shipped
with the system.
1 RT -11 or RSX -11 M system software kit
1 DLDP + diagnostic kit
• Systems built before April 1980 use 871-A power controllers. Systems
built after April 1980 use 871-C power controllers.
61

PDP-11T23
Optional terminals available for the system include the following.
LA38 DECwriter IV
LA 120 DECwriter III
VT100 Alphanumeric Video Terminal

PDP-11 T23 Operator Switch Panel
Three control switches on the front of the PDP-11 T23 provide a communication link between the operator and the microcomputer system.
The switches labeled AUX ON/OFF, HALT, and RESTART provide power,
stop, and bootstrap control, respectively. The switch functions are defined
as follows.

Switch

Position

Function

AUX ON / OFF

OFF

In the normal factory configuration, this
removes ac power from the system.

In the normal factory configuration, this
applies ac power to the system. If the
HALT switch is up, the system is automatically booted.

Up (Enable)

This enables the processor to run.

Down (HALT)

This halts the processor, which will respond to console odt commands. Refer
to the Microcomputer Processor Handbook, EB-18451-20, for ODT instructions.

RESTART
(Momentary
Switch)

When this switch is activated, and when
the HALT switch is up, the processor carries out a power-up sequence and displays the bootstrap dialog as:

HALT

RESTART

28*
START?

*The BDV11 software automatically sizes the available memory in the system and prints the number 28. The 28 is the present limit for the software.
The actual available memory maximum is 124K words. The user should be
aware of the actual memory and not depend on the printout. The memorysizing software will be updated and eventually print out the actual memory
size up to the addressing limit of the CPU.

PDP-11T23

Ilooooij

I
II digital 11T23 11

1 digital PDP 11/231

II (c:) ~~g ) II

.[1000011

I
0

-----

----

PDP-11 T23 Computer System

PDP-11T23
LED
INDICATORS

SPARE

PWR OK RUN

RESTART

CONTROL
SWITCHES

HALT

AUX OFF

MR-4B91

Front Panel Switches and Indicators

The PDP-11 T23 front switch panel also contains two indicators that provide
the following information.

LED

Function

PWR OK

Illuminated when the proper dc output voltages are being generated by the microcomputer system.

RUN

Illuminated when the processor is operating; turned off when
the processor is not executing instructions.

RLO 1 Disk Drives
The RLO 1 disk drive is a random access mass storage device with a removable, top-loading disk cartridge. Access to the disk is provided by a lift-up
cover. The RL01 has four indicators on its front panel. Their functions are
as follows.

Indicator

Function

LOAD
(Push Button)

Lights to indicate that the spindle has stopped and a cartridge may be loaded.

UNIT SELECT
(READY)

Lights to indicate that drive 0 or 1 is ready to read, write,
or receive controller commands.

PDP-11T23
FAULT

Lights to indicate that a drive error condition exists.

WRITE PROT
(Push Button)

Lights to indicate that the cartridge currently mounted is
protected from having data written on it.

The following is an example of the PDP-11 T23 microcomputer with an expanded configuration using both the BA 11-N and BA 11-M boxes.

System Requiremp-nts

Input Power (V)
Frequency
Current
PDP-11 T23 Computer
RL01 Disk
Power Controller

120
50/60
12 A
AA
AK
871-A •
or
871-C

Models
AB

240
50/60
8A
AB
AK
871-B

120
50/60
16 A
AA
AK
871-COO

.. Systems built before April 1980 use 871-A power controllers. Systems
built after April 1980 use 871-C power controllers.

LOAD

UNIT SELECT
(READY)

FAULT

RLO 1 Disk Drive (Front View)

PDP-11T23

FROM DLV11-J
FROM DRIVE 0
BOTTOM
DRIVE 0
PWR CORD

BC06R FROM RLV11
FROM PWR
CONTROL (J1)
TO DRIVE 0 TOP

11/23
PWR CORD

TOP
BOTTOM
(TERMINATOR)
DRIVE 1
PWR CORD

~-~::7-------k..iJ--.JLCI RCUIT
BREAKER
EXPANSION BOX
(IF REQUIRED)

TO J2 ON 11/23
FRONT PANEL

MONITOR
LAMP

FROM RL01
DRIVE 1

AC CIRCUIT~-+I-t-"..~~
BREAKER

PDP-11T23 (Rear Panel Removed)

PDP-11T23
115 VAC/230 VAC
SWITCH

POWER
CONNECTOR

CIRCUIT
BREAKER

PDP-11 /23 Microcomputer (Rear View)

C/D BUS
(FOR INTERCONNECTING)

Q-BUS

CD KDFll-AA (M8186)
@

MSVll-DD (M8044D)

CD MSVll-DD (M8044D)
RLVll (M8013) DISK CONTROL
0

®
CD

3
4

RLVll (M8014) BUS CONTROL

DLV11-J (M8043) *

CD
®
@
*NOTE:

8
9

BDVll-~A (M8012-YA)

MUST BE AT CS REVISION 'E' OR HIGHER

NOTE: CI RCLED NUMBERS (i) THROUGH (g)'REFER TO THE DMA
PRIORITY SEQUENCE AND TH'E"'PHYSICAL IN'fERRUPT PRIORITY
ON EACH OF THE INDIVIDUAL INTERRUPT LEVELS.
MR-4877

Typical PDP-11 T23 Module Configuration

PDP-11T23

CD
<V
@
@

BA11-N
BOX

C
EMPTY

MSV11-DD (MB044D)

EMPTY

MSV11-DD (MB044D)

EMPTY

DLV11-J (MB043)'

EMPTY

B
9

OPTION

M9400-YE _~LL/L L

/1//////

r--

BC05L-XX

BCV-XX JUMPER/CABLE
TERMINATOR OPTION

OPTION
-~ ~///////////// ~
@
OPTIONS
@

-@
14

OPTIONS

M9400-YD _ r - - -

@ OPTION

---

BC05L-XX

-BCV1A-XX

M9401 _ r - - "

@=
@-

3
4

JUMPE R/CAB LE
TERMINATOR OPTI ON
EMPTY

@
@)

BA11-N
BOX

RLV11 (MB014) BUS CONTROL

(i)

M9401

RLV11 (MB013) DISK CONTROL

®
®

BA11-M
BOX

KDF11-AA (MB1B6)

OPTION

-®
@
®--

=-®

OPTION

BDV11-AA (MB012-YA)

"NOTE: MUST BE AT CS REVISION 'E' OR HIGHER

NOTE: CI RCLED NUMBERS
THROUGH
REFER TO THE DMA
PRIORITY SEQUENCE AND THE PHYSICAL INTERRUPT PRIORITY
ON EACH OF THE INDIVIDUAL INTERRUPT LEVELS.

PDP-11 T23 Module Expansion Example

0322

COMMERCIAL SYSTEMS

0322
The standard Datasystem 322 includes the following.
•

Desk-like cabinet

•

Central processor with 32K bytes of MOS memory

•

One RXO 1 dual floppy disk unit with 512K bytes of data storage

•

VT52 video/keyboard transaction terminal

Options include:
•

Additional memory up to a total of 56K bytes

•

Additional dual floppy disk unit in the same cabinet

•

Choice of printers (30 cps up to 300 Ipm)

•

Cartridge disk drives (2.5 million bytes removable; 5.0 fixed)

•

Up to three video or hard-copy terminals

•

2780 communications package and CTS-300 DICAM, providing both
batch and interactive communication capabilities.

Further information may be found in the DEC Datasystem 320 Family Service Manual, EK-DDS03-SV.

0322

VT52

(OPTIONAL RX01)

Basic 322 System

0322

MR-0781

Optional Cabinet and Printer

0322

Basic 0322 System, Rear View with Door Removed

0322 System Model Designations
Model Designation
D322AInput Power / Frequency
Software Category
0322H9820RXV11PDP-11/03VT52LAV11- •
DS3RKH967RKV11-

AA
115/60
A
A
W
DA
JA
AE
PA
AA
HK
DA

·Model AA + LAV11 = Model BA
Model AD + LAV 11 = Model BD
Model AY + LAV11 = Model BY
Model AZ + LA V 11 = Model BZ
72

AD
230/50
A
B
W
DO
JB
AF
PO
AD
HL
DB

AY
115/60
C

AZ
230/50
C

same
as
AA
column

same
as
AD
column

0322
0322 SPECIFICATIONS· SEE 0324 SPECS FOR PRINTER SPECS
BASIC 322
116V 60HZ

POWER
CONNECTOR

230V 50 HZ

OPTIONAL CABINET
115V 60HZ

230V 50HZ

G.
G. 16©
G.
G.
15©
--WI I

16~

WI I

16~

NEMANO.
DEC PIN

5-15P
90·08938

6-15P
90-08853

6·15P
90'()8938

6·15P
90'()8853

AMPERAGE

12 AMPS

6 AMPS

12 AMPS

6 AMPS

BTU/HOUR

3400

1400

HEAT DISSIPATION

1000W

400W

SHIPPING WEIGHT
(APPROXIMATEI

400 LBS
182 KG

300 LBS
136 KG

300 LBS
136KG

·SPECIFICATIONS HAVE BEEN FIGURED ON THE MAXIMUM CONTAINED IN EACH UNIT.
MR-0782

Modules Included In the Basic System
Processor
KD 11-P (M7264-BB)
Resident memory addressed as bank 0
CPU refresh disabled
Powers up to 173000

Or
KD11-Q (M7264-YB)
No resident memory
CPU refresh disabled
Powers up to 173000

Memory
MSV 11-B (M7944)
4K RAM
Three in basic system with KD 11-P
Addresses start at bank 1
Refreshed by REV 11-C

Or
73

0322
MSV 11-C (M7955-YO)
16K RAM
One in basic system with KD 11-0
Addresses start at bank 0
Internal refresh

Serial Line Interface
DL V 11 (M7940)
Device address 177560
Vector 60
9600 baud
EIA
One stop bit, eight data bits, no parity

RX01 Floppy Disk Interface
RXV 11 (M7946)
First device address (disk 0) 177170
First vector 264
Second device address (disk 1) 177150
Second vector 270

Bootstrap / Diagnostic
REV 11-C (M9400-YC)
Bootstrap enabled
Diagnostics enabled
Refresh enabled for MSV 11-B
Refresh disabled for MSV 11-C

Terminator
lEV 11 (M9400-YB)
120 n terminator
74

0322
Optional Modules for Recommended Expansion
LA 180 Printer Interface
LA V 11 (M7949)
Device address 177510
Vector 200
Or
LPV 11 (M8027)
Device address 177510
Vector 200
RK05 Disk Interface
RKV11-D
Interfaced to computer by M7269
See the "CPU / Options" section for more detailed information.
Communications Interface
DUV11 (M7951)
Device address 160010
Vector 440
DL V 11 (M7940)
Device address:
console 177560
second terminal 176500
Vector:
console 60
second terminal 300

D322

KD11-P (M7264-BB)
CPU
BACKPLANE

MSV11-B (M7944)

REV11-C (M9400-YC)

FRAME 1

MSV11-B (M7944)

DLV11 (M7940)

(M9400-YE)

MSV11-B (M7944)

~v,.-xx

........

{

BC05L-XX

....RXV11 (M7946)

(M9401)
EXPANSION
BACKPLANE
FRAME 2

~V'A-XX

BCV1A-02 (M94CJO.YD)

BC05L-XX

{

(M9401)
EXPANSION
BACKPLANE
FRAME 3

TEV11 (M9400-VB)

-MR-0783

-IN MOST CASES M9400 MODULES ARE PLACED IMMEDIATELY
FOLLOWING THE LAST MODULE IN THE SYSTEM. THE TEV11,
HOWEVER, IS AN EXCEPTION TO THE GENERAL RULE. IN THE
BUSINESS PRODUCTS SYSTEMS IT IS PLACED IN THE LAST SLOT
OF THE LAST BACKPLANE IN ORDER TO MINIMIZE NOISE.

0322 Module Utilization Drawing for Basic System
Using PDP-11 /03-JA or - JB CPU Box

0322

C
KD11-P (M7264-BBI

CPU
BACKPLANE
FRAME 1

MSV11-B (M79441

REV11-C (M94OC)..VCI

MSV11-B (M79441

DLV11 (M79401

(M9400-YEI

MSV11-B (M79441

BC05L-XX

DCV'D-XX {

(M94011

RXV11 (M79461

EXPANSION
BACKPLANE

MSV11-B (M79441

LAV11 (M79491

FRAME 2

MSV11-B (M79441

(M9400-VD)

DLV11 (M79401

BCOSL-XX

RXV11 (M79461

(M94011
EXPANSION
BACKPLANE
FRAME 3

TEV11 (M9400-VBI

RKV11 (M7269)

MR-0784

0322 Module Utilization Drawing for Recommended
Expanded Systems Using PDP-11 /03-JA or -JB CPU Box

0322

KD11-Q IM7264-YBI
CPU
BACKPLANE
FRAME 1

MSV11-C IM7965-YDI

2
3

REV11-C IM9400-YCI

DLV11 IM79401

IM9400--YEI

RXV11 1M79481

---t
BC05L-XX

IM94011
EXPANSION
BACKPLANE
FRAME 2

~"-xx

IM9400-YDI

{

BC05L-XX

IM94011
EXPANSION
BACKPLANE
FRAME 3

TEV11 IM9400-YDI
MR-0786

0322 Module Utilization for Basic System
Using POP-11 /03-JC or -JO CPU Box

0322

KDll.Q (M7264-YB)
CPU
BACKPLANE
FRAME 1

MSVll-C (M7965-YD)

MSVll-C (M7965-YD)
(M9400-YE)

REVll-C (M9400-YC)

BC05L-XX

8CVI8-XX {

1""""'"'1

EXPANSION
BACKPLANE
FRAME 2

BCV1A-XX

(M9401)

DLV11 (M7940)

DLVll (M7940)

RXVll (M7946)

LAV11 (M7949)

(M9400-YD)

RXVll (M7946)

{

BC05L-XX

........

RKVll (M7269)

(M9401)
EXPANSION
BACKPLANE
FRAME 3

TEVll (M9400-YB)

MR-0786

0322 Module Utilization for Recommended
Expanded Systems Using POP- 11 /03-JC or -JO CPU Box

0324
0324
The standard Datasystem 324 includes the following.
•

Stylized cabinet and desk

•

Central processor with 32K bytes of MOS memory

•

One RK05J removable disk drive with a capacity of 2.4 million bytes of
data

•

One RK05F fixed disk drive with a capacity of 4.S million bytes of data

•

VT52 video / keyboard transaction terminal

Options include additional memory up to a total of 56K bytes.
Further information may be found in the DEC Datasystem 320 Family Service Manual, EK-DDS03-SV.

VT52

TABLE

CPU

Basic 324 System

0324

RK05J

o
DO

IIlrn'IOOOI
iI!jj/,IOODD
111111111111111111111111111111111111111111111111111111

Optional Cabinet and Printer

0324

0324 System Model Designations

Model Designation
D324AInput Power / Frequency
Software Category
0324H9602RKV11PDP-11/03H970VT52LAV11-RXV11-Model AA + LAV11
Model AD + LAV11
Model AY + LAV11
Model AZ + LAV11

AA
115/60

AD
230/50

A
A

A
B
CD
DB
JB
DA
AF
PO
DO

CC
DA
JA
DA
AE
PA
DA

AY
115/60
C

AZ
230/50
C

same
as
AA
column

same
as
AD
column

Model BA
Model BD
Model BY
Model BZ

D324 SPECIFICATIONS'
PRINTER LA180
115V
60HZ
15 A
POWER
CONNECTOR

NEMA NO.
DEC PIN

230V
50HZ
15A

RK05 CABINET
230V
50HZ

CPU CABINET
115V
60HZ

115V
60HZ
30AW

30AW

15·30 P
12-11193

230V
50HZ
20A X

VT52 DESK
115V
60HZ
15A

230V
50HZ
15A

II -II -- @G@ @@ ©~
©~
5·15 P
90-08938

6·15 P
90-08853

AMPERAGE

1.5A

24A

BTU/HOUR

1023

1400

66·20 P
12-11192

5·15 P
90-08938

6-15 P
90-08853

24A

.5 A

3400

400

HEAT DISSIPATION

300W

400W

loo0W

1000W

118W

SHIPPING WEIGHT
(APPROXIMATE)

120 LBS
55 KG

300 LBS
136 KG

400 LBS
182 KG

225 LBS
102 KG

• SPECIFICATIONS HAVE BEEN FIGURED ON THE MAXIMUM CONTAINED IN EACH UNIT.

MR·0790

0324
Modules Included in the Basic System
Processor
KD 11-P (M7264-BB)
Resident memory addressed as bank 0
CPU refresh disabled
Powers up to 173000
Or
KD11-Q (M7264-YB)
No resident memory
CPU refresh disabled
Powers up to 173000

Memory
MSV 11-B (M7944)
4K RAM
Three in basic system with KD 11-P
Addresses start at bank 1
Refreshed by REV 11-C
Or
MSV 11-C (M7955-YD)
16K RAM
One in basic system with KD 11-Q
Addresses start at bank 0
Internal refresh

Serial Line Interface
DL V 11 (M7940)
Device address 177560
Vector 60
9600 baud
EIA
One stop bit, eight data bits, no parity

0324
Disk Drive Interface
RKV11-D
Interfaced to computer by M7269
Device address 177400
Vector 220

Bootstrap / Diagnostic
REV11-C (M9400-YC)
Bootstrap enabled
Diagnostic enabled
Refresh enabled for MSV 11-B
Refresh disabled for MSV 11-C

Terminator
TEV 11 (M9400-VB)
120 n terminator

Optional Modules for Recommended Expansion
LA 180 Printer Interface
LAV 11 (M7949)
Device address 177510
Vector 200
Or
LPV 11 (M8027)
Device address 177510
Vector 200

0324
RX01 Floppy Disk Interface
RXV 11 (M7946)
First device address (disk 0) 177170
First vector 264
Second device address (disk 1) 177150
Second vector 270

Communications Interface
DUV11 (M7951)
Device address 160010
Vector 440
DL V 11 (M7940)
Device address:
console 177560
second terminal 176500
Vector:
console 60
second terminal 300

0324

KD11-P IM7264-8BI
CPU

MSVll-B IM79441

REV11-C IM9400-YCI

BACKPLANE
FRAME 1

MSV11-B IM79441

DLVll IM79401

IM9400-YEI

MSVll-B IM79441

OCV1B-XX {

EXPANSION
BACKPLANE
FRAME 2

IM94011

RKV111M72691

IM9400-YD)

BC05L-XX

OCV1A-XX {

EXPANSION
BACKPLANE
FRAME 3

BC05L-XX

IM9401)

TEV11 IM9400-YBI

-MR-0791

*IN MOST CASES M9400 MODULES ARE PLACED IMMEDIATELY
FOLLOWING THE LAST MODULE IN THE SYSTEM_ THE TEVll,
HOWEVER, IS AN EXCEPTION TO THE GENERAL RULE_ IN THE
BUSINESS PRODUCTS SYSTEMS IT IS PLACED IN THE LAST SLOT
OF THE LAST BACKPLANE IN ORDER TO MINIMIZE NOISE_

0324 Module Utilization Drawing for Basic System
Using PDP-11 /03-JA or - JB CPU Box

0324

KD11·P (M7264-BB)
CPU
BACKPLANE

MSV 11·B (M7944)

REV11-C (M940O-VC)

FRAME 1

MSV11·B (M7944)

DLV11 (M7940)

(M9400-VE)

MSV11·B (M7944)

......

BC05L-XX

--1
(M9401)

RKV11 (M7269)

MSV11·B (M7944)

LAV11 (M7949)

MSV11·B (M7944)

(M9400-VD)

DLV11 (M7940)

EXPANSION
BACKPLANE
FRAME 2

BC05L-XX

OCV'A-XX {

(M9401)

DLV11 (M7940)
RXV11 (M7946)

EXPANSION
BACKPLANE

FRAME 3

TEV11 (M9400..VB)

MR-0793

0324 Module Utilization Drawing for Recommended
Expanded Systems Using PDP-11 /03-JA or -JB CPU Box

0324

KD11.Q (M7264·YBI
CPU

MSV11-C (M7955·YDI

BACKPLANE
FRAME 1
4

BCV1B-XX

{

REV11-C (M9400-YCI

DLV11 (M79401

(M9400-YEI

RKV11 (M72691

BC05L-XX

(M94011

EXPANSION
BACKPLANE
FRAME 2

-~V1A-XX
4

{

(M9400-VD)

BC05L-XX

(M9401)
EXPANSION
BACKPLANE
FRAME 3

TEV11 (M9400·YB)
MR·0792

0324 Module Utilization for Basic System
Using POP-11 /03-JC or -JO CPU Box

0324

KD11-Q IM7264-YBI
CPU
BACKPLANE

MSV11-C IM7955-YDI

FRAME 1

MSV11-C IM7955-YDI
IM9400-YEI

~V'B-XX

REV11-C IM9400-YCI

BC05L-XX

{

..EXPANSION
BACKPLANE
FRAME 2

~V'A-XX
EXPANSION
BACKPLANE
FRAME 3

IM94011

DLV111M79401

DLV11 IM79401

RKV111M72691

DLV11 IM79401

LAV111M79491

IM9400-VDI

RXV111M79461

BC051.-XX

{

IM9401)

TEV11IM9400-YBI

MR-0794

0324 Module Utilization for Recommended
Expanded Systems Using POP-11 /03-JC or -JO CPU Box

0325
0325
The D325 system, with DIGITAL's fully supported CTS-300 software license
and DIBOL instruction set, includes the PDP-11 /03 central processor, 64K
bytes of MOS memory, bootstrap loader, serial line interface, and VT52
CRT console terminal. There is an RLV 11 controller with dual five-megabyte
removable disk drives (RL01) for use as a system device and as a primary
backup and load device. This configuration is arranged in an H9602 cabinet
and an H9532-AA desk.
Space is reserved in this configuration for a printer. Any of the following
may also be added: additional RLO 1 disk drives plus cabinet, dual floppy
disk unit, choice of four printers, up to three video or hard-copy terminals
and / or a 2780 communication package and CTS-300 DICAM (a software
package).

CPU

LA180
OPTIONAL
PRINTER

0325 System

0325
Model Designation

D325A
Input Power / Frequency
H9602
PDP-11/03
RL01
H9532
VT52
LA180·

NE
PA

·ModelAA + LA180
Model AD + LA 180

Model BA,
Model BD.

AA
115/60

AD
230/50

CM
NC

CN
ND

AK
AA

NF
PD

0325 SPECIFICATIONS
PRINTER LA 180
115V
60HZ
15A
POWER
CONNECTOR

NEMA NO

230V
50HZ
15A

RL01 CA61NET
115V
60HZ

230V
50HZ

30A W

CPU CABINET
115V
60HZ
30AW

230V
50HZ
20A X

VT52 DESK
115V
60HZ
15A

230V
50HZ
15A

WI. ~
WI. --- @,@ @@ ©©
©
5-15 P

6-15 P

15-30 P

66-20 P

5-15 P

6-15 P

DEC PIN

90-08938

90-08853

12-11193

12-11192

90-08938

90-08853

AMPERAGE

1.5A

2.6A

1.3A

.5A

BTU/HOUR

1023

1100

3400

400

HEAT DISSIPATION

300W

960W

118W

SHIPPING WEIGHT
(APPROXIMATE)

120 LBS
55 KG

275 LBS
125 KG

350 LBS
159 KG

2~ LBS

225 LBS
102 KG

102 KG

D325
Modules Included In the Basic System

Processor
KD11-Q (M7264-YB)
No resident memory
CPU refresh disabled
Powers up to 173000

Memory
MSV 11-DD (M8044)
64K byte MOS RAM
One in basic system
Addresses start at bank 0
Internal refresh

Serial Line Interface
DL V 11 (M7940)
Device address 177560
Vector 60
9600 baud
EIA
One stop bit, eight data bits, no parity

Disk Drive Interface
RLV11 (M8013 and M8014)
Device address 174400
Vector 160

Bootstrap
BDV 11-AA (M80 12)
Bootstrap enabled
Real time clock enabled (switch B5)
92

D333C
LA 180 Printer Interface
LPV 11 (M8027)
Device address 177514
Vector 200
C/D BUS FOR
Q-BUS

INTERCONNECTING
D

KDll-Q (M7264-YB)
2

MSV11-DD(M8044-DA)

RLV11 (M8013)

RLV11 (M8014)

DLV11 (M7940)

EMPTY

LPV11 (M8027)

EMPTY
OPTION

OPTION

BDVll-AA (M8012-YA)
MR-4884

0325 Module Configuration Using PDP-11 /03-NC or PDP-11 /03-ND Box

D333C
The D333C data system with DIGITAL's fully supported CTS-300 software
license and DIBOL instruction set includes the PDP-11 /23 microcomputer
with 128K bytes of MOS memory, a four-channel serial line interface with
bootstrap/terminator and a VT100 CRT console terminal. There is an
RXV21 controller for a dual RX02 floppy disk storage medium. This configuration is arranged in an H9642 system cabinet and an H9532 work table.
This system can be expanded for greater storage capacity.
Model Designation
D333C
Input Power 1 Frequency
H9652
PDP-11/23
VT100
LA180
RX02

115/60

230/50

AA
NA
PA
BA

AB
NB

PO
BC

D333C
Compatible Options
•

An additional 128K bytes memory

•

Additional video or hard-copy terminals for a total of four

•

Additional storage medium
Second dual floppy disk (1 megabyte storage)

•

Choice of printers

•

BATCH or interactive communication software languages:
DICAM - Data System Interactive Communications Access Method
(for IBM 360/370 hosts)
DIBOL -

DIGITAL Business-Oriented Language

RDCP -

2780/3780 BATCH Communication Package.

CONNECTOR 1

CONNECTOR 2

r---------~A--------~'rr---------AA---------,

SLOT A

PROCESSOR
MODULE
OPTION 1
HIGHEST PRIORITY

SLOT B

SLOT C

SLOT D

ROW 1

KDFll·AA (M8186)

ROW 2

MSVll·DD (M8044D)

OPTION 2

ROW3

MSVll·DD (M8044D)

OPTION 3

ROW 4

RXV21 (M8029) •

OPTION 4

ROW 5

DLVll·J (M8043)"

OPTION 5

ROW6

LPVll (M8027)

OPTION 6

ROW 7

OPTION 7

ROW8

OPTION 8
(LOWEST PRIORITY)

ROW9

BDVll (M8012)
VIEW IS FROM MODULE SIDE OF BACKPLANE
'NOTE:

MUST BE AT CS REVISION 'El' OR HIGHER.

"NOTE:

MUST BE AT CS REVISION 'E' OR HIGHER.

D333 Module Configuration

D335C
D335C
The D335C data system, with DIGITAL's fully supported CTS-300 software
license and DIBOL instruction set, includes the PDP-11 /23 microcomputer
with 128K bytes of MOS memory, a four-channel serial line interface with
bootstrap/terminator, and a VT100 CRT console terminal. There is an
RL V 11 controller with 10-megabyte removable RLO 1 dual disk drives for
use as a system device and a primary backup and load device. This configuration is arranged in an H9642 system cabinet and an H9532 work table.
Space is available in this configuration for a printer.

Model Designations
D335C
Input Power / Frequency
H9642
PDP-11/23
RL01
H9532
VT100
LA180·

AA
115/60

AD
230/40

AA
AK
AB

AB
AK
AB
NB
PD

NA
PA

·Optional

Modules Included in the Basic System
Processor
KDF 11-AA (M8186)
Memory management standard
KEF 11-A floating point (optional)

Memory
MSV 11-DD (M8044)
64K bytes MOS RAM (two in basic system)
Addresses start at bank 0
Internal refresh

D335C
Serial Line Interface
DLV 11-J (M8043) (Must be at CS revision "E" or higher.)
Console device address 177560
Vector address 60
9600 baud
EIA RS423 and RS-232C
One stop bit, eight data bits, no parity

Disk Drive Interface
RLV11 (M8013 and M8014)/RL01
Device address 174400
Vector address 160

Bootstrap
BDV 11-AA (M80 12)
Bootstrap enabled
Real time clock enabled (switch B5)

LA 180 Printer Interface
LPV 11 (M8027)
Device address 177514
Vector address 200

D336C

CONNECTOR 1

CONNECTOR 2

r-----------------~H~--------~A~--------SLOTA

PROCESSOR
MODULE
OPTION 1
(HIGHEST PRIORITY

SLOTB

SLOTC

SLOT D

ROW 1

KDFll·AA (M8l86)

ROW2

MSVll·D (M8044D)

OPTION 2

ROW3

MSVll·D (M8044D)

OPTION 3

ROW4

RLV11 (M8013)

OPTION 4

ROW5

RLVll (M80l4)

OPTION 5

ROW6

DLVll·J (M8043) *

OPTION 6

ROW7

LPVll (M8027)

OPTION 7

ROW8

OPTION 8
(LOWEST PRIORITY)

ROW9

BDVll·AA (M80l2·YA)
VIEW IS FROM MODULE SIDE OF BACKPLANE
*NOTE:

MUST BE AT CS REVISION 'E' OR HIGHER.
MA48B6

0335 Module Configuration

D336C
The D336C data system, with DIGITAL's fully supported CTS-300 software
license and DIBOL instruction set, includes the PDP-11 /23 microcomputer
with 128K bytes of MOS memory, a four-channel serial line interface with
bootstrap/terminator, and a VT100 CRT console terminal. There is an
RL V 11 controller with 20-megabyte removable dual RL02 disk drives for
use as a system device and a primary backup and load device. This configuration is arranged in an H9642 system cabinet and an H9532 worktable.
Space is available in this configuration for added expansion such as a
printer, a serial line interface, synchronous communication, memory, floppy
control, etc.
97

D336C

Model Designations
0336C
Input Power / Frequency
H9642
POP-11/23
RL02
H9532
VT100
LA180·

AA
115/60

AD
230/50

AA
AK
AB
NA
PA

AB
AK
AB
NB
PO

·Optional

Modules Included in the Basic System
Processor
KOF 11-AA (M8186)
Memory management standard
KEF 11-A floating pOint (optional)

Memory
MSV 11-00 (M8044)
64K bytes MOS RAM (two in basic system)
Addresses start at bank 0
Internal refresh

Serial Line Interface
OLV 11-J (M8043) (Must be at CS revision "E" or higher.)
Console device address 177560
Vector address 60
9600 baud
EIA RS423 and RS-232C
One stop bit, eight data bits, no parity
98

D336C
Disk Drive Interface
RLV 11 (MBO 13 and MBO 14) / RL02
Device address 174400
Vector address 160

Bootstrap
BDV 11-AA (MBO 12)
Bootstrap enabled
Real time clock enabled (switch B5)

LA 180 Printer Interface
LPV 11 (MB027)
Device address 177514
Vector address 200

CONNECTOR 1

CONNECTOR 2

r---------~------~"r---------A--------~

SLOT A

PROCESSOR
MODULE
OPTION 1
(HIGHEST PRIORITY

SLOT B

SLOTC

SLOT 0

ROWl

KDFll-AA (M8l86)

ROW2

MSVll-D (M8044D)
MSVll-D (M8044D)

OPTION 2

ROW3

OPTION 3

ROW4

RLVlll(M80l3)

OPTION 4

ROW 5

RLVll (M80l4)

OPTION 5

ROW6

DLVll-J (M8043) *

OPTION 6

ROW 7

LPVl i (M8027)

OPTION 7

ROW8

OPTION 8
(LOWEST PRIORITY)

ROW9

BDVll-AA (M80l2-YA)
VIEW IS FROM MODULE SIDE OF BACKPLANE
*NOTE:

MUST BE AT CS REVISION 'E' OR HIGHER.
MR-4BB7

0336 Module Configuration

D336C

FRONT VIEW
~18"-.

(46 em)

42"

DISK
EXPANSION

RL01/2

CPU
EXPANSION

CPU

DISK
EXPANSION

RL01/2

~ (3815"em)

TABLE

22"
22"
1'--(56 em)--- ~(56 em)"
(Optional)

27"
(69 em)

48"
(122 em)

(BASIC SYSTEM)

TOP VIEW

~
Y15ft
(4.6 m)

~15ft
l'

OPTION
CABINET

CPU
CABINET

867 Watts
2948 Btu/hr
370 Ibs
(168 kg)

918 Watts
3121 Btu/hr
370 Ibs
(168 Kg)

-.:r

30"
(76 em)

(4.6 m)

CRT
150 Watts

•
14"

51~5BI~:hr

(36 em)

(16 kg)

30"
(76 em)
I

•

MR4BBB

0325, 0335, and 0336 Oata Systems

100

TELEPHONE COMPANY SYSTEM

CC1A PDP-11V03 SYSTEM
A non-DIGITAL terminal is used with this system. The terminal is a Tektronix'M 4023 AN. The Tektronix terminal must be an "AN" version and is configured for 9600 baud and checked out by the Western Electric Company
(WECO) representative.
For installation, a null modem is provided by DIGITAL Field Service. Use of
an H312 null modem will cause receive status errors, therefore a BC03M-L
cable is recommended for installation checkout. The terminal will be connected through the null modem directly to the DL V 11, by-passing the Bell
interface cabinet located on top of the PDP-11 V03 cabinet. After system
check, the WECO representative will connect the Bell interface.
When running the Tektronix terminal after the screen is full, the first seven
characters will be scrambled owing to terminal and software incompatibilities. Hit the ERASE key or change the baud rate on the back of
the terminal (rotary SW) and DL V 11 interface to 2400 baud. The diagnostics will run at this lower speed. Remember to return the system to 9600 for
the customer.
Step 4 of the installation procedure asks the DIGITAL Field Service engineer to show that the floppy disk will boot from drives 0 and 1. Other versions of the monitor would only boot from drive 0, but recent shipments of
this system should contain the newer floppies that will boot from both
drives.
Step 4 also asks the DIGITAL engineer to demonstrate the clock diagnostic
VKAHAO for at least 10 minutes. After several passes, the "TIME" printout
must have incremented to indicate that the clock is running. The clock is
unlike most PDP-11 real time clocks in that it is only a line "BEVNT" which
goes to the CPU causing an interrupt. If it is not working, check the "LTC"
switch on front panel and items in FA&T checklist, sheets 15 and 16.
For troubleshooting, the two backplanes can be separated by removing the
M9400-YE in slot 4 and switching DRV 11 No. 1 and DL V 11 (see sheet 11 of
configuration). This will allow the BA 11-MA to function as a system without
the BA 11-"ME connected. Remember to reconfigure to the original condition
when finished.
101

TELEPHONE COMPANY SYSTEM
DRV 11 No. 1 and DRV 11 No.2 must be set up properly for the slot position
where they are located or the wrong lines may be connected to them.
The PDP-tt / V03 System Manual, EK-11 V03-TM, should be available to the
Field Service engineer for 11 V03 and diagnostic information. The Microcomputer Handbook is also a good source of technical PDP-11 V03 information.

CC# 1A Diagnostic Check List
RXDP Diskettes
0#1
0#2
0#7
0#10
0#15
0#25
0#26
0#30
SPECIAL DECX 4

o
o 11 V03
o
o
o
o
o

o
o
o
o

VKAAAO
VKABAO
VKACBO
VKADBO
1-VKAHAO
DL V 11 M7940 - - VKAEB 1
DRV11 M7941- 2 - VKAFBO
MSV 11 CD M7955 - ZKMADO
RXV11 M7946 - 3 - ZRXBEO
ZRXAEO
REV M9400-Y A - - ZM9ADO

Basic Inst. Test
EIS
FIS
TRAPS
TIME

#25
#25
#25
#25
#25
#25
#25
#25
#15
#15
#10

1. Run two passes minimum, approximately 10 minutes and check that
"TIME" printout is incrementing.
2. Use a BC08R-1 loopback cable for testing. Diagnostic will come up
testing DRV 11 No.2; therefore, after several passes, halt CPU and
change address and vector information as shown:

102

TELEPHONE COMPANY SYSTEM
$DXO
DZaUJ-C 21-JUL-76 R
.R VKAFBO
} TESTING OF DRV11
ENII OF PASS
END OF PASS
END OF PASS
004410
@1200/167770
167760 )
001202/167772 167762
001204/167774 167764
001206/167773 167763
001210/000300 310
001212/000302 312
001214/000304 314
001216/000306 316
001220/167770
@200GEND OF PASS
END OF PASS

MODIFICATION OF PROGRAM
ADDRESS AND VECTORS FOR
DRV11 1
TYPE L.F. AFTER ENTRY ONLY.
TYPE C.R. ON LAST ENTRY.
TYPE 200G.
TESTING OF DRV11 1

004402
@

3. Run ZRXBEO before running ZRXAEO.

4. Special DECX map:
.MAP
CF'AFO AT
CPBIO AT
FF'AFO AT
DHCHO AT
BMCMO AT
RXArtO AT

017752 STAT 040020
021502 STAT 040020
023242 STAT 040020
024522 STAT 040020
025430 STAT 040020
030054 STAT 140000

5. Diagnostics available on single floppy.

NOTE
This is not an official software package and is intended for
field use only.
ENTRYt FILNAM.EXT
000001
000002
000003
000004
000005
000006
000007
000010
000011
000012
000013
000014
000015
000016
000017
000020

RXDP .BIN
UF'D2
.BIN
XTECO .BIN
VKAAAO.BIC
VKABAO.BIC
VKACBO.BIC
VKADBO.BIC
VKAEB1.BIC
VKAFBO.BIN
ZKMAB1.BIC
ZKMADO.BIC
ZRXBEO.BIC
ZRXAEO.BIC
ZM9ADO.DIC
VKAHAO.BIC
CHAIN .CCC

DATE

LENGTH

START

7-MAR-78
7-MAR-78
7-MAR-78
7-MAR-78
7-MAR-78
7-MAR-78
7-MAR-78
10-MAR-78
10-MAR-'78
10-MAR-'78
10-MAR-78
10-MAR-78
10-MAR-7S
10-MAR-78
4-APR-78
5-APR-78

17
30
26
17
17
16
12
7
6
9
9
17
20
7
17
1

000050
000071
000127
000161
000202
000223
000243
000257
000266
000274
000305
000316
000337
000363
000372
000413

103

TELEPHONE COMPANY SYSTEM

CC # 1A Module Jumper Information

Module

Option

Jumpers

Microcomputer
Handbook Page

M7264

CPU

W4, W6, W91N

243,236

M7955
M7955

MSV11CD
MSV11CD

1-5 ON, 6-8 OFF
3, 6, 7, 8 OFF, others ON

244
244

M7941

DRV11 No.1 A3, A121N [A = 767760]
V4, V51N
V = 310

M7941

DRV11 No.2 A 12, V3, V4, V51N [A = 767770] 290
V = 300

290

M9400-YA REV11-A

Remove W2

380

M7940

Refer to Micro Handbook

259

DLV11

104

TELEPHONE COMPANY SYSTEM

DIGITAL EQUIPMENT CORPORATION
MAYNARD, MASSACHUSETTS
DATE 14 JUN 78

MANUFACTURING SPECIFICATION
TITll

sees cnmn COro..£ 00, lA (CC ~O, lA) COflCiJPATlOO
REVISIONS

jcHG NO

REV

DESCRIPTION

DLV1l is current ly being shi[lped
wi th system due to unava il ab i 1ity
of DLVll-F. Change package to
reflect DLVll instead of DLVll-F.

ORIG

-'A

105

APPD BY

DATE

J. Tomaswick /14/78 J. Tomaswick 6/14/7E

SIZE ICODE
EN-olO'l· J6-N1721JI2)

DATE

NUMBER

MFGENG-O CONF -0004

I REV

TELEPHONE COMPANY SYSTEM

MANUFACTURING SPECIFICAnON
TITLE

CONTINUATION SHEET

SCCS CONTROL CONSOLE NO. lA (CC NO. lA) CONFIGURATION

INDEX

PAGE

ECO

REV

Index

Configuration Approvals

Users Page.

System Description.

Configuration Notes

Equipment List.

*
*

Installation Procedure.

Cabinet Layout.

Cabinet Modification.

Box Layout.

Bus Sequence.

*
*

Cab 1e Layout.

Device Address Assignment

Telco FA&T 11V03WA Checkl ist.

Telco FA&T 11V03WA Checklist.

Change Page

*
1

I"i I I MFGENG~~'t:~~r-0004 J
E

~c 11-11.11-10....... 71

CODE

R:V

SHEET -L. OF --1L-

106

TELEPHONE COMPANY SYSTEM

MANUFACTURING SPECIFICAnON
TITLE

SCCS CONTROL CONSOLE NO. lA

CONTINUATION SHEET

(CC NO. lA ) CONFIGURATION

CONF IGURATION APPROVALS

Olgihl Account Representative

Digital ProJ ect Manager

Olgltal Manufacturing Engineering Manager

01 gHa' Quality Control Manager

tHgita' F1e1d Service Product Support

0igital TELCO Engineering

Ofagnostlc Englneering

Production Manager
* CONFIGURATION REVIEWED
Be"

La6s Representative

Western Electric Purchasing
*Any review of these specifications by any Bell System representative shall be for
general arrangement of the work and shall in no case relieve you in any way of your
responsibilities as defined by our purchase orders.

I -A

SIZE ICODEI

DEC It-(J.ZHOU-HI7Z

HUMBER

MFGENG-O CONF-0004
SHEET _2_ OF

107

REV

1L-

TELEPHONE COMPANY SYSTEM

MANUFACTURING SPECIFIC AnON
TITLE

CONTINUATION SHEET

SCCS CONTROL CONSOLE NO. lA (CC NO. lA) CONFIGURATION

TO THE USERS OF THIS DOCUMENT:

This is a Digital Manufacturing Specification for a DEC system purchased by
Western Electric. Configuration approvals are included 1n order to assure that
a system is manufactured in accordance with the latest known requirements.
The information conta1ned herein 1s consistent w1th the 1nformat10n included 1n:
Bell Telephone Laboratories - SOli lP039-01
Western Electric J-Drawing JlC016K-l
DEC Standard Price L1st

It is imperat i ve that the Bell Laboratori es and/or Western El ectri c Purchas i ng
s i gnat or ies contact the Di gi ta 1 Account Representat i ve in the event of changes
to the SO and/or J-drawing. Should these changes aff~ct the contents of this
document, the Digital Account Representative shall contact the Digital Project
Manager who, in turn, shall have this document updated. Conversely, no changes
sha 11 be made to the product manufactured under thi s spec i fi cat ion without
written notification to and expressed approval of the Bell System signatories.
When Digital issues a new price list, the Digital Account Representative shall
assure that all requ; site equ i pment cont; nues to be offered under the DEC codes
listed herein. If any of these items is no longer listed, either of the following procedures shall apply.
1)

The Digital Account Representative shall notify the Bell Laboratories
and Western Electric signatories of changes to nomenclature and
packaging in order to include the then current equipment lists in the
next issued SO and J-drawi ng.
-orThe Digital Project Manager shall convene a configuration review committee meeting (attended by all the signatories of this document or
thei r des i gnated represent at i ves) for the purpose of 1dent Hying
the alternate equipment to be used for this project configuration.
At such a t1me, the short-term requirements and avallabil it1es of
the equ i pment 1i sted herei n shall be determi ned and the appropri ate
trans1tion plans shall be made.

Digital Field Service shall adhere to the information contained in this document. If the end-user wishes anything different, the end-user should be told
to contact the appropriate Western Electric Regional Office.
This specification is included with all shipments of DEC equipment for this
project.

S,}E1CODEl

Me: l"(III.·lOl~"J

108

NUMBER

REV

I MFGENG-O COOF -0004 *
SHEET --L- OF ...l1_

TELEPHONE COMPANY SYSTEM

MANUFAcruRING SPECIFICATION
TITLE

CONTINUATION SHEET

SCCS CONTROL CONSOLE NO. lA (CC NO. lA) CONFIGURATION

SYSTEM DESCRIPTION
The PDPllV03-WA configuration is a subsystem of the switching control
center system's control console No. lA.
The control console No. lA is used to provide remote maintenance, alarm,
surviellance and control of unattended electronic telephone switching
offices. Its most important function is to provide remote control
capabilities to restore the telephone switching office to service after
certain types of failures. The reliability and availability of the
control console are extremely important due to its potential use during
cr.itical periods where telephone service in a particular telephone
switchin9 office has been interrupted. It may be used in continuous
service (24 hr/day) application.
The microcomputer is connected via the DLVll to a
CRT for
display of alarm data as well as input of remote control requests. The
connect ion is accomplished via a null mOdem cable to provide the proper
handshak i ng and data interchange.
A telemetry data network is driven via a DRVll and is the primary link
from the control console to the remote telephone switching office.
Another DRVll sends data to a circuit that drives a local alarm display.
The microcomputer configuration carries a Western Electric designation
of JIC016K-1. The telemetry equipment, local alarm interface and cables
(including a null modem cable) have a designation of JIC016L-1. The CRT
is designated JIC016M-1.

SI]E ICODEI

DeC I~ltll 1011..... 71

NUMIER

IMFGENG-O CONF oi()004
SHEET

109

I REV
A

-L OF -!l..-

TELEPHONE COMPANY SYSTEM

MANUFAcnJRING

CONTINUATION SHEET

SCCS CONTROL CONSOLE NO. lA (CC NO. lA) CONFIGURATION

TmE

CONFIGURATION NOTES

This is a fixed configuration.

There is no optional equipment.

DiagnostiC media is RXDP diskette.

The DLVll will be configured as follows: EIA, 9600 BAUD,
8 data bits. 1 stoP. no parity, framing error halt strap ......
removed. Other options not specified here shall be set to
DEC Standards.

The REVll will be configured as follows:
ROM enabled.

At the time of installation or service call. a working 9600
BAUD terminal compatible with the system must be made
available by the customer.

Warranty is 90 days from date of in~tallation or six months
from ship date, whichever comes first.

The clock operation must be verified by running MD-11-DVKAH-XX
a minimum of two passes. See 1tem 7 on page 15.

The abil1ty of the system to boot MAINOEC 11 - DZQUJ'",DO from both
drive 10 and 11 must be demonstrated.

System enviromenhl requirements will be in accordance with
Bell System BSP - Section 760-251-150. "Site Prep and
Enviromental Considerations for Minicomputers in Standard
Systems".

10.

For installation testing. a null modem is required between
the DLV11-F serial 11ne unit and the 9600 BAUD terminal.
DEC shall provide th1s null modem during installation testing
of PDP 11 V03/WA.

11.

Installer will remove DRV11 11 and #2 and visually ver1fy
the vector address on each per the Device Address Assignment
Sheet. Us1ng DEC diagnostic MD-llDVKAF-B only one DRVll
will be run at a time.

12.

Max1mum current limitat 10n on power strip for use by customer
1s four (4) amps.

13.

The DRVll's will have a label placed on the handle on side 2
dep1ct1ng the address and vector of the DRVll as per the follow1ng
example:
VECT 310
DRVll 11 ADD 767760
or
VECT 300_
DRVll 12 ADD 767770

DMA refresh disabled.

l "I" I

"ZE CODE I

Me 11-(...'·101 ..... "

110

NUMBER

SHEET _5_ OF

--.!Z..

IMFGENG-O CONF -0004

REV

TELEPHONE COMPANY SYSTEM

MANUFACl'URlNG SPECIFICATION
TITLE

CONTINUATION SHEET

SCCS CONTROL CONSOLE NO. lA (CC NO. lA) CONFIGURATION

CONFIGURATION NOTES (cont.)
14.

In order to assure a higher quality level, pages 15 and 16
(Telco FA&T llV03WA, SCCS Control Console NO. lA (CC NO. lA)
Configuration Checkl1st) is to be completed by the PSI
personnel for each system. Their initials wl1l signify
that they have completed or verified each indicated
procedure.

ICODEI
NUMBER
1RI:V
A
MFGENG-O CONF -0004 *
I '~E

IHEET ~ 0' -!L

111

TELEPHONE COMPANY SYSTEM

MANUFAcnJRING

TlTLI

CONTINUATION IHIET

SCCS CONTROL CONSOLE NO. 1A (CC NO. 1A) CONFIGURATION

EQUIPMENT LIST

One (1) llV03WA composed of the following:

ill!1

.9ll

DE SCR I PTI ON

1l/03-KA consisting of:
-MSVll-CD
-KEVllA
-KDll-R
-BAll-MA

DRVll

DLVll

MSVll-CD

REVll-A

BAll-ME

BCVIB-06

H984-DA

BC05C-25

RXVll-BA

IS'IE JCODEI MFGENG~N~BIF~ooo41lEV
DeC Ifo<lIIll..._7,

112

TELEPHONE COMPANY SYSTEM

MANUFAcruRING IPEClFlCAnClN

CONTINUATION IHEET

SCCS CONTROL CONSOLE NO. lA (CC NO. lA) CONFIGURATION

TITLE

INSTALLATION PROCEOURE
The control console No. lA consists of:

-DEC Processor, JIC016K-l
-Interface Unit, JIC016L-l
-Tektronix model 4023AN CRT Terminal, JIC016M-l
After the above equipment has arrived at the site storage loc"ation, the
following procedures and guidelines shall be followed •.
1.

The Western Electric (WECO) installer shall verify that the CRT terminal
is operat iona 1.

The WECO ins ta 11 er sha 11 make arrangement s for the DEC representat i ve to
be at the job location and will secure permission for movement of the
DEC processor from the storage location to the job site.

At the job site, WECO installation shall provide all labor required for
unpacking and placing the equipment',in the desired location. The DEC
representative will supervise the unpacking and placement of DEC equipment
and verify any evident damages for subsequent claims.

After the WECO installer has mounted the interface unit on the processor
and lowered the interconnect cab 1es to the processor area, the DEC i nstaller will run diagnostics on the processor. The DEC installer will
provide the null modem cable to interconnect the DLVll to the CRT
terminal for testing. In addition to DEC diagnostics, the DEC installer
shall demonstrate the capability to boot from drive 0, Drive 1 and
demonstrate that the system clock is operat iona 1.

Upon successful completion of the diagnostics, the DEC installer shall
connect the following cables, previously lowered by the WECO installer,
to the processor.
"JI-DRV(2) .side up"
"J2-DRV(2). side up"
"J-DLV.side up"
"JI-DRV(l).side up"
"J2-DRV(1).side up"
AC Power Plug

The DEC installer shall demonstrate that the removal and reinsertion
of processor boards for cable connection did not affect processor
operation.

Upon successful completion, the WECO installer will accept the DEC
processor and initiate control console No. lA diagnostics.

"1E ICODE I

113

I REV
A·
IHEET _8_ OF ...!L
NUIilIER

I MFGENG-O CONF-0004

TELEPHONE COMPANY SYSTEM

MANUF At"I'lJlUNG TITLE

SCSS CONTROL CONSOLE NO.

CONTINUATION SHEET

lA (CC NO. lA) CONFIGURATION

CAB I NET LAYOUT

digital rxtil

IIIII~ IIIII {I1II ~ 11111
digital pdp 11/03

I<L!)~I

I;J

111E ICODEIMFGENG~u~eN~~0004 IR~V
IHEET ..2- OF -1.L

114

TELEPHONE COMPANY SYSTEM

CONTINUATION SHEET
TITLE

SCCS CONTROL CONSOLE NO. lA ( CC NO. lA) CONFIGURATION

II, II,'

•• ,,'

1:1 .·/I/vli"! IJI?, l'rJ

lie I"..." II. 1'I~ ..".rn'li/." wilL
ItI('I","',

IV/ex.

I"H· ....~I".IX.

2" ~L·O,.."

51/)(;. D~ BOX

SHEET

115

REV

*
..l2.- OF .17 _

FGENG-O CONF ·0004

TELEPHONE COMPANY SYSTEM

MANUF At7URIN

TITLE

SCCS CONTROL CONSOLE

NO. lA (CC NO. lA)

CONTINUATION SHEET

CONFIGURATION

CABINET LAYOUT

A
• M7264-YA
M7955
M7955
4

M9400-YE

(KDII-H)
(MSVll-CD)
(MSVll-CQ.L

1 M7941

(ORVll 11)

REV
DEC: 1~1I'l-l"J""71

SHEET

116

-l.L OF --E.

TELEPHONE COMPANY SYSTEM

MANUFAcnJRING SPECIFICA 0
TITLE

SCCS CONTROL CONSOLE NO. lA (CC NO. lA)

CONTINUATION SHEET

CONFIGURATION

BUS SEQUENCE

REV
A
SHEET

117

-.JL OF _

TELEPHONE COMPANY SYSTEM

MANUF ACI'lJRING SPECIFICAnON
TITLE

sees CONTROL CONSOLE NO. lA (ee NO. lA)

CONTINUATION SHEET

CONFIGURATION

CABLE LAYOUT

RXOIBA

BAll-MA

...j

U'l
0
U

CXl

c:(

ID N
0o ID

-' co
U'l0
00

CXl .....

BAll-ME

J 1

'IE CODEl

NUMBER
Io1FGENG-O
eOnF -0004

REV

SHEET lL- OF ...Q.

DEC 16o{JIlI-101''''I7'

118

-4

VEe
DES I G';A.TIm.

DRVll II

WECO
['IESIGNATION

Parallel 1

REGI5"J1:R
ADDRESS

767760

VECTOR

ArmRESS

310

PRIORITY

KlUNTING
CODE

+SVf)(

2 Slots

BUS
LOADS

CO~"'E"'TS

Parallel 2

767770

300

2 Slots

DLVll

Serial

777560

2 Slots

RXVll

Di sk-Cont

777170

264

2 Slots

!:j
c:

l!
z
0

DRVll 12

...~ ..,c>z

DEV ICF ADDRESS ASS IIiN~lErn

SO
~

9600 BAUD

;;

;:;

~0
Z

-f

m
r
m

co
I--

r-o'"

NOTE:

PRIG ~ITY DETERMIN D BY DEVI E CLOSES

TO THE (IPU.

SEE B S SEQUENCf :

PRIOR TY 1 = HIGHEST

~
CIt

:z:

'"'"....

'P
0

•

~
0

o
... ~

...

.".

lit
%

III

I-~:II

III

-4

"'C

:E:

o
Z

o
o

3:
"'C

»
Z

-<
en
-<
en
-f

m
3:

TELEPHONE COMPANY SYSTEM

MANUF ACTlIRlNG SP.."..,.·... •....... N
TITLE

CONTINUATION SHEET

sees CONTROL CONSOLE NO. lA (CC NO. lA) CONFIGURATION
TELCO FAn 11V03-WA sees CONTROL CONSOLE NO. lA (CC NO. \A) CHECKLIST
INITIAL
1 .) The cab fan power cord shou 1d be plugged into the rear plug
of the dual receptacle. (Mounted on side of cab).
2.) DRVll's should have a sticker on the module, side 2 under
the cable, giving address, vector and DRVl1 number 1 or 2.
3.) Cables for DRVll should be installed ribbed side up.
4.) Check for a green wire on the console board between
TP2 and W4.
5.) All ribbon cables should have the red strip on the right.
6.) Cable from J2 (console board) should be routed behind the
switch pane 1.
7.) Run diagnostic VKAHAO as shown. If the time is 000000,
the clock is not running. Write the time printed for
pass number 2:
(it takes 5 minutes per pass).

tnxo

_.. __

~ -2.1.=...lUI..-:..2•

.~ VK~_

~L"__.

•

_ __
__

.B.Uf-. ~---UllLUO 1 ....ltQIIIUOR...2BK '
___

___ ..

_._ .

DVKAH-A
J1£tt.QRY·~:5UZ6

PASS-oGOOOl ERRQR-OOOOOO RXERROR-OOOOOO TI"E-044416
PASS-000002 ERROR-OOOOOO ~XERROR-OOOOOO TI",-110101
8.) DLVll should be set up for EIA before software is run.
(NOTE: Do not ship 70-08360 cable).
9.) 74-16240-0-0 stickers on 11V03 and BAll-ME should be filled
out as shown. Note that DRVll '1 is addressed at 767760,
vector 310 and is in the llV03 box. DRVl1'2 is addressed
at 767770, vector 300 and is in the BAll-ME box.

S~E1CODE'

DEC 1"(~'.)·10l1""71

120

NUMBER

I MFGENG-O CONF -0004

'REV

SHEET -15.... OF -1L

TELEPHONE COMPANY SYSTEM

MANUFAcruRING SPECIFICAnON

tm.I

CONTINUAT'ON SHEET

SCCS CONTROL CONSOLE NO. lA (CC NO. lA) CONFIGURATION

fCPu
. .OT

MODULE NUMBER
A
8

MODULE NUMBER
D

-~-

ETCH
REV

MODULE NUMBER
C
D

BCVIB-06
Rx V II
I'¥ I~

DLVII

MODULE NUMBER
A
8

REV

ETCH
REV

*
cs

REV

* *' DR. vII ....z

RE~II-A

.... ....

CS
REV

MSV I L
MSV
I - C l>
8C.VIS-06
~ DRVII -1

CPU
. .OT

, -en

L<-.D

ETCH
REV

CS
REV

ETCH
REV

t~
I~ M

* • Current Revision

INITIAL

10.) Check that the red light (01) on the console board
goes off when DC power 1S turned off.

11.) Check that drive (I and drive 1 will boot, load and
run RXDP diagnostics (Rev D required).

DEC'

IS'ZE ICODEII

ORe 16-(111)-101_172

NUMSER

HFGENG-O CONF-0004
SHEET

121

REV

-ll... OF --E

Date

6/14/ 8

Change

...

1&.1
III

Requested
By

Effective
Date**

J. Tomaswick 6/14/78

III

Production

Natcrial

~Ianagcr

~Ianager

I'agcs
Affected

Final
Approval

Change
Descript ion

1,4,5,7,8 J. Tomaswic
11,12,14,6

"'z

III'"

DLVll is currently being
shipped with system due to
unavailabilty of DlVll-F.
Change Document to reflect
DLVll instead of DLV11-F.

...

~z ~I
0

<!)

l5
<!)

~
III

0
0

ffl

~~
III

----

LIJ

~
U)

<
Cl.

>
z>

c.!)

UJ
C)

<
a.

0
j:

o
o

U
11.1

LIJ

::J

:E
Z

:J:

.:..

II)

Ci2

-«
0

IIll:

-z
c.!)

u..

t U
.<
"::>

LIJ

:=;:

::l

LIJ

..J

< ...
;:::
Z

*- All ships on or !lfter this date must have change incorporated.
NOTE:

These changes wi 11 be incorporated in the next release cycle.

C\I
C\I

PDP-11L03

LABORATORY SYSTEMS

PDP-11L03
The OECLAB-11 103 (11 L03) system includes a POP-11 103 computer, an
RXO 1 dual floppy disk drive, and a terminal. The terminal is normally an
LA36 OECwriter II or a VT55 OECscope, although some custom systems
may have a VT52. Each system also includes some combination of OECLAB
modules and an H322 distribution panel to facilitate user I I 0 connections.
All models are configured to boot on power-up and halt on BREAK. Early
systems have 20K of memory, while later versions use a 16K memory. The
figures and tables that follow describe the models, specifications, and components.

RX01

11111111
1111111111111111
1IIIIIIiilllllllll::::IIII!11
111111111111111111
1111111
11111111
1111111111:11111111
11111111:::11111111::111111111
111111111111111111
111111111

11 L03 CABINET

MR-0767

OECLAB-11/03-CA, -CC, -CO, -GO, -HA, -HC, -HO, -MA, -MC, -MO, -KA

123

PDP-11L03

11 L03 CABINET

VT52/vT55 DECSCOPE

OECLAB-11 /03-0A, -DC: -~O, -GC, -JA, -JC, -JD, -NA, -NC, -NO, -LA

~
~

AC LINE

(1t5V,20A;
230V,10Al
H322

DISTRIBUTION
PANEL

nn n n n n n n n

U U_UU_UU_UU- -,.L- -LIU

MATE-N-LOK

II-----

c:::::::::Jc:::::::::Jc:::::::::J

____
1

C~N~

~
CABLE FROM DECWRITER
OR DEC SCOPE

MR-0769

124

PDP-11L03

DJ12

".~

OJ13
DJ14

H322

7014090

C..:r

I""

A6001

AAV11·A

M7952

A012

ADV11·A

KWV11·A

MR·0851

Analog Cable Connections

H322

DJ12

DJ13

J10

7014060

DJ14

DRV11

MR·0852

Digital Cable Connections

125

DECLAB-11 /03 System Model Designations

System
Requirements

Input Power (V)

115

115 220

115

115 220

115

115 220

Frequency (Hz)

PDP-11V03

LA36

RXV11

H984 (Cabinet)

SA 11 Extension Sox

ADV11 (AD12)
KWV 11 (M7952)
AAV11 (A6001)
DRV 11 (M794 1)
ISV11 (M7954)

........
rI

VT55
I\:)

0
W

DECLAB-11/03 System Model Designations (Cont)
System
Requirements

PDP-11V03

Input Power (V)

115

115 220

115

115 220

115 115 220

115 115

Frequency (Hz)

LA36
.....
I\)

"'-.J

VT55

RXV11

H984 (Cabinet)

BA 11 Extension Box

DE
FA

ADV11 (A012)
KWV 11 (M7952)
AAV11 (A6001)

"
"
C

.....
.....
I

DRV11
IBV 11 (M7954)

(,,)

PDP-11L03
Specifications
116V

POWER
CONNECTOR

230 V

60/60 HZ

60HZ

PLUG

RECEPTACLE

PLUG

RECEPTACLE

wi I
~

D OW

6-15R
12·05361

NEMA #6-16P
DEC #90-08938
CPU
CABINET

LA36

VT56

AMPERAGE
TYPICAL
MAXIMUM

10.1
11.3

2.0

WATTAGE
TYPICAL
MAXIMUM

860
1340

2730
3210

87.3
182

c:::::Ic::::I

6-16R
12.11204

NEMA #6-16P
DEC # 80-08853
CPU
CABINET

LA36

VT56

2.4

4.8
6.5

1.0

1.2

300

1000
1380

160

300

550
1020

500
1000

2800
3280

560
1020

500
1000

46.3
102

2&.8
57

87.3
192

46.3
102

2&.8
67

160

BTU/HOUR
TYPICAL
MAXIMUM
WEIGHT
KG
LBS

MA·0770

Modules Included In the Basic System
Processor
KD 11-F (M7264) in systems purchased prior to Oct. 1, 1977.
Resident memory addressed as bank 0
CPU refresh disabled
Powers up to 173000
KD11-R (M7264-YA) in systems purchased after Oct. 1, 1977.
No resident memory
CPU refresh disabled
Powers up to 173000

Memory
MSV 11-8 (M7944) in systems purchased prior to Oct. 1, 1977.
4K RAM
Refreshed by REV 11-A
Addressed as bank 1
128

PDP-11L03
MSV 11-CD (M7955-YD) in systems purchased after Oct. 1, 1977.
16K RAM
Internal refresh
Addresses start at bank 0
Part of the KD 11-R processor option

Serial Line Interface
DL V 11 (M7940)
Device address 177560
Vector 60
300 baud in systems using LA36 DECwriter II terminals
9600 baud in systems using VT55 DECscope
20 rnA active transmitter and active receiver
One stop bit, eight data bits, no parity
Framing error (BREAK) asserts BHAL T

Floppy Disk Interface
RXV 11 (M7946)
First device address (disk 0) 177170
First vector 264
Second device address (disk 1) 177150
Second vector 270

Bootstrap / Diagnostic / Terminator
REV 11-A (M9400-Y A)
Bootstrap enabled
Diagnostics enabled
Refresh enabled in PDP-11 V03-A / E
Refresh disabled in PDP-11 V03-F / H
120 Q terminator

Additional Modules Included in Optional Systems·
Analog-to-Digital Converter
ADV11-A (A012)
• For configuration details refer to the "CPU / Options" section.
129

PDP-11L03
Digital-to-Analog Converter
AAV11-A (A6001)

Programmable Real Time Clock
KWV 11-A (M7952)

Parallel Line Unit
DRV11 (M7941)

IEEE Instrument Bus Interface
IBV 11-A (M7954)

Module Utilization Notes
1.

Systems purchased before Oct. 1, 1977 have four MSV 11-8 4K memory boards instead of one MSV 11-CD module. They also have a KD 11-F
processor instead of a KD 11-H.

KD11-R = KD11-H + MSV11-CD
KD11-S = KD11-R + KEV11-A

All models of PDP-11L03 include the KEV11 EIS/FIS option.

M7264-YA PROCESSOR (KD11·H + KEV111

M7965-YD 16K MEMORY (MSV11-CDI

M7940SLU (DLV111

M94O().YA BOOT!
(REVll.AI
TERMINATOR

M7946

~'!"~:::ACE

(RXV111

M7964 ~~~TI~~~~~!CE IIBV11·AI
MR-0771

PDP-11 L03-MA, -MC, -MD, -NA, -NC, -NO

130

PDP-11L03
B

M7264-YA PROCESSOR (KD11·HI + KEV11
2

M7952 PROGRAMMABLE REAL TIME CLOCK (KWV11·AI

A012 AID CONVERTER (ADV11·AI

~~VE~~INATO"

M7946

~N~:~~ACE (RXV111

CPU BOX

BCV1B

M9401 BUS CONNECTOR

M7940SLU (DLV111

A6001 D/A CONVERTER (AAV11.AI
3

M7955·YD 16K MEMORY (MSV11·CDI
M940()"YA

~~~~NATOR (REV11·AI

M7941 PLU (DRV111

MR-0772

POP-11 L03-KA, -LA

M7264-YA PROCESSOR (KD11·HI + KEV11

M7952 PROGRAMMABLE REAL TIME CLOCK (KWV11·AI

A012 AID CONVERTER (ADV11·AI

OCOO~~VE ~~~INATO"

M7946

~~~:~~ACE (RXV111

CPU BOX

BCV1B

M9401 BUS CONNECTOR

3
4

M7940SLU (DLV111

M7955·YD 16K MEMORY (MSV11·CDI
M94OQ.YA

~~~~NATOR (REV11·AI
EMPTY

EMPTY
EMPTY

EXPANDER BOX
MR-0773

POP-11 L03-HA, -HC, -HO, -JA, -JC, -JO
131

PDP-11L03
A

M7264-YA PROCESSOR IKDll-HI + KEV11
M7962 PROGRAMMABLE REAL TIME CLOCK IKWV"-AI
A012 AID CONVERTER IADV"-AI

3
4

BCV1B

OC05~xrE ~'NATOR

M7946

~~~:~:ACE IRXV111

CPU BOX

M9401 BUS CONNECTOR

M7940 SLU IDLVll)

M7966-YD 16K MEMORY IMSV"-CDI

M7941 PLU IDRV111

EMPTY

M9400-YA

~~~~NATOR IREV"-AI
EMPTY

EXPANDER BOX
MA-0774

PDP-11 L03-CA, -CC, -CD, -GO, -DA, -DC, -DO, -GC

KD"-F PROCESSOR IM72MI

KWVll-A PROGRAMMABLE REAL TIME CLOCK IM79621

ADV"-A AID CONVERTER (A0121

(M9400-YEI

RXV"-A

~;~:~:ACE IM79Ml

CPU BOX

M9401

MSV1'-B 4K MEMORY IM79441

MSVll-B 4K MEMORY IM79441

DLVll SLU IM79401

REVll-A~~~~~NATOR IM9400-YAI

EMPTY

EMPTY
EXPANDER BOX
MA-0775

Early 16K PDP-11 L03-CA, -CC, -CD, -DA, -DC, -DO Systems
132

PDP-11L03
A

-.l

KD11-F PROCESSOR IM72641

KWV11-A PROGRAMMABLE REAL TIME CLOCK IM79521

DRV11 PLU IM79411

IM9400-YEI

DLVll SLU IM79401
RXV11-A ~N~:~~ACE IM79461

~~L_X~

BCV1B

CPU BOX

..L

IM9401 I

MSVll-B 4K MEMORY IM79441

MSV11-B 4K MEMORY (M79441

AAVll-A D/A CONVERTER (A60011
EMPTY

REVll-A

~~~~NATOR(M9400-YAI

EXPANDER BOX
MA-0776

Early 16K PDP-11 L03-HA, -HC, -HD, -JA, -JC, -JD Systems
A

KDll-F PROCESSOR IM72641

KWVll-A PROGRAMMABLE REAL TIME CLOCK (M79621

ADVll-A D/A CONVERTER IA60011

IM9400-YEI

~05L_~

BCV1B

RXVll-A

~N~:~~ACE IM79461

CPU BOX

.l
1

I
DLVll SLU (M79401

IM94011

MSV11-CD 16K MEMORY IM7955-YDI

REVll-A ~~~~NATOR IM9400-YAI

EMPTY

EMPTY
EXPANDER BOX
MA-0777

Early 20K PDP-11 L03-CA, -CC, -CD, -DA, -DC, -DD Systems
133

PDP-11L03

KD11·F PROCESSOR (M72641

KWV11·A PROGRAMMABLE REAL TIME CLOCK (M7952)

AAV11·A AID CONVERTER (A0121
(M9400·YEI

BC05L_X~

BCV1B

RXV11·A

~~~::~ACE (M79461

CPU BOX

I
1

DLV11 SLU (M79401

(M94011

MSV11-CD 16K MEMORY (M7955-YDI

DRV11 PLU (M79411

REV11·A ~~~::'NATOR (M940().YAI

EMPTY

EMPTY
EXPANDER BOX
MA-0778

Early 20K POP-11 L03-HA, -HC, -HO, -JA, -JC, -JO Systems

134

11/03-BASED MINC

PDP-11/03-BASED MINC/DECLAB-11 IMINC SYSTEMS

MODULAR INSTRUMENTATION COMPUTER (MINC)
The Modular INstrumentation Computer (MINC) is a real time operating system featuring on-line data storage and BASIC software with graphics, scientific, and laboratory subroutine packages. Each system consists of a
MINC chassis, an RX02 dual floppy disk drive, and a VT 105 terminal
mounted on a roll-around cart. The MINC chassis houses a power supply,
CPU and related modules, and up to eight MINC laboratory options.
The physical components of a MINC system are grouped into two categories: items common to all MINC systems, and those that can be purchased as options either when the system is first acquired or at some later
time as add-ons. Each MINC system is configured to boot on power-up and
halt on BREAK. The figures and tables that follow describe the modules,
specifications, and components.
All PDP-11 /03 MINC systems include the following standard items.
MINC cart, which provides support and transport for:
1. Dual diskette drive (RX02M)
2. MINC chassis (MNCBA) with power supply (H786). This contains:
KD11-NA
MSV11-DD
RXV21
DLV11-J
IBV11-A
BDV11-A

- LSI-11 processor with EIS / FIS
- Memory (64K bytes) single board
- Diskette drive interface
- Four-channel serial ASCII interface
- IEEE bus interface
- Bus terminator / diagnostic / bootstrap module.

3. VT105 terminal with built-in graphics capability.
MINC systems can include some or all of the following lab modules.
Analog-to-digital converter (MNCAD)
Preamplifier (MNCAG)
Dual multiplexer (MNCAM)
Clock (MNCKW)
135

11/03-BASED MINe
Digital-to-analog converter (MNCAA)
Digital input unit (MNCDI)
Digital output unit (MNCDO)
MINC systems can also include:
Dot matrix printer (LA35)
Isolation transformer (MNCIT)
110 baud, 20 mA serial line interface (DLV11-KC).

VT105

TERMINAL POWER
SWITCH

FUSE
(3AG 3 A SLOW BLOW, 250 V)

RX02
FLOPPY DISK

MINC System

136

MNCIT
(WHEN INSTALLED)

11/03-BASED MINe

MINC System Model Designation
System
Requirements

MNC11
-AA -BA

Input Power (V)
Frequency (Hz)

115
60

MNC11Chassis MNC BA
KD 11-NA (M7270)
MSV 11 0 (M8044)
RXV21 (M8029)
IBV11-A (M7954)
BDV11-A (M8012)
MINC Cart
RX02
VT105
LA35

-BC

-BD

-CA

-CC

-CD

115
60
1
AA

115
50
1
AA

230
50

115
60
1
AA/BA

115
60
1

115
50

AA/AC

BID

1
MA
MA

1
MC
MA

1
MD
MB

1
1
MA
MA
HE

1
1
MC
MA
HH
1

1
MC
MB
HS

MNC11-AB
MNCAD
MNCAA
MNCAM
MNCDI
MNCDO
MNCKW
MNCAG

Cable Console Interface
Software Kit (English)
Blank Control Panel
(MNCBL)
• User's options
• • As required to fill MNCBA plus one extra

137

11j03-BASED MINe

IEEE BUS CONNECTOR
(IBV11)

CABLE CONSOLE
INTERFACE
7015790-0-0
OR
1700211 (LATER MODELS)

LINE CORD
(115V)

1700156-0

~J/
~~--=-----I ~~
-

(3) LINE CORD
DEC TO IEC
17001500

POWER
LINE
OUTLET

CABLE RX02
INTERFACE
7015574-0

MINC System Cable Connections

138

11/03-BASED MINe

,...
N
,... N,...
N

~ 0a: 0 ;~ ~:2 :2~ ;

g
:2

iI
::;: ::;:

Q BUS

~ ~

« u«

~ ~ ~
Cl

'--y---'

PDP-11 /03 Module Utilization (MINe)

139

~ ~ ~:2 ;;>!

CO INTERCONNECTIONS

SLOTS 10 THROUGH 31 MINC OPTION
EXPANSION AREA
(SEE MNC11- C SYSTEM)

Q BUS OPTION

EXPANSION
AREA

OECLAB / MINC Specifications

.........

115 V, 50/60 Hz
Receptacle

Plug

5-15R
12-05351

NEMA No. 6-15P
DEC No. 90-08853

RX02

VT105

LA35

MINC
Chassis

RX02

3.75

3.0
2.0

1.75

Plug
Power
Connector

NEMA No. 5-15P
DEC No. 90-089 38
MINC
Chassis·

Amperage
Typical
Maximum

Wattage
Typical
Maximum

500
1200

Btu/Hour
Typical
Maximum
Weight
Kilograms
Pounds

460

300
250

225

34.02
75

16.3
36

230 V, 50 Hz

W
I

Receptacle
6-15R
12-11204

VT105

LA35

1.5

160
300

460

550
1020

225

46.3
102

34.02
75

* Includes MNCBA chassis with MINC lab modules and RX02 and VT 105.

1.0

250
300

160

550
1020

16.3
36

46.3
102

(J)

z
o

11/03-BASED MINe
NOTE
MINe option expansion area Is to be used only for MINe lab
module add-ons. No Qbus add-ons should be Inserted in this
expansion area. No backplane expansion of the MINe system
is possible. All Qbus add-ons must be inserted in either slot 5
or 6 (A and B only for double-height options).

System-Level Diagnostics
Two diagnostic chains are contained on the diagnostic floppy for system
troubleshooting. The diagnostic chain MINC 11.CCC provides the required
diagnostics for testing the CPU and related modules including the BDV 11,
the VT105 option, and MINC lab modules. This chain requires turnaround
connectors on SLU 0, SLU 1, SLU 2. For detailed operational information,
refer to Book 7, Working with MINe Devices, AA-D572A-TC. The contents of
file MINC11.CCC is as follows.
R VMNF??I 1
R VKAA??I 1
R VKAB??I 1
R VKAC??I 1
R VKAL??I 1
R VIBB??I 1
R VDLA?? 11
R VMNC??I 1
R VMNB??I 1
R VMNE??I 1
R VMND??I 1
R VMNA??I 1
R ZVTN??I 1
R VMNG??I 1

MINC-AA option sizer program
CPU test
Extended instruction test
Floating pOint instruction set test
Traps test
IBV11 test
DLV11-J test
Clock test
MNCDI test
MNCOO (digital out) diagnostic
DI A test
AID test
VT105 test
Termination program

The second diagnostic chain MNC 11.CCC provides the required diagnostics for performing a quick check of the MINC lab modules only. The contents of file MNC 11.CC are listed below.
R VMNF??I 1
R VMNC??I 1
R VMNB??I 1
R VMNE??I 1
R VMND??I 1
R VMNA??I 1
R VMNG??I 1

Startup I sizer program
Floating point instruction set test
MNCDI test
MNCDO test
DI A test
AID test
Termination program

Both programs are stored on the MINC diagnostic disk, available from the
Software Distribution Center (SDC).
Kit No.

ZJ281 - RZ (hard-copy documents)
ZJ281 - PX (RX02 floppy)
ZJ281 - RX (hard-copy I RX02 floppy kit)
141

11/03-BASED MINe
Modules In the Basic System
MNC11-AA (115 V, 60 Hz) and MNC11-AB (230 V, 50 Hz)

Processor KD11-NA (M7270)
With Extended Instruction Set / Floating Point Instruction Set (KEV 11-A, 23003B5)
Jumper W 1 installed - crystal clock
Jumper W3 removed - enable event line
Jumper W6 installed - } ower-u to 173000 (BDV 11)
Jumper W5 removed - p
p

Memory - MSV11-DD (M8044)
64K byte MaS RAM without parity
On-board memory refresh
Jumper configuration

Jumper

Jumper
State

Pin 1 to 3
Pin 1 to 2

OUT}
IN

Enable 2K I/O page option

Enable normal system power (+ 5 V)

Enable normal system power (+ 12 V)

OUT

Disable battery power (+ 12 V)

OUT

Disable battery power (+ 5 V)

Pin 10 to 14
Pin 16 to 15

IN
IN

S 1 through S5

}

Function Implemented

Select memory size of 64K bytes
Starting address bank 0

142

11j03-BASED MINe
Serial Line Interface - DLV11-J (M8043)
Number of serial lines: 4
Factory-set address and vector switches

Device

Address Vector

Baud
Rate

Console
SLU 2
SLU 1
SLU 0

777560
776520
776510
776500

9600
300
1200
9600

60
320
310
300

CONSOLE

MINC Terminal Distribution Panel
143

11/03-BASED MINe
Bus Terminator IDlagnostlc/Bootstrap BDV11-A (M8012)
Diagnostic / bootstrap conditions are factory-selected using switch packs.
Switch A
(E15)

RX02
Bootstrap

A1
A2
A3
A4
A5
A6
A7
A8

ON
ON
OFF
OFF
OFF
ON
OFF
OFF

Switch B
(E21)

RX02
Bootstrap

81
82
83
84
85

OFF
OFF
OFF
OFF
ON

IEEE Bus Interface - IBV11-A (M7954)
Address and vector switch settings:
Address 171420
82-1,4 and 5 = ON only

Vector 420
8-1 and 5 = ON only

Floppy Disk Interface - RXV21 (M8029)
Address and vector switch settings:
Address 177170
A7 and A8 = OUT only

Vector 264
V3, V6 and V7 = OUT only

144

DECLAB-11/MNC
DECLAB-11/MNC SYSTEM
The DECLAB-11 / MNC is a real time operating system featuring on-line data
storage, and FORTRAN software with graphics, scientific, and laboratory
subroutine packages. Each system contains as its main components an
MNC chassis, dual RL01 disk drives, and a terminal (VT105 or LA36). The
MNC chassis houses a power supply, CPU, and related modules, and up to
eight MNC- series options.
The physical components of the DECLAB system are grouped into two categories: items common to all MNC systems, and those that can be purchased as options, either when the system is first acquired or at some later
time. Each DECLAB system is configured to boot on power-up and halt on
BREAK. The figures and tables that follow describe the modules, specifications, and components.
All DECLAB systems include the following standard items.
Mass storage device containing two RLO 1 disk drives
MNC chassis (MNCBA) with power supply (H786). This contains:
KD11-NA
MSV11-DD
RLV11
DLV11-J
IBV11-A
BDV11-A

LSI-11 processor with EIS / FIS
Memory (32K word) single board
Controller (disk)
Four-channel serial ASCII interface
IEEE bus interface (optional)
Bus terminator / diagnostic/bootstrap module.

VT105 terminal with built-in graphics capability
DECLAB systems can include some or all of the following lab modules.
Analog-to-digital converter (MNCAD)
Preamplifier (MNCAG)
Dual multiplexer (MNCAM)
Clock (MNCKW)
Digital-to-analog converter (MNCAA)
Digital input unit (MNCDI)
Digital output unit (MNCDO)
DECLAB systems can also include:
Dot matrix printer (LAV 11 + LA 180 or LA35)
110 baud, 20 rnA serial line interface (DLV11-KC).

145

DECLAB-11/MNC
MNC CHASSIS

~~!!,!!!!!!~L??/,\ rr~ ;;=~:~~~ :--~'jijji;~,,",
II
I:
I'
I,
I,

11...... EXPANSION I'''''::,~_>-=~~:'-L...J
I: CABINET
I
- - ~
II (H9612)
DISK DRIVE
: :- - _ _
I UNIT 0 CJ
II
----J~
I,

DISK DRIVE
UNIT 1

II
11--ll
__

MASS STORAGE
DEVICE CABINET
H9610

VIDEO DISPLAY TERMINAL
MA·228'

DECLAB-11 / MNC System with Optional Units
12 A 115 VAC FAST BLOW FUSE
50/60 HZ
10 A
ACINPuT
CABLE FROM
VT100 OR VT105
115/230 VAC
INPUT

VT105 OR
LA36/LA3B
CONSOLE
CABLE
CABLE FROM
RLVll, SLOT 3

AC POWER
CABLE TO
MNCBA CHASSIS

DD~

MAX ACOUT
3A@230V
6A@115V

DECLAB-11 / MNC Cable Connections
146

DECLAB-11/MNC

DECLAB-11/MNC System Model Designation
System
Requirements

MNC11
-0

Input Power (V)
115
Frequency (Hz)
60
Cabinet I Power Controller (H961 0)
MNC11Chassis (MNCBA)
KD 11-NA (M7270)
MSV 11 D (M8044)
Dl V 11-J (M8043)
IBV 11-A (M7954)
BDV11-A (M8012)
RlV11- (M8013)
RlV11- (M8014)
lAV11-lA 180 Printer
VT105 Terminal
lA36
RlO 1 Disk Drive

-J

-K

-L

115
60

BB/BC
D

MA
HE
2

MNC11-AD
MNC11-AA
MNC11-AM
MNC11-DI
MNC11-DO
MNC11-KW
MNC11-AG
Cable Console Interface
Software Kit (English)
Blank Control Panel (BNCBl)
Installation Kit (MNCIK)
* User's options
• • As required to fill MNCBA plus one extra

147

DECLAB-11/MNC
33

--------------------------------------- -

::;

OBUS

CD INTERCONNECTIONS

- -- -- ------------------------------------ - -

;
g

SLOTS 10 THROUGH 31 DECLAB-MNC OPTION
EXPANSION AREA (FRONT VIEW)
DECLAB MODULE UTI LlZATION
• REPLACE THESE OPTIONS
WHEN NOT REOUI RED WITH
MB659 GRANT CARD OR

G7272

PDP-11 103 DECLAB Module Utilization

NOTE
DECLAB-MNC option expansion area Is to be used only for
MNC-serles module add-ons. No Qbus add-ons should be installed In this expansion area. No backplane expansion of the
MNC system Is possible.
System-Level Diagnostics
Two diagnostic chain files are contained on the RLO 1 diagnostic disk for
system troubleshooting. The diagnostic chain MNC 11 A.CCC provides the
required diagnostics for testing the CPU and related modules and MNCseries modules. This program does not test the BDV 11 or VT 105 options.
The contents of file MNC11A.CCC are as follows.
R VMNF??I 1
R VKAA??I 1
R VKAB??I 1
R VKAC??I 1
R VKAL??I 1

MINC-11 option sizer program
CPU test
Extended instruction test
Floating point instruction set test
Traps test
148

DECLAB-11/MNC
R VIBB??I 1
R VDLA?? 11
R VMNC??I 1
R VMNB??I 1
R VMNE??I 1
R VMND??I 1
R VMNA??I 1
R ZVTN??I 1
R VMNG??I 1

IBV11 test
DLV11-J test
Clock test
MNCDI test
MNCOO (digital out) diagnostic
AID test
VT105 test
Terminator program

The second diagnostic chain MNC11.CCC provides the required diagnostics for performing a quick check of the MNC-series modules only. The contents of file MNC 11.CCC are as follows.
R VMNF??I 1
R VMNC??I 1
R VMNB??I 1
R VMNE??I 1
R VMND??I 1
R VMNA??I 1
R VMNG??I 1

Start-up I sizer program
Floating point instruction set test
MNCDI test
MNCDO test
DI A test
AI D test
Termination program

Both programs are stored on the MNC diagnostic disk, Software Distribution Center (SDC) kit no. AX-E380EMC.

Modules in the Basic System
MNC11-AA (115 V, 60 Hz) and MNC11-AB (230 V, 50 Hz)

Processor KD 11-NA (M7270)
With Extended Instruction Set I Floating Point Instruction Set (KEV 11-A 23003B5).
Jumper W 1 installed - crystal clock
Jumper W3 removed - enable event line
Jumper W6 installed - }
Jumper W5 removed _ power-up to 173000

Memory - MSV11-DD (M8044)
64K byte MOS RAM without parity
On-board memory refresh
Jumper configuration
149

DECLAB-11/MNC

Jumper

Jumper
State

Pin 1 to 3
Pin 1 to 2

OUT
IN

Enable 2K 110 page option

Enable normal system power (+ 5 V)

Enable normal system power (+ 12 V)

OUT

Disable battery power (+ 12 V)

OUT

Disable battery power (+ 5 V)

Pin 10 to 14
Pin 16 to 15

IN
IN

Select memory size of 64K bytes

S 1 through S5

Starting address = bank 0

Function Implemented

Serial Line Interface - DLV11-J (M8043)
Number of serial lines: 4
Factory-set address and vector switches

Device

Address Vector

Baud
Rate

Console
SLU 2
SLU 1
SLU 0

777560
776520
776510
776500

300
1200
9600

60
320
310
300

9600/300·

·Varies depending on type of terminal.

150

OECLAB System Specifications
115 V, 50/60 Hz

Power
Connector

Plug

Receptacle

Plug

Receptacle

NEMA No. 5-15P
DEC No. 90-08938

5-15R
12-05351

NEMA No. 6-15P
DEC No. 90-08853

6-15R
12-11204

VT105

LA36

OECLAB/
MNC
System

RL01

VT105

LA36

2.0

2.5

1.5

1.0

160
300

500
1200

150
200

150

160
300

OECLAB/
MINC
System·

RL01

Amperage
Typical
Maximum

3.5

Wattage
Typical
Maximum

500
1200

150
200

3.0

150

Btu/Hour
Typical
Maximum
Weight
Kilograms
Pounds

230 V, 50 Hz

550
1020

600

550
1020

or-

......

DJ
I

134
295

34.02
75

16.3
36

46.3
102

134
295

34.02
75

16.3
36

46.3
102

...........

·Includes MNCBA chassis with MNC-series module and two RLO 1 drives.

DECLAB-11/MNC

CONSOLE

MINe Terminal Distribution Panel

152

DECLAB-11/MNC
Bus Terminator/Diagnostic/Bootstrap BDV11-A (M8012)
Switch A
(E15)

RL01
Bootstrap

A1
A2
A3
A4
A5
A6
A7
A8

ON
ON
OFF
OFF
OFF
OFF
ON
OFF

Switch B
(E22)

RL01
Bootstrap

81
82
83
84
85

OFF
OFF
OFF
OFF
ON

IEEE Bus Interface - IBV11-A (M7954) (Optional)
Address and vector switch settings:
Address 171420
82-1,4 and 5 = ON only

Vector 420
81-1 and 5 = ON only

Disk Interface - RLV11 (M8014, M8013)
Address and vector switch settings on M80 14 bus module:
Address 174400

Vector 160

153

DECLAB-11/MNC

MBO 14 Switch Setting
Switch

Position

Function

Bus Address
(174400)

ON
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF

A 12 (MSB)
A 11
A10
A09

Vector Switch OFF
(160)
OFF
ON
ON
ON
OFF
OFF

AOa
A07
A06
A05
A04
A03 (LSB)

va (MSB)
V7

V6
V5
V4
V3
V2 (LSB)

NOTE
Additional MINC/DECLAB Information can be found in the following manuals.
MINCIDECLAB Service Manual EK-MNC11-SV
DECLAB-11IMNC User's Guide EK-MNC11-UG

154

11/23-BASED MINC

PDP-11/23-BASED MINC/DECLAB-11 IMINC SYSTEMS
MINC
The Modular INstrumentation Computer (MINC) is a real time operating system featuring on-line data storage, and BASIC software with graphics, scientific, and laboratory subroutine packages. Each system consists of a
MINC chassis, an RX02 dual floppy disk drive, and a VT105 terminal
mounted on a roll-around cart. The MINC chassis houses a power supply,
CPU and related modules, and up to eight MINC laboratory options.
The physical components of a MINC system are grouped into two categories: items common to all MINC systems, and those that can be purchased as options, either when the system is first acquired or at some later
time as add-ons. Each MINC system is configured to boot on power-up and
halt on BREAK. The figures and tables that follow describe the modules,
specifications, and components.
All PDP-11 123 MINC systems include the following standard items.
MINC cart, which provides support and transport for:
Dual diskette drive (RX02M)
MINC chassis (MNCBA) with power supply (H786). This contains:
KDF11-AB
MSV11-DD
RXV21
DLV11-J
IBV11-A
BDV11-A

LSI-11 processor with memory management EIS I FIS
Memory (64K words) on two modules
Diskette drive interface
Four-channel serial ASCII interface
IEEE bus interface
Bus terminator I diagnostic Ibootstrap module.

VT105 terminal with built-in graphics capability.
MINC systems can include some or all of the following lab modules.
Analog-to-digital converter (MNCAD)
Preamplifier (MNCAG)
Dual multiplexer (MNCAM)
Clock (MNCKW)
Digital-to-analog converter (MNCAA)
Digital input unit (MNCDI)
Digital output unit (MNCDO)
155

11/23-BASED MINe
MINC systems can also include:
Dot matrix printer (LA35)
Isolation transformer (MNCIT)
110 baud, 20 rnA serial line interface (DLV11-KC).

VT105

MASTER SYSTEM
11t---r-+---CI RCUIT BREAKER

TERMINAL POWER
SWITCH

FUSE
(3AG 3 A SLOW BLOW, 250 V)

RX02
FLOPPY DISK

MINC System

156

MNCIT
(WHEN INSTALLED)

11/23-BASED MINe

MINC System Model Designation
System
Requirements

MNCFA
-AA -BA

Input Power (V)
Frequency (Hz)

115
60

MNCFAChassis MNC BA
KDF11-AB (M8186)
MSV 11 D (M8044)
RXV21 (M8029IBV 11-A (M7954)
BDV11-A (M8012)
MINC Cart
RX02
VT105
LA35

-BC

-BD

-CA

-CC

-CD

115
60
1
AA

115
50
1
AA

230
50

115
60
1
AA/BA

115
60
1
AA/AC

115
50

1
MA
MA

1
MC
MA

1
MD
MB

1
MA
MA
HE

1
MC
MA
HH

1
MC
MB
HS

BID

1
2

MNCFA-AB
MNCAD
MNCAA
MNCAM
MNCDI
MNCDO
MNCKW
MNCAG

Cable Console Interface 1
Software Kit (English)
Blank Control Panel
(MNCBL)
• User's options
• • As required to fill MNCBA plus one extra

QJV35-AX (RX02) diagnostic package supplied

157

11/23-BASED MINe

IEEE BUS CONNECTOR
(IBV11)

CABLE CONSOLE
INTERFACE

7015790-0-0

(3) LINE CORD
DEC TO IEC

1700150-0

POWER
LINE
OUTLET

INTERFACE

7015574-0

MINC System Cable Connections

158

~ ~

<.:J

'<t '<t <0
II: ~ en
N
'<t '<t <Xl
0
0
0
0
~ <Xl <Xl <Xl OJ
en
en
:2 L!) L!) :2 :2 :2 :2 :2
(')

'<t

0
<Xl

<Xl

II:

<0
<Xl

:2 :2
OBUS

--- -- -- --- ----- ----- ----- ----- ----- ----- 0
II:

0
II:

« «
u

I-

z z

;;: «
« ;;: >
II:
II:

....J

C1l
CO

<.:J

«
CD INTER·
CONNECTIONS

;;:
0

SLOTS 10 THROUGH 31 MINC OPTION
EXPANSION AREA
(SEE MNC11· C SYSTEM)
'NOTE:

MUST BE AT CS REVISION 'E' OR HIGHER.

"NOTE:

MUST BE AT CS REVISION 'E1' OR HIGHER.

PDP-11 V23 MINC Module Configuration

a BUS OPTION
EXPANSION
AREA

(/)

9 9
N ;;: ;;:

II:

:2 :2

co
~

u..
0

MINC System Specifications

..........

115 V, 50/60 Hz

230 V, 50 Hz

~
I

Plug

Receptacle

Plug

Receptacle

CIJ

NEMA No. 5-15P
DEC No. 90-08938

5-15R
12-05351

MINC
Chassis'

RX02

VT105

Amperage
Typical
Maximum

4.0

Wattage
Typical
Maximum

500
1200

460

Power
Connector

NEMA No. 6-15P
DEC No. 90-08853

6-15R
12-11204

LA35

MINC
Chassis

RX02

VT105

2.0

3.0

LA35

1.5
1.0

Btu/Hour
Typical
Maximum
Weight
Kilograms
Pounds

250
300

225

16.3
36

160
300

460

550
1020

225

46.3
102

'Includes MNCBA chassis with MINC lab modules and RX02 and VT 105.

250
300

160

550
1020

16.3
36

46.3
102

z
o

11/23-BASED MINe
NOTE
MINe option expansion area Is to be used only for MINe lab
module add-ons. No Qbus add-ons should be inserted in this
expansion area. No backplane expansion of the MINe system
is possible. All Qbus add-ons must be Inserted in either slot 5
or 6 (A and B only for double-height options).
System-Level Diagnostics
Two diagnostic chain files are contained on the diagnostic floppy for system troubleshooting. The diagnostic chain MNC 11 F .CCC provides the required diagnostics for testing the CPU and related modules including the
BDV11, the VT105 option, and MINC lab modules. This chain requires turnaround connectors on SLUs 0, 1, and 2. For detailed operational information, refer to Book 7 of Working with MINe Devices, AA-D572A-TC. The contents of file MNC11F.CCC are as follows.
R VMNF??I 1
R JKDA?? 11
R JKDB??I 1
R JKDC??I 1
R JKDD??I 1
R VIBB??I 1
R VDLA?? 11
R VMNC??I 1
R VMNB??I 1
R VMNE??I 1
R VMND??I 1
R VMNA??I 1
R ZVTN??I 1
R VMNG??I 1

MINC-11 option sizer program
CPU test
Extended instruction test
Floating point instruction set test
Traps test
IBV11 test
DLV11-J test
Clock test
MNCDI test
MNCOO (digital out) diagnostic
DI A test
AID test
VT105 test
Termination program

The second diagnostic chain MNCFA.CCC provides the required diagnostics for performing a quick check of the MINC lab modules only. The contents of file MNCFA.CC are listed below.
R VMNF??I 1
R VMNC??I 1
R VMNB??I 1
R VMNE??I 1
R VMND??I 1
R VMNA??I 1
R VMNG??I 1

Start-up I sizer program
Floating point instruction set test
MNCDI test
MNCDO test
DI A test
AID test
Termination program

Both programs are stored on the MINC diagnostic disk, available from the
Software Distribution Center (SDC).
Kit No.

QJV35 - RZ (hard-copy documents)
QJV35 - AX (RX02 floppy)
ZJ281 - RX (hard-copy / RX02 floppy kit)
161

11/23-BASED MINe
Modules in the Basic System
MNC11F-AA (115 V, 60 Hz) and MNC11F-AB (230 V, 50 Hz)

Processor (KDF11-AB) M8186
With warm floating pOint instruction set (KEF 11-A) and memory management.
Jumper W 1 installed
Jumper W4 removed
Jumper W5 removed
Jumper W6 installed
Jumper W7 removed
Jumper wa installed

- crystal clock
- enable event line

= } power-up to 773000 (BDV 11)
- enter console ODT on HALT
- power-up with PC at 173000a (bootstrap)

Memory - MSV11-DD (M8044-D)
64K bytes MaS RAM without parity
On-board memory refresh
Jumper configuration

Jumper

Jumper
State

Pin 1 to 3
Pin 1 to 2

IN
}
OUT

Disable memory I/O page options

Enable normal system power (+ 5 V)

Enable normal system power (+ 12 V)

OUT

Disable battery power (+ 12 V)

OUT

Disable battery power (+ 5 V)

Pin 10 to 14
Pin 16 to 15

IN
IN

} Select memory size of 64K bytes

Function Implemented

162

11/23-BASED MINe

MSV11-DDSwitch Settings
Position
1st Module
Switch Bank 0-7

Position
2nd Module
Bank 10-17

Position
3rd Module
Bank 20-27

Position
4th Module
Bank 30-37

8-1

OFF

8-2

OFF

8-3

8-4

8-5

Serial Line Interface - DLV11-J (M8043)
Must be at C8 revision "E" or higher.
Number of serial lines: 4
Factory-set address and vector switches

Device

Address

Vector

Baud
Rate

Console
8LU 2
8LU 1
8LU 0

777560
776520
776510
776500

60
320
310
300

9600
300
1200
9600

163

11/23-BASED MINe

CONSOLE

MINe Terminal Distribution Panel

164

11/23-BASED MINe
Bus Terminator/Diagnostic/Bootstrap BDV11-A (M8012)
Diagnostic/bootstrap conditions are factory-selected using switch packs.

Switch A
(E15)

RX02
Bootstrap

A1
A2
A3
A4
A5
A6
A7
A8

ON
ON
OFF
OFF
OFF
ON
OFF
OFF

Switch B
(E21)

RX02
Bootstrap

81
82
83
84
85

OFF
OFF
OFF
OFF
ON

Floppy Disk Interface - RXV21 (M8029)

A12

Wll

All

Al0

I I I I I I I I I

Wl0

I I I I I I I I
0

W18

W17

W16

W15

W14

W13

W12

1= JUMPER IN
0= JUMPER OUT

RXV21 Address and Switch Settings

165

DEVICE
ADDRESS
77717X

VECTOR
264

DECLAB-11/MNC 11/23
DECLAB-11/MNC PDP-11 123-BASED SYSTEM
The DECLAB-11 / MNC is a real time operating system featuring on-line data
storage, and FORTRAN software with graphics, scientific, and laboratory
subroutine packages. Each system contains as its main components, an
MNC chassis, dual RL01 disk drives, and a terminal (VT105 or LA36). The
MNC chassis houses a power supply, CPU, and related modules, and up to
eight MNC- series option.
The physical components of the DECLAB system are grouped into two categories: items common to all MNC systems, and those that can be purchased as options, either when the system is first acquired or at some later
time as add-ons. Each DECLAB system is configured to boot on power-up
and halt on BREAK. The figures and tables that follow describe the modules, specifications, and components.
All DECLAB systems include the following standard items.
Mass storage device containing two RLO 1 disk drives
MNC chassis (MNCBA) with power supply (H786). This contains:
KDF11-AB

MSV11-DD
RLV11
DLV11-J
IBV11-A
BDV11-A

LSI-11 processor with memory management, floating
pOint (KEF 11-A)
Memory (128K byte: two modules)
Controller (disk)
Four-channel serial ASCII interface
IEEE bus interface (optional)
Bus terminator / diagnostic / bootstrap module.

VT105 terminal with built-in graphics capability

DECLAB systems can include some or all of the following lab modules.
Analog-to-digital converter (MNCAD)
Preamplifier (MNCAG)
Dual multiplexer (MNCAM)
Clock (MNCKW)
Digital-to-analog converter (MNCAA)
Digital input unit (MNCDI)
Digital output unit (MNCDO)

DECLAB systems can also include:
Dot matrix printer (LAV 11 + LA 180 or LA35)
110 baud, 20 rnA serial line interface (DLV11-KC).
166

DECLAB-11/MNC 11/23
MNC CHASSIS

~~~!--0'\

r,::"-; ~ --~ ~_~---r - ~~~~~~

IIII

I:
II

I'
I 1.-;,:/~~,~-=_~~-----J

L. EXPANSION

I:
II

CABINET
(H9612)

c::::J '

DISK DRIVE

l:-__ - - ---J UNIT 0 [:]
II
I

II
II
11---

DISK DRIVE
UNIT 1

ll __

---

MASS STORAGE
DEVICE CABINET
H9610

VIDEO DISPLAY TERMINAL

DECLAB-11 / MNC System with Optional Units
12 A 115 VAC
50/60 HZ

FAST BLOW FUSE
10 A
ACINPUT
CABLE FROM
VT100 OR VT105

115/230 VAC
INPUT
VT105 OR
LA36/LA38
CONSOLE
CABLE
CABLE FROM
RLV11.SLOT3

AC POWER
CABLE TO
MNCBA CHASSIS

DO[§]

DD~

MAX AC OUT
3A@230V
6A@115 V

DECLAB-11 / MNC Cable Connections
167

DECLAB-11/MNC 11/23

DECLAB-11/MNC System Model Designation

System
Requirements

MNCFA
-K
-J

Input Power (V)
Frequency (Hz)
Cabinet I Power Controller (H961 0)
MNC11Chassis (MNCBA)
KDF 11-AB (M8186)
MSV11D (M8044)
Dl V 11-J (M8043)
IBV11-A (M7954)
BDV11-A (M8012)
RlV11- (M8013)
RLV 11- (M80 14)

115
60
BB/BC
D

1
2
1

lAV 11-lA 180 Printer
VT105 Terminal
lA36
RlO 1 Disk Drive
QJV35-AR Diagnostic Package (RlO 1)
MNC11-F-AD
MNC11-F-AA
MNC11-F-AM
MNC11-F-DI
MNC11-F-DO
MNC11-F-KW
MNC11-F-AG
Cable Console Interface
Software Kit (English)
Blank Control Panel (BNCBl)
Installation Kit (MNCIK)
• User's options
• • As required to fill MNCFA

168

MA
HE
2
1

2
1

DECLAB-11/MNC 11/23
33

3' 2

g
::;;

OBUS

-------------------------------------

-- -

-- ---

CD INTER·
~
CONNECTIONS:; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• NOTE: MUST BE AT CS REVISION
'E' OR HIGHER

SLOTS 10 THROUGH 31 DECLAB·MNC OPTION
EXPANSION AREA (FRONT VIEW)
DECLAB MODULE UTILIZATION

•• REPLACE THESE OPTIONS
WHEN NOT REOUI RED WITH
MB659 GRANT CARD OR
G7272 .

PDP-11 123 DECLAB Module Configuration

NOTE
DECLAB-11/MNC option expansion area Is to be used only for
MNC-serles module add-ons. No Qbus add-ons should be installed in this expansion area. No backplane expansion of the
MNC system is possible.
System-Level Diagnostics
Two diagnostic chain files are contained on the RLO 1 diagnostic disk for
system troubleshooting. The diagnostic chain MNC11F.CCC provides the
required diagnostics for testing the CPU and related modules and MNCseries modules. This program does not test the BDV 11 or VT 105 options.
This chain requires turnaround connectors on SLUs 0, 1, and 2. For detailed operational information, refer to Book 7 of Working with MINe Devices, AA-D572A-TC. The contents of file MNC11F.CCC are as follows.
R VMNF??I 1
R JKDA??I 1
R JKDB??I 1

MINC-11 option sizer program
CPU test
Extended instruction set
169

DECLAB-11/MNC 11/23
R JKDC??/1
R JKDD??/1
R VIBB??/1
R VDLA??/1
R VMNC??/1
R VMNB??/1
R VMNE??/1
R VMND??/1
R VMNA??/1
R ZVTN??/1
R VMNG??/1

Floating point instruction set test
Traps test
IBV11 test
DLV11-J test
Clock test
MNCDI test
MNCDO test (digital out)
01 A test
AID test
VT105 test
Termination program

The second diagnostic chain MNC11F.CCC provides the required diagnostics for performing a quick check of the MNC-series modules only. The contents of file MNC 11 F .CCC are as follows.
Start-up I sizer program
Floating point instruction set test
MNCDI test
MNCDO test
01 A test
AID test
Termination program

R VMNF??/1
R VMNC??/1
R VMNB??/1
R VMNE??/1
R VMND??/1
R VMNA??/1
R VMNG??/1

Both programs are stored on the MNC diagnostic disk, Software Distribution Center (SOC) kit no. BA-FO 18· -MC.
LOCAL POWER

POWER CONTROLLER
PLUG

RECEPTACLE
871-B

230V 10A
50/60HZ

NEMA # 6-15P
DEC # 90-08853

6-15R
12-11204

871-C

115V 20A
50/60HZ

HUBBELL # 5366-C
DEC # 12-15183

@
o IP

NEMA# 5-20R
12-12265
MR-5383

DECLAB/MINC and MINC RL01 Add-On Power Requirements
170

Specifications
115 V, 50/60 Hz

Power
Connector

230 V, 50 Hz

Plug

Receptacle

Plug

Receptacle

NEMA No. 5-15P
DEC No. 90-089 38

5-15R
12-05351

NEMA No. 6-15P
DEC No. 90-08853

6-15R
12-11204

VT105

DECLAB/
MNC
System

VT105

DECLAB/
MINC
System·

RL01

Amperage
Typical
Maximum

3.5

Wattage
Typical
Maximum

500
1200

150
200

LA36

RL01

3.0

250
300

LA36

1.5
2.0

2.5

160
300

150
200

1.0

250
300

160
300

Btu/Hour
Typical
Maximum

600

550
1-020

600

550
1020

~
~

Weight
Kilograms
Pounds

134
295

34.02
75

16.3
36

46.3
102

134
295

• Includes MNCBA chassis with MNC-series module and two RLO 1 drives.

34.02
75

16.3
36

46.3
102

z
o

DECLAB-11/MNC 11/23
Modules Included in the Basic PDP-11 123 System
MNC11F-AA (115 V, 60 Hz) and MNC11F-AB (230 V, 50 Hz)

Processor (KDF11-AB) M8186
With warm floating point instruction set (KEF 11-A) and memory management.
Jumper W 1 installed
Jumper W4 removed
Jumper W5 removed
Jumper W6 installed
Jumper W7 removed
Jumper W8 installed

- crystal clock
- enable event line

= } power-up to 773000 (BDV 11)
- enter console ODT on HALT
- power-up with PC at 1730008 (bootstrap)

Memory - MSV11-DD (M8044)
64K byte MaS RAM (without parity)
On-board memory refresh
Jumper configuration

Jumper

Jumper
State

Function Implemented

Pin 1 to 3
Pin 1 to 2

IN
}
OUT

Disable memory I/O page option

Enable normal system power (+ 5 V)

Enable normal system power (+ 12 V)

OUT

Disable battery power (+ 12 V)

OUT

Disable battery power (+ 5 V)

Pin 10 to 14
Pin 16 to 15

IN
IN

}

Select memory size of 64K bytes

172

DECLAB-11/MNC 11/23

MSV11-DD Switch Settings
Position
1st Module
Switch Bank 0-7

Position
2nd Module
Bank 10-17

Position
3rd Module
Bank 20-27

Position
4th Module
Bank 30-37

8-1

OFF

8-2

OFF

8-3

8-4

8-5

Serla! Line Interface - DLV11-J (M8043)
Must be at C8 revision "E" or higher.
Number of serial lines: 4
Factory-set address and vector switches

Device

Address

Vector

Baud
Rate

Console
8LU 2
8LU 1
8LUO

777560
776520
776510
776500

60
320
310
300

9600
300
1200
9600

173

DECLAB-11/MNC 11/23

CONSOLE

MINe Terminal Distribution Panel
Bus Terminator/Diagnostic/Bootstrap BDV11-A (M8012)
Diagnostic I bootstrap conditions are factory-selected using switch packs.
RL01
Bootstrap
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF

Switch A
(E15)
A1
A2
A3
A4
A5
A6
A7
A7
A8

174

DECLAB-11/MNC 11/23
Switch B
(E21)

Rl01
Bootstrap

B1
B2
B3
B4
B5

OFF
OFF
OFF
OFF
ON

IEEE Bus Interface - IBV11-A (M7954) optional
Address and vector switch settings:
Address 171420
S2-1, 4 and 5 = ON only

Vector 420
S-1 and 5 = ON only

Disk Interface - RlV11 (M8013, M8014)
Address and vector switch settings as shown in the following.

M8014 Switch Settings
Switch

Position

Function

Bus Address
(174400)

ON
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF

A 12 (MSB)
A 11
A10
A09

Vector Switch OFF
(160)
OFF
ON
ON
ON
OFF
OFF

175

AOa
A07
A06
A05
A04
A03 (lSB)

va (MSB)
V7
V6
V5
V4
V3
V2 (lSB)

CPU/OPTIONS

GENERAL MODULE INFORMATION

GENERAL MODULE INFORMATION
This section lists LSI-11 modules alphanumerically by module number. The
tables below list modules by option designation for cross-referencing. All
modules are (or will be) covered in Microcomputer Processor Handbook,
EB-20175-20, (CPUs and memories) or the Minicomputer Interfaces Handbook, EB-18451-20.
The following conventions are used in presenting module data.

Registers
The base address is listed first. This is normally the address of a control
status register. Abbreviations containing "CS" or "CSR" are for control
status registers. Abbreviations containing "DB," "DBR," or "BUF" refer to
data buffer registers.

Switches
Switches are labeled "S 1, S2, S3, ... " although they may be located in the
same DIP switch pack. Rocker switch states are selected by pressing the
side closest to the label of the state desired. For example, to select the ON
position, press the side of the rocker closest to the edge of the switch on
which "ON" is printed; disregard the red line on the end of the rocker.

Jumpers
"I" indicates that a jumper is inserted. "R" indicates that it is removed.
"X" indicates a "don't care" condition. Location drawings show jumpers
installed, for clarity, although they may not actually be installed for the
standard configuration. Tables define the jumper states. Jumpers are
shown as a solid line if they are normally installed.

NOTE
Jumpers are not always installed for a 1 and removed for a 0;
on some modules the reverse is true. See Appendix A for
XXDP + diagnostic names, functions, and multimedia assignments.
179

A012

A012
ADV11-A ANALOG-TO-DIGITAL CONVERTER

Amps
+5
2.0

Bus Loads
+12
0.45

AC
3.25

DC
1

Cables

BC04Z
BC04R
BCV11
BC08R used with H322

Standard Addresses
CSR
DBR

170400
170402

Vectors

AID Done
Error

400
404

Diagnostic Programs
Refer to Appendix A.

NOTE
CVADA?? and CXADC?? tests require wraparound connector
PN 70-12894.

Related Documentation
ADV11-A, KWV11-A AAV11-A, DRV11 User's Manual (EK-ADV 11-0P)
Field Maintenance Print Set (MPOO 193)
Microcomputer Interfaces Handbook (EB-20 175-20)

180

SI NGLE-ENDED
JUMPER LUGS

ADDRESS
BIT 2 SWITCHES

c~_~~noo
OFFSET-./
ADJ

S2
W3 ](/)
BIT 11

pWcrU
BIT3

VECTOR BITS
SW ITCHES

TAB C
(CLOCK
OVERFLOW
IN)

TAB S
(EXTERNAL START)

~~~N

11-4322

A012
Jumper W3 is inserted for single-ended operation, and removed for quasidifferential operation.

I I I I I I

STANDARD VECTOR
CONFIGURATION
(400)

VECTOR
SWITCH
(:il)

OFF OFF OFF OFF OFF

I t t t ttl 1
8 .......
_____________

CSR ADDRESS FORMAT

111111111010101110101010101010101

I I I I I I I I I I

STANDARD ADDRESS
CONFIGURATION
OFF OFF OFF

(170400)

ON OFF OFF OFF OFF OFF OFF

+ + + + ! ! ! ! ! !

CSR ADDRESS
SWITCH (S2)
•

ERR
INT ENA

1
.

AD
DONE

elK
START
ENA

ID
ENA

ADV 11-A Control/Status Register (CSR)

182

NOT USED

A012
CSR Bit Definition
Bit

Function

A/D Error (read/write) - The A/D Error may be program set or
cleared and is cleared by the processor initialize. It is set by any
of the following:
a.

attempting an external or clock start during the transition
interval

attempting any start during a conversion in progress

failing to read the result of a previous conversion before the
end of the current conversion.

Error Interrupt Enable (read/write) - When set, enables a program interrupt upon an error condition (A/D Error). Interrupt is
generated whenever bits 14 and 15 are set, regardless of which
was set first.

13-12

Not used.

11-8

Multiplexer Address (read/write) - Contain the number of the
current analog input channel being addressed.

A/D Done (read) - Set at the completion of a conversion when
the data buffer is updated. Cleared when the data buffer is read,
and by the processor initialize. If enabled interrupts are requested simultaneously by bits 07 and 15, bit 07 has the higher
priority.

Done Interrupt Enable (read/write) - When set, enables a program interrupt at the completion of a conversion (A/D Done). Interrupt is generated when bit 07 and bit 06 are both set, regardless of sequence.

Clock Start Enable (read/write) - When set, enables conversions to be initiated by an overflow from the clock option.

External Start Enable (read/write) - When set, enables conversions to be initiated by an external signal or through a Schmitt
trigger from the clock option.

10 Enable (read/write) - When set, causes bit 12 of the data buffer register to be loaded to a 1 at the end of any conversion.

183

A012
CSR Bit Definition (Cont)
Bit

Function

Maintenance (read/write) - Loads, when set, all bits of the converted data output equal to multiplexer address LSB (bit 08) at
the completion of the next conversion. Cleared by the processor
initialize. Used for "all Os" and "all 1s" tests of A/D conversion
logic.

Not used.

A/D Start (read/write) - Initiates a conversion when set.
Cleared at the completion of the conversion and by the processor initialize.

VERNIER DIA (WRITE)

I" " "I" I I "I
I . I I . I I . I I . I I . I
• MSB

~~M~S~B

LSB
01

__________________~.__________________~LS~B.

CONVERTED DATA (READ)

ADV 11-A Data Buffer Register (DBR)
DBR Bit Definition
The DBR is actually two separate registers: one read only, the other, write
only.
Bit

Function

Read Only

(Cleared at processor initialize.)

15-13

Not used. Should read as O.

ID (read) - When ID Enable (bit 03) of the CSR has been set,
BDR bit 12 will be loaded to a 1 at the end of conversion.

11-00

Converted Data (read) - These bits contain the results of
the last A/D conversion.

Write Only

(Set to 200 at processor initialize.)

15-08

Not used.

07 -00

Vernier D/ A (write) - These bits provide a programmed offset to the converted value (scaled 1 D/ A LSB = 1/50 A/D
LSB). The hardware initializes this value to 200 (mid-range).
Values greater than 200 make the input voltage appear
more positive.
184

A6001

A6001
AAV11-A DIGITAL-TO-ANALOG CONVERTER

Amps
+5
1.5

Bus Loads
-12 AC
0.4 1.91

Cables

DC
BC04Z
BC04R
BC11V

BC08R used with H322

Standard Addresses
DAC1
DAC2
DAC3
DAC4

170440
170442
170444
170446

Vectors
None. The AAV-11 does not cause interrupts.

Diagnostic Programs
Refer to Appendix A.

Related Documentation
ADV11-A, KWV11-A, AAV 11-A, DRV11 User's Manual (EK-ADV 11-0P)
Field Maintenance Print Set (MPOO 186)
Microcomputer Interfaces Handbook (EB-20 175-20)

185

»
0)

DO DODD

~34

Rf
(GAIN) (OFFSET)

Ris
(GAIN)(GAIN)

DAC 1

DAC 2

~ ~~ ~
0---0

0---<1

\37 (GAIN)
(OFFSET~R49
(OFFSET)

.,..........,.,..........,
W13

o
o
.....

DAC3

DAC 1

Ri
(OFFFET)

DAC 0

DAC2

DAC0

W14

DAC 3

-W17

WIG

MODE / LEVEL STRAPS

BIT 11

BIT 3
\

Ir--~I
(ADDRESS)

11-4319

AAV 11-A Address Switches (Set for 17044n)

A6001

111

STANDARD ADDRESS
CONFIGURATION
(1704401

~~~RESS

SWITCH

5
_9......'_8......'_7___'......6_... _.'_4-,,_3-,,'_2......'_1

LOGICAL 1 • ON
LOGICAL O. OFF
MA-0855

AAVll-A ADDRESS WORD

" I " I "I" I
1

15
1.

•

09
0

"0 • 0 : WORD OR LOW BYTE
"0' 1 : HIGH BYTE

1I I

o .

" 2

0
0

0
1
0

ADDRESS

DAC

MODE

170440
170441
170442
170443
170444
170445
170446
170447

0
0

WORD OR LOW BYTE
HIGH BYTE
WORD OR LOW BYTE
HIGH BYTE
WORD OR LOW BYTE
HIGH BYTE
WORD OR LOW BYTE
HIGH BYTE

1
2
2
3
3

"I
0

•

o
DAC
0

11-4313

AA V 11-A Address Decoding

187

A6001

Jumper Configurations for Bipolar Operation (as Shipped)
±2.56 V ±5.12 V ± 10.24 V
DAC1
W3
W4
W5
W6

OUT

OUT
OUT

OUT

DAC2
W7
W8
W9
W10

OUT

OUT
OUT

OUT

DAC3
W11
W12
W13
W14

OUT

OUT
OUT

OUT

DAC4
W15
W16
W17
W18

OUT

OUT
OUT

OUT

IN
IN

188

A6001

Jumper Configurations for Unipolar Operation

o V - +5.12 V o V - + 10.24 V
DAC1
W3
W4
W5
W6

IN
OUT
IN
OUT

IN
OUT
OUT
OUT

DAC2
W7
W8
W9
W10

IN
OUT
IN
OUT

IN
OUT
OUT
OUT

DAC3
W11
W12
W13
W14

IN
OUT
IN
OUT

IN
OUT
OUT
OUT

DAC4
W15
W16
W17
W18

IN
OUT
IN
OUT

IN
OUT
OUT
OUT

AAV11-A Input Code/Output Voltage Relationship
Input Code

Unipolar

Bipolar

0000
4000
7777

0V
1/2 FS
+FS - 1/2 LSB

-FS
0V
+FS - 1/2 LSB

189

BA 11-M

BA11-M

Mounting Box: Physical Specifications

a.9CM

(3.5INI

!-=================:::::::I~

14-------~1';31~~---J

34.3 CM
14 - - - - - - - ( 1 3 . 5 I Nl-------.l-I
1

POWER SUPPLY
AIR

AIR

}
'---

FRONT

PROCESSOR
MEMORY AND
DEVICES

SA 11-M Assembly Unit

190

BA11-M
Electrical (These specifications reflect the characteristics of the H780
power supply.)
Input Voltage (Continuous: see Note 1.)
100 Vac-127 Vac (H780-C, -H, -K)
200 Vac-254 Vac (H780-D, -J, -L)
Temporary Line Dips Allowed
100% of voltage, 20 ms max.
AC Inrush Current
70 A at 127 V 60 Hz (8.33 ms)
25 A at 254 V 50 Hz (10 ms)
Input Power (Fans Included)
340 W at full load max.
290 W at full load typical
EMI (Emission and Susceptibility)
Per DEC STD 102.7 and VDE N-12 limits
Input Protection
H780-C, -H, -K (100 Vac-127 Va c) fast blow, 5 A fuse
H780-D, -J, -L (200 Vac-254 Vac) fast blow, 2.5 A fuse
Hi-Pot
2 kV for 60 seconds from input to output, or input to chassis
Output Power (Combinations not to exceed 110 W.)
+5V, 1.5A- 18A
+ 12 V, 0.25 A - 3.5 A
Maximum DC Current Under Fault Conditions
+5 V bus = 28 A
+ 12 V buS = 9.5 A
+5 V Output
Total regulliltion
Line regulation
Load regulation
Stability
Thermal drift
Ripple
Dynamic load regulation

5 V ± 3%
±0.5%
± 1.0%
0.1 %/ 1000 hours
0.025%;0 C (See Note 2.)
150 mV p-p (1 % for f<3 kHz)
± 1.2%
di/dt = 0.5 A/J.ls
t:.L = 5 A

191

BA11-M
Noise

1% peak at 5 > 100 kHz (noise is superimposed on rippl'e)

Interaction due to + 12 V

± 0.05%

+ 12 V Output
Total regulation
Line regulation
Load regulation
Stability
(See Note 2.)
Ripple
Dynamic load regulation

12 V ± 3%
±0.25%
±0.5%
O. 1%/ 1000 hours
0.025%;0 C above 25 0 C
350 mV p-p (1 % for f <3 kHz)
±0.8%
di/dt = 0.5 A/J.Ls
f<500 Hz
6L = 3 A

Noise

1% peak f > 100 kHz (Noise is superimposed on ripple.)

Interaction due to + 5 V

±0.2%

Overvoltage Protection
+5V

+ 12 V
Adjustments
+5 V output

+ 12 V output

Controls
Rear panel

6.3 V nominal
5.65 V min.
6.8 V max.
15 V nominal
13.6 V min.
16.5 V max.

4.05 V-6.8 V
Guarantee range 4.55 V -5.65 V
10.6 V-16.5 V
Guarantee range 11.7 V -13.6 V

AC ON/OFF switch

Front console

DC ON/OFF switch
HALT/ENABLE switch

(Master only)

LTC ON/OFF switch

192

BA 11-M
Console Indicators
DC ON
RUN (master)
SPARE (master only)
Backplane Signals
BPOK H }
BDCOK H
Transmitted
BEVNT L
BHALT L
SRUN L
Received (master only)

Mechanical
Cooling
Two self-contained fans provide 0.7140 m 3 /min (30 ft 3 /min) air flow.
Size

13.97 cm w X 8.43 cm h X 37.15 cm I
(5-1/2 in w X 3-1/3 in h X 14-5/8 in I)
Weight

5.90 kg (13 Ib)

Environmental
Temperature
Ambient
Storage

5°-50° C (41°-122° F)
-40°-70° C (-40°-158° F)

Humidity

90% maximum without condensation

NOTES
1.

Operation from ac lines below 100 V may cause the power
supply to overheat because of decreased air flow from the
cooling fans.

Thermal drift parameters apply after five minutes of warmup and are measured with an averaging meter at the processor backplane terminal block under system loading.

193

BA 11-M
Option Variations
BA 11-MA

Consists of a BA 11-MC mounting box with H9270-A backplane
and H780A power supply for 115 Vac, 60 Hz.

BA 11-MB

Consists of BA 11-MC mounting box with H9270-A backplane
and H780-B power supply for 230 Vac, 50 Hz.

BA 11-MC

Consists of 3.5 inch high mounting box with no backplane or
power supply.

BA 11-ME

Consists of BA 11-MC mounting box with H9270-A backplane
and H780-E power supply for 115 Vac, 60 Hz.

BA 11-MF

Consists of BA 11-MC mounting box with H9270-A backplane
and H780-F power supply for 230 Vac, 50 Hz.

Power Supply Models

115 Vac
H780-A
H780-B
H780-C
H780-D
H780-E
H780-F
H780-H
H780-J
H780-K
H780-L
H780-M
H780-N
H780-P
H780-R

230 Vac

Line
Cord

Console
Fans Type

X
X
X
X

X
X
X
X
X
X
X
X
X
X

X
X

X
X
X
X
X
X
X
X
X
X
X
X

194

Master
Master
None
None
Slave
Slave
Master
Master
Slave
Slave
Note 1
Note 1
Note 2
Note 2

BA 11-M
NOTES
1.

The H780-M and -N have no control panel on the basic option. The Business Products 320 line uses a control panel
that has two DC ON indicators (PN 54-12695). This control
panel is carried as part of the 11 /03-J computer.

The H780-P and -R also use the 54-12695 control panel.
They differ from the -M and -N in that the basic power supply option includes the control panel, a line cord, and fans.

The 115 Vac options operate on 100 Vac-127 Vac at either 50 or 60 Hz. The 230 Vac options operate on 200
Vac-254 Vac at either 50 or 60 Hz.

Power Supply/Control Panel Interface Cables
Cable

DECPN

DC output cable
Power supply status cable (logic cable)
Power supply console cable

7011584-0-0
7011411-0K-0
7008612-0M-0

BLACK
WHITE
GREEN

1-=

}

115 VAC

CHASSIS
GROUND

TERMINAL BLOCK
(TB1)

115 Vac Terminal Block Wiring

BROWN
BLUE
}
GREENIYELLOW

CHASSIS

-= GROUND

TERMINAL BLOCK
(TB1)

230 Vac Terminal Block Wiring
195

230 VAC

BA11-M
Cable Interconnections
J4 12-PIN CONNECTOR
(SIDE 2 OF PC BOARD)
H780 POWER SUPPLY

AC LINE CORD

CONSOLE
SIGNAL/POWER
CABLE (11 in.)
I--~-+-+-.---......-r-r-_--J (70-08612- OM-O)

1
2
SIGNAL CABLE (10 in.)
( 70-11411-0K-0)

3
4
5
6
7
B
9
10

BPOK H
BEVNT L
SRUN L
(KEY)
GROUND
CL3 L
CS3 L
SPARE
BHALT L
DCOK H

I
2

3
4
5
6
7

SIGNAL

.!:!..!'!.

+5A
DC ON H
SRUN L

9
+5A
10 SPARE
II
SPARE
12 GROUND
13 GROUND
14 DC OK LED H
15 SPARE
16 B HALT L

iiEVNT[
GROUND
CL3
CS3
SPARE

SIGNAL

CONNECTOR PINS ON
H9270 P.C. BOARD
'0

_BDCOK H

L~~:::LTL

H9270 BACK PLANE REAR V I EW
(P.C. BOARO SlOE 2)

""'~SRUN L

STRIP

+5VB

BPOK H

TERMINAL BLOCK

H780 to H9270 Backplane Connections

Master jSlave Interface Cables
Length
10_2 em
15_0 em
22.9 em
27_5 em
35_6 em
45.7 em
124.0 em
61.0 em
1.83 m
3.05 m
4.88 m

DEC PN
(4 in)
(6 in)
(9 in)
(11 in)
(14 in)
(18 in)
(49 in)
(2 ft)
(6 ft)
(10ft)
(16 ft)

7008612-00
7008612-0F
7008612-0K
7008612-0M
7008612-1B
7008612-1 F
7008612-4A
7008612-02
7008612-6A
7008612-10
BC034-16*

* Refer to the "Systems Configurations" section for applications using this
cable.
196

BA11-M

+ 12 V Adjustment
Perform the following procedure when adjusting the + 12 Vdc output.
1. Apply power to the LSI-11 or PDP-11 /03 system and allow a five minute warm-up period.
2. Using a DVM, measure the + 12 V output at the LSI-11 or PDP-11/03
backplane terminal block.
3. Using a small screwdriver, adjust RB7 until the DVM indicates + 12.0
V (+ 11.64 V to + 12.36 V acceptable range). Turning RB7 CW (clockwise) decreases the + 12 V output, while turning CCW (counterclockwise) increases the output.

NOTE
If R87 is turned too far CCW, the + 12 V output will crowbar
and drop to approximately 0 V. This will occur between + 13.0
V and + 16.5 V. Do not allow the supply to crowbar as this may
blow the internal fuse (F 1) protecting the + 12 V regulator.
4. Using an oscilloscope, measure the ripple on the + 12 V output at the
backplane terminal block. The ripple should not be greater than 350
mV peak-to-peak.

+ 5 V Adjustment
Perform the following procedure when adjusting the + 5 Vdc output.
1. Apply power to the LSI-11 or PDP-11 /03 system and allow a five minute warm-up period.
2. Using a DVM, measure the + 5 V output at the LSI-11 or PDP-11 /03
backplane terminal block.
3. Using a small screwdriver, adjust RBB until the DVM indicates + 5.0 V
(+ 4.B5 V to + 5.15 V acceptable range). Turning RBB CW decreases
the + 5 V output, while turning CCW increases the output.

NOTE

If R88 is turned too far CCW, the + 5 output will crowbar and

drop to approximately 0 V. This will occur between +5.6 Vand
+ 6.8 V. Do not allow the supply to crowbar as this may blow
the internal fuse (F2) protecting the +5 V regulator.
4. Using an oscilloscope, measure the amplitude and frequency of the
ripple on the + 5 V output at the backplane terminal block. The ripple
should not be greater than 150 mV peak-to-peak with a period from BO
I1s-140 I1S. If the ripple period is not within BO I1S-140 I1S, adjust R96.
Turning R96 CW decreases the ripple period, while turning CCW increases the period. After adjusting the ripple period, recheck the + 5
V output (steps 2 and 3).

197

BA11-M

MEASURE HERE

H9270 BACKPLANE REAR V I EW
(P.C. BOARD SIDE 2)

TERMINAL BLOCK
MR-076&

Backplane Terminal Block

+12 V OUTPUT
ACAJUST (RS7)
CCItJ - INCREASE
CW - DECREASE

+5 V FREQUENCY
ADJUST (R69)
CCW - INCREASE
CW - DECREASE

+5 V OUTPUT
ADJUST (RSS)
CCW - INCREASE
CW DECREASE

HEAT SINK
FAN

FAN

Locations of H780 Adjustments

198

SA 11-M
Controls and Indicators
BA 11-M/H780 Controls and Indicators
Control!
Indicator

Type

Function

DC ON

LED Indicator

Illuminates when the DC ON/OFF
toggle switch is set to ON and proper
dc output voltages are being produced
by the H780.

If either the
5 or
12 V output from
the H780 is faulty, the DC ON indicator
will not illuminate. This is the only indicator on the H780-K and -L slave
supplies.
RUN

LED Indicator

Illuminates when the processor is in
the run state (see ENABLE/HALT).

SPARE

LED Indicator

Not used by the H780 or processor.
The H780 contains circuitry for driving
this indicator for user applications.

DC ON/OFF

Two-Position
Toggle Switch

When set to ON, enables the dc outputs of the H780. The DC ON indicator
will illuminate if the H780 dc output
voltages are of proper values. If a slave
supply is connected to a master, the
slave DC ON indicator will light if the
slave dc output voltages are of proper
value.
When set to OFF, the dc outputs from
the H780 are disabled and the DC ON
indicator is extinguished. If a slave
supply is connected to a master, the
slave DC ON indicator will also extinguish.

ENABLE/HAL T

Two-Position
Toggle Switch

When set to ENABLE, the BHAL T L line
from the H780 to the processor is not
asserted and the processor is in the
run mode (RUN indicator illuminated).

199

BA 11-M
BA 11-M/H780 Controls and Indicators (Cont)
Control!
Indicator

Type

Function

ENABLE/HAL T

Two-Position
Toggle Switch

When set to HALT, the BHAL T L line is
asserted, allowing the processor to execute console OOT microcode (RUN
indicator extinguished).

LTC ON/OFF
Switch

Two-Position
Generation

When set to ON, enables the toggle of
the line time clock (LTC) BEVNT L signal by the H780.
When set to OFF, disables the H780
line time clock.

AC ON/OFF
(Rear Panel)

Two-Position
Toggle Switch

When set to ON, applies ac power to
the H780.
When set to OFF, removes ac power
from the H780.

FUSE
(Rear Panel)

5 A or 2.5 A
Fast Blow

Protects H780 from excessive current.
H780-C, -H, and -K use a 5 A fuse.
H780-0, -J, and -L use a 2.5 A fuse.

ROWS
A

PROCESSOR
(HIGHEST PRIORITY LOCATION)

PROCESSOR OR OPTION 1

OPTION 3

OPTION 2

OPTION 4

OPTION 5

OPTION 7
(LOWEST PRIORITY LOCATION)

OPTION 6

SLOTS

VIEW FROM MODULE SIDE OF BACKPLANE

H9270 Option Positions

200

BAll-M
J2

,-...
14

~
14

C DCON H

B
1

+5A

9
0

TP4""

TPI

.n.

--0

CL3

CS3

7
4

PIN 1

CUT ETCH CON·

~1l~I~~;~~~ _~1
00
CUT IT SUCH
THAT THE GAP
CAN BE EASI L Y

~~P~l~oW~~~

STORE THE
GROUND PATH.

.rlI
~

C SPARE 3

C SPARE 4

C SPARE 5

C SPARE 6

TP3'

W2 (ETCH CUT)

01
DC

C SPARE 1

r, q>~

THIS ETCH CU T IS MADE
WHEN THE BALL·M IS USED
AS AN EXPAN DER BOX ON
11 03-L SYSTE MS. (BALL·N
AND BOVIll

'-'

H780 Slave Console Modification
H780 Slave Console Modification
The slave console (54-12143) for the H780 (in the SA 11-ME/F 3.5 inch
PDP-11/03 expander box) contains an etch that applies a ground signal to
pin 4 (and others) on J 1. This is desirable except when the SA 11-M is used
as an expander box and contains a line clock, such as with the SDV 11 or
when a SA 11-M is used to expand an PDP-11 /03-L system. In this case,
the SDV 11 requires the SEVNT signal to generate line clock interrupts. If
this etch is present, the signal SEVNT L is asserted (reference H780 sheet
3 schematic), turning off the SEVNT signal.
To correct this unwanted condition, it is necessary to cut an etch on the
54-12143 slave console board. This etch is made only for the reason described above.
ECO no. 54-12143-PN002 has been written to document this change. In the
ECO, the etch cut is referred to as W2. Pay particular attention to this when
adding a SA 11-M as an expander box, or when replacing the power supply/slave console assembly (H780-E/F /K/L) or the slave console board.

201

BA11-N

BA 11-N

Mounting Box: Physical Specifications

I...--I

57,BCm _ _ _-------l!
(22,7 in)
•

AC INPUT
PANEL
"'C

AIR

::tI

BACKPLANE
ASSEMBLY

en
C

"'C

~
-<

BA 11-NE and BA 11-NF Assembly Unit

202

BA 11-N

Power Supply Specifications
Item

Specification

Current Rating

5.5 A at 115 Vrms
2.7 A at 230 Vrms

Inrush Current

100 A peak for one-half cycle at 128 Vrms or
256 Vrms

Apparent Power

630 VA

Power Factor

The ratio of input power to apparent power
shall be greater than 0.6 at full load and low input voltage.

Output Power

+5 Vdc, ± 250 mV at 22 A. (A minimum of 2 A
of +5 Vdc power must be drawn to ensure that
the + 12 Vdc supply regulates properly.) + 12
Vdc, ±600 mV at 11 A.

Power-Up/Power-Down Characteristics
Static Performance
Power-up

BOCOK H goes high: 75 Vac
BPOK H goes high: 90 Vac

Power-down

BPOK H goes low: 80 Vac
BOCOK H goes low: 75 Vac

Oynamic Performance
Power-up

3 ms (min.) from dc power within specification
or to BOCOK H asserted.
70 ms (min.) from BOCOK H asserted to BPOK
H asserted.

Power-down

4 ms (min.) from ac power off to BPOK H negated.
4 ms (min.) from BPOK H negated to BOCOK H
negated.
5 microseconds (min.) from BOCOK H negated
to dc power as of specifications.
203

SA 11-N
Option Variations
BA 11-NC

Consists of 13.2 cm (5.2 inch) mounting box with metal cover,
H9273 backplane, and H786 power supply with console, for 115
Vac, 60 Hz.

BA 11-ND

Consists of 13.2 cm (5.2 inch) mounting box with metal cover,
H9273 backplane, and H786 power supply with console, for 230
Vac, 50 Hz.

BA 11-NE

Consists of 13.2 cm (5.2 inch) mounting box with metal cover,
H9273 backplane, and H786 power supply without console, for
115 Vac, 60 Hz.

BA 11-NE

Consists of 13.2 cm (5.2 inch) mounting box with metal cover,
H9273 backplane, and H786 power supply without console, for
230 Vac, 50 Hz.

CONFIGURATION
Jumpers and Switches
Backplane Jumper Positions - There are three jumper positions on the
H9273 backplane: W 1, W2, and W3. Jumpers are installed in all three positions when the backplane is manufactured. The conditions under which
jumpers should be inserted or removed are described in the "Backplane
Jumpers" table.
The jumper in position W 1 is involved with CPU event interrupts. These interrupts can be initiated in two ways. First, a signal source external to the
BA 11-N can be used to pull the LSI-11 bus BEVNT L line low; in this case,
the jumper of W 1 of each H9273 backplane in the system would have to be
removed. Second, the LTC signal generated in the H786 power supply can
be used to pull the BEVNT L line low, thereby initiating vectored interrupts
at a rate that depends on the BA 11-N line frequency. W 1 connects the LTC
signal to the BEVNT L line; hence, in this case, the jumper would be left in
position W 1 of the H9273 backplane. In a multiple-box system, the box containing the M8012 module (i.e., the last box in the system) must be the
source of the LTC signal; thus, the W 1 jumper must be inserted in the backplane of this box and must be removed from the backplane of the other
box(es).
The jumper in W2 connects CK 1 to CL 1 in row 1, while the jumper in W3
connects DK 1 to DL 1, also in row 1. These jumpers must be inserted whenever a quad KD 11 CPU resides in row 1 of the first box.

204

SA 11-N
All three of these jumpers can be inserted and removed without any need
for disassembly, other than removing the logic box base from the cover.
However, if it ever becomes necessary to have clear access to the backplane, follow the instructions given for removal of the logic assembly in the
BA 11-N Mounting Box Technical Manual, EK-BA 11N-TM.

Backplane Jumpers
Jumper
Position

Jumper(s) In

Jumper(s) Out

When the H786 power-supply generated LTC signal is
used to assert the LSI-11
bus BEVNT L signal.

When it is not desired to
have line time clock (LTC)
sourcing BEVNT L, such as
when an external source is
used instead.

W2, W3

When a processor module
(KD 11 or KDF 11) is inserted in row 1 of the backplane.

When any other module is
installed in row 1; that is,
when the backplane is part
of an expander box.

NOTE
In multiple backplane systems, only the one backplane can
have jumper W1 installed. If a BDV11 module is used, install
the jumper in the backplane containing the BDV11 module.

205

SA 11-N

Backplane JUmpers

206

Bezel Assembly Jumper Positions - There are four jumper positions, W 1,
W2, W3, and W4, on the printed circuit board of the bezel assembly. When
the board is manufactured, jumpers are inserted in positions W 1, W2, and
W4; position W3 is left blank.
If it is necessary to remove the bezel assembly printed circuit board for any
reason, follow the instructions for removal of the bezel assembly given in
the BA ll-N Mounting Box Technical Manual, EK-BA11N-TM.

Bezel Assembly Jumpers
Jumper
Position

Jumper In

Jumper Out

W1, W2

When
the
bezel
AUX
ON/OFF switch is used to
control the power-supplygenerated
LTC
signal.
(When the switch is in the
AUX ON position, L TC-initiated interrupts are possible).

When
the
bezel
AUX
ON/OFF switch is used to
turn the system power controller on and off.

When the bezel is to be
mounted on the expander
box. (W3 permits the HALT
switch to light the RUN indicator.)

When the bezel is part of
the main box; that is, the
CPU is mounted in this bezel's backplane.

When the bezel is part of
the main box. (W4 enables
the S RUN L signal to light
the RUN indicator.)

When the bezel is mounted
on an expander box.

207

BA11-N

SIDE 2

0
W1 0---0 0
0
W20---00
0
0---<>----0
W3 W4
0

~"
--

SWITCH CONTACTS
(S3, S2, Sl)

IT}

LED CONTACTS
(RUN, PWR OK)

BEZEL PRINTED CIRCUIT BOARD 12-12985
NOTES:
1. VIEW IS FROM THE REAR OF THE BEZEL
WHEN THE BOARD IS MOUNTED ON
THE BEZEL.
2. JUMPERS ARE MOUNTED ON SIDE 1.

BEZEL ASSEMBLY JUMPERS

JUMPER
POSITION JUMPER IN

JUMPER OUT

W1,W2

WHEN THE BEZEL AUX ON/OFF
SWITCH IS USED TO CONTROL
THE POWER SUPPLY GENERATED
LTC SIGNAL (WHEN THE
SWITCH IS IN THE AUX ON
POSITION, LTC·INITIATED
INTERRUPTS ARE POSSIBLE).

WHEN THE BEZEL AUX ON/OFF
SWITCH IS USED TO TURN THE
SYSTEM POWER CONTROLLER ON
AND OFF.

WHEN THE BEZEL IS TO BE
MOUNTED ON THE EXPANDER
BOX (W3PERMITSTHE HALT
SWITCH TO LIGHT THE RUN
INDICATOR).

WHEN THE BEZEL IS PART OF THE
MAl N BOX, I.E., THE CPU IS
MOUNTED IN THIS BEZEL'S
BACKPLANE.

WHEN THE BEZE L IS PART
OF THE MAIN BOX (W4
ENABLES THE S RUN L
SIGNAL TO LIGHT THE RUN
INDICATOR).

WHEN THE BEZEL IS MOUNTED
ON AN EXPANDER BOX.

Bezel Printed Circuit Board

208

REAR OF BACKPLANE

rT---I~~~~-:o:;----------Jf1
•

o 1 +12 VDC 18) I
2 +12VDC

SLOT D

SLOT C

SLOT B

SLOT A

BBl - W - l - - B POK H

BR1-BEVE:rF~ ~~T~.

3 GND +12 VDC I
4 GND +5 VDC

•

IROW 1)

I
I

BACKPLANE

P2-1

P2-2

P2-3

P2-4

BLANK PIN

H9273
LOGIC ASSEMBL Y

j.------'---b<i" 5 +5 VDC

GND

•

GND

•

P2-5
P2-6

P2-7

~~. - - - +5 VDC

P2-8

6 +5 VDC IB)

I-----+-+O~ I 7 GND +5 VDC I
I

I c=::=:::::J c=::=:::::J c:::===::::J c::==:=J

L __ __
8 +5 VDC

GND

~ ~

L....----------'

APl - - - B HALT L

•

BAl - - - B DCOK H

•

P2-9
P2-10

RO:"+-tr-+ _______ :J
~~
Jl0

J9
CABLE SIGNAL

H786
CONTROL BOARD

DC POWER HARNESS
7014091

H786 POWER
J:

~ ~ '"

I\)

r. J7-2

- 6

+12 VDC

!'-=-":""':"-f-(i" 5 GND +12V

IHGFEDCBI'

7011411

MONITOR BOARD
u

"" ~ "> ~ u

a" >~ s!

s! f-

LKJIHGFEDCBA

J2'-_ _ _ _ _ _ _---J

-f-T--!l+ ±frfrfra-~rBBB~~~~~~
~

h~~~~

)

JS.

4 GND +5V
~,,-+-f-(i~ I 3
~~-f-(i"

GND +5V

...J

2 +5 VDC

!'-'-'--'-t--!><i~ I 1 +5 VDC

(

'" '"

"">~ a
" "
a

L _____________________ _

SA 11-N Unit Interconnection (Sheet 1 of 2)

...J

::;)

u 0

~ ~
)

AC POWER HARNESS
7014093

A*! A~I A)

SA 11-N
BRN
YELlGRN
BLU
LINE CORD, 115 VAC, 1700083-02 ~
LlNECORD,230VAC, 1700090-00

115/~OUT

r-- -- -- -- -- -- ')- --,
IJ3~

J23~1

...J Cl UJ

AC INPUT BOX (H403-A)

<! z Z

l=<!J:::;

~~
~UJ
~
~~
~2
~~~~~~~~~~ ~

.:..: :..: . . . . . . :..:~

I ; ~~ ; ~ ~~ ~ ~~~ ~
12 11 10

1
Pl

IGA~.;-1I
115VAC

~
L_:..J

AC POWER
HARNESS
7014093

Pl-l
Pl-2
Pl-3
Pl-4

•

• LTC
• S RUN L

Pl-6
Pl-7
Pl-8

BLANK PIN
GND

GND
~ 1 •• +5 VDC
• SPARE
• B HALT L
10
• B DCOK H
1

Pl-9
Pl-l0
P2

~J_l

(

______

SA 11-N Unit Interconnection (Sheet 2 of 2)

210

I
I
I
I
I

B POK H

:I •

Pl-5

CABLE SIGNAL
7011411

IFRONTPANEi:AsSv-

)J21

_.J

BA 11-N
Adjustments
DC Voltage Measurement - The +5 Vdc and + 12 Vdc regulated voltages
can be measured at J7 of the backplane or, preferably, at the tip jacks on
the M8012 module. The pins of J7 are numbered, and the wires connected
to them are color coded. + 12 Vdc and +5 Vdc are assigned the following
pins and colors.
+ 12 Vdc

- pin 2, purple wire

+ 12 Vdc ground -; pin 3, black wire
+5 Vdc
- pin 5, red wire
+5 Vdc ground - pin 4, black wire

The tip jacks on the M80 12 module are color coded and labeled as follows.

+ 12 Vdc - J3, purple
+5 Vdc
ground

- J2, red
- J 1, black

Use a calibrated digital voltmeter to measure the voltages under normal
load conditions.

NOTE
Do not measure the dc voltages without a load on the power
supply; incorrect readings will result.

The +5 Vdc output should be +5 V ± 250 mV, while the + 12 Vdc output
should be + 12 V ± 600 mV. If either voltage is out of tolerance, adjust the
appropriate potentiometer on the control board. R 1 varies the + 12 Vdc
output and R22 varies the
5 Vdc output. The potentiometers are identified in the figure that follows. The correct output should be achieved when
a potentiometer is near its mid-range position. If a potentiometer must be
turned to near an extreme position to achieve tolerance limits, there is perhaps a problem somewhere in the regulator. If the output cannot be brought
within limits, replace the entire control board.

211

BA 11-N

R22
+5 VDC ADJUSTMENT

R1
+12 VDC ADJUSTMENT

Power Supply Adjustments

212

BA 11-N
Controls and Indicators
Operation - The SA 11-N can have a blank front panel or one equipped with
three switches and three indicators. In addition to the front panel switches
and indicators, there is an ON/OFF switch and a primary voltage selection
switch, both on the ac input box. The ON/OFF switch remains in the ON
position when a power controller is used to apply primary .power to the
SA 11-N; if a power controller is not used, the switch can be used to turn
power on and off.
BA 11-N Front Panel Switches and Indicators
Switch

Indicator

AUX ON/OFF

Function
Can be used for any desired function (switch is
rated at 48 V, 1 A dc). Two functions are explained below.
If the SA 11-N is wired to control system power,
the AUX switch turns the power on and off; if the
SA 11-N is not wired to control system power,
the switch can control the LTC signal, disabling
the signal when the switch is in the OFF position.

HALT

In the down position, the HALT switch forces the
CPU to suspend normal program execution, enables console ODT microcode operation, and
permits single-instruction execution. To resume
program execution, return the HALT switch to the
up position and enter a P command from the console terminal (providing that the contents of register R7 were not changed). Refer to the Microcomputer Processor Handbook, ES-18451-20, for
a description of console ODT command usage.
In an expander box, the HALT switch can be used
to light the RUN indicator.
When the momentary RESTART switch is activated, the CPU automatically carries out a power-up sequence; thus, the CPU can be rebooted
at any time from the front panel.

RESTART

PWR OK

The PWR OK indicator lights when the power
supply dc voltages are present.

RUN

The RUN indicator lights when the CPU is executing programs.

213

BA11-N
AC Voltage Selection - The BA 11-N can be used with line voltage of either
115 Vac or 230 Vac. Only the ac line cord is different for the two voltages.
However, a voltage selecting switch must be set to a position that corresponds to the line voltage being used. This switch is located on the rear of
the ac input box, above the circuit breaker. The switch lever protrudes
through a plate that is attached to the box.
If the line voltage being used is 115 Vac, the designation" 115 Vac" should
be printed on the plate above the switch lever. If the printing on the plate is
230 Vac, remove the plate. Flip the plate over and notice that 115 Vac is
printed on the opposite side; also, notice that the switch lever itself is imprinted with 230 Vac. Move the switch lever down; 115 Vac should appear
on the top of the lever. Replace the plate over the switch lever so that the
printing on the outside of the plate reads" 115" Vac. (When the plate is on,
the printing on the switch lever cannot be seen.) The plate is fabricated so
that the screw holes in the plate and the input box line up only when the
switch position corresponds to the printing on the outside of the plate.

VOLTAGE
SELECT
SWITCH

@ ~~8:'" TYPE 11

BA 11-N Voltage Select Switch

214

BA 11-N
Backplanes

J7
<01

+12 VDC(8)

e 2

+12 VDC

GND +12VDC

<0 4

GND +5VDC

SIGNAL
CONNECTlONS

••
•
••• •••
J9

e 5 +5VDC

GND

(9 6

+5VDC(8)

<0 7

GND +5VDC

e 8

+5VDC

-12V

H9273-A Power Connections

A81
BR1-B

BPOK H
EVENT L

AFl
(ROWl)

LTC
SRUN L
GND
GND

BA2,DA2

+5VDC

APl

BHALT L

BAl

BDCOK H

H9273-A Signal Connections

215

BA11-N

CONNECTOR 1

CONNECTOR 2

r---------~~--------~, (~-----------'----------~

SLOT A

SLOT B

SLOT C

SLOT D

ROW 1

(PROCESSO:R (OR M9401)

ROW2

OPTIPN 1

ROW3

OPTI:ON 2

ROW4

OPTI:ON 3

ROW5

OPTI:ON 4

ROW6

OPTIPN 5

ROW 7

OPTI:ON 6

ROW8

OPTIPN 7

ROW9

OPTIPN 8

CD INTERCONNECT
IN THESE SLOTS

VIEW IS FROM MODULE SIDE OF CONNECTORS.

BACKPLANE JUMPERS
JUMPER
POSITION JUMPER(SIIN

JUMPER(SIOUT

WHEN THE H786 POWER SUPPLY
GENE RATED LTC SIGNAL IS
USED TO ASSE RT THE LSll1
BUS BEVNT L SIGNAL.

WHEN IT IS NOT DESIRED TO
HAVE LINE TIME CLOCK (LTCI
SOURCING BEVNT L, SUCH AS
WHEN AN EXTERNAL SOURCE IS
USED INSTEAD.

W2, W3

WHEN A CPU MODULE IS
INSERTED IN ROW 1 OF THE
BACKPLANE.

WHEN ANY OTHER MODULE IS
INSTALLED IN ROW 1, I.E.,
WHEN THE BACKPLANE IS PART
OF AN EXPANDE R BOX.

H9273-A Backplane Connectors

216

BA 11-N
CO Bus Signals - The CO bus signals are supplied by slots C and O. The
+ 5 V supply voltage is bused to all rows on pin A2 of slots C and 0 (that is,
pins CA2 and OA2). Likewise, ground connections on pins CC2, CT 1, OC2,
and OT 1 are bused to all rows. All other pins connect only to an adjacent
row.
For example, pin CF2 of any row connects only to pin CF 1 of the adjacent
higher-numbered row. Pins on side 2 of the slot (B2, C2, etc.) connect to
the adjacent higher-numbered row (except OT2, which connects to CT2 of
the adjacent lower-numbered row), while pins on side 1 of the slot (B 1, C 1,
etc.) connect to the adjacent lower-numbered row (except pin A 1, which
connects to C 1 of the adjacent higher-numbered row).
Thus, each row, except 1 and 9, has 33 signal connections (other than + 5
V and ground) to both the adjacent higher-numbered row and the adjacent
lower-numbered row. To facilitate references to these two groups of 33 signals, group 1 is defined as the group of signals connecting a row (row X) to
its adjacent lower-numbered row (row X-1). Group 2 is defined as the group
of signals connecting a row to its adjacent higher-numbered row (row
X+ 1). Generally, group 1 signals are found on side 1 pins, while group 2
signals are found on side 2 pins.

BA 11-M/BA 11-N Expansion Configuration
• The LTC is sourcing the BEVNT L in the BA 11-MA box. (BOV 11 is not
being used.)
• Power is controlled by the 861 C power controller ON/OFF switch.
NOTES
1.

If a BOV 11, with E21 switch 5 "on," is used as the last
module in the BA 11-WE, install W1 in the BA 11-NE backplane. Turn off LTC switch (must remain off) in the BA 11MA.

BCV1B-XX' configuration: M9400 KE in first A-B slot after
options in BA 11-MA backplane. M9400 KO in first A-B slot
in BA 11-NE backplane.

* XX denotes cable length.

217

»
...

...

ROW1

PROCESSOR

ROW2

OPTION

ROW3

OPTION

(AC IN)

r
\.

'\
./

ROW4

OPTION
OPTION

BAll-MA
BOX

OPTION
)
OPTION

I--

861-C
POWER
CONTROLLER

MAX. CABLE LENGTH 3_05 M (10 FT)
SWITCHED
OUTPUTS

(2)BC05 - L

!---BCV1B - XX

(NOTE 2)

rROW 1

J3AC
OUT

J2
(AC IN)
NOTE
LEAVE DC SWITCH
POSITIONED ON_

ROW 2

OPTION

ROW3

OPTION

ROW4

OPTION

ROW 5

OPTION

ROW 6

OPTION

ROW 7

OPTION

ROW 8

OPTION

ROW9

BAll - NE
BOX

BA11-NE
BACKPLANE
JUMPERS

TERMINATOR

(NOTE1)

W1 - OUT
W2 -OUT
W3- OUT

VIEW IS FROM MODULE SIDE OF CONNECTORS_

BA 11-MA to an NE Box Expansion

MR.4973

BA 11-N

CONNECTOR 2

CONNECTOR 1
SLOT A.

J3ACOUTROW 1

AUX ON/OFF
SWITCH IBEZE L
PANEL)

SLOT B

SLOT C

SLOT D

PROCESSOR

ROW2

OPTION 1

ROW3

OPTION 2

ROW4

OPTION 3

ROW5

OPTION 4

BAllNC

J2 AC IN

ROW 6

OPTION 5

ROW7

OPTION 6

ROWS

OPTION 7

ROW9

'--

MAX. CABLE LENGTH 3.05 M 11 OFT)

S61C
(2) BC05· L

_BCV1S·XX

ROW 1

AC IN

ROW2

OPTION

(

ROW3

OPTION

"\
.J

OPTION
OPTION
OPTION

"TERMINATOR

ROW4

"AN ECO MUST BE INSTALLED IN THE SLAVE
BOARD I FA BDV11 IS USED IN A SA 11·M BOX.

SA 11-NC to an ME Sox Expansion
SA 11-NC backplane jumpers:
W1 - IN
W2 -IN
W3 -IN

(If M7264 or M7264-YA CPU is present.
If not, remove jumper.)

SA 11-NC bezel jumpers:
W1 - OUT
W2 - OUT

When bezel AUX ON/OFF switch is used to turn system
power controller on or off; otherwise IN.

W3 - OUT
W4 - IN

NOTES
1.

If a BDV11, with E21 switch 5 "on," is used as the last
module in the BA 11-ME, install ECO (see Appendix B) in
backplane of BA 11-ME. Remove W1 from the backplane of
BA11-NC.

BCV1B-XX configuration: see BA 11 MA/NE configuration
figure.
219

BA11-N

CONNECTOR I

SLOT A

861C
POWER
CONTROLLER
SWITCHED
OUTPUT

SLOT B

SLOTC

SLOT D

PROCESSOR

ROWI

CONNECTOR 2

ROW2

OPTION I

ROW 3

OPTION 2

ROW4

OPTION 3

ROW5

OPTION 4

ROW6

OPTION 5

ROW 7

OPTION 6

ROW8

OPTION 7

J2 AC IN

BAlI
BOX

ROW9
"MAX. CABLE LENGTH 3.05 M (I OFT)
(2) BC05· L

ROWI

6--~

J3 AC OUT"ii"O'WT

OPTION

J2 AC IN

ROW 3

OPTION

ROW4

OPTION

ROW5

OPTION

ROW6

OPTION

ROW7

OPTION

ROW8

!---BCVIB. XX

BAll· NE
BOX

OPTION
TERMINATOR

ROW9

BA 11-N to Another N Box Expansion

NOTES
1.

If a BDV 11, with E21 switch 5 "on," is used as the last
module in the BA 11-NK, install W1 in the BA 11-NK backplane. Remove W1 from the BA 11-NC backplane.

BCV 1B-XX· configuration: M9400 KE in first A-B slot after
options in BA 11-NC. 9400 KD in first A-B slot of BA 11-NK•

.. XX denotes cable length.

220

BA 11-N
BA 11-NC backplane jumpers:
W1 I

W21
W3 I

If using CPU M7264 or M7264-YA; otherwise R.

BA 11-NC bezel jumpers:
W1 I

W21
W3R

W41
BA 11-NE backplane jumpers:
W1 R
W2R
W3R

CAUTION
Do not attempt to source ac power for the BA 11-N mounting
box from the BA 11-N box ac outlet, because the current rating
of the BA 11-N box will be exceeded and severe damage may
occur. Also, do not attempt to provide ac power to three BA 11N boxes from one 861 C power controller.

221

BA 11-N

(AC IN)

ROW 1

PROCESSOR

ROW2

OPTION

ROW3

OPTION

'\
.J

OPTION

ROW4

OPTION

1
1 ..

OPTION

-----1

'--

MAX. CABLE LENGTH 1.83 M ( 6 FTI

(2)

o~--o

ROW 1

~u~CRl5W2

B61C
PWR CTRL.
SWITCHED
OUTPUT

J2
(AC IN)

I+----- BCV 1B XX

BC05·L

OPTION

ROW3

OPTION

ROW4

OPTION

ROW5

OPTION

ROW6

OPTION

ROW7

OPTION

ROW8

OPTION

BAll
BOX

ROW9
'--

MAX. CABLE LENGTH 3.05 M (1 OFT)
(2)

I+----- BCV 1A XX

BC05L

ROW 1

AC IN

ROW2

OPTION

ROW3

OPTION

J
~

\
\
TERMINATOR

ROW4

OPTION
OPTION
OPTION
(NOTE 1)

·AN ECO MUST BE INSTALLED IN THE SLAVE BOARC
IF A BDVl 1 IS USED IN A BAl 1-M BOX

BAll·NE
BACKPLANE
JUMPERS
Wl - OUT (NOTE 1)
W2 - OUT
W3 - OUT

BA 11-MA to an ME Box Expansion

NOTES
1.

If a BOV11, with E21 switch 5 "on," is used as the last
module in the BA 11-ME, install ECO (see Appendix B) in
the BA 11-ME backplane. Remove W1 from this BA 11-NE
backplane. Turn off LTC switch (must remain off) on BA 11MA.

BCV1B-XX' configuration": BCV1A-XX; M9400 YO in first AB slot after options in BA 11-NE; M9401 in first A-B slot in
BA 11-ME backplane.

• XX denotes cable length.
• • See BA 11-MA to an NE Box Expansion figure.
(See Appendix B for ECO information.)

222

DLV11-KA

DLV11-KA
EIA TO 20 MA CONVERTER

Amps
+S

Bus Loads
-12
0

AC
N/A

DC
N/A

Cables
BC21 A-03 EIA
BCOSF-XX 20 rnA

+ 12 V@ 0.27S max. (supplied by EIA SLU interface module).
Standard Addresses and Vectors, Diagnostic Programs
None

Related Documentation
DLV11-KA ElA to 20 mA Installation Guide (EK-DLVKA-IN)
DL V 11-KA Maintenance Print Set (MP00694)
Microcomputer Interfaces Handbook (EB-2017S-20)

CONFIGURATION
General
The DL V 11-K requires the configuration of 11 jumper wire connections and
1 capacitor connection. The configurations and functions of these jumpers
are shown in the following table.

DLV11-KB Jumper Configurations
Function

Jumper In

Jumper Out

Passive 20 mA Receiver
Active 20 rnA Receiver"
Passive 20 rnA Transmitter
Active 20 rnA Transmitter"
110 Baud Enabled"
110 Baud Disabled
Noise Suppression

W7,W9
W6, W8, W10
W2,W4
W1, W3, WS
W11

W6, W8, W10
W7,W9
W1, W3, WS
W2,W4

See following Note.

"Factory configuration
223

W11
See following Note.

DLV11-KA
NOTE
For use with an ASR-33 Teletype™, insert a 0.047 JLFaxial ceramic capacitor (DEC PN 10-12784-00) in the location designated C. This capacitor is inserted for the factory configuration. For any other terminal there is nothing inserted in
this location.
For proper operation of Teletype ASR-33 with DEC-supplied
paper tape software, the SLU should be configured for eight
data bits, two stop bits, and no parity. The Teletype models
can be L T33-DC, L T33-DD, L T33-DE, or an ASR-33 Teletype
with the LT33-MB modification kit installed.

0--011
O--OC

60--0
0--01
70--0
O--OB

, L - - - - - - - l 90--0

r-----,,----' 4

0--03
5

g:::g

20--0

0--0 10

NOTE:
THE NUMBER 2 INDICATES THAT
IT IS THE W2 JUMPER WI RE.

DL V 11-KB Jumper Locations

Installation Requirements
The DL V 11-KA option can be installed in a system that requires conversion
from EIA RS-232 standard to a 20 rnA current loop. The DL V 11-KA option
consists of a DL V 11-KB converter box and a BC21 A-03 interface cable as
shown in the preceding illustration. The BC21A-03 is a 0.9 m (3 ft) cable
that interconnects the DL V 11-KB to an EIA SLU interface module. The
smaller connector (2 X 5 pin) connects to the SLU module and the larger
connector (2 X 7 pin) connects to the DL V 11-KB box. Keying is provided
on both connectors, and cable retention is provided by "locking pins" on
the SLU connector. To disengage, pull back on the connector shell and the
connector will slide free. However, if the cable is pulled, the locking pins
will hold the connector firmly in place. A BC05F-XX cable can be used to
connect the DL V 11-KB converter box to DEC 20 rnA terminals including the
DEC-modified ASR-33 Teletype.
224

DLV11-KA
Cabling
Cables other than the DEC BC05F-XX can be used when installing the
DLV 11-KA option. However, any other cable must conform to the following
parameters to meet the baud rate versus cable length specification.
1. Resistance - NMT 30 Q/305 m (1000 ft) (NL T 22 AWG)
2. Capacitance to ground - NMT 50 pF /ft
3. Capacitance wire-to-wire - NMT 35 pF /ft
The BC05F-XX cable meets the above requirements. If the user desires to
use shielded cable, the shield should be grounded to the chassis at the
entry point and not to the DL V 11-KB converter box. The user can fabricate
custom cables for the 20 mA interface by using DEC connector, PN 1209340-01 (AMP PN 1-480460-0), and pins PN 1209378-03 (AMP PN
350079-4).

Baud Rate
The DL V 11-KA option will operate up to a maximum of 9600 baud, provided
that the interface module can accommodate these rates. However, the
maximum operational baud rate is also limited by the length of cable. Maximum recommended cable lengths for the specific baud rates are given in
the following table. These recommendations are conservative and will yield
satisfactory operation for almost all applications. These guidelines may be
exceeded, but this should only be done after reviewing the DLV 11-KA specifications, the severity of the operating environment, and the error rate that
can be tolerated.

Baud Rate vs Cable Length
Baud Rate

Max. Cable Length

9600
4800
2400
1200
600
300
110

30 m (100 ft)
76 m (250 ft)
152 m (500 ft)
305 m (1000 ft)
610 m (2000 ft)
1220 m (4000 ft)
1220 m (4000 ft)

225

DLV11-KA
Terminal Recommendations

DIGITAL
Terminals
orSLUs

Active DLV11-KA
Max. Cable
Length
(22 GA)

DLV11
DLV11-F
DLV11-KA
M598
LA36
VT52
LA180S
LA120
VT100
LA120
Teletype ASR-33

1220 m (4000 tt)
1220 m (4000 tt)
1220 m (4000 tt)
1220 m (4000 tt)
457 m (1500 tt)
1220 m (4000 ft)
1220 m (4000 tt)
1220 m (4000 tt)
1220 m (4000 ft)
1220 m (4000 tt)
305 m (1000 ft)

Passive DLV11-KA
Max.
Max. Max. Cable
Baud Length
Baud
Rate (22 GA)
Rate

·· ··..

··

·.
·.

9600
9600
300
9600
NA

9600
9600
110 NA

9600
9600
NA

9600
9600
300
9600

1220 m (4000 tt)
457 m (1500 tt)

·· ·.
·.

NA
671 m (2200 tt)

Operation at 9600 baud only recommended tor benign environments.
Operation with more than 8 m (25 ft) ot cable is not recommended.

PASSIVE RECEIVER

ACTIVE TRANSMITTER
CURRENT
SOURCE

XMIT

1
T

IN TERFA CE
CABLE
REC

I
A'.

XMIT

I
I

CURRENT
DETECTOR

I RCVR
I

RECEIVED
DATA

REC

_ _ _ _ _ _ _ _ ...J

20MA
LOOP

TRANSMITTEO
DATA

ACTIVE RECEIVER
RECEIVED
DATA

----------.

PASSIVE TRANSMITTER

CURRENT
SOURCE

I CURRENT I
I DETECTOR I

XMIT

REC

...
XMIT

REC

Standard Current Loop Interface
226

20MA
LOOP
XMTR

TRA NSMITTED
OAT A

DLV11-KA

DLV11-KA OPTION
BC21A-03
CABLE

BC05F-XX
CABLE

,----A----...
P1

+12 VDC

10)

1 (

< 2

2 (

< 3

3 (

SIG GND
9 )
EIA OUT

8 )

SIG GND
EIA SLU
INTERFACE
MODULE
SUCH AS THE
DLV11-J

7 )
SIG GND
5 )

I
I

6~I
4 )

KEY

< 5

4 (
DLVll-KB
EIA TO 20mA
CONVERTER
BOX

I READER PLS

2 X 5 PIN
AMP CONN

READER CL OUT +

5 (
READER +
CL IN +

7 (

< 8

B~(----

(NC)

SIG GND
< 9

MATE 'N' LOK
CONN

110BAUD
1 )

CL IN-

< 7
EIA IN

2 )

CL OUT-

6 (

3 )

(NC)

J1
< 1

<10

2 X 5 PIN
BERG CONN

TO 20mA
DEVICE

J2 MATE 'N' LOK
CONNECTOR

KEY
(NO PIN)
J1 BERG
CONNECTOR

DLV 11-KA Typical Installation

227

DLV11-KA

DLVll-J TO 20 MA TERMINAL

,\~~
LT33-DC/DD/DE
OR ASR33
WITH LT33-MD
MODIFICATION
KIT_
DLVll-KA

PRISOl

NOTE
1. PRISOI IS A SERIAL LINE PAPERTAPE
LOADER.

Typical Installation

228

G653/H223

G653/H223
MMV11-A CORE RAM MEMORY

Amps

+5
Stby.
Act.

3.0
7.0

+ 12
0.2
0.6

Bus Loads

Cables

AC
1.91

None

Standard Address
Not applicable

Vectors
None

Diagnostic Programs
Refer to Appendix A.

Related Documentation
Microcomputer Processor Handbook (EB-18451-20)
11 V03 Field Maintenance Print Set (MP00094)

NOTE
Because of addressing limitations, this module is not compatible with PDP-11 /23 systems with more than 64K bytes of
memory.

229

G653/H223
Backplane Jumpers
When installing the MMV 11-A in any slot but the last slot in a backplane,
two jumpers must be inserted on the backplane to maintain the interrupt
and DMA daisy-chain grants. If the MMV 11-A is placed in an even-numbered slot, the jumpers must connect as follows.
in the option slot
preceding MMV 11-A

to the option slot
following MMV 11-A

CN2
CS2

CM2
CR2

If the MMV 11-A is placed in an odd-numbered slot, the jumpers must connect as follows.
in the option slot
preceding MMV 11-A

in the option slot
following MMV 11-A

AN2
AS2

AM2
AR2

NOTE
The MMV11-A cannot be used in the BA 11-N mounting box, in
the H9273 backplane, or in any other backplane that does not
have the LSI-11 bus pinning in the "C" and "0" slots.

230

G653/H223

SWl

SW2
SW3
SW4 (NOT USED)

G653/H223

~m-15

ADDRESS
WORD

-----y

4096 LOCATION
ADDRESS

SW3

SW2

SWI

BANK

ON
ON
ON
ON
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
ON
ON
OFF
OFF

ON
OFF
ON
OFF
ON
OFF
ON
OFF

0
1
2
3
4
5
6
7

o - 17776
37776
57776
77 776
117776
137776
157776
177776

MMV 11-A Addressing

231

J
1

BYTE
POINTER

ADDRESSES
20000 40000 60000 100000 120000 140000 160000 -

NOTE
Bank 7 is norma Ily reserved
for peripherals.

H780

H780 POWER SUPPLIES

H780 Power Supplies
Models, specifications, and basic adjustments are presented in this section. For more detailed technical information, refer to H780-C,-D,-H,-J, -K,-L
Power Supply User's Manual, EK-H780C-OP-00 1, or to Microcomputer
Handbook, EB0794853.
H780 Specifications
Input Voltage
100 Vac-127 Vac (H780-A, -C, -E, -H, -K, -M, -P)
200 Vac-254 Vac (H780-B, -D, -F, -J, -L, -N, -R)
Operation from ac lines below 100 V may cause the power supply to
overheat because of decreased air flow from the cooling fans.
Temporary Line Dips Allowed
100% of voltage, 20 ms max.
AC Inrush Current
70 A @ 127 V, 60 Hz (8.33 ms)
25 A @ 254 V, 50 Hz (10 ms)
Fuses
5.0 A fast blow for 115 Vac options
2.5 A fast blow for 230 Vac options
Input Power (Fans Included)
340 W @ full load max
290 W @ full load typical
EMI (Emission and Susceptibility)
Per DEC STD. 102.7 and VDE N-12 limits
Output Power (Combinations not to exceed 110 W)
+5V1.5A-18A
+ 12 V 0.25 A-3.5 A

232

H780
+5 V Output
Total regulation
Line regulation
Load regulation
Ripple
Dynamic load regulation

Noise
Interaction due to + 12 V
+ 12 V Output
Total regulation
Line regulation
Load regulation
Ripple
Dynamic load regulation

Noise
Interaction due to + 5 V
Overvoltage Protection
+5V

+ 12 V
Adjustments
+5 V output

+ 12 V output

5 V ±3%
±0.5%
± 1.0%
150 mV p-p (1% for f <3 kHz)
± 1.2%
di/dt = 1.5 A/s
.61=5A
1% peak at f > 100 kHz (noise is superimposed on ripple)
±0.05%

12 V ±3%
±0.25%
±0.5%
350 mV p-p (1% for f < 3 kHz)
±0.8%
di/dt = 0.5 A/ s
f < 500 Hz
.61=3A
1% peak f > 100 kHz (noise is superimposed on ripple)
±0.2%

6.3 V nominal
min. = 5.65 V
max. = 6.8 V
15 V nominal
min. = 13.6 V
max. = 16.5 V

4.05 V-6.8 V
guarantee range 4.55 V-5.65 V
10.6 V-16.5 V
guarantee range 11.7 V - 13.6 V

Backplane Signals
BPOK H
BDeOK H
BEVNT L
BHALT L
SRUN L

233

H780
Size
13.97 em w X 8.43 em h X 37.15 em 1
(5-1/2 in w X 3-1/3 in h X 14-5/8 in I)
Weight
5.90 kg (13 Ibs)

+5 V F REOUENCY
ADJUST (R96)
CW - DECREASE
CCW - INCREASE

+-12 V OUTPUT
ADJUST (R87)
ccw - INCREASE
CW - DECREASE

'----

---

+5 V OUTPUT
ADJUST (R88)
CCW - INCREASE
CW - DECREASE

- ~

.-~ ....

H780 Voltage Adjustments

234

H780
H780 Controls and Indicators
Control!
Indicator

Type

Function

DC ON

LED Indicator

Illuminates when the DC ON/OFF toggle
switch is set to ON and proper dc output
voltages are being produced by the H780.
If either the + 5 V or + 12 V output from
the H780 is faulty, the DC ON indicator
will not illuminate. This is the only indicator on the H780-K and -L slave supplies.

RUN

LED Indicator

Illuminates when the LSI-11 or PDP-11 /03
processor is in the run state (see ENABLE/HAL T).

SPARE

LED Indicator

Not used by the H780 or processor. The
H780 contains circuitry for driving this indicator for user applications.

DC ON/OFF

Two-Position
Toggle Switch

When set to ON, enables the dc outputs
of the H780. The DC ON indicator will illuminate if the H780 dc output voltages
are of proper values. If a slave supply is
connected to a master, the slave DC ON
indicator will light if the slave dc output
voltages are of proper value.
When set to OFF, the dc outputs from the
H780 are disabled and the DC ON indicator is extinguished. If a slave supply
is connected to a master, the slave DC
ON indicator will also be extinguished.

ENABLE/HALT

Two-Position
Toggle Switch

When set to ENABLE, the BHAL T L line
from the H780 to the LSI-11 bus is not asserted and the processor is in the run
mode (RUN indicator illuminated).
When set to HALT, the BHAL T L line is asserted, allowing the processor to execute
console ODT microcode (RUN indicator
extinguished).

235

H780
H780 Controls and Indicators (Cont)
Control/
Indicator
LTC ON/OFF

Type

Function

Two-Position
Toggle Switch

When set to ON, enables the generation
of the line time clock (LTC) by the H780.
When set to OFF, disables the H780 line
time clock.

AC ON/OFF
(Rear Panel)

Two-Position
Toggle Switch

When set to ON, applies ac power to the
H780.
When set to OFF, removes ac power from
the H780.

FUSE
(Rear Panel)

5 A or 2.5 A
Fast Blow

Protects H780 from excessive current.
H780-C, -H, and -K use a 5 A fuse. H7800, -J, and -L use a 2.5 A.

236

M7264-XX

M7264-XX
LSI-11 PROCESSOR MODULES

Processor option designations and processor module numbers do not have
a one-for-one correspondence. This section describes processors both in
terms of option designations (KD 11-X) and module numbers (M7264-XX).
When replacing chip sets, check both the number on the handle and etch
revision on the board. The jumpers are defined in this section; however, the
"Systems Configurations" section presents the general rules for configuring refresh reply. For details of differences between various revisions
of the processor modules, refer to Appendix B of the Microcomputer Processor Handbook, EB-18451-20. For all commercial products systems, refer to the DEC Datasystem 320 Family Service Manual, EK-DDS03-SV-001,
available in hard copy or microfiche.

Processor Model Designations
KD 11-F
Processor with 4K RAM:
M7264 Mostek 4096
M7264-AB Intel® 2104
M7264-CB Fujitsu 8224
M7264-DB Intel 2104-A

M2264-EB Mostek 4027
M7264-FB DEC 4027
M7264-HB Motorola 4027
M7264-JB Fujitsu 8227

KD 11-H (M7264- Y A)
Processor without 4K RAM
EIS/FIS option can be added:
Etch Revs C and D use KEV 11
Etch Rev D uses KEV 11-B (EIS only)
Etch Revs E and Fuse KEV 11-A
KD 11-L
Processor with on-board 4K RAM and EIS/FIS:
Etch Rev C or D KD11-F plus KEV11 or
Etch Rev E or F KD11-F plus KEV11-A

237

M7264-XX
KD 11-N
Processor without on-board 4K RAM and with EIS/FIS:
Etch Rev C or 0 KD11-H plus KEV11 or
Etch Rev E or F KD11-H plus KEV11-A
KD11-P
Processor with on-board 4K RAM and with DIS:
Etch Rev E or F M7264-BB plus KEV 11-CA
KD11-Q
Processor without on-board 4K RAM and with DIS:
Etch Rev E or F M7264-YB plus KEV11-CA

...

M7264 Specifications
Size:

Quad-height module
26.6 cm (10.5 inches) X 22.8 cm (8.9 inches)

Power:

+5V ±5%, 1.8 A + 12V ± 5%,0.8A

Bus Loads:

AC - 2.4 unit loads
DC - 1 unit load

Environment:

DEC STD 102 Class C

Related Documentation
Microcomputer Processor Handbook (EB-18451-20)
KD 11-F Field Maintenance Print Set (MP-00049-00)
KD 11-H Field Maintenance Print Set (MP-00050-00)
KD 11-P Field Maintenance Print Set (MP-00264-00)
KD11-Q Field Maintenance Print Set (MP-00357-00)
KD 11-WA Field Maintenance Print Set (MP-00569-00)
LSI-11 Maintenance Card (EK-LSI11-MC)

238

M7264-XX

E41

E47

:r:

--'

0::

«
«
Cl

M7264 ETCH REV. C, D (W7 . W11 NOT USED)

mm[H
'W1O

I
II

E58

--'

E53

:r:

«
f«
Cl

0::

z
0

W1 •
W2 •

W11 •

W3 •

• JUMPERS PRESENT ONLY
WHEN ON·BOARD MEMORY
IS PRESENT

NOTE
M7264 ETCH REV E AND AFTER

239

M7264-XX

E53

IW1*

I
I

W2*

Wll'

W3*

wlO*I

I W4

• JUMPERS PRESENT ONLY
WHEN ON-BOARD MEMORY
IS PRESENT.

M7264-BB DIBOL Processor

Jumper

Function

Insert to select resident memory bank 1.

Insert to select resident memory bank O.

Remove to enable event line (LTC) interrupt.

Remove to enable processor controlled memory refresh.

W5,}

Power-Up Modes

Mode

o
1
2

Jumpers
W6 W5
R
R
I
I

R
I
R
I

Mode Selected
PC at 24 and PS at 26, or halt mode
ODT microcode.
PC at 173000 for user bootstrap
Special processor microcode
(not implemented).

240

M7264-XX
Jumper

Function

Factory-selected biasing voltage.
Installed for VDATA = VROM.

Factory-selected biasing voltage.
Installed for VCTL = VROM.

Remove to enable reply from resident memory.

W 10

Remove to enable reply from resident memory during refresh.

W11

Enable on-board memory select.

Processor Module Jumper States
(LSI-11 Without
On-Board Memory)

(LSI-11 With 4K
On-Board Memory)

Jumper

KD11-F, -L

KD 11-P

KD 11-H, -J,
-M, -R, -S, -U

KD11-Q

W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11

R
I
R
R
R
R

R
I
R
I
R
I

R
R
R
I
R
R

R
R
R
I
R
I

R
R
I

I
R
R

* May vary with ECO level. Do not alter.

241

M7264-XX
Diagnostic Programs
The following diagnostic programs are for use with LSI-11 processors except for the limitations noted.
VKAA??

LSI-11 basic instruction test

VKAB??

LSI-11 Extended Instruction Set (EIS) test. This program can
only be run on LSI-11 CPUs with the KEV 1"1 (EIS/FIS) or
KEV 11-CA (OIBOL instruction set) options installed.

VKAC??

LSI-11 Floating Point Instruction (FIS) test. This runs only on
LSI-11 CPUs that have the KEV 11 (EIS/FIS) option (2300385).

NOTE
The KD 11-P (or Q) supports DIS (DIBOL Instruction Set) and
EIS (Extended Instruction Set) but not FIS (Floating Instruction
Set). Therefore, FIS test (-VKACAO) will not run on a D322 or
D324.

VKAO??

LSI-11 traps test. This diagnostic auto-sizes for the EIS, FIS,
and OIBOL options.
•

Older versions (Rev B 1 and below) require the setting of
a bit in the software switch register if EIS, FIS, or OIBOL
is present.

•

Rev A diagnostics will not run on 0322 or 0324 systems
because of the DIS instructions.

NOTE
See Appendix A for XXDP + multimedia aSSignments.
VKAH??

Basic system exerciser. Tests serial line unit, memory, processor, EIS/FIS, clock, and both flQPpy disks under various
conditions. Software switch register must be set for options.

VKAI??

DIS move and string instruction tests. This diagnostic tests
the OIBOL instruction set. The CPU must have KEV 11-CA
(DIS) option installed. Ref 0322, 324.

VKAJ??

DIS decimal instruction tests. This diagnostic tests the 01BOL instruction set. The CPU must have the KEV 11-CA (DIS)
option installed. Ref 0322, 324.
242

M7264-XX

________________________~607~H________

1
TYPICAL CIRCUIT SCHEMATIC
REVISION IDENTIFIER
(EG. CS-M7264 REV. H)

iii
M

":-

TYPICAL ETCH REVISION

~-IOENTIFIER (EG. ETCH REV. 0)

M7264 Revision Identifiers

M7264-YA Etch Rev C
V BB

Comments

Chip

Vendor Number DEC Number

DATA
CONTROL
MICROM-O
MICROM-1

CP 1611 8-51
CP 1621 8-451
CP 1631 8-3006
CP 16318-3010
CP 1631 8-3007

2 1-11549-00
23-001 C2-0 1
23-086A5-0 1
23-088A5-0 1
23-087 A5-0 1

-5.1
-5.1 2004 pattern
-5.1 Without ECO 2
-5.1 With ECO 2
-5.1

EIS/FIS
(if present)
KEV11

CP16318-3015

23-091 A5-0 1

-5.1

RAMs
M7264
M7264-YA

Mostek
None

21-11749

-9

243

Without ECO 2A
With ECO 2A

M7264-XX
M7264-AB, M7264-YA Etch Rev D
Chip

Vendor Number DEC Number Vaa

Comments

DATA
MICROM-O
MICROM-1

CP 1611 8-51
CP 1631 8-3010
CP 1631 8-3007

2111549-00
23-088A5-0 1
23-087 A5-0 1

-5.1
-5.1
-5.1

2004 pattern

EIS/FIS
(if present)
KEV11

CP 1631 8-3015

23-091 A5-0 1

-5.1

KEV11-8
(EIS only)

CP 1631 8-12

12-090A5-0 1

-3.9

RAMs
M7264
M7264
M7264-A8
M7264-YA

Mostek
Mostek 4096
Intel 2104
None

21-11749
21-12726-00
21-12958-01

-9
-5.1
-5.1

Without ECO 4
With ECO 4
With ECO 4
Not present

M7264-AB, M7264-YA Etch Rev E
Comments

Chip

Vendor Number DEC Number Vaa

DATA

CP 1611 8-39
PO 1611 H

21-11549-01
21-15579-00

-3.9
-3.9

With ECO 21

CP 1621 8-173
CP 1621 8-439

23-002C4
23-001C3

-3.9
-3.9

With ECO 12
Without ECO 12

MICROM-O
MICROM-1

CP 1631 8- 103
CP 1631 8-073

23-00185
23-00285

-3.9
-3.9

EIS/FIS
(if present)
KEV11-A

CP 1631 8

23-00385

-3.9

RAMs
M7264
M7264-A8
M7264-YA

Mostek 4096
Intel 2104
None

21-12726-00
21- 12958-01

-5.1
-5.1

CONTROL
2004
pattern

Not present

244

M7264-XX

M7264-BB, M7264-YB Etch Rev E
Chip

Vendor Number DEC Number Vee

Comments

DATA

CP 1611 8-51
CP 1611 8-39
PO 1611 H

21-11549
21-11549-01
21-15579-00

-5.1
-3.9
-3.9

Without ECO 5
With ECO 5
With ECO 21

CP 1621 8-451

23-001 C2-0 1

-5.1

With ECO 5

2007
pattern

CP 1621 8-439
CP 1621 8-173
CP 1621 8

23-001C3
23-002C4
23-003C3

-3.9
-3.9
-3.9

Without ECO 12
With ECO 12
With ECO 21 *

MICROM-0/1

CP 1631 8-3010

23-00BA5-0 1
23-00186
23-00286
23-00386

-5.1
-3.9
-3.9
-3.9

Without ECO 10
With ECO 10
With ECO 12
With ECO 16

23-00485
23-00585

-3.9
-3.9

3025 pattern
3026 pattern

21-12726-00

-5.1

CONTROL
2004
pattern

DIS
(KEV11-CA)
DIS 2
DIS 3
RAMs
M7264-88
M7264-Y8

Mostek 4096
None

Not present

*This part of ECO 21 applies to M7264-88 and -Y8 variations only.

245

M7264-XX
M7264-CB, M7264-DB Etch Rev E
Chip

Vendor Number DEC Number V BB

DATA
CONTROL
MICROM-O
MICROM-1

CP 1611 8-39
PO 1611 H
CP 1621 8-173
CP 16318-103
CP 1631 8-073

2 1- 11549-01
21-15579-00
23-001C4
23-00185
23-00285

-3.9
-3.9
-3.9
-3.9
-3.9

EIS/FIS
(if present)
KEV11-A

CP 1631 8

23-00385

-3.9

RAMs
M7264-C8
M7264-D8

Fujitsu 8224
Intel 2104A

21-13787-01
21-13795-01

-3.9
-3.9

Comments

With ECO 21
2007 pattern

M7264, M7264-AB, -CB, -DB, -EB, -FB, -HB, -JB Etch Rev F
Chip

Vendor Number DEC Number V BB

DATA
CONTROL
MICROM-O
MICROM-1

CP 1611 8-39
PO 1611 H
CP 1621 8-173
CP 1631 8-103
CP 1631 8-073

2 1- 11549-01
21-15579-00
23-002C4
23-00185
23-00285

-3.9
-3.9
-3.9
-3.9
-3.9

EIS/FIS
(if present)
KEV11-A

CP 1631 8-135

23-00385

-3.9

RAMs
M7264
M7264-A8
M7264-C8
M7264-D8
M7264-E8
M7264-F8
M7264-H8
M7264-J8

Mostek 4096
Intel 2104
Fujitsu 8224
Intel 2104A
Mostek 4027
DEC 4027
Motorola 4027
Fujitsu 8227

21-12726-00
21-12958-01
21-13787-01
21-13795-01
21-13735-01
2 1- 12914-01
21- 14114-01
2 1- 14475-01

246

-3.9
-3.9

Comments

With ECO 21
2007 pattern

350 ns
350 ns
350 ns
350 ns
200 ns
200 ns
200 ns
200 ns

M7264-XX
M7264-BB, M7264-YB Etch Rev F
Chip

Vendor Number DEC Number Vaa

Comments

DATA

CP 1611 B-39
PO 1611 H
CP 1621 B-173

With ECO 21

CONTROL
MICROM-O
MICROM-1

CP 1631 B-101

-3.9
-3.9
-3.9
-3.9
-3.9

With ECO 21
Not present

DIS
KEV11-CA
DIS 2
DIS 3
RAMs
M7264-BB
M7264-YB

21-11549-01
21-15579-00
23-002C4
23-003C3
23-003B6

Mostek 4096
None

23-004B5
23-005B5

-3.9
-3.9

21-12726-00

-5.1

350 ns
Not present

Circuit Schematic/ECO History
Etch
Rev

CS
Rev

ECO
No.

Change value of C8 in clock pulse generator
circuit from 150 pF to 47 pF.

1. Logic changed to clock BRPL Y into reply flipflop with an earlier timing signal.

Change
(Basic model)

2. Logic changed to disable BBS7 L for the duration of BDMG L or BSACK L assertion.
3. SRUN L signal decoded and applied to backplane.
4. ECO 2A created M7264-Y A.
D

Logic changes for etch Rev C boards.

Circuit changes implemented to provide -5 V.
Documentation updated by ECO 4A.

247

M7264-XX
Circuit Schematic/ECO History (Cont)
Etch
Rev

CS
Rev

ECO
No.

New module layout. (OM A synchronization logic
changed.) Add jumpers for resident memory reply
and refresh reply. Add factory jumpers for Vaa selection. Logic change to allow external selection
of resident memory. Add factory adjustment
(R 15) for setting refresh clock to 1.6 ms. Terminate bus lines AA1, AB1, AC1, AD1, and BP1. Replace E53, E58, E63, E70 with -3.9 V chips.

1. Change DMA synchronization logic.
2. Terminate E45-12, -13 to +3 V.

Correct documentation errors.

Change R44 from 22n to 27n.
Change R45 from 10n to 22n.

01 ,E 1 9

Logic change implemented to inhibit BBS7 L during memory refresh.

F1,H1

Canceled by ECO 9A.

C
0
E

D2,E2 10
F2,H2
P

Change

1. Logic change implemented to inhibit BBS7 L
during memory refresh.
2. Removed
scheme.

OM A/refresh

alternate

cycle

3. Changed M7264-BB to -3.9 V LSI chips.
4. Documentation corrrected by ECOs 10A and
10B.
E

Created M7264-YB.

Phased out 23-001 C3 control chip and replaced
it with 23-002C4.

Replaced 23-001B6 microm with 23-002B6.

1. Created M7264-CB, -DB.

248

M7264-XX
Circuit Schematic/ECO History (Cont)
Etch
Rev

CS
Rev

ECO
No.

2. Operating frequency changed to 2.5 MHz
min.-2.631 MHz max.

Routed IF CLR to pin AF 1 from CH 1.

Replaced 23-002B6 microm with 23-003B6.

1. Released etch Rev F.

Change

2. Refresh 625 ± 20 Hz adjustment.
3. Pins 22 and 24 of E75 tied to phase 2 and
phase 4 for WCS.
4. SRUN buffered to CH 1, AF 1.
5. BPOK line deglitched.
6. Chip set changes (see data sheets).
7. Documentation updated by ECO 17 A.
C

D3,E3 18
F3,H3

Added resistors R24, R25, R26, and R27 to D pull
up BDAL 16 and BDAL 17 (formerly BAD 16 and
BAD 17). This ECO is normally required in systems using DRV 11-Bs or MSV 11-Ds.

Created M7264-EB, -FB, -HB, and -JB.

Create M7264-VC document changes.
1. Delete R50.
2. Add R60.

Use 1611 H (21-15579-00) data chip instead of
1611 A (21-14549-01).
Use 23003C3 control chip instead of 23002C4.
Change R45 from 22Q to 15Q and clock frequency to 2.47 MHz for -VB and -BB only.

249

M7269

M7269
BUS INTERFACE FOR RKV11-D DISK DRIVE CONTROLLER

Amps

Bus Loads

Cables

+5
+ 12
1.8max.
0

AC
DC
1.93

(2) BC05L + M993- Y A

Standard Address
RKDS
RKER
RKCS
RKWC
RKBA
RKDA
RKDB

(Drive Status)
(Error)
(Control/Status)
(Word Count)
(Bus Address)
(Disk Address)
(Data Buffer)

177400
177402
177404
177406
177410
177412
177416

Vector
220

Diagnostic Programs
Refer to Appendix A.

NOTE
The logic test programs should be run first, then the dynamic
test, and finally the performance exerciser.
Related Documentation
RKVII-D Disk Drive Controller User's Manual (EK-RKV11-0P-001)
RKVII-Disk Drive Controller Technical Manual (EK-RKV11-TM-001)
Field Maintenance Print Set (MP00223)
RK05/RK05J/RK05F Disk Drive Maintenance Manual (EK-RK5JF-MM-00 1)
RK05/RK05J Disk Drive Preventive Maintenance Manual
(EK-RK05J-PM- 001)
RK05F DEC Disk Drive Preventive Maintenance Procedure
(ED-RK05F-PM- 001)
Microcomputer Interfaces Handbook (EB-20 175-20)

250

M7269

c
c

1
1

JUMPER SETTINGS
INSTALLEO - Wl, W2, W3, W6, W7, Wll, W17
REMOVED - W4, W5, W8, W9, Wl0, W12, W13, W14, W15, W16

INTERRUPT
VECTOR
JUMPERS

NOTE:
NORMALLY INSTALLED
JUMPERS ARE SHOWN AS
SOLID LINES.

251

M7269
7

~ .---~--~ ----~--- ---~~~--. ~
15

I I I I I I I I I
::::~ULE ~ T
wr wr

TTTiT

CONFIGURED ~ I
ADDRESS (177400)

I· INSTALLED
R. REMOVED

DEVICE ADDRESS
MR-0803

I • INSTALLED
R· REMOVED

VECTOR ADDRESS
MR-0804

Jumper settings on the three RKV 11-0 modules are identical to those in
the standard RK 11-0 configuration. A breakdown is given below for reference. There are no jumpers on M7268.

Module

Installed

Removed

M7254 *
M7255* *
M7256

W1, W4, W6, W7
W1, W2, W6
W2, W5, W7

W2, W3, W5
W3, W4, W5
W1, W3, W4, W6, W8

Interrupt priority jumper (BR4-7) in socket E8 is not required since the
RKV 11-0 was designed for only single-line interrupt scheme.
2.88 MHZ crystal used OEC PN 18-10694-3.

252

M7269

~oW20

0--0

M7254

253

M7269

~W6
W4

M7255
MR·08in

254

M7269

roo
W7

o
W2

W8
o

M7256

255

M7269
RKV 11-0 Module Utilization
M7254

STATUS
CONTROL

M7255

DISK
CONTROL

M7256

DATA
PATHS

M7268

BUS
ADAPTER

H780POWER
SUPPLY

MR-0762

Drive Status Register (RKDS)
Address =

177400

NOTE
This register is a read-only register, and contains the selected
drive status and current sector address.

Bit Definitions
Bit

Function

00-03

Sector Counter (SC) - These four bits are the current sector address of the selected drive. Sector address 00 is defined as the
sector following the sector that contains the index pulse.

Sector Counter Equals Sector Address (SC = SA) - Indicates
that the disk heads are positioned over the disk address currently held in the sector address register.

Write-Protect Status (WPS) - Sets when the selected disk is in
the write-protected mode.

Read/Write/Seek Ready (R/W /S ROY) - Indicates that the selected drive head mechanism is not in motion, and that the drive
is ready to accept a new function.

Drive Ready (DRY) - Indicates that the selected disk drive complies with the following conditions.

256

M7269
Bit Definitions (Cont)
Bit

Function
1.
2.
3.
4.
5.

6.
7.

The drive is properly supplied with power.
The drive is loaded with a disk cartridge.
The disk drive door is closed.
The LOAD/RUN switch is set to RUN.
The disk is rotating at a proper speed.
The heads are properly loaded.
The disk is not in a DRU (bit 10 or RKDS) condition.

Sector Counter OK (SOK) - Indicates that the sector counter
operating on the selected drive is not in the process of changing, and is ready for examination. If this bit is not set, the sector
counter is not ready for examination, and a second attempt
should be made.

Seek Incomplete (SIN) - Indicates that due to some unusual
condition, to seek function cannot be completed. Can be accompanied by RKER 15 (drive error). Cleared by a drive reset
function.

Drive Unsafe (DRU) - Indicates that an unusual condition has
occurred in the disk drive, and it is unable to properly perform
any operations. Reset by setting the RUN/LOAD switch to
LOAD. If, when the switch is returned to RUN, the condition recurs, an inoperative drive can be assumed, and corrective maintenance procedures should begin. Can be accompanied by
RKER 15 (drive error).

RK05 Disk on Line (RK05) - Always set, to identify the selected
disk drive as RK05.

Drive Power Low (DPL) - Sets when an attempt is made to initiate a new function, or if a function is actively in process when
the control senses a loss of power to one of the disk drives. Can
be accompanied by RKER 15 (drive error). Reset by a BUS INIT
or a control reset function.

13-15

Identification of Drive (ID) - If an interrupt occurs as the result of
a hardware poll operation, these bits will contain the binary representation of the logical drive number that caused the interrupt.

257

M7269
Error Register (RKER)
Address =

177402
NOTE
This is a read-only register.

Bit Definitions
Bit

Function

Write Check Error (WCE) - Indicates that an error was encountered during a write check function as a result of a faulty bit
comparison between disk data and memory data. Clears upon
the initiation of a new function. This is a soft error condition.

Checksum Error (CSE) - Sets while performing a read function
as a result of a faulty recalculation of the checksum. Cleared
upon the initiation of any new function. This is a soft error condition.

02-04

Unused.

The remaining bits of the RKER are all hard errors, and are cleared only by
a BUS INIT or a control reset function.

Bit Definitions
Bit

Function

Nonexistent Sector (NXS) - Indicates that an attempt was
made to a sector address greater than 138 .

Nonexistent Cylinder (NXC) - Indicates that an attempt was
made to initiate a transfer to a cylinder address greater than
312 8 .

Nonexistent Disk (NXD) - Indicates that an attempt was made
to initiate a function on a nonexistent drive.

Timing Error (TE) - Indicates that a loss of timing pulses for at
least 5 JiS has been detected.

258

M7269
Bit Definitions (Cont)
Bit

Function

Data Late (OL T) - Sets during a write or write check function
when the multibuffer file is empty and the operation is not yet
complete. Sets during a read function when the multibuffer file is
filled and the operation is not yet complete.

Nonexistent Memory (NXM) - Sets if memory does not respond
with a RPL Y within 20 jlS of the time when the RKV 11-0 becomes bus master during a OMA sequence. Because of the
speed of the RK05 disk drive, it is possible that NXM will be accompanied by RKER 09 (data late).

Programming Error (PGE) - Indicates that RKCS 10 (format)
was set while initiating a function other than read or write.

Seek Error (SKE) - Sets if the disk head mechanism is not properly positioned while executing a normal read, write, read
check, or write check function. The control checks 16 times before flagging this error. A simple jumper change will force the
control to check just once.

Write Lockout Violation (WLO) - Sets if an attempt is made to
write on a disk that is currently write protected.

Overrun (OVR) - Indicates that during a read, write, read check,
or write check function, operations on sector 138, surface 1 of
cylinder address 3128 were finished, and the RKWC has not yet
overflowed. This is essentially an attempt to overflow out of a
disk drive.

Drive Error (ORE) - Sets if a function is either initiated or in process, and
a.

one of the drives in the system senses a loss of either ac or
dc power; or

the selected drive is not ready, or is in some error condition.

259

M7269
Control Status Register (RKCS)
Address =

177404

UNUSED

UNUSED
CP·3139

Bit Definitions
Bit

Function

Go - This bit can be loaded by the operator and causes the control to carry out the function contained in bits 01-03 of the
RKCS (functions). Remains set until the control actually begins
to respond to go, which may take from 1 /-ts to 3.3 ms, depending on the current operation of the selected disk drive (to protect the format structure of the sector). Write only.

01-03

Function - The function register, or function bits, are loaded
with the binary representation of the function to be performed by
the control when a GO command is initiated. These bits are
loaded by the program and cleared by BUS INIT. Read/write.
The binary codings are as follows.

04, 05

Bit 3

Bit 2

Bit 1 Operation
0
1
0
1
0
1
0

0
0

()

1
0
0

Control Reset
Write
Read
Write Check
Seek
Read Check
Orive Reset
Write Lock

Unused. The RK 11-0 uses these bits. Since the POP-11 /03 bus
structure has no provision for extended addressing, no connection is made to the bus from these bits on the RKV11-0.
They will respond as two unused read/write bits in the status
re~ister; but, like the RK 11-0 they, will increment should the
RKBA overflow.

260

M7269
Bit Definitions (Cont)
Bit

Function

Interrupt on Done Enable (IDE) - When set causes the control
to issue a bus request and interrupt to vector address 220 if:
a.
b.
c.
d.

a function has completed activity
a hard error is encountered
a soft error is encountered and bit 08 of the RKCS (SSE) is
set
RKCS 07 (ROY) is set and go is not set.

Read/write.
07

Control Ready (ROY) - Indicates that the control is ready to
perform a function. Set by INIT, a hard error condition, or by the
termination of a function. Cleared by go being set. Read only.

Stop on Soft Error (SSE) - If a soft error is encountered when
this bit is set:
a.

all control action will stop at the end of the current sector if
RKCS 06 (IDE) is reset, or

all control action will stop and a bus request will occur at
the end of the current sector if RKCS 06 (IDE) is set.

Read/write
09

Unused.

Format (FMT) - FMT is under program control, and must be
used only in conjunction with normal read and write functions.
Used to format a new disk pack or to reformat any sector
erased due to control or drive failure. Alters the normal write operation, under which the header is rewritten each time the associated sector is rewritten, in that the head position is not cbecked for proper positioning before the write. Alters the normal read
operation in that only one word, the header word, is transferred
to memory per sector. For example, a three-word read function
in format mode will transfer header words from three consecutive sectors to three consecutive memory locations for
software checking. Read/write.

Inhibit Incrementing the RKBA (IBA) - Inhibits the RKBA from incrementing during a normal transfer function. This allows data
transfers to occur to or from the same memory location throughout the entire transfer operation. Read/write.

Unused.

261

M7269
Bit Definitions (Cont)
Bit

Function

Search Complete (SCP) - Indicates that the previous interrupt
was the result of some seek or drive reset function. Cleared at
the initiation of any new function. Read only.

Hard Error (HE) - Sets when any of RKER 05-15 are set. Stops
all control action, and processor reaction is dictated by RKCS
06 (IDE), until cleared, along with RKER 05-15, by INIT or a control reset function. Read only.

Error (ERR) - Sets when any bit of the RKER sets. Processor
reaction is dictated by RKCS 06 and RKCS 08 (IDE and SSE).
Cleared if all bits in the RKER are cleared. Read only.

Word Count Register (RKWC)
Address =

WC16: ·

177406
14

;

; :

:wcoo

: :

CP-3140

Bit Definition
Bit
00-15

Function
WCOO-WC15 - The bits in this register contain the 2's complement of words to be affected or transferred by a given function. The register increments by 1 after each word transfer.
When the register overflows (all WC bits go to 0), the transfer is
complete and RKV 11-0 operation is terminated at the end of the
present disk sector. However, only the number of words specified in the RKWC are transferred. Read/write.

Current Bus Address Register (RKBA)
Address =

177410
13

Bit
00-15

Bit Definition
Function
BAOO-BA 15 - The bits in this register contain the bus address
to or from which data will be transferred. The register is incremented by two at the end of each transfer. Read/write.
262

M7269
Disk Address Register (RKDA)
Address =

177412

NOTE
This register will not respond to commands while the controller
is busy_ Therefore, RKDA bits are loaded from the bus data
lines only in the control ready (ROY - bit 07 of the RKCS) state,
and are cleared by BUS INIT and control reset. The RKDA is incremented automatically at the end of each disk sector.

Bit Definitions
Bit

Function

00-03

Sector Address (SA) - Binary representation of the disk sector
to be addressed for the next function. The largest vaJid address
(or number) for the sector address is 138 .

Surface (SUR) - When set, enables the lower disk head so that
operation is performed on the lower surface; when reset, enables the upper disk head.

05-12

Cylinder Address (CYL ADDR) - Binary representation of the
cylinder address currently being selected. The largest valid address or number for the cylinder address is 312 .

13-15

Drive Select (DR SEL) - Binary representation of the logical
drive number currently being selected.

263

M7269
Data Buffer Register (RKDB)
Address =

177416

: : : :

(15

: : : : : :
Bit Definition

Bit

Function

00-15

D800-D815 - The bits of this register work as a general data
handler in that all information transferred between the control
and the disk drive must pass through this register. Loaded from
the bus only while the RKV 11-0 is bus master during a OMA sequence. Read only.

NOTE
Address 177414 is unused.

264

M7269

TOM993·YA
tRK05}

TO M7269
tLSI·"

BUS}

M7268

M993·YA
TOP

GROOVE

~ ~~----------------------~~'=::JD30WN
\-CTJ ~

TOP~I____________________~

M7268
M7259
~--------~~-.~~

TOP
GROOVE SIDE

BC05L
BC05L
TOP~

__________________

MR·0763

RKV 11-0 Cable Connection

265

M7270

M7270
LSI-11/2 PROCESSOR MODEL DESIGNATIONS

KD11-HA
KD11-HB
KD11-HC
KD11-HD
KD11-HF
KD11-HJ
KD11-HU

Dual-height LSI-11 processor without memory
KD 11-HA + MSV 11-DB 8K word memory
KD 11-HA + MSV 11-DC 16K word memory
KD 11-HA + MSV 11-00 32K word memory
KD 11-HA + MSV 11-DA 4K word memory
KD 11-HA + MMV 11-A 4K word core memory
KD11-HA + MRV11-BA

KD11-XA
KD11-XB
KD11-XC
KD11-XD
KD11-XH
KD11-XJ

KD 11-HA, 2 MSV 11-ED 64K word memory
KD 11-HA, 4 MSV 11-ED 128K word memory
KD 11-HA, 9 MSV 11-ED 288K word memory
KD11-HA, 3 MSV11-DD
KD11-HA, 3 MSV11-DC
KD11-HA, 3 MSV11-DB

M7270 Specifications
Size:

Double-height module

Dimensions:

13.34 cm (5.25 in) X 22.8 cm (8.9 in)

Power:

+5 Vdc ±5%, 1 A
+ 12 Vdc ± 5%, .22 A

Bus Loads:

AC - 1.7 unit loads
DC - 1 unit load

Related Documentation
Microcomputer Processor Handbook (EB-18451-20)
KD 11-HA Print Set (MP-00495)
LSI-11 Maintenance Card (EK-LSI11-MC)

266

(Heathkit)
(Heathkit)
(Heathkit)
(Heathkit)
(Heathkit)
(Heathkit)

M7270

EVNTINTERRUPT
INSTALLED DISABLE
REMOVED = ENABLE

W3
Wl

>(KEVll OP~~6N SOCKETlI
\>

MASTER CLOCK
ENABLE
(ALWAYS INSTALLED)

MICROM 1

MICROM 0

CONTROL

DATA PATH

~~}- .------------------------~

POWER·UP MODE
SELECT

NOTE
TO DISABLE WAKEUP CIRCUIT,
REMOVE CAPACITOR Cl WHEN
USED WITH SEQUENCER POWER
SUPPLIES. (BAll·MAND BAll·N)

M7270 Jumpers and Socket Locations

267

M7270
Jumper
W1

Always installed - master clock enabled.

Removed - external event interrupt (line clock) enabled.
Installed - external event interrupt disabled.

Mode Selected
PC at 24 and PS at 26, or halt mode (mode 0).
ODT microcode (mode 1).
PC at 173000 for user bootstrap (mode 2).
Special processor microcode; not implemented (mode 3).

R·

I
I

R
I

Diagnostic Programs
The following diagnostic programs are for use with LSI-11 processors except for the limitations noted.
VKAA??

LSI-11 basic instruction test.

VKAB??

LSI-11 Extended Instruction Set (EIS) test. This program can be
run only on LSI-11 CPUs with the KEV 11 (EIS/FIS) or KEV 11-CA
(DIBOL instruction set) options installed.
.

VKAC??

LSI-11 Floating Point Instruction (FIS) test. This runs only on
LSI-11 CPUs that have the KEV 11 (EIS/FIS) option (23-00385).

VKAD??

LSI-11 traps test. This diagnostic auto-sizes for the EIS, FIS,
and DIBOL options.
a.

Older versions (Rev B 1 and below) require the setting of a
bit in the software switch register if EIS, FIS, or OIBOL is
present.

Rev A diagnostics will not run on 0322 or 0324 systems because of the DIS instructions.

NOTE
See Appendix A for XXDP + multimedia assignments.
VKAH??

Basic system exerciser. Tests serial line unit, memory, processor, EIS/FIS, clock, and both floppy disks under various conditions. Software switch register must be set for options.

• R = jumper removed; I = jumper installed.

268

M7270
Chip

Vendor Number

DEC Number Vee

DATA

CP 16118-39

CONTROL
MICROM-O
MICROM-1

CP 1621 8-173
CP 16318-103
CP 1631 8-073

2 1-11549-01
21-15579-00
23-002C4
23-00185
23-00285

-3.9
-3.5
-3.9
-3.9
-3.9

EIS/FIS
(if present)
KEV11-A

CP 1631 8-135

23-00385

-3.9

Comments

With ECO 6
2007 pattern

ECOs for Etch Rev E
CS Rev

ECO No.

Change
1. Remove blanking pulse.
2. Generate clock driver Vee from + 12 V.
3. Move K 1 MST8 L from E34-3 to E34-4.
4. Relayout board.

Change C31
10- 10279-0.

and C32 from

Change Augat socket to 8urndy socket.

Allow customer to remove C81.

Change R18 from 13-10317 to 13-10522.

Alternate part 19-14282-01 may be used to replace
E37.

Change part E30 from 21-11549-01 to 21-15579-00.

269

10-12312-01 to

M7940

M7940
DLV11 SERIAL LINE UNIT

Amps

Bus Loads

+ 12

1.0
(1.6 max.)

0.18
(0.25 max.)

AC
2.48

Cables

DC
BC05M for 20 rnA
BC05C for Bell 103 modem and
EIA
Be05C plus H312A or H308 for
EIA terminal

Standard Addresses

RCSR
RBUF
XCSR
XBUF

Console

Second
Terminal

Modem
(Auto Mode)

177560
177562
177564
177566

176500
176502
176504
176506

175610
175612
175614
175616

Vectors

Receiver Interrupt
Transmitter Interrupt

Console

Second
Terminal

Modem

60
64

300
304

Diagnostic Program
Refer to Appendix A.

270

M7940
NOTE
The DECX module DLA? requires a wraparound connector to
run. The connector is not available and must be made up from
the following parts:
Berg connector
Berg pins
No. 22 AWG wire

PN 12-10918-15
PN 12-10089-07
PN 90-07350-00.

Connect the following pins:
F to J
M to E

Related Documentation
Field Maintenance Print Set (MP00055)
Microcomputer Interfaces Handbook (EB-20175-20)

271

M7940

TP1

i
•• J ••

,'T·,

TP2

«
H

INSERT .005J..1F CAPACITOR
(PN10·01765) WHEN THE
SERIAL LINE DEVICE IS A
TE LETYPEWR ITE R
(L T33 OR L T35)

I.LI

I'-UlIOVIfl

>_NID
1.LI1D1D1f)1L

»»>

ILZZNZ

II111

11111

1111111111
GlOlO:;::N
«««« ««;;(<(<(

IflVIOUI

::r

I.LI

10..

CP- leol

272

BDAl
BITS ..-:1=-5__r_-------r------~.:..-----_r_-----__r_-------':.......,

I I
1

I 1 I

'-----------...
BBS7l
' l(U

ADDRESS JUMPERS:
IN STA llED ,0
REMOVED' 1

lJl

O~ CSR

}

1 - DATA BUFFER

~: ~~~~I~~~TER

(PART OF
FUNCTION
DECODING)

RANGE' 160000. -177776.

DL V 11 Address Bits

BDAl
BITS

15
0

I"-

II'l

VECTOR JUMPERS:
INSTAllED=O
REMOVED = 1

r<l

> 1

0 = RECEIVER
1 = TRANSMITTER

RANGE =0- 3748
Cp-1803

DL V 11 Interrupt Vector Bits

M7940
DLV11 SLU Factory Jumper Configuration
Jumper
Designation

Jumper
Status

A3
A4
A5
A6
A7
A8
A9
A10
A 11
A12

I
R
R
R
I
R
R
R
R
R

This arrangement of jumpers A3 through A 12 implements the octal device address 17756X,
which is the assigned address for the console
device SLU. The least significant digit is hardwired on the module to address the four SLU device registers as follows:

V3
V4
V5
V6
V7

I
R
R
I
I

This jumper arrangement implements the interrupt vector addresses 60 for received data and
64 for transmitted data.

NP
2SB
NB2
NB1

R
R
R
R

No parity.
Two stop bits (installed on 0322 and 0324).
Eight data bits.

PEV
FEH

R
I

EIA

Even parity if NP installed.
Halt on framing error (removed on 0322 and
0324).
12 V EIA operation disabled (installed on 0322
and 0324).

FRO
FR1
FR2
FR3

R
R
R
R

CL1

Function

x = 0, RCSR address
X = 2, Receive data register address
X = 4, XCSR address
X = 6, Transmit data register address.

110 baud rate selected.

20 rnA current loop active receiver and transmitter selected.

CL2
CL3
CL4

274

M7940
Number of Data Bits

5
6
7
8

NB1

NB2

Installed
Removed
Installed
Removed

Installed
Installed
Removed
Removed

Number of Stop Bits Transmitted
2SB installed = one stop bit.
2SB removed = two stop bits.
Parity Transmitted
NP removed = no parity bit.
NP and PEV installed = odd parity.
NP installed and PEV removed = even parity.
Framing Error
FEH installed = halt on framing error (console).
FEH removed = do not halt on framing error.

Unit

Address Jumpers

Address

A12 A11
Console
177560
First Option
176500
Second Option 176510
Third Option
176520
175610
Modem

Unit

Console
First Option
Second Option
Third Option
Modem

Vector

60
300
310
320
300

R
R
R
R
R

A10 A9 A8 A7 A6 A5 A4 A3
R
R
R
R
I

R
I
I
I
R

I
I
I
I
R

R
R
R
R
R

R
R
R
R
I

R
I
I
I
I

R
I
I
R
I

I
I
R
I
R

Vector Jumpers
V7

I
R
R
R
R

R
I
I
I
I

R
I
I
R
I

I
I
R
I
I

275

M7940
Baud Rate Selection
Baud Rate

FR3

FR2

FR1

FRO

50
75
110
134.5
150
200
300
600
1200
1800
·2400
·2400
4800
9600

I
I

R
R

R
R
R
R
R
R

R
R
R

R
R

I
I

R
R

R
I

R
R
R

I
I

R
R

R
R
R
R
I
I

R
I

• Either configuration may be used. Use second
configuration for D322 and D324.

Active transmit = CL3 and CL4 installed.
Active receive = CL 1 and CL2 installed.

NOTE
CL2 and CL3 are 180 Q resistors.

276

M7940
USE BC05M CABLE

L-.-r~-==~_1 ~ Hj y-6-1]
..

0 \ 00

o
o

Passive transmit = CL3 and CL4 as in preceding figure.
Passive receive = CL 1 and CL2 as in preceding figure.

NOTE
When configured for passive operation, the (+) and (-) lines
are reversed. Use a BC05F cable.
USE BCOlv OR BC05C CABLE

I
Jumper EIA must be inserted for EIA operation. Jumpers CL 1 through CL4
do not have to be removed when EIA is inserted.

RECE IVER
INTERRUPT
ENABL E
(READ/WRITE)

Receiver Control/Status Register (RCSR)
277

M7940
RCSR Bit Definitions
Bit

Function

Dataset Status - Set when CARRIER or CLEAR TO SEND and
DATA SET READY signals are asserted by an EIA device. Readonly.

14-08

Not used. Read as O.

Receiver Done - Set when an entire character has been received and is ready for input to the processor. This bit is automatically cleared when RBUF is addressed or when the BDCOK
H signal goes false (low). A receiver interrupt is enabled by the
DL V 11 when this bit is set and receiver interrupt is enabled (bit
6 is also set). Read-only.

Interrupt Enable - Set under program control when it is'desired
to generate a receiver interrupt request when a character is
ready for input to the processor (bit 7 is set). Cleared under program control or by the BINIT signal. Read/write.

05-01

Not used. Read as O.

Read Enable - Set by program control to advance the paper
tape reader on a teletypewriter device to input a new character.
Automatically cleared by the new character's start bit. Write
only.

(NOT USED)

DATA AND PARITY
(5-7 BIT DATA IS RIGHT JUSTIFIED. PARITY IS BIT 7.
NO PARITY BIT IS PRESENT WHEN 8-BIT DATA IS USED.I

Receiver Buffer Register (RBUF)

RBUF Bit Definitions
Bit

Function

15-08

Not used. Read as 0,

07-00

Contains five to eight data bits in a right-justified format. MSB is
the optional parity bit. Read only.

278

M7940

XCSR

TRANSMIT
INTERRUPT
ENABLE
(READ/W RITE)

Transmitter Control/Status Register (XCSR)

XCRS Bit Definitions
Bit

Function

15-08

Not used. Read as O.

Transmit Ready - Set when XBUF is empty and can accept another character for transmission. It is also set during the powerup sequence by the BOCOK H signal. Automatically cleared
when XBUF is loaded. When transmitter interrupt is enabled (bit
6 also set), an interrupt request is asserted by the OL V 11 when
this bit is set. Read only.

Interrupt Enable - Set under program control when it is desired
to generate a transmitter interrupt request when the OL V 11 is
ready to accept a character for transmission. Reset under program control or by the BINIT signal. Read/write.

05-01

Not used. Read as O.

Break - Set or reset under program control. When set, a continuous space level is transmitted. BINIT reset this bit. Read/write.

XBUF~I ~ ~~~~ ~ ~ ~ ~~ ~ ~ ~ ~~ ~ ~
__

~ •• ----~---------------"----------

(NOT USED)

DATA

Transmitter Buffer Register (XBUF)

XBUF Bit Definitions
Bit

Function

15-08

Not used.

07-00

Continuous five to eight right-justified data bits. Loaded under
program control for serial transmission to a device. Write only.

279

M7941

M7941
DRV11 PARALLEL LINE UNIT

Amps
+5
0.9
(1.6 max.)

Bus Loads
+ 12
0

AC
2.80

DC
1.0

Cables

(2) BC07D
(2) BC08R

Standard Addresses

DRCSR
DROUTBUF
DRINBUF

First
Device

Second
Device

MINC/
DECLAB

167770
167772
167774

167760
167762
167764

171770
171772
171774

300,
304

310
314

370
374

Vectors
Interrupt A
Interrupt B

Diagnostic Programs
Refer to Appendix A.
NOTE
Full testing requires a BC08-R wraparound cable for VKAF??
and ORA?

Related Documentation
ADVll-A, KWVll-A, AAVll-A, DRVll User's Manual (EK-ADV11-0P)
Field Maintenance Print Set (MP00054)
Microcomputer Interfaces Handbook (EB-20 175-20)

280

M7941

c
c

U
J1

U
J2

I V~;R--:U-;;~--'
I
I
I V4---VS I

I
I
I V3---V6 I
L ___ -:::-:..V?J

i ~DDRESS:;UMPERS- i
I
I

A3-A4--

--A9
--Al0

SLl \, SL2

o---7t---o

I
I

:LA...!=-::.
H= _____
==ta:...J

OPTIONAL EXTERNAL
CAPACITOR

"R-oaoe

281

M7941

~--'

BBS7 L
"!L1

~----------------.-.-~~----~~----.---'

ADDRESS JUMPERS
'NSTALLED -0
REMOvED "

I
L

BYTE SELECT
"h,qhbY'.!S-'51

0, 'ow by'.! 0 -7 I
REGISTE R
OOX ' DRCSR
0' X - DROUTBUF
'OX'DR'NBUF
, , X ' NO RESPONSE

~ ~ J h1 L

~-------'

(DRCSR-151
REQUEST I NG DEVICE
0' REQ A
1 • REO B

VECTO R JUMPERS:
INSTALLED·O
REMOVED -,

DRV11 PLU Factory Jumper Configuration
Jumper
Designation

Jumper
State

A3
A4
A5
A6
A8
A9
A10
A 11
A12

R
R
R
R
R
R
R
R
I
I

This arrangement of jumpers A3 through A 12 assigns the device address 16777X to the PLU.
This address is the starting address of a reserved block in memory bank 7 which is recommended for user device address assignments.
The least significant digit X is hardwired on the
module to implement the -three PLU device addresses as follows:

V3
V4
V5
V6
V7

I
I
I
R
R

This factory-installed jumper configuration implements the two interrupt vector addresses 300
and 304 for use as defined by application requirements.

SL1
SL2

R
R

These jumper posts are provided for the installation of an external capacitor.

Function

X = 0, DRCSR address
X = 2, Output buffer address
X = 4, Input buffer address.

282

M7941
External Capacitor
The pulse width of NEW DATA READY and DATA TRANSMITTED may be
modified by installing an external capacitor. Note that the trailing edge of
one of these two pulses must be used to clear interrupt requests.

Capacitor (}1F)

Pulse Width (ns)

None (as shipped)

350
750
1550
2330
3150

.0047
.01
.02
.03

NOTE
Any system containing a REV11 and a DRV11 that has a capacitor to extend NEW DATA READY and DATA TRANSMITTED
greater than 1800 ns may cause the REV 11 to hang the system
unless the REV 11 is at ECO 5 level or greater (Circuit Schematic Rev K).

DRCSR

CSRO
(READ/WRITE)

Control/Status Register
DRCSR Bit Definitions
Bit

Function

REQUEST B - This bit is under control of the user's device and
may be used to initiate an interrupt sequence or to generate a
flag that may be tested by the program.

14-08

Not used. Read as O.

REQUEST A - Performs the same function as REQUEST B (bit
15) except that an interrupt is generated only if INT ENB A (bit
06) is also set.
When the maintenance cable is used, the state of REQUEST A
is identical to that of CSRO (bit 00). Cleared by INIT when in
maintenance mode. Read-only.

283

M7941
DRCSR Bit Definitions (Cont)
Bit

Function

INT ENB A - Interrupt enable bit. When set, allows an interrupt
request to be generated, provided REQUEST A (bit 07) becomes
set.

INT ENB B - Interrupt enable bit. When set, allows an interrupt
sequence to be initiated, provided REQUEST B (bit 15) becomes
set.

04-02

Not used. Read as o. Can be loaded or read by the program.
Cleared by INIT. Read/write.

CSR 1 - This bit can be loaded or read (under program control)
and can be used for a user-defined command to the device (appears only on connector no. 1).
When the maintenance cable is used, setting or clearing· this bit
causes an identical state in bit 15 (REQUEST B). This permits
checking operation of bit 15 which cannot be loaded by the program.
Can be loaded or read by the program. Cleared by INIT.
Read/write.

CSRO - Performs the same functions as CSR 1 (bit 01) but appears only on connector no. 2.
When the maintenance cable is used, the state of this bit controls the state of bit 07 (REQUEST A).
Cleared by INIT. Read/write.

DROUTBUF

DATA OUT
(R EADI WRITE)
MR-Oatt

Output Data Buffer Register (DROUTBUF)

DROUTBUF Bits 15-00
Output Data Buffer - Contains a full 16-bit word or one or two 8-bit bytes:
high byte = 15-8; low byte = 7 -0.
Loading is accomplished under a program-controlled DATO or DATOB bus
cycle. It can be read under a program-controlled DATI cycle.
284

M7941
DRIN8UF

DATA IN
(READ ONLY)

Input Data Buffer Register (DRINBUF)

DRINBUF Bits 15-00
Input Data Buffer - Contains a full 16-bit word or one or two 8-bit bytes. The
entire 16-bit word is read under a program-controlled DATI bus cycle.

285

M7942

M7942
MRV11-AA READ-ONLY MEMORY

Amps

WIO PROMs
(0.6 max.)
With PROMs
(4.1 max.)

+5
0.4

-12
0

2.8

Bus Loads

Cables

AC
1.84

none

DC
1.0

Standard Addresses
Module is shipped with all jumpers installed, selecting bank 0 addresses
(0-1777).

Vectors, Diagnostic Program, Exerciser Program
None

Related Documentation
Field Maintenance Print Set (MP00066)
Microcomputer Processor Handbook (EB-18451-20)

NOTES
1.

Jumpers W8-W14 select chip set types (512 or 256).

Any row not populated with PROMs must have the BRPL Y L
jumper (WO-W7) removed.

286

M7942
MRV11-AA Address Word Formats
Bank Select
Bank

W15

W16

W17

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

2
3
4
5
6
7

R
R
~
~

NOTE
Because of addressing limitations, this module is not compatible with PDP-11/23 systems with more than 64K bytes of
memory.

512X4
PROM/ROM
CHIPS

~15~

I I

________~______~________. -______~______~

'-;".........""'7""""'-7-':::======::':==~=======::'::::::711
W~5
4096 - LOCATION ADDRESS
BYTE
W16
(WB-W10 INSTALLED; W11-W14 REMOVED)
POINTER

I wh

4K ADDRESS
SPACE JUMPERS
15
256 X 4
PROM/ROM
CHI PS
'----.l...--"-----'-""T""".l---'---.l---'---"'----'-__-'----'-__-'----'-__-'-----'-~

W16
~

4K ADDRESS
SPACE JUMPERS

HIGH/LOW 2K SELECT
W13 INSTALLED:
LOW 2K (0-7777)
W14 INSTALLED:
HIGH 2K (1000-17777)

MRV 11-A Address Word Format

287

M7942

12-15

8-11

4-7

3-0

c=J c=J F
I CE7
c=J ~ §
I CE6
c=J c=J F
I CE5
c=J c=J P
I CE4
c=J c=J E
I CE3
c=J c=J L=:==J CE2
c=J c=J p i C E 1
c=J c=J F
I CEO

L--------l

L-------.-I

L-------l

L-P
L-P

_-----1

L--------l

L--.-----l

M7942 ETCH REV. 0

M7942 Etch Rev D

288

M7942
512 by 4-Bit PROM Addresses
Bank Address
Jumpers
W15

W16

W17

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

R
R
R
R

Word/Byte
Address

Physical
Row

BRPLY L
Jumper

0-1777
2000-3777
4000-5777
6000-7777
10000-11777
12000-13777
14000-15777
16000-17777

CEO
CE1
CE2
CE3
CE4
CE5
CE6
CE7

WO
W1
W2
W3
W4
W5
W6
W7

256 by 4-Bit ROM Addresses
Bank Address
Jumpers

Word/Byte Address

W15

W16

W131nstalled
W17 W14 Removed

W13 Removed
W14 Installed

Physical BRPLY L
Row
Jumper

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

0-7776
10000-17776
20000-27776
30000-37776
40000-47776
50000-57776
60000-67776
70000-77776

100000-107776
110000-117776
120000-127776
130000-137776
140000-147776
150000-157776
160000-167776
170000-177776

CEO
CE2
CE4
CE6
CE1
CE3
CE5
CE7

I
I

R
R

BRPL YL Select
Empty Row Remove Jumper

CEO
CE1
CE2
CE3
CE4
CE5
CE6
CE7

WO
W1
W2
W3
W4
W5
W6
W7

289

WO
W2
W4
W6
W1
W3
25
W7

M7944

M7944
MSV11-B READ/WRITE MEMORY

Amps

+ 12

0.6
(1.12 max.)

0.3
(0.7 max.)

Bus Loads

Cables

AC
DC
1.89 1.0

none

Standard Addresses
Module is shipped with all jumpers installed, selecting bank 0 (0-17776).

Vectors, DEC/X 11 Exerciser Program
None

Diagnostic Programs
Refer to Appendix A.

Related Documentation
Field Maintenance Print Set (MP00067)
Microcomputer Processor Handbook (EB-18451-20)

NOTES
1.

Only one dynamic memory module in a system is needed
to reply to the refresh bus functions initiated by the processor. The module selected should be the one with the
longest access time (usually the module electrically farthest from the refreshing device).

290

M7944
NOTES (Cont)
2.

If a REV11 (M9400YA or YC) provides refresh, only the processor-resident memory (if present) should reply to refresh. If the processor board has no resident memory, the
memory module electrically farthest from the REV11
should reply.

Refer to the Refresh Configuration Procedures in the 1/ Systems Configurations" section.

'<t~

s:s:

1111

M7944 ETCH REV B

M7944 Etch Rev B

291

M7944
BDAL BITS

4096 LOCATION ADDRESS

BYTE
POINTER

4K ADDRESS
SPACE JUMPERS
/
Bank

NOTE:

No.

I:: Installed,

Address
Range

Octal Address
RAnge

OAK
48K
a·12K
12·16K
16·20K
2O·24K
2428K
28·32K

000000·017776
020000·037776
040000·057776
060000·077776
100000·117776
120000·137776
140000·157776
160000·177 776

A = Removed
MR·5429

MSV 11-8 Address Format! Jumpers

NOTE
Because of addressing limitations, this module is not compatible with PDP-11 /23 systems with more than 64K bytes of
memory_

MSV11-B Address Format/Jumpers
Reply to Refresh
Function

Reply
Don't reply

R
I

292

M7946

M7946
RXV11 FLOPPY DISK INTERFACE

Amps
+5
1.5 max.

+ 12
0

Bus Loads

Cables

AC
1.74

BC05L

Standard Addresses

RXCS
RXDB
Vector

First Device

Second Device

177170
177172
264

177150
177152
270

Diagnostic Programs
Refer to Appendix A.

NOTE
Run DZRXB before DZRXA.

Related Documentation
RXV11 User's Manual (EK-RXV11-0P-001)
Field Maintenance Print Set (MP00024)
Microcomputer Interfaces Handbook (EB-20 175-20)

293

3:
......

co
~

_WI

_w>
Wl _ _ _ _ _ _ W3

W2 ........... _____ ws

w.e...-..... ....-....W6
_ _ _ W13
WB.....-4 _____ W14
W16 .......... _ _ _ wg

_W4

_ws
_ _ W1

W1~

_we

W10 _ _ _ _ _ _ W17
W l 1 - - " _ _ _ W15

......--.Wl1

____ W12

ETCH REV B . MACHINE INSERTED JUMPERS

W13 ..........

....._W16

W1 ...........

....._W17

ETCH REV C· WIRE·WRAP JUMPERS

-8-.

DEVICE
ADDRESS

FACTORYCONFIGURED _ _ R
ADDRESS
RXCS' 177170
RXDB'I77172

Device Address

I\)

DAL BITS_15
VECTOR
ADDRESS

I I
:
0

.JUMPER ON _
M7946 MODULE

I I I I I I
I I I I I I

FACTORY-CONFIGURED - R
VECTOR ADDRESS=264

NOTE:
1= Jumper inslalled' Logical"
R' Jumper removed = Logica I 1
X' Don'l care
MR-OBI4

Vector Address

Unit

Address Address Jumpers
W17 W16 W15 W14 W13 W12 W11 W10 W9

First
177170
(Drives 0, 1)

Second
177150
(Drives 2, 3)

Unit

Vector

Vector Jumpers
W6

First
264
(Drives 0, 1)

Second
270
(Drives 2, 3)

M7946
NOTES
1.

When inserting the cable in the RXV11 interface module,
the red edge of the cable should be at the center of the
module (near the pin A end of J 1).

BUS INIT - Install W18 to pass bus INIT to the RX01 as initialize.

I
ERROR

NOT USED

RX
INIT

DONE

lNT
ENB

I I

UN1T
SEL

FUNCTION

000
001
010
011
100
101
110
11,

FILL SUFFER
EMPTY BUFFER
WRITE SECTOR
READ SECTOR
NOT USED
READ STATUS
WRITE DELETED
DATA SECTOR
READ ERROR
REGISTER

Receiver Control/Status Register (RCSR)

Bit Definitions
Bit

Function

Go - Initiates a command to RXO 1. Write only.

1-3

Function Select - These bits code one of the eight possible
functions. Write only.

Unit Select - This bit selects one of the two possible disks for
execution of the desired function. Write only.

Done - This bit indicates the completion of a function. Done will
generate an interrupt when asserted if interrupt enable (RXCS
bit 6) is set. Read only.

Interrupt Enable - This bit is set by the program to enable an
interrupt when the RXO 1 has completed an operation (done).
The condition of this bit is normally determined at the time a
function is initiated. This bit is cleared by the LSI-11 bus initialize (BINIT L) signal, but it is not cleared by the RXV 11 initialize bit (RXCS bit 14). Read/write.
297

M7946
Bit Definitions (Cont)
Bit

Function

Transfer Request - This bit signifies that the RXV 11 needs data
or has data available. Read only.

8-13

Unused.

RXV 11 Initialize - This bit is set by the program to initialize the
RXV 11 without initializing all of the devices on the LSI-11 bus.
Write only.

CAUTION
1.

Loading the lower byte of the RXCS will also load the upper byte of the RXCS.

Setting this bit (BIS instruction) will not clear the interrupt enable bit (RXCS bit 06).

Upon setting this bit in the RXeS, the RXV 11 will negate done
and move the head position mechanism of drive 1 (if two are
available) to track O. Upon completion of a successful initialize,
the RXO 1 will zero the error and status register, set initialize
done, and set RXES bit 7 (DRV RDY) if unit 0 is ready. It will also
read sector 1 of track 1 and drive o.
15

Error - This bit is set by the RXO 1 to indicate that an error has
occurred during an attempt to execute a command. This readonly bit is cleared by the initiation of a new command or by setting the initialize bit. When an error is detected, the RXES is
automatically read into the RXDB.

The RXDB register serves as a general purpose data path between the
RXO 1 and the RXV 11 interface. It may represent one of five RXO 1 registers
according to the protocol of the command function in progress. The RXO 1
registers include RXDB, RXTA, RXSA, RXES, and RXER.

CAUTION
Violation of protocol in manipulation of this register may cause
permanent data loss. Refer to RXV11 User's Manual.

298

M7946
RXDB-RX Data Buffer - All information transferred to and from the floppy
media passes through this register and is addressable only under the protocol of the function in progress.
15

----v
NOT USED

READ/WRITE DATA

RXDB Format
RXTA-RX Track Address - This register is loaded to indicate on which of
the 114 tracks a given function is to operate. It can be addressed only under the protocol of the function in progress. Bits 8 through 15 are unused
and are ignored by the control.
15

I I

~--------~i--------~
NOT USED

0-114.

RXTA Format
RXSA-RX Sector Address - This register is loaded to indicate on which of
the 32 sectors a given function is to operate. It can be addressed only under the protocol of the function in progress. Bits 8 through 15 are unused
and are ignored by the control.
15

0:.1

I I I I
0

L - -_ _ _ _ _ _~--------~

NOT USED

RXSA Format
RXES-RX Error and Status - This register contains the current error and
status conditions of the drive selected by bit 4 (unit select) of the RXCS.
This read-only register can be addressed only under the protocol of the
function in progress. The RXES is located in the RXDB upon completion of
a function.
15

I~~~ I

06
DD

NOT USED

RXES Format

299

M7946
RXDB Bit Definitions
Bit

Function

CRC Error - A cyclic redundancy check error was detected as
information was received from a data field of the diskette. The
RXES is moved to the RXDB, and error and done are asserted.
Parity Error - A parity error was detected on command or on address information being transferred to the RXO 1 from the LSI-11
bus interface. A parity error indication means that there is a
problem in the interface cable between the RXO 1 and the interface. Upon detection of a parity error, the current function is terminated; the RXES is moved to the RXDB, and the error and
done are asserted.

Initialize Done - This bit is asserted in the RXES to indicate
completion of the initialize routine, which can be caused by
RXO 1 power failure, system power failure, or programmable or
LSI-11 bus initialize.

3-5

Unused.

Deleted Data Detected - During data recovery, the identification mark preceding the data field was decoded as a deleted data mark.

Drive Ready - This bit is asserted if the unit currently selected
exists, is properly supplied with power, has a diskette installed
correctly, has its door closed, and has a diskette up to speed.
NOTES
1. The drive ready bit is valid only when retrieved via a read
status function or at completion of initialize when it indicates status of drive O.
2. If the error bit was set in the RXCS but error bits are not set
in the RXES, then specific error conditions contained in the
RXER can be accessed from the RXDB via a read error register function.

RXER-RX Error - This register is located in the RXO 1 and contains specific
RXO 1 error information. This information is normally accessed when the
RXCS error bit 15 is set but RXES error bits 0 and 1 are not set. This is e
read-only register.
300

M7946
15

~------~~----------~

NOT USED

RXER Format

Octal Code

Error Code Meaning

0010
0020
0030
0040
0050
0060
0070

Drive 0 failed to see home on initialize.
Drive 1 failed to see home on initialize.
Found home when stepping out 10 tracks for INIT.
Tried to access a track greater than 77.
Home was found before desired track was reached.
Self-diagnostic error.
Desired sector could not be found after looking at 52 headers (two revolutions).
More than 40 microseconds and no SEP clock seen.
A preamble could not be found.
Preamble found but no I/O mark found within allowable time
span.
eRe error on a header; no flag.
The header track address of a good header does not compare with the desired track.
Too many tries for an 10 address mark.
Data mark not found in allotted time.
eRe error on reading the sector from the disk. No code appears in the ERREG.
Parity error on some word from interface.

0110
0120
0130
0140
0150
0160
0170
0200
0210

301

M7948

M7948
DRV11-P FOUNDATION MODULE

Amps

Bus Loads

DC
+5
+12 AC
1.0
2.08 1.0
Plus user's logic

Cables

BC07A
BC07D
BC08R
BC04Z

Standard Addresses
No standard designated. Configurable within the range of 760000- 777776.
May conflict with DEC standard device addresses.

Vectors
None assigned. Configurable within the range of 0-374. May conflict with
DEC standard device vectors.

Diagnostic Program
None

Related Documentation
DRVll-P Foundation Module User's Manual
(EK-DR 11-0P)
Field Maintenance Print Set (MPOO 119)
Microcomputer Interfaces Handbook (EB-20 175-20)

302

+5V WIRE-WRAP PIN
UPPER RIGHT
PIN OF FIRST
FIVE MOUNTING
AREAS

GROUND WIRE-WRAP PIN
UPPER LEFT
PIN OF FIRST
FIVE MOUNTING
AREAS

••

•

:::
WIRE-WRAP PINS
FOR INTERCONNECTING
USERIC'S

'"o
~

N
<0

...

. ",

':11:
rt)lLJ

••

•

ii ii 1 -i~-- h-l
4

+5V WIRE-WRAP PIN
LOWER RIGHT
PIN OF All
MOUNTING
AREAS.
DESIGNATED
BY PLUS (+)
SIGN.
GROUND WIRE-WRAP PIN
LOWER lEFT
PIN OF All
MOU"ITiNG
AREAS.
DESIGNATED
BY MINUS (-)
SIGN.

REMOVE TO DISABLE
VECTOR ADDRESSING
(SEE TEXT)

USER WIRE-WRAP

60~ 3~
[ill]

USER WIRE-WRAP
PINS FOR CONNECTING
USER lOGIC TO "C"
AND "0" DRVll-P
MODULE FINGERS

+3V WIRE-wRAP PIN
FOR PULLING-UP
UNUSED GATE
INPUTS, ETC.

_----1- ~~~~:iD FROM

n~-~i--it--t-~ ~f~
\:.@D ..

1 TH ROUGH 120

illIJ •• [lli] •• [ill]

-~:~.::. :;~~~:::~~
~~::.:~.~~~~~~~~:
i:i:woo
;;;:;:;;~~~.;

BIAKI l - BIAKO l
CONTINUITY JUMPER.
REMOVE ONLY WH EN
USING THE CN2 AND
CM2 MODULE FINGERS.

iii:=i

;;j:u;~iL:ZiJr; i~wou iii:i

BDMGI l - BDMGO l
CONTINUITY JUMPER.
REMOVE ONt Y WHEN
USING THE CR2 AND
CS2 MODULE FINGERS.

+3V WIRE-WRAP PIN
FOR PULLING-UP
UNUSED GATE
INPUTS, ETC.

BDMGI l - BDMGO l
CONTINUITY JUMPER.
REMOVE ONLY WHEN
DMA GRANT ARBITRATION
lOGIC IS CONSTRUCTED
ON DRVII-P MODULE.

SPLIT LUGS TO ACCOMMODATE
EXTERNAL CAPACITOR (C3.) WHEN
ADJUSTING DELAY BETWEEN
BDIN l, BDOUT l, AND
BETWEEN VECTOR H INPUTS
AND BRPlY l.

M7948
Device Address Selection
The DRV 11-P will respond to up to four consecutive addresses in the bank
7 area (addresses between 160000 and 177776). The register addresses
are sequential by even numbers and are as follows.
Register
1

Octal Address

BBS7

1xxxxO
1xxxx2
1xxxx4
1xxxx6

2
3
4
DECODED
BY BBS7

DECODED FOR
I OF 4
REGI STERS

SELECTED BY WIRE - WRAP PINS

r-------~~-------,,~----------------~----------------__,,~

WIRE- WRAP
TO A GROUND
WP FOR "ZERO"
BITS IN THE
ADDRESS

DRV 11-P Device Address Select Format

Vector Address Selection
To cause separate vectors for an interrupt A and an interrupt B, wirewrap
WP5 to WP21.
1 ST
OCTAL
DIGIT

LEAST
SIGNIFICANT
OCTAL PREASSIGNED
DIGIT
AS
(0 OR 4)
ZEROS

2 ND
OCTAL
DIGIT

,.-----A------. ~
oa
alT oa AVAILABLE

0!5

•

r---

FORA;~Jis~~g - - -...:
SEE TEXT.

L ___ ~r-~'-~-r~~~-..-~.-~--~--~

WIRE-WRAP
TO A GROUND
WP FOR "ZERO" -----<.
BITS IN THE
ADDRESS

(SEE TEXT)

WP
74

~fL

WP
76

DRV11-P Vector Address Select Format
304

FROM INTERRUPT LOGIC

M7948
Bus Reply
The BRPl Y l signal is normally issued within 85 ns (max.) of receiving either BOIN l or BOOUT l, depending on the bus cycle. If the user's interface
requires more time before ending the bus cycle, the BRPl Y l signal can be
delayed up to a maximum of 10 by adding capacitor C39 across the split
lugs in the BRPl Y delay circuit. The amount of capacitance required for
various delays is given in the following table.
C39 R-C Delays for BRPL Y
Resistor
Capacitance
(Constant) (C39 Option)
680Q
680Q
680Q
680Q
680Q
680Q
680 Q

o pF
100 pF
120 pF
470 pF
560 pF
680 pF
1200 pF

Delay
(Typical)"
50 ns
75 ns
80 ns
165 ns
185 ns
210 ns
340 ns

*Typical BRPl Y delay with respect to OBOUT
and BOIN.

Maximum DRV11-P IC Density
(All Areas)
IC Type

Max ICs

6 pin
8 pin
14 pin
16 pin
18 pin
20 pin
22 pin
24 pin
40 pin

122
97
61
52
44
43
6
5
3

305

M7948
User Wirewrap Pins
Wirewrap
Pin

Function

WP 1

SPARE 0 - Spare input to the vector address multiplexer.
This input can be used to read part of a control/status register.

WP2

SPARE 3 - See WP1.

WP3

Ground for vector address bit V3. See WP23.

WP4

SPARE 1 - See WP1.

WP5

V2 - Vector address bit 02.

WP6

ENB CLK A H - ENB CLK A H is the clock input to the enable A
flip-flop of the A interrupt logic. When ENB CLK A H goes high,
ENB DATA A is clocked into the enable A flip-flop.

WP7

SPARE 2 - See WP1.

WP8

ENB B ST H - ENB B ST H is the status output from the enable
B flip-flop of the B interrupt logic. When ENB B ST H is high,
the enable B flip-flop is set.

WP9

IAKI L - Test point for the BIAK I bus signal. BIAKI L is the processor's response to BIRQ L and is daisy-chained such that
the first requesting device blocks the signal propagation.
Nonrequesting devices pass the signal on as BIAKO l. The
leading edge of BIAKI L causes BIRQ L to be unasserted by
the requesting device.

WP10

001 L - Test point for data/address bit one. Useful when testing the protocol logic. DO 1 is latched in the protocol logic at
the asserted edge of BSYNC l. DO 1 and 002 are decoded to
produce the SEL OEV outputs.

WP 11

BWTBT L - Test point for the BWTBT bus signal, while BOOUT
L is asserted, BWTBT L indicates a byte or word operation:
BWTBT L asserted indicates byte operation; BWTBT L unasserted indicates word operation. BWTBT L decoded with
BOOUT Land BOAL 0 L forms OUT LB L or OUT HB l.

WP 12

R C X X - Test point for monitoring the delay of BRPL Y.

306

M7948
User Wirewrap Pins (Cont)
Wirewrap
Pin

Function

WP13

BSYNC H - Test point for the BSYNC l bus signal. BSYNC l
indicates that the address is valid. At the assertion of BSYNC
l, address information is trapped in four latches. While unasserted, disables all outputs except the vector term of BRPl Y
L. BSYNC l is held throughout the entire bus cycle.

WP14

000 H - One of 16 data or address lines from the transceivers
for user applications. Address bit 00 is used for byte selection: 0 = low byte; 1 = high byte.

WP15

BOOUT l - Test point for the BOOUT l bus signal. BOOUT is a
strobe signal to effect a data output transaction. BOOUT l is
decoded with BWTBT land BOAlO to form OUT lB l and OUT
HB L. BOOUT l also causes BRPl Y l to be issued through the
delay circuit.

WP16

IN WO l - In Word (IN WO) is used to gate input data from a
selected register onto the lSI-11 bus. Enabled by BSYNC l
and strobed by BOIN L.

WP17

DO 1 H - One of 16 data or address lines from the transceivers
for user applications.

WP18

INIT 0 l - An initialize signal (asserted low) for user applications.

WP19

INIT 0 H - An initialize signal (asserted high) for user applications.

WP20

BRPl Y l - Test point for the BRPl Y l bus signal. BRPl Y l is
generated by VECTOR H (vector term), or by BSYNC and ENB
in combination with either BOIN l, or BOOUT L. Capacitor C37
can be added by the user to extend the delay.

WP21

VEC RQST B H - Used to distinguish whether device A or device B is making a request. VECT RQST B H is asserted for
device B requests and unasserted for device A requests.

WP22

V3 - Vector address bit 03. WP23 is used to select the state
of vector address bit 03. When not wrapped to a ground pin,
vector address bit 03 is a 1. When wrapped to WP3, vector
address bit 03 is a O.

307

M7948
User Wirewrap Pins (Cont)
Wirewrap
Pin

Function

WP24

ENB DATA A H - Interrupt enable A data line. The level on this
line, in conjunction with the ENB ClK A H (see WP6) line, determines the state of the A interrupt enable flip-flop within the
interrupt logic.

WP25

BIAKO l - Test point for the BIAKO l bus signal. BIAKO l is
the daisy-chained signal that is passed by all devices not requesting interrupt service (see WP9).

WP26

ENB ClK B H - ENB ClK B H is the clock input to the enable B
flip-flop of the B interrupt logic. When ENB ClK B H goes high.
ENB DATA B is clocked into the enable B flip-flop.

WP27

ENB DATA B H - Interrupt enable B data line. The level on this
line, in conjunction with the ENB ClK B H (see WP 26) lines,
determines the state of the B interrupt enable flip-flop within
the interrupt logic.

WP28

ROST B H - When RQST B H is asserted, the bus request flipflop for device B in the interrupt logic is enabled, and BIRO l
becomes asserted if the interrupt enable flip-flop is set.

WP29

VECTOR H - Test point for VECTOR H. This signal causes
BRPl Y l (vector term) to be generated through a delay independently of BSYNC land ENB H. VECTOR H also gates the
vector address onto the lSI-11 bus via the vector address
generator.

WP30

002 l - Test point for data/address bit 2. Useful when testing
the protocol logic. 002 is latched at the asserted edge of
BSYNC L. 002 and DO 1 are decoded to produce the SEl DEV
outputs.

WP31

ENB H - Test point for ENB H. This signal is the result of a
comparison between the device address on the lSI-11 bus
and the device address established by the user. When the addresses compare, ENB H is asserted and sent to the protocol
logic.

308

M7948
User Wirewrap Pins (Cont)
Wirewrap
Pin

Function

WP32

SEL DEV 6 L - One of four select signals that is true as a
function of BDAL 1 Land BDAL2 L if ENB H (see WP31) is asserted at the asserted edge of the BSYNC L. The four select
signals indicate that a user's register has been selected for a
data transaction. The select signals remain asserted until
BSYNC L becomes unasserted.

WP33

SEL DEV 4L - See WP32.

WP34

SEL DEV 2L - See WP32.

WP35

SEL DEV OL - See WP32.

WP36

OUT LB L - Out Low Byte is used to load (write) data into the
low byte of a selected user register. See WP37.

WP37

OUT HB L - Out High Byte is used to load (write) data into the
high byte of a selected user register. If used with OUT LB L,
the higher, lower, or both bytes can be written. OUT HB L is
enabled by BSYNC L and the decode of BWTBT Land BDALO
L, and strobed by BDOUT L.

WP38

BIRO L - Test point for the BIRO L bus signal. This signal is
asserted by a device needing interrupt service.

WP39

BDMGO L - This signal is generated by DMA devices as a result of arbitrating the BDMGI L line. Jumper W2 must be removed if the DRV 11-P is to be used for DMA service.

WP40

BDMGI H - Used as a source for the BDMGI signal to drive the
user's DMA request arbitration logic. See WP39.

WP41

ENB A ST H - ENB A ST H is the status output from the enable
A flip-flop of the A interrupt logic. When ENB A ST HA is high,
the enable A flip-flop is set.

WP42

A 12 - Used to select the user's device address along with
WP45, 44, 43, 47, 48, 46, 51, 49, 50. When not wrapped to a
ground pin, the particular device address bit will be a 1. When
wrapped to a ground pin (WP62 for bit A 12), the particular bit
will be a O.

309

M7948
User Wirewrap Pins (Cont)
Wirewrap
Pin

Function

WP43

A09 - User's device address bit 09. The associated ground
pin is WP63. See WP42.

WP44

A 10 - User's device address bit 06. The associated ground
pin is WP64. See WP42.

WP4S

A 11 - User's device address bit 06. The associated ground
pin is WP6S. See WP42.

WP46

A06 - User's device address bit 06. The associated ground
pin is WP66. See WP42.

WP47

A08 - User's device address bit 06. The associated ground
pin is WP67. See WP42.

WP48

A07 - User's device address bit 06. The associated ground
pin is WP68. See WP42.

WP49

A04 - User's device address bit 04. The associated ground
pin is WP69. See WP42.

WPSO

A03 - User's device address bit 06. The associated ground
pin is WP70S. See WP42.

WPS1

AOS - User's device address bit OS. The associated ground
pin is WP 17. See WP42.

WPS2

SPARE 4 - See WP 1.

WPS3

V4 - Vector address bit 03. The associated ground pin is
WP73. See WP 23.

WPSS

VS - Vector address bit OS. The associated ground pin is
WP7S. See WP23.

WPS6

V6 - Vector address bit 06. The associated ground pin is
WP76. See WP23.

WPS7

IN03 H - One of 16 data or address lines to the transceivers
for user applications.

310

M7948
User Wirewrap Pins (Cont)
Wirewrap
Pin

Function

WP58

SPARE ENB 0 - SPARE ENB 0 and SPARE ENB 1 (WP59) both
must be driven low to write data from SPARE inputs 0 through
7 to the LSI-11 bus via the transceiver. For 8-bit input applications, SPARE ENB 0 could be driven by one of the SEL OEV
lines, while SPARE ENB 1 could be driven by IN WO L.

WP59

SPARE ENB 1 - See WP58.

WP60

INOO H - See WP57.

WP61

009 H - See WP17.

WP62

Ground for user's device address bit A 12. See WP42.

WP63

Ground for user's device address bit A09. See WP42.

WP64

Ground for user's device address bit A 10. See WP42.

WP65

Ground for user's device address bit A 11. See WP42.

WP66

Ground for user's device address bit A06. See WP42.

WP67

Ground for user's device address bit A08. See WP42.

WP68

Ground for user's device address bit A07. See WP42.

WP69

Ground for user's device address bit A04. See WP42.

WP70

Ground for user's device address bit A03. See WP42.

WP71

Ground for user's device address bit A05. See WP42.

WP72

004 H - See WP17.

WP73

Ground for vector address bit V4. See WP23.

WP74

Ground for vector address bit V5. See WP23.

WP75

Ground for vector address bit V6. See WP23.

WP76

Ground for vector address bit V7. See WP23.

311

M7948
User Wirewrap Pins (Cont)
Wirewrap
Pin

Function

WP77

BBS7 H - Test pOint for the bank 7 select (BBS?) bus signal.
This line is asserted by the bus master when an address in
the upper 4K bank (28K-32K range) is placed on the LSI-11
bus.

WP78

SPARE 6 - See WP1.

WP79

002 H - See WP17.

WP80

IN 02 H - See WP57.

WP81

015 H - See WP17.

WP82

IN 13 H - See WP57.

WP83

014 H - See WP17.

WP84

013 H - See WP17.

WP85

012 H - See WP17.

WP86

IN 12 H - See WP57.

WP87

003 H - See WP17.

WP90

SPARE 7 - See WP1.

WP91

010 H - See WP17.

WP92

IN 09 H - See WP57.

WP93

Not used.

WP94

TRANS ENB C L - Enables user's data to be placed onto the
LSI-11 bus. Both TRANS ENB C and A (WP94 and WP 120) and
TRANS ENB 0 and B (WP95 and WP 100) must be driven low
prior to the processor's read data time.

WP95

TRANS ENB 0 L - See WP94.

WP96

IN 01 H - See WP57.

312

M7948
User Wirewrap Pins (Cont)
Wirewrap
Pin

Function

WP97

VEe ENS H - Test point for VEe ENS H. This signal gates the
vector address to the LSI-11 bus, provided that jumper W4
has not been removed. WP97 can be used as the source for
VEe ENS H when adding an additional gate to the DRV 11-P
for vector address expansion up to 774.

WP98

IN 06 H - See WP57.

WP99

IN 04 H - See WP57.

WP 100

TRANS ENS S L - See WP94.

WP101

IN 15 H - See WP57.

WP102

IN 14 H - See WP57.

WP103

Used to pull up the VEe ENS H line when jumper W4 is removed.

WP 104

Not used.

WP105

Not used.

WP106

008 H - See WP17.

WP107

006 H - See WP17.

WP108

IN 11 H - See WP17.

WP109

011 H - See WP57.

WP 110

Not used.

WP 111

Not used.

WP112

SPARE 5 - See WP1.

WP113

IN 08 H - See WP57.

WP 114

Not used.

313

M7948
User Wirewrap Pins (Cont)
Wirewrap
Pin

Function

WP115

BSYNC H - Test point for BSYNC H. At the asserted edge of
this signal, address information is trapped in four latches.
BSYNC H is the inversion of BSYNC l. See WP 13.

WP 116

Not used.

WP117

D05 H - See WP17.

WP118

IN 07 H - See WP57.

WP119

IN 05 H - See WP57.

WP 120

TRANS ENB A L - See WP94.

+3 V

There are two + 3 V source wirewrap pins on the DRV 11-P.
Each + 3 V source can drive up to 13 TTL unit loads. These
sources can be used for pulling up unused TTL inputs.

314

M7949

M7949
LAV11 PRINTER INTERFACE

Amps
+5
0.5

Bus Loads
+ 12
0

AC
1.8

DC
1.0

Cables

BC11S (for LA 180)
7009087 (for Centronics line printer™ models
101, 101A, 1010, 102A, and 303)

Standard Addresses
LACS
LADB

177514
177516

Vectors
200

Diagnostic Program
Refer to Appendix A.

Related Documentation
LAV11 User's Manual (EK-LAV11-0P-001)
Field Maintenance Print Set (MP00306)
LA 180 DECprinter I Maintenance Manual (EK-LA 180-MM)
Microcomputer Interfaces Handbook (EB-20 175-20)

315

M7949
CAUTIONS
1.

Switching - Switching the LA 180 off-line while the operating system is running a program may result in the computer hanging and
crashing the program. If this occurs, type P to continue. This problem does not occur if the LPV 11 is used in place of the LA V 11.

LA 180 to LAV 11 Cable - The only acceptable cable for use between the LA 180 and the LA V 11 is the BC 11 S. The end labeled P2
must attach to the LA 180. The end labeled P 1 must be attached to
the LAV11.

LA180 Modifications - On the LA180 logic board (54-11023), jumper W6 must be inserted. This ensures + 5 Vdc sense will read the
LAV11. Failure to do so will result in a continued error condition in
the LAV11 LACS buffer. W6 is located between J2 and J3 on the
54-11023 module.

Miscellaneous Jumpers - For an LA 180, the following jumper configuration must be maintained.
Jumper Condition

Function if Inserted

Transmit parity on line
+5 Vdc sense from LA 180
+5 Vdc sense from LAV11
DEMAND is asserted low
DEMAND is asserted high
P STROBE is asserted low
P STROBE is asserted high

W3
W4
W5
W6
W7

I
I
R
R
I
R
I

The field replacement for the LAV11 (M7949) is the LPV11 (M8027).

316

M7949

ST ANDARD CONFIGURATION

ADDRESS

SW3

SW2

j:3

WI'

1
2
3
4

4
5
VECTOR
SWI

4
6
7
8

OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
ON
ON
ON
ON
ON
OFF
ON
N.A.

STANDARD ADDRESS = 17751 X
VECTOR = 200

JUMPER

LA180

CENTRONICS

WI
W2
W3
W4
W5
W6
W7

I
I
R
R
I
R

R
I
R
I

KEY:

I = INSERT
R. REMOVE
11- 4146

317

M7949

All
153-41
A12
(53-51

A9
(S3-21
Al0
(S3-31

A7
IS2-51
AS
(53-11

A5
152-31

A3
IS2-11

A6
(52-41

A4
(52-21

V6
(Sl-51

V4
151-31

V7
ISl-61

V5
151-41

V2
(Sl-ll
V3
ISl-21

VECTOR SWITCHES
LOGIC 0 = SWITCH ON
LOGIC 1 - SWITCH OFF
MR 0815

LAV 11 Control/Status Register (LACS)

LACS Bit Definitions
Bit

Function

Error - The error bit is asserted (1) when an error condition (i.e.,
torn or no paper) exists in the line printer. This is a read-only bit,
which is reset only by manual correction of the error condition.

14-08

Unused.

Done - The done bit is asserted (1) when the printer is ready to
accept another character. This is a read-only bit set by INIT. The
done bit is cleared by loading the LADB register. An interrupt sequence is started if IE (interrupt enable, bit 06) is also set.

318

M7949
LACS Bit Definitions (Cont)
Bit

Function

IE - The interrupt enable bit is set or cleared (read or write bit)
under program control. It is cleared by the INIT (initialize) signal
on the LSI-11 bus.
(lNIT is caused by programmed RESET instruction, console start
function, or a power-up or power-down condition.) When IE is
set, an interrupt sequence is started if either error or done is
also set.

05-02

Unused.

On Line - The on line bit is asserted (1) when the LA 180 printer
(only) is on-line. Read only.

Busy - The busy bit is asserted (1) when the LA 180 printer
(only) is performing a print or paper advance operation.

PRINTER DATA

NOT USED

DATA BITS

06-00

LA V 11 Data Buffer Register (LADB)

LADB Bit Definitions
Bit

Function

15-08

Unused.

Parity - The parity bit is loaded with the data word if the parity
jumper is installed. Write only.

06-00

Data - The data comprises seven bits, with bit 06 being the
most significant. This buffered 7-bit character will be transferred
to the printer. These are all write-only bits.

319

M7950

M7950
DRV11-B GENERAL PURPOSE DMA INTERFACE

Bus Loads

Amps

+5
1.9

+ 12
o

AC
3.3

DC
1.0

Cables
Two BC04Z
Two BC08R

Standard Addresses
MINC/
DECLAB
Word Count Register (WCR)
Bus Address Register (BAR)
CSR
DBR

772410
772412
772414
772416

171770
171772
171774
171776

Vector
124 370

Diagnostic Programs
Refer to Appendix A.

Related Documentation
DRV11-8 General Purpose DMA Interface User's Manual
(EK -DRV 1B-OP-OO 1)
Field Maintenance Print Set (MPOO 160)
Microcomputer Interfaces Handbook (EB-20 175-20)

320

M7950
J1

DEVICE ADDRESS
SELECTION SWITCHES

VECTOR ADDRESS
SELECTION SWITCHES

-0

11 - 41~6

DECODED BY BBS?

DECODED FOR
1 OF 4
REGISTERS

SELECTED BY SWITCHES

r---------A---------,~------------------~------------------~,~

OFF' "ZERO"
ON- "ONE"

DRV 11-8 Device Address Select Format

4 TH
OCTAL DIGIT
10 OR 4)

1 ST
OCTAL
DIGIT

2 NO
OCTAL
DIGIT

3 RD
OCTAL
DIGIT

I ,------A---.,~

PREASSIGNED
AS ZEROS

,---A--.,
00

VECTOR
ADDRESS
SELECTION
SWITCHES

OFF' "ZERO"
ON' "ONE"

DRV 11-8 Interrupt Vector Address Select Format
321

M7950

NEX

MAl NT

STAT B

CYCLE

XAD 16

FNCT 2

LEGEND

R = Read only
R/W = Read / Wrlle
R/WO· Read / Write '0 0
W = Write only Always reads as a 0

CSR Format (11-4186)

CSR Bit Functions
Bit

Function

Go - Write only. Always reads as o.

01,02,03

Causes ready to be sent to the user's device, indicating that a command has been issued.

Allows DMA operation.

FNCT 1, 2, 3 - Read/write.
1.
2.

Three output.
Cleared by INIT.

04, 05

XAD 16,17 - Read/Write. Two bits used for extended addressing. Bits 04 and 05 increment with the address count
with the BAR wraps around to O.

IE - Read/write.
1.
2.

Enables interrupts to occur when ready set.
Cleared by INIT.

Ready - Read only. Indicates that the DRV 11-B is able to
accept a new command. Set by INIT. WCOFLO, ERROR;
cleared by go (bit 00).

Cycle - Read/write. Cycle eis used to prime a DMA bus
cycle; set by CYCLE REQUEST, cleared during DMA
cycle, INIT.

09, 10, 11

STAT A, B, C - Read only. Three device status input bits
that indicate the state of the DSTAT A, B, and C user signals.
322

M7950
CSR Bit Functions (Cont)
Bit

Function

MAl NT - Read/write. Maintenance bit for use with the
MAINDEC diagnostic.

ATTN - Read only. Indicates the state of the ATTN user
user signal; sets ready, error.

NEX - Read/write to 0 bit.

Nonexistent memory; indicates that as bus master,
the DRV 11-B did not receive BRPL Y or that a DA TID
cycle was not completed.

Set error.

Cleared by INIT or by writing it to a O.

Error - Read only.
1.

Indicates one of the following special conditions.
•
•

NEX (bit 14)
ATTN (bit 130)

Sets ready (bit 7) and causes an interrupt if IE (bit 6)
is set.

Cleared by removing the special condition as follows.
a.
b.

NEX is cleared by writing bit 14 to a O.
ATTN is cleared by the user device.

323

M7951

M7951
DUV11-DA SYNCHRONOUS SERIAL LINE INTERFACE

Amps

+5
0.86

Bus Loads

+ 12
0.32

AC
1.0

Cables

DC
1.0

BC05C

Standard Addresses
Floating - Configurable in the range of 760000-777776. Refer to Appendix
B.

Vector
Floating - Configurable in the range of 300-770. Refer to Appendix B.

Diagnostic Programs
Refer to Appendix A.

Related Documentation
DUV 11 Line Interface Technical Manual (EK-DUV 11-TM-OO 1)
Field Maintenance Print Set (MP00297)
Microcomputer Interfaces Handbook (EB-20 175-20)

324

M7951

TRANSMITTER
CHIP

RECEIVER
CHIP

ADDRESS/VECTOR
ROCKER SWITCHES

325

M7951
Switch Assignment for Option Switch Pack E55
Switch Number Function
SW1

Optional clear - Switch ON enables CLR OPT, which is
used to clear RXCSR bits 03, 02, and 01.

SW2

Secondary transmit - Switch ON enables secondary data
channel between the modem and DUV 11.

SW3

Secondary receive - Switch ON enables secondary data
channel between the modem and DUV 11.

SW4

Sync characters - Switch ON enables the receiver to synchronize internally upon receiving one sync character.
The normal condition of receiving two sync characters exists when SW4 is off.

SW5

Special feature - Switch ON allows external clock to be
internally generated, used when a modem is not being utilized.

SW6

Special feature - Optional feature is switched ON for program control of data rate selector.

SW7

Maintenance clock - Switch ON enables the clock that is
used for maintenance purposes only.

SW8

Not used.

OFF OFF OFF OFF OFF OFF OFF OFF OFF

llllllllll

SWITCH NO. \ 1

8 I ~

E38 SWITCH
LOGICAL 1 = ON
LOGICAL 0 = OFF
FACTORY ADORESS 1600

E39
SWITCH

Device Address Selection

326

o RXCSR
1 TXCSR
TXDBUF

M7951
15

10101010101010111 0 10111 0 1 0 l x l o l o l

~ ~ ~ ~ ~ ~ L~ ~~~~

ON OFF OFF ON OFF OFF
LOGICAL 1 = ON
LOGICAL 0 = OFF

~ ~ ~ ~ ~ ~

SWITCH NO.

FACTORY ADDRESS 440

E39 SWITCH

Interrupt Vector Selection

Guide for Setting Switches to Select Device Address
Module
Switch No.
Bit No.

1
2
12 11

E38
5
4
10 9
8

E39
2
1
4
3

Device
Address

ON 760010
ON
760020
ON ON 760030
ON
760040
ON
ON 760050
ON ON
760060
ON ON ON 760070
ON
ON
ON ON
ON
ON
ON
ON ON
ON ON ON
ON
ON
ON ON
ON

760100
760200
760300
760400
760500
760600
760700
761000
762000
763000
764000

NOTE
ON means switch closed to respond to logical 1 on the bus.

327

M7951
Guide for Setting Switches to Select Vector Address

Switch No.
Bit No.

E39
5

4
7

ON
ON
ON
ON
ON
ON
ON
ON

6
5

7
4

Vector
Address

ON
ON
ON
ON
ON
ON
ON

ON
ON

300
310
320
330
340
350
360
370
400
500
600
700

Receiver Status Register (RXCSR)
Receiver Status Register Bit Description
Bit

Function

Data Set Change (OAT SET CH) - When set, this bit indicates
a modem status change. This bit is set by a transition of any
of the following lines:
•
•
•
•
•

Ring
Clear to send
Carrier
Secondary received data
Data set ready.

If bit 05 of this register is set, the setting of this bit will cause
a RCVR interrupt.
Read only; cleared by INIT, master reset, and the DTI SEL 0
(RXCSR read strobe).
328

M7951
Receiver Status Register Bit Description (Cont)
Bit

Function

Ring - This bit reflects the state of the modem ring line. When
set, this bit indicates that a ring signal is being received from
the modem. Read only.

Clear to Send (CLR TO SEND) - This bit reflects the state of
the clear to send line from the modem. When set, this bit indicates that the modem is ready to accept data.

Carrier - This bit reflects the state of the modem carrier.
When set, this bit indicates that the carrier is up. Read only.

Receiver Active (REC ACT) - When the internal synchronous
mode is selected, this bit is set when the proper number of
contiguous sync characters (either one or, normally, two)
have been received. If external synchronous or isochronous
mode is selected, this bit follows the state of the search sync
bit (bit 04 of this register).
Read only; cleared by INIT, master reset, and SCH SYNC (1) H
(search sync) making 1 to 0 transition.

Secondary Receive Data (SEC RCV DAT) - This bit reflects
the state of the secondary receive data line from the modem.
This bit provides a receive channel for supervisory data from
the modem to the processor. Read only.

Data Set Ready (DAT SET RDY) - This bit reflects the state of
the data line from the modem. When set, this bit indicates
that the modem is powered up and ready. Read only.

STRIP SYNC - This bit determines whether sync characters
received from the modem are to be presented to the program
for reading. When this bit is set, received characters that
match the contents of the sync register do not cause a RCVR
interrupt provided no errors are detected, i.e., bit 15 of the
RXDBUF is clear.

Receiver Done (RX DONE) - This bit is set when synchronization has been achieved and a character has been loaded
into the RXDBUF, provided the STRIP SYNC bit is not set. If
the STRIP SYNC bit is set and the received character is a
sync character without errors, i.e., bit 15 of the RSDBUF is
clear, this bit will not be set.
329

M7951
Receiver Status Register Bit Description (Cont)
Bit

Function

Receiver Interrupt Enable (RX INTEB) - When set, allows a
RCVR interrupt request to be generated when the RX done bit
is set.
Read/write; cleared by INIT and master reset.

Data Set Interrupt Enable (OAT SET INTEB) - When set, allows a RCVR interrupt request to be generated when the OAT
SET CH bit is set.

Search Sync (SCH SYNC) - When set in the internal synchronous mode, enables the RCVR synchronization logic and
causes the RCVR to start comparing incoming data bits to the
contents of the sync register in an attempt to recognize a
sync character.
Read/write; cleared by INIT and master reset.

Secondary Transmit Data (SEC XMIT) - This bit reflects the
state of the secondary transmit data line to the modem. This
bit provides a transmit channel for supervisory data from the
processor to the modem.

Request to Send (REO TO SO) - When set, this bit causes
the request to send line to the modem to be reasserted. The
request to send line is a control lead to the modem. This line
must be asserted before the interface can transmit data to the
modem.

Data Terminal Ready (DATA TERM ROY) - When set, this bit
indicates that the interface is powered up, programmed, and
ready to receive data from the modem.
Setting this bit causes the data terminal ready line to the
modem to be asserted. The data terminal ready line is a control lead for the modem communication channel. When asserted, it permits the interface to be connected to the channel.
Read/write; optionally cleared by INIT and master reset.

330

M7951
11

• 08

07 •

NOT USED

f-----------

·00
RCVR DATA

READ

ONLY

---------------1·1

Receiver Data Buffer (RXDBUF)

Receiver Data Buffer Bit Description
Bit

Function

Receiver Error (RX ERR) - This bit is set whenever one of the
three receiver error bits is set (logical OR of bits 14, 13, and
12).
Read only; cleared only when bits 14, 13, and 12 are cleared.

Overrun Error (OVRN ERR) - When set, this bit indicates that
the processor has failed to service the RX DONE flag within
the time required to load another character into the RXDBUF,
i.e., (1 /baud rate) X (bit/char) seconds. Hence, the previous
character was overwritten (lost). This condition indicates the
loss of at least one character.
Read only; cleared by INIT, master reset, and DTI SEL 2
(RXDBUF read strobe).

Framing Error (FRM ERR) - When set, indicates that character received was not followed by a valid stop bit. This error
only occurs in the isochronous mode of operation.
Read only; cleared by INIT, master reset, and DTI SEL 2.

Parity Error (PAR ERR) - When set, indicates that the parity
of the received character does not agree with the parity programmed (odd or even). If parity is not programmed, this bit is
always cleared.

07-00

Receiver Data (RCVR DATA) - This register holds the received character for transfer to the program. The buffer is
right justified for 5, 6, 7, or a bits. If parity is received it is also
loaded into the buffer at the next vacant higher order bit position. Therefore, if a 5-bit character plus parity is framed by the
RCVR, the parity bit would be loaded into bit position 05 in the
RXDBUF and presented to the program for reading. If an a-bit
character plus parity is framed, the parity bit would not be
presented to the program for reading.
Read only buffer; cannot be cleared; INIT or master reset sets
the buffer to all 1s. Reading the RDXBUF causes the RXDONE
bit in the RXCSR to clear.
331

M7951
15

07 4

.00
SYNC REGISTER

141.-----------WRITE ONLY----------_.!

Parameter Status Register (PARCSR)
Parameter Status Register Bit Description
Bit

Function

13,12

Mode Select (MODE SEL) - These bits control the mode of
operation. Modes are selected as follows.
Mode

Bit 13

Internal Synchronous
External Synchronous
Isochronous
Illegal (Not Used)

1
0
0

Bit 12
1
0
0

Write only.
11, 10

Word Length Select (WORD LEN SEL) - These bits control
the length of characters received and transmitted by interface. Word length (not including parity) is selected as follows.
Bit/Char

Bit 11

Bit 10

5
6
7
8

0
0
1

0
1
0

Write only.

PAR ENB - If this bit is set, parity for each character will be
(parity enable) generated by the XMTR and checked by the
RCVR. If character length is fewer than eight bits, the parity
bit for received data is loaded into the RXDBUF for reading by
the program. If bad parity is detected at the RCVR, the parity
error flag is set (bit 12 of the RXDBUF). Write only.

332

M7951
Parameter Status Register Bit Description (Cont)
Bit

Function

Parity Sense Select (PAR SEN SEL) - When the parity enable
bit (bit 09 of this register) is set, the sense of the parity (odd
or even) is controlled by this bit. When this bit is set, even
parity is generated by the XMTR and checked for by the
RCVR (the program does not have to provide a parity bit to
the XMTR). When this bit is cleared, odd parity is generated
and checked. Write only.

07-00

Sync Register - This register contains the sync character.
The sync character is used by the RCVR to detect received
sync characters and thereby achieve synchronization.
The sync character is used as a fill character by the XMTR
when operating in the synchronous mode. Fill characters are
operating in the synchronous mode. Fill characters are transmitted when the program fails to provide characters to the
XMTR fast enough to maintain continuous transmission, i.e.,
(1 /baud rate) X (bit/char) seconds - 1/2 (bit time).

Transmitter Status Register (TXCSR)

Transmitter Status Register Bit Description
Bit

Function

Data Not Available (DNA) - This bit is set by the XMTR when a
fill character is transmitted. This applies only to the synchronous mode of operation and is caused by late program response to a TX DONE interrupt request.
The processor response to TX DONE must be within (16fbaud
rate) - (bit/char) seconds - 1/2 (bit time). If not, the fill
character is transmitted.
If bit 05 of this register is set, setting this bit causes an XMTR
interrupt request.
Read only; cleared by INIT, master reset, and DTI SEL 4
(TXCSR read strobe).

333

M7951
Transmitter Status Register Bit Description (Cont)
Bit

Function

Maintenance Data (MAl NT DATA) - This bit is used in the internal loop and external loop maintenance. Read/write bit;
cleared by INIT or master reset.

Single Step Maintenance Clock (SS ClK) - This bit is used in
the internal loop and external loop maintenance modes by diagnostic program to simulate the XMTR and RCVR clocks.
Read/write; cleared by INIT or master reset.

12, 11

Maintenance Mode Select 01 and 00 (MSO 1-MSOO) - These
bits are used to select the normal mode of operation or one of
three maintenance modes. Modes are selected as follows.

Mode

Bit 12

Bit 11

Normal
Internal Maintenance loop
External Maintenance loop
System Test

o
o

0
1

Read/write; cleared by INIT and master reset.
10

Receiver Input (RX INP) - This bit monitors the RCVR input in
the internal loop and external loop maintenance modes. Read
only.

Master Reset (MSTRST) - This bit is used to generate a ClR
(clear) pulse, which initializes the registers and the XMTR
and RCVR and inhibits the BRPl Y l (bus reply) signal. This bit
remains at a 1 for only 3 J-Ls after being set. Read/write.

Transmitter Done (TX DONE) - This bit is set by INIT and master reset and when the first bit of the character contained in
the XMTR register is placed on the XMTR output line. If bit 06
of this register is set when this bit is set, an XMTR interrupt
request is generated.

Transmitter Interrupt Enable (TX INTEB) - When set, this bit
allows an XMTR interrupt request to be generated by the TX
DONE bit.

334

M7951
Transmitter Status Register Bit Description (Cont)
Bit

Function

Data Not Available Interrupt Enable (DNA INTEB) - When set,
this bit allows a XMTR interrupt request to be generated by
the DNA bit.

Send - When set, this bit enables the XMTR and transmission
will start when a character is loaded into the TXDBUF. This bit
must remain set until the entire message is transmitted. If
not, transmission of the character currently in the XMTR register is completed and the XMTR will enter the idle state.
Read/write; cleared by INIT and master reset.

Half Duplex (HALF DUP) - When this bit is set, operation will
be in the half-duplex mode. In this mode, the RCVR is disabled
whenever bit 04 of this register is set.

Break - When this bit is set, the serial XMTR output D5 SERIAL DATA OUT H is held in the space (constant low) condition; otherwise, operation is normal. This bit is used by the diagnostic program in the internal loop or external loop
maintenance modes to inhibit the XMTR output while inputting
data to the RCVR via bit 14 of this register.
Read/write; cleared by INIT and master reset.

•

07.

NOT USED

•

XMTR DATA

1 - - - - - - - - - - WRITE O N L y - - - - - - - - - - - - t · 1

Transmitter Data Buffer (TXDBUF)
Transmitter Data Buffer Bit Description
Bit

Function

07-00

Transmitter Data (XMTR DATA) - This register is loaded by
the program with the character to be transmitted. Character
length is from five to eight bits. The character is right justified.
If a parity bit is enabled, it is generated by the interface.
Write only. INIT or master reset places all 1s in this register.

335

M7952

M7952
KWV11-A PROGRAMMABLE REAL TIME CLOCK

Amps

+5
1.75

Bus Loads

+ 12
0.01

AC
3.41

Cables

DC
BC04Z
BC08R

Standard Addresses
CSR
BufferIPreset Register (BPR)

170420
170422

Vector
440

Diagnostic Programs
Refer to Appendix A.

Related Documentation
ADV11-A, KWV11-A, AAV11-A, DRV11 User's Manual (EK-ADV 11-0P)
Field Maintenance Print Set (MP00200)
Microcomputer Interfaces Handbook (EB-20 175-20)

336

CLK STl

~R18

~R19

o 00

BIT 11

BIT 2
ADDRESS
SWITCHES

BIT 8

BIT 3

VECTOR
SWITCHES

MR-OBI7

M7952

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
11 11 11 1 1 1 0 10 1 0 1 1 1 0 1 0 10 1 1 10 1 0 1 0 1 0 I :g~~I~~
STANDARD ADDRESS
CONFIGURATION

I I I I I I I I I I
I I I I I I I I I I

OFF OFF OFF ON

(170420)

ADDRESS
SWITCH (S1)

OFF OFF OFF

ON OFF OFF

10 I
MA-0868

KWV 11-A CSR Address Switches (Set for 170420)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
o 1 0 1 1 0 1 0 1 0 1 0 1 1 10 1 0 11 1 0 1 1 0 1 0 10 I:g~~I~~
STANDARD VECTOR
CONFIGURATION

(440)

VECTOR
SWITCH (S3)

I I I I I I
Ii * * * * * I
ON

OFF OFF ON

OFF OFF

KWV 11-A Vector Address Switches (Set for 000440)

OFF~'ON
TTL REFERENCE
-------

~--------.--_--~--~~I
(JI-L1

BOARD HANDLE

________

ST LEVEL 2.
ST SLOPE 1 (J'-Tl
RIB
BOARD FINGERS

KWV 11-A Slope/Reference Level Selector Switches and Controls

NOTE
The user should take care that both TTL and variable switches
for either Schmitt trigger are not on simultaneously. This condition will not damage components, but will produce unpredictable reference levels. Note also that if no Signal is connected
to a Schmitt trigger input, both threshold switches for that ST
should be open for noise immunity. Alternatively, ST1 IN and
ST2 IN can be grounded externally.

338

M7952

INT 2

FOR

MAINT

ose

MAINT
ST1

INT OV

RATE

MODE

GO
11-4310

CSR Bit Assignments

CSR Bit Definitions
Bit

Function

ST2 Flag - Set by the firing of Schmitt trigger 2 or the setting of
the MAINT ST2 bit in any mode while the go bit or the ST2 go
enable bit is set. Cleared under program control. Also cleared at
the 1-going transition of the go bit unless the ST2 go enable bit
has previously been set.
Must be cleared after servicing an ST2 interrupt to enable further interrupts. When cleared, any pending ST2 interrupt
request will be canceled. If enabled interrupts are requested at
the same time by bits 07 and 15, bit 07 has the higher priority.
Read/write to O.

Interrupt on ST2 (lNT 2) - Set and cleared under program control.
When set, the assertion of ST2 flag will cause an interrupt. If set
while ST2 flag is set, an interrupt is initiated. When cleared, any
pending ST2 interrupt request will be canceled. Read/write.

ST2 Go Enable - Set and cleared under program control. Also
cleared at the 1-going transition of the go bit.
When set, the assertion of ST2 flag will set the go bit and clear
the ST2 go. enable bit. Read/write.

Flag Overrun (FOR) - Set when an overflow occurs and the
overflow flag is still set from a previous occurrence, or when
ST2 fires and the ST2 flag is already set. Cleared under program control and at the 1-going transition of the go bit.
This bit provides the programmer with an indication that the
hardware is being asked to operate at a speed higher than is
compatible with the software. Read/write.

339

M7952
CSR Bit Definitions (Cont)
Bit

Function

Disable Internal Oscillator (010) - Set and cleared under program control.
For maintenance purposes, this bit inhibits the internal crystal
oscillator from incrementing the clock counter. Used in conjunction with bit 10 below. Read/write.

MAINT OSC - Set under program control. Clearing is not required. Always read as a O.
For maintenance purposes, setting this bit high simulates one
cycle of the internal 10 MHz crystal oscillator used to increment
the clock counter. Write only.

MAINT ST2 - Set under program control. Clearing is not required. Always read as a O.
Setting this bit simulates the firing of Schmitt trigger 2. All functions initiated by ST2 can be exercised under program control
by using this bit. Write only.

MAINT ST 1 - Set under program control. Clearing is not required. Always read as a O.
Setting this bit simulates the firing of ST 1. All functions initiated
by ST 1 can be exercised under program control by using this bit.
Write only.

OVFLO FLAG - Set each time the counter overflows. Cleared
under the program control and at the 1-going transition of the
go bit.
If bit 6 is set, bit 7 will initiate an interrupt. Bit 7 must be cleared
after the interrupt has been serviced to enable further overflow
interrupts. If cleared while an overflow interrupt request to the
processor is pending, the request is canceled. If enabled interrupts are requested at the same time by bits 07 and 15, bit 07
has the higher priority. Read/write to O.

340

M7952
CSR Bit Definitions (Cont)
Bit

Function

Interrupt on Overflow (INTO V) - Set and cleared under program
control.
When this bit is set, the assertion of OVFLO flag will generate
an interrupt. Interrupt is also generated if bit 6 is set while OVFLO flag is set. If cleared while an overflow interrupt request to
the procesor is pending tne request is canceled. Read/write.

05,04,
03

Rate - Set and cleared under program control.
These bits select clock counting rate or source.
5

Rate

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Stop
1 MHz
100 kHz
10 kHz
1 kHz
100 Hz
ST1
Line (50/60 Hz)

Read/write to O.
2, 1

Mode - Set and cleared under program control.

Mode 0:
Mode 1:
Mode 2:
Mode 3:

Read/write.

Go - Set and cleared under program control. Also cleared when
the counter overflows in mode o.
Setting this bit initiates counter action as determined by the
rate and mode bits. In modes 1, 2, and 3 it remains set until
cleared. In mode 0 it clears itself when counter overflow occurs.
Clearing bit 0 zeros and inhibits the counter. Read/write.

341

M7952
CSR Bit Settings for Mode 0, Single Interval

Bit and CSR Name

Bit Condition
as Written by
Processor

15-ST2 FLG

Will be set to 1 on ST2 event.
Cleared by leading edge of go bit assertion except when ST2 GO ENA
has previously been set.

14-INT2

Set to 1 by program if interrupt on
ST2 event is desired.

13-ST2 GO ENA

Set to 1 by program if go is to be set
by external signal to ST2. Cleared by
leading edge of go bit assertion.

12-FOR

(0)

11-D10

10-MAINT OSC

9-MAINT ST2

8-MAINT ST1

7-0VFLO FLG

(0)

Will be set to 1 by counter overflow.
Always cleared by leading edge of
go bit assertion.

6-INT OV

Set to 1 by program for interrupt on
counter overflow.

5-Rate 2

4-Rate 1

Remarks

See bit definitions.

3-Rate 0

2-Mode 1

Set by program to O.

1-Mode 0

Set by program to O.

O-Go

Set by program to 1 unless ST2 GO
ENA is set; remains 1 until written to
o by program. Cleared when counter
overflows.

x = 0 or 1, depending on user requirements.
(0) = automatically cleared by go bit assertion.
342

M7952
CSR Bit Settings for Mode 1, Repeated Interval

Bit and CSR Name

Bit Condition
as Written by
Processor

15-ST2 FLG

Will be set to 1 on ST2 event.
Cleared by leading edge of go bit assertion except when ST2 GO ENA
has previously been set.

14-INT 2

Set to 1 by program if interrupt on
ST2 event is desired.

13-ST2 GO ENA

Set to 1 by program if go is to be set
by external signal to ST2. Cleared by
leading edge of go bit assertion.

12-FOR

(0)

11-010

10-MAINT OSC

9-MAINT ST2

8-MAINT ST1

7-0VFLO FLG

(0)

Will be set to 1 by counter overflow.
Always cleared by leading edge of
go bit assertion.

6-INT OV

Set to 1 by program for interrupt on
counter overflow.

5-Rate 2

4-Rate 1

3-Rate 0

2-Mode 1

Set by program to 1.

Same as for mode 0, except that bit
is not cleared when counter overflows.

Remarks

See bit definitions.

1-Mode 0

O-Go

x = 0 or 1, depending on user requirements.
(0) = automatically cleared by go bit assertion.
343

M7952
CSR Bit Settings for Mode 2, External Event Timing

Bit and CSR Name

Bit Condition
as Written by
Processor

15-ST2 FLG

Will be set to 1 on ST2 event.
Cleared by leading edge of go bit assertion except when ST2 GO ENA
has previously been set.

14-INT2

Set to 1 by program if interrupt on
ST2 event is desired.

13-ST2 GO ENA

Set to 1 by program if go is to be set
by external signal to ST2. Cleared by
leading edge of go bit assertion.

12-FOR

(0)

11-D10

10-MAINT OSC

9-MAINT ST2

8-MAINT ST1

7-0VFLO FLG

(0)

Will be set to 1 by counter overflow.
Always cleared by leading edge of
go bit assertion.

6-INT OV

Set to 1 by program for interrupt on
counter overflow.

Remarks

x = 0 or 1, depending on user requirements.
CO) = automatically cleared by go bit assertion.

344

M7952
CSR Bit Settings for Mode 2, External Event Timing (Cont)

Bit and CSR Name

Bit Condition
as Written by
Processor

5-Rate 2

4-Rate 1

3-Rate 0

1-Mode 0

Remarks

See bit definitions.

Set by program to 2.

O-Go

Set by program to 1 unless ST2 GO
ENA is set; remains 1 until written to
o by program. Cleared when counter
overflows.

x = 0 or 1, depending on user requirements.
(0) = automatically cleared by go bit assertion.
Mode 3 (external event timing from 0 base) is identical to mode 2 except
that the counter is zeroed after ST2 pulse. Counter continues to increment
until go bit is set to O.

345

M7954

M7954
IBV11-A LSI-11/INSTRUMENT BUS INTERFACE

Amps

Bus Loads

+12 AC
+5
0.8
o 1.77
(1.5 max.)

Cables

DC
1.0 BN 11 A used from IBV 11-A to first instrument.
BNO 1A used to any additional instruments.

Addresses

IBS (Instrument Bus Status Register)
IBD (instrument Bus Data Register)

Standard

MINC

160150
160152

171420
171422

Vectors
Error
Service request
Command and talker
Listener

420
424
430
434

Diagnostic Program
Refer to Appendix A.

Related Documentation
IBVtt-A LSI-tt/lnstrument Bus Interface User's Manual (EK-IBV11-TM)
Digital Interface for Programmable Instrumentation (IEEE Std. 488-1975)
Field Maintenance Print Set (MP00274)
Microcomputer Interfaces Handbook (EB-20 175-20)

346

M7954

VECTOR ADDRESS
SELECT SWITCHES

1511
DEVICE
IIBS & IBD REGISTERS)
ADDRESS SELECT
SWITCHES
IS21

IBV 11-A Address Bits

347

M7954
IBS REGISTER ADDRESS FORMAT
15

",,~J~~2~,~~ :'~t.;~1T
S2 INDIVIDUAL
SWITCH NUMBERS

IIIIIIIII

O'IBS REGISTER
I ' IBD REGISTER
NORMALLY 0
(RESERVED FOR
FUTURE USE)

NOTES:
1. OFF' Logical 0; ON· Logical 1
2. Only tho IBS REGISTER ADDRESS I. configured via S2. The IBD REGISTER ADDRESS always equals tho
IBS REGISTER ADDRESS +2.

INTERRUPT vECTOR

o • ERROR

I I

" 'CONFIGURATION
' ' ' ' ' ,moo (000420)
'''"'''.[

OFF

I ' SERVICE REQUEST
o • COMMAND AND TALKER

ON ,DISABLE ERRI

!~6~~~rTS

. . . - ' ' - - _ L - _ . L - _ . L - _ . L -_ _ _ _ _...L-....

51 INDIVIDUAL
SWITCH NUMBERS

OFF' NORMAL (ENABLE)
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-' ERRI INTERRUPTS

NOTES
1

OFF~LoglcoIO.

Only the VECTOR ADDRESS bits (8 4) ore conflQured ylO S1.
hardware - selected for the functIons shown

51-8 OFF: IBV11-A
51

ON~Loc;jlcol

1
Bits :3 and 2 ore

IBV11-A

Ihe only system controller connected to the instrument busj ERR1 Inlerruptsenobled

ON = Another system controller

connected to the instrument bus; ERR1 interrupts disabled.

IBV 11-A Interrupt Vector Addresses
08

15
IBS

07
I

BIT

I I Lt::

TCS CR/W)
EOPCR/W)
REMCR/W)
IBC CR/W)
LON CR/W)
TON (R/W)
IE CR/W)
ACC (R/W)
LNR (R)
TKR (R)
CMD (R)
(NOT USED)
(NOT USED)
ERI (R)
ER2 (R)
SRQ (R/W)

MR-0819

Instrument Bus Status Register
348

M7954
IBS Register Bits Description
Bit

Function

Take Control Synchronously (TCS) - Set and cleared under program control to enable or disable the IBV 11-A contro"er-incharge function by taking control synchronously or by negating
ATN. Setting TCS wi" cause NRFD to be asserted for at least
500 ns before DAV is checked. ATN is then asserted when DAV
is not asserted. NRFD must be unasserted and CMD is set 500
ns (minimum) after ATN is asserted. TCS is cleared by BINIT L
and IFC.

End or Po" (EOP) - Set and cleared under program control to
assert or unassert the EOI line. EOP is cleared by BINIT Land
IFC.

Remote On (REM) - Set and cleared under program control to
assert or unassert the REM line. REM is cleared by BINIT Land
IFC.

Interface Bus Clear (lBC) - When set, the leading edge of IBC
produces IFC for 125 (approximately). At the end of IFC, TCS is
automatically asserted and IBC is automatically cleared. IBC is
cleared by BINIT L.

Listener On (LON) - Set or cleared by the program to enable or
disable the IBV 11-A listener function. When LON is set and the
DAV line is asserted, the IBS LNR bit (bit 08) becomes set.
When LON is cleared, the IBV11-A ignores DAV. LON is cleared
by BINIT Land IFC.

Talker On (TON) - Set or cleared by the program to enable or
disable the IBV 11-A talker function. TON is cleared by BINIT L
and IFC.

Interrupt Enable (IE) - Set and cleared by the program to enable
or disable the IBV 11- A talker function. TON is cleared by BINIT L
and IFC.

Accept Data (ACC) - Set and cleared by the program. When
ACC is cleared, reading a data byte from the DIO lines wi" automatica"y assert the DAC line and clear the LNR bit (bit 08).
When ACC is set, the program must clear the low byte of the IBD
register in order to clear the LNR status bit and assert the DAC
line.

349

M7954
IB5 Register Bits Description (Cont)
Bit

Function

Listener Ready (LNR) - When set, LNR indicates that the IBV 11A has a data or command byte that is ready for reading from the
low byte of the IBO. LNR is set when LON is set and the DAV line
becomes asserted. LNR is cleared by reading the IBO low byte if
ACC is cleared, or by clearing the IBO low byte if ACC is set.
LNR is also cleared when LON is cleared by the program and by
BINIT Land IFC.

Talker Ready (TKR) - When set, TKR indicates to the LSI-11
processor that the IBV 11-A is ready for the next data byte to
betransmitted to the 010 lines via the low byte of the IBD register.

Command Done (CMD) - When set, CMO indicates to the LSI-11
processor that the IBV 11-A is ready for the next command byte
to be transmitted to the 010 lines via the low byte of the IBD register.

Not used. Read as O.

Error 1 (ER 1) - Set whenever a conflict occurs between the instrument bus ATN, IFC, or REN lines and their IBV 11-A control
hardware. When set, ATN H is cleared and cannot be set. This
condition can only be cleared by clearing the cause of the error.
ER 1 can occur when another system controller is connected to
the instrument bus. The error can then be suppressed by setting
the ER 1 inhibit switch (S 1-8) on the IBV 11-A module to the ON
position. If the IBV 11-A is the only system controller, set S 1-8 to
the OFF position.

Error 2 (ER2) - Set when the IBV 11-A tries to send a data or
command byte while there is no active listener or command acceptor on the instrument bus. ER2 is cleared by clearing both
the TON and TCS bits.

Service Request (SRO) - This bit always indicates the status of
the instrument bus SRO line. It may be written (set and cleared)
if the ER 1 inhibit switch is set.

350

M7954
OS

IBD
REGISTER

07
I

00
I

BIT

I
I

I'
NOTE:

NDAC<S:I> (R/W)
(DATA LINES)
DAC (R) (NDAC INVERTED)
DAV (R)
RFD (R) (NRFD INVERTED)
SRQ (R)
REN (R)
IFC (R)
ATN (R)
EOI (R)

R/W = Read I Write Bit
R • Read-Only Bit

* May be written only if ERI inhibit switch is on.
MR-082a

Instrument Bus Data Register

IBD Register Bit Description
Bit

Function

15-8

Instrument bus control line status. The program can monitor the
signal status of all eight control signals by reading this byte.
Note that DAC (bit 08) and RFD (bit 10) are inverted with respect to the actual instrument bus signal lines.

7-0

Instrument bus data input/output. The program can read or
write via the register byte to receive or transmit command or
data bytes over the instrument bus. Bits 7 -0 correspond to DIO
lines 8-1.

351

M7955

M7955
MSV11-C MOS READ/WRITE MEMORY

Module

Model

Description

M7955-YA

MSV 11-CA

4K by 16-bit read/write memory

Amps

Bus Loads

Cables

+5
+ 12
1.1
0.54
(2.0 max.) (0.56 max.)

AC
2.32

None

DC
1

Standard Addresses
Module is shipped configured to start at bank o.

Vectors
None

Diagnostic Programs
Refer to Appendix A.

Related Documentation
MSVll-C User's Manual (EK-MSV11-0P)
Field Maintenance Print Set (MP00259)
Microcomputer Processor Handbook (EB-18451-20)

352

M7955

Sl
S2
S3

S4
S5
OFF~ON

W14 W15

W12

W6 W2 W1 W5

M7955/MSV 11-C Jumpers
NOTES
1.

Only one dynamic memory module in a system is needed
to reply to the refresh bus transactions initiated by the
processor. The module selected should be the one with
the longest access time.

If a REV11 (M9400-YA or M9400-YC) provides refresh, only
the processor-resident memory (if present) should reply to
refresh. If the processor board has no resident memory,
the memory module electrically farthest from the REV11
should reply.

If MSV11-Cs are mixed with MSV11-Bs, the MSV11-Cs
should use internal refresh. Again, the memory electrically
farthest from the refreshing device should reply. Refer to
the "Refresh Configuration Procedure" in the "Systems
Configurations" section.

353

M7955
MSV11-C Jumper Configuration When Shipped
Jumper
Name
W1
W2
W3
W5

Jumper
State

Function Implemented
Battery backup power connected to system power.

Battery backup power only.

W1 W2 W3 W5
R
I
I
R
I
R
R
I

Battery backup power available but not desired for this
MSV 11-C module.
W6
W7

Internal refresh enabled.
Reply to refresh disabled.
W6 W7
R

External refresh; no reply.

External refresh; reply enabled.
W4
W8
W12
W16

W14

Factory configured to enable the memory banks appropriate to the memory model. These are normally not
changed except for:
1.

Maintenance - Refer to chapter 4 of MSV11-C
User's Manual, EK -MSV 11-0P.

Configuring for 28K system: Remove W16 to disable upper 4K. See configuration rules in the
"Systems Configurations" section.

Bus grant continuity provided.

W15
• Memory bank enable jumpers when supplied.

354

M7955
Module
Number

Option
Designation

Memory
Size
W4 W8 W12 W16

M7955-YD
M7955-YC
M7955-YB
M7955-YA

MSV11-CD
MSV11-CC
MSV11-CB
MSV11-CA

16K
12K
8K
4K

I
I
I

I
I
I
I

I
I

I
R
R
R

R
R

MsV11-CD Addressing Summary
Starting
Address

MsV11-CD
Banks

Address Range

0
20000
40000
60000
100000
120000
140000
160000
200000
220000
240000
260000
300000
320000
340000
360000
400000
420000
440000
460000
500000
520000
540000
560000
600000
620000
640000
660000
700000
720000
740000
760000

0-3
1-4
2-5
3-6
4-7
5-10
6-11
7-12
10-13
11-14
12-15
13-16
14-17
15-20
16-21
17-22
20-23
21-24
22-25
23-26
24-27
25-30
26-31
27-32
30-33
31-34
32-35
33-36
34-37

0-77777
20000-117777
40000-137777
60000-157777
100000-177777
120000-217777
140000-237777
160000-257777
200000-277777
220000-317777
240000-337777
260000-357777
300000-377777
320000-417777
340000-437777
360000-457777
400000-477777
420000-517777
440000-537777
460000-557777
500000-577717
520000-617777
540000-637777
560000-657777
600000-677777
620000-717777
640000-737777
660000-757777
700000-777777

x
x
x

x-x
x-x
X.-x

355

Switch
Setting
51 52 53 54 55
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

M7955
NOTES
1.

Switch setting:
1 = ON

0= OFF
2.

Each memory bank = one 4K address space.

Switches 6, 7, and 8 are not used.

NOTE
When used in PDP-l1/23 systems, the MSV11-C memory cannot be configured in the 56K-64K byte (28K-32K word) range
or in the 248K-256K byte (124K-128K word) range.

356

M7957

M7957
DZV11 ASYNCHRONOUS MULTIPLEXER

Amps

Bus Loads

+ 12

1.15

0.39

AC
1.26

DC
1.0

Cables

BC11-U

Standard Addresses
Floating - Configurable within the range of 160000-177770.

Mnemonic

Address

Control and Status Register
Receiver Buffer
Line Parameter Register
Transmitter Control Register
Modem Status Register
Transmit Data Register

CSR
RBUF
LPR
TCR
MSR
TOR

16XXXO
16XXX2
16XXX2
16XXX4
16XXX6
16XXX6

xxx

= selected in accordance with floating device address convention.
Refer to Appendix B.

Vectors
300-777 in accordance with floating interrupt vector assignments. Refer to
Appendix B.

Diagnostic Programs
Refer to Appendix A.

357

M7957
Related Documentation
DZVll Asynchronous Multiplexer Technical Manual (EK-DZV11-TM)
DZV 11 Print Set (MP-00462-00)
Microcomputer Interfaces Handbook (EB-20 175-20)

NOTES
1.

Use H325 test connector to test individual lines.

Use H329 test connector to test module without cables.
x

15
ADDRESS
SELECTION

I I
1

\~,

r-A----..
14

SWITCH E30

Address Switches
r-"---.,...---'---., ~ ,,---"---., ~ .,---"'----,
15

VECTOR
ADDRESS

SWITCH E2

Vector Switches

Modem Control Jumpers
There are eight jumpers used for modem control. The jumpers labeled W 1
through W4 connect Data Terminal Ready (DTR) to Request To Send
(RTS). This allows the DZV 11 to assert both DTR and RTS if using a modem
that requires control of RTS. These jumpers must be installed to run the
cable and external test diagnostic programs. The remaining four jumpers;
W5 through W8, connect the Forced Busy (FB) leads to the RTS leads.
With these jumpers installed, the assertion of an RTS lead places an ON or
BUSY signal on the corresponding forced busy lead. The forced busy jumpers (W5 through W8) are cut out unless the modem requires them.

358

M7957

W5
WB

-----..-C ~1

TE3 a::::
L-...-.

L........--.-----,I ~?_---'

W7
W6

~---,I ~~_----'
W1~

,...----W2

W12*

W9'

~W3

T;1\

W13'

W14' W15' W16'

A12

10000000000/
W10'

moooooom

ADDRESS SWITCHES

VECTOR SWITCHES

'NOTES:
JUMPERS W9, W12, W13, W14, W15, AND W16 ARE REMOVED ONLY FOR MANUFACTURING TESTS_
THEY SHOULD NOT BE REMOVED IN THE FIELD_
JUMPERS W10 AND W11 MUST REMAIN INSTALLED WHEN THE MODULE IS USED IN
A BACKPLANE THAT SUPPLIES LSI-11 BUS SIGNALS TO THE C AND D CONNECTORS
OF THE DZV11 (SUCH AS THE H9270).
WHEN THE MODULE IS USED IN A BACKPLANE THAT INTERCONNECTS THE C AND D SECTIONS TO AN ADJACENT MODULE,
JUMPERS W10 AND W11 MUST BE REMOVED_

M7957 Jumper Locations

Jumper Configuration
Jumper

Connection

Line

W1
W2
W3
W4
W5
W6
W7
W8

OTR to RTS
OTR to RTS
OTR to RTS
OTR to RTS
RTS to FB
RTS to FB
RTS to FB
RTS to FB

03
02
01
00
03
02
01
00

359

M7957
CONTROL
AND STATUS
(CSR)

CSR Bit Assignments

CSR Bit Assignments
Bit

Function

00-02

Not used.

Maintenance - This bit, when set, loops all the transmitter's serial output leads to the corresponding receiver's serial input
leads on a TTL basis. While operating in maintenance mode, the
EIA received data leads are disabled. Normal operating mode is
assumed when this bit is cleared. Read/write.

Master Clear - When written to a 1, this bit generates "initialize" within the DZV 11. A read-back of the CSR with this bit
set indicates initialize in progress within the device. This bit is
self-clearing. All registers, silos, and UARTS are cleared with
the following exceptions.
1.

Only bit 15 of the receiver buffer register (valid data) is
cleared; the remaining bits, 00-14, are not.

The high byte of the transmitter control register is not
cleared by master clear.

The modem status register is not cleared by master clear.

Master Scan Enable - This read/write bit must be set to permit
the receiver and transmitter control sections to begin scanning.
When cleared, transmitter ready (CSR 15) is inhibited from setting and the received character buffers (silos) are cleared.

Receiver Interrupt Enable - This bit, when set, permits setting
CSR 07 or CSR 13 to generate a receiver interrupt request.
Read/write.

360

M7957
CSR Bit Assignments (Cont)
Bit

Function

Receiver Done - This is a read-only bit that sets when a character appears at the output of the first-in/first-out (FIFO) buffer. To
operate in interrupt-per-character mode, CSR 06 must be set
and CSR 12 must be cleared. With CSR 06 and CSR 12 cleared,
character flag mode is indicated. Receiver done clears when
the receiver buffer register (RBUF) is read or when master scan
enable (CSR 05) is cleared. If the FIFO buffer contains an additional character, the receiver done flag stays cleared a minimum of one microsecond before presenting that character.

08-09

Transmitter Line - These read-only bits indicate the line number
whose transmit buffer requires servicing. These bits are valid
only when transmitter ready (CSR 15) is set, and are cleared
when master scan enable is cleared. Bit 08 is the least significant bit.

10-11

Not used.

Silo Enable Alarm - This is a read/write bit. When set, it enables
the silo alarm counter to keep count of the number of characters stored in the FIFO buffer. The counter is cleared when the
silo alarm enable bit is cleared. Conditioning of this bit must occur prior to any character reception.

Silo Alarm - This is a read-only bit set by the hardware after 16
characters have been entered into the FIFO buffer. Silo alarm is
held cleared when silo alarm enable (CSR 12) is cleared. This
bit is reset by a read to the receiver buffer register and does not
set until 16 additional characters are entered into the buffer. If
receiver interrupt enable (CSR 06) is set, the occurrence of silo
alarm generates a receiver interrupt request. Reception with
CSR 06 cleared, permits flag mode operation of the silo alarm
bit.

Transmitter Interrupt Enable - This bit must be set for transmitter ready to generate an interrupt. Read/write.

361

M7957
CSR Bit Assignments (Cont)
Bit

Function

Transmitter Ready - This bit is read only and is set by the hardware. This bit sets when the transmitter clock stops on a line
whose transmit buffer may be loaded with another character and
whose associated TCR bit is set. The transmitter number, specified in CSR 08 and CSR 09, is valid only when transmitter ready
is set. Transmitter ready is cleared by any of the following conditions:

a. when master scan enable is cleared
b. when the associated TCR bit is cleared for the line number
pointed to in CSR 08 and CSR 09
c. at the conclusion of the load instruction of the transmit data
register (low byte only).

If additional transmit lines require service, transmitter ready
reappears within 1.4 microseconds from the completion of the
transmit data register load instruction. The occurrence of transmitter ready with transmitter interrupt enable set, generates a
transmitter interrupt request.

362

M7957
RECEIVER
BUFFER
IRBUF)

DATA
VALID

LINE
B

LINE
A

RBUF Bit Assignments

RBUF Bit Assignments
Bit

Function

00-07

Received Character - These bits contain the received character, right justified. The least significant bit is bit 00. Unused bits
are o. The parity bit is not shown.

08-09

Received Character Line Number - These bits contain the line
number upon which the received character was received. Bit 08
is the least significant bit.

10-11

Not used.

Parity Error - This bit is set if the sense of the parity of the received character does not agree with that designated for that
line.

Framing Error - This bit is set if the received character did not
have a stop bit present at the proper time. This bit is usually interpreted as indicating the reception of a break.

Overrun Error - This bit is set if the received character was preceded by a character that was lost due to the inability of the receiver scanner to service the UART receiver holding buffer on
that line.

Valid Data - This bit, when set, indicates that the data presented in bits 00- 14 is valid. This bit permits the use of a characterhandling program that takes characters from the FIFO buffer until there are no more available. This is done by reading this register and checking bit 15 until the program obtains a word for
which bit 15 is o.

363

M7957
LINE
PARAMETER
(LPR)

LPR Bit Assignments

LPR Bit Assignments
Bit

Function

00-01

Parameter Line Number - These bits specify the line number for
which the parameter information (bits 3-12) is to apply. Bit 00 is
the least significant bit.

Not used. Must always be written as a 0 when specifying the parameter line number. Writing this bit as a 1 extends the parameter line number field into nonexistent lines. Parameters for lines
00-03 are not affected.

03-04

Character Length - These bits are set to receive and transmit
characters of the length (excluding parity) as shown below.

0
0

0
1
0

5 bit
6 bit
7 bit
8 bit

Stop Code - This bit sets the stop code length (0 = 1 unit stop;
1 = 2 unit stop or 1.5 unit stop if a five-level code is employed).

Parity Enable - If this bit is set, characters transmitted on the
line have an appropriate parity bit affixed, and characters received on the line have their parity checked.

Odd Parity - If this bit is set and bit 06 is set, characters of odd
parity are generated on the line and incoming characters are
expected to have odd parity. If this bit is not set, but bit 06 is
set, characters of even parity are generated on the line, and incoming characters are expected to have even parity. If bit 06 is
not set, the setting of this bit is immaterial.

364

M7957
LPR Bit Assignments (Cont)
Bit

Function

08-11

Speed Code - The state of these bits determines the operating
speed for the transmitter and receiver of the selected line.
11

Baud Rate

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
Invalid

Receiver Enable - This bit must be set before the UART receiver
logic can assemble characters from the serial input line. This bit
is cleared following a BINIT or device master clear.

13-15

Not used.

365

M7957
15

TRANSMIT
CONTROL
(TCR)

I I

LINE LINE LINE LINE
ENAB ENAB ENAB ENAB
a
3
2
1

TCR Bit Assignments

The TCR bits are represented in bits 00-03. These bits are read/write and
are cleared by BINIT or device master clear. Bits 04-07 are not used and
read as O.
The high byte of the TCR register contains the writable modem control lead,
the Data Terminal Ready (OTR). Bit designations are as follows.
Bit

08
09
10
11
12-15

Name
OTR line 00
OTR line 01
OTR line 02
OTR line 03
Unused; read as O.

Assertion of a OTR bit puts an ON condition on the appropriate modem circuit for that line. OTR bits are read/write and are cleared only by BINIT.
Jumpers have been provided to allow the RTS circuits to be asserted with
OTR assertions.
07

15
MODEM
STATUS
(MSR)

04
NOT USED

NOT USED

MSR Bit Assignments
Modem Status Register
The Modem Status Register (MSR) is a 16-bit read-only register. A read to
this register results in the status of the readable modem control leads, ring
and carrier. The ON condition of a modem control lead is interpreted as a
logical 1. Bits 04-07 and 12-15 are unused and read as a O. Remaining bit
designations are as follows.
Bit

00
01
02
03
04-07

Bit

Name
Ring line 00
Ring line 01
Ring line 02
Ring line 03
Unused; read as O.

08
09
10
11
12-15
366

Name
Carrier line 00
Carrier line 01
Carrier line 02
Carrier line 03
Unused; read as O.

M7957
15
TRANSMIT
DATA

12
NOT USED

(TOR)

TOR Bit Assignments

Transmit Data Register
The Transmit Oata Register (TOR) is a byte- and word-addressable, writeonly register. Characters for transmission are loaded into the low byte. TOR
bit 00 is the least significant bit. Loading of a character should occur only
when transmitter ready (CSR 15) is set. The character that is loaded into
this register is directed to the line defined in CSR bits 08 and 09. The high
byte of the TOR is designated as the break control register.
Each of the four multiplexer lines has a corresponding break bit for that
line. TOR bit 08 represents the break bit for line 00, TOR bit 09 for line 01,
etc. TOR bits 12 - 15 are unused. Setting a break bit forces that line's output
to space. This condition remains until cleared by the program. This register
is cleared by BINIT or device master clear. The break control register can
be utilized regardless of the state of the device maintenance bit (CSR 03).

367

M8012

M8012
BDV11 BUS TERMINATOR, BOOTSTRAP, AND DIAGNOSTIC ROM

Amps
+5
1.6

Bus Loads
+ 12
.07

AC
2

Cables

DC
None

Standard Addresses
ROM Window
Page Control Reg.
Scratch Pad Reg.
Option Select Reg.
Display Reg.
Line Clock CSR

173000-173776
177520
177522
177524 (read only)
177524 (write only)
177546

Standard Vectors
Line Clock

100

Diagnostic Programs
Refer to Appendix A.

Related Documentation
BDVII Bus Terminator, Bootstrap, Diagnostic ROM Technical Manual
(EK-BDV 11-TM)
Field Maintenance Print Set (MP00489)
Microcomputer Interfaces Handbook (EB-20175-20)

368

M8012
PURPLE

RED

GREEN LED

BLACK

O~FF
~N
__ 2

E15
SWITCH "A"
DIAGNOSTIC/
BOOTSTRAP
SWITCHES

__ 3
__ 4
__ 5

__ 6
__ 7
-_B

oDpN

OFF

23-0046E2
E21

~
__ 2

SWITCH "B"

-4
3
__

__ 5

DIAGNOSTIC/BOOTSTRAP
SWITCHES, BEVNT SWITCH

WITH ECO
MB012-1-00D1
WITHOUT ECO L.::..:_ _--'-_ _ _---'

BDV 11-A Switches and Indicators
D4 D6 D3 D2 D1

~ooo

[§""]

GREEN
LED

RESTART SWITCH

rcn)

HALT EN~BLE

Diagnostic Light Display

777524 READ ONLY
12

NOT USED

SWITCH NUMBER
ON = ONE
OFF = ZERO

______v-_ _ _

~J'~

__- - - -_ _ _

_ _ _ _ _ _ _ _J

E21

E15

(SWITCH "8")

(SWITCH "A")

Switch Register

369

M8012
777524 WRITE ONLY
15

NOT USED

LED
LOAD "0" TO TURN ON LED

Display Register

777546
07

NOT USED

NOT USED
1 = LINE CLOCK ENABLE

SWITCH "B5" MUST 8E
"ON" FOR PROGRAM CONTROLLED
LINE CLOCK

Line Clock CSR

777520
08

______________

________________

-JI'~

________________

______________

1ST 128 WORDS

2ND 128 WORDS

Page Control Register

777522
00

Read/Write Register

370

M8012
BDV11 Hardware Registers
Register

Function

Bus Address

Page Control
Register
(PCR)

Controls mapping of ROM
pages into physical ROM
addresses. Cleared when
power is turned on or
when RESTART switch is
activated. Sixteen bits.

177520. Word or byte
byte addressable; can
be read or written.

Read/Write
Register

Maintenance register used
for diagnostics. Cleared
when power is turned on
or when RESTART switch
is activated. Sixteen
bits.

177522. Word or byte
byte addressable; can
be read or written.

Switch
Register

Used for maintenance and
system configuration
(selects diagnostic and/
or bootstrap programs for
execution). Bits 0-11 of
the register (corresponding to E 15-1 through
E 15-8 and E21-1 through
E21-4, respectively) are
associated with BOAL
<0: 11 > L, respectively.
When an individual switch
of the register is closed
(on), the corresponding
BOAL signal is low (1).
Twelve bits.

177524. Read-only
register.

Display
Register

Controls the diagnostic
light display. Bits 0-3
of the register control
LEOs 01-04, respectively.
When a bit is set, the
corresponding LED is off;
cleared (all lights on)
when power is turned on
or when RESTART switch
is activated. Four bits.

177524. Word or byte
addressable; writeonly register.

371

M8012
BDV 11 Hardware Registers (Cont)
Register

Function

Bus Address

Line Clock
CSR

When cleared. this
register clamps the
BEVNT signal low (if
BEVNT switch is
closed). This action
permits program control
of the LSI-11 line time
clock (LTC) function.
Register cleared when
power is turned on or
when RESTART switch is
activated. One bit.

177546. Word or byte
addressable; writeonly register.

BDV11 (For ROMs 23-045E2 and 23-046E2 only)
Switch Settings and Mnemonics
For the discussion that follows. the M8012 switch E15 will be called "A"
and E21. "B."

Switches A 1 through B4 are defined as follows:
A10N
A2 ON
A3 ON

Execute CPU tests on power-up or restart.
Execute memory test on power-up or restart.
DECNET BOOT - A4. A5. A6. A7 are used as arguments.

Device

DUV11
DLV11-E
DLV11-F

ON
OFF
OFF

OFF
ON
ON

OFF
OFF
OFF

OFF
OFF
ON

DLV11-E RCSR = 175610; DLV11-F RCSR = 176500.

372

M8012
A4 ON Console test and dialog (A3 OFF).
A4 OFF Turnkey BOOT dispatched by switch setting (A3 OFF).
Switches A5, A6, A7, A8, B1 are used as arguments.

Device

Loop on Error
RK05
RL01
RX01
RX02
BDV11 ROM

OFF
OFF
OFF
OFF
OFF
ON

OFF
OFF
OFF
ON
ON
OFF

OFF
OFF
ON
OFF
ON
OFF

OFF
ON
OFF
OFF
OFF
OFF

ON
OFF
OFF
OFF
OFF
OFF

The BDV 11 ROM BOOT uses the following switches as arguments. (X = don't care.)

ROM

Extended DIAG
2708s
Program ROM

ON
OFF
OFF

X
ON
OFF

X
X
ON

All unused patterns or mnemonics will default to ROM BOOT
if switch B2, B3, or B4 is ON.
If an unrecognized mnemonic or switch setting (A5 through B 1) is encountered, the presence of additional ROM is checked (by checking B2, 3, 4)
and if present, the ROM BOOT is envoked.
If an unrecognized switch setting is encountered, a copy of the switches is

placed in location 2 with bit 15 set.
If no additional ROM exists, the switch checking routine will halt or the
mnemonic routine will reprompt.
If the console test is selected, the console test prompts with:
ZZK
Where ZZ is the decimal multiple of 1024.
START? Words of RAM found in the system.
Allowed responses are a two-character mnemonic with a one-digit octal
unit number, or one of two special, single-character mnemonics. The response must be followed by a return. The special single-character mnemonics are:
Y
N

Use switch settings to determine boot device; or,
HALT. Enter microcode ODT.
373

M8012
The two-character mnemonics are as follows. "N" is a digit from 1 to 7 indicating the unit number of the device.
DKN
DLN
DXN
DYN

RK05 bootstrap
RLO 1 bootstrap
RXO 1 bootstrap
RX02 bootstrap

BDV11 HALT/ENABLE, RESTART, AND BEVNT SWITCHES
HALT /ENABLE Switch
When this switch is in the ENABLE position, the LSI-11 CPU can operate
under program control. If the switch is placed in the HALT position, the CPU
enters the halt mode and responds to console OOT commands. While in
the halt mode, the CPU can execute single instructions, facilitating maintenance of the system. Program control is re-established by returning the
switch to the ENABLE position and entering a "P" command at the console
terminal (providing the contents of register R7 were not changed). Refer to
chapter 2 of the Microcomputer Handbook (1977 -1978) for a description of
console OOT command usage.

RESTART Switch
When the RESTART switch is cycled, i.e., moved from one side to the other
and back, the CPU automatically carries out a power-up sequence. Thus,
the system can be rebooted at any time for maintenance purposes.

BEVNT L Switch
Contact 5 of dip-socket switch E21 is the BEVNT L switch. When the switch
is off (open) the LSI-11 bus BEVNT L signal can be controlled by the powersupply-generated LTC signal. When the switch is on (closed), the LTC
function is program controlled; i.e., a single-bit write-only register in the
logic (address 177546, bit 6) clamps BEVNT L low when the register is
cleared. (The register is automatically cleared when the power is turned on
or when the RESTART switch is cycled.) The KW 11-L line time clock option
also uses bit 6 as the enable bit.

POWER OK LED and Tip Jacks
This green LED is lighted when the + 12 Vdc supply voltage is greater than
+ 10 V and the +5 Vdc supply voltage is greater than +4 V. The + 12 Vdc
voltage and the + 5 Vdc voltage can be measured at the tip jacks as indicated below. (Both J2 and J3 have a 560 Q resistor in series to prevent
damage from a short circuit; use at lease a 20,000 Q V meter to measure
the voltage.)

374

M8012
Jack

Color

Voltage

J1
J2
J3

Black
Red
Purple

Ground

+5 Vdc

+ 12 Vdc

Secondarily, the LED indicates the octal point for the diagnostic light display.
The BDV11 (M8012) is the new bootstrap module for the PDP-11/03s. It is
a quad module and it has 2K words of diagnostics in ROM installed on the
board. The failures of these diagnostics are indicated by the HALT address
in the ROM and by the state of the error lights on the board.
The "Diagnostic LED Error Display" table provides a cross-reference between the indications in the error lights and the failing system function. The
"BDV 11 Diagnostic Error Addresses" table provides a cross-reference between the HALT PC and the failing system function. (The HALT PC will be
displayed on the console terminal.)

375

Diagnostic LED Error Display

Red

Green Red
DCOK

Red

Red
Comments

OFF

+ 12 Vdc or +5 Vdc is bad.

OFF

CPU test error or fault, or configuration error.

OFF

Memory test error; register R 1 points to bad location.

OFF

Console serial line unit does not transmit.

OFF

Console terminal test waiting for response from operator on keyboard.

OFF

ON '

OFF

Load device status error.

OFF

Secondary bootstrap code incorrect. NOP instruction is not in location 000000; the medium is probably bad.

OFF

DECNET waiting for response from host computer.

OFF

DECNET received DONE FLAG set.

OFF

DECNET message received.

OFF

ROM BOOTSTRAP error.

HAL T switch is ON, unable to run (check computer and BDV 11
HAL T switch); or power-up mode is wrong; or system is hung.

M8012
04

02 000 1=

GREEN LEO

Diagnostic LED Error Display

BDV11 Diagnostic Error Addresses
Error
Address

Cause of Error

173022

Memory error 1. Write address into itself.

173040

Serial line unit switch selection incorrect; error in switches.

173046

Serial line unit error. CSR address for selected device in error.
Check CSR for selected device in floating CSR address area.

173050

CPU error 1. Register RO contains address of error.

173052

Memory error 2. Data test failed.

173106

Memory error 3. Write and read bytes failed.

173202

ROM loader error. Checksum on data block.

173240

CPU error 4. RO contains address of error.

173366

ROM loader error. Checksum on address block.

173402

ROM loader error. Jump address is odd.

173532

RL device error.

173634

CPU error 3. RO points to cause of error.

173642

A "NO" typed in console terminal test.

173656

Switch mode HALT. A match was not made with switches.

173656

RK device error

173670

Console terminal test. No DONE flag.

173706

CPU error 2. RO points to cause of error.

173712

RX device error
377

M8012

o
,.....-v-

3: 3:3: 3: J2

mTI o

CONMCIlJ3

3:3:3:3:~

W12

Wll
OFF

~:
=W13

~
~

OFF

@J5

MR·l2QP

BDV 11 Switch and Jumper Locations

378

M8012

00000

D1 D2 D3 D6 D4

OFF

__ 1
__ 2

__ 3
__ 4
W13

__ 5

-c:::::J-

__ 6
__ 7

__ B

ij
W6

E21
(DIAGNOSTIC/BOOTSTRAP
SWITCHES, BEVNT SWITCH)

E15
(DIAGNOSTI C/
BOOTSTRAP
SWITCHES)

BDV 11 Switches and Indicators

Socket Selection Logic
The socket selection logic determines which pair of sockets responds to
the ROM address signals. (Although the ROMs in the sockets actually respond, it is said, for ease of explanation, that the sockets respond).
Jumpers are inserted selectively in positions W 1-W4 and W9-W 12. These
jumpers cause the PCR page numbers and the selection signals (and,
therefore the sockets) to be related in definite ways. Group A in the
"BDV 11 Selection Signals/Sockets" table indicates that PCR pages are
assigned to specific ROM sockets. This is true within the confines of the
BDV11 module shipped by DIGITAL. On such a module, jumpers W1-W4 and
W9-W 12 are arranged as indicated under Group A in the table. Thus, the
PCR pages 0-17, for example, cause selection signal SB 1 L to be asserted, and SB 1 L causes sockets XE53 and XE48 to respond to address
signals A<O: 10> H. Other combinations of jumpers are possible, as indicated by Groups B through G in the table. Note that each selection signal
always selects the same pair of sockets; however, the relation of PCR
pages to selected sockets varies with jumper configuration.
379

peR
Group W1 W2 W3 W4 W9 W10 W11 W12

Page

Primary
Selection
Signal

(A<O:14>H)

Sockets
Selected

Addresses

SB1 L
0-17
20-37
SB2 L
40-47
SE1 L
50-57
SE2 L
360-377 SP1 L
340-357 SP2 L
320-337 SP3L
300-317 SP4L
260-277 SP5L
240-257 SP6L
220-237 SP7 L
200-217 SP8L

OK-2K
2K-4K
4K-5K
5K-6K
30K-32K
28K-30K
26K-28K
24K-26K
22K-24K
20K-22K
18K-20K
16K-18K

XE53jXE48
XE58jXE44
XE57jXE40
XE52jXE36
XE39jXE50
XE43jXE46
XE47 jXE42
XE51jXE38
XE55jXE37
XE60jXE41
XE59jXE45
XE54jXE49

40-57
60-77
0-7
10-17

SB1 L
SB2 L
SE1 L
SE2 L

4K-6K
6K-8K
OK-1K
1K-2K

XE53jXE48
XE58jXE44
XE57 jXE40
XE52jXE36

200-217
220-237
240-247
250-257

SB1 L
SB2 L
SE1L
SE2 L

16K-18K
18K-20K
20K-21K
21K-22K

Ibid.

240-257
260-277
200-207
210-217

SB1 L
SB2 L
SE1 L
SE2 L

20K-22K
22K-24K
16K-17K
17K-18K

Ibid .

c.u
CD
o

BDV11 Selection Signals/Sockets (Cont)
Primary
PCR
Selection Addresses
Signal
(A<O:14>H)
Group W1 W2 W3 W4 W9 W10 W11 W12 Page

· · · ·

I = inserted; R = removed.

270-277
250-257
230-237
210-217
260-267
240-247
220-227
200-207

Sockets
Selected

SP1L
SP2 L
SP3 L
SP4 L
SP5 L
SP6 L
SP7 L
SP8L

23K-24K
21K-22K
19K-20K
17K-18K
22K-23K
20K-21K
18K-19K
16K-17K

XE39/XE50
XE43/XE46
XE47/XE42
XE51/XE48
XE55/XE37
XE60/XE41
XE59/XE45
XE54/XE49

160-177 SP1 L
140-157 SP2 L
120-137 SP3 L
100-117 SP4 L
60-77
SP5 L
SP6 L
40-57
SP7 L
20-37
SP8 L
0-17

14K-16K
12K-14K
10K-12K
8K-10K
6K-8K
4K-6K
2K-4K
OK-2K

Ibid.

70-77
50-57
30-37
10-17
60-67
40-47
20-27
0-7

7K-8K
5K-6K
3K-4K
1K-2K
6K-7K
4K-5K
2K-3K
OK-1K

Ibid.

SP1 L
SP2 L
SP3 L
SP4 L
SP5 L
SP6 L
SP7 L
SP8 L

M8012
ROM Sockets Logic
The following figure represents the ROM sockets and shows the address
signals and enabling signals for each functional group of sockets. The diagnostic/bootstrap ROM sockets (which are selected by signals SB 1 Land
SB2 L) are supplied with 11 address bits, since these sockets are reserved
for 2K-word ROMs. The EPROM sockets (selected by signals SE 1 Land
SE2 L) are reserved for 1K ROMs; therefore, these sockets are supplied
with 10 address bits. The system ROM sockets can be occupied by either
2K ROMs or 1K ROMs; five jumpers on the BDV 11 module permit ROMs of
either size to be used.
W7

Al0 H -------o0ow;o----....-- ST2
+12 V

=t::

W13

+5V - - - - - - - O : 5 = = r S T 1

~
CB2

----,----()o

DB2 - - - - - '

CAUTION:
IMPROPER CONFIGURATION
OF THESE JUMPERS MAY CAUSE
ROM DAMAGE. BE SURE OF
ROM TYPE.

The following figure shows how these five i'Jmpers control the selection signals for the system ROM sockets, and relates the jumpers to the types of
ROM that can be used in the BDV 11. (If ROMs other than 8316E, 2716, and
2708 are used, do not alter configuration. See Caution.)

CAUTION
Improper configuration of these jumpers may cause ROM damage. Be sure of ROM type.

382

M8012

W7
Al0 H
+12 V

1
+5V

J
CB2~

ST2

~~
W13

i
r

DB2

ROM TYPE

1.
2
3.

ST1

JUMPERS INSERTED'
W5

W13

2708 2

2716

8316E3

8316E4

I=INSERTED; R=REMOVED
CB2 AND DB2 MUST BE SUPPLIED WITH EXTERNAL -5V POWER.
CHIP SELECT SIGNALS MUST BE PROGRAMMED AS FOLLOWS:

f.§.L

LOW

CS3
LOW

CHIP SELECT SIGNALS MUST BE PROGRAMMED AS FOLLOWS:

f.§.L
LOW

CS2
LOW

383

CS3
HIGH

M8013/14

M8013, M8014 RLV11 CONTROLLER

Amps

+ 12

6.5

1.0

Bus Loads

Cables

AC
3.2

BC08R-XX
70-12122 (1 per drive)

Transition Bracket Assembly
Terminator

70-12415-00
70-12293-00

Standard Addresses
CSR
BAR
DAR
MPR

174400
174402
174404
174406

Standard Vectors
160

Diagnostic Programs
Refer to Appendix A.

384

M8013/14
1

r--A--, ,
15

I I I I
1

ADDRESS SWITCH

I I I I I
0

1 = SWITCH ON
0= SWITCH OFF

Address Selection

0
,~

15
NOT USED

I I
0

I I I Io I
HARDWIRED

VECTOR SWITCH
N

SWITCH POSITION
N =ON
F = OFF

Vector Selection

Related Documentation
RL V 11 Controller Technical Description Manual (EK-RL V 11-TO)
RL V 11 Field Maintenance Print Set (MP00635)
RL01 Field Maintenance Print Set (MP00347)
RL02 Field Maintenance Print Set (MP00553)
RLO 1 Disk Drive IPB (EK-ORLO 1-IP)
RL02 Disk Drive IPB (EK-ORL02-IP)
RL01jRL02 User's Guide (EK-RL012-UG)
RLO 1jRL02 Pocket Service Guide (EK-RLO 12-PG)
Microcomputer Interfaces Handbook (EB-20 175-20)

NOTE
The M8013 must be installed above the M8014. The RLV11
controllers can only be used in a backplane built as an H9273
(slots A and B = LSI bus and slots C and D = interboard bus).
The BA 11-N box currently. is the only box that contains an
H9273 backplane.

385

M8013/14

BC06R CABLE

RED STRIPE

W2
CABLE CONNECTOR
TO DRIVE

rn vco

POT 15 KI

GND TP

0 VCI TP

o VCO TP

COMPONENT SIDE 1
RLV11 DRIVE BOARD MB013
JUMPERS W2 & W4 IN PLACE FOR E PROM USE
JUMPERS W1 & W3 IN PLACE FOR MASKED ROM USE

R~~D 0 Q
OR

EPROM

o
DV1

DA1

A
CY1

CA1

BY1

BA1

NOTE
JUMPERS ARE O-OHM COMPOSITION RESISTORS

RL V 11 Drive Module (M80 13)

386

AY1

AA1

M8013/14

COMPONENT SIDE 1
RLV11 BUS INTERFACE BOARD M8014

MSBI
BUS ADDRESS SWITCH
LSB

MSB~ VECTOR SWITCH
LSB

DAl

DYl

CYl

CAl

BYl

BAl

AYl

AAl

RLV 11 Bus Interface Module (M80 14)

CONTROL STATUS REGISTER (CSR)

774400

HCRC

~----R-EA~D~O~N-Ly----~A~------R-E-AD~ffl~R-'T-E-------~
ONLY

Control Status Register

387

M8013/14
CSR Bit Definitions
Bit

Function

Drive Ready (DRDY) - When set, this bit indicates that the selected drive is ready to receive a command (no seek operation
in progress). The bit is cleared when a seek operation is initiated and set when the seek operation is completed.

1-3

Function Code - These bits are set by software to indicate the
command to be executed.

F2 F1

FO Command

WRITE CHECK

0
0

MAINTENANCE MODE

Octal Code

0
0

GET STATUS

SEEK

READ HEADER

WRITE DATA

READ DATA

READ DATA WITHOUT
HEADER CHECK

Command execution starts when CRDY (bit 7) of the CSR is
cleared by software. In a sense, bit 7 can be considered a negative go bit.
4-5

Bus Address Extension Bits (BA 15, BA 17) - Two most significant bus address bits. Read and written as bits 4 and 5 of the
CSR, they function as address bits 16 and 17 of the BAR.

Interrupt Enable (IE) - When this bit is set by software, the controller is allowed to interrupt the processor at the assertion of
CRDY. This occurs at the normal or error termination of a command. Once an interrupt request is posted on the LSI bus, it is
not removed until serviced even if IE is cleared.

388

M8013/14
CSR Bit Definitions (Cont)
Bit

Function

Controller Ready (CRDY) - When cleared by software, this bit
indicates that the command in bits 1-3 is to be executed. Software cannot set this bit because no registers are accessible
while CRDY is O. When set, this bit indicates that the controller
is ready to accept another command.

8-9

Drive Select (DSO, DS1) - These bits determine which drive will
communicate with the controller via the drive bus.

Operation Incomplete (OP!) - When set, this bit indicates that
the current command was not completed within the OPI timer
period.

Data CRC (OCR C) or Header CRC (HCRC) or Write Check
(WCE) - If OPI (bit 10) is cleared and bit 11 is set, the CRC error
occurred on the data (DCRC). If OPI (bit 10) is set and bit 11 is
also set, the CRC error occurred on the header (HCRC).
If OPI (bit 10) is cleared and bit 11 is set and the function command was a write check, a write check error (WCE) has occurred.
NOTE
Cyclic redundancy checking is done only on the desired header. It is performed on the first and second header words, even
though the second header word is always O.

Data Late (DL T) or Header Not Found (HNF Error) - When OPI
(bit 10) is cleared and bit 12 is set, it indicates that a data late
condition occurred on a read without header check operation.
One of two conditions exists:
Write Operation - The silo is empty, but the word count has not
reached zero. (Bus request was ignored for too long.)
Read Operation - The silo is full (word being read could not enter the silo and the bus request was ignored too long.)
When OPI (bit 10) is set and bit 12 is also set, it indicates that a
timeout occurred while the controller was searching for the correct sector to read or write (no header; compare [NHFJ).

389

M8013/14
eSR Bit Definitions (Cont)
Bit

Function
Error Summary
Error

Bit 12

Bit 11

Bit 10 Comments

OPI
DCRC
WCE

0
0
0

0
1
1

1
0
0

HCRC
DLT
HNF

0
1
1

1
0
0

1
0
1

200 ms timeout
Function command is a write
check.

Nonexistent Memory (NXM) - When set, this bit indicates that
during a DMA data transfer, the memory location addressed did
not respond within 14 ms.

Drive Error (DE) - This bit is buffered from the drive error interface line. When set, it indicates that the selected drive has
flagged an error, the source of which can be determined by executing a GET STATUS command.
To clear the drive error bit, execute a GET STATUS command
with bit 3 of the DAR.

Composite Error (ERR) - When set, this bit indicates that one or
more of the error bits (bits 10-14) is set. When an error occurs,
the current operation terminates and an interrupt routine is initiated if the interrupt enable bit (bit 6 of the CSR) is set.
BUS ADDRESS REGISTER (BAR)

774402

BA14

BA12

BA1D
READIWRITE

Bus Address Register
BAR Bit Definitions
The Bus Address Register (BAR) is a 16-bit word-addressable register with
an address of 774 402. Bits 0 through 15 can be read or written; bit 0
should normally be written O. Expansion bits 16 and 17 are programmable
via bits 4 and 5 of the GSA.
390

M8013/14
The bus address register indicates the memory location involved in the
DMA data transfer during a read or write operation. The contents of the
BAR are automatically incremented by 2 as each word is transferred between system memory and controller in either direction. Clear the BAR by
executing a BUS INIT.
Disk Address Register (DAR)
The Disk Address Register (DAR) is a 16-bit read/write word-addressable
register with an address of 774 404. Its contents can have one of three
meanings, depending on the function being performed. Clear this register
by executing a BUS INIT.
DAR During a SEEK Command - To perform a seek function, it is necessary to provide address difference, head select, and head directional information to the selected drive.
DAR DURING SEEK COMMAND
15

DAR SEEK Command
Bit Definitions
Bits

Function

Marker (MRKR) - Must be a 1.
Must be a 0, indicating to the drive that a SEEK command is
being requested and that the remaining bits in the register will
contain the seek specifications.

Direction (DIR) - This bit indicates the direction in which a seek
is to take place. When the bit is set, the heads move toward the
spindle (to a higher cylinder address). When the bit is cleared,
the heads move away from the spindle (to a lower cylinder address). The actual distance moved depends on the cylinder address difference (bits 7 -14).

Must be a O.

Head Select (HS) - Indicates which head (disk surface) is to be
selected. Set = lower; clear = upper.

5-6

Reserved.

7 - 14

Cylinder Address Difference (OF <8:0» - Indicates the number
of cylinders the heads are to move on a seek.

Must be a O.
391

M8013/14
DAR During READ or WRITE DATA Command - For a read, write, or write
check operation, the DAR is loaded with the address of the first sector to
be transferred. Thereafter, as each adjoining sector is transferred, the DAR
is automatically incremented by 1. If the DAR increments to the nonexistent
sector address 50 s, an OPI timeout will occur. The drive must then seek to
a new track if the transfer is to continue.

DAR DURING READING OR WRITING DATA COMMANDS
15

DAR READ/WRITE DATA Command

Bit Definitions
Bit

Function

0-5

Sector Address (SA<5:0» - Address of one of the 40 sectors
on a track. (Octal range is 0 to 47.)

Head Select (HS) - Indicates which head (disk surface) is to be
selected. Set = lower; clear = upper.

7-14

Cylinder Address (CA<8:0» - Address of one of the 256 cylinders. (Octal range is 0 to 377.)

Must be a o.

DAR During a GET STATUS Command - After the GET STATUS command
is deposited in the CSR, it is the DAR's responsibility to get the command
transferred to the drive. Therefore, the DAR must also be programmed
along with the CSR to do the GET STATUS command.

DAR DURING GET STATUS COMMAND
15
7744041

RST

I x I x Ix Ix I x Ix Ix I I I I I I I I I
DAR GET STATUS Command

392

M8013/14
For a GET STATUS command, the DAR register bits must be programmed
as follows.
DAR Register Bits for a GET STATUS Command
Bit

Function

Marker (MRKR) - Must be a 1.
Get Status (GS) - Must be a 1, indicating to the drive that its
status word is being requested. At the completion of the GET
STATUS command, the drive status word is read into the controller multipurpose (MP) register (output stage of FIFO). With
this bit set, bits 8-15 are ignored by the drive.

Must be a O.

Reset (RST) - When this bit is set, the drive clears its error register of soft errors before sending a status word to the controller.

4-7

Must be a O.

8-15

Not used.

Multipurpose Register (MPR)
The MPR is two registers bearing the same base address. When writing
into that location, the word counter accepts the data. When reading from
that location, the FIFO output buffer provides the data.

MPR AFTER GET STATUS COMMAND

774406
SKTO

MPR Status Word

MPR After a GET STATUS Command - When a GET STATUS command is
executed and a status word is returned to the controller, the contents of
the MPR (FIFO output stage) are defined as follows.

393

M8013/14
Bits 0-2 - State<C:A) CST <C:A» - These bits define the state of the
drive.
Bits

Definition

a
a

a
1
a
1
a

a
a

Load Cartridge
Spin Up
Brush Cycle
Load Heads
Seek Track Counting
Seek Linear Mode (Lock On)
Unload Heads
Spin Down

Bit Definitions
Bit

Function

Brush Home (BH) - Asserted when the brushes are not over the
disk.

Heads Out (HO) - Asserted when the heads are over the disk.

Cover Open (CO) - Asserted when the cover is open or the dust
cover is not in place.

Head Select (HS) - Indicates the currently selected head.

Drive Type (DT) - Set =
clear = RLa 1.

Drive Select Error (DSE) - Indicates that multiple drive selection was detected.

Volume Check (VC) - vc is set every time the drive goes into
load heads state. This asserts a drive error at the controller but
not on the front panel. VC is an indication that the program does
not really know which disk is present until it has read the serial
number and bad sector file. (The disk might have been changed
while the heads were unloaded.)

Write Gate Error (WGE) - Indicates that the drive sensed that
write gate was asserted when sector pulse was asserted, or
write gate was set with the drive not ready, or the drive was
write locked.

lower; clear =

394

upper. Set

RLa2;

M8013/14
Bit Definitions (Cont)
Bit

Function

Spin Error (SPE) - Indicates that the spindle did not reach
speed in the required time; or indicates over speeding.

Seek Time Out (SKTO) - Indicates that the heads did not come
on track in the required time during a SEEK command or loss of
"ready to read/write during lock on" mode.

Write Lock (WL) - Indicates write lock status of selected drive.
Set = write protected.

Head Current Error (HCE) - Indicates that write current was detected in the heads when write gate was not asserted.

Write Data Error (WOE) - Indicates that write gate was asserted
but no transitions were detected on the write data line.
MPR DURING READ HEADER COMMAND

WcfRD

I I I I I I I I I I I I I I I I I
0

3RD

WORD~~~-r~-L~~~~-.~-L~-.~~.-~-L~~
CRC14

CRC12

CRC10

CRC4

CRCO

MPR Three Header Words

MPR After a Read Header Command - When a READ HEADER command
is executed, three words will be stored in the multipurpose register (FIFO
output buffer). The first header word will contain sector address (SAO:SA5),
head select (HS - set = lower; clear = upper), and cylinder address information (CAO:CA8). The second word will contain all Os. The third word will
contain the header CRC information. All three words are readable by the
main program.

395

M8013/14
MPR DURING READ/WRITE COMMANDS FOR WORD COUNT
15 14 13 12
11
10 09 08 07 06 05 04 03 02

774406

we11

MPR Used As Word Counter
Bit Definitions
Bit

Function

0-12

Word Count (WC< 12:0» - 2's complement of total number of
words to be transferred.

13-15

Must be a 1 for word count in correct range.

MPR During READ/WRITE DATA Commands - When transferring data via
DMA, the MPR functions as a word counter and is loaded by program with
the 2's complement of the number of words to be transferred. It is then incremented by 1 by the controller as each word is transferred. The reading
or writing operation generally is terminated when the word counter overflows. The word counter can keep track of from one data word to the full 40sector count of 5120 data words (decimal). The maximum number of words
that can be transferred in a single operation is limited by the number of sectors available to be written in the track.

NOTE
The RL01/RL02 disk drive will not do spiral read/writes_ If
data is to be transferred past the end of the last sector of a
track, it is necessary to break up the operation into the following steps.
1.

Program the data transfer to terminate at the end of the
last sector of the track.

Program a seek to the next track. This can be accomplished either by a head switch to the other surface but
the same cylinder, or a head switch to move to the next
cylinder.

Program the data transfer to continue at the start of the
first sector on the next track.

396

M8016

M8016
KPV11-A (M8016) POWER FAIL/LINE TIME CLOCK
KPV11-B (M8016-YB) KPV11-A + 120 Q TERMINATOR
KPV11-C (M8016-YC) KPV11-A + 250 Q TERMINATOR

Amps 24 V

Bus Loads

Cables

+5
+12
0.11
0.82

AC
1.6

70-12754 (for remote operation)

DC
1.0

Standard Address
LKS

177546

Standard Vector
LTC

100

Diagnostic Programs
Refer to Appendix A.

Related Documentation
Field Maintenance Print Set (MP00356)
Microcomputer Interfaces Handbook (EB-20 175-20)

Options to KPV11
DEC PN

Description

54-11808
70-11656
70-08612

Console panel printed circuit board assembly
Console bezel (dress panel)
Console signal/power cable (required for optional console
panel use)

397

M8016

EX CL
REM DC

+ t2V

o
W14

+5V

GND

W12

W13

R54**
W15

Wll

E12

~--+--+--+- E3

(KPV1-1-B,
KPV11-C
ONLY) [ E17

(KPV11-B
KPV11-C
ONLY)

. ; MAY USE 4-40 HARDWARE
•• = Remoye for 50 Hz operol ion
11-4836

398

M8016
KPV11 Factory Jumper Configuration
Jumper
Designation

Jumper
State

Function
Implemented

W1
W2
W3
W4
W5
W6
W7
W8
W9
W10

I
I
I
I
I
R
I
I
R
R

Sets address of line time clock status register
(lKS) to 177546.

W11

W12

Do not change. Must be installed for proper terminator function on KPV 11-8 and KPV 11-C.

Disables continuous or manual control of l TC interrupt request operation. Do not install when
W 13 is installed.

W13

l TC interrupt requests can be enabled and disabled by program. Do not install when W 12 is installed.

W14

Console (optional) l TC ON/OFF switch enabled.

W15

l TC signal occurs at the power line frequency.

399

M8016
NOTES
1.

Line Time Clock (LTC) controls
Function

W12

W13

disable LTC
enable LTC and enable LTC program control
enable LTC and disable LTC program control

I
R
R

R
I
R

LTC Remote Console Switch
Function

W14

console switch enabled
console switch disabled

I
R

Select LTC Frequency
Function

W15

LTC signal occurs at line frequency
LTC signal occurs at frequency inserted at
EXT TIME REF

I
R

External Transformer
The user must supply a 24 Vac, 200 mA center tapped
transformer to be connected to the two ac and the ground
tabs on the top of the module. If a transformer capable of
supplying more than 200 mA is used, current limiting in the
form of a fuse must be used to protect the KPV11-A module.

LKS (177546)
IS

BIT

1· ENABLE
O'DISABLE
(READ/ WRITE BIT)
MONITOR
SET TO "1" BY LINE FREQUENCY CLOCK
SIGNAL. CLEARED BY PROGRAM.
(READ/WRITE [CLEAR-ONLY] BIT)

Line Time Clock Status Register (lKS)

400

M8016

115vac.60HZ
} TO SYSTEM POWER
SUPPLY AND FANS

~-,-------------'GND

TO KPV11
24Vac INPUT
TERMINALS

*
GND------------------~.-~

(A) 115V CONNECTIONS (TYPICAL)

230Vac.50Hz
} TO SYSTEM POWER
SUPPLY AND FANS

r-----~nJ~----... AC

~-,-----------"'GND

~4_--~~------...

TO KPVll
24Vac INPUT
TERMINALS

GND-------------------L~~

(8) 230V CONNECTIONS (TYPICAL)

* 1 AMP FAST BLOW FUSES ARE RECOMMENDED
ON THE AC INPUT LINES TO PROVIDE ADEQUATE
PROTECTION TO THE KPVll.
11- 4839

Power Line Monitor Transformer Installation

401

M8017

M8017
DLV11-E ASYNCHRONOUS SERIAL LINE INTERFACE

Amps

+ 12

t5
1.0

0.15
(0.20 max.)

Bus Loads

Cables

AC
1.26

BC05C

Standard Address
RCSR
RBUF
XCSR
XBUF

175610
175612
175614
175616

NOTE
The DLV11-E is shipped configured for use with a modem.

Standard Vectors
Floating - Configurable within the range of 000-770. Refer to Appendix B.

MINC/DECLAB
Receiver Interrupt
Transmitter Interrupt

300
304

330
334

Diagnostic Programs
Refer to Appendix A.

Related Documentation
DL Vll-E and DLVll-F Asynchronous Line Interface User's Manual
(EK-DL V 11-0P)
Field Maintenance Print Set (MP00460)
Microcomputer Interfaces Handbook (EB-20175-20)
402

M8017

MN ... OMN ... O

1-1-1-1-0:0:0:0:

1'~11111

-Foll-FR
C1
Ml

IBG

---PB
OO,...~lt)-.:tM

»»»

IIIIII
IIIIIIIIII
N ... OcnOO,...~lt)"'M
:(::(::(c:(c:(c:(c(c(c(c(

1f
cs-

403

M8017
BDAL
08

5
BITS , ' ,

I 1 I

BBS7 L

., ell

;;;:

o • CSR

1 • DATA BUFFER

}

o , LOW BYTE} _ _ _ _- '
1 • HIGH BYTE

RANGE' 1600008 - 1777768

DL V 11-E Addresses

I I I I I I L

SELECTED BY USER.
ASSERTED L~~lbNlIWtu~~T '-\~_ _~
__
~_-.:~_---=-~_...:..-~
VECTOR JUMPERS,
INSTALLED' ,
REMOVED' 0

O· RECEIVER
, • TRANSMITTER

CONTROLLED BY INTERRUPT
LOGIC CIRCUIT.
RANGE' 0 - 7748

DLV 11-E Interrupt Vectors

Unit

Address Jumpers

Address

A3 A4 A5 A6 A7 A8 A9 A10A11 A12
Console
First Option
Second Option
Third Option
Modem

177560
176500
176510
176520
175610

R
R

R
R
R
R

404

I
I
I
I

R
R
R
R

R
R
R

I
I
I
I

M8017
Unit

Vector

Vector Jumpers
V3 V4 V5 V6 V7

Console
60
First Option
300
Second Option 310
Third Option
320
Modem
300

R
R
I
R
R

I
R
R
I
R

I
R
R
R
R

R
I
I
I
I

I
I
I
I

R
R
R
R

Jumper Configuration When Shipped
Jumper
Designation

Jumper
State
Function Implemented

A3
A4
A5
A6
A7
A8
A9
A10
A 11
A12

I
R
R
R
I
I
I
R
I
I

Jumpers A3 through A 12 implemented device address 17561 X. The least significant octal digit is
hardwired on the module to address the four device
registers as follows.

V3
V4
V5
V6
V7
V8

R
R
R
I
I
R

This jumper selection implements interrupt vector
address 300 for receiver interrupts and 304 for
transmitter interrupts.

RO
R1
R2
R3

I
R
I
I

The module is configured to receive at 100 baud
(see "Baud Rate Selection" table, which follows).

TO
T1
T2
T3

I
R
R
R

The transmitter is configured for 9600 baud if split
slPeed operation is used.

x = 0 RCSR
X = 2 RBUF
X = 4 XCSR
X = 6 XBUF

Break generation is enabled.

405

M80l7
Jumper Configuration When Shipped (Cont)
Jumper
Designation

Jumper
State
Function Implemented

Parity bit is disabled.

Parity type is not applicable when P is removed.

R
R

Operation with eight data bits per character (see
"Data Bit Selection" table, which follows).

Programmable baud rate function disabled.

C
C1

Programmable baud rate function disabled.
Common speed operation enabled.

S
S1

R
R

Split speed operation disabled.

Halt on framing error disabled.

R
I

Boot on framing error disabled.

-B
-FD

The DATA TERMINAL READY signal is not
forced continuously true.

-FR

The REQUEST TO SEND signal is not forced continuously true.

The circuitry controlling the REQUEST TO SEND
signal is enabled.

The FORCE BUSY signal is disabled.

M
M1

R
R

Factory test jumpers. Not defined for field use.

406

M8017
Baud Rate Selection

Program Control
Receive Jumpers
Transmit Jumpers

Bit

15
R3
T3
I
I
I
I
I
I
I
I
R
R
R
R
R
R
R

14
R2
T2
I
I
I
I
R
R
R
R
I
I
I
I
R
R
R

13
R1
T1
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R

12
RO
TO
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I

11 *

Baud
Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600

I = jumper inserted = program bit cleared.
R = jumper removed = program bit set.
*Bit 11 of the XCSR (write-only bit) must be set in order to select a new
baud rate under program control. Jumper PB must be inserted to enable
baud rate selection under program control.
Data Bit Selection
Jumpers

Number of Data Bits

2
I
I
R
R

I
R
I
R

5
6
7
8

407

M8017
Jumper Definitions
Jumper

Function

A3- A 12

These jumpers correspond to bits 3-12 of the address word.
When inserted, they will cause the bus interface to check for a
true condition on the corresponding address bit.

V3- V8

Used to generate the vector during an interrupt transaction.
Each inserted jumper will assert the corresponding address bit
on the LSI-11 bus.

RO-R3

Receiver and transmitter baud rate jumpers selected during
common speed operation.
Receiver-only baud rate select jumpers used during split speed
operation.

TO-T3

Transmitter baud rate select jumpers used during split speed
operation.
Both receiver and transmitter baud rates used if maintenance
mode is entered during split speed operation.

Jumper is inserted to enable break generation.

Jumper is inserted for operation with parity.

Removed for even parity; inserted for odd parity. Receive
checks for appropriate parity and transmitter inserts appropriate parity.

1, 2

These jumpers select the desired number of data bits.

Jumper is inserted to enable the programmable baud rate capability.

C, C1

These jumpers are inserted for common speed operation. (Note
that Sand S 1 must be removed when C and C 1 are inserted.)

408

M8017
Jumper Definitions (Cont)
Jumper

Function

S, S 1

Inserted for split speed operation. (Note that C and C 1 must be
removed when Sand S 1 are inserted.)

This jumper is inserted to assert BHAL T L when a framing error
is received, except when the maintenance bit is set. This places
the LSI-11 in the halt mode.

B, -B

Jumper B is inserted to negate BDCOK H when a BREAK signal
or framing error is received, except when the maintenance bit is
set. This causes the LSI-11 to reload the bootstrap. (Jumper -B
must be removed when B is inserted.)

-FD

Jumper is removed to force DATA TERMINAL READY signal on.

-FR

Jumper is removed to force REQUEST TO SEND signal on.

This jumper is inserted to enable normal transmission of the
REQUEST TO SEND signal.

Inserted to enable transmission of the FORCE BUSY signal (for
Bell model 103E data sets).

M, M 1

These are test jumpers used during the manufacturing of the
module. They are not defined for field use.

409

M8017

DLV11-E RCSR Bit Assignments
Bit

Function

DATA SET INT (Data Set Interrupt) - This bit initiates an interrupt sequence, provided that the DATA SET IN ENB, bit (05) is
also set.
This bit is set whenever CAR DET, CLR TO SEND, or SEC REC
changes state; i.e., on a 0-to-1 or 1-to-0 transition of anyone of
these bits. It is also set when ring changes from 0 to 1.
Cleared by INIT or by reading the RCSR. Because reading the
register clears the bit, it is, in effect, a "read-once" bit.

Ring - When set, indicates that a RINGING signal is being received from the dataset. Note that the RINGING signal is not a
level but an EIA control with the cycle time as shown below.
Read only.

MR-0954

CLR TO SEND (Clear to Send) - The state of this bit is dependent on the state of the CLEAR TO SEND signal from the data
set. When set, this bit indicates an ON condition; when clear, it
indicates an OFF condition. Read only.

CAR DET (Carrier Detect) - This bit is set when the data carrier
is received. When clear, it indicates either the end of the current transmission activity or an error condition. Read only.

RCVR ACT (Receiver Active) - When set, this bit indicates that
the DLV 11-E's receiver is active. The bit is set at the center of
the START bit, which is the beginning of the input serial data
from the device, and is cleared by the leading edge of R DONE
H.
Read-only bit; cleared by INIT or by R DONE H (bit 07).
410

M8017
DLV11-E RCSR Bit Assignments (Cont)
Bit

Function

SEC REC (Secondary Received or Supervisory Received Data)
- This bit provides a receive capability for the reverse channel
of a remote station. A space (+ 10 V) is read as a 1. (A transmit
capability is provided by bit 03.) Read only.

9-8

Not used. Reserved for future use.

RCVR DONE (Receiver Done) - This bit is set when an entire
character has been received and is ready for transfer to the LSI11. When set, initiates an interrupt sequence, provided that
RCVR INT ENB (bit 06) is also set.
Cleared whenever the receiver buffer (RBUF) is addressed. Also
cleared by INIT. Read only.

RCVR INT ENB (Receiver Interrupt Enable) - When set, allows
an interrupt sequence to start when RCVR DONE (bit 07) sets.

DSET INT ENB (Data Set Interrupt Enable) - When set, allows an
interrupt sequence to start when DATA SET INT (bit 15) sets.

Not used. Reserved for future use.

SEC XMIT (Secondary Transmitted or Supervisory Transmitted
Data) - This bit provides a transmit capability for a reverse
channel of a remote station. When set, transmits a space (+ 10
V). (A receive capability is provided by bit 10.) Read/write bit;
cleared by INIT.

REO TO SEND - A control lead to the data set which is required
for transmission. Ajumper on the DL V 11-E ties this bit to REO
TO SEND or FORCE BUSY in the data set. Read/write bit;
cleared by INIT.

DTR (Data Terminal Ready) - A control lead for the data set
communication channel. When set,permits connection to the
channel. When clear, disconnects the interface from the channel. Read/write bit; must be cleared by the program, not by INIT.
The state of this bit is not defined after power-up.

Not used. Reserved for future use.

411

M8017
14

RESERVED

RECEIVED DATA SITS

DLV11-E RBUF Bit Assignments
Bit

Function

Error - Used to indicate that an error condition is present. This
bit is the logical OR of OR ERR, FR ERR, and P ERR (bits 14, 13,
and 12, respectively). Whenever one of these bits is set, it
causes the error bit to set. This bit is not connected to the interrupt logic. Read-only bit; cleared by removing the error-producing condition.

NOTE
Error indications remain present until the next character is received, at which time the error bits are updated. INIT clears the
error bits.
14

OR ERR (Overrun Error) - When set, indicates that reading of
the previously received character was not completed (RCVR
DONE not cleared) prior to receiving a new character. Read
only; cleared by INIT.

FR ERR (Framing Error) - When set, indicates that the character that was read had no valid stop bit.

P ERR (Parity Error) - When set, indicates that the parity received does not agree with the expected parity. This bit is always 0 if no parity is selected. Read-only bit; cleared by INIT.

11-08

Not used. Reserved for future use.

07-00

Received Data Bits - Holds the character just read. If fewer than
eight bits are selected, then the buffer is right-justified into the
least significant bit positions. In this case, the higher unused bit
or bits are read as Os. Read-only bits; not cleared by INIT.

DL V 11-E XCSR Bit Assignments
412

M8017
DLV11-E XCSR Bit Assignments
Bit

Function

15-12

PBR SEL (Programmable Baud Rate Select) - When set, these
bits choose a baud rate from 50-9600 baud. Write only.

PBR ENB (Programmable Baud Rate Enable) - This bit must be
set in order to select a new baud rate indicated by bits 12 to 15.

10-08

Not used. Reserved for future use.

XMIT ROY (Transmitter Ready) - This bit is set when the transmitter buffer (XBUF) can accept another character. When set, it
initiates an interrupt sequence provided XMIT INT ENB (bit 06) is
also set. Read-only bit; set by INIT.

XMIT INT ENB (Transmitter Interrupt Enable) - When set, allows
an interrupt sequence to start when XMIT ROY (bit 07) is set.
Read/write bits; cleared by INIT.

05-03

Not used. Reserved for future use.

MAINT Used for maintenance function. When set, connects the
transmitter serial output to the receiver serial input while disconnecting the external device from the receiver serial input. It
also forces the receiver to run at transmitter baud rate speed
when split speed operation is enabled. Read/write bit; cleared
by INIT.

Not used. Reserved for future use.

Break - When set, transmits a continuous space to the external
device. Read/write bit; cleared by INIT.
08

00
TRANSMITTER DATA BUFFER

RESERVED

DLV11-E XBUF Bit Assignments
Bit

Function

15-08

Not used or defined. Not necessarily read as Os.

07-00

Transmitter Data Buffer - Holds the character to be transferred
to the external device. If fewer than eight bits are used, the
character must be loaded so that it is right-justified in the least
significant bits. Write-only bits; not necessarily read as Os.

413

M8017
Maintenance Aids
The DL V 11 is sh ipped with an H315 modem test connector. This is plugged
into the interface cable in place of a data set when maintenance programs
are running.

Maintenance Mode Logic
In the maintenance mode, the DLV11-E and DLV11-F modules route their
output data back to their input. To accomplish this, the computer program
sets the maintenance bit in the XCSR. The latch holding this bit has two
outputs. One goes to the break logic to prevent the generation of framing
error signals during operation in the maintenance mode. The other output
is applied to the maintenance mode data selector. The data selector normally routes the incoming data from the peripheral interface to the RBUF. In
the maintenance mode, however, it switches its input to the output of the
XBUF. This action loops the serial data out of the XBUF back into the RBUF
and disconnects the peripheral interface's data. While in the maintenance
mode, the serial output of the XBUF continues to go to the peripheral interface and out to the peripheral device.

MAINTENANCE MODE
DATA SELECTOR

~--t-"'S:=-ER,-,-,I.::..:.A=-L..:.;;IN:....:..:...H-..t RBUF

MAINT H

DAT02 H
XCSR
BIT 2

CO~~20L

MAINT L

LOGIC

Maintenance Mode Logic

414

M8018

M8018
KUV11-AA WRITABLE CONTROL STORE

Amps
+5
3

+ 12

Bus Loads

Cables

AC
1.4

17 -00124-00
17 -00124-01 (maintenance)

Standard Addresses
CSR and RAM Address
DATA I/O, bits 0-15
DATA I/O, bits 16-21

177540
177542
177544

Standard Vectors
None

Diagnostic Program
Refer to Appendix A.

Related Documentation
LSI-tt WCS User's Guide (EK-KUV11-TM)
KD 11-WA Maintenance Print Set (MP00571-00)

NOTES
1.

An M8018 can only be used with an M7264-YC LSI-11 processor.

To extend the M8018, the maintenance cable is required
(17-00124-01 ).

415

M8018
Switch Configurations
The range of microcode addresses to which the WCS will respond on the
microinstruction bus (MIS) (when the CSR enable bit is a 1) is determined
by an 8-wide DIP switch (SW 1) on the M8018 module.
Set switches S 1 through S7 (S8 is not used) on SW 1 as shown in the
"WCS Address Mode Switch Settings" table to select one of the four
modes of operation described below.

Mode I - The microcode is loaded from the LSI-11 bus into WCS RAM locations 0 to 1777. The WCS correspondingly responds to microaddresses
2000 to 3777 on the MIS.
Mode II - The microcode is loaded from the LSI-11 bus into WCS RAM locations 0 to 1777. The WCS initially responds to MIS microaddresses 3000
to 3777 from the first 512 words of RAM. If bits 21-18 of the microinstruction are coded to a 7 (octal) then the next microinstruction will be
accessed from the second 512 words of RAM. A second 7 (octal) will
toggle back to the first 512 words of RAM. This swapping between 512
word blocks for the same microaddress range is called "paging" and allows 1024 words of microcode to be implemented when only 512 microaddresses are available.
Mode III - This mode is the same as Mode I except that the two blocks of
512 words of RAM have been interchanged on the module. Addressing is
identical to that of Mode I.
Mode IV - The microcode is loaded from the LSI-11 bus into WCS RAM
locations 0 to 1777. The WCS correspondingly responds to MIS microaddresses 0 to 1777. This microaddress space is identical to MICROMs 0
and 1, which contain the base PDP-11 microcode for the LSI-11.

5WITCH 5W1

MODE
51

OFF

III

OFF

WCS Address Mode Switch Settings

416

M8018

B
wJ

B
S6
S7
S8

Address Mode Switch Location

MODELS
ITEM
KUV11-UH

KD11-WA

11/03-WC

11/03-WD

KD11-H CPU

M8018 WCS MODU LE

WCS CABLE
Part NO 17-00124-00

BDV11-AA BOOT
MODULE

BA11-NC BOX (115 V)

KD11-R CPU
(Includes MSV11-CD
memory)

BAll-ND BOX (230V)

Items Supplied Per Configuration

417

M8018
M7264

WCS to CPU Installation
LSI-11 Bus Address Decode and Control
This logic does the LSI-11 bus interface, and responds to four device addresses which have the following meanings.
LSI-11 Address

Meaning

177540

Control/status register and RAM address.

177542

Data input/output for RAM data word bits 0-15, or output for trace stack.

177544

Data input/output for RAM data word bits 16-21 and
data input/output for two user bits.

177546

Unused (but still responds) A DIN will read all Os.

NOTE
The address 177546 is the same address normally assigned to
the KW 11-L clock status register.
Read Back MUX
The read back MUX selects the source of the data to be output to the LSI11 bus at the proper time during an LSI-11 DATAl bus cycle.

Control Status Register
The CSR consists of five control/status bits and a RAM address register.
The control/status bits are described below.
418

M8018
eSR Bit

Definition

When this bit is asserted, it resets the WCS module, in
particular, the trace feature.

14, 13, 11

These bits control the trace mode of the WCS.

When this bit (the enable bit) is asserted, the WCS is
enabled to respond to the MIB. When it is disabled, the
WCS cannot respond to the MIB.

After the enable bit is disabled in the CSR, the RAM can be accessed by
writing an address (with enable bit = 0) to the CSR address. Then the
lower 16 bits at that address of RAM (microcode bits 0-15) can be accessed (read or write) at the second device address, and the upper eight
bits at the same address of RAM (the two user bits and microcode bits
16- 21) can be accessed (read or write) at the third device address.

177540
READIWRITE

TRACE
MODE
RESET

ENABLE
BIT

EXAMINE

UNUSED

RAM ADDRESS REGISTER

UNDEFINED
ENABLE (ALWAYS~O)

Control/Status and RAM Address Register

MICROCODE LOW WORD

RAM Data Input/Output
177542
R EADIWR ITE IF
177540 BIT 14 = 1 1-.._L---L_--I..._...l.-.,...-L----L_--L.._...J...._.l....-----IL---L_....L._...l.-_L----L_-l

WCS OUTPUT CYCLE
0= OUTPUT DISABLED
1 = OUTPUT ENABLED

Output for Trace Stack
177544
READIWRITE

USER BIT AND TRACE STOP

RAM Data Input/Output, User Bits Data Input/Output
LSI-11 Bit Assignments
419

M8021

M8021
MRV11-BA UV PROM-RAM

Amps

Cables

Bus Loads

+ 12

W/O PROM

0.58
(0.67 max.)

0.34

2.8
1.0
(0.41 max.)

With
PROMs

0.62
(0.744 max.)

0.5

DC
None

(0.6 max.)

Standard Addresses
RAMs
PROMs

20000-20777
140000-157777

Standard Vectors
None

Diagnostic Programs
Refer to Appendix A.

Related Documentation

MRV11-BA LSI-11 UV PROM-RAM User's Manual (EK-MRV11-TM)
Field Maintenance Print Set (MP00354)
Microcomputer Processor Handbook (EB-18451-20)

Recommended PROM Types
DEC MRV 11-BC Intel 2708
(DEC PN 23-00087-01)

1024 X 8-bit, MOS, tri-state, erasable
ultraviolet (24-pin DIP)
420

M8021

HIGH BYTE
PROMS

~~~SYTE - +

1ST 1K
PROMS

3RD lK
PROMS

2ND 1K
PROMS

o 4TH 1K
PROMS

o[JG[J 0
oGG[J
o-c:::l-O W22

o-c:::J-O W20 } RAM ADDRESS

oc:::J-O W19

o-c:::ro W18 BANK 7 ENABLE

PROM
{o-e::J-o W17
ADDRESS
o-e::J-oW16

:~~:LE{§En
o-e::::ro
W 11

";;:~~L{E

!mg'
o-c::::ro W5

~W4

o-c::roW3
PROM
{ o-e::::k> W2
ADDRESS o-c:J-o W1

o-c::J-o W21

MRV 11-BA RAM Addressing

421

M8021

JUMPER_ WJ

W,9

W20

!!! !!!!!!
CONF;~~:::~:~-{~ i !!! l! l!
FACTORY

CIRCUITS
1256,01377

BYTE POINTER
IDATOB BUS CYCLES ONLYI
0= WRITE LOW BYTE (0,7 )

4K AND lK
SELECT

}

, = WRITE HIGH
DECODED BY ADDRESSING
AND CONTROL LOGIC

R· ,

a l WORDSI

256WORD
SELECT
R=O

1. Factory configured address range"" 20000 - 20377
2. I ::II Jumper installed; A '" Jumper removed
3. Wl0 removed'" RAM ENABLE

Wl0 Installed'" RAM DISABLE

MRV 11-BA RAM Addressing

81 TS

O_2 -,-_O'--r_O_O..,
_~';...7...,.....~~'.:,.5-,-_-r-'...;;.J-,-_'.:,.2..,--,11-r-,-,--,-...;.09'--r_-r_O_7..,-.....
06'--r....;.;;..-,-...;;.04---,_0...,;3-r_

-l I I I I
111 11
l l ! l l
~~,""" {~ ill
:g~~!~S

'---r--"

JUMPER _

W,5

iACTORY
CONFIGURATION -

W17

W'6

•

OECODED BY PROM
INTEGRATED CIRCUITS

PROM SIZE 11K WITHIN 4K BANKI
DECODED BY ADDRESSING AND
CONTROL LOGIC.'K SEGMENTS
ARE ENABLED VIA Wll-W14,

PROM

SIZE

JUMPER CONFIGURATION

W12

W13

NOTES'
1. Factory configured address range'" 140000·157777

2. I '" Jumper Installed; A = Jumper removed

MRV 11-BA PROM Addressing

422

W14

M8021
RAM Addressing Summary
Memory Jumper Configuration
(I = Installed; R = Removed)
Address
Range (Octal)

000000-000777
001000-001777
002000-002777
003000-003777
004000-004777
005000-005777
006000-006777
007000-007777
010000-010777
o1 1000 - 0 1 1777
012000-012777
013000-013777
014000-014777
015000-015777
016000-016777
017000-017777
020000-020777
021000-021777
022000-022777
023000-023777
024000-024777
025000-025777
026000-026777
027000-027777
030000-030777
031000-031777
032000-032777
033000-033777
034000-034777
035000-035777
036000-036777
037000-037777
040000-040777
041000-041777
042000-042777
043000-043777
044000-044777
045000-045777
046000-046777
047000-047777

Bank W3 W4 WS W6 W7 W8 W9 W19 W20

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

2
2
2
2
2
2
2
2

423

I
I
I
I
I
I
I
I

I
I
I
I

R
R
R
R
R
R
R
R

I
I
I
I

I
I
I
I
I
I
I
I

I
I
I
I

R
R
R
R
R

I
I
I
I

R
R

R
I
I
I
I
I
I
I
I

R
R
R
R

R
R
R
R
I
I
I
I

R
R
R
R

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

M8021
RAM Addressing Summary (Cont)
Address

Memory Jumper Configuration
(I = Installed; R = Removed)

Range (Octal)

Bank W3 W4 W5 W6 W7 W8 W9 W19 W20

050000-050777
051000-051777
052000-052777
053000-053777
054000-054777
055000-055777
056000-056777
057000-057777
060000-060777
061000-061777
062000-062777
063000-063777

2
2
2
2
2
2
2
2
3
3
3
3

064000-064777
065000-065777
066000-066777
067000-067777
070000-070777
071000"'071777
072000-072777
073000-073777
074000-074777
075000-075777
076000-076777
077000-077777
100000-100777
101000-101777
102000-102777
103000-103777
104000-104777
105000-105777
106000-106777
107000-107777
110000- 110777
111000-111777
112000-112777
113000-113777
114000-114777
115000-115777
116000-116777
117000-117777

3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

424

R
R
R
R
R
R
R
R

I
I
I
I
I
I
I
I

R
R
R
R
R
R
R
R

I
I
I
I

R
R
R
R

I
I
I
I

R
R

I
I

R
R
R
R
R
R
R
R
R
R
R
R

I
I
I
I

R
R
R
R

R
R

I
I

R
R
R
R
R
R
R
R

I
I
I
I

I
I
I

I
I
I
I
I
R
R
R
R
R
R
R
R

R
R
R
R

R
R

I
I

I
R

R
R

I
I

R
R

I
I

R
R
R
R

R
R

I
I

I
I
I
I

R
R
I

R
R

I
I

I
I
I
I

R
R

R
R
R
R

R
R

I
I

R
R
R
R

I
I

R
R
R

R
R
R
R

I
R
R

M8021
RAM Addressing Summary (Cont)
Address

Memory Jumper Configuration
(I = Installed; R = Removed)

Range (Octal)

Bank W3 W4 W5 W6 W7 W8 W9 W19 W20

120000-120777
121000-121777
122000-122777
123000-123777
124000-124777
125000-125777
126000-126777
127000-127777
130000-130777
131000-131777
132000-132777
133000-133777
134000-134777
135000-135777
136000-136777
137000-137777

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

140000-140777
141000-141777
142000-142777
143000-143777
144000-144777
145000-145777
146000-146777
147000-147777
150000-150777
151000-151777
152000-152777
153000-153777
154000-154777
155000-155777
156000-156777
157000-157777
160000-160777
161000-161777
162000-162777
163000-163777
164000-164777
165000-165777
166000-166777

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7"
7"
7"
7"
7"
7"
7"

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

I
I

I
I
I
I

R
R
R
R

R
R

I
I

R
R
R
R
R
R
R
R

I
I
I
I

R
R

I
I

R
R

I
I

R
R
R
R
I
I
I
I

I
I

R
R
R
R
R
R
R

R
R

I
I
I
I

I
I

R
R
R
R

R
R
R
R
R
R
R
R

I
I
I
I

I
I
I
I
I
I
I

I
I
I
I

R
R
R
R

R
R
R

I
I
I
I

R
R
R
R

R
R

I
I

R
R

I
I

R
I

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
I

R
R

I
I
I
I
I
I

"The bank 7 enable jumper W 18 is factory installed to allow addressing in
bank 7.
425

M8021
RAM Addressing Summary (Cont)
Address

Memory Jumper Configuration
(I = Installed; R = Removed)

Range (Octal)

Bank W3 W4 W5 W6 W7 W8 W9 W19 W20

167000-167777
170000-170777
171000-171777
172000-172777
173000-173777
174000-174777
175000-175777
176000-176777
177000-177777

7"
7"
7"
7"
7"
7"
7"
7"
7"

R
R
R
R
R
R
R
R
R

R
R
R
R
R
R
R
R

I
I
I
I

R
R

I
I

R
R

R
R
R
R

I
I

R
R
R
R
I

• The bank 7 enable jumper W 18 is factory installed to allow addressing in
bank 7.

426

M8021
NOTE
The following jumper configurations illustrate configuring the
address range in banks above bank 7 (not implemented in present LSI-11 system configurations). W8, W9, W 19, and W20
can be configured as shown in the preceding pages to select
the desired segment within the bank.
Address

Memory Jumper Configuration
(I = Installed; R = Removed)

Range (Octal)

Bank

200000-217777
220000-237777
240000-257777
260000-277777
300000-317777
320000-337777
340000-357777
360000-377777
400000-417777
420000-437777
440000-457777
460000-477777
500000-517777
520000-537777
540000-557777
560000-577777
600000-617777
620000-637777
640000-657777
660000-677777
700000-717777
720000-737777
740000-757777
760000-777777

10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

I
I
I
I
I
I
I
I

R
R
R
R
R
R
R
R

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

I
I
I
I
I
I
I
I

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

I
I
I
I

I
I

R
R

R
R
R
R

I
I

427

R
R
R
R
R
R
R
R

R
R

R
R
R
R
R
R
R
R
R
R
R

I
R

M8021
PROM Addressing Summary
Address

Memory Jumper Configuration
(I = Installed; R = Removed)

Range (Octal)

Bank

000000-017777
020000-037777
040000-057777
060000-077777
100000-117777
120000-137777
140000-157777
160000-177777
200000-217777
220000-237777
240000-257777
260000-277777
300000-317777
320000-337777
340000-357777
360000-377777
400000-417777
420000-437777
440000-457777
460000-477777
500000-517777
520000-537777
540000-557777
560000-577777
600000-617777
620000-637777
640000-657777
660000-677777
700000-717777
720000-737777
740000-757777
760000-777777

0
1
2
3
4
5
6
7*
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

W15

W17

W16

I
I
I
I
I
I
I
I

R
R
R
R

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

I
I
I
I
I
I
I
I

R
R
R
R
R
R
R
R

I
I
I
I

R
R
R
R
I
I
I
I

R
R

R
R
R
R
R
R
R
R
R
R
I

I
I

R
R

I
I

R
R

I
I

*The bank 7 enable jumper W18 is factory installed to allow
addressing in bank 7.

428

R
R
R
R

M8021
PROM Addressing
Address*
Octal Binary
0
2
4
6
10
12
14

10090807060504030201 Address Bits
22 23 1 2 3 4 5 6 7 8 PROM Pins

00000000000 L
00000000010 L
00000000100 L
00000000110 L
00000001000 L
00000001010 L

3776 11111111110 H

L
L
L
L
L
L

H H

L
L
L
L
L
L

H H H H

L
L
L
L
H
H

L L
L H
H L
H H
L L
L H

Actual Logic
Levels Required

(1024 10
Locations)

H H H

*Bus address bit 0 is not used. Therefore, only even-numbered addresses
are shown.

429

M8027

M8027
LPV11 LP05/LA180 INTERFACE MODULE

Amps
+5
0.8

Bus Loads
+ 12
0

AC
1.4

I LPZS

Cables

DC
BC 11 S-25 for LA 180
70-11212-25 for LP05

Standard Addresses
LPCS
LPDB

177514
177516

Standard Vector
Done or error interrupt 200

Diagnostic Programs
Refer to Appendix A.

Related Documentation
LP25 Line Printer Maintenance Guide (ER-OLP25-5V)
LPVII Printer User's Manual (EK-LPV 11-0P)
LA 180 DECprinter I User's Manual (EK-LA 180-0P)
LA 180 Field Maintenance Print Set (MP-LA 180-00)
LA 180 DECprinter I Maintenance Manual (EK-LA 180-MM)
LP05 Technical Manual, Model 2230 Line Printer (Dataproducts
Corporation)
LPV 11-V Field Maintenance Print Set (MP00467)
Microcomputer Interfaces Handbook (EB-20175-20)

NOTE
The LPV11 (M8027) is a direct replacement for the LAV11
(M7949).
430

M8027

1~~.'MN
w6A !mH
pI Ow,
W14

> > »»

F+

2. 2. 2.

> »»>

W4
W3

~2~Y i
:;::;::;:~ ~

bb6~ &

III V

<1:<1:

TI ~W7
W,}

NOTE:

i ~JHUE~:E~~R~~::pN J~~~ECRL;~~~L~NN~~I~:~~~RBEE
~ USED TO REPLACE PREVIOUSLY REMOVED FACTORY

INSTALLED (W) JUMPERS (SHOWN INSTALLED).

o =WIRE WRAP PIN.

431

W13
W12
Wll
Wl0
W9

M8027
DEVICE ADD:::

~,."";';'-r-,;,;;"",r:""'''''';';'-,-''';;;''''-:~'''';;:'''''';';'''-r-;,;""r,.-=,.-~....==-r-=':'-r-''::''''

FDRMAT
L-~--~~~~~~~~-r~~~-L'-~~~~~-r~~

FACTDRY

CD~~U~~7~1~~
LPDa - 177518

I
t

+ t

I
t

+ t + + + +

All

Al0

All

A7
(W41

AS
(W31

A4
(W2j

A3
JUMPER
(FACTDRY INSTALLEDI

I-INSTALLED-LDGICAL-O
R-REMOVED-LOGICAL-l

LPV 11 Interrupt Device Address Format and Jumpers

BITS
VECTOR ADDRESS
FORMAT

II
0

FACTORY
CONFIGURATIDN

I-INSTALLED-LOGICAL 0
R-REMOVED-LOGICAL 1

I I I I I I I I I
1111111
l ! ! ! !! l
0

- 200

JUMPER
(FACTORY INSTALLEDI

(W141

va
V4
V5
V3
!W131 (W121 (Will (Wl01

(wei

LPV 11 Vector Address Format and Jumpers

LPV 11 Jumper Definitions
Jumper
Designation

Configuration
When Shipped

A12
A 11
A10

R
R
R
R
R
I

A9
AS

A7
A6
A5
A4
A3
VS
V7

V6
V5
V4

V3
V2

Function
Jumper wires W2, W3, and W4 are factory installed to negate address bits 4, 5,
and 7, respectively.
This sets 177514 as the base address.

R
I
I
R

I
R
I
I
I
I
I

Jumper wires W9 through W 14 are factory installed to negate vector bits 2, 3, 4,
5,6, and S.
This sets 200 as the interrupt vector.

432

M8027
LPV11 Jumper Definitions (Cont)
Jumper
Designation

Configuration
When Shipped

Function
W 1 installed to delay BRPL Y L.

T
W7

R
I

Supports both uppercase and lowercase
printing. For uppercase only, remove W7
and install T.
Do not configure the module with both
jumpers W7 and T installed.

Configured to transmit parity (bit 07) to
printer.
Parity Option

Jumper WS

Jumper P

Normal parity
bit
No parity,
bit 07 low
No parity,
bit 07 high

Installed

Removed

Installed

Do not configure the module with both
jumpers W8 and P installed.
NOTE
If the LPV 11 interface module is used with an LP05 printer
equipped with the Direct Access Vertical Form Unit (DAVFU), it
is recommended that the user remove jumper WS. The LP05 interface module does not support the DAVFU Function.

F-

F+

W6 is installed at F + to enable error filter operation with the LP05.
For operation without the error filter, remove W6 and install a jumper at F - .
Do not configure the module with jumpers
installed at both F + and F - .
The I!A 180 automatically enables the error filter circuit regardless of the jumper
configuration.

433

M8027

LPCS
y
(NOT USEDI

ERROR
(READONLVI

y
(NOT USEDI

DONE
(READ ONLVI

ON LINE
IREAD·ONL VI

INTERRUPT ENABLE
(READ/WRITEI

BUSV
(READ·ONL VI
MR·0823

LPV 11 Control/Status Register (LPCS)

LPCS Register Bit Functions
Bit

Function

Error - Asserted (1) whenever an error condition exists in the
line printer. Error conditions include the following.
LP05 errors:

•
•
•
•
•
•
•

Power off
No paper
Printer drum gate open
Over-temperature alarm
PRINT INHIBIT switch off
Printer off-line
Torn paper

LA 180 errors:
•
•

Fault (paper fault)
ON-LINE switch (in OFF position)

Reset by manual correction of error condition if LPCS bit 06 is
not set. If bit 06 is set, bit 15 is reset by manual correction of the
error and (1) reading the interrupt vector if the interface is
"ready," or (2) after reading the LPCS if the interface is "not
ready." Read only.
14-08

Not used. Read as Os.

434

M8027
LPCS Register Bit Functions (Cont)
Bit

Function

Done LP05 - Asserted (1) whenever printer is ready for next
character to be loaded. Indicates that previous function is either
complete or has been started and continued to a point where
the printer can accept the next command. This bit is set by the
LSI-11 processor asserting BINIT L; if bit 06 is also set, an interrupt sequence is initiated. Also set by the printer when on-line
and ready to accept a character. Cleared by loading (writing
into) the LPDB register. Inhibited when bit 15 is set. Read only.
LA 180 - Asserted (1) when the printer is ready to accept another character. Done is set by the LSI-11 processor asserting BINIT L and is cleared by loading (output transfer to) the LPDB
register. If the interrupt enable bit is set, setting done will initiate an interrupt request.

Interrupt Enable - Set or cleared by the program. Also cleared
by the LSI-11 processor asserting BINIT L. When set, an interrupt sequence is initiated if either the error or done bit is set.

05-02

Not used. Read as Os.

On-Line - Not supported and not required by DEC software.

Busy - Not supported and not required by DEC software. The following information is for reference only.
LA 180 - Set when the LA 180 prints a line or advances paper.
LP05 - Not used. Read as O.

435

M8027
08

I I I I I I
I I I I I I I I
I

LPoB

y
(NOT USEol

PARITY 07
OR 08
(OR PAPER
INSTRUCTION
FOR LPOSl

(REAOIWRITEl
MA-0824

LPV 11 Data Buffer Register (LPDB)

LPDB Register Bit Functions
Bit

Function

15-08

Not used. Read as Os. Data written into these bits is lost.

Parity or 08 - Optional use. Read as o.
LA 180 - Optional parity bit.
LP05 - Optional paper instruction bit. Not supported by the
LPV 11 (read as 0).

06-00

Data - Seven-bit ASCII character register. Characters are sequentially output to the printer buffer via this register. Read as
all Os.

436

M8028

M8028
DLV11-F ASYNCHRONOUS SERIAL LINE INTERFACE

Amps
+5
1.0

+ 12
0.18

Bus Loa(is

Cables

AC
2.2

BC05M for 20 mA
BC05C for EIA modem
BC05C plus H312A for EIA terminal

DC
1.0

Standard Addresses

RCSR
RBUF
XCSR
XBUF

Second
Console Terminal Modem

MINC/DECLAB

177560
177562
177564
177566

175610
175612
175614
175616

176500
176502
176504
176506

175610
175612
175614
175616

Standard Vectors
Floating - Configurable in the range of 000-770. Refer to Appendix B.

Receiver
Transmitter

Second
Console Terminal Modem

MINC/DECLAB

60
64

330
334

300
304

Diagnostic Programs
Refer to Appendix A.

Related Documentation
DL V 11-E and DL V 11-F Asynchronous Line Interface
User's Manual (EK-DLV 11-0P)
Field Maintenance Print Set (MP00461)
Microcomputer Interfaces Handbook (EB-20175-20)

437

M8028

'III Ii

C-___~

IEF

N~O

---cnCO""f.DIJ')'I::t'M

rrrrnnn I

lBG

MT
M.ql/)cD,...CO

frnrr

MR-2696

DL V 11-F Etch Rev B Jumper Locations

438

M8028

[

_4P
_4A
_3P
_5A

_R3
_R2
_Rl
_RO

_2P
_2A
_ _ lP
-lA

-B
--B
_H

-----..Sl
-----..TO
-----..Tl
-----..T2
-----..T3
_ _ Cl
_EF
_Ml
_C
_ S
--E
-----.. 1
_2
_P

_A12
_All

_ _ 3A

_M
_BG
_MT
_V5
-V
_
_6
V7
_A7
--A6
-A5

-----..Al0

_A9
-----..A8

_V8
_A4
_A3
_V4
_V3
_PB
_BPl
_AAl
_ABl

DL V 11-F Etch Rev C Jumper Locations

439

M8028
BDAl
BITS

II I I I
o

;;;

o • CSR

I ,DATA BUFFER

)

o • lOW BYTE) _ _ _-----.J
I • HIGH BYTE

RANGE· 1600008 - 1777768

DL V 11-F Addresses
Address Jumpers
Address

Unit

Console
177560
First Option
176500
Second Option 176510
176520
Third Option
175610
Modem

A12

R
R

A 11

A10 A9 Aa A7 A6 AS A4 A3

R
R
R
R

R
R

I
I
I
I

R
R
R
R

I
I
I
I
I

R
R
R

I
I
I
I

Etch Rev C

BD1

AA1

AB1

Vector Jumpers
Unit

Vector

va V7 V6 VS V4 V3

Console
First Option
Second Option
Third Option
Modem

60
300
310
320
300

R
R
I

R
R

440

R
R

R
R
R
R

I
I
I
I

R
R
R
R
R

I
I
I
I
I

M8028
00

0, RECEIVER
I 'TRANSMITTER

VECTOR JUMPERS'
INSTALLED'I
REMOVED, 0

CONTROLLED BY INTERRUPT
LOGIC CIRCUIT
RANGE· 0 -7748

DLV 11-F Interrupt Vectors

Jumper Configuration When Shipped
Jumper
Designation
A3
A4
A5
A6
A7
A8
A9
A10
A 11
A12

Jumper
State
R
I
I
I
R

Function
Jumpers A3 through A 12 implement device
address 17756X. The least significant octal
digit is hardwired on the module to address
the four device registers as follows.

RCSR

I
I
I

X
X
X

2
4

RBUF

XBUF

V3
V4
V5
V6
V7
V8

I
R
R
I
I
I

This jumper selection implements interrupt
vector address 60 for receiver interrupts
and 64 for transmitter interrupts.

I
R
R
R

The transmitter is configured for 9600 baud
if split speed operation is used.

I
R

Break generation is enabled.
Parity bit is disabled.

Parity type is not applicable when P is removed.

T1
T2
T3

XCSR

441

M8028
Jumper Configuration When Shipped (Cont)
Jumper
Designation

Jumper
State

Function

1
2

R
R

Operation with eight data bits per character.
(See "Data Bit Selection" table.)

Programmable baud rate function disabled.
Common speed operation enabled.

C
C1
S
S1

R
R

Halt on framing error enabled.

H
B
B

Boot on framing error disabled.

1A
2A
3A
1P
2P

I
I
I

4A
5A
3P
4P

I
I

The 20 rnA current loop receiver is
configured as an active receiver.

R
R
The 20 rnA current loop transmitter is
configured for active operation.

R
R
Error flags disabled.

EF
M
M1
MT

Split speed operation disabled.

R
R
R

Factory test jumpers. Not defined for field use.
Maintenance bit disabled.

442

M8028
Baud Rate Selection

Program Control
Receive Jumpers
Transmit Jumpers

Bit

15
R3
T3
I
I
I
I
I
I
I
I
R
R
R
R
R
R
R
R

14
R2
T2
I
I
I
I
R
R
R
R
I
I
I
I
R
R
R
R

13
R1
T1
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R

12
RO
TO
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R

11 •

Baud Rate

50
75
110· •
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

I = jumper inserted = program bit cleared.
R = jumper removed = program bit set.
Bit 11 of the XCSR (write-only bit) must be set in order to select a new
baud rate under program control. Also, jumper PB must be inserted to
enable baud rate selection under program control.
When configured for 110 baud, the UART is set for two stop bits.

443

M8028
Data Bit Selection
Jumpers

Number of Data Bits

2
I
I
R
R

I
R
I
R

5
6
7

Jumper Definitions
Jumper

Function

A3-A 12

These jumpers correspond to bits 3-12 of the address word.
When inserted, they will cause the bus interface to check for a
true condition on the corresponding address bit.

V3- va

Used to generate the vector during an interrupt transaction.
Each inserted jumper will assert the corresponding vector address bit on the LSI-11 bus.

RO-R3

Receiver and transmitter baud rate jumpers selected during
common speed operation.
Receiver-only baud rate select jumpers used during split speed
operation.

TO-T3

Transmitter baud rate select jumpers used during split speed
operation.
Both receiver and transmitter baud rates used if maintenance
mode is entered during split speed operation.

Jumper is inserted to enable break generation.

Jumper is inserted for operation with parity.

Removed for even parity; inserted for odd parity. Receiver
checks for appropriate parity and transmitter inserts appropriate parity.

1, 2

These jumpers select the desired number of data bits.

Jumper is inserted in order to enable the programmable baud
rate capability.

444

M8028
Jumper Definitions (Cont)
Jumper

Function

C,C1

These jumpers are inserted for common speed operation. Note
that Sand S 1 must be removed when C and C 1 are inserted.

S, S1

Inserted for split speed operation. Note that C and C 1 must be
removed when Sand S 1 are inserted.

This jumper is inserted to assert BHAL T L when a framing error
is received, except when the maintenance bit is set. This places
the LSI-11 in the halt mode.

B,B

1A,2A,
3A

These three jumpers are inserted to make the 20 mA and 3A
current loop receiver active. (Jumpers 1P and 2P are removed
when 1A, 2A, and 3A are inserted.)

1P, 2P

These jumpers are inserted to make the 20 mA current loop receiver passive. (Jumpers 1A, 2A, and 3A must be removed when
1P and 2P are installed.)

4A, 5A

Inserted to make the 20 mA current loop transmitter active. (3P
and 4P must be removed when 4A and 5A are inserted.)

3P, 4P

Inserted to make the 20 mA current loop transmitter passive.
(4A and 5A must be removed when 3P and 4P are inserted.)

Jumper is removed to enable the error flags to be read in the
high byte of the receiver buffer.

When inserted, enables maintenance bit.

M,M1

These are test jumpers used during the manufacturing of the
module. They are not defined for field use.

445

M8028

1t - 4965

DL V 11-F RCSR Sit Assignments

DLV11-F RCSR Bit Assignments
Bit

Function

15-12

Not used. Reserved for future use.

Receiver Active (RCVR ACT) - When set, this bit indicates that
the DL V 11-F interface receiver is active. The bit is set at the
center of the start bit, which is the beginning of the input serial
data from the device, and is cleared by the leading edge of
ROaNE H.

10-08

Not used. Reserved for future use.

Receiver Done (RCVR DONE) - This bit is set when an entire
character has been received and is ready for transfer to the LSI11 bus. When set, initiates an interrupt sequence provided
RCVR INT ENS (bit 06) is also set.
Read-only bit; cleared whenever the receiver buffer (RSUF) is
addressed or whenever RDR ENS (bit 00) is set. Also cleared by
INIT.

Receiver Interrupt Enable (RCVR INT ENS) - When set, allows
an interrupt sequence to start when RCVR DONE (bit 07) sets.
Read/write bit; cleared by INIT.

05-01

Not used. Reserved for future use.

Reader Enable (RDR ENS) - When set, this bit advances the paper-tape reader in DIGITAL-modified TTY units (L T33-C; L T35-A,
-C) and clears the done bit (bit 07).
This bit is cleared at the middle of the start bit, which is the beginning of the serial input from an external device. Also cleared
by INIT. Write only.

446

M8028
14

RESERVED

RECEIVED DATA BITS

DLV11-F RBUF Bit Assignments
Bit

Function

Error - Used to indicate that an error condition is present. This
bit is the logical OR of OR ERR, FR ERR, and P ERR (bits 14, 13,
and 12, respectively). Whenever one of these bits is set, it
causes the error bit to set. This bit is not connected to the interrupt logic.
Read-only bit; cleared by removing the error condition.

NOTE
Error indications remain present until the next character is received, at which time the error bits are updated. INIT clears
the error bits.

Overrun Error (OR ERROR) - When set, indicates that the reading of the previously received character was not completed
(RCVR DONE not cleared) prior to receiving a new character.
Read-only bit; cleared by INIT.

Framing Error (FR ERR) - When set, indicates that the character that was read had no valid stop bit. Read-only bit; cleared by
INIT.

Parity Error (P ERR) - When set, indicates that the parity received does not agree with the expected parity. This bit is always 0 if no parity is selected.

11-08

Not used. Reserved for future use.

07-00

Received (Data Bits) - Holds the character just read. If fewer
than eight bits are selected, then the buffer is right-justified into
the least significant bit positions. Then, the higher unused bit or
bits are read as Os. Read-only bits; not cleared by INIT.

447

M8028
iO

RESERVED

DLV11-F XCSR Bit Assignments
Bit

Function

15-12

Programmable Baud Rate Select (PBR SEL) - When set, these
bits choose a baud rate from 50-9600 baud. Write only.

Programmable Baud Rate Enable (PBR ENB) - This bit must be
set in order to select a new baud rate indicated by bits 12 to 15.
Write only.

10-08

Not used. Reserved for future use.

Transmitter Ready (XMIT ROY) - This bit is set when the transmitter buffer (XBUF) can accept another character. When set, it
initiates an interrupt sequence provided XMIT INT ENB (bit 06) is
also set.

Transmitter Interrupt Enable (XMIT INT ENB) - When set, allows
an interrupt sequence to start when XMIT ROY (bit 07) is set.
Read/write bits; cleared by INIT.

05-03

Not used. Reserved for future use.

MAINT - Used for maintenance function. When set, connects
the transmitter serial output to the receiver serial input while
disconnecting the external device from the receiver serial input.
It also forces the receiver to run at transmitter baud rate speed
when split speed operation is enabled. Read/write bit; cleared
by INIT.

Not used. Reserved for future use.

Break - When set, transmits a continuous space to the external
device.
Read/write bit; cleared by INIT.

448

M8028
08

TRANSMITTER DATA BUFFER

RESERVED

11·5155

DLV11-F XBUF Bit Assignments
Bit

Function

15-08

Not used. Not. defined. Not necessarily read as Os.

07-00

449

M8029

M8029
RXV21 FLOPPY DISK CONTROLLER

Amps
+5
1.8

+ 12

Bus Loads

Cables

AC
3.0

BC05L-15

DC
1.0

Standard Addresses

RXCS
RXDB

First Controller

Second Controller

177170
177172

177200
177202

Standard Vectors
264

270

Diagnostic Programs
Refer to Appendix A.

Related Documentation
RXV21 Field Maintenance Print Set (MP00628)
RX02 Floppy Disk System User's Guide (EK-RX02-UG)
RXO 1/RX02 Reference Card (EK-RX 102-RC)
RX02 Technical Manual (EK-ORX02-TM)
Minicomputer Interfaces Handbook (EB-20 175-20)
RX02 Field Maintenance Print Set (MP-00629-00)

CAUTION
PDP-11/23 systems require the M8029 to be at CS revision E1
or higher.

450

M8029

BC05L-15
CABLE CONNECTION

O--OA3
0--0 A 120--0 A4
0--0 V2 0--0 A5
o OV3 O--OA6
O--OV4 0
OAl
O--OV5 0
OAB
o OV6 O--OA9
0--0 Vl O--OA10
o OVB O--OA11

M8029 Module Address and Vector Jumpers

451

M8029
STANDARD ADDRESSES
15

: :

177170
DTHE R 177200

: : : : : : : : : :
0

STANDARD VECTOR ADDRESS
15

264
OTHER 270

RX2BA 177172
STARTING MEMORY ADDRESS OF DATA

RXDB

177172
NOT USED

DATA BYTE

RXV21 Error Codes

Error Reg

Error Codes

15141312111098

Track addr sel DV

DV
DEN HD DEN
SEL DV1 LD DVO

3 2

Target Sector

Target Track

Current Track DV 1

Current Track DVO

Word Count Reg

Error Code

1 0

DEN
CMD

The following sequence is used to get definitive error information following
a bootstrap operation. (It is assumed that the bootstrap program has halted
and the CPU is in ODT.)
1. Examine R5 (RF will contain RXES after an error).
2. Examine RXER by:
• Loading the READ ERROR REGISTER command
(777170/XXXXXX 17<CR».

into RX2CS

• Examining the four words of error information that will be transferred
into locations 2000, 2002, 2004, and 2006.
• Reading and decoding this information using the format shown below. The error code can be used to help identify the failing FRU.
452

M8029

DONE

RX2CS Format RXV21

Bit Definitions
Bit

Function

Go - Initiates a command to RX02. Write only.

1-3

Function Select - These bits code one of the eight possible
functions described below. Write only.

Code

Function

000
001
010
011
100
101
110
111

Fill Buffer
Empty Buffer
Write Sector
Read Sector
Set Media Density
Read Status
Write Deleted Data Sector
Read Error Code

Unit Select - This bit selects one of the two possible disks for
execution of the desired function. This bit is readable only when
done is set, at which time it indicates the unit previously selected. Read/write.

Done - This bit indicates the completion of a function. Done will
generate an interrupt when asserted if interrupt enable (RX2CS
bit 6) is set. Read only.

Interrupt Enable - This bit is set by the program to enable an
interrupt when the RX02 has completed an operation (done).
The condition of this bit is normally determined at the time a
function is initiated. Read/write; cleared by initialize.

Transfer Request - This bit signifies that the RXV21 needs data
or has data available. Read only.

Density - This bit determines the density of the function to be
executed. This bit is readable only when done is set, at which
time it indicates the density of the function previously executed.
Read/write.

453

M8029
Bit Definitions (Cont)
Bit

Function

Head Select - This bit selects one of two heads for double-sided
operation, readable only when done is set. At that time the side
that was previously selected is not valid.

Reserved for future use. Must be written as a o.

RX02 - This bit is set by the interface to inform the programmer
that this is an RX02 system. Read only.

12-13

Extended Address - These bits are used to declare an extended bus address. Write only.

RXV21 Initialize - This bit is set by the program to initialize the
RXV21 without initializing all devices on the UNIBUS. Write only.
CAUTION
Loading the lower byte of the RX2CS will also load the upper
byte of the RX2CS.
Upon setting this bit in the RX2CS, the RXV21 will negate done
and move the head position mechanism of both drives (if two
are available) to track o. Upon completion of a successful initialize, the RX02 will zero the error and status register, and set
initialize done. It will also read sector 1 of track 1 on drive 0 into
the buffer.

Error - This bit is set by the RX02 to indicate that an error has
occurred during an attempt to execute a command. Read only;
cleared by the initiation of a new command or an initialize.

I0 I
t

0-114.

NOT USED

RX2TA Format (RXV21)
RX2TA (RX Track Address) - This register is loaded to indicate on which
of the 1148 (0-76 10 ) tracks a given function is to operate. It can be addressed only under the protocol of the function in progress. Bits 8- 15 are
unused and are ignored by the control.

454

M8029
15

NOT USED

RX2SA Format (RXV21)

RX2SA (RX Sector Address) - This register is loaded to indicate on which
of the 328 (1-26 10 ) sectors a given function is to operate. It can be addressed only under the protocol of the function in progress.
15

1~lol
RX2WC Format (RXV21)

RX2WC (RX Word Count Register) - For a double-density sector, the maximum word count is 128 10 , For a single-density sector the maximum word
count is 64 10 , If a word count is beyond the limit for the density indicated,
the control asserts word count overflow (bit 10 of RX2ES). This is a writeonly register. The actual word count, and not the 2's complement of the
word count, is loaded into the register.
15

RX2BA and RX2DB Format (RXV21)

RX2BA (RX Bus Address Register) - This register specifies the bus address of data transferred during fill buffer, empty buffer, and read definitive
error operations. Incrementation takes place after a memory transaction
has occurred. The RX2BA, therefore, is loaded with the address of the first
data word to be transferred. This is a 16-bit, write-only register.
RX2DB (RX Data Buffer) - All information transferred to and from the floppy media passes through this register and is addressable only under the
protocol of the function in progress.
RX2DB (Data Buffer Register [177172]) - This register serves as a general purpose data path between the RX02 and the interface. It may represent
one of six RX02 registers according to the protocol of the function that is in
progress.
455

M8029
This register is read/write if the RX02 is not in the process of executing a
command; that is, it may be manipulated without affecting the RX02 subsystem. If the RX02 is actively executing a command, this register will only
accept data if RX2CS bit 7 (TR) is set. In addition, valid data can only be
read when TR is set.

CAUTION
Violation of protocol in manipulation of the data buffer register
may cause permanent data loss.

WC
OVFL

DEN
ERR

HD
SEL

CRC
SIDE 1
RDY

RX2ES Format (RXV21)

RX2ES (RX Error and Status) - This register contains the current error and
status conditions of the drive selected by bit 4 (unit select) of the RX2CS.
This read-only register can be addressed only under the protocol of the
function in progress. The RX2ES is located in the RX2DB upon completion
of a function.
RXES bit assignments are as follows.
Bit Definitions
Bit

Function

CRC Error - A cyclic redundancy check error was detected as
information was retrieved from a data field of the diskette. The
data collected must be considered invalid. The RX2ES is moved
to the RX2DB, and error and done are asserted. It is suggested
that the data transfer be tried up to 10 times, as most errors are
recoverable (soft).
Side 1 Ready - This bit, when set, indicates that a double-sided
diskette is mounted in a double-sided drive and is ready to execute a function. This bit is valid only at the termination of an initialize sequence or a maintenance READ STATUS command.

456

M8029
Bit Definitions (Cont)
Bit

Function

Initialize Done - This bit is asserted in the RX2ES to indicate
completion of the initialize routine which can be caused by
RX02 power failure, system power failure, or programmable or
bus initialize.

RX AC LO - This bit is set by the interface to indicate a power
failure in the RX02 subsystem.

Density Error - This bit indicates that the density of the function
in progress does not match the drive density. Upon detection of
this error the control terminates the operation and asserts error
and done.

Drive Density - This bit indicates the density of the diskette in
the drive selected (indicated by bit 8). The density of the drive is
determined during read and write sector operations.

Deleted Data - This bit indicates that in the course of recovering data, the "deleted data" address mark was detected at
the beginning of the data field. The DRV DEN bit indicates
whether the mark was a single- or double-density deleted data
address mark. The data following the mark will be collected and
transferred normally, as the deleted data mark has no further
significance other than to establish drive density. Any alteration
of files or actual deletion of data due to this mark must be accomplished by user software.

Drive Ready - This bit indicates that the selected drive is ready
if bit 7 = 1 and all conditions for disk operation are satisfied,
such as door closed, power OK, diskette up to speed, etc. The
RX02 may be presumed to be ready to perform any operation.
This bit is only valid when retrieved via a read status function or
initialize.

Unit Select - This bit indicates that drive 0 is selected if bit
8 = O. This bit indicates the drive that is currently selected.

Head Select - This bit indicates which side of a double-sided
drive performed the last operation.

Word Count Overflow - This bit indicates that the word count is
beyond sector size. The fill or empty buffer operation is terminated and error and done are set.

Nonexistent Memory Error - This bit is set by the interface when
a DMA transfer is being performed and the memory address
specified in RX2BA is nonexistent.

457

M8029
Function Codes
Following the strict protocol of the individual function, data storage and recovery on the RXV21 occur with careful manipulation of the RX2CS and
RX2DB registers. The penalty for violation of protocol can be permanent
data loss.
A summary of the function codes is presented below.
000
001
010
011
100
101
110
111

Fill Buffer
Empty Buffer
Write Sector
Read Sector
Set Media Density
Read Status
Write Deleted Data Sector
Read Error Code

The following paragraphs describe in detail the programming protocol associated with each function encoded and written into RX2CS bits 1-3 if
done is set.
Fill Buffer (000) - This function is used to fill the RX02 data buffer with the
number of words of data specified by the RX2WC register. Fill buffer is a
complete function in itself: the function ends when RX2WC overflows, and if
necessary, the control has zero-filled the remainder of the buffer. The contents of the buffer may be written on the disk by means of a subsequent
WRITE SECTOR command or returned to the host processor by an EMPTY
BUFFER command. If the word count is too large, the function is terminated, error and done are asserted, and the word count overflow bit is set
in RX2ES.
To initiate this function the RX2CS is loaded with the function. Bit 4 of the
RX2CS (unit select) does not affect this function since no disk operation is
involved. Bit 8 (density) must be properly selected since this determines
the word count limit. When the command has been loaded, the done bit
(RX2CS bit 5) goes false. When the TR bit is asserted, the RX2WC may be
loaded into the data buffer register. When TR is again asserted, the RX2BA
may be loaded into the RX2DB. The data words are transferred directly from
memory and when RX2WC overflows and the control has zero-filled the remainder of the sector buffer, if necessary, done is asserted, ending the operation. If bit 6 RX2CS (interrupt enable) is set, an interrupt is initiated. Any
read of the RX2DB during the data transfer is ignored by the interface. After
done is true, the RX2ES is located in the RX2DB register.
Empty Buffer (001) - This function is used to empty the contents of the
internal buffer through the RXV21 for use by the host processor. This data
is in the buffer as the result of a previous FILL BUFFER or READ SECTOR
command.

458

M8029
The programming protocol for this function is identical to that for the FILL
BUFFER command. The RX2CS is loaded with the command to initiate the
function. (This function will ignore bit 4 RX2CS, unit select.) RX2CS bit 8
(density) must be selected to allow the proper word count limit. When the
command has been loaded, the done bit (RX2CS bit 5) goes false. When
the TR bit is asserted, the RX2WC may be loaded into the RX2DB. When TR
is again asserted the RX2BA may be loaded into the RX2DB. The RXV21
assembles one word of data at a time and transfers it directly to memory.
Transfers occur until word count overflow, at which time the operation is
complete and done goes true. If bit 6 RX2CS (interrupt enable) is set, an
interrupt is initiated. After done is true, the RX2ES is located in the data
buffer register.
Write Sector (010) - This function is used to locate a desired sector on
the diskette and fill it with the contents of the internal buffer. The initiation
of the function clears RX2ES, TR, and done.
When TR is asserted, the program must load the desired sector address
into RX2DB, which will drop TR. When TR is again asserted, the program
must load the desired track address into the RX2DB, which will drop TR. TR
will remain unasserted while the RX02 attempts to locate the desired sector. The diskette density is determined at this time and is compared with
the function density. If the densities do not agree, the operation is terminated; bit 4 RX2ES is set, RX2ES is moved to the RX2DB, error (bit 15
RX2CS) is set, done is asserted, and an interrupt is initiated, if bit 6 RX2CS
(interrupt enable) is set.
If the densities agree but the RX02 is unable to locate the desired sector
within two diskette revolutions, the interface will abort the operation, move
the contents of RX2ES to the RX2DB, set error (bit 15 RX2CS), assert
done, and initiate an interrupt if bit 6 RX2CS (interrupt enable) is set.
If the desired sector has been reached and the densities agree, the RXV21
will write the 128 10 or 6410 words stored in the internal buffer followed by a
CRC character which is automatically calculated by the RX02. The RXV21
ends the function by asserting done and, if bit 6 RX2CS (interrupt enable) is
set, initiating an interrupt.

CAUTION
The contents of the sector buffer are not valid data after a
power loss has been detected by the RX02. However, write
sector will be accepted as a valid instruction and the (random)
contents of the buffer will be written, followed by a valid CRC.
NOTE
The contents of the sector buffer are not destroyed during a
write sector operation.

459

M8029
Read Sector (011) - This function is used to locate the desired sector and
transfer the contents of the data field to the internal buffer in the control.
This function may also be used to retrieve rapidly (5 ms) the current status
of the drive selected. The initiation of this function clears RX2ES, TR, and
done.
When TR is asserted the program must load the desired sector address
into the RX2DB, which will drop TR. When TR is again asserted, the program must load the desired track address into the RX2DB, which will drop
TR.
TR and done will remain negated while the RX02 attempts to locate the desired sector. If the RX02 is unable to locate the desired sector within two
diskette revolutions for any reason, ·the RXV21 /RX211 will abort the operation, set done and error (bit 15 RX2CS), move the contents of the RX2ES
to the RX2DB, and if bit 6 RX2CS (interrupt enable) is set, initiate an interrupt.
If the desired sector is successfully located, the control reads the data address mark and determines the density of the diskette. If the diskette
(drive) density does not agree with the function density the operation is terminated and done and error (bit 15 RX2CS) are asserted. Bit 4 RX2ES is
set (density error) and the RX2ES is moved to the RX2DB. If bit 6 RX2CS
(interrupt enable) is set, an interrupt is initiated.
If a legal data mark is successfully located, and the control and densities
agree, the control will read data from the sector into the internal buffer. If a
deleted data address mark was detected, the control will set bit 6 RX2ES
(DD). As data enters the internal buffer, a CRC is computed based on the
data field and the CRC bytes previously recorded. A nonzero residue indicates that a read error has occurred and the control sets bit 0 RX2ES
(CRC error) and bit 15 RX2CS (error). The RXV21 ends the operation by
asserting done and moving the contents of the RX2ES into the RX2DB. If bit
6 RX2CS is set, an interrupt is initiated.
If the desired sector is successfully located, the densities agree and the
data is transferred with no CRC error; done will be set and if bit 6 RX2CS
(interrupt enable) is set, the RXV21 initiates an interrupt.

Set Media Density (100) - This function causes the entire diskette to be
reassigned to a new density. Bit 8 RX2CS (density) indicates the new density. The control reformats the diskette by writing new data address marks
(double or single density) and zeroing all of the data fields on the diskette.

460

M8029
The function is initiated by loading the RX2CS with the command. Initiation
of the function clears RX2ES and done. When TR is set, an ASCII "I" (111)
must be loaded into the RX2DB to complete the protocol. This extra character is a safeguard against an error in loading the command. When the
control recognizes this character it begins executing the command.
The control starts at sector 1, track 0 and reads the header information,
then starts a write operation. If the header information is damaged, the control will abort the operation.
If the operation is successfully completed, done is set and if bit 6 RX2CS
(interrupt enable) is set, an interrupt is initiated.
CAUTION
This operation takes about 15 seconds and should not be interrupted. If for any reason the operation is interrupted, an illegal diskette will be generated which may have data marks of
both densities. This diskette should be completely reformatted.
Maintenance Read Status (101) - This function is initiated by loading the
RX2CS with the command. Done is cleared. The drive ready bit (bit 7
RX2ES) is updated by counting index pulses in the control. The drive density is updated by loading the head of the selected drive and reading the
first data mark. The RX2ES is moved into the RX2DB. The RX2CS may be
sampled when done (bit 5 RX2CS) is again asserted and if bit RX2CS (interrupt enable) is set, an interrupt will occur. This operation requires approximately 250 ms to complete.
Write Sector with Deleted Data (110) - This operation is identical to function 010 (write sector) with the exception that a deleted data address mark
is written preceding the data rather than the standard data address mark.
The density bit associated with the function indicates whether a single- or
double-density deleted data address mark will be written.
Read Error Code (111) - The read error code function implies a read extended status. In addition to the specific error code, a dump of the control's
internal scratch pad registers also occurs. This is the only way that the
word count register can be retrieved. This function is used to retrieve specific information as well as drive status information depending upon detection of the general error bit.
The transfer of the registers is a DMA transfer. The function is initiated by
loading the RX2CS with the command; then done goes false. When TR is
true, the RX2BA may be loaded into the RX2DB and TR goes false. The registers are assembled one word at a time and are then transferred directly to
memory.

461

M8029
FOLLOWING IS THE REGISTER PROTOCOl.
15
WORD 1

WORD COUNT REGISTER

DEFINITIVE ERROR CODE

CURRENT TRACK ADDR DRV 1

CURRENT TRACK ADDR DRV 0

TARGET SECTOR

TARGET TRACK

BAD TRACK

SOFT STATUS

15
WORD 2

15
WORD3

15
WORD 4

Definitive Error Codes
10

Drive 0 failed to see home on initialize.

Drive 1 failed to see home on initialize.

Tried to access a track greater than 76.

Home was found before desired track was reached.

Desired sector could not be found after 52 tries.

110

More than 40 /-LS and no SEP clock seen.

120

A preamble could not be found.

130

A preamble found but no 10 mark found within allowable time.

150

The track address of a good header does not compare with desired track.

160

Too many tries for lOAM.

170

Data was not found in allotted time.

200

CRC on reading the sector from the disk.

220

Failed maintenance wraparound check.

230

Word count overflow.
462

M8029
240

Density error.

250

Incorrect key word on SET DENSITY command.

Register Protocol
Word 1<7:0>
Word 1< 15:8>
Word 2<7:0>
Word 2<15:8>
Word 3<7:0>
Word 3< 15:8>
Word 4<7>
Word 4<5>
Word 4<6><4>
Word 4<0>
Word 4< 15:8>

Definitive error codes
Word count register
Current track address of drive 0
Current track address of drive 1
Target track of current disk access
Target sector of current disk access
Unit select bit·
Head load bit·
Drive density bit of both drives·
Density of READ ERROR REGISTER command·
Track address of selected drive· *

RX02 Power Fail or Initialize
When the RX02 control senses a loss of power within the RX02, it will unload the head and abort all controller action. The RXAC L line is asserted to
indicate to the RXV21 that subsystem power has gone. The RXV21 asserts
done and error and sets the RXAC L bit in the RXZES.
When the RX02 senses the return of power, it will remove done and begin a
sequence to:
1. Move each drive head position mechanism to track 0
2. Clear any active error bits
3. Read sector 1 of track 1, on drive 0
4. Assert initialize done in the RXES.
Upon completion of the power-up sequence, done is again asserted. There
is no guarantee that information being written at the time of a power failure
will be retrievable; however, all other information on the diskette will remain
unaltered.
For DMA interfaces, the controller status soft register is sent to the
interface at the end of the command. The four status bits are included
in an 8-bit word. Unit select = bit 7; density of drive 1 = bit 6; head
load = bit 5; density of drive 0 = bit 4; density of READ ERROR REGISTER command = bit o.
The track address of the selected drive-error is only meaningful on a
code 150 error. The register contains the address of the cylinder that
the head reached on a seek error.
463

M8043

DLV11-J SERIAL LINE UNIT

Amp

Bus Loads

+5V + 12 V AC
1.0
0.25

Cables

DC
BC21B-XX
BC20N-XX (Refer to DLV 11-KA)
BC20M-XX

Standard Addresses
Configuration No. 1

Channel 0

Channel 1

Channel 2

Channel 3

RCSR
RBUF
XCSR
XBUF

176500
176502
176504
176506

176510
176512
176514
176516

176520
176522
176524
176526

177560
177562
177564
177566

176500
176502
176504
176506

176510
176512
176514
176516

176520
176522
176524
176526

176530
176532
176534
176536

300
304

310
314

320
324

60
64

Configuration No. 2
RCSR
RBUF
XCSR
XBUF
Standard Vectors
Configuration No. 1
Receiver
Transmitter

464

M8043
Configuration No. 2
Receiver
Transmitter

300
304

310
314

320
324

330
334

Diagnostic Programs
Refer to Appendix A.

NOTE
This test requires that four H3270-A loopback plugs be inserted into the DLV11-J module in order for the diagnostic to
run.

Related Documentation
DL V11-J User's Guide (EK-OLV1J-UG)
Field Maintenance Print Set (MP00586)
Microcomputer Interfaces Handbook (EB-20 175-20)

465

M8043

RCSR

RECEIVER
DONE
(READONLYI

NOTE:
ONE OF FOUR CHANNELS SHOWN.
FORMAT THE SAME FOR ALL CHANNELS.

RECEIVER
INTERRUPT
ENABLE
(READIWRITEI

RCSR Registers Bit Assignments
Word

Bit

Function

RCSR

8-15

Not used. On read = O.

Receiver Done - Set when an entire character has
been received and is ready for input to the processor. This bit is automatically cleared when RBUF is
read, when INIT is asserted (on power-up or reset instruction), or when reader enable bit is set. Read
only.
If receiver interrupt enable (bit 6) is set, the setting
of receiver done starts an interrupt sequence.

Receive Interrupt Enable - Set under program control when it is desired to allow a receiver interrupt
sequence to occur when a character is ready for input to the processor (signified by receiver done
being set). Cleared under program control or by INIT.
Read/write.

1-5

Not used. On read = O.

Reader Enable - Setting this bit advances the paper
tape reader on an L T -33 terminal one character at a
time and the setting of this bit clears receiver done
(bit 7). Write only.
The DL V 11-KA 20 rnA current loop option is required
for operation of this bit.

466

M8043

RBUF

NOT USED

RECEIVE OATA
(7,8 BIT DATA IS RIGHT JUSTIFIED.I
IF BIT UNUSED ~ 0
(REAO ONLYI

(READ
ONLYI
NOTE:
ONE OF FOUR CHANNELS SHOWN,
FORMAT THE SAME FOR ALL CHANNELS.

RBUF Register Bit Assignments
Word

Bit

Function

RBUF

Channel Error Status - Logical OR of bits 14, 13, and
12. Read only.

Overrun Error - When set, indicates that the reading
of the previously received character was not completed (RCVR done not cleared) prior to receiving a
new character. The first character is "lost." Read
only; cleared by INIT being asserted.

NOTE
When back-to-back characters are received, one full character
time is allowed from the instant when receiver done (bit 7) is
set to the occurrence of an overrun error.
13

Framing Error - When set, indicates that the character read had no valid stop bit. This indicates that the
currently received character and the next character
are invalid. Read only; cleared by INIT.

Parity Error - When set, indicates that the parity received does not agree with the expected parity. This
bit is always 0 if no-parity operation is configured for
the channel. Read only.

NOTE
Error bits remain valid until the next character is received, at
which time the error bits are updated.
8- 11

Not used. On read = O.

0- 7

Data Bits - Contains seven or eight data bits in a
right-justified format. Bit 7 = 0 when seven data bits
are enabled. Read only.

467

M8043

TRANSMIT
READY
(READ ONLY)

TRANSMIT BREAK
(READ/WRITE)

TRANSMIT
INTERRUPT
ENABLE
(READ/WRITE)
NOTE
ONE OF FOUR CHANNELS SHOWN
FORMAT THE SAME FOR ALL CHANNELS.

XCSR Registers Bit Assignments
Word

Bit

Function

XCSR

8-15

Not used. On read = O.

Transmit Ready - Set when XBUF is empty and can
accept another character for transmission. It is also
set by INIT during the power-up sequence or during a
reset instruction.
If transmitter interrupt enable (bit 6) is set, the setting of transmit ready will start an interrupt sequence. Read only.

Transmit Interrupt Enable - Set under program control when it is desired to generate a transmitter interrupt request (when transmitter is ready to accept
a character for transmission).
The bit is cleared under program control, during
power-up
sequence,
or
reset
instruction.
Read/write.

1-5

Not used. On read =

Transmit Break - Set or reset under program control.
When set, a continuous space level is transmitted.
However, transmit done and transmit interrupt enable can still operate, allowing software timing of
break. When not set, normal character transmission
can occur. Read/write; cleared by INIT being asserted.

468

M8043
15

RCSR

INOT USED)

RECEIVER
DONE
IREAD ONLY)
RECEIVER
INTERRUPT
ENABLE
IREADIWRITE)

RBUF

NOT USED

RECEIVE DATA
17.8 BIT DATA IS RIGHT JUSTIFIED.)
IF BIT UNUSED = 0
IREAD ONLY)

XCSR

INOT USED)

TRANSMIT BREAK
IREADIWRITE)

TRANSMIT
INTERRUPT
ENABLE
IREADIWRITE)

XBUF

: I

I : : : : :

INOT USED)

TRANSMIT DATA
17. B BIT DATA IS RIGHT JUSTIFIED.)
IWRITE ONL Y) ON READ = 0

NOTE
ONE OF FOUR CHANNELS SHOWN.
FORMAT THE SAME FOR ALL CHANNELS.

DL V 11-J SLU Register Formats

XBUF Register Bit Assignments
XBUF

8-15

Not used. On read = O.

0-7

Data bits - Contains seven or eight right-justified
data bits. Loaded under program control for serial
transmission. Write only.

469

M8043
Jumper Configurations

2 X3

CHOAND{
CHl EIA
SELECTION

R 3

MOe_
NOe _
e
Mle_
Nle_ e

Rl0
CHO ....c:::J-e
CHO{

E f'i"l
De_
S ri""I

{

De_

CHl

::::i
Z

~Ul
«Il:

~.~

::a:«
::a:1l:
0«
uo..

pe_

CHl

E'"

~[L

Jl 1~~2:~
2::t.: V

3~N

}:-:!!":ATE

e_
e -_
_

eM2
eN2
eM3
eN3

}

CH2 AND
CH3 EIA
SELECTION

SELECTION
ALWAYS
IN

LUT

CHl TERM RESISTOR
CHO TERM RESISTOR
CH2 TERM RESISTOR
'-----CH3 TERM RESISTOR

S ...
Pe_
CH2

Ef'i"l

CH2{

De_

sf'i"l
Pe_
CH3

Ef'i"l

De_
S ......

pe_

o "X

ADDRESS AND
A5"-'1
A9 ......
A12e
Al0e_
Alle_
Ase_
C2e Cle V5......
o1X

VECTOR JUMPERS

~{A6_
A7. e

V6V7-

BX H

'--v-'

BREAK SELECTION
(CHANNEL 3)

DLV 11-J Component and Jumper Factory Configuration Summary

470

M8043
Address Selection

~ j j j j j j j j ~~YTIE
~SELECT~
~~~:~~DR~~SS
,~--e-~~= ~~~~
!
rI
SELECTED
III
BANK

IDEVICEI

FACTORY

SELECT

POINTER

=176500

10=XCSR
11 = XBUF

---.J

3 WIRE WRAP POSTS
IX. 1,01 ARE
PROVIDED FOR
EACH BIT.

2 WIRE WRAP
POSTS ARE
PROVIDED FOR
EACH BIT.

JUMPER X TO 1 = 1
JUMPE R X TO 0 = 0
NOTE:
RANGE 16ooooB-1777708 NON EXTENDED ADDRESS
7600008 -777770 8 EXTENDED ADDRESS

JUMPER IN = 1
JUMPER OUT = 0

00 = CHANNEL 0
01 = CHANNEL 1
10 = CHANNEL 2
11 = CHANNEL 3

Device Register Address Format
It is possible to independently configure the last four addresses (channel
3) to the LSI-11 console device (addresses 177560-177566) when certain
base addresses and console select jumpers· are installed. In this configuration, the preceding addresses (channels 0, 1, and 2) are not affected;
they are normal offsets of the configured base device address as shown in
the following table.
General Device Register Address Assignments
(Without Console Selected)
Address

Device Register

Module Base Address (BA)
BA + 2
BA + 4
BA + 6
BA + 10
BA + 12
BA + 14
BA + 16
BA + 20
BA + 22
BA + 24
BA + 26
BA + 30
BA + 32
BA + 34
BA + 36

Channel 0 RCSR
Channel 0 RBUF
Channel 0 XCSR
Channel 0 XBUF
Channel 1 RCSR
Channel 1 RBUF
Channel 1 XCSR
Channel 1 XBUF
Channel 2 RCSR
Channel 2 RBUF
Channel 2 XCSR
Channel 2 XBUF
Channel 3 RCSR
Channel 3 RBUF
Channel 3 XCSR
Channel 3 XBUF

* Console select jumpers C 1 and C2 installed select channel 3 as console

device.
471

M8043

General Device Register Address Assignments
(General Configuration With Console Selected)
Address

Device Register

Module Base Address (BA)
BA + 2
BA
4
BA + 6
BA + 10
BA
12
BA
14
BA + 16
BA
20
BA
22
BA + 24
BA + 26
177560
177562
177564
177566

+
+

* Channel 3 is enabled as a console device.

472

M8043

Specific Device Register Address Assignments
(DLV11-J Configured With BA = 176500 and BV = 300
Without Console Selected)
Address

Vector

176500
176502

RCSR
RBUF

300

176504
176506

XCSR
XBUF

304

176510
176512

RCSR
RBUF

310

176514
176516

XCSR
XBUF

314

176520
176522

RCSR
RBUF

320

176524
176526

XCSR
XBUF

324

176530
176532

RCSR
RBUF

330

176534
176536

XCSR
XBUF

334

177560
177562

RCSR
RBUF

177564
177566

XCSR
XBUF

Channel

Channel 0

Channel 1

Channel 2

Channel 3

Channel 3
Console Device

NOTE
All addresses are in octal notation.

473

M8043
Vector Selection
When channel 3 is configured as the console device interface using console select jumpers C 1 and C2, the interrupt vectors of the channel become 60 and 64. This is true regardless of the configured base vector of
the module. It should be noted that the preceding channels (0, 1, and 2) are
not affected and their vectors are normal offsets of the base vector configured, as shown in the following table.

General Vector Assignments
(Without Console Selected)
Vector Offsets

Interrupt Vector

Module Base Vector (BV)
BA + 4
BA + 10
BA + 14
BA + 20
BA + 24
BA + 30
BA + 34

Channel 0 Receiver
Channel 0 Transmitter
Channel 1 Receiver
Channel 1 Transmitter
Channel 2 Receiver
Channel 2 Transmitter
Channel 3 Receiver
Channel 3 Transmitter

General Vector Assignments
(With Console Selected)
Vector Offsets

Interrupt Vector

Module Base Vector (BV)
BA + 4
BA + 10
BA + 14
BA + 20
BA + 24
60
64

Channel 0 Receiver
Channel 0 Transmitter
Channel 1 Receiver
Channel 1 Transmitter
Channel 2 Receiver
Channel 2 Transmitter
Channel 3 Receiver·
Channel 3 Transmitter·

• Console selected

474

M8043

Specific Vector Assignments
(DLV11-J Configured With BV = 300
Without Console Selected)
Octal Vector

Interrupt Vector

300
304
310
314
320
324
330
334

Channel 0 Receiver
Channel 0 Transmitter
Channel 1 Receiver
Channel 1 Transmitter
Channel 2 Receiver
Channel 2 Transmitter
Channel 3 Receiver
Channel 3 Transmitter

Specific Vector Assignments
(F actory-Configured With BV = 300
With Console Selected)
Octal Vector

Interrupt Vector

300
304
310
314
320
324
60

Channel 0 Receiver
Channel 0 Transmitter
Channel 1 Receiver
Channel 1 Transmitter
Channel 2 Receiver
Channel 2 Transmitter
Channel 3 Receiver·
Channel 3 Transmitter·

64
• Console selected

475

M8043
17

o
'--y----J~

FACTORY-CONFIGURED
BASE INTERRUPT VECTOR
ADDRESS = 300
TWOWIREWRAP
POSTS ARE PROVIDED
FOR EACH BIT.
JUMPER IN = 1
JUMPER OUT = 0

CHANNEL
0 = RECEIVER
REQUESTING
INTERRUPT
INTERRUPT 4 = TRANSMITTER
(0-3)
INTERRUPT

1
1
'-----y--l

THREE WIRE WRAP
POSTS ARE PROVIDED
FOR BIT V5.
JUMPER X TO 1 = 1
JUMPER X TO 0 = 0 WITH CONSOLE
NO JUMPER = 0 WITHOUT CONSOLE

OTE:
RANGE 0-377B (040B NOT ALLOWED IN CONSOLE MODE)

Console device jumpers are used to select channels as the console interface. These jumpers (C 1 and C2) will affect address and vector selection.

Summary of Console Selection Jumper Configurations
Label

Console Selected

Console Not Selected

Install jumper from
wirewrap pins
X to 1.

Install jumper from
wirewrap pins
X to o.

Install jumper from
wirewrap pins
X to 1.

Install jumper from
wirewrap pins
X to O.

Configuring Channel Word Formats
Each DL V 11-J SLU channel can be individually configured for number of
data bits (7 or 8); even, odd, or not parity; 1 or 2 stop bits, and baud rate
(described in the next section). A summary of possible character format
jumper configurations is shown below.

476

M8043
Summary of Character Format Jumper Configurations
UART
Label Parameter

X toO

X to 1

Comments
LSB is
transmitted
first

Number of
data bits

7 bits

8 bits

Number of
stop bits

1 bit

2 bits

Parity
inhibit

Parity generation
and detection
enabled

Parity generation
and detection
disabled

Even parity
enabled

Odd parity
enabled

Even parity
enabled

Requires'
P jumper
connected
from X to 0

NOTE
E jumper must be connected to either 0 or 1, even if the parity
bit is disabled. Two stop bits are generally used only with
Teletype terminals.
CAUTION
To prevent hardware damage within the channel, the E jumper
must ALWAYS be installed. This is true regardless of the configuration of the P (parity) jumper.

Baud Rate Selection
NOTE
A 110 baud rate clock generator circuit is contained on the optional DLV11-KA 20 mA option. When 110 baud operation is
desired, do not connect the baud rate jumper on the DLV11-J
module for that particular channel. The 110 baud rate will be
supplied by the DLV11-KA option through the interface connector.

477

M8043
Configure baud rates (except 110 baud) by connecting a jumper from an
appropriate baud rate generator output wirewrap pin to the baud rate clock
input pin (labeled 0-3); one jumper is required for each channel. Baud rate
generator outputs are identified below.
Baud Rate Generator Outputs
Wirewrap
Pin Label

Baud Rate
(Blt/S)

150
300
600
1200
2400
4800
9600
19200
38400

T
V
W
y
L
N
K

NOTE
If more than one channel requires the same baud rate, the
wirewrap jumpers may be daisy-chained.
Channel 3 Break Response
Channel 3 (normally used as the console device) can respond to a break
condition on the receive line such as when an operator presses the BREAK
key on the associated terminal. The BREAK key transmits a continuous
space signal which is detected by the DL V 11-J circuits as a framing error.
If no operation is desired, do not connect jumpers to the B, X, and H wirewrap pins.

Channel 3 Break Operation Jumper Summary
Break
Response
Operation

Jumper Connection

Boot

Install jumper between wirewrap pins X and B.

Halt

Install jumper between wirewrap pins X and H.

No response

No jumper installed.

478

M8043

Summary of Serial Channel Signal Level
Compatibility Configurations
Serial Channel Signal Level
Serial Channel
Signal Level
Modifiers

20 rnA Current
Loop (Required
DLV11-KA Option)

EIA RS-422

EIA RS-232C
and RS-423

MO-3 jumpers

Connect wirewrap pins X
and 2.

Connect wirewrap pins X
and 3.

Connect wirewrap
pins X and 3.

NO-3 jumpers

Connect wirewrap pins X
and 2.

Connect wirewrap pins X
and 3.

Connect wirewrap
pins X and R for
program-controlled
paper tape reader
functionality.

Termination
resistor
(one per
channel)

Install a
100 Q, 1/4
W, non-wirewound, fusible
resistor.

No resistor
installed.

Wave shaping
resistor,
one per channel
pair (channel
pairs 0 and 1;
2 and 3).

Not required.

Install resistor (see next
table). 1/4 W
non-wirewound.

Install 22 K Q
non-wirewound
resistor.

479

M8043
EIA RS-422 - To configure an SLU channel for EIA RS-422 signal levels,
connect the M(MO-M3) and N(NO-N3) jumper wirewrap pin X of the desired
channel to the respective wirewrap pin 2. Install (solder) a 100 ohm, 1/4 W
fusible resistor (non-wirewound) into the termination resistor mounting
pads for the channel being configured. The resistor must be removed for
any configuration other than EIA RS-422.
EIA RS-423 and RS-232C - To configure an SLU channel to be compatible
with both the EIA RS-423 and RS-232C (which on the DL V 11-J are met simultaneously), connect each M(MO-M3) and N(NO-N3) jumper X wirewrap
pin of the desired channel to the respective wirewrap pin 3.
Slew Rates - The signal rise and fall time may be controlled on EIA RS-423
and RS-232C SLU channel configurations by installing (soldering) an appropriate value of non-wirewound, 1/4 W resistor into the wave-shaping resistor pads provided (R 10 and/or R23). An appropriate resistor value can
be selected by referring to the following table. The value of resistor R 10 determines the slew rate of both channels 0 and 1 which are simultaneously
set to the same value. Similarly, R23 controls the slew rate of both channels 2 and 3.

EIA RS-423 and RS-232C Wave-Shaping Resistor Values

Baud Rate

Wave-Shaping Resistor

38.4K
19.2K
9.6K
4.8K
2.4K
1.2K
600.0
300.0
150.0
110.0

22 kQ
51 kQ
120 kQ
200 kQ
430 kQ
820 kQ
1 MQ
1 MQ
1 MQ

See Note.

NOTE
Determined by other channel of the two-channel pair.

480

M8043
20 rnA Current Loop - To configure an SLU channel for 20 rnA current loop
operation, connect the M(MO-M3) jumper pin X to pin 3 for the desired
channel. If the 20 rnA terminal contains a paper-tape reader that can be
program-controlled (such as a DEC-modified L T-33 Teletype or Teletype
ASR-33 with L T22-MD modification kit), connect wirewrap jumper N(NO-N3)
pin X to the respective pin R.
When the DL V 11-KA 20 rnA current loop option is connected to the channel
interface connector, operating power for the option circuits is supplied by
the DL V 11-J. To configure a channel for 110 baud operation, enable the
110 baud rate clock on the DL V 11-KA option and remove the baud rate selector jumper for the channel on the DL V 11-J module. The clock needed by
the DL V 11-J is automatically supplied through the serial line connector
cable.

481

M8043

DLV11-J TO MODEM OR ACOUSTIC COUPLER

_gl

tDLV11 J f f i - '50FT

BC20M-50~~~~~~J..g DLV11-J)

DLV11-J TO LOCAL TERMINAL
14FT

-~-9FT~l!l
(NOTE 2)

NOTES:
1. MODEM USED IS A "MANUAL TYPE" SUCH AS BELL 103A WITH B04B.
2. DEC EIA RS·232C TERMINALS (VT52, LA36, LS120, ETC.) COME EQUIPPED
WITH A 9 FT CABLE. NON-DEC EIA RS·232C TERMINALS ARE CONNECTED
SIMILARLY EXCEPT 9 FT OF LENGTH MUST BE DEDUCTED FROM THE
TOTAL CABLE LENGTH.

DL V 11-J Cabling Summary

482

M8043

2 X 5 PIN AMP NO 87133-5
RECEPTACLE

:1~

8
10

STANDARD EIA RS-232C
25 PIN CONNECTOR

~-------------5FT------------~

(SEE NOTE)
7
9 L -_ _ _-L..-'

NOTE:
CABLE RETENTION IN DLV11-J CONNECTOR
IS PROVIDED BY" LOCKING PINS". PULL
BACK ON THE RECEPTACLE TO SLIDE OUT
OF DLV11-J CONNECTOR. HOWEVER, IF THE
CABLE IS PULLED, THE "LOCKING PINS"
HOLD THE RECEPTACLE FIRMLY IN THE
DLV11-J CONNECTOR.

o
GROUND SHIELD (ATTACH TO CHASSIS)

INDEX KEY

( 5 ( - - , CLEAR TO SEND (CB)
I

4(--...1 REQUEST TO SEND (CA)

RCV DATA - >7

6(--, DATA SET READY (CC)
I
I
~10>-l~-I---------------"";';;;"-'-I""'1\,I-<20(--...1 DATA TERMINAL READY (CD)
+12 VDC

RCV DATA + > 8 >--i!--+-----------------t--_t__( 3 < R ECE I V ED DATA (BB)
XMIT DATA + > 3 >-I~-I---------------I-__I__< 2< TRANSMITTED DATA (BA)
GAD> 2 >-1--1-------------11--+-< 7 < SI GNA L G ROUN D (AB)

,)J---------II--+-< 1 <
DLVll-J MODULE

CONNECTOR

CABLE

EIA
RS-232C
CONNECTOR

PROTECTIVE GROUND (AA)
MODEM

BC21B-05 Peripheral Device Cable

483

M8043

BC21B-05
L-__________~~4r-----------5FT------------~--------~

NOHS:

CD MODEM OR ACOUSTIC COUPLER.
MODEMS SHOWN ARE "MANUAL" MODEMS
SUCH AS BELL 103A DATA SETS WITH B04IB
AUXILIARY SET.

o =2NECTORS
X 5 PIN AMP NO B7133-5 CON-

~ = EIA RS-232C 25 PIN MALE CONNECTORS

~ = EIA RS-232C 25 PIN FEMALE CONNECTORS

DL V 11-J to Modem or Acoustic Coupler

484

M8043

TERMINAL

..
BC20N-05
"NULL MODEM"
CABLE

~4r-------9FT------~~1

TERMINAL

NOTES
TERMINALS SHOWN ARE DEC EIA RS-232C
TERMINALS (SUCH AS VT52, LA36, LS120,
ETC.)
DEC TERMINALS ARE CONSTRUCTED WITH 9
FOOT CABLES, WHEN USING NON-DEC EIA
RS-232C TERMINALS DEDUCT 9 FEET FROM
THE TOTAL CABLE LENGTH.

[6J = 2 X 5 PIN AMP NO 87133-5 CONNEC·
TORS

~= EIA RS-232C 25 PIN MALE CONNECTORS

~= EIA RS-232C 25 PIN FEMALE CONNECTORS
MR-1282

Local Terminal Cabling

485

M8043

CONNECT TO CHASSIS
GROUND

10
~-------------50FT------------~

2 X 5 PIN AMP NO 87133·5 RECEPTACLE

INDEX KEY

INDEX KEY
NOTE
BOTH CONNECTORS HAVE THE SAME CABLE
RETENTION MECHANISM. CABLE RETEN·
TION IS PROVIDED 8Y "LOCKING PINS".
PULL ON RECEPTACLE TO RELEASE.

BC20M-50 DL V 11-J to DL V 11-J Cable

BCOlV-25
OR
BC05C-25

= 2 x 5 PIN AMP NO 87133·5 CONNECTORS

= EIA RS·232C 25 PIN MALE CONNECTORS

= EIA RS·232C 25 PIN FEMALE CONNECTORS

= 40 PIN BERG MALE CONNECTORS

= 40 PIN BERG FEMALE CONNECTORS

DL V 11-J to SLU Module Cabling

486

M8044/45

M8044/45
MSV11-D, -E MOS READ/WRITE MEMORY

Model

Memory Capacity

Module

Parity Bits

MSV11-DA
MSV11-DB
MSV11"DC
MSV11-DD
MSV11-ED

4K by 16 bits
8K by 16 bits
16K by 16 bits
32K by 16 bits
32K by 18 bits

M8044-AA
M8044-BA
M8044-CA
M8044-DA
M8045-DA

No
No
No
No
Yes

Amps

Bus loads

Cables

AC
2

None

+5
2.0

+ 12
0.41

Standard Addresses
Module is shipped configured to start at bank O.

Vectors
None

Diagnostic Programs
Refer to Appendix A.
NOTE
DEC diagnostic will not check parity.

Related Documentation
MSVll-0, -£ User's Manual (EK-MSV1D-OP)
Field Maintenance Print Set (MP00259)
Microcomputer Processor Handbook (EB-18451-20)

487

M8044/45
Address Selection
The MSV 11-D or MSV 11-E address can start at any 4K bank boundary. The
address configured is the starting address for the contiguous portion of
memory (4K, 8K, 16K, or 32K) contained on the module.

ADDRESS
SWITCHES

{IJ~~=~

MEMORY (
SIZE

5"
7e1.

SEE NOTE 1

S1-1

S1-4

•••
•••

S1-5
12 14 10

PARITY/NO
PARITY
OPERATION

17 15 16

SEE NOTE 2

NOTES:
1. JUMPER 1 TO 2 = 30K OPTION (MINC) 1 TO 3 FOR NO 30K OPTION
2. JUMPER 5 TO 7 FOR MSV11-D OR 5 TO 6 FOR MSV11-E

MSV 11-D, MSV 11-E Switch and Jumpers M8044,45

Set the switches to the desired starting address as listed in the table. Note
that the module is designated to accommodate a 128K system addressing
capability. However, the present addressing capability of the LSI-11 system, including all PDP-11 /03, PDP-11 V03 and PDP-11 T03 systems, is 32K.
PDP-11/23 systems, however, can address within the full 128K word
range. By PDP-11 convention, the upper 4K address space is normally reserved for peripheral device and register addresses. Thus, with the present
LSI-11 maximum addressing capability of 32K, bank 7 (address
160000-177777) normally should not be used for system memory.

488

M8044/45
Factory-configured modules will not respond to bank 7 addresses. In special applications that permit the use of the lower 2K portion of bank 7 for
system memory (i.e., MINC), enable the lower 2K portion of bank 7 by removing the jumper from wirewrap pins 1 and 3 and connecting a new jumper from 1 to 2.

NOTE
If 30K option is enabled, some diagnostics may not run.

Battery Backup Power
MSV 11-0 and MSV 11-E modules are factory configured with power jumpers
installed for normal system power only. If the system uses a battery backup
power source, remove jumpers W2 and W3. Install new jumpers W4 and
W5. (Two jumpers are removed and two new jumpers are installed.)
Parity
One jumper is factory installed for nonparity (MSV 11-0) or parity (MSV 11E) operation, depending on the model. 00 not reconfigure this jumper.
Standard jumper configurations are listed below.
• All MSV 11-0 models: jumper installed from pin 7 to pin 5.
• All MSV 11-E models: jumper installed from pin 6 to pin 5.

NOTE
This memory parity feature is not supported by DEC diagnostics or CPUs.

Memory Size
Two jumpers are factory installed to configure addressing logic for memory
size (number and type of memory-integrated circuits). 00 not reconfigure
these jumpers. Standard jumper configurations are listed below.

Models

Jumpers (Two Installed)
Memory· Select Pins
Memory Range Pins

MSV11-0A
MSV11-0B
MSV11-0C
MSV 11-00, EO

From 17 to 14
From 12 to 14
From 16 to 14
From 10 to 14

489

From 17 to 15
From 17 to 15
From 16 to 15
From 16 to 15

MSV11-D, MSV11-E Addressing Summary
Switch Settings

MSV11-DA,
MSV11-EA

4K Memory Bank(s) Selected
MSV11-DB,
MSV11-DC,
MSV11-EB
MSV11-EC

MSV11-DD,
MSV11-ED

N
F
N
F
N

0
1
2
3
4

0-1
1-2
2-3
3-4
4-5

0-3
1-4
2-5
3-6
4-7

0-7
1-10
2-11
3-12
4-13

N
F
F
N
N

F
N
F
N
F

5
6
7
10
11

5-6
6-7
7-10
10-11
11-12

5-10
6-11
7-12
10-13
11-14

5-14
6-15
7-16
10-17
11-20

N
N
F
F
F

F
F
N
N
F

N
F
N
F
N

12
13
14
15
16

12-13
13-14
14-15
15-16
16-17

12-15
13-16
14-17
15-20
16-21

12-21
13-22
14-23
15-24
16-25

F
N
N
N
N

F
N
N
F
F

F
N
F
N
F

17
20
21
22
23

17-20
20-21
21-22
22-23
23-24

17-22
20-23
21-24
22-25
23-26

17-26
20-27
21-30
22-31
23-32

Starting
Address

S1-1 S1-2 S1-3 S1-4 S1-5

0
20000
40000
60000
100000

N
N
N
N
N

N
N
N
N
F

N
N
F
F
N

120000
140000
160000
200000
220000

N
N
N
N
N

N
N
N
F
F

F
F
F
N
N

240000
260000
300000
320000
340000

N
N
N
N
N

F
F
F
F
F

360000
400000
420000
440000
460000

N
F
F
F
F

F
N
N
N
N

MSV11-D, MSV11-E Addressing Summary (Cont)

MSV11-DA,
MSV11-EA

4K Memory Bank(s) Selected
MSV11-DB,
MSV11-DC,
MSV11-EB
MSV11-EC

MSV11-DD,
MSV11-ED

N
F
N
F
N

24
25
26
27
30

24-25
25-26
26-27
27-30
30-31

24-27
25-30
26-31
27-32

24-33
25-34
26-35
27-36
30-37

N
F
F
N
N

F
N
F
N
F

31
32
33
34
35

31-32
32-33
33-34
34-35
35-36

31-34
32-35
33-36
34-37

X
X
X
X
X

F
F

N
F

36
37

36-37

X
X

Switch Settings
Starting
Address

S1-1 S1-2 S1-3 S1-4 S1-5

500000
520000
540000
560000
600000

F
F
F
F
F

N
N
N
N
F

F
F
F
F
N

N
N
F
F
N

620000
640000
660000
700000
720000

F
F
F
F
F

N
N
N
F
F

740000
760000

F
F

NOTES
1.

Switch settings:
N = ON
F = OFF

In unmapped systems, bank 7 cannot be selected as factory configured; however, the user can enable the lower
2K portion of bank 7.

X = Do not use.

30~33

M8047

M8047
MXV11-AA/AC MULTIFUNCTION MODULE

The MXV 11 is a multifunction option module used for the LSI-11, LSI-11 /2,
or LSI-11 /23 systems. It contains read/write memory provisions for readonly memory, two asynchronous serial line interfaces and a 60 Hz clock
derived from a crystal oscillator.
Detailed technical information is beyond the scope of this document. Additional information can be found in the Microcomputer Processor Handbook,
EB-18451-20.

Model Designations
•

MXV11-AA contains 8K bytes of random access memory .

•

MXV 11-AC contains 32K bytes of random access memory.

Both models have two 24-pin sockets that provide for
5 V read-only memories in which 1K X 8, 2K X 8, or 4K X 8 ROMs may be used. These sockets may also be used for 256 words of bootstrap code.

Amps

+ 12

1.2

0.1

Bus Loads

Cables

AC
2

BC20M-XX
BC20N-XX (Refer to DL V 11-KA)
BC21B-XX

DC
2

Standard Addresses
RAM - Starts on any 8K boundary below 64KB.
SLU

Channel 0
176500

Channel 1
177560

Standard Vectors
SLU

300

60
493

M8047
Diagnostic Programs
Refer to Appendix A.
Requires wraparound connectors to completely exercise SLU.

Options
MXV 11-A2 Boot ROMs for RX02, RXO 1, or TU58
PNs: 23-03901-00, 23-04001-00

ROMs
Power:

+5 V ± 5%

Pins:

24-Pin DIP

Access Time:

Up to 450 nanoseconds

Array Size:

1K X 8, 2K X 8, or 4K X 8 bits

Type:

Typical PROM types:

UV PROMs

Chip
Array Size

Memory Size

Intel 2758
Intel 2716
Intel 2732
Mostek MK27 16
T.I. TMS 2516
T.I. TMS 2532

1K X 8 bits
2K X 8 bits
4K X 8 bits
2K X 8 bits
2K X 8 bits
4K X 8 bits

1K words
2K words
4K words
2K words
2K words
4K words

1K X 8 bits
1K X 8 bits
1K X 8 bits
2K X 8 bits

1K words
1K words
1K words
2K words

Bipolar PROMs
Intel 3628
Signetics 82S 2708
Signetics 82S 181
Signetics 82S 191

494

M8047

CHANNELl
J66 J65
.A..A.

J68.A.
J67.A.

/!t\~

J64 J63 J62 J6l J60 J59

.A.J58
.A. J57
.A. J56
.A.J55
.A.J54
.A.J53
.A.J52
.A.J5l
.A. J50
.A. J49
.A.J48
.A.J47
.A.J46
.A.J45
.A. J44
.A. J43
.A. J42
.A. J41

.A.J40
.A. J39
.A.J38
.A.J37
.A. J36
.A.J35
.A.J34
.A.J33
.A.J32
.A.J3l
.A.J30

.A. J29
.A. J28
.A.J27
.A. J26
.A.J25
.A.J24
.A.J23
.A. J22
.A. J2l
.A.J20
.A.J19
.A.J18
.A.J17
.A.J16
.A.J15
.A.J14
.A.J13
.A. J12
.A.Jll
.A.Jl0
.A.J9
.A.J8
J7
.A.
.A..A. .A..A.
J6 J5 J4 J3

MXV 11-A Jumper Locations

495

M8047
MXV11-A Jumper Functions
Pin

Function

Option

Clock L. Open collector output of the clock.
Connected to pin AF 1 (SSpare 2). Wirewrap to J4
to implement the clock option.

60 Hz

BEVNT L. Event interrupt (pin BR 1) used for the
clock option.

60Hz

BOCOK H. OCOK (pin BA 1) when high allows the processor to operate; when low initializes the system.
Connected to J6 to use the boot option.

Boot

Framing Error. Open collector output of framing
error from serial line one. Connected to pin AE 1
(SSpare 1). Wirewrap to J5 to implement the boot
option. Reset by bus initialize or reception of
a valid character.

Break

BHAL T L. Halt (pin AP 1) when low will stop program execution and cause the processor to enter
OOT microcode. Connected to J6 to implement the
halt option.

Halt

GNO. A ground signal that can be used to disable
ROM by wirewrapping to J21 or to disable a serial
line by wirewrapping to an address input pin (J23
or J24 for serial line 0; or J25, J26, J27, or J28
for serial line 1).

ROM

A 13 L. Address bit 13 asserted low. Wirewrap to
J 11 to select bank 1 with the ROM address decoder.

ROM

J10

A 13 H. Address bit 13 asserted high. Wirewrap to
J 11 to select bank 0 with the ROM address decoder.

ROM

J 11

A 13 M. Address bit 13 input to the ROM address
decoder. See J9 and J 1O. Used only if J20 is
wirewrapped to J21.

ROM

J12

A03 H. Address bit 03 asserted high. Wirewrapped
to the serial line address decoders (J23 or J24 for
serial line 0, J25, J26, J27 or J28 for serial line
1) when address bit 03 is to be decoded as a 1.

SLU

496

M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J13

A04 H. Address bit 04 asserted high. Wirewrapped
to the serial line address decoders when address
bit 04 is to be decoded as a 1.

SLU

J14

A05 H. Address bit 05 asserted high. Wirewrapped
to the serial line one address decoder when address
bit 05 is to be decoded as a 1.

SLU

J15

A09 H. Address bit 9 asserted high. Wirewrapped
to the serial line one address decoder when address
bit 09 is to be decoded as a 1.

SLU

J16

A09 L. Address bit 09 asserted low. Wirewrapped
to the serial line one address decoder when address
address bit 09 is to be decoded as a O.

SLU

J17

A05 L. Address bit 05 asserted low. Wirewrapped
to the serial line one address decoder when address
bit 05 is to be decoded as a O.

SLU

J18

A04 L. Address bit 04 asserted low. Wirewrapped
to the serial line address decoders when address
bit 04 is to be decoded as a O.

SLU

J19

A03 L. Address bit 03 asserted low. Wirewrapped
to the serial line address decoders when address
bit 03 is to be decoded as a O.

SLU

J20

ROM address. Output of the ROM address decoder.
Connected to J21 when ROM is to be used in bank 0
or bank 1.

ROM

J21

ROM select. ROM address selection enable asserted
high. Wirewrapped to J8 (GND) to disable ROM, to
J20 for bank 0 or bank 1, or to J22 for bootstrap.

ROM

J22

Boot address. Output of the bootstrap address
decoder. Connected to J21 when ROM is to be used
in the bootstrap range from 173000-173776 (773000773776 for LSI-11 /23).

BOOT

J23

Serial line 0 address decoder input asserted high.
May be wirewrapped to A03 H (J 12), A03 L (J 19),
A04 H (J13), or A04 L (J18).

SLU

497

M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J24

Serial line 0 address decoder input asserted high.
May be wirewrapped to A03 or A04, whichever bit is
not wired to J23. May be wirewrapped to GND (J8)
to disable serial line o.

SLU

J2SJ28

Serial line 1 address decoder input asserted high.
Four address decoder inputs to be connected to
address bits A03, A04, AOS, and A09. Whether the
high or low assertion state of a bit is wirewrapped
to an input determines if that bit is decoded as a
1 or a o. See J 12 through J 19. May be wirewrapped
to GND (J8) to disable serial line 1.

SLU

J29

ROM address bit 09 input. Wirewrapped to A09 H
(J 15) for normal ROM addressing and also for the
MXV 11-A2 option when the TUS8 bootstrap is desired.
Wirewrapped to A09 L (J 16) for the MXV 11-A2 option
when the disk bootstrap is desired.

ROM

J30J32

RAM starting address selection. These pins are
wirewrapped to J33 (logic 0) or J34 (logic 1) to
select the RAM starting address (see the following).

RAM

J32

J31

J30

Bank

Starting
Address

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
2
3
4
5
6
7

000000
020000
040000
060000
100000
120000
140000
160000

J33

GND. Logic 0 level signal used for selecting the
RAM starting address and for enabling some ROM IGs
in the ROM sockets.

RAM,
ROM

J34

+3 V. Logic 1 level signal used for selecting the
RAM starting address and for enabling some ROM IGs
in the ROM sockets.

RAM,
ROM

498

M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J35

A 12 H. Address bit 12 asserted high. Used for
addressing 4K X 8 bit ROMs. Wirewrapping to J37,
J38 or J39, depending on the ROM used.

ROM

J36

A 11 H. Address bit 11 asserted high. Used for
addressing 2K X 8 and 4K X 8 bit ROMs. Wirewrapping to J37, J38, or J39, depending on the ROM.

ROM

J37

Pin 18 on both ROM sockets. Used for addressing
or enabling ROM. Wirewrapped to J33 for ground,
to J34 for + 13 V, to J35 for A 12, or to J36 for A 11.

ROM

J38

Pin 19 on both ROM sockets. Used for addressing
or enabling ROM. Wirewrapped to J33 for ground,
to J34 for +3 V, to J35 for A 12, or to J36 for A 11.

ROM

J39

Pin 21 on both ROM sockets. Used for addressing
or enabling ROM. Wirewrapped to J33 for ground,
to J34 for + 3 V, to J35 for A 12 to J36 for A 11 or
to J40 for +5 V.

ROM

J40

+ 5 V. Used to power some ROMs on pin 21.

ROM

J41

Used for 150 baud. Wirewrapped to J45 for serial
line 0, to J46 for serial line 1. (See following
table.)

SLU

J42

Used for 1200 baud.

SLU

J43

Used for 300 baud.

SLU

J44

Used for 2400 baud.

SLU

J45

Clock O. The clock input for serial line 0 transmit
and receive, 16 times the baud rate. Wirewrapped to
either J41, J42, J43, J44, J47, J48, J49, or J50.

SLU

J46

Clock 1. The clock input for serial line 1 transmit
and receive, 16 times the baud rate. Wirewrapped to
either J41, J42, J43, J44, J47, J48, J49, or J50.

SLU

J47

Used for 4800 baud.

SLU

J48

Used for 9600 baud.

SLU

499

M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J49

Used for 19.2K baud.

SLU

J50

Used for 38.4K baud.

SLU

J51

Vector o. Vector enable for channel o. Used to
drive vector bits that pass the test: logic 1 for
channel 0, and logic 0 for channel 1. Wirewrapped
to J53 for bit 03, to J54 for bit 04, to J55 for
bit 05, to J56 for bits 06 and 07.

SLU

J52

Vector 1. Vector enable for channel 1. Used to
drive vector bits that pass the test: logic 0 for
channel 0 and logic 1 for channel 1. Wirewrapped
to J53 for bit 03, to J54 for bit 04, to J55 for
bit 05, to J56 for bits 06 and 07.

SLU

J53

Vector bit 03. Selects how bit 03 is to be driven
for interrupt vectors. Wirewrapped to J51 if a
logic 1 for channel 0 and a logic 0 for channel 1;
to J52 if a logic 0 for channel 0 and a logic 1 for
channel 1; to J57 if a logic 0 for both channel 0
and channel 1; or to J58 if a logic 1 for both
channel 0 and channel 1.

SLU

J54

Vector bit 04. Selects how bit 04 is to be driven
for interrupt vectors. Wirewrapped the same as J53.

SLU

J55

Vector bit 05. Selects how bit 05 is to be driven
for interrupt vectors. Wirewrapped the same as J53.

SLU

J56

Vector bits 06 and 07. Selects how bits 06 and 07
are to be driven for interrupt vectors. Wirewrapped the same as J53.

SLU

J57

GND. Logic 0 signal for configuring vector bits.
Wirewrapped to J53, J54, J55 and/or J56 when the
corresponding vector bites) will be logical 0 for
both serial line channels.

SLU

J58

+3 V. Logic 1 signal for configuring vector bits.
Wirewrapped to J53, J54, J55 and/or J56 when the
corresponding vector bites) will be logical 1 for
both serial line channels.

SLU

500

M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J59

Seven bits parity, eight bits no parity, channel 1.
Wirewrapped to ground (J65) for seven bits with
parity or to + 3 V (J66) for eight bits with no
parity.

SLU

J60

Two stop bits. Selects one or two stop bits for
channel 1. Wirewrapped to ground (J65) for one
stop bit or to + 3 V (J66) for two stop bits.

SLU

J61

Even parity. Selects odd or even parity for
channel 1 when seven bits with parity (J59 wirewrapped to ground) is selected. Wirewrapped to
ground (J56) for odd parity or to + 3 V (J66) for
even parity.

SLU

J62

Seven bits parity, 8 bits no parity, channel O.
Wirewrapped to ground (J65) for seven bits with
parity or to + 3 V (J66) for eight bits with no
parity.

SLU

J63

Two stop bits. Selects one or two stop bits for
channel O. Wirewrapped to ground (J65) for one
stop bit or to + 3 V (J66) for two stop bits.

SLU

J64

Even parity. Selects odd or even parity for
channel 0 when seven bits with parity (J59 wirewrapped to ground) is selected. Wirewrapped to
logic 0 (J65) for odd parity or to logic 1 (J66)
for even parity.

SLU

J65

Logic O. Ground signal used for configuring
serial line interfaces.

SLU

J66

Logic 1. + 3 V signal used for configuring line
interfaces.

SLU

J67

Clock in. Clock input for baud rates, memory
refresh and negative voltage generator. Wirewrapped to J68. Not a user option.

SLU

J68

Clock out. Crystal oscillator output at 19.6608
MHz. Wirewrapped to J67. Not a user option.

SLU

501

M8047
Standard Factory Configuration
Wirewrap
From

Pins
To

Wirewrap
Level

RAM Bank 0

J30
J32
J31

J31
J33
J32

L1
L1
L2

SLU Channel 0 Address 176500

J23
J24

J18
J19

L1
L1

SLU Channel 1 Address 177560

J28
J26
J25
J27

J19
J15
J14
J13

L2
L1
L1
L1

ROM Bootstrap (TU58)

J37
J21
J34
J33
J29

J38
J22
J37
J39
J15

L1
L1
L2
L2
L2

SLU Vectors CHO (300)
CH1 (60)

J53
J54
J56
J54

J57
J52
J51
J55

L1
L1
L1
L2

SLU Parameters (8 Data Bits,
No Parity, 1 Stop Bit)

J59
J62
J60
J61
J59
J63

J61
J64
J63
J62
J66
J65

L1
L1
L2
L2
L2

Baud Rates CHO (38.4K)
CH1 (9600)

J45
J46

J50
J48

Break Generation
(Halt Option)

Crystal Clock

J68

J67

Function

502

M8047
Configuring the RAM
The RAM can be configured to start on any 8KB boundary below 64KB. Because of this restriction, the MXV 11 (8KB version) is not usable for memory
above 56KB. The MXV 11 can be used in 18-bit memory address systems,
but it is restricted to being assigned to the memory area at or below 56KB.
Five wirewrap terminals, J30 through J34, select the starting address. The
following figure shows the jumper configurations required to obtain the desired starting addresses.
17

a :

J3< J3< J30

1a 1a Ia _

FACTORY CONFIGURED

1 = CONNECT JUMPER TO J34
2 = CONNECT JUMPER TO J33

RAM Starting Address Selection

Configuring the ROM
Depending on the ROM type, the module's capacity is 1K, 2K, or 4K words
using a pair of 1024 X 8-, 2048 X 8-, or 4096 X 8-bit ROMs respectively.
The user configures jumpers on the module for the ROM type being used.
The actual procedure for loading data into EPROMs, PROMs (or writing
specifications for masked ROMs) will vary depending on the manufacturer,
and is beyond the scope of this section. The user must refer to the manufacturer's data sheets and to the chapter, "Using PROMs" in the Microcomputer Processor Handbook, EB-18451-20. The user must be aware of
the relationship of the EPROM, PROM, or ROM pins to the LSI-11 data bits,
and the relationship of the pins to the memory address bits. Refer to the
following figure for ROM socket pin assignments. All ROMs used on the
MSV 11-A must conform to these pin assignments.
The factory configuration allows for using the MSV 11-A2 bootstrap ROMs.

Configuring the Bootstrap ROM - The ROM can be configured to operate
in the I/O page to support bootstrap programs. The address area contains
256 words from 173000 to 173776 (773000 to 773776 for the LSI-11 /23).
The MXV 11-A is configured at the factory to allow for using the MXV 11-A2
TU58 bootstrap. To reconfigure the MXV 11-A to use the disk bootstrap, remove jumper J29 to J 15 and install jumper J29 to J 16.

503

M8047
A08 H
23 [J------r.)(IJ29

A07 H
A06 H

21 L J - - - - { ) ( ] J39

A05 H
A04 H

U---~)(]J38

A03 H
A02 H

AOI H

(008 H) 000 H

~---f')(lJ37

(009 H) 001 H

(010 H) 002 H

GNO

NOTE:
DATA OUT PINS SHOWN IN PARENTHESES
REFER TO THE HIGH 8YTE SOCKET XE67.
DATA OUT PINS 000 H THROUGH 007 H
REFER TO THE LOW 8YTE SOCKET XE57.

MXV 11-A ROM Socket Pin Assignment

ROM Bank Selection - If the MXV 11-A sockets are used for program ROM
instead of a bootstrap ROM, the memory must be selected by a jumper connecting J20 to J21. When main ROM memory is selected, the entire 4K
word bank is enabled. If a 1K or 2K ROM is used, it will "wraparound" and
give invalid data, depending on how the address lines are configured when
the nonexisting ROM area is addressed. Main memory may be positioned in
bank 0 or bank 1. To position the ROM in bank 0, jumper J 10 to J 11. To
position the ROM in bank 1, jumper J9 to J 11.

Configuring the Specific ROM Types - Additional jumpers must be connected depending on the type of ROM used. The "EPROM Address Jumpers" table describes the jumper configuration when using typical ROMs
such as the Intel 2716 (2K X 8) or 2732 (4K X 8) EPROMs. The user must
refer to the manufacturer's data sheets when configuring jumpers for other
ROM types.
The function of wirewrap pins J29, J38, J37, and J39 are shown in the following table. These pins are to be connected as required to pins J33
through J40.

504

M8047
EPROM Address Jumpers
2716 ROM

Function

Bank 0
From to

Bank Enable
Bit 09 Input
Address or Enable
Address or Enable
Address or Enable

J20
J29
J38
J37
J39

J21
J15
J36
J33
J40

2732 ROM

Bank 1 BankO Bank 1
to
to
to
J21
J15
J36
J33
J40

J21
J15
J36
J35
J33

J21
J15
J36
J35
J34

CONFIGURING THE SERIAL LINE UNITS
Serial Line Register Address Selection
Four device registers (RCSR, RBUF, XCSR, and XBUF) are provided for
each of the two serial lines. Jumpers are configured to establish separate
base addresses for each serial line as shown.
• Serial port 0 may be assigned to one of the four starting addresses:
176500, 176510, 176520, 176530.
• Serial port 1 may be assigned addresses in two ranges. The first range
starts at 176500 and covers the eight starting addresses from 176500
to 176570. The second range starts at 177500 and also contains eight
possible starting addresses, including the standard console address,
177560. Since several other standard DIGITAL devices use addresses
in this second range, it is recommended that only the console address
be used.
The format of an SLU address is shown in the following figure. Note that bits
13- 17 are neither configured nor decoded by the MXV 11-A module. These
bits are decoded by the bus master module as the bank 7 select (BBS7 L)
bus signal. This signal becomes active only when the I/O page is accessed. Bit 0 is used as the byte pointer.
00 = RCSR
01 = RBUF
10 = XCSR
11 = XBUF

1 = RANGE 2
0= RANGE 1

BAN K SE LECT 7

NOTE:
JUMPER POSTS ARE WIRED TO A HIGH
ADDRESS LINE FOR A 1 AND TO A LOW
ADDRESS LINE FOR A O. REFER TO
TABLES 7 AND B FOR JUMPER CONFIGU·
RATIONS.

.----"----,

SERIAL LINE 0
J26

SERIAL LINE 1

J2&

MXV 11-A SLU Address Format
505

M8047
Bits 1 and 2 select one of the four device registers within the addressed
serial line. Bits 3 and 4 are used to select one of four possible device addresses for serial line O. Bits 3, 4, 5, and 9 are used to select the device
addresses in two ranges for serial line 1 (console). The following table describes the jumper combinations to select one of four device addresses for
serial line 0 (I/O).
Serial Line 0 Address Jumpers
Address
(Octal)

Jumper Posts
J23 to
J24 to

176500

J 18 (Logic 0)

J 19 (Logic 0) Factory Configuration

176510

J 18 (Logic 0)

J 12 (Logic 1)

176520

J13 (Logic 1)

J19 (Logic 0)

176530

J13 (Logic 1)

J12 (Logic 1)
NOTE

Logic 1
J13 (A04 H)
J12 (A03 H)

Logic 0
J18 (A04 L)
J19 (A03 L)

Serial line 1 may have 16 possible device addresses in two ranges. The
following table describes the jumper combinations to select the eight device registers available in range 1. Only one device address is used in
range 2.
Serial Line 1 Address Jumpers
Address
(Octal)
Range 1

J26
to

Jumper Posts
J25
J27
J28
to
to
to

176500
176510
176520
176530
176540
176550
176560
176570

J16
J16
J16
J16
J16
J16
J16
J16

J17
J17
J17
J17
J14
J14
J14
J14

J18
J18
J13
J13
J18
J18
J13
J13

J19
J12
J19
J12
J19
J12
J19
J12

J15

J14

J13

J19

Range 2
177560

(See the following Note.)
506

M8047
NOTE
Factory configurations use only one address in range 2 to
avoid possible device conflicts. The remaining addresses are
pre-assigned to other devices.

Logic 1
J1S (A09 H)
J14 (AOS H)
J13 (A04 H)
J12 (A03 H)

Logic 0
J16 (A09 L)
J17 (AOS L)
J18 (A04 L)
J19 (A03 L)

Control/Status Register
The MXV 11-A has two control/status registers (CSRs) for each of its two
serial line units. The following figure shows the control/status registers
and the read/write data registers. Transmitter control/status registers 0
and 1 (XCSRO and 1) and receiver control/status registers 0 and 1 (RCSRO
and 1) operate with serial lines 0 and 1, respectively.

Both serial line units have the same bit assignments. There are four registers for each serial line. They are sequential in this order: 0, receiver status; 2, receiver data; 4, transmitter status; and 6, transmitter data. All
unused bits are read as O.

507

M8047

RCSR

(NOT USED)

RECEIVER
DONE
(READ ONLY)
RECEIVER
INTERRUPT
ENABLE
(READIWRITE)

RBUF

RECEIVE DATA
(7,8 BIT DATA IS RIGHT JUSTIFIED.)
IF BIT UNUSED = 0
(READ ONLY)

XCSR

(NOT USED)

TRANSMIT
READY
(READ ONLY)

TRANSMIT BREAK
(READIWRITE)

TRANSMIT
INTERRUPT
ENABLE
(READIWRITE)

XBUF

: I

I : : : : :

(NOT USED)

TRANSMIT DATA
(7, B BIT DATA IS RIGHT JUSTIFIED.)
(WRITE ONLY) ON READ = 0

NOTE
ONE OF FOUR CHANNELS SHOWN.
FORMAT THE SAME FOR ALL CHANNELS,

MXV11-A SLU CSR Formats

508

M8047
Bit Assignments for the Receiver Status Register
Bit

Function

Interrupt enable, read/write. A 1 enables receiver interrupts, a 0
disables interrupts. Cleared by initialize.

Receiver done, read only. A 1 indicates that the serial interface
has received a character. If enabled by bit 6, receiver done will
request an interrupt. Receiver done is cleared by reading the receiver data register or by initialize.

0-7

Data bits, read only. Bit 0 is the least significant bit and bit 7 is
the most significant. If seven data bits plus parity is selected, bit
7 will always read as a o.

Parity error, read only. A 1 indicates that the word being read in
bits 0 through 6 has a parity error. Bit 12 will always read 0 when
eight data bits and no parity are selected. Cleared when read, or
by initialize.

Framing error, read only. A 1 indicates that a start bit was detected, but there was no corresponding stop bit. A framing error
will be generated when a break is received. Cleared when read,
or by initialize.

Overrun error, read only. A 1 indicates that a word in the receiver
buffer had not been read when another word was received and
placed in the receiver buffer. Cleared when read, or by initialize.

Error, read only. A 1 indicates that one or more of bits 12, 13, and
14 are 1. Cleared when read, or by initialize.

509

M8047
Bit Assignments for the Transmitter Status Register
Bit

Function

Break, read/write. When set to a 1, bit 0 causes the serial output
signal to go to a space condition. A space condition longer than
a character time causes a framing error when it is received and
is regarded as a break. Cleared by writing a 0, or by bus initialize.

Interrupt enable, read/write. A 1 enables transmitter interrupts; a

o disables interrupts. Cleared by initialize.
7

Transmitter ready, read only. A 1 indicates that the serial interface is ready to accept a character into the transmitter data register. If enabled by bit 6, transmitter ready will request an interrupt. Transmitter ready is cleared when data is written into the
transmitter data register. It is set by initialize.

0-7

Data bits, write only. Bit 0 is the least significant bit and bit 7 is
the most significant bit. If seven data bits plus parity are selected, bit 7 will not be transmitted. The transmitter data register
will read all Os.

Interrupt Vector Selection
Two consecutive interrupt vectors (one for receive and one for transmit)
are provided for each of the two serial lines. The interrupt vector format is
shown in the following figure. Each SLU port can be independently configured to operate in one of two ranges: 000 to 074, or 300 to 376.

NOTE
BITS 3 THROUGH 7 MAY BE WIRED
TO ONE OF FOUR WIREWRAP POSTS
J51 (VEe 0), J52 (VEe 1), J57 (GNDI
OR J58 (+3 VI

J56'

J55

J54

J53

1 = TX
2 = Rev

MXV 11-A Interrupt Vector Format
The following table lists the vector addresses that may be assigned to the
serial lines. Note that all vector addresses in the 000 to 074 range, except
060, are reserved vector locations. The jumper selectable bits are 3
through 7. Bits 6 and 7 are wired together.

510

M8047
Serial Line Vector Addresses
Serial Line 1 (Console)

Serial Line 0 (I/O)

000
010
020 DIGITAL Reserved
030 Do not use
040
050
060 Console
070 DIGITAL Reserved

300
310
320
330
340
350
360
370

The following example illustrates the procedure for configuring the vector
addresses. Assume that 60 is the address for serial line 1 (console) and
310 is the address for serial line 0 (I/O). The example describes the relationship between the vector bases, vector address bits, and the jumper
posts. The jumpers are configured using the following four rules.
1. If a bit =

1 in both vector bases, it is tied to J58 (logic 1).

2. If a bit = 0 in both vector bases, it is tied to J57 (logic 0).
3. If a bit = 1 for serial line
(vector 1).

and a 0 for serial line 0, it is tied to J52

4. If a bit = 0 for serial line
(vector 0).

and a 1 for serial line 0, it is tied to J51

Interface Connector Pins
Two 10-pin connectors (one for each serial line) are provided on the
MXV 11-A module. Connector pins and signal functions are described in the
following table and shown in the following figure.
TYPICAL INTERFACE
CONNECTOR
1 OF 2

NO PIN
(FOR CABLING
INDEXING)

MXV 11-A Connector Pins
511

TOP OF
MXVll-A
MODULE

1118047
MXV11-A I/O Connector Pin Functions
'in

3
4
5
6
7

8
9

Signal

Function

UART CLOCK The baud rate clock appears on this pin. When an internal baud rate is selected, this pin is a TTL output.
When no baud rate is selected on the module, this is
an external baud rate input. The high level for the
clock> 3.0 V.
GND
Transmitter output
XMIT+
GND
GND
NC
Key, pin not provided
RCVReceiver input most negative
Receiver input most positive
RCV+
GND
Power for the DL V 11-KA option
+ 12 V

Current Loop
rhe MXV 11-A module can interface with 20 rnA active or passive current
oop devices when used with the DL V 11-KA option. This option consists of
a DL V 11-KB (EIA to 20 rnA current loop converter) and a BD21 A-03 inter:ace cable. The MXV 11-A does not have the capability to support the reader-run portion of the DLV 11-KA option. The DLV 11-KA option is placed between the MXV 11-A serial line output and the 20 rnA current loop
:>eripheral device.
MXV11-A Interface Cables
Cable

Application

Length

3C21B-05

EIA RS-232C modem cable to interface with
modems and acoustic couplers (2 X 5-pin
AMP female to RS-232C male).

1.5 m (5 ft)

3C20N-05

EIA RS-232C null modem cable to directly
interface with a local EIA RS-232C terminal
(2 X 5-pin AMP female to RS-232C female).

1.5 m (5 ft)

BC20M-50

EIA RS-422 or RS-423 cable for high-speed
transmission (19.2K baud) (2 X 5-pin AMP
female to 2 X 5-pin AMP female).

15 m (50 ft)

BC05D-10

Extension cable used in conjunction with
BC21B-05.

3 m (10 ft)

BC05D-25

Extension cable used in conjuntion with
BC21B-05.

7.6 m (25 ft)

BC03M-25

"Null modem" extension cable used in
conjunction with BC21B-05.

7.6 m (25 ft)

512

M8047
NOTE
"Strapped" logic levels are provided on Data Terminal Ready
(DTR) and Request To Send (RTS) for operation of modems
with manual provisions (such as Bell 103A data set with 804B
auxiliary set).

The MXV 11-A may operate with several peripheral device cables and options for flexibility when configuring systems. A variety of cables and options, as well as the primary application of each, are shown with the
MXV11-A.

1. The receivers on the MXV 11 have differential inputs. Therefore, when
designing an RS-232C or RS-423 cable, receive data (pin 7 on the 2 X
5-pin AMP connector) must be tied to signal ground (pins 2, 5, or 9) in
order to maintain proper EIA levels (see the following figure).
2. To connect directly to a local EIA RS-232C terminal, it is necessary to
use a null modem. To design the null modem into the cable, one must
switch received data (pin 2) with transmitted data (pin 3) on the RS232C male connector as shown in the following figure.
To mate to the 2 X 5-pin connector block, the following parts are needed:
Cable Receptacle (OTY 1)

AMP PN 87133-5
DEC PN 12-14268-02

Locking Clip Contacts (OTY 9)

AMP PN 87124-1
DEC PN 12-14267-00

Key Pin (pin 6) (OTY 1)

AMP PN 87179-1
DEC PN 12-15418-00

513

M8047

EIA
RS232C

MXV11 A

< 5 f- -, CLEAR TO SEND ICBI
I

GND> 9

RCV DATA> 7

F1~10

f- ---l REQUEST TO SEND ICAI

6 f-

750D.
1/2W

+12 VDV

--, DATA SET READY ICCI
I

---.J DATA TERMINAL READY ICDI

<RECEIVE DATA IBBI
2 <TRANSMITTED DATA IRAI
7 <SIGNAL GROUND lAB I
1 <PROTECTIVE GROUND IAAI

"- 3

RCV DATA> B ,r

XMIT DATA> 3

GRD> 2

CABLE
MXV11-A
CONNECTOR

EIA
RS·232C
CONNECTOR

8218-05 Modem Cable

514

MODEM

M8047

~MXV"A~ - - --15.2 M (50 FT)----~

-----IBC20M-50------

MXV11-A TO LOCAL TERMINAL
~~;.::...-----4.2M(14FT)----MXV11-A

BC20N-05

--~-2.7

M (9 FT)

(NOTE 2)

~
~.

EJ
MXV11-AD

"~----11.8 M (39 FT)----------_

--=----

-~~--_co_________co_BC21 B-05
BC03M-25
2.7 M
NOTES:
(9 FT)
1. MODEM USED IS A "MANUAL TYPE"
SUCH AS BELL 103A WITH 804B.
2. DEC EIS RS-232C TERMINALS (VT52,
LA36, LS120, ETC.) COME EQUIPPED
WITH A 9 FT CABLE. NON-DEC EIA
RS-232C TERMINALS ARE CONNECTED
SIMILARLY EXCEPT 9 FT OF LENGTH
MUST BE DEDUCTED FROM THE TOTAL
CABLE LENGTH.
3. XX = CABLE LENGTH WHICH MUST BE
SPECIFIED WHEN ORDERING.

MXV 11-A EIA Cable Configurations

515

MB047

MXVll-A TO 20 MA TERMINAL

WITH LT33-MD
MODIFICATION
KIT.
OLVll-KA

PRISOl

NOTES:
1. PRISOI IS A SERIAL LINE PAPER TAPE
LOADER.
2. MXVll-A WILL NOT SUPPORT DLVll-KA
READER RUN CIRCUITS.
3. XX = CABLE LENGTH WHICH MUST BE
SPECIFIED WHEN ORDERING.

MXV 11-A 20 rnA Cable Configurations

516

M8048

M8048
MRV11-C READ-ONLY MEMORY (ROM) MODULE

The MRV 11-C is a flexible, high-density ROM module used with the LSI-11
bus. The module contains 129 wirewrap pins and 16 24-pin ROM chip sockets that use a variety of user-supplied ROM chips. Masked ROMs, fusible
link ROMs and ultraviolet erasable PROMs are acceptable to use. The
.MRV 11-C is shipped without jumpers installed.
Using 4K X 8 ROM chips, the total capacity of one M8048 module can be
64K bytes, accessible either by direct access or window mapping.

Amps

+5
0.8

+ 12

Bus Loads

Cables

AC
2

None

(plus ROM chip power)

Standard Addresses
Recommended window starting address 760000
Bootstrap starting address: 16-bit system 173000; 18-bit system 773000
Technical detailed information is beyond the scope of this manual. Additional information can be found in the Microcomputer Processor Handbook,
EB-18451-20.

517

M8048
Compatible UV PROMs (Ultraviolet)
UV PROMs

Chip Array Size

Maximum Memory Siz.e

Intel 2758
Intel 2716
Intel 2732
Mostek MK2716
T.I. TM8 2516
T.I. TM8 2532

1K X 8
2K X 8
4K X 8
2K X 8
2K X 8
4K X 8

16K bytes
32K bytes
64K bytes
32K bytes
32K bytes
64K bytes

Compatible PROMs
PROM

Chip Array Size

Maximum Memory Size
16K bytes
16K bytes
16K bytes
32K bytes

Intel 3628
1K X 8
8ignetics 828 2708 1K X 8
8ignetics 828 181 1K X 8
8ignetics 828 191 2K X 8

518

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80tf
60tf
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t t tf
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DALO-15
Jl13
All
J22 I'"'D-B-1----Y-8-,51--.----..:...:..:..:.------o

Jl12

Jl15
A12
Y84I--+-.---..:...:..:.=-------o
J117
DB3 DRIVERS Y831--+-+-----,
+5 VDC----<>
J111
DB4
Y821--t-t----,

Jl16

J24
+5 VDC -----<>
J23

DB2

800T

085

All
A12
ENABLE

J18
Y81

CSR ADDRESS

Jl14

MEMORY

BOOT
ENABLE

BIT 1
BIT 2
BIT 3
BIT 4

BIT 12
BIT 11
BIT 10
BIT 9
BIT 8

J17
J15
J13
J11

J12
JlO

Ih~-rlj~..n).1 CONTROL

01
1"0

STATUS
REG.

J16
J14

DB1
DB2

HIGH
BYTE

YB5
Y84

BINARY
DECODER

DB3 DRIVERSYB11--t-t-..-I---t---l SELC

CEO

DB4

YB21-+-+-t---<.-t---i SELB

CE1

085

YB31-+-+-+-I----<......, SELA

CE2
CE3

J39

WINDOW
ENABLE

CE4
CE5

J38 , . . . - - - - - - - - ,
DB1 LOW
YB5

AD15

J37

DB2 !~6E

YB4

DB3 DIRECT

YB1

DB4 ADDRESS YB21------'
DRIVERS
DB5
YB31------'

J34
WINDOW

J69

ENABLE~

J71

DIRECT ---0
ENABLE

MRV 11-C Configuration Interconnections

J79

CE4
CE5

CE6

CE7

M8048

WINDOW
MAPPING

YES

END
MR·3879

Configuration Procedure

521

M8048
Wirewrap Pin Identification
Wirewrap Pin
Designation

Function

J1
J2
J3
J4
J5
J6
J7
J8
J9
J 10
J 11
J 12
J 13
J 14
J 15
J 16
J 17
J 18
J 19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
J41
J42
J43

RXCX pull-up resistor
RXCX optional capacitor
RXCX signal
LMA TCH input for BDOUT control
LMATCH for BDOUT control
Window address enable ground
Window address enable
High byte chip enable bit A 11
CSR high byte bit 8 chip enable output
High byte chip enable bit A 12
CSR high byte bit 9 chip enable output
High byte chip enable least significant bit
CSR high byte bit 10 chip enable output
High byte chip enable intermediate bit
CSR high byte bit 11 chip enable output
High byte chip enable most significant bit
CSR high byte bit 12 chip enable output
Boot address chip enable bit A 11
Boot address chip enable bit A 12
Boot address chip enable least significant bit
Boot address chip enable intermediate bit
Boot address chip enable most significant bit
Boot address chip enable ground reference
Boot address chip enable 5 V reference
Direct address bit 11 chip enable output
Low byte chip enable A 11 bit
CSR low byte bit 0 chip enable output
Direct address bit 12 chip enable output
Low byte chip enable A 12 bit
CSR low byte bit 1 chip enable output
Direct address bit 13 chip enable output
Low byte chip enable least significant bit
CSR low byte bit 2 chip enable output
Direct address bit 14 chip enable output
Low byte chip enable intermediate bit
CSR low byte bit 3 chip enable output
Direct address bit 15 chip enable output
Low byte chip enable most significant bit
CSR low byte bit 4 chip enable output
Reserved for future DIGITAL use.
Window address bit 15 compare ground
Window address bit 13 compare input
Window address bit 12 compare ground
522

M8048
Wirewrap Pin Identification (Cont)
Wirewrap Pin
Designation

Function

J44
J45
J46
J47
J48
J49
J50
J51
J52
J53
J54
J55
J56
J57
J58
J59
J60
J61
J62
J63
J64
J65
J66
J67
J68
J69
J70
J71
J72
J73
J74
J75
J76
J77
J78
J79
J80
J81
J82 .
J83
J84
J85
J86

Window address bit 14 compare input
Window address bit 14 compare ground
Window address bit 15 compare input
Window address bit 16 compare ground
Window address bit 16 compare input
Window address bit 13 compare ground
Window address bit 17 compare input
Window address bit 17 compare ground
Window address bit 12 compare input
Direct address 32K memory limit output
Direct address 16K memory limit output
Direct address memory limit input
Direct address 8K memory limit output
Direct address bit 17 compare ground
Direct address bit 16 compare input
Direct address bit 16 compare ground
Direct address bit 17 compare input
Direct address bit 15 compare ground
Direct address bit 15 compare input
Direct address bit 14 compare ground
Direct address bit 14 compare input
Direct address bit 13 compare ground
Direct address bit 13 compare input
CSR high byte bit 15 enable ground
CSR high byte bit 15 enable input
High byte chip enable window address function
High byte chip enable direct address function
High byte chip enable function select drivers
Bit 7 chip select enable input
Bit 7 chip enable decoder output
Bit 6 chip select enable input
Bit 6 chip enable decoder output
Bit 5 chip select enable input
Bit 5 chip enable decoder output
Bit 4 chip select enable input
Bit 4 chip enable decoder output
Bit 3 chip select enable input
Bit 3 chip enable decoder output
Bit 2 chip select enable input
Bit 2 chip enable decoder output
Bit 1 chip select enable input
Bit 1 chip enable decoder output
Bit 0 chip select enable input
523

M8048
Wirewrap Pin Identification (Cont)
Wirewrap Pin
Designation

Function

J87
J88
J89
J90
J91
J92
J93
J94
J95
J96
J97
J98
J99
J100
J101
J102
J103
J104
J105
J106
J107
J108
J109
J110
J 111
J 112
J 113
J 114
J 115
J 116
J 117
J118
J119
J120
J121
J122
J123
J124
J125
J126
J127
J128
J129

Bit 0 chip enable decoder output
Boot address enable ground
Boot address enable
DAL 4 CSR address select signal
DAL 4 CSR address select ground
DAL 1 CSR address select signal
DAL 1 CSR address select ground
DAL 2 CSR address select signal
DAL 2 CSR address select ground
DAL 3 CSR address select signal
DAL 3 CSR address select ground
Pin 18 input for chip set 5
Chip wirewrap interconnection for chip set 5
Pin 20 input for chip set 5 (chip enable 5)
Pin 18 input for chip set 4
Chip wirewrap interconnection for chip set 4
Pin 20 input for chip set 4 (chip enable 4)
Pin 18 input for chip set 6
Chip wirewrap interconnection for chip set 6
Pin 20 input for chip set 6 (chip enable 6)
Pin 18 input for chip set 7
Chip wirewrap interconnection for chip set 7
Pin 20 input for chip set 7 (chip enable 7)
Reserved for future DIGITAL use.
ROM interconnection, ground reference
Chip enable bit bus input
Address bit A 11, used as chip input A 10
Chip interconnection loop (to wirewrap pins)
Address bit A 12, used as chip input A 11
Chip interconnection loop for chip pin 21
ROM interconnection + 5 Vdc voltage reference
Pin 18 input for chip set 0
Chip wirewrap interconnection for chip set 0
Pin 20 input for chip set 0 (chip enable 0)
Pin 18 input for chip set 1
Chip wirewrap interconnection for chip set 1
Pin 20 input for chip set 1 (chip enable 1)
Pin 18 input for chip set 2
Chip wirewrap interconnection for chip set 2
Pin 20 input for chip set 2 (chip enable 2)
Pin 18 input for chip set 3
Chip wirewrap interconnection for chip set 3
Pin 20 input for chip set 3 (chip enable 3)

524

M8048
Control and Status Register
Each MRV 11-C board uses one 16-bit control and status register located in
the system I/O page to determine mapping of ROM segments into windows
in the window mapped mode. The default address for this CSR is 177000
(777000 in the PDP-11 /23 system). The valid address range for CSRs is
177000 to 177036 (777000 to 777036 on PDP-11 /23s).
The CSR contains a 5-bit read/write field for each window. The number
stored in this field (0 to 31 10) selects the desired 2Kb region from the
MRV 11-C board to be associated with the window in question. CSR bits 0
through 4 control the mapping of the low address window, window O. The
low five bits of the upper byte (bits 8 through 12) control the mapping of
window 1.
The MRV11-C optionally provides a window enable/disable capability.
When this option is selected, bit 15 of the CSR is used to enable or disable
window response under program control. When bit 15 is a 0, the board will
respond to references to the CSR or DATI or DA TIO references to either of
the windows. When bit 15 is a 1, only the CSR will respond. If the enable/disable option is not selected, bit 15 of the CSR will be read only and
will always be O. The enable/disable bit has no effect on direct mode addressing or the bootstrap window capability. If enable/disable option is
used, bit 15 on system initializes, disabling the board.
Control and Status Register Addresses
CSR
Address

Bit 4
J90 to J91

Bit 3
J96 to J97

Bit 2
J94 to J95

Bit 1
J92 to J93

177000·
177002
177004
177006
177010
177012
177014
177016
177020
177022
177024
177026
177030
177032
177034
177036

R
R
R
R
R
R
R
R
I
I
I
I
I
I
I
I

R
R

R
I
R
I
R
I
R
I

R = jumper removed.

I
I
R

R
I
I
I
I
R

I
I
R

R
R
I
I
I
I

I
I
R
R
I
I

I
R
I
R
I
R
I

I = jumper installed.

• Default address

NOTE
Install J67 to J68 to allow the use of bit 15 of the CSR.
525

M8048
MRV11-C Direct Addressing Starting Address
Starting
Address

Bit 17
Bank 57 to 60

Bit 16
59 to 58

Bit 15
61 to 62

Bit 14
63 to 64

Bit 13
65 to 66

0
20000
40000
60000
100000
120000
140000
160000

0
1
2
3
4
5
6
7

I
I
I
I
I
I
I
I

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

200000
220000
240000
260000
300000
320000
340000
360000

10
11
12
13
14
15
16
17

I
I
I
I
I
I
I
I

R
R
R
R
R
R
R
R

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

400000
420000
440000
460000
500000
520000
540000
560000

20
21
22
23
24
25
26
27

R
R
R
R
R
R
R
R

I
I
I
I
I
I
I
I

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

600000
620000
640000
660000
700000
720000
740000
760000

30
31
32
33
34
35
36
37

R
R
R
R
R
R
R
R

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

R = jumper removed.
I = jumper installed.

526

R
R
R
R
R
R
R
R
R
R
R
R
I

R
R
R
R

M8048
Using Multiple Boards
Up to 16 MRV11-C boards may be configured in a single system. When multiple boards are present, each board has a unique control and status register address assigned in increasing order from 177000 (777000 in PDP11/23 systems). Each board can have a unique 4Kb area of the physical
address space set aside for its windows, but it is also possible to share
one 4Kb area of the address space among all MRV 11-C boards installed in
the system. This is done by using the enable/disable capability discussed
earlier. When enable/disable is implemented, the disable bit in the CSR will
be set automatically by BINIT on the bus or by execution of the RESET instruction. Therefore, the initial state of the system will have all boards disabled. To access a particular segment of ROM in this multiboard configuration, the programmer first enables the desired board and maps the
segment. When access to that segment is completed, the board is again
disabled to allow another board to be selected some other time.

Chip Enable Jumpers
Sockets Enabled

Chip Enable Signal Wirewrap Jumpered Pins

XE43,XE44
XE37,XE38
XE31, XE32
XE25,XE26
XE41, XE42
XE35, XE36
XE29,XE30
XE23,XE24

CEO

J86 to J87
J84 to J85
J82 to J83
J80 to J81
J78 to J79
J76 to J77
J74 to J75
J72 to J73

CE1
CE2
CE3
CE4
CE5
CE6
CE7

NOTE
J40 and J110 are unused at this time.
ROM Chips
The ROM is provided by the user and consists of up to 16 chips that are
inserted into prewired sockets. The chips will be either 1K X 8 bit, 2K X 8
bit, or 4K X 8 bit ROMs. When the MRV 11-C is fully populated, the result
will be either 16K, 32K, or 64K bytes of memory. These ROMs can be supplied by a variety of vendors and the basic configuration for many of the
ROMs is standardized except for pins 18, 19, 20, and 21. The configuration
of these pins will vary depending upon the size of the ROM and the vendor
who supplies them. The user should verify the vendor's specifications in
order to determine if a particular ROM can be used on the MRV 11-C.

527

M8048
The MRV 11-C module is configured so that the user can select the signals
that are applicable to pins 18, 19, and 21. The board provides wirewrap
pins for the user to select the A 11, A 12, 5 Vdc or ground. There are three
individual loops that interconnect all chips and three wirewrap pins available for each individual chip. Wirewrap pin J 112 interconnects pin 19 of all
the chips and pin J 116 interconnects pin 21 of all the chips; these are normally designated as the A 10 or A 11 inputs to the chips.

Wirewrap pin J 114 interconnects wirewrap pins that are individually associated with each chip. Pin 18 of each chip is individually wired to a wirewrap pin and chip pin 20 is wired to the chip enable signal. Chip pin 20 is
also individually wired_ to a wirewrap pin. The user must determine from the
vendor's specifications which signals apply to which pins and must install
jumper wires as needed to configure an operational module.

INTEL 2716

INTEL 2732

PIN CONFIGURATION

Vee

Vpp __ TO +5 VDC

VCC

All

OE/Vpp

A l O - TO All H

I T - TOOE

AID
cr
__ TOOE

BE_ TOCE

GND

2K X 8 ROM

4K X 8 ROM

MRV 11-C ROM Pin Configuration Sample

528

TO Al2 H
TOCE

_TOAll H

M8049

M8049
DRV11-J GENERAL PURPOSE PARALLEL LINE INTERFACE

Amps
+5

Bus Loads
AC
2

+ 12

1.BA

DC
1

Cables

BC02D-XX
BCOBY-XX
BC05W-XX (For loopback
half-twist connection)

Standard Addresses

CSR
DBR

764160
764162

764164
764166

764170
764172

D
764174
764176

Standard Vectors
Software programmable in the range 0000 8 -1774 8 ,

Diagnostic Programs
Refer to Appendix A.

NOTE
Both the XXDP + diagnostics and the DEC/X 11 module require
the installation of a BC05W-XX loop back cable.

Related Documentation
DRV 11-J Field Maintenance Print Set (MP-00B66-00)
DRVII-J User Guide (EK-DRV11J-UG)
Technical, detailed information is beyond the scope of this manual. Additional information can be found in the Microcomputer Interfaces Handbook,
EB-20 175-20.
529

M8049
Device Address
There are eight device registers on the M8049 module that can be individually addressed by the computer program. These registers are divided into
four control status registers (CSR A, B, C, D), and four data buffer registers
(DBR A, B, C, and D).

Addresses for the module are selectable from location 760000 octal
through 777600 octal address range. When more than one DRV 11-J is desired, the module's starting address must be assigned in descending order
and separated by 20 octal addresses. Example: the first module will be
760060, the second 760040, and the third, 760020 octal.

Nine address jumpers (W 1 through W9) are installed or removed to establish a base device register address. Note that address bits A 13 through
A 15 are neither configured nor decoded by the module. These bits are decoded by the bus master module as the bank 7 select (BBS7L) bus signal.
Address bit 0 is used by the program to select a high-byte or low-byte operation. Address bits 1 through 3 are used to select one of the eight device
registers in the addressed module.

'------v----'
BBS7 L = 1 (LI

'---v----'
ADDRESS JUMPERS

BYTE
SE LECT
1 = HI BYTE
0= LO BYTE

INSTALLED = ALLOWS MATCH TO OCCUR WITH A 1 (LOW) ON THE CORRESPONDING BUS LINE.
REMOVED = ALLOWS MATCH TO OCCUR WITH A a (HIGH) ON THE CORRESPONDING BUS LINE.

DRV 11-J Device Address Format

530

M8049
DRV11-J Registers
Mnemonic

Description

Address (Octal)"

CSRA
DBRA
CSRB
DBRB
CSRC
DBRC
CSRD
DBRD

Control Status Register A
Data Buffer Register A
Control Status Register B
Data Buffer Register B
Control Status Register C
Data Buffer Register C
Control Status Register D
Data Buffer Register D

7XXXXO
7XXXX2
7XXXX4
7XXXX6
7XXX10
7XXX12
7XXX14
7XXX16

• XXXX is jumper selectable between 60000 and 77760 octal
in a modulas of 20 octal.

Interrupt Vector Addresses
The DRV 11-J may be programmed to operate in systems requiring either
vectored interrupts or polled interrupts. If the DRV 11-J is used in a system
that required vectored interrupts, the interrupt vector addresses must be
programmed into a 64 X a-bit RAM (vector address memory) contained in
two interrupt controller chips (E2 and E 10). Each interrupt controller chip
may store a maximum of 32 interrupt vector addresses. CSRB bits D 07 -00
are used in conjunction with CSRA bits 07 -00 to program the 32 vector addresses for group 1 interrupt control. CSRD bits 07 -00 are used in conjunction with CSRC bits to program the 32 vector addresses for group 2
interrupt control. Note that vector address bits V9 through V2 are programmed by CSRB or CSRD bits D7 through DO, respectively.
A total of 64 vector addresses in the 0000 through 1774 octal range may be
stored in the vector address memory. To avoid device conflicts, refer to Appendix A of the Microcomputer Interfaces Handbook, EB-20 175-20, when
assigning vector addresses.

V9
I

, V6
I D4I
D5

CSRB (GROUP 11
OR
CSRD (GROUP 21

DRV 11-J Vector Address Format

531

00
0

M8049

(

U
PORT C AND D

U
PORT A AND B

SOFTWARE
CONTROLLED
VECTOR INTERRUPT

.J4~OO

lBJ3c:=::::J
Wl0

DRV 11-J Jumper Locations

532

M8049

DRV11-J Factory Jumper Configuration

Jumper

Function

Jumper
State"

A12

A 11

A10

CSRA
DBRA
CSRB
DBRB
CSRC
DBRC
CSRD
DBRD

Reserved for future use.

DRV 11-J monitors group 2 vectored
interrupts using port A I/O bits
11 -08 and USER RPL Y (A through D)
signals (default configuration).

W10
W11

Group
Vector
Interrupts

Function
This arrangement of jumpers W 1
through W9 assigns the device address
764160 octal to the first of eight
addressable bus registers. With a
starting address of 764160 octal, the
remaining bus registers are
automatically assigned the following
contiguous addresses.

• R = removed = o.
I = installed = 1.

533

764160
764162
764164
764166
764170
764172
764174
764176

M8049
12

UNUSED

CSRA Bit Assignments

CSRA Bit Function and Description
Bit

Function

07-00

C/S7-C/SO - These bits are used in conjunction with CSRD bits
(07 -00) to program interrupt control group 1. They contain status information when read, and command words when written.
Unaffected by BINIT. Read/write.

Direction A (DIR A) - Used for controlling DBRA. This bit, in conjunction with the USER RDY signal, controls the direction of data
transfer. When the DIR bit is cleared, the ORV 11-J ROY output
signal is asserted and the ORV 11-J is the input device. When set
and the USER ROY signal is asserted, the ORV 11-J is the output
device. The negation of either OIR or USER ROY will cause the
DRV 11-J outputs to remain in their high impedance state.
Cleared by BINIT. Read/write.

Interrupt Enable (IE) - Enables the DRV 11-J to generate processor interrupts when set. Used to enable both group 1 and group 2
interrupts. Cleared by BINIT. Read/write.

14-10

Unused. Read as Os.

User Ready A (RDY A) - Used for controlling OBRA. When read,
yields the state of the USER ROY signal. A 0 equals negated,
and a 1 equals asserted. It is used in conjunction with the DIR bit
to enable DRV 11-J output operations. The user device asserts
this signal when it desires the ORV 11-J to output data. Unaffected by BINIT. Read only.

534

M8049
15

CSRB Bit Assignments

CSRB Bit Function and Description
Bit

Function

07-00

D7 -DO - These bits are used in conjunction with CSRA bits
(07 -00) to program interrupt control group 1. They contain information selected by the command word loaded through CSRA.
The registers available are the IRR, ISR, ACR, IMR and the vector
address memory. Unaffected by BINIT. Read/write.

Direction B (DIR B) - Used for controlling DBRB. This bit, in conjunction with the USER RDY signal, controls the direction of data
transfer. When the DIR bit is cleared, the DRV 11-J RDY output
signal is asserted and the DRV 11-J is the input device. When set
and the USER RDY signal is asserted, the DRV 11-J is the output
device. The negation of either DIR or USER RDY will cause the
DRV 11-J outputs to remain in their high impedance state.
Cleared by BINIT. Read/write.

14-09

Unused. Read as Os.

User Ready B (RDY B) - Used for controlling DBRB. When read,
yields the state of the USER RDY signal. A 0 equals negated,
and a 1 equals asserted. It is used in conjunction with the DIR bit
to enable DRV 11-J output operations. The user device asserts
this signal when it desires the DRV 11-J to output data. Unaffected by BINIT. Read only.

535

M8049
15

RgV 1 4 - - - - U N U S E D - - - - - t

CSRC Bit Assignments

CSRC Bit Function and Description
Bit

Function

07-00

C/S7-C/SO - These bits are used in conjunction with CSRD bits
(07 -00) to program interrupt control group 2. They contain status information when read and command words when written.
Unaffected by BINIT. Read/write.

Direction C (DIR C) - Used for controlling DBRC. This bit, in conjunction with the USER ROY signal, controls the direction of data
transfer. When the DIR bit is cleared, the DRV11-J ROY output
signal is asserted and the DRV 11-J is the input device. When set
and the USER ROY signal is asserted, the DRV 11-J is the output
device. The negation of either DIR or USER ROY will cause the
DRV 11-J outputs to remain in their high impedance state.
Cleared by BINIT. Read/write.

14-09

Unused. Read as Os.

User Ready C (ROY C) - Used for controlling DBRC. When read,
yields the state of the USER ROY signal. A 0 equals negated,
and a 1 equals asserted. It is used in conjunction with the DIR bit
to enable DRV 11-J output operations. The user device asserts
this signal when it desires the DRV 11-J to output data. Unaffected by BINIT.

05
D5

CSRD Bit Assignments

536

D41

M8049
CSRD Bit Functions and Description
Bit

Function

07-00

07 -DO - These bits are used in conjunction with CSRC bits
(07 -00) to program interrupt control group 2. They contain information selected by the command word loaded through CSRC.
The registers available are the IRR, ISR, ACR, IMR and the vector
address memory. Unaffected by BINIT. Read/write.

Direction 0 (DIR D) - Used for controlling DBRD. This bit, in conjunction with the USER ROY signal, controls the direction of data
transfer. When the DIR bit is cleared, the DRV 11-J ROY output
signal is asserted and the DRV 11-J is the input device. When set
and the USER ROY signal is asserted, the DRV11-J is the output
device. The negation of either DIR or USER ROY will cause the
DRV 11-J outputs to remain in their high impedance state.
Cleared by BINIT. Read/write.

14-09

Unused. Read as Os.

User Ready 0 (ROY D) - Used for controlling DBRD. When read,
yields the state of the USER ROY signal. A 0 equals negated,
and a 1 equals asserted. It is used in conjunction with the DIR bit
to enable DRV 11-J output operations. The user device asserts
this signal when it desires the DRV 11-J to output data. Unaffected by BINIT. Read only.

I·
\:

1/0 BUS <15:8>

HIGH BYTE READ

·1·
.1.

1/0 BUS <7:0>

LOW BYTE READ

WORD READIWRITE

·1

Data Buffer Register Bit Assignment

Data Buffer Registers
The data buffer registers (DBRA, DBRB, DBRC, and DBRD) are 16-bit wordaddressable registers that contain output data when written and input data
when read. In an output mode, reading the input register will yield the output buffer contents. The output buffers DBRA through DBRD are not cleared
by initialize. The bit assignment is the same for all four registers.

537

M8049
Programmed Data Transfer
Input and output data transfers may be performed under program control by
addressing the data buffer registers (DBRA, B, C, or D) and then reading or
writing the data. Data is transferred on a 16-bit word-by-word basis by reading or writing the appropriate data buffer.

Interfacing to User's Device
Two board-mounted 50-pin male connectors (J 1 and J2) interface the
DRV 11-J to the user device. Connector J 1 is used to interface the port A
and port B signals, while J2 is used for the port C and port D signals. Location of the connector pins is shown below with the "interface signal names
and their respective connector pins listed in the table that follows.

DRV 11-J I/O Connector Pin Locations

I/O Connector Pin Functions

Signal Name

Connector
Pin

Signal Name

Connector
Pin

DRV11-J RDY A
DRV11-J RPLY A
USER RDY A
USER RPLY A
A I/O 15
A I/O 14
A I/O 13
A I/O 12
A I/O 11
A I/O 10

J1-29
J1-33
J 1-31
J1-27
J1-45
J1-46
J1-43
J1-49
J1-48
J 1-44

DRV11-J RDY D
DRV11-J RPLY D
USER RDY D
USER RPLY D
D I/O 15
D I/O 14
D I/O 13
D I/O 12
D I/O 11
D I/O 1C

J2-29
J2-33
J2-31
J2-27
J2-45
J2-46
J2-43
J2-49
J2-48
J2-44

538

M8049
I/O Connector Pin Functions (Cont)

Signal Name

J1
Connector
Pin

Signal Name

J2
Connector
Pin

A I/O 9
A I/O 8
A I/O 7
A 1/06
A I/O 5
AI/04
A I/O 3
A I/O 2
A I/O 1
A I/O 0

J1-50
J1-47
J 1-41
J1-36
J1-42
J1-35
J1-40
J1-38
J1-39
J1-37

01/09
01/08
01/0 7
01/0 6
01/0 5
01/04
01/03
01/02
01/0 1
01/00

J2-50
J2-47
J2-41
J2-36
J2-42
J2-35
J2-40
J2-38
J2-39
J2-37

GNO
GNO
GNO
GNO
GNO

J 1-26
J1-28
J1-30
J1-32
J1-34

GNO
GNO
GNO
GNO
GNO

J2-26
J2-28
J2-30
J2-32
J2-34

ORV11-J ROY B
ORV11-J RPLY B
USER ROY B
USER RPLY B
B I/O 15
B I/O 14
B I/O 13
B I/O 12
B I/O 11
B I/O 10
B I/O 9
B I/O 8
B I/O 7
B I/O 6
BI/O 5
B I/O 4
BI/O 3
BI/O 2
B I/O 1
B 1/00
GNO
GNO
GNO
GNO
GNO

J1-20
J1-24
J 1-22
J 1-18
J1-6
J1-5
J1-8
J 1-2
J1-3
J1-7
J 1-1
J1-4
J 1-10
J 1-15
J1-9
J 1-16
J 1-11
J 1-13
J 1-12
J 1-14
J 1-17
J 1-19
J 1-21
J1-23
J1-25

ORV11-J ROY C
ORV11-J RPLY C
USER ROY C
USER RPLY C
C I/O 15
C I/O 14
C I/O 13
C I/O 12
C I/O 11
C I/O 10
C 1/09
C I/O 8
C I/O 7
C I/O 6
C I/O 5
C 1/04
C I/O 3
C I/O 2
C I/O 1
C 1/00
GNO
GNO
GNO
GNO
GNO

J2-20
J2-24
J2-22
J2-18
J2-6
J2-5
J2-8
J2-2
J2-3
J2-7
J2-1
J2-4
J2-10
J2-15
J2-9
J2-16
J2-11
J2-13
J2-12
J2-14
J2-17
J2-19
J2-21
J2-23
J2-25

539

M8049
I/O Signal Functions
Signal Name"

Function

DRV11J ROY [X]

This signal is asserted by the DRV 11-J to inform the
user that data may be placed on the I/O bus associated with the signal. It is asserted when the corresponding DIR bit is cleared.

DRV11J RPL Y [X]

This signal is asserted when the DRV 11-J has accepted data (DRV 11-J is the input device) by reading the corresponding data buffer with the associated DIR bit cleared, or when data is available for the
user device (DR V 11-J is the output device) by writing the corresponding data buffer with the associated DIR bit set.

[X] I/O < 15:00>

These are the 16 three-state data buffer inputs and
outputs.

USER ROY [X]

This signal is asserted by the user device to inform
the DRV 11-J that it requires input data (DRV 11-J is
the output device) and, in conjunction with the associated DIR bit, enables the DRV 11-J th ree-state outputs.

USER RPL Y [Xl

This signal is asserted by the user device when data
is accepted (DRV 11-J is the output device) or when
data is available (DRV11-J is the input device).

• [Xl equals either A, B, C, or D.
540

M8049
Cables
The three types of cable used to connect the DRV 11-J to a user device are
described below.

Cable Description
Cable Type- Description

Max_ Length--

BC02D-XX

Flat, 50 wires, shielded connectors
(DEC PN 12-11664) on both ends

1.83 m (6 ft)

BC08Y-XX

Round, 50-pin Berg to 50-pin Berg,
50 wires

1.83 m (6 ft)

BC05W-XX

Flat, 50 wires, shielded connectors
(DEC PN 12-11664) on both ends

7.6 m (25 ft)

I/O Signal Specifications
All data buffer signals (I/O < 15:00» at the connectors (J 1 and J2) are
defined as being asserted (1) high (+ 3 V) and negated (0) low (GND). All
protocol signals (DRV11-J ROY, DRV11-J RPLY, USER ROY and USER
RPL Y) at the connectors are defined as being asserted (1) low (GND) and
negated (0) high (+3 V).

I/O Signal Loopback Connections
The DRV 11-J signal pin assignments are arranged to permit loopback operation when a BC05W-XX cable is installed with a half-twist connecting J 1-1
to J2-50. With the cable installed in this manner, the proper connections
are made to loopback the DRV 11-J protocol signals.

-xx in the cable denotes length in feet. For example, a 1.83 m (6 ft)
BC02D cable would be ordered as BC02D-06.
Maximum cable length is specified as being from DRV 11-J to DRV 11-J.
541

M8049
DRV11-J Loopback Signal Connections
J1 Pin No.

Port B

Port A

Signal

J2 Pin No .

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
20
22
24

....... DI/09
50
B I/O 9
....... D I/O 12
B I/O 12
49
......... D I/O 11
B I/O 11
48
....... DI/08
47
B I/O 8
B I/O 14
....... DI/O 14
46
....... D I/O 15
B I/O 15
45
......... DI/O 10
B I/O 10
44
......... D I/O 13
B I/O 13
43
....... D1/05
42 Port D
B I/O 5
....... D I/O 7
41
B I/O 7
.......DI/03
40
B I/O 3
....... D I/O 1
39
B I/O 1
......DI/02
38
B I/O 2
....... DI/OO
37
BI/OO
.....D1/06
36
B I/O 6
......D1/04
35
B I/O 4
USER RPLY B + - DRV11-J RPLY D 33
DRV 11-J RDY B--- USER RDY D
31
USER RDY B
------ DRV 11-J RDY D 29
DRV 11-J RPL Y B--' USER RPL Y D
27

27
29
31
33
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

USER RPLY A +-DRV11-J RPLY C 24
DRV 11-J RDY A-+ USER RDY C
22
USER RDY A
-+-DRV11-J RDY C 20
DRV 11-J RPL Y A-+ USER RPL Y C
18
.....C I/O 4
16
A I/O 4
...... C I/O 6
15
A I/O 6
....... CI/OO
14
A I/O 0
...... C I/O 2
13
A I/O 2
12 Port C
A I/O 1
'-'CI/O 1
....... CI/03
11
A I/O 3
10
A I/O 7
'-'C1/07
......... C I/O 5
9
A I/O 5
....... CI/O 13
8
A I/O 13
....... C I/O 10
7
A I/O 10
....... CI/O 15
6
A I/O 15
5
A I/O 14
'-'CI/O 14
....... C1/08
4
A I/O 8
...... CI/O 11
3
A I/O 11
2
+-+CI/O 12
A I/O 12
1
A I/O 9
'-'CI/09

Connector pins 17, 19, 21, 23, 25, 26, 28, 30, 32, 34 on J 1 and J2 are
grounds.
542

M8186

M8186
KDF11-AX 11/23 MICROCOMPUTER

The KDF 11-A is a 16-bit, double-height, multilayered, microcomputer module. The processor (microcomputer) uses the existing LSI-11 bus. The
KDF 11 is backward-compatible with existing LSI-11 /2 processors and I/O
interfaces. Memory management is included as a standard feature.
The KEF 11-A option (not part of a standard system) is a floating point microcode extension chip that mounts to a socket on the KDF 11-A processor
module. This chip option can execute the PDP-11 /34 (FP 11) floating point
instruction set. These instructions supplement the integer arithmetic instructions (for example, MUL, DIV) in the basic instruction set.
Four 40-pin chip sockets mounted on the KDF 11-A module are to accommodate the following chip functions.
• Memory Management Unit (MMU)
• Spare
• Floating point (optional)
• Data/control unit (the basic processor)

KDF 11 Specifications
Identification:

M8186

Size:

Double-height module

Power Requirements:

+5 V ± 5% 2.0 A

+ 12 V ± 5% 0.2 A

Bus Loads:

AC 2 unit loads
DC 1 unit load

Environmental:

DEC STD 102 Class C

543

M8186
Diagnostic Programs
The following diagnostic programs are used with the LSI-11/23 processor,
except for the limitations noted.
JKDBBO
JKDABO

CPU trap and EIS diagnostics
Memory Management Unit (MMU)
Requires KTF 11-A option (21-15542-00/01) installed in IC
socket E57.

JKDCAO

Floating point diagnostic - Part 1

JKDDAO

Floating point diagnostic - Part 2
The floating tests require the KEF 11 option to be installed on
the board. These diagnostics expect the CPU to be fault free.
Therefore, the JKDB?? diagnostic should be run before the floating point diagnostics.

NOTE
See Appendix A for multimedia assignments.
Related Documentation
Microcomputer Processor Handbook (EB-18451-20)
KDF 11-A Field Maintenance Print Set (MP-00734-00)
LSI-11, PDP-11 /23 Reference Card (EH-17898-20)
KEF11-A (Floating Point Option Installation)
The KEF-11 AA floating point option resides in two MOS/LSI chips contained on one 40-pin hybrid package (57-00001-01). The KEF11-AA requires
the memory management chip to be present along with the base MOS/LSI
chips, since all of the floating point accumulators and status registers are
in the MMU chip. Chapter 10 in the Microcomputer Processor Handbook,
EB-18451-20 covers the KEF 11 in detail.
Early revision M8186s require an ECO (M8186-S-0007) to accommodate
the KEF 11-AA option. Modules at hardware revision A5 (A etch) or C 1 (C
etch) and below, require this change.
Remove E57 (DEC PN 21-15542-00)
Install E57 (DEC PN 21-15542-01)
Remove E31 (DEC PN 57-00000-00)
Install E21 (DEC PN 57-00000-01)

NOTE
Mark Rev A6 or C2 on the module handle to indicate the new
revision, depending on original etch rev.
544

M8186
After the ECO is installed, install the KEF 11-AA option (57-00001-01) in IC
socket position E39.

KDF 11 Variations
AA -LSI-11 /23 16-bit microcomputer with KTF 11-AA memory management
(M8186)
AB -KOF 11-AA with KEF 11-AA (floating point option)
AC -KOF 11-AA without KTF 11-A
GO -KOF11-AC with MXV11-AC and MSV11-CO (32K words)
HO -KOF 11-AC with MSV 11-00 (32K words)
HF -KOF 11-AA with two MSV 11-00 (64K words)
HH -KOF 11-AA with three MSV 11-00 (96K words)
HK -KOF 11-AA with four MSV 11-AA (128K words)
RE -KOF 11-AA with MXV l1-AC, MSV 11-00 (48K words) and QJV 13-0Z
(RT2 V 4.0, license only)
RE -KOF 11-AA with MXV 11-AC, two MSV 11-00 (80K words) and QJV 13OZ
RJ - KOF 11-AA with MXV 11-AC, three MSV 11-00 (112K words)
QJV13-0Z

and

SE -KOF 11-AA with MXV 11-AC, MSV 11-00 (48K words) and QJ642-0Z
(RSX 11-S V 2.2, license only)
SG -KOF 11-AA with MXV 11-AC, two MSV 11-00 (80K words) and QJ642OZ
SJ - KOF 11-AA with MXV 11-AC, three MSV 11-00 (112K words)
QJ642-0Z
XA -KOF 11-AA with two MSV 11-EO (64K word) (parity)
XB -KOF 11-AA with four MSV 11-EO (128K word) (parity)

545

and

M8186
Data/Control (DC302, DC303) Hybrid
The data chip (DC302) contains the PDP-11 general registers, the processor status word (PS), several working registers, the arithmetic and logic
unit (ALU), and conditional branching logic. The DC302 chip:
• performs all arithmetic and logical functions
• handles all data and address transfers with the LSI-11 bus (except relocation, which is handled by the MMU)
• generates most of the signals used for interchip communication and
external system control.

Control Chip
The control chip (DC303) contains the microprogram sequence logic and
552 words of microprogram storage in programmable logic arrays (PLA)
and read-only memory (ROM) arrays. The control chip accesses the appropriate microinstruction in the PLA or ROM and sends it along the MIS to the
data and MMU chips for execution. The control chip accesses only its local
storage.

MMU Chip
The MMU chip serves two purposes.
• It provides the memory management function.
• It provides storage for the KEF 11-AA floating point accumulators and
status registers.

This chip provides user and kernel mode address relocation of 18 bits. Sixteen-bit virtual addresses are relocated via mapping registers (PARs) to
the appropriate 18-bit physical address for the transmission to the external
system bus.
The MMU chip is controlled by information received on the microinstruction
bus (MIS) from both the data chip and the control chip and by several discrete control inputs. The KDF 11-AA can operate without the MMU chip;
however, the memory would be limited to 32K words and the floating point
registers would not be available.

546

M8186

0--0

W18

~W19

E57

E48

E39
(;J

::::1-

E31

W17
-I

-..0

<{a:
<{z

I-z
<{-

1-1-

-10-

u..

0---<>

o--oW15
W14o---<>
0---<> Wl:l
W120--0
0---<> Wl1
Wl 0 0---<>
0---<> W9
W8o---<>
O--OW7
W6o---<>
o--oW5

IWl

W2
0---<>

0---0

KDF 11-AA Rev A Jumpers

547

M8186
M8186 (Etch Rev A) Jumper Configurations
Jumper

Name

Function

Factory Set

Master clock

In - enabled

Reserved for
DEC use

Removed - do not install

Out

Reserved for
DEC use

Installed - do not remove

Event line
enabled

Out - enabled

W5,W6

Power-up mode

(. See footnote.)

W5 -In
W6 - Out

Halt/trap option

In - traps to 108
on HALT

Out - enters console
OOT on HALT
W8

Bootstrap address In - powers up to
bootstrap address 1730008

Out - powers up to
address specified by
W9-W15
W9-W15 User-selectable
W9-W 15 correspond to
bootstrap address address bits 9 through
15, respectively, in
mode 2
In = logic 1
Out = logic 0

Power-Up Mode Selection
Mode

Name

PC@24
Console OOT
Bootstrap
Extended
microcode

Out
In
Out
In

Out
Out
In
In

2
3

548

W9-W15-ln

M8186
M8186 (Etch Rev A) Jumper Configurations (Cont)
Jumper

Name

Function

W16

Reserved for
DEC use

Factory-installed;
do not remove.

W17

Reserved for
DEC use

Factory-installed;
do not remove.

W18

Reserved for
DEC use

Factory-installed;
do not remove.

Factory Set

~W18
L -

E39
<.:I

«-

1-1-

-10..

-1
~O

RED JUMPER WI RE
8YPASSES Dl

E31

f-z

-""'------

«0:

«z
u

o--oW15
W140---0

o---oWl~

W120--0
0---0 W1'
Wl00---0
0---0 W9
W80---0
O--OW7
W60--0
o--oW5

0--0

W30--0
W20--0
0 - - 0 W16
0 - - 0 W17

KDF 11-A Rev C Jumpers

549

M8l86
M8186 (Etch Rev C) Jumper Configurations
Jumper

Name

Function

Factory Set

Master clock

In - Enabled

Reserved for
DEC use

Removed - do not install

Out·

Reserved for
DEC use

Installed - do not remove

In •

Event line
enabled

Out - enabled

W5, W6

Power-up mode

(. • See footnote.)

W5 -In
W6 - Out

Halt/trap option

In - traps to 108 on
HALT

Out

Out - enters console
OOT on HALT
Bootstrap address In - powers up to
1730008

Out - powers up to
address specified by
W9-W15
W9-W15 correspond to
W9-W15 User-selectable
bootstrap address address bits 9 through
15, respectively
In = logic 1
Out = logic 0
• Refer to FCO M8186-ROO09
Mode

Name

PC@24
PS@26
Console OOT
Bootstrap
Extended
microcode

Out

In
Out
In

Out
In
In

1
2
3

550

W9-W15-ln

M8186
M8186 (Etch Rev C) Jumper Configurations (Cont)
Jumper

Name

Function

Factory Set

W16, W17 Reserved for
DEC use

Factory-installed;
do not remove.

W16, W17-ln

W18

Out = disabled
In = enabled

Wake-up circuit

Hardware Revision System
As other modules have the etch revision level coded into the etch and the
circuit schematic revision level coded on the module handle, the M8186
has both codes stamped on the module handle.
The revision identifier is a two-field alphanumeric designation. The first field
indicates the etch revision. The second field indicates the modifications to
this etch.

IDENTIFIES ETCH LEVEl-------Jt

t""---IDENTIFIES MODIFICATIONS

M8186 Revision Identifiers
The M8186 started as hardware revision AO, as shown above; that is, etch
revision "A" with no modifications or work. As ECOs were released calling
for rework (not a new etch), the hardware revisions were released and the
etch revision field was incremented from A to B to C. No etch revision liB"
for the M8186 modules was built so the revision level appeared to change
from "A" to "C" via ECO no. 4. Etch revision "C" modules had ECO no. 5
incorporated on them before being released, therefore their hardware revision status did not change with ECO no. 5.

551

M8186

The hardware revision history of the M8186 is shown below.

NOTE:
ALL MODULES SHIPPED ARE
AT REVISION A3 OR GREATER
NEW ETCH REVISION "C"
CREATED. NO REVISION
"6" MODULES WERE BUILT

CURRENT STATUS
AS OF THIS WRITING

RELEASE

"AD"

REWORK
ECO NO 1

"Al"

REWORK
ECO NO 2

"A2"

REWORK
ECO NO 3

"A3"

RELAYOUT
ECO NO 4

~
~

j~r

REWORK
ECO NO 5

"A4"

"CO"

REWORK
ECO NO 6

"A5"

"Cl"

REWORK
ECO NO 7

"A6"

"C2"

REWORK
ECO NO 8

"A6"

REWORK
ECO NO 9

"A7"

"C2"

"C3"

M8186 ECO Summary

552

NOTE:
THE RELAYOUT INCORPORATED
THE CHANGES FOR ECO NO 5

NOTE:
THIS WAS A DOCUMENTATION
CHANGE ONLY

M8186
11/23 (M8186) ECO Summary
The following table details the ECOs issued since the first M8186 shipment.
These ECOs are coded "M8186-MlOOOX", where "X" is the ECO number
shown below.
ECO No.

Problem

Quick Verify

Too many wires and etch cuts,
new etch needed. Note that
the jumper locations change
for etch revision "C".

Module handle will be
stamped "C?" (where
"?" refers to the CS
revision).

Possible parity errors when
using parity memories
(MSV 11-E, etc.)

Check for etch cut to
E7 pins 16 and 18.

NOTE
Implementation of this ECO impacts configurations. This ECO
is discussed in detail below.

The internal wake-up circuit
defeats the sequencing provided by standard DEC power
supplies. This ECO should
be installed when the M8186
is used with same.

Red jumper wire is
installed in parallel
with 01.

CTl/DAT hybrid (57-00000-00)
and MMU IC (21-15542-00) were
not compatible with KEF 11-AA
floating point option. The
FP registers in the MMU were
inaccessible, and the CTl/DAT
data path caused intermittent
errors in floating point
instructions.

CTl/DAT should be
57-00000-01 and MMU
should be 21-15542-01
for floating point
compatibility.
Coordinate with ECO
M8186-0009.

MMU (21-15542-01) was included as part of the M8186
module. It should have been
specified as an option that
could have added to the
MMU from the M8186. ECO
KDF 11 A-OOO 1 adds it back in
at the option level
(KDF11-AB, KDF11-AA). This
is a documentation change
only.

Modules in systems may
or may not have MMU,
depending upon which
option they represent.
Spares, however, are
ordered as modules and
will not have MMUs.
MMUs must be ordered
separately.

553

M8l86
fCO No.

Problem

No jumper table in print
set (documentation change
only).

Prints contain a
jumper table.

Metal oscillator may short
to adjacent components.

Oscillator has nylon
spacer. Manufacturing change only. Do
not retrofit in
field!

Possibility of worst case
MMU timing violations.
Change configuration of
W2 and W3 to adjust
timing. This ECO must
be installed:

Module will have W2
removed and W3 in.
On etch Rev "A"
modules, W3 is installed by soldering
a jumper wire from
E2 pin 5 to E2 pin
15.

Quick Verify

when ECO M8186-0007
is put in

when a microcode
option (i. e., KEF 11)
is installed

when a 40-pin IC (CTl/
OAT, MMU or KEF11)
is replaced

whenever unexplained
system crashes occur.

ECO No.5
A circuit was included in the KDF 11-A to compensate for a design limitation
in the MSV 11-C and MRV 11-C. That is, these devices do not use BBS7 to
deselect themselves. It is this limitation that causes the requirement to
jumper-deselect memory in the 28K-32K range on lSI-11s; otherwise the
MSV 11-C would respond to peripheral addresses. Unfortunately, the parity
problem with MSV 11-E could not be fixed except by disabling this circuit.
As a result, after this ECO is installed (hardware revision "A4" and above,
and all etch revision "C"), the MSV11-C cannot be configured in the
28K - 32K (word) or in the 124K -128K (word) range. MRV 11-C cannot be
configured in the 28K-32K (word) range on mapped systems when used in
the "direct" or "window" addressed modes. On unmapped systems
(11/03 and KDF 11-AC) it may be configured in the I/O page.

554

M9400

M9400-XX
REV11, TEV11, AND BCV1X

Bus Loads

Amps

Cables

+ 12 AC

M9400-YA (REV11-A)

1.64
(2.24 max.)

1.0

M9400-YB (TEV 11)

0.54
(0.70 max.)

M9400-YC (REV 11-C)

1.0
(1.85 max.)

2.21

1.0

M9400-YO (BCV 1A)

(2) BC05 L

M9400-YE (BCV 1B)

0.29

(2) BC05 L

1.64

2.21

1.0

2.21

1.0

M9400-YF (REV 11-F)
M9400-YH (REV 11-H)
M9400-Y J (REV 11-J)

(2) BC05 L

M9400-YK (REV 11-K)
M9400-YL (REV 11-L)
M9400- YM (REV 11-M)
M9400-YN (REV 11-N)

1.64

2.21

Related Documentation
REV 11-A, C Field Maintenance Print Set (MP00073)
REV 11-H Field Maintenance Print Set (MP00331)
TEV 11 Field Maintenance Print Set (MP00074)
Microcomputer Interfaces Handbook (EB-20175-20)
555

1.0

M9400

c
W2

DMA
REFRESH
ENABLE

CONNECTORS PRESENT ONLY ON YO, YE, YJ, AND YK

BOOTSTRAP
ROM
ENABLE

DOD 0
E29

E25

E22

E19

W3
(ALWAYS
INSTALLED)

M9400 Jumper Locations

W 1: Installed to enable BDMG arbitration.
Installed on -VB, -YO, and -YE modules.
Not installed on -VA, -ye, -YF, -YH, -YK, and -YJ modules.
W2: Install to enable DMA refresh.
W3: Always installed.
W4: Install to enable bootstrap ROMs.
If REV 11 refresh is enabled, the memory electrically farthest from the
REV11 must reply to refresh. Also, processor refresh must be disabled.

556

M9400
NOTES
1.

If no memory replies to REV 11 refresh, the REV 11 may
hang the processor. The problem will appear to be a nonfunctioning CPU.

If the REV11 is not up to ECO no. 5 level or greater, the
same symptoms may occur if a DRV 11 is present that has
an external capacitor to extend NEW DATA READY to
greater than 1.8 J,LS.

Ji/#MA
"oQ:

"oQ:!

~"'~'"

"oQ:

II
"'~!#'
~
~
~ ~
8 #

c:-

VA·

c:-

YE
YF*

YH*

YJ*

YK*

~'"

REVll·A

TEVll

REVll·C

BCV1A·XX

BCV1B·XX

REVll·F

REVll·H **

REVll·J

REVll·K **

oQ:

YC*

$;:-

",'" ,f
R" .# ~:~:~~ATI ON

!rQ:

,l o~ l

I
~

x = FEATURE PRESENT
I = JUMPER INSTALLED
R = JUMPER REMOVED
* FACTORY·SET POTENTIOMETER
** REMOTE BOOT

M9400 Jumper Variations
The jumper states indicated in the preceding figure are as they are shipped
from the factory.
BCV options also include M9401 backplane connectors and BC05L expansion cables. Certain rules for cable lengths and module locations must be
observed. Refer to the "Systems Configurations" section for these configuration rules.
557

M9400
REV 11 ROM Program Commands
Command

Function

OOT (Halt). This allows the operator to examine and/or alter
memory and register locations via the console device. Control can be returned to the REV 11 program by entering the
ODT P (proceed) command if the PC has not been altered,
and the console device will display the $ prompt character. If
the PC has been altered, the operator can start program execution by entering the starting address 165006 and the G (go)
commands as follows.
@ 165006G
$

The processor responds by displaying the $ prompt character
on a new line and another REV 11 command can be entered.
XM<CR>

Memory Diagnostic program. After successfully completing
the diagnostic, the prompt character ($) is displayed on the
console device. Errors are indicated by the following displays
on the console device.
1.

173732
@

This is an address test error. The expected (normal) data
is in R3 and the invalid data is in the memory location
pointed to by R2. If desired, continue diagnostic program
execution by entering the ODT P command.
2.

173756
@

This is a data test error. The expected (normal) data is
stored in R3 and the invalid data is in the memory location pointed to by R2. If desired, continue diagnostic program execution by entering the ODT P command.
3.

000010
@

A timeout trap has occurred in testing memory locations
outside of the first (lowest) 4K memory.

558

M9400
REV 11 ROM Program Commands (Cont)
Command

Function
4.

nnnnnn
@

A timeout trap has occurred in testing memory locations
within the first 4K memory. The nnnnnn displayed is an
indeterminate number.
The actual memory test consists of an address test and a
data test. The address test first writes all memory locations
with addresses; it then reads and verifies the addresses. The
data test consists of two parts. An "all 1s" word is first
walked through all memory locations, which are initially o.
The second part consists of walking an all Os word through all
memory locations which are all 1s.
XC<CR>

Processor Diagnostic program. This is a memory-modifying
instruction test. Successful execution of the diagnostic program results in the prompt character ($) being displayed on
the console device. Errors are indicated by the following.
1.

The program halts when an instruction sequence is not
correctly executed.

The program halts in the trap vector area for various
traps.

NOTE
When a halt occurs, the console ODT M command can be used
to determine how the halt mode was invoked. When the system
fails to successfully execute the above diagnostics, maintenance diagnostic programs should be used to thoroughly test
processor (and memory) functions.
DX<CR> or RXV 11 floppy disk system bootstrap. Entering the DX <CR>
command starts the memory-modifying CPU instruction test
DXn<CR>
and memory test execution (see the XC and XM commands).
Successful test execution results in execution of the bootstrap program for disk drive 0, the system disk. Otherwise,
specify the drive number (n) as 0 (drive 0) or 1 (drive 1).

559

M9400
REV 11 ROM Program Commands (Cont)
Command

Function
Floppy disk bootstrap errors are:
1.

The program halts and the console device displays the
following.

165316
@

This indicates that the device done flag in the RXV 11 interface was not set within the required time (approximately
1.3 seconds). The bootstrap can be restarted by entering
the P command; the $ is then displayed on the console device and the bootstrap command can be entered.
2.

The program halts and the console displays the following.

165644
@

This indicates that a bootstrap error occurred. The
RXV 11's error register contents are stored in R2. By examining the contents of R2 and using the information
contained in the RXV11 User's Manual, the exact nature
of the error can be determined. Examine the contents of
R2 (nnnnnn) as follows.
@ R2/nnnnnn<CR>
@P
$

After examining R2, the bootstrap can be restarted by the
P command; enter the desired bootstrap command immediately after the $ prompt character.
3.

The program halts in the trap vector for traps; a timeout
trap returns the program to the $ prompt character. If a
timeout trap occurs, first check for proper system cable
connections and device interface module installation.
Then, attempt to bootstrap the system by again entering
the desired bootstrap command.

560

M9400
REV 11 ROM Program Commands (Cont)
Command

Function

OK <CR>
or
DKn<CR>

Disk Drive System Bootstrap. Entering the OK command
starts the memory-modifying CPU instruction test and memory test execution (see the XC and XM commands). Successful test execution results in execution of the bootstrap program for disk drive 0, the system disk. Otherwise, specify the
drive number n as (drive 0), 1 (drive 1), or 2 (drive 2).

Disk bootstrap errors are:
1.

The program halts and the console device displays the
following.

165724
@

This indicates that the device done flag in the RKF 11-0
interface was not set within the required time (approximately 1.3 seconds). The bootstrap can be started by
entering the P command; the $ is then displayed on the
terminal and the bootstrap command can be entered.
2.

The program halts and the console then displays the following.

165644
@

This indicates that a bootstrap error occurred. The
RKV 11-0 error register contents are stored in R2. By examining the contents of R2 and using the information
contained in the RKV11-D User's Guide, EK-RKV11-0P,
the nature of the error can be determined. Examine the
contents of R2 (nnnnnn) as follows:

@R2/nnnnn<CR>
@P
$

After examining R2, the bootstrap can be restarted by the
P command; enter the desired bootstrap command immediately after the $ prompt character.

561

M9400
REV11 ROM Program Commands (Cont)
Command

Function
3.

AL<CR>

Absolute Loader program, normal (absolute address) loading
operation. Entering AL <CR> specifies that a paper tape is
to be loaded via the console device (CSR address =
177560). However, another device can be specified by entering the appropriate CSR address. For example, to load paper
tapes in absolute loader format via a device whose CSR address is 177550, enter the following command.
$ AL 177550<CR>

The program responds by first executing the memory-modifying CPU instruction test and memory test (refer to the XC
and XM commands). Successful test execution results in execution of the Absolute Loader program.
A successful program load is indicated when the console device displays the following.

165625
@

The loaded program automatically starts execution, or Absolute Loader errors are:
1.

Checksum error, with the program halting and producing
the following display.

165534
@

Program halts in the trap vector area for traps other than
a timeout trap.

Timeout trap occurs, causing the display of $ on a new
line on the console device.

562

M9400
REV11 ROM Program Commands (Cont)
Command

Function

AR<CR>

Absolute Loader program, relocated loading operation. When
this command is entered, the memory-modifying CPU instruction test and memory test are automatically first executed
(refer to the XC and XM commands), followed by the Absolute
Loader program. Successful execution of the tests results in
the program halting with the following console display.
165412
@

The operator must then enter the appropriate "software
switch register" contents in R4. To select relocated loading,
which uses an address (bias) contained in the software
switch register, enter the following commands.
@ R4/ xxxxxx nnnnnn<CR>
@P

The value nnnnnn is a relocation value selected by the operator as directed in the PDP-II Paper Tape Software Handbook, 11-XPTSA-BO. Observe that the least significant lin"
value entered must be an odd number; this sets the software
switch register (R4) bit 0 to a logical 1, selecting the relocated loading mode. Note that the program being loaded must
be in Position Independent Code (PIC) format for relocated
loading.
When large programs are contained on more than one tape,
the program halts at the end of the first tape. Install the second tape in the reader and enter a "1" in R4 using the OOT
command shown below; resume loading by entering the P
command.
@ R4/xxxxxx 1<CR>
@P

The six octal digits (xxxxxx) are the present contents of R4.
Entering a value of 1 selects relocated loading for the next
program tape, starting at the address following the end of the
previous load operation. The P command allows the Absolute
Loader program execution to continue the loading process
once the software switch register value has been entered.

563

M9400
REV 11 ROM Program Commands (Cont)
Command Function
A successful program load is indicated when the loaded program automatically starts execution, or the console device
displays.
165626
@

Absolute Loader errors are as described for the AL command.

564

RK05

RK05 Disk Drive
The RK05-J disk drive uses a removable disk cartridge and the RK05-F
uses a fixed, dual-density disk cartridge. Both drives are interfaced by the
RKV11-D option. The RKV11-D is set at address 177400 and vector 220.
Applicable diagnostic programs are found in Appendix A.

Related Documentation
RKV 11-D Field Maintenance Print Set (MP-00223-00)
RK05-J Field Maintenance Print Set (MP-ORK05-0J)
RK05-F Field Maintenance Print Set (MP-ORK05-0F)
RKVll-D User's Guide (EK-RKV11-0P)
Microcomputer Interfaces Handbook (EB-20 175-20)
RK05 Disk Drive User's Guide (EK-ORK05-0P)
RK05/05J/05F Maintenance Manual (EK-RK5JF-MM)
RK05 Exercisor Maintenance Manual (EK-RK05X-MM)

I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1I~1~lIl il l l~ l~
RK05 Disk Drive

565

RK05
Controls and Indicators for the RK05, RK05-J, and RK05-F
Controls and
Indicators

Description

RUN/LOAD
(Rocker Switch)

Placing this switch in the RUN position (provided
that all interlocks are safe):
a.
b.
c.
d.

locks the drive front door
accelerates the disk to operating speed
loads the read/write heads
lights the RDY indicator.

Placing this switch in the LOAD position:
a.
b.
c.
d.

unloads the read/write heads
stops the disk rotation
unlocks the drive front door when the disk has
stopped
lights the LOAD indicator.

CAUTION
Do not switch to the LOAD position during a write operation;
this results in erroneous data being recorded.
WT PROT
(Rocker Switch
Spring-Loaded Off)

Placing this momentary contact switch in the PROT
position lights the WT PROT indicator and prevents
a write operation; it also turns off the FAULT indicator, if that is lit.
Depressing this switch in the WT PROT position a
second time turns off the WT PROT indicator and allows a write operation.

PWR (Indicator)

Lights when operating power is present. Goes off
when operating power is removed.

RDY (Indicator)

Lights when:
a.

the disk is rotating at the correct operating
speed

the heads are loaded

no other conditions are present (all interlocks
safe) to prevent a seek, read, or write operation.

Goes off when the RUN/LOAD switch is set to
LOAD.

566

RK05
Controls and Indicators for the RKOS, RKOS-J, and RKOS-F (Cont)
Controls and
Indicators

Description

ON CYL (Indicator)

Lights when:
a.

the drive is in the ready condition

a seek or restore operation is not being performed

the read/write heads are positioned and settled.

Goes off during a seek or restore operation.
FAUL T (Indicator)

Lights when:
a.

erase or write current is present without a write
gate

the linear positioner transducer lamp is inoperative.

Goes off when the WT PROT switch is pressed, or
when the drive is recycled through a run/load sequence.
WT PROT (Indicator) Lights when:
a.
b.

the WT PROT switch is pressed
the operating system sends a WRITE PROTECT
command.

Goes off when the WT PROT switch is pressed a
second time, or when the drive is recycled through a
run/load sequence.
LOAD (Indicator)

Lights when the read/write heads are fully retracted
and the spindle has stopped rotating.

WT (Indicator)

Lights when a write operation occurs. Goes off when
the write operation terminates.

RD (Indicator)

Lights when a read operation occurs. Goes off when
the read operation terminates.

567

RK05
Performance Specifications
Storage Medium
Type

Single-disk magnetic cartridge (RK05, RK05J - removable; RK05F - nonremovable)

Disk Diameter

5.51 cm (14 inches)

Magnetic Heads
Number

Bit Transfer
Transfer Code
Transfer Rate

Double frequency, NRZ recording
1.44 m bit/s

Electrical Requirements
Voltage
Power
Starting Current

115/230 Vac @ 50/60 Hz ± .05 Hz
250 VA
Power only: 1.8 A
Start spindle: 10 A (for 2 seconds)

Model Designation
RK05-AA, RK05J-AA, RK05F-AA, RK05F-FA 95 - 130 Vac @ 60 ± 0.5 Hz
RK05-AB, RK05J-AB, RK05F-AB, RK05F-FB 290 - 260 Vac @ 60 ± 0.5 Hz
RK05-BA, RK05J-BA, RK05F-AC, RK05F-FC 95 - 130 Vac @ 50 ± 0.5 Hz
RK05-BB, RK05J-BB, RK05F-AD, RK05F-FD 190 - 260 Vac @ 50 ± 0.5 Hz

Dimensions and Weight
Width:
Depth:
Height:
Weight:

48 cm (19 in)
67 cm (26.5 in)
27 cm (10.5 in)
50 kg (110 Ib)

568

RK05
Unit Selection
An RK05 disk drive may be configured to respond to a desired unit designation by selecting the appropriate setting on a rotary switch. The rotary
switch is located on the second module in the card cage. The circuit cards
are located behind the prefilter, and may be accessed by removing the rear
cover panel on the bottom side of the disk drive unit. In the RK05-J, the
rotary switch is on the M7700 module. In the RK05-F it is on the M7680.
M7700 OR M7680

r--

"' "-

"--

M7700 or M7680 Placement

Bootstrap Program for RK05
If an RK05 is used in a system that has no hardware bootstrap module, the
disk drive may be booted by entering the following program manually.
@RO/OOOOOO OnOOOO<CR>·
@R 1/000000 177404<CR>
@1000/000000 000005<LF>
001002/000000 010061 <LF>
001004/000000 000006<LF>
001006/000000 012761 <LF>
001010/000000 177400<LF>
001012/000000000002<LF>
001014/000000 012711 <LF>
001016/000000 000005<LF>
001020/000000 105711 <LF>
001022/000000 100376<LF>
001024/000000 005007 <CR>
@1000G
• n = 0 for drive 0; 2 for drive 1; and 4 for drive 2.
569

RK05

o 0 00
DISK DRIVE
UNIT NUMBER
SELECTOR SWITCH

Controller Switches

570

RL01/02

RL01/RL02

RL01/RL02 Disk Drive
The RLO 1 is a 5,000,000 byte disk drive that uses a modified, removable,
5440-style cartridge (RL01K-DC). The RL02 is a dual-density version of the
RLO 1. The RL02 uses an RL02K-DC cartridge. Both the RLO 1 and RL02 use
the RL V 11 interface module. Up to four drives of either type in any combination can be connected to an RL V 11 interface. The RL V 11 is normally
configured for a bus address of 77440X octal with a vector address of 160
octal. For more in-depth information, refer to the RL V 11 (M80 13/80 14)
section. Additional information can be found in the following manuals.
RLOI/RL02 Disk Drive Technical Manual (EK-RL012-TM)
RL VII Technical Description (EK-RLV 11-TD)
RLO 1/RL02 Pocket Service Guide (EK-RLO 12-PG)
RLOI/RL02 Disk Subsystem User's Guide (EK-RL012-UG)
RLO 1 Illustrated Parts Breakdown (EK-ORLO 1-IP)
RL02 Illustrated Parts Breakdown (EK-ORL02-IP)
RLO 1 Field Maintenance Print Set (MP-00527 -00)
RL02 Field Maintenance Print Set (MP-00698-00)
RL V 11 Field Maintenance Print Set (MP-00635-00)
Microcomputer Interfaces Handbook (EB-20 175-20)
SpeCifications RLO 1 /RL02
Medium
Type:

Single platter, top-loading cartridge (similar to IBM 5440).
Embedded servo information.

Capacity:

RLO 1K-DC = 5.2 Mb
RL02K-DC = 10.4 Mb

Cylinders:

RL01 = 256
RL02 = 512

Sectors:

Heads:

571

RL01/02

(A)

LOAD
SWITCH AND
INDICATOR
(B)

UNIT SELECT
PLUG/READY
LIGHT

(D)

WRITE
PROTECT AND
SWITCH INDICATOR

RLO 1jRL02 Controls and Indicators

Data Transfer
MFM (Miller coding) recording; 244 ns cell time; 4.1 megabytes/s (4.9
J,Ls/word).

RL01/RL02 Bootstrap
Ensure that the heads are over cylinder 0 and head 0 is selected by releasing the LOAD switch, waiting for the LOAD indicator to light, then depressing the LOAD switch. After the drive is ready, initialize the controller with a
system initialize. Perform a bit status clear. Load the following program into
memory.
LOC

Contents

Comments

10000
10002
10004
10006

012737
000014
174400
000001

Load CSR

Wait

Start the program at 10000 and allow it to run for a few seconds, halt the
program and restart at 00000.

572

RL01/02
RLO 1 /RL02 Controls and Indicators

Switches

Function

Power ON/OFF
Circuit Breaker
(Located in the
rear of the drive)

In the OFF position, ac power is removed from the
drive.

(A) LOAD

This is a PUSH/PUSH alternating action switch.
When depressed, the RL01/RL02 begins a "cycle
up" sequence, provided that:

In the ON position, ac power is supplied to the drive.

•
•
•
•
•
•

the RLO 1/RL02K cartridge is installed
the cartridge cover is in place
the access door is closed
all ac and dc voltages are within spec
the R/W heads are retracted
the brushes are in the "home" position.

When released, the RL01/RL02 will begin a "cycle
down" sequence.
(B) UNIT SELECT
PLUG

This is a cam-operated switch that is activated by inserting a numbered, cammed button. The switch
contacts are binary encoded so that the drive assumes the logical unit number that is printed on the
button.

(D) WRITE PROTECT This is an alternating action PUSH/PUSH switch.
When depressed, the drive assumes a write protect
status (during a write operation). When released,
the drive is no longer write protected.

573

RL01/02
RL01/RL02 Controls and Indicators (Cont)
Indicators

Function

(A) LOAD (Yellow)

Indicates that the drive is ready to have a cartridge
loaded (or unloaded). The LOAD indicator will light
when:
•
•
•

the spindle is stopped
the R/W heads are "home"
the brushes are "home."

(8) READY (White)

When lit, indicates a "drive ready" condition; i.e.,
the heads are loaded and detented.

Indicates when one of the following has occurred.
•
•
•
•
•
•
•

drive select error
seek timeout error (1.5 second)
write current in heads during "sector time"
loss of system clock from RL V 11
write data error (no transitions)
spin error (over speed or 40 sec timeout)
write gate error (attempting to write when not
ready, when write protected, or during sector
time)

(D) WRITE PROTECT Indicates that drive is write protected. That is, write
(Yellow)
operations to the cartridge will be inhibited (and the
FAULT indicator will light).

574

RX01

RX01 Floppy Disk Drive
The RXO 1 floppy disk drive is part of the RXV 11 floppy disk system, and is
interfaced by the RXV 11 interface module (M7946). The disk system uses
address 177170 and vector 264 for the first option, and address 177174
and vector 270 for a second option.

[llmmll~lllllllli:lilil~IIIIIIIII~11
RXO 1 Floppy Disk

Model Designations
RXV 11-AA Single Drive System, 115 V /60 Hz
RXV 11-AC Single Drive System, 115 V /50 Hz
RXV 11-AD Single Drive System, 230 V /50 Hz
RXV 11-BA Dual Drive System, 115 V /60 Hz
RXV 11-BC Dual Drive System, 115 V /50 Hz
RXV 11-BD Dual Drive System, 230 V /50 Hz

575

RX01
Related Documentation
RXV11 User's Manual (EK-RXV11-00)
RXO 1/RXB/RX11 Floppy Disk System Maintenance Manual (EK-RXO 1-MM)
RXV 11 Field Maintenance Print Set (MP-00024-00)
RXO 1 Field Maintenance Print Set (MP-00296-00)
RXO 1/RX02 Reference Card (EK-RXO 1-RC)
Microcomputer Interfaces Handbook (EB-20175-20)

NOTE
50 Hz versions are available in voltages of 105, 115, 220, and
240 Vac by field-pluggable conversion. Refer to the
RX01/RXB/RX11 Floppy Disk System Maintenance Manual for
complete input power modification details.

AC Power
The RXV 11 floppy disk system is available in the following three ac voltage/model configurations.

Models

Voltage/Frequency

RXV11-AA, -BA
RXV11-AC, -BC
RXV11-AD, -BD

100 Vac-132 Vac, 60 Hz
100 Vac-132 Vac, 50 Hz
180 Vac-264 Vac, 50 Hz, in one of two voltage
ranges. The actual voltage range is user-selected by
installing the appropriate power harness during system installation, as follows.
Voltage
Range

Power Harness
PN

180-240
200-264

70-10696-04
70-10696-03

Power Consumption
RX01

RXV 11 interface (M7946)
Power input (ac)

3 A at 24 V (dual), 75 W;
5 A at 5 V, 25 W
Not more than 1.5 A at 5 Vdc
4Aat 115Vac
2 A at 230 Vac

576

RX01
Bootstraps for Manual Entry
Full Length Version

Abbreviated Version
(Drive 0 Only)

@1000/000000 12702<LF>
001002/0000001002n7<LF>*
001004/000000 12701<LF>
001006/000000 177170<LF>
001010/000000 130211<LF>
001012/000000 1776<LF>
001014/000000 112703<LF>
001016/0000007<LF>
001020/000000 101 OO<LF>
001022/000000 10220<LF>
001024/000000402<LF>
001026/000000 1271 O<LF>
001030/000000 1 <LF>
001032/000000 6203<LF>
001034/000000 103402<LF>
001036/000000 112711 <LF>
001040/000000 111 023<LF>
001042/000000 32011 <LF>
001044/000000 1776<LF>
001046/000000 100756<LF>
001050/000000 103766<LF>
001052/000000 105711 <LF>
001054/000000 100771 <LF>
001056/0000005000<LF>
001060/000000 2271 O<LF>
001062/000000 240<LF>
001064/000000 1347<LF
001066/000000 122702<LF>
001070/000000 247 <LF>
001072/000000 5500<LF>
001074/0000005007<CR>

@1000/000000 5000<LF>
001002/000000 12701<LF>
001004/000000 177170<LF>
001006/000000 105711 <LF>
001010/000000 1776<LF>
001012/000000 12711 <LF>
001014/000000 3<LF>
001016/000000 5711<LF>
001020/000000 1776<LF>
001022/000000 100405<LF>
001024/000000105711<LF>
001026/000000 100004<LF>
001030/000000 116120<LF>
001032/0000002<LF>
001034/000000 770<LF>
001036/000000 O<LF>
001040/0000005007<CR>

*n = 4 for unit 0
n = 6 for unit 1
<LF> = Line Feed
<CR> = Carriage Return
Starting address = 1000

577

RX02

RX02 Floppy Disk Drive
The RX02 is part of the RXV11-XX floppy disk system. The RXV21-8X options use the RX02 in double-density mode with the RXV21 (M8029) interface module. The RXV21-DX options use the RX02 in single-density mode
with the RXV 11 (M7946) interface module.

mRtImo RX02

Front View of the Floppy Disk System
The density mode of the RX02 is selected by switches on the M7744 controller module. This module is located in the RX02 floppy disk drive. The
following switch settings define the mode of the RX02.
Controller Configuration Switch Settings
(Located on M7744 Module)
Interface

51-1

51-2

RX211 jRXV21
RX8EjRX 11 jRXV 11
RX28

OFF
ON
OFF

ON
OFF
OFF

NOTE
The subject of the RX02 as used in a PDP-8 system is beyond
the scope of this document.
Detailed configuration and diagnostic information is contained in this manual. Refer to the section covering the applicable interface (M7946 or
M8029).
578

RX02
Related Documentation
RX02 Floppy Disk System User's Guide (EK-ORX02-UG)
RXO 1/RX02 Reference Card (EK-RX 102-RC)
Microcomputer Interface Handbook (EK-20175-20)
RX02 Print Set (MP-00629-00)

Module Designations
RXV21

-DA
-DC
-DD

M7946
M7946
M7946

RX02-DA
RX02-DC
RX02-DD

115 V, 60 Hz
115 V, 50 Hz
230 V, 50 Hz

-BA
-BC
-BD

M8029
M8024
M8027

RX02-BA
RX02-BC
RX02-BD

115 V, 60 Hz
115 V, 50 Hz
230 V, 50 Hz

Power Requirements
The RX02 is designed to use either a 60 Hz Vac or a 50 Hz power source.
The 60 Hz version will operate from 90 Vac-128 Vac, without modifications,
and will use less than 4 A operating. The 50 Hz version will operate within
four voltage ratings and will require field verification/modification to ensure
that the correct voltage option is selected. The voltage ranges of 90
Vac-120 Vac and 184 Vac-240 Vac will use less than 4 A operating. The
voltage ranges of 100 Vac-128 Vac and 200 Vac-256 Vac will use less
than 2 A. Both versions of the RX02 will be required to receive the input
power from an ac source (e.g., 861 power control) that is controlled by the
system's power switch.

Input Power Modification Requirements
The 60 Hz version of the RX02 uses the H771-A power supply and will operate on 90 Vac-128 Vac, without modification. To convert to operate on a
50 Hz power source in the field, the H771-A supply must be replaced with
an H771-C or -D and the drive motor belt and drive motor pulley must be
replaced. The H771-C operates on a 90 Vac-120 Vac or 100 Vac-128 Vac
power source. The H771-D operates on a 184 Vac-240 Vac or 200
Vac-256 Vac power source. To convert the H771-C to the higher voltage
ranges or the H771-D to the lower voltage ranges, the power harness and
circuit breaker must be changed. The appropriate jumper and circuit breaker are shown in the following figure.

579

RX02
JUMPER P1

SHIPPING
RESTRAINT (RED)
VOLTAGE (VAC)

JUMPER

CIRCUIT BREAKER

90-120
100-128
184-240
200-256

70-10696-02
70-10696-01
70-10696-04
70- 10696-03

3_5 A, 12-12301-01
3.5 A, 12-12301-01
1.75 A, 12-12301-00
1.75 A, 12-12301-00

RX02 (Rear View)

Bootstrap for Manual Entry (ODT)
RX02/RXV 11 (M7946)
@1000/XXXXXX
1002/XXXXXX
1004/XXXXXX
1006/XXXXXX
1010/XXXXXX
1012/XXXXXX
1014/XXXXXX
1016/XXXXXX
1020/XXXXXX
1022/XXXXXX
1024/XXXXXX
1026/XXXXXX
1030/XXXXXX
1032/XXXXXX
1034/XXXXXX
1036/XXXXXX
1040/XXXXXX
1042/XXXXXX
@1000G

5000<LF>
12701<LF>
177170<LF>
105711<LF>
1776<LF>
12711<LF>
3<LF>
5711<LF>
1776<LF>
100405<LF>
105711 <LF>
1000004<LF>
116120<LF>
2<LF>
770<LF>
O<LF>
5000<LF>
110<CR>

<LF> = Line Feed.
<CR> = Carriage Return.
XXXXXX = Original contents of location opened.
580

RX02
RX02/RXV21 (M8029)
@2000/XXXXXX
2002/XXXXXX
2004/XXXXXX
2006/XXXXXX
2010/XXXXXX
2012/XXXXXX
2014/XXXXXX
2016/XXXXXX
2020/XXXXXX
2022/XXXXXX
2024/XXXXXX
2026/XXXXXX
2030/XXXXXX
2032/XXXXXX
2034/XXXXXX
2036/XXXXXX
2040/XXXXXX
2042/XXXXXX
2044/XXXXXX
2046/XXXXXX
2050/XXXXXX
2052/XXXXXX
2054/XXXXXX
2056/XXXXXX
2060/XXXXXX
2062/XXXXXX
2064/XXXXXX
2066/XXXXXX
2070/XXXXXX
2072/XXXXXX
2074/XXXXXX
2076/XXXXXX
2100/XXXXXX
2102/XXXXXX
2104/XXXXXX
2106/XXXXXX
2110/XXXXXX
2112/XXXXXX
2114/XXXXXX
2116/XXXXXX
2120/XXXXXX
2122/XXXXXX
2124/XXXXXX

12701<LF>
177170<LF>
12700<LF>
100240<LF>
5002<LF>
12705<LF>
200<LF>
12904<LF>
401 <LF>
12703<LF>
177172<LF>
10011 <LF>
1776<LF>
100440<LF>
12711<LF>
407<LF>
10011<LF>
1776<LF>
100433<LF>
110413<LF>
304<LF>
30011 <LF>
1776<LF>
110413<LF>
304<LF>
30011 <LF>
1776<LF>
100422<LF>
12711<LF>
408<LF>
10011 <LF>
1776<LF>
100415<LF>
10513<LF>
30011 <LF>
1776<LF>
100411 <LF>
10213<LF>
6052<LF>
60502<LF>
122474<LF>
120427<LF>
7<LF>

581

RX02
RX02/RXV21 {M8029){Con~
2126/XXXXXX
2130/XXXXXX
2132/XXXXXX
2134/XXXXXX
@2000G

3737<LF>
5000<LF>
5007<LF>
O<CR>

582

APPENDIX A
DIAGNOSTIC MEDIA AVAILABILITY

Module
Number

Option
Name

M7264-XX KD11-F/
KD11-H/
KD11-HW
(LSI-11)

Diagnostic
and DEC/X11
Diagnostic and
File Names
Notes DEC/X11 Module Titles

VKAB??BI?
VKAC??BI?

VKAD??BI?

VKAH??BI?
VKAI??BI?

VKAJ??BI?

VKAL??BI?

XCPA??OBJ
XCPB??OBJ

(Listing)
(Binary PT)
(Listing)
LSI-11 EIS Instruction Set Test
(Binary PT)
(Listing)
LSI-11 FIS Instruction Set Test
(Binary PT)
(Listing)
LSI-11 Traps Test
(Binary PT)
(Listing)
LSI-11 4K System Exerciser
(Binary PT)
(Listing)
LSI-11 DIS Move & String Test
(Binary PT)
(Listing)
LSI-11 DIS Decimal Instructions
(Binary PT)
(Listing)
LSI-11 Trap Test (30K + FIS)
(Binary PT)
DEC/X11 Processor Test Module (Listing)
(Binary PT)
(Listing)
DEC/X 11 EIS Exerciser Module
(Binary PT)

LSI-11 Basic Instruction Test

VKAA??BI?

Listing
and
Paper Tape
PNs
AC-8186C-MC
AK-8188C-MC
AC-8190A-MC
AK-8192A-MC
AC-8194C-MC
AK-8197C-MC
AC-8198C-MC
AK-8-IC-MC
AC-8210A-MC
AK-8212A-MC
AC-8214A-MC
AK-8217A-MC
AC-8218A-MC
AK-8221A-MC
AC-FO 12A-MC
AK-F014A-MC
AC-E664G-MC
AK-E665G-MC
EC-E667 J-MC
AK-E668J-MC

R R

R R R

X X

L L
0 0
5 1 2

0
1 2

13 18 19 20

13 18 1920

13 18 19 20

14 18 1920

Module
Number

Option
Name

Diagnostic
and DECjX11
Diagnostic and
File Names
Notes DECjX 11 Module Titles

M7269

RKV11-D

ZRKH??BI?

7,8

ZRKI??BI?

ZRKJ??BI?

ZRKK??BI?

7,9

ZRKL??BI?

7,10

XRKA??OBJ

M7270

KD11-HA

VKAA??BI?
VKAB??BI?
VKAC??BI?

VKAD??BI?

VKAH??BI?
XCPA??OBJ
XCPB??OBJ

RK 11 jRK05 Performance
Exerciser
RK 11 Utility Package

Listing
and
Paper Tape
PNs

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
RK11 Basic Logic Test No.1
(Binary PT)
RK 11 Basic Logic Test No.2
(Listing)
(Binary PT)
RK11jRK05 Dynamic Test
(Listing)
(Binary PT)
DECjX 11 RK 11 Exerciser Module (Listing)
(Binary PT)

AC-9232G-MC
AK-9235G-MC
AC-9236F-MC
AC-9239F-MC
AC-9240E-MC
AK-9243E-MC
AC-9244F-MC
AK-9247F-M1
AC-9248E-MC
AK-9251E-MC
AC-E676G-MC
AK-E677G-MC

LSI-11 Basic Instruction Test

AC-8186C-MC
AK-8188C-MC
AC-8190A-MC
AK-8192A-MC
AC-8194C-MC
AK-8197C-M1
AC-8198C-MC
AK-820 1C-MC
AC-8210A-MC
AK-8212A-MC
AC-E664G-MC
AK-E665G-MC
AC-E667 J-MC
AK-E668J-MC

(Listing)
(Binary PT)
(Listing)
LSI-11 EIS Instruction Set Test
(Binary PT)
LSI-11 FIS Instruction Set Test
(Listing)
(Binary PT)
LSI-11 Traps Test
(Listing)
(Binary PT)
(Listing)
LSI-11 4K System Exerciser
(Binary PT)
DECjX11 Processor Test Module (Listing)
(Binary PT)
DECjX 11 EIS Exerciser Module
(Listing)
(Binary PT)

R R
X X

R
K
0
5

R R
L L

0
2

13 18 1920

13 18 19 20

13 18 1920

16 18 1920

13 18 19 20

13 18 1920

14 18 1920

0
1

0
2

Module
Number

Option
Name

Diagnostic
Diagnostic and
and DEC/X11
Notes DEC/X11 Module Titles
File Names

M7940

DLV11

VKAE??BI?

11a,12 DLV11 Test

XDLA??OBJ

11a

VKAF??BI?

DRV11 Test

XDRA??OBJ

DEC/X11 DR11-A Exerciser
Module

M7941

())

DRV11

Listing
and
Paper Tape
PNs

R R
X X

R R R
K L L

0
2

13 18 1920

14 18 1920

13 18 1920

13 18 19 20

(Listing)
(Binary PT)
DEC/X11 DL 11 Exerciser Module (Listing)
(Binary PT)

AC-8202B-MC
AK-8205B-MC
AC-E709J-MC
AK-E710J-MC

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8206D-MC
AK-8208D-MC
AC-E854D-MC
AK-E855D-MC

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048F-MC

(Listing)
(Binary PT)
(Listing)
RX 11 Interface Diagnostic
(Binary PT)
DEC/X11 RX01 Exerciser Module (Listing)
(Binary PT)

AC-9334E-MC
AK-9337E-MC
AC-9339F-MC
AK-9343F-MC
AC-E736E-MC
AK-E737E-MC

13 18 1920

16 18 1920

M7942

MRV11-AA

M7944

MSV11-B

ZKMA??BI?

MOS/Core 0-124K Exerciser

ZQMC??BI?

0-124K Memory Exerciser (16K)

ZRXA??BI?

7,14

RX11 System Reliability TEST

ZRXB??BI?

XRXA??OBJ

M7946

RXV11

12 13 18 19 20

Module
Number

Option
Name

Diagnostic
Diagnostic and
and DECjX11
Notes DECjX 11 Module Titles
File Names

M7948

DRV11-P

M7949

LAV11

ZLAE??BI?

LA 180 Printer Diagnostic

XLPA??OBJ

M7950

DRV11-B

VDRA??BI?

13,15

VDRB??BI

M7951

DUV11-DA

XDRF??OBJ

ZDUQ??BI?

ZDUR??BI?

ZDUS??BI?

ZDUT??BI?

ZDUU??BI?

ZDUV??BI?

XDUA??OBJ

Listing
and
Paper Tape
PNs

(Listing)
(Binary PT)
DECjX 11 LP 11 Exerciser Module (Listing)
(Binary PT)

AC-8906B-MC
AK-8908B-MC
AC-E670F-MC
AK-E671 F-MC

DRV 11-B DMA Interface
Diagnostic
DRV 11-B Interprocessor
Exerciser
DECjX 11 DRV 11-B Exerciser
Module

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8178A-MC
AK-8180A-MC
AC-8182A-MC
AK-8184A-MC
AC-E739C-MC
AK-E740C-MC

(Listing)
(Binary PT)
DUV 11 Off-Line Receiver Tests
(Listing)
(Binary PT)
DUV 11 Off-Line Receiver Timing (Listing)
(Binary PT)
DUV 11 Off-Line Transmitter Tests (Listing)
(Binary PT)
DUV 11 Off-Line Timing & Interrupt (Listing)
(Binary PT)
DUV11 Off-Line Combined Tests (Listing)
(Binary PT)
DECjX 11 DU 11 Exerciser Module (Listing)
(Binary PT)

AC-8704C-MC
AK-8707C-MC
AC-8708B-MC
AK-8711B-MC
AC-8712B-MC
AK-8715B-MC
AC-8716B-MC
AK-8719B-MC
AC-8720B-MC
AK-8723B-MC
AC-8724B-MC
AK-8727B-MC
AC-E7181-MC
AK-E7191-MC

DUV11 Off-Line Logic Tests

R R

X X
0 0
1 2

0
5

L L
0 0
1 2

13 18 1920

14 18 19 20

15 18 1920

14 18 19 20

12 15 18 19 20
12 15 18 19 20
12 15 18 19 20
12 15 18 19 20
12 15 18 19 20
12 15 18 19 20
5

14 18 19 20

Module
Number

Option
Name

Diagnostic
and DEC/X11
Diagnostic and
File Names
Notes DEC/X 11 Module Titles

M7952

KWV11-A

VKWA??BI?

17,18
19,20
21

XKWE??OBJ

M7954

IBV11-A

M7957

MSV11-C

DZV11

DEC/X 11 KWV 11-K Exerciser
Module
IBV 11-A Diagnostic

XIBA??OBJ

22,23
24
22,23
24
25

ZKMA??BI?

MOS/Core 0-124K Exerciser

ZQMC??BI?

0- 124K Memory Exerciser (16K)

VDZA??BI?

26,27

VDZB??BI?

26,27

VDZC??BI?

26,27

DZV 11 4 Line Asynch
MUX 1 OF 2
DZV 11 4 Line Asynch
MUX 2 OF 2
DZV11 Cable and Echo Test

VIBA??BI?
VIBB??BI?

M7955

KWV 11-A Diagnostic

IBV 11-A (30K) Diagnostic
IBV 11-A Exerciser Module

VDZD??BI?

DZV 11 Overlay for ITEP

XDZB??OBJ

DEC/X 11 DZV 11 Exerciser
Module

Listing
and
Paper Tape
PNs

R R
X X

R R R
K L L

0
5

0
2

0
1

0
2

(Listing)

AC-8222C-MCM 4

13 18 19 20

(Binary PT)
(Listing)

AK-8225C-MC
AC-E920B-MC

14 18 19 20

15 18 19 20

(Binary PT)

AK-E921B-MC

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-A880A-MC
AK-A882A-MC
AC-FO 15A-MC
AK-F017A-M1
AC-E914D-MC
AK-E915D-MC

14 18 19 20

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048F-MC
AC-A877 A-MC
AK-A879A-MC
AC-A938A-MC
AK-A940A-MC
AC-A941A-MC
AK-A943A-MC
AC-A935A-MC
AK-A937 A-MC
AC-E911 C-MC
AK-E912C-MC

13 18 19 20

12 15 18 19 20

12 13 18 19 20
9

15 18 19 20

14 18 19 20

Module
Number

Option
Name

Diagnostic
and DEC/Xll
Notes
File Names

M8012

BDV11-AA

VM8A??BI?

28,29
30

XBMD??OBJ

M8013/
M8014

RLV11

Diagnostic and
DEC/Xll Module Titles

Listing
and
Paper Tape
PNs

BDV 11-AA Diagnostic

(Listing)
(Binary PT)
DEC/X 11 LSI-11 BDV 11 Exerciser (Listing)
(Binary PT)

(Xl
(Xl

13 18 1920

18 1920

AC-B 107B-MC
AK-B109B-MC
AC-F111B-MC
AK-F 108B-MC
AC-F 115B-MC

10 17

18 19 20

10 17

18 1920

10 17

18 1920

10 17

18 1920

10 17

18 1920

10 17

18 1920

11 17

18 1920

11 17

18 1920

11 17

18 1920

RL 11 /RL V 11 Controller Test 1

ZRLH??BI?

7,32
33·

RL 11 /RL V 11 Controller Test 2

ZRLI??BI?

7,34

RL01/02 Drive Test 1

(Binary PT)
(Listing)

AK-F 112B-MC
AC-F 119C-MC

(Binary PT)
(Listing)
(Binary PT)
(Listing)

AK-F116C-MC
AC-F 123B-MC
AK-F 120B-MC
AC-F 127B-MC

(Binary PT)
RL01/02 Drive Compatibility Test (Listing)
(Binary PT)
(Listing)
RL01/02 Bad Sector File Tool

AK-F 124B-MC
AC-F 131 B-MC
AK-F 128B-MC
AC-F 135B-MC

ZRLJ??BI?

7,36

RL01/02 Drive Test 2

ZRLK??BI?

7,35
37

RLO 1/02 Performance Exerciser

ZRLL ??BI?

7,35

ZRLM??BI?

7,35
38

ZRLN??BI?

7,39
40 ,.
7

XRLA??OBJ

RL01/02 Drive Test 3
RL11/RLV11/RL01/RL02
Exerciser

0 0 0
5 1 2

AC-B061 C-MC
AK-B063C-MC
AC-F060C-MC
AK-F061C-MC

7,31

35 •

0
2

ZRLG??BI?

(]1

R R R
K L L

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)

RLV11 RL01 Diskless Test

VRLA??BI?

R R
X X

(Binary PT) AK-F 132B-MC
(Listing)
AC-F843A-MC
(Binary PT) AK-F844-MC
(Listing)
AC-E965D-MC
(Binary PT) AK-E966D-MC

Listing
and
Paper Tape
PNs

R
X
0
1

R
X
0
2

(Listing)
(Binary PT)

AC-A883A-MC
AK-A885A-MC

13 18 19 20

(Listing)
(Binary PT)
DEC/X 11 DL 11 Exerciser Module (Listing)
(Binary PT)

AC-B 150B-MC
AK-B 152B-MC
AC-E709J-MC
AK-E710J-MC

13 18 19 20

14 18 1920

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-E 102A-MC
AK-E104A-MC
AC-E992B-MC
AK-E993B-MC

13 18 1920

14 18 1920

(Listing)
(Binary PT)
(Listing)
(Binary PT)
0-124 K Memory Exerciser (16K) (Listing)
(Binary PT)

AC-B153A-MC
AK-B 155A-MC
AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048F-MC

15 18 1920

13 18 1920

LA 180 Printer Diagnostic

AC-8906B-MC
AK-8908B-MC
AC-E670F-MC
AK-E671F-MC

Module
Number

Option
Name

Diagnostic
Diagnostic and
and DEC/X11
File Names
Notes DEC/X11 Module Titles

M8016

KPV11-X

VKPA??BI?

41,42
43

KPV 11-A Diagnostic

M8017

DLV11-E

VDVA??BI?

llb

DLV11-E Off-Line Test

XDLA??OBJ

llb

VKUA??BI?

KUV 11-AA (LSI WCS) Diagnostic

XKUA??OBJ

DEC/Xl1 KUVll-AA Exerciser
Module

M8018

KUV11-AA

ex>

M8021

M8027

MRVll-BA

LPV11

VMRA??BI?
ZKMA??BI?

4a,46

ZQMC??BI?

4b,46

ZLAE??BI?
XLPA??OBJ

LSI-ll UVPROM-RAM
(MRVll-BA) Test
MOS/Core 0-124K Exerciser

(Listing)
(Binary PT)
DEC/X 11 LP 11 Exerciser Module (Listing)
(Binary PT)

R R R
K

0
5

0 0
1 2

12 13 18 1920

13 18 1920

14 18 1920

Module
Number

Option
Name

Diagnostic
and DECjX11
Diagnostic and
File Names
Notes DECjX 11 Module Titles

M8028

DLVll-F

VDVC??BI?

lla

XDLA??OBJ

l1a

ZRXC??BI?

ZRXD??BI?

ZRXE??BI?

ZRXF??BI?

XRXB??OBJ

VDLA??BI?

47,48

XDLA??OBJ

MSVll-DXj ZKMA??BI?
MSVll-EX
ZQMC??BI?

M8029

RXV21

(J1

co
o

M8043

M8044/
M8045

DLV11-J

DLVll-F Off-Line Test

Listing
and
Paper Tape
PNs

,(Listing)
(Binary PT)
DECjX 11 DL 11 Exerciser Module (Listing)
(Binary PT)

AC-E0068-MC
AK-E008B-MC
AC-E709J-MC
AK-E710J-MC

(Listing)
(Binary PT)
RX02 SS Performance Exerciser (Listing)
(Binary PT)
RX02 Formatter Program
(Listing)
(Binary PT)
RX02 FCTNjLog
(Listing)
(Binary PT)
DECjX 11 RX02 Exerciser Module (Listing)
(Binary PT)

AC-E509A-MC
AK-E511A-MC
AC-E512B-MC
AK-E514B-MC
AC-E622A-M2
AK-E624A-M2
AC-E625A-MC
AK-E627A-M 1
AC-F098C-MC
AK-Fl00C-MC

(Listing)
(Binary PT)
DECjX 11 DL 11 Exerciser Module (Listing)
(Binary PT)

AC-E 188B-MC
AK-E 19OB-MC
AC-E709J-MC
AK -E71 OJ-MC

RX02 Utility Driver

DLVll-J Test

(Listing)
AC-8850F-MC
(Binary PT) AK-8854F-MC
0-124K Memory Exerciser (16K) (Listing)
AC-9045F-MC
(Binary PT) AK-9048F-MC

MOS/Core 0-124K Exerciser

R R

R R R

X X
0 0
1 2

L L
0 0
1 2

13 18 19 20

14 18 19 20

13 18 1920

13 18 19 20

16 18 19 20

15 18 19 20

14 18 1920

13 18 1920

12 13 18 19 20

Module
Number

Option
Name

Diagnostic
and DEC/X11
Diagnostic and
File Names
Notes DEC/X11 Module Titles

M8047

MXV11-AX

VMXA??BI?

ZKMA??BI?

ZQMC??BI?

XDLA??OBJ

MXV 11-AX Diagnostic

(Listing)
(Binary PT)
(Listing)
MOS/Core 0-124K Exerciser
(Binary PT)
0-124K Memory Exerciser (16K) (Listing)
(Binary PT)
DEC/X11 DL 11 Exerciser Module (Listing)
(Binary PT)

AC-E656A-MC
AK-E658A-MC
AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048F-MC
AC-E709J-MC
AK-E710J-MC

(Listing)
(Binary PT)
(Listing)
(Binary PT)

(Listing)
(Binary PT)
DCF11-AA Diagnostic
(Listing)
(Binary PT)
KEF11-AA Diagnostic no. 1
(Listing)
(Binary PT)
KEF 11-AA Diagnostic no. 2
(Listing)
(Binary PT)
DEC/X11 Processor Test Module (Listing)
(Binary PT)
(Listing)
DEC/X 11 EIS Exerciser Module
(Binary PT)
DEC/X11 FP11 Exerciser Module (Listing)
(Binarv PT)

M8048

MRV11-C

M8049

DRV11-J

VDRC??BI?

DRV11-J Diagnostic Test Part 1

VDRD??BI?

DRV11-J Diagnostic Test Part 2

JKDA??BI?

KTF 11-AA Diagnostic

0'1

M81~9

KDF11-A

JKDB??BI?
JKDC??BI?
JKDD??BI?
XCPA??OBJ
XCPB??OBJ
XFPA??OBJ

Listing
and
Paper Tape
PNs

R R
X X

R R R
K L L

0
2

12 15 18 19 20
4

13 18 19 20

12 13 18 19 20
5

14 18 19 20

AC-F756AcM 1
AK-F757A-M1
AC-F759A-MC
AK-F760A-MC

15 18 19 20

AC-F 138C-MC
AK-F 136C-MC
AC-F141C-M1
AK-F 139C-MC
AC-F241B-MC
AK-F240B-MC
AC-F244B-MC
AK-F243B-MC
AC-E664G-MC
AK-E665G-MC
AC-E667 J-MC
AK-E668J-MC
AC-E742G-MC
AK-E743G-MC

13 18 1920

13 18 19 20

14 18 19 20

14 18 1920

14 18 19 20

Module
Number

Option
Name

M9400/
M9401

REV11-X/
TEV11/
BCV1X

ZM9A??BI?

Bootstrap/Terminator Test

XBMC??OBJ

DEC/X11 Bootstrap/Terminator

ADV11-A

VADA??BI?

ADV 11 Performance Test

XADC??OBJ

2,3

DEC/X 11 ADV 11 Exerciser
Module

A012

A6001

G653/
H223

AAV11-A

MMV11-A

Listing
and
Paper Tape
PNs

Diagnostic
Diagnostic and
and DEC/X11
File Names
Notes DEC/X11 Module Titles

VAAA??BI?

AAV11 Diagnostic Test

XAAC??OBJ

DEC/X 11 AAV 11 Exerciser
Module

ZKMA??BI?

ZQMC??BI?

R R R
K L L

AC-8954E-MC
AK-8957E-MC
AC-F057N-MC
AK-F058N-MC

13 18 19 20

14 18 1920

(Listing)
AC-8174C-MC
(Binary PT) AK-8176C-MC
(DOC/PT Kit'
ZJ250-RB
(Listing)
~C-E923B-MC
(Binary PT) AK-E924B-MC

18 1920

(Listing)
AC-8169A-MC
(Binary PT) AK-8172A-MC
(DOC/PT Kit)
ZJ248-RB
(Listing)
AC-E917B-MC
(Binary PT) AK-E918B-MC

18 19 20

18 1920

(Listing)
(Binary PT)
(Listing)
(Binary PT)

(Listing)
(Binary PT)
0-124K Memory Exerciser (16K) (Listing)
(Binary PT)

MOS/Core 0-124K Exerciser

R R
X X

AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048G-MC

12 13 18 1920

Notes
1.

Wraparound test and auto-tests require Berg test connector 7012894-00.

Requires an analog ground on any channel to be tested.

May be run asynchronously if KWV 11 is present in system. If run
asynchronously, XKWE??OBJ must be deselected from the
DEC/X 11 run.

4a.

Memory space under test should be contiguous and read/write.
For systems having noncontiguous memory, the memory boundaries must be defined by the operator before running the program.
This diagnostic requires 8K of memory space to run in.

4b.

This test will run successfully only on an 11/23 processor with a
minimum of 16K of memory.

LTC must be disabled.

VKAA??BI? and VKAD??BI? should be run on the CPU prior to
running this test.

Scratch media must be mounted in drives to be tested before
starting the diagnostic.

ZRKJ??BI?, ZRKK??BI?, ZRKL ??BI?, and ZRKI??BI? (if needed)
should be run on subsystem before running this test.

ZRKJ??BI? should be run on the sybsystem before running this
test.

10.

ZRKJ??BI? and ZRKK??BI? should be run on the subsystem before running this test.

11 a.

A wraparound test connector must be installed to run this test.
The connector is not available from stock. The F.E. must make
one up himself. The following instructions (excerpted from Tech
Tip PDP-11 /03 TT-11) tell how this is done. The following items
are required:
1 Berg connector
4 Berg pins
#22 wire

(12-10918-15)
( 12-10089-07)
(90-07350-00).

Crimp a short length of wire between two Berg pins. Make up two
sets of these. Install one set from pin F to pin J, anQ one set from
pin E to pin M of the Berg connector.
~-~-::593

11b.

To completely exercise the modem control portion of the DLV11E, a special wraparound connector (H315) must be installed on
the modem end of the I/F cable. This test connector loops back
certain control lines as well as the data lines.

12.

The test has baud rate dependent configuration requirements.

Baud Rate

No. of Stop Bits No. of Bits

110
All others

8
8

13.

Requires BC08R test cable for full test of module's data lines.

14.

ZRXB??BI? should be run on the subsystem before running this
test.

15.

If a REV 11 is in the system, DMA refresh must be disabled and
CPU refresh must be enabled.

16.

H315A connector required for external loopback testing.

17.

If customer hardware is connected to the KWV 11 which could inject signals on ST 1, ST2 or slave in inputs, it must be disconnected from the inputs.

18.

All switches in switch pack 2 should be left off unless you are instructed otherwise.

19.

I/O signal test no. 1 (ST1 in, ST2 out); install a jumper between
J 1-SS (ST2 out) to J 1-VV (ST 1 in).

Switch Pack 2
Switch

State

2
3
4
5
6
7

Off
On
Off
Off
On
On
Not used.

Use a program starting address of 210.

594

20.

I/O signal test no. 2 (clock overflow tests); install a jumper between J1-RR (clock overflow) to J1-TT (ST2 in).

Switch Pack 2
Switch
2
3
4
5

6
7

State
Off
Off
Off
On
Off
On
Not used.

Use a program starting address of 214.
21.

I/O signal test no. 3 (ST 1 out, ST2 in); install a jumper between
J1-UU (ST1 out) to J1-TT (ST2 in).

Switch Pack 2
Switch

State

2
3
4
5
6
7

Off
Off
Off
On
On
On
Not used.

Use a program starting address of 220.
22.

Test may be run with a "known good module" in the system for
comparison. The good module should be located second (electrically) on the bus, with a cable connecting it and the module under test.
"known good module" address - 760160
"known good module" vector - 660

23.

Starting restrictions:
If a free-running clock, such as 60 Hz from the power supply, is
attached to the BEVNT bus line on REV C/O/E systems, an interrupt to location 100 will occur when using the OOT "G" and "L"
commands. This will happen prior to the program executing the
first instruction. This program cannot disable the BEVNT bus line
by inhibiting interrupts.

595

User systems reqUiring a free-running clock attached to the
BEVNT bus line can temporarily avoid this situation by setting the
PSW to 200, loading the PC with the starting address, and then
using the lip" command, instead of using the starting address and
the "G" command.
Before using the ilL" command, the PSW can be set to 200 to inhibit interrupts after loading the absolute loader.
24.

Possible program bombs:
The first two tests check to see if the IBV 11-A responds to the address the program thinks it is at. If not, a bus error occurs.
Bus errors may alter the preset contents of location 4 before the
trap is executed. Program control may be transferred to an area of
the program which is not set up to handle the trap. Or, control may
be passed to some totally unknown and irrelevant piece of code
residing accidently in memory. If this occurs, the program will
most probably bomb, and it may also overwrite parts of itself. If this
occurs, the program must be reloaded before proceeding.

25.

If the IB-bus cable is not removed from the module under test, any
errors which are detected could be from some device out on the
IB-bus and not necessarily from the IBV 11-A.

26.

If run in staggered maintenance mode, an H329 staggered turnaround connector is required.

27.

If run in external maintenance mode, an H325 cable turn-around
connector is required on all lines which have been selected to be
tested.

28.

This test assumes that the module under test resides in the same
backplane where the line time clock is generated.

29.

Test 3 assumes that switch no. 5 of E21 is in the ON position.

30.

For the rocker switch test, the operator should specify the configuration for the module under test.

31.

VRLA??BI? should be run on the subsystem before running this
test.

32.

VRLA??BI? and ZRLG??BI? should be run on the subsystem before running this test.

33.

A KWV 11 programmable line clock is required to run test no. 7.
596

34.

VRLA??BI?, ZRLG??BI?, and ZRLH??BI? should be run on the
subsystem before running this test.

35.

A KWV 11 programmable line clock is required for some tests.

36.

VRLA??BI?, ZRLG??BI?, ZRLH??BI?, and ZRLI??BI? should be
run on the subsystem before running this test.

37.

VRLA??BI?, ZRLG??BI?, ZRLH??BI?, ZRLI??BI?, ZRLJ??BI?,
and ZRLN??BI? should be run on the subsystem before running
this test.

38.

VRLA??BI?, ZRLG??BI?, ZRLH??BI?, ZRLI??BI?, ZRLJ??BI?,
ZRLK??BI, and ZRLN??BI? should be run on the subsystem before running this test.

39.

VRLA??BI?, ZRLG??BI?, ZRLH??BI?, ZRLI??BI?, and ZRLJ??BI?
should be run on the subsystem before running this test.

40.

A KWV 11 programmable line clock is required for tests 1 and 4.

41.

To check the power fail circuitry, nonvolatile memory must be in
the first 4K of memory.

42.

Power up option no. 1 should be selected on the CPU module for
power fail testing.

43.

The module should be in the standard factory configuration.
jumpers in:
jumpers out:

W1-W5, W7, W8, W11, W13-W15
W6, W9, W10, W12

44.

If the test is to be run in all address modes, then an extender card
and a special test cable (17-00124-01) are required.

45.

The exerciser may be run with the module in address modes 1 or 3
only.

46.

This test may be run only if RAM is present on the board.

47.

All channels must be configured to the same bit-word length.

48.

A wraparound connector (H3270) is required for the data
wraparound tests for each of the lines to be tested.

49.

Requires a BC05W-02 cable to be installed between the Berg connectors. The cable should have a half twist in it.

597

10.

JKDB??BI? should be run on the first 16K of memory before running this test.

51.

JKDC??BI? should be run on the module before running this test.

598

Media Availability

01
CO
CO

No.

Media Package
Identifier

Title

Notes

Media PNs

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

CZZGG??
CZZGL??
CZZGO??
CZZGY??
CZZGZ??
CZZHD??
CZZHE??
CZZHG??
CZZHQ??
CZZHZ??
CZZID??
CZZIH??
CZZMC??
CZZMD??
CZZMT??
CZZMU??
CZZMZ??
CZZZD??
CZZLA??
CZZLN??

DXDP + 7 DEC/X 11 EXEC 1
DXDP+ 12 RC,RF,RK11
DXDP+ 15 RX11 DIAG
DXDP + 25 LSI FLP 1
DXDP + 26 DEC/X 11 EXEC 2
DXDP + 30 DEC/X 11 EXEC 3
DXDP+ 31 LSI FLP 2
DXDP + 33 LSI FLP 3
DXDP + 43 LSI FLP 4
DXDP + 52 RL02 DIAG no. 1
DXDP + 56 RL02 DIAG no. 2
DXDP+ 60 LSI FLP 5
DYDP+ 3 LSI-11 no. 1
DYDP+ 4 DEC/X11 no. 1
DYDP + 20 LSI-11 no. 2
DYDP+ 21 DEC/X11 no. 2
DYDP + 26 LSI-11 no. 3
LSI-11 DKDP + Diagnostic PKG
DLDP+ (RL01) Diagnostic PKG no.
DLDP + (RL02) Diagnostic PKG

AS-9645?-M?
AS-9650?-M?
AS-9653?-M?
AS-9663?-M?
AS-9664 ?-M?
AS-9668?-M?
AS-9669?-M?
AS-9671 ?-M?
AS-C638?-M?
AS-F547?-M?
AS-F753?-M?
AS-F804?-M?
BA-F021 ?-M?
BA-F022?-M?
BA-F048?-M?
BA-F049?-M?
BA-F558?-M?
AN-9696?-M?
AX-E380?-M?
BC-F916?-M?

1
1
1
1
1
1
1
1
1
2
2
2
2
2

Documentation
Media Kit PNs
ZJ271-RY

ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RX
ZJ271-RX
ZJ271-RX
ZJ271-RX
ZJ271-RX
ZJ278-RE
ZJ278-RQ
ZJ278-RH

Notes
1.
2.

Documentation/media kit ZJ271-RY contains all of these floppies as well as all of the applicable documentation.
Documentation/media kit ZJ271-RX contains all of these floppies as well as all of the applicable documentation.

APPENDIX B
FLOATING ADDRESSES / VECTORS
FLOATING ADDRESSES
The conventions for the assignment of floating addresses for modules on
. the LSI-11 bus are the same as UNIBUS devices. UNIBUS devices are used
to explain the ranking sequence.
The floating-address convention used for communications and for other devices that interface with the PDP-11 series of products assigns addresses
sequentially starting at 760 010 (or 160 010) and proceeds upward to 763
776 (or 163 776). For the sake of compatibility with UNIBUS conventions,
addresses are expressed as consisting of 18 bits (7XX XXX) rather than 16
bits (1 XX XXX).
Floating addresses are assigned in the following sequence.

Rank

UNIBUS
Device

2
3
4
5
6
7
8
9
10

DJ 11
DH11
DQ11
DU11
DUP11
LK11A
DMC11
DZ11
KMC11
RL 11 (extras)

LSI-11
Device

DUV11

DZV11
RLV 11 (extras)

FLOATING VECTORS
The conventions for the assignments of floating vectors for modules on the
LSI-11 bus will adhere to those established for UNIBUS devices. UNIBUS
devices are used to explain the priority ranking for floa'ting vectors and are
included in the subsequent table of trap and interrupt vector:s as a guide for
the user.
The floating-vector convention used for communications and for devices
that interface with the PDP-11 series of products assigns vectors sequentially starting at 300 and proceeding upward to 777. (Some LSI-11 bus
modules,. such as the DLV 11 and DRV 11, have an upper vector limit of
377.) The following table shows the sequence for assigning vectors to modules. It can be seen that the first vector address, 300, is assigned to the
first DL V 11 in the system. If another DLV 11 is used, it would then be assigned to all the DL V 11 s (up to a maximum of 32); addresses are then assigned consecutively to each unit of the next highest-ranked device
(DRV 11 or DLV 11-E, and so forth), then to the other devices according to
their rank.
601

Ranking for Floating Vectors
(Start at 300 and proceed upward.)
,

Rank

UNIBUS

1
2
3
4
5
6
7
8
9
10
11
12
13
.14
15
16
17
18
19
20

DC11
KL 11, DL 11-A, -B
DP11
DM 11-A
DN11
DM11-BB
DR 11-A
DR 11-C
PA611 Reader
PA611 Punch
DT11
DX11
DL 11-C, -D, -E
DJ11
DH11
GT40
LPS11
DQ11
KW11-W
DU11

602

LSI-11 Bus

DL V 11, -F ,. -J

DRV11-B
DRV11

DLV11-E

KWV11
DUV11