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Document:	KY11-LB Programmer's Console/Interface Module Operation and Maintenance Manual
Order Number:	EK-KY1LB-MM
Revision:	001
Pages:	105
Original Filename:	KY11-LB_MaintMan.pdf

OCR Text

EK-KY1LB-MM-001

KY11-LB programmer’s

console/interface module
operation and maintenance
manual

digital equipment corporation - maynard, massachusetts

st Edition, January 1977

Copyright © 1977 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

‘DECSYSTEM-20

MASSBUS

TYPESET-11

UNIBUS

CONTENTS

e B e

e B

CHAPTER 1

CHAPTER 2

OPERATING CHARACTERISTICS
INTRODUCTION

. ... ...

GENERAL DESCRIPTION

... ... ... ... e

. . . . . . . . . .

FUNCTIONAL DESCRIPTION
SPECIFICATIONS

e s

. . . . . . . . . . . .

. . . . .

Electrical Specifications

. . . . .

Mechanical Specifications

Environmental Specifications

. .

. ...

..o

...

.0,

e e

e e e

e e e e e e e e e e e e e e

FUNCTIONAL DESCRIPTION
. . . .

Console Mode

. . . . . .
. .

i i

. .

. . . . .

MICROPROCESSOR INSTRUCTIONSET

CHAPTER 3

INTERFACE MODULE
MICROPROCESSOR

. . . . . .

State Control

e e e

... .

2.4

General Organization

o e
e

e e

e e e e e e e

. . . . . . . . . . . .
. . . . .. .. .. e

Transition State Diagram

. . . . .. ... e

. . . . . . . . . . .

Address Register

Bus Address Register

3.2.3

Switch Register

3.2.4

Data BusControl

3.2.5

UnibusControl

e ee
e e

e e

. . . . . . . .

. .

.. ..
e

e e e e
e e e e

.. ...
.. .. ..

. . . . . .

e e e e e e e e

. . e

. . . . . . . . .« . .
.

e e e e e e

e e e e e e e e e e e

. . . . . . . . . . . .
. . . . . . .

e e e e

i v v v vt v e

INTERFACE MODULE REGISTERS AND CONTROLS

3.2.2

e e e

. . . .. .. ... ... .....

Microprocessor Timing

3.2.1

e e e e e e e e e e e

. . . . . . . . . . . . .

System Start-Up

s e e e e e

e e e e e e e e

. .

HARDWARE ORGANIZATION

W W W wwww

Maintenance Mode

. . . . . . .
. . @ i

2.3

AWk~

.. .. ... ...

CONTROLS AND INDICATORS

et et ek el ek

e e e e

. . . .

INTRODUCTION

e e e
i

. .

PROGRAMMER’S CONSOLE KEYPAD FUNCTIONS/

CHAPTER 4

e e

. . . .. . .. ..

. . .. ...

2.2

2.2.2

e e e

. . . . . . . . .

. . . .

e e e e

M7859 Interface Module Performance Specifications

2.1

2.2.1

e e

e e e e e

e e e e e e e e e

i v ittt

. . . . . . . . .« . 0 i i i

e e

MICROPROCESSOR INSTRUCTION DESCRIPTION

4.1

DATA AND INSTRUCTION FORMATS

4.2

MICROPROCESSOR INSTRUCTIONS

4.2.1

Index Register Instructions

4.2.2

Accumulator Group Instructions

4.2.3

Program Counter and Stack Control Instructions

4.2.4

Input/Output Instructions

4.2.5

Machine Instruction

. .

. . ... ... .. ... ......
. . . . ..

... .. ...

. .

...

0000,

. . . . . .. .. ... ... ...

. . . . .. .. .. ..

. . . . . . . . .. .. .. 000,
. .

. .

.00 0000 o0

CONTENTS (Cont)

Page

CHAPTER 5

INTERFACE MODULE DETAILED LOGIC DESCRIPTION

5.1

e
e e e e e e e e e e
INTRODUCTION . . . . o et e e e e e e
PROGRAMMER’S CONSOLE KEYPAD FUNCTION SEQUENCES
. . . ..

5-3

Console Mode Key Functions
. .
Maintenance Mode Key Functions
DETAILED LOGIC DESCRIPTION
.
Clock CirCuitry . . . .+ o v o o e
Power-Up Logic/Interrupt
. . . .
MiICTOPIOCESSOT . . v v v v e e e e
Timing State Decoder
. . . . . .
Address Register . . . . . . . . .

5-3
5-5
5-5
5-5
5-5
5-6
5-6
5-6

5.2.1

5.3.1
5.3.2
5.3.3

5.3.4
5.3.5

.
.
.
e
.
e
.
.

. . . . .. .. ... .. .. ...
. . . . . . .. .. ... ... ...
. . . . . . . ... ...
e e e e e e e e e e e e e e e e
. . . . . . ...
.. ... ...
e e e e e e e e e e e e e e e e e e
. . . . . ..
oo,
...
e e e e e
e e
e

5.3.6

ROM

. . .

5.3.7

RAM

. . . .

e e e e

5.3.8

Switch Register

5.3.9

Switch Register Address Decode Logic

5.3.10

Bus Address Register

5.3.11

Data Bus Control Logic

5.3.12

UnibusControl

5.3.13

Keypad ScanLogic

5.3.14

Indicator Logic

5.3.15

Halt Logic

5.3.16

Buffers

5-1

e e e e e e e e e e e e

5-7

e e e e

e e e

5-7

. . . . . . . . . . . . . . e

5-7

e e

. . . . . . . . ..e

e e e e e .

5-7

000

5-8

e e e e e e e e e

5-8

. . . . . . . . . . . . . .. ..
. . .. ... .. ... e

. . . . . . . . . . . .

0 o i

. . . . . . . . . . . . . . . .

. . . . . . . . . . . . ..

. . . . . . . . .

5.3.16.1

Tristate Buffers (8093)

5.3.16.2

Tristate Transceivers (8833)

CHAPTER 6

CONSOLE MODE OPERATION

6.1

INTRODUCTION

. . . . .

CONSOLE KEY OPERATIONS

. . . . . . . . . . .

EXAMPLES OF CONSOLE SEQUENCES

CHAPTER 7

MAINTENANCE MODE OPERATION

7.1

INTRODUCTION

. . . . .

NOTES ON OPERATION

CHAPTER 8

KY11-LB MAINTENANCE

8.1

PRELIMINARY CONSIDERATIONS

8.2

M7859 FAILURES

6-5
6-6

7-1

. . . .. ... ... .....

7-1

e e e e e e e e e e e

7-2

e e e

e e e e

e e

6-1

. . . . ... ... . .......

. . . . . . . . . .

. . . .

it i i
e

6-1

e e

MAINTENANCE MODE KEY OPERATIONS
7.3

... 5-11

e e e e e e e e e e e e e e e e e e

6.4

. .

e 5-11

. . . . . . . . . . . . . ... . ... 5-11

NOTES ON OPERATION

. . . . .

e 5-11

e e e e 5-11

e e e e e e e e e e e e e e

6.3

. . .

e e

. . . . . . .. . .. . . ... ...

e 5-10

e e 5-10
e

e e e

. ... ........ e

.......

8-1

. . . . e
e

8-2

. . .. .. . . ... ...

e e

CONTENTS (Cont)

CHAPTER 9

KY11-LB INSTALLATION

9.1

KY11-LB DESCRIPTION

9.2

CPUBOXTYPE

. .

. ... .

.. . .

. ..

e
s

9.3

CPU DIFFERENCES

9.4

BA11-L 13.3 CM (5-1/4 INCH BOX) INSTALLATION

. .. ... ......

. .

. . .

.. ..

9.5

BA11-K 26.7 CM (10-1/2 INCH BOX) INSTALLATION

9.6

MAINTENANCEMODE HOOK-UP

APPENDIX A

KY11-LB MICRO-CODE LISTINGS

APPENDIX B

IC DESCRIPTIONS

...

. ...
.. .. ...
...

...

......

FIGURES

Title

Programmer’s Console/Interface — PDP-11/04/34 Configuration
Interface Module (M7859)

KY11-LB Logical Organization
KY1I-LBKeypad

. .

... .

. ..

... ...

...

Interface Module Detailed Block Diagram
Microprocessor Signal Interface

Timing Diagram — Microprocessor Instruction
Transition State Diagram

. .

RAM Address Allocations

Keypad Image
.

M7266

. . .

. .

e e

. .

. . . . . .

. .

. . . . . . . . .

Clock Waveforms
M7263

. . .. . . .

...

...
...

i e

e e

e e e e

e e

e e e

....
e
....
.

. e

e
e

. . . . @ .

e
e
e

TABLES

Table No.
2-1

3-1
3-2

5-1

Title

KY11-LB Controls and Indicators . . . . . . . . . . . ..
State Control Coding
. . . . . e
e e e e e e e e e e e
Cycle Coding
. . . . . . . i i i e
e
e
e e e e e
RAM Function Address Assignments
. . . . . .e
e e e

Page

... .. ...
e e e
e
e e e e e
e
e e e e e e

2-3
3-2
3-3
5-2

KY11-LB PROGRAMMER’S CONSOLE/INTERFACE MODULE OPERATION

PREFACE

The KY11-LB Programmer’s Console/Interface Module Operation and Maintenance Manual provides
the information required to operate this option in console or maintenance mode. The manual also
presents a detailed theory of operation of the interface module hardware and software components,
data on the utilization of the programmer’s console as a maintenance tool for the PDP-11/04/34
processors, and information on the troubleshooting and maintenance of the interface module itself.
The information is presented in nine chapters:
Chapter 1

Provides an inroduction, general description, and overview of electrical and
mechanical specifications.

Chapter 2

Presents a functional description of the console, operating modes, controls
and indicators, and a general discussion of interface module hardware organization and software facilities.

Chapter 3

Describes, on a detailed block diagram level, interface module functions,
registers and controls, and the functions of the MOS/LSI microprocessor.

Chapter 4

Describes the microprocessor instruction set.

Chapter 5

Presents a description of the M7859 Interface module to the logic level.

Chapter 6

Provides operating information on console utilization in console mode.

Chapter 7

Contains procedures for using the console in maintenance mode (maintenance of PDP-11/04/34 processor).

Chapter 8

Covers some maintenance techniques for the KY11-LB interface module.

Chapter 9

Describes installation procedures for various options.
NOTES
In the material presented in this manual, the term
‘“processor”’ refers to the KD11-D, KDI11-E, and
KD11-EA PDP-11/04/34 processors.
If the operator is not familiar with console functions,
Chapter 6 should be consulted.

CHAPTER 1

OPERATING CHARACTERISTICS

1.1
INTRODUCTION
The PDP-11/04/34 Programmer’s Console and Interface module (KY11-LB) provides all the functions now offered with the PDP-11/05. The Programmer’s console interfaces to the Unibus (Figure 11) through a quad SPC module. To use this option, the normally provided KY11-LA Programmer’s
Console must be removed and the KY11-LB Console installed in its place. The KY11-LB Console
contains a 7-segment LED display and a 20-key keypad for generating the console commands. Several
indicators are also provided for additional convenience in monitoring system status.

PROGRAMMER'S

CONSOLE/

—

KD11-D

ADDITIONAL

MEMORY

MQDULE

KY11-LB

[

PROCESSOR

11-4855

Figure 1-1

Programmer’s Console/Interface - PDP-11/04/34 Configuration

The KY11-LB Programmer’s Console/Interface module comprises an INTEL 8008 single-chip, large
scale integration (LSI) microprocessor and associated registers, Unibus control logic, and auxiliary
memory. The unit is also provided with a 20-key keypad for operator/programmer interaction with
the KD11-D, -E, -EA via the interface module, six indicator LEDs, a 6-digit, 7-segment display for
address or data, and a dc power switch. The microprocessor communicates with a read-only memory
(ROM) which contains a number of fixed routines for use during normal console and maintenance
operation.

1.2

GENERAL DESCRIPTION

The M 7859 Interface module (Figure 1-2) functions as the interface between the programmer’s console
and the KD11-D, KD11-E, or KD11-EA processor, via the Unibus. The unit consists of solid state
integrated circuits with TTL~compatible input and output lines. The heart of the interface module is a
single-chip, large scale integration (LSI) microprocessor which executes designated keyboard functions
via programs stored in ROM memory. Auxiliary logic functions including clock, decoding and timing
circuitry, and addressing and Unibus drivers/receivers comprise the remaining logic of the board.

1-1

8141-14

Figure 1-2

Interface Module (M7859)

The microprocessor chip is an 8-bit, parallel control element packaged as a single metal oxide silicon
circuit in an 18-pin, dual in-line package. With the addition of external clock driving circuitry and
decoding elements, plus memory and data bus control, the unit is capable of performing as a powerful,
general-purpose, central processing unit. Internal logic of the microprocessor chip is structured around
an 8-bit internal data bus and includes instruction decoding, memory control, accumulator and
scratchpad memory, arithmetic and logical capability, program stack, and condition code indicators.
Data transfer between the microprocessor chip and the remaining logic functions of the interface
module is accomplished through an 8-bit, bidirectional data port which is an integral part of the
microprocessor. An internal stack (scratchpad memory) contains a 14-bit program counter (PC) and
an additional complement of seven 14-bit registers for nesting up to seven levels of subroutines. The
14-bit addressing capacity allows the microprocessor to access up to 16K memory locations which may
comprise any mix of ROM or RAM.
1.3
FUNCTIONAL DESCRIPTION
The KY11-LB Programmer’s Console permits the implementation of a variety of functions through a
20-key keypad located on the front panel of the programmer’s console. Keypad functions are divided
into two distinct modes: console mode and maintenance mode. In console mode operation, a number
of facilities exist for displaying addresses and data, for depositing data in and examining the content of
Unibus addresses including processor registers for entering data into a temporary buffer for use as
address or data, and for single instruction stepping the processor. The latter feature is especially useful
during program debugging functions.
Normal console keyboard functions are not available during maintenance mode. This mode permits
sampling and display of the Unibus address lines and Unibus data lines, and may allow the console to

take control of the Unibus to examine and deposit Unibus addresses if a processor is not present in the
system or is malfunctioning. Additionally, the maintenance function permits assertion of the manual
clock enable and display of the current processor microprogram counter (MPC). Single-clock cycling
of the MPC is also possible to facilitate step by step checkout of processor op codes and control logic
during maintenance functions. In conjunction with this function, assertion of manual clock enable
permits the processor to be stepped through its power-up routine. The manual clock enable may be
dropped via the START key at any time with a resulting dislay of the current MPC. Exit from maintenance mode to console mode may be accomplished at any time by depressing the CLR key on the
keypad.
1.4

1.4.1

SPECIFICATIONS

M?7859 Interface Module Performance Specifications

Operating Speed at 500 kHz
Two-Phase Clock Period
Time State (SYNC)
Instruction Time (Microprocessor)
Word Size

2 us
4 us
12-44 us

Data

8-bit word

Instruction

1, 2, or 3 8-bit words

Address

14 bits

Memory Size
ROM
RAM

4 512 X 4 organized as 1024 8-bit words
16 words by 8 bits

1-3

Input/Output Lines

Memory Data
Address
Control (Address)
Unibus Control

16 bits
18 bits
2 bits
5 bits

Microprocessor Instruction Repertoire

48 Basic Instructions
Instruction Categories

1.4.2

Electrical Specifications

Power Supply

+5Vat30A
-15 V at 60 mA

Input Logic Levels (all modules)
|
TTL Logic Low
TTL Logic High
Output Logic Levels (all modules)
TTL Legic Low

TTL Logic High

0.0 to 0.8 Vdc
2.0 to 3.6 Vdc

0.0to 0.4 Vdc
2.4 to 3.6 Vdc

Power Consumption
Interface Module
Monitor/Control Panel

1.4.3

W
14
1'W

Mechanical Specifications

M7859 Interface Module

Board Type

Dimensions

Height
Length

Quad SPC

21.44 cm (8.44 in)
26.08 cm (10.44 in)

Programmer’s Console (Overall Panel Dimensions)
Width
Height
Depth

1.4.4

47.63 cm (18.75 in)
13.02 cm (5.125 in)
6.76 cm (2.66 in)

Environmental Specifications

Ambient Operating Temperature
Humidity

5° to 50° C (41° to 122° F)
10% to 95% maximum,
wet bulb 32° C (90° F)

1-4

HLT GRANT

SSYN

ADDRESS/DATA BU

MICROPROCESSOR

8008

TRANS-

DATA BUS

CEIVER

3-STATE

3STATE

3-STATE

3STATE

ROM

BUFFER

512X 8

DATA IN (3-STATE)

RAM
16X 8

CLOCK

DATA OUT

TIMING

TIME STATES

DECODER

ADDRESS

14.8

7-0

DATA BUS
CONTROL

RAM CNTRL

4 L

ROM ENABLE

INPUT/OUTPUT
PORTS

l CONSOLE

DISPLAY I
'

ADDRESS/DATA BUS

BUS CONTROL

BUS ADDRESS

S.R.

REG

REG 3

REG 2

REG 1

CONTROL

INIT

KEYPAD

HLT RQST

MSYN

]

i)i

TRANSCEIVER

777570

BUS ADDRESS <17:0>,
C1, CO
UNIBUS

11-4852

Figure 2-1

KY11-LB Logical Organization

2-2

SWITCH REGISTER

TRANSCEIVER

BUS DATA <15:0>

HLT/SS

DEP

EXAM

DIS AD

LAD

CONT

BOOT

LSR

CLR

INIT

CNTRL

START

J
11-4846

Figure 2-2

Table 2-1

Control/Indicator

KY11-LB Keypad

KY11-LB Controls and Indicators

Function
Keyboard - Console Mode

LAD

Load Address — Moves the 18-bit number in the temporary register into the Unibus address pointer. The temporary register is
then cleared and displayed.

LSR

Load Switch Register — Moves the 16 lower bits of the temporary register to a register which can be read via Unibus address
777570. The switch register contents will be displayed.

DEP

Deposit — Causes the console to do a DATO on the bus address
pointed to, using the data in the temporary register (two MSBs
are truncated). Sequential deposits cause the address pointer to
be incremented. This key is operative only if the processor is
halted.

Numerics — These keys are used to enter data into a temporary
data buffer prior to use as either address or data. Use of a
numeric key forces the console to display the data held in the
temporary buffer. A 6-digit number is generated as octal digits
are entered from the right and left shifted.
CNTRL

Control - This key is used only in conjunction with other keys
either to prevent accidental operation of certain functions or to
provide entry into maintenance mode or other features. When
used, the CNTRL key must be pressed first and held down
while the second key is pressed. Those keys which are interlocked with the CNTRL key are indicated by “CNTRL-second
key” (e.g., CNTRL-START).

2-3

Table 2-1

KY11-LB Controls and Indicators (Cont)

Control /Indicator

Function

CNTRL-INIT

Initialize — Operative only if the processor is halted. Causes
BUS INIT L to be generated for 150 ms.

DIS AD

Display Address — This key causes the current Unibus address
pointer to be displayed. The next examine or deposit will occur
at the address displayed.

EXAM

Examine - Causes the console to do a DATI on the bus address
pointed to and stores the data in the temporary register which is
then displayed. Sequential examines cause the address pointer
to be incremented by 2 or by 1 if the address is in the range
777700-777717. This key is operative only if the processor is
halted.

CLR
CNTRL-BOOT

Clear Entry - Clears the current contents of the temporary register which is then displayed.
Causes M9301 bootstrap terminator to be activated if present in

the system. Console will boot only if the processor is halted.
CNRL-HALT/SS

CNTRL-CONT

Halt/Single Step - Halts the processor if the processor is running. If the processor is already halted it will single-instruction
step the processor. It also retrieves and displays the contents of
R7 (program counter). The CNTRL key is not required to
Single-Instruction Step the machine.
.

Continue - Allows processor to continue using its current program counter from a halted state. The contents of the switch
register are displayed.
|

CNTRL-START

Operative only if halted, this causes the program counter (R7)
to be loaded with the contents of the Unibus address pointer.
BUS INIT L is then generated and the processor is allowed to
run. Switch register contents are then displayed.

CNTRL-7

Causes the Unibus address pointer to be added to the temporary data buffer which is also incremented by 2. This allows the
console to calculate the correct offset address when mode 6 or 7,
register 7 PIC (Position Independent Code) instructions are
encountered.

CNTRL-6

This causes the switch register to be added to the temporary
data buffer. This is useful when mode 6 or 7 instructions are
encountered not using R7.

CNTRL-1

Maintenance Mode - This combination puts the console into
maintenance mode with certain maintenance features available.
When the console is in maintenance mode, the normal console
mode keypad functions are not available. The CLR key causes
the console to exit from maintenance mode into console mode
via a processor halt.
2-4

Table 2-1
Control /Indicator

KY11-LB Controls and Indicators (Cont)
Function
Keyboard - Maintenance Mode

NOTE|

In maintenance mode the keypad functions are redefined with the following definitions.
DIS AD

Causes the Unibus address lines to be sampled and displayed.

CLR

Returns the console to console mode via a console halt.

EXAM

Causes the console to sample the Unibus data lines and display
the data.

Causes the console to take control of the Unibus. Should be
used only when a processor is not present in the system.
HLT/SS

Asserts manual clock enable and displays the current microprogram counter (MPC).

CONT

Asserts manual clock enable, generates a manual clock pulse,
and displays the current MPC.

BOOT

Boots the M9301. If manual clock enable is asserted, this will
allow the processor to be stepped through the power-up routine.

START

Drops manual clock enable and displays the current MPC.
Indicator LEDs - Any Mode

DC ON

All dc power (+5 V) to logic is on.

BATT

Battery monitor indicator, operative only in machines having
the battery back-up option. This indicator has four states:

Off - Indicates either no battery present or battery failure if a battery is present.
On (continuous) - Indicates that a battery is present and
charged.
Flashing (slow) - Indicates ac power is ok and battery is
charging.

Flashing (fast) - Indicates loss of ac power and that battery is discharging while maintaining MOS memory
contents.

RUN

Indicates the state of the processor, either running or halted.

2-5

Table 2-1

KY11-LB Controls and Indicators (Cont)

Control /Indicator

Function

SR DISP

Indicates that
displayed.

MAINT

Indicates that console is in maintenance mode.

BUS ERR

Indicates that an examine or deposit resulted in a SSYN timeout or that HALT REQUEST failed to receive a HALT

the content of the switch

being

GRANT.
DC Power Switch

DC OFF

All dc power to logic is off.

DC ON

All dc power to logic is on.

STNBY

DC power is provided to MOS memory only.*
*Available in all BA11-C machines. Available in BA11-K boxes which have
Battery Backup Option only.

Table 2-1 refers to certain registers which are located in the scratchpad RAM. These include the

Subwn—

followmg
Display Data
Keypad Image
Temporary Data Buffer
Unibus Address Pointer

Switch Register Image
EXAM, DEP, ENB and CI1 flags

Detailed discussion of the scratchpad RAM and its registers is set forth in Chapter 5.
2.2.2

Maintenance Mode
Mantenance mode is entered by pressing the CNTRL key and the 1 key simultaneously. Note that the
functions performed by the appropriate keys are quite different from console mode. This mode offers
the ability to assert the manual clock enable and thus to single-clock cycle the processor while monitoring the contents of the processor microprogram counter.
2.3

HARDWARE ORGANIZATION

A detailed block diagram of the interface module showing data flow and controlis indicatedin Figure
2- } The control functions shown include those for the Unibus interface and the internal data bus with

the microprocessor. The latter controls include those for reading from and writing into the RAM,

enablmg ROMs 1 and 2, and reading the Unibus temporary buffer register or loading the bus address
and switch registers. All of these functions occur on appropriate control from the stored program and

keypad.

2-6

DIN 0-7H

20
MASTER

CLOCK

o1
02

8 BIT BUS

TRANS-

CEIVERS

16 BIT
ADRD 0-7H

ADDR

ADRD 08
1024 x 8

ROM 1 EN

SO S1 S2

——» BUS SSYN L (TO HALT)

LOGIC

<15:0>

BUS DATA

o
9
ENDB~BL

ROM

ADDR
DECODE

REG

INT

POWER-

S.R.

{DECODE 777570)
.

ROM 2 EN

=
o«

SWITCH

REG

SYNC H

(16 BITS)

LOGIC

ADDR

b WAITL

[ax]

REG

—— TS2L

ADRD DO 0-7

LOAD

—— TS1L

GATING

DECODER }—— T1IL

BYTES

|—— TS3L

| e CLRBUS L

182

TS5L

E:HALT RQSTL

UNIBUS | 1. e BUSINT L

— TS4L

ADRD 05

CNTL

LOGIC

777570

<17:0>

|1+ EN DB—BUS L

L BUSMSYN L

BUS ADDRESS

L1
& TAKE BUS L

2
Q

[%7]

SINGLR

ADRD 6, 7

cvcLe

CNTL

[ MANCLKENL

——» MAN CLK L

)

BUS

ADRD 0-7

ApnppR
REG

‘_'1

18 BITS

| 8 o READ INPUT 07 L

EN AR—BUS L

——* DIN DRIVERS D15 H

c FS,?, %DP%1F3LIN 1
:

DATA

BUS

CNTL

+2 CONTROL

‘

BITS

RAM WRITE

:;:: DIN BUS L (RAM)
F84+ LOAD REG 0-5H
;

AND IND CNTL

[~ ROM 1 EN L
preyit» ROM 2 EN L

—e»BUSER L

IND

ADRD 4.7

[

e srRDISP L

CNTL | 1 e maINTMOL

L
ADRD 0-3H

DISPLAY

> BOOTL

16X 8
RAM

DOUT 0-7H
f

SCAN SIGS

RAM-DIN BUS L
KEYPAD

SCAN

RAM WRITE H

SWITCHES (20)

LOGIC

CONN 0 — CONN 11 H

(MPC INPUTS]
FOR DISPLAY

KEYPAD

MAINT

CONN

HALT GRANT H

|
» BUSBUSY L

CLR BUS L

PU PL

BUS BUSY L

HALT

* BB SSYNH

CNTL

BUS SSYN L

- BUS SACK L

BUS INIT L
TAKE BUS L

— RUN L

11-484%

Figure 2-3

Interface Module

Detailed Block Diagram

2-7

Decoder for Timing States

The decoder element receives the state outputs SO, S1, and S2 from the microprocessor and generates
the time states for the operation of the interface module. A sync pulse corresponding to two phase
clock periods (1 time state) is also provided by the microprocessor.
Power-up Logic

This circuitry activates the microprocessor, clearing its various registers and generating a clear line to
all the registers of the interface module. There are separate clears for the address register and all other
registers.

Address Register

This 16-bit register is the principal buffer between the microprocessor and the remainder of the logic of
the interface module. Although designated as an address register, the element also handles control data
for the Unibus, data bus, and other control functions and outputs to the bus address and switch
registers. One of its major functions is to receive the microprocessor program counter contents for
fetching new instructions from the ROM or RAM.
RAM

The 16-word by 8-bit RAM gives the interface module a scratchpad memory which may be read or
whose contents may be modified under program control.
ROM

The ROM, consisting of four 512 X 4-bit ROMs, makes a total of 1024 8-bit bytes available for the
stored programs which execute the console functions.
Switch Register Address Decoding

This logic decodes 777570, an 18-bit address defining the switch register and a DATI on the Unibus to
cause the switch register to be enabled onto the Unibus.
Switch Register

This 16-bit buffer register handles the data word to the Unibus.
Bus Address Register

This 20-bit register buffers address information between the interface module and the Unibus. Eighteen bits are allocated for the actual address, and two control bits indicate the direction of data flow.
Scan signals for the keypad and NUM lines for the display logic are specified by this register.
Tristate Gates

These units are used to gate buffered Unibus data (16 bits) and Unibus address (18 bits) lines onto the
tristate data bus by asserting an appropriate read input line. Keypad outputs and those maintenance
lines provided for display of the processor microprogram counter are similarly buffered and gated. The
outputs are all wire ORed onto the internal data bus and applied as input to the tristate transceivers.
Keypad Scan and Display Logic

This circuitry develops read and drive signals for the keypad and LED display respectively. Five read
signals developed from the scan signals are used to scan the keypad switch closures in groups of four.
The drive signals are applied to the LED displays whose values are determined by the 3-bit NUM
~input.

Data Bus Control

This circuitry performs all internal interface module control functions including RAM control, ROM
enable, and selection of input/output ports. The logic also determines system operation during instruction, data fetch, or data out (TS3) via a 32- X 8-bit ROM.

Unibus Control
The Unibus control register supervises data transfers between the interface module and the Unibus.
According to the input bit patterns to the register, data transfer from the interface module to the
Unibus, halt request, bus master sync, and other functions may be generated as required for proper
interfacing of the two elements. Two other signals generated in the Unibus control register permit
single stepping of the processor clock.
Indicator Logic
This 4-bit register drives appropriate console indicators to show certain console states or errors. An
indicator is turned on to show the existence of a bus error, when the switch register is being displayed
or when in maintenance mode.
Halt Logic

This circuitry halts the processor under various conditions and performs handshaking functions when
the console takes complete control of the bus. When a HALT from the console is detected by the
processor, the processor recognizes it as an interrupt request. The processor then inhibits its clock and
returns a recognition signal to the console causing the console to assert an acknowledge. The console
now has complete control of the Unibus and processor and may maintain this condition, with the
processor halted, as long as desired.

2.4

MICROPROCESSOR INSTRUCTION SET
The interface module microprocessor has a repertoire of 48 basic instructions. According to the

instruction type, these may range from 1 to 3 bytes (8 to 24 bits) in length. The successive bytes of a
given instruction must be located in sequential memory locations. Instructions fall into one of five
categories:

Index Register
Accumulator (Arithmetic/Logical)
Program Counter and Stack Control
Input/Output
Machine
A description of the microprocessor instructions and the number of time states required for their
execution is given in Chapter 4.

2-10

CHAPTER 3
INTERFACE MODULE

3.1

MICROPROCESSOR

3.1.1
General Organization
The microprocessor sends and receives data over an 8-bit data and address bus (Do to D) and utilizes
four input and four output lines (Figure 3-1). The microprocessor contains six 8-bit data registers, an

8-bit accumulator, two 8-bit temporary registers, four flag bits, and an 8-bit parallel binary arithmetic
unit. The arithmetic element is capable of performing addition, subtraction, and logical operations.
Additionally, a memory stack containing a 14-bit program counter and seven 14-bit words is used to
store program and subroutine addresses. The microprocessor machine cycle usually requires five
sequential states: TS1, TS2, TS3, TS4, and TSS. During time states TS1 and TS2, the external memory
is addressed by a lower and an upper address byte respectively to form a 14-bit address. Also at TS1
time, the program counter (PC) is incremented for the next instruction fetch cycle. During time state
TS3, the instruction addressed during states TS1 and TS2 is fetched and during the final two cycles,
TS4 and TS5, it is executed. Figure 3-2 shows the possible number and sequence of the instruction
states. Note that for this application of the microprocessor, the interrupt function is utilized only
during the power-on sequence.
FROM:

ROM
RAM

DATA (Unibus)

ADDRESS (Unibus)

—

KEYPAD

MAINT

NOT USED
{(+5 V)

FROM
MASTER CLOCK

D1
D7

INTERRUPT

READY

il >

PROCESS

CESSOR

D3
D4
D5

MICRO-

\ % P yYYVYY

DO
FROM POWER-ON
LOGIC

SSTATE

—>

TRANS-

Ea—

CEIVERS

SX:iOING
> TO

——— |

L
-

ADDRESS REG

AND RAM

> TIMING PHASE
DECODER

11-4856

Figure 3-1

Microprocessor Signal Interface
3-1

/N /]

2 L
SYNC

NSNS

—
AN

TS1

CPU

LOWER

INTERRUPTED

8-BITS

ADDRESS

ouT

TS2

WAIT

HIGHER

753

EXTERNAL

8-BITS

MEMORY

TWO BITS

(OPTIONAL)

ADDRESS

NOT READY

CONTROL

STOPPED

INSTRUCTION | HALT

OR DATA

INSTRUCTION

DATA OUT

CPU

FETCH, OR

RECEIVED

TS4

TS5

EXECUTION

INSTRUCTION

(8-BITS)

ouT
11-48€9

Figure 3-2

3.1.2

Timing Diagram - Microprocessor Instruction

State Control

The microprocessor operates as a sequential state machine, controls the use of the data bus, and,

according to its stored program, determines whether it sends or receives data. Output state signals SO,

S1,and S2 are decoded externally and distributed to the peripheral control logic. Table 3-1 shows the
coding of the state bits to yield a given phase.
3.1.3 Microprocessor Timing
The microprocessor machine cycle is shown in Figure 3-2. Since machine operation is asynchronous,

the exact timing sequences depend on the instruction executed. A typical cycle may consist of five
states. During T1 and T2, an address is sent to memory; at T3 time, instruction or data fetch occurs; T4
and TS provide execution time.
A number of microprocessor instructions may require up to three cycles and do not require the two
execution states T4 and T5. As a result, cycle length is variable and the state counter determines
whether T4 and TS5 are to be executed or omitted. This is accomplished via the cycle control coding

(Table 3-2) in bits D6 and D7. Cycle 1 is always an instruction fetch cycle (PCI). The second and third
cycles are for data reading (PCR), data writing (PCW), or 1/0 operations (PCC). The cycle type bits
D6 and D7 are present on the data bus during
T2 time only.

s
O rt

State

Tl
T11

O OO

—

OO OO

State Control Coding

—_—m

Table 3-1

3-2

T2
WAIT

STOPPED
T4
TS

Table 3-2

3.1.4

Cycle Coding

Cycle

Function

PCI

PCR

Designates the address is for a memory read data (additional

PCC

Designates the data is a command I/O operation.

PCW

Designates the address is for a memory write data.

Designates the address is for a memory read (first byte of

instruction).

bytes of instruction or data).

Transition State Diagram

Possible state transitions within the processor are shown in Figure 3-3. Note that a normal machine
cycle would begin at cycle 1, run from T1-T5, and revert back to cycle 1 again. The state counter
within the microprocessor operates as a 5-bit feedback shift register with the feedback path controlled
by the current instruction. The number of states normally required by each instruction is discussed in
Chapter 4.

{CYCLE 1) (HLT - INT + RETURN{CF)) + {CYCLE 2) (OUT + LMr)

+ (CYCLE 3} {LM! + JUMP (CF)) + CALL (CF)

:
—

CYCLE 1

CYCLE 2

—

{CYCLE 1) (HLT = INT) + RDY

CYCLE 3

T (CYCLE 2) (LMI + JUMP + CALL)}
(CYCLE 1) (LrM) + ALUM + ALUI + IN + OUT + Lrl + JUMP + CALL

(CYCLE 1) LMr

NORMAL RETURN AT END OF MEM CYCLE

NOTE: CF = Failure Condition
11-4857

Figure 3-3

Transition State Diagram

3-3

3.1.5 System Start-Up
The microprocessor of the interface module is running any time power is applied to the system. When
power (VDD) and clocks (01, 02) are first turned on, a flip-flop internal to the microprocessor is set by
sensing the rise of VDD. This internal signal forces a HALT (00000000) into the instruction register
and the microprocessor is then in the stopped state. The next 16 clock periods are required to clear
internal chip memories and other external logic and registers. Upon clearing the registers the system is
ready for operation. If for any reason during operation, the microprocessor decodes a HALT, the
system reverts to the beginning of the program after 16 clock periods.
3.2

INTERFACE MODULE REGISTERS AND CONTROLS (Figure 2-1)

3.2.1
Address Register
This is the principal buffer register between the microprocessor and the rest of the interface module

logic. It has a capacity of 16 bits (two 8-bit bytes). The low order byte is loaded by time state TS1 and
the high order byte by time state TS2 during each cycle.
3.2.2 Bus Address Register
The bus address register buffers address data between the interface module and the Unibus. Address
information may be loaded into this register at time state TS3.

3.2.3

Switch Register

Similar to the bus address register, the switch register buffers outgoing data. This element may also be
loaded at TS3.
3.2.4 Data Bus Control
The principal function of the data bus control is to determine interface module operation during TS3
time. It determines, through input bit coding, the type of function to be performed (i.e., RAM control,

ROM enable) or programs any of its other I1/O in accordance with the stored program.
3.2.5 Unibus Control
This register is also loaded at TS3 and is selected by the data bus control for activation at that time.
According to its input coding, U.C.R. may issue a HALT request, BUS INIT, enable-data bus-to-bus,
or generate a bus master sync in addition to other functions.

3-4

CHAPTER 4
MICROPROCESSOR INSTRUCTION DESCRIPTION

4.1
DATA AND INSTRUCTION FORMATS
Data in the CPU is stored in the form of 8-bit binary integers. All data transfers to the system data bus
will be in the same format.

| D7 Ds Ds Dy D; D, Dy Dy |
DATA WORD

The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be
stored in successive words in program memory. The instruction formats then depend on the particular
operation executed.
One Byte Instructions

|D; Ds Ds D, D; D, D, D, |

OP CODE

Two Byte Instructions

(D7 D¢ Ds D4 D3 D, Dy Dy |

OP CODE

D7 Ds Ds D4 D3 D, Dy Dy |

OPERAND

Immediate mode instructions.

Three Byte Instructions

[D, D, D; D, D, D, D, Dy|

OP CODE

[D, D; D; D, D, D, D; Dy |

LOW ADDRESS

[X X D,D,D,D,D, Dy]

HIGH ADDRESS*

*For the third byte of this instruction, D¢ and D- are “‘don’t care” bits.

4-1

JUMP or CALL instructions

4.2

MICROPROCESSOR INSTRUCTIONS

4.2.1

Index Register Instructions

The load instructions do not affect the flag flip-flops. The increment and decrement instructions affect
all flip-flops except the carry.

Minimum

States

Mnemonic

Instruction Code

D,Dy

D;D,D; D,D;D,

DDD

Description of Operation

Required

(1) Lryr,

(5)

Load index register r; with the content
of index register r,.

(2) LtM

(8)

DDD

Load index register r with the content
of memory register M.

LMr

(7)

111

Load memory register M with the content of index register r.

(3) L1l

(8)

LMI

DDD

110

BBB

111

110

(5)

DDD

INr

B B

DCr

Load index register r with data B . . . B.
Load memory register M with data

B...B.

Increment the content of index register
r(r+ A).
Decrement the content of index register
r(r+# A).

4.2.2

Accumulator Group Instructions

The result of the ALU instructions affect all of the flag flip-flops. The rotate instructions affect only
the carry flip-flop.

Minimum

Mnemonic

States

Instruction Code

D,D¢

DsD4D3 D,D{ D,

Description of Operation

Required

ADr
ADM

(5)
(8)

1
0O
10

000
000

S S S
111

Add the content of index register r,
memory register M, or data B.. . B to

ADI

(8)

000

100

sets the carry flip-flop.

ACr
ACM

(5)
(8)

1
1

001
0 0 1

S
1

Add the content of index register r,
memory register M,ordataB...Bto

ACl

(8)

g (];

0
0

S
1

% % 113 ]13 ?3 g

4-2

the accumulator. An overflow (carry)

the accumulator with carry. An over-

flow (carry) sets the carry flip-flop.

Mnemonic

Minimum

Instruction Code

States

b,D, D,D,D, D,D. D,

Description of Operation

Required

SUr

(5)

SUM

(8)

SUI

(8)

Subtract the content of index register

111

r, memory register M, ordataB...B

(1; (];

(]; B g B (1; g

from the accumulator. An underflow

(borrow) sets the carry flip-flop.

010

SBr

(5)

011

Subtract the content of index register

SBM

(8)

011

111

r, memory register M, ordataB...B
from the accumulator with borrow.

SBI

(8)

011

BBB

100

An underflow (borrow) sets the carry

NDr

(5)

Compute the logical AND of the con-

NDM

(8)

100

(8)

OB (];

B B g

accumulator.

XRr

(5)

101

Compute the Exclusive OR of the con-

XRM

(8)

101

111

tent of index register r, memory M, or

XRI

)

101

100

data B. .. B with the accumulator.

BBB

BB
S

NDI

BB
0

tent of index register r, memory

ORr

(5)

110

ORM

(8)

110

111

tent of index register r, memory

(8)

g (];

B B g

B (]; ](3)

flip-flop.

Compute the Inclusive OR of the con-

accumulator.

CPr

(5)

111

Compare the content of index register

CPM

(8)

111

r, memory register M,ordataB...B

CPI

(8)

g g

]13 ]13 113

]13 (}; ](3)

the accumulator is unchanged.

RLC

(5)

OO0

00O

OT10O0

with the accumulator. The content of

Rotate the content of the accumulator
left.

RRC

(5)

0OO0O1

010

Rotate the content of the accumulator
right.

RAL

(5)

OO0

010

Rotate the content of the accumulator
left through the carry.

RAR

(5)

0 0

O' 11

010

Rotate the content of the accumulator
right through the carry.

4-3

4.2.3

Program Counter and Stack Control Instructions

Minimum

Mnemonic

States

Instruction Code
D,D¢ D;D;D; D,D;D,

Description of Operation

Required

(4) IMP

(5) JFc

(1D

Qorll)

XXX

100

Unconditionally jump to memory ad-

B,B,

B,B,B,

dress By .. .B3B, .. .B,.

X X

B3;B;B;

B;B;B;g

0C,C;

00O

Jump to memory address

B,B,

B,B,B,

B;...B3B, ...B, if the condition

X X

B;B;B;

By;B,;B,

flip-flop c is false. Otherwise,

execute the next instruction in
sequence.

(5) JTc

Qorll)

1CC

000

Jump to memory address

B,B,

B,B,B,

B; ...B3B, ...B, if the condition

X X

B3B;B;

B;B;B,

flip-flop c is true. Otherwise, execute

the next instruction in sequence.

(4) CAL

(1D

XXX

110

Unconditionally call the subroutine at

B,B,

B,B,B,

memory address By .. .B3;B, .. .B,.

X X

By;B;B;

BB, B,

Save the current address (up one level

in the stack).

(5) CFc

Qorll)

0GCC;

010

Call the subroutine at memory address

B,B,

B,B,B,

B; ...B3B, ...B, if the condition

X X

B3ByB;

ByB,B,

flip-flop ¢ is false, and save the current

address (up one level in the stack).

Otherwise, execute the next instruction in sequence.

(5) CTc

Qorll)

1CC

010

Call the subroutine at memory address

B,B,

B,B,B,

B; ...B3B, ...B, if the condition

X X

B;B;B;

B;B,B,

flip-flop c is true, and save the current

address (up one level in the stack).
Otherwise, execute the next instruction in sequence.

(4) RET

(5)

XXX

111

Unconditionally return (down one level
in the stack).

(5) RFc

(3 or 5)

0C,C3

Return (down one level in the stack) if
the condition flip-flop c is false. Otherwise, execute the next instruction in
sequence.

(5) RTc

(3 or5)

1CC;

Return (down one level in the stack) if
the condition flip-flop ¢ is true. Otherwise, execute the next instruction in
sequence.

RST

(5)

AAA

101

Call the subroutine at memory address
AAAO000 (up one level in the stack).

4-4

4.2.4

Input/Output Instructions

Minimum

Mnemonic

INP

Instruction Code

States
Required

D,Dy

(8)

DsD,D;

D,D;D,

Description of Operation

|
0O0OMMMI

Read the content of the selected input
port (MMM) into the accumulator.

ouT

(6)

RRM

MMI

Write the content of the accumulator
into the selected output port
(RRMMM) (RR # 00).

4.2.5

Machine Instruction

Minimum

Mnemonic

Instruction Code

States

D,D¢

D;D,D;

D,D,;D,

00O

O0O0X

Description of Operation

Required

(4) HLT

€3]

Enter the STOPPED state and remain
there until interrupted.

HLT

111

Enter the STOPPED state and remain
there until interrupted.

NOTES:

(1)

SSS =Source Index Register

These registers, r; , are designated A (accumulator—000).

DDD = Destination Index Register

B(001), C(010), D(011), E(100), H(101), L(110).

(2)

Memory registers are addressed by the contents of registers H & L.

(3)

Additional bytes of instruction are designated by BBBBBBBB.

(4)

X=“Don’t Care”.

(5)

Flag flip-flops are defined by C4Cj:

carry (00 overflow or underflow), zero (01-result is zero),

sign (10 MSB of result is “1”’), parity (11-parity is even).

4-5

CHAPTER 5

INTERFACE MODULE DETAILED LOGIC DESCRIPTION

5.1

INTRODUCTION

]

Keypad operation initiates appropriate microprocessor routines which perform certain data transfers
within the interface module, between the interface module and the Unibus, and between the interface
module and the programmer’s console display. Prior to discussing the interface module logic, the
sequences (i.e., register transfer, I/O operations, etc.) which occur after pressing a given key are briefly
described.

Figure 5-1 shows the 16-word by 8-bit scratchpad RAM and its address allocations. This data is also
summarized in Table 5-1. The keypad image within the RAM is shown in Figure 5-2.

RAM

]

[

ADDRESS

DISPLAY DATA

1
2

UNUSED
KEYPAD IMAGE

TEMPORARY

7 UNUSED

1799909777

13
14

UNIBUS ADDRESS POINTER

EXAM | DEP

W/””///yé
UNUSED

FLAG J FLAG V77vovzore

ENB

[

SWITCH REGISTER IMAGE

17
11-4853

Figure 5-1

RAM Address Allocations

5-1

KEYPAD IMAGE

CLR

LSR

LAD

DIS AD

INIT

EXAM

CNTRL

DEP

START

BOOT

CONT

HLT/SS

11-4854

Figure 5-2

Table 5-1

Keypad Image

RAM Function Address Assignments

Function

Address (Octal)

Display Data
(18 bits)

Address Bits

Word 0
Word 1

Bits 0-7
Bits 0-7

Word 2

Bits 0, 1

Word 3
Word 4
Word 5
Word 6
Word 7

Bits 0-3
Bits 0-3
Bits 0-3

Temporary Data Buffer
(18 bits)
}

Word 10
Word 11
Word 12

Bits 0-7
Bits 0-7
Bits 0, 1

Unibus Address Pointer
(18 bits)

Word 13
Word 14
Word 15

Bits 0-7
Bits 0-7
Bits 0, 1

EXAM FLAG
DEP FLAG
ENB FLAG
C1FLAG

Word 15
Word 15
Word 15
Word 15

Bit 7
Bit 6
Bit 3
Bit 2

Switch Register Image
(16 bits)

Word 16
Word 17

Bits 0-7
Bits 0-7

Keypad Image
(20 bits)

5-2

Bits 0-3
Bits 0-3

5.2

PROGRAMMER’S CONSOLE KEYPAD FUNCTION SEQUENCES

5.2.1

Console Mode Key Functions

NUMERICS

(0-7)

Value of Key

2.
3.

Temporary — Display

_(eft shifted)| Temporary Data Buffer

Clear indicators.

B
—

LAD

Temporary -+ Unibus Address Pointer

Zero - Temporary
Temporary — Display
Clear/Indicators.

Switch Register Image — Switch Register
SR DISP indicator is set.

Temporary —» Switch Register Image

LSR

CLR
Zero —» Temporary
Temporary - Display
Clear indicators.

EXAM

Pre-increment Unibus address pointer if the EXAM flag is set.
Unibus Address Pointer — Bus Address Register
Bus Address Register - Unibus Address
Assert MSYN.

NOTE
Console waits for BUS SSYN to be returned. If

Now

Unibus Data - Temporary
Temporary — Display
Set EXAM flag.

SN~

SSYN does not occur within 20 us, the transfer is
aborted and the BUS ERR indicator is set.

Pre-increment Unibus address pointer if the DEP flag is set.

DEP

Unibus Address Pointer - Bus Address Register with C1 = 1.
Bus Address Register - Unibus Address
Temporary — Switch Register
Switch Register
Assert MSYN.

- Unibus Data

NOTE
Console waits for BUS SSYN to be returned. If
SSYN does not occur within 20 us, the transfer is

aborted and the BUS ERR indicator is set.

Set DEP flag.
Switch Register Image — Switch Register
5-3

DIS AD
1.
2.

Unibus Address Pointer — Display
Clear EXAM or DEP flag if set.

CNTRL-INIT

Set BUS INIT and HALT REQUEST for 150 ms.

CNTRL-HLT/SS
1.
Clears BUS SACK./BUS BUSY if set and sets HALT REQUEST
2.

When HALT BUSY is active, sets 777707 - Bus Address Register

3.
4.

Assert MSYN

Bus Address Register - Unibus Address

- NOTE
Console waits for BUS SSYN to be returned. If
SSYN does not occur within 20 us, the transfer is
aborted and the BUS ERR indicator is set.
5.
6.

Unibus Data - Temporary
Temporary — Display

CNTRL-CONT

1.
2.
3.

:
Clears BUS SACK and BUS BUSY.
Switch Register Image — Display
Set SR DISP indicator.

CNTRL-BOOT
1.
Sets and clears BOOT signal
2.
Switch Register Image — Display
3.
Set SR DISP indicator.

N
—

CNTRL-START
777707 - Bus Address Register with C1 = 1
Bus Address Register - Unibus Address
Unibus Address Pointer - Switch Register
Switch Register - Unibus Data

Assert MSYN.
NOTE
Console waits for BUS SSYN to be returned. If
SSYN does not occur within 20 us, the transfer is
aborted and the BUS ERR indicator is set.

6.
7.
8.
9.

Switch Register Image —» Switch Register
Assert BUS INIT for 150 ms.
Switch Register Image —» Display
Set SR DISP indicator.

CNTRL-7
1.
Unibus Address Pointer + Temporary +2 — Temporary
CNTRL-6
.
1.
Temporary + Switch Register Image - Temporary

5-4

CNTRL-1
I.
Set maintenance indicator.

MPC Lines (sampled) — Display

5.2.2

Maintenance Mode Key Functions

CLR

1.
2.
3.

Clears indicators.
Clears manual clock enable, if set.
Goes to halt condition.

DIS AD
1.

Unibus Address (sampled) — Display

EXAM
1.

Unibus Data (sampled) - Display

HLT/ISS
1.
Sets manual clock enable.
2.
Clears BUS SACK and BUS BUSY.
3.
MPC (sampled) —» Display

5.3

1.
2.

Sets and clears manual clock
MPC (sampled) —» Display

Sets and clears BOOT signal.

1.
2.

Clears manual clock enable, if set.
MPC (sampled) —» Display

Sets TAKE BUS signal, forcing console to assert BUS BUSY.

DETAILED LOGIC DESCRIPTION

5.3.1
Clock Circuitry
The M7859 Interface board is driven by an MC 4024 (E42) 1-MHz clock (drawing CS M7859-0-1,
sheet 2). The I-MHz output at E42-8 is toggled down to two nonoverlapping 500-kHz pulses at E12-5,

6, and E30, and these pulses are applied to the microprocessor (E18) input as 01 and 02. The 02 clock,
designated as KY1 CK2 H and KY1 CK2 L, is also used as a control pulse to clear system registers
and together with the sync pulse to define the end of a timing cycle.
Figure 5-1 shows the relation between the two clock pulses.
5.3.2 Power-Up Logic/Interrupt (Drawing CS M7859, Sheet 2)
The power-up logic/interrupt circuitry is comprised of E1-6, E40-10, E1-4, E36, E12, E29-1, E6, and
E26. These elements sense when the system turns on, generate the interrupt to the microprocessor
needed to start it, and clear registers to force program startup at location 0.

5-5

BUS DC LO at E1-3 initiates the function by clearing E36 which is configured as an 8-bit counter and
generates KY1 PUP 1 L. This signal is routed to the Unibus control, indicator control, switch register,
and bus address register as a master clear line. The address register is provided with its own clear line,
KY1 ADR CLR L.

BUS DC LO L puts the microprocessor in the STOP state. The counter starts counting in the STOP
state (E6, E36). KY1 STOP L and KY1 C2 L at E29-1 clock E6. E6 is a divide by two on the clock,
while E36 counts from 0-7. Sixteen clock periods are thus counted. At the transition of E36 from 7 to
0, the interrupt is generated at E12-8 and the microprocessor goes into the T11 state (Interrupt). KY1
TI1I L and KY1 CK2 L then reset E12 and clear the address register via E6-6 and the system is
initialized.
5.3.3 Microprocessor (Drawing CS M7859, Sheet 2)
The 8008 Microprocessor Chip (E18) was discussed in detail in Chapter 3. According to drawing CS
M7859, sheet 2, the unit communicates over an 8-bit bidirectional data bus via 8833 tristate transceivers E16 and E17, with the satellite logic of the interface module. A single interrupt line is received
from the power-up logic to initiate microprocessor operations. Driven by a 2-phase, 500-kHz clock
(Figure 5-1), the element yields a 3-bit state output code, SO, S1, and S2, plus a sync pulse, to drive a
7442 Timing Phase Decoder. The latter element provides eight separate timing cycles for the sequencing of interface module data transfers and other discrete operations.
5.3.4 Timing State Decoder
The timing state decoder (E23) receives the state outputs SO, S1, and S2 from the microprocessor and
generates the timing states for the interface modules (drawing CS M7859, sheet 2). This unit is a 7442
4-line to 10-line decoder, with two unused outputs, that yields an 8-output sequence according to its 3input state code. State control coding is presented in Chapter 3. State control inputs are determined in
the microprocessor and depend on an internal 5-bit feedback shift register with the feedback path
controlled by the instruction being executed.
5.3.5 Address Register (Drawing CS M7859, Sheet 2)
The: address register, the principal buffer between the microprocessor and the remainder of the interface module logic, consists of four 74175 quad, D-type, double rail output latches. The low order bits

are handled by ES5 and E4 which generate KY1 ADRD 0 L through KY1 ADRD 3 L (E5) and their
complements (for RAM addressing), and KY1 ADRD 4 H through KY1 ADRD 7 H (E4), respectively. This 8-bit byte is the low order unit of the address or data with E10 and E28 containing the high
order information ADRD 08-13 and PC FUN 1 and 0.
The data contained in the address register is routed to the following locations according to direction by
the stored program:
1.

ROM (address of next instruction)(KY1 ADRDOL - KY1 ADRD 8 L plus ROM 1 ENL
or ROM 2 EN L)

RAM (address of data to be read or written) (KY1 ADRD 0L - KY1 ADRD 3 L)

Unibus Control (KY1 ADRD 0 H - KY1 ADRD 3 H)

Indicator Control (KY ADRD 4 H - KY! ADRD 7 H)

Data Bus Control (KY! ADRD 9 H- KY1 ADRD 13 H, KY1 PC FUN 0 H, KY1 PC
FUN 1 H)

Switch Register (KY1 ADRD 0 H - KY1 ADRD 7 H)

Bus Address Register (KY ADRD 0 H - KY1 ADRD 7 H)

-5-6

The address register is loaded with a low order byte (E4 and ES) by signal KY1 LD AD 1 H, generated
by AND E22-12 at time state TS1. The high order byte is gated in E28 and E10 by KY1 LD AD 2 H
generated at E22-6 at timing state TS2.
5.3.6

ROM

The interface module ROM consists of E3, E21, E33, and E39 (drawing CS M 7859, sheet 3). The four
512-word by 4-bit elements are addressed so that the ensemble looks like two 512- X 8-bit RMs. E3
and E21 are activated by KY4 ROM 1 EN L and E33 and E39 by KY4 ROM 2 EN L. Address bits
KY1 ADRD O H through KY1 ADRD 8 H are routed to all four ROM elements with the enable 1 or 2
determining the address activated and thus yielding 1024 8-bit locations. Outputs are wire ORed with
various inputs to give the KY2 DIN 0 H through KY2 DIN 7 H inputs to the tristate transceivers, E16
and E17.

The ROM 1 or RM 2 enables are generated by the data bus control logic.
5.3.7

RAM

The scratchpad RAM consists of E11 and E27 (drawing CS M7859, sheet 3). These units effectively
comprise a 16-word by 8-bit read/write memory, and serve as working storage for the microprocessor
programs in storing addresses and data. Data is routed to the RAM (KY1 DOUT 0 H through KY1
DOUT 7 H) directly from the tristate transceivers of the microprocessor bidirectional
data bus during
RAM write operations. The 4-bit address lines KY1 ADRD 0 L through KY1 ADRD 3 L specify the
address to be read from or written into during read/write.
Selection of the RAM for read or write is determined by the stored program via the data bus control.
Either KY4 RAM - DIN BUS L or KY4 RAM WRITE H must be true to select the RAM. Output
lines are wire ORed with various other microprocessor input ports to be routed to the 8833 tristate
transceivers.
5.3.8 Switch Register (Drawing CS M7859, Sheet 6)
The switch register contains the 16-bit data used and consists of four 74175 quad, D-type, double rail

output latches. The four elements comprising the register are E9, E19, E2, and E15. These units feed
the 8641 bus transceivers E7, E25, E8, and E13 (respectively). Incoming 16-bit data (KY5 BB D00 H
through KY5 BB D15 H) is applied to the 8093 tristate buffers and gated by an appropriate read line
from the data bus control. Outgoing data (BUS D00 L through BUS D15 L) is gated by KY4 EN DB
L, a signal generated in the switch register address decoding logic (sheet 5).
|
The switch register is addressable from the Unibus as address 777570 as described in Paragraph 5.3.9.
5.3.9 Switch Register Address Decode Logic (Drawing CS M7859, Sheet 5)
The switch register address decoding logic allows the Unibus to address the switch register via a
decoding of address 777570. The logic has two outputs:
1.
2.

BUSSSYNL
KY4ENDB- BUSL

K44 EN DB - BUS L at E43-10 gates the data lines onto the Unibus (CS M7859, sheet 6) while the
assertion of BUS SSYN L designates that the slave device has completed its part of the data transfer.
The second stage of the address decode at E32 is gated by assertion of BUS MSYN L at E32-10.
Assertion of MSYN requests that the slave defined by the A (address) lines perform the function
required by the C lines. In this case, KY7 BB C1 H at invertor E40-9 specifies that the data is to be
transferred to the Unibus data lines.

5-7

5.3.10 Bus Address Register (Drawing CS M7859, Sheets 7 and 8)
The bus address register consists of five 74175 quad, D-type, double rail output latches. The five
elements comprising the register are E67, ES7, E73, E58, and E51. Input to the bus address register is
from the address register (KY1 ADRD 0 H through KY1 ADRD 7 H). Outputs are routed to the
display and keypad logic and to the 8641 Unibus transceivers E61, E56, E65, E55, and E50.
A Unibus address is enabled to the Unibus via the bus address transceivers from the bus address

register by KY7 EN AR L generated at E51-11. The switch register is available to the Unibus as
address 777570 via the bus address transceivers and the switch register decode logic. The latter function is discussed in Paragraph 5.3.9.
E67 and E57 contain the keypad scan signals (KY6 SCAN 1 L through KY6 SCAN 6 L) while E73
drives the display (KY6 NUM 1 H through KY6 NUM 3 H).

Incoming 18-bit address information (KY6 BB A00 H through KY7 BB A17 H) is applied to the 8093
tristate buffers and gated by an appropriate read line from the data bus control.
5.3.11
Data Bus Control Logic (Drawing CS M7859, Sheet 5)
The data bus control directs the reading and loading of the various interface module registers, the
reading of the ROMs, and the reading/writing of the RAM. It also determines the direction of data
flow in the interface module and between the interface module and the Unibus, i.e., whether data will
be read from or be routed to the Unibus. A list of I/O functions and associated select signals follows:

Select Signal
READ INPUTOL
READ INPUT 1 L

Function

READ INPUT 2L
READ INPUT 3 L
READ INPUT 4 L

UNIBUS ADDRESS

READ INPUT 5L

KEYPAD REG

READ INPUT 6 L
READ INPUT 7L

MAINTENANCE

LDREGOH
LDREG1H
LD REG2H

BUS ADDR REG

LDREG3H
LD REG 4 H

SWITCH REG

LDREGSH

UNIBUS CONT LOGIC

ENROMI1L
EN ROM 2L

ROM SELECT

RAM WRITE H

RAM WRITE

RAM DINBUSL

ENABLE RAM DATA

DIN DRIVERS DISH

DISABLE DATA IN

UNIBUS DATA

5-8

Specifically, the data bus control logic decodes memory references into three areas (ROM 1, ROM 2,
and RAM) and determines whether the access is a read or write. The logic also decodes 1/0 instructions and generates loading or gating signals depending on the direction of data transfer and the port
selected.
In order to facilitate understanding of the logic, the following explanation of memory address allocation and I/O instruction operation is included.
ROM 2 (E33 and E39)
Memory addressing space spans locations 0 through 777.
ROM 1 (E3 and E21)
Memory addressing space spans locations 4000 through 4777.

RAM (El11 and E27)
Memory addressing space spans locations 20000 through 20017.
The two bus control signals provided by the microprocessor and latched with the upper byte of the
address register, KY1 PC FUN 0 H and KY1 PC FUN 1 H, determine data transfer direction and 1/0
operations. The following table explains the decoding of these signals.

PC FUN 0

PC FUN 1

Memory read of first byte of instruction only (fetch)

Memory read of additional bytes of instruction or data.

Memory write (used only to write into RAM).

I/O operation

Memory reads and writes signify that the address register (KY1 ADRD 0 H through KY1 ADRD 13
H) contains the address of the location in memory to be accessed.
.

The code for 1/O operations, however, signifies a very different situation. This is due to the following
occurring after the initial instruction fetch cycle:
1.

During TSI the content of the A register (accumulator) in the microprocessor is available on
the data lines and is latched into the low byte of the address register.

During TS2 the content of the instruction register (containing the I/0 instruction) is available on the data lines and is latched into the high byte of the address register.

During TS3 of an INP (input) instruction, data on the data lines is loaded into the A register. On OUT (output) instructions, the data is strobed out of the low byte of the address
register.
I/0O Instruction Code:
INP 01 OOMMMI
OUT 01 RRMMMI

Note that the two most significant bits of the instruction will correspond to PC FUN 0 = | and PC
FUN 1 = 0 when loaded into the high byte of the address register, thus denoting an 1/O operation.
Therefore, the data bus control logic determines whether to gate data into the microprocessor during
TS3 (INP) or to load the data from the low byte of the address register into an output port during TS3
(OUT).

The 32 X 8 PROM (E34) does the initial decoding of the type of transfer (read, write, or I/O) from the
signals KY1 PC FUN 0 H and KY1 PC FUN 1 H. If the transfer is a memory read or write, it is
decoded into one of the following four signals. KY4 RAM - DIN BUS L (RAM read), KY4 ROM 1
EN L (memory read in address range 4000-4777), KY4 ROM 2 EN L (memory read in address range
000-777), and an enable which is ANDed with KY1 SYNC H, KY1 TS3 L, and KY1 CK2 L to
provide a write pulse, KY4 RAM WRITE H, to the RAM.

Another enable from the PROM is ANDed with KY1 TS3 L to provide the signal KY4 DIN DRIVER
DIS H. This signal is normally high, disabling the driver portions of the 8833 transceivers (E16 and
E17). It will be low only during TS3 and when data transfer is into the microprocessor.
Two other outputs of the PROM are used for 1/O operations. One output of the PROM (E34-7), when
low, enables the 74154 4-to-16 decoder on all I/0O instructions. The second output (E34-9) determines
whether the 1/0 instruction is INP or QUT. If the instruction is OUT, then the signal will be high.
Note that address register bits KY1 ADRD 11, KY1 ADRD 10 H, and KY1 ADRD 9 H, are applied
to the low order inputs of the 74154. This selects which of the possible ports will be used. The fourth
input, the highest order input, determines if it is an INP or OUT instruction. This input is the ANDed
condition of the PROM output (E34-9), KY1 SYNC H, KY1 TS3, and KY1 CK2. Thus, if the instruction is an INP, then the input gating signal will be one of the lower order eight outputs of the 74154
(KY4 READ IN 0 L through KY4 READ IN 7 L).

If the PROM signal (E34-9) is high, signifying an OUT instruction, then initially a low order output is
selected (does not substantially affect anything) and then a high order output will be pulsed as the
gated clock pulse is applied to the high order input of the 74154. Thus, the high order outputs are
pulsed and buffered to provide loading pulses to the selected registers (KY4 LD REG 0 H, etc.).
5.3.12

Unibus Control (Drawing CS M7859, Sheet 5)

Uhnibus control is accomplished via two 74175 quad, D-type, double rail output latches, E52 and E64.
The stored program input bit configurations are read in under control of an appropriate data bus
control signal, LD REG 5 H. E64 D2 and D3 latches are utilized for the manual clock enable and
manual clock lines while the other six lines are Unibus control signals.

5.3.13

Keypad Scan Logic (Drawing CS 5411800-0-1)

The logic and driving circuitry for the keypad and display elements is located on a circuit board in the
rear of the programmer’s console panel.

Scan signals for the keypad are generated at the interface module (bus address register). These six lines
(KY6 SCAN 1 L through KY6 SCAN 6 L) are then routed through hex 7417 buffer drivers to the
console circuit board where they are designated as READ and DRIVE signals. As indicated by CS
5411800-0-1, sheet 2, READ 1 through READ 5 signals continuously scan the keypad in groups of 4.
As each READ signal is applied to check for a pressed key, a corresponding DRIVE signal is simultaneously generated and applied to the appropriate transistor in the LED display circuitry (CS 11800-01, sheet 3).

A pressed key thus results in activation of 1 to 4 lines. This information is routed out through J1
interface module and applied to the data bus for eventual read-in to the miroprocessor.

to the

3.3.14 Indicator Logic (Drawing CS M7859, Sheet 5)
The indicator control consists of a single quad, D-type, latch configuration, 74175 (E68) and four 7417
open collector inverters (E69) for driving the panel indicators. Input bit coding KY1 ADRD 4 H
through KY1 ADRD 7 H via the stored program determines which of the following panel indicators
are turned on:
1.
2.
3.
4.

BUS ERR
SR DISP
MAINT
BOOT

5.3.15 Halt Logic (Drawing CS M7859-0-1, Sheet 9)
The halt logic allows the console to obtain control of the Unibus in order to perform Unibus transactions. Control of the Unibus is passed to the KY11-LB from the PDP-11 processor via a HALT
REQUEST and HALT GRANT sequence. Use of the HALT/SS key initiates a program sequence
within the KY11-LB to issue a HALT REQUEST to the PDP-11 processor. The procesor will arbitrate the request and at the appropriate time will respond with HALT GRANT. The reception of
HALT GRANT H by the halt logic direct sets the HALT SACK flip-flop on E63-4, causing BUS
SACK L to be generated at E62-13. The set output of the HALT SACK flip-flop (E63-5) sets up the
data input of the HALT BUSY flip-flop (E63-12).
The reception of BUS SACK L by the PDP-11 processor will cause it to drop HALT GRANT H.
When the Unibus becomes free (unasserted BUS BUSY L and BUS SSYN L), the E63-11 will be
clocked, setting the HALT BUSY flip-flop. This, in turn, asserts BUS BUSY L through E62-10 and
causes the RUN indicator to be turned off via the 7417 buffer (E66-12). This logic operates in the same
manner if the HALT GRANT is generated not by a HALT REQUEST from the KY11-LB but by a
HALT instruction in the PDP-11 processor. The output of the HALT BUSY flip-flop (KYB HALT
BUSY H) can be tested by the microprocessor program to check if the console has control of the
Unibus before performing Unibus transactions.
The HALT SACK and HALT BUSY flip-flops are direct cleared by either BUS INIT L from the

Unibus or by the signal KY4 CLR BUS L which can be generated by the microprocessor program.
Clearing these flip-flops relinquishes control of the Unibus to the PDP-11 processor.
The signal KY4 TAKE BUS L, which can direct set the HALT BUS flip-flop, allows the microprocessor program to perform Unibus operations without first obtaining the Unibus through a legal
request. This signal is only used during maintenance mode operation of the KY11-LB to bypass a
failing or hung processor.
5.3.16

Buffers (Drawing CS M7859, Sheet 4)

5.3.16.1

Tristate Buffers (8093) — The following units, which are gated by read input signals from the
data bus control, buffer input data from several sources.

1.
2.
3.
4.

Unibus Data
Unibus Address
Keypad Register
Maintenance Inputs (from processor microprogram counter).

Outputs from the 8093s are wire ORed and sent to the tristate transceivers with the ROM and RAM
data as KY2 DIN 0 H through KY2 DIN 7 H.
5.3.16.2 Tristate Transceivers (8833) — These units buffer data between the microprocessor bidirectional data bus and the satellite logic of the interface module.

5-11

CHAPTER 6

CONSOLE MODE OPERATION

6.1

INTRODUCTION
This chapter is a recapitulation of all console key and indicator functions. Operation, use, and examples of the utilization of each key are presented. Key operations are divided into console mode and
maintenance mode. Examples of console sequences to demonstrate the proper use of the KY11-LB are
presented together with further notes and hints on operation.

6.2
CONSOLE KEY OPERATIONS
This section describes the operation of each key in a step-by-step procedure. The reader is assumed to
have read earlier chapters as some descriptions include the use of keys previously described.

A notation for each key will be introduced in each description and is enclosed in angle brackets < >.
These notations are used extensively in Paragraph 6.4 to describe various sequences of key operations.
<CLR> - Used to clear an incorrect entry or existing data.
1.
2.
3.

Press and release the CLR key.
The display (six digits) will be all zeros.
Clears the SR DISP, BUS ERR, or MAINT indicators if on.

Numerics 0-7 - Used to key in an octal numeric digit (0 through 7).
1.
2.

Press a numeric key (0 through 7).
The corresponding digit will be left shifted into the 6-digit octal display with the previously
displayed digits also being left shifted.
Release the numeric key.

N
LN -

To enter the number <xxxxxx>, e.g., 123456:
Press and release the CLR key (000000 will be displayed).
Press and release the 1 key (000001 will be displayed).
Press and release the 2 key (000012 will be displayed).
Press and release the 3 key (000123 will be displayed).
Press and release the 4 key (001234 will be displayed).
Press and release the 5 key (012345 will be displayed).
Press and release the 6 key (123456 will be displayed).

6-1

The number has now been entered. Leading zeros do not have to be entered.

<LSR> - Used to load the switch register (accessible as Unibus address 777570). |
1.

Press and release the LSR key.

The display will show the data loaded and the SR DISP indicator will be on.

To load the number 777 i.e., <LSR 777>, into the switch register:
1.
2.
3.

Press and release the CLR key.
Key in the number 777.
Press and release the LSR key.

777 will be displayed and the SR DISP indicator will be on.

<LAD> - Used to load the Unibus address pointer prior to performing an EXAMINE, DEPOSIT, or

START.

1.
2.

Press and release the LAD key.
Display will be all zeros.

To load address 200, i.e., <LAD 200>:

Press and release the CLR key.

Key in 200.

3.
4.

Press and release the LAD key.
Display is all zeros.

<DIS AD> - Displays the current contents of the Unibus address pointer.
1.

Press and release the DIS AD key.

Display will show the current Unibus address pointer.

BN
-

To perform the sequence:
LAD 400
DIS AD

Press and release the CLR key.
Key in 400.

Press and release the LAD key (display is all zeros).
Press and release the DIS AD key.
Display shows the 400 from the Unibus address pointer.

<DEP> - Used to deposit a number into the location pointed to by the Unibus address pointer.
1.

2.
3.

Processor must be halted (RUN indicator off); otherwise key is ignored.
Press and release the DEP key.
Display shows the data deposited.

6-2

To deposit <DEP xxxx> (e.g., 5252) into location 1000, the sequence is as follows:

DAL~

LAD 1000
DEP 5252

Press and release the CLR key.
Key in 1000.
Press and release the LAD key.
Key in 5252,
Press and release the DEP key.

<EXAM?> - Used to examine the contents of a location pointed to by the Unibus address pointer.
1.
2.
3.

Machine must be halted.
Press and release the EXAM key.
Display shows the contents of the location examined.

To examine general-purpose register R7 (program.counte'r) at Unibus address 777707, the following
sequence is used:

SRS

LAD 777707
EXAM

Press and release the CLR key.
Key in 777707.
Press and release the LAD key.
Press and release the EXAM key.
The contents of R7 will be displayed.

<CNTRL>
- The CNTRL keyis always usedin conjunction with some other key. When it is used it
must be pressed and held down while the second keyis pressed and released.
<CNTRL-HLT/SS> - Used to halt the processor.
1.
2.
3

Press and hold down the CNTRL key.
Press and release the HLT/SS key.
Display will show the current contents of R7 (program counter) and the RUN indicator will
be off.
:
Release the CNTRL key.

If the processor is already halted, the use of the HLT /SS key will single-instruction step the processor.
(The CNTRL key is not required to single-instruction step the processor once halted.)
1.
2.
3.

Press and release the HLT/SS key.
Processor will perform one instruction and halt.
Display will show the new current contents of R7 (program counter).

6-3

<CNTRL-CONT> - Used to allow the processor to begin running from a halt.
1.
2.
3

Press and hold down the CNTRL key.
Press and release the CONT key.

Processor will run unless a program halt instruction is encountered. The RUN and SR DISP
indicators should be on and the contents of the switch register should be displayed. If a halt
instruction was encountered, the indicators will be off and the program counter will be
displayed.
Release the CNTRL key.

NOTE

If the processor is already running, use of
<CNTRL-CONT> will result in the switch register
being displayed; there will be no other effect on the
processor.

LN
-

<CNTRL-BOOT> - Used to initiate running of M9301 Bootstrap program.
Processor must be halted.
Press and hold down the CNTRL key.
Press and release the BOOT key.

Processor should start running (RUN indicator on) the bootstrap program selected on the
M9301.
NOTE

For more information concerning the M9301 Bootstrap program, consult the system users guide.
5.

Release the CNTRL key.

<CNTRL-START> - Used to start the processor running a program from a given starting address.
Processor must be halted; otherwise key is ignored.

Release the CNTRL key.

Press and hold down CNTRL key.
Press and release the START key.

RUN indicator will be on unless a halt instruction is encountered. The SR DISP indicator
should also be on and the contents of the switch register should be displayed.

To start running a program at location 1000, the following sequence is used:
Press and release the CLR key.
Key in 1000.
Press and release the LAD key.
Press and hold down the CNTRL key.
Press and release the START key.
'
Release the CNTRL key.

<CNTRL-INIT> - Generates a Bus Initialize without the processor starting.
Processor must be halted.
Press and hold down the CNTRL key.
Press and release the INIT key.
Bus Initialize will be generated for 150 ms.
Release the CNTRL key.
6-4

<CNTRL-7> - Used to calculate the correct address when a mode 6 or 7 register R7 instruction is
encountered.
1.
2.
3.

Press and hold down the CNTRL key.
Press and release the 7 key.
Display will show the new temporary register which contains the old temporary register plus
the Unibus address point or plus 2.

See Paragraph 6.4 for an example.
<CNTRL-6> - Used to calculate the offset address when mode 6 or 7 instructions other than register
R7 are encountered.
1.
.

Press and hold down the CNTRL key.
Press and release the 6 key.

Display shows the new temporary register, which contains the old temporary plus the switch
register.

Release the CNTRL key.

See Paragraph 6.4 for an example.
<CNTRL-1> - Used to enter the console into maintenance mode. Maintenance mode should only be
used as an aid to troubleshooting hardware problems. Maintenance mode provides no help in debugging software problems.
1.

Press and hold down the CNTRL key.

2.
3.

Press and release the 1 key.
MAINT indicator will be on and the MPC (microprogram counter) will be sampled and

displayed.
Release the CNTRL key.

6.3 NOTES ON OPERATION
An erroneous display will result if, while the processor is running and the switch register is being
displayed, a numeric key is pressed. Although the SR DISP indicator will remain on, the display no
longer reflects the actual contents of the switch register. If at any time while the processor is running, it
is desired that the switch register contents be displayed, the CNTRL-CONT keys should be used.
As a general practice, prior to entering a new 6-digit number and if the display is nonzero, the CLR key

should be used to initially zero the display.
In order to single-instruction step the processor from a given starting address, the program counter
(R7) must be loaded with the starting address using the Unibus address of R7 (777707) i.e., to singleinstruction step from the beginning of a program starting at location 1000, the following sequence is
necessary:

LAD 777707
DEP 1000
CNTRL-INIT (if desired)

HLT/SS
HLT/SS
etc.

The console requires an 18-bit address. This is especially important to remember when accessing device

registers (i.e., 777560 instead of 177560). Otherwise an erroneous access to memory or to a nonexistent
address will occur.

The Unibus addresses for the general-purpose registers can only be used by the console. A PDP-11
program using the Unibus addresses for the general-purpose registers will trap as a nonexistent
address. Also, internal registers R10 through R17, which are used for various purposes (depending
upon processor), may be accessed by the console through Unibus addresses 777710 through 777717.
The BUS ERR indicator on the console reflects a bus error by the console only. The indicator will not
reflect bus errors due to other devices succh as the processor.

6.4

EXAMPLES OF CONSOLE SEQUENCES

This section combines key operations with example sequences to demonstrate the proper use of the
KY11-LB Programmer’s Console.

The following sequences use the notations for key operations as described in Paragraph 6.2.

The angle brackets <

> will be used in the sequences to identify the display contents after the

operation is performed, i.e., LAD 200 <0>
1.
2.
3.
4.
5.

Press and release the CLR key.
Press and release 2 key.

Press and release 0 key.
Press and release 0 key.
Press and release the LAD key.

000000 will be displayed in the 6-digit readout.

Example 1

This sequence uses the examine function and the switch register Unibus address 777570 to read the
contents of the switch register.

LSR 123456
LAD 777570
EXAM
DIS AD
LSR 777
EXAM

<123456>
<0>
<123456>
<777570>
<777>
<777>

Example 2

This sequence demonstrates the use of the following keys: LAD, DIS AD, LSR, EXAM, DEP,
CNTRL-START, CNTRL-CONT, and CNTRL-HLT/SS.

This example loads the following program into memory, which is then run to demonstrate various
operations.

Program

Memory Location/Contents

1000/13737
1002/177570
1004/1014
1006 /0000
1010/137

;Move the contents of
the switch register to
memory location 1014
;Halt
;Jump to location 1000

1012/1000
1014/0000
6-6

Sequence
LAD 1000
DEP 13737
DEP 177570
DEP 1014
DEP
0
DEP 137
DEP 1000
DEP0
LAD 1000
EXAM
EXAM
EXAM
EXAM
EXAM
EXAM
EXAM
DIS AD
LSR 123456
LAD 1000
CNTRL-START
LAD 1014
EXAM
DEP
0
EXAM
DIS AD
LSR 125252
CNTRL-CONT
LAD 1014
EXAM
DEP
0
LAD 1006
DEP 240
EXAM
LAD 1000
CNTRL-START
LSR 70707
CNTRL-HLT/SS
LAD 1014
EXAM
HLT/SS
HLT/SS
HLT/SS

LSR 05252
HLT/SS
LAD 1014
EXAM

<0>
<13737>
<177570>
<1014>
<0>
<137>
<1000>
<0>
<0>
<13737>
<177570>
<1014>
<0>
<137>
<1000>
<0>
<1014>
<123456>
<0>
<1010>
<0>
<123456>
<0>
<0>
<1014>
<125252>
<1010>
<0>
<125252>
<0>
<0>
<240>
<240>
<0>
<125252>
<10707>
<0>
<10707>

<052525>
<0>
<052525>

6-7

Example 3

This sequence demonstrates the use of CNTRL-7 and CNTRL-6. The following data are loaded into
memory:

1000/177
1002,/100
1004,/000
1006/5060
1010/1020

1104/1006
RO = 777760

The sequence to load the data is as follows:
LAD 1000
DEP 177
DEP 100
DEPO
DEP 5060
DEP 1020
LAD 1104
DEP 1006
LAD 777700
DEP 777760

<0>
<177>
<100>
<0>
<5060>
<1020>
<0>
<1006>
<0>
<777760>

Sequence

LAD 1000
EXAM
EXAM
CNTRL-7
LAD
EXAM
LAD
EXAM
EXAM
LSR
LAD 777700
EXAM
CNTRL-6
LAD
EXAM

<0>
<177>
<100>
<1104>
<0>
<1006>
<0>
<5060>
<1020>
<1020>
<0>
<777760>
<100006>
<0>
<177>

CHAPTER 7
MAINTENANCE MODE OPERATION

7.1
INTRODUCTION
This chapter covers the keypad facilities of the programmer’s console available for hardware maintenance of the processor.
7.2

MAINTENANCE MODE KEY OPERATIONS
The following definitions apply to a subset of the same keys used in console mode; however the
functions and operations differ from those in console mode. In general, console mode functions are
not available while in maintenance mode, and many keys have no function in maintenance mode.

NOTE
Maintenance mode operation is indicated by the
MAINT indicator being on.

In order to use the hardware maintenance features available in maintenance mode, the maintenance
cable (11/04) or cables (11/34) must be connected between the K'Y 11-LB interface board (M7859) and
the corresponding processor board (M7263-11/04, M7266-11/34, M8266-11/34A, or
M8267-FP11A). An exception to this is the 5 (maintenance mode) operation which allows the console
to examine or deposit into memory or device registers without the processor being either present or
functional.
DIS AD (Maintenance Mode) — Used to display Unibus address lines.
1.
2.

Press and release the DIS AD key.
Unibus address lines will be sampled (read once) and displayed, i.e., display will not be
updated as address lines change.

EXAM (Maintenance Mode) ~ Used to display Unibus data lines.
1.
2.

Press and release the EXAM key.

Unibus data lines will be sampled and displayed.

HLT/SS (Maintenance Mode) - Asserts manual clock enable and displays MPC (microprogram

counter).
1.

Press and release the HLT/SS key.

Manual clock enable will be asserted.
MPC will be sampled and displayed.

CONT (Maintenance Mode) - Single microsteps the processor through one microstate and displays

the MPC.
1.
2.
3.

'
Press and release the CONT key.
Manual clock will be pulsed.
New MPC will be sampled and displayed.

BOOT (Maintenance Mode) - Boots the M9301. If manual clock enable is asserted, the M9301 routine
will not be entered but because the M9301 simulates a power fail the processor will power up through
location 24.
1.
2.

Press and release the BOOT key.
The display is not affected. If manual clock enable is asserted, the MPC is now at the
beginning of the power-up sequence. To see the new MPC, use the HLT/SS key.

START (Maintenance Mode) - Drops manual clock enable.

2.
3.

Press and release the START key.

Manual clock enable is released.
MPC will be sampled and displayed.

CLR (Maintenance Mode) - Returns console to console mode operation.
Press and release the CLR key.
MAINT indicator is off.
Processor should halt.
Program counter should be displayed.

S (Maintenance Mode) - Allows the console to take control of the Unibus if a processor is not in the
system.

1.
2.
3.

Press and release the 5 key.
The MAINT indicator will be off (console mode operation now).
Console attempts to read the program counter which is not present and therefore the BUS
ERR indicator will be on.

7.3

NOTES ON OPERATION
If the single-microstep feature in maintenance mode is to be used, it is preferable that the processor be
halted prior to entering maintenance mode, if it is possible. This is because the assertion of manual
clock enable, which turns off the processor clock if it is running, cannot be synchronized with the
processor clock. Therefore, if the processor is not halted, the clock may be running and the assertion of
manual clock enable may cause an erroneous condition to occur.
In order to single-microstep the processor from the beginning of the power-up sequence, the following
steps may be used:

Halt the processor if possible.

Use CNTRL 1 to enter maintenance mode.

Use HLT/SS to assert manual clock enable (RUN indicator should come on).

Use BOOT to generate a simulated power-fail (will not work if M9301 is not present in the
system).

7-2

Use HLT/SS to display the MPC (microprogram counter) for the first microstep in the
power-up routine.
Use CONT to single-microstep the processor through the power-up routine. (The new MPC
will be displayed at each step.)
Unibus address lines and Unibus data (see NOTE below) lines may be examined at any
microstep by using DIS AD and EXAM, respectively. Use of these keys does not advance
the microprogram. To redisplay the current MPC without advancing the microprogram, use
the HLT/SS key.
To return from maintenance mode, use the CLR key.
To single-microstep through a program, the program counter (R7) must first be loaded with
the starting address of the program as in single-instruction stepping the processor prior to
entering maintenance mode.
NOTE
Because the data transfer occurs asynchronously
with the processor clock, Unibus data will not be displayed on DATI in maintenance mode when using
the console with an 11/04 processor. Unibus data on
DATO on the 11/04 and both DATI and DATO on
the 11/34 will be displayed.
Due to hardware changes, the M8266 module will
gate the AMUX lines onto the Unibus when manual
clock enable is asserted and a Unibus transaction is
not occurring.

7-3

CHAPTER 8
KY11-LB MAINTENANCE

8.1

PRELIMINARY CONSIDERATIONS
The following is a guide to locating possible problems on the KY11-LB.

Power Switch Failure - If the power switch fails to control the power supply, check cable

7011414-2-2 (BA11-L) at J2 or cable 7011992-0-0 (BA 11-K) at Faston tabs TB4 and TBS5 on
the bezel-mounted board to ensure that cable(s) are securely and correctly installed.

If the power switch does turn on the power supply (fans turn) but the DC ON indicator does
not come on, check cable 7011992-0-0 (BA11-K) at tabs TB6 and TB7 on the bezel-mounted
board.
If the four indicators on the left side of the keypad are all on, then the cable 7012214-0-0
connecting the bezel-mounted board to the interface board (M 7859) is probably plugged in
backward on one end.
|
If no display and none of the four indicators are on, then check cable 7012214-0-0 at J1 on
the bezel-mounted board and M7859 board to ensure that it is correctly and securely
installed.

Note that there should be no cables from either the bezel-mounted board or the M7859

board attached to the backplane. The connection at the backplane is for use by the KY11LA Operator Console only.

If the RUN indicator is on but there is no display and no response from the keypad, the
problem is probably at the M7859 Interface module. Check the module to ensure that the
microprocessor chip (E18) is securely installed in its socket.
If the display works and the console responds to the keypad except for the BOOT key, check
that cable 7011413-0-0 is properly connected to the M9301 and to the bezel-mounted board
at tabs TB1 and TB2.
If the display MPC, single microstep, etc. functions in maintenance mode do not work
correctly, check that the cable(s) from J2 and J3 of the M7859 are properly installed.
NOTE
These cables should be installed only for maintenance of the processor. By disconnecting these cables
for normal operation, the effect is that the maintenance functions are nonoperative except for the
TAKE BUS function.

8-1

8.2

M7859 FAILURES

In general, there are two levels of possible failures on the M7859 module. The first level and most
difficult to fix is the microprocessor and its support logic which constitutes about 1/3 of the logic. The
second level is failures which occur in the peripheral logic constituting the Unibus interface and the
|

display /keypad interface. These are generally easier to troubleshoot.

Generally, a first level failure is readily apparent and will usually be indicated when no display is on
and the only indicators on are DC ON and RUN.

A second level failure, although easier to troubleshoot, is not always readily apparent as it may only
occur on certain key functions or may be data dependent. A failure on the display/keypad interface
would be indicated by odd displays, row, or column failures on the keypad. The Unibus interface can
be tested with a good confidence level by loading the switch register with a 123456 data pattern and
then reading it back over the Unibus by examining location 777570.

The following is a guide to troubleshooting a failing M7859 module. Generally, the minimum equipment needed is a dual-trace oscilloscope with delayed sweep.

Check that 9 V is available at pin 1 of the microprocessor, E18.

Check that the clock frequency is 1.0 MHz + 2% at the test point, TP1. The frequency can
be corrected if needed by adjusting the variable resistor at the top of the module.

Check that the two clock signals are at E18-15 and E18-16. These clocks should be 500 kHz
frequency with nonoverlapping positive pulses of 0.5 ms duration (Figure 8-1).

E18-16

-5

——
2 usec—————.l

E18-15 02

| .5 usec I

FIG X
11-4858

Figure 8-1

Clock Waveforms

8-2

Check the signal at E18-18 which should be at logic low. If the signal is high the micro-

processor may not have responded to the interrupt request on power-up. If the signal is
toggling, this may be indicative of a different class of problems discussed in the following
paragraphs.
The M 7859 logic is such that if the microprocessor encounters a HALT instruction and goes
to the STOP state, peripheral logic will automatically try to restart the microprocessor from
location 0. Hence, if there are problems in the microprocessor support logic, such as address
or data failures, time state decoding failures, etc., the microprocessor will not follow the
program and generally encounters a HALT instruction.
The general technique to solve this class of problems is to sync off of the signal STOP L and
to use delayed sweep to track addresses backward to find the specific failing address. A
quick check of the number of times TS1 L is true between the times that STOP L is true will
give an idea of how far into the program the failure occurs. In general the easiest technique is

to use the TS3 L signal as a visual key on one channel while using the other channel to probe
addresses, data, timing signals, etc.

CHAPTER 9
KY11-LB INSTALLATION

9.1
KY11-LB DESCRIPTION
The KY11-LB is a programer’s console option for both the 11/04 and 11/34 CPUs. It replaces the
KY11-LA (operator’s console) which is the standard console on 11/04s and 11 /34s. The hardware in
the KY11-LB option is exactly the same for both the 11/04 and 11/34. The KY11-LB contains a bezel
assembly (consisting of a keypad, 7-segment display, indicator lamps, and ON/OFF switch) and a

separate SPC quad interface module (M 7859). Also, three loose piece cables: two 10-conductor, 45.7
cm (18 inch) long cables and one 20-conductor cable. The two 10-connector cables are not required for
normal console functions and should only be installed when using the console in maintenance mode.

9.2
CPU BOX TYPE
PDP-11/04s and 11/34s are available in both the BA11-L 13.4 cm (5-1/4 inch) box and BA11-K 26.7

cm (10-1/2 inch) box. The difference between these two boxes creates the only difference in installing
the KY11-LB. In all cases, the 10-conductor cable, running from the operator’s console to the CPU
backplane, is not used and must be removed when the KY11-LB is installed. It is extremely important
not to connect this cable to the KY11-LB as a short circuit may result.

9.3

CPU DIFFERENCES
The 11/04 is a single-module CPU (M7263). The 11/34 is a 2-module CPU (M7265 and M7266).
Maintenance mode connections between KY11-LB and 11/04 are made on the M7263. Maintenance

mode connections between KY11-LB and 11/34 are made on the M7266 (Figures 9-1 and 9-2). Note
that all figures in this procedure show the M7266 module (11/34). This is done because the hook-up
for normal KY11-LB operation is the same for both CPUs.
To identify cables and part numbers for cables, refer to Figure 9-3.
9.4

BAI11-L 13.3 CM (5-1/4 INCH BOX) INSTALLATION
1.

Remove the operator’s console (KY11-LA), noting to which Faston tabs the M9301 is connected. The connections will be to the same tabs on the KY11-LB. The cable from H777
Power Supply plugged into J2 on the KY11-LA will plug into J2 on the KY11-LB. The cable
from the CPU backplane to J1 on the KY11-LA must be removed. No connection is made
from the backplane to the KY11-LB.

9-1

CONNECTOR FOR KY11-LB
CONNECTS TO J2 ON M7859
PIN 1

D
®

a—

DURING MAINT MODE OPERATIONS

/ ©®

/1 N

M7263

(11/04)

\_’___\

11-4849

Figure 9-1

M7263

CONNECTORS FOF KY11-LB
CONNECTED TO M7859 ONLY
DURING MAINT MODE OPERATION

Em@/@
E111

-otnnq

."'\q

[T
S
Y

E94

M7266
(11/34)

~—

—

T~
11-4850

Figure 9-2

9-2

M7266

INDICATES PIN 1

F"<']:

—)

]
20 CONNECTOR

10 CONNECTOR

PART #70-11411-1D-0

(18 in. LONG)

PART #70-12214-0-0

PART #70-11411-0J-0

LENGTH 27 4" + 1

(8 in. LONG)

11-4851

Figure 9-3

Cables

Install M7859 (KY11-LB interface) in any SPC slot (within CPU backplane) and connect it
to the KY11-LB bezel as shown in Figure 9-4.
CONFIGURATION NOTE
The M7859 consumes 2A at +5 V and can only be
plugged into the CPU backplane.
‘
WARNING
When doing any reconfigurating of the CPU back-

plane that might be necessary to make room for the
M7859, be sure that the M9302 is never installed in a

modified Unibus slot (which results in short circuits).
9.5

BAI11-K 26.7 CM (10-1/2 INCH BOX) INSTALLATION

Remove the operator’s console (KY11-LA), noting to which Faston tabs the M9301 is connected. The connection will be the same tabs on the KY11-LB (Figure 9-5). You will notice
that J2 on the operator’s console is not used on the BA11-K box. The signals and voltages
that come in on this jack in the BA11-L box come in on Faston tabs in the BA11-K box. The
cable connecting the CPU backplane to J1 on the operator’s console must be removed and
no connection from the backplane to the KY11-LB is made.

Install M7859 (KY11-LB interface) in any SPC slot (with CPU backplane) and connect to
KY11-LB bezel as shown in Figure 9-5.
WARNING
When doing any reconfigurating of the CPU backplane that might be necessary to make room for the
M7859, be sure that the M9302 is never installed in a
modified Unibus slot (which results in short circuits).

LI
J2

M7266

CPU BACKPLANE

RED STRIPE _|

10 CONDUCTOR CABLE
10 CONDUCTOR CABLE ~5

RED STRIPE
RED STRIPE

TM81

7TB2

TB3

TB4

TB5

TB6

OPERATORS CONSOLE KY11-LA

P
2

M7266

M7859

»*

\T D

—

CPU BACKPLANE

REDSTRIPE
:

10 CONDUCTOR CABLE -~

20 CONDUCTOR CABLE

TB1

TB2

RED STRIPE —

TB3

TB4

TB5

TB6

PROGRAMMERS CONSOLE KY11-LB

TOM9307 wa

)

¥ THIS CONNECTOR NOT USED
11-4847

Figure 9-4

BAIll-L

L
J2

M7266

CPU BACKPLANE

RED STRIPE

10 CONDUCTOR CABLE ~5\,

RED STRIPE

RED/BLK T.P,

BT BTENA +5Vl GND

U Ut

TB1

TB2

TB3

GND

TB5

TB6

U U

TB4

OPERATORS CONSOLE KY11-LA

M7266

M7859

*
W

—

N
TM\

CPU BACKPLANE

REDSTRIPE
RED/BLK T.P.

20 PIN CABLE

BLUE/BLK T.P.

RED STRIPE

ENA

+5V

GND

U U U

TB1

TB2

TB3

U U

TB4

TBS

TB6

—F

PROGRAMMERS CONSOLE KY11-LB

TOMI301 -

X H775C
11-4848

Figure 9-5

9-5

BAI11-K

9.6 MAINTENANCE MODE HOOK-UP
To utilize the KY11-LB as a maintenance tool for troubleshooting the CPU or
system,

additional

cable(s) must be installed. The 11/04 requires one additional cable and the 11 /34 requires two additional cables.

PDP-11/04 (Maintenance Mode Cabling)

The 11/04 requires only one additional cable for maintenance mode operation. This
10-conductor
cable (Part No. 70-11411-1D-0) connects J2 of the M7859 to the unmarked male
connector on the
M7263 (11/04 CPU). The cable (70-11411-1D-0) has a pointer on each end to indicate pin 1 as shown
in Figure 9-3. Install the cable with the pointer on the end of the cable lined up with
pin 1 on the CPU
module (M7263). Pin 1 on M7263 is called out on Figure 9-1. Points on J2 (M7859)
and the cable
should also be lined up.
PDP-11/34 (Maintenance Mode Cabling)
The 11/34 requires two additional cables for maintenance mode operation. Both cables
are the

and are the same part as is used on the 11/04. See Figure 9-3 for part number.

same

NOTE
Maintenance cables for both 11/04 and 11/34 are all

45.7 cm (18 inch) long, 10-conductor cables.

When installing maintenance cables connect J2 (M7859) to J1 (M7266) and
J3 (M7859) to J2 (M7266).
The pointers on the cable and board must be matched at both ends of the cables.

9-6

APPENDIX A
KY11-LB MICRO-CODE LISTINGS

A-1

RYLLLE

PROGRAM

RT-11

MACRQO

FMACROS

UMD 210

FOR

LATLY

8008

FAGE

RIS

)

KYL1LE

FROGRAM

RT-11

MACRKRO

YMO2-10

1LIL2E

F&GE

RT-11 MACRD

UMQO2-10

QOL1L3T2E

FaGE

)

KYllLH FROGRAM

000000

)

00QL00

0GOOO0

Q0B001

2]
¥4

QOOQ02
OOQO03

KYLLLER

NOOOO4

QOQA0YH

QOQQ0S

QOQOOY

OO0003

QQOO0Y

00040

Q00403

Q00402

NUMEX

QOQA01

NUMAX

QQO400

UMEX

F B QG R A M

NLIMOX
S

NLIME
X

Q000G
Q00001
0OQO00

90000
QGOGO0

STARTS

SINTTEAL
TZE

BEGINZ

§FRESET

PCoT0

10,

RETTSTER

QOO0
6100 ToN )

Q&G

QGO0N2

CAOY

FOINT

ENARLE

ADUIRES:

00003

LA X

00003

Vb6

QOQ04

020

000085

0O005

104

QQO0E

013

Q007

QOO

00010

Q01O

104

00011

00l

00012

QOO

00013

OVER?

00013

Q44

QQ0: 4

QQ0

0001E

00016

Q0017

JME

OVETR

SME

BEGIN

LET

Lty

QOO0LE

QOOLS
QOOLY

[

FOINT

LOCATION

(RaM)

FOINTED

§ ZERQ

v ZERD

REGLSTER

304
REGL
S

MEMORY

370
D&

35000

s DECIRETMENT

REGESTER

REGL

yJUME

BACK

LUNTIL

DESEFLE

sLALL

HLSrFLAY

RAM

L.
TS

ALl

ZERTIETD

120

(O3

)

GO0
DrsE1s

Cal

SURROUTINE
. STaYs

Q00
KY 11

RKAM.

EOGRAM

RT-11

Moy R

QCE1RTEE

FaGE

A-2

37
38

SLINTIL
00024

JSMEKEYSEY

00026

104

QOO27
Q0030

125
000

KEY

DEPRESSED

RETURNG

FROM

DESPLAY

sLUME

TOREY

POTEPLAY

SUBROUTINE
.

FROGRAM

SUBROUTINE

HALT

OUCURS.

’

3¢

SERVICE

ROUTINEG,

40
41

4.3

Q0031

OEsHLST

X0%

00031

FFOR

00032

Q0032

Q44

QOO33

200

0034

L8O

00035

OO034

Q00

113

s IFOBIT O DS

00041

040
LEG

00043

00044

D00

00045

00044

Q40

REGS

QOOHO

D&Y7

010

00052
GOO%HZ

02L&
00

NIVE

FLE

NXT

tLHI

Q00%4

H56

0005

QO0%h4

G570
58

044

QOOH4

200

00057
GQOG7

J40

00061

001

00082

006
00

HLTS

LCT

QOOLY

FLAG

BRIT

THE

$JLIMF

BUSY

BEING

SET, (KYLL-LE

RBUSY)
.

Mal
T BUSY

THE

PREVENT

FURTHER

SERUTCING

FLaG,

H&LT

FOTHERWISE

VICE

CONTINUE

SLOATE

L.y

FMALGK

OFF

NIOE 200

FPREEN

ROUTINE,

THE

DISPLAY

ROUTINE,

THE

©C

WITH

KEYSERVICE

FLAG

DISFLAY
STORED

DIGLT

SERVICED

FERESET

BUT

STILL

DEPFRESSED,

REGUSTER

WITH

A-WITH

JERD,

USED

:
COVPRESET

'
,
REGO

POUTHFUTS

:
THE

ZERD

TURN

OFF

THE

DESFLAY.

RT-11 MACRO VMO2-10

'
COUNTER,

THIS BIT WHEN SET INOTCATES THAT A KEY HAS

:
LAl

COLLT

KYL1LE PROGRAM

FOR

RBUS

121

066

HALT

FROGROM

DUT

00063

FOR

'
nDIseEss

O008S

00064

LT
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TEMMORARY

APPENDIX B
IC DESCRIPTIONS

B-1

7493

BINARY COUNTER

RO (1)

R1(1)

12
J

O3S
J

—QT

¢}

R3(1)

08
J

F—O T

R2{1)

11
J

11—

CLR

CLKBC

CLKO

LOGIC

DIAGRAM

|03

R3(t) ——
7493

R2(1) p—

R1(1) 22
12
RO(1) p—

CLKBC

CLKO

TOI

VCC= PIN

GND:=PIN 10

7493

TRUTH

TABLE

(SEE NOTES)
CLKBC

INPUT

Rl
R2 R3
(o

tl1{1]o0

¢]

O=LOW

OUTPUT

PULSE | ..y
(M)

Notes:

Truth table applies when 7493 is used as 4-bit ripple — through counter.

Output RO(1) connected to input CLKO.

3. To reset all outputs to logical 0 both pins 02 and

1= HIGH

03 inputs must be high.
4.

Either (or both) reset inputs RQ(1) (pins 02 and (3}
must be low to count,

IC-7493

8641

QUAD BUS TRANSCEIVER

The 8641 consists of four identical receiver/drivers and a single enabling gate in one package for
interfacing with the PDP-11 Unibus. The transceiver drivers are enabled when ENABLE A and
ENABLE B are both low. The other input of each driver is connected to the data to be sent to the
Unibus. For example, when enabled, DATA IN 1 (pin 2) is read to the Unibus via BUS 1 (pin 1).
During a write operation, data comes from the Unibus as BUS 1 (pin 1) and is passed through the
receiver to the device as DATA OUT 1 (pin 3).

BUS 1 ——]

DATA IN1 —2]
DATA OUT 1 ——|
BUS 2

—2

8641

ENABLE A ——]

GROUND——

[

;

—

DATAIN1—

—

ENABLE A:DO*
ENABLE B

BUS 4
DATA IN 4

L13 paTA OUT 4

DATA IN 2 ——
DATA OUT 2 —2]

_—

Vee

BUS 3
DATA
IN 3
pata ouT 3

ENABLE B

BUS
1

{

~_~/

DATA OUT

I1IC - 8641

B-3

74154 4-LINE TO 16-LINE DECODER
The 74154 4-Line to 16-Line Decoder decodes four binary-coded inputs into one of 16 mutuallyexclusive outputs when both strobe inputs (G1 and G2) are low. The decoding function is performed
by using the four input lines to address the output line, passing data from one of the strobe inputs with
the other strobe input low. When either strobe input is high, all outputs are high.

t150—)

f14 o.fi_
¢

12—

T E
fol 10

16 OUTPUTS

1 OF 16 MUTUALLY

fg o— | EXCLUSIVE OUTPUTS

74154

DECODED FROM BCD INPUT

f210— | WHEN BOTH STB1 AND
fe b 7

STBO ARE

LOW

fsP—

5
f4 oO——

Bco | -2

INPUT

FOR DECODING

4
f3 O——

dp2

5 ==

fip—

23 DO

fo D——J
1

STB1

STBO

Notes For Demultiplexing:

+5V = PIN Zf"

GND=PIN 12

Inputs used to address output line.

Data passed from one strobe input
with other strobe held low.

Either

strobe high gives all high outputs.
IC-74154

B-4

74175

QUAD STORAGE REGISTER
TRUTH

TABLE

INPUT

|OUTPUTS

'nf1

R{1)R(O)

H
L

L
H

th = Bit time before
clock pulse.
tht1=Bit time after

clock pulse.

(353

R3(1) E—W
14

R3(0) —

1
ran
TM

1
202

74175

— Dt

poo®

; [ OUTPUTS

1o ROLZL
——Q[CLK FOO,
CLEAR

R1(1) p—

rit0) |5

L—‘DO

RO(1) —

(5)

ril

RO(0) ._E_J

CLR

CLK

(1)
R

QICLK (01)r—(-6—)0
CLEAR

[

(12)

D2 o

(10)

faF—
R2

ek o)
CLEAR

L7
D3 13 13!

CLOCK (9)

fiJ

CLEAR

0—

15
D3 23)—(—)0

QCLK (o)“—‘”-o
CLEAR

]

Pin (16)=Vcc , Pin (8)=GND
IC-74175

B-5

Reader’s Comments
. KY11-LB Programmer’s Console/Interface
Module Operation and Maintenance Manual
EK-KY1LB-MM-001

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