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EK-OKL10-MG-003

April 1985

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Document:	-003 KL10 Maintenance Guide Volume 1 Rev 3 Apr85
Order Number:	EK-OKL10-MG
Revision:	003
Pages:	395
Original Filename:	EK-OKL10-MG-003_KL10_Maintenance_Guide_Volume_2_Rev_3_Apr85.pdf

OCR Text

K10
Maintenance
Guide

Company
Confidential

VolumeIl

dlilalitla]l

EK-OKL10-MG-003

KL10

Maintenance Guide
Volumell

Prepared by Educational Services
Digital Equipment Corporation
Marlborough, MA

FOR INTERNAL USE ONLY

1st Editibn, February 1979

2nd Edition, December 1983
3rd Edition, April 1985

The material in this guide is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for

any errors that may appear in this guide.
Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation.

Eflfiflflfl

EDUSYSTEM

RSTS

DEC
DECsystem-10
DECSYSTEM-20
DECUS

IAS
MASSBUS
OMNIBUS
0s/8

RSX
UNIBUS
VAX
VMS

DIBOL

PDP .

~iii-

ORDERING

KL10/KS10

Maintenance

Guides

order

one or

the

both

distribution

Publishing

Order

PROCEDURES

these

list),

guides

send

Circulation

your

(if

you

have

order

TWX

guide

per

name)

never

been

memo

to:

Services

Processing

NRO-2/W3
TWX

Specify

RCS

Code

the

NR12

following:

Name

Badge
Cost

Number
Center

Location
Quantity:

(only

one

EK-OKL10-MG

(KL10

Maintenance

Guide)

EK~OKS10-MG

(KS10

Maintenance

Guide)

copy

each

KS10 Maintenance Guide Volume II
If

you

not

have

Volume

receive

Volume

(Software

1980,

then your

June
for

that

gqguide.

Publishing
Order

the

name

order

KS10

may

not

Volume

Maintenance

and

II,

Guide,

Diagnostics),

send

the
a

but

distribution

TWX

did

distributed

memo

list

to:

& Circulation Services

Processing

NRO-2/W3
TWX

Specify

RCS

Code

the

NR12

following:

PLEASE

ADD

NAME

THE

DISTRIBUTION

LIST

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Cost

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Location
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Deletions
To

and

deleted

subscription

from

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List

(Volume

only)

Transfers
the

someone
&

distribution

list

else,

TWX

Circulation

send

memo

transfer

your

to:

Services

Maintenance

NRO-3/M1
TWX

RCS

Code

Specify

the

following:

Remove:

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Name

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Cost

Number
Center

Location
Add:

New

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Cost

Number
Center

Location

State

which

Maintenance

Guide

you

want

stop

receiving

transfer:
EK-OKL10-MG

(KL10

Maintenance

Guide)

(KS10

Maintenance

Guide)

EK-0OKS10-MG

—iv-

the

Reader:

IMPORTANT - This guide contains information for internal use only

and is intended for use by DIGITAL Field Service engineers only.
Refer to the Field Service Methods and Procedures Manual for
company policy pertaining to internal information.

OBJECTIVE - The objective of this guide is to organize and present
the maintenance information necessary to resolve 80% of all KL1O
hardware malfunctions.

in subsequent
To properly maintain and improve this guide
revisions, we need feedback concerning accuracy and clarity. This
communication is very helpful to your fellow engineers. Please
and comments that would
suggestions,
forward any corrections,
improve

to:

this guide

Customer Services, Systems Engineering
RE: KL10 Maintenance Guide

(CSSE)

MR01-1/S35

ORGANIZATION - Volume I contains general maintenance

pertaining

the KL10.

The volume

separate Table of Contents as

information

sections with

into

GENERAL INFORMATIONbconsists of miscellaneous maintenance
information that cannot be classifed and filed

the

is divided

follows.

SWITCHES

JUMPERS

AND

in any of

sections.

hardware

other

contains

hardware switch positions and

pertaining

information

jumper connections.

TABLES AND MAPS describes the process tables and bit maps
the KL10 mainframe and peripheral
associated with

of check and
CHECKS AND ADJUSTMENTS consists
preventive and
during
performed
procedures

equipment.

adjustment
corrective

maintenance.

DIAGRAMS AND MULS contains block
layouts, and module utilization
KL10-based

diagrams, power supply
1lists associated with

systems.

MULTI-CPU contains maintenance and diagnostic information

DECnet-10/20

specific

information.

multiprocessor

contains

systems.

system

hardware

and

software

The information in each hardware section is arranged according
unit and subsystem (i.e., CPU, memory, disk, tape, and I/0).

Volume

with

contains

the

separate
1.

additional

KL10.

tables

The
of

hardware

volume

contents

formats,

diagnostics,

and

NETWORK

INTERCONNECT

provides

module

formats,
HSC

locations,

diagnostics,

SUBSYSTEM

label

and

information

tabbed

sections

consists

CLUSTER

switch

TROUBLESHOOTING

isolation

the

presents

routines,

error

S/X

BUS

contains

RA81,
,

information.

ARM-10LS

provides

fault

isolation

SOFTWARE

KLDCP,

D20MON

programs.

SYSTEM

SOFTWARE
and

presents
in

TOPS-20
and

NOTES

consists

and

RP20

fault

FSC,

jumper,

installation,

operation,

and

information

MEMCON,

and

memory

TRACON,

DIAMON,

DDT,

message

information

typical

operating

formats.

programs

stop/error

information

PIP

contains

provides

for

information.

description,

information

supplies

error

Error

’

addition

and

HSC50

includes

RSX~-20F

TOPS-10

other

KLDCPU,

command

PARSER,

GALAXY-10,

and

procedures

1installation,

the

systems

card

information.

MAINTENANCE

DIACON,

RA60,

registers

and

genral

operation

the

bit/error

level.

RP07

stops,

setting,

information.

includes

cluster

RPO7/RP20

information.
descriptions

label

Codes.

13.

software

into

COMPUTER
INTERCONNECT contains
descriptions of
the
card
cage,
module
locations,
switch
settings,
bit/error

cage,

12.

and

divided
follows.

SYSLIB-20F

and

codes.

TOPS-10,

DECnet-10,

programs.

system

program,

command

summary/format,

information.

blank

pages

for

note

taking.

COMPUTER

INTERCONNECT

-1~

Table

Contents

Page

CI120

CARD

CAGE

Rear

Panel

On.otooo'o-lonoo-tooooto

oooo.0.00.'.0-'0000-.0-0

Connectors

Internal SlOt ASSlgnments....OCO‘O......l‘l...O.O.'Qb......4
MODULE

LOCATIONS

(Refer

RH/DTE/CI/NI
MBox/EBox
GENERAL

POWER

Volume

DIAGRAMS

MULS)

0.0...00.000-05

to".ooot.ootl.oo..0'00..

.000.0.Qouotn.ooououoo

o..ocob.ot'..o"ou.o.oo.n

oonooooo.lcoo.tc.no.o.a.

SUPPLY

SPECIFICATIONS

KLlO I/O DC Power DlstrlbUtlon.C..l....'....."..OQ.I....O‘ 7
Link/Front

Voltage

0.0...COCl..".ll...“.'.....'..'..

End

Monitor

Module

Board

0o
oo

L0100

SWITCH SETTINGS...'..

CONTROL AND STATUS REGISTER..I...l.‘........'........O.'...I....9
Bit

Map/Definitions

0000000.0000000ocoo.ooolo'..uouui

cco.oo.lo

PORT

CONTROL

Format

BLOCK
o

Error Word Format s/Definitions

STATUS

PORT

READ

COMMAND

COUNTERS

CRAM

0600000090

PARITY

Hardware
EXCLUDING

CI20

o..ooo.n.

006

5000000080000

LABELS

0000000

5055000200900

000000002
00 00000800
0080

560040

FORMAT'

0000

START-UP

seees 17
a0

6000008000s0s0000e0

ceeee

0!"00.!00.0......0!00..li.’()
A

0000e68000e08

000000000
seeen
00

SPECIFICATION

Chart

cieed

0000060000060

PROCEDURE'

ERROR

Error
AT

FORMAT

COMMAND

DESKEWING/ADJUSTMENT

coo.o.oo.Qn'n---'--o-coo

PERFORMANCE'MONITORING'

COUNTERS

DIAGNOSTICS..

CI20

FIELD

SET

CI20

T T
¥

G
)

COMPUTER INTERCONNECT
-0=

DOCUMENTATION

Refer to the CI20 Reference Manual (Document No. EK-0CT20-TM) for
functional/logic/installation descriptions.

The Print Set can be ordered as follows:
Order No.

Print Set

MP01903
MP01906-01
MP01909-01

CI20-A
CI20-B
CI20-C

(KL10O-E)
(KL10-D)
(KL10-R)

COMPUTER

Cl CARD CAGE

INTERCONNECT

REAR VIEW
TOP

REAR PANEL CONNECTORS

DC POWER +5.0 VOLTS, GND

DC POWER —5.2 VOLTS, GND

PLI

’J 8

g'l

FOR NIA USE ONLY

VOLTAGE MONITOR FOR +5.0 VOLTS

VANE SWITCH

TRANSMIT PATH B

TRANSMIT PATH A

RECEIVE PATH B

000

CARD CAGE:

FAN AC

VANE SWITCH

RA RB [_ _]JTA

FAN SUBASSEMBLY:

BOTTOM
MR-14240

COMPUTER INTERCONNECT
-4-

INTERNAL SLOT ASSIGNMENTS

TOP
MUL DECAL

(LOCATED ON SIDE DOOR)
MODULE

LOCATION

L0109
L0100

LEFT
RIGHT

)

¥ | Y
&)

g | £

’

(@)]
-]

-]
)

o | o
—

—

Cl CARD CAGE

(OPENED FRONT DOOR VIEW)
MR-14264

COMPUTER

INTERCONNECT

-5~

MODULE

LOCATIONS

RH/DTE/CI/NIA

The

following

Slot

modules

M3001

M3002

PORT

M3003

CBUS/PLI

16}

171}

located

follows:

EBUS

INTERFACE/PORT ALU
MICROPROCESSOR CONTROL
INTERFACE

BLANK MODULE ASSEMBLY

18}
Refer

are

Module

'
to

Volume

DIAGRAMS

MULS

MBOX/EBOX
Slot

Module

M8532-YA

BOARD

PIC

for

all

other

slot

assignments.

COMPUTER INTERCONNECT
—-6-

GENERAL POWER SUPPLY SPECIFICATIONS

The

following

voltage

backplane of the option.

POWER SUPPLY
TYPE

OouUTPUT

measurements

are

TOLERANCE
MINIMUM
MAXIMUM
VARIABLE

702

made

MAXIMUM RIPPLE
IN MILLIVOLTS

600

703

+10

+11.0

#9.4

+1.8
-3.0

+1.9
-3.15

+1.7
=-2.85

705

+10

+11.0

+9.4

706

+50

+54.0

+49.0

1500

723

+9.5

+7.8

600

-15

-18,0

-=14.7

900

+10

+11.0

+9.5

700

VARIABLE

600

725
728

-16.5

-15

-16.0

732

739

+53

+65

+55

+65

+30

-14.5

+52

300

N/A
N/A

300
700

700

250

+63

250

+20

-15

-16.5

+3.5

+2.5

N/A
N/A
N/A

744/7440

+5.05

+4.95

150

745

-15

-15.05 ~-14.95

754

+20

+20.2

761

-2
-5.2

NONE

770

+15

+15.05 +14.95

778

-15

-16.5

-14.5

700

7131/7131A

+5.07

+4.93

742/7420

+25 V

-5

+12
-2

-5.2

-5.05

-=13.5

+19.8

-4.95

450

450
150

NONE

+12.18 +11.82
-1.97
-2.03

-5.28

-5.12

from

450

100

50
50

the

KL10 I/O DC POWER (DISTRIBUTION)
Cl

CARD
CAGE
HINGE

NIA20

H744/H7440

CARD
CAGE

+5H

PT20U

203 PT21-U

5 [JpPr21-L

J1 3] pPT22U

H744

SND j1 a P pr22L
w5

+5 K

J15 gPT23-L
J1 3 [

PT24V

J12GND
.

+5 L

H770

PT11-U

3P PT12U

5 I PT6L

30 PmU

.
PT5-L

J14

415

+15IN

'136ND

I
41

TABS OF

KPLANE
CPU BACKPL

H744

kw2o

JPT3U

FmT

T =" 1

I
{

I
(

| b=—m =——|

5
4 [)——
=

1/0 HARNESS

2FeTay

5 JPTI-L

s|3lslsl

| o

+HF) +1+

2PpPr7u

3fer20

PT2-L

1 spPmL

w 8 - Q
EY B EY

onp V1 3PP U
J1

4 : PT8-L

3] PT5-U

PT6-U

GND 1 s[5 PT6L

pPrisu

J1 2PPTIU

GND

5B
H744

“ovp st

PTI5-U

GND 1 afgPTI6L

(701087

+5 A

H744

5 3 PT15-L
3

-15

2 O PTI3U

4 :] PT14-L

~{ H745

n 3[pT14U
1

VOLTAGE

MONITORS
N

T N1
J1

5 spemiaL

GND 1

—

APT11

F————— =

J1 3 ==
GND

1 2PPT6U | 16 p0weR

5 Y

+5 E
H744

GND J1

2 [JPT23U

GND 11 4 [ Pr2aL

5 3 PT
3 |QPT

H744

H7420 NO. 3

’

J1 aperi2L

H744

CT2

abpT

anp ¥

213 PT19.U

GND'y1 4 B prao

CT1

H744

J1
GND Y1

3R PTI1BU

J4-2

J1 1 CROBAR

H744/H7440

Nns g PT19-L
J1

H744

SENSORS AND

23er

2PpTi7U
s Ppr17-L

J1 4pT18-L
5

H744

91
J1

Gnp V1

H744

J6-3

H7420 NO. 2

5 F

TO CPU

CONTROL TABS

51 4PT5L

- Y

)

NLL(T[F]

VIEWED FROM BACK OF

CABINET DOOR OPEN
MR-14239

LOUNNODHILNI ¥ILNIWOD

H7420 NO.
1

BACK DOOR

TO AIR FLOW

TO H761 IN

CPU CABINET

COMPUTER INTERCONNECT
-8

SWITCH

SETTINGS

L0100

LINK/FRONT

END MODULE

0=0FF (CLOSED)
1=0ON (OPEN)

sS4

|92]
~l

0
1
0

0
0
1

0
0
0

0
1
0
1
0

0
0
1
1
0

1
1.
1
1
0

0
0
0
0
1

0
0
0
0
0

OO0 ODDODDODOODOOODODOO0O

COCO0O0O0O0O0OCOOOOOOOOO

1
1
1
1
1
1

0
0
0
1
1
1

0
1
1
0
0
1

1
0
1
0
1
0

9
10
11
12
13
14

4
5
6
7
8

0
0
0
0
0
0

DC VOLTAGE MONITOR BOARD 5414506-01
Switch

All

other

should

switches

on.

should

off.

0
1
2

Switch Setting

cleoReoloNoNololololololeNeNe
ol

Node

Control and Status Register (CSR)

00 01

Bit Map

02 03 04 05 06 07 08
)

10 11
|

12 13

20 21

22 23 24 25

27 28 29

32 33 34 35

IDLE

ERROR

LooP

OR DEP

PORT

CLEAR

DIAG

ID CODE

PORT

SEL

PARITY

LAR

ERR

DMS

'RQST

RQST

INTER

CSR

DISABLE

COMPLETE

‘

PORT

CRAM

ENABLE

PARITY

CHNG

COMPLETE

ERROR

CMD

DISABLE

DIAG
TEST

DIAG
SINGLE

FREE
QUEUE

EBUF

RSP
QUEUE

cYe

ERR

AVAIL

PIA

QUEUE

“AVAIL

CODE
01

DIAG

CSR

EBUS

ENABLE

PIA
01

PORT

'DIAG

SPARE

DATA

MPROC

PIA

RUN

GEN

CODE

PATH

EBUS

ERR

|
MR-14237

Y¥ILNAWOOD

MBUS

EXAM

LOINNOOHILNI

RQST

PRESENT

-6-

PORT

COMPUTER INTERCONNECT
-10-

-3

BIT

DEFINITIONS

DEFINITION

NAME

(=]

—

CSR

PORT

PRESENT

DIAG

RQST

CSR.

the

This diagnostic bit indicates that the
contents of the CSR have changed since

CHNG

CSR

bit
diagnostic
port has requested

this
set,
When
indicates that the

CSR

access
DIAG

Indicates to the KL10 that the port
present (installed and powered-up).

the

port

the

port

read

last

was

micrporocessor.
UNUSED

Not

used

DEP

RQST

EXAM

Used

RQST

INTERRUPT

CRAM

PAR

either

microprocessor

the

KL1O.

microprocessor

the

port

the

interrupt

the

port

request an EBus interrupt on PI level
00 (Examine or Deposit function). The
immediately
bit
this
of
setting

generates

Used

request.

microprocessor

request an EBus interrupt on PI levels
01 through 07. The setting of this bit
immediately generates the interrupt
request.

ERR

(CRAM)
control RAM
If
been detected.

Indicates that a
parity error has

the

set,

bit

this

port

microprocessor will be immediately
halted and RQST INTERRUPT (CSR bit 05)
will be set. A hardware nonvectored
(40 + 2n)

interrupt will be

forced.

A CRAM PAR ERR may be forced in order
to halt the port
specific location

MBUS

ERR

cannot be
until this

The port
restarted

microprocessor
(CSR bit 32 set)

Indicates
driver has

that more than one MBUS
been turned on at the same

bit

microprocessor
(break point).

cleared.

time. That is, more than one set of
port logic is trying to drive the MBUS
at

the

same

time.

port
the
set,
is
bit
this
I1f
microprocessor will be immediately
halted and RQST INTERRUPT (CSR bit 05)
will be set. A hardware nonvectored
(40 + 2n) interrupt will be forced.

The port
restarted
bit

microprocessor
(CSR bit 32 set)

cannot be
until this

cleared.

UNUSED

Neither the port microprocessor or the

UNUSED

_Neither the port microprocessor or the

UNUSED

Neither the port microprocessor or the

IDLE

DISABLE

KL10

LOOP

use

this bit.

use this bit.

use

bit.

this

Indicates that the port microprocessor

is in the Idle Loop, and is not "hung"
in some other microcode

COMPLETE

Informs

microprocessor
the

ENABLE

COMPLETE

Informs

UNUSED

the

ENABLED

KL10

has

routine.

that

the

port

that

the

port

placed

itself

state.

DISABLED

microprocessor
the

the

KL10

has

placed

itself

state.

Neither the port microprocessor or the
KL10 use

this bit.

COMPUTER

INTERCONNECT

-11~-

CSR

BIT

DEFINITIONS

(Cont)

PORT

CODE

DEFINITION

Three-bit

PORT

IDENT

PORT

CODE

Informs

software

PORT

CODE

port

not

RH20

the

KL10,

Hardwired

CLEAR

that

CODE

this

field.

a CI20

controller.

that:
00

and

PORT

When

set

the

port.

and

all

The

this

control

bit

resets

halted

microprocessor

pertinent

registers

logic

are

clears

itself

placed

and

reset

after

the

reset

enables

the

KL10

state,

The

bit

function
DIAG

TEST

EBUF

This

completed.

diagnostic

bit

do
an
EBus
interface
loopback
function
by
loading
and
reading
the
EBus buffer
(EBUF).
If the port is not

DIAG

GEN

EBUS

running
(CSR bit
bit is set, then

32 is reset)
a KL10:

DATAO

loads

data

DATAI

places

This
to

DIAG

SEL

the

error.

When

ERR

(CSR

the

same

this

DIAG

SINGLE

CYC

will
error.

bit

read

(LAR).

and

DATAI

will

the

asserted

diagnostic

microprocessor
this

bit

MPROC

RUN

(CSR

microcycle
cleared

The

current

fetched

(RAR).

stored
the

cycle.

the

set

and

then

the

content:s

enables
the
port
single cycled. If

the

KL10

sets

the

port

eXecute

MPROC

RAM

RUN

LAR

be
to

the

The

KL10

the

Latch

and

executing

load
the

one

will

halts.

executed

Address

address

from

(LAR)

before

bit

microprocessor

the

KL10

Address

32),

microcycle.

address

address,

bit

halt.

CRAM

will

the

was

and

address

from

The

of
the

and

when

set

D01-D12.

microprocessor

LAR

bit

to
set

PAR

there

reset,

the

EBus

EBUS

Latah

this

are

cause

KL10

parity

enables

the

bits

This

also

assuming

the

EBus
set,

CONO,

EBUF.

checker

an
is

this

EBus.

enables

bit

24)

the
the

parity

contained

bit

decode

diagnostic

DATAI

into

data

EBus

bit

EBus

This

LAR

EBUF

diagnostic

test

forcing

real

EBus

and

executed

completion
must read
Address

into

the

single

COMPUTER INTERCONNECT
] 2=

(Cont)

CSR BIT DEFINITIONS

DEFINITION

Reserved

EBUS PARITY ERR

When

future software use.

for

KL10,

the

read

and

CRAM

this

bit

(CSR

bit

the

Port

indicated that an EBus parity error
has been detected. When written as a
"1" by the KL10, this bit will clear

itself

ERR

PARITY

.
06)

FREE

QUEUE

ERR

Used by the
Driver that

entries
Datagram
Free
26

DATA

PATH

CMD

QUEUE

ERR

AVAIL

Queue.

the

Informs

Used
port

UNUSED

Not

used

empty

DISABLE

Used
port

the

Port Driver
itself in

(set CSR bit

Used
port

KLI1O.

place

state

the

tell the
DISABLED

tell

12).

Port Driver
place itself in

the

(set CSR bit

port

the

either

microprocessor

RUN

the
command

previously

inform the Port
Used by the port to
Driver that it has placed an entry on
Queue.
Response
empty
the previously

MPROC

port

error

queue.

RESP

ENABLE

entry

the

inform

the Port Driver to
placed
has
it
that

that

command
AVAIL

Driver

Port

detected
has
microprocessor
in the DMA data path.

gqueue

QUEUE

inform

port

there are no free queue
the
either
on
available
the Message
oOr
Queue
Free

the

the
ENABLED

13).

When set by the KL10, this bit causes
the CRAM Control Register to reset and
enables

the

port

microprocessor

clocks. The port will start cycling at
RAM
the
in
contained
address
the
Address Register (RAR). The next and
subsequent addresses will be fetched
from

PIAOOQ

PIAO]

PIAQ?2

the Am2910

sequencer.

Three-bit KL10 EBus Physical Interrupt
Assignment (PIA) field (PI level 01 35
through 07).

COMPUTER

INTERCONNECT

-13-

WN
O~

COMMAND QUEUE 3 INTERLOCK

COMMAND QUEUE 3 BLINK
COMMAND QUEUE 2 INTERLOCK

N0 OTh

W W WWWwoWwowWwowwNRNNNONNNRNONNNRBDEN
S 5 9 3
s o3 o

MESSAGE FREE QUEUE ENTRY LENGTH
DATAGRAM FREE QUEUE ENTRY LENGTH

WN=0©®© 0N PWN=00OONO®ADWN
= O © 0O N

PORT CONTROL BLOCK
BUFFER DESCRIPTOR TABLE STARTING ADDRESS

RESERVED

COMMAND QUEUE 3 FLINK

COMMAND QUEUE 2 FLINK

COMMAND QUEUE 2 BLINK
COMMAND QUEUE 1

INTERLOCK

COMMAND QUEUE 1 FLINK
COMMAND QUEUE 1

BLINK

COMMAND QUEUE O INTERLOCK

COMMAND QUEUE O FLINK

COMMAND QUEUE O BLINK
RESPONSE QUEUE INTERLOCK
RESPONSE QUEUE FLINK

RESPONSE QUEUE BLINK
MESSAGE FREE QUEUE INTERLOCK

MESSAGE FREE QUEUE FLINK
MESSAGE FREE QUEUE BLINK
DATAGRAM FREE QUEUE INTERLOCK
DATAGRAM FREE QUEUE FLINK
DATAGRAM FREE QUEUE BLINK

RESERVED
RESERVED
RESERVED

RESERVED
PORT ERROR WORD O
PORT ERROR WORD
1

PORT ERROR WORD 2

PORT ERROR WORD 3

PORT ERROR WORD
4
PCB BASE ADDRESS

... PILEVEL

CHANNEL LOGOUT WORD 1 ADDRESS

CHANNEL COMMAND WORD

RESERVED TO PORT
MR-14247

"COMPUTER INTERCONNECT
-14-

Port

Block

Control

Content

Description

Word

Buffer descriptor table (BDT) starting address: The KL10
physical memory address of the first word of the buffer

~descriptors. Buffer descriptors contain the information
needed to tell the port where and how to access a data
buffer in KL10 memory.

Message free -queue entry length: The maximum number of
words allowed in an entry on a message free queue. This

Datagram free queue'entry length: The maximum number of

is a software

restriction.

words allowed in an entry on a datagram free queue.
Reserved

Queue Interlock words, FLINKs, and BLINKs.

4-24
25-28

= Reserved

29-33

Port error words 0, 1, 2, 3, and 4. The port writes the
error words when it encounters a fatal error, writing as
much information as possible directly into KL10 memory.

The KL10 physical memory address of

PCB'base address:

The priority interrupt (PI) level assigned to the CI20

Channel logout word 1 address

Channel command word (CCW): The port writes a CCW-style

PCB word 0. The CI20 has no other way to find the PCB.

word in this location in order to transfer data over the
KL10 CBus. The port driver software writes a channel
jump word in the EPT location corresponding to the RH20
position that the CI20 occupies.

Reserved to the port microcode.

Error Words 0,1 (words 29,30) are written by the port
when it encounters fatal errors associated with queue

manipulation. This error reporting strategy requires the
port to write as much information as possible directly
into the host memory. This approach requires the
smallest subset of port hardware and microcode to be
working

errors.

these

report

The information in these words provides sufficient data for the

port driver to determine the type of error and where the error
occurred. When the error is detected, the port writes the contents

the

generate

error

words

the

host

interrupt.

in the

following

enters

PCB,

the disabled

state,

and

The format of error word 0 is shown in the following figure and

described

(

]

| 08

MBZ
|

)

RSP | DFQ |MFQ | D__L

Q
|

CMD

(

table.

12
T

I E—

FLINK ADDRESS

L1 (¢

)]

]

|
MR-14452

COMPUTER

INTERCONNECT

-15=—

Bit
Error
BITS

NAME

CMD

Map,

Word

Error

Bit

Word

Descriptions

DESCRIPTION

Error

occurred

queue

while

touching

The

queue

with

queue

that

had

the

error.

These

the

CMD

bit

on.

entry.

the

command

error

QUEUE.,

1-2

QUEUE

The

command

bits

are

valid

only
0

CMD

QUEUE

CMD

QUEUE

CMD

QUEUE

CMD

QUEUE

RSP

Bit is on if error occurred while port was
attempting to build a response queue entry.

DFQ

Bit

touching

error

occurred

command

while

the

port

was

datagram

free

queue.,

MFQ

Bit

touching

error

occurred

command

while

the

port

was

message

free

queue,

D L

Bit

command

linking
error

command

7-11

MB?Z

12-35

FLINK

ADR

Error

word

port

processor

occurred.

(word

This

appeared

following

fiqgure.

the

ADDR

from

bits

0,4,

Bits

will

question.

the

contains
to

the

access

written

EBUS.

The

format

valid

only

word

the

queue

function

word

that

the

memory

corror

the

same

format

this

word

given

the

)

]

(

]

Bit

]

l
12

was

off

when

port
is

delinking

)

API

FUNC

Bit

was

FLINK

memory

here

while

queue.
port

=zero.

entry

CODE

and

queue.

Address

occurred

while

with

30)

used

word

error

occurred

]

(

)

(

PHYSICAL ADDRESS

]

MR-14257

Error
or

word

receiver

given

the

(word

31)’contains

spurious

attention.

following

figure.

the

The

format

data
of

error

transmitter
word

INTERCONNECT

COMPUTER

-16-

27 28
ZERO

35
DATA

MR-14252-

Error word 3 (word 32) contains the channel logout word 1 written

by the port on any kind of channel error detected during or
immediatly after a DMA transfer. The format of error word 3 is
given in the following figure and described in the following
table,

MEM

]

(

LONG [SHORT| OVER [COMMAND LIST POINTER

LXE

—W

wWC

|[(ADR OF CURRENT CCW+1)

RUN

]

)
MR-14253

Description

Bits

Name

MEM PE

Memory parity error

-ADR

Not

-WC=0

NXM

Channel

LXE

Error

detected

LONG WC

Port

completed

SHORT WC

OVER RUN

address

parity

error

Channel word count did not = 0 when channel
did

store

channel

CCW

not

Channel
but

EPT

reference did not exist
aborts

port

transfer

transfer,

in memory

term

transfer,

but word

count

specified

reached

data

transferred

port

still

read,

If device

buffers

after

were

has

CCW,

data

port

sent data but channel

full

"1f device write, port
buffers were empty

reqg

channel

data but

Error word 4 (word 33) contains channel logout word 2 written by
the port on any kind of channel error detected during or

immediately

after

given

following

the

DMA

transfer.

format

|
I
|
l
CURRENT WORD COUNT

The

|
|
OPCODE

]

)

(

error

word

|is

(

figure.

)

]

14
I
V1
CURRENT DATA
BUFFER ADDRESS

£ (

MR-14254

INTERCONNECT

COMPUTER
-17-~

STATUS FIELD

The STATUS field
queue

entry.

The

updated by the

various

valid

port when

values

defined below. Note that bit 0 of
definition of the remaining bits.

lcLos

the

it builds a
the

STATUS

field

response

field. are

defines

the

PATH A

PATH B

ACK l NAK |NRSP

ACK | NAK lNRSP
MR-14259

BIT

NAME

DESCRIPTION

CLOS

A packet had a

transmitted
path

indicated

path

retry failure on a path but was

successfully

The

that
also

failed
in

the

marked

the

and

the

type

Path

bits.

being

other
of

The

bad

path.

failure

indicated

the

VvCDT

this

(Virtual Circuit Descriptor Table).
2

PATH A ACK

PATH A NAK
\

PATH A NRSP

The packet was ACKed on this path.

The

packet

was

NAKed

least

The packet received No ReSPonse at least once
on this path,

PATH B ACK

PATH B NAK

PATH B NRSP

The packet was ACKed on this path.
= The

packet

was

path.
7

once

path.

The

NAKed

least

packet received No ReSPonse

on this path.

once

this

.
at

least once

COMPUTER INTERCONNECT
_18-

00
1

ERROR TYPE
|
|

|
MR-14258

NAME

DESCRIPTION

PTH A

The error is associated with path A.

B
PTH

The error is associated with path B.

ERROR TYPE

NO PATH ERRORS

(402)

(404)

(406)

FRROR = 1 => Access Control violation.
ERROR = 2 => Invalid Buffer Name.

ERROR = 3 => Buffer Length violation.

(410)

ERROR = 4 => pPacket size violation.

(420)
(422)

ERROR = 10 => Invalid Remote port.
ERROR = 11 => CRC error reported on

(424)

ERROR = 12 => No legal path.

(430)

ERROR = 14 =>

(434)
(436)

ERROR = 16 => PLI data PE in body.
ERROR = 17 => Port disabled

(414)
(416)

ERROR = 6§ => Local unrecognized command.
FRROR = 7 => Internal port hardware error.

received packet.

(426)

ERROR = 13 => Command not legal in disabled
state,

(432)

ERROR = 15 =>

PLI data PE in SRC byte.
PLI data PE in OPC byte.

during

processing.

Path Errors B

(502)
(504)
(506)
(510)

(512)

ERROR =
ERROR =
ERROR =
ERROR =

41
42
43
44

=> Remote unrecognized command
=> Virtual Cicuit closed
=> Retries Exhausted (NAK)
=> Retries Exhausted (NRSP)

FRROR = 45 => Transmitter Timeout

COMPUTER
..19-

PATH

Errors

ERROR = 101 => Remote unrecognized command
ERROR = 102 => Virtual Cicuit closed
ERROR = 103 => Retries Exhausted (NAK)
ERROR = 104 => Retries Exhausted

(NRSP)

ERROR = 105 => Transmitter Timeout
PATHS A,B Errors

ERROR = 142 => Virtual Cicuit closed
1]

ERROR = 143 => Retries Exhausted

(NAK)

ERROR = 144 => Retries Exhausted (NRSP)
ERROR = 145 => Transmitter Timeout

INTERCONNECT

COMPUTER INTERCONNECT
-20-

PORT PERFORMANCE MONITORING

the

The port microcode implements several counters which are under
control of the port driver. The command queue entry Set

Counters (SETCNT) allows the port driver to point and/or clear the
counters. It also allows the port driver to enable or disable the
event counting. There is a mask that is used to control the
loading and enabling of the various event counters. For each
counter, there are 2 bits in the mask; the first bit enables the
counting of the event, and the second bit controls the clearing of
the event counter. The port driver may instruct the port to count
events for a specified port or a cumulative count for all ports.
The format of the SETCNT command is:
FLINK

BLINK

RESERVED FOR SOFTWARE

23|24 4———» 31 32 4935
1516 ¢——»
07|08 ¢——-——
00 @———»
MBZ
XCT_ID

00 -

00 €—
00 *

OPC

FLAGS

STATUS

XCT__ID

MASK

MBZ

—» 31|32 @35
MBZ

31|32 #4935
—
MBZ

31|32 435
19|20 ¢————»
—»

THRESH
MBZ
31| 324 ®35
—» 23|24 4——»

PORT

MBZ
RESERVED
FOR
SOFTWARE

MBZ

6
7

QUEUE
LENGTH
-1

MR-14249

COMPUTER

INTERCONNECT

-21-

WORD:BITS

NAME

DESCRIPTIO]

3:16-23

OPCODE

OPCODE = 201 octal

6:0-19

MASK

This
the

6:0

PTH
A ACK

If on,

count ACKs

6:1

PTH
A ACKC

If on,

clear the counter.

6:2

PTH
A NAK

If on,

count NAKs

6:3

PTH
A NAKC

If on,

clear the counter.
count NO RSPs received on Path A.

(SETCNT).

the 18 bit mask used to control
enabling
and
loading
of
the

counters,

received on Path A,

received on Path A.

6:4

PTH
A NRSP

If on,

6:5

PTH
A NRSPC

If on,

clear the counter.

6:6

PTH
B ACK

If on,

count ACKs received on Path B.

6:7

PTH
B ACKC

If on,

clear the counter.

6:8

PTH
B NAK

If on,

count NAKs received on Path B.

6:9

PTH
B NAKC

If on,

clear the counter.