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Document:	DTR01 DR01 Channel Interface Subsystem Technical Manual Oct78
Order Number:	EK-DTR01-TM
Revision:	001
Pages:	68
Original Filename:	EK-DTR01-TM-001_DTR01_DR01_Channel_Interface_Subsystem_Technical_Manual_Oct78.pdf

OCR Text

DTRO1/DRO1

Channel Interface Subsystem
Technical Manual

digital equipment corporation ® marlboro, massachusetts

EK-DTRO1-TM-001

DTRO1/DRO1
Channel Interface Subsystem
Technical Manual

digital equipment corporation ® marlboro, massachusetts

Ist Edition, October 1978

Copyright © 1978 by Digital Equipment Corporation
The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL
DEC
PDP
DECUS
UNIBUS

DECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX

VMS

11/78-38

MASSBUS
OMNIBUS
0S/8
RSTS
RSX
1IAS

CONTENTS

INTRODUCTION

1.2

GENERAL DESCRIPTION ...ttt

]

CHAPTER1

Page

cceeeees ettt eeeeteee s sesnees e s ae e s aes

Environmental Operating Spe01flcat10ns

Operational Spec1f1cat10ns

14.3
144

Mechanical SPecifiCations .............covvvieiiiiieeiee
e
e e
Electrical Specifications...

reeerrenreneaeaes

‘

14.2

14.1

CHAPTER 2

SITE PREPARATION AND PLANNING

2.1

SITE CONSIDERATIONS...........ooetoiectetnieenreeire
et e e v s sesssase s enssne eienses 2e |

USER INTERFACE CABLING.......cccitiiitiieiinierietee
e eesiresaeseeentenesese snesesnes 2-1

2.3

SYSTEM CONFIGURATION GUIDELINES .......ccoocimiiiiiiiiiieiccrere
s2-4

CHAPTER3

INSTALLATION

3.1

DTRO1 INSTALLATION PROCEDURES........ccccoviriiiviiiiieiecnee 31

3.2

RH20 CLOCK DESKEW PROCEDURE...........ccocceiiiiiiiitee et 3-1

RH20/CHANNEL CONTROL LOGICDIAGNOSTICS ........cccotiiviinnieiennnenns 3-1

USER INTERFACE CABLING......c.ce ittt
st e e e 3-2

GROUNDING ...ttt
et ecc e et e stessae s et e csse s s snbeeeas3-2

3.7

DEVICE NUMBER SELECTION

3.8

MAXIMUM TRANSFER RATE ADJUSTMENT

3-2

CHAPTER 4

OPERATION/ PROGRAMMING

4.1

DTRO1 OPERATION ......ooiiiiiiiiiitittis
et teeeee e svteetae e s et sanes sre e s eesen se s sveand4-

)

4.1.1

Single-Word Transfer —- Write........ccccccviviiiiiiiiiiiniii
e cese e 4

4.1.2

Single-Word Transfer— Read .........ccccooiviieiiiiiiiiiiiiicc
e e4

4.2.1

Commumcatlon Between the DTROI and the KLIO B C D

OF B PrOCESSOT ..ottt ettt
e e e e ee e e e seeeee s e s e e s e4-2

CONTENTS (Cont)

Page
4.2.1.1

Loading DRO1/DTRO1 External Registers.......ccccoceeetivieeeiciinennennnnnnn 4-2

42.1.2

4.2.1.3

DATAT oo oo ceeveesse e eesssesseesssesesee
s s eeseeeeeeeesrer e ...........4-3

4.2.2

Programmable Registers in DR01-CL Channel Interface Unit...........

4.2.2.1

Control and Status 1 Register (RHCS1)........ccoeeeiiveivieiiiieeens

422.2

Interface Status Register (RHIS) - REG 1 ......cvvvvvieiieviieienilineeieinn,

4223

Input Buffer Register (RHIB)-REG 2..........cccccovvvvvvvieiiriievicciveeeeeennnn
428

4.2.2.4

Attention Summary Register (RHAS)-REG4 ........ccccoeevviviviiirrrviennnns4-8

4.2.2.5

User Function and Status Register (RHFS) - REGS...........ovuvee.ee. 4-10

42.2.6

Drive Type Register (RHDT) - REG®6........cccceveeeiveviieinennnnnennen. eeeeeees 4-10

4.2.2.7

4.2.3

Output Buffer Register (RHB) - REG 7........cccoovvvviiicriiiii
e, 4-10
LinK OPeration.....c.cccceiuiieiieieeeiieiiiirieiieesceeene
e ersrseeenreeseseeseesssssnes sresesssesnens4-10

42.3.1

DRO1-C/RH20 Registers Link Configuration ..........cccccceeeervevecr
vnnee, 4-12

4.2.3.2

DRO1-C/DR11-B Registers Link Configuration.........c.ccceeeviveeeenrnnnne. 4-15

CHAPTER 5

TECHNICAL DESCRIPTION

5.1

SYSTEM DESCRIPTION ...ttt
et
e 5-1

DATA TRANSFERS ...
e
ere e aae cras sabe e e e e 5-1

5.2.1

REG 0 (RHCSI) Control and Status Register Slgnal Flow...

5.2.2

REG 1| (RHIS) Interface Status Register Signal Flow..........ccccccovviirviinvnnnnnnns 5-5

vererrerneneenannad=1

5.2.3

REG 2 (RHIB) Input Buffer Register Signal Flow ..........cccccccoeveiiiiiniiinnennnn
. 59

5.2.4

REG 4 (RHAS) Attention Summary Register Signal Flow...........c.cceceueennns 5-9

5.2.5

REG 5 (RHFS) User Function and Status Register Signal Flow......ccc.ee..05-9

52.6

REG 6 (RHDT) Drive Type Register Signal Flow...

5.2.7

REG 7(RHOB) Output Buffer Reglster Slgnal Flow

veeverennnssrennerneennee =13

cereerrnrerireneeennnne
=13

5.3
CHAPTER 6

PREVENTIVE MAINTENANCE

6.1

GENERAL. ...ttt
et etee et creree e eeseeaeeeseeeaeet e essss st bansseennsssaed6-1

6.2

HIGH PERFORMANCE CHECKOUT..........coiiiiiiirriinrine
st e
e 6-2

CHAPTER 7

SERVICE

7.1

GENERAL.. ..o

st s eser et e e ees e teaes e es sas st arens su svasanse sasssvens 7-1

7.2
APPENDIX A

DTRO01 INSTALLATION CONSIDERATION

POSTINSTALLATION CONSIDERATIONS ........ccooevivvierrecreeevrneene
e AR

CONTENTS (Cont)

APPENDIX B

LINKING PROCEDURE

B.1

B.2

DRO01/DRO1 LINKING PROCEDURE ..o B-2

APPENDIX C

USER INTERFACE SPECIFICATION

C.1
C.1.1

USER INPUT/OUTPUT SIGNALS.......cottiiiiiiiiiiiit
i
e C-1
SIZNALS LSt .. e it ieieieei e creie
e
e
er e e e e e e e vvrea C-1

C.1.2

C.1.2.1

Timing ConsidErations .........ceuueiirineeiruioniereeeeerneeraa
et eer e s rereesosne s C-1
Read Operation.......ccvueieeuiieriieeeieeieecciiesiee
e vrnne e sevesaeeesenenn sessaansnnnn s O 1

C.1.2.2

Write Operation .......cccccceeevveieneeceneciecveein
e csinesesenees s snnnesnne G-

FIGURES

Figure No.
1-1

2-1
2-2

2-3
3-1

3.2
4-1

4-2

43
4-4
4-5

4-6

4.7
4-8

49
4-10

4-11
4-12

4-13
5-1

5-2

Title

Page

Possible DTRO1 Subsystem Configurations..........ccceceeevevemeieriiiiiniiiinininieienenn 1-1
DRO1 User Interface Connector Slot View Shown from Backplane.......................2-1
Module M9760-YA
..
2-5
DTRO1 Maximum and Mmlmum Configuratlon .................................................. 2-6
Massbus Cabling.........ccoiiiiiiiiin
i
et
e et
s e s eee s aeseesaaae s 3-1
25 MHz KL10-B,C,Dor E System SCLK Setting......cccoeeerivreeeeenriiineriennianniens 3-3
Communications Between DTRO1 and KL10-B, C, D or E Processor ...................4-4
DATAO External RegisSter........cucuiviiiiiiiiiiiiiiiiiieee st
seecea e o 4-5
DATAI Bit FOIMat.....ccooiiiiiiiiiiiiiiiiccien
s v cere sressstss s s s e st sne e e s oennsnn o84-5
RHCS1 (REG 0) Bit Map......coooiiiceiiiiei
it e
et ntietnres e esass st s srb s s sesaens 4-7
RHIS (REG 1) Bit Map....ccociiiiiiiiiiiiiiiiiieiiinie
e cneeeesseeisesne sesiianesssesenes sessse e seseseces4-7

RHIB (REG 2) Bit MaD .....ooivieeirieiies
et st vesvesresesvssnssssesssseesesssssssnsnnesuones =9
RHAS (REG 4) Bit Map ....ccooiiiiiiiiiiiiiiiieeccecerienceiereeses
s sssiss s s ssn s aeanas ane sesee soes4-9

RHEFS (REG 5) Bit MAp......oiiieiiiiiiiiiiirie
eneereeeee e ssssevesseneasinsses soosanss e snesses s4-11
RHOB (REG 7) Bit Map ..ot
iiie i vinnsiesren e ssneseaesesienintesiansnsssssssnasssssanes 4-11
RHIS(REG 1) LINK A .uouiiiiiieie e
eie e reeeeestesseneseesesusssase
sesssns sanasan essaeanes 4-13
RHFS (REG 5) LInK A....oiieeeiieee
et et ectnsnneesinsesessaesssns nesss on sessnssses 4-13
RHIS(REG 1) Link B.....ccoviiiiiriiii
e
e, reereeirereeeeeeseeenrtes
e st abeeaae 4-16
RHFEFS (REG 5) LINK Bo....oooiiiviiiiiiicie
ettt e cviteees s sresvee e sbesse s sessmas s enesaasns 4-16

A Typical DTROIL SyStem....cc.uuuuiuiuiiiireiniiiiieieereneeseeeiernesisesimesseiies
e snssssessessss 5-2
Communication Between DTRO1 and KL10-B, C, D or E Processor ....................5-3

FIGURES

Figure No.

Title

Page

5-3

DTRO1 Subsystem Data Flow Block Diagram...

5-4

REG 0 (RHCSI1) Control and Status Register C1rcu1t Block Dlagram ................... 5-5

SPUORIORRRE.
"|

5-5

REG 1 (RHIS) Interface Status Register Circuit Block Diagram....

5-6

DTROI TIMING.....cieeiiiiiiieeiieee

e ierceeseeerer st ceretnesreereeeesesse srvasesessssesssssassesssnssssrsssene 5-7

vererereeneeneand=0

5-7

Data Format
..

ceerverersesreressneeennenns
=10

5-8

REG 2 (RHIB) Input Buffer Reglster C1rcu1t Block Dlagram ............................. 5-10

5-9

REG 4 (RHAS) Attention Summary-Register Circuit Block Diagram.................5-11

5-10

REG 5 (RHFS) User Function and Status Register Circuit Block Diagram......... 5-12

5-11

REG 6 (RHDT) Drive Type Register Circuit Block Diagram...........cccceeevveenen... 5-13

5-12

REG 7 (RHOB) Output Buffer Register Circuit Block Diagram ..........ccecoeuuen.... 5-13

5-13

DTRO1 Link Connectors...

Ceeresneeenaaseneeaeeeessureasseveseessnsanseererene
s d=1 4

5-14

DTROI1 Back-to-Back Slgnal Connectlons

7-1

MB8432 Buffer/Test Module Block Dlagram ......................................................... 7-1

ferereterreseresaesesnserenseeseeseserennennses
=k D

C-1

Read and Write Timing DIiagrams ...........ccccccceevieiiiiiiiniiniiiieieiieieeee
e s vessnnen seenees C-4

TABLES

Table No.

Title

Page

1-1

Electrical SpecifiCations..........cccevvieeiiiiiiieeeiirie
e
veecese e ee e veeeer s snnsnnesenees L =4

2-1

Interface Signal Pin ASSIZNMENtS.........cccviivvieeiiiiniiierineiiereeeiieeeee
srrieeeaeesvnveneseees 22

5-1

DRO1 to DRO1 Slgnal Conncctlons .................................................................... 5-16

5-2

DR11-B to DROI Signal Connections............cccceeeenvevnnrnennneeeereeesrereesreseseseseseeese
=17

6-1

Left Half Switches — Standard Definition......c.cccoouvueieeivereevreenreerencreeereeeseenees
00 0-1

6-2

Right Half Switches - Standard Definition .......... eeseenseeeeennasniesssernsareaneanesaes
ssnnen 6-2

6-3

Command Data Commands..........ccc.eceviiiriiininineiesicneeeeeesreeeesnenesescosesne
e sen 002073

C-1

USer INput SigNals........cccouiuiiiiiiiieoiieiiiticeiieesrcreeeeees
e esreeesaeneesessssesssnssssessnnsees C-2

C-2

User Qutput Signals .......covuicieeieiniiieiiecisereecciireeeeieeeeseeeseesesneeeesrenesssnsass
snsesenesss C=3

CHAPTER 1
INTRODUCTION

1.1

PURPOSE AND USE

‘

The DTROLI is a channel port system which provides a general-purpose access to the KL10-B, C, D or
E main memory unit via a user high-speed port interface.

The DTRO1 subsystem enables a user interface/device to perform high-speed block transfers to or
from the system’s main memory unit via the mass storage bus and appropriate RH20 controller.
Although the maximum subsystem rate within a block is one megabyte, the transfer rate is primarily
determined by the user interface. Therefore, an adjustment for limiting the maximum transfer rate of
the DRO1 has been provided so that it will not exceed the bandwidth of the system.

The DRO1-C and DTROI subsystems can also be used to establish a high-speed interprocessor link
between a KL10-B, C, D or E and another KL10-B, C, D or E, a PDP-11, or a PDP-11/70. (See Figure
1-1.)

INTERFACE
INTERFACE

KL10

~ USER DEVICE
UNIBUS

DR11B | “ppp.11

INTERFACE

DR70A | 11/70

'
INTEAFACE

DTRO1 |~ KL10

8 INTERFACES
MAXIMUM

MR-1785

Figure 1-1

Possible DTRO1 Subsystem Configurations

1-1

1.2
GENERAL DESCRIPTION
Communication and control between the DTRO1 subsystem and the host processor is implemented
with seven programmable registers located in each DRO1-CL. Communication and control of the user
interface/device is implemented via 8 status bits, 8 user function bits, 4 attention bits, and 1 user error
bit along with 18 separate data in and out lines plus optional parity.

13
FEATURES AND CAPABILITIES
The DTRO1 provides the following features.
¢ Performs high-speed block transfers (block can be any size to the maximum amount of core in

the system) between main memory and user devices.
¢ Provides a high-speed channel interface with access to KL10-B, C, D or E main memory unit.

e Establishes high-speed interprocessor links between separate computer systems as follows.
KL10-B, C, D or E to KL10-B, C, D or E

KL10-B, C, D or E to Unibus PDP-11 system

KL10-B, C, D or E to PDP-11/70 system
¢ Currently provides an interface from any user device interfaced through a direct memory access device interface (DR11-B) to a PDP-11 Unibus.

* Provides an interface expanded beyond a PDP-11 Unibus direct memory access interface
(DR11-B) with the following additional features.
Enables data input and output as either word or byte (switch selectable). Byte data is in the
low order bits on 8 lines.
Provides optional parity checking for data transferred with the user device.
Provides for additional user-defined status and function bits.
* A maximum of 8 channel interfaces are available to user devices or computers.*

The user interface connects to dedicated slots in the DRO1-CL interface unit. The user device currently
interfaced through the DR11-B to the Unibus can be connected to the DTROI subsystem with a
minimum of changes, since the physical signal pins out of these connector slots are almost identical.
In addition to the standard interface connector, a second expanded interface connector slot is provided
in the DRO1-CL unit to increase the flexibility of the user interface.

*For link configurations, DR11-Bs or DR70As are not supplied. They are mounted externallyin a PDP-11 cabmet or

mounting box, not a part of the DTROI1 system.

1.4

SPECIFICATIONS

1.4.1

Mechanical Specifications

There are three configurations of DTRO1 Channel Interface Subsystems and two configurations of
DROI Channel Interfaces available. They are as follows. -

'DTRO1-AA/AB
- Description

H9502 cabinet containing power control, DRO1 mounting box
and DRO1-CL logic plus RH20 option set. Contains space for
two additional DRO1-CL options and cabinet space for two additional DROl mounting boxes (either DTRO1-CC/CD or
DRO1-CA/CB).*

Prerequisitet

KL10-B,C, D or E

Dimensions
'

152 cm X 76 cm X 66 cm
(60 in X 30 in X 26 in)

Weight

204 kg (450 Ib)

DTRO01-CA/CB

Description

H950 cabinet containing power control, DRO1 mounting box,

and DROI-CL logic plus RH20 option set. Contains space for
two additional DRO1-CL options and cabinet space for two additional mounting boxes (either DTRO1-CC/CD or DROI1CA/CB).*

Prerequisitet

KL10-B, C,

Dor E

Dimensions

175 cm X 48 cm X 68 cm
(69 in X 19 in X 27 in)

Weight

159 kg (350 Ib)

DTRO1-CC/CD (Second System Box)

Description

Mounting box containing DRO1-CL logic plus RH20 option

set. Only one DTROI-CC/CD may be added to a DTROI
CA/CB, AA/AB. Contains space for two additional DRO1 CL
options.

Prerequisites?

KL10-B, C, D or

Eand DTRO1-CA/CB or AA/AB (space per-

mitting)

Dimensions

27 cm X 48 cm X 69 cm

Weight

50 kg (110 1b)

(11 in X 19'in X 27 in)

*Only one DTR01-CC/CD mouhting box may be added to a DTR01-CA/CB, AA/AB cabinet.

1System prerequisite requires the KL10-B, C, D or E CPU to be at revision level 10 or greater.
1-3

DRO01-CA/CB

Description

DRO1 mounting box containing DR0O1-CL logic with space for
two additional DRO1-CL options.

Prerequisite

DTRO1-CA/CB or AA/AB

Dimensions

27 cm X 48 cm X 69 cm
(I1'in X 19 in X 27 in)

Weight

50 kg (110 1b)

DRO01-CL

Description

Channel interface logic unit

Prerequisites

DROI1-CA/CB, or DTR01-CC/CD,
DTRO1-AA/AB (space permitting)

Dimensions

42 cm X 22 cm X 6 ¢cm
(17in
X 9in
X 3 in)

Weight

8 kg (18 1b)

DTRO1-CA/CB or

1.4.2
FElectrical Specifications
Electrical characteristics are provided in Table 1-1.

1.4.3 Operational Specifications
The following are the operational characteristics of the DTRO1.

Transfer Rate

1 megabyte/second (max.) word mode
500 kilobytes /second (max.) byte mode
(mode is switch-selectable)

Output Levels

TTL, 30 unit loads max., high = logic 1

Input Levels

TTL, 8 unit loads max., high = logic 1

User Cable or Link Cable*

9 m (30 ft) max. from user device to DTRO1 channel interface

Host Cable*

BQ06S, 30 m (100 ft) max. from RH controller to DTR subsystem

Commands

Read, Write, and Interface Clear (octal codes 71, 61, and 11
respectively only); all other codes are not valid.

*Only standard host 12 m (40 ft) and link 8 m (25 ft) cables will be supplied with the system. If special length cables are
required, they must be specified at the time the system is ordered.

Table 1-1

Configuration

Voltage

DTROI1-AA

115 Vac £10%

DTRO1-AB

240 Vac £10%

DTRO1-CA
DTRO01-CB

DTRO1-CC

Electrical Specifications

Current*

Frequency

Power

BTU

50/60 £3 Hz

400 W

1320

25A

50/60 £3 Hz

400 W

1320

115 Vac £10%
240 Vac £10%

5SA
25A

50/60 +3 Hz
50/60 £3 Hz

400 W
400 W

1320
1320

DTRO1-CD

230 Vac £10%

115 Vac £10%

50/60 £3 Hz

300 W

990

DRO1-CA
DRO1-CB

115 Vac £10%
230 Vac £10%

4A
2A

50/60 £3 Hz
50/60 +3 Hz

300 W
300 W

990
990

DRO1-CL

+5Vdc
-15 Vdc

10A
1A

65 W

215

Power Connector:

DTRO1-CA uses NEMA L5-30P
DTRO1-CB uses NEMA L6-20P
DTRO1-AA uses NEMA L5-30P
DTRO1-AB uses NEMA L6-20P

50/60 £3 Hz

300 W

990

*These current values are estimated for the basic option configurations.

1.4.4 Environmental Operating Specifications
The following are the environmental operating specifications of the DTROL1.
Temperature

10 - 40° C (50 - 104° F) max.
Temperature change rate is 10° C (18° F) max. per hour.

Humidity

10% to 90% (no condensation)

Altitude

2 km (8000 ft)

Atmosphere

Noncorrosive

Shock

10 G for 10 ms

1-5

CHAPTER 2
SITE PREPARATION AND PLANNING

2.1
SITE CONSIDERATIONS
The basic system entry level unit is the DTRO1, consisting of a DTRO1 cabinet, DRO1-CL interface

and mounting box and RH20 controller. The DTROI cabinet can be located within 30 m (100 ft) of the
RH20 connected via BCO6S cables. If space permits placing a second system box (DTR01-CC/CD) in
the DTRO1 cabinet, the DTRO1 cabinet must be located within 30 m (100 ft) of each RH20 it is
connected to via BCO6S cables.

The DRO1-CA/CB eXpander interface box is provided for additional system expansion and is
mounted in the DTROI cabinet.

The DRO1-CL is the basic channel interface composed of a logic system unit. It provides a user
interface access into the system. The DRO1-CL can be mounted in either the DTR01 or DR0O1-CA /CB
boxes. (See Paragraph 2.3 for further guidelines.) The DRO1-CL is normally located as close as possible to the user interface (9 m or 30 ft maximum cable separation).
2.2

USER INTERFACE CABLING

The user interface is generally located external to the DTRO1 cabinet and is cabled to the DRO1 with
two M9760-YA modules or other suitable terminators. A cable from the user interface is normally
attached to the two M9760-Y
A modules which mount in the two double-height connector slots. As an
alternative, if the user interface is small enough, it can be located in the same cabinet with the DRO1
and the two units may be connected directly with two BC11A cables. However, this configuration is
not generally recommended and the user interface must be powered separately. Figure 2-1 shows the
location of the two user interface connector slots in the DROI system unit.

SLOT
NUMBER

)

STANDARD INTERFACE | EXTENDED INTERFACE

M9760-YA

! . )

M5903 (MB3

M5903 (MB2)

M8432

USER INTERFACE AND TEST CONNECTORS

)

M8431-YA
CONTROL LOGIC

ZONE

M5903 (MB1)

LINK CONNECTOR 1
BC11-A
B

LINK CONNECTOR 2
BC11-A
D

F
MR-0887

Figure 2-1
DROI1 User Interface Connector Slot
View Shown From Backplane
2-1

Table 2-1 is a list of user interface signal pin assignments for each of the DRO1 connector slots.

Table 2-1

Interface Signal Pin Assignments

Signal
Source
(See Note)

Signal

Slot

Zone

Lug
Pin

TCC
TCC
TCC
TCC
TCC
TCC
TCC
TCC
TCC
TCC
TCC
TCC

DATA 0 OUTH
DATA 01 OUTH
DATA 02 OUTH
DATA03 OUTH
DATA 04OUTH
DATA 05 OUTH
DATA 06 OUT H
DATA 070OUTH
DATA 08 OUT H
DATA 09 OUTH
DATA 10OUTH
DATA 11 OUTH

D04

-S1

D04
D04
D04
D04
D04
D04
D04
D04
D04
D04
D04

R1
U2
P1
T2
NI
S2
Ml
R2
L1
P2
K1

B
B
B
B
B
B
B
B
B
B
B

R1
U2
P1
T2
N1
S2
Mi
R2
L1
P2
K1

DATA 12 OUTH
DATA 13OUTH

D04
D04

DATA 140UTH
DATA 150OUTH
DATAOO0INH
DATAOI INH

D04
D04
Q04
C04

DATAO02INH
DATAO3INH
DATA 4 INH
DATAOSINH
DATA 06 IN H
DATAO7INH
DATA O8INH
DATAO09INH
DATA 10IN H
DATA 11 INH
DATA 12INH
DATA 13INH
DATA 14IN H
DATA 15INH
CYCLE REQUEST A
CYCLE REQUEST B
DEVICE STATUS 00
DEVICE STATUS 01
DEVICE STATUS 02
DEVICE STATUS 03

C04
C04
Co4
C04
C0o4
Q04
C04
Q04
Q04
C04
Q04
C04
C04
C04
Q04
D04
C04
C04
C04
E04

DEVICE STATUS 04
DEVICE STATUS 05
DEVICE STATUS 06
DEVICE STATUS 07

E04
E04
E04
E04

N2
M2
L2
K2.
Cli
D1
D2
El
E2
Fl
F2
H1
H2
J1
J2
K1
K2
L2
M2
N2
Al
Ul
P2
L1
R2
N2
P2
R2
D2
T2

B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
A
A

N2
M2
L2
K2
Ci
D1
D2
El
E2
Fl1
F2
H1
H2
J1
n
K1
K2
L2
M2
N2
Al
Ul
P2
L1
R2
N2
P2
R2
D2
T2

TCB

FUNCTION BIT00V”

D04

TCB
TCB
TCB
TCB
TCB
TCB
TCB
DTC

FUNCTION BIT 01”
FUNCTIONBIT 02"
FUNCTION BIT 03
FUNCTION BIT 04
FUNCTION BIT 05
FUNCTION BIT 06
FUNCTION BIT 07
READY H

D04
- D04
F04
F04
F04
F04
F04
D04

J2
H1
H2
N2
K2
L2
P2
J1

B
B
B
B
B
B
B
B

J2
H1
H2
N2
K2
L2
P2
Ji

TCC
TCC
TCC
TCC
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USA
USB
USB
USB
USB
USB

|
-~

Table 2-1

Interface Signal Pin Assignments (Cont)

Signal
Source

.
Signal

Slot

Zone

Lug
Pin

FDC
TCC

GOH
READH~

D04
D04

Vi
D2

B
B

\'A!
D2

TCC

END CYCLE H

Co4

USA
DTC

ERROR H
BUSY H

C0o4
C04

M1
S2

A
A

Mi
S2

TCC
USB

INITH
ATTN BITO00H

C04
E04

U2
E2

A
A

U2
E2

USB
USB

ATTNBITO1 H
ATTN BIT02 H

E04
E04

H1
J1

A
A

H1
I

USB

ATTN BITO3 H

E04

USB
USB

DATA 16INH
DATA 17INH

E04
E04

Al
F1

A
A

Al
Fl

- USB

DPALOINH

E04

Cli

DPA HI IN H
DATA 16 OUT H
DATA 170UTH
OUT PARITY HI
OUTPARITYLO
WORD MODE H
INHIBIT INPUT PARITY H
ACLOH
+3 volts

E04
E04
F04
F04
F04
E04
E04
F04
E04

D1
Bl
H1
J1
K1
L1
El
S2
Ul

A
A
B
B
B
A
A
B
A

D1
Bl
H1
I
K1
L1
El
S2
Ul

USB
TCB
TCB
TCB
TCB
USB
USB
ISR
CPF

Reserved for Link
Do not use:

CO04R 1

NOTE
Since the DRO01 interface does not contain any type

of word counter, it must rely on the internal channel

C04V1

word count of the KL10-B, C, D or E to indicate

C04T2

transfer end. This causes some delay to exist between

DM F1

the last word transferred and the WCOYV in the inter-

DMEF2
DO04H2
EO04F2

nal channel signalling transfer end and results in one
or more additional END CYCLE pulses to the user’s
interface.

E04L2

E041.2
E04S2
E04U2

Note:

The user’s interface should be designed to prevent a
malfunction from occurring due to these additional
pulses.

Signal
Source

Drawing Referenced

TCC
USA
USB
TCB
DTC
FDC
ISR
CPF

M8432-0-1 sheet 5 of §
DRO01-0-03 sheet 1 of 2
DRO01-0-04 sheet1 of 1
M8432-0-1 sheet 4 of 5
DRO01-0-03 sheet 1 of 2 and DTRO01-0-2
DRO01-0-03 sheet 1 of 2 and DTR01-0-2
M8431-Y
A-1 sheet 8 of 11
MB8431-YA-1 sheet 4 of 11

2-3

All output signals are driven with 7437 drivers. These drivers can sink 60 mA in the output low state
and can source 1.5 mA in the output high state. This is equivalent
to a fan-out of approximately 30 unit

loads.

All input signals are received by 7414 Schmitt trigger receivers for noise immunity. The signal inputs
are terminated at the receiver input with a 180 ohm resistor to +5 V and a 390 ohm resistor to ground
on the M9760-YA module. (See Figure 2-2.) This termination requires a driver in the user interface
capable of sinking at least 25 mA. A driver such as the 7437 or 74H40 will satisfy this requirement. If
the use of lower powered drivers is desired, the terminators may be removed from the M9760-YA
module. However, it is not recommended to use lower power drivers for cable lengths greater than 1.5
m (5 ft).

2.3

SYSTEM CONFIGURATION GUIDELINES
Figure 2-3 provides a graphic description of the system’s expansion capability by providing the system
minimum and maximum configurations. The maximum configuration rules are listed below.

Eight DRO1-CLs per Massbus (RH20)

Any RH20 option set used by DRO1-CLs cannot be shared with other devices.

One Massbus per DRO1 mounting box

Two Massbuses per DTRO1 cabinet

Three DRO1-CLs per DRO1 mounting box

Three DRO1 mounting boxes per cabinet

7.
.

One additional (second) DRO1 system box per DTRO1 cabinet (DTRO1-CC/CD). If a second DRO1 system box is placed in the DTROI1 cabinet, the maximum configuration per
cabinet i1s:

Massbus no. 1 = 3 DRO1-CLs
Massbus no. 2 = 6 DR0O1-CLs.

/ ‘

M9760-YA-1

1l 2 2 2 2 2 2 2 1I 2
ZONE A

ZONE B

MR-0886

Figure 2-2

Module M9760-YA
2-3

Moommcsox 1

RH20| passaus | |

DRO1-CL

RH20 | MASSBUS

Mommvesox
)

|
|

DRO1-CL,

|
|

DRO1-CL,

DRO1-CL3

|
|
I

L NS I GERAD ShEND SR J
FGmmG
sox ]
RH20 | MASSBUS

!
I

MAXIMUM EXPANSION
FOR ONE MASSBUS IS
EIGHT DRO1-CLS ON

Il
:

DRO1-CL,4

DRO1-CLg

DRO1-ClLg

|
|

lI
b

ONE MASSBUS.

CGENED

eunanl

GEbED
G
CER

FVIOUNTING Box

DTRO1 MINIMUM CONFIGURATION

DRO1-CLy

DRO1-CLg
DRO1-CLg

|
|
I
I
:

DTRO1 MAXIMUM CONFIGURATION
MR-0888

Figure 2-3

DTRO1 Maximum and Minimum Configuration

CHAPTER 3
INSTALLATION
3.1

DTRO1 INSTALLATION PROCEDURES
Verify that the KL10-B, C, D or E CPU in the system is at revision level 10 before proceeding with the

installation. Observe the CPU revision sticker on the module enclosure door on the CPU logic.
NOTE
DO NOT proceed with the DTRO1 installation if the
KL10-B, C, D or E CPU is not at machine level 10.

Install the RH20 option module set into the next available channel backplane slot or another slot if
preferred. Refer to the RH20 Massbus Controller Unit Description (EK-RH20-UD) and/or KL10 System Installation Manual.
3.2

RH20 CLOCK DESKEW PROCEDURE

Perform the RH20 clock deskew procedure for the RH20 being installed. (Refer to the KL10 Maintenance Handbook EK-KL10-HB.)

RH20 /CHANNEL CONTROL LOGIC DIAGNOSTICS

Run the following RH20/Channel Control Logic Diagnostics. Refer to diagnostic listing fiche for
program and error information.
DGKBD.A11

Version 0.10 (or later)

DGKBE.A11
DGRHB.A10

Version 0.10 (or later)
Version 0.11 (or later)

Upon successfully running the diagnostics above, connect the DTRO1 cabinet/DRO1-C logic to the

RH20 with the supplied BO06S-XX cable. (See Figure 3-1.) Jumper W1 on each H870 (Massbus
terminal pack) must be cut for the proper operation of the DRO1. The total length of the Massbus

cable should not exceed 30 m (100 ft) with BCO6S round cable from the CPU.

DTRO1 CABINET
BCO6R

KL10

RH20

BCO6S

CONNEC-

TOR

JPANEL

BCO6R

DRO1

USER

INTERFACE

USER

LOGIC

CABLE

BCO6R

MR-0889

Figure 3-1

Massbus Cabling

3-1

3.4 USER INTERFACE CABLING
The user interface is cabled to the DRO1 with the two M9760-YA modules. A cable from the user
interface is normally attached to the two M9760-Y
A modules which mount in the two double-height
connector slots.
3.5
GROUNDING
In addition to the ground wires in the user interface cable, the DRO1 should be grounded to the user

interface through a separate cable. This ground strap provides a low resistance path to ground. Also,
the DRO1 and the Massbus controller should share a common ground. Using the supplied ground
cable, connect the DTRO1 cabinet to the host system ground.
3.6

POWER UP UNIT

Plug the unit into the appropriate ac outlet and power up the DTRO1 cabinet. Check all logic voltages.
+5V+025V
-15V£05V
3.7
DEVICE NUMBER SELECTION
Dual in-line package (DIP) switches, SW1-1, SW1-2, SW1-3 on the DROI control board (M8431-YA)

select the device number of the DRO1 on the Massbus. (See Table 2-1.) (Switch in the ON position = 0;
SW1-1is LSB; SW1-3 is MSB.) The rocker switches represent an octal number from 0to 7. The DRO1
is shipped with the switches set for unit 7. Switch SW1-7 indicates byte mode when ON and word mode
when OFF. Switch SW1-8 indicates inhibit input parity when ON and enable input parity when OFF.
3.8

MAXIMUM TRANSFER RATE ADJUSTMENT
The DROI is shipped from the factory with its maximum rate set to 3.4 us per 36-bit word. This is
equivalent to a high-speed disk such as the RS04. The maximum transfer rate may be increased or
decreased as required.

Verify that the sync clock (SCLK) timing is set up properly for the KL10-B, C, D or E version to which
it is connected. Using Test 6 of the DFDRA diagnostic and a 1-word transfer, monitor pin D02M2
with an oscilloscope on the DR0O1-CL backplane. For a 25 MHz* KL10-B, C, D or E CPU the
maximum settings are as follows.

SCLK width = 800 ns
SCLK period = 1.7 us
The SCLK width adjustment potentiometer on the M8431-YA module is R3 located front/bottom.
The SCLK period potentiometer is R6 located rear/top. Slot A of the module is at the top; Slot F is at
the bottom. It may be necessary to limit the maximum transfer rate of the DRO1 so that it does not
exceed the bandwidth of the system. On heavily loaded systems, problems such as data late errors on
other system devices or in the DR0O1 may occur during peak periods of system operation if the speed is
not limited.

If the speed must be limited, first determine the maximum transfer rate allowable.
NOTE
Determining the available bandwidth to the DRO1
can be a very complex system problem requiring a

-comprehensive knowledge of the system architecture.
If the system bandwidth is not extremely critical, an
estimate of the available bandwidth may suffice;
however, in critically loaded systems, customers
should have the system bandwidth analyzed by
DIGITAL personnel.
*For a 30 MHz KL10-B, C, D or E system the same settings are used but the period may be shortened with approval of the

factory.

3-2

When the available bandwidth has been determined, adjust the DROI as follows.
1.

Calculate the reciprocal of the bandwidth to determine the minimum period of the transfer

(for example, if the bandwidth is 500 kHz, the minimum period is 2 us).

Monitor the SCLK L signal located on the DRO1 backplane D02M2. Run the bandwidth
portion of the DRO1 diagnostic DFDRA using Test 6 and a 1-word transfer. The signal in Figure
3-2 should be observed at D02M2.

re—— MIN PERIOD ——

SCLKL

e A

DO2M2

NOMINAL

800 NS

FOR 25 MHZ KL10 SYSTEM, THE MAXIMUM SETTING IS AS FOLLOWS:
A = 800 NS

B =900 NS
PERIOD
= 1.7 uS
MR-0890

Figure 3-2

25 MHz KL10-B, C, D or E System SCLK Setting

The low portion (A) of the SCLK L signal is normally set at 800 ns. This corresponds to the
minimum setting of potentiometer R3 which is located at the bottom when DRO1 is
mounted vertically. Do not adjust R3 unless it is necessary to make the DRO1 run slower

than the adjustment allowed by potentiometer R6 described in the next step.

Potentiometer R6 controls the width of the high portion (B) of the SCLK L signal. Potentiometer R6 is at the top when DRO1 is mounted vertically. Adjust R6 so that the total width
of the low and high portions equals the desired minimum period calculated in step 1. If the
range of the R6 adjustment does not allow slowing the DRO1 enough, leave R6 at its maximum setting and increase R3 until the desired value is obtained.

M5903 ENABLE SWITCHES

Each M5903 Massbus transceiver has an enable switch that enables the receivers. The function of these
switches is not implemented on the DRO1 and the switches should always be set to the ON (up)
position.
3.10

CHECKOUT AND ACCEPTANCE

Make sure the BCO8R loopback cable is installed between J1 and J2 on the M8432 board and that the
user connector modules (M9760-YA boards) have been removed from the DROI-CL logic. Also remove any link cables (i.e., nothing in CDEF01, CDEF04). Load the DTRO1 diagnostic, DFDRA.A10
and continue with the DTRO1 subsystem checkout. Refer to the DTRO1 Checkout/Acceptance Procedure.

3-3

CHAPTER 4
OPERATION/PROGRAMMING
4.1

DTRO01 OPERATION

The user must define an operation protocol to be used in communications between the host system and
the user’s device. The user function, status, and attention bits and also possibly a fixed message size
and/or data block size to be transferred should be considered. Once a protocol is defined, the programming of the DTRO1 subsystem can be accomplished.
A data transfer can be functionally performed as follows.

4.1.1

Determine if the DRO1 interface is ready.

Load the user ffinction/ status as defined in the prbtocol.

Initialize and generate the desired channel transfer command list.

Initialize and generate the desired data buffer area.

With the user’s program, load the read or write command indirectly via RH20 STCR, REG
40 into the RH20 secondary transfer command register (RHCS1, REGO bits 00-05).

Wait for DONE (indicates transfer completed).

Check status and proceed.
Single-Word Transfer — Write

‘

To transfer a single word of data from the host to the user interface device under program control,
load the output buffer, RHOB (REG 7) with the desired data.

NOTE
This procedure assumes a single-word transfer pro-

tocol is defined so that the user interface is assured of
taking stable data (i.e., some strobe signal may be
provided via a dedicated user function bit).
4.1.2

Single-Word Transfer - Read

To transfer a single word from the user device interface to the host under program control, read the
input buffer register, RHIB (REG 2).

NOTE
This procedure assumes that the user device will supply the data word stable for the interface to read.
Caution must be taken to ensure stable data that is
not changing when the program reads it by implementing a handshake protocol possibly with dedicated user function/status bits.

4-1

42.1

PROGRAMMING

Communication Between the DTR01 and the KL10-B, C, D or E Processor (See Figure 4-1)

~ Communication and control between the DTRO1 subsystem (RH20 and DTRO1) and the KL10-B, C,
D or E processor is implemented with DATAO and DATALI instructions from the CPU. These instructions cause bits within the DRO1 external registers to be loaded or cleared. The KL10-B, C, D or E

CPU communicates with the RH20 Massbus controller via the EBus and the RH20 Massbus controller communicates with the DRO1 via the Massbus.

Data is transferred through the DROI registers to or from the RH20 Massbus controller via the MBus
data lines. Data is transferred between the RH20 and the CPU via the CBus and between the CPU and
main memory via the SBus.
A secondary method available to transfer data to and from the RH20 Massbus controller is via DRO1
external registers 23 and 7, respectively, using DATAI and DATAO instructions. (See Paragraphs
4.1.1 and 4.1.2.)
‘

42.1.1
Loading DR01/DTRO01 External Registers - The CPU issues a DATAO or DATALI instruction to read or write the designated DR01/DTRO1 registers. When using DATAO, setting bit 06, LR
= 1 writes into the DRO1 register (RS00-37g) and setting bit 06, LR = 0 loads a register address (plus

control data and a drive address if RS = 00-37g) so that a register may be read by a subsequent
DATALI Repeated DATAI commands will read the same register; that is, DATAI will always read the
register specified by the last DATAO (LR = 0 or 1).
When the RH20 detects an error caused by a nonexistent drive or control bus parity during the writing
or reading of an external register, an interrupt occurs and the program is inhibited from writing any
more registers with a DATAO unless DRAES, DATAI bit 09, was set by the DATAO that preceded
or caused the error. (A DATALI is not inhibited and it can be used to read back the failing register and
drive address.)

For a more detailed description of DATAO/DATALI instructions, refer to the RH20 Massbus Con-

troller Unit Description, EK-RH20-UD.

4.2.1.2 DATAO - The DATAO command is used to write both internal and external registers. The
bit format for the DTR01 DATAO (external registers) is shown in Figure 4-2.
The preparation register is not addressed directly. It is loaded with address and control information
(bits 00-06, 09 and 14-18) by all DATAO commands, provided there has been no previous register
access error detected (RAE, CONI bit 24 = 0) or there has been an error and it has been disabled
(DRAES, DATALI bit 09 = 1). When RAE = 1 and DRAES = 0, the preparation register is not loaded
and the DATAO command is not executed.by the RH20. The following list explains the functions of
the bits in the DATAO external register.

4-2

Bits

Description

00-05

REGISTER SELECT (RS) - Six-bit register select code. RS = 40-77g when addressing
an internal register of RH20. RS = 00-373 when addressing an external register of
DRO1.

LOAD REGISTER (LR) - When equal to 1, causes the addressed register to be writ-

ten. When equal to 0, only the preparation is loaded, thus providing a means to store
address and control information for a subsequent register read operation (DATAI).
09

15-17

DRAES - Prevents RAE (CONI bit 24) from generating an RH20 interrupt request
and from inhibiting subsequent register write operations.
DRIVE SELECT (DS) ~ Specifies the drive number (0-7g) when addressing an external
register (RS = 00-373).

CBEP - When writing an external register (RS = 00-37g, LR = 1) causes even parity to
be transmitted on the Massbus (control bus) data lines. Used by the diagnostics to
cause parity errors in a drive.

20-35

EXTERNAL REGISTER DATA - Specifies the register contents when an external
register is written.

42.1.3 DATAI - The DATAI command is used to read both internal and external registers. The
register that is read is determined by the address and control data stored in the preparation register by
a previous DATAO. Bit format for the DATAI command is shown in Figure 4-3. The following list
explains the functions of the bits in the DATAI external register.
Bits
00-05

Description

LOAD REGISTER (LR) - Indicates the state of the LR bit stored in the preparation
register. Equals 0 when the previous DATAO loaded only the preparation register.
Equals 1 when the DATAO wrote the specified register.

CONTROL BUS PAR ERR (CBPE) - Indicates that bad parity was detected on the
Massbus (control bus) data lines during the DATAI Sets RAE (CONI bit 24).

DRAES - Indicates that register access errors have been disabled. Set by DATAO bit

09 = 1.
10

TRANSFER RECEIVED (TRA) - Indicates that a drive responded (asserted transfer
on the Massbus) during the DATALI.

15-17

DRIVE SELECT (DS) - The drive select code stored in the preparation register by a
DATAO.

CONTROL BUS PARITY BIT (CPA) - Indicates the state of the parity bit received
on the Massbus (control bus).

20-35

EXTERNAL REGISTER DATA (ERD) - The contents of the register addressed by
'
the DATAL
4-3

l DTRO1

DRO1-CL

REG 0

REG 1

RHCS1

RHIS

DATA

KL10
CPU

MASSBUS

EBUS

conTroL(

(CONTROL)

) |
'l

REG2 |

RHIB

| REG4

DEVICE

RHAS
CONTROL

RH20

MASSBUS

CONTROL-

REG 5

REG 6

RHFS

RHDT

LER
REG 7

RHOB

DATAO

CBUS

DATAI

(DATA)

DATA
(PRIMARY

FLOW)

1B
I

MAIN

MEMORY

MR-1784

Figure 4-1

Communications Between DTRO1 and
KL10-B, C, D or E Processor

DATAO EXT REG
00

05 06 07 08 09 10

R
]

00-378

[

NOT

"lusep|

13 14

| NOTUSED

}

17 18 19 20

EXTERNAL REGISTER DATA =

[

}

(MASSBUS BITS C15—00)
1

]

CBEP

DRAES

NOT
USED
DRIVE SELECT

CODE
MR-1225

Figure 4-2

DATAO External Register

DATAI EXT REG

05 06 07 08 09 10 11
T

(RS) CODE

1415

17 18 19 20
)

[

IGNORE
i

| NOT

[

35
||

)

]

)

]

EXTERNAL REGISTER DATA (MASSBUS BITS C15—00)

[

}

NOT

USED

LOAD CTRL | TRA

DRIVE

CTRL BUS

REG

BUS | REC

SELECT

PARITY

(LR)

PAR

CODE

BIT

ERR

(DS)

DRAES
MR-1226

Figure 4-3

DATAI Bit Format

4.2.2 Programmable Registers in DR01-CL Channel Interface Unit
Communication and control between the DTRO1 subsystem and the host processor is implemented
with seven programmable registers located in each DRO1-CL channel interface unit. Paragraphs
4.2.2.1 through 4.2.2.7 describe the seven programmable registers and formats.
4.2.2.1

Control and Status 1 Register (RHCS1) - REG 0 - Register 0 is the control status 1 (RHCS1)

operational status. Register bits 00 through 05 and bit 11 are dedicated for use by the interface as
shown in Figure 4-4.
Register bits 00-05 indicate the command to be performed and are stored in the selected device (LSB =
bit 0).
Bits

Description

15-12

Not used

Device Ready - Always read as a 1 (DRY)

10-06

Not used

05-01

F4-F1 - Command function code; can be written at any time

Function

F4-F1 (bits 05-01) Equal

Read

708

Write

603

Interface Clear

10g

GO - The GO bit is a read/write bit that indicates interface busy. A lockout feature is
not provided if the GO bit is set. Therefore,
do not write this register during a data
transfer.
Function is GO

Bits 05-00 Equal:

Read

71g

Write

Interface Clear

4.2.2.2

613
11g

Interface Status Register (RHIS) - REG 1 - This register provides general status information

for the DRO1-CL, the user-defined error bit, and attention signals. The register format is shown in
Figure 4-5.
|
15

ATA - An attention condition sets the ATA bit and the ATA summary line. An ATA

condition is caused by the error bit (ERR) setting or the setting of any user-defined
attention or error bits. ATA is cleared by INIT, RH CONTROLLER CLEAR, loading a data transfer command with GO set, or writing the appropriate bit in the RHAS
register, REG 4. The last two methods do not clear the error condition in the device.
This is a read-only bit. ATA is set on power-up.

4-6

RHCS1

DRY

(REGO)

F4 | F3

FO | GO

ALWAYS =1

Figure 4-4

RHIS

{REG1) ATA | ERR

MR-0871

RHCS1 (REG 0) Bit Map

USER

;

ERR ICPE | IDPE | IRDY

AT3 | AT2 | AT1 | ATO

USER{ USER | USER|USER

CYCLE
MR-0872

Figure 4-5

RHIS (REG 1) Bit Map

4-7

ERR - ERR is set when one or more error conditions (USER ERR, ICPE, and IDPE)
have been set. ERR is a composite error bit (logical OR) of all error conditions in the
RHIS register. The ERR bit is cleared only by INIT, RH CONTROLLER CLEAR or
an INTERFACE CLEAR command while ERR is set. On power-up, ERR is set. This
is a read-only bit.

13-11

Not used.

USER ERR - User-defined error condition from user interface sets USER ERR.
USER ERR is cleared by writing an INTERFACE CLEAR command into RHCSI,
assuming the interface clears with INIT set. This bit may be used to terminate a data
transfer if the word count has not overflowed. Therefore, USER ERR may not indicate
an actual error condition. The user status bits may be used to provide more detail
concerning why the USER ERR is set. This bit is read-only.

ICPE - Sets ERR and indicates a parity error has occurred in transferring control data
over the control bus. This bit is read-only.

IDPE - Indicates a parity error in transferring data over the data bus during a write

device or a data parity error in data received from the user interface during a read
device, if enabled. This bit is read-only.

IRDY - Indicates that the DRO1-CL is ready to accept a new data transfer command.

IRDY is set by completion of a block data transfer or an error condition. It is cleared
by issuing a Data Transfer command with GO set. This is a read-only bit.

06-05

Not used.

CYCLE - This write-only bit is used to prime bus cycles if the user interface is not self-

starting. Writing a 1 into this bit causes CYCLE in the interface to set, initiating transfers.

03-00
:

4223

AT3-ATO - Read-only, user-defined attention bit. Sets ATA and causes an interrupt if
enabled. Cleared by removing the attention condition in the user interface.

Input Buffer Register (RHIB) - REG 2 - This register reflects the state of the DATA IN (0:15)

lines from the user interface. DATA IN 16 and 17 are not readable via RHIB. This read-only register is
shown in Figure 4-6.
15-0

DI15-DIO0 - User input data lines

4224 Attention Summary Register (RHAS) - REG 4 - This register consists of eight status bits, each
corresponding to the AT
A status bit of one drive. Bit 00 is the ATA bit of drive 0, bit 01 is the ATA bit
of drive 1, etc. to bit 07. Bits 08-15 are not used. This read /write register is shown in Figure 4-7.

The timing of transfers on the control bus to and from this register is special. When this register (REG
4) is read by the controller, each drive gates its ATA bit out onto one of the C lines (drive 00 onto C00,
etc.). Because all drives are responding at once, the normal handshake sequence is not valid. Instead,
the controller waits the maximum delay time and then unconditionally strobes the C lines. The con- troller negates DEMAND after it has strobed the C lines. No drive may disable its C line output until
it has negated transfer (typically after receiving the negation of DEMAND). When the transfer line
becomes negated at the controller (after each drive has negated TRANSFER), the controller knows
that the cycle is complete.

4-8

(::ég) D115 { D114 | b3 | o112 | b1 |pito|

pie [ pis | bi7 | pie | D15 | D14 | D13 | DI2 | DI1 | DIO
MR-0873

Figure 4-6

RHIB (REG 2) Bit Map

RHAS, REG4
15

]

}

NOT USED
[

{

DRIVE

DRIVE
1

ATA

DRIVE

ATA

DRIVE

MR-1227

Figure 4-7

RHAS (REG 4) Bit Map

Since no single drive is generating all of the C bits, it is impossible for any drive to generate a valid
parity bit. Therefore, the controller ignores the CPA line and does not check parity when reading the
attention summary register.
When this register is selected, all drives respond. When reading this register, each drive presents its
ATA bit in the appropriate bit position. When writing, each drive receives a bit from the control bus,
and if the bit is set, the drive resets its ATA bit. For each bit position and drive, Table 4-1 applies when
writing into this register.

Bit Written

ATA Before

ATA After

—_—0
= O

ATA Bit Status

— O
O

Table 4-1

0
1
0
0

This scheme allows the program to reset the ATA bits which were already seen and acted upon,
without accidentally resetting other ATA bits which may have become set in the meantime.
4.2.2.5 User Function and Status Register (RHFS) - REG 5 - This register provides eight generalpurpose status bits and eight general-purpose user function bits. Each status bit reflects the state of a
user-defined signal connected to the interface inputs (+3 V = 1, 0 V = 0). The output of the user
function bits are made available to the user interface for any user-defined function. The register format
is shown in Figure 4-8.

15-08

UF07-UFO00 - User-defined function, read/write

07-00

STO7-STOO0 - Status bit, read-only

42.26 Drive Type Register (RHDT) - REG 6 - This register is used to identify the interface types
which exist on the Massbus. For the DRO1-CL interface, this register always equals a 4 (000004 octal).

4.22.7 Output Buffer Register (RHB) — REG 7 - This write-only register provides a means of transferring a word of data to the user interface under program control. The outputs of this register appear
on the DATA OUT lines (0:15). This register may not be used while a block data transfer command is
-in progress. The register format is shown in Figure 4-9. DATA OUT 16 and 17 cannot be written via
this register (RHOB).
15-00

DO15-DO0 - Output data to user interface

4.2.3 Link Operation
In a link configuration the functional operation of the RHIS (REG 1) and RHFS (REG 5) bits differ
from the standard operation. Paragraphs 4.2.3.1 and 4.2.3.2 define the RHIS (REG 1) and RHFS
(REG 5) bits for a DTRO1 interprocessor link operation.
NOTE
Link Relationship — Side A is the nearest interface;
Side B is the farthest or other interface.

4-10

(2222) UF07 | UF06 |UFO5 |UF04 |UFO3 | UF02 | UFO1 | UF00 | STO7 | STO6 | STOS | STO4 | STO3 | STO2 | STO1 | STOO
MR-0874

Figure 4-8

15
RHOB

(REG7) DO15|D0O14|

13
D013

|D012{DO11|

RHFS (REG 5) Bit Map

DO10| DO0Y9 | DOO8 | DOO7 | DO06| DOO5 | DOO4 | DOO3 | DOO2 | DOO1

00
(DO0OO
MR-0875

Figure 4-9

RHOB (REG 7) Bit Map

4-11

4.2.3.1 DRO01-C/RH20 Registers Link Configuration* - RHCS1 (REG 0) is the same as the standard
configuration. Refer to Figure 4-10 for bit map. RHIS (REG 1) is redefined as follows.
Bits

Description

ATA - Same as for standard definition

ERR - Composite error bit — includes LINK ERROR set by the other side. This is a
read-only bit.

13-11

Not used

LINK ERR - Indicates that an error condition has been signaled from the other processor. This bit is set by the other processor writing its LKALERR bit in register 5.
LINK ERR causes an ATTENTION INTERRUPT if INTERRUPT ENABLE is set.
LINK ERR is normally used to terminate a data transfer if the word counts are not

equal.

ICPE - Same as for standard definition
08

IDPE - Same as for standard definition

IRDY - Same as for standard definition

06-05

Not used

CYCLE - Maintenance-only bit

LATAO3 - General-purpose link attention bit. This bit is set by the other processor
setting its LINK FUNCTION 02 bit. Available for system software protocol definition.

LATAO2 - General-purpose link attention bit. This bit is set by the other processor

setting its LINK FUNCTION 01 bit. Available for system software protocol definition.
|

LKMASTER - Indicates to the processor that it has received control of the link. It is

set after the other processor has released link mastership and a processor has set the
LINK REQUEST bit in register 5. LKMASTER sets ATTENTION INTERRUPT
and causes an interrupt if enabled.

LKBREQ - Indicates the state of the other processor’s link request bit. LKBREQ is set
when the other processor is requesting link mastership. LKBREQ sets ATTENTION
INTERRUPT and causes an interrupt if enabled.

RHIB - (REG 2) This is the same as the standard configuration.
RHAS - (REG 4) This is the same as the standard configuration.

RHFS - (REG 5) The format of REG 5 is shown in Figure 4-11. RHFS (REG 5) is defined as follows.
* Also applicable for DR70A

4-12

11
T

RHIS

(REG1)| ATA | ERR

09-

LINK

erp | 'CPE [ IDPE [ IRDY

LATA|

LATA

00
LKB

03 | 02

LKBLERR

CYCLE

(LKALERR)

REQ

LKBLFO1 | LKBREQ

(MAINONLY)

LKBLF02

LK
MASTER

LKAREQ

(WHEN
MASTER)
MR-0882

Figure 4-10

RHIS (REG 1) Link A

RHFS | LAF | LAF | LAF | LAF | LAF | LAF | LAF | LAF | LAS | LAS | LAS | LAS | LAS | LAS | LAS | LAS

(REG5)|{

LKALFO7

LKALFO5

LKALFO06

LKALERR

LKALFO4

LKALFO1

LKALF02

| LKBREADY |

LKAREQ

LKBERR

LKBREAD

LKBLFO7

LKB PWR
FAIL

LKBLF05

LKBLFO06

LKBLFO04

.
MR-0883

Figure 4-11

RHFS (REG 5) Link A

4-13

Bits

Description

LAF7-LKALFO07 - General-purpose link function bit. Available to the system software protocol definition. Setting this bit sets LINK STATUS 03 on the B side.

LAF6-LKALF06 - General-purpose link function bit. Available to the system software protocol definition. Setting this bit sets LINK STATUS 02 on the B side.

LAF5-LKALFO5 - General-purpose link function bit. Available to the system software protocol definition. Setting this bit sets LINK STATUS 01 on the B side.

LAF4-LKALF04 - General-purpose link function bit. Available to the system software protocol definition. Setting this bit raises LINK STATUS 00 on the B side.

LAF3-LKALERR - Link A link error bit. This bit is provided to the software to signal
an error condition to the B side. This will cause the other side’s ERR and ATA bits to
set causing an interrupt. This bit normally terminates a data transfer if the word counts
are not equal.

LAF2-LKALFO02 - General-purpose link function bit. Available to the system software protocol definition. Setting this bit sets LINK ATTENTION 03 on the B side.

LAF1-LKALFO1 - General-purpose link function bit. Available to the system soft-

ware protocol definition. Setting this bit sets LINK ATTENTION 02 on the B side.

LAFO0-LKAREQ - Link A side request bit. LINK REQUEST is asserted by processor
A to become link master. If the other processor is not in control of the link, the requesting processor immediately becomes link master. Setting LINK REQUEST interrupts
the other processor and sets LINK REQUEST ATTENTION on the B side. LKAREQ
also sets LKMASTER ATTENTION on the A side when A becomes link master.

LAS7-LKBREADY - Link B side ready bit. Status bit provided to the A side indicating that the Link B side is ready for a transfer operation. This is a read-only bit.

LAS6-LKBREAD - Link B side read function line. Status bit provided to the A side
indicating that the B side link is set up for a read data transfer to the B side. This is a
read-only bit. Valid only when read bit is 0. When cleared, this bit indicates write.

LAS5-LKBERR - Link B side error bit. Status bit provided to the A side indicating
that the B side has an active ERROR condition set. This is a read-only bit.

LAS4-LKB PWR FAIL - B power fail indicates a power failure condition in the other
interface. This is a read-only bit.

LAS3-LKBLFO07 - General-purpose link status bit. Available for system software protocol definition. Set by Link B side LINK FUNCTION bit 07. This is a read-only bit.

LAS2-LKBLFO06 - General-purpose link status bit. Available for system software protocol definition. Set by Link B side LINK FUNCTION bit 06. This is a read-only bit.

LAS1-LKBLFO05 - General-purpose link status bit. Available for system software protocol definition. Set by Link B side LINK FUNCTION bit 05. This is a read-only bit.

4-14

LASO0-LKBLF04 - General-purpose link status bit. Available for system software protocol definition. Set by Link B side LINK FUNCTION bit 04. This is a read-only bit.

RHDT - (REG 6) This is the same as the standard configuration.

RHOB - (REG 7) This is the same as the standard configuration.
4.2.3.2

DRO01-C/DR11-B Register Link Configuration - Only the following bits are redefined as indicated on the following bit maps of RHIS (REG 1) and RHFS (REG 5). These redefined bits are
described in Paragraph 4.2.3.1. Refer to Figure 4-12 for bit map.
Bits

Description

LATA 3 - General-purpose link attention bit. This bit is set by the other processor
setting its Function 3 bit in the DR11-B interface. Available for system software protocol definition. Causes an ATA interrupt if enabled.

LATA 2 - General-purpose link attention bit. This bit is set by the other processor
setting its Function 2 bit in the DR11-B interface. Available for system software protocol definition. Causes an ATA interrupt if enabled.
.

LKB REQ - Indicates that the other processor is requesting a transfer by setting its
Function 1 bit in the DR11-B interface. Causes an ATA interrupt if enabled.

LAF6 - (LKALF06) General-purpose link function bit, available to system software
for protocol definition. This bit set asserts the DSTAT C input line of the DR11-B.

LAFS - (LKALFO5) General-purpose link function bit, available to system software
for protocol definition. This bit set asserts the DSTAT B input line of the DR11-B.

LAF4 - (LKALF04) General-purpose link function bit, available to system software
for protocol definition. This bit set asserts the DSTAT A input line of the DR1 1-B.

LAF3 - (LKAREQ) Raises the ATTN line on the DR11-B interface. Available to
system software for general-purpose definition to indicate an error condition or a
transfer request.

LAS 7 (LKDBRDY) DR11-B side READY bit. Status bit provided to the A side to
indicate that DR11-B is able to accept a new transfer command. Refer to Figure 4-13
for bit map.

4- 15

RHIS
ATA | ERR
(REG1)

LKB
REQ

LATA|LATA
02
03

ICPE | IDPE | IRDY
1

LKDRBF2

LKDRBF1

LKDRBF3
MR-0884

RHIS (REG 1) Link B

Figure 4-12

15
RHFS
(REGS)

LAF | LAF | LAF | LAF
3
4
5
6

LKALFO06

(DSTAT C)

LKALFO4

LAS
7

LKDRBRDY

(DSTAT A)

LKALFO5
(DSTAT B)

LKAREQ
MR-0885

Figure 4-13

RHFS (REG 5) Link B

4-16

CHAPTER §

TECHNICAL DESCRIPTION
5.1 SYSTEM DESCRIPTION
Figure 5-1 is a typical DTRO1 subsystem. The basic unit in the DTRO1 subsystem is the DRO1-CL
channel interface unit. The DROI allows a user device to perform high-speed block data transfers to or
from memory via the Massbus and an appropriate Massbus controller. The transfer rate is determined
by the user device. Provisions have been made in the DRO1 to limit the transfer rate of the user device
so that it will not exceed the bandwidth of the system.
Normally the DROI is used in conjunction with an RH20 Massbus controller as shown in Figure 5-1.

A maximum of eight DRO1s can be daisy-chained together with the first DRO1 connected to the RH20
via the Massbus and the last DRO1’s Massbus connected to a Massbus terminator pack.
52
DATA TRANSFERS
A
Communication and control between the DTRO1 subsystem and the host processor is implemented
with seven programmable registers located in each DRO1-CL channel interface unit (see Figure 5-2).
The registers are loaded and cleared by DATAO and read by DATALI instructions from the CPU (see

Paragraph 4.2). The actual data transfer between the user device and the CBus is enabled using a read
or a write from the register control (see Figure 5-3). During a write operation, data is placed onto the
CBus and travels via the RH20 write register from the Massbus to the DROI1 interface and then over
the device data lines to the device. During a read operation, data travels over the device data lines
through the DROI1 interface to the Massbus data lines and then onto the CBus via the RH20 data
buffer read register. The following is a description of how these data transfers are accomplished.
The seven function registers are used to perform data transfers by performing the following steps.
1.
2.

Determine if the DROI1 interface is ready.
Load the user function/status as defined in the protocol.

Paragraph 4.2.1 provides the information for programming these steps using DATAO and DATAI
instructions to read or write the seven external registers located within each DRO1. Paragraph 4.2.2
provides a detailed description of the contents of each of the seven registers. Figures 5-4, 5-5, and 5-7
through 5-12 are flow diagrams which provide the data flow within the DRO1 control (8431), the DRO1
test card (8432) and the three Massbus transceivers (MB1, MB2, and MB3) for the DROI1 registers.
5.2.1
REG 0 (RHCS1) Control and Status Register Signal Flow
As shown in Figure 5-4, the control and status register generates the function code and GO pulse to
enable a READ, WRITE or INTERFACE CLEAR. It also contains the drive ready status (DRY).
DRY is an unconditional status bit returned. This register is selected to be loaded or read onto the
Massbus by DATAO or DATALI instructions from the KL10-B, C, D or E CPU.

All Massbus lines of the DROI logic are reset by INIT which becomes true (+3 V) whenever the
Massbus is initialized. The DRO1 is initialized also when an INTERFACE CLEAR command
(RHCSI, REG 0 bits 05-00 = 11g; see Paragraph 4.2.2.1) is received by the interface. This means bit 00

or the GO bit = 1.

5-1

CONFIGURATION RULES:

Grorenes — —
KL10

RH20 | MASSBUS

l l MOUNTING BOX
l

| !
l

DRO1¢-CL

I
| '
I
|

DRO14-CL

'
DRO1,-CL

1 . MAX 8 DRO1-CL per Massbus (RH20).

2. Dedicated RH20 for DRO1 subsystem; no
sharing.
3. MAX 1 Massbus per DRO1 box
4. MAX 2 Massbus per cabinet.
5. MAX 3 DRO1-CL per DRO1 box
6. MAX 3 DRO1 box per cabinet

7. Only 1 second system box per cabinet

(DTRO1-CC/CD).

8. If second system box in cabinet, max con-

figuration is:

MB NO 1 =3 DRO1-CL
MB NO 2 =6 DRO1-CL

DRO15-CL

DRO14-CL

DRO15-CL

DRO145CL

DRO14-CL

CABINET
MR-0869

Figure 5-1

A Typical DTRO1 System

5-2

|
- -—fl__——— —

|
MAIN

MEMORY

SBUS

KL10

cPU

MASSBUS

CBUS

pDATA

FLOW)

REG 1

REG 5

RHIS

RHFS

REG 2
RHIB

REG 6

RHOB

RH20

MASSBUS

CONTROL

CONTROLLER

DATA

CONTROL

|
CONTROL

EBUS

DEVICE

RHDT

REG 7

(PRIMARY |

DATA

REG 4
RHAS

REG 0
RHCS1

| | oro

DATAI

DTRO1 CABINET

DATAO

MR-1783

Figure 5-2 Communication Between DTROI and
KL10-B, C, D or E Processor
5-3

RH20 MASSBUS CONTROL (1 OF 8)
DATA BUFFER

PRA

WRITE

SRA

DATA IN LINES

>
SRB

PRB

REQUEST

DATA $ STROBES

LINES

EXCEPTION

SCANNER SYNC (TIMING) LOGIC

scik
WCLK

STROBES

ERROR

DONE

RESET

START

ctom

CLK, CYCLE REQ A, B, END

y EN D (DATA CYCLE)

OCCUPIED

STORE

CHANNEL START/STOP AND BLOCK COUNT LOGIC

DONE

‘ CONTROL

RESET
>

INTERRUPT

LOGIC

EBL

Zgfi?:;‘ifi

EBL

IDPE

INTERFACE

MASSBUS

ATTENTION}

Sle

ATTENTION

USER ERROR, USER ATTENTION

0 INT

DATAO

REG 35

RS04-01/|
DS02—00

GATE

| DS02-00
RS04-01/

DATAO/DATAI " |~REPARATION (XX) 2R T0

TG DATAT"]_SBAR (FILE)

Foo-02

SATA

DEMAND
»|

PBAR (FILE) (72)

“DATAI

INSTRUCTION | DATAO/DATAI

TRANSFER

DATAI

DATAOD

DATAO

= Bl

CONI

“ | Dos

CONO

VIR
\

DECODERS

(73)g

—»{

Ta)g
8

(76)g

DCR

(77)g

=
CONTROL
AND2l
STATUS

2
(00)g

N NTERFACE STATUS

(01)g

A RITE

INPUT BUFFER

READ/WRITE

TCR TO | MASSBUS

PTCR (FILE)

READMRITE—+|
READ

(701 | MASSBUS

STCR (FILE) (71)g

CONTROLLER

AND

IRDY

RUN

DEVICE

ERROR

CLK

ACKN

OCCUPIED

RUN

‘ TCR TO

BITS

CS00—06

CYCLE, BUSY, READ, GO

DATA

DONE

PI 01-07

% EN B/D (REQ/DATA CYCLE)

SEL 0-7

;

WR CLK

ERROR

EXCEPTION

scLk|

DATA TRANSFER CONTROL LOGIC

& |LASTWORD| |
o
©

DATA OUT

’
READY

LINES

READ

DEMAND

DRIVE

CONTROL

cton|
TRANSFER|

DEMAND|

READ//amTE

CONTROL

[———

TRANS|FER

DATA IN

(02g

ATTENTION SUMMARY

DI15—DI00

_ (0dg

»] USER FUNCT AND STATUS
DRIVE TYPE

WRITE

|ctoo

:ECF;IE, - LOGIC

038

READWRITE

FEGISTER

TRO
CONTROL

SUTPUT

UTPUT B

USER DEFINED FUNCTION
AND STATUS

(05)g
(06)g

BOFEER

DATA OUT DO15-D0Q0

—

—_—

@oig

STATUS

@78

CONTROL

READ EXT REG

LOAD EXT REG

‘

EBI

STROBE

LOAD
MASS BUF
D035

MASSBUS

FILE
,

BUFFER

CONTROL|

|CONTROL (16 BITS)

E BUS

INPUT

MR-1786

Figure 5-3

DTRO1 Subsystem Data Flow Block Diagram

5-4

MB1 O1
Co5-C

CONTROL

|
MB1CO0

(cPF)

PARITY
AN
FUNDCTION
REGS

.
REGISTER

FCT 0004

IBUS

FCT

REG 0 RHCS1 CONTROL AND STATUS REGISTER

001—05'

00—04

MUX
(RMX)

MASSBUS

(w1 l;\11\)|SCEIVER
1BUS C00 >| T

E67

RMX READ CS1

DRY

ENABLE

{BUS

ci1

MASSBUS

» TRANSCEIVER
(MB2)

E32,

MR-1782

Figure 5-4 REG 0 (RHCS1) Control and Status Register
Circuit Block Diagram

type of command to be
01-05 are decoded to determine,theWRIT
The contents of RHCS1, REG 0 bits
E or INTERFACE
READ
and code (other than
executed by the logic. Any invalid comm
1).
ace in the busy state (GO =
CLEAR) will hang the DRO1-CL interf

ion of RUN from the
of the data transfer command (negat
The GO bit is cleared at the completion
set and INTERFACE
ns
remai
bit
and is issued, the GO
Massbus). If the INTERFACE CLEAR comm
transfer command
valid
new
a
and is received. Each time
CLEAR is asserted until the next comm
the user interface.
to
ted
genera
is
(READ or WRITE) is written into the command register, a GO pulse
The GO bit, if set, is readable also back to the CPU.

Signal Flow (See Figure 5-5.)
522 REG 1 (RHIS) Interface Status Register
to do data transfers. READY occurs when BTC ENBL is

READY indicates that the interface is ready

low.

the interface status
is produced by the BCD decoder, E80E63onflip-f
AS0-7 for attention summary register3 use
lop using TCB
at
ced
produ
is
-ATO are present. MB ATTN USA user error. The IDPE
register (ISR) when TCB ATO0ERR
and ICPE
the
status bits which use
ATO0-ATO3. ERR and USER ationareand
t are
circui
this
to
inputs
signal
ol
Contr
checking circuitry.
are produced via the parity gener
MBI
are
t
circui
this
to
inputs
data
the
I BUS C08-C15 and
RMX I BUS C00-C07 and RMXB D12and function
D17. Parity is generated in the controlareparity
MB3
and
D11,
D00-D05, MB2 D06via interface
sent
errors
parity
Any
).
OBRB
registers (CPF) and output buffer registers (OBR and
ERR.
USER
and
ced ERR
status register (ISR) to the same circuit that produ

E bit. A data transfer is
ace status register generates the CYCL
As shown in Figure 5-5, the interf
the CYCLE REQUEST A or
is set either by the logical OR ofRHIS
usually initiated when the cycle flip-famlopwriti
REG 1 (see Paragraph
of
04
bit
ng a CYCLE bit,
B user input lines or via the progr
D or WRITE)
(eithe
cycle
er
transf
g diagram (Figure 5-6), a dataeted (indicated by ther REA
4.222). As shown in the timinprevi
negation of BUSY
has been compl
then begins provided that the aceousis cycle
us). BUSY is asserted for
still receiving RUN from the Massbning
and READY and while the interf
transfer
each word or byte transferred. BUSY is also used to indicate the begin of a new data
cycle.

5-5

REG 1 RHIS INTERFACE STATUS REGISTER
REGISTER

MULTIPLEXER

TRANSFER
BYTE
CONTROL
(BTC)

ENBL |

E11B

DATA TIMING
conTROL

(RMX)

READY

B
C00—07

B
C00—05

MASSBUS

(DTC)

TRANSCEIVERS

ES5

(MB1)

J1-JJ-BB2

USA
USER

ERROR

INTERFACE

STATUS

TEST CARD

AS0—7

SES;STER

8432

AT00—03

CYCLE

co6,
E43,

MASSBUS

TRANSCEIVERS

(MB2)
RMXB IBUS

CONTROL

C15-08

PARITY AND

FUNCTION

REGISTERS

RMX 1BUS

C07—C00

—

C08—11

MULTIPLEXER

»|

ICP

(RMXB)

ERR

(CPF)
E21,

MB ATTN

73
USER ERR

MB1 D00—05
MB2 D06—11
MB3 D12—17

IDPE

OUTPUT BUFFER | ouTPUT
REGISTER
PRTY ERR
E58, 60, 64, 65

66, 70,71, 72
77,78, 83, 84
(ORB)

C08—15

\CPE

E33, 44, 45

C12—15

MASSBUS
TRANSCEIVERS
(MB3)

51, 57, 63

69, 75,
81

E24

25
MR-1779

Figure 5-5

REG 1 (RHIS) Interface Status Register
Circuit Block Diagram

BYTE MODE WRITE:

USER GO H

[]

(

BUF RUN H

USER READY
H

(

( (

( (
LR

ENABLE NEXT CYCLE H

-CYCLE REQUEST
H

r_‘ '

1
|

\
=)

CYCLE (1) H
i

BUSY (1) H

[

BYTE PTR (1) H

[ (

[

[ (

[

( (

[

)

BYTE DELAY (1) H
|

)

END CYCLE (1) H
LO TO HI BYTE
H

SCLK (1) H

)

]

(

)

(

LO BYTE

HI BYTE
MR-0878

Figure 5-6

DTRO1 Timing (Sheet 1 of 2)

5-7

WORD MODE DRO1 TIMING

USER GO H

[]

BUF RUN
H

o
|I

{

USER READY
H

ENABLE NEXT CYCLE H

CYCLE REQUEST
CYCLE (1) H

[

BUSY (1) H

|
|

[

DTC CLEAR CYCLEH

SCLK WIDTH (MIN 150ns MAX 20us)
WORD DELAY (MIN 150ns MAX 20us)

]

SCLK (1) H

‘J

s s
,

]
J

s s
|

END CYCLE (1) H

| I

l
MR-0879

Figure 5-6

DTRO1 Timing (Sheet 2 of 2)

3-8

If CYCLE REQUEST is received before the completion of the previous cycle, the request is stored and
the new data transfer cycle begins as soon as the previous cycle is completed. Thus, the user device can
overlay cycles so that the interface is primed to begin another cycle immediately upon completion of
the first. If a CYCLE REQUEST is received before a valid data transfer command, it is ignored.

When a write command is received (RHCSI, REG 0 bits 05-00 = 61g) from the host, negation of
either CYCLE REQUEST A or B occurs. The DROI1 data transfer control strobes out the data and the
if desired.
host may change the data lines

Completion of the data transfer is indicated by the negative transition of the BUSY signal and the

assertion of the END CYCLE signal.

The BUSY signal is cleared as soon as the END CYCLE signal is asserted. The data from the previous
cycle remains valid on the data lines until the new data is received from the Massbus controller. New
data will be presented on the data lines along with the optional parity bit as soon as the data transfer
cycle is complete (END CYCLE asserted and BUSY cleared). The data lines become stable when
BUSY clears. The user device may then delay initiating another cycle until it has processed the data or
it may immediately initiate another cycle if the data is strobed within the next 250 ns. BUSY will set
immediately following the negative transition of CYCLE REQUEST only if the interface has completed the previous data transfer operation and READY is reset.

During a read operation, a READ command is received (RHCS1, REG 0 bits 05-00 = 71g) from the
host. The user device must provide the DATA IN (0-15) signals plus the optional parity bit (DPA IN
LO and DPA IN HI). If parity is not used, the Input Parity Inhibit (IPI) signal must be asserted by the
user interface to prevent an undesired parity error indication. Use of additional data bits (bits 16 and
17) is intended for interfacing to larger machines. They are not used with the PDP-11 systems. (See
Figure 5-7.)

This interface performs no data packing or formatting of the data passed between the host and the user
interface. For a read, device data lines from the user must be stable 50 ns prior to the high-to-low
transition of either CYCLE REQUEST A or B. The user device must maintain the data lines stable
until the cycle begins with the positive transition of the BUSY signal. At this point, the interface has
strobed in the data and the user device may change the data lines if desired. Completion of the data
transfer will be indicated by the negative transition of the BUSY signal and the assertion of the END
CYCLE signal. The BUSY signal will be cleared as soon as the END CYCLE signal is asserted.
5.2.3

REG 2 (RHIB) Input Buffer Register Signal Flow

An alternate method of performing a read is by using the input buffer register (RHIB) REG 2 as
shown in Figure 5-8 using a DATALI instruction from the KL10-B, C, D or E CPU. This transfer is
performed over the Massbus C lines instead of over the CBus data lines as in the primary method
‘

described previously.

5.24

REG 4 (RHAS) Attention Summary Register Signal Flow

As shown in Figure 5-9, the attention summary register (RHAS) REG 4 uses the ATO0-ATO3 at the
user device interface via the test card and the device select code US00-02 to develop the AS00-ASQ7
signals. The interface only asserts one bit if it reads attention service corresponding to its device select

code.
5.2.5

REG 5 (RHFS) User Function and Status Register Signal Flow

As shown in Figure 5-10 Massbus control signals C08-C14 are used for the FR00-07 general-purpose
user function bits which are user-defined. The DS00-07 general-purpose status bits reflect the state of
user-defined signals connected to interface inputs via the test card. Both groups of eight signals are sent
via the Massbus transceivers to the Massbus when the user function and status (RHFS) register is read.
5-9

17.18 19 20
1

DATA FORMAT

)

]

WORD 1

»
1

WORD 2
1

*Bits 0, 1 or 18, 19 are not used with PDP-11 type transfers.
MR-0880

Figure 5-7

Data Format

REG 2 (RHIB) INPUT BUFFER REGISTER

MULTIPLEXER

MASSBUS

DATA 00-07 IN

CO0—05 IN

TRANSCEIVER

USER DATA LINES
DATA 0007 IN

(MB1)

TEST

CARD

E13,

C06,
07 IN

8432
MASSBUS

TRANSCEIVER

DATA 08—-15IN

CO08-11 INA
TM

(MB2)

(RMXB)
USER DATA LINES

)

DATA 08—15IN

MASSBUS
C12-151IN | TRANSCEIVER

CPA

E18,

(MB3)

MR-1787

Figure 5-8

REG 2 (RHIB) Input Buffer Reglster
Circuit Block Dlagram

5-10

REG 4 (RHAS) ATTENTION SUMMARY REGISTER

TEST

ATO0—ATO3

CARD
8432

INTERFACE

STATUS

MULTIPLEXER

(RMX)

MASSBUS
CS00— C00— TRANSCEIVERS
Cso7

(ISR)

CO05

(MB1)

DEVICE
SELECT

CODE
USs00-02

SELECTION

CONTROL

US02-uUs00

(RSC)

MASSBUS

E44, 45, 51
57,63, 69,
80, 86

E25

TRANSCEIVERS

E62,

(MB2)
MR-1788

Figure 59

REG 4 (RHAYS) Attention Summary

REG 5 (RHFS) USER FUNCTION AND STATUS REGISTER

ere—ehs .

CONTRO

PARITYL

AND

Cc08-15
REGISTER

FUNCTION

MULTIPLEXER

(CPF)

C12—15
oh

MASSBUS

‘TRANSCE|VERS

(MB3)

FR0O0—07 | (RMXB)

MB2

C08—C11
—_—

E30,

E18,

C08—11

*1 MASSBUS
TRANSCEIVERS

06,

:JNSESRFACE

TEST

CARD

8432

|(mB2)

)

MULTIPLEXER

DS00—-07 |

(RMX)

MASSBUS

C00—07
E13,

c00—05

| TRANSCEIVERS
(MB1)

MR-1789

Figure 5-10

REG 5 (RHFS) User Function and Status Register
Circuit Block Diagram

5-12

5.2.6 REG 6 (RHDT) Drive Type Register Signal Flow

Figure 5-11 illustrates the drive type circuit which uses the SEL RHDT signal to produce a 4g drive
type code on control line 02 to the Massbus via Massbus transceiver MB1.

REG 6 (RHDT) DRIVE TYPE REGISTER
MB1

RS03—-04

err—————

MB2

RS02—-00

—_—

MASSBUS

SELECTION

MULTIPLEXER

TRANSCEIVERS

CONTROL

(RMX)

SEL RHDT

C02

(MB1)

(RSC)
E22, 23, 28

E16,

32
MR-1780

Figure 5-11

REG 6 (RHDT) Drive Type Register
Circuit Block Diagram

5.2.7 REG 7 (RHOB) Output Buffer Register Signal Flow
An alternate method of performing a write is by using the output buffer register (RHOB) REG 7 as
shown in Figure 5-12 using a DATAO instruction from the KL10-B, C, D or E CPU. This transfer is
performed over the Massbus C lines instead of over the CBus data lines as in the primary method
described previously.

USER
REG 7 (RHOB) OUTPUT BUFFER REGISTER
MASSBUS
TRANSCEIVER

»|

(MB3)

OUTPUT

TEST

BUFFER

CARD

(OBRB)
MASSBUS

TRANSCEIVER

INTERFACE

D08—17

(OBR)

CPF BUF
C06—C11

OUTPUT

(MB2)

|
BUFFER
D00—-07 | REGISTER

D00—07
CPF BUF

MASSBUS

- TRANSCEIVER

(MB1)

D08—-17

C00—Co05|
»

E59, 60, 70

(OBRB)

72,76,77,

E64, 66, 71

83, 84

E1,6, 10,
E76,

14,15

MR-1781

Figure 5-12

REG 7 (RHOB) Output Buffer Reglster
Circuit Block Diagram

5-13

5.3

LINK OPERATION
The DTRO1-C can be used to establish a high-speed interprocessor link between separate computer
systems. This is accomplished by interconnecting two DRO1-CL units, one on each system; or with a
DR11-B interface via a BC11A type cable. The functional operation of the RHIS (REG 1) and RHFS

(REG 5) bits differ from the standard operation. (See Paragraph 4.2.2.) Figure 5-13 shows how
DTRO1 link connectors are implemented. See Tables 5-1 and 5-2.
NOTE
Link relationship - Side A is the nearest interface,
Side B is the farthest or other interface.

TO OTHER

TO OTHER PROCESSOR

PROCESSOR (PDP-11)

(DECSYSTEM-10

UNIBUS

MASSBUS)

DR11B

[

DRO1

LINK

CONNECTORS

]

[

[ ]

IDE

SLOT 4

SLOT 1
C

SLOT 1

LINK

CONNECTOR

CONNECTORS

DRO1

TO DECSYSTEM-10
MASSBUS

TO PROCESSOR

MASSBUS
BACK-TO-BACK

DR11-B TO DRO1

CONNECTION OF DRO1’S
MR-0881

Figure 5-13

DTRO1 Link Connectors

5-14

The back-to-back interconnection of two DROIls is shown in Figure 5-14.

CPU A

CPU B

DATA OUT 00:17
DATA IN 00:17

®DATA IN 00:17

DATA OUT 00:17

AT00=

ATO @a—

»ATO1

»AT00

A LINK REQUEST

B LINK REQUEST
A

MCLK

LINK

MASTER

o
P
NOTE
FOR DRO1 TO DRO1 SIGNALS, SEE
TABLE 5-1.

FOR DR11-B TO DRO1

SIGNALS, SEE TABLE 5-2.
MR-1228

Figure 5-14

DTRO1 Back-to-Back Signal Connections

5-15

Table 5-1

DRO1 to DRO01 Signal Connections

CPU A (DRO1)

CPU B(DRO1)

USA CYCLEREQUEST A
TCB FROO-FR02

TCC END CYCLE
USB AT00, AT02, AT03
USB DS07
USA DATA 00, 02-15 IN
USB DS06
USA REQUEST CYCLE A
TCC DATA 00-15 OUT
TCB FROS5
TCB FRO3
DRB ENB
TCB FR04, FR06
TCB DATA 16 OUT
USB DATA 16 IN
TCB LO PAR OUT
TCB HI PAR OUT

DTC READY
TCC DATA 01-15 OUT
TCC READ
TCC END CYCLE
USA DATA 00-15IN
USA DS01
USA ERROR
+3 VSOURCE
USA DS00, 02
USB DATA 16IN
TCB DATA 16 OUT
USBDPA LOIN
USB DPA HI IN

USB INHIBIT INPUT PARITY
USB DATA 17 IN
USB ATO1
USB ATO00, 02,03
USB WORD MODE
+3VC
USB DS06
MCLK
FDC ARB CLK
FDC LINK MASTER (1) B
USB DS03
USB DS04
USB DS05
USB DS07
FDC ARB CLK
TCBDATA 17 OUT
TCB HI PAR OUT
TCB LO PAR OUT
TCB FRO3
LOCKOUT
TCB FR04-FRO6
TCB FRO7
ISR ERR(1)B
ACLO

TCB DATA 17 OUT

LOCKOUT
TCB FRO0-FR02
+3A
USB USER WORD MODE
TCC READ
E01F2
LOCKOUT
TCB FRO7
ACLO
ISR ERR (1) B
DTC READY
MCLK
USB DATA 17 IN
USBDPAHIIN
USBDPA LOIN
ERROR
USB ATOI
FDC LINK MASTER (1) BH
USA DS00-DS02
USB DS03
USB DS05
USB DS04

5-16

Table 5-2

DRI11-B to DR01 Signal Connections

CPU A (DR11-B)

CPU B (DRO1)

D6 CYCLE REQUEST A
D6 END CYCLEOUT
D6 DAT 00-15 IN
D6 DSTAT B
D6 ATTN
+3V F03 Ul

TCC END CYCLE
USA REQUEST CYCLE A
TCC DATA 00-15 OUT
TCB FRO5
TCB FR03
DRB ENB

D6 WC INC ENB
D6 DSTATA, C
BA INC ENB
D6 FNCT 1, 2, 3
D6 READY
D6 DATO00-15 OUT
D6 C1 CONTROL
SINGLE CYCLE

TCB FR04, TCB FR06
DRB INB
USB AT00, AT03, AT02
USB DS07
|
USA DATA 00-15 IN
FDCREAD B
DRB ENB

5-17

CHAPTER 6
PREVENTIVE MAINTENANCE
6.1
GENERAL
In addition to the normal preventive maintenance checks recommended for DEC devices, the corrective maintenance procedure (Paragraph 7.2) should be run periodically to check the DRO1 operation.
Since there are no console switches on the KL10-B, C, D or E, the 16 switches on the PDP-11 are used
together with 20 software switches to make up the 36 KL10-B, C, D or E switches. In stand-alone
mode, the rightmost 16 address switches on the PDP-11 are mapped to the leftmost 16 switches for the
KL10-B, C, D or E, the rightmost 20 KL10-B, C, D or E switches are software-defined, using the

console command SW.
The 20 software switches may be examined at any time (even during typeout) by typing the following.
<CONTROL X>SW<CARRIAGE RET>
The software switches may be set at any time by typing:
<CONTROL X>SW <lefthalf> <righthalf>

where:

<lefthalf> is the desired octal value of the left half of the switches (See Table 6-1)
<righthalf> is the desired octal value of the right half of the switches (See Table 6-2).
Table 6-1

-10

Left Half Switches — Standard Definition

-11
SW

Octal

Use
When 1

Meaning

0
1
2
3
4
5
6
7
8

15
14
13
12
11
10
9
8
7

400000
200000
100000
040000
020000
010000
004000
002000
001000

ABORT
RSTART
TOTALS
NOPNT
PNTLPT
DING
LOOPER
ERSTOP
PALERS

Abort diagnostic at the end of the current pass
Restart diagnostic
Print statistics
Inhibits all but forced printouts
Output to LPT (or logical device in user mode)
Ring the bell on error (this is forced)
Loop on error
Halt on error (switch ignored if in user mode)
Print all errors

10
11
12
13
14
15
16

5
4
3
2
1
0

000200
000100
000040
000020
000010
000004
000002

TXTINH
INHPAG
MODDVC
INHCSH
OPRSEL
CHAIN
KAHZ50

Shorten error printout
Inhibit paging
Not used
Inhibit operation of the cache
Operator select
Not used
Not used

000001

RESERVED | Not used

-9

000400

RELIAB

RELIAB - do each test more than once

Table 6-2
-10

Right Half Switches - Standard Definition

Use

Octal

When 1

18
19
20
21
22
23

400000
200000
100000
040000
020000
010000
004000
002000

TRASW

001000

LOOPTS

Loop on current test

27
28-35

000400
000377

SPCTST
TSTMSK

Loop on specific test
Mask for specific test number

24
25

Meaning

Trace current test number
Not used
Not used
Not used
Not used
Not used
RCFGSW | Allow reconfiguration at the end of main diagnostic logic
INHRSW
Skip portion of pass count printout

The leftmost 16 KL10-B, C, D or E switches are unaffected by the SW command. The switches can be
changed while the program is running by typing the following.
<CONTROL G>

In user mode, the switch definitions remain the same as in EXEC mode. However, all 36 switches are

software-defined. When the diagnostic is started or restarted, the user will be asked about the switches
and may then respond with the following options.

Response

Meaning

Leave switches 0.

Same as the last time switches were specified.

Y
N

6.2

Allows user to specify the switces in octal.
KL10: leave switches 0.
KL10, KI10: use physical console switches.

HIGH PERFORMANCE CHECKOUT

The DRO1 is a high-performance device and system problems caused by the simultaneous operation of
a number of high performance options can be just as detrimental as a logic problem in the DROI. It is
therefore recommended that the performance of systems containing a DRO1 be thoroughly evaluated
at the time of installation and after any major change in the system configuration. To evaluate the
performance of the system, run the DTRO1 diagnostic, DFDRA.A10 as instructed in the diagnostic
listing under the monitor in user mode with other system modules simultaneously. If problems develop
such as data late errors on any device in the system, attempt to correct the problem by limiting the
transfer rate of the DROI.

A console mode is provided in the diagnostic to assist in accessing internal and external registers. Table
6-3 lists the commands used for the diagnostic console command mode.

6-2

Table 6-3

Command Data Commands

Command

Meaning

CFG
CMO
CNI
CNO
CSW
DDT
EXT
HLP

Change configuration

Change printout mode
Do CONI to read control status in RH20
Do CONO to load control data in RH20
Reset switch
Go to DDT
Back to program dispatcher
Print HELP message

IDT
LAS

Identify configuration
Load attention summary register

LCS
LDC
LDR*

Load control and status 1 register
Load diagnostic control register

LFS
LIB
LIS

LIV

LOB
LSB
LST
LWT
RAS
RCS
RDA*
RDR*
RDT
RFS
RIB
RIS
RIV
ROB
RPB
RPT
RRD

RSB
RST
SDT
SWI

Load register with data
Load function and status register
Load input buffer register
Load interface status register
Load interrupt vector register
Load output buffer register
Load secondary block address register
Load secondary transfer control register
Load the write register
Read attention summary register
Read control and status 1 register
Read registers from O up to 7
Read register
Read drive type register
Read function and status register
Read input buffer register
Read interface status register
Read interrupt vector register
Read output buffer register
Read primary block address register
Read primary transfer control register
Read the read register
|
Read secondary block address register
Read secondary transfer control register
Test data transfer with word count (33-100)
Print current state of switch

*Address must also be provided.

6-3

CHAPTER 7
SERVICE
7.1

GENERAL

The DRO1 interface contains the testing circuitry required for maintenance purposes. Buffer/test module M8432 includes the test circuitry and most of the drivers and receivers that connect to the user
interface. Figure 7-1 is a block diagram of the M8432 module.

[user

USER

DRIVERS

RECEIVERS | | RECEIVERS

INTERFACE | | INTERFACE

DATA

(8:17)

(0:7)

LOCATED ON M8432 MODULE

DATA OUT

(0:7)

DATA OUT (8:17)

[DPAINLO

SILo

J\/L J1

DPA INHI

I V

|
||

FROM USER

INTERFACE

MR-0891

Figure 7-1

M8432 Buffer/Test Module Block Diagram

As) must be removed. The
To use the DRO1 in maintenance mode, the user interface cabling (M9760-Y
and J2) on the M8432.
(J1
connectors
test
two
the
between
installed
be
then
must
cable
test
BCOS8R

Refer to the maintenance cable signal drawing DTR01-0-3 which shows the signal interconnections in
the maintenance mode.
7.2

CORRECTIVE MAINTENANCE

If a problem develops relating to the DRO1, connect the BOO8R cable as described above and run the
DTRO1 diagnostic, DFDRA.A10, as instructed in the diagnostic listing.
7-1

APPENDIX A

DTRO01 INSTALLATION CONSIDERATION
A.1

POST INSTALLATION CONSIDERATIONS

If the interface connection of the customer /user does not include the extended user interface connector
of the DTRO1/DRO1, the user might desire to disable certain floating input signals in slots E/F04

(extended user interface connector DRO1-CL logic).

“This can be accomplished by grounding the following pins on the M9760-Y
A cable connector module
normally inserted in slots E/F04 of the DRO1-CL logic.
Pin

Signal Disabled

EAl

USB DATA 16 IN
USB DATA 17IN
USB ATO1
USB ATO02
USB ATO3
USB DS06
USB AT00
USB AT00
USB DSO03
USB DS04
USB DSO05
USB DS07

EF1

EHI
EJ1
EK1
ED2
EE2
EN2
EN2
EP2
ER2
ET2

APPENDIX B

LINKING PROCEDURE

"B.1- DRO1/DR11-B LINKING PROCEDURE

The following procedure should be consulted to configure a link interconnection between a DR0O1-CL

and a DR11-B interface.
1.

Refer to the DRO1/DR11-B link logic connection drawing, C-IC-DTRO01-0-6.

Install a BC11A or equivalent type cable between slots C/D04 of the DR11-B interface and
slots C/DO01 of the DRO!-CL logic to be linked. The cable length must not exceed 9 m (30 ft)
in length.

Use a pair of the following connector boards: M908, M959, M930, M970, M974. Insert the

pair into slots E/F01 of the DRO1-CL logic of the supplied M9760-YA cable connector

board and ground the following pins on the board to disable floating input signals in slot
E/FO1 (extended link connector slot).
Pin

Signal Disabled

EBI1
FHI
FH2
FJ2
FK2
FL2
FN2
FP2
FR2
FS2

USB DATA 16 IN
USBDATA 17IN
ERROR H
USB ATO1
USA DS01
USA DS02
USA DS00
USB DS03
USB DSO05
USB DS04

Set DRO1-CL DI SWITCH SW1 as desired.

b.
c.

Set SW1-1, SW1-2, and SW1-3 to the desired drive address.

Select word mode (SW1-7 = OFF).
Set no input parity check (SW1-8 = OFF).

Refer to the following drawihgs for further information on the DR0O1/DR11-B linkage.
D-BD-DTRO01-0-8

DRO1-C/DR11-B Register Link Configuration
D-IC-DTRO01-0-10

DRO1/DR11-B Link Signal Translation

A-SP-DTRO01-0-12

DRO1/DR11-B Linking Procedures

B-1

B.2
DRO1/DR01 LINKING PROCEDURE
The following procedure should be consulted to configure a link interconnection between a DRO1-CL

and another DRO1-CL interface.
1.

Refer to the DROI link connection drawing, C-IC-DTRO01-0-7, for cable installation

Install two BC11A or equivalent type cables between slots C/D04 and E/F04 of one DRO1CL interface and slots C/DO01 and E/F01 of the other DRO1-CL logic to be linked.
The
cable length must not exceed 9 m (30 ft) in length.

Set DRO1-CL DIP SWITCH SW1 as desired

b.
c.

Set SWi-1, SW1-2, and 1-3 to desired drive address

Word mode should be selected (SW1-7 = OFF)
Set no input parity check (SW1-8 = OFF).

Refer to the following drawings for further information on the DROI1 /DROL1 linkage.
D-BD-DTRO01-0-9
DRO1-C/RH20 Register Link Configuration

D-IC-DTRO01-0-2
-DROI1 Link Signal Translation
A-SP-DTRO01-0-13
DRO1/DROI Linking Procedure

B-2

APPENDIX C

USER INTERFACE SPECIFICATION
C.1
USER INPUT/OUTPUT SIGNALS
|
This section describes the signals made available to the user dev1ce to control the operation of the
interface. Paragraph C.1.1 describes the user input/output signals. Paragraph C.1.2 details the timing
considerations and restrictions on the use of the signals.
C.1.1

Signals List

Tables C-1 and C-2 list the signals available to the user device. Input loading refers to the number of
TTL unit loads the input signal must drive. A unit load is defined as:
2.4 V < Input high voltage < 5.0

V @ 40 pA plus terminator load

0.0 V < Input low voltage < 0.4 V @ 1.6 mA plus terminator load
where current flow is defined positive into the driven gate.

All output Signals are driven with 7437 drivers. These drivers can sink 60 mA in the output low state

and can source 1.5 mA in the output high state. This is equivalent to a fan-out of approximately 30 unit
loads.

All input signals are received by 7414 Schmitt trigger receivers for noise immunity. The signal inputs
are terminated at the receiver input with a 180 ohm resistor to +5 V and a 390 ohm resistor to ground.
All signal inputs represent one unit load.
C.1.2 Timing Considerations
The negation of READY, as well as a nominal 1 us pulse on the GO signal, indicates to the user device
that a valid data transfer command has been received by the interface. The READ and WRITE signals
will indicate which direction of transfer has been requested by the processor.

C.1.2.1
Read Operation - If the operation is to be a read, the user device must provide the DATA IN
(0:15) signals plus optional parity bit (DPA IN LO and DPA IN HI).
NOTE
If parity is not used, the Input Parity Inhibit (IPI)
signal must be asserted by the user device to prevent
an undesired parity error indication. The use of the
two additional data bits DATA IN 16 and 17 is not
required on the PDP-11 and is intended for interfacing to larger machines such as the
DECsystem 10.
In Figure C-1, the data lines must be stable 100 ns prior to the high-to-low transition of either CYCLE
REQUEST A or B. The negation of either of these two signals will set the CYCLE flip-flop and will
cause the interface to begin a data transfer cycle provided the following conditions are met.
1.
2.

The interface has completed the previous cycle (indicated by negation of the BUSY signal).
The interface is in the RUN mode (indicated by negation of READY).
C-1

Table C-1

Name
DATI17 INDATO0 IN

No. of
Signals

Description*

Data input from user device.
'

‘

NOTE
Bits 17 and 16 may be tied to ground if only 16-bit data
transfers are desired.

CYCLE REQUEST
AB

User Input Signals

2
‘

The logical OR of these two signals is used to set the CYCLE

flip-flop in the interface. CYCLE initiates the sequence of performing a data transfer operation provided that the interface
has been given a data transfer command. Either of these two
inputs should be pulsed positve for 100 ns minimum duration to
initiate a bus transfer sequence. CYCLE sets on the +3 V to

ground transition of the input.

STO0-STO07

Device Status Bits 0:7. The signal levels applied to these lines

appear as bits 00:07 of
ground = logical 0.

ERROR

RHFS. Levels are: +3 V = logical 1;

User-defined error bit. The level applied to this line appears as
bit 10 in the interface status register (RHIS). Setting this bit will

cause ATA and ERR to set and will cause an interrupt in the
processor if the interrupt enable is set.

ATO-ATS3

User-defined signals that can
be used to cauée an interrupt in

the processor without indicating an error condition.
DPA IN LO
DPA IN HI

Data Parity In - Implemented by the user to provide parity with
incoming data to the interface. Parity checking on the input
data is performed in the interface if IPI (Input Parity Inhibit) is
not set (odd parity).

IPINH

Input Parity Inhibit - Asserted by the user to inhibit parity
checking on data which it transfers into the interface.

*Maximum loading for each user input signal = 1 each

Table. C-2

Name
DATI17 OUTDAT00 OUT

No. of
Signals
18

User Output Signals

Description

Data output to user device. These signals represent the contents
of the interface output buffer which is loaded when the interface
performs a write cycle. Levels are: +3 V = logical 1; ground =
logical 0. All lines cleared to 0 by INIT.

INIT

This line is true (+3 V) whenever the Massbus is initialized
which occurs on power up, power down, console start, REST
instruction, or when an interface clear command is received by
the interface.

F00-F07

These 8 lines are derived from the function bits in RHFS (bits

READY

This signal is derived from the Interface Ready (IRY) bit in
RHIS (bit 7). This signal is true (+3 V) after INIT; it becomes
false (ground) when the GO bit is loaded with a data transfer
command and it becomes true again when word count over-

8-15) and are user-defined to specify device operation. Levels
are: +3 V = logical 1; ground = logical 0. Clear by INIT.

flows or an error condition develops.
BUSY

'END CYCLE

BUSY indicates that data transfer sequence is in progress.
BUSY is true (+3 V) when CYCLE is set and becomes false
(ground) when the data transfer cycle is complete.
This pulse is a 100 ns positive pulse that indicates the bus cycle
is complete.

USER GO

This signal is a 1 us positive pulse that results from setting the
GO bit in RHCSI1 with a data transfer command. Indicates that
a new operation is to be performed.

READ

Indicates that a read command has been given to the interface
by the controller; that is, the processor is requesting data to be
input to the interface.

WRITE

Indicates that a write command has been given to the interface
by the controller; that is, the processor is requesting to output
data to the interface. Normally, the negation of the READ signal may also be used to indicate a write command.

DPA OUT LO
DPA OUT HI

DATA PARITY OUT indicates the parity of the data in the
output data buffer (odd parity). DPA OUT LO is for the low
byte and DPA OUT HI is for the high byte.

READ OPERATION

CYCLE REQUEST

BUSY

___J

DELAY

(MIN = 150 NS, MAX = 20 uS

'——S‘,—IL

END CYCLE H (100 NS)

DATA STROBED BY INTERFACE. DATA MUST BE STABLE 100 NS _/

PRIOR TO THE NEGATIVE TRANSACTION OF CYCLE REQUEST.

WRITE OPERATION

CYCLE REQUEST

”

BUSY

DELAY

fih

(MIN
= 150 NS, MAX
= 20 uS

(

END CYCLE H (100 NS)

NEW DATA RECEIVED__/
FROM CONTROLLER

DATA GUARANTEED STABLE
MR-0848

Figure C-1

Read and Write Timing Diagrams

If the CYCLE request is received before the completion of the previous cycle, the request will be stored
and the new data transfer cycle will begin as soon as the previous cycle is finished. This allows the user
device to overlap cycles so that the interface will be primed to begin a second cycle immediately upon
completion of the first cycle. If a CYCLE REQUEST is received before a valid data transfer command, it will also be stored and acted on as soon as the command has been received from the procesSOr.

The beginning of a new data cycle is indicated by the low-to-high transition of the BUSY signal. If
both conditions 1 and 2 above are true, the cycle will begin immediately following the negative transition of CYCLE REQUEST. The user device must hold the data lines stable until the cycle begins
(positive transition of BUSY signal). At this point, the interface has strobed in the data lines and there
is no further need for the user device to hold the lines stable while the interface completes the transfer.
The completion of the data transfer will be indicated by the negative transition of the BUSY signal and
the assertion of the END CYCLE signal. The BUSY signal will be cleared as soon as the END
CYCLE signal is asserted.

C.1.2.2 Write Operation - When a write command has been received from the processor, the negation of either of the CYCLE request signals will have basically the same effect as in a read but the
direction of the transfer will be opposite. (See Figure C-1.)

As in a read operation, if the CYCLE REQUEST is received before it can be processed by the interface, it will be stored as soon as a new data transfer cycle can be started.
The beginning of the data transfer cycle is indicated by the low-to-high transition of the BUSY signal.
The data from the previous transfer cycle will remain valid on the DATA OUT (0:15) lines until the
new data is received from the Massbus controller (approximately in the middle of the data cycle). The
new data will be presented to the user device on the DATA OUT lines along with an optional parity bit
as soon as the data transfer cycle
is complete (assertion of END CYCLE and clearing BUSY). The
data lines will be stable as soon as BUSY clears. The user device may then delay initiating another
cycle until it has processed the data or it may immediately initiate another cycle if the data is strobed
well within the next 250 ns. Figure C-1 shows the timing diagram of the read and write operations.
NOTE
BUSY will set immediately following the negative
transition
of CYCLE REQUEST only if the interface has completed the previous data transfer operation and the READY signal is reset.

C-5

DTRO1/DRO1 CHANNEL INTERFACE

SUBSYSTEM TECHNICAL MANUAL

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