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Document:	PDP-8/L Maintenance Manual Volume 1
Order Number:	DEC-8L-HR1B-D
Revision:	0
Pages:	82
Original Filename:	DEC-8L-HR1B-D_8LmaintVol1.pdf

OCR Text

DEC-8/L-HR1B-D

PDP-8/L
- MAINTENANCE MANUAL
VOLUME |

DIGITAL

EQUIPMENT

CORPORATION

MAYNARD,

MASSACHUSETTS

st Printing October 1968
2nd Printing May 1969

3rd Printing (Rev) December 1969
4th Printing July 1970

The material in this manual is for information purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CONTENTS
Page

CHAPTER 1
INTRODUCTION AND DESCRIPTION
Introduction

1-1

Description

1-1

Pertinent Documents

1-1

CHAPTER 2

w—

Environmental Requirements

2-3

Internal Option Installation

2-3

Interface

2-3

1/0O Bus

2-3

2-1

1/O Cables

2-4

Space Requirements

Cable Connectors
Interface Connections

External Equipment Cable Locations

—l

Bus Driver/Receiver Modules
M111/M906 Positive Input Circuit

HWDN

DNDDDND
NN
DN
N
N
DN
D
DN
N
N

\l.\l\l\l\10~01-h-h-h-l=-wl\>

INSTALLATION

M516 Positive Bus Receiver Input Circuit

Mé623/M906 Positive Output Circuit

2-7

Mé60 Bus Driver Output Circuit

2-7

CHAPTER 3
OPERATION

w
w

Teletype

3-4

3-5
3-6

3-4

Teletype Loading Procedures

3-1

Manual Loading Procedures

3-1

Operating Procedures

Computer

Controls and Indicators

Off-Line Teletype Procedure

L E.5.4

CONTENTS (Cont)
Page

CHAPTER 4
THEORY

Section I:
4.1

Block Diagram Discussion
Registers

4-1

4.1.1

Accumulator (AC)

4-1

4.1.2

Link (L)

4-1

4.1.3

Program Counter (PC)

4-1

4.1.4

Memory Address Register (MA)

4.1.5

Memory Buffer Register (MB)

4.1.6

Sense Register (Sense)

4.1.7

Instruction Register (IR)

4.1.8

Switch Register (SR)

4.2

Major Register Gating Network

4.3

Timing and Control Elements

4.3.1

Timing Elements

4-3

4.3.2

Control Elements

4-3

4.4

Input/Output

4-3

4.5

Memory

4-3

4.5.1

Core Array

4-3

4,5.2

Memory Control

4-3

4.5.3

Address Selection

4-3

4.5.4

Inhibit Drivers

4.5.5

Sense Amplifiers

Section II:

4-4

General Theory

4.6

Time States/Time Pulses

4-4

4.7

Major States

4-4

4.8

Intemal Data Flow

4-4

4.9

Instructions

4-4

4.9.1

Memory Reference Instructions

4-5

4,9.2

Augmented Instructions

4-6

4.10
4.10.1

Program Interrupt
Instructions

4-11

CONTENTS (Cont)
Page

Section III:

Detailed Memory Theory

4.11

Overall Memory Theory

4-11

4,12

Memory Operation

4-12

4,12.1

Memory Control

4-12

4.12.2

Read/Write

4-12

4.12.3

Address Selection

4-16

Section 1V:

4.13

Detailed Processor Theory

Timing

4-19

4.13.1

Manual Function Timing Generator

4-19

4.13.2

Manual Operations

4-19

4.13.3

Time States

4-21

4,14

1/O Timing

4-21

4.15

Memory Protect

4-24

4,16

Major States

4-25

4,17

Intemal Data Flow

4-26

4.17.1

Source

4-27

4.17.2

Route

4-27

4.17.3

Destination

4-27

4,18

Operating Instructions

4-28

4.18.1

Instructions

4-29

4.18.2

Memory Reference Instructions

4-29

4.18.3

Direct/Indirect Addressing

4-34

4.18.4

Augmented Instructions

4-35

CHAPTER 5
MAINTENANCE

5.1

Equipment

5.2

Programs

5.3

Preventive Maintenance

5.3.1

Weekly Checks

5.3.2

Preventive Maintenance Tasks

5.4

Corrective Maintenance

5.4.1

Preliminary Investigation

5.4.2

System Troubleshooting

CONTENTS (Cont)
Page

5.4.3

Logic Troubleshooting

5.4.4

Circuit Troubleshooting

5.4.5

Repairs and Replacement

5.4,6

Validation Tests

5.4.7

Recording

5.5

Adjustments

5.5.1

Power-Up Threshold Adjustment

5.5.2

Memory Alignment Procedure

5.6

ASR33 Teleprinter and Control Maintenance

5-11

5.6.1

Equipment

5-11

5.6.2

Programs

5-12

5.6.3

Preventive Maintenance

5-12

5.6.4

Corrective Maintenance

5-15

ILLUSTRATIONS
1-1

PDP-8/L

2-1

Table Top PDP-8/L Dimensions

2-1

2-2

Rack-Mounted PDP-8/L

2-2

2-3

Chassis-Track Specifications

2-2

2-4

Rack-Mounted PDP-8/L Frame with Track-Slide Specifications

2-3

2-5

1/O Bus Configuration

2-4

2-6

1/0 Signal Connections

2-5

2-7

Cable Location Convention on Option Mounting Panels

2-6

2-8

M111/M906 Logic Diagram

2-6

2-9

Typical M516 Positive Bus Receiver Input Circuit

2-6

2-10

Typical M623/M906 Positive Output Circuit

2-11

Typical M660 Bus Driver Output Circuit

2-7

3-1

PDP-8/L Front Panel

3-1

3-2

Teletype Model ASR33 Console

3-3

4-1

System Block Diagram

4-2

Memory Reference Instruction Bit Reference

4-5

4-3

IOT Instruction Bit Assignments

4-6

4-4

Group 1 Operate Instruction Bit Assignments

4-7

ILLUSTRATIONS (Cont)
Page

4-5

Group 2 Operate Instruction Bit Assignments

4-9

4-6

Memory System, Block Diagram

4-13

4-7

Memory Timing Diagram

4-14

4-8

Simple Core Memory Plane

4-9

Memory Address Selector or Read/Write Current Control

4-17

4-10

Manual Function Timing Diagram

4-18

4-11

System Timing Diagram

4-22

4-12

1/O Timing Diagram

4-23

4-13

Data Flow

4-28

4-14

Direct and Indirect Address Selection, Simplified Flow Chart

4-36

5-1

IC Location

5-6

5-2

IC Pin Location

5-6

5-3

Memory Control Waveforms

5-9

5-4

Representative Read/Write Current Waveforms

5-10

5-5

Representative Inhibit Current Waveforms

5-12

5-6

Representative Sense Amplifier Waveforms

5-14

5-7

Teletype Connections

5-16

5-8

Teletype Signal Waveform and Bit Relationship for the Character "U"

5-17

4-15

TABLES
3-1

Computer Controls and Indicators

3-1

3-2

Teletype Controls and Indicators

3-4

3-3

Readin Mode Loader Program

4-1

Example of Register Contents During JMS Instruction

4-33

Maintenance Equipment

5-1

5-2

Maintenance Programs

5-2

5-3

Power Supply Specifications

5-4

Teletype Maintenance Tools

5-13

5-5

Teleprinter Maintenance Programs

5-13

vii

PDP-8/L MAINTENA
MANUAL
NCE
VOLUME
1

Figure

1-1

PDP-8/L

CHAPTER 1
INTRODUCTION AND

1.1

DESCRIPTION

INTRODUCTION

quotient in the accumulator, and a 12-bit remainder
in core memory
.

This manual covers installation, operation, theory,
and maintenance of The Programmed Data Processor -

8/L (PDP-8/L).

Flexible, high-capacity, input/output capabilities of

It is the intent of this manual to

the computer allow it to operate a variety of periph-

provide the field service engineer or maintenance

eral equipment. In addition to the Teletype keyboard/printer and perforated-tape reader/punch
equipment supplied with a basic PDP-8/L, the system

technician who is familiar with digital logic circuitry
with the information he needs to install and maintain

a PDP-8/L system.

The bulk of the manual assumes

that the reader is conversant with DIGITAL's system

of logic notation.

If this is not the case, the reader

should refer to applicable sections in the appendix
for a description.

can operate a number of optional devices, such as a

high-speed perforated-tape reader and punch, card
reader, line printer, analog-to-digital converters,

cathode-ray~tube displays, magnetic-drum systems,
magnetic disk-file systems, and magnetic-tape equipment.

1.2

Programmed Data Processor-8/L (PDP-8/L) (see Frontispiece) serves as a small-scale general-purpose computer that functions as an independent information-

handling facility in o large computer system, or as
the control element in a complex processing system.

The PDP-8/L is a one~address, 12-bit, fixed-wordlength, parallel computer using two's complement
Normal cycle time of the 4096-word

(referred to as 4K) random-access, magnetic core
memory is 1.6 ps.

The

computer itself needs no modification for the addition

The Digital Equipment Corporation integrated-circuit

arithmetic.

Instruments or equipment of special design can

also be connected into the PDP-8/L system.

DESCRIPTION

of these peripheral devices.

The PDP-8/L is completely self-contained, and, under
normal conditions, requires neither special power
sources nor rigidly controlled environmental conditions.

A single source of 105-130 Vac, 47-63-Hz,

single=phase power permits internal power supplies to
produce all required operating voltages. M-=Series*
modules, using TTL~type integrated-circuit packs,
ensure reliable operation in ambient temperatures between +10°and +55°C.

An additional 4K of memory may

be available to the system simply by adding an MC

8/L memory expansion and control unit.

1.3

PERTINENT DOCUMENTS

The following documents serve as source material and
Standard features of the system include indirect addressing, facilities for instruction skipping and pro-

complement the information in this manual:

gram interruption as functions of input/output device

conditions, and optional high-speed information

by DIGITAL, which notes the function and speci-

Logic Handbook, C-105 (1969 edition) printed

transfers into peripheral mass memory devices via a

fications of the M-Series modules and module ac-

cycle stealing data break.

cessories for the PDP-8/L.

The PDP-8/L performs one addition in 3.2 ps (with

PDP-8/L Users Handbook.

tation rate of 312,500 additions per second to be

Technical Manual, Automatic Send and Re-

achieved.

ceive Sets (ASR) (Bulletin 273B Volumes 1 and 2).

one number in the accumulator), permitting a compuIt performs subtraction in 6.4 s (with

the minuend in the accumulator) using two's complement addition.

Multiplication takes approximately

This manual covers operation and maintenance of
the Teletype unit.

384 s, using a subroutine that operates on twosigned
12-bit numbers to produce a 24~bit product, leaving
the 12 most significant bits in the accumulator.

Divi-

sion of two signed 12-bit numbers takes approximately

*M Series is a registered trademark of Digital Equip-

490 ps, using a subroutine that produces a 12-bit

ment Corporation.

4, Parts, Model 33 Page Printer Set (Bulletin
1184B) contains an illustrated parts breakdown to
serve as a guide to disassembly, reassembly, and
ordering replacement parts for the Teletype unit.

5. Instruction List F-816, printed by DIGITAL.
This is a shirt-pocket list of all memory reference
instructions, all augmented instructions, the most
common IOT instructions, and the ASCII code used
with many 1/O devices.

6. Instruction manuals and MAINDEC programs
for appropriate input/output devices are prepared
by DIGITAL.

Digital Program Library Documents. Perforated program tapes and descriptive matter for the
Program Assembler Language (PAL III), FORTRAN,
FOCAL, utility subroutines, and the maintenance
programs (MAINDEC) prepared by DIGITAL are

available to PDP-8/L users.

The list of programs

currently in the library and available is provided
in Appendix D.

CHAPTER 2
INSTALLATION

This chapter contains installation and interface information for the PDP-8/L and its options.

the teletype to be placed near the computer.

2.1

Figures 2-1 through 2-4 provide PDP-8/L. dimensions
for both tape top and rack-mounted configurations.

If DEC cabinets are not purchased, the cabinets at

the installation should provide for access to all doors
and panels for maintenance.

The PDP-8/L is available in either the table top or
rack=mounted configuration. The rack-mounted configuration and peripherals may be purchased com-

pletely installed in DEC cabinets or unmounted for

The rack-mounted configuration is attached to the
cabinet on sliding chassis tracks. There are two sets
of tracks; one set for each frame side. The track sections interlock; one section being bolted to the cabinet and the other bolted to the logic main frame.

Figure 2-3 shows the chassis frack specifications. A
rear view of the rack-mounted PDP-8/L and track-

slide specifications is illustrated in Figure 2-4.

installation in a customer cabinet. The standard
teletype automatic send receive (ASR) set requires a
floor space of approximately 22-1/4 in. wide by

Figure 2-1 illustrates the table top dimensions, and
Figure 2-2 illustrates the rack-mounted PDP-8/1..

Figure 2-1

Table top PDP-8/L Dimensions

Hlw

SPACE REQUIREMENTS

18-1/4 in. deep. The teletype signal cable requires

ISTES

Figure 2-2

Rack-Mounted PDP-8/L

AUTOMATIC LOCK OUT

QUICK DISCONNECT
RAISE MANUAL RELEASE ARM

AUTOMATIC CHANNEL STOP
1 _3—..

’

2 45/64 "

TO REMOVE OR RETURN CHASSIS

1" FROM
TOP OF CHASSIS

Y BASIC CABINET
1

':(

21 78

CHASSIS

—

pil=y

hatl Il

N.
y

25/32

SIDE VIEW OF
MOUNTING HARDWARE

Figure 2-3

Chassis=Track Specifications

2-2

»
"]

¢ OF MOUNTING HOLES

¢ OF SLIDE

5/32"

REAR VIEW OF
MOUNTING HARDWARE

'«

:— FRONT PANEL

Y CHASSIS

A |

1 174"
TQ OF SLIDE

t
1/4"x 716"
SLOT

TYP

Figure 2~4

Rack-Mounted PDP-8/L Frame with
Track=Slide Specifications

2.2

ENVIRONMENTAL REQUIREMENTS

The PDP-8/L is designed to operate between g20° and

130°F (0°and 55° C). The life~expectancy of the
system, however, can be extended if the temperature
at the installation site is maintained at between 70°

ing for the locations of each module of all internal
options.

If an option involves an external device,

dress connecting cables through the opening at the

rear of the PDP-8/L to the option.

and 85°F (between 21° and 30° C).

During shipping or storing of the system, the ambient
temperature should be maintained within 32° to

130° F to prevent damage to the system. Although
all exposed surfaces of Digital cabinets and hardware

2.4

INTERFACE

2.4.1

1/O Bus

are treated to prevent corrosion, exposure of systems

to extreme humidity for long periods of time should

The PDP-8/L uses a series /O bus system to permit

For external options, forced air cooling should be used
if more than a few module-filled H?11 mounting pan-

devices and the 8/L without modifying the computer
wiring. In a series 1/O bus, the computer sends all
1/O signals to the first device. This device uses the

els are needed.

pertinent signals and sends all of the signals to the

be avoided.

interface connections to be made between external

The low power consumption of Mseries modules results in approximately 15W dissipation
in a typical H?11 mounting panel of 64 modules. If

of cables to be connected to the PDP-8/L and two

only one or two panels of logic are used, convection

sets connected to each device:

cooling is sufficient.

1/O bus signals from the computer itself or the previ-

2.3

INTERNAL OPTION INSTALLATION

The installation of the internal options involves the
addition of the logic modules in the proper locations.
WHEN INSERTING OR REMOVING ANY MODULES

next I/O device (see Figure 2-5). This allows one set
one receiving the

ous device, and one passing the 1/O bus signals to
the next device. The data break cables are used in
the same manner.

When the equipment location does not make series bus
connections feasible, or when cable length becomes

IN THE LOGIC FRAME THE 8/L SYSTEM MUST BE

excessive, additional interface connectors can be

TURNED-OFF.

provided near the computer.

Refer to the module utilization draw-

DEVICE
2

DE\?ICE

___________
rmmmm
e
—
-y

—
PDP

8L
©

110 casLes

©&-t+—=—=-- —
DATA

BREAK

10 CABLES

IO CABLES TO

——% ADDITIONAL DEVICES
DATA BREAK CABLES

DATA

BREAK

TO ADDITIONAL DEVICES

CABLES

Figure 2-5

I/O Bus Configuration
are used with flexprint cable, The M904 connectors
terminate the cooxial cable ends.

1/O Cables

2.4.2

Eighteen conductor coaxial cables or flexprint cables

Both connectors are wired double-sided with 36 pin
contacts. Each connector terminates two coaxial or

with either M904 or M903 cable connectors, respec-

tively, provide signal connection between the computer and optional equipment. These cables are connected by plugging the connectors into standard FLIP

flexprint cables. The conductors from both types of
cables terminate at the connector pin locations indicated below. Each signal conductor is isolated by a
ground conductor. The connector pin locations for
signals are: B1, D1, E1, H1, J1, L1, M1, P1, S1,
and D2, E2, H2, K2, M2, P2, S2, T2, V2. The
ground pin locations on each connector are: Al, C1,

CHIP module receptacles. Use of coaxial cable protects systems from radiated noise and cross talk between individual lines. Coaxial cable used between
the PDP-8/L and options has the following specifications:

F1, K1, N1, R1,T1, and C2, F2, J2, L2, N2, R2,
uz2.

13.75 pf/ft approximately (unterminated)

Z0 =95Q +5%

124 Nhy/ft approximately

=0.095 ohm per foot nominal

2.5

All interface connections to the PDP-8/L are made at

assigned module receptacle connectors in the mounting
frame. Capital letters designate horizontal rows of
modules within a mounting frame from top to bottom,
i.e., A is the first row, B is the second row, etc.
Module receptacles are numbered from left to right as
viewed from the wiring side (right to left from the
module side). Terminals of a connector or module are
assigned capital letters from top to bottom omitting
G, I, O, and Q. Double sided connectors or modules are used with the suffix number "1" designating
the one side and suffix number "2" designating the

Y =79% of velocity of light, approximately

(~ 1.5 ns/ft.).

The flexprint cable is generally used because of its

high flexibility. The conductors are #30 AWG flat

copper
.

The maximum length of 1/O cabling, from the PDP8/L to the last device is 50 ft. This can be 50 ft. of
coax or a combination of coax and flexprint, inwhich
case the flexprint cannot exceed a total length of

other side.

15 ft.

2.4.3

Figure 2-6 shows the signals and pin locations at each
connector block. The 1/O cable connectors are in-

Cable Connectors

serted into these locations to form the 1/O bus. The

arrows associated with each signal show the signal
direction. The arrows pointing to the connectorblock

The M903 and M904 cable connectors are used with
the cable types described above.

INTERFACE CONNECTIONS

M903 connectors

2-4

—ja—o

JI|

———o—o

jae——

Mi
P!

}a—— DATA

Ll
M

——fo—
—jo—

la—— DATA

—jo—

le—— DATA

S| —jo——

la—

DATA
le—— DATA

— je——
E2 —jo—

——

K2
M2

—— 3 CYCLE
M—— CA INCREMENT
—— BWC OVERFLOW

DATA

$2 —————e—— EXT DATA
T2
—

——j&¢—— [INPUT BUS 0@

DI —j&—— NPUT BUS @1
E | ——}&—— INPUT BUS
H| ———#¢—— |[NPUT BUS
J | ———— INPUT BUS
LI —4&— |(NPUT BUS

02
03
04
@5

M| —j&—— INPUT BUS 06

——Jea—— (NPUT BUS @7
S| -—:: INPUT BUS @8
D2 ——]
INPUT BUS 09
E2 ——J&—— INPUT BUS |0

H2 ———j&—— INPUT BUS
K2 ——&—— 1/0 SKIP
M2 —Je—— INT RQST

ADD

__}UNUSED

D 34

e——

-—

INCREMENT
: MEMORY
B INITIALIZE

D 35
Bi

————» BMBOQO (I)

DI ——1—» BMBQI (1)
EIl ———» BMBQ2 ()
HI ——+——» BMB@3 ()
J | ———1—» BMBO3(l)
L| ————» BMB24(Q)

M| ——1—» BMB@4(l)
Pl

————» BMB25
(@)

———f—= BMBO5(I)
D2 ——}—» BMBO6(0)
E2
> BMBO6
(1)

H2
K2

—— BMBQ7 (@)
——» BMB@7(l)

P2 ———Je—— AC CLEAR
S2 ——+—» B RUN (0)

M2
*-—— DATA IN
p2
-— B BREAK (0)
$2 ——4—» B ADD ACCEPTED (1)

<KAVIVTXIMOWLWIOUTrcecImMow
PPROPOPPOPNONNON
-~ —— ——— =)

DATA

2
>

———fe—

——» BMBQ8 (@)

—» BMB@8 (1)

S?2
T2

—— BMB®@9
()
—— BMB 1@ (1)

ve2

Figure 2-6

:“

OO0 00| O|0|0|00|o|o

DATA

le—— DATA

la—— DATA

—-|Oj0lm|~ [l
el alcalrol= S

le——

J i

—_

B> 2> > p| > |22
>

Bl ——ja——o
DI ——tfa——

C 36

}¢—— DATA 00
le—— DATA 01

C 35

B!
DI

— BMB || (I}

—® B

INITIALIZE

1/0O Signal Connections

indicate signals coming to the computer from the 1/O

option mounting panel are wired in parallel with the

connector block indicate signals from the computer to

the I/O cabling to the next device, the bottom slots

bus.

Similarly, the arrows pointing away from the

external devices through the 1/0O bus.

2.6 EXTERNAL EQUIPMENT CABLE LOCATIONS
The 1/O cables connected within the computer at the
locations specified by Figure 2-6 are generally con-

top module slot locations 1 through 5.

To continue

are used.

2.7

BUS DRIVER/RECEIVER MODULES

The following paragraphs describe each bus driver
and receiver module type shown on Engineering

nected on an option mounting panel as indicated in

Drawing BS-8L-0-10.

Figure 2-7.

tion and drive for signals between the processor and

This illustration shows the DEC conven-

tion for cable terminations.

These circuits provide isola-

1/O cabl es.

Module slot locations 1 through 3 (looking at the
wiring pin side) in the A row of an option mounting

panel are reserved for program interrupt cable con-

nections in (or out).

2.7.1

MI11/M906 Positive Input Circuit

Module slot locations 4 and 5

are reserved for Data Break cable connections in

(or out).
Module slot locations 1 through 5 in the B row of the

Figure 2-8 shows the M111/M906 logic configuration.
The M111 Inverter module is used in conjunction with
the M906 Cable Terminator module which clamps the
input to prevent excursions beyond +3V and ground.

BMBOO | ACO0 BUS
to
to
AC11 BUS
BMB11

BACO0
to
BACIHI

f .(F

DATA ADDOO
to
DATA ADDI11

DATAO00
to
DATAII

BIOP 1, 2, 4

SKIP BUS

BRK RQST

3 CYCLE

BTS 3, 1

INT RQST BUS

DATA IN

CA INCREMENT

B INITIALIZE

AC CLEAR

MB INCREMENT

EXT DATA ADD

B ADD

B WC

B RUN

ACCEPTED

CONT BUS

’

OVERFLOW

B BREAK

B INITIALIZE

SAME ASSIGNMENTS AS ABOVE

Figure 2-7 Cable Location Convention on Option Mounting Panels

The incoming DATA and DATA ADD signals for data

2.7.2 M516 Positive Bus Receiver Input Circuit

inverted and isolated from the 1/O cables through
this logic.

Figure 2-9 shows the M516 logic configuration. Six
four-input NAND gates with overshoot and undershoot

break and other signals (Drawing BS-8L-0-10) are

[ 810 oUTPUT SIGNAL TO PROCESSOR 1

|
|
I

M1ttt

{16 INVERTERTS)

M906

(18 CIRCUITS)

| atO

‘

[p——— VN +5V

810 0UTPUT SIGNAL T PROCESSOR |

|S
|

|
|
I

B10 PO(SITIVE BUS INPUT SIGNAL
FROM EXTERNAL DEVICE)

USED

INTERNALLY

|
|

+5V

POSITIVE BUS INPUT SIGNAL
(FROM EXTERNAL DEVICE)

S _

Figure 2-9

Figure 2-8

M516

(SI1X GATES)

|
|
|

M111/M906 Logic Diagram

Typical M516 Positive Bus Receiver

Input Circuit
2-6

clamp on one input of each gate. The 1/O SKIP gate
(Drawing BS-8L-0-10) is an example of M516 application.

level. The ACO0 through AC11 signals (Drawing
BS-8L-0-10) are examples of M623 application.

The input signals applied to pins B1, C1,

2.7.4 M660 Bus Driver Output Circuit

and D1 are from internal options. With the I/O SKIP
gate, these signals are PWR SKIP, RDR SKIP, and

Figure 2-11shows the M660 logic configuration. This

TT SKIP.

bus driver circuitry provides low impedance 100 ohm
terminated cable driving capability, using M-Series
levels, or pulses of duration greater than 100 ns.
Each output can drive +5 mA at the high level and
sink 20 mA at the low level, in addition to the term-

2.7.3 M623/M906 Positive Output Circuit
Figure 2-10shows the M623/M906 logic configuration.
The M623 Bus Driver module contains 12 negative
NAND circuits. Used with the M906 Cable Termin=ator module, the output is clamped to prevent excursions beyond +3V and ground.

ination current required by the G717 Termination

module.

+5 mA at the high level and sink 20 mA at the low

POSITIVE

(TO

BUS

OUTPUT

SIGNALS

EXTERNAL DEVICE)

IOP 1, IOP 2,

IOP 4, TS 3 and TS1 (Drawing BS-8L-0-10),

M906

|(1BCIRCUITS)

The M660 module is used in the PDP-8/L

for the following output signals:

The output can drive

POSITIVE BUS OUTPUT SIGNAL
(TO EXTERNAL DEVICE)

M660

{3 CIRCUITS)

OUTPUT
FROM

Figure 2-10

SIGNAL

PROCESSOR

Figure 2-11
Typical Mé60 Bus Driver Output Circuit

Typical M623/M906 Positive Output Circuit

2-7

CHAPTER 3
OPERATION

This chapter contains operating information for the
PDP-8/L and the ASR33 Teletypewriter.

regarding the controls and indicators of fHe PDP-8/L

Operating

and the ASR33 Teletypewriter.

information for the peripheral input/output devices
is contained in their respective manuals.

3.1.1
3.1

CONTROLS AND INDICATORS

The following paragraphs contain detailed information

Computer

Figure 3-1 shows the location of the controls and
indicators of the PDP-8/L, and Table 3-1 describes

their functions.

MEMORY ADDRESS

S———

IHBTRUCTION

MEMORY BUFFER

WMAJOR STATES

ACCUMULATOR

Figure 3-1

1IN

PAR

PROT

RUN

PDP-8/L Front Panel

Table 3-1

Computer Controls and Indicators
Control or Indicator

OFF-POWER-PANEL LOCK switch

Function

In OFF position, all power is removed from machine; in POWER

position, the machine operates normally, in PANEL LOCK position
power is applied and all manual controls except the switch register
are disabled.

Table 3-1 (Cont)
Computer Controls and Indicators
Control or Indicator

MEM PROT switch

DATA FIELD switch

Function

When up, protects last page of memory (locations 7600, to 7777 )

from modification; when off, normal read/write operation prevails.
Determines which core memory field (if extra 4K has been added) is
being addressed for data storage and retrieval .

INST FIELD switch

Determines which core memory field (if extra 4K has been added) is
being addressed for instruction storage and retrieval .

EA indicator

Indicates when extended memory is being addressed.

MEMORY ADDRESS indicators

Indicates address of memory that is being operated upon.

MEMORY BUFFER indicators

Indicates content of above address.

ACCUMULATOR indicators

Indicates contents of AC.

LINK indicator

Indicates contents of L.

SWITCH register

Provides a means for manually setting a 12-bit word into the machine.

INSTRUCTION indicators

Indicates contents of Instruction Register.

MAJOR STATES indicators

Indicates which of the six major states (Fetch, Execute, Defer,
Word Count, Current Address, or Break) the processor is in.

ION indicator

Indicates that interrupt system is enabled.

PAR indicator

Indicates (when parity option is installed) a parity error.

PROT indicator

Indicates that a memory protect violation has been detected.
Machine will halt with this condition.

RUN indicator

Indicates RUN flip=fiop is set.

LOAD ADDR switch

Transfers contents of switch register into PC and into MA.

START key

Starts the program by turning off the program interrupt circuits,
clearing the AC and L, setting the Fetch state, and starting the
central processor timing.

CONT key

This key sets the RUN flip-flop to continue the program in the state
and instruction designated by the lighted console indicators, at the
address currently specified by the PC if SING STEP key is not on.

STOP key

Causes the RUN flip=flop to be cleared at the end of the instruction in progress at the time the key is pressed.

Table 3-1 (Cont)
Computer Controls and Indicators
Control or Indicator

Function

SING STEP switch

Steps program one cycle-at=time so that operator can observe contents of register in each major state.

This key transfers the content of core memory at the address specified

EXAM key

by the content of MA, into MB.

The content of the MA is then in-

cremented by one to allow examination of the contents of sequential
core memory addresses by repeated operation of the EXAM key.

The

major state flip=flop register is cleared.

This key transfers the content of switch register into MB and core

DEP key

memory at the address specified by the current content of MA.
major state flip=flop is cleared.

The

The contents of PC and MA are then

incremented by one to allow storing of information in sequential core

memory addresses by repeated operation of the DEP key.

Figure 3-2

Teletype Model ASR33 Console

3-3

Figure 3-2 shows the location of the ASR33 Teletype-

as the programming and use of the computer become
more sophisticated, they are valuable in preparing
the initial programs and learning the function of ma-

writer controls and indicators, and Table 3-2 is a

chine input and output transfers.

3.1.2

Teletype

list of the ASR33 controls and indicators with an explanation of their functions.

3.2 OPERATING PROCEDURES

All of the procedures described in the following paragraphs require that the OFF-POWER-PANEL LOCK
switch be set to POWER.

3.2.1

Many means are available for loading and unloading
PDP-8/L information. The means used depend upon
the form of the information, time limitations, and the
peripheral equipment connected to the computer. The
following procedures are basic to any use of the PDP8/L. Although these procedures are used infrequently

Manual Loading Procedures

Programs and data can be stored or modified manually
by means of the facilities on the operator console.
The chief use of the manual data storage facility is to
load the Readin Mode Loader program into the computer core memory. The Readin Mode Loader (RIM)

Table 3-2

Teletype Controls and Indicators
Control or Indicator

REL. pushbutton

Function

Disengages the tape in the punch to allow tape removal or tape
loading.

B. SP. pushbutton

Backspaces the tape in the punch by one space, allowing manual
correction or rubout of the character just punched.

OFF and ON pushbuttons

Control the use of the tape punch with operation of the Teletype
keyboard/printer.

START/STOP/FREE switch

Controls use of the tape reader with operation of the Teletype. In
the lower FREE position, the reader is disengaged and can be loaded
or unloaded. In the center STOP position, the reader mechanism is
engaged but de-energized. In the upper START position, the reader
is engaged and operated under program control .

Keyboard

Provides a means of printing on paper in use as a typewriter and

punching tape when the operator presses the punch ON pushbutton.

The keyboard also supplies input data to the computer when the LINE/
OFF/LOCAL switch is in the LINE position.
LINE/OFF/LOCAL switch

Controls application of primary power in the Teletype and controls
data connection to the processor.

In the LINE position, the Teletype

is energized and connected as an I/O device of the computer.

the OFF position, the Teletype is de-energized. In the LOCAL
position, the Teletype is energized for off-line operation, and signal
connections to the processor are broken. Only line use of the Teletype requires that the computer be energized through the POWER
switch if primary power for the Teletype is supplied from a source
other than the outlet at the back of the computer.

is a program used for loading into the PDP=8/L other

programs that have been assembled on perforated tape
in RIM format.

This program and the RIM tape format

are described in the PDP-8/L Users Handbook (see
Small Computer Handbook, C-800, 1968 edition) and
in Digital Program Library descriptions. The RIM program is also listed in Table 3-3 for rapid reference
and can be used as an exercise in manual data storage.
To store data manually in the PDP-8/L core memory
proceed as follows:

Set the bit switches of the SWITCH REGISTER
(SR) to correspond with the address bits of the first

word to be stored.

To check the contents of an address in core memory,
set the address into the MA as in step a; then press

the EXAM key. The MEMORY BUFFER lights indicate
the contents of the address. The contents of the MA
are incremented by 1with the operation of the EXAM
key, so that the contents of consecutive addresses can
be examined by repeated operation of the EXAM key
after the original (or starting) address is loaded. Any
address can be modified by repeating steps a and b.

3.2.2

Teletype Loading Procedures

Press the LOAD ADDR key and
observe that the address specified by the SR is held

under program control.

in the MA, MEMORY ADDRESS.

Loader stored in core memory allows RIM format tapes

Information can be stored or modified in the computer
For example, having the RIM

to be loaded as follows.

Setthe SR to correspond with the data or in-

struction word to be stored at the address just set
into the MA. Lift the DEP key and observe that

Set the Teletype LINE/OFF/LOCAL switch to
the LINE POSITION,

the MB, and hence the core memory, holds the

word set by the SR.

Load the tape in the Teletype reader by setting

the START/STOP/FREE switch to the FREE position,

Observe that the contents of the MA have been incremented by 1 so that additional data can be stored at

releasing the cover guard by means of the latch at
the right, loading the tape so that the sprocket

sequential addresses by repeated SR setting and DEP
key operation.

wheel teeth engage the feed holes in the tape,
closing the cover guard, and setting the switch to

Table 3-3
Readin Mode Loader Program

Address

Ccc?nc::nlf

Tag

7756,

6032

BEG,

7757,

6031

KCC
KSF

/CLEAR AC AND FLAG
/SKIP IF FLAG =1

7760,

7761,
7762,

Mnemonic

Comments

5357

JMP .-1

6036

/LOOKING FOR CHARACTER

KRB

/READ BUFFER

7106

CLL RTL

7763,

7006

RTL

7764,

/CHANNEL 8 IN ACO

7510

SPA

/CHECKING FOR LEADER

7765,

5357

JMP BEG+1

/FOUND LEADER

7766,

7006

RTL

7767,

6031

KSF

/OK, CHANNEL 7 IN LINK

7770,

5367

JMP -1

7771,

6034

KRS

7772,
7773,
7774,
7775,
7776,

7420
3776
3376
5356
0

SNL
DCA I TEMP
DCA TEMP
JMP BEG
0

TEMP,

/READ, DO NOT CLEAR

/CHECKING FOR ADDRESS
/STORE CONTENTS
/STORE ADDRESS
/NEXT WORD
/TEMP STORAGE

3.2.3

the STOP position. Load the tape in the back of
the reader so that it moves toward the front as it is
read. Proper positioning of the tape in the reader

The Teletype can operate separately from the PDP-8/L

for typing, punching tape, or duplicating tapes.
use the Teletype in this manner:

finds three channels being sensed to the left of the
sprocket wheel and five channels being sensed to
the right of the sprocket wheel.

Assure that the primary Teletype power is on.

b. Set the Teletype LINE/OFF/LOCAL switch to

Set the MEMORY PROTECT switch to down

the LOCAL position.

position.

Off-Line Teletype Procedure

c. Load the punch as follows. Raise the cover
and manually feed the tape from the top of the roll
into the guide at the back of the punch. Advance
the tape through the punch by manually turning the

Load the starting address of the RIM Loader

program (7756 ) into the MA using the SR and the

friction wheel; then close the cover.

LOAD ADDR key.

d. Energize the punch by pressing the ON pushbutton, and produce about 2 ft of leader. The
leader-trailer can be either 200, or 377, code.

e. Press the computer START key and set the 3position Teletype reader switch to the START position. The tape is read into memory by program

To produce the 200, code _|eqder,»s»i_mul?angously

the
press and hold

CTRL and SHIFT keys with the

left hand; press and hold the REPT key; press and
release the P key. When the required amount of
" leader has been punched, release the REPT key,

control .

then CTRL and SHIFT keys.. To produce the 377

The RIM Loader program loads the Binary Loader (BIN)

code leader, simultaneously press and hold bothTM

program as previously described. Withthe BIN Loader

the REPT and RUB OUT keys until a sufficient
amount of leader has been punched.

stored in core memory, program tapes assembled in

Program Assembly Language (PAL III) binary format
can be stored as described in the previous procedure,

checksum error has been detected; therefore, the pro-

If an incorrect key is struck while punching a tape,
the tape can be corrected as follows. If the error is
noticed aofter typing and punching N characters, press.
the punch B. SP. (backspace) push-button N+1 times
and strike the keyboard RUB OUT Key N+1 times.
Then continue typing and punching with the character

gram has been stored incorrectly, and the storage pro-

which was in error.

except that the starting address of the BIN Loader

(77778) is used in step d.

After storing a program in

this manner, the computer stops; the AC should contain

all 0's if the program is stored properly.

If the com-

puter stops with a number other than 0 in the AC, a

cedure should be repeated.

When the program has

gram starting address (usually designated on the leader

To duplicate and obtain a listing of an existing tape,
load the tape to be duplicated in the paper tape reader

of the tape) into the PC and MA using the SR and

or set the LOCAL/LINE switch to LOCAL and turn the

LOAD ADDR key.

punch on, and turn the paper tape reader on.

been stored correctly, initiate it by loading the pro-

Then press the START key.

3-6

- CHAPTER 4
THEORY

This chapter is divided into four sections and covers

4.1.5

Section I contains a discussion of the theory at a

All data to be written into core memory is loaded

the theory of operation of the PDP-8/L Computer.

block diagram level; Section Il contains a discussion
in terms of general theory of operation; Sections III
and IV cover detailed memory theory and detailed
processor theory, respectively.
SECTION 1

BLOCK DIAGRAM DISCUSSION
The following paragraphs discuss the major function-

al elements of the PDP-8/L as shown in the system
block diagram (Figure 4-1).
4.1 REGISTERS

4.1,1

Accumulator (AC)

The 12-bit AC serves as an input/output register for

programmed information transfers between core memory and peripheral equipment, and as a transfer register through which arithmetic and logic operations
are performed.

4.1.2

Link (L)

This 1-bit register extends the arithmetic facilities
of the accumulator and serves as the carry register
for two's complement arithmetic.

4.1.3

Program Counter (PC)

This 12-bit register contains the address of the corememory location from which the next instruction will
be taken.

4,1.4 Memory Address Register (MA)

Memory Buffer Register (MB)

first into the 12-bit MB.,

Through the facilities

provided by the major-register gating network, the
MB accepts data from any of the major registers in
the processor and, during a high-speed data-break

transfer, from peripheral devices.

Its only output

capabi lity, other than its direct access to core mem-

ory, is through the processor interface to optional
peripheral equipment.

4.1.6 Sense Register (Sense)
All data read from core memory is strobed first into

this 12-bit register.

It accepts data only from the

core memory and transfers data directly to the
Instruction Register (IR) and, through the major reg~
ister gating network, to any other register in the
processor .

’

4.1.7 Instruction Register (IR)

This 3-bit register contains the operation code of the
instruction currently being performed by the computer. The three most-significant bits of the current
instruction load into the IR from Sense during a
Fetch cycle. The contents of the IR are decoded to
produce discrete levels for each of the eight basic
instructions.

4.1,8 Switch Register (SR)
The 12-bit SR performs a dual function in that it
permits the manual loading of either a discrete corememory address into the PC or a 12-bit data or control word into core memory. The SR is loaded by 12
toggle switches located on the operator's console.
Actuation of either the LOAD ADDR or DEP keys
then causes the stored information to be loaded into
the MA or MB, respectively.

This 12-bit register contains the address in core memory that is currently selected for reading or writing.

4,2

.
core memory

are implemented through the major-register gating

This address is decoded by the memory selection
matrix to permit addressing of all 4096 words of the

MAJOR REGISTER GATING NETWORK

All internal data transfers occurring in the PDP-8/L

(NPLT/OLTPUT

e
‘

EXTERANA,

DRBUESRS/
v

RECEIVERS

[—

—

IINTROL M

NPUT BUS

-y

;

170 8uS
'

NTERNAL )

PCS:T VE BUS

GATING

MB DATA <—

AC DATA @

sieNaLs

;

BITS)

‘

BTy

;

}

|
;

‘

‘(

‘

|
I

—

swiTcn

rERATORS

RE((SéSTER

CONTROVS

INDICATORS

;

OPERATOR'S CONSOLE

Figure 4-1

System Block Diagram

PROCESSOR

NTROL

5
4096 12-8i

WORD

MEMORY

CORE

- PLANE

‘

}

S H+ ==

[

(12

l
CONTROL

MEMORY
A

ME MORY

BITS)

]

CONTROL

—_—

;

o TeeTvee

\ ¢

PROGRAM

(12

;L_g_______________4____!_“._.4_J

CONTROL @

TELETYPE f

[

MEMORY EXT

| GATING NETWORK

— — —
. —
. — = — = - =MAJOR
!
REGISTERS

L——{ COUNTER {PC) |—# BUFFER (MB] [—p{ ,REGISTER
ADDRESS(MA)

BITS)

—

GATING

conTroL &

NT INPUT
BUS —¥

H
|

.
|ViiNPUTBUS
l
1

(12

—_ —

PULSES | |
!

ADDER

]

: !

ACCUMULATOR

r|—¢

‘

!P! _——

BUS

“

‘

’

[

—e

[

SONTROL 4—

;

nE T
AJDRESS
i

|
!

AT JATA 4r—

i | REGISTER
OUTPUT
GATING NETWORK

!
coNTROL —#

e
CTivE BBLS
POSITIVE
fi

r—

M3 SaTa 4—

— = —
r _— = !| | =REGISTER
GAT:NG

INPUT

SENSE AMPL

—*
REGISTER
12

BITS)

L —T—L—l—}i ;e

INSTRUCTION

BITS)

;

SENSE

CONTROL

wemony

]

network.

The network contains a separate gate

PR8/L
PP8/L

- structure and a common register input bus for each

of the 12 bits,

Transfers between registers and into

and out of memory occur through the network.

Data

High-Speed Tape Reader

High-Speed Tape Punch

The. data-break peripherals, also optionally avail-

and address information received through the 1/0

able, are represented by mass memory devices, such

interface also pass through this network.

as magnetic tape, magnetic drum, and disk file
systems,

4.3

TIMING AND CONTROL ELEMENTS

A Teletype ASR33 Automatic Send-Receive Set is
provided as standard equipment with the PDP-8/L.
In addition to a manual keyboard and hard-copy

4.3.1

Timing Elements

printout facilities, the ASR33 contains an 8-level
paper~tape punch and a paper-tape reader, all of

The processor and memory control circuits in the

which are interfaced with the processor through the

standard PDP-8/L use fixed and variable delay
lines in place of timing clocks. Interleaving of

Teletype control logic and internal positive bus.

fixed delay sequences provides asynchronous control

between the processor and the memory.

The overall

cycle time of approximately 1.6 ps is determined by
the memory timing.

4.5

MEMORY

For applications involving real

time, the KW8I Real Time Clock option is added to

The standard memory supplied with the PDP-8/L is a

the system,

random-access, coincident current, magnetic-core

memory with a storage capacity of 4096 12-bit words.
The core planes and diode matrices that make up the
4.,3.2 _@nfrol Elements

core array are mounted on printed-circuit cards.

Circuits in the PDP-8/L control program advance

These cards plug directly into the PDP-8/L logic rack
receptacles with the sense and inhibit inputs attached

and instruction skipping.

These circuits, which

on connector cards.

operate in response to conditions established in

8/L frame.

either the processor or peripheral equipment, control
the flow of information between registers.

An additional 4K of core mem-

ory may be optionally added externally to the PDP-

In addi-

tion, they initiate program interrupt operations

The major elements of the core memory are described

during which subroutines enable the servicing of
peripheral equipment.

in the following paragraphs.

4.5.1

Core Array

4.4, INPUT/OUTPUT
The ferrite-core array consists of 12 (64 x 64) core

The PDP-8/L operates with two basic types of input/
output (I/O) equipment. Peripherals which commun-

of data and program storage.

icate with the processor through the external positive

plane is optionally available to permit a parity bit

programmed transfer 1/0 bus, and those which use

for each word in memory.

the external positive data break facility. In addition the high-speed perforated paper tape readerand
punch peripherals operate directly from control

4.5.2

planes.

This provides a total of 4096 12-bit words
A thirteenth core

Memory Control

modules located within the PDP-8/L processor assemMemory control circuits determine the sequence of

bly.

operations of the complete read/write memory cycle,
starting and stopping each function as required.

Typical of optionally available programmed transfer

1/0 bus peripherals are:
VC8/L
KV8/L
CR8/L
VP8/L

Oscilloscope Display Control
Storage Tube Display and Control
Low-Speed Card Reader
Incremental Plotter

4.,5.3

Address Selection

The Memory Address register (MA) contains the 12-bit
address of the currently selected core-memory locat-

4-3

ion. This address is decoded through the selection
switches and the diode matrix to enable passage of
read/write currents through specific X and Y drive
lines of the memory. The coincidence of these

Count (WC), Current Address (CA), and Break (B).
The outputs of these flip-flops generate enabling

location desired.

The first three major states (F, D, and E) are suffic-

4.5.4 Inhibit Drivers

logical operations, memory read/write operations,
and data transfers through the 1/0 bus. The lastthree

levels used within the control elements of the proces- sor to implement particular machine functions.

currents selects the specific 12-bit core-memory

ient to perform most machine functions in the areasof

major states (WC, CA, and B) are used only for highspeed data transfers through the optional KD8L Data-

The PDP-8/L memory is so configured that, unless
prohibited, all bit locations of the addressed memory
cell would be switched to a logical 1 during the write
portion of the memory cycle. Inhibit drivers, therefore, are used to ensure that the logic O levels stored
in the MB will be retained in the corresponding bit
locations of the addressed memory cell.

Break facility.

The processor determines, near the end of each computer cycle, which major state will be needed for the
activities to be performed in the next computer cycle,
At the very end of the cycle (TP4) the new majorstate will be entered by the setting of that particular
flip-flop.

4.5.5

Sense Amplifiers
4.8

During the read portion of the memory cycle, sense
amplifiers detect analog signals induced in the sense
windings of the core array. These signals are amplified and used to set corresponding bits of the Sense

INTERNAL DATA FLOW

The simplified system block diagram shown in Figure
4-1 depicts the flow of data through the major elements of the PDP-8/L. Note that all data transfers
into the four major registers (AC, PC, MB, and MA)

occur through a register gating network and a common
register bus. The outputs of these four registers, plus
the Sense and SR, and the data input from the external interface are all connected to the input gates
of the major-register gating network.

SECTION 11

GENERAL THEORY
The following paragraphs discuss the major functional

elements of the PDP-8/L in terms of their operational
dynamics.

These dynamics will be discussed in great-

This permits incoming data to be strobed into any
desired major register, or the contents of any register
to be complemented, incremented, or transferred into

er detail in Sections Il and 1V

any other major register.

The complementing function
is implemented by transferring the 0 output of the
desired register through the gating network and back
into the same register. The incrementing function is
performed by transferring the 1 output of the register

4,6 TIME STATES/TIME PULSES
Each computer cycle consists of four basic time divisions, T1, T2, T3, and T4, as denoted on the system

flow diagrams.

through the gating network while inserting a carry
into the low-order bit of the word. The data is then
transferred back into the desired register.

Each time division consists of a time

state (TS) and its associated time pulse (TP).

The

time states each extend throughout their particular

time division (TS1, TS2, TS3, TS4) and end with a
time pulse (TP1, TP2, TP3, TP4).
4,9 INSTRUCTIONS

In general, the time states generate enabling levels
associated with the register outputs. Time pulses are
used to strobe data into registers.

Instruction words are of two types:
and augmented.

memory reference

Memory reference instructions store

The PDP-8/L contains six major-state flip-flops.

or retrieve data from core memory, while augmented
instructions do not. All instructions utilize bits O
through 2 to specify the operation code. Operation
codes of Og through 5g specify memory reference
instructions, and codes of 68 and 7g specify augment-

These are:

ed instructions.

4.7 MAJOR STATES

Fetch (F), Defer (D), Execute (E), Word

4-4

Memory reference instruction execu-

tion times are multiples of the 1.6 ys memory cycle.

Execution Time: 3.2 ps with direct addressing,
4,8 ps with indirect addressing .

Indirect addressing increases the execution time of a
memory reference instruction by 1.6 ps.

The aug-

. mented instructions, input-output transfer and oper-

ate, are performed in 4.25 and 1.6 ps, respectively.

(All computer times are *12%.)

Operation: The AND operation is performed between
the content of memory location Y and the content of

the AC.

The result is left in the AC, the original

content of the AC is lost, and the content of Y is
restored.

4.9.1

Corresponding bits of the AC and Y are

operated upon independently .

Memory Reference Instructions

Since the PDP-8/L system contains a 4096-word core
memory, 12 bits are required to address all locations.
To simplify addressing, the core memory is divided

Original

ACj

]

into blocks, or pages, of 128 words (200g addresses) .
:Pages are numbered Og through 37g, each field of

4096-words of core memory uses 32

pages.

The seven

address bits (bits 5 through 11) of a memory reference

instruction can address any location in the page on
.which the current instruction is located by placing
a 1 in bit 4 of the instruction.

This instruction, often

called extract or mask, can be considered as a bitby-bit multiplication. Example:

Symbol:

Final

ACjA Yj =>ACj

By placing a 0 in bit

" 4 of the instruction, any location in page 0 can be
Two's Complement Add (TAD Y)

addressed directly from any page of core memory.
All other core memory locations can be addressed

indirectly by placing a 1 in bit 3 and placing a 7-bit

Octal Code:

effective address in bits 5 through 11 of the instruct-

Indicators:

IR1, FETCH, EXECUTE

ion to specify the location in the current page or

Execution Time:

page O which contains the full 12-bit absolute address

4.8 ps with indirect addressing .

“of the operand.

Operation: The content of memory location Y is
added to the content of the AC in two's complement

Word format of memory reference instructions is

arithmetic.

3.2 ps with direct addressing,

shown in Figure 4-2 and the instructions perform as

The result of this addition is held in the
AC, the original content of the AC is lost, and the

follows:

content of Y is restored.

OPERATION
CODES O-5
p

MEMORY
PAGE

If there is a carry from

]

INDIRECT
ADDRESSING

ADDRESS

Figure 4-2

Memory Reference Instruction Bit Reference

Logical AND (AND Y)

Octal Code:
Indicators:

ACO, the link is complemented.

IRO, FETCH, EXECUTE

This feature is use-

ful in multiple precision arithmetic.
Symbol:

ACO =11

+Y0 -11=>AC0
- 11

Execution Time:

Increment and Skip If Zero (ISZ Y)
Octal Code: 2
Indicators: IR2, FETCH, EXECUTE
Execution Time: 3.2 ps with direct addressing,
4.8 ps with indirect addressing.
Operation: The content of memory location Y is incremented by one in two's complement arithmetic.
If the resultant content of Y equals zero, the content
of the PC is incremented by one and the next instruction is skipped. If the resultant content of Y does
not equal zero, the program proceeds to the next

instruction. The incremented content of Y is restored
to memory. The content of the AC is not affected by

3.2 ps with direct addressing,

4.8 ps with indirect addressing .
Operation: The content of the PC is deposited in core

memory location Y and the next instruction is taken
from core memory location Y + 1. The content of the

AC is not affected by this instruction.
Symbol:

PC +1 =2>Y
Y +1=>PC

Jump to Y (JMPY)
Octal Code:
Indicators:

IR5, FETCH

this instruction.

Execution Time: 1.6 ps with direct addressing,
3.2 ps with indirect addressing.

Symbol:

Operation: Address Y is set into the PC so that the

Y +1=2>Y

If resultant YO - 11 =0, then PC +1 = >PC

Octal Code:

The content of

Symbol:

Y = >PC

IR3, FETCH, EXECUTE

Execution Time:

3.2 ps with direct addressing,
4.9.2

4.8 ps with indirect addressing.

Operation: The content of the AC is deposited in
core memory at address Y and the AC is cleared.
The previous content of memory location Y is lost.
Symbol:

The original content of the PC is lost.
the AC is not affected this instruction.

Deposit and Clear AC (DCA YY)

Indicators:

next instruction is taken from core memory address Y.

Augmented Instructions

There are two augmented instructions which do not
reference core memory. ‘They are the input-output
transfer, which has an operation code of 6, and the

AC =>Y

operate which has an operation code of 7,

then 0 = >AC

through 11 within these instructions function as an

Jump to Subroutine (JMS Y)
Octal Code: 4
Indicators: IR4, FETCH, EXECUTE

Bits 3

extension of the operation code and can be microprogrammed to perform several operations within one
instruction. Augmented instructions are one-cycle
(Fetch) instructions that initiate various operations
as a function of bit microprogramming.

GENERATES

PULSE AT
EVENT TIME 3
IF A1

PULSE AT
EVENT TIME 1
iF A1

AN IOP 4

OPERATION
CODE 6

—A—

DEVICE
SELECTION

AN I1OP
1

—A—

e —

GENERATES
AN 10P 2
PULSE AT

EVENT TIME 2
IF A1

Figure 4-3

IOT Instruction Bit Assignments

4.9.2.1

Input/Output Transfer Instruction - Micro-

The operate instruction consists of two groups of

instructions of the input-output transfer (IOT) group

microinstructions.

initiate operation of peripheral equipment and effect

for clear, complement, rotate, and increment opera-

Group 1 (OPR 1) is principally

information transfers between the processor and an I/O
Specifically, upon recognition of the opera-

tions and is designated by the presence of a 0 in bit

device.

tion code 6 as an IOT instruction, the computer

the content of the accumulator and link and continu-

enters a 4.25 ps expanded computer Fetch cycle by

ing to, or skipping, the next instruction based on the

Group 2 (OPR 2) is used principally in checking

setting a PAUSE flip-flop and enabling the 10P

check.

generator to produce IOP 1, IOP 2 and IOP 4 pulses

instruction,

A1 in bit 3 designates an OPR 2 micro-

as a function of the three least significant bits of the
instruction (bits 9 through 11). These pulses occur
at 1 ps intervals designated as event times 1, 2 and
3 as follows.

Instruction
Bit (MB)
11
10
9

IOP
Pulses
IOP 1
IOP 2
IOP 4

(o))
Pulse
IOT 1

Event
Time
1

IOT 2
IOT 4

2
3

4.9.2,2,1

Group 1 Microinstruction - The Group 1

operate microinstruction format is shown in Figure

4-4 and the microinstructions are explained in the

succeeding paragraphs.

Any logical combination of

bits within this group can be combined into one
microinstruction,

For example, it is possible to

assign ones to bits 5, 6, and 11; although it is not

logical to assign ones to bits 8 and 9 simultaneously
since they specify conflicting operations.

The IOP pulses are gated in the device selector of
the selected equipment to produce 10T pulses that
enact a data transfer or initiate a control operation. Program selection of an equipment is accomplished by bits 3 through 8 of the IOT instruction.
These bits form a 6-bit code that enables the device
selector of a given device. The format of the IOT

No Operation (NOP)

Octal Code:

instruction is shown in Figure 4-3.

7000

Sequence:

None

Indicators:

IR7, FETCH

Execution Time:

Operation:

1.6 ps

This command causes a 1-cycle delay in

the program and then the next sequential instruction

4.9.2.2 Qperate Instruction - With operate instructions, the programmer can consider logical sequences
occurring during one computer Fetch cycle, These
sequences provide a logical method of forming micro-

is initiated.

instructions.

Symbol:

CODE 7

or loop timing with peripheral equipment timing.

None

ROTATE 1

ROTATE

OPERATION

This command is used to add execution

time to a program, such as to synchronize subroutine

CLA

.
2

CONTAINS
AOTO

AC ANDL

CMA

—A—

CLL

PR
7

CML

SPECIFY

2 POSITIONS

RIGHT

r——t—
5

POSITION IF A O,

IF
A 1

—A—

ROTATE

AC AND L

LEFT

GROUPH

Figure 4-4

Group 1 Operate Instruction Bit Assignments

4-7

IAC

Symbol: ACj=>ACj +1
ACI11 =>1L

Increment Accumulator (IAC)

" Octal Code: 7001
Sequence:

Indicators:

IR7, FETCH

L=> AC0

Rotate Two Right (RTR)

Execution Time: 1.6 ps
Operation: The content of the AC is incremented by

Octal Code: 7012
Sequence: 4
Indicators: IR7, FETCH
Execution Time: 1.6 ps

one.

Symbol: AC +1 =>AC

Operation: The content of the AC is rotated one
binary position to the right with the content of the

Rotate Accumulator Left (RAL)
Octal Code:

link . This instruction is logically equal to two
successive RAR operations.

7004

Sequence:

Indicators:

IR7, FETCH

Symbol:

ACl0 =L

Execution Time: 1.6 ps
Operation: The content of the AC is rotated one
binary position to the left with the content of the
link . The content of bits AC1 ~ 11 are shifted to the
next more significant bit, the content of ACO is
shifted into the L, and the content of the L is shifted

AC11 = ACO

L=>ACI

Complement Link (CML)
Octal Code: 7020
Sequence: 2
Indicators: IR7, FETCH

into AC11,

Execution Time:

Symbol: ACj= > ACj- 1

Operation:

ACO = >L

L=>ACN

Complement Accumulator (CMA)

Octal Code: 7006
Sequence: 4

Octal Code: 7040
2

Sequence:

IR7, FETCH

Execution Time:

1.6 ps

Indicators:

IR7, FETCH
Execution Time: 1.6 ps
Operation: The content of the AC is set to the one's

Operation: The content of the AC is rotated two
binary positions to theleft with the content of the

link .

complement of the current content of the AC. The
content of each bit of the AC is complemented
individually.

This instruction is logically equal to two

successive RAL operations.
Symbol:

1.6 ps

The content of the L is complemented.

Symbd|: L=>L

Rotate Two Left (RTL)

Indicators:

ACj = >ACj +2

ACj = > ACj -2

Symbol: ;&_C_| = >ACj

ACl =>L

Complement and Increment Accumulator (CIA)

ACO = >ACITI
L=>ACI0

Octal Code:
Rotate Accumulator Right (RAR)

Sequence:

7041

2,3

Indicators:

Octal Code:

1R7, FETCH
Execution Time: 1,6 ps
Operation: The content of the AC is converted from
a binary value to its equivalent two's complement
number. This conversion is accomplished by com-

7010

Sequence:

Indicators:

IR7, FETCH

Execution Time:

1.6 ps
Operation: The content of the AC is rotated one
binary position to the right with the content of the
link. The content of bits ACO - 10 are shifted to the
next less significant bit, the contentof AC11 is shifted into the L, and the content of the L is shifted into

bining the CMA and IAC commands, thus the content
of the AC is complemented during sequence 2 and is
incremented by one during sequence 3.
Symbol:

ACO.

4-8

ACj = >AC(j,
then AC +1 =2>AC

Clear Link (CLL)

Indicators:

IR7, FETCH

Execution Time:

Octal Code: 7100
Sequence: 1
Indicators: IR7, FETCH
Execution Time: 1.6 ps

Operation:

The content of the L is cleared to contain

a0.

Symbol:

1 =>ACj

4.9.2.2.2
Symbol:

1.6 ps

Operation: Each bit of the AC is set to contain a
binary 1. This operation is logically equal to combining the CLA and CMA commands.

Group 2 Microinstructions - The Group

2 operate microinstruction format is shown in Figure

0=>L

4-5 and the primary microinstructions are explained
in the following paragraphs. Any logical combina-

Set Link (STL)

tion of bits within this group can be composed into

Octal Code: 7120
Sequence: 1,2

one microinstruction.

Indicators:

If skips are combined in a single instruction, the
inclusive OR of the conditions determines the skip
when bit 8 is a 0; and the AND of the inverse of the
conditions determines the skip when bit 8isa 1. For
example, if ones are designated in bits 6 and 7 (SZA
and SNL), the next instruction is skipped if either
the content of the AC =0, or the content of L =1,
If ones are contained in bits 5, 7, and 8, the next
instruction is skipped if the AC contains a positive
number and the L contains a 0.

IR7, FETCH

Execution Time:

1.6 ps

Operation: The L is set to contain a binary 1. This
instruction is logically equal to combining the CLL
and CML commands.

Symbol:

1 =>L

Clear Accumulator (CLA)

Halt (HLT)

Octal Code:

7200

Sequence:

Indicators:

IR7, FETCH

Execution Time:

Operation:

Octal Code: 7402
3
Indicators: IR7, RUN off

Sequence:

1.6 ps

The content of each bit of the AC is

Execution Time:

Symbol: 0=>AC

Set Accumulator (STA)

ted during either sequence 1, or 2, and so are performed before the program stops.

Octal Code: 7240
Sequence: 1,2

Symbol:

0 = >RUN
REVERSE
SKIP

OPERATION
CODE 7

[ o)

1.6 ps

Operation: Clears the RUN flip~flop at Sequence 3,
so that the program stops at the conclusion of the
current machine cycle. This command can be combined with others in the OPR 2 group that are execu-

cleared to contain a binary 0.

CLA

—

——

CONTAINS A1

SMA

TO SPECIFY

SENSING OF
BITS 5,6,7

SZA

7
H—’

HLT

——

—

OSR

CONTAINS A O

GROUP 2

TO SPECIFY

GROUP
2

Figure 4-5
Group 2 Operate Instruction Bit Assignments

4-9

OR With Switch Register (OSR)

Skip on Zero Accumulator (SZA)

Octal Code:

Octal Code: 7440
Sequence: 1

7404

Sequence:

Indicators:

IR7, FETCH

Indicators: IR7, FETCH

Execution Time: 1.6 ps

Execution Time:

Operation: The inclusive OR operation is performed
between the content of the AC and the content of
the SR. The result is left in the AC, the original

Operation:

1.6 ps

The content of each bit of the AC is

sampled, and if any bit contains a 0 the content of

the PC is incremented by one so that the next se-

content of the AC is lost, and the content of the SR
is unaffected by this command. When combined with
the CLA command, the OSR performs a transfer of the
content of the SR into the AC,

quential instruction is skipped.

Symbol: ACj V SRj = >AC(j

Symbol: If ACO - 11 =0, then PC +1 = >PC

Skip, Unconditional (SKP)
Octal Code: 7410
Sequence: |
Indicators:

IR7, FETCH

Execution Time:

1.6 ps

Operation: The content of the PC is incremented by
one so that the next sequential instruction is skipped.
Symbol:

PC +1 =>PC

If all bits of the AC
contain a 0, no operation occurs and the next sequential instruction is initiated.

Skip on Non-Zero Accumulator (SNA)

Octal Code:

7450

Sequence:

Indicators:

IR7, FETCH

Execution Time:

Operation:

1.6 ps

The content of each bit of the AC is

sampled, and if any bit contains a 1 the content of
the PC is incremented by one so that the next sequential instruction is skipped.

If all bits of the

AC contain a 0, no operation occurs and the next

sequential instruction is initiated.

Skip on Non=Zero Link (SNL)

Octal Code: 7420
1

Sequence:

Indicators:

IR7, FETCH

Execution Time:

Operation:

1.6 ps

The content of the L is sampled, and if

it contains a 1 the content of the PC is incremented
by one so that the next sequential instruction is skipped.

If the L contains a 0, no operation occurs and

the next sequential instruction is initiated.
Symbol:

If L=1, then PC +1 =>PC

Symbol: If ACO - 11 #0, then PC +1 = >PC
Skip on Minus Accumulator (SMA)

Octal Code: 7500
|

Sequence:

Indicators:

IR7, FETCH

Execution Time:
Operation:

1.6 ps

The content of the most significant bit of

the AC is sampled, and if it contains a 1, indicating

the AC contains a negative number, the content of
the PC is incremented by one so that the next se-

quential instruction is skipped.

If the AC contains

a positive number no operation occurs and program

Skip on Zero Link (SZL)
Octal Code:

7430

Sequence:

Indicators:

IR7, FETCH

Symbol:

Execution Time:

Operation:

control advances to the next sequential instruction.

1.6 ps

Skip on Positive Accumulator (SPA)

The content of the L is sampled, and if

it contains a O the content of the PC is incremented

Octal Code:
|

by one so that the next sequential instruction is skip-

Sequence:

ped.

Indicators:

If the L contains a 1, no operation occurs and

the next sequential instruction is initiated.

1f L =0, then PC +1 =>PC

7510

IR7, FETCH

Execution Time:

Operation:
Symbol:

ACO =1, then PC +1 = >PC

1.6 ps

The content of the most significant bit

of the AC is sampled, and if it contains a 0 indicat-

ing a positive number (or zero), the content of the

4,10.1

Instructions

PC is incremented by one so that the next sequential
instruction is skipped.

If the AC contains a negative

number, no operation occurs and the program con-

trol advances to the next sequential instruction.

Symbol:

1f ACO =0, then PC +1 = >PC

The two instructions associated with the program
interrupt synchronization element are IOT microinstructions., These instructions are:
Interrupt Turn On (ION)

Octal Code: 6001
Event Time: Not applicable

Clear Accumulator (CLA)

Indicators:

IR6, FETCH, ION

Execution Time:

4,25 ps

Octal Code: 7600
Sequence: 2

Operation:

Indicators:

respond to a program interrupt request,

IR7, FETCH

Execution Time:

Operation:

This command enables the computer to
If the inter-

rupt is disabled when this instruction is given, the

1.6 ps

Each bit of the AC is cleared to contain

a binary 0,

computer executes the next instruction, then enables
The additional instruction allows exit

the interrupt.

from the interrupt subroutine before allowing another

Symbol:

interrupt to occur. This instruction has no effect upon
the condition of the interrupt circuits if it is given
when the interrupt is enabled.

0= >AC

Symbol:
4,10

1 = >INT. ENABLE

PROGRAM INTERRUPT

Interrupt Turn Off (IOF)

Some of the 1/0O devices used with the PDP-8/L require several instructions to complete a data transfer

program interrupt facility.

Octal Code: 6002
Event Time: Not applicable
Indicators: 1Ré, FETCH
Execution Time: 4.25 ps
Operation: This command disables the program inter-~
rupt synchronization element to prevent interruption
of the current program.

When the program enables the program interrupt

Symbol:

or perform a specified operation.

Others are so slow

in operation, relative to the computer, that it would
consume a prohibitive amount of time to have the
computer wait in a skip loop for their operation to be
completed.

These devices, therefore, employ the

0 = >INT.ENABLE, INT.DELAY

facility, the computer senses interrupt requests from

peripheral devices. The interrupt may also be initiated in response to a programmed IOT instruction.

An interrupt is allowed to occur only on completion
of the instruction currently in process and takes affect
at the beginning of the following Fetch cycle.

SECTION III

DETAILED MEMORY THEORY
The following paragraphs discuss memory theory at a

detailed level.
A program interrupt is similar in effect to a JMS to
memory address 0000.

The content of PC is saved in

location 0000 and the next instruction taken from

4,11 OVERALL MEMORY THEORY

location 0001g. The instruction stored at this
location is usually a JMP to a peripheral servicing
subroutine .

The basic PDP-8/L contains a single 4096-word,
12-bit core memory which performs all normal funct-

ions of data storage and retrieval.

All necessary

After identifying the interrupting device and ser-

control elements for the memory are contained within

vicing it, the processor performs a JMP I 0000 (jump
to the address specified by the content of location

the basic PDP-8/L.

0000) to return to the point at which the program was

The memory capacity of the computer can be increas-

interrupted.

ed, to a maximum of 8192 words with or without

parity. If the parity option is selected, the parity

triggers the first delay, (Drawing BS-8L-0-13),

bit is carried as the thirteenth bit in each word. Use
of the extended memory option, however, necessitates the addition of the type MC8/L Memory Extension Control. The extended memory is located
external to the processor.

MEM BEGIN is produced, setting the READ and

LOCK flip-flops.

The READ flip~flop enables the

read/write switches to provide the read currents to
the memory stack,

The LOCK flip-flop prevents

initiation of another memory cycle until the present

cycle is completed.

Another tap of the delay line

Figure 4-6 is a block diagram showing the interrela-

provides the pulse input to the variable delay en-

tionship of the major elements of the PDP-8/L mem-

abled by the READ flip-flop.

ory and its control elements.

the variable delay generates STROBE FIELD 0 and

STROBE.
4,12

MEMORY OPERATION

functions:

The variable delay is adjusted so these

signals occur toward the end of the read cycle.

STROBE FIELD O gates the sense amplifier outputs

PDP-8/L memory operation involves five major
write.

The pulse output of

address selection, read, sense, inhibit,

The memory control provides the timing and

initiation of the read, sense, inhibit and write
functions. Address selection is performed by the
contents of the MA register, applied through the
address selection X and Y Diode Selection Matrices.

(Drawing BS-8L-0~14) into the Sense register.

STROBE returns to the central processor to clear the
MEM IDLE and PAUSE flip-flops (Drawing BS-8L-0-2)
and continue the processor timing cycle.

Approximately 400 ns after Read is initiated, a CYC

DONE pulse is produced.

CYC DONE terminates the

Read cycle, sets the CYCLE flip-flop, and initiates
the second transition of the memory cycle through the

4.12,1

same delay lines.

Memory Control

The memory control consists of series-connected de-

The setting of the CYCLE flip-flop

enables CYC DONE (delayed) to set the INHIBIT flip~
flop. The inhibit output gates the data from the MB

lay lines with associated logic gates and control

to the inhibit drivers (Drawing BS-8L-0-14).

flip-flops (Drawing BS-8L-0-13).

Write portion of the memory cycle is initiated approx-

An initiating

signal, MEM START, from the central processor,
cycles through the delay lines alternately settingand

clearing the varioys control flip-flops, and returns to
the ‘processor as the MEM DONE signal. The timing
for this cycle is fixed by prewired taps on the delay
lines. The control flip-flops enable the read/write

The

imately 50 ns after the INHIBIT flip-flop is set. When

set, the WRITE flip-flop enables the read/write
switches to provide the write currents to the memory
stack, and clear the LOCK flip-flop. Another delayed CYC DONE pulse clears the CYCLE flip-flop

during the write portion of the memory cycle.

and inhibit currents, and control the memory cycle.
A second CYC DONE pulse, generated approximately

Figure 4-7 illustrates the waveshapes of the memory
control signals. The transition and duration times
are approximate due to the inexact delay through
the pusle amplifiers (approximately 50 ns), and gates

(approximately 20 ns).

For explanation purposes, it

is assumed that the processor POWER CLEAR signal
has been generated, and the START key actuated

400 ns after the initiation of the inhibit operation,
terminates the inhibit and write operations.

In addi-

tion, this CYC DONE pulse combines with LOCK (0)
to generate MEM DONE, indicating the end of the

memory timing cycle.

MEM DONE sets the MEM

IDLE flip-flop (Drawing BS-8L~0-2) in the processor

control, reinitiating another processor/memory cycle.

producing MEM START
.

The MEM START signal to the memory control circuit-

ry is gated by the field selection signal EA. Initially,
MEM START sets the MEM ENABLE flip-flop when

EA specifies basic memory field operation. The

4.12.2 Read/Write
The ferrite~core memory consists of 12 planes (13 if
the parity option is selected), each containing 4096

buffered MEM ENABLE output enables the contents

ferrite cores arranged in a 64 x 64 core array.

of the sense register to the major register bus; the

core assumes a stable magnetic state corresponding
either to a binary 1 or a binary 0.

X- and Y -axis selection current drivers, and the
inhibit drivers.

Each

Selection and switching of the cores is provided by
The memory timing cycle consists of two transitions

four windings traversing each core in the memory in

through the same delay lines.

a standard 3D selection technique. An X-axis read/

After MEM START

—r’

r—— >~ TO INSTRUCTION REGISTER

CURRENT

LIMITING

BIT OO

RESISTORS

(6624)

AB25/AB 26

" MB 00 .I_,

BIT 00

| | horivers
:

FROM <
MEMORY

A23,B823,824

6228'S)

BUFFER

12-BIT WORD

e SLICE

——————————————
——

MAOQO (0) o—~

[

MAOO (1) @—»{ ADDRESS

€L-v

778

00g

INHIBIT &—

DECODING

MAO1 (1) @— SELECTION|

cD20 /CD22

]

DIODEMATRIX
SELECTION|

(6610,6611)

cD20/CD22

swITCHES

|I | (6221'Ss)

(6221'S) DI8 /DI9

CLAMP

o}
MAO3(0)

SEWER OK a— MEMORY VOLTAGE

STOP OK @

REGULATION AND
6826)
AB27

MEM

SUPPLY+

su’fity

MAO9(0 )

[BD MEM
M
MAO4(1)
(

MAO3(1)

DETECTION

SWITCHES

(6221'S) D23 /024

NEG

MAOCS(1)

CURRENT

LIMITING

MA10(1 )|

NEG

CLAMP

MEM
BMEM.

—o

RESISTORS

(6624's)

AB 25 /AB 26

R/W RETURN | RW/SOURCE

SELECTION | SELECTION
SWITCHES

SWITCHES

D25

c25

(G6228)

(6228)

READ (1)
WRITE (1}

THERMISTOR
(IN MEMORY

STACK)

Figure 4-6

CIS
DI6

M310 DI4,015

M360 CI7
M617

8 MEM ENABLE @———
o

MATI(1)

MAOS( 1)

M3
M216

lt—e B MEM ENABLE

ADDRESS DECODING

MEMORY CONTROL |g STROBE

DIT

Memory System, Block Diagram

TO/FROM

[ MEM DONE
Llg MEM

‘

Y R/W SOURCE
INHIBIT

AND SELECTION | NETURN RETURN | ®AND SELECTION

SHUT DOWN «—|

CIB/CI9 pg—e MAOSB(1}

|
n'—

SWI

[#—® MAO6 (1)

|| | SELECTION [#—® MAOT (1)

______________

ADDRESS DECODING

POWER CLEAR #—

ADDRESS

DECODING

{

I 77g
!

X R/W SOURCE

le—o MAO6 (0)

Y-AXIS

|
|!5

B MEM ENABLE @—»

00g

(6610,6611)

(C23/C24

-AXIS

MATRIX

(G221's)

|DIODE SELECTION|

SWITCHES { |

__POWER OX

B MEM ENABLE

STROBE FIELD @

8 MEM ENABLE o——T

MAOC2 (1) @&—a

MEM 11

MEW BEGIN

| core mEmMORY|

NE T WORK

BIT 11

|
&—

TO MAJOR
REGISTER
GATING

» MEM 0?2

|
|

A18-A20/B18 -B20

BIT 11

MEM SUPPLY- o—l

+ MEM 01

SENSE AMPLIFIERS
AND MEM REGISTER
020)

1
i
I

MEM SUPPLY+

> MEM 00

POWER CLEAR

START

CP TIMING

+3V

MEM START
ov
+3v

MEM ENABLE

ov
+3v
READ

ov
+3V

STROBE
ov
+3v
LOCK
ov
+3v

CYC DONE
ov
+3v

CYCLE
ov
+3v

INHIBIT

ov
+3v
WRITE
ov
+3v

MEM DONE

* The MEM START pulse width depends on the path of its origin i.e., approximately 150
nsec if generated by a manual function like actuating Dep key, and approximately 500

nsec if generated from a previous program instruction.

Figure 4-7

Memory Timing Diagram

write winding passes through all cores in each of 64

current level is known as the half-select value.

horizontal rows; a Y-axis read/write winding passes

the reinforcing magnetic field caused by the coincident current of both an X and a Y read/write winding

through all cores in each of 64 vertical rows; and a

Only

sense and an inhibit winding pass through all cores of

can cause the core located at the point of coincidence

each of 12 (or 13) planes.

to change state. It is this principle that allows the
relatively simple winding arrangement to select one

Through the use of select-

ion circuits controlling the inputs of the X and Y

read/write windings, any one of the 4096 12-bit word

and only one memory word out of a possible 4096 in

locations can be addressed for writing data into, or

‘each array .

reading data out of memory.

Figure 4-8 shows a simple 4 x 4 core array.

The

winding scheme shown on this array is identical to

The level of the read, write, and inhibit currents

that used in the planes of the PDP-8/L memory.

passing through these windings is such that no single
winding produces a magnetic field strong enough to

A half-select current passing through the X2 winding

cause a core to change its magnetic state.

from right to left (write direction) produces a magnet-~

This

ic field that tends to change all the cores in that

flow, therefore, the X2Y3 core on each plane

horizontal row from the 0 to the 1 state.

changes to, or remains in, the 1 state.

The flux

This makes

produced by this current is, however, insufficient to

each of these cores equivalent to one bit of a 12-bit

complete the state transition in any core.

storage cell.

Simultan-

eously, passing a half-select current through the Y3
winding from top to bottom (write direction) tends to

It should be noted that passing half-select value write

produce the same effect on all cores in that particular

currents through a particular pair of X and Y windings

vertical row.

Note, however, that both currents

produces the 1 state in all 12-bit positions of the

pass through one core, located at the intersection of

selected core-memory storage cell.

the X2 and Y3 windings.

information, however, it is also necessary to write

This then becomes the

To store usable

selected core.

the O state during the write cycle in any or all bit

The X and Y windings are so configured that, when

formed by the inhibit windings, and the prior occur-

half-select value write currents are passed through

rence of a read cycle which put all the cores in the

each, their resultant magnetic fields add in the core

"0" state.

locations of the selected storage cell.

at their point of intersection.

This is per-

Their combined (full-

select) current then ensures that the selected core is
left in the 1 state.

Each inhibit winding, shown as a broken line on
Figure 4-8, passes through all cores on a particular

In the PDP-8/L core memory the X2 windings of all

plane.

12 planes are connected in series, as are the Y3

read and write currents flow in opposite directions,

windings.

the half-select value current in the inhibit windings

When X2Y3 half-select write currents

Y2
——

——

@N\—

|
X3

Unlike the X and Y windings, in which the

|
|

f
|

|
||

I
|

READ

INHIBIT

l
|

WRITE

WRITE <—X——>READ

|
INHIBIT

SENSE

WINDING

Figure 4-8

Simple Core Memory Plane

4-15

always flows in the same direction.

The magnetic

field generated by the inhibit current of a value and

MB for restoration to its original location during the
write portion of the memory cycle.

polarity which effectively cancels the field generated by the Y-axis half-select write current.

This

prevents the setting to the 1 state of any core through

4.,12.3 Address Selection

which inhibit current is flowing.

The memory selector switches decode the address

Each of the 12 inhibit windings is connected to the
output of an inhibit driver circuit. Each driver, in

specified by the MA and select the proper source
and return lines for both the X~ and Y-axes. These

turn, is controlled by the output of one bit of the

memory buffer register, which contains the data to

selection circuits are shown on Drawings BS-8L-015 (X-axis selection), and BS-8L-0-16 (Y-axis

be stored in memory. When the write operation com-

selection) in Volume Il of this document.

mences, each inhibit driver connected to an MB bit

ity of the magnetic field applied to the cores of the

containing a 0 is activated. The resulting half-current
value output of the driver then prevents the writing of
a logic 1 in its assigned core plane. The MB bits
containing logic "1s" disable their respective inhibit
drivers. This allows the cores pertaining to these bits
to have "1s" written into them. The content of the

addressed cell is determined by the direction of

MB is therefore written intact into the selected corememory storage cell.

The polar-

current flow through the core read/write windings.
It differs for a read or write cycle. The read/write
current selection circuits are shown on Drawing

BS-8L-0-13 (Memory Control).
Figure 4-9 provides a combined and simplified version
of these two drawings showing the selection of a Y-

axis memory cell and the method of determination of

read/write current direction. The drawing assumes a
To read out information contained in the 12-bit X2Y3

content of 0 in bits 6 through 11 of the MA, address-

memory cell, half-select read currents are passed
Since read

ing cell 00 on Drawing BS-8L-0-16.

through both the X2 and Y3 windings.

current flows in the opposite direction of write current,
all cores in the X2Y3 cell previously set to the 1state
are switched to the O state.

NOTE

Cores already in the 0

state are, of course, unaffected.

The component designation numbers used in

A sense amplifier circuit is provided for each of the

assist in this discussion and do not relate to

12 core planes in the memory.

actual designations.

Figure 4-9 have been arbitrarily assigned to

The input to edch

amplifier is a sense winding which passes through
every core on the associated plane.

If, during the

the 1 to O state transition, the flux change induces a

With a read operation in process, the READ (1) line
will be affirmed enabling gates 3 and 6. The outputs

current in the sense winding of that plane.

of these gates turn on both Q3 and Qé.

read operation, the addressed core in a plane makes
This

current develops a 20-30 mV pulse at the input to
the sense amplifier. This input is amplified, shaped,
and after threshold detection is used to set a SENSE
flip-flop connected to the output of the sense ampli-

This estab-

lishes a positive source and negative return for the
windings of all Y-axis cores serviced by address-

selection gates 1 and 2.

This is the proper polarity

and current direction for a read operation.

fier when STROBE FIELD O is generated.

With MAO6-11 =0, gates 1 and 2 have been enabled,

Addressed cores which were already in the O state,
when saturated by the full-select read flux, will
induce a limited amount of noise into their sense
winding.

The voltage level produced by this noise
(in the order of 5 mV) will be insufficient to activate
the sense amplifier associated with that plane. The
SENSE flip-flop for that bit will therefore remain

clear, indicating a logic 0 in that location.

and both Q1 and Q2 will conduct.

Current then

flows through D1 and Q1 to D8.

The read current
then passes through the winding of the cores on the
Y-axis of 00 attempting to switch the cores to the 0

state.

There are 12 X 64 cores along this Y-axis;

one for each bit and each X-axis.

The read current

then passes through D4, bypassing Q2 and returns to
the memory supply (=) through Q6. The current does
not pass through the cores on the 01 through 07 and

Since this type of readout destroys the content of the

addressed cell (by switching all cores to Os), the data
stored in the Sense Register will be transferred to the

10 through 77 Y-axis because of back biased diodes
within the matrix, and on the address selection

switches (Drawing BS-8L-0-16).

In a write operation, Q4 and Q5 would be turned on

stated, each core through. which write current passes

by gates 4 and 5, reversing the direction of current
flow. The address selection path, however, remains
the same through the core winding on the Y=-axis of
00. The new current direction (write) attempts to
set the cores to the 1 state. As has been previously

will be set to the 1 state unless the inhibit driver
associated with that core has been activated by the
sensing of a logic 0 in that particular bit-position of
the MB.

AXES

Y10-Y70

fll

ON AX1S YOO
ALL CORES

%oe
p

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t—e

e
D5

ifoe

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MAO6 (0)

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c228

+3V

MAOB8(0)

MAO9(0)

MA10(0)
MA11(0)

READ (1)

WRITE (1)

Memory Address Selector or Read/Write
Current Control

4-17

D | R

228

MEMORY SUPPLY (+)

|
l
|
|
|

|
|
l
|

B MEM ENABLE

Figure 4-9

|
|
|
|
|
l

YR’ETURN

MAOT(0)

T T T

MEMORY SUPPLY

(-)

ST FLTR

ouTPUL

OUTPUT

MFTSO

MFTPO

BENEN =

KEY

4——

SWITCH

BUMPS,

INTEGRATING

[—

OPERATIONS -MANUAL

FLTR

CONTACT BOUNCE

CIRCUIT

FUNCTIONS

ETC

RENDERS 100 MS DELAY

(IN

—»0OUT)

MFTSO

~N==-- ~=-— - —% TO SS

:14—— 2us DELAY: (MFTP1eMANUAL PRESET)
o
1

J—

L_il

—

MFTSH

]

2 us

—

SIDE

OF FF)

fl:"‘. -— — — %

TO SS

]

MFTP1

[—

::4— 2 us DELAY
= {MFTP2)
"

_1_—

MFTS?2

2us

(1SIDE OF FF)
o)

MFTP?2

STANDARD

PULSE

150ns*50ns

MFTS3

Figure 4-10

Manual Function Timing Diagram

4-18

SECTION IV

2 ps to generate MFTP2 which clears the MFTS2

DETAILED PROCESSOR THEORY

flip-flop. The MFTS2(0) level then generates the
MFTS3 timing level through a NAND gate.

This section describes in detail the computer timing,
data flow, and the generation of the instruction set.

This detailed discussion of theory enables the service
technician to bridge the gap between the engineering
drawings and the various logic functions.

The applications of the manual function timing levels
and pulses are described with the key functions.

4.13.2

Manual Operations

The following keys and switches are provided on the
operators' console:

START, STOP, LOAD ADDR,
CONT, EXAM, DEP, SING STEP, MEM PROT,
DATA FIELD, INST FIELD, and the Switch Register.

4.13 TIMING

The following paragraphs discuss the internal timing
of the processor.

4.13.1

Manual Function Timing Generator

When the computer is initially started, or when data
is manually deposited, examined, or continued, or
the memory addressed, the processor and/or memory
cycles are entered by application of the Manual
Function Time signals. These signals include the
time=-state levels MFTSO, MFTS1, MFTS2, and MFTSS3,
and fiming pulses MFTPO, MFTP1 and METP2 (Draw-

ing BS-8L-0-2). The levels and pulses are independent from, and not to be confused with, the processor
timing-generator signals.

Figure 4-10 shows the timing relation-

ship between the manual timing signals.

When any of the levels KEY LA, KEY ST, KEY EX,
KEY DP or KEY CONT are activated by pressing
one of the associated keys, a low-to-high level
transition occurs. The transition is smoothed by an
integrating filter which eliminates the noise gener-

ated by the closure of the key.

To perform this

function, a 100 ms delay is incorporated as part of

the filter.

which consists of a bank of 12 switches.

These switches, used singly or in combination, permit
manual intervention to start the program, stop the
program, load data into a selected memory location,
examine the contents of a memory location, and run
the program step-by-step for troubleshooting the
system, or debugging new programs.

The following paragraphs contain detailed descriptions of the main control switches.

The DATA and
INST FIELD switches are described with extended
memory operation.

The MEM PROT switch function

is described in Paragraph 4.15 of this chapter.

The generator and the

manual timing signals are described in the following

paragraphs.

All are single switches with the exception of the SR

The filter output activates the ST (Schmitt

LOAD ADDR - The memory location to be addressed
is toggled into the switch register, and LOAD ADDR

keyed.

This clears the major state register. MANUAL
PRESET, which performs this operation, is generated
by the MFTPO pulse when LOAD ADDR is pressed.
No further operations occur until MFTS2 when the
address toggled into the switches is loaded into the

PC and MA. This occurs through the generation of
an SR ENABLE signal (Drawing BS-8L-0-4) a MA

LOAD signal at MFTP1 and a PC LOAD signal at
MFTP2 (Drawing BS-8L-0-6).

Trigger) which combines with RUN (0) to generate

‘MFTS0. The RUN (0) level controls the timing generator by preventing manual time levels and pulses from
occurring if a key is pressed when the computer is
running.

MFTSO is inverted to produce MFTSO which

sets the MFTS1 flip-flop.

MFTSO also combines with

Deposit (DEP) - If data is to be manually loaded into
memory, the starting location is placed in the PC, as
described with LOAD ADDR, and the data loaded,

word-by-word through the SR (Switch Register) by the

action of DEP.

KEY EX + DEP to enable clearing of the RUN flip-

flop during T3 of the processor cycle.
Timing level MFTSO generates an MFTPO pulse.

This
pulse is delayed 2 ps to produce MFTP1. The MFTPI
pulse sets the MFTS2 flip-flop which clears the MFTS1
flip-flop ending that time state. MFTP1 is delayed

Pressing DEP clears the major state registers during
MFTO by generating the MANUAL PRESET level.

Manual time-pulse MFTPO generates MANUAL PRESET when DEP is pressed.

During MFT1 the contents
(starting address) of the PC are transferred to the MA.
The generation of the PC ENABLE signal (Drawing

BS-8L-0-4) by MFTS1-KEY STHX+DP, and the MA
LOAD signal (Drawing BS-8L-0-6) by MFTP-KEY

stops. This permits the operator to examine the
contents of the location addressed by observing the
MB indicator lights located on the console panel.

STHEX+DP perform this transfer operation.
During MFT2, the address in MA is incremented and

During the write portion of the memory cycle, the

transferred back to PC, leaving the current address
in MA and placing the next consecutive memory

content of the MB containing the word examined is
restored to the original memory location. Thus, the

address in PC.

content of the examined address remains in the MB

This transfer is accomplished by an

MA ENABLE level (at MFTS2), and a PC LOAD

and in the memory location.

pulse (at MFTP2).

address examined may be modified through the use of
the Switch Register switches and DEP. It should be

The address is incremented by the

insertion of a Carry into the adder of the least-significant bit during the transfer of the address into PC.

The content of the

started to permit loading of the SR data into the

noted, however, that as part of the cycle which
extracted the data from memory, the PC was incremented by one to set up the address of the next instruction. The next word, therefore, would be loaded
into the core-memory address next in sequence to the
address of the presently displayed word. The 12-bit

currently addressed memory location. The actuation
of any manual key, except LOAD ADDR, generates

SR and LOAD ADDR must therefore be used to set the
PC back to the address of the displayed word prior to

a MEM START pulse at MFTP2 (Drawing BS-8L-0-2),

insertion of the new word.

This occurs by generating a CARRY INSERT level
(Drawing BS-8L-0-5) during MFTS2,
During this transfer operation the memory cycle is

initiating the memory cycle.

START - Pressing START initiates execution of a program previously loaded into core memory. When this
key is pressed, MFTPO is combined with the KEY ST
level to generate the INITIALIZE and INITIALIZE
signals (Drawing BS-8L-0-2) which clear the teletype circuits and initialize the machine. The MFTPO
pulse also generates MANUAL PRESET, which sets the

During MFT3, the actuation of Deposit generates

SR ENABLE (Drawing B5-8L~0-4). This gates the
data as signified by the Address switch positions,
onto the major-register bus. TP2 of each cycle, the
MB LOAD pulse (Drawing BS-8L-0-6), permits MB

to accept the Address register data present on the

major-register bus. During the write portion of the
memory cycle, this data is written into the memory
location specified by the contents of MA ., This completes the deposit cycle.

TS1 flip-flop.

During MFT1, the contents of the PC transfer through
the major register gating network to the MA, and the
MFTS1(0) level clears the IOP flip~flops.

Subsequent data is loaded in sequential memory
locations by toggling the data into the SR and act-

During MFT2, the AC, LINK (Drawing BS-8L-0-8)
and INT ENABLE (Drawing BS-8L-0-7) flip-flops are
cleared and the Fetch flip=flop is set. The memory
cycle is also initiated at this time by the generation
of MEM START (Drawing BS-8L-0-2).

vating DEP. The PC is incremented for each deposit,
making further addressing unneccessary until such
time as access to a non-sequential memory address is
required,

Examine (EXAM) - The actuation of EXAM permits
inspection of the word in the currently addressed
memory location. This sequence is identical to the
previously discussed deposit operation up to the start
of the memory cycle.

The memory signal STROBE is activated during the
memory cycle.

STROBE initiates the automatic se-

quences of the processor by continuing the processor
cycle.

The RUN flip-flop is set by processor time-

pulse TP3, and the program instructions are executed
until either a halt command is encountered, or the
computer is manually stopped.

During the read portion of the memory cycle, the
contents of the address specified, when the LOAD
ADDR key was pressed, are transferred from core
memory to the Sense register. The memory signal
STROBE FIELD 0 allows this transfer and also ends
processor time-state TS1, and initiates TS2. At the
end of T2, time-pulse TP2 generates an MB LOAD

STOP - Pressing the STOP key will halt a program at
the termination of the current cycle.

Operation of

this key generates a KEY STOP level which clears the .
RUN flip-flop at the next TP3 pulse.

Clearing RUN

inhibits generation of the next MEM START pulse pre-

pulse which completes the examine operation by

venting another memory cycle.

transferring the contents of the Sense register to the
MB. Upon completion of this transfer, the processor

data between registers is inhibited after completion

The transfer of any

of the current cycle, preventing loss of data.

4-20

The

operator can examine the contents of the registers
prior to the start of the next cycle.

During processor time=-state TS3 the INHIBIT and
WRITE control flip-flops (Drawing BS-8L-0-13) are
set by the delayed MEM START signal. At the end of

SING.STEP - Pressing the SING STEP switch causes
the program to step one cycle at-a time. The RUN
flip-flop is not set. Subsequent actuation of the

the memory cycle, the INHIBIT and WRITE flip-flops

are cleared and

CONIT key generates a single MEM START pulse, but
prevents the processor from automatic execution of
the program, therefore permitting only a single pro-

MEM DONE is generated.

MEM DONE sets the MEM IDLE flip-flop (Drawing
BS-8L-0-2), The setting of this flip-flop allows the
generation of MEM START (initiating another memory
cycle)and TP4, if RUNs stillset and PAUSE iscleared. Time pulse TP4 clears TS4 and sets TS1, initiat=ing another processor cycle.

cessor/memory cycle to be executed.

4.13.3 Time States

The paragraphs above describe the relationship be-

Four time-state levels (TS1, TS2, TS3, and TS4) and
associated time pulses (TP1, TP2, TP3, and TP4) are
generated during each computer cycle. This train of
levels and pulses is initiated at the start of each memory cycle and terminated upon its completion. The
generation of the time state and time pulses and their
relationships are discussed below and are shown in
Figure 4-11.

tween the PDP8/L processor and memory timing cycles
when the previous cycle initiates the next cycle by
generating TP4 and MEM START.

This assumes that

the PDP-8/L is running. When the computer is
initially started (by pressing START, LOAD ADDRTM,
DEP, or CONT) the processor and memory cycles are
entered in the following manner.

The processor timing cycle is initiated by generating

MANUAL PRESET which sets the TS1 flip-flop, and

TS1, the first time-state produced (Drawing BS-8L0-2), is entered at the end of the previous processor

simultaneously clears the TS2, TS3, and TS4 flip-

cycle by TP4.

of the keys mentioned above except for CONT. When
this key is pressed, a TP4 is forced, setting the TSI
flip=flop.

flops. MANUATL PRESET is generated by pressing any

The memory cycle is also initiated at

this time by generating MEM START (Drawing BS-8L0-2). The duration of TS1 and generation of time
pulse TP1 depends on the memory signal STROBE
which is produced during the Read portion of the
memory cycle. Therefore, the duration, of TS1

By pressing any of the keys above with the exception
of LOAD ADDR, MEM START is generated initiating
a memory cycle.

depends on the memory used and the STROBE delay
adjustment.
During processor time TS1, MEM START initiates the

Although normal computer operation is through the
use of a continuously running stored program, pro-

memory cycle by progressing through a delay chain

ceeding in sequence from instruction-to-instruction,

(Drawing BS-8L-0-13). MEM START is delayed to
generate MEM BEGIN which starts the Read function
by setting the READ flip-flop. The memory signal
STROBE (Drawing BS-8L-0-13) is generated by an

this process must be started manually. The SING
STEP key previously mentioned may also allow com~puter program progression, a cycle at a time, for
maintenance and program debugging purposes.

adjustable delay toward the end of the Read portion

of the memory cycle by MEM START (delayed).
STROBE allows the transition from processor time state
TS1 to TS2, and generates time pulse TP1 (Drawing
BS-8L-0-2). STROBE also clears the MEM IDLE flipflop disabling MEM START.

4,14 1/0 TIMING
The processor timing cycle is interrupted between T3

and T4 to perform an 1/O cycle, if specified by an
IOT (input/output transfer) instruction. During the
I1/0 cycle, up to three pulses (IOPs) can be generat-

When STROBE generates TP1, the processor-timing-

progression continues. TP1 is delayed by 0.15 ps
to generate TP2 which clears the TS2 flip-flop and

sets the TS3 flip-flop.
generate TP3.

TP1 is also delayed 0.4 ps to

The third time-pulse (TP3) clears TS3,

and if the instruction performed is not an input/output
“instruction (IOT), TP3 sets the TS4 flip-flop.

* When LOAD ADDR is pressed, MEM START is

inhibited, therefore, there is no memory cycle.

4-21

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ed, depending on the IOT instruction performed (see
IOT instruction description in Paragraph 4.18.4).

iated logic gates and an IOP register. 1/O START

the PR8/L High-Speed Reader, and others.

same lines as 1/O RECYCLE and ends the cycle by
generating 1/O END which initiates processor time

The IOP generator consists of delay lines with assoc-

The IOP pulses provide control between the processor
and peripheral equipment such as the ASR33 Teletype,

The fol-

lowing paragraphs describe the 1/O timing and the
associated logic circuitry. Refer to Figure 4-12
i llustrating the 1/O timing, and Drawing BS-8L-0-2.

is transmitted through the delay lines, re-enters the

state TS4.

TPS—I_l
1/0 START —l__]

PAUSE —[
]

110 roT—si330msfe-|
I

’

e— 580ns

—

1/0 ON
1/0 STROBE PULSES
OCCUR 580 ns AFTER

_l THE START OF EACH —I

1/0 STROBE

IOP LEVEL

170 RECYCLE

—L_l

f4———— 800ns ———P»
IOP A

IoP B
IopPC

IOP 1

‘

IopP 2

IoP
4

1/0 END

NOTE:

Timing Tolerance+ 12 %

Figure 4-12

1/0 Timing Diagram

The protect function is performed by generating the

When activated, T/O START sets the PAUSE flip-flop

PROTECT level. PROTECT is produced by assertion
of either the MEM ALT 1, MEM ALT 2, or WC(0)
levels combined with TS2(1) and the following signals.

(Drawing BS-8L-0-2) to prevent initiation of another

processor/memory cycle during the I/0 cycle. 1/0
START also triggers the delayed

pulse sequence.

Approximately * 200 ns after 1/0 START, 1/0 ROT is

KEY PROTECT (asserted by the MEM PROT key);

produced, setting the IOPA and 1/O ON flip-flops.

This allows generation of an IOP1 pulse if MB11 is

EMA (enabling the protect function in the basic

set. 1/O STROBE is generated 600 ns later from another tap of the delay line. 1/O STROBE clears 1/O
ON terminating IOP1 and generating 1/O RECYCLE.
1/O STROBE is also used in conjunction with IOP

memory; disabling it if the extended memory field
is added to the system);

pulses to enable AC LOAD (Drawing BS-8L-0-6) for
clearing and loading data from a device into the
accumulator. However, the clearing and loading
operations normally occur as a result of IOP2, and

MAOQO (1) through MAO4 (1) (defining the restricted
area 76004 through 7777g in memory).

indicates the end of the first pass through the delay
lines. This signal feeds back through the same delay

PROTECT. MEM ALT 1 (Drawing BS-8L-0-4) is produced when the MB is altered by executing the DCA
or JMS instructions, by incoming data with a data
break request, or by pressing DEP., MEM ALT 2
(Drawing BS-8L-0-5) is generated when the MB could
be altered by producing CARRY INSERT with the
ISZ instruction, CA INCREMENT or MEMORY INCREMENT with 1 and 3 cycle data breaks, or the

The MEM ALT 1 and MEM ALT 2 levels are produced
in the following manner to allow generation of

IOP4 (refer to Paragraph 4.18.4) 1/O RECYCLE

lines, generating another 1/0O ROT and 1/O STROBE.
On this pass IOPB is set, and IOP2 is produced if

MB10 is active. When the second 1/O STROBE is
generated, another I/O RECYCLE is issued, and another pass through the delay lines occurs.

On the

third pass, IOPC is set by /O ROT, and IOP4 is produced if MB09 is active.

EXAM or DEP key.

The setting of IOPC dis-

ables I/O RECYCLE; however,

another path is enabl-

WC(0) generates PROTECT at the beginning of a 3cycle data break to prevent alteration of the MB.

ed for 1/0O STROBE, and 1/O END is generated. Time

state TS4 is entered by I/O END, and after a 300 ns
delay PAUSE is cleared. This ends the 1/O cycle,
and the processor cycle is continued.
4,15

When PROTECT is active, the following events occur:

MEMORY PROTECT

ILLEGAL REF flip-flop is set by TP2.
ILLEGAL REF (0) is logically ORed with KEY
This clears the RUN flip-flop at TP3.

When the MEM PROT key is activated, access to
memory addresses 7600g to 7777g in the top memory

field is prohibited.

Normally, the RIM and BIN

loader programs are stored in this memory area. When

MB.

these loaders are usually stored in the optional field
in the same area of memory, instead of in the basic
memory field.

AC ENABLE is disabled during the DCA

instruction.

The protect feature ensures that no alteration of the
restricted memory area occurs, either by inadvertent

manual operation, or with program debugging/editThis feature also allows programming

use as a "read only" section of memory, when the
RIM and BIN loaders are shifted elsewhere.

MEM ENABLE 0-4/5-11 is disabled prevent-

ing a data transfer from the Sense register to the

an additional 4K of memory is added to the system,

ing processes**,

SS.

SR ENABLE is disabled for the DEP operation.

CARRY INSERT is disabled (see MEM ALT 2

previously described).

The

following paragraphs describe the protect circuitry

on Drawing BS-8L-0-3.

tion.

*1/O timing references do not include transition time through logic gates, therefore timing

tolerance is +20%.
**The MEM PROT key must be unactuated when

loading data into the restricted area of memory.

4-24

PC LOAD is disabled during the JMS instruc-

4.16

MAJOR STATES

bits 4 through 11 of the instruction.

The process of

address deferring is called indirect addressing because

A total of six major states are provided to perform all

access to the operand is addressed indirectly, or de-

computer operations.

ferred, to another memory location.

These states are Fetch (F),

Defer (D), Execute (E), Word Count WC), Current
Address (CA), and Break (B).

Each major state occurs

in one complete 1.6 us computer cycle.

The Defer state can be entered only from the Fetch

The execu-

state when one of the multiple-cycle instructions

tion of a computer instruction consumes one or more

AND, TAD, ISZ, DCA, JMS, or JMP is indirectly

major states, depending upon the operations to be

addressed (MBO3 = 1).

performed.

is made during T4 time by TP4 in the Fetch cycle.

The following paragraphs describe the

Under these conditions, entry

relationship between the states, their functions and

D SET (Drawing BS-8L-0-3) enables the DEFER flip~-

generation.

flop.

It is generated by the active levels MB03 =1,

and B FETCH (1), and the inactive level IOT+OPR.
Fetch (F) - During this state an instruction is read into

If the multiple-cycle instruction being performed is

the Sense register and the memory buffer at the address

not a JMP command, entry into the Execute state is

specified by the content of the program counter.

The

made from the Defer state.

When the JMP instruction

instruction is restored in core memory and retained in

is performed with no BRK REQ, the instruction is

the memory buffer.

completed and the Fetch state is entered.

The operation code of the in-

struction is transferred to the instruction register for
decoding, and the content of the program counter is

Execute (E) - This state is entered for all memory

incremented by one.

reference instructions except JMP.

During an AND,

TAD, or ISZ instruction the content of the core memThe Fetch state is entered by pressing START.

The

and MFTP2 (Drawing BS-8L-0-2) is produced. This

ory location specified by the address portion of the
instruction is read first into the Sense register and
subsequently into the memory buffer, and the opera-

pulse, combined with Key ST, sets the FETCH flip-

tion specified by bits 0 through 2 of the instruction

Manual Function Time Generator is then activated,

flop.

(instruction operation code) is performed.

During a

DCA instruction, the content of the accumulator is

The Fetch state can also be entered during T4 time,

transferred into the memory buffer and is stored in

by TP4 of a Fetch cycle or an Execute cycle. Entry

core memory at the address specified by the instrucDuring a JMS instruction the content of the

occurs from a single-cycle Fetch cycle including all
of the OPR and IOT commands and the JMP command
when directly addressed.

tion.

program counter is written into the next core memory
address and the address specified by the instruction is

Entry into the Fetch state

occurs from the Execute cycle if BRK REQ occurs.

transferred into the program counter to change pro-

When these conditions are met, F SET (Drawing

gram control .

BS-8L-0-3) is active, enabling the FETCH flip-flop.
F SET is produced when the following signals are

The Execute state can be entered at the conclusion of

inactive:

the Fetch, Defer, Execute, or Break state if there is

D SET, E SET, BREAK OK, and SPECIAL

a PROGRAM BRK REQ.

CYCLE.

In this event the EXECUTE

flip-flop is enabled by the E SET level (Drawing BS8L-0-3).

With a PROGRAM BRK REQ, E SET is

generated by INT OK

If a multiple=cycle instruction is fetched, the follow-

ing major state will be either Defer or Execute. The
multiple-cycle instructions include the AND, TAD,

(Drawing BS-8L-0-7).

Entry into the Execute state can also occur from two

other methods.

1SZ, DCA, JMS, and the indirectly-addressed JMP
instruction. When the above instructions are directly
addressed, the EXECUTE flip-flop is set; when the
instructions are indirectly addressed the DEFER flipflop is set. The following major state entry is executed by TP4 in both cases.

One of these occurs at the conclusion

of the Fetch state when the instruction being performed is a directly~addressed multiple~cycle command.
When the signals MBO3 (0) and B FETCH (1) are active
and JMP is inactive, E SET is generated enabling the

EXECUTE flip~flop.

Defer (D) ~ When a 1 is present in bit 3 of a memory
reference instruction, the Defer state is entered to

The other Execute-state entry method is from the

obtain the full 12-bit address of the operand from the
address in the current page or page 0, specified by

formed.

Defer state when any instruction except JMP is perIn this event, E SET is produced by the

DEFER (1) level and the JMP level inactive.

4-25

Regardless of the source of the Execute-state entry,
the EXECUTE flip~flop is set in the previous major
state during T4 by time-pulse TP4.

The Execute state is the last state that a multiplecycle instruction enters. At the conclusion of this
state the Fetch state is entered again except whenthe
PDP-8/L acknowledges a device requesting any type

same location.

The Break state immediately follows

the Current Address state.

Since the only entry path to the Current Addressstate
is by progressing through the Word Count state witha
3-cycle data break, the CURRENT ADDRESS flip-flop
is set during T4 time by TP4 when the WORD COUNT
flipflop is reset (Drawing BS-8L-0-3).

of break request at this time.

Word Count (WC) - This state is entered when an
external device supplies signals requesting a data
break and that the break is a 3-cycle break. When
this state occurs, a transfer word count in a core
memory location designated by the device is read into the memory buffer, incremented by 1, and rewritten in the same location. If the word count overflows,
indicating that the desired number of data break

transfers will be enacted at the completion of the
current break, the computer fransmits a signal to the
device. The Current Address state immediately follows the Word Count state.

Break (B) - This state is entered to enact a data transfer between computer core memory and an external
device, either as the only state of a 1-cycle data
break or as the final state of a 3-cycle data break.
When a break request signal arrives and the cycle

select signal specifies a 1-cycle (3-cycle) break,

the computer enters the Break state at the completion
Information transfers occur
between the external device and a device-specified
core memory location, through the memory buffer.
When this transfer is complete, the program sequence
resumes from the point of the break. The data break
(one or three cycle) does not affect the contents of
the accumulator, the link, or the program counter.
of the current instruction.

The Word Count state is entered at the end of each
major state excepting the Current Address or the
Word Count States when there is a request for a 3cycle data break. The request is acknowledged
dwing T4 time.

The Break state is entered by the active B SET level
and time pulse TP4 in the final major state of the
current instruction. In this event, B SET (Drawing
BS-8L-0-3) is generated by the inactive BREAK OK
level. Synchronization of the asychronous Break
signal (from the device) is done with the BREAK
SYNC flip-flop (which is set during TP1 of either a
one or three-cycle break).

The WORD COUNIT flip-flop is enabled in the
previous major state by the WC SET level (Drawing
BS-8L-0-3). This level is generated by the active
3-cycle and BREAK OK levels. The WORD COUNT
flip~flop is set by time-pulse TP4 in the previous

Entry into the Break state also occurs when there is a
3-cycle data break ., This is the last cycle of this
type of break and Break state entry is entered directly from the Current Address state. When this occurs,
B SET, generated by CURRENT ADDRESS (0) (Drawing BS-8L-0-3), enables the BREAK flip-flop. This
flip-flop is set by time-pulse TP4 in the Current

major state.

At the conclusion of the Word Count state, the

combination of WORD COUNT (1) and time-pulse
TP4 sets the CURRENT ADDRESS flip~flop to the one
- state enacting Current Address entry.

Address state ,

Current Address (CA) - As the second cycle of a 3~
cycle data break, this cycle establishes the address
for the transfer that takes place in the following cycle
(Break state). Normally the location following the
word count is read from core memory into the memory
buffer and incremented by one to establish sequential
addresses for the transfers, and also is transferred to

At the conclusion of the Break state; the Word Count
state is entered if there is still a 3~cycle break, the
Execute state is entered if there is a program break,
and the Fetch state is reinstated if there is no longer
a break request.

the Memory Address register to determine the address

selected for the next cycle. An inhibit signal (from
the data break device) can be supplied to the computer so that the word read during the cycle is not
incremented.

4.17 INTERNAL DATA FLOW

When the content of one of the major registers (MB,
MA, AC, PQC) is transferred or modified, the data flow
proceeds as i llustrated by Figure 4-13. For ease in
understanding the data flow, the sequence of events

Incrementation, if it occurs, occurs

on the transfer to the memory buffer from core memory.

This word is rewritten into core memory at the

4-26

is described in three steps:

(1) source, (2) route,

the content of the Link shifts to ACO1, ACOO shifts

and (3) destination.

two places to the right (AC02), ACOI shifts to ACO3
etc.

4.17.1

Source

As Figure 4-13 illustrates, the 12-bit inter-register

When the AND instruction is performed the contents

transfers are gated into the major register network by

enable gates.

ldentical data shifting into the REG BUS lines

to the AC bits occurs with each bit.

The basic gating levels include:

of the MB are gated in on the lower level, bypassing

the adders.

ENABLE, SR ENABLE, PC ENABLE, MEM ENABLE,

The NO SHIFT signal does not gate the

contents of the MB; however, the AC is gated by this

and AC ENABLE.

All enable gates are partially conditioned by processor or manual function time-state

signal.

levels such as TS2(1), MFTS(1), TS3(1).

applied in the same manner as the NO SHIFT level,

Thus, to allow the MB data to flow to the

REG BUS lines, AND ENABLE is generated, and

The enable

levels allow the data from one register to enter the

for each MB bit.

major register gating network (Drawing BS-8L-0-9)

in a parallel transfer.

4.,17.2

4,17.3

Route

All 12-bit inter-register data transfers enter onto the

After the contents of a register(s) are enabled, the

REG BUS lines 00 through 11 after passing through

data enters the major register gating network includ-

the major register gating network.

ing the adders and input to the REGister BUS lines

(Drawing BS-8L-0-9, all sheets).

Destination

the data input.

The major register

These lines are

The data on these lines is loaded

into the specified register by a clocking pulse, i.e.,

gating network consists of an upper and lower gating
network and adder for each of 12 bits.

if the AC is the destination, the AC LOAD pulse is
There are three other major-register load

generated.

The upper level gating permits the register data to

pulses.

They are:

LOAD.

Each load pulse occurs at the end of a pro-

MB LOAD, MA LOAD, and PC

enter the adders by combining major register levels
such as AC00(0), DATAQO, MEMO3, and other data

cessor or manual function time period by time pulses

inputs with an enable level, or levels, depending on
the operation performed.

bered that time-state levels partially condition the

such as TP3, TP4, and MFTP1.

enable levels, and time pulses partially condition
the load pulses.

The lower level gating network includes the adder
circuitry, and logic gates for shifting operations. The
adder circuits permit propogation of carries, and pro-

As Figure 4-13 illustrates, data can enter the major

vide a method of incrementing data as the 1SZ, 1AC,

and MA + 1-PC functions require whether or not the
operation requires a carry.

It should be remem-

MA, PC, AC, SR, the INPUT BUS, DATA BUS, DATA

The data in the upper

ADDR BUS, or from the Sense (MEM) register.

gating levels passes through the adders to the lower
level gates (Drawing BS-8L-0-9, all sheets).

How-

ever, data transfers from the REGister BUS can flow
only to the MB, MA, PC, or AC.

When any inter-register transfer within the PDP-8/L is
performed, excepting rotate, shift operations, and the
AND instruction,

a NO SHIFT (Drawing BS-8L-0-5)

is generated. NO SHIFT allows data to pass from the
adders directly through the lower level gates to the

When a shift or rotate instruc
-~

tion is performed, specific upper, and lower gating

levels direct data to the adder through a particular
lower-level gate to the bus.

For example, when the

Data flow into core memory always occurs through
the MB under MA addressing control. For example,

when data in the AC is transferred to core memory

(DCA instruction), the AC data transfers to the MB
The

through the major-register gating network .

contents of the MB are sampled, inhibited if necessary, and written into memory.

The contents of the
MA determine the address location in which the

RTR instruction (rotate every AC and Link bit right

Write operation occurs.

two places) is performed, AC ENABLE and DOUBLE

memory location are transferred to the MB, the data

When the contents of a

RIGHT ROTATE levels are generated (Drawing BS-

flow occurs through the Sense Amplifiers into the

8L-0-5).

AC ENABLE allows the AC data into the

SENSE register.

adders.

DOUBLE RIGHT ROTATE directs each adder

output two places to the right.

For the RTR command,

The data then transfers to the IR
for decoding, and through the major register gating

network to the MB.

4-27

The normal mode of PDP-8/L operation is execution

The data flow from outside the major registers to one
of them, occurs through the INPUT BUS for devices
such as the Teletype and through the DATA, and
DATA ADDR lines for DATA BREAK devices.

of a prestored programmed instruction sequence. A
program interrupt can modify programmed operation,
or a data break can temporarily suspend programmed
operation. A program interrupt transfers program
control from the main program to a subroutine to

effect an information transfer with an 1/O device or

4.18

peripheral equipment. A data break is an automatic
operation suspending the main program for one or

OPERATING INSTRUCTIONS

three cycles to permit a high-speed 1/O device to

The following paragraphs describe in detail, the

exchange information with the core memory.

dynamics of the computer operations.

CORE
OUTPUT

INHIBIT

CORE

SENSE

STROBE_ | AMP'S

MEMORY

DRIVERS

X AND Y
SELECT

INHIBIT

|
|

of sense res,

memoRY TiMING
AND

CONTROL

CARRY O0OUT flER

ENABLE

CARRY

iNserT | &

GATES

LOAD

GATES

(3)

MA
MAJOR

L | ac

REGISTERS

INPUT

BUS

DATA

ADDR

MEM

DATA BREAK

DATA

FACILITY

EXTERNAL
OPTIONS

REG. BUS (2)

l———> CP

|INTERNAL|
OPTIONS

CONTROL

CENTRAL

PROCESSOR

TELETYPE

CONTROL

MAJOR

TIMING AND
CONTROL

STATE

GENERATOR

LOGIC

NOTES:

OPTIONS

THREE STEP
1. SOURCE

OPERATION

2. ROUTE
3. DESTINATION

Figure 4-13

4-28

Data Flow

4.,18.1

Instructions

In effect, each AC bit is compared with the corresponding memory~cell bit.

The following explanations of the functions performed

Only when the AC bits

corresponding to the addressed memory—cell bits are

during the execution of each instruction assume that

both a 1 will the particular AC bit remain a 1 at the

the PDP-8/L is energized and is operating normally

end of the operation.

The logical AND is therefore

under control of the main program.

a transfer of binary Os.

The original contents of the

Each explanation
begins at the start of the Fetch cycle, when the

AC are lost.

address of the instruction is in the MA and a memory
read operation is initiated.

Instructions performed by the PDP-8/L are either

The sequence of events listed below describe the

memory reference instructions or augmented instruc-

order in which the AND instruction is enacted. The
events described in a through k are common to all

tions.

A memory reference instruction contains an

operation code (in bits 0 through 2) and an address in

memory-reference instructions.

core memory at which the operation is to occur (in

bits 3 through 11).

An augmented instruction is

used when the operand is already in a register such

as the AC; in this case, no memory address is requir-

instructions at the completion of the last instruc
-

ed.

tion performed.

Bits O through 2 of an augmented instruction

In all cases, the FETCH flip-flop

is set during T4 by time-pulse TP4.

contain the operation code which determines the
general class of the instruction.

The Fetch state is always entered with all

Bits 3 through 11 of

the instruction contain information which permits the

required operations to occur during the two or three

during times Tl and T2 are the same.

With all instructions the functions that occur

execution time states of a single (Fetch) cycle.
c.

Operations performed in this manner are said to be
"microprogrammed,
" since several such operations

During TS1 of the Fetch cycle, the MA is

incremented and its contents transferred to the

PC by TP1.

may take place during a single instruction.

This will provide the address of the

next instruction.

4.18.2

Memory Reference Instructions

ister at this time.

The format of a memory reference instruction appears

in Figure 4-2,

With the exception of JMP, instruc-

Execute.

The Sense bits 0

through 2 are also enabled to the IR.

Fetch and

Time=-pulse

TP2 loads the Sense bits O through 2 into the IR

Instructions which reference any other

page require three cycles:

During TS2 the word in the sense register is

ready to transfer into the MB.

tions which reference a memory address in page O or
in the current page occur in two cycles:

The word in the currently

addressed location is also read into the Sense reg-

and the complete word in the Sense register into

a Fetch cycle in which

the MB.

the instruction word is brought out of memory and

For the AND instruction, the IR will be

loaded with Os because the AND operation code

contains the effective address of the operand in the

is Og.

The contents of the IR (Og) produce the
This level is used by the processor
for input-gating control functions for this instruc-

current page or page 0; a Defer cycle (referto Direct/

AND level.

Indirect Addressing in this chapter) in which the
absolute address of the operand is brought out of

tion.

memory and enters the MA; and the Execute cycle,
in which the operand is brought out of core memory

and operated on.

No operations occur for the AND, TAD,ISZ,

DCA, JMS and indirectly addressed JMP.

The following explanations of memory reference

instructions assume that the instruction is directly

During TS4, Sense register bits 5 through 11

are enabled to the corresponding MA bits, and

addressed; however, the JMP instruction is described

during time=-pulse TP4 these bits are gated into

with direct and indirect addressing as an example.

the MA.

It is also assumed that no break cycle has been initi-

The same enabling and gating signals

affect Sense register bits O through 4 and MA bits

ated.

0 through 4 depending on the status of MB04. This

the contents of the addressed memory cell and the

memory buffer bit determines whether the addressed cell is on the current page (MB04 = 1), or on
page zero (MB04 =0). Ifit is on page zero,

contents of the AC.

zeroes are transferred into MAOO through MAO4.

AND - The logical AND operation occurs between
The result is stored in the AC.

4-29

g. Also during T4 the next major state entry is
determined by the status of MBO3. If this bit
contains a 1, indirect addressing is indicated and

the DEFER flip-flop is set by TP4.

If this bit

contains a 0, direct addressing occurs and TP4 sets
the EXECUTE flip-flop.

Only one major state can

be entered at any time.

The state entered de-

tion code 1q is decoded by the IR to generate the
TAD gating level used by the processor to implement
the TAD operations. The actual two's complement
- add is performed in the Execute cycle in the follow~ing sequence.

a. During the memory strobe portion (T1) of the
Execute cycle, the addend reads into the Sense
register from the addressed memory cell.

pends on the input-gating of each major state
controlling flip-flop during TS4.

memory Write function occurs and the instruc-

b. During T2 the operand in the Sense register
is transferred to the MB and IR for processing

tion is written back into core memory.

and decoding.

Towards the end of the processor cycle, the

When this

is done, MEM DONE is generated, and TP4 is
produced initiating another processor cycle and

clearing TS4.

and applied to the major register input gating net-

MEM DONE also enables another

memory cycle to be initiated.

i .

During T3 the MB and AC outputs are enabled

work .

Carries are generated and propogated in

the adders as required. Time pulse TP3 allows
generation of an AC LOAD pulse during the
Execute cycle of the TAD instruction. ACLOAD
transfers the sum of the AC and MB into the AC.

During the strobe portion of the Execute cycle,

the operand stored at the address currently held by
the MA reads into the Sense register. At TP2 the
operand transfers to the MB.,

During the Write portion of the memory cycle the
operand in the MB is rewritten into the original
address cell. If there is no break request and SKIP =
0, the contents of the PC are loaded into the MA at
this time by TP4. This time pulse also clears the IR
and sets the FETCH flip-flop.

i During TS3 the AND ENABLE level permits
the AND-combining of the AC and MB through the
major register gating network. Time-pulse TP3
sets the AC bits whose register inputs are active

(high), and clears the other AC bits.
k.

This concludes the TAD instruction; the program is
ready to fetch the next instruction from the location
specified by the contents of the MA,

Toward the end of the Execute cycle the

operand, which is unaltered in the AND process,
is rewritten into memory during the Write portion
of the memory cycle.

The operand of other

Increment and Skip if Zero (ISZ) - The ISZ instruction
reads the contents of the addressed memory cell into
the Sense register, and transfers the contents of this
register through the major register gating network with
a carry insert to the MB. If the incremented contents
of the MB are not 0, the program proceeds to the next

instructions such as the DCA, JMS, and ISZ is
altered before it is rewritten.
.

1If there is no break request and SKIP =0, the

contents of the PC are loaded into the MA during
Execute T4 time by TP4.

This time pulse also

clears the IR and sets the FETCH flip=flop. This

instruction. If the incremented contents of the MB
are equal to 0, the contents of the PC increment by
1, and the program skips the next instruction. The
events that occur in performing the ISZ instruction

concludes the logical AND operation; the program
is ready to fetch the next instruction from the
location specified by the contents of the MA.

are listed in sequence below.

Two's Complement Add (TAD) - The contents of the

Operations during the Fetch cycle of an 1SZ

" AC are lost.

instruction are similar to those during the Fetch
cycle of an AND instruction. Refer to events a
through h of the AND instruction. The only difference between these two instructions during the
Fetch cycle is the operation code 28 decoded by

in the same manner as the AND instruction.

During the Fetch cycle, the TAD instruction operates
Refer to

the memory location signified by the contents of

events a through h for these operations.

the MA is transferred into the Sense register.

addressed memory cell add to the contents of the

AC in 25 complement arithmetic.

The result of the

addition is stored in the AC,and the operand (addend)
is restored to memory. The original contents of the

the IR for the ISZ instruction.

The opera-

4-30

During T1 of the Execute cycle, the word at

During T2 of the Execute cycle the Sense register is transferred to the MB through the major

to generate AC ENABLE during T2.

contents of the AC to transfer through the major reg-

The levels TS1(1), DCA, and B EXECUTE(1) combine

The incrementation

occurs through the application of a carry insert

ister gating bus to the MB.

level to the adder of the least significant bit
during the transfer operation. If the carry insert

At the end of T2, time-pulse TP2 generates an MB

level produces a carry out from the most significant bit, indicating an all 0 condition in the
register, the SKIP flip-flop is set at TP2,
d.

This allows the

LOAD pulse that allows the contents from the AC to

be loaded into the MB.

No event occurs during T3 of the Execute

cycle.

However, if the SKIP flip-flop has been

set, the PC is incremented and transferred to the

MA .

LOAD pulse; however, no enable levels are
generated. This lack of enable levels places

This causes the next sequential instruction

to be skipped during T4.

If the SKIP flip-flop

During T3, time=-pulse TP3 generates an AC

was not set, the contents of the PC are transferred

the equivalent of all Os on the input to the

to the MA without incrementation, resulting in a

major register gating network.

skipping.

pulse therefore, loads these Os into the AC,

The AC LOAD

effectively clearing the register.

During the memory Write pottion of the

memory cycle the incremented contents of the

'MB are written into the address cell from which

the contents of the MB are written into the core

they were removed.

location specified by the MA. During T4, if
neither a break request not a skip = 1 level is
present, the contents of the PC are transferred to

Time-pulse TP4 (at the end of TS4) sets the

During the Write portion of the memory cycle

the MA to specify the next desired core location.

FETCH flip-flop if there is no break request.

Time pulse TP4 sets the FETCH flip-flop allowing
entry into the Fetch cycle.

' Deposit and Clear Accumulator (DCA) - The DCA
instruction deposits the contents of the AC into the
addressed memory cell and the AC clears. The origin-

al contents of the addressed cell are destroyed.

The

Jump to Subroutine (JMS) - The JMS instruction

sequence of events that occur in performing the DCA

provides an exit from the main program into a sub-

instruction are listed below.

routine.

The contents of the PC (current program

count) incremented by 1, are written into the core
memory address specified by the JMS instruction.

That address transfers to the PC and increments by 1;

Operations during the Fetch cycle of a DCA

this incremented address fetches the first subroutine

instruction are similar to those occurring during
the Fetch cycle of the AND instruction.

instruction during the next instruction cycle. When

Refer to

events a through h of the AND instruction.

the subroutine ends, the main program is re-entered

The

by a jump indirect to the address specified by the

operation code for the two instructions differs.

original JMS instruction.

The operation code 3g decoded by the IR for the
DCA command generates a DCA level which is

and transferring this count into the PC causes the

used as a gate~enable signal for this instruction.

main program sequence to continue.

The sequence of events in performing the JMS instruc-

b. During T4 of the Fetch cycle the EXECUTE
flip-flop is set to allow entry into this state.
c.

The contents of that

address are now the incremented main-program count;

tion are listed below.

In addition, to further clarify

the JMS operation,a sample program with this instruction is given in Table 4-1,

During T2 of the Execute cycle, the DCA

level combined with B EXECUTE (1) inhibits

MEM ENABLE 0-4/5-11,

This prevents the

contents of the Sense register from transferring
to the MB.

Therefore, the contents of the

addressed cell are lost.

Operations during the Fetch cycle of a JMS

instruction are similar to those occurring during

4-31

b. During TS1 of the Fetch cycle for instruction
21g, the contents of cell D21g reads into the
Sense register. Upon completion of the Read

the Fetch cycle of the AND instruction.

Refer
to events a through h of the AND instruction.
The operation code for the two instructions
differ. The operation code 4g decoded by the
IR for the JMS command generates a JMS level
which is used as a gate-enable level for this
instruction.

During T1 of the Execute cycle no operations

occur,

c. During T2 of the Execute cycle the contents
of the PC are transferred to the MB if there is
no skip condition (SKIP = 0). In order to perform
this operation, PC ENABLE and MB LOAD are
generated. PC ENABLE allows the contents of
the PC to enter the major register bus. The
contents of the bus are loaded by MB LOAD into
the MB.

operation the Sense register contains JMS/0/100
(41008) .

The JMS operation code 4g is in bits 00 through 02;

page O is specified by bit 03 = 0 (denoting a direct
address) and bit 4 = 0 (denoting page 0). Bits 05
through 11 specify location 100g (of page 0). Also
during TS1 the contents of the MA increments as it
transfers into the PC,

c. During T2, the contents of the Sense register
(the JMS instruction) transfers into the MB. Bits

00 through 02 transfer into the IR where they are
decoded to produce the JMS level.
d.

d. During T3, the current address is incremented
by one and transferred to the PC. To do this, the
MA ENABLE, CARRY INSERT, and PC LOAD
signals are generated. MA ENABLE allows the
contents of the MA to enter the major register
network bus. CARRY INSERT adds one to the
contents of the bus. Finally, PC LOAD loads the
PC with the incremented contents of the bus.

No operations occur during TS3.

e. During T4 of the JMS Fetch cycle, the
contents of the MB (the JMS instruction) is
written back into its original core location (D2]8).
f. At TP4, the contents of bits 05 through 11
are transferred to the corresponding bits of the
MA and, because bit MBO4 =0, bits MAOO
through 04 are cleared to indicate page 0. The
MA now contains (0/1 00)g, the address specified
by the JMS instruction.

e. During the Write portion of the memory cycle,
the contents of the MB (described in event ¢ of
this instruction) are written into memory at the
location specified by the JMS instruction.

During T1 of the JMS Execute cycle, the

contents of core location (0/100g), as specified

f. During T4 the FETCH flip=flop is set by TP4
if there is neither a break request nor a SKIP =1

by the address portion of the JMS instruction,

(which is now in the MA), reads into the Sense

level.

During T2 of the JMS Execute cycle, the

contents of the PC, which is D/22,, (address of

The events above describe the JMS operation. These
events are easier to understand, however, if a concrete example is given. The following events describe the sample program of Table 4-1., The program
sequence assumes that the main program is in page D
of memory (current page), and that the 21st instruc
tion is JMS directly page O location 100,. The
following conditions are also assumed for this ex-

the next sequential main-program instruction)
transfers into the MB. The SKIP flip~flop is
assumed cleared.

During T3, the contents of the MA, (0/100g),

which is the current subroutine address, is incremented by one as it is transferred to the PC.

ample: memory pages are designated 0, A, B, C,
D, E; each page contains locations designated 0
through 1774; and the subroutine is in page O starting
at location 101g.

i. During T4, the contents of the MB (D/22g)
are written into memory location (0/100,). At
TP4, the contents of the PC (0/101g) transfer to
the MA to select the core memory location con-

taining the first active instruction of the subroutine. At this time, the JMS Execute cycle is
terminated and the Fetch cycle of the first instruc-

a. During T4 of instruction 20g in the main
program, the PC contains the address of the
next instruction, location 21g in page D (current
page). This address is transferred into the MA,

tion of the subroutine entered.

4-32

main-program instruction (D/22;). By this means

k. During T1 of the Fetch cycle, the first instruction of the subroutine reads from core location

(0/101g) into the Sense register.

the subroutine is terminated and the main program
re-entered at the point at which it was interrupted.

The programthen

proceeds to execute the subroutine.

I. The last instruction of the subroutine must be a
jump indirect to the location originally specified

by the JMS instruction, in this case (01 008). As
noted in step | above, location (0/100g) contains

the address in core memory of the next sequential

Jump (JMP) - The JMP instruction links two program
instructions that are executed consecutively when the
instructions are not in sequential locations. This
instruction is commonly used to link a program together when the program length extends over more

Table 4-1

Example of Register Contents During JMS Instruction

PC Contents

Cycle

Fetch or

Time

TS4

0-4

5-11

(page)

(location)

MB Contents

0-4

D/20 Unknown

5-11

Unknown

MA Contents

0-4

5-11

Execute

Fetch

Command

PC-MA
1-F

TS1

D/21

JMS/0/100

Unknown

MA+1-PC
Memory ~MB

TS2

D/21

JMS/0/100

MEM-M
MEM~1B

TS3

No Operations

TS4

D/21

JMS/0/100

MB-Memory
MEM-MA
1-E

Execute

TS1

0/100

xxx/x/xxx

TS2
TS3

D
0/101

0/100
0/100

xxx/x/xxx

TS4

0/101

100

Memory~MB
PC-MB
MB-MEM

D
D

22
22

0
0

100
100

100

MA+1-PC

0/100

MB-MEM
PC-MA
1-F

Fetch

TS1

102

0/101

1st subroutine
instruction

4-33

101

MA+1~
Memory -+

than one page (1 77g locations) of core memory. JMP

is also extensively used in program loops such as

bits 05 through 11 of the Sense register transfer

counting and comparing in conjunction with the skip

to the corresponding bits of the MA and bit 04
of the MB is examined. 1f MB04 = 0 (absolute
address of operand on page 0) MAOO through
MAO4 arecleared. If MB0O4 =1 (absolute address
of operand on current page) bits 00 through 04 of
of the MA (current page address) are circulated
out of, and back into, the same MA bits. Also
during T4, the JMP instruction is restored, intact,
in its original core memory location. At the end
of T4 the DEFER flip-flop is set allowing entry
into the Defer state.

instructions.

The JMP instruction contains either the absolute corememory address of the next operand (direct addressing)
or the address of a location containing the absolute
core-memory address of the next operand (indirect
addressing). When the next operand is located either
in the current page or page zero of memory, direct’
addressing is used requiring only a single fetch cycle
to extract the operand and prepare for its execution.
If, however,
the next operand is located in any other
page in memory, its 12-bit absolute address must be
stored in either the current page or page zero at alocation specified by bits 05-11 of the JMP instruction.
This is known as indirect addressing, and requires
both a Fetch cycle and a Defer cycle to extract the

For an indirectly addressed JMP during T4,

The following events relate to the JMP instruction when the Defer state is entered. This state
can be entered with any of the memory reference
instructions and is not restricted to JMP instruc-

tion exclusively.

operand for processing.

The events that occur in performing the JMP instruction are listed in sqquence below.
a. Operations occurring during T1 and T2 of the
JMP Fetch cycle are identical to those events of
the AND instruction in the same time periods
except for the operation code 5g decoded by the
IR for the JMP instruction. Refer to events a
through d of the AND instruction.
b.

Operations during T3 of the Fetch cycle
depend upon whether the JMP specifies direct
(MBO3 = 0) or indirect (MBO3 = 1) addressing.

indirect addressing is indicated no operationsoccur

during T3.

If direct addressing is indicated, the
specified address (SENSE 05 through 11) is loaded
into the corresponding bits of the PC. If the instruction specifies that the operand is located on
page 0 (MBO4 = 0), bits 00 through 04 of the PC
are cleared.

If, however, the instruction specifies that the operand is in the current page (MBO4=
1) bits 00 through 04 of the MA are transferred to

the corresponding bits of the PC,
c.

The following events occur during T4 of the
Fetch cycle of a direct address. JMP (if neither
a break request nor a skip is specified):

e. During T1 of the Defer cycle, the absolute
12-bit address of the operand is read from the
memory location specified by the JMP instruc-

tion (or any of the memory reference instructiong
into the Sense register.
f.

During T2, the contents of the Sense register

are transferred to the MB if an Auto Index is not

required. When there is an Auto Index, the
contents of Sense are incremented by 1 in the
major register gating network before loading into
the MB. An Auto Index occurs when a memory
reference instruction such as the JMP command
is indirectly addressed in one of the locations
10g through 17g on page zero of memory.
g.

During T3 the contents of the Sense register

are transferred to the PC (intact if an Auto Index
is not specified, and incremented by one if an
Auto Index is specified).
h.

During T4 if no break request is specified, the

contents of the PC are transferred to the MA . Also
during T4 the contents of the MB are written back
info memory at the original location (intact if
Auto Index was not performed, or incremented by
1 if Auto Index was performed). At the end of T4
the FETCH flip-flop is set allowing Fetch cycle
entry for the next instruction performed.

During

the ensuing Fetch cycle the operand is read from
memory and its operations begun.

The PC transfers to the MA, the JMP instruction
is restored intact, to its original core memory
location, and the FETCH flip-flop is set. The
operand is removed from core-memory during the
next machine cycle (Fetch) and implemented.

4.,18.3

Direct/Indirect Addressing

Six of the eight basic instructions in the PDP-8/L
repertoire are designated as memory-reference instruc-

tions.

These instructions (AND, TAD, ISZ, DCA,

is extracted from memory, only bits 5 through 11 are

JMP, and JMS), as part of their function either write

transferred to the MA.,

into or read from memory.

a 1, bits O through 4 of the MA are left unchanged

If bit 4 of the instruction is

and the next location addressed is on the current page.

The first three bits (0-2) of these 12-bit instructions

If, however, bit 4 isa 0, bits 0 through 4 of the MA

contain the operation code designating the specific

are cleared.

function to be performed.

tion on page O of the memory.

The remaining nine bits

This addresses the bit 5 through 11 loca-

location involved in the required operation.

(3-11) are, therefore,available to specify the memory
A com-

Figure 4-14 is a simplified flow chart showing the

plete specification of any one of the 4096 locations

sequence of operation of both the direct and indirect

in the basic PDP-8/L memgory, however, requires the
use of 12 address bits (2" “ = 4096).

addressing functions.

To minimize the

number of instructions required to access memory,

therefore, both direct and indirect addressing is used

4.18.4 Augmented Instructions

in the PDP-8/L.

The two classes of augmented instructions used in the
The memory is organized into 32 pages (or blocks),

PDP-8/L are:

each containing 128 consecutive memory locations.

has the operation code 64

These pages are numbered 0 through 378.

and the operate instruction
(OPR), which has the operation code 7,. Augmented

The speci-

fication of any of the 128 locations on a particular

instructions.are single-cycle (Fetch) instructions

page requires only seven bits (27 =128). Bits 5

which initiate various operations as a function of bit

through 11 of the memory-reference instructions are

used for this purpose.

The input/output transfer (IOT) which

mi croprogramming .

With the operation code

carried in bits O through 2, bits 3 and 4 remain to

Input/Qutput Transfer - The IOT class of augmented

specify the direct/indirect addressing mode of opera-

instructions generate pulses (IOP pulses) that allow

tion,

the PDP-8/L processor to communicate with both the

The status of bit 3 of the instruction specifies whether

internal and external devices. The IOP pulses generated by performing this instruction are used for timing,

direct or indirect addressing is to be performed. When
bit 3 = 0 direct addressing is specified, i.e., the

control applications, synchronization, and data transfer functions,

location specified in bits 5 through 11 contains the
operand upon which the function described in bits

The format of the 1OT instructions differs from that of

0 through 2 is to be performed.

the memory reference instructions as illustrated in

If bit 3 =1 indirect

addressing is specified, i.e., the location specified
in bits 5 through 11 contains the absolute 12-bit

Figure 4-2.

address of the operand.

device selector circuitry in a given 1/0O device, and

Bits:00 through 02 contain the operation
code (6g), bits 03 through 08 form a code that enables

An additional computer cycle

(Defer) is therefore required to extract the 12-bit

bits 09 through 11 enable the generation of 1OP pulses

which control the data transfer, clearing, and sync-

address of the operand from the specified address.

chronization operations.
The status of bit 4 determines whether the location

The following events describe the operation of the

specified by bits 5 through 11 is on the currently
addressed page of memory, or on page 0 (1 =current

10T instructions.

page, 0 = page 0). Through the use of bit 4, therefore, a memory reference instruction can address 256

Operations during Tl and T2 of the IOT

Fetch cycle are identical to events a through d

locations; 128 in the current page, and 128 in pageO.

of the AND instruction, except for the operation
code 6g decoded by the IR for 1OT instructions

It should be noted that the full, 12-bit absolute
address of the desired location must be present in the
MA to permit access to that location. The 12-bit
starting address of the program is entered into the MA
through the switch register and the LOAD ADDR key
when programmed operation commences. In normal
operation, the PC is incremented during each Fetch
cycle to step the address to the next sequential memory location. When a memory reference instruction

during T2,

The resulting IR generated 10T level

is used in [OP generation and other processor

control functions.

At the end of TS3 of the Fetch cycle, TP3

sets the PAUSE flip-flop and triggers the IOP
generator,

The processor timing sequence is

interrupted between T3 and T4 to allow the 1/0
cycle to occur.

4-35

LOAD STARTING
ADDRESS Y

{SRO-11

—& PCO-1)

}
SET Y INTO MA

(PCO ~11 —&» MAQ-11}

SET FETCH
STATE

INCREMENT

(NOW HOLDS Y + 1}

}
INSTRUCTION

RETRIEVAL

FIRST

RETRIEVE
>

INSTRUCTION

FROM

Y AND SET INTO MB

SET OP CODE
INTO iR

(SENSE 0-2%IRO-2)

EFFECTIVE

@ AED:ESS oF
OPERAND

SET

EFFECTIVE

ADDRESS OF

———»

OPERAND

(Z) INTO MA (SENSE
5-11+ MAS-11)

1S
MB4

YES

0?2

CURRENT

SELECT

PAGE (MAO—5

NOT CHANGED)

SET

(soEf LA%AEEMO

DEFER

STATE

(X) OF OPERANDO
@ :ggglégge — [{_\DDRESS
ROM LOCATION 2 IN PAGE
RETRIEVE

ABSOLUTE

OR CURRENT PAGE

RETRIEVAL

SET

SET ADDRESS OF

EXECUTE

STATE

OPERAND (X) INTO MA
SENSEOQ-11-=MAOD-11

SET

EXECUTE
STATE
RETRIEVE OPERAND
FROM LOCATION Z
IN_PAGE O OR

PAGE

CURRENT

OPERAND

RETRIEVAL

RETRIEVE OPERAND
FROM

LOCATION X

(MAY BE IN

ANY PAGE)

THE

EXECUTE

INSTRUCTION

ON OPERAND

SET ADDRESS OF
NEXT
INSTRUCTION
{(Y+1)

INTO

(PCO—11 —#» MAC-11)

SET

FETCH

STATE

INCREMENT

(NOW HOLDS

Y + 2}

v
RETRIEVE

SECOND

INSTRUCTION FROM
LOCATION Y + 1

Figure 4-14

Direct and Indirect Address Selection,
Simplified Flow Chart

4-36

During the 1/O cycle specific IOP pulses

tion, when set to 1 specifies an RAR (rotate AC and

are generated depending on the status of bits

L to the right one place) operation. Bit 09 similarly
specifies an RAL (rotate AC and L to the left one
place) operation. It is physically possible, by setting

MBO9 through MBI11.

Any IOP pulses that are generated are gated

both bit 09 and 08 to the 1 state, to request an impossible, conflicting operation, i.e., rotate AC and
L both right and left one place simultaneously.

in the device selector of the addressed 1/0 device
to produce 10T pulses.

The IOT pulses control

the operation of the device, effect a transfer of
information between the device and processor, or

Both groups of OPR microinstructions are single-cycle

initiate action in the processor such as clearing

the AC, or incrementing the PC.

(Fetch) instructions.

In addition,

with each IOP pulse generated, 1/O STROBE is

The instruction descriptions contain the primary signals

produced and used within the processor to allow

necessary to perform the specified operations.

AC LOAD (Drawing BS-8L-0-6) to clock data

from the 1/O device into the AC.

Refer-

ence to the mechanization charts indicates where and

“how the primary signals are generated.

Certain IOT instructions are normally combined

For ease of explanation, the signals and conditions

to clear the AC and transfer data to the accumulator in one computer cycle.

The following sequence of events

describe the operations of this class of instructions.

common to most of the OPR instructions are listed be-

This is performed

low.

by generating AC LOAD as described above, and

disabling AC ENABLE (Drawing BS-8L-0-4),
AC CLEAR (Drawing BS-8L-0-4), gated by 1/0
STROBE, disables AC ENABLE, thus Os are loaded

into each AC bit when 1/0O STROBE occurs. Dur-

The operation code is 7g-

Actual AC and L operations occur during T3

of the Fetch cycle.

ing IOP 2 or 4, time data is loaded into the AC by

1/0O STROBE.

The OPR level decoded by the IR serves as

an enabling level, and also combines with MB03

e. Two IOT instructions used with the PDP-8/L
to enable/disable the program interrupt facility.
These instructions ION (6001g), and IOF (60028)

to form OP1 and OP2 levels.

are processor IOT instructions.

such as AC LOAD, that perform the transfer of

When ION is

Time pulse TP3 generates the load signals

performed, the program interrupt facility is en-

data from the major register gating network to

abled by setting the INT ENABLE flip-flop. 1OF
disables the program interrupt facility by ensur-

the indicated register.

ing that the INT ENABLE flip-flop is cleared.

Themajorstate B FETCH (1) and time-state

TS3 signals are used as enabling levels.

Operate (OPR) - The OPR class of augmented instructions consists of two categories of microinstructions

Group 1, and Group 2.

NO SHIFT signal is generated to allow all trans-

The formats of these groups

appear in Figures 4-4 and 4-5, respectively.

In each

fers from the adder of the major register gating

case, bits 00 through 02 contain the operation code
7g.

Except for the rotate OPR 1 instructions, the

network onto the network bus.

Group 1 commands, designated by a 0 in bit 03,

are called OPR 1 instructions.

OPR 1 instructions

g. There is only one OPR 1 NOP instruction
(7000,); however, each bit is discussed in order.
Therefore, several events occur when this in-

perform AC and Link operations such as clearing,

complementing, rotating, and incrementing.

Group

2, designated by a 1 in bit 03 and a 0 in bit 11 are
called OPR 2 instructions. These commands check

struction is performed.

the contents of the AC and Link, and on the basis of

The OPR instructions and their operations are

the results, determines whether the next sequential

described below.

instruction is to be performed or skipped.
a.

During Tl and T2 of the Fetch cycle the

The OPR 1 operations may occur either singularly or

operations that occur are identical to events

in logical combinations.

a through d of the AND instruction.

Care must be exercised,

however, to ensure that contradictory or conflicting
operations are not specified within the same instruc-

tion.

examined to determine whether the instruction

For example, bit 08 of the OPR 1 microinstruc-

4~37

During T3 bit 03 of the OPR instruction is

(5) NOP (no operation). When the 7000g instruction is performed, MBO5 =0, MBO7 =0,
and no other operand exists (refer to instruction
description 1). The L = L circulation occurs and
the contents of the Link are circulated through
the major register gating network and returned

is an OPR 1 (MB0O3 = 0) or an OPR 2 (MB03 =1).
Appropriate levels are generated in the control
circuits to implement the requirements of each
group. The descriptions of the instructions that
follow should be carefully traced in the flow
chart (Drawing BS-8L-0-1) to facilitate understanding of the system operation. The order of
appearance of the instruction descriptions paral lels the order shown in the flow diagram. It
should be noted that, through microprogramming,
operations may be combined during the same

unaltered to the Link.
signals are generated.

(6) CML (complement the Link). When the
7020g instruction is performed, MBO5 =0,
MBO7 =1, and no other operand exists. The 0
side of the Link bit (L) transfers through the
major register gating network into the Link

cycle. For instance; AC
-~ AC (CMA) andL ~L

(CML) may occur in the same instruction to com-

plement both the AC and the Link.

(L = L). This transfer occurs when L ENABLE,
AC LOAD, and NO SHIFT levels are generated.

During T3 when the OPR 1 instructions are
specified (MBO3 = 0) the following instructions
can be performed. They are:
(1)

(7) CLL (clear the Link). When the 7100g instruction is peformed, MB0O5 =1, with no other
operand exists, and a logic O level is transferred
to the Link. The operation is performed by generating AC LOAD and NO SHIFT signals with

When the 7000g instruction is performed, MB04 = 0, MB06 = 0, and
no other operand exists. The contents of the AC
are circulated through the major register and

NOP (no operation).

adder network, and returned unaltered to the
AC (AC =~ AC). This transfer occurs when AC

no enable levels existing.

ENABLE, AC LOAD, and NO SHIFT are gener-

(8) STL (set the Link). When the 71204 instruction is performed, MBO5 =1, MBO7 = 1 and
no other operand exists, the combined operations
of the CML and CLL instructions described in
6 and 7 above occur (L + L »L), The Link is set
to the 1 state by clearing it, then complemen-

ated. The events described in 5 and 9 of the
OPR 1 instructions also occur simultaneously
with the AC circulation.

(2) CMA (complement the AC). When the
7040, instruction is performed, MB0O4 =0,
MBO0& = 1, and no other operand exists. The
0 side of all AC bits (AC) is transferred through
the major register gating network to the AC
(AC = AC). This transfer occurs when the AC
ENABLE, NO SHIFT and AC LOAD signals are

ting it.

(9) NOP (no operation). When the 70008 instruction is performed, MB08 =0, MB0? =0,
and no other operand exists. In addition to the
events described for this instruction in 1 and 5,
the NO SHIFT level is generated. This level
controls transfers of all data from the adder onto
the major register bus. This signal is generated
for all OPR 1 instructions, and is gated by
MBO8 = 0, and MB09 = 0. It should be noted

generated.

(3) CLA (clear the AC). When the 7200g
instruction is performed MBO4 = 1, MB0O6 =0,
and no other operand exists, logic 0 levels are
transferred to all AC bits. This transfer occurs

that the NO SHIFT signal is also generated for
all instructions except for the EAE shift group,
but there is a different path activated.

by producing AC LOAD and NO SHIFT levels,
with no-enable levels existing. This operation
clears (sets all bits to 0) the AC register (0 ~
AC).

(4)

This transfer occurs when

the L ENABLE, AC LOAD, and NO SHIFT

(10)

CLA/CMA (clear and complement the AC).

RAR (rotate the AC and Link right one

place).

when the AC ENABLE, AC ENABLE, NO SHIFT

When the 7010g instruction is performed, MB08 =1, and no other operand exists.
The contents of the AC and L are shifted one
bit to the right. The Link status is transferred
into AC00, while AC11 status transfers into the
Link. The RAR operation occurs when the L
ENABLE, AC ENABLE, RIGHT SHIFT and AC

and AC LOAD signals are generated.

LOAD signals are generated.

When the 7240g instruction is performed MB04
=
1, MB06 =1, and no other operand exists.

The

AC is cleared then complemented (AC + AC ~
AC, set AC = -1), This effectively sets all of
the AC bits to the 1 state. This operation occurs

4-38

(11)

RAL (rotate AC and the Link left one
When the 7004, instruction is perform-

The operations performed during T1 and T2 of the Fetch
cycle of the OPR 2 class of instructions are identical

place).

ed, MBO? =1, and no other operand exists.

to those previously described for those time states in
the AND instruction. The following instruction
descriptions therefore, describe the OPR 2 instructions

The contents of the AC and Link are shifted one
bit to the left.

The content of ACO0 is trans-

ferred to the Link, and the content of the Link
bit is transferred to AC11.

during T3 of the Fetch cycle.

The RAL operation

is performed when LEFT SHIFT, L ENABLE,

(1)

AC ENABLE, and AC LOAD signals are generated.

quential program instruction is skipped. When
the AC =0, the SKIP flip-flop is set to the one

instruction (RTL) is performed, MB10 =1, and
the operand for either the RAR or RAL instruc-

state by TP3, B FETCH (1), OPR, and a skipenable level generated by AND-combination

However, to avoid confliciting

of all AC 0-side outputs.

operations, only one of these operands should
exist at one time.

The RTR command rotates

(2)

the contents of the AC and Link two places to
the right.

Similarly, the RTL command rotates

operand exists.

If ACOO =1, a minus

AC is specified, the SKIP flip-flop is set, and

the next sequential program instruction is skip-

Both the RTR and RTL instructions occur when

ped. This flip-flop is set by a load pulse generated by the TP3, B FETCH (1) and OPR signals.
The skip-enable level is produced by MB05 (1)
combined with ACO00 (1).

L ENABLE, AC ENABLE, DOUBLE RIGHT
ROTATE or DOUBLE LEFT ROTATE, and AC

LOAD are generated.

IAC (increment the AC).

When the
instruction is performed, MB11 =1 and

no other operand exists.,

When the 7500

The content of ACQO0 is sensed

to determine its status,

the left.

(13)

SMA (skip on minus AC).

instruction is performed MBO5 = 1 and no other

the contents of the AC and Link two places to

70014

When the 7440g

operand exists. The contents of the AC register
are checked and if the AC =0, the next se-

(12) RTR and RTL (double rotate, right or left).
When the 7012g instruction (RTR) or the 7006g

tion exists.

SZA (skip on zero AC).

instruction is performed MB06 = 1 and no other

(3)

SNL (skip on non-zero Link).

When the

7420g instruction is performed, MB07 = 1 and
no other operand exists. The Link bit is sensed

The AC is incremented

by 1, by transferring the contents of the AC to

to determine whether it is in the 1 state, and if
it is, the next sequential program instruction is

the major register gating network, adding a
logic 1 through the network adder, and transferring the incremented contents into the AC.

skipped.

The AC ENABLE, AC LOAD, and CARRY INSERT signals are generated to perform this in-

bination of TP3,B FETCH (1), and OPR signals.

The SKIP flip~flop is enabled by
LINK (1), and MBO7 (1), and set by the com-

struction.

(4)

The IAC command can be combined with either

operand exists.

the CLA or CMA commands to perform the
functions of both during one cycle.

SKP (skip unconditonally).

When the 7410g

instruction is performed, MB08 =1, and no other

The next sequential instruction

is skipped regardless of the contents of the AC

When the

and Link.

The SKIP flip~flop is enabled by
MBO8(1), MB11(0), and OP2; it is set by the

CLA/IAC instruction or the CIA (IAC/CMA)
instruction is performed, the operations of both

combination of TP3, B FETCH (1), and OPR.

separate instructions are performed simultaneous-

ly, during T3.

When one of the SZA, SMA, or SNL operands
is combined with MB0O8 (1), reverse sense skipping occurs, i.e., SZA becomes SNA (skip on
non-zero AC, 7450,), SMA becomes SPA (skip

When MBO3 =1, and MB11 =0 the OPR 2 group of

on plus AC, 7510g), and SNL becomes SZL (skip

microinstructions is specified.

on zero Link,7430g).

These microinstructions

may be performed singly or in useful logical combinations.

The available commands include:

CLA, HLT,

(6)

HLT (halt operation).

‘

When the 7402g is

OSR, and seven skip instructions dependent upon the

performed, MB10 =1 and no other operand

status of the AC and/or Link .

exists.

4-39

This operation clears the RUN flip-flop,

the OSR and CLA may be made resulting in the

inhibiting the generation of a MEM START level
which prevents the start of another machine

LAS (load the AC with the contents of the SR).

cycle. The computer stops after T4 time.

(6) OSR (inclusive OR between the SR and AC).
When the 7404g instruction is performed,
MBO9? =1, and no other operand exists. The
result of the inclusive OR remains in the AC.
The OSR operation occurs when the AC ENABLE, AC LOAD, SR ENABLE, and NO SHIFT
signals are generated.

(7) CLA (clear the AC). When the 7600g
instruction is performed MBO9 = 1 and no other
operand exists. The AC is loaded to all Os
(0 -~ AC). This instruction is identical to the
OPR 1 CLA instruction with the exception of
the OP 2 and MB04 levels. The CLA instruction (OPR 2) exists in order to combine with
the OPR 2 microinstructions. As a result the
AC can be cleared after it is sensed by one of
the skip instructions, or combination between

(8) NOP (no operation). When the 7400g
instruction is performed, MBO3 =1, and no
other operand exists. The same events described
for the NOP conditions of the OPR1 instruction
descriptions 1, 5, and 9 occur.

The OPR2 instructions listed above may be logically

combined to perform more than one operation in a

single Fetch cycle. Examples of two of the combined
microinstructions are listed below; however, many

other useful combinations exist.

(1) SZA CLA (7640g) . When this instruction
is performed, the content of the AC is sensed.
If each AC bit is a binary 0, the next instruction is skipped and the AC is cleared.
(2) SNA SZL (7470g) . When this instruction
is performed the next sequential instruction is
skipped if both the AC =0 and the Link =0.

4-40

CHAPTER 5
MAINTENANCE

This chapter contains information pertinent to preven-

5.1

EQUIPMENT

tive maintenance, corrective maintenance, and

troubleshooting techniques for the PDP-8/L.

Table 5-1 lists the equipment and relevant specifications needed for maintenance of the basic PDP-8/L.
Also included is the actual equipment used by Digital
Equipment Corporation field service personnel.

Table 5-1
Maintenance Equipment

Equipment

Specifications

Model or Type

Multimeter

10K ohms/volt-20K ohms/volt

Triplett Model 310

Oscilloscope

dc to 50 mc with calibrated
deflection factors from 5 mV
to 10V/div. Maximum horizontal sweep rate of 0.1 ps/div.
Delaying sweep is desirable and
dual trace is a necessity.

Tektronix Type 453

Probes

X10 with response characteristics

Tektronix Type P6010

matched to oscilloscope

Clip-on
current probe | 2 mA/mV or 10 mA/mV

Tektronix Type P6019
with passive terminator

Recessed

Tektronix

Probe Tip

Unwrapping
tool

Gardner-Denver
505-244-475

Wire-Wrap

Gardner-Denver

tool

A-20557-29

30 gauge bit

Gardner-Denver

for wrap tool

504221

Sleeve for 30

Gardner-Denver

gauge bit

500350

Spray paint

Krylon 1501

Glossy white

Table 5-1
Maintenance Equipment (cont.)
Equipment

Specifications

Mode! or Type

Spray paint

DEC black

Module

DEC No. W982

Extender (2)
Assorted lengths affixed
with 30 gauge termi=-point

Jumper Wires

connectors

5.2

PROGRAMS

Table 5-2 lists the Maintenance Programs supplied
by DEC for ascertaining proper operation of the

Table 5-2
Maintenance Programs*
Program Name

DEC Number

Instruction Test 1

MAINDEC 81-D01B

Use

Tests AND, TAD, and Operate

Instructions only

Instruction Test 2

MAINDEC 81-D02B

Extensive test of Auto Index,

Indirect Address, and the DCA
Instruction

Instruction Test 2B

MAINDEC 08-D02A

Tests 25 add and rotate logic

Random JMP Test

MAINDEC 08-D048

Extensive test of JMP instruction

Random JMP-JMS

MAINDEC 08-D05B

Extensive test of JMS instruction

Random 1SZ Test

MAINDEC 08-D07B

Extensive test of ISZ instruction

Memory

MAINDEC 08-D1J0

Test

Checkerboard
Memory Address

Tests memory circuits susceptibility
to noise

MAINDEC 08-D1B0O

Tests address selection logic

MAINDEC 08-D1AB

Test ability to retain memory
information during loss of power

Test
Memory Power

on/off Test
* Programs are subject to change

5-2

5.3

PREVENTIVE MAINTENANCE

Clean the air filter.

Use a vacuum cleaner to

remove accumulated dirt and dust.
A systematic preventive maintenance program can be
c.

a useful deterrent against system failures. Proper
application of such a program is an aid fo both service-

Lubricate slide mechanisms and casters, with a

light machine oil.

man and user, since detection and prevention of

Wipe off excess oil.

probable failures can reduce maintenance and down-

d. Visually inspect equipme.nf fof general condi-

time to a minimum.

tion.

Repaint any scratched areas with DEC black

paint or Krylon glossy white No. 1501.
Scheduling of computer usage should always include
time set aside for maintenance purposes.

Careful

diagnostic testing can make evident problems which

Inspect all wiring and cables for cuts, breaks,

fraying, wear, deterioration, kinks, strains, and

may only occur intermittently during on-line opera-

mechanical security.

tion.

defective wiring or cable covering.

Tape, solder, or replace any

We suggest weekly program checks scheduled on the
following criteria:

Inspect the following for mechanical security:

key switches, control knobs, lamps, connectors,
transformers, fans, capacitors, etc.

Tighten or

replace as required.

1000-hours - electrical

500-hours - mechanical
g.

or at least every three months.

Inspect all module mounting panels to ensure

that each module is securely seated in its connector.

Remove and clean any module which mayhave

collected excess dirt or dust.

5.3.1

Weekly Checks

Inspect power supply components for leaky

capacitors, overheated resistors, etc.

Time should be scheduled each week to operate the
MAINDEC programs.

Replace

any defective components.,

Run each program listed in

Table 5-2 for at least five minutes.

Take any

i. Check the output voltage of the 718 power
supply as specified in Table 5-3. Use a multi-

corrective action necessary at this time and record
the results in the log book.

External cleanliness of

meter to make these measurements without dis-

the system should also be maintained on a weekly
basis.

connecting the load.

With the exception of Mem-

ory Supply + the outputs of the supply are not
adjustable; therefore, if any output voltage is not

within tolerance, the supply is considered defective and corrective maintenance should be perform-

Many hours of computer downtime can be avoided by

rigid adherence to a schedule based on the condition
of the air filter.

ed.

A dirty filter can cause machine

i«

failure through overheating which has a number of
The frequency of this practice depends
upon system environment and usage . After several
weeks, the frequency of cleansing for the particular
bad effects.

environment will be determined.

Run all MAINDEC programs to verify proper

equipment operation.

Each program should be

allowed to run for at least five minutes.
k.

The procedure for

Perform all preventive maintenance operations

for each peripheral device included in the system.

filter cleansing is described under Preventive Maintenance Tasks.

Enter preventive maintenance results in the log

book
.

5.3.2

Preventive Maintenance Tasks
5.4

The following tasks should be performed on at least

CORRECTIVE MAINTENANCE ,

a three-month's schedule:

The PDP-8/L is constructed of reliable TTL M-series
a.

modules.

Clean the exterior and interior of the equip-

Use of these circuits with faithful perform-

ment cabinet, using a vacuum cleaner and/or

ance of the preventive maintenance tasks ensure re-

clean cloths moistened in nonflammable solvent.,

latively little equipment downtime due to failure.

5-3

5.4.1

Should a malfunction occur, maintenance personnel
should analyze the condition and correct it as indi-

cated in the following procedures.

Neither special

test equipment nor special tools are required for corrective maintenance other than a broad-bandwidth
oscilloscope, a Tektronix Type P5019 current probe,
and a multimeter. The best corrective maintenance
tool is a thorough understanding of the physical and
electrical characteristics of the equipment. Persons
responsible for maintenance should be thoroughly
familiar with the system concept, the logic drawings,
the operation of specific module circuits, and location of mechanical and electrical components.
It is virtually impossible to outline any specific procedures for locating faults within complex digital sys-

tems, such as the PDP-8/L. However, diagnosis and
remedial action for a fault condition can be undertaken logically, and systematically in the following
phases:

(Q:‘h(DQ_GO'Q

.
.

Preliminary Investigation

Before commencing troubleshooting procedures,
explore every possible source of information. Think
over the problem, Gather all available information
from those users who have encountered the same
problem and check the system log book for any previous references to the problem.
Do not attempt to troubleshoot by use of complex

system programs alone. Run the MAINDEC programs
and select the shortest, simplest program available
which exhibits the error conditions. MAINDEC
programs are carefully written to include program
loops for assistance in system and logic troubleshooting.

5.4.2

System Troubleshooting

Once the problem is understood and the proper program is selected, the logical section of the system
at fault should be determined. Obviously, the
program which has been selected gives a reasonable
idea of what section of the system is failing. However, faults in equipment which transmits or receives
information, or improper connection of the system,

Preliminary Investigation
System Troubleshooting
Logic Troubleshooting
Circuit Troubleshooting
Repairs and Replacement
Validation Test
Recording

Table 5-3

Power Supply Specifications

Voltage

Current

Use

Pins (G785)

(AB28)

+7V (rms) £ 20%

1.75A | Panel Lights

AN2, AP2,AR2,AS2

5V, 3%

Logic

=15V (-14v
to -19V)

1.5A

Keys and Switches, | AB2
Sense Amplifier
Main Supply

-15V (Zener
Regulated)

N/A

Sense Amp Slice
Reader Clock

AV2
BB2

-30V (-28V
to -38V)

1.75A

Memory Supply -,
Teletype

BS2,BT2,BU2,BV2

-6V (varies)

1.7A

Memory Supply +

BM2,BN2,BP2,BR2

AA2,AF2,AH2,AJ2,AK2

AL2,AM2,BA2

CAUTION

frequently give indications similar to those caused
by computer malfunctions.

Do not use the lowest or highest resistance
ranges of the multimeter when checking
semiconductor devices. The X10 range is
suggested. Failure to heed this warning

~ Disconnect any peripheral devices which are not
necessary to operate the failing program,

may result in damage to components.

Now, reduce the program to its simplest scope loop
and duplicate this loop in a dissimilar portion of
memory to verify, for instance, that an operation
failure is not dependent upon memory location. This
process can aid in distinguishing memory failures
from processor failures. Use of the technique described above often pinpoints the problem to a few
modules.
5.4.3

Measure the forward and réeverse resistances of

diodes. Diodes should measure approximately 20Q
forward and more than 1000Q reverse. If readings
in each direction are the same and no parallel paths
exist, replace the diode,
Measure the emitter-collector, collector-base, and
emitter-base resistances of transistors in both directions. Short circuits between collector and emitter or
an open circuit in the base-emitter path cause most

Logic Troubleshooting

failures.

Before attempting to troubleshoot the logic, make
sure that proper and calibrated test equipment is
available. Always calibrate the vertical preamp
and probes of an oscilloscope before using. Make
sure the oscilloscope has a good ac ground and keep

A good transistor indicates an open circuit

in both directions between collector and emitter.
Normally 50 to 100Q) exist between the emitter and
the base, or between the collector and the base in
the forward direction, and an open circuit condition
exists in the reverse direction. To determine forward
and reverse directions, consider a transistor as two

the dc ground of the probe as short as possible.

diodes connected back to back. In this analogy,
PNP transistors would have both cathodes connected
together to form the base, and both the emitter and

Use the oscilloscope to trace signal flow through the
suspected logic element. Oscilloscope sweep can be
synchronized by control pulses or by level transitions
whichare available on individual module terminals
at the wiring side of the logic. Care should be
exercised when probing the logic, to prevent shorting
between pins. Shorting of signal pins to power
supply pins can result in damaged components. With-

collector would assume the function of an anode.
In NPN transistors the base would be a commonanode connection; and both the emitter and collector,
the cathode.

Multimeter polarity must be checked before measuring

in modules, unused gate inputs are held at +t3 V.
This voltage is introduced from pin Ul or V1 of
modules M113, M117, or M617. The number in
parentheses beside each +3V input represents the
wiring run number for that +3V line. Each line can
handle a maximum of 15 loads.

resistance, since many meters apply a positive volt age to the common lead when in the resistance mode.
Since IC's contain complex circuits with only the
input, output, and power terminals available, static
multimeter testing is limited to continuity checks for
shorts between terminals. 1C checking is best done
under dynamic conditions using a module extender

to make terminals readily accessible. Using PDP-8/L

engineering drawings and M-series module schematics,
you may locate an IC on a circuit board as follows.

5.4.4 Circuit Troubleshooting

a. Hold the module with the handle in your left

Engineering schematic diagrams of each module are
supplied with each PDP-8/L system and should be

hand; component side facing you.

referred to for detailed circuit information. Copies
of engineering schematic diagrams are contained in

b. IC's are numbered starting at the contact end
of the board; upper right hand corner.

Volume II.,

c¢. The numbers increase toward the handle.

Visually inspect the module on both the component
side and the printed-wiring side to check for overheated or broken components or etch. If this inspection fails to reveal the cause of trouble or to
confirm a fault condition observed, use the multi-

d. When a row is complete, the next IC is

located in the next row at the contact end of the
board. (See Figure 5-1).
e. The pins on each IC are located as Figure 5-2
illustrates .,

meter to measure resistances.

5-5

—

| SSE—

electrical current, take the following special precautions:

Use a heat sink, such as a pair of pliers, to

grip the lead between the joint and device being
soldered.

Use a 6V iron with an isolation transformer.

Use the smallest iron adequate for the work.

Use

of an iron without an isolation transformer may
result in excessive voltages presented at the iron

tip.

L |

possible time to prevent damage to the component

Perform the soldering operation in the shortest

and delamination of the module etched wiring.

d. IC's may be easily removed by using a solder
(@]

puller to remove all excessive solder from contacts.

——

Then, by straightening the leads, lift the IC from

its terminal points.

If it is not desirable to save

the defective IC for test purposes; then the terminals may be cut at the IC body and each terminal
removed from the board individually.

—

CAUTION
Never attempt to remove solder from termin-

Figure 5-1

IC Location

al points by heating and rapping module
against another surface.

This practice can
result in module or component damage .

Always remove solder by the use of asolder-~
sucking tool .

When removing any part of the equipment for repair
and replacement, make sure that all leads or wires
14

[101]

which are unsoldered, or otherwise disconnected,
are legibly tagged or marked for identification with
their respective termindls.

Replace defective com-

ponent only with parts of equal or better quality, and
equal tolerance.

O
guuduggd
{

In all soldering and unsoldering operations in the
repair and replacement of parts, avoid placing ex-

cessive solder or flux on adjacent parts or service

Figure 5-2

IC Pin Location

lines.

When repair has been completed, remove all

excess flux by washing junctions with a solvent such
as trichlorethylene,

Be very careful not to expose

painted or plastic surfaces to this solvent,
5.4.5

Repairs And Replacement
5.4.6

Validation Tests

When soldering semiconductor devices (transistor,
diodes, rectifiers or integrated circuits) which may

be damaged by heat, physical shock, or excessive

Always return repaired modules to the location from

which they were taken.

If a defective module is

replaced by a new one, while repairs are being made,

hold voltage.

tag the defective module noting the location it was

set when the voltage at test point A27U2 changes

taken from and the nature of the failure.

When re-

The threshold reference is properly

from a low voltage (-6V) to a higher voltage (-2V)

pairs are completed, return the repaired module to

as the +5V supply voltage passes through 4.75V after

its original location and ascertain that the repairs

turn-on.

have resolved the problem,

G826 variable resistor R2, 1000Q Minnelco, and

To confirm that repairs have been completed, run all

performs several functions. When the +5V supply
voltage is less than this threshold, the regulated

tests which originally exhibited the problem,

The threshold voltage is adjusted by the

memory supply voltage is held off.

modules have been moved during the troubleshooting

A comparison

amplifier on the G785 module, continually monitors

period, return all modules to their original postions

the raw power supply input to the +5 regulator and

before running the validation tests.

anticipates any voltage decrease.

When a change

occurs, the LINE LOW level is asserted.
Anytime that a module is replaced by one from spares

LINE LOW

controls various logic signals to the central processor

to correct a problem, always return the module to its

by initiating POWER OK and a power failure action

original location to confirm its defectiveness before

SHUT DOWN; a STOP OK level from the processor

initiating repair procedures.

allows a shut down of the memory supply voltage

when the +5V supply voltage fails.

As the threshold

is reached during turn-on, POWER CLEAR produces
5.4.7

a pulse to ground and then returns to a high level.
Also, with these conditions, POWER OK is a low
logic level, and SHUT DOWN is a high logic level.

Recording

A log book is supplied with each PDP-8/L system.
Corrective maintenance is not complete until all

The inverse of these levels should exist before the

data indicating the symptoms given by the fault, the

threshold is reached. The STOP OK level originates
from the central processor and its undriven input

method of fault detection, the component at fault,

should remain high having no effect during alignment.

activities are recorded in the log book.

Record all

and any comments which would be helpful in maintaining the equipment in the future. The log should
be maintained on a daily basis, recording all operator

5.5.2

Memory Alignment Procedure

usage and preventive maintenance results.

To adjust or check the memory currents, the PDP-8/L
should be allowed to warm up for approximately 1 hr
5.5

ADJUSTMENTS

before measurements are made.

In addition, the

measurements should be performed at an ambient

Note:

The measurements and adjustments in the

temperature of 25°C,

following paragraphs are analog in nature, and are
not of the on-off, high-low nature.

These areas re-

The G826 negative regulator control module at loca-

present tuned sections of the computer that must be

tion AB27 and the negative regulator portion of the

properly aligned by qualified personnel.

718 power supply control the memory voltage regulation, and therefore control the memory currents.

Adjustments of the PDP-8/L should never be undertaken until it has been confirmed that a failure is

due to circuit aging or misalignment rather than a
component failure.

The voltage difference between MEMORY SUPPLY+
and MEMORY SUPPLY - provides the read/write,

Replacement of certain com-

ponents or excessive environmental handling may

and inhibit currents through the memory stack.

preclude any other corrective action.
The negative regulator control (G826) serves to vary
the 718 regulator for temperature variations by a

5.5.1

thermistor and difference amplifier tracking circuit

Power=Up Threshold Adjustment

which compares the regulated memory voltage to an

This adjustment is preset at the factory and should

adjustable reference.

only be attempted in the field by skilled personnel.

located on the G826 module varies this reference volt-

A Trimpot (R28, 2000Q

Bourns)

age, and therefore, varies the memory currents.,

The G826 Negative Regulator Control module contains a difference amplifier that compares the +5V
supply voltage with an adjustable reference thres-

Adjustment of the trimpot varies the MEMORY

SUPPLY+ voltage between approximately -1V and

5-7

ence in current should not be confused with amplitude

-12V; the subsequent variation of the regulated

variations within the read/write current due to bad

memory supply voltage should be between -18V and
-29V. Normally, the regulated memory voltage
should be set to approximately =22 .5V, measured
with a multimeter across memory supply+ and memory

address decoding selection switches; these differences
are also apparent at the memory stack inputs and vary
with different addresses. The current loops, provided
for use with a Tektronix Type P6019 current probe,
are as follows:

supply-.

If the voltage can be adjusted but not to the above
value, the thermistor across the regulator control
(pins B27R2 and B2752) should be investigated. The
thermistor is located within the memory stack and
outputs on the inhibit connector card (pins B2252
and B22T2); its resistance should be 330Q+10% at
25°C. Shunting resistance in the regulator control

X Source
Y Source
X Return
Y Return

C23T2 to C25K1
C18T2 to C2551
D19T2 to D25K]
D23T2 to D2551

Examination of the current at these loops has the
advantage that the currents for all memory addresses
pass through these common points. The waveshape
should be inspected on each of the four loops tocheck
that no leakage to ground exists between the voltages,

would reduce this value if a measurement is made
with the modules connected.

If no voltage adjustment is possible, either the
Negative Regulator (G785) portion of the 718 power
supply or the Regulator Control (G826) can be at

MEMORY SUPPLY+and MEMORY SUPPLY-.

The regulated memory voltage was previously adjusted
in a static condition for =22 .5V; there shouldbe no
change although the memory is now cycling. The resultant stack current should be approximately 320 mA
(this value varies with stack vendors, and is best
determined by adequate core output with minimum

fault.

In alignment of the memory, the actual outputs of
the various memory control flip-flops should be
checked against those of Figure 5-3. An approximate initial STROBE adjustment can be such that its
leading edge occurs 500 ns after the leading edge of
MEM START. The width of the strobe signal should
be less than or equal to 80 ns and have an approximate adjustment range for its leading edge from
MEM START from 350 ns to 650 ns. A clockwise
rotation of the adjustment on the variable delay line
(M360 at C17) increases this delay. The final adjustment of strobe must be made in relation to the

noise). The lower read/write current amplitudes on

the current amplitudes on the current loops equal the
current amplitudes in the stack windings; the current
measurements can conveniently be made there. Correlation between the voltage and current should exist.
Variations in current amplitude at successive address-

es should be less than 20 mA.

Failure of the R/W

selection switches is indicated by the lack of proper

read/write currents of any address. If all the R/W

analog data signal from core memory.

selection switches appear to have failed, inspection

should be made at the input logic signals, READ (1)
and WRITE (1), and the input supply voltages. To

The R/W selector switches are examined by inspecting the current wave forms on the current loops at

analyze the read/write currents for individual address-

the source and return signals. The current waveturns are similar to those of Figure 5-4 which repre-

es, the following program may be used:

sent the equal amplitude read/write currents measur-

0000

ed on the memory stack input. When running a
multiple-selection program such as MEMORY
CHECKERBOARD, the wave forms differ in the
amplitudes of the read/write currents due to the
contribution of the base currents to the emitter
currents of the address decoding and selectionswitch-

0001

0002
0003
0004

Beg, LAS
DCA Temp

TAD I Temp
JMP Beg
Temp, O

7604
3004

1404
5000
0000

The read/write currents for individual addresses may

es.

be examined by setting the desired address into the

switch register.

Of course, since the currents for

all memory addresses pass through the common test

The additional current (approximately 30 mA) appears

on the return current through the R/W selection

point, you will also be examining the currents for

switches to MEM SUPPLY-. Depending upon the
loop examined, it is sometimes additional read current

those locations which the test program occupies. You

and sometimes additional write current.

those addresses within the program; if not, relocate

must first ascertain that the currents are proper for

This differ-

5-8

Q-sf sg
134)0D

_! |_

5-9

[

sio|

[SA¢aW0.l4I.-0oJunS0AwGDbAs)iy

the program to some other area of memory.

By select-

does not correct the problem; then , the logic signal

ing individual addresses via the switch register, wave-

inputs from the memory address (MA) register should be

form deformities may be traced to defective associated

inspected.

R/W switches.

cording to the selected address, attention should be

If those signals are correct and vary ac-

turned to the memory stack with its attendant diode

If the improper waveform remains fixed to a specific

selection matrices.

address and replacement of the associated R/W switch

—

MEM START _/

0.0lps
|

0.38 s

0.76 ps

TR
A

SRR

320 ma

READ

1.5048

L <20ma
WRITE

0.28
us
NORMAL READ/WRITE
CURRENT WAVEFORM

320 ma

)

S—

OPEN

DIODE, BAD R/W

SWITCH

(BOTH WAVEFORMS MAY

ALSO BE

SHORTED DIODE

ABNORMAL READ/WRITE
CURRENT WAVEFORMS

Figure 5-4

Representative Read/Write Current
Waveforms

5-10

NEGATIVE)

The diode selection matrices (G611 and G610) sand-

Twelve 6020 sense amplifiers are associated with each

wich the memory planes of ferrite cores betweenthem.

memory stack; each amplifier transforms the analog

Also connected to this unit are two W025 cable con-

pulse output of ferrite core to a usable logic level,

nectors, one for the inhibit inputs, the other for the

The sense windings for each bit enter a differential

sense outputs.

amplifier with a threshold voltage established as a

The X-axis Diode Selection Matrix (Drawing D-BS8L-0-15) has half its diodes on the G610 board and
half on the G611 board; the same is true of the Yaxis Diode Selection Matrix (Drawing D-BS-8L-0-16).

The inductor symbol connecting the centers of the

function of the fixed SLICE voltage.

The test points

(pins E1 and K2) after the amplifiers allow observation of the waveforms for comparison with those of

Figure 5-6. The preliminary setting of STROBE

should now be modified as a function of the data output from core memory.

two sets of diodes represents the stack winding traver-

sing the 12 core planes.

The windings are identified

on the diode matrix selection boards as X, 0-64 and
X, 0-64 for the X~axis windings and Y, 0-64 and Y,

0-64 for the Y-axis windings.

Suspected opens and

shorts in the windings, detected during dynamic tests,

should be verified by measurements across these

points with an ohmeter.

The resistance of the read/

write winding is 3.5Q *10%.

The forward andreverse

resistance of the diodes in the matrix should also be

The leading edge of STROBE is set approximately at
the center or just past the midpoint of the amplifier

"one" output. This adjustment should be late enough
to sense all "one" data with normal variations in de~
lay, and yet centered in the "zero" data output.
Each sense amplifier test point should be examined
and the final adjustment of the strobe signal should
be made using the most sensitive sense amplifier as
a criteria,

checked when address selection failures are attributed to stack failures.

The lack of proper waveforms at all addresses indicates that the sense amplifier or the core winding
is in error,

The sense amplifier may be checked by

exchanging a known good amplifier with the suspected one. The absence of an input signal indicates

CAUTION

The memory stack is expensive and

the stack sense winding should be checked or the

fragile; it is easily damaged and must

sense connector W025 at AB21)for a resistance of

be handled with care.

21Q £10%.

Testing and adjustment of the memory section of the

Twelve inhibit drivers are associated with each mem-

PDP-8/L is now completed by running the memory

ory stack.

address test and memory checkerboard test (worst

To inspect the inhibit currents you will

need two module extender boards (W982) at AB22,

pattern).

These extender boards provide current loops for each

may be necessary to increase or decrease the ampli-

of the 12 inhibit lines. Inhibit current should be

Final adjustment of the read/write currents

tude of the core input and corresponding noise .

inspected and compared with the waveform in Figure

5-5. Inhibit current amplitude is approximately
290 mA as noted; more important, however, is the

ratio of read/write and inhibit currents. This ratio is
0.85 of the read/write current and should exist regardless of the read/write current amplitude. Failure of

5.6

a specific inhibit driver can be determined by move-

This section contains information pertinent to the
maintenance of the ASR33 and its associated control
logic.

ment of the suspected driver to another location,

Movement of the failure indicated that the module
should be repaired or replaced.

ASR33 TELEPRINTER AND CONTROL
MAINTENANCE

No movement of

the failure indicates that either the input signals or

output load is causing the failure.

The logic inputs,

B INHIBIT and B MEM ENABLE, from the memory

5.6.1

Equipment

control; the connection through the current limiting

resistor; and the memory buffer signals should be

Table 5-4 lists the special tools needed for mainten-

checked.

ance of the ASR33 Teleprinter.

If the stack is suspected, the specific

All of these items

winding should be measured for a resistance of 14Q

can be obtained from Digital Equipment Corporation

£10%.

or from the Teletype Corporation.

5.6.2

Programs

CAUTION

Table 5-5 lists the maintenance programs supplied by
DEC for aid in maintaining the ASR33 and associated

Do not use alcohol, mineral spirits, or

other solvents to clean plastic parts

control logic.

5.6.3

with protective decorative finishes.
Normally, a soft, dry cloth should be
used to remove dust, oil, grease, or
otherwise clean parts or subassemblies.

Preventive Maintenance

Teletype preventive maintenance is scheduled on the

To clean plastic surfaces, we recommend using any

same frequency as discussed in Paragraph 5.4,

MEM START J

0O0us
|

of several household cleaner-waxer liquids such as

{.5us

290ma

NORMAL INHIBIT
CURRENT WAVEFORM
t.0us

BAD

ABNORMAL INHIBIT

CURRENT WAVEFORM

A
BAD TRANSFORMER, OPEN DIODE

OPEN

Figure 5-5

DIODE

WINDING

Representative Inhibit Current Waveforms

5-12

Table 5-4
Teletype Maintenance Tools

Item

Part No.

Item

Part No.

8 oz. scale.

110443

Bending Tool

180993

32 oz, scale

110444

Extractor

182697

64 oz. scale

82711

Tweezer

151392

Set of gauges

117781

Spring hook (push)

142555

Offset screwdriver

94644

Spring hook (pull)

142554

Offset screwdriver

94645

Screw holder

151384

Handwheel

161430

Handwheel adaptor

181465

Contact adjustment tool

172060

Gauge

180587

Gauge

180588

Gauge

183103

Table 5-5

Teleprinter Maintenance Programs
Program Name

DEC No.

Reader Test

MAINDEC-81-D2PB

Use

Function test and exerciser

for ASR33/35 teletype paper
tape reader

Punch Test

MAINDEC-81-D2QB

Function test and exerciser

for ASR33/35 teletype paper
tape punch

Keyboard Test

MAINDEC-81-D2RB

Function test and exerciser

for ASR33/35 teletype keyboard

Combination Test

MAINDEC-81-D2TB

Exerciser program used to

test ASR33/35 printer and
punch simultaneously

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"Jubilee" or "Jato." To clean the printer platen,

we recommend using a lacquer thinner.

During overhaul, subassemblies and metal parts can
be cleaned in a bath of trichlorethylene. Proper
lubrication should be performed often.

Brush Holder (Distributor)
Clutches
Code Bar Reset
Print Suppression
" Blocking Levers
Print Suppression

Carriage Drive Bail
Print Trip Lever

Wipe

b. Clean external areas of paper tape punch
and reader, using a soft brush or cloth.

Remove and empty paper tape punch chad

box.

Run teleprinter combination test (MAINDECd.
81-D2TB) for approximately 15 min.

Preventive Maintenance Tasks

a. Inspect platen and paper guides. Clean
platen, using a lacquer thinner to remove shiny
surfaces.

Clean ribbon guides and replace ribbon, if

necessary.

Remove cover and check for vibration effects;
c.
loose nuts, screws, retaining clips, etc.

d. Remove distributor rotor and clean disk
surface, using cotton swab moistened in "Freon"
or "Trichlorethylene."

Check selector magnet coil for signs of over-

heating.

Clean between selector magnet pole piece

" and armature with bond paper to remove any
lubricant or dirt.

g. Clean and lubricate Teletype as instructed
in Teletype Bulletin 273B. Follow instructions
literally so as not to over lubricate.

h. The following adjustments should be checked.
Pages indicated are in Bulletin 273B, Volume II.
Trip Shaft
Trip Lever

574-122-700 Page 13
574-122-700 Page 14

Line Feed

Keyboard Trip Lever
Reader Trip Lever
Detent Lever

Sensing Pin

Tape Lid Latch Handle

Feed Pawl
Registration

574-122-700 Pages 16-24
574-122-700 Pages 30-34
574-122-700 Page 35
574-122-700 Page 37
574-122-700 Page 43
574-122-700 Page 44
574-122-700 Pages 61-62
574-122-700 Page 78
574-122-700 Page 85
574-122-700 Pages 89-95
574-122-700 Page 141
574-124-700 Pages 6-9
574-124-700 Page 10
574-124-700 Page 15
574-124-700 Page 18

574-125-700 Page 11
574-125-700 Page 12

Run each of the Teletype MAINDEC Programs
i.
for at least two passes each.

Check that tape holes are being punched

cleanly.

5.6.4

Corrective Maintenance

Figure 5-7 is a simplified drawing of the control
circuits for the ASR33 Teleprinter. Details of the
cable connector are included to show how a tele-

printer is modified to operate with the PDP-8/L.

During off-line operation, the keyboard distributor
effectively drives the printer selector magnetf. This
means that any character received from the keyboard
or paper tape reader is automatically reproduced on
the printer and paper tape punch. During on-line
operation, this continuity is broken and a teletype
receiver (M706) is used to accept the input from the

reader or keyboard while a teletype transmitter (M707)
is used to drive the printer and paper tape punch.
The clock (M452) develops a TTI clock (880 Hz) and

a TTO clock (220 Hz).

These clocks are used to shift the bits through the
transmitter and receiver buffers. Adjustment is made
by viewing the TTO clock output with the oscilloscope
probe on C33K2 and adjusting the trimpot for a 4.5 to
4.6 ms repetition rate. Most teletype problems can
be traced to one of four areas as follows.
T Q

a. Inspect platen and paper guides.
clean, using a soft, dry cloth.

Dashpot
Final Printing Alignment

o n

Weekly Tasks

574-122-700 Page 15

ASR33 keyboard or reader
ASR33 printer or punch
M706 receiver
M707 transmitter

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