Digital PDFs

DEC-8L-D4BA-D

April 1969

15 pages

Original

2.0MB

view download

OCR Version

2.1MB

view download

Document:	MC8-L FuncDescr Jun70
Order Number:	DEC-8L-D4BA-D
Revision:	0
Pages:	15
Original Filename:	DEC-8L-D4BA-D_MC8L_Memory_Extension_Control_Option_Functional_Description_Apr69.pdf

OCR Text

DEC-8L-D4BA-D

MCS8/L
MEMORY EXTENSION CONTROL

OPTION FUNCTIONAL DESCRIPTION

DIGITAL

EQUIPMENT

CORPORATION

MAYNARD,

MASSACHUSETTS

Ist Printing April 1969

The following are registered trademarks of Digital
Equipment Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

MC8/L

MEMORY EXTENSION CONTROL

INST FIELD key raised, or by the program.
through the Instruction Buffer (IB) register.

All

program executed transfers of the IF come from

the IB.
INTRODUCTION

The content of the INST FIELD key is

loaded directly into the IF and the IB by manual operation of the LOAD ADDR key.

An additional 4096 (4K) core memory can be

added to the standard PDP-8/L 4K core memory to yield the maximum storage capacity of
8192 words. Figure 1 shows the MC8/L modules and their locations in the BAO8 Peripheral
Expander and Figure 2 illustrates the Memory
Extension Control organization, and it's relationship to the standard memory. The Memory
Extension Control is placed in the BAO8 Peripheral Expander Cabinet as shown in Figure 2.

Transfer of MC8/L control and data signals
occurs mainly through the special signal cables

and connectors. The PDP-8/L 1/O BUS is connected to the BAO8. Some of the I/O BUS signals are used by the MC8/L option; however,
other options make use of this bus so it must be

supplied.

When a -

JMP or JMS instruction is executed, the con-

tent of the IB is transferred into the IF.

When an interrupt occurs, the content of the
IF is transferred to the Save Field (SF) regisAt the end of the interrupt subroutine the

ter.

IF status is restored through the IB from the SF
by execution of the RMF instruction.
When the CIF instruction is executed (refer to
Memory Extension Control Instruction Descrip-

tions in this section) the content of MBOS8 is
transferred to the IB; the content of the IB is
transferred to the IF at the execution of a JMP

or JMS instruction. During the time between
the CIF instruction and the JMP or JMS, pro-

gram interrupts are inhibited.

The following paragraphs describe the use of

the MC8/L control logic, and the Memory
Extension Control instruction set. It is assumed
that the reader understands the memory timing,
read, write, inhibit and sense elements of the

basic memory system described in Volume I,

Chapter 4, of the PDP-8/L Maintenance Manual.

The memory system elements described

Data Field Register (DF)

This 1-bit register determines the field used for
data storage and retrieval.

The DF can be

loaded from three discrete sources:

MBO8, the

Save Field (SF1), and the DATA FIELD key.

above are identical to those in the expanded 4K

core memory; therefore, maintenance and operation are the same.

Initially, the DF is loaded from the DATA
FIELD key by manual operation of the LOAD
ADDR key.

LOGIC DESCRIPTION

Instruction Field Register (IF)

This 1=bit register determines the memory field
to be used for storage and retrieval of program
instructions. The IF register can be loaded
directly by pressing LOAD ADDR with the

While the program is running, a

CDF (change data field) instruction can be used
to alter the content of the DF to permit selection of the other memory field.

Bit 08 of the

CDF instruction contains the desired field address (either O or 1). Once loaded, the content of the DF remains unchanged until altered;
either manually by LOAD ADDR and the asserted DATA FIELD key, or under program control

by a CDF instruction.

Figure 1

Memory Extension Control in the BAO8 Peripheral Expander

PDP-8/L

MC8/L AND

l€«—— FROM EXTENDED MEMORY

e——]

CENTRAL

PROCESSOR

MEM 0011

TIMING

X :;‘lg Y

—®

INHIBIT

DRIVERS [ TM

CORE
MEMORY

|| MPLIFER
fr o
SENSE

‘

:
S

|o] ADDRESS
AXIS

AND

SPECIAL SIGNALS &

—4

? MC8/L
<

SELECTORS

STANDARD

INHIBIT

MEMORY

SIGNALS
AND FROM —> DRIVERS TM
TO

I/0 BUS CABLES

MEMORY

BMA

o
o
2
t

SIGNALS (

TIMING GENERATOR

TO_AND_FROM
PROCESSOR ¢

EXTENDED MEMORY

SENSE

RIB,C|F,CDF,AND
ROF LOGIC

2
=

GENERATORL
o Appress —TM

EXPANDER

SF, DF, EA,INT,
INH

ME MORY

PERIPHERAL

c%"fi%«?fié‘fi%

BUS

» TO EXTENDED MEMORY

STANDARD

BA®8

4K
e

SENSE
o
AND
Xk
SLICE
O
AMPAL'!‘I-;)IERS——u glfl

SENSE

REGISTERS

&Jg

)

BMB
8L -000t¢

Figure 2

Block Diagram, MC8/L Memory
Extension Control

During a program-interrupt operation, the content of the DF is automatically stored in the
Save Field register (SF1) and is restored to the
DF upon completion of the interrupt subroutine

by the RMF instruction.

Instruction Buffer Register (IB)

This 1-bit register provides input buffering for

data transfers made into IF under program con-

trol. Manual transfers are made directly into
IF and, simultaneously, into IB. This transfer
of data into both registers is necessary to pre-

vent inadvertent changing of the content of IF.
The output of IB is loaded into IF at the execution time of every JMP or JMS instruction
strobes the output of IB into IF.

Extended Address (EA) Field Selection

The EA flip~flop (drawing D-BS-MC8-L-2)
allows access to either memory field. The flipflop outputs, EA (for field O, the standard core
memory) and EA (for the extended memory)
enable each memory timing generator when at
a high logic level.

The EA extended address field enable flip=flop
can be activated from one of three sources: the
the IF register, the DF register, or the BF register. The IF register is gated to the EA flipflop except during a break cycle or an indirectly
referenced data handling instruction (AND,
TAD, ISZ and DCA). In addition, when the
LOAD ADDR and the INST FIELD keys are
operated, the IF is gated to EA to generate the
memory field enable level. The DF register is
gated to EA when any indirectly~addressed

memory reference instruction other than JMP or

Save Field Register (SF)

JMS is executed (AND, TAD, ISZ or DCA).
The BF decoder allows the BF to gerierate the
memory field select code during a break cycle.

This 2-bit register provides temporary storage
for the content of both IF and DF during a pro-

Interrupt Inhibit

gram interrupt. This is necessary to permit IF
and DF to be cleared so the program interrupt

subroutine can start in field 0. At the conclu-

sion of the interrupt subroutine, an RMF in-

struction loads the content of SFO into IB for
subsequent transfer into IF, and the content of

SF1 into DF. The last instruction in the sub-

routine (JMP10) completes the transfer from IB,
to IF.

The interrupt inhibit (drawing D-BS~MC8L-2)
logic disables the INT OK (drawing D-BSPDP-8-1L-7) level in the processor from the time
a CIF instruction is decoded until a JMP or

JMS command finishes the CIF instruction.
This prevents operation of an interrupt before
the field is changed. Interrupt synchronization is restored after the IF is loaded from the
IB, allowing further program interrupt to occur.

Break Field Register (BF)
MEMORY EXTENSION CONTROL INSTRUCTION DESCRIPTIONS

This 1-bit register determines the field to be
used for storage and retrieval of data transfers
from 1/O devices using the data break facility.
The BF is loaded from the EXT DATA ADD line
by BTP2 of the cycle before a data break is
initiated.

The following paragraphs describe the basic
microinstruction set necessary to control pro=gram execution with the Memory Extension Control option. See Table 1 Basic IOT Micro-

instruction Set for the MC8/L.

Table 1

Basic IOT Microinstruction Set for the MC8/L
Mnemonic

Octal

Operation

62N1

Change to Data Field N. The data field register is
loaded with the selected field number (0 or 1). All
subsequent memory requests for operands are automatically switched to that data field until the data

Program Interrupt

CDF

field number is changed by a new CDF command, or
during a program interrupt.

CIF

62N2

Change Instruction Field. The instruction buffer
register is loaded with the selected field number
(O or 1). The next JMP or JMS instruction causes
the new field to be entered.

RDF

6214

MB8 = >DF

MB8 =>1B.

Read Data Field. The content of the data field
register is transferred into bit 8 of the AC. Bits 6
and 7 are cleared, all other bits of the AC are not
affected.

RIF

6224

DF = > AC8

Same as RDF, except reads the instruction field.
IF = >AC8

RIB

6234

Read Interrupt Buffer. The instruction field and data
field, stored in the same field during an interrupt,
are read into AC 8 and 11 respectively.

SFO =>

AC8 SF1 = > ACT1
RMF

6244

Restore Memory Field, Used to exit from a program
interrupt.

Change Data Field (CDF)

Change Instruction Field (CIF)

This instruction (octal code 62N 1, where N is
the octal number of the field to which control
is changing, N is Og for field 0, and 1g for
field 1) is used prior to storing or retrieving

This instruction (octal code 62N2, where N is
the octal number of the field to which the program is changing) is executed prior to JMP or

data with any indirectly-addressed memoryreference instruction other than JMP or JMS.
This instruction is generated by combining
BIOP1 and MBO3 through MBO7 levels (drawing
D-BS-MC8-1~2).

MBO8 (N = MB06 a 0, MBO7 a 0 and MB08

JMS instruction.

The 62N2 instruction allows

either a O for field 0 or 1 for field 1) to be
loaded into the IB by combining it with BMBO9
(0) to enable the IB

flip~flop data input and

clocking the clock input with LOAD IB.

The

content of IB is then transferred to the IF when

Read Data Field (RDF)

Restore Memory Field (RMF)

This instruction (octal code 6214) reads the
contents of the DF flip-flop onto the ACIO8
line. The data is transferred to accumulator
bit ACO08 in the same manner as with the RIB

the next JMP or JMS command is executed
(LOAD IF active).

instruction.

This instruction (octal code 6244) restores the
contents of the SF to the DF and IB registers.

The conclusion of an interrupt subroutine (JMP

Read Instruction Field (RIF)

D-BS-MC8-L-2) allows bit SF1 to be loaded into the DF. The content of the IB is transferred

This instruction (octal code 6224) reads the contents of the IF flip-flop onto the ACIO8 line.
The data is transferred through the INPUT BUS
08 line to bit AC08 in the same manner as the

10) loads the IF from the IB. RMF (drawing

to the IF by executing a JMP or JMS instruction.

RDF.

Read Interrupt Buffer (RIB)

This instruction (octal code 6234) allows storing
that same field in memory if the power failure
option is installed. This instruction reads the
contents of the 2-bit SF register into the AC on
the ACIO8 and ACI11 lines (drawing D-BS-

MC8-L-2). These lines activate the INPUT
BUS 08 and 11 lines in the processor.

ENGINEERING DRAWINGS

The following drawings pertaining to the
MC8/L option are contained in this section.

D-BS-MC8-L-1

D-BS-MC8~L-2
Execution of the RIB instruction generates AC
LOAD and AC ENABLE in the processor which
AC LOAD (draw-

ing D-BS-PDP8-L-6) is generated by I/O ENABLE and I/O STROBE as a result of performing
this IOT (6234) command. I/O ENABLE also
produces AC ENABLE (drawing D=-BS-PDP8-L-

Memory Control

Memory Extension Control

D-BS-MC8-L-3

Sense Amp and Inhibit

D-CS-MC8-L-4
D-CS-MC8-~L-5
D-1C-MC8-L-6

X-Axis Selection
Y-Axis Selection
Special Signal Con-

allows transfer of the data on INPUT BUS 08

and 11 to the accumulator.

Title

Drawing Number

Drivers

nectors

D-UA-BCO8A-0-0

BCO8A Cable

B MEM ENABLE

M617

N'viizs-

| 813

BIl

MEM ENABLE (1)

HI,J1KI

[

AB3Q

NTL_ZE
s

Y A

l.(IIfll_z 1

—|

WRITE

T write (1)

INHIBIT

ae0

BEGIN

1
T

Locx

[

F2yH2

—————————————————— -—

—d

D2,e2

Ta]

ve
V2

813

I 12

B INHIBI

_____________________Mis

2
vAl

MEM

|
|

M9G3

A29

DONE

829

LRI

[

L
-

M360

—

CP PWR.OK

#T2

—

| LOCK(@)
- - -

- - -

BI3

Vie—— +3(I)

isz ol %CZD664 {|
i

[__‘

usd

Boe

THERMISTOR [T2|
.

—

P——
Abe
mns
Bra -

|
!!

AD2

BD2

BF2

)——I——«' AA2 AF2
+5(1
|*5¢2)——4Ba2 AM2

+5(4
) —+—1

+5(3)—+—4
AHZ AL2

|
POWER CLEAR

ere AJ2|AS2
|

REGULATOR

AND POWER

3F2

gs2| DETECTOR
, 6826

—

Bvz]

TAT2

150 N

-5

) A3

B3I

|BK2

b V2

===

| 6624

B@2

MEMORY SUPPLY
—

182

|
'

)

FIELD

|
|

)DTZ

vag3

REF

U?‘V\erl

r832
X

READ

B MEM ENABLE
WRITE

|
|

AB2

(1)

+3v (1)

AV?2 o——f———SLICE

ca2
—

: E2

—

RETURN

R/W

RETURN

St |
|

|
—I

6228

—

ve,

CLAMP

—

| E2
|

‘T‘vz

NEG CLAMP

________

NEG

HALF

r
M2

% LOOPS FOR

R/W

L‘

6228

[bz,

|
.

| -

R/W

|
|

:_|_: 2as |

SOURCE (8V)
|

SOURCE

__ _|__ = _|82

I
+5V

wal

SOURCE

33, Fa

| 823

vz |

R/W —\q

i
I

1,,

| 6624

=
ay2

lr—— —_

I
|

|
:

B2 . D2I

L—

{

LSTROBE

E2 S

UNREG — 15

,(\ZJEEMP

gv2 |

BL I

)

g?%:
2us

aN2

!
LiNE
LOW

BM2

AB3I av:_z.g :

MG 3

524

les2

|
_|

POWER SUPPLY
CONNECTOR
.

%ARZ

AK2

AJ2

lg7a5
'A,828

A Qi

| Be!
°e

)

| BV2
M|

GND BCZ AE2 BE2 BEZ - LMEMORY SUPPLY + | ..o
| AC3
6624
M
+5 REG SUP
|
a2
AC2

=
- —

el
Y

—I

e -

wo2s

tock ()

CvC DONE

w990

I
i

-15V

START

cveLe(n)

MEM

_________

INHIBIT (1)

l_ =

IM2.
MS03

[

MEASURING

SELECT

MEMORY

CURRENTS

D-BS-MC8-L-1

Memory Control

2 |

I
|

———

——

Ri8

—

MG23

haa

|
|

ZLR

;
i

AMF

IB,IF,DF

M3
!

‘

XIII

M216
i
AL
t
.
|

i
L__._L_ R

L.OAE SF

KEY CLEAR

A22

| —
|
=

Ll
|

IB,IF

EXT DATA ADD

m2i6 |
a2y
—_ e | —— e — e L
l

i
|

[

1H2

BMB 28

(@)

ROF

pT—

BMB G?B(gg 28.()

- 000
07

'm
T T T T T
I _______

sme 07 (1)

’

MIt7

—

ame g8 (1)

RIF

h20

.:
22t

]

BMB @7 (1)

gERIrEr

Ml S

‘

]

EY CLEAR

BIoP2

E SET +
F SET

leslas

CoF

SToF

w2,

L1 O

A24

BMB 09(1)

LT w1

¢
s

BMB

‘ _______ I

I Mt

. _R2
sfp

MN3

= T

A22

]

mate

N2 3y

|A24

M —‘l______
-

KEY DF

—_—————
= - — = = ——— —— - —

| K20

Al [TTot

[

[__K_ZQ @

I mnz

(¢)

ul
SFI

(1)

BMB

§3(2)

s8MB

¢4(|)

BMBge (1)

foae HI[W

BMB
95 @)T—— e

oRl:—+3V

BMA. B3

BMA D@

F () Mz
|

si|

Ju2

810P1

m————

S _BM_B_(JS_('_)_ _______ -

K2|@

+3v

R
I

H2 |

eves@

BMB £8(2)

S (o B o -l it
I T~

—| 5
LDAD SF

Ale

aF(1N—!

A25

—_— e

JMP + JMS
—_—
SET 1B, IF

E
R
=

v T1asr

SET

[

| M

b—

DK—’—o————SET 1BIF
;|

-5

i
|

—

‘_ ______ r—}— -~ -

INT nvegIT

I-I—

(CAD IF _L<DB'_:

[

L_
|

A24

|
|

I} A26

‘r—

- - == '

BMA 3

BMA @6

ottt

BMB 06 (@)

BMB 1 (@)

BMB 11(0)

BMA @9

BMB 1% (1

BMB (|

BMB 32 (P)

BMB @i ()

BMA @6
£l

(

BMB 22 (@)

BMA @9

smMB @8 (1)

BmM8 @1 (1)

ams 62(1)

— 1L.OAD SF
+

KEY CLEAR

D-BS-MC8-L-2

Memory Extension Control

8
1-

:g;: (aszy

gat2

[]J2

suppLY— |

ME MORY

AC2

Fal Az2

;

|twre

oarveqH
2l §p 2

’

laosk_

ENABLE

Vil —

BMBOO(Q)

_gmes

152

L 02

M 7TH

oriver|F (|

= g

AQ9

_MEM 02

MEM 03

BMB@4 ()

pMI

SENSE ©

SENSE @1 P

[TIsENsE @2P]

‘

Ci—y-

St —¢-

)

Cl—y-

—e

!
'

lpi

TYseEnsE @4P)

Cl—y

)

02_|E2

SAC2 ADZ
OMIT

FOR

Is2

S1—¢

(LM

Ly(o2_g2

et oM

OAE2 OAF?2

PAK 2 SAL2

SAM2 ®AN2

SAP2 ®AR?

P2iBo3

INHIB

YR2 |

[orwver|R2l

B DI

BMB@S8 (9)

B M2

BMBG9 (9)

_ __
_ _
MEM @9

MEM 10

MEM LL

902

]

SENSE &8P
]

[LE

4‘

ooy

pk2 ) M2

I
|

SENSE @9PT)
-

—¢

SENSE 10P
)
]

SENSE I

‘

Lt M

b2 je2

OBE2 ®BF2

bBH2 eBJ2

IR1

(o]

)

eBC2 #BD2

s8MBI | (@)

Teoz20

(02 €2

BMBI2 ()

e
_ _

BGY

[

JT2

D
|

6020

€l

oriver|NI'

G624

fr2

IRt

M1l B@3

NPT)

T2 |

|RiTe62as
|

;

‘

Ts2

.
mvel=
1

] D2

lg228

9BR2
)

L Ju2]'® | L_ Jsif "

Is2

LlMy oy |2 _jE2

jorver|FIl

NEEY

cl—¢

BP29

. BO3 |

SENSE @7[]

Is2

GAH2 OAU?

j—MEM 08

95!

SENSE 067

TNHIB

L _Jkif ®

]

—o

loy

6320

| R}

_ _

BN2

TM2 |

[IsENSE @5f
)

IRt
El

MR-8_-8

]

BM2¢

E1lBE3

N2 |

parvealH2!

| Al

BMBQ7 (@)

¢BL2

F2BG3

{ives

IT2

§12

Bk2e

|k2[662¢'T
— |H1 (41 Te624T ~ |52 T2Tcea
T ~ (A1

Iv2

I
7]

MEM @7

9FI

[TYseNsE @3P]

orver|NIl

BoS

|inwze

] LI

}MEM 06

MEM 05

I
1]

K2 |

L _g] 7

]

BMBG6 (@)

_MEM ga

Js2

MI'B@2

TEz
|

6020

] M2

BMBG5 (@)

|oriver|lR2

[

] DI

ABes
__ ___ ___ __

6020

¢BJ2

,EACH
Be2 |

BH2¢

=
6624

l| Al ] D2

BMBO
3 (D)

¢BF2

fvzl= 7

| G228

INHIB

| E2
|

BMBQ2 (@)

BE2¢9

P2l Bo2

L_ Jue

bAS? SAT2

_SEC

— ki

|
1]

ls2
g2

INKIB

I
[

| RY
£l

9BD2

TM2 |

B LI

E1}B@2

briverjH

iv2

1 T2

:‘33,5

uz2

]

Y12

L— e

BC2¢

|1 |J1 T662e
| ~ [$2 |T2T662s
T — |F1 RITce24
| ~|J2

N2 |

linms

9AR2

’

MEM Q1

oriver|NI!

B M2

Go20

| T2

L s

Y52

|rnus

F2lee2

AQS

AP2¢

|J2z [k2T662¢
T

MI| AG3

BMB@I (@)

oriver|R2!

] o]

| 6228

_MEM 0Q

{R2

ro3

PAN2

[T2T6624T ~ |P1 |RI 16624 T

P2l

|inwie

L — Jue

AM2

FIELD

9AL2

L RA33_|

MEM P

'
|

STROBE

priver|F Il

AK29

~F
G624

TIBECIN ——9—dsense P ]

|inwas

Iv2

| 81

Tp2

[

®AJ2

Ellae3

| T2

__
MEM

)

{6023

B MEM

oriverH2l

L- i

6228

AH29

[E2
[

3MB PARITY opbD

9AF2

|| Al B D2

€2

|Nwure

|— ==,
A2
T D2

AE2Y

Fa2l aes

c62s |

8 '”;"\i';
Suaas

A D2

|[k2Teb2e
T ~|v2 (k2 Te624T ~ [HI [U1T662¢
T 7 |S2

‘

|52

VAR

(D2 JE2

®BK2 eBL2

OBM2 ®BN2

U M0

BP2 8BR2

)

MC-8L-A

D-BS-MC8-L-3

Sense Amp and Inhibit Drivers
13

q G611
U

rszz<

o115V,

cea

cpo7

R2|

szl

»urlzlcfiz

| H2

R2l

[cF

I
i

X R/W SOURCE

9DE2

§DF2

2TM 124

§DH2

¢DJ2

pDK2

¢DL2

IDM2

TIS2TRIT
T T

¢DN2

06 3

$DP2

$DR2

¢DS2

DT2

$DU2

G6lg

§DV2
) ¢poas

Ney T T
T[SeT /2|7
(52
272 T T TP

KT 32T T TlMZT

. |

—|

b §

[

]

8Map3

ENABLE

SU-.

MEM

Joe]

_ _

RETURN

R
W

¢pD2

Clk2TM Jel TM 7 T M27 (2] — 7 Tz TNzlT
T

[2]

¢pc2

3
|

- _d

[

3
b

;

[

cC2

—

)

l
|

|CD2

—

oz.ezez 22

{ 27 3

——e

1"LZZ—E£i

{CE2

S8
EN

)

[

‘

s sz

) 20

P2l |cHz

30
~

| F2

jev2

40 3

[CK2

BB
i

CLAMP

Cte

!
BMAD | —————4>—D

G612 TF INSTALLED

452l

IN CDZ7
|%G6ll
IS REPLACED WITH A

oTM
s7£

c.2

NOTES:

“[,?

G2i\

[

NEs

[CNZ|

CM2]

BEMAQ2

|ICP2|

; o

" _____ B

ve)

BMA g —

[

iC—

[

‘%I

;

}

- 6¢

»in-m

CLAMP

2:| cs2

:
|

aMA02 —

[cu2

N I T2
& oq‘sz| =

——o

|
|'

—

;

D-CD-MC8-L-4

X-Axis Selection

(6221
| czz

‘

NZ:

[

FZS

R
/2

I—szzn

BMAGE —

C’”_‘

M2 |

l|
|
|

- =

ilcF

val

kel

MAGS ——»—D

IF2

]

3 VI ENABLE

L fzhEmEese—/
T

o
o
27 %

]

11€02

sgs E2

[

)

hat |

‘

TM~

—

M2 | CE2

|
P2l [CHZ
L

6612 IF INSTALLED

lya

s t;;;
67

lsaifcx2

IH2

IS REPLACED WITH A

#i-‘“

cL2

IMAQ7 ——

I *661l IN CDC7
-

a0 3

O 72—21 .

)

60 3

oyN2l11992

Nall¥

{

50 %

CP:

Jai

CLAMP

cR2

TM
| |enz
o

————————————

——l

p2, | cS2

Nes

;

CLAMP

7¢

by CcT2

NEG

s2! |cu2

R2|

SMAOS8

cDo5

etV

2MAQ7

GG(IZG

{

cea

)

|cc:

$DC2

]
¢DD2

DE2

DF2

me (2l
TR/Tzl
1 TM 7 7 TM
/]

Y R/W RETURN

eDH2

¢DJ2

POK2

#DL2

___

CLAMP

j
I

BMAI!

9DN2

pOP2

PJDR2

26 7

¢DS2

¢DT2

$DU2

Géll

4DV2
) (po7 %

Tl T T TN
RIT T TLlFeTNRlTT T ST
A2
"5(%'
N /1
t'g(%‘
J"S(‘jl

| 72

I
|

V2,

'|
]

z]s [
!

aMA g9

o2 £2 -1

]

BMA

6221
D98

R _10_____________

!'
|

]

i
b

22l
DGO
aman

(

[

pDM2

T Tlee TNl T T T ST RLT T TR

NEG

.
p

-8

I
D2 1
lE2 |

BMAGS

B MEM ENABLE
St

Y RMW SOURCE

BMA

F—————- -

NEG

CLAMP

oMAl —=— lg ______ i

D-CS-MC8-L-5

Y-Axis Selection
17

2 j

BMA
g4 e 35
)

Q€

A @9

MEM

START

MEM

—
DONE

A3l

[

()

(a0)

1
®
DI©

Cl
N
Dt*

cl
@
ol*

cl
d
D1
-

Cl
D!»

i
&
Bf
-»

TFi

13
K1

.=
L
=

o
*
M

-®L
M

NI
®

Ri|

Tai

F2|

[r2

e2|

—

Br]

—let
K1

BMA @8

B3¢

BMA @7

M9G3

A30

BMA §3

M9B3 M9g3

B29

BMA @2 -

M9@3

A29

S
BMA 01

M9D3

L
vl

kel

GO
vz
k2|

wen o
MEM

MEM

MEM
03
€

MEM G4

MEM 5
MEM

MEM &7

MEM @8
MEM ©

M2l

MB PARITY 00O

)

p2|

s2|

Jue

va|

\_/

[Te|

vz
.

oFi

HI
-»-

Te)Fi

H I

.
K1
Kl

1
o
.

Lt
»>
Ml

L
©
M

‘l'

NI
.

rRi|
-

NI
"

R
"]

k2|

el
le2|

{wk2|

ENRBLE
ST

semece

BTP3

KEV CLR

—

—
KEY OF

£ SET + F SET
*

1
-

Ri|

e2]

Je2

Fe|

lr2

Pl3

<21

)

m2i

[m2]

mef

Ima|

)

r2|

P2l

R2 |

s2|

[ue

BEMA

—
EMA

s2|

(T2|

ve|

|[u2
B

1
=

STOPO:

C.RPWRO
LINE

LOW

-»

Kev Coas — el
J2

1
-

o1y
K1
Kl

L
M

KEY IF

Lt
M

—_—
INTT5i5%F
INHIBIT

€2

wio — gzlb
ME

m2|

M903

T2l

[t2|

va]

1
=

D-IC-MCB8-L-6

Special Signal Connectors
19

2 |
PART

NO.

DimM YA

BCosA - |

| FT

BCOBA- 2

2 FT

BC@BA-3
BCOSA- 4

3 FT
2 FT

SCoBA- 6

BCOBA- 5

5 FT

gggg’“ 7

SEE NOTE *|

FLEXPRINT

SIDE

8 F
T

BC@P8A-IO

10 FT

BCOGA -

SEE NOTE

I. ATTACH
ITEM

“=Z

/2 FT

ITEM

(FLEX

¥®5

(EVELETS).

FLEXPRINT

FOLLOWING

LEN6THS,

—
]

)

ANT 7T 7

WIR

PINS,

EXAMPLE :

WIRED

ON.

P2-Al

4 TOLERANCES:

PRIOR

THE

29" T0
P

Pl-Al
AND

P2-B2

PI-B2
AND

(STD. CABLE)

—

4 IncH

5 FT

10FT

ELECTROACALLY

SEE NOTE

CUT

:NEXéDRlNTE.\DC”Tg‘N\P? (?):“ F-THE

5 FLEXFPRINT ¢ (
FLEXPRINT

FABRICATION ;

SIDE

CLAMP)

FLEXPRINT A’ — DIM ' PLUS IZ INCHES
FLEXPRINT “B”“— DIM “A” PLUS ., - -

0 TO 25
FT
Z

(TAPE)

THEN ASSEMBLE
ITEM®3
TO
ITEM *1 (FLIP CHIP) WITH ITEM *2 OR *g

4 FI

8A -8
BCZ8A - 3

NOTES:

1 INCH
2

—Z77)

INCHES

CONNUECTED

‘A

«——

D-UA-BC08A-0-0
21

BCOB8A Cable