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DEC-8L-D4BA-D

June 1970

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Document:	MC8-L FuncDescr Jun70
Order Number:	DEC-8L-D4BA-D
Revision:	0
Pages:	14
Original Filename:	DEC-8L-D4BA-D_MC8-L_FuncDescr_Jun70.pdf

OCR Text

DEC-8L-D4BA-D

MC8/L
MEMORY EXTENSION CONTROL
OPTION FUNCTIONAL DESCRIPTION

DIGITAL EQUIPMENT

CORPORATION o MAYNARD,

MASSACHUSETTS

Ist Printing April 1969
2nd Printing June 1970

The material in this manual is for information purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP
DIGITAL

FOCAL
COMPUTER LAB

MC8/L
MEMORY EXTENSION CONTROL

INST FIELD key raised, or by the program
through the Instruction Buffer (IB) register.

All

program executed transfers of the IF come from

the IB.

INTRODUCTION
An additional 4096 (4K) core memory can be

added to the standard PDP-8/L 4K core mem-

ory to yield the maximum storage capacity of
8192 words. Figure 1 shows the MC8/L modules and their locations in the BAO8 Peripheral
Expander and Figure 2 illustrates the Memory

Extension Control organization, and it's relationship to the standard memory. The Memory
Extension Control is placed in the BAO8 Peripheral Expander Cabinet as shown in Figure 2.

Transfer of MC8/L control and data signals
occurs mainly through the special signal cables
and connectors. The PDP-8/L 1/O BUS is con-

The content of the INST FIELD key is
loaded directly into the IF and the IB by manual operation of the LOAD ADDR key. When a
JMP or JMS instruction is executed, the content of the IB is transferred into the IF.

When an interrupt occurs, the content of the
IF is transferred to the Save Field (SF) regis-

ter.

At the end of the interrupt subroutine the
IF status is restored through the IB from the SF

by execution of the RMF instruction.

When the CIF instruction is executed (refer to
Memory Extension Control Instruction Descriptions in this section) the content of MBOS8 is
transferred to the IB; the content of the IB is

nected to the BAO8. Some of the I/O BUS signals are used by the MC8/L option; however,

transferred to the IF at the execution of a JMP

other options make use of this bus so it must be

the CIF instruction and the JMP or JMS, pro-

supplied.

or JMS instruction.

During the time between

gram interrupts are inhibited.

The following paragraphs describe the use of

the MC8/L control logic, and the Memory
Extension Control instruction set.

It is assumed

that the reader understands the memory timing,

Data Field Register (DF)

read, write, inhibit and sense elements of the

This 1-bit register determines the field used for

basic memory system described in Volume I,

data storage and retrieval.

Chapter 4, of the PDP-8/L Maintenance Manu~

al.

The memory system elements described

The DF can be

loaded from three discrete sources:

MBOS8, the
Save Field (SF1), and the DATA FIELD key.

above are identical to those in the expanded 4K

core memory; therefore, maintenance and opera-

tion are the same.

LOGIC DESCRIPTION

Initially, the DF is loaded from the DATA
FIELD key by manual operation of the LOAD
ADDR key. While the program is running, a

CDF (change data field) instruction can be used
to alter the content of the DF to permit selec-

Instruction Field Register (IF)

This 1-bit register determines the memory field
to be used for storage and retrieval of program
instructions. The IF register can be loaded
directly by pressing LOAD ADDR with the

tion of the other memory field.

Bit 08 of the

CDF instruction contains the desired field ad-

dress (either O or 1).

Once loaded, the con-

tent of the DF remains unchanged until altered;

either manually by LOAD ADDR and the asserted DATA FIELD key, or under program control

by a CDF instruction.

Figure 1

Memory Extension Control in the BAO8 Peripheral Expander

During a program=interrupt operation, the content of the DF is automatically stored in the

Extended Address (EA) Field Selection

Save Field register (SF1) and is restored to the
DF upon completion of the interrupt subroutine

allows access
to either memory field.

by the RMF instruction.

flop outputs, EA (for field O, the standard core

The EA flip-flop (drawing D-BS-MC8~L-2)
The flip-

memory) and EA (for the extended memory)

enable each memory timing generator when at
a high logic level.

Instruction Buffer Register (IB)

tion time of every JMP or JMS instruction

The EA extended address field enable flip-flop
can be activated from one of three sources: the
the IF register, the DF register, or the BF register. The IF register is gated to the EA flipflop except during a break cycle or an indirectly
referenced data handling instruction (AND,
TAD, ISZ and DCA). In addition, when the
LOAD ADDR and the INST FIELD keys are
operated, the IF is gated to EA to generate the
memory field enable level. The DF register is

strobes the output of IB into IF.

gated to EA when any indirectly-addressed

This 1-bit register provides input buffering for
data transfers made into IF under program con-

trol.

Manual transfers are made directly into

IF and, simultaneously, into IB.

This transfer

of data into both registers is necessary to pre-

vent inadvertent changing of the content of IF.
The output of IB is loaded into IF at the execu-

memory reference instruction other than JMP or

Save Field Register (SF)
This 2-bit register provides temporary storage
for the content of both IF and DF during a program interrupt. This is necessary to permit IF
and DF to be cleared so the program interrupt

subroutine can start in field 0. At the conclusion of the interrupt subroutine, an RMF instruction loads the content of SFO into IB for
subsequent transfer into IF, and the content of
SF1 into DF. The last instruction in the subroutine (JMP10) completes the transfer from IB,
to IF.

JMS is executed (AND, TAD, ISZ or DCA).
The BF decoder allows the BF to generate the
memory field select code during a break cycle.

Interrupt Inhibit
The interrupt inhibit (drawing D-BS-MC8L-2)
logic disables the INT OK (drawing D-BS-

PDP-8-L-7) level in the processor from the time
a CIF instruction is decoded until a JMP or

JMS command finishes the CIF instruction.
This prevents operation of an interrupt before
the field is changed.

Interrupt synchroniza-

tion is restored after the IF is loaded from the

IB, allowing further program interrupt to occur.
Break Field Register (BF)
MEMORY EXTENSION CONTROL INSTRUCTION DESCRIPTIONS

This 1-bit register determines the field to be
used for storage and retrieval of data transfers

from 1/O devices using the data break facility.
The BF is loaded from the EXT DATA ADD line

by BTP2 of the cycle before a data break is
initiated.

The following paragraphs describe the basic
microinstruction set necessary to control pro-

gram execution with the Memory Extension Control option. See Table 1 Basic IOT Micro-

instruction Set for the MC8/L.

Table 1

Basic IOT Microinstruction Set for the MC8/L
Mnemonic

Octal

Operation

62N1

Change to Data Field N. The data field register is
loaded with the selected field number (0 or 1). All

Program Interrupt

CDF

subsequent memory requests for operands are auto-

matically switched to that data field until the data
field number is changed by a new CDF command, or
during a program interrupt.

CIF

62N?2

Change Instruction Field. The instruction buffer
register is loaded with the selected field number
(0 or 1).

The next JMP or JMS instruction causes

the new field to be entered.
RDF

6214

6224

MB8 =>1B.

Read Dcta Field. The content of the data field
register is transferred into bit 8 of the AC. Bits 6
and 7 are cleared, all other bits of the AC are not
affected.

RIF

MB8 = >DF

DF = > AC8

Same as RDF, except reads the instruction field.
IF =>ACS8

RIB

6234

Read Interrupt Buffer. The instruction field and data
field, stored in the same field during an interrupt,
are read into AC 8 and 11 respectively. SFO = >
AC8 SF1 = > AC11

RMF

6244

Restore Memory Field, Used to exit from a program
interrupt.

Change Data Field (CDF)

Change Instruction Field (CIF)

This instruction (octal code 62N1, where N is
the octal number of the field to which control
is changing, N is Og for field 0, and 1g for

This instruction (octal code 62N2, where N is
gram is changing) is executed prior fo JMP or

data with any indirectly~addressed memoryreference instruction other than JMP or JMS.
This instruction is generated by combining
BIOP1 and MBO3 through MBO7 levels (drawing
D-BS-MC8-L-2).

MB08 (N = MB06 a 0, MBO7 a 0 and MBO8
either a O for field 0 or 1 for field 1) to be
loaded into the IB by combining it with BMBO9
(0) to enable the IB flip-flop data input and
clocking the clock input with LOAD IB. The

field 1) is used prior to storing or retrieving

the octal number of the field to which the pro-

JMS instruction.

The 62N2 instruction allows

content of IB is then transferred to the IF when
the next JMP or JMS command is executed

(LOAD IF active).

Read Data Field (RDF)

This instruction (octal code 6214) reads the
contents of the DF flip-flop onto the ACIO8

line. The data is transferred to accumulator
bit ACO8 in the same manner as with the RIB

Restore Memory Field (RMF)

instruction.

This instruction (octal code 6244) restores the
contents of the SF to the DF and IB registers.

The conclusion of an interrupt subroutine (JMP

10) loads the IF from the IB. RMF (drawing

D-BS-MC8-L-2) allows bit SF1 to be loaded in-

to the DF.

The content of the IB is transferred

to the IF by executing a JMP or JMS instruction.

Read Instruction Field (RIF)

This instruction (octal code 6224) reads the contents of the IF flip-flop onto the ACIO8 line.

The data is transferred through the INPUT BUS
08 line to bit ACO8 in the same manner as the
RDF.

Read Interrupt Buffer (RIB)

This instruction (octal code 6234) allows storing
that same field in memory if the power failure

ENGINEERING DRAWINGS

option is installed.

The following drawings pertaining to the

This instruction reads the
contents of the 2-bit SF register into the AC on

the ACIO8 and ACIIT lines (drawing D-BSMCB8-1L-2). These lines activate the INPUT
BUS 08 and 11 lines in the processor.
Execution of the RIB instruction generates AC

LOAD and AC ENABLE in the processor which
allows transfer of the data on INPUT BUS 08

MC8/L option are contained in this section.
Drawing Number

D-BS-MC8-L-~1
D-BS-MC8~L-2

Title

Memory Control
Memory Extension Control

D-BS-MC8-L-3

Sense Amp and Inhibit

ing D-BS-PDP8-L-~6) is generated by 1/O EN-

D-CS-MC8-L-4
D-CS-MC8-L-5
D-1C-MC8-L-6

X~-Axis Selection
Y-Axis Selection
Special Signal Con-

produces AC ENABLE (drawing D~BS-PDP8-L-

D-UA-BCO8A-0-0

BCO8A Cable

and 11 to the accumulator.

AC LOAD (draw-

ABLE and I/O STROBE as a result of performing
this IOT (6234) command. 1/O ENABLE also

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