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EK-KK11A-UG-001

October 1978

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Document:	KK11-A Cache Memory Users Guide
Order Number:	EK-KK11A-UG
Revision:	001
Pages:	28
Original Filename:	EK-KK11A-UG-001_Oct78.pdf

OCR Text

(]

EK-KK11A-UG-001

KK11-A

cache memory

user's guide

digital equipment corporation - maynard, massachusetts

Ist Edition, October 1978

\‘/

The drawings and specifications herein are the property of Digital Equipment
Corporation and shall not be reproduced or copied or used in whole or in part
as the basis for the manufacture or sale of equipment described herein without
written permission.

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in
this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL
DEC
PDP
DECUS

DECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM

MASSBUS
OMNIBUS
0s/8
RSTS

UNIBUS

VAX

RSX

VMS

IAS

CONTENTS

Page

OVERVIEW ...ttt
tes s sre e s e sssa s s e e e essae s e sesntsses s snnasesesnaneess 1-1
PHYSICAL DESCRIPTION ......oooiiiiiiiiiiimiec ettt e
e 1-1
SYSTEM ARCHITECTURE.........ccooiiiii
ittt creee s e 1-1
CACHE MEMORY ORGANIZATION.......cooiiriiiceenee et 1-1
Addressing Cache.........ooooeiiiiii
e
e e 1-3
MU PTOCESSINE.c.eeeeeeirereiereeecriire
e eee s e e reecee e bbae e e eesesatbbeeseesesosenasnnes 1-4
NPR Memory References.........cccevvuieeieriiiiniiiiniciens
e seeerece e 1-5
Unibus REGISTEIS .....uveeiiieieieiiiireeerneeeeceneeetete
e eesisineretes essssnsareeseesesesennenne 1-5
PerfOrmMancCe.......ccoouuiieeeieieceeeeres
et crer e
e ae
s 1-5

CHAPTER 2

INSTALLATION

2.1

SCOPE ...ttt
e e sererte s s saarase s st bbe s eae s eense e e senart e e e e snnneeeennnne2-1
UNPACKING AND INSPECTION .....cooiiiiiiiiieniteeeceeee st 2-1
UNPACKING ...evvviieiieiierieie
et iittae e s e steeesee s sessanae e e essesesaanns2-1
PRE-INSTALLATION CHECK.......ccccoiiiiiiiiiiiiiititeeeceteecccteee
e 2-2
BA11-KA MOUNTING BOX INSTALLATION PROCEDURE ...................... 2-2
BA11-L MOUNTING BOX INSTALLATION PROCEDURE........................ 2-6
OPERATION ... .ottt
et es et et e sae e e s smeesae s sambeaesennns2-7
CHECKOUT PROCEDURES. ...ttt
e sraeene e e e 2-7

CHAPTER 3

SERVICE
MAINTENANCE PHILOSOPHY ...ttt
eeee e eeneae e 3-1
SYSTEM MAINTENANCE AND TESTING .......ccocooiiiiirerreeeecceieeeenee 3-1
TROUBLESHOOTING GUIDELINES.........cccooiiiiiiienieen et 3-1

W N

22
2.2.1
222
23
24
2.5
2.6
2.7

f.db)b)

n BN
-

esd paad

)

INTRODUCTION

- aaabnLios

CHAPTER 1
—

PREFACE

INSPECTION ..t
ee et eeaeeeereereeer e ereeeneeaeeenaaasaesaaassasssesnssensanes 2-2

FIGURES

Figure No.
1-1

1-2

Title
General System ATchiteCture.......ccoiiiiiiiiiiiiei oo
Cache Memory FOrmat........coooeiiiiiiiiii i

iil

Page
e e 1-2
aaneens 1-2

FIGURES (Cont)
~

Title

Page

Direct Mapping Cache Memory System ...........cccocceeeee ....................................... 1-3

Cache Installation Diagram..........c.cccccceevivirininnierecnnnnns ....................................... 2-3
Power /Configuration Schematic ...........cccooeiicennene ....................................... 2-5
Troubleshooting Flowchart.........cccocoiinniiinnin ....................................... 33
e ....................................... 3-8
Backplane JUMPETrS ........ccccoovimiiiiniiiennniiiin

TABLES
~—r

wt.\)-—-

)
it o

Table No.

Title

Page

Cache Responses to Hit/Miss Operations.............coce.e.e ....................................... 1-4
+5 V Power Consumption For Some Common Options ....................................... 2-4
Maintenance Equipment Required...........cccccooeiinnnnen. ....................................... 3-1

‘/

PREFACE

This manual describes the KK11-A Cache Memory option to the KD11-EA central processing unit of
the PDP-11/34A system. The user must be familiar with the KD11-EA to completely understand the
contents of this manual.

The following documents are useful references:

KDI11-EA Central Processor Maintenance Manual (EK-KDI1EA-MM-001)
KDI11-EA Print Set (MP00043)
KK11-A Print Set (MP00574)
BA11-K Print Set

KY11-LB Programmer’s Console/Interface Module Operation and Maintenance Manual
(EK-KYI1LB-MM-001)

CHAPTER 1

INTRODUCTION

1.1 OVERVIEW
The KK11-A is a cache memory option to the PDP-11/34A’s KD11-EA processor. The cache is a
small, high-speed memory that maintains a copy of previously selected portions of main memory; it is
designed to decrease central processing unit (CPU) to memory read access time.
1.2

PHYSICAL DESCRIPTION

The KK11-A is implemented on a hex multilayer module (M 8268) that contains a 1024-word, high-

speed random access memory (RAM) organized as a direct mapped cache with write-through com-

patible with the current version of the PDP-11/34A. The M8268 module interfaces to the KD11-EA
processor (M 8265 module) via a 40-pin over-the-top connector (H8821 or H8822). The only power
required is 5 Vdc at 4 A maximum (Figure 2-2).
1.3

SYSTEM ARCHITECTURE

Cache operates as an associative memory in parallel with the Unibus main memory but with its own
high-speed data path (AMUX lines that are also used by the FP11-A - a floating-point option). Cache
reads by the CPU result in data being transmitted over the AMUX lines. Read misses (desired data is
not present in cache) and write hits (bus address and cache location match) which result in cache
updates are accomplished by the cache capturing the data from the Unibus as the CPU/main memory
transaction occurs. Direct memory access (DMA) transfers to memory are also monitored by the
cache (Figure 1-1).

1.4

CACHE MEMORY ORGANIZATION

Cache memory consists of twenty-eight 1024 X 1 RAM chips arranged as shown in Figure 1-2. Specific
implementation of the cache memory organization for the PDP-11/34A is as follows.
Cache Characteristics

PDP-11/34A Implementation

Address mechanism

Direct mapping - allows each word from main memory only
one possible location in cache. Requires only one address comparison (Figure 1-3).

Block size

Block size of one - every time a fetch to the backing store
(main memory) occurs, only one word is allocated to cache in
the event of a miss.

Set size

Set size of one - there is one unique location in cache for any
given word from backing store. If a miss occurs, only one
cache location is available for data to be written into.

Write-through

Data from a write operation is written into cache and simultaneously copied into main memory. Maintains main memory
(backing store) with a valid copy of all data.

1-1

I
|
K

UNIBUS

>
~

R MISSESMW HITS
CACHE

DMA

UP-

foaresl
|
CPU

CACHE

NPR

DEVICES

"MONITORED BY
CACHE

READS

[7{o]

MEM

A MUX

FP11-A

(OPT.)
ALL MEMORY SHOULD BE LOCATED

BETWEEN THE CACHE AND ALL NPR DEVICES

r—--—-=-—="77

cru

MA-1896

~—

Figure 1-1

General System Architecture

(28, 1024X1 RAM CHIPS)

PARITY——;

PAR'TY—_l

VALID BITS ——

PARITY———J I ——HI BYTE——I l'——LO BYTE .

je— ADDRESS
—
171615141312113}

j————————188ITS
P

—

B'A15141312111098P 766 43 2710 P
.

|
|

I
1

POSITIONS

CACHE INDEX

F— TAG FIELD —»

!
|

- — — —

—DATAFIELD— — —

—

|
!

[}

1023, [

"——-——-———-28 BITS

1024 WORDS

BLOCK SIZE OF 1
SET SIZE OF 1
VALID BITS = TWO SETS:
SET OF 1024 A BITS
SET OF 1024 B BITS
MA-1900

Figure 1-2

Cache Memory Format

~——

MAIN

MEMORY

ADDRESS
287460

BLOCK

257450

CACHE

1 201620

hANAN A

S
Wg
W0
W

8412

4570

m—— <7}

1302

746

11-2835

Figure 1-3

Direct Mapping Cache Memory System

The 1024 cache index positions contain 28 bits each. The tag field contains seven address bits. Each
position contains a tag parity bit and two valid bits. One valid bit is currently active, allowing the other
bit to be cleared concurrently. The use of two sets of valid bits allows the cache to be flushed (cleared)
by switching to the second previously cleared bit set and then clearing the first set of valid bits. This
method allows the use of one set of valid bits while the other set is being cleared, useful in multiprocessing applications. The data field of the index position consists of two 8-bit bytes of data, each
with byte parity.

1.4.1

Addressing Cache

When addressing cache, the PDP-11/34A uses an 18-bit address formatted as shown below.
1, 0 | — BiT POSITION

11410

| |— cacke FieLo Name

CHECKED AGAINST
TAG FIELD OF

ADDRESS OF 28-8/T WORD
IN CACHE

INDEX WORD

BYTE FIELD — SELECTS
HI OR LO BYTE

MA-1059

The lower part of the address (10:1) is applied against the 1K cache matrix and the high-order bits
(17:11) are checked against the tag field of the index word obtained (data field in cache). If the tag field
in the address matches the tag field stored with the data in cache, a hit is designated. If the fields do not
match, it is designated as a miss.

1-3

The processor always looks for data in the fast cache memory first.
If a CPU hit occurs during a read non-bypass mode (Table 1-1) data is read from cache; in
bypass mode, cache is invalidated.
If a CPU hit occurs during a write non-bypass mode, data is written into cache; in bypass
mode, cache is invalidated.
.

If a CPU miss occurs during a read non-bypass mode, data and tag are written into cache; in
bypass mode, cache is not affected.
If a CPU miss occurs during a CPU write non-bypass or bypass mode, cache is not affected.

Table 1-1

Mode

Read

Bypass

Cache Responses to Hit/Miss Operations

DMA Miss*

Not

Affected

DMA Hit*

CPU Hit

Not

Cache

Affected

Read

CPU Miss

Write Data
Write Tag

Write Valid

Read
Bypass

Write

Not
Affected

Invalidate
(UCB)t

Invalidate

Bypass

Affected

Not

Invalidate

Write
Bypass

Not
Affected

Invalidate

Write Data
Write Valid

(UCB)t

Not
Affected

Not

Affected

Not
Affected

*DMA hit/miss operations are discussed in Paragraph 1.4.3.
tUCB = Unconditional bypass

14.2
Multiprocessing
Additional functionality is required to perform multiprocessing.

¢ Unconditional Cache Bypass
In bypass mode, all memory references are forced to be misses and to invalidate (clear valid bit)
on cache hits.

Conditional Cache Bypass*
A virtual page can be defined such that all memory references to that page by the CPU result in
being bypassed.
LOCK (ASRB) Instruction*

Guaranteed ownership of the cache for the duration of the destination operand cycle; must
operate in bypass mode.

*Not implemented in the KD11-EA Processor.
~~

1-4

NPR Memory References

1.4.3

o Ifa DMA hit occurs during a read non-bypass mode, the cache is not affected; in bypass mode,
cache is invalidated (unconditional cache bypass) Table 1-1.

e If a DMA hit occurs during a write non-bypass mode or bypass mode, cache is invalidated.
e If a DMA miss occurs during a read or write bypass and non-bypass modes, cache is not
affected.

1.4.4

Unibus Registers

The following hardware registers are implemented in the cache.
e Cache Memory Error Register (CME)
Address 777 744

Parity error detection of cache memory, high byte, low byte, and tag.

e Cache Control Register (CCR)
Address 777 746

The state of specific CCR bits control (1) valid, UCB, and flush cache, (2) the response of the

cache to parity errors, and (3) the occurrence of CPU forced misses.
e Cache Maintenance Register (CMR)
Address 777 750

Contains one read/write bit used for memory system maintenance.
¢ Cache Hit Register (CHR)
Address 777 752

Contains the seven bits of the tag store memory of the last valid access and indicates the

number of cache hits on the last six CPU accesses to non-1/O page memory.
1.4.5

Performance

The cache system is intended to simulate a system having a large amount of moderately fast memory.
Therefore, the system contains a small amount of very fast memory (cache) and a large amount of slow
memory (backing store). The cache system works because it can successfully predict which words a
program will require most of the time. Program behavior is such that cache hits should occur 85 to 90
percent of the time, substantially decreasing average access time.

Unibus Transactions - For a normal memory read (MM11-DP), BUS BUSY is asserted for 1.2 us. A
cache hit read results in the CPU asserting BUS BUSY for approximately 450 ns. Thus, for every cache
hit, about 750 ns are saved.

CHAPTER 2
INSTALLATION

2.1

SCOPE

Information for installing the KK11-A Cache Memory option and checkout procedures to ensure
proper operation of the cache and the system are provided in this chapter.

The following tools are required:
N

No. 2 Phillips screwdriver
Multimeter with ohm capability
Diagonal cutting pliers

Soldering iron, 40 watt
Solder sucker
Spares kit (Control Distribution)
Wire-wrap tools

2.2

UNPACKING AND INSPECTION
NOTE

Customer should not unpack the cache memory
option unless a DIGITAL representative is present;
to do so voids the warranty.

Unpacking

2.2.1

If the customer’s receiving area procedures require it and/or to facilitate inventory, the shipment may
be moved to the computer area. Otherwise, unpacking and inventory must be done in the receiving
arca.

Follow steps 1 through 4 to unpack the shipment.
1.

Ensure that the shipping container is sealed. If container is open, notify the customer and
record it on the installation report or LARS form.

Check the shipment against the packing list to ensure that the correct number of containers
has been received and that they are the correct ones. If the shipment is incorrect, notify the
customer and the branch service manager or supervisor. The customer should check with the
carrier to try and locate the missing item(s).

Check all containers for external damage. If any damage is found, notify the customer and
record it on the installation report or LARS form.

Open containers one at a time, starting with the one marked “OPEN ME FIRST.” Inventory the contents of each package with its packing slip and record any missing items on the
installation report.

~—

NOTE

Packing materials such as foam fillers and plastic
inserts should be retained if reshipment is con-

templated.

2.2.2

Inspection

Inspect each component for damage, e.g., scratches, chips, or breaks. Report any damage to the
customer and record it on the installation report. Report any damaged components that require re-

placement immediately to the branch service manager.

2.3

PRE-INSTALLATION CHECK

The KK11-A cannot be installed unless the CPU is a PDP-11/34A. Inspect the serial number tag for
proper CPU verification. Ensure that the CPU is operating properly by running the following diagnostics.

DFKAA
DKKTH
CcZQMC

PDP-11 /34 basic instruction test
KT exerciser (PDP-11/34)
0-124K memory exerciser (16K)

The KK11-A cache memory option for the PDP-11/34A consists of the following:
M8268
H8821
H8822

2.4

Cache module
20-pin over-the-top (OTT) connector
20-pin over-the-top (OTT) connector

BA11-KA MOUNTING BOX INSTALLATION PROCEDURE

The BA11-KA mounting box is capable of delivering 64 A of +5 Vdc, which is supplied by two H7441
regulators. The +5 V is distributed to the backplane in the BA11-KA via five Mate-N-Lok connectors.
One H7441 +5 Vdc regulator supplies two Mate-N-Lok connectors; the other H7441 +5 Vdc regulator supplies the remaining three Mate-N-Loks. The PDP-11/34A CPU backplane, DD11-PK,
attaches to the BA11-KA power distribution board via connectors J9 and J11, thus allowing the CPU
backplane the full capabilities of one H7441 regulator (i.e., 32 A of +5 Vdc). To prevent overloading
of the +5 Vdc, the current drain of the modules contained in the DD11-PK should not exceed 32 A
(Table 2-1).

If the total current drain used by the devices in the BA11-KA exceeds 61 A without cache, an expander
box will be needed (Figure 2-1).

NOTE

To prevent overloading of the +5 Vdc, the current
drain should be calculated. The current drain should
not exceed 32 A in the DD11-PK backplane.

SEE NOTE 1

SEE NOTE 6
SEE NOTE 1

SEE NOTE 6

m8268

MB8265

|~
M8266

-/
/ LA

MB8256

M8266

34241

SLOT CONFIGURATION “C”

SEE NOTES 3 & 4

SEE NOTE 6

\N <

%SEE NOTE 2

#5 #4 43 42 1
sLoT

#3 #2 i

"D~

NOTES:
1.

SEE NOTE 5

MODULES M8265 AND M8266 ARE PART

CACHE MEMORY (KK11-A) | D-UA-M8268-0-0] 3

BOARD. \ INTERCON N4

O PIN

-0- | 2
UA-H8821-0-0

D-UA-

D-UA-H8822-0-0 | 1

sLoT

CONFIGURATION “'B"
SEE NOTE &
4.

OF KD11-EA AND ARE SHOWN FOR REF.

CONFIGURATION C SHOWS SLOT3 UTILIZATION FOR EITHER KK11-A OR FP11-A

ONLY.

ALL CONFIGURATIONS SHOWN ARE
USED IN THE BA11-K {10.5in. BOX)

PARTS LIST

1 ] TRICONN BOARD

#L #4 43 42 41

THE W9042 EXTENDER BOARD ASSY. IS
USED FOR SOME MAINTENANCE OPER-

:
i

ATIONS.

SEE NOTE 3

STORED IN THE BACKPLANE AND IS
MA-2277

CONFIGURATION “A”
SLOT CONFIGURATION

WHEN ONLY ONE IS PRESENT.

M8267. 5412416 AND W9042 ARE PART
OF FP11-A AND ARE SHOWN FOR REF.

ONLY.

CONFIGURATIONS B & D SHOW TYPICAL
MAINTENANCE SET UP.

OR BA11-L (5-1/4 BOX).

MA-2278

Figure 2-1

Cache Installation Diagram

2-3

Table 2-1
+5 V Power Consumption
For Some Common Options
—

Option Number

Description

+5VA

Mounting Code

ARI11

10-bit A/D converter
Line interface and clock
Digital 1/0
Synchronous line interface
Programmer’s console/interface

40A

DL11-WA/B
DRI11-K
DUP-11
KYI11-LB

Hex
Quad
Quad
Hex
Quad (in PDP-11/34

LA180
MSI1-FP

DECprinter I
8K MOS memory

1.5A
20A

MSI11-JP
MM11-CP
MMI11-DP

16K MOS memory
8K core memory
16K core memory

20A
30A
30A

20A
25A
36A
30A

CPU backplane)
Quad
Hex
Hex
Hex Quad
2 Hex

M7850
M9301
M9302

Parity control
Bootstrap
Unibus terminator

RX1t
TMBI11
LP1IW.V
MMI11-YP
FP11-A

Floppy disk

I5A

Quad

Tape control
Printer
32K core memory
PDP-11/34 floating-point

6.0A
1.5A
50A
70A

SUt
Quad
2 Hex
Hex

DLI11A-E
DUI1
KGl1l1
RK11-D

processor (FPP)
Asynchronous line interface
Synchronous line interface
CRC generator
RKOS controller

1.8A
20A
1.2A
75A

Quad
Quad
Quad
SUt

M9312
RK611

Bootstrap
RKO06 controller

20A
150A

DH module
2 SUst

KDI11-EA

1.0A
20A
1.3A

PDP-11/34 A CPU

11.5A

—

DH* module
DH* module
DH* module

.
-

—

2 Hex

*DH = double height.

+SU = single unit.

Perform the following steps when installing KK11-A with the FP11-A present.
1.

Turn system power OFF.

Extend the BA11-KA mounting box from the system.

Remove the top cover by loosening the screw at the side, then slide the cover off.

If the KY11-LB is present, remove the two maintenance connectors from the M8266.

Remove the 54-12416 OTT connector from the M8266 and M8267 modules.

Remove the M8266 module from slot 1.

Visually verify that M8266 ECO No. 4 is installed by checking that resistor R2 is 1 k{2.

NOTE

Where R2 is less than 1 kQ, install a 1 kQ resistor
per instructions on M8266 ECO No. 4.
8.

Replace M8266 into slot 1 and replace the 54-12416 over-the-top connector.

Remove the H8821 connector from the M8265 and M8267 modules.

10.

11.

Remove any module in slot five and carefully reconfigure the modules in the DD11-PK

backplane (Figure 2-2).

Insert the M8268 module into DD11-PK slot 5.
NOTE

To prevent overloading of the +5 Vdc, make sure
that the current drain does not exceed 32 A. Calculate power consumptions using 4 A for KK11-A
(cache), 7 A for FP11-A, and 11.5 A for KD11-EA.

CPU

)

CPU—>(11.58)

FP11-A (FPP)e

(7.08)

KY11-

BOOT

L1200

vi1-L8

e NOTES:

{3.0a)
y

KK11-

PARITY CORE MEMORY IN SLOTS 8, 7,

HEX OR QUAD »

AND 8.

HEXORQUAD+
:

° umaus]

]

HEX OR QUAD «

QUAD o

JuniBus

(2.0n)

QUAD -

ADDITIONAL

BEFORE PLUGGING IN ANY ADDITIONAL
INTERFACES INTO THE EMPTY SLOTS IN

THE CPU BACKPLANE. PLEASE DO A

3 [ (1) 84K BYTE (5.08) (2) 32K BYTE (4.08)

POWER CONSUMPTION CHECK IN ORDER

TO ENSURE THAT THE 32 AMP POWER

MM11-YP OR MS11-JP

REGULATOR LIMIT FOR THAT CPU BACK-

5 | (1) 84K BYTE (5.0a) (2) 32K BYTE (4.0a)
P

OD11-DK IS REQUIRED FOR ALL MEM-

IN THE FIRST 9-SLOT BACKPLANE.

DL11-W {2.0

PARITY

IF THE FP11-A IS USED, A

ORY DUE TO THE POWER RESTRICTIONS

’
MAY BE USED FOR B4KW of) MS11-JP

PARITY MEMORY OR 32KW OF MM11-YP

.
1-A (CACHE) = {4.0a)

5
6

IF THE FP11-A (S NOT USED, THE 7.0a

PLANE HAS NOT BEEN EXCEEDED.

MM11.YP OR MS11-JP

;

HEX OR QUAD o

HEX OR QUAD »

M8302

2] (130

QUAD «

{1) SYSTEM UNIT »
MA-2279

Figure 2-2

Power/Configuration Schematic

12.

Install the H8822 connector on the M8265, M8267, and M8268 modules (slots 2, 3, and §,
respectively). Make sure the arrow on this connector points toward slot 1.*

13.

Check that both FORCE MISS switches S1 and S2 are on. Have both switch handles pointing toward the console.

14.

Loosen both screws on the bottom of the BA11-K
A mounting box and remove the cover.

*When using other than the M9301-YF bootstrap terminator, the handle of the bootstrap terminator may interfere with the H8822 connector. Therefore, carefully remove that part of the handle which interferes.

2-5

15. Check for continuity between backplane connection CO1E1 and B02A1. This is the cache hit
line; if not present, a jumper (30 gauge wire, DIGITAL P/N 91-05740) should be installed.
Then recheck for continuity.

16. Replace the bottom and top covers, and slide the BA11-K into the system chassis.
17.

Power-up the system.

18. Verify the CPU, cache, and FP11-A by running the diagnostics listed in Paragraph 2.7.
To install cache when the FP11-A is not present, perform the following steps.
1.

Repeat steps 1 through 8.

Remove any module in slot 3 and carefully reconfigure the modules in the DD11-PK back-

plane (Figure 2-2).

Insert the M8268 cache module into slot 3 of the DD11-PK.

Install the H8821 connector on the M8265 and M8268 modules (slots 2 and 3, respectively).
Make sure that the arrow on this connector points toward slot 1.*

5.
6.

Check that both FORCE MISS switches S1 and S2 are on. Have both BATT switches

pointing toward the console.

Complete steps 14-18 in the previous procedure.

2.5 BAI1l-L MOUNTING BOX INSTALLATION PROCEDURE
The 13.3 cm (5 in) BA11-L mounting box can contain a power supply with eithera32 Aor25A +5V
regulator. Use the following chart in determining whether you have the proper 32 A supply.
Cwurrent

Regulator

25A

H777-AA
-AB
-BA
-BB

32A

H777-CB
-CA
-DA
-DB

NOTE

To prevent overloading of the +5 Vdc, make sure
that the +5 Vdc current consumption does not exceed the capacity of the regulator.

Perform the following steps when installing the KK11-A in a BA11-L mounting box.
1.

Slide the wire frame out of the wrap-around.

Turn CBI to off first, then turn the DC ON/DC OFF switch to DC OFF.
If the KY11-LB is present, remove the two maintenance connectors from the M8266 mod-

rl:/llzke sure that the DD11-PK is Rev C or later.
Remove the M8266 module from slot 1 and visually verify that ECO M8266 No. 4 (R2 =1
kQ) is installed.
NOTE
:
:
When R2 is less than 1 k2, change this resistor per
instructions on M8266 ECO No. 4.

Replace M8266 into slot 1.

Remove any module in slot 3 and carefully reconfigure the system.
Insert the

M 8268 cache module into DD11-PK slot 3 or 5.

Install the H8821 or H8822 connector on the M8265 and M8268 modules (slots 2 and 3 or
slots 2 and 5, respectively). Make sure arrow points toward slot 1.
10.

Check that both FORCE MISS switches S1 and S2 are on. Have both switch handles pointing toward the console.

2.6

Reconnect the KY11-LB maintenance cable to the M8266 module.

12.

Turn CBI on and slide the wire frame inside the wrap-around carefully.

13.

Turn DC OFF to DC ON.

14.

Verify CPU, memory, and cache by running the diagnostics listed in Paragraph 2.7.

OPERATION

The cache module is program transparent. The only observable effect while in operation will be
reduced program run time.
2.7

CHECKOUT PROCEDURES

Run CPU and PDP-11/34A cache diagnostics for verification of the functionality of the options.
e PDP-11/34 Diagnostics
DFKAA
DFKAB

DFKAC
DKKTH

CzZQMC

PDP-11/34
PDP-11/34
PDP-11/34

Basic instruction test
Trapstest

ElSinstruction test
KT exerciser (PDP-11/34)

0-124K memory exerciser (16K)

2-7

e PDP-11/34A FPP Diagnostics

DFFPB

PDP-11/34

FPP Diagnostic Part |

DFFPC

PDP-11/34

FPP Diagnostic Part 3

DFFPB

PDP-11/34

FPP Diagnostic Part 2

~—

e PDP-11/34 Cache Diagnostics

CFKKAA

PDP-11/34

Cache diagnostics

The startup procedure is non-stanard form. A “RUN” command is required in addition to the
normal load and go at address 200.

Procedures are included with the diagnostic media.

e DEC/X11 monitor - the QABM monitor must be patched when the command “CON” for
cache on is given.

The patch for this problem is:
~—

MOD

13136

13140

240

~—

CHAPTER 3

SERVICE

3.1

MAINTENANCE PHILOSOPHY

The field maintenance and repair philosophy reflects a module replacement approach. Once the cache
has been identified as the failing option in the PDP-11/34A system, the module should be replaced.
The faulty cache is returned to the Maynard facility in Massachusetts or to European Depots for
repair (whichever location is feasible). Because of the complexity of the cache module and its etch
width, on-site component level repair is not encouraged. The standalone diagnostics should be run to
detect the cache module failure.
3.2 SYSTEM MAINTENANCE AND TESTING
For a PDP-11/34A system that is unable to load diagnostics, use procedures in Chapter 6 of the PDP11/34A4 System User Manual to diagnose the problem. Table 3-1 lists the maintenance equipment
required to troubleshoot the cache.

Table 3-1

Maintenance Equipment Required

Equipment

Manufacturer

Model/Type/Part No. | DEC Part No.

Oscilloscope

Tektronix

453*

Volt/Ohmmeter (VOM)| Triplett

Unwrapping Tool

29-13510

Gardner-Denver

505244 475

29-18387

A-20557-29

29-18301

1018

29-13467

DEC Catalog #11812A

Hand-Wrap Tool

Gardner-Denver
DEC Catalog #11811A

Wire Strippers

Miller

Module Extender
Boards (2)

DEC

W9042

*Tektronix type 453 oscilloscope is adequate for most test procedures; Type 454 or equivalent may be required
for some measurements.

33 TROUBLESHOOTING GUIDELINES
The following guidelines are provided for debugging failures in the cache memory module installed in
a PDP-11/34A system. Standard PDP-11/34A diagnostics should be run first before attempting to
follow the procedures outlined in this section.

3-1

To verify the system integrity, run the following diagnostics in the sequence given below.
DFKAB
DFKAA
DFKAC
CZQMC

Traps Test (at lease Rev C)
PDP-11/34 CPU Test
EIS Test
0-124K Memory Exerciser

If the FP11-A option is included with the system, run the following diagnostics.
DFFPB
DFFPB

DFFPC

PDP-11/34 FPP Diagnostic - Part 1
PDP-11/34 FPP Diagnostic
- Part 2

PDP-11/34 FPP Diagnostic - Part 3

The flowchart in Figure 3-1 is a helpful tool in troubleshooting the system.

3-2

~——

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ANY

LOAD ADDRESS

NPR DEVICES

LOCATION 200

BETWEEN CACHE

A
AND DEPOSIT

AND MEMORY,

BRANCH SELF (777)

ALL MEMORY MUST BE BETWEEN THE

PRESS CONTROL

CACHE MODULE AND ALL NPR DEVICES.

START CAUSING

REMOVE RESPECTIVE NPR DEVICE AND

EXECUTION OF THE

REINSTALL IT ON THE OTHER SIDE OF

INSTRUCTION

THE MEMORY (SEE FIGURE 1-1 OF

CHAPTER 1). IN CACHE. MSYN IS INHIBITED. THUS ABORTING THE MAIN

MEMORY TRANSFER. CACHE HITS BY

HALT THE CPU AND

THE CPU RESULT IN THE DATA BEING

EXAMINE THE CACHE

TRANSMITTED OVER THE AMUX LINES.

HIT REGISTER

READ MISSES AND WRITE HITS WHICH

ADDR=777752

RESULT IN CACHE UPDATES ARE
ACCOMPLISHED BY THE CACHE
CAPTURING THE DATA FROM THE
UNIBUS AS THE CPU/MAIN MEMORY
TRANSACTIONS OCCUR. DMA TRANSFERS

TO MEMORY ARE MONITORED BY
THE CACHE IN ORDER TO INVALIDATE

CACHED LOCATIONS. THIS REQUIRES
THAT MEMORY BE LOCATED ELECTRICALLY CLOSE TO THE CACHE.

GO
T0

DOES

THIS REGISTER

CONTAIN 77

CACHE APPEARS TO
B8E WORKINGRUN CACHE

DIAGNOSTICS
MA-2281

Figure 3-1

Troubleshooting Flowchart

(Sheet 4 of 5)

3-6

SHEET 4

LOAD ADDRESS OF
THE CACHE CONTROL
REGISTER

ADDR=777746

EXAMINE CCR BI!TS

LOAD ADDRESS OF
THE CACHE MEMORY

HIGH (BIT3) OR

ERROR REG

FORCE MISS LOW

ADDR=777744

(BIT2) SET

EXAMINE CMER BITS

ARE

THE PARITY

BIT 18

BITS SET IN THE

BIT
THE ONLY
IN THE
SET

CMER

TT T
T

CMER

CHECK FOR A

INITIALIZE
CPU

PARITY ERROR
IN BACKING
STORE {(MAIN

MEMORY

oio "

THE CME

RUN CACHE

DIAGNOSTICS

BITS CLEAR

CFKKAA

RUN CACHE

RUN DECX11

[*—

MA-2280

Troubleshooting Fiowchart
(Sheet 5 of 5)

Figure 3-1

3-7

SEE VIEW A
+15V JUMPER

DD11-P

-15V JUMPER

+5V JUMPER

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PIN AO1A1

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NOTES

1. JUMPERS SHOWN ARE

@
oLTC

©_

-16TO -15B

+15 TO +15B

+5TO +6B

2. USE #20 INSULATED
BUS WIRE FOR JUMPERS

A
VIEW
11.5343

Figure 3-2

Backplane Jumpers

3-8

~—r

KK11-A CACHE MEMORY USER’S GUIDE

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