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EK-DZV11-TM-001

June 1978

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Document:	DZV11 Asynchronous Multiplexer Technical Manual
Order Number:	EK-DZV11-TM
Revision:	001
Pages:	137
Original Filename:	EK-DZV11-TM-001_Jun78.pdf

OCR Text

EK-DZV11-TM-001

DZV11 asynchronous
multiplexer

technical manual

digital equipment corporation - maynard, massachusetts

Ist Edition, June 1978

Copyright © 1978 by Digital Equipment Corporation
The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL
DEC
PDP
DECUS
UNIBUS

DECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX

VMS

MASSBUS
OMNIBUS
0S/8
RSTS
RSX
IAS

CONTENTS

Page

CHAPTER 1

GENERAL DESCRIPTION

1.1

1.34

INTRODUCGTION ......ooiiiitiieeeecreee
s eeiree et sresre s e e s ssetesesssesese s s s ssaass e s ssananeasns 1-1
PHYSICAL DESCRIPTION ...ttt
ennre e 1-1
DZV11 ConfigUrations.........cccueeereeeerierernierisiniiessisessonseeeinseessnsnessssseeeessens 1-1
BC11U Interface Cable...........cccovmiiiiiiiiiiiicciiiniiiiinecnne
s 1-4
TSt CONMECLOTS «.vvetieeriereeieeiaeeeieeeeererreenteeeteeeereeeeennsrabisssbsasssssssiesssessasssns 1-5
SPECIFICATIONS ...ttt
ettt eeese e ssssseettt s e s se s s es s bbb b bn st e e e s e e e ensans 1-5
ENVIronmeENtal .......oovvvviirmemiiiiieciieeieeesraeeeeeeeeeeeseeeseeetsesteesssanssrsssiassiaraaranes 1-5
EIECEIICAL.....uviiiieiiiiiiieeeciciitiitee
eee e e es e s
eeeeesesee e st s bbanaes s es e e s e es s s annnnnns 1-5
PEIfOTMAICE. ......cevvevrirnerinrirerinriaaeaeaeaeeeaeaeeraerereeseriastesstarstsrsssssssrsssarsssennn 1-5
Maximum Configurations ...........cccceeeereereerrriiiniierenieeennenie 1-5
TRIOUGNPUL.....eveiiiiiiiiiee ittt
e 1-7
RECEIVETS ....cooiveiiieiireeeeiirieeeinerreenrannsseeanaenneneesarsssatsssasesassessssensiessmnnnennses 1-7
T AN uuueueititeiceeeresereeerereeeeeeeeeeeeeeeneeenresttessrtesssresrassssrssssstsarssansens 1-7
Baud Rate Generator .........uuueiieiieriiereiiereireerreeeseesiseseeseserseneessiensenmnnenee 1-7
Performance SUMMATY .......ccoooeiieiiriiieeeeerceninieensnriisre
s snsnnnnes 1-7
0113
1] o1 £ PSP
PP PPROPPN 1-7

CHAPTER 2

INSTALLATION

2.1

232

SCOPE ..ottt
e e e e e e e e e e i vebeseeaaeseesaseessassrattatttesessos sttt b bsareeeeeeenes2-1
UNPACKING AND INSPECTION ......cccveiiiiiiieiiiceeeeiriiiiees e 2-1
INSTALLATION PROCEDURE..........cccvviiiiiiiiieicieetininiiiee e 2-1
Jumper Configuration .........ccccccviiiiiiirniniiiciii
e 2-1
Device OPeration .........cc.ccceeieiiiiiiiiiiiiiiiiee
et
sibae e 2-1
Modem Control JUMPETS.........ccciieeiiiiiiiiiiiiniiriiiiiie
e snesniniiesseeseseene 23
Module Installation........cccoveeiiiriiieireeiiieiir
e 2-3

CHAPTER 3

DEVICE REGISTERS

1.2
1.2.1
N~

1.2.2

1.2.3
1.3
1.3.1

1.3.2
1.3.3

1.3.3.1

1.33.2
1.3.33
1.3.34

1.3.35
1.3.3.6

2.2
N

231

23.1.1
23.1.2

3.1

32
3.2.1

322
323
324

325
3.2.6

sssessssbaabbbreesaeeeneensasans 3-1
tt
et e tereteeeeaessssessssssbasaeseaee
.t
e eeeeee
SCOPE ..
DEVICE REGISTERS ...ttt
ecieete e sreee e ssnne s seaiss e s ssnbes s e e ennnes3-1
2 |
Control and Status Register..........ccccoeeevicenninnn. U UUURRUUUUUUPPTPTRRORRRRPP
Receiver BUfer..........ooiiiviiiiieieeeeer ettt 3-1
e3-5
Line Parameters ReGiSter.........ccccceeeriiiiiiiiinniieeiiiiiiiiiiiine
e 3-5
iiiiiieeieee
eeeviiiiiiiiiiiiminni
Register............c
Control
Transmitter
3-7
e
iiieiciee
Modem Status REGISter .......coceeieiiieriiieiiic
iiiiiie 3-8
e
Transmit Data RegiSter ......coooviiiiiiiimreiiiiiiiirncc

CONTENTS (Cont)

Page

CHAPTER 4
4.1
4.2
4.3

44
44.1

44.2
443
444
44.5

44.6
44.7
448

PROGRAMMING

SCOPE ..ottt eeeebe e e e e e e e e e e s s baar e s s ssaseesesasant s e s sasbtesessbns s e s s s snbse e s antsanans 4-1
DEVICE ADDRESS ASSIGNMENTS.......ccooiiiiiiiiiiiiee e 4-1
INTERRUPT VECTOR ADDRESS ASSIGNMENTS ......cooviiiiiiiiiniiinen. 4-1
PROGRAMMING FEATURES .......ccooiiieiiiiireicceein ettt 4-2
nss
s §"2
BAUA RALE ....covveieiieeeciecereceeecteeeteeeeaeessenesssessseesveesseeeseesnanesnessanesnneo
Character Length ........ccoocceieiiiiiiiiiiiiiiiiie et 4-2
ieeieeeit 4-3
ceieiiiiie
ettt
SEOP BitS...cc
SPR PP4-3
|0§1520U ORI
IPON4-3
OO
OO
¢ g 101 £
|0110
e 4-4
Emptying the Silo.....cccecerviiniiniiiiiiic
e, 4-4
Transmitting 2 Character.........ccccccererininiiiiniiiiiiiiiie
Data Set COoNtrol..cccviivviiieeieeeieccereeeeeeeeeeecereecsstes ettt 4-5

CHAPTER 5

TECHNICAL DESCRIPTION

5.1

GENERAL.......ooiiiicteeecteeeeeette
e e seete e esssaessessenarres s sesnssse s s sanbbas s s abnee s essrbaeaans 5-1
INTERFACE FUNCTIONS......cooiiiitrreceeeireenennrntes
s
snaee s sesnesessnnns5-1
LSI-11 to DZ 11 INterface......ceeeeiieceiiiiieeeeeeesrerenrccee
e eenananes5-1
DZV11 to Data Set INnterface .........ccovvveeenniierenviieiiininiieciic
e 5-8
CIRCUIT FUNCTIONS ... ceeiietteienreessenrtessesssiseeeesenaasssssssnssesssasnesssonnnns 5-11
CIRCUIT OPERATION ........ottiiiicirceniieeeeceeeeessinite
e ssnan s esaras s s enansseseanens5-13
BUS INEEITACE .....vveeeeeiiiieeeeciite
et ceeerce et e e rere s e s bt e sana e s e ans e 5-13
I/O CONLIOL.....iiiiiiiiiiiiieiie
et 5-15
INPUt OPETation........covvieiriiiiiiiiiiintirieiii
et e et
sbe e seee e5-16
OULPUL OPETALION .....cooureenriiiiiriiitiiitesii
et
eebe et bs e eraeeneeas 5-17
Vector OPEration.......cc.cccuvuiiiiiieiiniiiiiiineriniee
et s s s e sas s 5-18
INitialize CIrCUIL...eeeeeecieieeiieiieererecree
et et ee et 5-18
INtErruPt LOZIC....coeeiiiiieiiiiieiiiiiiiii ittt 5-19
Interrupt TransactionsS..........ccccoveiveeiiiiineieeiniiiie
i, 5-19
EIA RECEIVETS...cceieiiiieeiiieneeeeeeeriesiisisitiecteeesieeairasesieesesssessssassnasssessessssnnsns 5-21
EIA TransSmitterS.......uccueiuumervmeeemeeereeemteeeeeesieeriessreersressississiissiisiisrmsse 5-22
UARTS ceovviiiiiiiie e ceieteseetreeeeettee s sssaaaes s e saseeessensbeeessansraeseessanaersasanenessses 5-22
Setting Line Parameters...........ccccovviivniniiinniiciinniinnnnneeieeeitesesnnee
e 5-22
UART Receiver Operation.........ccccceeeeeurreriniiniieiinnineccnsnneeseenssneeeen 5-23

5.2
5.2.1

5.2.2
5.3
54

54.1

542
54.2.1
5422
5423
5424

543
54.3.1
544

5.4.5
54.6

5.4.6.1
54.6.2
5.4.6.3
5.4.7
54.8
549

549.1

549.2
5.4.10
54.11
54.12
5.5

~—

UART Transmitter Operation...........cooveevcmreiriieeiiiniinninniceceeinnninnnne. 5-24
Break (BRK) Bits .......cccciiiiiiiiiiinticiiiiieiiiccie
et
ceanareae e 5-25
Speed and Format Control ..........cccoviiiiniiiiniiiiiieiiiecie e 5-25
RECEIVET CONLIOL .....uviiiiiiiieecciieee
et ceee e st e e s st e
sanes5-27
RECEIVET SCANMET .....uviiiiieeiireciiieneeereeereennrereeeereeseessssisretteseseesssnnanaes 5-27
SHIO BUTET ..vvvvviiieeeeeecittre ettt
e e s s e snbseeaece s e e s snen 5-28
Transmitter CONLIOL ......evvvviiieiiiiiiieiieeeeiereceetee
e erree et e recte st e ressesesaessssseanns5-30
Maintenance Mode.............oeemiemmiimmiemmeimniiisiessiesiies 5-33
POWET SUPPIIES ...eeeieiiiiieeieiieeeeeiiee ettt saae e s sann e e 5-33
SUMMARY OF DEVICE REGISTERS ...ttt
eeneee e 5-33
iv

~—

CONTENTS (Cont)

Page

CHAPTER 6

MAINTENANCE

6.1

SCOPE ...ttt eertee e s esbt e e s srare e e s ssstbae e s sesaeesessssaaas s e sssbbabe e s e s sabb e e e s enaae 6-1

6.2

PREVENTIVE MAINTENANCE ........ccoveiiiriieiincertenininticenincc
e nsnae e6-1

6.3

CORRECTIVE MAINTENANCE ..........otiiiiierienccnecesseeieee
s sereeecessseeeceens 6-1
GENETAL ..ottt eeeee e e et e e e s saet e eesesssraeesesesnsnneessssansnesssonarasessssnraes 6-1
Tools, Test Equipment, and Troubleshooting Aids........c..cccovviivniiinnnnnnnnnen. 6-1
DEC/X11 Exerciser Program...........ccccocueeviiniinreiniineeniieninesiesessneieenennes 6-2
XXDP Diagnostic PrOZIamS .........ccoverimeteeiennnereriecsiieteissiiaiessinsneessssnneenes 6-2
(€11
-1
O
ORI 6-2

6.3.1

6.3.2

6.3.3
6.34

6.34.1
6.3.4.2
6.3.4.3
6344
6.3.4.5

6.3.4.6
6.34.7
6.3.5

6.3.5.1
6.3.5.2
6.3.5.3

6.354

6.3.6

Maintenance MOAES........ccunriiiieriieieiieeeccceeeererrecscree
et e6-3
Setup Proceaures........cccoeccueeeiiiiieeiiiniiiieieiieee et 6-3
Software Switch RegiSter.....cccccummririiieeireiiiiiiiiiiieie
i 6-3
AULO-SIZINZ .....uiiiiiiiiiiiiiieeerrrrer i ireee e rreete s sssbrre s srate s saaanae s s e anraes 6-5
Parameter Inputs and Dialogue ...........ccccceinviirinnniiiniiininiiniicn, 6-5
Functional DesCription.........cccccvviiriiiiiniieinnniireeeenniieeenecinneesssneeesens 6-8
Interprocessor Test (ITEP) .........cooviiiiiiiiimiiiiiiiiiicinnitincccreccccnee, 6-11
Starting ITEP .......ooooiiiceieeiretcceeeeee et 6-12
Console DIialogUe ......ccccovreueeeeiieiiieiiiiiiiiiiieirecer e 6-12
Operational Switch Settings.........cccoovviiiiniiiiiiiiinniiiiici
e,6-14
TESEINE .oeeeeeiiiiieieieiirce ettt et ee et e s eaan bt
e e aa e e e e 6-15
ManUal TeStS...ccciiiiiiiiieiet
e
e e s s aseet et s e ses s bbb
e e e 6-15

APPENDIX A

IC DESCRIPTIONS

GENERAL......oooititiieectier
e ertre st e s e st e e eaessssas s e s st asssaatesosnan s s bt sesnbaeses A-1
UART ottt et e s sttt s e e s sa s e s sse e s aee e s se e s sbabaess bt besaantessaneeeeassesasasens A-1
DCOO3 INTERRUPT CHIP ........uoviiiiiiiiiieienenecereressesenines
s snnansseessssnanesssnnee A-8
DC004 PROTOCOL CHIP......ouoeiiierieeiicrrine
et ecciinrcc e nnnicce s eensees A-12
DCO005 BUS TRANSCEIVER CHIP ........ooviiiiiiiriiniccireccnineece e A-17
COM 5016 DUAL BAUD RATE GENERATOR ........ccccccvriviiiniiiiiiiniiienns A-22
3341 FIFO SERIAL MEMORY ...ttt
sireee s iine s ssnaees A-22

APPENDIX B

CONNECTOR PINNING

APPENDIX C

GLOSSARY

A2
A3
A4
AS
A.6

FIGURES

Figure No.

Title

Page

DZV11-A (M7957 MOQUIE)....c.cocirriiiiciniiiiniccieeneniennenesesesneeresseneeee
s snenesssensnnens 1-2
DZV11 System APPLCALIONS .......eueviriieeieiiirriiiererreeeeniesesrieretsesseees
s saarssseeees 1-3

FIGURES (Cont)

Figure No.

OO0
) N

@ o @ o MMMWR\)NN—'—‘

— W=
&
E-N WN—

1-3

5-10
5-11

5-12

5-13
5-14
5-15

5-16
5-17
5-18
5-19
5-20
5-21

5-22
5-23

5-24
5-25
5-26

5-27
5-28
5-29

5-30
5-31

5-32
5-33

5-34
6-1

6-2

Title

Page

DZV11-B (M7957 Module, H325 and H329 Connectors and

Cable Assembly BCI1U-25) .....oiiiimiiiiiiiiiiie it 1-4
Test Connectors H325and H329 ...ttt 1-5
e 1-6
Loopback CONNECLIONS .......covirieriirrietiitieieie st
2-2
tt
it
n
......coiviiiitiiiii
LOCAtIONS
Jumper
M7957
2-4
e
i
essee
e
s
se
e
e
e
s
s
e
e
e
e
e
e
s
e
iineiin
e
e
e
i
rrriire
...vvvv
M 7957 AdATess SEIECLION
2-4
essaenes
sssses
esseaaaeaaanaasaarenaaaa
e
s
s
nneeriisiss
M 7957 VeCtOr SELECHION. ....uuuiirerirenriiren
Register Bit ASSIZNMENTS.......ccoiiiiiiiiiiiieiinie e 3-2
Labeling CONVENTIONS ......coocveiiiiiiiiiinieinitiniinstes et 5-1
LSI-11/DZVI1INterface......ccovviviieiininiiiniiiicnccii 5-2
Interrupt Request/Acknowledge Sequence...........ooccevieeniiiiniinniiiiii 5-4

DATIBUS CYCIE...ooiiiieieeeiiee ettt 5-5
DATO or DATOB BUS CYCIE.......oieiiiiiiiiiieiiiiiiiieiece e 5-6
e 5-7
DATIO or DATIOB BUS CYCle ....coviiiiiiiiiiiiiiiiiiiiiitir
eee 5-9
iiiiiniiiiiccc
..cccooviiiiii
Modem........c
Local
by
Established
Channel
5-10
iiiiies
oviiiiiiiiiii
..........ccc
Modem
Channel Established by Remote
5-11
rrereeeceene
iiniierireereesrretrre
Interface with Bell Data Station..........oooveiieiiieiiiiiniiiiiinmi
Simplified Functional Block Diagram..........ccociviiiiiniiniininiii, 5-12
Bus Interface, I/O Control and Interrupt LOZIC.......coceniniiiinininiiiniininis 5-14
s 5-16
Data Input TImMiNg ....cccceoiiiiiiiiiiiiie
tt 5-17
it
eiiieiiiiiinie
Data Qutput Timing......cccccee
e 5-18
Initialization SigNals.......c.ccoceveeiiiiiiiiiiiii
INErTUPL LOZIC. uiuiieiieiiiiiiiieiiiiii ettt 5-20
INtErrupt TIMINE ...oooveeriiiiiiiiiie et 5-21
EIA RECEIVETS .coeeiiiiiieiiieieeeieeeeieeieeeeeeeeeeeeeeeeeenteestetseetenttsreresesssaasarsanaranasbreaesaannee 5-21
EIA TTANSIITLETS «.oovvvvveiiiiieeieeereeererrrerereaeeeeeeeesreestessesestmansinnernsrsssrsssrsnsssssrissraasns 5-22
R TS oottt ettt ee e e e e ee e atbateeeessaes e ababs s e e e e sas e s e nnaanbsseaaesesssaseabaeeas 5-23
UA
UART and Break Bit RegiSters.........ccccvviviiiiiiiiiiiiniiniieinnecnccninens 5-24
s 5-26
Speed and Format Control ..........ooivviiiiiiiiiini
e s e s s s s s s s e aan e s s ee s e e as 5-27
s s s s se s e aecere
RECEIVET CONITOL . uinieiiiii
UURO PP PPPPPOIPPPRE5-29
(=, cOU TP
1(o310T
tas 5-31
rsaseesaasassssnssns
eenreennriesissr
i
TransSmitter CONEIOL .....uvuuveveerereeiiirrrnnieiei
e 5-32
sae
Transmitter TIMINE .....cccecoiierieriieeeeniiiii it
Maintenance MOdE ....ooooeeiiiiiiieniiieieee e 5-34
s 5-35
POWET SUPPIES ....civiiiieeiieeeiieei ittt
5-35
e
iimiiiiiiiiiiiiiiie
SChemMe........cccoci
Labeling
Bit
5-36
eie
e
iiiiiiiiiiiiri
..cooiiiiiiiii
Control and Status RegiSter......
5-37
Receiver Buffer ReEIStEr ....c.uiveeureericieeiciiiiiicinii e
Line Parameter ReISter ......cccuveiiiiiiiiiiiiiiiiiiiiiinic s 5-38
iiii 5-39
e
Transmit Control REQISter..........cccvviiiiiiiiiiiii
5-40
e
iiiiiiieee
.....oeeeiiiiriiiiiiiiii
REZIStEr
Status
Modem
5-41
s
iiiiei
........ccovueiiiiiiiiiiii
Transmit Data ReZISter
6-4
e,
Maintenance Mode Data FIoW......cocooviiiiiiiiiiiciiiiiiiii
Interprocessor Test (ITEP) ... 6-5
vi

FIGURES (Cont)

Figure No.
A-1
A-2
A-3
A-4
A-5

A-6
A-7

Title

Page

Format of Typical Serial Character .........c..cccevvvviiviiiriiniiiennieeiniie
e A-1
UART TTaANSIEEET ....uvveieieiieeeeeeeeeereenieeraeesieeeeeeeseteseeeesrtsnessesstesssesssersssessansanannns A-2
UART RECEIVET ......veiiiiiiiireceeieeercrerrecesee
e s sssnsber st s st e e s s s e asbaanbena s s e s e enenA-6
UART Chip Pin Designations..........ccccoveuvuieiiiiniiieiiinnninesinnnieesesneesssesinsesans A-7
DCO003 Logic SYMbOL ....cc.eeeiiiiiiieciiiiiiiiiiir ittt A-8
DCO003 A Section TiminE......cccieeeereariierieeereeericeretetietttrceetrrerrrestsessiessisesasrsassaaenes A9
DC003 A and B Section TimMing........ccceeiieiriiiiiereeeeeniennienieeinieeerrenne
s sssnnnnnesA-10
DC004 Simplified Logic Diagram.........ccccccvvniiiinuiiininireeninieenieienieeesee
s A-13
DCO004 Timing DAagrami........cccccceeiiieiriiniiniiiienerreiiieiiieiinissiseseesseseseesssssssnnnes A-15
DC004 Loading Configuration ............cccoevueiriiiiinineiinnnnieninnennienennesesnee
e A-16
DC005 Simplified Logic Diagram.........c..occeevvviiinnnriinniiiiiiiiiieecniene, A-20
DCO005 Timing Diagram ..........ccccereeeiiiiieriininiiiinniene
et eiinere s innessesnnesA-21
COM 5016 Simplified Block Diagram..........cccccevviiiiinmieininiiinniecnecnneseae. A-22
COM 5016 Pin LOCAtIONS ......cuunrirriireiereeieinnititeeetettieecssssnssstrneeeeessssssssnnns A-23
3341 FIFO Serial MemMOTY.....cccouiiiiiiiciinerieeeeeneccsiinnnneettteeeeesessssssnssssssneeesseens A-25
COMMECIOTS 1.eeeieiieeereeerereeirereerereeeeeererteeeeeseresarerereenstaasssesssssssebsssssssssaanssisssssssssnnes B-1

TABLES

Table No.

Title

Page

Items Supplied per Configuration..........cccoccevvvviiiiniriciiiniiiiii
e,2-1
Jumper Configuration ..........ccevveiiiiiiiiiiieiiie
s 2-3
M7957 Vector Address Switch Selection ........ccccevevveiiiinciciiciine
e 24
Vector SWitch Selection .........uviiiireiireiieiiiieiiicice i 2-5
DZV11 Register Address ASSIgNMENtS ........cccceeeeeieiiniiiiiiinmeeeiniiien 3-1

5-4

CSR Bit ASSIZNMENLS .......euviieireieerieiiriiiettieitieeniieciirestirresese
e sssasnnssressessenns 33
RBUF Bit ASSIZNMENTS ....cccceiuneeniiiieeriiiiiiiiittteteeenen
e ssenssinssssseseee s sssssnsseeaesees 3-5
LPR Bit ASSIZNMENTS ....ccceeiiiriiirireinniirieirriiiiiiiirrriieeecintests
s sissiassssereeeesessesssnnsnes 3-6
Baud Rate Selection Chart ..........ccceeeeeeiiiiiiniiiiiiiiicnincc
i 4-2
LSI-11/DZV11 Interface Signals...........ccccoovmiiviiiniinniiiniiieecseie
s5-2
Modem Control Signals ...........cccoveeeeiiiiiiiiiiiiiiiii 5-8
Multiplexer Addressing ..........cccccevviiivimmiiiiiiiiiiiiii
e 5-15
Transceiver SWItChING.........ooveeeeiiimiiiiiiiiiiiiireier
e 5-15
Byte Selection (Output Operations Only).........cccceoviiiiiiiiniciiinniiii
e, 5-18
Diagnostic PrOGIamS. .....ccuueiiiiiiieiiiiiiiiiiniiniit
sttt ssiee s sisse e ssbaae s s beee s 6-2
Multimedia ASSIZNMENTS.......ccuuuuriereieereiiiiieette
e 6-3
Typical Map of DZVI11 Status......ccccccovvviiiiiiiiniiciiiiciiieii e 6-6
DV ZA TEStS...oovereiiiiieiiiniiiniereniiennesrueeeseesesesaaasasaessessaesseressressrrestieseesneee 6-8
DVDZB TESS ..ovuvuieiiiiiitiiieieeerttranseeaaeeerertaanaseteerenesnnne
e eeermsesiasessssssssaarsosssenses 6-10

vii

TABLES (Cont)

Table No.

Title

Page

6-6

Valid Mode COMDbINAtIONS ........cccevevieirerniueireriinienininineensseeessessseeessseseessssssnenes 6-12

6-7

A-1

Meaning of Parameter NO. L.........c.cooiiiiiiiiiiieiiiecieeeceeccccreeeeeecreee
e enae e v e e6-13
Parameter NO. 1 EXaMPIES ......cccvrviuiiiiiiiiiiiecrcittenecinneessesiseeeeesiveeesesneseeesennseenns 6-13
Operational SWitCh Settings............cccveeeeiiiiiiiiiiiieeeir
e
e carre e e e e eeanees6-14
UART Signal FUNCLIONS......cccccitiiiiiiiieiiciiteececietecsesiieeesesirsaeesesnaeeeseesneessensnnns A-3

A-2

DCO03 SiZNAlS.....cccocoiiiiierie

A-3

DC004 Signal Timing versus Qutput Loading.........cccoccvveeiivercccvvenvinrenneennreennenne A-14

6-8

6-9

A-4

ettt e

srreeee e ssseraeeee e e s e e s s e e b e e e e e e ae e e nnnene A-11

DC004 Pin/Signal Descriptions.........cccceeiieerecieereienesieensneesseressiesessseessneseenens A-16
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viii

~—7

CHAPTER 1

[

GENERAL DESCRIPTION

1.1 INTRODUCTION
The DZV11, shownin Figure 1-1, is an asynchronous multiplexer that provides an mterface between
an LSI-11 processor and four asynchronous serial data communication channels. It can be used with
the LSI-11 processor in a variety of applications that include data concentration, real-time processing,
and cluster controlling. The DZV11 provides an EIA RS232C interface and enough data set control to
permit dial-up (auto-answer) operation with modems capable of full-duplex operation,* such as the
Bell models 103, 113, 212, or equivalent. Remote operation over private lines for full-duplex point-topoint or full-duplex multipoint as a control (master) station is also possible. Figure 1-2 depicts several
of the possible applications for the DZV11 in an LSI-11 system.

The DZV11 has several features that provide flexible control of parameters such as baud rate, character length, number of stop bits for each line, odd or even parity for each line, and transmitter-receiver
interrupts. Additional features include limited data set control, zero receiver baud rate, break generation and detection, silo buffering of received data, and line turnaround.

Program compatibilityis maintained with the Unibus option DZ11-A. The only compatibility exception is the number of serial channels supported. The DZV11 does not support 20 mA operation.

1.2

PHYSICAL DESCRIPTION

The DZV11 comprises a single quad size module, 21.6 X 26.5 cm (8.51 X 10.44 inches), which is
designated as the M7957 module. All input and output leads are available on a Berg header. The
DZV11 connects to the LSI-11 QBus by the H9270 mounting panel or equivalent. All QBus input/output signals enter and leave the module via the mounting panel pins.

1.2.1

DZV11 Configurations

The DZV11 can be supplied in two configurations. The DZV11-A, as shown in Figure 1-1, consists of
the M7957 module only. Cabling assemblies for connection to terminals and modem channels are not
supplied with the DZV11-A, but are available in the DZV11-B. The DZV11-B consists of an M7957
module, BC11U-25 cable assembly, and two accessory test connectors, H329 and H325. This configuration is shown in Figure 1-3.

*The DZV11 data set control does not support half-duplex operations or the secondary transmit and receive
operations available with some modems such as the Bell 202, etc.

1-1

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1-3

M7957 MODULE

CABLE ASSEMBLY
BC11U-25

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By

(%I’lh"‘\»
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TEST CONNECTOR H325
MK-0179

TEST CONNECTOR H329

Figure 1-3 DZVI11-B (M7957 Module, H325 and H329
Connectors and Cable Assembly BC11U-25)

1.2.2

BC11U Interface Cable

The interfacing cable for terminal and modem connections to the DZV11-B is provided by the BC11U
cable assembly (Figure 1-3). It consists of four separate cables, 762 cm (25) in length, each terminated
by a separate EIA-type connector housing and a common Berg housing. Each cable within the assembly provides nine input/output leads. The EIA connector pinning conforms to EIA standard RS232C
and CCITT* recommendation V.24. The leads supported by the DZV11-B are:
Circuit AA (CCITT 101)
Circuit AB(CCITT 102)
Circuit BA (CCITT 103)
Circuit BB (CCITT 104)
Circuit CD (CCITT 108.2)
Circuit CE (CCITT 125)
Circuit CF (CCITT 109)

Pin 1
Pin 7
Pin 2
Pin 3
Pin 20
Pin 22
Pin 8

Protective Ground
Signal Ground
Transmitted Data
Received Data
Data Terminal Ready
Ring Indicator
Carrier
NOTE

Signal ground and protective ground are connected
together.

*CCITT _ The Consultive Committee International Telegraph and Telephone is an advisory committee established under the United Nations to recommend worldwide standards.

1-4

1.2.3 Test Connectors
Figure 1-4 shows the two accessory test connectors, H329 and H325, that are provided with each
DZV11-B. The H325 plugs into an EIA connector on the BC11U to loopback data and modem signals

onto a single line. The H329 plugs into the M7957 module socket housing and provides staggered
loopback of the data and modem lines. The loopback connections are shown in Figure 1-5.
1.3

SPECIFICATIONS

Environmental, electrical, and performance specifications for the DZV11 are discussed in the follow-

ing paragraphs.
1.3.1

Environmental

The DZV11 operates in an environment from 5° to 50° C (41° to 122° F) and in a relative humidity of
10 to 95 percent.
1.3.2 Electrical
Power Consumption

1.15A@ +5Vdc
039A@ +12Vdc

For each line, the DZV11 provides a voltage level interface whose levels and connections conform to
EIA standard RS232C and CCITT recommendation V.24. The leads supported by the DZV11 are
listed in Paragraph 1.2.2. Each DZV11 meets the LSI-11 QBus interface specification and represents
one unit load as an interface.
1.3.3
Performance
The following paragraphs describe the DZV11 performance capabilities and restrictions.
1.3.3.1

Maximum Configurations - The DZV11 multiplexer is assigned a device address in the float-

ing address space. The floating address space starts at 760010 and extends to 764000.

A maximum
configuration of DZV11s is not limited by floating address space, but is limited by the rules governing
an intermediate size system configuration. Therefore, a maximum of seven DZV11 multiplexers may
reside in a 9 X 4 backplane.

H325

M-8z

Figure 1-4

Test Connectors H325 and H329

H329

w0160

H329 STAGGERED TURNAROUND
TRANSMITO

— RECEIVE 1

DTRO

# RING 1

1
— CARRIER

RING 0 @#—

CARRIER
O @—

DTR 1

RECEIVE O @«—

TRANSMIT 1

NOTE:

LINE 2&3 ARE STAGGERED IN THE SAME WAY.

H325 LOOPBACK CONNECTIONS

SCE -fi-—’
scr 15

scr —
1
SEC XMIT —»

SECRCV

XMIT DATA —2—=——>

RCV DATA - R—
4

REQ TO SEND —

CLR TO SEND
CARRIER
14
NEW SYNC ———
DATA SET RDY

DTR

RING

—O UMPER

0 REMOVED

22
MA-0561

Figure 1-5

Loopback Connections

1-6

1.3.3.2 Throughput - Each DZV11 is capable of a throughput rate of 10,970 characters per second.
This rate is calculated as follows:
(Bits/second X no. lines X direction) divided by bits/character.
(9600 X 4 X 2) 1/7 equals 10,970 characters/second.
For a character service routine of 100 us or less, the device throughput rate can be sustained.
1.3.3.3 Receivers - The receivers provide serial- to-parallel conversian of 5-, 6-, 7-, or 8-level code
with one start space and at least one stop mark. The character length, number of stop bits, parity
generation, and operating speed are programmable parameters for each line. A receiver and transmitter of a corresponding line share the same operating speed with provisions for enabling/disabling
of that receive line.
Each receiver is double-buffered and has an allowable input distortion of 43.75 percent on any bit.
Also, the accumulated character distortion must not exceed 43.75 percent. Break detection is provided
on each receiver.
1.3.3.4 Transmitters - The transmitters provide parallel-to-serial conversion of 5-, 6-, 7- or, 8-level
code with or without parity. The parity sense, when selected, can be either odd or even. The stop code
can be either 1 or 2 units except when 5-level code is selected. When S-level code is selected, the stop
code can be set to 1 or 1.5 units. The character length, number of stop units, parity generation and
sense, and operating speed are programmable parameters for each line. The operating speed for the
transmitter is common with the receiver. Breaks are capable of being transmitted on any line. The
gross start-stop distortion for a transmitter’s TTL output is less than 2.5 percent for an 8-bit character.
1.3.3.5 Baud Rate Generator - The baud rate generator is a MOS/LSI device which provides the
DZV 11 multiplexer with full programmable capability for operating speed selection. Each line has an
independent generator capable of producing 1 of 15 selectable baud rates. Speed tolerance for all rates
is less 0.3 percent with a clock duty of 50 percent + 5 percent. (Sec below for rates.)

1.3.3.6 Performance Summary - The following summarizes the programmable features offered for
each line.

1.3.4

Character length

5-, 6-, 7-, or 8-level code

Number of stop bits

{ or 2 for 6-, 7-, or 8-level code
1 or 1.5 for 5-level code

Parity

0Odd, even or none

Baud rates

50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400, 3600,
4800, 7200, and 9600

Breaks

Can be generated and detected on each line.

Interrupts

The following interrupts are available on the DZV11.
Receiver Done Interrupt
The Receiver Done interrupt occurs every time a character appears at the output of the receiver buffer

Silo Alarm Interrupt

The Silo Alarm interrupt occurs after 16 entries have been made into the receive buffer register by the
scanner. This interrupt disables the Receiver Done interrupt and is rearmed when the receive buffer
register has been read.

Transmit Interrupt

The Transmit interrupt occurs every time the scanner finds a UART buffer empty condition, and the
transmitter control register bit is set for that line. It can be enabled or disabled from the bus.

1-8

CHAPTER 2
INSTALLATION

2.1

SCOPE

This chapter contains the procedures for the unpacking, installation, and initial checkout of the
DZV11 Asynchronous Multiplexer.
2.2

UNPACKING AND INSPECTION

The DZV11

is packaged in accordance with commercial packaging practices. First, remove all packing

material and check the equipment against the shipping list. (Table 2-1 contains a list of supplied items
per configuration.) Report damage or shortages to the shipper immediately and notify the DIGITAL
representative. Inspect all parts and carefully inspect the module for cracks, loose components, and

separations in the etched paths.

Table 2-1

M7957 module

HAXAX | W

> X

Description

> X

Quantity

Items Supplied per Configuration

BC11U-25 cable assembly

H329 test connector
H325 test connector
Print set (B-TC-DZV11-0-1)

DZVI11-A and -B
1
1

Order number MP00462
Software kit ZJ251-RB
DZV1I User's Guide

(EK-DZV11-UG)

2.3 INSTALLATION PROCEDURE
The following paragraphs describe the installation of the DZV11 option in an LSI-11 system.

2.3.1 Jumper Configuration
There are 16 machine-insertable jumpers on the M7957 module (Figure 2-1).
2.3.1.1

Device Operation — Jumpers W10 and W11 must be installed only when the module is used on
an H9270 backplane, or one that applies LSI-11 bus signals to the C and D sections of the module.

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*NOTES:

JUMPERS W9, W12, W13, W14, W15 AND W16 ARE REMOVED ONLY FOR MANUFACTHEY SHOULD NOT BE RENMOVED IN THE FIELD.
TURING TESTS.

JUMPERS W10 AND W11 MUST REMAIN INSTALLED WHEN THE MODULE IS USED IN
A BACKPLANE THAT SUPPLIES LSI-11 BUS SIGNALS TO THE C AND D CONNECTORS
WHEN THE MODULE IS USED IN A BACKOF THE DZV11 (SUCH AS THE H9270).
PLANE THAT INTERCONNECTS THE C AND D SECTIONS TO AN ADJACENT MODULE,
JUMPERS W10 AND W11

MUST BE

Figure 2-1

REMOVED.

MK-0064

M7957 Jumper Locations

2-2

2.3.1.2 Modem Control Jumpers — There are eight jumpers used for modem control. The jumpers
labeled W1 through W4 connect Data Terminal Ready (DTR) to Request To Send (RTS). This allows
the DZVI11 to assert both DTR and RTS if using a modem that requires control of RTS. These
jumpers must be installed to run the cable and external test diagnostic programs. The remaining four

jumpers, W5 through W8, connect the Forced Busy (FB) leads to the RTS leads. With these jumpers
installed, the assertion of an RTS lead places an ON or BUSY signal on the corresponding Forced
Busy lead. The Forced Busy jumpers (WS through W8) are normally cut out unless the modem requires them (Table 2-2).

Table 2-2

Jumper

Connection

Line

DTR to RTS

WS
W6

RTS to FB
RTSto FB

03
02

RTSto FB

w17

2.3.2

Jumper Configuration

RTS to FB

Module Installation

To install the M7957 module, perform the following.
1.

Refer to Paragraph 4.2 for descriptions of the address assignments. Set the switches at E30
so that the module responds to its assigned address. When a switch is closed (ON), a binary
1 is decoded. When a switch is open (OFF), a binary 0 is decoded. Note that the switch
labeled 1 corresponds to address bit 12, 2 corresponds to address bit 11, etc. ( Figure 2-2 and
Table 2-3).
Vector selection is accomplished by the 8-position switch at E2. Switch positions 7 and 8 are

not used. Switch position 6 corresponds to vector bit 3, 5 corresponds to vector bit 4, etc.
When a switch is closed (ON), a binary 1 is decoded. When a switch is open (OFF), a binary

0 is decoded (Figure 2-3 and Table 2-4).
If the module is part of the DZV11-A option, perform step 3. If it is a part of the DZV11-B
option, proceed to step 4 for testing.
a.

Insert the module in a quad QBus slot of the backplane.
CAUTION

Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides and changing switch settings inadvertently.

Run the DZV11 diagnostics, MAINDECs DVDZA and DVDZB, in internal mode to
verify operation. Refer to the listing for assistance. Run at least three passes without
error.

Proceed to step 8.

ADDRESS SELECTOR

~—

A12 A11 A10 AO9 AO8 AO7 AO06 AO5 AO4 AO3

10|

SWITCH
E30

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E30

Figure 2-2

M7957 Address Selection

Table 2-3

Address Switch Selection

Address

Al2

160000
160010

X
-

Switch

160020

160030
160040
160050

160060

160070
160100

163760 | 163770

X
-

| x

| -

Al0 | A9

All

NOTE:

X
X

—

X
—_

X = ON
- = OFF

VECTOR SELECTOR

NOT

VO8 VO7 V06 VO5 V04 VO3
ON

OFF

‘

USED
7

MA-0214

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Figure 2-3

M7957 Vector Selection

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340
350

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320
330

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V08

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Vector

Switch

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Vector Switch Selection

Table 2-4

Insert the H329 test connector in J1 with the letter side facing up. J1 is the cable connector at

the top of the M7957 module.

Insert the module in a quad QBus slot of the backplane.
CAUTION
Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides and changing switch settings inadvertently.

Run the DZV11 diagnostics, MAINDECs DVDZA and DVDZB, in the staggered mode to

verify module operation. Refer to the diagnostic listing for the correct procedure. Run at
least three passes without error.

Replace the H329 test connector with the Berg end of the BC11U cable assembly. Observe
the “This Side Up” wording on the assembly. Refer to D-UA-DZV11-0-0 for installation
help.

Connect the H325 test connector on the first line and run MAINDEC DVDZC. Select the
cable test portion of the diagnostic. Three passes are required without error. Repeat this step
for each line.

Run DEC/X11 system exerciser to verify the absence of QBus interference with other system devices.

The DZV11 is now ready for connection to external equipment. If the connection is to a

local terminal through the DZV11-B option, a null modem cable assembly must be used.
Use the BCO3M or BCO3P null modem cables for connection between the BC11U and the
terminal. The H312-A null modem unit may also be used in place of the null modem cables.
If connection is to a Bell 103 or equivalent modem, install the appropriate line of the BC11U
connector into the connector on the modem. A BCO5D cable may be required between the
BC11U and the modem. Refer to Paragraph 2.3.1.2, Modem Control Jumpers, for selection
of jumpers for modem options such as RTS and forced busy. All of the cables mentioned,
excluding the BC11U, must be ordered separately as they are not components of a standard
DZV11 shipment. When possible, run the diagnostic DVDZC in echo test mode to verify the
cable connections and the terminal equipment.

~—r

CHAPTER 3
DEVICE REGISTERS

3.1

SCOPE

This chapter provides a description of each DZV11 register, its format, and its bit functions.

3.2 DEVICE REGISTERS
The DZV11 contains six addressable registers. A comprehensive pictorial of these registers’ bit assignments is shown in Figure 3-1. Table 3-1 lists the registers and associated DZV11 addresses.
3.2.1

Control and Status Register

The control and status register (CSR) is a byte- and word-addressable register. All bits in the CSR are
cleared by an occurrence of BINIT or by setting device Master Clear (CSR 04). The format is shown in
Figure 3-1 and the bit assignments are listed in Table 3-2.

3.2.2 Receiver Buffer
The receiver buffer (RBUF) is a 16-bit read-only register that contains the received character at the
output of the FIFO buffer. A read of the register causes the character entry to be extracted from the
buffer and all other entries to bubble down to the lowest unoccupied location. Only the Valid Data bit
(RBUF 15) is cleared by BINIT or by setting device Master Clear (CSR 04). Bits 00-14 are not

affected. The bit assignments for the RBUF register are listed in Table 3-3.

Table 3-1

DZV11 Register Address Assignments

Mnemonic

Address

Control and Status Register
Receiver Buffer
Line Parameter Register
Transmitter Control Register
Modem Status Register
Transmit Data Register

CSR
RBUF
LPR
TCR
MSR
TDR

76XXX0
76XXX2
76XXX2
T6XXX4
76XXX6
76XXX6

XXX = Selected in accordance with floating device address scheme.

Program

Capability

Read/Write
Read Only
Write Only
Read/Write
Read Only
Write Only

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Table 3-2

" Bit

Title

00-02

Not used

Maintenance

CSR Bit Assignments

Function

This bit, when set, loops all the transmitter’s serial output leads

to the corresponding receiver’s serial input leads on a TTL
basis. While operating in maintenance mode, the EIA received
data leads are disabled. Normal operating mode is assumed
when this bit is cleared. This bit is read/write.

Master Clear

When written to a 1, this bit generates ‘‘initialize” within the

DZV11. A read-back of the CSR with this bit set indicates initialize in progress within the device. This bit is self-clearing. All
registers, silos, and UARTS are cleared with the following ex-

ceptions.
1.

Only bit 15 of the receiver buffer register (Valid Data)
is cleared; the remaining bits 00-14 are not.

The high byte of the transmitter control register is not

cleared by Master Clear.
3.

The modem status register is not cleared by Master
Clear.

Master Scan
Enable

This read/write bit must be set to permit the receiver and transmitter control sections to begin scanning. When cleared, Transmitter Ready (CSR 15) is inhibited from setting and the received
character buffers (silos) are cleared.

Receiver

This bit, when set, permits setting CSR 07 or CSR 13 to gener-

Interrupt
Enable

ate a receiver interrupt request. This bit is read/ write.

Receiver Done

This is a read-only bit that sets when a character appears at the
output of the first-in/first out (FIFO) buffer. To operate in interrupt per character mode, CSR 06 must be set and CSR 12
must be cleared. With CSR 06 and CSR 12 cleared, character
flag mode is indicated. Receiver Done clears when the receiver
buffer register (RBUF) is read or when Master Scan Enable
(CSR 05) is cleared. If the FIFO buffer contains an additional
character, the Receiver Done flag stays cleared a minimum of 1
us before presenting that character.

08-09

Transmitter Line
Number

These read-only bits indicate the line number whose transmit
buffer requires servicing. These bits are valid only when Transmitter Ready (CSR 15) is set and are cleared when Master Scan
Enable is cleared. Bit 08 is the least significant bit.

10-11

Not used

Table 3-2

CSR Bit Assignments (Cont)

Bit

Title

Function

Silo Enable
Alarm

This is a read/write bit. When set, it enables the Silo Alarm
counter to keep count of the number of characters stored in the
FIFO buffer. The counter is cleared when the Silo Alarm Enable bit is cleared. Conditioning of this bit must occur prior to
any character reception.

Silo Alarm

This is a read-only bit set by the hardware after 16 characters
have been entered into the FIFO buffer. Silo Alarm is held
cleared when Silo Alarm Enable (CSR 12) is cleared. This bit is
reset by a read to the receiver buffer register and does not set
until 16 additional characters are entered into the buffer. If Receiver Interrupt Enable (CSR 06) is set, the occurrence of Silo
Alarm generates a receiver interrupt request. Reception with
CSR 06 cleared, permits flag mode operation of the Silo Alarm
bit.

Transmitter
Interrupt

This bit must be set for Transmitter Ready to generate an interrupt. It is read/write.

Enable

Transmitter
Ready

This bit is read only and is set by the hardware. This bit sets
when the transmitter clock stops on a line whose transmit buffer

may be loaded with another character and whose associated
TCR bit is set. The transmitter line number, specified in CSR 08
and CSR 09, is only valid when Transmitter Ready is set. Transmitter Ready is cleared by any of the following conditions.
1.

When Master Scan Enable is cleared

When the associated TCR bit is cleared for the line
number pointed to in CSR 08 and CSR 09

At the conclusion of the load instruction of the transmit data register (low byte only)

If additional transmit lines require service, Transmitter Ready
reappears within 1.4 us from the completion of the transmit
data register load instruction. The occurrence of Transmitter
Ready with Transmitter Interrupt Enable set, generates a transmitter interrupt request.

3-4

Table 3-3

RBUF Bit Assignments

Bit

Title

Function

00-07

Received
Character

These bits contain the received character, right justified. The
least significant bit is bit 00. Unused bits are 0. The parity bit is

Received
Character

These bits contain the line number upon which the Received
Character was received. Bit 08 is the least significant bit.

08-09

not shown.

Line Number

10-11

Not used

Parity Error

This bit is set if the sense of the parity of the received character

Framing Error

This bit is set if the received character did not have a stop bit

Overrun Error

Valid Data

does not agree with that designated for that line.

present at the proper time. This bit is usually interpreted as indicating the reception of a break.

This bit is set if the received character was preceded by a charac-

ter that was lost due to the inability of the receiver scanner to
service the UART receiver holding buffer on that line.

This bit, when set, indicates that the data presented in bits 00-14

is valid. This bit permits the use of a character-handling program that takes characters from the FIFO buffer until there are
no more available. This is done by reading this register and
checking bit 15 until the program obtains a word for which bit
15 is zero.

3.2.3

Line Parameter Register

The line parameter register (LPR) controls the operating parameters associated with each line in the
DZV11. The LPR is a word-addressable, write-only register. The line parameters for all lines must be
reloaded following an occurrence of either BINIT or device Master Clear. Table 3-4 lists bit assignments.

3.2.4

Transmitter Control Register

The transmitter control register (TCR) is a byte- and word-addressable register. The low byte of the
TCR register contains the transmitter control bits which must be set to initiate transmission on a line.
Each TCR bit position corresponds to a line number. For example, TCR bit 00 corresponds to line 00,
bit 01 to line 01, etc. Setting a TCR bit causes the transmitter scanner clock to stop if the UART for
this line has a transmit buffer empty condition. An interrupt is then generated if Transmitter Interrupt
Enable is set. The scanner clock restarts when either the transmit data register (TDR) is loaded with a
character or the TCR bit is cleared for the line on which the clock has stopped. TCR bits must only be
cleared when the scanner is not running (i.e., Transmitter Ready is set or Master Scan Enable is
cleared).

LPR Bit Assignments

Table 3-4
Bit

00-01

Title

Function

Parameter Line

These bits specify the line number for which the parameter information (bits 3-12) is to apply. Bit 00 is the least significant

Number

bit.
02

Not used

Must always be written as a zero when specifying the parameter
line number. Writing this bit as a one extends the parameter line
number field into nonexistent lines. Parameters for lines 00-03
are not affected.

03-04

Character
Length

These bits are set to receive and transmit characters of the
length (excluding parity) as shown below.
04
0
0
1
1

03
0
1
0
1

5 bit
6 bit
7 bit
8 bit

Stop Code

This bit sets the stop code length (0 = 1 unit stop, 1 = 2 unit
stop or 1.5 unit stop if a 5-level code is employed).

Parity Enable

If this bit is set, characters transmitted on the line have an appropriate parity bit affixed, and characters received on the line
have their parity checked.

0Odd Parity

If this bit is set and bit 06 is set, characters of odd parity are
generated on the line and incoming characters are expected to
have odd parity. If this bit is not set, but bit 06 is set, characters
of even parity are generated on the line, and incoming characters are expected to have even parity. If bit 06 is not set, the
setting of this bit is immaterial.

08-11

Speed Code

The state of these bits determines the operating speed for the
transmitter and receiver of the selected line.

Baud Rate

0
0
0
0
0
0

0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

50
75
110
134.5
150
300

600

0
1
1
1

1
0
0
0

1
0
0
1

1
0
0
0

1200
1800
2000

3-6

2400

Table 3-4

Bit

08-11

(cont)

Title

Function

Speed Code

Baud Rate

1
1
1
1

0
1
1
1

1
0
0
1
1

1
0
1
0
1

3600
4800
7200
9600
Invalid

(cont)

LPR Bit Assignments (Cont)

Receiver
Enable

This bit must be set before the UART receiver logic can assemble characters from the serial input line. This bit is cleared
following a BINIT or device Master Clear.

13-15

Not used

The TCR bits are represented in bits 00-03. These bits are read/write and are cleared by BINIT or
device Master Clear. Bits 04-07 are unused and read as zero.

The high byte of the TCR register contains the writable modem control lead, data terminal ready

(DTR). Bit designations are as follows.
Bit

Name

08
09
10
11
12-15

DTR Line 00
DTR Line 01
DTR Line 02
DTR Line 03
Unused; read as zero

Assertion of a DTR bit puts an ON condition on the appropriate modem circuit for that line. DTR
bits are read/write and are cleared only by BINIT. Jumpers have been provided to allow the RTS
circuits to be asserted with DTR assertions.
3.2.5

Modem Status Register

The modem status register (MSR) is a 16-bit read-only register. A read to this register results in the
status of the readable modem control leads, Ring and Carrier. The ON condition of a modem control
lead is interpreted as a logical one. Bits 04-07 and 12-15 are unused and read as a zero. Remaining bit
designations are as follows.

Bit
00

01
02
03
04-07

Name

Bit

Name

Ring Line 00

Carrier Line 00

Ring Line 01
Ring Line 02
Ring Line 03
Unused; read as zero.

09
10
11
12-15

Carrier Line 01
Carrier Line 02
Carrier Line 03
Unused; read as zero.

3.2.6

Transmit Data Register

The transmit data register (TDR) is a byte- and word-addressable, write-only register. Characters for
transmission are loaded into the low byte. TDR bit 00 is the least significant bit. Loading of a character should occur only when Transmitter Ready (CSR 15) is set. The character that is loaded into this
register is directed to the line defined in CSR bits 08 and 09. The high byte of the TDR is designated as

the break control register.

Each of the four multiplexer lines has a corresponding break bit for that line. TDR bit 08 represents
the break bit for line GO, TDR bit 09 for line 01, etc. TDR bits 12-15 are unused. Setting a break bit
forces that line’s output to space. This condition remains until cleared by the program. This register is
cleared by BINIT or device Master Clear. The break control register can be utilized regardless of the
state of the device Maintenance bit (CSR 03).

~—

3-8

CHAPTER 4
PROGRAMMING

4.1

SCOPE

4.2

DEVICE ADDRESS ASSIGNMENTS

This chapter contains information for programming the DZV11 in the most efficient manner. To do
so, the programming controls must be fully understood. The following paragraphs discuss the DZV11
from the programming point of view and describe recommended programming methods.
The device address assigned to the DZV11 resides in the floating address space of the LSI-11. This
address space ranges from 1600103 to 163776g. Each DZV11 requires increments of 10g address locations and the first option should be configured with an address of 160010g. The initial configured
address assumes that the system consists of only DZV11s in the floating address field. If the DUV1I
option is also configured in the floating address field, assign the DZV11 an address that establishes a
gap of 10g address locations between the last DUV11 and the first DZV11. For example: If the system
consists of one DUVI1I located at 160010g, the DZV11 should be configured with an address of
160030g.

4.3

INTERRUPT VECTOR ADDRESS ASSIGNMENTS

The DZV11 device vector address is selected from the floating vector space. This space ranges from
address 300g to address 7763. Each DZV11 requires increments of 10g address locations for its two
contiguous interrupt vectors. If the DZV11 is the only option in the floating vector area, configure it
for a vector of 300g. If there are options other than the DZV11 residing in the floating vector area,
other configuration rules must be applied. When configuring the device vector, only the first vector
address must be considered. The first vector, or base vector, must start on a zero boundary.
A zero boundary is one that has the three least significant bits equal to zero. The second vector is
controlled by the first vector and data bit 02. Data bit 02 is generated by the M7957 hardware.
Any option ahead of DZV11 in the floating vector space that is not in the configuration should not
occupy any vector space gap. For example, if only DZV11 is in the system, the vector for DZV11
should be 300. The simplest case is as follows.

Option

Address

Vector

Comment

GAP
GAP
GAP
GAP
GAP
GAP
GAP
DZVii
GAP

160010
160020
160030
160040
160050
160060
160070
160100
160110

300
-

No QBus-compatible DJ11
No QBus-compatible DH11
No QBus-compatible DQI1 1
No DUV11
No QBus-compatible DUP11
No QBus-compatible LK11
No QBus-compatible DMCl1
No more DZVll1s

Each DZV11 requires two interrupt vectors, one for the transmitter section and one for the receiver
section. If simultaneous interrupt requests are generated from each section, the receiver section would
have priority in placing its vector onto the LSI bus. A receiver interrupt to address XXO0 is generated
from having either a Receiver Done (CSR 07) or Silo Alarm (CSR 13) occurrence. A transmitter
interrupt to address XX4 is generated by Transmitter Ready (CSR 15). Additional prerequisites for
generating interrupts are that the individual interrupt enable bits (CSR 06 and CSR 14) be set. The
recommended method of clearing interrupt enable bits is first to raise the processor status word to level

~—

4; next, to clear these interrupt enable bits; and then lower the processor status word to zero. Using this
method prevents false interrupts from being generated.

4.4

PROGRAMMING FEATURES

The DZV11 has several programming features that allow control of baud rate, character length, stop
bits, parity, and interrupts. This paragraph discusses the application of these controls to achieve the
desired operating parameters.

4.4.1

Baud Rate

Selection of the desired transmission and reception speed is controlled by the conditions of bits 08-11
of the LPR. Table 4-1 depicts the required bit configuration for each operating speed. The baud rate
for each line is the same for both the transmitter and receiver. The receiver clock is turned on and off

by setting and clearing bit 12 in the LPR for the selected line.

Table 4-1 Baud Rate Selection Chart
Bits

4.4.2

~—

Baud Rate

0
0
0
0
0
0
0
0
1
1
{
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
Not used

Character Length

The selection of one of the four available character lengths is controlled by bits 03 and 04 of the LPR.
The bit conditions for bits 04 and 03, respectively, are as follows: 00 (5-level), 01 (6-level), 10 (7-level),

and 11 (8-level). For character lengths of 5, 6, and 7, the high-order bits of the received character are

forced to zero.
4-2

~—

4.4.3

Stop Bits

The length of the stop bits in a serial character string is determined by bit 05 of the LPR. If bit 05 is a
zero, the stop length is one unit; bit 05 set to a one selects a 2-unit stop unless the 5-level character
length (bits 03 and 04 at zero) is selected, in which case the stop bit length is 1.5 units.
4.44

Parity

The parity option is selected by bit 06 of the LPR. Parity is enabled on transmission and reception by
setting bit 06 to a one. Bit 07 of the LPR allows selection of even or odd parity, and bit 06 must be set
for bit 07 to be significant. The parity bit is generated and checked by hardware and does not appear in
the RBUF or TBUF. The parity error (bit 12, RBUF) flag is set when the received character has a
parity error.
4.4.5

Interrupts

The Receiver Interrupt Enable (RIE) and Silo Alarm Enable (SAE) bits in the CSR control the circumstances upon which the DZV11 receiver interrupts the LSI-11 processor.
If RIE and SAE are both clear, the DZV11 never interrupts the LSI-11 processor. In this case, the
program must periodically check for the availability of data in the silo and empty the silo when data is
present. If the program operates off a clock, it should check for characters in the silo at least as often as
the time it takes for the silo to fill, allowing a safety factor to cover processor response delays and time
to empty the silo. The Receiver Done (RDONE) bit in the CSR sets when a character is available in the
silo. The program can periodically check this bit with a TSTB or BIT instruction. When RDONE is
set, the program should empty the silo.
If RIE is set and SAE is clear, the DZV 11 interrupts the LSI-11 processor to the DZV11

receiver vector

address when RDONE is set, indicating the presence of a character at the bottom of the silo. The
interrupt service routine can obtain the character by performing a MOV instruction from the RBUF.
If the program then dismisses the interrupt, the DZV11 interrupts when another character is available
(which may be immediately if additional characters were placed in the silo while the interrupt was
being serviced). Alternatively, the interrupt service routine may respond to the interrupt by emptying
the silo before dismissing the interrupt.
If RIE and SAE are both set, the DZV11 interrupts the LSI-11 processor to the DZV11 receiver vector
when the Silo Alarm (SA) bit in the CSR is set. The SA bit is set when 16 characters have been placed
in the silo since the last time the program has accessed the RBUF. Accessing the RBUF clears the SA
bit and the associated counter. The program should follow the procedure described in Paragraph 4.4.6
to empty the silo completely in response to an Silo Alarm interrupt. This ensures that any characters
placed in the silo while it is being emptied are processed by the program.
NOTE
If the program processes only 16 entries in response
to each Silo Alarm interrupt, characters coming in
while interrupts are being processed build up without
being counted by the Silo Alarm circuit and the silo
may eventually overflow without the alarm being issued.

If the Silo Alarm interrupt is used, the program will not be interrupted if fewer than 16 characters are
received. In order to respond to short messages during periods of moderate activity, the LSI-11 program should periodically empty the silo. The scanning period depends on the required responsiveness
to received characters, While the program is emptying the silo, it should ensure that DZV'11 receiver

interrupts are inhibited. This should be done by raising the LSI-11 processor priority. The Silo Alarm

interrupt feature can significantly reduce the LSI-11 processor overhead required by the DZV11 receiver by eliminating the need to enter and exit an interrupt service routine each time a character is
received.

4-3

The Transmitter Interrupt Enable (TIE) bit controls transmitter interrupts to the LSI-11 processor. If
enabled, the DZV11 interrupts the LSI-11 processor at the DZV11 transmitter interrupt vector when
the Transmitter Ready (TRDY) bit in the CSR is set, indicating that the DZV11 is ready to accept a
character to be transmitted.

4.4.6

Emptying the Silo

4.4.7

Transmitting a Character

The program can empty the silo by repeatedly performing MOV instructions from the RBUF to
temporary storage. Each MOV instruction copies the bottom character in the silo so it is not lost and
clears out the bottom of the silo, allowing the next character to move down for access by a subsequent
MOV instruction. The program can determine when it has emptied the silo by testing the Data Valid
bit in each word moved out of the RBUF. A zero value indicates that the silo has been emptied. The
test can be performed conveniently by branching on the condition code following each MOV instruction. The TST or BIT instruction must not access the RBUF because these instructions cause the next
entry in the silo to move down without saving the current bottom character. Furthermore, following a
MOV from the RBUF, the next character in the silo is not available for at least 1 us. Therefore, on fast
CPUs, the program must use sufficient instructions or NOPs to ensure that successive MOVs from the
RBUF are separated by a minimum of 1 us. This prevents a false indication of an empty silo.

The program controls the DZV11 transmitter through four registers on the QBus: the control and
status register (CSR), the line parameter register (LPR), the transmit control register (TCR), and the
transmit data register (TDR).

Following DZV11 initialization, the program must use the LPR to specify the speed and character
format for each line to be used and must set the Master Scan Enable (MSE) bit in the CSR. The
program should set the TIE bit in the CSR if it wants the DZV11 transmitter to operate on a program
interrupt basis.

The TCR is used to enable and disable transmission on each line. One bit in this register is associated
with each line. The program can set and clear bits by using MOV, MOVB, BIS, BISB, BIC, and BICB
instructions. (If word instructions are used, the Line Enable bits and the DTR bits are simultaneously
accessed.)

The DZV11 transmitter is controlled by a scanner which is constantly looking for an enabled line (Line
Enable bit set) which has an empty UART transmitter buffer. When the scanner finds such a line, it
loads the number of the line into the 2-bit transmit line number (TLINE) field of the CSR and sets the
TRDY bit, interrupting the LSI-11 processor if the TIE bit is set. The program can clear the TRDY bit
by moving a character for the indicated line into the TBUF or by clearing the line enable bit. Clearing
the TRDY bit frees the scanner to resume its search for lines needing service.

To initiate transmission on an idle line, the program should set the TCR bit for that line and wait for
the scanner to request service on the line, as indicated by the scanner loading the number of the line
into TLINE and setting TRDY. The program should then load the character to be transmitted into the
TBUF by using a MOVB instruction. If interrupts are to be used, a convenient way of starting up a line
is to set the TCR bit in the main program and let the normal transmitter interrupt routine load the
character into the TBUF.

NOTE

The scanner may find a different line needing service
before it finds the line being started up. This occurs if
other lines request service before the scanner can find
the line being started. The program must always
check the TLINE field of the CSR when responding
to TRDY to ensure that it loads characters for the
correct line. Assuming the program services lines as
requested by the scanner, the scanner eventually
finds the line being started. If several lines require

service, the scanner requests service in priority order
as determined by line number. Line 3 has the highest
priority and line 0 the lowest.
To continue transmission on a line, the program should load the next character to be transmitted into
the TBUF each time the scanner requests service for the line as indicated by TLINE and TRDY.
To terminate transmission on a line, the program loads the last character normally and waits for the
scanner to request an additional character for the line. The program clears the Line Enable bit at this
time instead of loading the TBUF.
The normal rest condition of the transmitted data lead for any line is the one state. The Break (BRK)

bits are used to apply a continuous zero signal to the line. One bit in the TDR is associated with each
line. The line remains in this condition as long as the bit remains set. The program should use a MOVB
instruction to access the BRK bits. If the program continues to load characters for a line after setting
the BRK bit, transmitter operation appears normal to the program despite the fact that no characters
can be transmitted while the line is in the continuous zero sending state. The program may use this
facility for sending precisely timed zero signals by setting the BRK bit and using transmit ready interrupts as a timer.
It should be remembered that each line in the DZV 11 is double buffered. The program must not set the
BRK bit too soon or the two data characters preceding the break may not be transmitted. The pro-

gram must also ensure that the line returns to the one state at the end of the zero sending period before
transmitting any additional data characters. The following procedure accomplishes this. When the
scanner requests service the first time after the program has loaded the last data character, the program
should load an all-zero character. When the scanner requests service the second time, the program
should set the BRK bit for the line. At the end of the zero sending period, the program should load an
all-zero character to be transmitted. When the scanner requests service, indicating this character has
begun transmission, the program should clear the BRK bit and load the next data character.
4.4.8

Data Set Control

The program may sense the state of the Carrier and Ring Indicator signals for each data set and may

control the state of the Data Terminal Ready signal to each data set. The program uses two registers to
access the DZV 11 data set control logic. There are no hardware interlocks between the data set control
logic and the receiver and transmitter logic. Any required coordination should be done under program
control.

The Data Terminal Ready (DTR) bits in the TCR are read/write bits. Setting or clearing a bit in this
register turns the appropriate DTR signal on or off. The program may access this register with word or
byte instructions. (If word instructions are used, the DTR and Line Enable bits are simultaneously
accessed.) The DTR bits are cleared by the INIT signal on the QBus but is not cleared if the program
clears the DZV11 by setting the CLR bit of the CSR.
The Carrier (CO) and Ring (RI) bits in the MSR are read-only bits. The program can determine the
current state of the Carrier signal for a line by examining the appropriate bit in the MSR. It can
determine the current state of the Ring signal by examining the appropriate bit of the ring register. The
program can examine these registers separately by using MOVB or BITB instructions or can examine
them as a single 16-bit register by using MOV or BIT instructions. The DZV11 data set control logic
does not interrupt the LSI-11 processor when a Carrier or Ring signal changes state. The program
should periodically sample these registers to determine the current status. Sampling at a high rate is
not necessary.

4-6

CHAPTER S

TECHNICAL DESCRIPTION

5.1

GENERAL

This chapter describes the DZV11 at three levels: interface, circuit function, and circuit operation.
Where practical, the illustrations reference the circuit schematic page number and use the signal mnemonics (Figure 5-1). Signal mnemonics in the Field Maintenance Print Set are prefaced by the page
number on which they originate. For example, D12 VALID DATA H originates on sheet D12. The
print set is helpful, but not essential, for understanding this chapter.

For further information about the LSI chips used on the DZV11, refer to Appendix A.

INDICATES THAT SIGNAL IS IN
/ LOGIC LOW STATE WHEN TRUE

BINIT L

1/0
CONTROL
LOGIC

INDICATES THAT SIGNAL IS IN
LOGIC HIGH STATE WHEN TRUE

INITIALIZE H

\ REFER TO SHEET D5 OF THE CIRCUIT SCHEMATICS
TO LOCATE THE DETAILS OF THIS CIRCUIT.

MK-0130

Figure 5-1

5.2

INTERFACE FUNCTIONS

5.2.1

LSI-11 to DZV11 Interface

Labeling Conventions

This paragraph illustrates the sequences of signal exchanges that occur among the LSI-11, the DZV11,
and data sets. For a detailed description of LSI-11 operation, refer to the Microcomputer Handbook
(DEC part number EB 07948 53/77). For a discussion of the signals at the circuit level, refer to
Pararaph 5.4 of this manual. For information about the specific meaning and function of modem
signals, refer to the documentation for the modem with which the DZV11 is to be used.
Figure 5-2 lists the signals that interface the LSI-11 to the DZVI11. Table 5-1 defines these signals.
Figures 5-3 through 5-6 indicate their interaction.

5-1

<: DAL L BOAL 15 L">
BINIT L
BIRQ L
BIAK! L

BIAKO L

CPU

DZV11

BBS7 L
>

BSYNC L
BDIN L

BDOUT L
BWTBT L
e
—

BRPLY L

MK-0141

Figure 5-2

Table 5-1

Mnemonic

BINIT L

LSI-11/DZV11 Interface

LSI-11/DZV11 Interface Signals

Description

Initialize - BINIT is asserted by the processor to initialize or clear all devices

connected to the 1/O bus. The signal is generated in response to a power-up
condition.

BIRQ L

Interrupt Request — A device asserts this signal when its interrupt enable and
interrupt request flip-flops are set. If the processor's processor status (PS)
word bit 7 is 0, the processor responds by acknowledging the request by
asserting BDIN L and BIAKO L.

BIAKI L
BIAKO L

Interrupt Acknowledge Input and Interrupt Acknowledge Output - This is
an interrupt acknowledge signal that is generated by the processor in re-

sponse to an interrupt request (BIRQ L.) The processor asserts BIAKO L,
which is routed to the BIAKI L pin of the first device on the bus. If the device
is requesting an interrupt, it inhibits passing BIAKO L. If it is not asserting
BIRQ L, the device passes BIAKI L to the next (lower-priority) device via its
BIAKO L pin and the lower-priority device’s BIAKI L pin.

BBS7 L

Bank 7 Select - The CPU asserts BBS7 L when an address in the upper 4K
bank (address in the 28K-32K range) is placed on the bus. BSYNC L is then
asserted and BBS7 L remains active for the duration of the addressing portion of the bus cycle.

Table 5-1

LSI-11/DZV11 Interface Signals (Cont)

Mnemonic

Description

BSYNC L

Synchronize - BSYNC L is asserted by the CPU to indicate that it has placed
an address on BDALOQ-15 L. The transfer is in process until BSYNC L is
negated.

BDIN L

Data Input - BDIN L is used for two types of bus operations:

When asserted during BSYNC L time, BDIN L implies an input
transfer, and requires a response (BRPLY L). BDIN L is asserted
when the CPU is ready to accept data from the DZVIL1.

When asserted without BSYNC L, BDIN L indicates that an interrupt operation is occurring.

BDOUT L

Data Output - BDOUT, when asserted, implies that valid data is available
on BDALO-15 L and that an output transfer is taking place. BDOUT L is
deskewed with respect to data on the bus. The DZV11 must assert BRPLY L
to complete the transfer.

BWTBT L

Write/Byte - BWTBT L is used in two ways to control a bus cycle:

BRPLY L

Itis asserted during the leading edge of BSYNC L to indicate that
an output sequence is to follow (DATO or DATOB), rather than an
input sequence.

It is asserted during BDOUT L, in a DATOB bus cycle, for byte
addressing.

Reply - BRPLY L is asserted in response to BDIN L or BDOUT L and
during IAK transaction. It is generated by the DZV11 to indicate that it has

placed its data on the BDAL bus or that it has accepted output data from the
bus.
BDALOL
BDALI L

BDAL2 L
BDAL3 L
BDAL4 L

BDALS L
BDAL6 L
BDAL7 L
BDALS8 L
BDAL9 L
BDALIOL
BDALII L
BDALI2 L

BDALI3 L
BDALI4 L
BDALIS L

Data/Address Lines - These lines form a bidirectional bus. First, the CPU
places address information on the bus. After the desired device has been
addressed, the CPU removes the address. Then data is placed on the bus. For
an output transfer, the CPU places the data on the bus. For an input transfer, the DZV11 places the data on the bus.

DzZV11

LSi-11

STROBE INTERRUPTS

-«-— — —

® Assert BDIN L

~ -

INITIATE REQUEST

® Assert BIRQ L

TMTM RECEIVEBDIN L

® Store "interrupt selected”

GRANT REQUEST

in device

® Pause and assert
BIAKO L

RECEIVE BIAKI L
®

Receive BIAK | L and inhibit

BIAKO L
® Place vector on BDAL 0-15 L
® Assert BRPLY L
® Terminate BIRQ L
7~

~
~

»
RECEIVE VECTOR & TERMINATE

REQUEST
® Input vector address

® Terminate BDIN L and BIAKO L

- COMPLETE VECTOR TRANSFER
® Remove vector from
BDAL bus

® Terminate BRPLY L

PROCESS THE INTERRUPT
® Save current program PC
and PS on stack

® Load new PC and PS from
vector addressed location
® Execute interrupt service
routine for the device

Figure 5-3

Interrupt Request/Acknowledge Sequence

MK 0131

LSI-11

DZV1i1

ADDRESS DZV11
® Assert BDALO-15 L with
address and

® Assert BBS7 if the

address is in the 28 - 32K range ___
~

——

® Assert BSYNC L

—

S——

—

DECODE ADDRESS

® Store ‘device selected”’
operation

a—"
/
/
—
/
a—

REQUEST DATA

® Remove the address

from BDALO-15 1.

and negate BBS7 L

- —

® Assert BDIN L

~ —
S—

S—

INPUT DATA
® Place data on BDALO-15 L

a—

—

TERMINATE INPUT TRANSFER
® Accept data and respond by
negating BDIN L

TERMINATEBUSCYCLE

— -

—

® Assert BRPLY L

a— -

4
~

S—

T~ ~» OPERATION COMPLETED

@— — — — — — — — —

® Negate BSYNC L

® Terminate BRPLY L
MK-0132

Figure 5-4

DATI Bus Cycle

5-5

LSI-11

DZV11

ADDRESS DZV11
e Assert BDALO-15 L with
address and

® Assert BBS7 L (if address
is in the 28 - 32K range)
® Assert BWTBT L (write
cycle)

e Assert BSYNC L
S
——

—

~TM

DECODE ADDRESS
® Store ““device selected”’

OUTPUT DATA

operation

——— -

® Remove the address from
BDALO-15 L

and negate BBS7 L and BWTBT L
(BWTBT L remains active if

DATOB cycle)

® Place data on BDALO-15 L
® Assert BDOUT L

— —~—

—_

TM =

‘— ——

—— - -

m— -

TAKE DATA

® Receive data from BDAL lines
® Assert BRPLY L

TERMINATE OUTPUT TRANSFER
® Remove data from BDALO-15 L

and negate BDOUT L

T —

—

T -

TERMINATE BUS CYCLE

OPERATION COMPLETED
® Terminate BRPLY L

am— —_ - - -

® Negate BSYNC L {and BWTBT L
if a DATOB bus cycle}

Figure 5-5

MK-0133

DATO or DATOB Bus Cycle

DzVv11

LSI-11
ADDRESS DZV11

® Assert BDALO-15 L with
address

® Assert BBS7 and if the
address is in the 28 - 32K range
® Assert BSYNC L
—

——

S——

T~ —= DECODE ADDRESS

® Store “‘device selected”

operation

[NPUT DATA

—
—

REQUEST DATA

J—

® Remove the address from
BDALO-15 L

and negate BBS7 L
® Assert BDIN L
d ——

it ——

——

® Place data on BDALO-15L
® Assert BRPLY L

—
—

a—
a—

TERMINATE INPUT TRANSFER

® Accept data and respond by
terminating BDIN L

—— —~—

— S—

—

—~

—a COMPLETE INPUT TRANSFER
®

_
/

J—

Remove data

® Terminate BRPLY L

a—
OUTPUT DATA
e Place output data on BDALO-15 L
e (Assert BWTBT L if an output

byte transfer)
@ Assert BDOUT L

—

T—

TERMINATE OUTPUT TRANSFER
® Terminate BDOUT L, and remove ——
data from BDAL lines

— -

— -a TAKE DATA
® Receive data from BDAL lines
® Assert BRPLY L
_

a— - -

———

—

TERMINATE BUS CYCLE
o Negate BSYNC L

-— — = -

J—

OPERATION COMPLETED

® Terminate BRPLY L

{and BWTBT L if in
a DATIOB bus cycle)

Figure 5-6

MK-0134

DATIO or DATIOB Bus Cycle

5-7

Transactions between the LSI-11 and the DZV11 may be program-initiated or interrupt-driven. An
interrupt-driven transaction is illustrated in Figure 5-3. An input operation (DATI) is equivalent to a
read operation. An output operation (DATO or DATOB) is equivalent to a write operation. A DATI
reads a word. A DATO writes a word. A DATOB writes a byte. These operations are described further
in Paragraph 5.4.

A DATIO cycle is equivalent to a read-modify-write operation. An addressing operation and an input
word transfer are first executed in a manner similar to the DATI cycle; however, BSYNC L remains in
the active state after completing the input data transfer. This causes the addressed device or memory to
remain selected, and an output data transfer follows without any further addressing. After completing
the output data transfer, the device terminates BSYNC L, completing the DATIO cycle. The sequence
required for a DATIO cycle is shown in Figure 5-6. Note that the output data transfer portion of the
bus cycle can also be a byte transfer. This is a DATIOB cycle. Figure 5-6 illustrates both.
5.2.2

DZV11 to Data Set Interface

When the DZV11 interfaces a local terminal, the only exchanges may be EIA level data. When interfacing a data set, however, the DZV11 controls from one to three signals, and monitors two others.

Table 5-2 defines the modem control signals. Figures 5-7 through 5-9 illustrate typical sequences. The
response the DZV11 makes to the Ring and Carrier signals is under program control.

Table 5-2

Signal

Modem Control Signals

Function

Data Terminl Ready

Enables the local modem to be connected with a remote
modem. This signal is negated to terminate a call.

Request to Send

Holds the modem in the transmit mode.

Forced Busy

Used with Bell Model 103E and 113B equipment. Signals
the modem controller to switch to another channel.

Ring Indicator

Indicates that the local modem is receiving a ringing signal
’

C'arrier (Received Line
Signal Detector)

from a remote modem.

Indicates that the local modem is receiving a signal from a
remote modem, and that the signal meets the suitability
criteria of the local modem.

5-8

~—

DATA TERMINAL
EQUIPMENT (DTE)

DATA COMMUNICATION
EQUIPMENT (DCE)

PROGRAM ASSERTS
DATA TERMINAL
READY (CD)

CUSTOMER DIALS NUMBER.
\

RING BACK IS HEARD.
ANSWERING STATION
ASSERTS DATA TERMINAL

READY. BOTH STATIONS
ENTER DATA MODE.

DATA SETS EXCHANGE
CARRIER FREQUENCIES.
CHANNEL ESTABLISHED.

CARRIER DETECT (CF)
IS ASSERTED.

RECEIVED DATA (BB)
LEAD UNCLAMPED

TRANSMITTED

DATA (BA)
DATA

RECEIVED

COMMUNICATION

DATA (8B)

BEGINS

DzZVv11

DATA SET

MODELS 103A/E/G/H, 113A, 212A

(ORIGINATING EQUIPMENT)

Figure 5-7

Channel Established by Local Modem

5-9

MK-0135

DATA TERMINAL

DATA COMMUNICATION

EQUIPMENT (DCE)

EQUIPMENT (DTE)

RINGING SIGNAL

RECEIVED FROM

1eD

NG psSER

L—

REMOTE STATION

RING INDICATOR (CE)
IS ASSERTED

PROGRAM ASSERTS

]

DATA TERMINAL

READY (CD)

T Tepn,

SEND (CA)

Reg

VEST 16

SENp

DATA SETS EXCHANGE

CARRIER SIGNALS

AND ESTABLISH CHANNEL
-

CARRIER DETECT (CF)

IS ASSERTED

TRANSMITTED
DATA (BA)
.

DATA

COMMUNICATION

BEGINS

RECEIVED

DATA(BB)

DZV11

DATA SET
MODEL 202D

(ANSWERING EQUIPMENT)
NOTE:

EXAMPLE SHOWS MODEM CONFIGURED FOR UNATTENDED ANSWERING AND
FULL DUPLEX DATA-PHONE SERVICE. (DATA-PHONE IS A SERVICE MARK OF

THE AT & T CO.)

Figure 5-8

Channel Established by Remote Modem

5-10

MK-0136

DATA TERMINAL

DATA COMMUNICATION

EQUIPMENT (DTE)

EQUIPMENT (DCE)

PROGRAM ASSERTS

DATA TERMINAL

READY (CD). THIS

A TERMINAL READY

ASSERTS BOTH
REQUEST TO SEND

REQ
%

BUSY.

’W

{CA) AND FORCED

CUSTOMER DIALS
NUMBER. DATA

?:L»:T'\IISEILESTABLISHED
.

—

CARRIER ASSERTED

CARRIER DETECT (CF)

IS ASSERTED.

TRANSMITTED DATA (BA)
DATA

COMMUNICATION

RECEIVED DATA (BB)

BEGINS

MODEL 103E WITH

DzV1i1

FORCED BUSY OPTION.

(ORIGINATING EQUIPMENT)

mx-0157

~—

Figure 5-9

5.3

Interface with Bell Data Station

CIRCUIT FUNCTIONS

The major functional areas of the DZV11 circuitry are represented in Figure 5-10. The numbers in the
blocks refer to the paragraphs in which the block is discussed.

Data to be transmitted on the communication lines moves from the LSI-11 bus through the bus
interface to the TDR in the UARTs. There it is converted from parallel to serial and sent to the EIA
transmitters. The transmitters convert the serial data from TTL to EIA levels and send it to the
communication line (or data set.)

Data coming in from the communication lines is converted from EIA to TTL by the EIA receivers,
then from serial to parallel by the UARTs. The parallel data leaves the UART receiver buffers and is
stored in the silo buffer. From there it is transferred via multiplexers to the bus interface. The bus
interface places the data on the LSI-11 bus.

The interrupt logic requests interrupt service when a transmitter is empty and when the silo buffer has
either 1 or 16 characters of received data, as selected by the program.

The transmitter control determines which of the four possible lines is to be used, and controls the
loading of the data.

The receiver control scans the receiver status and controls the loading and unloading of the silo.
5-11

BREAK

EIA

LOGIC

TRANS.

PARA.

5.4.7

5.4.5

}

MITTER
CONTROL

5.4.10

BUS

5.4.11
D10

LOGIC

D13

5.4.1

RUPT
o

AND

PARA.

CONTROL

D3Q
8

544

FORMAT

PARA.
D11

SPEED

RECEIVER

5.4.9

D14

D12

CONTROL

g':fi;\-

PARA.

549

PARA.

INTER-

EIA

RCVR.

BUFFER
PARA

PLEXER

LSI-11 BUS

AND

5.4.6

SILO

MULTI-

1/0

PARA.

BUFFERS) |
PARA.

PARA.

CONTROL
PARA.

LOGIC

TRANSMIT

DATA

FACE

(INCLUDES
RECEIVE

INTER-

5.4.1

MAINT.
MODE

UARTs

PARA.

D6
D10

D10
TRANS-

~—r

5.4.8
D8

FROM/TO
REGISTERS

5.4.2

POWER

SUPPLIES
PARA.

5.4.12

Figure 5-10

Simplified Functional Block Diagram

5-12

MK.-0156

The speed and format control generates clock signals for the UARTs. Under program control, it
\_1

selects baud rate and stop bit, parity bit and character length parameters.
The break logic inhibits output data to create a BRK signal. The four lines operate independently and
under program control.
The maintenance mode data selector provides the capability of switching the data outputs the data
inputs. This is used to verify module operation.

The power supplies convert voltages available on the LSI-11 bus into other voltages also required by
the module.
Each of the circuits shown in Figure 5-10 is described in greater detail in Paragraph 5.4.
5.4 CIRCUIT OPERATION
The interaction between the LSI-11 and the DZV11 is asynchronous to the interchanges between the

DZV11 and the communication lines it controls. Therefore, the circuit description in this paragraph
treats the module from three points of view. Paragraphs 5.4.1 through 5.4.3 cover the operations of
moving control, status, and character data between the LSI-11 and the DZV11 internal registers.
Paragraphs 5.4.4 through 5.4.7 discuss the flow of data between the external lines and the DZV11
internal registers. Paragraphs 5.4.8 through 5.4.11 discuss functions that are controlled by the computer but directly affect the movement of data between the DZV11 and the lines. Paragraph 5.4.12
discusses the power supplies.
5.4.1 Bus Interface
Data and control signals move between the LSI-11 bus and the DZV11 transmit and receive circuitry

by means of a group of bus transceivers, multiplexers, and latches. Figure 5-11 indicates the functional
relationship of these circuits to the addressable device registers.
The bus transceivers are contained in four DC005 transceiver chips. These interface LSI-11 bus lines
BDALOO through BDALL1S5 to the module’s internal device data bus lines 00 through 15. The device
data bus lines have three logical conditions: TTL low, TTL high, and disabled. The disabled state is a
very high impedance, which permits the internal bus lines to be used in both directions by high-speed,
low-power devices.

The transceiver chips also perform the functions of address decoding and vector generation. Address
decoding is accomplished by comparing the states of BDALO3 through BDAL12 with the states selected by address switches A03 through A 12 (switches 10 through 1, respectively, on switchpack E30).
When the LSI-11 addresses an I/O device, it asserts BBS7 L (bank select 7) during address time. This
indicates that the address is in the 28K-32K range of addressing space, and enables the DCO0O0S transceivers to decode the address. If the address matches the switch selection, the circuit asserts DEVICE
SELECT H to the I/O control logic.
During data time, the transceivers transfer data from the LSI-11 bus lines to the device data bus lines if
the operation is an output data transfer. If the operation is an input data transfer, the I/O control logic
asserts READ L and READ DEVICE H. This switches the transceivers to their opposite state, in
which they transfer data from the device data bus to the LSI-11 bus.
The bus interface logic generates vector addresses under the control of the interrupt logic and vector
address switches V03 through V08 (switches 6 through 1, respectively, on switchpack E2). The vector
switches set the states of vector bits 03 through 08 when the interrupt logic enables vector generation.
Bit 02 is controlled directly by the interrupt logic. It is set for a transmitter interrupt and cleared for a
receiver interrupt.

5-13

SW1-SW10 | ADDRESS

A12-A03 | SWITCH
D2|

E30

BDAL 00:15 L ) BUS
,

,—.>

TRANS-

TCR

CEIVERs

BBS7

~—

DCO005

) TDR

D2 |

t
VECTOR

3"(‘)’;‘3‘3’3

SWITCH E2

LPR
D51
y

~—=

[«4]

[

CSR

g T g

INITIALIZE

alg g

§
4

PLEXERS

TCR

INITH

<[BINITL
A
INIT L

P
)

BIRQ L

INTERRUPT|

-1z

BIAKI L

CHIP

[BIAKO L

DCO003

[ ENABLE
nAR

DS) Ol
wl n-

a
o

REQUEST

7
w

Sl <

——3

BWTBT LL
| BDOUT
BRPLY L
)

MUX

ADDRESS

ENCODER
D3

[

CONTROL
PROTOCOL

LD LPR REG L

CHIP

LD TDR REG H

LOAD

|pa

BREAK

LD TCR HIGH BYTE H

SEL 4|SELECT 02 L

,|DECODER [i D TCR LOWBYTE H

SEL OfSELECT 06 L

EL 2|SELECT 04 L

DELAY
D4

SEL GISELECT 00 L

MSR

INWD

BSYNC L

RBUF

BDIN L

fa———~

MULTI-

>la >

CIRCUIT

OUT LB

LD CSR HIGH BYTE H
LD CSR LOW BYTE H

D4
MK-0127

Figure 5-11

Bus Interface, I/O Control and Interrupt Logic

5-14

on the
When an interrupt occurs, the conditions selected by the vector switches are immediately placed
the
from
H
DEVICE
READ
LSI-11 bus lines. The transceivers do this without need of READ L or
1/O control circuit.

5.4.2

1/0 Control

device
The 1/O control logic controls the flow of status bits and data bits between the LSI-11 and the
is
register
registers. It monitors the three least significant bits of the address word to determineLwhich
to
Byte)
(Write
to be read or loaded, and which byte in the register is affected. It monitors BWTBT bytes, but reads
determine if a byte is being loaded or a word is being loaded. (The LSI-11 canis write
only words.) Control signals BDIN L and BDOUT L indicate whether data to be moved into the
computer or out of it.

The chip uses
The major element in the 1/O control circuit is a DC004 protocol chip (Figure 5-11).
four register
of
one
asserts
device data bus bits 01 and 02 to decode the device register address and then
byte or
high
a
for
HB
OUT
select lines. It uses device data bus bit 00 and BWTBT L to select either
L), the
BDOUT
by
d
(indicate
OUT LB for a low byte. If the operation is an output data transfer
a load
produce
to
signals
select
register load decoder uses OUT LB, OUT HB (or both) and the register
the
from
loaded
be
to
register
pulse. The load pulse enables the proper byte or bytes of the selected
~

device data bus.

If the
The register select lines are also used to control the address lines on a group of eight multiplexers. ers
to
multiplex
the
switches
control
I/O
the
L),
operation is an input data transfer (indicated by BDIN
ers
multiplex
the
enables
L
READ
H.
DEVICE
the selected register and asserts READ L and READ
READ
to place the data from the selected register on to the device data bus (Table 5-3). READ L and
to the
bus
data
device
the
from
data
the
transfer
to
rs
DEVICE H together enable the bus transceive
LSI-11 bus (Table 5-4).

Table 5-3

SELECT L*

—
02

F
F
F
T

F
F
T
F

F
T
F
F

Multiplexer Addressing
MUX
:
—_—
SO
S1

Selected
Register

F
F
T
T

F
T
F
T

CSR
RBUF
TCR
MSR

*T = TRUE condition, that is, +3 V on signal lines with an H suffix
and 0 V on signal lines with an L suffix.
Table 54

Transceiver Switching

READ L*

READ DEVICE H

Mode

LSI-11 bus to device data bus

Does not occur

LSI-11 bus disconnected/device

data bus open

Device data bus to LSI-11 bus

*T = TRUE condition, that is, +3 V on signal lines with an H suffix and 0 V on
signal lines with an L suffix.

5-15

5.4.2.1
1.

Input Operation - An input data transfer (DATI bus cycle) proceeds as follows.
The CPU places the device address on LSI-11 bus lines BDALOO L through BDALISL, and
asserts BBS7 L. BWTBT L is negated at this time because all input transfers are full words
(Figure 5-12).

BDIN

BRPLY

Bz N\
/
swrsT Y

X
MK-0137

Figure 5-12

Data Input Timing

The bus transceivers are configured to receive from the LSI-11 bus unless switched otherwise. BBS7 L enables the transceivers to decode the address and to assert DEVICE SELECT
H, which enables the /O control circuit.

The CPU asserts BSYNC L. The leading edge of BSYNC L latches the states of DEVICE
SELECT H and device data bus bits 00 through 02 into the protocol chip. These are decoded .
to select the desired register by addressing the multiplexers.

Next, the CPU removes the address from the LSI-11 bus lines, negates BBS7 L, and asserts
BDIN L. BDIN L causes the I/O control to generate READ L and READ DEVICE H.
These signals place the contents of the selected register on the device data bus and the LSI-11
bus. BDIN L also generates BRPLY L. This signals the computer that the data is on the bus.

The computer reads in the data and then negates BDIN L.

The I/O control logic responds to the negation of BDIN L by negating BRPLY L.

The CPU terminates the bus cycle by negating BSYNC L.

In the absence of a TRUE condition on BSYNC L, the protocol chip releases the register
selection lines and the READ L and READ DEVICE H signals. The bus interface reverts to
its normal condition of receiving from the LSI-11 bus and transmitting onto the device data
bus.

5-16

5.4.2.2. Output Operation - The DZV11 can accept data from the computer in
either bytes or words.
To write a word out to the module, the CPU performs a DATO bus cycle. To
write a byte, it performs
a DATOB bus cycle (Figure 5-13). An output data transfer proceeds as follows.
1.

The CPU places the device address on the LSI-11 bus and asserts BBS7 L and BWTBT L.

(During address time, BWTBT L is asserted for an output operation and negated for an
input operation.) BBS7 L enables the bus interface to decode the address and assert DEVICE SELECT H to the I/O control. The bus interface also applies address bits 00 through
02 to the I/O control.

oac

ssvve \

soout

BRPLY
BBs7
BWTBT

n___ ./
\_
\

/[
/

ASSERTION =BYTE \
MK-0142

Figure 5-13

Data Output Timing

The CPU asserts BSYNC L. The leading edge of BSYNC L latches the states of DEVICE
SELECT H and bits 00 through 02 into the protocol chip. The chip decodes the register
address and asserts the appropriate select line.
The CPU removes the address from the bus lines and negates BBS7 L. If a byte is to be

transferred, BWTBT L remains asserted. If a word is to be transferred, BWTBT L is negated.

At this time, the CPU asserts BDOUT L. BDOUT L enables the protocol chip to decode the
states of BWTBT L and the latched-in address bit 00. The chip uses the signals to assert
OUT HB, OUT LB, or, for word transfers, both (Table 5-5). These signals are gated with the
select lines to produce a load pulse (or pulses) for the selected byte(s).
After the protocol chip receives BDOUT L, it initiates the Bus Reply signal. If the register
being loaded is the LPR or the TDR, the Bus Reply signal is delayed before going to the
CPU as BRPLY L. The delay ensures a minimum of 300 ns setup time for the register being
loaded. The LPR and TDR are located inside the UART and baud rate generator chips, and
therefore require longer to set up than the high-speed latches comprising the other registers.
After the delay times out, BRPLY L is asserted to the CPU to indicate that the register is
loading data.

5-17

Table 5-5 Byte Selection
(Output Operations Only)

Bus Bit 00

Asserted

Signals

Bytes

Don’t care

OUTLBL

Both

OUTLBL

Low

OUTHBL

High

BWTBT L

Device Data

Selected

and
OUTHBL

Next, the CPU removes the data from the bus lines and negates BDOUT L.

The protocol chip responds to this by negating BRPLY L.

The CPU then terminates the bus cycle by negating BSYNC L and, if applicable, BWTBT L.

When BSYNC L is negated, the protocol chip negates the register select and byte lines.

5.4.2.3 Vector Operation — The 1/O control has the additional function of asserting BRPLY L in
response to VECTOR-TO-BUS H from the interrupt control circuit. This action is part of the interrupt sequence, and is independent of the BSYNC L and DEVICE SELECT H. It is discussed in
Paragraph 5.4.3.

5.4.2.4 Initialize Circuit - This circuit produces two initialization signals (INITIALIZE H and INITIALIZE L) when it receives either BINIT L from the LSI-11 bus or the Master Clear bit from the
CSR. Both input signals also generate other clear signals (Figure 5-14). The initialization and clear
signals clear the registers and latches on the module to set initial conditions.
MASTER CLEAR H

ONE
CS

u SEC

BIT 04

ONE-

SHOT

o———:D

INITIALIZEH

PN
LSI-11 BUS

‘

BINIT
L

MODEM CLEAR L

—————0

) INITIALIZE L

CLEAR REPLYH

MK 0138

Figure 5-14

Initialization Signals
5-18

5.4.3 Interrupt Logic
Most of the logic for interrupts is contained in a single DCO003 interrupt chip (Figure 5-15). The chip

contains two interrupt channels: one for receiver interrupts and one for transmitter interrupts. The
circuit generates a receiver interrupt either when the RBUF has one character ready for the computer
(Receiver Done interrupt) or when the silo buffer has 16 characters ready (Silo Alarm interrupt).
The Receiver Done interrupt is enabled by setting CSR bit 06. The Silo Alarm interrupt is enabled by
setting bit 12. Setting bit 12, however, inhibits the receiver done signal from the RBUF. Therefore,
Receiver Done interrupts do not occur when Silo Alarm interrupts are enabled.

The circuit generates a transmitter interrupt when the TDR is empty and ready for another data
output from the computer. The Transmitter Ready interrupt is enabled by setting CSR bit 14.
Both the TIE and RIE bits are located physically in the DC003 interrupt chip although they are
functionally part of the CSR.

The LSI-11’s Interrupt Acknowledge signal (BIAKI L /BIAKO L) is daisy-chained through the devices
on the LSI-11 bus. A device priority is established by its position in the Interrupt Acknowledge daisychain. In the DZV11 interrupt logic, the chain goes through both the receiver section and the transmitter section of the interrupt chip. It passes through the receiver section first, thereby giving receiver
interrupts priority over transmitter interrupts.

Backplanes that provide bussed LSI-11 signals to the C and D sections of the module also use the
daisy-chain scheme in the C section. Jumpers W10 and W11 on the DZVI11 pass the Interrupt Acknowledge and DMA Grant signals to prevent breaking the chain in that section of the backplane.
5.4.3.1 Interrupt Transactions - When interrupts are enabled and a condition requiring service occurs, the interrupt sequence proceeds as follows.
1.

The interrupt logic asserts BIRQ L, the interrupt request line (Figure 5-16).

The LSI-11 responds to BIRQ L by asserting BDIN L and then BIAKI L. BIAK is the
bussed Interrupt Acknowledge signal. It is passed down the priority chain until it reaches the
section of the interrupt chip that initiated the request.

When the interrupt logic receives both BDIN L and BIAKI L, it asserts VECTOR-TO-BUS
H to the vector selection switches. If the interrupt is a transmitter interrupt, the circuit also
asserts VECTOR BIT 02 H. This signal adds four to the base (receiver interrupt) vector that
is asserted by VECTOR-TO-BUS H. The circuit also negates BIRQ L.

VECTOR-TO-BUS H causes the I/O control logic to issue BRPLY L to the LSI-11. VECTOR-TO-BUS H and, if applicable, VECTOR BIT 02 H cause the bus transceivers to place
the selected vector on the LSI-11 bus lines.

The computer reads in the interrupt vector and then, as a result of receiving BRPLY L,

The interrupt logic negates VECTOR-TO-BUS H and, if applicable, VECTOR BIT 02 H.

The negation of VECTOR-TO-BUS H causes the I/O control logic to negate BRPLY L,
and the bus transceivers to remove the vector from the LSI-11 bus lines.

negates BDIN L. Shortly after this, it also negates BIAKI L.

An interrupt transaction does not require BBS7 L, DEVICE SELECT H, BSYNCL, or READ L. The
interrupt logic overrides the normal 1/O protocol.
5-19

VAN

BUS

Jl>

BDAL 00:15 L

INTERFACE

DEVICE DATA

CIRCUITS

BUS 00:15 H
D2

BBS7 L

V8 V7 V6 V5 V4 V3 V2
T

$—5

[

LVECTOR BIT 02
H

VECTOR

VECTOR-TOBUS H

SWITCH

fDCo03 INTERRUPT

BIRQ L

BDIN L

HIP

INTERRUPT
CONTROL
CIRCUITRY

RECEIVER | MITTER
|TRANS-

BIAKI L

INTERRUPTL NTERRUPT

CHANNEL

BIAKO L

LSI-11 BUS

cSR

|SILO ALARM ENABLE H

BIT

|SILO ALARM

ENABLE L

—
==

RCVR

[

|chANNEL

]

| RECEIVER

DONEH

| |

CIRCUITS

D11, D12

j4SILOALARM H
RECEIVER

INTERRUPT—2

LOW BYTE H

TRANS-

DEVICE DATA '

BUS 14 H

INTERRUPT | p GSR
ENABLE
HIGH BYTE H

MITTER

CIRCUITS

CSR BIT 06] H

ENABLE
MITTER

TRANS-

SE\SIIO%EHDATA

IA c

[CSRBIT 14

)
/

TRANSMITTER READY H

BINIT L

INITIALIZE L

RPLY L
BRPL

CONTROL
o

VECTOR-TO-BUS
H
-TO-

MK-0159

D4, D5

Figure 5-15

Interrupt Logic

5-20

BIRQ

BDIN

BIAKI

—

BRPLY

—

BDAL

BSYNC

(UNASSERTED)

BBS7

{UNASSERTED)

VECTOR

MK.0153

Figure 5-16

Interrupt Timing

A Silo Alarm interrupt can be distinquished from a Receiver Done interrupt by checking SAE bit

(CSR bit 12) when entering a service routine.
5.4.4

EIA Receivers
The DZV11 receives three modem signals for each of the four communicaton lines it interfaces. Carrier
Detect, Ring Indicator, and Received Data are received and converted from EIA levels to TTL levels.
The Carrier and Ring signals go to the modem status register. The received data signals go to the
RBUF (in the UARTS). Refer to Figure 5-17.

MODEM

CARRIER DETECT

CARRIER

EIA-TO-TTL

RING INDICATOR

RECEIVERS

RECEIVED DATA

( PART
OF MUX )

~——* MODEM

RING

STATUS
REGISTER

DATA
IN

MAINTEN
-

|ANCE

MODE DATA

SERIAL IN

—

SELECTOR

D13

D10

ONE OF FOUR CIRCUITS

RBUF
D14

(PART OF
UARTSs)
MK 0154

Figure 5-17

EIA Receivers

5-21

5.4.5 EIA Transmitters
The DZV11 can control up to three modem control signals for each of the four communications lines it
interfaces (Figure 5-18). Control bits from the TCR are converted from TTL levels to EIA levels to
drive modem control lines. For each line there is a single control bit that is always connected to data
terminal ready (DTR). These signals may be jumpered to also control request to send (RTS). If this

done, they may then be further jumpered to control forced busy (for Bell model 103E and 113B
modems with the forced busy option).
Data to be transmitted from the computer to the lines moves from the transmitter data buffer to the
EIA transmitters, where it is converted from TTL levels to EIA levels and placed on the lines.

TRANSMIT
CONTROL

{HIGH BYTE)

AN,
TENANCE

MODE

DATA

)

D14

DATA TERMINAL READY

REQ TO SEND
D6

MODEM

FORCED BUSY
TRANSMITTED DATA

SELECTOR

D10 I._
Figure 5-18

5.4.6

{>Cfi

TRANSMIT
DATA

D13

EIA TRANSMITTERS

D10y

ONE OF FOUR CIRCUITS

MK-0155

EIA Transmitters

UARTs

The DZVI11 uses four UART chips, one for each of the four communication lines. Each UART
performs part of the functions of receiver buffer (RBUF), transmitter data register (TDR), and line
parameter register (LPR) for the channel under its control. The RBUF takes serial data received by the
EIA receivers, strips off the start, stop, and parity bits, converts it to parallel data, stores it in the silo
buffer, and then places it on the device data bus. The TDR takes parallel data from the device data
bus, appends start, stop, and parity bits, converts it to serial data, and sends it to the EIA transmitters.
The LPR controls the speed, parity, and number of stop bits that the RBUF and TDR use. (Figure 519).

5.4.6.1 Setting Line Parameters — The various formats and speeds available are described in Paragraph 1.3.3 (Performance). The names and meanings of the LPR bits are listed in Table 3-4. The low
byte of the LPR is contained inside the UARTSs, and controls the data format. The high byte is
contained in the baud rate generator circuits, and controls the speed at which data is transmitted and
received.
When the computer addresses the LPR, the I/O control logic generates a load pulse. The load pulse
enables the LPR bits 00 and 01 to strobe the selected UART and baud rate generator. Bits 03 through
07 are latched into the UART to select the data format. Bits 08 through 11 are latched into the baud
rate generator to select the speed. Bit 12 enables the Receiver Clock signal to reach the UART.

5-22

BREAK
REGISTER

(HIGH
BYTE)
D10
DATA

BREAK

EIA

LOGIC

TRANS-

MITTERS

(LOW
BYTE)

D10

TDR

INTER-

FACE

STATUS

BUFFER

MULTIPLEXER

(HIGH

MAINT.

BYTE)

MODE

D12

DATA

SELECTOR

DATA

D10

(LOW
BYTE)
D3

FROM/TO

REGISTERS

RBUF

DEVICE DATA BUS

SILO

BUS

EIA

DATA

—

RECEIV-

FORMAT

(LOW

ERS

D13

BYTE)

D14

SPEED

(HIGH
BYTE)
D8
LPR

Figure 5-19

MK.0139

UARTs

5.4.6.2 UART Receiver Operation — Serial data coming in from the EIA receiver is applied to the
receiver section of the selected UART. The UART samples the serial input at the receiver clock rate
(16 times the data bit rate). The line is in a continuous marking state when idle. When a start bit
arrives, the UART detects the mark-to-space transition. It samples the line again at the time corresponding to the middle of the start bit. If the line is marking, the UART logic assumes that the first
sample was noise, and resumes sampling. If it finds that the line is still spacing, however, the logic
assumes it is receiving a start bit, and enters the data entry mode. In this mode, the UART shifts the
data serially into an internal register (Figure 5-20). If parity is enabled, the UART checks the total of
the received data bits plus the parity bit. (It checks for an even total if even parity has been selected,
and an odd total if odd parity has been selected.) A parity error causes the UART to set the parity
error flag bit in the high byte of the RBUF word.

5-23

BREAK
BITS
D10

UARTS

D13,D14

HOLDING REGISTER

‘DEVICE DATA BUlS/

EIA

BREAK

TRANS.

LOGIC

PARALLEL-TO-SERIAL

TRANSMITTER SHIFT REGISTER

|__

D10

D10
MAINT.
MODE

LOGIC

D10

SERIAL-TO-PARALLEL
RECEIVER SHIFT REGISTER

Eia

RECEIVERS|,
D7

SILO

BUFFER <

HOLDING REGISTER

D12

MK-0140

Figure 5-20

UART and Break Bit Registers

The UART checks the stop bit to see if it is marking. If the line is spacing instead, the UART sets the
framing error flag bit. If the line is marking, the UART logic assumes there is a valid stop bit.
About half way through the stop bit time, the UART transfers the received character data, the parity
error bit, and the framing error bit from the serial shift register to the holding register. At this time it
asserts the Data Available signal to the receiver control logic. If the previous character has not yet been
serviced by the receiver control logic, the UART sets the overrun error flag bit to indicate that the
previous character was lost.

The receiver control loads the contents of the RBUF (data and status) into the silo buffer for subsequent transfer to the computer. The receiver control circuit determines when and what type of
receiver interrupt to request.

5.4.6.3 UART Transmitter Operation - During idle time, the UART transmits a continuous marking
signal and holds the Transmitter Ready (TBMT) signal asserted. The transmitter control circuitry uses
this signal to determine when to initiate a transmitter interrupt request.

5-24

When the computer has data to transmit to a communication line, it uses a DATO or DATOB sequence to address the TDR and place the data on the bus lines. The low byte of the TDR word is
loaded into a holding register in the UART. When the data enters the holding register, the UART
negates TBMT. It then transfers the data in parallel from the holding register to a serial shift register

and reasserts TBMT. In the serial shift register, the UART attaches start, stop, and parity bits, as set
by the LPR. The assembled character is then shifted serially out to the EIA transmitter.

Because the transmitter, like the receiver, is double-buffered, it can be loaded with a second character

before the first one moves out.

Break (BRK) Bits

5.4.7

The transmission and reception of BRK bits are closely related to the transmission and reception of
data. A Break signal is a continuous spacing condition on the serial data line. When a UART receives
a Break signal, it interprets the continuous space as a character that is missing a stop bit. Therefore, it
sets the framing error flag. The program then determines how a framing error is handled.
A Break signal may be transmitted by interrupting the flow of serial data leaving the UART. The high
byte of the TDR may be thought of as a break register. It contains one BRK bit for each of the four
communication channels. Setting one of these bits inhibits the flow of data from the UART transmitter to the EIA transmitter, thereby causing a Break to be transmitted on the communication line.
Refer to Figure 5-20.

Speed and Format Control

5.4.8

The circuits controlling speed and format include the LPR, two dual baud rate generator chips, an
oscillator, and two addressable latches. Refer to Figure 5-21.

When the LSI-11 computer writes a word out to the LPR, the following events occur.

1.
2.

During address time, the bus interface and 1/O control circuitry decode the address and

produce a load pulse, LD LPR REGISTER L.

During data time, the load pulse enables two addressable latches to be addressed by bits 00
through 02. One latch routes the state of bit 12 to a gate that inhibits or enables the receiver
clock to the selected UART.

The other latch applies an enabling signal (CONTROL STROBE) to both the UART and
the baud rate generator chip section that control the communication line selected by bits 00
through 02.

3.
4.

Bits 03 through 07 are strobed into the selected UART to select the number of data bits; the

number of stop bits; and odd, even, or no parity.

Bits 08 through 11 are strobed into the selected baud rate generator chip to control the
amount by which the 5 MHz oscillator is divided to produce the UART clock signal. Table
4-1 and Paragraph 4.4.1 describe the baud rate selection scheme.

Thus, the LPR is formed by the latches located in the UARTS, baud rate generators, and addressable
latches.

5-25

LPR BITS

(ON DEVIDE

DATA BUS

LINES)

RECEIVER

CLOCK

CLOCK
—

ENABLE

TO THE OTHER THREE
ENABLING GATES.

LATCH

ey cE DATA BUS 12

ENABLE

LD LPR REG L

MASTER

5 MHZ

SCAN

OSCILLATOR

CLOCK

COUNTER

DEVICE DATA BUS 11
DEVICE DATA BUS 10

SPEED

CONTROL | DEVICE DATA BUS 09

]
BAUD RATE

) RECEIVER CLOCK

| TRANSMITTER CLOCK

GENERATORS

DEVICE DATA BUS 08
D8

r DEVICE DATA BUS 07

}(‘fi

DEVICE DATA BUS 06

%
UART
ONE OF

FORMAT J DEVICE DATA BUS 05

(FOUR)

DATA

CONTROL
DEVICE DATA BUS 04

DEVICE DATA BUS 03

D13,D14
DEVICE DATA BUS 02

LINE

DEVICE DATA BUS 01

SELECTION | pEviCE DATA BUS 00

CONTROL STROBE
LINE

ENABLE

CONTROL STROBES

LATCH

TO OTHER UARTS
f———

Figure 5-21

Speed and Format Control

5-26

MK-0152

5.4.9

Receiver Control

Receiver Scanner - The receiver scanner circuit samples the states of the Data Available (DA)

5.4.9.1

signals from the UARTSs. When it detects a TRUE condition, it generates a load pulse to transfer the
received data from the UART to the silo buffer. The sequence in which the receiver data available flags
are scanned and the characters loaded into the silo buffer is controlled by a 4-phase timing sequencer
and a group of multiplexers, demultiplexers, and counters.

The sequencer produces four timing signals (Figure 5-22). The signals times are designated Phase 1
through Phase 4.

LOAD
SILo

MASTER

SCAN

CLOCK

SILO LOAD H

DEMUX RCV DATA ENABLE 00-03)
|
DEMUX

w s RESET DA 00-03
5

\_FLOP

IN READY— ,_.\\\ 3\

D 1M

|
RCV SCAN LEAD A | DATA
AVAILABLE ]

GENERATOR
D11

REQUEST H

RCV SCAN LEAD B

—GRESS

—

FLIP

SILO LOAD

ENABLE

SILO

YARTS I'eE 0003 M Mux

00-03

c of_

—

BUFFER

o
MUX

OR 00-03> S0 S1

SRS

PE 00-03

MUX

SEQUENCER

Sa 0003

Mg a1

D11

READY

—

r—— b |

!__L—I__,

SERIAL IN

D13, D14

RD1-RD8

D11

D12

]

SILO

cou NTER .o

p11]

siLo
ALARM
FLIP

MK-0160

Figure 5-22

Receiver Control

5-27

FLOP

During Phase 1, a signal toggles the address generator to increment by one count. The two least
significant bits of the counter are used as a 2-bit address code, designated RCV SCAN LEAD A and
RCV SCAN LEAD B. These two signals address a multiplexer. The multiplexer selects the Data
Available line from the UART corresponding to the address code and applies it to a gate. The other

input to the gate is a Ready signal from the silo buffer. This signal is asserted when the silo buffer is
ready to accept data. If the Data Available signal is set and the silo buffer is ready, the gate asserts
SILO LOAD REQUEST H. The load request is applied to the load silo flip-flop.
RCV SCAN LEAD A and RCV SCAN LEAD B also address a demultiplexer. The demultiplexer
places an enabling signal (RCV DATA ENABLE) on the line to the UART addressed by the scan
leads. This is the same UART that is having its Data Available line sampled. The RCV DATA ENABLE signal enables the UART to place the contents of its receiver holding register on the lines to the
silo buffer (RD1 through RDS).

During Phase 2, the sequencer clocks the load silo flip-flop. If SILO LOAD REQUEST H is true, the
flip-flop sets. When the flip-flop sets, one output goes to the silo buffer as LOAD SILO H and strobes
received data from the UART into the silo buffer. At the same time the data enters, status information
is also loaded into the silo. Framing Error, Overrun Error, and Parity Error bits from the selected
UART are routed via multiplexers into the silo. The states of RCV SCAN LEAD A and RCV SCAN
LEAD B are loaded into the silo to indicate which communication line the received character came
from.

LOAD SILO H also goes to a latch in the sequencer. From there it passes through a demultiplexer and
asserts RESET DA to the selected UART. RESET DA clears the data available flag in the UART so

that another character may be received.

At the beginning of Phase 3 time, the zero output of the load silo flip-flop clocks the silo counter. The
silo counter increments by one count to keep a tally of the number of times the silo buffer has been
loaded. The silo counter counts only when SAE is set.
Phase 4 re-establishes the initial conditions of the scanner circuit for the next scan cycle.
5.4.9.2 Silo Buffer — The silo buffer comprises four 4-X 64-bit 3341 serial memory chips. The chips
are arranged as a 16-bit-long, 64-word-deep first in/ first out (FIFO) memory. Data is entered in the
“top” of the memory as described in the previous section. The In Ready signal means there is a
vacancy in the top word of the memory. Similarly, the Out Ready signal indicates there is a word in the
“bottom” of the silo waiting to be shifted out.

The buffer stores full RBUF words. Received character data is stored in the low byte, and receiver
status data in the high byte. The buffer shifts data in when it receives LOAD SILO H from the load silo
flip-flop, and it shifts data out when it receives UNLOAD SILO H from the unload control (Figure 523).

Data is shifted out as a result of either a Receiver Done interrupt or a Silo Alarm interrupt. The
presence of an Output Ready signal from each of the four chips asserts RECEIVER DONE H to the
interrupt logic. If the Receiver Done Interrupt Enable bit is set, the interrupt logic asserts the Interrupt
Request signal to the CPU.

If the Silo Alarm Interrupt Enable bit is set, RECEIVER DONE H is inhibited at the interrupt logic.
In this case, a receiver interrupt is not requested until the silo buffer has 16 characters ready. Setting
Silo Alarm Enable zallows the silo counter to increment each time the silo is loaded. On the sixteenth
count, the siio counter overflows, and the Carry Out signal sets the silo alarm flip-flop. The flip-flop, in
turn, asserts SILO ALARM H to the interrupt logic.

5-28

_ |

OIS H3d ng

A1Q0H A"GH

14IHS 1IN0

1S3N0D3YH WHV1H

__A__L11N1dII4dI0NimH0mSSsAN1ANAtQQQ0HHY—____AVIvAY01S,avo1H3AI303H3NOH vous

_ADYNVIS__a——_»—,“LLddIIHMSs11IINN00-___onNIAQVIHVOl|OIS4H,SLW2A0v1ivaa.ivor4lv3aX3TILoISOWQVOIONINSOWIHSWYIHILVNI
N~

QAVD3YH

——

_NLAIHS

5-29

3-4aLen]vyEo~'ym HA1SG0OH .uv4
NI AQH

sne

NN L0

1dYYILNI
21907

1O€9nI73ByS~n1g

When the interrupt request is acknowledged, the silo is unloaded. The unloading sequence is the same
for both types of receiver interrupts. It proceeds as follows.
1.

When data reaches the bottom of the silo, the Out Ready signals are gated together to

produce RECEIVER DONE H.

RECEIVER DONE H is applied to a latch. When a CPU input transaction (DATI) addresses the RBUF, READ RCV BUFFER H latches the state of RECEIVER DONE H.

The output of the latch is VALID DATA H. This signal conditions one input of a one-shot.

The trailing edge of READ RCV BUFFER H triggers the one-shot, which generates UNLOAD SILO H.

5.4.10

UNLOAD SILO H causes the silo buffer to shift out an RBUF word (character and status
data). The word is transferred via a multiplexer to the device data bus. From there the bus
transceivers place it on the LSI-11 bus. VALID DATA H is applied to the multiplexer along
with the output of the silo buffer, where it becomes bit 15 of the RBUF word.
Transmitter Control

The transmitter control circuit checks the transmitter control register to determine which lines are
enabled. It checks the UARTSs to determine which are ready to transmit, and it enables the UART
controlling the highest priority line to load data from the CPU.
The sequence begins with the Master Scan Enable signal from the CSR (Figures 5-24 and 5-25).
MASTER SCAN ENBL H triggers a 350 ns one-shot. The leading edge of the one-shot output clocks
a 4-bit latch. A True bit in the latch indicates that the corresponding line is enabled and that the
transmitter buffer empty flag is set for the UART controlling that line. Outputs from the latch are
applied to a priority encoder. The priority encoder generates a 2-bit code to represent the communication line number. When more than one channel is ready at the same time, the code always indicates
the one having the highest priority. (Line 03 has the highest priority; line 00, the lowest.) This code
addresses two multiplexers in the transmitter control circuit, and also goes to CSR bits 08 and 09. The
CSR bits TLINE A and TLINE B tell the program on which line the next character will be transmitted. The priority encoder also applies a Ready signal to the transmitter ready flip-flop when any of
the bits in the latch are true.

The trailing edge of the 350 ns one-shot output performs two functions.
1.

The zero (false) output clocks the transmitter ready flip-flop. Assuming a Line Enable bit is
set and a TBMT signal is true, the transmitter ready flip-flop asserts TRANSMITTER
READY H to the interrupt logic and the CSR. If enabled, a transmitter interrupt request is
initiated.

The transmitter ready flip-flop also disables the gate controlling the input to the 350 ns oneshot. This inhibits further clocking until the line can be serviced. At the same time, the signal
enables the contents of the line enable latch to enter a multiplexer.
2.

The second function of the trailing edge of the 350 ns one-shot is to trigger a 100 ns one-shot.
The output of the 100 ns one-shot disables the input to the 350 ns one-shot. The 350 ns oneshot is inhibited to prevent losing the latched-in line number.

5-30

TBMT 00

FROM
UART

| 1BMT 01

TRANS-

TBMT 02

MITTERS

TBMT 03

TRANSMITTER
READY FLIP FLOP

TCR
BITS

giTACBUS

)

00-03

VICE

LATCH

PRIORITY

—

'—*:)fl

L o

ENCODER

I—

CLK

MASTER SCAN

LOW BYTE H

TRANSMITTER
LINE B

TRANSMITTER]

CLR CLK

LINE A

—

ENBL H

350

MUX

100

STB

ONE

SHOT ||

gs
3V

SHOT

MUX

DEVICE

DATA BUS

MASTER SCAN ENBL L

MASTER

PULSE

03
LOAD IN

FORMING

CIRCUIT

—

¢ PROGRESS L

ST8 5 THRL 03 Ly
DEMUX

1/0

ONE

SHOT

HTHRLO2L | L
UART

CONTROL

THRL 01 L[

O——"—"|

LD TDR

TRANS-

MITTERS

THRL
00 L
[y
HRLOO
L
S1

- one
us

FROM

I
L
MK 0143

Figure 5-24

Transmitter Control

5-31

LOGIC

—

LD TCR

TRANSMITTER

1} —READYHL INTERRUPT

TO CSR
»BITS

08, 09

TRANSMITTER IDLE SEQUENCE

MASTER SCAN

INITIATE TIMING SEQUENCE

ENBL H

350 NS

ONE SHOT () H

—J

NOTE 1.
o re 5

100 NS

ONE SHOT (1) H

TRANSMITTER LOADING SEQUENCE
NOTE 1.

350 NS

ONE SHOT (1) H

)___.()

100 NS

(

)

ONE SHOT (1) H

{

TBMT-TCR

CONDITION

3.
NOTE

2__.(
> _—''v

TRANSMITTER
READY (1} H

PROGRAM RESPONSE

ONE SHOT
MCLEARS READY

INTERVAL

LD TDR
REGISTER H

ONE SHOT

1uSEC (1) H

1 uSEC

NOTE 4.

NOTE 5.

NOTES:
1.

CLOCK EDGE FOR SAMPLING (TBMT-TCR) CONDITIONS.

CLOCK EDGE FOR TRIGGERING 100 NS ONE SHOT AND

TRANSMIT READY SETS. TIMING SEQUENCE IS DISABLED.

~—

PRESENTING (TBMT-TCR) CONDITIONS.
4.

POSITIVE EDGE CLEARS TRANSMIT READY AND KEEPS

TIMING SEQUENCE DISABLED.
5.

FALLING EDGE INITIATES TIMING SEQUENCE FOR
NEW SAMPLE.

Figure 5-25

MK-0151

Transmitter Timing

5-32

The assertion of TRANSMITTER READY H ultimately results in the CPU performing a DATOB to
load data into the TDR. During address time, the /O control asserts load pulse LD TDR REGISTER
H. LOAD IN PROGRESS L from the I/O control strobes LD TDR REGISTER H into a demultiplexer. The demultiplexer output is a transmitter-holding register load pulse (THRL). It is routed to
the UART which controls the line addressed by the priority encoder. This enables the UART transmitter to load character data from the device data bus during data time.
When LD TDR REGISTER H returns to the negated state, the trailing edge triggers a 1 us one-shot.
The output of the one-shot clears the transmitter ready flip-flop. It also disables the gate controlling
the input to the 350 ns one-shot. The 350 ns one-shot is inhibited in order to allow the UART sufficient
time to drop its transmitter buffer empty flag before the circuit starts another scan cycle.
When the program is finished sending a message, it clears the Line Enable bit in the TCR. This occurs
after the enable bit and TMBT signals have already been latched in and TRANSMITTER READY H

has been asserted. It is, therefore, necessary to prevent the scanner from locking up on a line for which
there is no data. This is accomplished by clearing the transmitter ready flip-flop if it is set for a line
which is no longer enabled. The states of the Line Enable bits from the TCR are applied to a multiplexer. The bit corresponding to the line addressed by the priority encoder is passed to a pulse-forming
circuit. When the bit is cleared, a 50 ns pulse is formed. This pulse clears the transmitter ready flip-flop,
thereby negating TRANSMITTER READY H and allowing the 350 ns one-shot to fire for the next
transmitter scan cycle.
5.4.11

Maintenance Mode

The DZV11 can be switched to receive the data that it is transmitting (Figure 5-26). The four serial
data lines leaving the UARTS are applied to both a data selector and the EIA transmitters. The data
selector controls the inputs to the UART receivers. During normal operation, data from the EIA
receivers is routed through the data selector to the UART receivers. In the maintenance mode, the data
selector ignores the inputs from the EIA receivers. Instead, it routes the output data to the UART
receivers. This internal “wrap-around” feature is enabled by setting the Maintenance bit in the CSR.
Setting CSR bit 03 asserts MAINTENANCE H, which switches the data selector. External maintenance configurations are discussed in Chapter 6.

5.4.12

Power Supplies

In addition to the +12 V and +5 V available on the LSI-11 bus, the DZV11 also requires +3V, -9V,
and - 12V. The +3 V source is a voltage divider. The negative voltages are produced by two capacitive
charge pump circuits.

Each of the two charge pumps uses the following scheme.

An oscillator running at approximately 500 kHz switches a pair of drivers on and off (Figure
5-27).

5.5

The outputs of the drivers are capacitively coupled to a rectifier.

The negative-going output of the rectifier builds up a charge on a capacitor.

The charge is Zener-regulated back to the required negative voltage.

SUMMARY OF DEVICE REGISTERS

This paragraph contains drawings that relate the bits in each register to the circuits in which they are
used. Each bit is represented by a block containing the information shown in Figure 5-28. For a
description of the meanings and functions of the bits, refer to Chapter 3. For a discussion of their
usage, refer to Chapter 4.

5-33

~—

TDR
HIGH

BYTE

LOW
BYTE

SERIAL OUT

BREAK

00-03

LOGIC

e
e

TDR

D10

UARTS

DATA OUT 00-03

EIA

TRANSMITTERS

u-—__|

D10

N
RBUF
LOW
BYTE

MAINT.

SERIALIN

00-03

MODE
DATA

SELECTOR

D13,D14

D10

}
DATA IN 00-03

EIA

RECEIVERS
D7

CSR
BIT 03

MAINTENANCE H

MK-0144

Figure 5-26

Maintenance Mode

5-34

RECTIFIER

)

0sc

c RECTIFIER

L J (_q
______—-{—
DRIVERS | —

_____1JL(__
0sC

DRIVERS | 9

REGULATOR

REGULATOR ——*_12V A

REGULATOR —*_12V
B
+5V

-+ +3V

D1
T

3b3
=

MK 0145

Figure 5-27 Power Supplies

BIT NAME

BIT NUMBER

RO = READ ONLY
RW = READ/WRITE
WO = WRITE ONLY

LINE

ENAB

b9
CIRCUIT SCHEMATIC PAGE
ON WHICH BIT IS HELD.
MK.0183

Figure 5-28

Bit Labeling Scheme

5-35

CSR

DESTINATION

BITS

SOURCE

TRANSMITTER] ;FE‘QS\S/MH'TTER 5 RO
CONTROL

L
.

505

DEVICE

) DATA4

INTERRUPT

TIE

“Jroaic

RECEIVER

CONTROL

14 RW

LSI-111olINTERFACE BUS 1
T

MULTIPLEXER

TRDY

JsiLo aLARM| H |> RO

D11

—
7

DATA

12 RW

DEVICE

BUS

LS1-11 |+ INTERFACE|BUS 12
D2

—

D11

SAE

MULTIPLEXER

SILO ALARM ENABLE [RECEIVER

CONTROL

D11

TRANS-

MITTER

TRANSMITTER

|LINEB

T LINE|

CONTROL |TRANSMITTER
D9
>

LINE A

DEVICE

: gfigg‘e
DEVICE

]

ROl

RECEIVER

| o

BDQ

07 R _RO

DONE 1

06 RW|
RIE

05 RW

BUS

FACE

|paTA

DEVICE

BUS 04

MSE

04 RW|
CLR

DEVICE

D12

DATA
|BUSO5

LSI-11 o30S
o

MULTIPLEXER

T LINE|—l

DONE H
conTroL RECEIVER
[BREC
'

D12

[INTERRUPT

| LOGIC

l—- CONTROL
MASTER SCAN ENBL

TRANSMITTER

liNniTiALIZE

CONTROL

|- ciRCUIT

03 RW

BUS 03

MAINT [MAINTENANCE H

| D5]

MAINTENANCE
DATA

SELECTOR

00
MK-0158

Figure 5-29

Control and Status Register

5-36

DATA

|RECEIVER

ps|

D10

DESTINATION

SOURCE
VALID

DATAH

! OVERRUN
ERROR

OR 0003

RECEIVER

SILO

CONTROL

BUFFER

D12

FRAMING
ERROR
PARITY

ERROR

UARTS
RCV
LINE B

LINE
B D12
RCv
D11

D12|

A
LINE

RCV DATA 07

RD8

RX
LINE
A D12

RBUF

MULTIPLEXER

BUS
INTERFACE

D7p12

RCV DATA 06

RD7

SILO
RD6

BUFFER

RCV DATA 05

RBUF

05 RO
RBUF

RCV DATA 04

RD5

RCV DATA 03

RD4

RCV DATA 02

RD3

RCV DATA 01

RD2

D12

D1 2

RBUF

D12

RBUF

D12

02_ RO
RBUF

D2012

RBUF

D119
D13,
D14

RCV DATA 00

RD1

00 RO
RBUF
DO

| D12
Figure 5-30

D12

Receiver Buffer Register
5-37

D3
MK-0146

LSI-11

LPR

BITS

SOURCE

DESTINATION

DEVICE DATABUS 12

ENAB

SPEED WO,

DEVICE DATABUS 11

CODE

D
DEVICE DATA BUS 10

CODE

DEVICE DATA BUS 08

SPEED WO
CODE

A
07

oDD

ENB

DEVICE DATA BUS 05

sTtop

ODD PARITY L

PARITY ENABLE L

D13,D14

CHAR

~——

LGTH

B )13, D14
CHAR

LGTH

A D13,D14
02

DEVICE DATA BUS 01

UARTS

CODE

DEVICE DATA BUS 04

DEVICE DATA BUS 03

PAR wo

DEVICE DATA BUS 06

PAR

LSI-11

FORMAT

CONTROL

C
D8
SPEED WO
B

DEVICE DATA BUS 07

AND

SPEED WO
CODE

DEVICE DATA BUS 09

BUS
INTERFACE

SPEED

LINE WO
B

DEVICE DATA BUS 00_|

LINE

D13,D14

SPEED

AND

FORMAT

CONTROL

D8
MK .0147

Figure 5-31

Line Parameter Register

5-38

TCR

SOURCE

DESTINATION

BITS

DEVICE DATA BUS 11

DEVICE DATA BUS 10

DTR
2

DEVICE DATA BUS 09

DTR

DEVICE DATA BUS 08|

BUS

~—

DTR

DATA TERM RDY 03

DATA TERM RDY 02

D6
RW

EIA
TRANS-

DATA TERM RDY 01

MITTERS

DATA TERM RDY 00

D6j

INTERFACE

LSI-11 :>

| DEVICE DATA BUS 03

us 02
DEVICE
EVICE D DATA BUS

’

LINE
ENAB

|
|DEVICE DATA BUS 01

|DEVICE DATA BUS 00

LINE

ENAB

LINE

ENAB

TRANSMITTER

CONTROL

LINE
ENAB

D9
MK-0148

Figure 5-32

Transmit Control Register
5-39

MSR

SOURCE

DESTINATION

BITS

‘

11_RO

CARRIERO3H

'co

|||

3 by
'

CARRIER 02 H |10 RO

EIA

b7
2

RECEIVERS
CARRIERO!1

__RO

€O

'
CARRIER00H

]

08
RO
|%8 (ROl
|

~—

MULTI%

PLEXER

BUS
INTER-

FACE

LSI-11
05

04
D2

RING 03 H

~—

D7
EiA

RING 02 H

Ri2

RECEIVERS

D7
RING 01 H

D7
RING 00 H

Rio

MK -0149

D3
~

Figure 5-33

Modem Status Register
5-40

TDR

BITS

SOURCE

DESTINATION

—

3
12

DEVICE DATA BUS 11

BUS
INTERFACE

ohe

DEVICE DATA BUS 10

DEVICE DATA BUS 09

DEVICE DATA BUS 08

DEVICE DATA BUS 07

D10

grx WO

510

|
LOGIC

D10

0
07

BREAK

D10

TBUF WO
7

D13, D14

LSi-11

DEVICE DATA BUS 06

TBUF

D13,D14
DEVICE DATA BUS 05

tgur WO

5
D13,D14

TBUF

DEVICE DATA BUS 04

UARTS

D13, D14
DEVICE DATA BUS 03

DEVICE DATA BUS 02

rgyr WO
3

D13,D14

tgyr WO
2

___D13,D14]

DEVICE DATA BUS 01

[01 tgur WO
1

D13, D14
DEVICE DATA BUS 00

TBUF WO
0

D13, D14

D13,D14
MK.0150

Figure 5-34

Transmit Data Register
5-41

CHAPTER 6
MAINTENANCE

6.1

SCOPE

The DZV11 is maintained by periodically exercising its functions to verify operation, and by replacing
it with another module if it fails. Module-level repair is to be performed with automated test equipment at DIGITAL’s repair centers. This chapter focuses on defining the existence of a DZV11 malfunction. If a malfunction is detected, the failing module should be tagged and turned in to the
Logistics Group at the nearest DIGITAL Field Service Branch Office.

6.2

PREVENTIVE MAINTENANCE

There are no adjustments or other special requirements for the DZV11. Preventive maintenance consists of checking power supply voltages and running the exerciser program. This occurs as part of
normal system maintenance. Similarly, the DZV11 option should be included in any cleaning and
inspection effort performed on a system operating in a harsh or dirty environment. In summary, the
preventive maintenance for the DZV11 is accomplished by normal system-level preventive maintenance.

6.3
6.3.1

CORRECTIVE MAINTENANCE
General

The need for corrective maintenance may be recognized by a failure during normal operation or by
errors detected during system maintenance. Ideally, the DEC/X11 system exerciser program (MAINDEC-11-DXQLO) will indicate a failure by errors in one of its software modules. Once an error is
detected (by either the operating system or the exerciser), the diagnostic programs are run to further
isolate the failure. If the failure is isolated to a DZV11, the module is replaced. Refer to Chapter 2 for
installation information.

This chapter gives a brief description of the diagnostic programs and test modes. For details refer to
the program listings.

If it should become necessary to troubleshoot the DZV11 to the component-part level, consult the
program listing on the use of looping features. By using the program to keep the option in the failing
mode, and by using Chapter 5 and the circuit schematics to locate the related circuitry, a person may
be able to isolate the problem to a failing component. This type of maintenance is not recommended if
module replacement is possible.

6.3.2

Tools, Test Equipment, and Troubleshooting Aids

The minimum requirements for corrective maintenance are the programs listed in Table 6-1 and, if

required by the system hardware configuration, a screwdriver to remove cover panels. The first two
programs can test the DZV11 using the internal wrap-around feature described in Paragraph 5.4.11.

6-1

Table 6-1

Diagnostic Programs

Program

Code

Title

MAINDEC-11-DVDZA

DZVI1 ASYNC MUX PRT 1 OF
2

MAINDEC-11-DVDZB

DZV11 ASYNC MUX PRT 20OF 2

MAINDEC-11-DVDZC

DZVil CABLE & ECHO TST

MAINDEC-11-DVDZD
MAINDEC-11-DZITA

DZVI11 OVERLAY FOR ITEP
INTERPROCESSOR TEST PROGRAM (ITEP)

More thorough checks can be made by using the H329 and H325 test connectors. The H329 connects
data lines and control signals in a staggered loop-back configuration. This connector plugs into the
Berg header connector on the module, and allows the diagnostic program to check out the entire
board. The H325 test connector plugs into the modem end of the interface cable. It loops back data
lines and control signals without staggering the lines. This allows the program to test both the module
and the cable. These text connectors are illustrated in Figure 1-4 and their part numbers appear in
Table 2-1.
If it is necessary to troubleshoot to the component-part level, an ohmmeter, an oscilloscope, and a
quad extender card are also necessary. Before probing the module, make a thorough visual inspection
for damaged parts or printed circuits.

6.3.3
DEC/X11 Exerciser Program
The DEC/X11 system run-time exerciser consists of various software modules configured to run interactively. The exerciser is unique to the system it exercises, and must be reconfigured if options are
added to the system. Unlike the diagnostic programs, which thoroughly test the option in isolation, the

exerciser tests the option’s ability to run in the system environment. It does this by performing a
representative sample of the option’s functions while also testing other system components.
DZV11s that are shipped as part of systems are already included in the system exerciser. Those shipped
as separate orders are not covered by the system exerciser, and DEC/X11 must be reconfigured to
accommodate them. To build DEC/X11, refer to the DEC/X11 User’'s Documentation and Reference
Guide (DEC part number MAINDEC-11-DXQBA).
The DZV11 module of DEC/X11 is titled, “DZBA DEC/X11 DZV11 ASYNCHRONOUS MODULE TEST” and is found in the DXQLO library (DEC/X11 LSI OPTIONS LIBRARY No. 1).

6.3.4

XXDP Diagnostic Programs

6.3.4.1

General- The diagnostic package consists of three stand-alone programs (DVDZA, DVDZB,
and DVDZC) and an overlay for the interprocessor test program (DVDZD). To run the interprocessor
test, it is necessary to first load the ITEP monitor (DZITA). These programs are available on the
media listed in Table 6-2. Details of the programs may be found in the program listings. This paragraph presents general procedures and information.

6-2

Table 6-2

Multimedia Assignments

Media

Title

Part Number

Paper Tape

DZV11i DOC/PT KIT

ZJ251-RB

Floppy Diskette

RXDP #43 LSI #4

AS-C638n*-MC

CZZZCnn XXDP DIAG PKG3
CVZZDnn LSI-11 RKDP1 DIAG PKG
CZZRAnn RMDP DIAG PKG

AN-9695n-MC
AN-9696n-MC
AM-C751n-MC

Disk Packs

(RKO05)
(RKO05)
(RKO06)

*The n in the titles and part numbers indicates the revision level, and is subject to updating. For example,
CZZZCVO0 indicates Rev. V, patch 0 of CZZZC. Similarly, AN-9695V-MC indicates Rev. V in the part number.

6.3.4.2 Maintenance Modes — Figure 6-1 illustrates the data paths for the maintenance modes. The
two basic programs (DVDZA and DVDZB) can be run in the internal, staggered, or external modes.
The cable and echo test (DVDZC) can be selected either to loop characters from the program out
through the test connector and back to the program, or else to loop characters from a test console
through the DZV11 and back out to the test terminal. The interprocessor test program requires that
another CPU be running the test along with the LSI-11 under test. The other CPU may be a local
system, or a remote system (such as the turnaround system at DIGITAL in Maynard, Massachusetts).
Refer to Figure 6-2. In this test, the two processors communicate to check the hardware from end to
end. It is possible, however, to operate the program with an H325 loopback connector instead of
another processor.

6.3.4.3 Setup Procedures - Running the internal loopback test requires no setup. The loopback function is enabled by CSR bit 03. The staggered loopback test requires that the module header connector
be removed and replaced by a H329 test connector. The preferred method of doing this is to power
down the computer, unplug the DZV11 module, and switch from the interface cable to the H329 test
connector. The module is then reinstalled, taking care not to snag the components on anything, and
the computer is powered up.

The external test requires that the far end of the BC11U interface cable be disconnected from the
modem or terminal. Plug the H325 test connector into the modem-end of the cable.
Setup for the cable test also requires an H325, as indicated in Figure 6-1. The echo test requires a
terminal connected to the DZV11. This may require a null modem, depending on the type of terminal.
Setup for the interprocessor test varies depending on the equipment available.

6.3.4.4 Software Switch Register - The LSI-11 uses location 176 for a switch register instead of front
panel swtiches. To change the operating parameters, load the program and then use the ODT slash
command to open location 176. Refer to the applicable program listing for a definition of bits. Assemble the corresponding octal number and enter it into location 176. Then start the program at
location 200.

6-3

3
Dzv-11

INTERNAL

_—

H329

DzZvil

STAGGERED

LSI11BUS &

¢ LSI-11BUS

LSI-11 BUS

4 LSI-11BUS

)

DzV11

EXTERNAL (DVDZA or DVDZB)
or CABLE (DVDZC only)

v
e
-

NULL*
MODEM

TEST

TERMINAL

BC11U

DzVi1

ECHO (DVDZC only)

* ANULL MODEM, SUCH AS AN H312, MAY BE NECESSARY,
DEPENDING ON THE TERMINAL USED FOR TEST.

Figure 6-1

Maintenance Mode Data Flow

6-4

MK-0177

REMOTE LINK

MODEM
P

['_

—_

DZV11

i
»

+———— <
N

| MODEM

NULL

\‘.

mooem |—T ——--*% D

)

LOCAL LINK
\D H325

* BOTH PROCESSORS MUST BE RUNNING DZITA.

Figure 6-2

MK-0178

E
5

Interprocessor Test (ITEP)

The software switch register may be accessed while the program is running. Type a CONTROL G to

stop the program and open the switch register.

6.3.4.5 Auto-Sizing - The two basic tests (DVDZA and DVDZB) have auto-sizing capabilities, and
may therefore be run without modification of the switch register.

The auto-sizer routine detects all DZV11 device and vector addresses within the floating address and
vector area. The values of the other parameters are by default set for 19.2K baud, internal loopback,
and the testing of all four lines. These values are stored in a status table in locations 1500 through 1740
(Table 6-3). They are printed by the console terminal during the test.

6.3.4.6 Parameter Inputs and Dialogue - The DVDZA and DVDZB diagnostics may be run with
parameters specified by the operator. To do this, set bit 00 in the software switch register and then start
the program at location 200. The program responds with a series of questions.
1st CSR ADDRESS (160000:163770):

Answer this question by typing in the address of the DZV11 CSR at which you wish testing to begin.
Follow all answers with a carriage return.

1st VECTOR ADDRESS (300:770):

Type the vector of the DZV11. Note that all the DZV1ls must be contiguous for both address and
vector locations.

Table 6-3

Typical Map of DZV11 Status*

Location

Contents

1500

160100

1502

000300

Meaning

CSR address of first DZV11

in system.

Receiver interrupt vector
for first DZV11 in system.

1504

000017

TCR bit representation of
active lines to be tested.

1506

017470

LPR bits representing the
following: receiver enabled,
19.2K baud, 8 bits per
character, and 2 stop bits.

1510

000000

Indicates the selected maintenance mode, where:
000000 = Internal

000200 = External with H325
100000 = Staggered with H329
*This table is an example. Consult the program listing for details.

MAINTENANCE MODE

(EXTERNAL (H325) (E))
(INTERNAL (DZCSR03=1) (I))
(STAGGERED (H329) (S))
Type an E, I, or S, as appropriate. If running external, all selected lines must be terminated by H325
test connectors.

# OF DZV11s (IN OCTAL) (1:20):
Type the total number of DZV11s to be tested.
Other parameters (e.g., baud rate) that are not included in the opening dialogue may be entered via the
software switch register. All extra parameters are assigned to all DZV11s in the system. The program
run time is approximately 1.5 minutes on the first pass and 2.5 minutes on subsequent passes. Run at
least three error-free passes.
Operation of the cable and echo test (DVDZC) always requires an opening dialogue. Special switch
settings, however, are not required for normal operation. Start the program and respond to the questions with an answer followed by a carriage return
VECTOR ADDRESS -

Type the vector of the DZV11 under test.

6-6

CONTROL REGISTER ADDRESS Type the CSR address of the DZV11 under test.
WHICH TEST? ECHO OR CABLE (E OR C)
Type E or C, as required.
BAUD RATE -

Type one of the following: 50, 75, 110, 135, 150, 300, 600, 1200, 1800, 2000, 2400, 3600, 4800, 7200, or
9600.
LINE -

Type the number of the line that has the H325 test connector on it. The lines are numbered 0, 1, 2, 3.
At this point, the test begins.
Cable Test
If the cable test (C) was selected, the system prints:
CABLE TEST
The cable text executes in approximately 15 seconds at 9600 baud. It prints an end-of-pass message
after each pass. To change lines, strike any key on the console terminal while the program is running.
The system responds with:
LINE:

At this point, change the H325 test connector to another line and type the new line number. The
system prints:
CABLE TEST
and continues.

Echo Test

If the echo test (E) is selected when the program asks which test, the subsequent baud rate and line
questions are answered the same way. After the line number is typed, the system prints:
TERMINAL ECHO TEST

on the console terminal, and prints:
THE QUICK BROWN FOX JUMPED OVER THE LAZY DOGS BACK 0123456789

on the DZVI11 terminal. To have this message printed continuously, type a CONTROL G on the

console terminal while the message is being printed by the DZV11 terminal. The program prints a
prompt character on the console terminal and waits for a new switch register setting. Set the switch
register to 377 to have the program output on the quick brown fox message continuously.
To return to the normal flow of the diagnostic, type a CONTROL G and change the switch register to
something other than 377.

6-7

The console terminal prints:

TYPE A CHAR. ON DZV11 TERMINAL

At this point, any printable character typed on the DZV11 terminal is echoed back to that terminal.
If a CONTROL C is typed on the DZV11 terminal, the program prints the end-of-pass message on the
console and then resumes with the quick brown fox message on the DZVI11 terminal.
To change lines, type any printable character on the console terminal. The system prints:
LINE:

and waits for a response. Plug the next line into the DZV11 terminal and continue until all the lines
have been tested. Refer to the listing for explanations of error printouts.

6.3.4.7

Functional Description - This paragraph briefly describes the diagnostic programs used with

the DZV11. For a more detailed treatment, refer to the program listings.

DVDZA - This is the first of a 2-part series used for basic option checkout. It exercises the read /write
bits of the registers, performs simple transmission and reception exercises for each line, and verifies the
interrupt capabilities of the option (Table 6-4).

Table 6-4
Test

Number

DVDZA Tests

Functions

Proves the bus reply response during a read or write to the following device registers:

CSR, RBUF, TCR, and MSR.

Proves that bit CLR can be set, and that it will clear by itself.

Verifies that the read/write bits of the CSR can be set. Then verifies that they can be
cleared. Also verifies that after being set again, they can be cleared by a Master Clear.
The bits tested are: MAINT, MSE, SAE, RIE, and TIE.

Tests that all of the TCR bits can be set, cleared, and cleared by a Master Clear. Also

Verifies that RDONE, TRDY, TLINE B, TLINE A, and SA are read-only. Tests that

Tests that the following CSR bits are read-write: TIE, SAE, MSE, and MAINT.

Performs reset testing. Also tests read-only bits in RBUF and write-only bits in LPR.

tests that the DTR bits can be set, cleared, and cleared by a RESET.

TRDY is zero until a line is selected and MSE is set.

Checks that setting CLR in the CSR will clear these bits.

6-8

Table 6-4

DVDZA Tests (Cont)

Test

Number

Functions

Performs reset testing. Also tests read-only bits in the MSR and write-only bits in the
TDR.

Verifies that setting DTR causes CO and RI to set under the following circumstances:
1.
2.

For the same line if in external mode
For the staggered line if in staggered mode.

Lines are staggered as follows: line 0 with line 1, line 2 with line 3. This test is run only if
an H325 or H329 is connected to the DZV11 under test.
N

Verifies that TRDY is set when a line is ready to be loaded. Verifies that the line
specified by TLINE A and TLINE B in the CSR corresponds to the line selected in the
TCR.

Transmits one character and receives one character on one line at a time. The character
is 252. All selected lines will be turned on. This is the first time any data is checked in
the receiver. Using switch 09 with this test establishes a tight scope loop that transmits
a steady stream of characters.

Clears RX ENAB in the LPR for each line to verify that each receiving line can be
disabled. This test also verifies that the silo can be emptied by setting CLR in the CSR.

Proves that the transmitter transmits characters and the receiver receives characters.
One line at a time is tested, based upon valid lines. This is the first point at which all
data is tested.

Exercises one line at a time to prove that:
1.
2.
3.

17.

The transmitter BRK bit works.
The receiver can flag framing errors.
The receiver can flag parity errors.

Verifies that the DZV11 does not interrupt while the processor status does not allow
interrupts. Also checks that the DZV11 can interrupt when the processor status does

allow interrupts.
20

Verifies that the receiver interrupts before the transmitter, even when the transmitter
was enabled first.

DVDZB - This program is the second of the two basic option diagnostics. It exercises the transmitters
and receivers in all possible operating modes and at all possible data rates. Error conditions are induced and the option is checked for the ability to recognize these errors (Table 6-5).

Table 6-5
Test
Number

DVDZB Tests

Functions

Verifies OVRN ERR and SA one line at a time, based upon valid lines. As each of the
first 16 characters are sent, Silo Alarm is tested to be cleared. On the 16th character, the
program tests for Silo Alarm to set. Then the entire silo is filled and an overrrun error is

expected on the 65th character.

Using switch 09 for this test sends 20 characters on the line previously selected. This
occurs continuously while SW09 = 1.

Tests that SAE inhibits interrupts. Sets RIE and checks that SA causes an interrupt on
the 16th character. Tests all selected lines one at a time.
Interrupt test on the transmitter and receiver. Runs all qualified lines at maximum
speed.

DZV11 relative timing test.

Each selected line, one at a time, runs 16 characters at all baud rates, and then the
highest baud rate with all character lengths. Each successive parameter decreases in
time from the previously selected parameter. The time is checked aginst the previous
time. The parameters are:

Eight bits per character plus two stop bits at 50, 75, 110, 134.5, 150, 300, 600,
1200, 1800, 2000, 2400, 3600, 4800, 7200, and 9600 baud.

Five, six, and seven bits per character with two stop bits and at 19.2K baud.
Each line completes all of the checks before the next line is tested.

Checks parity errors in staggered mode only. All selected lines are enabled simultaneously. Tests for even parity on odd lines and odd parity on even lines. Then it checks
the reverse. The test verifies that PAR ERR can be set.

DVDZC - This program verifies the cable interface connection between the module and the EIA
connector. The diagnostic includes a cable test, an echo test, and a test of modem control signals.

The cable test transmits a binary count pattern via the test connector to the receivers. The data flow is
from the program out through the interface cable to the test connector, and back.
The echo test accepts one character at a time and retransmits that character on the same line. The data
flow is from a test terminal in through the interface cable and DZV11 to the program and back out to
the terminal.

The third test verifies that setting DTR for a given line causes CO and RI to set. Jumpers W1, W2, W3,
and W4 must be installed for this test.

6-10

6.3.5

Interprocessor Test (ITEP)

The interprocessor test program (ITEP) verifies the operation of the DZV11 by using it in a communications link with another processor. The other processor may be on an LSI-11 or PDP-11 system at
the same location as the system under test, or it may be in a remote communications test center.
DVDZD is the DZV11 overlay of the test program. It must be run along with DZITA-D, the monitor
program.

ITEP has four testing modes. The overlay performs the following functions in the four modes.

Internal Loopback Mode
L.

Establishes the modem connection.

Waits to receive a message terminated by the receive terminating character (001).
Verifies the data against the data selected by SW09 and SW10 (SWO07 = 0).
Transmits the data selected by SW09 and SW10 (SWO08 = 0), or transmits the received data
(SWO08 = 1).
Returns to monitor for “END PASS” (SW04 = 1), or goes to step 1 (SW04 = 0).

The overlay establishes the modem connection.
Transmits the selected data.
Enables the receiver.
Waits for the message to be received.
Verifies the data (SW07 = 0).

Returns to the monitor for “END PASS” (SW04

AN
o ol h

External Loopback Mode (Full-Duplex Only)

1) or goes to step 1 (SW04 = 0).

NP WD -

One-Way-In Mode

The overlay establishes the modem connection.
Enables the receiver.
Waits for the message to be received.
Verifies the data (SW07 = 0).
Returns to the monitor for “END PASS” (SW04

1) or goes to step 1 (SW04 = 0).

RN
=

One-Way-Out Mode

The overlay establishes the modem connection.
Enables the transmitter.
Transmits the selected data.

Returns to monitor for “END PASS” (SW04 = 1) or goes to step 1 (SW04 = 0).

6-11

6.3.5.1 Starting ITEP- ITEP requires a complete communications loop (Figure 6-2). Ensure that a
loop is established with compatible equipment. The variable parameters must be the same in each of
the two processors. The mode must be one of the options listed in Table 6-6. The system that is to
receive data first should be loaded and started first. If the modem being used on this system has an
automatic answer feature, it should be enabled. The system that is to transmit first should then be
loaded and the connection established. If the LSI-11 line clock is to be used, it should be enabled prior
to program execution. The load address is 200. Refer to the program listing for details regarding
restrictions, error messages, and optional selections.

Table 6-6

Valid Mode Combinations

CPU No. 1

CPU No. 2

One-Way-Out

One-Way-In

One-Way-Out

External Loopback

Internal Loopback

External Loopback

(full-duplex)

External Loopback

(full-duplex)

External Loopback
(full-duplex with
H325 test connector

on end of modem
cable)

6.3.5.2

Console Dialogue- After the program has been started, the dialogue for input parameters

proceeds as follows.

The program types the name of the overlay, followed by a question mark. If you wish to set
up just the indicated overlay, type a carriage return.

The program types the default address of 160010. Type a carriage return if the default
address is correct for the DZV11. If not, type the actual CSR address.

The program types the default vector address of 300 and a question mark. Type a carriage
return to use the defult vector. If using a different vector, type the actual vector.

The program types 200 as the priority setting. For the LSI-11,

this indicates that the proces-

sor will acknowledge interrupts. For a PDP-11, this indicates priority level 4. Type a car-

riage return to use this priority. If a different priority is required on a PDP-11, type the
appropriate code (240 for priority level 5, 300 for priority level 6, etc.).

6-12

~—

Next the program types the default value for parameter no. 1 of 011070 and a questiori
mark. Type a carriage return to use the default value. To select a different value, refer to

Tables 6-7 and 6-8.

NOTE

If any of the values in items 2 through 5 are changed,

the new value becomes the default value for sub-

sequent restarts of the program.

Table 6-7

Bits 0, 1
Bits 3, 4
Bit 5
Bits 6, 7
Bits 8-11
Bit 12

Line number being used; default setting is for line 0.
Character length; default is 8 bits.
Stop bit count; default is 2 stop bits.
Parity enable and select; default is no parity.
Baud rate select; default is 110 baud.
Receiver on (this should always be set).

Table 6-8

~—

Meaning of Parameter No. 1

Parameter No. 1 Examples

Value*

Baud Rate

10070
10470
11070
11470
12070
12470
13070

50
75
110
134.5
150
300
600

1200

13470

1800
2000
2400
3600
43800
7200
9600

14070
14470
15070
15470
16070
16470
17070

*These examples set the receiver for line 0, set the
baud rate as listed, and set the format for 8 bits
per character with 2 stop bits and no parity. For
definitions of the other possible settings, refer to
Table 3-4.

6-13

6.3.5.3

Operational Switch Settings - The program instructs the operator to set console switches. On

a PDP-11 with front panel switches, set the switches according to Table 6-9. On an LSI-11, modify the

contents of the software switch register (location 176) according to Table 6-9. If no change is desired,
type a carriage return. If an error is made while modifying the software switch register, CONTROL U
allows re-entering the correct value. The contents of the switch register can be changed during program
run time by typing a CONTROL G and then entering a new value.

Table 6-9

SWI5

Halt on error

SwWi4

Single pass

Operational Switch Settings

SW14 has no effect if SW04 = 0.
SW13

Inhibit error typeouts

Swi2

Inhibit all typeouts except errors. If SW12 = 0 and SW04 = 1, END PASS is typed and
transmitted /received data is typed.

SWi11

Use previously specified data.

SW10

Data select (with SW(9)

SWQ09

Data select (with SW10)
00 =1
Get data from operator.
01 =1

Test message no.l ($A quick brown fox)

10=1
11
=1

Test message no.2 ($B numerics)
Test message no.3 ($C comtest/quick brown fox/numerics)

SWO08

Transmit received data (internal loopback mode).

SWo7

Do not test received data.

SW06

Monitor transmitted data on console terminal.*

SWO05

Monitor received data on console terminal.*

SWo04

Return to monitor for END PASS.
When SW04 = 0, program loops in the overlay, never returning to the monitor.

SWO03

Internal loopback mode

SW02

External loopback mode

SWO01

One-way-in mode

SW00

One-way-out mode

*In many cases, not all the data appears on the console terminal. This is especially true when the communications interface is running at a faster baud rate than the console, but even at equal or slower baud rates, not
all characters may appear on the console.

6-14

When the communication link is established and the dialogue has been completed, start the program
by using the CONTINUE switch (on a PDP-11) or the ODT P command (on an LSI-11).

6.3.5.4 Testing - If one-way-in or internal loopback modes are selected, the program sets Data Terminal Ready and waits for data. If one-way-out or external loopback modes are selected, the program
sets Data Terminal Ready and then waits for the Carrier bit before attempting to transmit data.

NOTE
For example, to test a line in external loopback
mode with message no. 3, use a switch setting of
3024.

6.3.6

Manual Tests
This paragraph contains several short tests that can be performed using the hardware ODT commands. The examples given here assume that the reader is familiar with the use of ODT and that the
DZV11 CSR address is set for 160010. The letter n is used to indicate 2 number that may vary. For an
explanation of ODT commands, refer to 1977-78 Microcomputer Handbook, Section 2, Chapter 2.

This test verifies that the CLR bit will clear the CSR and the low byte of the TCR.

@160010/000000 <LF>

Open the CSR

160012 /0nnnnn <LF>

Open the RBUF.

160014/000000 <LF>

Open the TCR.

160016/000000 <CR>

Open the TDR.

@160010/000000 10050 <LF>

Open CSR; enter bits.

160012/0nnnnn <LF>
160014/000000 7417 <LF>

Open TCR; enter bits.

160016 /000000 <CR>
@160010/111450 20 <LF>

Open CSR; set device clear.

160012 /0nnnnn <LF>
160014/007400 <LF>

Observe that low byte of TCR is cleared.

160016/000000 <CR>

The MSR may contain a value of 007417 if the
H329 is connected.

@160010/000000

Observe that CSR is cleared.

6-15

This test makes a basic check of the transmitter scanner. It performs a Master Clear, sets the
TCR bit for line 3, and then verifies that line 3 appears in the CSR. It clears the TCR bit for
line 3 and then checks that the line numbers in the CSR are clear.

@160010/000000 20 <CR>

Set Master Clear.

@/000000 50 <LF>

Set MSE and MAINT.

160012/0nnnnn <LF>
160014 /000000 10 <t
>

Set TCR bit 03.

]

Read CSR for TRDY set and Tx line

160010/101450 <LF>

160012 /0nnnnn <1t
>

160012 /0nnnnn <LF>
160014/000010 0 <1>

Clear TCR bit 03.

160012/0nnnnn <1t>
160010/000050

Read CSR for TRDY and TLINEs cleared.

To perform the same test on line 2, proceed as follows.

@160010/000000 20 <CR>

Set Master Clear.

@/000000 50 <LF>

Set MSE and MAINT in CSR.

160012/0nnnnn <LF>
160014 /000000 4 <1>

Set TCR bit 02.

160012 /0nnnnn <1t>
160010/101050 <LF>

Check CSR for TRDY set and Tx line = 2.

160012/0nnnnn<LF>

160014/000004 0 <1t>

Clear TCR bit 02.

160012 /0Onnnnn <1t
>
160010/000050

Check CSR for TRDY and TLINEs cleared.

6-16

To perform the same test on line 1, proceed as follows.
@160010/000000 20 <CR>

Set Master Clear.

@ /000000 50 <LF>

Set MSE and MAINT in CSR.

160012 /0nnnnn <LF>
160014 /000000 2 <1>

Set TCR bit 01.

160012 /Onnnnn <1>

160010/100450 <LF>

Check CSR for TRDY set and Tx line = 1.

160012/0nnnnn <LF>
160014/000002 0 <1t>

Clear TCR bit 01.

160012/0nnnnn <1>
160010,/000050

Check CSR for TRDY and TLINE:s cleared.

To perform the same test on line 0, proceed as follows.
@160010,/000000 20 <CR>

Set Master Clear.

@/000000 50 <LF>

set MSE and MAINT in CSR.

160012/0nnnnn <LF>
160014 /000000 1 <1>

Set TCR bit 00.

>
160012 /Onnnnn <1
N

160010/100050 <LF>

Check CSR for TRDY set and Tx line = 0.

1600012/0nnnnn <LF>
160014/000001 0 <1t>

Clear TCR bit 00.

160012/0nnnnn <1t>
160010,/000050

Check CSR for TRDY and TLINEs cleared.

6-17

This next test checks that line 3 is the highest priority line when all lines are enabled at once.

It checks that line priority goes from 3 to 0.

@160010/000000 20 <CR>

Set Master Clear.

@/000000 50 <LF>

Set MSE and MAINT in CSR.

160012 /0nnnnn <LF>
160014/000000 17 <t>

Set TCR bits for lines 3, 2, 1, and 0.

160012/0Onnnnn <1t>
160010/101450 <LF>

Check CSR for TRDY set and Tx line = 3 (highest priority line).

160012 /0nnnnn <LF>
160014/000017 7 <1t>

Clear only TCR bit 3.

160012 /0Onnnnn <1t>
160010/101050 <LF>

Check CSR for TRDY set and Tx line = 2 (next
highest priority).

160012 /0nnnnn <LF>
160014 /000007 3<
t>

Clear TCR bit 02.

160012 /0Onnnnn < 1>
160010/100450 <LF>

Check CSR for TRDY set and Tx line = 1 (third
highest priority).

160012/0nnnnn <LF>
160014/000003 1 <1>

Clear TCR bit 01.

160012/0nnnnn<
1>
160010/100050 <LF>

Check CSR for TRDY set and Tx line = 0 (lowest priority).

160012/0nnnnn <LF>

160014/000001 0 <1>

Clear TCR bit 00.

160012 /0nnnnn < 1>
160010/000050

Check CSR for TRDY and TLINEs cleared.

6-18

This test checks the receiver without using the transmitter scanner. The BRK bit is set and
the RBUF is tested to see that it contains an all-zero character and a framing error.
@160010/000000 20 <CR>

Set Master Clear.

@ /000000 50 <LF>

Set MSE and MAINT in CSR.

160012/0nnnnn 17470 <LF>

Load LPR with 19.2K baud, 8-level, 2 stop bits,
and line 0.

160014,/000000 <LF>

160016/000000 400 <CR>

Set Break bit in TDR for line 0.

@160010/000250 <LF>

Read CSR for RDONE set.

160012/120000 < 1>

Check RBUF for Data Valid and FRAM ERR
set, for RX line = 0, and for all zeros in data
bits.

160010/000050 <LF>

Check CSR for RDONE cleared.

160012,/020000

Check RBUF for Data Valid cleared.

To perform the same test on line 1, proceed as follows.
@160010,/000000 20 <CR>

Set Master Clear.

@ /000000 50 <LF>

Set MSE and MAINT in CSR.

Load LPR with 19.2K baud, 8-level, 2 stop bits,

160012/0nnnnn 17471 <LF>

and line 1.

160014/000000 <LF>
160016,/000000 1000 <CR>

Set Break bit in TDR for line 1.

@160010/000250 <LF>

Check CSR for RDONE set.

160012/120400 < 1>

Check RBUF for Data Valid and FRAM ERR
set, for RX line = 1, and for all zeros in data
bits.

160010/000050 <LF>

Chgek CSR for RDONE cleared.

160012/020400

Check RBUF for Data Valid cleared.

6-19

To perform this test on line 2, proceed as follows.
@160010/000000 20 <CR>

Set Master Clear.

@ /000000 50 <LF>

Set MSE and MAINT in CSR.

160012/0nnnnn 17472 <LF>

Load LPR with 19.2K baud, 8-level, 2 stop bits,

and line 2.
160014,/000000 <LF>
160016,/000000 2000 <CR>

Set Break bit in TDR for line 2.

@160010/000250 <LF>

Check CSR for RDONE set.

160012/121000 < 1>

Check RBUF for Data Valid and FRAM ERR

set, for RX line = 2, and for all zeros in data
bits.
160010/000050 <LF>

Check CSR for RDONE cleared.

160012/021000

Check RBUF for Data Valid cleared.

To perform this test on line 3, proceed as follows.
@160010/000000 20 <CR>

Set Master Clear.

@ /000000 50 <LF>

Set MSE and MAINT in CSR.

160012 /0nnnnn 17473

Load LPR with 19.2K baud, 8-level, 2 stop bits,
and line 3.

160014/000000 <LF>
160016/000000 4000 <CR>

Set Break bit in TDR for line 3.

@160010/000250 <LF>

Check CSR for RDONE set.

160012/121400 <1
>

Check RBUF for Data Valid and FRAM ERR
set, for Rx line = 3, and for all zeros in data bits.

160010/000050 <LF>

Check CSR for RDONE cleared.

160012/021400

Check RBUF for Data Valid cleared.

6-20

This test transmits and receives several characters on line 0. It uses 8-level with 2 stop bits at
19.2K baud in maintenance mode.

@160010/000000 20 <CR>

Set Master Clear.

@ /000000 50 <LF>

Set MSE and MAINT in CSR.

160012 /0nnnnn 17470

Set LPR bits for 19.2K baud, 8-level, 2 stop bits,

160014/000000 1 <1>

Set TCR bit 00.

line 0.

>
160012/0nnnnn <1

Check CSR for TRDY set and Tx line = 0.

160010/100050 <LF>
160012 /0nnnnn <LF>
160014/000001 <LF>

Load octal 377 into TDR.

>
160016/000000 377 <1
160014/000001 <1>

Check RBUF for Data Valid set, for OVRN
ERR, FRAM ERR, and PAR ERR clear, for
Rx line = 0, and for the data to be 377.

160012/100377 <1>

160010/100050 <LF>

Check CSR for TRDY set and RDONE cleared.

160012/000377 <LF>

Check RBUF for Data Valid cleared.

160014/000001 <LF>

Load octal 252 into TDR.

160016,/000000 252 < 1>
160014,/000001 < 1>

Read RBUF for Data Valid set, the error bits

160012/100252 < 1>

clear, Rx line = 0, and the data to be 252.

160010/100050 <LF>

Check CSR for TRDY set and RDONE cleared.

160012/000252 <LF>

Read RBUF for Data Valid cleared.

160014/000001 <LF>

6-21

160016,/000000 125 < 1>

Load octal 125 into TDR.

160014,/000001 < 1>
160012/100125 < 1>

Check RBUF for Data Valid set, no error bits
set, Rx line = 0, and the data being 125.

160010/100050 <LF>

Check CSR for TRDY set and RDONE cleared.

160012/000125 <LF>

Read RBUF for Data Valid cleared.

160014/000001 <LF>
160016,/000000 0< 1>

Load a 0 into TDR.

160014/000001
< 1 >

160012/100000<
1 >

Read RBUF for Data Valid set, no errors, Rx
line = 0, and the data bits being Os.

160010/100050

Check CSR for TRDY set and RDONE cleared.

This test sets the maintenance bit but disables the receivers. It then transmits a character and
checks to see that it is not received.

@160010/000000 20 <CR>

Set Master Clear.

@ /000000 50

Set MSE and MAINT in CSR.

160012/0nnnnn 7470 <LF>

Load the LPR with RX ENAB cleared.

160014/000000 1<t >

Set TCR bit 00.

160012/0nnnnn <1t>

Check CSR for TRDY set and RDONE cleared.

160010/100050 <LF>

160012/0nnnnn <LF>
160014/000001 <LF>

160016/000000 377 <t>

Load 377 into TDR.

160014/000001 <1t>

160012 /0nnnnn <1 >

Check RBUF to see that Data Valid did not set.

160010/100050

Check CSR to see that RDONE is clear.

6-22

~—

This test sets line O for 5-level code and then attempts to transmit and receive 377. Transmitted bits are masked in the process, and a 37 is received. This proves that the UARTSs have
switched to S-level.

@160010/000000 20 <CR>

Set Master Clear.

@ /000000 50 <LF>

Set MSE and MAINT in CSR.

Load LPR for 19.2K baud, 5-level, line number

160012/0nnnnn 17400 <LF>

Set TCR bit 00.

>
160014/000000 1 <1t
>
160012/0nnnnn <1t

Check CSR for TRDY set and line numbers 0.

160010/100050 <LF>
B~

160012/0nnnnn <LF>

160014/000001 <LF>
Load 377 into TDR.

>
160016/000000 377 <1t

160014/000001 <1>
>
160012/100037 <1

Read RBUF for Data Valid set, no errors, line

160010/100050

Check CSR for TRDY set and RDONE cleared.

= 0, data 37.

6-23

APPENDIX A

IC DESCRIPTIONS

A.1

GENERAL

This appendix contains data on the LSI chips used by the DZV11. The other smaller ICs are common,
widely-used logic devices. Detailed specifications on these chips are readily available, and hence are
not included here.

A.2

UART

The UART is a MOS/LSI device packaged in a 40-pin DIP. It is a complete subsystem that transmits
and receives asynchronous data in duplex or half-duplex operation. The receiver and transmitter can
operate simultaneously. The transmitter accepts parallel binary characters and converts them to a
serial asynchronous output.

The receiver accepts serial asynchronous binary characters and converts them to a parallel output. The
receiver and transmitter clocks are separate and must be 16 times the desired baud rate. The allowable
clock rate is dc to 160 kHz.
N

Control bits are provided to select: character lengths of 5, 6, 7, or 8 bits (excluding parity); odd, even,
or no parity; and 1 or 2 stop bits for 6-, 7-, or 8-bit characters. For 5-bit characters, 1 or 1-1/2 start bits
are used. The format of a typical input/output serial word is shown in Figure A-1.

Both the receiver and transmitter have double character buffering so that at least one complete charac-

ter is always available. A register is also provided to store control information.

MARK (1)
SPACE (0)

START

CHARACTER

STOP
DATA DATA DATA DATA DATA DATA DATA DATA
8 PARITY 1
7
6
5
4
3
2
1

FIRST CHARACTER

-—

1 LSB

GHDNI

| MSB |

RPN

T
|

DATA
STOP
1
START
2

)

-——
MK 0165

Figure A-1

Format of Typical Serial Character

A block diagram and simplified timing diagram for the UART transmitter are shown in Figure A-2.
The transmitter data buffer (holding) register can be loaded with a character when the TBMT (Transmitter Buffer Empty) line goes high. Loading is accomplished by generating a short negative pulse on
the DS (Data Strobe) line. The positive-going trailing edge of the DS pulse performs the load operation. The character is automatically transferred to the UART transmitter shift register when this
A-1

PARALLEL DATA INPUT

(DB1-DB8)

DATA STROBE (DS)

TRANSMITTERBUFFER —

X
L

| [T

EMPTY {TBMT)
START

ASYNCHRONOUS

patA

SERIAL OQUTPUT (SO}

END OF CHARACTER

(EOC)

[

/[ DATA

STOP

M
TRANSMITTER TIMING DIAGRAM

NO. STOP BITS -38]

—

EVEN PAR. SEL. 32,

CONTROL

NO PARITY 2.}

37
ITS/ICHAR. ——»
BITS.
38

HOLDING

PAR

F—»

GEN

CONTROL STROBE ————J34

SERIAL

OuTPUT

ouTPUT
LOGIC

DECODER

END OF
24
—~ CHARACTER

(EOC)
XMTR

XMTR

DATA

HOLDING

SHIFT

BUS

LOAD

DATA STROBE 23

SHIFT
22

TBMT

TIMING

GENERATOR

MK 0162

Figure A-2

BUFFER

EMPTY

F/F

cLocK INPUT 20,

TRANSMITTER

UART Transmitter

A-2

register becomes empty. The desired start, stop and parity bits are added to the data and transmission
begins. One-sixteenth of a bit time before a complete character (included stop bits) has been transmitted, the EOC (End-of-Character) line goes high and remains in this state until transmission of a
new character begins.

A block diagram and simplified timing diagram for the UART receiver are shown in Figure A-3. Serial
asynchronous data is sent to the SI (Serial Input) line. The UART searches for a high-to-low (mark-tospace) transition on the SI line. If this transition is detected, the receiver looks for the center of the start
bit as the first sampling point. If this point is low (space), the signal is assumed to be a valid start bit
and sampling continues at the center of the subsequent data and stop bits. The character is assembled
bit by bit in the receiver shift register in accordance with the control signals that determine the number
of data bits and stop bits and the type of parity, if selected. If parity is selected and does not check, the
RPE (Receiver Parity Error) line goes high. If the first stop bit is low, the FER (Framing Error) line
goes high. After the stop bit is sampled, the receiver transfers in parallel the contents of the receiver
shift register into the receiver data buffer (holding) register. The receiver then sets the DA (Received
Data Available) line and transfers the state of the framing error bits to the status holding register.
~—

When the module accepts the receiver output, it drives the RDA (Reset Data Available) line low which
clears the DA line. If this line is not reset before a new character is transferred to the receiver holding
register, the OR (Overrun) line goes high and is held there until the next character is loaded into the
receiver holding register.

Figure A-4 is a pin/signal designation diagram for the UART. The function of each signal is given in
Table A-1. In the function column, the references to high and low signals are with respect to the pins
on the UART.

Table A-1
Pin

Number

UART Signal Functions

Mnemonic

Name

Function

Vee

+5V

Power Supply

-12V

Ground

RDE

Received Data Enable

A logic low on this line places the re-

5-12

RDI1-RD8

Received Data

Power Supply (Later designs do not

use this pin.)

ceived data onto the output lines.

Eight data out lines that can be wire

ORed. RD8 (pin 5) is the MSB and

RD1 (pin 12) is the LSB. When 5, 6,
or 7, bits are low. Character is right
justified into the least significant bits.

PER

Receiver Parity Error

Goes high if the received character

FER

Framing Error

Goes high if the received character has

parity does not agree with the selected
parity.

no valid stop bit.

Table A-1

UART Signal Functions (Cont)

{

Number

Mnemonic

Name

Overrun

Goes high if the previously received
character is not read (DA line not reset) before the present character is
transferred to the receiver holding register.

SWE

Status Word Enable

When low, places the status word bits
(PE, OR, TMBT, FE, and DA) on the

Function

output lines.

RCP

Receiver Clock

Input for an external clock whose frequency must be 16 times the desired

receiver baud rate.

RDA

Reset Data

When

low,

resets the received DA

(data available) line.
19

Received Data

Goes high when an entire character
has been received and transferred to
the receiver holding register.

Serial Input

Input for serial asynchronous data.

External Reset

After power is turned on, this line
should be pulsed high which resets all
registers, sets serial output line high,

sets end-of-character line high, and
transmitter buffer empty line

sets

high.
22

TBMT

Transmitter Buffer
Empty

Goes high when the transmitter data
holding register may be loaded with
another character.

Data Strobe

Pulsed low to load the data bits into
the transmitter data holding register
during the positive-going trailing edge
of the pulse.

EOC

End-of-Character

Goes high each time a full character,
including stop bits, is transmitted. It

remains high until transmission of the
next character starts. This is defined
as the mark (high) to space (low) tran-

sition of the start bit. This line re-

mains high when no data is being
transmitted. When full speed transmission occurs, this lead goes high for
1/16 bit time at the end of each char-

acter.

Table A-1

UART Signal Functions (Cont)

Pin
Number

Mnemonic

Name

Function

Serial Output

Output for transmitted character in
serial asynchronous format. A mark is
high and a space is low. Remains high
when no data is being transmitted.

26-33

DB1-DB8

Data Input

Eight parallel data-in lines. DB8 (pin
33) is the MSB and DBI (pin 26) is the
LSB. If 5-, 6-, or 7-bit characters are
selected, the least significant bits are
used.

Control Strobe

When high, places the control bits
(POE, NP, SB, NB1, and NB2) into
the control bits holding register.

No Parity

When high, eliminates the parity bit
from the transmitted and received
character and drives the received Parity Error (PER) line low. As a result,
the receiver does not check parity on
reception and during transmission.
The stop bits immediately follow the
last data bit.

2SB

Two Stop Bits

Selects the number of stop bits that
immediately follow the parity bit. A
low inserts 1 stop bit. A high inserts
1.5 stop bits for 5-character formats
and 2 stop bits for other character
lengths.

37, 38

NB2, NBI

Number of bits per
character

(excluding parity)

Select 5, 6, 7, or 8 data bits per character as follows.

Bits/
Char

NB2
37

NB1
(38)

5
6
7
8

L
L
H
H

L
H
L
H

POE

Even Parity Select

Selects the type of parity to be added
during transmission and checked during reception. A low selects odd parity
and a high selects even parity.

TCP

Transmitter Clock

Input for an external clock whose frequencey must be 16 times the desired
transmitter baud rate.

START
SERIAL INPUT (SI)

sTOP

sTop START

]1/fi DATA

\ [ DatA

ASYNCHRONOUS

RECEIVED DATA
AVAILABLE (DA)

PARALLEL DATA OUT

(RD1--RD8)
RESET DATA

AVAILABLE (RDA)
RECEIVER TIMING DIAGRAM

REC DATA
AVAILABLE

OVERRUN

REC
PARITY

FRAMING

ERROR

119
)

DATA BITS
r

REC

—

RD1
tse

AND GATES

ENABLE

14 ‘Q’SSD

y—t—I—LLu S
I

STATUS

N GATES
AND

RDS
MSB

DATA

RESET

pata —
[ R

} AVAILABLE

‘

OVERRUN
c

D
:

PARITY

—9

FRAME

CERR
"R

DATA HOLDING REGISTER

)

SERIAL

DATA

RECEIVER SHIFT REGISTER

INPUT

CLOCK

INPUT

17
—

_ fl

. _DATA AVAILABLE|
PARITY ERROR

CONTROL LOG!IC

|39

EVEN

PARITY
SELECT

NB2

FRAMING ERROR

—

MKD|6;

NB1

PARITY NUMBER OF

BITS/CHARACTER

Figure A-3

UART Receiver

RESET DATA AVAILABLE->1§G RDA
STATUS WORD ENABLE-J-G—C SWE
RECEIVED DATA ENABLE-’iC RDE

OR
FER

RECEIVER CLOCK 111 RCP
SERIAL INPUT-+22] SI

DATA BIT INPUTS €

PER

DB8

RD8

DB7

RD7

DB6

RD6

DB5

RD5

DB4

RD4

DB3

RD3

DB2

RD2

-1 DB1

RD1

o9
el

19 . RECEIVE DATA AVAILABLE

Js—’OVERRUN
'4 . FRAMING ERROR

'3+ RECEIVE PARITY ERROR

>RECEIVED DATA BITS

25 __ SERIAL OUTPUT
LTRANSMITTER BUFFER EMPTY
EOC -2—4—*END OF CHARACTER
SO

DATA STROBE-=230 DS
TRANSMITTER CLOCK->icl TCP
XR

EXTERNAL RESET———*—l

TBMT

€S
34

NB2

NB1

|37

|38

CONTROL STROBE

|35

POE

2SB

|39

|36

NOTE:

NO. OF BITS PER CHAR{

1= +5V

PIN 2= —12V*

PIN 3= GROUND

NO PARITY

PARITY SELECT
MK 0166

TWO STOP BITS

*LATER DESIGNS DO NOT REQUIRE -12V.

Figure A-4

UART Chip Pin Designations

A-7

DCO003 INTERRUPT CHIP

The interrupt chip is an 18-pin DIP device that provides the circuits to perform an interrupt transaction in a computer system that uses a ‘“‘pass-the-pulse’ type arbitration scheme. The device provides
two interrupt channels labeled A and B, with the A section at a higher priority than the B section. Bus
signals use high-impedance input circuits or high-drive open-collector outputs, which allow the device
to directly attach to the computer system bus. Maximum current required from the V. supply is 140

~—

mA.

Figure A-5 is a simplified logic diagram of the DC003 IC. Timing for the interrupt section is shown in
Figure A-6, while Figure A-7 shows the timing for both A and B interrupt sections. Table A-2 describes the signals and pins of the DC003 by pin and signal name.

DC003

~~—7

17
————

RQSTAH

15
16

—-{

ENADATAH

ENA ST H

14
—————4

ENACLKH

07
——

BlAKIL

BIRQL

OP——

BIAKO L

06
Pp———

05
04

———

BINITL

INITOL

P————

VECTORH

p——r

————a

BDINL

13
02

—————

ENBCLKH

VEC

RQSTB

12
—

—{

EnBDATAH

0
11

RQSTB H

ENBSTH

J———

e
MK-0164

Figure A-5

DCO003 Logic Symbol

300
MIN'\{

300
/MIN
x

BINIT L

INITOL _of

7-35
|

]

ENA DATA H

[

[]

ENA CLK H 30M|N——-‘E 1
|

ENASTH

7-30—

[—
[

RQSTA H

BIRQ L

15-65— |o— —

BDIN L

[—20-90

35 MIN —»]

BIAKI L

)

1
3BEMIN— |—

]

|- 10-45
10-45 =+[~

VECTOR H

12-55

BIAKO L

I'—

|
]
I

1
I

NOTE:

TIMES ARE IN NANOSECONDS.

Figure A-6

DCO003 A Section Timing

b—lj:12—55
1

MK-0173

BINIT L

300

'M|N|300?
MIN,

INITO L

7--35

ENB DATA H

)

[

ENB CLKH

ENB ST H

BIRQ
L

RQSTB H

ENA DATAH

ENA CLK H

30 MIN —

ENASTH

RQSTA H

BDINL

35 MIN —»

BIAKI L

fe—

35 MIN —el
1

|o—

VECTOR H

VECRQSTB H
NOTE:

MK-0175

TIMES ARE IN NANOSECONDS.

Figure A-7

DCO003 A and B Section Timing

A-10

Table A-2

Pin
Number
1

DCO003 Signals

I/O Name

Symbol

Function

Interrupt
Vector Gating

VECTOR H

This signal gates the appropriate vector address onto the bus and to form
the bus signal BRPLY L.

VEC RQSTB H

When asserted, this signal indicates
RQST B service vector address is required. When negated, it indicates
RQST A service vector address is required. VECTOR H is the gating signal for the entire vector address; VEC
RQST B H is normally bit 2 of the address.
THE BDIN signal always precedes a
BIAK signal.

Signal
Vector

Request B
Signal

Bus Data In

BDIN L

Initialize Out

INITOL

This is the buffered BINIT L signal
used in the device interface for general
initialization.

Bus Initialize

BINIT L

When asserted, this signal brings all
drive lines to their negated state (except INITO L).

Bus Interrupt
Acknowledge

BIAKO L

This signal is the daisy-chained signal

that is passed by all devices not re-

questing interrupt service (see BIAKI
L). Once passed by a device, it must
remain passed until a new BAIKI L is
generated.

Bus Interrupt
Acknowledge

BIAKI L

This signal is the processor’s response
to BIRQ L true. This signal is daisychained such that the first requesting
device blocks the signal propagation
while non-requesting devices pass the
signal on as BIAKO L to the next device in the chain. The leading edge of
BIAKI L causes BIRQ L to be unasserted by the requesting device.

Asynchronous
Bus Interrupt

BIRQL

The request is generated by a true
RQST signal along with the associated true Interrupt Enable signal. The
request is removed after the acceptance of the BDIN L signal and on the
leading edge of the BAIKI L signal, or
the removal of the associated inter-

Request

rupt enable, or due to the removal of
the associated request signal.

Table A-2
Pin

DC003 Signals (Cont)

Number

I/0 Name

Symbol

Function

17
10

Device
Interrupt
Request
Signal

RQSTA H
RQSTB H

When asserted with the enable A/B
flip-flop asserted, this signal causes
the assertion of BIRQ L on the bus.
This signal line normally remains as-

16
11

serted until the request is serviced.

Interrupt
ENA ST H
Enable Status | ENB ST H

This signal indicates the state of the
interrupt enable A /B internal flip-flop
which is controlled by the signal line

ENA/B DATA H and the ENA/B
CLK H clock line.

15
12

Interrupt
Enable Data

14
13

Interrupt
Enable Clock

ENA DATA H
ENB DATA

ENA CLK H
| ENB CLK H

The level on this line, in conjunction
with the ENA /B CLK H signal, deter-

mines the state of the internal interrupt enable A flip-flop. The output of
this flip-flop is monitored by the
ENA/B ST H signal.

When asserted (on the positive edge),
interrupt enable A/B flip-flop assumes the state of the ENA/B DATA
H signal line.

DC004 PROTOCOL CHIP

The protocol chip is a 20-pin DIP device that functions as a register selector, providing the signals
necessary to control data flow into and out of up to four word registers (8 bytes). Bus signals can
directly attach to the device because receivers and drivers are provided on the chip. An RC delay
circuit is provided to slow the response of the peripheral interface to data transfer requests. The circuit
is designed such that if tight tolerance is not required, then only an external 1K +20 percent resistor is
necessary. External RCs can be added to vary the delay. Maximum current required from the V¢
supply is 120 mA.

Figure A-8 is a simplified logic diagram of the DC004 IC. Signal timing with respect to different loads
are tabularized in Table A-3 and are shown in Figure A-9. Figure A-10 shows the loading for the test
conditions in Table A-3. Signal and pin definitions for the DC004 are presented in Table A-4.

NS
]

VECTOR H [}1

203 Vvce

BDAL2[]2

19[JENBH

DC004

BDAL 1[]3

BDALO[]4

H SEL6 L

18[JRXCX H

BWTBT L []5

16[J SEL4 L

BSYNC L[]8

1s[JSEL2
L

BDIN L[]7

14[]SELO
L

BRPLY L[]8

13[JouTHB L

BoouT L[]

12JOUTLB L

GND[}10

1M[JINWD
L

~AAM——— +VCC

ENB H|19

ENB

LATCH

BSYNC L—*G

BDAL2 L|02

—{D

ENB,

SYNC

]

GND

02
LATCH

Ll
BDAL1 L@

DAL 2

DECODER

O————16]sELaL

01
LATCH
|
o

BDALO L.*-—-.fi D

SELBL

DAL

SEL2 L
.————-. SELOL
13JOUTHB L

00
LATCH

12]JOUTLB L
BWTBT L

|05

BDOUT L{09

T1{INWD L
MK 0171

Figure A-8§

DCO004 Simplified Logic Diagram

A-13

Table A-3

DC004 Signal Timing versus Output Loading

With Respect To

Test

Output
Being
Negated

Output
Being
Asserted

Min | Max | Min | Max | FigureA-10

Condition

(ns)

(ms)

Reference

BSYNCL

Load B
Load C

15
15"

35
40

)5
5

25
30

ts, tg

OUTLBL

BDOUTL

Load B

tg, t10

Load C

OUTHBL

DBOUTL

Load B

tg, t11

INWD L

BDIN L

Load A
Load B

5
5

25
30

5
5

25
30

ti1, t12

BRPLY L

OUTLBL

-10

t13, t14

BRPLY L

OUTHBL

-10

t13, t14

(Load A)

(Load B)

BRPLY L

INWD L

-10

t13, ti4

Signal

SELnL
(n=0,
2,4, 6)

Pin 18 Connection
RX = 1K +5%
350 +5%
15 pF £5%

Pin 18 Connection
RX = 4.64K £1%

(Load A)

(Load B)

BRPLY L

VECTOR H

t13, t14

BRPLY L

300

400

-10

t13, t14

(Load A)

OUTLBL

(Load B)

BRPLYL

OUTHBL

300

400

-10

t13, t14

BRPLY L

(Load A)

(Load B)

(Load A)

(Load B)

INWDL

300

400

-10

t13.t14

BRPLY L

VECTOR H

330

430

t13, ti4

(Load A)

A-14

(Load A)

CX = 220 pF +1%

Load C

25MINy,

,0L
BDAL(2,17

/25 MIN

| 70000
MIN

w720

15 MINy,

777

OUTLB L

BDIN L

{

]

— I-——T12

BRPLY L

T13—» ‘:

Ry Cx H

R
T15 —

_"IT—1—4F‘-- 2.4V

B
ey
].-_

—

I-—T16

*TIME REQUIRED TO DISCHARGE Rx Cx FROM ANY CONDITION ASSERTED = 150ns

MK -0172

NOTE

TIMES ARE IN NANOSECONDS.

Figure A-9

IZ__.J:‘_“

Th—] =

T10

(WD L

VECTORH

QT_

OUTHB L

~—

1sMIN,= | 1O MIN

BDOUT L

—=T6 [

Ev*TS:l

SEL (0,2, 4,6) L

BSYNC L

DC004 Timing Diagram

vee
28092

60¢2

FROM

OUTPUT

OouTPUT

j[ 200pF

OUTPUT ’ l 15pF

DIODE-

LOAD B

LOAD A

LOAD C
MK.0176

Pin
1

Figure A-10

DC004 Loading Configuration

Table A-4

DC004 Pin/Signal Descriptions

Signal
VECTOR H

Description
Vector - Thxs mput causes BRPLY L to be generated
through the delay circuit. Independent of BSYNC L and
ENB H.

BDAL2 L

Bus Data Address Lines — These signals are latched at the

3
4

BDALI L
BDALOL

assert edge of BSYNC L. Lines 2 and 1 are decoded for the

BWTBT L

select outputs; line O is used for byte selection.
Bus Write/Byte - While the BDOUT L input is asserted,
this signal indicates a byte or word operation: asserted =
byte, unasserted = word. Decoded with BDOUT L and
latched BDALO L to form OUTLB L and OUTHB L.

BSYNC L

BDIN L

Bus Synchronize - At the assert edge of this signal, address
information is trapped in four latches. While unasserted,
disables all outputs except the vector term of BRPLY L.
Bus Data In - This is a strobing signal to effect a data

input transaction. Generates BRPLY L through the delay

circuit and INWD L.
8

BRPLY L

Bus Reply - This signal is generated through an RC delay
by VECTOR H, and strobed by BDIN L or DBOUT L,
and BSYNC L and latched ENB H.

Table A-4

DC004 Pin/Signal Descriptions (Cont)

Signal

Description

BDOUT L

Bus Data Out - This is a strobing signal to effect a data
output transaction. Decoded with BWTBT L and BDALO
to form OUTLB L and OUTHB L. Generates BRPLY L
through the delay circuit.

INWDL

In Word - Used to gate (read) data from a selected register
onto the data bus. Enabled by BSYNC L and strobed by
BDIN L.

12
13

OUTHB L
OUTLB L

Out Low Byte, Out High Byte - Used to load (write) data
into the lower, higher, or both bytes of a selected register.
Enabled by BSYNC L and decode of BWTBT L and
latched BDALO L, and strobed by BDOUT L.

14
15

16
17

SELO L
SEL2 L
SEI4A L
SEL6 L

Select Lines — One of these four signals is true as a function
of BDAL2 L and BDALI L if ENB H is asserted at the
assert edge of BSYNC L. They indicate that a word register has been selected for a data transaction. These signals
never become asserted except at the assertion of BSYN L
(then only if ENB H is asserted at that time) and, once
asserted, are not negated until BSYNC L is negated.

RXCX

External Resistor Capacitor Node - This node is provided
to vary the delay between the BDIN L, BDOUT L, and
VECTOR H inputs and BRPLY L output. The external

resistor should be tied to V. and the capacitor to ground.
As an output, it is the logical inversion of BRPLY L.

ENB H

Enable - This signal is latched at the asserted edge of
BSYNC L and is used to enable the select outputs and the

address term of BRPLY L.

A.5

DC005 BUS TRANSCEIVER CHIP

The 4-bit transceiver is a 20-pin DIP, low-power Schottky device for primary use in peripheral device
interfaces, functioning as a bidirectional buffer between a data bus and peripheral device logic. In
addition to the isolation function, the device also provides a comparison circuit for address selection
and a constant generator, useful for interrupt vector addresses. The bus /0 port provides high-impedance inputs and high-drive (70 mA) open-collector outputs to allow direct connection to a computer’s
data bus. On the peripheral device side, a bidirectional port is also provided, with standard TTL inputs
and 20 mA tri-state drivers. Data on this port is the logical inversion of the data on the bus side.

Three address jumper inputs are used to compare against three bus inputs and to generate the signal
MATCH. The MATCH output is open-collector, which allows the output of several transceivers to be
wire-ANDed to form a composite address match signal. The address jumpers can also be put into a
third logical state that disconnects that jumper from the address match, allowing for “don’t care”
address bits. In addition to the three address jumper inputs, a fourth high-impedance input line is used
to enable/disable the MATCH output.

Three vector jumper inputs are used to generate a constant that can be passed to the computer bus.
The three inputs directly drive three of the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three operational states: receiver data, transmit data, and
disable.

Maximum current required from the V¢ supply is 100 mA.

Figure A-11 is a simplified logic diagram of the DC005 IC. Timing for the various functions is shown
in Figure A-12. Signal and pin definitions for the DCO005 are presented in Table A-5.

Table A-5

DC005 Pin/Signal Descriptions

Function

Name

BUSOL

BUS2 L

inputs. Low = 1.

BUS3 L

18
17
7

DATO H
DAT 1 H
DAT2 H

Peripheral Device Data - These four tri-state lines carry
the inverted received data from BUS (3:0) when the transceiver is in the receive mode. When in transmit data mode,

BUS1L

Bus Data - This set of four lines constitutes the bus side of

the transceiver. Open-collector outputs; high-impedance

the data carried on these lines is passed inverted to BUS

(3:0). When in the disabled mode, these lines go open (hi7). High = 1.

14
15
16

JV1H
JV2H
JV3H

Vector Jumpers — These inputs, with internal pull-down
resistors, directly drive BUS (3:1). A low or open on the
jumper pin causes an open condtion on the corresponding

BUS pin if XMIT H is low. A high causes a one (low) to be
transmitted on the BUS pin. Note that BUS 0 L is not
controlled by any jumper input.

MENB L

Match Enable — A low on this line enables the MATCH

output. A high forces MATCH low, overriding the match
circuit.

MATCH H

Address Match - When BUS (3:1) matches with the state

of JA (3:1) and MENB L is low, this output is open; other-

wise, it is low.

A-18

~—r

Address Jumpers - A strap to ground on these inputs allows a match to occur with a one (low) on the corresponding BUS line; an open allows a match with a zero (high); a

N unllen)

Function

> > >

Name

DCO005 Pin/Signal Descriptions (Cont)

ot oy G

Table A-S§

strap to V disconnects the corresponding address bit
from the comparison.

XMIT H

REC H

Control Inputs — These lines control the operational of the

transceiver as follows.

REC XMIT
0
0
1
1

0
1
0
1

DISABLE: BUS and DAT open
XMIT DATA: DAT to BUS
RECEIVE: BUS to DAT
RECEIVE: BUS to DAT

To avoid tri-state overlap conditions, an internal circuit

delays the change of modes between XMIT DATA mode,

and delays tri-state drivers on the DAT lines from en-

abling. This action is independent of the DISABLE mode.

DC005 TRANSCEIVER

JATL

L
JA2

TN
)

— 20Vee

L
- 19 JA3

MATCH H 3+

BUSO

BUS1

— 18 DATO H

RECH

17 DAT1H

XMITH

16 JV3 H

DAT3H

— 15 JV2
H

DAT2H

- 14 JV1 H

BUS3L

- 13 MENB L

BUS2L

L
- 12 BUSO

GND

— 11 BUST

JA1

BUS2

@:}

JA2

r—<<}
BUS3

JA3

MENB

{i6] Jv3

>—

:&}L
13}

XMIT

REC

vce
Figure A-11

(ig+— GND
DCO005 Simplified Logic Diagram
A-20

DAT3

—

TRANSMIT DATA TO BUS

XMITH

[

1
-

|~5T030ns

RECH (GROUND)
BUS L - OUTPUT

5T025ns+
=
=
DATH—INPUT ]
—
R

B
5T030ns
"

|+5TO25ns

[

RECEIVE DATA FROM BUS (BUS INITIALLY HIGH)
XMIT H (GROUND)
REC H

]

DAT H - OUTPUT

0TO30ns

—_——

BUS L - INPUT

l-8T0O30ns

[

RECEIVE DATA FROM BUS (BUS INITIALLY LOW)
XMIT H (GROUND)

RECH

]

DAT H — OUTPUT

|+=0T030ns

BUS L —INPUT

-8
TO 30 ns

]

|~0TO30ns

—
|

VECTOR TRANSFER TO BUS
WVH

]

|+-20nsMmAX

|+ 20ns MAX

BUS L — OUTPUT

ADDRESS DECODING
BUS L — INPUT

X
-

MATCH H

|
.

]

|=~10T040ns
X

j5TO 40 ns

MENB L

+-10
TO 40 ns

RECEIVE MODE LOGIC DELAY

XMIT H
REC H

T
l+40 TO 90 ns

DAT (3:0) H (OUTPUT)

¥/

MK-0174

Figure A-12

DCO00S Timing Diagram
A-2]

A.6

COM 5016 DUAL BAUD RATE GENERATOR
The 5016 is an LSI MOS device containing two independent sections. Each section divides its input
clock frequency by one of 16 divisors to produce one of 16 different clock outputs. The divisors are
stored in ROMs on the chip. The ROMs are addressed by circuits that latch in and decode the logical
states of the address lines (Figure A-13). The address lines may be strobed or held at a dc level. Table
A-6 lists the frequencies selected by the address lines. Figure A-14 depicts the 5016 pin locations. Table
A-7 defines their functions.

A.7 3341 FIFO SERIAL MEMORY
The 3341 first-in/first-out memory chip asserts Input Ready when it is ready to load data. Each time
Shift In is asserted, the chip accepts 4 bits of parallel data and shifts them to the output end of a 64- X
4-bit register. It then asserts Output Ready. When Shift Out is asserted, the chip places the data in the
output latches (Figure A-15).

LATCH

Tc _L
|

DECODE

ROM

CIRCUITS

CLOCK

-—+{

CLOCK

DIVIDER

R
RA

—

—_—

LATCH

AND

CIRCUITS

Rc
— .|

Rp ——-—-I

ROM

DECODE

Figure A-13

MK.0184

COM 5016 Simplified Block Diagram

A-22

Table A-6

COM 5016 Selectable Frequencies

.
.
Transmit/Receive Address

0
0
0
0
0

0
0
0
0
1

0
0
1
1
0

0
1
0
|
0

0
0
0
1
|
1
1
1
1
1
1

1
1
1
0
0
0
0
1
1
1
1

0
1
|
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1
0
|

Baud

Frequency
16X Clock

Rate

(kHz)

50
75
110
134.5
150

0.8
1.2
1.76
2.1523
2.4

300
600
1200
1800
2000
2400
3600
4800
7200
9600
19800

48
9.6
19.2
28.8
32.081
384
57.6
76.8
115.2
153.6
316.8

18 —— CLOCK

Crystal Frequency = 5.0688 MHz

CLOCK —
vVee —

17— fr

fR —1

RA —

15 }—— TB

RB —~

14— T¢

Rc —-

13}— TD

Rp —-

12 b— STT

STR —

—— GND

VDD —-

10— NC
MK-0185

Figure A-14

COM 5016 Pin Locations

A-23

Divisor
6336
4224
2880
2355
2112

1056
528
264
176
158
132
88
66
44
33
16

Table A-7
Pin

Number

Mnemonic

CLOCK

(XTAL/EXT1)

COM 5016 Pin Functions

Function

Name

7 Extemal 7C16ck;Inprut

This input is either one pin of a crystal

oscillator package or one polarity of
another external input.

Power Supply

+5 V supply

Receiver Output

This output runs at the frequency se-

4-7

Ra ,Rp

Receiver Address

The logic levels on these inputs select

STR

Strobe-Receiver

A high-level input strobe loads the re-

Frequency

Address

lected by the receiver address.

the receiver output frequency, fg.

ceiver address (R, Rp, Rc, Rp) into

the latch and decode circuits. This input may be strobed or hard-wired to a
high level.

Vbbp

Power Supply

No Connection

GND

Ground

STT

Strobe-Transmitter

A high-level input strobe loads the

Address

+12 V supply

transmitter address (TA, Tp, Tc, Tp)

into the latch and decode circuits.
This input may be strobed or hardwired to a high level.

13-16

TD, TC, TB, TA

Transmitter Address

| The logic levels on these inputs select

Transmitter Qutput

This output runs at the frequency se-

CLOCK
(XTAL/EXT?2)

Inverted External | Thisinput is either one pin of a crystal
Clock Input
oscillator package or one polarity of

Frequency

the transmitter output frequency, fr.

lected by the transmitter address.

another external input.

A-24

LOG!C BLOCK DIAGRAM
4

Do —*
5
D1—=

FIFO

64 WORD x 4 BIT

6 | INPUT

MAIN REGISTER

D2 —*STAGE

7
D3 —*

FIFO

OUTPUT "

STAGE

2
INPUT READY <+—{

|NPUT

SHIFT IN

CONTROL
LOGIC

MAIN REGISTER

CONTROL LOGIC

E—

OUTPUT

le—— SHIFT OUT

CONTROL

14
— OUTPUT READY

LOGIC

= PIN 16
Vgs
MASTER RESET

VoD =PIN 8
VgGg =PIN 1

PIN CONFIGURATION

LOGIC SYMBOL
2

INPUT

SHIFT

READY

ouT

QuUTPUT

3 — SHIFT IN

READY

(TOP VIEW)

vee [t

INPUT READY [ 2
— 14

SHIFTIN ] 3

3341
4 —Dg

Qo b— 13

] D1

0| P 12

6 — 0>

e — 1

03 ——- 10

] Vss

15 [} SHIFT OUT
14 [7] OUTPUT READY

Do [ @

127 Qq

1] Q2

10 ]a3

vpop[]e

9] MR

MASTER RESET
MK 0167

%,
Vss =PIN 16
+ 5V
Vpp = PIN 8

GND

VGG =PIN 1 —12V

Figure A-15

3341 FIFO Serial Memory

A-25

B
APPENDIX

CONNECTOR PINNING

Table B-1 lists the DZV11 header connector pinning. Table B-2 lists the edge connector pinning (Figure B-1). Table B-1 also lists the pinning of the BC11U interface cable, and the color of the wires. Note
that the wiring sequence does not simply repeat itself for each of the four cable connectors. Instead, the
sequence appears twice and then its mirror image is repeated twice. The header connector is wired this
way to prevent damage to the EIA transmitters and receivers in the event that the connector is reversed. Reversing the connector, however, reverses the line numbers. Observe the “This Side Up”
sticker on the connector.

EDGE

{—CONNECTOR

)

HEADER

&
CONNECTOR

MK-0169

Figure B-1

Connectors

B-1

Connector Pinning

Table B-1

g‘:‘;‘)"’

BCIIU Cable

| Black

Transmitted Data 00

Brown

Received Data 00

Gray

Data Terminal Ready 00

White

Ring 00

Green

Forced Busy 00

Yellow

Request to Send 00

Blue

Orange

Violet

Red

EIA Signal Description

(;eru—rid 7

Ground

Connector

onnector Pin

Carrier 00
P5

Wire

Color

Ground

Black

Transmitted Data 01

Brown

Received Data 01

Gray

Data Terminal Ready 01

White

Ring 01

Green

Forced Busy 01

Yellow

Request to Send 01

U
\Y%

U
A%

4
5

Blue
Orange

Ground

Violet

Carrier 01

Red

B-2

Table B-1

Connector Pinning (Cont)
Header

(Berg)
Connector

Pin | Wire
Comector
PS

Color

Carrier 02

Red

Ground

Violet

Orange

Request to Send 02

Blue

Forced Busy 02

Yellow

Ring 02

Green

Data Terminal Ready 02

White

Received Data 02

Gray

Transmitted Data 02

Brown

Ground

Black

EIA Signal Description

Carrier 03

KK | 8

Red

Ground

Violet

Request to Send 03

Blue

Forced Busy 03

Yellow

Ring 03

Green

Data Terminal Ready 03

White

Received Data 03

Gray

Transmitted Data 03

Uuu

Brown

Ground

\'A

Black

Orange

Table B-2

DZV11 Edge Connector Pinning

Mnemonic

AA2

BDALI4L
BDALISL
BDIN L
BDOUTL
BIAKIL

BU2

BV2
AH2
AE2
AM?2

+12
BBS7L
BDALOL
BDALIL
BDAL2L
BDAL3L
BDAL4L
BDALSL
BDAL6L
BDAL7L
BDALSL
BDAILSL

BD2
AP2
AU2
AV2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2

BIAKOL
BINITL
BDMGIL
BDMGOL
BIRQL
BRPLYL
BSYNCL
BDCOK H
GND
GND
GND
GND

AN2
AT?2
AR2
AS2
AL2
AF2
A2
BAI
AC2
ATI1
BC2
BTI

BDALIIL
BDALI12L
BDALI3L

BR2
BS2
BT2

Wil

CS2
CM2
CN2

BDALIOL

BA2
BVI
CA2
DA2

BP2

w10

CR2

~—

APPENDIX C

GLOSSARY

BBS7 L - Bussed Bank 7 Select (Table 5-1).

BDALOO L through BDALI1S L - Bussed Data/Address Lines (Table 5-1).
N

BDIN L - Bussed Data Input (Table 5-1).
BDOUT L - Bussed Data Out (Table 5-1).

BIAKI L - Bussed Interrupt Acknowledge In (Table 5-1).
BIAKO L - Bussed Interrupt Acknowledge Out (Table 5-1).
BINIT L - Bussed Initialize (Table 5-1).

BIRQ L - Bussed Interrupt Request (Table 5-1).

Break - A continuous spacing condition on the serial data line, interpreted as a framing error.
BRK 3 through BRK 0 - TDR bits 11 through 08. When set, the Break bit causes the transmission of a
Break signal.

BRPLY L - Bussed Reply (Table 5-1).
BSYNC L - Bussed Sync (Table 5-1).
BWTBT L - Bussed Write Byte (Table 5-1).

Carrier - A carrier is a continuous frequency capable of being modulated or impressed with a signal.
The name Carrier, however, is used in the DZVI11 print set to refer to the received line signal detector
input from the modem. This signal is referred to as *““Carrier Detect” and “Carrier On” in some books.

CCITT - The Consultive Committee International Telegraph and Telephone is an advisory committee
established under the United Nations to recommend worldwide standards.
CHAR LGTH A, CHAR LGTH B - LPR bits 03 and 04. These bits determine the length of the
characters the DZV11 receives and transmits (Table 3-4).
CLR - CSR bit 04. Controls the device Master Clear signal (Table 3-2).

CO - Carrier On. Also referred to as “Carrier” or “Carrier Detect.” Some sources abbreviate Carrier
Detect to CD. Do not confuse CD or CO with EIA signal CD. EIA signal CD is Data Terminal
Ready. The EIA signal designation for Carrier On (or Carrier Detect) is CF.
C-1

CO3 through CO0- MSR bits 11 through 08, representing the Carrier signal for lines 03 through 00.
CONTROL STROBE H - This signal is generated by the speed and format control circuits on circuit
schematic sheet D8. It loads the speed parameters into the baud rate generators on sheet D8, and loads

the data format parameters into the UARTSs on sheets D13 and D14.
CSR - Control and Status Register (Table 3-2).
DAOO through DAO3 - Data Available. These signals come from the
(sheets D13 and D14),

R DONE pins on the UARTSs

DATA IN 00 H through DATA IN 03 H - These signals are the received data from the EIA signal
lines. They originate at the EIA/TTL receivers (sheet D7) and go to the maintenance mode data

selector (sheet D 10).
DATA TERM RDY 00 through DATA TERM RDY 03 - Data Terminal Ready signals for lines 00
through 03 (sheet D6). Refer to Table 5-2.
Data Valid - Bit 15 in the RBUF. The Output Ready signals from the four silo memory chips are
ANDed to form RECEIVER DONE H. When the RBUF is addressed, RECEIVER DONE H is
latched as VALID DATA H (sheet D12). VALID DATA H becomes Data Valid (bit 15) in the
RBUF.
DATI - Data input bus cycle.
DATIO - Data input/output bus cycle.
DATIOB - Data input/output bus cycle involving a byte.

DATO - Data output bus cycle involving a word.
DATOB - Data output bus cycle involving a byte.
DCE - Data communication equipment.
DEVICE DATA BUS - The bidirectional tri-state bus internal to the module; signal lines DEVICE

DATA BUS 00 through DEVICE DATA BUS 15.
DEVICE SELECT H - This signal is the wired-AND of the MATCH signals from all four bus transceiver chips (sheet D2). It enables the protocol chip (sheet D4).

DTE - Data terminal equipment.
DTR - Data Terminal Ready. Refer to Table 5-2.
DTRO through DTR3 - Bits 08 through 11 in the transmitter control register. They represent the state
of Data Terminal Ready for each of the four lines.
EIA - Electronic Industries Association.
FB - Forced Busy. Refer to Table 5-2.
FEOO through FE 03 - Framing Error signals from the UARTSs (sheets D13 and D14).

FIFO - First-In/First-Out.
Forced Busy - Used with some modem equipment such as Bell models 103E and 113B. Signals a
modem controller to switch to another channel.
FRAM ERR - Framing Error; RBUF bit 13.
Framing Error — This error occurs when a UART receiver does not detect a stop bit at the time it tests

for one. This may be caused by a transmission error or by a Break signal.
INITIALIZE H, INITIALIZE L - These are the device initialization signals. They are generated by

either the CLR bit (CSR bit 04) or by BINIT from the LSI-11 bus (sheet DS5).
LD BREAK REGISTER H - Load pulse for the high byte of the transmit data register. (sheets D4

and D10).
LD CSR HIGH BYTE H - Load pulse for the high byte of the control and status register (sheet D4).
LD CSR LOW BYTE H - Load pulse for the low byte of the control and status register (sheet D4).
LD LPR REGISTER L - Load pulse for the line parameter register (sheets D4 and D8).
LD TCR HIGH BYTE H - Load pulse for the high byte of the transmit control register (sheet D4).

LD TCR LOW BYTE H - Load pulse for the low byte of the transmit control register (sheet D4).
LD TDR REGISTER H - Load pulse for the low byte of the transmit data register (sheet D4).
LINE A, LINE B - Bits 00 and 01 of the line parameter register. This is a 2-bit code that specifies the

number of the line to which the parameters apply.
LINE ENABO through LINE ENAB3 - Bits 00 through 03 in the transmit control register. Each of
these bits enables transmission on the corresponding line.
LOAD IN PROGRESS L - Indicates that either the line parameter register or the transmit data
register is being loaded. BRPLY is delayed 300 ns while a load is in progress for either of these two
registers (sheet D4).

LOAD SILO H - Enables silo buffers to load data (sheets D11 and D12).
LPR - Line parameter register. Refer to Table 3-4.

MAINT - Maintenance bit (CSR bit 03). Enables the internal loop-back maintenance mode.
MAINTENANCE H - This signal is set by the MAINT bit (sheet D5) and controls the maintenance

mode data selector (sheet D10).

MASTER CLEAR H - This signal is derived from the clear bit CLR (CSR bit 04). See shect D5.

MASTER SCAN CLOCK H - This signal is produced by dividing the master oscillator clock signal
(sheet D8). It drives the receiver scanner (sheet D11).
MASTER SCAN ENABLE H - Set by the MSE bit. Enables both transmitter and receiver control
circuitry (sheets DS, D9, D11).

MASTER SCAN ENABLE L - Set by the MSE bit. Enables the master scan clock (sheets DS and
D8).
MSE - Master Scan Enable. CSR bit 05.
MSR - Modem Status Register. Refer to Paragraph 3.2.5.
ODD PAR - Odd Parity. Line parameter register bit 07. Refer to Table 3-4.

OR 00 through OR 03 - Overrun error signals from UARTS (sheets D13 and D14) to silo buffer (sheet
D12).
OUT HB - Output high byte. Indicates that an output data transfer will be made to the high byte of
the selected register (sheet D4).
OUT LB - Output low byte. Indicates that an output data transfer will be made to the low byte of the
selected register (sheet D4).
OVRN ERR - Overrun Error. RBUF bit 14. Refer to Table 3-3.
PAR ENAB - Parity Enable. Line parameter register bit 06. Refer to Table 3-4.
PAR ERR - Parity Error. RBUF bit 12. Refer to Table 3-3.
PE 00 through PE 03 - Parity error signals from the UARTS (sheets D13 and D 14) to silo the buffer
(sheet 12).
PSW - Processor Status Word.

QBUS - LSI-11 Bus.

RBUF - Receiver Buffer. Refer to Table 3-3.
RBUF DO through RBUF D7 - Received data bits. RBUF bits 0 through 7.
RCV CLOCK 00 H through RCV CLOCK 03 H - Receiver clocks from the baud rate generators

(sheet D8) to the UARTS (sheets D13 and D14).
RCV DATA 00 through RCV DATA 03
- Received data bits from the silo buffer (sheet D12) to the
multiplexers (sheet D3).
RCV DATA ENABLE 00 through RCV DATA ENABLE 03 - These signals enable the UARTS for

the selected lines. They originate in the receiver control circuitry (sheet D11) and go to the UARTSs

(sheets D13 and D14).
RD1 through RD8 - Received data bits from the UARTS (sheets D13 and D14) to the silo buffer
(sheet D12).
RDONE - Receiver Done. CSR bit 07. Refer to Table 3-2.
READ DEVICE H and READ L - These signals control the operating mode of the bus transceivers
(sheets D2 and D4).
READ RCV BUFFER H - This signal controls the unloading of the silo buffer (sheets D4 and D12).

C-4

RECEIVER DONE H - In the DZV11, this signal does not come from the UARTSs. It is the result of
anding the Output Ready signals from each of the four FIFO memory chips (sheet 12). It sets the
RDONE bit in the CSR (sheet D3) to indicate that a character of received data is ready in the silo
buffer.

RECEIVER INTR ENABL - Receiver Interrupt Enable (sheet D5).

RESET DAOO through DAO3 - These signals are made up in the receiver control circuitry (sheet D11)
to reset the Data Available signals in the UART (sheets D13 and D14) for the selected line.
R1 - Ring Indicator.

RI0 through RI3 - Modem status register bits 0 through 3, indicating the states of the Ring signal on
the corresponding lines.

RIE - Receiver Interrupt Enable. CSR bit 06. Refer to Table 3-2.

RING 00 through RING 03 - The Ring Indicator signals for lines O through 3, after having been

converted from EIA to TTL levels (sheet D7).
RO - Read-Only.

RTS - Request to Send. Refer to Table 5-2.
RW - Read/Write.

RX ENAB - Receiver Enable. Line parameter register bit 12. Refer to Table 3-4.

RX LINE A, RX LINE B - Receiver Line A and B, respectively. RBUF bits 08 and 09. Refer to Table
3-3.

SA - Silo Alarm. CSR bit 13. Refer to Table 3-2.

SAE - Silo Alarm Enable. CSR bit 12. Refer to Table 3-2.

SEL 0 - Select line for device register 0 (the CSR). See sheet D4.

SEL 2 - Select line for device register 2. For an input (read) operation, this is the RBUF. For an output

(write) operation, this is the LPR. See sheet D4.

SEL 4 - Select line for device register 4 (the TCR). See sheet D4.

SEL 6 - Select line for device register 6. For an input (read) operation, this is the MSR. For an output

(write) operation, this is the TDR. See sheet D4.

SERIAL INOO H through SERIAL INO3 H - Serial input data from each of the four lines. It is called
Data In between the receivers (sheet D7) and the maintenance mode data selector (sheet D10). From
there to the UARTS (sheets D13 and D14), it is called Serial In.

SERIAL OUTO00 through SERIAL OUTO3 - Serial data out of the UARTS (sheets D13 and D14). It

goes to the EIA drivers and the maintenance mode data selector (sheet D10).

SILO - This term refers to a buffer that automatically shifts data from its input end to its output end.
When a silo is loaded, the data does not queue up from the input end toward the output end, as in a
shift register. Instead, it stacks up at the output end, and is immediately available for unloading.
C-5

SILO ALARM H - This signal is the output of a latch that is set when 16 characters have entered the
silo (sheet D11). It is cleared by either reading the RBUF or clearing the Silo Alarm Enable bit in the
CSR.
SILO LOAD REQUEST H - This signal is asserted when the Data Available signal for the selected
line is set and the In Ready signals from the silo buffer chips are set. See sheet D12.
SPEED CODE A through SPEED CODE D - Bits 08 through 11 of the line parameter register. Refer
to Table 3-4.

STOP CODE - Bit 05 of the line parameter register. Refer to Table 3-4.
TBMT - Transmitter Buffer Empty.
TBMTO0O0 through TMBTO3 - These are Transmitter Ready signals from the UARTS (sheets D13 and
D14) to the transmitter control circuitry (sheet D9).
TBUFO through TBUF7 - Transmit data bits; bits 0 through 7 of the TDR.
TCR - Transmitter control register. Refer to Paragraph 3.2.4.
TDR - Transmit data register. Refer to Paragraph 3.2.6.
THRLOO L through THRLO3 L - Transmitter Holding Register Load signal for lines 0 through 3.

From the transmitter control circuitry (sheet D9) to the UARTS (sheets 13 and 14).
TIE - Transmitter Interrupt Enable. CSR bit 14. Refer to Table 3-2.
TLINE A, TLINE B - CSR bits 08 and 09. Indicate which line is selected for transmission. Refer to
Table 3-2.
TRAN INTR ENBL H - Transmitter Interrupt Enable signal (sheet D5).
TRANSMITTER READY H - This signal indicates that a line has been selected and that the corre-

sponding UART transmitter is ready to be loaded.

TRDY - Transmitter Ready. CSR bit 15. Refer to Table 3-2.

TTL - Transistor-Transistor Logic. The normal logic levels are approximately 4 V for one state and 0
V for the other.

TX CLOCK 00 H through TX CLOCK 03 H - Transmitter clocks for lines 0 through 3. They come

from the baud rate generators (sheet D8) and go to the UARTS (sheets D13 and D14).

UART - Universal Asynchronous Receiver/Transmitter. Refer to Appendix A.
UNLOAD SILO H - The unload signal to the Shift Out pin on the silo buffer memory chips.

VECTOR BIT 02 - Bit 02 of the vector term. This determines whether the computer uses a receiver
interrupt service routine or a transmitter interrupt service routine. See sheets D5 and D2.
VECTOR-TO-BUS H - This signal asserts the vector selected by the switch pack at E2 (sheet D5). It

also goes to the protocol chip (sheet D4) to cause assertion of BRPLY.

XMIT DATA 00 through XMIT DATA 03 - Transmitted data leaving the EIA drivers.

C-6

~—

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DZV11 ASYNCHRONOUS MULTIPLEXER

TECHNICAL MANUAL
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