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EB-05583-75

May 1975

179 pages

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Document:	LSI11 PDP-11/03 Processor Handbook
Order Number:	EB-05583-75
Revision:	0
Pages:	179
Original Filename:	EB-05583-75_LSI11PDP11-03ProcessorHandbook_1975.pdf

OCR Text

. ~nmnomn
0

000

processor
handbook
digtal equipment corporation

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in
this handbook.

The following are trademarks of
Digital Equipment Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

DEC US

LSl-11

CONTENTS
1-1
1-1
1-1

CHAPTER 1 INTRODUCTION
1.1 The LSl-11 Concept .
1.2 PDP-11/03
1.3 Features .
1.4 System Architecture
1.5 Microcomputer
1.5.1 General Registers
1.5.2 The Processor Status Word .....
· i.5.3 Instruction Set .
1.6 LSl-11 Memory Organization
1.7 LSl-11 BUS
1.7.1 Bidirectional Lines
1. 7 .2 Master Slave Relation
1.7.3 Interlocked Communication

1-10
1-12
1-12
1-12

CHAPTER 2 SPECIFICATIONS
.......... .
2.1 LSl-11 Operating Specifications ................. .
2.2 PDP-11/03 Operating Specifications ... .
2.3 H9270 Backplane Packaging and Mounting ..
2.4 PDP-11/03 Packaging and Mounting .....

2-1
2-1
2-2
2-2
2-2

CHAPTER 3 ADDRESSING MODES ....
3.1 Single Operand Addressing ....
3.2 Double Operand Addressing .
3.3 Direct Addressing
3.3.1 Register Mode ....
3.3.2 Autoincrement Mode .
3.3.3 Autodecrement (Mode 4)
3.3.4 Index Mode (Mode 6) .
3.4 Deferred (Indirect) Addressing ............... .
3.5 Use of the PC as a General Register .
3.5.1 Immediate Mode .....
3.5.2 Absolute Addressing ..... .
3.5.3 Relative Addressing .
3.5.4 Relative Deferred Addressing
3.6 Use of Stack Pointer as General Register .
3.7 Summary of Addressing Modes
3.7.1 General Register Addressing ................. .
3.7.2 Program Counter Addressing

3-1
3-3

CHAPTER 4 INSTRUCTION SET
4.1 Introduction
4.2 Instruction Formats ........ .
4.3 List of Instructions .. .
4.4 Single Operand Instructions ............ .
4.5 Double Operand Instructions
4.6 Program Control Instructions

iii

1-1
1-3
1-4
1-5
1-7
1-8
1-9

3-3

3-5
3-5
3-7
3-8
3-9
3-11
3-13
3-14
3-15
3-16
3-16
3-17
3-17
3-17
3-19
4-1
4-1
4-2
4-4

4-6
4-24
4-34

CHAPTER 5 PROGRAMMING TECHNIQUES ..
5.1 The Stack
·
5.2 Subroutine Linkage ....
5.2.1 Subroutine Calls
5.2.2 Argument Transmission
5.2.3 Subroutine Return
...................... .
5.2.4 LSl-11 Set Subroutine Calls
5.3 Interrupts
. .. . ... .. . ... .. . . .............. .
5.3.1· General Principles .
5.3.2 Nesting
5.4 Programming Peripherals
5.5 Device Registers

5·1
5-1
5.5
5.5
5-6

5.9
5.9

CHAPTER 6 EXTENDED ARITHMETIC OPTION ..
6.1 General ......... .
6.2 Fixed Point Arithmetic (EIS) ................. .
6.3 Floating Point Arithmetic (FIS) .

6·1
6·1
6-1
6-6

CHAPTER 7 CONSOLE OPERATION
7-1 General
............ .
7.2 Interfacing
7.3 CDT/Console Microcode

7·1
7-1
7-1
7-2

5·10
5-10

5-11
5·13
5-14

APPENDIX A

Memory Map ....

A·l

APPENDIX B

Instruction Timing

B·l

APPENDIX C

LSl·ll PDP-11 Family of Computers ....... .

C·l

APPENDIX D

Instruction Index

D·l

APPENDIX E

Summary of LSl-11 Instructions .....

E·l

The LSl-11 (PDPll/03) is the smallest member of the PDP-11 family
of computer systems. It offers the user minicomputer performance in a
microcomputer package that crosses traditional industry barriers. Therefore, the us,er can truly add computer power in systems previously too
small for computer application. Yet for our traditional user, the boxed version of the LSl-11, the PDPll/03, offers a completely integrated smaller
systems tool at lower cost without sacrificing performance. The LSl-11
(PDPll/03) maintains traditional PDP-11 architectural compatibility.
This includes programs up to 64K bytes and the use of the (optional)
floating instruction set (FIS) and extended instruction set (EIS).
Since the main design objective of the PDP-11 family has always been
to optimize total system performance, the interaction of software and
hardware have been carefully considered at every step in the design
process. The initial PDP-11 was specified in the ISP language and extensively simulated and benchmarked.
The effort of bringing the LSl-11 to the marketplace has required extensive design engineering ranging over many disciplines. The basic N-channel MOS semiconductor densities are state-of-the-art, since the PDP-11
requires many circuits. In fact, the 4-chips that comprise the processor
have approximately 50,000 active elements in an area of about 4 x 200
mils x 200 mils (0.16 square inches). Extensive circuit simulation was
carried out for the basic circuits that comprise those elements-using a
DECsystem-10. The basic logic masks were laid out using an Applicon
system for computer-aided-design, which is based on a PDP-11. Two
levels of simulation were carried out on a DECsystem-10 to check the
logic (Gate Level), and the behavior of the microprograms (RegisterTransfer Level). Finally, complete systems were simulated (including
1/0 equipment).
All the preparation in the design and production of computers, we believe, is necessary to support our main goal: providing high performance
quality computers at the lowest cost by which you, our users, can apply
them.

fL~
C. Gordon Bell
Vice President, Engineering
Digital Equipment Corporation

CHAPTER 1
INTRODUCTION

1.1 THE LSl·ll CONCEPT
DIGITAL introduced the first PDP-11 Processor in 1970. Since then, a fam·
ily of PDP-11 Computer products has been constantly evolving-not just
a family of processors, but a family of peripherals, software, and services. Today, the PDP-11 family is the broadest family of compatible
computer products on the market, with one of the latest additions being
the LSl-11.
The LSl-11 is a 16-bit microcomputer with the speed and instruction set
of a minicomputer. Due to its size and unique capabilities, it can fit into
almost any instrumentation, data processing, or controller configuration.

1.2 PDP-11/03
The PDP-11/03, a 3lh "H x 19"W x 13% "D boxed version of the LSl-11,
is designed as an off-the-shelf microcomputer system. It consists of an
LSl-11 microcomputer, a modular power supply, and a mounting box. The
mounting box is designed to mount in a standard 19" cabinet. For a
description of PDP-11/03 specifications, refer to Chapter 2.
1.3 FEATURES
The LSl-11 has the following features:
• 400 Plus Instruction Set
More than 400 instructions make up the LSl-11 's extensive instruction
set. This instruction set (also used by the PDP-11/ 35,40) permits the
user to take advantage of standard PDP-11 software. The only departure from the standard software is the addition of two new instructions, used to explicitly access the processor status word (PSW), Development programs as in the PDP-11 family include assemblers,
linkers, editors, loaders, utility packages, operating systems, and
higher level languages.
• Extensive Compute Power and Small Processor Size
The processor module is built around a set of four N-channel metal
oxide semiconductor (MOS) chips, which include control and data
elements as well as two microcoded read-only memories (microms).
The latter are programmed to emulate the powerful PDP-11/35,40 instruction set, along with routines for on-line debugging techniques
(ODT), operator interfacing, and boot-strap loader capability. The
processor also contains a 16-bit buffered parallel input/ output (I/ 0)
bus, a 4096-word MOS random-access memory (RAM), a real-time
clock input, priority interrupt control logic, power-fail/ auto restart, and
other features to provide stand-alone operation. The entire processor,
plus all of the above-mentioned features, are contained on one 8.5-by10-inch printed circuit board.
1-1

• Modularity
The processor, memory, device interfaces, backplane, and interconnecting hardware are all modular in design. Module selection, such as
the type and size of memory, and device interfaces, enable custom
tailoring to meet specific application requirements.
• Serial and Parallel 1/0 Modules
Serial and parallel 1/0 modules are available for interfacing the processor bus with external devices. These modules simplify connection
to peripherals when and if required, and also facilitate assembly of
prototype systems without penalizing later development of customized
interfaces.
• Choice of Memory
Memory modules are offered for applications requinng more storage
than is available with the 4096-word MOS random-access memory on
the processor board. Included are a non-volatile 4096-word core memory, a 1024-word static RAM, a 4096-word dynamic RAM which can be
automatically refreshed by central processor microcode, and read·only
memory (PROM/ ROM) with capacity to a maximum of 4096 words in
512-word increments (2048 words in 256-word increments).
• 16-Bit Word (Two 8-Bit Bytes)
Direct addressing of 32K 16-bit words.
• Word or Byte Processing
Very efficient handling of 8-bit characters without the need to rotate,
swap, or mask.
• Asynchronous Operation
System components run at their highest possible speed; replacement
with faster devices means faster operation without other hardware or
software changes.
• Stack Processing
Hardware sequential memory manipulation makes it easy to handle
structured data, subroutines, and interrupts.
• Direct Memory Access (OMA)
Inherent in the architecture is direct memory access for multiple devices.
• 8 General-Purpose Registers
For accumulators or address generation.
• Priority-Structured I/ 0 System
Daisy-chained grant signals provide a priority-structured 1/0 system.
• Vectored Interrupts
Fast interrupt response without device polling.
• Single and Double Operand Instructions
Powerful and convenient set of programming instructions.
• Power-Fail/ Auto Restart
Whenever DC power sequencing signals indicate an impending AC
power loss, a microcoded power-fail sequence is initiated. When power
is restored, the processor can automatically return to the run state.
Four options are available for power up sequencing.

J-2

1.4

SYSTEM ARCHITECTURE

A complete and powerful microcomputer system can be configured by
utilizing the KDll-F microcomputer, appropriate memory, 1/0 devices,
and interconnection hardware. The LSl-11 bus (implemented on the
H9270 card guide backplane assembly) is the interface which enables a
complete system to be configured.

H9270 BACKPLANE

LSI ·11 BUS

MSVll·A
11( • 16
SIT RAM

SERIAL
DEVICES

MSV11·8
41(•16
BIT RAM

MMVll·AA
41( •16
BIT CORE

SPECIAL
HIGH·SPfEO
UO USER
INTERFACES

PARALLEL
DEVICES

Figure 1-1

LSl-11 System Configuration

All LSl-11 modules connected to this common bus structure receive the
same interface signals. LSl-11 bus control and data lines are bidirec·
tional, open-collector lines which are asserted when low. All transactions
on the bus are asynchronous. The bus is composed of 16 multiplexed
data/ address lines, six data transfer control lines, six system control
lines, and five interrupt and direct memory access (DMA) control lines.
Interrupt and DMA are implemented with two daisy-chained grant signals which provide a priority-structured 1/0 system. The highest priority
device is the module electrically located closest to the microcomputer
module. Only when a device is not asserting a request does it pass grant
signals to lower priority devices.
The LSl-11 bus provides a vectored interrupt interface for any device.
Device polling is not required in processing interrupt requests. When an
interrupting device receives a grant, the device passes to the processor
an interrupt vector which points to a new processor status word and the
starting address of an interrupt service routine for the device.
The H9270 backplane assembly contains all of the wiring for the LSl-11
bus, plus standard power and system control wires.

1-3

1.5

MICROCOMPUTER

The microcomputer connected to the LSl-11 bus controls the time allocation of the LSl-11 bus for peripherals and performs arithmetic and
logic operations and instruction decoding. It contains multiple highspeed, general-purpose registers which can be used as accumulators,
address pointers, index registers, and other specialized functions. The
processor does both single and double operand addressing and handles
both 16-bit word and 8-bit byte data. The bus permits data transfers
directly between 1/0 devices and memory without disturbing the processor registers.
The microcomputer processor is implemented with four LSI 40-pin chips.
The four chips are the control chip, the data chip, and two microm
(microcode read-only memory) chips.

Control Chip
This chip provides the microinstruction address sequence, for the microm
and control for the data access port. It contains the following features:
• Programmable Translation Array (PTA)-Provides a decoding mechanism for generating microinstruction addresses from macroinstructions.
• Location Counter (LC)-Stores the address in the microm from which
accesses are being made.
• Return Register (RR)-Used to hold a microsubroutine return address.
• Data Transfer Control Logic-Provides control and timing signals for
data/ address port.
• Interrupt Logic-Provides control over three internal flags for the processor and four external flags for the system.

Data Chip
The data chip incorporates the paths, registers, and logic to execute
microinstructions. It offers the following features:
• Register File-Provides multiple registers for storage of frequently required data.
• Arithmetic and Logic Unit (ALU)-Performs the arithmetic and logic
operations necessary for instruction execution.
• Condition Flags Logic-Monitors the status of the result from the ALU
section.
• Data/ Address Port-Provides access to the data address lines.

Microm Chips
The microm chips provide storage of the microcode for emulation of the
basic PDP-11/35,40 instruction set, resident ODT (octal debugging technique) firmware, resident ASCII/ console routine, and bootstrap.
An optional fifth chip (third microm) can be added to the LSl-11 processor, via a socket available on the microcomputer module, to extend the
instruction set to include fixed and floating point arithmetic instructions.

1-4

1.5.1 General Registers
The LSl-11 central processor module contains eight 16-bit general-purpose registers that can perform a variety of functions. These registers
can serve as accumulators, index registers, autoincrement registers, autodecrement registers, or as stack pointers for temporary storage of data.
Arithmetic operations can be from one general register to another, from
one memory location or device register to another, or between memory
locations or a device register and a general register. The following illustration identifies the eight 16-bit general registers RO through R7.

GENERAL
REGISTERS

RO
Rl
R2
RJ
R•
RS
R6

It SP)

STACK POINTER
R7

ltPC)

PROGAAM COUNTER

Figure 1-2

General Register Identification

Registers R6 and R7 in the LSl-11 are dedicated. R6 normally serves
as the Stack Pointer (SP) and contains the location (address) of the last
entry in the stack. Register R7 serves as the processor's Program
Counter (PC) and contains the address of the next instruction to be executed. It is normally used for addressing purposes only and not as an
accumulator. Register operations are internal to the processor and do
not require bus cycles (except for instruction fetch); all memory and
peripheral device data transfers do require bus cycles and longer execution time. Thus, general registers used for processor operations result in
faster execution times. The bus cycles required for memory and device
references are described below.
Bus Cycles
The bus cycles (with respect to the processor) are:
DATI

Data word transfer in

DATIO

Data word transfer in, followed by word transfer out

Equivalent to Read operati on
Equivalent to Read/ Modify
Write

DATIOB

Data word transfer in, followed by byte transfer out

Equivalent to Read/ Modify
Write

DATO

Data word transfer out

DATOB

Data byte transfer out

Equivalent to Write operati on
Equivalent to Write operati on

1-5

Every processor instruction requires one or more bus cycles. The first
operation required is a DATI, which fetches an instruction from the location addressed by the Program Counter (R7). If no further operands are
referenced in memory or in an 1/0 device, no additional bus cycles are
required for instruction execution. If memory or a device is referenced,
however, one or more additional bus cycles are required.
Note the distinction between interrupts and DMA operations: Interrupts,
which may change the state of the processor, can occur only between
processor instructions; DMA operations can occur between individual bus
cycles since these operations do not change the state of the processor.
Addressing Memory and Peripherals
The maximum direct address space of the LSl-11 is 32K 16-bit words of
memory. LSl-ll's memory locations and peripheral device registers are
addressed in precisely the same manner. The upper 4096 addresses
(28K-32K) are usually reserved by convention for peripheral device addressing. However, the user does not need to dedicate the entire 4K
space to 1/0; he can implement only what he needs.

An LSl-ll word is divided into a high byte and a low byte as shown
below.
0

LOW PifTE:

: HIGH: BYTE :
I

Figure 1-3

High and Low Byte

Word addresses are always even-numbered. Byte addresses can be either
even- or odd-numbered. Low bytes are stored at even-numbered memory
locations and high bytes at odd-numbered memory locations. Thus, it is
convenient to view the memory as:
16-BIT WORD
BYTE

BYTE

HIGH
HIGH
HIGH

LOW
LOW
LOW

8-BIT BYTE

000000
000002
000004

LOW
HIGH
LOW
HIGH
LOW

___.-"'.'.

HIGH

LOW

HIGH
HIGH

LOW
LOW

01 7772
01 7774
017776

WORD ORGANIZATION

Figure 1-4

000000
000001
000002
000003
000004

HIGH
LOW
HIGH

01 7775
017776
017777

BYTE ORGANIZATION

Word and Byte Addresses for First 4K Bank

1-6

Certain memory locations have been reserved by convention for interrupt
and trap handling and peripheral device registers. Addresses from O to
376 8 are usually reserved for trap and device interrupt vector locations.
Several of these are reserved in particular for system (processor in·
itiated) traps.
1.5.2

The Processor Status Word (PSW)
0

[~=~=~~~~---~~=~=-~---~~~Rl-ORTY~:~r~l_N_l_z~l_v~I~cI

) 1 UJ:~'°"

~------NEGATIVE
'---------TRACE TRAP

Figure 1-5

Processor Status Word (PSW)

The Processor Status Word (PSW) contains information on the current
processor status. This information includes the current processor priority,
the condition codes describing the arithmetic or logical results of the
last instruction, and an indicator for detecting the execution of an in·
struction to be trapped during program debugging. The PS word format
is shown above. Certain instructions allow programmed manipulation of
condition code bits and loading or storing (moving) the PSW. The two
instructions for explicitly accessing the PSW are described in Chapter 4.
Priority Interrupt Bit
The processor operates with interrupt priority PSW bit 7 asserted (1) or
cleared (0). When PSW bit 7
1, an external device cannot interrupt the
processor with a request for service. The processor must be operating at
PSW bit 7
0 for the device's request to take effect. As compared to
other PDP-ll's, the LSl-11 operates at 1 line multi level priority.

Condition Codes
The condition codes contain information on the result of the last CPU
operation. The bits are set as follows: (The bits are set after execution
of all arithmetic or logical single operand or double operand instructions.)
Z
N
C

= 1, if the result were zero
= 1, if the result were negative
= l, if the operation resulted in a carry from the MSB (most

significant bit) or a 1 were shifted from MSB or LSB (least
significant bit)
1, if the operation resulted in an arithmetic overflow

Trap (T Bit)
The program can only set or clear the trap bit (T) by popping a new PSW
off the stack. When set, a processor trap will occur through location 14 at
completion of the current instruction execution, and a new processor
status word will be loaded from location 16. This T b"1t is especia\ly useful in debugging programs as an efficient method of installing breakpoints.

1-7

1.5.3 Instruction Set
Implementing the PDP-11 instruction repertoire in the LSI chip set permits the user to take advantage of Digital Equipment Corporation's years
of experience with the PDP-11 family-more than 17,000 units installed,
with all associated application notes, software, documentation, training,
reliability, customer references, and the DECUS library of application
programs.
The instruction complement uses the flexibility of the general-purpose
registers to provide more than 400 powerful hard-wired instructionsthe most comprehensive and powerful instruction repertoire of any computer in the 16-bit class. Unlike conventional 16-bit computers, which
usually have three classes of instructions (memory reference instructions, operate or accumulator control instructions, and 1/0 instructions),
all data manipulation operations in the LSl-11 are accomplished with
one set of instructions. Since peripheral device registers can be manipulated as flexibly as memory by the central processor, instructions that
are used to manipulate data in memory can be used equally well for data
in peripheral device registers. For example, data in an external device
register can be tested or modified directly by the CPU without bringing it
into memory or disturbing the general registers. One can add or compare data logically or·arithmetically in a device register.
The basic order code of the LSl-11 uses both single and double operand
address instructions for words or bytes. The LSl-11 therefore performs
very efficiently in one step such operations as adding or subtracting two
operands or moving an operand from one location to another.
LSl-11 Approach
ADD A, B

Add contents of location A to location B;
store results at location B

Conventional Approach

LOA A

Load contents of memory location A into
accumulator

ADD B

Add contents of memory location B to accumulator

STA B

Store result at location B

Addressing
Much of the power of the LSl-11 is derived from its wide range of addressing capabilities. LSl-11 addressing modes include sequential forward or backward addressing, address indexing, indirect addressing, 16bit word addressing, 8-bit byte addressing, and stack addressing. Variable-length instruction formatting allows a minimum number of words
to be used for each addressing mode. The result is efficient use of program storage space.

1-8

1.6 LSl·ll MEMORY ORGANIZATION
The LSl-11 processor organization and addressing, register, memory, and
device addresses are shown.
RESERVED VECTOR LOCATIONS
4 BUS ERROR, TIME OUT
O ~--------.
10 RESERVED
14 BPT TRAP INSTRUCTION, T BIT
~ !OT EXECUTED
DEVICE INTERRURT
AND SYSTEM
24 PONER FAIL/RESTART
TRAP VECTORS
} 30 EMT EXECUTED
34 TRAP EXECUTED
1

PROCESSOR
MODULE
RESICfNT
READ/WRITE
MEMORY(4K)

!6~ ~============: ~ ~~ ~~~D~ ~1~
100 EXTERNAL EVENT
LINE NTERRUPT
244 FIS TRAP
17 7 7 6

USER AND SYSTEM
PROGRAMS AND
STACK(S)

~MORY

ADORESS
(28K LOCATIOllS)

NOTE:
DEVICE VECTORS AND
DEVICE ADDRESSES
ARE SELECTED BY
JUMPERS LOCATED ON
THE DEVICE NTERl'ACE MODULES

OPTIONAL
MEMORY

32K MAXIMUM
WORD LOCATIONS

_. . . ____. . ._ __

:~~~~~::=========:}
DEVICE & REGISTER

=~=~OFOR

DEVICE ADDR., ETC:

- - - - ' ' - - - - - - - - - LOC 177776 ....___ _ _ _ ___,
MEMORY ORGANIZATION

NOTE
There is 32K of users memory space available;
however 0-28K is recommended for memory address locations, and 28K-32K for peripherals
1/0 device addresses, etc.
Figure 1-6

Memory Organization

1-9

1.7 LSl·ll BUS
The LSl·ll bus is a simple, fast, easy-to-use interface between LSl-11
modules. All LSl-11 modules connected to this common bidirectional bus
structure receive the same interface signal lines. A typical system application in which the processor module, memory modules, and periph·
eral device interface modules are connected to the bus is shown in Figure
1·7.
KEYBOARD ANO
CRT DtSPl.AY l/O

OoUAJCONTROI.

TO/FROM
USER'S DEVICE -~--~

TO/FROM VT50

DECSCOPE OR
LA36 TELEPRNTER

4K
PROM
PROCESSOR
MODULE

AND 41(
~ITE

MEMORY

Figure 1·7

Typical Bus Application

Bus data and control lines are bidirectional open-collector lines that are
asserted low. The bus is comprised of 16 data/address lines (BOAL
0-15), and 17 control/synchronization signal lines, and system function
lines.
Control signal lines include two daisy-chained grant signals (four signal
pins), which provide a priority-structured 1/0 system. The highest priority
device is the module located electrically closest to the microcomputer
module. Higher priority devices pass a grant signal to lower priority de·
vices only when not requesting service. For example, "Module A," shown
in figure 1·8, is the highest priority device, and is capable of interrupting
processor operation and/or executing OMA transfers. Modules B and C
have lower priorities, respectively. Module B can receive a grant signal
when Module A is not asserting a request. Similarly, Module C can re·
ceive a grant signal when both Modules A and B are not asserting a re·
quest.
Both 16-bit address and 16·bit data words (or data bytes) are multi·
plexed over the 16 BOAL lines of the LSl·ll bus. For example, during a
programmed data transfer, the processor will assert an address on ttre
bus for a fixed time.

1·10

HIGHEST
PRIORTY
DEVICE

~-----.

KDIH

MICRO·
COMPUTER

DECREASING FRIORITY -

BIAK
~E

MOOULE
8 .

MOOUlE

MODULE
(CO'HAINS4K
READIWRITE
RAM)

BIAIC

PRIORITY
STRUCTURED
DAISY-CHAINED

WAtiJij8"~

SYSTEM MODULES
REQUEST
SIGNALS
FROM
ADDITIONAL
} SYSTEM
MOOULES

Figure 1-8

Bus Priority Structure

After the address time has been completed, the processor initiates the
programmed input or output data transfer. The actual data transfer is
asynchronous and requires a reply from the addressed device; bus synchronization and control signals provide this function.
The processor module is capable of driving six device slots (doubleheight) along the bus without additional termination, as provided with the
H9270 backplane. Devices or memory can be installed in any location
along this bus, as long as the desired priority order of the devices is
maintained. Position 1 (figure 1-9) has the highest priority, position 6
the lowest.

COMPONENT SIDE UP
PROCESSOI!
POSITION 2
POSITION 3
POSITION 6

POSITION 1
POSITION 4
POSITION S

8
C
(MODULE INSERTION SIDE)

Figure 1-9

Devices Priority Guide

The bus protocal allows for a vectored interrupt by the device. Hence,
device polling is not required in interrupt processing routines. This results in a considerable savings in processing time when many devices
requiring interrupt service are interfaced along the bus. When an interrupting device receives an interrupt grant signal, the device passes to the
processor, an interrupt vector. The vector points to two addresses which
contain a new processor status word and the starting address of the in·
terrupt service routine for the particular device.
One bus signal line (BEVNT) functions as an external event interrupt line
via the processor module. This signal line can be connected to a 60 Hz
line frequency source, and can be used as a real-time interrupt. A wire
wrap connection on the processor module enables or inhibits this function. When enabled, the device connected to this line has the highest in·
terrupt priority external to the processor. Interrupt vector 1008 is reserved for this function, and an interrupt request via the external event
line causes new PC and PS words to be loaded from locations 1008 and
1028.

1-11

1.7.1 Bidirectional Lines
With bidirectional and asynchronous communications on the LSl-11 bus,
devices can send, receive, and exchange data at their own rates. The
bidirectional nature of the bus allows utilization of common bus interfaces for different devices, and simplifies the interface design.
1. 7 .2 Master Slave Relation
Communication between two devices on the bus is in the form of a
master-slave relationship. At any point in time, there is one device that
has control of the bus. This controlling device is termed the "bus master." The master device controls the bus when communicating with
another device on the bus, termed the "slave." A typical example of this
relationship is the processor, as master, fetching an instruction from
memory (which is always a slave). Another example is a DMA device interface, as master, transferring data to memory, as slave. Bus master
control is dynamic. The bus arbitrator on the processor module, for example, may pass bus control to a DMA device. The DMA device, as master, could then communicate with a slave memory bank.
Since the LSl-11 bus is used by the processor and all 1/0 devices, there
is a priority structure to determine which device gets control of the bus.
Every device on the LSl-11 bus which is capable of becoming bus master
is assigned a priority according to its position along the bus. When two
devices which are capable of becoming a bus master request use of the
bus simultaneously, the device with the higher priority position will receive control.
1.7.3 lnlerlocked Communication
Data transfer on the LSl-11 bus is interlocked so that communication is
independent of the physica(bus length and the response time of the
slave device. The asynchronous operation precludes the need for synchronizing with, and waiting for, clock impulses. Thus, each device isallowed to operate at the maximum possible speed.
Full 16-bit words or 8-bit bytes of information can be transferred on the
bus between a master and a slave. The information can be instructions',
addresses, or data. This type of information transfer occurs when the
processor, as master, is fetching instructions, operands, and data from
memory, and storing the results into memory after execution of the instruction.

1-12

CHAPTER 2

SPECI FICATIO NS
2.1 LSl-11 OPERATING SPECIFICATIONS
Tables 2-1 and 2-2 list the electrical and mechanical specifications of the
LSl-11 options. All LSl-11 modules will operate at temperatures of 41 ° F
to 122°F (5°C to 50°C) with a relative humidity of 10% to 95% (no
condensation), with adequate airflow across the modules.
TABLE 2-1
LSl-11
Nomenclature

LSl-11 ELECTRICAL SPECIFICATIONS

Module
Description

Power Requirements*
+12V±3%**

v ±5%**

KDII-F

Microcomputer with
4K X 16 RAM

I.SA (Typ)
2.4A (Max)

O.SA (Typ)
I.IA (Max)

MSVII-A

lK X 16 RAM

O.SA (Typ)
I.SA (Max)

0.IA (Typ)
O.IA (Max)

MSVll-B

4K X 16 RAM

0.6A (Typ)
l.lA (Max)

0.3A (Typ)
0.6A (Max)

MRVll-AA 4K X 16 PROM/ ROM
(OK implemented)
0.2A (Typ)
0.4A (Max)
2.SA (Typ)
(4K implemented)
4.IA (Max)
MMVll·A

4K x 16 Core

3.0A (Stby) (Max) 0.2A (Stby) (Max)
7.0A (Optg) (Max) 0.6A (Optg) (Max)

DLVll

Serial Line Unit

1.0A (Typ)
I.GA (Max)

DRVII

Parallel Line Unit

O.SA (Typ)
1.3A (Max)

0.ISOA (Typ)
0.250A (Max)

*Preliminary
**At the module connector
For all Modules:
Electrical Input Logic Levels:

Electrical Output Logic Levels:
Bus Low: O.S Vdc Max
Bus High: 2.7 Vdc Min

Bus Low: 1.3 Vdc Max
Bus High: 1.7 Vdc Min
2-1

TABLE 2·2

MECHANICAL SPECIFICATIONS
Module
Dimension
(Tolerance ± 0.05")

LSl·ll
Nomenclature

10.436 x 8.50 x 0.5"
10.436 x 8.50 x 0.9"
10.436 x 8.50 x 0.5"
5.187 x 8.50 x 0.5"
5.187 x 8.50 x 0.5"
5.187 x 8.50 x 0.5"
10.436 x 8.50 x 0.9"
5.187 x 8.50 x 0.5"
5.187 x 8.50 x 0.5"
11.15 x 11.0 x 2._80"

KDll·F
KDll·J
MSVll·A
MSVll·B
MRVll·AA
MMVll·A
DLVll
DRVll
H9270

2.2 PDP·ll/03 OPERATING SPECIFICATIONS
Table 2·3 lists the environmental and electrical specifications of the
PDP·ll/03.
TABLE 2·3

PDP 11/03

OPERATING SPECIFICATIONS

Temperature
Relative Humidity

41°F to 122°F (5°C to 50°C)
10% to 95% (no condensation)

Input Voltage:
PDP-11/03-AA, BA

90-132 Vac, 115 Vac nominal,
47-63 Hz
180-264 Vac, 230 nominal,
47-63 Hz

PDP·ll/03·AB, BB
Input Power:
PDP-11/03-AA, AB, BA, BB

210 watts max at full load,
190 watts typical at full load

2.3 H9270 BACKPLANE PACKAGING AND MOUNTING
The H9270 Backplane (Figure 2-1) is designed to accept the KDll-F
or KDll-J microcomputer and up to six 1/0 interface modules, or memory modules. Mounting of the H9270 backplane can be accomplished in
any one of three planes, as shown in Figure 2-1.
2.4 PDP·ll/03 PACKAGING AND MOUNTING
The PDP-11/03 shown in Figure 2-2 is offered in the following versions:
Designation
PDP-11/03-AA

4K RAM Configuration (KDl 1-F), 115 Vac

Description

PDP-11/03-AB

4K RAM Configuration (KDl 1-F), 230 Vac

PDP-11/03-BA

4K Core Configuration (KDl 1-J), 115 Vac

PDP-11/03-BB

4K Core Configuration (KDl 1-J), 230 Vac

2-2

The PDP-11/03 is designed with a removable front panel. Removing the
front panel exposes the LSI modules and cables. This enables replacement or installation of a module from the front of the PDP-11/03. The
11/03 power supply is located on the right-hand side of the PDP-11/03
when viewed from the front. The power supply contains three front
panel switches and indicators which are accessible through a cutout in
the front panel. Therefore, when the front panel is removed, the lights
and switches are still attached and functional.
The PDP-11/03 is designed to mount in a standard 19" cabinet (Figure
2-3). A standard 19" cabinet has two rows of mounting holes in the
front, spaced 18Yi6" apart. The holes are located If2" or % " apart from
each other. Standard front panel increments are 1 % ".

MOUNTING
BRACKET
0.218"DIA

HOLES
(4 PLACES)

Figure 2-1

H9270 Backplane Mounting (SHT 1 of 2)

2-3

SIDE MOUNTING
0.187 DIA HOLES
4 PLACES

REAR MOUNTING

OCNNECT

10-32 THDx0.5" LONG

0.31 ' -

/T"'EADEDSTUO{HCACESJ

i
I

'~-1~;~1:"·· -==--0"

BLOCK

...

VIEW FROM REAR OF BACKPLANE

TOP AND BOTTOM MOUNTING

I·

11.15"

9.04"

6-32 THD HOLE
xo.25" DEEP

---- -----9- ---- - - - - --:@'

5.250"

Figure 2-1

Backplane Mounting (SHT 2 of 2)

2-4

C=:J IT
l....t:::========:lj_l

3-112"

i
r

f--1·1/2"

19"------~

13.50"
POWER SUPPLY
AIR

AIR ·
/I

.....__

FRONT

PROCESSOR,
MEMORY AND
DEVICES

Figure 2-2

PDP-11/03 Assembly Unit

2-5

FRONT VIEW

a ~r
o--z--------- _1_1_
T
+
114"

518"

TOP OF A STANDARD
FRONT PANEL

1-3/4"

3-112"

518"

t.
0 +

--- 0
0

0
0

518"

*·

5/8"

------ 90 _k

-------18-5/16"-------

l---

18-5/16''-------L.19" TYP

-u--~3/8" TYP

~,--~.-.-r-----------------,.-.:

3.50" 1.75"

FRONT OF BOX( PANEL REMOVED)

~._•.....___ _ _ _ _ _ _ _ _ _ _ _ ___..___.ci:I 114" TYP

19"

3.50'

FRONT

_l__._____ _ _ _t-_

~13~"
Figure 2-3

~ ~.,..

PDP-11/03 Cabinet Mounting

2-6

CHAPTER 3

ADDRESSING MODES
Data stored in memory must be accessed and manipulated. Data han·
dling is specified by an LSl·ll instruction (MOV, ADD, etc.), which
usually indicates:
• The function (operation code).
• A general-purpose register is to be used when locating the source aper·
and and/or a general-purpose register to be used when locating the
destination operand.
• An addressing mode (to specify how the selected register(s) is/are to
be used).
A large portion of the data handled by a computer is usually structured
(in character strings, arrays, lists, etc.). LSl-ll's addressing modes provide for efficient and flexible handling of structured data.
The general registers may be used with an instruction in any of the
following ways:
• As accumulators. The data to be manipulated resides within the register.
• As pointers. The contents of the register is the address of the operand,
rather than the operand itself.
• As pointers which automatically step through memory lo~ations. Auto·
matically stepping forward through consecutive locations is known as
autoincrement addressing; automatically stepping backwards is known
as autodecrement addressing. These modes are particularly useful for
processing tabular or array data.
• As index registers. In this instance, the contents of the register and
the word following the instruction are summed to produce the address
- -Of the operand. This allows easy access to variable entries in a list.
An important LSl-11 feature, which should be considered in conjunction
with the addressing modes, is the register arrangement:
• Six general-purpose registers (RO - RS)
• A hardware Stack Pointer (SP), register (R6)
• A Program Counter (PC}, register (R7)
Registers RO through RS are not dedicated to any specific function; their
use is determined by the instruction that is decoded:
• They can be used for operand storage. For example, contents of two
registers can be added and stored in another register.
• They can contain the address of an operand or serve as pointers to
the address o! an operand.
• They can be used for the autoincrement or autodecrement features.
• They can be used as index registers for convenient data and program
access.

3·1

The LSl-11 also has instruction addressing mode combinations that facilitate temporary data storage structures. This can be used for convenient
handling of data which must be frequently accessed. This is known as
stack manipulation. The register used to keep track of stack manipulation is known as the stack pointer. Any register can be used as a "stack
pointer" under program control; however, certain instructions associated
with subroutine linkage and interrupt service automatically use Register
R6 as a "hardware stack pointer." For this reason, R6 is frequently referred to as the "SP":

• The stack pointer (SP) keeps track of the latest entry on the stack.
• The stack pointer moves down as items are added to the stack and
moves up as items are removed. Therefore, it always points to the top
of the stack.
• The hardware stack is used during trap or interrupt handling to store
information allowing the processor to return to the main program.
Register R7 is used by the processor as its program counter (PC). It is
recommended that R7 not be used as a stack pointer or accumulator.
Whenever an instruction is fetched from memory, the program counter
is automatically incremented by two to point to the next instruction
word.
The next section is divided into seven major categories:
• Single Operand Addressing-One part of the instruction word specifies a
register; the second part provides information for locating the operand.
• Double Operand Addressing-part of the instruction word specifies the
registers; the remaining parts provide information for locating two
operands.
• Direct Addressing-The operand is the contents of the selected register.
• Deferred (Indirect) Addressing-The contents of the selected register
is the address of the operand.
• Use of the PC as a General Register-The PC is unique from other
general-purpose registers in one important respect. Whenever the
processor retrieves an instruction, it automatically advances the PC
by 2. By combining this automatic advancement of the PC with four
of the basic addressing modes, we produce the four special PC modes
-immediate, absolute, relative, and relative deferred.
• Use of Stack Pointer as General Register-Can be used for stack
operations.
• Summary of Addressing Modes
NOTE
Instruction mnemonics and address mode symbols are sufficient for writing assembly language
programs. The programmer need not be concerned about conversion to binary digits; this
is accomplished automatically by the assembler
program.
3-2

3.1 SINGLE OPERAND ADDRESSING
The instruction format for all single operand instructions (such as clear,
increment, test) is:

MODE

OP CODE---~
DESTINATION ADDRESS----------~

Bits 15 through 6 specify the operation code that defines the type of in·
struction to be executed.
Bits 5 through 0 form a six-bit field called the destination address field.
This consists of two subfields:
a) Bits O through 2 specify which of the eight general purpose registers
is to be referenced by this instruction word.
b) Bits 3 through 5 specify how the selected register will be used (ad·
dress mode). Bit 3 is· set to indicate deferred (indirect) addressing.

3.2 DOUBLE OPERAND ADDRESSING
Operations which imply two operands (such as add, subtract, move and
compare) are handled by instructions that specify two addresses. The
first operand is called the source operand, the second the destination
operand. Bit assignments in the source and destination address ffelds
may specify different modes and different registers. The Instruction
format for the double operand instruction is:

OP CODE
15

MODE
12

Rn
9

MOOE

SOURCE ADDRESS~--~
DESTINATION A D D R E S S - - - - - - - - - - - - - '

The source address field is used to select the source operand, the first
operand. The destination is used similarly, and locates the second operand and the result. For example, the instruction ADD A, B adds the
contents (source operand) of location A to the contents (destination
operand) of location B. After execution B will contain the result of the
addition and the contents of A will be unchanged.
·

3-3

Examples in this section and further in this chapter use the following
sample LSl-11 instructions. A complete listing -0f the LSl-11 instructions
is located in the appendix.

Mnemonic

, Description

Octal Code

CLR

clear (zero the specified destination)

0050DD

CLRB

clear byte (zero the byte in the specified
destination)

1050DD

INC

increment (add 1 to contents of destination)

0052DD

INCB

increment byte (add 1 to the ~ntents of
destination byte)

1052DD

COM

complement (replace the contents of the
destination by their logical complement;
each 0 bit is set and each 1 bit is cleared)

0051 DD

COMB

complement byte (replace the contents of the
destination byte by their logical complement;
each 0 bit is set and each 1 bit is cleared).

1051DD

ADD

add (add source operand to destination
operand and store the result at destination
address)

06SSDD

DD = destination field (6 bits)
SS = sourc~ field (6 bits)
) =contents of

3-4

3.3 DIRECT ADDRESSING
The following table summarizes the four basic modes used with direct addressing.-

Dl RECT MODES
Mode

Name

Assembler
Syntax

INSTRUCTION

(Rn)+

-(Rn)

ADDRESS

INSTRUCTION

X(Rn)

Index

OPERAND

ADDRESS

Autodecrement

1NSTRUCTION ~

Autoincrement

Function

: '"'7"0N

OPERAND

Value X is added to (Rn) to produce address of operand. Neither X nor (Rn) are modified.

~r-----A-00-R-ES-S-~~
+

_OPE_R_AN_O__.

3.3.1 Register Mode
OPR Rn
With register mode any of the general registers may be used as simple
accumulators and the operand is contained in the selected register. Since
they are hardware registers, within the processor, the general registers
operate at high-speeds and provide speed advantages when used for
operating on frequently-accessed variables. The assembler interprets
and assembles instructions of the form OPR Rn as register mode operations. Rn represents a general register name or number and OPR is
used to represent a general instruction mnemonic. Assembler syntax requires that a general register be defined as follows:
RO= %0

(% sign indicates register definition)

= %1

R2 -

%2, etc.

3-5

Registers are typically referred to by name as RO, Rl, R2, R3, R4, R5,
R6 and R7. However R6 and R7 are also referred to as SP and PC,
respectively.

Symbolic

Octal Code

Instruction Name

INC R3

005203

Increment

Operation:

Add one to the contents of general register 3

R0
RI
R2

._l_o_._o_.._o_.__o_.__.._o_.___.._o_.._,__o~j_o_.._o_._)_o~l~o-·....__._~1l~~~~R.
~·---~~-----6- '-5

R3
R4

0
~·

OP CODE (INC(0052))_J
DESTINATION FIELD-----------~

R6(SP)
R7 (PC)

ADDR2,R4

Add

060204

Operation:

Add the contents of R2 to the contents of R4.

BEFORE
R2

AFTER
00000
__
2~

. _ I_ _

I __._o_ooo_04__

. _ I_ _

R4 ...

o_oo_o_o_s__,,

Complement Byte

105104

COMBR4

0_0_000_2__,,

One's complement bits 0-7 (byte) in R4. (When
general registers are used, byte instructions only
operate on bits 0-7; i.e. byte 0 of the register)

Operation:

BEFORE
R4

AFTER
02<!222

3-6

022155

3.3.2 Autoincrement Mode
OPR (Rn)+
This mode provides for automatic stepping of a pointer through sequential elements of a table of operands. It assumes the contents of the
selected general register to be the address of the operand. Contents of
registers are stepped (by one for bytes, by two for words, always by
two for R6 and R7) to address the next sequential location. The autoincrement mode is especially useful for array processing and stack processing. It will access an element of a table and then step the pointer to
address the next operand in the table. Although most useful for table
handling, this mode is completely general and may be used for a variety
of purposes.

Autoincrement Mode Examples
Symbolic
Octal Code

005025

CLR (R5)+

Operation:

005025

030000

~
I 111!11s I

005025

30000

000000

I __03_0_00_2_

R5 __

Clear Byte

Use contents of R5 as the address of the operand.
Clear selected byte operand and then increment
the contents of R5 by one.

BEFORE
AIDRESS SPACE

I 20000

105025

CLRB(R5)+

Operation:

20000

AFTER
ADDRESS SPACE

30000

Clear

Use contents of R5 as the address of the operand.
Clear selected operand and then increment the
contents of R5 by two.

BEFORE
ADDRESS SPACE

20000

Instruction Name

105025

AFTER
ADDRESS SPACE

030000

30000~
30002~

I 20000

3-7

105025

1-1-11__._oo_o_

R5 l....__0_3_00_0_1____.

ADD(R2)+,R4

Add

062204

The contents of R2 are used as the address of the
operand which is added to the contents of R4. R2
is then incremented by two.

Operation:

AFTER
AOORESSSIW:ES

REGISTERS
10000

062204

REGISTERS

112

100004

020000

010000

1000021

3.3.3 Autodecrement Mode (Mode 4)
OPR-(Rn)
This mode is useful for processing data in a list in reverse direction.
The contents of the selected general register are decremented (by two
for word instructions, by one for byte instructions) and then used as
the address of the operand. The choice of postincrement, predecrement
features for the LSl-11 were not arbitrary decisions, but were intended
to facilitate hardware/software stack operations.

Autodecrement Mode Examples

Symbolic

Octal Code

Instruction Name

INC-(RO)

005240

Increment

Operation:

The contents of RO are decremented by two
and used as the address of the operand. The
operand is incremented by one.

AFTER

BEFORE

, ooo I

005240

000000

11114

INCB-(RO)

Operation:

RCil

ADDRESS SPACE

REGISTERS

ADDRESS SPACE

1000

017776

005240

017774

17774

105240

jOOOOot

Increment Byte

The contents of RO are decremented by one then
used as the address of the operand. The operand
byte is increased by one.

3-8

AFTER

BEFORE

1000

AOORESS SPACE
105240

RGI

017776

1000

ADDRESS SPACE

10!1240

000
177741 000
17776 .__ ___._____

ADD-(R3),RO

064300

Operation:

The contents of R3 are decremented by 2 then
used as a pointer to an operand (source) which is
added to the contents of RO (destination operand).

064300

AFTER
AOORESSSPACE

ADDRESS SPACE

10020

Add

Rf)

000020

10020

064300

0000010

R3 _, _ _
r:n_1_11_& _ _

: : : ,....__
ooooso
_ __

3.3.4 Index Mode (Mode 6)
OPR X{Rn)

The contents of the selected general register, and ~n index word following the in·
struction word, are summed to form the address of the operand. The contents of
the selected register may be used as a base for calculating a series of addresses,
thus allowing random access to elements of data structures. The selected register
can then be modified by program to access data in the table. Index addressing instructions are of the form OPR X(Rn) where X is the indexed word and is located
in the memory location following the instruction word and Rn is the selected general register.

Index Mode Examples
1.

Symbolic

Octal Code

Instruction Name

CLR 200{R4)

005064
000200

Clear

Operation:

The address of the operand is determined by
adding 200 to the contents of R4. The operand location is then cleared.

3.9

AFTER

BEFORE
REGISTER

AOORESS SPACE

/a __

1020~05064
1022

ADDRESS SPACE

l..___oo_•ooo
___,

000200

1024

005064

1022

000200

I __0_0_10_0_0_ _,

R4 ..

1024

!000
.+200

1200

1020

1200

1202

COMB 200(Rl)

Complement Byte

105161
000200

The contents of a location which is determined by
adding 200 to the contents of Rl are one's complemented. (i.e. logically complemented)

Operation:

BEFORE

AFTER

ADDRESS SPACE

1020

105161

1022

000200

201761
20200

011!000

ADD 30(R2),20(R5) 066265
000030
000020

017777

1020

105161

!022

000200

201761
20200

166:000

017777

~--------- 01777
+200
7
-020177

The contents of a location which is determined by
adding 30 to the contents of R2 are added to the
contents of a location which is determined by ad·
ding 20 to the contents of R5. The result is stored
at the destination address, i.e, 20(R5)

Operation:

BEFORE
ADDRESS SPACE

1020~265

1022

000030

1024

1130

000020

2020 1

Add

AFTER
ADDRESS SPACE

I
R5 I
R2

001100
002000

1020

066265

1022

000030

1024

000001

1130

000001

2020

1100
+30

2000
+20

li30

2620

3-10

000020

000001

000002

__,

l.___00_20_00_ _.....

3.4 DEFERRED (INDIRECT) ADDRESSING
The four basic modes may also be used with deferred addressing. Whereas
in the register mode the operand is the contents of the selected register.
In the register deferred mode the contents of the selected register is the
address of the operand.
In the three other deferred modes, the contents of the register selects
the address of the operand rather than the operand itself. These modes
are therefore used when a table consists of addresses rather than operands. Assembler syntax for indicating deferred addressing is "@"(or
"( )" when this is not ambiguous). The following table summarizes the
deferred versions of the basic modes:
Mode

Name

Assembler'
Syntax
@Rn or (Rn)

Function

IINSTRUCTION 1------f OPERAND I
3

Autoincrement Deferred

@(Rn)

+ Register is first used as a
pointer to a word containing
the address of the operand,
then incremented (always by
2; even for byte instructions).

I WST~~· 1------f

'°j"' T.__AOO_R-ES_S_~_ ~~~
•2

Autodecrement Deferred

I 1NSTRUCTION 1------f A O ' 1------f
Index Deferred

WST,.,XCTOON

@-(Rn) Register is decremented (always by two; even for byte instructions) and then used as
a pointer to a word containing
the address of the operand.
-2

ADDRESS

1------f

OPERAND .

@X(Rn) Value X (stored in a word following the instruction) and
(Rn) are added and the sum
is used as a pointer to a
word containing the address
of the operand. Neither X nor
(Rn) are modified.
AOORESS

---~~------~~
+
ADDRESS

-:
:

3-11

OPERAND

The following examples illustrate the deferred modes.
Register Deferred Mode Example
Symbolic

Octal Code

Instruction Name

CLR @R5

005015

Clear

Operation:

The contents of location specified in R5 are
cleared.

BEFORE
ADDRESS SPACE

AFTER
REGISTER

AOORESS SPACE

I __00_1_1_00_ __.

: : 11---000-1-00--

:: 1--00000--0--

R5 ..

1_ _00_1_1_00_ _ _

Autoincrement Deferred Mode Example (Mode 3)
Symbolic
Octal Code Instruction Name
INC@(R2) +

005232

Operation:

Increment

The contents of R2 are used as the address of the ·
address of the operana.
Operand is increased by one. Contents of R2 is incremented by 2.
,

BEFORE

AFTER

ADDRESS SPACE

1010~

ADDRESS SPACE

1010~

010300

010302

1012~

10300

,l-__00_1_01_0_~

Autodecrement Deferred Mode Example (Mode 5)
Symbolic

Octal Code

COM @·(RO)

005150

Operation:

Complement

The contents of RO are decremented by two and
then used as the address of the address of the operand. Operand is one's complemented. (i.e. logically complemented)
AFTER
ADORESS SPACE

BEFORE
REGISTER

ADDRESS SPACE

10100 l--°'-23_45
__

l__o 1_0_11_s_.....

10102 •

____

10774 ·~_ _
0_10_100
__
10776

___,

~:,.

.- ;~;:
3-12

010100

Index Deferred Mode Example (Mode 7)
Symbolic
ADD@ 1000(R2),Rl
Operation:

067201

1022

001000

000002

067201
001000

Add

AFTER
AOORESS SPACE

1024

1050

Instruction Name

1000 and contents of R2 are summed to produce
the address of the address of the source operand
the contents of which are added to contents of Rl;
the result is stored in Rl.

BEFORE
ADDRESS SPACE
1020

Octal Code

I
I

001234
000100

001050

067201

1022

001000

1024

11~0
'-c===:l

1020

10501

1000

1100

_+100

I
I

001236
000100

000002

001050

~1100

3.5 USE OF THE PC AS A GENERAL REGISTER
Although Register 7 is a general purpose register, it doubles in function
as the Program Counter for the LSl-11. Whenever the processor uses· the
program counter to acquire a word from memory, the program counter
is automatically incremented by two to contain the address of the next
word of the instruction being executed or the address of the next instruction to be executed. (When the program uses the PC to locate byte data,
the PC is still incremented by two.)
The PC responds to all the standard LSl-11 addressing modes. However,
there are four of these modes with which the PC can provide advantages
for handling position independent code and unstructured data. When
utilizing the PC these modes are termed immediate, absolute (or immediate deferred), relative and relative deferred, and are summarized
below:
Mode

Name

Assembler
Syntax

Function

Immediate

Operand follows instruction

Absolute

@#A

Absolute Address of operand
follows instruction

Relative

Relative Address (index value)
follows the instruction.

Relative Deferred

Index value (stored in the
word following the instruction)
is the relative address for the
address of the operand.
3-13

The reader should remember that the special PC modes are the same as
modes described in 3.3 and 3.4,, but the general register selected is R7,
the program counter.
When a standard program is available for different users, it often is helpful to be able to load it into different areas of memory and run it there.
LSl-11 's can accomplish the relocation of a program very efficiently
through the use of position independent code (PIC) which is written by
using the PC addressing modes. If an instruction and its operands are
moved in such a way that the relative distance between them is not
altered, the same offset relative to the PC can be used in all positions
in memory. Thus, PIC usually references locations relative to the current
location.
The PC also greatly faciiitates the handling of unstructured data. This is
particularly true of the immediate and relative modes.

3.5.1 Immediate Mode
OPR #n,DD

Immediate mode is equivalent to using the autoincrement mode with the PC. It
provides time· improvements for accessing constant operands by including the
constant in the memo..Y location immediately following the instruction word.

Immediate Mode Example
Symbolic
ADD #10,RO

Octal Code

Instruction Name

062700

Add

000010
The value 10 is located in the second word of the
instruction and is added to the contents of RO.
Just before this instruction is fetched and executed, the PC points to the first word of the instruction. The processor fetches the first word and
increments the PC by two. The source operand
mode is 27 (autoincrement the PC). Thus, the PC
is used as a pointer to fetch the operand (the second word of the instruction) before being in·
cremented by two to point to the next instruction.

Operation:

BEfOA~

ADDRESS SPACE
1020

062700

1022

000010

1024

AFTER
ADDRESS SPACE

000020

>Oro~
1022

1024

3-14

000010

PC
....-----

000030

3.5.2 Absolute Addressing

QPR @#A
This mode is the equivalent of immediate deferred or autoincrement deferred using the PC. The contents of the location following the instruction are taken as the
address of the operand. Immediate data is interpreted as an absolute address
(i.e., an address that remains constant no matter where in memory the as-sembled instruction is executed).

Absolute Mode Examples

Symbolic

Octal Code

Instruction Name

CLR@#llOO

005037
001100

Clear

Clear the contents of location 1100.

Operation:

AFTER

BEFORE
ADDRESS SPACE
20

005037

001100

ADORES$ SPACE

005037

001100

/PC

1100
1102

177777

1100
1102

000000

ADD@#2000,R3 063703
002000

Operation:

Add contents of location 2000 to R3.

BEFORE
ADORES$ SPACE

AFTER
ADDRESS SPACE

000500

063703

002000
/PC

000300

2000

3-15

000300

001000

3.5.3 ·Relative Addressing
QPR A
or
OPR X (PC)
, where X is the location of A relative to the instruction.
This mode is assembled as index mode using R7. The base of the address calculation, which is stored in the second or third word of the instruction, is not the address of the operand, but the number which, when added to the (PC), becomes
the address of the operand. This mode is useful for writing position independent
code (see Chapter 5) since the location referenced is always fixed relative to the
PC. When instructions are to be relocated, the operand is moved by the same
amount.

Relative Addressing Example
Symbolic
Octal Code
INC A

005267

Instruction Name
Increment

000054
To increment location A, contents of memory location immediately following instruction word are added to (PC) to produce address A. Contents of A .
are increased by one.

Operation:

AFTER
ADDRESS SPACE

BEFORE
ADDRESS SPACE

1020 1---oo_s2_61_ _~,

1020

0005267

1022

000054

1024

-Pc

1026

1026
t024

,,~,.,~

1100

000001

3.5.4 Relative Deferred Addressing
OPR@A or
OPR@X(PC), where x is'l!ocation containing address of A, relative to the instruction.
This mode is similar to the relative mode, except that the second word of the instruction, when added to the PC, contains the address of the address of the operand, rather than the address of the operand.
Relative Deferred Mode Example
Symbolic
Octal Code
CLR@A

005077

Instruction Name
Clear

000020
·Operation:

Add second word of instruction to updated
PC to produce address of address of operand.
Clear operand.

3-16

BEFORE

AFTER

ADDRESS SPACE

(PC•102011020

005077

1020

005077

1022

000020

1022

000020

IO~IO~ri
~

10100

"-Pc

1024

(PC•I02211024

100001

10441

010100

, 10100I

000000

1044

3.6 USE OF STACK POINTER AS GENERAL REGISTER
The processor stack pointer (SP, Register 6) is in most cases the general
register used for the stack operations related to program nesting. Auto·
decrement with Register 6 "pushes" data on to the stack and autoincre·
ment with Register 6 "pops" data off the stack. Index mode with SP
permits random access of items on the stack. Since the SP is used by
the processor for interrupt handling, it has a special attribute: autoin·
crements and autodecrements are always done in steps of two. Byte
operations using the SP in this way leave odd addresses unmodified.

3.7 SUMMARY OF ADDRESSING MODES
3.7.1 General Register Addressing
Risa general register, 0 to 7
(R) is the contents of that register

ModeO

R
OPERAND

INSTRUCTION ~

Mode 1

INSTRUCTION

OPR R

ADDRESS

R contains operand

OPR (R)

OPERAND

3·17

R contains address

Mode 2

Auto-increment

OPR (RH

R contains address, then increment (R)
INSTRUCTION

ADDRESS

OPERAND
~-----•2 FOR
+ 1 FOR

Mode 3 Auto-increment OPR @(R)+
deferred

INSTRUCTION

ADDRESS

WORD,
BYTE

R contains address of address,
then increment (R) by 2

ADDRESS

OPERAND

Mode4

Auto-decrement

OPR -(R)

Decrement (R), then R contains address

INSTRUCTION

Mode 5

ADDRESS

Auto-decrement
deferred

-2 FOR WORD,
-1 FOR BYTE

ADDRESS

-2

Mode6

Index

OPR X(R)

INSTRUCTION

Decrement (R) by 2,
then R contains
address of address

OPR @-(R)

INSTRUCTION

OPERAND

ADDRESS

OPERAND

(R)

+ Xis address

ADDRESS
OPERAND

PC+2

3-18

Mode 7 Index deferred
PC I INSTRUCTION ~---

----l

OPR @X(R)

(R) + X is address of address

ADDRESS

OPERAND

c=CJ1--------~

PC+2

3.7.2 Program Counter Addressing
Register= 7

Mode 2

Immediate

INSTRUCTION

QPR #n

Operand n follows instruction

OPR @#A

Address A follows instruction

---~

PC+2I.....

Mode 3

PC+2

Absolute

INSTRUCTION

~-1

Mode 6

OPERAND

Relative

OPR A

PC+ 4 +Xis address
'-v-"

updated PC
PC

I INSTRUCTION I

PC+2~
PC+4

NEXT INSTR

~---

Mode 7 Relative deferred

OPR @A
PC+ 4 +Xis address of address
'-v-"

updated PC
PC I INSTRUCTION

PC+2

~··f=<Y1'

PCi4 I NEXT INSTR!

,---A-DD-R-ES-s--,H

~--____.

3-19

OPERAND

----

3-20

CHAPTER 4

INSTRUCTION SET

4.1 INTRODUCTION
The specification for each instruction includes the mnemonic, octal code, binary code, a diagram showing the format of the instruction, a symbolic
notation describing its execution and the effect on the condition codes,
a description, special comments, and examples.
MNEMONIC: This is indicated at the top corner of each page. When the
word instruction has a byte equivalent, the byte mnemonic is also shown.
INSTRUCTION FORMAT: A diagram accompanying each instruction
shows the octal op code, the binary op code, and bit assignments. (Note
that in byte instructions. the most significant bit (bit 15) is always a 1.)
SYMBOLS:
( ) = contents of
SS or src =source address
DD or dst =destination address
loc = location
+-=becomes

t = "is popped from stack"
.i = "is pushed onto stack"
I\

=boolean AND

v = boolean OR
JiJ-= exclusive OR

=boolean not

Reg or R = register
B =Byte

• = {O for word
1 for byte
, = concatenated

4-1

4.2 INSTRUCTION FORMATS
The following formats include all instructions used in the LSl-ll. Refer
to individual instructions for more detailed information.
1. Single Operand Group (CLR, CLRB, COM, COMB, INC, INCB, DEC,
DECB, NEG, NEGB, ADC, ADCB, SBC, SBCB,
TST, TSTB, ROR, RORB, ROL, ROLB, ASR,
ASRB, ASL, ASLB, JMP, SWAB, MFPS, MTPS,
SXT, XOR)
15

:
2. Double Operand Group (BIT, BITB, BIC, BICB, BIS, BISB, ADD, SUB,
MOV, MOVB, CMP, CMPB)
15

: OP

C~DE :

3. Program Control Group
a. Branch (all branch instructions)
15

OP
1

~ODE :

OFFSET

b. Jump To Subroutine (JSR)
15

:a:

c. Subroutine Return (RTS)
0

d. Traps (break point, IOT, EMT, TRAP, BPT)
15

OP CODE

e. Mark (MARK)

f. Subtract I and branch (if = O)(SOB)
15

4-2

4. Operate Group (HALT, WAIT, RTI, RESET, RTT, NOP)
0

5. Condition Code Operators (all condition code instructions)
15

6. Fixed and Floating Point Arithmetic (optional EIS/FIS) (FADD, FSUB,
FMUL, FDIV,
ASHC)

MUL,

DIV, ASH,
0

Byte Instructions
The LSl-11 includes a full complement of instructions that manipulate
byte operands. Since all LSl-11 addressing is byte-oriented, byte manipulation addressing is straightforward. Byte instructions with autoincrement or autodecrement direct addressing cause the specified register to
be modified by one to point to the next byte of data. Byte operations in
register mode access the low-order byte of the specified register. These
provisions enable the LSl-11 to perform as either a word or byte processor. The numbering scheme for word and byte addresses in memory is:

VtORO OR BYTE

HIGH BYTE

ADDRESS

ADDRESS
002001

BYTE 1

BYTE 0

002000

002003

BYTE 3

BYTE 2

002002

The most significant bit (Bit 15) of the instruction word is set to indicate
a byte instruction;
Example:
Symbolic

Octal,

CLR
CLRB

005000
105000
4-3

Clear Word
Clear Byte

4.3 LIST OF INSTRUCTIONS
The LSl-11 instruction set is shown in the following sequence.

SINGLE OPERAND
Instruction

Mnemonic

Op Code

Page

General
CLR(B)
COM(B)
INC(B)
DEC(B)
NEG(B)
TST(B)

clear dst ............................................. .
complement dst ................................. .
increment dst ..................................... .
decrement dst ................................... .
negate dst ......................................... .
test dst ............................................... .

•05000
•051DO
•052DD
•053DD
•054DO
•05700

4-6
4-7
4-8
4-9
4-10
4-11

Shift & Rotate
ASR(B)
ASL(B)
ROR(B)
ROL(B)
SWAB

arithmetic shift right ........................... .
arithmetic shift left ............................. .
rotate right ......................................... .
rotate left ................................. : ......... .
swap bytes ......................................... .

•0620D
•063DO
•0600D
•06100
000300

4-13
4-14
4-15
4-16
4-17

Multiple Precision
ADC(B)
add carry ........................................... .
SBC(B)
subtract carry ..................................... .
SXT
sign extend ......................................... .

•055DO
•056DO
006700

4-19
4-20
4-21

106700
1064SS

4-22
4-23

move source to destination ............... .
compare src to dst ............................ .
add src to dst ..................................... .
subtract src from dst ......................... .

•lSSDD
•2SSDD
06SSDD
16SSOD

4-25
4-26
4-27
4-28

bit test ............................................... .
bit clear ............................................. .
bit set ................................................. .
exclusive or ....................................... .

•3SSDO
•4SSDD
•5SSDD
072RDO

4-30
4-31
4-32
4-33

PS WORD OPERATORS
MFPS
MTPS

move byte from PS ............................. .
move byte to PS ................................. .

DOUBLE OPERAND
General
MOV(B)
CMP(B)
ADD
SUB
Logical
BIT(B)

BIC(B)
BIS(B)
XOR

4-4

PROGRAM CONTROL
Op Code

Instruction

Mnemonic

or
Base Code Page
Branch
BR
BNE
BEQ
BPL
BMI

branch (unconditional) ....................... .
branch if not equal (to zero) ............. .
branch if equal (to zero) ................... .
branch if plus ..................................... .
br~nch if minus ................................. .
branch if overflow is clear ................. .
branch if overflow is set ..................... .
branch if carry is clear ....................... .
branch if carry is set ......................... .

000400
001000
001400
100000
100400
102000
102400
103000
103400

4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43

Signed Conditional Branch
BGE
branch is greater than or equal
(to zero} ............. ·............................ .
BLT
branch if less than (zero} ................... .
BGT
branch if greater than (zero} ............. .
BLE
branch if less than or equal (to zero} ..

002000
002400
003000
003400

4-45
4-46
4-47
4-48

Unsigned Conditional Branch
BH I
branch if higher ................................. .
BLOS
branch if lower or same ..................... .
BHIS
branch if higher or same ................... .
BLO
branch if lower ................................... .

101000
101400
103000
103400

4-50
4-51
4-52
4-53

Jump & Subroutine
· JMP
jump .................................................. .
JSR
jump to subroutine ............................ .
RTS
return from subroutine
MARK
mark .
SOB
· subtract one and branch (if ~ 0) ....... .

000100
004RDD
00020R
006400
077ROO

4-54
4-56
4-58
4-59
4-61

emulator trap ..... ................ 104000-104377
trap ....................... :.............. 104400-104777
breakpoint trap .................
000003
input/ output trap . . .. . . ... . .. . . . . . .. .. . .. ..
000004
return from interrupt
000002
return from interrupt . ........................
000006

4-63
4-64
4-65
4-66
4-67
4-68

BVC
BVS

BCC
BCS

Trap & Interrupt
EMT
TRAP
BPT
IOT
RTI
RTI

MISCELLANEOUS
HALT
halt
WAIT
wait for interrupt .
RESET
reset external bus .

000000
000001
000005

4-71
4-72
4-73

00021R
00022N

4-74
4-75

RESERVED INSTRUCTIONS

4-5

CONDITION CODE OPERATORS
CLC
clear C
...................... .
CLV
clear V ............................................... .
CLZ
clear Z ............................................... .
CLN
clear N ............................................... .
CCC
clear all CC bits ................................. .
SEC
set C ................................................... .
SEV
set V ............................................ .
SEZ
set Z ................................................. .
SEN
set N ................................................... .
sec
set all cc bits .................................... .
NOP
no operation ....................................... .

4-76
4-76
4-76
4-76
4-76
4-76
4-76
4-76
4-76
4-76
4-76

000241
000242
000244
000250
000257
000261
000262
000264
000270
000277
000240

4.4 SINGLE OPERAND INSTRUCTIONS

CLR
CLRB
•05000

clear destination
0

o
6

Operation:
Condition Codes:

(dst).0
N: cleared

Z: set
V: cleared
C: cleared
Description:

Word: Contents of specified destination are replaced with zeroes.
Byte: Same

CLR Rl

Example:

Before

After

(Rl) =-= 000000

(Rl) = 177777

NZVC

1.1 1 1

0100

4-6

COM
COMB
•05100

complement dst

1011, 0

Operation:

(dst).-(dst)

Condition Codes:

N: set if most significant bit of result is set; cleared otherwise
Z: set if result is 0; cleared otherwise
V: cleared
C: set

Description:

Replaces the contents of the destination address by their logical complement (each bit equal to 0 is set and each bit equal
to 1 is cleared)
Byte: Same

Before
(RO)= 013333.

After
(RO) = 164444

NZVC
0 1 10

NZVC
1001

4.7

INC
INCB
increment dst
0

•05200

Operation:

(dst).(dst) + 1

Condition Codes:

N: set if result is <0; cleared otherwise
Z: set if result is O; cleared otherwise
V: set if (dst) held 077777; cleared otherwise

C: not affected
Description:

Word: Add one to contents of destination
Byte: Same

Example:

INC R2
Before
(R2) = 000333

After
(R2) = 000334

NZVC
0000

4-8

DEC
DECB
•05300

decrement dst
0

Operation:

(dst}.( dst)-1

Condition Codes:

N: set if result is <0; cleared otherwise
Z: set if result is 0; cleared otherwise
V: set if (dst) was 100000; cleared otherwise
C: not affected

Description:

Word: Subtract 1 from the contents of the destination
Byte: Same

Example:

DEC R5
Before
(R5) ==000001

After
(R5) == 000000

NZVC

1000

0100

4-9

NEG
,NEGB
negate dst

jo11 Io

•05400
0

Operation:

(dst). -(dst)

Condition Codes:

N: set if the result is < 0; cleared otherwise
Z: set if result is O: cleared otherwise
V: set if the result is 100000; cleared otherwise

C: cleared if the result is O; set otherwise
Description:

Word: Replaces the contents of the destination address by its
two's complement. Note that 100000 is replaced by itself -(in
two's complement notation the most negative number has
no positive counterpart).
Byte: Same

Example:

NEG RO
Before
(RO) - 000010

After
(RO) - 177770

- N ZVC
0000

NZVC

4-10

1001

TST
TSTB
test dst

1011 I o

•057DD
0

Operation:
Condition Codes:

1 : 1

(dst)..,.(dst)
N: set if the result is < 0; cleared otherwise
Z: set if result is 0; cleared otherwise

V: cleared

C: cleared
"9scription:

Example:

Word: Sets the condition codes N and Z according to
the contents of the destination address, contents of
dst remains unmodified
Byte: Same
TST R1
Before

(Rl) -012340

After

(Rl) -012340

NZVC

0011

0000

4-11

Shifts
Scaling data by factors of two is accomplished by the shift instructions:
ASR - Arithmetic shift right
ASL - Arithmetic shift left
The sign bit (bit 15) of the operand is reproduced in shifts to the right.
The low order bit is filled with 0 in shifts to the left. Bits shifted out of
the C bit, as shown in the following examples, are lost.
Rotates
The rotate instructions operate on the destination word and the C bit as
though they formed a 17-bit "circular buffer." These instructions facilitate sequential bit testing and detailed bit manipulation.

4-12

ASR
ASRB
•06200

arithmetic shift right
1011, 0

Operation:

(dst)~dst)

Condition Codes:

N: set if the high-order bit of the result is set (result < 0);
cleared otherwise
Z: set if the result - O; cleared otherwise
V: loaded from the Exclusive OR of the N-bit and C-.bit (as set
by the completion of the shift operation)
C: loaded from low-order bit of the destination

Description:

Word: Shifts all bits of the destination right one place.
Bit 15 is reproduced. The C-bit is loaded from bit 0 of
the destination. ASR performs signed division of the
destination by two.
Word:

shifted one place to the right

Byte:

4-13

ASL
ASLB
•06300

arithmetic shift left

1011, 0 0

Operation:

(dst)~dst)

shifted one place to the left

Condition Codes:

N: set if high-order bit of the result is set (result < 0); cleared
otherwise
Z: set if the result = O; cleared otherwise
V: loaded with the exclusive OR of the N-bit and C-bit (as set
by the completion of the shift operation)
C: loaded with the high-order bit of the destination

Description:

Word: Shifts all bits of the destination left one place. Bit 0 is
loaded with an 0. The C-bit of the status word is loaded from
the most significant bit of the destination. ASL performs a
signed multiplication of the destination by 2 with overflow in·
dication.
Word:

Byte:

~-L..,-1~~~·~'~·.......L....__.___,J.-o[~ -....,I::--'---!'~'~·---1...'........L..__.__....Jl15

000 ADDRESS

EVEN ADDRESS

4-14

ROR
RORB
• rotate right

I I
0/1

•06000
0

I 1 I 1 I 0 I 0 : 0 I 0

Operation:

(dst) ~ (dst)
rotate right one place

Condition Codes:

N: set if the high-order bit of the result is set (result < 0);
cleared otherwise
Z: set if all bits of result - 0; cleared otherwise
V: loaded with the Exclusive OR of the N-bit and C-bi.t (as set
by the completion of the rotate operation)
C: loaded with the low-order bit of the destination ·

Description:

Rotates all bits of the destination right one place. Bit 0 is
loaded into the C-bit and the previous contents of the C-bit
are loaded into bit 15 of the destination.
Byte: Same

Example:
Word:

Ep-1,5

Byte:

ODD

EVEN

[]

4-15

[]

ROL
ROLB
•06100

rotate left
1011 I o

O
I

0 I 0

Operation:

(dst) +-- (dst)
rotate left one place

Condition Codes:

N: set if the high-order bit of the result word is set
(result < 0): cleared otherwise
Z: set if all bits of the result word = O; cleared otherwise
V: loaded with the Exclusive OR of the N-bit and C-bit (as set
by the completion of the rotate operation)
C: loaded with the high-order bit of the destination

Description:

Word: Rotate all bits of the destination left one place. Bit 15
is loaded into the C-bit of the status word and the previous
contents of the C-bit are loaded into Bit 0 of the destination.
Byte: Same

Example:

Word:
dst

~-~I~_,____._~~~:..L--J.--L-J---L-l---l-.JI
'--~~1s~~~~~~~~~~~~~~~~~~_Jo

Bytes:

I ~l_.__.__._E~~-N_,___,__.__,I

-·~-r

......._1

4·16

1...__-{~-r

SWAB
swap bytes

000300
d

I d

Operation:

Byte 1 /Byte 0 •Byte O/Byte-1

Condition Codes:

N: set if high-order bit of low-order byte (bit 7) of result is set;
cleared otherwise
Z: set if low-order byte of result = O; cleared otherwise
V: cleared
C: cleared

Description:

Exchanges high-order byte and low-order byte of the destination word (destination must be a word address).

Example:

SWAB R 1
Before

(R 1) == 077777

After

(Rl) == 177577

NZVC
11 11

4-17

NZVC
0000

Multiple Precision
It is sometimes necessary to do arithmetic on operands considered as
multiple words or bytes. The LSl·ll makes special provision for such
operations with the instructions ADC (Add Carry) and SBC (Subtract
Carry) and their byte equivalents.
For example two 16-bit words may be combined into a 32-bit double
precision word and added or subtracted as_ shown below:

32 BIT WORD
OPERAND

31
OPERAND

Afl

RESULT

Example:

The addition of -1 and -1 could be performed as follows:
-1 - 37777777777
(Rl) - 177777
ADD
AOC
ADD

(R2) -= 177777

(R3) = 177777

Rl,R2
R3
R4,R3

1. After (Rl) and (R2) are added, 1 is loaded into the C bit
2. AOC instruction adds C bit to (R3); (R3) = 0
3. (R3) and (R4) are added
4. Result is 37777777776 or -2

4·18

(R4) = 177777

ADC
ADCB
add carry

I 1o
011

•05500
0

0
6

+ (C bit)

Operation:

(dst) ~ (dst)

Condition Codes:

-N: set if result <0; cleared otherwise
Z: set. if result = O; cleared otherwise
V: set if (dst) was 077777 and (C) was l; cleared otherwise
C: set if (dst) was 177777 and (C) was l; cleared ~therwise

Description:

Adds the contents of the C-bit into the destination. This permits the carry from the addition of the low-order words to be
carried into the high-order result.
Byte: Same

Example:

Double precision addition may be done with the following in-.
struction sequence:
ADD AO.BO
add low-order parts
ADC Bl
add carry into high-order
ADD Al.Bl
add high order parts

4-19

SBC
SBCB
subtract carry

1011 I o

•05600

I
6

Opsation:

(dst).(dst)-(C)

Condition Codes:

N: set if result <O; cleared otherwise
Z: set if result O; cleared otherwise
V: set if (dst) was 100000; cleared otherwise
C: set if (dst) was 0 and C was 1; cleared otherwise

Description:

Word: Subtracts the contents of the C-bit from the destination. This permits the carry from the subtraction of two loworder words to be subtracted from the high order part of the
result.
Byte: Same

Example:

Double precision subtraction is done by:
SUB
SBC
SUB

AO.BO
Bl
Al.Bl

4-20

SXT
006700

sign extend

0 I 0

0 .. 1

·,

d
.

Operation:

(dst) _. 0 if N bit is clear
(dst) •-1 N bit is set

Condition Codes:

N: unaffected
Z: set if N bit clear
V: cleared
C: unaffected

Description:

If the condition code bit N is set then a -1 is placed in the
destination operand: if N bit is clear, then a 0 is placed in the
destination operand. This instruction is particularly useful in
multiple precision arithmetic because it permits the sign to
be extended through multiple words.

SXT A

Example:
Before
( A)-012345

After
(A )-177777

NZVC

1000

4-21

MFPS
Move byte From Processor Status word

106700

(dst) ~ PSW
dst lower 8 bits

Operation:

Condition Code
Bits:

N =set if PSW bit 7 = 1; cleared otherwise
Z = set if PS <0:7>
O; cleared otherwise·
V =cleared
C = not affected

Description:

The 8 bit contents of the PS are moved to the effective destination. If destination is mode 0, PS bit 7 is
sign extended through upper byte of the register. The
destination operand address is treated as a byte address.

Example:

M FPS RO
after

before

RO (000014]
PS [000000]

RO [O]
PS (000014]

4-22

MTPS
1064SS

Move byte Jo Processor Status word

Operation:

PSW ~ (SRC)

Condition Codes: Set accoring to effective SRC operand bits 0-3
Description:

The 8 bits of the effective operand replaces the current contents of the PSW. The source operand address
is treated as a byte address.
Note that the T bit (PSW bit 4) cannot be set with this
instruction. The SRC operand remains unchanged.
This instruction can be used to change the priority bit
(PSW bit 7) in the PSW

4-23

4.5 DOUBLE OPERAND INSTRUCTIONS
Double operand instructions provide an instruction (and time) saving facility
since they eliminate the need for "load"and "save" sequences such as those
used in accumulator-oriented machines.

4-24

MOV
MOVB
•lSSDD

move source to destination
1011 I 0

1
12

I
6

Operation:

(dst).(src)

Condition Codes:

N: set if (src) <0: cleared otherwise
Z: set if (src) =0: cleared otherwise
V: cleared
C: not affected

Description:

Word: Moves the source operand to the destination location.
The previous contents of the destination are lost. The contents of the source address are not affected.
Byte: Same as MOV. The MOVB to a register (unique among
byte instructions) extends the most significant bit of the low
order byte (sign extension). Otherwise MOVB operates on
bytes exactly as MOV operates on words.

ExamPle:

MOV XXX,Rl
: loads Register 1 wi.th the contents of memory location: XXX represents a programmer-defined mnemonic used to represent a memory location
MOV
# 20,RO
: loads the number 20 into
Register 0; "#"indicates that the value 20 is the operand
MOV @ # 20,-(R6)
; pushes the operand contained in location 20 onto the stack
MOV (R6) + ,@ # 177566 : pops the operand off a stack
'and moves it into memory location 177566 (terminal print
~
buffer)
MOV Rl,R3
register transfer

; performs an inter

MOVB @ # 177562, @ # 177566
; moves a character from terminal keyboard buffer to terminal printer
buffer.

4-25

CMP
CMPB
compare src to dst

10/11 0

•2SSDD
d

s
6

Operation:

(src)-(dst)

Condition Codes:

N: set if result <0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow; that is. operands were
of opposite signs and the sign of the destination was the
same as the sign of the result: cleared otherwise
C: cleared if there was a carry from the most significant bit of
the result; set otherwise

Description:

Compares the source and destination operands and sets the
condition codes, which may then be used for arithmetic and
logical conditional branches. Both operands are unaffected.
The only action is to set the condition codes. The compare is
customarily followed by a conditional branch instruction.
Note that unlike the subtract instruction the order of oper·
ation is (src)-(dst), not (dst)-(src).

4·26

ADD
add src to dst

06SSDD
d

Operation:

. d

I
12

(dst) ~ (src)

+ (dst)

Condition Codes: N: set if result <0; cleared otherwise
Z: set if result
O; cleared otherwise
V: set if there was arithmetic overflow as a result of
the operation; that is both operands were of the same
sign and the result was of the opposite sign; cleared
otherwise
C: set if there was a carry from the most significant bit
of the result; cleared otherwise

Description:

Examples:

Adds the source operand to the destinatign operand
and stores the result at the destination address. The
original contents of the destination are lost. The con·
tents of the source are not affected. Two's comple·
ment addition is performed.
Note: There is no equivalent byte Mode.
Add to register:

ADD

# 20,RO

Add to memory:

ADD

Rl,XXX

Add register to register:

ADD

Rl,R2

Add memory to memory:

ADD@ # 17750,XXX

XXX is a programmer-defined mnemonic for a memory
location.

4-27

SUB
subtract src from dst

16SSDD
d

Operation:

Condition Codes:

(dst) ~ (dst) -

(src)

N: set if result <0; cleared otherwise
Z: set if result = 0; cleared otherwise

V: set if there was arithmetic overflow as a result of the oper·
ation. that is if operands were of opposite signs and the sign
of the source was the same as the sign of the result; cleared
otherwise
C: cleared if there was a carry from the most significant bit of
the result: set otherwise
Description:

Subtracts the source operand from the destination operand
and leaves the result at the destination address. The orignial
contents of the destination are lost. The contents of the
source are not affected. In double-precision arithmetic the Cbit. when set. indicates a "borrow".

Example:

SUB R 1, R2
Before

After

(Rl) = 011111

(R2) = 012345

(R2) =001234

NZVC

1111

000 0

4-28

Logical
These instructions have the same.format as the double operand arithmetic group.
They permitoperations on data at the bit level.

4-29

BIT
BITB
•3SSDD

bit test

jo11 I O
15

d
12

d
0

Operation:

(src) /1. {dst)

Condition Codes:

N: set if high-order bit of result set: cleared otherwise
Z: set if result = O: cleared otherwise
V: cleared
C: not a·ffected

Description:

Performs logical "and"comparison of the source and destination operands and modifies condition codes accordingly.
Neither the source nor destination operands are affected.
The BIT instruction may be used to test whether any of the
corresponding bits that are set in the destination are also set
in the source or whether all corresponding bits set in the destination are clear in the source.

Example:

BIT

#30.R3

test bits 3 and 4 of R3 to see
if' both are off

R3=0 000 000 000 011 000
Before

After

NZVC

1111

0001

4-30

BIC
BICB
•4SSDD

bit clear

[ott I 1

Operation:

Condition Codes:

(dst).-(src)l\(dst)
N: set if high order bit of result set; cleared otherwise

Z: set if result = O; cleared otherwise
V: cleared
C: not affected

Description:

Clears each bit in the destination that corresponds to a set
bit in the source. The original contents of the destination are
lost. The contents of the source are .unaffected.

Example:

BIC R3,R4
Before
(R3) ==001234

After
(R3) =001234

(R4) = 001111

(R4) = 000101

NZVC

1111

0001

Before:

{R3)=0 000 001 010 011 100
(R4)=0 000 001 001 001 001

After:

(R4)=0 000 000 001 000 001

4-31

BIS
BISB
bit set

•SSSDD
s

I
15

Operation:

(dst)4(src) v (dst)

Condition Codes:

N: set if high-order bit of result set. cleared otherwise
Z: set if result = O: cleared otherwise
V: cleared
C: not affected

Description:

Performs "Inclusive OR"operation between the source and
destination operands and leaves the result at the destination
address: that is. corresponding bits set in the source are set
in the destination. The contents of the destination are lost.

Example:

BIS RO,Rl
After

Before
(RO) =001234
(Rl) = 001111

(RO)= 001234
(Rl) = 001335

NZVC
0000

NZVC
0000
Before:

(R0)=0 000 001 010 011 100
(Rl)=O 000 001 001 001 001

After:

(Rl)=O 000 001 011 011 101

4-32

XOR
074RDD

exclusive OR
I •I I

Operation:

Condition Codes:

I d

(dst).RY(dst)
N: set if the result <0: cleared otherwise

Z: set if result = O: cleared otherwise
V: cleared
C: unaffected
Description:

The exclusive OR of the register and destination operand is
stored in the destination address. Contents of register are
unaffected. Assembler format is: XOR R.D

Example:

XOR RO,R2
After

Before

(RO)= 001234
(R2) = 000325

(RO) =001234
(R2) = 001111

NZVC

1111

0001

Before:

(RO)=O 000 001 010 011 100
(R2)=0 000 001 001 001 001

After:

(R2)=0 000 000 011 010 101

4-33

4.6 PROGRAM CONTROL INSTRUCTIONS
Branches
These instructions cause a branch to a location defined by the sum of
the offset (multiplied by 2) and the current contents of the Program
Counter if:

a) the branch instruction is unconditional
b) it is conditional and the conditions are met after testing the con·
dition codes (NZVC)
The offset is the number of words from the current contents of the PC
forward or backward. Note that the current contents of the PC point to
the word following the branch instruction.
Although the offset expresses a byte address the PC is expressed in
words. The offset is automatically multiplied by two and sign extended to
express words before it is added to the PC. Bit 7 is the sign of the offset.
If it is set, the offset is negative and the branch is done in the backward
direction. Similarly if it is not set, the offset is positive and the branch is
done in the forward direction.
The 8-bit offset allows branching in the backward direction by 200, words
(400 bytes) from the current PC, and in the forward direction by 177.-,
words (376 bytes) from the current PC.
The PDP·ll assembler handles address arithmetic for the user and com·
putes and assembles the proper offset field for branch instructions in the
form:
Bxx

loc

Where "Bxx" is the branch instruction and "loc" is the address to which
the branch is to be made. The assembler gives an error indication in the
instruction if the permissable branch range is exceeded. Branch instruc·
tions have no effect on condition codes. Conditional branch instructions
. where the branch condition is not met, are treated as NO OP's.

4.34

BR
branch (unconditional)
loo

000400 Plus off set

1J
8

1!S

PC ~ PC

Operation:

OFFSET

+ (2 x offset)

Condition Codes: Unaffected
Description:

Provides a way of transferring program control within
a range of -12810to +127i 0 words with a one word in·
st ruction.

New PC address
Updated PC

= updated PC + (2 X offset)

= address of branch instruction + 2

Example: With the Branch instruction at location 500, the following offsets apply.
New PC Address
474

476
500
502
504

506

Offset Code

Offset (decimal)

375
376

-3
-2

377

-1
0

000
001
002

4.35

+1
+2

BNE
001000 Plus offset

branch if not equal (to zero)

fo 1 o

0
8

OFFSET
I

+ (2 x offset) if Z = 0

Operation:

PC • PC

Condition Codes:

Unaffected

Description:

Tests the state of the Z-bit and causes a branch if the Z-bit is
clear. BNE is the complementary operation to BEQ. It is used
to test inequality following a CMP. to test that some bits set
in the destination were also in the source. following a BIT.
and generally, to test that the result of the previous operation was not zero.

Example:

CMP
BNE

A,B
C

: compare A and B
: branch if they are not equal

will branch to C if A f=- B
and the sequence
ADD A,B
BNE C
will branch to C if A + B

4·36

: add A to B
: Branch if the result is not
equal to 0

f 0

BEQ
001400 Plus offset

branch if equal (to zero)
0

OFFSET

I
8

+ (2 x offset) if

Operation:

PC .- PC

Condition Codes:

Unaffected

Description:

Tests the state of the Z·bit and causes a branch if Z is set. As
an example. it is used to test equality following a CMP oper·
ation, to test that no bits set in the destination were also set
in the source following a BIT operation, and generally, to test
that the result of the previous operation was zero.

Example:

CMP

A.B

SEQ

; compare A and B
: branch if they are equal

will branch to C if A = 8
and the sequence

ADD
BEQ

A.B
C

(A - B = 0)
; add A to B
: branch if the result= 0

will branch to C if A + B = 0.

4-37

BPL
100000 Plus offset

branch if plus

11 I O

Operation:

PC ~ PC

OFFSET

o I o
7

+ (2 x offset) if N = 0

Condition Codes: Unaffected
Description:

Tests the state of the N-bit and causes a branch if N
is clear, (positive result). BPL is the complementary
operation of BMI.

4-38

BMI
100400 Plus offset

branch if minus

I 0

OFFSET

+ (2 x offset) if N = 1

Operation:

PC • PC

Condition Codes:

Unaffected

Description:

Tests the state of the N-bit and causes a branch if N
is set. It is used to test the sign (most significant bit)
of the result of the previous operation), branching if
negative. BMI is the Complementary Function of BPL-

4-39

BVC
branch if overflow is clear
0

oI o

I 0

Operation:

102000 Plus offset

PC ~ PC

OFFSET

+ (2 x offset) if V = 0

Condition Codes: Unaffected
Description:

Tests the state of the V bit and causes a branch if the
V bit is clear. BVC is complementary operation to BVS.

4-40

BVS
102400 Plus offset

branch if overflow is set

J1 Io o

OFFSET

0 I 1

Operation:

PC ~ PC + (2 x offset) if V = 1

Condition Codes: Unaffected
Description:

Tests the state of V bit (overflow) and causes a branch
if the V bit is set. BVS is used to detect arithmetic
overflow in the previous operation.

4·41

BCC
branch if carry is clear

Operation:

103000 Plus offset

PC +- PC

OFFSET
I

+ (2 x offset) if C = 0

Condition Codes: Unaffected
Description:

Tests the state of the C-bit and causes a branch if C
is clear. BCC is the complementary operation to BCS.

4-42

BCS

branch if carry is set

11 I O

103400 Plus offset
OFFSET

Operation:

PC ~PC

+ (2 x offset) if C = 1

Condition Codes: Unaffected
Description:

Tests the state .of the C-bit and causes a branch if C
is set. It is used to test for a carry in the result of a
previous operation.

4•43

Signed Condlional Branches
Particular combinations of the condition code bits are tested with the signed conditional branches. These instructions are used to test the results of instructions in
which the operands were considered as signed (two's complement) values.
Note that the sense of signed comparisons differs from that of unsigned comparisons in that in signed 16-bit, two's complement arithmetic the sequence of
values is as follows:
largest

077777
077776

positive

000001
000000

177777
177776
negative
100001
smallest

100000

whereas in unsigned 16-bit arithmetic the sequence is considered to be
highest

177777

000002
000001
lowest

()()()()()()

4.44

BGE
branch if greater than or equal
(to zero)

002000 Plus offset
OFFSET

Operation:

PC-. PC + (2 x offset) if Ny. V • 0

Condition Codes:

Unaffected

Description:

Causes a branch if N and V are either both clear or both set.
BGE is the complementary operation to BLT. Thus BGE will
always cause a branch when it follows an operation that
caused addition of two positive numbers. BGE will also cause
a branch on a zero result.

4-45

BLT
branch if less than (zero)

oI o

OFFSET
I

Operation:

002400 Plus off set

PC • PC

+ (2 x offset) if N y. V = 1

Condition Codes: Unaffected
Description:

Causes a branch if the "Exclusive Or"of the N and V bits are
1. Thus BLT will always branch following an operation that
added two negative numbers, even if overflow occurred.
In particular. BLT will always cause a branch if it follows a
CMP instruction operating on a negative source and a posi·
tive destination (even if overflow occurred). Further. BLT will
never cause a branch when it follows a CMP instruction operating on a positive source and negative destination. BLT will
not cause a branch if the result of the previous operation was
zero (without overflow).

4-46

BGT
003000 Plus offset

branch if greater than (zero)

OFFSET

Operation:

PC • PC + (2 x offset) if Z v(N "' V) == 0

Condition Codes: Unaffected
Description:

Operation of BGT is similar to BGE, except BGT will not cause
a branch on a zero result.

4-47

BLE
branch if less than or equal (to zero)

I I
0

Operation:

OFFSET

0 I 0
8

PC • PC

003400 Plus offset

+ (2 x offset) if Z v(N y. V) = 1

Condition Codes: Unaffected
Description:

Operation is similar to BLT but in addition will cause a
branch if the result of the previous operation was zero.

4-48

Unsigned Conditional Branches
The Unsigned Conditional Branches provide a means for testing the result of
comparison operations in which the operands are considered as unsigned values.

4-49

BHI
101000 Plus offset

branch if higher
11

Operation:

OFFSET
8

PC -. PC

+ (2 x offset) if C - 0 and Z - 0

Condition Codes: Unaffected

Description:

Causes a branch if the previous operation caused neither a
carry nor a zero result. This will happen in comparison (CMP)
operations as long as the source has a higher unsigned value
than the destination.

4-50

BLOS
101400 Plus offset

branch if lower or same

I, 1

o o o o
8

_ Operation:

OFFSET

PC • PC

+ (2 x offset) if C v Z

Condition Codes: Unaffected

Description:

Causes a branch if the previous operation caused either a
carry or a zero result. BLOS is the complementary operation
to BHI. The branch will occur in comparison operations as
long as the source is equal to, or has a lower unsigned value
than the destination.

4-51

BHIS
103000 Plus off set

branch if higher or same

I, o o o o
Operation:

OFFSET
8

PC • PC

+ (2 x offset) if C

Condition Codes: Unaffected

Description:

BHIS is the same instruction as BCC. This mnemonic is in·
cluded only for convenience.

4·52

BLO
103400 Plus offset

branch if lower
0

OFFSET
8

Operation:
1

PC • PC

+ (2 x offset) if C - 1

Condition Codes: Unaffected

Description:

BLO is same instruction as BCS. This mnemonic is included
only for convenience.

4-53

JMP
jump

I 0

000100
0

o Io

o Io : o

Operation:

I d

PC ~ (dst)

Condition Codes: unaffected
Description:

JMP provides more flexible program branching than
provided with the branch instructions. Control may be
transferred to any location in memory (no range limita·
tion) and can be accomplished with the full flexibility
of the addressing modes, witti the exception of register mode 0. Execution of a jump with mode 0 will
cause an "illegal instruction" condition, and will cause
the CPU to trap to vector address 4. (Program control cannot be transferred to a register.) Register deferred mode is legal and will cause program control to
be transferred to the address held in the specified
register. Note that instructions are word data and must
therefore be fetched from an even-numbered address.
Deferred index mode JMP instructions permit transfer
of control to the address contained in a selectable
element of a table of dispatch vectors.

Example:
JMP

FIRST

; Transfers to First

JMP

@LIST

; Transfers to location pointed to at
LIST

First:

List:

; pointer to FIRST

FIRST
JMP

@(SP)+

4-54

; Transfer to location pointed to by
the top of the stack, and remove
the pointer from the stack

Subroutine Instructions
The subroutine call in the PDP-11 provides far automatic nesting of subroutines, reentrancy, and multiple entry points. Subroutines may call
other subroutines (or indeed themselves) to any level of nesting without
making special provision for storage of return addresses at each level of
subroutine call. The subroutine calling mechanism does not modify any
fixed location in memory, thus providing for reentrancy. This allows one
copy of a subroutine to be shared among several interrupting processes.

4-55

JSR
jump to subroutine

004RDD

Id
15

Operation:

Description:

d d

(push reg contents onto processor stack)
reg.PC

(PC holds location following JSR; this address
now put in reg)

PC.(dst)

(PC now points to subroutine destination)

In execution of the JSR. the old contents of the specified register (the "LINKAGE POINTER") are automatically pushed
onto the processor stack and new linkage information placed
in the register. Thus subroutines nested within subroutines
to any depth may all be called with the same linkage register.
There is no need either to plan the maximum depth at which
any particular subroutine will be called or to include instructions in each routine to save and restore the linkage pointer.
Further, since all linkages are saved in a reentrant manner
on the processor stack execution of a subroutine may be in- ·
terrupted, the same subroutine reentered and executed by an
interrupt service routine. Execution of the initial "subroutine
can then be resumed when other requests are satisfied. This
process (called nesting) can proceed to any level.
A subroutine called with a JSR reg,dst instruction can access
the arguments following the call with either autoincrement
addressing, (reg)+, (if arguments are accessed sequentially)
or by indexed addressing, X(reg), (if accessed in random order). These addressing modes may also be deferred,
@(reg) + and @X(reg) if the parameters are operand addresses rather than the operands themselves.

4-56

JSR PC. dst is a special case of the PDP-11 subroutine call
suitable for subroutine calls that transmit parameters
through the general registers. The SP and the PC are the only
registers that may be modified by this call.
Another special case of the JSR instruction is JSR PC,
@(SP)+ which exchanges the top element of the processor
stack and the contents of the program counter. Use of this
instruction allows two routines to swap program control and
resume operation when recalled where they left off. Such rou·
tines are called "co-routines."
Return from a subroutine is done by the RTS instruction. RTS
reg loads the contents of reg into the PC and pops the top
element of the processor stack into the specified register.

Example:
Before:

JSR R5, SBR

(PC)

(SP)

SBR

n-2

After:

PC+2

Stack

~.
'~

DATA 0

JSR PC, SBR
Stack
Before:

After:

(PC)

(SP)

SBR

n-2

Ej
~
2

4-57

RTS
return from subroutine

I 0

o Io

00020R

o Io

Operation:

PC ~(reg)
(reg) ~(SP) t

Description:

Loads contents of reg into PC and pops the top element of
the processor stack into the specified register.
Return from a non-reentrant subroutine is typically made
through the same register that was used in its call. Thus, a
subroutine called with a JSR PC, dst exits with a RTS PC and
a subroutine called with a JSR R5, dst. may pick up para·
meters with addressing modes (R5) +, X(R5), or @X(R5)
and finally exits, with an RTS R5

Example:
Before:

RTS R5
(PC)

(SP)

SBR

Stack

PATA 0

After:

n+2

4-58

DATA 0

MARK
mark

0
15

0064NN
0

o I '

+ 2 + 2n n = number of parameters

Operation:

SP• updated PC
PC•R5
RS.(SP) _.

Condition Codes:

unaffected

Description:

Used as part of the standard PDP-11 subroutine return convention. MARK facilitates the stack clean up procedures involved in subroutine exit. Assembler format is: MARK N

Exa"1ple:

MOV
MOV
MOV

RS,-(SP)

MOV
MOV

PN,-(SP)

MOV

SP ,RS

JSR

PC.SUB

;place old RS on stack
;place N parameters
;on the stack to be
;used there by the
:subroutine

Pl,-(SP)
P2,-(SP)

# MARKN,-(SP) •

;places the instruction
- ;MARK N on the stack
;set up address at Mark N instruction
;jump to subroutine

At this point the stack is as follows:

OLD R5
P1
PN

MARK N
OLD PC

4.59

And the program is at the address SUB which is the
beginning of the subroutine.
SUB:
;execution of the subroutine
itself
RTS R5

;the

return

begins:

this

causes the contents of R5 to be placed in the PC which
then results in the execution of the instruction MARK
N. The contents of old PC are placed in R5
MARK N causes: (1) the stack pointer to be adjusted
to point to the old R5 value; (2) the value now in R5
(the old PC) to be placed in the PC; and (3) contents
of the old R5 to be popped into R5 thus completing
the return from subroutine.

4-60

SOB
077ROO

subtract one and branch (if '=!; 0)

OFFSET

0 I 1

I
9

Op•ation:

(R) +- (R) - 1; if this result =fa 0 then PC +-PC -(2 x
offset) if (R) = O; PC +- PC
'

Condition Codes~

unaffected

Description:

The register is decremented. If it is not equal to 0, twice the
offset is subtracted from the PC (now pointing to the follow·
ing word). The offset is interpreted as a sixbit positive number. This instruction provides a fast, .efficient method of loop
control. Assembler syntax is:
SOB

R,A

Where A is the address to which transfer is to be made if the
decremented R is not equal to 0. Note that the SOB instruction can not be used to transfer control in the forward direction.

4-61

Traps
Trap instructions provide for calls to emulators, I/ 0 monitors, debugging
packages, and user-defined interpreters. A trap is effectively an interrupt
generated by software. When a trap occurs the contents of the current
Program Counter (PC) and processor Status Word (PS) are pushed onto
the processor stack and replaced by the contents of a two-word trap vector containing a new PC and new PS. The return sequence from a trap
involves executing an RTI or RTT instruction which restores the old PC
and old PS by popping them from the stack. Trap instruction vectors are
located ,at permanently assigned fixed addresses.

4-62

EMT
104000-104377

emulator trap

Operation:

O I Or
8

f(SP).PS
f(SP).PC
PC.(30)

PS.(32)

Condition Codes:

N: loaded from trap vector

Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

All operation codes from 104000 to 104377 are EMT
·instructions and may be used to transmit information
to the emulating routine (e.g., function to be performed). The trap vector for EMT is at address 30. The
new PC is taken from the word at address 30; the new
processor status (PS) is taken from the word at address 32.
Caution: EMT is used frequently by DEC system software and is therefore not recommended for general

use.
Before:

PS 1

Stack
I

After:

(32)

(30)

DATA 1

DATA 1
PS 1

n-4.

4-63

PC 1

TRAP
104400-104777

trap

I o

oI 1

Operation:

I 1

f {SP)4PS

t {SP)4PC
PC.(34)
PS4(36)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Operation codes from 104400 to 104777 are TRAP instructions. TRAPs and EMTs are identical in operation, except
that the trap vector for TRAP is at address 34.

Note: Since DEC software makes frequent use of EMT, the
TRAP instruction is recommended for general use.

4-64

BPT
breakpoint trap

000003

o 1 o:o

o o

, I
0

Opemion:

f (SP).PS
f(SP).PC
PC• (14)
PS •(16)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Performs a trap sequence with a trap-vector address of 14.
Used to call debugging aids. The user is cautioned against
employing code 000003 in programs run under these debugging aids.
'(no information is transmitted in the low byte.)

4-65

IOT
input/ output trap

000004
o

o'.o

Operation:

t (SP).PS
t(SP).PC
PC.(20)
PS.(22)

Condition Codes:

N:loaded from trap vector
Z:loaded from trap vector
V:loaded from trap vector
C:loaded from trap vector

Description:

Performs a trap sequence with a trap vector address of 20.
(no information is transmitted in the low byte)

4-66

RTI
000002

return from interrupt

Operation:

0
0

P<ACSP"

PS•(SP)•
Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Used to exit from an interrupt or TRAP service routine.
The PC and PS are restored (popped) from-the processor stack. If a trace trap is pending, the first instruction after RTI will not be executed prior to the
next T traps.

4-67

RTT
return from interrupt

000006
0

Operation:

0
~(SP) .+.

PS•(SP) .+.
Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Operation is the same as RTI except that it inhibits a
trace trap while RTI permits trace trap. If new PS has
T bit set, trap will occur after execution of first in·
struction after RTT.

4-68

Reserved Instruction Traps-These are caused by attempts to execute
instruction codes reserved for future processor expansion (reserved instructions) or instructions with illegal addressing modes (illegal instructions). Order codes not corresponding to any of the instructions described are considered to be reserved instructions. JMP and JSR with
register mode destinations are illegal instructions, and trap to vector
address 4. Reserved instructions trap to vector address 10.
Bus Error Traps-Bus Error Traps are time-out errors; attempts to reference addresses on the bus that have made no response within a certain
length of time. In general, these are caused by attempts to reference
non-existent memory, and attempts to reference non-existent peripheral
devices. Bus error traps cause processor traps through the trap vector
address 4.
Trace Trap-Trace Trap is enabled by bit ~ of the PSW and causes processor traps at the end of instruction execution. The instruction-that is
executed after the instruction that set the T-bit will proceed to completion and then trap through the trap vector at address 14. Note that the
trace trap is a system debugging aid and is transparent to the general
programmer.
The following are special cases of the T-bit and are detailed in subsequent paragraphs.

1. The traced instruction cleared the T-bit.

2. The traced instruction set the T-bit.
3. The traced instruction caused an instruction trap.
4. The traced instruction caused a bus error trap.
5. The processor was interrupted between the time the T-bit was set and
the fetching of the instruction that was to be traced.
6. The traced instruction was a WAIT.
7. The traced instruction was a HALT.
8. The traced instruction was a Return from Interrupt.

NOTE
The traced instruction is the instruction after the
one that set the T-bit.

An instruction that cleared the T bit-Upon fetching the traced Instruction, an internal flag, the trace flag, was set. The trap will still occur at
the end of execution of this instruction. The status word on the stack,
however, will have a clear T-bit.
An instruction that set the T-bit-Since the T·bit was already set, setting
it again has no effect. The trap will occur.

4-69

•

An instruction that caused an Instruction Tra~The instruction trap is
performed and the entire routine for the service trap is executed. If the
service routine exists with an RTI or in any other way restores the
stacked status word, the T-bit is set again, the instruction following the
traced instruction is executed and, unless it is one of the special cases
noted previously, a trace trap occurs.
An instruction that caused a Bus Error Tra~This is treated as an In·
struction Trap. The only difference is that the error service is not as
likely to exit with an RTI, so that the trace trap may not occur.
Note that interrupts may be acknowledged immediately after the loading
of the new PC and PS at the trap vector location. To lock out all interrupts, the PSW at the trap vector should set Bit 7.
A WAIT-T bit trap is not honored during a wait.
A HALT-The processor halts. The PC points to the next instruction to
be executed. The trap will occur immediately following execution resump·
ti on.
A Return from Interrupt-The return from interrupt instruction either
clears or sets the T-bit. If the T-bit was set and RTT is the traced instruction, the trap is delayed until completion of the next instruction.
Power Failure Tra~Occurs when AC power fail signal is received while
processor is in run mode. Trap vector for power failure is location 24
and 26. Trap will occur if an RTI instruction is executed in power fail
service routine.
Trap Priorities-In case of internal and external multiple processor trap
conditions, occurring simultaneously, the following order of priorities is
observed (from high to low):
Bus Error Trap
Memory Refresh
Instruction Traps
Trace Trap
Halt Line
Power Fail Trap
Event Line Interrupt
Device (Bus) Interrupt Request
If a bus error is caused by the trap process handling instruction traps,
trace traps, or a previous bus error, the processor is halted. This is called
a double bus error.

4-70

4. 7 MISCELLANEOUS

HALT
000000.

halt

!0 1 0 0 0 o o o o:o o o o o o 0 0)
1

Condition Codes:

not affected

Description:

Causes the processor to leave RUN mode. The PC
points to the next instruction to be executed. The
processor goes into the HALT mode. The console mode
of operation is enabled.

4-71

WAIT
000001

wait for interrupt
0

o I o

0
0

Condition Codes: not affected
Description:

Provides a way for the processor to relinquish use of
the bus while it waits for an external interrupt request.
Having been given a WAIT command, the processor
will not compete for bus use by fetching instructions
or operands from memory. This permits higher transfer rates between a device and memory, since no processor-induced latencies will be encountered by interrupt requests from devices. In WAIT, as in all instructions, the PC points to the next instruction following
the WAIT instruction. Thus when an interrupt causes
the PC and PS to be pushed onto the processor stack,
the address of the next instruction following the WAIT
is saved. The exit from the interrupt routine (i.e. execution of an RTI instruction) will cause resumption of
the interrupted process at the instruction following the
WAIT.

4-72

RESET
000005

reset external bus

jo 1 o

o'.o

Condition Codes: not affected
Description:

Sends INIT on the BUS for 10 µsec. All devices on the
BUS are reset to their state at power-up. The processor remains in an idle state for 90 µsec following issuance of INIT.

4-73

(NO ASSIGNED MNEMONIC)
15

00021R
0

(R) ~gets contents of 5 internal 16 bit registers R ~
R
12 at end of inst.

Operation:

Condition Codes: Unaffected
Description:

Contents of register R (low order 3 bits of inst.) is
used as a pointer. The contents of the internal hidden
temporary registers are consecutively written into
memory and the contents or R are incremented by 2
until the five 16 bit registers have been written.
{R) ~
(R)
12". Primarily used as a maintenance aid in diagnostic routines. The interpretation
of the five words in memory is as follows:

Memory
Location

Microlevel
Register
Symbol

(R)

RBA

Bus address Register. It contains the last
non-instruction fetch bus address for destination modes, 3, 5, 6 and 7.

(R)+2

RSRC

Source Operand Register. It contains the last
source operand of a double operand instruction. The high byte may not be correct if it
was source mode 0.

(R)+4

ROST

Destination operand register. It contains the
last destination operand fetched by the processor.

(R)+6

RPSW

PSW and Scratch Register. The top 4 bits
are PSW bits 4 thru 7. The remaining bit interpretation is a function of the last instruction and may not be that useful for all cases.

(R)+lO

RIR

Instruction Register. It contains the present,
not past, instruction being executed, and will
always be 36R where R is the register in the
format. The 360 is a result of firmware instruction decoding and is caused by 150
being added to the opcode (21R+150=36R).

Function

4-74

00022N

(NO ASSIGNED MNEMONIC)
15

o : o : o: o Io : o : o : o :

Operation:

Causes Micro Instruction Control Transfer to Microlocation 3000

Condition Codes: Unaffected
Description:

This instruction can be used to transfer Microcontrol
to Microcode address 3000 in the Microprocessor. If
Microaddress 3000 does not exist this opcode will
cause a reserved instruction trap through memory location 10.
This is a reserved DEC instruction.

4-75

Condition Code Operators

CLN

SEN
SEZ
SEV
SEC

CLZ
CLV
CLC
CCC
condition code operators

0 I 0

0002XX

oI ,

0 I 0

Description:

Set and clear condition code bits. Selectable combinatiohs of
these bits may be cleared or set together. Condition code bits
corresponding to bits in the condition code operator (Bits O·
3) are modified according to the sense of bit 4, the set/clear
bit of the operator. i.e. set the bit specified by bit 0, 1, 2 or 3,
if bit 4 is a 1. Clear corresponding bits if bit 4 - 0.

Mnemonic
Operation

OP Code

CLC

Cleare

000241

CLV

ClearV

000242

CLZ

Clear Z

000244

CLN

Clear N

000250

SEC

SetC

000261

SEV

SetV

000262

SEZ

SetZ

000264

SEN

Set N

000270

sec

Set all CC's

000277

CCC

Clear all CC's

000257

ClearVand C

000243
000240

NOP

sec

No Operation

Combinations of the above set or clear operations may be ORed together to form
combined instructions.

4-76

CHAPTER 5

PROGRAMMING TECHNIQUES

In order to produce programs which fully utilize the power and flexibility
of the LSl-11, the reader should become familiar with the various programming techniques which are part of the basic design philosophy of
the LSl-11. Although it is possible to program the LSl-11 along traditional lines such as "accumulator orientation" this approach does not
fully exploit the architecture and instruction set of the LSl-11.

5.1 THE STACK
A "stack," as used on the LSl-11, is an area of memory set aside by the
programmer for temporary storage or subroutine/interrupt service link·
age. The instructions which facilitate "stack" handling are useful features not normally found in low-cost computers. They allow a program
to dynamically establish, modify, or delete a stack and items on it. The
stack uses the "last-in, first-out" concept, that is, various items may be
added to a stack in sequential order and retrieved or deleted from the
stack in reverse order. On the LSl-11, a stack starts at the highest location reserved for it and expands linearly downward to the lowest address
as items are added to the stack.
LON ADDRESSES

HIGH ADDRESSES

Figure 5-1: Stack Addresses
The programmer does not need to keep track of the actual locations his
data is being stacked into. This is done automatically through a "stack
pointer." To keep track of the last item added to the stack (or "where
we are" in the stack) a General Register always contains the memory
address where the last item is stored in the stack. In the LSl-11 any
register except Register 7 (the Program Counter-PC) may be used as a
"stack pointer" under program control; however, instructions associated
with subroutine linkage and interrupt service automatically use Register
6 (R6) as a hardware "Stack Pointer." For this reason R6 is frequently
referred to as the system "SP."

5-1

Stacks in the LSl-11 may be maintained in either full word or byte units.
This is true for a stack pointed to by any register except R6, which must
be organized in full word units only.

WORD STACK
007100

ITEM #1

0070 76

ITEM #2

007074

ITEM# 3

00 70 72

ITEM#4

-SP

007072

007070
007066
007064

NOTE: BYTES
ARE ARRANGED IN
WORDS AS FOl.LOvVING
BYTE 3
BYTE 2
BYTE 1
BYTE 0

BYTE ST.OCK
007100
007077
007076
007075

ITEM#!
ITEM #2
ITEM#3
ITEM#4

--RO-R5

007075

Figure 5-2: Word and Byte Stacks

Items are added to a stack using the autodecrement addressing mode with the
appropriate pointer register. (See Chapter 3 for description of the autoincre·
ment/decrement modes).
This operation is accomplished as follows;
MOV Source,-(SP)

;MOV Source Word onto the stack
or

MOVB Source,-(R)

;MOVB Source Byte onto a stack

This is called a "push" because data is "pushed onto the stack."

5-2

To remove an item from a stack the autoincrement addressing mode with
the appropriate R is employed. This is accomplished in the following
manner:
MOV (SP), + ,Destination

;MOV Destination Word off the stack
or

MOVB (R) + ,Destination

; MOVB Destination Byte off the stack

Removing an item from a stack is called a "pop" for "popping from the stack."
After an item has been "popped," its stack location is considered free and available for other use. The stack pointer points to the last-used location implying
that the next (lower) location is free. Thus a stack may represent a pool of shareable temporary storage locations.

HIGHMEMORY~.-sp ~
t

-sP

LOW MEMORY I AN EMPTY STACK
AREA

t~SP

STACK

} AREA

2.P\JSHINGA OATUM
ONTO THE STACK

3 PUSHING ANOTHER
DATUM ONTO THE
STACKS

~~p
5. POP

7 POP

Figure 5-3: Illustration of Push and Pop Operations

5-3

As an example of stack usage consider this situation: a subroutine (SUBR) wants
to use registers 1 and 2, but these registers must be returned to the calling pro·
gram with their contents unchanged. The subroutine could be written as follows:
Address

Octal Code

Assembler Syntax

076322
076324
076326
076330

010167
000074
010267
000072

MOV Rl,TEMPl ;save Rl

076410
076412
076414
076416
076420
076422
076424

SUBR:

MOV R2,TEMP2 ;save R2

MOV TEMPl. Rl ;Restore Rl

016701

000006
MOV TEMP2, R2 ;Restore R2

016702
000004
000207

RTSPC
TEMPI: 0
TEMP2: 0

000000
()()()()()()

*Index Constants

Figure 5-4: Register Saving Without the Stack
OR: Using a Stack
Address

Octal Code

010020
010022

010143
010243

010130
010132
010134

012301
012302
000207

Assembler Syntax

SUBR:

MOV Rl, -(R3) ;push Rl
MOV R2, -(R3) ;push R2

MOV (R3) +, R2 ;pop R2
MOV (83) +, Rl ;pop Rl
RTSPC

Note: In this case R3 was used as a Stack Pointer
Figure 5-.5: Register Saving using the Stack
The second-. routine uses four less words of instruction code and two words of
temporary "stack" storage. Another routine could use the same stack space at
some later point. Thus, the ability to share temporary storage in the form of a
stack is a very economical way to save on memory usage.

5.4

As a further example of stack usage, consider the task of managing an
input buffer from a terminal. As characters come in, the terminal user
may wish to delete characters from his line; this is accomplished very
easily by maintaining a byte stack containing the input characters. Whenever a backspace is received a character is "popped" off the stack and
eliminated from consideration. In this example, a programmer has the
choice of "popping" characters to be eliminated by using either the
MOVB, (MOVE BYTE) or INC (INCREMENT) instructions.

001011

001010

001007

c
IJ

INC R3

001006•

001005

001004

001003

001002

001001

001002

001001

Figure 5-6: Byte Stack used as a Character Buffer

NOTE that in this case using the increment instruction (INC) is preferable to MOVB since it would accomplish the task of eliminating the unwanted character from the stack by readjusting the stack pointer without
the need for a destination location. Also, the stack pointer (SP) used in
this example cannot be the system stack pointer (R6) because R6 may
only point to word (even) locations.
5.2 SUBROUTINE LINKAGE
5.2.1 Subroutine Calls
Subroutines provide a facility for maintaining a single copy of a given
routine which can be used in a repetitive manner by other programs
locatep anywhere else in memory. In order to provide this facility, generalized linkage methods must be established for the purpose of control
transfer and information exchange between subroutines and calling programs. The LSl-11 instruction set contains several useful instructions
for this purpose.
LSl-11 subroutines are called by using the JSR instruction which has the
following format.
a general register (R) for linkage----.
JSR R,SUBR
an entry location (SUBR) for the subroutine_J
5-5

When a JSR is executed, the contents of the linkage register are saved
on the system R6 stack as if a MOV reg.-(SP) had been performed.
Then the same register is loaded with the memory address following the
JSR instruction (the contents of the current PC) and a jump is made to
the entry location specified by the DST operand.
Octal Code

Address

Assembler Syntax

OOICXXl
001002

JSRR5 SUBR
004567
index constant fur SUBR 000060

001064

SUBR

Olnnmm

MOVA.8

Figure 5-7: JSR using R5
BEFORE

AFTER

(R5l• 000132
(R6)• 001776
(PC)<(R7)•001000

(R5l-001004
(R6)•001774
(PC)•(R7)•001064

002000
001776
001774

-----

002000
--OO_t_77_6_ _1001776 - - - - 001774

001772

00t772

----000132

-SP

001774

· Figure 5-8: JSR
Note that the instruction JSR RG,SUBR is not normally considered to be a meaningful combination.
5.2.2 Argument Transmission
The memory location pointed to by the linkage register of the JSR instruction may
contain arguments or addressses of arguments. These arguments may be accessed from the subroutine in several ways. Using Register 5 as the linkage regis·
ter, the first argument could be obtained by using the addressing modes indicated by (R5), (R5) + ,X(R5) for actual data, or @(R5) +,etc. for the address of
data. If the autoincrement mode is used, "the linkage register is automatically updated to point to the next argument.
Figures 5-9 and 5·10 illustrate two possible methods of argument transmission.
Address Instructions and Data
010400
010402
010404
010406

020306
020310

JSR R5,SUBR
Index constant for SUBR
arg # 1
arg #2

SUBR:

MOV (R5) + ,Rl
MOV (R5) + ,R2

SUBROUTINE CALL
ARGUMENTS

;get arg # 1
;get arg # 2 Retrieve Arguments
from SUB

Figure 5-9; Argument Transmission -Register Autoincrement Mode
. 5-6

Address

Instructions and Data

010400
010402
010404
010406
910410

JSR R5,SUBR
index constant for SUBR
077722
017724
077726

077722
077724
077726

Arg #l
arg #2
arg #3

020306
020301

SUBR:

SUBROUTINE CALL
Address of Arg # 1
Address of Arg. # 2
Address of Arg. # 3

arguments

MOV @(R5) + ,Rl ;get arg # 1
MOV @(R5) + ,R2 ;get arg #2

Figure 5-10: Argument Transmission-Register Autoincrement Deferred Mode
Another method of transmitting arguments is to transmit only the address of the first item by placing this address in a general purpose
register. It is not necessary to have the actual argument list in the same
general area as the subroutine call. Thus a subroutine can be called to
wo.rk on data located anywhere in memory. In fact, in many cases, the
operations performed by the subroutine can be applied directly to the
data located on or pointed to by a pointer without the need to ever
actually move this data into the subroutine area.
Calling Program: MOV
JSR

POINTER, Rl
PC,SUBR

SUBROUTINE

(Rl) + .(Rl)

ADD

;Add item # 1 to item # 2. place
result in item # 2, Rl points
to item # 2 now

etc.
or
ADD

(Rl).2(Rl)

;Same effect as above except that
Rl still points to item # 1
etc.

ITEM

# 1

ITE.M

I _____,

_ R , ....

Figure 5-11: Transmitting Stacks as Arguments

5-7

Because the LSl·ll hardware already uses general purpose register R6
to point to a stack for saving and restoring PC and PS (processor status
word) information, it is quite convenient to use this same stack to save
and restore intermediate results and to transmit arguments to and from
subroutines. Using R6 in this manner permits extreme flexibility in nest·
ing subroutines and interrupt service routines.
Since arguments may be obtained from the stack by using some form of
register indexed addressing, it is sometimes useful to save a temporary
copy of R6 in some other register which has already been saved at the
beginning of a subroutine. In the previous example RS may be~used to
index the arguments while R6 is free to be incremented and decremented
in the course of being used as a stack pointer. If R6 had been used
directly as the base for indexing and not "copied," it might be difficult
to keep track of the position in the argument list since the base of the
stack would change with every autoincrement/decrement which occurs.

or; #1

or;

ar9 #2

or; • 2
or; # 3
but when another item
TO is puShed

SP_.

or9#2 Is at source

or;# 2 Is at source

-4(SPl

-2 (SP)

Figure 5·12: Shifting Indexed Base

However, if the contents of R6 (SP) are saved in RS before any arguments are
pushed onto the stack, the position relative to RS would remain constant.

org # 1
SP___.

or; #1

-RS

or; • 2

or; # 2

org#2 1s at 2 (R5l

or9 • 2 is still at 2 IR5l

Figure 5·13: Constant Index Base Using "R6 Copy"

5-8

5.2.3 Subroutine Return
In order to provide for a return from a subroutine to the calling program
an RTS instruction is executed by the subroutine. This instruction should
specify the same register as the JSR used in the subroutine call. When
executed, it causes the register, specified, to be moved to the PC and
the top of the stack to be then placed in the register spe~ified. Note that
if an RTS PC is executed, it has the effect of returning to the address
specified by the contents ofthe top of the stack.
Note that the JSR and the JMP instructions differ in that a linkage register is always used with a JSR; there is no linkage register with a JMP
and no way to return to the calling program.
When a subroutine finishes, it is· necessary to "clean-up" the stack by
eliminating or skipping over the subroutine arguments. One way this can
be done is by making the subroutine keep the number of arguments as
its first stack item. Returns from subroutines would then involve calculating the amount by which to reset the stack pointer. Resetting the
stack pointer then restores the original contents of the register which
was used as the copy of the stack pointer. The LSl-11 however, has a
specific instruction (MARK instruction) used to perform the clean-up
task. The MARK instruction which is stored on a stack in place of "number of argument" information may be used to automatically perform
these "clean-up" chores.
5.2.4 LSl-11 Set Subroutine Advantages
There are several advantages to the LSl-11 Set subroutine calling procedure.
a. arguments can be quickly passed between the calling program and
the subroutine.
b. ~f the user has no arguments or the arguments are in a general 1 register or on the stack, the JSR PC, DST mode can be used so that
none of the general purpose registers are taken up for linkage.
c. many JSRs can be executed without the need to provide any saving
procedure for the linkage information since all linkage information is
automatically pushed onto the stack in sequential order. Returns can
simply be made by automatically popping this information from the
stack in the opposite order of the JSRs.
Such linkage address bookkeeping is called automatic "nesting" of subroutine calls. This feature enables the programmer to construct fast,
efficient linkages in a simple, flexible manner. It even permits a routine
to call itself in those cases where this is meaningful. It also allows subroutines to be interrupted by external devices without losing the proper
return linkage registers.
5.2.5 Trap Subroutine Calls
The TRAP instruction may be used to call subroutines. The TRAP instruction is typically used with a package of many different subroutines such
as the software floating-point math package. The subroutines in the
package are assigned a unique number which is to be included in the
TRAP instruction. When a subroutine is called, a "TRAP n" instruction
is executed, where "n" is the number (o ===: n ~ 255) which designates

5-9

the subroutine to be invoked. Arguments are typically passed on the
stack, in the registers, or they may follow the TRAP instruction. The
advantages of using the TRAP instruction are that a program using a
TRAP subroutine package may be assembled and linked independent of
the TRAP package and the subroutine call only requires one word, as
opposed to two words which are normally required using the JSR instruction. The disadvantage of using the TRAP instruction is the extra
overhead incurred in the software decoding of the TRAP instruction.
MOV ARG, -(SP)

Calling
Program:
- Trap
handler:

TRAPH:

TRAP 3

; Push argument onto the
stack
Invoke subroutine # 3

MOV RO, -(SP)

; Save register

; Copy address of the
TRAP instruction +2
MOVB -2(RO), RO
; Copy subroutine number
in TRAP instruction
BIC #177400, RO
; Clear possible sign
extension bits
ASL RO
; Convert to word offset
JSR PC,@TRPTBL(RO) · ; Call subroutine
; Restore register
MOV (SP)+, RO
; Return to user
RTT
MOV 4(SP), RO

TRPTBL: SUBO

; Table of pointer to

SU Bl
SU82

)

subroutines

SU83

5.3 INTERRUPTS
5.3.1 General Principles
Interrupts are in many respects very similar to subroutine calls. However,
they are forced, rather than controlled, transfers of program execution
occurring because of some external and program-independent event
(such as a stroke on the teleprinter keyboard). Like subroutines, interrupts have linkage information such that a return to -the interrupted
program can be made. More information is actually necessary for an
interrupt than a subroutine because of the random nature of interrupts.
The complete machine state of the program immediately prior to the
occurrence of the interrupt must be preserved in order to return to the
program without any noticeable effects. (i.e. was the previous operation
zero or negative, etc.) This information is stored in the Processor Status
Word (PS). Upon interrupt, the contents of the Program Counter (PC)
(address of next instruction) and the PS are automatically pushed _onto
the R6 system stack. The effect is the same as if:
MFPS, -(SP)
MOV R7,-(SP)

; Push PS
; Push PC

had been executed.
5-10

The new contents of the PC and PS are loaded from two preassigned consecutive memory locations which are called an "interrupt vector." The
actual locations are chosen by the device interface designer and are
locate.d in low memory addresses. The first word contains the interrupt
service routine address (the address of the new program sequence) and
the second word contains the new PS which will determine the machine
status including the operational mode and register set to be used by the
interrupt service routine.
After the interrupt service routine has been completed, an RTI (return
from interrupt) is performed. The two top words of the stack are automatically "popped" and placed in the PC and PS respectively, thus resuming the interrupted program.
5.3.2 Nesting
Interrupts can be nested in much the same manner that subroutines are
nested. In fact, it is possible to nest any arbitrary mixture of subroutines
and interrupts without any confusion. By using the RTI and RTS instructions, respectively, the proper returns are automatic.

Process 0 is running;
SP is pointing to loca·
tion PO.

Interrupt stops process 0
with PC = PCO, and
status= PS 0 ;starts process 1.

3. Process 1 uses stack for
temporary storage (TEO, TEl).

PO~
PSO

SP~

PCO

PO
PSO
PCO
TEO
SP-

TEI

4. Process 1 interrupted with PC == P¢ 1
and status = PS1; process 2 is started

Po
PSO
PC 0
TEO
TE I
PS 1
SP-

5-11

PC 1

Process 2 is running and does a
JSR R7,A to Subroutine A with
PC = PC2.

PO
PSO
PCO
TEO

TE,
PS 1
PC 1
SP-

Subroutine A is running
and uses stack for
temporary storage.

PC2

PO
PSO
PCO
TEO
TE 1
PS 1
PC 1
PC2
TA1
SP-

7. Subroutine A releases the temporary

TA2

storage holding TAI and TA2.

PSO
PCO
TEO
TE 1
PS1
PC1
PC2

8. Subroutine A returns control to process
2 with an RTS R7,PC is reset to PC2.

PSO
PCO
TEO
TE1
PS1
SP-

5-12

PC 1

9. Process 2 completes with an RTI. instruction
(dismisses interrupt) PC is reset
to PC(l) and status is reset to PSl;
process 1 resumes.

PO
PSO
PCO
TEO

SP-

10. Proce~s 1 releases the temporary
storage holding TEO and TEl.

TE1

PO~
PSO

SP~

PCO

11. Process 1 completes its operation
with an RTI PC is restored to PCO
and status is reset to PSO.

Figure 5-14: Nested Interrupt Service Routines and Subroutines
Note that the area of interrupt service programming is intimately involved with
the concept of CPU and device priority levels.

5.4 PROGRAMMING PERIPHERALS
Programming of LSl-11 modules (devices) is simple. A special class of
instructions to deal with input/output operations is unnecessary. The·
bus structure permits a unified addressing structure in which control,
status, and data registers for devices are directly addressed as memory
locations. Therefore, all operations on th.ese registers, such as transferring information into or out of them or manipulating data within them,
are performed by normal memory reference instructions.
The use of all memory reference instructions on device registers greatly
increases the flexibility of input/output programming. For example, information in a device register can be compared directly with a value and a
branch made on the result:
CMP RBUF,
BEQ SERVICE

#101

In this case, the program looks for 101 in the DLVll Receiver Data
Buffer Register (RBUF) and branches if it finds it. There is no need to
transfer the information into an intermediate register for comparison.
When the character is of interest, a memory reference instruction can
transfer the character into a user buffer in memory or to another peripheral device. The instruction:
MOV DRINBUF LOC

5-13

transfers a character from the ORVIi Data Input Buffer (DRINBUF) into a
user-defined location.
All arithmetic operations can be performed on a peripheral device register. For example, the instruction ADD # 10, DROUT BUF will add 10
to the DRVll's Output Buffer.
All read/write device registers can be treated as accumulators. There is
no need to funnel all data transfers, arithmetic operations, and comparisons through a single or small number of accumulator registers.
5.5 DEVICE REGISTERS
All devices are specified by a set of registers which are addressed as
memory and manipulated as flexibly as an accumulator. There are two
types of registers associated with each device: (1) control and status
registers; (2) data registers. The following examples are general, for
specific device register information refer to the applicable manual.
Control and Status Registers-Each device can have one or more control and status registers that contain the information necessary to communicate with that device. The general form, shown below does not
necessarily apply to every device, but is presented as a guide.
15

ERROR _:_________J
DONE OR READY
INTERRUPT ENABLE
ENABLE

BIT

- NAME

DESCRIPTION

Error

Set when an error occurs.

Done or Ready

Set when the device in either ready to
accept new information, or has completed an operation and has data
available.

Interrupt Enable

When set, an interrupt will be requested when a done or error condition occurs.

Enable

Set to allow the peripheral device to
perform a function.

Many devices require less than sixteen status bits. Other devices will
require more than sixteen bits and therefore will require additional status
and control registers.
Data Buffer Registers-Each device has at least one buffer register for
temporarily storing data to be transferred into or out of the processor.
The number and type of data registers is a function of the device. The
DLVl 1 for example uses single 8-bit data buffer registers. The DRVl 1
uses 16-bit data registers and some devices may use more than 1 register for data buffers.
5-14

Interrupt Structure-If the appropriate interrupt enable bit is set, in the
control and status register of a device, transition from 0 to 1 of the
READY or ERROR bit, where applicable, should cause an interrupt request to be issued to the processor. Also if READY or ERROR is a 1
when the interrupt enable is turned on, an interrupt request is made.
If the device makes the request and the processor's priority is zero,
and no higher priority devices are requesting an interrupt,_ the request
is granted, and the interrupt sequence takes place.
a. the current program counter (PC) and processor status (PS) are
pushed onto the processor stack;
b. the new PC and PS are loaded from a pair of locations (the interrupt
vector) in addressed memory, unique to the interrupting device.
Since each device has a unique interrupt vector which dispatches control to the appropriate interrupt handling routine immediately, no device
polling is required. The Return from Interrupt Instruction (RTI) is used
to reverse the action of the interrupt sequence. The top two words on
the stack are popped into the PC and PS, returning control to the interrupted sequence.
Programming Example-A DLVl 1 interrupt routine to service a low-speed
paper tape reader, could appear as follows (assume the DLVl 1 's interrupt vector is 60s and PRSER is the service routine for the device):
First the user must initialize the Stack Pointer (R6) and device
vector locations. Then the user must initialize the service
routine by specifying an address pointer and a word count:
INIT: MOV # BUFADR, RO
MOV # COUNT, COUNTR
MOV # 101, RCSR

; set address pointer into
register
; set counter
; enable DLVl 1
interrupt enable &
reader run enable,
Program continues until
interrupt occurs
When the interrupt occurs and is acknowledged, the processor stores
the current PC and PS on the stack. Next it goes to the interrupt vector
and picks up the new PC and PS location 60, 62. When the program
was loaded, the address of PRSER would be put in location 60 and 200a
in 72 (to set the processor's priority to 4 and inhibit new interrupts).
The next instruction executed is the first instruction of the devica-.service routine at PRSER.
PRSER:

MOVB RBUF, (RO)+

; move character from
DLVl 1 's receiver data
buffer register to buffer and
increment pointer
; decrement character count
; branch when COUNTR equals O
; set reader enable for next
; character input

DEC COUNTR
BEQ DONE
INC RCSR
DONE:

; return to interrupted program

RTI

5-15

5-16

CHAPTER 6

EXTENDED ARITHMETIC OPTION
6.1 GENERAL
This chapter describes the Extended Arithmetic Chip, which is an option
on the KDll·F, KDl 1-J Microcomputer Module. The KEVll option allows
extended manipulation of fixed point numbers (fixed point arithmetic)
and enables direct operations on single precision 32-bit words (floating
point arithmetic).
6.2 FIXED POINT ARITHMETIC (EIS)
The following instructions apply to fixed point numbers:

Mnemonic

Instruction

Op Code

MUL

multiply
divide
shift arithmetically
arithmetic shift combined

070RSS
071RSS
072RSS
073RSS

DIV

ASH
ASCH

Operand formats are:
15

16-bit single word:

Is l
15

0
I

NUMBER
I

Is I

14
I
HlrH NUMBER PA~T

32-bit double _word:
15
I
LOW NUMBER PART

S is the sign bit.

S
S

= 0 for positive quantities
= 1 for negative quantities; number is in 2's
complement notation

6·1

MUL
multiply

oI 1

070RSS

Operation:
Condition Codes:

: r

s
5

I s

s
0

R. Rvl• R x(src)
N: set if product is <0: cleared otherwise

Z: set if product is O: cleared otherwise
V: cleared
C: set if the result is less than-2 15 or greater than or equal to
2 1!i-l:
Description:

Example:

The contents of the destination register and source taken as
two's complement integers are multiplied and stored in the
destination register and the succeeding register (if R is even).
If R is odd only the low order product is stored. Assembler
syntax is : MUL S,R.
(Note that the actual destination is R. Rvl which reduces to
just R when R is odd.)
16-bit product (R is odd)
CLC
MOV #400,Rl
MUL # 10.Rl
BCS ERROR

;Clear carry condition code

;Carry will be set if
;product is less than
; -21s or greater than or equal to 2'
;no significance lost

Before

After
(R 1) = 004000

(R 1) = 000400

Assembler format for all EIS instructions is:
OPR src, R

6-2

DIV
divide

0 I 1

071RSS
1 I 0

s I s
9

Operation:

R. Rvl• R. Rvl /(src)

Condition Codes:

N: set if quotient <0: cleared otherwise
Z: set if quotient = 0: cleared otherwise
V: set if source = 0 or if the absolute value of the register is
larger than the absolute value of the source. (In this case the
instruction is aborted because the quotient would exceed 15
bits.)
C: set if divide 0 attempted; cleared otherwise

Description:

The 32-bit two's complement integer in Rand Rvl is divided
by the source operand. The quotient is left in R: the remainder in Rvl. Division will be performed so that the remainder
is of the same sign as the dividend. R must be even.

Example:

CLR RO
MOV # 20001,Rl
DIV#2,RO

Before
(RO) = 000000
(Rl) = 020001

After
(RO)= 010000

(Rl)=OOOOOl

6-3

Quotient
Remainder

ASH
072RSS

shift arithmetically
0
15

Operation:
Condition Codes:

R• R Shifted arithmetically NN places to right or left
Where NN = low order 6 bits of source
N: set if result <O; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if sign of register changed during shift; cleared otherwise
C: loaded from last bit shifted out of register
The contents of the register are shifted right or left the number of times specified by the shift count. The shift count is
taken as the low order 6 bits of the source operand. This
number ranges from -32 to + 31. Negative is a a right shift

Description:

and positive is a left shift.

[I I
J 15

~-I

1-0
l-0

6 LSB of source
011111
000001
111111
100000

Action in general register
Shift left 31 places
shift left 1 place
shift right 1 place
shift right 32 places

Example:

ASH RO, R3
Before
(RO)= 001234
(R3) = 000003

After
(RO) = 012340 _
(R~) = 000003,.

6-4

ASHC
arithmetic shift combined

073RSS

I 1

Operation:

I
.

R, Rvl•R, Rvl The double word is shifted NN places to the
right or left, where NN =low order six bits of source

Condition Codes:

N: set if result <0; cleared otherwise

Z: set if result = O; cleared otherwise
V: set if sign bit changes during the shift; cleared otherwise

C: loaded with high order bit when left Shift; loaded with low
order bit when right shift (loaded with the last bit shifted out
of the 32-bit operand)

Description:

The contents of the register and the register ORed with one
are treated as one 32 bit word, R + 1 (bits 0-15) and R (bits
16-31) are shifted right or left the number of times specified
by the shift count. The shift count is taken as the low order 6
bits of the source operand. This number ranges from -32 to
+ 31. Negative is a right shift and positive is a ·left shift.
When the register chosen is an odd number the register
and the register OR'ed with one are the same. In this case the
right shift becomes a rotate (for up to· a shift of 16 ). The 16
bit word is rotated right the number of bits specified by the
shift count.

[~f~~~~~~-L--L-~_,J,J
R+tl

F
15

~
OR

6-5

1-0

6.3 FLOATING POINT ARITHMETIC (FIS)
The Floating Point instructions used are unique to the LSl-11 and PDP11/ 35 & 40. However, the OP Codes used do not conflict with any other
instructions.
Mnenomic

Instruction

Op Code

FADD
FSUB
FMUL
FDIV

floating add
floating subtract
floating multiply
floating divide

07500R
07501R
07502R
07503R

The operand format is:
7
EXPOrlENT
I

6
FRACTION (HIGH PART)
I
I

I
HIGH ARGUl\llENT

0
1
FRACTION (LOW PART)

LOW ARGUl\llENT

--s = sign of fraction; 0 for positive, 1 for negative
Exponent= 8 bits for the exponent, in excess (200)a notation
Fraction
23 bits plus 1 hidden bit (all numbers are assumed to be
normalized)

The number format is essentially a sign and magnitude representation.
The format is identical with the 11/45 for single precision numbers.
Fraction
The binary radix point is to the left (in front of bit 6 of the High Argument), so that the value of the fraction is always less than 1 in magnitude. Normalization would always cause the first bit after the radix point
to be a 1, such that the fractional value would be between lh and 1.
Therefore, this bit can be understood and not be represented directly,
to achieve an extra 1 bit of resolution.
The first bit to the right of the radix point (hidden bit) is always a 1. The
next bit for the fraction is taken from bit 6 of the High Argument.
The result of a Floating Point operation is always rounded away from
zero, increasing the absolute value of the number.
Exponent
The 8-bit Exponent field (bits 14 to 7) allow exponent values between
-128 and +127. Since an excess (200)a or (128),o number system is
used, the correspondence between actual values and coded representation is as follows:
Actual Value

Representation

Decimal
+127

Octal
377

Binary
11 111 111

+1
0
·-1

201
200
177

10 000 001
10 000 000
01 111 111

-128

000

00 000 000

6·6

If the actual value of the exponent is equal to -128, meaning a total
value (including the fraction) of less than 2- 128 , the floating point number
will be assumed to be 0, regardless of the sign or fraction bits. The hardware will generate a clean 0 (a 32-bit word of all zeros).

Example of a Number

+(12)10

= +(llOO)z

= +(24)10 x (.11)2

[16 x <1h + %)

Exponent

Fraction

,....----A-----

representation: 0

= 12]

roooooo 0000000000000000

10 000 1001

hidden bit is a 1
radix point is understood
Registers
There are no pre-assigned registers for the Floating Point option. A gen·
eral purpose register is used as a pointer to specify a stack address.
The contents of the register are used to locate the operands and answer
for the Floating Point operations as follows:
(R)

High B argument address
(R)+2
Low B argument address
(R)+4 = High A argument address
(R)+6 = Low A argument address

After the Floating Point operation, the answer is stored on the stack as
follows:

(R)+4 =address for High part of answer
(R)+6
address for Low part of answer

where (R) is the original contents of the general register used.
After execution of the instruction, the general register will point to the
High answer, at (R)+4.
Condition Codes
Condition codes are set or cleared as shown in the Instruction Descrip·
tions, in the next part of this section. If a trap occurs as a function of
a Floating Instruction, the condition codes are re-interpreted as follows:
V = l, if an error occurs
N
l, if underflow or divide-by-zero
C = l, if divide by zero

Z=O
Overflow
Underflow
Divide by O

0
1
1

0
0
1

0
0
0

1
1

6-7

Traps occur through the vector at location 244. A Floating Point instruction will be aborted if an interrupt request is issued before the instruction
is near completion. The Program Counter will point to the aborted Floating instruction so that the Interrupt will look transparent.
Assembler format is: OPR R

INSTRUCTIONS

FADD
07500R

floating add
jo 1 1

1 o

1 1 0'.o

o 1o o

ojr
3

•I
0

Operation:

[(R)+4, (R)+6] ~[(R)+4, (R)+6]+[(R),(R)+2], if
result ~ 2· 128 ; else [(R)+4, (R)+6] ~

Condition Codes:

N; set if result < O; cleared otherwise
Z: set if result
O: cleared otherwise
V: cleared
C: cleared

Adds the A argument to the B argument and stores
the result in the A Argument position on the stack.
General register R is used as the stack pointer for
the operation.

Description:

A~A+B

FSUB
07501R

floating subtract

Operation:

[(R)+4, (R)+6] ~[(R)+4, (R)+6]-[(R), (R)+2], if
result ~ 2· 128 ; else [(R)+4, (R)+6] ~

Condition Codes:

N: set if•result < O; cleared otherwise
Z: set if result = O; cleared otherwise
V: cleared
C: cleared

Description:

Sutracts the 8 Argument from the A Argument and
stores the result in the A Argument position on the
stack.
A~A-8

6-8

FMUL
floating multiply

07502R
1

Operation:

[(R)+4, (R)+6] ~[(R)+4, (R)+6]X [(R), (R)+2] if
result ~ 2- 128 ; else [(R)+4, (R)+6] ~

Condition Codes:

N: set if result < O; cleared otherwise
Z: set if result
O; cleared otherwise

V: cleared
C: cleared

Multiplies the A Argument by the B Argument and
stores the result in the A Argument position on the
stack.

Description:

A~A X B

FDIV
07503R

floating divide

1 I 0

: 0

I 0

~r
3

J
0

Operation:

[(R)+4, (R)+6] ~[(R)+4, (R)+6] I [(R),(R)+2 ] if
result ~ 2-i 28 ; else [(R)+4, (R)+6)] ~o

Condition Codes:

N: set if result
Z: set if result
V: cleared
C: cleared

Description:

Divides the A Argument by the B Argument and
stores the result in the A Argument position on the
stack. If the divisor (B Argument) is equal to zero,
the stack is left untouched.

< O; cleared otherwise

= 0; cleared otherwise

A~A/B

6-9

6-10

,,CHAPTER 7

CONSOLE OPERATION
7.1 GENERAL
The LSl-11 can use a standard ASCII terminal or keyboard printer with a
20 mA current loop and resident microcode for console operation. The
LA36 is ideally suited for this use and will be described in this chapter.

7.2

INTERFACING

Interfacing with the LSl-11 (Figure 7-1) can be accomplished through
the DLVl 1 Serial Line Unit (SLU) and BC08R cable assembly. One end
of this cable connects to a 40 pin connector on the DLVll, the other
end of the cable is terminated with a Mate-N-Lok connector that is pincompatible with the following peripheral options:
LA36 DECwriter
LT33 Teletypewriter
LT35 Teletypewriter
VT058 Alphanumeric Terminal
VT50 DECscope
RT02·B Remote Data Entry Terminal
For a detailed description of the DLVq, refer to the LSl-11 user's
manual.

KD11-F
MICROCOMPUTER MODULE
4KRAM

H9270 BACKPLANE

LSI-11. BUS

DLV11
SERIAL
LINE UNIT

LA36 DECWRITER
20MA

PRINTER
LINE/LOCAL

SELECTION
KEV BOARD

NOTE: DLV11

LOOP RECEIVER
20MA
LOOP DRIVER

BC05M CABLE
ASSEMBLY

177560

Figure 7-1

Console Interfacing with LA36
7-1

7.3

ODT/CONSOLE MICROCODE
The LSl-11 does not have ·an internal or external switch register or control function switch option. In a typical configuration there is no bus
device which responds to address 177570 (the SWR address on PDP-11).
The function of Load Address, Deposit, Examine, Continue, Start/ Halt
are implemented With microcode routines that communicate with an
operator via a serial stream of ASCII characters. For operation, it requires a serial line interface (e.g., DLVl l) at Bus address 177560 and
a device that can interpret and display as· well as send ASCII characters
(e.g., LA36).
The HALT or ODT microcode state of the KDll-F can be entered in five
different ways (others are a· subset of these) from the RUN state:
• Execution of a LSl-11 HALT instruction
• A double Bus Error (Bus Error trap with SP (R6) pointing to nonexistent memory)
• The assertion of a low level on the B HALT line on the Bus
• As a powerup option
• ASCII break with DLVll framing error asserting the B HALT line (enabled by jumper of DLVl 1)

Upon entering the HALT state, the KDl 1-F responds through the console device with an ASCII prompt character sequence. The following
prompt sequence is used:

• CR LF nnnnnn CR LF @ (where nnnnnn is the location of the next
LSl-11 instruction to be executed and @ is ODT prompt character).
The following is a list of the command character set and its utilization.
In each example the operator's entry is not underlined, and the KDll-F
response is. Note that in part the character set is a subset of ODT-11.
The input character set is interpreted by the KDll-F only when it is in
the HALT state.
Note also that all commands and characters are echoed by the KDll-F
and that illegal command characters will be echoed and followed by ?
(ASCII 012) followed by CR (ASCII 015) followed by LF(ASCll 012) followed by @ (ASCII 100). If a valid command character is received when
no location is open (e.g., when having just entered the halt state), the
valid command character will be echoed and followed by a,? CR, LF, @.
Opening non-existent locations will have the same response. The console
always prints six numeric characters; however, the user is not required
to type leading zeros for either address or data.

7-2

"/" slash (ASCII 057)
This command is used to open a memory location, general purpose
register, or the processor status word.
The / command is normally preceded by a location identifier. Before the contents is typed, the console will issue a space (ASCII 40)
character.
example:
@ 001000/ 021525
where:
@ = KDllF prompt character (ASCII 100)
001000 =octal location in address space to be opened
/ =command to open and exhibit contents of location

012525 =contents of octal location 1000

NOTE
If / used Without preceding location identifier,
address of last opened location will be used.
This feature can be used to verify the data just
entered in a location.

"CR" carriage return (ASCII 015)
This command is used to close an open location. If contents of
location are to be changed, CR should be preceded by the new
value. If no change to location is necessary then CR will not alter
contents.
example:

@ 001000/ 012525 CR LF
@ /012525

OR
example:

@ 001000/ 012525

15126421 CR LF

@ /126421
where:
CR= (ASCII 015) used to close location 1000 in both examples.
Note that in second example contents of location 1000 was
changed and that only the last 6 digits entered were actually placed
in location 1000.

7-3

"LF" line feed (ASCII 012)
This command is also used to close an open location or GPR
(general purpose register). If entered after a location has been
opened, it will close the open location or GPR and open location
2 or GPR
l. If the contents of the open location or GPR are
to be modified, the new contents should precede the LF operator.

example:
@ 1000/ 012525 LF CR
001002/ 005252 CR LF

@
where:
LF
(ASCII 012) used to close location 1000 and open location
1002, if used on the PS, the LF will modify the PS if the data has
been typed, and close it; then a CR, LF, @ is issued. If LF is used
to advance beyond R7, the register name that is printed is meaningless but the contents printed is that of RO.

"t" up arrow (ASCII 135)
The "t'' command is also used to close an open location or GPR.
If entered after a location or GPR has been opened, it will close
the open location or GPR and open location -2, or GPR-1. If the
contents of the open location or GPR are to be modified, the new
contents should precede the "t" operator.
example:
@ 1000/ 012525j _£R LF
000776/ 010101 CR LF
@
where:

"t"

= (ASCII 135) used to close location 1000 and open location

776.

(ASCII 135) up arrow:
If used on the PS, the t will modify the PS if the data has been
typed and close it; then CR, LF, @ is issued. If t is used to decrement below RO, the register name that is printed is meaningless
but the contents is that of R7.

7-4

"@"at sign (ASCII 100)
The @ command is used once a location has been opened to
open a location using the contents of the opened location as a
pointer. Also the open location can be optionally modified similar
to other commands and if done, the new contents will be used
as the pointer.
example:
@ 1000/ 000200 @ CR LF

---

000200/ 000137 CR LF

@
where:
@ = (ASCII 100) used to close open location 1000 and open lo·
cation 200.
Note that the @ command may be used with either GPRs or
memory contents.
If used on the PS, the command with modify the PS if data has
been typed and close it; however, the last GPR or memory location
contents will be used as a pointer.

"~" back arrow (ASCII 137)
This command is used once a location has been opened to open
the location that is the address of the contents of the open location plus the address of the open location plus 2. This is useful
for relative instructions where it is desired to determine the effective address.

example:
@ 1000/ 000200 - CR LF
----------

001202/ 002525 CR LF
@

where:
"~" = (ASCII 137) used to close open location 1000 and open
location 1202 (sum of contents of location 1000, 1000 and 2).
Note that this command cannot be used if a GPR or the PS is the
open location and if attempted, the command will modify the GPR
or PS if data has been typed, and close the GPR or PS; then a CR,
LF. @ will be issued.

7-5

$ dollar sign (ASCII 044) or Fi (ASCII 122) internal register
designator:
Either command if followed by a register value 0-7 (ASCII 060067) will allow that specific general purpose register to be opened
'if followed by the I (ASCII 057) command.
example:
@ $ n/ 012345 CR LF
---

where:
$ = register designator. This could also be R.
n =octal register 0-7.
012345 =contents of GPR n.
Note that the GPRs once opened can be closed with either the CR,
LF, "t'', or @ commands. The "<E-" command will also close a
GPR but will not perform the relative mode operation.

"$ s" (ASCII 044; ASCII 123) processor status word
By replacing "n" in the above example with the letter S (ASCII
123) the processor status word will be opened. Again either $ or
R (ASCII 122) is a legal command.
example:
@ $ S/ 000100 CR LF
---·@
where:
$ = GPR or processor status word designator
S = specifies processor status register; differentiates from GPRs.
000200 =eight bit contents of PSW; bit 7 = 1, all other bits= 0.
Note that the contents of the PSW can be changed using the CR
command but bit 4 (the T bit) cannot be set using any of the
commands.

"G" (ASCII 107)
The "G" (GO) command is used to start execution of a program
at the memory location typed immediately before the "G".
example:
@ 100 G or lOO;G
The LSl-11 PC(R7) will be loaded with 100 and execution will begin
·at that location. Before starting execution, a BUS INIT is issued
for 10 µsec followed by 90 µsec of idle time. Note that a semicolon character (ASCII 073) can be used to separate the address
from the G and this is done for PDP-11 ODT compatibility. Since
the console is a character-by-character processor, as soon as the
"G" is typed, the command is processed and a RUBOUT cannot
be issued to cancel the command. If the B HALT L line is asserted,
7-6

execution does not take place and only the BUS INIT sequence is
done. The machine returns to console mode and prints the PC
followed by CR,LF,@.

---

10.

upu (ASCII 120)
The "P" (Proceed) command is used to continue or resume ex·
ecution at the location pointed to by the current contents of the
PC(R7).
example:
@ P or ;P

If the B HALT L line is asserted the INIT line will not be asserted, a
single instruction will be executed, and the machine will return to
console mode. It will print the contents of the PC followed by a
CR,LF,@. In this fashion, it is possible to single instruction step
through a user program.
The semicolon is accepted for PDP-11 ODT compatibility. If the
semicolon character is received during any character sequence,
the console ignores it.
11.

.. M" (ASCII 115)
The "M" (Maintenance) command is used for maintenance purposes and prints the contents of an internal CPU register. This
data reflects how the machine got to the console mode.
example:
@ M 000213 CR LF

------

The console prints six characters and then returns to command
mode by printing CR,LF,@.
The last octal digit is the only number of significance and is encoded as follows. The value specifies how the machine got to the
console mode.
Last Octal Digit Value

Function

Halt instruction or B Halt line

Bus Error occurred while getting device
interrupt vector

Bus Error occurred while doing memory
refresh

Double Bus Error occurred (stack was
non-existent value)

Non-existent Micro-PC address occurred
on internal CPU bus

In the above exa'.llple, the last octal digit is a "3", which indicates
a Double Bus Error occurred.
•
7-7

12. . "RO" RUBOUT (ASCII 177)
While RUBOUT is not truly a command, the console does support
this character. When typing in either address or data, the user can
type RU BOUT to erase the previously typed character and the
console will respond with a ""'-." (Backslash-ASCII 134) for every
typed RUBOUT.
example:
@ 000100/ 077777

123457 (RUBOUT) "'- 6 CR LF

@ 000100/ 123456
In the above example, the user typed a "7'' while entering new
data and then typed RUBOUT. The console responded with a ""'-"
and then the user typed a "6" and CR. Then the user opens the
same location and the new data reflects the RUBOUT. Note that
if RUBOUT is issued repeatedly, only numerical characters are
erased and it is not possible to terminate the present mode the
console is in. If more than six RUBOUTS are consecutively typed,
and then a valid location closing command is typed, the open
location will be modified with all zeroes.
The RUBOUT command cannot be used while entering a register
number. R2 "'- 4 / 012345 will not open register R4; however the
RUBOUT command will cause ODT to revert to memory mode and
open location 4.

13.

"L" (ASCII 114)
The "L" (Boot Loader) command will cause the processor to selfsize memory and then load from the specified device a program
that is in Bootstrap Loader Format (e.g.-Absolute Loader). The
device is specified by typing in the address of the input control
and status register immediately before the "L".
example:
@ 177560L
First memory is sized, starting at 28K and the device address
(177560) is placed in the last location for Absolute Loader compatibility. Then the program will be loaded by setting the "GO"
bit in address 177560 and reading a byte of data from 177562.
The loading begins at the address specified in the Bootstrap loader
format. The loading is terminated when address XXX775 has been
loaded and execution automatically begins at XXX774. It is up to the
program being loaded to halt the processor if that is desired. In~
the case of the Absolute Loader, the processor will halt and the
console will print XXX500 (the current PC) followed by CR,LF,@.
(XXX
017 for 4K memory; XXX = 157 for 28K memory).

When loading a program using the "L" command, the B HALT L
line is ignored. If a timeout error occurs, the console will terminate
the load and print ?,CR,LF,@.
Any device address may be used as long as it is software com7-8

patible with the DLVI 1. If no address is typed, address 0 will
be used.

14.

"CONTROL-SHIFT-$" (ASCII 23)
This command is used for manufacturing test purposes and is not
a normal user command. It is briefly described here so that in case
-a user accidentally types this character, he will understand the
machine response. If this character is typed, ODT expects two more
characters. It uses these two characters as a 16-bit binary address
and starting at that address, dumps five locations in binary format
to the serial line.
It is recommended that if this mode is inadvertently entered, two
characters such as a NULL (0) and @ (ASCII 100) be typed to
specify an address in order to terminate this mode. Once completed, ODT will issue a CR, LF, @.

7-9

7-10

APPENDIX A

MEMORY MAP

RESERVED VECTOR LOCATIONS
000 (RESERVED)
004 TIME OUT & OTHER ERRORS
010 ILLEGAL & RESERVED INSTRUCTION
014 BPT INSTRUCTION AND T BIT
020 IOT INSTRUCTION
024 POWER FAIL
030 EMT INSTRUCTION
034 TRAP INSTRUCTION
060 CONSOLE INPUT DEVICE
064 CONSOLE OUTPUT DEVICE
100 EXTERNAL EVENT LINE INTERRUPT
244 FIS (OPTIONAL)
DEVICE ADDRESSES
.160000 DEVICE ADRESSES
ARE SELECTED BY
JUMPERS LOCATED
ON THEIR LINE UNIT

177776

MODULES.

A-1

A-2

APPENDIX B

INSTRUCTION TIMING

8.1 LSl-11 INSTRUCTION EXECUTION TIME
The execution time for an instruction depends on the instruction itself,
the modes of addressing used, and the type of memory referenced. In
most cases the instruction execution time is the sum of a Basic Time,
a Source Address (SRC) Time, and a Destination Address (DST) Time.
INSTR TIME =

Basic Time + SRC Time+ DST Time

(BASIC Time= Fetch Time+ Decode Time + Execute Time)
Some of the instructions require only some of these times. All timing
information is in microseconds, unless otherwise noted. Times are typical; processor timing can vary ±20%.

SOURCE AND DESTINATION TIME

MODE

SRC TIME
(Word).

SRC TIME
(Byte)

DST TIME
(Word)

DST TIME
(Byte)

0
1
2
3
4
5
6
7

0
1.40 µsec
1.40
3.50
2.10
4.20
4.20
6.30

0
1.05 µsec
1.05
3.15
1.75
3.85
3.85
5.95

0
1.75 µsec
1.75
4.20
2.45
4.90
4.55
7.00

2.10 µsec
2.10
4.20
2.80
4.90
4.90
6.65

NOTE FOR MODE 2 and MODE 4 if R6 or R7 used with Byte operation, add 0.35 ,usec to SRC time and 0.70 µsec to DST time.

INSTRUCTION TIME
OOPS (Double Operand)

DMO

DMl-7

MOV
ADD,XOR,SUB,BIC,BIS
CMP,BIT
MOVB
BICB,BISB
CMPB,BITB

3.50 µsec
3.50
3.50
3.85
3.85
3.15

2.45 µsec
4.20
3.15
3.85
3.85
2.80

8-1

SOPS (Single Operand)

OMO

DMl-7

CLR
INC,ADC,DEC,SBC
COM, NEG
ROL,ASL
TST
ROR
ASR
CLRB,COMB,NEGB
ROLB,ASLB
I NCB, DECB, SBCB,ADCB
TSTB
RORB
ASRB
SWAB
SXT
MFPS (1067DD)
MTPS (1064SS)

3.85 µsec
4.20
4.20
3.85
4.20
5.25
5.60
3.85
3.85
3.85
3.85.
4.20
4.55
4.20
5.95
4.90
7.00

4.20 µsec
4.90
4.55
4.55
3.85
5.95
6.30
4.20
4.20
4.55
3.50
4.90
5.95
3.85
6.65
6.65
1.00·:=

•:=For MTPS use Byte DST time not SRC time.
·~Add 0.35 µSec to instr. time if Bit 7 of effective QPR =1
JMP/JSR MODE

DST TIME

1
2
3
4

0.70 µsec
1.40
2.10
1.40
2.80
2.80
4.90

5
6
7

INSTRUCTION

TIMES

JMP
JSR (PC=LINK)
JSR (PC~LINK)

3.50 µsec
5.25
6.40

ALL BRANCHES
SOB( BRANCH)
SOB(NO BRANCH)

3.50
4.90
4.20

SET CC
CLEAR CC
NOP

3.50
3.50
3.50

RTS
MARK
RTI

5.25
11.55
8.75*
8.75*+

RTT

8-2

(CONDITION MET OR NOT MET)

INSTRUCTION

TIMES

TRAP,EMT
IOT,RPT

18.55*

WAIT
HALT
RESET

6.30
5.60
5.95 +10.0 µsec. for INIT + 90.0 µsec.

MAINT INST. (00021R)
RSRVD INST. (00022N)

20.30
5.95

16.80'"~ µsec

(TO GET TO UADDRESS 3000)

* IF NEW PS HA'S BIT 4 or BIT 7 SET ADD 0.35 µsec FOR EACH
+ IF NEW PS HAS BIT 4 (T BIT) SET ADD 2.10 µsec
EXTENDED ARITHMETIC (KEVll) INSTRUCTION TIMES
EIS Instruction Times
MODE

SRC TIME

0
1
2
3
4
5
6
7

0.35 µsec.
2.10
2.80
3.15
2.80
3.85
3.85
5.60

INSTRUCTION
MUL
DIV
ASH (RIGHT)
ASH (LEFT)
ASHC (RIGHT)
ASHC (LEFT)

BASIC TIME
24.0 to 37.0 µsec.

If both numbers less than
256 in absolute value
64.0 µsec. Worst Case 16 bit multiply
78.0 µsec. Worst Case
1.75 per shift
10.1
10.8
2.45 per shift
10.1 + 2.80 per shift
10.1 + 3.15 per shift

+
+

FIS Instruction Times (µsec)
INST. TIME= BASIC TIME+ SHIFT TIME FOR BINARY POINTS+ SHIFT
TIME FOR NORMALIZATION
INSTRUCTION

BASIC TIME

FADD
FSUB

42.1 µsec
42.4

8-3

EXPONENT DIFFERENCE

ALIGN BINARY POINTS

0- 7
8-15
16-23

2.45 µsec per shift
3.50 + 2.45 per shift over 8
7.00 + 2.45 per shift over 16

EXPONENT DIFFERENCE

NORMALIZATION

0- 7

2.1 µsec per shift
2.1 + 2.1 per shift over 8
4.2 + 2.1 per shift over 16

8-15
16-23

INSTRUCTION

BASIC TIME (µsec)

FMUL

52.2 base time+ 3.85 per "l" bit. If either argument
has 8 bits of precision
93. 7 Worst Case
232 Worst Case
151 Typical

FDIV

B-4-

("")

.:...

CENTRAL PROCESSOR

LSl·ll

11/05

Main Market
Memory
Reg to Reg Transfer
Max Mem Size (words)
Max Address Space
General Purpose Reg
Stack Processing
Micro-programmed
Instructions

OEM

Stack Limit Address

OEM
core, MOS, ROM
3.5 us
32K
32K
8
yes
yes
basic set + XOR,
SOB, MARK, SXT,
RTT, MTPS, MFPS
option (internal)
MUL, DIV,
ASH, ASHC
option, FADD,
FSUB, FMUL, FDIV
none

11/10

11/15

End User
core
3.7 us
28K
32K
8
yes
yes
basic set

OEM

Memory Management

11/20

11/35

11/40

option (external)

optio" (extern a I)

software only

400 (fixed)

not available

Modes
Automatic Priority
Interrupt

1
l·line
multi· level

1
4·1ine
multi-level

l·line
multi·lev

4·1ine
multi·lev

End User
core
0.9 us
124K
128K
8
yes
yes
basic set+
XOR, SOB, MARK,
SXT, RTT
option (internal)
MUL, DIV,
ASH, ASHC
hardware option
32·bit word
400 or
programmable
(option)
option
MFPI, MTPI
1 std, 2 opt
4·1ine
multi·level

Power Fail and
Auto-Restart

standard

option

standard

Extended Arithmetic
(hardware)
Floating Point

End User
core
2.3 us
28K
124K
32K
128K
8
yes
no
basic set

OEM

11/45
OEM & End User
bipolar, MOS, core
0.3
0.45 0.9
124K
128K
16
yes
yes
same as 11/40 +
MUL, DIV, ASH,
ASHC, SPL
standard (int)

hardware option
32 or 64·bit word
programmable

ren

.....
I

.....

...........

-g

c
-g

.....
.....
I

"Tl

-<
0

option MFPI, MFPD
MTPI, MTPD
3
4·1ine
multi· level
+
8 software levels
standard

"Tl

("')

0 >
""O
3: ,.,,
-g ""O
c:: z

,.,, ><c
~

:::0

("')

C-2

APPENDIX D

INSTRUCTION INDEX
4-19
4-27
4-14
6-4
6-5
4-13

4-42
4-43
4-37
4-45
4-47
4-50
4-52
4-31
4-32
4-30
4-46
4-48
4-53
4-51
4-39
4-36
4-38
4-65
4-35
4-40
4-41

BCC
BCS
BEQ
BGE
BGT.
BHI
BHIS
BIC(B)
BIS(B)
BIT(B)
BLT
BLE
BLO
BLOS.
BMI
BNE
BPL
BPT
BR
SVC
BVS

4-8
4-66
4-54
4-56
M

4-59
4-22
4-25
4-23
6-2
N

4-10
4-76

NEG(B)
NOP
R
RESET
ROL(B)
ROR(B)
RTI
RTS
RTT ..

........................

4-73
4-16
4-15
4-67
4-58
4-68

s
4-20
4-61
4-28
4-17
4.-21

SBC(B)
SOB ...
SUB
SWAB
SXT

4-9
6-3

4-64
4-11

TRAP
TST(B)

4-63

4-72

WAIT

F
FADD
FDIV

. INC(B)
IOT

MARK
MFPS
MOV(B)
MTPS
MUL ...

EMT

4-71

4-6
4-26
4-7
4-76

DEC(B)
DIV

HALT .

JMP ...
JSR

c
CLR(B)
CMP(B)
COM(B)
COND. CODES

6-9
6-8

FMUL
FSUB .

A
ADC(B)
ADD
ASL(B)
ASH
ASHC
ASR(B)

6-8
6-9

XOR
D-1

4-33

NUMERICAL OP CODE LIST
OP Code Mnemonic

OP Code Mnemonic OP Code Mnemonic

HALT
WAIT
RTI
BPT
IOT
RESET
RTT

00 60 DD
00 61 DD
00 62 DD
00 63 DD
00 64 NN
00 67 DD

gg ~ ~;} (unused)

00 70 00 }

00 00 00
00 00 01
00 00 02
00 00 03
00 00 04
00 00 05
00 00 06

JMP
RTS

00 01 DD
00 02 OR
00 02 10

}1,ese"'edi

00 02 40

NOP

00 02 27

00 0241 }

-!-

cond
codes

()() 02 77
00 03 DD
00 04
()() 10
00 14
00 20
00 24
00 30
00 34

SWAB

xxx BR
xxx BNE
xxx BEQ
xxx BGE
xxx BLT
xxx BGT
xxx BLE

ROR
ROL
ASR
ASL
MARK
SXT

(unused)

00 77 77
01 SS DD)
02 SS DD
03 SS DD
04 SS DD
05 SS DD
06 SS DD

MOV
CMP
BIT
BIC
BIS
ADD

07 OR SS
07 1R SS
07 2R SS
07 3R SS
07 4R DD

MUL
DIV
ASH
ASHC
XOR

07 50 OR
07 50 1R
07 50 2R
07 50 3R

FADD
FSUB
FMUL
FDIV

07 50 40 }

(unused)

07 67 77

00 4R DD

JSR

07 7R NN

00 50 DD
00 51 DD
00 52 DD
00 53 DD
00 54 DD
00 55 DD
00 56 DD
00 57 DD

CLR
COM
INC
DEC
NEG
ADC
SBC
TST

10 ()()
10 04
10 10
10 14
10 20
10 24
10 30

SOB

xxx BPL
xxx BMI
xxx BHI
xxx BLOS
xxx BVC
xxx BVS
xxx BCC,
BHIS
10 34 xxx BCS,
BLO

D-2

10 40 00 }

EMT

10 43 77

10 44 00 }

TRAP

10 47 77
10 50 DD
10 51 DD
10 52 DD
10 53 DD
10 54 DD
10 55 DD
10 56 DD
10 57 DD

CLRB
COMB
INCB
DECB
NEGB
ADCB
SBCB
TSTB

10 60 DD
10 61 DD
10 62 DD
10 63 DD
10 64 SS
10 67 DD

RORB
ROLB
ASRB
ASLB
MTPS
MFPS

11 SS DD
12 SS DD
13 SS DD
14 SS DD
15 SS DD
16 SS DD

MOVB
CMPB
BITB
BICB
BISS
SUB

APPENDIX E

SUMMARY OF LSl-11 INSTRUCTIONS

MOOE

Name

Mode
0
1
2

3
4

5
6
7

Symbolic

Description

(R) is operand [ex. R2=%2)
(R) is address
(R) is adrs; (R) +(1 or 2)
(R) is adrs of adrs; (R) + 2
(R) - (1 or 2); is ad rs
(R) - 2; (R) is adrs of adrs
(R)
X is adrs
(R)
X is adrs of adrs

(R)
(R)+
<a(R)+
-(R)
!ii-(R)

+
+

X(R)
@X(R)

PROGRAM COUNTER ADDRESSING

Reg= 7
MOOE

2
3
6
7

immediate
absolute
relative
relative deferred

operand n follows instr

@#A address A follows instr
A
instr ad rs+ 4
X is adrs

@A instr ad rs+ 4

+
+ X is ad rs of adrs

LEGEND
Operations

Op Codes
•
= O for word/1 for byte
SS = source field (6 bits)
DD = destination field
(6 bits)
R
= gen register (3 bits),
o to 7
XXX =offset (8 bits),
+127 to -128
N
= number (3 bits)
NN = number (6 bits)

) = contents of
= contents of source
=contents of destination

s
d

= contents of register
=becomes

X
O/o

= relative address
=register definition
= Concatenated with

Boolean

Condition Codes

•

= conditionally set/cleared
= not affected
o =cleared
1 =set

=AND
= inclusive OR
= exclusive OR
=NOT

E-1

SINGLE OPERAND:

OPR dst

OP CODE

SS 0" OD

Mnemonlc

Op Code

Instruction

General
CLR(B)
COM(B)
INC(B)
OEC(B)
NEG(B)
TST(B)

•
•
•
•
•
•

05000
051DD
05200
05300
054DD
05700

clear
complement (1 's)
increment
decrement
negate (2's compl)
test

0
"'"'d
d+1
d-1
-d
d

•
•
•
•

06000
06100
06200
06300
000300

rotate right
rotate left
arith shift right
arith shift left
swap bytes

-+ C,d

add carry
subtract carry
sign extend

d+C
d-C
O or -1

dst Result N

Rotate & Shift
ROR(B)
ROL(B)
ASR(B)
ASL(B)
SWAB

c. d +d/2
2d

z V c
0 0
0 1

0 0

.. .. .. ..
.. .. .. ..
0 0

Multiple Precision
AOC(B)
SBC(B)
SXT

• 05500
• 056DD
006700

. .. .
0

Processor Status (PS) Operators
MFPS

106700

MTPS

1064SS

DOUBLE OPERAND:
15

move byte from
PS
move byte to PS

OPR src, dst

..
....

d +-PS

PS +-S

OPR src, R or OPR R, dst

12
OP '.:ODE

DD
I

'."- I

OP COO€

Mne·
monlc

Op Code Instruction

s
SS 0" DD

Operation

General
MOV(B) • 1SSDD
CMP(B) • 2SSDD
ADD
06SSDD
SUB
16SSDD

d +- s
s-d
d+-s+d
d+-d-8

move
compare
add
subtract

Logical
BIT(B)
BIC(B)
BIS(B)
XOR

• 3SSDD
• 4SSDD
• 5SSDD
074RDD

bit test (AND)
bit clear
bit set (OR)
exclusive OR

E-2

S II d
d +-('-'S) II d
d+-svd
d+-r¥d

z v c

..
... ... .. ...
... ...
..
0

0
0
0
0

Optional EIS
MUL
DIV
ASH

070RSS
071RSS
072RSS

ASHC

073RSS

r <E- r x s
r <E- r/s

multiply
divide
shift
arithmetically
arith shift
coml!loined

•

•
•

•

Optional FIS
FADD
FSUB
FMUL
FDIV

07500R
07501 R
07502R
07503R

BRANCH:

B - - location

floating add
floating subtract
floating multiply
floating divide

0 0
0 0

If condition is satisfied:
Branch to location,
New PC <E- Updated PC + (2 x offset)
,.-----"-----,

adrs of br instr+ 2

•

BASE CODE

XXX

Op Code = Base Code + XXX
Mnemonic

Branch Condition

Base Code Instruction

Branches
BR
BNE
BEQ
BPL
BMI
BVC
BVS
BCC
BCS

000400
001000
001400
100000
100400
102000
102400
103000
103400

branch (unconditional)
br if not equal (to 0)
br if equal (to 0)
branch if plus
branch if minus
br if overflow is clear
br if overflow is set
br if carry is clear
br if carry is set

(always)

:;t 0
-0

Z=O
Z=1
N=O
N =1
V=O
V=1
C=O
C=1

Signed Conditional Branches
BGE
BLT
BGT
BLE

002000 br if greater or
equal (to 0)
002400 br if less than (O}
003000 br if greater than (0)
003400 br if less or
equal (to 0)

N~V=O

<O
>O

N_..,.V=1
Z v (N...,.V) = 0
Zv(N...-V)=1

cvz= 0
CvZ = 1

Unsigned Condltlonal Branches
BHI
BLOS
BHIS
BLO

101000 branch if higher
101400 branch if lower
or same
103000 branch if higher
or same
103400 branch if lower

E-3

~
~

C=O

C=1

JUMP Ir SUBROUTINE
Mnemanic

Op Code

Instruction

JMP
JSR
ATS

0001DD
004RDD
00020R

MARK
SOB

0064NN
077ANN

jump
PC <E- dst
jump to subroutine}
return from
·
use same A
subroutine
mark
aid in subr return
subtract 1 & br
(A) - 1, then if"(R) f. O:
(if -:j:. 0)
PC <E- Updated PC (2 x NN)

Notes

TRAP Ir INTERRUPT:
Mnemanic
EMT
TRAP
BPT
IOT
RTI
ATT

Op Code

Instruction

Notes

104000
to 104377
104400
to 104777
000003
000004
000002
000006

emulator trap
(not for general use)
trap

PC at 30, PS at 32

breakpoint trap
input/output trap
return from interrupt
return from interrupt

PC at 14, PS at 16
PC at 20, PS at 22

PC at 34, PS at 36

inhibit T bit trap

MISCELLANEOUS:
Mnemonic

Op Code

Instruction

HALT
WAIT
RESET
NOP

000000
000001
000005
000240

halt
wait for interrupt
reset external bus
(no operation)

CONDITION CODE OPERATORS:
15 .

0
1

I011 I N I z I v I c I

OP COOE BASE • 0002.W

= CLEAR SELECTED COND. CODE BITS
= SET SELECTED COND. CODE BITS

Mnemonic

Op Code

Instruction

CLC
CLV
CLZ
CLN
CCC

000241
000242
000244
000250
000257

clear C
clear V
clear Z
clear N
clear all cc bits·

SEC
SEV
SEZ
SEN

000261
000262
000264
000270
000277

set C
set V
set z
set N
set all cc bits

sec

E-4

z v c

- 0
- - 0 -

0
0
0 0 0 0
1

- 1
- "" 1

PROCESSOR STATUS WORD

I
..________...;

1 ~CARR•

OVERFLOW
ZERO

NEGATIVE
TRACE TRAP
PRIORITY

POWERS OF 2

.!!.

0
1
2
3
4
5
6
7
8
9

1
2
4
8
16
32
64
128
256
512

ABSOLUTE
LOADER
Starting
Address: - 500
Memory Size:
4K 017
BK 037
12K 057
16K 077
20K 117
24K 137
28K 157

~
10
11
12
13
14
15
16
17
18
19

2n
1,024
2,048
4,096
8,192
16,384
32,768
65,536
131,072
262,144
524,288

BOOTSTRAP LOADER
Address

Contents Address Contents

-744
-746
-750
-752
-754
-756
-760
-762

016 701 -764
000 026 -766
012 702 -770
000 352 -772
005 211 -774
105 711 -776
100 376
116 162

E-5

000

002

005
177
000
177

267
756
765

400

560 (TTY)

TRAP VECTORS
000
004
010
014
020

(reserved)
Time Out & other errors
illegal & reserved instr
BPT instruction
IOT instruction

024
030
034
244

Power Fail
EMT instruction
TRAP instruction
FIS (optional)

ODT COMMANDS

Format
RETURN
LINE FEED

Description
Close opened location and accept next command.
Close current location; open next sequential
location.
Open previous location.
Take contents of opened location, index by contents of. PC, and open that location. (ASCII 137)

I
$n/or Rn/
r;G or rG
nL
;P or P
RUBOUT

Take contents of opened location as absolute
address and open that location.
Open the word at location r.
Reopen the last location.
Open general register n (0-7) or S (PS register).
Go to location r and start program.
Execute bootstrap loader using n as device CSR.
Console device address is 177560.
Proceed with program execution.
Erases previous numeric character.
Response is a backslash (".).
7·BIT ASCII CODE

Octal

Code

Char

Code

000
001
002
003
004
005
006
007
010
011
012
013
014
015
016

NUL
SOH
STX
ETX
EOT
ENO
ACK
BEL
BS
HT
LF

040
041
042
043
044
054
046
047
050
051
052
053
054
055
056
057
060
061
062
063
064
065
066
067
070
071
072
073
074
075
076
077

017

020
021
022
023
024
025
026
027
030
031
032
033
034
035
036
037

VT
FF
CR

so
SI
DLE
DC1
DC2
DC3
DC4
NAK
SYN

ETB
CAN
EM
SUB
ESC
FS
GS
RS

Octal
Char

Code

100
101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
120
121
122
123
124
125
126
127
130
131
132
133
134
135
136
137

!
II

$
D/o
&

+
I
0
1
2

3
4
5
6
7

8
9

~
>?
E-6

Octal
Char

Code Char

140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161
162
163
164
165
166
167

A
B

E
F
G
H
I
J
K
L
M
N

u
v
w

x
z

[

170

171

'
a

f
g
h
i
j
k

I
m
n
0

p
q
r

s
t

u
v

w
x
y

172

173
174
175
176
177

{

}

DEL

NOTES

DIGITAL EQUIPMENT CORPORATION, Corporate Headquarters: Maynard,
Massachusetts 01754, Telephone: (617) 897-5111
SALES AND SERVICE OFFICES
UNITED STATES-ALABAMA, Huntsville • ARIZONA, Phoenix and Tucson •
CALIFORNIA, El Segundo, Los Angeles, Oakland, Ridgecrest, San Diego, San
Francisco (Mountain View), Santa Ana, Santa Clara, Stanford, Sunnyvale and Woodland
Hills• COLORADO, Englewood • CONNECTICUT, Fairfield and Meriden • DISTRICT
OF COLUMBIA, Washington (Lanham, MD) • FLORIDA, Ft. Lauderdale and Orlando •
GEORGIA, Atlanta • HAWAII, Honolulu • ILLINOIS, Chicago (Rolling Meadows) •
INDIANA, Indianapolis • IOWA, Bettendorf • KENTUCKY, Louisville • LOUISIANA,
New Orleans (Metairie) • MARYLAND, Odenton • MASSACHUSETTS, Marlborough,
Waltham and Westfield • MICHIGAN, Detroit (Farmington Hills) • MINNESOTA,
Minneapolis • MISSOURI, Kansas City (Independence) and St. Louis • NEW
HAMPSHIRE, Manchester • NEW JERSEY, Cherry Hill, Fairfield, Metuchen and
Princeton • NEW MEXICO, Albuquerque • NEW YORK, Albany, Buffalo (Cheektowaga), Long Island (Huntington Station), Manhattan, Rochester and Syracuse •
NORTH CAROLINA, Durham/Chapel Hill • OHIO, Cleveland (Euclid), Columbus and
Dayton • OKLAHOMA, Tulsa • OREGON, Eugene and Portland • PENNSYLVANIA,
Allentown, Philadelphia (Bluebell) and Pittsburgh • SOUTH CAROLINA, Columbia •
TENNESSEE, Knoxville and Nashville • TEXAS, Austin, Dallas and Houston • UTAH,
Salt Lake City • VIRGINIA, Richmond • WASHINGTON, Bellevue • WISCONSIN,
Milwaukee (Brookfield) •
INTERNATIONAL-ARGENTINA, Buenos Aires • AUSTRALIA, Adelaide, Brisbane,
Canberra, Melbourne, Perth and Sydney • AUSTRIA, Vienna • BELGIUM, Brussels •
BOLIVIA, La Paz • BRAZIL, Rio de Janeiro and Sao Paulo • CANADA, Calgary,
Edmonton, Halifax, London, Montreal, Ottawa, Toronto, Vancouver and Winnipeg •
CHILE, Santiago • DENMARK, Copenhagen • FINLAND, Helsinki • FRANCE,
Grenoble and Paris • GERMANY, Berlin, Cologne, Frankfurt, Hamburg, Hannover,
Munich and Stuttgart • HONG KONG • INDIA, Bombay • INDONESIA, Djakarta •
IRE LAND, Dublin • ITALY, Milan and Turin • JAPAN, Osaka and Tokyo • MALAYSIA,
Kuala Lumpur • MEXICO, Mexico City • NETHERLANDS, Utrecht • NEW ZEALAND,
Auckland • NORWAY, Oslo • PUERTO RICO, Santurce • SINGAPORE • SWEDEN,
Gothenburg and Stockholm • SWITZERLAND, Geneva and Zurich • UNITED
KINGDOM, Birmingham, Bristol, Edinburgh, Leeds, London, Manchester and Reading
• VENEZUELA, Caracas •