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Document:	Asynchronous Serial Interface for Connecting a PDP-11 to the ARPANET (BBN 1822) by Ronald C. Crane July 1976 Technical Report No. 116 The views and conclusions contained in this document are those of the author and should not be interpreted as necess
Order Number:	XX-2FB88-F9
Revision:	0
Pages:	46
Original Filename:	CSL-TR-76-116.pdf

OCR Text

Asynchronous Serial Interface for
Connecting a PDP-11

to the

ARPANET (BBN 1822)

Ronald C. Crane

July 1976

Technical Report No. 116

The views and conclusions contained
in this document are those of the
author and should not be interpreted
as necessarily representing the officia I
policies, either express or implied, of
the Defense Advanced Research Projects
Agency or the United States Government.

This research

was supported

by the

Defense Adva riced Resea rc h Projects
Agency under ARPA Order No. 2494,
Contract No. MDA903-76C -0093.

PlGnAL svsnms LABORlTORV
STlllFORD ElECTROlllCS LRBORRTORIES
STanFORD unwm5m . STIIIFORP, CIlllFORnM

Asynchronous Serial Interface
for Connecting a
PDP-11 to the ARPANET (BBN 1822)

Technical Report No. 116

July 1976
Ronald C. Crane
Digital Systems Laboratory
Departments of Electrical Engineering and Computer Science
Stanford University
Stanford, California

ABSTRACT
This report describes an interface to permit the connection of any PDP-11
to either the Packet radio network or the ARPAnet. The interface connects
to an IMP on one side, meeting the specifications published in BBN report
number 1822, and to a 16 bit parallel interface (DRV-11 or DRll-C) as described in the DEC peripherals and interfacing handbook. The interface card
itself is a double height board (5.2"x8.5") which can be plugged into any
peripheral slot in a PDP-11 backplane. The interface card is connected to
the parallel interface card via two cables with Berg 40 pin connectors
(DEC H-856) and to the IMP via an Amphenol bayonet connector (48-l@R-18-31s).
All 3 cables and connectors are supplied with the I/O interface card. The
parallel interface card (DEC DRll-C or DRV-11) together with the special I/O
interface card described in this report comprise the 1822 interface. The
report includes descriptions of the operation of circuits, programming, and
diagnostics for the 1822 interface.
KEY WORDS
BBN 1822 INTERFACE, HOST-IMP INTERFACE, LSI-11, PDP-11, DRV-11, DRll-C
PACKET-RADIO-HOST INTERFACE, ASYNCHRONOUS SERIAL INTERFACE, ARPANET
The views and conclusions contained in this document are those of the author
and should not be interpreted as necessarily representing the official
policies, either express or implied, of the Defense Advanced Research Projects
Agency or the United States Government.
This research was supported by the Defense Advanced Research Projects Agency
under ARPA Order No. 2494, Contract No. MDA903-76C-0093

T.able of Contents
Contents

Section
1.0

Introduction
1.1

2.0

3.0

4.0

Block Diagram

Page
3
3

Transmit Section

2.1

Host Power Relay

2.2

Data Section
2.2.1
Data Path
Handshaking Procedure
2.2.2
Last Host Data Bit Signal
2.2.3
Transmit Enable
2.2.4
Initialize Pulse
2.2.5
Load Pulse
2.2.6
Interrupt Request
2.2.7

Receive Section

3.1

IMP Power Sensing

3.2

Data Section
Interrupt Request
3.2.1
Initialize 6 Read Pulses
3.2.2
Bit 15 Output
3.2.3
3.2.4
Data
Bit Count
3.2.5
Receiver Timing
3.2.6

Electrical Specifications
4.1

Line Drivers and Receivers

4.2

Power Distribution on Board

5.0

Changing Time Delays

6.0

Connectors

6.1
7.0

Loopback Test Connector

Programming

21
23

7.1

Status Register

7.2

Input and CL&put Buffers

8.Q

7.3

Transmit Register
Data Section
7.3.1
Control Section
7.3.2

7.4

Receive Register
Data
7.4.1
Control
7.4.2

7.5

Reference Tables

Diagnostics

G.1

Packet Source/Sink Program
Description of Program
8.1.1
Running Source/Sink Program
8.1.2
Source/Sink Program Listing
8.1.3

8.2

Scope Loop
8.2.1
Running Scope Program
Using Scope Loop
8.2.2

Appendix
A

DRll-C Specifications

Parts list for Interface

413

’

l.Q

Introduction

This report describes an interface to permit the
connection of any PDP-11 to either the Packet radio network
or the ARPAnet. The interface connects to an IMP on one
side, meeting the specifications published in BBN report
number 1822, and to a 16 bit parallel interface
(DRV-11 or
DRll-C)
as described in the DEC peripherals and interfacing
handbook.
The interface card itself is a double height
board (5.2"x8.5")
which can be plugged into any peripheral
slot in a PDP-11 backplane. The interface card is connected
to the parallel interface card via two cables with Berg 40
pin connectors (DEC H-856) and to the IMP via an Amphenol
bayonet connector
(48-10R-18-31s).
All 3
cables
and
connectors are supplied with the I/O interface card. The
parallel interface card (DEC DRll-C or DRV-11) together with
the special I/O interface card described in this report
comprise the 1822 interface.
Except for differences in handling the IMP power relay
status, this interface reflects the current prototype as
constructed by SRI.
In the SRI unit, an interrupt is
continuously generated when the IMP goes
down.
Tne
interrupt
generation can be stopped by disabling the
receiver, after which it is necessary to poll the interface
to see if the IMP comes back up. The interface describe0
here generates one interrupt on each change of state of tile
IMP.
The
following
sections describe the operation of
circuits,
programming,
and diagnostics
for
the
1822
interface.
1.1

Block Diagram

The block diagram shows the basic parts of the special
I/O interface card and its connections to the parallel
interface card and the IMP.
The parallel interface card performs interrupt control
on the PDP-11 unibus. It has 3 addresses on the Unibus; the
control and status register, the output register, and the
input gate. The status register includes both the interrupt
enable bits as well as the transmit and receive enable bits.
The output register is a buffer whose contents change only
when the interface is loaded (written into). The input gate
does not contain a buffer.
Its function is only to gate its
input signal to the Unibus. Thus the data sections of the
I/O card need only store data for the receiver, but not the
transmitter. A block diagram and description of the parallel
interface unit supplied by DEC are in the appendix.
In the following section, the reader is referred to the
block diagram as well as the circuit and timing diagrams
that follow.

1
I

2.0

Transmit Section

The transmitter has two independent sections.
the power relay and the other is the data section.

One is

2.1 Host Power Relay
Bits 12 and 13 in the output register control the host power
relay contacts.
They are the R and S inputs to an R-S flip
flop. Setting bit 12 closes the contacts, and setting bit
13 opens the contacts.
If both bits are on, the contacts
will be closed.
If both bits are simultaneously cleared
after both being set, the resulting contact position is
indeterminate.
Last State
New State
Bit Bit
Bit
Bit
13
12
13
12
( any 1
0
0
( any )
0
1
( any 1
1
0
( any 1
1
1
1
1
0
0
Initialize Pulse

Contact Status
No change
Contacts closed
Contacts open
Contacts closed
Indeterminate
Contacts open

Bits 12 and 13 need to be set only once, as can be seen
from the table, since the state of the relay remains at its
previous setting when bits 12 and 13 are both zero.
Since the transmit register cannot be used to read out
the state of the relay, bit 13 of the receive register is
used for that purpose. Bit 13 is a 1 if the contacts are
open, and 0 if they are closed.
Bit 13 of INBUF
0
1

Contact position
CLOSED
(Host power on)
OPEN
(Host power off)

The relay used is a Magnecraft W107-DIP-1 reed relay.
Magnecraft claims the contact bounce is less than 500
microseconds. Therefore to be safe, no data should be
transmitted until 1 millisecond after the relay is closed.
This means that bit 12 of the transmit register ( OUTBUF )
must be set before transmit enable is 'set to prevent the
interface from transmitting a byte when the power bit is
set.
2.2 Data Section
The data section of the transmitter is an 8 bit parallel to
serial converter implemented with a multiplexer. The 8 bit
data byte and control information are supplied by the DRll-C
whose output buffer holds these values until they are
replaced by new data and control information.

2.2.1 Data Path
The actual parallel to serial conversion is done by an 8
line multiplexer
(74152), which selects bits 7 to 0 of the
output buffer and directly feeds the output driver. The bit
selection is done by the low order 3 bits of a 4 bit binary
counter (74193). The counter starts at zero and is advanced
one count each time the RFNHB (Ready for Next Host Bit) line
makes a high to low transition. On the 8th count the high
order bit becomes a 1 and is used to inhibit further
counting and also to generate a transmit interrupt request.
2.2.2 Handshaking Procedure
When the RFNHB line goes high, and transmit enable is a 1
(enabled),
the TYHB (There's Your Host Bit) line goes high
indicating availability of a data bit.
RFNHB eventually
goes low indicating acceptance of data. This triggers the
74123 pulse generator generating a pulse T4 seconds long
(nominally 1 microsecond).
The leading edge of the pulse
advances the counter. The TYHB line is held low for at
least the duration of the pulse, and possibly longer if the
RFigHB line remains low for longer than the pulse duration.
Using the pulse generator provides a straightforward method
of meeting the minimum pulse width requirements for the
2-Way handshake.
This is useful when operating over long
cables. For systems using only a 4-Way handshake, a simple
time delay would suffice as long as it is long enough to
allow the counter and multiplexer to settle after being
advanced (See transmit timing diagram for details).
2.2.3 Last Host Data Bit (LHDB) Signal
The LHDB signal is asserted if the Last Byte signal is
present (bit 11 in OUTBUF is a 1)
and the counter is
selecting
the last bit of the byte to be transmitted. The
timing for this signal coincides with the timing for the
data signal.
2.2.4 Transmit Enable
The transmit enable signal is used to gate out the interrupt
request signal as well as to hold off data transmission
while it is low.
When the transmit enable signal is
returned to the " 1 " (enabled) state, the transmitter waits
for new data to be loaded into the output register
(OUTBUF)
before starting transmission. This means that the transmit
enable line cannot be used to turn the transmitter on and
off in the middle of a byte since the remainder of the byte
would never be transmitted.

2.2.5

Initialize Pulse

The initialize pulse resets the counter to zero and opens
the host power relay contacts. It also clears the registers
in the DRV-11, thus clearing the transmit enable signal.
2.2.6 Load Pulse
The load pulse resets the counter and holds the TYHB line
low for the duration of the load pulse
(nominally 300
nano-seconds). If it is the first load pulse after the
transmit enable line has been raised (=l), it also clears
the hold-off flip-flop.
The hold-off flip flop prevents
handshaking from occurring until the first load pulse after
the transmit enable line goes high.
2.2.7

Interrupt Request

A transmit interrupt can occur only after the last data bit
has been received by the IMP and both of the following
conditions have been met.
XMT enable is set
XMT interrupt enable is set

(=I)
(=l)

Bit 0 in DRCSR
Bit 6 in DRCSR

If one wishes only to poll the interface, only the XMT
enable needs to be set.
Bit 7 of the status register
(DRCSR)
indicates
the state of the INT A line. If an
interrupt has been requested, bit 7 will be a one.
If bit
6 is also set, an interrupt will actually occur.

+
I

/
aI
5

vv-I

N-l

s
d

1-I
n-r
NN-I
n-1

I - tj 3-I

VI
\o

1
o

is clocked or

Signal is

_\,+Discontinuous

the

Input

break

can be

irrelevant.

in time: timing sequences separated by
may not follow each other m normal operation.

timing diagram.
Ez On
either 0 or 1.

width

The width of the

The

lead.

A positive pulse appears on this lead.
pulse may be indicated as well.

Uext to an input lead indicates the device is clocked or
triggered by a high to low level transition.

1Scxt to an input lead indicates the device
triggered by a low to high level transltion.

Yorcnclatucc

A negative pulse appears on this
u pulse may be indicated as well.

* Vertical bar indicates transition

LOAD 1
PULSE 0

XMT
F
ENABLE0

HOST
LDB

DATA

REQ

INT A

TYHB

RFNHB

2-Way
Handehake

Figure 3
TRANSMIT TIMING

8th Bit

7th Bit 1 Last Bit of Pkt

7th Bit Last Byte

2-Way or 4-Wa
Handshake
I
ignored

3.0

Receive Section

Tne receive section supplies one byte of data along with
control information.
The receiver is divided into two
One part senses the status of the IMP power relay
parts.
contacts and the otner sart performs the handshaking and
serial to parallel conversion.
3.1 ip1P power Sensing
The IMP power relay contacts grounaf the filtered input to
the inverter. The 39 ohm resistor, 5 microfarad capacitor
and the 1BK resistor provide some debouncing of the relay
contacts.
This supplies a signal through the inverters
directly to the DRV-11 (bit 12). The high to low and low to
high transitons generate a pulse via the EXCLUSIVE-OR gate
and time delay which sets the power interrupt flip flop.
See figure 4 illustratin j the EXCLUSIVE-OH pulse generator.
An interrupt request is generated if the receive enable bit
is set in the DRCSR (bit 1). An interrupt will actually
occur if bit 5 is also set.
These actions will occur
independent of actions in the data section of the receiver.
Bit 14 (=l) indicates that the interrupt was initiated t3 y
the INP po\nJer relay (IMP recently down) and bit 12 indicates
the current status of the Ii'W relay.
3.2 Data Section
The data path in this section is from We line receiver
directly to the serial-in, parallel-out shirt register
(74164).
The data is strobed into the shift register Tl
sec. after the THB signal is asserted (=l). Tile time delay
Tl allows deskewing of the signals on the TYItj line and the
data and LDB lines.
This time delay can be varied by
changing the timing capacitor. After the data is strobed
into the register,
the RFNW line is dropped (=cI).
It is
held down for a minimum period of T2 sec.
and possibly
longer if the TYIB line has not dropped when T2 has elapsed.
The RFNIB line will not go high again until tile TYIB line is
dropped.
This
meets
the
requirement of tne 4-\iay
handshaking procedure. The perioa T2 occuring after t i l e
data is strobed
into the register is to meet the mininun
pulse width requirements when using the 2-Way handshaking
procedure on long cables. The pulse width requirement at
the I;IP end of the cable can also be met by changing
the
appropriate timing capacitor on the interface card.

3.2.1

Interrupt Requests

An interrupt request can be generated only if the Receive
enable line is high (DRCSR bit 1 is 1)
and one of the
following is true:
8 bits have been received since the last interrupt as
a)
counted by the 74193 counter.
The Last Data Bit UJW
flip flop has been set by
b)
receipt of an LDB signal.
The power status flip flop has been set due to a change
c>
in
the status of the IMP power relay contacts.
(Connecting and disconnecting the cable will have the
same effect.)
3.2.2

Initialize and Read Pulses

Both the read and the initialize pulses produce a pulse on
the clear line in the interface. The initialize pulse is
inverted and fed directly to the clear line. The trailing
edge of the read pulse indicates that the data has been read
from the register. The pulse generator T3 generates a 1
lmicrosecond pulse AFTER the trailing edge of the read pulse.
idhen
the
clear line is lowered
(=Q) I the register,
flip-flops, and counter are cleared. T2 pulse generation is
inhibited and the TYIB input signal is held low for the
duration of a clear pulse.
3.2.3 Bit 15 Output
Bit 15 is the OR value of bit 14 (IMP recently down) and bit
11, the LIDB bit in the receive register.
It is V" only if
the last bit of a packet has been received (the only time
the LIMB line is asserted) or the the IMP has lost and/or
regained power (its relay contacts changed position).
3.2.4 Data
The data bits appear in the low order byte of the receive
register (bits g-7).
The most significant bit (MB) or bit
7 is the first bit received from the line and the least
significant bit (LSB) or bit GJ is most recently received
bit.
3.2.5 Bit Count
The three
bits (8,9,10) indicate how many bits have been
received since the last interrupt. If a number other than Q
appears in these three bits, a full byte has not been
received.
The bits are a binary number indicating how many
bits have been shifted into the register. The data bits are
shifted into the low order byte starting at bit 0 and moving
toward bit 7. Thus, the MSB starts at bit 0 and moves
toward bit 7, its final destination.
If the bit positions

were numbered 1 to ti (LSD to r'JIS13) instead of 0 to 7,
then
the bit count
(l&9,8) i s the position of the MSB. 000
Tileans the MSt3 has reached its final destination.
3.2.6 Receiver Timing
See the timing diagrai;ls for the receiver in figure 6.

P
id

l-Off
O-On

IMP PWR

Figure

EXCLUSIVE-OR Pulse Generator

1
-

Truth Table

IMP Power Relay Receiver Circuit Pulse Generator

Exclusive OR

Y = AK + AB

Exclusive OR Pulse Generator (on level transitions)

clocked

I/
\A

Input

c a n be

The width of the

the

+,Discontinuous in time: timing sequences separated by a break
ray not follow each other in normal operation.

may be

n e g a t i v e p u l s e appears on
indicated as well.
-Lr Apulse
On timing diagram. S i g n a l i s irrelevant.
zz either 13 or 1.

this lead.

The width of

RECEIVE UNIT TIMING

4-Way Handshake Last Bit

Figure 6

2-Way or 4-Way
Handshake

input. lead indicates the device is clocked or
to
an
trlggcced by a high to low level transltlon.

Uext

A positive pulse appears on this lead.
J-L pulse may be indicated as well.

? triggered by a low to hlqh l e v e l transition.

Wext to an input lead indicates the device

Worcnclaturc

LDB UNF

INT B REQ.

CLEAR LTNF

COUNTERJIATA
& LOB STROBE

RFNIB

TYIB

I
4-Way Handshake

,>7.

,..

A- . . .

Read or Clear Pulse

Electrical Specifications

4.0

This section provides details on the power Miring for the
board and data on the line drivers and receivers.
4.1 Line Drivers and Receivers

(DM 8820 and DM 8830)

The line drivers are National DM 7830/8830 differential
The receivers are National DM 7820/8820
balanced drivers.
Connection details are
differential balanced receivers.
shown in the figure showing drivers and receivers. The
termination
receivers provide a high impedence (2.5K or 5K)
of the line, with protective clamping at + and - 4 volts
with respect to ground. When an input is out of the + or 4 volt range, the input impedence from the out of rarqe
input to ground is 180 ohms. The maximum input voltage for
any input lead should be held to + or - 10 volts with
respect to ground. This is the dissipation limit of the
yotection circuit.
The outputs are balanced differential and provide a 1.2
volt differential voltage swing with a +.6 volt common mode
voltage (both measured open circuit).
i>utput
B
0 v +1.2 v
a v
+1.2 v

Logic State

w
1

The output impedence is 130 ohms differential balanced \nlith
respect to ground (or 65 ohms to ground from each side).
4.2

Power Distribution

The power distribution is shown in figure 8.

Figure 7
Line Drivers & Receivers
Electrical Specifications
Differential Balanced Drivers (130 ohms balanced,
65 ohms each side to ground)

Drivers:

Input
TTL

Nat ional DM7830/8830
(2 units per package)

Input

outputs (volts)
B

Logic

Voltage

0 v

1.2

3 v

1.2

II.

Receivers

Balanced Differential, NO termination
+3.6 volts
?l

Balanced
Input

A+
l TTL output

2 units per package
-3.6 volts
Diodes are lN4148 or equiv.
Typical threshold voltage is 100 mV.
Non-inverting input resistance is 2.5K ohms to ground.
(pins 3 & 11)
Inverting input resistance is 5K ohms to ground (pins 1 & 13).
Protection clamps input to receiver at + 4 volts.
180 ohm
-& watt input resistor will fail with-sustained inputs
ibove 10 volts.
The 7820 and 7830 operate over the military temperature
range (-55OC to 125OC).
The 8820 and 8830 operate
over the commercial temperature range (OOC to 70°C).

.- ;“*

0
0

I
f 0
j
I
(

i%
-0
a
-0
L

z
I

l
M

>
Lo
+

%
>
N
I--

5.0

Changing Time Delays

The value of the time delays is linearly proportional to the
value of the timing capacitor over reasonable values of time
delay.
Thus to change the time delays,
timing
the
capacitors should be changed accordingly. All time delays
shown are set to one microsecond.

6.0

Connectors

The I/O interface card makes 4 connections to
world.

the

outside

Edge connector on the card. DEC double height
a)
board. +5 volts and ground are used.
Current
consumption is about 6130 mA.
b) Berg 40 pin connectors (2), one for input and one
for output to parallel interface. They are labeled Jl
and J2 corresponding to DEC nomenclature.
(Pin
numbers at the top of the schematics indicate the
connector number and pin number. Connector 2, pin VV
is 2-VV.) The connector number is DEC H-856
c)

Amphenol 31 pin female bayonet connector. This is
specified by the BBN 1822 report. The pin numbers for
this connector are on the bottom of the schematics
along with the signal name. The connector is Amphenol
number 48-10R-18-31s.

213

6.1
Originate
Pin No.

Loopback Test Connector
Destination
Pin No.

Signal
Name

+ LDB
- LDB

3
4

23
24

+ Data
- Data

5
6

19
20

+ TYB
- TYB

7
8

17
18

+ RFNB
- RFNB

11
12

13
14

Power Relay
Power Relay

‘
\

S\\

,”
/ ,-

I-

7.0

Programming

The programmer has 3 registers to deal
with in
programming the interface: the status register, the input
buffer, and output buffer.
7.1 Status Register
This register has 4 read/write enable bits, and 2 read
only status bits.
There are two enable bits, one each to
allow operation of the transmitter and receiver.
The two
status bits indicate whether a receive interrupt request has
occurred. An interrupt request can occur only if the
respective transmitter or receiver has been enabled.
An
interrupt will actually occur if the appropriate interrupt
enable bit (one for receive & one for transmit)
has also
been set.
7.2 Input and Output Buffers

Both the input and output buffers are divided into a data
section (bits 0:7) and a control section (bits 8:15).
The
user should not write into the transmit register or read
from the receive register if they are in the process of
transmitting or receiving a byte of data.
Reading or
writing into a register while it is in the process of
transferring a byte may cause some bits to become lost
and/or out of synchronization.
This can be avoided by
waiting until either an interrupt or interrupt request (as
seen in the status register) is present before accessing the
register.

7.3 Transmit (Output) Register
r3ne byte of data will oe transiGtted each time this rqister
is loaded if the transmit enable bit is set. Any old data
will be cleared upon loading, independent of the state of
transmit enable.
7.3.1 Data Section (Bits 0:7)
Bit 0 is least significant bit.
Bit 7 is the most
significant bit and is the first bit to be transmitted.
7.3.2 Control Section
Bit 11 (LHDB)- If this bit is set, the last host data
bit line will go high during the transmission of tile
last data bit in the byte (bit 0).
Bit 12 - Host Power Relay Set- If this bit is set, the
host power relay contacts will be closed indicating host
is up. This bit need be set only once since the
interface will latch the value. Either an initialize
pulse or setting bit 13 will clear the latch. The latch
will remain in the last state to which it was set.
Bit
13 of the receive register contains the status of the
latch.
Although the power latch can be set any time, it is
recommended that the relay be turned on before the
transmit enable bit is set in the status register. This
prevents a data byte from being transmitted when the
relay is turned on. It is important because the host
must wait until the contacts have solidly closed before
transmitting data which is approximately 1 mS for the
relay used.
Bit 13 - Host power relay clear clears the HOST power relay.

Setting

this

bit

7.4.0 Receive Register
Reading the receive register clears the receive buffer
making it ready for another byte. Thus program testing of
control bits should be done after the contents of the
receive register have been moved elsewhere. If the receiver
wishes to suspend receipt of more data he can:
a) Not read the receive register.
b) Clear recieve enable after a receive interrupt and
then read the receive buffer. In this case he has
access to all data accepted by the interface and
blocked data at the entry point to the interface.
c) Clear receive enable
without
waiting
for an
interrupt. In this case some bits may be lost.
Setting receive enable will start the receiver again,
but not necessarily where it left off.
7.4.1 Data (Bits 0:7)
Bit Q is LSB and the last one received from the 1i.n~.
Bit 7 is MSB and the first one received from the line.
7.4.2 Control
Bits 8,9,10 - Point to last bit received in byte.
Bit 11 - (=l) Indicates last data bit line was asserted
concurrently with receipt of the last data bit.
Bit 12 - IMP Power status.
IMP power relay.

Indicates current status of

Bit 13 - Host power relay status. 0 - ON

the

1 - OFF

Bit 14 - Indicates the IMP has been down since the last
interrupt was serviced.
(i.e. the interrupt was
generated by IMP changing status.) (see bit 12 for
current status)
Bit 15 - Either bit 11 or 14 is a 1.
This bit being se t
indicates the current interrupt requires special
handling either because it is the last byte of a
packet, or the IMP has been down.

'7. 5

Programming the 1822 Interface
(with the DRV-11 or DRll-C)

The bus address and interrupt vector locations shown ar?
for the first DRll-C (DRV-11) in a system.
If there is more
than one DRll-C, or other devices competing for the same
address area, the proper numbers may not be the ones shown.
Check
the appropriate system documentation and/or the
hardware address jumpers on the DRll-C to be sure.

RCV
XMT XMT
U s e d - - - - ' Req. Int. A Xnt.B-Not Used
EnableEnable
B
-_________- - __----- A
15
14 13
12
I--9+-8 11 710
6
5
4
3
I
1
!
I

RCV
Req.

Not

Control and Status Register - DRCSR

Used - H o s t Host Byte -Used
Pwr. Fvr.
15
14
13
12
11
10 ,
- Not - - lear Set Last - Not
1
1
Transmit Register - OUTBUF

IMP NO NO
vas
Host IMP
‘lv l4 down Pwr. Fwr.
15
14
13
12
I

167770

6,
I

5,
DATA

3,
2
1
0
,--I

167772

Bit
Count

Last
Byte
11

9,
I

RCV XMT
EnableEnable
(CSRl)XR 0
2
1
0

DATA
9

5
I

Receive Register - INBUP 167774

2
1

Control and Status Register

DRCSR

167770

Function

Bit 15-

This bit indicates that the DRV-11 has received a request from the
If bit 5 of this register is
interface to generate an interrupt.
This bit is read only.
set, an interrupt will occur.

Bit 14-8 NOT USED
Bit 7

This bit indicates that the DRV-11 has received a request from the
interrupt.
If bit 6 of the
interface
to generate a transmit
interface is set, an interrupt will occur. This bit is read only.

Bit 6

interrupts
to
Transmit interrupt ENABLE- Setting this bit allows
be generated upon completion of transmission of each byte of data.
This bit is read/write.

Bit 5

Receive interrupt ENABLE- Setting this bit allows interrupts to be
generated upon receipt of each byte of data and/or a change in the
This bit is
status of the IMP power bit in the interface.
read/write.

Bits 4-2 NOT USED
Bit 1

Receive enable- Setting this bit enables the receiver (by allowing
bits
the RFNB line to go high). The interface will then receive
it is full, or it receives the last data bit (LD5)
until either
signal. At this point the interface stops and requests an
interrupt. It will not accept any new bits until the present
load of bits is read from INBUF. This bit is read/write.

Bit B

the transmitter
Transmit enable-Setting this bit enables
(by
allowing the TYB line to go high).
The interface will transmit
all bits which are loaded into OUTBUF after this bit is enabled.
This bit is read/write.

Transmit Register

OUTBUF

167772

Transm ission of a b y t e is initi ated each time
All bi ts are read/write.
OUTBUF is 1 oaded, the transmitter is enabled (bi t 0 of DRCSR is set).

Bit
15-14
13

Function

Not used
Setting

set

latch.
12

this bit releases the Host relay contacts.
This bit
only
once, as the interface holds the information
Either bit 13 OR bit 12 should be set.
NOT BOTH.

need
in a

Host Power Set- This bit sets the Host relay contacts.
As with
bit 13, this bit need be set only once, since the interface holds
the information in a latch. Either bit 13 or bit 12 snould b e
data should be sent until at least 1
NOT
BOTH.
No
millisecond after this bit is set to allow for relay contact
bounce.
set.

Last Data Byte-

This bit causes the last data bit (LDB)

go high concurrently with the transmission of the last
byte.

10,9,8
7-0

This is typically

DATA

(Bit 7 is the high order byte, and

set with the last byte of a packet.

NOT USED (On the early unit, these bits indicated
position to be transmitted within the byte.)
byte. 1

line

bit of the

bit

last
the

bit
order

Receive Register

INDUF

167774

The interface will receive bits until either it is full, or it receives the
(LIDB) signal.
At this point the interface stops and
last IMP data b i t
It will not accept any new bits until the present
requests an interrupt.
load of bits is read from INBUF.
BIT

FUNCTION

Special conditon - If set,
the b y t e of data j u s t received
requires special handling.
(i.e. it is either the last byte of a
packet, or there has been a change in the status of the IMP relay
contacts (IMP recently down).

IMP just went down or IMP has been down and just came up
0 - No change in IMP status
l- IMP has been down recently
(see

bit

for

current

status).

relay
HOST POWER- Indicates the current status of the Host power
as set or cleared b y either bit 12 or 13 respectively in the
This
bit
should
be
interpreted
as
transmit register OUTBUF.
follows:
- HOST power relay contacts closed
( ON 1
f - HOST power relay contacts open ( OFF )

IMP POWER- Indicates the current status of the IMP power
relay.
The bit should be interpreted as follows:
0 - IMP power ON
l- IMP power OFF
(See bit 14 to determine if the interrupt was generated by the
power circuit.)

LAST BYTE - If this bit is set, the data byte is the last one in
Bits 8,9,10 should b e checked
to determine the
a packet.
position within the byte of the last bit transmitted.

lB,9,8

Bit Count - The three bits (10,9,8) indicate how many b i t s have
been received since the last interrupt.
If a number other than 0
appears in these three bits, a full byte has not been received.
The bits are a binary number indicating how many bits have been
shifted
into
the
register.
The data bits are shifted into the
i t s
toward bit
7,
low order byte starting at bit 0 and moving
final destination. If the bit positions were numbered 1 to 8 (LSB
instead of 0 to 7, t h e n t h e b i t c o u n t (10,9,8) is t h e
to MSB)
000 means the MSB
has reached
its final
position of the MSB.
destination (position 8).

7-8

DATA - Bi t 7 is the MSB of the da ta byte and is the first bit
the byte to be received from the IMP.

INTERRUPT VECTORS FOR THE INTERFACE
Transmit Interrupt Vector
LOC.

300
302

Contents
XMT
200

=(PC)
=(PS)

Receive Interrupt vector
Lot.
304
306

Contents
RCV
200

= (PC)
=(PS)

XMT- Address of transmit interrupt routine
RCV- Address of receive interrupt routine

Diagnostics

8.0

It is assumed that the DRll-C or DRV-11 is functional
before these tests are attempted. If the above is not true,
the programmer/user has no means of accessing the special
If in doubt, the DRll-C tests should be run
I/O card.
first.
8.1

Packet Source/Sink

8.2

Scope Loop

8.1 Packet Source Sink Program
8.1.1

General

The packet source and sink program can be used to make
the interface do handshaking for hardware and software
checkout purposes.
The transmit part continuously loads the contents of 16
sequential memory locations into the transmit buffer.
The
low order byte is transmitted as data. Bit 11 of the high
order byte may be set both as an end of packet indicator and
also to test the LDB lines in the interface.
The receive or sink program circularly fills a 16 word
area in memory with the contents of the receive register.
The user may stop the program at any time to see the
contents of the last 16 bytes received.

8.1.2
A)

Running Source/Sink Program
Location 6Q2 determines what the program does.
It is
loaded into the control and status register of the
interface.
It should be loaded with one of the
following.
101 Transmit Only
Receive Only
42
143 Transmit & Receive
(octal) contain the transnit
Locations 440 to 476
buffer.
They should be filled with the data and
control as the user wishes. Words from the buffer are
successively loaded into the output buffer of the
interface.

Load the program into memory using ODT or switch
register. Alternately assemble the listing and load it
from some storage device.

The program starts at location 600 (octal) after it
loaded.

Source/Sink Program

8.1.3
Memory
location
(octal)

Contents

300
302
304
306

1000
200
70Q
200

Function

(octal)
\

I- Interrupt Vectors
I
/

4013
I

436

44Q
I

476

I- Receive Buffer
I bytes)

I- Transmit Buffer 16 words (8 transmitted
I bytes)

6130
GQ2
604
606
610
612
614
616
620
622
624
626

12737
see table
167770
127615
440
12704
400
12706
20130
12537
167772
777

7130
702
704
706
710
712
714
716

13724
167774
22704
440
113132
12704
400
2

MOV

1000
1002
1004
1006
117110
lQ12
1014
1016

12537
167772
22705
500
1002
12705
440
2

MOV

16777Q
167772
167774

16 words (8 received

MOV C(loc 602),DRCSR
101-Transmit
42-Receive

143-Both

R5=44Q
R4=400
R6=2000
MOV

(R5)+,0UTBUF

BR 626

Start transmitter
Wait loop

INBUF,(R4)+

COMP #440,R4
BNE 716
R4=400
RTI
(R5)+,0UTBUF

COMP #500,R5
BNE 1016
R5=440
RTI
DRCSR
OUTBUF
INBUF

8.2

Scope Loop Program

8.2.1

Running Scope Loop Program

Load Source/Sink program in 8.1.3 .

Location 602 should be 143 (transmit & receive)

Locations 440 to 446 should be:
440
442
444
446

000000
0Q0002
000200
004001

Change contents of location 1006 from
transmitter loops after 4 bytes.

Start program at location 60Q (octal).

5QQ

450

Using Scope Loop

8.2.2

The loop program transmits two word
transmitted continuously. They are:
Word 1

000002

octal

Word 2

1000Ql

octal

packets.

TheyT are

word
each
The most significant bit (MSB) of
transmitted first. Thus, the bytes are sent as follows:
Memory
Byte
Location No.
1
2
3
4

440
442
444
446

Binary
LSB

Octal
LSB

MSB

000
002
200
001

0Q000000
00000010
10000000
00000001

MSB

(LHDB asserted with
LSB of byte 4)

The last host data bit (LHDB) line is asserted with the last
bit (LSB) of the second word.
Scope Pattern for Test Program
(with loopback connector)

LDB
Line
TYHB/RFNIB
Line,

I
I

Data
Line

I
I
I

I
I‘
I
I
i----J‘!--I .-" -.__-___-.
I
I
t
Byte 1 1
Byte 2 1
Byte 3 1
MSB
LSB
LSB
MSB
LSB ' MSB

I
I
- __-- I Byte 4
MS B
LSB

Appendix

‘35

DRll-C Specifications
(from DEC Peripherals and Interfacing Handbook)

Parts list for Interface

REQ A (IN1 A)

I N T E R R U P T ,- REQ B IIM 5)
%;!
,It
A
,-IE 8

-.--- D

IS.00

- -

r,,:,,--TZ

I
I
I

I
I 1

~REOUEST A

:REQUtST

8 1

USER
DEVICE
LOCK
l
A 1 200
c
IO
M SYN
SSYN

D 1S:OO
P

AD3RESS
SELECTION
IOGIC

lPECElVClS
7

RFGISTER AND
CONTROL LOGIC
-----__-__--------I

I4
7
6

‘REQ
IE
iE
IAlAlBl

INPUT OA:A RWER

OUTPUT DATA BUFFER

B
4

CSR CSR
1
0

4-202

The register addresses can be changed by altering the jumpers on the
address selection logic. However, any arograms or other software re-

DR,NEiUF
?b7? 74

DROUTBUf f
767771

DRCSR UEO
?b???O
B

REGISTERS

BC08R (Berg-to-Berg) flat cable. Available in lengths of 1, 6, 8, 10,
12, 20, and 25 feet. When ordering, the dash number indicates the
.
desired cable length; e.g., BC08R-1 or BC08R-25.
M971 connector board. A single-height by 8-l/2 in. board that brings
the signals from one Berg connector to the module fingers.
BCllK-25 cable. Consists of a 20 twisted-pair cable with a Berg connector on one end only. Available in 25 ft lengths.
H856 Berg connector. Includes an H856 Berg connector and 40 pins.
Crimping tools are available from: Berg Electronics, Inc., New Cumberland, Pa. 17070.

BIT

The following accessories are available for interfacing:

REQUEST A

REQUEST B

NAME

Although the REQUEST and CSR bits can be used for any function the
user desires, standard PDP-11 interface conventions attempt to allocate
bit 15 for error conditions and bit 7 for ready indications and both of
these bits can generate interrupt requests. In addition, bit 0 is normally
used for start or go commands.

Physical Description
The DRll-C interface is packaged on a single quad module that can be
plugged into a small peripheral slot (SPC).

4-203

Read-only bit. Cleared by INIT when in Maintenance Mode.

When the maintenance cable is used, the state of
REQUEST A is identical to that of CSRO (bit 00).

Performs the same function as REQUEST B (bit
15) except that an interrupt is generated only if
INT ENB A (bit 06) is also set.

Read-only bit. Cleared by INIT when in Maintenance Mode.

When the maintenance cable is used, the state of
this bit is dependent on the state of CSRl (bit
01). This permits checking interface operation by
loading a 0 or 1 into CSRl and then verifying that
REQUEST B is the same value.

When used as a flag, this bit can be read by the
program to monitor external device status.

When used as an interrupt bequest, it is se<by the
external device and inithates an interrupt provided
the INT ENB B bit (bit 05) is also set.

This bit is under control of the user’s device and
may be used to initiate an interrupt sequence or
to generate a flag that may be tested by the program.

FUNCTION

DRCSR Bit Assignments

Two REQUEST bits, which are under device control, may be used to provide device status indications, or may be used to initiate interrupts when
used with associated INT ENB (interrupt enable) bits which are under
program control. Two other bits (CSRO and CSRl) are controlled from
the UNIBUS and serve as command bits.

The DRll-C can also be used as an interprocessor buffer (IPB) to allow
two PDP-11 processors to transfer data between each other. In this case,
one DRll-C is connected to each processor bus and the two DRll-Cs
are cabled together, thereby permitting the two processors to communicate.

The module has two Berg connectors for all user input/output signals.
Two M971 connector boards, which are not supplied with each interface,
can be used to bring all input/output lines to individual pins on a back
panel via two H856 cables. Note that this cable is a “mirror image”
rather than a straight one-to-one cable.

Control and Status Register (DRCSR) 767 770
The control and status register is used to enable interrupt logic and to
provide user-defined command and status functions for the external
device.

ferring to these addresses must also be modified accordingly if the
jumpers are changed.

DRll-C

A maintenance cable, which is supplied with the interface, permits
checking of the DRll-C logic by loading the input buffer from the output
buffer rather than from the user’s device. Thus, a word from the bus is
loaded into the output register and the same word appears when reading
the input buffer, provided the interface is functioning properly.

tenance mode, they are also used to check operation of the interface.

DRll-C

W
4

CSRl

Read/write bit. Cleared by INIT.

When the maintenance cable is used, the state of.
this bit controls the state of bit 07 (REQUEST A).

Performs the same functions as CSRl (bit 01) but
appears only on Connector No. 2.

Read/write bit (can be loaded or read by the program). Cleared by INIT.

When the maintenance cable is used, setting or
clearing this bit causes an identical state in bit 15
(REQUEST B). This permits checking operation of
bit 15 which cannot be loaded by the program.

This bit can be loaded or read (under program
control) from the UNIBUS and can be used for a
user-defined command to the device (appears
only on Connector No. 1).

Can be loaded or read by the program (read/write
bit). Cleared by INIT.

Interrupt enable bit. When set, allows an interrupt
sequence to be initiated, provided REQUEST B
(bit 15) becomes set.

Can be loaded or read by the program (read/write
bit). Cleared by INIT.

Interrupt enable bit. When set, aliows an interrupt
sequence to be initiated, provided REQUEST A
(bit 07) becomes set.

4-204

The DROUTBUF is cleared by INIT.

Whenever the maintenance cable is used, the data from the output
buffer is also applied to the input buffer register. This permits checking
operation of the interface logic.

The contents of the output buffer register may be read at any time by
means of a DATI or DATIP bus cycle. During the read operation, the output of the buffer is fed directly to the bus data lines.

Output Buffer Register (DROUTBUF) 767 772
The output buffer is a 16-bit read/write register that may be read or
loaded from the UNIBUS. Information from the bus is loaded into this
register under program control. At the time of loading, a pulsed signal
(NEW DATA READY) is generated to inform the user’s device that the
register has been loaded. The trailing edge of the positive pulse should
be used 13 allow the data to be loaded and settle on the user’s input
lines. Data from the buffer is transmitted to the user’s device on the
data OUT lines by means of a DATO or DATOB bus cycle.

CSRO

iNT ENB B

0 0

1NT ENB A

DRll-C

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2

Connector

TT
LL
H
BB
KK
HH
EE
cc
Z
Y
W
v
U
P
N
M
LL
S

OUT00
OUT01
OUT02
OUT03
OUT04
OUT05
OUT06
OUT07
OUT08
OUT09
OUT10
OUT1 1
OUT12
OUT13
OUT14
OUT15
NEW DATA RDY’:‘
DATA TRANS.*
CSRO
CSRl
INIT
!NIT

Signal

1
1
1
1
1
1
1
1
1
1
1
1
1
1.
1
1
1
2
2
1
1
2

C
K
NPi
U
L
N
R
T
W
X
Z
AA
BB
FF
HH
JJ
vv
C
K
DD
P
RR, NN

Connector Pin

outputs

4-205

‘;r Pulse signals, approximately 400.ns w~dc. Width can be changed by
user.

IN00
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
REQ A
REQ B

Signal

Inputs

Input and Output Signals

Whenever the maintenance cable is used, the input buffer register receives data from the output buffer regtster rather than from the user’s
device. This permits checking of the interface logic by loading a word
from the bus into the output register and verifying that the same word
appears in the input buffer.

Input Buffer Register (DRINBUF) 767 774
The input buffer is a 16-brt read-only register that receives data from the
user’s device for transmission to the UNIBUS. Information to be read is
provided by the user’s device on the data IN signal lines. Because the
input buffer consists of gating logic rather than a flip-flop register, the
data IN lines must be held until read onto the bus. The register is read
by a DATI sequence and the data is transmitted on the UNIBUS for
transfer to the processor or some other device. When the input lines are
read during a DATI sequence, a pulsed signal (DATA TRANSMITTED) is
sent to the user’s device to inform it that the transfer has been completed. The trailing edge of the positive-going pulse indicates that this
transfer is completed,

DRll-C

CrJ

M971

DRll-C

Pin Connections

B
A

UU
VV

A2
Al

c”
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
AA
BB
cc
DD
EE
FF
HH
JJ
KK
LL
MM
NN
PP
RR
ss
7-r

GND
uu
NEW DATA VV
RDY

OPEN
OPEN
OUT00
OPEN
OPEN
OPEN
OPEN
GND
OUT01
OUT04
GND
3UT05
INIT H
OUT06
GND
OUT07
OUT03
GND
OUT08
OUT09
GND
OUT10
OUT1 1
OUT12
GND
CSRl
GND
OUT13
OUT14
OUT15
GND
REQ A
GND
OUT02
GND
OUT02
GND
OPEN

Name

4-206

OPEN
GN.D
IN00
GND
INIT H
GND
INIT H
GND
IN01
IN04
GND
IN05
OPEN
IN06
GND
IN07
IN03
GND
IN08
IN09
GND
IN10
IN11
IN12
GND
REQ B
GND
IN13
IN14
IN15
GND
CSRO
GND
IN02
OPEN
IN02
OPEN
DATA
TRANS.
OPEN
OPEN

vv
uu
TT
ss
RR
PP
NN
MM
LL
KK
JJ
HH
FF
EE
DD
cc
BB
AA
Z
Y
X
W
V
U
T
S
R
P
N
M
L
K
J
H
F
E
D
C

Name

Connector No. 2 Connector No. 1

A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
AA
BB
cc
DD
EE
FF
HH
JJ
KK
LL
MM
NN
PP
RR
ss
l-r

u2
Ul
v2
Vl
T2
Tl
T2
Tl
s2
Sl
R2
Rl
P2
Pl
N2
Nl
M2
Ml
L2
Ll
K2
Kl
52
Jl
H2
Hl
F2
Fl
E2
El
D2
Dl
c2
Cl
82
Bl
A2
Al

Berg
Board Header

B
A

p”pA
NN
MM
LL
KK
JJ
HH
FF
EE
DD
cc
BB
AA
Z
Y
X
W
V
U
T
S
R
P
N
M
L
K
J
H
F
E
D
C

W
uu
T-r
ss

IN09
IN08
GND
IN03
IN07
GND
IN06
OPEN
IN05
GND
IN04
IN01

OUT08
OUT09
GND
OUT10
OUT1 1
OUT12
GND
CSRl
GND
OUT13
OUT14
OUT15
GND
REQ A

W
X
Y
Z
AA
BB
cc
DD
EE
FF
HH
JJ
KK
LL

black
wh-vio
black
red
brown
yellow
black
blue
brown
orange
brown
blue
black
yellow

black/ red
brown/yellow
black/ blue
brown/orange
brown/ blue
black/yellow
bro;lrn/violet

Ul
u2

S
T

black
wh-blu

black/white-blue

4-207

MM
NN

N
R

brown
red

brown/ red

brown
‘violet

M
P

brown
green

brown/green

GND
GUT02

OUT03
GND

GND
0 UT07

OUT05
OUT06

GND
INIT

IN10
GND

IN12
IN11

REQ B
GND

IN14
GND

IN15
IN13

CSRO
GND

OUT01
OUT04
K
L

black
wh-grn

black/white-green

GND
INIT

IN02
GND

IN02
OPEN
OPEN
GND

OPEN
OPEN

H
J

E
F

black
wh-red

black
wh-gry

black/white-violet

DATA TRANS.
OPEN

U
V

OUT00
OPEN

OPEN
OPEN

Connector
No. 2

black
orange

C
D

black
wh-yel

OPEN
OPEN

Connector
No. 1

black/orange

A
B

black
wh-org

Color

black/white-red

black/white-grey

black/white-yellow

black/white-orange

Twisted Pair

BCllK Connections

DRll-C

Al
A2
Al
A2
Bl
82
Cl
c2
Dl
D2
El
E2
Fl
F2
Hl
H2
Jl
J2
Kl
K2
Ll
L2
Ml
M2
Nl
N2
Pl
P2
Rl
R2
Sl
s2
Tl
T2
Tl
T2
Vl
v2

Berg
Header Board

M971

DRll-C

1.5A at +5V
(no current needed at -15V)

Input Current:

TTL levels capable of driving 8 unit loads except for the
following:

outputs:

4-208

INiT (initialize) = common signal on both connectors
driven by one 30-unit load driver

DATA TRANSMITTED = 30 unit loads

NEW DATA READY = 30 unit loads

One standard TX unit load; diode protection clamps to
ground and +5V

Inputs:

Miscellaneous:

1 SPC slot
quad module

Mechanical
Mounting:
Size:

Priority level:
Bus loading:

floating (see Appendix A) (2 needed for
each DRl I-C)
BR5 (may be changed)
1 bus load

767 760 to 767 764
767 750 to 767 754
WC)
WC)

2nd DRll-C
3rd DRll-C
4th DRll-C

UNIBUS Interface
Interrupt vector addresses:

767 770
767 772
767 774

GND
GND
NEWDATA RDY OPEN

GND
IN00

logic 1 =+3v
logic 0 = 0 V

uu
vv

GND
OPEN

GND
INIT

Input/output levels:
(user interface)

pink
wh-red

pink/white-red

ss
-l-r

GND
OUT02

Priority interrupt interface control

black
green

black/green

PP
RR

SPECIFICATIONS
Usage:

black
violet

black/violet

DRll-C

4-209

A MAINT cable (supplied with basic system) jumpers
the DROUTBUF outputs to the DRINBUF inputs and
forces bits 15 and 7 to read as CSRl and CSRO, respectively.

16-bit word from the UNIBUS. Either a full word or an
8-bit byte (either high or low) may be loaded from the
bus.

Data Outputs:

Maintenance
Mode:

16-bit word from the external device

INIT (initialize) - c o m m o n signal on both connectors
driven by one 30-unit load driver

DATA TRANSMITTED-drives 30 unit loads, positive
pulse, 400-ns wide unless width changed by an external
capacitor

NEW DATA READY-drives 30 units, positive pulse,
400~ns wide unless width changed by an external capacitor

Data Inputs:

Signals:

DRll-C

i
Parts List for Interface
I.C. rdumber

Reference
Number in
Circuit

Price

SfJ7404
SN740Q
SN7402
Sl\r7402
SN7474
SN74123
SlJ74123
SN74193
SiJ74164
DM8820
DM8820
DM8830
DA8830
SN74193
SN74152
SN7402
SN7400
Magnecraft W107-DIP-1 Relay

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

.70
. 55
.55
. 55
. r;d
2.4rj
2.4;)
3.3;
cJ . 5 5j.i;9
3.63
3. c!9
3.1>9
3.30
7.ti0
.55
.55
4.OF

Connectors
Jl
DEC H-d56
52
DEC H-d56
INP Conn. r\mphenol 48-10R-18-31s
Resistors

(all l/4 Watt 58, $.06 ea.)
1
8
1
16
3
1
1
4

39 ohm
100 ohm
120 ohm
180 ohm
1K ohm
3.313 ohm
10K ohm
22K ohm

1
4
18
1
1

1502 mfd mylar
i00 pf mica
.01 mfd. ceramic
5 mfd tantalum
10 mfd. tantalum

.13 ea

2
19

3.6V .5 Watt zeners
lN4148

lid5227B

Capacitors
. 25 ea.

3"rr
-AL'
2.34
:52$3 4

.a0 ea.
.25 ea.

1.60
4.75

Diodes

Circuit Board
Douglass Electronics

ll-DE-11

Total
(excludes labor, connecting wire, solder, etc.)
1976 Catalog prices
4D

24.75
$16--