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EK-T3TM8-MM-001

April 1976

323 pages

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Document:	TS03-TM8-E DECmagtape System Maintenance Manual Apr76
Order Number:	EK-T3TM8-MM
Revision:	001
Pages:	323
Original Filename:	EK-T3TM8-MM-001_TS03-TM8-E_DECmagtape_System_Maintenance_Manual_Apr76.pdf

OCR Text

TS03/TMS-E
DECmagtape system
maintenance manual

EK-T3TM8-MM-OOI

digital equipment corporation • maynard, massachusetts

] st Edition, Apri11976

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon·
sibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL's DECset·8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem·l0
DECSYSTEM·20

DECtape
DECUS
DIGITAL
MASSBUS

PDP
RSTS
rYPESET·8
TYPESET·II
UNIBUS
4/76 - 26

CONTENTS
PART I

SYSTEM INFORMATION
Page

CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.4
1.5
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.7

INTRODUCTION . . . . . . . . . . . . . . . . . . . . .
SYSTEM CONFIGURATION . . . . . . . . . . . . . . .
TM8-M FUNCTIONAL BLOCK DIAGRAM DESCRIPTION
APPLICABLE DOCUMENTS . . . . . . . . . . . . . .
MAGNETIC TAPE FUNDAMENTALS - DEFINITIONS
RECORDING METHODS AND DECmagtape FORMATS
NRZI Recording Method . . . . . . . . . .
Tape Format . . . . . . . . . . . . . . . . . . . . .
Cyclic Redundancy Check (CRC) Characters
.... .
Longitudinal Redundancy Check (LRC) Character
Data Files . . . . .
Track AsSignments .
SPECIFICATIONS

CHAPTER 2

INSTALLATION

2.1
2.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.3
2.4
2.4.1
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.3
2.4.4
2.5

SITE PLANNING AND CONSIDERATIONS
Space Requirements . . . . .
Power Requirements . . . . . .
Environmental Requirements
UNPACKING . . . . . . . . . . . .
Cabinet Unpacking Instructions
Device Unpacking Instructions .
INSPECTION . . . . . . . . . . . .
INSTALLATION
....... .
Cabinet Installation
Device Installation . . . . . . . . . . . . . . .
TS03 Mounting Instructions . . . . . . .
TM8-E Controller Mounting Instructions ' ..
H720 Power Supply Mounting Instructions
I/O Signal Cable Connections
. . . . . .
Power Connections .
. . . . . .
ACCEPTANCE TESTING . . . .
. . . . . .

CHAPTER 3

SYSTEM OPERATING INSTRUCTIONS

3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5

SCOPE . . . . . . . . . . . . . . .
CONTROLS AND INDICATORS
OPERA TING PROCEDURES .. .
Tape Threading . . . . . . . . . . .
Tape Loading . . . . . . . . . . . . . .
Placing Tape Unit On-Line . . . . . . . .
Tape Unloading and Rewind .
Power Shutdown .. . . . . . . . . . . . . .

iii

1-1
1-1
1-3
1-6
1-7
1-8
1-9
1-9
1-11
1-12
1-12
1-12
1-13

2-1
2-1
2-1
2-1
2-1
2-1
2-2
2-3
2-3
2-3
2-3
2-3
24
2-5
2-5
. 2-10
. 2-11

. . . . '.

3-1
3-1
3-1
3-1
3-1

3-3
3-3
. . . . . ..

3-3

CONTENTS (Cont )

CHAPTER 4

CUSTOMER EQUIPMENT CARE AND OPERA TlON

4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3

SCOPE . . . . . . . . . . . .
REQUIREMENTS . . . . . . . . . .
CARE OF MAGNETIC TAPE .. ..
CARE OF TS03 TAPE TRANSPORT
General . . . . . . . .
Preventive Maintenance
Materials Required

CHAPTER 5

SYSTEM MAINTENANCE

5.1
5.2
5.3
5.3.1
5.3.2
5.4
5.5
5.5.1
5.5.2
5.5.2.1
5.5.2.2
5.5.3
5.5.3.1
5.5.3.2
5.5.3.3
5.5.3.4
5.5.3.5
5.5.3.6
5.5.3.7
5.5.3.8
5.5.3.9
5.5.3.10
5.5.3.11
5.5.3.12
5.5.3.13
5.5.3.14
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.7
5.7.1
5.7.2
5.7.3

SCOPE . . . . . . . . . .
MAINTENANCE PHILOSOPHY
TEST EQUIPMENT . . . . .
Standard Test Equipment
Special Test Equipment
PREVENTIVE MAINTENANCE
ADJUSTMENTS
General . . . . . . . . . .
Test Box . . . . . . . . .
Functions of Test Box
Test Box Operation
Adjustment Procedures
Voltage Check
Tape Path Alignment
Capstan Creep Adjustment
Mag Pot Adjustment ..
Write Lock Adjustment
Head Shield Adjustment
Tape Cleaner Adjustment
Capstan Perpendicularity Adjustment
Photo Sensor Adjustment
Tape Speed Adjustment
Read Skew Adjustment
Read Level Adjustment
Write Skew Adjustment
Ramp Time Adjustments
CORRECTIVE MAINTENANCE
TM8-M Diagnostics . . . . . .
Corrective Action Flow Diagram
Functional Block Diagram . . .
TM8-E Controller Troubleshooting Hints
TS03 Transport Troubleshooting Hints
TS03 Transport Troubleshooting Tables
Troubleshooting Procedure
PARTS REPLACEMENT . . . . . .
Roller Guide Replacement .. .
Tape Tension Arm Replacement
Reel Motor or Belt Replacement

-t-l
4-\

4-2
4-'1
4·2

4·2
4·2

5·1
5·1
5·1
5·1
5·2
5-2
5·3
5·3
5·3
5·3
54
5·7
5·7
5·9
5-14
5-15
5·17
· 5·18
· 5-19
· 5·19
· 5-20
5-21
5-21
5-24
5-24
5·26
5-27
· 5-27
5·27
5-27
5·27
5·27
5-27
5-27
5·34
5·34
5·34
5·34

CONTENTS (Cont)
Page
5.7.4
5.7.5
5.7.6
5.7.7
5.7.8
5.7.9

Capstan Motor Replacement
Supply Hub Replacement
Magnetic Head Replacement
Photosensor Replacement
Magpot Replacement ...
Tape Cleaner Replacement

· 5-34
· 5-35
· 5-36
· 5-36
· 5-36
· 5-37

APPENDIX A

TM8-E/TS03 CONTROL TEST, PART 1

APPENDIX B

TM8-E/TS03 CONTROL TEST, PART 2

APPENDIX C

TM8-E/TS03 DATA RELIABILITY, 9-TRACK

APPENDIX D

TM8-E/TS03 DRIVE FUNCTION TIMER

APPENDIX E

TM8-E/TS03 UTILITY DRIVER

ILLUSTRA TIONS
Figure No.
1-1
1-2
1-3
14
1-5
1-6
1-7
1-8
2-1
2-2
2-3

24
2-5
2-6
2-7
2-8
2-9
2-10
3-1
3-2
4-1
5-1
5-2
5-3

54
5-5

Title
TM8-M System Configuration
. . . . . . . . . .
TS03-M Master Tape Transport with M8920 Adapter Module
........ .
TM8-E Controller
TM8-M Functional Block Diagram . . . . . . . . . . . . .
Reference Edge of Tape . . . . . . . . . . . . . . . . .
Track-Bit Weight Relationship for Nine-Channel Transport
Data Recording Scheme . . . . . . .
Tape Format . . . . . . . . . . . . .
Space and Service Clearance, Top View
Cabinet Installation . . . . . . . . .
.... .
TM8-E Module Orientation
Paddle Board Jumpers on Side 2 of Cable Assembly 7011571 .
TM8-E Controller Cabling . . . . .
. . . . .
7011571 Cable Assembly
M8920 Cabling to TM8-E
Securing TM8-M Cables
I/O Cable Connection Diagram
Power Connection Diagram
Tape Threading Diagram
Controls and Indicators
Opening Head Shield
TS03 Test Box . . . .
Test Box Installation .
TS03 Adjustment Flowchart
Plug-In Modules and Test Point Locations
TS03 Tape Transport, Rear View

Page
1-1
1-2
1-3
14
1-7
1-7
1-9
1-10
2-2

24
2-5
2-6
2-7
2-7
2-8
2-9
2-9
· 2-10
3-1
3-2
4-3

54
5-5
5-6
5-8
5-9

ILLUSTRAnONS (Cont)
Figure No.
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25

TItle

Page

Head Assembly with Tape Guides
. . . . . . . . . . .
. . 5-10
Roller Guide/Tape Tension Arm Connection, Bottom View ..
· 5-11
Use of Alignment Tool . . .
. . . . . . . . .
· 5-12
Tape Path Alignment . . . . . . . . . . . . . . . . . . . .
· 5-13
Servo Pre-Amp, Card No. 13 . . . . . . . . . . . . . . . . . . . . . . . . .
· 5-15
Mag Pot Position Sensor Assembly, Plastic Cover Removed
· 5-16
Supply Reel, Side View
. . . . . . . . . . .
· .. 5-17
Head Shield Adjustment . . . . . .
. . . . . .
· 5-18
Tape Oeaner Adjustment: . . .
. .... .
· 5-19
Capstan Perpendicularity Check
.... .
. . 5-20
Capstan Motor Mounting Screws
. . . . . . . .
· 5-20
Tape Speed and Read Pre-Amp Adjustment
....... .
· 5-22
Skew Error (Caused by non-perpendicularity of head assembly to reference edge of tape) · 5-23
Location of Skew Adjustment . . . . . . . . . . . . . . .
.. . . . .
· 5-23
Read Skew Adjustment Waveform . . . . . . . . . . . . .
. . . . . .
· 5-24
Skew Error (Caused by misalignment of Read/Write heads)
..... .
· 5-25
Write Skew Adjustment . . . . . . . .
· 5-26
Ramp Time Adjustments . . . . . . . . .
· 5-26
TM8-M Corrective Action Flow Diagram
· 5-28
Reel Hub Adjustment . . . . . . . . . .
· 5-35

TABLES
Table No.

1-2
1-3
1-4
2-1
2-2
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7

Title

Page

Applicable Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6
Five-Character Record . . . . . . . . '. . . . . . .
1-11
CRCC In Register When Writing . . . . . . . . . . .
1-11
T503 Track Assignments for Data and Parity
1-12
7010570 Cable Connections . . . . . . . . . . . . .
· 2-10
Power Harness Color Coding . . . . . . . . . . . . . . . . . .
· 2-11
Customer Equipment Care Operations . . . . . . . . . . . . . .
4-3
Standard Test Equipment Required
. . . . . . . .
5-2
Diagnostic Descriptions . . . . .
. ......... .
5-2
Special Test Equipment and Tools . . . . . . . . .
5-3
TM8-M Diagnostics . . . . . . . . . . . . . . . . . .
. . . . '. 5-27
TS03 DECmagtape Transport Troubleshooting Hints
· .. 5-29
High Error Rate Troubleshooting
· 5-31
Control Malfunctions Troubleshooting . . . . . . . . . .
· .. 5-32

CONTENTS
PART II

TM8-E CONTROLLER
Page

CHAPTER 6

INTRODUCTION

6.1
6.2

GENERAL DESCRIPTION
PHYSICAL DESCRIPTION

CHAPTER 7

BLOCK DIAGRAM DESCRIPTION

7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.3.2
7.3.2.1
7.3.3
7.3.4
7.3.5
7.4
7.4.1
7.4.2
7.4.3
7.4.5
7.4.6
7.5
7.5.1
7.5.2
7.5.3

INTRODUCTION . . . . . . . . .
M8321 OUTPUT CONTROL MODULE
lOT Instruction Decoder
Function Decoder . . . . . . . .
Gating Logic . . . . . . . . . . . .
Read/Compare Error Detection Logic
Skip Logic . . . . . . . . . .
M8327 REGISTERS MODULE
Multiplexer and Data Register
Command Register ., - . . .
Buffered Command Register (BCM)
Function Register
. . . . . . . .
Current Address Register . . . . . . . . .
Word Count Register . . . . . . . . . . . . . . . . .
M8323 TRANSPORT STATUS AND CONTROL MODULE
Main Status Register .
Second Status Register . .
Error Flag . . . . . . . .
lllegal Function Detection
PRESET and SET Pulse Genera tor '"
Control Busy (CNTL BSY) . . . . . . .
M8322 CONTROL AND DATA BREAK MODULE
Data Break Control Logic
Function Decoder
Interrupt Logic . . . . .

CHAPTER 8

PROGRAMMING INFORMATION

8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.1 0

INTRODUCTION . . . . . . . . . . . . . . . . . . . . .
INSTRUCTIONS AND REGISTER BITS
SING LE CYCLE DATA BREAK
Signal Conventions '"
Write Data ..
Read Data
Read/Compare
Extended Gap
Write End-of-File
Space Forward
Space Reverse
Rewind . . . .
Continuous Operation .

7.4.4

6-1

6-2

vii

7-1
7-1
7-1
7-2
7-2
7-2
7-2
7-2
7-2
7-3
7-3
7-3
7-5
7-5
7-5
7-5
7-5
7-6
7-6

7-7
7-7
7-7
7-7
7-7

7-7

"
8-1
.. 8-1
· . 8-11
· 8-13
· . 8-16
· 8-22
· . . . 8-22
· 8-22
· . 8-22
· . . . 8-22
· . . . 8-23
· 8-23
· . . . 8-23

CONTENTS (Cont)
Page

8.4
8.4.1
8.4.2

PROGRAMMING NOTES AND EXAMPLES
Programming Notes
Programming Examples

CHAPTER 9

DETAILED LOGIC DESCRIPTIONS

9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.1.3
9.4.1.4
9.4.1.5
9.4.1.6
9.4.1.7
9.4.1.8
9.4.1.9
9.4.1.10
9.4.1.11
9.4.1.12
9.4.2
9.4.2.1
9.4.2.2
9.4.2.3
9.4.2.4
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7

INTRODUCTION . . . . . . . . . .
M8321 OUTPUT CONTROL MODULE
Input/Output Instruction Decoder .
C Line Select Logic
TP3 Logic
CLR ALL Logic
AC ENABLE Logic
Skip Logic . . . .
Output Control Function Decoder
Read/Compare Logic .. .
.... .
Write Data Select Logic
M8327 REGISTERS MODULE
Data Buffer Register and Multiplexer
AC Input Gating . . . . . . .
Current Address (CA) Register . . .
Word Count (WC) Register
Function Register . . . . . . . . . .
Command Register . . . . . . . . . .
Buffered Command Register (BCM) .
M8323 TRANSPORT STATUS AND CONTROL MODULE
Main Status Register . . . . . . . . . . . . .
SC-2 Error Flag Logic
megal Function Logic
Data Late Logic . . . . . . .
Record Length Incorrect Logic
Tape Rewinding
End of Tape . . . . . .
Beginning of Tape
Read/Compare Error
Parity Error
File Mark (EOF)
Select Remote .
File Protect
Second Status Register . .
EMA 7 Increment Error
Vertical Parity Error (C VPE)
LRC ERROR
....... .
CRC ERROR
....... .
Main and Second Status Register Multiplexer
Extended Memory Address Increment Logic
Control Busy (CNTL BSY) . . . . .
PRESET and SET Pulse Generator .
Data Late Error Check Logic . . . .

viii

. . . . . . . . . . 8-23
· 8-23

. . . . . . . . . . 8-23

9-1
9-1
9-1

9-1
9-1

9-3
9-3
9-3

9-3
9-5
9-5
9-5
9-5
9-8

9-8
9-9
· 9-11

· 9-12
· 9-13
· 9-13

· 9-13
· 9-13

.. 9-15
. . . 9-16

· 9-17
· 9-17
· 9-17
· 9-17
· 9-17

· 9-17
· 9-17
· 9-17

· 9-17
· 9-20
· 9-20
· 9-20
.9-22
· 9-22
· 9-22
· 9-22
· 9-22
· 9-22
. . . 9-22

CONTENTS (Cont)
Page

9.5
9.5.1
9.5.2
9.5.2.1
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
9.5.10
9.5.11
9.5.12
9.5.13

M8322 CONTROL MODULE
. . . 9-23
Control Function Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
Data Break Request Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
Word Count Overflow Logic . . . . . . . . . . . . . . . . . . . . . . . . •. . . 9-25
Data Break Priority Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Processor Control Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
MITF (JOB DONE) Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
Interrupt Logic . . .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
Change Transport Control Logic . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . 9-29
Change Direction Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
Write Data Ready Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
Read and Write Control Logic . . . . . .
. . . . ... . . . . . . . . . . . . . . 9-30
Data Multiplexer Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
POWER OK Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 9-32
Initialize Logic . . . . . . . . . . . . . . .
.. . . . . . . . . . . . . . . . . . . 9-33

APPENDIXF

TM8-E INTERFACE AND INTERNAL SIGNALS

APPENDIXG

SPARE PARTS

APPENDIXH

IC DESCRIPTIONS

ILLUSTRA nONS
Figure No.
6-1
7-1
7-2
7-3
74
7-5
8-1
8-2
8-3
84
8-5
8-6
8-7
8-8
8-9
8-10
9-1
9-2
9-3
94
9-5

Title

Page

TM8-M Block Diagram . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . ..
6-1
TM8-E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Contents of Command Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-3
Contents of Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Contents of Main Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Contents of Function and Second Status Regist.er . . . . . . . . . . . . . . . . . . . . . . 7-6
LWCR and RWCR Instruction Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
LCAR and RCAR Instruction Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
LCMR and 'RCMR Instruction Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
LFGR and RFSR Instruction Data Flow.
. . . . . . . . . . . . . . . . . . . . . .. 84
LDBR and RDBR Instruction Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
RMSR Instruction Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Single Cycle Data Break Data Transfer Data Flow . . . . . . . . . . . . . . . . . . . . . . 8-12
Single Cycle Data Break Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Core Dump Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' . . . . . . 8-14
TM8-E Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
lOT Decoder Logic . ... . . . . . '.' . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-2
Skip Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Output Control Function Decoder . . . . . . . . . . . . . . . . . . .' . . . . . . . . . .. 94
Read/Compare and Write Data Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Input Data Multiplexer and Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

ILLUSTRATIONS (Cont)
Figure No.
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
F-1

TItle
Data Register and Function Register Output Multiplexer
AC Input Gating and Holding Buffer Register
Current Address and Word Count Registers
Function Register . . . . . . . . .
Command Register and Multiplexer
Erro r Flags . . . . . . . . . . . . .
illegal Function Flag and Control Logic
Data Late and EMA Increment Error Flags
Record Length Incorrect Error Detection Logic
Parity Error Flags
.............. .
Main Status Register and Second Status Register Multiplexer
PRESET and SET Pulse Generation Logic
Data Late Error Check Logic
Control Function Decoder . . . . . . . . .
Data Break Control Logic . . . . . . . .
Priority and Processor Control Logic with 0 (Highest) Priority Installed
.....
MTTF (JOB DONE Flag) and Interrupt Request Logic
Change Transport and Buffered Command Register Control Logic
Change Direction Detection Logic
Write Data Ready Logic
Read and Write Control Logic
Data Multiplexer Control Logic
Initialize and Clear Logic
Omnibus Pin Assignment . . .

Page
· 9-8
.. 9-9
· 9-10
· 9-11
· 9-12
· 9-14
· 9-15
· 9-16
· 9-18
· 9-19
· 9-20
· 9-21
· 9-23
· 9-24
· 9-25
· 9-26
· 9-28
· 9-29
· 9-30
· 9-30
· 9-32
· 9-32
· 9-33
· F-2

TABLES
Table No.
7-1
8-1
8-2
8-3
9-1
9-2
9-3
F-1
F-2
F-3
F4
F-5

F-6
F-7
G-1

Title
Command Register Contents and Function
Function Register Contents and Functions
Main Status Register Contents and Indications
Second Status Register Contents and Functions
C line Select Levels for TM8-E Transfer Operations
Data Multiplexer Selection Levels . . . . . . . . . .
Read and Write Control Logic Signal Levels
M8321 Output Control Module Signals and Interface
TM8-E M8323 Transport Status Control Module Signals and Interface
TM8-E M8321 Output Control Module Edge Connector Signals
TM8-E M8327 Register Module, Edge Connector Signals
..... .
TM8-E M8322 Control Module, Edge Connector Signals . . . . . . .
TM8-E M8323 Transport Status and Control ModUl:;, Edge Connector Signals
TM8-E Signals and Signal Functions
TM8-E Spare Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page
7-8

84
8-8
· 8-10
· 9-3
· 9-5
· 9-31
F-3
F4
F-5
F-6
F-7
F-8
F-9
G-1

CONTENTS
PART III

TS03 DECmagtape TRANSPORT
Page

CHAPTER 10

GENERAL INFORMATION

10.1
10.2
10.3

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
PHYSICAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
ELECTRICAL AND MECHANICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . 10-1

CHAPTER 11

THEORY OF OPEARTION

11.1
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.1.1
11.3.1.2
11.3.1.3
11.3.2
11.3.2.1
11.3.2.2
11.3.2.3
11.3.3
11.3.3.1
11.3.3.2
11.3.4
11.3.4.1
11.3.4.2

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
TRANSPORT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Read Ope!"ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Rewind Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
FUNCTIONAL BLOCK DIAGRAM DESCRIPTION
. . . . . . . . . . . . . . . . . . . . 114
Adapter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Control Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Write Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Read Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Transport Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Transport Control Logic Operation During a Write Sequence . . . . . . . . . 11-19
Test Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Servo System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Reel Servos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Capstan Servo . . . . . . . ~ . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
Data Section . . . . . . . . . . . r • • • • • • • • • • • • • • • • • • • • • • • • • 11-22
Write Electronics .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
Read Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25

CHAPTER 12

DETAILED LOGIC DESCRIPTIONS

12.1
12.2
12.3
12.3.1
12.3.2
12.3.2.1
12.3.2.2
12.3.3
12.3.4
12.3.4.1
12.3.4.2
12.3.5
12.3.5.1
12.3.5.2
12.4
12.4.1
12.4.2

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
NOTES TO TRANSPORT SCHEMATIC DIAGRAMS . . . . . . . . . . . . . . . . . . . . 12-1
TYPE M8920 ADAPTER CIRCUIT DESCRIPTION . . . . . . . . . . . .. . . . . . . . . 12-2
Clock Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Read/Write Control Logic (ROM/Delay Counter) . . . . . . . . . . . . . . . . . . . 12-2
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Rewind Off-Line Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Shutdown Logic (Engineering Drawing 09) . . . . . . . . . . . . . . . . . . . . . . 124
Write Strobe 'Generation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Write Data Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
Write File Mark Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
Record and File Mark Detection Logic . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
File Mark Record Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
Data Record Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
TS03 POWER SUPPLY CIRCmT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 12-6
Primary Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Secondary Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6

CONTENTS (Cont)

Page
12.4.3
12.4.4
12.4.5
12.4.6
12.5
12.5.1
12.5.2
12.5.3
12.5.4
12.5.5
12.6
12.6.1
12.6.2
12.6.3
12.6.4
12.7
12.8
12.8.1
12.8.2
12.8.3
12.9
12.9.1
12.9.2
12.10
12.11
12.12
12.12.1
12.12.2
12.12.3
12.12.4
12.12.5
12.12.6
12.12.7
12.12.8
12.13
12.13.1,
12.13.2
12.13.3
12.14
12.15

+10 Volt Regulator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
±10 Volt RegulatOl
+5 Volt Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Short-Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
TYPE 3842 CONTROL INTERFACE MODULE CIRCUIT DESCRIPTION (TD9) . . . . . 12-7
Tape Motion Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Write Select
Rewind Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
End-of-Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Output Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
TYPE 3843 PUSHBUTTON CONTROL MODULE CIRCUIT DESCRIPTION (T07,8) . . . 12-8
Front Panel Pushbutton Controls
. . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
Write Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
Test Panel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
TYPE 3645 RAMP GENERATOR MODULE CIRCUIT DESCRIPTION (TD5) . . . . . . 12-10
TYPE 3844 SENSOR AMPLIFIER/DRNER MODULE CIRCUIT DESCRIPTION (TD6)
12-10
BOT, EOT, and TAPE THREADED Sensor Amplifiers . . . . . . . . . . . . . . . 12-11
File Protect Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Write, Erase Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
TYPE 4306 SERVO PREAMPLIFIER MODULE CIRCUIT DESCRIPTION (T03,4) . . . 12-12
Ca pstan Servo Amplifier Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Reel Servo Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
TYPE 3631 READ PREAMPLIFIER CARD CIRCUIT DESCRIPTION (T010) . . . . . . 12-12
TYPE 4218 MAGPOT TENSION ARM POSITION SENSOR CIRCUIT
DESCRIPTION (TD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
TYPE 4845 DELAY TIMING MODULE CIRCUIT DESCRIPTION (T012) . . . . . . . . 12-14
Crystal Oscillator Divider
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
Skew Gate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
Skew Lamp
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
Blank Space Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
Read Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-15
Data Lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
TYPE 3848 FOUR-CHANNEL WRITE AMPLIFIER MODULE CIRCUIT
DESCRIPTION (TD13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
Write Data Strobe Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
Write Amplifier Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
Write Amplifier Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
TYPE 4178 QUAD READ AMPLIFIER MODULE CIRCUIT DESCRIPTION (T010,11) . 12-16
TYPE 4179 READ AMPLIFIER/CLIPPING CONTROL MODULE CIRCUIT
DESCRIPTION (TD10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17

CHAPTER 13

PARTS IDENTIFICATION

APPENDIX I

TRANSPORT SIGNAL DESCRIPTIONS AND INTERFACE INFORMATION

1.1
1.1.1

INPUT SIGNALS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Setup Commands

xii

1-1
1-1

Page
1.1.2
1.1.3
1.1.4
1.1.5
1.2
1.2.1
1.2.2
1.3

Tape Motion Commands .
Write Cpmmands . . . . .
Read Commands . . . . .
Shutdown Commands
INTERF ACE OUTPUT SIGNALS
Status Outputs . . . . . . .
Read Outputs
...:....
SUMMARY OF INTERFACE CHARACTERISTICS

APPENDIXJ

DEC/VENDOR TS03 TRANSPORT PART NUMBERS

1-1
1-2
1-3
1-3
1-3
1-3
14
1-5

ILLUSTRATIONS
Figure No.
10-1
10-2
11-1
11-2
11-3

114
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
12-1
12-2
13-1
13-2
13-3
1-1

Title
TS03 Transport and TS03 Adapter Module (M8920)
TS03 Transport Physical Dimensions
TS03 Block Diagram . . . . . . . . . . .
Adapter Block Diagram . . . . . . . . .
Control Logic Functional Block Diagram
Commands Processing Sequence Flow Diagram
Control Logic BOT Write Operation Flow Diagram
Write Logic Functional Block Diagram . . . . . . . .
.....
Write Operation Flow and Timing Diagram
Write File Mark Operation Flow and Timing Diagram
Read Logic Functional Block Diagram
Control Logic Block Diagram
. . . . .
Reel Servo System . . . . . . . . . . .
. . . . . .
.... . . .
Write Data Section . . . . . . . . . . .
Typical Write Amplifier Channel (0-7), Fixed Channel P Delay
Skew Characteristics
Read Data Section . . .
Clock Logic Timing
Differential Transfonner
Front Panel Parts Identification
Tape Transport Parts Identification (Top View)
Tape Transport Parts Identification (Rear View)
Summary of Adapter Characteristics . . . . . .

Page
10-3

104
11-2
11-5
11-6
11-8
11-10
11-11
11-14
11-15
11-16
11-18
11-21
11-22
11-23
11-24
11-26
· 12-3
12-13
13-2

134
13-5
1-6

TABLES
Table No.
11-1
11-2
11-3

Title

Page

Operations Versus Commands Required .
Commands and Corresponding Delays ..
Adapter /Transport Interface Signal Names

· 11-7
· 11-8
11-17

xiii

TABLES (Cont)
Page
114
13-1
13-2
13-3
134
13-5
13-6

Transport Status . . . . . . . . . . . . . .
Illustrated Parts Breakdown for Figure 13-1
Dlustrated Parts Breakdown for Figure 13-2
Illustrated Parts Breakdown for Figure 13-3
Replaceable/Spare Parts for Figure 13-1
Replaceable/Spare Parts for Figure 13-2
Replaceable/Spare Parts for Figure 13-3

xiv

11-20
13-3
13-6
13-6
13-7
13-8
13-8

PREFACE

This manual provides a complete description of the TS03/TMS-E DECmagtape System henceforth referred to as
the TMS-M. Included are installation instructions, operation and programming information, functional block
and logic level descriptions, preventive and corrective maintenance procedures, and removal and replacement
procedures. The manual is divided into three parts:
Part I contains a general description of the system, complete system installation instructions and maintenance information including customer care and operation, preventive maintenance, corrective maintenance, and removal and replacement procedures.
Part II contains a complete description of the TMS-E Controller including specifications, programming
information, and functional block, logic level, and flow diagram descriptions.
Part III contains a complete description of the TS03 DECmagtape Transport including specifications,
operation, and functional block, logic level, and flow diagram descriptions.

PART I
SYSTEM INFORMATION

CHAPTER 1 INTRODUCTION
CHAPTER 2 INSTALLATION
CHAPTER 3 SYSTEM OPERATING INSTRUCTIONS
CHAPTER 4 CUSTOMER EQUIPMENT CARE AND OPERATION
CHAPTER 5 SYSTEM MAINTENANCE

APPENDIX A

CONTROL TEST, PART 1

APPENDIX B CONTROL TEST, PART 2
APPENDIX C

DATA RELIABILITY, 9-TRACK

APPENDIX D

DRIVE FUNCTION TIMER

APPENDIX E

UTILITY DRIVER

7461·10

TM8-M DEC magtape System

Part I

CHAPTER 1
INTRODUCTION

1.1 INTRODUCTION
The TMS-MA/MB* DECmagtape System is a magnetic tape storage system that interfaces with the PDP-Sf A, E,
F and M family of proces.;ors and peripherals and provides storage for digital information. The system reads and
records digital data in parallel in a nine-channel, industry-compatible format.
1.2 SYSTEM CONFIGURATION
The TMS-M DECmagtape System is composed of the units shown in Figures 1-1, 1-2, 1-3 and 1-4, and listed
below.
1.

DECmagtape Controller - The TMS-E interfaces the DECmagtape system to the PDP-S Omnibus.
The controller consists of four modules which plug into the Omnibus. It controls data transfers, issues
control commands to the TS03 master, and monitors system operation. Each TMS-E can control two
TS03 transports: a master and a slave.

--..
WRITE

DATA

WRITE STROBE

)

II'"

CONTROL

0
M
N
I
B
U
S

)

...

WRITE

DECMAGTAPE
CONTROLLER
TM8-E

K. REA D DATA

MASTER
DECMAGTAPE
TRANSPORT
TS03-MA/MB

STATUS

DATA

.,)

COMMANDS
READ STROBE

...

SLAVE
DEC MAGTAPE
TRANSP.ORT
(TS03-SA/SB )

( INCLUDES
M8920
ADAPTER)

READ DATA

STATUS

fAC

foc

fAC

DC
'0lIl

POWER SUPPLY
(H720-E/F)

PRIMARY AC POWER

08-1668

Figure I-I TM8-M System Configuration

*The TM8-M System is commonly referred to by its component sub-units - the TS03 and the TM8-E, hence the manual title "TS03/TM8-E
DECmagtape System Maintenance ManuaL" However, within this manual the system will be referred to as the TM8-M_ The TM8-MA is a
115 V, 60 Hz system. The TM8-MB is a 230 V, 50 Hz system.

1-1

Part I
TS03

MASTER TAPE
TRANSPORT

M8920
ADAPTER
MODULE

7461-2

Figure 1-2 TS03-M Master Tape Transport with
M8920 Adapter Module

Master DECmagtape Transport - The TS03-M consists of an M8920 adapter module and a TS03
tape transport. The M8920 processes commands from the controller and issues motion and
read/write commands to the master and slave transports; the M8920 also monitors status lines from
the master and slave transports. Any status changes at the selected transport are reported immediately to the controller. In response to inputs from the adapter, the tape transport controls tape motion
and records and reads data on magnetic tape. Two models of the master DECmagtape transport are
available: the TS03-MA, which requires 115 V, 60 Hz primary power and the TS03-MB, which
requires 230 V, 50 Hz primary power. Both m'odels also require +5 :!: 5% V at 3 A and an AC LO
signal.
1-2

Part I

M8321

M8327

M8322

M8323

7724-&

Figure 1-3 TM8-E Controller

Slave DECmagtape Transport - The TS03-S consists of a tape transport only. In response to inputs
from the master transport adapter, it controls tape motion and records and reads data on magnetic
tape. The TS03-SA requires 115 V, 60 Hz primary power and the TS03-SB requires 230 V, 50 Hz
primary power.

Power Supply - the H720 provides switched ac and dc operating power for the TMS-M system. Two
models of the power supply are available: the H720-E, which requires 115 V primary power and the
H720-F, which requires 230 V primary power.

1.3 TMS-M FUNCTIONAL BLOCK DIAGRAM DESCRIPTION (Figure 1-4)
The TMS-E Controller interfaces the PDP-S with the TS03-M Tape Transport. Bits MOO to MD 11 are transferred from the Omnibus to the data mux and register. In the Write 9-Channel Mode the output from the
mux/register is DB4 to DB 11, which passes through the data select logic and becomes WOO to WD7. In the write
Core - Dump Mode the data mux and register outputs data in two cycles: DBO to DB5 in the first cycle and
DB6 to DBII in the second cycle. The data select logic outputs two 6-bit data cycles using channels WOO to
WD5. Channels WD6 and WD7 are not used in the Core Dump Mode.
1-3

Part I

DATA
BuS
GATING

r-J-ATA 0-11

",-

8327

DATA
BUFFER
REGISTER
8327

t-- LWCR

DBC 1/2

I---- LCAR

t-- LCMR
lIO
INSTRUCTION
DECODER

f-+ LFGR
f-+ RCMR
I-- RWCR

[

READ/
COMPARE
LOGIC
8321

MPXOMPX 11

RIC
ERROR

f-+ RCAR

t-- RCMR
8321 t-- RMSR

DATA MU)(
AND
DATA REGISTER

~-------------4~~b

MPX AlB

8327

~-------~~~d

'-----....-----'

I---'----'----...J

I~~l'

(%/0

MOO - MOll

WFMK

MD 3-8

M
N

B
S

LFGR

AC ENABLEl

I,i/i/?;:tl//;/'ii;//,II/'

832;1

BAC 0-6

FUNCTION
REGISTER

IFRo-2

v ........._ _--=-.::.=..:..J
8327r

BACO-BAC"

AC
GATING

WXG
READ/WRITE

OUTPUT
CONTROL
FUNCTION
DECODER

RWD
MPX AlB

8321
LWCR

8327 ,H BACO-l1

READ/WRITE
WCOv

COUNT wC

•

~_ _~8~3~2~2~

WORD COUNT
REGISTER
WC 0~11

r::~~:l~~~~~;L~E~•

...

8327

DATA B R E A K h
REQUEST LDGIC

PRIORITY
LOGI C
MAC 1/2
8322

1 PEVN

BSELO-2

GATE

MAC 1

COMMAND
REGISTER
8327

-v

U ~DATA
0-6

MUX

~~~~~~~
REGISTER
8327

~
~A O N

~~i~--~-~

...
v

~__~8~32~7~

GATE
8327

8327

EOT IBOT IEOF/R EW/W RL

r-~----L-~V~P~E~R~R~~r---------~
l- ____~

LCAR

•

MAC 1 1

GATE

MISCEL ERRORS.

fRWC;/

COUNT CA

RCMR

STATUS
REGISTERS

8323

~3271

RFSR

CRC ERR
LRC ERR
PARITY ERR

PARITY
ERROR
FLAGS

l-.

/(0

8323 l-.

"
STATUS-~0
'-

MAO-MAll
DATA 0 - OAT

EMAO- EMA2 EMA7
INIT

~------...J-~-----~D~A~T~A~O~-~l'~-----~1

I
I
I
I

I
I
I

~-----------------------------------------------------------------------------------TM8-E ------------------------------------------------------------------~
08 -1514

Figure 1-4 TM8-M Functional Block Diagram
(Sheet 1 of 2)

1-4

STATUS

DTL,TTL LOGIC
XPRT RDY

OP AMPS

RWNDG

DC MOTORS

END OF TAPE
EDT

LOAD POINT

BOT

WRLCK

+,-10 :UOp~EL~
+,-24

110/220/230
TD2

POWER

* M8920 output jocks J 2, J4 and J6 connect
to J2, J3 and J 1 respectively on the
second tope drive (il used)

WRL

M8920--------------------------------------------~I··-------------------------------

TS03S--------------------------------------~·1

NOTE: Lettering on connectors C and D are connecting points to other half of this illustration.
They do not represent connector pin lettering.

OB-1515

Figure 1-4 TM8-M Functional Block Diagram
(Sheet 2 of 2)

1-5

Part I
Write data lines WDO to WD7 are fed into the MS920 adapter where parity and CRC are generated. The write
logic amplifies the eight data channels plus the parity channel (six data channels plus parity in Core Dump
Mode) and drives the transport write heads. Write (REC) pulses and LRC pulses are obtained from the write
strobe generator in the MS920 adapter.
The read logic receives data from the read heads and sends it to the MS920 adapter where the data is checked for
LRC, CRC and vertical parity errors. Any such errors will raise error flags in the TMS-E and set appropriate
error bits in the status register. The contents of the status register are sent to the processor via the Data Bus. In
addition, the data bits are monitored for tape marks which signify an end-of-file condition.
In the Read 9-Channel Mode of operation, read channels RDO to RD7 carry eight data bits and RDP carries a
parity bit into the data mux and register in the TMS-E. From there, the bits are sent to the data lines of the
Omnibus via the data bus gating logic. In the Read Core - Dump Mode, data is read from the tape in two cycles.
During the first cycle, RDO to RD5 carry six bits to the data register where they are held until the second cycle.
During the second cycle, six more bits are added to the first cycle bits in the data register which then outputs 12
bits over the data lines to the Omnibus.
Detailed operation of the TMS-E and the TS03-M is given in Parts II and III of this manual. Figure 1-4 can be
used along with the detailed illustrations contained therein.

1.4 APPLICABLE DOCUMENTS
Table 1-1 lists PDP-S documents that are applicable to the TMS-M DECmagtape System.

Table 1-1
Applicable Documents
Description

Title

Number

H720 Power Supply and
Mounting Box Manual

EK-H720-TM..Q03

A theory manual that provides a functional and detailed
circuit description of the H720 Power Supply.

PDP-8 Processor and
Systems Manuals.

A series of maintenance and theory manuals that provide
a detailed description of the basic PDP-8 System.

PDP-8 Processor
Handbook

A general handbook that discusses system architecture,
addressing modes, the instruction set, programming
techniques, and software.

PDP-8jE, F, M
External Bus Options;
Maintenance Manual
Volume 3

DEC-8E-HMM3A-C-D

A handbook devoted to a discussion of the various
peripherals used with PDP-8 systems. It also provides
detailed theory, flow, and logic descriptions of the
Omnibu~ and external device logic; methods of interface
construction; and examples of typical interfaces.

PDP-8jA Miniprocessor

EK-BA002-MM..QOI

Contains the necessary information to operate, interface
to, maintain and troubleshoot the PDP-8j A.

Users Manual

*Applicable manuals are furnished with the system at time of installation. The document number depends upon the specific PDP-8
family processor.
tUse the processor handbook unique to the actual CPU.

1-6

Part I

I.S

MAGNETIC TAPE FUNDAMENTALS - DEFINITIONS

Reference Edge - The edge of the tape as defined by Figure 1-5. For tape loaded on a TS03, the
reference edge is toward the observer.

TAPE
LEADER

OXIDE
SURFACE

~~--- SUPPLY

REEL
10-1265

Figure 1-5 Reference Edge of Tape
2.

BOT (Beginning-of-Tape) Marker - A reflective strip placed on the nonoxide side of the tape, against
the reference edge, 15 ft (±l ft) (457 cm, ±30.5 cm) from the beginning of the tape.

EaT (End-of-Tape) Marker - A reflective strip placed on the nonoxide side of the tape, against the
nonreference edge, 25 to 30 ft (762 to 914 cm) from the trailing edge of the tape.

9-Channel Recording - Eight tracks of data plus one track of vertical parity. Figure 1-6 shows the
relationship between track and bit weight for a 9-channel transport.·

BIT WT TRACK

22 - 1 -

RD 7

20 - 2 -

RD 6

24 - 3 -

RD 5

P -4-

RD 4

25 -5-

RD 3

26 - 6 -

RD 2

27_7-

RD 1

2 1-8-

RD 0

23 - 9 -

RD P
READ HEAD
11-3091

Figure 1-6 Track-Bit Weight Relationship for
Nine-Channel Transport
·When the track vs bit channel standard was adopted, the outer tracks were more susceptible to bit dropping errors. Consequently, channels
containing the least I s were assigned the outer locations on the tape.

1-7

Part I
5.

Tape Character - A bit recorded in eelch of the nine channels.

Record - A series of consecutive tape characters. *

File - An undefined number of records (minimum = zero, no maximum).

Interrecord Gap (lRG) - A length of erased tape used to separate records (0.5 in. (1.27 cm) minimum
for 9-track; maximum IRG is 25 ft)(762 cm).

Extended IRG - A length of erased tape (3 in. (7.62 cm) minimum) optionally used to separate
records. It must be used between BOT and the first record.

10.

Tape Speed - The speed at which tape moves past the read/write heads; normally stated in inches per
second.

11.

Tape Density - The density of sequential characters on the tape. It is normally specified in byt~s per
inch (bpi), which is equivalent to characters per inch.

12.

Write Enable Ring - A rubber ring which must be inserted on the supply reel to allow the transport to
write on the particular tape. This safety feature helps prevent accidental destruction of previously
recorded data.

13.

Tape Mark (TM) - A record written on the tape to designate the end of a file; sometimes referred to
as a file mark (FMK). In the TM8-M, the tape mark is always preceded by an extended IRG.

1.6 RECORDING METHODS AND DECmagtape FORMATS
The DECmagtape system is an on-line mass storage system for programs or data. Data is recorded on tape in
vertical rows termed characters. Each character consists of eight data bits and one vertical parity bit. The vertical _
parity bit is program-selected as even or odd. The odd parity bit guarantees that each character records at least
one I-bit.
The parity bit is generated according to the rule that the number of Is in a character (parity bit included) is odd
or even. For example, if odd parity is used and the character contains an even number of 1 bits, the paiity bit is
generated as a 1 bit and an odd number of 1 bits are recorded; then, if an even number of bits are read back from
tape, a vertical parity error is generated to notify the program that the data is in error.
The data characters are recorded in blocks of characters termed records (Figure 1-7). Each record contains a
specified number of characters determined by the word count. The minimum record length is 3 characters; the
minimum word count is the 2's complement of 3 or 7775 8 • If a write operation is attempted for a record with less
than 3 characters, the controller's response is undefined (i.e., the operation may be successful or unsuccessful
depending on the data pattern. If the operation is unsuccessful the tape drive will run away and refuse to accept
fu!'ther commands until halted by a clear command.)
Records are separated by interrecord gaps (lRGs). The IRG is 0.5 in. (1.27 cm) minimum (approximately 0.6 in.
(1.5 cm) in normal operation), but may be extended to 3 in. (7.62 cm) by performing an extended gap operation.
Tape IRGs (unrecorded areas) provide areas on the tape for the transport to start or stop and also separate data
records.

*In the TM8-M System a record must be ~3 characters long to be recognized as such.

1-8

Part I
~I.------ FILE -----~·I

FILE MARK :23

FILE MARK: 23 8

r-0.6~

:---APPROX 3.8"---:

DATA PREVIOUS_
RECORD

i---IRG--I-- DATA NEXT
I
RECORD

I--O.6'~

I,,~*+*'
CRL 1

~**--I
FILE tMARK

LRCC

LAST DATA
CHARACTER
OF PREVIOUS
FILE

LRCC

FIRST DATA
CHARACTER
OF NEXT
FILE

IIII~*+*~

III

LAST DATA
CHARACTER
OF PREVIOUS
RECORD

'11111

J CR~C i

LACC

IRG

FILE MARK AND GAP FORMAT

LFIRST DATA
CHARACTER
OF NEXT
RECORD

FORMAT

**=*

= 3 CHAR. SPACE
7 CHAR.SPACE
11-3069

Figure 1-7 Data Recording Scheme

1.6.1

NRZI Recording Method

The TS03 employs the NRZI (non-return-to-zero change on one) recording method. In the NRZI method, a 1 bit
is represented by a reversal in the direction of tape magnetization on a track; a 0 bit is represented by no change
in tape magnetization.

1.6.2 Tape Format
The format (Figure 1-8) is composed of from 18* to 2048 nine-bit characters spaced 1/800 in. (3 mm) apart,
followed by 3 character spaces, a CRC character, 3 more spaces and an LRC character. This unit of data is called
a record. At 800 characters per inch, the record is between 1/32 in. (79 mm) (minimum) and 5 in. (12.7 cm)
(maximum). Between each record is a gap of at least 1/2 in.** The tape structure consists of a number of records
followed by a file mark (Figure 1-7). Since data is recorded and read at high speed, IRGs are used to provide
space for starting and stopping the TS03 transports. The TS03 transport accelerates from standstill to full speed
in approximately 0.2 in. (0.5 cm) of tape and decelerates from full speed to standstill in 0.2 in. (0.5 cm) of tape;
thus, the minimum IRG of 0.5 in. (1.27 cm) provides adequate space for starting and stopping the tape transport.
The CRC character (Paragraph 1.6.3) is generated in the TS03 master logic during a write operation and written
at the end of a record. The check character performs the same function to a record as the parity bit does to a
character.

·USt\SCII program standards, not a hardware limit.
**0.5 in. 0.27 em) minimum; 0.6 in. (1.5 em) nominal.

1-9

Part I

REFERENCE EDGE
(FRONT FLANGE
OF REELl

/i
!

LRC

0.005"::';10% (NOTE 3)

CRC 0.005":!' 10%

---,.:.-~I.LOCK

INTERBLOCK GAP_.......
0.50 MIN
(NOTE 2)

WRITE TRACK
0.043" MIN

r - - - - - -

-- - -

LOAD POINT
BEGINING OF
TAPE REFLECTIVE

~~~~~~R~~_~STRIP ON

NONOX IDE (SHINY)
SIDE OF TAPE

END
OF
TAPE

.Ir--I'--+--_ PAR ITY (000)
BEGINING
OF
TAPE

END POINT
END OF TAPE
REFLECTIVE
STRIP ON NONOXIOE
(SHINY) SIDE OF
TAPE
"L - -TAPE
-MOTION
---V

8E- 0500

LEGEND:

NOTES:

B PI
BOT
LRC
CRC

Tape is shown with oxide side up. read/write
head on same side as oxide. Tape shown representing 1 bits in all NRZI recording; 1 bit
produced by reversal of flux polarity. tape
fully saturated in each direction.

Tape to be fully saturated in the erased direction in the interrecord gap and the initial gap.

An LRC bit is written in any track if the longitudinal count in that track is odd. Character
parity is ignored in the LRC character.

CRC - Parity of CRC character is odd if an
even number of data characters are written.
and even if an odd number of characters are
written.

Tape Bits per Inch
Beginning of Tape
Longitudinal Redundancy Check
Cyclic Redundancy Check

Figure 1-8 Tape Format

The LRC is the final character in the record and is generated so that for each track the sum of 1 bits (CRC
character included) is even. The LRC character is written on tape by clearing the write buffer in the tape transport after the CRC character is written. The LRC strobe resets the write buffer, causing a 1 to be written on each
track containing an odd number of Is; a 0 is written on each track containing an even number of Is.

1-10

Part I
1.6.3 Cyclic Redundancy Check (CRC) Characters
The CRC character provides a method of error detection and correction on TS03 DECmagtape Transports. The
code has nine check bits that form a check character at the end of each record. To perform a correction, a record
in which an error has been detected must be reread into memory with the LRC and CRC characters for program
evaluation. Errors involving more than one track can be detected but ilot corrected.
The CRC character is generated as follows:
I.

The CRC register, located in the TS03, is cleared at the beginning of each record. As each data bit is
written on tape, it is exc1usively-ORed with its corresponding bit in the CRC register.

The CRC register is shifted one position to the right after the exclusive-OR operation has taken place.

The bits entering CRC 2, CRC 3, CRC 4, and CRC 5 of the CRe register are inverted if the bit
entering CRCP is a I. Data is shown in Table 1-2; the resultant CRC character is shown in Table 1-3.
Table 1-2
Five-Character Record

Bit

Data
Character 0

Data
Character 2

P
0

0
1

0
,0

0
0

1
1

0
0

1
1

0
1

3
4

Characters
Data
Character 3

Data
Character 4

0
0
0

1
1
1
1

0
0

0
0
0
1

1
1

Character 4

Final
CRC

CRCC
On Tape

1
1
1
1

Data
Character 5

Table 1-3
CRCC In Register When Writing
CRC Register
CRC Bits

CRC
Cleared

CRCP
CRCO
CRC}
CRC2
CRC3
CRC4
CRCS
CRC6
CRC7

0
0
0
0
0
0
0
0
0

Character I

Character 2

Character 3

0
0

0
0
0
0

0
0
0
0
0

0
0

1
1
1

}

0
0
1

0
0
0
0

}

0
0
1

1
1

1-11

1
1

}

0
0
0

}

Part I
4.

Steps 1-3 are repeated for each data character of record.

At CRC time, all positions of the CRC register, except CRC 2 and CRC 4, are complemented and the
resultant CRC character is written on tape.

The CRC register is cleared for the next record.

1.6.4 Longitudinal Redundancy Check (LRC) Character
The LRC character is written three spaces after the CRC character. The vertical.parity bit is always written on
the LRC character; the vertical parity of LRC is never checked. The LRC character makes the longitudinal
parity even for the entire record, including the CRC. The LRC is generated in the TS03 by the LRC register in
the following manner:

The LRC register is cleared at the beginning of a record.

As characters are written on tape, corresponding 1 bits complement the LRC register at the time data
is written on tape.

At LRC time, the LRC strobe clears the write buffer and Is are written on tape in only those channels
for which the write buffer is set prior to clearing.

Following this method, the LRC character forces an even number of bits to be recorded on each track
of the tape. The CRC character is included in determining the LRC character.

1.6.5 Data Files
As previously stated, a record is a group of characters preceded by an IRG and terminated by three spaces, a
CRC character, three more spaces and an LRC character. A file is a group of records separated by IRGs and
terminated by a 3 in. (7.62 cm) gap followed by a file mark. The file mark is a record consisting of a single data
character [the end-of-file (EOF) character] followed by seven blank characters and an LRC character. The CRC
character is not written on an EOF record. The LRC character with a file mark is a duplicate of the EOF
character (23 8).
1.6.6 Track Assignments
The track assignments for read, write, and parity bits are shown in Table 1-4.
Table 1-4
TS03 Track Assignments for Data and Parity
Transport
Track Number

Write
Data Bits

Read
Data Bits

Binary
Weight

1 furthest from
transport
2
3
4
5
6
7
8
9 closest to
transport

WDS

RDS

WD7
WD3
WDP
WD2
WDl
WDO
WD6
WD4

RD7
RD3
RDP
RD2
RDl
RDO
RD6
RD4

2°
24

1-12

2s
26
27
21
23

Part I
1.7

SPECIFICATIONS

Main Specifications
Storage medium
Capacity /tape reel
Data transfer speed
Drives/control, max.

Data Organization
N umber of tracks
Recording density
Inter-record gap
Recording method

9
800 bpi
0.5 in. min. (1.27 cm)
NRZI

Tape Motion
Read/write speed
Rewind time
Tape drive
Reel braking
Speed variation
Start/stop distance
Start/stop time

12-1/2 in./sec
1 minute, max.
single capstan
dynamic servo control
3% instantaneous; 1% long term
0.19 in. (0.48 cm)
30 msec

Tape Characteristics
Length
Type
Reel diameter

600 ft (182.9 m)
Mylar base, iron-oxide coated
7 in. (17.8 cm)

Mechanical
Tape drive, mounting
Tape drive, size
Tape drive, weight
Control unit, PDP-II
Control unit, PDP-8

Mounts on slides in a std 19-in. (48.3 cm) cabinet
10-1/2 in. (26.7 cm) panel height, 17-in. (43 cm) deep
37 lb. (16.7 kg)
Panel mounted, 5-1/4 in. (13.3 cm) high
Mounts in the computer assembly

Power
Input Current
Heat dissipation

1 A at 90 to 132 Vac, or 0.5 A at 180 to 240 Vac
100 W
-

Environmental
Operating temperature
Relative humidity
Altitude

15° C to 32° C
20% to 80%, with max wet bulb 25° C and min dew point 2° C
10,000 ft (3,048 m)

Miscellaneous
BOT, EaT detection
Magnetic head

Photoelectric sensing of reflective strip, industry compatible
Dual gap, read after write, 0.15-in. (0.4 cm) gap

Models
TM8-MA
TM8-MB
TS03-MA
TS03-MB
TS03-SA
TS03-SB

Tape drive and PDP-8 control, 115 Vac, 60 Hz
Tape drive and PDP-8 control, 230 Vac, 50 Hz
Master tape drive, 115 Vac, 60 Hz
Master tape drive, 230 Vac, 50 Hz
Slave tape drive, 115 Vac, 60 Hz
Slave tape drive, 230 Vac, 50 Hz

1/2-in. (1.27 cm) wide magnetic tape (industry compatible)
5 million characters
10,000 char/sec

1-13

Part I

CHAPTER 2
INSTALLATION

2.1

SITE PLANNING AND CONSIDERATIONS

2.1.1 Space Requirements
Figure 2-1 illustrates the space and service clearances required. Adequate space must be provided to slide the
equipment out of the rack for servicing and to open the front door on the TS03 DECmagtape Transport.
2.1.2 Power Requirements
The TMS-M DECmagtape System can be operated from a nominal 115 or 230 Vac, 50/60 Hz power source. Line
voltage should be maintained to within 10 percent of the nominal value and the frequency should not vary more
than 3 Hz. Ensure that primary power is compatible with the H720 Power Supply.
2.1.3 Environmental Requirements
The operating environment should have cool, well filtered, humidified air, a temperature range of 15° to 27° C,
and relative humidity of 40 to 60 percent.
2.2 UNPACKING
The TMS-M may be shipped in two different configurations:
with each device packaged separately.

with the system installed in an equipment rack or

2.2.1 Cabinet Unpacking Instructions
To unpack the cabinet, proceed as follows:
1.

Remove outer shipping container.
NOTE
The container may be either heavy corrugated cardboard
or plywood. In either case, remove all metal straps first,
then remove any fasteners and cleats securing the container to the skid. If applicable, remove wood framing and
supports from around the cabinet perimeter

Remove the polyethylene cover from the cabinet.

Unbolt cabinet(s) from the shipping skid. The bolts are located on the lower supporting side rails, and
are exposed by opening the access door(s). Remove the bolts.

Raise the leveling feet above the level of the roll-around casters.

Use wood blocks and planks to form a ramp from the skid to the floor and carefully roll the cabinet
onto the floor.

Roll the system to the proper location for installation.
2-1

Part I
SWINGING DOOR
(RH) NOTE 1

18 ~3~
(46.35cm)

nJp~~~~~~~~~~I\n-------------------~
+

REMOVABLE
END PANEL

REMOVABLE
END PANEL _ _ _ _ _

1--0---------,
I

48 7/ 32"
(122.47cm)

I
I

CABLE ACCESS----__________~___ I

,': _Q _

FAN
PORTS
30"
(76.2cm)

LEVELER
4 PLACES

+
CASTER SWIVEL
RADI US 2 13h~
(4) CASTERS

~1.1_ _-2111/16 ----~
:

NOTES:
,. Door may. be L.H. or R. H.
Allow space for either case.

2. CABINET 71'l1~(t82.28cm} high
(floor line to cabinet top).

Figure 2·1

(54.87 cm)

TS03 EXTENDED
FROM CABINET

19"
(48.26 cm)

L________ J~
i1-3092

Space and Service Clearance, Top View

2.2.2 Device Unpacking Instructions
Before unpacking the equipment, check the shipping list to ensure that the correct number of packages have been
received. Check the shipping list for the correct TMS-E module types. Carefully remove each device from its
shipping carton. Note that the side mounts are already attached to the TS03 transport(s) and the mounting
hardware is packed in a bag in each shipping carton.

2-2

Part I
2.3 INSPECTION
After removing the equipment from its container(s), inspect it and report any damage to the responsible shipper
and the local DIG IT AL Sales Office. Inspect as follows:

2.4

Inspect all switches, indicators, and panels for damage.

Remove equipment covers where necessary and inspect for loose or broken modules, blower or fan
damage, cable damage, and loose nuts, bolts, screws, etc.

Inspect wiring side of logic panels for bent pins, broken wires, loose external components, and foreign
material.

Check TS03 transport(s) for any foreign material that may have lodged in the tension arm, reel hubs,
and other moving parts.

Check power supply for proper seating of fuses and power connectors.

Inspect each TMS-E module for shipping damage.

INSTALLATION

2.4.1 Cabinet Installation
If the equipment is already mounted in the cabinet, proceed as follows:

Lower the leveling feet so that the cabinet is resting on the floor, not on the roll-around casters.

Use a spirit level to level the cabinet; ensure that all leveling feet are firmly on the floor.

Remove the shipping screws which secure the equipment to the cabinet.

Plug the H720 Power Supply ac power cord into a receptacle having the correct voltage and
frequency.

2.4.2 Device Installation
The equipment should be mounted in a 19 in. by 20 in. (4S.3 cm by 50.S cm) equipment bay. Figure 2-2 shows a
recommended cabinet layout. The equipment should be mounted from the top down.
2.4.2.1

TS03 Mounting Instructions - To mount the TS03, proceed as follows.
NOTE
If two TS03 transports (master and slave) are to be
installed, the slave (the unit without the M8920 adapter
module) is installed at the uppermost position.

Remove the outer portions of the guides from the TS03 chassis by actuating the slide releases and
mount the guides to the cabinet in the 19th hole from the top of the cabinet using the eight screws
provided. Ensure that the guides are level and parallel to each other.

Lift the TS03 up and slide it carefully into the guides until the slide releases lock.

2-3

Part I

TS{/)3
SLAVE

TS{/)3
MASTER

MOUNT GUIDES IN
19th HOLE FROM THE TOP

~ OF CABINET

MOUNT GUIDES IN
34th HOLE

NOTE 1

NOTE 2

PDP-8

NOTES:
NOTE 1

1. Expander box or other option
2. Contains four cords of TM8-E.
3. The TM8-E may be installed in
a separate expansion cabinet.

MOUNT IN

~ 69th HOLE
H720
POWER SUPPLY

08 -1669

Figure 2-2 Cabinet Installation

Carefully lift the slide releases and push the transport fully into the cabinet.

If a second TS03 transport is to be installed, repeat steps 1 through 3 above, but mount the guides in
the 34th hole.

2.4.2.2 TM8-E Controller Mounting Instructions - Perform the following procedure to install the four TMS-E
modules:
1.

Ensure that power is removed from the PDP-S and the TS03(s).

If the TMS-E and the TS03 are installed in more than one cabinet, ensure that the cabinets are tied to
the same ground or install a ground wire between the cabinets.

Ensure that the TMS-E module jumpers are correctly installed to select the priority assigned to the
TMS-E. (See "Data Break Priority Logic" in Chapter 9 of Part II of this manual.)

Insert the TMS-E modules into the Omnibus in the order shown in Figure 2-3.
CAUTION
The modules must not be installed upside down. The +5 V,
0.01 ~F capacitors should be at the bottom (next to the
Omnibus) on all modules installed on the Omnibus.

Install six HS51 edge connectors between the four modules as shown in Figure 2-5. The interconnections are made via connectors E, F, Hand J as shown in Figure 2-5 and on Signal Mapping
Drawing TMS-E-2.

2-4

Part I

M8321
Ma327

M8322

Ma323

0.01 p.F CAPACITORS
7724-1

Figure 2-3 TM8-E Module Orientation

2.4.2.3 H720 Power Supply Mounting Instructions - Using the hardware provided, mount the H720 Power
Supply in the cabinet at the 69th hole position.
2.4.3 I/O Signal Cable Connections
To install the I/0 signal cables, perform the following steps.
1.

Check both 7011571 cables to ensure that the jumpers shown in Figure 2-4 are installed.*

*The 7011571 cable is a modified BC08L cable. The modification consists of connecting the cable ground plane to M8920 output ground (pins
T I and C2) on the paddle card.

2-5

Part I

C2 TO GROUND

••••••••
• • •••••••••
•
•••••••
••••••••••

......... .
-

• • • • • • ••
• • • ••
•• •• •• •• •• •• ••
•

T1 TO GROUND

08-1672

Figure 2-4 Paddle Board Jumpers on Side 2
of Cable Assembly 7011571

Connect the two 40-pin connectors (PI and P2) of one of the 7011571 cables to 11 and J2 respectively
on the M8321 module.· The rough side of the cable faces the module. Connector P2 extends out
beyond Pi and connects to the inner jack (2) on the module. (See Figure 2-5.)
NOTE
The two ribbon cables that make up a 7011571 cable
assembly are the same length. The position of the cable
ends on the paddle board causes one of the cable plugs
(Pl) to extend out beyond the other (PI) at the other end
of the cable assembly. (See Figure 2-6.)

Tag the paddle board end of the cable as connecting to M8321.

Connect the two 40-pin connectors (PI and P2) of the other 7011571 cable to 11 and J2 respectively on
the M8323 module. The rough side of the cable faces the module. Connector P2 extends out beyond
PI and connects to the inner jack (J2) on the module.

Slide out the TS03-M drawer. Unscrew the two knurled screws holding the M8920 module and allow
the module to hang down as shown in Figure 2-7.

Connect the cable from the M8321 module to the "C" connector on the M8920 module and connect
the cable from the M8323 module to the "D" connector of the M8920 module using the two H870
edge connectors.

2-6

Part I
H861 EDGE
CONNECTORS (8)

M8323

E
F
J
H

7011171 CABLE
ASSEMBLIES

Figure 2-5 TM8-E Controller Cabling

t:;'231
M8321

ROUGH
jSIDE

(f;f 0

\\PADD~E ~
BOARD

llLJ
\

~SMOOTH 0;2
SIDE

Figure 2-6 7011571 Cable Assembly

2-7

0 LC::::Jl 0 0

~COMPONENT
SIDE

08-1675

Part I

PADDLE BOARD
CONNECTORS

KNURLED
SCREW

H870 EDGE
CONNECTORS

F
7724·'

Figure 2-7 M8920 Cabling to TM8-E

Remove one screw from the center cable strain relief and loosen the other. (See Figure 2-8.)

Swing the strain relief 0 ut and place the two 7011571 cables up against the edge of the chassis. Leave
enough slack so that the cables are not strained when the M8920 module is swung down.

Swing the top of the strain relief back into place. Insert the removed screw and tighten both screws.

10.

Install the 7010570 master/slave cables between the M8920 module connectors (J 1 through J6) and
the TS03 master and slave transport connectors as listed in Table 2-1 and shown in Figure 2-9. Use
the three strain reliefs as in steps 7, 8, and 9 to secure the 7010570 cables. Tighten the two screws on
each of the transport connectors.

2-8

Part I

STRAIN RELIEFS (3)

7724-2

Figure 2-8 Securing TM8-M Cables

TS03 MASTER (TS03-M)

TS03 SLAVE (TS03-S)
TRANSPORT (REAR VIEW)

TRANSPORT (REAR VIEW)

J2 WRITE

Jt CONTROL

7011571
CABLES

Jl CONTROL

OMNIBUS

H870
EDGE CONNECTORS
08 -1664

Figure 2-9 I/O Cable Connection Diagram

2-9

Part I
Table 2-1
7010570 Cable Connections
From
M8920 Adapter Board
Connector

To
TS03 Master
Connector

J2
J3

J3
J5
J2

TS03 Slave
Connector

J2
J3
J1

J4
J6

2.4.4 Power Connections
To make power connections, proceed as follows. (See Figure 2-10.)
1.

Install the power harness (70-10832) between the H720 Power Supply and the M8920 adapter module
in accordance with color coding listed in Table 2-2.

Plug the TS03 master and slave transport ac power cords into the H720 Power Supply switched
receptacles.

Plug the H720 Power Supply power cord into the site's primary ac power outlet having the proper ac
voltage and frequency. Check the label on H720 Power S~pply for power requirements.

Using tie wraps, neatly dress all cables and harnesses. Leave service loops so TS03 drives can be
extended from the cabinet and the M8920 adapter can be swung down on its hinges.

TS03 MASTER (TS03 - M)
TRANSPORT (REAR VIEW)

TS03 SLAVE (TS03-S)
TRANSPORT (REAR VIEW)

M8920 ADAPTER
SWITCHED AC POWE

POWER HARNESS
(70-10832)

H720 POWER SUPPLY

PRIMARY
AC POWER

08-1671

Figure 2-10 Power Connection Diagram

Part I
Table 2-2
Power Harness Color Coding
DC Voltage/Signal

Wire Color

+5 V
Gnd
ACLO

Red
Black
Yellow

2.S ACCEPTANCE TESTING
Refer to the TMB-MA & MB/TS03 Drive System Checko1:!t and Acceptance - WM (Engineering Drawing No.
SP-TMB-M-I) for the acceptance test procedures for the TM8-M Tape Drive System.

2-11

Part I

CHAPTER 3
SYSTEM OPERATING INSTRUCTIONS

3.1

SCOPE

This chapter covers operation of the TM8-M, including a description of controls and indicators and all operating
procedures.

3.2

CONTROLS AND INDICATORS

Figure 3-2 describes the controls and indicators.

3.3
3.3.1

OPERATING PROCEDURES
Tape Threading

To thread the tape on the transport, proceed as follows:
1.

Raise the latch of the quick-release hub and place the tape file reel to be used on the supply hub
(Figure 3-1) with the write enable ring side next to the transport deck.

Hold the reel flush against the hub flange and secure it by pressing the hub latch down.

Thread the tape along the path as shown in the threading diagram (Figure 3-1).

Holding the end of the tape with a finger, wrap a few turns counterclockwise around the takeup hub.

Figure 3-1

Tape Threading Diagram

3.3.2 Tape Loading
Pressing the LOAD pushbutton energizes the reel servos and initiates a load sequence. Tape advances to the load
point marker and stops. If for some reason the load point marker is already past the sensor (as, for example, in
restoring power after a shutdown), tape will continue to move. Under these conditions, press LOAD and then
REWIND and the tape will rewind to the load point. Once pressed, the LOAD switch is illuminated and is
inactive until power has been turned off or tape is removed from the machine.

3-1

Part I

UNIT SELECT Plug - One of two plugs can be inserted,
designating unit as 0 or 1.

mamaomo
~3

WRITE ENABLE Indicator - Illuminated whenever a reel
with a write enable ring is mounted on the supply hub.

ON LINE Pushbutton/Indicator - A momentary pushbutton, which functions as alternate action. When first
activated, the tape unit is placed in an on-line condition;
when the tape unit is on-line, it can be remotely selected
and will be ready if tape is loaded to or past the load point.
When activated again it takes the unit off-line. The
indicator is illuminated in the on-line condition. The load
function must be performed before the unit will go on-line.

UNIT

SELECT

WRITE
ENABLE

ON LIN.

LOAD

REWIND

NOTE
I n a single drive system, the drive is always
designated as drive O. In a dual drive system,
either drive can be designated as drive O.

D
D
D

LOAD Pushbutton/Indicator - The momentary pushbutton activates the reel servos (tensions tape) and starts the
load sequence. The indicator is illuminated when the reel
servos are activated and tape is tensioned.
REWIND Pushbutton/Indicator - The momentary pushbutton activates a rewind operation. This control is enabled
only when tape is tensioned and the unit is off-line. The
indicator is illuminated during either a local or a remote
rewi nd operati on.
POWER Switch - The ON/OFF switch applies ac power to
the tape transport.

ON
POWER

OFF

11-3045

Figure 3-2 Controls and Indicators

3-2

Part I
3.3.3 Placing Tape Unit On-Line
After the tape is properly threaded and has been loaded and brought to the load point, press the ON LINE
pushbutton and check that the ON LINE indicator illuminates. (The REWIND pushbutton is disabled when the
tape unit is on-line.) On-line status enables the tape unit to be remotely selected and to perform all normal
operations under remote control.
3.3.4 Tape Unloading and Rewind
Provision is made in the TS03 transport for rewinding a tape to the load point under remote control. However,
this operation may also be performed manually. Proceed as follows:
1.

If the 0 N LINE indicator is illuminated, press the ON LINE pushbutton. Check that the indicator
extinguishes when pressure is removed.

Press the REWIND pushbutton. The tape will now rewind to the load point marker.

After the tape has been positioned at the load point under remote or local control, press the REWIND pushbutton to rewind the tape past the load point to the physical beginning of the tape.
NOTE
The rewind sequence cannot be stopped until the tape has
rewound either to the load point or until tension is lost at
the physical beginning of the tape.

3.3.5 Power Shutdown
A tape transport should not be turned off when tape is loaded and is past the load point marker. The TS03
transport is designed to prevent physical damage to the tape in the event of power failure, and to minimize
operator error which could destroy recorded data. In the event of power failure during tape unit operation,
manually wind the tape forward several feet before restoring power. When power has been restored, press the
LOAD pushbutton, then the REWIND pushbutton. This will rewind the tape to the load point. If desired, the
tape can then be advanced to the data block nearest the point at which the power failure occurred by initiating
the appropriate control commands.
CAUTION
In dual drive systems, when one drive is on-line and running, do not turn power off at the unused drive, i.e., do not
set the TS03 POWER ON/OFF switch to OFF. To do so
may result in data errors on the drive that is running.

3-3

Part I

CHAPTER 4
CUSTOMER EQUIPMENT
CARE AND OPERATION

4.1

SCOPE

The information contained in this chapter will assist the customer in caring for his equipment and ensure the
highest level of performance and reliability.

4.2 REQUIREMENTS
The customer is directly responsible for:
1.

Obtaining operating supplies, including disk cartridges, disk packs and filters, magnetic tape, DECtape, paper tape, cassettes, printer paper, printer ribbons, plotter paper, etc.

Supplying accessories, including disk storage racks, DECtape storage racks, carrying cases for disk
cartridges and DECtape, cabinetry, tables and chairs.

NOTE
Users of Digital Equipment Corporation equipment may
obtain the proper operating supplies and accessories by
contacting:
Digital Equipment Corporation
DEC Supplies Order Processing
146 Main Street
Maynard, Massachusetts 01754
Phone: (617)897-5111, Ext. 5218,5907
Boston Area: (617)890-0330
TWX: 710-347-0212
Cable: Digital Mayn
Telex: 94-8457
3.

Maintaining the required logs and report files consistently and accurately.

Making the necessary documentation available in a location convenient to the system.

Keeping the exterior of the sysli!m and the surrounding area clean.

Turning off the teletypewriter and/ or line printer when these devices are not in use.

Performing the specific equipment care operations described for the various devices at the suggested
frequencies, or more often if usage and environment warrant.

Ensuring that ac plugs are securely plugged in each time equipment care operations are performed.

4-1

Part I
4.3

4.4

CARE OF MAGNETIC TAPE
1.

Do not expose magnetic tape to excessive heat or dust. Most tape read errors are caused by dust or
dirt on the read head; it is imperative that the tape be kept clean.

Always store tape reels inside containers when not in use; keep the empty containers tightly closed to
keep out dust and dirt.

Never touch the portion of tape between the BOT and EaT markers; oil from fingers attracts dust
and dirt.

Never use a contaminated reel of tape; this will spread dirt to clean tape reels, and could have an
adverse effect on tape transport reliability.

Always handle tape reels bv the hub hole; squeezing the reel flanges could lead to tape edge damage in
winding or unwinding tapes.

Do not smoke near the tape transport or storage area; tobacco smoke and ash are especially damaging to tapes.

Do not place magnetic tape near any line printer or other device that produces paper dust.

Do not place magnetic tape on top of the tape transport, or in any other location where it might be
affected by hot air.

CARE OF TS03 TAPE TRANSPORT

4.4.1 General
Digital Equipment Corporation tape transports are highly reliable precision instruments which will provide years
of trouble-free performance when properly maintained. A planned program of routine inspection and maintenance is essential for optimum performance and reliability.
4.4.2 Prel'entil'e Maintenance
To ensure continuing trouble-free operation, a preventive maintenance schedule should be kept. Oniy a few items
are involved, but they are very important to proper tape transport operation. The frequency of performance will
vary somewhat with the environment and degree of use of the transport so a rigid schedule applying to all
machines is difficult to define. The recommended periods apply to units in constant operation in ordinary environments. They should be modified if experience shows other periods are more suitable.
Before performing any cleaning operation (Table 4-1), remove the supply reel and store it properly. All items in
the tape path must be cleaned on a per-shift basis. In cleaning, it is important to be thorough yet gentle and to
avoid certain dangerous practices. It should be remembered that the tape cleaner is a strong cleaning agent and
should not come in contact with painted surfaces or plastic.
CAUTION
Do not use: acetone or lacquer thinner; aerosol spray
cans; rubbing alcohol; excessil'e cleaner. Be extremely
careful not to allow the cleaner to penetrate ball bearings,
tension rollers, and motors.
4.4.3

Materials Required
1.

DECmagtape system and magtape cleaning kit

Lint-free wipers
4-2

Part I
Table 4-1
Customer Equipment Care Operations
Device: TSO) DEC magtape Transport
Operation

Frequency
Once
per shift

Clean tape path according to the following procedure. (Time required = 5 min.)
a.

Remove tape from transport.

Using head cleaner and lint-free cloth, clean the following (Figure 4- 1):
Head and head shield
Load point/end-of-tape sensor
Missing tape sensor
Both tape guides
Tape cleaner
Tape tension roller (not shown)
Capstan (not shown)

Using a clean, dry, lint-free cloth or wipe, once again go over each
surface listed above to dry and remove any residue.

NOTE
Do not use any cloth or wipe that has come in
contact with the tape path as it is probably
contaminated.
d.

Using a clean, lint-free cloth or wipe, dust the inside and outside of
the plexiglass door. If dirt and dust have accumulated, a mild soap
and water solution or antistatic cleaner may be used. Ensure that
the door is dry before returning the tape transport to service.

HEAD COVER REMOVED FOR CLARITY

Figure 4-1

Opening Head Shield

4-3

11-3051

Part I

CHAPTER 5
SYSTEM MAINTENANCE

5.1 SCOPE
This chapter provides a complete description of TMS-M preventive and corrective maintenance procedures.
5.2 MAINTENANCE PHILOSOPHY
The TMS-M DECmagtape System is highly reliable and will provide years of trouble-free performance when
properly maintained. A planned program of routine inspection and maintenance is essential for optimum performance and reliability.
The preventive maintenance required on each unit differs in accordance with its design. The TMS-E Controller,
MS920 adapter, and H720 Power Supply are total solid state units with no moving parts; therefore, no preventive
maintenance is required on these units. The TS03 transport, however, requires daily customer care consisting of
head and tape path cleaning (Chapter 4). Otherwise, the transport requires very few adjustments and these
should not be performed unless problems are encountered in transport operation. See Paragraph 5.4 for the
recommended preventive maintenance procedure.
Corrective maintenance consists of troubleshooting at the system level using system diagnostics and visual observations to localize the failure to a particular unit, whether it be the TMS-E Controller, the MS920 adapter, the
TS03 transport, or the H720 Power Supply. Once the faulty unit is determined, unit level troubleshooting will be
performed using unit functional block diagrams, engineering flow diagrams, timing diagrams, and detail logic
diagrams to localize the failure to an electrical module or mechanical part.

NOTE
In the case of the TS03 transport, troubleshooting tables
are provided (see Tables 5-5, 5-6 and 5-7) listing the symptoms, possible causes, indications, and recommended
actions.
Once the faulty module or mechanical part is located, it should be replaced. If the faulty part is a module, it
should be returned to the depot for repair; if a mechanical part fails, it should be replaced and repaired only if the
cost warrants it.

5.3 TEST EQ UIPMENT
Test equipment required to maintain the TMS-M falls into two categories:
test equipment.

standard test equipment and special

5.3.1 Standard Test Equipment
'Maintenance procedures for the TMS-M require the standard test equipment and diagnostic programs listed in
Table 5-1, in addition to standard hand tools, cleaners, test cables, and probes. Table 5-2 describes the diagnostic
programs.

5-1

Part I
Table 5-1
Standard Test Equipment Required
Designation

Equipment

Manufacturer

Multimeter
Oscilloscope
XIO Probes (2)
Diagnostics (MAINDECS)

Triplett or Simpson
Tektronix
Tektronix
DIGITAL

Model 630NA or 260

1 ype 453 or equivalent
P6008
MAINDEC-08-DHTSA
MAINDEC-08-DHTSB
MAINDEC-08-DHTSC
MAINDEC-08-DHTSE
MAINDEC-08-DHTSF

Table 5-2
Diagnostic Descriptions
Number

Title

Description

MAINDEC-08-DHTSA

TM8-E/TS03 Control Test,
Part 1

Twelve tests to checkout the TM8-E independent
of the TS03.

MAINDEC-08-DHTSB

TM8-E/TS03 Control Test,
Part 2

Twelve tests to checkout the TM8-E and the TS03
together as a subsystem.

MAINDEC-08-DHTSC

TM8-E/TS03 Data Reliability
9 Track

Used to collect statistical information pertaining to
the data reliability of 9-track transports used with
the TM8-E.

MAINDEC-08-DHTSE

TM8-E/TS03 Drive Function
Timer

Tests the TM8-E and TS03 with selected operations
that are timed and the execution times are printed
out.

MAINDEC-08-DHTSF

TM8-E/TS03 Utility Driver

Allows operator to perform any test in any order.
Tests will operate regardless of results or errors.

5.3.2 Special Test Equipment
The special test equipment and tOQls required are listed in Table 5-3.

5.4 PREVENTIVE MAINTENANCE
Refer to TS03 DECmagtape Transport Preventive Maintenance Manual. Document No. EK-TS03-PM-OOI.

5-2

Part I
Table 5-3
Special Test Equipment and Tools

5.5

Equipment

Manufacturer

Part No.

Test box
Tape path alignment tool
Transport module extender
Skew tape (7 in. (7.78 cm) reel)
Scratch tape (600 ft.(182.9 cm))
Scratch tape (600 ft.(182.9 cm))
Magna-See@ (also renew solution)
Magnifying glass
Reflective tape marker
Write ring
Head cleaner, capstan cleaner,
lint-free cloth (Kimwipes)
Scotch tape (3/4 in.)

DIGITAL
DIGITAL
DIGITAL
DIGITAL
DIGITAL
DIGITAL
eBS

29-21922
29-21904
29-21925
29-22020
18-09540-00*
18-09540-02*
29-16871
29-20273
90-09177

DIGITAL
DIGITAL

TueOl
Buy Locally

ADJUSTMENTS

5.5.1 General
Most of the adjustments in this paragraph relate to ensuring that data is written and read perpendicular to the
reference edge of the tape. Properly written data is necessary to ensure that a tape written on one machine can be
read on another (compatibility). Many of the adjustment procedures utilize the test box, shown in Figures 5-1
and 5-2. A description of the test box is given in Paragraph 5.5.2.
The TS03 adjustment procedures are summarized in Figure 5-3. The sequence of the procedures is logical providing complete adjustment of the TS03 while minimizing adjustment time and tape handling. Adjustments can be
performed separately and in any order, except as noted in Figure 5-3.

5.5.2 Test Box
5.5.2.1

Functions of Test Box - The test box provides:

An alternative motion control source bypassing the controller interface logic and the TS03 control
panel logic. All combinations of speed and direction are available with BOT (LOAD POINT) and
EOT interlocks to prevent running tape off of the reels.

A write test feature to generate an all Is pattern for correcting write skew.

A skew light indicator to detect when data falls outside the skew window.

A choice of instantaneous and average (dynamic) skew error indication in the form of a voltage level.

Automatic, rapid, stop-start capability for use in ramp time adjustments.

@Magna-See is a registered trademark of Columbia Broadcasting System, Inc., Danbury, Conn.
*No. 00 is packaged in a canister. No. 02 is tape-seal package.

5-3

Part I

7856-6

Figure 5-1

5.5.2.2

TS03 Test Box

Test Box Operation

Hookup - The test box is connected to the only exposed edge connector among the PC boards (slot
10). The connector is not keyed and mu:;t be installed with the RED wire (pin A) to the left and to the
rear. (See Figure 5-2.)

Activation - To enable the test box:
a.
Drive must be OFF-LINE (TS03 Control Panel).
STOP Switch must be pressed.
b.
c.
TEST MODE must be pressed.
NOTE
Test mode is terminated by pressing the test mode switch a
second time or placing the drive ON LINE pushbutton.

5-4

Part I

RED
WIRE

7856-10

Figure 5-2 Test Box Installation

Motion Switches
a.
Each of the four motion switches performs its indicated function and is interlocked with the
other motion switches.
b.

Motion is terminated by the STOP button or by reaching either tape sensor (BOT or EaT).

Pulling the toggle switch (next to the connector cable) forward causes normal test motion to be
cycled on and off at approximately 10 times per second.

5-5

Part I

o
4

NOTES
I.

A number to the left of a flow block indicates thet the
associeted procedure is dependent on any other procedure having a lower flow symbol number
e.g. A reed level adjustment must be preceded by a tape
speed adjustment. a capstan perpendicularity adjustment and a tape peth alignment.

mechanical adjustment

.,A.,

electrical adjustment

0""0 switch ..ttings
08-1685

Figure 5-3 TS03 Adjustment Flowchart

5-6

Part I

Toggle Switch - The three-position toggle switch at the top of the test box selects instantaneous ske\\
(middle position) or average (dynamic) skew (rear position). The forward position provide"
rapid (10 cps) start/stop operation.

Write test
a.
Must be in test mode.
b.
Operates only in Forward R un condition.

Indicators - All indicators operate whether in test mode or not.
a.
Test mode - Test mode is selected
b.
Write test - All Is being written on tape.
c.
Load Point - At beginning of tape (BOT).
d.
EOT - At end of tape.
e.
DATA - Data is being read.
f.
SKEW - Data packet width exceeds skew window.
(normal window = 16/32 in. (1.264 cm);
read while write = 12/32 in. (0.948 cm);
test mode = 5/32 in. (0.395 cm»

Test Point - Provides skew error indication in the form of a voltage level. The skew error is proportional to the measured voltage such that 1 V equals 10 J.LS of error.

Adjustments - Two calibration adjustments are associated with the skew conversion circuit. Engineering Drawing TD8 contains the information necessary for making these calibrations. Both adjustments are located inside of the Test Box.

5.5.3 Adjustment Procedures
Remove the screen covering over the PC boards and the protective cover in front of the head assembly.
CAUTION
Always remove power from the tape drive when removing a
PC board.
The PC boards are identified in Figure 5-4. Most adjustments and test points referred to in the procedure are
found in Figure 5-4.
5.5.3.1 Voltage Check - The power supply provides ±24 Vdc (unregulated), ± 10 Vdc (regulated), and +5 Vdc
(regulated). These voltages are not adjustable but should be checked to verify correct operating voltages. Perform
the following steps to check the operating voltages.

Power Switch ON.

Measure +24 Vdc and -24 Vdc supplies (Figure 5-5). Both supplies will measure about 26 Vdc when
under light load.

Measure + 10 Vdc, -10 Vdc, and +5 Vdc at test points A, B, and C on sensor amplifier. Voltage
tolerance is ± 5%.

5-7

Part I

GROUND

SENSOR ADJ

TP-F

TP-E

TP-A
SPEED ADJ
START RAMP ADJ

STOP RAMP ADJ

TPC
TPB
TPA, ---..",..,.,..,,-

7856-9A

ITEM
NO.

PART
NO.*

13
12
11
10
9
8

4306-002
3844-001
3645-002
3843-001
3842-001
3841-001

INDICATES TAPE CHANNEL NUMBER

ITEM
7
6
5
4
3
2
1

SERVO PREAMPLIFIER
SENSOR AMPLIFIER/DRIVER
RAMP GENERATOR
TAPE MOTION CONTROL
INTERFACE CONTROL
CONTROL TERMINATOR

4845-001
4179-004
4178-004
4178-004
3860-001
3848-001
3849-001

*Vendor part nos. See Appendix J for cross reference to DEC part nos.

Figure 5-4 Plug-In Modules and Test Point Locations

5-8

TIMING DELAY
P CHANNEL/CLIPPING
QUAD READ AMPLIFIER
QUAD READ AMPLIFIER
DATA TERMINATOR
4 CHANNEL HEAD DRIVER
5 CHANNEL HEAD DRIVER

Part I

------- + 5 V - - - : -

SERVO

7856-4

-24 V ON

+24 V ON

Ql0 CASE

Q9 CASE

Figure 5-5 TS03 Tape Transport, Rear View

5.5.3.2 Tape Path Alignment - The tape path leading to and from the tape head must be as straight as possible.
Variations in the tape path will cause the tape to be twisted as it moves over the head. The alignment procedure
will compensate for mechanical tolerances and wear of buffer arm rollers and tape guides. Perform the following
steps to accomplish a tape path alignment.
NOTE
An alternate tape path alignment procedure, not requiring
the tape path alignment tool, can be found immediately
following this procedure.
1.

Remove protective covering in front of M8920 module by removing two Phillips head screws (master
drive only).

Remove the control panel cover by lifting up and outwards from bottom.

Remove both tape guides (screws will be used to mount alignment tool) (Figure 5-6).

5-9

Part I

TAPE CLEANER

EaT/BOT
TAPE SENSOR

HEAD SHIELD

7B56-5

TAPE GUIDE (2)

TAPE GUIDE
SCREW (2)

MISSING TAPE
SENSOR

READIWRITE HEADS

Figure 5-6 Head Assembly with Tape Guides

M aunt tape path alignment tool using tape guide screws. Tighten screws finger-tight.

Use an Allen wrench to loosen tape path alignment clamp screws on both tape tension arms from
bottom side of drive (Figure 5-7).

Loosen perpendicularity adjustment lock screws.

Center each roller guide in the "Vee" of the alignment tool and lock in place with the clamp. The
clamp handle has a slip clutch to prevent damage to the roller (Figure 5-8).

Tighten perpendicularity adjustment lock screw for both rollers.

Disengage one clamp.

5-10

Part I
MAG POT ASSEMBLY

ROLLER GUIDE
SHAFT (THREADED

TAPE PATH
ALIGNMENT

PERPENDICULARITY
ADJUSTMENT

END)

CLAMP SCREW

LOCK SCREW

TAPE TENSION ARM

7856-1

Figure 5-7 Roller Guide/Tape Tension Ann Connection,
Bottom View

10.

Align the roller path with a guide by pressing the released roller inward until the roller guide face just
touches the outer f8~e of the alignment tool. (Figure 5-9).

11.

Tighten the tape path alignment clamp.

12.

Repeat steps 9, 10, and 11 for the other roller guide.

5-11

Part I

7856-3

Figure 5-8 Use of Alignment Tool

ALTERNATE PROCEDURE
Tape Path Alignment Without Use of Alignment Tool
This procedure is provided in case the special purpose alignment tool is not available. The following material is
required for this special procedure:
•

Stainless steel 3/16 in. rod (0.1875 in. dia. by approximately 4 in. (10.16 cm) long)

•

10-32 nut (2)

•

#10 washers (10)
(Refer to Figure 5-7 throughout this procedure.)

Remove the roller guide to be aligned and replace it with a length (4 in. (10.16 cm) approximately) of
3/16 in. (0.1875 in.) stainless steel round rod stock. Clamp in place with the tape path alignment
clamp screw.

Loosen the perpendicularity adjustment lockscrew slightly so that with moderate pressure the end of
the tape tension arm can be rotated.

Thread mag-tape over the rod.

While holding the rod, run the tape forward. Tilt the rod up and down until a position is found at
which the tape runs with equal tension on its inside and outside edge and the tape enters the tape
guides correctly and winds correctly on the center of the take-up reel.

5-12

Part I

7856-7

a. Setting Roller Guide Position

ABUTTING
SURFACE

~DIRECTION

~ OF PRESSURE

08-1679

b. Proper Alignment Position
Figure 5-9 Tape Path Alignment

5-13

Part I
5.

When this position is found, ti~hten the perpendicularity adjustment lockscrew securely.

Replace the roller guide and clamp lightly by gently tightening the tape path alignment clamp sc~ew.

The roller guide shaft end is threaded to allow use of a nut for fine adjustment. Place several No. 10
flat washers over the threaded end and install a 10-32 nut on the shaft.

Pull the roller guide so that the roller is too far out. Lightly tighten the adJustment nut.

Load the tape on the transport and feed it forward.

10.

Tighten the nut pulling the roller guide back in toward the transport until the tape runs along the
reference edge just inside the outer surface of the roller guide with the spring-loaded side of the tape
guide manually pushed in.

11.

Tighten the tape path alignment clamp screw.

12.

Remove the adjusting nut and washers.

5.5.3.3 Capstan Creep Adjustment - The capstan servo loop employs an operational amplifier which is subject to dc
offset due to component tolerances and aging. This offset could cause the capstan motor to creep. To adjust for
capstan creep, perform the following steps:
NOTE
Tape tension arms may be clamped in alignment tool to
reduce noise distraction.
1.

With power OFF, extend servo Pre-Amp Card (No. 13) using the extender board.

Power up the drive unit.

Fold a piece of white paper in half twice to obtain quadruple thickness.

Press LOAD button and hold.

Insert quadruple thickness paper under EOT /BOT sensor lamp (Figure 5-6). Insert paper from the
front, not the side, taking care that the paper does not get between the head and head shield.

Release the LOAD switch; capstan should be stationary.

Attach voltage probe to test point "A" (Figure 5-10).

Set capstan creep adjustment (R56) for minimum voltage.

Remove folded white paper.

10.

Remove power from tape drive.

11.

Remove extender board and replace Servo Pre-Amp Card in slot 13.

5-14

Part I

CAPSTAN CREEP
ADJUSTMENT (R56)

TEST POINT A

7856-12

Figure 5-10 Servo Pre-Amp, Card No. 13

5.5.3.4 Mag Pot Adjustment - A magnetic potentiometer provides an electrical indication of spring tension on
the tape tension arm. An electrical null point in the center of the tension arm travel arc indicates when the tape
tension is at approximately 8 ounces. The procedure will ensure that the tension arm is at a null when in the
center of the travel arc and that the null is the correct one. Refer to Figure 5-11 during the procedure.
1.

With power ON a'1d the tape path alignment tool attached, press LOAD button on the drive control
panel. Both reels will rotate counterclockwise.

Insert folded white paper under BOT IEOT sensor lamp.

5-15

Parr I

MAG POT
AMPLIFIER
BOARD

MAG POT

ARMATURE

SETSCREW
7856-2

Figure 5-11 Mag Pot Position Sensor Assembly, Plastic Cover Removed
3.

Manually swing tension arm into "Vee" of alignment tool and clamp in place. Reel should stop. Slow
reel motion is acceptable. Perform this procedure for both reels.

If conditions in step 3 are not met, adjustment is required. Slip off the plastic mag pot cover.

Loosen armature set screw.

Adjust armature until motion stops.

5-16

Part I
7.

Tighten armature set s'trew.
CAUTION
The magpot has two null positions 180 0 apart. Adjusting
for the wrong null will cause the tape tension arm to seek
the limits of the .arc instead of its center. A 180 0 null position is also indicated if the tape hub spins clockwise when
the tape tension arm is released without the tape threaded.

Replace mag pot cover.

Remove alignment tool and replace tape guides.

10.

Verify proper operation by checking output of mag pot at pin 4 of the mag pot connector for approximately + 5 to -5 V change while manually moving the buffer arm from one stop to the other (pin 4
wire on take-up reel is violet; pin 4 wire on supply reel is grey).

5.5.3.5 Write Lock Adjustment - A mechanical sensor detects the presence of the write ring. When the ring is
detected, a solenoid withdraws the sensor away from the write ring and provides a write enable indication on the
front panel. The adjustment procedure compensates for mechanical tolerances and verifies that the write lock
operation is functioning.

Hold control panel LOAD button pressed.

Press write ring sensor approximately 1/8 in. (0.32 cm). Sensor should retract and hold itself just
behind hub flange (Figure 5-12).
WRITE RING SENSOR

HUB FLANGE

08-1667

Figure 5-12 Supply Reel, Side View

5-17

Part I
3.

Release LOAD switch. Sensor should extend to original position.

If the sensor does not withdraw behind the hub flange, loosen two adjustment screws in the sensor
assembly and reposition the assembly so that the sensor is behind the hub flange when in the withdrawn state.

5.5.3.6 Head Shield Adjustment - Write head flux generated during a read-whi~e-write operation is great enough
to effect data being read. The "cross-talk" from write heads to read heads may cause parity, CRC, or LRC errors
to be indicated at the controller when no errors exist. The head shield provides magnetic shielding between the
read and write heads. To adjust the head shield, perform the following steps:
1.

With tape removed from machine, loosen the stop screw (Figure 5-13).

Fold a section of magtape onto itself to obtain a triple thickness (0.006 in. (15 mm)).

Insert the triple thickness of tape between the head shield and the top surface of the head.
CAUTION
Do not use feeler gauges - they will scratch the head

surface.
4.

Press the shield firmly against tape and tighten stop screw.

HEAD SHIELD

STOP SCREW

7856-5A

Figure 5-13 Head Shield Adjustment

5-18

Part I
5.

Remove tape by lifting head shield.

Close the head shield.

5.5.3.7 Tape Cleaner Adjustment - The tape cleaner catches loosened oxide from the surface of the tape before it
can relocate itself to the head or another part of the tape.
1.

Mount tape on drive.

NOTE
Choice of skew tape here will simplify later adjustments.
2.

Verify that the surface of the tape cleaner (Figure 5-6) presses lightly against the tape Gust enough to
deflect the tape path) and that it is parallel to the tape (Figure 5-14).

TAPE PATH
WITH CLEANER

-~TAPE

PATH WITHOUT
CLEANER

PLUG
08 -1676

Figure 5-14 Tape Cleaner Adjustment

If the requirements of step 2 are not met, remove the plug in the end of the tape cleaner and loosen the
Allen screw inside.

Adjust cleaner for proper position, tighten the Alien screw, and replace the plug.

5.5.3.8 Capstan Perpendicularity Adjustment - The capstan axis must be perpendicular to the tape path or the
tape will move sideways on the capstan as the tape direction is changed. To adjust for capstan perpendicularity,
perform the following steps:

NOTE
See Figure 5-3 for adjustments which must precede the
capstan perpendicularity adjustment.
1.

With the tape threaded, move it forward several feet (about 2 meters) at normal speed.

Note the position of the tape relative to the inner edge of the capstan.

Run the tape reverse for one foot and note the position of the tape as in step 2.

If the difference between the two edge positions is less than 1/32 in. (79 mm), (half the thickness of a
penny), capstan perpendicularity is all right (Figure 5-15). If the difference is more than 1/32 in. (79
mm), and if adjustment screws A and B in Figure 5-16 are provided, proceed to step 5.

5-19

Part I

TAPE MOTION
~

1/32"
CAPSTAN

08 -1673

Figure 5-15 Capstan Perpendicularity Check

Om
08 -1674

Figure 5-16 Capstan Motor Mounting Screws
5.

Slightly loosen mounting screws I and IV, then II and III.

Adjust set screws A or B for minimum sideway tape movement when running tape one foot (30 cm)
forward to one foot (30 cm) reverse.

Tighten four mounting screws so that those closest to the adjusted set screw are adjusted last.

Observe the tape motion through tape guide. When properly aligned, the tape will have a slight
tendency to follow the spring loaded (inside) edge guide when the inner guide is pressed manually.
The tape should not run hard against either guide surface.

5.5.3.9 Photo Sensor Adjustment - The Load Point (BOT) and EOT sensors employ a balanced analog circuit
using two cadmium sulfide photo resistors. The photo sensor adjustment compensates for aging of the photo
resistor elements. Perform the following steps:
1.

Verify that both upper and lower photo sensor lamps are illuminated.

Verify that tape is threaded and that a reflective maker is not positioned between the sensor lamps.

5-20

Part I

Measure voltage between TP-E and TP-F on the sensor amplifier board (No. 12) (Figure 5-4).

Set the photo sensor adjustment for 0 V difference between test points.

5.5.3.10 Tape Speed Adjustment - Tape speed must be maintained at a constant value so that tapes written on
one drive will be compatible with other drives. To adjust tape speed, perform the following steps.
NOTE
See Figure 5-3 for adjustments which must precede the
tape speed adjustment.
1.

Mount skew master tape.

Attach test box.

Run tape F\VD.

Observe any of the read preamp test points (Figure 5-17) using the oscilloscope; check for a sine wave
with a period of approximately 200 p.s. The waveform may not be stationary due to small tape speed
variations.

Adjust speed control potentiometer for a 200 p.s period. Refer to Figures 5-4 and 5-17 for location of
potentiometer.

5.5.3.11 Read Skew Adjustment - This adjustment serves to mechanically position the read heads perpendicular
to the reference edge of the tape as shown in Figure 5-18.
NOTE
See Figure 5-3 for adjustments which must precede a read
skew adjustment.

Run skew master tape forward.
CAUTION
Do not run skew tape at fast speed -

FWD or REV.

If skew error LED on the test box is lit, adjust the skew adjustment screw until the light is out (Figure
5-19).
a.

An alternate procedure is to use an oscilloscope and adjust for minimum voltage level at the test
point on the test box (Figure 5-20). Set sweep speed for lOOms/division. Set vertical gain to 0.5
V /division thereby giving 10 p.s of character skew per 1 V of output.

Still another method (not using the test box) is to place the scope on pin 8 on the edge connector
at the top of the motion control card and adjust for minimum data packet spread.

Select REVERSE RUN. When the tape stops, remove the master skew tape.

5-21

Part I

TAPE SPEW ADJUSTMENT POT

READ
PRE-AMP
TEST POINT
(CHANNEL 3*)

READ PRE-AMP
ADJUSTMENT (CHANNEL 3*)

*Read pre-amp channels from
left to right are: 3, 5, 7, 6, 4~
2, P, 1, O.

Figure 5-17 Tape Speed and Read Pre-Amp Adjustment

5-22

Pari f
REFERENCE
EDGE

T",PE MOTION

,
I
,,
I

t
PATIERN RESULTING FROM
MISALIGNMENT OF HEAD

PATIERN RESULTING AFTER HEAD
IS ALIGNED USING MASTER SKEW TAPE

~
DEVIATION FROM PERPENDICULARITY
CAUSED BY MISALIGNMENT

08-1681

Figure 5-18 Skew Error (Caused by non-perpendicularity of
head assembly to reference edge of tape)

SKEW ADJUSTMENT

Figure 5-19 Location of Skew Adjustment

5-23

Part I
SKEW

20 Jl,S 16 Jl,S 10 Jl,S -

6 Jl,S -

08-1682

Figure 5-20 Read Skew Adjustment Waveform

5.5.3.12 Read Level Adjustment - This adjustment is made by measuring the read signal while writing an all 1s
pattern. (This technique results in an observed signal amplitude that is more constant and 10 percent greater than
a normal read.)

NOTE
See Figure 5-3 for adjustments which must precede a read
level adjustment.
1.

Mount scratch tape with write ring.

Write an all Is pattern by making the following selections on the test box:
a.
b.
c.

Test mode
Write test
Forward run

Using an oscilloscope, observe the waveform at the first test point (Channel 3) on read preamp
(Figure 5-17).

Adjust the potentiometer adjacent to the test point for a sine wave of 9 V (±0.5 V) peak-to-peak.

Repeat this procedure for each of the remaining eight read preamplifiers.

5.5.3.13 Write Skew Adjustment - Although read and write heads share the same head assembly, they are not
perfectly parallel due to machining tolerances (Figure 5-21).

5-24

Part I
READIWRITE
MAGNETIC
HEAD
....- - - - - - - -...... - - - HEAD MOUNTING PLATE

TAPE MOTION

,
I

WRITE
HEADS

...Jt
I

READ
HEADS

ALL·' PATTERN ON TAPE

ALL - , PATTERN WITH

WITHOUT WRITE DESKEWING

WRITE DESKEWING

DEVIATION FROM PARALLELISM
INHERENT IN HEAD

08·1680

Figure 5-21 Skew Error (Caused by misalignment of
Read/Write heads)
After the mechanical read deskewing has been accomplished, the write heads are deskewed by providing appropriate electrical delays to each write channel.
NOTE
See Figure 5-3 for adjustments which must precede a write
skew adjustment.

With SCRATCH TAPE still mounted, make the following selections on the test box.
a.
b.
c.

Test mode
Write test
Forward run
This operation causes an all 1s pattern to be written on tape.

Attach the reference probe (channel No.1), of a dual channel oscilloscope, to test point p (parity
channel) board no. 6 (Figure 5-4).

Attach channel no. 2 test probe to test point 0 (read channel 0) on board no. 5.

Verify that the second read pulse has less than 1.7 J.LS separation from the reference channel, as shown
in Figure 5-22.
NOTE
The instability in the untriggered pulse is caused by
dynamic skew.

5-25

Part I

<1.7~s

---lI

DYNAMIC
SKEW

;"""or--"T"T- rl- -,

WRITE
SKEW

:::

I I

~--~

I I

I I
I I

300nl

I I
I I

I
I

I I

~--~~------~~~-~~--~-"p" CHANNEL REFERENCE
08-1677

Figure 5-22 Write Skew Adjustment

Repeat steps 3 and 4 for the remaining seven read channels. Channels 4 through 7 are located on an
identical PC board in slot 4. Make note of any channels that exceed the 1.7 #J,S tolerance.

If any channel has a pulse separation greater than 1.7 #J,S, power down and extend the appropriate
write amplifier card (channels 0 through 2 on card 2; channels 3 through 7 on card 1).

Restore power and test conditions, and adjust the appropriate four bit "DIP" switches for minimum
pulse separation. Note that each switch doubles the change of the previous switch. Switch S 1 provides
a 3.1 #J,S change while S4 provides a 25 #J,S change. A closed switch will move the corresponding pulse
to the left.

5.5.3.14 Ramp Time Adjustments - Tape acceleration and deceleration times must have close tolerances to
provide interrecord gap compatible with other tape drives.

With the scratch tape mounted, press FORWARD RUN on the test box to run the tape forward at
low speed.

Pull the test box toggle switch forward.

Attach the oscilloscope external trigger to red wire on the test box connector (Figure 5-2).

Observe test point "A" on the ramp generator card (Figure 5-4) for positive going RAMP (Figure 5-

23).
5.

Adjust Start Ramp Potentiometer for 30 ms ramp time.

Adjust Stop Ramp Potentiometer for 30 ms ramp time.

Power down and restore the drive to its original condition.

FORWARD MOTION

I
t

I
START - . j 30ms
RAMP

~ 30ms I - STOP

I.-

RAMP

08-1678

Figure 5-23 Ramp Time Adjustments

5-26

Part I

5.6 CORRECTIVE MAINTENANCE
Corrective maintenance information is provided to guide and aid the maintenance technician when isolating and
repairing faults. The information consists of five troubleshooting aids: the TMS-M diagnostics, the corrective
action flow diagram, the functional block diagram, TS03 transport troubleshooting hints, and TS03 transport
troubleshooting tables.
5.6.1 TM8-M Diagnostics
Diagnostics, consisting of a paper tape and documentation, are provided with each system. The documentatiolJ
includes instructions on loading, running, and interpreting diagnostic printouts. The diagnostics provided with
the TMS-M are listed in Table 5-4.
Table 5-4
TM8-M Diagnostics
Title

Designation

TM8-E/TS03 Control Test, Part 1
TM8-E/TS03 Control Test, Part 2
TM8-E/TS03 Data Reliability, 9-Track
TM8-E/TS03 Drive Function Timer
TM8-E/TS03 Utility Driver

MAINDEC-08-DHTSA
MAINDEC-08-DHTSB
MAINDEC-08-DHTSC
MAINDEC-08-DHTSE
MAINDEC-08-DHTSF

5.6.2 Corrective Action Flow Diagram
Figure 5-24 provides sequential procedures for troubleshooting the TMS-M.
5.6.3 Functional Block Diagram
Figure 1-4 functionally separates the circuitry comprising the three major units (TMS-E, MS920, TS03) into
functional blocks and depicts signal flow between those blocks within each unit; it also depicts interfacing
between each unit and interfacing between the TMS-E and the Omnibus. The functional block diagram can be
used in conjunction with Figure 5-24 for troubleshooting and maintenance.
5.6.4 TM8-E Controller Troubleshooting Hints
The diagnostics listed in Table 5-4 will test 'and troubleshoot all functions of the TMS-E Controller. By using the
diagnostics and the functional block diagram (Figure 1-4), troubles within the controller can be isolated and
repaired.
5.6.5 TS03 Transport Troubleshooting Hints
Table 5-5 suggests possible causes when problems are encountered with the transport.
5.6.6 TS03 Transport Troubleshooting Tables
Tables 5-6 and 5-7 list transport symptoms versus possible causes, indications, and corrective actions.
5.6.7 Troubleshooting Procedure
When problems are encountered in system operation, the technician should
I.

Discuss the symptoms with operation personnel to determine the exact nature of the failure.

Refer to the corrective action flow diagram (Figure 5-24) and proceed as directed.

5-27

USING TESTER,
ATTIEMPT
FAIl.ED
OPERATION

YES

TIMING DIAGRAMS
AND DETAIL LOGIC
TROUBLESHOOT TO FAUL TY
COMPONENT

REPLACE FAILED
MODULE OR
MECHANICAL
PART
REFER TO TRANSPORT TROUBLESHOOTING TABLES
5-5 ,5-6 AND 5-7
AND DETERMINE
TROUBLESHOOT
FAILED POWER
VI
I

COMPONENT

SUPPLY

'""
t:l

.....

REFER TO
FUNCTIONAL
BLOCK DIAGRAM
(FIGURE 1-41
AND TROUBLE
SHOOT TO
FAILED PART

VERIFY SYSTEM
OPERATION USING
DIAGNOSTICS AND
ONLINE OPERA
TION

MODULE
FAILURE

08-1683

Figure 5-24 TM8-M Corrective Action Flow Diagram

Part I
Table 5-5
TS03 DEC magtape Transport Troubleshooting Hints
Problem
General

Hints
Problems in the TS03 transport can usually be classified as either mechanical or
electrical but often the classification may be confusing because a basically
mechanical problem can cause what appears to be an electronic malfunction and
vice versa. In any case the problem should be thoroughly analyzed before
adjustments are made.
Electronic troubleshooting is greatly facilitated by the modular construction - a
new card may be substituted and the effect observed. Most difficult, of course,
are subtle problems and those of an intermittent nature.
Visualizing solution (Magna-See) is useful under certain conditions for
troubleshooting. At high densities the data cannot be satisfactorily resolved but
such problems as a dead track, improper gap length, etc., can be isolated rapidly
by its use.
If a tape has had visualizing solution applied to it, do not reuse that portion of
the tape as it will contaminate the head. Cut the visualized portion off and
discard.
To use visualizing solution, shake the can thoroughly, remove top, and pass
portion to be visualized through the solution. Snap the tape vigorously to
remove excess solution and let dry. Iron powder will be left in magnetized areas.
This can be picked off using Scotch tape and applied to a sheet of paper for a
permanen t record.

High Error Rate

Usually the more difficult problems involve a higher than permissible error rate
for which there is no obvious reason. If operating properly with good tape, the
transport should make very few errors in writing and, if rewriting is included in
the program, it should make no read errors.
Useful clues are:

In what mode (read or write) are many errors occurring?

At what point in the block does the error occur?

What is the nature of the error: VRC, CRC, LRC?

Are the errors pattern related?

Do errors occur only on certain sets of commands?

The first thing to be done is to inspect the head and other items in the tape path
for dirt accumulations. Be sure everything is clean. Check the tape being used
and try a new reel if tape is doubtful. Check interface connections for broken
wires or bad contacts. Table 5-6 is a troubleshooting chart concerned with high
error rate.

5-29

Part I
Table 5-5 (Cont)
TS03 DECmagtape Transport Troubleshooting Hints
I!ints

Problem
Compatibility

The IS03 transport accepts and produces tapes conforming to the ANSI
standards. Occasionally compatibility problems can arise:
1.

Tapes written by and acceptable to the TS03 transport are not
acceptable to another transport.

Foreign tapes cannot be read by the TS03 transport but its own
tapes can be.

Three items may be involved: skew, speed, ramp times. These should be
checked as described in the adjustment procedures.
Other Malfunctions

Normal troubleshooting procedures are involved in finding
malfunctions. The first things to check are the supply voltages:

electronic

±24 V nominal unregulated will normally be about ±26 V under light load.
±10 V ± 0.5 V
+5 V ± 0.25 V
Convenient test points for measuring supply voltages are:
+24 V - Case of Q9 (MJ802) on heat sink
-24 V - Case of QI0 (MJ4502) on heat sink
+10 V - Sensor amplifier/driver TPA
-10 V - Sensor amplifier/driver TPB
+5 V - Sensor amplifier/driver TPC
Voltages are measured to chassis (ground).
NOTE
Turn power off when removing or inserting cards.
If the voltages are not correct, the trouble is in the power supply or the
malfunction is loading the supply excessively. Pulling cards from their sockets
can help isolate an overloaded condition. The power supply is short-circuit
protected on the regulated voltages. A short circuit on +24 V should blow the
fuse. Assuming the voltages are correct, Table 5-7 should help in isolating
malfunctions.

5-30

Table 5-6
High Error Rate Troubleshooting
Indication

Action

Reference

Symptom

Possible Cause

Continuous errors, every block
(read mode).

Broken connection to interface or internally.

Continuity.

Correct connection.

Bad preamplifier channel.

No output at test point on
write test.

Replace preamplifier.

Bad quad read amplifier
channel.

No data at test point.

Replace quad read amplifier.

Tape speed grossly wrong.

Visual or skew master.

Adjust speed.

5.5.3.10

Bad head channel.

No output at preamplifier test
point on write test.

Replace head.

5.7.6

Broken connection on write
data or WDS lines.

Continuity.

Correct connection.

Bad write amplifier channel.

Wrong or no signal at write
amplifier test point in write
test mode.

Replace write amplifier.

Frequent write errors, few or
no read errors.

Write-read crosstalk.

Noisy signal at preamplifier
test point.

Check preamplifier gain.
Check head shield spacing.

Frequent CRC and LRC
errors, no VRC errors.

Wrong CRC generation in
interface.

Wrong data at input.

Correct interface.

Read or write errors only at
start of block.

Ramp time wrong.

Read signals appear before
ramp is complete.

Adjust ramp time.

5.5.3.14

Read errors on long blocks
only.

Tape path misaligned.

Tape bears heavily on one
gUide surface.

Tape Path alignment.

5.5.3.2

Pattern related errors.

Write-read crosstalk.

Noisy signal at preamplifier
test point.

Check preamplifier gain.
Check head shield spacing.

5.5.3.12
5.5.3.6

Continuous errors, write mode
only.

5.5.3.12
5.5.3.6

Table 5-7
Control Malfunctions Troubleshooting
Symptom
LOAD pushbutton activates servos
when pressed but does not hold.

After load, tape runs and does not
stop.

Possible Cause

Sensor amplifier driver module

Card cage

Replace module.

Pushbutton control module

Card cage

Replace module.

Photosensor (BKN) malfunction

Deck

Replace sensor.

Reference

Marker strip missing from tape.

Tape

Apply reflective strip.

Misadjustment of photosensor
on sensor amplifier driver
module.

Card cage

Adjust photosensor.

5.7.7

Tape feeds forward af1ter load point
marker is sensed.

Same as load point above but for
EOT.

REWIND pushbutton inoperative.

Logic malfunction, pushbutton
control module.

Rewind does not stop at LP but
continues until tape is wound off
reel.

Same as above.

Arms badly off center of arc at
rest.

Actioh

Broken tape Signal clears load
flip-flop.

No EOT signal.

Reels rotate uncontrolled when
power is turned on

Location

5.5.3.9

Card cage

Replace module.

Photosensor adjustment wrong on
sensor amplifier driver module.

Card cage

Adjust photosensor

Servo preamplifier malfunction.

Card cage

Remove preamplifier. If reels stop,
replace preamplifier module.

Servo power amplifier (bad power
transistors) .

Heat sink

Replace heat sink assembly or
locate and replace bad power
transistors.

Magpot adjustment.

Deck

Adjust magpot setting.

5.5.3.9

5.5.3.4

Table 5-7 (Cont)
Control Malfunctions Troubleshooting
Symptom

Possible Cause

Arms bottom when starting or stopping. Weak reel torque, otherwise
normal.

Servo preamplifier malfunction.

Card cage

Magpot adjustment (spacing).

Deck

Check adjustment.

Bad reel motor.

Deck

Replace reel motor.

Location

Action
Replace module.

Reference
5.5.3.4

Tape moves erratically, slips on
capstan.

Head face shield touching tape.

Deck

Adjust head shield setting.

5.5.3.6

Defective tension roller.

Deck

Replace roller.

5.7.1

Capstan turns slowly when it should
be stopped.

Capstan zero adjustment on servo
preamplifier module.

Card cage

Adjust zero.

5.5.3.3

Part I
5.7 PARTS REPLACEMENT
In most instances, assembly methods for parts replacement are obvious. Electronic parts are nearly all on plug-in
modules. Items in the transport tape path may require machine realignment if replaced. If only one item in the
transport tape path is replaced at a time, the complete alignment procedure may usually be avoided. Examples of
transport parts replacement follow.
Roller Guide Replacement (Figure 5-7)

5.7.1

Loosen the tape path alignment clamp sc~ew and remove the roller shaft from the tape tension arm.
Do not loosen the perpendicularity adjustment lockscrew.

Insert a new roller guide shaft and clamp lightly by tightening the clamp screw.

Follow the tape path alignment procedure of paragraph 5.5.3.2 to install and align the new roller
guide.

5.7.2 Tape Tension Arm Replacement
Tension arms are replaced by removing roller guides and disassembling. Do not attempt to remove the pin
holding the arm to its shaft; replacement assemblies are supplied pinned. Reassemble. the arm mechanism.

It will be necessary, if tension arms are replaced, to perform the complete tape path alignment procedure (Paragraph 5.5.3~2).
5.7.3 Reel Motor or Belt Replacement
1.

Unplug the motor and remove the motor and mounting plate.

Remove the motor from mounting plate. Replace with a new motor.

Hook the drive belt on the motor pulley and replace the screws holding the motor mounting plate to
the deck assembly.

Hold tension against the belt and tighten the mounting screws.

Check belt tension by squeezing between thumb and forefinger. The belt should deflect about 1/4 in.
(0.6 cm). If not, loosen the screws and move the motor.

Plug in the motor.

5.7.4 Capstan Motor Replacement.
1.

Remove the capstan lockscrew.

Remove the capstan. The capstan fits a taper on the motor shaft so it may be readily remo.ved once
loosened. It may require considerable force to break loose, however. Pullers are available for this use
but a screwdriver properly protected to prevent marring may be used to pry against the panel.

Remove the four capstan motor mounting screws. Unplug and remove the motor.

Install a new motor. Note if a red dot is present on the motor housing. If a dot is present, the motor
should be oriented to place the dot as near as possible to the outside end of the deck.

Adjust by procedure given under tape path alignment, Paragraph 5.5.3.2.

5-34

Parr I
5.7.5 Supply Hub Replacement
After Inng use. components in the quick-Iockinr, mechanism may become worn to the point that adju~tment of
locking pressure cannot securely hold the tape ree\. It is not necessary to replace the hub in its entirety: a hub
repair kit is included.
Repair kits consist of a replacement lock lever, thrust washer, and 0 ring. (See Replaceable Parts List, Part III,
Chapter 13.) To install:
I.

Remove the lock adjusting nut.

Pull the lock lever out.

Remove the thrust washer.

Replace the thrust washer.

Install a new lock lever and replace the adjusting nut.

I nstall a new 0 ring.

Adjust the hub for proper holding force. Verify using several different reels. Refer to Figure 5-25 for
more detailed adjustment procedures.

HUB
BEARING CARRIER

DECK PANEL

HUB
ADJUSTING NUT

~I----- DRI VE

HUB
HEIGHT SHIMS

HUB

4--

.305(REF)

PULLEY

NOTES:
11-3052
1. Loosen hub adjustment nut.
2. Open hub, install tape reel.
3. Close hub. Tighten hub adjusting nut until 0 ring presses firmly against reel.
4. Check for slippage under torque by holding hub or drive pulley. Reel should not slip on hub.
5. Open and close several times and recheck for slippage.
6. Try several reels, checking for slippage.

Figure 5-25

Reel Hub Adjustment

5-35

Part I
5.7~6

Magnetic Head Replacement
Replacement heads are supplied as complete assemblies together with mounting plate and face shield. A write
deskewing chart is supplied with each head.
1.

Unplug the head connectors.

Remove the head mounting screw and remove the head, passing connectors through the panel hole
provided.

Be sure the adjusting screw on the replacement head is almost completely unscrewed.

Mount a new head with the mounting screw fairly loose. Screw in adjusting screw until point protrudes enough to engage its conical locating hole. Tighten the mounting screw.

Plug in the head.

Deskew the read head as described in the deskew adjustment procedure (Paragraph 5.5.3.11).

Set the deskewing switches on the write amplifiers to correspond to the chart supplied.

Place the chart over the old chart to record switch settings.

5.7.7 Photosensor Replacement
1.

Remove the photosensor assembly by unplugging and removing the mounting screws. Since it will not
pass through the hole provided, the connector must be removed by cutting the cable. Retain the
connector.

Replacement sensors are provided with connector pins crimped to wires but with no connector shell
installed.

Replace the assembly, passing the wires through the hole provided. Replace the screws.

Snap pins into the connector shell in the same color sequence as in the shell just removed; plug in the
assembly.

Adjust as described in adjustment procedure.

5.7.8 Magpot Replacement (Figure 5-11)
1.

Unplug the magpot assembly from its cable.

Remove the rotor by loosening the set screw.

Remove the screws holding the magpot PC board and remove the assembly.

Install a replacement unit.

Adjust the magpot according to Paragraph 5.5.3.4.

5-36

Part I
5.7.9 Tape Cleaner Replacement
1.

Remove the circular snap-in plug cover.

Remove the mounting screw and tape cleaner.

Mount a new cleaner assembly with the mounting screw finger-tight.

Adjust the cleaner surface so that it just touches the tape and is parallel to the tape surface.

Tighten the mounting screw and install the snap~in plug cover.

5-37

PART II
TM8-E CONTROLLER

CHAPTER 6 INTRODUCTION
CHAPTER 7 BLOCK DIAGRAM DESCRIPTION
CHAPTER 8 PROGRAMMING INFORMATION
CHAPTER 9 DETAILED LOGIC DESCRIPTIONS

APPENDIX F

TM8-E INTERFACE AND INTERNAL SIGNALS

APPENDIX G

SPARE PARTS

APPENDIX H

IC DESCRIPTIONS

Part II

CHAPTER 6
INTRODUCTION

6.1

GENERAL DESCRIPTION

The TM8-E DECmagtape Control interfaces the PDP-8/ A, E and M with the TS03 Transport (Figure 6-1).

~----I
ON THE
OMNIBUS

U
S

TS03S
SLAVE
TRANSPORT

I
I
I

0
M
N
PDP-B
COMPUTER

TMB-E
DECMAGTAPE
CONTROLLER

MB920
ADAPTER

I
I
I

TS03S
SLAVE
TRANSPORT

TS03M MASTER
TRANSPORT

_____ -1

08-1684

Figure 6-1

TM8-M Block Diagram

To perform this function, the TM8-E:
1.

Decodes programmed instructions.

Accepts and stores word count, current address, command, and function words.

Selects a program-designated transport (two maximum in the system) and starts the operation designated by the program.

Generates break requests to initiate a single cycle data break.

Generates interrupts and skips for flag checking.

Buffers the input/output data and controls the writing on the 8 LSBs of a 12-bit word on 9-track
transports.

6-1

Part II
7.

Performs housekeeping chores for single cycle data breaks, i.e., increments Word Count and Current
Address Registers.
. .

Provides Error and Job Done flags.

Provides lOTs for TM8-E maintenance.

6.2 PHYSICAL DESCRIPTION
The following quad modules comprise the TM8-E:
M8321 Output Control Module
M8322 Control and Data Break Module
M8323 Transport Status and Control Module
M8327 Registers Module
These quad modules must be inserted into the Omnibus and connected together via HS51 edge connectors. Two
7011571 cables are used to connect the TMS-E (input and output) to the TS03. The TMS-E receives +5 V logic
power from the PDP-S Omnibus. No power is supplied to or received from the TS03 by the TMS-E or PDP-S.

6-2

Part II

CHAPTER 7
BLOCK DIAGRAM DESCRIPTION

7.1 INTRODUCTION
Figure 7-1, a block diagram of the TMS-E DECmagtape Control, depicts the flow of signals among the modules,
Omnibus, and the TS03 DECmagtape and slave. The modules are inserted into the Omnibus and signals are
carried between the modules by HS51 edge connectors. The TMS-E is connected to the TS03 DECmagtape by
two 7011571 cables. The TMS-E modules are described in the following paragraphs.

TM8-E REGISTER MODULE
(M8327)
(1) DATA REGISTER
MAOO-MAll (2) COMMAND REGISTER
(3) FUNCTION REGISTER
MDOO-MDll (4) WORD COUNT
REGISTER
(5) CURRENT ADDRESS
REGISTER
(6) BUFFERED COMMAND
REGISTER

EMAOO-EMA02.

TM8-E TRANSPORT
STATUS AND CONTROL
MODULE (M8323)
READ DATA
(1) MAIN STAUS REGISTER
(2)SECOND STATUS
CON ROLS
REGISTER
(3) CONTROL LOGIC
.-- (4) ERROR FLAG

STATUS TO AC

M
N
I
8
U

'""- (M8322)
~

(1) FUNCTION DECODER
(2)PRIORITY LOGIC
(3) DATA BREAK CONTROL
LOGIC
(4)INTERRUPT LOGIC
(5) CONTROL LOGIC
(6) JOB DONE FLAG
(MTTF)

CONTROLS

TRANSPORT

WRITE DATA

TS03M
STATUS
DECMAGTAPE
WRITE DATA
TRANSPORT

TS03S
SLAVE
READ DATA TRANSPORT

TM8-E OUTPUT CONTROL
MODULE (M832l)
TRANSPORT
(1) INSTRUCTION
CONTROL
DECODER
(2)FUNCTION DECODER
(3)SKIP LOGIC
(4) READ COMPARE LOGIC

TM8-E CONTROL MODULE

READ
DATA

STATUS

DATA 00- DATA 11
08 -1670

Figure 7-1

TM8-E Block Diagram

7.2 M8321 OUTPUT CONTROL MODULE
The MS321 Output Control module comprises three lOT instruction decoders, a function decoder,
read/compare error detection logic, buffers, gating logic to multiplex data to be written on DECmagtape during
a write operation, and skip logic.
7.2.1 lOT Instruction Decoder
The three decoders (device codes 70, 71, and 72) provide control signals in response to the lOT instructions. The
lOT decoders generate control signals that are distributed to the logic of the other TMS-E modules to control
data transfer between the TS03 and core memory. The control signals also control the loading and reading of
TMS-E Registers and enable the error detection logic to monitor data transfer operations.

7-1

Part II
7.2.2 Function Decoder
The function decoder receives three function bits from the Function Register and decodes them to select one of
the following DECmagtape functions (Paragraph 7.3.3).

Offline
Rewind
Read
Read/Compare

Write
Write End-of-File
Space Forward
Space Reverse

The function signals generated by the function decoder are sent to the TS03 master to control the selected
DECmagtape transport.
7.2.3 Gating Logic
The WD bits are gated to the Write Data Buffers in response to control signals from the TM8-E control module
and transferred to the TS03. Data is written in 9-bit characters (8 data bits plus parity). Parity for each character
is generated in the TS03 master.
7.2.4 Read/Compare Error Detection Logic
The read/compare error detection logic compares data read from the DECmagtape with data in memory during
the break cycle and generates a read/compare error if the data is different. This operation is accomplished by
Exclusively-Oring the memory data with the data read from the DECmagtape. Note the parity bit is not checked
by read/compare.
7.2.5 Skip Logic
The skip logic grounds the skip line and causes the program to skip the next instruction when the following
conditions exist:
1.
2.
3.

Tape Unit Ready (TUR) and an SKTR instruction is executed by the program.
ERROR flag is set and an SKEF instruction is executed by the program.
Control not busy and an SKCB instruction is executed by the program.
JOB DONE (MTTF) is set and an SKJD instruction is executed by the program.

This logic is used by the programmer for flag and error checking operations.
7.3 M8327 REGISTERS MODULE
The M8327 Registers module contains all of the TM8-E registers except the Main Status Register and Second
Status Register. Each of the registers on the M8327 module is described in the following paragraphs.
7.3.1 Multiplexer and Data Register
The Multiplexer and Data Register stores information to be multiplexed to or from the transport or Omnibus. It
accomplishes this task in the following manner:

1.
2.
3.
4.

It receives data to be written on tape from the MD lines during a write break cycle.
It receives data from the AC via lOT instructions.
The Omnibus receives data from the tape transport during a read operation via the Data Bus.
The Data Register receives data from the tape transport.
The master system receives data from Data Buffers during a write break cycle.

7-2

Part II

7.3.2 Command Register
The Command Register (Figure 7-2) is loaded with a 12-bit word from the AC by an LCMR instruction. The
Comm and Register is used to select a tape transport (0-7), * enable or disable interrupts, select parity mode (odd
or even), select memory field, and select DECmagtape recording densities. The contents of the Command Regis. ter are transferred to the AC for ,program evaluation by an RCMR instruction.

SEL~CTION J

UNIT
TRANSPORT 0- 7

'J J

PARITY: 0= EVEN
1 = ODD

LDEN 5

DEN 8

SEL 16 (UNUSED)

EXTENDED MEMORY,
ADDRESS 2 (EMA 2)

I NTERRUPT ENABLE ON
ERROR FLAG (IEEF)

EXTENDED MEMORY,
ADDRESS 1 (EMA 1)

INTERRUPT ENABLE
ON MAGTAPE FLAG
(MTTF) (JOB DONE) (IEMF)

EXTENDED MEMORY,
ADDRESS 0 (EMA 0)
8E-0614

Figure 7-2

Contents of Command Register

7.3.2.1 Buffered Command Register (BCM) - The Buffered Command Register is loaded with SEL 0 through
SEL 2 when LBCM is asserted by the control logic. The output of BCM (B SEL 0 through B SEL 2) is compared
with SEL 0 through SEL 2 to determine when a new transport has been selected by the program. If the program
selects a new transport, CHG TRANS is asserted to inform the controller that a new transport has been selected.
LBCM is asserted when the following conditions exist:
I.
2.
3.

The CHG TRANS flip-flop is set and the Rewind Status from the selected transport is asserted.
CLR ALL is asserted.
At TP4 time, if anyone of the following conditions exist:
a.
C TUR L asserted.
b.
C SDWN L asserted.
c.
C SELR L negated.

7.3.3 Function Register
The Function Register (Figure 7-3) is loaded from the AC by an LFGR instruction. The three most significant
bits (F0-2) are decoded by function decoders in the M8321 Output Control module and the TM8-E M8322
Control module to select the following DECmagtape functions.
Offline

Selected transport is taken 0 FFLINE and rewound to beginning of tape (BOT).

Rewind

The selected transport rewinds to BOT at 75 in./sec and stops.

Read

Data is transferred from tape to memory in the forward direction only.

Read/Compare

Data read from the tape is compared to data in core memory; if there is a comparison
error, the Current Address (CA) Register stops incrementing and the CA Register
holds the memory address in error at the end of the operation.

*0-1 for TMS-M.

7-3

ParI II

I I I I I I I I I I
1

FU~CTIONJ

SEL ECTION
000
001
010
011
100
101
110
111

OFF LINE
REWIND
READ
READ ICOMPARE
WRITE
WRITE FILE MARK
SPACE FORWARD
SPACE REVERSE

L
L

EMA INC

LUNUSED
ENAB~,.E

GO WHEN EOUAL
TO A ONE

ENABLE CHECK
CHARACTER
EXTEND GAP

8E-0613

Figure 7-3

Contents of Function Register

Write

Data is written on tape in the forward direction only.

Write End-of-File

The transport leaves a 3-inch (7.62 cm) gap and writes a File Mark that consists of one
character followed by three character spaces and an LRC character.

Space Forward

The transport moves forward, at 12.5 ips, the number of records specified by the Word
Count (WC) Register (Paragraph 7.3.5). If File Mark is encountered, the transport
stops at IRG; if EOT is encountered, the transport stops at the next IRG.

Space Reverse

The transport spaces in reverse, at 12.5 ips, the number of blocks specified by the WC
Register. If at the beginning of tape (BOT) a File Mark is encountered, the tape stops.

The remaining bits of the Function Register enable the following operations ifthey are set by a 1 from the AC.
Extended Gap

If bit 3 is aI, there is a 3-inch (7.62 cm) gap between records. This bit is used only
during write functions.

Enable Check
Character

If bit 4 is a 1 and a 9-track transport is selected, the LRC and CRC are transferred to
memory at the end of a record during read operations. This operation is accomplished
by executing two more data breaks after the WC Register overflows. Record Length
Incorrect is disabled at this time.

When bit 5 is aI, the controller asserts GO, sets CNTL BSY (Control Busy), generates
PRESET, and if no illegal functions exist, SET is asserted to start an operation. A GO
command is issued to the transport ifit is ready (TUR is true, and SELECT REMOTE
is low).

EMA INC Enable

If bit 6 is a 1, the EMA bits in the Command Register and the CA Register are used as a
IS-bit register to address the PDP-8 core memory as a block instead of in 4K segments.

Continuous Operation

The MTTF (JOB DONE) signifies the end of a specified operation. If an LFGR
instruction is desired immediately, prior to TUR, this instruction may be executed by
the program.

7-4

Part II

7.3.4 Current Address Register
The CA Register is loaded from the AC by an LCAR instruction with a memory address that is one location less
than the desired starting memory location. The CA Register is incremented before each data transfer to sequentially address a block of memory during a data transfer operation. The contents of the CA Register are placed on
the MA lines during a single cycle data break to address memory.

7.3.5 Word Count Register
The WC Register counts the number of words in a block of data transferred to or from memory by the TM8-E.
The 2s complement of the number of words to be transferred is loaded into the WC Register by an LWCR
instruction at the beginning of a data transfer. The WC Register is incremented before each data character is
transferred until the WC Register contains all Os, causing an OVERFLOW. When the WC Register overflows,
data transfer is stopped. This register is also used in spacillg operations to count records to be spaced over.

7.4 M8323 TRANSPORT STATUS AND CONTROL MODULE
The TM8-E transport status and control logic contains the majority of the Main Status Register, the second
Status Register, the error detection logic (ERROR flag), an illegal function detection logic, and receives read
data (RDO-RD7) from the TS03 master before it is applied to the Data Register.

7.4.1

Main Status Register

The Main Status Register (Figure 7 -4) retains transport status information that is transferred to the AC by an
RMSR instruction for evaluation by the program.

ERROR FLAG
TAPE REWINDING

BEGINNING OF
TAPE (BOT)
SELECT REMOTE

LRE: ;~:Ef!~L~N
ERROR

FI LE PROTECT

END OF TAPE (EOT)

PARITY ERROR (VERTICAL,
LRC, OR CRC ERROR)

DATA REQUEST LATE
RECORD LENGTH
INCORRECT

FILE MARK (EOF)

8 E- 0612

Figure 7-4

Contents of Main Status Register

7.4.2 Second Status Register
The Second Status Register (Figure 7-5) retains additional transport status information that is transferred to the
AC by an RFSR instruction for evaluation by the program.

7-5

Part II

I14,........-----

FUNCTION
SECOND STATUS
J
REGISTER BITS --~.....
,. ----REGiSTER BITS ~

FU~CTION ~

000 OFF LINE
001 REWIND
010 READ
011 READ COMPARE
100 WRITE
101 WRITE FILE MARK
110 SPACE FORWARD
111 SPACE REVERSE

LLONGITUDINAL
PARITY ERROR

CRC ERROR

LATERAL
PARITY ERROR

EMA I NCREMENT ERROR

EXTENDED GAP
ENABLE CHECK
CHARACTER

NOT USED
TRANSPORT CHANNEL
(9 CH = 1 )
GO BIT (1)
8E- 0611

Figure 7-5

Contents of Function and Second Status Register

7.4.3 Error Flag
The Error flag is set by anyone of the following error conditions:
End of Tape (EOT)
Read/Compare (R/C) ERROR
Parity Error
Beginning of Tape (BOT)
EMA 7 INC ERR
Record Length Incorrect
Data Late
Illegal Function
File Mark
7.4.4 Illegal Function Detection
The Illegal Function flag sets, setting the Error flag, if any of the following are attempted:

A rewind is attempted when tape is at BOT.

A space reverse is attempted when tape is at BOT.

An attempt is made to select other than 800 bpi density on 9-track transports.

An attempt is made to read after write on the same transport.

lOTs are executed to load the Data Buffer Register, Command Register, or Function Register while
the control is busy.

7-6

Part II

Issue a write or write File Mark to a tape transport with the write ring removed.

An attempt is made kl start an operation when the following conditions exist:
a.
b.
c.

CH G TRANSPORT L is true.
TUR H is true.
PRESET is true.

7.4.5 PRESET and SET Pulse Generator
PRESET is a fixed delay which is generated to allow adequate time for interrogation of the control to check for
errors and illegal functions prior to asserting the SET pulse. If there are no illegal functions or errors, the SET
pulse is asserted, thus asserting the C SET H signal to the tape transport and starting tape motion.
7.4.6 Control Busy (CNTL BSY)
CNTL BSY is set when the GO bit is issued to indicate that an operation is pending.
7.5 M8322 CONTROL AND DATA BREAK MODULE
The MS322 Control and Data Break module comprises the data break control logic, a control function decoder,
and the interrupt logic.
7.5.1 Data Break Control Logic
The data break control logic allows the TMS-E to transfer large blocks of data between the TS03 Master and
memory. When the TMS-E asserts BRK RQST, a priority check is made by the controller. A priority network on
the MS322 module is compared with priorities of other peripherals requesting a data break and, if the TMS-E has
the highest priority, the break control allows the TMS-E to assert the break control lines. This action enables the
TMS-E to assume control of the CP Major Register gating and to address memory using the current address
logic and data break control logic. When BRK RQST is granted by the TMS-E, data is transferred from the
TMS-E Data Register to the Data Bus (read) or from the MD lines to the MS321 Output Control module (write
or read/compare). The TMS-E is capable of one Single Cycle Data Break approximately every 100 p-s until a
complete record is transferred to or from memory. The CRC and LRC characters are also transferred to memory
during a read operation if the ENABLE CHECK CHARACTER bit in the Function Register is set.
7.5.2 Function Decoder
The control function decoder decodes FRO-FR2 from the Function Register and generates the same function as
the output control function decoder on the MS321 Output Control module (Paragraph 7.2.2). The outputs of this
function decoder are applied to the control logic on the control module. The FRO-FR2 function bits are applied
to the control function decoder from the Function Register.
7.5.3 Interrupt Logic
The interrupt logic on the TMS-E control module generates an interrupt request (lNT RQST) when the following conditions exist (Table 7-1):
1.
2.

Bit 4 in the Command Register (lEEF) is set (1) and the Error flag is set.
Bit 5 in the Command Register (lEMF) is set (1) and the Job Done flag (MTTF) is set.

7-7

Part II
Table 7-1
Command Register Contents and Function
Function

Bit No.
Bits 0,1, and 2
SELO
(Bit 0)

SEL 1
(Bit 1)

SEL2
(Bit 2)

0
0
0
0
1
1
1

0
0
1
1
0
0
1

o
1

Transport 0
Transport 1
Transport 2
Transport 3
Transport 4
Transport 5
Transport 6
Transport 7

TM8-M System has a maximum
of two transports.

Bit 3

0= Even parity; 1 = Odd parity

Bit 4

If bit 4 is ai, enable interrupt Error flag.

Bit 5

Enable interrupt on JOB DONE (MTTF) if bit 5 is a 1.

Bits 6, 7, and 8

Extended memory address (EMA) , these bits
determine which memory field the controller uses for
data transfer operations during a Data Break.
Function Register bit 6 (Table 8-1) determines if the
EMA address is to be incremented or used in the
Wrap-around mode.

Bit 6
(EMAO)

Bit 7
(EMA 1)

Bit 8
(EMA 2)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Bit 9

Field 0
Field 1
Field 2
Field 3
Field 4
Field 5
Field 6
Field 7
Reserved for future use.

7-8

Part II
Table 7-1 (Cont)
Command Register Contents and Function
Bit No.
Bits 10 and 11

Function
Density bits, these bits select the density for tape
transport operation and are referred to as Den 8 (bit
10) and Den 5 (bit 11).

Bit 10
Den 8

Bit 11
Den 5

0
0
1
1

0
1
0
1

200 bpi, 7-track (Not used)
556 bpi, 7 -channel (Not used)
800 bpi, 7-channel*
800 bpi, 9-channel

*This mode is also referred to as Core Dump Mode. When this command is issued to a 9-track transport, zeros are
written on tracks 0 and 1 of the DEC magtape and the 9-track transport operates as a 7-track transport.

7-9

Part II

CHAPTER 8
PROGRAMMING INFORMATION

8.1 INTRODUCTION
This chapter describes the instructions used to program the TM8-E and the register bits associated with each
instruction. The single cycle data break data transfer operation is also described. Programming notes and examples are provided.
8.2 INSTRUCTIONS AND REGISTER BITS
The following instructions are used to program the TM8-E. Refer to the appropriate table for the register bits
associated with each instruction.

Load Word Count Register (L WCR)
Octal Code:

6701

Operation:

Loads the WC Register with the contents of the AC (Figure 8-1) and clears the AC. The
WC Register should not be loaded when the control is busy. If the register is loaded
during CNTL BSY, data reliability and tape compatibility are not ensured. The WC
Register is loaded with the 2s complement of the number of words to be transferred or
number of blocks to be spaced. The WC Register is incremented at TPI of a data break
cycle during data transfers, at LRCS during a space forward, or at the first word of a
record during a space reverse operation.
RE-2 weo H

RE-2 DATA 0 L
RE-2 DATA 1 L
RE-2 DATA 2 L
RE-2 DATA 3 L
RE-2 DATA 4 l
WORD
COUNT
REGISTER

DATA
BUS
GATING

RE-2 DATA 5 l
RE-2 DATA 6 l
RE-2 DATA 7 L
RE-2 DATA 8 l
RE-2 DATA 9 l
RE-2 DATA 10 l

(RE-2)
OC-2 BTP3 H

Figure 8-1

RE-2 DATA 11 l

(RE-2)
ClK

(RE-2)

OC-2
lWCR l

oe-2
RWCR L

LWCR and RWCR Instruction Data Flow
8-1

8E-0703

Part II
Clear Word Count Register (eWeR)
Octal Code:

6702

Operation:

Clears the WC Register. This instruction is used primarily in maintenance operations
and should never be used during CNTL BSY.

Load Current Address Register (LeAR)
Octal Code:

6703

Operation

Loads the CA Register with the contents of the AC (Figure 8-2) and clears the AC. The
CA Register is loaded to one less than the memory address of the first word to be
transferred. If this instruction is executed during CNTL BSY, one of the following
occurs:
1. In the Wrap-around Modes (Function bit 6 = 0), the location of the data transfer
cannot be ensured within the selected memory field.
2. In the EMA INC ENABLE Mode (Function bit 6 = 1), the location of the data
transfer cannot be ensured within memory.
The CA Register is incremented at each BRK RQST.

RE-2 CAO H

RE-1 BACO

RE-2 DATA 0 L

RE-1 BAC1

RE-2 DATA 1 L

RE-1 BAC2

RE-2 DATA 2 L

RE-1 BAC3

RE-2 DATA 3 L

RE-1 BAC4

RE-2 DATA 4 L

RE-1 BAC5
RE-1 BAC6

HOLDING
BAC

CURR
ADDR
REGISTER

DATA
BUS
GATING

RE-2 DATA 5 L
RE-2 DATA 6 L

RE-1 BAC7

RE-2 DATA 7 L

RE-1 BAca

RE-2 DATA a L

RE-1 BAC9

RE-2 DATA 9 L

RE-1 BAC10

RE-2 DATA 10 L

RE-1 BAC11
(RE-2)
OC-2 B TP3 H

RE-2 DATA 11 L

(RE-2)
CLK

(RE-2)

OC-2
LCAR L

OC-2
RCAR L
8E-0704

Figure 8-2

LCAR and RCAR Instruction Data Flow

8-2

Part II
Clear Current Address Register (CCAR)
Octal Code:

6704

Operation:

Clears the CA Register. This instruction is used primarily for maintenance and should
never be used during CNTL BSY.

Load Command Register (LCMR)
Octal Code:

6705

Operation:

Loads the Command Register w;th the contents of the AC and clears the AC (Figure 83). This instruction must not be issued during CNTL BSY. The LCMR instruction
selects tape transport, Parity Mode, memory field, recording densities, and enables or
disables interrupts (Table 7-1 and Figure 7-2).
OC-2 LCMR

OC-2 RCMR

RE-I BACO ,-.--L-----, RE-I SELO H

RE-l BSELO H

DATA I L

RE-l SEll H

~g~ RE-I BSEL I H

DATA 2 L

RE-ISEL2H

REG
(RE-t) RE-l BSEL2 H

DATA 0 L

COMMAND

)....---<~~ REGISTER

DATA 3 L

RE-I IEEF H

DATA 5L

RE-I IEMF
OC-2 LCMR

DATA 6 L
HBAC

DATA 8L

(RE-I)

RE-l DATA 2 L
-RE-I DATA 3 L
RE-I DATA 4 L

RE-I CEMAO H

DATA 7 L

RE-I DATA I L

RE-I PEVN H

DATA 4 L
(RE-I)

RE-I DATA 0 L

PIO
COMMAND
REGISTER

(RE-2)

RE-I DATA 5 L

DATA
BUS
GATING

RE-I DATA 6 L

RE-I CEMAI H

RE-I DATA 7 L

RE-I CEMA2 H

RE-I DATA 8 L

RE-I SELl6 H

DATA 9L
PIO
COMMAND
REGISTER

DATA 10 L
DATA II L

IRE-I)

OC-2
AC ENABLE

RE-I DATA 9 L

RE-I SEL 8 H
RE-I DEN 5 H

RE-I DATA 10 L
(RE-I)

OC -2
LCMR

RE-l DATA II L

EMAO L}
EMAIL

BRK
FIELD

EMA2 L
CB-2 MACI H
8E- 0709

Figure 8-3

LCMR and RCMR Instruction Data Flow

Load Function Register (LFGR)
Octal Code:

6706

Operation:

Loads the Function Register with the contents of the AC and clears the AC (Figure 84). The Function Register is the last register loaded because it contains the GO bit. This
instruction determines the function the transport is to perform (Table 8-1 and Figure 73).

8-3

Part II
(6716)
OC -2 LFGR

OC-2 RFSR L

1
RE-' BACO

RE-' FR 0 L

RE-' DATA 0 L

RE-' BAC1

RE-' FR , L

RE-' DATA' L

RE-' BAC2

RE-' FR 2 L

RE-' DATA 2 L

RE-' BAC3

RE-1 DATA 3 L

RE-' FR 3 L

FUNCTION
REGISTER

RE-' BAC4

ENABLE CHECK CHAR L

RE-' BAC5

RE-' GO L

RE-' BAC6

RE-' EMA INC

DATA
BUS
GATING

RE-' DATA 4 L
RE-' DATA 5 L

SC-, 7 CHAN+ DEN 5 L

RE-, DATA 6 L

ENABLE L

(RE-1l

NOT USED

RE-' DATA 7 L
(RE-2)

-----se-2 DATA 8 L

se-, EMA 7 INC

se-2 DATA 9 L

SC-2 VP ERROR H
DATA
BUS
GATING

SC-2 eRe ERROR H
se-2 LRe ERROR H

SC-2 DATA' 0 L
SC-2 DATA 11 L

(Se-2)

0':-2 RFSR L
(67'6)
8E-0710

Figure 8-4

LFGR and RFSR Instruction Data Flow

Table 8-1
Function Register Contents and Functions
Bit No.

Function

Bit 0,1, and 2

Function Selection: These bits determine
function the transport is to perform_

Bit 0

Bit 1

Bit 2

the

Offline: The selected transport is taken offline and
rewound to BOT. The MTTF is set when the
transport responds to this function and the controller
can select and use another transport. The transport
must be manually reset to the on-line state. The WC
and CA Registers neea not be loaded.
Rewind: The transport rewinds at high speed (75
in/sec) to BOT and stops. The MTTF is set when the
transport responds to the Rewind function. The
controller can select and use another transport. The
WC and CA Registers.need not be loaded.

8-4

Part II
Table 8-1 (Cont)
Function Register Contents and Functions

Bit No.

Function

Bit 0, 1, and 2 (Cont)

Bit 0

Bit 1

Bit 2

Read: Data is transferred from the tape to memory
in the forward direction only. All registers must be
loaded.

Read/Compare: Tape data is compared to data in
core memory. All registers must be loaded. If there is
a comparison error, CA incrementation ceases, the
RIC ERROR bit is set, and tape motion continues to
the end of the record. The CA Register contains the
address of the word that produced the error.

Write: Data is written on the tape in the forward
direction only. All registers must be loaded. The write
function is controlled by WC OVERFLOW (which
disables the write); the transport writes the
appropriate check characters to end the block.

Write End-of-File (File Mark): The transport writes
the File Mark, which consists of a one word record.
The CA and WC Registers need not be loaded.

Space Forward: The tape moves forward at 12.5 ips
the number of records specified by the WC Register,
or until a File Mark is read. If EOT is read, space
forward stops at the first interrecord gap. The CA
Register need not be loaded for space forward to
occur.

Space Reverse: The tape moves in the reverse
direction at 12.5 ips the number of blocks
specified by the WC Register, or until a File Mark or
BOT marker is read. The CA Register need not be
read during a space reverse.

Bit 3

Extended Gap: When bit 3 is aI, the transport
writes with an additional 3-inch (7.62 cm) gap
between records.

8-5

Part II

Table 8-1 (Cont)
Function Register Contents and FWlctions
Function

Bit No.
Bit 4

Enable Check Character: When this bit is set (1), it
allows the check characters to be read into the
computer during a read function. When the word
count overflows, this bit allows two breaks for the
CRC and LRC to be transferred to memory. If a
record length incorrect error occurs, the check
character is considered bad and is not used. nus bit is
used primarily for error correction.

Bit S

Go: This bit causes the controller to issue a set
command to the transport when the transport is
capable of accepting it. The set command is not
issued if the specified function is illegal.

Bit 6

EMA INC Enable: If this bit is not set (0), the
TM8-E (like all other PDP-8 data break options)
treats the extended memory the same way, i.e., each
4K block is used in a Wrap-around Mode. If this bit is
set (1), the extended memory is treated as a
continuous memory rather than 4K blocks. When the
last location in one field is reached, the EMA bits are
incremented and the transfer continues in the next
field; i.e., if a word is placed in Field 2, location
7777, the following word is placed in Field 3,
location 0000 if the EMA increment bit is set. If bit 6
is not set, the word is placed in Field 2, location
0000.
In both modes of operation, the current address is set
to one less than the first location to be accessed. In
EMA increment mode, the 12-bit CA Register and the
three EMA bits are treated as one IS-bit register with
the EMA bits most significant. For example, to access
Field 2, location 20, load EMA =2 and CA =0017;
to access Field 2, location 0, load EMA = 1 and
CA = 7777. If Field 7 is selected, the EMA cannot
increment, but wraps around in Field 7 and an EMA
7 INCREMENT ERROR occurs.

Load Data Buffer Register (LDBR)

Octal Code:

6707

Operation:

Loads the Data Buffer Register with the contents of the AC, clears the AC, and sets the
MTTF flag (Figure 8-5). This instruction is used for maintenance purposes.

8-6

Part II
RE-l DBC2 L

b
RE-l BAC 0 H

RE-3 MPX 0 H

RE-l DB 0 H

RE-l DATA 0 L

RE-l BAC 1 H

RE-3 MPX 1 H

RE-l DB 1 H

..... RE-l DATA 1 L

RE-l BAC2

RE-3 MPX 2H

RE-I DB 2 H

RE-l DATA 2 L

RE-l BAC3

RE-3 MPX 3H

RE-1DB3H

RE-l DATA 3L

RE-l BAC4

RE-3 MPX4 H

RE-1DB4H

RE-3 MPX 5 H

RE-1DB5H

RE-1BAC5

MU LT I PLEXER

RE-I BAC6 H

RE-3 MPX 6 H

DATA
- - -BUFFER---

RE-l DB 6H

RE-l DATA 4L
DATA
BUS
GATING

RE-l DATA 5L
RE-l DATA 6L

RE-1BAC7H

RE-3 MPX 7 H

RE-l DB7H

RE-l DATA 7 L

RE-l BAC8 H

RE-3 MPX 8H

RE-1DB8H

RE-l DATA 8 L

RE-l BAC9 H

RE-3 MPX 9H

RE-l DB9 H

RE-IDATA9L

RE-l BAC 10 H

RE-3 MPX 10H

RE-1DB10H

RE-l DATA 10L

RE-l BAC 11 H

RE-3 MPX 11 H

RE-l DB 11 H

RE-l DATA 11 L

(RE-3)

IRE-I)

CB-2 MPX
A

CB-2 MPX
B

I
CB-2 DBCl L

(RE-l)

OC-l ROB
8E-0707

Figure 8-5

LDBR and RDBR Instruction Data Flow

Read Word Count Register (R WCR)

Octal Code:

6711

Operation:

Clears the AC and transfers the contents of the WC Register into the AC (Figure 8-1).
This instruction is used primarily for maintenance, but it can also be used during error
check routines.

Clear Transport (CLT)

Octal Code:

6712

Operation:

Clears the transport master registers and all TM 8- E registers and flags.

Read Current Address Register (RCAR)

Octal Code:

6713

Operation:

Clears the AC and transfers the contents of the CA Register to the AC (Figure 8-2).
This instruction is used primarily for maintenance, but it can be used for error check
routines.

Read Main Status Register (RMSR)

Octal Code:

6714

Operation:

Clears the AC and transfers the contents of the Main Status Register to the AC (Figure
8-6). The 12-bit Status Register contains the status of the transport and control logic
(Table 8-2 and Figure 7-4) ..

8-7

Part II
Table 8-2
Main Status Register Contents and Indications
Bit No.

Status Indication

Error: The Error flag interrupts the processor if bit 4 in the Command Register is set (1).
An ILLEGAL FUNCTION or SELECT ERROR sets the MTTF flag immediately and stops
data break operations. The following errors, if they occur during any operation, set the Error
flag after the MTTF flag is set.
BOT
EOT
READ/COMPARE ERROR
Parity Error (VPE, CRCE, or LRCE)
RECORD LENGTH INCORRECT
File Mark (EOF)
DATA LATE
EMA 7 INCREMENT ERROR

Rewind Status (RWS): A 1 indicates the selected transport is rewinding.

Beginning of Tape (BOT): A 1 indicates the BOT reflective strip is sensed by the selected
transport.

Select Remote: A 1 indicates the selected transport is not on-line.

Parity Error: A 1 indicates a longitudinal parity error, vertical parity error, or CRC error has
been detected.

File Mark (FMK): A 1 indicates the selected transport has detected a File Mark during a
write FMK, space, read, or read/compare operation.

Record Length Incorrect: A 1 indicates that during a read or read/compare operation, the
record length was different from the contents of the WC Register. The WC Register is read to
determine whether the record was long or short.

Data Request Late: A 1 indicates the computer failed to service the BRK RQST before the
next data transfer to or from the transport.

End of Tape (EOT): A 1 indicates the EOT reflective strip has been sensed by the selected
transport.

File Protect: A 1 indicates the selected transport has a write lockout ring removed, and no
write functions are accepted.

R/C ERROR: A 1 indicates a comparison failure occurred during the read/compare
function. The CA Register contains the address of the word that produced the error.

8-8

Part II

Table 8-2 (Cont)
Main Status Register Contents and Indications
Status Indication

Bit No.
11

A 1 indicates that one of the following lllegal Functions has been programmed.
1.
2.
3.
4.
S.
6.

Execution of LCMR, LFGR, or LDBR while the control is busy.
Specifying any density but BOO bpi for a 9-track transport.
A space reverse function when the transport is at BOT.
Read, read/compare, or space forward after a write or write end-of-file (WEOF)
command on same transport.
Changing to transports that are not ready (TUR is false).
Attempting to rewind when tape is at BOT.

SC-2 ERROR L I<

DATA 0 L

SC -2 REWINDING L

DATA I L

SC-2 BOT L

DATA 2 L

SC-l SELR H

DATA 3 L

SC- 1 PARITY ERR L
SC-2 FM L
SC-l RECO RD LENGTH
INCORRECT L

DATA 4 L
MS
DATA
BUS
GATING

DATA 5 L
DATA 6 L

SC -I DATA LAT E L

DATA7 L

SC-2 EOT L

DATA 8 L

SC-2 WRL L

DATA 9L

o C-I RC ERROR L

DATA 10 L

SC-2 ILLEGAL
FUNCTION L

DATA 11 L
(SC-2)

Y
OC-2 RMSRL
8E-0708

Figure B-6

RMSR Instruction Data Flow

Read Command Register (RCMR)

Octal Code:

6715

Operation:

Clears the AC and transfers the contents of the Command Register to the AC. The
contents of the Command Register for this instruction are the s~me as that for the Load
Command Register instruction shown in Table 7-1 and Figure 7-2.

8-9

Part II
Read Function Register and Second Status Register (RFSR)

Octal Code:

6716

Operation:

Clears the AC and transfers the contents of the Function Register and Second Status
Register to the AC (Figure 8-4). The contents of the Second Status Register and Function Register are shown in Table 8-3.

Table 8-3
Second Status Register Contents and Functions

Function

Bit No.
7

Not used.

EMA 7 INC ERROR: EMA 7 INC ERROR occurs if an attempt is made to increment the
EMA from Field 7 to Field O. The data wraps around in Field 7.

Vertical Parity Error (VPE): A 1 indicates that a VPE error has been detected. 'This bit is set
only on the character that is bad and cleared by the next good character.

CRC Error (CRCE): A 1 indicates a CRC error has been detected.

Longitudinal Parity Error (LPCE): A 1 indicates that an LPCE has been detected.

Read Data Buffer Register (RDBR)

Octal Code:

67i7

Operation:

Clears the AC and transfers the contents of the Data Buffer Register to the AC (Figure
8-5). This instruction can be used in an error check routine to read the contents of the
LRC Register.

Skip If ERROR Flag Is Set (SKEF)

Octal Code:

6721

Operation:

Skip the next instruction if the Error flag is set.

Skip Control Not Busy (SKCB)

Octal Code:

6722

Operation:

Skip the next instruction if the control is not busy. Control is busy when the transport is
in a GO condition, control is not busy when MTTF is set at the End of Job (data
transfer completed).

Skip Job Done (SKJD)

Octal Code:

6723
8-10

Part II

Operation:

Skip the next instruction under following conditions.
1. When JOB DONE (MTTF) is set at LRCS time of a read, read/compare, write, or
write File Mark operatio~.
2.

At the'IRG following EOT, FMK, or WCOV during space operations.

MTTF is set by OFFLINE function, SELECT ERROR, or REWINDING status.

MTTF is set by an LDBR (Load Data Buffer Register) instruction.

Skip i/ Tape Unit Ready (SKTR)

Octal Code:

6724

Operation:

Skip the next instruction if TUR is true.

Clear A II Registers and Flags (CLF)

Octal Code:

6725

Operation:

Clear all TM8-E registers and flags if TUR is true. If TUR is false clear MTTF, Error
flag, and Status Registers.

Check/or Data Late Error (CKDL)

Octal Code:

6726

Operation:

Force a D AT A LATE error condition during a data transfer. This instruction is used
only for maintenance (Paragraph 9.4.7).

Set Break Request (SBRM)

Octal Code:

6727

Operation:

Set BRK RQST for one data break. This instruction is used for maintenance only.

S.3 SINGLE CYCLE DATA BREAK
The single cycle data break is used for data transfers between PDP-8 core memory and the TS03 DECmagtape
transports (Figure 8-7). The concept of data transfers and the interrelationship of the data break interface are
explained in Chapter 6 of the PDP-8/ E & PDP-8/ M Small Computer Handbook, 1972. Figure 8-8 is a timing
diagram of the single cycle data break interface; reference this diagram during the discussion of the TM8-E
functions and programming that follows. Data flow for the Core Dump Mode of operation is shown in Figure 89. TM8-E functions are illustrated in Figure 8-10.
NOTE
The programs and timing diagrams presented here are not
necessarily the best or only way to program the TMS-E.
They are shown to illustrate TM8-E functional operation
and the interaction of functional groups of logic. The timing diagram referred to in the description of TM8-E functions is part of the TM8-E print set (Drawing D-TDTM8-E-l).

8-11

Part II·
~~--------------------------------------TMB-E CONTROLLER ------------------------------------------------~.~16.---PDP8 - - .
rCB-lOBCl L

f'I'

RE-lDBll H

RE-IOATA 11 L

RE-3MPX10 H

RE-1DB10 H

RE-IDATA 10 L

SC-2RD5 H

RE-3MPX9 H

RE-IDB 9 H

RE-IDATA 9 L

CRD4

SC-2RD4 H

RE-3MPX8 H

RE-1DB8 H

RE-1DATA 8 L

CRD3

SC-2RD3 H

RE-3MPX7 H

RE-lDB7 H

RE-3MPX6 H

DATA

RE-lDB6 H

BUFFER

RE-IDB5 H

CRD7

SC-2 RD6 H

CRD6
CRD5

CR02

RE-3MPXll H

SC-2RD7 H

SC-2RD2 H

...i

MULTIPLEXER

CLR

-------

RE-lDATA 7 L
DATA
BUS
GATING

RE-IDATA E> L

CRDI

SC-2RDI H

RE-3MPX5 H

CRDO

SC-2RDO H

RE-3MPX4 H

RE-10B4 H

RE-IDATA 4 L

CROP

SC-2RDP H

RE-3MPX3 H

RE-l DB3 H

RE-IDATA 3 L

RE-3MPX2 H

RE-1DB2 H

RE-IDATA 2 L

RE-3MPXI H

RE-lDBl H

RE-lDATA I L

W
M8323
Jl

(RE-3)

(RE-ll

~-3MPXO H

(RE-l)

CLR

I
MPX
A

RE-IDBO H

MJx
B

CB-lOBCL

RE-IMPXO H

MOO L

RE-1MPXI H

MOl

RE-IDBI H

MD2 L

RE-1MPX3 H

MD3

RE-1MPX4 H

MD4 L

RE-loB3 H
NOT
USED

OC-ICWDl

RE-lDB4 H
RE-IOB5H

- - DATA
- --

RE-IMPX5 H

MD5

OC-1CW03
OC-1CWD4
OC-ICW05

OC-ICWD6
OC-1CWD7

M8321
J2

Figure 8-7 Single Cycle Data Break
Data Transfer Data Flow

8-12

RE-lDB6 H

RE-IMPX6 H

MOE> L

RE-loB7 H

RE-IMPX7 H

M07 L

RE-1DB8H

RE-1MPX8 H

M08 L

RE-lDB9 H

RE-1MPX9 H

MD9 L

RE-l oB10 H

RE-1MPX10 H

MDIO L

RE-loBll H

RE-1MPXll H

MOll L

CB-1WR9 H

OMNIBUS

MULTIPLEXER

BUFFER

OC-1CW02

RE-1MPX2 H
RE-IDB2H

OC-lCWOO

RE-IDATA 0 L

LROB

CB - 2DBC2 L

RE-l DBO H
TUIO

RE-IDATA 5 L

CB-2DBCl L

CB-2 MPX
A

CB-2MPX
B

08-1666

Part II
TPI
TP2

n
-.I1

TP3
TP4
*INT STROBE
* BRK RQST L

---,

n
n

n
n
n

n
f"LrL
f"L-

I
U

CB-2 MAC ACC L
CB-2 E26

TMS- E NO-GO
PRIORITY CB-2GO
* CPMA DISABLE L
* BRK IN PROG L
CB-2 MACI (1)

CB-2 MAC2 (1)

* MS,IR DISABLE L

*MA,MS,LD CNTL
CB-I COUNT WC L
SC-1 COUNT CA L

---,

*BRKCYCLE L
*OMNIBUS SIGNALS AS CONTROLLED BY THE TMS-E
8E-0502

Figure 8-8

Single Cycle Data Break Timing Diagram

8.3.1 Signal Conventions
The following signal conventions are used in the TM8-E.
1.

Interface signals. All signals that are used to interface the TM8-E with the TS03 are preceded by C,
e.g.,C SET L. All signals applied to the TS03 are asserted when they are low (0.0 V); all signals from
the TS03 are asserted when they are high (+ 3.0 V).

All signals on the TM8-E modules followed by L, e.g., SBRM L, are asserted (true) when they are 0
V. All signals followed by H, e.g." SEL 1 H, are asserted (true) when they are 3.0 V.

All signals on the TM8-E preceded by B, e.g., BTP3 L, are inverted signals or the outputs of holding
registers, e.g., B SEL 0 H.

All signals on the TM8-E have a prefix to indicate their origin as shown in Appendix F.

8-13

CB-2 DBC1 l
C RD7

SC-2 RD7 H

C RD6

SC-2 RD6 H

C RD5

SC-2 RD5 H

C'RD4

SC-2 RD4 H

RE-3 MPX11 H

RE-l DB10 H

RE-3 MPX9 H

RE-1 DB9 H

DATA
BUFFER

RE-3 MPXB H

M
A
S
T
E
R

C RD3

RE-1 DB11 H

ClK

RE-3 MPX10 H

RE-3 MPX7 H

RE-3 MPX4 H

SC-2 RD3 H
SC-2 RD2 H

RE-3 MPX1 H

SC-2 ROO H
SC-2 RDP H
MB323
J1

RE-3 MPXO H
CB-2
MPX
A

CB-l
MPX
B
CB-1
WR1st7
DB 0

(RE-1)
ClK

C woo

ClK

DATA
BUFFER

C WDI
CWD2

~_ _ _

C WD3

T
A

C WD5
CWD6

DB 9

CWD7

DB 11
MB321
J2

DATA
BUFFER

DB10

(OC-1)

(OC-l)
CB-' WR2nd7

RE-l DATA 2 l
RE-1 DATA 1 l

RE-l DBO H

RE-l DATA 0 l
OC-1
ROB

RE-3 MPXO H

MOO l

RE-3 MPX 1 H

MOl l

RE-3 MPX2 H

MD2 l

RE-3 MPX3 H

MD3 l

RE-3 MPX4 H

MD4 l

RE-3 MPX5 H

MD5 l

(RE-l)
ClK

0
M
N
I
B
U
S

:::::

MULTIPLEXER

MD6 l

RE-3 MPX7 H

MD7 l

RE-3 MPXB H

MOB l

RE-3 MPX9 H

MD9 l

RE-3 MPX10 H

MD10 l

RE-3 MPX11 H

MOll l

DBCl l

TMB-E CONTROllER

-I·

PDPB

-I
08 -1665

Figure 8-9

"'tI

- - - - - - RE-3 MPX6 H

C WD4

RE-l DB2 H
RE-1 DBl H

CB-2
DBC2 l

o
I

RE-l DATA 4 l

CB-2
DBC2 l

TS03

RE-l DATA 6 l
RE-1 DATA 5 l

RE-l DB3 H
DATA
BUFFER

RE-3 MPX2 H

SC-2 RD1 H

DATA
BUS
GATING

RE-1 DB5 H
RE-l DB4 H

RE-3 MPX3 H
C RD2

RE-1 DATA B l
RE-1 DATA 7 l

RE-l DB6 H
-- - - - - -

RE-3 MPX5 H

RE-1 DATA 9 l

RE-l DBB H
RE-l DB7 H

RE-3 MPX6 H
MULTI PLEXER

RE-' DATA 11 L
RE-1 DATA 10 l

Core Dump Data Flow

Figure 8-9

COHo

np Data Flow

FIG. 9·10

NO 8ET Oil PRESET
Ta03 WILL NOT RUN

YES

08-1694

Figure 8-10

TM8-E Flow Diagram (Sheet 1 of 9)

Part II

REWIND

OFFLINE

~ ~GO~--OiL
••

L~7_R ~

____

~~.--~_ _ _ _L""'TG_R_ _. - - .
GO

GO = 1
CONT

CHG

./:lGO=O
FIG. 9-9

CONT

DIR OR CHG TRANS

FIG 9·9

= 1
CHG

DIR OR CHG TRANS

FIG.917

FIG. 9·17

SEND C SET
CRWD,AND

SEND CREW

CWRDTOTHE
TRANSPORT

TO TRANSPORT

CONT

08-1692

Figure 8-10

TM8-E Flow Diagram (Sheet 2 of 9)

8.3.2 Write Data
Data can be written on a DECmagtape only in the forward direction (see D-TD-TM8-E-l, sheets 7 and 8 for
timing diagram). The CA Register must be loaded with the starting memory address minus one; the WC Register
must be loaded with the 2s complement of the number of words to be transferred. The density and parity bits in
the Command Register (Table 7-1) must be set to select tape density, parity mode, and tape unit. The write
function is controlled by the WC Register such that when WCOV occurs, the data transfer stops. CB-3 MTTF is
set when the LRC character passes under the read heads. Note that the WC, CA, and Command Registers must
be loaded prior to the Function Register because the Function Register contains the GO bit, which initiates tape
movement and sets SC-l CNTL BSY (control busy). If any errors other than illegal functions or select errors
occur during a write operation, the Error flag is set after MTTF is set. Operation may be continued on the same
transport in the same direction immediately if the registers are reloaded following MTTF. A continuous operation may still be achieved when a change direction or change transport is encountered; however C TUR from
the selected transport must be asserted.

8-16

Part II

YJ
WRITE

FIG. 9-8

WRITE

FIG. 9-9

CHECK
FLAGS
BREAK
INCREMENT WC
ClR BRK ROST
ClR DATA LATE
MD-DB

08-1690

08-1691

Figure 8-10

1M8-E Flow Diagram (Sheet 3 of 9)

Figure 8-10

TM8-E Flow Diagram (Sheet 4 of 9)

Part II

WRITE FILE MARK

READ OR READ/COMPARE

L....._ _ _- - . . . . J FIG. 9-9

CHG DIR
OR
CHG TRANS

FIG. 9-8

FIG. 9·9

FIG.9·12

FIG. 9-3

FIG. 9-22

WRITE
----~
FILEMARK
SETS ERROR

NO
-

PROGRAM STOP

FLAG

08-1688

Figure 8-10

08-1689

Figure 8-10

TM8-E Flow Diagram (Sheet 5 of 9)

8-18

TM8-E Flow Diagram (Sheet 6 of 9)

Part II

SET ERROR IF ANY
CLR GO
CLR BRI( ROST
CLR CNTL BSY

NOTE
IF BIT 4
IN THE COMMAND
REGISTER IS SET
DDTWO MORE
BREAKS TO READ LRC AND CRC

08-1687

Figure 8-10

TM8-E Flow Diagram (Sheet 7 of 9)

8-19

Part II

READ/COMPARE

CHECK FLAGS

DISABLE
CA
INCREMENT

LONG
RECORD

08-1686

Figure 8-10

TM8-E Flow Diagram (Sheet 8 of 9)

8-20

Part II

~
SPACE

' - - _ - . . , . _ _....J FIG. 9-8

00=0

FIG.!l-9

FIG. 9·17

YES

FIG. 9·12

SPFWD

FIG. 9·22

CHECK
FLAGS

YES

CONT

08-1693

Figure 8-10

TM8-E Flow Diagram (Sheet 9 of 9)

8-21

Part II
&.3.3 Read Data
Records are read from a DECmagtape transport and transferred to memory only in the forward direction (DTD-TM8-E-l, sheets 1 and 6 for timing diagrams). The WC, CA, and Command Registers must be loaded
because they are for a write operation. Density tape unit, and parity must be selected; density and parity must be
the same as they were when the data was written on tape. During a read operation, the number of words loaded
into the WC Register (in 2s complement) is transferred to memory. If the WC Register is set to less than the
actual record length, only the number of words in the WC are transferred. If the WC Register is greater than or
equal to the actual record length, the entire record is transferred to memory. In either case, a record length
incorrect error (SC-l REC LNG INCORRECT) is generated for evaluation by the program. The WC and CA
Registers contain the number of words read from tape and the address where the last word was stored. The
contents of the WC Register can be checked by the program to determine the cause of error (record too long or
too short).
Parity checks are made by the TS03 as data is read from tape. If any parity errors are detected, the SC-2 ERROR
flag is set at the same time as CB-3 MTTF. The Second Status Register must be read and evaluated by the
program to determine what caused the error. CB-3 MTTF (Job Done flag) is set when the LRCS character is
read from tape. Note that a BRK RQST is made for each character read from tape except in the Core Dump
Mode where two characters are read before a BRK RQST is made. Continuous operation may be obtained under
the same conditions as a write operation. Read after write operations set the Illegal Function flag. To read the
CRC and LRC characters, bit 4 in the Function Register must be I.
8.3.4 Read/Compare
The read/compare operation (see D-TD-TM8-E-I sheet 2 for timing diagram) compares data read from tape
with data from memory that is addressed by the CA Register. The WC and CA Registers must be loaded and
density and parity modes must be set. If an OC-I R/C ERROR occurs, the incrementation of the CA Register
stops and the CA Register contains the address of the data that produced the error. An OC-I R/C ERROR also
sets bit lOin the Main Status Register (Figure 7-4). Tape motion continues to the end of record and MTTF is set.
If interrupt is enabled (Figure 7-2), the program is interrupted by an OC-l R/C ERROR and the Main Status
Register is read to determine if the error was a OC-l R/C ERROR. The CA Register must be read by the
program to determine the memory location where data was stored that caused the error. Note a read/compare
operation cannot follow a write operation; the tape must be backspaced before starting a read/compare
operation.
8.3.5 Extended Gap
Extended Gap is used with write operation (bit 3 in the Command Register must be set) to cause the transport to
leave a 3-inch (7.62 cm) blank space (gap) at the beginning of a record (Drawing No. TD-TM8-E-I, sheets 1
through 9). This feature is used to leave spaces to separate records or groups of records and to space over bad
spots on tape. Note that the only difference between this operation and a normal write operation is the time
required to obtain the first write strobe pulse from the TS03 (Table F-7 for definition).
8.3.6 Write End-or-File
The write end-of-file operation (D-TD-TM8-E-l, sheet 4) writes a single character (23 8) on tape to designate the
end of a record or group of records. The EOF character !s followed by an LRC character that is identical to the
EOF character. The WC and CA Registers do not have to be loaded for this operation.
8.3.7 Space Forward
The space forward operation (see D-TD-TM8-E-l, sheet 5 for timing diagram) causes the tape to space forward a
number of records specified by the WC Register. The WC Register must be loaded with the 2s complement of the
number of records to be spaced over. The WC Register is incremented by the C LRCS pulse at the end of each
record. CB-3 MTTF sets when the WC Register overflows and the last record has been passed over. Note that an
attempt to Space Forward when the tape is at EOT is an error that sets the SC-2 ERROR flip-flop after CB-3
MTTF is set. Space forward is terminated if a File Mark is encountered. SC-2 ILLEGAL FUNCTION is set if
space forward is initiated after a write or write File Mark function.

8-22

Part 1/
8.3.8 Space Reverse
The space reverse operation (see D-TD-TM8-E-l, sheet 3 for timing diagram) causes the tape to space reverse a
number of records specified by the WC Register. The WC Register must be loaded with the 2s complement of the
number of records to be spaced over. CB-3 MTTF sets when the WC Register overflows and the last record has
been passed over. Note that an attempt to do a space reverse operation when tape is at BOT is an illegal function
that sets the SC-2 ILLEGAL FUNCTION flip-flop and ends the operation. A space reverse operation is terminated if a File Mark, BOT, or WCOV is encountered.

8.3.9 Rewind
The rewind operation causes the tape to rewind at high speed to BOT. The WC and CA Registers need not be
loaded for this operation. CB-3 MTTF is set when the selected transport asserts Rewind Status. After one
transport is given the command to rewind, another transport can be selected for other operations. If the selected
unit is rewinding, C TUR is false (not ready) and no operations can "e performed on that transport.
8.3.10 Continuous Operation
As previously stated, an operation ends when the CB-3 MTTF (Job Done) flag is set. To continue an operation
after CB-3 MTTF sets, the program must execute the LFGR instruction before SDWN (tape settling down time)
to restart the transport and continue the operation. Note that the WC and CA Registers may have to be loaded
to select new word count and memory address parameters. The operation continues until the WC Registers
overflow and the operation is terminated.
8.4 PROGRAMMING NOTES AND EXAMPLES
This section is not designed to teach programming but to give some programming notes and examples to be used
when programming the TM8-E. For programming information, refer to Introduction to Programming, 1970 and
PDP-8IE and PDP-8IM Small Computer Handbook, 1972.
8.4.1 Programming Notes
The only programming restrictions to be considered are those that generate SC-2 ILLEGAL FUNCTIONS
(Table 8-2), which includes attempting to perform read operations after write operations. To read after writing a
record, the program must perform at least one tape move operation, i.e., space reverse or rewind.
8.4.2 Programming Examples
The following routine is an example of the method to be used to program the TM8-E. Note that in this particular
example program interrupts are not used.
The general method of calling this TM 8-E routine is as follows:

Set locations COMMAND (Figure 7-2), CUR ADR, WRD CNT, and FUNCTN (Figure 7-3) as
indicated at the end of the TM8-E routine.

Execute JMS TM8-E.

The routine returns to the next location if and only if the CB-3 Error flag is set with the final contents of the
Function/Status Register in the MQ and the final contents of the Main Status Register in the At. Refer to Table
8-2 for conditions to set the CB-3 Error flag. The routine returns to the second location following JMS TM 8 if
the Error flag is cleared (the AC is all Os and the MQ is unchanged).

8-23

TM8E,

o
ClA
ClF
TAD
lCMR
ClA CMA
TAD
lCAR
TAD

TM8ENO,

TM8EOK,

lWCR
TAD
lFGR
SKEF
SKP
JMP
SKTD
JMP
SKEF
JMP
RFSR
MOL
RMSR
SKP
ISZ
ClF
JMP 1

COMMAND,

FUNCTION,

CURADR,

WRDCNT,

COMMAND

Part II
Enter here.
Ensure AC = 0000
Clear TM8-E flags.
Get drive, parity, field, and density.
load Command Regi~ter.
Get starting address minus one.

CURADR
WRDCNT

FUNCTION

TM8ENO

load CA Register.
Get 2's complement of the number of words to be transferred
or records to be spaced.
load WC Register.
Get Function, Gap, GO bit, and EMA Increment.
load Function Register and GO.
Wait for ERROR flag or MTTF flag.
ERROR flag set.

-4

MTTF set? ERROR flag set?
No. No errors reported for this operation.
ER ROR flag set. Read Function/Status.
Register and load into MO.
Read Main Status Register and leave in AC.
Bypass return address update if in error.
TM8E
No error reported then update return address.
Clear TM8-E flags.
TM8E
Exit.
This location must contain all information to be loaded into the TM8-E Command
Register.
This location must contain all information to be loaded into the TM8-E Function
Register.
This location must contain the first memory address minus one to be used in
Write, Read, or Read/Compare operations.
This location must contain the 2's complement of absolute value of the number
of words to be transferred in Write, Read or Read/Compare operations, or the
absolute numeer of records to be spaced in Space Forward or Space Reverse
operations.
TM8EOK

The following is an example of a TM8-E routine using the Program Interrupt System.
TM8-E

ClA
ClF
TAD
IOF
lCMR
ClA CMA
TAD
lCAR
TAD
lWCR

COMMAND

WRDCNT

Enter here.
Clear AC (AC = 0000).
Clear TM8-E flags.
Get drive, parity, field, and density (Table 8-1).
Turn PDP-8/E Interrupt System off.
load Command Register (Table 7-1).
Get starting address minus one.
CURADR.
load CA Register.
Get 2's complement of number of words to be transferred or
records to be spaced.
load WC Register.

8-24

TM8-E (Cont)

Poll another
Device
TM8-E No,

TM8EOK,

TAD
lFGR
ION
INT SET,
TM8-EOK

FUNCTN

If ERROR flag is set then Read Function/Status Register and
load into MO.

RFSR
MOL
RMSR
ISZ
ClF
JMP 1
tNT SER

Part II
Get Function, Gap, GO bit, and EMA Increment (Table 8-2).
load Function Register and GO (Table 8-2).
Turn on program interrupt system.
E R RO R flag set.
Service another device if Interrupt Request is made.

TM8-E

Read Main Status Register and leave in AC.
No error reported then update return address.
Clear TM8-E flags.

2
Continue servicing other devices.

8-25

Part II

CHAPTER 9
DETAILED LOGIC DESCRIPTIONS

9.1 INTRODUCTION
The logic in the TM8-E is broken into functional groups for discussion purposes. Figures 9-1 through 9-28
should be used to understand the interaction of the logic, signal flow between groups of logic, and the input or
output signals. The purpose of each group of logic is discussed in Chapter 7.
NOTE
The signals on the 1MS-E print set are preceded by two
letters and a number to indicate the origin of the signal,
i.e., a signal with SCI in front of it originates on sheet I of
the status and control module prints. Signals without prefixes are Omnibus signals.
9.2

M8321 OUTPUT CONTROL MODULE

9.2.1 Input/Output Instruction Decoder
The I/O instruction decoders (Figure 9-1) decode instructions from the Memory Data Bus and generate signals
to control the operation of the TM8-E. Bits MD 3 through MDII are gated by I/O PAUSE when an I/O
instruction is executed by the processor. Bits MD 3 to MD 6 generate a signal, 67XX, which partially enables the
gates to the I/O decoders. MD 7 and MD 8 generate a signal (670X, 671X, or 672X) to apply bits MD 9, MD 10,
and MD 11 to the I/O decoder. Each I/O decoder is an 8251 IC; the 8251 IC is a binary-to-decimal decoder,
which decodes MD 9 through MD 11 and produces a low on one output line. The low out of the 8251 IC
indicates which instruction is to be executed. As an example, a 670X instruction with MD 9 low and MD 10 and
11 high (100) produces a low on pin 4 of the 670X decoder to indicate that a LFGR instruction (6706) was
executed by the program. INT I/O L is grounded to prevent execution of lOT instructions by the processor while
TM8-E instructions are underway.
9.2.2 C Line Select Logic
The C line select logic (Figure 9-1) controls the direction of data flow between the Data Bus and AC and
determines if the AC is to be cleared or not. Table 9-1 shows the status of CO and C 1 to transfer data between the
AC and Data Bus using the TM8-E lOT instructions.
9.2.3 TP3 Logic
TP3 is used to enable the selection of the 670X I/O decoder and is used throughout the TM8-E to enable the
execution of instructions (Figure 9-1) and to enable data transfers using the single cycle data break interface.

9-1

P/O M8321(OC-2)
6721 (SKEF)
E26
( 672 X) n::..:..==.:.;=.,.
8251 n=..:..::...;..:.:::..:..;~
IC
6725(CLF)
MO 7 -

......-a

CLR ALL L
E30
(671X)
8251
IC

6713(RCAR)
6714(RMSR)
6715(RCMR)
6716(RFSR)
6717(ROBR)

:::::
6701(LWCR)
6702(CWCR)
E22
(670X)
8251
IC
670X

CWCR L

6703(LCAR)
6704(CCAR)
6705 (LCMR)

CCAR L

6706 (LFGR)

M08

6707(LOBR)

LCMR L

LFGR L
BTP3

M011

M010.

LCMR+LFGR
+LOBR

M09
BTP3

8E-0562

Figure 9-1

lOT Decoder Logic

Part II
Table 9-1
C Line Select Levels for TM8-E Transfer Operations
Instruction

Transfer of Operation

LWCR
LCAR
LCMR
LFGR
LDBR
RWCR
RCAR
RMSR
RCMR
RFSR
RDBR

Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low

High
High
High
High
High
Low
Low
Low
Low
Low
Low

AC ~ Data Bus 0 ~ AC
AC ~ Data Bus 0 ~ AC
AC ~ Data Bus 0 ~ AC
AC ~ Data Bus 0 ~ AC
AC ~ Data Bus 0 ~ AC
Data Bus ~ AC
Data Bus ~ AC
Data Bus ~ AC
Data Bus ~AC
Data Bus ~ AC
Data Bus ~ AC

9.2.4 CLR ALL Logic
CLR ALL L (Figure 9-1) is asserted to clear TM8-E logic under the following conditions:
1.

At TP3 time, if a CLT (6711) instruction is executed by the program.

When a CLF (6725) instruction is executed by the program (if C TUR is true).

When PWR OK H from the processor is lost due to a power failure.

When the processor asserts INIT H. This occurs during power up or when the CLEAR key is pressed
on the PDP-8 console.

9.2.5 AC ENABLE Logic
OC-2 AC ENABLE (Figure 9-1) is asserted when a 670X instruction is executed by the program to enable gates
to apply the Data Bus information to the TM8-E registers that are loaded from the AC (Figure 9-7) and Control
CO and Cl levels (Paragraph 9.2.2).

9.2.6 Skip Logic
The skip logic (Figure 9-2) asserts OC-2 SKIP BUS L and causes the processor to skip an instruction when the
following conditions exist.

1.
2.
3.
4.

The 6721 (SKEF) instruction is executed and the SC-2 Error flag is set.
The 6722 (SKCB) instruction is executed and SC-l CNTL BSY flag is set.
The 6723 (SKJD) instruction is executed and CB-3 MTTF flag is set.
The 6724 (SKTR) instruction is executed and C TUR L is true.

9.2.7 Output Control Function Decoder
The output control function decoder (Figure 9-3) is an 8251 IC, which decodes the three most significant bits of
the Function Register and determines what function the TS03 transport performs (Table 8-1). The 8251 IC is a
BCD-to-decimal decoder which decodes FRO, FR 1, and FR2 and produces a low on one output line. The low
out of the 8251 IC indicates the function to be performed. As an example, if FRO is low, and FRI and FR2 are
high, pin 9 is low indicating a write operation is to be performed. The outputs of the function decoder, applied to
the tape transport, are defined in Table F-7 and Figure 7-3.

9-3

Part II

PIO M8321(OC-2)
SC -2 ERROR L
OC -2 6721 L

SC-1 CON BUSY L
OC-26722L
OC-2
SKIP BUS L
CB-3 MTTF L
OC-2 6723 L

SC -1 TUR L
OC -2 6724 L
8E-0548

Figure 9-2

Skip Logic

P/O M8321 (OC-l)

+5V

+3V

~~........--~---- J2 - DD C

REV H

+3V

JI-X C FWD H

CB-I SPACE REVERSE
RE-1
FRO H
RE-I
FRI H
RE-I

FR2 H

CB-3INIT H

CB-I SPACE FORWARD
EI2
OUTPUT
CONTROL
FUNCTION
DECODER

CB-I WRITE END OF FI LE
CB-I WRITE
CB-' READ/COMPARE
CB-I READ
CB-I REWIND

~-----<......- -.......- - - -

+5V

JI-BB C WRE H

+3V

CB-IOFFLINE
J2-RR C WFMK H

Jl-Z C RWD H

J2-V CWXG H

CB-2 RDB L
BE-0547

Figure 9-3

Output Control Function Decoder

9-4

Part II
9.2.8 Read/Compare Logic
The read/compare logic consists of 12 Exclusive-OR gates and the OC-I R/C Error flag (flip-flop). The 12 bits of
data from the Memory Data Bus (data read from memory) are Exclusively-ORed with 12 bits of data from the
Data Register (data read from tape). During the data break, at TP3 time, if the data from memory is different
from data read from DECmagtape the SC-I R/C ERROR flag is set and CA incrementation stops. Tape motion
continues until an LRC strobe is obtained at end of record. RE-I DEN 5 H Cind RE-l DEN 8 H are used to
enable a gate on the outputs of the Exclusive-OR gates for the four most significant bits to prevent them from
causing a read/compare error. RE-I R/C ENABLE is always high when a read/compare function is selected by
the program. Refer to D-TD-TM8-E-I, sheet 2, for the timing during a read/compare operation.
9.2.9 Write Data Select Logic
The write data select logic selects 6 or 8 bits of data from merr. Jry to be written on DECmagtape (Figure 9-4).
The gates labeled C on Figure 9-4 are enabled by CB-l WR 9 H to apply 8 bits of data from the Data Buffer
Register to the selected transport (see D-TD-TM 8-E-I, sheet 8, for timing).
The control signals for the gates originate in the control logic shown in Figure 9-26. The outputs to the transport
are limited to 0.0 V and +3 V levels by the diode and resistor networks tied to the output lines.
9.3 M8327 REGISTERS MODULE
The TM8-E Registers are used to address memory, count the words in a data transfer, select DECmagtape
operations, and generate command signals for the TM8-E control logic and the tape transports. Each of the
registers used in the TM8-E are discussed in the following paragraphs; the Status Register is discussed with the
Transport Status and control logic in Paragraph 9.4.1.
9.3.1 Data Buffer Register and Multiplexer
The Data Buffer Register and Multiplexer (Figure 9-5) provides temporary storage for data manipulation (transfers and read/compares). Inputs to the Data Multiplexer come from memory (MD 0 through MD II), from the
AC (DATA 0 -DATA II), or from the tape (CRD 0 through CRD 7). The Data Multiplexer is a 74153 IC (refer
to Appendix H for logic diagram, truth table and pin locations), which selects one of the four data inputs to be
applied to the Data Buffer Register. CB-2 DB MPX A and CB-2 DB MPX B controls the selection of data that is
supplied to the Data Buffer Register. Table 9-2 shows the levels required to load the Data Buffer Register for
each operation. CB-I DBC I and CB-I DBC 2 are used to clock the output of the multiplexer into the Data
Buffer Register. The Data Buffer Register is two 74174 ICs (refer to Appendix H for truth table, logic diagram,
and pin locations) each containing six flip-flops that are set or cleared by the input from the multiplexer. The
contents of the Data Buffer Register are applied to the read/compare logic, to output control logic, and to an
8235 IC as shown in Figure 9-6. During a read operation or when a RDBR instruction is executed, the data is
transferred to the Data Bus. During a read operation, data is transferred to a memory location selected by the
Current Address Register during single cycle data break. If the RDBR (6717) instruction is executed, the data is
transferred to the AC via Data Bus. Refer to the flow diagram (Figure 8-10 and Figure 8-5) for an illustration of
this operation. The timing diagrams for these operations are shown in Drawing No. D-TD-TM8-E-I, sheets 1
through 9.
Table 9-2
Data Multiplexer Selection Levels
Operation

CB-2 DB MPXA H
(pin 14)

CB-2 DB MPXB H
(pin 2)

Load Data Buffer
Write
Read 7 Channels
Read 9 Channels

low
high
low
high

low
low
high
high

9-5

+5V

CB-' WR 1st 7 H _--.....___

MOOl

MOll

M02l

+3V
M03L
CWOO H
M04l
CW01 H
M05l
CW02 H
M06l
CW03 H

M07l
CW04 H
MOB l
CW05 H
M09l
CW06 H
M010l
CW07 H
+5V
MOll l

OC-2 ClR RC
ERROR l
+5V

OC-' RC ERROR l

OC-' READ COMPARE l
+3V

Figure 9-4

Read/Compare and Write Data Select Logic

+5V

8E-0584

Part II

r---------..,I
I
I
I

P/O M8322(CB-2)

CB-l R lst 7 L

I ~B-2
I
I
L.... _ _ _ _ _ _ _ _ _ ..JI
CB-2 MAC2 H
CB-2 B TP3 H
CB-I WRITE H

E19*

E31 x:"'~-=--t"t
--

DBC2

CB-IR9CHL
OC-2 LDBR L

RE-3 MPXO H

RE-3 MPX I H
RE-3 MPX2 H
E19
74174

RE-3 MPX3 H
RE-3 MPX4 H

:8
E

H-

E20

MD5L

RE-l
,-- DB2
RE-1
I- OB3
RE-'

RE-'
I- OB5

MD"4L

RE-1
DBO
RE-'
OBI

r-- DB4

RE -3 MPX5 H

RE-I
BAC 4

.....l!....J

+3V
(RE-ll

MPX
4

SC-2 RD6 HSC-2 ROO H- 74153
RE-I BAC 5 HE26

E20

SC-2 RD7 H SC-2 RDI H-

MPX
5
l14

MD6L

c:E>
E20

-----------,
I
I
P/O M8322 (CB-2)

RE-I
BAC 6

H-

MPX
6

SC-2 RD2 H.r: 74153
E25
MD7L :BRE-1BAC7HE20
r
MPX
f--I-SC-2 RD3 H .......~....;.7_~

I
I
I

CB-'~2nd7L

CB-2 MAC2 H
CB-2 B TP3 H
CB-l WRITE H

CB-1R9CH

L ___o~~:...

114 .,.

MD8 L ~
E36

SC-2 RD4H.L
MD9 L ~RE-IBAC9HE36
SC-2 RD5

l14

CB-2
OBCl

___ J
DB

r- oB7

RE-3 MPX8 H
RE-3 MPX9 H

RE-I
I- OB6
RE-I

RE-3 MPX7 H

74153
E43
MPX
9

E31

RE-3 MPX6 H

RE-I
~l...
BAC8H- MPX
8
I-

E19*

74174
E44

RE-3 MPXIO H

RE-I
r- oBB
RE-l
I- oB9
RE-I
r- oBIO
RE-l

RE-3 MPX11 H

t- OBII

---<'f'::\

MD10L

RE-l
BAC 10

H-

SC-2 RD6 H L
MOIl L : a R E - I BAC II H
E36
4

"'=

12 l..

+3V
(RE-])

MPX
10
74153
E42

r MPX
SC-2 RD7 H-*-L....o_'...,I........l

*Same AND gate
shown twice on this illustration.

CB - 2 DB MPX A H _ _-.1Il....
14_L
_ _---J

8E-0581

(RE-3)

Figure 9-5

Input Data Multiplexer and Data Register

9-7

Part II
P/O M8327

RE-' FRO L

(RE-l)

RE-' DBO
RE-' FR, L

DATA 0

R_E_-_,D_B_'- - - - - I 8235
RE-' FR2 L
E4
RE-' DB 2

DATA 2

RE-' DB 3

r;:; M-;21-:

DATA 1
DATA 3

(RE-l)

RE-' EN CHECK CHAR L
-

+5V

OC-\
READ L

I
I
L _____________ ....J

RE-' DB 4
RE-'GO

DATA 4

RE-' DB 5

DATA 5

8235

SCot 7 CHAN + DEN5 L
RE-' DB 6
+3V
RE-' DB 7

E23

DATA 6
DATA 7

(RE-ll

+3V
RE-' DBB
DATA 8
RE-' DB9
RE-' DB10
RE-' DBll

8235
E35

DATA 9
DATA 10
DATA 11

(RE-l)

+3V
8E-0569

Figure 9-6

Data Register and Function Register Output Multiplexer

9.3.2 AC Input Gating
The AC input gating (Figure 9-7) is used as a buffer between the Data Bus (inputs from the AC) and the TM8-E
Registers. OC-2 AC ENABLE L is asserted (low) any time a 670X instruction is executed by the program to
transfer data from the AC to the TM8-E Registers. The outputs of the NAND gates enabled by OC-2 AC
ENABLE are applied to the Command, Data, and Function Registers, and to two 74174 ICs, which provide a
Holding Buffer for inputs from the AC. The 74174 ICs (refer to Appendix H for truth table, logic diagram, and
pin locations) are 6-bit buffer registers for inputs to the WC and CA Registers and bits 6 through 8 of the
Command Register. SC-l B TP3 is used to clock the outputs of the NAND gates into the AC Holding Buffer
Register. The outputs of the AC Holding Buffer Register are applied to the WC and CA Registers (Figure 9-8).
9.3.3 Current Address (CA) Register
The Current Address Register (Figure 9-8) is a ripple counter that sequentially addresses locations in memory by
incrementing before each data transfer. The CA Register is loaded with a 12-bit address that is one less than the
desired starting address. The CA Register is incremented by the leading edge of SC-l COUNT CA L (Figure 9-8)
each time a BRK RQST is made by the TM8-E. CB-2 MAC ACC is asserted after a BRK RQST is granted to the
TM8-E and removes the SC-l COUNT CA L signal from the CA Register. The CA Register is not incremented
when SC-I COUNT CA L goes high because the counter increments only a high-to-Iow transition of the signal.
The CA Register is loaded by the LCAR instruction before each DECmagtape operation and must not be loaded
during CNTL BSY.

9-8

Part II
P/O M8327(RE-1)

BTP3
liRE-I B
ACO H

DATA 0 L

DA
*RE-l B
AC lH

DATA 1 L

HBAC OH

HBAC
DB

HBAC 1 H

liRE-I B
AC 2H

DATA 2 L

DATA :3 L

liRE-IS
AC 3H

DATA 4 L

liRE-IS
AC 4H

HaAC 2 H

74174
E9
DO

HBAC 3H

HBAC 4H

*RE-IS
AC 5H

DATA 5 L

HBAC 5 H

TO WORD COUNT AND
CURRENT ADDRESS REGISTERS

+:3V
*RE-I B
AC 6H

DATA 6 L

DA
liRE-I S
AC 7 H

DATA 7 L

DATA

HBAC 6H

HBAC
DB

HBAC 7H

TO BITS 6-8 OF
COMMAND REGISTER

liRE-IS
AC 8H

*RE-l B
AC 9H

DATA 9 L

DATA 10 L

*RE-l B
AC 10H

DATA 11 L

IIRE-t B
AC 11 H

HBAC 8H

74174
E39
DO

HBAC 9H

HBAC 10H

HBAC 11 H

AC ENABLE L
+3V

8E-0551

• OUTPUTS TO COMMAND REGISTER. DATA REGISTER AND FUNCTION REGISTER.

Figure 9-7

AC Input Gating and Holding Buffer Register

The output of the CA Register is applied to the MA lines when CB-2 MAC 1 H enables the NAND gates (Figure
9-8) to select a location in memory which contains data to be read or a location to store data from the DECmagtape. The contents of the CA Register are also applied to an 8235 IC for transfer to the AC when an RCAR
instruction is executed by the program. The CA Register is read by the program during error check routines and
maintenance operations to determine what address in memory generated an error. The CA Register is cleared by
a CCAR instruction.
9.3.4 Word Count (WC) Register
The Word Count Register is a ripple counter that (Figure 9-8) counts the data words transferred to or from the
DECmagtape during transfers and counts the records during space operations. The WC Register is loaded from
the AC with the 2s complement of the number of words to be transferred or number of records to be spaced when
a L WCR instruction is executed by the program.

9-9

Part II
PIO M8327(RE-3)

OC -2 LWCR L

OC- 2 CWCR L

RE -1
HBAC OH
RE-l
HBAC 1 H

DATA OL
DATA IL

RE-l
HBAC 2H

DATA 2L

RE-l
HBAC 3H

DATA 3L

RE-l
HBAC 4H
RE-l
HBAC 5H

DATA 4L
DATA 5L

RE-l
HBAC 6H

DATA 6L

RE-l
HBAC 7H

DATA 7L

ReAR L
RE-l
HBAC 8H

r;/0-;;8~(~1)-

I
I

RE-l
HBAC 9H
RE-l
HBAC 10H

DATA 9 L

RE-l
HBAC II H

DATA IlL

DATA BL
DATA 10L

OC-2
SBRM L
E27 " } - - - - f
SC-2
BL RCS L CB-l SPACE H

L __

OC-2 CCAR L

'-:C-::"M:'"

RE-l
HBAC OH

RE-2 CAO L

RE-l
HBAC 1 H
RE-l
HBAC 2H
RE-l
HBAC 3H

RE-l
HBAC 4H
RE-l
HBAC 5H

r -;0 -;83~(S~1) -

I
I

CB -1
BRK RQST

SC-2
RC ERROR L

I
I

- --,

RE-l
HBAC 6H
RE-l
HBAC 7H

+3V

I
I

CB-2 MAC ACC L

I
I

~~AiuCSL~
+3V

E23

L ___ _

RE-l
HBAC 8 H
RE-l
HBAC 9H
RE-l
HBAC 10 H
RE-l
HBAC 11 H
SC-l
COUNT CA L
8£-0583

Figure 9-8

Current Address and Word Count Registers

9-10

Part II

The output of the WC Register is applied to an 8235 IC and is transferred to the AC when an RWCR instruction
is executed by the program. When bit 0 makes the transition from the high to low state RE-2 WC 0 is applied to
the CB-I WCOV flip-flop (Figure 9-1). CB-I WCOV indicates to the control logic that the data transfer is
complete (the specified number of words have been transferred). Word count is incremented during the break
cycle when SC-I COUNT WC makes a high to low transition by asserting one of the following:
I.
2.

CB-2 MAC ACC L during a Read or Write operation.
C LRCS L during a CB-I SPACE operation if a File Mark is not detected.

9.3.5 Function Register
The Function Register (Figure 9-9) is loaded with 6 bits of data from the AC by an LFGR instruction. The 6 bits
determine the function (Table 8-1) the transport is to perform and provide control signals to initiate D ECmagtape operations. The Function !tegister consists of two 74175 ICs (refer to Appendix H for truth table, logic
diagram, and pin locations) which contain the flip-flops that are set or cleared by bits from the AC. The three
most significant bits of the Function Register (FRO through FR2) are applied to the output control function
decoder (Figure 9-3) and the control function decoder (Figure 9-19). FR3 through FR6 are applied to the control
logic to accomplish the functions shown in Table 8-1. The CB-3 MTTF input to the 74175 IC clears the three
least significant bits FR4 through FR6 when the CB-3 MTTF (Job Done) flag is set at LRCS time (Figure 9-22).

PIO M8327(RE-l)
E21
OC - 2 LFGR L

I
RE-l FRO H

.....
RE-l BAC OH
RE-l BAC I H
RE- I BAC 2 H

RE-l FRI H

FR
E14
74175

RE-1FR1L
RE -1 FR 2 H

.....

RE - I BAC :3 H

RE-l FRO L

RE-l FR2 L
RE-l FR3 H
RE-! FR3 L

(RE-I)

I
RE-1BAC4
RE-l BAC5
RE-! BAC6

P--RE-! ENABLE CHECK CHAR L
- R E - l GO H
FR
E27
74175

c)-- RE-t

GO L

c)-- RE-l

EMA INC ENABLE

(RE-I)

CB-3 MTT F L

8E-055O

Figure 9-9

Function Register

9-11

Part II
The outputs of the Function Register are also applied to an output multiplexer (Figure 9-8) for transfer to the AC
when an RFSR instruction is executed by the program. The 8235 IC transfers the function and status to the Data
Bus for display in the AC or evaluation by the program when RE-I RFSR L is asserted. RE-I RFSR L is
asserted when an RFSR instruction is executed by the program.
NOTE
The Function Register .ust be the last register loaded
because it contains the GO bit, which initiates CNTL
BSY, PRESET, and SET to start the tape transport.
9.3.6 Command Register
The Command Register (Figure 9-10) consists of nine flip-flops and a 3-bit ripple counter that are loaded from
the AC when an LCMR instruction is executed by the program (Table 7-1).

, - - R E - ' B SEL 0 H
r - RE-' B SEL 1 H
....- RE·I B SEL Z H

r/~ ;8;-2;(OC-2) - - - - - - ,
5V
I

P/O M8327 (RE-l)

E37

J
CB-3 LBCML

RE-I BAC OH

RE-' SEL 0 H

RE'I BAC lH

RE-' SEL I H
CM
0-3
74175 RE-' SEL 2 H
EI5

RE-' BAC 2H
RE-I BAC 3H

r-c:

r--

+3V
+3V

RE-1"BAC4H
RE-I BAC5H
RE-' BAC 9H
RE·I BAC10H

Y
OC-Z
~ LCMR L

.----.
I
I

CM
H BAC 7H . 6-8
74197
E31
H BAC 8H

I
I
I

RE-1EMAZ-,

RE-Z

r- ~EMA7H
E30
RE-Z
EMA 0

I
I
I
I

RE-2

~EMAI
EZ8

RE-Z

+3V

~/~8::7(~-22....

I-o-CB-2 MAC 1 H

I
I

+3V

8235
E40

E38

+5V

)

+5V~
E38

+5V~
E3Z

+5V

J 1-J
C SEL Z H

-+3V

•

J 2-NN
C PEVN H

-:,:

DATA iI L
DATA 8 L

+5V~

+5V

E39

DATA 4 L

,-(

DATA 5L
8Z35
E29

DATA 6L
DATA 7 L

+5V~
E32

-+3V

•

J I-N
C DEN 8 H

~+3V

r
J I-R
C DEN 5 H

+!V
~

oC- Z RCMR L

J I-T
C SEL 16 H

..-<l

- ---- J

J 1- F
C SEL I H

E38

+ 3V

+3V

J 1-0
C SEL 0 H

E38

DATA 10L

+3V

+5V~

-I--

+5V

£38

DATA 9 L

r<l
~

~EMA2
EZ8

SC -, EMAINC L

.•

RE-' DEN 5 H

EZ8

H BAC 6H

DATA 3 L

L_ RE-I IEMF H

I
I

r--

DATA 2 L

DATA 1 L
8Z35
E5

RE-I DEN 8 H

CB-3
CLR ALL L~~

I
DATAOLI

r RE-I IEEF H
CM
4.5.
9-1"
74174
E45

RE-I BACllH

r-cl
BCM
7495
EIO

L. __ ...

- ---':'

___ ..J
IE-OSI4

Figure 9-10

Command Register and Multiplexer

9·12

Part 1/
The four flip-flops that receive RE-l BAC 0 through RE-l BAC 3 (Table 7-1) as inputs are on a 74175 (refer to
Appendix H for truth table, logic diagram, and pin locations). Three of the flip-flops on this IC generate SEL 0
th~ough SEL 2 for indicating selection of one of the transports and provide an input to the Buffered Command
Register for transport selection (Paragraph 9.3.7). AC 03 is used to select odd or even parity mode for the TS03
Transport. If this flip-flop is in a 0 state, even parity is selected and C PEVN L to the TS03.is asserted.
RE-l BAC 4, RE-I BAC 5, and RE-I BAC 9 through RE-I BAC 11 are appliec1 to a 74174 IC (refer to Appendix
H for truth table, logic diagram, and pin locations), containing six flip-flops that are loaded by the inputs from
the AC (Table 7-1).
The remainder of the bits from the AC (AC 6 through AC 8) are applied to a 74197 IC (refer to Appendix H for
truth table, logic diagram, and pin locations) containing three flip-flops to select a memory field during data
transfer. The 74197 IC is a 3-bit ripple counter that is incremented by S~-I EMA INC L if bit 6 in the Function
Register is set (1). The output of the 74197 IC (RE-I EMA 0 - RE-I EMA 2) is applied to the Omnibus when CB-'
2 MAC 1 H enables the three AND gates (Figure 9-10) during a single cycle data break. Refer to Paragraph 9.4.2
for a discussion of the SC-I EMA INC L signal generation.
The contents of the Command Register are transferred to the Data Bus when the program executes an RCMR
instruction to assert the control input of the 8235 ICs (Figure 9-10). The Command Register is cleared by CB-3
CLR ALL L (Paragraph 9.2.4).
9.3.7 Buffered Command Register (BCM)
The Buffered Command Register (Figure 9-10) receives RE-I SEL 0 through RE-I SEL 2 as inputs from the
command register. RE-l B SEL 1 through RE-I B SEL 2 out of the BC\{ are applied to the TS03 to select a
transport and provides an input to a comparison circuit to determine when a new transport has been selected
(Figure 9-23). CB-2 CHG TRANS L is asserted if RE-I SEL 0 through RE-l SEL 2 from the command register
and RE-l B SEL 0 through RE-l B SEL 2 from the Buffered Command Register are different; thus CB-2 CHG
TRANS L is asserted if a new transport is selected by the program. The output of the BCM holds the select lines
to the previously selected transport in the same state until C SOWN L (settled down) is obtained from the
transport. Then the BCM is loaded by RE-2 LBCM L to select a new transport. Thus the BCM allows the
program to load the command and select a new transport without deselecting the previously selected transport
before it stops.
9.4 M8323 TRANSPORT STATUS AND CONTROL MODULE
The M8323 Transport Status and Control module consists of the Main. Status Register (Table 8-2), Second
Status Register (Table 8-3), logic for generation of timing and control signals, and a Data Multiplexer to transfer
the contents of the Status Registers to the Data Bus.
9.4.1 Main Status Register
The logic elements that make up the Main Status Register perform as follows.
9.4.1.1 SC-2 Error Flag Logic - The SC-2 Error flag (Figure 9-11) is set immediately if the program attempts an
illegal function or if SC-2 SEL ERROR is asserted by the selected transport. The SC-2 Error flag is set after CB-3
MTTF is set if any of the following errors are detected.
1.
2.
3.
4.
5.
6.

7.
8.

EOT
BOT
DATA LATE
PARITY ERROR (LRCE, CRCE, or VPE in Second Status Register)
REC LNG INCORRECT
EMA 7 INC ERROR (Second Status Register)
RIC ERROR
File Mark (FM)

9·13

PIO M8323(SC-2)

+5V

+5V
E19
E23

C EOT L

CB-3MTTF L

-.-.--0

SC-2
ILLEGAL
FUN. L

SC-2 B BOT L
+3V
C FM L
SC-l RECORD LENGTH
INCORRECT L

DATA LATE L -------SC-l PARITY ERROR L
SC-l EMA 7 INC ERROR L
OC-l RIC ERROR L

-------I
OFFLINE L ------.I

SC-l SEL ERROR H

D
E1
ERROR
(MS)

CR -3 CLR STATUS L

Figure 9-11

Error Flags

SC-2
ERROR L

Part II

9.4.1.2 Illegal FUDction Logic - The SC-2 ILLEGAL FUNCTION flip-flop (Figure 9-12) is set if the program
attempts any of the following SC-2 ILLEGAL FUNCTIONS:
1.

fhe program exe~utes an LCMR, LFGR, or LDBR instruction when the SC-l CNTL BSY flip-flop
is set (Paragraph 9.4.5).

Selection of any density other than 800 bpi.

Selection of a space reverse operation when the selected TS03 Transport is at BOT.
P/O MS323(SC-2)

+!W

CB-I REWIND L

C BOT L - + - - I
SC-2

'----~l~V-

SC-I C T CH L
RE-I DEN 8 H

SC-I TUR L

rp/~S;;'(o7-2)- -

-,
SC-2
ILLEGAL

OC-~ LCMR

OC-2 LFGR
I OC-2
LDBR
L

FUN. L

SC-I
CLR STATUS L

+5V

r;/O-:S;;;(;-.U--'C WRLl;

CB-I WRITE
SC-!
PRESET H

CB-! SP
FWD L

I CB-I READ L
I CB-! RIC
I
fP/OM8322cCB- 1)' -

I
I
I

-1

CB-! WFM L

I
I

CB-3 CHG
CLEAR L

L ________ _

SC -I
PRESET H
8E -0565

Figure 9-12

Illegal Function Flag and Control Logic

9-15

Part II
4.

Selection of read. read/compare, or space forward after a write or write end-of-file operation if the
same transport is used.

Changing to a transport that is not ready (C TUR is false) and SC-l PRESET is issued.

Attempting a rewind when tape is at BOT.

Any write command issued to a transport with write lockout set.

9.4.1.3 Data Late Logic - The SC-l Data Late (Figure 9-13) flip-flop is set if the computer fails to service a
BRK RQST before the next word is transferred to or from tape. A counter made up of flip-flops A, B, and C
(Figure 9-13) counts the Read Strobe or Write Stro be pulses generated by the tape transport each time a character is read from or written on tape. SC-l W RS L or SC-l B RDS L clocks the three flip-flops (A, B, and C). CB-2
MAC ACC L (Figure 9-13) is asserted after a BRK RQST is granted to the TMS-E by the processor to clear the
counter and prevent the SC-l DATA LATE flip-flop from setting when the next SC-l WRS or SC-l B RDS
pulse occurs. If CB-2 MAC ACC is not asserted by the time the next SC-l WRS or SC-l B RDS pulse occurs, the
set side of the B flip-flop causes SC-l D ATA LATE to set. The set output of the B flip-flop is applied to the clock
input of SC-l DATA LATE if the NAND gate tied to the set output is not disabled by C 7 CH L or RE-I DEN 5
H. The SC-l DATA LATE flip-flop is always cleared during a space operation since no data is transferred. SC-l
DATA LATE is also cleared when a File Mark (C FMK) is detected during a read operation or by CB-3 CLR
STATUS L.
+3Vl

+3Vl

PIa M8323 (SC-l)
D

+3V

+5V

E12
B

E12
A

+5V

CB-l
WCOV H

Ell

Ell
DATA
LATE
(MS)

SC -1
TEST **

SC-l
DATA
LATE L

C 7 CH L
RE-l DEN 5 H
CB-3 CLR STATUS L
E23

SC -2 SPACE H

CB-2 B TP3
CB-l BRK RQST H

CB-3 CLR STATUS L
SC -1
EMA 7 INC ERR H

RE-1 GOH

RE-1 EMA INC EN L

+ 3V

RE-2 EMA 7 H

SC - 1
EMA 7 INC ERR H

~------+----i D

E13
EMA
INC
ERROR
(SS)

*SAME INVERTER
It*TEST POINT NOT ON THE TOP OF CONNECTOR

Figure 9-13

Data Late and EMA Increment Error Flags
9-16

SC -1
EMA 7 INC ERR L

8E-0582

Part II

9.4.1.4 Record Length Incorrect Logic - The SC-I RECORD LENGTH INCORRECT flip-flop (Figure 9-14)
is set when the number of data words read from the tape and the contents of the WC Register are different
(record too long or too short). As previously stated, the WC Register is loaded with the 2s complement of the
number of words to be transferred. Word count is incremented during the data transfer. The WC Register should
contain all Os and generate CB-l WCOV L before the LRC character is read from tape. If C LRCS H occurs
before CB-I WCOV, gate E33 (Figure 9-14) is enabled, and the SC-I RECORD LENGTH INCORRECT flipflop sets. This condition occurs if the WC Register has been loaded with a word count greater than the number of
words in the record (record is short). To detect a record that is too long, a counter made up of flip-flops A and B
(Figure 9-14) counts the RDS pulses that occur after CB-I WCOV H. If two or more C RDS L pulses occur after
CB-I WCOV and there are no C LRCS Lor C CRCS L pulses, the SC-I RECORD LENGTH INCORRECT
flip-flop sets. This condition occurs if the Word Count Register is loaded with a word count less than the number
of words transferred (record is long). Note that flip-flop A is cleared by C CRCS L or C LRCS L so that SC-l
RECORD LENGTH INCORRECT is not set during the termination of a normal operation.
CB-I SPACE Hand C FILE MARK L keep the SC-I RECORD LENGTH INCORRECT flip-flop cleared
during a space or write File Mark operation. CB-3 CLR STATUS L clears the SC-l RECORD LENGTH
INCORRECT flip-flop when the Status Register is cleared by a CLF instruction.

9.4.1.5 Tape Rewinding - Tape rewinding (C RWS L) is asserted (Figure 9-16) if the selected transport is
rewinding.
9.4.1.6 End of Tape - End of tape (C EOT) is asserted if the End of Tape reflective strip has been detected by the
TS03 (Figure 9-11). IfC EOT is detected before CB-3 MTTF (JOB DONE) is set, the SC-2 ERROR flip-flop sets
and the Main Status Register must be read by the program to determine the cause of the error.
9.4.1.7 Beginning of Tape - Beginning of tape (C BOT) is asserted when the BOT reflective strip is detected by
the tape transport. If BOT is detected before CB-3 MTTF (JOB DONE) is set, the SC-2 ERROR flip-flop
(Figure 9-11) sets. The Main Status Register must be read by the program to determine the cause of the error.
9.4.1.8 Read/Compare Error - The read/compare operation is discussed in Paragraph 7.2.4.
9.4.1.9 Parity Error - The SC-I PARITY ERROR flip-flop (Figure 9-15) is set if the TS03 detects any of the
following errors.
I.
2.
3.

C LRCE (Longitudinal Parity Error)
C CRCE (Cyclic Redundancy Check Error)
C VPE (Vertical Parity Error)

If SC-I PARITY ERROR is set, the SC-2 ERROR flip-flop (Figure 9-11) sets when MTTF (JOB DONE) sets.
SC-I PARITY ERROR is cleared any time a File Mark is read from tape. During space operations, CB-l
SPACE H keeps SC-I PARITY ERROR cleared (Figure 9-15) to prevent generation of erroneous parity errors.
Note that the C VPE is cleared by the next good word read from tape and will not be seen unless it occurs as the
last word read from tape.

9.4.1.10 File Mark (EOF) - The File Mark flip-flop (Figure 9-15) is set any time the TS03 detects a File Mark
during a space, read, or read/compare operation.
9.4.1.11 Select Remote - SC-I SELR L (Select Remote) (Figure 9-17) is true when the selected transport is
OFFLINE (not ready). SC-I SEL ERROR is set if SC-I SELR L is lost during data transfer operation.
9.4.1.12 File Protect - File Protect is a 1 when write lockout (C WRL L) is asserted by the TS03, indicating that
the selected transport has the write lockout ring removed. Transports without a write lockout ring will set the
ILLEGAL FUNCTION flag during SC-I PRESET time (Figure 9-12) if they are selected for a write or write File
Mark operation.
9-17

rp~ -;;;~(-;B~)

P/O M8323 (SC-l)

I
I
I

--i

CB -1 READ L
CB-IREADI
COMPARE L

+3Vt

L ________ ..J

D
RECORD
LENGTH
INCORRECT
E26

SC-t
RECORD
LENGTH
INCORRECT L

E31
+3VI

+3VI

SCot FM L
SC-2
SPACE H

CB-I WCOV H

D
CB-3 CLR
STATUS L

EI~A

E1~B

SC -I
RDS·R +RC L

E31
C

+3V
C LRCS L
C RDS L
C LRCS L

Figure 9-14 Re,cord Length Incorrect Error Detection Logic

Part II

P/O M8323 (SC-l)

C LRCE L

E34

LRC
ERROR
(55)

BROS H

SC-l LRC ERROR H

o
E26
PARITY
ERROR
(MS)
SC-l VPE H

SC-l
PARITY
ERROR L

+3Vl
CLEAR
STATUS L --~t-------------.

r -SC-2
---,

I SPACE H
IL:SC-2
E32 ...JI
____

E35

FMK
(MS)

C
C FM

L -----'

SC-1FML

C CRCE L

SC-l CRC ERROR L

E35
CRC

C RDS L
C CRCS L

ERROR
(MS)

SC-l CRC ERROR H

+3Vl
8E-0549

Figure 9-15

Parity Error Flags

9-19

Part II
P/O M8323
C RWS L

SC- 2 ERROR L

SC-2
.-REWINDING L

...--

SC - 2 BOT L
C SELR L

...--

SC -1
SELR H

DATA 0
MS
0-3
E9
8235

DATA 1
DATA 2
DATA 3

...--=

(SC-2)

Y rI
+3V

SC-l PARITY ERR L
r--

...

SC-1 FM L

SC-l REC L ENGTH INCORRECT L

...-...--

SC - 1 DATA LATE

DATA 4
MS
4-7
E21
8235

DATA 5
DATA 6
DATA 7

(SC-2)

I' I'

+3V

SC-2 EOT L
SC- 1 EMA 7 INC ERROR H
CWRL L
SC-1 VP ERR H
OC -1 RIC ERR L

SC-l CRC ERR H

MS
AND
SS
8-11
E37
8235

DATA 8
DATA 9
DATA 10
DATA 11

S C - 2 ILLEGAL FUN L
SC-l LRC ERR H
OC-2 RMSR L
OC-2 RFSR L

(SC-2)

r Jr
8E-0552

Figure 9-16

Main Status Register and Second Status Register Multiplexer

9.4.2 Second Status Register
The Second Status Register is read using the RFSR lOT (Figure 8-4). This lOT transfers the condition of the
Second Status Register to the AC for evaluation by the program. The logic elements in the Second Status
Register perform as follows.
9.4.2.1 EMA 7 Increment Error - RE-2 EMA 7 flip-flop (Figure 9-13) is set if the program tries to increment
from Field 7 to Field 0 (RE-l EMA INCREMENT bit must be set). If RE-2 EMA 7 H (Figure 9-10) is applied to
the data input and RE-l EMA INC L is asserted, the RE-2 EMA 7 flip-flop sets, which in turn sets the SC-2
ERROR flag when CB-3 MTTF is set (Figure 9-11). Refer to Paragraph 9.4.3 for a discussion of the EMA INC
logic. The Second Status Register must be read by the program after CB-3 MTTF is set to determine the cause of
the error.
9.4.2.2 Vertical Parity Error (C VPE) - The SC-l VPE flip-flop (Figure 9-15) is set during a read or
read/compare operation if the TS03 detects a vertical parity error and asserts C VPE L. SC-l VPE is cleared
when the next good word is read from tape. If SC-l VPE is set at the end of an operation, the last word in the
record was the one that set SC-l VPE.

9-20

PIO M8323 (SC-l)
~---------------------------------------'---SC-I

STOP L

SC-I CLR STATUS L

C SELR L

+5V

C TUR. L - - - - - - - - - - - - - - - ,

R36
C39

+5V
SC- t CNTL BSY H - - r - -.....
CB-2 CHG OIR L
CB-3 CHG TRANS L - - -

R38
C41
SC-I
1 SETH

+3V'-------~---~

rp;; ;;3~ I

I
I

+5V
+5V

I
C SETHI

J2-J
RE-I GO H

C SOWN L

+3V
RE-I GO H

SC-1 STOP L

CB -3 B TP4 H

I
I
I
L_____ J

SC-I
CNTL BSY H

SC-I
CNTL BSY L

CB-3 MTTF L

+3V
CB-3 CLR ALL L

8E-0567

Figure 9-17

PRESET and SET Pulse Generation Logic

Part II
9.4.2.3 LRC ERROR - The SC-l LRC ERROR flip-flop (Figure 9-15) sets if the TS03 detects an LRC error
when the LRC character is read. The TS03 asserts C LRCE L when an error is detected and sets SC-l PARITY
ERROR and SC-l LRC ERROR.
9.4.2.4 CRC ERROR - The SC-l CRC ERROR flip-flop (Figure 9-15) sets if the TS03 detects a CRe error
when it reads the CRC character from tape. The TS03 asserts C CRCE L when a CRC error is detected to set the
SC-l CRC ERROR flip-flop and the SC-I PARITY ERROR flip-flop.
9.4.3 Main and Second Status Register Multiplexer
The contents of the Main Status Register and Second Status Register (Figure 9-16) are applied to three 8235 ICs.
The 12 bits (Figures 7-4 and 8-6) from the Main Status Register are applied to the Data Bus if an RMSR
instruction is executed by the program and the 4 bits from the Second Status Register (Figures 7-5 and 8-4) are
transferred to the Data Bus if an RFSR instruction is executed by the program. Note that 8 bits of the Function
Register (Figure 9-9) are also applied to the Data Bus when the RFSR instruction is executed by the program.
9.4.4 Extended Memory Address Increment Logic
The EMA bits (6,7, and 8) in the Command Register (Figure 9-10) are used to select one of the memory fields
during a data break operation if bit 6 in the Function Register is a 1. When bit 6 is set, the PDP-8 memory is
treated as continuous memory instead of 4K blocks (Table 8-1). To accomplish this, the EMA bits must be
incremented when the last memory location (7777) in each field is addressed and SC-l COUNT CA L is asserted.
The RE-l EMA INC flip-flop (Figure 9-13) is set when the Current Address Register goes to all Os and RE-I
EMA INC EN L is asserted (bit 6 in the Function Register is I). The EMA bits in the Command Register are
incremented each time bit 0 in the CA Register makes a 1 to 0 transition until the EMA bits are all Is (RE-2
EMA 7). When RE-2 EMA 7 H is asserted, the NAND gate on the output of RE-l EMA INC is disabled. If an
attempt is made to increment beyond Field 7, the RE-l EMA INC ERROR flip-flop is set by RE-2 EMA 7 H
and the set side of RE-l EMA INC. The RE-l EMA INC flip-flop is cleared at TP3 time of BRK RQST and
remains cleared until RE-2 CA 0 L makes a high-to-Iow transition at the end of a memory field.
9.4.5 Control Busy (CNTL BSY)
The SC-l CNTL BSY flip-flop (Figure 9-17) is set by RE-I GO and OC-2 B TP4 when bit 5 in the Function
Register is loaded with a i. SC-l CNTL BSY is cleared when MTTF (JOB DONE) sets at the end of an operation
or by CB-3 CLR ALL.
9.4.6 PRESET and SET Pulse Generator
Figure 9-17 shows the SC-l PRESET and SC-l SET pulse generation logic. The 74123 ICs are -monostable
multivibrators that generate a pulse on the output when the input signal makes a high-to-Iow transition. The
duration of the output pulse is determined by an external resistor and capacitor, i.e., C39 and R36.
SC-l PRESET is a 2.5 jlS pulse (approximate time) that is triggered when the RE-l GO bit (bit 5) in the Function
Register is set. Note that C SELR Land C TUR L must be asserted to enable the gate when starting from a
standstill condition. In a continuous mode of operation, C SDWN L allows the RE-I GO signal to trigger the
74123 IC if CB-2 CHG DIR or CB-2 CHG TRANS are both high (false~. If CB-3 CHG DIR or CB-3 CHG
TRANS are asserted the TM8-E must wait for C SELR Land C TUR L. When SC-l PRESET returns to the
clear state, E2 is clocked, and if the SC-2 ERROR flag is not set' the second 74123 IC is triggered. When the
second 74123 IC is triggered, it outputs a 1.0 jlS pulse (approximate time) that is applied to the TS03 to initiate
tape motion. The E2 flip-flop is cleared by CB-3 CLR STATUS L, the SC-I SET paIse, or the SC-2 ERROR
flag.
9.4.7 Data Late Error Check Logic
The logic shown in Figure 9-18 is used to check the Data Late Error Logic (Figure 9-13). The processor timing is
stopped at TP3 time by the assertion ofSC-l NOT LAST XFER and restarted by asserting SC-l BUS STROBE.

9-22

Part II
PIa M 8323 (SC-2)

SC-2
NOT LA ST XFER L

+5V

R37

C40

C38

OC-2
IBCM L
RE-l GO H

74123
ONE
SHOT
E8

+3Vl

+3V
+3V

R35

74123
ONE
SHOT
E4

SC-2
BUS STROBE L

+3V

E1
E19
">-----IC

CB-2
B TP3 H

8E-0558

Figure 9-18

Data Late Error Check Logic

The 74123 ICs are monostable multivibrators that are triggered on a high-to-Iow transition of the input signal to
generate an output pUlse. The duration of the output pulse is determined by an external capacitor and resistor,
i.e., C40 and R37. When the CKDL instruction is executed by the program, OC-2 IBCM L is asserted to trigger
the first 74123 IC and generate a long timing pulse, which is ANDed with El flip-flop and applied to the
Omnibus as SC-l NOT LAST XFER to stop processor timing. El is cleared at TP3 time and the trailing edge of
the first 74123 causes the second 74123 IC to output a pulse. This pulse asserts SC-l BUS STROBE Land
restarts processor timing. During the time processor timing was stopped, an attempt was made by the TM8-E to
transfer data. The SC-l DATA LATE ERROR flip-flop (Figure 9-13) should be set, because the TM8-E would
normally transfer several words in a time period this long. If the SC-l DATA LATE ERROR flip-flop does not
set, this group of logic is not working properly.
9.5 M8322 CONTROL MODULE
The logic elements of the M8322 Control module are described in the following paragraphs.
9.5.1 Control Function Decoder
The control function decoder (Figure 9-19) is an 8251 IC that decodes the three most significant bits (FRO-FR2)
of the Function Register (Table 8-1) to set up the control logic for the tape transport operation.
NOTE
This decoder is identical to the output control function
decoder (Paragraph 9.2.7).
The 8251 IC is a BCD-to-decimal decoder that decodes bits FRO through FR2 and produces a low on one output
line of the IC for each 3-bit combination, i.e., 1002 causes pin 9 to be low and indicates a write operation. The
outputs of the IC are NORed to generate one signal to represent a combination of operations, i.e., CB-l SP REV
Land CB-l SP FWD L are NORed to generate CB-l SPACE H, to reduce the number of signals that are applied
to elements of the control logic.

9-23

Part II
P/O M8322 (CB-l)
CB -1
OFFLINE L

RE-l FRO H

CB-I
REWIND H
CB -I
READ L
RE-l FR! H

CB-I
R+R/C H

CB -I
R+R/C+WR L

CB-I
RIC L
FR
8251
E43

(CB-l)
RE-I FR2 H

CB-I
WRITE L
CB -1
R+R/C+WR+WFMK L

CB -I
WFM L

CB -1
R+R/C+SP FWD H

CB-I
SP FWD L

CB-,
SP REV L

CB-l
FWD L

CB-I
SPACE H

L - -_ _ _ SP

8[-0568

Figure 9-19

Con trol Function Decoder

9.5.2 Data Break Request Logic
Figure 9-20 shows the logic used to make a BRK RQST during data transfer operations. The CB-l BRK RQST
flip-flop is cleared and CB-l BRK RQST H is asserted when the following conditions exist during read, write,
and read/compare operations.
1.

Write operation and SC-1 SET H are asserted for the first CB-1 BRK RQST at the beginning of a
write operation.

If CB-1 WRITE 1st 7H is low and SC-1 WRS L (write strobe) is asserted during a write operation.
Refer to Paragraph 9.5.10 for origin and discussion of these signals.

If CB-l READ 9 or SC-2 READ 2nd 7 is asserted (Figure 9-20) during a read operation.

If an SBRM instruction (for maintenance only) is executed by the program.

Note that the CB-l BRK RQST flip-flop is set for only write, read, or read/compare operations, which are the
only operations requiring data transfers. CB-1 BRK RQST is set and CB-l BRK RQST H is negated by CB-I
MAC ACC L at TPI time when the BRK RQST is accepted by the processor. The BRK RQST flip-flop is
negated by SC-I DATA LATE, CB-3 CLR ALL, RECORD LENGTH INCORRECT, or CB-l WCOV ifRE-I
ENAB CHK CHAR is not asserted. E24 is cleared at the beginning of each data transfer operation by SC-I
PRESET H so that SC-I RECORD LENGTH INCORRECT, CB-l WCOV, or SC-2 ERROR can be reported
during the operation and stop data transfers if these errors occur.

9-24

Part II

P/O M8322(CB-\}
RE-l
GO H

E40
RE-2
WCO H

+3V

o
E24

CB-3 CLR
STATUS L

SC-l REC LENGTH INCORRECT H

SC - 1 PRESET H
CB-3 CLRALLL--------*-------------------------------~

CB-l READ L
10-----10

BRK
RQST
E24

RE-l WRITE H
OC-? SBRM L
CB-l READ 9 CH L
CB-l READ 2nd 7 L
CB-l WRITE 1st 7 H

+3V
8[-0546

SC-l WRS L

Figure 9-20

Data Break Control Logic

9.5.2.1 Word Count Overflow Logic - The CB-I WCOV flip-flop (Figure 9-20) is set by RE-2 WCO L when bit 0
in the WC Register makes a high-to-Iow transition (Figure 9-9). The set side of CB-I WCOV is applied to NAND
gate E32, which has as its other input RE-I ENAB CHK CHAR L. If bit 4 in the Function Register (Table S-I) is
0, RE-l ENAB CHK CHAR is high and CB-l WCOV (Figure 9-20) sets E24 flip-flop which causes CB-I BRK
RQST to negate and stop data transfers. If bit 4 in the Function Register is a I, RE-I ENAB CHK CHAR L is
asserted and CB-l WCOV does not set E24. This allows two more data breaks to transfer the CRC and the LRC
character on a Read from the transport to memory. CB-l WCOV is cleared by CB-3 CLR STATUS when a CLF
instruction is executed by the program.
9.5.3 Data Break Priority Logic
The priority of the TMS-E (Figure 9-21) is established by removing one of the A jumpers (AO-AS) and installing
one of the B jumpers (BO-B5); thus to establish a 0 priority (the highest priority) for the TMS-E, remove AO and
install BO. By this action all five NAND gates are disabled and the output of E9 is high, which enables E21. This
enables the set side ofE26 to be applied to the CB-2 MAC I and CB-2 MAC 2 flip-flops and allows the TMS-E to
begin a data break operation at TP4, because the TMS-E has been assigned the highest priority. No other
peripheral using the data break interface can have its AO jumper removed and its BO jumper installed. Note that
when NAND gate E34 is enabled at TS4 time, DATA 0 line is low (the TMS-E 80 line is in place). Since all of the
other peripherals are monitoring the Data Bus, one of the NAND gates in their priority logic is enabled and their
BRK RQST is not accepted.

9-25

P/O M8322(CB-2)

BO
DATA 0 ~~i---t"f-----.....

+3V

....._ _0.81

*CB-2
MA, MS LOAD CONT. L

DATA 1 -41.....-.t-o(J

'---0.

DATA 2 ...........-.t-<I
CB-2 MAC ACC L

CB-2
MAC 2 H

. -_ _o.B3

DATA 3 ......-+-<1
*CB-2
MSIR DISABLE L

+3V
DATA 4 -4.....-.t-o(J
*CB -2
BRK CYCLE L

.---0.

DATA 5 -4~-a
·CB- 2
BREAK IN PROG L

DATA6 p
N:l6

* tNT STROBE H

*CB - 2
BREAK DATA CONT L
CB-\ READ L

CB-1
BRK RQST H -----~

*CB-2
CPMA DISABLE

+3V

*OMNIBUS SIGNALS
8E-O!l61

Figure 9-21

Priority and Processor Control Logic with 0 (Highest) Priori~y Installed

Part II

As a further example, consider what happens if the TM 8-E ranks third in the priority structure. This priority is
establisl:ed by removing jumper A2 and installing jumper B2. Because jumpers AO and A 1 are left in place, two
other peripherals can keep the TM8-E.from making a BRK RQST. If the second highest priority peripheral has a
BRK RQST at the same time as the TM8-E, its interface brings the DATA l1ine low during TS4 and NAND
gate E5B is enabled. "fhe output of E5B causes the output of E9 to go low and disable AND gate E21. This
prevents the set side of E26 from setting CB-2 MAC 1 and CB-2 MAC 2 until the other peripheral completes its
data break operation. As implied, priority decreases from 0 through 11, and the TM 8-E is assigned any priority
between 0 and 5 by removing the correct A jumper and installing the correct B jumper.
9.5.4 Processor Control Logic
The logic shown in Figure 9-21 is used to control the PDP-8 processor during a single cycle data break operation.
If E21 is enabled by the priority logic and the set side of E26, CB-2 MAC 1 and CB-2 MAC 2 are set to assert the
Omnibus signals (the Omnibus signals are explained in Chapter 9 of the PDP-8/ E and PDP-8/ M Small Computer Handbook) and take control of the processor for a single cycle data break operation. Note that MA, MS is
not asserted until TPI time. CB-2 BREAK DATA CONT L, which controls direction of data flow on the Data
Bus, is controlled by READ L. During a read operation, CB-I READ L is asserted and data is transferred from
tape to memory. During write and read/compare operations, CB-I READ L is high to transfer data from
memory to the TM8-E. CB-2 MAC I and CB-2 MAC 2 are cleared by the output of AND gate E21 at TP4 time if
BRK RQST is removed. CB-l BRK RQST (Figure 9-20) is cleared by CB-2 MAC ACC L at the same time CB-2
MAC I and CB-2 MAC 2 are set to start a single cycle data break. The TM8-E continues to make break requests
and to transfer data to or from memory until the WC Register reads all Os (WCOV).
9.5.5 MTTF (JOB DONE) Logic
MTTF (Job Done flag shown in Figure 9-22) is set by one of the following conditions to indicate that a specified
function is complete or cannot be performed.

C LRCS (LRC character read from tape at the end of a record) during a read, read/compare, write,
or write File Mark operation.

The C LRCS is read from tape during a space operation.

File Mark, EOT, or WCOV are encountered during a space operation.

The selected transport is given a command to rewind and C RWS is asserted by the selected transport
to indicate rewind has started.

The selected transport is given the CB-I OFFLINE command and C SEL ERR L is asserted by the
TS03.

If lOT LDBR is executed by the program and CB-I WCOV L is asserted.

9.5.6 Interrupt Logic
The Interrupt logic (Figure 9-22) asserts INT RQST L, which is serviced by the processor (i.e., perform a flag
check routine) when one of the following conditions exist.

Bit 6 in the Command Register (Interrupt Enable on SC-2 ERROR flag) is a I and the SC-2 ERROR
flag is set (Figure 9-12). Note that the SC-2 ERROR flag does not set until after CB-3 MTTF is set
unless CB-3 SEL ERR or SC-2 ILLEGAL FUN is set at the beginning of an operation.

Bit 5 in the Command Register (Interrupt Enable on Job Done flag) is a 1 and the CB-3 MTTF flag is
set.

9-27

P/O M8322(CB-3}

+5V
+3V

CB-I WCOV H
OC-2 LDBR L

CB-I REWIND H

CB-I OFFLINE L
CB -3 SEL ERROR H

SC-ISETH

CB-3 CLR STATUS L
SC-2 REWINDING L

SCot FM L
CB-I WCOV L
RE-t rEEF H

+ 3V

CB-t ERROR H
SC-2 EOT L

CB-I READ

E8
PRESET H

CB-3

CB-I SPACE H
~-

1>--"-- INT RQST L

CB-I READ/COMPARE ~.-------\
SC-2 B LRCS L

CB- 3 MTTF L

CLR STATUS L
CB-3 CLEAR STATUS L
8E- 0553

Figure 9-22

MTTF (JOB DONE Flag) and Interrupt Request Logic

Part II

9.5.7 Change Transport Control Logic
Figure 9-23 shows the logic used to generate the CB-3 CHG TRANS L signal when a new transport is selected by
the program. If an LCMR instruction is executed by the program, flip-flop E3 clears (Figure 9-23) and enables
NAND gate E7. At TP4 time, the output of E7 supplies a clock input to E8 and :f any of the inputs (RE-l SEL 0
- RE-l SEL 2 and RE-l B SEL 0 - RE-l B SEL 2) to the E4 Exclusive-OR gates are different, E8 zeroes and
asserts CB-3 CHG TRANS L. The output of E7 ~lso clocks the E3 flip-flop, causing it to set and disable E7. If C
TUR Land C SOWN L are asserted or SEL REM L is negated, NAND gate Ell is enabled at TP4 time. LBCM
L is asserted to load the Buffered Command Register with bits RE-l SEL 0 through RE-l SEL 2 from the
Command Register (Figure 9-10). If CB-3 CHG TRANS is set and C RWS L is asserted, RE-l LBCM Lis
asserted to load the BCM (Figure 9-23). CB-3 CLR STATUS resets the CB-3 CHG TRANS flip-flop. The
Buffered Command Register is also loaded with P E-l SEL 0 through RE-l SEL 2 when CB-3 CLR ALL is
asserted (CLF instruction executed by the program).

P/O M8322CCB-3)

+3V

0
E3

C
+5V

OC -2
LCMR L

CB-3B
INITIALIZE L
CB-2 CHG
DIR L

+3VI

RE-I SEL 2 H = : j

E8
CHG
TRANS

E12
C

E18

CB-3 CHG
CLR L

CHG TRANS L

RE-I B SEL 2 H

~/O
t.1832,:.J
(CB-I)

OC-2
LBCM L

CB -3 CLR
STATUS L

SC-2 REWINDING L
CB-3 B TP4 H

CB-3
CLR
ALL
L

SC-2 TUR L - - - Q
SC-2 SOWN L - - - Q
SC-l

SELR H - - - - - - '

Figure 9-23

8E-0563

Change Transport and Buffered Command Register Control Logic

9.5.8 Change Direction Control Logic
Figure 9-24 shows the logic used to detect a change in direction of tape movem~nt. E35 flip-flop is cleared by SCI SET H at the beginning of all operations except space reverse, rewind, or offline. This applies a high to the
input of E4, which is the same as the high out of E19. E4 has a high output if both inputs are equal and a low
output if the inputs are unequal. If CB-l SP REV L, CB-l REWIND L, or CB-l OFFLINE L are asserted, the
output of E19 goes low and the output of E4 (CB-3 CHG DIR L) is asserted. CB-3 CHG DIR L forces the
control to wait for C TUR Land C SELR L before starting a new operation.

9-29

Part II
P/O M8322 (CB-2)

+3V

CB-l SP REV L
CB - 1 REWIND L
CB - 1 OFFLINE L

8E-0554

CB-3 CHG CLEAR L

Figure 9-24

Change Direction Detection Logic

9.5.9 Write Data Ready Logic
Figure 9-25 shows the write data ready logic. C WDR H is applied to the selected transport when the TM8-E is
ready to start a write operation. SC-I SET Hand CB-I WRITE H enable NAND gate E32 to set flip-flops E23A
and E23B. This enables E27B to assert CB-I WDR H. E23A is cleared when CB-I WCOV L is asserted, which in
turn disables NAND gate E27B and CB-I WDR H goes low. This operation disables NAND gate E27A and C
WDR H goes low. SC-I DATA LATE Land SC-2 ERROR L clear both E23 flip-flops if these errors occur
during a write operation. If a CLF instruction is executed by the program, CB-3 CLR STATUS sets E23A and
E23B to cause CB-I WDR H to go low, which terminates a write operation.
PIO M8322(CB-l)
CB- 3 CLR STATUS L
SC-I DATA LATE L
SC-2 ERROR L

rproM8321Wc-2) - - 1

CB-I WRS L

+5V

CB-I WCOV L - - - - - ;

I
I

SC-I SET H
CB-I WRITE H
CB-l 7 CHANNEL
+ DEN5 H

IL _ _ _ _ _ _ .J
C WDR L
>------e--J2-L L

SC-I 7 CHANNEL L _ _ _ _ _ _ _ _ _ _ _--1
+ DEN5 L
8E -0560

Figure 9-25

Write Data Ready Logic

9.5.10 Read and Write Control Logic
The logic shown in Figure 9-26 is used to generate control signals during read and write operations. Table 9-3
shows the levels of the control signals and the logic used to assert each signal for each read and write operation
on the transports.
The Read and Write control signals are applied to the CB-I BRK RQST control16gic to determine when a BRK
RQST is to be made by the TM8-E (Figure 9-20). CB-I BRK RQST is clocked on the falling edge of the SC-I
RDS or SC-l WRS pulses. Refer to Drawing D-TD-TM8-E-l, sheets I through 8, for the timing diagrams that
illustrate these operations.
9-30

Table 9-3
Read and Write Control Logic Signal Levels
Operation

Read a 9-bit
Character
From
Transport
Read Ist 7-bit
Character
From Transport in Core
Dump Mode
Read 2nd 7-bit
Character
From Transport in Core
Dump Mode
Write a 9-bit
Character on
Transport
Write Ist 7-bit
Character on
Transport in
Core Dump
Mode
Write 2nd 7-bit
Character on
Transport in
Core Dump
Mode

CB-l WRITE
2nd 7 L

Enabled
Gate

high
level

E32

high
level

E37A

Set to 1
state on rising
edge ofC RDS

low
pulse

high
level

E37B

high
level

low
pulse

high
level

E41C

high
level

low
pulse

E41A

Set to 1
state on rising
edge ofC WRS

high
level

low
level

high
level

E41B

Reset to 0
state on rising
edge ofC WRS

SC-l
SC-l
RDSL WRSL

CB-l
READ9L

low
pulse

high
level

low
pulse

high
level

low
pulse

high
level

low
pulse

high
level

low
pulse

high
level

low
pulse

high
level

low
pulse

high
level

low
pulse

·Condition of E40 does not matter.

CB-l READ
1st 7 L

CB-l READ
2nd 7 L

CB-l
WRITE9L

CB-l
WRITE 1st 7 L

Condition
of E40

Reset to 0
state on the
rising edge
ofRDS

Part II
P/O M8322(CB-1)
CB-I
WRITE H
CB-I
RD lat 7 l
SC-I WRS l

CB-\ WR lat 7 H

E40

E39

CB-I
RD 2nd 7 l

CB-I WR 2nd 7 H
CB-I
RD 9l
CB-l 7
CH + DEN 5 H

E39

CB-\ WR 9 H

SC-\ 7 CH
+ DEN5 l
8E-0555

Figure 9-26

Read and Write Control Logic

9.5.11 Data Multiplexer Control Logic
Figure 9-27 shows the Data MUltiplexer Control logic used to select data read from tape, from memory, or
from the AC as input to the Data Register (Figure 9-5). Table 9-2 shows the level ofCB-2 DB MPXA Hand CB2 DB MPXB H for all TM8-E operations.
9.5.12 POWER OK Logic
The POWER OK logic shown in Figure 9-28 is used to assert CB-3 CLR ALL if PDP-8 power falls below a
certain level. If PWR OK H goes low, NAND gate El6 is enabled to assert CB-3 CLR ALL. This initializes all
TM8-E logic and the TS03.

P/O M8322 (CB-2)

CB - I WRITE L - - - ,

CB-2
CB-\ 7 CHANNEL + DEN 5 L

MPXAH

E1B
r----IC

CB-3 CLR ALL L
+3V
oc -2 LDBR L
CB-1
WRITE L

r:----- -,
I P/O M8322(CB-l)

CB-2
+3V

MPXB H

E1B

I
t-T---+---*---tc
I
L _____ ..J
CB-l R+ RC H
+3V
SC-l SET H

8E-0557

Figure 9-27

Data Multiplexer Control Logic

9-32

Part II
P/o M8322(CB-3)
*POWER
OK

lPia M8323(SC-2) ,
I SC-2BOT L
I
IL SP
R~~-(
______ .J

+5V

SC-2 SP REV ,BOT L

Rl
*INIT H

CB -3 CLR ALL L

E15

OC-2 CLF L

I
I
I
I
I
>-----4~ C INIT H I
+5V

+5V

l!/~ !:!.8~ ~O::~

+5V

CB-3
CLR
STATUS L

SC-l
TUR L

r --- ------,

I
I
I

J2 - FF

___ .J

SC-l
SELR H

SC-l PRESET H

E12

Ea
CB-3 SEL ERR L

*OMNIBUS SIGNALS
+3V
8E-0566

Figure 9-28

Initialize and Clear Logic

9.5.13 Initialize Logic
INIT H (Figure 9-28) is asserted when the PDP-8 is powered up or by pressing the CLEAR key on the PDP-8
power control console. Note that INIT H is not the same signal as C INIT H; C INIT H is used to clear all logic
in the TS03 when the following conditions exist.
1.

INIT H is asserted by the processor.

If the tape unit is ready (C TUR L true) when a CLF instruction is executed by the program (CB-3
CLR ALL is asserted).

If a space reverse operation is attempted and transport is at BOT.

If the CLT instruction is executed to assert CB-3 CLR ALL.

9-33

Part III

CHAPTER 10
GENERAL INFORMATION

10.1 GENERAL DESCRIPTION
The TS03 DECmagtape Transport is a synchronous digital tape unit capable of reading and writing industrycompatible tapes and read-after-write operation. The unit is designed for applications requiring high reliability at
moderate tape speeds.
The TS03 is designated as either a master transport (TS03M) or a slave transport (TS03S). The TS03M comprises
a TS03S and a M8920 adapter module with the M8920 adapter interfacing up to two TS03S slave units (Figure
11-1). Thus a TM8-M System will have one TS03M Transport and possibly one TS03S Transport.
The TS03 contaios all the electronics necessary to accept, format, and record data and to retrieve, check, and
output data. To accomplish this, the TS03 performs the following functions:
Tape motion control
Tape formatting
Parity generation
Cyclic redundancy check (CRC) character generation
Longitudinal redundancy check (LRC) character generation
Interrecord gap control
Even parity zero character conversion
Status monitoring
Parity, CRC character, and LRC character error detection
File protection
The TS03 is a 9-track, 800 bpi unit with a standard tape speed of 12.5 in. per second and a data transfer rate of 10
kHz.
10.2 PHYSICAL DESCRIPTION
The transport portion of the TS03 is completely housed in a 19 in. wide by 17 in. deep by 9 in. high chassis; the
adapter portion is contained on a hex height module which mounts just below the chassis in a special mounting
bracket. The transport (Figure 10-1) contains the read/write and motion control electronics. The adapter module
(Figure 10-1) contains the formatting, parity, CRC, gap control, and error detection electronics.
10.3 ELECTRICAL AND MECHANICAL SPECIFICATIONS
Tape (Computer Grade)
Width
0.5 in. (1.27 cm)
Thickness
1.5 mils (0.038 mm)
Tension
8.0 oz (227 g)
Reel Diameter
Capacity
Reel Hub

To 7.0 in. (17.78 cm)
600 ft (182.40 m)
3.69 in. (9.37 cm) dia. (per industry standards)

10-1

Part III

Reel Braking

Dynamic

Recording Mode
(I ndustry-Compatible)

NRZI

Tape Drive

Single capstan

Tape Speed

12.5 in.jsec

Instantaneous Speed Variation

±3%

Long-term Speed Variation

±1%

Start/Stop Displacement

0.1875 in. (0.476 cm)

Start/Stop Time at 12.5 in./sec

30 ms

Rewind Speed

75 in./sec(190.5 cm)

Magnetic Head Assembly
(Write to Read Gap Displacement)
Dual Gap Nine-Track
Read After Write
Interchannel Displacement Error
(Measured with Master Skew Tape)
Write
Read

150 ~in. (3.8 ~m) maximum
150 ~in. (3.8 ~m) maximum

Erase Head

Full width

Beginning-of-Tape (Load Point) and
End-of-Tape Reflective Strip Detection
(Industry-Compatible)

Photoelectric

Broken Tape Detection

Photoelectric

Dimensions (Figure 10-2)
Transport Mounting (Horizontal)
Height
Width
Depth (From Mounting Surface)
Depth (Overall)
Weight
Shipping Weight

Standard 19 in. (48.26 cm) RETMA rack
8.72 in. (22.14 cm)
19.00 in. (48.26 cm)
14.38 in. (36.53 cm)
16.88 in. (42.88 cm)
35 lb (15.85 kg)
45 lb (20.38 kg)

Operating Environment
Ambient Temperature
Relative Humidity (Noncondensing)
Altitude

+2 0 to +50 0 C
15% to 95%
To 30,000 ft (9120 m)

Power Requirements

0.15 in. (0.38 cm)

115/230 Vac, 50 to 500 Hz, single phase
200 V A nominal; 300 VA maximum

10-2

Part III

7461-2

Figure 10-1 TS03 Transport and TS03 Adapter Module (M8920)

10-3

Part III
1.00
I-- (1.54)

17.00

(U.l~)

,,'

FS~

''')'I

I:
L~L ,j L ~ L. ~ .. oJ

L.~L.~L""'L..IL~L."'1,;;J

~ fl rl fl r1rl rl

rlflrlrlrlrlrl

L.~

0
l-

I-

I\,

r
et(S)
!IOTE: DIMENSIONS FUS! 5HOW!! A'" III JIICHES.
0111£11510115 III PAREIITHESES ARE III CEIITIMETUS.

MOUNTING
SURFACE

'"r

(l)

CONTROL PANE L

~ETAIN:

HINGE (PULL OUT LOIIER
END OF PANEL FOR ACCESS
TO RACK HOUNTING SCREWS)

"OUNTING HOLES AIt[ FlItt
ZERO NONTILT TYPE SLIDE
NO. C30e-14 (NOT SUPPLIED

.u
~.----

.--

-,-

~:;:>

""u"nN'
SUAFAGE

IIITH UNIT) (DIIIENSIONS
TYPICAL ON 80TH SIDES)

--- ----- ----------- 1
to...-

~--

DUST COYER OPEl'
TO APPAOXIMATEU
110 DEGREES.

~tJ·SE£ DETAIL "A'

--:+

o 0

8.72
(tz.14)

5.06

(12.85 )

:;.

:. B
I

l.fs
t-- (3.18)

.19

(.48)
~

3.62, _ _....._ - 3.62
(9.19)
(9.19)

___________________________ 14.38
(36.53)

1.40
(3.55 )

----------------+e_
16.88
(42.88)

DETAil "A"
TYPICAL SLOT
PATTEIII

1.48 Tn
(3.75)

14--------------------(!::
..
~ )-------------------.l
11-3046

Figure 10-2 TS03 Transport
Physical Dimensions
10-4

PART III
TS03 DECmagtape TRANSPORT

CHAPTER 10 GENERAL INFORMATION
CHAPTER 11

THEORY OF OPERATION

CHAPTER 12 DETAILED LOGIC DESCRIPTIONS
CHAPTER 13

PARTS IDENTIFICATION

APPENDIX I TRANSPORT SIGNAL DESCRIPTIONS AND INTERFACE INFORMATION
APPENDIX J DEC/VENDOR TS03 TRANSPORT PART NUMBERS

Part III

CHAPTER 11
THEORY OF OPERATION

11.1 INTRODUCTION
This chapter provides a complete description of the TS03 to the functional block level. Functionally, the TS03
can be divided into four major blocks (Figure 11-1):
Adapter Logic
Transport Control Logic
Servo System
Data Section
The adapter logic interfaces the TS03 transport to the controller. In response to commands from the controller,
the adapter:
1.

Formats the data on the tape.

Generates motion signals to start and stop the tape drive, to move the tape forward or backward.
and to move the tape at normal read/write speed or at a higher speed during a rewind operation.

Generates strobes to write data and CRC, LRC, and file mark characters on tape.

Generates write strobes to notify the controller to send the next write character.

Transmits read strobes received from the tape transport out to the controller.

Generates parity and the CRC characters for recording on the tape.

Performs parity, CRC, and LRC error checks on all read data.

Detects file mark records on the tape and notifies the controller.

The Control logic:
1.

Controls ramp voltage to the servo, thereby controlling direction and speed of tape movement.

Generates control signals to the data section which enable and disable the read and write amplifiers.

Controls the erase head.

11-1

TS03M TAPE TRANSPORT

,-----I

TS03S TAPE TRANSPORT

I
I I
I

SERVO
SYSTEM

CAPSTAN
MOTOR

REEL
MOTOR POWER
BUFFER ARM
FEEDBACK

ON LINE

WDR

REEL
MOTOR

LOAD
REWIND

L_-,

...

SEL (2:0)

RAMP
VOLTAGE

DRIVE SEL
SW GND

SET

WD(7:0)

TACH
FEEDBACK

L_j - - - - -,

TO/FROM CONTROLLER
INIT

CAPSTAN
MOTOR POWER

CONTROL
PANEL
SWITCHES

MASTER
SELECT
SWITCH

.I ,/'"

SEL DRIVE (0:\)
FWD
MOTION COMMANDS
(FWD, REV, WRE,
RWD, WXG, WFMK)
WRS

I
I

7 CH

REV

MOT

WRE

LTCH

RUN CMD

STATUS (LOAD POINT, END
OF TAPE ,RWNDG,
XPAT ROY, WRLCK II

ADAPTER
LOGIC
(M8920)

RDS

ERASE
HEAD

MOT

TRANSPORT
CONTROL
LOGIC

TUR

WRITE READY

RWND PLS
RD (7:0,P)

AT LOAD POINT
SELECTED a ON LINE

OFF LINE PLS

DRIVE BUSY

DRIVE (0:1) ON LINE

SELR
RWS
BOT
EOT
SOWN

REC

LRC PLS

LRCS

WD (G:7,P)

CRCS
FMK

K
A

RD (·G: 7, P )

ERRORS( LRCE,CRCE,VPE)

..... DRIVE (0:1) RD STRB

WRL

WRITE
HEADS

DATA
SECTION

K
L ___
---- -- -- --- ---

Figure 11-1 TS03 Block Diagram

READ
HEADS

~
11- 3068

Part III

The servo system consists of the electronics and electromechanical components that are required to advance the
tape past the magnetic heads at accurately controlled speeds while maintaining constant tape tension. The servo
system is composed of two subsystems: the capstan subsystem, which drives the tape at accurately controlled
speeds, and the reel servo subsystem, which maintains constant tape tension.
The data section consists of read and write amplifiers, output drivers, and tirr:ing and control logic. The data
section controls the1read/write heads and generates a read data strobe that is used by the adapter logic to transfer
data out to the controller.
11.2 TRANSPORT OPERATIONS
The TS03 performs three basic types of operations: write, read and rewind; all other operations are simply
variations. The following paragraphs explain how these operations are performed (Figure 11-1).
Once the controller initializes the adapter logic by asserting INIT, the controller must select the transport (drive 0
or 1) and parity sense (odd or even) before any operations can be performed.
When the controller selects a transport via the SEL lines, the adapter asserts SEL (select) to the selected transport
and, if the transport is on-line (ON LINE indicator illuminated), DRIVE ON-LINE is asserted to the adapter
and the adapter asserts SELR (select remote) back to the controller. If the selected transport is ready (i.e., tape is
loaded and is not rewinding or advancing to the load point (BOT marker», the transport also asserts XPRT
RDY (transport ready) to the adapter, causing the adapter to assert TUR (tape unit ready) to the controller.
With these conditions satisfied, the controller can now raise the command lines required to perform a given
operation and asserts SET to initiate that operation.
11.2.1 Write Operation
To perform a write operation, the controller raises WRE (write enable) and FWD (forward) and asserts SET.
The adapter logic responds by asserting FWD MOT (forward motion) and WRE L TCH (write enable latch) to
the transport control logic, begins to count off a delay, and clears TUR to the controller. The transport logic
responds by asserting WRITE READY and SEL DRIVE to the data section and a ramp-up, forward motion
voltage to the servo system. Hence the servo system starts moving the tape forward at normal speed and the data
section is enabled. The adapter then completes the delay count. (The delay allows the tape to accelerate to normal
operating speed and ensures that the heads have moved well past the BOT marker when starting from a BOT
position.) Assuming the controller will have placed a character on the write data lines and asserted WDR (write
data ready) to the adapter when the delay expires, the adapter immediately generates a parity bit and a write
strobe (REC) to load the data character with parity into the data section. The data section immediately records
the character, reads it back, and places it on the read data lines to the adapter along with a read strobe. The
adapter then checks the read character for parity errors and outputs the character back to the controller, along
with a read strobe (RDS). The adapter then asserts a write strobe (WRS) to the controller to request the next
character. The controller then places the next character on the write data lines. This process is repeated over and
over until the last character is recorded and the controller clears WDR.
When WD R clears, the adapter generates two more write strobes to properly terminate the record. REC is
asserted along with the CRC character to the data section for recording. Then the LRC PLS is generated to the
data section to generate the LRC character, which is then recorded. The adapter reads the two check characters,
outputs them to the controller, along with the CRC and LRC strobes (CRCS and LRCS), and checks for CRC
and LRC errors. If a CRC or LRC error is detected, the respective error line is also asserted to the controller.
Next, the adapter terminates the write operation by clearing FWD MOT to the transport control logic, asserting
SDWN (settle down) to the controller and counting off deceleration delay. When FWD MOT clears, the transport control logic applies a ramp-down voltage to the servo system and clears the WRITE READY and SEL
D RIVE lines to the data section. Hence, the servo system stops the tape and the data section stops writing and
reading data.

11-3

Part III
When the deceleration delay expires, the adapter asserts TUR and clears SOWN to the controller. Thus the TS03
is ready to perform the next operation.
11.2.2 Read Operation
To perform a read operation, the controller raises FWD and asserts SET. The adapter logic responds by asserting FWD MOT to the transport control logic, starting the delay count and clearing TUR. The transport control
responds by asserting SEL DRIVE to the data section and a ramp-up v~ltage to the servo system. The servo
system then begins to move the tape forward, and the read portion of the data section is enabled. The adapter
completes the delay count and begins to accept read data, along with read strobes from the data section. Each
character read is checked for a parity error and output to the controller, along with a read strobe. Upon reading
the final two characters (normally a CRC and LRC\character) and checking for errors, the adapter clears FWD
MOT, asserts SOWN to the controller, and begins to count off a deceleration delay. When FWD MOT clears,
the transport control logic applies a ramp-down voltage to the servo system to stop tape motion and clears the
SEL DRIVE line to the data section to stop reading. When the deceleration delay expires, the adapter asserts
TUR and clears SOWN to the controller.
11.2.3 Rewind Operation
To perform a rewind operation, the controller asserts RWD (rewind) and SET. The adapter logic responds by
asserting R WND PLS to the transport control logic. The transport control logic responds by clearing XPRT
ROY, asserting R WNDG to the adapter and applying a high-speed reverse, ramp-up voltage to the servo system.
The adapter asserts R WS (rewind status) to the controller while the servo system rewinds the tape past the load
point. The transport control logic then applies a forward motion ramp-up voltage to the servo system, which
moves the tape forward to the load point and stops the tape. The transport control logic then clears RWNDG
and asserts LOAD POINT and XPRT RDY to the adapter. The adapter clears RWS and asserts TUR to the
controller.
11.3

FUNCfIONAL BLOCK DIAGRAM DESCRIPTION

11.3.1 Adapter Logic
Figure 11-2 is a block diagram of the adapter logic. The diagram separates the adapter logic into six areas and
shows adapter data and signal flow.
As stated previously, the adapter logic enables software control of the TS03 DECmagtape Transport. Referring
to Figure 11-2, note that the control logic responds to inputs from the controller by generating control signals for
the write logic and the read logic as well as control signals for the tape transport. These control signals control
the reading and writing of data, tape motion, and interrecord gaps. In addition, the control logic provides clock
signals (TIME PLS 1,0) for the adapter logic, monitors transport status lines, and initializes the adapter logic
whenever INIT is asserted by the controller.
In response to inputs from the control logic and the controller, the write logic and read logic transfer data to and
from the tape transport. The write logic accepts write data from the controller and monitors the controller C
WDR {write data ready) line. If the C WDR line is true, the write logic generates parity, write strobes (REC),
CRC characters, LRC strobes (LRC PLS), and the file mark character and outputs this information to the tape
transport via the transport drivers for recording. The read logic accepts read data from the transport and monitors the RD STRB line. Using RD STRB and the read data, the read logic detects data records and file mark
records. In addition, checks are made for parity, CRC, and LRC errors.
11.3.1.1 Control Logic - The control logic can be divided into nine logic sections (Figure 11-3). Each section
performs a specific function to perform the eight different operations of which the control logic is capable. Table
11-1 lists those operations and indicates the commands that must be issued by the controller to initiate them.

11-4

Part III

BWD (7:0. P)

.
~

C WDR
C WFMK

'ROM

CONTROLLER

{

WD (7:0)

..
r

PEVN LTCH

B LRC PLS

B REC
TRANSPORT
DRIVERS
(04.010)

WRITING

B REV MOT

B REV MOT
B RWND PLS

C SET

REV

MOT

B RWND PLS

C INIT

RWNO PI.S

B OFF LINE PLS

C SEL (2:0)

OFF LlN[ PLS

B OFF LINE PLS

CFWD

SEL 1

B SEL DRIVE I

C REV

SEL 0

B SEI. DRIVE 0

WRE LTCH

B WRE LTCH

C PEVN
CWRE

CONTROL
LOGIC
(03.05.06.07.09)

B WRE LTCH

READING
DRIVE SEL SW GND

C WFMK

B DRIVE 0 ON LINE

C RWD

B DRIVE I ON LINE

} 'RO"

TAPE
TRANSPORT

BOT

B LOAD POINT

EOT

I B LOAD POINT

(FROM
WRITING
WR ITE LDGIC)
INHIBIT STATUS

RWS

B END OF TAPE

ROY

I B END OF TAPE

RD STRB

B RWN DG

C SELR

ON LINE

C EOT

EDT

C RWS

RWS

PEVN LTCH

C SOWN

SOWN

MOT

C TUR

TUR

TIME PLSO

I B RWNDG

LRC RD TIME

RECORD

IN H VPE DEl

SET

ENB LRCE DET

FWD LTCH

EOR TIME

CRC RDTIME

C CRCS

CRC RD TIME

COMP RD STRB

C RDS

COMP RD STRB

C FMK

FMK

CONTROLLER
DRIVERS
(03)

B FWD MOT

MOT

C 7CH

C LRCS

.-.J

TO
DRIVE 1
AND DRIVE 0

B FWD MOT

FWtl

C WXG

C WRS

B REC

REC

TIME PLS 1.0

FROM
CONTROLLER

B LRC PLS

LRC PLS

MOT

TO CONROLLER
DRIVER

'")

V
WRITE
LOGIC
(010.0111

SET

...

BWD(7:0.P)
WD(7:0,P)

B XPRT ROY

TRANSPORT
RECEIVERS
(04)

I B XPRT ROY
B DRIVE 0

I B DRIVE 1 RD STR B

ACT

RO
(7:0, P)

h
A

FILE

READ
LOGIC
(08.012.013)

FROM
DRIVE 1
AND DR IVE 0

RD STR B

B RD(7:0, p)

I BRD(7:D,P)

1
I

B WRLr.K

I B WR LCK

MARK DETECTED

EIGHT SPACES
C VPE

BAD PARITY

C LRCE

LRC REG NOT ZERO

C CRCE

CRCE

AC RD (7:0.P)

..,IRD 7:0,P)

... C BOT

.... BOT

CWRL

WRL

11-3066

Figure 11-2 Adapter Block Diagram

11-5

Part III

C SEL fJ
FROM{
CONTROLLER

C SEll

STATUS
INHIBIT
LOGIC

INHIBIT STATUS

TO CONTROLLER
DRIVERS

FROM

C SEL 2

CONTROLLER

DRIVE SEl SW GND

CHANGE UNIT

(03)

FROM
TRANSPORT

{ . DR'VE g ON LINE
B DRIVE 1 ON LINE

ON LINE TO CONTROLLER
DRIVERS

TAPE DRIVE
ON LI NE

DE1 ECT LOGIC
(05)

~L~J

MOT

FROM
CONTROLLER

C INIT

FROM POWER
SUPPLY

AC LO

SYSTEM
INITIAliZATION
(06)

TO TRANSPORT
DRIVERS

SYSTEM RESET
~

EOT

f--=-- CONTROlL ER

PWR OK

DRIVERS

EOT
STATUS
REGISTER
(05)

(FROM TRANSPORT RECEIVERS)~
P.EV MOT
FWD MOT

CHANGE UNIT

RWND PLS

EXT CLOCK
MAINT INPUTS'f
NOT USED
TESTING
DURING NORMAL
RESET CTR
OPERATION

TIME PLS 1

TIME PLS 1
CLOCK
LOGIC
(06)

TIME PLS"
I--

~}TO
TRANSPORT

LTO FIG
11-6

DRIVERS

TRANSPORT
RECEIVERS

TAPE
MOTION
STATUS
LOGIC
1D5)

ROY
MOT

SYSTEM RESET
DRIVE STOPPED

C FWD

FROJ
CONTROLLER

C REV
C PEVN

CHANGE UNIT

RWS....

FROM {

COMMAND
STATUS
REGISTER
(07)

CWRE

~}
SOWN

TO
CONTR OLLER
DRIVE RS

REV MOT

FWD MOT

~(OT
FIGURES
PEVN LTCH }TO
11- 6 a 11-9
FWD LTCH
• TO FI GURE 11-9

PEVN LTCH
FWD LTCH
MOT
WRE LTCH

TO
CONTROLLER
DRIVERS

TIME PLS"

LRC RD TIME •
INH VPE DET

MOT
ENB LRCE OfT

PWR OK

L. TO FIGI'-6S1'-9

SYSTEM RESET

:
C WRE

(FROM FIGURE 11-9)

TIME PLS 0

(FROM FIGURE 11-6) WRITING

MOT
C WXG
CWFMK
CONTROLLER
FROM!
C RWD
C SET
FROM
TRANSPORT
RECEIVERS

BOT

RWND PLS
READ/WRITE
DRIVE STOPPED
CONTROL
LOGI C
ROM/DELA Y CTR ~ (TO FIGURE1'-9 S 11-6)
(07)

READING

RECORD ACT

SHU T
DOWN
LOGIC
(09)

TO
-. TRANSPORT
DR IVERS

FROM TRANSPORT
RECEIVERS

EOR TIME
CRC RD TIME~

TO FIGURE
COMP RD STRB } 11-9

RD STRB
RD ClR

(TO TRANSPORT RECEIVERS S FIGURE 11-6)

OFF LINE PLS

(TO TRANSPORT DRIVERS)

RD CLR
08 -1698

Figure 11-3 Control Logic Functional Block Diagram

11-6

TO
CONTROLLER
DRIVERS

Part III
Table 11-1
Operations Versus Commands Required

Operations

Write Extended
Gap (WXG)

Controller Commands Required
Write File
Write Enable
Forward
(WRE)
(FWD)
Mark
(WFMK)

Rewind, Off-Line

Reverse
(REV)

Rewind
(RWD)

Rewind

Write
Write-with-extended
In terrecord-Gap
Write File Mark

Read

Space Forward

Space Reverse

To prepare the control logic to receive commands, the controller asserts C INIT. Asserting C INIT generates
SYSTEM RESET, which clears the command status register and resets the motion flip-flop in the read/write
control logic.
The controller then issues the commands by asserting the command lines and generating a C SET pulse. The
command processing sequence that results is illustrated in Figure 11-4. Note that different operations require
that different delays be generated by the delay counter (Table 11-2). These delays are incorporated for the
following reasons:

To allow time for the tape to accelerate to normal operating speed from a stopped condition.

To allow time for the tape to decelerate from normal operating speed to a stopped condition.

To allow time for the transport to move the tape BOT marker well past the read/write heads when
starting from the BOT position.

To enable the writing of industry-compatible extended interrecord gaps and file marks.

Note that the rewind operation does not require a delay.
Due to the similarities of the eight operations performed by the control logic, the following paragraphs will
explain first a write operation and then point out the differences between a write operation and the other
operations.

11-7

Part III
WRITE. WRITE FMK. READ
SPACE FWD. SPACE REV.
WRITE XIRG

LOAD DELAY
INTO DELAY
COUNTER
ANDS~T

(SEE NOTEI

MOTION EN·
ABLE FLlP·FLOP

ISSUE SET
PULSE

NO
TRIGGER
OFF LINE
ONE SHOT

YES
NO

TRIGGER
REWIND
ONE-SHOT

NOTE:
PERFORM
OPERATION

NOTE 1: SEE "COMMANDS AND CORRESPONDING
DELAYS" TABLE FOR ROM OUTPUT
AND DELAYS ASSOCIATED WITH EACH
COMMAND.

11·3040

Figure 11-4 Commands Processing Sequence Flow Diagram

Table 11-2
Commands and Corresponding Delays
Commands

ROM Address

2s Complement
of Delay

Delay (ms)

Delay (in.)

(WFMK + WXG)· BOT
WRE· FWD· BOT
(WFMK + WXG)· BOT
FWD· BOT
WRE·FWD·BOT
FWD·1rnT"
DRIVE STOPPED·WRE
DRIVE STOPPED·WRE

14 8
16 8
48
12 8
68
28
24 8 ,26 8
20 8 ,22 8

20000
25000
31400
33400
37230
37423
37754
37777

819.2
563.2
332.8
256.0
35.7
23.7
2.0
0.1

10.05
6.85
3.97
3.01
0.256
0.117
0.025
0.001

11-8

Part III
Write Operation (Figure 11-5) - To initiate a write operation, the controller must raise the C WRE and C FWD
lines and issue the C SET pulse. Assuming the tape is positioned at the BOT marker, the control logic responds to
these inputs by presetting the delay counter to 25000 and then asserting MOT, WRE LTCH, and FWD MOT
and clearing TUR. When FWD MOT asserts, the tran~port begins to move the tape forward while the delay
counter counts off the delay period. The transport actually moves the tape forward 6.85 in. (17.4 cm) before the
delay period expires. This distance ensures that the tape has reached operating speed and is well past the BOT
marker and that start-up transients and noise have subsided. When the delay period expires (counter equals
400(0), the READING line asserts, enabling the read and write logic. When the controller raises the C WDR
(write data ready) line, a write strobe (REC) is generated and the data is actually written on the tape. A write
strobe (C WRS) is sent to the controller 50 p,S later, requesting the next character. While the write head records
the data, the read head reads the data back. Each time the read head detects a character, a RD STRB (read
strobe) is sent back to the read logic. Upon receiving three read strobes (minimum record length), the read logic
asserts RECORD ACT to the shutdown logic. The recording operation then continues until all the data is
recorded and the controller clears the C WDR line. When C WDR is cleared, WRITING (which is controlled by
the write logic, Figure 11-6) clears and the shutdown logic is enabled.

When the shutdown logic detects a gap three character times long between successive read strobes, CRC RD
TIME is asserted to the read logic and the controller drivers. If the record was recorded correctly, the next two
characters detected by the read head should be the CRC character and the LRC character in that order. The read
strobe resulting from the CRC character clears CRC RD TIME and asserts LRC RD TIME to the controller
drivers. The read strobe resulting from the LRC character clears LRC RD TIME and eight character times later
the shutdown logic asserts RD CLR. If the CRC and LRC characters are not detected by the read head, the RD
STRB will be generated internally by the shutdown logic; however, the shutdown will wait 56 character times
instead of the normal 8 before asserting RD CLR. The extra delay is provided to ensure that the read head has
passed the end of the record before the tape stops in the event of a bad tape spot or a write circuitry malfunction.
The assertion of RD CLR loads the delay counter for a delay and clears READING. In this case, because it was
a write operation, the counter is set for a delay of 2 ms. In the case of read operations, the counter is set for a 0.1
ms delay. A smaller delay is used during a read operation to ensure that any unwanted data that may be written
on the tape by the write heads while turning off is erased. When the delay expires, the read/write control logic
clears MOT, WRE LTCH, and FWD MOT. When MOT is cleared, the tape motion status logic asserts SDWN
(settle down) to the controller drivers to indicate that the transport is iri the process of stopping. Clearing WRE
LTCH and FWD MOT actually causes the transport to stop the tape. The read/write control logic delay counter
then counts off a 32 ms deceleration delay (which allows time for the tape to stop) and asserts DRIVE STOPPED
to the tape motion status logic. The tape motion status logic then clears SDWN and asserts TUR (tape unit
ready) to the controller drivers, indicating that another operation may be performed.
Read and Space Forward Operations - The differences between a BOT write operation and a BOT read operation

or BOT space forward are as follows:
1.

The controller asserts C FWD but does not assert C WRE and C WDR.

The read/write control logic delay counter is preset to 33400 and the tape is only advanced 3.01 in.
(7.65 cm) instead of 6.85 in. (17.4 cm) before the delay expires and READING is asserted.

C WRE is not asserted so the transport write logic is disabled.

C WDR is not asserted so the adapter write logic is disabled.

The delay counter counts off a 0.1 ms delay before clearing MOT and FWD MOT.

11-9

1 -+ COMP RD STRB
0-+ CRC RD TIME
1 -+ LRC RD TIME
RESET SHUT
DOWN CTR
TIME PLS 0 STEPS
SHUT DOWN CTR.
READ STROBE
RESETS SHUT
DOWN ICTR BEFORE
IT REACHES A
COUNT OF THREE

---

1-+ MOT
1 -+ FWD'MOT
1- WRE LTCH
0-+ DRIVE STOPPED
0-+ TUR

2MS DELAY

O-MOT
0- FWD· MOT
0-+ WRE LTCH
1-SDWN

1 -+ COMP RD STRB
0-+ LRC RD TIME
RESET SHUT
DOWN CTR

READ HEAD
READS
CHARACTER
BACK

32MS DELAY

563.2MS
DELAY
S.6MS
DELAY

NOTE:

ENABLES

DURING WRITE OPERATION
THE WRITE HEAD RECORDS
THE DATA ON THE TAPE
AND THE READ HEAD READS
THE DATA AFTER IT IS
RECORDED.

C
"·3036

Figure 11-5 Control Logic BOT Write Operation Flow Diagram

Part III
SET
C WD (7:0)

."")

FROM}
CONTROLLER
FROM}
FIGURE
11-3

PEVN LTCH

WD(0:7,P) ..
PARITY
GENERATION
AND ZERO
CHARACTER
CONVERSION
LOGIC

I--

---J

\0111

COMPIL.ER
LOGIC
(011)

~
~

IlcRcle:7 P)",

WD(7:0,P) .... TO
TRANSPORT
DRIVERS

Jo..

)
III'"

WRITE
WR PLS
C WDR
FROM}
CONTROLLER

C WFMK

WFMK LTCH

TIME PLS 0
TIME PLS I
FROM]
FIGURE
11-3

READING

WRITE
STROBE
GENERATION
LOGIC
(010)

MULTIPLEXER
(011)

LRC PLS
REC

SET
MOT

DATA

CRC WR TIME

WRITING

} TO
TRANSPORT
DRIVERS
} TO FIGURE 11-3
AND
CONTROLLER
DRIVER
~

08-1696

Figure 11-6 Write Logic Functional Block Diagram

Write File Mark Operation - The differences between a BOT write operation and BOT write file mark operation
are as follows:

In addition to C FWD and C WRE, the controller asserts C WFMK but does not assert C WDR.

The read/write control logic delay counter is preset to 20000 and the tape is advanced 10.05 in. (25.5
cm) before the delay expires and READING is asserted.

C WFMK enables the adapter write logic to write the file mark character and to generate the LRC
PLS which causes the transport data section to write the LRC character.

Write Extended Interrecord Gap Operation - The only difference between a BOT write operation and a BOT
write-with-extended-interrecord-gap is that the tape is advanced 10.05 in. (25.5 cm) instead of 6.85 in. (17.4 cm)
before the delay expires and READING is asserted.
Space Reverse Operation - The differences between a BOT write operation and a space reverse opperation are as
follows:

The controller asserts the C REV line only.

The read/write control logic delay counter is preset to 37423 and the tape is moved backward only
0.117 in. (2.97 mm) before the delay expires and reading is asserted.

C WDR is not asserted so the adapter write logic is disabled.

11-11

Part III

Because there are no CRC and LRC characters at the beginning of a record, two CaMP RD STRB
pulses must be generated internally by the shutdown logic and the shutdown counter counts off 5.6
ms before asserting RD CLR.

The read/write control logic deceleration delay is 0.1 ms.

Rewind Operations - The differences between a BOT write operation and a rewind off-line operation are as
follows:
1.

The controller asserts C WRE and C RWD but does not assert C FWD and C WDR; thus OFFLINE PLS and R WND PLS are generated and sent to the tape transport, initiating a high-speed
rewind operation and extinguishing the transport ON LINE indicator.

The read/write control logic delay counter is preset for no delay and the motion flip-flop is held in a
reset condition; therefore, DRIVE STOPPED is asserted immediately to the tape motion status logic.

At the tape motion status logic, RWS (rewind status) asserts and ROY clears, causing TUR to clear
and RWS to assert to the controller. If the transport is still selected when the rewind is completed,
RWS clears and ROY asserts, causing RWS to clear and TUR to assert.

The rewind operation differs from the rewind off-line operation in that C WRE is not asserted by the controller;
therefore, OFF-LINE PLS is not generated and the transport ON LINE indicator remains illuminated.
The only control logic functional blocks not fully discussed in the preceding paragraphs are listed below and
discussed in the following paragraphs.
Tape Motion Status Logic
Tape Drive On-Line Detect Logic
EaT Status Register Logic
Status Inhibit Logic
Tape Motion Status Logic - This logic determines the tape motion status and generates outputs t9 the controller
drivers to notify the controller. The logic monitors MOT and DRIVE STOPPED from the read/write control
logic and the RWS and ROY inputs from the tape transport. If the transport is on-line with tape loaded and is
not rewinding or advancing to the load point, the transport asserts ROY as soon as it is selected by the adapter
(B SEL DRIVE asserted). When ROY is asserted by the transport, the tape motion status logic asserts TUR to
the controller drivers.

The tape motion logic essentially operates in two modes: the rewind mode and the nonrewind mode. If the
controller issues a nonrewind command (for example, a write command), the M aT input is asserted and DRIVE
STOPPED is cleared, causing the TUR output to clear. When the operation is completed, the MOT input clears
and SOWN asserts. DRIVE STOPPED asserts 32 ms later, SOWN clears, and TUR asserts. If the controller
issues a rewind command, the transport clears ROY and asserts RWS; MOT and DRIVE STOPPED remain
unchanged, i.e., cleared and asserted, respectively. In response, the tape motion status logic clears TUR and
asserts RWS. The transport then rewinds the tape past the BOT marker, ciears RWS, advances the tape forward
to the BOT marker, and asserts ROY and BOT. The tape motion status then clears R WS and asserts TUR.
The CHANG E UNIT input to the tape motion status logic merely serves to reset the logic each time a new drive
is selected by the controller.

11-12

Part III
Tape Drive On-Line Detect Logic - This logic monitors C SEL 2 from the controller, MOT from the read/write
control logic, and DRIVE (1 :0) ON-LINE and DRIVE SEL SW GND from the master and slave tape
transports.
The DRIVE SEL SW GND input determines which transport is drive 0 and which transport is drive 1 as
addressed by the controller. The unit select switches located on the master and slave transport front panels
control this input. If an even number switch is installed in the master tape transport, it is addressed as drive O. If
an odd switch is installed in the master transport and an even switch in the slave, the master is addressed as drive
1. If no switch is installed in the slave transport, the master is addressed as drive O. If the master is the only
transport in the system, it is addressed as drive O.
In accordance with the controller input, the tape drive on-line detect logic selects either the master or slave tape
transports by asserting SEL 1 or SEL 0 provided the motion flip-flop is reset. If the transport selected is on-line
(ON LINE indicator illuminated) the ON-LINE output is asserted to the controller drivers and C SELR is
asserted, notifying the controller that the designated transport is on-line and has been selected. If, for example,
the master transport is drive 0, the controller must clear C SEL 2 to select the master transport. Note that the
tape drive on-line logic will not select a new transport while the motion flip-flop is set.

EOT Status Register Logic - The EOT status register logic monitors the EOT input from the tape transport and
the SEL 0 line from the tape drive on-line detect logic and stores the EOT status of each transport in a register. If
drive 0 is selected and EOT asserts while FWD LTCH is asserted, EOT is asserted to the controller drivers. If
drive 1 is then selected, the EOT status of drive 0 is stored and EOT is cleared. The REV MOT and RWND PLS
inputs reset the portion of the EOT status register relating to the drive currently in use. The PWR OK input
clears the entire register.
Status Inhibit Logic - This logic inhibits status outputs to the controller when the controller selects a drive other
than 0 or 1 and whenever a new drive is selected. If the controller asserts C SEL 0 or C SEL 1, INHIBIT
ST ATUS asserts to the controller drivers and inhibits all status outputs until both inputs are cleared. Whenever
the controller clears or asserts C SEL 2, the EOT status register asserts CHANGE UNIT (250 ns pulse), which
also causes the status inhibit logic to assert INHIBIT STATUS but for only 250 ns. This prevents the transfer of
erroneous status during the drive select operation. Thus, status outputs to the controller are inhibited as long as
an illegal drive unit is selected and each time the controller selects drive 0 or drive 1.
11.3.1.2 Write Logic - The write logic generates the strobes necessary to write data, the CRC character, and
the file mark character (Figure 11-6). In addition, the write logic generates parity and the CRC and file mark
characters and converts all zero characters to 20 s when even parity (PEVN LTCH asserted) is selected.
The write strobe generation logic is enabled by READING and either C WDR or C WFMK. If READING and
C WDR assert, a normal write operation is performed. If READING and C WFMK assert, a write file mark
operation is performed. See Figures 11-7 and 11-8 for write operation and write file mark operation flow and
timing diagrams.
11.3.1.3 Read Logic - The read logic (Figure 11-9) monitors the read data and RD STRB inputs to determine
whether a data record or a file mark record is being read and also checks for parity, CRC, or LRC errors.
The record and file mark detection logic decodes the characters read and generates outputs accordingly. The
clearing of MOT at the end of the previous operation and the assertion of SET at the beginning of the current
operation serve to initialize the logic and assert FMK.

11-13

CWDR

READING

NOTE 3

4CHAR
4 CHAR...r- TIMES . ,
TIMES

I
I

REC

NOTE 1

ISSUE REC PULSE
TO SELECTED
TRANSPORT AND
WR PLS TO CRC
COMPILER LOGIC

WRS

CRCWR TIME

LRC PLS

WRITING

WAIT 4
CHARACTER
TIMES AND
ASSERTCRC
WR TIME

NOTE 2

NOTES:
(1)

ASSERTION OF
WRITING INHIBITS
SHUT DOWN COUNTER
IN THE CONTROL
LOGIC

(21

ASSERTION OF
CRCWR TIME
SELECTSCRC
(O:7,PIINPUTS
AT WRITE DATA
MUL TIPLEXER

(31

LRC PLS RESETS
TRANSPORT
DATA BUFFER
THUS WRITING
LRC CHARACTER.

"·3038

Figure 11-7 Write Operation Flow and Timing Diagram

CWFMK

1-+C WFMK
1-+WFMK LTCH
SET FMK F/F

NOTE 1

~____________________________________________________________________

WFMK F/F

WFMK LTCH
NO

READING

I
SOO ,",5

V 'l

ISSUE REC PULSE
TO SELECTED
TRANSPORT AN D
RESET WFMK F/F

0-+ WRITING
1-+ SHIFT
REGISTER

WAITS
CHARACTER
TIMES AND
ISSUE LRC PLS

REC

:::::
.....

LRC PLS

WRITING

NOTE:

WFMK LTCH FORCES
WRITE MULTIPLEXER
OUTPUT TO 23 8 (FILE
MARK CHARACTER).
11-3039

Figure 11-8 Write File Mark Operation Flow and Timing Diagram

Part III

RD(7:0,P)
FROM{
TRANSPORT
RECEIVERS

RECORD AND
FI LE MARK
DETECTION LOGIC

EIGHT SPACES
FMK

(08)

MOT
SET

FROM
TRANSPORT
RECEIVERS

RD (7: 0,P)

(FROM FIGURE.
11- 3)

PEVN LTCH

FROM
TRANSPORT
RECEIVERS

RD (7:0,P)

(FROM FIGURE
11-3)

TO FIGURE 11- 3

FILE MARK DETECTED

RD STRB
TIME PI..S 0

FROM{
FIGURE
11- 3

RECORD ACT

....

-+
---+

....

PARI TV ERROR
DETECTION
LOGIC
(013)

TO
CONTROLLER
DRIVERS

BAD PARITY

---+

....

.,.)

SET

L RC ERROR
DETECTION
LOGIC
( 013)

LRC REG NOT ZERO

COMP RD STRB
CRC RD TIME
FROM{
FIGURE
11-3

FWD LTCH
SET

FROM
TRANSPORT
RECEIVERS

RD (7:0,P)

..)

CRC ERROR
DETECTION
LOGIC
( 012)

CRCE

08-1697

Figure 11-9 Read Logic Functional Block Diagram

The logic decodes characters read as well as the format in which they are recorded. If a file mark record is
detected (a file mark character followed by seven blank character frames and an LRC character), all four outputs
are asserted, indicating that a record has been detected and that record was a file mark. The three outputs to the
controller drivers serve to notify the controller that a file mark record has been detected. The RECORD ACT
output enables the shutdown counter in the control logic. If a data record is detected (three or more data
characters followed by a CRC and an LRC), FMK is cleared, RECORD ACT is asserted, and FILE MARK
DETECTED and EIGHT SPACES remain cleared.
The parity error detection logic uses the simple generate-and-compare technique to check for parity errors. The
logic uses the character read to generate the parity bit as selected by the PEVN L TCH input, then compares the
parity bit generated to the parity bit read. If they do not match, BAD PARITY is asserted to the controller
drivers.
The LRC error detection logic uses a flip-flop register and a compare network to check the number of 1 bits
recorded on each channel of a record, including the CRC and LRC characters. If the number of ones recorded is
odd, LRC REG NOT ZERO asserts to the controller drivers, causing LRCE to be asserted to the controller.
Note that LRC REG NOT ZERO may assert several times during a particular record; however, the controller
driver is only enabled during LRC read time while the tape is moving forward. The CRC error detection logic
uses the data characters in each record to compile the CRC character; it then compares the character compiled to
the CRC character recorded. If they do not compare, CRCE is asserted to the controller drivers. Note that the
CRCE output from the CRC error detection logic is only enabled when CRC RD TIME and FWD LTCH are
asserted. At the controller drivers, the C CRCE output is disabled whenever a file mark record is detected.
11-16

Part III

11.3.2 Transport Control Logic
The control logic section of the tape transport generates the appropriate internal tape motion commands in
response to input commands from the adapter, the front panel and the test panel. The control logic receives these
commands and generates transport motion if all internal interlocks are satisfied. In addition, the control logic
returns the transport status outputs to the adapter and illuminates the respective indicators on the front panel
and the test panel. Table 11-3 lists the signals interfacing between the adapter and the transport.

Table 11-3
Adapter/Transport Interface Signal Names

BFWDMOT
BREVMOT
B OFF-LINE PLS
B RWNDPLS
BWRELTCH
B SEL DRIVE (1 :0)
B DRIVE (0:1) ON LINE
B WD (0:7, P)
BXPRT RDY
BRD(0:7,P)
BWRLCK
BRWNDG
B LOAD POINT
BENDOFTAPE
REC
LRC PLS
RDSTRB
DRIVE SEL SW GND

11.3.2.1 Functional Operation - Five plug-in circuit cards constitute the control section logic (Figure 1110): Control Terminator Type 3841 (not shown), Interface Control Type 3842, Pushbutton Control Type 3843,
Ramp Generator Type 3645, and Sensor Amplifier jDriver Type 3844. The modules are housed in the card cage
assembly and plug into the master board. Figure 11-10 is a simplified block diagram of the control logic, showing
the signal flow between the control modules. The input signals from the adapter are supplied, after being terminated on the control terminator module, to the control interface module, where these signals are acknowledged if
certain interlocks are satisfied. The motion commands are then supplied to the pushbutton control module. This
card also includes the interlocks for the front panel push buttons and for the test panel pushbuttons. If the
interlocks are satisfied, the pushbutton control module encodes all tape motion commands onto three command
lines: RUN NORMAL, RUN FAST, and RUN REVERSE. The three command lines are then supplied to the
ramp generator module, which produces accurate analog voltage output. The voltage output of the ramp generator is then supplied to the capstan servo amplifier module\in the servo system. The voltage output of the ramp
generator in conjunction with the feedback from the capstan tachometer is used to energize the capstan motor
and to advance the tape in the desired direction at the proper speed. The ramp generator provides linear rampups to speed and linear ramp-downs to standstill in order to minimize the stress on the tape and maintain
accurate speeds.
The sensor amplifier driver module receives the inputs from the file protect switch, the load point sensor, end-oftape sensor, and broken tape sensor. These signals are amplified and supplied to the other modules in the control
section where they provide the inputs to the interlocks. The sensor amplifier driver module also contains the
drivers for the front panel indicators, the driver for the file protect solenoid, and the write and erase head drivers.

11-17

Part III

FRONT PANEL PUSHBUTTONS

[

I REWINDI

LINEI~

ION

__
C0~ITROL:.l

-9-.Q-...c;::L

L__:
i

INTERFACE

DRIVE (0 1) ON LINE

i--"I

~I,P~R~Rl

IPLUG-IN fJ.OOULE

~.-+-

REVERSE I
CMD
FWD MOT
REV MOT

RAf1P
GENERATOR
LOGIC &
Af1PLIFIERS

RUN

SEL DRIVE

REVERSE

RUN CMD

RArlP
VOLTAGE

(TO CAPS TAfl
SERVO)

(1:0)

OFF LINE
PLS

-t----+---+--..............,

BU S Y
ON LINE
REWINDING
D,RIVE

DRIVE
CONTROL
LOGIC

STOPPED

TEST MODE
WRITE TEST

RWNDPLS~---~--~---~I

STOP
FWD RUN
REV RUN
FAST FWD
FAST REV

F ROt·'
TEST
BOX

PUSHBUTTONS

WR I TE
READY
DATA
SECTION)

TO/FROM
ADAPTER
LOGIC

~+---~.-------------.(TO

WRITE AMP OUTPUTS
FROM

DRIVE
(Oi;
ON LINE

.. DATA SECTION
TAP ESTOPPED

XPRT
ROY

REWINDING

WRITE
HEAD C.T.

WRITE
READY
WRLCK

RWNDG
LOAD
POINT

F I LEI
PROTECT ~
SWITCH

ERASE
HEAD

FILE
PROTECT
CIRCUIT

AT LOAD
POINT

END OF
TAPE

LOAD ENDOF BROKEN
POINT TAPE

~
------

PHOTOSE~SORS

11-3047

Figure 11-10 Control Logic Block Diagram

11-18

Part III

11.3.2.2 Transport Control Logic Operation·During a Write Sequence -A write operation will be used as an
example to demonstrate the interaction ()f the different components of the control logic. The whole operation is
described, showing the flow of commands and the required control interlocks.
The front panel is used to prepare the transport for operation. After the power is turned on and the tape is
properly threaded, the front panel LOAD pushbutton is pressed. This sets the load flip-flop on the pushbutton
control modules, generating RUN NORMA.L true to the ramp generator card. The ramp generator outputs a
linear ramp voltage to the capstan servo amplifier card, initiating forward tape motion at normal running speed.
The ramp generator also supplies TAPE STOPPED to the interface control card where it is converted to TAPE
RUNNING STATUS and then sent to the adapter logic. When the load point reflector marker is detected by the
respective photocell, the signal is amplified by the sensor amplifier/driver card and is supplied as AT LOAD
POINT to the pushbutton control module. AT LOAD POINT true sets the ON TAPE flip-flop to the true
condition, terminating the synchronous forward motion by setting RUN CMD false. The tape is stopped at the
load point and is properly loaded. Pressing the front panel ON LINE pushbutton now places the transport online, preparing the transport to respond to adapter commands once it is selected by the adapter. When the
transport is selected (input line select going true), the transport can accept commands from the adapter and
return the transport status outputs back to the adapter. At this time, the transport status lines would be in the
states shown in Table 11-4. In addition to the status lines, the front panel ON LINE and UNIT SELECT
indicators are illuminated, as is the WRITE ENABLE indicator if the supply reel contains a write enable ring.
If the write operation is to be initiated, the adapter logic now supplies WRE LTCH (set write status) level true
and then a FWD MOT (forward command). The WRE LTCH level is sampled on the leading edge of FWD
MOT. If the level is true, a flip-flop on the interface control module is set, which generates WRITE CMD true.
WRITE CMD is supplied to the pushbutton control module where it generates WRITE READY true provided
WRITE RING ON (file protect) is false (supplied from the sensor amplifier/driver module), DRIVE BUSY is
false (this signal is generated on the pushbutton control and is true whenever the transport is searching for load
point and is rewinding), and a forward motion command is given. These interlocks ensure that the transport
writes data on tape only when the tape is properly loaded, the reel has a write enable ring, and the tape is moving
forward at normal running speed. WRITE READY true is supplied to the sensor amplifier/driver module where
it turns on write and erase head current drivers. WRITE READY and SELECTED & ON LINE (combining ON
LINE true and SEL DRIVE (1 :0) true) are also supplied to the data electronics card cage where they enable the
write and read amplifier stages.

If WRITE READY does go true, the adapter logic supplies the properly formatted data to be written on tape.
The write operation can be interrupted in case of broken tape; when the TAPE THREADED (broken tape)
signal is supplied from the sensor amplifier/driver module, all servos are disabled immediately. Note that an
END OF TAPE indication does not terminate a write operation, but leaves it up to the adapter to do so. When
the write operation is terminated by the adapter, the tape is rewound to the load point when the adapter issues
RWND PLS. Note that the tape cannot be rewound past the load point by a command from the adapter. In
order to rewind the tape off the takeup reel, the transport must be taken off-line, either through an adapter
command or by pressing the front panel ON LINE pushbutton again. Once the transport is off-line, the front
panel REWIND pushbutton can be activated to rewind the tape completely off the takeup reel.
11.3.2.3 Test Box - The test box provides a means of exercising, testing, and adjusting the tape transport while
it is off-line, eliminating the need for a separate test fixture or for the use of valuable computer time. The test box
can initiate forward and reverse tape motions at either normal or high tape speeds. It can also initiate a write test,
generating a crystal-controlled all-Is test pattern on tape. The test box also provides indicators for load point,
end-of-tape, and data. A toggle switch on top of the test box can select a start/stop operation of the capstan servo
system for checking the ramp generator.

11-19

Part III
Table 11-4
Transport Status
Status Line

State

Point of Origin

DRIVE (0: 1) ON-LINE

True

Supplied from the on-line flip-flop on the pushbutton
control module, routed through the interface control
module.

XPRTRDY

True

This signal, generated on the interface control module,
combines DRIVE BUSY false (meaning the transport is
loaded and not rewinding or searching for load point) and
SELECTED & ON LINE true (meaning the transport is
on-line and SEL DRIVE (1 :0) is true).

TAPE RUNNING
STATUS

False

This signal goes true on the ramp generator when tape
motion is initiated. It is not used in the TMS-M System.

RWNDG

False

At this time, the rewind flip-flop on the pushbutton control
module is in the cleared state.
This signal is true if the reel of tape mounted on the supply
hub does not contain a write enable ring. It is false if the
reel does contain the ring and is available for writing. The
signal originates on the sensor amplifier/driver module.

WRLCK

LOAD POINT

True

This signal is equivalent to the inverse of the WRLCK signal
and is true whenever the other is false, e.g., whenever the
supply reel contains a write enable ring. The signal
origin_ates on the interface control module. It is not used in
the TMS-M System.

WRITEENB

END OF TAPE

Since the tape is at load point, the sensor amplifier/driver
supplies this signal true. When OFF LD PT is true, the
transport does not acknowledge a REWIND CMD or
REVERSE CMD from the interface, but must be taken
off-line and rewound by using the front panel pushbutton.

False

This signal goes true only when the end-of-tape reflective
marker is detected by the respective photosensor. The
signal is supplied to the sensor amplifier/driver module.

An additional indicator monitors excessive skew, and is used in the aligning of the read/write head when using an
SOO character/in. skew master tape. When the head is properly aligned and the data is written on tape properly,
the SKEW indicator is extinguished. The toggle switch on top of the test box can select instantaneous skew or
average skew for the head alignments.
The controls and interlocks for the test box are located on the pushbutton control card. The skew detect network
is located on the delay timing module in the read logic section of the transport. The test box becomes operational
only when the transport is off-line, with the test box STOP pushbutton pressed. If these conditions are satisfied,
the test box pushbuttons are enabled when the TEST MODE pushbutton is pressed.

11-20

Part III

11.3.3 Servo System
The servo system includes two subsystems: the capstan servo subsystem, which drives the tape at accurately
controlled speed, and the reel servo system, which maintains constant tape tension.
11.3.3.1 Reel Servos - Two identical reel servos are employed for the supply and the takeup reels. A simplified
block diagram is shown in Figure 11-11. Each reel servo includes a spring-loaded buffer arm, a magnetic position
sensor coupled to the buffer arm shaft, a servo amplifier (located on the Servo Preamplifier Type 4306 module),
power transistors (located on the chassis heat sink), and a high power dc motor.

SPRING

REEl
MOTOR

POSITION - -...L/
PREAMPl

OFFSET

POWER
AMPl
11-3058

Figure 11-11 Reel Servo System

The tape tension is maintained by the interaction of the spring-loaded buffer arms, the capstan, and the respective reel motors. The magnetic position sensors, called magpots, produce a corrective voltage whenever the buffer
arms swing away from the center of their arcs. The magpots are rotary differential transformers with oscillator
and phase detector circuitry. The output of the magpot circuitry provides a bipolar dc voltage which has a linear
relationship to the tension arm position and a null at the center position. The magpot output is summed with a
signal from the capstan tachometer in the higher speed versions of the machine. The effect of the tachometer
component is to speed up the response of the reel servos.
As shown in Figure 11-11, the corrective voltage approaches 0 V in the rest position where the torque of the
motor is balanced against the buffer arm spring tension near the center of the tension arm swing. When capstan
motion pulls the tape, the buffer arm moves, causing a change in the magpot output. This is amplified in the
servo preamplifier whose signal drives power transistors that control the dc motor current to provide' a change in
torque until the torque matches the buffer arm spring tension at the null position again. Since the system is
bipolar, seeking a null which is controlled by a'magnetic core position, the adjustments are mechanical and will
not drift with temperature or component degradation.

11-21

Part III

11.3.3.2 Capstan Servo - The single capstan drive motor is part of a high performance velocity servo system. In
addition to the motor, the capstan servo system includes a dc tachometer, coupled to the capstan motor shaft,
and the capstan amplifier, located on the servo preamplifier module. The linear analog ramp voltage produced
by the ramp generator card (in the control logic section) is supplied to the servo preamplifier module where it is
compared with the feedback supplied from the capstan tachometer. Any resulting difference is amplified and is
supplied to the capstan power transistors, located on the chassis heat sink. The output of the power transistors
energizes the capstan motor, advancing tape at accurately controlled speeds.
11.3.4 Data Section
The data section includes read and write amplifiers and interface cards providing output drivers and timing
controls. Block diagrams are shown in Figures 11-12, 11-13 and 11-15.
The data section consists of eight circuit cards, seven of which plug into the master board. These are a delay
timing module, a read amplifier/clipping control card, a pair of quad read amplifier modules, a four-channel
write amplifier card, a five-channel write amplifier card, and a data terminator card. A read preamplifier board is
mounted on the TS03 main chassis.

r -WRiTEAMPLImR/CONTRO-L-1
WRITE
CONTROL
(FROM READ
BUFFER)
REC
LRC
PLS

----+-1-~E---~I

.-J

~:i I~G
- ~~~I~ -~---~I~---~·~
I
(ALL CHANNELS)

. I ~~~~ROL I~T-I-M-I-NG--+I-------1~~(:~[E C~:~~ElS)
(PARITY

~ CHANNEL)

WOP

PLUG-IN MODULE

I.
1----11.... WRITE AMPLI FIERS

WRITE
HEAD

WOO - - -.....
WDI
WD2

I . (PARITY. 0, 1. 2) ~---4-----"""
I.
~----.---~----~

FROM
APAPTER

IL _ _ _ _ _ _ _ _ ---'I
GATING

Loa Ie

WRITE LRCC

r 5-CHANNEL WRITE AMPLI FIER-'
I PLUG-IN MODULE
I
WD3

----+-1--..

1"'----1... .

WD 4. - - -.....

W0 5 ---"'"+t-

...........
WD6 ----+I---t.....
W0 7 -----1-1-.......... .

WRITE
AMPLI FIERS
(3 THRU 7)

IL _GATING
WRITE
LRCC
______
__
-.J

11-3053

Figure 11-12 Write Data Section

11-22

Part III

11.3.4.1 Write Electronics - A write amplifier channel is provided for each tape channel. Four such channels
and the circuitry common to all write amplifiers are contained on Write Amplifier Type 3848, and the five
remaining write amplifier stages are located on Write Amplifier Type 3849. These cards plug into the master
board, from which the necessary head con~ections are made.
Each write amplifier channel consists of an input buffer, a digitally adjustable deskewing circuit, a clocked flipflop, and a pair of head drivers, as shown in Figure 11-13. Digital write deskewing and its advantages are
explained in the following paragraphs.

SKEW ADJUSTMENT SWITCHES

WRITE CURRENT
SUPPLY
WRITE DATA STROBE

INPUT
DATA

L..r""'O...----..COUNT/LOAD

320 kHz-CRYSTAL CONTROLLED

FREQUENCY' 32XDATA

WRI TE RESET
11-3062

Figure 11-13 Typical Write Amplifier Channel (0-7), Fixed Channel P Delay

Manufacturing tolerances in the production of magnetic heads cause deviations in the parallelism between the
write gap and the read gap of the magnetic heads, as shown in Figure 11-14. While the magnetic heads are
manufactured so that this deviation does not exceed 250 microinches, it is important to correct for it; otherwise
the skew across the bits of a character may cause errors during the reading of the data on compatible systems.
The skew caused by the physical characteristics of the head should not be confused with azimuth or with the skew
caused by the misalignment of the whole magnetic head with respect to the tape path, shown in Figure 11-14.
Azimuth can be corrected by aligning the read head to be perpendicular to the tape path using a skew master tape
- a tape written by a special machine equipped with a full-width write head set perfectly perpendicular to the
tape. The head aligning procedure is made particularly simple by the use of the optional test panel, as described
in Part I, Chapter 5 of this manual.
While azimuth can be corrected by manually adjusting the position of the read head, the skew caused by the
parallelism tolerance between the write head and read head must be corrected electronically. This is done by
delaying the channels with respect to a fixed reference so that all the bits of the character are read simultaneously.

11-23

Part III

READ/WRITE
MAGNETI C
HEAD

HEAD MOUNTING PLATE

TAPE MOTION

I
I
I
I

t
I

WRITE
GAP

..Jt
I

L
READ
GAP

I
I

f
ALL-l PATTERN ON TAPE
WITHOUT WRITE DESKEWING

ALL-l PATTERN WITH
WRITE DESKEWING

DEVIATION FROM PARALLELISM
INHERENT IN HEAD
(PARALLEL WITHIN 250 "in.)

REFERENCE TO HEAD
TAPE MOTION

PATTERN RESULTING FROM
MISALIGNMENT OF HEAD

PATTERN RESULTING AFTER HEAD
IS ALIGNED USING SKEWMASTER

DEVIATION FROt PERPENDICULARITY
CAUSED BY MISALIGNMENT
11-3063

Figure 11-14 Skew Characteristics

11-24

Part III
Conventional skew correction methods employ adjustable delays supplied by analog circuitry in the read circuits.
While these methods compensate for the skew of the character written on tape by the same machine, they do not
correct the character itself as it is written on tape; consequently when the tape is read on a different machine, the
skew is uncorrected. Also the delays generated by analog circuits are subject to drift and may require periodic
readjustment.
In this tape unit, the skew correction problems are overcome by write deskewing circuits, shown in Figure 11-13.
The main component of the deskewing circuit is a divide-by-16 counter clocked by a crystal-derived frequency
(320 kHz) at 32 times the data rate (generated on the delay timing module). The counter of channel P is preset to
the count of eight, supplying a fixed 1/4 character delay. The parallel inputs of the counters of the other eight
channels are adjustable using a set of four switches for each counter, varying the skew delay of each channel in
1/32 character increments. Each head is pretested and the switch positions are determined to compensate for any
deviation from parallelism between the write and the read gaps, using channel P as a reference. Once the head is
installed on a machine and the write amplifier switches are set, the switch positions should not be changed for the
life of the magnetic head. These switch positions are displayed on a tape inside the machine. If the magnetic head
is replaced, the replacement head is pretested in the factory- and is supplied with a 'new tag showing the switch
positions required to compensate for the characteristics of the new head.
The digital write deskewing method ensures that the character written on tape has minimum skew, increasing the
compatibility of tapes between different tape transports. Using digital circuitry with a crystal-controlled reference frequency provides for a high degree of precision and stability for all skew adjustments.
The write electronics section also includes the write data strobe buffer which clocks the write amplifier flip-flops,
and a write amplifier reset circuit to clear all write amplifier flip-flops. The write amplifier reset is used to write
the LRC character. During a write test mode, initiated by the test box with the recorder off-line, the write
electronics generates an allis test pattern on tape derived from a crystal-controlled reference frequency (10 kHz),
supplied from the delay timing module in the read electronics. The test pattern can be used to test the write
deskewing, as well as the other functions of the data electronics.
11.3.4.2 Read Electronics - The function of the read electronics is to convert the data recovered from the tape
into digitized waveforms, deskew it, and supply it to the adapter logic with its respective read strobe. The read
electronics also detect the interrecord gap and excessive skew. The components comprising the read section
include the magnetic read head, the Read Preamplifier Type 3631 module, Delay Timing Type 4845 module,
Read Amplifier/Clipping Control Type 4179 module, and a pair of Quad Read Amplifier Type 4178 modules.
Figure 11-15 is a functional block diagram of the read section, showing the general signal flow between the cards.
The low level analog signals, on the order of tens of millivolts, are supplied from the read head to the read
preamplifier module where they are linearly amplified to an output voltage (adjusted by a potentiometer for each
read preamplifier stage) of approximately 9 V peak-to-peak in 800 character/in NRZI read operation. The
amplified analog signals are then supplied to the nine read amplifier stages, eight of which are located on the
quad read amplifier modules while that of channel P is located on the read amplifier/clipping control module.
Each read amplifier stage includes a peak detection circuitj a filtering network, an output data register, and a
pulse generator.

11-25

Part !II

TO i f ST BOX
(

«
«

~ffi

~ T p; I G

Ii!
t;

READ GAP
DtHeT
NETWOR'

I
TO

WR I TE
LOGIC

{"OkH'
10kHz

DRIVE
BUSY
SELECTED& ON UNE

FRan {
CONTR
LOGIC

READ
SELECT
DELAY

AT LOAD POINT

CRYSTAL
OSCILLATOR
& DIVIDING
NETWORK

INHIBIT
DATA
OUTPUT

, t -

320kHz

SKEW
DETECT
NETWORK

RO
STRB

READ
CLOCK
GENERATION

I
TRAtiSFER DATA

RUN CMO

L--=.

--------

..,
DATA
PACKET
(0-31

DATA
PlICKET
(4-71

CHANNEL

a
1
2
3

~
~

.........
~
;;!

.......

<=1-----

.:::::::

:::::

€i-

INHIBIT.........
DATA
OUTPUT

RO 3

r+-

LIP
v: CCLIP

....V

'---

QUAD
READ
Af.1PLlf-JER
NO.2

CHAN 4
READ
CHAN 5
PRECHAN 6
Arw LI FIE R
CHAN 7

REFERENCE
REFERENCEi

RO 4
RO 5
RO 6
RO 7

.....

----4

INHIBIT
DATA
OUTPUT
~

RO 2

f4-- ....

OATA/
PACKET (PI

RO 1

QUAD
READ
AMPLIFIER
NO.1

CHAN 0
CHAN 1
CHAN 2
CHAN 3
INHIBIT
DATA
OUTPUT

4
5
6

-TOINTERFACE
RO 0

~----

~I-

CHAN P

CHANNEL P
J\i~ PLI FIE R
!4- r-4
STAGE

RO P

-+4
RUN CMO

READ

AMPLIFIER
CLIPPU~G

CONTROL

REVERSE Ct.10

AUTO
CLIPPING
LEVEL
CONTROL

DRIVE BUSY
WRITE READY

}

FROM
CONTROL
SECTION

-..J
11-3048

Figure 11-15 Read Data Section

11-26

Part III

The analog signals from the preamplifier are detected only when they exceed the positive or negative clipping
levels provided by the read amplifier/clipping control module. They are then rectified and peak detected, with
the resulting digitized waveforms containing negative-going transitions corresponding to the peaks of the input
analog signals, e.g., 1 bits in the NRZI coqe. The digitized waveforms are supplied to a filtering network which
eliminates spurious pulses between transitions. The data of each channel is then stored in a register and generates
a DATA PACKET to the delay timing module. Following the skew delay, the delay timing card supplies a
TRANSFER DATA output to clock the data registers of all nine channels simultaneously, supplying the data
character and read clock to the interface.
When an error is detected and the transport is commanded by the adapter logic to reread a block, the read
amplifier clipping levels are switched automatically by the read amplifier/clipping control module to maximize
the recoverability of marginally recorded data. The clipping levels are kept normal on the first reread; on the
second reread they are switched to lower levels in order to recover possible partial dropouts. If the block is still in
error and a third reread is commanded, the clipping levels are switched to higher levels to eliminate possible
baseline spikes. During read-after-write operations, higher clipping levels are used.
The delay timing module contains circuitry common to all nine channels. It includes a crystal-controlled
oscillator and divider network which produce the synchronous clocks used in the skew delay network, the data
strobe generation, and the gap detect network, and are also supplied to the Write Amplifier Type 3848 module to
generate the write test pattern. The crystal-controlled clocks ensure high precision in the performance of all data
synchronized functions.

11-27

Part III

CHAPTER 12
DETAILED LOGIC DESCRIPTIONS

12.1 INTRODUCTION
This chapter contains circuit descriptions of the individual circuit cards comprising the TS03 DECmagtape
Transport. Module layout drawings are provided with each description. (See engineering drawing for module
schematics.) The descriptions are arranged by functional group as listed below.

Functional Group

Module Name and Type

Adapter Logic

M8920 Adapter

Overall

TS03S Power Supply

Control Electronics

Control Interface Module (Type 3842)
Pushbutton Control Module (Type 3843)
Ramp Generator Module (Type 3645)
Sensor Amplifier IDriver Module (Type 3844)
Connector Board (Type 4013)
Control Terminator Module (Type 3841)

Servo System

Servo Preamplifier Module (Type 4306)
Magpot Sensor (Type 4218)

Read Electronics

Data Terminator Module (Type 3860)
Read Preamplifier Card (Type 3631)
Delay Timing Module (Type 3845)
Quad Read Amplifier Module (Type 4178)
Read Amplifier IClipping Control Module (Type 4179)

Write Electronics

Four-Channel Write Amplifier Module (Type 3848)
Five-Channel Write Amplifier Module (Type 3849)

12.2 NOTES TO TRANSPORT SCHEMATIC DIAGRAMS
The following conventions have been observed in preparing schematics for this manual:
1.

Resistor values are given in ohms. If wattage is unspecified, the resistor may be either 114 or 112 W.

Capacitor values may be given in picofarads or microfarads. Those values for which neither designation is provided are assumed to be obvious from circuit function. Filter capacitors on certain supply
lines do not have logic significance. In general, they are not shown on schematics. On PC board
silkscreens, they are designated as CF.

12-1

Part III
3.

Normally, IC power connections are on pins 14 (+5 V) and 7 (ground) for 14-pin packages, and 16
(+5 V) and 8 (ground) for 16-pin packages. Some ICs (7476,7492,7493, for example) have power
connections on pin 5 (+ 5 V) and pin 10 (ground). Operational amplifiers in the 8-pin package have
power connections on pin 4 (-Vcc) and pin 7 (+Vcc). Power connections are not shown unless they
are nonstandard.

Where multiple inputs are tied together only one pin may be designated on the schematic.

Unused inputs that are tied high are not normally indicated unless the connection has logic
significance.

From and to designations are intended to describe inputs and outputs only. The same signal may be
connected to several other points not shown on a particular drawing.

If not indicated, diodes are IN914, NPN transistors are 2N2714, and PNP transistors are MPS6517.

Unless otherwise specified, light-emitting diodes are FL VI 02 or equivalent.

Socket terminals are designated with numbers for component side connections and letters for circuit
side connections when a double-sided socket is used. These are the designations on the socket. When
a single-sided socket is provided, all connections are designated by letters regardless of which side of
the board they lie on the etch. Letters follow the 22-pin alphabet,
ABCDEFHJKLMNPRSTUVWXYZ; numbers are 1 through 22.

12.3 TYPE M8920 ADAPTER CIRCUIT DESCRIPTION
The following paragraphs provide detailed circuit descriptions on those portions of the adapter logic which
perform unique or complex operations. Each description covers a functional block on the control logic, write
logic, and read logic functional block diagrams and is titled accordingly. The circuits described are listed as
follows:
Functional Area

Circuit

Engineering Drawing Reference

Control Logic
Control Logic
Control Logic
Write Logic
Read Logic

Clock Logic
Read/Write Control Logic (ROM/Delay Counter)
Shutdown Logic
Write Strobe Generation
Record and Tape Mark Detection Logic

D6
D7
D9
DI0
D8

12.3.1 Clock Logic
The clock logic generates two 10 kHz pulse trains which are 180 degrees out of phase. See the timing diagram for
logic operation and timing specifications (Figure 12-1).
12.3.2 Read/Write Control Logic (ROM/Delay Counter)
The following paragraphs describe the read/write control logic relative to two different operations:
operation and a rewind off-line operation (engineering drawing D7).

12-2

a write

Part III
200 KHZ

40 KHZ _;.--___

FF1 (1) H -/------1)

FF2 (0) H

FF1 (0) H

FF3 ( 1 ) H --~H-------I

FF3 (0) H

,
.., - - - - - - - - 1 0 0 (i5) .... S - - - - - - - - - . . ,
TIMEPLS0

_~~~

_______________

____________________________________

___

1~'---50(± 5),c.IS,--~.1
TIME PLS 1
11-3044

Figure 12-1 Clock Logic Timing

12.3.2.1 Write Operation - To initiate a write operation, C WRE Hand C FWD H must be asserted by the
controller. When SET L asserts, the following operations occur at the read/write control logic:
1.

The ROM is addressed and the proper count is output to the delay counter. The count varies in
accordance with the tape position relative to the BOT. If the tape is positioned at the BOT (BOT H
asserted), the delay counter is set to 250008 •

The motion enable flip-flop is set.

The load delay counter one-shot (E27-5) is triggered and the LD input to the delay counter asserts.

Assuming the tape is ppsitioned at BOT, the assertion of the LD input loads the delay counter to a count of
250008 using the output from the ROM and RWND L. Note that zeros are loaded into the first and second most
significant bits (R3 and R2) of Part D of the delay counter due to the assertion of SET L. The load delay counter
one-shot then resets and sets the motion flip-flop, asserting MOT H. Thus READING H remains cleared. TIME
PLS 0 then clocks the delay counter for 563.2 ms, the second most significant bit of Part D of the delay counter
sets, and READING H asserts. The read/write control logic remains in this state until RD CLR (1) H is asserted
by the shutdown logic.
The assertion of RD CLR (1) H loads the delay counter with a deceleration delay using the ROM output RWND
L. In this case, because a write operation is being performed, the delay counter is set to 37754 8 • RD CLR (1) H
also sets the two most significant bits (R2 and R3) of Part D of the delay counter because SET L is cleared. TIME
PLS 0 L then clocks the delay for 2 ms, the most significant bit (R3) is reset, and the motion enable flip-flop (E259) is reset. Resetting the motion enable flip-flop asserts EI4-3, which resets the motion flip-flop, thereby clearing
MOT H and the FWD MOT H oUfput to the tape transport. The transport begins to stop the tape. TIME PLS 0
L then clocks the delay counter for 32 ms (allowing time for the transport to stop the tape), and INHIBIT
DELAY COUNT L asserts, inhibiting the clock input to the delay counter and asserting DRIVE STOPPED L.
Assertion of DRIVE STOPPED L notifies the tape motion status logic that tape deceleration delay has expired.

12-3

Part III

12.3.2.2 Rewind Off-Line Operation - To initiate a rewind off-line operation, C RWND Hand C WRE H must
be asserted by the controller. When C SET H asserts, the following operations occur:
l.

The ROM is addressed and a stop count is output to the delay counter.

The motion enable flip-flop is set.

The off-line one-shot (E33-13) is triggered, asserting OFF-LINE PLS H to the tape transport.

The rewind pulse one-shot (E27-13) is triggered, asserting RWND PLS H to the tape transport.

The load delay counter one-shot (E27-5) is triggered, asserting LOAD DELAY CTR L.

The assertion of LOAD DELAY CTR L loads the delay counter with a stop count, i.e., the counter is set so that
DRIVE STOPPED L asserts. When the load delay counter one-shot resets, the motion flip-flop is held in the
reset state by RWND PLS H. Thus MOTION H remains cleared, DRIVE STOPPED L remains asserted, and
the tape is rewound to the BOT.
12.3.3 Shutdown Logic (Engineering Drawing D9)
The shutdown logic is enabled when RECORD ACT H asserts and WRITING L clears. With those conditions
established, TIME PLS 0 H clocks the shutdown counter. However, the counter is prevented from counting past
a count of2 initially by COMP RD STRB L (composite read strobe), which is generated each time RD STRB H
(read strobe) is received. After the last data character is read, there is a gap of three character times before the
CRC character is read. During that time, the shutdown counter reaches a count of 3, the CRC flip-flop (E61-5) is
set, and CRC RD TIME (1) H asserts. A read strobe is then received due to the CRC character and COMP RD
STRB L asserts and clears the shutdown counter again. When COMP RD STRB L returns high, the CRC flipflop is reset and the LRC flip-flop (E45-5) is set, asserting LRC RD TIME (1) H. The counter then counts to 3
again, but this time LRC RD TIME (1) H holds the CRC flip-flop in the reset state. Another read strobe is then
received due to the LRC character, and COMP RD STRB L asserts again, clearing the shutdown counter. When
COMP RD STRB L clears, the LRC flip-flop is reset and the EOR flip-flop (E45-9) is set. Note that the read
strobe resulting from the LRC character is also ANDed with LRC RD TIME (1) H to load the shutdown
counter with a binary count of 56 (0111000). The shutdown counter is then clocked by TIME PLS 0 and, at a
binary count of 64, the read clear one-shot is triggered, the counter is disabled, and RD CLEAR (I) H asserts to
the read/write control logic.
The EOR one-shot (E28-5) is provided to ensure that the shutdown process is completed when the CRC and
LRC characters are not detected at the end of a record. This is always the case when the tape is moving backward, and might occur when the tape is moving forward if there is a bad spot in the tape or the write circuitry
malfunctions. Note that when the last data character read strobe is received, the shutdown counter counts to 3
and sets the CRC flip-flop, thus asserting CHK CHAR RD TIME H. If the CRC read strobe is not received, the
shutdown counter counts to 5, placing a low on the EOR one-shot. At a count of 6, the EOR one-shot is
triggered, asserting INTERNAL STRB (1) H and thereby generating COMP RD STRB H. Thus the counter is
cleared, the LCR flip-flop is set, and the CRC flip-flop is reset. The counter then counts up again and if the LRC
read strobe is not received, the same operation is repeated. The shutdown counter then starts its final count cycle;
however, in this case the counter starts from a count of 8 instead of a binary 56, due to the absence of the LRC
read strobe. Therefore the final count cycle is 56 counts long instead of the normal 8. In the event a bad tape spot
is encountered or the write circuitry malfunctions, this extended count cycle ensures that the tape moves past the
end of the record before stopping.
12.3.4 Write Strobe Generation Logic
The following circuit description will cover the two modes in which the write logic can operate:
write tape mark (engineering drawing DI0).

12-4

write data and

Part III

12.3.4.1 Write Data Circuit - 'When the C WDR H and READING H inputs are asserted, the write data mode
is enabled and WRITING L and WRITING H,assert. WRITING H enables the clock pulse (TIME PLS 1 H}to
generate write strobes to the transport (REC H) and is also output to the controller driver where it enables the
clock pulse (TIME PLS 0 H) to generate the write strobe (C WRS L), thus notifying the controller that a
character has been recorded and requesting the next character. When the last data character has been strobed to
the transport, the controller clears the C WDR H input, causing WRITING L to go high, inhibiting the strobe
outputs, and setting the writing done flip-flop (E47-6). Setting the writing done flip-flop places a high on the
input to the shift register and the next assertion of TIME PLS 0 loads a 1. The shift register output then resets the
writing done flip-flop so that no more ones wilt be loaded into the shift register. TIME PLS 0 then shifts the 1 bit
through the shift register and, at bit position 3, CRC WR TIME H asserts, enabling another write strobe (REC
H) to the transport to record the CRC character. The 1 bit is then shifted to bit position 7 and LRC PLS H is
generated and sent to the transport to record the LRC character. Thus the CRC and LRC characters are recorded at the end of each record.
12.3.4.2 Write File Mark Circuit - To write a file mark, the controller asserts C WFMK Hand C WRE H,
places a file character on the write data lines, and issues a SET H pulse, thereby setting the file mark flip-flop
(E44-5) and file mark latch flip-flop (E44-9). After the acceleration delay expires, READING H asserts, WRITING L asserts, and the clock pulse generates REC H. The same clock pulse that generates REC H also generates
WR PLS L, which resets the file mark flip-flop on its trailing edge, thereby clearing WRITING L. Thus only one
write strobe is generated to record the file mark character. Clearing WRITING L sets the writing done flip-flop
and the shift register is loaded and shifted up. However, when CRC WR TIME H asserts, REC H is inhibited by
WFMK LTCH (0) H. Therefore, the CRC character is not written. When the 1 is shifted to bit position 7, LRC
PLS H is generated the same as in the normal write data mode. Thus the file mark record consists of only two
characters.
12.3.5 Record and File Mark Detection Logic
This logic detects data records and file marks (engineering drawing D8). File marks are detected by decoding the
characters read; two octal 23 characters at the beginning of a record followed by at least seven blank character
frames constitute a file mark record. Data records are detected by counting read strobes; a minimum of three
read strobes constitutes a data record.
The MOT H and SET L inputs preset the record and file mark detection logic before the first character (of a
current record) and accompanying read strobe is detected. SET L asserts at the beginning of each operation and
sets the file mark flip-flop (E47-9), thereby asserting FMK (1) H. MOT H is cleared at the end of each operation
and serves to preset the read strobe counter to a count of 1.

12.3.5.1 File Mark Record Detection - When a file mark character (23 8) is the first character read, FMK
CHAR L asserts. The assertion of FMK CHAR· L is ANDed with the set condition of the file mark flip-flop,
placing a high on the D input. Thus the assertion of RD STRB H leaves the flip-flop unchanged and steps the
read strobe counter to a count of 2. Now assuming the octal 23 character detected was in fact the first character
of a file mark record, the next and final character detected will be the LRC character which is also an octal 23.
Therefore when the next character is read, FMK CHAR L remains asserted, the file mark flip-flop remains set,
and the read strobe counter is stepped to a count of 3. At a count of 3, ENB FMK CTR H (enable file mark
counter) asserts and enables the file mark counter. The file mark counter is then clocked to a count of 8 by TIME
PLS 0 L and EIGHT SPACES H asserts, which inhibits the counter and asserts RECORD ACT H. EIGHT
SPACES H is ANDed with FMK (1) H to assert FILE MARK DETECTED L.
Note that if another read strobe is received before the file mark counter reaches a count of 8, ENB FMK CTR H
clears and RD STRB CTR = 4 (1) H asserts. Thus the file mark counter is cleared and disabled, the read strobe
counter is disabled, and RECORD ACT H is asserted. In this case, the two successive octal 23 characters do not
constitute a file mark record because data does not follow a file mark record that closely.

12-5

Part III
12.3.5.2 Data Record Detection - When a character other than an octal 23 is the first character read, FMK
CHAR L remains cleared and a low is applied to the file mark flip-flop. Thus the accompanying read strobe
resets the file mark flip-flop and steps the read strobe counter to 2. Now, regardless of what the next character is,
the file mark flip-flop remains cleared and the read strobe counter is stepped to 3. As previously stated, a count of
3 enables the file mark counter; however, the file mark detection logic was disatiled by resetting the file mark flipflop. Upon the receipt of the next character, the read strobe counter is stepped to a count of 4, RECORD ACT H
asserts, and the read strobe counter is disabled.

12.4 TS03 POWER SUPPLY CIRCUIT DESCRIPTION
The TS03 Power Supply produces the unregulated and regulated voltages required by motors and electronics.

12.4.1 Primary Power
Primary power is switchable to allow either 115 V or 220 V mains. Frequency is not critical and may be from 48
Hz to 500 Hz. These voltages were selected because 220 V mains predominate in Europe. A simple modification
allows 230 V operation if required. For 115 V operation, the two 115 V primary windings of T 1 are connected in
parallel by S2. For 220 V operation, a 105 V tap on primary winding 2 is connected in series with primary 1.
Modification for 230 V operation requires removal of the violet wire and installation of a jumper from S2-6 to
S2-3.
12.4.2 Secondary Power
Transformer secondary voltages are rectified to produce nominal unregulated voltages of ±24 V (±26 V under
light load) and +8 V. A voltage of ±24 V regulated is supplied to motor drive circuits and provides sources from
which ± 10 V regulated is produced. A voltage of +8 V is the source for a high efficiency +5 V regulator.
12.4.3 + 10 Volt Regulator
Pass transistor Q3 is fed from +24 V and its base is driven by monolithic regulator E2. Voltage output is
determined by R8 and R9. Q7 and Q8 control power supply tracking when powering down. As +24 V drops due
to the discharge of C 1, Q8 cuts off at approximately 13 V on the + 24 V line. When this happens, Q7 is turned on,
shorting out R9 and dropping the regulator reference voltage to zero. The + 10 V output is cut off and drops to
zero. Since + 10 V is the reference for -10 V, -10 V also drops to zero. This action occurs before the +5 V
supply has dropped sufficiently to cause indeterminate logic states; turn-off transient motions are prevented.
12.4.4 -10 Volt Regulator
The -10 V supply is regulated by pass transistor Q4 driven by Q6. Its reference is + 10 V as determined by R13,
R14. In this way, the two regulated voltages are made to track or retain a constant relationship to each other.
12.4.5 + 5 Volt Regulator
Integrated Circuit regulator El controls + 5 V output in conjunction with pass transistor Q 1 and driver Q2.
Output voltage is set by R4, R5. Q2 assures that sufficient base drive is available for Ql. Integrated circuits El
and E2 consist of a differential amplifier with built-in zener reference together with facilities for short-circuit
protection.
12.4.6 Short-Circuit Protection
Drop-through series resistors (e.g., RIO in the -10 V supply), provide short-circuit protection. If the drop across
RIO exceeds approximately 0.6 V, Q5 is turned on, connecting Q4 base to emitter and cutting off Q4. This
corresponds to approximately 1.5 A under short-circuit conditions. Similar circuits are provided in ICI and IC2.

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Part III

12.5 TYPE 3842 CONTROL INTERFACE MODULE CIRCUIT DESCRIPTION (TD9)
This module contains a set of receivers for the adapter control commands:
FWD MOT
REV MOT
OVERWRITE (Not used)
RWND PLS
SEL DRIVE
WRE LTCH
OFF LINE PLS
It also contains drivers that return the recorder status outputs to the interface:

DRIVE ON LINE
RWNDG
WRLCK
LOAD POINT
WRITE ENB (Not used)
XPRT RDY
END OF TAPE
TAPE RUNNING STATUS (Not used)
Certain controls and delays are also provided to ensure proper tape motion and transport operation.

12.5.1 Tape Motion Controls
The motion control commands from the adapter, FWD MOT and REV MOT, are translated on this card into
the internal motion commands of the transport: run normal (RUN CMD) and reverse (REVERSE CMD).
These internal motion commands are supplied to the pushbutton control modules, where they are combined with
commands supplied from the transport push buttons and internal interlocks to generate the commands that
initiate actual tape motion on the ramp generator module.
On this module, FWD MOT and REV MOT are supplied to an interlocking network that ensures that the tape
comes to a stop before its direction of motion is reversed. The interlocking network includes flip-flop El-3, edge
circuits E2-6 and E2-8, NAND gate E3-6, and interlocking flip-flop E3-10. Whenever flip-flop El changes states
due to a change in the direction of motion (e.g., from FWD MOT to REV MOT), its output generates a pulse
through the edge circuits consisting of inverters E2 and the associated capacitors. The pulse is gated through E3-6
to the set input of interlocking flip-flop E3-10. The flip-flop can be set only if TAPE STOPPED is true, indicating
that the tape is still moving. In this case, TAPE STOPPED low at input pin W is inverted by E18-12and supplies
a high input to the clear of E3. The flip-flop can then be set by the pulse on its set input, its 0 output going low.
The 0 output of E3 then inhibits run normal gate E15 at pin 2, setting RUN CMD false. After the tape has
ramped down to a stop, TAPE STOPPED goes false clearing interlocking flip-flop E3, whose output then
enables the run normal gate. RUN CMD then goes true if the following conditions are satisfied: SELECTED
& ON LINE is true, indicating that the transport is on-line and selected by the adapter; DRIVE BUSY is false,
indicating that the transport is not rewinding or searching for the load point; and a REV MOT command is not
given at the load point. (This would activate NAND gate E15-8 and would disable the run normal gate at E15-1.)
If the above conditions are satisfied, RUN CMD goes true at output pin V, and is supplied to the pushbutton
control module where it initiates tape motion at the normal running speed. The direction of motion is determined
by the state of flip-flop El. If a reverse command (REV MOT) has been given, flip-flop El is cleared and enables
NAND gate E14-6, generating REVERSE CMD (reverse) true, providing SELECTED & ON LINE is true,
DRIVE BUSY is false, and AT LOAD POINT is false. No adapter reverse command is acknowledged by the
transport when the load point is detected. If a forward command (FWD MOT) has been given, the El flip-flop is
set thereby inhibiting E14 and negating REVERSE CMD.
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Part III
!2.5.2 Write Select
During a write operation, the adapter supplies WRE LTCH (write latch) true at pin K; WRE LTCH is inverted
by E9-4 and is supplied to the D input of flip-flop E7. The flip-flvp is toggled provided that the transport is
selected and on-line, after NOR gate El-II is activated by a synchronous motion command. This would activate
NAND gate EI-8 and trigger one-shot E4-4, generating a 2 #lS pulse. On the trailing edge of the pulse, the Q
output of the one-shot toggles E7-3, causing the Q output of the flip-flop to go high and activating NAND gate
EIO-II, generating WRITE CMD true al output pin H. The EIO-12 input from some un\lsed circuitry stays high
to keep E I 0 enabled.
12.5.3 Rewind Flip-Flop
When a RWND PLS (rewind command) is given by the adapter, it sets the rewind flip-flop ES-3, provided that
the transport is selected, on-line, and not at the load point. The I-output of the flip-flop then goes high, generating R WNDG true to the adapter and REWIND CMD through an edge circuit consisting of inverter E6-6,
NAND gate E6-8, and capacitor CS. REWIND CMD is supplied to the pushbutton control module. The flipflop is cleared when the tape returns to and stops at the load point, or when TAPE THREADED is detected.
12.5.4 End-of-Tape
An end-of-tape indication is set when the EOT marker is encountered in the forward direction and remains set
until the marker is passed in the reverse direction.
A true END OF TAPE signal at pin Z if machine status is NOT REWINDING (ES-S,8) and REVERSE CMD
(EI4-6) causes Ell to be preset by EI9-8. An EOT status is then signaled at the interface by EI6-3.
Upon passing the EOT marker in the reverse direction, E13-3 is high and the END OF TAPE signal clocks Ell
clear on the trailing edge of the END OF TAPE signal, dropping the END OF TAPE signal at the interface. Ell
is preset to the clear state by TAPE THREADED at pin X.
12.5.5 Output Status
The status gates on this module are all preconditioned by select and on-line being true; consequently, the transport returns status indications only when it is selected and on-line. The XPRT RDY status is generated when
DRIVE BUSY, supplied from the pushbutton control module, is false and the transport is not rewinding. The
LOAD POINT output is also preconditioned by the rewinding status being false.
12.6 TYPE 3843 PUSHBUTTON CONTROL MODULE CIRCUIT DESCRIPTION (TD7,8)
The circuitry used to carry out the motion commands issued by the adapter or by the pushbutton panels (both
the main control panel and the test panel), is located on the pushbutton control module. This module generates
the motion command lines RUN NORMAL, RUN FAST, and RUN REVERSE, which are supplied to the
ramp generator module to initiate actual tape motion.
12.6.1 Front Panel Pushbutton Controls
The LOAD, ON LINE, and REWIND pushbuttons, located on the main control panel, are connected to respective flip-flops on the pushbutton control card. When the LOAD pushbutton is activated, it grounds the input to
inverter EI2-1, setting the load flip-flop which consists of NOR gate E13-6 and inverter EI2-I. Once the load
flip-flop is set, E13-6 goes low, is inverted by EI2-4, and removes the direct-clear from on-line flip-flop EIO-3.
Thus the on-line flip-flop can be set only after the transport has been loaded. When the ON LINE pushbutton is
activated the first time, it toggles EIO-I to the set, or on-line, position and the outputs of the flip-flops generate
ON LINE true. Inverters E12-8 and E12-10 are connected as a protective flip-flop on the clock input to ElO-I.
Once the on-line flip-flop has been set, ON LINE true is inverted twice by E9, setting the common of the
REWIND pushbutton on the control panel high, disabling that pushbutton. The on-line flip-flop can be cleared
by pressing the front panel pushbutton a second time, or by an adapter off-line command (OFF LINE CMD),
supplied from the adapter control module.

12-8

Part III
The REWIND pushbutton can be activated only when the transport is off-line. When activated, the REWIND
pushbutton sets the flip-flop that consists of gates E8-8 and E8-6, provided that the transport is loaded at the
time (LOAD true at E8-13) and test mode is not selected (E7-8 high). Consequently the transport cannot be
rewound by the pushbutton during test mode, when on-line, or when LOAD is false. When the transport is online, the rewind flip-flop can be alternately set by REWIND CMD, supplied from the adapter control module.
The output of the rewind flip-flop, (REWINDING), activates NOR gates E15-8 and EI4-6, generating RUN
FAST and RUN REVERSE true to the ramp generator module, initiating a fast reverse motion to the load
point. When the load point is detected, the photosensor amp driver module supplies the load point pulse at input
pin H of the pushbutton control module, clearing the rewind flip-flop.
An additional flip-flop, ElO-6, is used to locate the tape position. Before the tape is loaded, the flip-flop is cleared
by LOAD false at EIO-8. When the transport is loaded, the direct-clear is removed and NAND gate E14-11 is
enabled. Since the on-tape flip-flop is still cleared, its Q output high activates NAND gate EI4-8, generating
RUN NORMAL at output pin Y, advancing the tape to the load point. When the load point marker is detected,
AT LOAD POINT true at input pin 21 from the photosensor module is gated through E16-3 and direct-sets flipflop E 10-7 to the on-tape state, terminating the tape motion. Similarly, when the load point is detected during
reverse tape motion, the on-tape flip-flop is toggled by NAND gate E16-11 to the clear state, initiating forward
tape motion back to the load point.

12.6.2 Busy
This module generates a DRIVE BUSY output when the tape is not loaded, when it is advancing to the load
point, or when the transport is off-line and not in test mode. In any of these cases, NOR gate E4-8 is activated
and supplies DRIVE BUSY true to the adapter control module.
12.6.3 Write Ready
WRITE READY true is generated in two different cases: when the control interface module adapter supplies
WRITE CMD true and the transport is not in test mode (TEST MODE false), or when the transport is in the
write test mode and flip-flop E6-14 is set. In either case, NOR gate EI-8 is activated, enabling NAND gate E4-5.
The gate is activated provided that DRIVE BUSY is false, WRITE RING ON (file protect) is false, and the
transport is not in reverse motion (RUN REVERSE is false). E4-6 then goes low, is inverted by E5-12, and
generates WRITE READY true at output pin J to the four-channel write amplifier module.
12.6.4 Test Panel Control
To activate the test panel, the transport must be off-line and the test panel STOP pushbutton must be pressed. In
that case, the TEST MODE pushbutton on the test panel can be activated, setting the flip-flop that consists of
inverters EII-8 and EII-IO, which in turn toggles the test mode flip-flop E6-6 to the test mode state, generating
TEST MODE true. The test mode flip-flop is direct-cleared when the transport is placed on-line or when the
TEST MODE pushbutton is activated a second time. After the test mode flip-flop has been set, the other test
panel pushbuttons are enabled. The WRITE TEST pushbutton may then be activated, setting the protective flipflop consisting of inverters E 11-4 and E 11-6, which in turn toggles write test flip-flop E6-1 to the write test mode,
provided that forward motion is selected. The Q output of tne write test flip-flop then activates NOR gate EI-8,
in turn activating write ready gate E4-5, provided that WRITE RING ON, RUN REVERSE and DRIVE BUSY
are all false. In that case, WRITE READY true is generated at output pin J to the write amplifier module, where
it enables the write data strobe circuitry. During the write test, the write amplifiers generate consecutive all-Is
characters which may be used to adjust the skew.
Additional test panel pushbuttons are FORWARD RUN, a normal forward run button, FAST FORWARD, a
high-speed forward button, REVERSE RUN and FAST REVERSE buttons. The reverse motion buttons can be
activated only if on-tape flip-flop E 10 is set and the tape is not at the load point, activating NAND gate E3-3,
which in turn activates NAND gate E7-6 (when the test mode flip-flop is set) and setting the common of the
reverse buttons low. The forward motion commands are terminated when either the STOP pushbutton is activated, clearing the test mode flip-flop, or the end of tape is detected, in which case END OF TAPE IND true is
inverted by E17-4, disabling NAND gate E7-3 and setting the common of both forward motion buttons high.
12-9

Part III
Similarly, the reverse motion can be terminated by activating the STOP pushbutton, which terminates all test
mode operations, or when the load point is detected, in which case AT LOAD POINT true is inverted by E 17-3
and disables NAND gates E3-3 and E7-6, setting the common of the reverse buttons high. The pushbutton
control module also drives the test panel indicators, lighting the DATA lamp when any data is being processed
by the write/read electronics, illuminating the SKEW indicator when the skew is out of adjustment, illuminating
the EOT indicator when the transport is at the end of tape, and illuminating the LOAD POINT indicator when
the transport is at the beginning of tape.

12.7 TYPE 3645 RAMP GENERATOR MODULE CIRCUIT DESCRIPTION (TD5)
The ramp generator produces the proper analog signal inputs to the capstan servo system to control the direction
and velocity of tape motion. The outputs are voltages that rise and fall linearly at controlled rates to highly stable
levels. These analog signals are controlled by digital logic outputs from the control section. Waveforms produced
are shown with the schematic.
Two similar ramp generator circuits are provided: one for normal speed operation and one for high speed
operation. E4 is an operational amplifier in the run normal speed circuit. The amplifier output is normally
saturated in the negative direction. When its positive input at pin 5 is high, the output saturates at + 10 V. This
occurs when the RUN NORMAL input sets flip-flop E7. E4 feeds FETS Ql, Q2 which are connected in a
constant-current circuit. The magnitude of current flow in the circuit is controlled by R3 and R4. R3 controls
current in the positive-going direction, or start ramp, while R4 controls the negative-going stop ramp
Since C 1 is charged by a constant current, its voltage rises linearly until clamped by CR 1 to a value one diode
drop below +S V. Q3 is an emitter follower whose output rises to a value of +5 V, since the emitter can rise one
diode drop higher than the base. When the input from E7 to E4 drops, the voltage fed to Ql, Q2 goes to -10 V
and C 1 is discharged linearly until clamped by the base-collector diode of Q3. Since Q3 base goes one diode drop
negative, and the emitter is at zero, a positive-going ramp has been generated.
The ramp voltage output from Q3 is fed to FET switches Q4 and Q5. If forward direction has been selected, Q4 is
on and QS is off. The ramp is then amplified by unity gain operational amplifier E3, without inversion, and
appears as a positive-going ramp at test point A. If reverse is selected, Q5 is on and Q4 is off. The ramp is then fed
to the inverting input of E3 and appears as a negative-going ramp at test point A. Forward/reverse selection is
controlled by flip-flop E6 and Q9, QlO.
Ramp amplitude and, therefore, tape speed is controlled by normal speed control R14 and output summing
resistor RlS. The fast forward and reverse ramps are produced by a similar circuit involving amplifiers El and
E2. However, since rewind speed and ramp time need not be precisely controlled, resistors are used instead of
FETs to charge and discharge C4 and produce an approximate O.S second rise/fall time. CR9 and CR 10 isolate
the ramp output from any small offsets that may be present in E2. Rewind speed is controlled by summing resistor R 16. Operational amplifier ES at zero ramp output has a slight bias produced by R37 and R38, keeping its
output negative. When the ramp rises above the bias, ES switches to positive output, indicating that the tape is
running. This output is used to gate off the input circuits through ElO and E9. Flip-flops E7 and E8 may be reset
by run normal or run fast inputs going false, but cannot be set again until the tape comes to a stop. This prevents
damage from illegal commands and reduces timing requirements.
Type 364S Ramp Generator includes an additional flip-flop, Ell-8, whose function is to enable consecutive run
normal commands to be received without requiring the tape to ramp down to a stop following each normal speed
operation. Following a run fast command, however, flip-flop Ell is set by E8, inhibiting any run normal commands until the tape comes to a stop, at which point E9-6 clears Ell-9, and the 0 output at Ell-8 enables E7-2.

12.8 TYPE 3844 SENSOR AMPLIFIER/DRIVER MODULE CIRCUIT DESCRIPTION (ID6)
This module responds to signals from photo resistive cells which sense load point and end-of-tape reflective strips,
and broken tape. In addition, this module contains the file protect circuitry and the write and the erase head
drives.

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Part III

12.8.1 BOT, EOT, and TAPE THREADED Sensor Amplifiers
The load point sensor amplifier and the end-of-tape sensor amplifier operate interdependently to detect the load
point and the end-of-tape markers. The active components in detecting EOT and load point are two operational
amplifiers, E6 and E8, and two transistors. Q I and Q2, in conjunction with associated components. Transistors
QI and Q2 act as current sources; potentiometer RI6 is used to adjust the transistor base currents to equalize the
voltage at the inputs of E8, the load point sensor amplifier, and E6, the end-of-tape sensor amplifier. Resistors
R18, R19, R20, and R21 are used to bias the amplifiers' inputs when plain tape is in front of the photo sensors.
When either the load point marker or the end-of-tape marker is detected, the resistance of the respective photoresistive cell is lowered by approximately 64> percent of its unilluminated value. Each cell is returned to + 10 V, and
a 30 percent change in its resistance, causing a 30 percent change in the input potential, will be sufficient to switch
the output of the respective operational amplifier. Resistors R 17 and R22 serve as feedback loops for noise
protection. Thus when load point is detected, the load point sensor output at input pin Y of this module saturates
E8, causing its output to go high, and is inverted twice by E7 to generate AT LOAD POINT true at output pin 19
to the pushbutton control module. The output of inverter E7-8 is also supplied to an edge circuit which produces
a I /J.S pulse on the trailing edge of AT LOAD POINT. This pulse is output at pin 8 to the pushbutton control
module. The EOT sensor amplifier operates in the same manner, generating a high output when the EOT marker
is detect.ed, and supplying END OF TAPE true at output pin X to the pushbutton control and control adapter
modules.
When the broken tape photoresistive cell is illuminated, the resistance of the cell is reduced enough for the + 10 V
to turn on transistor Q3. The collector of the transistor goes to ground, generating TAPE THREADED true at
output pin 18. When LOAD SW is high at input pin U, the output of E4-8 is low. This causes the collector ofQ3
to be low through the diode CR3 and the TAPE THREADED output will be true at output pin 18. Also, when
power is initially turned on, capacitor C9 will cause the TAPE THREAD ED output to be high, which presets the
load flip-flop on the adapter control module.
12.8.2 File Protect Circuits
The file protect switch output is supplied to this module at input pin T. When a reel is loaded without a write
enable ring, the switch contact remains grounded; the switch input at pin T is inverted by E2-6 and enables
NAND gate E4-13. The gate is activated when TAPE THREADED is true before the transport is loaded.
Whenever the LOAD pushbutton has not been energized, E4-8 low grounds the clear input of flip-flop E4-1
through diode CRI4. E4-2 then issues WRITE RING ON (file protect) true at output pin 9 to the adapter
control card, while the 0 output of E4 high is inverted by E2-8 to turn off transistor Q5, disabling the file protect
solenoid output at pin P.
When a reel with a write enable ring is used, the file protect switch is opened, setting input pin T high and
enabling NAND gate E2-13. Again the gate can be activated only when TAPE THREADED is high, before the
transport is loaded. The output of the gate then goes low to set flip-flop E4-5; the flip-flop can be set only after
LOAD SW has gone false. This provision is made to ensure that the write mode can be selected only at the time
tape is first loaded. Once flip-flop E4 is set, its I output issues WRITE RING ON false, and, after being inverted
by E 1-10, lights the WRITE EN ABLE lamp through output pin H. The 0 output of the flip-flop low is inverted
by E2-8 and turns on transistor Q5, activating the file protect solenoid through pin P. The file protect solenoid
then draws in the switch pin, and the transport is ready for the write operation.
12.8.3 Write, Erase Drives
When the file protect switch is grounded, it also turns off transistor Q7, in turn shutting off the current at the
base of Q8. This cuts off the write head and erase head drive currents supplied by transistor Q8. In order for the
write and erase drives to be turned on, the file protect switch must be opened and WRITE READY must be true
at input pin 7. This will activate NAND gate E2-3 causing op amp E3 to turn off transistor Q9, in turn enabling
transistor Q8 to turn on and supply the write and erase head currents at pins 22 and J.

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Part III
The zener diode in the base of Q7 detects when power is being dropped. This turns off Q7 early enough in the
power-down sequence to turn on Q9 and remove the head current supplied by Q8. This avoids putting unwanted
remnants on tape during a power failure.
12.9 TYPE 4306 SERVO PREAMPLIFIER MODULE CIRCUIT DESCRIPTION (TD3,4)
This module contains the capstan servo and reel servo amplifier stages. The following paragraphs describe their
operation.
12.9.1 Capstan Servo Amplifier Stage
The capstan servo amplifier portion of this module is a part of a velocity servo system which produces accurately
controlled capstan speeds with linear ramp-ups and ramp-downs. The analog linear signal supplied from the
ramp generator module is input at pin N of this module and is summed with the output of the dc tachometer
coupled to the capstan motor shaft, supplied at pin P of this module. Any difference between the two voltages is
amplified by operational amplifier E5. The amplification of E5 is controlled by two negative feedback loops, one
supplied directly from the output of E5 through resistors R39, R40 and capacitor C9, and the other loop from the
capstan motor through resistor R71. The L.ero offset of the amplifier is adjusted by potentiometer R56 to eliminate capstan creep during standstill.
The output of amplifier E5 is supplied to a pair of complementary driver stages, including transistors Ql1, Q12,
Q 17, and Q18. The output of these stages is supplied to a pair of power transistors located on the heat sink servo
power assembly, which is on the rear of the unit. The power transistors' output then energizes the capstan motor,
advancing tape at accurately controlled speeds.
12.9.2 Reel Servo Amplifiers
Takeup and supply reel servos are provided to maintain tape tension at a constant value. Three main components
are included: magpot position sensor, reel servo amplifier, and reel motor.
The magpot position sensor measures tape tension by the position of a spring-loaded buffer arm. At the approximate center of the arc, sensor output is zero. As the buffer arm moves off center, a positive or negative voltage is
produced which is proportional to the error.
The output of the reel servo amplifier on this module is supplied to a pair of power transistors located on the
servo power assembly on the heat sink on the rear of the unit. The output of the power transistors then energizes
the respective reel motor, returning the buffer arms to their proper locations.
12.10 TYPE 3631 READ PREAMPLIFIER CARD CIRCUIT DESCRIPTION (TDI0)
Read Preamplifier Type 3631 includes nine identical amplifier stages which accept the analog signals from the
read head winding and supply the amplified outputs to the read amplifier modules.
The channel 0 amplifier stage is shown in the schematic; the other channels are identical. The amplifier stage
consists of high-gain operational amplifier El and negative feedback including resistors R2, R3, R4, R5, and
capacitor C2. The input head signal is filtered by resistor Rl and capacitor Cl, and is supplied to the noninverting input of El. The negative feedback network controls the output amplitude and response.
Potentiometer R4, located in the feedback network, is adjusted so that the amplified analog output at test point
A is 9 V peak-to-peak while writing 800 flux reversals per inch (see adjustment procedures in Part 1 of this
manual).
12.11 TYPE 4218 MAGPOT TENSION ARM POSITION SENSOR CIRCUIT DESCRIPTION (TD3)
In the reel servo system, it is necessary to produce an analog signal representing tension arm position. The signal
must be zero at the nominal resting position of the tension arms and should linearly represent angular deviations
from the center of arm travel by positive and negative voltages,. A common method utilizes lamps, photocells,
and a shutter to produce the required voltage. This method suffers from the mortality of lamps and the relatively
slow response of photocells.
12-12

Part III

The magpot operates as a differential transformer, an example of which is shown in Figure 12-2.

MOVABLE ARMATURE - ....

FIXED CORE

11-3050

Figure 12-2 Differential Transformer

Magnetic flux produced by current in winding 1 will produce voltages E2 and E3 in the other windings. If the
armature is symmetrically located with respect to 2 and 3, flux in the two windings will be equal, and since they
have the same number of turns, E2 = E 3. If the armature is displaced as shown, E2 > E3 since the flux coupling E3
has been reduced. Displacement in the opposite direction produces E3 > E 2. Displacement from center then is
represented by Eo = E2 - E 3. In the configuration shown in Figure 12-2, this relation is linear only for very small
displacements because area relations are not linear.
The magpot is an adaptation of the above scheme in that there are three windings on a magnetic core. The core in
this case is a ferrite pot core while the armature is half a pot core. Windings 2 and 3 are around legs of the pot
core while 1 is around the center portion common to the two legs. Winding 1 is energized by a high-frequency
oscillator (approximately 200 kHz). The magpot is in balance and E2 = E3 when the armature couples equally to
the two legs. As the armature is rotated, the area available for magnetic flux increases linearly for one leg and
decreases linearly for the other leg. Thus the difference in induced voltages is a linear representation of angular
movement.
The 200 kHz oscillator is a Hartley circuit comprising Q.l, CI, C2, RI, R2. It produces a 40 V peak-to-peak sine
wave across the primary winding.
The two secondary windings are connected in series and their voltages are rectified by CR 1, CR2. The two
rectified voltages are subtracted and referenced to ground. Thus the input to EI operational amplifier is a dc
voltage equal to E2 - E 3. This voltage is null when E2 = E3 and is positive or negative depending upon which is
larger. Secondary voltages induced are at all times large enough to overcome the diode drops in CRI, CR2.
DC output of the rectifier circuit is amplified by Eland fed from the output to the appropriate reel servo
amplifier.
Voltage output for a given angular deflection depends upon coupling between the fixed core and armature at that
setting. The gain relations are such that a spacing of 0.030 in. (76.2 mm) between core and armature results in ±5
V output for full arm travel. Spacing is established by two 0.015-in. thick plastic spacer washers on the shaft.

12-13

Part III
12.12 TYPE 4845 DELAY TIMING MODULE CIRCUIT DESCRIPTION (TDI2)
Crystal oscillator, dividers, and timing circuits associated with read electronics comprise Type 4845 Delay Timing. Use of this circuitry eliminates the need for analog delays in forming the read skew gate, detecting gaps, etc.
Since the delays required vary with tape speed, switches are provided t<> select appropriate delays. Delays
required are fractions or multipleS' of character times; therefore it is only necessary. to change the division ratio to
accomplish all required modifications. As the TM8-M System operates only at a speed of 12.5 inches per second,
the switches are shown on the logic diagram set for that speed; i.e., S2, S6 and S7 closed. Crystal-controlled
pulses generated are also supplied to write electronics in the test mode to allow writing an all Is test pattern.
12.12.1 Crystal Oscillator Divider
E5 together with several discrete components is connected as a crystal oscillator. The two inverter sections are
biased into the linear region by R 1, R2, and R3. Positive feedback thn 'lgh Y 1 causes the circuit to oscillate at the
crystal frequency. A series of dividers E2 (+ 12), El, E4 (+ 16) are selected by S2, S6, and S7 to produce two
output frequencies: 10 kHz, which is the repetition frequency of the data to be read and 320 kHz which is 32 X
10 kHz and divides the bit cell into 32 increments. These are fed to counter circuits which determine delays.
12.12.2 Skew Gate Generation
Skew gate length has three values depending upon operating mode: 1/2 of one bit cell for read, 3/8 for write,
and 5/32 for test mode. The write skew gate is shortened to provide a more stringent skew criterion to reveal
incipient skew problems.
Pulse outputs from the nine read amplifiers are wire-ORed and appear at pin R. E3 buffers the pulse input and
feeds out to the test panel for service use.
The first DATA PACKET pulse to appear clears E14 and counter E15 begins to count 320 kHz pulses. E15 has
been preset clear by low levels on inputs ABCD. At the count of 16, representing 1/2 character time, E15 QD has
been high and goes low, setting El4 and stopping the count. With E14 set, Ell, a four-stage shift register, starts
shifting right. A 1 has been preset in position A and Os are shifted in, causing the I to progress to the right. Shift
frequency is 320 kHz. At the time El4 is set, a I is in QA and El2 produces a data transfer pulse to the read
amplifiers, causing the data to appear at their outputs. At the next count QB goes high, triggering one-shot EIO (2
/JS) and producing a read data strobe RD STRB at the output. At the third count, Qc goes high as a delay, and
on the fourth count QD goes high. If strap STI is installed, a second data transfer pulse is produced, returning
the read amplifier output to zero. After the fourth shift pulse, the circuit remains quiescent until the next DATA
PACKET.
12.12.3 Skew Lamp
At a time just after the skew gate (at RD STRB time), output from E14 is inspected by one-shot EIO. If the skew
delay circuit has been retriggered by a skewed input, EI0 is triggered, producing a relatively long SKEW
ERROR pulse to the SKEW indicator lamp.
12.12.4 Write Mode
If write is selected, WRITE READY is high, causing counter E15 to be preset with a count of 4 by E12.
Operation is otherwise identical to read operation but delay is reduced from 16 to 12 counts or 3/8 of one bit cell.
12.12.S Test Mode
In test mode, delay is further reduced to provide a marginal skew check. The counter is preset by the TEST
MODE input (pin U) to E15 and delay is five counts or 5/32 of one bit cell. An all Is pattern on a properly
deskewed machine should fall within this time; however, due to bit crowding on tape, random data generally will
not.

12-14

Part III

12.12.6 Blank Space Detection
Type 4845 detects the space between the last data character and the CRC and clears read amplifier outputs. The
read amplifier outputs are again cleared after the CRC (if not all zeros) and once again after the LRC, leaving all
outputs cleared in the IRG. Whenever E 14 is set (between bits), counter chain E6, E7 counts 320 kHz; it is
cleared by E14 if a DATA PACKET is detected. Should the counter reach a count of 32, indicating a missing bit,
E7 is set which in turn sets E8. The next 320 kHz pulse, through E8 pin 3, clears E7, leaving E8 set and the
counter held clear by E8 pins 8, 12. E9 produces a RESET pulse at pin K, clearing the read amplifier. At the next
DATA PACKET, input E8 is cleared and the cycle is free to repeat. This DATA PACKET may result from the
CRC, LRC, or the first character of the succeeding block.
12.12.7 Read Delay
When the tape is stopped as indicated by RUN CMD false, SELECTED & ON LINE false, AT LOAD POINT
true or DRIVE BUSY true, the E19-6 output (INHIBIT DATA OUTPUT) is asserted thereby gating off RD
STRB pulses at E9.
Upon receipt ofa RUN CMD input, counter chain E17, E18 is enabled for a count of 128 10 kHz pulses. This
corresponds to 0.16 in. (0.41 cm) of tape movement. DuringJhis time, outputs remain disabled.
12.12.8 Data Lamp
Drive for the test panel DATA lamp comes from E14 through E8 pin 6, which is low whenever E14 is set
(between characters). An inverter on the PCB module actually drives the LED indicator.
12.13 TYPE 3848 FOUR-CHANNEL WRITE AMPLIFIER MODULE CIRCUIT DESCRIPTION (TDI3)
This module generates the internal write data strobe and contains the write amplifier stages for four of the data
channels, channel P through channel 2. These are explained in detail in the following paragraphs.
12.13.1 Write Data Strobe Generation
The REC (write data strobe) is input from the adapter at pin A and is supplied to an edge circuit consisting of
inverters E5 and E6, capacitor C8, and NAND gate E6-8. If WRITE READY and SELECTED & ON LINE are
true at input pins 12 and 13 of E6, the gate transmits a short pulse on the leading edge of each REC input. The
pulse is gated through NOR gate E5-6 and triggers one-shot E1-1 on its trailing edge. The Q output of the oneshot supplies a positive 0.5 !J,S pulse which is gated through NAND gate E7-3, provided that the transport is not
in a test mode. The pulse then enables write NAND gates Ell and E 15*, gating the input write data to the write
amplifier stages. It is also supplied as WRITE DATA STROBE to Type 3849 five-channel writt: amplifier module. When El-13 generates the write strobe, its Q output triggers the second E1 one-shot, which in turn inhibits
E6 for a 3.5 !J,S duration, inhibiting any pulses during that time.
If the transport is in test mode, TEST MODE true at pin K enables NAND gates E5-2 and E7-10, 12 while
disabling NAND gate E7-2. If WRITE READY is true, crystal-controlled data frequency (10 kHz) supplied
from the delay timing module, is gated through NAND gate E5-12 and NOR gate E5-6 to generate the test mode
strobes. These are gated through the E7-8 and E7-11 NAND gates and direct-clear the write amplifier flip-flops
on this module and on the other write amplifier module, writing the all-is characters of the test mode.

12.13.2 Write Amplifier Stages
The data inputs are supplied from the data terminator card at pins 11, 12, 13, and 14, are inverted, and then
strobed through NAND gates Ell and E15* by the WRITE DATA STROBE, generated at test point B. The write
channels are then supplied to the amplifier stages, each consisting of a divide-by-16 counter, a pair of flip-flops,
and a pair of drivers. The amplifier stages are digitally deskewable, where the delay of channels 0 through 7 is
adjusted to coincide with that of the reference channel, channel P, when read back.
*E15 is the Ell equivalent in channels I and 2 which are not shown.

12-15

Part III
The delay of channel P is permanently set to the count of eight, equivalent to 1/4 character delay, by counter E8.
\\thenever the input data is 1, the WRITE DATA STROBE pulse is gated through EII-8 and direct-clears flipflop E9-13. The Q output of the flip- flop goes high, removing the direct-clear from the E8 counter. The counter is
then clocked by 320 kHz at 32 times the data frequency until the count of eight, at which point the Qd output of
the counter goes low and toggles the E9 flip-flop to the set state. The Q output of E9 then goes low, locking the
counter and toggling the output flip-flop E9-9. During the next 1 character, the same process is repeated with
output flip-flop E9-9 toggling to the opposite state. When a 0 is input, the input NAND gate EII-8 does not
transmit the write data strobe, and consequently the write amplifier flip-flops are not toggled. The outputs of
flip-flop E9-5, 6 are then supplied to a pair of drivers E 10 which energize the write head, reversing the flux for
each 1 while remaining unchanged for each 0, as required for NRZI.
The operation of the amplifier stages of the eight other channels is identical to that of channel P, except that their
delay is digitally adjustable. Four switches are connected to the parallel inputs of the skew delay counters of the
eight channels, as shown for data channel O. The skew of each channel can be measured and adjusted during the
write test mode, which writes all-l s cha:acters, by observing the analog outputs at the Type 3631 read preamplifier module.
Opening the switches reduces the count while closing them increases it. Thus when the switches are all opened,
the counter is direct-set to 16, gating the data character to the output without any delay. When the switches are
all closed, the skew counter is set at 0 and the character will be delayed 16 counts, or 1/4 character time behind
channel P.
12.13.3 Write Amplifier Reset
An LRC PLS pulse is input at pin J from the data terminator card, and is gated through NAND gate E2-3,
provided that SELECT & ON LINE is true, to set flip-flop E2-12. The I output of the flip-flop goes high,
removing the direct-clear from shift register E3. The register is then clocked by 320 kHz at 32 times the data
frequency. On the seventh pulse, the Qg output of the register goes high and is inverted by E4-8 to issue WRITE
RESET, resetting the write amplifier flip-flops on this module. WRITE RESET is also output at pin H to the
Type 3849 write amplifier where it resets the flip-flops of the other amplifier stages. On the eighth pulse to the
register, the Qh output goes high and is inverted by E4-11, clearing flip-flop E2 and locking itself until the next
LRC is issued by the interface.
12.14 TYPE 4178 QUAD READ AMPLIFIER MODULE CIRCUIT DESCRIPTION (TDI0, 11)
Quad read amplifier type 4178 accepts amplified head signals from the head preamplifier module and supplies
decoded and deskewed data outputs to the adapter. Each module contains four amplifier stages., and each transport contains two of these modules. The channel P amplifier stage is located on the read amplifier/clipping
control module. The operation of the channel A amplifier stage is explained in the following paragraphs. The
other amplifier stages operate identically.
The amplified analog signal is supplied from the read preamplifier at input pin J. The signal is filtered through
R 1; the negative half-waves are routed through diode CR 1 while the positive half-waves are routed through CR2.
CRI and CR2 are back biased by the negative and positive clipping levels, respectively, supplied from the Data
Clip Level Control to eliminate spurious baseline pulses. The negative half-waves are then differentiated by C4
and R6 and are input at the inverting input of operational amplifier EI. At the leading edge of the negative
analog half-wave, the differentiated output of C4 and R6 swings negative, crossing zero at the peak of the analog
signal and then going positive until the trailing edge of the analog signal. Normally the op amp output is low,
since the noninverting input of El is negatively biased through R7 and R9. When the leading edge of the
differentiated signal exceeds the input threshold, the output of the amplifier swings positive. The amplifier output
returns to 0 V at the zero crossover of the differentiated signal, corresponding to the peak of the input analog
signal. A similar transition occurs for the positive half-wave, since it is input at the noninverting input of the
amplifier. Consequently the amplifier output goes high and returns low for each I character, with the negativegoing transition occurring at the analog peak. The output of the amplifier is limited by diodes CR3 and CR4 and

12-16

Part III

is inverted by NAND gate E2-3. E2-3 output is supplied to a filtering network, consisting of C6, R 11, R 12, and
CR5, whose output is in turn supplied to the Schmitt trigger input of one-shot E3. The output of E2-3 is normally
high, and the voltage at the input of E3-5 is at 3.3 V. When the output of El swings positive, E2-3 goes low and
capacitor C6 discharges through R12 with a slow time constant, approximately 5 p,s at 25 in./sec. The voltage is
clamped at 0 V by diode CR5. When the output of EJ goes low again at the peak of the analog input, E2-3 goes
high and C6 charges with a much faster time constant, approximately 300 ns. When C6 charges up to 1.8 V, oneshot E3 triggers, generating a 300 ns pulse:The Q output of the one-shot is connected back to E2-2, disabling the
gate and preventing the one-shot from being retriggered by spurious pulses on the input.
The positive pulse generated by the Q output of E3 is inverted by E2-11 and is output as DATA PACKET at pin
V. The pulses of all the amplifier stages are wire-ORed and supplied to the delay timing module where they are
used for read deskewing and read data strobe generation. The Q output of one-shot E3 direct-sets flip-flop E4-4,
the data storage register. The Q output of E4-5 sets the D input of output register E4-12 high. A skew delay time
is provided for all channels to be read after the leading data pulse is detected. TRANSFER DATA (supplied
from the delay timing module) toggles the output register flip-flops of all channels simultaneously after the
allowed skew delay time, outputting the deskewed, decoded data to NAND gate E2-9 and, on its trailing edge,
clears the first stage of E4. The gate is enabled by INHIBIT DATA OUTPUT false, supplied from the delay
timing module at input pin S. E2-8 supplies the output data at pin W to the interface. The length of the skew
delay time is varied" depending on the operation being performed. This is described in the delay timing module
circuit description.
12.15 TYPE 4179 READ AMPLIFIER/CLIPPING CONTROL MODULE CIRCUIT DESCRIPTION
(TDIO)
This module contains the P channel read amplifier stages and the read amplifier clipping level control. The
operation of the P channel amplifier is explained in the circuit description of the quad read amplifier module, and
the read amplifier clipping level control is explained below.
The read amplifier/clipping control provides four clipping levels to the read amplifier: normal, low, high, and
very high. When an error is detected during a read operation, the transport may be commanded by the tape
control unit to backspace over the erroneous block to reread it. The clipping level is kept at a normal level during
the first reread. If a second reread is commanded, the clipping level is switched from normal to a lower clipping
level, to compensate for a possible partial dropout. If a third reread is initiated, the clipping level is switched to a
higher than normal level to eliminate possible baseline noise spikes. During a read-after-write operation, the
normal and high clipping levels are combined to supply a still higher clipping level which is not used during a
read operation. The switching of the clipping levels is explained in detail below.
The initial stage of the circuitry will be both E 10 flip-flops set and both E II flip-flops clear. This is established by
DRIVE BUSY at pin Y true when tape is initially loaded or rewound. Since the first command from the load
point is always a run forward command, RUN CMD (run normal) at pin H true and REVERSE CMD (reverse
select) at pin W false causes E8-8 to be low, clearing the E9 flip-flop. The EIO flip-flops remain in the set state
when clocked by E9-3 high. The circuitry remains in the states just described until a reverse command is given to
the tape unit. When RUN CMD and REVERSE CMD are true, E8-6 goes low, direct-clearing the EI0 flip-flops
which causes EI0-8 to go high removing the direct-clear from the Ell counter flip-flops. Also E8-6 low ~ets the
E9 flip-flop which makes E9-6 low; El1-12 toggles causing El1-3 to go high, putting the counter in the "01"
state. The clipping level does not change because the E12, E13 gating described in the next paragraph establishes
the same clipping level. The circuitry will now remain in this state until a forward command is given. The next
forward command causes E8-8 to go low, clearing the E9 flip-flop and toggling EIO-5 high. At this point two
things could happen: the tape unit will be commanded to go forward to continue reading the next data block,
or to backspace if the adapter decides to reread the data block. If the tape unit is commanded to go forward to
continue reading, then E8-810w makes E9-3 high, causing EI0-8 to go low which direct-clears the Ell counter to
its initial state. If instead the tape unit is commanded to go in reverse, EII-12 goes low, toggling the Ell counter
to its next state. This establishes the next clipping level in the sequence.

12-17

Part III
The EI0 flip-flops are cleared asjust described. The Ell counter will continue to toggle every time the tape unit is
commanded to backspace after being commanded to go forward once, Two forward commands in succes~ion
will reset the Ell counter by setting EI0-8 low, and reading oontinues at the normal clipping level.
The clipping levels established by the Ell counter through E12 and E13 are as follows:
1.

00 and 01 cause E13-6 and E13-11 to be low and E13-3 to be high, establishing the normal read
clipping level;

10 causes E13-6 and E13-3 to be low and E13-11 to be high, establishing the low clipping level;

11 causes E13-3 and E13-11 to be low and E13-6 to be high, establishing the high read clipping level.

During a read-after-write operation, WRITE READY at input pin J is inverted by E7-12 and disables the
automatic clipping level control by direct-setting the EIO flip-flops, keeping the Ell counter direct-cleared. At
the same time, WRITE READY true activates NOR gate EI3-4, enabling the higher clipping level, while the Q
output of E11-510w enables the normal clipping level. Thus the normal and high clipping levels are combined to
generate a still higher clipping level used during read-after-write only.
The automatic clipping level control is also disabled when DRIVE BUSY is true at input pin Y of the module. In
this case, NOR gate E7-6 is high, and direct-sets the E10 flip-flops which in turn keep the reread counter Ell
cleared.
Operational amplifier E6 is connected with negative feedback through R26, establishing its gain at a value
determined by the ratio of the input resistance to +10 V switched by E13 to the value of R26 (22K).
Capacitor C 10 acts as an integrator, slowing the response of E6 to a change in input, which avoids coupling
enough signal through C4 and C5 into El to cause a spurious output. E5 is connected as an inverter, outputting
an equal but opposite polarity voltage to that voltage at E6-6. The negative clipping level voltage (TPD) and
positive clipping level voltage (TPC) are then applied to each read amplifier through a resistor-dividing network
to back bias diodes CR 1 and CR2. This establishes the amplitude of analog input from the read preamplifier
required for E 1 to switch and thus detect data.

12-18

Part III

CHAPTER 13
PARTS IDENTIFICATION

Figures 13-1 through 13-3 and Tables 13-1 through 13-3 show the location and identify parts comprising the
TS03 DECmagtape Transport. Tables 13-4, 13-5, and 13-6 list replaceable/spare parts.
NOTE

See the engineering drawing set for parts information on
the M8920 adapter module.

13-1

Part III
6

8,9

9,10

7856-8

Figure 13-1

Front Panel Parts Identification
13-2

Part III

Table 13-1
Illustrated Parts Breakdown for Figure 13-1

1
2
3
4
5
6
7
8
-9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

Description

Part No.

Item

151-0057-001
151-0038-001
190-444 8-00 1
291-3922-xxx
391-4440-xxx

190-2744-001
198-0011-001
190-2772-001

*
*

291-1509-001

*
*
*
*
*

190-4554-001

*
*
*
*
*
*
*
*

190-4013-001
191-0805-001

*
*

Control Panel Assembly (Note 1)
Pushbutton Switch Assembly
Power Switch
LED Display, PC Board Assembly
Switch Cover (Note 1)
Control Panel (Note 1)
Dust Cover Assembly
Hub, Quick Release (Note 2)
Hub Bearing Assembly
Takeup Hub
Capstan Wheel
Tape Guide Assembly
Head Cover (Note 1)
Head Assembly
Photosensor Assembly, Load Point, EDT
Photosensor Assembly, Broken Tape
Tape Cleaner
Tension Roller Guide Assembly
Tension Arm Bearing Assembly
Magpot Tension Sensor Assembly
Magpot Circuit Module
Spring, Tension
Tension Arm Assembly
Reel Motor Assembly
Belt, Supply Drive
Belt, Takeup Drive
File Protect Switch Assembly
Connector PC Board Assembly
Pulley, Reel Drive
Capstan Motor/Tachometer Assembly
Read Preamplifier PC Board Assembly

NOTES
1.
Specify logo and paint color if different from standard.
2.
Order repair kit 198-0100-001 as spare (Table 13-6).
*Indicates replaceable part. For part number, see Replaceable Parts List (Table 13-4).

13-3

Part III

7856-98

Figure 13-2 Tape Transport Parts Identification (Top View)

134

Part III

7
2

3
7856-4A

Figure 13-3 Tape Transport Parts Identification (Rear View)

13-5

Part III
Table 13-2
IDustrated Parts Breakdown for Figure 13-2
Item

1
2
3

Part No.

Description

190-4442-001

Power Supply ICard Cage Assembly
Transformer Assembly
CapaCitor, 18,000 mF/25 V
Capacitor, 39,000 mF/lO V
Motherboard Assembly
Rectifier
Servo Preamplifier Module
Sensor Amplifier/Driver Module
Ramp Generator Module
Pushbutton Control Module
Control Interface Module
Control terminator Module
Delay Timing Module
Read Amplifier/Clipping Control Module
Quad Read Amplifier Module
Data Terminator Module
Four-Channel Write Amplifier Module
Five-Channel Write Amplifier Module

*
*
*

4
5

190-4206-001

*
*
*
*
*
*

7
8
9
10
11
12
13
14
15
16
17
18

190-3841-001

*
*
*
190-3860-001

*
*

*Indicates replaceable part. For part number, see Table 13-5.

Table 13-3
Illustrated Parts Breakdown for Figure 13-3
Item
1
2
3
4
4
4
5
6
7
8
9
10
11
12

Part No.

*
190-4352-001
127-0003-001

*
*
*
*
*
148-0122-001
148-0121-001
148-0102-003
148-0102-004
148-0053-001
148-0075-001

Description
Voltage Regulator/Servo Power Assembly
Voltage Regulator PC Board Assembly (Note 1)
Power Receptacle
Fuseholder
Fuse, 3AG, 3 A (115 V operation)
Fuse, 3AG, 1.5 A (220/230 V operation)
Switch, 115/220 V
Power Cord (not shown)
Power Transistor Type MJ802 Motorola (Note 1)
Power Transistor Type MJ4502 Motorola (Note 1)
Power Transistor type MJ900 Motorola (Note 1)
Power Transistor Type MJ 1000 Motorola (Note 1)
Power Transistor Type 2N3055 (Note 1)
Power Transistor Type 2N4910 (Note 1)

NOTES
1.
Normally voltage regulator/servo power assembly is replaced as a module. These
parts are listed for reference purposes.
*lndicates replaceable part. For part number, see Table 13-6.

13-6

Part III
Table 13-4
Replaceable/Spare Parts for Figure 13-1
Description

Qty Spare

Note

Item

Part No.

1984439-001

Control Panel Assembly

198-2771-xxx

Dust Cover Assembly

198-2605-001

Capstan Wheel

198-1509-001

Tape Guide Assembly

198-2399-010

Head Assembly, Nine-Track

198-2399-003

Head Assembly, Seven-Track

198-1138-001

Photosensor Assembly, Load Point/EDT

198-1139-001

Photosensor Assembly, Broken Tape

198-2747-001

Tape Cleaner Assembly

198-2647-002

Roller Guide Assembly

198-0013-001

Magpot Tension Sensor Assembly (includes Magpot
Circuit Module)

198-0017-002

Spring, Tension (package of 2)

198-2827-001

Tension Arm Assembly

198-4438-001

Reel Motor Assembly

25/
26

198-0101-001

Belt Kit (1 each supply /takeup)

198-2641-001

File Protect Switch Assembly

198-2484-00 1

Capstan Motor Assembly

198-3631-xxx

Read Preamplifier Printed Circuit Board Assembly

NOTES
1. Unless specified, control panels and dust covers will be shipped with standard paint colors. If special paint
or logo is required, please specify.
2. Head is supplied on mounting plate and with face shield and connector. Specify number of tracks. All heads
are read after write with side mounted erase. Deskew chart is furnished with each head.
3. Capstan motor/tachometer assembly is supplied with capstan wheel in case of damage to capstan in
removal.
4. Assembly varies with speed of machine. Please specify when ordering.
5. Delay timing module version varies with machine specifications. Consult card identification strip or
schematic section for module type required.
6. Heat sink assembly includes regulation module 1904352-001. This module is not readily replaceable
without replacing heat sink.
7. Repair kit contains those items subject to wear.

13-7

Part III
Table 13-5
Replaceable/Spare Parts for Figure 13-2
Item

Part No.

198-4474-601

Transformer Assembly

198-3625-199

Capacitor, Electrolytic, 18,000 mF, 25 V min

198-3610-449

Capacitor, Electrolytic, 39,000 mF, 10 V min

198-0108-001

Rectifier, MR751, Motorola (package of 6)

198-4306-xxx

Servo Preamplifier Module

198-3844-001

Sensor Amplifier/Driver Module

198-3194-xxx

Ramp Generator Module

198-3843-001

Pushbutton Control Module

198-3842-001

Control Interface Module

198-4845-xxx

Delay Timing Module (9-track, special)

4,5

198-4179-xxx

Read Amplifier/Clipping Level Module

198-4178-xxx

Quad Read Amplifier Module

198-3848-001

Four-Channel Write Amplifier Module

198-3849-001

Five-Channel Write Amplifier Module

Description

Qty Spare

Note

Table 13-6
Replaceable/Spare Parts for Figure 13-3
Description

Qty Spare

Item

Part No.

198-4441-001

Voltage Regulator/Servo Power Assembly

198-0802-001

Fuse Holder

198-0133-030

Fuse 3AG, 3 A (115 V) (box of 5)

198-0133-015

Fuse 3AG, 1.5 A (230 V) (box of 5)

198-5001-103

Switch, 115/220 V

198-0068-001

Power Cord

198-0100-001

Hub Repair Kit

198-0102-001

Brush Replacement Kit, Reel Motor (4 brushes)

198-0103-001

Brush Replacement Kit, Capstan Motor (2 brushes)

13-8

Note
6

Part I

APPENDIX A
'TM8-E/TS03 CONTROL TEST, PART 1

IDENTIF"ICATIO~

.. -----------.
PRODUCT CODE:
P~ODUCT

NAMEJ

MAINDEC-~8-DHTSA·A·D

TMS-E/TS03 CONTROL TEST PART 1

DATE CRF;ATECt

JUNE 75

MAINTAINER.

DIAGNOSTIC GROUP

AUTHOR:

R, B, BARNES

THt INrORMATION IN THIS ~OCUMENT IS SUBJECT TO
CHANGE WITHOUT NOTICE AND SHOULD NOT BE CONSTRUED
AS A COMMITMENT BY CIGITA~ EQUIPMENT CORPORATION.
DIGITAL EQUIPMENT CORPORAT10N ASSUMES NO
RESPONSIBILITY fOR ANY ERRORS THAT MAY APPEAR IN
THIS MANUAL,
THE SOrTWARE DESCRIBED IN THIS DOCUMENT IS
rURNISHED TO THE PURCHASER UNOER A LICENSE rOR USE
ON A SlNG~E COMPUTER SYSTEM AND CAN BE COPIED
(WITH THE INCLUSION Of OIGITAL'S COPYRIGHT NOTICE)
ON~Y ,OR UIE IN SUCH SYSTEM, EXCEPT AS MAY
OTHERWISE BE PROVIDED IN WRITING BY DIGITAL,
DIGITAL EQUIPMENT CORPORATION ASSUMES NO
R.ESPONSIBILITY rOR THE USE OR RELIABILITY or ITS
SO'TWARE ON EQUIPMENT THAT IS NOT SUPPLIEO BY
OIOITAL,
CO'YRIGHT ec) 197', BY CIGITAL EQUIPMENT CORP"

A-I

MAYNAHO MA,

Part I

NOTE:

T~ERE ARE rIVE DIAGNOSTIC PROGRAMS ASSOCIATED WITH THE TMe·E/TS03 DECMAGTAPE
CONTROL A~D ITS TRANSPORT SYSTEM, ALTHOUGH PHYSICALLY SEPAHATE, THESE
PROGRAMS MUST BE TREATED AS A LARGE INTEGRATED TEST, AND TO (NSURE PROPER
SYSTEM OPERATION, THESE T~STS HUST BE EXECUTED IN THE ORDER D~LINEATED BELOW,

Ir A GIVE~ TEST SHOULD FAIL AND IT A~pEARS THAT A rIX HAS BEEN fOUND,
ALL PROGRAMS MUST ONCE AGAIN aE RUN, ONLY WHEN A~L TESTS HAVE HUN WITHOUT
ANY UNACCEPTABLE ERRORS CAN THE TM8-E/TS~3 SYSTEM BE CONSIDERlD UP,

TMS.E
PROGRAMS'
ORDER
or _____
EXECUTION
• • __ DIAGNOSTIC
________
. _ . ______
• ___
__ w_

--_-.-~

TM8-E/TS~3

CONTROL TEST PART 1

(MAINDEC-~8-DHTSA)

TM8-£/TS~3

cONTROL TEST PART 2

(MAINOEC-~8-DHTSe)

TM8-E/TS03 DRIVE FUNCTION TIMER

(MAINDEC-~8·0HTS~)

••,. TM8-E/TS03 DATA RELIASILITY 9 TRACK (MAINDEC·ZS-UMTSC)
TM8-E/TS0;} MULTIDRIVE DATA EXERCISER
SYSTEM)

A-2

(MAINOEC·~8·DHTSO)

(IF' 4;(

sysn.:;.j)

( 1f 81< OR LARGER

Part I

TAB~E

OF CONTENTS

~-------------.--

ABSTRACT

2.3

REQU I ~n1ENTS
HAROWARE
'1EMORy
PRELIMINARY ~ROGRAMS

:5 •

CONVENTIONS

••

PROGRAM LOAOING pqOCEDURE

PROGRAM STARTING PROCEOVRE

STANQARO TEST PROCEOURE

F'RCGRAM CONTRO~S
PROGRAM MONITOR CONTRO~ VIA KEYBOARO COMMA NOS
TEST SE~ECTION COMMANDS
TEST CONTINUATION COMMA NOS
TEST INTERRUPT COMMAND
MISCELLANEOUS COMMANDS
SWITCH REGISTER CONTRO~ OPTIONS

2.1
2.2

1.1
&.1.1
'.1.2

'.1. J

1.1.4
1.2

8.:5.1

ERRORS
ERROR HALTS
ERROR REPORTS
STANDARD ERROR RECOVERY PROCEOURE
SUB TEST ~OOPS

RESTRICTIONS

8.
1.1

e.2

8.J

EXECUTION TIME
11.

rEST A8STRACTS

12.

LISTING

A·3

(PAGE 1)
1.

ABSTRACT
T~E TM8-E/TS03 CONTRO~ TrST PART 1 IS A~ I~TEGRATED SERIES or SUBTESTS DESIGNED TO AID IN T~E CHECKOUT AND MAINTENANCE OF T~E
T~e-E DEC~AGTAPC CONTRO~ WITHOUT DEPENDENCE ON TRANSPURT SySTEM USE. VERSATILITY OF USEAGE IS AFFORDED THROUGH A MODEST KEY.
BOARD MONITOR AND SWITCH REGISTER CONTROL OPTIONS,

THIS PROGRAM CONSISTS Or 12 MAJOR TESTS (TEST ~l THROVGH TEST
or WHICH CONSISTS or A NUMBER or SUBTESTS DESIGNATED
8Y THE LETTERS A THROUGH i.

14) EACH

REQUIREMENTS

PDP-8/E, 81M, Sir
TELETYPE OR COMPATIBLE OEVICE (TTY)
T~B-E

2.2

D£CMAGTA~E

CONTRO~

~EMORY

THIS PROGRAM REQUIRES 4K or MEMORY AND MAY RESIDE IN ANY MEMORY rIELD, ALL or EXISTING MEMORY IS USEO
TO TEST THE ABILITY Of THE TM8-E TO ADDRESS CORRECTLY DURING
OMA T~ANsrERS.
2.3

PRELIMINARY ~ROGRAMS
ALL PROCESSOR/MEMORY ~IAGNOSTICS

Part I

(PAGE 2)
3.

~ONVENTIONS

-----.-- .....
I~ THE DESCRIPTION or ANY KEYBOARD COMMANOS GIVEN IN T~lS MANUAL, THE SACK ARROW (~) CO~RESPONDS TO DEPRESSING THE RETURN
KEV, AND THE NUMBER SIGN (#) CORRESPONDS TO DEPRESSIN~ THE
LINE .. rEED KEY,

THE pROGRAM PRINTS A LErr BRACKET CC) WHEN IT IS READY TO ACCEpT A KEYBOARD
COMMAND.
4.

PROGRAM LOACING PROCEDUR[
.----.----~------

---~.-

LOAD THE PROGRAM INTO ANV DESIRED MEMORY rIELO USING THE
STANDARD BINARY LOADER TECHNIQUE.
5.

PROGRAM STARTING pROCEDURE
.~~--~--~---------~.-.~

...

LOAD ADDRESS ~2~O,

LOAD THE EXTENDED AODRESS WITH THE PROGRAM FIELO.

SET THE SR TO 40~a,

DEPRESS CLEAR, THEN CONTINUE,

THE PROGRAM WILL PRINT ITS TITLE AND MAINDEC NUMBER, THEN
ASK "ExTENDED MEMORy7(0-7)". TyPE THE NUMBER Of THE HIGHEST
EXISTING MEMORY rIELD. THEN THE PROGRAM MONITOR WILL ASSUME
CONTROL, GO TO THE STANDARO TEST PROCEDURE IN PARAGRAPH 6,

~OTE:

THE PROGRAM MAY BE RESTARTED AT ANY TIME AT ADURESS
IN THIS CASE THE PROGRAM ByPASSES ALL
PROGRAM INITIALliATION AND GOES DIRECTLY TO TH~ ~RO·
GqAM MONITOR TO ACCEPT KEYBOARD COMMANDS.
~201,

A-5

Part I

(PAGE 3)
STANDARD TEST PROCEDURE
.------------.----~~--.

USt Or T~E STANDARD TEST PROCEDURE ENSURES PROPER TM8~E
CHECKOUT. ANY ERROR OCCURRENCE RESULTS IN AN ERROR R~PORT
ON THE TTY AND IN A R~TU~N TO THE PROGRA~ MONITOR, A~~ OP.
TIONA~ T~ST PROCEDURES AffORDED BY PROGRAM MONITOR ANU SWITCH
REGISTER CONTROL ARE DESCRIBED IN PARAGRAP~ 7. ERROR R~.
COVER V PROCEDURES AND RELATED INfORMATION ARE GIVEN IN PARAGRAPH 8.
ACCOM~LISH

THE fOLLOWING STEPS.

START THE PROGRAM AS DESCRIBED IN PARAGRAPH 5.

Ir A T513 TRANSPORT SYSTEM IS CONNECTED, ENSURE THAT ALL
DRIVES ARE orf ~INE. ALL LEVELS INPUT rROM THE TSeJ TO
THE TM8-E SHOULD BE AT A "HIGH" LEVEL.

SET THE SR=~0~1.

TYPE "TA~" WHICH RESU~TS IN THE EX£CUTION OF TEST e1
THROUGH TEST 14. SEVERAL PASSES WILL BE HAOE OF EACH TEST.

AfTER A~~ TESTS HAVE BEEN EXECUTED, THE PROGRAM WILL PRINT
"PASS 0~01". THEN ANOTHER PASS IS AUTOMATICALLY STARTED.

ALLOW THE PROGRAM TO RUN tOR AT LEAST 2 PASSES.
EACH PASS TAKES APPROXIMAT[~Y 15 MINUTES.

A-6

funl

PROGRAM CONTROLS
-----~---.---

(PAGE 4)

THE FOLLOWING SUB~ARAGRAPHS OESCRIBE THOSE CONTRO~S W~ICH
T~£ USER HAS OVER THE PROGRAM,
THERE ARE TWO MAIN SOURC£S Of PROGRAM CONTROL: A) PRQGHAM
MONITOR CONTRO~ VIA KEySOARD COMMANDS; ANO B) SWITC~ ~E
GISTER CONTRO~.
7.1

PROGRAM MONITOR CONTROL VIA KEYBOARD COMMANDS
-.------------~-------------~-.---.--~-------

THf PROGRAM MONITOR KEYBOARD COMMANDS ARE DESCRIBED eE~OW.
IF A COMHANO ERROR IS DETECTED, MONITOR ~RINTS "?"
AND T~E COMMAND MUST BE RETYPED. COMMANDS MAY BE INPUT ArTER
MONITOR ~AS PRINTED A ~ErT BRACKET ct). T~E TEST INTERRUPT
COMMAND MAY BE TY~EO AT ANY TIME.
THE pROGRAM MONIToR IS ENTERED UNDER ANY or THE FOLLOWING
CONDITIONS.

7.1.1

ArTER PROGRAM STARTUP WITH SR 0-1, OR A RESTART AT 0281.

AN ERRO~ OCCURS AND SR2=0.

ALL SELECTED TESTS ARE DONE.

T~E TEST INTERRUPT COMMAND (REFERENCE PARAGRAPH 7.1.3) IS
TyPED By THE USER,

TEST SELECTION COMMANOS
.~.--.-----.~-----.--

THE FOLLOWING COMMANDS ARE USED TO SE~ECT FROM ONE TO TWE~VE
TESTS FOR EXECUTION, REGAROLESS OF THE ORDER IN WHICH A TEST
SELECTION IS MADE. THOSE TESTS ARE EXECUTEO IN NUMERICAL ORDER,
rr A GIVEN TEST IS SPEClrIEO TWICE IN THE SAME SELECTlON,
IT WILL 8£ DELETED fROM THAT SE~ECTION,
COMMAND
-~-~--

TA~

RUN ALL TESTS (TEST 01 THROUGH TEST 14)

T~lT10TN~~

RUN THE T~ST(S) INDICATEO. T01 THROUGH
T14 IN OCTAL ARE T~E VALlO SELECTIONS. If
THE US~R SELECTS OTHER THAN T01 THROUGH T14
THE PROG~AM WILL EXECUTE ONE or THE VA~ID
TESTS (UNDETERMINED),

Part I

7,1,2

TEST

(PAGE: 5)
COMMANDS

CONTI~UATIO~

T~E FOLLOWING COMMANDS ARE USED TO CONTINUE IN THE rEST SEOU£NCE IF T~AT SE~UENCE ~AS BEEN INTERRUPTED BY AN lRHOR
WITH SR2:~,

COMMAND

RESULT
.---_
..
CONTlNUE IN T~E TEST SEQUENCE, IF NO T~STS
ARE SELECTED, MONITOR WILL PRINT "1". If
THIS OCCURS A NEW TEST SELECTION MUST BE
MADE.
CONTINUE WIT~ T~E NEXT SUeTEST If THE CURRENT
SUBTEST IS fAI~lNG AND SEVERAL SETS Of DATA
REMAIN TO BE USED IN THAT SUBTEST. THIS
COMMAND ENABLES THE USER TO EXIT A fAl~lNG
DATA SUBTEST AND CONTINUE WITH THE NEXT SUBTEST,
AfTER THE CURRENT "£X~" COMMAND HAS BEEN
UTILl~ED FOR A fAILING DATA SUBTEST EXIT, IT
IS NO LONGER ErfECTIVE. IF NO TESTS ARE
SELECTED, MONITOR WILL PRINT "1". IN THIS
C~SE A NEW TEST SELECTION MUST BE MAD~.

A-8

Part I

(PAGE: 6)

7.1.3

TEST INTERRUPT

CO~MANO

--.----~--------------

THC rOLLOWING COMMA~O MAY BE USED TO INTERAUPT TESTING AND
RETURN TO THE PRJGRA~ MONITOR.
COM~MJD

ALTMOOE KEY
7.1. 4

~q SCELL A-'EOUS

COMMAND
.-~~-.-

.-- ......
I~TERRUPT
A~D "ESC"

TEST EXECUTION. RESPONDS TO "ALT"
TEST SE~ECTION IS UNAfFECTEJ.

~EYS.

COMMANDS
RSSULT

... ----

TRACE THE PROGRAM f~OW USING THE ERROH REPORT fORMAT (MODIfIED), THIS COMMAND is A PRE·
rlX TO ALL "TEST SE~ECTIQN" AND "TEST CO~TINUATION"
COMMANDS, AND RESULTS
I~ A MOUIFIED ERROR REPORT rOR EACH SUBTEST
THAT PASS~St TRACE REPORTS ARE CONTROLLED
VIA SR BITS 3 AND 4 IN THE SAME MANNER AS ERROR
R~PORTS.
~TR" REMAINS IN EFFECT UNTI~ THE
NEXT ~NTRY TO THE PROGRAM MONITOR.
DUMP THE CONTENTS Or MEMORY LOCATION ~NNN IN
fIE~D M ON THE TTY.
LINE-rEED DUMPS THE CONTENTS or T~E NEXT LOCATION; CARRIAGE RETURN
R~TURNS TO THE PROGRAM MONITOR.
TEST SE~ECTION IS UNArfECTED.

A-9

Part I

'.2

(PAGE 7)
SWITCH REGISTER CONTRO~ OPTIONS
SR BIT STATE
...

--FUNCTION
..

0
1

RUN A~~ TESTS NORMALLY.
QUICK VERIFY (ONE PASS IS MADE or EACH SELECTED TEST).

ENAiLE TEST IN PROGRESS REPORTS. AS SOON AS
A TEST IS STARTED THE TEST NUMBER (TE~TNN)
IS PRINTED ON THE TTY.
DlSAB~E TEST IN PROGRESS REPORTS.

-~.

.---~

1
2

-.~.

RETURN TO PROGRAM MONITOR ON ANY ERROH
OCCURRENCE.
RETURN TO PROGRAM MONITOR ONLY Ir A rATAL
ERROA HAS OCCURRED.

0
1

OISABL.E

•

e
1

o
1

E~ASLE

ERROR AND TRACE REPORTS.

ERROR AND TRACE REPORTS INCLUDE APPLICA~LE
DATA ONLy.
FORCE ERROR AND TRACE REPORTS TO INCLUOE AL.~
POSSIBLE DATA.
DISABLE SUBTEST LOOP.
LOOP ON CURRENT SUBTEST.
REMAINS CONSTANT.

ALL VARIABLE DATA

INHIBIT LOOPS 6-9 RESPECTIVELY,
ENABLE LOOPS 6~9 RESPECTIVELy. LOOPS 6-9 ALLOW THE USER TO LOOP ON A SMALL cRoup OF SUBTESTS WITHIN THE CURRENT TEST THERE~Y ENABLING
INCREASING THE TESTING FREQUENCY OF A SMALL SET or
fUNCTIONS. THE LISTING MUST BE REFERENCED
TO DETERMI~E WHICH SUBTESTS ARE INCLUUEO IN
EACH ~Oop. THE END OF EACH LOOP IS MARKED AS
" ••••• LOOP N••••• ".

INHIBIT LOOP ON CURRENT TEST (TEST ~1 • TEST 14).
ENASLE ~OOP ON CURRENT TEST,

TERMINATE TESTING UPO~ COMPLETION OF ALL
SELECTED TESTS AND DELETE TEST S£LECTION.
RUN ALL SELECTED TESTS CONTINUOUSLy. AT
THE COMPLETION OF EACH PASS THROUGH THE ENTIRE TEST SELECTION, THE NUMBER or PASSES EXECUTED (IN OCTAL) IS ~RINT£D (PASS ~NNN)t

A-IO

Part I

(flAGE 8)
8.

ERRORS

..... -.

8.1

£~ROR

HALTS

.-.-----~-

ARE NO ERROR HA~TS IN THIS PROGRAM. Ir AN ERROH SHOULD
OCCUR AND SR2=0. THE PROGRAM WI~L STOP TtSTING AND RETURN TO
THE PROG~AM MONITOR TO AWAIT A USER COMMAND. RErER TO PARAGRAPH
'.1 rOR AVAILABLE COMMANDS.
T~ERE

A-11

Part I

(PAGE 9)
8.2

£RROR REPORTS

.1I!t.----- ____ •

WHEN SR4.~. ERROR R~PORTS INCLUDE ONLY THAT INFORMATION
WHICH APPLIES DIRECTLY TO THE ERROR. Ir SR4=1. A~L POSSIBLE
I~rORMATION IS PRINTEO WHETHER APPLICABL~ OR NOT.
AN EX·
AMPLE Of A MAXIMUM INfORMATION ERROR REPORT IS SHOWN SELOW.

-ERel0

PClZ250 1116706 12 1 6716 Gc:gege 60:7777 00:7717
WCI1234 CA;234' CMI0000 rSII000 MSI.eee 09&0000 Ac:e001

THt SYMBOLS USED IN THE ERROR REPORTS ARt DEfINED BELOW.
SYMBOL

DEFINITION

aERNNX

iRROR OccuRREe IN TEST NN, SUBTEST X. (IF NN=I~, THE
ERROR OCCURRED OUTSIDE OF A fORMAL TEST,)

afENNX

fATAL ERROR

TRaNNX

TRACE ~EPORT INDICATOR,
IS ENABLEO.

NO ERROR OCCURRED aUT TRACE

PClNNNN ADDRESS IN PROGRAM AT WHICH ERROR WAS OETEcrEO.
I11NNNN OCTAL CODE fOR 10Tl IN A VARIABLE IUBTEST,
t2.NNNN OCTAL COOt rOR 10T2 IN A VARIABLE 9UBTEST,
THE FOLLOWING THREE SYMBOLS ARE fURTHER OEfIN~D IN TH, PRO~RAM LISTING IN THE SUB TEST COMMENTS.
CDINNNN GOOu TEST VALU~
BO:NNNN REA~ TEST VALUE (BAD)
OO:NNNN PREVIOUS GOOD TEST VALUE (OLD>

THE FOLLOWING SYMBOLS INOIeATE THE CONTENTS or THE SP~ClfIED
qEGISTER AT THE TIME THE ERROR WAS DETECTED.
WC'~N~N

waRO COUNT REGISTER

CAINNNN CURRENT ADDRESS REGISTER
CMINNNN COMMAND REGISTER
rs,NNNN rUNCTION/STATUS RE~lSTER
~SaNNNN

HAIN STATUS REGISTER

OBINNNN ~ATA BUrFER REGISTER
~CINNNN

PROCESSOR ACCUMULATOR
ERRORS,)

(VA~ID

A-12

ONLY rOR ILLEGAL SKIP

Part I

8.3

STA~DARD

(" AGE un
ERROR RECOVERY PROCEDURE

.-~.-.----~~-.--------~---.~--.--

THE STANDARD ERROR RECOVERY PROGEDURE ASSUMES THAT TH~ STANDARD
TEST PROCEDURE IS 8EING USED. THAT IS, THAT ALL ERROR OCCURRENCE~
RESULT I'l AN ERROR REPORT AND IN A RETURN TO THE PROGRAM
MONITOR,
WHEN AN [RROR OCCURS, USE THF rOLLOWING STEPS AS A GU1DE fOR
RECOVERy REfERRING TO PA~A~RAPH 6.2 fOR (RROR REPORT syMBOL
OEr UJI T IONS.

8.3.1

REfERENCE THE POINT IN THE PROGRAM LISTING INOICATED BY
THE "PC:" NUMBER.

THE (RROR CODE IN THE LISTING SHOULD MATCH THE CODE IN THE
ERROR REPORT (ERNNX OR fENNx).

COMMENTEO IMMEDIATELY BELOW THE ERROR CODE IN THE LISTING IS AN ExPLANATION Of TH[ NUMBERS PRINTED AfTER THE
GO, BD AND 00 SYMBOLS.

IN THE IMMEDIATE VICINITY OF THE ERROR CoDE AND RELATED
SUBTEST A DESCRIPTION Of THE SUBTEST WILL BE fOUND.

It THE ERROR IS rATAL CfENNX), THERE IS NO STANDARD RECOVERY. THE CAUSE Of THE fAILURE MUST BE DETERHINED
THROUGH STATIC MEANS.

Ir THE [RROR IS NON-fATAL (ERNNX), THE USER MAY ELECT TO
cONTINUE IN T~E TEST SEQUENCE (C~), OR TO ENTER A SUBTEST LOOP AS OESCRIBEO BELOW,

SUBTEST LOOPS

... ..,.-.------.

TO ENTER A SUBTEST LOOP, CARRY OUT THE fOLLOWING STEPS,
A.

sET SR BITS 2, 3 AND '-1.

TYPE "C~".

TO EXIT A SUBTEST LOOP, RtstORE THE SWITCHES TO THEIR NORMA~
POSITION.

A-I3

Part I

RESTRICTIONS

(PAGE 11)

.,-.--.----..
NONE.

1~.

EXECUTION TIME

.-.--.---_ ... --

ONt NORMA~ PASS or A~~ TESTS TAKES APPROXIMATELY ~5 MINUTES.
A QUICK VERl~Y PASS (SR0.1) TAKES ONLY 2 MINUTES,
11.

TEST ABSTRACTS

.--_ .. ----- . .,,.

TEST ~1 VERIfiES THE ~XISTENCE or THE VARIOUS 67~X ANU 671X
tOT'S EXCEPT RMSR (.714), AND TESTS THE 9ASIC OP[RATIUN or ALL
TM8~E PEGIST(RS EXCEPT THE HAIN STATUS AND STATUS PORTION O~
THE ~UNCTION/STATUS REGISTERS.
TEST 22 IS A WORST CASE DATA T[ST, DATA IS LOADED INTO AND
READ BACK rROM ALL NON.STATUS REGISTER BITS AND VERlrlEU.
TEST e3 VERlrIES THE EXISTENCE O~ THE VARIOUS rUNCTIONS (AS FAR
AS POSSIBLE WITHOUT A TRANSPORT) By CHECKING EACH FUNCTION'S
AFrECT ON CURRENT ADDRESS AND WORD COUNT INCREMENTING, AS WELL AS
VERIrVl~G THAT DATA IS TRANsrERRED BETWEEN THE CONTRO~ AND THE PROCESSOR
I~ THE PROPER DIRECTION OURING DMA TRANSr(RS.
TEST 14 TESTS THE ABILITV Or WORD COUNT, CURRENT ADORESS AND
COMMAND REGISTER BITS 6-e TO INCREMENT PROPERLy.
TEST e5 VERIfIES THAT PROPER DATA TRANSFERS ARE MAOE eETWEEN
THE DATA BUfrER AND MEMORy IN BOTH OIRECTIONS.

A-14

Part I

(PAGE 12)
TEST 06 VERIrIES THAT THE CURRENT ADDRESS REfERENCES TH( CORRECT
~EMORY LOCATION AND THAT COMMANO REGISTER BITS 6.& REfERENCE THE
CORRECT ~EMORY fIELD. A~~ EXISTING fIELOS ARE UTILIlEO IN THIS TEst
TEST 01 TESTS THE VARIOUS STATUS BITS TO CONTAIN THE PROPER
STATUS AS GOVERNED BY THE "NO TRANSPORT" CONDITION.
TEST 1~ CHECKS VARIOUS POSITIVE AND NEG4TIVE CONDITIONS or
MAG TAPE rLAG, E~ROR flAG, GO BIT, ILLEGAL fUNCTION,
READ-COMPARE ERROR AND EMA OVERflOW ERROR AS A NO
TRANSPORT CONDITION WILL ALLOW.
TEST 11 EXERCISES THE lOT'S SKEf AND SKTO UNDER I~TERESTING
AS WELL AS OTHER SKIP AND NO SKIP lOT'S IN THE
67ZX lOT DECODER.

CONDITIO~S

TEST 12 CHECKS TH~ UNIQUENESS or INTERRUPTS AS CAUSED BY
MAO TAPE fLAG AND THE ERROR flAG.
TEST 13 VERIPIES THE UNIQUENESS Of ALL 672X lOT'S IN RELATION
TO cu' A~~O SBRM.
TEST 14 COMPLETELY TESTS THE PROPER OP(RATION or THE
READ~COMPARE LOGIC.
12.

LISTING (ATTACHED)

.-'!I--".

A-IS

Part I

APPENDIX B
TM8-E/TS03 CONTROL TEST, PART 2

lOENTlrlcATtON

..... _----- .......
'RODUCT COOEI

MAINDEC-IS·OHTSS·A-O

'ROoUCT NAMEI

TM8-E/TSS3 CONTROL TEST PART. 2

DATE CREATEDI

15 JUNE 75

MAINTAINER,

DIAGNOSTIC GROUP

AUTHOR:

R. B. BARNES

THE INrORMATION I~ THIS OOCUMENT IS SUBJECT TO
CHANGE WITNOUT NOTICE AND SHOULD NOT BE CONSTRUEO
AS A COMMITMENT BV DIGITAL EQUIPMENT CORPORATION.
OIGITAL EQUIPM[NT CORPORATION ASSUMES NO
RESPONSIBILITV rOR ANY ERRORS THAT MAY APPEAR IN
T~IS MANUAL..
T~E sorTWARE OESCRIB~D IN THIS DOCUMENT IS
rURNISH£D TO THE PURCHASER UNOER A LICENSE rOR USE
O~ A SING~E COMPUTER SYSTEM AND CAN BE COPIED
(WITH THE INC~USION Of DIGITAL.'S COPYRIGHT NOTICE)
ONLY fOA USE IN SUCH SYSTEM, EXCEPT AS MAY
OT~ERWISE BE PROVIDED IN WRITING BY DIGITAL.

OIGITAL EQUIPMENT CORPORATION ASSUMES NO
RESPONSIBILITY rOR THE USE OR RELIABILITV or ITS
SOPTWARE ON EQUIPMENT THAT IS NOT SUPPLIED BY
DIGITAL.
COPVRIGHT ee) 197', RY DIGITAL EQUIPMENT CORP"

B-1

MAY~AHO.

MA.

fun!

NOTE

ARE FIVE ~IAGNOSTIC PROGRAMS ASSOCIATEO WITH THE TMI-[ UECMAGTAPE
A~O iTS TRANSPORT SYSTEM,
ALT~OUGH PHYSICALLY SEPA~ATE, T~ESE
oROGRAMS ~~ST BE TREATED AS A LARGE INT~GRATEO TEST, AND TJ ~N~URE PROPER
SvST~M OPERATIO~, THESE TFSTS MUST BE EXECUTED IN THE ORDER D~LINEATED 8E~OW.
~~~~E

CO~~ROL

:r A GIVEN T[ST SHOULD rAIL AND IT APPEARS THAT A rIX HAS BEEN FOUND.
PROGRAMS MUST ONCE AGAIN Bl RUN, ONLY WHEN ALL TESTS HAV~ ~UN WITHOUT
UNACCEPTABLE ERRORS CAN T~E TMe-E SYSTEM BE CONSIDERED UP.

A_~
A~Y

T~8-E/TS. 3

DIAGNOSTIC PROGRAMS' ORDER or EXECUTION

------~-----------.---~--~----.~-.-----------

TM8-[/TS~3

CO'~THOL

TEST PART 1

(MAINDEC-~8·0HTSA)

TM8-[/TS~3

CO~TROL

TEST PART 2

(MAINDEC-~8-0HT~B)

T~8-E/TS03

DRIVE rUNCTION TIMER

TM8-E/TS03 DATA RELlABILITY 9 TRACK

T~8-3/TS~3

(MAINOEC-0e·OHTS~)

MULTIORIVE OATA EXERCISER

B-2

(MAINOtC-08-UH TSC)
(MAINDEC.~8-UHTSD)

Part I

TABLE OF CONTENTS
1•

ARSTRACT

REQUIREMENTS

~.1

\-IARDWARE

2.2
2.3

~EMORV

3•

CONVENTIONS

4•

PROGRAM LOADING PROC~OURE

PROGRAM STARTING PROCE~URE

6.
6.1
6.2

ST4NOARD TEST PROCEDURE
ORIVE SELECTION
TEST PROCEOU~E

7.1
&.1.1
'.1.2
1.1.3
7.1.4
7.2

PROGRAM CONTROI..S
PROGRAM MONITOR CONTRO~ VIA KEyBOARD COMMANDS
TEST SELECTION COMMANOS
TEST CONTINUATION COMMANOS
TEST INT[RRU'T C~MHANUS
MISC[LLA~EOUS COMMANDS
SWITCH REGISTER CONTROL OPTIONS

PRELIMINARY PROGRAMS

8.3.1
8.3.2

E:RRORS
ERROR HALTS
ERROR REPORTS
STANDARD ERROR RECOVERY PROCEDURE
SUBTEST LOOPS
~INI SCOPE LOOPS

RESTRIcTIONS

1~"

e:Xe:CUTIOrJ TH-1E

11.

TEST ABSTRACTS

12.

LISTI~G

8.
8.1
8.2
8.3

B-3

Part I

(PAGE 1)
1.

ABSTRACT
....

.----

THE TMa-[ CONTROL TEST PART 2 IS AN INTEGRATED SERIES or susTESTS DESIGNED TO AID IN T~E CHECKOUT ANO MAINT(NANCE or THE
TM8-E OrCMAGTAPE CONTRO~ AND T503 MASTER/SLAVE T~ANSPORT SySTEM, VERSATILITY Or US,AGE IS ArrORDEO THROUGH A MODEST KEY.
~OARD MONITOR ANO SWITCH RE~ISTER CONTROL OPTIONS.
T~IS .ROGRAM CONSISTS Or 12 MAJOR TESTS (TEST 15 THROUGH TEST
3~) EACH
WHICH CONSISTS or A NUMBER or suaTESTS DESIGNATED
9Y T~E LETTERS A THROUGH!. THESE TESTS PROGRESS rROM THE
rUNCTIONS TESTED I~ THE TMS-£ CONTROL TEST PART 1 AND REQUIRE
A T503 T~ANSPORT SYSTEM TO BE ON LINE rOR PROPER EXECUTION.

_.--- -----.

REQUI~EM£NTS

2.1

~AROWARE

----- .. -PDP-S/E, 81M, 8/r
OR COMPATIB~E DEVICE (TTY)
YM8-[ OECMAGTAPE CONTROL
Tse3 MASTER/SLAVE TRANSPORT SYSTEM

TE~ETYPE

2.2

MEMORY

. --_

THIS ,ROGRAH REQUIRES 4K or MEMORY AND MAY. RESIDE IN ANY MEMORV rIELO.
2.3

PR[~I~INARY PROGR~HS

.----.-------------.

ALL PAOC[SSOR/MEMORY OIAGNOSTICS
TM8-E CONTROL TEST PART 1

B-4

Part I

(PAGE 2)

CONVENTIONS

_.--------.

IN TH~ DESCRIPTION or ANY KEYBOARD COMHA~DS GIVEN IN THIS MANUAL, THE BACK ARROW (~) CORRESPONDS TO DEPRESSING THE RETURN
KEY, AND T~E NUM~ER SIGN (*) CORRESPONDS TO DEPRESSING THE
LINE-rEED ~EY. A LETTER PRECEDED BY AN UP ARROW (t) SHUULn
~E TYF'ED WI TI.f THE "CTRL" KEY DEPRESSED
THE PROGRAM PR 1NTS
LEPT BRACKET (C) WHEN IT IS READV TO ACCEPT A KEYBOARD
COMMAND.
t

,.t,

WHEN T~E PROGRAM ~RINTSI
S~TUP

DRV N (N TRK)

THE OPERATOR MUST ENSURE T~AT THE. FOLLOWING STEPS ARE CARRIED
OUT.
A.

MOUNT A SPARE REEL or INOUSTRY COM~ATIBLE MAGNETIC TAPE
ON THAT DRIVE WITH T~E fILE PROTECT RING I~ PLACE
(WRITE: ENABLED),

LOAD T~E TAPE AND POSITION AT BOT.

SET THE DRIVE SELECTOR SWITCH TO THE CORRECT DRIVE
POSITION.

n.
r.

SWITCH T~AT DRIVE ON LINE.
[NSUQE T~AT ALL OTHER ORIVES ARE orr LINE.

B-5

PROG~A~

(PA~E 3)
PROCEDURE

~OADING

.------------------~--p
~OAD T~E
STANDA~D

~ROG~AM

PROGRAM INTO ANV OESIRED MEMORY FIELD USIN~ THE
BINARY ~JADER TECHNIQUE,
STARTI~G

PROCEDURE

.--------------------_.--A.

LOAJ ADDRESS J2~0t

LOAD THE EXTENDED ADDRESS WITH THE PROGRAM rIELO.

CLEAR AL~ SWITCHES.

JEPRESS C~EA~, THEN CONTINUE.

TH( PROGRAM WILL PRINT ITS TITLE ANO MAINOEC NUHB~R. THEN
ASK rOR DRIVE SELECTION. PRIOR TO MAKING DRIVE
SELECTION, GO TO THE STANDARU TEST P~OCEOURE IN PARAGRAPH 6.

~OTE:

THE PROGRA~ HAY BE RESTARTED AT ANY TIHE AT AOURESS
a2?1. IN THIS CASE THE PROGRAM BVPASSES AL~
PQOGRAM I·~ITIALI!ATION AND GOES DIRECTLY TO rHL PROGQAM ~ONITOR TO ACCEPT KEVBOARD COMMANDS.

STA~~ARD

TEST PROCEDURE

.---------------------.

USE or THE STANDARD TEST PROCEOURE ENSURES PROP~R TM8-E/TS~3
CHECKOUT
A~Y E~ROR OCCURRENCE RESULTS IN AN ERROR RLPORT
eN T~E TTY AND I'J A RETURN TO THE PROGRAM MONITOR. ALL OPe
T!O~~~L TEST PROCE~URES AFrORDED BV PROGRAH MONItOR ANU SWITCH
REGISTER CONTRO~ ~RE DESCRIBED IN PARAGRAPH 7. ERROR RlCOVE~V PROCEOURlS A~D RELATED INF'ORMATION ARE GIV~N IN PARAGRAPH 8.
6.1

MRIVr

SE~ECTIO~

TO SPEClrV
ST£PS.
A.

c IT~~R

~ITH

T~E

DR1V~

TO BE TESTED. CARRY OUT T~l FOLLUWING

START THE PROGRAM AT 02~0 AS DESCRIBED IN PARAG~APH 5,
THE PROGRAM MONlTOR IN CONTROL TyPE "1~".
"D~lVE1"

BY TYPING THE DRIVE NUMBER (0-1).

RESPONO TO

RESPOND TO "1 OR 9 TRACK?" BV TYPING "1" OR "9".

TAKE THE ACTION DESCRIBED IN PARAGRAPH 3 TO nSErup URV
N (N TRK)".

Part I

(PAGE 4)

6.2

TEST ~ROCEDU~E
..... ----_ ...

---

THE FOLLOWING STEPS ARE TO BE ACCOMPLISHE~ rOR lACH D~IVE
I~ THE SYSTEM UN8ER TEST.
A.

SELECT T~E DRIVE UND~R TEST AS DRIVE
SET4i (REfER TO 6.1).

AND ACCOMPLIS~ THe

S~T

RESULTS IN THE EXECUTION OF TEST 1~
SEVERAL PASSES WILL BE MADE OF EACH
T[ST WIT~ THE EXC~PTION or TEST 3~. DURING TEST J~ FOLLOW THE DIRECTIONS AS PRINTED BY T~E PROGRAM. WHEN
EACH STEP HAS BEEN CARRIED OUT, TYPE ~C~" TO CONTINUE IN THE TEST.

WHEN ALL TESTS ARE COMPLETED, "SELECTED TESTS ~ONE" WILL
B~ PRINT~O ANO TH~ PROGRAM MONITOR WILL BE HEADy TO
ACCEPT A NEW COMHAND.

USING THE SAME DRIVE, SELECT THAT DRIVE AS DRIVE 1
(~EFER TO 6.1).

SET THE SR TO

TYPE "TAX"" WHICH RESULTS IN THE EXECUTION or TeST 15
THROUGH TEST 27. ONLY ONE PASS WILL BE MAD[ or EACH

THE SWITCH REGISTER (SR) TO 0000.

TYPE

"TA~" WHICH
T~ROUGH TEST 3~.

f~(1~.

TE:ST.

WHEN ALL TESTS ARE COMPLETED, "SELECTED TESTS DONE" WILL
BE P~INTEO AND THE PROGRAM MONITOR WILL BE READvro
ACCEPT A NEw COMMANO.

USING TH£ S~ME DRIVE, EXECUTE STEPS ( THROUGH H W!TH
THAT DRIVE SELECTED AS DRIVE 2, 3, 4, 5, 6 ANO 7 •

•

EACH ADDITIONAL DRIVE ON THE SYSTEM REPEAT STEPS A
TI.fRQUGInf It

~OR

B-7

Part I

pqOGRAM CONTROLS
--~-

THE
THE

(PAGE 5)

... ---- .. ---r~LL~WING
~S[R

~AS

SUBPARAGRAPHS OESCRIBE THOSE
OVER THE PROGRAM,

CO~TRO~S

WHICH

T4ER[ ARE TWO

HAI~ SoURCES OF PROGRAM CONTROL!
A) PRUGHAM
~ONITOR·CONTROL VIA KEyBOARD COMMANOS; A~O B) SWITCH HEGIST(~ CONTROL.

1.1

~ROGRAM

~ONITO~

CONTROL VIA KEYBOARD

------~--~-------~.~-----~---~-.-

COH~ANDS

----.~--

.. -

rYE pqOGRAM MONliOR KEY80AQU COMMANDS ARE DESCRIBED B~LUW.
Ir A COMMAND ERROR IS DETECTED, MONITOR PRINTS "?"
COMMAND ~UST BE RETYPED. COMMANDS MAY BE INPUT ArTER
HAS PRINTED A LEF'T BRACKET «(). TEST INTERHUfJT
COMMA-JDS MAY BE TYPE:O AT ANY TI ME.

A~D THE
MONIT~R

T~E

~~OG~AM

MONITOR IS ENTERED UNDER ANY

or THE raLLoWING

CONDITIONS.

AfTER PROGRAM STARTUP,

A'J

ALL SELECTEJ TESTS ARE DONE,

A TEST INTERRUPT COMMAND (REFERENCE PARAGRAPH 7.1.3) IS
TVPEO BY THr US~R!

ERROR OCCURS ANO SR2=L'J.

1.:.1 TEST SELECTION

CO~MANOS

--~-~-~-----~----------

rOLLOWING COMMANDS ARE USED TO SELECT FROM ONE TO TWELVE
TESTS rOR EXECUTION. REGARDLESS OF THE ORnER IN WHICH A TEST
SE~ESTIO'J IS MADE, THOSE TESTS ARE EXECUTE~ IN NUMERICAL ORDER.
IF A GIVEN TEST IS SPECIFIED TWICE IN THE SAME SE~E~TION,
IT WILL OE DELET[~ FROM THAT SELECTIO~.
T~E

--~--

...

RESULT

..........

RJN ALL TESTS (TlST 15 THROUGH TEST

3~)

RUN ALL TESTS EXCEpT TEST 30
(MAf~UAL I NTERVENT ION TEST)

T15T22TNN"

RUN THE TESTeS) INDICATEO. T15 THROUG~
T30 IN OCTAL ARE THE VALID SELECTIO~S. IF
THE USER SELECTS OTHER THAN T15 THROUG~ T30
THE PROGRAM WILL EXECUTE ONE OF TH[ VALID
TSSTS (UNDETERMlNED),
B-8

Part I

(PAGE 6)
7.1.2TEST CONTINUATION COMMANDS
-----~-----.-----~-~~.----

THE rOLLOWING COMMA~DS ARE USED TO CONTINUE IN THE TEST SEnUENcE lr THAT SEQUENCE HAS BEEN I~JTERRUPTED BY AN lR~OH
WITH SR2:0, OR AS IN THE CASE OF TEST 30 ~4ERE T~E US£R MUST
CARRY OUT SOME MANUAL INTERVENTIO~.

...COMMAND
---"' ...

RESULT

... -... '"

CONTINUE IN THE TEST SEQUENCE. If NO TlSTS
ARE SEL~CTEO, MONITOR WILL PRINT "1". IF
THIS OCCURS A NEW TEST SEL[CTION MUST Bt
MADE.
CONTINUE WITH THE NEXT SUSTEST lr THE CURRENT
SUeTCST IS fAILING AND SEVERAL SETS Of UATA
REMAIN TO BE US~O IN THAT SUBTEST. THIS
COMMAr~D ENA~LES THE USER TO EXIT A FA!LING
DATA SUBTEST AND CONTINUE WITH THE NEXT SU8TEST.
ArTER THE CURRENT "EX~" COMMAND ~AS BEEN
UTI~I~EO fOR A fAILING DATA SU8TEST EXIT, IT
IS NO LONGER EFFECTIVE. IF NO TESTS ARE
SE~ECTEO, MONITOR WILL P~INT "7".
IN THIS
CAS~ A NEW TEST SELECTION MUST BE MAD~,

MINI SCoPE LOOP. THIS COMMAND SHOULD BE USED
WHEN AN ERROR HAS OCCURRED IN ~ ~U~TEST
WHICH TESTS TIME SEQUENCED OPERATIONS. "NN"
IS THE BIT NUMBER (I~ OCTAL) IN THE EHROR
STATUS W~RO (E:RSTAT) WHICH INDICATES A FAILURE.
SR5 MUST BE SET TO A 1 TO UTILI~E THIS ~EATURl
COR~ECT~V,
REFER TO PARAGRAPH 8 rOH MORE
ON~y

I r~ F" aR~1 A T ION •

B-9

Part I

7.1.3

(PAGE 7)
TEST INTERRU'T COMMANDS

.---------------------T'~E rOLLOWING
qETU~~ TO THE

COMMA~DS MAY BE USED
P~OGRAM MONITOR.

TO INTERRUP1 TESTING A~O

IN MOST CASES, ALL TE~T

SEL.ECTIO'!S WILL BE: DEL.ETED AND THE USER MUST RESELCCT
T4E TESTS TO BE EXECUTED. TWE MOST COMMON USES or THESE COMMANDS ARE TO REWI~O THE SELlCTEO DRIVE, AND TO lXIT A MINI
SCOPE LOOP •

.. --- .. ALT"1QOE KEY

INTERRUPT TEST EXECUTION.
A:-.JD "ESC" I(EYS.

RESPONDS TO "ALT"

I~TERRUPT TEST EXECUTION, DELETE 4LL TEST SEL.ECTIONS, AND REWIND THE SELECTED DRIVE TO
BOT.

TEST EXECUTION, DELETE ALL rEST SELECTIONS,
FORCE A DUMP or ALL TM8-E REGISTERS ON
THE TTY. (THE REGISTER ~UMP rORMAT IS A
MODIFIED ERROR REPORT rOR~AT.)
I~TERHUPT

A~D

7.1.4

MI SCrLLA'JEOUS CO~MANDS

---- ..

--------~-------

COMMA~D

.--.---

RESULT
I~ITIAL.l!E

AND ALLOW NEW ORIVE SELECTION.

T~ACE THE PROGRAM FLoW USING THE ERROR REPORT rOR~AT (MODIFIED), THIS COMMA~D IS A PRErIX TO ALL "TEST SELECTION" AND "TE~T CONTINUATION"
COMMA~DS, AND RESULTS
l~ A MODIFIED ERROR REPORT rOR EACH SUBTEST
T4AT PASSES. TRACE REPORTS ARE CONTROLLED
VIA SR BITS 3 AND 4 IN T~E SAME MANNEH AS ERROR
REPORTS. "TR" REMAINS IN EFFECT UNTIL THE
~EXT ENT~Y TO THE PROGRAM MONITOR.

DUMP T~E CONTENTS or MEMORY LOCATION NNN~ IN
FIE~D ~ ON THE TTY.
LINE-rEED DUMPS TM~ CONTeNTS O~ T~E NEXT LOCATION, CARRIAGL RETURN
RETURNS TO THE PROGRAM ~ONITOR. TEST SELECTION IS UNMr~ECTED.

B-IO

Part I

1.2

SWITC~

(PAGE 8)
REGISTER CONTROl OPTIONS

.---~.-----.-----~---.-.------.

SR BIT
-~

..-- ..
... -. STATE
1

rUNCTION
RUN ALL TESTS NORMALLY (SEVERAL PASSES Or
EACH SE~ECTEO TEST EXCEPT TEST 3~).
QUICK VERIry (ONE PASS IS MADE or EACH SELECTED TEST).
E~ABLE

TEST IN PROGRESS REPORTS.

AS SOON AS

A TEST IS STARTED THE TEST NUMBER (TESTNN)

2
1

IS PRINTED ON THE TTY.
DISABLE TEST IN PROGR~SS REPORTS.

RETURN TO PROGRAM MONITOR ON ANY ERHOH
OCCURRENCE.
RETURN TO PROG~AM ~ONITOq ONLY Ir A rATAL
ERROR HAS OCCURRED.

E~ABLE

DISABLE

5
1

ERROR AND TRACE REPORTS,

ERROR AND TRACE REPORTS INCLUDE APPLICABLE
DATA ONL.y,
rOReE ERROR AND TRACE RE~ORTS TO INCLUDE ALL
POSSIBLE DATA,
DISABLE SUBTEST LOO~.
LOOP ON CURRENT 5UBT[ST, ALL VA~IA~L~ UATA
REMAI~S CONSfANT.
THIS SWITCH MUST ALSU BE
SET TO ENTER A "MINI SCOPE LOOP".
LOOPS 6-9 RESPECTIVELY.
LOOPS 6·9 RESPECT I VELy. LOOPS 6-9 ALLOW
USER TO LOOP ON A S~ALL GROU~ Or SUB~
TESTS WITHIN THE CURRENT TEST THERE~y ENABLING
I ~ICREAS I NG THE TEST PJG F'REOUENCY Or A SMALL SET OF'
FUNCTIONS, THE ~ISTING MUST BE REFERENCED
TO DETERMINE WHICH SUBTESTS ARE INCLUUED IN
EACH LOOP, THE END Or EACH LOOP IS M~RKED AS
" ••••• LOOP N•••• *".
I~HIBIT

E~JA~LE
T~E

o
1

11
1

I~H18IT LOOP ON CURRE~T TEST (TEST 15 - TEST 3~),
ENABLE: 1.00 P ON CUr:tRE~Ji TEST.

TERMINATE TESTING UPON COMPLETIO~ OF ALL
SELECTED TESTS AND DEI.ETE TEST SeLECTION.
RUN ALL SELECTED TESTS CONTINUOUSLy. AT
T4E COMPLETION OF' EAC~ PASS THROUGH THE E~ ..
TIRE TEST SELECTION, THE NUMBER or PASSES EXeCUTED (IN OCTA~) IS PRINTEO (PASS ~NNN).

Part I

(PAGE 9)
8.

ERRORS

.---- ..

B.l ERROR ~AL T5

.---------- ..

THERE ARE NO ERROR HALTS IN THIS PROGRAM. Ir AN ERROR SHOULD
A~O SR2=0, THE PROGRAM WILL STOP TESTING AND ~E(URN TO
THE P~OGRA~ MONITOR TO AWAIT A USER COMMAND. RErER TO PARAGRAPH
fOR AVAILABLE COMMANDS.

OCCUR

'.1

B-12

Part I

(PAGE 10)

8.2

rRROR REPORTS

.---- .. ---_ .. -WHEN SR4.~, ERROR REPORTS

INC~UOE ONLY T~AT INrORMATION
APPLIES DI~EC'LY TO THE ERROR, Ir SR4=1, A~L POSS1BLE
INrORMATION IS PRINTED WHETHER APPLICAB~E OR NOT, AN EXA~PLE or A MAXIMUM INFORMATION ERROR REPORT IS SHOWN BELOW.

W~ICH

-ER15D

PC:025~

WCf1234 CA:2343

11:6706 1216716
rSl0000

CM:~0~0

GO:~000 BO:7777 00:77/7
MS:000~ DB:~~0~ AC:00~a

THE SYMBOLS USED IN THE ERROR REPORTS ARE OEFINED BELOW.
SYMBOL

.----.

DEPI~ITION
~~-~-~----

.ERNNX

E:RROR OCCURRED IN TEST N~J, SUBTEST X. (IF' NN=31, THE
ERROR OCCURRED OUTSIDE OF A rORMAL TEST.)

.rENNX

fATAL ERROR

TR*NNX

TRACE REPORT INDICATOR, NO ERROR OCCURREO Bur TRACE
IS ENABLED OR THE "'C" COMMANO WAS TYPED BY THE USER.

PCINNNN ADDRESS

PROGRAM AT WHICH ERROR WAS DETECfEU,

111NNNN OCTAL CODe: FOR lOTi IN A VARIABLE SUBTEST.
I2INN'JN OCTAL CODE fOR 10T2 IN A VARIABLE SUliTEST,

THE FOLLOWING THREE SYMBOLS ARE FURTHER OEF"INED IN TH£ PROLISTING IN THE SUeTEST COMM[~TS.

~RAM

GO : NN~-JN GOOD TEST VALUE:
BD'N~NN REA~

TEST VALUE (8AO)

OO,NNNN PREVIOUS GOOD TEST VALUE (OLD)

THE rOLLOWING SYMeO~S INOICATE THE CONTENTS or THE SPEClrIED
REGISTER AT THE TIME THE ERROR WAS OETECTED.
WCtNNNN WORD COUNT REGISTER
CA:NNNN CURRENT ADORESS REGISTER
CMINNNN COMMAND REGISTER

rSaNNNN rUNCTION/STATUS REGISTER
MSINNNN ~AIN STATUS REGISTER

nB1NNNN DATA BUFFER REGISTER
ACINNNN PROCESSOR ACCUMULATOR
ERRORS.)
B-13

(VA~10

ONLY rOR ILLEGAL SKIP

Part I

B.3

(PAGE 11)
STANDARD ERROR RECOVERY PROCEDURE
---------~----~---~-----------.--

THt STANDARO ERROR RECOVERY PROCEDURE ASSUMES THAT TH( STA~DARO
TEST PROCEDURE IS BEING US~DJ THAT IS, T~AT ALL ERROR OCCURRENCES
~ESUL T I J AN ERROR REPORT AND IN A RETURN TO THE PROGHAM
~ONITOR.

WHEN AN rRROR OCCURS, USE THE fOLLOWING STEPS AS A GU!OE rOR
REFERRING TO ~ARAGRAPH 8.2 rOR £RROR REPORT SyMBOL
OEF"INITIONS.
PECOV~Ry

~Er£RENCE

THE POI~T IN
THE "PC:" NUMBER.

T~E

PROGRAM ~ISTING INOICATEU BY

THE ERROR CODC IN THE LlSTING SHOULD MATCH THE (;OUE IN THE
REPORT (ERNNx OR FENNx).

[~ROR

~OMMENTED

IMMEDiATELY BELOW THE ERROR CODE IN THE LISTIS AN EXPLANATION OF THE NUMBERS PRINTED ArTEH THE
GO, BD ANO 00 SYMSOLS.
I~G

IN T~E IMMEDIATE VICINITY or THE ERROR CODE AND RELATED
SUBTEST A DESCRIPTION or THE SUBTEST WILL BE rOUNU.

I F" T:~e: SVMBOLS "GO" AND "BD'· ARE OEr I NED AS THE GUOD AND
REA~ (BAD) VALUES OF ERSTAT (ERROR STATUS WORD), rHAT SUB-

TEST TESTS TIME SEQUENCED OPERATIONS.
IN THIS CASE, ANY
gITS W~lC" DlrrER BETWEEN GO AND BD INDtCAT~ ~HICH TIME
sraUENCED OPERATION(S) FAILED. THE TIME SEQUENCEU uP·
lqATIONS ARE COMMENTED WITH THE 8IT POSITION TO WHICH THEY
~ORRESPOND ANJ EXACT~Y WHAT IS BEING TESTED AT THAT TIME.

I r THE ERROR IS rATAL (FENNX), THERE IS NO STANUAHO REw
COVE~Y.
THE CAUSE Or THE rAl~URE MUST BE DETERMINED
T~POtJGH STATIC MEANS.

Ir T~E ERROR IS NON-rATAL (ERNNX), T~E USER MAY E~ECT TO
CONTINUE IN T4E TEST SEQUENCE (C.), OR TO ENTER A SUBT(ST OR MINI scoPt ~OOP AS DESCRIBED BELOW.

I~ t

I F' Ti~E FA I LING SUBTEST DOES NOT
ATIO~S, ENTER A SUBTEST LOOP AS

TEST TIME SEQUENCEO OPERDESCRIBED IN &.3.1 BELOW.

Ir THE "-AILING SUBTEST OOES TEST TIME SEQUENCED OPEHATIONS,
AS DESCRIBEO IN 8.3.1
IN 8.3.2.

T~E USER MAY eNTER A SUBTEST ~OOP
o~ A Ml~I SCOPE LOOP AS DESCRIBED

B-14

Part I
(~AGE

8.3.1

12)

SUBTEST LOOPS
.. ..

.. --- -- ---TO ENTER A SUBTESi ~OOP, CARRY OUT THE rOLLOWING STEPS.
A.

SET SR BITS 2, 3 AND '·1.

R•

TVPEl' C....

iO EXIT A SU8TEST LOOP, RESTORE THE SWITCHeS TO THEIR NORMAL
POSITION.

8.3.2

MINI SCOPE ~OOPS

.- ..

--.~--

NO~E:

.. --- .. --

MINI SCOPE LOOPS WILL WORK ONLY ~OR SUBTESTS wHICH
TEST TIME SEQUENCED O~ERATIONS.

TO ENTER A MINI SCOPE LOOP, CARRY OUT THE FOLLOWING ST£~S.
A.

SET SR BITS 2, J AND 5-1.

TYPE "SNN~" WHERE NN 15 THE BIT NUMBER (IN OCTAL) OF THE
FIRST fAILING TIME SEQUENCED OPERATION. THE PROGRAM
WILL LOOP CONTINUOUSLY FROM THE LAST "SET" COMMANU
THROUG~ THE TIME SEQUENCED OPERATION TEST SPECIfIED IN
"SNN"". A "CLEAR TRANSPORT~ (eLT) IS ISSUED ArTEH THE
COMPLETION or EACH ~OOP.

TO EXIT A MINI SCOPE LOOP, TYPE "tR" WHICH WILL INTERHUPT THE
LOOP, DELETE ALL TEST SELECTIONS, REwIND THE SELECTED
nRIVE, A'ID RETUR~ TO THE PROGRAM MONITOR.

B-15

Part I

(PAGE 13)
Q.

RESTRICTtONS
-~---

.. ------

ONE DRIVE MAV BE TESTED AT ONE TIME.
ALL. Cl THE Q DRI VES 11 UST BE 0F' F" LIN E •

O~lV

lkL EXECU'!'I011 TIME
---------_ ... --EXECUTIO~ TIME VAqIES OE~ENOENT UPON THE TYPE Of ORIVE ~EING
TESTED. ONE LONG PASS OF' A rUl.L TEST SELECTION FOR A Y TRACK
nQIVE TAKES APPROXIMATE~V 15 MINUTES.
11..

TEST ABSTRACTS

.- .. --.. ------ ..

TEST 15 C~ECKS BASIC TMS-E CONTRO~ rUNCTIONS THAT DO
REQUIRE A DRIVE TO BE ON l.INE. NO TAPE MOTION, HOWEVER, IS
1!\.JITIATEO,
TEST 16 CHECKS TI~E SEQUENCED CONDITIONS INCLUDING TA~E
~OTION rOR WRITE. READ, READ-COMPARE, SPACE rORWARD, SPACE
REVERSE AND REWIND fUNCTIONS. ALL OPERATIONS ARE OUN~ AT
800 BPI ~ITH 9 TRACK DRIVES IN CORE DUMP MODE.
TEST 17 VERIPIES THAT RECORDS WRITTEN IN ONE PAHtTY MODE, THEN
READ IN THE OTHER MODE CAUSE LATERAL (VERTICAL) PARITY ERRORS.
TEST 20 VERIfIES THE ABILITY or THE DRIVE TO WRITE A FI~E
AND ALSO THE ABILITV TO RECOGNI~E A rILE HARK.

~ARK

TEST 21 EXERCISES VAkl0US COMBINATIONS Or WRITE,
A~O SPACE REVERSE.

B-16

WRIT~

rILE MARK

Part I

(JiAGE: 14)

TEST 22 CONTINUES VARIOUS 'OSITIVE AND NEGATIVE TESTING SEQUENCES
O~ TH£ TMa·E CONTROL UTILIllNG TAPE MOTION.
TEST 23 VERIrIES T~E P~OPER OPERATION OF THE CONTINUOUS MODE or
SINGLE DRIVE OPERATION UTILllING VARIOUS COMBINATIONS Of DRIVE
rUNCTIONS.
TEST 24 TESTS THE CHANGE DIRECTION MODE or OPERATION UTILlilNG
VARIOUS COMBINATIONS or rUNCTIONS WHICH CAUSE DIRECTION RE.
VERSAL.
TEST 25 15 A BASIC TEST or THE ABILITY or THE TMS-E/TSI3 TO PASS DATA
CORRECTLy.
TEST 26 VERlrIES THE PROPtR GENERATION or THE CYCLIC HEuUNOANCv CHECK CHARACTER (CRCC) By COMPARING SIMULATED VALUES
TO THOSE VALUES GENERATED BY THE HARDWARE AND WRITTEN ON TAPE.
THIS TEST IS RUN ON 9 TRACK DRIVES ONLY.
TEST 27 OOES NOT APPLY TO THE TS~3 •••••
TEST 3B IS A MANUAL INTE~VENTION TEST W~ICH TESTS SUCH THI~GS
4S fIL£ PROTECT. THE Off LINE fUNCTION A~D THE PROPlR EffECT O~ THE CONTROL BY THE PROCESSOR "I~ITIALIlE" SIGNAL.
12.

LISTING

... _....

(ATTAC~ED)

B-17

Part I

APPENDIX C
TM8-E/TS03 DATA RELIABILITY, 9-TRACK

IDENTIrIC~TIO"

••••••••••••••
PRODUCT CODEI

MAINDEC·~R·DHTSC·~·D

PRODUCT NAME.

T~A·E/TS0l

CREATEDI

15 JUNE 75

DAT~

DATA RILIAiILITY 9 T~ACK

MAtNT~INE~1

nIAGNOSTIC GPOUP

AUTHOP:

R. 8, BARNES

THE INFORMATION IN THIS DOCUMENT IS SUIJECT TO
CHA~~E wITHOUT NOTICE AND SHOULD NOT eE ~ONSTRUEO
AS A COMMITM[NT BY DIGITAL FQUIPMENT CORPO~ATION.
DIGIIAL E~UIPMENT CO~POPATION ASSUMES NO
RESPONSI8ILITY F'OP ANY ERPORS THAT MAY APPEAR IN
THIS ,..ANUAL.
THE 50FTWA~E DESC~I~ED IN THIS DOCUMENT IS
fURNISH€U TO TH~ PURCHASER UNDEP LICENSE fOR USE
ON A SINGLE COMPUTER SYSTEM, AND CAN ~E COPIED
(wITH INCLUSION Of DIGITAL·S COPY~IGHT NOTICE)
ONLY rOR USE IN SUCH SYSTtM, EXCEPT 4S HAY
OTHf.PWISE BE P~OVIUf.D IN wPITING BY DIGITAL,
DIGITAL EQUIPMENT CORPORATION ASSUMES NO
R~SPONSIBILITY FO~ THE US' OP ~ELIABILITY OF ITS
SOrTwA~~ ON EQUIPME~T THAT IS NOT SUPPLltD dY
DIGITAL,
COPY~IGHT

ee) 1975, ~Y DIGITAL EQUIPMENT COAPt' MAYNARD, MA,

C-l

hnl

NOTE
....

A~[ rlVt DlAGNOSTIC P~OG~AMS ASSOCIATED WITH TH! TMB-! DEC~AGTAPE
ONTROL AND ITS tRA~SPORT SYSTEM, ALTHOUGH PHY~ICALLY SEPA~ATE, THESE
pROG~AMS MUST 8t TREATED AS A LAMGE INTEG~ATED TEST,
AND TO ENSU~E PROPER
SYSTE~ ~PlRATION, THESE TESTS MUST BE EXECUTED I~ THE O~D[R DELINEATED BELOW,
~Hr~f.

Ir A G1V[N TEST SHOULD fAlL AND IT APPEARS THAT A rIX HAS BEEN rOUND,
ALL pPOG~AMS ~UST ONCE AGAIN BE RUN. ONLY WHEN ALL TESTS HAVE RUN WITHOUT
ANY UN ACClPTA8Ll E~RORS CAN THE TM8-E SYSTEM BE CONSIDERED UP,

TMg-L DIAGNOSTIC PROGRAMS' ORDER or EXECUTION
................•....•••..........•.......•..
1.

TM8·~/rS01

CONT~OL

TEST PART 1

(MAINDEC-,e-DHTSA)

TM8·E/TS~1

CONTPOL TEST PART 2

(MAINDEC-,a-DHTSB)

TM8-~/TS03

DRIVE fUNCTION TIMER

(MAINDEC-'I-DHTSE)

T~8·E/T5~)

DATA RELIABILITY 9 TRACK

TM8-!/T50) MULTIDRIVE DATA EXERCIS!P

C-2

(~AIND!C-".DHTSC1
(~AIND!C-ll-DHTSD)

rOR 4~ SYSTEMa
rOR IK AND LARGER

Part I

.......•.. -----_.

TABLE OF CONTENTS

ABST~ACT·
~E:QUlREMENTS
HA~DWARE

MEMO~Y
P~ELIMINARY

PROG~~MI

PPOG~AM

LOADING PPOC!DURE

P~OGRAM

STARTING PROCEDURE

STANDARD TEST PPOCEDU~E
DPIVr; SELECTION
T~ST SELECTION
TEST SEQUENCE SELECTION TABLE (TST)
DATA PATT~~N SEL~CTION TABLE (PAT)
PA~ITY SELECTION (PAR)

5,1
5.2
5.2.1

5,2.2
5.2,3
5.2,4
S.2.S

DENSITY SEL~CTIO~ (DEN)
~ECORD LENGTH SEQUENCE SELECTION CRt!)

STOP MODE SEL,.CTION (W~O'
STOP MODE SELECTION (~MO)

5.2.b
5.2. 7

W~lr~
~EAD

SWITCH REGIST~~ CONTROLS

~~ROR RI:PORTS
ACCUMULATED WRITE E~~ORS REPO~T
WRITi STATUS ERROR ~EPORT
ACCUMULATED READ FPRORS REPORT
READ STATUS ERROR PFPORT

7.1
7.2

7.3
7.4

~EST~ICTIONS

P~OG~AM

DESCRIPTION

LISTING

C-3

Part I

(PAGE 1)
WA~NINGI

ANY
T~E

P~OG~A~ INTE~RUPT THAT OCCURS 7ROM A DEVICE OTHEP THAN
TM8.E IS A fATAL [PROP AND WILL RESULT IN A PROGRAM HALT.

A8STF<ACT

==: •••••
THE TMe·E DATA RELIABILITY TEST (9 TRACK) IS PPIMARILY DEfOR THE COLLECTION OF STATISTICAL INfO~MATION PERTAINING
TO TH~ DATA ~ELIABILITY or THE 9 TRACK TAPE DRIVES ASSOCIATED
~ITH THE TM8.f DECMAGTAPE CONTROL,
THE PROGRAM IS ALSO DESTGN~D TO BE USEABLF AS AN AID IN THE CHEC~OUT AND MAINTENANCE
or lHf TM8-~ AND ASSOCIATED 9 TRACK DRIVES,
8IGN~D

THIS PROGRAM ~AY ALSO 8E USED AS AN EXTENDED DATA RELIABILITY
ACCEPTANCE TEST YO~ 9 TRACK ORIVES,
ALL TAPE OPERATIONS ARE DONE IN 9 TRACK COMPATIBLE MODE,
CORE nUMP MODE IS NOT UTILIZED,

.,.

~~QUIREMENTS

••••••••••••
2.1

HARDWARE

••••••••

PDP·S/E, 81M, 8/f
OR COMPATIBLE DEVICE (TTY)
T~8-f DEC MAGTAPE CONTROL
TS~3 MASTER/SLAVE !PANSPO~T SYSTEM WITH fROM ONE TO EIGHT
9 TPACK DRIVES,
T~LETYPE

,,2

MEMOPY
••••••
THIS PROGPAM REQUIRES 4K or MEMORY lND MAY RESIDE IN ANY MEM.
fIELD.

O~'i

,,1

PPELIMINARY
...••.•....
....... PROGRA~S

ALL PROCESSOR/MEMOPY DIAGNOSTICS
TMS·E CONTROL T~ST PART 1
TMS.E CONTROL TEST PART 2
T~8·E DRIVE FUNCTION TIMER

C-4

Part I

(PAGE 2)

........•.......•. .....

1, PPOGJ:(AM LOADl~G PPOCEDURE
~-

LOAD THE
~fANDARD

PROGRAM STARTING PPOCEOURE
••••••••••••••••••••••••••

LOAD ADDRESS ~2~0.

LOAD THE EXTENDED ADDRESS WITH TH! '~OG~AM FIELD.

CLEAP ALL SWITCHES.

THE PROGRA~ ~ILL P~INT ITS TITLE A"D MAINDEC NUMBER, THEN
ASK FOR D~lVE SELECTION. PRIOR TO MAKING DRIVE SELECTION
GO TO T~E STANDA~O TEST PROCEDURE IN PARAGRAPH 5.

NOTE'

P~OGRAM INTO ANY DESI~ED MEMORY FIELD USING THE
BINARY LOADE~ TECHNIQUE.

ThE P~OGRAM MAY BE RESTARTED AT ANY TIME AT ADDRESS
0201. IN THIS CASE THE P~OGRAM ASKS IMMEDIATELY rOR
D~IVF SELECTION.

STANDARD TEST PROCEDURE
•••••••••••••••••••••••

USE OF THE STANDARD TEST PROCEDURE RESULTS IN EACH SELECTED
T~ST SEQUENCE RU~NING FPOM ijOT TO tOT.
NO REPORTS WILL OCCUR
WHEN NON.FATAL ER~ORS ARE DETECTED, HOWEVER, THESE E~RORS
~lLL BE ACCUMULATED AND ~EPO~TED AT THE END or EACH PASS or
TAPE. ANY VARIATIONS FROM THIS SCHEME A~E CONTROLLED THROUGH
THE SWITCH REGISTl~ OPTIONS AS LISTED IN PARAGRAPH 6.
ERRO~
REPO~T DESCRIPTIONS ANO PELATED INrO~MATION ARE GIVEN IN PARGRAPH 7.
5,1 DRIVE SELECTION

••••••••••••••••
ACCOMPLIS~ THE FOLLO~ING STEPS
r~ACK DRIVES TO BE TESTED.

TO SETUP AND SELECT THOSE 9

PLACE A SPARE REEL OF lNDUSTRY CO~PATIBL! MAGNETIC TAPE
WITH THE rILE PPOTECT RING IN PLACE (WPITE ENABLED) ON
EACH DRIVE TO BE TESTED,

LOAD THE TAP~ POSITION TO 80T AND SWITCH THE DRIVE ON LIN!.

STANT THE PROGRAM AS DESCRIBED IN PA~AGR1PH 4.

THE PROGRAM WILL EVENTUALLY PRINT "SELFCT DRIV!S".

TYPE THE DRIVE NUMBEPS OF THOSE 9 TRACK DRIVES TO BE
TESTED, TYPING THE SAME DRIVE NUMBER TWICE WILL DEL!T~
THAT DRIVE FROM THE SELECTION.

~HEN

ALL DRIVE NUMBEPS

H~VE

BEEN TYPED IN, TYPE CARRIAGE RETURN.
C-5

Part I
(PAGF. 3)

S.2

ItSl SELECTION
••••••••••••••
ACCOMPLISH THE FOLLO~ING STEPS TO SELECT THE DESIPEO TEST SEQUENCES.

A'TE~

D~IVE

SELECTION IS COMPLETE, THE PROGRAM wILL PRINTs

"TST PAT PAR DEN RLS WMO RHO"
8.

PESPOND BY TYPING THE DESIRED CODE FOR EACH OF THE PARAME.
TERS USING THE TABLE BELOW AND ~EFERENCING tHE INDICATED
PARAGRAPH.

•••••••••

DEY'IN ITION
••••••••••

TST

TE6T

PARAMETER

PAT
PAR
DEN
RLS
~MO
~~o

REFERENCE PARA.
•••••••••••••••

SEQUENCE
5.2.1
DATA PATTERN
5.2.2
PARITY
5.2.3
DENSITY
5.2.4
PECORD LENGTH
5.2.5
SEQUENCE
wPI'fE. STOP MODE 5.2.6
PEAD STOP MODE 5.2.7

AFTER ALL PA~AMETERS FOR A SPECIFIED TFST SEQUENCE HAVE
SEEN ENTER!D, TYPE A SPACE, IF THE SELECTION IS VALID,
TH~ P~OGRAM WILL PRINT "O.K.".

~EPEAT

wHEN ALL DESIRED TEST SE~UENCES HAVE BEEN SPECIfIED AND
HOeK," HAS BEEN PRINTED BY THE PROGRAM rOP EACH SET OF TEST
SEQUENCE PARA~ETERS, TYPE CA~PIAGE RFTUPN.

THE PROGRAM ~ILL NOW STA~T EXECUTING T~E SELECTED TEST
SEQUENCES ON THE D~IV[S UNDE~ TEST.

AS EACH TEST SEQUENCE IS COMPLETED ON EACH DRIVE, THE
ACCUMULATED ERRORS DETECT~D WILL BE ~EPORTED. REFERENCE
PARAG~APH 7 ro~ DETAILS.

STEPS 8 AND C FOR ALL DESIRED TEST SEQUENCES.

C-6

Part I

(PAGE 4)

•.....•........ -............. -.... .

5,2,1 TEST SEQUENCE SELECTION TABLE (TST)

THE FIRST SELECTIO~ M~OE IS "TST"
TYPE IN THE NUMA~R OF THE TEST OESIPED.
TEST
NUMBER

DESC~IPtlON

••••••

• ••••••••••

~RITE
RO~S,

Ie EOT ON ONE DPIVE, TYPE ACCUMULATED WRIT! ERCHANGE DRIVES.

WRITE ONE ~ECORD LENGTH SEQUENCE OP 256 RECORDS, CHANGE
DRIVES, AS EACH DRIVE PEACHES EOT TYPE ACCUMULATED
WRITE ERRORS.

WR1TE ONE RECORD, CHANG! DRIVES, AS EACH DRIVE ~!ACHES
EOT TYPE ACCUMULATED WRITE ERPORS.

WRITE TO EOT, TYPE ACCUMULATED WRITE ERROPS, REWIND,
CHANGE ORIVES, READ TO EOT, TYPE ACCUMULATED PEAD
E~RORS, C~ANGE DRIVES,

WRITE ON~ PECORD LENGTH SEQUENCE, BACKSPACE, ~EAD, CHANGE
DRIVES AS EACH DRIVE REACHES Eor TYPE ACCUMULATED WRITE
AND ~EAD ERPOP INFORMATION,

WRITE ON~ ~ECORD, BACKSPACE, READ, CHANGE DRIVES.
AS EACH DFIVE REACHES
EOT TYPE OUT ACCUMULATED ERRO~ INfORMATION,

WRITE ONE ~ECO~D LENGTH SEQUENCE OR 256 RECO~DS, CHANGE
DRIVES, BACKSPACE, CHANGE O~IVES, READ, CHANGE DRIVES.
AS EACH DRIVE ~EACHES EOT TYPE ACCUMULAT~D E~~O~ IN.
fORMAT10N.

WRITE ONE ~ECO~D, CHANGE D~IVES, BACKSPACE, CHANG!
DPIVES, ~~AD, CHANGE DRIVES, AS EACH D~IV£ ~EACHES
lOT TYP~ ACCUMULATED ER~OR INFORMATION.

lEST 8 RUNS DIFFERENTLY DEPENDING ON THE WMO AND RMO
IF 80TH ARE SELECTED 0 (NONSTOP), EACH
WRITE ANO READ PASS WILL BE MADE TO THE END OF A RECORD
LENGTH SEQUENCE BEFORE CHANGING DRIVES. Ir EITHER
SELECTION IS START/STOP (1) OR RANDOM (2) THAT PASS
~ILL BE MADE WITij DRIVE CHANGE BETwEEN EACH RECORD.
(I.E., WMO:0 AND RMO~1, THE WRITE PASS IS ~ADE NONSTOP
ON EACH DRIVE TO E~D OF RLS, THE READ PASS IS MADE
START STOP WITH A DRIVE CHANGE BETwEEN EACH RECORD'.
S~LECTION.

C-7

Part I

(PAGE 5)

TEST 9 IS A READ ONLY TEST THAT MAY BE USED TO T!ST
DRIVl COMPATABILIT~ OR MULTIPLE PEAD PASSES OVER
DATA PREVIOUSLY WRITTEN. EITHER PATTEPN 1 (RANDOM
DAlA) IS NOT A VALIry SELECTION rop TEST 9 EXCEPT WITH
C[RTAIN PESTPICTIONS.
A.

TEST 9 SELECTION FOLLOWS TEST 3.

TEST q SELECTION FOLLOWS TEST 6 WITH SR0-1

TEST 9 SELECTION FOLLOWS TEST 8 WITH SF0c1

TEST 9 SELECTION FOLLOWS TEST S WITH SR0-t
ANO ONLY A SINGLE DRIVE WAS SELECTED,

DATA PATTE~N SELECTION TABLE (PAT)
••••••••••••••••••••••••••••••••••

tHE SECOND SELECTION IS "PAT".
TYPE IN THE NUMBE~ 0' THE DATA PATTE~N DESIRED, US! T~BLE
"A" IF PA~lTY SELECTION WILL 8E EVEN, TABLE "8" IF PARITY WILL
BE ODD.
A.

~VEN

PARITY DATA PATTERNS

•••••••••••••••••••••••••
PAT

•••

DESCRIPTION

DATA
••••

• ••••••••••
HIGH rREQUENCY OUTSIDE SKEW

SLIDING NO BIT (0)
CHARACTER PATTERN

0377
0177
0277
0337
V'357
V'367

0373

0375
0376

0103

HIGH FREQUENCY EVERY OTHER TRACK

0273

HAL' FPECUENCY OUTSIDE TRACKS
HIGH FREQUENCY ALL INSIDE
TRlCKS

0001

INCREMENTING CHARACTER PATTERN
NO 00 CODES

0002
0003

0004
C-8

Part I

(PAGE 6)
5

037'7
~177

THREE 0 HITS EACH TRACK
EVEP'X 7TH wORD

~211

0337
~157

0367
~373

0375
0376
6

0377

ALL l'S ALL TPACKS

RANDOM

RANOOM DATA PATTE~N WITH NO 00
CODES

OUO PARITY DATA PATTERNS
••••••••••••••••••••••••

PAT

DAT~

DESCRIPTION

•••

••••

• ••••••••••

0004

HALF FREQUENCY OUTSIDE
SKEW

e,000

SLIDING 1 ~IT CHAR.
ACTER PATTlRN (ISO·
LATED BIT)

~20~

0100

0"'40
0~20

'-"~10
0~04

e"'ftA2
0001

0274

HIGH FREQUENCY EVERY OTHER TRACK

003'7

THREE 0'S, THREE 1'5, THREE 0'S,
THREE 2-5, SIX 0'5 EVERY TRACK

0k176
0201
01'74

0003
037~

"'007
0360

e-9

Part I

(PAGE 1)
4

0"'(01

INCREMENTING CHARACTEP PATTERN

"'~02

00 CODES INCLUDED

0003
~~04
0~00

0200
0100

EACH TRACK 3 BITS EVERY
SEVENTH ~OPD

~~40

0~20

0010

0004
0002
0~01

~l7'7

ALL ONES HIGH F~EQUENCY AL~ TRA:KS

f<)~OOM

RANOOM DATA WOPO PATTERN 00 CODES
INCLUDED

PARITY SELECTION (PAR)
••••••••••••••••••••••

THE THIRD SELECTION IS "PAR"
SPEClFY PARIT~ BY TYPING THE DESIRED CODE AS DESCRIBED BELOW.
CODE
••••

P~RITY

EVEN
ODD

• •••••

DENSITY SELECTION (DEN)
•••••••••••••••••••••••

AFTER PARITY HAS BEEN SELECTED, 800 BPI WILL AUTOMATICALLY
BE SELECTED ANO PRINTED BY THE PROGPAM.

C-10

fun!

(PAGE 9)
5.2.; R~CO~D LENGTH SEQUENCE SELECTION (PLS)
••••••••••••••••••••••••••••••••••••••
AfTEF THE DENSITY SELECTION SPECIFY THE DESIRED RFCO~D LENGTH
SEQUENCE SELECTION (RLS) BY TYPING TH£ DESIRED CODE AS DEfINED
8~LOw,

COOF
••••

PECORD LENGTH SEQUENCE
••••••••••••••••••••••

ALL RECORDS ARE 24 WORDS (24 CHARACTERS)
ALL RECORDS ARi 4008 WORDS (4008 CHARACTERS)
RECORDS PROG~ESS YROM 24 WORD. TO 4008 WORDS
(~I~ TO MAX)
RECOROS PROGAESS FROM 4~0a WORDS TO 24 WORDS
(MAX TO MIN)

2
3

5.2.6 WPITE STOP MODE SELECTION eWMO)

••••••••••••••••••••••••••••••••
ArTER THE RECORD LENGTH SEQUENCE SELECTION, SPECIFY THE Ap.
PPOPRIAT~ CODE fOR THE DESIRED WRITE STOP MODE (WMO),
CODE
••••

WPITE STOP MODE
•••••••••••••••

NONSTOP,THE NEXT WRITI OFEPATION IS
INITIATED WITHOUT WAITING YOM TAPE UNIT READY,
ST~RT/5TOP.
ALL WRITE OPEPATIONS ARE INITI.
ATED AFTER TAPE UNIT READY.
RANDOM, COMBINED NONSTOP, START/STOP AND
~ANDOM STALL OPE~ATIONS.

2
~.2.7

READ STOP MODE SELECTION eRMO)
••••••••••••••••••••••••••••••
AFTEP WRITE STOP MODi SELECTION, SPECIFY THE APPROPRIATE CODE
rOH tHE OESI~ED ~EAD STOP MODE (~MO),
CODE
••••

RlAD STOP MODE
• •••••••••••••

NONSTOP. THE NEXT READ·COMPARE OPERATION IS
INITIATED WITHOUT WAITI~G ro~ TAPE UNIT READY,
START/STOP, ALL ~EAD.COMPARE OPE~ATIONS AR~
INITIATEO AFTER TAPE UNIT PEADY.
~ANDOM,
COMBINED NONSTOP, START/STOP AND RANDOM
STALL FEAO.COMPAPE OPERATIONS.

C-ll

Part I

(PAGE 9)

6. SwvITCH REGISTER CONT~OLS
••••••••••••••••••••••••
THE rOLLO~ING TABLE INDICATES THE CONTROL THE SWITCH REGISTER
HAS OVER P~OGPAM OPERATION wHEN A P~PTICULAR SP bIT IS SET TO
THE "1" STATE.
SR SIT
.......

.fUNCTION
........
DUMP EPROR COUNTERS AND PROCEED TO NEXT
TE~T SEQUENCE AT THE END Of ONE RECORD LENGTH
SEQUENCE. (256 RECORDS FO~ RLSa0 OR 1, ONE
MIN TO MAX SEQUENCE rOR RLS-2, OR ONE MAX TO
MIN SEQUENCE FOR RLS=l.)

DELETE WRITE WITH EXTENDED INTERRECORD GAP,
USE OF THIS SwITCH WILL CADSE RECORDS WITH
~PITE ERRORS TO BE LEFT ON TAPE,

PEPORT ALL wPITE ['~ROPS AS THEY OCCUR.

SELECT WPITE STATISTICAL RECOVERY, USE or
THIS SWITCH WILL SELECT THE BACKSPACE 2 RtCOPOS, SPACE fORWARD 1 R~CORO, REWRITE SEQUENCE. THIS SEQUE~CE CAUSES THE SAME RECORD
TO BE REWRITTEN ON APPROXIMATELY THE SAME AREA
or TAPE If A WRITE ERROR OCCU~S,

REPORT ALL READ·COMPA~E STATUS AND DATA ERRORS
AS THEY OCCUP,

DELETE READ PETRIES. THIS SWITCH IS AN AID
TO SCOPING PEAO CIRCUITS B~ DELETING THE BACKSPACE,
~EREAD TWICE SEQUENCE.

INCREMENT PATTERN SELECTION AND REPEAT LAST TEST SEQUENCE. PATTERN SELECTION IS PESlT TO ITS ORIGINAL
SELECTION AFTER PATTERN 7 HAS BEEN tXERCISED.

COMPLEMENT PARITY SELECTION AND ~EPEAT TEST
SEQUENCE IF NEW PARITY SELECTION IS DIFFERENT THAN
THE O~IGINAL TEST SEQUENCE.

C-12

Part I

(PAGE 10)
8

NO ,.UNCTION

INC~EMENT RLS SELECTION TO THE NEXT SEQUENCE. lfTER
MAX. TO MIN. HAS 8EEN EXE~CISEO RESET RLS SELECfION
TO ITS ORIGINAL TEST SEQUENCE SELECTION.
l~CREMENT ~MO TO TNE NEXT STOP HOOE.
AfTER RANDOM
START/STOP HAS BEEN EXERCISED, RESET WMO TO ITS ORIGINAL TEST SELECTION.

lNCREM[NT RHO TO THf NEXT READ 8TOP MODE. AfTER READ
START/STOP HAS BEE~ EXERCISED, RESET RHO TO ITS
ORIGINAL TEST SF.LECTION.

~ANDOM

REPORTS
•...•........

ER~OR

~ORMAL MODE (SR.~000) or OPERlTION fOR THIS TEST IS TO SI~PLY
ACCUMULATE THE ERRORS THAT OCCUR AND TO DUMP THE CONTENTS Of TH'
COUNTE~S ON TH~ TTY AS
EACH DRIVE PEACHES EDT. THE ONLY
~~ROR R~PORT
IHAT CAN OCCU~ IN THIS MODE IS If THE SYSTEM
fAILS TO WRITE THE SAME RECORD rou~ TIMES IN A ROW
wITH EXTLNOED INTERRECORO GAP,
T~E

SWITCH R~GISTER BITS 2 AND 4 ALTER THIS MODE Of ERROR REPORTING
BY 'ORCING REPORT5 YOR ALL ~RITE AND PEAD-CO~PARE ERRORS, RESPECTIVELY, AS THEY OCCUR,
7.1

ACCUMULATED
ERROPS REPORT
•...•......................
-- ...
~RITE

WHEN A WRITE OPERATION ENCOUNTEPS EOT, THE YOLLowING REPORT
15 PIHNTEO.

END OF TAPE
PAT PAR DEN MODE RECORDS LENGTH

O~V

8~0

SSTP

WRITE ERRO~S.00~9
kECOVEREO AT 1 0P.~2
R~COVER~U AT 2 0~~l
PtCOV~R~D AT 5 ~~01
PERMANENT bADSPT P0~l

02954 2016 MAX TO

WITH TH~ fOLLOwING DEfINITIONS.
SYMBOL

.- ....

DErI~ITION

DRV
PAT

D~lVE

......... .
NUMBER
SELECTED DATA

PATT~RN

C-13

~IN

Part I

(PAGE 11)
PAR

DEN
MODE
RE.CO~DS

LENGTH
wRITE ERRORS
J(ECOVERED AT N

SELFCTlD PARITY
SELECTED DENSITY
w~ITE STOP MODE
NUMBER OF ~ECOP05 WRITTEN
SELECTED RECORD LE~GT~ SEQUENCE
(2016 SHOWN IS AVERAGE LtNGtH)
TOTAL wRITE ERPORS
NU~~ER OF wRITE ERRORS RECOVERED ON THE NTH
RE\t4RITE

PERt-1ANE.NT 8ADSPT

NUMBER or WRITE ERRORS ~OT
PECOVERED AfTER 1 ~EwRITES

A SIMILAR REPORT WILL OCCUR WHEN THE END or A RECORD LENGTH
SEQU~NCE IS REACHED AND SR0=1.
HOWEVER "END or TAPE" IS REPLACED
BY "W~ITE DUMP".
7.2 WRITE STATUS ERROP REPORT

•••••••••••••••••••••••••
IF SR2-1 WHE~ A ~PITE ERROR IS DETECTED, THE FOLLOwING [RROR REPORT
wILL BE PRINTED.
WPITE STATUS ER~OP
rUNCTN STATUS WROCNT CUPADR RECORDS LENGTH
NNNN
NNNN
NNNN
NNNN
NNNN
NNNNN
NN~N

CO~O

WITH THE FOLLOWING DEfINITIONS,
SYMBOL

••••••
COMO

FUNCTN
STATUS
W~DC~T

CURAD~
R~CORDS
L~NGTH

DEfINITION
• •••••••••

COMMAND REGISTER
fUNCTION/STATUS REGISTER
MAIN STATUS REGISTER
WO~~ COUNT REGISTEP
CU~RENT ADDRESS ~EGISTER
RECO~D NUMBER
RECORD LENGTH

THE ABOVE REPORT WILL ALSO BE 'ORCED, REGARDLESS or SR SETTINGS,
IF A WRITE E~ROR PEPSISTS AFTER FOUR REW~ITES WITH EXTENDED
INTERRECOPD GAP. THE ~EPORT IS AMENDED WIT~I
"XRIG WRITTEN 4 TIMES".

C-14

Part I

(PAGE 12'
7,3

ACCUMULATED READ
••..•...•....••...•...........
E~PO~S

~HEN

RYPO~T

A R£AD.COMPA~E OPE~ATION ENCOUtlTER5 EOT, THE FOLLOWING REPORT 15 PRINT!~.

READ PASS
END or TAPt;
D~V PAT PAR Or.N MODE RECORDS LENGTH
1
7
1 800 N5TP 02954 2016 MAX TO MIN
READ ERRORSc0~10
NON RECOVERABLEa0002
DArA ERRORS-0001
DATA NO SfATUS-0001
~ITH

THE fOLLOwING DEFINITIONS (PErrR TO 7,1)'

......

DEfINITlON

~EAD

TOTAL ~UMBER or READ ERRORS INCLUDING EPRORS ON REREAD,
TOTAL NUMBER or NON RECOVERABLE PEAD ERRORS
(AfTER TwO REREADS)
TOTAL NUMBER 0' DATA (REAO-COMPARE) ERRORS
NOT INCLUDING REREADS,
TOTAL NUMB~R or DATA ER~ORS NOT INCLUDING
RE~EADS, wITHOUT ACCOMPANYING PAPITY E~ROR5 OR
OTH~R STATUS ERPOPS,
THIS TYPE Of ~RROR S~OULD
ALWAYS AE CONSID~RED NON RECOVERAHLE IN NATURE,

SY~SOL

ERRO~S

NON RECOVl~A.8LE

DATA ERROPS
DATA NO STATUS

......... .

A SIMILAR REPORT WILL OCCUR wHEN THE END Of A RECORD LENGTH SEQUENCE IS
REACHED AND SR0-1. ~OwEVER "END or TAPE" IS REPLACED BY "READ DU~P",
7.4

Rt;AD STATUS ERROR REPORT

........................
If SR4al WHEN A READ-COMPARE STATUS ERROR IS DETECTED, THE
fOLLOWING ERROR ~EPORT ~ILL BE PRINTED,

READ STATUS ERROP
COMO fUN~TN STATUS WROCNT CURADR RECOPDS LENGTH
NNNN
NNNN
NNNN
NNNN
NNNN NNNNN
NNNN
REfER TO 7.2 fOR
A.

SY~BOL

DEfINITIONS,

RESTPICTIONS
.........•..
If A~Y DEVICE OTHE~ THAN THE TMB-r CAUSES A PROGPA~ tNTE~RUPT,
THE PROG~AM ~ILL HALT, THE REASON ro~ THIS RESTRICTION IS
T~AT EXT~EMELY TIME CRITICAL OPERATIONS
AP[ SEING EXECUTED
IN THE BACKGPOUNO wHILE ~ECOROS ARE BEING WRITTEN AND REAOCOMPAPED, THE PROGPAM MUST CONSTANTLY ~ONITOR TH[ 1~8-~ CUPRENT
ADDRESS PEGISTER A5 DATA TPANSFEPS AR~ TA~ING PLACE,

C-JS

Part I

(PAGE 13)
9.

DESCRIPTION
•••••••••••••••••••

P~OGJ<A~

T~IS

AND

IS DESIGNED AROUND TWO MAIN SUBROUTINES AND A
SUBROUTINES fOR MANIPULATING ORIVE SELECTION
AND RECORD POSITION TABLES.

PROGRA~

b~~I~S

~R~OR

SHO~TER

THE TWO MAIN SU~ROUTINES APE THE WRITE AND READ.eOMPA~E ~OUTIN!S.
THE wPITE ROUTIN~ EXITS AfTEP EVERY RECOPD, EVEPY RECORD
L~NGT~ SEQU~NCE, OR AT END Or TAPE.
THE Y-EAD ROUTINE EXITS WHEN
lHE ~AST RECORD ~RITTEN ON TAPE HAS BEEN PFAD. SOME TESTS
MANIPULATE THE LAST RECORD COUNTEP SO THE PEAD POUTINE EXITS
AfTE~ ~VERY RECORD.
OTH~R SUbFOUTINES USED seT UP DRIVE SELECTION TO THE LOWEST
DRIVE NUM8E~, CHANGE DRIVE SELECTION TO TH~ NEXT HIGHEST DRIVE,
AND G[T AND SAVE FRPOP AND POSITION TABLES rOR TH[ DRIVE
CUR~~NTL~

SELECTED,

ALL THESE SUBROUTINES ARE TIED TOGETHER IN VARIOUS SEQUENCES
fOR ItST SELECTIONS 0 THROUGH 9.
ALL DATA IS CHECKED USING THE READ·COMPA~E FUNCTION, THE
READ fUNCTIO~ IS NEVE~ USED. BY USING THIS METHOD, RECORDS
A~E USED WHICH ARE MUCH LONGER THA~ COULD EVF.F
BE POSSIBLE
IN A 4K SYST~~ THAT ALSO CONTAINS THIS PPOGRA~, THE OVERALL
CONCEPT USED TO ALLO~ UTILIZING LONG RECORDS IN THIS PROGRAM
IS TO USE A RELATIVELY SHORT DATA BUfFER, THEN MONITO~ING
THE CURRENT AOO~ESS REGI5TE~, RESEt THE CU~RENT ADDRESS TO
T~E START OF THE BUfFER WH~N IT FEACHE5 THE END O~ THE BurrER.
THIS TECHNIOUE INVOLVfS TIM~ CRITICAL PROG~AM EXECUTION, HENCE
NO PRO~RA~ INTEP~UPTS ARE ALLOWED OTHER THAN THOSE CAUSED BY
IHt: IMS-E.
10.

..... . (ATTACHED

LISTING

C-16

Part I

APPENDIX D
TM8-E/TS03 DRIVE FUNCTION TIMER

............ "...
PROOUCT coo,,

MAINC£C.0a-OHTSE-A.O

PRODUCT NAM,~

TMS-t/TS03 DRIVE rUNCT10N T!MER

OAT[ CRtATEg!

JUNE 16. 1",

MAINTAINERI

DIAGNOSTIC CROUP

AUTHORI

H. B, BARNES

THE IN'ORMATION IN THIS OOCUMENT IS SUBJECT TO
CHANGE WITHOUT NOTIQ£ ANO sHoy~C NOT Bt CONSTRUtD
AS A COMMITMENT BY CIQITA~ EQUI~MENT CORPOAATION~
OlgITA~ EQU1~MENT CORPORATION ASSUMES NO
RESPONIIBILITY 'OR ANY tRROR! THAT MAY APPEAR IN
THIS MANUAL.
THE SO,TWARE CESCRIBEC IN THIS DOCUMENT IS
rURNISHEO TO THE PURCHASER UNOER A LICENSE 'OR US~
ON A SINGLE COMPUTtR SYSTEM ANO CAN 8E COPIED
(WITH THE INCLUSION or CIyITAL'S COPYRIGHT NOTICE)
nN~Y POR USE IN SUCH SYSTEM, EXCEPT AS MAY
OTHERWISE BE PROVIDEC IN WRITING BV CIGITAL.
DIGITAL EQUIPMENT CQRPO"ATION A5SUMES NO
RESPONSIBILITY 'OR THE USE OR RELIABILITV or ITS
SQfTWARE ON EQUIPMENT T~AT l~ NOT SUPPLI£O BY
OlG1TAL.
COPYRIGHT CC) 1"'. BV glGtTAL EQU1~MENT CORP., MAVNAMO, MA

D-I

Part I

..NOTE-.
ARt 'IVE DIAGNOSTIC ~AOGAAMS ASSOCIA'ED WITH THE TMS.E utCMAGTAPE
aND ITS TRANS'ORT SYSTEM, A~T~OUGH PHYSICA~~Y S£PA~A!E, TMEst
'ROGRAMS MUST IE TREATED AS A ~A~GE INTEGRATEC TEST. ANO TO ,NSURE PROPER
SVSTEM OPERATION, THEIE TESTS MUST BE £XECUTtD IN THE OROtR O'LINEATEC BE~OW~
T~tR[

CONTRO~

l' A GIVEN TEST SHOU~C 'AI~ AND IT APPEARS THAT A 'IX HAS SEEN rOUND,
ALL PROGRAMS MUST ONCE AGAIN at RUN. ON~V WHEN A~L TEST! ~AV~ RUN WITHOUT
ANY UNACCEPTABLE [RRORS CAN TME TMS.E SYSTEM BE CONSIOEREC up.
TM8.t OIAQNOSTIC PROGRAMS. OROER 0' EXECUTION
...
-...... -- .. -- ...... ------.-- •........•...•
1",

TMa.E/TSIJ3 CONTRO~ T[$T ~AAT

3'.

TMe.E/Tse3 ORIVE rUNcTION TIM,~

4'.

T"18.£/T$"1 CATA R'~IAel~lTY 9 TRACK

T~a.E/Tse3

CMAINOCc.ea.OHTSAI
"
Z", TMSeE:/TS"3 CONTROl. T[5T PAAT 2 CMAINO£c.ee·OHTIBJ
CMAINOEc.ee·OHTS,)
CMAINDEC.".gHTSCJ ,o~ 41< IVSTE"1S

MULTIDRlvt DATA EXERCISER (M AINCEc.ea e gHTSC) rOR at< AND ~ARGE"

D-2

Part I

or CONTENTS
•.•....•..•...•..
TA8~t

ABSTRACT

2~
2~i

AtQUIR[M£N'5

2'"

~ARDWA"t
~EMO"V

PROGRAM ~OAOING 'ROCEOU~E

~ROGRAM

,~
'~i
,~a

ITANOAAD TEST ~ROCtgURC
OAIV[ S[LECTION
T[ST PROCEDURE

~ROGR'M CQNT"O~S

I~I

~R£LIMINAAV P~OGRAMS

STARTJNG pROCEO~RE

,.,

tRRORS

,~,

TIME ~IMI'S l'tcl'lcATION

AtlTRICTIONS

t~ECU'IO~ 'I~~

11i

PROGRAM OEIC R1'TION

11 t,

L1S T INrJ

Part I

4aSTRACT

(F'AGE 1)

••...•..
T~E T~8E CRIVE rU~CTION TIMER ASSISTS IN
THE TESTING 0' THE TMlt CONTRO~ UNIT AND
'503 TAPE UNIT~ SE~ECTEO OPERf ONS AAE
E~ECUT£O, TIMEO, ANC T~, TIMES ARE T~tN
PRINTEO (IN Ml~LlSECO~O~"
THERE IS NO ~lMIT OR
~RROR T[STING rACl~'T'E5 IN THE PROGRAM, T~E
OEClSION ON T~£ VA~IO'TY 0' TIMES MEASUReD MUST
BE MAO£ BY TH[ OPERATOR, ANY CON'I~URATION
or UP TO 8 TI13 TAPt UNITS (1 ANO • C~'NNt~)
MAY BE S£L.tCTEO.

REQUIRfM£N'S
.•..........

........
'DP-e/f, 11M, II'
TE~ETYP[ OR COMPATls~t CEVICE (TTV'
TMI-E OECMAGTA'£ CONT~O~
T'03 M'STtA/S~AVE TRANSPORT 5Y~TtM
2',1

MEMORY

••••••
'HIS PROGRAM REQUIRES .~ 0' MEMORY AND MAY RtSIDE !N
ANY MtMORY rIE~D.

I~I

'AE~I~IN'AY PROGRAMS
.....•...........••.

PROCESSOR/MEMORY DIAG~OSTICS
'"8-E CONfAO~ TEIT PART 1
T~8-[ CON'RO~ TtS' PART 2
A~~

PROGRAM LOAOING PRCCE~UA[

... --.-- ... - ... _-_ ...... .
'WE !,ROGRAM INTO ANY D£SIREO flttMORY 'I[L.D USING
THt STANOARC 81NAR¥ ~OACER TECHNIQUE •

~OAO

•~

PROGRAM STARTIN~ PROCEDURE

..•..•...............•...•
A.

c,
0,
E.

LOAD ACDRI.S 1211
L.OAO THE EXTENDED ADORESS WITH 'HE PROGRAM rtELO~
c~tAR 'WITC~ES

DEPRESS CL.EAR. THtN CONTINUt
TH~ 'RO~RAM WILL PRINT ITS rlTLE ANO MAINOEC NUMBt A, THEN
ASK rOR DRIVE S~LtcTJON, ~RIOA TO MAKING o~!Yr
SELECTION. GO TO THt STANDARD 'EIT 'ROCEOURE IN PARAGRAPH '.

~OTE'

THE PROGRAM MAY BE RESTART~O AT ANY TIME AT ADURESS
IN THIS CAst THE PROGRA" ByPASSES PR1~TING
ITS TITLE ANO IMMEDIATELY ASKS '0" DRIVE S~L.ECTION.

e2~1.

Part I

(PAGE ~)
,~

......

STANDARD T£ST ~RoctOURt
~-.--.-

-.-.~.--

USE 0' T~E STANDARD TEST PROCEDURE ENSURtS PROPE~ THS.E/TSB3
CHEC~OUT.
IN'ORMATI0~ REGAROING T~E
TIME ~tMJT SP£CIPICAT10NS 'OR THE 'APE OPERATIONS TIM~O
BV THIS PROGRAM ARt GIVEN IN PARAGRAPH 7.~. NO
ERHOR OETECTION OR Ot~I~ION$ REGAROING P~O~ER PUNCTJON TIMES
ARE CARRIED OUT BV T~~ PROGRAM,
'~1

..-....

CRIVE SELEOTION
,,~

---.-~

TO SP£ClrV THE ORIVtCS) TO SE T£5T£0,
STtPSI

'~I

CA~RV

OUT THE PO~~OWING

MOUNT A S~AR£ R£t~ Or INOUSTRV COMPATIBLE MAQNETIC TAPE
O~ AL~ DRIVES TO eE SE~ErTEO WITH THE WRITE [N4BL~
RING IN PLACE CWR'T~ tNA8~[O)' LOAO THE TAPt~ AN~
POSITION AT BOT, ASSIGN ORIVE NUMB[RS IN THE 'OL~OWING
SEOUENCE, e'7'1,6'i'~'J'4' ANO THtN SWITCH ON ~rN[.

START OR RESTART TH~ PROGRAM AS OESCRIBED IN P'RA~RAPH 4!

RtSPONO TO "SE~tcT cRIVES" BY '-ETTING SR BIT N • ~ rOR
EACH ORIVE TO BE Tt 5T t O (DAIVE N)~ THEN 0E PA t S5 UONTI~UE'

~ES~ONO TO "SE~tcT 7 ANOIOR 9 '~AC~ OPERATION" IY
SETTING SR BIT N ~ • ON~Y rOR THOSE SE~ECT£o B~'VtS
wHICH ARt , T~ACK UNITS, THtN OE~~t'S CONTIN ~,

... ...-...

T[ST PRQCEDURE
~"'''

ACOOMPLISH THE 'OLLOWIN~ STtPS rOR ALL DRIVES IN THE ~VST[M UNOER TEST~
A.

SELECT ALL DRIVES IN T~E SY5TE~ UNOER TEST AS OESC RI BEO IN
PARAGRAPH
ASOVE.

AS SOON Ai TRACK ~[~ECTION IS COMP~ETE. THe PROGRAM
WILL START TIMING TME ~ARIOUS 'A~E O~RATION$
AND INDICATING A~~ TIMES ON THE TTV.

REPEAT THE ENTIRE TIMING PROCEDURE 2 TIMES~

COMPARE THE RESULTS AS PRINTtD ON THE TTV WITH THt ~lMITS
SPtcl,IED IN PA~AgRAPH 7,1. ADOITIONAL INrORMAT10N IS
GiVEN IN THE ~ROGRAM DESCRIPTION IN PARAGRAPH 1J~

'.1

D-5

Part I

(PAGE: 3)

... -.•....... -..
THERE ARt NO SWITC~ R(GISTEA OPTIONS ASSOCIATED WI'H r~IS ~ROG~A~.

,0,

[RHORS

....

_-.

THERE IS NO ERROR DETECTION INC~UO~O IN THIS PROGRAM~
4~~ DECISIONS MUST at MACE BY THE USER 9V COMPARING
THE rUNCTION TIMES ~RINTtc ON THE 'TV WITH THOSE rIM('
GIVEN IN THE TA9~t a£~ow.

·····.·······.-_·.w···· ••
THE TABLE BEL.OW L.lS TS T~E TIME L.tMITS IN THE SAME 'ORMAT
AS THEV ARE PRINTEO ON THE TTV.
rU~JC"10N

8"21 BPI
WR rM BOT DELAV
WRITE SHUTOOWN
WR I TE: ST ART
WR NONSTOP GAP
BI<SP SHOWN.SOWN
REAO SHUTOOWN
WRIT[ )(IRe;
L.A.T CHAR TO CUR
RO rM BOT OELAV

uNITe
'64
2. e
36

WRITE Eor
EFt TO £r SP TIME
WR TO ERASE HEAD
1 INCH OATA TIME
GAP1
GA'2

349

SPC£ SHOWN.SOWN

"I'"
.,
•
4
4

33;)

;'0

.8
,,4
33

.'
'"
3
3"
6

348

UNIT1
SAME
SAME
SAME
SAME
SAME
SAME
SAME
SAME
SAME
SAME
SAME
SAME
SAME
SAME

GA'~

GAl'.

GA'~

GA"'6
GAP,

GAPe

0-6

Part I
(!"Cit

... _-- ..... ..
~JONE

•

EXECUTION TIME

.-.-_ ..... -...

EXECUTION TIM[ VARIES o~~tNOING ON THE NUMBER ANO TY~'S or
DRIVES 8tlNG TESTED.

1e~

.... -.. ..... -...
PROGRA~ OESCRl~TION
-.~

1~~1

WRITE ~ROM BOT O£LAY
THIS IS THE TIME NECESSARY To MOVE BEGINNING
or TA~£ (BOT, MA~Kt~ AP~ROXIMATELY 6 l~CHES

'HE WRITE H~AD,
THE rlRST RECORD ON TAP~ MUST BE W~tTT[N
AT L~AST 3" AWAY rROM T~[ SOT MARKER.

~AST

P~OCEOUR£

To MEASURE T!MEI

REWINO TO BOT.

INJTIALl!£ we & CA ~OCATIONS.

LOAD COMMA NO REGISTER
~ITH ORIVE $£LECT, "1 B~J, 000 PARITY~

LOAD rUNCTION WITH WRITt , Go 8ITS.

NO~lTOR

CA RtGZST[A UNTIL IT INOICATtS rIRIT
WORD HAS aEEN TAKEN,

r. THE TIME rROM "GO" UNTIL rIRST WORO IS
OUTPUT IS "WRITE fROM 80 T DELAY."

D-7

fun!

WRITE SHJTOOWN

(~AGE

T~lS IS T~E TIME ~EC£SSARY TO CONTINUE MOVING
TAPE ArTER A RECORD IS WRITTEN 50 'HAT T~E
PROPEA I~TERRECORO GAP WI~~ EXIST BETWEEN RECORes.
~ROCEOURE

TO MEASUR& TIMEI

REWINO TO SOT~
INITtA~lit WC I CA ~OCATIONS TO WRIT~
WO~O RECORO rROM BOT,

2Z0(11)

ONE

c. LOAD COMMAND RtGIITtR WIT~ CRIVE SE~tCT,
8~0

11~3

BPI, 000 'ARITy.

LOAD 'UNCTION WITH WRI!~ , ijO BtT8~

ArTER MTT' SET' INDICATING TME END or RECORD, !NtTtATt A CONTINUOUS WRITE
ANo TIME Tl~L THE rlRST WORe II TRANsrERRto rROM MEHOR¥
TO T~[ TMI.£ CONTRO~ (OCCURS APPROXIMATE~V ON TH~ ~EAOING EOGE or SOWN)

WRITE START
THE TIME NEC£SSARV rOM TAPE TO AcceLERATE TO
rULL S~EEO • GUARANTEE A l/2" INT£RRECORO QAP~
~ROCEDUR[

TO MEASURE TIMEI

SAM, AS "WRIT[ rROM BoT" ~XCEpT NOW WE ARE
NOT AT aOT~
A,
B.
c~

E,
1e~.

INITIA~I~t WC , CA ~EGISTER,
LOAD COMMANO WITH DRIVE SE~ECT, 011 BPI. 000 PARITV.
LOAD JUNCTION WITH WRITE & GO IITS'
MONITOR CA rOR IT$ S(COND INCRtMENt,
THE TIME 'ROM "~O" UNTl~ 2Ne INCREMENT or CA
IS APPROXIMAT£~Y tQ~A~ TO "WAITE START~.

WRITE NO~STOP GAP
WRITE NONSTOP GAP IS ~QUIVA~ENT TO THE SU~
or "WRITE SHUTOOWN" , "WRITE START" ANO 15
THE TIME N£C£SSARV TO INSURE T~AT 'HE INTERRECORO
GAP WILL BE AT LEAST ~/a" WHEN WRl'ING
NON-STOP,
PROCEC UR £ TO MEASURE TIMEI
A,
9.

n.
r.

E,
G,

1~ITtA~l~E we & CA ~OCATIONS
LOAO COMMANO WITH oR1V£ ~E~ECT. 8~0 aPI. 000 PAA1TV.
LOAD 'uNCTtON,wRITt, GO BITS,
WAIT rOR "JOB DONE,"
ISSUE "CLr,"
RE.I~ITIALl~E we & CA ~OCATIONS,
LOAD rUNCTION.WHITE, GO BITS.
TIME PRO~ 2ND "GO" UNTI~ fI~ST WORD Of 2NO WRITE
IS OUTPUT IS "WHITE NONSTOP GAP."

Part I

(f2Ar;E 6'
10,'

BACKSPACE SHUTDOWN • SErT~E DOWN D[~AY
THIS IS TME ~ENGTH or TIME NECESSARY TO
GUARANTEE THAT Ir A WHITE OPERATION ro~~ows
• BACKSPACE TME TAPt Wl~~ BE POSITIONEO
SUCH T~AT 4~~ PREVIOUS OATA IS IN 'RONT
or T~E WRITE ANO ERASt H[AOS AND WI~~
BE ERASED'.
PROCEDURE TQ M~ASURt TIMEI
RECORD IS USEe W~lOH WAS JUST WRIT'EN IN
PREVIOUS TEST "WRITt NONSTOP GAP"~

1~~6

COMMAND WITH CRIVE SE~£CT. 010 BPI, 000 PAAITV.

~OAD

SET WC TO BACKSPACE 1 RECORC,

ISSUE BACKSPAct, QO,

ApT[q JOB CONE BECOMES A ONt
INOICA'ING TH~ eEijlNNING or THE RECORO
MONITOR TUR UNTI~ IT BECOMES A "1",
TH~ TIME PROM JOB DONE UNT1~ TUR IS
"BACKSPACE SHUTDOWN. SETTLEOOWN otLAV~"

REAC S~UTOOW~

THIS IS THE AMOUNT or TIME NECES~AAV TO CONTINUE
MOVING TA'£ A,TER A RECORO IS READ SO THAT
T~ERE IS tNOUG~ GAP rOA TAPE TO BE rULLY
ACCELERATtO l' A REAO 15 fOL~OWEO BY A !AC~SPACE~
~~EAO SHUTOOWN" MUST ALSO BE ~ESS 'HAN "WRITE
SHUTOOWN" TO 'UARANTtE T~AT THE W~fTE ANO
r~ASt ~EAOS WI~~ Bt POSITIONED SUCH THAT
A~~ PREVIOUS OATA 15 IN 'RONT or TME HtAOS
ANO Wl~~ BE ERASED IP A WRITE 'OL~OWS
A REAO~ IN AOOITION WHtN A WRITE 'OL~OWS
A READ THE INTtRRECC"C QAP MUST STI~L BE
AT I.E:AST 1/2"i
PROCrOURt TO MEASURE TIMEI
A.

RECORD USED IN "BACKSPACE SHUTOOWN" IS REAO,

I~ITIALIZE

ISSUE RtAO rUNCTION, 8ZZ BPI, GO.

APTER MTT' SETS INDICATING THE tNO or RECORD, INITIATE A CONTINUOUS WRIT£ ANO
TIME T!~~ THE flR5T WORO IS TRANSPERRto pROM MEMO~Y TO TH~ T~8.E CONTRO~
(OOCuRS APPROxIMATE~Y ON T~E LEAOING EOGE OF SOWN'~

WC 4 CA REGISTERS.

D-9

Part I

le~,

WRITE XIRG

(PACiE 1)

THIS IS THE TIME ~tCESSARY TO CAUS~ THE
CENERATION or AN INT[RRtCORO GAP T~AT IS AT
LEAST 3" ~O~C AS CO~PAR~O WITH THE NORMAL
3/5" GA~.
T~E PURPOSE IS TU E~lMl~AT£
WRITE ERRORS THAT MAY a~ CAUSEO IY A
DErEcTtvE A~EA ON TAPt, NORMA~LY ONE
REWRITE WITH XIRG WOU~O 8E su,rlCIlNT
I' IT ISNt' T~E PROCtgURE WOULD BE TO
REPEAT THE "BACKS'ACE-RtWRITE WITH XIRO"
SEQUENeE UNTIL A RECORO IS WRI'TEN WITHOUT
[RRORS+' tACH SUCCESSIVE REWRITE WOULD ADD
3" TO HE !NTtRRECO~O G.~ UNTIL "0000" TAPE

WAS Rt'CHED
PROCEDURE TO MEASURE TIMEI

IS NOT 90T,
"B. TAPE
INITIALI!E we • CA REYISTERS.

le~8

f
,

ISSUE WRITE WITH XIRG 'UNCTION. lee IPI. GO.

0',

MONITOR CA TO DETERMINE WHEN
rlRST WORD IS OUT~UT,

[',

TH£ T+ME 'ROM "GO" UNTIL rlRIT WORD II
OUTPU II "W~lTt WITH XIRG",

LAST CHARACTER TO CU READY
THIS IS THE AMOUNT Or TIME IT TAKEI rOR THC
CONTROL TO SENSE 3 HI5SIN~ WORDS ON TA,t
(END or RECORD) UNTIL "OU ~tADY" BECOMeS A "li"
PROCEDURE TO MEASURi TIMEI
A.

PROGRAM USES SAHt RiCORD THAT WAS
WRJTT[N OURING "WAITE XIRG."

LOAD COMMANO WITH O"IVE SE~tCT. lee BPI, ODD PARITY,

l~rTIA~llE

WAIT 'OR JOB OONE~

AEINlflAL1!E we & CA ~OCATIONS~

LOAD COMMAND WITH OAIVE SE~ECTI Bee BPI. ODD PARITY,

ISSU£ ~tAD rUNCT10N, GO.

WC TO SPACE REVERSE 1 RECORD.

WAIT UNTIL WCa0 A~O THEN MONITOR "CU READY"
IT BECO~£~ A "1".

U~Tl~

THE TIME rRO M WC.~ UNTl~ "CU RrAOY" • 1 IS
"LAST CHARACTER TO CU REAOy".

D-I0

Part I
(FIAGE 8)
1~~9

READ PROM BOT
THE rlRST RECORO wRITTEN ON TAPE 1& SUPPOStD
TO 8E AT ~EAST 6" rROM T~E aOT MARKER
IN T~E EVENT T~AT THIS CONOITION WASN'T MET
%T IS STt~L OESIR[ASLE TO REAO T~E RECORO~
REAO rROM aOT IS THE TIME 'ROM W~EN A REAO
rUNCTION IS ISSUEO UNTI~ T~E rlRST WORO IS
OUTPUT',
PRocrOUR£ TO M[ASURt TIMEI
A.

THE RECORe THAT WAS WRJTTEN JUST orr BOT
OUAING "WRITE START"
USED.

TAPE IS REWOUND TO SOT~

INITIA~liE

ISSUE READ rUNCTION, leI BPI, GO,

MONITOR CA TO OtTERMINE WHEN flRIT WORe

we & CA REGISTERS,

IS OIJTPUT',
r~

1',10

THE TIME '~OM "QO" U~J~ 'IRST IRtAK IS
"READ 'ROM 80T,"

!PAC£ SHUTOOWN • SETT~tgOWN 0E~AV

SPACE SHUTDOWN IS THE AMOUNT 0' TI~E NECtSIARY
TO CONTI~UE MDVING TAPt ArTt~ A RECO_O ,I
IPACED QV£~ IN T~' 'QRWARD QlRtCT10N 'ON THi
SAME REASONS AS "AtAO 5MUTOgwN",
PROCEDURE TO MEASURE Tl"EI
A.

SAME R£CO.O IS USED A5 IN T~ W~ITE START,
INITIA~li£

we TO ~~ACt rORWA~D 1 AECORO,

ISSUE S~AC£ rOAWAHD 'UNCTION,

~ONITO~

JOB CONt UNTI~ IT J5

eJ~ .~l,

.t.

c, TIME '~OM Joe CONt 11 UNTI~ TU" II

"SPACE SHUTDOWN ~ IETT~EDOWN OE~AY",

0.11

GO;

Part I

10.11

w~ITE

(PAGE 9)

Eor

TO WRI1E AN ENO 0' rl~E ~ARK I! IS NECESSARY
rOR TAPE TO MOVE J lNCHtS SErORE W~ITING
A HECORO WIT~ £XTENUEO INT[RRECORO GA'.
~OWEVER. AN Eor MARK COHRESPON05 TO A
1 WORO RECORO, T~t TIMt s~ou~O BE
S~IG~'~Y ~ARGER THAN "WRITt XIRG"~
TO MEASURE TIM[I

P~OC[OURE

11~12

UNIT IS RtWOUNO TO eo!,

TA~£

t~tTIA~l!E

ISSue WRITE. ae0 aPI, GO.

WAIT rOR 10e CONt,

I: "

ISS UEeL. , '.

ISSUE WRITE tor rUNCTION, ell aPI. GO;

WAtT 'OR JOB CONt .~

THE TIME rROM "ijO" UNTl~ "Joe aONE" IS
"WRITE EO',"

we & CA REGISTERS,

EOR TO EO' TIME
THIS IS T~£ TIME ~tEOEO TO MOVE TA'£ FROM
ENO 0' A RECORD TO AN END 0' 't~E MARK
WRITTEN A,TtR IT, THE ~ROCEOUR£ UIEe TURNS
OUT TO Bt A T[ST or THt WRITE ANO tRASt
~tAO PO~ARITIE8,
I" THt TIME PRINTEO IS
EQUAL. TO IERO IT IS AN INOICATION THAT THt
Eor WAS ~O' rOUNO WHtN "JOB OONE" BECAME A ONE;
T~E

THIS COU~O
"ROB~EMSI

INOICATE ONE OR MORE or THE rOL.L.OWING

(RASE HEAo POL.ARrTY REVERSED,

ERASE HEAO CURRENT NOT iurrlCICNT TO ~ULL.Y
SATURATE TAPE.

ONE OR MORE or WRIT' HEAO TR~C~S ~O~ARITY
REVERSEO,

ON! OR MORE SENSITIVE REAO AMPL.l'!E~'~

WRITE EOr rUNCT10N OION'T REALL.Y WRITE AN EO, MARK~

OTHERW!SE "EOR TO Eor SPACE TIMt" SHOULD BE
SLl~HTLY LARGER THAN "WRITE Eor."

0-12

Part I

(PAGE: .1~)
PROCEDURE TO MEASURE TIMEI
A,

A RECORO ANO EOf WA' p~tYJOUSL' WRITTEN
rROM BOT rOR "WRITE: EO'",

TAPE IS REWOUNO TO BOT,

REWRITE RECORO OVER PREVIOUSLY WRITTEN REeo~o,

BACKS~ACE:

SET we REGISTER TO ~PACE 2 R£COROS~

ISSUE SPACE rCRWARO rUNCTroN, SET GO,

WAIT POR we REGISTER TO INDICA'E THAT
rlRST RECORO HAS Ht,N SPACEg OVER 'HEN
MONITOA ~CU ~EAOV" UNTIL IT StCOMES A
"1" •• 'TEA "eU HEAOV" CHECK TO SEE I' "EOr"
IS A 1 IN STATU~ R£~ISTtR, I' EO' IS NOT
SET TMEN ZERO TIME QOUNTtRi

TIME 'ROM WC'.l UNTIL "CU PtAOV" IS "EOR TO EO' SpACE TIME"

OVER RECORO JUST WRI'T[N~

D-13

Part I

(flAQE
1~.13

1.'

WRITE TO ERASE H~AO
THt "WRITE TO ERASE ~tAC" TEST INSURES T~AT THE
TAPE IN 'RONT or THE WRITE HEAO IS ERASEO
OURING A WRITE O~£RAT'O~,
TO MEASURE TIMEI

~~OCECURE

A ~ONG RtCORO HAS BtEN WRITTEN '"OM aOT. SAHE
REcORe T~AT WAS USEe TO TIM£ "WAITt rROH aOT

DE~AY"

TAPE IS R[WOU~O TO BOT~

we REGISTER IS INITIA~I~EO rOR A 3 WORO RECORD
CA ~EGISTER IS INITIA~liEO TO ~77'~

~OAO COMMANO RE~15TtR
8~0 8~!, 000 PA~lTV,

~OAO

MONITOR CA UNTl~ IT 1$ 3771 INDICATING 2 WOROj
SEEN OUTPUT, TMEN ISSUE eLT WHICH
STO'S A~~ DATA TRAN~r[RS , CAUSES THE ORIVE
TO S~UTCOWN.

REWl~O

INJTIALlaE CA TO ~77'

ISSUE READ 'UNCTION, 001 B~l, lET GO,

MONITOR CA UNTI~ IT IS 3171 THEN
GO TO TIMING ROUTINi ANC TIME UNTIL CA~~mmm
THIS TtME WI~~ lN01~ATE THE DISTANCE BtTWEEN
THE ~AST WORO or TH' NEW DATA ANO THE
rlRST WORe or THE O~O OAT4 WHICH IS ALSO
THE AMOUNT or TA', T~AT WAS ERASEO BV
THE ERASE HEAO OUH1NG THE WRITE OPERATION~

WITH CRIVE SE~ECT,

'UNCT10N REGISTER WITH WAtTE & 00 BITS,

~AV[

TO BOT~

D-14

Part I

(fiACiE:
11~14

1l)

ONt INCH OAT A TIME
ONE INCH or OATA, 8~0 BPI (A~SO '5' & 211 l~
, CHANNE~ UNIT), IS wHITTEN ANO TIMED TO
OET[RMJNE If TAP~ IS MOVING AT PRO~ER SPEED.
~ROCEDUR£

11~1'

To MEASURt TIMEI
we & CA REGISTERS. OA(3716) WC(.~01~)

INITIA~I~E

ISSUE WRITE rUNCTION,

WAIT rOR CURRENT MEMORY ADORESS REGISTeR
TO INOICATE 'IRiT WORC IS TAKEN AND THeN
MONITOR WORe COUNT UNTI~ EQUA~ TO lERO,

TIME '~OM PIRST
COUNT~I IS "ONE

e~0,

"6 OR 2a~ BPI, GO,

WOAQ OUTPUT UN'I~ WORD
INC~ DATA TIMt~"

GAP CONSISTENCY

'OR PROPtR OPERTION THE INTERRECOAO GAPS ON
TAPE MUST A~WAVS Bt AT ~EAST 1/i or AN INCH.
THIS WI~~ A~~OW OATA WRITTEN USING ONE TAPE
UNJT TO BE READ O~ ANOT~ER rAPE UNIT WHEN
THE START/STOP CHARACTERISTICS or £ACH UNIT
ARE DlrrER£NT, THE MINI~UM GAP SI!E or
1/2 AN I~CH IS G£NERATEQ WHEN A WRITE 'O~~OWS
A REAC~ ALL OTHER GAPS SHOULD aE LARGER
OE~ENDING ON HOW THtY WERE WRITTEN.
pROCEDURE To HEASURE TIMEI
A. A TOTAL 0' NINE ~ECORDS ARE WRITTEN ON
TAPE ,rROM BOT) UTl~IiING olffERENT SEQUENCE!
TO GENERATE THE INT~RREcoRO GAPS.
9.

TH£ TAPE IS REWOUND TO aOT~

INITIAL1~£

lSSU£ REAO fUNCTION, eBI BPI, SET "GO"~

£.

WAIT ,OR "OU READY" TO BECOME. 1
TH£N REPEAT STEP C AND RESET "GO" TO
CONTINUE NONSTO~.

NOMITQR CA REGISTER TO OETERMINE WHEN
PIRST WORD IS INPUT.

THE TIME PROM W~£N "GO" IS RESET UNTIL
THE rlRST WORD IS INPUT WI~L R£PLECT
TH£ SllE or TH~ ~AP,

ST£~S t,P ARE REPEATED UNTIL A~L 8
GAPS A~E MEASURED.

WORD cOUNT AND CURRENT ADCRESS A~G'IT£R!,

D-15

Part I

(r-'AGE 1~)
PROGRAM SEQUeNCE rOM EAC~ GAP,
GAPl

WRITE rO~LOW£O BY A WRITE

GAP2

WRITE rO~LO~EO ev l WRITE (START/STOP),

GAPJ

REAO rOL~OWEO BY A W~lTE (START/STOP),

GAP4

WRITE~BACKSPACE

GAP,

SA~[

GAP6

SAMt A9 GAP4 txctPT WRITE_SACKSPACE REPEATED ~ TIMESi

OAP7

SAME A9 GAP4 EXCEPT WHITE-SACKSr-'ACt REPEATED 4 YIMESi

GAPe

SAME AS GAr-'4 EXCEPT WRITE.aACKS~ACE REPEATED ,

(NONSTO~)~

'OLlOWED BY A WRITE

(STAAT/S'Or-'J~

AS GAP4 tXCEPT WRITE_BACKSPACE "EPEATEC 2 TtMESi

I!MES~

GAP LENGTHS SHOU~O REr~tcT T~E rOL~OWING RE~ATION§~Ir-'1
8)7>6)')4)1. a)J
11~

~ISTING
..
--.--

(ATTACHEO)

D-16

Part I

APPENDIX E
TM8-E/TS03 UTILITY DRIVER

IOE~T1F'1t;ATION

PRODUC" oODtl

MAINOEC·~B80HTSf·A~O

ftRODUCT ~AHf;1

TH8.E/TS~J

n.'E CRE4TEIH

21..SEPT~15

MAINTAINERI

DIAGNOSTIC GROUP

AU'PHORI

Ft·, B. BARNe;S

UTILITY ORlvER

THt tN'ORMATION IN THIS DOCUMENT IS SUBJECT TO CHA~GE WITHOUT
A~'O ~HOUI.O NOT ,&: CONSTRUED AS A COMM I TME~T £IV 0 I GI TAL.
EQUIPMENT CO~PORATJCN. OIGITAL EQUIPMENT CORPORATION ASSUMES
NO RESPONSIBII.ITY POR ANY EHRORS T~Ar HAY APPEAR IN TH!5 MANUAL.
~OT I CE

DESCRI6tD IN THIS OOCUMENT IS rURN1SH£C yo THE
PURCHASER UNOtR A ~'C~N'E POR ~~£ ON A SINGLE COMPUTEH SYSTEM
AND CAN BE COPIEO (WITH INCI.USION or OIGITALIS COPVRtijHT
NOT lCE» ONLY rOA. USE I N SUCH SY:»TEM, EXCEPT AS MAY gTHEHw 1SE
BE PROVIDED IN WRITI~ij av OIGITAL,
,.~[ SO'T~ARt

OIGITAL P.QUIPMENT CORPO~ATION ASSUMES NO RESPONSISII.ITY rCA
THt USe OR REI.IA81l.JTV Qr ITS sorTWARE ON·~QUI'H£N" THAT IS
NOT SUPPLIEO 9¥ OIG1TAL.
COPYRIGHT c~, 19"
BY C1Gl?A~ ~QUIP~ENT COR'ORATI0N

E-I

Part I

TAB~E

.. ....
F'ARAGRAPH
-.~

~.
44 ,

"
"
6,

8,
9.

Dr CONTENTS
SUBJECT

........

AEJSTfUCT
REQUIREMENTS
~OAOJ~G PROCEDURE
TAR INC ~ROCEDURE
CONSO~E SWITCHES
OPERATION
P~OG"AH OESCRIPTI0N
SY~T'M OISPL.AY
I. J~T PH,

E-2

PAGE

_.-.
1

1
1
1

1
2
~

Part I

CPACiE 1)
1~

4B5TRACT

.........
'~IS PROGRAM IS I~TE~UE~ AS A BRUTE fORCE ROUTINE TO
EXECU'£ AN OPERATION OR SEaUE~jC~ OP OPERATIONS cnNTINu,OUSLY
REGAROL~SS gr THE "RESULTS Of T~~ OPERATION,
T~L UTILlTY
D~IVER WILL ALLOW THE O~ERATOR TO 00 ANYTHING IN ANY URUER~
THtRE .Rt ~o ERROR C~~CKS OH PRINTOUTS MADE. AND A~Y
VAAJA'IO~ rRCM PRESET S~~UENCES ANO VALUES ARE MAOE BY
CHANGING '~E A~PROPRIAT~ MEMORV LOCATIONS.

REUVIR~MENTS
.....•......

••
B,

LOADING ~ROC£oURt
..•..•...........
ws~

ANY PD~.8 PROCESSaA
TM8.£ ~AGTAPE CONTROLLER
AT LtAST C~E TAPt O~IV[
A' LEAST lK or CaRt

STANOARD BINARY LOAQJNG PROC£DURE~

STARTING PROCEOURE

..•...............
4LWAYS STA~T AT 20m~8l.

CON$OLE
StTT1NijS
....
-.............•....
swrTC~

SW",

1 • STOP AfTER ~AC~ OPEfU TJON

SW1'

STOP AT
1
0 • PROCEED

SW~I

• IGNORE ~NC or TAPE

SW:SI

1
Z

~EGlST[R (SEE PAGE 4)
• OISPI.AY
CO NOT OISP~Ay

PROCEEO

THE END OF' THE OPERATION

a • ~ EWpJ 0 ATE 0 T

•

E-3

Part I

(PAGE 2)

... ......
~

THE PROGqAM OP£RATIO~ 15 PUITE SlHP~E, BUT DOES ~EQUIHE
THE OPER4TOR TO ~AVE K~OW~£OGE or ~AGTAPE SYSTEM AS O~.
ERAT£D O~ TM8.C CONTRO~~ERI THL OPERATOR ~UST ~£ A~LE TO
DECIDE W~10H S£QUENct or OPERATIONS S~OU~D BE RUN AND
WHAT VA~UtS TO ASSlijN T~£ VARIOUS PARAMETERS REQUIRED TO
RUN THEM. THE OPtRATION SEQUENCE IS SET UP BY FI~LING
• TABLE (fNTa~) WITH C~.CODES IN THE DESIRED SEQUENCE AND
LOA~l~O THE NUMBER or O~ERATI0NS IN A COUNTER CFNC'N),
THE PROG~AH W1L~ EXtcUT, EACH or THE OPERATIONS tN TH~
TAB~£ IN THAT ORDER CONTINUOUS~Y UNLESS STOPPEO 8Y SW~ ~R
9Wl aEtNQ lET TO A ONE ~1)~ THE PROGRAM IS PRESET TO DO
CONT!~UOUS WRITE TO UNI! ~£RO ("
WITH DENSITY or 81~ BPI
(9 TRK, IN 000 PARITY, 'AC~ RECORO IS TWENTY C2B) CHAN.
AeTiRS AND DATA IS TAKEN fROM MEMORY STA~TING AT ~ocAT10N
411, tv THE PROGRAM 15 LOADED AND STARTED AT 2B0 WITH NO
CHANGES ~AD£ AND SWITgH'S 1- ANg l' SET TO ~ERO (B), THIS
OPERATION W1L~ EXEQUTt QONTINUOUS~¥.
,~t rOLLOWING IS A ~l"
~LUI 'HEIR OESCAtPT10N

•....•...

of PARAMETERS WHICH HAV BE VAHIED
AND CORE ~OCAT!ONSI

........

.. .....•....

UDES

UNIT DESCRIPTI0NI D£SITY,
PA~ITV, UNIT NUMAER, ETC.

WDQNT

NUMBER or WORDS PER READ
OR WRITE

WADD

STARTING ADORESS or WHITE
BUfI"PEFr,

STARTING ADDRESS OP R~AO
BUFfER',

~ADO

seNT

NU"B[R or RECORDS '0 y£
SP.CEO OVER (POHWAAU UR

REVE~SE).

NUMBER or OPERATiONS TO
BE EXECUTEO IN SEQUENCe
fROM FUNCTION TAeLf,

rCNTR

OE~AY

JOD~Y

fL.AG.
OE~AY

OPD~Y

E-4

Tl~E

rOR Joe CONE

BETWEEN OPEHATtUNS.

Part I

(PA~E

TABLE Or or-COOl TO BE
[XECUTEO.
6~1

FUNCTION COOES

(F!L~

INTeL WITH AN¥ or T~E rOLLOWING)

orF'l.lN[
REi/INo
-=
2"l:''' • READ
3~"i'I ! REAO COMPARE:
~"lc1fJ

!II

1li~0

41""" ..• WRITE END or
~RITE

5~e"

rl~~

SeNT)
Jl'ORWARO
,,,.,0 , SPACE
SPACE REVERSE (Sl£ SeNT)
6~""

.~2

<S~E

OENSITV sELleT (SITS ~0 • 11 OF UDES)

• 2~0RPt 7TRK
01 • 556BPI 7TAK

1~ • 6~219~! 7TRK
11 • 8~~BPJ 9TRK
6~~

'AAITY CBJT 3 Or UOtS)
" • EVEN PARITY
1 • ODD F'ARITY

6~~

UNIT SELECT (BITS 0, ~, 2 Of UD~S)
iHHlI

:II

UNIT 21

001 • UNIT 1

E-5

Part I

..•..••.......•... ,
I~ OReER TO MAINTAI~ T~~ CONTINUOUS EXECUTION Of OPERATION
AS OESCRIBEO, T~E PHO~RA~ IS ORGAINlEO AS POLLOWS.

START
C!L.EAR AI.L. PL.A"!
SETUP

"'OuSEKEEPING
StTVP OP-COOE REQUIRED PARA~[T[HS
STAHT fUNCTION
WAIT-roR JOB DONEI PER ADOL.Y

EXECUTe
AWAIT ENO

PER OPDI.V
If ENO or SEQUENCEI STOP ~
£L.Sl JUMP TO STAHT
PAU~E

OELA'"
END or SEQUENCE?

5TO"

JUMP To START

RESTART SEQUENCE

..REG1S!!R
.......--.... (PtA
DISPLAY

SW3~1)

8ECAUSE IT IS NOT POSSl~L.E TO EXA~INE T~E OONTENT~ or
VARIOUS HAROWARE R~G!~T~RS o~ !Hl TM8-E OIRECTLY, A
SOFTWARE ROUTINE l~ P~OVIDEO TO DISPLAY TH~M IN THf

ACCUMU~ATOR t.e) WHENEVER THE PROGRAM IS STOPPED BY
SW. oR 1, WHEN STOPPED AT THE END or AN OPERATION OR
SEQUENCE or OPERATICN~, SET SW3.~ AND PRESS CONTINUE
SIX (6) TIMES, EAQH CONT1NV~/~'L.T. WIl.l. DISPLAY A
OlffER£NT REGlSTER~ TO EXIT TMIS ROUTJNE AND cONT!NUE
OPERATION, $£T S~3.Z AT ANV TIME, CONTINUE/HAI.T MAY
BE PERPORMED MORt THAN ~tX (6) TIMES TO ~[EXAMtNL A~L

REGISTERS~

FO~~OWING I' THE ~I~T o~ REyIS!tRS OISP~AY(D AND THE
OR PER IN WHICH THEY APP'AR~

ReAR

:1.
••

RMSR
ReMR

RWCA

Rf'SR

ROBR

WORO COYNT
CURRENT ADDRESS

MAIN ;'TATUS COMMAND. R[GIS.TER
F'UNCTION/STA!US
DATA tlu~rER

~lSTING

.. -'!'--!!'"

E-6

Part II

APPENDIX F
TMS-E INTERFACE AND INTERNAL SIGNALS

Appendix F lists and identifies all the TS03/TMS-E interface signals. Figure F-l identifies the interface with the Omnibus
along with the Omnibus pin assignment for each signal. Also listed are all the signals internal to the TMS-E.
Two 7011571 cables are used to connect the TMS-E to the TS03. One cable is connected between the MS321 Output
Control module and the "C" connector on the MS920 adapter module to provide control signals to the tape drive and
data to be written on the TS03 0 ECmagtape (Table F-l). The other cable connects the MS323 Status and Control
module to connector "0" on the MS920 adapter module to provide status information and data read from the TS03
OECmagtape to the TMS-E Controller (Table F-2). The signals on the HS51 edge connectors that interconnect the four
TMS-E modules. are shown in Tables F-3 through F-6. Table F-7 lists and defines all signals within the TMS-E Controller.
The signal prefix indicates the origin of the signal. i.e .. all signals prefixed by C originate at the TS03. The following is a list
of the prefixes and their meaning.

Origin
TS03
MS321 module
MS322 module
MS323 module
MS327 module

Prefix
C
OC
CB
SC
RE

The numeral following the prefix indicates the sheet of the module print where the signal originates. i.e .. RE-2 indicates
the signal originates on the MS327 Module. sheet 2.

F-I

+15V

+5V

-15V

-15

-15V

GND

SP GND

GND

MA6L

IR0 L

I/O PAUSE L

TPI H

MA4L

INT STROBE H

MA0 L

EMA0L

MA9L

IR1L

C0L

TP2 H

MA5L

BRK IN PROG L

MAIL

GND

MA10L

IR2 L

C1L

TP3 H

MA6L

MA,MS LOAD CONT L

MA2L

EMA2 L

MAil L

C2 L

TP4H

MA7L

OVERFLOW L

MA3 L

MEM START L

MD6L

BUS STROBE L

TSI L

MD4 L

BREAK DATA CONT L

MD0 L

MD DIR L

MD9L

INTERNAL I/O L

T S2 L

MD5 L

BREAK CYCLE L

MDIL

SOURCE H

MDI0 L

USER MODE L

NOT LAST XFER L

TS3 L

MD6 L

LA ENABLE L

MD2 L

STROBE H

GND

+5V

MDII L

F SET L

INT ROST L

TS4 L

MD7L

INT IN PROG H

MD3 L

INHIBIT H

DATA 6 L

PULSE LA H

INITIALIZE H

LINK DATA L

DATA 4L

NTS STALL L

DATA 0 L

RETURN H

DATA 9 L

STOP L

SKIP L

LINK LOAD L

DATA 5 L

RES H

DATA 1 L

WRITE H

GND

DATA 10 L

KEY CONTROL L

CPMA DISABLE L

IND I L

DATA 6 L

RUN L

DATA 2 L

ROM ADDRESS L

DATA 11 L

MS,IR DISABLE L

IND2 L

DATA 7L

POWER OK H

DATA 3 L

LINK L

c:::::J1

QUAD MODULE
(COMPONENT

c:::J

---

SIDE)

~----------------------~

<c -< ~",." z,; r ~;mo 0", " ,

< c-<w" ~z",r ~~I~moO "'"

~--------------

C2-

D2
CONNECTOR D
SI DE t

D
08

Figure F-1

Omnibus Pin Assignment

1699

Part II

Table F-l
M8321 Output Control Module Signals and Interface

M8920
Connector C
Pin No.

Jl
M8321
Pin No.

A1
B1
C1
01
E1
F1
S1
J1
K1
L1
M1

0
F
J
L
R
N
LL
V
X
Z
BB

J2
M8321
Pin No.

Signal
C SEL 0 H
C SEL 1 H
C SEL 2 H
CSEL16H
C DEN 5 H
C DEN 8 H
C FMK L
CWXG H
C FWD H
C RWDH
CWRE H

02
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
S2
T2

L
N
R
T
V
X
Z
BB
DO
FF
JJ
LL
NN

CWDOH
CWD1 H
CWD2 H
CWD3H
CWD4 H
CWD5 H
CWD6 H
CWD7 H
C REWH
C INITH
CSET H
CWDR H
C PEV W H

CWFMK H

*Not used in TM8-M system.

F-3

Description
Buffered SE LECT 0
Buffered SE LECT 1
Buffered SELECT 2
Not used
*Density 5
*Density 8
File Mark
Extended gap
Move tape forward
Move tape reverse
Write Enable with CFWD H, go
off line with CREW H
Write bit 0
Write bit 1
Write bit 2
Write bit 3
Write bit 4
Write bit 5
Write bit 6
Write bit 7
Rewind
Initialize
Begin tape operation
Write Data Ready
Generate or check for even parity
when asserted
Write File Mark

Part II

Table F-2
TM8-E M8323 Transport Status Control Module Signals and Interface

M8920
Connector 0
Pin No.

J1
M8323
Pin No.

A1
B1
C1
F1
H1
J1
K1
L1
M1
N1
P1
R1
S1
02

0
F
J
R
T
V
X

J2
M8323
Pin No.

Signal

Description

C ROS L
CSOWN L
CTUR L
C ROO L
C R01 L
C R02 L
C R03 L
C R04 L
C R05 L
C R06 L
C R07 L
CROP L
C FMK L
CWRS L

C CRCS L

F2
K2

R
X

M2
N2
P2

BB
DO
FF

C RWS L
C BOT L
CWRL L
C VPE L
C SELR L
C 7CH L

R2
S2
T2
U2

JJ
LL
NN
RR

C EOT L
C CRCE L
C LRCE L
C LRCS L

Read Data strobe
Tape motion is stopping
Tape Unit Ready
Read bit 0 from tape unit
Read bit 1 from tape unit
Read bit 2 from tape unit
Read bit 3 from tape unit
Read bit 4 from tape unit
Read bit 5 from tape unit
Read bit 6 from tape unit
Read bit 7 from tape unit
Read Parity bit
File Mark (end of file)
Write Strobe indicates data on CWO
lines has been written on tape
CRC strobe, appears with CRC
character
Tape Rewinding
Beginning of Tape
Write Lock prevents writing on tape
Vertical Parity Error
Existing transport is on line
7 channel asserted when 7 channel
tape unit is selected
End of Tape
CRC Error
LRC Error
LRC strobe appears with the LRC
character

BB
DO
FF
JJ
LL

Part II

Table F-3
TM8-E M8321 Output Control Module Edge Connector Signals
To M8327 Connector F
Signal
Pin No.
Not used
OC-2 RWCR L
RE-1 DB7 H
RE-1 FRO H
RE-1 DB5 H
CB-1 WR 1st 7 H
Not used
R~-1 DB3 H
RE-1 DB2 H
Not used
CB-3 MTTF L
5C-2 ERROR L
OC-2 LCAR L
5C-1 TUR L
OC-2 LCMR L
CB-3 CLR ALL L
OC-2 LCM/F lOB H
OC-2 LFGR L
Not used
Not used
RE-1 DB6 H
Not used
OC-1 RIC ERROR L
RE-1 CB1 H
OC~2 LWCR L
OC-1 ROB L
RE-1 DBO H
OC-2CCAR L
RE-1 FR3 L
OC-2IBCM L
OC-2 CLF L
5C-1 CONTROL B5Y L
OC-25BRM L
OC-2 LDBR L
Not used
Not used

To M8327 Connector H
Signal
Pin No.

A1
B1
C1
01
E1
F1
H1
J1
K1
L1
M1
N1
P1
R1
51
T1
U1
V1
A2
B2
C2
02
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

CB-2 MAC 2 H
RE-1 5EL 16 H
RE-1 PEVN H
5C-1 5ET H
Not used
RE-1 DBa H
Not used
RE-1 DB9 H
Not used
RE-1 DB10 H
Not used
Cg-1 WR 2nd 7 H
RE-1 DEN a H
RE-1 FR1 H
RE-1 FR2 H
OC-2CWCR L
OC-2 RM5R L
OC-2 RCAR L
Not used
Not used
CB-1 WDR H
Not used
CB-3INIT H
RE-1 B5EL2 H
RE-1 B5EL 1 H
RE-1 B5ELO H
CB-1 WR9 H
RE-1DB11H
RE-1 DEN5 H
OC-2 AC ENABLE L
OC-2 B TP3 H
OC-2 RF5R L
OC-2 RCMR L
RE-1 DB4 H
Not used
Not used

F-5

A1
B1
C1
01
E1
F1
H1
J1
K1
L1
M1
N1
P1
R1
51
T1
U1
V1
A2
B2
C2
02
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

Table F-4
TMS-E MS327 Register Module, Edge Connector Signals
To M8322 Connector E
Signal
QC·2lDBR l
OC·2SBRM l
CB·' WDR H
QC·2ClF l
SC-l SET H
RE·' ENABLE CHECK
CHAR l
SC·2 RDl H
SC·2 ERROR l
RE·l SEl2 H
RE·l SEll H
CB·3lBCM l
RE·' B SElO H
RE·2CAO H
SC·2 RD 2 H
CB·2 DB MPXB H
SC·2 RD3 H
SC·2 RDP H
SC·2 RD5 H
Not used
Ngtused
SC·l CONTROL BSY L
QC·2IBCM L
SC·' TUR l
SC·' EMA INC l
SC·2 RD OH
Not used
SC·l 7 CHANNEL H + DEN 5 H
SC·2 RD 7 H
RE·' BSEL 0 H
RE·l SEL H
CB·2 DBC 2l
RE·2WCO H
RE·' DBC , H
CB·2 DB MPX A H
Not used
Not used

Pin No.

To M8321 Connector F
Signal
Pin No.

To M8321 Connector H
Signal

Pin No.

To M8322 Connector J
Pin No.
Signal

Al
Bl
Cl
Dl
El
Fl

Not used
OC·2 RWCR l
RE·1DB7
RE·l FRO H
RE·' DB5
CB·l WR 1st 7 H

Al
Bl
Cl
01
El
Fl

CB·2 MAC 2 H
RE·l 5EL 16 H
RE·l PEVN H
5C·l 5ET H
Not used
RE·l DBa H

Al
Bl
Cl
01
El
Fl

5C·2 RD 6 H
CB·l COUNT WC L
CB·2 MAC 1 H
OC·2 LCMR L
RE·1 5EL 16 H
IEEF L

Al
Bl
Cl
01
El
F1

Hl
Jl
Kl
II
Ml
Nl
Pl
Rl
Sl

H1
Jl
K1
L1
Ml
Nl
P1
Rl
51

Ul
Vl
A2
B2
C2

Not used
RE·1DB3
RE·1DB2
Not used
CB·3 MTTF L
SC·2 ERROR L
OC·2 LCAR L
SC·l TUR L
OC·2 LCMR L
CB·3 CLR ALL L
OC·2 lCM/F lOB H
OC·2 LFGR L
Not used
Not used
RE·1DB6

Ul
Vl
A2
B2
C2

Not used
RE·l DB9 H
Not used
RE·1 DB10 H
Not used
CB·l WR 2nd 7 H
RE·l DEN a H
RE·l FR1 H
RE·l FR2 H
OC·2CWCR L
OC·2 RM5R L
OC·2 RCAR L
Not used
Not used
CB·l WR 7 H

H1
J1
Kl
Ll
Ml
Nl
Pl
R1
51
Tl
Ul
Vl
A2
B2
C2

H1
J1
Kl
L1
Ml
Nl
P1
R1
51
T1
Ul
V1
A2
B2
C2

02
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

Not used
OC·l RC ERROR L
RE·' DB1
OC·2 LWCR L
OC·' RD B L
RE·1DBO
OC·2 CCAR
RE·' FR3 H
OC·2IBCM
OC·2 CLF
SC·l CONTROL BSY
OC·2 SBRM
OC·2 LDBR
Not used
Not used

02
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

. Not used
CB·3INIT H
RE·l BSEL 2 H
RE·' B 5EL 1 H
RE·l B 5EL 0 H
CB·' WR 9 H
RE·l DB" H
RE·' DEN 5 H
OC·2 AC ENABLE L
OC·2 BTP 3 H
OC·2 RF5R L
OC·2 RCMR L
RE·l DB4 H
Not used
Not used

02
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

RE·1 IEEF L
5C·l COUNT CA L
Not used
Not used
CB·l WR 9 H
OC·2lCM/F/DB H
Not used
DC·1 RC ERROR L
OC·2 RM5R l
CB·2 WR 2nd 7 H
CB·3 CLR ALL L
CB·l WR 1st 7 H
Not used
Not used
RE·l EMA INC
ENABLE L
CB·2DBCl L
RE·l DEN 5 H
OC·2 RF5R L
5C·2 RD 4 H
CB·3 MTTF L
RE·l GO H
RE·2 EMA 7 H
CB·2 MAC 2 H
RE·' FR2 H
RE·l FRO H
RE·l FRl H
CB·3INIT H
RE·l DEN a H
Not used
Not used

02
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
52
T2
U2
V2

Table F-5
TM8-E M8322 Control Module, Edge Connector Signals
To M8l27 Connector E
Signal
SC·2 RD3 H
SC·2 RDP H
SC·2 RD5 H
Not used
Not used
SC·1 CONTROL
BSY L
OC·2IBCM L
SC·l TUR L
SC·l EMA INC L
SC·2 RDO H
Not used
SC·l 7 CHANNEL H + DEN 5 L
SC·2 RD7 H
RE·l B SELl H
RE·l BSELOH
CB·2 DBC 2 L
RE·2 WCO L
OC·2 LDBR L
OC·2SBRM L
CB·l WDR L
OC·2 CLF L
SC·1 SET H
RE·1 ENABLE
CHECK CHAR L
SC·2 RDl H
SC·2 ERROR L
RE·1SELOH
RE·1SEL1H
CB·3 LBC M L
RE·l B SEL 0 H
RE·2CA 0 L
SC·2 RD2 H
CB·2 DB MPX B H
RE·l DBC 1 H
CB·2 CB MPX A H
Not used
Not used

Pin No.

To M8l2l Connector F
Signal
Pin No.

To M8l2l Connector H
Signal

Pin No.

To M8l27 Connector J
Signal
Pin No.

Tl
Ul
Vl
A2
B2
C2

SC·l PRESET H
SC·l TUR L
SC·l FM L
SC·1 Test
Not used
SC·l SDWN L

Tl
Ul
Vl
A2
B2
C2

CB·l SP REV L
CB·l REWIND L
CB·l BRK RQST H
Not Used
Not used
RE·l DEN 8 H

T1
Ul
Vl
A2
B2
C2

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
Al
Bl
Cl
Dl
El
F1

CB·2 CHG DI R L
SC·2 RDP H
SC·2 RD5 H
SC·2 RD3 H
SC·2 RD2 H
RE·2 CAO L
SC·l RD7 H
SC·2 RDl H
Not used
SC·2 RDO H
SC·l EMA INC L
SC·2 ERROR L
SC·l DATA LATE L
CB·3 CLR STATUS L
CB·l OFF LINE
CB·2 BTP3 H
CB·1 SPACE H

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
A1
Bl
Cl
D1
E1
F1

OC·2 RMSR L
OC·l RC ERROR L
OC·2 LCM/F IDB H
RE·2 EMA 7
SC·l COUNT CA L
RE·2 GO H
SC·2 RD4 H
OC·2 RFSR L
RE·l DEN 5 H
RE·l EMA INC ENABLE L
RD6 H
CB·l R/RC H
RE·1 WR/WFM
CB·2 R/RCAFT WR
Not used
Not used
SC·1 RDS • R + RCH

D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
Al
Bl
Cl
D1
E1
F1

H1
Jl
K1
L1
M1
Nl
Pl
Rl
Sl

CHG TRANS L
SC·2 EOT L
CB·3 MTTF L
Not used
SC·2 REWINDING L
SC·2 BOT L
CB·3 SEL ERROR L
SC·l WRS L
SC·l SELR L

Hl
J1
K1
L1
M1
Nl
Pl
Rl
Sl

Hl
Jl
K1
Ll
Ml
Nl
Pl
Rl
Sl

OC·l RC ERROR L
OC·2 RMSR L

Hl
J1
K1
L1
Ml
Nl
Pl
Rl
Sl

S2
T2
U2
V2

OC·2IBCM.L
CONTROL BSY H
Not used
Not used

S2
T2
U2
V2

SC·l WRS H
CB·l WCOV H
SC·1 SET H
SC·2 B LRCS L
CB·2 MAC ACC L
SC·l 7 CHANNEL + DEN 5 L
CB·3 BTP4 H
CB·3 CLR ALL
SC·l RECORD LENGTH
INCORRECT H
Not used
SC-2 SP REV· BOT H
Not used
Not used

S2
T2
U2
V2

CB·3INIT H
RE·l DEN 8 H
Not used
Not used

S2
T2
U2
V2

CB·l WR 2nd 7 H
CB·3 CLR ALL L
CB·l WR 1st 7 H
Not used
Not used
RE·1 EMA INC
ENABLE L
CB·2 DBC 1 L
RE·1 DEN 5 L
OC·2 RFSR L
SC·2 RD4 H
CB·3 MTTF L
RE·l GO H
RE·2 EMA 7 H
CB·2 MAC 2 H
R&l F2 H
RE·l FRO H
RE·l FRl H
SC·2 RD6 H
CB·l CONT WC L
CB·2 MACl H
OC·2 LCMR L
RE·l SEL 16 H
RE·1 IEEF
RE·l IEMF
SC·l COUNT CA L
Not used
Not used
CB·1 WR9 H
OC·2 LCM/F/DB H

T1
Ul
Vl
A2
B2
C2
D2
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
Al
Bl
Cl
D1
E1
F1

Part II
Table F-G
TMS-E MS323 Transport Status and Control Module, Edge Connector Signals
To MS322 Connector H
Signal
Pin No.
CB-1 R/RC H
RE-1 WR/WFM
R/RC AFT WR
Not used
Not used
SC-1 RDS • R + RCH
SC-1 WRS H
CB-1 WCOV H
SC-1 SET H
SC-2 B LRCS L
CB-2 MAC ACC L
SC-1 7 CHANNEL + DEN 5 L
CB-3 BTP4 H
CB-3 CLR ALL
SC-1 RECORD LENGTH
INCORRECT H
CB-1 SP REV L
CB-1 REWIND L
CB-1 BRK RQST H
Not used
Not used
RE-1 DEN 8 H
OC-2 RMSR L
OC-1 RC ERROR
OC-2 LCM/F/DB H
RE-2 EMA 7 L
SC-1 COUNT CA L
RE-2 GO H
SC-2 RD 4 H
OC-2 RFSR L
RE-1 DEN 5 H
RE-1 EMA INC ENABLE L
SC-2 RD 6 H
Not used
SC-2 SP REV BOT H
Not used
Not used

To MS322 Connector F
Signal
Pin No.

A1
B1
C1
01
E1
F1
H1
J1
K1
L1
M1
N1
P1
R1
S1

SC-2 ERROR L
SC-1 DATA LATE L
CB-3 CLR STATUS L
CB-1 OFF LINE L
CB-2 B TP 3 H
CB-1 SPACE H
CB-3 CHG TRANS L
SC-2 EOT L
CB-3 MTTF L
Not used
SC-2 REWINDING L
SC-2 BOT L
CB-3 SEL ERROR L
SC-1 WRS L
SC-1 SELR L

A1
B1
C1
01
E1
F1
H1
J1
K1
L1
M1
N1
P1
R1
S1

T1
U1
V1
A2
B2
C2
02
E2
F2
H2
J2
K2
L2
M2
N2
P2
R2
S2
T2
U2
V2

SC-1 PRESET H
SC-1 TUR L
SC-1 FM L
SC-1 Test
Not used
SOWN L
CB-2 CHG 01 R L

T1
U1
V1
A2
B2
C2
02

SC-2 RDP H
SC-2 RD 5 H
SC-2 RD 3 H
SC-2 RD 2 H
SC-1 RD 7 H
SC-2 RD 1 H
Not used
SC-1 RD 0 H

E2
F2
H2
J2
L2
M2
N2
P2

SC-1 EMA INC L
OC-2 LBCM L
SC-1 CONTROL BSY H
Not used
Not used

R2
S2
T2
U2
V2

F-8

Part II
Table F-7
TM8-E Signals and Signal Functions
Signal

Origin

Function

BAC 0 - BAC 11

Processor
AC

A 12-bit data word transferred from the processor AC to load
TM8-E registers.

OC-2 AC ENABLE

M8321

AC ENABLE is asserted any time a 670X instruction is
executed to enable bits on the Data Bus to be applied to the
TM8-E registers.

CBOT

TS03

BOT indicates the reflective strip at the beginning of the tape
is being sensed by the tape transport. If the transport is
rewinding or doing a space reverse operation when C BOT is
asserted, the transport stops.

*BREAK CYCLE L

M8322

*BRK IN PROG L

M8322

*BRK RQST

M8322

The BRK RQST flip-flop is set by an SBRM instruction or
during the write, read, and read/compare operations to initiate
the single cycle data break and transfer data.

RE-1 B SELO
RE-1 B SEL 1
RE-1 B SEL 2

M8327

RE-l B SEL 0 through RE-l B SEL 2 are outputs of the
Buffered Command Register applied to the TS03. They are
compared with RE-1 SEL 0 through RE-1 SEL 2 on the
M8323 module; if they are different, the CB-2 CHG TRANS L
signal is asserted.

*BUS STROBE

Processor
M8323

***

OC-2 CCAR

M8321

OC-2 CCAR is asserted when a 6702 instruction is executed to
clear the CA Register.

*CO and C1

M8321

OC-2 CLF

M8321

Clear all Flags (CLF) is asserted when the 6725 instruction is
executed to clear the TM8-E and the Transport Master System
Register if tape unit is ready (TUR). If tape unit is not ready,
clear status register, MTTF, and ERROR flag.

*Omnibus signals.
**Refer to Table 9-3, PDP·8IE & PDP·8IM Small Computer Handbook.
***Refer to Table 9-2, PDP·8IE & PDP-81M Small Computer Handbook.

F-9

Part II
Table F-7 (Cont)
TMS-E Signals and Signal Functions
Signal

Origin

Function

CB-3 CLR ALL L

Processor
M8322
M8321

Signal asserted by INIT from processor, SC-l TUR AND OC-2
CLF, DC-I CLT, and the INITIALIZE instruction to clear all
TM8-E and TS03 Master System registers.

CB-3 CLR STATUS

M8322

CB-3 CLR STATUS is asserted to clear the status registers,
ERROR flag, and MTTF if a CLF instruction is executed and
C TUR is not asserted by the transport.

SC-l CONTROL BSY

M8323

The Control Busy flip-flop is set by an RE-l GO command at
the Command Register (bit 5 = 1) on the next TP4 time and
cleared by MTTF.

SC-l COUNT CA L

M8323

SC-l COUNT CA L is asserted at break request time. If the
Read/Compare (R/C) Error flag is set to stop incrementing the
CA Register, the address of the data that produced a
Read/Compare error is left in the CA Register.

CREVH

M8321

C REV H is asserted by the space reverse function.

CB-2 CHG DIR L

M8322

The change direction flip-flop is set any time a change in
direction is sensed.

C SDWN L

TS03

Tape settling down (C SDWN L) is asserted 2.3 ms after the
MTTF flag sets for 10 ms.

C LRCS L

TS03

LRC strobe (C LRCS) is asserted by the TS03 when a LRC
character is read from the tape.

C CRCS L

TS03

CRC Strobe (C CRCS) is asserted when a CRC character is
read from tape.

CVPEL

TS03

Vertical Parity Error (C VPE L) is asserted when the TS03
detects a vertical parity error to set the VPE flip-flop.

C CRCE L

TS03

Cyclic redundancy check error (C CRCE L) is asserted when
the TS03 detects a CRC error.

C LRCE L

TS03

Longitudinal redundancy check error (C LRCE L) is asserted
when the TS03 detects an LRC error.

CSELRL

TS03

Select remote (C SELR L) is asserted when the transport is
selected and on-line. Other status signals are not valid until C
SELR L is asserted.

C SEL 16 H

M8327

For future use.

F-I0

Part II
Table F-7 (Cont)
TM8-E Signals and Signal Functions
Signal

Origin

Function

CFWDH

M8321

C FWD H is asserted by rean, read/compare, write, write File
Mark, and space forward functions.

CRWSL

TS03

Rewind status (C RWS L) is asserted any time the selected
transport is rewinding.

CCRCE

TS03

The CRC Error (CRCE) is set when the TS03 detects a CRC
error.

CB-3 T INIT L

M8322

T INIT (tape initialize) is asserted by space reverse at BOT,
select error, and CLR ALL L.

C INIT L

M8321

C IN IT L (initialize transport) is asserted by INIT from
processor.

CSETH

SET (C SET H) is generated by the TM8-E to initiate transport
operation.

CREWH

M8321

C REW H is asserted when 1 XXX is loaded into the Function
Register and initiates the rewind operation. The three bits are
decoded by the output control function decoder and applied
to the tape transport. The transport rewinds to BOT and stops.

CWDRH

M8322

Write data ready (C WDR H) is asserted by SC-l SET during a
write operation and is negated when word count goes to zero
by word count overflow (CB-l WCOV).

CWFMKH

M8321

Write File Mark (C WFMK) is asserted when SXXX is loaded
into the Function Register. The 3 bits (FRO-FR2) are
decoded by the output function decoder, and C WFMK is
asserted to cause the TS03 to write the End of File Mark
(EOF).

CWREH

M8321

Write enable (C WRE H) is asserted to inform the TS03 that
the TM8-E is ready to write, write File Mark, or rewind.

CWDOH
CWOl H
CWD2H
CW03H
CW04H
CWDS H
CWD6H
CWD7H

M8321

C WDO H through C W07 H are data bits to be written on tape
during a Write operation. C WDO Hand C WDI H are zero
values in the core dump mode.

F-ll

Part II
Table F-7 (Cont)
TM8-E Signals and Signal Functions
Origin

Function

CWXGH

M8321

Extended Gap (C WXG H) is asserted when bit 3 in the
Function Register is a 1 to cause the transport to leave a
3-inch gap between records.

SC-l DATA LATE L

M8323

SC-l DAT A LATE L is asserted when the computer fails to
service a BRK RQST before the next data transfer to or from
tape.

CRDOL
C RDI L
C RD2 L
C RD3 L
CRD4L
C RD5 L
CRD6L
C RD7 L

TS03

C RDO L through C RD7 L are data bits read from the tape
during a read or read/compare operation. C RDO and C RDI
are zero values in the Core Dump Mode.

C PEVN L

M8321

C PEVN L is asserted when bit 3 in the Command Register is a
1 to select odd parity. Even parity operation on 9-track tapes
causes a 1 to be written on channel 3 (on the Parity track) if
Data is all Os.

C RDSL

TS03

Read Strobe (C RDS L) is a 100-ns pulse asserted by the TS03
each time a data character is read from DECmagtape.

CTURL

TS03

Tape unit ready (C TUR L) is asserted by the TS03 when the
selected tape unit is ready.

C 7 CH L

TS03

Not used in TM8-M System. Remains negated.

CB-3 CHG TRANS L

M8322

The CB-3 CHG TRANS flip-flop sets and asserts CB-3 CHG
TRANS L when RE-1 BSEL 0 through RE-1 BSEL 2 from the
Buffered Command Register and RE-1 SEL 0 through RE-1
SEL 2 are different. CB-3 CHG TRANS is cleared by the next
SC-1 SET Pulse.

CPMA DISABLE

M8322

OC-l R/C ERROR L

M8321

The OC-l R/C Error flag is set to assert OC-l R/C ERROR if
an error occurs during a read/compare operation (data read
from DECmagtape is different from data in memory).

Signal

*Refer to Table 9-3. PDP-RIE & PDP-81M Small Computer Handbook.

F-I2

Part II

Table F-7 (Cont)
TM8-E Signals and Signal Functions
Signal

Origin

Function

RE-l DBOO-RE-l DBII

M8327

RE-l DB 00 through RE-l DB 11 is a 12-bit word from the
Data Register which could be data read from tape, data from
th~ AC, or data from the Memory Data lines. The input to the
Data Register is controlled by a data multiplexer on the input
of the Data Register. These bits are applied to the
read/compare error detection logic to compare them with
memory data during a read/compare operation.

CB-2 DB MPX A L

M8322

Selects data for input to the Data Register (Table 9-2).

CB-2 DB MPX B L

M8322

Selects data for input to the Data Register (Table 9-2).

RE-l DEN 5 H (bit 10)

M8321

See Table 8-1 for this function bit.

RE-l DEN 8 H

M8321

See Table 8-1 for this function bit.

RE-IIEEF

M8327

Enable Interrupt when ERROR flag (RE-I IEEF) is asserted if
bit 4 in the Command Register is a I.

RE-l IEJF

M8327

Enable Interrupt when JOB DONE (RE-l IEJF) is asserted if
bit 5 in the Command Register is a 1.

RE-l EMA 0
RE-l EMA 1
RE-l EMA 2

M8327

RE-l EMA 0 through RE-2 EMA 2 are used to address
extended memory (Table 7-1). Bit 6 in the Function Register
must be a 1 to use extended memory addressing.

RE-2 EMA 7 INC ERR L

M8327

RE-2 EMA 7 INC ERR L is asserted when the program tries to
increment beyond memory fields 7 and sets bit 8 in the
Second Status Register.

RE-l EMA INC EN L

M8327

Extended memory address increment (RE-l EMA INC EN L)
is asserted when bit 6 in the Function Register is a 1 to allow
memory to be treated as a continuous memory rather than 4 K
blocks.

RE-l ENAB CHK CHAR L

M8327

Enable check character (RE-l ENAB CHK CHAR L) is
asserted and sets bit 4 of the Second Status Register if bit 4 of
the Function Register is a 1 to read the eRe and LRC
character.

F-13

Part II
Table F-7 (Cont)
TM8-E Signals and Signal Functions
Signal

Origin

Function

SC-2 EOT L

TS03

End of Tape (SC-2 EOT) is asserted if the EOT reflective strip
is sensed by the selected transport. C EOT sets bit 8 of the
Main Status Register.

SC-2 ERROR L

M8323

The SC-2 ERROR flag is set by anyone of the following
conditions:
EOT
RIC ERROR
PARITY ERROR
BOT
EMA 7 INC ERR
REC LENGTH INCORRECT
DATA LATE
EOF
ILLEGAL FUNCTION
SELECT ERROR
The Error flag allows the skip line to be grounded if the SKEF
instruction is executed by the program.

RE-I FRO-FR2

M8327

Function bits FRO through FR2 are decoded by function
decoders in the TM8-E output control module and TM8-E
control module to determine TS03 DECmagtape functions and
generate TM8-E control signals (Table 8-1).

RE-I GO

M8327

RE-I GO is asserted when bit 5 in the Function Register is a 1.
RE-I GO must be a I to allow tape operation to start.

SC-2 ILLEGAL FUNCTION

M8323

SC-2 ILLEGAL FUNCTION is asserted by any of the
conditions listed in Table 8-2 to set bit II in the Main Status
Register.

INT STROBE H

Processor

INT I/O L

M8321

INIT

Processor

*Clears all flags in the TM8-E and TS03. It is asserted by
preSSing the CLEAR key on the front panel or by a 6007 lOT
instruction.

*Refer to Table 9-3, PDP-8/E & PDP-81M Small Computer Handbook. }
**Refer to Table 9-1, PDP-8/E & PDP-8IM Small Computer Handbook.

F-14

Omnibus signals

Part II
Table F-7 (Cont)
TM8-E Signals and Signal Functions
Signal

Origin

Function

*CB-3 INT RQST L

M8322

CB-3 INT RQST L is asserted by one of the following
conditions:
Bit error in the Command Register is a 1 and the SC-2
ERR lR flag is set.
Bit 5 in the Command Register is a 1 and the JOB
DONE (CB-3 MTTF) flag is set.

*1/0 PAUSE L

M8321

C LRCE L

TS03

LRC ERROR (C LRCE L) is set by the TS03 when a LPE is
detected by the Master System.

OC-2 LWCRL

M8321

OC-2 LWCR is asserted to load the WC Register when a 6701
instruction is executed by the program.

OC-2 LDBR

M8321

Load Data Buffer (OC-2 LDBR) is asserted when a 6707
instruction is executed by the program to transfer the contents
of the AC to the Data Buffer Register. This instruction also
sets CB-3 MTTF (JOB DONE).

MAO-MAll

Omnibus**

MAO through MAll are used to address 4096 possible
memory locations. During a data break, the CA Register
controls the MA lines to select a memory location for a data
transfer between memory and the DECmagtape.

CB-2 MAC ACC L

M8322

CB-2 MAC ACC is asserted when a BRK RQST is granted to
enable the data transfer and clear BRK RQST.

SC-2 NOT LAST XFER L

M8322

MDO-MDll

Processor

***

MSIRDISABL

M8322

****

CB-l OFFLINE L

M8322 and
M8321

CB-1 OFFLINE is asserted when OXXX is loaded into the
Function Register by a LFGR instruction and the selected
transport rewinds to beginning of tape and stops. The
transport must be manually reset to on-line condition.

SC-l PARITY ERROR L

M8323

The SC-1 PARITY ERROR flip-flop is set when an LRC, CRC,
or VPE error is detected by the selected tape transport.

*Refer to Table 9-1, PDP·8IE & PDP-81M Small Computer Handbook.
**Refer to Table 9-2, PDP-8 IE & PDP-8IM Small Computer Handbook.
***Refer to Table 94, PDP-8IE & PDP-81M Small Computer Handbook.
****Refer to Table 9-3, PDP-8IE & PDP-81M Small Computer Handbook.

F-15

Part II
Table F-7 (Cont)
TM8-E Signals and Signal Functions
Signal

Origin

Function

RE-l PEVN H

M8327

If RE-l PEVN is high, the TS03 generates and checks for even
parity; if it is low. the TS03 generates and checks for odd
parity. The level of RE-l PEVN is controlled by bit 3 of the
Command Register (when bit 3 is ai, RE-l PEVN is low).

*POWEROKH

Processor

POWER OK goes high when a PDP-8 power failure occurs and
generates a CB-3 CLR ALL to stop all transports and end any
operation occurring at the time of a power failure.

SC-l PRESET H

M8323

SC-l PRESET H is a 2.5 fJ.S pulse that is triggered by setting
the RE-l GO bit in the Function Register to a 1 if the selected
transport is ready (C TUR is true). RE-l PRESET H triggers
the RE-l SET pulse.

RE-l RCARL

M8321

Read CA Register (RE-l RCAR) is asserted when the 6713
instruction is executed by the program to transfer the contents
of the CA Register to the AC.

OC-l RDB L

M8321

Read Data Buffer (OC-l RDB) is asserted by an RDBR
instruction or by CB-2 MAC 1 H during a read data break to
transfer the contents of the Data Buffer Register to the data
lines.

RE-l RDBR L

M8321

Read Data Buffer Register (RE-l RDBR) is asserted when a
6717 instruction is executed by the program to ground OC-l
RDB L and transfer the contents of the Data Buffer Register
to the AC.

SC-l RECORD LENGTH
INCORRECT H

M8323

SC-l RECORD LENGTH INCORRECT is asserted and sets bit
6 in the Main Status Register if the record length differs from
the WC Register. The WC Register must be read by the
program to determine if the record was too short or too long.

RE-l REWIND

M8321

RE-l REWIND is asserted by the function decoders if a 1XXX
is loaded into the three most significant bits of the Function
Register.

RE-l RFSR L

M8321

RE-l RFSR is asserted when a 6716 instruction is executed to
transfer the contents of the Second Status Register and
Function Register to the AC.

OC-2 RMSR L

M8321

OC-2 RMSR is asserted when a 6714 instruction is executed
by the program to transfer the contents of the Main Status
Register to the AC.

*Omnibus signals.

F-16

Part II
Table F-7 (Cont)
TM8-E Signals and Signal Functions
Signal

Origin

Function

OC-2 RWCRL

M8321

OC-2 RWCR is asserted when a 6711 instruction is executed
by the program to transfer the contents of the WC Register to
the AC.

RE-1 SELO H
RE-1 SEL 1 H
RE-1 SEL 2 H

M8327

RE-1 SEL 0 through RE-1 SEL 2 are loaded into the three
most significant bit positions of the Command Register by an
LCMR instruction. These bits are used to select one of the two
transports for a data transfer operation (Table 7-1).

SC-1 SET H

M8323

SC-1 SET H is approximately a 5 J.1B pulse that is triggered by
setting the GO bit in the Function Register to 1. SC-1 SET H
is applied to the selected transport to start tape movement if
TUR is true (tape unit ready).

OC-2 SKIP L

M8321

The OC-2 skip line is grounded when one of the following
conditions exist:
SKEF instruction is executed and the SC-2 Error flag is
set.
SKCB instruction is executed and SC-1 CONTROL BSY
is not set.
SKTR instruction is executed and C TUR is asserted.
SKJD instruction is executed and the JOB DONE (CB-3
MMTF) flag is set.

CB-1 SPACE H

M8322

CB-1 SPACE H is asserted during space reverse or space
forward operation and continued until EaT, FMK, or WCOV,
is encountered. File Mark is read from the tape.

CB-1 SP FWD L

M8322

CB-1 SP FWD is asserted when 6XXX is loaded into the three
most significant bit positions of the Function Register. The
transport spaces forward the number of records specified by
the WC Register.

CB-1 SP REV L

M8322

CB-1 SP REV is asserted when 7XXX is loaded into the three
most Significant bit positions of the Function Register. The
transport spaces in reverse the number of records specified by
the WC Register.

F-17

Part II
Table F·' (Cont)

TM8-E Signals and Signal Functions
Signal

Origin

Function

SC-1 SELR L

M8323

Select remote (SC-1 SELR L) indicates to the control that the
selected transport is on -line.

OC-2 SBRM L

M8321

Set BRK RQST Maintenance (OC-2 SBRM) is asserted when a
6727 instruction is executed by the program to initiate one
single cycle data break.

SC-1 TURL

TS03 and
M8322

Tape unit ready (SC-l TUR L) is asserted when the selected
tape transport is ready.

RE-2 WCOL

M8327

Word count 0 (WCO) is asserted when the WC Registers read all
Os to indicate the data transfer is complete. RE-2 WCO is used
to generate CB·l WCOV (word count overflow).

CB-1 WCOV L

M8322

Word count overflow (RE-2 WCOV) is asserted when the WC
Register contains all Os to negate C WDR and end a data
transfer operation.

CB-1WR9L

M8322

Enables logic to apply 8 bits of data to the selected transport
during a write operation.

CB-1 WR 1st 7 L

M8322

Enables the logic to apply the six most significant bits of a
l2-bit data word from memory to the selected transport
during a write operation. Tracks 0 and 1 are Os in the Core
Dump Mode.

CB-1 WR 2nd 7 L

M8322

Enables logic to apply the six least significant bits of a 12-bit
data word to the selected transport during a write operation.
Tracks 0 and 1 are Os in the Core Dump Mode.

SC-1 WRS L

TS03

Write strobe (SC-l WRS) is asserted by C WRS from the TS03
when the selected transport is ready to write new data: C
WRS is a 100 ns pulse that is asserted once for each character
written on tape.

F-l8

Part II

APPENDIX G
SPARE PARTS

Table G-l lists the recommended spare parts for the TM8-E.

Table G-'
TMS-E Spare Parts
DEC Part Number

Description

10-00007
10-00042
10-00067
10-01610
12-09941
13-00204
13-00229
13-00275
13-00286
13-00293
13-00317
13-00443
13-00498
13-00534
13-01316
13-01401
13-01420
15-10015
19-05547
19-05575
19-05576
19-05578
19-05570
19-09004
19-09055
19-09056
19-09057
19-09058
19-09267
19-09485

Capacitor, 15 pF, 100V
Capacitor, 1000 pF, 100V
Capacitor, 618 pF, 35V
Capacitor, 0.01 J..L F, 100V
Connector, 40 pins
Resistor, 47n, "4W
Resistor, 1Don, 'Y4W
Resistor, 220n, 'Y4W
Resistor, 270n, "4 W
Resistor, 330n, "4W
Resistor, 470n, 'Y4W
Resistor, 417n, "4W
Resistor, 18 Kn, "4W
Resistor, 100 Kn, 'Y4W
Resistor, 8.2 Kn, "4W
Resistor, 750n, "4W
Resistor, 27n, 'Y4W
IC, DEC 4008
IC, DEC 7474
IC, DEC 7400
IC, DEC 7410
IC, DEC 7430
IC, DEC 7401
IC, DEC 7402
IC, DEC 7495
IC, DEC 74HOO
IC, DEC 74H 10
IC, DEC 74H21
IC, DEC 74H11
IC, DEC 380

G-l

Quantity

1
2
2
1
1
1
2
2
3
3

1
3
1
2
2
2
2
1
2
2

1
1
3
3

Part II
Table G-' (Cont)
TMS-E Spare Parts
DEC Part Number
19-09486.
19-09584
19-09667
19-09686
19-09704
19-09705
19-09712
19-09928
19-09929
19-09935
19-09937
19-09955
19-10035
19-10435
19-10651
19-10652

Description
IC, DEC 384
IC, DEC 8251
IC, DEC 74H74
IC, DEC 7404
IC, DEC 314
IC, DEC 8881
IC, DEC 8242
IC, DEC 7416
IC, DEC 7414
IC, DEC 8235
IC, DEC 74153
IC, DEC 7412
IC, DEC 74197
IC, DEC 74123
IC, DEC 74175
IC, DEC 74174

C-2

Quantity
2
1
2
1
3
1
1
2
2

Part II

APPENDIX H
IC DESCRIPTIONS

This appendix provides detailed descriptions of ICs used in the TMS-E. A detailed schematic plus a packaging diagram
with pin number assignments. and a truth table are provided on each of the following ICs:
DEC 74153
DEC 74174
DEC 74175
DEC 74197

H-l

Part II
DEC 741531C
The DEC 74153 IC is a Dual 4-Line to 1-Line Data Selector/Multiplexer (see below for truth table, logic diagram,
and pin numbers). The IC can be used in one of two modes, a 4-line to l-line multiplexer or a parallel-to-serial
converter. A strobe enable signal line is provided to select each of the input lines as an output. In the TMS-E, the
strobe lines are tied together to allow the selection of signals from the MD lines, Data Bus, or data read from the
T503 Transport.

CONTROL INPUT
E

STROBE

OUTPUT

Y
A

LOW

HIGH

LOW

HIGH

LOW

HIGH

DON'T CARE
TRUTH TABLE

LOW

HIGH

LOW

(EACH HALF)

Vee

PIN LOCATOR
(TOP V lEW 0 F r C)
8[-0138

DEC 74153 IC (Sheet 1)

H-2

Part II

CONTROL {
INPUTS

F
OUTPUTS

2B
DATA
INPUTS

STROB E - - - - - - - { " ' I

LOGIC DIAGRAM

DEC 74153 IC (Sheet 2)

H-3

Part II
DEC 741741C

The 74174 IC contains six flip-flops with single rail output with a buffered clock and direct clear input. Each
flip-flop has an individual data input. The truth table and logic diagram are shown below.

Input

Outputs

tn+l
A

TRUTH TABLE

D
H
L

H
L

L
H

INPUT
tn

(3)

OUTPUTS
t n +1

H
L

L
H

tn : Bit time before
clock pulse.
t n +1 :Bit time ofter
clock pulse.

..-----<~ CLOCK

CLEAR

(4)

(5)

°B

CLOCK
CLEAR

C (6)

(7) Oc

CLOCK
CLEAR

(11)

o O--+---+--f DO

(10)

CLOCK
CLEAR

E (13)

.--t----1~ CL OCK

CLEAR

(14)

F O--+---+--f OF

Pin (16)= VCC. Pin (B)= GND

11- 1112

DEC 74174 IC

Part II
DEC 741751C

The 74175 IC contains four flip-flops with double rail outputs with a buffered clock and direct clear input. Each
flip-flop has an individual input. The truth table and logic diagram are shown below.

TRUTH TASLE
INPUT
tn

OUTPUTS
tn + 1

H
L

L
H

tn =Sit time before
cloc k pulse.
tn1"1 = Sit time ofter
clock pulse.

r---~CLK

<>--+--+---1 DS

A
CLEAR

(5)

(7)

CLK Os
CLEAR

(12)

(10)

~-+~nCLK Oc
CLEAR

~(~_13"";')-+-~_--1

~--.e-----+~nCLK

U'"

CLOCK

(15)

D
CLEAR

CLEAR O----I::lI

Pin (16)= Vce. Pin (8) =GND

11-1113

DEC 74175 IC

H-5

Part II
DEC 741971C

The DEC 74197 IC is a pre-settable binary counter that can also be used as a latch. The IC consists of four
dc-coupled master-slave flip-flops connected to provide a divide-by-2 counter and a divide-by-8 counter. The logic
diagram, a truth table, and a pin locator are shown in the 74153 description.
The 74197 can be used in anyone of three modes, viz; the divide-by-2/divide-uy-8 mode, requiring no external
interconnection or IC pins, the latch mode, and the binary counter mode. If the first listed mode is used, an input at
pin 8 is divided by 2 by flip-flop A and the result is taken from pin 5; an input at pin 6 is divided by 8 by flip-flops
B, C, and D and the result is taken from pin 12. Transfer of information to the outputs takes place on the
negative-going (trailing) edge of the clock pulse.
To use the latch mode, enter data at the four data inputs (pins 4,10,3, and 11) and enter a strobe pulse at pin 1.
The output pins, 5, 9, 2, and 12, respectively, will follow the inputs when pin 1 is low, but will remain unchanged
when pin 1 is high and the clock inputs are inactive.

Count
Clock 1 Input

Output
OC OB

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

COUNT/LOAD

DATA C

Vee

CLEAR

DATA 8

GND

CLOCK 1

8E- 0372

DEC 74197 IC (Sheet 1 of 2)

H-6

Part II

DATA A - - - - - - - - - - - 1
COUNT/LOAD ------~
CLEAR

-....----0/
t----QA

DATA

8--------+---i-""----~

1---........-Q8

DATA C - - - - - - - - + - - - i f - - - t

DATA D - - - - - - - - + - - - - t

I-----QD

8E-0373

DEC 74197 IC (Sheet 2 of 2)

H-7

Part III

APPENDIX I
TRANSPORT SIGNAL DESCRIPTIONS
AND INTERFACE INFORMATION

1.1 INPUT SIGNALS
All commands from and to the input/output connector are preconditioned by loading the machine and placing it
on-line using the front panel controls. The next commands set up the recorder.

I.l.1 Setup Commands
Signal

Pin No.

Description

Transport Select
(SLT)

PI-J

A level that when true enables all the adapter drivers and receivers
in the transport, thus connecting the transport to the controller.
The transport must also be on-line, and SLT must be true for the
entire write sequence (until tape motion stops). The SLT level
may be removed to disconnect the machine from the system. The
machine will remain in the last condition established by SWS.

Data Density Select
(DDS)
(Dual Density Only)

PI-D

Used when the TRANSPORT DENSITY SELECT switch is in the
remote position. When true, this level selects the high read
density (dual density).

Pin No.

Description

Overwrite
(OVW)
(Optional)

PI-B

A level that when true conditions appropriate circuitry in the
transport to allow updating (rewriting) of a selected record. The
transport must be in the write mode of operation to utilize the
OVW feature.

Synchronous Forward
Command
(SFC)

PI-C

A level that when true, with the transport ready and on-line,
causes tape to move forward at the specified speed. When the
level goes false, tape motion ramps down and ceases.

Synchronous Reverse
Command
(SRC)

PI-E

A level that when true, with the transport ready and on-line,
causes tape to move in a reverse direction at the specified speed.
When the level goes false, tape motion ceases. If the load point
marker is detected during an SRC, the SRC will be terminated. If
an SRC is given when the tape is at the load point, it will be
ignored.

I.l.2 Tape Motion Commands
Signal

I-I

Part III
Signal
Rewind Command
(RWC)

Pin No.

Description

PI-H

A pulse input will rewind the tape past the load point and stop.
The transport will then initiate a load forward sequence and
return the tape to the load point marker. This input will be
accepted only if the load point output is false. The transport may
be taken off-line while rewind is still in process. Rewind will
continue normally.

Pin No.

Description

PI-K

A level that must be true at the leading edge of an SFC (or RUN
and FWD) when the write mode of operation is required, and
must remain true for a minimum of 10 JlS after the leading edge
of the SFC (or RUN and FWD). SWS is sampled at the leading
edge of the SFC or SRC (or RUN and FWD), toggling the
read/write flip-flop to the appropriate state. Internal interlocks in
the 9800/9700 will prevent writing in the reverse direction, when
the write enable ring is missing, when the tape unit is off-line,
when loading to a load point, and during a rewind.

1.1.3 Write Commands
Signal
Set Write Status
(SWS)

Write Data Inputs
WDP
WOO
WDI
WD2
WD3
WD4
WDS
WD6
WD7

P2-L
P2-M
P2-N
P2-P
P2-R
P2-S
P2-T
P2-U
P2-Y

These are levels that if true at WDS time will result in a flux
transition being recorded on tape (transport is in the write mode).
Data inputs must have settled 0.5 J.1S before the leading edge of
the WDS pulse and must remain quiescent 0.5 J.1S beyond the
trailing edge of the WDS pulse. The CRCC is written by providing
the correct data character together with a WDS four character
times after the last data character of the record.
The LRCC is written using the WARS signal. The LRCC can also
be written by providing the correct data character together with a
WDS. If the LRCC is written (DATA-WDS) in this manner, a
WARS should be given one character time after tpe LRCC to
ensure proper IRG erasure in case of data input error.

Write Data Strobe
(WDS)

P2-A

A pulse of 2 JlS nominal width for each character to be written.
Writing occurs on the leading edge of the WDS. WDS may be a
1 JlS minimum, 3 J.1S maximum pulse. Data inputs must have
settled for at least 0.5 J.1S before the leading edge of WDS and
remain quiescent for at least 0.5 JlS beyond the trailing edge.

Write Amplifier Reset
(LRC PLS)

P2-C

A pulse of 2 J.1S nominal width that, when true, resets the write
amplifier circuits on the leading edge. The purpose of this line is
to enable writing of the longitudinal redundancy check character
(LRCC) at the end of a record. This ensures that all tracks are
properly erased in an interrecord gap (IRG).
The leading edge of the WARS pulse should be eight character
times after the leading edge of the WDS associated with the last
data character in the block (four character times after the CRCC
is written).
1-2

Part III
1.1.4 Read Commands
A read-after-write machine will always have read selected. When write is selected (SWS), the data just written will be
read back using a high threshold level on the read amplifiers. When SWS is false, the normal threshold is applied to
the read amplifiers.
Signal
Automatic Clipping
Level Disable
(ACLD)

Pin No.

Description

P3-6

When true, this level overrides the automatic clipping level
electronics and holds the read electronics in the normal clipping
level.

1.1.5 Shutdown Commands
The use of a given magnetic tape unit may be terminated by an off-line command. Once this command is given, the
tape unit may be returned to an adapter command only by operating the front panel ON LINE switch.
Signal
Off-Line Command
(OFFC)

Pin No.

Description

PI-L

A level or pulse (minimum width 2 p.s) that resets the on-line
flip-flop to the zero state, placing the transport under manual
control. It is gated only by SELECT in the transport logic,
allowing an OFFC to be given while a rewind is in progress. An
OFFC should be separated from a rewind command by at least
2 p.s.

1.2 INTERFACE OUTPUT SIGNALS
All output signals are enabled only when the tape transport is on-line and selected.
1.2.1 Status Outputs
Signal

Pin No.

Description

On-Line
(ONL)

PI-M

A level that is true when the on-line flip-flop is set. When true,
the transport is under remote control. When false, the transport is
under local control.

Transport Ready
(RDY)

PlOT

A l~vel that is true when the tape transport is on tape; that is,
when the initial load sequence is complete and the transport is
not rewinding. When true, the transport is ready to receive a
remote command.

High Density Indicator
(HDI)
(Dual Density Only)

PI-F

A level that is true only when the high-density mode of operation
is selected.

File Protect
(FPT)

PlOP

A level that is true when a reel of tape without a write enable ring
is mounted on the transport supply (or file) hub.

Write Enable
(WEN)

PI-S

A level that is true when a reel of tape with a write enable ring is
mounted on the transport supply (or file) hub. Opposite of file
protect.

1-3

Part III
Pin No.

Description

Load Point
(LDP)

PI-R

A level that is true when the load point marker is under the
photosensor and the transport is not rewinding. After receipt of
an SFC, the signal will remain true until the load point marker
leaves the photosense area. (Circuitry using this output should
not use the transitions to and frJm the true state.)

Tape Running
(RNG)

PI-V

This is a level that is true when tape is being moved under capstan
control and remains true until tape motion has ceased. (Includes
forward, reverse, an -1 rewind tape motion.)

End-of-Tape
(EDT)

PI-U

A level that is true for the duration of the EDT marker. (Circuitry
using this output should not use the transitions to and from the
true state.)

Rewinding
(RWD)

PI-N

A level that is true only when the transport is engaged in a rewind
operation or returning to the load point. (Goes true
approximately 5 J.lS after a rewind command is given.)

Signal

1.2.2 Read Outputs
Read outputs are present at all times in tape units when a dual gap head is used (read after write). The high threshold
level is selected internally when SWS is selected. In a read/write tape unit (single-gap head), read outputs are
inhibited when SWS is true.
Signal
Read Data Strobe

Pin No.

Description

P3-B

A pulse of 2 J..lS minimum width for each data character read from
tape. Although the average time between two read data strobes is

rDn<;:\
\.I.'-.LJl...I'

71 (sec)

= [lis-d)]

where
s = tape speed in inches per second
d = density characters per inch
the minimum time between consecutive read data strobes is less
than this figure due to skew and bit crowding effects. A
guaranteed safe value for the minimum time is 1/2 7 1.
Read Gap Detect
(RGAP)

P3-N

A level that is true approximately nine character spacings after
the last data byte, and remains true until the first data byte of the
subsequent data block.

NOTE
This level will be true whenever tape motion is at rest.

1-4

Part III
Signal
Read Da ta Level
RDP
ROO
RDI
RD2
RD3
RD4

RD5
RD6
RD7

Pin No.

P3-1
P3-3
P34
P3-8
P3-9
P3-1
P3-1
P3-1
P3-1

Description
Nine staticisers are provided, which act as a one-stage read
deskewing buffer. Each output is a level that changes to the
appropriate state approximately 1 JlS before the read data strobe
and remains in that state until 1 JlS before the next read data
strobe. Data lines return to false condition in the IRG when tape
motion stops, regardless of the last character read.
It is recommended that read data strobes and the read gap detect
be ignored during the first read or write operation from load
point for T2 ms after the load point output goes false, where
T2 = 1000/s (s = speed of tape unit).

The read gap in a read-after-write tape unit is downstream from
the write gap. Thus-when the write gap is initially energized, the
read gap may detect a flux change depending on the initial state
of magnetism on the tape.
1.3 SUMMARY OF INTERFACE CHARACTERISTICS
Figure 1-1 shows the location of connectors and pin numbers with signal names.

1-5

Part III

:IA

,. .,,!'TI I

v
II

J3 READ

A Jl CONTROl V

0 (@
11-3059

INPUT
OUTPUT
WRITE CONNECTOR J2
Active
A
B
C
0
E
F
H

J
K
L
M
N
P
R
S
T
U
V

Ground

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

17
18

CONTROL CONNECTOR J1 (Cont)

Signal

Mnemonic

Active

Ground

Write Data Strobe
N. C.
Write Amplifier Reset
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Write Data Channel P
Write Data Channel 0
Write Data Channel 1
Write Data Channel 2
Write Data Channel 3
Write Data Channel 4
Write Data Channel 5
Write Data Channel 6
Write Data Channel 7

REC

L
M
N
P
R
S
T
U
V

10
11
12
13
14
15
16

LRC PLS

WOP
WOO
WD1
WD2
WD3
WD4
WD5
WD6
WD1

1
2
3
4
5
6
7
8

2
3
4
5
6
7
8

Spare
Overwrite (Not Used)
Synchronous Forward
Data Density Select
Synchronous Reverse
Data Density Indicator
Rewind Command
Select
Set Write Status

Figure 1-1

OVERWRITE
FWD MOT
DDS (Not Used)
REV MOT
001 (Not Used)
RWND PLS
SEL DRIVE (1 :0)
WRE LTCH

17
18

Off-Line Command
On-Line Command
Rewinding
File Protect
Load Point
Write Enable
Transport Ready
End-of-Tape
Tape Running

Mnemonic
OFF LINE PLS
DRIVE (0:1) ON LINE
RWNDG
WRLCK
LOAD POINT
WRITE ENB
XPRT ROY
END OF TAPE
TAPE RUNNING
STATUS (Not Used)

READ CONNECTOR J3

CONTROL CONNECTOR J1
A
B
C
0
E
F
H

Signal

10
11
12
13
14
15
16

17
18

A
B
C
0
E
F
H

J
K
L
M
N
P
R
S
T
U
V

Summary of Adapter Characteristics

1-6

Read Data Channel P
Read Data Strobe
Read Data Channel 0
Read Data Channel 1
Not Used
Auto Disable (Not Used)
Not Used
Read Data Channel 2
Read Da~Channel 3
Not Used
Not Used
Gap Detect
Not Used
Read Data Channel 4
Read Data Channel 5
Not Used
Read Data Channel 6
Read Data Channel 7

RDP
RD STRB
ROO
RD1

RD2
RD3

RD4
RD5
RD6
RD7

Part III

APPENDIX J
DEC/VENDOR TS03 TRANSPORT
PART NUMBERS

Vendor Number

DEC Number

154-0035-001
190-1509-001
190-2399-010
190-2641-001
190-2747-001
190-3631-005
190-3645-002
190-3841-001
190-3842-001
190-3843-001
190-3844-001
190-3848-001
190-3849-001
190-3860-001
190-41 78-004
190-4179-004
190-4220-001
190-4306-001
190-4352-001
190-4845-001
192-9900-001
190-4448-001
190-4441-001
190-3468-001
190-264 7-002
190-2484-001
128-0091-001
125-0030-006
190-4218-001
190-4438-001
151-0057-001
190-1139-001
190-1138-001
151-0038-001
125-0006-001
125-0015-001
125-0008-103
125-0040-001
154-0001-001

29-21904
29-21905
29-21906
29-21907
29-21908
29-21909
29-21910
29-22269
29-21911
29-21912
29-21913
29-21914
29-21915
29-22268
29-21916
29-21917
29-21918
29-21919
29-21920
29-21921
29-21922
29-21923
29-21924
29-21925
29-21926
29-21927
29-21928
29-21929
29-21930
29-21931
29-21932
29-21933
29-21934
29-21935
29-21936
29-21937
29-21938
29-21939
29-21940

Description
Tape Path Alignment Tool
Tape Guide
Head Assembly
File Protect Assembly
Tape Cleaner Assembly
Read Preamplifier Module
Ramp Generator Module
Control Terminator Module
Interface Control Module
Tape Motion Control
Sense Amplifier/Driver Module
Write Amplifier (4-Channel) Module
Write Amplifier (5-Channel) Module
Data Terminator Module
Quad Read Amplifier Module
Read Amplifier/Clip Control Module
Mag Pot PLB
Servo Preamplifier Module
Voltage Regulator PCB
Timing Delay Module
Test Panel
LED Display
Voltage Regulator/Servo Power Amplifier
Module Extender
Tension Roller
Capstan Motor
Spring
O-Ring
Mag Pot
Reel Motor
Switch
Broken Tape Sensor
Tape Photo Sensor
Switch
Reel Drive Belt (Supply)
Reel Drive Belt (Take-Up)
Bearing
Bearing
Capstan Puller

J-l

Part III

Vendor Number

DEC Number

190-4474-601
148-0114-001
148-0108-001
148-0122-001
151-0802-002
115-3625-199
115-3610-449
198-0100-001
148-0121-001
148-0075-001
148-0053-001
148-0102-003
148-0102-004
198-0133-030
198-0133-015

29-21941
29-21942
29-21943
29-21944
29-21945
29-21946
29-21947
29-21964
29-10334
29-19037
15-10008
15-10712
15-10853
90-07217
90-08388

Description
Transformer
LED Fairchild FLV-102
Diode MR751
Power Transistor MJ802
Fuse Holder
Capacitor (18K MFD or larger)
Capacitor (40K MFD or larger)
Hub Repair Kit
Power Transistor MJ4502
Transistor 2N4910
Transistor 2N3055A
Transistor MJ -900
Transistor MJ-1 000
Fuse 3 A-3 AG (l15 V)
Fuse 1.5 A-3 AG (230 V)

J-2

Reader's Comments

TS03/TM8-E
DECmagtape System
Maintenance Manual
EK-T3TM8-MM-OOI

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Fold Here -

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-- -

FIRST CLASS
PERMIT NO. 33
MAYNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation
Technical Documentation Department
146 Main Street
Maynard, Massachusetts 01754

~D~DDmD WORLDWIDE SALES AND SERVICE

DIGITAL EQUIPMENT CORPORATION

MAIN OFFICE AND PLANT
Maynard, Massac!-"jsetts, U.S A 01754' Telephone From !vIeiro",,, '-<i" [",,:>1(// 6~6-8600. f:-,ewhere (617)-897-5111
nVX 7i~-347·0?12 CaGle OiGlT,j,L MA'rr,.' Telex. 94-8457

DOMESTIC
NORTHEAST

MID-ATLANTIC (con!.)

WEST

CENTRAL (cont.)

REGIONAL OFFICE

235 Wyman Street. Waltham. Mass 02154

310 S?r"J:-,el . . ."'ay. Sunr.yvale California 94086
Teleph::me (408)·735-9200
Dataphon(>' 408-735-1820

Telephone: (617)-890-03300310

Dataphone 617-890-3012 or 3013

Ann Arbor. Mlc,",lgan 48103
Dataphone 313-769-9883

NEW YORK

ARIZONA

Dataphone

313-557-3063

Phoenl.(
4358 East
Telephone

PhoeniX, Arizona 85040
Dataphone 602-268·7371

CALIFORNIA
Santa Ana
2110 S A'lne Street. Santa Ana. California 92704
Telephone (714}-979-2460
Oata~hone 714-979-7850

MID-ATLANTIC
COLORADO
Dataphone' 513-298-4724

Maryland

FLORIDA

301 AS9·7900 X53

Orlando
SUite 130

Drive, Orlando. Florida 32809

Telephone

Dataphone 305-859-2360

7901 E Bellevue Avenue
SUite 5, Englewood. Colorado 80110
Telephone (303)-770-6150
Dataphone

303-770-6628

CENTRAL
New Mexico 87112
Dataphone 505-294-2330

100
Pittsburgh. Pennsylvania 15235
Dataphone 412-824-9730

Dataphone 305-859-2360

OREGON

NORTH CAROLINA
Durham/Chapel Hill

Portli?f1d
SUite 168
5319 S W Westgtlte Drive. Portland, Oregon 97221

Executive Park

Telephone (503)·297·3761/3765

3700 Chapel HJII Blvd

Durham North Carolina 27707
Telephone (919)-489-3347
Dataphone 919-489-7832

Texas 75234
Dataphone

214-620-2061

Monterey Park Houston. Texas 77036
Te!ephone (713)-777-3471
Dataphone

713-777-1071

HOUSTON
6656 Hornwood Drive
WASHINGTO~

Bellevue
13401 N E Bellevue, Redmond Road. SUite III
Bellevue. Washington 98005
Telephone ~206)-545-405a!455-5404
Dataphone

206-747-3754

INTERNATIONAL
EUROPEAN HEADQUARTERS

UNITED KINGDOM (coni.)

ISRAEL

JAPAN

Digital Equipment Corporation International Europe

READING

DEC Systpms Computers ltd

81 route de l'Alre
1211 Geneva 26. SWitzerland
Telephone 427950
Telex 22683

Fountain House Butts Centre
Reading RGl 70N Enqland
Telephone (0734)-58355')
Telex

TEL AVIV

Digital Equipment Corporation International
Kowa BulldJ!1g No. 16 - Annex, First Floor
9-20 Akasah.a :-Chome
Mlnato-Ku Tckyo 107. Japan
Telephone 586-2771
Telex J-26428
Rikel Trading Co. Ltd (sales only)
Kozato-Kaikan Bldg
"10 18·14 Nls,",lshlmbashl l·Chome
MJnflto-Ku, Tokyo, Japan
Telephone 5915246
Telex 781-4208

8483278

S,.lIte 103, Southern Habakuk Street
Tel AVIV, Israel

Telephone (03) 443114/440763

FRANCE
Digital Equipment France
Centre Slllc - Cldex L225
94533 Rung's, Frarce
Telephone 687-2333
Telex

Telex 922·33-3163

NETHERLANDS
Digital Equipment N V

CANADA

THE HAGUE

26840

OIQltal EqUipment of Canada, ltd

Sir Winston
RljswljklThe
Telephone 94

CANADIAN HEADQUARTERS

P
Sox 11500
Ottawa, OntariO Canada
Telephone

Digital Equipment N V IS A
Telex

212·32882

GERMAN FEDERAL REPUBLIC
Digital Equipment GmbH

PUERTO RICO

K2H BKB

BELGIUM

(613)-592-5111

TWX 610-562-8732

TORONTO

BRUSSELS
108 Rue D'Arlon
1040 Brussels. Belgium
Telephone 02-139256

25SO Goldenridqe Road. Mlssissauga, Ontario

Te:ephone (416)·2709400
Telex

TWX 61O·492·711B

ARGENTINA

25297

BUENOS AIRES

MUNICH
8 Muenchen 13, Wallenstelnplatz2
Tulephone 081'·35031
Telex 524-226

Coasin SA
Vlrrey del Plno, 4071, Buenos Aires
Telephone 52-3185
Telex 012-2284

SWEDEN
DI~:lItal Equipment AB

STOCKHOLM
Englundavagen 7.17141 Saine Sweden
Telephone 9a 1390
Telex 17050
Cable Digital Stockholm

BRAZIL
RIO DE .'4NEIRO -

Dlglta! Equipment Corp. A/S

OSLO

SAO PAULO

Trondhelmsvelen 47
Oslo 5, Norway
Telephone 02/683440

Telex' 19079 DEC N

'46 ~.Ao1ln Street Maynard. Massachusetts 01754
Tt'iephone (617) 897-5111
From Metropolitan Boston, 646-8600

Digital Equipment Aktlebolag

COPENHAGEN
Hellerupveq 66
;:>900 Hellerup Denmark

AUSTRIA
D:q,t<l! Eqllipment Corporation Ges m b H

HELSINKI

U K

ltd

~EADQUARTERS

FountAin HOllse Butts Centre
Read.r q RGl 70N EnqlClnd
Telephone (0734)S23555
Tel.f'v

TWX

710347·0217/0212

Cable

DIGITAL MAYN
94-8457

Telex

FINLAND

MMIAhilferstrilsse 136. 1150 Vienna 15, Austria
Telephone 8'55186

UNITED KINGDOM

GENERAL INTERNATIONAL SALES
REGIONAL OFFICE

DENMARK

VIENNA

Ambnex S A
Rua Ceara. 104 2 e 3 anda(f~s ZC - 29
RIO De Janeiro - GB
Telephone 264-7406/0461/7625

NORWAY

DIf)ltill Equipment Co

Dlq,tal EqUipment Corporation De Puerto RICO
407 del Parque Street
Santurce P.Jerto RICO 00912
Telephone (809)-723·8068/67
Telex 385-9056

Ambrrex SA
RL3 Tuol. 535
Sao Paulo - Sf"
Telephone 52-780611870, 51.0912

PORTO ALEGRE -

Rua Coronel Vicente 421/101
Pc r\:) Alegre - AS
Telephone 24-7411

CH'LE
SA"IT,,' GO

Digital Equipment AB

Coasln Chile ltda. (sales 'nly)
Casillfl 14588. Correc ~5
Telephone 396713
Ca'Jle COACHIL

Tltlsm8antle 6
SF·D0710 Helsinki 71
Telephone (090) 370133
CClbie Digital Helsinki

INDIA
BOMBAY

SWITZERLAND
8483278

Digital Equipment Corpor?t.on S A

GENEVA
20 OU;]I Ernest Anser~pt
BOlte Postale 23.1211 Geneva 8. SWitzerland
Telephonp No 022 2C 4C 2C <lnd 2C ')C 92 <Ll"'d 2C 6e 93
Telex 289201

Hlndltron Computers Pvt Ltd
69.'A 'L laqmohandas Mdrg
Bcmbay-6(WB) India
Tf':lerhone 38-1615 36-5344
Cable TEKHIND

Telex 011·2594 Plent\l

'.~EXICO
MEX'CO CITY
Mex tek SA
Eugenia 408 Deptos 1
Apdo Postal 12-1CP
MeXICO 12. 0 F
Tefephon~ (90S) 53$·09-10

ITALY

PHILIPPINES
MANILA
l'lli
Telex

843-33615

SPAIN
Digital Equipment Corporation ltd

VENEZUELA

MADRID
AI,"'IO lr>qenlerClS S A
Teleohone 21')3543
~.1:1r'ch,ster

M3? 9P-1-1

TI'lp"( 668666

printed in U.S.A.

Enr,q,.e Larreta 1:?
Telex 27249

Stanford Computer Corpor.::!,on
POBox 1608
416 DasrnMma< St M<'lrl.!a
Tel~pt'oOne 49·S'J·96
Telex 742·0352

Mzldfld 16

Gr8f1(luxer 76 Barcelona 6

CARACAS
Coas,'l. C A
Apartado 50919
Sabana Gr8nck No 1 Car8cas 105
Telephone 72·8662 72·9637
Cable !~,STRUVEN