Digital PDFs

EK-8A002-MM-002

November 1976

606 pages

Original

49MB

Document:	PDP-8/A Miniprocessor Users Manual
Order Number:	EK-8A002-MM
Revision:	002
Pages:	606
Original Filename:

OCR Text

1st Edition, November 1975
2nd Printing (Rev), December 1976

Copyright @ 1976 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual,.
Printed in U.S.A.

This document was set on DIGITAL'S DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-10
DECSYSTEM-20

DECtape
DECUS
DIGITAL
MASSBUS

PDP
RSTS
TYPESEiT-8
TYPESEiT-11
UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION AND DESCRIPTION
SYSTEM DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
KC8-AA Programmer's Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Limited Function Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
MM8-A Core Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
MS8-A Readmrite Semiconductor Memory (RAM) . . . . . . . . . . . . . . . . . . 1-8
MR8-A Read Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
MR8-FB Reprogrammable Read Only Memory (PROM) . . . . . . . . . . . . . . . . 1-9
G8016 Power Supply Regulator Module . . . . . . . . . . . . . . . . . . . . . . . . 1-9
G8018 Power Supply Regulator Module . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Option Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
DKC8-AA I10 Option Board (M8316) . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
KM8-A Extended Option Board (M8317) . . . . . . . . . . . . . . . . . . . . . . . 1-10
Peripheral Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
CONSOLE OPERATION
Limited Function Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
Programmer's Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Entering Data From the Programmer's Console . . . . . . . . . . . . . . . . . . . . 1-10
Examining Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Entering Data in Memory

CHAPTER 2

INSTALLATION AND ACCEPTANCE TEST
SITE CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Power Source
I10 Cabling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Fire and Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
UNPACKING INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
PACKINGINSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
BA8-C Chassis Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Other PDP-8/A Chassis Assemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PDP-8/A BASIC SYSTEM COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Chassis Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Expansion Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
PDP-8/A Module Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
KK8-A Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . 2-14
MS8-A Readmrite Random Access Memory (RAM) . . . . . . . . . . . . . . . 2-16
MR8-A Read Only Random Access Memory (ROM) . . . . . . . . . . . . . . . 2-16
. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
MM8-AA 8K Core Memory
MM8-AB 16K Core Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
DKC8-AA 110 Option Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
KM8-A Extended Option Board . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
. . . . . . . . . . . . . . . . . . . . . 2-30
Semiconductor Memory Power Supply
Core Memory Power Supply Regulator
. . . . . . . . . . . . . . . . . . . . . 2-32
Limited Function Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
KC8-AA Programmer's Console . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

iii

CONTENTS (Cont)

EMA<0:2>L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
MA<0:11>L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Memory Data and Direction Control .
13 Lines . . . . . . . . . . . . . . . . . . . . 3-10
MD<0:11>L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
MD DIR L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Data Bus .
12 Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
I10 Control Signals .
10 Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
I10 PAUSE L .
Pin CD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
INTERNAL I10 L .
Pin CL1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
SKIP L .
Pin CS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
INT RQST L .
Pin CP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
C<0:2>L .
Pins CE1 (CO L); CHI (C1 L); CJ1 (C2 L ) . . . . . . . . . . . . . 3-12
BUS STROBE L .
Pin CK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
NOT LAST XFER L .
Pin CL1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
INITIALIZE H .
Pin CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
DMA Control Signals .
8 Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
BRK IN PROG L - Pin BE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
CPMA DISABLE L .
Pin CU1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
. . . . . . . . . . . . . . . . . . . . . . . . . 3-14
.
MS, IR DISABLE L Pin CV1
MA, MS LOAD CONT L .
Pin BH2 . . . . . . . . . . . . . . . . . . . . . . . 3-14
BREAK DATA CONT L .
Pin BK2 . . . . . . . . . . . . . . . . . . . . . . . 3-14
OVERFLOW L - P i n BJ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
BK CYCLE L .
Pin BL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
RUN L .
Pin BU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Timing Signals .
9 Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
CPU STATE .
6 Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Major State Lines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
IR<0:2>L
Memory Timing Signals .
5 Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
. . . . . . . . . . . . . . 3-16
SOURCE H .
Pin AL2, and RETURN H .
Pin AR2
WRITE H .
Pin AS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
INHIBIT H .
Pin AP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
STROBE H .
Pin AM2
Miscellaneous Signals .
18 Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
IND1 L .
Pin CU2, and IND2 L .
Pin CV2 . . . . . . . . . . . . . . . . . . . 3-16
MEM START L .
Pin AJ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
STOP L .
Pin DS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
LINK L .
Pin AV2
LINK LOAD L .
Pin CS2, and LINK DATA L .
Pin CR2 . . . . . . . . . . . 3-17
F SET L - Pin DP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
USER MODE L .
Pin DM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
INT IN PROG H .
Pin BP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
LA ENABLE L .
Pin BM2, and KEY CONTROL L .
Pin DU2 . . . . . . . . . 3-18
PULSE L A H - P i n DR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
ROM ADDRESS L .
Pin AU2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
NTSSTALL L - Pin BR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
SW .
Pin DV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
POWER OK H .
Pin BV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
'

CONTENTS (Cont)
Page

RES .
Pin BS2
Special Signals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Time Pulses and Time States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Relationship Between CPU and Memory Timing . . . . . . . . . . . . . . . . . . . . 3-22
Basic I10 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Expanded I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Data Break Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Data Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Final Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
CPU Major States
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
IR (FETCH Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Timing Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
ASYNCHRONOUS SIGNALS, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
SPECIAL SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
ELECTRICAL CHARACTERISTICS AND INTERFACING . . . . . . . . . . . . . . . . 3-25
Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Bus Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Driving the Omnibus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
DRIVE AVAILABLE FOR PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
RECEIVERS AND LOAD RELIEF TECHNIQUES . . . . . . . . . . . . . . . . . . . . . 3-28
INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
Programmed I/O Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
Flag Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
I10 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
InputIOutput Timing for Programmed I10 Interfaces . . . . . . . . . . . . . . . . . 3-33
PROGRAM INTERRUPT TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . 3-33
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
Data Break Interface Ex$ample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
Data Break Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
TH REE-CYCLE DATA BREAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
GENERAL CAUTIONS REGARDING INTERFACE DESIGN . . . . . . . . . . . . . . . 3-38
TRANSMISSION LINE EFFECTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
EXTERNALBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
Positive I10 Bus Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
The Nature of the External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-40
External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
BAC 00-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
AC 00-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
BMBOO. 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.41
BIOP 1.2. and 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
BTS1. BTS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

CONTENTS (Cont)
Page
BRUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
AC CLEAR
SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
B INITIALIZE 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
DATA 00- 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
B BREAK
DATA OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
DATA ADD 00-1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
BRK RQST
ADD ACCEPTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
MB INCREMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
CA INCREMENT INH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3 CYCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
WC OVERFLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
EXT DATA ADD 0-2
B INITIALIZE 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43

CHAPTER 4

CENTRAL PROCESSOR UNIT
CENTRAL PROCESSOR UNIT. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . 4-1
TIMING GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Power OnIRun Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Timing Register Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
CPU Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Memory Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
I10 Transfer Stall Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Memory Stall Logic
FRONT PANEL OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Limited Function Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Programmer's Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Clock Timing Logic
.
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Register Logic
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Multiplexer Logic
RegisterIMultiplexer Gating Logic Timing . . . . . . . . . . . . . . . . . . . . 4-27
. . . . . . . . . . . . . . . . . . . . . . 4-30
ADDRSIDISP Readout Circuit Logic
Function Button Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
DISP Button Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
. . . . . . . . . . . . . . . . . . . . . . . . . . . .4-39
THIS. HLT. BOOT Logic
Console Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
INSTRUCTION DECODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Instruction Register Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
Major State Register Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-46
. . . . . . . . . . . . . . . . . . . . . . . . . . . .4-49
DATA ENAIDATA CMP Logic
.
.
.
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
Address Update Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51
Major Register Load Signal Logic
.
.
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . .4-53
AC Register Control Logic
MAJOR REGISTER GATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Page Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
Carry In Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-59

CONTENTS (Cont)
Page

4.5.3
4.5.4
4.6
4.6.1
4.6.2
4.6.3
4.6.4

Skip Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63
Link Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
I/O TRANSFER LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67
Programmed I/O Transfer Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67
Processor IOT Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67
Program Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73
Data Break Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73

CHAPTER 5

MEMORY OPTIONS
SECTION 1
MR8-A READ ONLY MEMORY (ROM)
MR8-A READ ONLY MEMORY (ROM) DESCRIPTION . . . . . . . . . . . . . . . . . . 5-3
MR8-A Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
M R8-A Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Timing and Control
Input and Output Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Programming Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Preparation ofthe PaperTape . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Blasting
DETAILED LOGICDESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Addressing Block Diagram Description . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Field and Size Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
Chip Select Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
The 13th Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Timing and Control
Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Control Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Sequence of Control Operations . . . . . . . . . . . . . . . . . . . . . . . . . .5-16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-16
Initial Conditions
Single Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Memory Data and Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Memory Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Address and Chip E:nable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Memory Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Data Transfer Lines
Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
M R8-A SWITCH LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19

SECTION 2
RANDOM ACCESS MEMORY (RAM)
SEMICONDUCTOR RANDOM ACCESS MEMORY (RAM-MS8-A) DESCRIPTION . . . . 5-21
Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
MS8-A Specifications

viii

CONTENTS (Cont)
Page

...............................
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..................................
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FUNCTIONALDESCRIPTION
5-23
Address Select Logic
5-23
Timing and Control
5-24
Memory Chip Array
5-24
Memory Data
5-25
Operation
5-25
INPUT AND OUTPUT SIGNALS
5-25
PROGRAMMING
5-26
DETAILED LOGIC DESCRIPTION
5-26
Address Selection Logic
5-27
Field Selection
5-27
Starting Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Memory Size Selection
5-28
TIMING AND CONTROL LOGIC
5-29
MS8-A Timing Chain
5-29
5-30
Operation of a RAM Cycle
Read Cycle
5-30
Write Cycle
5-33
5-33
Operation of a ROM-RAM Cycle
Memory Data and Memory Output Register
5-37
SWITCH DEFINITIONS
5-37

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SECTION 3
MR8-FB REPROGRAMMABLE READ ONLY MEMORY (PROM)

...................................
.................................

MR8-FB 1K MEMORY
5-41
M R8-FB Specifications
5-42
M R8-FB Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Address Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
Starting Address Decoder
.
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
Bootstrap Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
Memory Control and Timing Logic
Rear or ReadIWrite
5-44
1K PROM
5-44
13th Bit PROM
5-44
ROM Address Flag
5-45
Read~WriteMemory (RAM)
5-45
Data Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
MR8-FB PROGRAMMING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
PROM Erasing Procedure
DETAILED LOGIC DESCRIPTION
5-51
Address Decoder
5-51
Timing and Processor Control for SW Start of Memory . . . . . . . . . . . . . . . . 5-51
5-54
Field and Startinq Address Select Logic
Memory Address Control Signal Generation . . . . . . . . . . . . . . . . . . . . . . 5-55
NTSSTALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
ROM ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
1K PROM Memory and Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
256 Read~WriteMemory and Control Logic . . . . . . . . . . . . . . . . . . . . . . 5-57
ROM and RAM Data Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59

..................................
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CONTENTS (Cont)

SECTION 4
CORE MEMORY SYSTEMS
MEMORY SYSTEM. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 5-61
MEMORY SYSTEM. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 5-61
MM8-AA 8K CORE MEMORY SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
Memory Core
5-63
Hysteresis Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
XIY Select Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
Magnetic Core In Two-Dimension Array . . . . . . . . . . . . . . . . . . . . . . . . 5-65
Assembly Of 12-Stacked Core Mats . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
Core Selection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
Organization Of XIY Drivers And Current Source . . . . . . . . . . . . . . . . . . . 5-69
X And Y Current Sources - General Description . . . . . . . . . . . . . . . . . . . 5-69
Stack Charge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
Power Fail Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
Core Selection Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
Address Decoding Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73
Diode Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73
Operation Of Selection Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73
Operation Of The Core Selection Switches . . . . . . . . . . . . . . . . . . . . . . . 5-79
Sense/Inhibit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79
Sensellnhibit Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79
Readmrite Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81
Inhibit Control Logic
Field Select Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81
Sense Register Enable L.ogic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
Sense Register Clear Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
Strobe Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84
Strobe Setting Jumpers
Sense Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-86
Sense Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86
Inhibit Driver Load Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87
Inhibit Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87
Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90
POWER NOT OK
Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91
Circuit Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93
Core Memory Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93
MM8-A6 16K CORE MEMORY SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94
Assembly Of Twelve Care Mats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94
Address Decoding Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94
Operation Of The Core Selection Switches . . . . . . . . . . . . . . . . . . . . . . 5-100
ReadIWrite Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100
Field Select Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-104
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105
Inhibit Control Logic

.....................................

CONTENTS (Cont)
Page
Sense Register Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105
Sense Register Clear Timing
5-105
Strobecontrol Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-106
Strobe Setting Jumpers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-106
Inhibit Driver Load Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108
Sense Amplifier
Inhibit Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108
Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109
POWER OK
Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109

.............................

CHAPTER 6

PDP-8/A OPT1ON MODU LES
SECTION 1
DKC8-AA I/O OPTION MODULE (M8316)
DKC8-AA IIO OPTION MODULE BLOCK DIAGRAM DESCRIPTION . . . . . . . . . . . 6-3
Serial Line Unit (SLU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
General Purpose 12-Bit Parallel I10 . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Real Time Crystal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Front Panel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
SERIAL LINE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
SLU Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
SLU FUNCTIONAL DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Methods of Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Transmit Operation
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
SLU Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Parity Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Number of Bits Per Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
SLU PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
SLU DETAILED LOGIC DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Device Select Logic
SLU Operation Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
SLU Interrupt and Skip Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
SLU Timing Generator and Baud Rate Select Logic . . . . . . . . . . . . . . . . . . 6-12
Universal Asynchronous ReceiverITransmitter (UART) . . . . . . . . . . . . . . . . 6-14
UART Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
UART Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-17
Level Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Reader Run Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Request to Send and Terminal Ready . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
REAL TIME CLOCK
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
REAL TIME CLOCK PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
REAL TIME CLOCK DETAILED LOGIC DESCRIPTION . . . . . . . . . . . . . . . . . 6-21
Device Select and Operation Decoder Logic . . . . . . . . . . . . . . . . . . . . . . 6-21
. . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Real Time Clock Frequency Dividers
Real Time Clock Interrupt and Skip Logic . . . . . . . . . . . . . . . . . . . . . . . 6-23

CONTENTS (Cont)
Page

GENERAL PURPOSE PARA.LLEL I10 BLOCK DIAGRAM DESCRIPTION . . . . . . . . 6-23
. . . . . . . . . . . . . . . . . 6-24
GENERAL PURPOSE PARA.LLEL I10 PROGRAMMING
DETAILED LOGIC DESCRIPTION
6-24
Device Select and Operations Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Interrupt and Skip Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Receive and Transmit Operations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Transmit Operation
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Parallel I10 Output Register
6-29
Parallel I10 Input Buffer and Data Gates . . . . . . . . . . . . . . . . . . . . . . . . 6-30

.............................

..............................

SECTION 2
KM8-A EXTENDED OPTION MODULE (M8317)
KM8-A EXTENDED OPTION BOARD (M8317) . . . . . . . . . . . . . . . . . . . . . . 6-32
Memory Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
Timeshare Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
Power FailIAuto Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-33
Bootstrap Loader
MEMORY EXTENSION AND TIMESHARE DESCRIPTION . . . . . . . . . . . . . . . . 6-33
MEMORY EXTENSION BLOCK DIAGRAM DESCRIPTION . . . . . . . . . . . . . . . . 6-33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
Control Logic
Instruction Field Register (IF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Data Field Register (DF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Instruction Buffer Register (IB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Save Field Register (SF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
TIMESHARE CONTROL BLOCK DIAGRAM DESCRIPTION . . . . . . . . . . . . . . . 6-35
MEMORY EXTENSION AND TIMESHARE PROGRAMMING . . . . . . . . . . . . . . . 6-35
Memory Extension Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
Timeshare Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
MEMORY EXTENSION AND TIMESHARE DETAILED LOGIC DESCRIPTION . . . . . 6-38
Memory ExtensionITirn~eshareDevice Select . . . . . . . . . . . . . . . . . . . . . . 6-38
Memory Extension and Timeshare Operation Decoder . . . . . . . . . . . . . . . . . 6-39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
Input Multiplexer
Instruction Field Register and Controls . . . . . . . . . . . . . . . . . . . . . . . . 6-41
Data Field Register and Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
Output Multiplexer
Timeshare User Buffer Register and Control Logic . . . . . . . . . . . . . . . . . . . 6-46
Trap Detect Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51
Interrupt Inhibit Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51
. . . . . . . . . . . . . . 6-51
POWER FAILIAUTO RESTART AND BOOTSTRAP LOADER
. . . . . . . . . . . . . . . . . 6-51
Power FailIAuto Restart Block Diagram Description
Power FailIAuto Restart Programming . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
Bootstrap Loader Block Diagram Description . . . . . . . . . . . . . . . . . . . . . 6-54
BOOTSTRAP ROM ORGANIZATION AND PROGRAMMING . . . . . . . . . . . . . . . 6-54
ROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
Auto-RestartIBootstrap Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55

CONTENTS (Cont)

ROM Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
Bootstrap Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
Obtaining Blank ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
ROM PROGRAM LISTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
POWER FA1LIAUTO RESTART AND BOOTSTRAP OPERATION AND TIMING
. . . . 6-57
Power Fail Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
Auto-Restart Operation and Timing
6-68
Bootstrap Operation and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70
POWER FA1LIAUTO-RESTARTAND BOOTSTRAP OPERATION DETAILED
LOGIC DESCRIPTION
6-70
Power FailIAuto-Restart Device Select and Operation Decoder . . . . . . . . . . . . 6-71
Power Fail Interrupt and Skip Logic
6-71
Bootstrap and Auto-Restart Timing Clock . . . . . . . . . . . . . . . . . . . . . . . 6-73
Bootstrap Initialization Logic
6-73
Auto-Restart Initialization Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73
Auto-Restart and Bootstrap Address Counters . . . . . . . . . . . . . . . . . . . . . 6-75
ROM Memory Control and Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . 6-75
Bootstrap and Auto-Restart Operation Control Logic . . . . . . . . . . . . . . . . . 6-75

..........................

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CHAPTER 7

POWER SUPPLY
GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7-2
PDP-8IA SEMICONDUCTOR BASIC POWER ASSEMBLY
Power Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Regulator Board (G8016) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
+5 Vdc Regulator Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7-6
+5 Vdc Regulator Circuit. Battery Operation
Battery Empty Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Battery Charging Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
215 Vdc Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
POWEROKHCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
AC LOW L Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
8A400/600/800 BASIC POWER ASSEMBLY . . . . . . . . . . . . . . . . . . . . . . . . 7-12
H9194 Connector Block Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Regulator Board (G8018) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
+5 Vdc Regulator Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
-5 Vdc Regulator Circuit
+20 Vdc Regulator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Â ±5 Vdc Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
POWER OK H Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
AC LOW L Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
8A420/620/820 BASIC POWER ASSEMBLY . . . . . . . . . . . . . . . . . . . . . . . . 7-20
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
Interlock and Triac Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
. . . . . . . . . . . . . . . . . . . . . . 7-22
Line Level Transformer and Peak Detector
. . . . . . . . . . . . . . . . . . 7-22
ThermistorIThermostat and Emergency Shutdown
POWER OK H Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26

.................

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xiii

CONTENTS (Cont)
Page
CHAPTER 8

MAINTENANCE AND TROUBLESHOOTING

.............

MAINTENANCE AND TROUBLESHOOTING REQUIREMENTS
8-1
Diagnostic Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Equipment
8-3
8-3
PREVENTIVE MAINTENAIICE INSPECTIONS
Scheduled Maintenance
8-3
The Importance of a Preventive Maintenance Schedule . . . . . . . . . . . . . . . . 8-3
PDP-8IA TROUBLESHOOTIING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8-3
Operator Errors
8-4
Troubleshooting Procedures
Validation Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8-4
Cable Problems
Log Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Removal and Replacerrient of Modules . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Removal and Replacemient of Regulator Board . . . . . . . . . . . . . . . . . . . . 8-5
Removal and Replacemient of LEDs on the Limited Function Panel . . . . . . . . . . 8-5
. . . . . . . . . . 8-6
Removal and Replacemient of LEDs on the Programmer's Console
POWER SUPPLY ADJUSTMENTS
8-6
G8016 Power Supply Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
+5 V Adjustment (G8016) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
G8018 Power Supply Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
+5 V Power Supply Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
+20 V Power Supply Adjustment
. . . . . . . . . . . . . . . . . . . . . . . . 8-6
POWER FAILIAUTO-RESTART LEVEL ADJUSTMENT (G8016 AND G8018) . . . . . . 8-6
G8018 Power Fail/Auto-Restart Adjustment
. . . . . . . . . . . . . . . . . . . . . 8-9
G8016 Power FaillAuto-Restart Adjustment
. . . . . . . . . . . . . . . . . . . . . 8-9
LINE VOLTAGE AND FRElQUENCYCOMBINATIONS
8-9
8A400/600/800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8A420/620/820
8-11
PDP-8lA Semiconductc)r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

.......................................
......................
................................
....................................
..............................

.....................................

.............................

..................

....................................

CHAPTER 9

SPARE PARTS

APPENDIX A

INSTRUCTION SUMMARY

APPENDIX B

OMNIBUS SIGNAL LOCATlDR

APPENDIX C

MODULE ASSIGNMENT AND POWER REQUIREMENTS

APPENDIX D

PROGRAM LOADING PROCEDURES
TURNING THE SYSTEM OIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ-lNMODE(R1M) LOADER
BINARY (BIN) LOADER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LOADING BINARY TAPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D-I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2

APPENDIX E

ASCII CHARACTER CODES

xiv

D-3
D-4

CONTENTS (Cont)
Page
APPENDIX F

DEVICE CODES

APPENDIX G

MEMORY CYCLE TIME SUMMARY

APPENDIX H

ENGINEERING DRAWINGS

ILLUSTRATIONS

Figure No

Title

Page

PDP-8/A Miniprocessor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
PDP-8/A System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
PDP-8/A Limited Function Panel
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
PDP-8lA Programmer's Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
State Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
8A420.8A620. 8A820 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
PDP-81A Computer Packaging (Inner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
PDP-8lA Computer Packaging (Outer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
. . . . . . . . . 2-7
Part of M8320 Module Showing R55 which is Removed for 8A Operation
PDPaIA Semiconductor Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
PDP-8/A Semiconductor Computer Chassis Dimensions . . . . . . . . . . . . . . . . . . . 2-10
PDP-8/A Chassis (H9300) (Transformer Cover Removed) . . . . . . . . . . . . . . . . . . 2-11
PDP-8/A Chassis (8A42018A62Ol 8A820) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
8A420/6201820 Chassis Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73
8A60018A620 Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
KK8-A (M8315) CPU Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
MS8-A (M8311) Readmrite Random Access Memory . . . . . . . . . . . . . . . . . . . . 2-17
MR8-A (M8312) Read Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . 2-19
MM8-AA Core Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
MM8-AB Core Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
DKC8-AA (M8316) 110 Option Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
D Etch Revision of DKC8-AA (M8316) 110 Option Board . . . . . . . . . . . . . . . . . . 2-26
KM8-A (M8317) Extended Option Board . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Semiconductor Memory Regulator Board (G8016) . . . . . . . . . . . . . . . . . . . . . 2-31
8A MASTERISLAVE Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
G8018 Core Memory Regulator Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Limited Function Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
KC8-AA Programmer's Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
PDP-8/A Electrical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Paper Tape Leader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
LT33 Teletype Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
PDP-8/A Omnibus (H9194) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
PDP-8/A Hex and Quad Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
8A Chassis (H9300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Modules Connected With H851 Type Connector . . . . . . . . . . . . . . . . . . . . . . . 3-6

I L LUSTRATIONS (Cont

Figure No

Page

Title

Omnibus Signal Locator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3-21
Timing For One Memory Cyc:le
3-21
Time State and Time Pulse Change Timing
3-22
TP3 Timing During IOT Transfer
Memory Timing
3-22
Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
Basic IIOTiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
CAF Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23
3-23
Timing to Stop CPU Using Not Last XFER L
Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
External Loading of Link Tiniing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
CPU Restart Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-24
Data Break Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Data Exchange Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
End of Data Break Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
CPU Major States Timing
FETCH Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Start Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Stop Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Typical I10 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
Sample Programmed I10 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
Timing for Sample Programmed I10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
Sample One Cycle Data Break Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
Data Break Control Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
Three Cycle Data Break Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . 3-38
Parallel Connection of Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
External Bus Signals and Rela~tedOmnibus Signals . . . . . . . . . . . . . . . . . . . . . . 3-41
CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Timing Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Power ONIRUN Logic
4-4
Timing Register Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Timing Register Normal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
CPU Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
CPU Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Memory Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Memory Timing Signals
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
I10 Transfer Stall Logic
I10 Timing (NOT LAST XFER L Asserted) . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Memory Stall Logic
. . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Timingl NTS STALL L Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Limited Function Panel Circuit Board Schematicl 8A Computers . . . . . . . . . . . . . . 4-17
Limited Function Panel Circuit Board Schematic, PDP-81A Semiconductor Computer . . . 4-18
Programmer's Console Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Clock Timing Logic
Timingl Clock Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Register Logic
4-25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Multiplexer Logic

...............................
..........................
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........................................

xvi

ILLUSTRATIONS (Cont)

Figure No

Ttle

Page

MPXlEnable Signal Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
RegisterlMultiplexer Gating Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
RegisterlMultiplexer Gating Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
ADDRSID ISP Readout Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Resultant Displays . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
OCTAL Designations .
Function Button Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
DISP Button Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
THISI HLTI BOOT Logic
STATEI MD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Console Control Logic .
Console Control Logic .MAI DATAI SR ENABLE
. . . . . . . . . . . . . . . . . . . . . 4-41
ROM A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
ROM B Logic
ROM C Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
ROM D Logic
ROM E Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
ROM F Logic
ROM H Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
ROM J Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
Instruction Registers Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
Major State Registers Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49
Data ENAlData CMP Logic
Address Update Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51
Major Register Load Signal Logic
AC Register Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
Block DiagramI Major Register and Gating (BITO) . . . . . . . . . . . . . . . . . . . . . . 4-55
Page Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
Carry In Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-62
Skip Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64
Link Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66
Major Register Gating (BITOO)I Programmed I10 Transfer . . . . . . . . . . . . . . . . . . 4-68
Programmed I10 Transfer Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69
Processor IOT Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71
Program Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74
Major Register Gating (BIT0II Data Break Transfer
. . . . . . . . . . . . . . . . . . . . . 4-75
Data Break Transfer Control Signal Logic . . . . . . . . . . . . . . . . . . . . . . . . . . 4-77
AUTO-START Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78
AUTO-START TimingI CPU Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79
MR8-A ROM Memory Module (M8312) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4
ROMIRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
ROM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
ROM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Detailed Block Diagram of Address Select Logic . . . . . . . . . . . . . . . . . . . . . . . 5-10
Field and Size Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Chip Select Decoding
13th Bit Mapping into 1K X 1 Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
13th Bit Mapping into 4K X IArray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Timing and Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
ROM-RAM Selection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

xvi i

Figure No

Title

Page

.....................................

Single Step Operation
5-17
Arrangement of 1K Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
ROM 4K Memory - Physical Layout of Module . . . . . . . . . . . . . . . . . . . . . . . 5-18
5-22
RAM MS8-A Module M8311
MS8-A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-24
Read Cycle Flow Chart
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Write Cycle Flow Chart
Address Selection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-28
ROM (lC8223) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Memory Timing Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
TP4 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
Source Time Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32
Operations at TP1
5-33
Stall + 400 ns Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
Write Cycle Logic
ROM-RAM Initial Delay Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
ROM-RAM Initial Delay Tim~ngDiagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
5-37
Detailed Timing of Initial Delay in ROM-RAM Cycle
Memory Array and Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Simplified MR8-FB Block Diagram
MR8-FB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
Bootstrap Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
13th Bit Readwrite Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
PROM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
PROM Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50
Address Decoder Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
ML8-F Timing and SW Operation Control Logic . . . . . . . . . . . . . . . . . . . . . . . 5-53
Field and Starting Address Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54
Memory Address Control Sigtial Generator
. . . . . . . . . . . . . . . . . . . . . . . . . 5-55
PROM and Control Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56
ROM and RAM Data Multiplt?xerand Latch . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
RAM Memory (256 Word) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58
Core Memory System Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . 5-62
Core Memory Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
MM8-AA Core Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
Magnetic Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
Magnetic Core Hysteresis Loop
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
5-66
Three Wire Memory Configuration
Core Stack Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67
8K + 12 Bit Stack and Sense Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
Current Path For Write Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69
Current Path For Read Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
Decoding of X and Y Driver Current Sources Block Diagram . . . . . . . . . . . . . . . . 5-71
Stack Charge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72
Power Fail Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72

.................................

......................................

....................

..............................

xvi ii

IL LUSTRATI ONS (Cont )

Figure No

Title

Page

Decoding Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73
Organization of Planar Stack Diode Matrix for X Select Lines . . . . . . . . . . . . . . . . 5-78
Operation Of Selection Switches To Select Line XO . . . . . . . . . . . . . . . . . . . . . 5-78
Detailed Operation Of Selection Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81
Inhibit Operation For Bit 0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
Inhibit Control Logic
Field Select Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
Memory Sense Register Enable Logicfor Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . 5-83
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
Clear Time Control Logic
Strobe and Clear Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85
Strobe Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85
Strobe Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86
Sense Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87
Inhibit Drivers Load Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-88
Inhibit Drivers Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-88
Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91
POWER NOT OK Circuit
Margining Test Fixture Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
Test Point Signals
MM8-AB 16K Core Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95
MM8-AB 16K Core Memory Stack Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
16K X 12 Stack and Sense Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97
16K Core Memory Module Wiring Assembly . . . . . . . . . . . . . . . . . . . . . . . . . 5-98
Decoding of X and Y Driver Current Sources Block Diagram . . . . . . . . . . . . . . . . 5-99
Decoding Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103
Inhibit Operation For Bit 0
Field Selection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-104
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105
Clear Time Control Logic
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-106
Strobe and Clear Timing
.
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
Strobe Control Logic
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
Inhibit Driver Load Gates
.
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108
Inhibit Drivers for Bit 0
.
.
.
.
.
.
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-110
Current Source
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-111
POWER NOT OK Circuit
DKC8-AA 1/0 Option Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Serial Line Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Transmitter Block Diagram (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
UART Receiver Block Diagram
Timing Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
SLU and Real Time Clock Device Select Logic . . . . . . . . . . . . . . . . . . . . . . . . 6-10
SLU Operation Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
SLU Interrupt and Skip Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
SLU Timing Generator and Baud Rate Select Logic . . . . . . . . . . . . . . . . . . . . . 6-13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Format of Input/Output Character
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Receiver Timing Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Transmitter Timing
. . . . . . . . . . . . . . . . . 6-19
EIA and 20 mA t o TTL Converters and Reader Run Logic
TTL to EIA and 20 mA Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

xix

I L.LUSTRATI ONS (Cont )

Figure No

Title

Page

Real Time Crystal Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
. . . . . . . . . . . . . . . . 6-22
Real Time Clock IOT Decoder and Interrupt and Skip Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Real Time Clock Frequency Dividers
General Purpose Parallel I10 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Parallel I10 Device Select and Operation Decoder . . . . . . . . . . . . . . . . . . . . . . 6-27
General Purpose Parallel 1/0 Interrupt and Skip Logic . . . . . . . . . . . . . . . . . . . . 6-28
Parallel I10 Strobe Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-29
Parallel I10 Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
Parallel I10 Input Buffer and Data Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
KM8-A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
Memory Extension and Timeshare Block Diagram . . . . . . . . . . . . . . . . . . . . . . 6-34
. . . . . . . . . . . . . . . . . . . 6-39
Memory Extension and Timeshare Device Select Logic
Memory ExtensionITime Share Operation Decoder . . . . . . . . . . . . . . . . . . . . . 6-40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-42
Input Multiplexer
IF Register and Control Logic: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43
IF and DF Field Address Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
Data Field Register and Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
Output Multiplexer
. . . . . . . . . . . . . . . . . . . . . . . . 6-49
Time Share User Buffer Register and Control
Trap Detect Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
Interrupt Inhibit Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-52
Power Fail and Auto Restart Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
Bootstrap Loader Block Diagram
16 Bit Word ROM Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
Auto Restart Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
Bootstrap Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
Auto Restart and Bootstrap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-70
Bootstrap Timing
Power Fail Auto Restart Device Select and Operation Decoder . . . . . . . . . . . . . . . 6-71
Bootstrap and Auto Start Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-72
Bootstrap and Auto Start Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-74
CLKI and CLK2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75
Auto Restart Initialization Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76
Auto Restart and Bootstrap ROM Address Counters . . . . . . . . . . . . . . . . . . . . . 6-77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78
ROM Memory Control and MUX
Bootstrap and Auto Restart Operation Control Logic . . . . . . . . . . . . . . . . . . . . 6-79
. . . . . . . . . . . . . 7-2
Interconnections. PDP-8lA Semiconductor Basic Power Assembly
Power Board Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
G8016 Regulator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
+5 Vdc Regulator Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Regulator Board Edge Connector
+5 Vdc Regulator Circuit. Battery Operation . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Battery Empty Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Battery Charging Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-10
21 5 Vdc Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
POWER OK LCircuit
AC LOW L Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Voltage Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-12
Battery Hold-up Time. Minimum Line Voltage vs % o f Full-Rated Load . . . . . . . . . . . 7-13

I LLUSTRATIONS (Cont)

Figure No

Title

Page

Interconnections. 8A400/600/800 Basic Power Assembly . . . . . . . . . . . . . . . . . . 7-14
Connector Block Assembly Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
+5 Vdc Regulator Circuit
- 5 Vdc Regulator Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
+20 Vdc Regulator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
k15 Vdc Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
POWER OK H Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
AC LOW LCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Timing. AC LOW L Circuit (60 Hz Operation) . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Interconnections. 8A420/620/820 Basic Power Assembly . . . . . . . . . . . . . . . . . . 7-21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Interlock and Triac Control Circuit
Line Level TransformerIPeak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
. . . . . . . . . . . . . . . . . . . . . 7-25
ThermistorlThermostat and Emergency Shutdown
POWER OK Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
G8016 Regulator Board Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
G8018 Regulator Board Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
H9194 Connector Block Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
50 Hz and 60 Hz Connections on 10 Slot Machines . . . . . . . . . . . . . . . . . . . . . 8-11
Omnibus Signal Locator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

TABLES

Table No

Title

Page

PDP-8/A Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
PDP-8/A Computer Assemblies
PDP-8/A Limited Function Panel Controls and Indicators . . . . . . . . . . . . . . . . . . 1-11
PDP-8/A Programmer's Console Controls and Indicators . . . . . . . . . . . . . . . . . . . 1-12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Summary of Installation Functions
PDP-8/A Computers. Dedicated Omnibus Slots . . . . . . . . . . . . . . . . . . . . . . . 2-8
KK8-A (M8315) Central Processor Unit Switch Settings . . . . . . . . . . . . . . . . . . . 2-16
MS8-A Readmrite Memory Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
MR8-A Read Only Memory Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
MM8-AA 8K Core Memory Jumper Installation . . . . . . . . . . . . . . . . . . . . . . . 2-21
. . . . . . . . . . . . . . . . . . . . . . 2-21
MM8-A6 16K Core Memory Jumper Installation
DKC8-AA I10 Option Board Switch Settings for C Etch Module . . . . . . . . . . . . . . 2-26
. . . . . . . . . . . . . . . . 2-27
DKC8-AA Option Board Switch Settings for D Etch Module
Auto-Restart Select Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Bootstrap Select Switch Settings (for ROMs Labeled 87A2 and 88A2) . . . . . . . . . . . 2-29
Bootstrap Select Switch Settings (for ROMs Labeled 158A2 and 159A2) . . . . . . . . . . 2-29
BootstrapIAuto-Restart Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Bootstrap Switch Settings for ROMs (E82 and E87) Labeled 87A2 and 88A2 . . . . . . . . 2-52
Bootstrap Switch Settings for ROMs (E82 and E87) Labeled 158A2 and 159A2 . . . . . . 2-53
Basic PDP-8/A Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
. . . . . . . . . . . . . . . . . . . . . . . 3-5
Slot Assignments for Modules on the Omnibus
Load Resistor and Drivers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

xxi

TABLES (Cont)

Table No

Title

Page

Omnibus Signal Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
lOTs For Sample Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Transfer Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
Time State Stall Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Primary Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Clock Timing Control Signals
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Register Logic Bus Line Data
DEC7447A InputIOutput Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Function Button Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Display Control Signals
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
ROM H Input/Output Signals
DATA ENAIDATA CMP Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
PC. AC. MQ CLK Signal Loading
ROM D InputIOutput Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
ROM C Input/Output Signals
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61
ROM B Input/Output Signals
ROM E InputIOutput Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
ROM J InputIOutput Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72
ROM A InputIOutput Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76
M R8-A Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
MR8-A Signal Definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Switch Setting t o Select Memory Field
MA0 and MA1 States for Memory Field Sizes . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Switch Settings for States MA0 and MA1 . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
States of MA3 and MA2 to Select and Address Range . . . . . . . . . . . . . . . . . . . . 5-14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
MS8-A Specifications
MS8-A Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
MS8-A Readwrite Memory Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
MR8-FB Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-46
Core Selection Decoding Scheme "X" READ . . . . . . . . . . . . . . . . . . . . . . . . 5-74
Core Selection Y READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80
Address Block Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
Strobe Select Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84
V REF Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
Voltage Test Points
Memory Data Errors Possible Causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93
Core Selection Decoding Scheme "Y" READ . . . . . . . . . . . . . . . . . . . . . . . 5-101
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103
Core Selection. Y Read
Address Block Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-104
COL and C1 L Levels for Data Bus Transfers . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
D Etch SLU Baud Rate Select Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
UART Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
J4 Input Signal Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
J5 Output Signal Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
ROM No. 1 and ROM No. 2 Listings (for ROMs Labeled 87A2 a~nd88A2) . . . . . . . . . 6-58
ROM No. 1 and ROM No. 2 Listings (for ROMs Labeled 158A2 and 159A2) . . . . . . . . 6-63
PDP-8/A Family. Primary Power Assemblies . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

xxii

TABLES (Cont)

Table No

Title

Page

Maintenance Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Preventive Maintenance (3 Months or 500 Hours) . . . . . . . . . . . . . . . . . . . . . . 8-4
PDP-8/A Line Sets. Fuses. and Transformer Assemblies . . . . . . . . . . . . . . . . . . . 8-9
PDP-8/A Semiconductor Recommended Spare Parts . . . . . . . . . . . . . . . . . . . . . 9-1
8A Recommended Spare Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
RIM Loader Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2
Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1

xxiii

CHAPTER 1
INTRODUCTION A N D DESCRIPTION

This manual provides the user with the necessary information to operate, interface to, maintain, and troubleshoot the
PDP-8/A Miniprocessor manufactured by Digital Equipment Corporation, Maynard, Massachusetts.
The PDP-8/A is the newest model of the PDP-8 family consisting of the PDP-8/E, PDP-8/F, PDP-8/M and PDP-8/A. The
following illustrates how the PDP-8/A relates to its family members.
KIT-8/A
Modules

PD P-8/A
Small to Medium
Configurations

PDP-8/M
Medium to Large
Configurations

PDP-8/E
Large
Configurations

KIT-8/A is a module set version of the PDP-8/A configured to solve application problems that do not require a complete computer package with power, front panel, chassis, and cooling. Kits consist of processor, memory, option
boards, and mounting hardware including:
Central Processor Unit, Hex Module (M8315)
Read/Write Random Access Memory (RAM), Quad Module (M8311)
Read Only Memory (ROM), Quad Module (M8312)
Reprogrammable Read Only Memory (PROM), Quad Module (M8349)
DKC8-AA 1/0 Option Board with Serial I/O, Parallel I/O, Real-Time Crystal Clock, and Programmer's Panel Control,
Hex Module (M8316)
KM8-AA Extended Option Board with Memory Extension, Timeshare Control, Power Fail/Auto-Restart, and Bootstrap
Loader, Hex Module (M8317)
MM8-AA(8K) and MM8-AB( 16K) Core Memory Modules
PDP-8/A - There are two basic types of computers in the PDP-8/A family. The first type is the PDP-8/A, which uses
semiconductor memories (MS8 and MR8). The second type is represented by a series of computers, each of which uses
8K or 16K core memory (MM8); this series consists of the 8A400, 8A420, 8A600, 8A620, 8A800, and 8A820
computers, When a reference applies to both types of computers, the designation "PDP-8/Ar' is used. "PDP-8/A Semiconductor" refers to the semiconductor-memory computer, while "8A400," for example, refers to a specific core-memory machine and "8A" refers to the core-memory machines in general.

PDP-8/A Semiconductor (Semiconductor Memory); designed to provide the security and data integrity of hard wired,
solid state logic and relay controllers, and in addition, provide the flexibility, power, and low cost of a computer. Space is
available to install 1 0 modules.
Semiconductor memory:
RAM 1 K, 2K, 4K (M8311)
ROM 1K, 2K, 4K (M8312)
PROM 1 K with 256 word RAM (M8349t

On Quad Modules

Battery backup:
System 1 to 7 minutes with provision for additional external batteries

8 A (Core Memory); provides the lowest cost c:omputers in the 8K to 32K memory range for small computer systems
and mainframes. The PDP-8/A Central Processor Unit and two new core memories are used. Space is available for 12 or
2 0 modules.
Core memory:
8K (MM8-AA) and 16K (MM8-AB) Hex Modules (two slot spaces are required for each module).

Most of the options available for other members of the PDP-8 family are compatible with the PDP-8/A (see Paragraph
2.4 for a list of those that are not compatible). However, the DKC8-AA I/O Option module, the KM8-AA Extended Option
module, and several memory modules have been designed exclusively for the PDP-8/A.
Companion Documents include:
1.

Introduction to Programming - 19 7 3

0 5 / 8 Handbook

POP-8/A Miniprocessor Handbook - 1975- 1976

POP-8/A Operators Handbook(DEC-8A-HOPHB-A-D)

PD P- %/A Engineering Drawings

PDP-8/E Maintenance Manual Volurne II (DEC-8E-HMM2A-D-D) and Ill (DEC-8E-HMM3A-C-D).

All of these documents are available from Communications Services, Digital Equipment Corporation, Maynard, Massachusetts, 01754.
Table 1- 1 lists the functional characteristics of the PDP-8/A.

Table 1-1
PDP-8/A Functional Characteristics
TYpe

Single address, fixed word length, parallel transfer programmed data processor.

Word Length

12 bits.

Cycle Time

1.5 us minimum (See memory speeds).
Memory Type

ie (us)
All Other States

ROM Only
ROMIRAM (ROM Cycle)
ROMIRAM (RAM Cycle)
RAM Only
Core Memory
Memory Types

RAM
ROM
PROM
Core

1K, 2K, 4K
1 K, 2K. 4K
1K
8K, 16K

Memory Expansion
Hardware Registers

5(AC, MQ, MB, PC, CPMA).

Auto Index

8 Auto Index registers per 4K memory field.

Addressing Capability

One instruction may address 256 locations directly or 4096 locations indirectly.

Instruction Set

6 memory reference instructions, 20 microprogrammable operate microinstructions,
and 8 inputloutput transfer instructions for the CPU and each of up to 60 I10
devices.

Instruction Execution Time

Operate microinstruction
Directly addressed M RI
Indirect1y addressed M R I

InputIOutput Capability

Programmed data transfer, program interrupt system transfer, and 12 channels of
internal and/or external direct memory access (data break).

Auto Start Feature

The CPU contains an auto-start which can start the CPU at one of six switch selectable addresses upon application of power.
-

*Cycle times reflect 1.5 MS memory.

1.5 us*
3.0 us*
4.5 us*

Table 1-1 (Cont)
PDP-8/A Functional Characteristics

------Options

Two new option boards which may be used separately or together.
1.

Front Panel Control
Serial Line Unit
Parallel I10
Real Time Clock

Power FailIAuto Restart
Memory Extension
Timeshare Control
Bootstrap Loader

Size (W X H X D)

19 X 10.5 X 10.5 in. (48 X 27 X 27 cm) - POP-8/A Semiconductor, 8A400.
8A60OI8A800.
19 X 10.44 X 23 in. (48 X 26.52 X 58.42 cm) - 8A420, 8A620.8A820.

Weight

55 Ib ( 2 5 kg) - PDP-8/A Semiconductor, 8A400, 8A600, 8A800.
1 17 Ib (53 kg) - 8A420, 8A620, 8A820.

Operating Environment

Ambient temperature
Relative humidity

Power Requirement

Approximately 150 W at 115 Vac, 50 or 6 0 Hz or 230 Vac, 50 or 6 0 Hz (voltage
and frequency specified at time of order).

41Â t o 122O F (5Oto 50Â C)
10% t o 95% maximum. Wet bulb 90Â F (32' C)

1.1 SYSTEM DESCRIPTION
The PDP-8/A is a general purpose miniprocessor. Its processor structure is single-address, fixed word length, parallel
transfer, using 12-bit, two's complement arithmetic. The cycle time of the processor is 1.5 us. Standard features include
one level of indirect addressing and facilities for instruction skipping, program interrupts as a function of input/output
device conditions, and auto-restart features.
Five 12-bit registers are used to control cornlputer operations, address memory, perform arithmetic or logical operations, and store data. An optional Programrner's Console provides switches and indicators that permit convenient
monitoring and modification of machine operation.
The flexible, high capacity input/output capabilities of the PDP-8/A allow it to operate a great variety of peripheral
devices. More than 6 0 input/output device options including high-speed paper-tape equipment, card readers, line
printers, disk and magnetic tape bulk storage devices, and a wide range of data acquisition, transmission, and display
peripherals are available from DIGITAL for the PDP-8/A.
Each PDP-8/A system is completely self-contained. A single source of 1 1 5 or 2 3 0 Vac power is required; internal power
supplies produce all the necessary operating voltages for the system. The basic PDP-8/A computer consists of a rackmountable chassis with a power supply and an Omnibus (backplane) into which are inserted the central processor, the
memory system, and the optional Programmer's Console and console terminal cor~trol.In the PDP-8/A, a bus is defined
as a group of signal lines carrying related information, such as the 12 bits of an instruction or data word. The Omnibus
may be considered a wide bus containing several buses along with many other signal lines. Each PDP-8/A Omnibus has a
slot for the central processor unit, two slots reserved for the t w o option boards, plus several identical nondedicated
module slots. Each slot will accept a 144-pin quad or hex-sized module. (Some slots will accept a 180-pin hex module.)
The Omnibus provides two-way signal paths between corresponding pins of the modules that are plugged into it.

A PDP-8/A computer pictured in Figure 1-1 shows both the Limited Function Panel (the panel on the bottom with three
switches and three indicators) and the Programmer's Console. The Programmer's Console can be located remotely from
the chassis; in such a case, or when the system does not include a console, a blank panel is attached.
PDP-8/A computers have three different mechanical assemblies that can be characterized by the number of available
Omnibus slots; that is, the PDP-8/A semiconductor computer assembly has a 10-slot Omnibus, while the 8A computer
assemblies have either a 12-slot or a 20-slot Omnibus. Table 1-2 relates the various PDP-8/A computers to some of the
basic system components. Note that the 8A400 can be considered the basic 8A computer, having a core memory, an 8A
CPU, and a 12-slot Omnibus. Thus, the 8A420 differs only in that it has a 20-slot Omnibus; the 8A600 differs in that it
has a PDP-8/E CPU; the 8A620 differs in that it has a PDP-8/E CPU and a 20-slot Omnibus; the 8A800 differs in that it
has an FPP-8/A (not indicated in Table 1-2); and, the 8A820 differs in that it has an FPP-8/A and a 20-slot Omnibus.
Also, note that only 8A computers that use a PDP-8/E CPU can be expanded.

Table 1-2
PDP-8/A Computer Assemblies
-

Computer

CPU

Memory*
-

Basic Power Assembly

Omnibus

Expandable

Semiconductor

Core

Yes. As many as 20 slots
can be added.

Core

Yes. As many as 20 slots
can be added.

Core

*A KM8-A (or KM8-E) Extended Memory Option module must be included in all the 8A computers, since their basic memory capacity
is 8 K or 16K; the K M 8 is optional with the PDP-8/A Semiconductor computer, since the basic memory can be less than, greater than,
or equal to 4K.

Figure 1-2 represents, pictorially, the PDP-8/A Omnibus and the relationship of the fundamental system components
. e . , CPU, memory, power supply, option, and peripheral interfaces). These components are described briefly in the
following paragraphs.

Figure 1 - 1

PDP-8/A Miniprocessor

,15VAC/230

VAC

KK8-E
CENTRAL PROCESSOR UNIT ( M 8 3 0 0 ,
M 8 3 1 0 ) , TIMING GENERATOR ( M 8 3 3 0 1 ,
B U S LOADS ( M 8 3 2 0 )

CONTROLS

DATA

(M837

CONTROLS

, ,, ,
a

DKC8-AA

K M 8 - A EXTENDED OPTION BOARD

I / O OPTION BOARD

PERIPHERAL
CONTROLLER
OR
INTERFACE

(M8317)

(1) S E R I A L

KK8-A CENTRAL
PROCESSOR UNIT

POWER SUPPLY

POWER

POWER FAIL

CONTROL

DATA

LINE UNIT.

(1) MEMORY EXTENSION AND T I M E
SHARE CONTROL.

(2) REAL TIME CRYSTAL CLOCK.

TIMING

(3) GENERAL PURPOSE PARALLEL I / O

(2)

(4) PROGRAMMERS FRONT PANEL
CONTROL.

POWER FAIL AND AUTO
RE START.

( 3)

BOOTSTRAP LOADER

CONTROL

DATA

( SUPPLIED
BY CUSTOMER
OR DEC)

0
DATA

CONTROL

TIMING

TIM.ING

STATUS

CONTROL

OMNIBUS

,T~M~NG

coNroi I R !

I O , C

n t j ~ ~ DA,TA

C,ONTOL

MS8-A RANDOM ACCESS
MEMORY (RAM)

MR8-A READ ONLY MEMORY

M8311 )

(M8312)

1K ,2K OR 4 K

Figure 1-2

TI~NG

DA(A

MR8-FB 1K PROGRAMMABLE
READ ONLY MEMORY WITH
256 WORD RAM
(PROM
(M8349

PDP-8/A System Block Diagram

CONTROL
+

TIMING

DATA
+

MM-AA CORE MEMORY ( 8 K )
H 2 1 9 A AND G 6 4 9

M M 8 - A B CORE MEMORY (16K)
H 2 1 9 B AND G 6 5 0

DATA

1.1.1 Central Processor Unit (CPU)
The KK8-A is contained on one hex module and has all the circuitry needed to manipulate data and generate control
signals; this circuitry includes the major registers and gating, the instruction decoder, the timing generator, and the autostart logic. The KK8-E is comprised of 4 hex modules. Two of these, M 8 3 0 0 and M8310, constitute the CPU; another is
the Timing Generator (M8330), and the last is the Bus Loads (M8320).
1.1.2 KC8-AA Programmer's Console
The DKC8-AA I/O Option board contains the circuitry required to connect the PDP-8/A Programmer's Console to the
Omnibus. This console consists of an array of controls and indicators that facilitate c:omputer operation and maintenance.
Key pad switches provide convenient control of the system by allowing the operator to start and stop program execution,
examine and modify the contents of memory, select various modes of operation, and load and execute short machine
language programs.
1.1.3 Limited Function Panel
The Limited Function Panel (Figure 1-3), which is often used without the Programmer's Console in dedicated applications, provides the necessary controls to apply power to the computer and start a program. A PANEL LOCK switch,
which is significant only when a Programmer's Console is present, allows the operator to disable most of the console
switches. This feature protects an operating program from being disturbed by accidental closure of a switch.

71 18-5

Figure 1-3

PDP-8/A Limited Function Panel

1.1.4 Memory
The PDP-8/A memory can be configured from ROM, RAM, PROM, or core memory to meet the user's particular requirements. Memory sizes below 4K, (such as 1K RAM, 1 K ROM, and 1 K PROM) are allowed, and the memory system can be expanded to 32K provided there is adequate current available from the power supply. Each of the
various memory options available is discussed in the following paragraphs.
1. l . 5 M M 8 - A Core Memory
The MM8-A is a 12-bit word, random access core memory system for the 8A computer. There are two versions available,
the MM8-AA (8192 12-bit words) and M M8-AB ( 16,384 12-bit words). Memory cycle time is 1.5 us. A one inch thick
hex module board contains the core stack, drive circuits, sense circuits, address decoders, etc. These circuits perform all
the operations required to transfer data into or out of core memory. The system plugs into one Omnibus slot but occupies
two spaces on the Omnibus because of the thickness of the module.
1.1.6 MS8-A Read/Write Semiconductor Memory (RAM)
The read/write semiconductor memory is a random access memory (RAM) mounted on a single quad board with a
capacity of 1K, 2K, or 4 K 12-bit words. Memory cycle time is 2.4 ps for instruct:ion fetches and 2.8 ps for all other
states.

1.1.7 MR8-A Read Memory (ROM)
The MR8-A is a semiconductor read only memory mounted on a single quad board with a capacity of 1K, 2K, or 4K
12-bit words. Memory cycle time with ROM memory only is 1.5 us.
For those systems containing both ROM and RAM, a 13th bit in each memory location containing ROM and RAM
may be set to a logical 1 when the ROM is programmed to allow the program to address a word in read/write memory. When the 13th bit is on, the content of that memory location is interpreted as a memory address instead of an
operand and used to address the desired RAM memory location. This allows the programmer to use instructions that
require read/write operations (i.e., JMS, DCA, ISZ Instructions) when writing the ROM program.

1 . I .8 MR8-FB Reprogrammable Read Only Memory (PROM)
The MR8-FB is an ultraviolet-erasable semiconductor memory mounted on a single quad board with a capacity of
1024 12-bit words of PROM and 2 5 6 words of read/write memory. PROM memory also has a 13th bit which can
be set to one, to address one of the 2 5 6 RAM locations. When the 13th bit is one, the eight least significant bits
read from a PROM location are used as an address to select one of the RAM locations. This allows the programmer
to use instructions that require read/write operations.
1 . I .9 G8Ol6 Power Supply Regulator Module
The G8016 Power Supply module provides 4-5 Vdc and -1 5 Vdc and
15 Vdc for the semiconductor versions of
the PDP-8/A Miniprocessor. The supply consists of a quad size board containing all the power generation and regulation circuitry necessary to provide these voltages. The power available is:

+5 Vdc
+I 5 Vdc
I 5 Vdc

20 A
0.75 A
max
0-75
A max

1 .I. I 0 G8Ol8 Power Supply Regulator Module
The G8018 module supplies power for core memory systems for the 8A. It differs from the semiconductor power supply
module in that more power is available:

NOTE
The G8016 and G8018 Power Supply modules are not
interchangeable. The semiconductor supply (G8016) will
operate only with the PDP-8/A Semiconductor computer; the core memory supply (G8018) will operate only
with the 8A computers.
1 . I . I 1 Interfacing
The PDP-8/A Omnibus is an internal input/output bus designed to eliminate random wiring and provide convenient
access to data and control signals. Interfacing is accomplished by inserting modules into non-dedicated slots.
The KA8-E positive I/O bus interface provides an extension to the bus system that facilitates interfacing PDP-8 family positive bus equipment with the PDP-8/A. The positive I/O bus was designed for use with PDP-8/1 and PDP-8/L
compatible peripherals, but it may be employed with almost any positive bus equipment.

PDP-8/A systems provide three types of data transfer: programmed data transfers, program interrupt transfers, and
direct memory access transfers. Programmed data transfer is the easiest to implement and is the most direct method
of handling data I/O. Program interrupt transfers provide an extension of programmed 1/0 capabilities by allowing
1/0 operations involving two or more devices to be performed concurrently. The data break system uses direct memory access for applications involving extremely fast data transfer rates. All three I/O techniques are described in
Chapter 9 of the M;niprocessor Handbook. A detailed description of the Omnibus and its signals is contained in
Chapter 3 of this manual.

1.1.I
2 Option Modules
The PDP-8/A has two multi-option hex modules available. The M8316 module, which contains four separate PDP-8/A
options, and the M8317 module, which contains three options. Each of these modules and the options provided by them
are discussed in the following paragraphs and more fully described in Chapter 6.

1.1.13 DKC8-AA 1/0 Option Board (M8316)
The M 8 3 1 6 module contains a Serial Line Unit (SLU), a Real Time Crystal Clock, a General Purpose 12-Bit Parallel
I/O, and the Programmer's Console control.
1.1.1 4 K M 8 - A Extended Option Board (MI831 7)
The M8317 module contains the Memory Extension and Timeshare Control, Power Fail and Auto Restart, and the
Bootstrap Loader options.
1.1.1 5 Peripheral Options
Digital Equipment Corporation designs and manufactures many of the peripheral devices offered with the PDP-8/A.
All peripheral options purchased from Digital include the necessary cables, controllers, interfaces, etc. required for
system operation. Most options can be added to the system simply by inserting the modules into the Omnibus and
making cable connections between the modules and the peripherals,
1.2 CONSOLE OPERATION
There are two types of panels for the PDP-8/A - the Limited Function Panel and th~eProgrammer's Console. The Limited
Function Panel is supplied with each PDP-8/A. The Programmer's Console is optional.
1.2.1
Limited Function Panel
The Limited Function Panel (Figure 1-3) has the necessary switches to apply power and to bootstrap the computer, and
indicators - POWER ON, RUN, and BATTERY CHARGING - to determine whether the computer is operating. Table 1-3
describes the function of the various switches and indicators on the Limited Function Panel.
1.2.2 Programmer's Console
The key pad switches and indicators on the PDP-8/A Programmer's Console (Figure 1-4 and Table 1-4) augment the
Limited Function Panel by allowing manual control of computer operation, and by presenting a convenient indication of
program conditions within the computer. PDP-8/A program execution can be started, stopped, monitored, or switched
among various modes of operation. The key pad switches also provide a means of selecting a memory location or major
register for examination and allow selective modification of read/write memory.
Entering Data From the Programmer's Console
1.2.3
Data is entered into registers from the programmer's console by first pressing the numbered key pad switches corresponding to the octal number to be entered, then the key pad switch corresponding to the register into which the data is
to be entered. For example, to load an octal number 7 0 0 0 into the switch register, press 7, then press 0 three times, and
then press LSR. The data entered will be transferred to the switch register. To read the data that was entered in the
switch register, press SR and then DISP; the data is displayed in the 4 character octal readout.

Table 1-3
PDP-8lA Limited Function Panel
Controls and Indicators
Control or Indicator

Function
In the up position, this switch applies power to the computer and all controls and
indicators. Power is removed by moving the switch down.

PANEL LOCK

In the up position, this switch disables all key pad switches except Switch Register
(SR) and the read functions. The RUN and BATTERY CHARGING indicators are
not affected.

BOOT

When this switch is down, the Omnibus SW line is disabled (voltage level high). When
it is up, the SW line is asserted (low). This switch i s used to start programmable read
only memory (PROM) and bootstrap loader programs. The key pad BOOT switch on
the Programmer's Console has the same function.

BATTERY CHARGING

This indicator i s a LED. It lights when the battery backup supply is charging in the
PDP-8/A semiconductor computers; in the 8A420,8A620, and 8A820 computers, it
lights when both G8018 regulators are operating properly. The indicator i s present on
the 8A400, 8A600, and 8A800 computers, but is not used.

POWER

This indicator is a LED, lit when ac power is applied to the computer.

RUN

This indicator is a LED, lit when the RUN flip-flop i s set.

0 8 -1121

Figure 1-4

PDP-8/A Programmer's Console

1.2.4 Examining Memory Locations
To determine the content of a location in memory, enter the memory field and press LXA, then enter the memory
address and press LA. Press M D and then DISP. Now press E THIS and the contents of this memory location will
be displayed in the 4-character octal readout. If you wish to examine two or more consecutive memory locations,
content of the next memory location will be displayed each time E NEXT is pressed.

1.2.5 Entering Data in Memory
To enter (deposit) data in a memory location, first enter the field into which data is to be deposited and press LXA,
then enter the address and press LA. Now enter the data and press D THIS. If you wish to enter data into two or
more consecutive memory locations, press D NEXT after each entry is made.

Table 1-4
PDP-8/A Programmer's Console Controls and Indicators
Control or Indicator

Function

ADDRS

ADDRS is a 5 character octal readout that displays the content of
the 3-bit Extended Memory Address (EMA) register and the 12-bit
Memory Address (MA) register. The five characters (digits) show the
address of the memory location to be accessed next.

DISP

DISP i s a 4 character octal readout that displays the content of the
register that has been selected for display. The Accumulator (AC),
Multiplier Quotient (MQ), Status Register, Switch Register (SR),
State, Memory Data (MD), or Data Bus (BUS) content may be read.
To select one of these for display, first press the appropriate key pad
switch (e.g., AC) and then press DISP. One of the LED indicators to
the left of the key pad will be lit, indicating which data is displayed
in the readout. DISP also indicates the number button that i s pressed;
i.e., if 3 (STATUS) is pushed, 3 appears in the right-most DISP position (if DISP is pushed after 3, the STATUS indicator lights and the
DISP readout indicates the Status register contents). Thus, the operator can view the addresses being entered and the data being
deposited.

RUN

This indicator is a LED, lit when the RUN flip-flop i s set.

Key Pad Switches
AC (0)

When key pad AC and then DISP are pressed, the content of the AC
at Time State 1 i s displayed in the 4 character octal readout. The AC
indicator to the left of the key pad will also light.
When key pad MQ and then DISP are pressed, the content of the MQ
register is displayed in the 4 character octal readout. The MQ indicator to the left of the key pad will also light.

BUS (2)

When key pad BUS and then DISP are pressed, the content of the
DATA BUS (DATA 0-1 1) at Time State 1 is displayed in the 4 character octal readout. The BUS indicator to the left of the key pad will
also light.

STATUS (3)

When key pad STATUS and then DISP are pressed, the content of
the Status Register is displayed in the 4-bit octal readout (Figure
1-5). The STATUS indicator to the left of the key pad will also light.
The six most significant bits of the Status Register (bits 0-5) indicate either a set or cleared condition (logical one or logical zero).
Thus, the octal readout for these digits must be decoded to determine whether the bit is set or cleared.

First
Digit
Position

Illegal Characters
2, 3, 6, and 7

An octal 4 or 5 indicates that the link is set. An octal 1 or 5 indicates
that the Omnibus interrupt request line i s asserted.

Table 1-4 (Cont)
PDP-8/A Programmer's Console Controls and Indicators
Control or Indicator
Key Pad Switches (Cont)
Second
Digit

Function

An octal 4, 5,6, or 7 indicates that the INTERRUPT INHIBIT flipflop is set. The INTERRUPT INHIBIT flip-flop is located in the
memory extension and timeshare option.
An octal 2,3, 6, or 7 indicates that the interrupt system i s enabled.
An octal 1,3, 5, or 7 indicates that the USER MODE line i s
asserted. Signal USER MODE originates in the memory extension
and timeshare option on the Extended option board to disable execution of all OSR, LAS, HLT and IOT instructions when the computer is operating in Timeshare mode.

Third
Digit

Displays the content of the 3-bit instruction field register (IFO-2)
contained in the memory extension and timeshare option on the
extended option board.

Fourth
Digit

Displays the content of the 3-bit data field register (DFO-2) contained in the memory extension and timeshare option on the extended option board.
When key pad switch SR and then DISP are pressed, the content of
the SR (switch register) will be displayed in the 4 character octal
readout. The SR indicator to the left of the key pad will also light.
When key pad switch STATE and then DISP are pressed, the condition of the major states, 3 bits of the instruction register (I RO-2),
and 6 major Omnibus signals are displayed in the 4 character octal
readout (Figure 1-6). The STATE indicator to the left of the key
pad will also light. The octal readout must be decoded to determine
if the individual bits are in a set or cleared condition (a logical one or
a logical zero).

STATE (5)

First
Digit
Position

Illegal Characters
3,5,6, and 7

A zero indicates that the processor is in the DMA state.
An octal 1 indicates that the processor is in the Execute major state.
An octal 2 indicates that the processor is in the Defer major state.
An octal 4 indicates that the processor is in the Fetch major state.

Second
Digit

Displays the content of the 3-bit Instruction Register (I RO-2).

Table 1-4 (Cant)
PDP-8/A Progranlmer's Console Controls and Indicators
Control or Indicator
Key Pad Switches (Cont)
Third
Digit

Function

An octal 4, 5, 6, or 7 indicates that the MD DIR line on the Omnibus
i s asserted. Signal MD D IR is low and bit 6 i s a logical one during
operations that read data from memory. MD DIR is high and bit 6
is a logical 0 during operations that write data into memory.
An octal 2,3, 6, or 7 indicates that BREAK DATA CONT line on the
Omnibus is asserted. BREAK DATA CONT i s low and bit 7 is a
logical one during some direct memory access (DMA) operation.
An octal 1,3, 5, or 7 indicates that the SW line on the Omnibus is
asserted. This occurs only when BOOT on the Programmer's Console
or the Limited Function Panel is pressed.

Fourth
Digit

An octal 4,5, 6, or 7 indicates that the I10 PAUSE line on the
Omnibus is asserted. Signal I10 PAUSE L is generated during the
execution of an IOT instruction.
An octal 2, 3, 6, or 7 indicates that the BREAK IN PROG line on the
Omnibus i s asserted (one or more devices are requesting a data
break). The highest priority device will begin a DMA operation a t the
beginning of the next cycle.
An octal 1,3, 5, or 7 indicates that the BREAK CYCLE line on the
Omnibus i s asserted (a DMA operation is taking place).
When MD and then DISP are pressed, the data on the 12-bit
MEMORY DATA bus (MDO-11) on the Omnibus are displayed in
the four character octal readout. The bus normally carries the content of the l a s t memory location addressed by the 15-bit memory
address register.
Pressing LA (load address) loads the contents of the entry into the
Central Processor Memory Address (CPMA) register and enables the
FETCH major state for the next processor cycle.

LXA

Pressing LXA (Load Extended Address) loads the right-most digit of
the entry into the Data Field (DF) register and the next digit of the
entry into the instruction Field (IF) register.

INIT

Pressing INIT (Initialize) generates an INIT pulse that clears the AC,
the LINK, all I10 device flags and registers, and all interrupt system
flip-flops. This i s equivalent to a programmed CAF instruction.

RUN

Pressing RUN generates a MEM START L signal, and sets the RUN
flip-flop. The program starts executing a t the address that is in the
CPMA register.

Table 1-4 (Cont)
PDP-8/A Programmer's Console Controls and Indicators
Control or Indicator
Key Pad Switches (Cont)
LSR

Function

Pressing the LSR switch loads the entry into the Switch Register.
The Switch Register serves as a 12-bit temporary storage register for
data entries. The contents of the Switch Register can be read under
program control by the OSR and LAS instruction.

BOOT

Pressing BOOT twice causes the SW flip-flop to assert and then
negate the SW line on the Omnibus. The transition from assertion to
negation of the SW line causes a bootstrap operation to be performed. The signal from this BOOT switch is ORed with the signal
generated by BOOT on the Limited Function Panel so that either
switch can assert the SW signal on the Omnibus.

E THIS

Pressing E TH IS (Examine This) loads the contents of the memory
location addressed by the CPMA register into the Memory Buffer
(MB) register. The CPMA and PC are not incremented after this
operation. To observe the content of the MB, press MD, then DISP.

E NEXT

Pressing E NEXT (Examine Next) loads the content of the memory
location addressed by the CPMA into the Memory Buffer (MB) register and increments the CPMA and PC registers. This feature allows
the operator to step through a program and observe the operation
of one of the major registers, buses, etc., in the octal readout.

D THIS

Pressing D THIS (Deposit This) loads the content of the entry into
the MB register and into memory a t the address specified by the
CPMA register. The CPMA and PC are not incremented by this
operation.

D NEXT

Pressing D NEXT (Deposit Next) loads the content of the entry into
the MB register and into memory a t the address specified by the
CPMA register. At the end of the operation, the PC and CPMA registers are incremented.
Pressing HLTISS (HaltISingle Step) while the machine is running will
cause it to stop. If the machine i s stopped, pressing HLT/SS causes
the machine to execute one machine cycle.

FIRST
DIGIT OF
OCTAL
DISPLAY
A

LINK

1
NOT
USED

T
!:i

THIRD
DIGIT OF
OCTAL
DISPLAY

SECOND
D I G I T OF
OCTAL
DISPLAY

INTERRUPT
ENABLED

INTERRUPT
INHIBIT

FIRST
DIGIT OF
OCTAL
DISPLAY

IFO

DFI

Status Information

SECOND
DIGIT OF
OCTAL
DISPLAY

THIRD
DIGIT OF
OCTAL
DISPLAY

IR1
IRO

IF2

IFI

US'ER
MODE

Figure 1-5

DEFER

FOURTH
D I G I T OF
OCTAL
DISPLAY

MD DIR

1R2

FOURTH
D I G I T OF
OCTAL
DISPLAY

BREAK DATA
CONT

BREAK
I N PROG
PAUSE
BREAK
CYCLE
08-1149

Figure 1-6

State Information

CHAPTER 2
INSTALLATION A N D ACCEPTANCE TEST

This chapter contains supplementary information and procedures for installing the PDP-8/A Computer System. Basic
installation and planning information, such as space requirements, environmental requirements, installation requirements, and system configuration data, are provided in Chapter 13 of the PDP-8/A Miniprocessor Handbook. Installation functions are summarized in Table 2-1.
All PDP-8/A computers and modules are tested thoroughly at DIGITAL'S manufacturing facilities before they are shipped.
However, many switches and jumper wires can be arranged by the customer for specific purposes; furthermore, there is a
need both to verify the accuracy of system interconnections and site preparations, and to detect possible hidden damage
incurred during shipping. Consequently, a number of initial operating tests are also included in this chapter.

Table 2-1
Summary of Installation Functions
Identify space and power required for system configuration.
Survey proposed site
Prepare site in accordance with environmental space and power requirements.
Unpack equipment and check inventory checklist.
Install equipment.
Run acceptance test.
Enter results of acceptance test in log book.

2.1 SITE CONSIDERATIONS
Adequate site planning and preparation can simplify the installation process and result in an efficient, more reliable
PDP-8/A system installation. DEC Sales Engineers or Field Service Engineers are available for counseling and consultation with user personnel regarding the installation.
Site planning should include a list of the actual components to be used in the installation; this list should also include such items as storage cabinets, supplies, work tables, etc.
Primary planning considerations are:
1.

The availability and locations of adequate power

Protection against direct heat sources

Electrical noise radiation

Shock

The existence of fire protection devices.

If existing environmental conditions dictate, air conditioning and/or dehumidifying equipment (though not required for
the PDP-8/A) can become part of the site planning program.
2.1.1 Power Source
The power source should be free from conductive interference. In addition, all computer system supplies should be
connected to the same power source to avoid loading and source differentials that may affect computer operation.
2.1.2 1/0 Cabling Requirements
The cabling for rack-mounted equipment can be routed into the chassis through an opening located in the rear of
the chassis. Subflooring is not necessary because casters elevate the cabinet high enough to provide sufficient cable
clearance. The cabling should be located where it cannot be damaged. This is especially important if the processor
and peripherals are not in close proximity.
2.1.3 Fire and Safety Precautions
The PDP-8/A Power Supply contains a thermal cut-out switch, circuit breaker, and fuses for protection against overheating and overloading. Both the cabinet and 'the power receptacle must be adequately grounded to ensure safe operation. A water pipe or steel beam provides an adequate ground. Refer to Chapter 13 of the PDP-8/A
Miniprocessor Handbook for grounding and povver installation procedures.
WARNING
The frame of the computer must be grounded to protect personnel from dangerous electrical shock.
Grounding is achieved automatically when a 3.-wire plug is used. However, a voltage reading from frame t o ground
should be performed initially.
Electrical fires, although extremely unlikely, should always be extinguished by a Class 3 (C02) fire extinguisher.

2.2 UNPACKING INSTRUCTIONS
All PDP-8/A computers are packaged in two containers, the inner container holding the computer, and a type of protective material. The steps in this section are sufficiently general to apply to any PDP-8/A. To unpack the PDP-8/A
computer, proceed as follows:
Open the outer carton and remove the inner carton.
Open the inner carton.
Carefully remove the cardboard from the top and sides of the computer.
Carefully remove the computer from the box.
Inspect the computer for damage. If the computer is damaged, notify the carrier immediately.
Unpack any other boxes included in the shipment.
Check that all equipment, software, manuals, etc., are present as specified on the shipping list inside the
carton.
Save the cartons and packing material to use if the PDP-8/A is later repacked.

2.3 PACKING INSTRUCTIONS
Two kinds of packages are used for PDP-8/A computers. The kind used and the applicable packing instructions depend
on the type of PDP-8/A chassis assembly.
2.3.1 BA8-C Chassis Assembly
The 8A420, 8A620, and 8A820 computers use a BA8-C chassis assembly (20-slot Omnibus). Figure 2-1 illustrates the
packing procedure. First, the computer is placed in the inner container (990541 7), the empty space is filled with plastic
protective material (AIR CAP, SD-120), and the container is sealed. The sealed inner container is surrounded with
protective foam material which is enclosed by the two telescope caps. Finally, the package is secured by two plastic
straps.
2.3.2

Other PDP-8/A Chassis Assemblies
CAUTION
The G8016 Regulator board assembly used on PDP-8/A
semiconductor computers contains a battery. This battery, while not of sufficient voltage to cause electrical
shock, represents a possible hazard if shorted. If repacking this type of computer, ensure that there is no loose
metal, such as solder, wire, or sheet metal parts inside
the cabinet.

The PDP-8/A semiconductor computer and the 8A400,8A600, and 8A800 computers use a chassis assembly that has a
10-slot or 12-slot Omnibus. To pack these computers proceed as follows:
1.

Place the computer in the smaller of the two shipping cartons with the back (side with power cord) of the
computer against the side of the carton.

Place the beveled die-cut sheet with foam protector (part number 9905675) in front of the computer (Figure
2-2). If the Limited Function Panel and a pop panel are on the computer, the beveled edge should be down
inside the carton. If the computer has a Programmer's Console, the beveled edge should be up so that the
cut-out in the cardboard fits the Programmer's Console.

Place the die-cut sheet with foam (part number 9905667) downward over the computer. The end with two
pieces of foam should be fitted around the fans and the other end should be positioned so that the cardboard
fits behind the cabinet mounting flange and the foam is against the side of the carton.

Close the flaps and seal the carton with tape.

Surround the sealed carton with protective foam material and enclose with telescope caps (Figure 2-3).

Strap in both directions using steel or plastic strapping.

FOAM PAD
(9905648 1

PACKAGED OPTION IN BOX
(990541 7 1

FOAM PAD
(9905648)

FULL TELESCOPE CAP

Figure 2 - 1

8 A 4 2 0 , 8 A 6 2 0 , 8 A 8 2 0 Packaging

SLOTTED
9905649)

Figure 2-2

PDP-8/A Computer Packaging (Inner)

PACKAGED OPTION IN BOX

FOAM PAD

CORRUGATED

Figure 2-3

PDP-8/A Computer Packaging (Outer)

2.4 PDP-8/A BASIC SYSTEM COMPONENTS
A PDP-8/A basic system comprises many components. The following three systems are the most common:
1.

A basic* PDP-8/A, a memory, and a Limited Function Panel.

A basic PDP-8/A, a memory, a Limited Function Panel, a KM8-A Extended Option board, a DKC8-AA I/O
Option board, and a Programmer's Console (Paragraph 2.6 describes operating tests for this system).

A system as described in type 2 above, but accompanied by a TeletypeB and diagnostic* * programs (Paragraph 2.8 describes operating tests for this system).

As Table 1-2 indicated, a PDP-8/E CPU (KK8-E) can be used with the PDP-8/A system (8A600 and 8A620). In addition
to the CPU, most DIGITAL PDP-8/E options will operate with the PDP-8/A computers. The following will not:
1.
2.
3.
4.

KP8-E Power Fail/Auto-Restart option
DK8-EA Line Frequency Real-Time Clock option
MM8-E 4K Core Memory
MM8-EJ 8K Core Memory

The KE8-E option (Extended Arithmetic Element) and the TD8-E DECtape Control will operate only with the 8A600 and
8A620 computers.
Modules can be inserted in almost any PDP-8/A Omnibus slot. There are, however, some restrictions and these are
summarized in Table 2-2. Notice that an M8320 module (Bus Loads) is inserted in slot 1 of the 8A600 and 8A620
computers. This module must be modified before it can be used in the 8A600 and 8A620 computers. If the modification
has been accomplished, R55 (Figure 2-4) will have been removed; if R55 is present, carry out the procedure outlined in
DEC ECO M8320-00007.

Figure 2-4 Part of M 8 3 2 0 Module Showing R55,
Which is Removed for 8A Operation

@Teletype is a registered trade mark of Teletype Corporation, Skokie, Illinois.
A

basic PDP-8/A is defined as a Central Processor Unit (CPU) and a chassis assembly (chassis, Omnibus, and power supply).

' Diagnostics are test programs written to find faults in the logic. The PDP-8/A programs are supplied on paper tape. Diagnostic programs are optional
and may be ordered from the Software Distribution Center, 146 Main Street, Maynard, Massachusetts 01754.

Table 2-2
PDP-8/A Computers, Dedicated Omnibus Slots

PDP-8/A Semiconductor,
8A400,8A420,8A8001 8A820

Omnibus Slot

Note 1: M8316 and M8317 are interchangeable in slots 2 and 3.
Note 2: Module numbers are related to options as follows:
M8315 - CPU ( K K ~ - A )
M8316 - I10 Option Board (DKC8-AA)
M8317 - Extended Option Board (KM8-AA)
1
M8320 - Bus Loads

M8330 - Timing en era tor

2.4.1 Chassis Descriptions
Three chassis types are available. The PDP-8/A Semiconductor computer chassis is illustrated in Figure 2-5 (the front
panels have been removed). Modules are inserted in the Omnibus from the front of the unit. Both quad- and hex-size
modules can be inserted; the fingers on connectors E and F of the hex size modules do not carry Omnibus signals (some
hex modules do not have connectors E and F). Figure 2-6 illustrates the dimensions of the same computer, as well as
indicating the ac line and fuse locations.

POWER
CONTROL
FUSE

REGULATOR
ASSEMBLY

MASTER-SLAVE
SWITCH

CABLE TO CONNECT
LIMITED FUNCTION
PANEL
7288-4

Figure 2-5

PDP-8/A Semiconductor Chassis

NOTE:
applied
ac pow

If you
advised

Figure 2-6

PDP-8/A Semiconductor Computer
Chassis Dimensions

Figure 2-7 shows the chassis that is used with 8A400,8A600, and 8A800 computers. The dimensions are the same as
the PDP-8/A Semiconductor chassis; interior components are different. The G8018 regulator assembly has been removed to show the connector in which the assembly is inserted. The Omnibus connector blocks in the connector E position
are needed to accommodate the E connector of the core memory modules.
Figure 2-8 shows the chassis used with the 8A420, 8A620, and 8A820 computers. The example shown is an 8A620,
containing the KK8-E CPU and Timing Generator, as well as the Bus Loads module. The H9195 Omnibus is mounted on
the Center Wall assembly (DEC Part Number 70-12561 ); modules are inserted from the front of the unit. Two G8018
regulator assemblies are contained in the rear of the chassis; the regulator boards are inserted in PC board slots that are
mounted on the rear of the Center Wall assembly. Figure 2-9 is an outline drawing that gives the chassis dimensions and
illustrates the placement of the G8018 assembly.

CORE
MEMORY
SLOTS

REGULATOR
BOARD SLOT

POWER
CONTROL
FUSE

Figure 2-7 PDP-8/A Chassis (H9300)
(Transformer Cover Removed)

CABLE TO CONNECT
LIMITED FUNCTION
PANEL

Figure 2-8

PDP8/A Chassis
(8,4240, 8A620, 8A820)

10.44 in.

2.4.2 Expansion Techniques
Table 1-2 noted that the 8A600 and 8A620 computers could be expanded, Either a BA8-C or an H9300 can be added to
the basic chassis increasing the system capacity accordingly. Figure 2- 10 illustrates the basic chassis and the expansion
possibilities available for each type.

Figure 2- 10

8A600/8A620 Expansion

The basic chassis is connected to the expander chassis by BC08H cable assemblies. One cable connector is inserted into
either the top slot or the bottom slot of the basic chassis, depending on whether the expander chassis is located above or
below. The other connector is inserted into slot 1 or slot 20 of the expander chassis. If the 8A620 is being expanded with
an H9300 chassis assembly, the M8300, M8310, and M8330 modules must be removed from the basic chassis and
placed in slots 10, 11, and 12, respectively, of the expander chassis. If the computer includes a KE8-E option, this too
must be removed from the basic chassis and inserted in the appropriate Omnibus slots of the expander. Refer to the
PDP8 Configuration Guide for definitive guidelines concerning expansion.

2.4.3 PDP-8/A Module Descriptions
The major units that constitute a PDP-8/A are described in the following paragraphs, along with the module switch
settings.
CAUTION
Switch settings may be accidentally changed unless
modules are removed and inserted carefully.
2.4.3.1 KK8-A Central Processor Unit (CPU,) - The KK8-A, shown in Figure 2-1 1 is a multilayer hex module
(M8315) which resides in the top slot of the Omnibus. The KK8-A has an auto-start feature used to start the computer
automatically when power is turned on.
NOTE
If you are not using the CPU Auto-Start feature, turn
switch S1-7 ON and switches S1-1 through S1-6 and
S1-8 OFF.
If you are using the CPU Auto-Start feature, set switches
3s shown in Table 2-3.

REVISION LETTER
O N UNDERSIDE OF
BOARD

Figure 2-1 1

KK8-A iM8315) CPU Module

Table 2-3
KK8-A (M8315) Central Processor Unit Switch Settings
Switch

Function (When in the ON Position)
Start in field 7 (OFF position specifies Field 0)
Start a t address 4000
Start a t address 2000
Start a t address 1000
Start a t address 0400
Start a t address 0200
CPU Auto Start Disabled
OFF

Starting address 0000 may be selected by leaving switches S1-2 through S1-6 all OFF. Only one switch in the group S12 through S1-6 may be ON at any time. Failure to observe this precaution will result in a malfunction, even if the autostart feature is not used,
2.4.3.2 MS8-A Read/Write Random Accoss Memory (RAM) - The MS8-A, shown in Figure 2-12, is a quad
module (M8311). semiconductor, read/write Random Access Memory available in the following configurations:

Option

Memory Size

Module Number

NOTE
If you are using a 4K R A M i n Field 0, set switches S11. 2, 3, 4, 5, 6 and 10 ON and turn S1-7, 8, and 9
OFF.
Set switches as shown in Table 2-4 if other memory configurations are used.
2.4.3.3 MR8-A Read Only Random Access Memory (ROM) - The MR8-A, shown in Figure 2-13, is a quad module
(M8312), Read Only Random Access Memory,, available in the following configurations:

Option

Memory Size

Module Number

THESE CHIPS NOT
PRESENT ON M8311-YA

CONNECTOR TO MR8-A
I F 13TH BIT MS8-AlMR8-A
ROMIRAM CONFIGURATION
IS USED

THESE CHIPS NOT
PRESENT ON M8311-YA
OR M8311-YB

Figure 2-12

MS8-A (M8311) Read/Write Random Access Memory

Table 2-4
MS8-A Readmrite Memory Switch Settings
Switch

S1-1,2, and 3

Field Selection

S1-1
ON
OFF
ON
OFF
ON
OFF
ON
OFF

S1-4 and 5

S1-2
ON
ON
OFF
OFF
ON
ON
OFF
OFF

S1-3
ON
ON
ON
ON
OFF
OFF
OFF
OFF

Field Selected
0
1
2
3
4

S1-5
ON
OFF
ON
OFF

First Address in this R A M is
0000
2000
4000
6000

5
6

First Address
S1-4
ON
ON
OFF:
OFF

ON for 4K Memory M8311-YD
OFF
ON for 2K: Memory M8311-YB
ON for 1Kl Memory M8311-YA
Test switch, normally ON

THESE THREE CONNECTORS ARE REMOVED
T O PROGRAM T H E ROM, BUT T H E Y MUST
BE I N PLACE FOR NORMAL OPERATION

Figure 2 - 1 3

CONNECTOR T O MS8-A
IF 13TH BIT MS8-AlMR8-A
ROMIRAM CONFIGURATION
IS USED

M R 8 - A ( M 8 3 1 2 ) Read Only Memory (ROM)

The first address is always location 0000 of the selected memory field.

NOTE
If you are using a 4K ROM i n Field 0 with no connections
t o RAM, set swiitches as follows: 8 1 -1 through S1-8; S61 through S6-8; S7-1 through S7-8; S8-1 through S8-8;
S9-1 through S9-8; S4-1, 2, 3, 6, 7, 8; and S6-3, 8; all
ON. S2-1 through S2-8; S4-4, 6; S6-1, 2; all OFF. If a
R A M is used with top connectors, change S4-7 t o OFF.
Table 2-5 lists the switch settings for other memory configurations.

CAUTION
All switches must be OFF when the M8312 is being
programmed (i.e., while data is being loaded into
ROM).
Table 2-5
MR8-A Read Only Memory Switch Settings
Switch
S1-1 to S1-8
S2-1, 8, and 5

Size Select Switch Settings
S2-1
ON
ON
OFF

S2-8
ON
ON
OFF

S2-2 and 4

OFF

S2-3,6, and 7

Field Select Switch Settings
Field
0
1
2
3
4
5
6
7

S2-6
OFF
ON
OFF
ON
OFF
ON
OFF
ON

S2-5
OFF
OFF
OFF

Memory Size
1K
2K
4K

S2-3
OFF
OFF
ON
ON
OFF
OFF
ON
ON

S2-7
OFF
OFF
OFF
OFF
ON
ON
ON
ON

84-1, 2, 3,4, 6, and 8
84-5
S4-7

OFF for ROMIRAM Combination; otherwise ON

S6-1 and S6-2
S6-3,4, 5, 6, 7, and 8

OFF
0N

2.4.3.4 MM8-AA 8K Core Memory - The MM8-AA, shown in Figure 2-14, is a hex module (G649) with H219A
stack assembly that contains 8K of core memory.
NOTE
If you are using core memory i n fields 0 and 1, install
W1-3 and W1-2 and remove W2-4 and W3-4.
Install or remove jumpers as shown in Table 2-6 if other memory fields are in use.

Table 2-6
MM8-AA 8K Core Memory Jumper Installation
Fields Used

W1-3

W1-2

W2-4

W 3-4

0 and 1
2 and 3
4 and 5
6 and 7

IN
OUT
IN
OUT

IN
IN
OUT
OUT

OUT
IN
OUT
IN

OUT
OUT
IN
IN

2.4.3.6 MM8-AB 16K Core Memory The M M8-AB, shown in Figure 2-1 5, is a hex module (G650) with H2 1 9 E
stack assembly that contains 16K of core memory.
NOTE
If the MM8-AB is installed in fields 0 through 3, jumpers
W1-3 and W1-2 should be installed and W2-4 and W3-4
should be removed.
Install or remove jumpers as shown in Table 2-7 if other memory fields are used.

Table 2-7
MM8-AB 16K Core Memory Jumper Installation
Fields Used

W1-3

W 1-2

W 2-4

W 3-4

0 to 3
4 to 7

IN
OUT

IN
IN

OUT
IN

OUT
OUT

Figure 2-1 4

M M8-AA Core Memory

Figure 2- 1 5

M M 8 - A B Core Memory

DKC8-AA I/O Option Board - There are t w o DKC8-AA hex modules (M8316) in existence; one is defined as
2.4.3.6
etch revision C (shown in Figure 2 - 16), the other as etch revision D (shown in Figure 2 - 17). The etch revision is identified
on side 2 of the PC board (side 1 is the component side). Lettering similar t o the following appears near the lower right
corner (when viewing side 2).
Option Board 1
Side 2
M8316
501 0900D
The letter D indicates the D etch revision. The information in this section is not totally applicable to each revision level;
differences that exist are indicated in the description.
The DKC8-AA combines four options:
1.

Serial Line Unit (SLU), 1 1 0 to 9 6 0 0 ( 5 0 to 9 6 0 0 for revision D) baud rate interface for Teletype, VT50, or
other compatible serial line unit.

Real-time Clock - Crystal controlled at 1 0 0 Hz.

General Purpose Parallel I/O - 12-bit I/O for user's device or another PDP-8/A.

NOTE
The General Purp~oseParallel 1/0 on the D etch revision
of the M8316 module can be used as an interface for the
LA180. Data t o the LA180 must be supplied i n complemented form. The lOTs are different from the LA8
interface designed for the LA180. A BC80-A cable, available from DIGITAL, must be used t o connect the General
Purpose Parallel I/O (J6) t o the LA180.
4.

Console Logic - Logic t o connect the KC8-AA Programmer's Console to the Omnibus.

NOTE
Revision C: For Teletype (ASR-33) operation without
real-time clock software, set switches S1-4, 6, and 8 t o
the ON position; set switches S1-1,2,3, 6, and 7 t o the
OFF position.
Revision D: For Teletype (ASR-33) operation without
real-time clock software, set switches S1-1, 3, 4. 6, 8,
and 9 to the ON position; set switches S1-2, 6, and 7 t o
the OFF position (S1-10 is a spare).

For other operation, set switches as shown in Tables 2 - 8 and 2-9.

REVISION LETTER
ON UNDERSIDE
O F BOARD (SIDE 2)

J5
PARALLEL 1/0
TRANSMIT

J2 PROGRAMMER'S
CONSOLE (CONNECTS)
TO BOTTOM CONNECTOR O F
PROGRAMMER'S CONSOLE

SIDE 1

C
J3
SERIAL
LINE U N I T

J4
PARALLEL I10
RECEIVE

S1-1

A
J1
PROGRAMMERS
CONSOLE

S1-10

Figure 2-1 7

D Etch Revision of DKC8-AA (M83 16)
I/O Option Board

Table 2-8
DKC8-AA I10 Option Board Switch Settings for C Etch Module

Function
-

81-2, 2 and 3

rate as shown below:
S1-1

S1-2

S1-3

OFF
OFF
OFF
OFF
ON
ON
ON
ON

OFF
OFF
ON
ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF
ON
OFF
ON

Baud Rate

Clear Data Available at Time State 1 (normally ON)
ON enables Real Time Clock
Test (normally ON, OFF for special testing)
ON for 1 stop bit, OFF for two stop bits
S1-8

ON enables TTY filter in 20 mA CKT (used only for 100 baud)

8071 -1

Table 2-9
DKC8-AA Option Board Switch Settings for D Etch Module
Switch
S1-1, 2, 3, and 4

Function
Baud rate as shown below:

ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
*OFF

ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF

S1-1

Baud Rate

ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19.2k

ON = Real Time Clock enabled
OFF = Real Time Clock disabled
ON = Test Switch (always ON)
ON = 1 Stop Bit in SLU character
OFF = 2 Stop Bits in SLU character
ON = ASRIKSR 33 DR35 filter in (across SLU 20 mA REC'V Leads
ON if Baud rate is 110 or below)
OFF = filter out
ON = TS1 clears DATA AVAIL flip-flop in Parallel I10 Section
OFF = DATA AVAIL not cleared by TS1
*Serial Line will not run at this Baud rate. This setting is not to be used.

KM8-A Extended Option Board - The KM8-A, shown in Figure 2 - 18, is a hex module (M8317) combining
2.4.3.7
the following options:
1.

Power Fail/Auto-Restart

Bootstrap Loaders - Provide commonly used I/O loaders.

Memory Extension and Timeshare Control

NOTE
I f you are using paper tape under control of the bootstrap
switches, no Auto-Restart, and timeshare enabled, set
the following switches ON: S1-1 through S1-4, S1-8,
S2-1, S2-6 through S2-7; set the following switches
OFF: S1-5 through S1-7, S2-2 through S2-4, and S2-8.
Other switch settings for the KM8-A are listed in Tables 2-10 through 2-13.

NOTE
There are t w o types of bootstrap ROM's used on the
KM8-A. E82 and E87 have different labels on them for
the t w o different bootstrap ROM's. Modules that have
E82 and E87 (Figure 2-18) labeled 87A2 and 88A2
should use Table 2-1 1 for switch settings. I f E82 and E87
are labeled 158A2 and 159A2, use Table 2-12 for switch
settings.

IS.

Â¥V

Figure 2-18

--35?3;-

v--^^ya

KM8-A (M8317) Extended Option Board

2-28

Table 2-10
Auto-Restart Select Switch Settings
Restart Address

S2-2

OFF
OFF
ON
ON

OFF
ON
OFF
ON

OFF
OFF
OFF
OFF

Table 2-11
Bootstrap Select Switch Settings
(for ROMs Labeled 8 7 A 2 and 8 8 A 2 )
Program

S2-5

S2-6

S2-7

S2-8

S1-1

S1-2

S1-3

Memory Address

'HI-LO RIM
RK8-E
*TC08
*RF08/DF32D
TA8-E

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

ON
ON
OFF
ON
ON

OFF
OFF
ON
ON
OFF

ON
ON
OFF
ON
ON

ON
OFF
ON
OFF
OFF

ON
ON
ON
OFF
OFF

7737
0024
7613
7750
4000

'May only be used with 4K of ReadIWrite Memory i n field 0.

Table 2-1 2
Bootstrap Select Switch Settings
(for ROMs Labeled 1 5 8 A 2 and 1 5 9 ~ 2 )

S2-5
Program

HI LO RIM
RK8-E
RX8-E
RF08lD F32D
TA8-E

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

---

S2-7

S2-8

S1-1

S1-2

S1-3

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
OFF

ON
ON
OFF
OFF
OFF

ON
OFF
ON
ON
ON

"0N
ON
ON
OFF
OFF

Memory Address

7737
0024
0033
7750
4000
--

Table 2-13
Bootstrap/Auto-Restart Switch Settings
Switches
~1-7

Feature

Start Switch
or Activating
Signal

Bootstrap Enabled and Auto-Restart Disabled

BOOT Key

OFF

Bootstrap Enabled and Auto-Restart Enabled

BOOT Key
or AC OK*

Bootstrap Disabled and Auto-Restart Enabled

AC OK*

OFF

Bootstrap Enabled and Auto-Restart Disabled

AC OK*

OFF

Bootstrap Enabled and Auto-Restart Disabled

AC OK* or
BOOT Key

OFF

Bootstrap and Auto-Restart Disabled

S2-1
Timeshare Enabled

OFF

Timeshare Disabled

S1-4
Bootstrap Activated in Run or Stopped State

OFF

Bootstrap Activated in Stopped State Only

Not Used

S1-5

*Starts if power voltage becomes adequate.

2.4.3.8
Semiconductor Memory Power Supply - The Semiconductor Memory Power Supply can supply 20 A at + 5
V. It will support only semiconductor memory (RAM and ROM). The G8016 regulator (Figure 2-18) plugs into a dedicated backplane slot near the bottom of the chassism.
The power supply has battery backup for power failures. The machine
will be totally supported for approximately 30-40 seconds after an ac line failure.
NOTE
All PDP-8/A Power Supply dc voltages are provided t o
drive logic inside the basic chassis. DIGITAL is not
responsible for the performance of the PDP-8/A if any dc
power is used outside the PDP-8/A chassis.

CAUTION

BATTERY
CHARGING
ADJUST

This area of the G8016 is normally covered with an
insulating shield. Removal of the shield exposes the
battery terminals. Should you accidentally short
these terminals with a ring or watchband, you
could receive a burn.

POWER FAIL UP POWER FAIL DOWN

7016-1 1

Figure 2-19

Semiconductor Memory Regulator Board (G8016)

NOTE
To enable control of the PDP-8/A power from the ONOFF Switch, set the MASTER/SLAVE switch to the
MASTER (to the right) position. (The switch is identified
in Figure 2-6.)
In the 8A computers the MASTER/SLAVE switch is mounted on the printed circuit board that includes the ON/OFF,
PANEL LOCK, and BOOT switches. This board is attached to the rear of the Limited Function Panel; remove the panel to
gain access to the MASTER/SLAVE switch. The switch is illustrated in Figure 2-20; if is shown in the MASTER position
(to the right when viewing the front of the switch).

2.4.3.9 Core Memory Power Supply Regulator
the currents specified:

- The core memory power supply supplies the following voltages at

It will support core memory. The G8018 regulator (Figure 2-2 1) plugs into a dedicated backplane slot near the bottom of
the chassis. (The board slot is pictured in Figure 2-7).

MASTE R/SLAVE
SWITCH

Figure 2-20

8A MASTEWSLAVE Switch

CIRCUIT
BREAKER

POWER OK LIGHT
(LIT WHEN ALL Dc
VOLTAGES ARE
PRESENT)

TOOL MUST
ENTER HERE
FOR +5V
ADJUSTMENT

ADJUSTMENT
TOOL MUST
ENTER HERE
FOR +20 VOLT
ADJUSTMENT +20 V ADJUSTMENT

+5 V ADJUSTMENT

-5 V FUSE
(2.5 A)

Figure 2-21

POWER
FA1L
UP

POWER
FAIL
DOWN

+20V FUSE
(4A)

G8Ol8 Core Memory Regulator Board

+15 V FUSE - 15 V FUSE
(2.5 A)
(2.5 A)
7404- 1

2.4.3.10 Limited Function Panel (Figure 2-22) The Limited Function Panel has three external switches and three
indicator lights (the MASTER/SLAVE switch is mounted in the rear of the panel for 8A computers).

7288-3

Figure 2-22

Limited Function Panel

Lights
1.

POWER light indicates the PDP-8/A is operating on ac power.

RUN light indicates the PDP-8/A RUN flip-flop is set.

The BATTERY CHARGING light indicates either that the power supply battery is being charged (PDP-8/A
semiconductor computer) or that both G8018 regulators are operating properly (8A420,8A620, and 8A820
computers). The light is present on the 8A400, 8A600, and 8A800 computers, but is not used.

Switches
1.

ON-OFF switch turns ac power on in the up position (this switch will not turn battery power on unless ac is
present). Turn power off before removing the power cord from the wall receptacle. Otherwise the PDP-8/A
will run on battery power for as long as the battery lasts.

On those systems having a Programmer's Console, the PANEL LOCK switch disables the following
switches: HLT/SS, E NEXT, E THIS, D THIS, D NEXT, LA, LXA, INIT, BOOT, and RUN. The down position activates the Programmer's Console; the up position panel-locks the console.

The BOOT switch initiates the bootstrap function (if it is enabled) on the KM8-A Extended Option Board
(M8317). It is normally left in the down position. This BOOT switch is not affected by PANEL LOCK.

2.4.3.1 1 KC8-AA Programmer's Console (Figure 2-23) - The Programmer's Console has seven-segment LED displays of the Extended Memory Address (EMA). Memory Address (MA), and the Status Register. The console can be
located up to 15 feet from the PDP-8/A. Two BC08R cables connect the console to the M8316 module (J 1 and J2).

08-1121

Figure 2-23

2.5

KC8-AA Programmer's Console

INSTALLING THE PDP-8/A AND TURNING POWER ON FOR THE FIRST TIME

2.5.1 Environmental and Power Requirements
Recommended operating conditions for the PDP-8/A are an ambient temperature of 5O to 50' C (4 1- 12 Z 0 F) and
a noncondensing relative humidity of 10-95%. Voltage requirements are 90-1 3 2 Vac single phase (using approximately 3.2 A), or 180-264 Vac single phase (using approximately 1.6 A). Line frequency may be 49-51 Hz or
59-61 Hz, depending on the power transformer used in the power supply. Check the label at the rear of the cornputer to determine the correct voltage and frequency.
WARNING
Be sure that the ac outlet provides a non-current-carrying ground.
2.5.2 Turning on the Computer for the First Time
After unpacking the computer, allow at least 3 0 minutes for the machine to stabilize to ambient temperature before
applying power. This time should be increased to one hour or longer when the difference between storage or shipping temperature and the operating ambient temperature exceeds 30Â F ( 17O C).

Install the equipment using the following procedure:
Check switch settings on all modules. (See instructions in Paragraph 2.4.3).
Ensure that the regulator circuit breaker is ON. (The breaker is pictured in Figure 2-6.)
Turn OFF the ON/OFF switch on the Limited Function Panel (Figure 2-22).
Ensure that all ac power is received from the same branch circuit if the system has more than one power
cord.
Plug in the power cord. If a power control is used, plug the power cord into the receptacle marked UNSWITCHED AC.
WARNING
D o n o t touch the computer after plugging it
in until proper grounding has been checked.
Before touching the computer, check frame to ground voltage to ensure that less than 10 Vac is present.
Without touching any metal part of the PDP-8/A, turn the power ON/OFF switch ON.
Repeat step 6. In case of difficulty, have an electrician check the socket into which the computer has been
connected (electrical connections a~reillustrated in Figure 2-24). If no difficulty is encountered, the computer
frame is properly grounded and there is no danger in touching it.
Power is now applied to the PDP-8/A. The fans should be running and the BATTERY CHARGING light should
light momentarily or stay on. (The light is not used in the H9300 chassis assembly.) If none of these occur,
check the MASTEWSLAVE switch (Paragraph 2.4.3.8). Turn the power OFF before checking the MASTER/SLAVE switch. This switch should be in the MASTER (to the right) position. Then turn the power ON. If
the condition still exists, refer to the basic maintenance section in Paragraph 2.10.
Turn the PDP-8/A power switch OFF and the Teletype LINE/OFF/ LOCAL switch to the OFF position.
Connect the Teletype signal cable to the short cable (DEC Part No. BC05M-1F, plugged into J3 of the
M8316) in the PDP-8/A. The cable connectors are keyed for proper mating.
Plug the Teletype into the same ac outlet as the PDP-8/A.
Turn power ON/OFF switch on the PDP-8/A to ON.
Turn the Teletype LINE/OFF/LOCAL switch to LINE. Only the hum of the running motor of the Teletype
and the PDP-8/A fans should be heard.
2.6 TESTING PDP-8/A WITHOUT PAPER TAPE DIAGNOSTICS
The procedures in this section are used to test the PDP-8/A computer from the Programmer's Console. No paper
tape diagnostic programs are required for these tests.

- - - - -- - - - --THESE
CONNECTIONS 1
PREMADE
ONLY I
AT THE
SERVICE 1
ENTRANCE 1

I
I

FRAME
GREEN WIRE OF
PDP- 8 / A POWER
CORD CONNECTS
T O T H I S PIN,

CURRENT

CONDUCTORS

117VOLTS
ACHOT

BLACK

WH!TE

WALL
RECEPTACLES
(FEMALE)

RETURN LINE

E A R T H GROUND - NO LOAD

BLACK

FRAME
GREEN WIRE 0,
PDP- 8/A POWER
CORD CONNECTS
TO THIS PIN

ONLY I
A T THE
SERVICE I
ENTRANCE 1

------ - - --

I
X-

NEUTRAL
RETURN L I N E

TO HIGH - Q U A L I T Y
GROUND, # 4 AWG
PLUG O F
COMPUTER

""^s C A R R Y I N G

I
I

-1

E A R T H GROUND - NO LOAD
- - - - CURRENT.FOR SAFETY PURPOSES

TO H I G H - Q U A L I T Y
GROUND, # 4 AWG
PLUG O F
COMPUTER
(MALE)

A VOLTAGE B E T W E E N T H I S W I R E A N D F R A M E I N D I C A T E S T H A T T H E R E C E P T A C L E I S ON A L I N E WHICH
I S A C O N S I D E R A B L E D I S T A N C E FROM T H E S E R V I C E E N T R A N C E ( T H E W A T T - H O U R M E T E R AND FUSE B O X )
A N D I S C A R R Y I N G S I G N I F I C A N T C U R R E N T T H I S VOLTAGE SHOULD NOT EXCEED 5 % OF T H E N O M I N A L L I N E
VOLTAGE.

Figure 2 - 2 4

PDP-8/A Electrical Connections

2.6.1 Programmer's Console
The Programmer's Console is shown in Figure 2 - 2 3 and is fully described in the PDP-8/A Miniprocessor Handbook and in
Paragraph 1.2. Its use in testing the PDP-8/A is described in detail in the paragraphs that follow.
2.6.2 Central Processor Test Routines
When no MAINDECs are available, small routines may be keyed into memory and run t o check PDP-8/A operation.
These tests will not completely check out a PDP-8/A, but will find the most common failures. All routines start at
address 0200. If any failures occur, carefully examine each instruction o f the routine. If the instructions are correct,
switch power off and check all o f the module switch settings (all memory contents are lost when power is switched
off and the routines must b e reloaded). If the routine is not entered properly, re-enter the routine and try to run
it again.
These routines are also useful when MAINDEC programs cannot be loaded because o f a hardware problem

2.6.3 Entering Test Routines from the Programmer's Console
The following procedure should be used t o run Routine 1, the first PDP-8/A test:
Press, in order, MD, DISP - this will let you see what you deposit.
Press, in order, 0 0 0 0 LXA - select memory field 0
Press, in order, 0 2 0 0 LA - start loading instructions at address 2 0 0
Press, in order, 7 0 0 1 D NEXT - deposit an instruction.
Press, in order, 2 3 0 0 D NEXT - deposit an instruction.
Press, in order, 5 2 0 1 D NEXT - deposit an instruction.
Press, in order, 5 2 0 0 D NEXT - deposit an instruction.
Press, in order, 0 2 0 0 LA - now get ready t o start at location 200.
Press, in order, AC, DISP - Do this to see the accumulator (AC).
Press, in order, INIT and RUN - start the program.
All other routines should be entered into memory using this procedure.
NOTE
If you make a mistake while you are entering a number, and you have not pressed D NEXT, LA etc., you
can correct the entry by re-entering the entire number.
The number appearing in the DISP indicator is the entry that the PDP-8/A will use.

2.6.4 Central Processor Test Routines
The following routines should be used t o check the CPU:
Routine 1
This program will increment the AC slowly so that the user can see that it is working. The internal numbering system of the PDP-8/A does not use 8 and 9.

/Increment the AC by 1 - start here.
/Increment a location and skip if it is zero,
/Jump back 1.
/Start program over again.

Routine 2
This routine should print a pattern of all printable characters. Omit this routine if your PDP-8/A is not equipped with
a Teletype, or similar terminal.

NOTE
Ensure that the Teletype is set to LINE for routines 2
and 3.

The following line will print out while this routine is running. Characters may or may not be printed after the letter Z,
depending on the column width of the terminal. These extra characters should be disregarded. Disregard the first line
printed.
!

#$%&I()"

0200
0201
0202
0203
0204

+,-./0123456789:;< = >?@ABCDEFGHIJKLM NOPQRSTUVWXYZ (Random Characters)
700 1
6046
6041
5202
5200

/Increment the AC by 1 - start here.
/Transmit.
/Am I done transmitting?
/No I am not done transmitting.
/Yes I am done. Jump back and start over

Routine 3
This routine will print what is typed on the terminal (echo characters). Type several lines of sentences, making sure
the terminal prints out what you type. Omit this step if your PDP-8/A is not equipped with a terminal.

/Has a key been pressed?
/No, go back and wait.
/A Key was hit, Read it.
/Transmit the character to the printer.
/Am I done printing?
/No. Go back one.
/Yes I am done. Let's go back to wait for another key.
Routine 4
The following program checks some of the operate instructions. The program should halt at location 0021 6 (ADDRS
should read 0021 7) with the AC cleared. (AC=0000)

/Clear the AC, then complement the AC.
/Increment the AC by 0202.
/Skip if AC=O, then clear the AC.
/Error halt. Computer should not halt here.
/Set the link to 1.
/Rotate the AC right one. The AC should then equal 4000.
/Skip if the AC bit 0 = 0 .
/Skip unconditionally.
/Halt. Computer should not halt here.
/Increment the AC by one.
/Byte swap, AC should equal 0140.
/Add 7 6 4 0 to 0 140.
/Skip if link equals 1.
/Halt on error.
/Good halt if AC = 0000.
Routine 5
The following routine tests the ISZ instruction. The program should halt at location 00207 (ADDRS should read
00210) with AC cleared (AC=0000). To read the AC, press AC and then the DISP button.

/Clear the AC and link.
/Store 0 in location 300.
/Index the AC.
/Index location 300.
/Jump back and do again.
/Done check if AC = 0000.
/Error (AC and location 3 0 0 should be zero).
/Good halt.

Routine 6
This routine tests the JMS instruction. This routine should halt with ADDRS = to 0021 5 with the AC cleared
(AC=0000). To read the AC, press AC and then the DISP button.

/Clear the AC and link.
/Zero Pass counter.
/Zero entry.
/JMS to subroutine.
/Return address written here.
/Get return address.
/Complement and index the AC.
/Add to known good return address.
/Skip on 0 AC.
/Error halt.
/Increment Pass counter.
/Do again.
/Good halt.
/constant.
Routine 7
This routine tests the Jump instructions. The program should halt at location 0 0 2 1 4 (ADDRS should read 0021 5).
Run this test twice.

/Jump 210.
/Error halt.
/Jump 206.
/Error halt.
/Jump 212.
/Error halt.
/Jump 204.
/Error halt.
/Jump 202.
/Error halt.
/Loop to do this program 4096 times.
/Start program over again.
/Good halt after 4096 passes.

2.7 LOADING THE R I M A N D BINARY LOADERS
Programs in binary format may be used in machines with 4K or more of Read/Write Memory. The RIM loader must
be used to load the Binary Loader. The Binary loader is then used to load a program in binary format.
The RIM and Binary Loaders reside in the highest 1 K of a 4K memory. Machines with less than 4K of memory require the RIM loader to be loaded at addresses in the lowest 1 K of memory. Use of the Binary Loader on machines
with less than 4K of Read/Write memory is not recommended because of the length of the Binary Loader routine.
Each test procedure will tell you where to load the RIM loader.

2.7.1 Loading the R I M Loader
The RIM Loader is a 17-instruction program needed to load the Binary Loader and other RIM formatted tapes. There are
two methods of loading the RIM loader: Manually loading each instruction through the Programmer's Console keys
(described in the next few paragraphs), and using the bootstrap option, if there is 4K or more of Read/Write memory and
the KM8-A Extended Option Board (M8317) is in the computer. If you use the second method, turn to Paragraph 2.7.3.

Enter RIM Loader through the Programmer's Console keys as follows:
Press keys from left t o right as ordered in the following steps ( 1 through 2 2 ) .
MD
0000

xxxx
6032
603 1
5357
6036
7106
7006
7510
5357
7006
6031
5367
6034
7420
3776
3376
5356
0000
0000

xxxx

DISP
LXA
LA
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
D NEXT
LA

/Enables memory data t o the readout display
/Sets instruction and Data field t o 0
/ADDRS should read the OXXXX value, see the
bottom of this table for the value of XXXX.
/DISP should read 6 0 3 2
/DISP should read 6 0 3 1
/DISP should read 5 3 5 7
/DISP should read 6 0 3 6
/DISP should read 7 1 0 6
/DISP should read 7 0 0 6
/DISP should read 7 5 1 0
/DISP should read 5 3 5 7
/DISP should read 7 0 0 6
/DISP should read 6 0 3 1
/DISP should read 5 3 6 7
/DISP should read 6 0 3 4
/DISP should read 7 4 2 0
/DISP should read 3 7 7 6
/DISP should read 3 3 7 6
/DISP should read 5 3 5 6
/DISP should read 0000
/DISP should read 0000
/ADDRS should be OXXXX*

X X X X If you have a 4 K RAM, enter 7756. If you have less than 4 K of RAM, enter 0 1 5 6 for loading all tests except version A of
the MS8-A test (Enter 1756 for this case only).

2.7.2 Checking the R I M Loader
After completing the RIM loader procedure, the program may be checked by repeating the first three steps and pressing E NEXT. Each time E NEXT is pressed, the next four digits of the program should appear in the DISP lights.
When you are sure RIM loader is in memory correctly, proceed t o the Binary Loader procedure, or load and run RIM
format MAINDECs (Paragraph 2.8) if you have less than 4 K of read/write memory in your system.
2.7.3

Loading the Binary Loader
NOTE
Do not use the Binary Loader procedure if the memory
size is less than 4 K .

Place the tape labeled Binary Loader ( D E C - 0 8 - L B A A - P M ) in the Teletype reader, w i t h the
START/STOP/FREE lever set t o FREE. Position the tape so that the printed arrow on the tape points toward
you, and the single row of data holes at the beginning of the tape is over the read head (Figure 2-25).

Ensure that the LINE/OFF/LOCAL switch of the Teletype is set to LINE, and the papertape reader's
START/STOP/FREE lever is set to the START position (Figure 2-26).

If the K M 8 - A A Extended Option Board ( M 8 3 1 7 ) is not available, the RIM loader must be loaded at this
time using the RIM loading procedure (Paragraph 2.7.1).

If the RIM loader was keyed in manually, press (in order) 7756, LA, INIT, and RUN. The RUN light
should be on. The Teletype reader should be reading tape.

If the KM8-AA Extended Option Board (M8317) was set up for Hi-Lo RIM, ensure that the BOOT switch
on the Limited Function Console is down; then press the BOOT key on the Programmer's Console twice.
The RUN light should go on and the Teletype reader should read tape.

If the tape fails to read in or stops before the end of tape, reload the RIM loader using the RIM Loader
procedure (Paragraph 2.7.1 ).

After the tape is read to the trailing single row of data holes, press the HLT/SS key. The reader should
stop reading tape. The Binary Loader should now be in memory.

LEADER : SINGLE ROW 0;

,
DATA HOLES ( HOLE "8")

PROGRAM DATA
08-0843

Figure 2-25

Paper Tape Leader

PAPER ROLL UNWINDS
COUNTER-CLOCKWISE

Figure 2-26

LT33 Teletype Controls

2-42

2.7.4

Loading Binary Formatted Paper Tapes
Press (in order) 7777, LA, MD, DISP and E THIS. The DISP register should read 5301. If it does not,
check the RIM Loader and reload the Binary Loader.
If the content of address 07777 was 5301, press 7777, LA, and LSR.
Place the binary formatted paper tape in the reader, with the single row of data holes over the read
head.
Place the Teletype LINE/OFF/LOCAL switch to LINE.
Place the reader switch in the START position.
Press (in order) INIT, then RUN. The reader should start reading tape.
The Programmer's Console RUN light should go out when the first bit of trailer (row of single data holes
at the end of tape) is over the read head. The reader should automatically stop. Move the reader lever to
STOP or FREE.
Press (in order) AC, then DISP. The DISP register should read 0000. If the DISP register does not equal
0000, the tape must be reloaded.
Now the program is ready to run.

2.8 TESTING THE PDP-8/A USING MAINDEC DIAGNOSTIC PROGRAMS
MAINDECs are test programs designed to test the KK8-A or KK8-E CPU, the DKC8-AA I/O Option Board, the KM8-A
Extended Option Board, and read/write memory. The minimum PDP-8/A system that can be tested with MAINDEC
programs consists of a box, an Omnibus, a power supply and the following options:
Option

Description

CPU

I/O Option Board
Programmer's Console
ASR-33 Teletype
with at least 1 K of Read/Write memory starting in location 0 0 0 0 of field 0.
The PDP-8/A read/write memory can be any of the following:
Memory
MS8-AA
MS8-AB
MS8-AD
MM8-AA
M M8-AB

Size, Type
1 K Semiconductor
2K Semiconductor
4K Semiconductor
8K Core
16K Core

If your machine has a MR8 Read-only Memory, you should consult your local Field Service representative before
attempting to run MAINDECs.

2.8.1 Central Processor Unit (CPU) Test
The Central Processor Test is a good overall test of the PDP-8/A, I t is recommended that this test be the only one
run unless specific problems are encountered.
The CPU Test checks the CPU for proper operation. The program first checks the HALT instruction (that's why the
program stops at step 7); then tests the remaining instructions.
T w o variations of the CPU test exist. One of these variations applies if the PDP-8/A has 4 K or more of ReadIWrite
memory; the other, if it has less than 4K. In the steps below, the steps which are memory-size-dependent are enclosed in boxes. You should enter the information or perform the operation indicated for your memory configuration
(refer t o sticker o n the back of the PDP-8/A).

Load RIM Loader (see Paragraph 2 . 7 . 1 ) , starting with one of the following addresses:

>or=4K: Load Bin Loader (See Paragraph 2.7.3)
4K: Skip this step

Place "PDP-8/A CPU Test" in paper-tape reader. Ensure that the headerltrailer code (hole "8") is over
the read head. Tape number is:

Run the appropriate loader

>or=4K: Press 0000 and LX.A.
Press 7 7 7 7 and LSR.
Press 7 7 7 7 and LA.

< 4K: Press 0 1 56 and LA.
Press I NIT.
Press RUN.
Tape will read into memory,

>or=K: Tape will stop automatically. Press AC, DISP. DISP indicators should equal 0 0 0 0 .

< 4K: Tape must be stopped when trailer is reached. Press HLT/SS.
5.

Set up location 0 0 2 1 in the program as follows:
Press 0 0 2 1 then LA.
Press 4 0 0 0 then D THIS.

Start Program as follows:
Press 0000 then LSR.
Press 0 2 0 0 then LA.
Press INIT.
Press RUN.

Program will stop (RUN Ight will go off) with ADDRS = 0 0 2 2 2 . Press STATUS and then DISP.
DISP indicators should equal 4 0 0 0 .
Press AC, then DISP.
DISP indicators should equal 7777.

Press RUN. Allow program t o run for 1 0 minutes. If no errors are detected the program will not halt.

While program is still running, press any key on the Teletype.
Program should halt.

2.9 ADDITIONAL DIAGNOSTIC TESTS
These programs should be run t o isolate specific problems. I t is not recommended that they be run as a periodic confidence check.
2.9.1 Memory Test
The M S 8 - A MOS Memory Test checks all locations in memory field 0 for proper operation. It relocates itself in memory and tests all o f memory not occupied by the program. This test assumes that the CPU is functioning correctly.
1.

Load RIM Loader (see Paragraph 2.7.1), starting with address:

U s e 1756 if the tape is the A revision (MAINDEC-08-DJMSA-A-PM). The revision letter is the single letter just before the final

PM.

Place tape labeled "1-4K M S 8 - A MOS Memory Test" (MAINDEC-08-DMSA-A-PM) in the paper-tape
reader.

Run RIM Loader using one of the following;

>or=4K: Press 0000, and LXA.
Press 7756, and LA.
<4K: Press 0 1 5 6 " and LA.
* Use 1756 if tape is the A revision (MAINDEC-08-DJMSA-A-PM).

Press INIT, then RUN.
Tape will read into memory.
Tape must be stopped when trailer is reached (press HLT/SS)

Set up location 0 0 2 1 :
Press 0 0 2 1 and LA.
Press 4 0 0 0 and D THIS.

Set up location 0 0 2 3 :
Press 0 0 2 3 and LA.
Do one of the following:

If 4K: Press 7777, and D THIS
If 2K: Press 3 7 7 7 , and D THIS
If 1 K: Press 1777, and D THIS,

Start program as follows:
Press 0000, then LSR.
Press 0 2 0 0 , then LA.
Press INIT, then RUN.

Allow program t o run for 5 minutes. There should be no halts. A t the end of 5 minutes, while program is
still running:
Press 0 4 0 0 , then LSR.
Program will halt,

2.9.2 DKC8-AA Test
The DKC8-AA I/O Option Test program tests for proper operation of the Serial I/O, Parallel I/O, and Real Time clock
contained o n the M 8 3 1 6 module. I n addition t o the paper tape(s), the following equipment is needed:
W 9 8 7 Quad Module Extender
Three Termi-point Jumpers (Available in a package of 100, type 9 1 5. Any length may be used, although 8 in.
is probably most useful).
BC08R cable (any stock length)
These items are supplied as a portion o f the PDP-8/A maintenance kit, and may also be ordered separately using
the numbers just mentioned. This test requires placing the DKC8-AA on a module extender; hence a table t o support the Programmer's Console or cables t o extend the panel cables should be available.
1.

Turn PDP-8/A power OFF. Without altering the M 8 3 1 6 switch settings, remove the M 8 3 1 6 from the
PDP-8/A. Be sure t o provide enough slack in the Teletype cable and the parallel I/O cables to allow easy
removal o f the module. Plug the W 9 8 7 Quad Extender into the slot previously occupied by the M 8 3 1 6 ,
and plug the M 8 3 1 6 into the extender. Remove the parallel I/O cables (if used) from J 4 and J5, marking
the cables so they can be properly reinstalled at the end o f this test. Plug one end of the BC08R cable
into J4. Plug the other end of the BC08R cable into J5. There should be one fold and n o twists in the
cable. D o not remove the Teletype cable or the cables to the Programmer's Console. Turn PDP-8/A
power ON.

Using the same procedure as for steps 1, 2, 3, and 4 o f the CPU test, (Paragraph 2.8.1)
load the tape into
memory.
CAUTION
Do not use the loading procedure for memory test.
The tape t o be loaded is:

>or=4K: MAINDEC-08-DJDKA-PB1
<4K: MAINDEC-DJDKA-PM 1

Without turning power off, remove the Teletype cable from J 3 and install three Termi-Point jumpers as
follows:

Change S t - 5 on the M 8 3 1 6 from OFF t o ON. Make n o other switch changes a t this time.
4.

Set up location 0 0 2 1 as follows:
Press 0 0 2 1 then LA.
Deposit one of the following numbers by entering i t via the numeric keys, then press D THIS:

Memory Size
1K
2K
4K
8K
16K

Enter
6000
6001
6003
6007
6017

Start program as follows:
Press 0000, LSR then LXA.
Press 0 2 0 0 , INIT then RUN.

Allow program t o run for 5 minutes. There should be n o halts while program is still running:
Press 0 4 0 0 then LSR.
Program will halt.
Then:
>or= 4K: Skip t o Step 9

< 4K: Continue o n t o Step 7.

(Omit if >or= 4K) Return S 1 - 5 t o off. Remove the Termi-point jumpers from J 3 and re-install the Teletype cable. (Be sure it is installed so the printed A o n the cable connector is at the same end as the
printed A on J3.) Load:

and then repeat steps 3, 4, and 5 of this test. Allow program t o run for 5 minutes (no halts). Then:
Press 0 4 0 0 then LSR
Program will halt.

(Omit if >or= 4K). Return S 1 - 5 to off. Remove the Termi-point jumpers from J 3 and re-install the Teletype cable as described in step 7.
Load:

and then repeat steps 3, 4, and 5. Allow program t o run for 5 minutes (no halts). Then:
Press 0 4 0 0 then LSR.
Program will halt.
9.

D o this step regardless o f memory size.
For a C etch revision: Set S 1 - 3 and S 1- 7 ON; leave S 1 - 5 ON.
For a D etch revision: Set S1-1, 2, 4, 5, and 7 ON; set S 1 - 3 OFF.
Continue for either revision.
Remove the Termi-point jumpers from J 3 .
Now connect:

Start program, as described in step 5, and allow program t o run for 5 minutes (no halts). Then:
Press 0 4 0 0 then LSR.
Program will halt.
Then do one of the following:

>or= 4K; Skip t o step 11
< 4K: D o step 1 0

10.

Skip this step if
or = 4K.)
For a C etch revision: Set S1-3, 5, and 7 OFF.
For a D etch revision: Set S1-1, 3, and 4 ON; set S1-2 and 7 OFF.
Continue for either revision.
Remove Termi-point jumpers from J3. Replace Teletype cable as described under step 7. Load

and repeat steps 3, 4, and 5. Allow program to run for 5 minutes. Then
Press 0 4 0 0 t h e n LSR.
Program will halt.
1 1.

Do this step regardless o f memory size.
For a C etch revision: Set S1-3 and S1-7 ON; set S1-8 OFF.
For a D etch revision: Set S1-1, 2, 4, and 7 ON; set S1-3 and S1-8 OFF,
Continue for either revision.

Press 0 0 0 0 then LSR.
Then do one of the following:

>or = 4K: Press 4 0 0 0 then LA.
<4K: Press 1 2 0 0 then LA.

Press INIT and then RUN.
The program should run for 3 0 seconds k 0.5 seconds from the time the RUN button is pressed; then
halt.
Now:

>or = 4K: Press 4023 or LA.
<4K: Press 1223 then LA.

Press INIT and then RUN.
Program will halt.
Turn on S1-3 and S1-7.
Turn off S1-8.
Press 0 0 0 1 and LSR.
Press RUN.,

WARNING
Do not press IN IT.
The program should run for 3 0 seconds

0 . 5 seconds, and then halt.

12.

D o this step regardless o f memory size.
Turn PDP-8/A power OFF.
For a C etch revision: Set S1-3, 5, and 7 OFF; set S 1 - 8 ON.
For a D etch revision: Set S1-1, 3, 4, 8, and 9 ON; set S1-2, 5, and 7 OFF.
Continue for either revision. Remove all Termi-point jumpers. Replace Teletype cable on J 3 , being sure the
pin letters o n the cable and board connector match. Remove the BC08R cable from J4 and J5. Re-install
parallel I/O cables (if used). Remove the W 9 8 7 Quad Extender from the PDP-8/A, and re-install the M 3 1 6 .
Be careful not to alter switch settings accidently while inserting the M 8 3 1 6 .

KM8-A Extended Option Board Test

2.9.3

NOTE
Make sure you have the correct diagnostic program.
is for M 8 3 1 7 modules havM A I N DEC-08-DJ KMA-Aing ROMs E82 and E87 labeled 8 7 A 2 and 88A2; M A I N DEC-08-DJKMA-13is for ROMs labeled 158A2 and
159A2.
The K M 8 - A Extended Option Board Test program tests the circuitry contained on the M 8 3 1 7 module. As in the previous test, the module under test is placed o n a W 9 8 7 Quad Module Extender t o allow the operator t o alter switch
settings without turning off power t o the PDP-8/A. Again, it is advisable t o have a table to support the Programmer's Console.
The following series of tests are designed for operation on a PDP-8/A with 4 K or more of memory, since t w o of the
three options on this module require at least 4.K of memory. Also available for this option are test programs which
will run in 1 K o f memory. Consult your local DIGITAL sales office if more information on the 1 K programs is
needed.
1.

Turn OFF power t o the PDP-8/A, and place the M 8 3 1 7 on the W 9 8 7 Quad Extender. The M 8 3 1 7 must
be plugged into slot 2 or 3 of the Omnibus.

Write on paper the position of all switches o n the M 8 3 1 7 , and then place all these switches in the OFF
position. Unplug the controllers for any bootstrappable options (such as the PC8-E, TA8-E, RK8-E controllers and the KA8-E Positive I/O adapter), but leave the Teletype connected.

Turn on power, and load RIM at address 7 7 5 6 using the keys. D o not attempt t o use the bootstrap - it
was disabled a t step 2. Load the Binary Loader (see Paragraphs 2.7.1 and 2.7.3).

Read in the tape (MAINDEC-08-DJKMA-PB) using the Binary Loader. (See Paragraph 2.7.4).

Set up location 0 0 2 1 as follows:
Press 0 0 2 1 then LA.

Deposit one of the following numbers (depending on memory size) by entering i t via the numeric keys
and then pressing D THIS.
Memory Size
4K
8K
12K
16K
32K

Enter
7003
7007
7013
7017
7037

Start program:
Press 0000, LXA, then LSR.
Press 0200, INIT, then RUN
Allow program to run for 1 0 minutes. Then:
Press 0 4 0 0 and LSR.
Program will halt.
Turn S2-1 on. Then:
Press 4255 then LA.
Press 0000, LSR, INIT, and then RUN.
Program will halt,
Set up for bootstrap test:
Press 4465, LA, INIT, then RUN.
Program will halt.
Test the paper tape bootstrap as follows:
Turn ON S2-5, S2-6, S2-7, S1-1, S1-2, S1-3, S1-6, S1-7, and S1-8. Make sure Teletype reader lever is in
either the STOP or FREE position.
Press:
BOOT
BOOT
H LT/SS
0000, then LSR
4401. LA, INIT, and then RUN
Program will halt with ADDRS = 0 4 4 6 2 if paper tape bootstrap is correct.

NOTE
There is no point in checking a bootstrap unless your
PDP-8/A is equipped with the option, (e.g., unless your
PDP-8/A is equipped with an RK8-E, do not bother t o
test the RK8-E bootstrap).
10.

Check any other bootstraps as follows:
Repeat step 8.
Set switches according t o Table 2 - 1 4 or 2 - 1 5, depending on the bootstrap you are testing.
Leave S1-6, S1-7, and S 1 - 8 ON.
Press:
BOOT
BOOT
H LT/S S

NOTE
There are t w o different types of ROMs for the M8317
module. Those modules that have ROMs labeled 87A2
and 88A2 should use Table 2-14 for bootstrap select
switch settings (siae Figure 2-18 for switch and ROM
locations). Those modules that have ROMs labeled
168A2 and 169A2 should use Table 2-16 for switch
settings.
Enter the value o f SR from Tables 2 - 1 4 and 2 - 1 5, then press in order;
LSR, 4400, LA, INIT, then RUN
Program will halt w i t h ADDRS = 04.462 if Bootstrap is correct.

Table 2-14
Bootstrap Switch Settings for ROMs (E82 and E87)
Labeled 87A2 and 88A2
Bootstrap

S2-5

S2-6

HI LO R I M
R K8-E
TC08
RF08lDF32D
TA8-E

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

ON
OFF
ON
ON

1 ON 1 ONF 1
OFF

OFF

ON
OFF
ON
OFF
OFF

ON
ON
ON
OFF
OFF

0000
0004
000 1
0002
0003

Bootstrap

HI LO RIM
RK8-E
R X8-E
RF081DF32D
TA8-E

Table 2-15
Bootstrap Switch Settings for ROMs (E82 and E87)
Labeled 158A2 and 159A2
S2-5

S2-6

S2-7

S2-8

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
OFF

ON
ON
OFF
OFF
OFF

ON
OFF
ON
ON
ON

ON
ON
ON
OFF
OFF

Make sure the BATTERY CHARGING light on the Limited Function panel is off. If this light is on, leave
PDP-8/A power on but do not attempt the following test until the BATTERY CHARGING tight is off.

NOTE
Unless you have experienced a recent
power failure while the PDP-8/A was running or have unplugged the PDP-8/A power
cord without first turning the ON/OFF
switch to OFF, it is very unlikely that the
BATTERY CHARGING light will be on by
the time you get to this test.
Turn ON S1-1, 3, 6, 7, and 8; S2-3, 5, and 7. Turn OFF S1-2, 4, and 5; S2-1, 2, 4, 6 and 8.
Enter the following:
Press 4 6 0 0 then LA.
Press 0000, LSR, INIT, then RUN.
PDP-8/A will halt.
Press 0002, LSR, INIT, and then RUN.
Without operating the panel ON/OFF switch, unplug the power cord of the PDP-8/A from the wall receptacle. ADDRS should display 04764, and the RUN lights on the Limited Function Panel and the Programmer's Console should be off.
Re-insert the power cord. The program should begin running again. Do not leave power cord unplugged
any longer than necessary, since the batteries will discharge.
Repeat step 15 four times.
Turn OFF power. Return the M8317 switches to the original positions, wrtten down at step 2. Remove
the W987 Quad Extender, and replace the M8317 in the PDP-8/A box. Be careful not to disturb the
switch settings on this module or any adjacent modules while so doing. Replace the Programmer's
Console.

2.9.4 Testing Extended Memories
A good test of extended memories, the CPU and the memory extension control may be made by running the 1 K to
32K Random Memory Reference Instruction Exerciser Test. This test may also be used in systems w i t h as little as
1 K of memory.
1.

Load RIM loader, as described in Paragraph 2.7.1 starting with one of the following addresses:

Place MAINDEC-08-DJEXA-PM i n paper-tape reader, enter same address as given for step 1, and press:
LA.
1000, then LXA.
INIT, then RUN.
Press HLT/SS when trailer is over read station.

Set up location 0021 by pressing:

0021 and LA
Memory Size
1K
2K
4K
8K
12K
16K
32K

Enter
4000
400 1
4003
4007
401 3
4017
4037

Enter number corresponding t o memory size from chart, then press D THIS.

Enter the following:
Press 0 0 0 0 then LSR.
Press 0200, INIT, and then RUN

Run t w o minutes for each 1 K of memory (4K: 8 minutes, 8K: 16 minutes, etc.).

2.1 0 BASIC PDP-8/A MAINTENANCE
Table 2-16 lists some basic PDP-8/A problem symptoms and their possible causes.

Table 2-16
Basic PDP-8/A Troubleshooting
Symptom

Possible Cause/Solution

No lights, fans not running

Fuse Blown. Power Switch is OFF. AC power not connected. MASTER1
SLAVE switch in wrong position.

Fans running, but no lights

Circuit breaker on the regulator assembly is OFF.

RUN light does not come on after
BOOT switch is activated

Check switches on KM8-A Extended Option Board (M8317). Switch
settings are in Tables 2-10 through 2-13.

BATTERY CHARGING light stays
on

The battery requires a minimum of 15 hours of charging after a complete
discharge. The light normally flashes on momentarily after power on if
battery has been fully charged.

RUN light comes on when power
switch is turned on

This function is switch selectable on KK8-A CPU Module (M8315) and
KM8-AA Extended Option Module (M8317).

RUN light stays on after AC power
is unplugged

Do not unplug AC power unless PDP-8lA power is shut off. The PDP-8lA
behaves as if there has been a power failure, and the battery supply takes
over.

Peripheral will not BOOT with
BOOT switch

BOOT switch on Limited Function Panel in wrong position, it should be
down. PANEL LOCK should be down. Check switches on the Extended
Option Board (M8317). Check baud rate switches on DKC8-AA I/O Option
Board (M8316). Switch settings are in Paragraph 2.4.3.6.

Machine remains powered even
with ONIOFF switch set t o OFF

Fuse in power control relay circuit i s blown. Set ON/OFF switch to OFF,
then unplug the power cord before attempting to change this fuse.

Light on the G8018 Regulator
board is out (8A computers).

Turn off power, remove regulator board, check +5 V circuit breaker
and -1 5 V, *I
5 V, and +20 V fuses.

CHAPTER 3
INTERFACING TO THE O M N I B U S

This chapter provides the necessary interfacing information for users to understand operation of the Omnibus or to
build a special interface for the PDP-8/A. It deals primarily with hardware design considerations required to build an
interface for the Omnibus. Programming information is contained in two other PDP-8 documents, Introduction to Programming and Programming Languages. A user who plans to write a program for his/her interface should be familiar
with these documents. However, DIGITAL has many device handlers and software packages the user may be able to
use as written, or modified, to operate devices with the PDP-8/A.
Signals are transferred from module to module on a device called the Omnibus. All PDP-8 modules and options that are
compatible with the PDP-8/A plug into the Omnibus. The Omnibus is an etched board with rows of connectors soldered
to it. The pin assignment is the same on all connectors. The Omnibus is comprised of 96 signals and provides the means
to transfer these signals from module to module.
There are many advantages to the Omnibus approach. Because all connectors on the Omnibus carry the same signals, a module can be placed anywhere on the bus with the following exceptions:
1.

The CPU must be plugged into either the top slot (slot 1) or the bottom 3 slots (refer to Table 2-2).

The PDP-8/A option boards must be plugged into slots 2 and 3 (either module in either slot). MOS memory cannot be plugged into slots 2 or 3.

All hex modules should be plugged into the top slots followed by quad modules in the lower slots.

OMNIBUS PHYSICAL DESCRIPTION
The Omnibus (Figure 3-1) consists of standard DEC H863 connector blocks mounted on an etched circuit board and
wave soldered. The connectors are arranged to accept hex and quad type modules (Figure 3-2). The Omnibus has 1 0
slots if it is a semiconductor machine and 12 or 2 0 slots if it is a core memory machine. Core memory machines use an
extra connector (E) to supply + 2 0 V and -5 V to the MM8-AA and MM8-AB core memory modules.
3.1

All pins on the Omnibus are parallel-wired (e.g., pin CM2 of slot 1 is wired to pin CM2 of slot 2) to form a parallel bus
comprised of 96 Omnibus signals. The parallel bus is used to connect the central processor, memory, peripherals, and
options. All modules must plug into the Omnibus.
The Omnibus is mounted on the PDP-8/A chassis (Figure 3-3 shows an 8 A chassis). Modules are inserted and removed
from the.front of the chassis. For connections to the outside world, connectors on the sides of the modules connect to a
shielded coaxial cable or flat ribbon cable. An opening in the chassis allows cables to be routed to the user's device.

CONNECTOR
A

CONNECTOR
B

CONNECTOR
C

CONNECTOR
D

CONNECTOR
E

SLOT 1

CORE MEM(
SLOTS
(USED ON
8A COMPUT

SLOT 12

POWER
SUPPLY
REGULATOR
SLOT

Figure 3-1

PDP-8/A Omnibus (H9194)

HEX MODULE

QUAD MODULE

Figure 3-2

3.2

PDP-8/A Hex and Quad Modules

BUS SPECIFICATIONS

Logic Levels
Logical 1
Logical 0

Maximum Voltage: 4-0.4 V
Minimum Voltage: -0.5 V
Maximum Voltage: 4-5.0 V
Minimum Voltage: 4-3.0 V

3.3 METHODS OF DATA TRANSFER
There are three methods o f accomplishing input/output data transfers: Programmed I/O Transfers, Interrupt Transfers, and Data Break Transfers.
3.3.1 Programmed I/O Transfer
The simplest method o f accomplishing an input/output transfer is t o employ the Programmed I/O Transfer. This
method relies upon the processor t o check the Status Flag and service the flag w i t h a subroutine.

3.3.2 Interrupt Facility
A more efficient method o f input/output transfers is t o employ the Interrupt System. This method uses the Programmed I/O Transfer, but the device signals the processor when a transfer is requied by grounding an INTERRUPT
REQUEST line. The processor responds a t the end o f the current instruction by entering a service routine.
3.3.3 Data Break Transfer
A still more efficient method of transfer is to employ the Data Break System. Whenever the data break device decides that it is time t o transfer, i t generates MS, IR DIS t o force the processor into a Direct Memory Access state
and CPMA DIS t o disable the CPMA register. This leaves the data break device free t o supply its o w n address and
t o manipulate the Major Registers Control logic so that i t can input and output data. The processor responds t o a

CORE
MEMORY
SLOTS

t
REGULATOR
BOARD SLOT

CABLE TO CONNECT
LIMITED FUNCTION
PANEL

POWER
CONTROL
FUSE

Figure 3 - 3

8 A Chassis (H9300)

break at the end of the current cycle. In general, data break requires more hardware than Programmed I/O. Additional logic is necessary to handle addressing, etc., and some Programmed I/O is necessary t o initialize and check
the status of the device.

3.3.4 The External Bus
The External Bus, which is mechanically and electrically organized the same as the I/O Bus o n the PDP-8/L or the
PDP-8/1 computers, plugs into the Omnibus by way of the Positive I/O Bus Interface and the Data Break Interface.
Each of these modules receives the same signal o n the same pins as any other module plugged into the Omnibus.
The interfacing details of the External Bus are given in Paragraph 3.1.9 and Volume II of the PDP-8/E Maintenance
Manual (DEC-8E-HMM2A-D-D).
The PDP-8/A Miniprocessor Handbook contains the information required to select the type of interface required for
the user's device and describes each o f the transfer methods in detail.

3.4 M O D U L E CONFIGURATION O N T H E O M N I B U S
The basic PDP-8/A system is comprised of one Central Processor Unit and at least one memory module. Other modules
may be plugged into the Omnibus t o add additional memory, options, or device interfaces t o the system. Table 3 - 1 lists
the PDP-8/A-compatible modules along with their Omnibus slot assignments.
Hex and quad modules cannot be inter-mixed on the Omnibus. All hex modules should be put together in the top
slots and all quad modules in the bottom slots.

For options that require additional modules to hold all the logic, two or more modules may be connected with H851 top
connectors (Figure 3-4).

Table 3-1
Slot Assignments for Modules on the Omnibus
Option

Optical Mark Card Reader Control
Card Reader Control
Interprocessor Buffer
I10 Option Module
Synchronous Modem Interface
Buffered Digital I10
Positive I10 Interface
Programmer's Console
Data Break Interface
Redundancy Check Option
Central Processor Unit
Central Processor Unit
Timing Generator
Bus Loads
Asynchronous Data Interface

Extended Option Module
Line Printer Control
Line Printer Control
Core Memory (8K)
Core Memory (16K)
Read Only Memory (1K )
Read Only Memory (2K)
Read Only Memory (4K)
Reprogrammable Read Only Memory
Readwrite Memory (1 K)
Readwrite Memory (2K)
Readwrite Memory
Reader Punch Control
RKO5 Disk Control
TU60 Cassette Interface
TU10 DEC Magtape Control
Point Plot Display Control
Video Display and Terminal Control
DK8-EP Real Time Clock
AD8-A AID Converter

Option
Designation

Type of
Module

Number O,
Modules

Omnibus Slot
Assignment

CM8-F
CR8-F
D B8-EA
DKC8-AA
DP8-EA, EB
DR8-EA
KA8-E
KC8-AA, AB
KD8-E
KG8-EA
KK8-A

Quad
Quad
Quad
Hex
Quad
Quad
Quad
PNL.MT.
Quad
Quad
Hex

1
1
1
1
2
1
1
0
1
1
1

4-last *
4-last
2-last
2-3
2-last
2-last
4-last
N.A.
4-last
4-last
1
Refer
to
Table 2-2
2-last
2-last
2-3
2-last
2-last
4-8
4-8
2-last
2-last
2-last
2-last
4-last
4-last
4-last
4-last
4-last
2-last
4-last
2-last
4-last
2-last
2-last

KK8-E
K L8-JA
K L8-M
KM8-A
LE8-XX
LS8-F
MM8-AA
MM8-AB
M R8-AA
MR8-AB
MR8-AD
M R8-FB
MS8-AA
MS8-AB
MS8-AD
PC8-E, PR8-E
RK8-EA
TA8-AA
TM8-EA, -FA
VC8-E
VT8- E
DK8-EP
AD8-A

) !S
Quad
Quad
Quad
Hex
Quad
Quad
Hex
Hex
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad

2
1
1
1
1
1
1
1

2
2
1
1
1
1
1
1
1
1
3
1
4
2

3
2
1

' L a s t ' applies except when considering both a non-expanded 8A600 or 8A620, and the added chassis of an expanded 8A600 or 8A620
(refer to Table 2-21.

3.5 OMNIBUS PIN ASSIGNMENT
Figure 3-5 relates the PDP-8/A modules (both quad and hex) and the Omnibus signals. The connectors are illustrated in
the lower part of the figure. The component side of the module is side 1. Individual pins are specified in this manner: BH 1
means connector B, pin H, side 1; DM2 means connector D, pin M, side 2, and so on. Each connector pin has a
corresponding pin on the Omnibus that carries a specific PDP-8/A signal. The upper part of Figure 3-5 relates the signal ,
names to the Omnibus/module connector pins. The L (low) or H (high) after the signal name identifies the assertion level
for that signal. For example, MDO L is asserted (a logical one) when it is low (-I-0.4 to -0.5 V). Most signals on the
Omnibus are tied through a load resistor to 4-5 Vdc. High level signals should be a minimum of 4-2.6Vdc and low level
signals should be +0.4 Vdc, as defined by TTL logic.

Figure 3 - 4

Modules Connected With 1-1851 Type Connector

The Omnibus is wired so that the signal appearing on a specific pin is the same for most slots on the Omnibus. For
example, pin CK1 of every Omnibus slot carries signal BUS STROBE L. There are some exceptions and these are noted in
Figure 3-5. In slot 1, which has the KK8-A CPU plugged into it, pins AA1 and CAI are tied to 4-5 Vdc instead of being
test points as indicated in Figure 3-5. These pins supply the extra 4-5Vdc current required for the M 8 3 1 5 module. Slots
2 and 3 also have pins with signals but they are different from the signals in the other slots.

BA1 of slots 2 and 3 carries BATTERY EMPTY L

BE1 of slots 2 and 3 carries AC LOW L

DA1 of slots 2 and 3 carries PANEL LOCK L

CONNECTOR, SIDE
E1

+ 20V

T P NOTE 5

+15V

T P NOTE 2

+5 V

TP NOTE 3

+5 V

TP NOTE 2

+5V

N O T USED

- 15V

- 15

T P NOTE 4

- 15V

GND

SP GND NOTE 1

GND

NOT USED

MA8L

IROL

I/O

TP1 H

MA4 L

INT STROBE H

MA0 L

â‚¬M L

+20V

MA9 L

I R 1L

CO L

TP2 H

MA5 L

BRK IN PROG L

MA1 L

EMA IL
GND

- -

PAUSE L

GND

MEM REFRESH(+5V)

MA10L

IR2 L

C1 L

TP3 H

MA6 L

MA.MS LOAD CONT L

MA2 L

EMA2 L

MEM REFRESH (+5V)

MA 11 L

C2 L

TP4H

MA7 L

OVERFLOW L

MA3 L

MEM START L

+20V

MD8 L

BUS STROBE L

TS1 L

MD4 L

BREAK DATACONTL

MDO L

MD DIR L

NOT USED

MD9 L

INTERNAL I/O L

T S2 L

MD5 L

BREAK CYCLE L

MD 1 L

SOURCE H

-5V

MD 10 L

USER MODE L

NOT LAST XFER L

TS3 L

MD6 L

L A ENABLE L

MD2 L

STROBE H

GND

+20 V

MDll L

F SET L

I N T ROST L

TS4 L

MD7 L

I N T IN PROG H

MD3 L

INHIBIT H

NOT USED

DATA 8 L

PULSE L A H

INITIALIZE H

L I N K DATA L

DATA 4 L

NTS S T A L L L

DATA 0 L

RETURN H

1 NOT USED

1 DATA 9 L

LINKLOADL

lDATA5L

1 RES H

1 DATA 1 L

1 WRITE H

GND

Notes
1. This pin is connected t o ground on the
bus but serves as a logic signal within
modules for testing.
2.

Pins A A 1 and C A I in slot 1 supply
+5 V t o the CPU module.
Pin BA1 of slots 2 and 3 supplies
BATTERY EMPTY t o the option
modules.

Pin BB1 of slots 2 and 3 supplies AC
LOW to the option modules.

DA1 of slots 2 and 3 supplies PANEL
LOCK t o the option modules.

CONNECTOR F
NOT CONNECTED
TO THE OMNIBUS

1 NOT USED

JUMPER 1

JUMPER J

1 STOP L

GND

N O T USED

DATA 1 0 L

NOT USED

DATA 11 L

1 SKIP L
GND

GND

KEY CONTROL L

CPMA DISABLE L

IND 1 L

DATA 6 L

MS.IR DISABLE L

IND2 L

DATA 7 L

.
Ã‘Ã

HEX MODULE
(COMPONENT SIDE)

GND
1

RUN L
POWER OK H

DATA 2 L
DATA 3 L

ROM ADDRESS L
LINK L

3.6 MAJOR GROUPS OF SIGNALS
The 96 signals of the Omnibus can be divided into nine major classes.

3.6.1 Memory Address - 1 5 Lines
The 1 5 signals EMA<0:2>L and MA<0: 11>L form a bus which defines the currently active memory address. The
source of MA<O: 11 >L is the CPU during instruction processing, and the currently active data break device during
Direct Memory Access (DMA) operations. The source of EMA<0:2>L is the memory extension control during instruction processing, and the currrently active data break device during DMA operations. Load resistors within the
CPU define EMA<0:2>L as zeros (highs) if there is no memory extension control in the system.
3.6.2

Memory Data and Memory Direction Control - 13 Lines

3.6.2.1 MD<0:11 >L - The 1 2 signals MD<O: 1 1>L form a bidirectional data path between memory and CPU.
In addition, these lines are monitored by Programmed I/O devices to determine device code and sub-device operation, and by data break devices t o obtain output (memory-to-DMA device) words.
3.6.2.2 MD DIR L - The source -of information on MD<O: 1 1>L is controlled by M D DIR L. If M D DIR L is
low, the data of the currently active memory is gated onto MD<O: 1 1 > L If M D DIR L is high, the contents of the CPU'S
memory buffer register are gated onto MD<O: 1 1 L.

3.6.3 Data Bus - 12 Lines
The 1 2 signals DATA<O: 11 >L form a multi-purpose 12-bit bus used for data exchange between peripheral and
CPU, for data input from DMA devices, for front-panel monitoring of selected registers, and for the determination of
data break priority.
3.6.4 I/O Control Signals - 1 0 Lines
This group of signals controls the I/O dialogue between CPU and programmed peripherals. This group includes
INITIALIZE H, which is used for clearing peripheral flags.
3.6.5 DMA Control Signals - 8 Lines
This group of signals controls the operation of data break (DMA). Several of these signals are also activated for certain
front panel operations. Included in this group is RUN L, which is used for clearing data break requests when the computer
is halted.
3.6.6 Timing Signals - 9 Lines
Five time pulses serve as system clocks. Similarly, four time state levels serve as system enabling levels. All of these
signals originate within the main timing generator of the CPU.
3.6.7 CPU States - 6 Lines
The major state of the CPU appears on FL, DL, or EL (FETCH, DEFER, or EXECUTE); the operation code of the instruction
currently being processed appears on IR<0:2> L.

3.6.8 Memory Timing Signals - 5 Lines
Five signals originate in the main timing generator of the CPU and are bused to all memories. These signals
(SOURCE H, RETURN H, WRITE H, INHIBIT H, and STROBE H) control all memory operations.

3.6.9 Miscellaneous Signals 1 8 Lines
These signals do not fit into any of the above categories. A large percentage of them are used by the Programmer's
Console. Two signals (ROM ADDRESS L and NTS STALL L) are driven by some types of memories under special
conditions, and are monitored by the CPU and other memories. The rest of these signals are truly miscellaneous. Included
in this group is a signal (POWER OK H) that reports the validity of the power supply voltages.

3.6.10 Special Signals
Slots 2 and 3 of the Omnibus carry some special signals which are used on the PDP-8/A option modules. They are: AC
LOW L, BATTERY EMPTY L (associated with the battery back-up power supply), and PANEL LOCK (disables operations
from the Programmer's Console when the PANEL LOCK switch is placed in the down position).
3.6.1 1 Interconnections
The interconnection of various system parts via the Omnibus is shown below:

CPU

MEM
EXT

b
0

i u t
n t h

MEM
b

b
0

i u t
n t h

I10

i u t
n t h

DMA

b
0

i u t
n t h

PANEL
b

b
0

i u t
n t h

MEM ADD
MEM DAT
DATA BUS

I10 CTRL
DMA CTRL
TIMING
CPU ST

MEM TIM
MISC
T h i s is just the DMA portion of what is usually a complex peripheral. Such a peripheral usually uses the programmed
110 signals as well.

3.7 DETAILED DESCRIPTION OF THE 96 OMNIBUS SIGNALS
This paragraph describes the logical operation of each of the Omnibus signal lines. The paragraphs are arranged similar to Paragraph 3.6 for easier correlation.
3.7.1 Memory Address - 15 Lines
These signals are changed starting at the leading edge of PULSE LOAD ADDRESS H or TP4 H and remain static
through the entire memory cycle.
3.7.1.1

EMA <0:2>L. - Must be settled 50 ns prior to leading edge of SOURCE H and RETURN H.

Signal

EMAO L
EMA1 L
EMA2 L

AD2
AE2
AH2

Most Significant Bit

Least Significant Bit

3.7.1.2

3.7.2

M A <0:11>L. - Must be settled 5 0 ns prior t o leading edge of SOURCE H and RETURN H.
Signal

MA0 L
MA1 L
MA2 L
MA3 L

AD1
AE1
AH1
A J1

MA8 L
MA9 L
MA10 L
M A 11 L

DDI
D E1
DH1
DJ1

Most Significant Bit

Least Significant B i t

Memory Data and Direction Control

- 13 Lines

3.7.2.1 MD<0:11 >L. - These lines form the data path t o and from memory. If M D DIR L remains l o w for the entire
memory cycle, information from memory may be placed on the M D lines as late as 1 5 0 ns prior t o TP2; otherwise, the
information must be present 2 5 0 ns before TP2. If M D DIR L is allowed t o go high, the new M D information from the
CPU's Memory Buffer register must be o n the Omnibus 1 5 0 ns prior t o the leading edge of INHIBIT H, and must remain
static for the duration of INHIBIT H for proper memory operation. It is desirable that the M D lines remain static into Time
State 1 (TS1) of the next machine cycle t o facilitate displaying the contents of memory when single-stepping programs.
Signal

MDO L
MDI L
MD2 L
MD3 L

AK1
ALI
AM1
AP1
BKI
BL1
BM1
BPI
DKI
D L1
DM1
DP1.

Most Significant B i t

Least Significant Bit

3.7.2.2 MD DIR L - L=memory driving M D lines; H=CPU1s M B register driving M D lines. M D DIR L is always
low from 1 0 0 ns after the leading edge of TP1 H t o the leading edge of TP2 H, when it may be allowed t o go high.
The gating from M D DIR L t o the drivers of the M D bus is static; hence care should be taken t o guarantee that this
line does not g l i t c h " . If M D DIR L remains low for the entire memory cycle, the information on the MD lines is
valid from the time it is placed on the Omnibus through the end of the memory cycle. No extra time need be allotted for computing and storing information in the CPU's M B register, and no time need be allotted for M B driver
turn-on and bus propagation after TP2.
Signal

MD DIR L

AK2

3.7.3

Data Bus - 12 Lines

DATA <0:11 > L The data is a multi-purpose, 'I 2-bit bus whose use is a function of the machine state. During TS1 of
every memory cycle, the data bus carries indicator information as defined by the IND lines, (Paragraph 3.7.9.1 ).
During TS2 of FETCH cycles, the data bus carries the contents of the AC. During TS2 of DMA cycles, the data bus carries
information to be placed in memory, or information to be added to the contents of memory. During TS3 of IOT instructions, the information on the data bus is a function of the I/O control lines (Paragraph 3.7.4.5). During TS3 of OP2
instructions, the contents of the CPU's AC are placed on the data bus if the CLA bit (bit 4 of the instruction word) is zero,
and the contents of the control panel's switch register are placed on the data bus if bit 9 of the instruction word is a one.
This implements the OSR and LAS instructions. During TS4 of all machine cycles, the data bus is reserved for determining data break (DMA) priority. See Paragraph 3.7.5 for more details.
A good general rule is for all logic to stay off the data bus unless there is a valid reason for placing data on that
bus. The data bus must be left free for use by the CPU.
Signal

DATA0 L
DATA1 L
DATA2 L
DATA3 L

AR1
AS1
AU 1
AV1

DATA8 L
DATA9 L
DATA10 L
DATA1 1 L

DR1
DS1
DU1
DV1

Most Significant Bit

Least Significant Bit

3.7.4 I/O Control Signals - 10 Lines
Basic I/O devices may perform data exchange between the AC of the CPU and the device's registers. The state of
the device is tested using skip instructions. These devices need not make connection to C2 L, BUS STROBE L, and
NOT LAST XFER L.
More complicated I/O devices may use BUS STROBE L and NOT LAST XFER L to stall the CPU, perform multiple
transfers in a single IOT, and/or modify the PC (and/or the Link).
3.7.4.1 1/0 PAUSE L - Pin CD1 - I/O PAUSE L is low if F L, MDO L and MD1 L are low and USER MODE L
and MD2 L are high. Also included is a gating term from the timing chain. It is the command to all Programmed I/O
peripherals to compare their device codes with the contents of MD<3:8>L. If a peripheral finds equality with
MD<3:8>L, it decodes MD<9: 11 >L to determine the sub-device operation to be performed. The peripheral has
100 ns in which to decode its subdevice operation and assert information onto the C lines and data bus. Similarly, it
must remove all information 100 ns after I/O PAUSE L is negated.
I/O PAUSE L remains asserted during extended I/O cycles until the CPU has been restarted. (Paragraph 3.7.4.7)
Although not mandatory, it is strongly urged that the peripheral logic design incorporate load-relief logic to minimize
loading on the DATA and M D buses when I/O PAUSE L is negated. Loading rules require load relief if there is more than
one Programmed I/O peripheral.

3.7.4.2
I N T E R N A L I/O L - P i n CL1
INTERNAL I/O L alerts the KA8-E Positive I/O Bus Adapter that an I/O
device o n the Omnibus has recognized the IOT being processed. If the KA8-E finds this line not asserted, it processes the IOT by stopping the CPU and entering an expanded I/O cycle.
All internal (Omnibus) I/O devices ground this line if they find equality between M D < 3 : 8 > L
when I/O PAUSE L i s low.

and their device code

3.7.4.3 SKIP L - Pin CS1 - SKIP L is sampled b y the CPU a t TP3 t o determine i f an I10 skip should occur. The skip
occurs i f SKIP L is low. This line is sampled every TP3 (not just during I O T instructions) i f the processor is n o t i n the
D M A state.

3.7.4.4 I N T RQST L - Pin CP1 - I N T RQST L is sampled b y the CPU at the leading edge o f I N T STROBE H i f all
other interrupt conditions are met t o determine i f an interrupt request is pending. This line is asserted b y a peripheral
device when a condition that causes an interrupt is encountered. Since the CPU contains a synchronizing flip-flop, this
line may be asserted at any time. I n addition, i f this line is grounded 100 ns or more before TP3, the SRQ instruction
will skip.
3.7.4.5
C < 0 : 2 > L - Pins C E 1 (CO L); C H I (C1 L); C J 1 ( C 2 L) - C<0:2>L
an IOT as shown below:

control the type of transfer during

Transfer
H x
L H
L L
x H
x L

H
H
H
L
L

A C -+ DATA<O: 11>L+ A C (Peripheral may "or" information o n t o DATA<O: 11>L)
A C + DATA<O:Il>L; 0+ A C
DATA<O: 11>L+ A C
DATA<O: 11>L+PC+ PC
DATA<O: 11>L+ PC

x =doesn't matter. In general, peripherals use only SKIP L to modify the PC, and so do not make connection to C2 L. See
Paragraph 3.8.4 for the impact on timing.

3.7.4.6
B U S STROBE L - P i n C K 1 - BUS STROBE L is a negative-going pulse which causes the AC or PC t o
be loaded during an IOT. BUS STROBE L is also used in conjunction w i t h NOT LAST XFER L during long I/O cycles
(Paragraph 3.7.4.7).
During an IOT, gating within the CPU generates a single BUS STROBE L pulse at TP3 time if NOT LAST XFER L is
high (i.e., i f the IOT is not an extended IOT). If an extended I/O cycle is in 1 rocess (i.e., if NOT LAST XFER L is low
at TP3 H), the peripheral must generate all BUS STROBE L pulses. The AC or PC (depending o n C2 L) is loaded a t
the leading (falling) edge o f BUS STROBE L.
3.7.4.7
N O T L A S T XFER L - P i n C L 1 - Most peripheral controllers require only one transfer per IOT; hence the
single transfer a t TP3 time is adequate. Such peripherals d o n o t ground NOT LAST XFER L and d o not drive BUS
STROBE L. Other, more complex peripherals (the KA8-E Positive I/O Interface, for example) require extended timing
and use NOT LAST XFER L t o "stall" the CPU i n a n I/O cycle.
To stop the CPU in TS3 of an I/O cycle, ground NOT LAST XFER L prior t o TP3 H of the IOT.
The CPU will remain in TS3, and will not generate INT STROBE H or BUS STROBE L. Timing is n o w controlled by the
peripheral.
The peripheral may make any number of transfers by controlling C<0:2>L,
NOT LAST XFER L at ground.

generating BUS STROBE L and keeping

The CPU is restarted by allowing NOT LAST XFER L to go high before the leading (falling) edge of BUS STROBE L.
I n addition t o making a final data transfer, the CPU restarts by generating INT STROBE H, entering TS4 and by negating I/O PAUSE L.

3.7.4.8

INITIALIZE H - Pin CR1 - INITIALIZE H is asserted (high) by:

Pressing the Programmer's Console INIT key.

Executing the CAF instruction (octal 6007),

Negating the POWER OK H.

INITIALIZE H statically clears the AC, Link, interrupt system, and peripheral flags. It also sets the interrupt enable
flip-flops of peripherals that must remain program-compatible with older versions that did not have an interrupt enable flip-flop. (Two important devices in this category are the TTY and paper-tape reader/punr' interrupt enables.)

3.7.5 DMA Control Signals - 8 Lines
Data breaks (DMA) allow a peripheral t o communicate directly with memory, bypassing the CPU. The only CPU register available t o the DMA device is the M B ; all other CPU registers must be preserved. Data breaks may occur between any CPU cycles, but a data break cannot be performed while the CPU is in the midst of an extended I/O
cycle because the currently active memory is then supplying information to the bus.
Data breaks take place in the following sequence:
1.

A t INT STROBE H leading edge, th~edecision t o request a data break is made at the peripheral by setting its
break request flip-flop.

A device starting a data break unconditionally asserts CPMA DISABLE L and BREAK IN PROG L until its
break request flip-flop is cleared.

Data break priority is determined on DATA<O: 1 1 >L when TS4 L is asserted. Each data break device is
assigned a unique line on DATA<O: 1 1>L, with DATA0 L being the highest-priority line. Each requesting
device asserts its line on DATA<Q: 1 1 >L, and examines the state of all higher-priority lines t o determine
if they are all high. For example, a device asserting DATA5 L examines DATA<0:4>L to make sure
these lines are all high. The device finding all higher-order lines high proceeds t o step 4 below; all other
devices remain in step 3.

The device winning the priority test sets its M A Control flip-flops at the leading edge of TP4 H. (The
path from TP4 H t o the Memory Address lines must have as little delay as possible; hence two flip-flops
are recommended t o provide adequate drive without introducing the delay of a buffer (Paragraph
3.7.5.7). The M A Control flip-flops gate the break address onto the 1 5 Memory Address lines, and assert
MS, IR DISABLE L and (if this cycle is a data exchange cycle) BK CYCLE L.

At TP1 ti, the active device asserts MA, M S LOAD CONT L.

For input t o memory, the active device merely places its data on DATA<O: 1 1 >L during TS2. For output
from memory, the device asserts BREAK DATA CONT L during TS2 L, and loads its register with the
contents of M D < 0 : 1 1 >L at the leading edge of TP2 H, TP3 H, or TP4 H. For Add To Memory, the device places the data t o be added on DATA<O: 1 1 >L during TS2, and asserts BREAK DATA CONT L during TS2. The modified information is loaded into the CPU's M B and overflow flip-flop at TP2 H, and may
be read by the device at TP3 H or TP4 H. (TP3 H is generally used, since OVERFLOW L is valid only at
this time.) The data prior t o modification may be read at the leading edge of TP2 H.

A t the completion o f a data break, all lines are in the same order and a t the same times in which they
were asserted.
Three-cycle data breaks are merely three one-cycle data breaks w i t h a special control to handle Word
Count and Current Address cycles. BREAK CYCLE L is not asserted during these t w o cycles; it is asserted only for the final, data exchange cycle.
D M A latency is the longest machine cycle, plus the time o f TS4.

3.7.5.1 BRK I N PROG L - Pin BE2 - This signal provides indicator information t o the console. I t is grounded at
INT STROBE H leading edge if a break is to take place, and asserts the console BRK IN PROG bit of the Major
State Register.
3.7.5.2 CPMA DISABLE L - Pin CU1 - CPMA DISABLE L is asserted (low) by break devices if data breaks are
t o occur. I t is sampled by the CPU and memory extension control a t the leading edge of TP4 H. If CPMA DISABLE
L is l o w at that time, the memory extension control's field bits and the CPU's Memory Address bits are removed
from E M A < 0 : 2 > L and M A < 0 : 1 1>L. I f CPMA DISABLE L is negated (high) at the leading edge of TP4 H, the
memory extension field bits and the CPU's Memory Address register are gated to E M A < 0 : 2 > L and MA<O: 1 1 > L
respectively.

3.7.5.3 MS, IR DISABLE L - Pin CV1 When MS, IR DISABLE L is high, the Major State and IR flip-flops drive
the Major State and IR lines on the Omnibus (Paragraph 3.8.1). When MS, IR DISABLE L is asserted (low), the M a jor State and IR lines are not driven by the CPU. Unless some external device asserts a Major State, the CPU is
then in the D M A state.

3.7.5.4 MA, M S LOAD CONT L
Pin BH2 - When M A , M S LOAD CONT L is negated (high), the CPU and
memory extension control function normally. Asserting this line inhibits the loading of new information into the
CPU's Major State and Memory Address registers, and into certain control flip-flops of the memory extension control. This signal must n o t change while TP4 H i s high. I t is normally changed at TP1 time.

3.7.5.5 BREAK DATA CONT L - Pin BK2 This signal is ignored unless F L, D L, and E L are all high. BREAK
DATA CONT L should be stable as early in TS2 as possible, and defines the information loaded into the M B at TP2
H. I f BREAK DATA CONT L is high during TS2 of a D M A , DATA<O: 1 1 > L is loaded into MB<O: 1 l>.
If BREAK
DATA CONT L is low during TS2 of a DMA, M D <0: 1 1 >I plus DATAO: 1 1 L is loaded into M B <0: 1 1 >. Making
BREAK DATA CONT L l o w and placing n o information (zeros) o n DATA<O: 1 1 > L causes a D M A that does, not modify memory.

3.7.5.6 OVERFLOW L - Pin BJ2 This line is asserted (low) during TS3 if a carry occurs at TP2. Hence this line
is asserted if any of the following occur:
1.

Auto Index or J M S wrap-around

ISZ overflow

Data break overflow or carry

3.7.5.7 BK CYCLE L - Pin BL2 - Panel information from the data break device. Low indicates that a break data
transfer cycle is in process.
3.7.5.8 RUN L - Pin BU2 - This signal is really a CPU state since it indicates that the CPU's timing generator is
running (when low). I t is included in this group of signals because its most important function is as a gating term
used t o clear all break requests when negated (high).

Timing Signals

3.7.6

- 9 Lines

Five pulses and four levels originate in the timing generator of the CPU and are used as system clocks and enabling
levels respectively. Time pulses are nominally 1 0 0 ns wide (INT STROBE H i s more loosely defined. Refer t o Paragraph 3.8.1). Time states change nominally 5 0 ns after the leading edge of the time pulse. When the CPU is
stopped, the machine is a t the beginning o f TS1. Applying a single M E M START L causes the timing chain t o start
and continue t o run until:
1.

The STOP L line on the Omnibus is asserted a t TP3, or

The CPU encounters a HLT instruction a t TP3, or

POWER OK H is negated a t TP3 and the current memory cycle is complete.

A time state precedes the time pulse of the same number; INT STROBE H is coincident with TP3 H except when in
an extended IOT operation; TS1 L i s automatically entered a t the end o f TS4.

Signal

TS1 L
TS2 L
TS3 L
TS4 L

INT STROBE H
3.7.7

BD2

CPU STATE - 6 Lines

3.7.7.1

Major State Lines
The CPU Major State appears o n these lines unless MS, IR DISABLE L is asserted (Paragraph 3.7.5.3). The Major
State as seen by the CPU's instruction decoder is taken from these lines, thus it is possible t o build special options
which force instructions t o the CPU. Normally, the Major State lines change at TP4.

Major State

3.7.7.2 IR<0:2>L - These reflect the state of the CPU's instruction register provided MS, IR DISABLE L is high.
A l o w o n IR<0:2>L represents a one in the corresponding bit of the Instruction Register. As in the case of the M a jor State lines, the IR lines are disconnected from the Instruction Register if MS, IR DISABLE L is low. The instruction seen by the CPU during D and E Major States is obtained from these lines. During instruction FETCH, the Direct
JUMP, IOT, and operate instructions are decoded directly from the M D lines. A s with the Major State lines, i t is possible t o force instructions during defer or exec:ute cycles. The IR i s loaded at TP2 of an instruction FETCH (F L is
low), or a t TP4 if an interrupt is being honored (INT I N PROG H i s high).
Signal

IRO L
IR1 L
IR2 L

DD2
DE2
DH2

3.7.8 Memory Timing Signals - 5 Lines
These signals are defined in terms of the 1.5 us memory cycle. (See Paragaraph 3.8.2 for waveforms.)

3.7.8.1 SOURCE H Pin AL2, and RETURN H Pin AR2 - These signals become asserted (high) at the same
time and direct the memory to turn on its read/write currents. RETURN H becomes negated 50 ns later than
SOURCE H, thereby defining the voltage to which the memory stack is charged.
3.7.8.2 WRITE H - Pin AS2 - WRITE H controls the direction of current flow in the memory stack. It is high during write and low during read. If WRITE H is low, the positive-going transition of SOURCE H is usually used to clear
all Memory Buffer registers.
3.7.8.3
INHIBIT H - Pin AP2 - INHIBIT H is a gating level to the inhibit drivers of core memory. When high, it
causes the selected memory's inhibit drivers to turn on.
3.7.8.4 STROBE H - Pin A M 2 - The leading edge of STROBE H provides a time reference from which the
strobe in each individual memory is derived. Each memory delays this edge by an optimum amount for that memory,
and then strobes its sense amplifiers. The selected memory must have its data on MD<0: 1 1 L at or before strobe
leading edge plus 150 ns (this time does not include bus charging time).

3,7.9

Miscellaneous Signals - 1 8 Lines
INDI L

IND2 L

H
L
H
L

H
L
L

Information on DATA<O: 1l > L
Status Word *
MQ<0: 1I>
All zeros (highs)
AC<O: 1I>

*STATUS WORD (Figure 1-51

Information

Bit

LINK
Not used
INT RQST L (low on DATA2 L if INT RQST L [Pin CPI] is low)
INT INH Flip-Flop**
INTERRUPT DELAY Flip-Flop (denotes interrupt on)
User Mode L**
IF<0:2>**
D F<0:2>**
**From memory extension control if present, otherwise these remain high (zeros).

3.7.9.1 IND1 L
Pin CU2, and IND2 L - Pin CV2 - These signals control the information gated to
DATA<O: 1 1> L during TS 1. Since DATA<O: 1 1>L is defined as low for a 1, ones in register bits place lows on
DATA<O: 11>L.
Gating circuitry in any logic driving IND1 L and IND2 L should ground IND1 L and allow IND2 L to go high if LA
ENABLE L is asserted (low) (Paragraph 3.7.9.9).
3.7.9.2 MEM START L - Pin AJ2 - Grounding MEM START L causes the timing chain of the CPU to start.
MEM START L may be a 100 ns negative-going pulse, or it may be a level that is low if TS1 L is asserted and the
logical decision to start the machine has been made. MEM START L must not be asserted (low) beyond TP2 H,
since it may then interfere with possible HLT instructions.

A single MEM START L pulse causes the CPU to start and continue to run until halted by the program or by the
STOP L line (Paragraph 3.7.9.3).

3.7.9.3 STOP L - Pin DS2
STOP L is sampled by the CPU at the leading edge of TP3 H of every machine
cycle. If STOP L is asserted (low), the CPU completes its current memory cycle and stops in TS1 (just after TP4 H
goes to ground). At that point in its cycle, the CPU can display:
New Memory Address (on EMA<0:2>L and MA<O: 11 L)
New Major State (on F L, D L, and E L)
Memory Data of last-referenced location (on MD<O: 11 >L)
Status or AC or MQ (on DATA<O: 1 1> L depending on IND 1 L and IND2 L)
Any other lines on the Omnibus for which display provision has been made
STOP L is asserted by HLT/SS on the Programmers Console, and is also asserted when:
Single deposit (D THIS) operation is in process
Examine operation is in processor
A HLT instruction (octal 7402) is executed.
POWER OK H is low KEY CONTROL L is low during examine or deposit condition (Paragraph 3.7.9.9).

3.7.9.4

LINK L - Pin AV2 - LINK L is low if the LINK bit of the CPU is a one, and high if the LINK is a zero.

3.7.9.5 LINK LOAD L - Pin CS2, and LINK DATA L - Pin CR2 - These t w o signals allow loading of the LINK
from the Omnibus. Loading occurs on the leading (falling) edge of LINK LOAD L, and the data loaded into the LINK
is a one if LINK DATA L is low. These two signals should be used only in extended I/O cycles while NOT LAST
XFER L is low.
3.7.9.6 F SET L - Pin DP2 - This line is asserted (low) if the Major State gating of the CPU indicates the next
Major State will be a FETCH. The conditions causing this line to be asserted are:

A Major State of EXECUTE, no interrupt being honored (Paragraph 3.7.9.8).

A Major State of DEFER and an IR of 5 (JMP instruction).

A Major State of FETCH, a JMP instruction and MD3 L high (direct jump).

A Major State of FETCH and an IOT instruction.

A Major State o f FETCH and an operate instruction.

D M A ( F L, D L and E L all high).

3.7.9.7 USER MODE L - Pin D M 2 - This line is normally driven by the timeshare portion of the memory extension control and is tied high by a load resistor in the CPU if no memory extension control is in the system. USER
MODE L is changed only at TP4 time.

If USER MODE L is high, the CPU and control panel function normally. If USER MODE L is asserted (low), the following operations are inhibited:
1.

The HALT instruction (inhibited in the CPU)

The OSR and LAS instructions (inhibited in the panel logic)

1/0 PAUSE L remains high even though an IOT instruction is fetched from memory (inhibited in the
CPU).

Interruption of the program, upon detection of any of these conditions, is handled by the memory extension control.

3.7.9.8

INT I N PROG H - Pin BP2 - INT IN PROG H is allowed to go high if:

The interrupt system has been turned on by an ION or RTF instruction and at least one subsequent instruction fetch has occurred.

An interrupt request has been recognized by the INT SYNC flip-flop of the CPU (which sets at the leading edge of INT STROBE H if INT RQST L and FSET L are both low).

There is no interrupt inhibiting condition. This condition is preserved in the INT INHIBIT flip-flop in the
memory extension control, and is generated if a CIF, CUF, SUF, RMF or RTF instruction has been processed and a JMP or J M S has not yet occurred to complete the field change.

INT IN PROG H is used by the CPU to load 0 into the CPU's MA, force the Major State to EXECUTE and IR to
JMS, and to turn off the interrupt system. INT IN PROG H is also used by the memory extension control to load the
save field, and to clear the IB, IF and DF. INT IN PROG H goes high at INT STROBE H time, and is not negated
again until the interrupt system is turned off (INT IN PROG H, INT STROBE H and not DMA).

3.7.9.9 LA ENABLE L - Pin BM2, and KEY CONTROL L - Pin D U 2 - These lines must not be asserted unless
the CPU is in the DMA state (MS, IR DISABLE L low and F L, D L, and E L all high). If LA ENABLE L is low, any
logic driving IND1 L and IND2 L must assert IND1 L and turn off any drivers driving IND2 L.
The function of LA ENABLE L, KEY CONTROL L, and BREAK DATA CONT L are defined as follows:

Load Address Enable

Key Control

Break Data Control

Function

XLA 7
XLA 0
Non-stop deposit
Load address
Panel examine
Panel deposit
Add t o memory*
Break deposit*
*See Paragraph 3.7.5.5.

E THIS or E NEXT on the Programmer's Console asserts STOP L, performs one memory cycle at the address in the
CPU's MA register, does a break add to memory, and increments the MA.
D THIS or D NEXT on the Programmer's Console asserts STOP L, performs one memory cycle at the address in the
CPU's M A register, does a break deposit with the Entry Register of the console providing input data, and increments
the MA.

Load Address - There are two possible functions. If PULSE LA H is asserted, the M A is loaded from
DATA<O: 1 1 > L If MEM START L is asserted, the CPU starts, performing an examine at whatever location is in the
CPU's MA. A t TP3 H, the contents of DATA<0:11 >L are loaded into the PC and transferred to the CPU's M A at
TP4 H. The CPU is not stopped. (STOP L is not asserted.)
Non-stop Deposit - Same as panel deposit except STOP L is not asserted, so the CPU continues to run. Useful for
loading bootstrap programs into memory.
XLAO - There are two modes of operation. If PULSE LA H is asserted, the memory extension control is loaded with
whatever is on DATA<6: 11 >L. If MEM START L is asserted, the CPU starts and does an examine at whatever location is in the CPU's MA, The memory extension control is loaded at TP3 H, but 0 is on DATA<6: 11 >L so the memory extension control's IF, 16, and DF registers are cleared. STOP L is not asserted, so the CPU continues to run.

XLA7 - Like XLAO with MEM START L, except that the CPU places 7777 on DATA<O: 11 >L, loading 7 into the
IB, IF, and DF. The AC must be 0 for this function to work properly.

3.7.9.10 PULSE LA H - Pin DR2 PULSE LA H causes the CPU's M A register to be loaded if KEY CONTROL L
is high; or the memory extension control's IB, IF, and DF registers to be loaded if KEY CONTROL L is low. PULSE
LA H is a nominal 100 ns positive-going pulse.
3.7.9.11 ROM ADDRESS L - Pin AU2 - ROM ADDRESS L is examined by core and other read/write memories.
If ROM ADDRESS L is high, the read/write memory functions normally. If ROM ADDRESS L is low, the read/write
memory is disabled. ROM ADDRESS L is asserted by small ROMs which overlay read/write memories, thus providing a small number of read-only locations in a large read/write memory. The gating for this signal must be fast.
There are only 25 ns from the time the address lines have been established to the time this signal must be asserted,
ROM ADDRESS L also modifies the JMS instruction by inhibiting the incrementing of the new PC contents. This action causes the JMS instruction to act like a JMP instruction (except for timing) if a J M S to ROM is attempted.

3.7.9.12 NTS STALL L - Pin BR2 - NTS STALL L (Next Time State Stall L) provides a means of stalling machine operation to accomodate memories slower than the one for which the timing chain was designed.
When NTS STALL L is high, the timing chain of the CPU functions normally. If NTS STALL L is asserted (low), the
timing chain functions normally to the middle of the next time pulse. The time state changes and the time pulse completes in the normal 100 ns, but the timing chain stalls at the beginning of the new time state. The stalling of the
time state continues until NTS STALL L goes high, restarting the timing chain. NTS STALL L has no effect on the
duration of the five memory timing signals. It merely stretches the time before read, the time between read and
write, and the time after write before new addres~s.NTS STALL L must be low, 100 ns, before the leading edge of a
time pulse to guarantee stalling in the next time state. The timing generator will not stall in the next time state if
NTS STALL L is high for the 100 ns prior to the leading edge of the time pulse.

NTS STALL
Low at

Time State
Becomes Longer at

And There is

TP1 H

TS2

Longer time from end of read t o TP2, allowing the CPU t o accommodate memories with long read access time.

TP2 H

TS3

Longer time from when MB is loaded t o the start of write.
Longer time from start of write t o time address is changed,*accommodating memories with long write times.

TP4 H

TS 1

Watch break latency when using NTS STALL.

Longer time from address change t o start of read.

3.7.9.13 S W - Pin D V 2 - This line reflects the state of the bootstrap flip-flop controlled by the switch on the Programmer's Console ORed with the state of the bootstrap switch o n the Limited Function Panel. The signal is low if
the switch is up o n the Limited Function Panel.
On machines equipped w i t h bootstrap options, the low-to-high transition of this line initiates bootstrap operation if
the CPU is halted. If there is n o bootstrap option in the machine, this line is available for any use the user may devise.

3.7.9.14 POWER OK H - Pin BV2 POWER OK H originates in the power supply and reports the state of the
dc voltages t o the CPU, memory extension control and core memories. The dc supplies are in regulation if this signal
is high (Paragraph 3.9).
A s the dc supplies fall toward ground, POWER OK H will be negated but may go somewhat positive again as the
+ 5 V supply nears ground. POWER OK H must remain at less than 0 . 4 V until all supply voltages are less than 30%
of their nominal value, otherwise, modification o f core memory contents may occur.
POWER OK H being low asserts STOP L. POWER OK H going l o w is also applied t o an integrator in the CPU, the
output o f which generates INITIALIZE H and is used as a master clear for the timing chain. Similar integrators in
each o f the core memories enable and disable the memory current supplies.
Negating POWER OK H does the following:
1.

STOP L i s asserted immediately.

A t the next TP3 H, RUN L i s negated by the CPU.

A t the following TS1, all break devices clear their break requests and the memory extension control initializes its EMA Enable flip-flop. The gating t o accomplish this is usually the A N D of POWER OK H
being low, TS1 L being low, and RUN L being high.

After a delay ( 1 5 - 5 0 0 u s ) long enough t o allow the longest possible memory cycle t o complete, the timing chain is preset t o the beginning of TS1 w i t h TP4 low. All memory timing signals are made low. The
CPU's control flip-flop, which gates the CPU's M A onto the Memory Address lines, is placed in the "enabled" state. INITIALIZE H is generated, clearing the AC, LINK and interrupt system.

After a similar delay, each core memory disables its current sources so that memory cannot be altered if
memory timing signals should become asserted as the dc voltages go away.

Upon application o f power:
1.

The CPU, extension control and peripherals are all initialized.

Memory current sources are enabled 1 t o 7 0 m s after POWER OK H is asserted. This enabling is accomplished by an integrating capacitor, so that "spikes" o n POWER OK H are filtered out.

The internal clear signal and the Omnibus INITIALIZE H signal are negated 2 0 0 to 1 0 0 0 ms after
POWER OK H is asserted.

All portions of the computer should be ready t o run 0 . 1 sec after POWER OK H is asserted. M E M
START L will not be recognized until after INITIALIZE H is negated.

3.7.9.15 RES - Pin BS2 RES is an unused line. Digital Equipment Corporation reserves the right t o define this
line at a later date, and disclaims any responsibility t o make this definition agree w i t h any prior illicit use.

3.7.9.16 Special Signals Special signals AC LOW L, BATTERY EMPTY L, and PANEL LOCK are carried only on
pins in slots 2 and 3 of the Omnibus.

3.7.9.16.1 AC LOW L Pin BB1 (Slots 2 and 3 Only) - AC LOW L is asserted when the ac voltage falls below
9 5 Vac &3% and is negated when ac voltage goes above 1 0 5 Vac k 3 % (with corresponding values to 2201240
Vac operation). AC LOW L is controlled by a detector in the power supply which senses changes in the ac voltage
levels. On semiconductor machines, the system can continue t o operate in the absence of ac power for up t o 45 seconds fully loaded. In these machines AC LOW is the signal t o switch to battery backup power. With core memory
machines, AC LOW causes an interrupt that allows the program time to transfer the contents of the active registers
to nonvolatile core memory.

3.7.9.16.2 BATTERY EMPTY L Pin BA1 (Slots 2 and 3 Only) BATTERY EMPTY L is asserted when a circuit in the power supply senses that the battery voltage has fallen below a certain value, This indicates that the battery has only 1.0 ms of run time remaining before the computer is halted by negation of POWER OK H (Paragraph
3.7.9.14).

3.7.9.16.3 PANEL LOCK L
Pin D A 1 (Slots 2 and 3) - PANEL LOCK L is asserted when the PANEL LOCK
switch is in the up position t o disable all key pad switches except Switch Register (SR) and the read functions.
3.8 TIMING
Many signals on the Omnibus are wire-ORed. For these signals, the high level is determined by a load resistor and
the low level is determined by one or more open-collector gates which ground the signal. Bus capacitance is moderately high; hence fall times in such situations are fast and rise times are slow (about 1 0 0 ns). This 1 0 0 ns is considered in the following timing diagrams by adding the 1 0 0 ns t o the set-up times where necessary. This requires
C<0:2>L t o be defined from 4 5 0 ns before the leading edge of BUS STROBE L; 1 0 0 ns of this time is allotted t o
charging C<0:2>L.
3.8.1 TimePulsesandTime States
The time pulses (TP1 H, TP2 H, TP3 H, INT STROBE H, and TP4 H) plus their associated time states (TS1 L, TS2 L,
TS3 L, and TS4 L) serve as the timing reference from which all other timing is derived (Figure 3-6). Timing pulses
and time states are derived from a master crystal clock ( 2 0 MHz) in the timing generator of the CPU. This clock has
a stability of 0.1%; hence the time between positive edges of time pulses is accurate to 0.1%. Time pulse widths are
90-1 1 0 ns; the uncertainty is caused by gate skew and threshold variation. Time states change nominally at 50 np
after the leading edge of the time pulses, but logic delays and loading introduce an uncertainty i n this time.
Figure 3 - 7 details time pulse and time state change (this applies t o TP1 H, TP2 H and TP4 H.)

T P H~
TP1H

TP2 H

IÃ‘

TP3 H
TS1 L Ã‘Ã

T I ME PULSE

TS2 L

-90

TS3L

TS4 L
A = 350ns
B =400ns
C=400ns
0=350ns
TOTAL TIME' 1500ns

Figure 3 - 6

to 110ns-

-9013s
10 ns MIN Ã‘Ã‘

MAXIMUMÃ‘
I
I

TI ME STATE
OLD

UNCERTAIN

1 NEW

ce ,157

Timing For One Memory Cycle

Figure 3 - 7

Time State and Time Pulse Change Timing

Figure 3 - 8 details TP3 H timing if NOT LAST XFER L is high and if I/O PAUSE L is high. (See Paragraph 3.8.5 for other
conditions.)
3.8.2 Memory Timing
Normal memory timing is based on 1.5 u s core memory, and is shown in Figure 3-9.

READ

WRITE

350n<

SOURCE H
0
-ns

TIMESTATE

110ns MAXIMUM --I
dons MINIMUM
1
-I--UNCERTAIN
I TS4

I<-

-- -<Â - - - - TS3

INT
STROBE H

-0

Figure 3-8

I
I

INHIBIT H

TP3 Timing During IOT Transfer

150ns--'

iÃ§

-I

-90

to150ns

STROBE H

RETURN H

t o 5 0 nsec

{ 5017s 4 >Â¥

1
r-50ns

P-

I
I
WRITE H
I
Unless otherwise noted a l l times above
ore + or - 1 0 nsec.

Figure 3-9

m%1160

Memory Timing

3.8.3 Relationship Between CPU and Memory Timing
The timing relationship between the (read) CPU and memory is shown in Figures 3-10 (Read) and 3-1 1 (Write).
MD<O: 1 1 >L changes at TP2 H only if M D DIR L is allowed to go high. If M D DIR L remains low, MD<O: 11 >L is
settled on bus at STROBE H leading edge +250 ns.
The times given take into consideration the type of load on MD<O: 1 1 >L, EMA<0:2>L
position, plus maximum bus capacitance.

ROM ADDRESS L,USER MODE L

and MA<O: 1 1 >L and its

- --- - -- - - - - I
I * LSETTLED
(INCLUDES BUS CHARGE TIME)

OLD

2 5 n s MINIMUM

4 I----

SOURCE H

1
EMA,MA,-ROM ADORES L

------- -

Ã‘Ã‘Ã‘Ã‘Ã

STABLE FROM PREVIOUS READ

TP2 H

-I

IÃ‘

STROBE H

+
1 2 0 ns MAXIMUM
--------

-------MD<0:11 > L
a
a memories t
edge of SOURCE H

MD DIR L

OLD

INHIBIT H

I* I

I -4

I-120ns

1
min

- - - - - --7
- - *I-- - - - - -2 -0 t-o 1-5 0-ns- - MD<0:11 > L
Â¥

New Memory Data o n bus Ã‘Ã‘Ã‘Ã‘Ã‘

NEW Memory Data s e t t l e d

u Uncertain

Uncertain
MD<0,11> changes at T P 2 H only if MD DIR L is
allowed t o go high. IfMD OIR L remains low MD c0.11 >
is settled on the bus at STROBE H leading edge 2 5 0 n s

WIT82

Figure 3-10

Memory Timing

Figure 3-1 1

Write Timing

3.8.4 Basic 1/0 Timing
The Basic I/O timing in Figure 3-1 2 assumes the following:
1.

Single transfer during IOT

No modification of PC (no connection to C2)L

C<0: 1 >L do not go to ground and then positive between the falling edge of I/O PAUSE L and the rising edge of TP3 H.

The peripheral must place its data on DATA<O: 11 >L and assert any C lines at least 2 5 0 ns prior to TP3 H. SKIP L
must be asserted at least 100 ns before TP3 H if a skip is to occur. Peripheral registers are loaded at the leading
edge of TP3 H. Peripheral registers must be edge-triggered, since DATA<O: 11 >L may start to change before TP3
H goes low again.
The timing for the CAF instruction is shown in Figure 3-13.

3.8.5 Expanded I/O Timing
The restrictions of Paragraph 3.8.4 regarding single transfer and limited use of C<0:2>L do not apply.
The timing required to stop the CPU (this operation is not confined to lOTs) using NOT LAST XFER L is shown in
Figure 3-1 4.
TP3 H

INITIALIZE H

Ã‘ k - 2 0 n s m i n

kÃ3 0 0 to 900ns -4

(Never extends t o next T P 3 H)

1 1 0 PAUSE L

DATA<O:ll>L
Indicator
information

[

AÃ‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã

Figure 3 - 13

-------- ------- -------------I

IÃ‘

TP3 H

C A F Instruction Timing

Dependson
C<O:l> L

Break
Priority

Ãˆ

Dimension A = 4 5 0 t o 5 5 0 nsec
Dimension B = 5 0 nsec minimum
1 0 0 nsec maximum
Uncertain

NOT LAST
XFER L

1 0 0 n s mln
-4 I-Ã 2 0 ns m i n

r-------

Figure 3 - 1 4 Timing to Stop CPU
Using Not Last XFER L

Basic I/O Timing

Figure 3- 12

Figure 3-1 5 shows the timing required to make transfers t o or from the AC, or to the PC.
Peripheral data registers should be edge-triggered and loaded at the leading edge of BUS STROBE L (since the contents of the Data Bus may change as a result of sending BUS STROBE L to the CPU).
External loading of LINK must take place only in an expanded I/O cycle, and not at restart time. Figure 3 - 16 shows
the timing for this operation.

- - - - - - - - -f---I

DATA<O:ll > L

1 PERIPHERAL DATA*

C<O:I>L

---

I*Ã‘300nsmin------#

LINK DATAL--

C2 L
BUS STROBE L
( p e r i p h Ã § r a gen8rated
- 1

2 0 t o 150 ns Ã‘*
90-150 n s i

LINK L

OLD

"If required for input transfer. The 350 ns
includes 100 nt for charging the bus.

Transfer Timing

LINK L O A D L

Figure 3 - 15

- - 7 - - - - -I---"bus information
-4 150ns minimum
2 0 ns rninlmum-

~Defined
r--- 4 5 0 ns min ----I L 2 0 n s

NEW

Figure 3 - 16

External Loading of Link Timing

Figure 3-1 7 shows the timing to restart the CPU after the peripheral has completed its data transfers. Loading LINK
is not allowed during this operation because of timing restrictions as the CPU leaves TS3.

3.8.6 Data Break Timing
The timing required to initiate a data break is shown in Figure 3-1 8. These signals are controlled by the device making the break request.
3.8.6.1 Data Exchange - The data exchange timing is shown in Figure 3-19. Data to be placed in memory or
used to modify memory must be in a register which has been loaded prior to TP1 H.
3.8.6.2

Final Operations - The timing required to end a data break transfer is shown in Figure 3-20.

--I l*- 2 0 nsec

*
~
9 0 to150nsec2 0 t o 1 0 0 ns -4

B R K I N P R OTG L:

- - L

CPMA DIS L

priority on
data bus

$;".WEE)

high
4 mans minimum -t
BUS STROBE L

INT STROBE H

NOT LAST XFER L 1

1 '

-4

INT STROBE H

9 0 to 2 0 0 nsec
O t o 5Ons--

I"Ã 5 0 nsec mln.

b-150ns minÃ‘Â
TP4 H
MA<O;I~>~

-- -- - -- - -

110 PAUSE L
( I t IoT 1

n
-!-

O l d MA
I

MS,IR
DISABLE L

+ LTime s t a t e
o f CPU "Ã‘Ã‘IÃ‘Ã‘Ã
20 tot00ns

TS 3

- - - - ---

Break EMA and MA o n bus

50nsmax-

2 0 n s m i n - 4 ~
100nsminG

TS4

TP1 H
MA.MS1 LOAD CONT L '

'This BUS STROBE L is generated by the
controllingperipheral, and causes a data
transfer. The setup time requirementsfor
C(0:2)L and DATA(0:lllL must be met.

Must be low 2Onsec
before next T P 4 H
coding edge.
W.1188

Figure 3- 17

OB-1189

Figure 3-18

CPU Restart Timing

Data Break Timing

BRK I N PROG L

-----a

4 b - 2 0 n s m m -4lINT STROBE H
TP4 H

IÃ‘

I
I

'I----->J

CPMA DIS L
data settled on bus '

4 lÃ‡-20n min

MS,IR DISABLE L

1
4*b

-4 b-2011s

I
min 1

I---.

100ns m i n i t 4 .

OVERFLOW L 1 -

TP3 H
BREAK DATA CONT L must b e s e t t l e d o n
bus a t same t i m e as Input data.

Figure 3-19

2 0 ns mi,, Ã‘ I
.
-

Data Exchange Timing

>Â¥

-----

MA, MS LOAD CONT L
Including bus charge time.

Figure 3-20

MA,MS LOAD CONT L
must be high 20nsec
p r i o r t o TP4 H

End of Data Break Timing

3.8.7 CPU Major States
The timing for the Major State of the CPU is shown in Figure 3-21.
3.8.7.1

IR (FETCH Cycle) - The timing for a FETCH cycle is shown in Figure 3-22.

TP4 H
FL,DL,D

L---

n
- - - -p - -2 0 -t o -1 5-0 n-s e-c
I

OLD
4

b- 2 0 t o 1 5 0 nsec
- - ---- -------

IR<0:2>L--

NEW
(Â¥-4 t o 2 0 0 nsec

----- -------

F SET L ,

OLD

NEW ( o r not v a l i d
I f FETCH 1

F SET L

(Â¥Ã‘40to200ns
I

NOTVALID

NEW

W-1172

Figure 3-21

3.8.7.2

CPU Major States Timing

Figure 3-22

FETCH Cycle Timing

Interrupt Recognition - The timing associated with interrupt recognition is shown in Figure 3-23.

3.8.8 Timing Start and Stop
The timing for starting and stopping the CPU is shown in Figures 3-24 and 3-25.

START

INT

STROBE H

MEM START L y
p
'
4
-90
to400ns
62 0 t o 1 0 0 n s
RUN L
3 5 0 t o 4 5 0 ns Pf i r s t TP1 H
IÃ‘

.
n
4 b-

5 0 n's minimum to be recognized

I N T RQST L

0%1175

1- - -;

I N T I N PROG H

4 I-- 2 0 t o 150 nsec

F SET L

Figure 3 - 2 4

Â4 0 t o 2 0 0 m

Start Timing

4 0 t o 2 0 0 ns 4

~ Ã ‘

ST0 P

- --------

2 0 t o 150 nsec -4

Major states, I R

--.------

STOP L

4 hÃ 5 0 n s

Previous S t a t e
' JMS ond EXECUTE
Â¥Go low a t JMS and EXECUTE and INT STROBE.
,,,

Interrupt Timing

TP3H

-4

RUNL

Figure 3-23

1
-20

' - I

min

t o 150ns

TP4 H
TSl L
CPU stopped
W1116

Figure 3-25

Stop Timing

3 . 9 ASYNCHRONOUS SIGNALS
The following signals are allowed to change asynchronously with respect to the CPU's timing chain:
POWER OK H (when negated also causes INITIALIZE H to change)

sw
IND1 L
IND2 L
INT RQST L
STOP L

3 . 1 0 SPECIAL SIGNALS
The following signals should be asserted only when the CPU is not running:
MEM START L (Paragraph 3.7.9.2)
PULSE LA H ( 9 0 ns min width positive pulse)

3.11

ELECTRICAL CHARACTERISTICS A N D INTERFACING

3.1 1.1 Logic Levels
Low = -0.5 V to 4-0.4 V
High = +3.0 V to +5.0 V.
3.1 1.2 Bus Loads
All bus load resistors are on the CPU module (instead of at the end of the bus) and the resistors are returned t o 4-5
Vdc. The Omnibus is restricted to 12 slots and may not be extended. Maximum bus capacitance is limited to 150 pF
of which 3 0 pF is caused by the 12 slot bus and connectors.
3.1 1.3 Driving the Omnibus
Table 3-2 is a list of Omnibus signals, their load type, if they must sink, drivers, and number of inputs. The load type
( 1 through 6),and type of driver (OC, TRI, and UTI) are defined at the end of Table 3-2.

Table 3-2
Load Resistor and Drivers Summary
Signal

BREAK CYCLE L
BREAK DATA CONT L
BRK IN PROG L
BUS STROBE L
CO L
C1 L
C2 L
CPMA DISABLE L
DL
DATA 0 L
DATA 1 L
DATA 2 L
DATA 3 L
DATA 4 L
DATA 5 L
DATA 6 L
DATA 7 L
DATA 8 L
DATA 9 L
DATA 10 L
DATA 11 L
EL
EMAO L
EMAI L
EMA2 L
FL
FSET L
INDI L
IND2 L
INHIBIT H
INITIALIZE H
INT IN PROG H
INT RQST L
INT STROBE H
INTERNAL I10 L
I10 PAUSE L
IRO L
IR1 L
IR2 L
KEY CONTROL L
LA ENABLE L
LINK DATA L
LINK L
LINK LOAD L
MA0 L
MA1 L
MA2L

Load Type

Driver Must Sink (mA)

60
16
16
16
16
30
16
16
16
16
16
16
16
16
16
16
16
16
30
30
30
30
30
Do not drive TTL output
16
16
Do not drive TTL output
See Note 1
16
16
Do not drive TTL output
16
Do not drive TTL output
16
16
16
16
16
16
Do not drive
60
30
30
30

Drivers

---1-0c
---1-0c

----

-------

---TR I
3-OC
2-oc
3-OC
2-oc
3-0C
2-OC
2-oc
2-oc
2-oc
2-oc
2-oc
2-oc
TRI

-------

---TR I
1-0c

-------

1-TTL
E.F.
2-oc

----

TTL
1-0c
TTL
TR I
TR I
TR I
1-0c
1-0c
1-0c
1-0c
1-0c
TR I
TR I
TR I

Number of
Inputs (TTL)

Table 3-2 (Cont)
Load Resistor and Drivers Summary

Signal

Load Type

MA3L
MA4 L
MA5L
MA6 L
MA7 L
MA8 L
MA9 L
MA 10 L
MA11 L
MA, MS LOAD CONT L
MDOL
MD 1 L
MD2L
MD3L
MD4L
MD5L
MD6L
MD7L
MD8L
MD9L
MD 10 L
MD 11 L
MD DIR L
MEM START L
MS IR DISABLE L
NOT LAST XFER L
NTS STALL L
OVERFLOW L
POWER OK H
PULSE LA H
RES
RETURN H
ROM ADDRESS L
RUN L
SKIP L
SOURCE H
STOP L
STROBE H

Driver Must Sink (mA)

Drivers

30
30
30
30
30
30
30
30
30
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Do not drive
See Note 2
See Note 2
16
Do not drive TTL output
30
Do not drive TTL output
16
Do not drive TTL output
16
Do not drive TTL output

TR I
TRI
TR I
TR I
TR I
TR I
TR I
TR I
TR I

Do not drive TTL output
Do not drive TTL output
Do not drive TTL output
Do not drive TTL output
Do not drive TTL output

TTL
TTL
TTL
TTL
TTL

sw
TP1 H
TP2 H
TP3 H
TP4 H
TS1 L
*Active pull-up when CPU tristate drivers are enabled.

----

TR I
TR I
TR I
TR I
TRI
TR I
TR I
TR I
TR I
TRI
TR I
TR I
1-0c
1-0c
1-0c

------1-0c

---------TTL

----

TTL

----

TTL
3-OC
TTL

----

Number of
Inputs (TTL)

Table 3-2 (Cont)
Load Resistor and Drivers Summary
Signal

TS2 L
TS3 L
TS4 L
USER MODE L
WRITE H

Load Type

Driver Must Sink (mA)

Drivers

Do not drive TTL output
Do not drive TTL output
Do not drive TTL output
16
Do not drive TTL output

TTL
TTL
TTL

----

TTL

Number of
Inputs (TTL)

---3
2 112
2
1

NOTES
1.

INITIALIZE H and PULSE LA H. Driver must supply 30 mA at +3 V, and source less than 1 mA a t ground.
An emitter follower is recommended. Typical circuit is shown in Figure 3-26.

POWER OK H. This line is driven high by circuitry within the power supply, but can be grounded by
options (such as the bootstrap loaders) which need to initialize the CPU and memory extension MA Control
flip-flops. The power supply driver must supply a minimum of 30 mA a t +3 V, and must not supply more
than 100 mA when the output is shorted to ground. Peripheral drivers must sink 200 mA a t 0.4 V, and sink
less than 1 mA leakage a t +5 V.

The DEC 8881 (PIN 19-09705) will meet the 16 and 30 mA requirement. Two8881's in parallel will meet
the 60 mA requirement.
LOAD 1: 470 A2 to +5 V, Clamp to +3 V.
LOAD 2: 390 0 to +5 V, Clamp to +3 V.
LOAD 3: 2-470 S2 in series to -1 5 V, Clamp diode with anode ground.
LOAD 4: 390 A2 to +5 V, ferrite bead in series with pin to limit rise time.
LOAD 5: 390 0 to +5 V, series ferrite bead, Clamp to +3 V on "finger" side of ferrite bead.
LOAD 6: 150 0 to +5 V, Clamp to +3 V.
TRI = Tristate driver
UTI = Utilogic input (SIGNETICS314,380,384 or equivalent)
OC = Open collector

3.12 DRIVE AVAILABLE FOR PERIPHERALS
Table 3 - 3 lists the currents that are available for driving options, memories, etc, from the CPU and memory extension. Signals marked * are generally not used as output from CPU or memory extension.
3.13 RECEIVERS AND LOAD RELIEF TECHNIQUES
The use of Utilogic gates (Signetics SP314, SP380, etc) or other high impedance circuits as bus receivers is strongly
recommended. These gates have high threshold and l o w input drive, and thus present maximum noise immunity
while introducing minimum bus reflections. Since 1 0 m A is available only o n CPU timing and memory timing signals,
buffering and load relief techniques must be used t o decrease loading on the Omnibus.
A typical I/O decoder is shown in Figure 3 - 2 6 . Note the use of buffered I/O PAUSE L. This signal keeps the M D receivers from loading the M D lines, since buffered 1/0 PAUSE L supplies all needed base current t o the three gates
on the M D lines unless I/O PAUSE L is low. Similar techniques should be employed for signals from
DATA<O: 1 1 > L t o peripherals.

Table 3-3
Omnibus Signal Drive Currents
Signal
BREAK CYCLE L
BREAK DATA CONT L
BRK IN PROG L
BUS STROBE L
C<0: 2> L
CPMA DISABLE L
DL
DATA<O: 11>L
EL
EMA<0:2>L
FL
FSET L
IND1 L
IND2 L
INHIBIT H
INITIALIZE H
INT IN PROG H
INT RQST L
INT STROBE H
INTERNAL I10
I10 PAUSE L
IR<0:2>L
KEY CONTROL L
LA ENABLE L
LINK DATA L
LINK L
LINK LOAD L
MA<0: 11>L
MA, MS LOAD CONT L
MD<O: 11>L
MD DIR L
MEM START L
MS. IR DISABLE L
NOT LAST XFER L
NTS STALL L
OVERFLOW L
RES
RETURN H
ROM ADDRESS L
RUN L
SKIP L
SOURCE H
STOP L
STROBE H
TP<1:4>H
TS<1:4>L
USER MODE L
WRITE H

Source mA @ +3

Sink mA @ GND

5
Depends on driver
10
3
5

10
10 Each
10 Each
3
10

Figure 3 - 2 6

Typical I/O Decoder

3.14 INTERFACE EXAMPLES
This section provides the user w i t h interface examples and timing for Programmed I/O, Interrupt, and Data Break
transfers. For a more complete description o f these examples refer t o Chapter 9 of the Miniprocessor Handbook.
The interface examples contain some special integrated circuits. These IC's, which are listed below, were chosen t o
minimize loading o n the Omnibus. Do not replace them w i t h other devices having the same function unless you have
compared input loading and threshold figures (for input devices) or output driver and leakage (for the output device).

Input Devices
Device No.

Manufacturer Type

DEC Part No.

3 14
380
384

SIGNETICS SP314A
SIGN ETICS SP380A
SIGNETICS SP384A

19-09704
19-09485
19-09486

Output Devices
Device No.

Manufacturer Type

DEC Part No.

8881

Several 7438

19-09705

3.14.1 Programmed I/O Interface Example
The Programmed I/O Interface (Figure 3-27) that illustrates the most commonly used transfer consists of:
1.

A device selection circuit

A device operations decoder

I/O control logic and

Input/output buffers.

Device Selection Circuit - M D 3 - 8 bits are used t o carry the device select information. The example in Figure 3 - 2 7
shows the DEC380 and DEC314 being used as a simple device select and operations decoder. When octal 5 2 is received and signal I/O PAUSE L is asserted by the processor, gate 3 1 4 is qualified. The output is used t o assert signals INTERNAL 1/0 L and M Y DEVICE L. No operation can occur unless signal M Y DEVICE L i s asserted by the
device selection decoder.
Operations Decoder - M D 9 - 1 1 bits determine the type of operation to be performed. Three DEC380's are shown
(Figure 3 - 2 7 ) receivinc these bits. The outputs of these gates are in turn presented to a binary-to-octal decoder type
8 2 5 1 and the decoded results control the interface. The lOTs in Table 3 - 4 illustrate the various types of transfers
available.

Table 3-4
lOTs For Sample Interface
IOT

Function
--

N o t used.
Transfer content o f the A C t o the output buffer.
Clear the AC.
Transfer the content o f the A C t o the output buffer and clear the AC.
Transfer the content of the input buffer t o the A C (OR transfer).
Clear the flag.
Transfer the content o f the input buffer t o the A C (jam transfer).
Skip if flag is set (1).

3.14.2 Flag Logic
The flag is represented as a 7 4 7 4 D-type flip-flop. The C and D inputs are used by the peripheral device t o set the
flag. If the flag is an input flag, i t is set when data is loaded into the input holding register. If the flag is an output
flag, i t is set when the data in the output holding register has been processed by the peripheral, (i.e., when new data
may be loaded into the output register without disturbing the output devices operation). Two flags are required for
both input and output transfers.
3.14.3 Interrupt Request
The basic I/O interface may also be used t o perform interrupt transfers by adding a gate t o assert the interrupt
request line when a flag is set by a n external signal (Figure 3 - 2 5 ) . The processor responds to the INT RQST line by
completing the current instruction and then executing a J M S t o location 0. Simultaneously, the interrupt system is
turned off. The execution of the J M S instruction saves the current program count in location 0 . I t is up t o the program to identify the interrupting device by polling (testing) device flags sequentially. After the device has been serviced, the interrupt service routine returns t o the main program with a J M P indirect instruction. It is a good idea to
have an interrupt gate in the logic even if the interrupt system is not going t o be used. There is no penality for adding this gate because the CPU will not respond t o the state of INT RQST unless the interrupt system is enabled or
an SRQ instruction is fetched. Including this gate allows the user to recode the program for interrupt without changing the hardware.
3.14.4 O u t p u t Buffer
The output buffer receives processor data during IOT instructions and outputs data t o a device under control of device timing. This buffer must be a D-type (edge-triggered) register. The command signal that loads the output buffer
also initiates action within the peripheral. The output flag should be cleared at or before the time this buffer is
loaded and should n o t be set again until the device has completely processed the data word.

3.14.5 Input Buffer
The input buffer receives device data at the device timing and applies the data t o the data bus during an IOT instruction. The same signal that loads the input buffer is often used t o set the input flag.
3.14.6 I/O Control
The I/O control includes INT RQST, which immediately responds when the flag is set; SKIP, which is asserted when
IOT 6527 is decoded and the flag is set; CO and C1, which may be asserted by the operations decoder during various conditions of data transfer; and input/output enabling logic, which responds t o the operations decoder and controls the I/O buffers (Table 3-5).

3.14.7 Input/Output Timing for Programmed I/O Interfaces
A timing diagram corresponding t o the programmed I/O interface example is illustrated in Figure 3 - 2 8 . A n explanation of the time periods from A t o J is:

Period

Function

Time

A--D & E--J

350 ns

Time required t o perform the transfer (PAUSE).

A--B & E--F

70 n s

Time required t o decode the device selection and assert I N T E R N A L 110.

A--C & E--H

100 ns

Time required t o decode the I O T and assert the necessary "C" lines or SKIP
and supply data i f needed.
The time when the transfer takes place. Note that the data bus w i l l change a t
this time. This is the reason that edge triggering must be used.

Note:

The C lines control the direction o f data transfer.

3.15 PROGRAM INTERRUPTTRANSFERS
The main difference between Programmed Interrupt transfers and Programmed I/O transfers is the software required.
Chapter 6, Introduction t o Programming, contains a thorough discussion o f software for the interrupt system.
The hardware required for Interrupt transfers is the same as already described under Programmed I/O tranfers, except the gate driving INT RQST L i s required.

3.15.1 Interrupt Timing
Within each IOT, timing is the same as that already described for Programmed I/O transfers. Since several devices
may be simultaneously active using the interrupt system, the speed o f response of the interrupt system is o f interest.
The state of the interrupt system is sampled 3 5 0 ns before the end o f every machine cycle. If a device requests an
interrupt, the CPU will start executing the J M S to location 0, a maximum of 3 machine cycles plus 4 5 0 ns after
receipt of the request. The J M S t o location 0 takes one machine cycle, and the interrupt system is disabled in that
same machine cycle. From this point on, the response time o f the interrupt system depends o n the instruction sequence of the interrupt handler. A typical interrupt handler program requires about 4 0 machine cycles t o completely
handle an interrupt. In critical cases, the user should count up the maximum number of machine cycles that can occur with the interrupt system disabled.

3.1 5.2 Data Break Interface Example
The basic break interface required to transfer data consists of a Break Memory Address register ( B K M A ) t o address
memory independently of the processor; a Break Priority Network t o assure the activation of the device with the
highest priority; Input/Output Buffers, and Break Control Logic. A sample data break interface is illustrated in Figure
3 - 2 9 . The data break sequence of events is described in terms of the primary data break control signals and the processor timing given in Paragraph 3.7.5.

Table 3-5
Transfer Control Signals
TYpe of
Transfer

Transfer
11 Lines
*C1

Information
Gated Onto the
Data Bus

Bus Set-up
Time with
Respect to
BUS
STROBE

Action
Required by
Peripheral at
Interface

Action by
Processor

Contents of
Data Bus
During Transfer

Output AC
Data Bus.
AC unchanged.

AC Register

Load data bus
into buffer.

Transfers AC to
Data Bus. AC remains unchanged.

AC register only. User modification of this type of transfer may
bring undesirable results.

Output AC
DATA Bus

AC Register

Ground CO.

Transfers AC to
Data Bus and
clears AC.

AC Register.

AC Cleared

Load data bus
into buffer.

CO
CJ

Input AC
Peripheral
Data

Peripheral Data
and content of
AC Register.

Gate peripheral
data to data bus.
Ground C1.

Transfers content
of AC to the Data
Bus. The ORed
result loaded into
the AC.

AC ORed with Peripheral Data.

Input Jam.
Data Bus
AC.

Peripheral Data

Gate peripheral
data to data bus.
Ground CO and
C1.

Transfer data bus
to AC Register.

Peripheral Data.

*CO is connected to pin CE 1. C 1 is connected to pin CH 1 on the Omnibus.

c0 L

' 1

I/O
PAUSE L

I/O PAUSE L

C0 L

NOT USED FOR OUTPUT OR SKIP
I

IINDICATORS
1

DATA
BUS

i I !

1 I PRIORITIES

DATA
BUS
BUS
MD

MD
BUS

1 INDICATORS I AC 1

1 1

CHANGING

INTERNAL
I/O L

SKIP L

I
1

IOT 6 5 2
I

I 1
I 1

PRIORITIES

14/6

INTERNAL
I/O L

1 DATA-AC
I
!

[

I 1

NOT USED

OUTPUT TRANSFER OR SKIP
IOT

INPUT TRANSFER

I ACTION

IOT

1 6 5 2 1 1 AC-OUTPUT

BUFFER

1 6 5 2 3 I AC-OUTPUT

BUFFER.0-AC

6524
6526

6527

ACTION
INPUT BUFFER AC-AC
INPUT BUFFER-AC

(OR)

(JAM)

SKIP IF FLAG IS SET

REFER TO APPENDIX D FOR OMNIBUS PIN NUMBERS FOR SIGNALS

Figure 3 - 2 8

Timing for Sample Programmed I/O

3.15.3 Data Break Timing
The important timing consideration in data break (Figure 3-30), as in program interrupt, is whether sufficient time is
available from the time the flag (in this case, the break request) is set t o the time the data is moved in or out of
memory. The PDP-8/A honors break requests between major states of an instruction. The break system is synchronized 3 5 0 ns before the end o f every memory cycle. A t the same time the processor tests for the possibility of interrupt, i t tests for the possibility of break. The break system takes precedence over interrupts. Assuming no
extendedl/O the processor requires n o more than 1 memory cycle i - 4 0 0 ns t o recognize a break request.
As a rule, the user should assign highest priority to the device that has data available for the shortest amount of
time. The user should assume that all devices request data breaks simultaneously and calculate the response time of
the break system as seen by each device t o ensure that response time is less than the maximum allowable for that
device.

I N T STB- TP3
TS 4

I
1
1
I

TP4

1
n

I
I

MY PRIORITY

PRIORITY

CPMA DISABLE

I
I

1 CPMA DISAmED BK MA ENABLED

MAC
MS IR DISABLE

BK REQUEST &\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\y
BK IN PROG

---

1 1

-- -

I
-1

aK CYCLE

1 I

BK DATA CONT

OVFL

1 LOW IF ADM
I
I
I
1 TRANSFER DIRECTION LATCHED
I
1 SET IF ADM OVERFLOWED
I
I
I

I
I

Figure 3-30

- ---

- - .
------ A

I
BREAK C Y U E FOR THIS DEVICE

rn 0-1

Data Break Control Timing Diagram

3.1 6 THREE-CYCLE D A T A B R E A K
I t is possible t o use memory locations as Word Count (WC) and Current Address (CAI registers by using a more complex D M A control. Figure 3 - 3 1 is a simplified diagram illustrating the interaction between the processor and a threecycle data break device. The initial set-up and exit phases include operations similar t o those required for a singlecycle data break; however, the data transfer phase of a three-cycle break is divided into a W C cycle, a CA cycle, and
a data transfer cycle.
During initial set-up, the running program uses instructions t o load the memory locations designated as the dev~ce
WC and CA registers, then executes IOT instructions that initialize the device and specify any necessary transfer parameters. Once the device control circuitry has been enabled, the processor is free t o perform other tasks while the
peripheral accesses storage locations and executes the data break transfers.
Each three-cycle data break begins with a WC cycle during which the device gates the address o f its WC register
onto the Omnibus. The address is fixed (hardwired1,'and is usually an even number (bit 1 1 0 ) address. During the
word count cycle, the contents of the word count location is returned from memory and applied to one leg of the
processor's adder register. The device gates a 1 into the other adder inputs via the data bus, thereby incrementing
the word count. The resulting addition is tested for overflow while the incremented word count is restored t o memory. If overflow occurs, the peripheral clears its &abling circuits and sets its device flag as soon as the current transfer has been completed. In any event, the device concludes each WC cycle by testing the data bus to determine
whether any higher priority device has entered a break request.
If there is no higher priority request o n the data bus, the device immediately begins its CA cycle. The CA memory
address is usually one greater than the WC address. The CA memory location is incremented tn the manner just described, and the incremented value is restored t o memory and also transferred t o the device break address register.
Break priority is tested again at the end o f the CA cycle.

m1
ADDRESS

w71

12-BIT CURRENT ADDRESS

1
1~4-

BIT It = I(CA REGISTER)
BIT 11 =@(WCREGISTER)

INPUT GATES

COUNT
WIREDADDRESS
WORD

MB
REGISTER

Figure 3 - 3 1

Three Cycle Data Break Simplified Block Diagram

During the data transfer cycle, the peripheral generates a signal t o specify the direction of the transfer, gates the contents of its break address register onto the Omnibus, and either accepts or transmits one word of data. If WC overflow did not occur during the WC cycle, the device relinquishes control of the processor and begins t o prepare for
the next data transfer. When WC overflow does occur, the device flag is set and the running program executes IOT
instructions t o perform any operations that may be required t o terminate the block l/O process.
Chapter 5 of Introduction To Programming contains the necessary information to program a three cycle data break
device.

3.17

GENERAL C A U T I O N S REGARDING1 INTERFACE D E S I G N
1.

Minimize capacitance on the Omnibus lines. The Omnibus will work properly only if the 1 0 0 ns allowed
for bus charge time is met. Limit wire lengths on interface modules t o 6 inches per signal. In general,
this requirement means you should place bus receivers and drivers near the pins (which you will do anyway to minimize the crossovers if making a printed circuit board).

Good ground grids on interface boards are mandatory.

Observe normal TTL rules for + 5 volt bypassing. (Normal DIGITAL bypassing is 0.01 mfd per IC, plus a
6.8 mfd tantalum capacitor where power supply voltage enters board.)

Except when gating EMA<O:2> 1- and MD<O: 1 1
react.

> L t o bus ( 5 0 ns max), a peripheral has 1 0 0 ns t o

3.1 8 TRANSMISSION LINE EFFECTS
Rise-times o n the Omnibus are generally long compared t o propagation velocities. Hence most Omnibus signals
should be treated as capacitively-loaded lines.
Some signals driven by TTL drivers are a different matter entirely. These signals must be kept short (less than I foot)
and critical rise times controlled.
The signals which must b e so treated are the nine CPU timing signals, the five memory timing signals, and l/O
PAUSE L.
The characteristic impedance o f the Omnibus itself (about 120 ohms) is a very small part of the overall picture. Of
far more importance is the value and position o f the capacitive load presented by boards connected t o the Omnibus.

3.19 EXTERNAL BUS
There are t w o additional basic techniques of receiving and sending'data t o the Omnibus:

Using the KA8-E Positive 110 Bus lnterface option.

Using the KA8-E Positive 110 Bus lnterface and the KD8-E Data Break lnterface.

3.1 9.1 Positive 110 Bus Interfacing
Previous discussions have brought out the fact that peripherals can be interfaced w i t h either the Omnibus or the external bus. This means that a PDP-8/A user can utilize not only devices designed exclusively for the PDP-8/A, but
also devices originally designed for use w i t h the PDP-811 and PDP-8/L computers - and even devices o f his o w n
manufacture.
This paragraph deals with the external bus, its applications, and the technique of interfacing peripherals t o the bus.
Equipment that was designed for the PDP-811 and PDP-8/L may be used by interfacing t o the external bus; i t can
also be used with the PDP-8/A. The user may want t o transfer data between the PDP-8/A and a remote location.
The external bus, which is designed t o drive long interconnecting lines, is ideally suited for this application.
This paragraph is intended t o answer general question about the external bus and its relationship to the Omnibus.
For a detailed description and timing information about the KA8-E and KD8-E; refer to Volume I1 of the PDP-8/E
Maintenance Manual. You may obtain a copy of this manual from Digital Equipment Corporation, Communications
Services, 146 Main Street, Maynard Massachusetts, 01 754,

3.19.2 The Nature of the External Bus
The external bus is a number of signal lines (88, excluding grounds) that enable data transfers between the PDP-8/A
and peripherals. These lines carry data and control signals between the peripheral and t w o interface boards - the
Positive 110 Bus lnterface (KA8-E) and the Data Break lnterface (KD8-E) that plug into the PDP-8/A Omnibus.
These t w o boards convert the Omnibus signals into PDP-811 and PDP-8/L-type bus signals. For instance, PDP-8/1
peripherals need IOP pulses to perform instructions. The PDP-8/A does not generate internal IOP pulses, but it does
provide signals ( M D bits 09, 10, and I I ) that can be converted into IOP pulses by the Positive 110 Bus interface.
Other signals normally required b y these peripherals are, in essence, available o n the Omnibus. For example, BAC
(buffered accumulator) bits must be supplied for the PDP-811 peripherals. The PDP-8/A data lines carry the necessary accumulator information. The Positive 110 Bus lnterface merely buffers the DATA bits and, thus, provides the external bus BAC signals.
Although the external bus consists of signal lines from both the Positive 110 Bus lnterface and the Data Break lnterface, it is not always necessary to use both boards. When only Programmed 110 transfer peripherals are used, the
Positive 110 Bus lnterface provides all the necessary signals. If data break peripherals are to be connected, both interfaces must be used,. Because each data break peripheral requires its o w n data break interface board, the number of
signal lines comprising the bus may vary. There may be as many as 12 o f these data break peripherals connected in
the system, each contributing 36 signal lines t o the external bus. Figure 3 - 3 2 illustrates the bus and its use when
applied t o a series o f peripherals.

OMNIBUS
DATA 0-11
MD 00-11
TS 1

TS3
RUN
110 PAUSE

INTERNAL 110
TP 1

<
<
<
4

PDP-8/A
PROCESSOR
AND

CONTROL

<
<

<
4

e
4

<
4

<
e

TP3
INITIALIZE
co

>
>
>
>

+
-

*
3

**
3

*
*

BIOP 2
BIOP 4
BTS 3
BTS 1

B INITIALIZE1
POSITIVE
110 BUS
INTERFACE

BMB 00 -1 1,

<
<
<
<

c2
INT RQST
BUS STROBE
NOT LAST TRANSFER

DATA 0-11
MA O - l l
BREAK CYCLE
MA, MS LOAD CONTROLCPMA DISABLE
MS, I R DISABLE
MD DIR
BRK DATA CONT
EMA 0-2
BRK IN PROG

EXTERNAL BUS

- TAcE-IT
- 2)
BIOP

AC 00-11
SKIP
INT RQST
AC CLEAR
B RUN

DATA ADDRESS 00-1 1
BRK RQST
6
DATA OUT
4
MB INCREMENT
<
B BREAK
ADD ACCEPTED
B INITIALIZE 2

+
(12) -

(18)

PERIPHERAL
DEVICE

(,2)

DATA
BREAK
INTERFACE

OVERFLOW
MD 00-11
INITIALIZE
INT STROBE

<
e
<

TP4

-----Figure 3 - 3 2

DATA 00- 1 1

3 CYCLE
CA INC INHIBIT
EXT DATA ADD 0-2
WC OVERFLOW

(12)(31

* - - - - - -

Parallel Connection of Peripherals

3.1 9.3 External Bus Signals
Figure 3 - 3 3 shows not only the external bus signals, but also those Omnibus signals that are used by the t w o interfaces. Signal directions are shown for both buses. Some of the Omnibus signals - DATA 0 - 1 1, for instance - are
common t o both interfaces, but for clarity this commonality has been disregarded. The external bus signals are
grouped according t o the interface connector where they originate. Paragraph 3.19.4 lists the bus signals and the
connector and pin where each may be found). When similar signal lines are represented by one line of the drawing,
as BAC 0 0 - 1 1, the actual number o f lines is indicated in parentheses. The external bus signals are discussed in detail in the following paragraph with emphasis o n the relationship between these signals and the Omnibus signals.
3 . 19 . 4

External Bus Signals

3.19.4.1 BAC 00-1 1 - These signals represent the content of the PDP-8/A Accumulator register (AC). lnformation in the AC is transferred on the Omnibus data lines t o the Positive 110 Bus lnterface. The interface buffers the
signal and provides the BAC output. The BAG bits are strobed into registers in the peripheral when an IOT instruction is generated. 1 = 4-3 V.
3.19.4.2 AC 00-1 1 - The signals on these lines represent the contents of a register in the peripheral. This information is transferred to the Positive l/O Bus lnterface where i t is put on the data lines for transfer t o the PDP-8/A AC.
1 = GND.

18 ACTIVE LINES PER CABLE

1
POSITIVE
110 BUS
INTERFACE

DATA BREAK
INTERFACE
NO. 1

DATA BREAK
INTERFACE
NO. 2

BREAK

DATA
BREAK

PROGRAMMED 1 / 0
TRANSFER DEVICES

EXTERNAL BUS

-X DAISY-CHAINED WITHIN EACH DEVICE.
08-1260

Figure 3 - 3 3

External Bus Signals and Related Omnibus Signals

3.19.4.3 BMB 00-11 - The signals o n these lines represent the contents of the Memory Sense registers. This information is transferred from memory on the Memory Data ( M D ) lines. The M D lines are monitored by the positive
I/O bus interface and the signals are converted t o the B M B bits. These bits are used during IOT instructions;
B M B 0 3 - 0 8 carry the device selection code, while B M B 0 9 - 1 1 are converted t o BIOP pulses. 1 = + 3 V.
3.19.4.4 BlOP 1, 2, and 4 - These pulses are generated in response t o the voltage levels o n MDO9- 1 1 (BIOP4-1 ,
respectively). These pulses generate IOT pulses within the peripheral, causing it t o perform a certain operation. The
width of the BIOP pulses and the interval between pulses are variable and can be adjusted on the Positive I/O Bus
Interface. Pulse = + 3 V.
3.19.4.5 BTS1, BTS3 - These signals represent the TS1 and TS3 signals of the Omnibus. They synchronize operations in the peripheral w i t h those in the computer and perform functions peculiar to the peripheral. They are primar
ily used in data break timing. Pulse = + 3 V.
3.19.4.6

B RUN - If this signal is GND, the computer is executing instructions.

3.19.4.7 AC CLEAR - When this signal is asserted (brought t o GND) along with the AC bits, the result is a jam
transfer o f data t o the AC. The signal may also be asserted by a separate IOP, clearing the AC.
3.19.4.8 SKIP - SKIP is asserted (grounded) by an IOT instruction. I t causes the next sequential instruction t o be
skipped. If the SKIP bus is asserted during more than one IOT of an I/O instruction, the program skips a corresponding number o f instructions. N o more than three skips can be made by a single instruction.
3.19.4.9 B INITIALIZE 1 - This 6 0 0 ns duration positive pulse is used t o clear AC and link and t o clear all flags
in peripherals. I t is generated a t power turn on, and by the Clear All Flags (CAF) IOT, 6 0 0 7 .
3.19.4.10 DATA 00-11 * - These lines transfer data from a data break peripheral to the data break interface. The
peripheral transfers the information when it receives the B BREAK signal from the interface, indicating the start of
the true break cycle. A t TS2 of this break cycle, the data break interface transfers the data to the Omnibus DATA 0 1 1 lines, which carry the data t o the PDP-8/A memory buffer. 1 = GND.

Pertains to DATA Break interface only.

3.19.4.1 1 B BREAK* - This signal is generated in the data break interface and transferred t o the peripheral, where
i t enables a parallel loading o f data, either into or out of the peripheral. The data break interface, in addition t o generating B BREAK, asserts the Omnibus BREAK CYCLE line, notifying the computer that the break cycle has begun. 1
= GND.

3.19.4.12 D A T A OUT* This signal is produced by the peripheral and sampled by the data break interface. When
DATA OUT is asserted (grounded) during the break cycle, data is transferred from the computer's memory to the
peripheral.
3.19.4.13 D A T A A D D 00-1 1 - These lines transfer address information from the peripheral t o the OMNIBUS M A
lines. If the peripheral is a 3-cycle break device, the address represents the memory location o f the word count.
Since this location is always the same for a 3-cycle device, the DATA ADDRESS lines are hard-wired in the peripheral. This address must be even (ending in 0, 2, 4, or 6) for word count. The data stored in this location represents the 2's complement of the number of data words t o be transferred. The next sequential location is read from
memory as the Current Address register.
The data stored in this location represents the memory address of the data t o be transferred. If the peripheral is a 1cycle break device, the address o n the DATA ADDRESS lines is provided by a register in the peripheral and represents the memory address o f the data t o be transferred. The address o n the DATA ADDRESS lines is sampled by
the TP4 pulse. The OMNIBUS CPMA DISABLE line is asserted by the data break interface a t TP4 t o enable the
DATA ADDRESS information t o be placed o n the M A lines. 1 = GND.
3.19.4.14 BRK RQST* - This signal is asserted (brought t o ground) by the peripheral when i t is ready for a word
transfer. When BRK RQST is present at INT STROBE time, the data break operation is entered. The OMNIBUS INT
I N PROG line is asserted, and a load enable signal is provided for the data break interface break memory address
( B K M A ) register.
3.19.4.15 A D D ACCEPTED* - This signal is generated by the data break interface when a BRK RQST signal has
initiated the data break operation. A D D ACCEPTED is used in the peripheral t o clear the BRK RQST flip-flop. Pulse
= GND.
3.19.4.16 M B I N C R E M E N T * - When this signal is at ground level during the true break cycle, the contents of the
memory location are acted upon as outlined in the following table.

MB Increment

Data O u t

Operation Performed

Low

Contents o f the memory location
are incremented.

M B INC

Low

High

Data o n the D A T A 00-1 1 lines
is added t o the contents o f the
memory location.

A d d t o Memory ( A D M )

Descriptive Term
Used f o r Operation

3.19.4.17 CA I N C R E M E N T I N H * - When this signal is asserted (grounded) during the CA cycle of a 3-cycle data
break, the CA is not incremented.
3.19.4.18 3 CYCLE* - This signal is transferred from the peripheral t o the data break interface t o notify the interface logic t o set either the W C flip-flop (3-cycle transfer) (ground input) or the B flip-flop (1-cycle transfer).
3.19.4.19 W C OVERFLOW* - The interface transfers this signal t o the peripheral t o notify it that the word count
location in memory has become zero and that the data transfer should end. The signal is also present when overflow
occurs during M B increment or A D M . Pulse = GND.
'Pertains t o DATA Break interface only.

3.19.4.20 EXT DATA ADD 0-2* These three lines are used when a KM8-AA Memory Extension and Timeshare ,
interface is included in the basic PDP-8/A. The peripheral uses the lines t o indicate the particular memory field involved in the transfer.4
During a 3-cycle data break, WC and CA cycles always occur in field 0, while only the B cycle occurs in the field
specified by the extended data address. 1 = GND.

3.19.4.21 B INITIALIZE 2 * - This positive signal clears all flags in the peripheral and is essentially the INITIALIZE
signal o f the Omnibus, It is used by the break device in lieu of B INITIALIZE 1 t o reduce loading on the latter.
* Pertains to Data Break interface only.

CHAPTER 4
CENTRAL PROCESSOR UNIT

4.1 CENTRAL PROCESSOR UNIT, GENERAL DESCRIPTION
The detailed description of the central processor unit (CPU) relies on logic drawings extracted from the complete set of
drawings and schematics that appear in Appendix H. The extracted drawings are functional and often comprise logic from
more than one sheet of the complete set. Generally, the extracts do not include integrated circuit pin numbers; these can
be found in the print set. Appendix H also contains flow diagrams that relate to the significant CPU operations. Become
familiar with these flow diagrams; they not only describe the overall CPU operation concisely, but also help you understand difficult areas in the detailed logic descriptions.
The CPU manipulates data in response to a predetemined sequence of instructions. In the PDP-8/A both the data
and the instructions are stored in memory. An instruction is brought from memory to the processor where it is decoded to determine, first, what to do to the data, and second, what data is affected. When the data has been manipulated, the result is stored within the processor, transferred t o a memory location, or transferred to some peripheral
equipment.
The CPU logic is contained on a hex-size printed circuit board that plugs into the Omnibus and is assigned the module designation M8315. Because the Omnibus accepts only four printed circuit board connectors, two of the connectors (E and F) extend off the Omnibus. The fingers on these connectors are test points that provide access to
certain significant signals in the Instruction Decoder and in the Timing Generator. These test points are shown in the
logic drawings (CS M83 1 5-01) in Appendix H of this manual.
Figure 4-1 is a block diagram of the CPU. The Programmer's Console, although not physically part of the CPU, is
functionally inseparable. The operator can communicate with the major registers and cause data transfers to occur
by operating various console buttons. Data is transferred between the console and the processor on the DATA lines
in response to control signals generated within the console logic. The console is provided at the customer's option; a
Limited Function Panel (not illustrated in the block diagram) is provided with each PDP-8/A. This panel enables an
operator to turn power on, to lock out most of the Programmer's Console functions (if the console is part of the system), and to initiate memory and processor timing, provided certain options are plugged into the Omnibus.
The basic timing cycle of the PDP-8/A is 1.5 u s and is divided into four time states. The Timing Generator (TG), besides determining the basic timing cycle, provides the synchronizing signals that enable specific CPU operations to
occur during assigned time states. These synchronizing signals are applied to all CPU functional sections as well as
to memory and to options and peripherals.
To perform all the operations involved in retrieving, storing, and modifying information, the CPU utilizes the major
registers. Data is transferred between registers, between registers and memory (via the Omnibus M D lines), between
registers and peripherals (via the Omnibus DATA lines), and between registers and internal options. Transfers are accomplished by a major register gating network that selects the particular register to take part in the transfer and performs
some operation on the data being transferred. The selection and operation performed are determined by control signals
developed within the Instruction Decoder (ID); the ID also provides the control signals that determine the destination of
the transferred data.

1
INSTRUCTION
REGISTER
LOGIC

ROM U

u 1

1-0

LINES

MEMORY
TIMING
SIGNALS

TIME
PULSE
SIGNALS

TIMESTATE
SGNALS

I
MD
BUS

Ac
REGISTER
GATING

CONSOLE CONTRCC
SIGNALS

1 AC REGISTER

1 GATING SIGNALS

, ,

, D;;y ,

L
;DDER

LOGIC GATING

LOGIC G A T I N G

L I N K AND S K I P
CONTROL S I G N k L S

I
I 1 0 CONTROL
SIGNALS

MA BUS

MDBUS

DATA B U S

OMNIBUS

!I-

M A d O R REG4STER
G A T I N G CONTROL
SIGNALS

CONTROL
SIGNALS

T ISIGNALS
M E STATE

LOGIC GATING

Figure 4-1

CPU Block Diagram

TIME
4 NPDU L S E
TtME STATE SIGNALS

DATA BUS

The signals that control the major registers and their gating are developed within the ID largely in response to three
variables:
1.

Basic instructions (as decoded by the Instruction Register logic)

Processor major states (as determined by the Major State Register logic)

Time states and time pulses.

These variables are combined in a number of Read-only Memories (ROMs) to produce control signals that make the
major register gating network function.

4.2 TIMING GENERATOR
The various PDP-8/A operations take place in designated time periods of the operating cycle. These time periods are
delimited by signals produced in the Timing Generator, located on the CPU printed circuit card. Signals TS1 through
TS4 divide the timing cycle into four nearly-equal states, while signals TP1 through TP4 identify the end of each
time state; these t w o groups of signals form the foundation for all control signals used in the CPU and in memory.
Figure 4-2 is a block diagram of the Timing Generator. Central to the generator is the Timing Register logic that provides gating signals for both the CPU Timing logic and the Memory Timing logic. Basic inputs to the Timing Register
logic are supplied by a crystal-controlled clock and by initializing logic that operates when power is applied to the
CPU and when the user initiates timing. Normal operation of the Timing Register logic can be modified by either the
Memory Stall logic or the I/O Transfer Stall logic. The former suspends timing to accommodate memory that has a
slower-than-normal cycle time; the latter suspends timing t o facilitate multiple I/O transfers between the CPU and a
peripheral.

MEMORY
TIMING
LOG1C

20MHz
CLOCK

STROBE
SOURCE
RETURN
INHIBIT
WRITE

TO, T 1
TIMING
REG I S T E R

MEMORY
STALL
LOGIC

NTS
STALL L

Figure 4-2

^Ã‘

MDO-2

NOT LAST
XFER L

Timing Generator Block Diagram

4.2.1 Power On/Run Logic
The Power On/Run logic is shown in Figure 4-3. The CLEAR L signal and the GO(1) signal are generated in this'
logic and are used t o begin the timing register operation. The RUN L signal is also produced and is used by the front
panel t o indicate that timing cycles are being generated. Included in this logic is the auto-start circuit that enables a
user t o have a program begin automatically at a pre-selected address.

QUAD FF

DATA 0 L

------

DATA 1 L
DATA 2 L

CLEAR
L

DATA 3 L
DATA 4 L

RUN L

ME)

RK0)

Figure 4 - 3

STARTL

I A

E21
DIlb.1

ON L

Power ON/RUN Logic

When the power is turned on, POWER OK H (a logic signal generated in the dc power supplies) remains low until
the dc voltages have attained a predetermined value. Throughout the time that POWER OK H is low, the CLEAR L
signal is asserted. Also, during this time, the dc voltages, while not yet at the predetermined value, are of sufficient
magnitude t o allow the logic t o operate. Consequently, the ON L signal is generated, holding the RUN flip-flop in the
clear state. When POWER OK H is asserted, the ON DLY one-shot multivibrator is triggered (CLEAR L is negated
approximately 3 0 p s later because of the delay circuit that includes NOR gate E36; this delay has greater significance when POWER OK H is negated for some reason, as will be shown later in this section). The ON L signal remains low 1 0 0 ms, long enough for all memory circuits t o stabilize before operations are attempted.
When the ON L signal is negated, the RUN flip-flop can be set if MEM START L is asserted. M E M START L can be
asserted automatically or manually, depending on the user's wish. For the moment, assume that the auto-start feature is disabled and the user causes the M E M START L signal t o go low by pushing the RUN button on the Programmer's Console. The RUN flip-flop is set, asserting the RUN L signal and enabling the next clock pulse t o set the
GO flip-flop. The resulting high GO(1) signal permits the Timing Register t o begin its shifting operation.

The M E M START L signal can be asserted automatically soon after ON L i s generated. The CLEAR L signal holds
both E42 flip-flops in the clear state when power is applied. If the OFF contact of switch S1 is open, as shown in
Figure 4-3, the MEM START L line is grounded (the Timing Generator is always in time state one - TSL L is asserted - when not running). Thus, as soon as ON L is negated, the RUN flip-flop is set by the M E M START L signal.
The nature of the RUN flip-flop (DEC74S74) is such that when the clear and preset inputs are l o w at the same time,
both the 1 and 0 outputs are high. When one of the inputs goes high, the other input then prevails. Thus, when ON
L goes high, M E M START L sets the RUN flip-flop.
The auto-start feature is selected by the user with switch S1, a two-position switch with individually movable contacts. If the OFF contact is open, the auto-start feature is enabled; when this contact is closed (in the ON position),
the resulting ground prevents automatic assertion of M E M START L. When auto-start is selected, the program begins automatically a t the address specified by one of the top five contacts (Figure 4-3). Thus, if contact 4 K i s closed,
the program will begin at address 4000(8); if contact 4 0 0 is closed, the program starts at address 0 4 0 0 ( 8 ) (although all five contacts may be left open, causing the program t o start at address 0000(8), only one of the contacts
may be closed a t any time). If contact F7 is open, the address selected will be in instruction and data field 0; if F7
is closed, the address is in instruction and data field 7 . When there is no memory extension control on the Omnibus,
field 0 is selected regardless of the setting o f contact F7. Refer t o Paragraph 4.6.4, which describes the sequence of
operation for the auto-start feature.
The Timing Generator can be halted by a program instruction, by various front,panel operations, or by negation of
the POWER OK H signal. All of these occurrences cause the STOP L signal t o be asserted; the next TP3 H pulse
clears the RUN flip-flop, and TP4 H then enables a clock pulse t o clear the GO flip-flop. The timing halts at the beginning of TS1 L.
When POWER OK H goes low, because power is turned off or because a dc voltage drops below a desired level, a
delay circuit prevents the CLEAR L signal from immediately clearing the GO(1) flip-flop, and, thereby halts timing prematurely (premature timing halt is undesirable because of the likelihood of altering the contents of core memory). Instead, the delay of approximately 30 u s ensures that the RUN and GO flip-flops are cleared at TP3 time and TP4
time, respectively; thus, timing proceeds t o its normal conclusion.

4.2.2 Timing Register Logic
The Timing Register logic is shown in Figure 4-4. The register comprises four DEC74S194 integrated circuits - 4bit, bi-directional, shift registers. The four registers are shown in the configuration that applies during normal operation, i.e., when neither of the stall networks is active.
The diagram in Figure 4 - 5 will help you visualize the process used t o generate the timing signals. Conditions at time
t o of this diagram can be characterized thusly: Power has been applied t o the CPU; the 2 0 Mhz clock is producing
clock pulses; the dc voltages have attained a level sufficient t o assert the POWER OK H signal; timing has not yet
been started by the user ( M E M START L is high). Under these conditions the outputs of registers E9 and E l 6 are
low, the outputs of E l 1, except R2(1), are low, and the outputs of â ‚ ¬ may be low or high, depending o n the state
of flip-flop E8 at power-on.
When the user causes M E M START L t o be asserted, the GO flip-flop i n the Power On/Run logic is set, asserting
the GO(1) signal. Registers E9 and E l 1 are placed in the right shift mode. Each clock pulse shifts a l o w into R3(1)
of E l 1, while shifting-down the high that began in R2(1). When the high is shifted into E9-R1 ( I ) , the STP (Set Time
Pulse) signal places register E l 6 in the right shift mode. The next clock pulse causes E16-R3(1) (TO) t o assume a
state opposite t o that exhibited by E16-R2(1) ( T I ) before the clock pulse. Simultaneously, the CTS signal places E9
and E l 1 in the parallel load mode. The new state of TO is then loaded into E l 1, E l 1 and E9 revert t o the right shift
mode, and the shifting process is repeated. Each time the STP signal goes high, E l 6 is placed in the right shift
mode and either TO or T I changes state. Because the change of state is coincidental with the transition of register
stage E9-RO(1), the signal from this stage is called CTS (Change Time State), although the change is actually effected by the STP signal. The TO and T I signals, besides being essential in the Timing Generator, are used in the CPU
t o generate many major register gating signals.

110 STALL

S1
4-

DS2
R3(1)

D2 74~194R2(1'
STP

l 6

s
CLR CLK

CLEAR L
CLOCK

INPUTS

S 0 CLK DSO DS2

CTS

INT STROBE L

CLR S l

PARALLEL I N
0 3 0 2 Dl 0 0

x l x l x l x

OUTPUTS
R3(l) R 2 ( 1 )
L

Rid)

R0(1)

X = ~ o n ct a r e
a ,b ,c ,d = Level of steady - state inputs at D3. D2. Dl, DB.

R N (1) 0 = Level of R N (1 before, the indicated steady-state
conditions were established.
RN ( 1 ) n = Level of R N (1) before the most recent upward
transition of the clock.

Figure 4-4

Timing Register Logic

DSO

CLR CLK

RK1)
R0(1)
DSO

7 Pons
CLOCK

rUTJTJ-LnJTnJTJTJTnJVTJTTUUTJ-U^^

â‚¬16-

PARALLEL LO

SERIAL
SHIFT

â‚¬16- (1)(T0)

E 9 , E i 1 -S1

SERIAL
PARALLEL). SHIFT
LD

MEM START L

I
1

I N T STROBE H

â‚¬12-

E12-R1 ( I )

â‚¬12-R0<

L - - - -

Figure 4 - 5

Timing Register Normal Timing

4.2.3

CPU Timing Logic
The CPU Timing logic is shown in Figure 4-6. The Timing Register signals TO and T I are applied t o a decoder,
DEC74S139, which generates the four time state signals (refer t o the function table). Then each time state signal is
applied to a pulse synchronizer, DEC74120, the associated time pulse signal is produced (the pulse synchronizers for
TP2, TP3, and TP4 are not shown; they are similarto that of TP1).
The Timing Register signals LD and STP enable the clock to set and clear the TPC (Time Pulse Clock) flip-flop. The
resulting TPC H signal acts as clock for the pulse synchronizer, generating a time pulse signal of 1 0 0 ns width. Figure 4-7 is a diagram of the CPU timing signals.

4.2.4 Memory Timing Logic
The Memory Timing logic is shown in Figure 4-8, while a timing diagram is given in Figure 4-9. STROBE H,
SOURCE H, RETURN H, INHIBIT H, and WRITE H are used by memory to control the read and write portions of the
timing cycle. RETURN H and SOURCE H, generated during both halves of the cycle, turn memory current on; the
conjunction of these two signals determines the width of the current pulse. RETURN H remains high 5 0 ns longer
than SOURCE H to ensure that the memory stack does not retain a capacitive charge. STROBE H, generated only
during the read half of the cycle, provides a time reference from which the outputs of the sense amplifiers are sampled. WRITE H and INHIBIT H are asserted only during the write half of the cycle; WRITE H enables the proper
read/write switches, while INHIBIT H turns on the inhibit drivers associated with memory control. Refer to Chapter 5
for details concerning memory operation.

TPC L

1 1 1

INHIBITED
TP1 L, TP1 H

NOTE:
TP2, TP3, 8 TP4 generated in the
same way as TP1.

Figure 4 - 6

CPU Timing Logic

4.2.5 I/O Transfer Stall Logic
Because o f gating delays, some PDP-8/A-compatible peripherals need more time for an 1/0 transfer than is available
w i t h normal processor timing; furthermore, some peripherals must make more than one I/O transfer during a single
IOT instruction. To satisfy these requirements, the I/O Transfer Stall logic, shown in Figure 4 - 1 0 , interrupts normal
processor timing and stall the timing signals in TS3. The peripheral controller must assert the NOT LAST TRANSFER L signal t o initiate the stalling operation. A t the next occurrence of TP3 the processor timing is halted. The peripheral transfers the information, generating a BUS STROBE L signal w i t h each w o r d of data transmitted. This
continues until the controller negates the NOT LAST XFER L signal, signifying that the next B U S STROBE L signal
issued will be the last. This last B U S STROBE L signal restarts the processor timing, allowing T S 3 t o end and T S 4
t o begin.
The I/O Transfer Stall differs from the M e m o r y Stall significantly: The former stalls timing only in TS3, the latter in
any time state; an I/O Transfer Stall occurs near the end o f the time state, while the M e m o r y Stall occurs at the beginning; I/O Transfer Stall affects the memory timing signals in n o way, while M e m o r y Stall is primarily concerned
w i t h these signals. Despite these differences, the stalling process is effected, essentially, in the same way, i.e., the
CTS signal, which places shift registers E9 (Figure 4 - 1 0 ) and E l 1 in parallel-load w h e n high, is held active by the
signal a t the corresponding register input (input DO of E9); therefore, the Timing Register cannot be shifted d o w n
and timing signals are stalled.

-I
CLOCK

rSons

STP

TS4 L
TPC H
T p l I4

TSl L

350ns

Figure 4-7

CPU Timing Signals

INHIBIT H

c
SOURCE H

RETURN H

STROBE H
TPI L
CLEAR L

R0(1)

ICLR
CLK DSE
TP2 L

WRITE H
08-1272

Figure 4-8

Memory Timing Logic

STROBE H
SOURCE H

RETURNH

INHIBIT H

WRITE H

08 -1273

Figure 4-9
I 1 0 PAUSE L

Memory Timing Signals

I 1 0 PAUSE H

S BUS ST8

-hi

z
Sl

MDf L

BUS STROBE L

74120
PULSE
SYNC

EI9

S I N 1 ST8
I N 1 STROBE H

TPC L

I N 1 STROBE L

I 1 0 STALL L
I

- LD
- STP
+CTS

NOT LASTXFER L

Figure 4- 10

l/O Transfer Stall Logic

The logic in Figure 4-10 is effective not only when timing must be stalled, but also when an 110 transfer can be
made without the necessity of interrupting the timing cycle. When the instruction in the addressed memory location
is an IOT instruction, NAND gate E l 8 asserts the 110 PAUSE L signal when the TP1 L signal comes true during the
Fetch cycle, If the IOT instruction does not require an extended timing cycle, the NOT IAST XFER L signal remains
high; thus, during TS3 both the S BUS STB and S INT STB signals are asserted. The TPC signals generated at TP3
time trigger the pulse synchronizers producing the BUS STROBE L signal and the INT STROBE signals. The active
BUS STROBE L signal causes the AC register or the PC register to be loaded, while the active INT STROBE L signal
enables the timing cycle to proceed into TS4.
If the timing cycle must be extended, the peripheral controller grounds the NOT LAST XFER L line before TP3, preventing the pulse synchronizers from being triggered by the TPC pulses. The controller must provide a BUS STROBE
L signal along with each data transfer. To stall the timing cycle, the NOT LAST XFER L signal must cause the CTS
signal to be suspended in its high state (Figure 4-1 1). NOT LAST XFER L does this by enabling the clock to set the
110 STALL flip-flop, which is then latched in the set state; 110 STALL L generates the required high DO input at shift
register E9, suspending CTS and, consequently, holding E9 in parallel load. Because E l 6 is halted in parallel load by
the same signal, 110 STALL L, the Timing Register stalls just before the normal end of TS3 L, even though the TP3
pulse is completed.
The timing cycle remains stalled until NOT LAST XFER L is negated, at which time S INT STB is asserted (S BUS
STB is also asserted but has no significance at this time). The last BUS STROBE L generated triggers the INT
STROBE pulse synchronizer, producing both INT STROBE signals. The first clock pulse to occur after INT STROBE L
is asserted brings the ISD signal low, thereby placing E l 6 in the right shift mode and causing the D-input of the 110
STALL flip-flop to go low. The next clock pulse clears the 110 STALL flip-flop and places E l 6 in parallel load once
again. The third clock pulse brings the CTS signal low, and normal timing operation is resumed.

4.2.6 Memory Stall Logic
The Memory Stall logic is shown in Figure 4-12. This logic is designed t o modify the normal operation of the Timing
Generator so that memories that have a cycle time slower than 1.5 p s can be used with the PDP-8/A CPU. A slower
memory grounds the Omnibus NTS STALL L line to halt the Timing Generator during one or more processor time states
of a timing cycle. In order to stall the generator in a particular time state, the memory logic must assert the NTS STALL L
signal at least 100 ns before the time pulse that precedes the time state in which the stall is to occur. For example, to
suspend the timing in TS3, the memory must assert NTS STALL L at least 1 0 0 ns before TP2. The timing will halt at the
beginning of TS3, except for the TP2 signal, which is completed during its normal time; the timing remains in the stalled
condition until the NTS STALL L signal is negated.
Figure 4-13 is a timing diagram that illustrates the process just described, i-e., the Timing Generator is stalled at the
beginning of TS3. This diagram shows NTS STALL L being asserted during TP1 and negated approximately 700 ns
later. Fifty nanoseconds after NTS STALL L is negated, the normal timing resumes and TS3 L is asserted for the
usual period of 4 0 0 ns. Note that the WRITE H signal is'stalled along with the processor timing signals. This is the
only memory timing signal whose duration is affected by the stalling process; all other memory signals are active for
the usual length of time regardless of the time state chosen for stalling. For example, if NTS STALL L is asserted
before TP1, the timing halts at the beginning of TS2; however, STROBE H, SOURCE H, RETURN H, and TP1 are
completed in the normal period of time.
Table 4 - 1 indicates the result achieved by stalling the timing generator at the start of each of the time states.

4.3 FRONT PANEL OPERATIONS
There are two types of control panels for the PDP-8/A. The Limited Function Panel is supplied with each computer;
it enables an operator to turn the computer on, and it provides several elementary indications of the PDP-8/A8s operating condition, The Programmer's Console, KC8-AA, is an option that enables one to control computer operations
and to make step-by-step checks on significant conditions within the computer.

TI0

TI5

T20

T25

T 35

T30

CLOCK

Ell-Rl (I 1

I10 PAUSE H

NOT LAST XFER L
S BUS STB

S I N T ST0

1
J

I
]

TS3 L

110 STALL L

1
08-1276

Figure 4-1 I 110 Timing (NOT LAST XFER L Asserted) (Sheet 2 of 2)

NTS S T A L L L

08-1277

Figure 4- 12

Memory Stall Logic

4.3.1 Limited Function Panel
Two Limited Function Panels are in use; one is used with the PDP-8/A Semiconductor computer, while the other is used
with the 8A computers. The switches, indicators, and circuit components of each panel are mounted on a circuit board
that is attached to the rear of the panel; the switches protrude through the panel and the indicators are visible through
panel openings. The circuitry associated with each panel is the same, but the location of circuit components differs, as is
shown by Figures 4- 1 4 and 4- 15. Connector J 1 of the 8A-type circuit board connects to the H9194 Omnibus, while J 1
of the PDP-8/A semiconductor-type circuit board connects to the H9192 Omnibus via the Power Board Assembly. The
following description applies equally to each circuit board, except where noted otherwise.

The three LED indicators provide a basic indication of the computer's operating condition. In the PDP-8/A Semiconductor
computer, the BATTERY CHARGING indicator lights when the battery charger circuit on the power supply regulator
board is operating; when charging current ceases to flow, the LED is extinguished, indicating that the battery is fully
charged. In the 8A420, 8A620, and 8A820 computers the BATTERY CHARGING indicator lights when both G8018
regulators are operating correctly. The indicator is not used in the 8A400, 8A600, and 8A800 computers. The POWER
indicator monitors the secondary of the power transformer; when lighted, it indicates that ac power has been applied to
the computer. The RUN indicator lights when the Timing Generator is turned on and the Omnibus RUN L signal is
asserted. RUN L turns off transistor E1C allowing the LED to glow; when the Timing Generator is off, E1C conducts and
the LED remains dark.
The three switches on the front of the panel permit limited control of the computer. The PANEL LOCK switch is
shown in the active (up) position, the position that disables the console pushbuttons, except LSR and DISP. The
BOOT switch, shown in the inactive (down) position, is used to initiate bootstrap loading of programs. When the
switch is in the position shown, transistor E1A is off and the BOOT signal is high (BOOT becomes SW L on the Omnibus). To initiate a bootstrap operation, the operator must raise the BOOT switch and then return it to the down position. When the switch is raised, transistor E l D is turned off, causing E1A to turn on; this action brings the SW L
signal low. When the switch is returned to the down position, E1A is turned off and the SW L signal goes high. The
low-to-high transition is used by the Bootstrap Loader option (M8317) to begin the bootstrap operation.
The computer's primary power can be controlled from two locations - the Limited Function Panel, where the
ON/OFF switch enables the operator to turn the power on or off, and a remote position, where the POWER
REQUEST signal can be switched to turn the power on or off. The MASTER/ SLAVE switch determines the source
of primary power control. With the switch in the MASTER position the panel ON/OFF switch assumes control; with
the switch in the SLAVE position, the remote location assumes control (the power can be turned off by the panel
ON/OFF switch even though the SLAVE position has been selected).

gg
-zodw( Gmz-wE =&-mE
n
I

aI i

n
I

If)

Table 4-1
Time State Stall Results
NTS S T A L L L Asserted Before

e State Stalled

Result
The time from the end of read t o TP2 is increased, accommodating memories with long
read-access time.
The time from the loading of the MB register
t o the start of write is increased.
The time from the start of write t o the change
of address is increased, accommodating
memories with a long write time.
The time from the change of address t o the
start of read is increased.

The two switches are illustrated in Figures 4 - 1 4 and 4-1 5, along with part of the associated circuitry. The circuitry
and the signals are discussed in detail in Chapter 7, Power Supply; only the result of the switching operation is presented here. Table 4-2 shows what happens when the switches are in the indicated positions. The LINE LEVEL signal shown in the figures is a measure of the ac line voltage and is present as long as the ac line is connected to
the computer.

4.3.2 Programmer's Console
Figure 4-1 6 is a block diagram of the PDP-8/A Programmer's Console logic. Included in the block diagram is the
console control logic, part of the I/O option board (DKC8-AA) that plugs into the Omnibus. The console logic is contained on two printed circuit boards that are mounted on the rear of the console. The two boards connect electrically
by short lengths of cable; the console connects to the I/O option board by a cable that can be as long as 15 feet,
enabling the console to be located remotely from the PDP-8/A mainframe.
There are 2 0 pushbuttons, 8 LED (light-emitting diodes) indicators, and 9 7-segment LED displays visible on the front of
the console. See Chapter 1 for a description of the indicators and controls for both the Programmer's Console and the
Limited Function Panel.
The Programmer's Console pushbuttons can be grouped into number buttons and function buttons. Number buttons
are used to specify addresses and data, and to select the data from a specific source (for example, the AC register or
the DATA bus) for display in the DISP readout. When a number button is pushed, the number is displayed as the
right-most digit in the DISP readout. If a second number button is pushed, it appears as the right-most digit, while
the first is shifted left by one position. Any number of digits may be entered in the DISP readout, although only the
four displayed have meaning; collectively, the digits are referred t o as the "entry."
Function buttons are used t o start and stop CPU timing, to initialize selected CPU hardware, to load addresses and
data specified by the entry, and t o display the data from the source selected by the entry.
When the operator pushes a function button, the logic generates the signals KFUNO L, KFUN1 L, and KFUN2 L in a
combination that is peculiar to that button. The button is identified as "number" or "function" by the NUM H signal
or the FUN L signal, respectively (only one number or one function button can operate at the same time). Either of
these two signals causes the clock timing logic to assert three basic timing signals, KEY ST0 H, MCLOCK L, and
KEY F L.

BATTERY CHARGING

1I 4

R3
470

R4
820

POWER

0
6

RUN

12
0

AC O F F L

I I
E1D

R5
820

- - - .-'

Dl
0672
n

I 0
I

D2
D672

R6
820

.a.

LINE LEVEL

D3
^lN4004
POWER R E Q U E S T

Figure 4-14

8
0

Limited Function Panel Circuit Board Schematic, 8A Computers

If a number button has been pushed, the signal combination representing that button is loaded into the number shift
register, gated through a data selector by the GATE ENT L signal, and loaded into the DISP flip-flops. The readout
control logic generates signals that multiplex the number data to the DISP readout circuits on the DISPLAY 0, 1,
and 2 lines, while at the same time asserting signals that direct the number data to the correct digit of the DISP
readout. When the operator pushes a second number button, the first number is shifted to bit position two of the
number shift register, while the second number is loaded into bit position one. Both numbers are gated to the readout circuits as just described and displayed in the correct digit position. A third and fourth number can be entered in
the same way. The DISP readout then shows the octal representation of whatever the entry is intended to specify,
the most significant bit of the data being contained in the left-most digit. This entry is displayed until the operator
pushes either another number button, changing the content of the number shift register, or a function button, disposing of the entry.

-----

LIMITED
FUNCTION 1 6
10POWER BOARD ASSEMBLY
1 PANEL CIRCUIT
BOARD 1
1
-

pK-1;, @!'

CHARGING

BATTERY

I---

E1C

CHARGING

RUN L

BOOT

^
P A N E L LOCK

AAC

OFF L

-!i

'SLAVE

POWER
REQUEST

BATTERY O F F

Figure 4-1 5

Limited Function Panel Circuit Board Schematic,
PDP-8/A Semiconductor Computer

The disposition of the entry depends upon what the entry represents; i.e., is it an address or is it data? If it is an address,
the operator can transfer it to the CPMA register by pushing the LA (load address) button. When this button is pushed,
the signals representing the LA function are loaded into the latch circuits and applied to a decoder. The decoder output
causes the gating logic to generate signals that gate the entry to the CPMA register via the Omnibus DATA lines. First,
the GATE ENT L signal selects the output of the number shift register for transfer to the console control logic on the BUS
0-1 1 lines. Then, the KCCN 1 SR ENABLE L signal is asserted by the interface gating logic, placing the entry on the
Omnibus DATA 0-1 1 lines. Transfer control signals asserted by the interface gating logic direct the information on the
DATA lines to the CPMA register and cause the register to be loaded.

Table 4-2
Primary Power Control

MASTERISLAVE Switch

Condition of transistor E l B is irrelevant.
POWER REQUEST signal is grounded
(irrelevant in this situation).
Line voltage is applied t o the power
transformer.
I f POWER REQUEST is not grounded
at the remote location, El B is on; thus,
AC OFF L is low and ac line voltage
is not applied to the power transformer.
BATTERY OFF is grounded in the
power supply to prevent the battery
supply from operating.

AC OFF L is grounded, causing the ac
line voltage t o be removed from the
power transformer.
BATTERY OFF is grounded to prevent the battery supply from operating.

MASTER

AC OFF L is grounded, causing the
ac line voltage to be removed from
the power transformer.
BATTERY OFF is grounded to
prevent the battery supply from
operating.

SLAVE

I f POWER REQUEST is grounded,
E l B i s off. AC OFF L and BATTERY
OFF are high. Line voltage is applied
to the power transformer.

If the entry is data, rather than an address, it can be deposited in a memory location that is addressed as just described.
The DTHIS or DNEXT button causes the gating logic to assert the GATE ENT L signal, placing the entry on the BUS 0-1 1
lines. Again, the KCCN1 SR ENABLE L signal passes the entry to the Omnibus DATA 0-1 1 lines where it is routed to the
MB register and placed on the M D 0-1 1 lines.
Rather than depositing the data in memory, the operator can load it into the switch register for future use by pressing the LSR button. At any later time, he or she can display the contents and, if necessary, make changes manually;
the operator can also program certain operations that use whatever data is stored in the register.
To display the contents of a register or of another available source, the operator pushes one of the buttons numbered from 0 to 6 . The source of data represented by each of these numbers is indicated above the button. Thus,
when the operator wishes to view the contents of the AC register, for example, he or she first pushes the button
numbered "0". The signals representing number 0 are loaded into the number shift register and the number is dis3
played in the right-most digit of the DISP readout. Then, the operator pushes the DISP function button. The output
from the BCD-to-decimal decoder clocks the ENTO H, ENT1 H, and ENT2 H signals into flip-flops; the flip-flop outputs, DISPO H, DISP1 H, and DISP2 H, cause the AC indicator to light. At the same time, the interface gating logic
asserts Omnibus signals that gate the AC register contents onto the DATA 0-1 1 lines; the KCCN1 DATA ENA L signal gates the DATA line signals through the selector to the BUS 0-1 1 lines. From the BUS 0-1 1 lines the AC contents are routed through the DISP flip-flops and the multiplexer to the DISP readout; they are displayed there until
another number or function button is pushed.

E N T 0,1,2

GATE
SR L

GATE
ENT L

SWITCH
REGISTER

NUM H

NUMBER
BUTTONS

K FUN 0.1.2 L

TIMING
LOGIC

Ã CLOCK L

KEY F L

LATCH
CIRCUITS
ENABLE

t
NOTE:
Unless noted, logic i s P/0 MS 40421

BCD- TO
DECIMAL
DECODER

pRUN, HLT
E THIS, E NEXT
D TH1S.D NEXT

Figure 4-16 Programmer's Console Block Diagram (Sheet 1 of 2)

GATE ENT L

GATING
LOGIC,
BUFFERS

PANEL 8 CPU

DISP
FLIP-FLOPS

CLOCK

DSP LTH L

ADDR
FLIP-FLOPS

I
ADDR 0.1.2 H

DISPLAY 0.1.2 H

MUX

A D D R S I D I S P OCTAL READOUT CKTS
4

1
I

I
\
\
MPX A

MPX B

CLOCK

t
D I S P 0.1.2 H

ADD LTH L

DIGIT
CONTROL
SIGNALS

CONTROL

GATE SR L

I
I
I

CONTROL

PANEL 8 CPU CONTROL

SIGNALS

1
I

I
I N T ERFACE
GAT I NG
LOGIC

08-1282

Figure 4-16 Programmer's Console Block Diagram (Sheet 2 of 2)

Clock Timing Logic - The clock logic is shown in Figure 4-1 7. The logic includes two priority encoders
( E l and E6), t w o one-shot multivibrators (E18), two flip-flops (E23), and a 4-bit shift register (E24). The one-shot
multivibrators comprise a free-running clock-pulse generator that produces a 4 0 0 ns MCLOCK L pulse every 1 ms.
This MCLOCK L signal is used throughout the console logic and is fundamental to the operation of the clock timing
logic.
4.3.2.1

When the operator pushes a button on the front of the console, one of the priority encoders generates a binary representation at the AO, A1, and A2 outputs. These outputs become the KFUNO L, KFUN1 L, and KFUN2 L signals that
are important in the logic that follows (Table 4 - 3 lists the console pushbuttons and the corresponding binary representations.) The encoder also produces a signal at the GS output (FUN L or NUM L); this indicates the identity (function or number) of the selected pushbutton and causes a low voltage level to be applied to the serial-input line
(DSO) of the 4-bit shift register (unless a button on the console is pushed, this shift register is constantly right-shifting a high voltage level that appears at the serial input; consequently, the register is always fully-loaded, except
when front panel operations are in progress). The 4th MCLOCK L pulse to appear after the button has been pushed
shifts a low into bit position 4 of the register (R3(1)), thereby causing flip-flop E23A and, in turn, E23B to be set.
Thus, the KEY F L and KEY STB H signals are generated, KEY STB H being somewhat less than 4 0 0 ns wide due
to the delay in E24 and E23. Figure 4-18 shows the timing of the clock timing logic.
Note that 4 MCLOCK L pulses must be counted by the shift register after the pushbutton has been activated (i.e.,
when NUM L is asserted). This requirement ensures that switch contact-bounce will not affect circuit operation. For
the same reason, four pulses must be counted after the button has been released (if a new button is pushed before
this happens - a near physical impossibility - the KEY ST6 H signal will not be generated).
If two or more buttons are pushed simultaneously, the priority encoders ensure that only the button having highest
priority is represented at the encoder outputs. Highest priority is assigned to the 0 number button and to the DISP
function button; the remaining buttons are assigned priorities that correspond to their relative positions in Figure 417 (e.g., button 7 has the lowest priority in the number group; the HLT/SS button has lowest priority in the function
group).
The number buttons have priority over the function buttons. When a number button is pushed, the encoder EO output is high. This output is applied to the E l input of the function encoder and disables it, keeping all outputs high.

4.3.2.2 Register Logic The Register logic is shown in Figure 4-1 9. (Figure 4 - 2 3 relates signals in this paragraph
and in paragraphs 4.3.2.3 and 4.3.2.4). The logic consists of 4-bit shift registers â‚¬ E2, and E3, quad flip-flops E5,
E6, and â ‚ (these flip-flops comprise the switch register), and data selectors E9, â‚¬1 and E l 1. When a console button is pushed, a binary-coded representation appears on the KFUN lines. If the button is one of the number group,
the NUM CLK H signal is generated, loading the signals into RO(1) of each shift register (the E MODE L signal is
high at this time (Figure 4-23); hence, the shift registers are in the parallel load mode, ensuring that the as-yet
unused bit positions are loaded with ground-level signals). Because the button is from the number group, the GATE
ENT L signal is generated periodically and gates the signals through the data selectors to the BUS lines.
If the operator pushes a second number button, the NUM CLK H signal right-shifts the registers; consequently, the
signals representing the first number are shifted to R1 ( I ) , while the signals representing the second number are
shifted into RO(1) (note that the E MODE L signal is low at this time). Data representing four numbers can be entered in the registers and gated to the BUS lines. For example, consider what happens when the operator wishes to
deposit data word 6203(8) in memory. After selecting the memory address, he or she pushes the four octal numbers
consecutively, beginning with 6. When the operator has entered all four numbers, the data is represented on the
BUS lines as shown in Table 4-4. By pushing the DTHIS and DNEXT button, the data is routed through the logic
and deposited in the selected memory location. This action then negates the GATE ENT L signal, removing the data
from the BUS lines after it has been operated on. However, the data is retained in the shift register until the operator pushes another number button.

Table 4-3
C:lock Timing Control Signals
--

Pushbutton

DEC9318 Output

Control Si ial Generated
NUMH
FUN L

KFUNOL

5(STATE)
6(MD)
7
DISP
LSR
LA
LXA
INIT
RUN
ENEXT
ETH IS
DNEXT
DTHIS
HLTISS
BOOT

STHISL

AO, A1, A2, GS
A1, A2, GS
AO, A2, GS
A2, GS
AO, A1, GS
A1, GS
AO, GS
GS
AO, A1, A2, GS
A1, A2, GS
AO, A2, GS
A2, GS
AO, A1, GS
A1, GS
AO, GS
140, GS
GS
GS
A1, GS

E l 8 0 (0) H

KEY F L

K E Y STB H

n
08-1284

Figure 4-18

Timing, Clock Timing Logic

SHLTL

The operator can load the switch register from the shift register at any time by pushing the LSR button. The data is
retained in the switch register unless a power down condition occurs, clearing the register, or until new data is loaded
from the shift register. Data is gated from the switch register to the BUS lines by the GATE SR L signal. This signal is
asserted whenever the operator has selected the switch register contents for display in the DISP readout, or when a
program instruction has directed that the switch register contents be placed on the Omnibus DATA lines (SR DATA L is
asserted).
The operator displays the contents of some source by, first, pushing the appropriate button and, second, pushing the
DISP button. The binary-coded representation of the source is loaded into RO(1) of the shift registers and, thus, appears on the ENTO, ENT1, and ENT2 lines. These lines carry the binary-coded signals to the display control logic and
to the display indicators.

MUM C L K
1-

-DCLK1
3

CLKO
R3Ã‡

R2(l)

. BO
B1
A1

E3
7495
Dl

FO -BUS

F l -BUS

Ell
Rid)

BUS6

-A2
83

BUS9

K FUN 0 L -

RKO)

D O

RO(0)

E7
D3

R3(0)

0 2

R2(0)

K FUN 1 L -

Figure 4- 19

A3
Sl

Table 4-4
Register Logic Bus Line Data
Octal Number

Bus Line

Voltage Level

The Multiplexer logic, shown in Figure 4-20, consists of hex flip-flops E l 2 through
4.3.2.3 Multiplexer Logic
E l 5 and multiplexers E l 7 through E l 9. Data on the BUS lines is clocked into the flip-flops and gated by the multiplexers to the readout circuits via the DISPLAY lines or the ADDR lines. The data on the BUS lines is either the entry, which will be displayed in the DISP readout until disposed of, the contents of some source (the AC register, for
example), which will be displayed in the DISP readout, or the address of the currently-addressed memory location,
which will be displayed in the ADDRS readout.
Entry data is gated from the register logic onto the BUS lines by the GATE ENT L signal. When GATE ENT L is low,
the DSP LTH L pulse clocks the BUS lines data into hex flip-flops E l 3 and E l 5. The flip-flop outputs are applied t o
multiplexer E l 9 and half of multiplexer E18. The multiplexers are controlled by signals MPX A and MPX B, which
are generated by the readout control logic. The readout control logic also generates enabling signals that are applied
to the DISP and ADDRS readout circuits. Each of these enabling signals is applied to a 7-segment LED display. The
enabling signals and the MPX signals are related in such a way that the correct data is displayed in each LED display. The block diagram in Figure 4-21 illustrates the method of gating the BUS lines data to the proper LED display. Figure 4-23 shows the timing of the signals involved in the procedure.
The table in Figure 4-21 relates the enable signals, the MPX signals, and the BUS lines. For example, the readout
control logic asserts enable signal 0 when both MPX A and MPX B are low. Signal 0 is applied to the anode connection of the right-most LED display (the one showing the LSD of the 4-bit octal DISP readout). The MPX signals
gate the multiplexer A inputs to the DISPLAY lines; thus, the data on the BUS 9, BUS 10, and BUS 11 lines is applied to the cathode connection of the LED displays. Only the right-most display indictates a number at this time.
The contents of a register, or some other source, are gated to the DISP readouts in the same way as is entry data. The
address of the currently-addressed memory, however, is clocked into hex flip-flops E 12 and E14 (Figure 4-20) by the
ADR LTH L signal. This address is gated onto the BUS lines from the Omnibus DATA lines by the M A ENA L signal,
which is asserted periodically provided that neither the LA, the LXA, nor the DEP button has been activated. The MPX
signals place the current address on the ADDR lines and the address is displayed in the ADDRS readouts.

BUS 0
BUS 3

.DISPLAY 0 H

BUS 6
BUS-9

DISPLAY 1 H

BUS 1
BUS 4
BUS 7
BUS 10

BUS 2
BUS 5
BUS 8
BUS 11

I
ADR L T H L
MPX B

Figure 4 - 2 0

Multiplexer Logic

4.3.2.4 Register/Multiplexer Gating Logic Timing
The signals that control the Register logic and the Multiplexer logic are produced by the gating logic shown in Figure 4-22; the signals are related by the timing diagram in
Figure 4-23. The lower portion of Figure 4-23 shows timing signals that are generated in the ADDRSIDISP Readout
Circuit logic; these signals are included to illustrate their relationship to the MPX signals.

The timing diagram shows what happens when the operator pushes a number button, the AC button in this example, and then the DISP button. The KFUN signals (not shown) are parallel loaded into the shift register by NUM
CLK H, after which the E MODE L signal goes low to place the register in the right shift mode. GATE ENT L gates
the entry to BUS lines 9, 10, and 11, and the DSP LTH L signal clocks the entry into the flip-flops. MPX A and
MPX B gate the entry to the DISPLAY lines and it is displayed in the right-most position of the DISP readout when
the 0 signal is low.
The MA ENA L signal is asserted periodically. When this signal is low, the address on the Omnibus M A lines is placed on
the console BUS lines. The ADR LTH L signal clocks the address into the flip-flops; the MPX signals gate the address to
the ADDR lines, and it is displayed in the ADDRS readout. Note that M A ENA L is negated whenever the LA, the LXA, or
the DEP button is pushed. Each of these buttons asserts the GATE ENT L signal for as long as the button is held down,
and entry data is placed on the BUS lines for transfer to the Omnibus. Thus, address information must be kept off the
BUS lines during this period.
When the DISP button is pushed at t(1) time, the E MODE L signal is negated by KEY STB H, and GATE ENT L
remains high. The entry is gated to the DISP key logic on the ENT lines and loaded into flip-flops there. This action
causes the AC indicator to light and asserts three signals - BUS EN L, IND1 L, and IND2 L - that transfer the contents of the AC register to the BUS lines. The DSP LTH L signal clocks the AC register data into the flip-flops, the
MPX signals place the data on the DISPLAY lines, and the data is displayed in the DISP readout. As before, the address on the M A lines is displayed in the ADDRS readout (the address remains unchanged throughout the timing
illustrated).

0
1
2

I I

1-1

1-1
1-1

READOUT
CONTROL
LOGIC -

1
1
1

1-1

1-1
1-1

?-SEGMENT
SIGNALS

BUS 0 - DO
BUS 3 - B 0
FOBUS 6- CO
BUS 9 - A 0
E l9
BUS 1
Dl
BUS 4
B1
BUS 7
C1
c,
BUS10- A1

BCD-70-7
SEGMENT
DECODER
DISPLAY 0 H

DISPLAY 1 H

BUS2-DO
BUS 5
B0
BUS 8
CO
BUS11 - A 0

F0-

B
0

ENABLE
0
1

DISPLAY X H
A
C

MPX A
MPX B

Figure 4-21

M PWEnable Signal Relationship

BUS LINE DISPLAYED
9, 10, 11
6,7, 8

NUM CLK H

( S E E FIGURE 4 - 2 7 )
SR-DATA

GATE SR L

BPOK H

PWR OK H

KEY STB H

E MODE L

E
MODE

u
u

NUM H
M CLOCK L

GATE ENT
ADR LTH L

8RUN L

DSP LTH L
BTS1 L

Ã‘L>-C>
MPX A

Figure 4-22

SEE FIGURE 4 - 2 6

MA ENA L

M CLOCK L

NUM H

KEY F L

KEY STB H

E MODE L

NUM CLK H

GATE ENT L

DSP LTH L

ADR LTH L

M A 0 (1) H

FUN L

MA ENA L

BUS EN L

IND1 L

IND 2 L

MPX A

MPX B

â‚¬25-R3(

â ‚ ¬ 2 FO

â ‚ ¬ 2 F1

â‚¬2

â‚¬22-

E 2 2 -F4
NOTE:
RUN L NOT ASSERTED,

Figure 4-23

4.3.2.5 ADDRS/DISP Readout Circuit Logic - The logic shown in Figure 4 - 2 4 consists largely of 7-segment
LED displays. The DISP information is displayed on components E3, E4, E5, and E7; ADDRS information on components â‚¬ E l 1, E l 2, E l 4; and extended memory information on component â‚ 5.
The relationship between the MPX signals and the display enable signals (0, 1, 2, 3, and 4) has been discussed and
is not repeated here (refer to Paragraphs 4.3.2.2 and 4.3.2.3). When an enable signal is generated, the corresponding transistor is turned on, supplying anode current to one or more of the LED displays. For example, if 0 goes low,
Q2 conducts, providing anode current for LED displays E3 and E9. Either E8 or E13, each a decoder/driver, provides
high sink-current outputs that are applied to the LED cathodes. Thus, the octal information carried on the DISPLAY
lines or the ADDR lines is displayed by the correct component.

Table 4 - 5 relates the displayable octal digits to the input/output signal levels of the DEC7447A decoder/drivers,
while Figure 4-25 shows how the octal digits are derived in the 7-segment displays. When the digit 2 is to be displayed in one of the ADDRS LED displays, for example, output pins a, b, d, e, and g of E l 3 go low. The LED segments with the corresponding designations are activated and the digit appears in t h e readout.

Table 4-5
DEC7447A InputIOutput Signals
Octal Number

Input Pins

Figure 4-25

Output Pins

OCTAL Designations - Resultant Displays

4.3.2.6 Function Button Logic Figure 4-26 shows the Function Button logic. The latch, E26, the BCD-to-decima1 decoder, E29, and the gating logic, including hex buffers E28 and E31, are illustrated.
When a button is pushed, the binary code is clocked into the latch by the KEY F L signal. The latch output is decoded by E29 to produce an output signal that corresponds to the selected button (the 8251 function table in Figure
4-26 relates the decoder outputs to the function buttons). Note that the input at D3 of the decoder must be low.
This requirement can be met in one of t w o ways: First, if the CPU is not running and the PANEL LOCK switch is in
the off position, any function button will enable NAND gate E25B; second, if the CPU is running, the DISP button or
the LSR button will enable NAND gate E25A. The second method ensures that the operator cannot inadvertently disrupt the CPU when it is in automatic operation (as will be seen, neither the DISP button nor the LSR button disrupts
operation).
The decoder output signal is applied to gating logic that generates the necessary control signals (the gating logic for
the DISP button is shown in a separate illustration, Figure 4-25). Table 4 - 6 lists the control signals generated by
each function button and gives a summary of the result achieved. Refer to Paragraph 4.6.4 for a discussion of the
CPU gating during console operations.

KEY STB H

^>-^

DISP

P
(O
UR
LS
2E
1 LA H

KFUN 0
KFUN 1
K FUN 2
BRUN L

INITIALIZE
(CR 1 )

LAD.

R3(1)
MEM START L
(AJ2)

^_^

l3
KEY C N T L L

KEY F L-

K E Y CONTROL L
(DU2)

MS. I R DIS L

MS. IR DISABLE L

DIS2

PAN LOCK

I DO I D l 1 D2 1 D3 I OUTPUT
1 LO I LO I LO I LO 1
FO

BUTTON
DISP

BUFFER

LXA

INIT

LA ENAB L
I

---.

DIS4
LO

1 DIS2 1 INPUT 1 OUTPUT
I

BREAK DATA
CONT L ( B K 2 )

GATE E N T L

Figure 4-26

Function Button Logic

LA ENABLE L
(EM21

Table 4-6
Function Button Control Signals
Function Button

Control Signal Generated

Signal Function

LSR

LD SR H

Load entry into Switch Register.

MS. IR DIS L

Asserts the Omnibus MS, IR DISABLE L signal, placing the
CPU in the DMA state and, thus, permits the console to
communicate directly with memory (refer to Paragraph
4.6.4, Data Break Transfers).

GATE ENT L

Gates the entry from the number shift register to the console BUS lines.

LA ENAB L

Causes the Programmer's Console control to generate the
KCCN1 SR ENABLE L signal, thereby gating the entry
from the BUS lines to the Omnibus DATA lines.
Generates the IND1 L signal ensuring that only the entry is
placed on the DATA Bus. INDI L and IND2 L determine
the type of information placed on the DATA bus during
TS1. The information can be any of the following:

LXA

INDI L

IND2 L

DATA Bus Information

Status word (see Table 4-15 for the
Status word description)

MQ register contents

Logic 0 (HI)

AC register contents

PULSE LOAD ADD 1-

After the entry has been gated from the DATA bus to the
CPMA register, PULSE LA H causes the CPMA LOAD signal
to be generated, loading the entry into the register. Note
that buffer E31 generates PULSE LOAD ADD L when KEY
STB H is asserted, which is quite some time after the entry
has been placed on the DATA bus (the top four outputs of
E31 are controlled by the enable input a t DIS4, while the
bottom 2 outputs are controlled via DIS2).

MS. IR DIS L
GATE ENT L
LA ENAB L
IN1 L

See entry for LA.

KEY CNTL L

Causesthe Omnibus KEY CONTROL L signal to be asserted. This signal and LA ENABLE L combine to gate the
entry from the DATA bus to the IF and DF registers of the
extended memory option.

Table 4-6 (Cont)
Function Button Control Signals
-

Function Button

Control Signal Generated

Signal Function

PULSE LOAD ADD L

Causes the extended memory control (M8317) to generate
a clock pulse that loads the entry into the IF and DF
register.
Asserts the Omnibus INITIALIZE L signal, causing the AC,
the Link, the interrupt system, and peripheral flags to be
cleared.

RUN

MEM ST L

Asserts the Omnibus MEM START L signal, causing the
CPU timing generator (TG) to start generating timing
signals.

ETHIS

MEM ST L

See 'RUN'.

MS. IR DIS L

See 'LA'.

KEY CNTL L
BK DATA CNTL L

These two signals assert Omnibus signals KEY CONTROL L
and BREAK DATA CONT L, respectively; these Omnibus
signals, along with LA ENABLE L, control CPU major register gating operations in the DMA state.
When BREAK DATA CONT L and KEY CONTROL L are
low and LA ENABLE L is high, the following sequence of
events occurs: During TS1 the contents of the CPMA register are incremented and loaded into the PC register; during
TS2 the contents of the addressed memory location are
placed on the MD lines and loaded into the MB register;
during TS3 the Omnibus STOP L signal i s generated causing
the TG RUN flip-flop to be cleared a t TP3 time (the TG
halts in TSI, after TS4 operations have been completed see 'THIS L' for a description of TS4 operations).
The operator can cause the data contained in the MB register to be displayed in the DISPLAY readout by pushing the
MD button and then the D ISP button. Alternatively, the
operator can push the console buttons in the following
order to examine a memory location: LA; MD; DISP;
ETH IS.

THIS L
(Generated by clock
timing logic)

Asserts the Omnibus MA, MS LOAD CONT L signal, preventing TP4 from loading the CPMA register. Thus, the addressed memory location remains unchanged and the
operator can modify the data by using the deposit function.

Table 4-6 (Cont)
Function Button Control Signals
Function Button

This pushbutton generates the same signals as does ETHIS,
except for THIS L. Hence, the CPMA register is loaded at
TP4 time and a new address is placed on the MA lines during
TS1 of the next timing cycle. The operator can use this
button to examine consecutive memory locations. The
following order is most advantageous: MA; MD; D ISP;
ENEXT; ENEXT.. .; ENEXT.

ENEXT

DTH IS

Signal Function

Control Signal Generated

MEM ST L

See 'RUN'.

MS. IR DIS L

See 'LA'.

GATE ENT L

Gates the entry from the number shift register to the console BUS lines.

DEP L

Asserts the console KCCN1 SR ENABLE L signal, which
gates the entry from the BUS lines to the Omnibus DATA
lines; the entry i s placed on the CPU SUM lines and loaded
into the MB register at TP2 time. During the write half of
the timing cycle the entry is written into the addressed
memory location.

KEY CNTL L

When LA ENAB L and BK DATA CNTL L are high and
KEY CNTL L is low, the following sequence of events
occurs in the CPU major register gating: During TS1 the
contents of the CPMA register are incremented and loaded
into the PC register; during TS2 the DATA lines are gated
to the CPU SUM lines; during TS3 the STOP L signal is
generated, causing the RUN flip-flop to be cleared at TP3
time (the TG halts in TS1, after TS4 operations have been
completed - see THIS L'for a description of TS4 operations).

THIS L
(Generated by clock
timing logic)

Asserts MA, MS LOAD CONT L, preventing TP4 from
loading the CPMA register. Thus, the addressed memory
location remains unchanged.
This button generates the same signals as does DTHIS, except for THIS L. Thus, DNEXT can be used to deposit data
in consecutive memory locations.

DNEXT

4.3.2.7 DISP Button Logic
Figure 4-27 shows the logic associated with the DISP button. This button is used
when the operator wishes to display the contents of a register (AC, MQ, or SR), or the information carried by a bus
(DATA, MD), or STATE information. The pushbutton has two functions: It causes the appropriate console indicator to
light, signifying the source of the information being displayed; and it generates the control signals that gate the appropriate data to the display readout on the console.

STATE

STATUS BUS

GATE SR L

74 174

ENT 0 H

D 5

R5(1 1 .

ENT1 H

RI(1)

ENT 2 H

RO(1)

DISP 0 H

D2
+

DISP 2 H
DISP I N H H
EMODE L 1

BPOK H

EMODE

I I-

8251
E35

~ ~ D Ã ‘ Ã4

1 4

f50

0 12

f60

0 6

DO
D3

ADR LTH L
X = DON'T CARE

DSP L T H L

Figure 4-27

DISP Button Logic

MD L

f 2 oLA
LXA
f3 0

BRUN L

BUS EN L
STATE L

8097
E34

0 2

MCLOCK L

13 0
11 0

IN1 L 1

IND2 L

Whenever a number button is pushed, the binary code for that button is entered in the number shift register; the
code is carried on the ENTO H, ENT1 H, and ENT2 H lines to the DEC74174 hex flip-flop (E36 in Figure 4-27).
When the operator pushes the DISP button, decoder E29 generates the DISP signal that enables KEY STB H to load
the binary code into E36. Hence, the code appears on the DISPO H, DISP1 H, and DISP2 H lines.
A DEC74145 decoder, E17, monitors the DISP lines and causes an appropriate indicator to light. The function table
in Figure 4-27 indicates the relationship between the DISP lines and the source indicators (note that the EMODE
flip-flop must be in the clear state for an indicator to be lighted; this flip-flop ensures that a lighted indicator is
turned off when the next number button is pushed).
A DEC8251 decoder, E35, and a hex buffer, ECM, also monitor the DISP lines; these two components generate the
signals that cause the information to be gated to the DISPLAY readout. Table 4-7 relates the number buttons, the DISPO
H, DISP1 H, DISP2 H signals, and the control signals generated by E34 and E35. The top four entries (buttons 0 through
3) indicate that BUS EN L is asserted, along with some combination of IND1 Land IND2 L. BUS EN Lcauses information
on the Omnibus DATA lines to be gated to the console BUS lines (Paragraph 4.3.2.9), while the IND signals select the
type of information that is placed on the DATA lines by the CPU major register gating (refer to the LA entry in Table 4-6,
which relates IND signals and DATA bus information). The last three entries also indicate some combination of the IND
signals being generated; however, the signals fall into the "don't care" category in these situations. The M D L and STATE
L signals gate information from the MD bus and from selected Omnibus lines, respectively, onto the console BUS lines,
while the GATE SR L signal gates the console switch register contents to the BUS lines. The information on the BUS
lines is clocked into flip-flops in the multiplexer logic by the DSP LTH L signal (Figure 4-20) and displayed in the
DISPLAY readout.

Table 4-7
Display Control Signals
Button

DISPO H

D8SP1 H

DISP2 H

Control Signal(s1

0(AC)
1(MQ)
2(BUS)
3(STATUS)
46R)
5(STATE)
6(MD)

LO
LO
LO
LO
HI
HI
HI

LO
LO
HI
HI
LO
LO
HI

LO
HI
LO
HI
LO
HI
LO

BUS EN L, IND1 L, IND2L
BUS EN L, IND2L
BUS EN L, I N D I L
BUS EN L
GATE SR L, IND1 L, IND2L
STATE L, IND2L
MD L, I N D I L

When a source has been selected for display, the source identity is loaded into the hex flip-flop E36. Hence, the
DISP lines reflect this identity until another source is selected for display. In some circumstances, the control signals
generated by E34 and E35 could impair operation, consequently, some means must be provided to prevent the signals from being generated in such circumstances. These means are provided by NAND gate E30, which, when inhibited, disables E34 and E35. The contents of a source are displayed during alternate periods of the MCLOCK L signal
(when the CPU is not running) or during TS1 of alternate timing cycles. The display information timeshares the BUS
lines with current address information that is displayed in the ADDR readout. This timesharing is accomplished by
the M A 0 flip-flop, which alternately enables and disables NOR gate E22; thus, E34 and E35 are disabled during the
time that the address information is being routed to the ADDR readout.
NOR gate E22 also inhibits E30 when the EMODE flip-flop is set. As noted earlier, a lighted indicator is turned off
by this flip-flop when a number button is pushed. More importantly, the control signals are negated so that the entry
can be viewed in the DISPLAY readout as it is being entered via the number buttons.

Another situation that requires E34 and E35 to be disabled arises when either the LA or the LXA pushbutton is activated.
In such a situation an address is placed on the BUS lines and gated to the Omnibus DATA lines; consequently, display
information must be kept off the DATA lines during the time that these functions are active. This is accomplished by NOR
gate E32, which inhibits NAND gate E30 when the LA or LXA signal is generated by decoder E29.

4.3.2.8 THIS, HLT, BOOT Logic - The logic shown in Figure 4-28 has several functions. Consider the HLT/SS
pushbutton. If the CPU is running when the operator pushes this button, the Omnibus STOP L signal is asserted and the
RUN flip-flop is cleared at TP3 time (Figure 4-3); the CPU stops in TS1. If the CPU is stopped when the button is pushed,
not only is the STOP L signal asserted, but also the MEM ST L signal (Figure 4-28); hence, the CPU executes one timing
cycle before stopping in TS1. Note that the PANEL LOCK L signal must be negated for the DEC8097 hex buffer to
operate. Thus, the CPU cannot be halted when the PANEL LOCK switch on the Limited Function Panel is in the up
position. Furthermore, as Figure 4 - 2 6 shows, if the PANEL LOCK switch is on when the CPU is stopped, the processor
cannot be started.

SHLT L

H LT/SS

KEY STB H
MUM H

13 9

0 14

SING STEP L

{-t>tsTop
L ( DSZ 1

BPOK
H
0 10

0
0-

8097
E2 8

9 3

B F

11 3

BOOTF
FUN L

1 4 12
*

-^1- 1

D1S4

MA,MS LOAD
CONT L ( B H 2 )

D1S2
I

BTS1 L

Figure 4-28

THIS, H LT, BOOT Logic

Both the ETHIS and the DTHIS pushbuttons start a timing cycle. The single cycle that is executed differs from that
executed by the ENEXT/DNEXT functions in one way, i.e., the memory address is not updated when the THIS functions are used. The THIS flip-flop, which is clocked at the end of TS1, is cleared when either of the THIS buttons is
pushed; thus, the MA,MS LOAD CONT L signal is asserted, preventing the CPMA LOAD signal from being generated at TP4 time of the timing cycle.
The dc set input of the THIS flip-flop is connected as shown to prevent improper operation should the ETHIS or
DTHIS button be pushed by mistake while the CPU is running. The dc set line is held low when the RUN L signal is
asserted, preventing the flip-flop from being cleared by the BTSl L signal should STHIS L be inadvertently
generated.
The BOOT pushbutton enables the operator to load bootstrap programs. A low-to-high transition of the Omnibus SW L
signal causes the bootstrap option control (M8317) to initiate a bootstrap operation, provided the CPU is not running. To
bring about this transition of the SW L signal, the operator must push the BOOT button twice. The first push causes
NAND gate E21 to set the BOOTF flip-flop (the KEY STB H pulse is generated when BOOT is pushed, but neither NUM H
nor FUN L is asserted); the second push causes the flip-flop to be cleared. Thus, the SW L signal first goes low and then
goes high, initiating the bootstrap operation.

Console Control Logic - The Console Control logic is part of the I/O Option board (M8316) that plugs into the
PDP-8/A Omnibus. Data is transferred between the Omnibus and the console logic via the Console Control logic. The
complete logic drawings for the console control are included in Appendix H of this manual. Figures 4-29 and 4-30 show
portions of that logic t o illustrate how data is handled by the control.

4.3.2.9

MDO L - 0

FL-0

MD1 L - 0

DL*

MD2 L Ã ‘

EL-

MD3 L
I R 0 L*

8234
~5

A0
B@

-B U S 0

- BUS 1

-BUS 2

-BUS3

s0
T

STATE L
KCCN1 STATE ENA L
KCCN1 SR
ENABLE L
KCCN1 MD ENA L

Figure 4-29 Console Control Logic - STATE, M D

Figure 4 - 2 9 shows how STATE data and data carried by the M D lines are placed on the console BUS lines. The
DEC 8 2 3 4 multiplexers are controlled by the t w o enable signals, KCCN1 M D ENA L and KCCN1 STATE ENA L.
When the operator pushes the appropriate console button - M D or STATE - and then pushes the DISP button, either M D L or STATE L is asserted by the DISP button logic. If the CPU is in TS1 and KCCN1 SR ENABLE L is negated, the applicable data is gated onto the BUS lines.
Logic that performs a function similar to that of Figure 4-29 is shown at the top of Figure 4-30. Multiplexer E l
places either M A bus information or DATA bus information on the BUS lines. Only the multiplexer that accommodates bits 0 through 3 is shown; bits 4 through 1 1 are handled in like manner. Remember that M A bus data is
displayed during alternate periods of the MCLOCK L signal when the CPU is halted, or during TS1 of alternate timing cycles when the CPU is running. The information on the DATA bus can be displayed during those alternate periods when M A bus data is not displayed. If the operator wants t o view the contents of the M Q register, for example,
he or she pushes number button 1 and then the DISP button. The BUS EN L signal is asserted, the M Q contents
are placed on the BUS lines and displayed in the DISPLAY readouts.
The foregoing operation, as well as those carried out by the logic in Figure 4-29, depends on the KCCN1 SR ENABLE L signal being negated. The logic that generates KCCN1 SR ENABLE L is shown at the bottom of Figure 4 30. This signal gates Bus-lines information onto the DATA bus in three situations: When either the LA or the LXA
pushbutton is activated, generating LA ENAB L and causing the entry to be loaded into the CPMA register; when
either the DTHIS or the DNEXT pushbutton is activated, generating DEP L during TS2 and causing the entry to be
loaded into the MB register; or, when either an LAS (7604) or an OSR (7404) operate instruction is programmed,
generating SR DATA L during TS3 and causing the result of the specified operation to be loaded into the AC
register.

-1

DATA 0 L
MA 1 L

BUS

BUS 1

DATA 1 L
{r
MA 2 L
DATA 2 L

BUS 2

DATA 3 L
KCCN1 M A E N A L
BBUF T S 1 H
KCCN1 S R E N A B L E L

BUS E N L

-^y
Ã‘Ã

'^-OB2
BUS 2

DATA 1 L

DATA 2 L

DATA 3 L

.iÃ‘BO

BBUF T S 2

0 A0

BUS 3

DATA 0 L

8235

OA1
'Ã‘

DEP L

0 A2

BUS 1

L A ENAB L
KCCN1 SR
ENABLE L

H-W-

BBUF TS3 H

r-'
SR Ã‘ DATA L

INTERLOCK L
U S E R MODE L
MDO L

MD9l l L
M

a
Figure 4-30

Console Control Logic-MA, DATA, SR ENABLE

4.4 INSTRUCTION DECODER
Logic within the ID, monitors the M D lines, decoding the information thereon and generating major register gating
control signals. The gating control signals are developed largely in response to basic instructions, CPU major states,
and time states and time pulses. In addition, Programmer's Console operations and I/O transfers can control major
register gating to some extent.
The ID logic (Figure 4-16) includes the Instruction Register, the Major State Register, the AC Register gating, and a
number of Read-only Memories (ROMs). The ROMs play a most important part in the CPU operation. Major register
gating responds, basically, to program instructions or as a result of directions entered manually at the Programmer's
Console. Program instructions include memory reference instructions, operate instructions, and IOT instructions; each

of these types of instructions can be subdivided further. Furthermore, each instruction behaves differently depending
on the particular major state and time state. Consequently, major register gating control signals must be generated
under a variety of circumstances. A most convenient method of accommodating such an abundance of variables is to
devote a ROM to a significant set of circumstances. Thus, we have ROM D dedicated to operate microinstructions
during TS3, ROM J responding to Processor-IOT instructions during TS4, ROM F decoding skip and link instructions
during TS3, and so on.
The ROMs are illustrated in Figures 4-31 through 4-38 as they appear in the logic diagrams. All except ROM F (a
1024-bit ROM) are 256-bit ROM organized as 3 2 8-bit words selected by a 5-bit input code. Pins 1 0 through 1 4
are the input pins, pin 1 4 representing the most significant bit of the input code. Pins 1 through 7 and 9 are the output pins, while pin 15 is an enable input (a low voltage applied to this pin enables the ROM to function). For ROM F
the input pins are 1 through 7 and 15 ( 15 is most significant), the output pins are 9 through 12 (10 and 12 are not
used), and the enable pins are 13 and 14.

L A ENABLE L

SEL c L

SEL B L
SEL A L

KEY CONTROL L Â¥^3

CARRY EN L

BREAK DATA CONT L Â¥12

F 6 0Ã PC EN L

D3
F 5 0 Ã ‘ M EN L
D2
01

DATA CMP L
DATA ENA L

7442
DCDR
E71

F4 Â¡Ã‘

EN L

F30Ã‘PAGEEN
F 2 0Ã AND EN L

F1 0Ã IS2 S K I P TST L

EL
DL
FL
7442

Figure 4-31

1NT I N
ROG L
SET L
DL
FL

ROM A Logic

PC EN L
MA EN L
MD E N L

MSo
1

ADDRESS
UPDATE

PAGE EN L
AND EN L
I S 2 SKP TST L

TS4 L
NOTE :
For 7 4 4 2 function table see ROM A .

Figure 4-32

ROM B Logic

-9

IRO L

IRl L

E L

SEE ROM A
FOR 7 4 4 2 DCDR

S E L A L
5
+CARRY
EN L

E7 0
INSTR

F L
Tl

ROM
IR2L

+SEL
- s7E L

4
-AC

LD EN L

&PC

LD EN L

DATA CMP L
1
Â¥DAT

ENA L

MDO

Figure 4-33

ROM C Logic

MQ CLR E N L

MQ L D E N L
MQ

BUS L

AC L D E N L
AC-

BUS L

DATA CMP L
DATA E N A L

Figure 4-34

ROM D Logic

A H

SELC L (SEE ROM A FOR 7442 DCDR)

GTF H

AC-Ã

Figure 4-35

BUS L

ROM E Logic

ADLK L
(ZERO L )

Figure 4-36

ROM

ROM F Logic

OP2tOP3L
IR1 L

I O T XFER L

IR2 L
MD3 L

â‚¬
OPR/IOT/
MAJOR STATE
ENABLE

STATUS L

4
I N T ON L
SRQ H

MD9 L

PROCESSOR

E SET L
D SET L

Figure 4-37

ROM H Logic

SKON H

MD10 L

GTF H

MD11 L

RTF H
CAP H

Figure 4-38

ROM J Logic

Note that most of the ROM input signals are taken from the M D lines, the Instruction Register (IR lines), and the
Major State Register. For the moment it is enough to be aware of the logic shown in Figures 4-31 through 4-38. In
Paragraph 4.5, tables are provided that enable one to determine easily the input/output relationship for each ROM
and to relate the ROM outputs to the major registers and gating. ROMs H and J are used for other than major register gating purposes and are discussed in Paragraphs 4.4.2 and 4.6, respectively.
In addition to the logic already mentioned, the ID includes logic that supplements the ROMs for special purposes.
This logic is discussed in paragraphs following the Instruction Register and Major State Register descriptions.
4.4.1 Instruction Register Logic
The Instruction Register logic is shown in Figure 4-39. Operations in each CPU Major State are determined by the
type of instruction contained in the addressed memory location. This instruction is placed on the MD lines during
TS2 of a Fetch cycle. M D bits 0, 1, and 2, which identify the basic instruction, are applied to the B inputs of the
DEC74157 multiplexer. During TS2, these input signals are gated to the multiplexer outputs and applied to the data
inputs of the quad flip-flop. Because the CPU is in the Fetch state, both enabling inputs of the quad flip-flop are low,
and at TP2 time the individual flip-flops are clocked. The flip-flop outputs, which represent the basic instruction (see
the IR Table), are distributed throughout the CPU logic on the IR lines.

r0
A0

MDO L

0 BO

INT I N
PROG H

0 A1

F L

0 B1

+3 V

MD1 L

L
-

040

FO 0
Fl

MUX 7 4 1 5 7
E51
F2 0

a 3Q

F3 0

0 20

0 82

AC ZERO L

4A3
MD2 L

QUAD F F 8 T 1 0
E5 0
DATA
ENA

IR,
FLAG

40 0 Ã ‘ Ã ‘ I

3 0 0Ã‘Ã‘I

-rR2

10 e

0 10

MS, I R E N L

0 83
STB

8T10

1 NQ 1 DATA 1 OUT 1
IN
LO
-H I

ENA
LO
LO
HI
X

NQ
CONT
OUT
LO
LO
HI
LO
LO N O C H A N G E
HI
HI-Z

IR TABLE

08-1305

Figure 4-39

Instruction Registers Logic

During TS4, the signals on the A inputs of the rnultiplexer are gated t o the flip-flop inputs. Providing an interrupt has
not been honored, the flip-flop is placed in a "no change" state; thus, the flip-flop outputs remain unchanged at TP4
time. However, if the INT IN PROG H signal had been asserted at TP3 time, the flip-flop's contents are changed at
TP4 time. The IR lines then represent the J M S instruction and, because the Major State register logic asserted the E
L signal at the same TP4 time, the CPU enters the Execute state and performs the J M S operations. An interrupt can
be honored during any major state timing cycle, as long as the cycle is the last one of the instruction; therefore, the
IR lines can be changed at TP4 of any state, as the logic demonstrates.
The MS, IR EN L signal can be negated at TP4 time by a data break peripheral or by the Programmer's Console. The
flip-flop outputs are removed from the IR lines and the CPU enters the DMA state.
When MS, IR EN L is asserted again, the IR lines assume the states that existed before the DMA interruption and
the interrupted instruction operations are resumed. If the MS, IR EN L signal is negated at the same time that the IR
flip-flops are clocked to the J M S state (as a result of INT IN PROG H being asserted), the CPU enters the DMA
state. On completion of the DMA operations, the CPU enters the Executive state and performs the J M S operation.

4.4.2 Major State Register Logic
The CPU operations are grouped functionally into the four major states - Fetch, Defer, Execute, and DMA. The first
three are entered actively when flip-flops in the Major State Register logic are set (only one major state flip-flop may
be active at any given time). The fourth state, DMA, results when none of the first three has been entered.
The logic is shown in Figure 4 - 4 0 and includes ROM H. Table 4 - 8 relates the input and output signals of ROM H,
the basic instruction involved, and the present and next CPU Major State. For example, input code 22(8) occurs during the Fetch cycle of a DCA instruction, resulting in the E SET L signal being asserted by the ROM. Note that the
INPUT SIGNAL LOW column indicates the signals that must be low to achieve the desired input code (this convention is chosen because most of the Omnibus signals are active when low). Three stages o f the 8T10 quad flip-flop
are used t o generate the F L, D L, and E L signals. The quad flip-flop is enabled by the MS, IR EN L signal; when
this signal is negated (MS, IR DISABLE L has been asserted by a peripheral or by the Programmer's Console) the
flip-flop outputs are removed from the output lines and the DMA L signal is asserted.
The flip-flops are clocked by the CPMA LOAD signal, which is generated during automatic operation at TP4 time
and during manual operation when the LA button is pushed. Some type of manual operation always precedes automatic operation; for example, to initiate automatic operation of a stored program, the operator must load the CPMA
register with the starting address of the program. He loads this address by pushing the console LA button, causing
the Programmer's Console logic t o assert first, the MS, IR DISABLE L signal and, second, the PULSE LA H signal.
MS, IR DISABLE L causes the DMA L signal to be asserted. This action results in ROM H being disabled; consequently, both the D SET L signal and the E SET L signal are negated, and IF SET L in the Major State register
logic is asserted. Because o f gating differences in the Programmer's Console logic, MR, IR DISABLE L is asserted
much earlier than PULSE LA H. Thus, IF SET L is low when CPMA LOAD goes high, and the Fetch stage of the
quad flip-flop is set, asserting the F L signal. If the operator now pushes the RUN button, the CPU begins automatic
operation in the Fetch state of the addressed instruction.
Since all instructions begin in the Fetch state, this state is entered from any state that completes an instruction.
Thus, Fetch can be entered from the Execute state of a 2 - or 3-cycle instruction; Fetch can be entered from the Defer state of a 2-cycle instruction; Fetch can be entered from the Fetch state of a one-cycle instruction; finally, Fetch
can be entered from the DMA state. When the Fetch state of a multi-cycle instruction has been completed, either a
Defer state or an Execute state follows, unless the operator pushes the HLT/SS button or a data break device
causes suspension of program control. Either event can cause a halt or interruption when the Fetch state is completed; then the DMA state is entered. When operations in this state have been carried out, control is returned to
the program, and the multi-cycle instruction can be completed.
ROM H provides the outputs that control the Major State Register flip-flops; Table 4 - 8 relates these outputs t o the
input select codes. The table shows those circumstances in which either the D SET L signal or the E SET L signal is
asserted. When neither of these signals is low, IF SET L is asserted. For example, ROM H is disabled during the Execute state; consequently, IF SET L is asserted during all Execute cycles.

A A A
a

A A
CJ

Ã‡

Table 4-8
ROM H InputfOutput Signals
(ROM is enabled for Fetch or Defer Major State)
Input
Code

IRO L

Signal
IR2 L

ROM
Output Signal

Basic Instruction Programmed
-

x
x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x

OP2 + OP3 L
OP1 L
IOT XFER L
10T XFER L
D SET L

D SET L

x
x
x
x

E SET L
E SET L
E SET L
D SET L
E SET L
E SET L
E SET L
D SET L
E SET L
E SET L
E SET L
D SET L
E SET L
E SET L
E SET L
D SET L
E SET L
E SET L
E SET L

Present Major StatefNext Major State

OPERATE
OPERATE
I OT
I OT
JMP
JMP
JMP
JMP
JMS
JMS
JMS
JMS
DCA
DCA
DCA
DCA
I sz

IS2
Isz
IS2
TAD
TAD
TAD
TAD
AND
AND
AND
AND

Fetch/Fetch ( I F SET L is low)
Fetch/Fetch (IF SET L is low)
FetchIFetch (I F SET L is low)
FetchIFetch (IF SET L is low)
Fetch/Defer
DeferIFetch (IF SET L is low)
Fetch/Fetch (I F SET L is low)
Defer/Fetch (IF SET L is low)
Fetch/Defer
DeferIExecute
FetchIExecute
DeferIExecute
Fetch/Defer
DeferfExecute
FetchIExecute
DeferfExecute
FetchIDefer
Defer/Execute
Fetch/Execute
Defer/Execute
Fetch/Defer
Defer/Execute
Fetch/Execute
Defer/Execute
Fetch/Execute
DeferIExecute
Fetch/Execute
Defer/Execute

Consider the table entry for input code 21(8), for example. This combination of input signals is obtained when the
CPU is in the Defer state of an indirectly-addressed DCA instruction. DCA is normally a 2-cycle instruction, but indirect addressing means that the Defer state must be completed before the instruction is executed. Thus, the E SET
L signal is asserted during the Defer cycle, and the E L signal is generated at TP4 time.
Note that the INT IN PROG H signal asserts E SET L. INT IN PROG H is asserted when an interrupt request is honored by the interrupt logic of the timing generator module. A t TP4 time the Execute state is entered; E SET L can be
asserted in this manner during either a Fetch, a Defer, or an Execute state, provided the particular state is the final
state of an instruction.
As shown earlier, Fetch can be entered from the DMA state. If MS, IR DISABLE L is asserted because manual operations are being performed, Fetch always follows DMA. However, if MS, 1R DISABLE L has been asserted by a data
break peripheral, the Fetch state may or may not follow the DMA state. A data break operation can begin at the end
of any Major State. Program control is halted for one timing cycle (control can be halted for three cycles, as well; for
convenience, a halt of one cycle is considered). When the Data transfer has been completed, program control is reestablished and the previously interrupted operation continues. An example of the interrupting process is given in the
following paragraph.
If operations are being carried out in the Fetch state of a 2-cycle DCA instruction, the E SET L signal is asserted. If
a peripheral initiates a data break during this Fetch state, MS, IR DISABLE L is asserted at TP4 time. A t the same
time, CPMA LOAD is produced by TP4 and MA, M S LOAD CONT L, and Execute flip-flop is set; however, MS, IR
DISABLE L removes the flip-flop outputs from the output lines and the DMA state is entered, instead of the Execute
state. It could be assumed that the next TP4 pulse (of the DMA state) would set the Fetch flip-flop; however, at
TP1 of the DMA state the peripheral asserts MA, M S LOAD CONT L, thereby preventing the TP4 pulse in question
from setting the flip-flop. Instead, this TP4 negates MS, IR DISABLE L. The Execute flip-flop is still set and, thus, E
L is asserted. Operations begin in the Execute state of the interrupted instruction. At TP1 of this state, MA, M S
LOAD CONT L is negated, completing the return t o uninterrupted operation.

4.4.3 D A T A ENA/DATA CMP Logic
Figure 4-41 shows supplementary logic that generates the DATA ENA L and/or the DATA CMP L signals. These signals are used in major register gating t o select the information on the DATA lines or the complement of that information for application t o the adders; alternatively, a logic 0 may be gated t o the adders. Table 4-9 relates the state of
the t w o signals t o the type of data gated t o the adders,

TO ROM A.C. D,E

TS2 L Ã ‘
DATA CMP L

F L-0

TO R O M A,C,D.E

08-1307
Figure 4-41

Data ENA/Data CMP Logic

As Figure 4-41 shows, ROMs A, C, D, and E can control the t w o signals, and do in all but one instance, i.e., during
TS2 of a Fetch cycle. In this instance the t w o signals cause the AC contents t o be gated t o the adder and placed on
the major register gating SUM lines (AC->BUS L is asserted by the logic shown in Figure 4-44). If an SZA instruction has been issued, the AC contents will be tested by the Skip logic (Paragraph 4.5.3).

Table 4-9
D A T A E N A I D A T A CMP Gating
Signal
D A T A ENA L

-4

Data Transferred t o Adder

D A T A CMP L

H I (Logic 0)
H I (Logic 0)
Complement of information on DATA lines
Information on DATA lines

4.4.4 Address Update Logic
Figure 4-42 shows supplementary logic that generates PC LD EN L, CARRY EN L, and SEL B L. All three signals
are used to implement the M A i - 1 >PC operation that takes place during TS1 of each Fetch cyle and during TS1 of
selected DMA cycles.

SEL B L
(MA EN L )
NOTE:
TO LOW= TSI or T S 4
T I LOWSTSI or T S 2

Figure 4-42

Address Update Logic

During TS1 the SEL B L and CARRY EN L signals are asserted, assuming LA ENABLE L is high. SEL B L causes
decoder E71 (Figure 4-31) to assert the M A EN L signal, gating the CPMA address to one input of the adders
(DATA CMP L and DATA ENA L provide a logic 0 at the other adder input). CARRY EN L enables the Carry In logic
to add 1 to the address. If the CPU is in a Fetch cyle, PC LD EN L is asserted by NAND gate E55, enabling the PC,
AC, M Q CLK signal to load the PC register at TP1 time. However, if the CPU is in the DMA cycle, PC LD EN L is
asserted by ROM A (Figure 4-31); again, the PC register is loaded at TP1 time. This operation is carried out whenever the console E NEXT, D NEXT, E THIS, or D THIS button is pushed.
When the operator loads an address with either the LA pushbutton or the LXA pushbutton, the console logic asserts
the LA ENABLE L signal to prevent spurious incrementing of the address. LA ENABLE L can also be asserted during
the BOOT (or NON-STOP) DEPOSIT procedure. In this procedure PC LD EN L, CARRY EN L, and SEL B L are generated by ROM A, the PC register is incremented at TP1 time, data is written into memory, and the CPU continues to
run (unlike the normal deposit function that halts after a single timing cycle).

4.4.5 Major Register Load Signal Logic
The logic that generates the major register load signals is shown in Figure 4-43. At the top is the logic that produces the clock signal for the PC, the AC, and the M Q registers. When a particular register's load enable signal (PC
LD EN L, for example) is asserted, the PC, AC, M Q CLK signal causes data to be loaded into that register. Table 41 0 lists the timing pulses and shows the conditions under which a particular pulse causes PC, AC, M Q CLK t o load
a given register. Included is the reason each register is being loaded.

I O T XFER L
TP3 H
PC, AC,
MQ CLK

BUS
STROBE L

MA,MS LOAD CONT
Tp4 L

^L>

CPMA LOAD

PULSE L A H
KEY CONT L

MD DIR L

Figure 4-43

Major Register Load Signal Logic

Logic that procudes the CPMA LOAD signal appears in the middle of Figure 4-43. The CPMA register is loaded at
each TP4 time, providing the MA, M S LOAD CONT L signal has not been asserted, and when the operator loads an
address with the Programmer's Console LA pushbutton.
When the LA button on the console is pushed, the console logic causes the entry to be gated to the CPMA register.
PULSE LA H is asserted and, since KEY CONT L is negated by the LA pushbutton, the CPMA LOAD signal loads
the address into the register.
Each TP4 pulse generates a CPMA LOAD signal when MA, M S LOAD CONT L is high. MA,MS LOAD CONT L can
be asserted by a data break peripheral to ensure that the CPU returns to the correct major state at the end of the
data break (Paragraph 4.6.2). Or, MA,MS LOAD CONT L can be asserted by the console E THIS or D THIS pushbutton. When either of these pushbuttons is activated, the address selected for examining or depositing is incremented
and loaded into the PC register at TP1 time; hence, MA,MS LOAD CONT L prevents the incremented address from
being loaded into the CPMA register at TP4 time.

Table 4-10
PC, AC, MQ CLK Signal Loading
Timing Pulse

Necessary Condition

Fetch cycle

PCIUpdated address stored in PC

DMA cycle

PCIUpdated address stored in PC

DMA cycle

PCIAn Auto-Start address provided by the Programmer's
Console is loaded from the DATA lines; it is transferred
into the CPMA a t TP4 time

Defer cycle

PCIDuring a JMP I instruction, the address to which program control is to be transferred is loaded into the PC

Fetch cycle

PCIDuring a JMP instruction, the address to which program control is to be transferred is loaded into the PC
AC or MQIOperate instructions can cause either or both
registers to be loaded

Execute cycle

PCIDuring a JMS instruction, the address to which program control is to be transferred is loaded into the PC
ACIDuring a DCA instruction, 0000 is loaded into the
AC, clearing it.
During a TAD instruction, the result of the addition of
the AC contents and the contents of the addressed
memory location i s loaded into the AC
During an AND instruction, the result of the logicalANDing of the AC contents and the contents of the
addressed memory location i s loaded into the AC

BUS STROBE L

IOT transfer in progress

AC or PCIlnformation placed on the DATA lines by a
peripheral i s loaded into the AC or the PC

TP3 112

RTR or RTL microinstruction programmed

ACIThe contents of the AC register are shifted left or
right by one place

TP4

RAR, RAL, RTR, or RTL
microinstruction programmed

ACIThe contents of the AC register are shifted left or
right by one place; if RTR or RTL, this i s the second
shift to occur during TS4

The logic that generates the M D DIR L signal is shown at the bottom of Figure 4-43. Each TP1 pulse clears the DIR
flip-flop, asserting the M D DIR L signal during the read portion of the memory cycle; thus, data in the addressed
memory location is placed o n the M D lines. A t TP2 time the DIR flip-flop is kept in the clear state if the instruction
is in the Fetch state; hence, the data placed o n the M D lines during the read half of the memory cycle is rewritten
in the same location during the write half of the cycle. If the instruction is in other than the Fetch cycle, the DIR flipflop is set at TP2 time and M D DIR L is negated. This action gates the contents of the M B register, which is loaded
at each TP2 time, onto the M D lines; consequently, the M B register becomes the source of the data that is written
into memory during the write operation.
4.4.6 AC Register Control Logic
The logic in Figure 4 - 4 4 controls the AC register during many of its possible manipulations. Shown at the top of Figure 4 - 4 4 is logic tha,t generates the AC->BUS L signal. ROM D and ROM E are the primary producers of AC->BUS
L. The logic shown is needed for isolated events. Note that the gating of the signals results in AC->BUS L being
asserted during TS2 of a Fetch cycle, and during TS2 or TS3 of an Execute cycle.

MS1

ROM D
TO
AC-BUSL

TO
T1

ROM E

LO EN L
RR EN

L I N K RR EN

L I N K R L EN

XFER L
TS3 L

R L EN

TS4 L
NOTE:
T 0 HIGH= TS2
T 1 HIGH=TS3

Figure 4 - 4 4

AC Register Control Logic

In the first instance, a Fetch cycle, the AC register contents are placed on the DATA lines during TS2, gated t o the
adders by the DATA CMP L and DATA ENA L signals (Figure 4-53), and placed on the SUM lines. The SUM lines
are tested by the Skip logic (Paragraph 4.5.3) in carrying out the SZA microinstruction. If the AC contents were
0000, the ZERO L signal is loaded into the 2-flag flip-flop at TP2 time and the next program instruction is skipped.

In the second instance, an Execute cycle, two uses are made of the AC->BUS L signal. For one, the AC contents
are placed on the DATA lines during TS2 of the DCA instruction, gated to and loaded into the M B register at TP2
time, and written in the addressed memory location. For another, the AC contents are placed on the DATA lines during TS3 of the TAD instruction, gated to the adders, where the add operation is accomplished, and loaded into the
AC register at TP3 time.
Below the AC->BUS L logic is the byte-swap logic that generates the BSW L signal in response to the BSW microinstruction(7002). When the BSW instruction is issued, the AC contents are placed on the DATA lines during TS3,
gated to the adders, and put on the SUM lines. The BSW L signal, which is asserted at TP2 time, causes the information on the SUM 0 line to be gated t o the input of AC bit 6, and the information on the SUM 6 line to be gated
to the input of AC bit 0. Likewise, AC bits 1 and 7, 2 and 8, 3 and 9, 4 and 10, and 5 and 1 1 are swapped. At TP3
time, the AC is loaded and the byte swap has been carried out.
A t the bottom of Figure 4-44 is the logic that controls the loading and shifting of the AC register and the Link (the
LNK RR EN and LNK RL EN signals are used to control the Link and are explained in Paragraph 4.5.4; they are
shown here only for information). The AC register comprises DEC74S194 bidirectional shift registers that can be parallel loaded and shifted either left or right. The signals RR EN and RL EN, generated by multiplexer E68 in Figure 4 44, determine the mode of operation for the register, as outlined below.

RR EN

RL EN

AC Register Mode

HI
HI
LO
LO

HI
LO
HI
LO

Parallel-load
Right-shift
Left-shift
Do-nothing

The AC register can be loaded from the SUM lines at TP3 times, at BUS STROBE L time, at TP3 1/2 time (Paragraph 4.4.5), i.e., during TS3 and TS4. Most of the AC operations involve parallel loading in TS3. During, TS3 the
state of the AC LD EN L signal determines the state of the RR EN and RL EN signals. If AC LD EN L has been asserted by ROM C, D, or E, RR EN and RL EN place the AC register in the parallel load mode and the register is
loaded at TP3 time or at BUS STROBE L time.
During TS4 of a Group 1 operate microinstruction, the state of M D bits 8 and 9 determine the state of RR EN and
RL EN, respectively. This device permits the rotate instructions (RAR, RAL, RTR, and RTL) to shift the AC register
right or left. For example, the RAR (7010) instruction - rotate AC and Link right one - asserts the M D 8 L signal,
while negating the MD9 L signal. As a result, RR EN is high and RL EN is low, producing a right shift of the AC
register at TP4 time (AC1 1 is shifted into the Link register). If RTR (7012) - rotate AC and Link right two - is programmed, the AC is clocked at TP3 1/2 time as well as at TP4 time (AC10 is shifted into the Link register).

4.5 M A J O R REGISTER GATING
The major registers of the PDP-8/A perform all the operations needed to implement program instructions. For example, the PC register keeps track of the program steps, the CPMA register selects the memory location provided by
the PC, and the AC register uses the data in the selected memory location to carry out arithmetic operations. Information of one type or another (data, addresses, etc.) must be exchanged by the major registers or transferred between a register and some source or destination, such as a peripheral or core memory. The major register gating
network, illustrated in block diagram form in Figure 4-45, enables this exchange and transfer of information. The
block diagram shows the gating for bit 0 of the 12-bit data word; all other bits are gated similarly and differences
that exist are noted in subsequent discussions.

G^
SUM 0

C OUT L

ADDER

HI
HI

L O

- I -

L O ]

CHANGE

1 HI-Z

DATA 0 L

1 HI

LOGIC

ADD I N 0

-0

DIS2.4
BUF
8097
El05

AC-BUSLÃ‘OS

MAOL

F2
M UX
8234
E86

_
SO

M Q a B U S LÃ‘
A2

MUX
8235
E87

(ACO +AC6)

MDOL

!%LA CPMA
8T10

LINK 1

^
SUMO+SUM6

SUM 6

Figure 4-45

AND EN L

Block Diagram, Major Register and Gating (BITO)

MQ LOAD E N L
74163

Central to the major register gating is the DEC7483 full adder. When information is transferred from or to a major.
register, it passes through the adder, where it may or may not be modified, and is placed on the SUM line. Each register, except the MQ, is loaded from the SUM line. The register that is to receive the data is determined by various
control signals; these are generated in response to the instruction identity, the CPU major state, the timing generator
time state, or to some combination of these factors.
For example, the program count in the PC register is transferred to the CPMA register at the end of one instruction
to indicate the memory location of the next instruction of the program. Hence, during TS4, the PC EN L signal gates
the PC0 bit to the adder via the ADD IN 0 line. During the same time state, the DATA CMP L and DATA ENA L
signals disable the DEC74S158 data selector (E95), causing a logic 0 to be applied to the other input of the adder
(pin A4). The result, PCO, is placed on the SUM 0 line and loaded into the CPMA register by the CMPA LOAD signal, which is generated by each TP4 pulse. Some circumstances require that a program instruction be skipped; this
can be done if the program count in the PC register is incremented by the adder before being placed on the SUM
line. The CPU Carry In logic generates the C IN L signal during TS4, causing the adder to increment the program
count. The result, PC+ 1 (the logic 1 is added directly to bit 11 of the PC), is loaded into the CPMA register.
At times, information must be transferred between a major register and some source external to the CPU. A peripheral, for instance, can transfer data to the AC register during a programmed I/O dialogue. The peripheral places
the data on the DATA bus. During TS3 it is gated through the data selector to the adder and placed on the SUM
line. The byte-swap multiplexer (El 15) gates the data to the AC register and the register is loaded by the PC, AC,
MQ, CLK signal at TP3 time. The data transfercan be made in the opposite direction, as well. In this case, the AC>BUS L signal places the AC contents on the DATA bus during TS3. The peripheral is responsible for clocking the
data from the DATA bus into a peripheral buffer register. The original data may be returned to the AC register and
reloaded at TP3 time; alternatively, the data selector can be disabled so that logic zeroes are placed on the SUM
lines and clocked into the AC.
The foregoing examples are presented merely to familiarize you with the block diagram in Figure 4-45. To become
familiar with the operation of the major registers and gating, one should become adept at following the gating of
PDP-8/A instructions through the logic represented in the block diagram.
Most of the major register enable signals and the various multiplexer control signals were introduced in the ID discussion, Paragraph 4.4. There, it was pointed out that a number of ROMs play an important part in decoding instructions and generating major register gating control signals. The logic for each ROM was illustrated and mention was
made of tables relating the ROM input and output signals. Two of these tables (4-1 1 and 4-12) appear in this paragraph. Other tables appear in the Skip logic, in the Major State Register logic, and in Paragraph 4.6, I/O Transfer
Logic. Each table relates the input and output signals of a particular ROM and gives a brief resume of the result
achieved by each output condition. For example, Table 4-1 1 provides information about ROM D, which generates
major register gating signals when operate microinstructions are programmed. The INPUT CODE column lists the
codes represented by the input signals in octal form. The INPUT SIGNAL LOW column indicates the signals that
must be low to achieve the desired input code (this convention is chosen because most of the PDP-8/A Omnibus
signals are active when low). The ROM OUTPUT SIGNAL column shows the signals that are generated for each input code (consider the inverter at output pin 2 as part of the ROM), while the INSTRUCTION OCTAL CODE column
indicates the group of operate instructions that relate to each input code. Finally, the RESULT column summarizes
the events that take place in the major register gating logic in response to the signals generated by the ROM.
Each of the 256-bit ROMs has a similar explanatory table asociated with it. A t the top of each table is a notation as
to when the ROM is enabled. ROM D is enabled when pin 15, is low, i.e., during TS3 of an operate instruction.
Some of the ROM tables include a column headed DCDR OUTPUT SIGNAL. These ROMs generate three signals SEL A L, SEL B L, and SEL C L - that are applied to a BCD-to-decimal decoder, E71. The decoder then asserts the
signal indicated in the DCDR OUTPUT SIGNAL column.

To use the ROM tables with the block diagram in Figure 4 - 4 5 first consider what variables are represented by examining the instruction. Then find the ROM that is enabled for the set of variables exhibited. For instance, operate instructions are executed, for the most part, during TS3. ROM D is enabled during TS3, so refer t o Table 4 - 1 1. For a
specific example, think about the CMA (7040) instruction - complement the AC. Table 4-1 1 shows four entires in
the INPUT CODE column that apply to the octal code 70XX. Two of them, 3 4 and 36, generate the CARRY EN L
signal, which is not needed t o complement the AC; consequently, those entries can be ignored. Both of the remaining entires generate AC->BUS L and AC LD EN L. However, entry 3 5 generates DATA CMP L as well as DATA
ENA L, a combination that results in the complement of the information on the DATA lines being gated t o the SUM
lines. Thus, the events take place as follows: AC->BUS L gates the content of ACO t o the DATA 0 line (Figure 4 45); multiplexer â‚¬ gates the complement of the ACO bit t o the adder, which places the information on the SUM 0
line; multiplexer E l 15 passes the information on the SUM 0 line to the ACO-bit input, from where it is loaded at
TP3 time.
As another example, consider the basic AND instruction that directs a logical ANDing of the AC contents and the
contents of the addressed memory location. This is an interesting example, since the major register gating operates
intricately while executing the AND instruction. First of all, locate the ROM table that applies t o basic instructions Table 4-12. The entry for input codes 3 4 and 3 5 apply in this example. Input code 3 4 produces the M D EN L signal
that gates the operand of the AND instruction through buffer E l 0 5 and the adder t o the M B register during TS2. At
TP2 time, the M B register is loaded and becomes the source of data for the M D lines (this ensures that the operand
is re-written during the write operation). During TS3, input code 3 5 produces the AND EN L signal. As can be seen
from the function tables in Figure 4-45, AND EN L causes multiplexer E86 to gate the complement of the data on
the MDO line to the DATAO line; at the same time, multiplexer â‚¬ places the content of the ACO bit on the
DATAO line. If both MDO L and the ACO bit are logic 1 (MDO L is low and ACO is high), DATAO L is high, which is
not logic 1 but which is quickly converted t o logic 1 by multiplexer â‚¬9 Thus, the SUM 0 line goes low, multiplexer
E l 15 places a high at the input of the ACO bit, and a logic 1 is loaded into the AC at TP3 time. If either MDO L or
ACO is logic 0, a logic 0 is loaded into ACO at TP3 time.
Most of the gating control signals are generat,ed by the various ROMS. Those few that are not are produced by either the supplementary logic discussed in Paragraphs 4.4.3 through 4.4.6, or by the Carry In logic, the Skip logic,
and the Link logic. The last three groups of logic are discussed in detail in Paragraphs 4.5.2 through 4.5.4. Section
4.5.1 discusses Page logic, which modifies the block diagram of Figure 4-45 in certain circumstances.

4.5.1 Page Logic
The operand of a memory reference instruction (MRI) or the effective address of an indirectly-addressed J M P instruction can be stored in the current page or in page 0. The logic shown in Figure 4-46, which is only partially illustrated in the block diagram of major register gating, satisfies either eventuality.
A t TP4 of the Fetch cycle, the address of the MRI operand, for example, must be loaded into the CPMA register. If
the operand is on the same page as the MRI, only the relative address bits ( 5 through 11) of the CPMA register
need be changed; hence, M A bits 0 - 4 are loaded into CPMAO-4, respectively, t o specify the current page, while M D
bits 5-1 1 are loaded into CPMA5-1 1, respectively, to specify the relative address. However, if the operand is located
on page 0, both the relative address bits and the page bits must be changed; thus, zeroes are loaded into CPMAO-4,
while M D bits 5- 1 1 are, again, loaded into CPMA5- 1 1.
The MD4-bit is used to indicate current page or page 0. When M D 4 L is asserted, the MRI operand or the JMP I
effective address is on the current page. The PAGE EN L signal is asserted by ROM B for an MRI (Table 4-1 3) or by
ROM C for the J M P I instruction (Table 4- 12). As Figure 4 - 4 6 shows, M A bits 0 - 4 are placed on ADD IN lines 5- 1 1
( M D bit 5 is gated by an 8 0 9 3 tri-state quad buffer). When the MD4-bit indicates page 0, zeroes are placed on the
ADD IN 0 - 4 lines, while the M D lines are again gated t o ADD I N lines 5-1 1.
Note (Table 4-12) that the PC, rather than the CPMA, is loaded for the J M P I instruction. Also, this operation takes
place during TS3 rather than during TS4.

Table 4-11
ROM D Input/Output Signals
(ROM Enabled for OPR*TSE)
I

MD4L

n o u t Signal Low
I MD5L I MD6L

R O M Output Signal

I M D 7 L 1 MD11 L

Result

Instruction
Octal Code
-

X
X

DATA ENA L, AC LD EN L, MQ
DATA ENA L, AC LD EN L
DATA ENA L. AC LO EN L, MQ
DATA ENA L, AC LO EN L

BUS L, MQ CLR EN L

X
X

X
X
X
X

X
X

X
X
X
X

X
X

MQ AC, Clear MQ
DATA AC
MQ -+ AC
DATA AC
-+

BUS L

DATA CMP L, AC LD EN L, MQ CLR EN L
DATA ENA L, AC LD EN L
DATA CMP L, AC LD EN L
DATA ENA L. AC LD EN L

DATA ENA L, AC LD EN L, MQ -* BUS L, MQ LD EN L
DATA ENA L, AC BUS L. AC LD EN L
DATA ENA L, AC+ BUS L, AC LD EN L, MQ + BUS L
DATA ENA L, AC BUS L. AC LD EN L

Clear AC, Clear MQ
DATA AC
Clear AC
DATA -* AC
+

Swap AC and MQ

AC * AC
Inclusive OR, AC and MQ
AC AC

P
.
.
.

DATA CMP L, AC LO EN L, MQ LD EN L
DATA ENA L, AC+ BUS L, AC LD EN L
DATA ENA L, AC+ BUS L, AC LD EN L
DATA ENA L, AC BUS L, AC LD EN L

AC- MQ,O-+AC
AC 4 AC
AC AC
AC AC

DATA ENA L, DATA CMP L, AC LD EN L, CARRY EN L
DATA ENA L, DATA CMP L, AC LD EN L
DATA ENA L, AC LD EN L, CARRY EN L
DATA ENA L, AC LD EN L

DATA+l AC
DATA AC
D A T A + l + AC
DATA AC

DATA ENA L, DATA CMP L, AC LD EN L, CARRY EN L
DATA ENA L, DATA CMP L, AC LD EN L
DATA ENA L, AC LD EN L, CARRY EN L
DATA ENA L, AC LD EN L

DATA+l -+ AC
DATA -+ AC
D A T A + l + AC
DATA AC

DATA ENA L, DATA CMP L, AC BUS L, AC LD EN L, CARRY EN L
DATA ENA L, DATA CMP L, AC-Ã BUS L, AC LD EN L
DATA ENA L, AC + BUS L, AC LO EN L, CARRY EN L
DATA ENA L, AC BUS L, AC L D EN L

Complement and increment the AC
Complement the AC
Increment the AC
AC AC

DATA ENA L, DATA CMP L, AC-Ã BUS L, AC LD EN L. CARRY EN L
DATA ENA L, DATA CMP L, AC -Ã BUS L, AC LD EN L
DATA ENA L, AC BUS L, AC LD EN L, CARRY EN L
DATA ENA L, AC+ BUS L, AC LO EN L

Complement and increment the AC
Complement the AC
Increment the AC
AC -+ AC

ADD

IN?

IN3

ADD
IN6

HEX BUFFER
8097
'Io4

MA1 L

ADD
IN8

ADD
IylO

HEX8 0BUFFER
97
E77

D l S 4 0--

MD7L

MA3L

MD9L

'ls2LDlS4

MDll L

L--~-I

PAGEMD4
EN L

I
8097

ADD IN 0-4
MAOL-MA4L

ADDING-I1
MD6L-MDIIL

HI-Z

HI72

DIS 2,4

MD E N

Figure 4 - 4 6

Page Logic

4.5.2 Carry In Logic
The Carry I n (ogic is shown in Figure 4 - 4 7 . The C I N L signal enables the processor t o increment data. This signal is
applied t o the carry input of adder bit 1 1 . There, i t is added t o t w o other inputs - the addend and the augend; any
carry from the addition is applied t o adder bit 10, and so on, until a carry from adder bit 0 (C OUT L) is applied t o
the Link logic.
Data must be incremented for a variety of operations. This variety involves all the CPU Time States as well as the
CPU Major States. The digital multiplexer, DEC74151, has the versatility t o cope w i t h the many enabling signals
that are encountered. The 7 4 1 5 1 data select inputs at SO, S1, and S2 determine which of the 8 input lines is
routed to the output. The table in Figure 4-47 shows the inputs and outputs and lists the involved time states as
well.
Consider the major event that occurs during TS1 of a Fetch or D M A timing cycle, i.e., the address o n the M A lines
is incremented and loaded into the PC register at TP1 time. Because the address must be incremented, the Carry In
logic must assert the C I N L signal during TS1. The 7 4 1 5 1 table shows that during TS1, the input at either DO or
D4 is gated t o the output and causes the C I N L signal t o go low. Thus, the address can be incremented during the
Fetch state as well as during a D M A cycle, when either the E NEXT or the D NEXT button on the Programmer's Console might be pushed.
The Defer and Execute states do not require an incrementing process during TS1; however, since the adders are not
used at this time, i t is unnecessary t o prevent C I N L from being asserted. Note that CARRY EN L is asserted during
TS1, provided the LA ENABLE L line has n o t been grounded by the Programmer's Console. When either the LA or
LXA pushbutton is activated, the address t o be loaded is placed o n the DATA lines and gated through the adders t o
the CPMA register. Hence, the console also grounds the LA ENABLE L line so that C I N L does not increment the
selected address.

Table 4-12
ROM C lnput/Output Signals

Input
m e

Input Signal Low

ROM Output Signal

f3asic

1 Instruction
-

Result
Output
DcDR

PAGE EN L

DATA CMP L, PC LD EN L, SEL A L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L, PC LD EN L, SEL C L, SEL B L
DATA CMP L, CARRY EN Ll SEL C L
DATA CMP L, PC LD EN L, CARRY EN L, SEL B L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L
DATA ENA L
DATA CMP L, AC LD EN L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L

If MD4 L is logic 1 (operand is on current page), M A 0 4 is loaded into PCO-4, MD5-11 is loaded into PC5-11. I f MD4 L is logic 0 (operand is
loaded into PCO-4, MD5-11 is loaded into PC5-11.
MD + 1 + MB; (contents of indirectly-addressed auto-index register are incremented and used as effective address)
MD + PC (PC is loaded with the address to which program control will be transferred)

PC -+ MB; PC + 1 + MB if Skip flip-flop is active (program count to which control will return after forced-JMS i s completed, i s stored in locatio
MA + 1 + PC (program control is transferred to the location of the first subroutine instruction)
MD + 1 + MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)
No operation

JMS

AC -+ MB (AC register placed on data bus by AC register control logic, data bus gated to MB register)
O + AC
MD + 1 + MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)

DCA

No operation
-

DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATACMP L,SEL B L,SELA L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L
DATA CMP Ll SEL C Ll SEL B L
DATA ENA L, AC LD EN Ll SEL C L, SEL B L
DATA CMP Ll CARRY EN L, SEL C L, SEL B L
DATA CMP L
DATA CMP L, SEL C L, SEL B L
DATA CMP L, DATA ENA L, AC LD EN L, SEL A L, SEL C L
DATA CMP L, CARRY EN L, SEL C L, SEL B L
DATA CMP L
Note:

T I Low = TS1 + TS2
T I High = TS3 + TS4

MD EN L
ISZ SKP TST L
MD EN L

MD+MB
MD + ADDER, AC + ADDER (AC+ BUS L generated by AC register control logic); binary addition result to AC
MD + 1 -+ MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)
No operation

TAD

AND

MD + 1 + MB (data in specified location i s incremented to test for 77778 count)
1 + skip (if incremented data was 77778, C OUT L is asserted, Overflow flip-flop is cleared a t TP2, and Skip flip-flop goes active at TP3)
MD + 1 + MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)
No operation

MD EN L
AND EPJ L
MD EN L

MD+ MB
MD + DATA BUS, AC+ DATA BUS; Logical-AND result to AC
MD + 1 + MB (contents of indirectly-addressed auto-index register are incremented and used as effective address)
No operation

L A ENABLE L

CPMA DISABLE L
ROM ADDRESS L

IR0L

SKIP FF

DATA ENA

G
41

t3V

AC AUTO L
Q U A D FF

8TlO
E62

- 7M4y5x,

-D0
D7
D6

Ffl

D-

ES9

. D5

-D 4

Al,F,
D.E

SUM 8

th
STB

s2 S l s0

NOTE:

CPMA'LOAD

Figure 4-47

Carry In Logic

T I ANDTO LOW TOGETHER
DURING TS1

During TS2, no Fetch operations require data to be incremented, In the Defer state, however, an auto-index register
(memory locations 0 0 1 0 through 0017) miglit have been referenced by the instruction being performed (refer to
Introduction to Programming, 1972, for a discussion of auto-indexing). In this case, the content of the register is incremented before being used as the instructioii operand; thus, the information on the M D lines (the auto-index register contents) must be incremented during TS2 before being loaded into the M B register at TP2 time. The 74151
table shows that during TS2 of all but the Execute state, a high input at D6 causes the C IN L signal to go low. The
signal at D6, Al, is high when the data on SUIM lines 0 through 8 indicates that an auto-index register has been referenced. The CARRY EN L signal is asserted by ROM C during this operation; refer to Table 4-12 for verification.
In the Execute state, two situations require that the C IN L signal be asserted during TS2. First, an ISZ instruction
can direct the CPU to increment the data in the specified location and then skip the next instruction if the result of
the incrementation is 0000. Second, the CPU interrupt system might have honored an interrupt request during an instruction wherein the SKIP FF signal had been asserted; consequently, rather than storing the program count in
memory location 0000, the CPU must store the incremented program count during TS2 of the forced JMS
instruction.
In both these situations, a high input at D2 of the multiplexer causes the C IN L signal t o be asserted (CARRY EN L
is asserted by R O M C). For the JSZ instruction, the IRO L signal is high and, therefore, D2 is high. For the forced
J M S instruction IRO L is low and, because the SKIP FF signal is high, pin 2 is high.
TS3 operations in the Fetch state that require the C IN L signal to be asserted, involve the IAC operate microinstruction. If IAC has been programmed, the contents of the AC register are placed on the DATA lines during TS3
and gated to the adder. A 0 is gated t o the ADD IN line of the adder, while the input at pin 1 2 of the multiplexer
causes the C I N L signal to go low (the CARRY EN L signal is asserted by ROM Dl. The result, AC+ 1, is placed on
the SUM lines and loaded into the AC at TP3 time. Similar operations take place when the IAC command is microprogrammed with other Group 1 microinstructions.

A J M S instruction requires that the address on the M A lines be incremented during TS3 of the Execute state. When
a JMS instruction is programmed, the operand of the instruction specifies the first memory location of the subroutine. In this location (Y, for example) must be stored the program count, to which the program will return upon
completion of the subroutine. The first instruction of the subroutine is contained in location Y+1 and, in order to
transfer control to location Y+ 1, the address on the M A lines (location Y) must be incremented during TS3. A high
input at D3 of the multiplexer asserts the C IN L signal (ROM C asserts the CARRY EN L signal). D3 is high providing both CPMA DISABLE L and ROM ADDRESS L are negated.
During TS4 of both the Fetch and the Execute cycles, the program count in the PC register is transferred to the CPMA
register. However, certain situations require a skip of one program instruction; hence, the program count in the PC
register must be incremented before being transferred to the CPMA. One of these situations arises when a Group 2
operate microinstruction, such as SKP, is programmed; another results from an IOT instruction causing a peripheral to
assert the Omnibus SKIP L signal; finally, an IS2 instruction might have been programmed. In each situation the SKIP
flip-flop is set at TP3 time, asserting the SKIP FF signal, This signal at D l or D5 causes the 741 51 multiplexer to assert
the C IN L signal during TS4 of both the Fetch and Execute cycles (the CARRY EN L signal is asserted by ROM B).

4.6.3 Skip Logic
The Skip logic, shown in Figure 4-48, samples the contents of the AC register and/or the Link, and the state of the
Omnibus SKIP line. If the sampled data meets specified conditions, the program count is incremented before being
transferred to the CPMA register at TP4 time; consequently, the next program instruction is skipped (Table 4-1 3).
The Skip operation is used primarily during the implementation of operate microinstructions. The majority of the
Group 2 operate microinstructions, and nearly half of the combined microinstructions involve the Skip operation.
ROM F decodes the Skip microinstructions and asserts the ISKIP L signal during TS3. The Skip flip-flop is cleared at
TP3 time, and the SKIP FF signal causes the Carry In logic to increment the program count. Two examples are offered to demonstrate how the logic responds to skip instructions.
Consider the Group 2 operate microinstruction SMA (7500) - skip on a minus AC. Remember that minus numbers
in the PDP-8/A are those between 4000(8) and 7777(8), i.e,, bit 0 is logic 1. Thus, during TS3 of the SMA instruction, ROM F will assert the ISKIP L signal if ACO is logic 1 (a hig.h voltage level). When SMA is placed on the M D
lines and the IR register decodes MD bits 0, 1, and 2, the inputs to ROM F are as follows.

ROM F Input Pin

Voltage Level
Input Octal Code

ACO

HI
617

H IILO

(If ACO is logic I )
The ROM F pattern specification in Appendix J shows that >the binary data contained in octal location 156(8) is
'1000. Thus, the ROM outputs are as follows.

ROM F Output Pin

Voltage Level
Output Signal Asserted

HI
ISKIP L

Location 157(8) causes both the ADLK L and the ISKIP L signals to be asserted. If the AC is positive, i.e., ACO is
logic 0, the ISKIP L signal remains high for any of the four possible inputs - 056(8), 057(8), 016(8), and 017(8) (inputs 0 1 6(8) and 0 1 7(8) result if input pin 2 is low, in which case the AC is zero).
The SZA (7440) microinstruction - skip on a zero AC - tests the AC for a zero condition. During TS2 the AC->BUS
L signal is asserted (Figure 4-44) and the contents of the AC register are placed on the SUM lines. If all AC bits are
zero (low voltage levels), the ZERO L signal is asserted and clocked into the flip-flop at TP2 time. The ROM input
code is 026(8) or 027(8), and ISKIP L is asserted by itself or together with ADLK L.

LI.

The ISKIP L signal can be asserted t w o other ways: a peripheral can ground the Omnibus SKIP L line during an IOT
instruction, causing ISKIP L to be asserted during TS3; or, an ISZ instruction can cause the OVF (OVERFLOW) flip-flop to
be cleared, while also generating the ISZ SKP TEST L signal, thereby asserting ISKIP L.
An ISZ instruction directs the CPU to increment the data in the specified location and skip the next instruction if the
result of the incrementalism is 0000(8) (the operand of the instruction must be 7777(8) for such a result to occur).
The data is incremented during TS2 (Table 4-12; if the reshlt is 0000(8), the C OUT L signal is asserted by adder 0
and the OVF flip-flop is cleared at TP2 time. During TS3, ISZ SKP TEST L is generated by ROM C and the ISKIP L
signal is asserted. The Skip flip-flop is cleared at TP3 time and the following program instruction is skipped. Also during TS3, the OVERFLOW L signal is asserted. This signal is commonly used with a 3-cycle data break device; in
such an application, OVERFLOW L is used by the device control to indicate the last transfer o f the data break operation (Paragraph 4.6.4).
Note that the Skip flip-flop is clocked at TP3 time of all but a DMA cycle. This restriction it necessary because of
the possibility of a data break device assuming control of the CPU immediately after a progra interrupt request has
been honored. Consider the following sequence of events: The Skip flip-flop is cleared at TP time of an SMA operate instruction, asserting the SKIP FF signal; an interrupt request is honored at the same ti e (the INT IN PROG H
signal is asserted at INT STROBE L time); a data break device takes control of the CPU by a serting the CPMA DISABLE L signal at the same TP3 time and the MS, IR DISABLE L signal at the following T 4 time. The first event
would normally cause the program count to be incremented and transferred to the CPMA register at TP4 of the
SMA instruction. However, when the INT IN PROG H signal is asserted, ROM B (Table 4-1 3) is prevented from generating the necessary gating signals. If the third event did not occur, INT IN PROG H would force the CPU into the
Execute cycle of the J M S instruction, during which cycle the incremented program count would be stored in location
0000(8) for retrieval at the conclusion of the program interrupt (Table 4-12). But, event three does occur and, thus,
control of the CPU is assumed by the data break device before the instruction register is forced to the JMS instruction. When the data break device relinquishes control of the CPU, the Execute cycle of the J M S instruction will be
entered and the PC+1 will be stored in location 0000(8), provided the Skip flip-flop is still clear and SKIP FF is
high. This provision is accomplished by prohibiting any TP3 that occurs during the data break operation from setting
the Skip flip-flop,

4.5.4 Link Logic
The Link is used with a TAD instruction and with Group 1 operate microinstructions that manipulate both the Link
and the AC register. A TAD instruction causes the contents of a specified memory location to be added to the contents of the AC register. The result of the addition can include a carry from adder 0. Since such a carry is significant,
it is registered in the Link shift register. The shift register can then be manipulated so that the information can be
used in other AC operations. The Group 1 microinstructions can be used to clear and comple-ment the Link independently of the AC register, or to rotate the Link right or left along with the contents of the AC.
The Link logic is shown in Figure 4-49. The state of the link can be represented by the LINK BIT signal, which is
monitored by ROM F (Figure 4-48 shows all the input signals that are monitored by the ROM). When the Link is to
be complemented, because either a TAD instruction or a CML instruction is issued, ROM F controls the DEC74151
multiplexer with the ADLK L signal. The multiplexer provides Link inputs that are the complement of the Link's previous state. For example, assume that the Link contains a logic one. Thus, the LINK BIT signal is high. If the CML
instruction is issued, ROM F decodes its input signals and negates the ADLK L signal. The fO output of E48 goes
low; this level is parallel loaded into the Link shift register at TP3 time, complementing the previous state of the Link
(during TS3 of an operate instruction, ROM D in Table 4-1 1 asserts the AC LD EN L signal; the DEC 74S158 data
selector causes LNK RR EN and LNK RL EN to go high, placing the Link shift register in the parallel load mode).
When a TAD instruction is issued, the C OUT L signal may or may not be asserted. If not, the fO output of E48 assumes the same level as the previous state of the Link; i.e., if the Link was high before the TAD instruction, ADLK L
goes low when ROM F decodes its input signals, and the fO output goes high. Hence, the Link retains its previous
state (during TS3 of the Execute cycle of a TAD instruction, ROM C asserts the AC LD EN L signal; thus, the Link
shift register is kept in the parallel load mode). However, if the TAD instruction had resulted in a carry out, both
ADLK L and C OUT L are asserted and the fO output goes low, complementing the Link.

When the Link is to be cleared (CLL), ROM F negates the ADLK L signal no matter what the previous Link state.
The fO output of E48 is low, and the Link is cleared at TP3 time of the instruction.
Two of the processor IOT instructions are involved with the Link bit (Paragraph 4.6.2. The GTF instruction can be
used to transfer the state of the Link to the 0 bit of the AC register. The RTF instruction enables the programmer to
return a previous Link state from the AC register to the Link register. When the RTF instruction is issued the LINK
DATA L signal causes the fO output of E48 to assume the state of the ACO bit. Then this state is loaded into the
Link register at TP3 time by the LINK LOAD L signal (during TS3 of an IOT instruction, the LNK RR EN and LNK RL
EN signals are high, keeping the Link shift register in the parallel load mode).
During TS3 of an operate instruction, ROM D asserts the AC LD EN L signal; the Link shift register is placed in the
parallel load mode by LNK RR EN and LNK RL EN. If the instruction is a rotate instruction (RAR, RAL, RTR, RTL),
the state of the Link during TS3 is loaded into the Link shift register at TP3 time; i.e., the Link is not changed when
the shift register is clocked at TP3 time. During TS4, either LNK RR EN or LNK RL EN goes low, depending on the
direction of shift (i.e., if the instruction directs a rotation to the right, LNK RL EN goes low, while LNK RR EN goes
low for a rotation to the left); the Link shift register is placed in the right shift or left shift mode. If the instruction is
RTR or RTL, the Link shift register is clocked at TP3 1/2 time, halfway through TS4. At this time, the content of AC
bit 11 is loaded into R3(1) of the Link (assume the instruction is RTR); at the same time, AC bit 10 is shifted into
AC1 1. At TP4 time, the Link is clocked again and the content of AC bit 11 (originally in AC bit 10) is loaded into
R3(1) of the Link. Both R2(1) and R l ( 1 ) were loaded with logic 1 (positive voltage in the Link) at TP3 time; hence,
both RO(1) and R3( 1) are high after the t w o clocking operations and the LINK BIT signal exhibits the correct state.
The original content of the Link shift register has been rotated two places to the right. The single-rotate instructions
are effected similarly, but the Link shift register is clocked only at TP4 time, resulting in a shift of but one position.

4.6

1/0 TRANSFER LOGIC

4.6.1 Programmed I/O Transfer Logic
Programmed I/O transfers use IOT instructions to initiate data exchanges between a user device and either the AC
register or the PC register. Information is transferred t o and from a device on the Omnibus DATA bus. Figure 4 - 5 0
illustrates the major register gating for a programmed I/O transfer, while Figure 4-5 1 shows both the logic that generates
the gating control signals and a diagram that relates essential timing signals.
When an IOT instruction involving a data transfer is issued, the user device asserts the Omnibus C lines to generate
the necessary major register gating control signals. For example, if an IOT instruction directs a particular device to
transfer data to the PC register, the device asserts the C1 L signal and the C2 L signal and places the data on the
DATA bus. ROM E produces DATA ENA L and PC LD EN L, thereby gating the data to the PC register during TS3.
At TP3 time, essentially, the PC, AC, M Q CLK signal loads the data into the PC register.
Table 4 - 1 4 relates the input and output signals for ROM E and outlines the results achieved by the possible combinations of the C line signals. Note that six possible types of data transfers exist, which are represented by input
codes 20(8) through 27(8). Input code 37 results when a GTF instruction is issued and the GTF H signal is asserted
by the Processor IOT logic (Paragraph 4.6.2). The timing diagram in Figure 4-51 shows how the PC, AC, M Q CLK
signal is generated during a normal I/O transfer cycle, i.e., when the IOT instruction does not require an extended
timing cycle. (Paragraph 4.2.5 has a detailed discussion of I/O timing for both non-extended and extended timing
cycles.)

4.6.2 Processor IOT Logic
A number of internal IOT instructions are designated processor IOT instructions. They are represented as 600X(8)
and are concerned, in general, with program interrupts. The appropriate logic is shown in Figure 4-52.

SUM 0

03~:~
1; B:l
ADDER 0

ADD I N 0

DATA CMP L

MUX E 9 5

DATA ENA L
DATA 0 L

Ã‘

PC . A C ,
MQ CLK

Figure 4-50 Major Register Gating (BITOO),
Programmed 1/0 Transfer

When a processor IOT instruction is programmed, the INTERNAL 1/0 L signal is asserted so that peripherals interfaced to the Omnibus via the KA8-E option (Positive I/O Bus interface) will ignore the IOT instruction. The seven processor IOT signals are generated by ROM J. Table 4-15 lists the inputs and outputs for the ROM in detail. Note that
only inputs 20(8) through 27(8) are used for the processor lOTs. Inputs 1O(8) through 17(8) are used when STATUS
information is to be placed on the DATA lines during TS1.

Either a peripheral or the Programmer's Console can cause STATUS information to be placed on the DATA lines by
negating the IND1 L and IND2 L signals. When this is done the STATUS L signal is asserted by the DEC74S139
decoder during TS1, and ROM J generates the GTF H signal. The status of the INT ENA flip-flop is gated to the
DATA 4 tine, the status of the INT RQST line is gated to the DATA 2 line, and the status of the Link Bit is gated to
the DATA 0 line. If the operator has used the Programmer's Console to negate the IND signals, the STATUS information is gated to the console and displayed during TS1 (the programmer will have halted the CPU before attempting
to display the STATUS information).
The GTh H signal is also asserted when the GTF instruction is programmed. In this case, the I/O L signal is generated and the significant operation takes place during TS3 (when the STATUS L signal can be only high). Again, the
DATA 4, DATA 2, and DATA 0 lines reflect the status of the INT ENA flip-flop, the INT RQST L signal, and the Link
Bit, respectively. This information, and that carried on the remaining DATA lines, is gated to the AC register and
loaded at TP3 time (Table 4-14, especially the entry for Input Code 37(8)).
The RTF instruction causes ROM J to assert RTF H and INT ON H. RTF H restores a previous state of the Link,
while INT ON H turns on the interrupt system. Both the GTF and RTF instructions have minor significance within the
processor itself; their full potential is realized only when a KM8-AA Memory Extension option is included in the
system.

I / O PAUSE H

E 76
I/O

C1 L

SEL

c L

BUS L

AC L D E N L
DATA CMP L
DATA E N A L

I / O PAUSE L
I

BUS ST,ROBE L

TS
-3
- L
-

S BUS STROBE

I yM

L
L

TPC H
NOT L A S T
XFER L

PC,AC. MQ CLK

PULSE
SYNC

7z;o
C

-1-

USER MODE L
F H

1 / 0 PAUSE H

TP1 H

TP3 H

TPC

TS3 L

N O T L A S T XFER L
S BUS S T B

BUS S T R O B E L

PC,AC , M O C L K

Figure 4-51

Programmed I/O Transfer Logic

The CAF instruction causes the ROM to generate CAP H; thus, the CAF flip-flop is set at TP3 time. Transistor Q1 is
turned on, asserting the Omnibus INITIALIZE H signal as well as the CPU INIT Lsignal, The CAP flip-flop is cleared when
the TS1 L signal goes low, negating the initializing signals at the start of the next program instruction; the flip-flop is
cleared even if the operator has been single-stepping the CPU and ends with the CAP instruction (the timing generator
asserts the TS1 L signal before halting). When power is turned on, ON L is held low for 1 0 0 ms after POWER 0 K H goes
high. The initializing signals are generated for this length of time to enable all system equipment to complete the
necessary initializing operations. When ON L goes high, TS1 L clears the CAF flip-flop and the initializing signals are
negated.
The SKON H, SRQ H, INT ON H, and INT OFF L signals are program interrupt-generated signals. They are discussed
in detail in Paragraph 4.6.3.

Table 4-14
ROM E input/Output Signals
(ROM Enabled During TS3)
Input
Code

110 PAUSE H

put Si! a1 Low
GTF
C2 L

ROM Output Signal

Result

DCDR
Output

DATA CMP L
DATA CMP L
DATA CMP L
DATA CMP L
DATA CMP L
DATA CMP L
DATA CMP L
DATA CMP L
DATA ENA L, PC LD EN L

Input data to PC register

DATA ENA L, PC LD EN L

Input data to PC register

DATA ENA L, PC LO EN L, SEL C L

PC EN L

Input data added to PC contents, result loaded into
PC

DATA ENA L, PC LO EN L, SEL C L

PCEN L

Input data added to PC contents, result loaded into
PC

DATA ENA L, AC LD EN L

Input data to AC register

DATA ENA L, AC LD EN L, AC-+ BUS L

AC to the data lines (output transfer), AC contents
returned to AC; input data can be OR'ed with AC

DATA CMP L, AC LD EN L, AC+ BUS L

AC to the data lines (output transfer), zero to the
AC

DATA ENA L, AC LD EN L, AC + BUS L

AC to the data lines (output transfer), AC contents
returned to AC; input data can be OR'ed with AC

DATA ENA L, AC LD EN L

Link bit to ACO

1 / 0 PAUSE H

-^
INTERNAL I / O L

MD6 L
MD7 L
MD8

4-L

TP3H-c

+ 5V

0STATUS L
0

CAF

14
.

MD9 L

13
l2

CAF H
2
ROM

RTF H
GTF H

TP3H

LINK
LOAD L

IF SETL

ml
74S139

O F F L I N T ENA

-INT

ON L

DATA2L

INT RQST L

LINK BIT

Figure 4-52

ROM J
INPUT

Wl
(INDICATE)

1 RTFH

1 24

1 SRQH

DATA 0 L

Processor IOT Logic

Table 4-15
ROM J Input/Output Signals
(ROM Enabled Permanently)
Input
Code

10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27

In
i/O L

STATUS L

x
x
x

Processor-1OT
Instruction

X
X
X
X
X

x
x
x
X
X
X
X
X

*From memory extension control, if present.

Result

Status word gated to data lines during TS1. Information
on data lines shown below.

GTF H

Data Bit
0

GTF H
GTF H
GTF H
GTF H

2
4
5

CAF H
NOP
RTF H, INT ON H
GTF H
SRQ H
INT OFF L
INT ON H
SKON H, INT OFF L

6-8
9-1 1

Information
Link Status
Status of INT RQST L signal
Status of Interrupt Enable flip-flop
USER MODE L signal status*
!F<0: 2>*
DF<O: D*

4.6.3

Program Interrupt Logic
Program interrupt data transfers are more efficient than programmed I/O transfers. In the program interrupt transfer
mode, the program is interrupted only when an option demands attention by asserting the Omnibus INT RQST L signal.
The interrupt system monitors this INT RQST L signal. If the system is turned on when this signal is asserted, the
processor executes a hardware-generated J M S to location 0. Simultaneously, i t turns off the interrupt system; thus,
further interrupts can occur only when the present one has been serviced. A program subroutine is entered to determine
the identity of the requesting option. When this identity has been established, a servicing subroutine allows the option to
take part in a programmed I/O dialogue with the processor.

The Interrupt logic is shown in Figure 4-53. The system can be turned on when the ION instruction asserts the INT
ON H signal. Each stage of the DEC8271 quad flip-flop must be in the clear condition; if so, the DEC74153 multiplexer gates a high to input D l of the quad flip-flop and a low t o input D2. The quad flip-flop is set at INT STROBE
L time, asserting the INT ENA signal. During the next Fetch cycle, the high at multiplexer input B1 is gated to input
D2 of the quad flip-flop; again, input D2 of the flip-flop is high. D3 of the flip-flop might be high, as well, provided,
first, that the INT RQST L signal has been asserted by a peripheral and, second, that the Fetch cycle being performed is that of a 1-cycle instruction, i.e., IF SET L is low. However, if we assume that the Fetch cycle is part of a
multi-cycle instruction, D3 is low; thus, at INT STROBE L time INT DLY and INT ENA, only, are asserted. During the
concluding cycle of the instruction, and if the INT RQST L signal is low, all inputs to the quad flip-flop, except DO,
are high. At INT STROBE L time INT ENA, INT DLY, and INT SYNC go high and the INT IN PROG H signal is
asserted.
Because INT IN PROG H is high during TS4, the Instruction register is forced to J M S at TP4, while the Major State
register is forced to the Execute state. During this Execute state cycle, the program count to which control will return after the program interrupt, is stored in memory location 0000. The INT STROBE L pulse that occurs during the
forced-JMS Execute cycle clocks the quad flip-flop, negating the INT DLY and INT ENA signals and, as a result, the
INT IN PROG H signal (note that it now makes no difference what happens to the INT SYNC signal). The CPU then
proceeds t o the interrupt servicing routine. At the end of the routine, an IOT instruction turns on the interrupt system
again. Note that there is a delay of at least one complete timing cycle from the time that the INT ENA signal goes
high until the INT IN PROG H signal can again be asserted (if data break devices suspend the normal timing, there
can be a delay of many more than one cycle). This delay enables the CPU to obtain the return address from memory
location 0000, restoring control to the program before allowing a new interrupt to occur.
The IOF instruction turns off the interrupt system by asserting the INT OFF L signal. Because both INT DLY and INT
ENA are high and INT SYNC is low when the system is on (the system can be on without an interrupt request), the
multi-plexer gates the lows at its DO and D l inputs to the quad flip-flop. The INT STROBE L signal then clocks the
flip-flops, negating INT ENA and INT DLY.
Two CPU IOT instructions test the status of the interrupt system. The SKON instruction asserts the I SKIP L signal if
the interrupt system is on, i.e., if the INT ENA signal is high. If I SKIP L is low, the SKIP flip-flop is set at TP3 time.
Then, during TS4, the C IN L signal is asserted, the program count in the PC register is incremented, and the instruction following SKON is skipped. Because the INT OFF L signal is generated along with the SKON H signal (Figure 452), the interrupt system is turned off just after INT ENA is sampled. The SRQ instruction can also cause a program
instruction skip, but only if an interrupt request has been generated by a peripheral.

4.6.4 Data Break Transfers
Data transfers between a data break device and memory or between the Programmer's Console and memory occur
in the CPU DMA state. This state provides direct communication between the device and memory, allowing the device to assume control of major register gating by asserting a number of Omnibus signals when it is ready to make a
data transfer. Figure 4-54 illustrates the part of major register gating that is most involved with data breaks, while
Figure 4 - 5 5 shows the logic that generates the applicable gating signals.

I F SET L

I SKIP L

I N T RQST L

SRQ H
SKON H

STB1

STBO

INT OFF L

SHF

-C1
Bl
D2

F1-

' A 1

- BO

MUX
74153
E45

R 2 (1

INT DLY

-INT IN PROG H

QUAD FF
8271
E31

CO
FO -.

DO
INT ON H

DMA L

74153

S1
L
L

SO
L
H

STB0.1
L
L

827 1

Figure 4-53

SHF
L
L

LD
L
H

OUTPUT AFTER CLOCK (INT STROBE L)
SAME AS BEFORE CLOCK
SIGNAL AT CORRESPONDING INPUT

Program Interrupt Logic

When the data break device is ready t o begin a transfer, it asserts the MS,IR DISABLE L and CPMA DISABLE L signals; the former disables both the IR register and the Major State register (E62), forcing the CPU to the D M A state,
while the latter negates CPMA->BUS L at TP4 time, removing the CPMA register from the M A lines. With the
CPMA register disabled, the device can specify the memory location from or t o which data will be transferred.
Three types of data break transfers are available to a peripheral, i.e., Input (Break Deposit), Output, and Add t o Memory (ADM). Table 4 - 1 6 provides the input/output signal relationship for ROM A. The entries for input codes 30(8)
through 37(8) apply t o the Break Deposit and ADM operations; the Output transfer is just a variation of ADM. For
example: l f the device is to make an ADM transfer, it places the memory address on the MA lines after asserting
CPMA DISABLE L and MS,IR DISABLE L; at TP1 of the DMA cycle, the device asserts M A , M S LOAD CON1 L so
that TP4 of the D M A cycle does not clock the CPMA register (Paragraph 4.4.2); at the beginning o f TS2, the device
asserts BREAK DATA CON1 L, causing the M D EN L signal t o be produced by the decoder associated with ROM A
(Figure 4-31 shows the decoder) and, thus, gating the data in the addressed location to the adder; also, early in TS2

the device places the information t o be added on the DATA bus, from where it is gated t o the adder by multiplexer
E95; the result is placed on the S U M lines and loaded into the M B at TP2; because M D DIR L goes high at TP2,
the MI3 contents are placed on the M D bus and stored in the addressed memory location during the write operation.
If an output transfer is t o be performed, the device follows the same procedure as for the ADM, without placing information on the DATA lines; the data t o be transferred t o the device can be taken from the M D lines at TP2, TP3,
or TP4 time.
The A D M operation might result in a carry-out from adder 0 (C OUT L is asserted). If so, the OVF flip-flop, Figure 4 55, is cleared at TP2 time, and the OVERFLOW L signal is generated during TS3. The device can use this signal as
directed by the program; however, OVERFLOW L is commonly used with a 3-cycle data break device to indicate the
last transfer of the data break operation.
The Non-stop Deposit function, entries 10(8) through 13(8) in Table 4- 16, is intended to be used, primarily, during
bootstrap operations. The function gives the same result as Panel Deposit, but because STOP L is not generated, the
CPU continues to run. When the BOOT button on the Programmer's Console is pushed (or when the BOOT switch
on the Limited Function Panel is pressed), the Bootstrap Loader option provides the starting address for the bootstrap operation and asserts M E M START L, LA ENABLE L, and BREAK DATA CONT L The option places information
on the DATA bus during each TS2 until the bootstrap program is loaded entirely, at which time normal CPU operations are resumed.

SUM 0

COUT L

ADDER 0

<s
DATA CMP L

DATA ENA L

E95

DATA 0 L

MA EN L

MD EN L - 0
El04

El05

MD 0 L

A
CPMA 4 BUS L
CPMA LOAD

,b
ACO

Figure 4 - 5 4

r"'

MQ-BUS L

M BO
1

E86

CPMA 0

I
AC-BUS

AND E N L

Major Register Gating (BITO),
Data Break Transfer

â‚¬

Table 4-16
R O M A Input/Output Signals

fROM Enabled for OMA State)

Code
ENABLE L

Input ! inal Low
KEY
BREAK DATA
CONTROL L
CONT L

CPU
Time
State

ROM Output Signal

DCDR
Output Signal

TS 1

LOAD

DATA CMP L

TS4

DATA CMP L, SEL A L, SEL C L

AND EN L

EXTENDED

TS2

DATA CMP L,SEL C L, SEL B L

MD EN L

ADDRESS,

TS3

DATA CMP L, SEL A L, SEL C L

AND EN L

FIELD 7

DATA CMP L

LOAD

DATA CMP L

EXTENDED

DATA CMP L, SEL C L, SEL 6 L

ADDRESS,

DATA CMP L

FIELD 0

DATA CMP L, PC LD EN L, CARRY EN L, SEL B L

When console 'LXA' button is pushed, address is placed on data bus (DATA 6-1 1),gated to IF and DF registers and loaded by PULSE LA H.

See text

When console 'LXA' button is pushed, address is placed on data bus (DATA 6-1 11, gated to IF and DF registers and loaded by PULSE LA H.

See text

MA+1 + PC at TPl

DATA CMP L, SEL G L

NON-STOP

PC contents loaded into CPMA at TP4.

DATA ENA L

DEPOSIT

Information on data bus gated to MB, loaded at TP2, deposited in addressed memory location.

DATA CMP L

No major register operation.

TS1

DATAENA L

TS4

DATA CMP L, SEL C L

LOAD

TS2

DATACMPL.SELCL,SELBL

ADDRESS

TS3

DATA ENA L, PC LD EN L

TS1

DATA CMP L, PC LD EN L

TS4

DATA CMP L, SEL C L

PANEL

PC contents loaded into CPMA at TP4, providing MA, MS LOAD CONT L is high (signal is low if 'E THIS' button i s pushed).

TS2

DATA CMP L, SEL C L, SEL B L

EXAMINE

Data in addressed location loaded into MB at TP2; operator used 'MD' and 'DISP' buttons to display MB contents.

TS3

DATA CMP L, STOP L

TS1

DATA CMP L, PC LD EN L

TS4

DATA CMP L, SEL C L

PANEL

PC contents loaded into CPMA at TP4, providing MA, MS LOAD CONT L is high (signal is low if 'D THIS' button is pushed).

TS2

DATA ENA L

DEPOSIT

Console entry data placed on data bus, gated to MB, loaded at TP2, deposited in addressed memory location.

TS3

DATA CMP L, STOP L

When console 'LA' button is pushed, address i s placed on data bus, gated to CPMA, and loaded by CPMA LOAD signal.

See text
-

MA+1 (See Figure 4-54) loaded into PC at TP1.

Timing generator 'RUN' flip-flop cleared at TP3, halting timing cycle after TS4 i s completed.

MA+1 (See Figure 4-54) loaded into PC at TP1.

Tirnina Generator 'RUN' flip-flop cleared at TP3, halting timing cycle after TS4 is completed.
-

TS1

DATA CMP L

TS4

DATACMPL

TS2

DATA ENA L, SEL C L, SEL B L

No major register operation.

ADD
MEMORY

BREAK

NO major register operation.

Data in addressed location gated to adder, added to information placed on data bus by peripheral; result loaded into MB at TP2, returned
to memory.

No major register operation.

TS1

DATACMP L

TS4

DATACMP L

BREAK

No major register operation.

TS2

DATA ENA L

DEPOSIT

Peripheral places information on data bus; information gated to MB register, loaded at TP2, written into addressed memory location.

TS3

DATACMP L

No major register operation.

1
CPMA D I S A B L E L 4

QUAD F/F

R3(111-

CLEAR L

CPMA 4 BUS L

QUAD F/F
40
30

-E!-,
DL

DMA L

20
MS,IR DISABLE L
CLK

CLR

-1
-

TP4
MA ,MS
LOAD C O N T L

CPMA LOAD

PULSE L A H
KEY CONTROL L

SEL C L

L A ENABLE L

SEL B L

BREAK DATA
CONT L
TO

ROM A
DMA

SEL A L

CARRY E N L

PC L D E N L

STOP L

DATA C M P L
0

Figure 4-55

DATA ENA L

Data Break Transfer Control Signal Logic

Communication between memory and the Programmer's Console is also effected during the DMA state. The Panel
Exam and Panel Deposit functions permit an operator t o examine or deposit data in an addressed location (refer t o
Paragraph 4.6.4 for details); the Major Register gating during all timing cycles of both functions is outlined in Table
4 - 16.
The Load Address and Load Extended Address functions can be initiated by the Programmer's Console LA and LXA
pushbuttons, respectively. The applicable TS1 operations are shown in the table. Each of these functions can be initiated by the auto-start feature that is available with the PDP-8/A CPU. This feature was introduced in Paragraph
4.2.1 ; the Major Register gating and the appropriate timing will be detailed in the following paragraphs.
Figure 4 - 5 6 shows the auto-start timing, while Figure 4 - 5 7 illustrates the associated logic. The discussion that follows assumes that contact 4K of switch S1 is closed and contact F7 is open, i.e., the starting address is in memory
field 0.

POWER OK H

CLEAR L

DATA 0 L
CPMA-ÃˆBU

KEY CONTROL L

LA ENABLE L

M S , I R DISABLE L

CPMA LOAD
NOTE:
Signal relationship is only
approximate.

Figure 4 - 5 6

n
A

ZERO'S
I NTO CPMA

40000
INTO CPMA

4001
I NTO CPMA

AUTO-START Timing

When the auto-start sequence begins, the memory field address is loaded into the IF and DF registers of the KM8AA Extended Memory option. This event occurs during the first timing cycle of the sequence, when the KEY CONTROL L and LA ENABLE L signals are asserted. The entries in Table 4 - 1 6 for input codes 4(8) through 7(8) apply t o
this first timing cycle. During TS1 no major register operations take place (the RESULT entry for TS1 indicates what
happens when an extended address is loaded from the Programmer's Console). During TS2, the data i n the addressed memory location - a location that is both random (the state of the CPMA at power-on is uncontrollable) and
immaterial - is gated through Major Register gating t o the M B register, loaded at TP2, and returned to the memory
location ( M D DIR L goes high at TP2). This operation is of no significance to the auto-start feature, but is necessary
so that the data in the memory location is retained. During both TS3 and TS4 the DATA lines are high (multiplexers
E 8 6 and E87 are disabled), and the IF and DF registers are loaded with logic 0. Since the SUM lines are also high
during TS3 and TS4, the CPMA register is loaded with zeroes at TP4.

/-DATA

0 L

~K./-DATAI

1
I 400~~0I
200 ^ro
I OFF/
1

~K'/-DATA~L

+3 V

RlO) -

DATA3 L
DATA 4 L

F 7 y

BREAK DATA CONT L

KEY CONTROL L
F/ F

L A ENABLE L

- MEM START L

MS.IR DISABLE L
CPMA
DIS L

I
CLEARL
TP4

1
1

MA. M S LOAD CONT L

Figure 4-57

CPMA LOAD

AUTO-START Timing, CPU Logic

During the second timing cycle of the sequence, KEY CONTROL L is negated, while DATA 0 L is asserted; input
codes 14(8) through 17(8) of Table 4-16 are pertinent. In TSI, no operation takes place (the RESULT entry indicates what happens when an address is loaded from the Programmer's Console). During TS2, the data in location
0000(8) is gated to the MB, loaded, and returned to memory. In TS3 the information on the DATA lines, 4000(8), is
gated to the PC register and loaded at TP3 time. During TS4, the PC contents are gated through Major Register gating to the CPMA register and loaded at TP4 time. At this same TP4 time MS,IR DISABLE L is negated and the CPU
goes into the Fetch cycle, carrying out the instruction in location 4000(8).
If the auto-start address had been located in memory field 7, Major Register gating operations in TS3 and TS4
would have been as outlined in the entries for input codes l ( 8 ) and 3(8) of Table 4-1 6. During both time states the
AND EN L signal gates the contents of the AC register through multiplexer E87 to the DATA bus. If the AC contains
zeroes, as it must for this function to work properly, 7777(8) is placed on the DATA bus and the IF and DF registers
are loaded with 7(8). All other autostart operations are the same as for memory field 0 .

CHAPTER 5
MEMORY OPTIONS

PDP-8/A Memory Options are as follows:
M R 8 - A Read Only Memory (ROM) in 1 K, 2K, or 4 K sizes.
MS8-A Random Access Read Write memory (RAM) available in 1 K, 2K, or 4 K sizes.
MR8-FB Reprogrammable Read Only Memory (PROM) available in 1 K size with 2 5 6 words of read/write RAM
memory.
M M8-AA 8 K Core Memory
M M8-AB 16K Core Memory
The PDP-8/A memory system can be configured from ROM, RAM, or PROM or combinations of these memories.
The memory system can be expanded up to 3 2 K provided there is adequate current available from the power supply.
Each of the various memory options is discussed in the following sections.

SECTION 1
MR8-A READ ONLY MEMORY (ROM)

5.1 MR8-A READ ONLY MEMORY (ROM) DESCRIPTION
The MR8-A is a semiconductor memory option for the PDP-8/A. It consists of either 1 K, 2 K or 4 K X 12 data storage locations which are addressed in the same way as core memory locations. However, unless operated together
with a writable memory such as the MS8-A (RAM), it is a read only device.
A write capability is furnished by the MS8-A RAM memory. Special circuitry enables the MR8-A to utilize the write
capabilities of the RAM. Each of the 4 K locations in the ROM has an additional 13th bit, which when set to a logical 1, directs the access of a location in the RAM. Write type instructions have operands whose locations in the
ROM have the 13th bit set to a 1, specifying that the remaining 12 bits are to be treated as an address of a RAM
word.
Programming methods used with core memories can be adopted (without substantial alteration) to the ROM/RAM
combination.
The capacity of the MR8-A depends on the number of memory chips on the board. The normal complement is a 16
X 3 array of Silicon Gate MOS chips, each organized in a 256 words X 4 bit matrix. This constitutes a 4 K X 12
memory. In addition, 4 chips are required for the 13th bit. This standard configuration can be changed by removing
chips in 1K blocks.
Additional information on the memory chips is contained in subsequent paragraphs and in Appendix D .
The description that follows is divided into two parts: a general discussion with blocks of logic, such as address selection
and timing and control, and a more detailed description of the logic in each block.

5.1 . I M R8-A Physical Description
The MR8-A is a quad module (Figure 5-1) with four bottom connectors (A, B, C, and D) which plug into the Omnibus. In addition, it has four top connectors, three (F, H, and J), which are used for programming and one ( E l which
provides interconnection with the RAM module (M8311).
Figure 5-2 shows the arrangement of the ROM and RAM boards and the Omnibus.

5.1.2 MR8-A Specifications
The MR8-A specifications are listed in Table 5-1.
5.2 FUNCTIONAL DESCRIPTION
The MR8-A ROM memory performs three basic functions:
1.

ROM address decoding

ROM content accessing

When 13th bit is set, RAM addressing

CONNECTOR T O MS8-A
I F 13TH BIT MS8-A/MR8-A
ROMIRAM CONFIGURATION
IS USED

THESE THREE CONNECTORS ARE REMOVED
TO PROGRAM THE ROM, BUT T H E Y MUST
BE I N PLACE FOR NORMAL OPERATION

Figure 5-1

MR8-A ROM Memory Module ( M 8 3 l Z )

BUS

(USUALLY FIELD

EMA
BITS

0- 2

ROM

(OVER THE TOP)
-SCRATCH PAD ADDRESS
0-11. THE ADDRESS
LINES FROM ROM TO
RAM WOULD BE USED
FOR SCRATCH PAD WRT.
OPERATIONS. NO MEMORY
EXTENSION IS REWIRED
FOR THIS OPERATION.

THE ADDRESS BUS WOULD BE
USED TO ACCESS RAM AS
MAIN FRAME MEMORY

Figure 5-2

ROM/RAM Configuration

Table 5-1
MR8-A Specifications
Characteristic

Specification

Power Requirements for the 1024 Bit Chip
1 K size memory
4K size memory

Typical
+5Vk5%2A
+5V*5%5A

Memory Cycle Time
ROM (alone)
ROM-RAM (ROM cycle)
ROM-RAM (RAM cycle)

Worst Case
+5 V Â 5% 2.7 A
+5 V k 5% 7.4 A

1.5ps

1.6 ps
300 ns are added to the normal RAM cycle

Programming Method
Memory Capacity
Temperature
Environment
Testing

By external means (MR8-SA Programmer)
IK,2K or 4K
5to 5 0 C
Standard Computer Environment
The tape used in programming the ROM is utilized t o run the
diagnostics.

The major logic blocks and signal flow for accomplishing these functions are shown in Figure 5-3. The timing of the
signals during one memory cycle is shown in Figure 5-4. A list and definition of the signals used in the timing diagram are defined in Table 5-2.
A general description of the operation of the MR8-A based on the functional blocks, the connecting signal lines, and
the timing diagram follows.
Detailed descriptions of each of the logic blocks are presented in Paragraph 5.4.

5.2.1 Addressing
At TP4 the ROM memory register is cleared and a new address is placed on the Memory Address lines MACO11>.

The eight least significant address bits MA<4-1 1 are driven directly to the memory chip array of 16 columns by
three rows and are applied in parallel to each chip where they are decoded by the chip circuitry; one word out of
256 on each chip is selected.
The four most significant address lines, MA<0:3>, are decoded to select one of 16 chip columns. The addresses
can range from 0-400(8) (the first column) to 7377-7777(8) (the 16th column), i.e., from 0 to 4096(10).
The address select logic also determines whether the address is within the ROM's memory space in the larger 32K
computer memory. This is done by decoding the three extended Memory Address lines, EMA<0:2>. A signal FIELD
H is transmitted to the control logic when a valid address has been decoded.
5.2.2 Timing and Control
The basic timing is provided by the processor, which generates four time pulses (TP1-TP4), four time states (TS1TS4), and two memory control signals (MD DIR L and RETURN H). However, additional control and timing signals
are required by the MR8-A for the selection of one out of two modes of operation mentioned above, ROM or ROMRAM combination.

CHIP SELECT
MAO-MA3

FIELD H

(fl

-3

RAM A D D L

TIMING

MEM CLR L

ROM S E L L

TIMING
AND
CONTROL

NTS STALL L
MD DIR L

ROM STROBE H
RAM EN H
MD EN H

Â¥

MEM DATA
MD(0-11)

TO
RAM

MEMORY
REGISTER

CHIP ARRAY 1 6 x 3

RAMADDL

Figure 5-3

ROM Block Diagram

Table 5-2
MR8-A Signal Definitions
Description

Signal Name
RAM SEL L

An enabling signal for the RAM transmitted through the E Connector.

RMAO L - RMA11 L

Twelve RAM address lines leading to the RAM through the E Connector, and
equivalent to the MAO-MA11 lines of the Omnibus.

ROM STROBE H

Clocks ROM memory register contents onto the MD or RMA lines.

MEM CLR L

Clears ROM memory register.

FIELD H

Asserted when the memory field and memory size have been selected. Used to
enable the timing and control logic.

CHIP SELECT

16 signal lines, one for each column of three chips in the 16 X 3 memory array,
are selected by the address decode logic.

A gating signal generated in the control logic. Directs the register data to the MD
lines (ROM cycle).
RMA EN H

A gating signal generated in the control logic. Directs the register data to the RMA
lines (ROMIRAM cycle).

BMA (0-3)

Four signals derived from the corresponding MA <0-3>. Used to generate the
13th bit (Figures 5-3 and 5-7).

M D DIR L

MEM CLR L

T P4 H

A L

RETURNH

'TSI

FIELD H

STALL R E S E T

NTS STALL L

'TPI

----------

ROM STROBE L

RAM SEL L

100

200

300

400

500

600

'Omnibus Sianals
NOTE:

700

800

900

NAN0
SECONDS

If the 13th bit is set, RAM SEL L will be asserted and the
STALL L line will not be released at the end of STROBE L.
The NTS STALL line will be held by the MR8-A for
400-800 ns by which time the MS8-A will have asserted
NTS STALL and taken control of the cycle.

Figure 5-4

ROM Timing Diagram

The ROM chips have a fast enough access time ( 8 0 ns) t o be compatible w i t h the READ time and the total memory
cycle time provided by the processor. However, when operating with the RAM additional time is required, first because the R A M chips are slower, and second, because of the delays due t o switching from one circuit t o the other.
A longer memory cycle time must be generated. This involves disabling the normal processor timing and activating
another timing chain. The new timing chain is located on the RAM module, M 8 3 1 1. However, the circuitry for initially stopping the processor clock is part of the ROM module. This circuitry asserts NTS STALL and stalls the processor at the next time state. Besides the capability to initiate STALL, the circuitry can also override STALL and
return t o normal processor timing.

5.2.3 Input and Output Signal Definition
The MR8-A utilizes signals that originate in the central processor and in other modules of the PDP-8/A. In addition,
the ROM generates signals for the operation of the RAM. The Omnibus signals are as follows:
M A 0-11 L
M D 0-1 1 L
EMA 0-2 L
TS1 L
M D DIR L
NTS STALL L
TP4 H
ROM ADDR L
POWER OK H
RETURN H
The Omnibus signals are completely defined in Chapter 3.
Signals generated by the MR8-A are defined in Table 5-2.

5.3 PROGRAMMING
The ROM chips are programmed electrically using the fusible link technique. Initially all bits of the ROM are in the 0
state. Information is introduced by selectively programming 1s in the proper bit locations. In addition, the chips that
make up the 13th bit must be a 1 in each address location that is allocated for write operations in the ROM-RAM
configuration. That is, all locations that will be modified during the execution of a program must be flagged. In this
category are instructions requiring a write operation such as DCA, ISZ, and JMS, as well as locations used es autoindex registers, and those reserved for the programming of peripherals.
5.3.1 Programming Operation
In programming, the address selection is accomplished by means of the same decoding circuitry used in the read
mode, A high voltage is applied to the four output pins, the Vcc, and Chip Set 1 Sel 1 terminals, to physically alter a
fusible nichrome link. The voltage pulses are approximately 4 8 V. To isolate these from the board circuitry, the chip
contacts that are used during programming are brought out t o three top connectors (F, H, and J) using the fingers
on one side of the board only.
The connections to the board logic are made to the corresponding fingers on the opposite side of the board. During
normal operation, single width connectors join the contacts on both sides of the board. However, during programming, the connectors are removed and three cables from the programmer (blaster) are attached to the module. These
cables have special connectors that make contact with the fingers on one side only - the chip terminal side. Additional protection to the circuitry is provided by a series of switches that are opened during programming (Paragraph
5.5.)

5.3.2 Programming Procedure
The programming of the ROM involves generating a paper tape containing the ROM pattern and then writing this
pattern into the ROM using a computer controlled blaster. The MR8-SA blaster is a special facility available at Digital for programming simultaneously all the chips on the board. Detailed description of both hardware and software
aspects of this facility are found in the PDP-8/A Miniprocessor Handbook. However, a brief summary of the procedures used is included here to complete the presentation.

5.3.2.1 Preparation of the Paper Tape In the preparation of the paper tape, the locations requiring a write function are flagged. As an example, let one such instruction in the program (at location 200) be:
1.

20O/DCA 2 5 0

Write accumulator contents into Location 250.

250/(1) 1000

Location 2 5 0 in ROM is flagged. It contains RAM Address 1000.

2a.

250/DWRITE 1000

Assembler statement for tagging writable Location.

In a core program, line 1. would be all that is required. When using the ROM-RAM combination, both line 1. and 2.
are needed.
A patch has been developed for the PAL 8 assembler to transform core type programs into a format required by the
ROM-RAM combination.
The writable locations in ROM are tagged using the DWRITE statement. The RAM addresses are specified. The assembler then generates a paper tape in the format used by the MR8-SA ROM programmer, which will program the
appropriate 13th bits. The format for the MR8-SA tape is shown in the PDP-8/A Miniprocessor Handbook, Chapter
11. The 12-bit data word, in this case the address in the Read/Write memory, is punched as a normal data word,
but in the second line of the data word, hole 7 is punched to signify to the programmer that the 13th bit for this
address should be set.

5.3.2.2 Blasting - The paper tape is loaded into a PDP-8/A computer that operates the blaster. An 8K memory is
required. The entire board is blasted at one time instead of individual chips.
5.4 DETAILED LOGIC DESCRIPTION
The block diagram in Figure 5-3 should be used to understand the relationship between the blocks of logic and the
signals that are generated by these blocks. Table 5-2 defines these signals. All Omnibus signals are defi
in f Yapter 3.
5.4.1 Addressing Block Diagram Description
The addressing section of the M R8-A accesses 4096 separate memory locations in the standard ROM by means of 12
memory address lines (MA<O: 11 >) and 3 Extended Memory Address lines (EMA <0:2>),
In addition, one 4K field must be selected from among 8 using 3 EMA lines of the extended memory control circuit.
The 13th bit logic is closely linked with the address circuitry. The detailed block diagram of the address select logic,
Figure 5-5 shows these functions.
The eight least significant lines MA<4: 11
256 locations is thus selected.

> are decoded by a circuit which is an integraI part of the chip. One of

Address lines MA<0:3> are used to generate 1 6 chip enable signals that are routed to the 1 6 X array of chips.
Each of the 16 lines activates three chips arranged vertically on the board. Since each chip has 4 bits per word, a
12-bit word is addressed. The total number of words accessed is 256 X 16 or 4096.
The M R8-A field select switch settings are compared with the EMA inputs to select the field. Field size is decoded by
means of a similar circuit. The output of this field circuit is an enabling signal FIELD H which allows the selection of this
field of memory.

MA4

- MA11

CHIP

EMA2-

MA0

- MA3 -

1K
0R
2K
CHIP

CHIP

'4 LINES

SELECT

SEL
DECODE

-C S O - CS15

- BMAO- B M A 3

Figure 5 - 5

Detailed Block Diagram of Address Select Logic

5.4.2 Field and Size Selection
The MR8-A is a 1 K, 2K, or 4 K memory that can be located at any 4K boundary at a 32K memory array, i.e., it must start
at address zero of one of eight 4K memory fields. The field selection logic is shown in Figure 5-6.
Three switches (S2-6, S2-3, and S2-7) and a comparator circuit consisting of three Exclusive-NOR gates with their
outputs tied together decode the Memory Extension address on lines EMA<0:2>.
The output signal FIELD H is true only if each one of the inputs from the switch settings matches that of the corresponding EMA line, e.g., if EMAO is low, switch S2-7 must be closed. The output of the corresponding ExclusiveNOR gate is a high and all other switch setting inputs must similarly correspond t o their respective EMA line.
A table of memory fields vs switch settings is shown in Table 5-3.
Each Field has an address range of 4K. Field 0, as an example, is composed of addresses 0-7777(8). A full complement of 1 K chips on the MR8-A will start at address 0 and end at the 4K boundary of the field.
A similar arrangement of NOR gate comparators and switches selects the proper size. The t w o most significant address
lines M A 0 and M A 1 are utilized for this purpose.
The states o f these lines for the respective field sizes are shown in Table 5-4.
The switch settings that correspond to the states of M A 0 and M A 1 are shown in Table 5-5.

The memory size selection circuit and the field selection circuit constitute a combined five bit comparison network
shown in Figure 5-6 that generates FIELD H, which, in turn is gated to produce the enabling signal ROM ADD L.

SIZE S E L E C T

^
MEM S I Z E

EMA 1

S2-1

S2-8

S2-3

C= Closed ( S w i t c h is ON)
0 = Open ( S w i t c h is OFF)
X = D O N T CARE

F I E L D SELECT

Figure 5-6

Field and Size Selection

Table 5-3
Switch Setting to Select Memory Field
Field
S2-6

Switch Settings
S2-3
S2-7

0 = Open (Switch is O F F )
C = Closed (Switch is O N )

S2-5

Table 5-4
M A 0 and M A 1 States for Memory Field Sizes

ADDR Line

M E M Size

Logic 0 is HI
X = Doesn't Matter

Table 5-5
Switch Settings for States M A 0 and M A 1
M E M Size

S2-1

Switch
S2-8

82-5

C = Closed (Switch is ON)
0 = Open (Switch i s OFF)
X = Doesn't Matter

5.4.3 Chip Select Decoder
The address decoding circuit provides for the utilization of a 1K (256 X 4) chip. In the 1K chip, the 8 least significant address bits (MA4 to MA1 1) are routed directly to the chip.
The four most significant bits, M A 0 to MAS, are decoded to generate the 16 chip select signals CSO to CS15 for
the 16 X 3 chip array.
The decoding network is shown in Figure 5-7. Address lines MA0 to MA3 are routed via one side of the AND-OR
gates to two 4 to 8 decoders (IC7442) to generate 16 chip select lines. Each chip select line represents 256 words.
The address decoding scheme is shown in Table 5-6.
5.4.4 The 13th Bit
The same type memory chip is used in the 13th bit as in the other 12 bits of the memory array. However, the chips
are organized in a 256 X 4 matrix for a total of 1024 bits. To be useful as a 13th bit a transformation of the 256
X 4 into 1024 X 1 matrix is required. A 4 to 1 multiplexer, 1C 741 53, is used for this purpose as shown in Figure
5-8.
The M A 2 and MA3 lines are used to strobe the Multiplexer. The four combinations of the two lines and their corresponding address ranges are shown in Table 5-7.
The output of the multiplexer has an address range of 1K.

LEAST
;ANT

ONE OF
TWO
EIGHT TO
FOUR
DECODERS

ALWAYS OPEN

BMA 1

S4-3

Figure 5-7

Chip Select Decoding

Table 5-6
Address Decoding

Address Lines

MSB
0

Bit Value

2048

1024

512

256

128

(7442)

ADDRESS RANGE

MA 4

i
CHIP

0-3778

1000 - 13778

08-1188

Figure 5-8

Decoded on Chip

Decoded on one of two ICs

MA 11

13th Bit Mapping into 1 K X 1 Array

LSB
1

Table 5-7
States of MA3 and MA2 to Select an Address Range

'MA3Mp12

Address Range

To obtain a 4K address range (4K words one bit wide), four such Chip-MUX assemblies are used and the most significant bits M A 0 and MA1 are used (Figure 5-91.
The output of this configuration is 1 bit, the 13th bit, with an address range of 4K, which in turn is used as key control element of the ROM.

5.4.5 Timing and Control
The Timing and Control Logic of the MR8-A is shown in Figure 5-10. It contains two timing one-shots and two control flip-flops.
One timing element asserts NTS STALL L and the other generates the ROM STROBE signal which clocks the control flip-flops and the memory register.
Switch S6-1 grounds the 13th bit. All inputs to the control flip-flops are 0 and therefore the output is a ROM output. This switch permits isolation of the ROM during trouble shooting.
S4-7 is closed and S4-8 is opened when there is no writable memory, and ROM operates in the read-only mode.
The switch settings are reversed, S4-8 closed and S4-7 open when the mode of operation is ROM-RAM. A complete list of switch settings is found in Paragraph 5.5.

MAT

256 X 4

13TH BIT
4K X 1
0-7777

Figure 5-9

13th Bit Mapping into 4K x 1 Array

5.4.6 Timing Generation
The STALL one-shot has a delay of 6 0 0 zk 2 0 0 ns. It is triggered when the Omnibus signal RETURN H goes high
and is gated with FIELD H which is asserted when a valid selection is made by the memory field and size select circuits. STALL is asserted immediately and is maintained for the duration of the pulse 6 0 0 zk 2 0 0 ns unless overridden by a Reset generated in the STALL control flip-flop. The conditions for aborting STALL will be explained in a
subsequent paragraph that discusses the utilization of the timing pulses in the control scheme.
The STROBE one-shot is triggered at the same time as the STALL one-shot, i.e., when RETURN H goes high. The
pulse duration is 175 & 2 5 ns. The output is gated with FIELD H (for the same reason as is the STALL one-shot)
and inverted by the NAND gate E-18. A positive pulse used to clock the two control flip-flops and the ROM memory
register appears at the end of the timed delay.
5.4.6.1 Control Flip-Flops - The t w o control flip-flops shown in Figure 5-10 are used to generate the control signals. The D input to both is the113th bit and they are both clocked by the STROBE one-shot. The output, after inversion, of the lower flip-flop when the data input is high ( 13th bit = 1), is RAM SEL L. R M A EN H is asserted
gating the data to the RAM address lines. Both signals are used in the ROM-RAM cycle.
When the data input is a low (13th bit = 0) the output after inversion is RAM SEL H (not a RAM cycle) and MD
EN H is asserted enabling the M D lines routing memory data to the processor. The output of the STALL Control flipflop resets the STALL one-shot. When the data input is a low (13th bit = 0 ) and ROM ADD L is asserted the stall
reset permits ROM to continue operation in a read only mode while ROM ADD L disables other Read-Write memories, RAM among others.
5.4.6.2 Sequence of Control Operations - The sequence of the control operations is shown in the two timing diagrams (Figure 5 - 4 and 5-1 l).
Refer to the timing diagram in Figure 5-1 1. NTS STALL L is asserted at RETURN time regardless of whether it is ROM or
ROM-RAM cycle (point 1). At STROBE time (point 2), a decision is made whether t o continue or abort STALL. This
decision is made by the STALL control flip-flop in response to the 13th bit data input, if pin E24-5 is low resetting the
STALL one-shot (point 3). Simultaneously, M D EN H (Pin E24-8) is asserted (point 4). When it is a ROM-RAM cycle,
STALL is continued and RAM is selected.
5.4.6.3 Initial Conditions - It should be noted that initally the two control flip-flops are set in opposite states. The
STALL flip-flop is set (pin 5 high) during a RAM cycle. The other flip-flop is in the reset condition (pin 8 high) during a
ROM cycle. So both the ROM and RAM cycles are "armed." When the selection is made at ROM STROBE, one fires and
the other is disarmed. This is shown graphically in the timing diagram (Figure 5-1 1). This decision does not take place
instantaneously. Pulling and releasing NTS STALL requires a time delay of approximately 8 0 ns. The memory cycle then
is 1.6 u s instead of the normal 1.5 us.
5.4.6.4 Single Stepping - In the single step mode of operation, MEM CLR L is enabled. Initially this clears the
memory register and all register flip-flop outputs to the gates go to zero, enabling the M D or the RMA lines.
If it is a ROM cycle RAM SEL H is high at the beginning of TP4 and E l 5 asserts MEM CLR L (Figure 5-12); therefore, the
memory register will be cleared immediately.
The data on the M D lines comes from two sources, the ROM and RAM registers. The ROM register is cleared immediately to make sure that valid data is placed on the M D lines in case the current cycle is a ROM cycle. Should it
turn out to be a RAM cycle, the initial output on the lines will be 0s until the RAM data appears. Because of the
inherent delay in the RAM cycle no valid data will be lost.

ROM-RAM
FIF

{

-------

rSTALL

E24-9

R A M SEL

E24 8

H (ROM)
R M A EN H ( R A M )

E24-5

STALL CONTINUED BY R A M

STALL

-------

ROM SEL

SELECT R A M

- - - - - STALL ( R A M )
- - - - - - - STALL RESET (ROM)
L

STALL (ROM)

RESET

I
I

- - - - - - - MD EN

STALL 0IS

RAM SEL ( H I

I
1

RETURN H

01s
I
0

I
1 50

1
350

Figure 5- 1 1

NANOSECONDS

ROM-RAM Selection Timing

RAM SEL H

Figure 5-12 Single Step Operation

5.4.7 Memory Data and Memory Register
The first 1 K block of the 4K R O M memory shown in Figure 5-1 3 is typical of all 4 1 K blocks.
I t consists of:
1.

Twelve preprogrammed chips, arranged i n a 4 X 3 array

Address and chip enable inputs,

A memory output register that accepts the data content of the memory chips, and

Transfer lines t o the processor ( M D lines) and RAM memory ( R M A lines)

These are described in the following paragraphs. The physical layout of the chips on the board is shown in Figure 5-

14.

I
'BhT

LINES

RMA SEL H

cs3

1
7

BIT 1

11
11 '
BITS

cso

ADDRESS RANGE :
0 - 2 5 5 (0-377.)
ADDRESS RANGE:
2 5 6 - 511 (4008 - 7 7 7 8 )
ADDRESS RANGE:
512-767(10008-13778)

BITS
0-3

FROM
STROBE
FLIP/FLOP

CLR

Figure 5- 13

08-1192

Arrangement of 1 K Memory

BITS 8-11
BITS 4 - 7

Figure 5-14

ROM 4 K Memory - Physical Layout of Module

5.4.7.1 Memory Chips - The semiconductor chips are the storage elements of the ROM memory. Basically they can
be programmed electrically after they are mounted on a module. Three of the four top connectors on the module F, H, and
J, provide access t o circuit elements on the chips that can either be shorted or opened by the application of a high voltage
t o selected connector pins. This introduces eithera logical one or zero into the selected memory cells. Two techinques are
available for programming the memory chips after they have been mounted on the module: - fusible link and avalanching. In general, a high voltage or current pulse alters the internal circuitry of the chip providing either a new current path
or opening an existing one.
The individual chips are mounted o n sockets for easy replacement and reprogramming in the event of failure or error.

5.4.7.2 Address and Chip Enable Inputs - Eight address lines ( M A < 4 : 1 1 >) are decoded on the chip and select
one of 2 5 6 locations. The chip select lines select one of four chips in a 1 K block. Each chip is organized as 2 5 6
words by 4 bits. Three chips are required for a 1 2 bit word.
5.4.7.3 Memory Output Register - The memory output register consists of 1 2 flip-flops ( 7 4 1 75's) one for each
bit in the memory chip, i.e., four flip-flops per chip and 1 2 for each memory location. The output of the register is
routed t o the M D or RMA lines by the STROBE pulse described above.
5.4.7.4 Data Transfer Lines - Routing the memory register contents is controlled by the gating signals M D SEL
H and R M A SEL H which originate in the Control and Timing section. In the event M D SEL H is asserted the memory contents are placed o n the M D lines. When R M A SEL H is asserted the memory data is routed out on the RMA
lines.

The physical layout of the memory is shown i n Figure 5-1 3. I t consists of four 1 K
5.4.7.5 Physical Layout
blocks described in the preceding paragraphs. Each 1 K block consist of 1 2 chips arranged in an 4 X 3 array. The
least significant address is on the right and the most significant on the left. The four least significant bits are on the
bottom.

5.5 MR8-A SWITCH LIST
The following is a list of the settings for the various switches on the MR8-A: They are listed in numerical order for
easy reference. Switches are open for normal operation unless noted.
S1

SW1 - SW8

SW8

OPEN FOR PROGRAMMING
CLOSED FOR OPERATION
OPEN FOR PROGRAMMING
M E M SIZE - CLOSED FOR 1 K, OTHERWISE OPEN
ALWAYS OPEN
FIELD SEL - CLOSED FOR FIELD 2, 3, 6, 7
ALWAYS OPEN
M E M SIZE - OPEN
FIELD SEL - CLOSED FOR FIELD 1, 3, 5, 7
FIELD SEL - CLOSED FOR FIELD 4, 5, 6, 7
M E M SIZE - OPEN FOR 4K, OTHERWISE CLOSED

SW1 - S W 8

OPEN FOR PROGRAMMING
CLOSED FOR OPERATION

SW1 - SW8
SW1 - SW4
SW5 - SW6
SW7

OPEN FOR PROGRAMMING
CLOSED FOR OPERATION
TEST ONLY - CLOSED FOR OPERATION
ROM ADDR - CLOSED IF USED AS ROM
WITHOUT READ/WRITE MEMORY
STALL - CLOSED IF USED WITH
READ/ WRITE MEMORY

SW8

SW1 - SW8

OPEN FOR PROGRAMMING
CLOSED FOR OPERATION

SW1 - SW2

OPEN FOR PROGRAMMING
CLOSED FOR COMPLETE ROM COMPARE
OPEN FOR PROGRAMMING
CLOSED FOR OPERATION

S W 3 - SW8

OPEN FOR PROGRAMMING
CLOSED FOR OPERATION
OPEN FOR PROGRAMMING
CLOSED FOR OPERATION
OPEN FOR PROGRAMMING
CLOSED FOR OPERATION

SECTION 2
R A N D O M ACCESS MEMORY ( R A M )

5.6 SEMICONDUCTOR R A N D O M ACCESS MEMORY (RAM-MS8-A) DESCRIPTION
The Random Access Memory (RAM), MS8-A, is one of three types of semiconductor memories that are available for
the PDP-8/A. The others, the ROM (Read Only Memory), MR8-A, and the PROM, MR8-FB, are described in Sections 1 and 3 respectively.
1 0 X 8-1/2 inches in size. The basic building block is a
Physically the RAM memory is a quad module (M831 I),
static MOS chip which contains 1 K X 1 bit storage cells organized in a 32 X 32 (1024 bits) matrix. In addition,
address decoding circuitry is an integral part of each chip. Twelve of these building blocks comprise a 1 K X 12 bit
memory.
The memory size can be increased in increments of 4K up to 32K. However, power requirements listed in Paragraph
5.2.3 must be considered. Standard size MS8-A options are 1 K, 2K, and 4K.
The static MOS is inherently slower than the processor memory cycle of 1.5 us. The RAM Read/Write cycle takes
2.8 u s and a Read only cycle takes 2.4 us.
The RAM provides a Write capability for the otherwise Read only ROM. This is accomplished by indirect addressing,
.e., when certain ROM locations are addressed they point to (Go To) RAM. Details of the RAM-ROM combined operation are described in subsequent paragraphs.
Another feature is the ability of the relatively small RAM to operate in a large PDP-8/A memory field - as large as
32K. The addressing circuitry provides the capability of positioning the small RAM, 1 K to 4K, at specific locations in
this field. However, RAM cannot be in the same field as a core memory.
The RAM memory operates on 5 Vdc and draws approximately 3 A independent of its state of activity. Power must
be ON to preserve the programmed contents. Protection against momentary power failure is incorporated in the
power supply circuitry. A battery is used to supply power for the MS8-A when ac power is lost for short periods. Intervals of power loss up to 4 0 seconds can be tolerated, however, should longer power failures occur, the RAM program must be reloaded.
5.6.1 Physical Description
The MS8-A RAM memory is packaged on one standard quad module, the M8311. The four bottom connectors (A,
B, C and D) plug into the Omnibus. In addition, one connector (E) at the top provides interconnection with the ROM
module (M8312). The MS8-A module is shown in Figure 5-1 5.
The ROM-RAM configuration is shown in Figure 5-2.

CONNECTOR TO MR8-A
I F 13TH BIT MS8-AlMR8-A
ROMIRAM CONFIGURATION
IS USED

THESE CHIPS NOT
PRESENT ON M8311-YA

THESE CHIPS NOT
PRESENT ON ME311-YA
OR M8311-YB

Figure 5- 15

RAM MS8-A Module M83 1 1

5.6.2 MS8-A Specifications
The MS8-A Specifications are listed in Table 5-8.

5.7 FUNCTIONAL DESCRIPTION
The MS8-A RAM can operate in either of two modes: - As a mainframe memory or as an auxiliary write memory
for the ROM. The basic memory structure to implement the functions of address selection, timing and storage are
discussed in the following paragraphs.
The overall functional block diagram is shown in Figure 5-16. The blocks to the right of the Omnibus are located on
the M8311 module; those blocks to the left, such as ROM MR8-A, provide signal inputs to the RAM memory but
are not physically part of the M 8 3 1 1. The circuit elements on the module can be conveniently grouped on the basis
of their function into four major blocks:
1.
2.
3.
4.

Address Select Logic
Timing and Control
Chip Array
Memory Data.

By looking at the input and output signals of these blocks we can get an overview of their operations.

5.7.1 Address Select Logic
The Address Select logic performs many functions. First it establishes the mode of operation of the RAM; either
mainframe memory or an auxiliary write memory for the ROM - a ROM-RAM combination. The start of this selection is the signal RAM SEL L coming from the ROM. Second, it decodes the extended memory control field address.
A unique address of one out of eight 4K fields is contained in the 3 EMA lines (EMA<0:2>). The address logic compares the 3-digit code with the field assigned to the RAM which is contained in three switch settings. The RAM may
be in a different field than ROM and still be a scratch pad memory. Third, it selects, by comparing the settings of 2
switches with the two most significant address lines, MA(0: l)/RMA(O: I ) , the starting address at any 1 K boundary
within the 4K field. As an example a 1 K memory can be assigned address ranges 0-1 777(8), 2000-3777(8) etc., depending on the switch settings.
The results of a successful selection are the activation of the timing and control circuitry through MEM SEL L, and
enabling signals to the chip select circuitry, EN<0:3>.

Table 5-8
MS8-A Specifications
Specification

Characteristic
-

Power Requirements
1K
4K

Typical
5Vk5%1.4A
5Vk5%3.5A

Worst Case
2.4 A
4.6 A

Memory Cycle Time

Fetch State

All Other States

2.4 ps
2.7 ps

2.8 ps
3.1 ps

Mainframe Memory (RAM)
Scratch Pad Memory (ROM/RAM)
Memory Capacity

1K, 2K, 4K (expandable t o 32K)

Temperature

5 to 5 0 C

Environment

Standard Computer Environment

12 X 4 ARRAY

ENABLE

CONTROL

TIMING

NTS STALL L

CONTROL

MEM DATA
CLK

MEM DATA
MEMORY

MEMORY DATA
MEMORY

Figure 5- 16

MS8-A Block Diagram

5.7.2 Timing and Control
The timing network is the second major logic block of the R A M module. The inputs are the basic processor clock signals listed in Table 5-9, the M E M SEL signal from the address select logic and RAM SEL L. I t contains its o w n
clock and control logic which generate the timing and control signals for the read and write operations of the
memory.
The major problem is t o fit in a longer memory cycle than the normal processor cycle. This involves stopping the processor clock during the read part of the cycle by assserting NTS STALL L and starting the memory clock. When the
read operation is over, the RAM timing chain is deactivated and the processor clock is restarted. This is repeated during the second part of the cycle in all Major States except Fetch.

5.7.3 Memory Chip Array
The next major logic block is a 12 X 4 array of the 1 K chips. These are N-channel static M O S devices organized in
1024 words X 1 bit.
Each chip has 1024 cells, each containing six transistors. Two are cross-coupled and act as the storage element;
t w o function as loading elements similiar t o resistors; the remaining t w o are gating devices for addressing each separate cell in the matrix. In addition t o the memory array proper, the chip circuitry includes the following:

1.
2.
3.
4.

Address decoding
Sensing
Write
Chip enable logic.

Ten address terminals on the chip connect t o the 10 least significant address lines, M A (2-11 ) or RMA (2-1I), depending o n the memory mode, mainframe or scratchpad for ROM. The lines are arranged in groups of five t o select
the cells for either reading or writing into.

Table 5-9
MS8-A Signal Descriptions
Signal

Description

FIELD H

Asserted when a valid field selection has been made. Used t o enable the relative address
selection logic.

MEM SEL L

Asserted when a valid address has been selected. Used t o enable the MS8-A timing chain
and the control flip-flops.

MEM D A T A CLK

Clocks RAM memory register contents onto the MD lines.

CE L (3-0)

4 chip enable lines, one for each row of 12 chips that enable the chip logic.

EN (3-0)

4 outputs o f relative address ROM (1C 8223) corresponding t o the respective chip
enable lines.

5.7.4 Memory Data
The memory data logic implements the transfer of data into and out of the memory cells. This involves the memory
output register, timing signals from the timing and control logic, and an Omnibus signal, MEM DATA DIR L which
controls the direction of the transfer into or out of the memory cell. When the M D DIR L signal is low, the transfer
is out of the memory into the processor or a read operation. When the signal is high, the direction of data transfer is
into the memory out of the processor or a write operation. The M D lines carry data, processor instructions, addresses, and operands as welt as select and operation codes for I/O devices.
5.7.5 Operation
The sequence of events during the read part of a RAM cycle is shown in Figure 5-1 7.
The timing is shown on the left and proceeds from TP4 at the top starting the read cycle with a change in memory
address and ending at TP2 at the bottom when the CPU takes the memory data.
The sequence of events for the write cycle is shown in Figure 5-1 8.
When operating as a scratchpad memory ROM-RAM cycle there is an additional delay of 300 ns in the decision by
the ROM as to whether it is a ROM or ROM-RAM cycle (see Section 1 for details). The MS8-A timing chain is used
to time out this initial delay. After 300 ns, the timing chain is reset and the rest of the timing proceeds as in the
RAM cycle.
5.8 INPUT A N D OUTPUT SIGNALS
The following signals are defined in Chapter 3.
MA 0-1 1 L
MD 0-1 1 L
MD DIR L
TS1 L
TP1 H
TP3 H
SOURCE H

EMA 0 - 2 L
FETCH L
NTS STALL L
TS2 L
TP2 H
TP4 H
ROM ADD L

The RMA 0- 1 1 L and RAM SEL L signals are defined in Table 5-2.
The signals generated in the MS8-8A are defined in Table 5-9.

a
CHANGE MEMORY
ADDRESS

I
RAM SEL L

I
CHIP ENABLE

MEM SEL L

CLR MEM
REGISTER

TIMING

n
PROCESSOR
STALLS

.
CLOCK MEMORY
DATA

CLR MEM
DATA CLOCK
FIF

Figure 5-17

NTS STALL

TIMING

SHIFT REG.

Read Cycle Flow Chart

5.9 PROGRAMMING
The programming of the RAM when operating alone, as a read/write memory, is the same as for a core memory.
When operating in conjunction with the ROM, the programming involves a special procedure for programming the
ROM. This is described in detail in Chapter 11 of the Miniprocessor Handbook.
5.1 0 DETAILED LOGIC DESCRIPTION
The block diagram (Figure 5-16) should be used to understand the relationship between the groups of logic. You
should refer to flow diagrams in Figures 5-17 and 5-18 for the operation sequence during read and write operations.
A detailed description of the logic is presented in the next paragraphs in the following order:
1.
2.
3.

Address Selection Logic
Timing and Control Logic
Memory Data and Memory Register

NTS STALL
(FOR 2102-0
N O T 2102.11

B WRITE L

TO CHIPS

I
MS8-A
TIMING
ACTIVATED

PROCESSOR
STALLS
A T TP4
7

,
TP3 +
3 5 0 NSEC

RESUME
PROCESSOR
TIMING

CLEAR
NTS STALL

B WRITE L
CLEARED

I
TP4

CLEAR CHIP
SELECT

Figure 5 - 1 8

CLEAR MS8-A
TIMING

Write Cycle Flow Chart

5.10.1 Address Selection Logic
The address selection logic includes field selection, relative address and memory size selection.
5.1 0.2 Field Selection
Figure 5 - 1 9 shows the field selection logic. The first selection is made of a particular 4 K memory field by means of
the three EMA lines (EMAO to EMA2) which originate in the extended memory option on the K M 8 - A module. If the
K M 8 - A is not in the system, these lines are zeros, and field zero is selected. They select one of eight 4 K memory
fields.
The switches ( S 1 - 3 t o S1-0) can be set t o any digital code between 0 and 7. This number is compared with the
number that appears o n the E M A line by a 4-bit comparator circuit (1C 8 2 4 2 ) . Three bits decode the field number.
The 4 t h bit tests the enabling signal ROM A D D L for a high. If there is a match, the R A M memory recognizes its
o w n address and enables further processing b y generating a signal FIELD H.

TO CLK
MA OR RMA LINES

TO C H I P
ENABLE

SEE NOTE 3

+
&
*

L
-

:f2fD
SELECT
E2

EMAO -EMA2

+ 5-7

FIELDH

8223
E9
RELATIVE
ADDRESS
ROM

SEE NOTE 1

Figure 5 - 1 9

MEM S E L L

NOTES:
1. Sl-1 = E M A 2
S l - 2 = EMAl
S l - 3 = EMAO
2. S l - 4 z S E L O
Sl-5zSELl
3. S l - 6 = 4 K
Sl-7*3K
S l - 8 ~ 2 K
Sl-9zlK

Address Selection Logic

5.10.3 Starting Address
The R A M memory is usually relatively small in comparison t o total computer memory space. Furthermore, i t is a specialized memory and i t is important t o conserve as much o f its space as possible. One means of doing it is t o use a
reference. Address and program the R A M memory relative t o this reference. As an example, memory address
5 2 7 3 ( 8 ) can be divided into t w o parts 4 0 0 0 ( 8 ) 4- 1273(8). The reference part of the address, 4000, can be a
switch setting and only the relatively small number 1 2 7 3 ( 8 ) need have a R A M location. However, additional logic is
required t o subtract the reference from the total address. The small ROM (IC 8 2 2 3 ) is programmed t o perform this
subtraction. The truth table is shown in Figure 5-20.
The inputs t o the ROM (IC 8 2 2 3 ) include, besides the ORed FIELD H and R A M SEL H signals, the t w o most significant bits of the address, M A <O: 1 and t w o lines from the switch references, SEL 0 and SEL 1. The logic in the
ROM automatically subtracts the switch reference address from the total address and generates the four signals,
EN<0:3>, that are routed t o the chip enable lines CE<3:0>. They, i n turn, enable four rows of 1 2 chips each. The
AND-OR gating of M A , RMA, and R A M SEL L o n the input side o f the ROM selects the operating mode, either
main memory or scratchpad memory t o the M R 8 - A ROM.

5.10.4 Memory Size Selection
On the output side of the ROM IC are four rrbemory size selection switches, This size selection o n the output side
must be compatible with the reference selection on the input side. The truth table for the ROM shows the compatible memory size.
Referring t o the above example and using the truth table (shaded portion), note the following:
Address 5 2 7 3 ( 8 ) falls in the range of addresses 4 0 0 0 - 5 7 7 7 ; M A 0 is 1 and M A 1 is 0 . For a starting address of
4 0 0 0 ( 8 ) SEL 0 is 1 ( S l - 4 is open) and 'SEL 1 is 0 ( S l - 5 is closed), The output is EN0 enabling the first r o w of
chips, since only a 1 K memory is required for the difference between 5 2 7 3 and 4 0 0 0 ( 8 ) which is 1 2 7 3 ( 8 ) .
Finally, a compatible memory size is either 1 K or ZK, i.e., closing either switch S 1 - 9 or S 1 - 8 will assert M E M SEL L.

W I T C H OFF=$
S1.4 S1.5

OUTPUT
..

INPUT

STARTING

FIELD

ADDRESS

SELECT
14

REF SELECT
SELO
13

SELl
12

INPUT ADDRESS
MA0
11

PIN NO.
ADDRESS

CHIP ENABLE
EN3 EN2 EN1

1
EN0 1 4 K

SWITCH SELECT
3K
2K
1K
SELECT
-ZEROS
ONLY

Figure 5-20

ROM (lC8223) Truth Table

5.11 T I M I N G AND CONTROL LOGIC
The RAM operations are controlled by timed signals which originate in the central processor and in the MS8-A timing chain. The processor timing chain generates four time states, TS1 to TS4, and four time pulses, TP1 to TP4. In
addition, the following signals are utilized:
1.
2.
3.

SOURCE H,
B WRITE L
MEMDIRL.

For a complete list of all signals see Table 5-9.
In addition, the slower RAM memory contains an a8uxiliarytiming chain which operates in conjunction with the processor main timing in the following manner. The processor clock is stopped during the read portion of the memory
cycle. I t is also stopped during the write portion of the memory cycle, provided the processor is not in the FETCH
state. The MS8-A timing is started as the main clock is stopped. When the operation is completed (either read or
write), the auxiliary timing chain is disabled and the processor timing is resumed.
The timing is further modified when the memory operates in combination with the ROM, the ROM-RAM mode. To
compensate for the additional time required, for the settling of the address signals originating in the ROM there is a
3 0 0 ns delay. For details refer to Section 1.

5.1 I.I M S 8 - A Timing Chain
The main components in the MS8-A timing chain shown in Figure 5-21, are the ten MHz crystal clock, a Serial lnParallel Out shift register, and two synchronizing flip-flops. The shift register can be visualized as a tapped delay line
except that the intervals are very accurately t~med.The data entered at the input shifts at each clock pulse progress
from RO to R8 for a maximum time span of 8 0 0 rbs, divided into 8 discrete 1 0 0 ns intervals. Each clock pulse advances the input one interval.
The shift register clock controlled by the logic is allc)wed to start and stop. It can be reset after the completion of the
timing of one event and be started for the timing of another. I t should be noted that the output of RO is fed back to
the reset of the synchronizing flip-flops. The result of this arrangement is that only one 1 bit is advanced along the
register, the rest being 0s.

E l2

R7
R6

El2

-c

TO O T H E R
FUNCTIONS

R4
R3

R2
R1

SER I N

R0
CLR

CLK

?
'

CLK L
A

MEM SEL L
RAM SEL L

TO O T H E R
FUNCTIONS

Figure 5-21

Memory Timing Chain

The shift register outputs are connected to control flip-flops that, in conjunction with other gating signals, enable the
memory chips at the proper time and clock the contents of the memory into the memory output register. In addition,
they disable the main clock and assert NTS STALL L. After a selected interval, the main clock is restarted, and NTS
STALL L is negated.

5.11.2

Operation of a RAM Cycle

5.1 1.2.1 Read Cycle - Figure 5-1 7 is the timing diagram for the detailed logic shown in Figures 5-22 through 526. The read cycle is started at TP4 and the synchronizing flip-flops and the shift register are cleared, initializing the
timing chain. In addition, the chip enable control flip-flop is cleared. A t SOURCE time, (SOURCE H is generated approximately 2 0 0 ns from TP4 HI, the memory register is cleared assuring a high to low transition on the M D lines.
In addition, the STALL and CHIP ENABLE flip-flops are clocked. If there is a valid address, STALL L is asserted and
the CHIP ENABLE signal is routed to the memory. The processor stalls at time TS2 and the timing chain of the
MS8-A controls the remainder of the read cycle.
The control elements involved are the memory data clock and the STALL control flip-flops shown in Figure 5-26. At
the expiration of a time interval, 8 0 0 ns, the signal MEM DATA CLOCK is generated and NTS STALL is cleared, restarting the processor timing. A t TP2, the processor takes the memory data. The shift register and memory data clock
flip-flops are cleared completing the read operation.

CLOCK H

LAST PULSE
OF SHIFT REG

MEM DATA
CLR H

STALL

350"s

+ 4 0 04ns 08-1182

Figure 5-22

Read Cycle Timing Diagram

+3v u
,

cE TO CHIP
SELECT

Tp4(cJ2)D-T@
MMl TP4 L

M M l PWR OK H

CLEAR C H I P
ENABLE

3V-D

E 12

El2

1 ,

0
4 CLR

El3

CLEAR TIMING
CHAIN

Figure 5-23

TP4 Logic

CHIP ENABLE

T
T
I

N T S STALL L
ROM
RE L
ADDR
E22B

MEM SEL H

Figure 5-24

Source Time Logic

5-32

Figure 5-25

sw-10

MMl TS2 H
MM1 MEM SEL H

Operations at TP1

P W R OK H
BACK EDGE
OF T P 2

MEM DATA CLK H

<rPL

NOTE;
Jumpers w l a W 4 select
400 nsec ( 2102-1)
or 800 nsec (2102-0) chips.
08-1206

Figure 5-26

Stall

+ 4 0 0 ns Logic

5.11.2.2 Write Cycle The flow chart and timing diagram are shown in Figures 5-1 8 and 5-27 and the logic dia-t
gram in Figure 5-28. The write cycle starts on The trailing edge of TP2 which clocks the STALL and B WRITE L flipflops (Dual E l 1 ). The data inputs to both flip-flops are high. If the signal F L is high, indicating a write operation, the
outputs of the flip-flop are high. The output of the inverter asserts NTS STALL L and B WRITE L respectively.
NTS STALL L is pulled during time state TS3 by the trailing edge of TP2. During time state TS4, the PDP-8/A stalls
and the MS8-A timing chain takes control. 350 ns after TP3 and STALL, NTS STALL is cleared and the main processor timing is resumed. The write control flip-flop is cleared 100 ns later. At TP4, the MS8-A timing chain and
chip select are cleared, completing the entire memory cycle.

5.1 1.3 Operation of a ROM-RAM Cycle
When the RAM operates in conjunction with the ROM, there is an additional delay due to the decision by the ROM
whether it is ROM only or a ROM-RAM cycle. During this decision time of approximately 3 0 0 ns, the 13th bit is
read and appropriate circuits are enabled. (See the ROM description in Section 1 for greater detail.)
There are two events which have to be timed - the RAM read cycle, which has been described above, and the selection of RAM by ROM, which precedes it.
The MS8-A timing chain times out this additional decision delay and at the end of 300 ns resets the shift register.
The timing chain is restarted and times out the RAM read cycle. The timing chain is therefore activated twice during
the read portion of the ROM-RAM memory cycle. The additional logic is shown in Figure 5-29 and the timing diagrams are shown in Figures 5-30 and 5-31. The operation is as follows (Refer to Figure 5-30 and 5-31 ) .

TIMING
CHAIN

1
F I R S T PULSE

1
I

-4 0 0 ns ,Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘1+-Ã‘Ã‘

3 5 0 nÃ

1
I

Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã

STALL

*Omnibus Signals

Write Cycle Timing Diagram

Figure 5-27

MEM SEL H

MM1 CLK

NTS STALL L

I - - ~
' ~ D
Ell
7474

R3
E 13

-c 3

SER
IN

?
3 5 0 msec AFTER T P 3

9
D

B WRITE L

E l1
7474

*TP~H(CE~)
MMt

MM1

cLKb
[
4 5 0 nsec AFTER T P 3

MEM DATA CLK

MM1 MEM SEL H
7474

* T P 2 - CLRS SHIFT REGISTER
BACK EDGE OF T P 2 ASSERTS STALL

Figure 5-28

Write Cycle Logic

T I M E I N NANOSECONDS

SOURCE H

STALL L

RAM SEL L

I
1

MEM SEL L

CLOCK H

E 13-9 1CLR

NOTE 1. 'STALL L' is asserted first (at SOURCE time1 by the ROM
memory, and is asserted at 'RAM SEL L' by the MS8-A.
From the second positive transition on â‚¬12- the memory
cycle is the same as a normal ReadIWrite Cycle.

Figure 5 - 3 0

ROM-RAM Initial Delay Timing Diagram

A t TP1 the synchronizing flip-flops are clocked. TS2 L follows at about the midpoint of the TP1 pulse. The RAM SEL
L signal appears at the input t o E19. The data input t o E l 6 pin 2 turns low. On the second clock pulse, a high appears at the input of the shift register. A t the third clock pulse, RO is high and E l 6 is clocked. A t the fourth clock
pulse, both inputs t o the NAND gate E4 are high. The output of E4, after inversion, clears the shift register and sets
the synchronizing flip-flop. This completes the first timing operation. The second timing operation n o w begins. This
time the shift register is not reset at R1 since the data output of E l 6 is a low. The result is that the timing proceeds
as in the previous cycle.

RAM SEL L

Figure 5-31 Detailed Timing of Initial Delay in ROM-RAM Cycle

5.1 1.4 Memory Data and Memory Output ~ e ~ i k t e r
A typical 1 K memory that consists of 12 1 0 2 4 X 1 chips is shown in Figure 5-32.
The ten address input terminals (A<0:9>) are connected to either the M A or RMA lines by the gating circuitry. The
RMA lines (RMA2 - RMA1 1) are selected when RAM SEL H is true. Two control inputs are available on the chip:
Chip Enable and B WRITE L, in addition to the data input and output terminals. (Terminals 11 and 12 respectively.)
The output data of the 12 chip array during a read operation is routed to a bank of 12 "D" type flip-flops. Their output in turn is gated with the Omnibus signal MEM DIR L, which directs the memory data onto the M D lines. This
occurs when the flip-flops are clocked by the signal MEM CLR L. During the write portion of the memory cycle the
chips accept data from the M D lines. When the control signal B WRITE L is true and MEM DIR L goes high.

5.12 SWITCH DEFINITIONS
The switch functions and settings are defined in Table 5-1 0.

(:
N

a Q

S St.

Table 5-10
MS8-A Readmrite Memory Switch Settings
S1-1, 2, and 3

S1-4 and 5

Field Selection
S1-1

S1-2

S1-3

Field Selected

ON
OFF
ON
OFF
ON
OFF
ON
OFF

ON
ON
OFF
OFF
ON
ON
OFF
OFF

ON
ON
ON
ON
OFF
OFF
OFF
OFF

0
1
2
3
4
5
6
7

S1-4

S1-5

First Address in this RAM

ON
ON
OFF
OFF

ON
OFF
ON
OFF

First Address

ON for 4K Memory M8311-YD, OFF for 1K or 2K
OFF
ON for 2K Memory M8311-YB, OFF for 1K or 4K
ON for 1K Memory M8311-YA, OFF for 2K or 4K
Test switch, normally ON

SECTION 3
MR8-FB REPROGRAMMABLE READ ONLY MEMORY (PROM)

5.13 M R 8 - F B 1K M E M O R Y
The MR8-FB (Figure 5-33) is a memory option for PDP-8/A computers. It is used in applications where 1. non volatility of a program's instructions is desired, and 2. less than 2 5 6 writable locations per 1 0 2 4 locations are required
for program execution.
The MR8-FB contains t w o semiconductor memory element types: reprogrammable read only memory and bipolar
random access read/write memory. For the purpose of simplicity in this manual- these memory elements will be referred t o as PROM and RAM respectively.
When 13th bit=O, DATA Out = PROM DATA and RAM is not accessed
When 13th bit= 1, DATA Out = RAM DATA and PROM DATA = RAM Address
The PROM section of the MR8-FB is organized as 1 0 2 4 13-bit words. Once loaded, the content of the PROM is permanent unless the PROM chips are exposed t o an intense source of ultraviolet light.

EMA0-â‚¬M

AND MA0-MA11

1~ x 12 BIT
@

PROM DATA

PROM

&?:;

SWITCH

Ã Ã
ADDRESS

RAM DATA

RAM

NOTES
When 13th Bit = 0 DATA OUT is PROM DATA and RAM
is not accessed. When 13th Bit = 1, DATA OUT is RAM
DATA and PROM DATA is RAM ADDRESS.

Figure 5-33

Simplified M R8-FB Block Diagram

The RAM section is organized as 256 12-bit words. The PROM is accessed at the address applied to the memory
address bus. The data out of the PROM is gated onto the memory data bus or applied to the address inputs of the
RAM. The path activated is determined by the state of the 13th bit of the PROM word. Although the PROM is accessed in all cases, any 256 locations of the PROM may be defined as read/write.
Other characteristics of the MR8-FB are as follows:
Physical - M8349 quad size module
System Memory Space - Each MR8-FB in a system occupies a 1024 (2000(8)) word block. The location of this
block within the 32K of available memory space is defined by the user via diode placement.
Program Startup - The user has the option of program start at relative location 0 or 2 0 0 of the MR8-FB. When enabled by the installation of a jumper, the start-up logic is activated by the BOOT switch or key on the front panel.
Battery Backup for RAM - Connectors are provided to supply the RAM only with power if power is lost to the rest
of the system (RAM loses data when power is removed.)

5.13.1

M R8-FB Specifications

Power Requirements

Characteristic

Specification
i - 5 V @ 3.8 A - 15 V @ 3 5 0 mA

Memory Cycle Time

3.7 p s

PROM Erasure Method

Ultraviolet Light

PROM Program Loading Method

By External Programmer (MR8-SL)

Memory Capacity

1 K of PROM with 256 words of ReadNrite Memory (RAM)

Operating Temperature
Testing

Two diagnostic programs, Internal Test (loaded
into the MR8-FB) and PROM Diagnostic are
supplied to check the MR8-FB. PROM diagnostic
is supplied on paper tape and runs in additional read/write

memory
to verify the contents of the M R8-FB
corresponds to the users papertape.

NOTE
The data tape used to program the MR8-FB must be
available to run the diagnostic.
5.13.2 MR8-FB Description
Figure 5-34 is a detailed block diagram of the MR8-FB. The functional groups of logic shown in Figure 5-34 are discussed in the following paragraphs.
5.13.3 Address Decoder
The Address Decoder contains address select diodes that can be arranged to assign a 2000(8) block of addresses to
the MR8-FB. When EMAO-EMA2 and M A 00-MA 11 are applied to the select diodes in the correct states, MCL
FIELD L is asserted to indicate that the MR8-FB is selected by the program. Also included is the Field Selection
Decoder, which, by using three jumpers, selects the field where the PROM program will run.

ROM04

RO M

M C L FIELD
r

<>
Â
¥
-

MCL FIELD

(WRITE)

MD DIR L
MDOO-MDll

2 5 6 WORD RANDOM
ACCESS MEMORY (RAM)
READ/ WRITE

R A M WRT EN

TP3

RAM
ADDRESS ROM04-ROM 11
ENABLE
(RAM ADDRESS)

WRITE
* DECODER

- ROM 11

DATA 0, DATA1, DATA4, AND DATA6-DATA 11 (ADDRESS)

LATCH

% SW START SIGNALS

ADDRESS

~ ~ 0 0 DECODER
-

MEMORY CONTROL MCL ENABLE
LOGIC
START ADDRESS

(1 ) STALL DELAY
(2) SW START
LOGIC DELAYS
TOGENERATE
PROCESSOR
CONTROL
SIGNALS

POWER OK H
RUN H

MEMORY
FIELD
AND
STARTING

F i
MCL ENABLE

RAMOO-RAM11

ROM

ROMOO-ROM11

NTS

EMAOEMA2

I NIT

DATA
MULTIPLEXER

(READ)

I-

ADDRESS
SELECT

1K WORD REPROGRAMMABLE
READ ONLY MEMORY
(PROM)

DISO

1*
NTS S T A L L L

BMA02

13BIT=1

4 TO 1
MULTIPLEX
SELECT
A

-BMA03

% The SW s t a r t signals are PULSE L A , MEM START,
MS. DIS, L A EN, K E Y CONT. These s i g n a l s a r e
explaned i n TABLE 9 - 4 of the S M A L L COMPUTER
HANDBOOK - 1972

Figure 5-34

1 3 B I T PROM

MR8-FB Block Diagram

ROM

5.13.4 Starting Address Decoder
The Starting Address Decoder is used to start a program whose starting address is location 000(8) or 200(8) of any
1 K memory in any memory field when BOOT on the Programmer's Console is pressed twice or BOOT on the Limited Function Panel is raised and then lowered.
5.13.5 Bootstrap Operation
When BOOT on the Programmer's Console is pressed twice or BOOT on the Limited Function Panel is raised and
lowered, the PROM initializes the CPU, loads a starting address, selects a memory field, and starts the program at
the address and field specified by the Starting Address Decoder. Figure 5-35 is a timing diagram for the Bootstrap
operation. The M R8-FB signals used in this and other timing diagrams are explained in Table 5- 1 1, When BOOT is
activated the PROM must:
1.

Initialize the CPU.

Load the starting address of the program, determined by jumpers (ST AD) on the board.

Load Extended Address (Memory Field), determined by by jumpers (EMA) on the board. The instruction
and Data Fields are connected together so both are enabled with one jumper.

Start the Program.

The BOOT feature may be used only on one MR8-FB and only if another option that uses BOOT Start is not installed on the Omnibus. The BOOT function is selected by the installation of the DIS jumper in the memory control
logic of the M 8 3 4 9 module.

5.13.6 Memory Control and Timing Logic
The memory control logic generates the necessary control signals to initialize the CPU and start a program at the
specified starting address during BOOT operations. It also produces the timing signals required for memory
operation.
5.13.7 Read or Read/Write
During a read operation the contents of the PROM memory location addressed by the program are applied to the
M D lines to be read into the processor. The timing diagram in Figure 5-36 assumes that the 13th bit is 0 and the
contents of the addressed PROM location are applied to the M D lines.
When the 13th bit is a 1, the 8 least significant bits (04-1 1 of the PROM output) are used as an address rather
than an operand to point to a read/write location in the 256-word RAM. Figure 5-37 shows the timing required for
this operation. The type of operation (read or write) is determined by the operand in the R A M I( 'cation addressed by
PROM or by an operand in PROM that writes in this location.

5.1 3.8 1K PROM
Figure 5-38 is a block diagram of the 1 K FROM. Only 2 5 6 words are shown in the diagram. A 256-word, 12-bit
PROM ( 1 2 X 2 5 6 ROM matrix) is formed by one 2 5 6 word, 8-bit ROM and half of one 2 5 6 word, 8-bit ROM. Using
six ROM chips in this way produces 1024 12-bit words of PROM. This is done by selecting one chip and either the
upper or lower half of another chip for each read operation (Figure 5-39). As an example, if memory location 0 0 0 0
is selected, E26 and the lower half of E50 are enabled.
5.13.9 13th Bit P R O M
The 13th bit PROM chip provides the additional bit for each of the 2000(8) locations in PROM. If this bit is set to 1,
the contents of the PROM location addressed by the program are used to select a location in readlwrite memory.
The 13th bit is not seen by the processor or program.

SW START

A-4

DL 1

--I.-l+

PWR OK H

INIT

DLY 2

\-.

EN ST ADD

INDI LA EN
MS IR DIS

\-.

\
\

\-.

DLY 3

DLY 4

PULSE LA H

EN EMA

MEM START

RUN

I I

*LD

-LD

EMA

+
1

Figure 5 - 3 5

Bootstrap Operation Timing

5.13.1 0 R O M Address Flag
The ROM Address flag is always disabled o n the MR8-FB. Y A I should never be installed. This is used o n some configurations o f PROM that are in the same field as core memory.
5.13.1 1 ReadIWrite Memory ( R A M )
The R A M is composed of twelve 256 X I-bit chips. When the 1 3 t h bit of a PROM location is set, the 8 least significant bits o f PROM i n that location are used t o address the R A M . The contents of R A M are then applied t o the M D
lines instead o f PROM. The output o f R A M is selected when ROM L i s made true by the 1 3 t h bit.
To write in a R A M location R A M M D DIR H must be asserted t o generate a WRITE EN. If WRITE EN L is asserted,
data o n the M D lines is written into the R A M location addressed by PROM, at TP3 time.

Table 5-1I
MR8-FB Signals
--

- p

Description

Signal
DLY 1

DLY 1 (Delay I ) is a one-shot multivibrator that ouptuts a 3 ms pulse when BOOT
on the Limited Function Panel i s pressed and raised, or BOOT on the Programmer's
Console is pressed twice. This pulse sets the MCL GO flip-flop and pulls PWR OK
low to start the timing and generation of CPU signals required to load the starting
address and tnemory field from the Starting Address Decoder.

DLY 2

D LY 2 (Delay 2) is a one-shot multivibrator that outputs a 100 ns pulse on the
trailing edge of INIT H when MCL GO i s set (1). This pulse sets MCL LA, clears MCL
KC, and triggers DLY 3 on the trailing edge. This enables the following signals to be
applied to the Omnibus:
*MS If3 DIS L
*LA EN L
*IND '1 L
*KEY CONT L
MCL EN ST ADDR H is then asserted to apply the starting address to the Omnibus.

DLY 3

DLY 3 (Delay 3) is a one-shot multivibrator that i s triggered by the trailing edge of
DLY 2 to generate a 250 ns pulse. The 0-side of DLY 3 is applied to DLY 4, which
is triggered on the trailing edge of this pulse. This is used to separate the setting of
levels from the pulse that loads these levels into the processor.
DLY 4 (Delay 4) is a one-shot multivibrator that is triggered on the trailing edge of
DLY 3. This delay, along with DLY 3' is triggered three times in the timing cycle.
Twice DLY 4 produces PULSE LA L and the last time it produces MEM START L.

EN EMA H

EN EMA H (Enable EMA) is asserted a t DLY 3 time when MCL GO (11, MCL KC
( I ) , and MCL. LA (1) are asserted. This puts the field select bits on the Data Bus, so
that a t the next PULSE LA, it i s strobed into the processor.

EN ST ADDR H

EN ST ADDR H (Enable Starting Address) is asserted a t DLY 2 time when MCL GO
( I ) , MCL KC (01, and MCL LA ( I ) are asserted. This puts the starting address on the
Data Bus, so that a t the next PULSE LA, it is strobed into the processor.

INIT*

INIT (Initialize) is asserted if PWR OK H i s asserted to clear all flags, the Act and
the interrupt and break systems.

IND I*

IND 1 is asserted low a t the same time as LA EN L to ensure that only the data lines
are on the Data Bus when the starting address is transferred during SW operations.

KEY CONT L*

KEY CONT I- is asserted by the MR8-FB to generate STOP L, enable loading of the
EMA, reset the RUN flip-flop, and disable the interrupt system.

*These signals are defined in detail in Chapter 3,

Table 5-11 (Cont)
MR8-FB Signals
Description

Signal
MCL GO H

The MCL GO flip-flop is set by a DLY 1 pulse when BOOT on the Limited Function
Panel is pressed and raised or BOOT on the Programmer's Console is pressed twice.
This signal enables the gates required to apply starting address, memory field, and
CPU control signals to the Omnibus.

MEM START L*

MEM START L is grounded prior to TP2 time to initiate a memory cycle. Memory
cycles are continued until STOP is set.

PULSE LA H*

PULSE LA H is asserted twice during a SW operation to transfer the contents of the
Data Bus to the CPMA Register. The Data Bus contains the starting address one time
and the EMA bits the other time.

PWR OK H

PWR OK H (Power OK) is normally negated (low) by the power supply output dropping below a predetermined level to initialize and stop the processor. In the MR8-FB,
PWR OK H is negated during a SW operation to initialize the CPU.

RAM 00 - RAM 11

RAM 00 - RAM 11 is the 12-bit output of the readlwrite memory location which i s
addressed by a location in PROM and applied to the MD lines if the 13th bit a t that
PROM location is set.

ROM 00- ROM 11

ROM 00 - ROM I 1 is the 12-bit output of PROM when a memory location in
PROM i s addressed by the program, If the 13th bit is set to 1, ROM 04 - ROM 11
are used to address a location in RAM.

RAM MD DIR H

RAM MD DIR H i s asserted by MD DIR L from the Omnibus to generate RAM WRT
EN. RAM WRT EN is applied to the RAM chips to enable data on the MD lines to
be written into RAM.

RAM WRT EN

RAM WRT EN L is asserted to enable the write input to all RAM chips during a
write operation. This signal is controlled by RAM MD D l R L whose state is determined by MD DIR L from the Omnibus, and by TP3*.

RETURN H*

RETURN H is asserted during a read or write operation. I t is used in the MR8-FB
during the read part of a cycle to trigger the NTS STALL one-shot multivibrator.

ROM ADDR L

ROM ADDR L is not used on the MR8-FB.

ROM L

ROM L is the output of the 13th bit multiplexer. I t is used to select the output
(ROM 00 - ROM 1Ior RAM 00 - RAM II)
to be put on the MD lines. It also
enables RAM for a write operation.

NTS STALL L

NTS STALL L i s asserted for 2.2 ps to allow time for access to PROM memory and
for data to settle on the MD lines. The trailing edge of NTS STALL L is used to
clock ROM 00 - ROM IIor RAM .OO- RAM IIout of the Data Multiplexer and
onto the MD lines during a read operation.

*These signals are defined in detail in Chapter 3.

Table 5-11 (Cont)
MR8-FB Signals
Description

Signal

sw*

SW is asserted (low) when BOOT is activated t o start the timing sequence which
loads the starting address. Note the SW D I S jumper must be installed t o use this
feature witti the MR8-FB. BOOT on the Limited Function Panel must be pressed,
then raised, or BOOT on the Programmer's Console must be pressed twice t o start
the SW start timing cycle.

*These signals are defined in detail in Chapter 3.

MEM STITP4

TP 1

TP2

TP3

RETURN

N T S STALL L

MEM TO MD

ROM DATA

READ FROM RAM

ROM L

-+7

RAM DATA

Figure 5-36

Read Timing

5.13.1 2 Data Multiplexer
The Data Multiplexer selects either ROM 00-ROM 11 or RAM 00-RAM 11 to be applied to the M D lines during a
read operation. ROM L is asserted if the 13th bit is a I to select RAM 00-RAM 11. If the 13th bit is 0, ROM L is
negated and ROM 00-ROM 11 is applied t o the M D lines.
5.14 M R 8 - F B PROGRAMMING
The PROM chip is an ultraviolet (UV) erasaktle device. Seven PROMS provide the 1 K X 12 plus 1 K X 1 bit storage.
The programming pulses needed are of high (35-48 V) amplitude. To isolate these from the TTL logic, all pins of the
PROM chips are brought out to top fingers on the 1-side of the module. The TTL levels associated with the normal
PROM functions are brought to the corresponding fingers on the 2-side. In normal operation, single-width top connectors join the 1-side to the 2-side of the module. To program the PROM, the top connectors are removed and four
cables are connected to the fingers instead. These cables make contact with the 1-side only and are interlocked to
prevent application of destructive voltages if the cables are plugged in incorrectly.

The PROM, when erased, contains all 0s. When programming the PROM, ones are inserted where needed. The 0
can be put in only by erasing the whole PROM. The PROM is reprogrammable a minimum of 1 0 0 times.

R/W

TPl

1 3 ' ~B I T

2 .zP6
II

NTS STALL L

M E M T O MD

RAM MD D
\ I\R- .

\ MB T O MD

,
RAM WRT ENL

RAM DATA

Figure 5-37

BMAO2 BMAO3
MA 0 4 L

MA 11 L

INPUT
DRIVERS

13th Bit Readmrite Timing

ADDRESS
DECODER

Figure 5 - 3 8

PROM
MATRIX

PROM Block Diagram

OUTPUT
BUFFERS

ROM 0 0 - R O M If+

12 BIT
MEMORY ADDRESS

-1

1
ADDR

ADDR

0 - 377
E2 0

400-777
E 26

ADDR

1000-1377
E 32

8 LEAST
SIGNIFICANT
BITS

1400-1777

+ 1400-1777

-----

ADDR
0-377

+ 1000-1377

E50

E 38
ADDR

8 LEAST
SIGNIFICANT
BITS

ADDR

A DDR

400-777
E42

8 LEAST
SIGNIFICANT
BITS

Figure 5 - 3 9

v
8 LEAST

SIGNIFICANT
BITS

4 MOST
SIGNIFICANT
BITS

PROM Addressing Scheme

A normal problem w i t h read-only memories is that codes must be specially written t o avoid instructions that require
a write operation he., JMS, DCA, and ISZ) and the placing o f variable locations in R/W memory. I n this PROM, that
restriction is removed if the total number of alterable locations in a piece of core is 2 5 6 or less. This is done by making the PROM a 13-bit memory. On a read access, if the 1 3 t h bit is a 1, the least significant 8 bits stored in the
ROM are treated as an address, rather than an operand, and point t o a read/write location. The 1 K of PROM provides 2 5 6 of these locations.
By checking a program as it is written, i t is possible t o tag all operands that may be changed in the course of execution and then to modify the program controlling the PROM programmer to set the 1 3 t h b i t for this address and
place the next available R A M address in this location. Thus, whenever this location in PROM i s accessed, the actual
data will be read from or written into the corresponding R A M location.
Programming Example

TAD CONST
DCA TEM
ISZ CNTR
TAD TEM
J M S SUBR
01254
03361
02255
01361
04300
/CONSTANT 1 0
/POINTS TO R A M LOCATION 1
/POINTS TO R A M LOCATION 2
/POINTS TO R A M LOCATION 3 FOR RETURN ADDRESS STORAGE

After PROM is programmed, it must be checked using the MR8-FB diagnostic and the data tape used to program
the PROM. PROM is read and compared to the program tape. The read/write locations specified by the 13th bit are
exercised to determine if they read and write correctly.
Refer to Introduction to Programming-7972 for other PDP-8/A programming information. The rules for programming
and generating paper tapes to program the MR8-FB are given in the MR8-F Program Format Description (DEC-08OM RAA-C-D).

5.14.1 PROM Erasing Procedure
The PROM data may be erased by exposure to high intensity, short-wave, or ultraviolet light at a wave length of
2537 A. The recommended integrated dose (i.e., UV intensity X exposure time) is 6 W sec/cm(2). The ultraviolet
lamps should be used without short wave filters and the PROM should be placed about one inch away from the
lamp tube. This operation has the effect of writing all 0s into the PROM.
WARNING
Short wave ultraviolet light can cause "sunburning" of
the eyes and skin. Eyes should be protected from
exposure.
5.15 DETAILED LOGIC DESCRIPTION
The MR8-FB logic has been divided into functional groups for discussion purposes. The block diagram, Figure 5-34,
should be used to understand the interaction of the logic, the signal flow within the module, and the input or output
signals.
5.1 5.1 Address Decoder
Figure 5-40 shows the Address Decoder logic. The address assigned to the MR8-FB is selected by cutting out one
of the diodes on each address bit. As an example, if the address assigned to the MR8-FB requires EMA 2 L to be 1,
diode D3 is taken out, so that when EMA 2 L is a 1, E24 and E l 7 do not ground the base of Q1. When the correct
combination of 1s and 0s (the address of the MR8-FB) are applied to the Address Decoder logic, the base of Q1 is
positive and E9 is enabled to assert MCL FIELD H and MCL FIELD L. This enables the memory address bits (MA
04-MA 11) to be applied to the 1 K PROM chips and select a PROM memory location. This also enables the 13th
bit decoder to determine if the 13th bit at that memory location is a 1.
5.1 5.2 Timing and Processor Control for SW Start of Memory
The logic used t o initialize the processor, load the starting address and memory field, and start the program is shown
in Figure 5-41. The timing required for this operation is shown in Figure 5-35.
A BOOT operation timing chain was implemented with four time-delay one-shot multivibrators designated DLY 1
through DLY 4. The 74123 1C (Figure 5-41) consists of two one-shot multivibrators that output a pulse each time
the input is triggered. The duration of the output pulse is determined by an external resistor and capacitor.
If the SW DIS jumper is installed, the timing chain is started by SW H from the Limited Function Panel when BOOT
is pressed and then returned to the up position or when BOOT is pressed twice on the Programmer's Console. A positive-going transition on the SW line sets DLY 1 for 3 ms. The RC network and feedback on the input line removes
switch contact bounce.
PWR OK H is negated (pulled low) shortly after the DLY 1 pulse is generated if the RUN ON jumper is installed to
supply a ground to E48, or if the RUN OFF jumper is installed and RUN L is negated (high). With the RUN OFF
jumper installed as shown in Figure 5-41, SW operation takes place only when the processor is not running. If the
jumper is installed in the RUN ON position, the SW operation takes place anytime BOOT is activated. When PWR
OK H goes low, the processor generates a 560 ms INIT H pulse to clear the processor and options.

EMA 0 L

EMA 1 L
Ã

MCL B M A 0 3
MA 0 3 L

MCL FIELD L

Figure 5 - 4 0

Address Decoder Logic

After the 3 I,-'s delay DLY 1 times out and the 0 side goes high, i t clocks the MCL GO flip-flop. MCL GO sets and
M C L CO ( 1 ) 1-1 ,s true. This signal enables the signals t o the starting address and field select logic, as well as most
of the signa:'
ed by the processor during an S W start sequence. The timing out of DLY 1 also removes the NOT
PWF OK signal, oilowing PWR OK t o go high (true).
Wh.-i iNIT times out and goes low, and w i t h M C L GO set, DLY 2 is triggered t o generate a 1 0 0 ns pulse. DLY 2 on
the leading edge ensu~esthat MCL KC is 0 and it sets M C L LA t o 1. With MCL LA and MCL GO set, I N D 1 L, LA
EN L, and M S IR DIS L are applied t o the Omnibus. With MCL KC cleared, MCL EN ST ADDR H becomes true and
the sta-'ing address is applied t o the data lines.
When DLY 2 times out ( 1 0 0 ns), its trailing edge triggers DLY 3, which produces a 2 5 0 ns pulse. This delay allows
the signals generated b\ the previous delay t o settle o n the Omnibus.
On the trailing edge o* U Y 3, DLY 4 is triggered, producing a 1 0 0 ns pulse. The DLY 4 pulse, along with MCL LA
being set, enables
M-Ã gate, E59 and produces PULSE LA 1-1 which loads the starting address into the processor.
This pulse is fed ~ L - Kt o 7LY 3, MCL L,A, and MCL KC. On the trailing edge of DLY 4, DLY 3 is triggered and MCL
KC is set. Because M C L i\C was a 0, MCL LA remains set.

N o w that MCL KC is set, MCL EN ST ADDR is removed, M C L EN EMA H is enabled, and the field address is applied t o the Omnibus, KEY CONT L i s also applied t o the Omnibus.
Once again DLY 3 times out and triggers DLY 4. This again produces the 1 0 0 ns PULSE LA H signal, retriggers
DLY 3, and clears MCL LA on its trailing edge. With MCL LA removed, all signals are disabled except M E M START.
When DLY 4 is triggered again by the trailing edge of DLY 3, the only signal generated is M E M START L. M E M
START L is applied t o the Omnibus t o start the timing chain on the timing board of the processor and the RUN flipflop sets. When RUN sets, MCL GO clears t o disable the S W start logic. The next TP2 pulse clears MCL KC.
A t this time, the program starts at the address specified by the starting address and field select logic (Figure 5-35).
5.15.3 Field and Starting Address Select L,ogic
The field and starting address select logic is shown in Figure 5-42. This logic determines the starting address and
field in which the program that is started with BOOT key resides. The starting address and field are selected by jumpers. Removing a jumper causes a 1 t o be placed onto the associated Data Bus line; otherwise, a 0 is placed on that
line. These jumper bits are applied t o the data bus when either MCL EN ST ADDR H or EN EMA H in the control
logic is true (Figure 5-41). DATA 6-8 and DATA 9 - 1 1 on the Data Bus are transferred t o the IF and DF of memory
extension control when PULSE LA H is asserted (Figure 5-42). DATA 00 and DATA 0 1 determines the 1 K block of
memory in which the program resides, and DATA 4 determines the starting address (000(8) or 200(8)).

lP1

DATA 0 L

DATA 11 L

Figure 5 - 4 2

Field and Starting Address Select Logic

5.1 5.4 Memory Address Control Signal Generation
The logic shown in Figure 5-43 generates NTS STALL L, and ROM ADDR L to control PROM and ROM memory
access.
5.1 5.5 NTS STALL
NTS STALL L (E21 B) is triggered by WRITE H and RETURN H. It generates a 2.2 p s pulse which is applied to the
memory timing module. NTS STALL L increases the memory cycle by 2.2 ns to allow for the longer access time of
PROM and time for the data on the M D lines to settle before it is transferred to the processor.
5.15.6 ROM ADDR
The MR8-FB does not occupy memory locations assigned to a regular core memory, the jumper on the output of
E44 is not installed, and ROM ADDR is never set. This feature is used on other versions of PROM not available for
the PDP-8/A.
5.1 5.7 1K PROM Memory and Control Logic
Figure 5-44 shows 400(8) words of PROM, the control logic required to read PROM, and the chip for the 13th bit
addressing. Reading of the other PROM chips is accomplished the same way as the 400(8) locations show (Engineering Drawing D-CS-M8349-0-0).
The Memory Address bits (MA 04-MA 11) are applied to the address inputs of the PROM 1702A chips when MCL
FIELD L is asserted by the Address Decoder (Figure 5-40). MCL FIELD L is asserted when this PROM is addressed
by the program. BMA 0 2 and BMA 0 3 are applied to NAND gates E l 2 where they are decoded to enable the two
addressed chips to be read. As an example, if BMA 0 2 and BMA 0 3 are both Os, E12D is enabled and E26 and the
lower half of E50 are selected. This is done by supplying a low input to CS of these 2 chips. The CS input to the
13th bit chip is grounded so this chip is read every time. The output PROM is applied to the Data Multiplexer (Figure 5-45) except when bit 13 is a 1. When bit 13 of the memory location addressed by the program is a 1, ROM H
and ROM L out of E l 6 are asserted. Bit 13 is a 1 when the program must address a location in read/write memory.
When ROM L is asserted, the eight least significant bits of PROM (ROM 4-ROM 11) are applied to the RAM chips
to select a location in RAM.

MCL FIELD H

+5 V

WRITE

RETURN

Figure 5-43

Memory Address Control Signal Generator

+5 V

INDICATES
MISSING LOGIC

MCL BMA02H

ROM 00 H

vcc

MCL BMA03H

ROM 01 H
ADDRESS
ROM 0 2 H
ROM 0 3 H

I I

1 NOTE

lW
ROM 0 4 H

MCL BMA03 H

MCL B M A 0 2 H
NOTE
These signals are used to select
other PROM chips.

Figure 5-44

PROM and Control Logic

RX~H

ROM 0 0 H
ROM 0 1 H
ROM 0 2

NTS STALL L
,--xYA2

SEL

ROM 0 3 H
RAM 0 0 H
RAM 0 1 H

E6
(74157)
f
(+

RAM 0 2 H

CLK

RAM 0 3 H

ROM 0 4

ROM 0 5 H

A
SEL

LATCH
â‚¬
(741 74)

[

ROM 0 6 H
ROM 0 7

RAM 0 4

RAM 0 5

RAM 0 6

RAM 0 7

+5V
CLR

El8
(74157)

-CLK
ST0

1 -

1
Ã
‘
Ã
‘
Ã
‘
Ã
‘
Ã
‘
Ã
‘
Ã
‘
Ã
‘
Ã

ROM 0 8 H
ROM 0 9 H

LATCH
E39
(74174)

SEL

ROM 10 H
ROM 11

CLR

RAM 0 8 H
RAM 0 9 H

E35
( 74157)

RAM 10 H
RAM 11 H
ST0

BE 0690

Figure 5 - 4 5

ROM and R A M Data Multiplexer and Latch

5.15.8 256 Read/Write Memory and Control Logic
ROM 0 0 - R O M 1 1 are applied to the 7 4 2 0 0 R A M chips when ROM L is asserted. ROM L is asserted if bit 1 3 is a
1. M C L FIELD L is always asserted when the PROM is addressed. ROM 0 4 - R O M 1 1 selects an address in R A M and
R A M 0 0 - R A M 11 are applied t o the Data Multiplexer (Figure 5 - 4 5 ) . The timing for this operation is shown in Figure
5-37.
If the instruction specifies a write operation for RAM, M D DIR L from the Omnibus is negated (high) and R A M WRT
EN L is asserted a t TP3 time. R A M WRT EN L is applied t o the WRT input of all twelve R A M chips and the data on
the M D lines ( M D 0 0 - M D 11) is written into the R A M location selected by ROM 0 4 - R O M 11.
The tabs shown in Figure 5 - 4 7 are used t o supply 4-5 V from a battery so that R A M will n o t be changed if power
fails. The jumper shown takes the 4-5 V from the Omnibus t o supply the R A M chips. I t can be changed t o use the
battery voltage if this is desired by the user.
5.15.9 ROM and R A M Data Multiplexer
The ROM and RAM Data Multiplexer is shown in Figure 5 - 4 6 . The multiplexer consists of three 7 4 1 5 7 ICs that select either ROM 0 0 - R O M 1 1 or R A M 0 0 - R A M 1 1 t o be applied t o the M D lines. If the 1 3 t h bit is a 1, ROM H is
true (high) and R A M 0 0 - R A M 1 1 are selected as an output; otherwise ROM 00-ROM 1 1 are selected.

BATTERY

1 '7
9'
1
RAM 0 0 H

MCL FIELD L

SUPPLY(+ SVJ

ROM 0 4 H
ROM 0 5 H
ROM 0 6 H
ROM 0 7- H
ROM 0 8 -H
ROM 0 9 H
ROM 1 0 H
ROM 11 H

RAM 0 5 H

I
1

TO ROM AND
RAM MULTIPLEXER

RAM 06 H
I

MCL FIELD H
!RAM

* DOTTED
LINES USED TO
INDICATE MISSING LOGIC

WRT EN L

RAM MD DIP H
RAM MD DIR L
BE-0691

Figure 5-46

RAM Memory (256 Word)

The output of the Data Multiplexer is applied to a Latch Register (E22 and E39) where the selected output is
clocked onto the Line Driver Buffer by NTS STALL L (Figure 5-44). The Line Drive Buffers are enabled by MCL
FIELD H and RAM M D DIR L. MCL FIELD H is asserted any time this PROM is selected and RAM M D DIR L is
high during read operations.

5.1 6 MAINTENANCE
The general procedures concerning preventive and corrective maintenance are given in Chapter 8. When a malfunction in the MR8-FB is suspected, the technician should use the diagnostic programs to determine the nature of the
problem. Refer to option schematic drawing E-CS-M8349-0-0 for 1C locations and pin numbers. Test points are provided on the module to facilitate trouble-shooting,
NOTE
If any 1702A PROM chips are changed during a
trouble-shooting or maintenance operation, all of
PROM must be erased and reprogrammed.

SECTION 4
CORE MEMORY SYSTEMS

5.17 MEMORY SYSTEM, GENERAL DESCRIPTION
The standard PDP-8/A core memory, designated MM8-AA(8K) or MM8-AB(16K), is a random access, coincidentcurrent, magnetic, readjwrite memory with a cycle time of 1.5 microseconds. The memory includes ferrite cores wired in
a 3-D, 3-wire, planar configuration. The basic unit can store up to 8 192 (8K) of 16384 ( 16K) 12-bit words, and can be
expanded to 32K words in 8K or 16K increments.
5.1 8 MEMORY SYSTEM, FUNCTIONAL DESCRIPTION
The memory system performs three basic functions for the PDP-8/A processor:
1.

It decodes and selects the desired core location in which a 12-bit word is stored or will be stored.

It reads a 12-bit word from the selected location.

It writes a 12-bit word into the same selected location.

These functions are illustrated in Figures 5-47 and 5-48, for which one memory cycle is represented. The M A register in the CPU is loaded at the beginning of the memory cycle. The address bus (MAO-MA111 will have settled at
the memory 50 ns before the SOURCE H (high) signal on AL2, Memory address decoders receive the M A bits and
turn on the corresponding driver and sink current selection switches. XY current flows when the read or write current
source is pulsed by the internal memory timing.
The outputs from the 12 selected cores are fed to their respective sense amplifiers. A strobe signal is used to gate the
sense amplifier into the Sense Register. If M D DIR L is low (as it always is during the READ portion of the memory cycle),
the output of the Memory Register is placed on the M D lines. During the write portion of the memory cycle, the memory
selection system uses the same address inputs and control signals; however, control signal WRITE H will go high,
causing the write current switches to be activated. To write the content of the Sense Register back into core, M D DIR L
will be low (active). Otherwise, the content of the Sense Register will be inhibited from being placed on the M D lines, and
a word from the processor will be written into core. The Sense Register is an integral part of the Sense Amplifier. The
INHIBIT TIME 2A L signal from the timing circuit controls the gating circuits, and only when INHIBIT TIME 2A L is low
will the Inhibit Drivers be activated. A logic zero received from the M D lines and INHIBIT TIME 2A L causes the
corresponding Inhibit Driver to produce inhibit current.

-------.-WRITE
STROBE

CURRENT
SWITCHES

TIMING

INHIBIT

SENSE
REG

CLEAR

Figure 5-47

INHIBIT
DRIVERS

MD 0 - 11
TO OMNIBUS

Core Memory System Functional Block Diagram

TIME (ns)

i
VIA

4
MA BUS

Ã‘

SOURCE H

4 h - 5 0 n s MINIMUM

W 5 0 n s MINIMUM

RETURN I4
WRITE H
TS1
ROM ADDR L

E%/

LOW I F A ROM IS SELECTED

POWER NOT OK L
MD DIR L

FIELD H

STAYS LOW I F FETCH CYCLE

HIGH I F THIS MEMORY IS SELECTED

INH ON H
MD DIR T I M E 2 H
TS1 + RET H
TS1

+ SOURCE H

I N H I B I T TIME 2 A L
READ DR TIME L
READ SINK TIME L
WRITE DR TIME L
WRITE SINK TIME L
READ/WRITE
CURRENT TIME H
CLEAR TIME L
STROBE TIME 2 A H
MDBUS

MIN

LO^^-

A DATA To cp

B
-

DATA TO MEMORY

Figure 5-48

Core Memory Timing Diagram

6.19 M M 8 - A A 8 K CORE MEMORY SYSTEM
The organization of the MM8-AA memory system is illustrated in Figure 5-49. One hex-size board with a piggy back
H219A stack board is used to contain the memory system as follows:
1.

G649 baseboard contains 12 Sense Amplifiers, Memory Registers, and Inhibit Drivers with the corresponding control logic, and current control, address decoding, selection switches, X-current source, Y-current source, and Power Fail circuit.

H219A Memory Stack contains 12 mats of 8192 cores per mat, X/Y diode selection matrix, and Stack
charge circuit.

6.19.1 Memory Core
The basic storage element in the MM8-AA Memory System (and in the MM8-AB, as well) is a small (18 Mil OD), toroidal
(ring-shaped) piece of ferrite material called a magnetic core. A single core, mounted on a ground plane, is illustrated in
Figure 5-50. Three wires pass through each core to accommodate the X- and Y-selection and the sense/inhibit function.
6.19.2 Hysteresis Loop
The characteristics of the magnetic core can be shown by a graph, plotting the current (the magnetizing force) versus
flux-density (the resulting magnetism) hysteresis loop as illustrated in Figure 5-51. This hysteresis loop illustrates the
magnetizing current, I, produced by the current contained in the three wires plotted along the horizontal axis, and the
resulting flux density, beta, through the core along the vertical axis. Two directions of current are shown.

p FIELD H
RETURN H
FIELD H
ROM ADDR L
TS 1
WRITE H

WRITE H
RETURN H
SOURCE H
FIELD H
TS 1
SOURCE H
FIELD H

--4

READ
WRITE
TIMING

EMA2L 4

8
STA CK

lx1,

& llYll

CURRENT
SOURCES

WRITE H

CKT

CIRCUIT
SOURCE H 4

CLEAR

WRITE H

CIRCUIT

SOURCE HWRITE H-

SENSE

CIRCUITS
+5V

STROBE

CIRCUIT

CLEAR TIME L

-5V

STROBE TIME 2 A H

ROM ADDR L
POWER
NOT OK L

+2 0 ~
Figure 5-49

MM8-AA Core Memory Block Diagram

DATA
OUT

V^Ã‘ L I N E

BONDING

Figure 5-50

Magnetic Core

R E A D CURRENT

WRITE C U R R E N T
SATURATION

fl F L U X D E N S I T Y
( MAGNETISM
R E M A N E N T POINT
OF RESIDUAL MAGNETISM

-Bm ( L O G I C O ' )

ZERO FLUX D E N S I T Y
ZERO CURRENT

LOG I C ' 0 "

R E M A N E N T POINT
OF R E S I D U A L
MAGNETISM

Figure 5-51

Magnetic Core Hysteresis Loop

Read current, with respect to the graph, is directed from right to left. If a logic 1 is stored in the core, B will move from the
remanent point, +Br, down to saturation at -Bm when the read current is turned on. When the magnetizing current is
removed, the flux density settles down to the remanent point at -Br. Write current is directed from left to right with
respect to the graph. If a 1 is to be written into core, the flux density will move from the point -Br to point +Bm on the
graph and then settle down to
Br when the magnetizing current is removed. Thus, points -Bm and +Bm are the
extreme saturation points, and points -Br and +Br are the extreme points in the normal logic states.

5.19.3 X/Y Select Lines
WY drive selection is accomplished by the coincidence and addition of two half select currents at one core in each bit of
the word length. All other cores on these activated X/Y lines will see only one half select current and will not switch. A
half selected core in the one state will move from Br to H and move back to Br at the end of the read current. During
write a half selected core will move from -Br to J and return t o -Br.

'3.19.4 Read Operation
Read occurs during the first half of the memory cycle. Its function is to sample either a logic 1 or logic 0 fully selected core. Thus, both the X- and Y-read half-select currents must be applied for the Sense/Winding to receive a signal resulting from the switching of flux in a core storing a 1 . If the core is in logic 0 state, no change in flux state
occurs and, therefore, no signal appears on the SenselLine.
6.1 9.5 Write Operation
Write occurs during the second half of the memory cycle. Because write follows read, the cores at the selected address
have been cleared to a logic 0 state. If the fully selected core (X- and Y-currents) is not inhibited, the magnetic flux moves
from point -Br to +Bm then returns to +Br on the graph, and a logical 1 is stored in the core. However, to store a 0 in
core, it is necessary to cause a less than fully selected condition. This can be achieved by generating an inhibit current and
applying this current to the Sensellnhibit line. If this inhibit current is in the opposite direction to the X- and Y-current, the
net result of the change in flux will be from point -Br to point J on the graph. The resultant effect is the cancelling of half
of the full current required to switch the state of the core. When all currents are removed, the flux state reverts back to
-Br on the graph.
5.1 9.6 Magnetic Core In Two-Dimensional Array
A partial three-wire memory configuration is illustrated in Figure 5-52. Half-select currents are produced for one X-line
and one Y-line, If, for example, the core at X3, Y2 is selected, the corresponding wires going through each row would
contain half-select current. For the X3 row, Y1 core would contain only half-select current, and Y2 core would contain
full-select current. All other cores in row Y2 would contain half-select current. The Sensellnhibit line terminates at the
Sense Amplifier and the Inhibit Driver in the manner shown in Figure 5-52. There are two termination points on the
Sense Amplifier side, and one termination point at the Inhibit Drivers,
The third wire (the Sensellnhibit line) receives the resulting signal from the core which sees coincident current. Y Read
current direction is from the top of the illustration down. Y Write current direction is from the botton of the illustration to
the top. The Inhibit current opposes the Y write current in those cores where zeros are to be written.

5.19.7 Assembly Of 12-Stacked Core Mats
The MM8-AA Memory is a 128 X 6 4 configuration (128 X-rows and 64 Y-rows). This configuration provides 8,192
cores per mat, for which one core can be selected during any one memory cycle and therefore, one bit of information per mat.
The memory stack component layout is illustrated in Figure 5-53. Figure 5-54 illustrates the X- and Y-windings
within memory stacks.
The MM8-AA is a 12-bit word memory system; thus, 12 mats are used. Each mat stores one unique bit of information, which is detected and sensed by one unique line called the SenseAnhibit line. SenseAnhibit lines are used to
detect and sense 12 unique bits of information. The arrangement of the X select lines is quite different from that of
the Y axis. All 12 mats contain 128 X-lines and 6 4 Y-lines. The threading of each of the X- and Y-lines continues
from one mat to the next through all 12 mats. For example, row X31 of mat 0 is common to row X31 of mat 1,
which is common to all subsequent mats at row X31. The common factor to each mat is the selection line that is
threaded through 12 X 6 4 cores or 768 cores. The intersection of X31 and Y29, therefore, occurs 12 times in the
12 mats. Because each mat contains a unique SenseAnhibit line, 12 unique bits of information can be stored to
form a 12-bit word.

5.1 9.8 Core Selection System
Core selection is accomplished by enabling the desired X-line and the desired Y-line and allowing current to pass
through the selected lines. To accomplish the selection of the X- and Y-lines, a decoding network that receives the
Memory Address bits and decodes for line selection is required. An X- and Y-current source is also required.

Y WRITE

INHIBIT

x WRITE

SELECTED

SENSE/INHIBIT
LINES
Y

READ

Figure 5-52

m
a

TO SENSE A M P L I F I E R
TERMINATION

Three Wire Memory Configuration

IT)

c\J

8K TERMINATIONS

8 K T E RMINATIONS

Figure 5-54

+ 12 Bit Stack and Sense Lines

In the block diagram (Figure 5-49) the primary selection components involved are:
1.

The Memory Address decoder, which receives Memory Address bits and control signals to select (enable)
the corresponding switch and driver.

An X and Y current source to provide the necessary select X and Y currents.

A source or driver switch and a sink to apply current to the selected row and to forward-bias the selection diode.

One read or write diode in the selection diode block becomes forward-biased by the driver and switch, while
all other diodes are back-biased by the stack charge circuit.

One selected X row containing 768 cores and a selected Y row containing 1536 cores.

A simplified view of one selected read/write path is shown in Figures 5-55 and 5-56,
6.19.9 Organization Of X/Y Drivers And Current Source
Figure 5-57 illustrates the organization and decoding of the X/Y drivers and current source, and the primary signals
required to make line selection and current switching possible. Five decoders are used to select one of 128 X-lines and
one of 6 4 Y-lines as determined by the content of bits M A 0 through MA1 1. A pulsed X- and Y-current, provided by the Xand Y-current source, are applied to the drivers. The read timing signals are applied directly to the 75325 1C read drivers
and sinks which switch current through the stack. The write operation uses similar decoding.

5.19.10 X And Y Current Sources General Description
The current source will be described in more detail in Paragraph 5.19.31.

CURRENT
MEASURING
LOOP

SELECTED WRITE DRIVER (SOURCE)

SWITCH

STACK
ONE
ROW

OTHER
UNSELECTED

CORES IN X

1536 CORES IN Y

-4

CURRENT FLOW
TO
OTHER
ROWS
UNSELECTED
-WRITE

L--

TO
STACK
CHARGE

-1 '
1

WRITE SINK
SWITCH

Figure 5-55

Current Path For Write Current

POWER
NOT
OK L

Figure 5-56

Current Path For Read Current

The two current sources supply temperature-dependent X/Y currents to the memory stack selection switches. The
current sources are turned on after the stack selection switches and it is the timing input to the current source which
determines the position and the width of the stack current. The amplitude of the current is proportional to a reference
voltage which tracks the temperature of the baseboard.

5.19.1 1 Stack Charge Circuit
The Stack Charge circuit (Figure 5-58) switches the stack charge voltage from near ground for a read operation to near
+ 2 0 V for a write operation. When control signal WRITE H is negated, level shifting circuits along with an output
transistor Q2 switch the output to ground. When WRITE H is asserted, the output switches to 4-20 V. The stack charge
driver provides the reverse bias condition on the non-selected diodes in the memory stack. Reverse biasing the nonselected diodes eliminates sneak currents. Refer to Paragraph 5.1 9.1 5 for the organization of the planar stack diode
matrix.
5.19.12 Power Fail Circuit
The power fail circuit (Figure 5-59) responds to the POWER NOT OK L signal from the processor. Its primary function is
to ensure that selected memory locations are not changed due to a power failure. The power supply senses a voltage
change when the dc voltage drops and grounds the POWER NOT OK L line before the voltage becomes too low. Less
than 2 0 p s later, the memory timing chain is shut off. Between 2 0 and 5 0 u s after the POWER NOT OK L signal is
asserted, the memory power fail circuitry turns off the X- and Y-current sources. When the machine is turned on initially
and the POWER NOT OK L signal is asserted, access to the memory is not allowed until 5 0 p s after power has been
applied.
5.19.13 Core Selection Decoders
Five decoders (7442 ICs) (Figure 5-57) are used to decode Memory Address register bits MAR0 L through MAR1 1 L and
EMA2 L. These bits are combined with WRITE H, FIELD H, TS1, SOURCE H, and RETURN H signals to enable the
appropriate sink and source switches. Signal WRITE H INV is generated when WRITE H is not asserted, while WRITE H
BU F is asserted along with WRITE H, The WRITE H signal is developed in the Timing Generator during the last half of the
memory cycle. SOURCE H is necessary to turn on the selected read and write sinks, and RETURN H is necessary to turn
on the selected source switches. Both RETURN H and SOURCE H are developed in the Timing Generator. RETURN H
remains on for 5 0 ns longer than SOURCE H to minimize power dissipation in the 75325 1C switches,

t
x WRITE
(CURRENT)

XOOO

- XI70

75325
SOURCE
COLLECTORS

WRITE
SINK
TIME L

7442
WRITE
DECODER

READ SINK
TIME L
7442
WRITE
DECODER

CONTROL LOGIC

MAR 11 L

MAR 8 L

FIELD H
SOURCE
CONTROL
LOGIC

'7 1

SOURCE
COLLECTORS

READ
(CURRENT)

READ DR
TIME L

7442

7442
READ
DECODER

DECODER

MAR 9 L

MAR 5 L

CONTROL LOGIC

MAR 11 L
+

SIÂ±

WRITE H BUF

POWER
NOT OK

- X Al 7 0
I

WRITE OR
TIME L

READ/
WRITE
CURRENT
TIME H

XOOO

RETURN H

MAR 8 L
+

LWRITEHINV
SOURCE H

SOURCE H

FIELD H SOURCE H

t
" Y " WRITE
(CURRENT)

4
75325

COLLECTORS

"Y' READ

SOURCE

(CURRENT)
WRITE DR
TIME L
7442
WRITE
DECODER

. .

MAR 2 L

CONTROL LOGIC

MAR 4 L
FIELD H

READ OR
TIME L

7442
READ
DECODER

EMA 2 L
MAR OL
MAR 1 L

MAR 2 L

EMA 2L

RETURN H
SOURCE H

Figure 5-57

75325
SOURCE <-" Y " READ
(CURRENT)
COLLECTORS

7442
WRITE
DECODER

WRITE H BUF

TS 1
WRITE H

READ SINK
TIME L

zLNtL

Decoding of X and Y Driver Current
Sources Block Diagram

i
MAR 4 L

MAR 1 L
TS 1

WRITE H 1NV

----------LO

CORE M E M O R Y STACK ( H 2 1 9 A )

W R I T E ti B U F
WRITE H
STACK BIAS

Figure 5-58

Stack Charge Circuit

OUTPUT T O
CURRENT
SOURCES

POWER N O T OK L

-STROBE
V- R E F

VOLT;

'4.7V
OUT

Figure 5-59

Power Fail Circuitry

6.1 9.14 Address Decoding Scheme
The block diagram in Figure 5-57 illustrates the method used to decode the MAR bits and EMA2 L. The process turns on
either a write or read source collector and the corresponding sink, thereby completing a current path through the stack.
The decoder is arranged as follows: The write selection decoders are on the left side of the illustration and the read
selection decoders are on the right side. The X selection decoders decode bits MAR5 L through MAR1 1 L. The Y
selection decoders decode bits EMA2 L and MAR0 L through MAR4 L. The X decoding scheme consists of a 1 6 X 8
matrix; the Y decoding scheme consists of an 8 X 8 matrix. The decoder outputs are applied to the selected switches.
The outputs of the selected switches connect to the selection diodes (Paragraph 5.1 9.5) which, in turn, are connected to
lines that are threaded through the memory cores. The arrangement of the illustration (Figure 5-57) permits correlation
with the engineering drawing schematics (G649).
The decoding scheme of the MAR bits and the EMA bits is illustrated in Figure 5-60. The illustration shows the five parts
of the the memory address, what is decoded, and where in the field of the drawing the decoders are located. Table 5-1 2
lists the necessary input control signals, the content of the memory address, the input pins, the output pins, and the
selected X- or Y-line. With this information, the user can easily trace through all of the components on any signal/current
path to find the selected components.

5.1 9.1 5 Diode Selection Matrix
Each of the X- and Y-select lines are connected to a corresponding string of diodes (Figure 5-61 ). Selection is such that
any one of the eight upper select lines will pass current in a path determined by whether it is a read or write operation. In
Figure 5-61, for X-selection, the example illustrates line X(12) being selected. The current passes through 7 6 8 cores and
back through one of the diodes. The path the current takes from this point is determined by the diode that is forwardbiased. The forward-biasing of a diode is accomplished by operating the switch and driver. If it is a write operation, WX2
is forward-biased and the current takes the path from WX2 to X I 0, If it is a read operation, RX2 is forward-biased and the
current takes the path from X I 0 to RX2. All diodes except the selected diode are reverse-biased.
6.19.16 Operation Of Selection Switches
Figure 5-62 illustrates the switching operation of the currents through XO select line. On the upper side, a pair of
transistors is used to either drive or sink current, depending on whether the operation is read or write. A complementary
pair of transistors on the lower side is used to either drive or sink the current. A line between the upper and lower side is
threaded through 768 cores. The read operation begins with the decoders. When an X-line such as XO is to be selected,
the read driver and read sink must first be turned on. To turn on the read driver and read sink, the input to the 75325
must be positive with respect to the emitter. This occurs only when the output of the decoder is low (active).

MAR
0

'FIELDI *Y rI ;
I
I

I
I

DIODE
MATRIX
END

I
I

Figure 5-60

T
1

I
I
I

6
Y

1
I
I

ADDRESS

DIODE
MATRIX
END

Decoding Relationships

1 WHAT I S DECODED
1
I
I

Table 5-12
Core Selection Decoding Scheme
"X" R EAD
Function

MAR5 L

Control Logic

Source
Output
Pins

4
MARS L

Turn on
Source Collectors

Turn on Sinks

TS1 + RET H
TS1 +SOURCE H
WRITE H I N V
READ DR TIME L

= H

= H
= H
= L

TS1 + R E T H
T S 1 + SOURCE H
WRITE H I N V
READ SINK TIME L

= H

*EXAMPLE:

Source Collector = 030
Sink
= + 6
(Total)

= H
=

= L

Line Selected

= 036

Octal

Sink
Input
Pins

Selected
Source

Selected
Sink

Octal

Table 5-12 (Cont)

Core Selection Decoding Scheme
"X" WRITE
Function

Turn o n
Source Collectors

Turn on Sinks

Control Logic

Source
Output
Pins

FIELD H
TS1 + R E T H
TS1 + SOURCE H
WRITE H BUF
WRITE DR T I M E L

FIELD H
TS1 + R E T H
TS1 +SOURCE H
WRITE H B U F
WRITE SINK T I M E L

*EXAMPLE:

Source Collector =
1
= +I20
Sink
(Total)

Line Selected

121 Octal

Sink
Input
Pins

Selected
Selected
Source Octal Sink

7 6 8 CORES

FORWARD B I A S E D W H E N WRITE
DRIVER AND SWITCH ARE E N A B L E D

'Â

D WHEN READ
ITCH ARE ENABLED

xoo

X10

X20

FROM UPPER
X R E A D / WRITE
DRIVERS/SWITCHES

x40

WXO

RXO

WX1

RX1

WX2

RX2

WX3

RX3

WX4

RX4

WX5

RX5

WX6

RX6

WX7

RX7
08-1243

Figure 5 - 6 1 Organization of Planar Stack
Diode Matrix For X Select Lines

+R E A D

CHARGE
CIRCUIT

O - wW R
^ I -T E4

r-L =
WRITE

SINK

75325

Figure 5 - 6 2

Operation Of Selection Switches To Select Line XO

6.19.17 Operation Of The Core Selection Switches
The cores that contain a selected X-line and selected Y-line define the location in which a 1 or 0 will be either written in
or read out. Figure 5-63 illustrates a small portion of memory and the corresponding X selection devices. The Y decoding
is similar and may be obtained from sheet 5 and 6 of the M M 8 - A A print set in Appendix H. Using Table 5-12, the
selection of any given core can be traced from the Memory Address register through the decoders and switches t o the
selected line and core.
To select the Y read stack line No. 2 5 (octal), the procedure using Table 5 - 1 2 is as follows:
A source collector switch t o select one end of the stack line and a sink switch to select the other end of the stack
line must be turned on together. This completes the current path from the current source through the source collector switch, through the selected stack line, through the sink switch t o ground.
Addresses EMA2L, EMAOL and E M A I L are decoded t o select any 1 out of 8 source collectors - in our example we
are selecting the address combination that gives us binary 0 1 0 (octal 2).
Addresses MAR2 L, MAR3 L, and MAR4 L are decoded t o select any 1 out of 8 sink switches. In our example we are
selecting the address combination that gives us binary 101 (octal 5). Table 5-13 shows selected stack lines for all
combinations of selected source collectors and selected sinks.
When a read driver and sink pair are selected and the current source is pulsed, a read current will flow from current
source through read driver, stack diode matrix, and read sink t o ground. During the read time period the state of the
stack charge ci,rcuit output will be low. The function of the stack charge circuit during read is t o hold all lines except
the selected line to ground t o prevent forward biasing the nonselected read diodes.
One current source is shared by the read and write source switches. The description of the write operation is similiar
to the above description of the read operation. The exception is the level of the stack charge circuit output which
will be in a high state of approximately 2 0 V. The function of the stack charge during write is t o back bias the unselected write diodes.

6.19.18 Sense/Inhibit Function
The previous paragraphs have described the memory core, the selection of memory core, and the selection of memory core in terms of the read/write operation. However, to perform a read or a write operation, sense amplifiers are
necessary to sense the state of the selected cores, and inhibit drivers are necessary to write 0s into core. Control
logic and data registers are also required t o control the data flow t o and from memory. These necessary circuits are
illustrated in a simplified diagram (Figure 5-64). The circuits designated correspond t o bit 0 .
6.19.19 Sense/Inhibit Line
The line that is used to sense a 1 during read is also used t o transmit inhibit current when a 0 is t o be written during the write portion of the memory cycle. The SenseAnhibit line passes through 8192 cores of one bit mat. Two
ends of this line are terminated through diodes t o ground at the input to the Sense Amplifier. The Inhibit Driver feeds
a center tap on the Sense Inhibit line (see Figure 5-64).
6.19.20 Read/Write Operation
The read operation involves the Sense Amplifier and the necessary control logic in conjunction with the selection system.
During the read portion of the memory cycle, the selected core develops a signal on the SenseAnhibit line only if a 1 was
previously stored in core. The sense registers in the sense amplifier are previously cleared and STROBE TIME 2A H gates
either a 1 or 0 into the Sense Register. When a 1 is sensed, the Sense Amplifier applies a low signal to the MD line
(Figure 5-64).

MAR 11MAR 10M A R 9 - 9 8

7442
E64

DECODER

7 6 5 4 3 2 1

(
wx,

A
I

A ~ 1 0 3 AL1139
t

X LINE

STACK
f

, , ,
/ Â ¥ / ' /

x00

Jim

J135
\\

M A R 8 - 1 \ 5 t 2 3 4 5 6 7 8 9
MAR 7
14
MAR GÃ‘1
755%
Y LINE

DECODER

MAR 5-12
08-1214

Figure 5 - 6 3

Detailed Operation Of Selection Switches

Table 5-13
Core Selection Y READ
Selected
Source

All numbers are in octal.

Selected Sink

ROM ADDR L

SOURCE H

CLEAR TIME

WRITE H

INHIBIT
TIMING
DRIVER

ROM ADDR L

INHIBIT TIME 2A L

SOURCE H

+20v
I
INHIBIT
DRIVER
Ql,Ql3

LATCH
REGISTER
I

SENSE INHIBIT L I N E
0 8 - 122s

Figure 5-64

lnhibit Operation For Bit 0

The output of the core stack which is stored in the sense register will be rewritten into the same core location during the
write half of the timing cycle. The M D DIR L pulse which gates the sense register data to the inhibit driver also puts the
same data on the bus where it is available to the CPU or a peripheral device.
The write operation involves the inhibit drivers, load gates such as E7, E8, sense register, and the necessary control logic
in conjunction with the selection system. The inhibit driver load gates receive ones and zeros via the M D lines from either
the M B register in the processor or the sense register. Control gating signals for the inhibit driver load gate, E l 3, are:

FIELD H, which indicates that the proper memory has been selected.

Not ROM Address

5.19.21 Inhibit Control Logic
The Inhibit Control logic (Figure 5-65) provides a gating control signal to the inhibit driver during the write portion of the
memory cycle. The logic receives RETURN H from the Omnibus, FIELD H from the Field Select Control logic, and TS1
and ROM ADDR L from the Omnibus. The write control bus signal is added into the Field Select Control logic.
6.19.22 Field Select Control Logic
There can be as many as 4 MM8-AA memories in the system, each memory being assigned to one 8K-block of memory
addresses. A particular memory responds only to addresses within its assigned block. The logic shown in Figure 5 - 6 6
allows the memory t o determine if one of its assigned locations is being addressed. If so, the logic asserts the FIELD H
signal and data is transferred t o or from the addressed location.
The EMAO L and E M A l L signals are used to specify an 8K-block of addresses. Selective installation of jumpers in the
logic (Figure 5-66) permits the logic t o respond t o any one of 4 combinations of the EMA signals. For example, the
jumper configuration depicted allows the FIELD H signal to be generated when locations in field 0 (0-8K) are addressed,
i.e., when both EMAO L and E M A l L are negated. Table 5 - 1 4 lists the EMA signals and relates them to both assigned
memory address blocks and installed jumpers.

FIELD H

TIME

TS 1

ROM ADDR L

Figure 5-65

Inhibit Control Logic

EMA0 L

-SPLIT

EMAl L

W R I T E H-

Figure 5-66

Field Select Control Logic

Table 5-14
Address Block Selection

EMAO L
HI
HI

EMAI L

Installed Jumpers

Memory Address Block
0-8K
8K-16K

1-3 and 1-2
2-4 and 1-2
3-4 and 1-3
3-4 and 2-4

5.19-23 Sense Register Enable Logic
The sense register enable logic is shown in Figure 5-67. When MD DIR TIME 2 H is asserted, the content of the sense
register is gated onto the M D line and to the inhibit driver.
5.19.24 Sense Register Clear Timing
'The logic associated with the generation of the CLEAR TIME L signal is illustrated in Figure 5-68, The timing signals are
shown in Figure 5-69. The SOURCE H signal triggers flip-flop E39 and creates a low at the output of NAND gate E30.
This is the leading edge of CLEAR TIME L, and the trailing edge is determined by the leading edge of the STROBE 0
signal.

SENSE
AMP

M D DIR T I M E 2 H

Figure 5 - 6 7

INHIBIT TIME 2 A L

Memory Sense Register Enable Logic for Bit 0

STROBE SET

WRITE H

SOURCE H

Figure 5 - 6 8

Clear Time Control Logic

5.19.25 Strobe Control Logic
The Strobe Control logic is shown in Figure 5-70, The timing signals that generate the strobe are shown in Figure 5-69.
SOURCE H triggers the STROBE one-shot, E44, and the trailing edge of the one-shot signal clocks flip-flop E39. The
output of E39 determines the leading edge of the STROBE TIME 2A H signal. The trailing edge of STROBE TIME 2 A H is
set by SOURCE H going low. The width of the STROBE one-shot output is proportional to the amplitude of a constant
current supplied by transistor 0 2 6 in the strobe adjustment circuit (Figure 5-71 1. The current in Q26 and, hence, the
position of the strobe may be adjusted through the use of jumpers in the emitter circuit of Q26. These jumpers are shown
in Figure 5-71, and Table 5-1 5 relates the jumper placement to the width of the one-shot output. Paragraph 5.19.26
discusses the jumper placement in detail.
5.19.26 Strobe Setting Jumpers
The jumper configuration is used to adjust the strobe position to account for the worst case tolerances in both the strobe
one-shot circuitry and its associated timing-logic circuitry. The ability to choose any one of sixteen strobe settings
provides the advantage of maximizing the memory margins over the entire operating temperature range.

Table 5-15
Strobe Select Jumpers

0 indicates [jumper out1
1 indicates [jumper in]

T I M E I N MICROSECONDS
0

1.0

1.2

1.1

1.3

1.4

1.5

SOURCE H BUF

SOURCE H INV

WRITE H INV

STROBE

(0)

CLEAR TIME ( 0 )

CLEAR TIME L

STROBE TIME ( 1 )

STROBE T I M E 2A H

Strobe and Clear Timing

Figure 5 - 6 9

ROM A D D R L

SOURCE H BUF 1
SOURCE H

STROBE SET

STROBE

Q 26

+5v

I n
7
-

- D
STROBE
TIME
E 39

STROBE
E 44

WRITE H
41

W R I T E H INV

Figure 5 - 7 0

Strobe Control Logic

STROBE T I M E 2 A H

B I T 0 SENSE
REGISTER OUTPUT-H

Figure 5-72

Sense Amplifiers

5.19.29 Inhibit Driver Load Gates
During read, the content of the selected core is stored in the sense amplifier latch and passes through gate E7 to the MD
bus (Figure 5-73). MD DIR TIME 2H will be high during read time. The same data signal will be on the input to the last
inhibit gate, E13; thus, the inhibit driver will turn on when the INHIBIT TIME 2A L pulse is applied to NAND gate E l 3
during the write portion of the cycle.
5.1 9.30 Inhibit Drivers
The inhibit driver for bit 0, shown in Figure 5-74, supplies inhibit current to the selected core when a 0 is to be written. A
zero will be represented by a low state on pin 2 of E l 3. For the inhibit time period, pin 3 will be pulsed low and pin 1 will
go high. Current will flow into the base of Q13, which will saturate. The collector of Q13 swings from +20 V down to
1.4 V. C83 acts as a low impedance source of current, which flows from C83 through D63, through the lower primary
winding, and through Q13 to ground.

The initial primary current drawn from C83 may reach a peak of 600 to 800 mA. As a result of the high peak primary
current, which' lasts for 60 ns, the rise time of the transformer secondary is significantly improved. The proper value of
capacitor in C83 will optimize the rise time of the secondary current without causing overshoot.

FROM SENSE
AMPLIFIER LATCH^

TO INHIBIT DRIVER
MD DIR TIME 2 H
I N H I B I T TIME 2 A L

Figure 5-73

Inhibit Drivers Load Gates

INHIBIT
TIME 2 A L

Figure 5-74

Inhibit Drivers Bit 0

Following the current rise time, the primary current amplitude is determined by the limit resistor R37. The current in the
secondary will build up with a rise time of approximately 100 ns. Diodes D l and D2 will be forward biased and a current
of z 6 5 0 mA will flow into the stack at pin J1. The sense inhibit winding is split, with 4 K cores on each half. The current
will divide equally in the stack and will return to the G649 base board and ground via pins J2 and J3.
At the end of the inhibit timing pulse the base of Q13 will go low and Q13 will turn off. During turnoff the collector of
Q13 will swing positive causing Q1 to conduct and recharge C83.
5.19.31 Current Source
The X current source is illustrated in Figure 5-75. The current source is a pulsed source which produces a current
width dependent on a timing input to E42. The current amplitude is adjusted by the use of jumpers W5-W8 (Table
5-16).

The jumpers are set at the factory and under no circumstances should they be modified in the field. The setting is made by
cutting combinations of jumpers. Sixteen discrete steps in reference voltage may be obtained by the jumper combinations
shown in Table 5-16. Each step is equal to 0.08 V. Nominal reference voltage is approximately 13.9 V @ 25O C.

A voltage is created by Zener diode D l 37 and is further adjusted by the following networks. R78 and the thermistor
network make up a divider to establish the value of the reference voltage at the non-inverting input of comparator E37.
The reference voltage can be adjusted for a current which gives an optimum margin by clipping one or more of the
jumpers W5-W8. The thermistor network, which consists of R92, R58, and R59, will cause the reference voltage to vary
as a function of temperature.
This reference voltage is buffered and applied to output transistors Q33 and Q34. Q36, Q37, and Q32 act as on/off
switches while the rest of the path of the reference voltage is linear.
When the READMRITE CURRENT TIME H signal goes high, Q37 turns on and Q32 turns off; thus, the reference voltage
appears at the collector of Q32 and across the load resistors R76 and R75. The base of Q34 will swing from 4-20 V
down to a V(REF) which is approximately 14.0 volts. Q34 will turn on, providing base current to Q36, which conducts
and causes current to flow into the stack through diodes D l 35 and D l 36. Q33 and Q35 are in parallel with Q34 and
Q36 and provide one half of the load current. The X current path has been described and the Y path is identical to the X.

5.19.32 POWER NOT OK
If a power supply is not within limits, POWER NOT OK L will be low at the input to 0 3 1 (Figure 5-76). 0 3 1 and 0 2 9 will
be off and Q30 and Q28 will be on, clamping the base of Q34 in Figure 5-75 to approximately 4-20 V.

Table 5-16
V REF Jumpers

OUT
0 UT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

OUT

IN
IN

OUT

IN
IN
IN
IN

OUT
OUT

OUT

IN
IN

OUT

6
7

IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT

OUT

IN
IN

OUT

IN
IN
IN
IN

OUT
OUT

OUT

IN
IN

0UT

IN
IN

IN
IN
IN
IN
IN

1
2
3
4

High Voltage

8
9
10
11
12
13
14
15
16

Low Voltage

Q28

V-REFERENCE

POWER
NOT
OK L

Figure 5-76

POWER NOT OK Circuit

Q34 and Q36 will not conduct until the POWER NOT OK L signal goes high. While POWER NOT OK L clamps the output
transistors Q33 and Q34, no X current can flow to the stack. The Y current is also clamped by Q30. The memory will
continue to operate for 20 u s after the POWER NOT OK L signal goes low. This allows time for the processor to complete
any required storage. When the POWER NOT OK L signal goes high, the processor must wait 5 0 u s before the memory
can be cycled. This allows time for all filter capacitors in the memory to charge.

5.19.33 Test Points
All test points (Table 5- 17) for on-line testing are brought out to J 147, a 7-pin connector on side (1) of the G649 near the
handle. (Pins 1 and 7 are marked in etch on the module). This connector makes it possible to margin the STROBE and X
and Y drive currents by attaching a field service margining fixture. The connection of the margining fixture and the pin
signals are illustrated in Figure 5-77. Signals on certain test points are shown in Figure 5-78.

NOTE
Do not attempt to margin the G649, Etch C (MM8-AA);
the margins achieved will be too wide to be acceptable.

Table 5-17
Voltage Test Points

Name

Voltage (In Volts)

VXY HIGH
VXY LOW
VREF
VREF SET B
VREF SET A
STROBE

EB1
EE1 will be lower than VXY HIGH
ED1
EH1
EJ1
EM1
EV1 will be
.20Â 1
when BV2 i s .
.> 2.5
EV1 will be . . . . . . . . . . . . . . . . . . . .4.9 5 0.3
when BV2 is.
< 0.5

...................
..................

...................

Field Service Connector J147 Pin #

GND
SPARE
VXY LOW 1
VXY HIGH 1

1
t5V

2
STB

3
GND

4
SPARE

5
XY
LOW

6
GND

7
XY
HIGH
08-1208

Figure 5-77

T P NAME
SOURCE H

Margining Test Fixture Connections

PIN
0
NUMBER
AL2
J

5.5
STROBE TIME 2A H

DA1

CLEAR TIME L

DBl

1-'

350

8
880

10
1030

270

[
I

4 2 120

Figure 5-78

Test Point Signals

The memory may be margined in the following manner:

With the processor halted, connect the cable from the field service margining fixture to J 147, ensuring that
the pin numbers of male and female connectors agree.

Set the X/Y switch to the nominal (center off) position and the STB switch to the HIGH poisiton.

NOTE
The processor should always be halted before changing
either switch; only one parameter should be margined at
a time while the other switch is in the nominal (center
off) position.

Run any appropriate diagnostic, e.g., EXTENDED MEMORY DATA AND CHECKERBOARD.

Repeat steps 2 and 3 with the STB switch in the LOW position, making certain that the processor is halted
while changing switch positions.

Repeat the above steps with the STB switch in the nominal (center off) position while toggling the X/Y switch
first to X/Y HIGH and then to X/Y LOW.

Any diagnostic failure that can be attributed solely to this procedure will denote a marginal and therefore defective
memory system.
Use of the STB switch will result in a k 10 ns change in a strobe position. Use of the X/Y switch will result in a & 1 0 mA
change in X and Y current amplitude during both read and write.

5.19.34 Circuit Variables
There are a number of variables in the memory system, such as X/Y field address, current amplitude, and strobe position.
The field address is factory set at address 0 and may be changed by field service to fit the customer's application. This is
done by solder lugs and jumpers as described in Paragraph 5.19.22.
The X/Y current is factory set and should not be changed in the field.
The strobe position is factory set and should not be changed in the field.

5.19.35 Core Memory Troubleshooting
Some memory data errors and their possible causes are listed in Table 5-18.

Table 5-18
Memory Data Errors Possible Causes

Symptom

Cause

Check

One bit 1 or 0
One bit 1 or 0
RandomIAll 0
RandomIAll I
RandomIAll 1
RandomIAll = 1
Random = 0
Random = I

Inhibit
Sense Amp
XY Current Low
XY Current High
Inhibit Timing
Inhibit CurrentIVolt Low
Inhibit CurrentIVolt High
5 V Spec S.A. Threshold

Collector of 2N3725
Pin 13 of Sense Amp
VREF @ ED1
VREF 0 ED1
Collector Q25
+20 V
+20 V
CK VOLT 0 C122

5.20 M M 8 - A B 16K CORE MEMORY SYSTEM
The MM8-AB 16K core memory is similar to the MM8-AA 8K core memory described in Paragraph 5.1 9. The functional
differences between the MM8-AA and MM8-AB are as follows:
1.

Most component designations illustrated are different because of the difference in the quantity of components and board layout. Refer to the MM8-AB print set in ~ ~ p e n d H
i xfor component numbers and
locations.

On the MM8-AA, field selection is ac:complished by EMAO Land EMA1 L. On the MM8-AB, field selection is
accomplished by EMAO. EMA1 L is used in the inhibit timing, the strobe timing, and the Y axis decoding
circuitry.

There are two inhibit timing circuits and two strobe circuits in the MM8-AB.

The Y axis in the the MM8-AB is twice that of the MM8-AA in order to double core storage capacity.

In the MM8-AB, the inhibit 2-to-1 transformer has been repackaged in a single in-line transformer; the
number of transformers is twice that of the MM8-AA.

The number of cores on an X line is increased from 768 to 1536 in order to increase storage from 8K to 16K.

The organization of the MM8-AB memory system is illustrated in Figure 5-79. One hex size board with a piggy-back
H219B stack board is used to contain the memory system as follows:
1.

G650 baseboard contains 12 Sense Amplifiers, Memory Registers, and Inhibit Drivers with the corresponding control logic, current control, address decoding, selection switches, X-current source. Y-current source,
and power fail circuit.

H2 198 Memory Stack contains 1 2 mats of 16,384 cores per mat. X and Y diode selection matrix, and stack
charge circuit.

5.20.1 Assembly Of Twelve Core Mats
The MM8-AB Memory is a 128 X 128 configuration (12 8 X-rows and 128 Y-rows). This configuration provides 16,384
cores per mat, for which one core can be selected during any one memory cycle and therefore, one bit of information per
mat.
The memory stack component layout is illustrated in Figures 5-80, 5-81, and 5-82. Figures 5-81 and 5-82 illustrate the
X- and Y-windings within memory stacks.
The MM8-AB is a 12-bit word memory system; thus, 12 mats are used. Each mat stores one unique bit of information for
each address, which is detected and sensed by one unique line called the Sensehhibit line. SenseAnhibit lines are used
to detect and sense 1 2 unique bits of information. The arrangement of the X/Y select lines is quite different from inhibit.
All 12 mats contain 128 X-lines and 128 Y-lines.

5.20.2 Address Decoding Scheme
The block diagram in Figure 5-83 illustrates the method used to decode the MAR bits and the EMA bits. The process
turns on either a write or read source collector and the corresponding sink, thereby completing a current path through the
stack. The decoder is arranged as follows: The write selection decoders are on the left side of the illustration and the read
selection decoders are on the right side. The X selection decoders decode bits MAR5 L through MAR1 1 L. The Y
selection decoders decode bits EMA1 L, EMA2 L, and MAR0 L through MAR4 L. Both decoding schemes consist of a 16
X 8 matrix. The decoder outputs are applied to the selected switches. The outputs of the selected switches connect to
the selection diodes which, in turn, are connected to lines that are threaded through the memory cores. The arrangement
of the illustration (Figure 5-83) permits correlatio~nwith the engineering drawing schematics (G650).

, -

T P [ABl]
EMAO L

FIELD H

FIELD
SELECT

clRculT

ROM ADDR L Ã‘Ã‘
WRITE H

4
1
-

T S ~

W R I T E H , ~ ; ; ~
RETURN H
TIMING
SOURCE H

I N H TIME 2A L

MD D I R L

EMA1 L-

TS1
RETURN H

INHIBIT
TIMING
CIRCUIT

FIELD H

INHIBIT
CIRCUITS

ROM ADDR L

I N H TIME 2 B L

MOO L
MDl L

MD2 L
DRIVERS

MD3 L

RECEIVERS

MD4 L

EMA1 L

w
CIRCUIT

POWER
N O T OK L

POWER

CIRCUIT
SOURCE H
WRITE H

EMAl L

SOURCE H --m
WRITEHÃ‘Ã

CLEAR
CIRCUIT

CLEARTIMEL
SENSE CIRCUITS

a
DATA LATCHES

CIRCUIT

STROBE T I M E 2 A H
STROBE TIME

2B H

w
b
A

Figure 5-79

M M 8 - A 6 1 6 K Core Memory

"I-

[

ff
-

- STAC
I

" x " WRITE
(CURRENT)

1r
WRITE

rz:{ 1
CURRENT

DR
TIME L

MAR 9~

M A R 5~

MAR 8 L

Ã‘Ã‘
YOOO

‘+

MAR 9 L

SOURCE
COLLECTORS
"Y' READ
(CURRENT)

WRITE DR
TIME L

7442
ADDRESS
DECODER

MAR 2 L

MAR 4 L

READ
(CURRENT)

TS 1

- Y170

MAR 5 L

MAR 8 L
WRITE H INV

RETURN H

SOURCE H

7
STACK 7
- Y7
Y O 0 0 - Y170

75325
SINKS

75325
SOURCE
COLLECTORS

READ SINK

WRITE
SINK
TIME L

CONTROL LOGIC

7442
ADDRESS

1
I 1

SOURCE
COLLECTORS

CONTROL LOGIC

MAR 11 L

ADDRESS
DECODER
7442

RETURN H

STAC K

FIELD H SOURCE H

WRITE H BUF

TS 1

READ DR
TIME L
7442
ADDRESS
DECODER

CONTROL LOGIC

FIELD H

WRITE H

XOOO - X I 7 0

X7
A

+ Ã

+2 0 V

WRITE
SINK
TIME L

I I

7442
ADDRESS
DECODER

MAR 11 L

Y 'CURRENT
SOURCE

75325
SOURCE +
COLLECTORS

"Xu READ

XWRITE

READ DR

TIME L

7442
ADDRESS
DECODER

EMA1 L
EMA2 L
MAR0 L
MAR1 L

MAR 2 L

SOURCE H

Figure 5-83 Decoding of X and Y Driver
Current Sources Block Diagram

MAR 4 L

IÃ‘Ã‘Ã‘Ã‘Ã‘Ã

. .

EMAl L
MAR0 L
MAR1 L

- (CURRENT)
Y READ

The decoding scheme of the M A bits is illustrated in Figure 5-84. The illustration shows the five parts of the memory
address, plus what is decoded, and where in the field of the drawing the decoders are located. Table 5-1 9 lists the
necessary input control signals, the content of the memory address, the input pins, the output pins, and the selected Yline (the core selection decoding logic for the MM8-AB X-axis is identical t o that of the M M8-AA core memory). With this
information, the user can easily trace through all of the components o n any signaVcurrent path t o find the selected
components.

5.20.3 Operation Of The Core Selection Switches
The cores that contain a selected X-line and selected Y-line define the location in which a 1 or 0 will be either written in
or read out. Figure 5-85 illustrates a small portion of the memory core selection logic, which is similar t o the M M 8 - A A
core selection logic. The difference is that o n the MM8-AB, the X line is threaded through 1 5 3 6 cores instead of 768. The
Y decoding is similar and may be obtained from sheet 6 of the M M 8 - A B print set in Appendix H. Using Table 5-19, the
selection of any given core can be traced from the Memory Address Register through the decoders and switches t o the
selected line and core.
To select the Y read stack line No. 2 5 (octal) the procedure using Table 5-1 9 is as follows: A source collector switch to
select one end of the stack line and a sink switch t o select the other end of the stack line must be turned on together. This
completes the current path from the current source, through the source collector switch, through the selected stack line,
through the sink switch t o ground.
Addresses EMA1 L, EMA2 L, MAR0 L, and MAR1 L are decoded to select any 1 of 1 6 source collectors. In our example
w e are selecting the address combination that gives us binary 0 0 1 0 (octal 02).
Addresses MAR2 L, MAR3 L, and MAR4 L are decoded t o select any 1 of 8 sink switches. In our example we are
selecting the address combination that gives us binary 101 (octal 5). Table 5 - 2 0 shows selected stack lines for all
combinations of selected source collectors and selected sinks.

5.20.4 Read/Write Operation
The read operation involves the sense amplifier and the necessary control logic in conjunction with the selection system.
During the read portion of the memory cycle, the selected core develops a signal on the Senseiinhibit line only if a 1 was
previously stored in core. The sense registers in the sense amplifier are previously cleared and STROBE TIME 2AH or
2BH gates either a 1 or 0 into the sense register. When a 1 is sensed, the sense amplifier applies a low signal to the MDO
line (Figure 5-85).
The output of the core stack, which is stored in the sense register, is rewritten into the same core location during the write
half of the timing cycle. The M D DIR TIME 2 H pulse gates the sense register data to the inhibit drivers and places the
data on the M D bus where it is available t o the CPU or a peripheral device.

EMA

FIELD

MAR

"
X

WHATIS
DECODED

WHERE
DECODED

Figure 5 - 8 4

Decoding Relationships

Table 5-20
Core Selection, Y Read
Selected
Source
Collector

Selec id Sink
4

000
010
020
030
040
050
060
070
100
110
120
130
140
150
160
170
All numbers are in octal.

EMA1

L BUF

FIELD H
WRITE H BUF
ROM ADDR L BUF

INHIBIT
TIMING
DRIVER
038

I I
5
EMA1 L I N V
TS1
RET H

INHIBIT
TIMING
DRIVER
039

MD DIR TIME 2 H
INHIBIT TIME 2B L

CLEAR TIME L

INHIBIT TIME 2 A L

STROBE TIME 2 A H
STROBE TIME 2 B H

4096 CORES

INHIBIT
DRIVER

Figure 5-85

Inhibit Operation For Bit 0

5- 1 03

The write operation involves the inhibit drivers, load gates such as E7 and E8, the sense register, and the necessary
control logic in conjunction with the selection system. The inhibit driver load gates receive ones and zeros via the M D
lines from either the MB register in the processor or the sense register. Control gating signals for the inhibit driver load
gate are as follows:
TS1

+ RET H

FIELD H
ROM ADDR L BUF
EMA1 L BUF
EMA1 L INV
WRITE H BUF

Field Select Control Logic
The function and operation of the MM8-AB field select control loic (Figure 5-86) is the same as the MM8-AA, except the
inputs are different. The MM8-AB memory uses only one bit, EMAO L, as an input.
The MM8-AB is configured in 16K boundaries and can be expanded to 32K. Table 5-2 1 relates EMAO L to the assigned
memory address blocks and to the installed jumpers.

Table 5-21
Address Block Selection
Memory Address Block

Installed Jumpers

16K-32K

1-2 and 1-3
1-2 and 2-4

FIELD H
EMAO L

Figure 5-86

Field Selection Logic
5-10 4

5.20.6 Inhibit Control Logic
The top part of Figure 5-85 shows the inhibit control logic. The signals used to create the inhibit timing signals are listed
RET H determines the width of the
in Paragraph 5.20.4. All signals contribute to gating the inhibit operation while TS1
inhibit current pulse.

6.20.7 Sense Register Enable Logic
The Sense Register Enable logic is shown in the bottom half of Figure 5-85. When MD DIR TIME 2 H is asserted, the
content of the sense register is gated onto the MD line and to the inhibit driver.
5.20.8 Sense Register Clear Timing
The logic that generates the CLEAR TIME L signal is shown in Figure 5-87. SOURCE H generates the CLEAR TIME L
signal at E42; the trailing edge of the signal is determined by the output of the STROBE one-shot multivibrator (E51). The
timing relationship is illustrated in Figure 5-88.

STROBE SET

SOURCE H INV

SOURCE H B U F i
SOURCE H

WRITE H INV-

WRITE H
- D

CLEAR
TIME
E48

Figure 5-87

Clear Time Control Logic

TIME IN MICROSECONDS

1.0

1.1

1.2

1.3

1.4

1
jT

SOURCE H BUF

SOURCE H INV

WRITE H INV

STROBE ( $ 1

CLEAR TIME (0)

CLEAR TIME L

STROBE TIME ( 1 )

STROBE

TIME 2A/2B H

I
^r-^i
Figure 5-88

Strobe and Clear Timing

5.20.9 Strobe Control Logic
The Strobe Control logic is shown in Figure 5-89, The timing signals that generate the strobes are shown in Figure 5-88.
SOURCE H INV triggers the STROBE one-shot, E51, and the trailing edge of the one-shot clocks the STROBE TIME flipflop, E48. The output of E48 determines the leading edge of the STROBE TIME 2A/2B H signals; the trailing edge is set
by SOURCE H going low. The width of the STROBE one-shot output is proportional to the amplitude of the constant
current supplied by (237. The current in Q37 and, hence, the position of the strobe signals can be adjusted by jumpers in
the emitter circuit of (237. The jumpers, W9 through W12 (shown in the G650 logic drawings in Appendix HI, are
counterparts of jumpers W9 through W 12 in the MM8-AA memory (Figure 5-71); hence, Table 5-1 5, which relates
jumper placement to the STROBE one-shot output, applies to both memories.
5.20.1 0 Strobe Setting Jumpers
The operation of the strobe circuit, adjustment, and jumper installation is the same as that for the MM8-AA which is
described in Paragraph 5.19.26.

EMAl L INV
EMAl L

EMAl L B U F i

ROM ADDR L BUF

=q+

STROBE TIME 2B H

STROBE TIME 2A H

ROM ADDR L

STROBE SET

, 1

+5v H

STROBE * 3 7

SOURCE H INV

0
WRITE H INV

STROBE
E51

- STROBE ' Â¡
TIME
E48

o r

SOURCE H BUF

Figure 5-89

Strobe Control Logic

6.20.11 Inhibit Driver Load Gates
During a read operation, the content of the selected core is stored in the sense amplifier latch. The stored output is fed to
pin 2 of E7 and is gated onto the Omnibus by M D DIR TIME 2 H (Figure 5-90).
The read data is also present at pins 3 and 12 of E l 2. The inhibit winding for the M M 8 - A 6 is divided into two 8 K
windings. One of the two inhibit windings is selected at E l 2 by timing signals INH TIME 2A L or INH TIME 2B L. These
timing signals are generated from the memory address.

M D DIR T I M E 2 H
TO INHIBIT
DRIVERS

Figure 5-90

Inhibit Driver Load Gates

5.20.12 Sense Amplifier
The sense amplifier logic of the MM8-AB is identical to that of the MM8-AA, described in Paragraph 5.19.27, but the
application is different in the MM8-AB. Input pins 6 and 7 (Figure 5-72) are connected to an 8K sense line and a second
strobe line (STROBE TIME 2 8 HI on pin 11 is added to control the additional 8K sense winding.
One dual sense amplifier is fed by the 8K sense lines and the two strobe signals, STROBE TIME 2A/2B H, determine
which of the two sense lines is selected. A resulting logical one signal is gated into the single latch circuit on the amplifier
output.

5.20.13 Inhibit Drivers
The inhibit drivers shown in Figure 5-9 1 are an expansion of the M M8-AA drivers shown in Figure 5-74. Each bit requires
two inhibit drivers to supply inhibit current to each of its two 8K windings. Since only one of the two drivers is on at a
given time Q1, C1, D5, and R31 are shared. A zero is represented by a low on pins 3 and 1 2 of E12, For the inhibit time
period, either INHIBIT TIME 2A L or INHIBIT TIME 2 0 L is low, turning on either Q13 or Q14. If Q13 is selected and
saturated, its collector swings from +20 V down to 1.4 V. C1 acts as a low impedance source of current which flows
through D2, the primary winding, and Q13 back to ground. The initial surge of current in the primary winding significantly
improves the rise time of the stack current. The circuit recovery operation is similar to the MM8-AA recovery operation
described in Paragraph 5.1 9.30. C1 is recovered through Q1 during the fall time of the primary current.

INH IBIT DRIVERS

INHIBIT TIME 2 A L

Q13
11

13
014

Figure 5-91

Inhibit Drivers for Bit 0

5.20.14 Current Source
With the exception of component designations, the MM8-AB current source is identical to the MM8-AA current source
described in Paragraph 5.1 9.31. The same circuit with MM8-AB component designations is shown in Figure 5-92. Table
5- 16 also applies to the M M8-AB system.
A voltage is created by Zener diode D l 0 0 and is further adjusted by the following networks. R125 and the thermistor
network make up a divider to establish the value of the reference voltage at the non-inverting input of comparator E44.
The reference voltage can be adjusted for a current that gives optimum margins by clipping one or more of the jumpers
W5-W8. The thermistor network, which consists of R137, R1 19, and R120, causes the reference voltage to vary as a
function of temperature.
This reference voltage is buffered and applied to output transistors Q52 and Q53. Q48, Q57, and Q56 act as on/off
switches while the remainder of the path of the reference voltage is linear.
When the READ/WRITE CURRENT TIME H signal goes high, Q57 turns on and Q56 turns off; thus, the reference voltage
appears at the collector of Q56 and across the load resistors R93 and R94. The base of Q52 will swing from 4-20 V
down to a V(REF) which is approximately 14.0 volts. Q52 will turn on, providing base current to Q48, which conducts
and causes current to flow into the stack through diodes D97 and D98. Q53 and Q49 are in parallel with Q52 and Q49
(Figure 5-92) and provide one half of the load current. The X current path has been described and the Y path is identical
to the X.

5.20.15 POWEROK
The POWER OK circuit is shown in Figure 5-93. If a power supply is not within limits POWER OK will be low at the input
to Q40. Q40 and Q41 will be off, and Q42 and Q44 will be on, clamping the base of Q52 (Figure 5-92) to approximately
+ 2 0 V.
Q52 and Q48 will not conduct until the POWER OK signal goes to its high logic state. While POWER OK clamps the
output transistors Q52 and Q53, no X current can flow to the stack. The Y current is also clamped by Q42. The memory
will continue to operate for 2 0 u s after the POWER OK signal goes low. This allows time for the processor to complete
any required storage. When the POWER OK signal goes high the processor must wait 5 0 ps before the memory can be
cycled. This allows time for all filter caps in the memory to charge.

5.20.16 Test Points
The M M8-AB Test Points are the same as for the M M8-AA described in Paragraph 5.19.33.

V - REFERENCE

POWER OK

STROBE V- REF

Figure 5-93

POWER NOT OK Circuit

CHAPTER 6
PDP-8/A OPTION MODULES

The DKC8-AA I/O Option module (M83 16) and the KM8-A Extended Option module (M8317) are multi-option modules
designed specifically for the PDP-8/A computer. The DKC8-AA I/O Option contains a general purpose 12-bit word
Parallel I/O, a Serial Line Unit, Real Time Clock, and the Programmer's Console interface. The KM8-A Extended Option
contains the Memory Extension control, Timeshare, Power Fail/Auto-Restart, and the Bootstrap Loader. Other PDP-8
family computers provide these options or similar options on separate quad modules, but the PDP-8/A is designed to
accept hex sized modules allowing more than one option per module.
This chapter is divided into two sections, Section 1 describes the DKC8-AA I/O Option module and Section 2 the KM8-A
Extended Option module. Each section contains a block diagram description of the entire option, followed by a block
diagram description and detailed logic description of each component on the option. The installation and acceptance test
procedures for these modules are contained in Chapter 2. The detailed logic description of the Programmer's Console
interface on the DKC8-AA option is in Chapter 4.

SECTION 1
DKC8-AA 1/0 OPTION MODULE ( M 8 3 1 6 )

The DKC8-AA I/O Option Module (M8316) contains four PDP-8/A options on one hex size module (the module is
illustrated in Figure 2-1 5).
1.

A Serial Line Unit (SLU) for interfacing to 2 0 mA or EIA serial devices.

A General Purpose 12-bit parallel 110.

A Real Time crystal clock.

Programmer's Console interface which provides the interface between the Programmer's Console and the
Omnibus.

6.1 D K C 8 - A A 1/0 OPTION M O D U L E BLOCK D I A G R A M DESCRIPTION
Figure 6-1 is a block diagram of the DKC8-AA I/O Option Module. The options on this module are described in the
following paragraphs.

, PROGRAMMED INSTRUCTIONS

12 BIT WORD ( OUTPUT)
-

(MD3- MD11)
AC DATA

1/0 PAUSE L

GENERAL
PURPOSE
PARALLEL
I /O

SERIAL DATA ( INPUT)
S E R I A L DATA (OUTPUT)

I+*-

SKIP L
I

RQST L

I I

CONTROLS

SERIAL
DEVICE

SERIAL LINE UNIT
(UART AND BAUD 4
RATE GENERATOR)

DATA

PARALLEL
DEVICE OR
ANOTHER
POP-8/A

12 B I T WORD ( I N P U T )

AC DATA

INT

m
PROGRAMMER'S
CONSOLE
INTERFACE

DATA
CONTROLS

* PROGRAMMERS
CONSOLE

Figure 6-1

DKC8-AA I/O Option Module Block
Diagram

6.1 . I Serial Line Unit (SLU)
The Serial Line Unit (SLU) consists of a universal asynchronous receiver transmitter (UART) driven by a packaged oscillator. The SLU provides an interface for use between the PDP-8/A Omnibus and any asychronous external device
which has electrically compatible data leads and which operates w i t h one o f the serial data formats available with
this interface.
Operation of the SLU is via programmed I/O. The skip and interrupt request lines of the computer are used. Data
transfers are between the PDP-8/A Accumulator and registers in the UART.

6.1.2 General Purpose 12-Bit Parallel 1/0
The General Purpose Parallel I/O o n the DKC8-AA module allows the PDP-8/A t o transmit or receive one 1 2 bit
word a t a time between user designed logic o n single ended data lines, or t w o PDP-8/A processors t o transfer data
t o each other, provided each processor has a DKC8-AA I/O option board and the proper cables.
All data transfers are between the AC and an external device via programmed I/O, Data transfer rate is software limited t o 5 0 K words/second.

6.1.3 Real Time Crystal Clock
The Real Time Crystal Clock on the DKC8-AA module interrupts the processor every 1 0 m s ( 1 0 0 HZ k 0.01%) if
interrupt enable is set. A skip instruction (CLSK) causes the program t o skip an instruction if the clock flag is set.
A switch o n the M 8 3 1 6 module allows the clock to be disabled.

6.1.4 Front Panel Control
The front panel control logic on the DKC8-AA module provides the interface between the Programmer's Console and the
Omnibus. The front panel is connected t o the DKC8-AA b y t w o BC08S cables. Standard lengths are 1 foot (30.5 cm) and
1 2 feet ( 3 6 6 cm), but cables u p t o 1 5 feet ( 4 5 7 cm) are allowed when the panel is operated remotely.
The DKC8-AA contains the necessary control logic multiplexers, drivers, and receivers t o load the extended memory
and memory address registers and provide manual control o f computer operation. The controls on the Programmer's
Console are explained in Chapter 1. The detailed logic o n the Programmer's Console and the logic o n the DKC8-AA
associated with the Programmer's Console are discussed in Paragraph 4.3.

6.2 SERIAL LINE UNIT
The SLU block diagram is shown in Figure 6-2. The SLU has t w o distinct functions: Receives parallel data (characters) from the AC and shifts them out t o a serial device as serial data; and receive serial data from a serial device,
changes it t o parallel data and transfers it t o the AC.

6.2.1 SLU Specifications
The SLU specifications are as follows:
Drive Capability:

2 0 m A serial

(Driverdreceivers will function properly a t 1 10
baud with up t o 5 0 0 0 feet of 1 8 gauge or
larger twisted pair cable.)

EIA Serial

(Driverdreceivers will function properly with
up to 5 0 feet of cable.)

SLU Specifications (Cont) .
Baud Rates:

The following baud rates are switch selectable o n the M 8 3 1 6 module:

Transmit and receive baud rates must be the same,
Stop Bits:

One o r t w o (switch selectable).

Parity:

Parity is enabled by installing a jumper. Even or o d d parity is selectable
using a second jumper.

Device Codes:

0 3 receive and 0 4 transmit. No other device codes are provided for

Number of Bits
per Character:

The number of bits per character is jumper selectable between 5 and 8 .
Jumpers N B 1 and N B 2 are used t o select the number of bits per character as follows:

Number of Bits

NBI

N B2

IN
OUT
IN
OUT

IN
IN
OUT
OUT

The normal configuration is 8 bits per character.
Cables:

A B C 0 5 M - 0 - 0 in lengths of 15, 25, or 5 0 feet connects to J 3 on the
M 8 3 16 module.
The end of the cable that connects t o J 3 o n the M 8 3 1 6 module is a
6 5 0 4 - 1 5 male Berg connector and the other end is a Mate-N-Lok female connector.

Modems:

The SLU will accommodate Bell 103A/E/F/G/H, 203/D, and 1 1 3 B or
equivalent type modems. A BC01V-25 cable must be purchased separately t o make connection t o the modem. The transmit and receive data
leads, (Data terminal ready and request to send) are permanently enabled are activated by this cable. The modem system must be a fullduplex dedicated line type modem. Furthermore, the READER RUN feature, normally present o n local terminals, cannot be used.

6.3 SLU FUNCTIONAL DESCRIPTION
The SLU uses a Universal Asynchronous Receiver/Transmitter through drivers and a cable t o the external device. The
UART performs serial t o parallel (receive) and parallel t o serial (transmit) conversion of data received from or sent t o
a serial device.

RECEIVE
DATA AVAILABLE

CONTROL
LOGIC

SER IA L
DEVICE

m+)

DECODE

TRANSMIT
BUFFER EMPTY ( TBMT)

1
P A R A L L E L DATA FROM B
P/0

DATA STROBE
TRANS

SERIAL
DATA OUT

TRANS
BUFFER

PARALLEL DATA OUT

M8316

08-1267

Figure 6-2

Serial Line Unit Block Diagram

Timing for the UART is derived from a 5.0688 MHz crystal oscillator and a network of frequency dividers. The frequency of the clock applied t o the UART is determined by the Baud rate (its frequency is 16 times the Baud rate)
which is switch selectable.
The SLU is operated via Programmed I/O. Instructions and data are received from the processor by way o f the Omnibus. The programmed instructions are decoded by 2 instruction decoders which are enabled when I/O PAUSE L is
asserted (low) on the Omnibus and either device code 0 3 or 0 4 is detected by the device select decoder. When this
happens, Internal I/O L is also asserted (low).
The UART operation can best be understood by dividing the operation into t w o functions. A block diagram description of these functions is given in the following paragraphs.

6.3.1 Methods of Data Transfer
Data transfers between the AC and registers in the SLU may take place via Programmed I/O or Programmed Interrupts. The processor is interrupted by an INT RQST if the interrupt enable flag is set and the RECEIVE or XMIT flag
sets. SKIP is asserted if the XMIT or RECEIVE flag sets while flags are being checked by the program.
6.3.2 Transmit Operation
Figure 6-3 is a block diagram of the UART transmit operation. The transmit portion of the UART receives an eight
bit parallel character and changes it t o 8 bits o f serial data for transmission t o a serial device. Bits 5, 6, and 7 are
zeros if they are not used. The number of bits/ctiaracters is selected by installing jumpers (see Table 6-2).

SERIAL
OUTPUT

XD06
XD 0 5
IT
rA
TER

XD04

v n n ~

m
XMTR
SHIFT
REGISTER

GU
TRANSMIT BUFFER EMPTY

Figure 6-3

Transmitter Block Diagram (UART)

A transmit operation is started when the XMIT flag is set and parallel data is transferred from the AC to the DATA
BUFFER register. A TRANSMIT DATA strobe is given loading the holding register. At this point TBMT is brought
low by the UART. On the next transition of the transmit clock, the Holding register is transferred to the transmit shift
register. TBMT is then allowed to go high setting the transmit flag. The transmit flag signals that the Holding register is empty and ready for another word. The DART then shifts out the word appending start and stop bits as required.

6.3.3 Receive Operation
A block diagram of the receive operation is shown in Figure 6-4, The receive portion of the DART will receive serial data
from a serial device and change it to parallel data for transfer to the AC. Data from the device is assembled in the
Receiver Shift register and transferred to the Data Holding register as parallel data. At this time, DATA AVAILABLE is
asserted by the UART, the RECEIVE flag is set and the data should be transferred to the AC. Meanwhile, serial data from
the device is available for transfer to the Data Holding register. The RECEIVE flag is cleared when the content of the Data
Holding register is transferred to the AC.
6.3.4 SLU Timing Generator
Figure 6-5 is a block diagram of the SLU timing and baud rate generator. A 5.0688 MHz crystal oscillator and a
programmable divider generate the clock signals required for the baud rates listed in Figure 6-5. The SLU clock signal is
16 times the selected baud rate. Different baud rates for transmit and receive are not allowed, thus the same clock is
used for both transmit and receive operations. The baud rate is selected by 3 switches which supply inputs to the Baud
rate selector.

DATA BITS T O AC
r

1 DATA HOLDING REGISTER 1
SERIAL
DATA
INPUT

RECEIVER SHIFT REGISTER

r
Ã‘^
I

DATA AVAILABLE

EVEN

PARITY
SELECT

Figure 6-4

NO
PARITY

~ 8 2
NBI
NUMBER OF
BITS/CHARACTER

o8-, 263

UART Receiver Block Diagram

5.068
MHz
OSCILLATOR

2 4 0 0 Hz
-(FOR
REAL-TIME
CLOCK)
BAUD RATE

CLOCK FREQUENCY
(Hz)
800
1200
1760
215 2
2400
4800
9600
19.2K
28.8K
3 2K
38.4K
57.6K
76.8K
1 1 5.2K
1 53.6K

B A U D RATE
SELECT
SWITCHES

BAUD
RATE
GENERATOR

SLU CLOCK

- (16X B A U D
RATE)

Figure 6-5

Timing Generator Block Diagram

6.3.5

Parity Generation
Parity generation and checking may be enabled by grounding pin 32 on the UART chip. If this pin is not grounded
(normal configuration) the UART will not check parity during receive or generate parity on transmit operations.

An Odd Parity Check is made if pin 39 on the UART is grounded and Even Parity Check is made if it is not.

6.3.6 Number of Bits Per Character
The number of bits per character may be 5, 6, 7, or 8 depending on jumper configuration of pins 37 and 38 of the DART
(Table 6-2). The pins are grounded by using insulated wire jumpers to tie them to any point on the M8316 module which
is grounded (drawing number D-CS-M8316-0-1),
6.4 SLU PROGRAMMING
The SLU IOT instructions are as follows:
Receive Instructions (Device Code 03)
Mnemonic

Octal Code

Function

KCF

6030

Clear receive flag, do not set reader run, do not request a new character from
the reader if it is in operation, do not clear the AC. Reader run is automatically cleared by the new incoming character.

KSF

6031

Skip if the receive flag is set.

KCC

6032

Clear receive flag and AC, set reader run.

KRS

6034

Inclusive OR receive buffer into the AC.

KIE

6035

Load AC11 into interrupt enable for both receive and transmit.
AC11 = 1. Enable interrupt
AC11 = 0. Disable interrupt

KRB

6036

Combined KCC and KRS. Clear flag, load AC with contents of receive buffer,
and set reader run.
Transmit Instructions (Device Code 04)
Function

Mnemonic

Octal Code

TFL

6040

Set transmit flag.

TS F

604 1

Skip if the transmit flag is set.

TCF

6042

Clear transmit flag.

TPC

6044

Load AC into transmit buffer and transmit.

SP I

6045

Skip on transmit or receive flag if interrupt enable is set to a 1.

TLS

6046

Combined TCF and TPC commands.

6.5 SLU DETAILED LOGIC DESCRIPTION
The SLU Logic is divided into functional groups for discussion purposes. The block diagram in Figure 6-2 should be
used to understand the interaction of the logic, the signal flow within the SLU and the input or output signals.

6.5.1 Device Select Logic
The device select logic for the SLU and the Real Time Clock are shown in Figure 6-6. M D 3 and M D 4 are gated by
I/O PAUSE L t o enable the device select ROM, when a 603X. 604X, or 613X instruction is decoded. The device select ROM asserts Internal I/O L for either of these instructions t o cause the positive I/O interface t o ignore these IOT
instructions.

6 O 3 X +604X+613X
DEV ICE
SELECT

INTERNAL
110 L ( CLI)

ENB

ROM #1 (E21) TRUTH TABLE
PIN
TRUE
NUMBER STATE FUNCTION ENABLED
C0DE;:tJT)
SLU RECEIVE
1
LOW
LOW
SLU TRANSMIT
604X
2
LOW
INTERNAL I10 L
603X + 604X + 613X
3
REAL TIME CLOCK
5
LOW
613X

INSTRUCTION OCTAL

I / O PAUSE L

Figure 6 - 6

SLU and Real Time Clock Device Select Logic

The device select ROM also decodes M D 5 - MD1 1 to generate three signals 603X, 604X, and 613X to enable the
operation decoders for SLU and Real Time Clock. The truth table in Figure 6 - 6 gives the function enabled by the inputs t o the device select ROM.
IOT instructions for the SLU are listed in Paragraph 6.4. ROM patterns for the SLU are contained in the M 8 3 1 6 engineering drawing in Appendix I.
6.5.2 SLU Operation Decoder
The SLU operation decoder is shown in Figure 6-7. The operation decoder consists of a ROM (E20) and a BCD to
decimal decoder (E25) t o decode M D 9 - MD1 1. The BCD t o decimal decoder is enabled by the signal 604X from
the device select logic and decodes M D 9 - MD1 1 to assert signals for the 6040, 6041, and 6 0 4 5 instructions.
The ROM (E20) is addressed by M D 9 - MD1 1, 603X, and 604X t o decode the remainder of the SLU instructions (ROM
No. 2 truth table in Figure 6-7).
The operation decoder supplies signals that represent the 603X and 604X instructions.
COL and C1 L are asserted t o control the direction o f data transfer o n the Data Bus (see Table 6 - 1).

B BUF MD11 H

3 BUF MD10 H

KLDK

ROMW2

KLDK 4 4

+46 H

KLDK 3 4

+ 36 H

KLDK 3 5

E20
5

B BUF M D 9 H

SL"
^OPERATION

R O M # 2 ( â ‚ ¬ 2 TRUTH T A B L E
INSTRUCTION OCTAL
CODE ( I N P U T )
PIN NO.
6030 6032t6036
1
3
6032 6036
7
6034 t 6036
6032 6034t6036
4

SLU

L
STATE

TRUE
STATE
HIGH
LOW
HIGH
LOW

B B U F MD11 H

^DO

Figure 6-7

t^>SLU Operation Decoder

Table 6-1
COL and C1 L Levels for Data Bus Transfers
Instruction

COL

C1 L

Direction of Transfer

6032
6034
6035
6036
6044
6046

High
High
High

High

Low

High

Low

High
High

Data Bus; 0
Data Bus -> AC
AC -+ Data Bus
Data Bus AC; 0
AC Data Bus
AC -^ Data Bus
-+

6.5.3 SLU Interrupt and Skip Logic
The interrupt and skip logic is used to interrupt the the program when a data transfer is required. To allow an interrupt, the INT EN flip-flop (E52) must be set by the 6035 instruction (Figure 6-8). The output of INT EN is gated
with RCV FLAG or XMIT FLAG t o assert INT RQST L when these flags are set. FCV FLAG is set when there is a
character in the Receive Buffer register and XMIT FLAG is set when the transmit Buffer register is empty.

INITIALIZE H

Ã‘
E 22

B BUF I N I T L

E69

74LS74

KLDK R C V FLAG

K L K L 2 RCD
DATA AVAI L H

74 LS74

I N T ROST L (CP1)

SKIP L (CSI)

+3V

K L K L 2 XMIT
BUFF MT H

ID l i KLDK XMIT FLAG
74LS74

8 BUF I N I T H

Figure 6-8

SLU Interrupt and Skip Logic

SKIP L is asserted when the RCV FLAG is set and a 6 0 3 1 instruction is executed or when the XMIT FLAG is set
and a 6 0 4 1 instruction is executed. Assertion of SKIP L (low) causes the program t o skip an instruction.
A more detailed description of the Interrupt and Skip logic can be found in Chapter 4.

6.6.4 SLU Timing Generator and Baud Rate Select Logic
The SLU Timing Generator is shown in Figure 6-9. The Timing Generator consists of a 5.0688 MHz oscillator and a dual
baud rate generator. The SLU CLK signal is 1 6 times the baud rate selected by S1-1 through S1-4 (Figure 6-5). The SLU
CLK is applied to the UART as both the receive and transmit clock (both are the same frequency). Thus, split baud rates
are not available.
The dual baud rate generator is a programmable divider (see block diagram). The switches S1- 1 to S1-4 will select the
frequency for the SLU. See Table 6-2 for SLU baud rate switch settings. A second fixed frequency of 2 4 0 0 Hz is also
generated for use by the real time clock.

LJ
OSCILLATOR

Hz
-2400
(FOR REAL-TIME

CLOCK1

Fg :
S1-2

Figure 6-9

J-

-(16XSLU CLOCK
BAUD
RATE)

SLU Timing Generator and Baud Rate Select Logic

Table 6-2
D Etch S L U Baud Rate Select Chart
Baud Rate

Sl-2
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
*OFF

ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF

ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF

*Serial line will not r u n a t this baud rate. T h i s setting is not t o b e used.

6-13

6.5.5 Universal Asynchronous Receiver/Transmitter (UART)
The UART (Figure 6-1 0) is a full duplex device with a receive and transmit section. The receiver section accepts serial binary characters from a serial device and converts them to a parallel format for transmission t o the AC via the
Data Bus. The transmitter section receives data in parallel format from the AC via the Data Bus and converts them
t o a serial data for output to a serial device. Table 6 - 3 lists the signals required t o operate the UART in the SLU.
The receiver block diagram (Figure 6-4) and transmitter block diagram (Figure 6-3) should be studied t o understand
the functional logic inside the UART.

UART Receive Operation - EIA or 2 0 mA serial data is received from a serial device (Figures 6 - 1 0 and
6.5.5.1
6 - 1 1) and converted t o TTL levels (Paragraph 6.5.6). Each data character contains a start bit, 5, 6, 7, or 8 data bits
and one or t w o stop bits (Figure 6 - 1 1). The number of data bits and stop bits are switch selectable (see Table 6-2).
The stop bits are opposite in polarity to the start bits.
The converted serial input is used t o supply an i~nput o SERIAL IN on the UART. The signal is jumpered t o pin E of
J3 by installation o f the proper cable for EIA or 2 0 mA operation.
The DART internally synchronizes the start bit with the clock input t o ensure a full 1 6 clock period and keep the
start bit independent of the time of data loading. The input bit is strobed at the center of the bit &8%. A start bit
that lasts for less than 1/2 of a bit time is rejected by the receiver.
When the receiver is in the idle state, it samples the serial input at the selected clock edges after the first low to
high transition of the serial input. If the first sample is high, the receiver remains in the idle state and is ready t o detect another low to high transition. If the sample is low, the receiver enters the data entry state.
There is no provision t o detect parity errors in the received data, however data transmitted to a serial device may
have an even or odd parity bit included in the data character (Table 6 - 2 and Figure 6 - 1 1).
The serial data is shifted into the UART a bit at a time and the occurrence of a stop bit indicates that the entire character has been received and shifted into the shift register. After the stop bit(s) has been sampled the receiver control
logic parallel transfers the content of the Shift register to the Data Holding register (Figure 6-4) and asserts RCD
DATA AVAIL H. RCD DATA AVAIL H sets the the RCV FLAG which pulls RESET AVAILABLE t o clear Data Available and the processor will be interrupted t o do a data transfer (Paragraph 6.5.3). Data is out on the Data Bus and
transferred t o the AC by the 6 0 3 4 or 6 0 3 6 instruction.

E I A I T T L RCVD DATA ( J 3 - M )

t
2 0 MA RCVD DATA ( J 3 - H 1

-- -

JUMPER BETWEEN
P I N S E AND M

KLDK 3 4 + 3 6 H

DA
OR ERR

K L K L I T T L SER DATA IN ( J 3 - E )

FR ERR

K L K L 2 RCD
19 DATA AVAIL H

JUMPER BETWEEN
PINS E AND H

P ERR
RD 7

+
KLKL1 SLUCLK

RDA
STB ST

R CLK
RD5

SERIAL I N

B BUF DATA4 H
XD7
B B U F DATA5 H

RD6

STB RD

xD6

RD4

E 47
UART
1602A

RD3

XD5
B BUF DATA7 H

XD4

B BUF D A T A 9 H

XD2
CLR

CLK

BBUF T P 3 H

RD 2

XD3

XDl

RD 1

DATA10 L (DUD

XDO

L D XO
RDO

X CLK

B BUF T S 4

DATA11 L ( D V I )

-1 2 V
SERIAL OUT
XBMT

K L K L 2 S E R I A L OUT
K L K L 2 X M I T BUF M T H

EOC
:LR LDC NB2NBI NP EP 2 ~ 6 2 1 3 4 37 3 8 3 5 3 9 3 6

7
1

+3V
OFF.2

STOP
BITS

s7-7

B BUF DATA 1 0 H

B B U F POWER H

BBUF TP1 H

Figure 6-10

Format of Input/Output Character

POWER OK L ( B V 2 )

Table 6-3
DART Signal Functions
Pin No.

Name

Function

Received Data

Eight data out lines. RD7 (pin 5) is the MSB and RDO (pin
12) is the LSB. When 5, 6, or 7 bit character is selected, the
most significant unused bits are low. Character is right
justified into the least significant bits.

PERR

Receive Parity

Not used.

FR ERR

Framing Errolr

Not used.

OR ERR

Overrun

Not used.

STB ST

Strobe Status

When asserted low, the transmit buffer output is applied to
the output lines.

CLK

Receiver Clock

Input for an external clock whose frequency must be 16
times the desired receiver baud rate.

RDA

Reset Data
Available

When low, resets the received DA (Data Available) line.

Received Data
Available

Goes high when an entire character has been received and
transferred to the receiver Holding register.

SERIAL IN

Serial Input

Input for serial asynchronous data.

CLR

Clear (reset)

When power is turned on, this line is pulsed high by Power
OK which resets all registers, sets serial output line high, and
sets transmitter buffer empty line high.

XBMT

Transmitter
Buffer Empty

Goes high when the transmitter Data Holding register may
be loaded with another character.

LD XD

Data Strobe

Pulsed low to load the data bits into the transmitter Data
Holding register during the positive-going trailing edge of
the pulse.

EOC

End of Character

Not used.

SERIAL OUT

Serial Output

Output for transmitted character in serial asynchronous
format. A mark i s high and a space i s low. Remains high
when no data is being transmitted. Unused bits are held low
out of the UART.

Data Input

Eight parallel Data In lines. XD7 (pin 33) is the MSB and
XDO (pin 26) is the LSB. If 5, 6, or 7 bit characters are
selected, the least significant bits are used.

Load Control

Not used.

Mnemonic

Table 6-3 (Cont)
UART Signal Functions
Pin No.

Mnemonic

Name

Function

No Parity

When high, eliminates the parity bit from the transmitted
and received character and drives the received parity error
line low. As a result, the receiver does not check parity on
reception and during transmission the stop bits immediately
follow the last data bit.

2 SB

Two Stop Bits

Selects the number of stop bits that immediately follow the
data bits. A low inserts 1 stop bit and a high inserts 2 stop
bits.

NB2, NBI

Number of Bits
per Character

Select 5, 6, 7, or 8 data bits per character as follows:

Even Parity Select

Selects the type of parity to be added during transmission
and checked during reception. A low selects odd parity and
a high selects even parity.

X CLK

Transmitter Clock

Input for an external clock whose frequency must be 16
times the desired transmitter baud rate.

START

ASYNCHONOUS
SERIAL I N

1\ 1

P A R A L L E L DATA OUT
(RD1- R D 8 )

STOP

DATA

RECEIVED DATA
A V A I L A B L E (DA)

DATA

,
I

RESET DATA
AVAILABLE ( D A )

START

STOP

Figure 6-1 1

Receiver Timing Diagram

6.5.6.2 UART Transmit Operation - A transmit operation (Figure 6-10 and 6-12) is started when a parallel data
character is transferred to the UART Data Holding register from the AC. The Data Buffer register (EBB) is loaded by an
6044 or 6046 instruction at TP3H time. The data is then loaded into the Data Holding register during TS4. The 6046
instruction also clears the transmit flag.

PARALLEL DATA INPUT

DATA STROBE ( DS

TRANSMITTER BUFFER
EMPTY

x
NOTE 1

7
STOP

ASYNCHRONOUS
S E R I A L OUT

DATA

NOTE 1
Set transmit flag.

Figure 6-12

Transmitter Timing

The data is immediately transferred from the Data Holding register into the Shift register by the UART control logic.
During this transfer the internal UART Control Logic will add Parity or no Parity, the stop bits, and provide for the
correct number of data bits. The format is determined by the STOP BITS switch 6 7 - 7 ) and jumpers installed on the
UART pins (Table 6-2.) After the transfer is complete, XMIT BUF MT H is asserted to set the XMIT FLAG. A t this
time the program is interrupted for another data transfer (Paragraph 6.5.3).
The transmit flag is always cleared during a power up or initialize operation.

6.5.6 Level Converters
Level conversions are provided on both the receive and transmit lines between TTL levels of ground and 4-3 V to
either EIA levels of A1 2 V or 2 0 mA current loop of operation.
The receive converter logic is shown in Figure 6-13. The EIA DATA IN at J 3 pin 5 is converted t o TTL levels by E78
and then fed t o pin M. A jumper on the cable for EIA devices feeds the signal t o pin E and it is applied as input t o
the UART SERIAL I N pin.
In the 2 0 mA converter logic, Q7 and Q8 are normally turned off until the current goes above a threshold of 1 0 mA,
A current greater than 1 0 mA turns Q7 on and a -10 mA turns Q8 on. When no signal is being received, Q7 and
Q8 are turned off. The differential changes at pms K and S are sensed by Q7 and Q8, amplified by Q9 and Q10, and
applied t o the latch flip-flop. The latch flip-flop (E77) is used t o eliminate noise on the receive line.

Switch S1-8 enables a filter when the ASR33 or ASR35 Teletype is the device connected t o the SLU.
The 2 0 mA RCVD DTA data on pin H is jumpered t o pin E by the cable used with 2 0 mA devices and it is applied
to the SERIAL I N input on the UART.
The transmit level conversion for EIA data is done by E38 (Figure 6 - 14). E38 receives TTL data ( 0 and 3 V levels) from
UART SERIAL OUT and changes it to -12 V levels.
In the TTL t o 2 0 mA conversion logic, a low out of E63 produces a low at the base of Q4 (the series transistor) es5 to -1 5 V. This provides a bias to enable Q5 and Q6. The conduction of Q5 and
tablishing a voltage divider from
Q 6 establishes a differential current source for the 2 0 mA current loop through the external device.

6.5.7 Reader Run Logic
The RDR RUN flip-flop (Figure 6-1 3) is set when a 6032 or 6 0 3 6 instruction is executed by the program. When
RDR RUN is set, Q3 conducts and energizes the Reader Run relay in the external device.

E I A DATA OUT ( J l - F )

K L K L 2 S E R I A L OUT

E63

Figure 6-14

INT RQST

2 0 MA X M I T - ( J l - K K )

---

M A G N E T OR
EQUIVALENT
TRANSISTOR
AMPLIFIER

TTL to EIA and 20 mA Converters

INTERNAL 1/0 L

INTERRUPT
ENABLE

CLEAR CLOCK FLAG

DECODER

DATA 11 H
( FROM THE AC )

INTERRUPT &
SKIP LOGIC
+

INTERRUPT
ENABLE
FLIP FLOP

SKIP ON FLAG

SKIP L

Figure 6-'15

Real Time Crystal Clock Block
Diagram

The divide by 1 0 counter (E59) provides for detection of noise spikes or random data on the receiver data line and the
occurrence of a pulse that is shorter than 1/2 of a bit time.
The counter does not count until Reader Run sets, because AND gate E65 is disabled and a high is supplied to the CLR
input of the counter. When RDR RUN sets, the start bit on the other input to NAND gate E65 enables the gate and
removes the high input to CLR. The counter starts counting and after 8 clock pulses or 1/2 of a bit time, the RDR RUN
flip-flop is cleared. This disables the AND gate and stops the counter.

6.6.8 Request t o Send and Terminal Ready
For modem operation, the RQST TO SEND and DATA TERM READY signals are always asserted (high) by a ground
applied to NOR gate E38 (Figure 6-13).
6.6 REAL TIME CLOCK
The Real Time Crystal Clock interrupts the processor every 1 0 ms if interrupt enable is set (10 0 Hz for &0.01%). A
Skip instruction causes the program to skip an instruction if the clock flag is set.
Figure 6-1 5 is a block diagram of the Real Time Crystal Clock. The 100 Hz clock signal is generated by a 5.0688
MHz crystal controlled clock and a group of frequency dividers. The CLK SEL switch enables the clock to be applied
to the CLOCK FLAG, which sets each time a clock pulse is generated.
When the CLOCK FLAG sets, the program is interrupted by INT RQST L if interrupts are enabled, or by SKIP L if the
program executes the Skip IOT.

6.7 REAL T I M E CLOCK PROGRAMMING
The instructions used to program the Real Time Crystal Clock are as follows:
Mnemonic

Octal Code

CLLE

6135

Function
Load the interrupt enable from the AC11.
A C I I = 1, set interrupt enable
A C I I = 0, clear interrupt enable
Interrupt enable is turned off when power is turned on and when the system
is initialized by I N I T on the Programmer's Console, or if the CAF instruction
is executed.

CLCL

Clear clock flag.

CLSK

Skip on clock flag.

6.8 REAL TIME CLOCK DETAILED LOGIC DESCRIPTION
The Real Time Clock logic is divided into functional groups for discussion purposes. Figure 6-1 5 should be used to
understand the relationship between the groups of logic and the flow of signals and data between them.
6.8.1 Device Select and Operation Decoder Logic
The device select logic for the Real Time Clock is the same as that for the SLU (Figure 6-61.When one of the Real
Time Clock instructions is detected, the 613X signal (Figure 6-1 6) enables the clock operation decoder (E25). E25 is
a BCD to decimal decoder which decodes MD<9: 11 to determine what operation the Real Time Clock will do.

BUF
INIT L

Figure 6-16

Real Time Clock IOT Decoder and Interrupt and Skip Logic

6.8.2 Real Time Clock Frequency Dividers
The Real Time Clock frequency dividers are shown in Figure 6-1 7. If TEST SWITCH (S1-6) is set to on to apply a ground
to the CLR input of the divide by 12 counter (E371, the counter is enabled. E37 is a modified divide by 16 counter which
has the divide by 2 output tied to the CLK BC input to cause a divide by 12 operation, and generation of a 2 0 0 Hz output.
The 2 0 0 Hz signal is applied to (a divide by two counter) to generate the 1 0 0 Hz TICK H signal which is used to set the
CLOCK FLAG (Figure 6-16) if S1-5 is set to ON.

KLKL 2+3V

KLKL 2 TICK H
100 Hz
Sl-5
C L K SEL

Figure 6- 17

TEST SWITCH

Real Time Clock Frequency Dividers

6.8.3

Real Time Clock Interrupt and Skip Logic

The interrupt and skip logic is used t o interrupt the program at a 1 0 0 Hz rate.
INT RQST L is asserted when the CLOCK FLAG sets if the CLOCK INTERRUPT ENABLE flip-flop is set. CLOCK INTERRUPT ENABLE is set by DATA1 1 from the AC being a one when the 6 1 3 5 instructions is executed by the program. SKIP L is asserted and the program skips an instruction if the CLOCK FLAG sets and 6137 instruction is
executed by the program.

6.9

GENERAL PURPOSE PARALLEL 1/0 BLOCK DIAGRAM DESCRIPTION

The General Purpose Parallel I/O (Figure 6-1 8) allows the PDP-8/A t o transmit or receive one 12-bit word at a time
between user designed logic on single ended data lines or t w o PDP-8/A processors t o transfer data t o each other,
provided each processor has a DKC8-AA I/O option board and the proper cables.
All data transfers are between the AC and an external device via programmed I/O. Data transfer rate is limited by
program execution time t o approximately 50K words/second.

DATA I N (DATA 0

- DATA 11

c
READY

DECODE
ONTROL
LOGIC

1 / 0 PAUSE L

AVAI L A B L E

INT
RQST

OUTPUT
BUFFER

I N T ENA
INTERRUPT
LOGIC

DATA OUT (DATA 0

Figure 6-18

- DATA 11

General Purpose Parallel I/O Block
Diagram

DATA O U T ( 1 2 B I T S )

FEATURES
Input/Output:

2 bits of parallel data input and output. Data is logic low true for both
transmit and receive operations.

Drive Capability:

Each output drives up to 25 TTL unit loads. Data In presents 4 TTL unit
loads to the driver circuit. Maximum cable length is 250 ft for transmit
or receive.

Signal Levels:

Logic High is 4.0 V to 2.6 V. Logic Low is 0.0 V to 0.6 V. All signals
are TTL compatible.

Cables:

All cables must be ordered separately. The BC08R cable should be used,
the standard length is 10 ft, but other lengths up t o 250 f t are available
on s,pecial order. Two cables are needed if both transmit and receive
functions are used. The BC80A-0-0 cable in lengths of 25, 50, and 100
f t are available for use with the LA180 printer.
Plug the Parallel I10 into Digital standard logic blocks. The use of one or
two M9lOO cables i s required.
To transmit data between two PDP-8/A computers, use two BC08R cables. Each cable connects J5 of one DKC8-AA to J4 of the other. The
cable must be turned over (connected backwards: pin A is plugged into
the pin VV end of the connector) at one end of each cable. (Tables 6 - 4
and 6-5).

6.10 GENERAL PURPOSE PARALLEL I/O PROGRAMMING
The following instructions are used to program the General Purpose Parallel I/O:

Mnemonic
DBST
DBSK
DBRD
DBCF
DBTD
DBSE
DBCE
DBSS

Octal Code

Function
Skip on Data Accepted, clear Data Accepted and Data Available, if Data
Accepted flag is set.
Skip on Data Ready flag.
Read data in to ACO-AC1 1.
Clear Data Ready flag, issue Data Accepted out pulse.
Load ACO-AC11 into buffer and transmit data out.
Set interrupt enable t o a 1.
Reset interrupt enable t o a 0.
I:jsue a strobe pulse.

6.1 1 DETAILED LOGIC DESCRIPTION
The General Purpose Parallel I/O logic is divided into functional groups for discussion purposes. The block diagram in
Figure 6-18 should be used to understand the relationship between the groups of logic.
6.1 1.1 Device Select and Operations Decoder
The device select and operations decoder logic is shown in Figure 6-19, Bits MD3 - MD8 are gated by I/O PAUSE
L when a 657X instruction is decoded to enable the operations decoder and assert INTERNAL I/O L. INTERNAL I/O
L causes the positive I/O bus interface to ignore this instruction.

The operations decoder (E25) decodes MD9 - ME11 1 to determine what operation is to be performed by the parallel 110.
E25 is a BCD to decimal decoder which decodes the 3 bits and asserts one of the output pins to represent instructions
6571 through 6577. When a 6752 instruction is decoded, CO L and C1 L are asserted (low) to allow data to be
transferred from the Data Bus to the AC.

Table 6-4
J4 Input Signal Pin Assignments
Fingers
M9lOO

DKC8-AA
J4 Pin No.

Signal Name

STROBE L

Comments

450 ns control pulse drives 10 unit loads.*

Not used
Not used
DATA IN 0 L

Most significant bit.

DATA IN 1 L

Input data low is true.**

DATA IN 2 L
DATA IN 3 L
Not used
SET DATA READY L

Low when input data is valid.

DATA ACCEPTED OUT L

Low when input data is accepted. Drives
25 unit loads.*

Not used
DATAIN 4 L
DATA IN 5 L
DATA IN 6 L
DATAIN7 L

Input data, low i s true.**

DATA IN 8 L
DATA IN 9 L
DATA IN 10 L
DATA IN 11 L

Least significant bit.
- --

All unspecified pins are ground.
*Unit load = I .6 m A @> logic low and 0.04 mA @ a logic high.
**Presents 4 unit loads to the drive circuit.

Table 6-5
J5 Output Signal Pin Assignments
Fingers
M9100

DKC8-AA
J5 Pin No.

Signal Name
-

Comments

-- - -

Not used
Not used
Not used

DATA OUT 0 L

Most significant bit.

DATA OUT 1 L
DATA OUT 2 L

Output data, low is true.**

DATA OUT 3 L
Not used

DATA AVAI LABLE L

Low when outpu,t data is valid.

DATA ACCEPTED IN L

Low when output data is accepted. Presents
4 unit loads to the driver circuit*

Not used

DATA OUT 4 L
DATA OUT 5 L
DATA OUT 6 L
DATA OUT 7 L

Output data, low when true.**

DATA OUT 8 L
DATA OUT 9 L
DATA OUT 10 L
DATA OUT 11 L

Least significant bit.

Pins A, B, C, E, H, K, M, P, S, U, W, Y , AA, CC,EE, HH, KK, MM, PP, and SS are grounded.
*1 unit load.
**Each output can drive 25 unit loads.

B BUF MD11 H

DBST (6570)
DESK (6571 )

MDIOL (DMI )

B BUF MD10 H

DBRD (6572)
DBCF (6573)

E25

B BUF MD9 H

DBTD (6574 )
74LS74 4 0OPERATION
DBSE (6575)
DECODER 5
DBCE (6576)

B BUF MD8 H

DBSS (6577)
80-

B BUF MD7 H

El7

J
B BUF MD6 H

MD5L (BLt )
41

M D 4 L (BM1)

MD3L (API 1

I / O PAUSE L
(CDI)

B BUF MD3 H

B BUF 1/0 PAUSE H

Figure 6-1 9

Parallel I/O Device Select and Operation Decoder

6.1 1.2 Interrupt and Skip Logic
The interrupt and skip logic is used to interrupt the program when a data transfer is required. To allow an interrupt
to occur, INT ENA must be set by the 6575 instruction. The one output of INT ENA allows INT RQST L to be asserted when DATA READY or B DATA IN sets. SKIP L is asserted if the 6571 instruction is decoded and B DATA
IN is set, or if the 6 5 7 0 instruction is decoded and DATA READY is set. (See the transmit and receive operations in
paragraph 6.1 1.3 for operation of these flags.)
6.1 1.3 Receive and Transmit Operations
The receive and transmit operations are described separately in the following paragraphs.
6.1 1.3.1

Transmit Operation - To transmit a 12-bit data word perform the following:

Load the output buffer by use of IOT 6 5 7 4 (Figure 6-20). Data will be transferred from the data lines on
the bus into the buffer at TP3 time.

At the trailing edge of TP3, DATA AVAILABLE becomes true (low) on the output cable (Figure 6-20).
There is a switch on the M 8 3 1 6 that will cause DATA AVAILABLE to be negated (go high) on the leading edge of the next TS1 pulse, if this is desired. This yields a pulse of about 4 5 0 ns in duration on the
DATA AVAILABLE signal line. The trailing edge of the pulse, on DATA AVAILABLE, could be used to
strobe the output data of the M 8 3 1 6 into the user's register. If TS1 is not used to negate DATA AVAILABLE, IOT 6 5 7 0 (DBST) should be used to negate DATA AVAILABLE.

The receiving device should then ground DATA ACCEPTED IN to signal the CPU that the transmitted
data has been received.
Assuming interrupt enable is true, the DATA ACCEPTED flip-flop will assert INT RQST L on the bus. (Figure 6-20).
The CPU then executes IOT 6 5 7 0 t o test the DATA ACCEPTED flip-flop and t o clear both DATA AVAILABLE and DATA ACCEPTED flip-flops. A t TP3 of IOT 6570, DATA AVAILABLE will go high on the output cable. This signals the end of the transmit sequence.
Receive Operation - The receive sequence is as follows:

The external device places data in some type of latching register then grounds the SET DATA READY
line on the input cable which raises the DATA READY flag. (Figure 6-20).
Assuming INTERRUPT ENABLE is true, INT RQST L will be asserted on the bus.
The CPU then executes the 6 5 7 1 IOT to test the DATA READY flip-flop; then IOT 6 5 7 2 should be issued to read the input data into ACO-11. (Figure 6-23).
The CPU should then execute IOT 6 5 7 3 t o clear DATA READY. This also sends a pulse out on the
DATA ACCEPTED out line on the input cable. This signal should be used by the external device to negate the SET DATA READY signal.
6.11.4 Strobe
IOT 6577 (Figure 6-21) creates a pulse on the STROBE line that goes from the high to low state at TP3 of IOT
6 5 7 7 and returns t o the high state at the next TS1. This pulse may be used t o start an event external to the CPU or
it may signal the end of an event.

STROBE L
(J4-D)

I N I T I A L I ZE H
(CR1)

Figure 6-21

BBUF INIT L

Parallel 1/0 Strobe Logic

6.11.5 Parallel I/O Output Register
The Parallel I/O output register (Figure 6-22) is loaded from the AC by a 6 5 7 4 instruction and is loaded into the
Transmit Buffer at TP3 time.

D A T A 6 L ( B U 1)

DATA OUT 6 L(J5-JJ)

B BUF DATA6 H

+ 5V
DATA OUT 7 L ( J 5 - L L )

+ 5V

1
1
1

DATA9 L ( DSl)

B BUF DATA9 H

DATA OUT 8 L (J5-NN)

!+
DATA O U T 9 L (J5-RR)

+5V
DATA10 L ( D u l l

DATA O U T 1 0 L ( J 5 - T T )

B B U F DATA10 H

+5 V
DATA11 L ( D V l )
B B U F DATA11 H

IOT

1 DECODER 1

D A T A OUT 11 L (J5-VV)

6574

Figure 6 - 2 2

Parallel I/O Output Register

6.1 1.6 Parallel 1/0 Input Buffer and Data Gates
The information received from the device (Figure 6 - 2 3 ) is transferred t o the AC via the Data Bus by the 6 5 7 2 instruction. CO L and C1 L (Figure 6 - 2 0 ) are asserted (low) t o allow data t o be transferred from the Data Bus t o the
AC.

DATA I N 0 L ( J 4 - L )
DATA0 L (AR1)

+ 5V
DATA

I N 1 L (J4- N )
DATA0 L (AS11

+ 5V

DATA

I N 3 L (J4-T )
DATA3 L (AV1)

DATA I N 5 L ( J 4 - F F )
DATA5 L ( B S D

+ 5V
DATA I N 6 L ( J 4 - J J )

$
T

DATA I N 8 L ( J 4 - N N )

+5 V
DATA I N 9 L ( J 4 - R R )

+5V
DATA I N 10 L ( J 4 - T T )
t5V
DATA I N 11 L ( J 4 - V V )

Figure 6-23 Parallel I/O Input Buffer
and Data Gates

SECTION 2
KM8-A EXTENDED OPTION MODULE ( M 8 3 1 7 )

6.12 KM8-A EXTENDED OPTION BOARD (M8317)
The KM8-A extended option module (M8317) (Figure 6-24) is a hex size module which comprises four PDP-8/A options:
1.

Memory Extension

Power Fail and Auto Restart

Timeshare Control

128-Location Bootstrap Loader

AUTO RESTART ENABLE ,

AUTO
RESTART

AC LOW

CONTROL

Â¥

MDBB- MDI 1

I
A U T O RESTART SELECT

T I M E SHARE

(INSTRUCTIONS)
USER MODE

sw
BOOTSTRAP ENABLE

L-

0--6

BOOTSTRAP
CONTROL
LOGIC AND
ROMS (128
LOCATIONS)

- BOOTSTRAP
SELECT

CONTROL SIGNALS

Figure 6-24

KM8-A Block Diagram

6.12.1 Memory Extension
The Memory Extension portion of the KM8-A extends the addressing capability of the PDP-8/A from 4096 words to
32.768 words.
6.1 2.2 Timeshare Option
The Timeshare portion of the KM8-A enables the PDP-8/A to operate in either the normal manner (Executive
Mode) or User Mode. User Mode enables the computer to function in a timesharing environment, in which a user
program is prevented from disturbing or interfering with another user program.
6.12.3 Power Fail/Auto Restart
The Power FaiVAuto Restart portion of the KM8-A interrupts the program when the power supply detects that the ac line
voltage has fallen below a certain level ( 9 5 V k 3% for 1 17 Vac operation). The power supply generates a signal AC LOW
which causes the Power FaiVAuto Restart to interrupt the program as the AC is going away. The power supply negates
the AC LOW signal when the AC line voltage rises above 105 V Â 3%.
6.12.4 Bootstrap Loader
The Bootstrap Loader portion of the KM8-A provides the logic to deposit into read/write memory one of several
programs contained on two ROMS. These programs provide the necessary instructions to load programs from paper
tape, disk, magnetic tape, etc, and to start the program at a specified location. Users may also purchase blank ROM
chips and write their own programs in them.
6.13 MEMORY EXTENSION AND TIMESHARE DESCRIPTION
Memory Extension hardware is required when more than 4K of memory is to be addressed. Except for data break
devices, the Memory Extension logic on the M 8 3 1 7 module is the only way to apply memory field addresses to the
three Omnibus Extended Memory Address lines (EMAO-EMA2). Memory is divided into eight 4K fields - field O(4K)
to field 7(32K). Each 4K of memory receives and decodes the EMAO-EMA2 signals. This provides an addressing capability up to 32,768 memory locations. On systems with 4K or less of memory, EMAO-EMA2 are all high representing all zeros, and field 0 is the only field that can be addressed by the program. However data break devices supply
their awn field address bits and they can address fields 1 through 7 without installing the KM8-A option.
Timeshare hardware is required for all systems that use a timeshare system monitor. Timeshare may be enabled or
disabled by a switch on the M 8 3 1 7 module.

6.14 MEMORY EXTENSION BLOCK DIAGRAM DESCRIPTION
The functional units that make the memory extension and timeshare option are explained in the following paragraphs
(Figure 6-25). The flow diagram in the KM8-A print set in Appendix H should be referred to during this discussion.

6.14.1 Control Logic
The control logic for the memory extension and timeshare option consists of device selector logic, operation decoders, and the INT RQST and SKIP signal lines. IOT instructions for memory extension and timeshare must be executed by the program to start operation (Paragraph 6.1 5).
Data paths between the memory extension and time share option are via the DATA BUS. When the data field or instruction field are to be stored in memory, the data path is from the DATA BUS to the AC register. A DCA instruction is then used t o store information in memory. The data paths between the memory extensionhimeshare and the
processor are via the M D lines (instructions) and DATA BUS (IF, DF, and USER MODE bits). When the program executes the CDF and CIF instructions the data field (CDF) and instruction field (IF) are carried on the M D lines.

EMA DISABLE
T

IB,UBOUT

:MA2

INSTRUCTION
BUFFER
REGISTER

DATA6-DATA8

e INSTRUCTION

FIELD
REGISTER

ADDRESS
GATES

INPUT
MULTIPLEXER

DATA IN

INSTRUCTION
SAVE FIELD
REGISTER

DATA
FIELD
REGISTER

IN^

DF
DATA IN
â‚¬ DF ON (1) H

EMA DF

DATA9-DATA11
IF, DF OUT

ENA MUX OUT

EMA DISABLE

OPE RATION
DECODER

DF ON

-I

I F CLK

INSTRUCTIONS

I
!M~-MDII
MD3-MD5
/ O PAUSE L

DEVICE

AND
,SELECT
OPERATION
DECODER
ROM

CLR CLK
RIF

I
CONTROL

Ãˆ

DATA IN

I B IN

fr-

BUFFER
MULTIPLEXER

I F IN

10 IN

DF, 10, UB CLK

UB IN

Ãˆ

IB. UB OUT

Ãˆ

INHIBIT
FLIP FLOP

INT IN PROG L
MD0-MD3
MD9- MD11
USER MODE H

TRAP
DETECT

ERROR

USER
INTERRUPT
FLIP FLOP

I N T RQST L

Figure 6-25

USER
BUFFER
REGISTER

Ãˆ

DF IN

TIME SHARE
DISA

Ãˆ

ENABLE MUX O U T

IEFER

IF, DF OUT

-0AD ADD ENA L
(EY CONTROL L

Ãˆ

DF, IB, UB, CLK

INTERNAL I / O L

OUTPUT

MULTIPLEXER

'7'

DATA IN

ADDRESS
GATES

Memory Extension and Timeshare Block Diagram

6.14.2

Instruction Field Register (IF)
The IF is a three-bit register that is an extension of the PC. The contents of the IF determine the field from which all
instructions are taken and the field from which operands are taken in directly-addressed Memory Reference Instructions. Pressing the console LXA switch transfers Entry Register bits 6 through 8 into the IF register. During a J M P
or J M S instruction, the IF is set by a transfer of information from the Instruction Buffer register. If the instruction is
a JMP, the IF i s updated at the conclusion of the instruction. If the instruction is a JMS, the IF is updated just before the execute portion of the instruction saving the return address in the new field. When a program interrupt occurs, the contents of the IF is automatically stored in bits 0 through 2 of the Save Field register for restoration to
the IF from the instruction buffer register at the conclusion of the program interrupt subroutine.

6.14.3 Data Field Register (DF)
This three-bit register determines the memory field from which operands are taken in indirectly-addressed Memory
Reference Instructions. Pressing the console LXA switch transfers the Entry register bits 9 through 11 into the DF
register. During a CDF instruction, the DF register is loaded from M D 6 - M D 8 to establish a new data field. When a
program interrupt occurs, the contents of the DF are automatically stored in bits 3 - 5 of the Save Field register. The
DF is set by a transfer of information from Save Field register bits 3 through 5 by the RMF instruction. This action is
required t o restore the Data Field at the conclusion of the program interrupt subroutine.
6.14.4

Instruction Buffer Register (I B)
The IB is a three-bit input buffer for the Instruction Field register. All field number transfers into the Instruction Field
register, except transfers from the operator's console switches, are made through the Instruction Buffer. The IB is set
by pressing the console LXA switch in the same manner as the Instruction Field register. A CIF microinstruction
loads the IB with the programmed field. A n RMF microinstruction transfers Save Field register bits 0 through 2 into
the IB t o restore the instruction field that existed before a program interrupt.

6.14.5 Save Field Register (SF)
When a program interrupt occurs, this seven-bit register is loaded from the USER FIELD flip-flop, and the IF and DF
registers. The SF register is loaded during the cycle in which the program count is stored at address 0000 of the
J M S instruction forced by a program interrupt request, then the Instruction Field, Instruction Buffer, and Data Field
registers are cleared. A n RMF instruction can be given immediately before exit from the program interrupt subroutine
t o restore the Instruction Field and Data Field by transferring the SF into the IB and the DF registers. (Also, see GTF
and RTF instructions.)
6.1 5

TIMESHARE CONTROL BLOCK D I A G R A M DESCRIPTION
The timeshare portion of the KM8-A module (Figure 6-25) operates in t w o modes defined by the USER Flag (UF)
flip-flop in the User Buffer. When the UF flip-flop is in the logic 1 state, operation is in the User Mode and user program is running. When the UF flip-flop is in the logic 0 state, operation is in the Executive Mode and the timesharing system's monitor is in control of the central processor. Four instructions (CINT, SINT, CUF, and SUF) are
used by the timesharing system's monitor in the executive mode and are never used by a user program. If a user program attempted t o use one of these instructions, execution of the instruction would be blocked (see next paragraph).
The timeshare option adds the necessary hardware t o the PDP-8/A to implement these instructions.
In Executive Mode, the computer operates normally. When the computer is operated in User Mode, operation is normal except for IOT, HLT, LAS, and OSR instructions. When one of these instructions is encountered, the trap detect
logic inhibits the normal instruction sequence (other than rewriting the instruction in memory), and generates an interrupt at the end of the current memory cycle. Any interrupt returns timeshare control to Executive Mode. The timesharing system's monitor program then analyzes the source of interrupt and takes appropriate action.
The timeshare option requires at least 8 K of memory. A switch on the KM8-A module is used to enable the timeshare
function.

6.16

M E M O R Y EXTENSION A N D TIMESHARE P R O G R A M M I N G

6.16.1 Memory Extension Programming
Instructions associated with the extended memory portion of the KM8-A option are as follows:
Mnemonic

Octal Code

Function

GTF

6004

Loads the contents of the SF register into AC5-11. Other AC bits are loaded
with information from the CPU, i.e., link, interrupt bus, interrupt on.

RTF

6005

Loads the USER BUFFER flip-flop, the Instruction Buffer register, and the
Data Field register with the contents of AC bits 5, 6-8, and inhibits processor
interrupts until the next JMP or JMS instruction. At the conclusion of the
JMP or JMS instruction, the contents of the USER BUFFER flip-flop and the
Instruction Buffer register are transferred into the USER FIELD flip-flop and
the Instruction Field register, respectively. ACO i s loaded into the Link.
The INTERRUPT ON flip-flop in the CPU is unconditionally set by this
instruction.
AC5 0
AC6-AC8
AC9-AC11

CDF

Clears User Flag
Instruction Field (0-7)
Data Field (0-7)

Loads the Data Field register with the program-selected field number N
(N = 0 to 7). All subsequent memory requests for indirect operands are automatically switched to that Data Field.
Loads the Instruction Buffer register with the program-selected field number
N (N = 0 to 7) and inhibits processor interrupts until the next JMP or JMS instruction. A t the conclusion of a JMP instruction or a t the beginning of the
execute portion of a JMS instruction, the contents of the Instruction Buffer
register i s transferred into the Instruction Field register.

CDF
CI F

Performs the combination of CDF and CIF operations.

RDF

ORs the contents of the Data Field register into bits 6-8 of the AC. All other
bits of the AC are unaffected.
ORs the contents of the Instruction Field register into bits 6-8 of the AC. All
other bits of the AC are unaffected.

RIB

Inclusively ORs the contents of the Save Field register (which is loaded from
the Instruction and Data Field during a program interrupt) into bits 6-8 and
9-1 1 of the AC, respectively. Thus, AC 6-1 1 contains the Instruction and
Data Fields that were in use before the last program interrupt. AC 5 is loaded
by the timeshare bit of the Save Field register. All other bits of the AC are
unaffected.

RMF

Restores the contents of the Save Field register (which is loaded from the
Instruction and Data Field during a program interrupt) into the Instruction
Buffer, the Data Field register, and the User Buffer (if timeshare option is
enabled). This command i s used upon exit from the program interrupt subroutine.

Instructions and data are accessed from the currently assigned instruction and data fields, which may be in the same
or different memory fields. When indirect memory references are executed, the operand address refers first to the instruction field to obtain an effective address, which, in turn, refers to a location in the currently assigned data field.
All instructions and operands are obtained from the field designated by the contents of the Instruction Field register,
except indirectly-addressed operands, which are specified by the contents of the Data Field register. In other words,
the DF is effective only in the EXECUTE cycle that directly follows the Defer cycle of a memory reference instruction
as follows:

Indirect
(Bit 3)

Page Bit
(Bit 4)

Field
In I F

Field
In D F

Effective Address
The operand is i n page 0 of field m at the address
specified by bits 5 through 11.
The operand is in the current page of field m at the
page address specified by bits 5 through 11 of the instruction.
The absolute address of the operand i n field n is taken
from the contents of field m. Page 0 at the page address specified by bits 5 through 11 of the instruction.
The absolute address of the operand in field n is taken
from the contents o f field m current page, at the page
address specified by bits 5 through 11 of the instruction.

Each field of extended memory contains eight auto-index registers in addresses 10(8) through 17(8). For example,
assume that a program in field 2 is running (IF = 2) and using operands in field 1 (DF = 1) when the instruction
and the contents of location 1 0 in field 2 are read, inTAD I 1 0 is fetched. The Defer cycle is entered (bit 3 = I),
cremented, and rewritten. If address 1 0 in field 2 originally contained 4321, it now contains 4322. In the execute
cycle, the operand is fetched from location 4322 of field 1. Program control is transferred between memory fields by
the CIF instruction. The instruction does not change the instruction field directly, because this would make it impossible to execute the next sequential instruction; instead, it loads the new instruction field in the I 0 for automatic
transfer into the IF when either a JMP or JMS instruction is executed. The DF is unaffected by the JMP and JMS
instructions.
The 12-bit program counter is set in the normal manner and, because the IF is an extension on the most significant
end of the PC, the program sequence resumes in the new memory field following a JMP or JMS. Interrupts are inhibited after the CIF instruction until a JMP or JMS is executed.

NOTE
The IF is not incremented if the PC goes from 7777 to
0000. This feature protects the user from accidently entering a nonexistent field.

To call a subroutine that is out of the current field, the data field register is set to indicate the field of the calling
JMS, which establishes the location of the operands as well as the identity of the return field. The instruction field is
set to the field of the starting address of the subroutine.

When a program interrupt occurs, the current instruction and data field numbers are automatically stored in the 7-bit
Save Field register; then the IF, 10, and DF, are cleared. The PC content is stored in location 0000 of field 0 and
program control advances to location 0001 of field 0. At the end of the program interrupt subroutine, the RMF instruction restores the IF, IB, and DF from the contents of the SF. Alternatively, the GTF and RTF instructions may be
used to handle the save field and link information.
6.1 6.2 Timeshare Programming
The instructions associated with the time share option are as follows:
Mnemonic

Octal Code

CINT

6204

Clears the USER INTERRUPT flip-flop.

SI NT

6254

When the USER INTERRUPT flip-flop is set the next sequential instruction
is skipped.

CUF

6264

Clears the USER BUFFER flip-flop.

SUF

6274

Function

Sets USER BUFFER flip-flop and inhibits processor interrupts until the next

JMP or JMS instruction. A t the conclusion of either of these instructions, the
content of the USER BUFFER flip-flop is transferred into the USER FLAG
flip-flop.
NOTE
If the machine is stopped while i n User mode, the user
flag (UF) may only be cleared by negating POWER
0 K.

6.17 MEMORY EXTENSION A N D TIMESHARE DETAILED LOGIC DESCRIPTION
The memory extension and timeshare block diagram in Figure 6-25 should be used to understand the interaction and
signal flow between functional groups of logic. The logic can be considered to be divided into four groups: the control
(located on the bottom left portion of the block diagram), the Instruction Field register (IF), the Data Field register (DF),
and the Timeshare control logic. The only interface is the Omnibus. All signals entering and leaving the system, therefore,
are directed to the Omnibus. Data is transferred between the processor and the KM8-A option via the Data Bus and
between memory and the KM8-A via the MD lines. Data is transferred via the Data Bus to the console indicators during
TS1 to tell the operator which instruction fields and data fields are being addressed by the program. When the data field
and/or instruction field are to be stored in memory, the data path is from the Data Bus to the AC register. A DCA
instruction is then used to store the information in memory.
6.17.1 Memory ExtensiodTimeshare Device Select
The device select logic for the memory extension and timeshare option is shown in Figure 6-26. ROM No. 1 (E27) is the
device select decoder for the memory extension and timeshare options. The address bits MD3-MD5 and MD9-MD11 are
enabled by 1/0 PAUSE L to select one of the ROlM memory locations. INTERNAL 1/0 L is asserted anytime a 62XX
instruction is decoded to direct the Positive I/O to ignore this IOT instruction (see E27 Truth Table in Figure 6-26).ROM
No. 1 also decodes the CIF (62N1) and CDF (62N2) instructions to generate the necessary control signals for the
execution of these instructions. The 6 2 x 4 output enables the operation decoder discussed in the next paragraph. The
ROM pattern generated by this ROM is listed in the printset in Appendix H.

MD5 L (EL11

E27
ROM # 1

SIGNAL

OCTAL CODE
62N 1
62N2
62N3

CDF
CIF
CDF,CIF

62x4

62N1 + 62N2 +
62N3 + 62x4

INTERNAL I10 L

10
11 AND 10
9
12

CDF ( 6 2 N l )

1/0 PAUSE L (CD1)

E27 TRUTH TABLE
PIN
NUMBER
11

ASSERTED
LEVEL
LOW
LOW
LOW
LOW
LOW
08-1356

Figure 6 - 2 6

Memory Extension and Timeshare Device Select Logic

6.17.2 Memory Extension and Timeshare Operation Decoder
The operation decoders are shown in Figure 6-27. There are t w o operations decoder: one for the 6 2 x 4 instructions
and one for the 600X instructions.
E39, the operation decoder for the 6 2 x 4 instructions, is enabled by 6 2 x 4 for the device select logic. The operation
decoder is a BCD t o decimal decoder which decodes M D 6 - M D 8 to generate the necessary control signals for the execution of these instructions. As an example, if the SUF (6274) instruction is executed by the program and MD6,
MD7, and M D 8 are all ones, pin 9 is asserted low to allow the execution of the SUF instruction. All other pins
would be high.
C1 L is asserted by the RIB, RIP, and RDF instructions to allow data transfers from the Data Bus t o the AC register.
M D 3 - M D 8 are enabled by I/O PAUSE at E37 to enable the decoding of MD9-MD1 1 when an 600X instruction is
executed by the program. The output of E37 enables E33 and EGO to decode MD9-MD1 1 and generate signals RTF
and GTF.

SUF ( 6 2 7 4 )
BBUF M D 6 H

B BUF M D 7 H

E39
OPERATION

DO DECODER

MD8 ti
~

CUF ( 6 2 6 4 )

7442
0 3

f
f20

RIB (6234)

RIF ( 6 2 2 4 )

RDF(6214)

'
KMTS 1 RDF L

k CINT ( 6 2 0 4 )

B BUF MD9 H

B BUF M D 5 H

B BUF M D 8 H

BBUF MD10HB BUF MD 11 H

Figure 6-27

Memory Extension/Time Share Operation Decoder

GTF ( 6 0 0 4 )

6.1 7.3 Input Multiplexer
The Input Multiplexer shown in Figure 6 - 2 8 receives data from the Memory Data lines (MD6-MD8) and the Data
Bus (DATA5-DATA1 1) and supplies an input t o the UB, IF, and DF registers as follows:
DATA5 to UB register
DATA6-DATA8 to IF register
RTF Instruction
DATA9-DATA11 t o DF register
M D 6 - M D 8 to IF register
CIF (62N1) Instruction
M D 6 - M D 8 to DF register
CDF (62N2) Instruction
M D 6 - M D 8 to IF and DF registers
CDF,CIF (62N3) Instruction
DATA6-DATA1 1 t o IF and DF register
when the LXA switch o n the Programmer's Console
is pressed. This asserts LOAD ADD EN L and
KEY CONTROL L which enables E53.
The Multiplexers are 74S257 ICs with Tristate outputs which select one of the inputs (DATA5-DATA1 1 or MD6-MD8)
as output to UB, IF, and DF registers. A low on the select input selects DATA5-DATA1 1 and a high selects MD6-MD8.
ENA OUT must be low t o enable either output t o be used.

6.1 7.4 Instruction Field Register and Controls
The control logic associated with the IF register (Figure 6-29) controls data flow and provides the necessary gating
and control signals t o enable gating, clocking, loading, etc., of the IF, IB, UB, and IF Save Field registers. This logic
loads either M D 6 - M D 8 or DATA5-DATA8 (depending on the instruction) into the IB and UB registers for transfer to
the IF register. If the RTF instruction is executed, the IB and UB registers are loaded from the Data Bus and inter-upts are inhibited until the J M P or J M S instruction is executed. A t the conclusion of the J M P or J M S instruction,
the content of the IB and UB register is transferred t o the IF register. If the CIF or CDF instructions are used M D 6 M D 8 are loaded into the IB register and transferred t o the IF register at the conclusion of a JMP instruction or at
the beginning of the execute cycle of a J M S instruction.
The IF in the Entry register on the Programmer's Console is transferred t o the IB register via the Data Bus when
LXA is pressed. This operation is enabled in the IF register control logic by LOAD ADD EN L and KEY CONTROL L
which enables NAND gate E53. This operation loads the IB register, enables the IF Multiplexer, and loads the IF register. PULSE LA L clocks the data into the register.
The content of the IF register is transferred to the Save IF register at TP4 if BBUF INT IN PROG H is asserted high. This
occurs anytime an interrupt occurs. Note that the CLR input of the IF register is clocked at the same time to clear the IF
register. I t is also cleared during power up when BBUF POWER OK H goes high.
To transfer the content of the Save IF register back t o the IF register, the program must execute the RMF instruction
at the conclusion of the interrupt service routine.
The RMF instruction enables the output of the Save IF register t o the IB and UB register and it is clocked into the
IB and UB register by BBUF TP3 H. The transfer from the IB and UB to the IF is made at the end of a J M P instruction or at the beginning of the execute cycle of a J M S instruction.

OUTPUT T o
DATA FIELD REG

75; : :7

B B U F DATA10 H

1 1

~31-

-B 3
B BUF DATA 11 H

BBUF MD6 H

A3
ENA
OUT

SELECT

B BUF DATA 6 H

BBUF MD7 H

B B U F MD8 H

B BUF DATA8 H

F 3 --

OUTPUT TO:
INSTRUCTION BUFFER
REGISTER
USER
BUFFER REGISTER

&
B BUF DATA 5 H

F1-'

E57
74S257

BBUF DATA 7 H

B3
A3
ENA
OUT

SELECT

GTF

Figure 6-28

Input Multiplexer

The content of the IF register may be read into the AC for storage in memory by the RTF or RIF instruction. These
instructions enable the IF multiplexer and the content of the IF register is applied to the output multiplexer (Paragraph 6.1 7.6) for transfer t o the AC via the Data Bus.
The output of the IF register is enabled t o the EMA lines (Figure 6-30) when DF ON and EMA DISABLE are both
cleared. DF ON is set only in the Execute cycle that directly follows the Defer cycle of a memory reference instruction. EMA DISABLE is set only during a break cycle by CPMA DISA L and cleared by TP4 at the end of the break
cycle. The break device supplies its o w n extended memory address during break cycles.
USER MODE H is asserted (low) when the User Flag in the IF register is set t o a one. The user flag is set only
when the computer operates as a timesharing system (see Paragraph 6.1 6.7).

KMTS1 I B IN L

DATA ENA

KMTS1 IB, UB OUT L

40
E2*
40
INSTRUCTION
BUFFER 30
REGISTER
74173* 2Q

'Â¥TF

1l :

--Â¥

1 MULTIPLEXER 1

0 UT
COUNT
CLK

CLR

KMTS1 DF. I B . UB CLK H

<MTS!
JSER MODE H
I

FROM
SHEET 1

DATA ENA

(DM21

30
REGISTER
20 (74173)* 20

MULTIPLEXER
AND I F REGISTER

OUT
COUNT
CLK

TO OUTPUT
MULTIPLEXER AND
I F REGISTER

CLR

CDF
CIF

* TRISTATE OUTPUT
KMTS1 ENA MUX OUT L

1
Figure 6-29 I F Register and Control Logic (Sheet 2 of 2)

The IB, IF, and IF Save Field registers are 7 4 1 7 3 ICs. Data is enabled into these registers by the t w o DATA ENA
inputs and a low to high transition on the CLK input. Data is enabled out of these registers by t w o low inputs t o
DATA CONT. The registers are cleared by applying a high signal t o the CLR input.
6.17.5 Data Field Register and Controls
The Data Field (DP) register (Figure 6-31) receives data from 3 sources:
1.

The M D lines when the CDF or CDF, CIF instructions are executed,

The Data Bus when the RTF instruction is performed or LXA on the Programmer's Console is pressed,

The DF Save register when the IF and DF are restored at the end of a routine t o service an interrupt.
The content of the DF register is transferred to the DF Save register when an interrupt occurs.

When the RTF instruction is executed by the program, the DF register is loaded from the AC via the DATA BUS and
the Input Multiplexer (Figure 6-28) and clocked into the DF register by BBUF TP3 H. When the CDF, CDF, or CIF
instructions are used t o load the DF register, it is loaded from M D 6 - M D 8 via the input multiplexer. Data is enabled
into the register by the CDF instruction and clocked into the register by BBUF TP3 H.
When LXA on the Programmer's Console is pressed, LA ENABLE L and KEY CONTROL L (E53) enables the Entry
register data from the Data Bus via the input multiplexer t o load the DF register. The input is clocked in by PULSE
LA H.
The content of the DF register is transferred t o the DF Save register anytime an interrupt request is made by a system device. When an interrupt request is made, BBUF INT IN PROG H is asserted (high), which clocks the content
of the DF field register into the DF Save register. The DATA EN inputs are grounded o n the DF Save register so it
needs only a clock pulse t o load the register.
The content of DF Save register is transferred back to the DF register by the RMF instruction which is executed at
the end of an interrupt service routine.
The content of the DF register is enabled out to the EMA lines by KMTS1 DF ON(1) H during Execute cycles that
directly follow a Defer cycle of a memory reference instruction (Figure 6-30). The other enabling signal KMTS1 EMA
DIS(0) H, is always high except during data break cycles when the EMA DIS flip-flop (Figure 6-30) is set by CPMA
DISABLE L.
6.17.6 Output Multiplexer
The Output Multiplexer (Figure 6-32) consists of t w o 8 2 3 4 ICs which enable the output of the UB, IF, and DF registers t o the Data Bus when instructions are executed t o transfer their content t o the AC. IND1 L and IND2 L enable
the content of the IF, DF, and UB registers to be applied t o the Data Bus during TS1 to display the IF, DF, and UB
in the Status register (Figure 1-5).

6.1 7.7 Timeshare User Buffer Register and Control Logic
The User Buffer register is used only when the timesharing portion of the KM8-A is implemented (Figure 6-33). Timeshare is enabled by turning S2-1 on the KM8-A module off.
The User flag is set if DATA5 is a one or cleared if DATA5 is a zero when the RTF instruction is executed.
When the SUF instruction is executed, the User flag is set by M D 8 as a one and it is cleared when the CUF instruction is executed by M D 8 as a zero.
The state of the User flag is transferred t o the IF registers at the same time and in the same way as the content of
the IB register is transferred t o the IF register (Paragraph 6.1 7.4).

DATA ENA

^>>

FROM INPUT MULTIPLEXER
AND DF REGISTER

E4 8
30
7 4 1 7 3 30
DATA
20
FIELD
20 ,
REGISTER

OUT
COUNT
CLK

CLR

BBUF TP3 H
KMTS1 DF.
1B. UB CLK H

7404
CIF

DATA ENA
4Q
30

40
E51
7 4 1 7 3 30
DATA

3
-

TO OUTPUT
MULTIPLEXER
AND DF REGISTER

COUNT
OUT

LA ENABLE

CLK

CLR

TP4 H (C J 2 )

* TRISTATE OUTPUT

- tzz

BBUF TS1 H

- l74sof

RUN H
BBUF POWER OK H

Figure 6-31

Data Field Register and Control Logic

- BO
A0
INPUT FROM
I F REGISTER

DATA 9 L (DS1)

fO O Ã ‘ DATA 6L(BUl)
DATA7 L ( B V l )

DATA 10 L(DU1)

DATA 8 L (DR I)

DATA 1 1 L ( DV1)
INPUT FROM
DATA FIELD
REG i S T E R
UB REGISTER

DATA 5 L ( B S D

KMTS RDF L

RIB
KMTSI R I F L

Figure 6-32

Output Multiplexer

- K M T S 2 TIME SHARE DISA L

BBUFTSlH

r - - - -1
1
INPUT
1

B BUF MD8 H

1 +5V

13'g~

TIMESHARE

L----J

+3VB

STB1
Dl

STb0
TO OUTPUT MULTIPLEXER
I F REGISTER AND I F
SAVE FIELD REGISTER

C1
f1

DATA5H

IMULTIPLEXER I

DISABLE

7415 3
-DO MULTIPLEXER
KMTS2 + 1

CO
BO

INT INH H

-A 0

vdz7'

BUFFER
2Q REGISTER 2Q

rUT
COUNT

LA ENABLE L (BM2)
KEY CONTROL L
(DV2

RMF
RT F

IRO L (DD2)

CUF
SUF

1
K MTS1
OUT L

FETCH L ( D J 2 )
740 4

DEFER L ( D K 2 )

PULSE LA H (DR 2 )

1
I

B B U F TP3 H
7404

KMTS1 DF, I B , UB. CLK H

MA. MS LOAD

+ 3VB
B BUF TS1 H
RUN H
BBUF POWER OK H

* TRISTATE OUTPUT

Figure 6-33

Time Share User Buffer Register
and Control

B BUF TP2 H

- --USER

INTERRUPT~
FLIP FLOP

B BUF MDO H
B BUF MD1 H

I N T ROST L (CPlÃ

CI NT
BBUF MD9 H

I
L ----J

B BUF MDlO H
B BUF MD2 H

I :&-

B BUFINIT L-

B BUF MD11 H

FETCH L ( D J 2 )

KMTS 2 USER MODE H

KMTS2 TIME SHARE DISA L
SI NT

0
Figure 6-34

Trap Detect Logic

'-m
I

SKIP L ( C S 1 )

6.17.8 Trap Detect Logic
The purpose of the trap detect logic in Figure 6-34 is t o generate an INT RQST if an IOT, HLT, LAS, or OSR instruction is executed by a user program while the computer is in the User Mode. NAND gate E l 1 is enabled by KMTS2
USER MODE H when 82-1 on is set to off. TP2 H is used to enable the input to INTERRUPT flip-flop so that an
INT RQST will not be made until the completion of the current memory cycle. Any interrupt returns the computer to
Executive Mode and the timesharing system monitor must determine what to do about the interrupt.
The SINT instruction asserts SKIP L if the USER INTERRUPT flip-flop is set. This instruction is used for flag checking routines.
The CINT instruction clears the USER INTERRUPT flip-flop.

6.17.9 Interrupt Inhibit Logic
The Interrupt Inhibit flip-flop in Figure 6-35 is set by KMTS2-l-1 INT INH H, which is asserted (high) if a CIF, CUF,
SUF, RMF, or RTF instruction is executed by the program and S2-1 is off (see Figure 6-33). S2-1 is set to off to
enable the Timeshare Mode. When the INTERRUPT INHIBIT flip-flop sets, INT IN PROG L is asserted (low) and the
interrupt system is turned off. Interrupt Inhibit is cleared when a JMP or JMS instruction is executed at the end of
an interrupt service routine. Also at this time the IF and DF registers are restored from the Save Field registers or
loaded with a new field.

6.18 POWER FAIWAUTO RESTART A N D BOOTSTRAP LOADER
The Power Fail/Auto Restart and Bootstrap options are discussed in the following paragraphs.

6.18.1 Power Fail/Auto Restart Block Diagram Description
The power supply monitors the ac line voltage and detects when the ac line voltage has fallen below a certain level,
(95 V &3% for 117 Vac operation), and generates a logic signal AC LOW. This signal causes logic in the Power
Fail/Auto Restart portion of the KM8-A extended option board to interrupt the program, which takes the necessary
action as the ac power is going away (Figure 6-35). In MOS memory systems, the automatic switch-over to a battery supply that allows the system to continue operation for an additional 4 5 seconds minimum, will occur. If power
is restored during this time, the system will automatically switch back to the regular power supply. In core memory
systems, the program should store all active registers (AC, MQ, etc.) and stop the system when a low ac voltage is
detected. The computer will restart and the program can restore the active registers when ac power goes above 105
Vac (1 17 Vac operation.)

Features
Restart Address:

One of four restart addresses may be selected, one at a time (4200,
2000, 0200, or 0000).

Auto Restart:

If Auto Restart is enabled, the PDP-8/A starts automatically when power
is applied. This allows the user to apply power remotely and start the
system without going to the PDP-8/A. (Auto-Start on the CPU must be
disabled.)

6.1 8.2 Power Fail/Auto Restart Programming (Figure 6-36)
T h e I O T i n s t r u c t i o n s u s e d with t h e P o w e r F a i l / A u t o R e s t a r t option a r e a s f o l l o w s :
Mnemonic

Octal Code

Function

SPL

6102

Skip if t h e AC L O W f l a g is s e t or AC L O W s i g n a l i s low. A f t e r d e t e c t i n g a n
AC L O W condition, f l a g s h o u l d b e c l e a r e d by a CAL i n s t r u c t i o n . T h e n t e s t
u s i n g t h e S P L i n s t r u c t i o n until a c g o e s a b o v e 105 V. T h e n t e s t by a n S P L ins t r u c t i o n to s k i p on t h e l e v e l AC L O W b e i n g low. T h e INT R Q S T l i n e will not
b e a s s e r t e d a f t e r t h e f l a g h a s b e e n c l e a r e d by CAL.

CA L

6103

C l e a r t h e AC L O W i n t e r r u p t .

SBE

6101

S k i p if t h e B A T T E R Y E M P T Y f l a g i s set.

The device code for this option is fixed as 10.

TO OMNIBUS

1
1

SEMICONDUCTOR
POWER SUPPLY

BATTERY
EMPTY

1 1 1

INTERRUPT

LOGIC

SKIP L
INT
RQST L

OMNIBUS

DATA 0

rn L
AC POWER
MONITOR LOGIC

SUPPLY
POWER

DATA 3
,

/KX)WL

LOW
FLAG

I
I

SWITCHES

AND LOGIC

I
DATA 11

-17:
INITIALIZE

F i g u r e 6-36

I
HOLDING
REGISTER

OMNIBUS
SIGNALS

DATA 4

RESTART
SELECT

CONTROL

,CONTROL SIGNALS
TO

OMNIBUS

P o w e r F a i l a n d Auto R e s t a r t B l o c k
Diagram

6.18.3 Bootstrap Loader Block Diagram Description
The Bootstrap Loader (Figure 6-37) on the M 8 3 1 7 module provides the logic to deposit one of several programs
that is contained in t w o ROMs on the M8317 module into read/write memory. These programs provide the necessary instructions to load programs from paper tape, disk, magnetic tape, etc., and to start the program at the specified location.

DATA 0 L - DATA 11 L

11-

BOOTSTRAP
PROGRAM ADDRESS SELECT
SSELECT
WITCHES

~~~~~~~

DATA GATES

ROM A D D R E S S ,

ROMS

4
CLOCK

Figure 6-37

Bootstrap Loader Block Diagram

The Bootstrap Loader may be activated by pressing the BOOT switch on the Limited Function Panel or the optional
Programmer's Console or from the transition of AC LOW from low to high. The computer must be halted for AC
LOW to activate the bootstrap. Two switches on the M8317 module select the appropriate signal to activate the
bootstrap.
The bootstrap can be started when the computer is turned on. This feature is enabled by a switch on the M8317
and allows the computer t o be started remotely when the PDP-8/A is used as a peripheral.

6.19 BOOTSTRAP R O M ORGANIZATION A N D P R O G R A M M I N G
For those users who wish to write their own program into the bootstrap ROMs, the following procedures should be
used.

6.1 9.1 ROM Organization
The t w o ROMs are connected as follows: the address lines are connected in parallel, i.e., two corresponding address
lines of each ROM are connected together, and the outputs are arranged in serial fashion forming an 8-bit word, 4
outputs from each ROM. Because 12 bits are required for data/address information, two sequential addresses must
be accessed from the ROMs to form a 16-bit word. Where the first 8 bits are temporarily stored in a register, then
the next 8 bits are accessed from the ROMs. A t this point, the control then decides what to do with 12 of the 16
bits. There are four possible actions that can take place at this time:
1.
2.
3.
4.

Load Address
Load Extended Address
Deposit
Start

The remaining 4 bits of the 16 actually tell the control which of the four actions are to take place. The 16-bit word
should look like the word in Figure 6-38.

CONTROL
WORD
LOAD
ADD

DEP.

DATA

Ã£

ADD

MSB

ROM # 1
( E V E N ADD)

"
ROM # 2
( E V E N ADD)

8
A

1 0 L S B

ROM # 2
(ODD ADD)

ROM#l
(ODD ADD)

2ndWORD
FROM ROMS

1 ' WORD
FROM ROMs

Figure 6-38

16 Bit Word ROM Format

The use of ROMs that have 256 addressable locations allows up to 128 words of ROM storage. These 128 locations may be used for bootstrap and/or auto-restart programs. Any auto-restart or bootstrap program may be located
anywhere in the ROMs as long as the program starts in an even address in the ROM. If it is required that both
bootstrap and auto-restart programs be accessible at the same time, activated by different signals, then of course
the auto-restart program(s) must be located in addresses 0 through 15 in the ROMs. This is due to the addressing
limits of the auto-restart select switches.

6.1 9.2 Auto-Restart/Bootstrap Sequence
The following events should take place when an auto-restart is initiated:

1.
2.

Load a 12 bit address
Load the extended address and start.

The following events should take place when the bootstrap is initiated:
1.
2.
3.
4.

Load a 12 bit initial address.
Load the Extended Address.
Deposit 12-bit data words, repeating as required by length of program, to be deposited.
Load a 12-bit starting address and start.

The decision to perform a bootstrap or an auto-restart is directed by a set of switches on the module. The bootstrap
may be activated by the transition of the signal AC LOW from a logic low to a logical high or by a similar transition
of the SW line on the Omnibus.
Auto-restart is only activated by AC LOW.
6.1 9.3 ROM Programming Examples
An auto-restart example is shown in Figure 6-39.
1.
2.

Load address 0200
Load field 0, start

Starting at ROM address 004.

ROM NO. 1

ROM NO. 2

Load Address 0200
Load Ext. Add 0 and Start

NOTE: Logic one ( 1) = + 3V
Figure 6-39

6.19.4

Auto Restart Example

Bootstrap Example (Figure 6-40)
Load address 0023
Load field 7
Deposit 2000
Deposit 6745
Deposit 0023
Deposit 7650
Deposit 5024
Deposit 6733
Deposit 5031
Load address 0024 and start

Starting at ROM address 124.
6.1 9.5 Obtaining Blank ROMs
Unprogrammed ROMs should be purchased by the user from Digital Equipment Corporation. The part number for an
unprogrammed 256 X 4 ROM is 23-OOOA8.

ROM NO. 1

ROM NO. 2

Load Add 0023
Load E x t Add 7
Dep 2000
Dep 6745
Dep 0023
Dep 7650
Dep 5024
Dep 6733
Dep 5031
Load Add 24 & Start

Figure 6 - 4 0

Bootstrap Example

6.20 ROM PROGRAM LISTING
All M 8 3 1 7 modules are shipped with the programs in either Table 6 - 6 or Table 6-7 stored in ROM No. 1 and ROM No. 2.
The ROM patterns for these ROMs are listed in the KM8-A print set in Appendix H.

6.21

POWER FAIL/AUTO RESTART AND BOOTSTRAP OPERATION A N D TIMING

6.21.1 Power Fail Operation
The power fail portion of the M 8 3 1 7 module initiates a controlled shutdown sequence when a power failure occurs.
Circuits in the power supply monitor the ac voltage (Paragraph 7.2) and generate AC LOW L when the voltage falls below
a predetermined level. In the 8 A core memory systems, AC LOW L causes an INT RQST and the program must take the
necessary action to store all active registers while the dc supply is adequate t o maintain system operation. INT RQST is
also asserted in these machines by ac power going low even though they switch to battery power. I n the PDP-8/A
Semiconductor memory system, operation is switched t o battery power automatically when ac power fails. If ac power is
not restored a fully loaded system will continue to run for up to 4 5 seconds. If ac power is restored, system operation is
switched back t o the regular power supply when they are in regulation. If power is not restored after a period of
approximately 4 5 seconds, the BATTERY EMPTY signal is asserted and causes an INT RQST. A t this time the program
has 1 ms t o do whatever is necessary t o shut down the system before battery power is removed. When power is removed
completely, the content of the MS8-A RAM is lost and programs in this memory must be reloaded.

Table 6-6
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled 87A2 and 88A2)
ROM
ADDRESS

MEMORY
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

AUTO/RESTART
LOAD ADDRESS 0000
AUTO/RESTART
LOAD FIELD O/START
AUTO/RESTART
LOAD ADDRESS 0 2 0 0
AUTO-RESTART
LOAD FIELD O/START
AUTO-RESTART
LOAD ADDRESS 2 0 0 0
AUTO-RESTART
LOAD FIELD OISTART
AUTO-RESTART
LOAD ADDRESS 4 2 0 0
AUTO-RESTART
LOAD FIELD O/START
HIGH-LOW PAPERTAPE
LOAD ADDRESS 7 7 3 7
LOAD FIELD 0
DEPOSIT 6 0 1 4

DEPOSIT 3376
DEPOSIT 7 3 2 6
DEPOSIT 1 3 3 7
DEPOSIT 2 3 7 6
DEPOSIT 5 3 4 1
DEPOSIT 6 0 1 1
DEPOSIT 5 3 5 6
DEPOSIT 3 3 6 1
DEPOSIT 1 3 6 1
DEPOSIT 3 3 7 1
DEPOSIT 1 3 4 5
DEPOSIT 3 3 5 7

Table 6-6 (Cont)
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled 87A2 and 88A2)
-

ROM
ADDRESS

MEMORY
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

DEPOSIT 1 3 4 5
DEPOSIT 3 3 6 7
DEPOSIT 6 0 3 2
DEPOSIT 6 0 3 1
DEPOSIT 5 3 5 7
DEPOSIT 6 0 3 6
DEPOSIT 7 1 0 6
DEPOSIT 7 0 0 6
DEPOSIT 7 5 1 0
DEPOSIT 5 3 7 4
DEPOSIT 7 0 0 6
DEPOSIT 6 0 3 1
DEPOSIT 5 3 6 7
DEPOSIT 6 0 3 4
DEPOSIT 7 4 2 0
DEPOSIT 3 7 7 6
DEPOSIT 3 3 7 6
DEPOSIT 5 3 5 6
LOAD ADDRESS 7 7 3 7 1
START
RK8/E
LOAD ADDRESS 2 3
LOAD FIELD 0
DEPOSIT 2 2 0 0
DEPOSIT 6 7 4 5

Table 6-6 (Cont)
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled 87A2 and 88A2)
ROM
ADDRESS

MEMORY
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

DEPOSIT 0 0 2 3
DEPOSIT 7 6 4 0
DEPOSIT 5 0 2 4
DEPOSIT 6 7 4 3
DEPOSIT 5 0 3 1
LOAD ADDRESS 24/
START
TC08
LOAD ADDRESS 7 6 1 3
LOAD FLD 0
DEPOSIT 6 7 7 4
DEPOSIT 1 2 2 2
DEPOSIT 6 7 6 6
DEPOSIT 6 7 7 1
DEPOSIT 5 2 1 6
DEPOSIT 1 2 2 3
DEPOSIT 5 2 1 5
DEPOSIT 0 6 0 0
DEPOSIT 0 2 2 0
LOAD ADDRESS
7754
DEPOSIT 7 5 7 7
DEPOSIT 7 5 7 7
LOAD ADDRESS 7 6 1 3 /
START
RF08/DF32D
LOAD ADDRESS 7 7 5 0
LOAD FIELD 0

Table 6-6 (Cont)
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled 87A2 and 88A2)
ROM
ADDRESS

MEMORY
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

DEPOSIT 7 6 0 0
DEPOSIT 6 6 0 3
DEPOSIT 6 6 2 2
DEPOSIT 5 3 5 2
DEPOSIT 5 7 5 2
LOAD ADDRESS 7 7 5 0 /
START
TA8/E
LOAD ADDRESS 4 0 0 0
LOAD FIELD 0
DEPOSIT 1 2 3 7
DEPOSIT 1 2 0 6
DEPOSIT 6 7 0 4
DEPOSIT 6 7 0 6
DEPOSIT 6 7 0 3
DEPOSIT 5 2 0 4
DEPOSIT 7 2 6 4
DEPOSIT 6 7 0 2
DEPOSIT 7 6 1 0
DEPOSIT 3 2 1 1
DEPOSIT 3 6 3 6
DEPOSIT 1 2 0 5
DEPOSIT 6 7 0 4
DEPOSIT 6 7 0 6
DEPOSIT 6 7 0 1

Table 6-6 (Cont)
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled 87A2 and 88A2)
ROM
ADDRESS

MEMORY
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

DEPOSIT 5 2 1 6
DEPOSIT 7 0 0 2
DEPOSIT 7 4 3 0
DEPOSIT 1 6 3 6
DEPOSIT 7 0 2 2
DEPOSIT 3 6 3 6
DEPOSIT 7 4 2 0
DEPOSIT 2 2 3 6
DEPOSIT 2 2 3 5
DEPOSIT 5 2 1 5
DEPOSIT 7 3 4 6
DEPOSIT 7 0 0 2
DEPOSIT 3 2 3 5
DEPOSIT 5 2 0 1
DEPOSIT 7 7 3 7
DEPOSIT 3 5 5 7
DEPOSIT 7 7 3 0
LOAD ADDRESS 4000/
START

Table 6-7
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled 158A2 and l59A2)
ROM
ADDRESS

MEMORY
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

AUTOIRESTART
LOAD ADDR ESS 0000
AUTOIR ESTART
LOAD FIELD OISTART
AUTOIRESTART
LOAD ADDRESS 0200
AUTO-RESTART
LOAD F IELD OISTART
AUTO-RESTART
LOAD ADDR ESS 2000
AUTO-R ESTART
LOAD FIELD OISTART
AUTO-RESTART
LOAD ADD RESS 4200
AUTO-R ESTART
LOAD FIELD OISTART
HIGH-LOW PAPERTAPE
LOAD ADDRESS 7737
LOAD FIELD 0
DEPOSIT 6014
DEPOSIT 3376
DEPOSIT 7326
DEPOSIT 1337
DEPOSIT 2376
DEPOSIT 5341
DEPOSIT 601 1
DEPOS
DEPOS
DEPOS
DEPOS
DEPOSIT 1345
D EPOS IT 3357

Table 6-7 (Cont)
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled l58A2 and 159A2)

ROM
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

7754

1345

DEPOSIT 1345

7755

3367

DEPOSIT 3367

7756

6032

DEPOSIT 6032

7757

6031

DEPOSIT 6031

7760

5357

DEPOSIT 5357

7761

6036

DEPOSIT 6036

7762

71 06

DEPOSIT 7106

7763

7006

DEPOSIT 7006

7764

7510

DEPOSIT 751 0

7765

5374

DEPOSIT 5374

7766

7006

DEPOSIT 7006

7767

6031

DEPOSIT 6031

7770

5367

DEPOSIT 5367

7771

6034

DEPOSIT 6034

7772

7420

DEPOSIT 7420

7773

3776

DEPOSIT 3776

7774

3376

DEPOSIT 3376

7775

5356

DEPOSIT 5356

7737

0023

0000

LOAD ADDRESS 7737/
START
RK8/E
LOAD ADDRESS 23
LOAD FIELD 0

0023

2200

DEPOSIT 2200

0024

6745

DEPOSIT 6745

MEMORY
ADDRESS

Table 6-7 (Cont)
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled 158A2 and l59A2)
ROM
ADDRESS

MEMORY
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

DEPOSIT 0023
DEPOSIT 7640
DEPOSIT 5024
DEPOSIT 6743
DEPOSIT 5031
LOAD ADDRESS 24/
START
RX8E
LOAD ADDR ESS 0024
LOAD FIELD 0
DEPOSIT 7126
DEPOSIT 1060
DEPOSIT 6751
DEPOSIT 7201
DEPOSIT 4053
DEPOSIT 4053
DEPOSIT 7104
DEPOSIT 6755
DEPOSIT 5054
DEPOSIT 6754
DEPOSIT 7450
DEPOSIT 7610
DEPOSIT 5046
DEPOSIT 1060
DEPOSIT 7041

Table 6-7 (Cont)
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled 158A2 and 159A2)
ROM
ADDRESS

MEMORY
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

DEPOSIT 1061
DEPOSIT 3060
DEPOSIT 5024
DEPOSIT 6751
DEPOSIT 4053
DEPOSIT 3002
DEPOSIT 2050
DEPOSIT 5047
DEPOSIT 0000
DEPOSIT 6753
DEPOSIT 5033
DEPOSIT 6752
DEPOSIT 5453
DEPOSIT 7024
DEPOSIT 6030
LOAD AD DR ESS 00331
START
R F08lD F32D
LOAD ADDRESS 7750
LOAD FIELD 0
DEPOSIT 7600
DEPOSIT 6603
DEPOSIT 6622
DEPOSIT 5352
DEPOSIT 5752

Table 6-7 (Cont)
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled 158A2 and 159A2)
ROM
ADDRESS

MEMORY
ADDRESS

CONTENTS
(ROM and/or
MEMORY)

7750

COMMENTS

0000

LOAD ADDRESS 77501
START
TA81E
LOAD ADDRESS 4000
LOAD FIELD 0

1237

DEPOSIT 1 237

1206

DEPOSIT 1206

6704

DEPOSIT 6704

6706

DEPOSIT 6706

6703

DEPOSIT 6703

5204

DEPOSIT 5204

7264

DEPOSIT 7264

6702

DEPOSIT 6702

7610

DEPOSIT 7610

321 1

DEPOSIT 321 1

3636

DEPOSIT 3636

1205

DEPOSIT 1205

6704

DEPOSIT 6704

6706

DEPOSIT 6706

6701

DEPOSIT 6701

521 6

DEPOSIT 521 6

7002

DEPOSIT 7002

7430

DEPOSIT 7430

1636

DEPOSIT I636

7022

DEPOSIT 7022

4000

Table 6-7 (Cont)
ROM No. 1 and ROM No. 2 Listings
(for ROMs Labeled l 5 8 A 2 and l59AZ)
ROM
ADDRESS

MEMORY
ADDRESS
-

CONTENTS
(ROM and/or
MEMORY)

COMMENTS

4024

DEPOSIT 3636

4025

DEPOSIT 7420

4026

DEPOSIT 2236

4027

DEPOSIT 2235

4030

DEPOSIT 521 5

4031

DEPOSIT 7346

4032

DEPOSIT 7002

4033

DEPOSIT 3235

4034

DEPOSIT 5201

4035

DEPOSIT 7737

4036

DEPOSIT 3557

4037

DEPOSIT 7730
LOAD ADDR ESS 40001
START

6.21.2 Auto-Restart Operation and Timing
The auto-restart portion of the M8317 module restarts the PDP-8/A after a power failure or when power is turned on
or 0000.The address is switch selectable
locally or remotely. The program may be started at address 4200,2000,0200,
on the M 8 3 1 7 module.
The computer must start by executing the instruction stored in the starting location.
The CPMA register and the IF and DF registers in the memory extension portion of the M8317 module must be
loaded with the starting address before CPU timing is allowed to start. Before start-up, all devices must be initialized
and the Major State register must be manipulated so that it starts out in the Fetch major state. The auto-restart
logic accomplishes this by asserting the Omnibus signals and performing transfers that normally occur from the Programmer's Console.

At the Programmer's Console, the start-up procedure is as follows:

2.
3.

Enter the Instruction Field and Data Field and press LXA (load DF and I F registers).
Enter starting address and press LA .
Press INI T and then RUN (Initialize and start from FETCH).

These operations are performed by the auto-restart portion of the KM8-AA.
The timing for this operation is shown in Figure 6-41. The detailed logic description of this operation is given in Paragraph 6.22.
The starting addresses (0000, 0200, 2000 and 4200) are stored in a 256 X 8 ROM along with the necessary control bits. The first ROM address to be accessed when the auto-restart operation begins is determined by switches on
the M8317 module which preset the ROM address counter to this first address. The address counter is. then incremented to read four ROM memory locations, which supply the field, the starting address and the necessary control signals required to load the field and starting address, initialize the processor, and start the program. Four of the
256 ROM locations are used for each of the starting addresses, a total of 16 addresses for the auto-restart operation. Except for the last 4 3 locations, the remainder of the ROM chip is used for bootstrap operation. (Refer to
Table 6-6 and Figure 6-40).

SEQUENCE I-

-BOOTSTRAP

AUTO- RESTART SEQUENCE4-

CLOCK^^;;
POWER O K H

;

n:;n

7f1

n:fn
SEE N O T E 2

AC LOW L

sw
A / R F/F L
!

"
!
_
7
P
'
I

- 1

INIT H

'--<+-

I
I

<SEE

NOTE 1

^____\Ã‘Ã‘Ã

H O LD F/F- H ÃˆÃ‘Ã‘Ã‘Ã‘Ã‘

SEE NOTE 3

A/R F/F L

0
-'

N I T GO F/F L

, ---"A" F / F H

'
L

-"B" F /-F H GO F/F H
-,

A C T I V E F/F H

7
~
v

CH6 SET CLOCK
ENABLE L
MX P W R OK L

SEE NOTE 3
IÃ‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã

SEE NOTE 3
-I

E
-I5
SEE NOTE 4

5. GO F I F CLEARS AT THE END OF
CYCLE.
6 , SEE D FO.KMB A FOR DETAILED
TIMING D A T A AFTER ACTIVE IS SET
1 . THE SWITCHING TIMES FOR AC LOW
ARE A FUNCTION OF THE SLEW
RATE OF THE CIRCUITS I N THE
POWER SUPPLY.

Figure 6-41

,
,
7

NOTES.
1. CLOCK ENABLE M A Y BE FALSE A T

THIS TIME, I F I N I T H IS FALSE.
CLOCK ENABLE THEN RETURNS HIGH
[ASSERTED1 WHEN I N I T H BECOMES
TRUE.
2 THE LOGIC WAITS FOR I N I T I A L I Z E
TO START OR E N 0 BEFORE CONTINUING
3 THESE FLIP FLOPS ARE CLEARED A T
THE CONCLUSION OF THE AUTO
RESTART CYCLE
4. ACTIVE SETS O N THE N E X T CLOCK
PULSE THEN CLEARS A T THE END
OF THE CYCLE

Auto Restart and Bootstrap Timing

6.21.3 Bootstrap Operation and Timing
The bootstrap operation portion of the M 8 3 1 7 logic is used to load short programs into memory which are used to
load programs from system devices and to start the program at the specified location. A bootstrap operation is initiated by pressing BOOT on the Programmer's Console twice or by raising and' lowering the BOOT switch on the
Limited Function Panel.
When the Bootstrap operation is initiated the following occurs:
1.

The CPU is initialized.

Load extended address and starting address to define the first address in which to deposit instructions.

Deposit instructions in sequential locations.

Load the starting address of the program just deposited.

Start the program.

In this operation the content specified locations in the 2 5 6 X 8 ROM is used to furnish the field, starting address,
control signals, and programmed instructions required to transfer a program from a system device (Table 6-6). The
specified location in ROM from which this information is obtained is determined by switches on the M8317 module.
The timing required for this operation is shown in Figures 6-41 and 6-42. The detailed logic description of this operation is given in Paragraph 6.22.

CLOCK

NOTES.
1
ONE "0EPOSIT"CVCLE I S SHOWN I N
DIAGRAM.
2. W E N "RUN" IS TRUE ILOWI A L L TIMING
IS HELD OFF U N T I L THE N E X T CLOCK
PULSE AFTER "RUN"G0ES FALSE IMIGHI
3 FOR THE "LOAO ADD" CYCLE SIGNALS
REMAIN M E SAME AS SHOWN EXCEPT
THAT "PULSE LOAO ADD" REPLACES
"MEM START'' A N D "KEY CONTROL'' IS
NEGATED. FOR "EXT LOAD AOO" KEY
CONTROL I S TRUE.
4. M E M START APPEARS HERE O N L V FOR
THE "START" FUNCTION. THE EARLIER
M E M START I S FOR "DEPOSITS" O N L V

CLOCK I
CLOCK 2

SW F/F H

S E T ROM A D D F/F H

( P U L S E L O A D ADD)
M E M START L

1
I

KEY C O N T R O L L

I
I

A SEE N O T E 4

DATA L I N E S L

I
RUNL
08-1364

Figure 6-42

Bootstrap Timing

6.22 POWER FAIL/AUTO-RESTART A N D BOOTSTRAP OPERATION DETAILED LOGIC DESCRIPTION
Some of the functional groups of logic on the M 8 3 1 7 are shared by the power fail/auto-restart and the bootstrap
option. During this discussion it will be pointed out that when a functional group of logic applies to only one of the
operations, or if it applies to more than one operation and its use. The block diagrams in Figures 6-36 and 6-37
should be used to determine which groups of logic are used by the individual operations and the interrelationship between the groups of logic as well as the signal flow.

6.22.1 Power Fail/Auto-Restart Device Select and Operation Decoder
The Power Fail/Auto-Restart device select and operation decoder logic is shown in Figure 6-43.

INTERNAL
BBUF MD11 H -

B BUF MD7 H

BBUFMD6H

BBUF MD10 H

M2
~2

ROM M 3
y36
MIKP M 4

6102

BBUF MD 9 H 610x<

OPERATION
DECODER F 5 ^

%;q
:$- A 4
B BUF MD5

AS
-J

MD11 L ( O L D

M D 3 L (API)
4
B l )
B BUF I / O PAUSE H

7404

Figure 6-43 Power Fail Auto Restart Device
Select and Operation Decoder
ROM No. 3, the device select decoder, is enabled by M D 3 L, M D 4 L and BBUF I/O PAUSE H when a 61XX instruction is executed by the program. When the ROM is enabled, it is addressed by BBUF M D 5 H-BBUF M D 8 H
and the AND of M D 9 L, BBUF M D 1 0 H, and MD1 1 L. When a 61 OX instruction is executed by the program, the
ROM address selected supplies an output which asserts INTERNAL I/O L and the 610X device select signal. INTERNAL I/O L is asserted t o tell the KA8-E Positive I/O that the instruction is not t o be decoded by the KA8-E. The
6 1OX signal enables the operation decoder to decode the 6 1 0 1 and 6 1 0 3 instructions. When the program executes
a 6 1 0 2 (SPL) instruction the output of AND gate E31 adds an additional bit to the ROM address t o select the location with an output which asserts INTERNAL I/O L and the 6 1 0 2 signal line.
This causes the power fail/auto-restart option t o execute the 6 1 0 2 instruction.
The operation decoder is enabled by the 610X signal when a 610X instruction is decoded by the program. The operation decoder is a 7 4 4 2 1C. The 7 4 4 2 1C is a BCD t o decimal decoder which decodes BBUF MD9-BBUF M D 1 0 and
asserts the necessary signals t o execute the 6107 and 6 1 0 3 instructions.
6.22.2 Power Fail Interrupt and Skip Logic
The power fail interrupt and skip logic is shown in Figure 6-44. There are t w o flags associated with SKIP L and INT RQS"'
L - 1. The AC LOW flag, which is set by AC LOW L from the power supply when the ac voltage falls below a specified
level, and 2. the BATTERY EMPTY flag, which sets when BATTERY EMPTY L is asserted by the power supply logic
(applicable only t o PDP-8/A Semiconductor computers). BATTERY EMPTY L is asserted prior t o depletion of the battery
so that the battery will never completely discharge. A fully loaded system runs approximately 4 5 seconds on battery
power.
INT RQST L is asserted to interrupt the program if the BATTERY EMPTY or the AC LOW flags sets. The program
must check the flags and determine which one caused the interrupt and what action is t o be taken.
SKIP L is asserted to cause the program to skip an instruction if flag AC LOW is set or the AC LOW level is asserted and the 6102 instruction is executed or if BATTERY EMPTY is set and the 6 1 0 1 instruction is executed. AC
LOW flag is cleared by the 6 1 0 3 instruction, but the program may still check the level by using the 61 02
instruction.

6.22.3 Bootstrap and Auto-Restart Timing Clock
The bootstrap and auto-restart clock logic in Figure 6-44 generates two clock signals, CLK1 and CLK2, which provide the timing pulses for the bootstrap and auto-restart operations. The MIKP1 CLK signal is generated by a 6 6
kHz (approximately) RC oscillator. The clock signal is disabled by holding ENA (E65) cleared, during initialization and
power up operations or when the bootstrap and auto-restart logic is in an inactive state (ACTIVE flip-flop cleared
and HOLD flip-flop set). The timing for the generation of CLK1 and CLK2 is shown in Figure 6-45. CLK1 and CLK2
pulse duration is approximately 7.5 us; both input to the JK flip-flop (E90) so that it complements on trailing edge
of each clock pulse. AND gates E86A and E86B are enabled on alternate clock pulses to generate two differentclocksignals at half the frequency of the MIKP1 CLK H signal.
6.22.4 Bootstrap Initialization Logic
The purpose of this logic is to initialize the CPU, Extended Memory Control and all peripherals, preset the ROM address counter to the address selected by the bootstrap select switches, set flip-flops to provide enabling signals for
the bootstrap operation, and clear the control shift register.
If S1-8 is on the bootstrap operation (Figure 6-46) is initiated when SW makes a low to high transition to clock the
HOLD flip flop causing it to set. If S1-4 is on HOLD will set only if the PDP-8/A is stopped. When HOLD sets, it
enables the clock (Figures 6-45 and 6-46) and clears INIT GO. The first CLK1 pulse after HOLD is set, sets flip-flop
A and B which enables AND gate E64. The high out of E64 turns Q1 on and the POWER OK H line is pulled low.
Asserting POWER OK H allows the CPU to negate INITIALIZE H after 2 0 0 to 1000 ms. The negation of INITIALIZE H and having cleared flip-flop A sets INIT GO.
The next CLK pulse after flip-flop A is cleared clears flip-flop B, which sets the GO flip-flop. If S1-7 is open, NAND
gate EGO is enabled when go sets to assert MIKP1 ENA BOOT ADD L. This enables the address selected by the
bootstrap switches to preset the ROM address counters to the address of the first ROM location to be accessed during the bootstrap operation Paragraph 6.21.3). The address is loaded into the address counter by the assertion of
MIKP1 ADD LOAD L during the next CLK2 pulse. ROM A SET is not cleared until ACT is set by the next CLK1
pulse so NAND gate E54 is enabled.
The next CLK1 pulse sets ACT, which in turn clears ROM A set and allows IDLE to clear on the next CLK1 pulse.
ROM A is held cleared to disable NAND gate E54 and hold MIKP1 LOAD ADD L high to remove the input from the
bootstrap select switches to the ROM address counters. At this time, the ROM address counters are preset to the
address of the first ROM location to be accessed.
At this point, control of the bootstrap operation is taken over by the four control bits out of ROM No. 1 control
counter (Paragraph 6.2 1-3).

6.22.5 Auto-Restart Initialization Logic
The purpose of this logic is to Initialize the CPU, the Extended Memory Control and all peripherals, preset the ROM
Address counter to the address selected by the auto-restart switches, set the necessary flip-flops to provide enabling
signals for the auto-restart operation, and clear the control shift register (Figure 6-47).
An auto-restart operation is initiated when AC LOW L is negated after power is turned on. The initialization and conditioning of the logic to enable an auto-restart operation is similar to the bootstrap operation so this description will
not be repeated.
Having disabled NAND gate E54, and not running the CPU enables the data input to the AR flip-flop, and when AC
LOW L is negated (high) the AR flip-flop sets. If S1-6 and S1-7 are ON (closed) the MIKP1 ENABLE RESTART
ADD L is asserted to apply the address selected by the auto-restart switches to the address counter input. ROM A
set is dc set by having cleared ACT during the initialization during power up. NAND gate E54 is enabled by CLK2
and MIKP1 ADD LOAD L presets the address counter with the address selected by the auto-restart switches. ROM
A is cleared, and the next CLK2 pulse after IDLE is cleared as it was for the bootstrap operation (Paragraph 6.21.3).

Figure 6-46

CLK1 and CLK2 Timing

6.22.6 Auto-Restart and Bootstrap Address Counters
The address counters in Figure 6-48 are preset to the first ROM address to be accessed when an auto-restart or
bootstrap operation is started. The first address is always an even number. The 2 8 2 6 6 IC's select either the condition of the bootstrap select switches or the auto-restart switches as input to the address counters. The address
counter, consisting of t w o 74197 ICs is loaded when MIKP1 ADD LOAD L is asserted (see Figure 6-47). Incrementation of the counter takes place at the end of a control register cycle where CLK2 is ANDed with RECYCLE
asserting MIKP1 INCRMT ADD counter L. The bootstrap and auto-restart switch settings are listed in Tables 2-1 0
through 2- 13.
6.22.7

R O M Memory Control and Multiplexers
ROM Nos. 1 and 2, along with their associated multiplexers and control logic, are shown in Figure 6-49. The ROMs
are addressed by the address counter and supply as output four control bits and a 12-bit word (Figure 6-38). The
control bits are used to generate control signals which are used to load an extended memory address (field), load the
memory address, or deposit a 12-bit word into read/write memory. The first 16-bit word read from memory also contains a bit which asserts MIKP2 START H. This signal is used to assert INITIALIZE H (Figure 6-49) during the first
pass through the control shift register, and initialize the CPU, extended memory option, and all peripherals. The content of the two addressed locations in ROM Nos. 1 and 2 are transferred to the Data Bus during TS2 for deposit
operations or by MIKP2 ENA DATA H to load the extended address or memory address.
MIKP2 ENA ADD DATA H is asserted by outputs of the control shift register (Figure 6-50) to enable the address
data.

6.22.8 Bootstrap and Auto-Restart Operation Control Logic
The function of the control shift register and the associated logic is to assert the Omnibus signals required to address memory deposit information in a memory location and start the program. During auto-restart operations, a
memory address is loaded into the memory address register and the program is started in field 0 at the selected
address.
The control shift register is a 7 4 1 6 4 1C used as an 8-bit shift register. A high on the two serial inputs allows the
first bit to become a one on the first CLK1 pulse after ROM A sets. Subsequent clock 1 pulses will shift the 1
through the shift register and as it is shifted, the control signals on the output are asserted to assert the necessary
Omnibus and control signals for the bootstrap and auto-restart operations. The timing required for these operations
is shown in Figures 6-43 and 6-44. In subsequent passes the bit 1 in the shift register is set to 1 by RECYCLE out
of the shift register.
A description of the Omnibus signal, asserted by the control signals out of the control shift register, is in Chapter 3.

A C LOW
L (Be11

Figure 6-47

Auto Restart Initialization Logic

ADDRESS
TO ROM
AND R O M # 2

LSB

AUTO
RESTART
SELECT

BOOTSTR
SELECT

MIKP1 ENABLE RESTART ADD L

MIKP1 ENA BOOT ADD L

MIKP1 ADD LOAD L

M I K P I INCRMT ADD COUNTER L

Figure 6-48

Auto Restart and Bootstrap ROM
Address Counters

MIKP1 LOAD 1ST ROM BYTE H

1 I

MIKP1 CLR L
T

M I K P 2 LOAD ADD H
I

ADDR
CNTR
(E911

MIKP2 LOAD EXT ADD H

ADD
CNTR
E 87

Figure 6-49

ROM Memory Control and MUX

M I K P 2 LOAD ADD H

LOAD ADD ENA L ( B M 2 )
M I K P 2 LOAD ADD ENA L
IND1 L ( C U 2 )

M I K P 2 DEPOSIT H
KEY CNTRO L ( D U 2 )

I
CLK 2

MIKP1 LOAD 1ST ROM BYTE H

SET-UP
E79
CONTROL
SHIFT
REGISTER
l

R3(D
R4(1)
R5(1)

PULSE

M I K P 1 ENA ADD DATA L

NULL
CLR
-

\ <

^ ,SER IN

1 1-

MIKP1 INCRMT ADD COUNTER L

C LR
CONT

B BUFF POWER OK H

MIKPI CLR L
CLK 1

M I K P 2 START H

7403

Figure 6-50 Bootstrap and Auto Restart
Operation Control Logic

PULSE L A H
(DR2)

CHAPTER 7
POWER SUPPLY

7.1 GENERAL
There are two types of computers in the PDP-8/A family, namely, the PDP-8/A Semiconductor computer and the 8Aseries of computers. A basic difference between these two types is their respective memories. The PDP-8/A uses
semiconductor memories that have capacities ranging from 1K to 4K (a maximum capacity of 32K is possible). The 8Aseries of computers uses expandable core memory of 8K or 16K. The PDP-8/A Semiconductor computer features battery
backup to power the computer during momentary ac power interruptions.
Another difference between the two types of computers is the Omnibus assembly used with each. The PDP-8/A computer uses a 10-slot Omnibus (1-19192)that accommodates both quad and hex modules (connectors E and F of the hex
modules do not plug into the Omnibus), while the 8A computers use either a 12-slot Omnibus (H9194) or a 20-slot
Omnibus (H9195). Both the 12-slot Omnibus and the 20-slot Omnibus have some slots that are reserved for hex
modules whose E connector must plug into the Omnibus. Power for the PDP-8/A is provided by an H763 Power Supply
assembly; this assembly includes a regulator pc board and a power pc board, both of which are inserted in the Omnibus.
Power for the 8A computers is provided either by an H9300 chassis assembly or by a BA8-C chassis assembly, each of
which includes a regulator PC board (pc boards, in the BA8-C) and the necessary Omnibus connector block(s).Table 7-1
summarizes the foregoing and also lists other assemblies that pertain to computer primary power.

Table 7-1
PDP-8/A Family, Primary Power Assemblies
--

Computer Type

Omnibus

Basic Power Assembly

Basic Power Assembly Includes

H763 Power Supply Assembly

G8016 Regulator Board
Power Board
Transformer Assembly
Line Set
Limited Function Panel

H9300 Chassis Assembly

H9194 Connector Block Assembly
G8018 Regulator Board
Transformer Assembly
Line Set
Limited Function Panel

BA8-C Chassis Assembly

H9195 Omnibus
Power Distribution Board Assembly (5412000)
G8Ol8 Regulator Board (2)
Transformer Assembly
Line Set
Limited Function Panel

All the basic power assemblies are discussed in this chapter, Paragraph 7.2 covers the PDP-8/A Semiconductor assembly, Paragraph 7.3 covers the 8A400/600/800 assembly, and Paragraph 7.4 covers the 8A420/620/820 assembly.

7.2 PDP-8/A SEMICONDUCTOR BASIC POWER ASSEMBLY
The basic power assembly for the PDP-8/A consists of the G8016 regulator board, the power board, a transformer
assembly, a line set, and a Limited Function Panel. Figure 7-1 illustrates the assembly interconnections. The Limited
Function Panel has been described in Paragraph 4.3.1, the regulator board is described in Paragraph 7.2.2, and the
power board is detailed in the following Paragraph 7.2.1.

7.2.1 Power Board
The power board circuits are shown in Figure 7-2 (only 117 V, 6 0 Hz operation is illustrated; fan connections are
not shown). The primary winding of transformer T I is connected across the ac line. The secondary voltage of T I is
rectified and filtered to produce the LINE LEVEL signal that is proportional to the line voltage. When the ON/OFF
switch and the MASTEWSLAVE switch are in the positions shown, relay K1 is not energized. Hence, Line 1 is connected to the primary of the transformer assembly via one of the normally-closed (NC) contacts of K1. If the
ON/OFF switch is moved to the OFF position, both the AC OFF L signal and the BATTERY OFF signal are grounded.
Current flows through the coil of K1, and the relay contacts move to the normally-open (NO) position. The line voltage is removed from the transformer assembly and the power supply shuts down.

LIMITED-FUNCTZ

I. PANEL

MASTER /

B A T T E R Y CHARGING
BATTERY OFF
AC O F F L

I
1

Figure 7-1

POWER

Interconnections, PDP-8/A Semiconductor Basic Power Assembly

If the MASTER/SLAVE switch is in the SLAVE position, K 1 is not energized as long as the POWER REQUEST signal
is grounded at the remote location. However, if the ground is removed from the POWER REQUEST line, transistor
E l conducts, grounding the AC OFF L signal and energizing the relay (BATTERY OFF is grounded via the relay NO
contacts). Once again, the power supply shuts down. Note that when the ON/OFF switch is moved to the OFF position it causes the relay to energize, even though the SLAVE position has been selected.
No matter which switch is used to control line voltage, both AC OFF L and BATTERY OFF are asserted when the
line voltage is purposely removed. The first signal, in addition to its relay-related function, causes the AC LOW L signal to be generated, while the second signal prevents the battery supply from operating (if the computer is equipped
with a battery). If the line voltage fails, the AC LOW L signal is asserted by the AC LOW L circuit, but BATTERY
OFF is not asserted; rather, the +5 V supply begins operating on battery power and does so until either the ac line
voltage is restored or the batteries are nearly drained, whichever occurs first (Paragraph 7.2.2.7 relates the AC LOW
L signal, battery power, and ac line voltage). If the ac line plug is pulled from the outlet while the switches are still
in the ON positions, the supply will go on battery power before shutting off; obviously, one should not remove
power in this way.
When the regulator board is not inserted in the power board connectors, transistor Q1 conducts, providing a path for
relay coil current; thus, the relay is energized and ac line voltage is not connected to the transformer assembly. Pins
AB2 and AA2 on the regulator board are connected; hence, when the board is inserted, pins AB2 and AA2 of J 1 0
are connected and Q 1 is turned off.

7.2.2 Regulator Board (G8016)
The G8016 regulator board is built on a quad module; the module can be inserted in pc board connectors mounted
on the power board of the 1-1763 assembly. The regulator board provides three dc voltages - + 5 Vdc,
15 Vdc, and
-1 5 Vdc. While the ferro-resonant transformer assembly (part of the H763 assembly) provides basic voltage regulation, a series regulator is used to generate the + 5 Vdc voltage. The & 15 Vdc voltages are derived from the 4- 5
Vdc circuit by an inverter circuit. The supplies have internal battery backup; automatic shift to battery-powered operation occurs when the ac line voltage falls below a selected level.

Figure 7-3 is a block diagram of the G8016 regulator board. A decision circuit in the i - 5 Vdc series regulator monitors the output of the ferro-resonant transformer secondary. If the voltage is above a specified level, the regulator
operates under ac power; otherwise, battery power is selected.

AC OPERATION

I ,

I
BATTERY
0 PERATION

w +5 VDC
4

k 15 VOLT
CIRCUIT

m ?15 VDC

POWER OK H
CIRCUIT

BATTERY

POWER OK H

ACLOWL

LINE LEVEL
AC OFF L

Ãˆ

BATTERY
EMPTY
CIRCUIT

-BATTERY
EMPTY L

BATTERY
CHARGING

Figure 7-3

G8016 Regulator Block Diagram

The
5 V output is generated by the 4-5 V regulator circuit. This output is used to generate the 15 V outputs and is
monitored by the POWER OK H circuit. As long as the 4-5 V output remains in regulation (within approximately 5 0
mV of the adjusted + 5 V level), POWER OK H remains high. If the output goes out of regulation, POWER OK H
goes low. POWER OK H being negated causes the CPU timing generator to halt and the AC LOW L signal to be
asserted.
The AC LOW L circuit, besides responding t o POWER OK H, monitors the AC OFF L signal, which is generated
when the operator turns off power from a remote location or with the ON/OFF switch, and the LINE LEVEL signal,
which is a measure of the ac line voltage.
If the supply shifts to battery-powered operation because of low line voltage, the battery empty circuit might generate the BATTERY EMPTY L signal. This would occur if the supply remains on battery power long enough for the batteries to discharge to a near empty state. The signal causes a program interrupt request to be generated by circuitry
on option board 2 (M8317).
If the batteries have been used to operate the supply, they must be re-charged when ac-powered operation is resumed. The battery charging circuit operates in this situation, asserting the BATTERY CHARGING signal until the batteries are re-charged to 90% capacity.

7.2.2.1 + 5 Vdc Regulator Circuit - The + 5 Vdc regulator circuit is illustrated in Figure 7-4. The output voltage
can be adjusted between 4.5 and 5.5 V by potentiometer R33. The supply regulates against line voltage variations
and load variations and features both over-current and over-voltage protection. In addition, excessive heat sink temperature causes the circuit breaker, CB 1, to open, shutting down the supply.
The rectifier diodes, D l and D2, supply about +8 V dc to the emitter of the series pass transistor, Q1 1. This positive voltage allows Q12 to conduct, providing base drive for the pass transistor. Q12 regulates the amount of base
drive supplied to Q11 by sampling the output voltage at the collector of Q1 1. If the output voltage, 4-5 Vdc, tends
to decrease, the voltage at the base of Q 15 goes less positive, causing Q15's collector current to decrease. This decrease raises the base potential of Q14, which then conducts less and provides less base current for Q13. Q13
draws less collector current; the base current of Q12 increases accordingly, resulting in increased drive for the pass
transistor. The increased base drive reduces the effective series resistance; thus, the collector voltage of Q 1 1 rises to
counteract the original drop. If the 4-5 V output tends to increase, Q13 shunts more current away from the base of
Q12, resulting in less base drive for the pass transistor and causing the voltage change to be opposed.

Figure 7 - 4

4-5 Vdc Regulator Circuit

If the output current exceeds 3 0
2 A, or if the 4-5 V supply is shorted t o ground, CB1 opens, shutting down the
supply. Over-voltage protection is provided by the SCR, D9, and Zener diode D l 6. When the 4-5 V output rises to
between 5.7 and 6.3 V, the Zener diode con!ducts. The voltage applied to the gate of D9 causes the SCR to fire,
shorting the input circuit and causing CB1 to open. Protection against excessive heat sink temperature is carried out
in the same way, i.e., the SCR is fired by a gate voltage, causing CB1 to open. If the temperature rises above 230Â
F (1 10Â C), thermal switch S1 closes, connecting the firing voltage to the SCR. The switch opens when the temperature cools to 194O F (90Â C); however, the circuit breaker must be reset manually.
If the regulator board is moved out more than one-eighth of an inch from its full-seated position in the power board
connectors, the 4-5 Vdc voltage is connected to pin BP2. The SCR is fired, opening the circuit breaker and shutting
down the supply. Figure 7-5 illustrates part of edge connector B of the regulator board: The dotted lines represent
pin BP2 of the power board connector, which is connected to + 5 Vdc. As long as the regulator board is properly
seated, the two pins do not make contact. If the regulator board is raised (in the arrow direction), BP2 on the regulator board connector makes contact with BP2 on the power boardconnector.

7.2.2.2 + 5 Vdc Regulator Circuit, Battery Operation
Figure 7-6 shows the significant circuit components of
the +5 V regulator circuit when that supply is operating with battery power. Transistor Q6 becomes the pass transistor, while control of the base drive for Q6 is effected by Q7 (Q7 and Q9 function analogously to Q12 and Q13 in
Figure 7-4).
Battery operation commences when an ac line voltage failure occurs (Paragraph 7.2.2.7 relates battery operation to
line failures). Zener diode D3, which conducts during normal ac line voltage operation, opens when the rectified voltage falls below that necessary to sustain conduction. When the diode opens, transistor Q1 stops conducting, removing the ground from the base of Q10 and allowing it to turn on. When Q10 conducts, Q8 also turns on and supplies
collector current to Q9. Thus, Q9 can shunt more or less current from the base of Q7, depending on whether the
+ 5 V output tends to increase or decrease, respectively.
The batteries can be damaged if they are allowed to discharge completely; consequently, transistors Q8 and Q10
turn off the supply before the discharge is complete. Q10 is biased so that it turns off when the 4-5 V output drops
out of regulation due to a dying battery; Q8 does likewise, causing Q7 to do the same. Thus, the pass transistor
stops conducting and the batteries cease to drain. The supply remains inactive until ac power is restored.
Battery operation of the supply must not begin when the ac power is turned off by the operator. The BATTERY OFF
signal, grounded by the Limited Function Panel ON/OFF switch or by the power board relay, K1, is applied to the
base of Q7. This ground ensures that both 0 7 and Q6 remain non-conducting; thus, the batteries do not drain
through Q6.

Figure 7-5

Regulator Board Edge Connector

7.2.2.3 Battery Empty Circuit If the ac line voltage drops below a specified value, battery-powered operation
begins. The batteries can sustain operation for a limited period of time; when this period is about to expire, the BATTERY EMPTY L signal is asserted. Interrupt logic on option board 2 generates an interrupt request and a program
subroutine is entered to prepare for the imminent power shutdown. The battery empty circuit is shown in Figure 7-7.
Transistor Q1 8 measures the voltage across the battery series pass transistor 0 6 . As long as Q6 is not in saturation
Q18 will conduct. When Q6 nears saturation (indicating battery failure is imminent) 0 1 8 stops conducting and
causes BATTERY EMPTY L to be asserted.

5 V supply is in regulation, a positive voltage on the base of Q1 9 causes it to conduct. The base of Q 17
When the
becomes more positive and 0 1 7 conducts, allowing 0 1 6 to turn on ( 0 1 6 turns off when there is no + 5 V, preventing discharge of the battery). The voltage present at the emitter of Q6 is applied through 0 1 6 to the emitter of
Q18. The base of 0 1 8 is connected directly to the collector of Q6; thus, the emitter-base bias of Q18 is dependent
upon the voltage across Q6, the battery regulator transistor. The values of resistors R42 and R43 are chosen so that
as long as Q6 is not in saturation, 0 1 8 will conduct. This will keep the base of 0 2 0 positive, and Q20 will conduct,
preventing the BATTERY EMPTY L signal from being asserted. When Q6 nears saturation, indicating the battery is
nearly exhausted, Q18 will no longer have enough base current to conduct. When Q18 stops conducting so, too, will
Q20; BATTERY EMPTY L will be asserted.
BATTERY EMPTY L is asserted immediately when the ONIOFF switch is turned to the OFF position, due to the AC
OFF L input at the base of 0 1 9 . This input causes 0 1 9 , 0 1 7, and Q16 to stop conducting, turning off 0 1 8 , and asserting BATTERY EMPTY L.

7.2.2.4 Battery Charging Circuit - The battery charging circuit is shown in Figure 7-8. The batteries are charged,
if necessary, when ac power is applied after having been turned off for some reason. When the voltage supplied by
the rectifier diodes, D l and D2, reaches a level that is sufficient to cause Zener diode D3 to conduct, transistor 0 5
turns on and draws current from the differential amplifier Q3/ 0 4 . The differential amplifier controls transistor 0 2 ,
which supplies charging current to the batteries through diode D4.

BTl
BT3

OFF L

Figure 7-7

Battery Empty Circuit

BATTERY
CHARGING

:
ETl

ET3
ET4

- ET2

08-1331

Figure 7-8

Battery Charging Circuit

The base of Q4 is held at a temperature variable reference voltage of approximately i - 2 . 4 V by Zener diode D7. Potentiometer R8 is adjusted so that the base of Q3 is at +2.4 V when the batteries are fully charged to i-9.4 V. If
the batteries need to be charged, the base of Q3 will be something less than i-2.4 V; hence, 0 4 conducts more
heavily than 03, lowering the base voltage of 02. Q2 supplies charging current to the batteries until they are
charged to the +9.4 V level. As the batteries are charging to this level, the differential amplifier is approaching the
balanced state; Q4 is conducting less, Q3 is conducting more, and the base voltage of Q2 is increasing. At the equilibrium condition, Q2 supplies only enough current to maintain the condition of Q3; thus, the batteries stop charging.
Diode D4 prevents the batteries from discharging through R8 t o ground when the supply is turned off.

7.2.2.5 & 1 5 Vdc Circuit - The & 15 V supply, shown in Figure 7-9, is an inverter circuit that is driven by the 4-5
V regulated output voltage. The 4-5 V output is applied to the center tap of T I and t o the base of both 0 2 6 and
Q27. When the power is turned on and the +5 V output approaches its operating level, one of the two transistors
will turn on before the other. If we assume that Q26 begins conducting first, then current begins to flow through the
primary winding from pin 2 to pin 1. The magnetic field generated in the core induces a voltage in the feedback
winding (pins 4-5). This induced voltage is of a polarity that supports the conduction of 026, while ensuring that
0 2 7 remains non-conducting. When the transformer saturates, the field in the feedback winding changes polarity,
causing 026 to turn off and 027 t o turn on. The current flowing in the primary from pin 2 to pin 3 induces a voltage in the feedback winding that supports the conduction of (227. Once again, the field reverses when the transformer saturates; Q27 turns off and Q26 turns on, The transistors alternate in the on/off cycle as long as
5 V is
applied to L1.

Each half of the secondary of T I contains about three times the number of turns as does each primary winding. Consequently, each half of the secondary winding will have an alternating voltage of about 15 V induced in it. This alternating voltage is rectified to produce the & 15 Vdc supply voltages.

7.2.2.6 POWER OK H Circuit - The POWER OK H circuit (Figure 7-10)monitors the + 5 Vdc regulated voltage,
5 Vdc output deteriorates,
asserting the POWER OK H signal as long as the voltage remains in regulation. If the
0 2 4 turns on, bringing POWER OK H near ground.

t5v

Figure 7-9

zk 15 Vdc Power Supply

POWER ,OK H

*
Figure 7-10

POWER OK L Circuit

When the supply is energized and the + 5 Vdc voltage is present and in regulation, the collector of 0 1 4 will be between 1.2 and 1.4 V. This voltage is applied to the base of 0 2 1 , causing it to conduct. 0 2 2 does not conduct; thus,
capacitor C4 charges to 15 V. 3 0 0 to 4 0 0 ms are required for C4 to charge to a value sufficient to allow Q23 to
turn on. When 0 2 3 conducts, 0 2 4 turns off, allowing the POWER OK H signal to be asserted. This positive voltage
feeds through D l 9 to capacitor C4, causing it to complete charging rapidly to prevent spikes on the POWER OK H
signal.
If the input to the + 5 V regulator drops below that required to maintain regulation, the collector of transistor Q14
will drop rapidly below 1 V. This will result in C4 discharging through 022, turning off 0 2 3 and causing Q24 to
ground the POWER OK H signal.

7.2.2.7 AC LOW L Circuit The AC LOW L circuit is shown in Figure 7-1 1. When the ac line voltage drops below a predetermined value, the AC LOW L signal is asserted. Interrupt logic on option board 2 uses the AC LOW L
signal to generate a program interrupt. The program will test for the AC LOW L condition and proceed to a subroutine designed to handle the situation.
E l is a differential amplifier that controls transistor Q25. Pin 3 of E l is held at a reference voltage by Zener diode
D22, while pin 2 is supplied with a voltage that is proportional to the ac line voltage. If the line voltage drops below
9 5 V (this level is determined by the setting of potentiometer R60), the LINE LEVEL signal causes the voltage at pin
2 of E l to drop below that of pin 3. The output at pin 6 goes positive, turning on Q25 and grounding the AC LOW
L signal.
If the line voltage begins to rise after a momentary failure, it must rise to some value higher than 9 5 V before pin 2
reaches a voltage sufficient to cause pin 6 to go low. This is because the resistance from pin 2 to ground is lowered
when the AC LOW L signal is asserted. The level to which the line voltage must rise (105 V for a 1 17 V system) is
set by potentiometer R63; when this level is reached, pin 6 goes low, turning off Q25 and negating AC LOW L.
Figure 7-12 shows a waveform that represents the RMS value of the ac line voltage as it might appear during a period of instability. When the RMS value drops below 9 5 V, the AC LOW L signal is asserted. lf the voltage returns to
1 0 5 V, AC LOW L is negated. This minimum line voltage at which the supply will operate depends on the load requirements. When this minimum is reached, the supply begins to operate under battery power. The batteries support
the supply for a period of time that also depends on load requirement (Figure 7-13 relates both minimum line voltage and battery support time to percent of full rated load).
Figure 7-12 illustrates the situation when the supply operates at 75% rated load. AC LOW L is asserted when the
RMS line voltage drops below 9 5 V. When this happens, an interrupt request will be generated by option board 2,
and a program subroutine will examine the situation. If the BATTERY EMPTY L signal is asserted while the AC LOW
L signal is low, another interrupt request is generated; a program subroutine will prepare for the imminent power
shut-down. However, if AC LOW L is negated without BATTERY EMPTY L having been asserted (i-e., either battery
power did not cut in or the batteries did not discharge to the warning point), the system can return to normal
operation.
When BATTERY EMPTY L is asserted, the supply can continue to operate on battery power for at least 1 ms. Then,
the + 5 Vdc output will drop out of regulation, the POWER OK H signal will be negated, and a power shut-down
will follow. When ac power returns, the supply again operates, the batteries begin to charge, and POWER OK H is
asserted. If the line voltage returns above 105 V, normal operation resumes.

LINE LEVEL

A C LOW L

R63
Q25

I[ D23

D20
u
n

POWER OK H

-15V

A C OFF L

D21

Figure 7-1 1

AC LOW L Circuit

t5v

AC VOLTS

I
I

BATTERY E M P T Y L

POWER OK H

SWITCH TO
BATTERY POWER

Figure 7-1 2

I
I

BACK TO
L I N E POWER

SWITCH TO
BATTERY POWER

I
I
I

SUPPLY
OFF

BACK TO
L I N E POWER

Voltage Monitor Waveforms

7.3 8A400/600/800 BASIC POWER ASSEMBLY
The basic power assembly for the 8A400/600/ and 8 0 0 computers consists of the H9194 Connector Block Assembly
(the Omnibus), the G8018 Regulator board, a transformer assembly, a line set, and a Limited Function Panel.
Figure 7-14 illustrates the assembly interconnections. The Limited Function Panel has been discussed in Paragraph
4.3.1; the connector block assembly is described in Paragraph 7.3.1, the regulator board in Paragraph 7.3.2.
7.3.1 H9194 Connector Block Assembly
The Connector Block assembly circuits are shown in Figure 7-1 5 (only 117 V, 6 0 Hz operation is illustrated; fan connections are not shown). The primary winding of transformer T I is rectified to produce the AC LEVEL signal that is
used in the G8018 board POWER OK H circuit. This same secondary voltage is rectified and filtered, producing the
LINE LEVEL signal, a dc level that is proportional to the ac line voltage amplitude.

When the ON/OFF switch and the MASTER/SLAVE switch are in the positions shown, relay K1 is not energized. Hence,
the ac line is connected across each of the two primary windings of the transformer assembly via the normally-closed
(NC) contacts of K1. If the ON/OFF switch is moved to the OFF position both the AC OFF L signal and the BATTERY OFF
signal are grounded. Current flows through the coil of K1, and the relay contacts move to the normally-open (NO)
position. The line voltage is removed from the transformer assembly and the power supply shuts down.
If the MASTER/SLAVE switch is in the SLAVE position, K1 is not energized as long as the POWER REQUEST signal is
grounded at the remote location. However, if the ground is removed from the POWER REQUEST line, transistor E l on the
Limited Function Panel conducts, grounding the AC OFF L signal and energizing the relay. (BATTERY OFF L is grounded
via the relay NO contacts). Once again, the power supply shuts down. Note that when the ON/OFF switch is moved to
the OFF position, it causes the relay t o energize even though the SLAVE position has been selected. No matter which
switch is used to control line voltage, both AC OFF L and BATTERY OFF L are asserted when the line voltage is purposely
removed. BATTERY OFF L causes the AC LOW L signal to be generated. If the line voltage fails, the AC LOW L signal is
asserted in the AC LOW L circuit, but BATTERY OFF L is not asserted.

BATTERY
HOLD-UP T I M E
I N MINUTES

100

% OF FULL RATED POWER

LINE VOLTAGE AT
WHICH BATTERY
POWER CUTS IN
(VOLTS R M S )

% OF FULL RATED POWER
08-1336

Figure 7-1 3 Battery Hold-up Time, Minimum Line
Voltage vs% of Full-Rated Load

When the regulator board is not inserted in the connector block assembly, transistor E1A conducts, providing a path
for relay coil current; thus, the relay is energized and ac line voltage is not connected to the transformer assembly.
Pins AB2 and AA2 on the regulator board are connected; hence, when the board is inserted, pins AB2 and AA2 of
J7 are connected and E1A is turned off.

The regulator board is protected from the effects of excessive temperature. Such temperature causes the thermostat to
activate the emergency shut-down circuit. The thermostat switch t(O), on the regulator board closes when high temperature is detected. The LINE LEVEL signal applied to the base of E1C and E 1B causes both transistors to conduct; relay K1
closes and the EMERGENCY SHUTDOWN L signal is generated, notifying the remote power control location of the shutdown.

'ONNECTOR BLOCK

I
J7

I
I

I
TO
CONNECTOR
BLOCK A S S Y

I
I

v
AC O F F L

AC L E V E L

INTERLOCK

POWER

RECTIFIER

i ^

SWITCHED
LINE 1

II XFMR
ASS'Y
I

I
I

Figure 7-1 4

Interconnections, 8A400/600/800
Basic Power Assembly

+5VDC
-5VDC
AC LOW L
POWER OK H

BATTERY OFF L
AC OFF L

v
A C LEVEL

u A

LINE L E V E L

+15 VDC
-15 VDC

SHUTDOWN

TRANSFORMER
AND RECTIFIER

G8018
REGULATOR
BOARD
+ 2 0 VDC

SWITCHEC
NEUTRAL

Figure 7 - 16

+ 5 Vdc Regulator Circuit

7.3.2 Regulator Board (G8Ol8)
The G8018 regulator board provides dc voltages of 4-5V, -5 V, + 2 0 v, 4- 15 V, and -1 5 V. Like the G8016, the G8018
has ac and dc voltage monitoring circuits that help to protect the operating program against voltage disturbances.

7.3.2.1 4-5 Vdc Regulator Circuit - The +5 Vdc regulator circuit is shown in Figure 7-1 6. Except for the component designations and the position of the circuit breaker, the circuit is identical to the 4-5 Vdc regulator circuit on
the G8016 board. Refer t o Paragraph 7.2.2.1 for a description of the circuit operation.

7.3.2.2 -5 Vdc Regulator Circuit - Figure 7-1 7 illustrates the -5 Vdc regulator circuit. The circuit is a simple
series regulator incorporating an operational amplifier in the voltage feedback path. The inverting input of the operational amplifier, E5, is connected to a voltage divider comprising precision resistors R32, R33, and R34. If the -5
Vdc output tends to vary relative to the + 5 Vdc supply voltage, the operational amplifier output causes transistor
Q20 to draw more or less base current from the pass transistor, Q8; thus, the pass transistor acts to force the output back to its equilibrium value.
The -5 Vdc circuit has no adjustment. The potentiometer in the 4-5 Vdc regulator circuit permits both supplies to be
adjusted at the same time, the -5 Vdc output tracking the + 5 Vdc output.

7.3.2.3 4-20 Vdc Regulator Circuit - Figure 7-1 8 shows the 4-20 Vdc regulator circuit. A precision voltage regulator, E l , provides series regulation of the output voltage. E l consists of a temperature-compensated reference amplifier, an error amplifier, a power series pass transistor, and current-limit circuitry. Pass transistor Q6 is included in the
circuit t o handle the current that exceeds the 1 5 0 mA capability of E l .
The 4-20 Vdc output is sampled by the voltage adjustment potentiometer, R22, and compared to the internally-generated reference voltage by E l . Any error voltage produced because of a change in the sampled output is amplified
and applied to the internal pass transistor, which controls the base current of Q6. Thus, Q6 varies its degree of conduction t o maintain the output voltage at a constant value.
The power resistor, R20, is connected to the current-limit circuitry of E l to protect the internal pass transistor if the
regulator output terminals are shorted. Zener diode D l 2 shorts the regulator input to ground, causing F1 to burn out,
if the output voltage rises above approximately 2 2 Vdc.

t 5 VDC

t5v
GND

Figure 7 - 1 7

~0~~
AT1,AUl

BAl,BA2

4F A
1

: S ;
1

- 5 Vdc Regulator Circuit

-t 2 0 VDC @ 4 ~

= =

I
!

L-A

$ -10
"out

723

N.1.

CL,

cs,Nv -

BDI,
BEl-BHl,
B J l ,BJ2

t 5 V GND

Figure 7 - 18

+20 Vdc Regulator Circuit

7.3.2.4 & I 5 Vdc Circuit - The 15 Vdc output?; are unregulated and are derived from a bridge rectifier, D 16, illustrated in Figure 7-19. After being filtered, each voltage is referenced to 4-5 Vdc ground before being applied to
the connector block assembly.

7.3.2.5 POWER OK H Circuit The POWER OK H circuit (Figure 7-20) monitors the dc voltages, negating the
POWER OK H s'ignal whenever one or more voltages falls below a minimum value. When all dc voltages are at a
satisfactory level, transistor Q16 conducts and LED D25 is illuminated. If a voltage deteriorates, 0 1 5 turns on heavily, negating POWER OK H and turning off 0 1 6 .

ALl ,ALZ
I --

t15 VDC @ 2 A

AMl,AM2
ANl-ARl

t5V GND

Figure 7-1 9

* 15 Vdc Circuit

t 5 VDC

r 7

Figure 7-2!0

POWER OK H Circuit

If the
5 Vdc regulated voltage goes out of regulation, the collector of Q4 drops much more rapidly than does the
+5 V output itself. Thus, the collector voltage of Q4 is monitored directly to provide faster response when the 4-5
Vdc output decreases. In such a situation, Q15 is turned on via a path that includes transistors Q9, 010, and 014.
The 4-20 Vdc output is monitored at the base of transistor 0 7 . When the base voltage drops because of a decrease
in the +20 Vdc output, Q7 turns off, resulting i n 0 1 5 turning on and negating POWER OK H.
The +15 Vdc output is measured at the base of 012. If the +15 Vdc voltage goes low, 012 turns on, again resulting in Q15 turning on the POWER OK H signal near ground. The -15 Vdc output is monitored to bring indirectly.
Since -1 5 Vdc is used by the voltage regulator integrated circuit in the -5 Vdc regulator circuit (Figure 7-17), a drop
in the -1 5 Vdc output will affect the -5 Vdc output in the same way. Thus, Q13 turns on, resulting in POWER OK
H being negated.

7.3.2.6 AC LOW L Circuit The AC LOW L circuit is shown in Figure 7-21. The circuit asserts the AC LOW L
signal in three situations: The ac line voltage drops below a predetermined value; the ON/OFF switch is turned t o
OFF, or the POWER REQUEST signal is negated; a dc voltage falls below a specified level. The AC LOW L signal is
used in option board 2 to generate a program interrupt request and t o initiate automatic program re-start when ac
power is restored aftera failure.
The AC LEVEL signal (Figure 7-21) is proportional to the ac line voltage. The signal is applied through potentiometer
R49 to the inverting input of an operational amplifier whose non-inverting input is held at a reference level by Zener
diode D27. When pin 2 of E2 goes below the level of pin 3, output pin 6 goes positive. The situation is represented
in Figure 7-22.

AC LEVEL
(AV2)

tsv

---

R53

'u P'

AC OFF%
(AU2)

&
+ 5 V GND

NOTE:
Wl:6OHz
W2: 5OHz
E2:OP AMP 7 2 7 4 1

Figure 7-21

BATTERY OFF L
POWER OK H

AC LOW L Circuit

---------- 1
LIMITED FUNCTION PANEL

1
1 BA8-C POWER

DISTRIBUTION BOARD

POWER
REQUEST

LINE
LEVEL

BAT
AC
CONSOLE TERY BATTERY
OFF L POWER
OFF L CHARGING

9 ) I

INTERLOCK A N D
T R I AC
CONTROL

H9195 OMNIBUS

THERMOSTAT

^
RECTIFIER

1 TRANSFORMER

I ASSEMBLY

I l l
I l l

1 1 1

I l l

I
I

J
I

MOTE
Connections are snown 101
nections are not illustrated.

taw,

o w r.1 oparoiiui.*

.,aas

Figure 7-23

I n t e r c o n n e c t i o n s , 8A420/620/820
Oasic F'u~vo~AssGE~?~;

7.4.2 Interlock and Triac Control Circuit
Figure 7 - 2 4 shows the interlock scheme and illustrates the Triac control circuit. The Triac, D4, is in series with the LINE
connection of the power transformer primary. The gate of the Triac (connected t o TB2) is controlled by the Darlingtonamplifier pair Q1/Q2. Q2 is an opto-coupled isolator that is turned on when the Peak Detector circuit generates the PEAK
DETECTED H signal. This signal is generated when the input voltage is near its peak value; because there is a 90Â phase
difference between voltage and current in the power transformer ferro-resonant core, the peak value of voltage corresponds t o the 0-value of current. Thus, PEAK DETECTED H is generated when the inrush current is near its minimum
value. The diode portion of Q2 conducts, provided both G8018 boards, the fan harness, and the Limited Function Panel
are in place. The transistor portion of Q2 is turned on by the emission from the diode; Q1 turns on, supplying gate current
for the Triac, which conducts and, hence, connects the LINE t o one side of the power transformer.
7.4.3 Line Level Transformer and Peak Detector
Figure 7-25 shows the Line Level transformer and the Peak Detector circuit. The line voltage is rectified to produce the
LINE LEVEL signal. This signal is filtered and divided to produce a reference voltage at the base of Q4D. The non-filtered
LINE LEVEL signal is applied t o the base of Q4C. When the base of Q4C rises above the reference voltage, Q4C conducts,
providing base current for Q5. When Q5 turns on, PEAK DETECTED H is asserted and the Triac control circuit connects
the ac line to the power transformer,
If the ON/OFF switch on the Limited Function Panel is moved t o the OFF position, AC OFF L is asserted, turning off Q4C;
thus, PEAK DETECTED H is negated. The Triac stops conducting and line voltage is removed from the power transformer.
If the Emergency Shutdown circuit (Paragraph 7.4.4) should activate, transistor Q7 turns o n and current flows in the relay
coil. Hence, Q4A and Q6 turn on, removing the emitter-base forward bias' from Q5; Q5 turns off, negating PEAK
DETECTED H.

7.4.4 Thermistor/Thermostat and Emergency Shutdown
The circuits shown in Figure 7 - 2 6 produce an emergency shutdown of power when excessive heat is detected. Transistor
Q4B is turned on if the thermostat on either or both G8018 boards activates or if one or more of the thermistors in the
fan assembly overheats. Then, Q7 turns on and current passes through the coil of relay K1; the relay contact closure
causes the EMERGENCY SHUTDOWN L signal t o be generated.
As Figure 7 - 2 6 indicates, there are three thermistors in the fan assembly. They are mounted so that each receives cooling
air from one of the fans. If the fans are providing a sufficient flow of air, the temperature of each thermistor is of such a
value that Vth is less than Vref. Thus, the output (at pin 2, pin 1, and pin 14) of each comparator of E l is connected to
ground and Q4B does not conduct (assuming that each thermostat remains inactive).
However, if the flow of air from one (or more) of the fans stops, the temperature of the thermistor associated with the fan
rises. As the temperature increases, the thermistor resistance decreases and Vth increases. If Vth becomes greater than
Vref, the related comparator output goes high (the comparator output is an open-collector transistor); hence, the base of
Q4B is pulled up toward the level of the POWER OK H signal, Q4B conducts, and EMERGENCY SHUTDOWN L is
generated.
When the EMERGENCY SHUTDOWN L signal is asserted, the Triac is turned off and the ac line is disconnected from the
primary of the power transformer (EMERGENCY SHUTDOWN L also notifies the remote power control location of the
shutdown). However, the 4- 12 Vdc voltage is still present; consequently, Q4B and Q7 remain on (Q4B is latched on by
the voltage at the cathode of diode D2). Q4B and Q7 can be unlatched only if the ON/OFF switch o n the Limited
Function Panel is moved to the OFF position. This action generates the BATTERY OFF L signal, which causes output pin
13 of comparator E l t o be grounded. The ground o n the base of Q4B turns Q4B and, in turn, Q7 off. Thus, the relay
opens. When the cause of the shutdown is corrected and the ON/OFF switch is returned t o the ON position, pin 1 3 of E l
goes high and the circuitry once again monitors the thermostats and thermistors.

INTERLOCK

--1

0 TOP G8018

[

HARNESS

1--

12
*

1
I
_1

[FUNCTION PANEL[
16

1
08-1810

Figure 7-24

Interlock and Triac Control Circuit

EMERGENCY
SHUTDOWN L

Figure 7-25

Line Level Transformer/Peak Detector

UPPER
FRONT
FAN

LOWER
FRONT
FAN

LOWER
REAR
FAN

P / 0 FAN
HARNESS

EMERGENCY

16
0
BATTERY OFF L

Figure 7-26

Thermistor/Thermostat and Emergency Shutdown

7.4.6 POWER OK H Circuit
The logic illustrated in Figure 7-27 monitors the POWER OK H signal generated on each G8018 regulator board. If both
of these signals are high, the Omnibus POWER OK H signal is asserted, and the POWER 0 K light on the Limited Function
Panel is lit. However, when either regulator board's POWER OK H signal is low, Omnibus POWER OK H will be taken to
ground by transistor Q8B or Q8D; in addition, transistor Q3 will conduct and the POWER OK light will turn off.

IÃ‘
7

POWER OK H
OMNIBUS BV2

- - _1

POWEROKH
B
v
*

(P7o BOTTOM
I~*O'*

BV2

POWEROKH

1 RUN 1

4%;

POWER OK LIGHT

P / 0 LIMITED
NOTE:
The BA8-C can be used to expand a PDP8-E computer. Jumper
W 1 must be removed for such expansion. Refer to the 8A-Family Expansion Guide for particulars.

Figure 7-27

POWER OK Circuit

CHAPTER 8
MAINTENANCE A N D TROUBLESHOOTING

This chapter contains pertinent information about preventive maintenance, PDP-8/A troubleshooting techniques, and
removal and replacement of modules.

CAUTION
ICs and individual components should not be replaced
at the user's installation. Modules should be returned
to DIGITAL for repair. Replacement of ICs and components on etched circuit boards require special equipment available at DIGITAL repair depots and at the
factory.
8.1 MAINTENANCE AND TROUBLESHOOTING REQUIREMENTS
To maintain and troubleshoot the PDP-8/A, the user must obtain the necessary diagnostic programs and test
equipment.
8.1.1 Diagnostic Programs
Diagnostics and supporting documentation are available from DIGITAL'S Software Distribution Center. The PDP-8
Software Price List may be obtained by writing:
Digital Equipment Corporation
Software Distribution Center
1 4 6 Main Street
Maynard, Massachusetts 0 1754.
The price list also explains h o w to order.
The following software kits are available for testing the PDP-8/A:
PDP-8/A 4K Basic Software Kit (ZF006-RB)
MAINDEC-08-DJKKA-PB
MAINDEC-08-DJKKA-D
MAIN DEC-08-DJMSA-PB
MAINDEC-08-DJMSA-D
MAINDEC-08-DJEXB-PB
MAINDEC-08-DJEXB-D
MAIN DEC-08-DJM MA-PB
MAINDEC-08-DJM MA-D

PDP-8/A CPU Test
PDP-8/A CPU Test Instructions
1-4K MS8-A MOS Memory Test
1-4K MS8-A MOS Memory Test Instructions
2-32K Processor Exerciser
2-32K Processor Exerciser Instructions
4-32K Memory Test
4-32K Memory Test Instructions

PDP-8/A 1 K and 2K Basic Software Kit (ZF007-RB)
MAINDEC-08-DJKKA-PM 1
MAINDEC-08-DJKKA-D
MAINDEC-08-DJMSA-PM
MAINDEC-08-DJM SA-D
MAIN DEC-08-DJEXA-PM
MAINDEC-08-DJEXA-D

PDP-8/A CPU Test
PDP-8/A CPU Test Instructions
1-4K MS8-A MOS Memory Test
1-4K MS8-A MOS Memory Test Instructions
1-32K Random Memory Reference Instructions
1-32K Random Memory Reference Instructions
Exerciser Instructions
2-32K Processor Exerciser
2-32K Processor Exerciser Instructions

1 K and 2K DKC8-AA Option Software Kit (ZF207-RBI
DKC8-AA Option Test 1
DKC8-AA Option Test 2
DKC8-AA Option Test 3
DKC8-AA Option Test 4
DKC8-AA Option Test Instructions
4K DKC8-AA Option Software Kit (ZF208-RB)
MAINDEC-08-DJDKA-PB1
MAIN DEC-08-DJDKA-D

DKC8-AA Option Test
D KC?-AA Option Test Instructions

4K KM8-A Option Software Kit (ZF209-RBI
MAINDEC-08-DJKMA-PB1
MAIN DEC-08-DJKMA-D

KM8-A Option Test
KM8-A Option Test Instructions

1 K, 2K KM8-A Option Software Kit (ZF210-RB)
MAINDEC-08-DJKMA-PM 1
MAIN DEC-08-DJKMA-PM2
MAINDEC-08-DJKMA-PM4
MAIN DEC-08-DJKMA-D

KM8A Option Test 1
KM8A Option Test 2
KM8A Option Test 3
KM8A Option Test Instructions

MR8-A ROM Software Kit (ZF211-RB)
MAINDEC-08-DJM RA-PM
MAINDEC-08-DJMRA-D

M R8-A ROM Compare Test
M R8-A ROM Compare Test Instructions

M R8-SA ROM Loader Software Kit (ZF204-RM)
MAINDEC-08-DJM RA-PB
MAIN DEC-08-DJM RA-D
MAINDEC-08-DJMRB-PB
MAINDEC-08-DJM RB-D

MR8-A ROM Compare Test
MR8-A ROM Compare Test Instructions
MR8-SA PROM Loader Program
M R8-SA PROM Loader Program Instructions

MR8-FB 1K Software Kit (ZF196-RBI
MR8-FB PROM Compare Test
MR8-FB PROM Compare Test Instructions
1 K MR8-FB PROM Internal Test
1 K MR8-FB PROM Internal Test Instructions

T h e kits should be ordered by the kit number (i.e., ZF196-RB is the kit number for the 1 K MR8-FB PROM.)
The information required to run the PDP-8/A diagnostics is provided in Chapter 2.
8.1.2
Equipment
Table 8-1 lists the equipment needed to run PDP-8/A diagnostics and test.

Table 8-1
Maintenance Equipment
Equipment
Multimeter
~ u m p e Wire
r
.
Cable
Quad Module
Extender (1)

Specifications

Equivalent
Triplett Model 310
30-gauge with Termi Point Connections
BC08R-1
W987

8.2 PREVENTIVE MAINTENANCE INSPECTIONS
This paragraph provides information for performing preventive maintenance inspections. This information consists of
visual, static, and dynamic tests that provide better equipment reliability. Preventive maintenance consists of procedures that are performed prior to the initial operation of the computer and periodically during its operating life.
These procedures include visual inspections, cleaning, and operational testing. A log should be kept to record specific
data that indicates the performance history and rate of deterioration; such a record can be used to determine the
need and time for performing corrective maintenance on the system.
Scheduling of computer usage should always include specific time intervals that are set aside for scheduled maintenance purposes. Careful diagnostic testing programs can then reveal problems that may only occur intermittently during on-line operation.

Scheduled Maintenance
8.2.1
The PDP-8/A must receive certain routine maintenance attention to ensure maximum life and reliability. Digital
Equipment Corporation suggests the maintenance defined in Table 8-2.
The Importance of a Preventive Maintenance Schedule
8.2.2
Computer downtime can be minimized by rigid adherence to a preventive maintenance schedule. A dirty air filter can
cause machine failure through overheating. All filters should be cleaned periodically. The procedure for filter cleaning
is described in Table 8-2.
8.3 PDP-8/A TROUBLESHOOTING
The PDP-8/A is constructed of highly reliable 1C logic modules. Use of these circuits and a minimum amount of preventive maintenance ensures relatively little equipment downtime due to failure. If a malfunction occurs, users should
analyze the condition and correct it by replacing the defective module.
Switches on modules that are used to replace another module should be set to correspond to the settings on the
module that was removed. Chapter 2 lists the switch settings for all PDP-8/A modules.
8.3.1
Operator Errors
Operator errors are the cause of many computer malfunctions. When it has been determined that a module is malfunctioning, it is a good idea to check the switch positions on the module before replacing the module. Chapter 2 lists all the
switch settings for the PDP-8/A modules and Table 2-1 6 lists basic symptoms and the corrective action required.

Table 8-2
Preventive Maintenance
(3 Months or 500 Hours)
Action
Clean

Clean the exterior and interior of the computer cabinet, using a vacuum cleaner and/or clean cloths
moistened in nonflammable solvent.
Clean the air filter. Use a vacuum cleaner to remove accumulated dirt and dust, or wash with clean hot
water and thoroughly dry before using.

Inspect

Visually inspect equipmentfor general condition. Repaint any scratched areas.
Inspect all wiring and cables for cuts, breaks, fraying, wear, deterioration, kinks, strains, and
mechanical security. Tape or replace any defective cable.
Inspect the following for mechanical security: key switches, control knobs, lamps, connectors, transformers, fans, etc. Tighten or replace as required.
Inspect all module mounting panels t o ensure that each module is securely seated in its connector.
Remove and clean any module that may have collected excess dirt or dust.

Perform

Run the necessary diagnostic programs t o verify proper computer operation.
Perform all preventive maintenance operations for each peripheral device included in the PDP-8/A
System as directed in the individual maintenance instructions supplied with each peripheral device.
Enter preventive maintenance results in log book.

8.3.2 Troubleshooting Procedures
When a malfunction is detected, gather all information available from other users who have encountered the problem
and check the system log book for any previous reference to this problem. Make a note of indications on the Limited
Function Panel and Programmer's Console before attempting to locate the module that is malfunctioning. This information is helpful for describing the malfunction in the log book or to your DIGITAL representative before he or she
arrives on site.
Do not attempt to locate the defective module using complex software systems. Run the diagnostic programs following the procedures in Chapter 2 and select the simplest program that exhibits the error condition. Diagnostic programs are carefully written to include programs that assist the user when isolating the defective module.
For those modules connected to peripheral devices (i.e., DKC8-AA), disconnect the peripheral device if it is not necessary to run the diagnostic, and rerun the diagnostic.

8.3.3 Validation Tests
If a defective module is replaced by a new module, tag the defective module noting the nature of the failure.
To confirm that the new module resolved the problem, run all tests that originally exhibited the problem. If modules
have been moved during the troubleshooting period, return all modules to their original positions before running the
validation tests. Contact your DIGITAL field service office for the procedure required to repair your module.

8.3.4 Cable Problems
Malfunctions of modules that have cables connected to them, which are not corrected by replacing the modules,
may be caused by defective cables. If the validation tests are run and the replacement module has not corrected the
problem, it is a good idea to ensure that the cable is connected correctly. If the cable is connected correctly and the
problem persists, remove and replace the cables.

8.3.5 Log Entry
A log book should be kept for each PDP-8/A System. Maintenance operations are not complete until all activities
are recorded in the log book. Record all data indicating the symptoms given by the fault, the method of fault detection, the module at fault, and any comments that would be helpful to maintain the equipment in the future.
The log book should be maintained on a daily basis, recording all operator usage and preventive maintenance results.

8.3.6

Removal and Replacement of Modules
CAUTION
Power should be turned OFF before attempting to remove or install a module.

The Programmer's Console must be removed to gain access t o PDP-8/A modules. To remove the Programmer's Console, grasp the console and pull it toward you. Do not remove any screws. There should be a table available on
which to place the Programmer's Console when it is removed. If a table is not available, disconnect the two cables
that are connected to the M8316 module.
To remove modules, unlock the locking handles on each side of the module by pulling them toward you. Slowly slide
the module out of the cabinet, being careful not to change positions of switches on the module.
To replace a module, slide the module back into the slot from which it was removed and push the two locking handles back into the locked position.
To replace the Programmer's Console, reconnect the two cables to the M8316 module, line up the four latches with
the holes, and push the panel into place.

8.3.7 Removal and Replacement of Regulator Board
The G8016 or G8018 Regulator Boards must be removed to replace fuses or to replace the regulator board.
To gain access to the regulator board in the PDP-8/A Semiconductor chassis or in the 8A400/600/800 chassis, turn
power OFF and remove the Limited Function Panel by pulling it toward you. Disconnect the cable from the Limited
Function Panel. Lay the Limited Function Panel out of the way. Use a flat-blade screwdriver to loosen the two fasteners
holding the Regulator Board assembly. Pull the assembly toward you slowly, being careful not to damage connectors or
components.
To replace the assembly slide it slowly back into the chassis, push the connector into the regulator board slot, and tighten
the two fasteners. Reconnect the cable to the Limited Function Panel. Line up the four latches with the four holes and
push the Function Panel back into place.
The Regulator Board assemblies in the 8A420/620/820 chassis are in the rear. After turning off the power, remove the
rear cover by loosening the four fasteners that hold it to the frame. Each assembly is removed by loosening the two
fasteners that secure it to the chassis and pulling the assembly from the regulator board connectors.

8.3.8 Removal and Replacement of LEDs on the Limited Function Panel
To replace the LED indicators on the Limited Function Panel, remove the Limited Function Panel as described in
8.3.7. After the Limited Function Panel is removed, remove the four screws that hold the printed circuit board on the
Panel.
CAUTION
Soldering iron used to remove and replace LEDs
should not exceed 40 W and should be free of dirt and
burned resin.
Use a soldering iron and solder sucker to remove solder from pins of LED to be removed. Note the connection for
the thickest pin on the LED so that the new LED can be installed with the pins connected to the correct polarity of
voltage. Insert the new LED and solder the pins on the printed circuit board.

Replace the printed circuit board using the four screws to fasten it down.
Reconnect the Limited Function Panel cable and reinstall the Limited Function Panel.

8.3.9 Removal and Replacement of LEDs on the Programmer's Console
To remove LEDs on the Programmer's Console remove the Programmer's Console as explained in Paragraph 8.3.6.
The cables must be disconnected from the M8316 module.
To remove the LEDs for the DISP and ADDR displays, take out the screws holding the two boards and remove the
board. Remove the segmented display by grasping and pulling on it. Replace the segmented display with one that
has the same part identification. Then replace the board and fasten with the screws that were taken out when the
board was removed.
To remove the LED'S for the status indicators (RUN, STATUS, MD etc.), remove the top board and bottom board by
removing the screws that hold them. Remove the solder from the LED to be removed using a 4 0 W soldering iron
and solder sucker. Remove the LED and note the connection for the thickest lead on the LED. Install the new LED
with the thickest lead in the same hole on the circuit board that was occupied by the one removed. Solder the LED
lead to the circuit board. Replace the bottom board and the top board.
Connect the cable on the Programmer's Console to t h e M 8 3 1 6 module and reinstall the Programmer's Console.

8.4 POWER SUPPLY ADJUSTMENTS
A W987 Module Extender board and an insulated adjusting tool are required to adjust the G8016 and G8018 Power
Supply voltages.
8.4.1

G8016 Power Supply Adjustment

8.4.1.1 + 5 V Adjustment (G8016) - To adjust the 5 V on the G8016 Regulator Board, install the W987 Module
Extender in one of the Omnibus slots. Connect an accurate digital voltmeter between pin CA2 on the Module Extender
board and any convenient ground. Use an insulated adjusting tool to adjust the + 5 V supply adjustment (Figure 8-1) to
read 5 V on the meter. After the power supply is adjusted, remove the meter leads and the Module Extender board.
8.4.2

G8Ol8 Power Supply Adjustment

8.4.2.1 + 6 V Power Supply Adjustment - To adjust the + 5 V supply install the W987 Module Extender board in one
of the Omnibus slots. Connect an accurate digital voltmeter between pin CA2 on the Module Extender board and any
convenient ground. Use an insulated adjusting tool to adjust the 4-5 V supply adjustment (Figure 8-2)for 5 V. Remove
the meter leads and the Module Extender after the power supply is adjusted.
8.4.2.2 +20 V Power Supply Adjustment - To adjust the -I-20 V supply, install the W987 Module Extender board in
one of the core memory slots (Figure 3-1) with the D connector on the Module Extender in the E connector on the
Omnibus. Connect a voltmeter between DA2 of the Module Extender board and some convenient ground. Use an
insulated adjusting tool to adjust the i - 2 0 V (Figure 8-2) for 20.0 V. After the 4-20 V adjustemnt is made, remove the
meter and the Module Extender board.
8.5

POWER FAIWAUTO-RESTART LEVEL ADJUSTMENT (G8016 AND G8018)
NOTE
This is a factory adjustment and should not be performed
in the field.

A Variac is required to adjust the Power Fail/Auto-Restart levels. The two potentiometers (up and down) are factory
adjusted so AC LOW L is true when ac line drops below 9 5 Vac, and false when the ac line voltage goes above 105 Vac.

CIRCUIT
BREAKER

TOOL MUST
ENTER HERE
FOR +5V
ADJUSTMENT

POVI~EROK LIGHT
(LIT WHEN ALL DC
VOLTAGES ARE
PRESENT)

ADJUSTMENT
TOOL MUST
ENTER HERE
FOR +20 VOLT
ADJUSTMENT +20 V ADJUSTMENT

+5 v ADJUSTMENT

-5 V FUSE
(2.5 A)

Figure 8-2

POWER
FA1L
UP

POWER
FA1L
DOWN

+20 FUSE
(4 A)

G8Ol8 Regulator Board Adjustments

+15 v FUSE - 15 V FUSE
(2.5 A)
(2.5 A)
7404-1

8.6.1 G8018 Power Fail/Auto-Restart Adjustment
To adjust the two levels, turn power OFF and connect a Variac to the 8A. Connect the Variac to the power source and
turn 8A power ON. Install the module extender module in slot 2 or 3 of the Omnibus and monitor pin BB1. Adjust the
Variac for approximately 8 0 Vac output, and verify that AC LOW on pin BB1 is low (true). Slowly adjust the Variac
voltage toward 120 Vac; as the voltage reaches 105 Vac the AC LOW signal on BB1 should go high (i-4 V). Adjust the
UP potentiometer (Figure 8-2) until AC LOW makes a low to high transition at 105 Vac.
Now turn the Variac voltage down to 9 5 Vac and adjust the DOWN potentiometer so that AC LOW (pin BB1) makes a
high t o low transition at 9 5 Vac.

8.6.2 G8016 Power Fail/Auto-Restart Adjustment
To make the Power Fail/Auto-Restart adjustment on the G8016, turn power OFF and remove all modules. Remove the
G8016 module, insert a W987 Extender Module into the regulator slot and mount the G8016 regulator in the extender
module. Adjust the two levels using the same procedure as for the G8018 (Figure 8-1 shows the adjustment potentiometers). Remove the extender board and replace the regulator and all modules.
8.6 LINE VOLTAGE AND FREQUENCY COMBINATIONS
The PDP-8/A computers can operate with a line voltage of either 1 15 Vac or 2 3 0 Vac, and with a line frequency of either
5 0 Hz or 6 0 Hz. Table 8-3 lists the PDP-8/A computers and the part numbers of the line sets, fuses, and transformers
that must be used with each line voltage/frequency combination. The operating voltage and frequency of each computer
can be changed by replacing one line set/fuse/transformer combination with another. Specifics relating to each computer
are given in the following sections.
Table 8-3
PDP-81A Line Sets, Fuses, and Transformer Assemblies
I

Computer

P/N

PDP-8/A
Semiconductor

7010041-01

1 15 VacI4A

Line Set
Rated Operating
Voltage and Current

Fuse
PIN

Transformer Assembly -P/N
Rating

50 Hz

60 Hz

7010040, with frequency
jumper 7010042

8.6.1 8A400/600/800
The transformer assembly (50 Hz or 6 0 Hz) includes two Mate-N-Lok connectors, three Quick Disconnect connectors,
and one Ring Tongue terminal. For 1 15 Vac operation, plug transformer assembly connector P2 ( 12-pin) into J 16 of the
H9 1 9 4 Connector Block assembly (Figure 8-3); for 2 3 0 Vac operation plug P2 into J 17. For either voltage, plug P I (6pin) of the transformer assembly into J 19 of the Connector Block assembly. For either voltage, connect the blue/black
wire from the transformer assembly to the center lug (TB2) of the Connector Block assembly; attach the other two wires
terminated by Quick Disconnect connectors to TB1 and TB3, either wire to either lug (the wire attached to the solderless
connector is a ground connection).

8.6.2 8A420/620/820,
The transformer assembly (50 Hz or 6 0 Hz) includes a 12-pin Mate-N-Lok connector (PI), two Faston connectors, one
Ring Tongue terminal (a ground connection), and a cable assembly terminated by twelve Ring Tongue terminals. For 1 15
Vac operation, plug P I into J7 of the Power Distribution Board; for 230 Vac operation, plug P I into J8. For either
voltage, connect the two Faston connectors to the 12 microfarad, 660 V capacitor mounted above the transformer
assembly. For either voltage, connect the twelve Ring Tongue terminals on the cable assembly to J10 of the Power
Distribution board. Wire colors-pin numbers match as follows: Violet-12, violet-11, yellow- 10, yellow-9, yellow/black-8,
violet/black-7, blue-6, orange-5, blue/black-4, orange/black-3, blue-2, orange-1.
8.6.3 PDP-8/A Semiconductor
This computer uses the same transformer for either line frequency. For 1 15 Vac, plug P I of the transformer assembly into
J7 of the Power board (Figure 8-4); plug the frequency jumper into J 4 of the Power board for 60 Hz operation and into
J5 for 50 Hz operation. For 230 Vac, plug P I into J6 of the Power board; plug the frequency jumper into J 4 or J5, as
before. Attach the Faston connectors to TB1-TB5 of the Power board as indicated in Figure 8-4.

5 0 H Z CONNECTIONS

6 0 H Z CONNECTIONS

Figure 8-4

TB4

TB1

TB2

TB3

T55

50 Hz and 60 Hz Connections on 10 Slot Machines

CHAPTER 9
SPARE PARTS

A list of recommended spares for the POP-8/A is contained in Tables 9 - 1 (PDP-8/A Semiconductor) and 9 - 2 (8A).
Table 9-1
PDP-8/A Semiconductor Recommended Spare Parts
Designation
(if any)

Name

Part
Number
-

K K8-A
DKC8-AA
K M8 -AA
M S8 -A
MS8-A
M S8 -A
Regulator

Central Processor
I/O Option Module
Extended Option Module
1 K RAM ReadANrite Memory
2K RAM Read/Write Memory
4 K RAM ReadANrite Memory
Power Supply Regulator
Console Logic
Console Cable
Remote Console Cable
Cable Limited Function Console
2 A Slow Blow Fuse (230 V)
4 A Slow Blow Fuse (115 V)
3/8 A Slow Blow Fuse
Diode Array
Power Relay
Battery

p
p

Quantity

Table 9-2
8A Recommended Spare Parts
Part
Number

Designation
(if any)
Memory Extension and Time
Share Option
Central Processor

I10 Option Module
Extended Option Module

8K Core Memory
16K Core Memory
Power Supply Regulator
Console Cable
Remote Console Cable
Cable Limited Function Console
Console Logic
4 A Slow Blow Fuse
(230 V - H9300 Chassis Assembly)
8 A Slow Blow Fuse
(115 V - H9300 Chassis Assembly)

3/8A Slow Blow Fuse
(H9300 Chassis Assembly)
2.5 A Slow Blow Fuse (+I5 V, -1 5 V, -5 V)
(H9300 Chassis Assembly)
4 A Fuse (+20 V)
12 A Slow Blow Fuse
(115 V - BA8-C Chassis Assembly)
6 A Slow Blow Fuse
(230 V - BA8-C Chassis Assembly)
112 A Fuse (BA8-CChassis Assembly)
2.5 A Slow Blow Fuse (+I5 V, -1 5 V, -5 V)
(BA8-C Chassis Assembly)
Diode Array
Power Relay Assembly

Quantity

APPENDIX A
INSTRUCTION S U M M A R Y

CPU INSTRUCTION SUMMARY

Sequence
1
1
1
1
1
1
1
3
3
2

BASIC INSTRUCTIONS

logical AND
2's complement add
increment, and skip if zero
deposit and clear AC
jump to subroutine

2
2
2
2
1

jump
in/out transfer
operate

OPCODE 0-5

skip on minus AC
skip o n zero AC
skip o n plus AC
skip o n on-zero AC
skip on non-zero link
skip o n zero link
skip unconditionally
inclusive OR switch register with AC
halts the program
clear AC

SMA
SZA
SPA
SNA
SNL
sz L
SKP
0s R
H LT
CLA

Cycles
AND
TAD
ISZ
DCA
JMS
JMP
IOT
OPR

INTERNAL IOT MICROINSTRUCTIONS
PROGRAM INTERRUPT AND FLAG ( 1 CYCLE)

GROUP 2 OPERATE MICROINSTRUCTIONS (1 CYCLE)

CPU Instruction Summarv

ADDRESS

REVERSE SKIP SENSING OF BITS 5,6,7

INDIRECT ADDRESSING
0 = DIRECT
1 = INDIRECT (ADD: 1 CYCLE)
MEMORY PAGE
O=PAGEO
1 CURRENT PAGE

OSR

HLT

SKON
ION
IOF
SRQ
GTF
RTF

6000
6001
6002
6003
6004
6005

skip i f interrupt ON, and turn OFF
turn interrupt ON
turn interrunt OFF
skip on interrupt request
get interrupt flags
restore interrupt flags

CAF

6007

clear all flags

OPERATION

DEVICESELECTION

IOT Instruction Bit Assignments

Logical Sequences:
1 (Bit 8 is Zero) - Either SMA or SZA or SNL
1 (Bit 8 is One) - Both SPA and SNA and S i L
2
- CLA
OSR, HLT
3

Memory Reference Instruction Bit Assignments
Group 2 Operate Instruction Bit Assignments

GROUP 1OPERATE MICROINSTRUCTIONS (1 CYCLE)

Sequence
no operation
clear AC
clear link
complement AC
complement link
rotate AC and link right one
rotate AC and link left one
rotate AC and link right two
rotate AC and link left two
increment AC
swap bytes in AC

NOP
CLA
CLL
CMA
CML
PAR
RAL
RTR
RTL
IAC
BSW

CLA

CLL

CMA

CML

BSW

ROTATE AC AND L RIGHT A
ROTATE AC AND L LEFT
ROTATE 1 POSITION IF A 0. 2 POSITIONS IF A 1

MQ MICROINSTRUCTIONS (1 CYCLE)

COMBINED OPERATE MICROINSTRUCTIONS (1 CYCLE)

Logical Sequences
1 - CLA CLL
2 - CMA CML
3 - IAC
4 - RAR, RAL, RTR, RTL, BSW
Group 1 Operate Instruction Bit Assignments

IAC

CIA
LAS
ST L
GLK
C LA
CLL
CLL
CLL
CLL
SZA
SZA
SNA
SMA
SM A
SMA
SPA
SPA
SPA
SNA

CLL
RAR
RAL
RTL
RTR
CLA
SN L
CLA
CLA
SZA
SN L
SNA
sz L
CLA
SZL

complement and increment AC
load AC with switch register
set link ( t o 11
get Jink (put link in AC bit 11)
clear AC and link
shift positive number one right
shift positive number one left
clear link, rotate 2 left
clear link, rotate 2 right
skip if AC=0, then clear AC
skip if AC=0 or link is 1, or both
skip if AC#O, then clear AC
skip if AC<0, then clear AC
skip if AC<0
skip if AC<0 or link is 1, or both
skip if AC>O
skip if AC>O and the link is 0
skip if ACS'O, then clear AC
skip i f AC#O and link=O

no operation
clear AC
load MQ from AC then clear AC
inclusive OR the MQ with the AC
clear AC and MQ
swap AC and MQ
load MQ into AC
load AC from MQ then clear MQ

NOP
CLA
MQL
MQA
CAM
SWP
ACL
CLA SWP

7
MQL

Logical Sequence:
1-CLA
2-MQA, MQL
3-ALL OTHERS
MQ Microinstruction Bit Assignments

11
1

DKC8-AA IIO OPTION BOARD INSTRUCTIONS
Serial Line Unit IOT Instructions (1 Cycle)

Receive
KCF
KS F
KCC
KRS
KIE

KRB

6036

Clear Receive flag, do not set Reader Run.
Skip if Receive flag is set.
Clear Receive flag and AC, set Reader Run.
Read Receive Buffer.
Load AC11 into I nterrupt Enable.
Set interrupt Enable.
AC11 = 1.
Clear Interrupt Enable.
AC11 = 0.
Combined KCC & KRS.

Transmit

TF L
TSF
TCF
TPC
SP I

6040
604 1
6042
6044
6045

T LS

6046

Set Transmit Flag.
Skip if Transmit flag is set.
Clear Transmit flag.
Load AC4-AC11 into transmit buffer and transmit.
Skip if transmit or receive flag i s set and if interrupt
enable is set.
Combined TCF and TPC commands.

General-Purpose Parallel I/O Instructions (1 Cycle)

DBST

6570

Skip on Data Accepted, clear Data Accepted and
Data Available.

DBSK
DBRD
DBCF

6571
6572
6573

DBTD

6574

DBSE
DBCE
DBSS

6575
6576
6577

Skip on Data Ready flag.
Read Data In to ACO-AC1 1.
Clear Data Ready flag, issue Data Accepted Out
pulse.
Load ACO-AC1 1 into buffer and transmit Data
Out.
Set Interrupt Enable to a 1.
Reset Interrupt Enable to a 0.
Issue a Strobe pulse.

Real Time Crystal Clock Instructions (1 Cycle)

CLLE

6135

CLCL
CLSK

6136
6137

Load Interrupt Enable from AC11
AC11 = 1, set Interrupt Enable
AC11 = 0, clear Interrupt Enable
Clear Clock flag.
Skip if Clock flag = 1.

KM8-A EXTENDED OPTION BOARD INSTRUCTIONS
Memory Extention Time Share Control Instructions (1 Cycle)
GTF

6004

Jam Transfer the status of the flags and link into ACO,
AC2, and AC4-AC11.
( 0 = cleared, 1 = set)
ACO = Link
AC2 = Interrupt Request
AC4 = Interrupt Enable
AC5-11 = User Mode and Save Field

RTF

Transfer the contents of AC5, AC6-AC11 to the user
buffer flip-flop, the instruction buffer and data field, and
inhibit processor interrupts until the next JMP or JMS instruction. User Field flip-flop and the Instruction Field
are loaded at the conclusion of the next JMP or JMS
instruction. The CPU loads the contents of ACO into
the L.ink and enables the interrupt system in response
to this IOT.

CDF

Load the Data Field register with the program selected
number N (N = 0-7).

CI F

Load the Instruction Buffer with the program selected
number N (N = 0-7) and inhibit program interrupts
until the next JMP or JMS instruction.

CDF CIF

Load the Data Field and Instruction Buffer with program
selected number N (N = 0-7). Combines CDF and CI F.

RDF

OR'S the content of the Data Field register with AC6AC8.

RIF

OR'S the contents of the Instruction Field register with
AC6-AC8.

RIB

OR'S the contents of the Save Field with AC6-AC8
and AC9-AC11. The time share bit of the Save Field
is 0Red into AC5.

RMF

Restores the contents of the Save Field register into the
Instruction Buffer, Data Field, and (if time share is
enabled) user buffer.
Clear User Interrupt flip-flop.

Memory Extensionflime Share Control Instructions (1 Cycle) (Cont)
SI NT

6254

Skip if User Interrupt flip-flop is set.

CUF

6264

Clear User Buffer flip-flop (exit time share mode).

SUF

6274

Set User Buffer flip-flop (enter time share mode)
following next JMP or JMS instruction.

(1 Cycle)

Power Fail/Auto Restart

SP L

6102

Skip if AC Low flip-flop is set.

CAL

6103

Clear AC Low flip-flop.

SB E

6101

Skip if Battery Empty flip-flop is set.

PERIPHERAL AND OPTION INSTRUCTION SUMMARY
LE8-E Line Printer

Mnemonic
Symbol

Octal
Code

PSKF
PCLF
PSKE
PST B

6661
6662
6663
6664

PSIE
PCLF, PSTB
PCIE

6665
6666
6667

Operation
Skip on Character Flag
Clear the Character Flag
Skip on Error
Load Printer Buffer, Print on Full Buffer or
Control Character
Set Program Interrupt Flag
Clear Line Printer Flag, Load Character, and Print
Clear Program Interrupt Flag

XY8-E Incremental Plotter Control
Mnemonic
Symbol

Octal
Code

Operation
Clear Interrupt Enable
Skip o n Plotter Flag
Clear Plotter Flag
Pen U p
Load Direction Register, Set Flag
Pen D o w n
Clear Flag, Load Direction Register, Set Flag
Set Interrupt Enable

PLCE
PLSF
PLCF
PLPU
PLLR
PLPD
PLCF, PLLR
PLSE

VC8-E C R T Display Control
Mnemonic
Symbol

Octal
Code

Operation
Clears Enables, Flags and Delays
Clears Done Flag
Skip o n Done Flag
Load X Register
Load Y Register
Clear Done Flag; Intensify; Set Done Flag
Transfers A C t o Enable Register
Transfers Display EnableIStatus Register t o A C

D lLC
DICD
DISD
DILX
DILY
DIXY
D lLE
DIRE

BB08-P General Purpose Interface U n i t
Mnemonic
Symbol

Octal
Code

Operation

GTSF
GCTF

6361
6362
6564
6371
6372
6374

Skip o n Transmit Flag
Clear Transmit Flag
( User-Assigned)
Skip o n Receive Flag
Clear Receive Flag
Read Device Buffer

G RSF
GCRF
GRDB

DR8-EA 12-Channel Buffered Digital I10
Mnemonic
Symbol

Octal
Code

Operation
Disable Interrupt
Enable Interrupt
Skip o n Done Flag
Clear Selective Input Register
Transfer Input t o A C
Clear Selective Output Register
Set Selective O u t p u t Register
Transfer Output t o AC

DBDI
DBEI
DBSK
DBCI
DBRI
DBCO
DBSO
DBRO
5X is the Device Code.

DP8-E AIEB Synchronous Modem Interface
Mnemonic
Symbol

Octal
Code

SGTT
SG R R
SSCD
SCSD
SSRO
SCS I
SRTA
SLCC
SSRG
SSCA
SRS2
SRSI
SLF L
SSB E
SRCD

6405
6404
6400
6406
6402
6401
6407
6412
6410
641 1
6414
641 5
6413
6416
641 7

SSTO

6403

Operation
Transmit G o
Receive G o
Skip if Character Detected
Clear Sync Detect
Skip if Receive Word Count Overflow
Clear Synchronous Interface
Read Transfer Address Register
Load Control
Skip i f Ring Flag
Skip i f CarrierIAGC Flag
Read Status 2
Read Status 1
Load Field
Skip o n Bus Error
Read Character Detected ( i f ACO=O)
Maintenance Instruction ( if ACO=1)
Skip if Transmit Word Count Overflows

DK8-EP Programmable Real Time Clock
Mnemonic
Symbol

Octal
Code

Operation
Clear Clock Enable Register per A C
Skip o n Clock Interrupt
Set Clock Enable Register per A C
A C t o Clock Buffer
Load Clock Enable Register
Clock Status t o A C
Clock Buffer t o A C
Clock Counter t o A C

CLZE
CLSK
CLOE
CLAB
CLEN
C LSA
CLBA
CLCA

DK8-EC Crystal Clock
Mnemonic
Symbol

Octal
Code

CLEI
CLDI
CLSK

6131
6132
61 3 3

Operation
Enable Interrupt
Disablelnterrupt
Skip o n Clock Flag and Clear Flag

KG8-EA Redundancy Check Option
Mnemonic
Symbol

Octal
Code

RCTV
RCRL
RCRH
RCCV
RCGB
RCLC
RCCB

61 10
6112
6111
6113
61 14
61 15
61 1 6

Operation
Test VRC and Skip
Read BCC L o w
ReadBCCHigh
ComputeVRC
Generate BCC
Load Control
Clear BCC Accumulation

DB8-E Interprocessor Buffer
Mnemonic
Symbol

Octal
Code

Operation

DBRF

65x1

Skip if the receive set to a 1

DBRD

65x2

Read incoming data into the AC, clear receive
flag

DBTF

65x3

Skip if the transmit flag is set t o a 1

DBTD

65x4

Load the AC into the transmit buffer, transmit
and set the transmit flag

DBEI

65x5

Enable the Interrupt Request line

DBDI

65x6

Disable the Interrupt Request Line

DBCD

65x7

Clear done flag

5X is the Device Code.

KL8-JA Terminal ControlIAsynchronous Data Interface
Mnemonic
Symbol

Octal
Code

KCF
KSF
KCC
KRS
KI E

6030
6031
6032
6033
6035
(ACI 1)

KSE

6035
(AC 10)

KRB
TFL
TSF
TCV
TPC
SP I

6036
6040
604 1
6042
6043
6045

T LS

6046

Operation
Clear Receive Flag
Skip on Keyboard Flag
Clear Keyboard Flag and set Reader Run Flag
Read Keyboard Status
Set or clear Interrupt Enable
A C I I = 1 set
A C I I = 0 clear
SetKlear Status Enable
AC10 = 1 Enable Status
AC10 = 0 Disable Status
Read Keyboard Buffer Combined KCC and KRS
Set Transmit Flag
Skip on Transmit Flag
Clear Transmit Flag
Load Print Buffer and Print
Skip if Interrupt Enabled and Transmit or
Receive Flag is set
Print character. Combined TCF and TPC.

Mnemonic
Symbol

Octal
Code

RPE
RSF
RRB
RFC
RFC, RRB
PCE
PS F
PCF
PPC
PLS

Operation
Set ReaderIPunch Interrupt Enable
Skip o n Reader Flag
Read Reader Buffer
Reader Fetch Character
Read Buffer and Fetch New Character
Clear ReaderIPunch Interrupt Enable
Skip o n Punch Flag
Clear Punch Flag
Load Punch Buffer and Punch Character
Load Punch Buffer Sequence

RK8-E Control and R KO6 DECpack Drive
Mnemonic
Symbol

Octal
Code

DSKP
DCLR
DLAG
D LCA
DRST
DLDC
DMAN

67x1
67x2
67x3
67x4
67x5
67x6
67x7

7X is the Device Code.

Operation
Disk skip o n Flag
Disk Clear
Load Address and G o
Load Current Address
Read Status Register
Load Command Register
Maintenance Instructions

TM8-EIF Control
Mnemonic
Symbol

Octal
Code

LWCR
CWCR
LCAR
CCA R
LCM R
LFGR
LDBR
RWCR
CLT
RCAR
RMSR
RCMR
RFSR
RDBR
SKEF
SKCB
SKJD
SKTR
CLR

6701
6702
6703
6704
6705
6706
6707
671 1
6712
6713
6714
6715
6716
671 7
6721
6722
6723
6724
6725

Operation
Load Word Count Register
Clear Word Count Register
Load Current Address Register
Clear Current Address Register
Load Command Register
Load Function Register
Load Data Buffer Register
Read Word Count Register
Clear Transport
Read Current Address Register
Read Main Status Register
Read Command Register
Read Function Register & Status
Read Data Buffer
Skip if Error Flag
Skip i f N o t Busy
Skip if Job Done
Skip i f Tape Ready
Clear Controller and Master

TA8-E DECassette
Mnemonic
Symbol

Octal
Code

KCLR
KSD R
KSEN
KSBF
K LSA
KSA F
KGOA
KRSB
7X is the Device Code,

Operation
Clear Status Register A and B
Skip o n Data Flag
Skip o n EOTIBOT, EOF, o r Drive E m p t y
Skip o n Ready Flag
Load Status A f r o m the A C
Skip o n any flag o r error
Read Status A
Read Status B

APPENDIX B
OMNIBUS SIGNAL LOCATOR

This Appendix contains a list of PDP-8/A signals and their corresponding Omnibus pin numbers. Figure B-1 illustrates
these pin locations on the module.
Signal

MEM REFRESH (4-5 V)

-5 V
BREAK CYCLE L
BREAK DATA CONT L
BRK IN PROG L
BUS STROBE L
CO L
C1 L
C2 L
CPMA DISABLE L
D L
DATA0 L
DATA1 L
DATA2 L
DATA3 L
DATA4 L
DATA5 L
DATA6 L
DATA7 L
DATA8 L
DATA9 L
DATA1 0 L
DATA1 1 L

Signal

Omnibus Pin
EL
EMAO L
EMA1 L
EMA2 L
FL
FSET L
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND

Omnibus Pin

Signal
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
IND1 L
IND2 L
INHIBIT H
INITIALIZE H
INT I N PROG H
INT RQST L
INT STROBE H
INTERNAL I/O L
I/O PAUSE L
IRO L
IR1 L
IR2 L
KEY CONTROL L
LA ENABLE L
LINK DATA L
LINK L
LINK LOAD L
MA0 L
MA1 L
MA2 L
MA3 L
MA4 L
MA5 L
MA6 L
MA7 L
MA8 L
MA9 L
M A 10 L
MA1 1 L
MA, M S LOAD CONT L
MDO L
MD1 L
MD2 L
MD3 L
MD4 L
MD5 L
MD6 L
MD7 L
MD8 L
MD9 L

Omnibus Pin

Signal
MD10 L
MD11 L
M D DIR L
M E M START L
MS, IR DISABLE L
NOT LAST XFER L
NTS STALL L
OVERFLOW L
POWER OK H
PULSE LA H
RES
RETURN H
ROM ADDRESS L
RUN L
SKIP L
SOURCE H
STOP L
STROBE H

sw
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TEST POINT
TP1 H
TP2 H
TP3 H
TP4 H
TS1 L
TS2 L
TS3 L
TS4 L
USER MODE L
WRITE H

Omnibus Pin

CONNECTOR, SIDE

PIN
E1

Notes
1. This pin is connected t o ground on the
bus but serves as a logic signal within
modules for testing.
2.

Pins A A 1 and C A I i n slot 1supply
-5 V t o the CPU module.

Pin BA1 of slots 2 and 3 supplies
BATTERY EMPTY t o the option
modules.

Pin BB1 of slots 2 and 3 supplies AC
LOW t o the option modules.

DA1 of slots 2 and 3 supplies PANEL
LOCK t o the option modules.

+20V

T P NOTE 5

+15V

TP NOTE 2

+ 5V

TP NOTE 3

+ 5V

TP NOTE 2

N O T USED

- 15V

- 15

T P NOTE 4

- 15V

GND

SP GND NOTE 1

GND

NOT USED

MA8L

IROL

I / O PAUSE L

TP1 H

MA4L

INT STROBE H

MA0 L

â‚¬M L

+20V

MA9 L

IRIL

CO L

TP2 H

MA5 L

BRK IN PROG L

MA1 L

EMA IL

GND

+5V

MEM REFRESH (+5V)

MA10 L

IR2 L

C1 L

TP3 H

MA6 L

MA,MS LOAD CONT L

MA2L

EMA2 L

MEM REFRESH (+5V)

MA 11L

C2 L

TP4H

MA7 L

OVERFLOW L

MA3 L

M E M START L

+2 0 V

MD8 L

BUS STROBE L

TS1 L

MD4 L

BREAK DATACONTL

MDO L

MD DIR L

NOT USED

MD9 L

INTERNAL I / O L

T S2 L

MD5 L

BREAK CYCLE L

MD1 L

SOURCE H

-5V

MD 10 L

USER MODE L

NOT LAST XFER L

TS3 L

MD6 L

L A ENABLE L

MD2 L

STROBE H

GND

6ND

GND

+20 V

MD11 L

F SET L

I N T ROST L

TS4 L

MD7 L

I N T IN PROG H

MD3 L

INHIBIT H

NOT USED

DATA 8 L

PULSE L A H

INITIALIZE H

L I N K DATA L

DATA 4 L

NTS S T A L L L

DATA 0 L

RETURN H

NOT USED

DATA 9 L

STOP L

SKIP L

LINK LOAD L

DATA 5 L

RES H

DATA 1 L

WRITE H

JUMPER 1

GND

GN D

GND

JUMPER 1

N O T USED

DATA 1 0 L

KEY CONTROL L

CPMA DISABLE L

IND 1 L

DATA 6 L

RUN L

DATA 2 L

ROM ADDRESS L

NOT USED

DATA 11 L

MS,IR DISABLE L

IND2 L

DATA 7 L

POWER OK H

DATA 3 L

LINK L

HEX MODULE

(COMPONENT SIDE

~2
CONNECTOR F
NOT CONNECTED
TO THE OMNIBUS

SI D E 1

)

‚ ¬
CONNECTOR E
SIDE 2

~ 2 -

HAVE 4 CONNECTORS

Figure B-1

Omnibus Signal Locator

6-3

APPENDIX C
MODULE ASSIGNMENT AND
POWER REQUIREMENTS

Option

Description

Board
Size

Card RD R Cont
Card RDR Cont
Interproc Buffer
RTC Crystal
RTC Prog
Option 1
Modem Interface
Digital I10
Positive I10
Prog Console
Data Break
Redundancy Check
CPU
Async Data Chart
Modem Control
Option 2
Mem Ext and TS Cont
Line Printer Cont
Line Printer Cont
8K Core, Operating
8K Core, Standby
16K Core, Operating
16K Core, Standby
1K ROM
2K ROM
3K ROM
4K ROM
1K PROM
1K RAM
2K RAM
3K RAM
4K RAM

Quad
Quad
Quad
Quad
Quad
Hex
Quad
Quad
Quad
Pnl Mt
Quad
Quad
Hex
Quad
Quad
Hex
Quad
Quad
Quad
Hex
Hex
Hex
Hex
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad

Slots
Used

Assigned
Slot No.

Curren

+I5 V

0.06 A
0.05 A

0.05 A
0.04 A

Option

Description
RDRIPunch Control
RX01 Control
RKO5 Control
TU60 Control
TU10 Control
Display Control
Display Control
Plotter Control
M8300, Major Reg
M8310, Major Reg Cont
M8330, Timing Gen
M8320, Bus Load
AID Conv
Floating Point
M8340, EAE IR
M8341, EAE Reg
MSLU
LA180 Cont
Boot Loader
RK05 Cont
TU56 Cont
TUI 0 Cont
Video Display Cont

Board
Size
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Hex

Hex
Quad
Quad
Quad
Quad
Quad
Hex

Slots
Used

Assigned
Slot No.

Current

+I5 V

0.09 A
0.01 A

1.0 A

0.09 A

APPENDIX D
PROGRAM LOADING PROCEDURES

INTRODUCTION
This appendix provides the user with procedures to accomplish the following:
1.

Turn the system on.

Load the Read In Mode (RIM) program. RIM must be in memory to load tapes from the high or low
speed paper-tape readers.

Load the Binary (BIN) loader - The Binary loader is a program that is used t o load the programs
punched in BIN format on paper tapes into memory.

Load BIN paper tapes using the Binary loader.

NOTE
R I M and BIN paper-tape formats are discussed in
Chapter 4 of the Introduction to Programming
Handbook.
D.1 TURNING THE SYSTEM ON
Before using the computer system, i t is good practice t o initialize all units. Ensure that all switches and controls are
as specified below:
1.

Main power cord is properly plugged in.

Teletype is turned to ON-LINE.

Low-speed punch is OFF.

Low-speed reader is set t o FREE.

Computer POWER ON

Console LOCK OFF (set t o down).

Ensure any peripherals supplied with the system are turned on. Refer to the maintenance manual supplied with the equipment for the startup procedures.

The system is now initialized and ready for use.

D.2 READ-IN MODE ( R I M ) LOADER
The RIM Loader is the very first program loaded into the computer; it is loaded by using the console switches or the
BOOT switch. Operating the BOOT switch causes a RIM program, contained in a ROM ON on the extend option
module to be deposited in memory. The RIM loader instructs the computer to receive and store in memory, data
punched on paper tape in RIM coded format. (The RIM Loader is used to load the BIN loader described in the next
paragraph.)

There are two RIM loader programs: one is used when the input is to be from the low-speed Teletype reader, and
the other is used when input is to be from the high-speed paper-tape reader. The locations and corresponding instructions for both loaders are listed in Table D-1.

Table D-1
R I M Loader Programs
--

Instruction

Location
Low-Speed Reader

High-speed Reader

The procedure for loading (keypadding) the RIM loader into memory using the Programmer's Console is as follows:
NOTE
On systems with an extended option module selected
for paper tape bootstrap, the user can press BOOT on
the Programmer's Console twice and the R I M program
is loaded automatically. Then go on to the procedure
to load the BINARY loader.

Press MD and then DISP to display the contents of the M D in the four character octal readout.
Enter the field that RIM is to be loaded into twice (i.e., if field 7 is being used, enter 77). Press LXA
(load extended address).
Enter 7756 and then press LOAD ADDRESS (LA) to load the starting address.
Enter the first instruction from Table D- 1 for the low-speed reader or high-speed reader, and press D NEXT.

Enter the remaining instructions from Table D-1; press D NEXT after each entry.
After all of the instructions have been entered, enter the starting address 7756 and press LA.
Check the entries you have made in the first 5 steps. To examine the first location, enter 7756 and then press
E NEXT. The numbers displayed in the four character octal readout should correspond to the first number
entered from Table D-1.
Press E NEXT and the second number from Table D-1 will be displayed. Check each instruction by observing
the number. If any errors are found, enter the address and press LA and the correct number using the keypad
switches and then press D NEXT.
After RIM has been loaded and checked, follow the instructions for loading the binary loader.

D.3 BINARY (BIN) LOADER
The BIN loader is a short utility program which instructs the computer to read binary coded data punched on paper
tape and store it in memory. BIN is used primarily to load the programs furnished in the software package (excluding
the loaders and certain subroutines) and the programmer's binary tapes.
BIN is furnished to the programmer on punched paper tape in RIM coded format. Therefore, RIM must be in memory before BIN can be loaded. The procedure for loading the binary loader is as follows:
Press M D and then DISP to display the contents M D lines in the four character octal readout
Enter the memory field into which RIM was loaded followed by the field into which BIN is to be loaded,
and then press LXA.
Enter 7756 and press LA. 7756 is the starting address of the RIM Loader program.

NOTE
Systems with high-speed readers perform steps 4 and
5; systems with. low-speed readers perform steps 6
and 7.
Turn high-speed reader on.
Put the Binary loader tape in the right hand side of high-speed reader with the printed arrows up and
pointing to the left (proceed to step 8).
Set the TTY to LINE.
Put the Binary loader tape in the low-speed reader with the printed arrows up and pointing toward you.
Set the low-speed reader lever to START.
Press INIT and RUN. The tape should read in. If the tape does not read in, go back to step 1 to be certain an operator error was not the reason the tape did not read in.
If the tape reads in, press HLT/SS when trailer (single row of holes) passes under the read head.
Enter the field the Binary loader was loaded into and press LXA,
1 1.

Enter 7777 and press LA.

12.

Press E THIS.

13.

The M D should read 5301. If it does not, go back to step 1 and repeat the procedure.

When stored in memory, BIN resides on the last page of core occupying absolute locations 7625 through 7752 and
location 7777.
BIN was purposely placed on the last page of core so that it would always be available; most of the programs in
DIGITAL'S software package do not use the last page of memory. The programmer must be aware that if he or she
writes a program that uses the last page of memory, BIN will be overwritten when the program runs on the computer. When this happens, the programmer must load RIM and then BIN before loading binary tape.

D.4 LOADING BINARY TAPES
The procedure for loading binary tapes is as follows:
Verify that the BINARY loader has been loaded.
Press AC and then DISP.
Enter the field into which the BINARY loader was loaded, and then enter the field into which binary tape
is to be loaded. Press LXA.
Enter 7777 and press LA.

NOTE
Perform steps 5 and 6 for low-speed readers and steps
8, 9, and 10 for high-speed readers.
Turn TTY to line and put the tape in the low-speed reader, ensuring that the leader (code 200) is in the
reader. The tape moves from back to front; the printed arrows on the tape should be up and pointing toward you.
Enter 7777 and press LSR.
Set low-speed reader to START. Proceed to step 11.
Turn high-speed reader on.
Enter 3777 and press LSR.
Put the tape in the high-speed reader, ensuring the leader (code 200) is in the reader. The tape moves
from right to left; the printed arrows on the tape should be up and pointing left.
Press AC and then DISP.
Press INIT and then RUN.
The tape should read in and stop at the first trailer code (not the physical end of tape), with the AC
equal to 0000. In case of difficulty, go back to step 1. Problems with reader motion are usually caused
by not loading the BIN loader correctly. Checksum errors (AC not equal to 0 ) are often the result of worn
tapes.

APPENDIX E
ASCII1 CHARACTER CODES
Character

8-Bit
Octal

6-Bit
Octal

'An abbreviation for American Standard Code for Information Interchange.

Decimal
Equivalent
(All Format)

Character

8-Bit
Octal

241
242
243
244
245
246
247
250
251
252
253
254
255
256
257
272
273
274
275
276
277
300
333
334
335
336
337
200
2 12
215
240
377
000
207
21 1
2 14

#
$

%
&
(
)
Â

+
/

>
?

@
[

I
?(TI2
<(-I2
LeadedTrailer
LINE FEED
Carriage RETURN
SPACE
RUBOUT
Blank
BELL
TAB
FORM

2The character in parenthesis is printed on some teletypes.

6-Bit
Octal

Decimal
Equivalent
(All Format)

APPENDIX F
DEVICE CODES

The device codes for PDP-8/A options and peripherals are listed in Table F-1.
Table F-1
Device Codes
Option Designation

Option Name
Optical Mark Card Reader
Card Reader
Interprocessor Buffer
Crystal Clock
Programmable Real Time Clock
I/O Option Board
Serial Line Unit
General Purpose Parallel I10
Real Time Crystal Clock
Synchronous Modem
12 Bit Digital I10
Positive I10 Bus Interface

LE8-E
LS8-F
PC%E, PR8-E
RK8-EA
TA8-AA
TM8-EA-FA
TD8-E
VC8-E
VT8-E
XY8-E
AD8-A

Data Break Interface
BCC GeneratorIDetector
Central Processor Unit (CPU)
Asynchronous Device Interface
Modem Control used with KL8E or ,K L8J
Extended Option Module
Memory Extension
Time Share
Power Fail
Line Printer Control
Line Printer Control
Paper Tape ReaderIPunch
RK05 Disk Control
TU60 Cassette Tape Transport Control
DECmagtape Control
DECtape Control
Point Plot Display Control
High Speed Display Terminal and Control
XY Plotter Control
AnalogIDigital converter

*Any one
**Any two contiguous, even-odd, e.g., 40141

Device Code

03 Receive.04 Transmit
57
13
40,41,42,43,45,46,47**
50,51,52,53,54,55,56,57*
The sum of the device codes for all
external bus devices
None
11
None
User defined in range 00-77 (2)

00.20-27
20-27
10
66
66
Reader 01 Punch 02
74
70,71,72,73.74,75,76,77*
70,71,72
77,76,75.74*
05
Any device code not assigned (3)
50
Any device code not assigned

APPENDIX G
MEMORY CYCLE TIME SUMMARY

Memory Configuration

ROM only
ROM/RAM(ROM Cycle)
ROMIRAM
RAM only
MR8-FB PROM
Core Memory

Fetch Major State

1.5 ps
1.6 ps
2.7 ps
2.4 ps
3.4 ps
1.5 ps

All other

APPENDIX H
ENGINEERING DRAWINGS

This appendix contains assembly drawings, schematic drawings, flow diagrams, and timing diagrams. They are arranged
in the order indicated by the list that follows. Those that relate to a particular computer are listed with that computer,
while those that apply to all computers are listed under "General."

PDP-81A Semiconductor
Title

Drawing Number

PDP-8/A Unit Assembly
Connector Block Assembly
Connector Block Assembly'
Power Supply Assembly
Limited Function Board
Regulator Board G8016
Power Board Assembly
4K X 12 MOS Memory (MS8-A)
ROM (MR8-A)
PROM IK (MR8-F)

Chassis Assembly8H9300
Connector Block Assembly
Connector Block Assembly
Limited Function Board
Regulator Board 8 A Core
Core Memory Stack88K
Core Memory Stack816K
8K, 12-bit Base Board
I6K8 12-bit Base Board

D-UA-H9300-0-0
D-CS-H9 I94-0-1
D-AD-H9194-0-0
D-CS-54II507-0-I
D-CS-G8018-0-1
D-CS-541I531-0-1
D-CS-541I531-YA-I
D-CS-G649-0-I
D-CS-G650-0-I

E-UA-BA8-C-0
D-cs-5412000-0-1
E-AD-7012561-0-0
D-AD-H9195-0-0
D-CS-5411507-0-1(See 8A400)
D-CS-G8018-0-1 (See 8A400)
D-CS-5411531-0-1 (See 8A400)
D-CS-5411531-Y A-1 (See 8A400)
D-CS-G649-0-1 (See 8A400)
D-CS-G650-0-1(See 8A400)

Unit Assembly, BA8-C
BA8-C Power Distribution Eloard
Wall Assembly, BA8-C Center
Backplane, 20-slot
Limited Function Board
Regulator Board 8 A Core
Core Memory Stack, 8K
Core Memory Stack, 16K
8K1 12-bit Base Board
16K, 12-bit Base Board
General
Title
Hex Omnibus CPU
Flow Diagram M83l5, FC1
Flow Diagram M8315#FC2
Flow Diagram M8315, FC3
Flow Diagram M83l5, FC4
Flow Diagram M83l5, FC5
Flow Diagram M83l5, FC6
Flow Diagram M8315, FC7
Flow Diagram M83l FC8
Flow Diagram M83l5, FC9
Flow Diagram M8315#FC10
Flow Diagram M83l5, Bus Timing
8 A Internal Option 1
Option Board 2
Auto-Restart, Bootstrap
Start-up Sequence
Bootstrap Timing Diagram
Flow Chart for Option
Board 2#M8317

Drawing Number

1.Y CDOROINATE HOLE LOCAlION
A S S )DRILLING HOLE LAYOUT
MODULE ECD HISTOEY
ETCHED CIRCUIT BOAPD

5010832

HEX BOARD HANDLE ASSY
EYELETS
CAP 6 6uf 3

9006132
5

I005306

I 1001610 01

C l 2 C13 C l 5 Cl6 C18 C l 9
C2l C2A C2E C27 C26 C31

DIODE 0662

I100113
1100114

096 THRU D l 0 0

R28

RES 3 3K 1/4W

I300439

' R61

1 RES 22K I 4' W 5'7

1301606

1 R50 R5l

5
5

RES 27 I I4U

1 Rq RIO R13
R14 R l 8
RES PACK 390 O H
P I 1 R l 2 6'15 RIG R l l
RES PACK 410 OW
--. +. ..

R38,R54

5
FBI THRU FBI5
,1 II ..+
E2

I E44 Ed9 â‚¬

E l l 0 El02

1
-

E54

RES I 5 0 I/4W

.-. .

-..
... .
5%

1 3 1 2 I l 4 DO

I312114 01

.-.
--

.-.-.

---

1811660-DO

-- .

..
.
-

IC OEC 1417

IC DEC 14H21
-- - .
IC OEC 7430

: 1909058

1903923

.
-

3
I

I-.

E41 E43 E6E

' El4

1 I

---

~ D m o % P r E " ~ L " m , m , .
~ m L mY x m s Q
", E Sl*m

IC PIN LO2ATIONS

,,,,.

3&
35

1911521

, 36

1910031

I37

IC DEC 14S40

1910541

139

..
E71

11 ii a$1

IC OEC 7431

IC DEC 1442
IC OEC 74S51

I905578

IC OEC 1432

-- .-. .--

2 1 E l 6 E32

1;:

TPANSI STOR OEC 30090
FERRITE BEAD CHOKE
--.20 MHz X'TAL OSC

.......

I301522

-1910046

C
I DEC 0234
1C DEC 0235
IC DEC a271
1C
I DEC
M C 8881
#TI0

256 BIT RON (A)

256 BIT SOU ( 0 )
256 BIT SOU (C)
=BIT

FSU ( 0 )

256 BIT RON (E)

15E BIT RON (H)
256 BIT Mil ( J )
I024 BIT ROU (F)

SWITCH SELECTION CHART

(FOR AUTO REW-

I FIELD 7
2 4000
7000

1000

L0e.f-ION)

a - V

! M&Y

*[?n
RATION

O U L %'A ( T C bi
5L C L O S L D A T A

d 4 d A

5555
0000

$&'-.b l.kt!

w~61
752 L

T61 T 5 3 L

TGl T S 4 I-

PL5 SYNC

+5u

r G 2 110 S T A L L L

TGZ

nu L

IS ENABLED TO THE PC

A M E M O R Y READ I S STARTED
(REFER TO TIMING)

INDICATOR INFORMATION IS PLACED
ON THE DATA BUS (REFER TO OPTI)
FOR THE PANEL TO DISPLAY

INDI

IND2

L : MQ-8us

4-INT ENABLE

THE AC I S GATED THROUGH THE ADDERS
TO SEE I F I T EQUALS 0

THE INSTRUCTION WILL APPEAR ONTHE

MD LINES FROM MEMORY
THE I R GETS LOADED WITH THE OPCODE
AND THE Z FLAG IS ADJUSTED

THE INSTRUCTION I S DECODEDAT THIS POINT AS FOLLOWS:
M-9123456789
1 0 I1
AND
TAD

GO TO FCZ
OPERATE

GO TO FC3
IOT

SO TO FC+
JUMP OR MEM HER

9901
d S\

~2;:
iz

B- I T S
- 3-11
ARENOT

IMPORTANT AT

THE ASTRJCTIOft IS DECODED ATTH S POINT AS FOLLOWS
T H E SEQUENCES OF OPERATION ARE LOGICAL NOT CiRONOLOGlCAL
ALL OP2 < O P 3 OCCUR AT TP3
ALL 0 EXCEPT ROTATE LEFTORRIGHT OCCUR AT TP3
A SIhGLE L E F T OR RIGHT ROTATE OCCURS AT TP4
A DOUBLE LEFT OR RIGHT ROTATE OCCURS A T T P < ; 3 ) $ A N D 4 / s E \ ~ ~ ~ " m
OPERATE
GROUP 3

0
9

0
0

OPERATE

NO OPERATION
AC 60ES TO THE M Q AND THE AC IS CLEARED
MQ'OREO'WITH THE AC GOES TOTHE AC
AC$iISWAPS WITH MQ @-11
THE AC IS CLEARED
BOTH THE AC AND MQ ARE CLEARED
THE MQ GOES TOTHE AC
THE MQ GOES TO THE AC ANDTHE MQ IS CLEARED

GROUP 2

,Grp ,
1

OPTATE

I T MAKE A SKIP DECISION
1
I
THEN REVERSE THEN DECISION I f BIT821
THEN CLEAR THE AC If 0114-1
-THENORTHEAC
WITH THE SWITCHS VBIT9.1
-THEN
STOP If
BIT 10 = I

-4,5,7
H H H :DATA ENA;AC-Ãˆail
H H L :DATA CMftMQ LDEN
H L H : DATA ENA;AC+BUS,
MQ-BUS
H L L : DATA ENA;MQ L D EN
L H H : DATA CMP;
L H L : DATA C M P i M Q CLR E N
L L H : DATA ENA; MQ-ÃˆBU
L L L : DATA EMA MQ C L R EN) M O

BUS

ENA O O M E
A D L K SLINK

DATA ENA:
M 0 4 ~ :0AC-ÃˆW
ENA. ROM F
I SKIP L =(MD~'AcI?
ADLK 'LINK

~ D l g " - u K ^ : STOP
hlDS : CONWLE PLACES SWITCH REG ON DATA WS

ENA. ROM D : DATA ENA. L
MD4
6 =@
1 :A
DATA
C4U
CM
SP L

THEN COMPLEMENT H BITS=,

MD8910
H HH
H IL
HL H
H L L
L HH
LHL
L L X

M D I I = I :CARRYEN;CINL-I
ENA. ROM F
MO-5.7

HO ROTATE
SWAP AC$-SW~THU S - 1 1
ROTATE LEFTOtlCE
ROTATE LEFT TWICE
ROThn R l c M T - } ~
ROTATE RIGHT TWICE
ILLEGAL
A C LO &u L

Ã RR

Ã‡.

:LNK RR EN

)

(

J 'SS

3 WOW 6W3

TS, 1 - H , H

EXECUTIONO F A J M P DIRECT OR THE ~ Ã ˆ G O P E R A T ~ O N FOR 6 M E M O R V
REFCREUCE. I N S T R U C T I O N

A MEMORY READ IS STARTED

INDICATOR INFORMATION IS PLACED
ON DATA BUS

THE ADDRESS WILL APPEAR ON
THE- M D LINES

IA(

MEMORY DATA*AI GOES
TO MEMORY BUFFER
SADDRESS #@1(<-6@17)

CARRY E N A ;
MD EN ;ENA.ADD-MD

MEMORY BUFFER IS LOADED
AND PLACED ON M D LINES

A M E M O R Y WRITE IS STARTED

Â¥I

I EM. ROM C

1 ENA. R O M F;OOES NOTHING

I F JMP; ENABLE MD TO THE PC

I F IMP; LOAD THE%

JMP;

60 TO F SET TIME
I F JMP; 60 TO E SET
MA-MD (PLACES THE OPERAND
ADDRESS N
I THE MA)
(THE EMA L I N E S M A Y
HAVE CHANGED-SEE OPT I)

A
M S , I R DIS: DMA
60 TO FCl@

E e l
PC,AC,MQCLK
CPMA DIS :INH.CPKWÃ‘~~S

ENA. ROM B
M O EN ;ADD<-MD
DATA ENA-H
A
CIP=$m-'
E SETi-1

E X E C U T I O N O F A DCA m d M 5

SPARES

SLU BAUD RATE SELECT CHAR1
4
M S 3 l L SWITCH SETTINGS

2
51-4
S 1- 5

SI-3 Sl-2 S H

BAUD RATE

ONIONONON]

50 EPUD

SERI8L LINE 0 A W RATE
(SEE CHART)

ON = REAL TI WE CLOCK ENABLED
OFF= RE& TIME CLOCK DISABLED

51-6

ON^ TEST SWITCH (ALWAYS ON)

Sl-7

ON= I STOP BIT I N SLU CHARACTER
OFF= 2 STOP BITS I N SLU CHARACTER

SI- 8

ON= ASR/K5R 33 DR35 FILTER I N
(ACROSS SLU 20 MA REC'V L E P ~ ~ )
OFF = FILTER OUT

51-3

ON= T 5 I CLE.AR5 "DhTA AVAIL" F/F I N

PARALLEL 1/0 SECTION
OFF ^"DATA AVAIL" NOT CLEARED BY T 5 l

3600 W D
OFF l O F F ~ O F F ~ O F F19.2K
~
BAUD

~ O F F~OFF[OFF ION

jle

SERIAL HUE WILL NOT RUN AT 1H15
BAUD RATE .
H I 5 SETTING 15 NOT TO BE USED

COMPONENT SUBSTITUTION CHART

TSV

iff2
POW OK H

~ N W KL

BK DftTR CNTL L

0 K DBTfl CNTL L

8 INIT L

iff.
-

STATE EN L

HCCN f

MD ENA L

KCCNI OKTK Et-lft I-

J2
0

LOAD ADD CNA

PULSE LORD RDD L

R44

I
I

1 RES. 100 dm 1/411 5%

I 1306229

RES. 27 (HI 1/4Ã 5%

1301522

110
11
13
I4

oi.az.a3

TRANS ISTOR DEC 3CQ98

E9.56.63.65.70.76

I.C.

7474

1503100
1965547

â‚¬12.13,28,54,73.

I.C.

1469

1915575

E33

1.C. 7410

IS65576

E18,E49

I.C. 7420

1905577

I6
17
18

Elt

I E90

1 El4,E32,E6S

] E31,34.44,45,60,86

E46.E57

1 lE6

I .C. 7430

ISB5570

I I.C. 7473

I 19H5501

I I.C. 74511

11910537

I .C. 745257

1911641

I I.C. 7402

I19B9684

I I.C. 74574

I 21
22
I23

8
F.B.
44S

4 lE82.E87.ESS.E93

I SOCKET,

16 P I N

IRES
2 2 0 I/*Ã 5%
~ c ~ , c c z , c ~ ~ , c ~ z . ,CTZ
c~~,c~z,c~~
D C I , DCZ.DFI.DF2. DNI,DNZ,DTI, D T 2

11211813

IBOOZ~I

fe2

I741
[SW5743-55
5856

154
53

IWREY4J UK,.

1 DECAL

WO-RESTART SELECT SWITCHES ARE
DEFINED A5 FOLLOWS:

L)I ROM ADDRESS TRANCE; 0 - 1 6
Â£b ON' LOGIC I OR LOW; O F F = LOSIC @ OR HIGH
CCI

OROED OF SIGNIFICANCE

I N WE -HUN" STATE
1. 'AC WW" WlL UASE NIT0 --ART
CUYUIlCHERU4C5

OL-W,
U4LY D 4 % - E W m O K S T C ? P ~STATE

SI-6.T. 8 "OFF":
BOOTSTRAP
AUTO-RESTMTT DISKBI.ED
2. E82 Â EST ARE HOT ON THE TA VARIATION. ALL OTHER mRT3
REMAIN THE SAME
3 I F AUTO-RESTART IS ENABLED THE AUTO-START
FEATURE OF THE CPU ( M W I S ~W T BE DISABLCD

WOTSTRflP SELECT SWITCHES ARE DEFINED AS FOLLOWS:
0.1 ROM ADDRESS RANEE: I f - 3T7

<A) ON- LOGIC 0 OR LOW; OFF = LOGIC I O R HICH
I

ORDER OF SIGNIFICANCE

= 2'
2m (nsB1
szc=2' = 100
S2T=ZS = 4 0
~ . 3 = 2 '= 2 0
10
S, 1-29
S, 2 =2' = t
S, 3
'2'
2

.
.

THE m OF ADDVSSS IS c-urn

BY
THE BOOTSTRAP/ AUIU-RESTflRT UIEIC

RFan6

-No

REF. DESIGNATION

DESCRIPTION

PART
HJMBER

d0.
I

PULSELOAD A D D H

I K P I LOAD ADD H
L O A D ADD E N A

Du2KEVCMrRLL

MS.IR DIS L

C L K ~ I

1
M I K P 1 LOAD I"

ROM

BYTE H

I^ADD

M I K P I L5B ROW ADD L

SET-UP

M W 1 ENR R O D DBTB L

PULSE
NULL

RwuKM
CHK~

- --

CLOCK
DISABLE

E98-8

EXTERNAL
CLOCK XN

lREV
I

=NO

I
1

rff

- 1

BOOTSTRAP/AUTORESTART CONTROL

NnmER

,Je3,7-p-,
1

INT I N PROS H wi
BBUF I N T I N PRO6 H

DATA 0 L

BBUF MD0 H

8637

DATA I L

8837 6

8837

8837 6

BBUF M D 2 H

I/b PAUSE L

BBUF DATA 0 H

BBUF 110 PBUSE H

T51LCK2

BBUF DATA I H

BBUF TSI H

TSZ L

BBUF DATA 2 H

cL2
BBUF T 5 2 H

TS3

BBUF M D 3 H

8831

t
BBUF MD4 H

BBUF DATA 4

DATA

BBUF M D S H

DATA 6 L

L
p
.-p@I4

8837 Â

D A T A 7 L 7 3 - 9937
3

BBUF T 5 3 H

BBUF T S 4 H

TPI

BBUF DATA 5 H

H cD2
BBUF T P I H

BBUF DATA 6 H

4
BBUF DATA 7 H

BBUF DATA 6 H

DATA q L Ds'

BBUF DfiTA 1 H

L~p

DATA I$

DATA Il

BBUF I N I T L

8 9 3 1 12

BBUF DATA 10 H

9931 14

BBUF DATA 1 1 H

Â£6

. BBUF POWER OK H

m
CHANGENO

I
8

IREV

BUS BUFFERS

I
8

NOT I.â‚CLOCK
¬5 ENULE MM bE FklAE Kl
1

AUTO-REST*.=

5EGbt.W.E

----Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘Ã‘

T U B TIME, IF !NIT H I S
FALSE. CLOCA E U M - E THEM
HIGH (KSXRTED) MEN

RTUEMS

M E MOTE 0 Z

L 9 c K \ ~I - ~ ~ r
SEE N O T E * i

I W H &EE.OMES TRUE

2. THE LOGIC WklTS FOR IU!TIALlâ‚
TO ^IMn OR LNQ liEFOR1
CDNT\UUlN&

3. THt-^E FLIP- FLOPS &RE
CLEARED AT THE CONCLUSION
OF THE kUTO RESTkRT 5YC.LE

4. ACTNE 5ETS X l T H E LEXT
CLOCK PUeE THEN C'-<MiS

tT THE END OF THE 3 C L E
5. GO F(F CLEARS AT Â¥"H END OF
CXLE

6 .DETAILED
SEE D-PO-T I M
KtiAb-A
I h L CATk FOR
kFTER
AFTER ACTHE

1% S 5 T

7. THE SWITCHING TIMES FOR AC
LOW MS. A FUHCTIOH O F TUE
S t E W ROTE OF THE CItAUITt. IU
THE POWER SUPPLY

W A I T F!F

I. ONE "DEPOSIT" CYCLE IS SHOWN IN
. DIAGRAM.

2 WHEN "RUN- IS TRUE (LOW) ALL TIMING
IS HELD OFF UNTIL THE NEXT CLOCK
PULSE AFTER - R U N GOES FALSE : H e
3. FOR THE -LOAD ADO- CYCLE SIGNALS
REMAIN THE SAME A:. SHOWN EXCEPT
THAT "PULSE LOAD ADO" REPLA^ES'MEl
START- AND KEY CONTROL' IS NEGATEC
FOR "EXT LOAD ADO" KEY CONTROL IS
TRUE.
4 MEM START APPEARS HERE ONLY FOR
THE START" FUNCTION. THE EARLIER
MEM START IS FOR "DEPOSITS' ONLY

3
ASSE.WELY IN STRUCnGNS
OPE.BKTIOU5TO BE PERTORMED PEU HARD
M U â 5TAMDW(DS ('5P7 & & 5 0 9 9 - 0 - 0 ) AND/
OR DEC- WORKMANSHIP STANDARDS
? IN5TM-1-TUE CONNE.C.TOP BLOCK ASSY
. \ T â ‚ ¬ M * INTO T H E POWER SOPPLY ASSY
I
T 0
2 WITH H A U W A R E ATTAC-Hâ‚¬

h PLUG-t-ME 516UAL

&JMPER,FBoHJ~OFT*

W â ‚ BD, INTO 39 OF T H E COUNECTOR BLOC1

B,sS<(
PLUCt-We
ITâ‚¬-MW
12

7UMPEWS FUOUTHE-PW5

SO \NTO THE CONNECTOR W C K P.55Y 4
PLf-c.EA.
ISV T O 16V, Â¥ 15i; T O MSV, + ' i V m 5 V
A M 0 <WD T O GRD
INSTALL THE W~OOULE~
PER RMCTS L1ST VAUVATIOUS B E L O W .

MOUMTING INSTRUCTIONS

D\Â¥5&OUUEC THE CAB&
FUMCTIOU 6D.

CENTER LINE. I5

FROM THE LIMITS:

3.RS.MOME THE LATCH MOLOING ?0 Â¥SPACER

4 PLhCE-5.
4. REMOTE THE %â‚¬

NUT FTOM THE CHA5

- 5 1 5 AÃˆT INSTALL ON CABltiET POST 8
PLACE'S PER WWNTING

D\UEUSloHS

ON 'SHEET * I .
5. K MKT BE MECE&BRY TO REMOVE THE
. E l L T E R RETMNER BNO THE F I L T E R 1M
0RDE.R TO HOUW THE BOX 1M R
CRBlUET.
b WITH T U C &Ã I N P L B C E , IU T H E CRE
UET,

KPl-WE THE LRTCH MOLDING

BUD SPBCER5

50 - 7 0

SECUBE

THE ESX TO THE C F46lUET.

1. PLUG THE. CB0I-E. 1UTO THE L I U I T E O

rUMCT!cW

aS R u b <BÂ£PLR'LEU W T O

FUNCTION P W E L
8 REPLRCC TW. Naw SHEL
9 WEIUSTBLL T H E FILTER
1Ã§E.TTOS MJD THE F I L T E R .

RI-L

eâ‚

I.REMOTE THE BLMJK BEZEL A55Y.
2REMOVE THE LIMITED FWCTIOU PANEL AND

n.c.

P D P ~-^NEE
su PPLY
O U T P U T 5 NEE PROUVDED "TO
D R I V E LOGVC
IMTEENM- 70 T H E
BhS I C h N C H \ME E t Ã ˆ C L O u
D\G\-TCiL W i U - M O T B E RESPONSIBLE FOB THE PERFORÃˆ^ftMC OF THE PDPSA I F hW/
D.C. POWER \ S T M E N Oi-iT5\Eâ
THE M h C H l W .
2. ENVIROUHWRL COUDlTIOU'a FOR
rtlP8B BRE S E C I F I E D Ik)
D E C 5 T D 102- C L R 5 5 *C"
EklVlR0UflE'kl-T.
3.
A S T E R I K ( ~ D E N 0 T E S MTG DIM
4. THE D I M FROM CEÃˆ>Â¥T LIME. Of R W T
CAB UPUtGrtT MOUNTIUG HOt-E. T O
LEFT CAB OPRAWT >AOUKIT\UG HOLE

~ 5 - s ~

18-31

FOR VOLTAGE AMTI 'FREQUÃˆUC CON-VERS\ON 5E.E DEC Ow^WlNG â‚¬-UI^-M165-

CONVLR51QN CHART

YYYY -

-R
J4,6dIHZ

(

)

J5,dHZ

5410960
%RD
A55Y

J7,ll5V

;

NEUTRAL
FWWER REQUEST

J6,Z30V

TW l B l T W l B 3 T B S
V ' J V V V

ATTACH T M E M W L â %-FX
BUACUKTCITCM
-15)TO TUE &Wâ‚ =T OF \N%â‚¬R iU TliE
W ~ ~ S ~ ~ ( I T E ~ ~ ) W I ~ % - ~ X \ ~ % R W S < ~ W
*-)AND
*BL'WAS~EU(ITEW*B) PLACE^8. N U 6 TUâ UE-T0RBDAS%VClTEMZl)
WTO
TUC XWEU m(17~-25>
+.w ~ S L U U E u51u6
1 1 4 T U U V FASTENER5 ATTACWS
19. A l T A C U -illâ
9 t L D MUT~(ITC~*~I)TO
7M
?O.

CHA5SnS CTIE~;)
SPLhCE5
A T T W N T H E LATCU MLCtUG(lTâ‚ 29)AND
T M â -ER(~Tâ‚¬M-?O)
TI+â CWS5SS
( l ~ ~ ~ ~ l ) w \ T ~ 5
~Pl LoG~-THO
3 2 x XUEwS

21.

(lTâ‚¬S1-2
PLU6 TME OTWU END OF TMâ U E m - 0

TO T U E W A 5 S l S C\Tâ‚¬M*
24.

5LlDE

F I L T E R (ITEM-6)

IUTO

fliT~.?aâ‚¬TB\~Lrnrl*4

NOTES',
I. T R A N S I S T O R
DEC 2 N 5 3 6 2 1 5 ' 0 1 9 G bi$Y
BE
d S E D AS A S E C O N D S ~ U R C E ' F O RI T E M
62

R30

RES

100 1/21 KTC

1x7

RE?.

2 7 1/2# 10%

HU760

07,012
TRNIS. DEC 2N3715
I 0 2
TRANS.
2K3762
6
01 03 04 05 09 010 013
O I ~ , Q ~ ~ , ~ I ~ ~ U ~ Tws.
. O Z ~OEC, O ~ ~ ,

1389444

16C130GI
1509641Kil
1510705

n,Q "?a ",C

?&
,57

9 0 - 0 1 9 2 6
?I-07380-00

-re8

O F C B i

91-07350-22

S O L D E R 8-T
SOLDERLESS
C 81 END

ZeL

T B 8 END.
CONNECTOR

<?a-Ol926

S P L I T LUG

SOLDER

5 I

S P L I T LUG

SOL-DEB A T

AT SPLIT L U G END
51

4 0 0

END

+.DO

[
c
*/R

*22 AWG
9
COMPOUBO

I SLREli 10-32 X.31

2
2
1

WIRE

THERMO

" 9008268

! DECAL

I FINAL INSP. P W . FOR G8016

BF F

1 PWER SUPPLY TESTER

REF
I

FKCKSING I N S T R U C T I O N

1 RW

Q T t R E F DESIGNATION

I
8

1
7

H 76 3
REGULATOR

$
13

/A-DC-741310300'97
% - S P - G ~ ( I ~ - ~ ~ - Q38
B - P D - G ~ @ ~ ~ - T A39
~ A - S P . ~ ~ O ~ I ~ ~ I O O

RWfSlCws

CWWW

='LANRETN

Ctl
I

901.030*01

DESCRIPTION

BOARD

C N C&
CCI
c.91 C#Z
cc2
CDl CDL
C E I C#â
cfl
c6-2
CH/ en2
C J l CJZ

DUI

DVI

DUZ
DVZ

~ R T T EMPTY
.
Cl~c~lT

msmw,m m mc,,8u7m mmm THC

~ : ; ~ ~ ; g ~ ~ ~ ~ NOTES:
~ ; z w ~ L
~ ~ T ~ , m - ~ m , * w ~ l ~ m w ~
l m m I + m " mnm

r n W @,974

1 FREQUENCY J d M P E R ( I T E M ~ ~ S ) M U S T

BE C O N N E C T E D

TO J + O R J5 BEFOREBOARD CAN BE TESTED

2 JUMPERS CITEMW27)MUST BE CONNECTED (re11TC c 3 - 1 6
7 ~ 1m
5 c 3 - a B E F O R E CANBE O P E R A T I V E

SEE NOTE 2

c m
~

' = 0 m D 5 V ~ ~ Y P m 7 W l .
Y W ~ S T A l W P E W

.,m

b2 FlN W f i T m S

C8S

UTSRPNMLKJHFEDCSA

VUTSRPNULKJHFEOCWA

VUTSRPNMLKJHFEOCBA

VUTSRPNULK,MFEDCBA

SWITCH
SWI- I
YWI-2
SWI-3
SWI-4
SWI-5
SWI-6
SWI-7
=I-8
SWI-9
SWI-I0

1
1

E M
EM[.
Eh!4
SEL0
SELI
4K

2K
IK

DEFINITIONS
FIELD SELECTON

' n ~ 's
.- m
STAFiTING m E S S SELECT
IS 0

'w'

M E W Y SIZE SELECT
SIZE -'ONr
OTHERS
M C T bFF'

U S D FOFI TEST WLY, ALWAYS

JUMPER
YA,YByYC AND YD
YE,YF, YH AND YJ

- wl,wz,w3 M E IN
- W4 AND W5 AftE IN

CONFIGURATION
w 4 AND w5 ARE W T
WI,W2 AND W3 ARE W T

b ~ '

MMI

MÂ£ DATA C U

-po^
,c

MMI

RE"&%

-W

TSZH

IRW

-- -

tit
$ 5

TWLE

W E B

4K X I 2 MOS MEMORY ,Mas,,
4

=LE

-5'-

lsn~n3

w 6

REV

rrr

, , "" ,

4. DIODES AND JUMPERS SHOWN IN DOTTED LINES ARE NOT PUT ON THE
m m URIK WFACTLWZ.
i n t i ix ADDED DIK CIIECVSUI
AS KWIREO. SOLID LIME JWPERS 1% POT 111 H
E
M MUM IS ASSEÃ‘LED

own

5. WLESS
11s
mTEo
KSISTMCE IS IN 0MB 1/41 Ãˆ
6. A

J W E R (MM JUHMESS) IS ONLY INSTALLED IF

IIE fnm ~CTESSES OVERLAY ast IBÃ‘ AMISSES

3. DEW W T W I IS Â¥OJIBTE TO 2 2

1 . (LESS

+ 54 MS.

OTHER DISF. SPFCIFIED ALL OELIY H I E S Ãˆ 1 ZO#

8-44
REF

DEC 1 7 0 2 A

w
I 2

~ BT,i,a~z,
~ ~ ~

CCI C C 2 Cn C F Z C N I C N Z CT2
D D l , DCZ,DFl,DF2,DUI ON2 DTI. OT2

10.44

REF

I "

.--

,--

I
I

CHART

Y VARIATION

REF
c o M p o N ~ N ~ s M:y9

Me343
YC

REF

OUT

1.C. DEC 7 4 2 0 0

OIOCE CJUMPER SETTINGS
FOR ADDRESS DEFINITIONS

UEMORV FIELD SELECT

'SW"OR"BOOT'
FIELD SELECT

-- .--

IOK POT 3/,v 10%
HEAT I N K : TRANSISTOR

JUMPER BELOW
R4

0
1
2

I
1
I
1

RS
1
1

R6
I

1 -

, - I -

I - = D I O D E O R JUMPERIN
=DIODE OR JUMPER On

I 13M143-10

1 1210001

K-Y COORDINATE HOLE LOCATION 1K-CO-M8349
ASY/DRILLING

HOLE LAYOUT

I ECO MODULE HISTORY

I JUMPER YA2 I

.MB

m
61

0 d 62

iO-AH-M8349-Ãˆ- 63

SCRE-ENS , DEC PIN C-MD-"1+04G81-0-0
(UCTES

CONTIUUED ON

ShEET

#3)

1 1 I 0-0-00!6HASSEMBLY
a121
1
I NSTRUTIONS
OPERATIONS TO BE PERFORMEO PER HARDWARE STANDAMS
SP-lSi5099-0 MID/OR OEC IORFJWiSHlP
STAWAROS.
ATTACH F O U TAPE (ITEM 0 4 ) TO CHASSIS (ITEM *4) AS
SHOW I N VIEW A-A.
INSTALL FAN HA6WESS (ITEM $0) INTO CHASSIS AS SHOW
I N DETAIL "A",
T A C H FILTER RETAINERS (ITEU Ãˆ6 TO THE TWO FANS
( I T E U P5) WITH T6-32 X .62 FLAT HEAD SCREW (ITEM P22)
U D THE APPROPRIATE MOUNTING HARDWARE (SEE NOTES # I & 2 )
FOUR PLACES EACH F t t l .
PLUG FAN HARNESS CONNECTORS J l 8 J 2 (SEE DETAIL "A")
ON TO THE FUN TERMINUS.
ATTACi FANS TO CiASSlS NITH R6-32 X .62 FLAT HEAD SCREWS
(ITEM Ã§22 AN0 THE APPBOPRIATE UOWTING HARDWARE (SEE
NOTE # I ) T I B PLACES EACH FUN,

J!4

REIORK FIVE CARD EIJIDES ( I T E U # l 3 ) AS W O W ON O E I A I L
"E".
S T A L L FULL LENGTH A
H O E S (ITEM -13)
CARD GUIDES AS SHOWN ( 1 0 PLACES).

AC OFF

+SV

MID REWORKED

INSTALL THE 4
TURN RECEPTACLES (ITEM Ãˆ32 ON THE TWO
A S ON THE BOTTOM OF THE CHASSIS,

L I N E LEVEL

ATTACH THE H9194 CONNECTOR BLOCK ASSEMBLY (ITEM #3) TO
THE REAR OF THE CHASSIS WITH #6-32 X .25 PAN HEAD SCREWS
E M 2
AN 0 E
X0
LOCK WASHERS (ITEM ÃˆZ5
TEN PLACES.
PLUG P I OF THE FAN HARNESS ( 4 P I N CONNECTOR) INTO 1 1 0 OF
THE H9194 (SEE DETAIL "a", SHEET 2)
aTTACH THE L I E Sâ‚ (ITEM #9,10,11 OR.12) TO THE FX&R OF
THE CHASSIS WITH TWO Ãˆ6-3 X .25 LG PAN HEAD SCREWS (ITEM
6
0
TWO 6 EXTERNAL TOOTH LICKBASHERS (ITEM Ãˆ21 AS
SHOWN.
PLUG P1 ( 6 P I N CONNECTOR) OF THE LINE SET INTO J I S OF THE
9
4 (SEE.DETAIL "0").
PLUG ONE END OF THE 16 CONOUCTOB CABLE (ITEM # I 9 1 INTO J l ,
OF THE H9194 AS SHOW.
SET THE TRANSFOmER ASSEMBLY (ITEU :I1 OR 18) I N THE CHAS!
Ah9 FASTEN THE GREEN WIRE TO THE CHASSIS WITH M E -0
X
.3B SCREW (ITEM #35) TWO # 4 INTERNAL TOOTH LOCK WASHERS
( E M 3 6 E
FLAT USHER (ITEM Ã§23 AN0 ONE M - 4 0 KEP
HUT (ITEM Ã ˆ I 5 AS SHOWN I N DETAIL "C".
PLACE THE TRANSFORMER ASSEMBLY I N POSITION (THE 16 CONDUC
OR CABLE SHOULD BE ROUTED WERNEATH THE TRANSFORBER) AN0
ATTACH TO THE C H I S I T FOUR U10-32 X .50 PAN HEAD
SCREWS (ITEM #30) MID $10 I N T E M A L TWTH LOCK WASHERS
(ITEM *31) AS SHOWN.
PLUG P2 OF THE TRANSFOBMER ASSEMBLY ( 1 2 P I N CONNECTOR) I N
EITHER J16 (115Ãˆ OR J 1 1 (230V) OF THE H9194 (SEE DETAIL
"B",)
CONNECT THE THREE LARGE WIRES ON THE TRANSFORSR ASSEMBLY
THE TABS TBI. TB2 MID TB3 (SEE DETAIL 3BI ON THE H9194.
BLU/BLK WIRE I S ALWAYS CONNECTED TO THE CENTER T I P l~T R--,
7>

VIO
YEL

PLU6 P I OF THE TRMISFORUER ASSEMBLY (6 P I N COHHECTOR) INT
I
OF THE H9194 (SEE DETAIL KB).

L U G THE 60016 RE6ULATOR B0AÃ‡ (ITEM Ãˆ2 INTO THE H 9 1 M A
SHOWN, AND SECURE I N PLACE UITH THE TWO ATTACHED 1/4 TURN
FASTENERS.
ATTbCH THE LATCH MOWINGS (ITEM P l 4 ) TO THE CHASSIS WIIH
#ID-32
x i s FLAT HEAD SCREW(ITEM #29) mu SPEEO w s
(ITEM #2B)

MASTER

DETAIL '-6"
SCALE.:

PLUG THE OTHER END OF THE 16 CONDUCTOR CABLE INTO J1 OF T I
LIMITED C T I O N PANEL (ITEM f 2 1 ) SEE DETAIL #C.
ATTACH THE LIMITED FUNCTION PANEL TO THE CHASSIS.
iTTACH THE BLANK BEZEL ASSEMBLY (ITEM Ã ˆ 2 0 TO THE CHASSIS.
L I D E FILTERS (ITEM Ã ˆ l INTO FILTER RETAINERS.

DETAIL. C "
S W I T C H LOCATIONS ON
'LIMITED F U N C T I O N BOARD OF
PANEL A55Y ( I T E M ^ Z I)
5rAIL'-

MOUNTING INSTRUCTIONS
1

W W L E A S S I W E N T S AN0 POWER REUUIREMENTS

(SEE N O T E S *

SEE DETAIL " 0 "

THE I FROM CENTER LINE OF RIGHT C M UPRICHT
WHINTING HOLE TO LEFT CAB UPRIGBT WUNTIIffi HOLE
CENTER LINE I S 18.31,

7 i 8 1 1
3.

H I V E THE BLANK BEZEL ASSV.

REUOVE THE L I U I I E D FWCTION P W E L A M DISCfflmECl THE
CABLE FRffll THE LIMITEO FUICTIOH M,

DELTAI L'D"
AVAILA~LE

CURRENT

-H93m-AA,AB
- H 9 3 0 0 - BA.BB

25A

*
-1A
2A

SCALE. '. -'Ã‘Ã

SHARED

TO CREATE A 115V 50 HZ CORE V A R l A T l f f l USE THE HS
E
L H E LINE SET I T E M 2
I T A 1 5 Z % s
HID PLUG P 2 [ l 2 P I N
LINE SET (DEC P A 0-ID-1010915-03)
CONNI OF THE T R A N S F O R M E R ASSEMBLY. INTO
~ 1 (61 1 5 ~ )
OF THE H9194

ALL H 9 3 W POWER SUPPLV D C OUTPUTS ARE PROVIOED TO
DRIVE LOGIC I N T E W L TO W E BASIC MACHINE ENCLOSURE,
D I C I T 1 L (ILL NOT BE RESPOKSIBLE FOR THE P E R F O m W E
OF THE H 9 3 B I F ANY OC POWER I S TAKEN CUTSIDE W E
MACHINE.

REMOVE THE LATCH W L D I N G I 4 PLACES),

REWVE THE SPEED B I T MB INSTALL OK CABINET m S T , 8
PLACES PER WUHTING DIKENSIMS.

E N V I K N E N T A L C C W I T I ~FQR H 9 3 W ARE SPECIFIED I N
KC m 102 CLASS ' T "
ENVIBC~EHT.

I T M A BE NECESSARY TO REWVE THE FILTER RETAINER A M
THE FILTER I N ORDER TO HOUNT THE BOX I N A CABINET

WITH THE BOX I N PLACE I N THE CABINET REPLACE THE
LATCH WLDIM ua S P ~ E R Sso AS TO S E ~ THE
E BOX TO
THE CABINET.
PLUG THE CABLE INTO W E LIMITEO F L N C T I M M Am
REPLACE LIUITEO FUNCTION F U E L .

THIS ITEM (NAUEPLATE) I S SHOW FOB REFERENCE WILY.
I T I L L BE Ã ˆ E OH A HIGHER LEVEL A S S E-M 8 1 Y .

INSTALL M O B U I E S S F O L L O W S
P L A C E M E N T O F HEX MOOULES I S FROM S L O T #!(TOP

+ 5V

MAX. LtNIl WEIGHT = 55 LB.

FOR UTG D i l l

REPLACE THE BL1MF, BEZEL ASSY: REINSTALL THE FILTER
RETAINER WO THE FILTER.

*
PL:E+EETO~QUAD.

BACKPLANE' DOWN

MOOULES I S FROM S L O T ~ ~ ~ T ~f
C M

- SV

tI5V

- MEMORY REFRESH

A C LOW

(+5V!

B M T E R Y CHARGING
INTERLOCK

-016

LINE LEVEL
A C OFF

-0 8

05
-015

BATTERY OFF
SPECIAL G N D

PANEL LOCK

-03

3w
+l5V

01
-0 2

5V
RUN

-0 12

09
0 10
011
0 14

AC I N

E M E R G E N C Y 5H;TL%?'5T

LINE I
NEUTRAL

RfvlwNs

-- -

CHANGENO

[REV

TITLE

CONN BLOCK ASSY
8

ISHEETZ

SCALE-++-

0f2

1-1

1 1 1 1 1 1 1 1
1

33 C'Ã PLACES)
3 2 (4 PLACES)
2

4 SIDE
~ 1,BPLACES
~
~
5SIDES)

(4 PLACE'S)
WIRE. Z t A W G , GREEN

9107lÃ§BB 5 5

WASHER,FLAT
8
9006660
-

WASHER,INTL TOOTH *8

9006634

II2

SPACER,*~-~
X.25AFXI.
~
25 900 9603
SGR , SLF-TPG '8-32~1.61 9009070

S C R SOL HD '8-32x1

9008471

90060 5 5 - 0 1

I
t

5 C R PHLPAN H D ' 8 - 3 2 X - 2 5

---

10.0 REF

re5

Z J ~ , J ~ ' C O N N B L K ~ ~ P I N S L T D ] II 9~ I ~ ~ ~ ~

~ J ~ - J ~ ~ C O N N B L K , ~ ~ P I N S L T D ] ~ Â £ I I18O Z

27,

6 Jl

PLACEc

J'21

J ~ ~ C O NBNL K . 2 8 8 P I N SLTD
I S O C K E T I C 14PIN

1210258

1211813-01

2 J14.J-20 'SOWET,IC, & P I N

CARDGUIDE,CENTER

12 1 0 6 9 8

CLIP. FUSE

9007203

SOCKET, RELAY

I I
PIN'I
\

L
(6PLACES)

S C A L E : I/I

TRANSFORMER

1611646

, I4

'03

I REF

/
pin

4 . 5 0 F.B.S.

IT (~PLACES)

't^

32:

Ill

NO S U B S T I T U T I O N S ALLOWED.

3 H E I W T O L E R A N C E MUST BE
W A T C H E D ON I T E M 7 (1000 P F )
HOT T O E X C E E D ,312.

/5.4./ REF

~~
SEMICONDUCTOR

I
PARTS LIST

R?Z

RES

R\O8

RES

7.74 K

I/+W

I
I
] 1 3 o S 1 3 1 - 0 0 in?

N R WIS-W\0

3.+8 U l/4W \-(WIRE -30 kWG 5OLlD GREEN

I 3 0 5 114 - 0 0
9105740-55

R\O\

RES 4b.4K

l14W

130331 1 - 0 0

R70

RES 5.b2K
ll4W
TRANSIPkD

1.A

1305128-00
30072.01-00

,=I

192

CEXT 54 50 Gz GY

t20v vz

50V

B3 5TRC0E T I M E 2A H

33 CLWR TIME Z L

BIT 5

-VREF

tV REF

077

4.7K
H I LLVEL G N D

L A
N

B3 51-

TIME ZA H

03 CLEAR TIML

BIT 8

r-----1

83 STROBE TIME ZA H A
63 CLEAR TIME L

-V REF
R34

DIP@
, .r

H I LEVEL GND

4.7K

ZN653l
Q10

ea01
E40

03 MD DIR TIME 2 H

DI&

,4128

- â‚¬

6 p,~

03 INHIBIT TIME ZAL

&::z

0 3 5TROBE TIME ZAH
B3 CLEAR TIME L

D@5
m
N
IU LEVEL GND

Ql2

ZN653l

-TIME L

BIT 7

83 S T P O S E T I M E Z f l H
8 2 STIP08C T I M E Z B h'

Z EXTERNAL
0
i 6 . 3TOOTH
1 ) ARE.
LOCK
BEING
WASHERS
USED (TO
ITEM

ENSURE A P 0 5 1 l W E G R O U N D .
3 INLET A I Q F L O W V O L U M E IS 5 4 0 C,Fl
W A X I M U W A1 S E A L E V E L .

ASSEMBLY INSTRUCTIONS

A
H f t N IMRNESS (ITCH 11) TO rbN5 (ITEM Ã£
33 &SCMBLE l/4 TUW RCCSPT4CLC (ITEM IS> TO
C W B I S ( l T E m 1)

4 4SSEMBLE LINE SET ASS" !ITEM 7 ORlTEMB)
6tU6

W L W UD XREW b - 3 2 1 2 5 L b (ITfNq)
TOOTH LOCKW5HI.R (ITEM 10).

b T

5 A S E W E XFMR t,%Y (ITEM ZOR3) T O CHAÃ‡.Sl
( I T E M 3) USING * I0 EKT ?COT# LCCKWASER (ITEm4
F T WASrtERf ITEM 5 ) WD 10-32 UEP Nul ( I T c r n ~
I

A T C H C-2 (6TOW!%) rROM UNE SET A M Y
7
8 ) AND XFMR W D O T E M 2 0R-i)
TO
USING
S T
(ITEMS
E M 4.5,Cb).
1) & S H O W BY D E T M L A,

5.2 ~SSEMBLEu E Y m m u m ~ E( ~ ~ 4 TO
8 )
USING
X
U
(ITEMS
A
\^iÂ£Zb
h S Y (ITCMI4). SEE DETAIL E

h 455EWLE CLNTCR WWL 4 5 5 ~(ITEM I*) I&!NG
"b EX1 TOOTH LDCKTOSULB (ITEM 10) tND PHL
W 0 SCREW 6-32 X ,361.6 (ITEM 25).
7 CHh5SIS
A55EM8LE
(ITEMI);
CARD GUIDE
USE TOOL
(ITEM PRCNIDED.
lq AND ITCM LO) T o

\ PLUG HFMR 45SV (ITEM T O R Â¥iTEM3 TO CENTER
W&LL ASSV (ITEM 24).

24 REF
/Ã R E D S T R I P E
5IDE

dREF~~\5
DETAIL 'Em
PROPER FOLDING
O F C A B L E (ITEM-41)

4 3 REF

1. ATTkCH CABLE Cf YFMR te&Y (ITEM TOR31 TO
CENTER WALL AS5Y (ITEM 24) AT 3 1 0 TERM,
STRIP
.
.
I
T C U CONN FROM LINE 5ET kSSV(lTEM7oR8
TO CENTER WALL (ITEM 24).
1 AKLMBLE C A P K I T W (ITEM 28) TO RE&UUWR
BOtRD SHELF A5SV ,(ITEMZ?) &IN6 CAPKITOR
CLRMP (ITEM Lq) WITH PHL Tub55 W%REW 8 - 2
X .36 L G (lTEM30),*8 EXT. T W T n mKW&HCR
flTEM 31)AND KEP NUT 6.32 (ITEM 41).
101 45SEM8LC 814 TUUN R E C â ‚ ¬ P T A < (ITEM 18)
T O REG SHELF AS$\ ( I T E M TI).
LO.? ASEMBLC WTFRPILLAR G W M E T ( l T â ‚ ¬ M
0 REG S H E S ASSf (ITEM1-1) USING PERMA
80ND AQKESIvE' ( I T ~ M35).
M B L E REG. SHELF ASS\ (ITEM 21) T O CHASSI
(lTEM1) 6 I N G * 8 â‚¬ TOOTH L X K W A W E R
(ITEMW).
(ITEM 31) AND PHL PAN HD SCREW 8 - 3 2 x . 3 ~
11.1 ATTACH CABLE OF XFMR 4s5Y (ITEM L m 3 ) TC
RCG. SHELF A S Y (ITEM 27) USING FLRT
B EX1 T m T H d C K WASHER (ITEM32)
WAWER
9 - 3 2 X . 3~8VLG.
E M3,)
C l l~E N~ a
W
D ]L. PAN MD SCREW '

11.2 ATTACH LEADS OF XFMR A55Y (ITEM Z C U 3 )
TO CAP&C(TCU ( ! T E ~ ~ ~ ) & M D C O VWITH
ER

DETAIL -C"
S W I T C J LOCAllON5 O N
I N i T E D FUNCTION BOARD
OF P A N E L ASST <"nâ‚¬l"
40)

DETAIL "B"
J A C K L O C A T I O N 5 O N POWER
D I S T R I B U T I O N B O A R D OF
C E N T E R W A L L A S S E f B L Y (ITE~"\*z+)

5412000
BAS-C P O W E R
DISTRIBUTION
BOARD

FPB-A
KE8-E

FLOATIS m l N T
M a 3 4 0 EAÂ 1R

;:;

Me341 EAE REG

; ;II
20

4 - 20

25A

LA8-P

LA180 CONT

QUAD

4 - 2 0

IDA

BOOT LOADER

QUAD

75A

KL8-A
E

RK8-L

MSLU

] RKB5 CON7

QUAD

- 20

0SA

425A

- - 05A

' 4 - m 1 3 5 A 1 - 1 -

Ã WITH K E 8 - E OPTION M E 3 4 0 f M8310 MUST BE MOVED TO SLOTS 16 4 17
RESPECTIVELY THE KE8-E OPTION PLUGS INTO SLOTS 16 / 19 ( M 8 M I # ~ 8 3 4 0 )

AVAILABLE CURRENT:

S L O T S I THRU 10
&+
- 15V +15V
25A
2A
2A
[ M A X > :MAXI [ M A X I

t 5V
-

-15V
+*
-

25A
(MAXI

2A
2A
( M u 1 (MAXI

ASSLW.BLY NS-32 CIIONS CONTINUED
1

I
NE
R L60l9 !'TE:M "Sb) TO CHASSIS
(ITEM 1) N D E N T E R *AU&55Y (ITEM 14).
12-1 INSERT UPPER G8018 ( n E M 3 b ) TO RC6 SHLLF

T 11) 4ND CENTER WALL f^Y

(ITEM24

ID.ADD \/4 TLRN UECEPT~CE (ITEM te) TO TOP
COVER ( I T E M - ~ R ) .
14. A55EMBLE TOP COVE3 (ITEM 38) TO CtIA55lS
(ITEM 1) USING *6 KYT 7207% LCUWA5HEU
(ITEM 10) M D PHI. PAN HD SCREW b-32 X .25 LG
(ITEM q).
15. A55EMBLF REAR COVER (ITEM 37) TO CHASSIS
(ITEM 1).
I6 ASSEMBLE LATCH MOLDING (ITEM 21) To CHASSIS
(ITEM 11 USING 10-32 SPEED NUT (ITEM 23) ANC
WL FLAT HD SLEW
1 0 - 3 2 x . i s LG (ITEM 21).
$1. &TTACH KEYBOARD CABLE (ITEM ))=I
To
L(M!TED FUNCTION P4NEL (ITEM 40).
18. ATT&CHs'/q BUN& B E Z E L ~ S ~(ITEM
Y
3q) TO
CUM~S~~S
(ITEM I).
1% ASSEMBLC HARNESSCOVER (ITEM~S) AND F\NGER
GUARD ( 1 7 E w i 1 ) TO FANS (ITEM ~ 9 U) 5 l W

M A X UN\T WE\GHT = U 1 LBS

MOUNTING INSTRUCTIONS
I SEE DETA1L"D" FOR WOUN-TING DIMENSION5

2 REPlOVE THE B L A N K B L T E L A S S E M B L Y OR
PROGRAMMER'S PAME.L
?.REMOVE THE LIMITED FUNCTION PANEL AND DISCONNECT
THE CABLE F R O M THE. LiM\-TED F U N C T I O N BOARD

R O V E THE LATCH MOLDING

f.4 P L C ' ~ ~

5 REMOVE THE 5PE.E.D NUT, AND I N S T A L L O N CAE UPRIGHT
EIGHT P L A C E S PER M O U N T I N G D I F E N 5 l O N 5

6 11MAY B E NECE55ARY TO REMOTE
AND

T H E F I N G E R GUARDS (4)
H A R N E S S COVER- I N ORDER T O MOUNT BOX. I N C A B .

A N D L O C K WA5HEQ5
T A T T A C U HOUNTING RAiL5 U S I N G %=CREWS
TO L t J T AND RIGHT 5\Câ O F C b B I N E l A 5 F E U D L T A \ L " D "
W I T H E 0
I N P L A C E , I N T H E C.A%i^.T,
R E - P L k C t 1V.E L A T C H
MOLDING ,SO A5 TO "sEC-URE
T H E 00Y. T O T H E CAS1NE.T.

9U
H
CAB\-^.
I N T O THE. I-lM\T^O
REPLACE -INâ P A N E L .

FUNCTVOM P A N C L

AND

IQREPLACE B L A N K B E Z L L OR PROGUAmMER'5 PANU
11 U E - l N 5 T A L L C\NG.ER

GUARDS

AND

HARNESS rnVER.

DETAIL ' D"
MOUNTING DIPICNSIONS

PDP-8A MINIPROCESSOR
USERS MANUAL
EK-8A002-MM-002

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