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EK-M8207-TM-002

November 1982

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Document:	M8207 Microprocessor Technical Manual 198211
Order Number:	EK-M8207-TM
Revision:	002
Pages:	101
Original Filename:	EK-M8207-TM-002_M8207_Microprocessor_Technical_Manual_198211.pdf

OCR Text

EK-M8207-TM-002

M8207 Microprocessor
Technical Manual

mamaama

EK-M8207-TM-002

M8207 Microprocessor
Technical Manual

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, May 1979
2nd Edition (Rev), November, 1982

Copyright© 1979, 1982 by Digital Equipment Corporation
The material in this manual is for informational purposes and is subject
to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.
Printed in U.S.A.
This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS

DECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
IAS

CONTENTS
Page
PREFACE
CHAPTER I

INTRODUCTION

I.I

PURPOSE ......................................................................................................... 1-1
DESCRIPTION ................................................................................................ 1-1
M8207 BASIC CONTROLLING ELEMENTS ................................................ 1-2
MAJOR FUNCTIONAL AREAS .................................................................... 1-2
MICROPROCESSOR FEATURES ................................................................. 1-5

1.2
1.3
1.4
1.5
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.9. I
2. 9 .2
2.10
2.11
2.12
2.13
2.14

TECHNICAL DESCRIPTION
SCOPE .............................................................................................................. 2-1
TIMING ........................................................................................................... 2-1
CONTROL ROM AND INSTRUCTION REGISTER .................................... 2-8
SOURCE ROM AND DATA MULTIPLEXER .............................................. 2-9
ARITHMETIC LOGIC UNIT, SCRATCHPAD, AND
FUNCTION ROM ........................................................................................... 2-9
MULTIPORT RAM ....................................................................................... 2-12
DATA MEMORY .......................................................................................... 2-14
PROGRAM COUNTER ................................................................................ 2-14
NPR AND MISCELLANEOUS REGISTERS ............................................... 2-16
Microprocessor NPR Control Register ........................................................ 2-16
Microprocessor Miscellaneous Register ....................................................... 2-19
BERG PORT .................................................................................................. 2-20
BRANCH CONTROL .................................................................................... 2-21
BRANCH REGISTER ................................................................................... 2-23
DESTINATION ROM ................................................................................... 2-23
CONTROL AND STATUS REGISTERS ...................................................... 2-23

CHAPTER 3

SERVICE

3.1
3.2
3.2. l
3.2.2
3.3
3.4
3.5
3.6
3.7

SCOPE .............................................................................................................. 3-1
MAINTENANCE PHILOSOPHY ................................................................... 3-1
Preventive Maintenance ................................................................................ 3-1
Corrective Maintenance ................................................................................ 3-1
MICROPROCESSOR USE WITH LINE UNIT .............................................. 3-2
LINE UNIT PORT CABLE CONSIDERATION ............................................. 3-2
M8207 LINE UNIT PORT ................................................................................ 3-2
MIC RO DIAGNOSTICS .................................................................................. 3-2
ROM REPLACEMENT ................................................................................... 3-3

APPENDIX A
APPENDIX B

MICRODIAGNOSTIC TESTS
INTEGRATED CIRCUIT DESCRIPTIONS

APPENDIX C

M8207 MICROPROCESSOR JUMPER CONFIGURATION
111

CONTENTS (Cont)
GLOSSARY

INDEX

FIGURES
Figure No.
1-1
2-1

2-2
2-3
2-4

2-5
2-6

2-7
2-8
2-9

2-10
2-11
2-12

2-13
2-14
2-15

3-1
C-1

Title

Page

Microprocessor Simplified Block Diagram ......................................................... 1-3
Microprocessor .................................................................................................. 2-2
System Clock ...................................................................................................... 2-5
Main Timing Chain ............................................................................................ 2-7
Control ROM, Maintenance and Instruction Registers ....................................... 2-8
Source ROM and DMUX ................................................................................ 2-10
ALU, Scratchpad, and Function ROM ............................................................. 2-11
M ultiport RAM ............................................................................................... 2-13
Data Memory ................................................................................................... 2-15
Program Counter ............................................................................................. 2-15
Interrupt and NPR Control .............................................................................. 2-17
Miscellaneous Registers .................................................................................... 2-18
Timing Through BERG Port ............................................................................ 2-21
Branch Control Logic ....................................................................................... 2-22
Branch Register ................................................................................................ 2-24
Destination ROM ............................................................................................ 2-25
Extract of M8207 Module Component Layout ................................................... 3-4
M8207 Microprocessor Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

TABLES
Table No.
1-1

2-1
3-1

C-1

. Title

Page

Microprocessor Features .................................................................................... 1-6
DMUX Select lnput ........................................................................................... 2-9
Chip Address Range ........................................................................................... 3-3
M8207 Jumper Chart ................................................. C-1

PREFACE

The M8207 Technical Manual describes the hardware portion of the processor operation. The
information presented consists of a brief discussion of the purpose and features of the M8207, a technical
description of circuit operation which includes key timing functions, and module level diagnostics.
Appendix A contains Microdiagnostic Tests, Appendix B contains Integrated Circuit Descriptions, and
Appendix C contains the M8207 microprocessor jumper configurations. A Glossary and an Index are
also provided.
The following documents provide supplementary information.

•

M8207 Print Set (D-CS-M8207-0-0)

•

M8203 Technical Manual (EK-M8203-TM-001)

CHAPTER 1
INTRODUCTION

I.I PURPOSE
The M8207, a Direct Memory Access (DMA) device, is a UNIBUS compatible, general purpose
microprocessor with Read Only Memory (ROM) control storage. Working as a parallel Input/Output
(1/0) processor, the M8207 is used primarily to reduce 1/0 load on the Central Processing Unit
(CPU), and therefore, functions more like a data handler than a data processor.
1.2 DESCRIPTION
The M8207 microprocessor is implemented on a single hex multilayer board and will operate in most
hex SPC slots of a UNIBUS (DDl 1-B backplane cannot be used). The only power requirement is +5
Vdc.
The functions performed by the M8207 are determined by the microprogram contained in its instruction memory as specified by the microcode stored in the ROMs.
The architecture is based on a 16-bit instruction set. The M8207 cannot modify its own instruction
area.
All communications between the microprocessor and external UNIBUS devices are accomplished
through a Multiport Random Access Memory (MP RAM). An 8-bit port (BERG Port) allows the
microprocessor to communicate with a line unit or other device without use of the UNIBUS.
M8207 features are outlined below.
•

Instructions - Located in 2-K by 16-bit ROM
(increase to 6K in 2K increments)
Length = 16-bits
Time = 180 ns minimum
except Branch True = 240 ns
MP RAM Access ;;i. 210 ns

•

Programming - ROMs perform an appropriate task

•

Data Memory - 4K- by 8-bits

•

Scratchpad - 16- by 8-bits

•

Data Paths - 8-bits wide

•

Non-Processor Request Address - 18-bits

•

Interrupt Vector - 2 (XXO and XX4)

•

Control and Status Register defined by the hardware - 1 byte
1-1

•

Control and Status Registers defined by microcode - 7 bytes

•

Arithmetic Logic Unit Functions - 16

•

Multiple Transfer per Non-Processor Request

•

Program Timer - 1 millisecond

•

UNIBUS Transfer - byte or word

•

Read Program Counter and Memory Address Register

•

Assert AC LO is jumper selectable

•

BERG Port is compatible with M8200 and M8204

1.3 M8207 BASIC CONTROLLING ELEMENTS
A simplified block diagram of the M8207 is shown in Figure 1-1. The block diagram identifies the
basic controlling elements of the M8207 and shows the functional location of the microprocessor
between the UNIBUS and its 1/0 Port. The M8207 I/OBERG Port interfaces with a line unit through
a one foot cable.
The M8207 interfaces with the UNIBUS and performs DMA operations using Non-Processor
Requests (NPRs) and interrupts (Bus Requests - BRs). Communication between CPU and the microprocessor's UNIBUS Control and Status Registers (CSRs) is done through Data In (DATI) transactions for reading and Data Out (DA TO) or Data Out Byte (DA TOB) transactions for writing.
1.4 MAJOR FUNCTIONAL AREAS
The major functional areas of the M8207 Microprocessor are:
Main Memory (MEM) and Memory Address Register (MAR)
The M EM is the M8207 data storage area consisting of a 4096 by 8-bit RAM. This area cannot be used
for instruction storage nor can the stored data be executed as an instruction. The MEM cannot be
accessed directly by the CPU.
The MAR is set up by the microprocessor to address the MEM.
Branch Register (BRG)
The BRG is an 8-bit register used as a temporary data register for branch determination and for a
rotate right operation. It has three modes of operation: load, shift right, and hold. Input data comes
from the Buffered Arithmetic Logic Unit (BALU). During a right shift, only the BRGs most significant bit (bit 7) is sourced from BALU bit 0. Output data goes to the B input of the ALU via the Data
Multiplexer (DMUX).
Program Counter (PC)
The PC is a 14-bit counter that can be parallel loaded from the ALU for the lower eight bits during a
branch instruction, when the branch is true. The upper six bits are loaded from two sources: from the
Program Counter Register (PCR - OUTBUS* 13) on branch condition 0, or, on branch conditions 1
through 7, from bits 11 and 12 of the branch instruction for the page bits. The field bits are simply
rewritten from the PC. The branch not true and the move instruction increment the PC. The output of
the PC controls the address of the Control ROM directly.

1-2

UNIBUS

~ SROM}

SELECT

DROM

FROM

14-

µP MISC

14-

MAR
BAG
CONTROL

14-

NPR
CONTROL

I+-

ALU
FUNCTION

14- RAM

ADDA

DATA

MULTIPORT.

,........., DMUX

1 MAR ]

'4--

---

14--

MEM

BAG
~

SP
INSTRUCTION
REGISTER

I
CROM
~

INST
REG

1
BRANCH
CONTROL

PROGRAM
COUNTER

ALU

TO T60

!+-BAG

t 1

l+--C+Z

f4-

1---

BALU

•

T120

DATA
OUT

SYSTEM CLK

CROM

•

DATA
IN

BERG DATA PORT

1/0 PORT
MK-0888

Figure 1-1

Microprocessor Simplified Block Diagram

1-3

Control ROM (CROM), Instruction Register (IR), and Maintenance Instruction Register (MIR)
The M8207 uses up to a 6K- by 16-bit array of RO Ms for the instruction memory. The CROM can be
configured for 2K, 4K, or 6K with the 23XXXF4 PROM. The CROMs are addressed by the PC
during execution of the previous instruction. At time state zero, the output of the RO Ms are clocked
into the IR. The outputs of the ROMs are wire-ORed with the outputs of the MIR. The MIR is used
for loading a single microinstruction from the CPU (typically for maintenance purposes). Selection
between the MIR and the ROMs is done by CSR 0, bit 9 (ROMI). When bit 9 is set, the MIR is
selected. The MIR is loaded every time CSR 6 is loaded.

Data Multiplexer (DMUX) and Source ROM (SROM)
The DMUX is an 8-bit wide, 8-to-l line multiplexer. Its 8-bit output goes to the B input of the ALU.
Input selection for the DMUX is controlled by the SROM which is a 32- by 8-bit ROM. The SROM
also determines if a move instruction is to be executed.

Scratchpad Memory (SP) and Addressing Multiplexer
The SP is a 16- by 8-bit read/write memory that is used for temporary storage of data. An operand can
be presented to the A input of the ALU only through the SP. Scratchpad addressing is done through a
multiplexer. During normal operation, the addressing is controlled by the lower four bits of the
CROM. During an output transfer to the destination field OUT or OUT* registers, SP address 0000 is
automatically presented to the A input of the ALU.

Arithmetic Logic Unit (ALU) and Function ROM (FROM)
The ALU allows the microprocessor to perform arithmetic and logic operations on its A and B inputs.
The FROM, which is a 32- by 8-bit ROM, controls up to 16 functions to be performed by the ALU.
The carry output (C bit) of the ALU is connected to a flip-flop to store the carry indication if it occurs
during a move, or if it is forced by the FROM.
The AB output (Z bit) of the ALU is connected to a flip-flop to store the indication of equality of the A
and B inputs of the ALU if it occurs during a move instruction.

Multiport RAM (MP RAM) and Associated Logic
The Multiport RAM is a RAM that contains all the M8207 status registers except four: NPR Control,
Miscellaneous, PC, and MAR registers. The Multiport RAM has two ports (A and B) that can be
accessed simultaneously for a read operation; however, only the A port can be written into. The
associated logic consists of read/write control and addressing multiplexers which allow access to the
Multiport RAM by the microprocessor and the CPU. The Multiport RAM contains the CSRs that are
accessible by both the M8207 and the CPU program. It also contains the NPR buffer pointers and
NPR data that are accessible only by the M8207.
Microprocessor registers 0 through 7 of OUT /!BUS and OUT* /!BUS*, and CSR bytes 0 through 7
arc implemented in the MP RAM.
NOTE
A write to CSR byte 1 sets and clears bits in internal
controlling logic and MP RAM. A read from CSR 1
reads the RAM only.

1-4

System Clock
The clock provides clock pulses for the microprocessor. It generates a series of three nonoverlapping
60 ns time pulses for a time interval of 180 ns for branch instructions, condition not true, and move
instructions that do not access the Multiport RAM. The branch true instruction delays T60 by 60 ns
for an instruction time of 240 ns. The move instruction that accesses the Multiport RAM adds a
minimum of 30 ns to the instruction time if the Multi port RAM is not being accessed by the processor.
The 30 ns is extended for a processor write or an NPR in progress; the system clock is held up until the
transfer is complete.

Non-Processor Request (NPR) and Control Logic
The control logic allows the microprocessor to initiate an NPR under microprogram control and
assume UNIBUS mastership so that it can transfer data to or from the CPU memory. The not last
transfer bit can be used to retain bus mastership for multiple OMA transfers.

Interrupt Control Logic
This logic allows the microprocessor to interrupt the CPU and cause vectoring to either of two locations in the floating vector address space. The vector address is switch selectable and occupies two
consecutive vector locations: XXO and XX4. The M8207 interrupt priority is plug selectable for level 4,
5, 6, or 7; however, it is normally shipped as a level 5 device.

Address Selection Logic
This logic consists of switches to specify the microprocessor device address plus logic to decode this
address. Address selection logic also decodes the selected register and the type of UNIBUS transaction
requested. Using these factors, the logic generates the appropriate control signals to implement a read
or write operation as directed by the UNIBUS control lines.

Destination R 0 M (DR 0 M) and D Decode
DROM and D Decode are driven by the destination field of the microinstruction, and control the
destination location of data in a move instruction.

NPR Control Register (Register 10) and Microprocessor Miscellaneous Register (Register 11)
These registers are used for M8207 general control and status. The bit functions are described in
Chapter 2.

Branch Control
The branch control multiplexer is driven directly by the instruction register output bits CROM
< 10:8>. It is used for determining branch conditions.

1.5 MICROPROCESSOR FEATURES
Features of the M 8207 provided in Paragraph 1.2 are compared with features of other microprocessors
in Table 1-l.

1-5

Table 1-1

(

Microprocessor Features
(M8204)
KMCll-A

(M8206)*

Function

M8200

M8207

Instruction
Time

300 ns min
except
MP· RAM
330 ns

180 ns min
except
Branch true
240 ns &
MP RAM
210 ns

300 ns min
except
MP RAM
330 ns

180 ns min
except
Branch true
240 ns &
MP RAM
210 ns

Instruction
Memory

lK X 16

6K X 16

lK X 16

4K X 16

Data Memory

256 x 8

4K X 8

lK X 8

4K X 8

Instructions
in ROM

yes

Instructions
inRAM

yes

Multiple
Transfer per
NPR

yes

Program
Timer

1 ms

50 µs

50µs

Load PC

yes

Read PC
(Host)

yes

Read MAR

yes

Assert AC LO

yes

selectable

yes

selectable

Load MAR HI

yes

Latch of
IBUS* 12-15
in Maintenance

yes

IBUS* 12-15

yes

LU Stop CLK

yes

Power

+5 V@7 A

*M8206 is a CSS special programming module for the M8207.

1-6

CHAPTER 2
TECHNICAL DESCRIPTION

2.1 SCOPE
The technical description is addressed to circuit operation on a functional level. Logic block diagrams
are included to supplement the text, and reference to the M8207 Print Set is made throughout the
chapter. The block diagram of Figure 2-1(Sheet1) shows the major interconnections between the basic
controlling elements of the microprocessor. A map of the Control and Status Registers (CSRs), is
provided in Figure 2-1 (Sheets 2 and 3). Detailed descriptions of the area represented in Figure 2-1
constitute the following sections of this chapter.

NOTE
Ox references in the text are based on the signal map
rather than the actual sheet numbers of the Print Set.
2.2 TIMING (Figure 2-2)
The basic timing is generated by a 33.33 MHz crystal that can be disabled by removing jumper WI to
accommodate automated circuit board testers. The crystal output provides the clock input to the
MSYNC flip-flop (016 of Print Set) and buffered clock inputs, via a 74S240 inverter, to the WAIT
SYNC, SYSTEM CLOCK (SYS CLK), and DELAY flip-flops.

The SYS CLK flip-flop:
•

is used to generate the 60 ns timing pulses for the timing chain.

•

is only held clear when the WAIT SYNC flip-flop is clear or in a wait state.

•

is held set during a master clear.

•

clear and K inputs are tied to + 3 volts.

•

J input comes from the output of the WAIT SYNC flip-flop.

•

output is used to drive the clocks of the RUN SYNC, TO, T60, and Tl20 flip-flops.

The WAIT SYNC flip-flop:
•

is used to eliminate timing problems when the wait signal goes away too close to the clocking
edge of the system clock.

2-1

1~ 141" 131

rcROM<15:13>
CROM

47.

SOURCE
SROM
S DECODE

<15:13>

1--MOV INST
1--READ LU

NPR
8 CONTROL

!--WRITE SP
1--WRITEMEM
1--SO
1--SI
1-- MAR INC
1-- LO MAR HI
1-- LO MAR LO

DESTINATION
D ROM
D DECODE

CROM
14,
<7:4>
CROM
<10:8>
CON D

ARITHMETIC
FUNCTION
F
ROM

...--

ALU FUNC
1-- ENC IN
1-- FORCE C IN
I-- CKC

8 LO BYTE
<7:0>

D MUX

~1K

BRANCH
INS!RU

r
c
z. ~

BRANCH CONTROL h
D2'

ALWAYS
CHANGE FIELD
RG 0
BRG 1
BRG 4
BRG 7

If-I-

t-2K

If--

~3K

I-

1--

I-

1-4K

CROM
11.12'

Figure 2-l Microprocessor (Sheet l of 3)
a. Interconnection Between Controlling
Elements

2-2

DATA
D10

~
-

YPLU
T120

U DATA

--1

ROM
<15: O>

D11

MAR l--T180
D1 2

8 DATA

LO L0,
LD HI.

BRG
D12 l--T12'0

CROM
6K X 16
DIVIDED
INTO 6 1 K
FIELDS.
EACH
FIELD HAS
4 PAGES

8 LU IBUS < 7:0 >T
8 CROM<7:0>
TIM-

D7
(TRISTATE DMUX SIG)

12 BALU<7:0>

MAR LATCH

U DATA
DMUX<7:0>
IBUS.--el
12+13
T1204

PCMUX 14-~HANGE
FIELD
02
2
JT412pc10.11
PCR
~11~
< 13:12 >

8
~

z
D8
T120--I

ALU

FORCE
c
D8

ENC

c
DB

ALU<7:0>

OUT*13
PCR
LO DATA 7aALU<6:0>
D13

8
8

]

BERG DATA
PORT
DATA CROM DATA
OUT <7:0> IN

SCRATCH
PAD
ADD
DATA h
.......
16X8
l--T180
OUT
D8
j_8
A
CIN
DB

rCARRY

l--T180
04 i--IBUS* 14+15

CROM <3:0>

PC LATCH

14
PC<13:07>

r-la slG 8
1

ADD D5.6
tPC<10:0>

MAIN MEM
4KX8

8 BRG<7:0>

MAINTENANCE
INSTRUCTION ROM
05,6

~fSRLD
NPR IN

INC

ROM 3
SEL
01, PROGRAM
2 COUNTER CLK !--T60
DATA
LO
BRANCH

D3 l--T180

I=I-

t-5K
t-

.......--1 A

MULTI
PORT
RAM
CSR
NPR

8 MEM<7:0>

t--

12ADD<11:0>

ROM <15:0>5..._; 16 BITS

~OK

NPR CONTROL
D3 j4-T180

<15:8>
8 HI BYTE

!--CLEAR
INSTRUCTION
REG D5, 6cLK !--TO

I-

UNIBUS

µP MISC
D13 l--T180

1-- BRANCH FIELD

CROM
<12:9>

ADD DATA
SMISC

BALU

8
CLK T120
DB

BALU<7:0>L

33,33·
osc

Tr r6o IT120 T1so
t 11

CLK
r-ff-·
µP LDMP

SYSTEM
CLK

~ WRITE

f--

~ READ

014
MK·0692

UNIBUS CONTROL AND STATUS REGISTERS

RUN

MCLR

(SEE NOTE 1) -<
(SHEET 3 OF 3)

ROl\ll

ROM 0 = 0

12
STEP
LU

LU
ROM
0
LOOP

ROM
1

STEP
µP

l 6 l 5 l 4 l 3 l 2l 1l 0

CSR ADDRESS

CSR BYTE 0

76XXXO

SR BYTE 3

CSR BYTE 2

CSR BYTE 5

CSR BYTE4

76XXX2
76XXX4

CRS BYTE 7

CSR BYTE6

76XXX6

ROM I= 0

CSR 7+6 (W/R)

ROM 0 = 1

ROM 1

CROM DATA

ROM 0 = 1 ROM 1 = 1 MAINTENANCE INSTRUCTION (W/R}

6
MK-0691

Figure 2-1 Microprocessor (Sheet 2 of 3)
b. UNIBUS Control and Status Registers

2-3

µP & LU CONTROL & STATUS REGISTERS

OUT*/IBUS*

OUT/IBUS

l 6 l 5 l 4 l 3 l 2 l 1 l 0

CSR BYTE 0
RUN

STEP
LU

MCLR

LU
LOOP

.. JM

ROM
1

STEP
µP

CSR BYTE 2
UNIBUS
CS Rs

µP NPR {
CONTROL
µP MISC {

CSR BYTE 3

BYTE
XFER
(CO)
BUS
RO

PROGRAM
COUNTER
(SEE NOTE 2)
MEMORY
ADDRESS
REGISTER

UNDEFINED {

MAR

10
VECT
ORXX4

l 3l

l 0

IN DATA LB

IN DATA HB

OUT DATA LB

OUT DATA HB

IN BA 7:0

IN BA 15:8

OUT BA 7:0

CSR BYTE 6

OUT BA 15:8

PGM
CLK

OUT
BA
17

Wo
IN
BA
16
OUT
BA
16

NOT
LAST
XFER

NPR
RQ

AC
LO

NON
EX
MEM

11
BERG PORT
DEVICE
REGISTERS
(SEE NOTE 4)

*PC13+-8
MAR 7 +- 0

CSR BYTE 4

PC 7 +- 0

CSR BYTE 5

CSR BYTE 7
IN
MAR OUT
NPR
BA
8
(C1)
17
R/W

µP NPR
DATA & ADDRESS
REGISTER
(SEE NOTE 3)

µP DEVICE
ADDRESS
(OCTAL)

12
13
14
15
16
17

MAR 12 +- 8

SEE NOTE 5

YC OPTION ONLY

NOTES
1.

UNIBUS CSRs ARE IN THE MULTIPORT RAM. BYTE 1 HAS A HARDWARE STATUS
REGISTER THAT IS ADDRESSABLE ONLY FROM THE ll!NIBUS. IF THE µP ADDRESSES
BYTE 1, IT WILL ONLY WAITE INTO THE RAM. ALL THE OTHER CSR BYTES ARE
DEFINED BY THE MICROCODE EXCEPT IN MAINTENANCE MODE.

IBUS* 12-15 REFLECT THE PROGRAM COUNTER FOR THE INSTRUCTION BEING EXECUTED AND THE MEMORY ADDRESS REGISTER FOR THE PREVIOUS INSTRUCTION.
OUT*13 IS THE PCR WHICH IS A SHADOW REGISTER. THE CONTENTS OF THE PCR
WILL BE TRANSFERRED TO THE PC ONLY ON A BRANCH (CHANGE FIELD).

NPR DATA AND BA REGISTERS ARE RAMs; HOWEVER. ADDRESS ASSIGNMENTS
ARE HARDWIRED AND CANNOT BE REDEFINED.

OPTIONAL - THESE REGISTERS ARE ONLY VALID IF EXTERNAL DEVICES ARE ATTACHED TO THE BERG PORT

OPTIONAL - YC ONLY FOR 22 BIT NPR ADDRESS

MK-0664

Figure 2-l Microprocessor (Sheet 3 of 3)
c. Microprocessor and Line Unit Control

2-4

S240

TO(O)

BTOL
T60(0)

TOH

D 16 r---R_U_N_S_T_E_P_L_----t D

74S74

74S112

74S112
t - - - t l ' N - - T120H

J
RUN
SYNC

T60

T120

0 t--~vvw-- T120L

TO(O)

T60(0)

PC CLK H

AND/OR CKT.
QUALIFYING
INPUTS
CROM BL
WRITE OUT H _ ___,,,..,.
BRANCH H
MP READ H

AND/OR
WRITE MP
BRANCH
READ MP
LU ADY

CROM BL
WRITE BOTH

(WAIT)

UNIBUS
WRITE L

T60(1)
MP READ H
B PORT BUSY L

T120H
µP LO MULTIPORT L

UNIBUS
CSR CNTR'L
74S74
D

-=
T120 L

MP READ
CYCL

MP
READ

-=
0

74S74

_ _ __.__ _ _ _ _ _ _ _ MP WRITE CYC H

D MP
WRITE

0 - - - 1 - - - - - - - - - - MP WRITE CYC L

0
REF 014 OF
M8207 PRINT SET

CLEAR L
MK-0693

Figure 2-2

System Clock

2-5

The RUN SYNC flip-flop:
•

is used to sync the transition of run or step to the system clock to eliminate race conditions.

•

is a 74S74 flip-flop whose data input is low true when either the run or step function is true.

•

is clocked clear to enable the start of the main timing chain.

Main Timing Chain (Figures 2-2 and 2-3)
Both high and low outputs of the RUN SYNC flip-flop go to TOs inputs. Once clocked clear, RUN
SYNC is latched clear until it is set by a negative OR on its preset side during time states TO and T60.
Data input to the RUN SYNC flip-flop must then be true low during T120 in order to reset RUN
SYNC for the next instruction.
The preset side of the time state flip-flops are tied to +3 volts. This ensures that all time states are not
true at the same time. The clear side of all time states are common to the CLEAR L signal from the
UNIBUS. The timing chain is cleared and restarted on a master clear or power up.
•

TO - TO is used to start an instruction. The high output from TO clocks the Instruction
Register (IR) and the line unit, or option, connected to the BERG Connector. Both outputs
from TO are input to T60 so that the next clock will generate the next time state.

•

T60 - T60 is clocked on the trailing edge of TO. TO is always 60 ns long. However, T60 is
delayed by a wait during a branch true or move instruction using the M ultiport RAM (line
unit WAIT L when the line unit is addressed and is not ready). The high output from T60 is
used to increment the Program Ornnter (PC) when branch is not true, and to generate the
wait pulse. During this time period, the instruction has been decoded, the arithmetic function has been executed, and execution of the instruction has started. Both outputs from T60
are input to T 120.

•

Tl20- The next clock clocks Tl20. The leading edge ofT120 is used to clock data out of the
Arithmetic Logic Unit (ALU). The source and arithmetic functions are complete at this
time; normally 120 ns from the beginning of the instruction. The trailing edge ofTl20 loads
all the registers and memories with data from the Buffered ALU (BALU). The exception is
the Multiport RAM which is loaded on the leading edge from the ALU.
During T 120, the RUN SYNC flip-flop is allowed to reset for the next instruction. Both the
leading and trailing edges of Tl 20 are actually used to load all registers and memories on the
board, except the PC. The PC is loaded by the DELAY flip-flop during a branch true, or
incremented by the leading edge of T60. Gating for the PC clock is done with a 74S51 (Dl4
of Print Set).

The wait for the timing chain is defined through a 74S64, which is a 4-2-3-2 input AND-OR gate. The
qualifying inputs are defined by the instruction and are qualified at the leading edge of T60. The four
qualifying conditions are:
•
•
•
•

Line unit not ready to be read
Branch true
Read to the Multiport RAM
Write to the Multiport RAM

The wait output is sync'd with the system clock through the WAIT SYNC flip-flop.

2-6

MOV EXCEPT MP+ BRANCH FLASE
0
60
120
10_0_ __
SYS CLK H

TOH

_j.__ LDIR

_,l CLK PC I....-----Tl 20 Hl~_______.fLo BALU~I_ __
T5 o H _ _ _ _

ALD REG FOR
'----~f'-MOV ONLY

T120 L

WAIT SYNC - - - - - - - - - - - - - - - - H
DELAY

L
BRANCH TRUE
120

SYS CLK H

TOH~ LD IR

..___ _ ____.I

T60 H

T120 H

l.._____________,

T120 L

WAIT SYNC

DELAY _ _ _ _ _ _ ____.KOLO PC
0

l~----

MOV MULTIPORT
60
120 150 180 210

SYSCLKH~~
TOH ---1'-LDIR
t - - - iL_____; ..,_._ _ _ _____,

T60H__GK~
T120 H

1 . . ._____. 5., s----f c8 ~:LU 1. . ._ __

T120 L

'----~t=LD AEG

WAIT SYNC
DELA y

REF 014 OF M8207
PRINT SET

~J
l?JJJ

----s~

I. . ___ __

l:EXTENDED DURING UNIBUS CYCLE
MK-0689

Figure 2-3

Main Timing Chain

2-7

2.3 CONTROL ROM (CROM) AND INSTRUCTION REGISTER (IR) (Figure 2-4)
CROM consists of up to six 2K- by 8-bit (82Sl91) high speed ROMs. The ROMs are broken up into
two groups of 2K each, whose address is controlled by the PC. The groups are selected and deselected
via three 74SOO gates (D2 of Print Set). These gates are driven by the high order bits of the PC and the
maintenance selection bit, CROM IN L, which is CSR 0 bit 9. When bit 9 is set, both sets of RO Ms are
disabled and the Maintenance Instruction Register (MIR) is selected, allowing an instruction to be
loaded in CSR 6.
When loaded, CSR 6 loads bytes 6 and 7 of the Multiport RAM (09 of Print Set) with data for the
microprocessor and loads the 16-bit MIR consisting of two 74S374 octal tristate D flip-flops (D5 and
D6 of Print Set). These flip-flops are selected during a maintenance instruction;
CROM and MIR outputs are wire-ORed to the IR; two 74SI75s are input by the lower eight bits
<7:0>, and a 74S374 octal D flip-flop is input by the upper eight bits < 15:8>. The low outputs of the
74Sl 75 are used by the BERG Port for address selection of LU IBUS and OUT registers.
The IR is clocked at the leading edge of TO; at the beginning of an instruction. The outputs of the IR
are used to control the microprocessor. They are decoded for the following via respective ROMs.
•

Type of instruction (Source ROM - SROM)

•

Function (Function ROM - FROM)

•

Destination (Destination ROM - DROM)

CROM outputs directed to the Data Multiplexer (DMUX) are used during maintenance to verify the
contents of the RO Ms.
TOH CLEAR L

MK-0689

C~L.,.,..K~C!loL.-.

UNIBUS
DATA
INTERFACE _D_<_1_5 :_o_>..... ~
(D11)

MAINT
REG.
2(74S374)

...

~--···-

<7:0>

i ... ..··
< 15:8>

LDWORD CROM
GL
IN L
OK
1K
PROGRAM
COUNTER
D1, 2

PC<10:0>
4K
5K

INSTR.
REG
2(74S175)

CROM<7:0>L

1(74S374)

CROM<15:B>H

CLK

CROM<7:0>H
}

(82S191)
TOH
GR.
1
CROM
GR.
6KX16 i------R_O_M_<_l5~:0~0_>_ _,. UNIBUS DATA INTERFACE
2
(D5.6)
(D11)
GR.
REF. 05, 06
3 CE
OF M8207
PRINT SET

CROM EN
(O+ 1 K)(2 +3KH4+5K)

Figure 2-4

MICROPROCESSOR
CONTROL

MK-0690

Control ROM, Maintenance, and Instruction Registers
2-8

2.4 SOURCE ROM (SROM) AND DATA MULTIPLEXER (DMUX) (Figure 2-5)
The DMUX consists of a tristate 8-to-1 multiplexer, and four octal tristate registers controlled by the
SROM and the Source Decoder. SROM is a 32- by 8-bit (23 I 20A I) ROM driven from instruction
register CROM bits 4, 7, 13, 14, and 15, which define the instruction and its source. SROM is always
enabled. Output bits 6, 7, and 8 are DMUX select inputs SO, SI, and S2 respectively.

Table 2-1
DMUXSelect
S2 St so

DMUX Select Input

Data Selected

Definition

(0)

CROM<7:0>H

Immediate branch and move instructions

(1)

LU IBUS<7:0> H

Reads all ones if nothing is connected to the BERG
Connector. There are IOg addresses provided, usually
from a MUX on the line unit

(2)

MEM<7:0>H

Location addressed by Memory Address Register

(3)

BRG<7:0>H

Single, 8-bit register used for shifting branch conditions

(4)

8 PORT<7:0>H

From Multiport RAM

(5)

8 PORT<15:8>H

IBUS and IBUS* registers for CSR and Non-Processor Request registers

(6)

NPR Control
Register

(See Paragraph 2.9)

(7)

Microprocessor
Miscellaneous
Register

Can only be accessed by the microprocessor (See Paragraph 2.9)

Disabling the DMUX and selecting individual octal registers is accomplished through a 74SI 38 decoder. The decoder monitors the source and instruction register lines. The 74LS374 octal registers are
clocked at the leading edge of T120. At this time the data in the registers are read from the PC and
Memory Address Register (MAR).
The outputs of the octal registers are wire-ORed with the outputs of the DMUX and provide the B
input to the ALU. Additional outputs from the SROM and Source Decoder are used by the timing and
branch logic for control of the microprocessor.
2.5 ARITHMETIC LOGIC UNIT (ALU), SCRATCHPAD (SP), AND FUNCTION ROM (FROM)
(Figure 2-6)
The ALU consists of two 74S 181 chips and performs arithmetic and logical operations on two designated operands; input A is the SP operand (scratchpad has 17 octal locations), and input B from the
DMUX is the Main Memory (MEM) or Branch Register (BRG) source operand for move and branch
instructions. A 5-bit function bus defines the type of operation to perform on the A and B operands
and is gated into the ALU from the FROM. The FROM is a 32- by 8-bit ROM whose address lines,
CROM 14, and <7:4> are from the IR.
2-9

ro~;------------------------------1

I PRINT SET

II
DMUX
8(74S251)

µP MISC REG

1 I 1 11

NPR CONTROL REG

1 I 1 Io

B PORT<15:8>H

B PORT<7:0>H

OCTAL REGISTERS
74LS374

PC<7:0>H

EN CLK

II
I

R
D

MAR

<7:0>H

EN CLK

1eus· 13L

<12:8>H

1eus· 14L

I
I

I
1
,
II
I

D
EN CLK

1eus· 15L

BINPUT
OF ALU

S2 S1 so

SOURCE DECODER

CROM 13H
CROM 14H

CROM 15H

1------'

74S138

SEL
A
B

000

CROM 4H

001

CROM 5H

010

CROM 6H

SEL

A
B

011
100

SROM 6
(23120A 1) - - - - - MOV INST H

101

1----....,. READ LU H

111

MAR

EN CLK

74S138

CROM 15. 14. 13, 7, 4

L---------------------------------J

1
01010

CROM<7:0>H

74LS374

CLK IBR H

I
Io
o Io I
o

LUIBUS<7:0>H

PC
< 13:8> H

1eus· 12L

o I 1 11

MEM<7:0>H

74LS374

B
INPUT

1 I 0 0 t----t-D_M_U_X_<-7:_0_>_H_.. ,,,,

BRG<7:0>H

74LS374

t DMUX <7:0> H

110

CROM 7

tDMUX =TRISTATE SIGNALS
(DMUX & OCTAL REGISTER
OUTPUTS WIRED ORI

000 =MOVE I
001 = MOVE IBUS
010 = MOV MEM
011 = MOVE BRG
100 = JMP I
101 = MOV IBUS*
110 = JMP MEM
111 = JMP BRG

REF D7 OF
M8207 PRINT SET
MK-0675

Figure 2-5

Source ROM and DMUX
2-10

+3 v
74S74
+5 V - - - - V ' - - - - - . - - - - - - - - - 4 0
·1 1----Z(1 )H

z
CLK ZH

CLEAR L
+3 v
74S74

...-----no
WRITE SPL

---C(1)H

c
CLOCK CH C

CLEAR L

BALU
<7:0> (1)L

COUT

T120

2(74S189)
AO A1 A2 A3

DATA BUS

ALU
F

DMUX<7:0>H

2(74S181)

M S3 S2 S1 SO

74LS157

ALU<7:0>H

CIN

<7:0>(1)H
CROM

BALU

MUX

<3:0>H

BALU
(74S175 < 7 :0>( 1)L
CLK CLR

SO STB
WRITE OUT H

CLEAR L
MP RAM
PC

23121A 1

FROM

CROM < 7:4 >, 14

INSTRUCTION
REGISTER

(32

·o FUNCTION

x 8)
DB CLK C

BUS
FORCE C
ENC

7450

REF 08
OF M8207
PRINT SET.
MK-0661

Figure 2-6 ALU, Scratchpad, and Function ROM

2-11

ALU functions are not allowed when bits 4 through 7 are used for address or data. The ALU then
selects the B inputs only. The results of the operations performed by the ALU are sent to: (1) the
BALU, (2) the DMUX for the Multiport RAM, and (3) the lower eight bits of the PC for branch
instructions.
The BALU (two 74S175 quad D flip-flops with both high and low outputs) clocks data out of the ALU
at T120. The output data from the BALU is clocked at Tl80 and provides input to the data memory,
SP, BRG, Non-Processor Request (NPR) control, miscellaneous register, Program Counter Register
(PCR), and the BERG Port. The BALU is clocked directly from the T120 flip-flop, and its clear input
is generated by master clear or initialize.
The ALU chips are configured for a ripple carry that is clocked into flip-flop C, which is used in
branch operations. The C flipflop is clocked by a 74Sl57 MUX, which provides the clock only on a
move instruction and when the FROM output CK C H is true. This occurs at T120.
The AB output from the ALU is asserted when the ALU output data bus contains all ones. The AB
outputs from each chip are wire-ORed and input to the Z flip-flop. The Z flip-flop is clocked at T120
on every move instruction. Both C and Z flip-flops are clocked from the same 74Sl57 MUX and
cleared by master clear or initialize.
The ALU A operand is always generated at the SP (two 74Sl89 RAMs). The SP is addressed by
CROM bits 0 to 3 via a 74LS157 MUX during all instructions except OUT and OUT*, when the SP
address is zero.
WRITE OUT H is asserted during an OUT or OUT* operation. The SP is inverted so the low side of
the BALU is used for data inputs (the RAM chips are always enabled). The SP is clocked from a
74Sl58 decoder MUX (Dl of Print Set), which selects the output of the DROM on a move instruction
by loading the SP at T180.
2.6 MULTIPORT RAM (Figure 2-7)
The Multiport RAM (82Sl 12 chips) is a 16- by 4-bit random access memory that is the main interface
between the processor and microprocessor. All data transferred from NPRs or through CSRs go
through the Multiport RAM. Data can only be written through Port A, but can be read from ports A
and B simultaneously. The read from ports A and Bis disabled during the write time to avoid reading
invalid data.

Addressing and data transfer is accomplished through 74LS157 Multiplexers. The microprocessor is
able to read and write the registers. The NPR logic reads and writes half of the Multiport RAM and
the Central Processing Unit (CPU) reads the other half.
Port A addressing goes through two levels of multiplexing. The first level is for control by the microprocessor or second multiplexer. The second level is for control by the CSR or NPR logic. This is
acomplished by two 74LSl57 MUXs. Selection control for the first MUX (MP RAM A ADDRS) is
via the microprocessor MP WRITE CYCLE H signal (014 of Print Set). The signal switches the
address to the lower three bits of the instruction (CROM <2:0>), and selects the data address to be
written from the ALU via the Multiport DMUX.

2-12

,-----OUT NPR

- ----,
CROM<2:0>

74LS157
A
UNIBUS
ADAS

74LS157
MP RAM

AA DRS

ADAS AO. A 1 LB. HB W

A1.A2 LDLB,HB

HPR MASTER L <CSR SEL>

(SEL ALU DATA)

UNIBUS
DATA
TRANSCEIVERS

A PORT< 15:0>H

4(74LS157)

MP RAM
DATA

MP DATA<15:0>H

I
I

----

_ _J

MP WRITE CYC H

DMUX&
UNIBUSADRS
TRANSCEIVERS

B PORT< 15:0>H

WRITE
CLK

ALU<7:0>H

LU MULTIPOAT L

MPWCYC H

D<15:0>H

I
I
I
I

MUX

LB WAITE L
HB WRITE L

MP RAM
A PORT
WRITE
DATA
INPUT

(16X4-BIT RAM)
4(82S112)

A PORT
R/WADDRS
.INPUT

B PORT
READ ADDRS
INPUT
18 19 20

OUT *L
MP WRITE CYCL
NPR MASTER

MP ADAS Al H
MPADRS AO H

74LS157
CROM 15H
CROM 6 H

-------t~B

CROM 5H
OUT NPR (Cl) H

MP RAM
B ADAS

B PORT BUSY L

REF D10
OF M8207
PRINT SET

STB

UNIBUS WRITE L

MK-0695

Figure 2-7

Multiport RAM

2-13

Control of the A Port address by the second MUX (UNIBUS ADRS MP RAM) occurs when the
microprocessor is not attempting to write to the Multiport RAM. The UNIBUS ADRS MP RAM
MUX is controlled by the NPR MASTER L signal. When the M8207 is bus master, bytes 0 + I or
bytes 2 + 3 are always addressed (A input is selected). RAM location is a function of direction. Bytes 0
+ I are selected for a data transfer in; bytes 2 + 3 are selected for a data transfer out. CSR selection
comes directly from the UNIBUS address transceivers. When NPR MASTER Lis high, the B input is
selected, allowing the UNIBUS address bits to control Multiport RAM address selection. Port A data
input is selected by four 74LS157 MUXs. Data is gated from the UNIBUS transceivers except when
the microprocessor MP WRITE CYCLE H signal is true, in which case the data comes from the ALU.
Port B address is selected by one 74LSI 57 M UX. CROM bits 5, 6 and 15 from the IR determine the B
address. The exception is when the UNIBUS WRITE L select input to the MUX selects OUT NPR
(Cl)H which is used for the NPR address, Multiport RAM address bytes 4 + 5 are selected for an NPR
read, and address bytes 6 + 7 are selected for an NPR write.
Port A output goes to the UNIBUS data transceivers (DI I of Print Set). Port B output goes to the
DMUX (D7 of Print Set) and to the UNIBUS address transceivers (D12 of Print Set). The write signal
to the Multiport RAM comes from a three input OR gate under three conditions:
•
•
•

NPR Load Multiport
Microprocessor Load Multiport
CSR Load Multiport

Its output is ANDed with the byte select for the byte to be written; LB WRITE L for bits 7-0; HB
WRITE L for bits 15-8.
2.7 DATA MEMORY (Figure 2-8)
The data memory, a 4K- by 8-bit array of 2147-3 chips, can only be accessed by the microprocessor for
data storage. The data memory is completely separate from the instruction memory. The memory is
addressed from the 12-bit MAR. A move instruction loads the MAR, high or low bytes, and also
increments the MAR via CROM bits 11 and 12 of the move instruction, which are input to the
Destination ROM. DROM controls both loading and incrementing of the MAR and data memory.
The MAR is clocked on every move instruction and cleared low on master clear and initialize. The
contents of the MAR can be read through IBUS* registers 14 and 15, with page and field overflow on
bits 5 and 6 of IBUS* register 10. IBUS* registers 14 and 15, represent the MAR for the previous
instruction (see Figure 2-1, Sheet 3 of 3). Data memory is loaded from the BALU at time 180. The
write pulse comes from a 74S158 (DI of Print Set) on a move instruction when the DROM output is
true. Data memory output is sent to the DMUX (D7 of Print Set).
2.8 PROGRAM COUNTER (PC) (Figure 2-9)
The PC is a 14-bit counter that is incremented at time 60 unless the instruction is a true branch. In this
case, the PC is parallel loaded 120 ns from the beginning of the instruction. The lower eight bits of the
PC are loaded from the ALU; the next four bits are loaded through a 74LSl57 MUX, and the upper
two bits are loaded from the Program Counter Register (PCR), bits 4 and 5.
•

If branch condition zero exists - the M UX selects PCR outputs < 13 :8 > H

•

If branch conditions I through 7 exist - CROM bits 11 and 12 of the IR are used for the
paging bits, and the field bits are reloaded from the PC.

The PCR is OUT* register 13. It contains the upper six bits to be loaded (PCR < 13:8 >H) into the PC
on branch condition 0. This provides extra field addressing with future expansion capability.
2-14

CROM
8-12H

MAIN MEMORY
4K X 8 ARRAY

MAR
LO HI
DROM
(23202A 1)

MAR
t-----3193 S 1S) MAR<11:0>H
LO LO

812147 · 3 )

OUT MEM<7:0>H

DMUX

INC
(01)

(01. 02)
BALU<7:0>(1)H
CLEAR L

Ls-

WRITE MEM L

REF 03 OF
M8207 PRINT SET
MK-0694

Figure 2-8

Data Memory

BRANCH INST L

74S151
BRANCH H

BRG4H
BAG 7 H
BRGOH
BAG 1 H

BRANCH
MUX
BRANCH L

Z(1)H
C(1)H
INST
REG
CROM<10:8>H
BRANCH COND

PC<7:0>H

ALU<7:0>H
PC

74S157
CROM 11.12 H

MUX

PCR4+5

PCR

PC CLK H

so
BRANCH FIELD H

CROM EN 2+3K

CLEAR L
MASTER
CLEAR
(INITIALIZE)

CLK

CROM IN L
PC 12

CLR

CROM
EN
GATES

CROM EN0+1K
CROM EN 4+5K
CROM
SELECT LINES

REFD1.D2
OF M8207
PRINT SET
MK-0663

Figure 2-9

Program Counter

2-15

The contents of the PC can be read by the program through INBUS* registers 12 and l3 for the
instruction that is being executed. The PC is cleared with CLEAR L during a master clear and bus
initialization. Branch control is accomplished through an 8-to-1 (74S15l) multiplexer driven by
CROM bits 8 thrnugh 10 from the IR. The branch MUX is only enabled during branch instructions.
2.9 NPR AND MISCELLANEOUS REGISTERS (Figures 2-10 and 2-11)
The microprocessor has two registers that are used for microprocessor hardware control and status,
INBUS* /OUT* 10 and 11. Register 10 controls the NPR circuitry and starts the NPR timing. Register
11 is a status register. The following discussion describes the bits and functions of both registers.
NOTE
Circled numerics are used in the following discussion
to associate those areas of text with corresponding
areas in Figures 2-10 and 2-11.
2.9.1 Microprocessor NPR Control Register (Register 10)
1

BYTE
XFER MAR
(CO)

MAR

OUT
NPR

(C1)

. 2

~BITS

IN
IN NOT
LAST NPR
BA17 BA16 XFER REQ
MK-0662

•

Bit 0 is the NPR bit and can only be written to a 1 by the microprocessor; clearing is done by
the hardware. The NPR flip-flop (Fig. 2-1 l G) ) is set through a NANO gate, via the flipflop's preset input when the program writes a 1 to bit 0. This starts the NPR cycle through
NPR control chip (Fig. 2-IO G) ), which generates BUS NPR, then waits for the request to
be granted via NPG IN. The microprocessor then bec~es bus master and the NPR MASTER H signal triggers the START one-shot (Fig. 2-10 UJ ), a 200 ns timer. The 200 ns time
period allows: (l) the multiplexers to select the address and data from the Multiport RAM,
(2) propagation through the Multiport RAM, the bus transceivers, and bus delays, and (3) a
75 ns deskew time for the signals on the bus.

The trailing edge of th~OO ns pulse from the start timer triggers the second timer CK l - a
75 ns ~er (Fig. 2-10 ~ ). The leading edge of CK 1 clocks the NPR DONE flip-flop (Fig.
2-10 '-.2.J ). The data input is clear at this time. The trailing edge of CKl clocks the OMSYNC flip-flop (Fig. 2-10..16) ), which generates master sync on the bus and enables CK2 a 75 ns timer (Fig. 2-10 (]}"'). CK2 is triggered after slave sync is returned and presets the
NPR DONE flip-flop.
The leading edge of CK2 does nothing; the trailing edge clocks the NPR LOAD MULTIPORT flip-flop (Fig. 2-10 @ ) during a transfer in and retriggers CKl. The leading edge
of CKl now clocks NPR DONE which is set and the data input is true, keeping NPR
DONE in a set state. The trailing edge of CKI clears OMSYN and retriggers CK2 which
clears NPR LOAD MULTIPORT and retriggers CKI. CKI clears NPR DONE which
clocks the NPR RQ flip-flop whose input is grounded.
Clearing the NPR RQ flip-flop clears the NPR control unless this is n~ the last transfer, in
which case NOT LAST TRANSFER signal is set (Figu~ 2-10, 2-11 \.2J ). When OMSYN
is set, an 18 microsecond timer is started (Fig. 2-10 Q9J ). If this timer times out before
slave sync is returned, the TIME OUT flip-flop is set (Fig.2-10 @ ). This clears the NPR
control circuitry as if slave sync had been returned, and presets a flip-flop (Fig. 2-11 @ )
that generates a signal line called NON EX MEM H gated to the DMUX.
2-16

NPR TIMING CHAIN

+5 v

+5V
NPR MASTER H

NPR ltEQ L
74LS123
START
200 ns

74LS123
CK1
75 ns

C 74LS112
OM SYN

74LS74
NPR
DONE

NPR DONE H

SSYN H

FIG. 2-10

+3 v

+5V
+5V

OUT NPR
(C1) H
1

J
74LSt23 1
CK2
75 ns

~-1----~=~~C 74LS112

LD
MP
+3 v

01.----NPR LD MULTIPORT

NPR REQUEST H

+3 v

~---.._

74LS123

0)
18 µs

74LS74
TIME
OUT

______________ ________ ____ ___
__...._

_._

__..

TIME OUT L

~------------....--BUSBUSYL

DC013

NPR
CONTROL
CHIP

BUS REQUEST
CHIP

BUSY
BUS NPRL
STEAL
GRANT

DC013

+ 3 V~STEAL

REQ
OUT

L<i__} GRANT

SSYN H
.----<11SSYN
BR MASTER H

..,....

CLR

BUS SACK L

SSYN L
INTR
DONE

BR MASTER L

__ _____

~----------1 BGIN

IN/OUT
BG 4,5.6

B
SACK

INTR
DONE

~B..:...R..:...R.:..:E:...:Q:....:L:..___ _ _ _ _-<JI REQ IN

BUS BG

BUS SACK L

,----<"11 SSYN

SACK

BR MASTER H

D13

NPG IN H

BG OUT I---+---,
SACK

INIT H

-= CLR

1209838

BUS BR L

1209838
PRIORITY
SOCKET

BUS BG

BUS INTR L

IN/OUT
BG 4.5.6.7

NPR REQ L

NPR MASTER L
MASTERU------r__;;:;_ _
NPR

REQIN

SACK

BGIN

BG OUT

CLR

SACK
CLR
EN

MASTER
BUS NPG OUT

TRIGGERS
START
F-F

NPR REQ H
NOT LAST XFER H
NOT LAST
XFER H

REF D15 OF
M8207 PRINT SET

BG OUT

MK-0679

Figure 2-10

Interrupt and NPR Control

2-17

BALU7(1)H

745138

BALU 7<4: 1 >H

CROM
DCODE
<2:0>

BR REQ H

OUT* LO
CLKS

BUS
REQ
CHIP
(DC013, D15)

D
74S74
BRANCH
REQ

T180

BR MASTER L
------c

CLEAR L

OAC L

74500

NPR REQ H
D

0-=NPR DONE H

I USE
I
I M8207-YC I CLEAR L
I
I
I
REG
I
I
11
I

74S74
NPR
REO

NPR
CONTROL
CHIP
(DC013-D15)

74LS153
MUX
OA16H
A

I
IL ____ ..JI

- - - - _o_A_1_7_H_ _ }

OUT A16 H
74LS175
µP
MISC

R/W H
VECTOR XX4H

TRISTATE SW
(D11)
& DMUX

CLEAR L
BALU 4(1) H

G INIT L

D15

STB

DMUX

OUT A17 H

BALU 2.3.5,6(1) H

BALU 0(1) H

D15

roPTIO-;ALl

74LS123 1
PROG
CLK
1 ms
0

+3V

TIME OUT L

OACH
NON EX MEM H

BALU 0(1) H
D
74LS74
NON EX
MEM

@
A

DMUX

TO
M9301

BALU 1 (1) H
74LS123
AC

~TAB

500 ms

-=- TP2

CLEAR L
+3V

FOR DOWN-LINE
LOADING OR BOOTING

REF D13 OF
M8207 PRINT SET

MK0696

Figure 2-11

Miscellaneous Registers
2-18

•

Bit I is the not last transfer bit which is part of a hex D flip-flop used for register I0. The
output of the flip-flip goes to the NPR circuit and keeps the NPR control chip (DC013)
from clearing at the end of an NPR cycle. This maintains BUS BUSY for multiple Direct
Memory Access (DMA) transfers. The NOT LAST XFER H signal line is also sent to the
DMUX (D7 of Print Set) and should be cleared when the last NPR RQ is set.

•

Bits 2 and 3 are NPR address bits 16 and 17 respectively. These bits are loaded into the hex
D flip-flop used for register 10 via the BALU (Fig.2-11
@). Outputs of the hex D flipflop (INl6 H, INI 7 H) are gated into a MUX (Fig. 2-11@ ) which is controlled by OUT
NPR (Cl) H. If this control signal is not set, bits 2 and 3 of register 10 are used as the upper
two bits of the NPR address. The MUX upper two bit outputs OA 16 H and OA 17 H are
also gated into the DMUX to be read by the microprocessor.

•

Bit 4 is the OUT NPR (Cl) H bit of register 10 used to control the direction of an NPR
transfer. Bit 4 is used by the multiplexers to select: (I) the registers to be used for the address
of an NPR transfer, and (2) the register to be loaded for an IN (read) transfer, or the register
to be loaded onto th~us for an OUT (write) transfer. Bit 4 is also loaded into the hex D
flip-flop (Fig. 2-11 QJ) ) and the output, OUT NPR (Cl) H controls bits 2 and 3 as
described in the previous paragraph. The control line is also gated into the DMUX to be
read by the microprocessor.

•

Bits 5 and 6 are read only bits showing MAR bits 8 and 10, which are page and field
overflow bits. These bits are duplicated in register 15 and kept in register 10 for compatibility with previous versions of the microprocessor family.

•

Bit 7 is used for byte transfers. This bit uses the hex D flip-flop and can be read through the
DMUX by the microprocessor.

2. 9 .2 Microprocessor Miscellaneous Register 11 (Register 11)

BR
RO

VECTOR
XXX
R/W

PGM
OUT
CLK OUT BA 16
BA 17

AC
LO

NON
EX
MEM

•BITS

MK-0680

•

Bit 0 is a nonexistent memory error. It uses a 74LS74 flip-flop that can be set and cleared by
the microprocessor. When a time out occurs during an NPR transfer, the flip-flop is preset,
indicating that slave sync was not returned within 18 microseconds. Bit 0 can be read
through the DMUX.

•

Bit I is AC LO which controls a one-shot (Fig. 2-11 @ ) that can be used to generate an
ac low on the UNIBUS, and a control signal to TPI (spade lug located near BERG Connector). This control bit should not be used for non-DEC programming unless the AC LO
function to the UNIBUS is disabled by removing jumper W3. Field Service representatives
should check this function if unusual problems are occurring with AC LO.
The AC LO feature is used for initializing the CPU and causes a one-half second AC LO
pulse on the UNIBUS (if W3 is installed). During this time, the microprocessor protects
itself from initialization by the UNIBUS INIT signal.

2-19

The output of the one-shot is also gated into an 888 l driver (Fig. 2-11 @ ) connected to
TPl. The output of the 8881 is GND when the AC LO bit is asserted and requires a pull-up
resistor (typically I K ohms at 5 volts). The intention is to drive a boot module directly
without using AC LO on the bus. The OAC H output is also input to the DMUX as a status
bit.

•

Bits 2 and 3 are OUT NPR a~ress bits 16 and 17 respectively. These bits are loaded into a
quad D flip-flop (Fig. 2-11 Q]) ) used for register 11 via the BALU. Outputs OUT Al 6 H
and OUT A 17 H are gated into the same MUX as IN A 16 H and IN A 17 H (see bits 2 and 3
of the NPR Control Register 10). The MUX is used to select the extended IN or OUT
address bits for NPR transfer (see bit 4 of register 10). These bits can also be read through
the DMUX by the microprocessor.

•

Bit 4 is the program clock which is a l ms one-shot (normally the function can change with
the "Y" version) (Fig. 2-11 @ ) used by the microprogram for timing. The output of the
one-shot, TIMER L, can be read through the DMUX by the microprocessor and does not
affect the operation of the microprocessor hardware.

•

Bit 5 has no hardware function, but should be reserved for future versions of the microprocessor. The bit is generated via register l ls quad D flip-flop and the output can be read
through the DMUX by the microprocessor.

•

Bits 6 and 7 are used for interrupts. Bit 6 selects the vector to be used for the interrupt. If bit
6 is set, the interrupt vector is XX4. If bit 6 is clear, the interrupt vector is XXO. Bit 7
initiates the interrupt.

The actual bit is written into register I ls quad D flip-flop (Fig. 2-1 l @ ). The flip-flop
output (XX4/XXO) goes to the tristate switch (DI I of Print Set) for the interrupt vector
address. and to the DMUX to be read by the microprocessor. Bit 7 is BR RQ (Fig. 211 @ ) which can only be written to a one by the microprocessor. The flip-flop must be
cleared by the hardware. A NANO gate is used to clock the data to the preset input of a
74S74 flip-flop. The data input to the flip-flop is tied to ground and used only to clear the
flip-flop on the completion of an interrupt. The BR RQ flip-flop is cleared by the CLEAR L
or OAC L signals. The output of the BR RQ flip-flop is used to initiate the interrupt through
the DCOl3 chip (Fig. 2-10 @ ). The DC013 uses the priority plug to ensure the proper
level, normally level 5. When the DC013 gives up bus mastership, the BR RQ flip-flop is
cleared.

2.10 BERG PORT (Figure 2-12)
The BERG Port is an 8-bit parallel port which allows the microprocessor to communicate with a line
unit without using the UNIBUS. The port runs at an instruction speed of 180 ns. Eight addresses are
used both for read and for write transactions (using the microprocessor as reference).
•

Read Transactions: The address is output 20 ns after the beginning of the instruction at time
zero (TO). Buffered TO goes to the port for syncing the line unit to the microprocessor. Data
must be valid for a read, 50 ns after the address is set up, and must remain valid until 20 ns
after the leading edge of IBR low. IN BUS has been read (IBR low) starting at Tl20 and
ending at Tl 80.

•

Write Transactions: The address is valid 20 ns from TO. The data is valid on the BALU lines
140 ns after TO. The data should be clocked on the trailing edge of OUT BUS WRITE
(OBW). Recommended interface chips are shown on the last sheet of the M8207 Print Set.
2-20

BUS TIMING THAU BERG

120

180

I
CROM LIN ES 0-+7 L

---<;:. . ___

c_R_O_M_L_IN_E_s_v_A_L_ID_ _:_A_D_R....
s_1_N_1o_u_T_

LINE UNIT IBUS 0-+7 H
BALU LINES 0-+7 L
TIMING PULSE

---+1------c~ DATA LUIBUS ~AUD
VALID FROM PREVIOUS INSTRUCTION

l__....._BT_O_L_ __

_..,.,

>------:..----BALU VALID

I
I

LINE UNIT HAS BEEN READ t
(IBUS READ)

IBR L

CLOCK DATATO LU t
(OUT BUS WRITE)

loBWL
I
I

T1
T2
T3
T4
T5

= 20 ns MAX
= 50 ns MAX
= 50 ns MIN FROM T120
= 20 ns MIN FROM T120 FOR LUIBUS LINES
= 40 ns MIN FROM T180 FOR BALU LINES

I
I

REF SHEET 21 OF
M8207 PRINT SET
MK-0681

Figure 2-12

Timing Through BERG Port

2.11 BRANCH CONTROL (Figure 2-13)
Three branch instructions are defined by Source Decoder input bits CROM <15:13>:
•
•
•

Branch Immediate (JMP I)
Branch Memory (JMP MEM)
Branch Register (JMP BRG)

When a branch condition is established, BRANCH INST Lis asserted. This provides the strobe input
to the 8-to-1 branch control multiplexer, which is driven directly by instruction register CROM
< 10:8> condition bits. The control MUX is disabled during a move instruction as defined by the
Source Decoder. In this case BRANCH INST L is unasserted, thereby removing the required strobe
input to enable the control MUX.
Branch MUX control inputs are:
•

+3 Volts (inputs DO, Dl) - branch always instructions

•

C(l) H bit (input D2) - branch on carry

2-21

•

Z(l) H bit (input D3) - branch on Z (ALU all ones)

•

BRG 0, 1, 4, 7 (H) bits (inputs D4 - D7)
BRG 0 (Branch Field) - During this branch, the upper six bits of the PC are always loaded
from the PCR (OUT* 13); the page and field bits are changed to the contents of register 13.
BRG 1, 4, 7 -These branches use bits 11and12 of the IR for paging bits, but cannot change
the field bits. The only way to change the field bits is with Branch 0, unless the field is
incremented into.

SOURCE
DECODER

CROM 13 H

SELA

CROM 14 H

SELB

CROM 15 H

SELC

SOURCE DECODER
INPUTS
CROM
14
15

}MDV
INST

OUTPUTS

0
0

JMPI

JMP BAG

0
0

JMP MEM

(D7)

BRANCH MUX
INPUTS

OUTPUTS
STB
(74S151)

STB

fOH

fOL

BAG 7 H

BAG 4 H

BAG 1 H

BRGO H

Z(1) H

BRANCH
MUX
03 (CNTR'L)

C(1) H

fOH

+3V

DO
S2

fOL

01
S1

BRANCH H

BRANCH L PC
LOAD
INPUT

CROM 10 H
INSTRUCTION {
REGISTER

CROM 9 H
CROM 8 H
MK-0668

Figure 2-13

Branch Control Logic
2-22

2.12 BRANCH REGISTER (BRG) (Figure 2-14)
The BRG is an 8-bit register which is used as a temporary storage register. It provides four distinct
modes of operation used under branch conditions:
•
•
•
•

Parallel Loading
Shift Right
Shift Left (ground input locks out shift left mode)
Inhibit Clock

These modes of operation are determined by the states of SO and SI inputs from the Desination ROM.
Refer to Figure 2-13 and note that the operations occur on the positive-going edge of CLK MAR
BRG L.

2.13 DESTINATION ROM (DROM) (Figure 2-15)
The DROM provides control lines SO and SI to the BRG and increment inputs to the MAR. DROM
also provides three additional control outputs determined by CROM input bits < 12:8>:
•

BRANCH FIELD H output is used as the select input to a 74SI 57 MUX in the PC circuitry.

•

SP and MEM outputs are gated into a 74Sl 58 MUX to generate: (I) the write enable input,
WRITE MEM L, for the memory, and (2) the write enable input, WRITE SP L, for the SP.

2.14 CONTROL AND STATUS REGISTERS (CSRO and CSR6)
The control and status registers are primarily defined by the microcode. Byte l of CSRO is defined by
the hardware. When written to by the CPU, the microprocessor can write into the Multiport RAM
without affecting the hardware register. CSR6 is only defined when used with byte 1, bit 9, and bit 10
of CSRO.
CSRO - Address 76XXXO
15
RUN

14
MCLR

STEP
LU

LU
LOOP

ROM

STEP
µP

BYTEO
CSR 0

BYTE 1
CSR 1

MK-0671

The M8207 uses the floating address area. Actual setting of the address depends on the microcode
variation option, of which the M8207 is a part. The space requires eight bytes or four words for CSRO
through CSR6 locations. 'The XXX in the address is switch selectable and should be set up when the
module is installed in the system. Bits and associated CSR 1 (high byte of CSRO) are controlled in the
following manner. Note that RUN bit 15 can be disabled via the RUN INHIBIT switch (see Dl6 of
Print Set).
NOTE
Switch 8 of the Interrupt Switch Pack is used to disable ALL CSRs.

2-23

GR INPUT
LOCKS OUT
SHIFT LEFT
MODE

PARALLEL LOAD

~
BALU 0(1) H

74LS194
03
R3

BRGOH

8ALU 1(1) H

BRG 1 H

BALU 2(1) H

BRG2 H

----

BALU 3 (1) H
CLEAR L

SHIFT
RIGHT

SHIFT
LEFT

INHIBIT

N
0

BRG3 H

RO= BRG 4

H
A
N

DSR

BRG4 H

G
E

-::-

DROM

{so

CLK MAR BAG L

CLK

N
0

(01)

c
H

BALU 4 (1) H

74LS194
03
R3

BRG4H

BALU 5(1) H

aRG 5 H

BALU 6(1) H

.R1

BRG 6 H

BALU 7(1) H

-----

BAG 7 H

CLEAR L
BALU 0(1) H

A
N

I l

G
E

RO= BALU 0

DSR
DSL

-::-

DROM

{80

__r-

CLK

CLK MAR BRG L

SI
(D2)

INPUTS

OUTPUTS

MODE

SERIAL

PARALLEL

CLR

so CLK

LEFT

RIGHT DO

(j)

x
x

H/L

<2>
®

x x x x
x x x x
x x x x

H/L RO

i
i
i

RO R1

PARALLEL LOADING - OUT =THE LEVEL OF STEADY STATE INPUTS (BALU BITS)
2

SHIFT RIGHT - OUT= RO IS AT LEVEL OF DSR INPUT RO-R3 SHIFTED RIGHT

SHIFT LEFT - OUT

= RO-R3 SHIFTED LEFT. DSL AT LOW LEVEL (GND IN)
AT VACATED R3 BIT POSITION

INHIBIT CLOCK - OUT

= NO CHANGE

Figure 2-14

Branch Register
2-24

MK-0670

CROM 8 H

23202A1
DROM
AO
08

CROM 9 H

CROM 10 H

MEM

CROM 11 H

MAR INC

LO MAR HI

LO MAR LO

CROM 12 H

USED BY AUTOMATED
TEST TO DISABLE DROM

BRANCH FIELD H

(01)

MICROINSTRUCTIONS
CROM BITS

BRANCH

MOVE

12.11

BRANCH ADDR BITS

MAR FUNCTION

10.9.8

CONDITION CODE

DESTINATION FIELD
MK-0669

Figure 2-15 .Destination ROM

2-25

•

BIT 8 (STEP µP} steps the microprocessor through one instruction cycle.

•

BITS 9, IO, JJ, 12 and 15 functions are asserted on the positive-going edge of CSRO clock
input signal.

•

BIT 9 (ROM I) when cleared generates CROM enable 0 + lK, 2 + 3K, and 4 + 5K inputs
to the control ROM circuitry. Bit 9 when set enables CSR6 to be used as the maintenance
register.

•

BIT IO (ROM 0) is ANDed with Al and A2 to provide the select input to the data select
multiplexers at the UNIBUS data interface. When select input is unasserted, A PORT data
is directed to the UNIBUS interface. When select input is asserted, ROM data is selected to
verify the contents of the ROMs.

•

BIT 11 (LU LOOP) connects line unit serial line back to its serial line in (optional with the
line unit).

•

BIT 12 (STEP LU} shifts transmitters/receivers (optional with the line unit).

•

BIT 13 reads/writes in the Multiport RAM; does not perform any hardware functions.

•

BIT 14 (MASTER CLEAR) clears both the microprocessor and line unit.

•

BIT 15 (RUN) controls the microprocessor clock via the RUN STEP L signal input to the
system clock circuitry (set on Master Clear).

•

BITS JJ, 12, 14, and 15 are directly connected to the line unit via the J 1 connector. (See Dl6
of Print Set.)

CSR6 - Address 76XXX6
In maintenance mode, an instruction can be loaded with bit 9 of CSRO. In CROM display, the contents of the ROM can be verified with bit 10 of CSRO in a set state.

2-26

CHAPTER 3
SERVICE

3.1 SCOPE
Maintenance procedures used in servicing an M8207 module are discussed in this chapter.
NOTE
The M8207 performs no useful function without application firmware supplied only by DIGITAL.
There are no built-in maintenance features such as
error checking or self-diagnosis.
3.2 MAINTENANCE PHILOSOPHY
The M8207 module is the Field Service Field Replaceable Unit (FRU). Isolation to the module must
be done through the use of DEC Diagnostics and/or any microdiagnostics that may have been incorporated in the Control Read Only Memory (CROM). In some applications, ROMs are provided
for replacement by a Field Change Order when an error is detected in CROM.
3.2.1 Preventive Maintenance
There is no specific Preventive Maintenance (PM) schedule for the M8207 module. Voltages and
connections should be checked during system PM or when problems exist. While special tools are
required for PM, standard test equipment may be used. The diagnostics include:
•
•

Microprocessor basic diagnostics (not requiring CROMs) are provided
Functional diagnostics based on ROM code application

3.2.2 Corrective Maintenance
Standalone diagnostics are provided for checkout of the basic M8207 Microprocessor. These diagnostics check out the M8207 logic and determine whether the microprocessor is capable of running a
microprogram from CROM.
Microinstructions are clocked into the Maintenance Instruction Register (MIR) from the UNIBUS,
allowing one microinstruction to be executed at a time. Although individual microinstructions are
executed at full microprocessor speed, the time between instructions depends upon Central Processing
Unit (CPU) execution time.
Basic M8207 diagnostics are designed to run on the basic microprocessor logic with or without
CROMs installed.
Functional diagnostics are provided for specific DIG ITAL supplied applications implemented in the
CROMs. These diagnostics are application oriented, implementing and testing features provided in

3-1

microcode as well as in the M8207 hardware. They should be run whenever possible to ensure total
option functionality. The functional diagnostics perform a Cyclic Redundancy Check (CRC) on the
CROM contents, before starting the microprocessor. CROMs can be diagnosed in 2K segments and
may be replaced if required.
NOTE
A 2K segment consists of2 chips, each 2K-by 8-bits.
When problems occur, the voltage levels should be checked on the backplane,* and all connections
should be checked for proper installation and seating. In systems where the M8207 is newly installed or
add-ons have been implemented, proper bus configuration must be ensured. Diagnostics should then
be run starting with the basic tests and continuing on to the functional diagnostics.
If a customer's application does not work, but all diagnostics run successfully, and the system checks
out, the M8207 should be replaced. Diagnostics should then be run on the new M8207. Upon successful completion of the diagnostic, the customer's application can be retried. The possibility that faulty
microcode or software drivers exist should be considered.
NOTE
The M8207 will only be supported when used in a
DIGITAL supplied subsystem, including DIGITAL
supplied microcode.
3.3 MICROPROCESSOR USE WITH LINE UNITS
M8207 diagnostics should be run before any line unit diagnostics. This is necessary because the M8207
provides all access and control for the line unit and could erroneously cause a line unit to appear
faulty.
As with M8207 basic tests, microinstructions are loaded and clocked at the CPU execution speed.
Execution of individual microinstructions occurs at the microprocessor cycle rate.
3.4 LINE UNIT PORT CABLE CONSIDERATION
The line unit cable (BC08S-I or BC08R-1) is susceptible to damage from frequent bending and chafing. This cable may be responsible for apparent line unit failures and should be replaced if in doubt.
3.5 M8207 LINE UNIT PORT
Only DEC supplied line units are supported on the line unit port.
3.6 MICRODIAGNOSTICS
Microdiagnostics are not part of the M8207 module. They must be incorporated as part of the application microcode. Recommended microdiagnostic tests are provided in Appendix A. A microdiagnostic failure, in general, is reason to run CPU based diagnostics or replace the indicated module.
It should be noted that the microdiagnostic cannot be relied upon for 100% logic failure detection.
The microdiagnostic relies upon a basically operational microprocessor. Some faults in a microprocessor could cause the microdiagnostic to report incorrect error information or, in extreme cases,
not to report at all.
*The M8207 microprocessor draws 7 amps at + 5 volts. This should be considered, especially when adding a load to a regulator. Nine slot SPC backplanes, such as the 0011-D, permit configurations with power supply overload capability.

3-2

Refer to Appendix A for error codes and a description of the internal and interface diagnostics. The
intent of the microdiagnostic is to:
•
•

Identify a faulty unit
Provide error information indicative of the fault

The first intent can help the customer isolate a faulty option under system operation. This could allow
reasonable system operation to continue while placing a call for service. And, if the customer can
identify the failing subsystem, the Field Service time needed to diagnose the problem would be reduced.
The second intent may indicate which module is defective, effectively reducing diagnostic and repair
time.
3.7 ROM REPLACEMENT
The Programmable ROMs (PROMs) on the M8207 are 2K- by 8-bits. The last four bytes on the
PROM contain information about the PROM. The first of the last four bytes contains the ASCII
Version number. The second byte contains the ROM number (0, I, 2, 3, 4, or 5). The third and fourth
bytes contain a negative CRC-CCITT word for that PROM. The two static diagnostics written for the
M8207 do not check the PROMs. The functional diagnostics written for a specific option associated
with the M8207 should be used for verification of ROM contents and ROM placement checking.
Figure 3-1 is an extract of the M8207 module component layout; component side view of upper connector pins and ROM portion. Pin 1 is identified on each chip to ensure proper orientation and
installation of a good chip should it become necessary. A ROM Kit including ROM replacement
procedures is supplied with the shipment.
Table 3-1 shows the relationship of the E numbers and address range of chips 0 through 5.
Table 3-1

Chip Address Range

Chip
Location

Chip
No.

Byte

Address
Range

E03

LOW

0000- 3777g

E02

HIGH

0000- 3777g

E04

LOW

4000- 7777g

EOl

HIGH

4000- 7777g

E05

LOW

10000-l 3777g

El4

HIGH

10000-l 3777g

CAUTION
Care should be exercised when replacing ROMs.
• Amid touching chip surface
• Handle ROMs by placing fingers on either
ends of the chip
• Do not bend pins during insertion

3-3

LB 4-5K
4

LB 2-3K
E4

LB 0-1K

E17
93516

?
~~

E16_
93516
E15
93516

HB 0-1K

I~ ~IN

HB 4-5K
E13
E14 5
PIN VCCONN
1 8641
C13

HB 2-3K
3

C12

LKJHFEDCBA

VUT5RPNMLKJHFEDCBA
MK-0686

Figure 3-1

Extract of M8207 Module Component Layout

3-4

Refer to Figure 3-1 and check for:
•
•

Proper chip orientation
Proper chip location

Following is a sample test to check out ROM 0 for CRC/CCITT (ROM contents) and ROM position.

10$

20$

30$

MOY
MOY

#0,ROMN
#0,CADDR

;ROM NUMBER
;GET STARTING ADDR.

MOY

#-1,CWORD

;INIT CRC WORD.

JSR

PC,GWORD

;GET FIRST BYTE.

MOYB
INC
JSR
MOYB

@SEL6,WORDT
CAD DR
PC,GWORD
@SEL6,WORDT+I

INC
CMP
BEQ

CAD DR
CADDR,#3777+1
20$

;STORE FIRST BYTE.
;UPDATEADDR.
;GET A BYTE.
;STORE IN HIGH BYTE OR
WORDT
;UPDATE ADDR.
;ATEND?
;YES,EXIT LOOP.

JSR

PC,CRCR

10$

COM

CW ORD

CMP
BEQ
ERROR

CWORD,WORDT
30$

MOY

#3775,CADDR

JSR
CMPB
BEQ
ERROR

PC,GWORD
ROMN,WORDT
40$

;NO-CALCULATECRC ON THIS
WORD.
;LOOP
;STORED CRC WORD IS
COMPLEMENT.
;EQUAL?
;ROM CRC WORD BAD.
;SET ADDRESS FOR ROM
NUMBER.
;READ ROM
;IS ROM NUMBER CORRECT?

40$
ENDTST

·*******************************************************************************

'·*
' GWORD
;*
;*
;*
;*

ROUTINE TO READ A WORD FROM ROM ON THE M8207
CALL=JSR PC,GWORD
ENTER WITH ADDRESS INCADDR
EXIT WITH DATA IN SEL6

·*******************************************************************************

3-5

GWORD: CLR
MOVB
JSR
.WORD
BIC
BISB
JSR

@SELO
CADDR+ l,@SEL2
R5,ROMCLK
121053
#377 ,1$
CADDR,1$
R5,ROMCLK

.WORD

100000

BIS

#2000,@SELO

;INIT
;SET HIGH BYTE OF ADDRESS
;MOY IBUS* 2 TO OBUS*13
;STRIP ADDR FIELD.
;ADD IN IMM ADDR.
;GO DO BRANCH
;BRANCH EXT PUTS ADDR. IN
PCREG.

RTS PC

;EXIT

.·*·********************************************************************************
•
ROUTINE TO SINGLE STEP AN INSTRUCTION IN THE
;*ROMCLK
M8207
.·*·*
CALL=JSR R5, ROMCLK
'
·*
•
·*
'

.WORD INSTR
RETURNS HERE
·********************************************************************************

ROMCLK:
BISB
MOY
BISB
BICB
RTS

#2,@SELI
(R5)+ ,@BSEL 6
#3,@BSELl
#7,@BSELI
R5

;SETROMI
;SET INSTRUCTION
;CLOCK INSTR.
;CLEAR

·********************************************************************************
;*CRCR
ROUTINE TO TAKE 16 BITS OF DATA AND CONVERT THEM
INTO
PART OF A SERIAL STREAM THAT WE'RE CALCULATING
·*
'
A CRC-CCITT WORD FROM.
·*
'
CALL=JSR PC,CRC
·*
ENTER WITH 16 BITS IN WORDT
·*
'
EXIT WITH 16 BIT WORD IN CWORD
·*
'
NOTE:: CWORD MUST HAVE BEEN INITED TO -1 PRIOR TO
'·*
·*
FIRST CALLING THIS ROUTINE
'
·********************************************************************************
'

.
'

CRCR:

MOV
MOY
MOY

Rl,-(SP)
R2,-(SP)
#16.,R2

;SAVE GEN REGS Rl,R2

3-6

10$

20$

CLC
ROR
ROR
BVC

CW ORD
WORDT
20$

MOV
BIC
BIC
BIS

#102010,Rl
CWORD,Rl
#102010,CWORD
Rl,CWORD

DEC
BGT
MOV

R2
10$
(SP)+,R2

MOV

(SP)+,Rl

;CRC/CCITT POLYNOMIAL

;RESTORE GEN REGS

;EXIT

RTS PC

3-7

APPENDIX A
MICRODIAGNOSTIC TESTS

A.I INTRODUCTION
The microdiagnostics contained in this Appendix were written for the M8207 Microprocessor. The
following tests are recommended for all M8207 applications.
NOTE
The microdiagnostics provided in this section are
EXAMPLES and are not to be construed as the
ONLY IMPLEMENTATION.
A.2 HARDWARE REQUIREMENTS
The following hardware is required to run the microdiagnostics.
•
•
•

Central Processing Unit (CPU)
M8207
16K Memory

A.3 RELATED SOFI'WARE
Internal microdiagnostics need no external supporting software. Interface microdiagnostics for PDP11 s require "CZDMTCO DMPll FCTNL TST#l.
A.4 INTERNAL MICRODIAGNOSTICS
•

Internal microdiagnostics are written in KDA assembler format that run on initialization
within the DMPl 1 subsystem. These diagnostics are go/nogo type.

•

Errors are isolated to the module level. When an error is detected, the microdiagnostic
attempts to insert an error number in BSEL4 and enter an infinite loop. The CPU software
may test the run bit and error number at the end of the test, or a visual inspection can be
performed by evaluation of the Control and Status Registers (CSRs).

•

Good and bad data are entered in BSEL 3 and 5 when applicable.

•

The current test number is entered in BSEL 6.

•

Test numbers are not in sequential order.
NOTE
If a hardware failure prevents the microdiagnostics
from reporting an error indication, some or all of the
above will not occur.
A-1

A.5 INTERNAL MICRODIAGNOSTIC TEST PROCEDURES
In the following microdiagnostic tests, CERROR is a macro that, when expanded, generates a current
error number, outputs this number to BSEL 4, and increments the error number to identify the next
error.
Example:
EXPANSION OF

CERROR

BRWRTE IMM.#
OUT
BR.SELB,OBSEL4
MK-0672

A.5.1 Branch Test #1 - Branch False and Branch Always
Errors in this test may be caused by the failure of a BR WRTE instruction and/ or the Arithmetic Logic
Unit (ALU), as well as the branch not operating properly.
START:

DBRANC:

DBR.F:

BRWR TE
OUT

IMM,O
BR,SELB,OBSELl

BRWR TE
OUT
CERROR

IMM,143
BR,SELB,OBSEL6

BR WR TE

IMM,O
DBRERR
IMM,376
DBRERR
IMM,375
DBRERR
IMM,357
DBRERR
IMM,177
DBRERR

BRWRTE
BRO
BRWRTE
BRl
BRWRTE
BR4
BR WR TE
BR7

;SHOW BRANCH TEST

;ERROR #l TO BSEL 4 IN CASE OF FAILURE

ALWAYS DBRFE

DBRERR:
ALWAYSDBRERR
DBRFE:

'
;ZERO
MASTER CLEAR BIT

;LOAD 0 IN BREG
;SHOULD NOT BRANCH, Z BIT CLEAR.
;SET ALL BUT BIT 0.
;NOW BRANCH ON BIT 0, IF ERROR.
;SET ALL BUT BIT 1.
;ONLY AN ERROR WILL CAUSE A BRANCH.
;SET ALL BUT BIT 4.
;ONLY AN ERROR WILL CAUSE A BRANCH.
;SET ALL BUT BIT 7.
;ONLY AN ERROR WILL CAUSE A BRANCH.
'
;NOW BRANCH TO END OF TEST.
;IF BRANCH ALWAYS FAILS, END UP IN
;ERROR ROUTINE

'
;LOOP
HERE ALWAYS
;END OFTEST

A-2

A.5.2 Branch Test #2 - Branch True
Errors in this test may be caused by the same failures defined in Test #1.
DBR.T:

DBR.T5:

BR WR TE
BR7
ALWAYS
BRWRTE
BR4
ALWAYS
BRWRTE
BRI
ALWAYS
BRWRTE
BRO
ALWAYS
SP

DBR.T6:

ALWAYS
SP

DBR.T7:

ALWAYS
ALWAYS

DBR.T2:

DBR.T3:

DBR.T4:

IMM,200
DBR.T2
DBRTER
IMM,20
DBR.T3
DBRTER
IMM,2
DBR.T4
DBRTER
IMM,l
DBR.T5
DBRTER
IMM,377,SPI 7
DBR.T6
DBRTER
BR,INCA,SPI 7
DBR.T7
DBRTER
DBR.T8

;SETBIT7
;BR IF KNOWN SET
;ELSE GOTO ERROR.
;SETBIT4.
;BR IF KNOWN SET.
;ELSE GOTO ERROR.
;SET BIT I
;BR IF KNOWN SET.
;ELSE GOTO ERROR.
;SETBITO
;BR IF KNOWN SET.
;ELSE GOTO ERROR.
;SET ALL BITS, CAUSEZ BIT SET.
;BR IF Z BIT SET.
'
;SET "C" (CARRY BIT).
;BR IF C BIT SET.
;ELSE GOTO ERROR.
;DOUBLE CHECK THAT BR ALWAYS WORKS

DBRTER:
CERROR
ALWAYS

•

;ERROR #2 IF BRANCH TEST (TRUE) FAILS
;LOOP HERE
;END OF TESTS

DBRTER

DBR.T8:

A.5.3 Extended Branch Test - Branch Field
This test performs branches to all fields and returns.
DBREXO

DBREXI:

DBREX2:

DBREX3:

DBREX4:

DBREX5:
DBREXR:
DB REX:

BR WR TE
OUT
JMPEXT
CERROR
ALWAYS
JMPEXT
CERROR
ALWAYS
JMPEXT
CERROR
ALWAYS
JMPEXT
CERROR
ALWAYS
JMPEXT
CERROR
ALWAYS
JMPEXT
CERROR
ALWAYS

IMM,135
BR,SELB,OBSEL6
DFLDO
DBREXR
DFLDI
DBREXR
DFLD2
DBREXR
DFLD3
DBREXR
DFLD4
DBREXR
DFLD5
DBREXR

;SET UP TEST NUMBER IN BSEL6
'

;BRANCH TO FLO 0
;ERROR #3 IF BRANCH EXT FIELD 0 FAILS
;ERROR
;BRANCH TO FIELD l
;ERROR #4 IF BRANCH EXT FIELD I FAILS
;ERROR
;BRANCH TO FIELD 2
;ERROR #5 IF BRANCH EXT FIELD 2 FAILS
;ERROR
;BRANCH TO FIELD 3
;ERROR #6 IF BRANCH EXT FIELD 3 FAILS
;ERROR
;BRANCH TO FIELD 4
;ERROR #7 IF BRANCH EXT FIELD 4 FAILS
;ERROR
;BRANCH TO FIELD 5
;ERROR #IO IF BRANCH EXT FIELD 5 FAILS
;LOOP ON ERROR
;END OFTEST

A-3

A.5.4 IBUS/OBUS Test
This test exercises the IBUS/OBUS (*)registers. Patterns are set up in SPl and SP2. Control is then
transferred to subroutine DWRIO.
Patterns used:

First pass - SPI = 125; SP2 = 252
Second pass - SPI = 252; SP2 = 125
Third pass - SPI and SP2 = 0

Time per pass:

approximately 16.8 ms

DIOT:

DIOTI:

BR WR TE
SP
CERROR

IMM,125
BR,SELB,SPl

BRWRTE
SP
CALLSB
CERROR

IMM,252
BR,SELB,SP2
SPO,DWRIO

BRWRTE
SP
BR WR TE
SP
CALLSB
CERROR

IMM,252
BR,SELB,SPl
IMM,125
BR,SELB,SP2
SPO,DWRIO

BRWRTE
SP
SP
CALLSB
ALWAYS

IMM,O
BR,SELB,SPl
BR,SELB,SP2
SPO,DWRIO
DSCRTH

DIOT2:

DIOT3:

;GET CONSTANT 125
;PUT INTO SPl
;ERROR#l l IF PATTERN 125/252 FAILS IN
;SCRATCHPAD TST
;GET CONST ANT 252
;PUT INTO SP2
;GO TO SUB DWRIO TO R/W IBUS/OBUS REGS
;ERROR #12 IF PATTERN 252/125 FAILS IN
;SCRATCHPAD
;GET CONST ANT 252
;PUT INTO SPl
;GET CONSTANT 125
;PUT INTO SP7
;GO TO SUB DWRIO TO R/W IBUS/OBUS REGS
;ERROR #13 IF PATTERN 0 FAILS IN
;SCRATCHPAD
'

;NOW WRITE ALL IBUS/OBUS REGS
;TO ZERO BY CALLING
;ROUTINE "DWRIO" WITH ZEROS IN

The DWRIO subroutine writes/reads out patterns in OBUS/IBUS(*). Enter with two patterns; one in
SPl, the other in SP2. Return address in SPO (must be in same page and field). If an error is detected,
hang in this routine.
NOTE
In comparing the register against S/B, use a one's
complement subtract. This allows branching on the Z
bit to be set if the register and S/B are equal.
DWRIO:

BRWRTE
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BRWRTE
OUT
OUT

SELA,SPl
BR,SELB,OINCON
BR,SELB,OOCON
BR,SELB,OPORT 1
BR,SELB,OPORT3
BR,SELB,OIDAT2
BR,SELB,OUTDA2
BR,SELB,IBA2
BR,SELB,OBA2
SELA,SP2
BR,SELB,OLINEN
BR,SELB,OPORT2

;GET FIRST PATTERN
;WRITE IN BSELO
;BSEL2
;BSEL4
;BSEL6
;OTHER SIDE #6

;#2

;#4

;#6
;GET NEXT PATTERN
;BSEL3
;BSEL5

A-4

DWRIO (Cont):
OUT
OUT
OUT
OUT
OUT
BRWRTE
NO DST

BR,SELB,OPORT4
BR,SELB,OIDATl
BR,SELB,OUTDA 1
BR,SELB,IBA 1
BR,SELB,OBA 1
IBUS,INCON
BR,SUBOC,SPl
DWRIOl

CERROR
ALWAYS DWRER
DWRIOI: BR WR TE IBUS,OCON
NO DST
BR,SUBOC,SPl
DWRI02
z
CERROR
ALWAYS DWRER
DWRI02: BRWRTE IBUS,PORTl
BR,SUBOC,SPl
NO DST
DWRI03
z
CERROR
ALWAYS DWRER
DWRI03: BRWRTE IBUS,PORT3
NO DST
BR,SUBOC,SPl
z
DWRI04
CERROR
ALWAYS DWRER
DWRI04: BR WRTE IBUS,INDAT2
NO DST
BR,SUBOC,SPl
z
DWRI05
CERROR
ALWAYS DWRER
DWRI05: BRWRTE IBUS,IODAT2
NO DST
BR,SUBOC,SPJ
z
DWRI06
CERROR
ALWAYS DWRER
DWRI06: BR WRTE IBUS,IIBA2
NO DST
BR,SUBOC,SPl
z
DWRI07
CERROR
ALWAYS DWRER
DWRI07: BRWRTE IBUS,IOBA2
NO DST
BR,SUBOC,SPl
z
DWRILl
CE RR OR
ALWAYS DWRER
DWRILl:
DWRIL2: BRWRTE IBUS,LINENM
NO DST
BR,SUBOC,SP2
z
DWRIL3
CERROR
ALWAYS DWRER
DWRIL3: BRWRTE IBUS,PORT2
NO DST
BR,SUBOC,SP2

;BSEL7
;OTHER SIDE #l
;#3
;#5
;#7
;GET CONTENTS OF BSELO
;COMPARE IT AGAINST S/B
;BR IF OK
;ERROR #14 IF INCON FAILS
;ELSE GO TO ERROR
;READBSEL2
;COMPARE AGAINST S/B
;BR IF OK
;ERROR #15 IF OCON FAILS
;READBSEL4
;COMPARE AGAINST S/B
;BR IF OK
;ELSE GO TO ERROR
;ERROR #16 IF PORT 1 FAIL
;READBSEL6
;COMPARE AGAINST S/B
;BR IF OK
;ELSE GO TO ERROR
;ERROR #17 IF PORT 3 FAILS
;READ OTHER SIDE #1
;COMPARE AGAINST S/B
;BR IF OK
;ELSE ERROR
;ERROR #20 IF INDA T2 FAILS
;READ#3
;COM}>ARE AGAINST S/B
;BR IF OK
;ELSE ERROR
;ERROR#21 IFIODAT2FAILS
;READ#5
;COMPARE S/B
;BR IF OK
;ELSE ERROR
;ERROR #22 IF IIBA2 FAILS
;READ#7
;COMPARE S/B
;BR IF OK
;ELSE ERROR
;ERROR #23 IF IOBA2 FAILS
;READBSELl

'
;COMPARE
S/B
;BR IF OK
;ELSE ERROR
;ERROR #24 IF LINENM FAILS
;READBSEL5
;COMPARE S/B
;BR IF OK
A-5

DWRIL3 (Cont):
DWRIL4
z
CERROR
ALWAYS DWRER
DWRIL4: BRWRTE IBUS,PORT4
NO DST
BR,SUBOC,SP2
z
DWRIL5
CERROR
ALWAYS DWRER
DWRIL5: BR WR TE IBUS,INDATl
BR,SUBOC,SP2
NO DST
DWRIL6
z
CERROR
ALWAYS DWRER
DWRIL6: BRWR TE IBUS,IODATl
NO DST
BR,SUBOC,SP2
DWRIL7
z
CERROR
ALWAYS DWRER
DWRIL7: BRWR TE IBUS,IIBAl
BR,SUBOC,SP2
NO DST
DWRIL8
z
CERROR
ALWAYS DWRER
DWRIL8: BRWRTE IBUS,IOBAI
NO DST
BR,SUBOC,SP2
z
DWREE
CERROR
DWRER:
ALWAYS DWRER

'
;HANG
FOREVER ON ERROR

DWREE:

,
RTNSUB

SPO,PO

;ELSE ERROR
;ERROR #25 IF PORT2 FAILS
;READBSEL7
;BR IF OK
;ELSE ERROR
;READ OTHER SIDE #0
;ERROR #26 IF PORT4 FAILS
;COMPARE S/B
;BR IF OK
;ELSE ERROR
;READ#2
;ERROR #27 IF INDATl FAILS
;COMPARE S/B
;BR IF OK
;ELSE ERROR
;READ#4
;ERROR #30 IFIODATI FAILS
;COMPARE S/B
;BR IF OK
;ELSE ERROR
;READ#6
;ERROR#31 IFIIBAI FAILS
;COMPARE S/B
;BR IF OK, ELSE FALL THRU FOR ERROR
;PICK UP#O
;TRY CLEARING RUN BIT
;ERROR #32 IF IOBAl FAILS

;EXIT SUBROUTINE

A.5.5 Scratchpad Test
The scratchpad test floats a zero through all scratchpads.
NOTE
As an overhead, main memory locations 0-15 will be
tested. To do this: ( 1) set up memory (loop point), (2)
do memory to scratchpad, (3) compare memory to
scratchpad, (4) see if test is completed, (5) modify
memory, (6) loop back to step 2.
DSCRTH: BRWRTE
OUT
DSP.ZI:
BRWRTE
SP
NO DST
NO DST
MEMINC

IMM,123
BR,SELB,OBSEL6
IMM,<377-17>
BR,SELB,SPO
IMM,O,LDMAR
IMM,O,LDMAPG
IMM,177

:DO LOOP IS 15 TIMES.

'
;SET
MEMORY ADDRZERO
;LOAD MAR UPPER
;PUT A 177 INTO THE FIRST LOC.

A-6

DSP.Z2:

MEMINC IMM,377

NO DST
SP
SP
SP
SP
SP
SP
SP
SP
SP

IMM,O;LDMAR
MEMX,SELB,SPO,INCMAR
MEMX,SELB,SPl ,INCMAR
MEMX,SELB,SP2,INCMAR
MEMX,SELB,SP3,INCMAR
MEMX,SELB,SP4,INCMAR
MEMX,SELB,SP5,INCMAR
MEMX,SELB,SP6,INCMAR
MEMX,SELB,SP7 ,INCMAR
MEMX,SELB,SPl O,INCMAR

SP
SP
SP
SP
SP
SP
SP

MEMX,SELB,SPI l,INCMAR
MEMX,SELB,SPI 2,INCMAR
MEMX,SELB,SPl 3,INCMAR
MEMX,SELB,SPI 4,INCMAR
MEMX,SELB,SPI 5,INCMAR
MEMX,SELB,SPl 6,INCMAR
MEMX,SELB,SPl 7,INCMAR

;MOVE ALL ONES TO MEMORY
;UPDATE MAR ADDR.
;SEE IF DONE
;IF DONE (=377) NEXT STEP
;ALSO LOOP
;LOAD TEST ADDR LOC WITH 0
;DO MEMORY TO SP NOW
;SET MEM ADD TO ZERO
;OK FOR THE NEXT 16 INSTRUCTIONS
;NOW COPY
;MEMORYINTOSCRATCHPAD
;REGS THIS TEST,
;NOTICE AS YOU GO THROUGH,
;IT DEPENDS HEAVILY UPON
;MAIN MEMORY BEING OK
;IF MAIN MEMORY IS BAD,
;TROUBLE LIES IN TWO AREAS
; I. TEST DOES NOT COMPLETE,
;DUE TO SHIFTS, ETC, PROPER
;COMPLETION MAY NOT BE
;ACHJEVED, THEREBY CAUSING
;PROBABLE "HANG"
;2. SP ERROR MAY BE INDICATED
;WHENREALLYAMEMORYWAS
;BAD.

NO DST

IMM,O,LDMAR

;DO COMPARISON BETWEEN MEMORY +SP
;START AT MEMORY LOC. 0.

COMP

MEMl,SPO
DSP.Cl

BR,INCA,SPO
DSPZ31
ALWAYS DSP.Z2
MEM
IMM,O
SP

z
DSPZ31:
DSP.Z3:

z
DSP.CI:

DPS.C2:

DSP.C3:

DSP.C4:

DSP.C5:

;NOW YOU MUST CHECK OUT
;THE SCRATCH PADS AGAINST THE
;ERROR #33 IF SPO BAD
;CONTENTS OF THE MEMORY. SINCE
;THIS IS A SCRA TCHPAD TEST,
;ASSUME THAT MEMORY IS GOOD.
;ERROR #34 IF SPI BAD
;YOU'LL FIND OUT LATER IF THAT
;WAS A BAD ASSUMPTION.

CERROR
ALWAYS DSPERR
COMP
MEMl,SPl
z
DSP.C2
CERROR
ALWAYS DSPERR
MEMI,SP2
COMP
z
DSP.C3
CERROR
ALWAYS DSPERR
COMP
MEMl,SP3
z
DSP.C4
CERROR
ALWAYS DSPERR
MEMI,SP4
COMP
z
DSP.C5
CERROR
ALWAYS DSPERR
COMP
MEMI,SP5
z
DSP.C6
CERROR
ALWAYS DSPERR

'
;ERROR
#35 IF SP2 BAD

'
;ERROR
#36 IF SP3 BAD

'
;ERROR
#37 IF SP4 BAD

'
;ERROR
#40 IF SP5 BAD

A-7

DSP.MI (Cont):

DSP.M2:

BRWRTE IMM,20
SP
BR,SUBOC,SPO
z
DSP.EX
MEM
IMM,177
ALWAYS DSP.Z3
BROTAT
MEM
BR,SELB
ALWAYS DSP.Z3

;LOOK TO SEE IF YOU'RE DONE
;' YES THIS EXIT

'
;ROTATE
RIGHT

DSP.EX:

A.S.6 ALU Test
The ALU test tests all ALU functions.
ADD
ADDC
SUBC
INCA
APL USC
TWOA
TWO AC
DECA
SELA
SELB
AORNB
AANDB
AORB
AX ORB
SUB
SU BOC
DALU:

DALU.l:

BRWRTE
OUT

AANDB*
A AND B* W /CARRY
A-B* W /BORROW
A+l*
A+CARRY*
A+A
A+A+CARRY*
A-1 *
SELECT A SIDE OF ALU
SELECT B SIDE OF ALU
A<ORNOT>B
A<AND>B
A<OR>B
A<EXCLUSIVEOR>B
-B(TWO'S COMPLEMENT)
A-B (ONE'S COMPLEMENT)
IMM,151
BR,SELB,OBSEL6

SP
BR WR TE
BR WR TE
BR WR TE

IMM,l,SPI
IMM,377
BR,ADD,SPI
BR,ADDC,SPI

;SPJ=I
;BREG=377
;BREG =O,SPJ = J,C= I
;BREG =2,SPI = J ,C=O

BR WR TE
SP
BRWRTE
SP
SP
SP
SP
SP
SP
SP
SP
SP
BRWRTE
SP
BR WR TE

BR,ADD,SPI
IMM,3,SP3
BR,SUB,SP3
BR,TWOA,SP3
BR,DECA,SP3
IMM,377,SPl7
BR,INCA,SP17
BR,A PLUSC,SPI
BR,DECA,SPl7
BR,TWOAC,SPI
BR,TWOAC,SPI
BR,APLUSC,SPI
IMM,O
BR,ADDC,SPI
IMM,11

;BREG=3
;SP3=3
;BREG=O
;SP3=6
;SP3=5
;SPJ7=377
;SPJ7=0,C= I ;SETS CARRY
;SPJ=2,C=O
;SPJ7=377,C=I ;SETS CARRY
;SPJ=5, C=O
;SP!= JO (NO CARRY)
;SP!= JO (NO CARRY)
;BRG=O
;SP!= JO (NO CARRY)
;BRG= J J,SPJ7=377

A-9

DALU. l (Cont):
SP
SP
SP
BR WR TE
SP
BR WR TE
BR WR TE
SP

BR,INCA,SP17
BR,SUBC,SPI
IMM,6,SP6
IMM,3
BR,SUBOC,SP6
IMM,O
BR,SELA,SP6
BR,INCA,SPI

BRWRTE
BR WR TE
BR WR TE
SP
BR WR TE
SP
BR WR TE
SPBR

BR,ADD,SPl
BR,ADD,SP17
BR,ADD,SP3
IMM,7,SP7
BR,SUB,SP7
BR,SELB,SPO
BR,SELB,SPO
BR,DECA,SPO
DALU.3

;SP17=0, C= I
;1-B W /C SPI =377
;SP6=6
;BR6=3
;SP6=2 (ONE'S COMP SUB)
;BRG=O
;BRG=2

,
;SPl =O,SPI 7 =O,SP3 =5
;BRG=2
;BRG=2
;BRG=7
;SP7=7
;BRG=7
;SPO=O
;SPO=O
;BR=377
;IF BR=377 NEXT TEST. ELSE
;SOMEWHERE AN ALU M FUNCTION
;OCCURRED.
;ERROR #53 IF ALU BAD

CERROR
DALU.2:

ALWAYS

;HANG HERE, ONE ALU ERROR.

DALU.2

The following section is broken out for logic testing of the ALU AORNB, AANDB, AORB, and
AXORB functions.
DALU.3:

BRWRTE
SP
BR WR TE
BR WR TE
SP
BR WR TE
SP
BWRITE
SP
BWRITE
SP
SP

IMM,253
BR,SELB,SPO
IMM,221
BR,AANDB,SPO
BR,SELB,SPIO
IMM,160
BR,AORB,SPIO
BR,AORNB,SPIO
BR,SELB,SPO
IMM,377
BR,AXORB,SPO
BR,DECA,SPO
DALU.4

CERROR
ALWAYS

DALU.2

;BINARY 10 IOI 011 {253)
;PUT IN SPO (253)
;BINARY 10010001 {221)
;AND BRG = 201
;SPl0=201;10 000 001
;BIG= 160 01 110 000
;SPI0=361 11 110 001
;BR=377 11 111 111
;SP0=377
;BREG=377
;SPO=O, BR=377
;SP0=377 Z BIT SET
;BRANCH IF Z SET
;ERROR #54 IF ALU BAD
;ELSE GO TO ERROR

DALU.4:

;END TEST

A.5.7 Memory Test (Moving Inversion)
This memory test uses the modified moving inversion.
DMEMS:

BRWRTE
OUT
NO DST
NO DST
SP

IMM,222
BR,SELB,OBSEL6
IMM,O,LDMAR
IMM,O,LDMAPG
IMM,O,SPO

;TEST NUMBER.
'

;LOAD LOW MAR TO ZERO.
;HIGH MAR ZEROED.
;NOW ZERO WHOLE MEMORY.

A-10

DMEMSl:

SPBR
BR4
MEM
ALWAYS

IBUS,MARH,SP 1
DMEMS3
MEMl,SELA,SPO
DMEMSI

;SEE IF THROUGH MEMORY
;IF OVERFLOW BIT SET, YES
;ELSE WRITE.lERO INTO MEM.

DMEMS3:

BRWRTE
SP

IMM,200
BR,SELB,SPI

;GET STARTING PATTERN
;PUT INTO SP!
;SPO WILL CONTAIN OLD PATTERN

DMEML:

NO DST
NO DST

IMM,O,LDMAR
IMM,O,LDMAPG

;NOW LOAD ADDR ZERO

DMEML2:

BR WR TE
BR4
BR WR TE
NO DST

IBUS,MARH
DMEML4
MEMX,SELB
BR,SUBOC,SPO
DMEML3
BR,SELB,OBSEL5
BR,SELA,SPO
BR,SELB,OBSEL3

OUT
BRWRTE
OUT
CERROR
ALWAYS

DMEML3:

MEM
BR WR TE
NO DST

OUT
BR WR TE
OUT
CERROR
ALWAYS
DMEML4:

BR WR TE
BRO
SP
BRSHFT
SP
ALWAYS

DMEMER: ALWAYS

DMEMER

SELA,SPI
MEMl,SELB
BR,SUBOC,SPI
DMEML2
BR,SELB,OBSEL5
BR,SELA,SPl
BR,SELB,OBSEL3

;READ MEM LOCATION
;SEE IFOLD PATTERN IS RETAINED
;IF YES WILL BRANCH
;WRITE BAD DATA IN SEL5
;GETGDDAT
;PUT IN BSEL3
:OLD PATTERN WAS NOT RETAINED
;POSSIBLE MEMORY DUAL ADDRESS ERROR.
;ERROR #55 IF MEMORY BAD
;WRITE NEW PATTERN
;READ NEW PATTERN
;WRITE OK?
;YES LOOP.
;BAD-BODA T TO BSEL5
;GETGDDAT
;PUT IN BSEL3
;ERROR #56 IF MEMORY BAD

DMEMER
SELA,SPI
DMEME
BR,SELB,SPO
BR,SELB,SPI
DMEML
DMEMER

;GET NEW PATTERN
;IF BIT TESTED, EXIT
;ELSE MAKE IT THE OLD PATTERN
;THEN ROTATE PATTERN RIGHT
;THEN WRITE NEW PATTERN

;LOOPHEREALWAYSON ERROR
;ESCAPE HERE ON TEST COMPLETE

DMEME:

A.5.8 Memory Test (Dual Addressing)
This test is broken into two parts. Part one ensures that addresses within a page will not dual address
against each other. Part two ensures that the pages do not dual address against one another. This
method is used because 12-bit addressing is implemented and memory storage is only 8-bits wide.
DOATST:

BRWRTE
OUT
BR WR TE
SP

IMM,132
BR,SELB,OBSEL6
IMM,O
BR,SELB,SP2

;TEST NUMBER
;PICK UPCONSTANTS

A-11

DOATST (Cont):

DOLi:

DOI:

DOL2:

NO DST
NO DST

IMM,O,LDMAR
IMM,O,LDMAPG

;LOAD ADDRESS ZERO.

MEMINC

SELA,SP2

SP
BR WR TE
BR4
BRWRTE
ALWAYS

BR,INCA,SP2
IBUS,MARH
DOI
IMM,O
DOLi

;WRITE EACH MEMORY LOCATION WITH ITS
;OWN ADDRESS.
;UPDATEADDR.
;MAKE SURE YOU DON'T REACH OVERFLOW.
;IF YOU DO, EXIT THIS LOOP.

NO DST
NO DST
BR WR TE
SP

IMM,O,LDMAR
IMM,O,LDMAPG
IMM,O
BR,SELB,SPl

BRWRTE
NO DST

MEMl,SELB
BR,SUBOC,SPl

002
BR,SELB,OBSEL5
BR,SELA,SPl
BR,SELB,OBSEL3

OUT
BRWRTE
OUT
CERROR

;ELSE DO NEXT ADDRESS.
;LOAD ADDRESS ZERO AGAIN.
;PICK UPCONSTANTS.

;READ MEMORY
;READ MEMORY ADDRESS, SEE IF IT
;CONTAINS ITS OWN ADDRESS BY
;COMPARING IT AGAINST OUR COUNTER.
;IT WILL BE 377 AFTER SUBTRACT.
;PUT EXPECTED INTO BSEL2

;DUAL ADDRESS ERROR #57
;MOST PROBABLY HERE.

DOU:

ALWAYS

DOU

002:

SPBR
BRWRTE
BR4
BRWRTE
ALWAYS

BR,INCA,SPl
IBUS,MARH
DOA
SELA,SPI
DOL2

;UPDATE ADDRESS.
;SEE IF YOU'RE THROUGH.
;WHEN OVERFLOW SET/

NO DST
NO DST

IMM,O,LDMAR
IMM,O,LDMAPG

;LOAD ADDRESS ZERO AGAIN.

BRWRTE
SP

IMM,O
BR,SELB,SPO

;PICK UP CONT

MEM

SELA,SPO

;NOW WRITE THE CURRENT PAGE
;NUMBER INTO THE JST ADDRESS OF EACH
;PAGE-LATER READTHEM BACK.

SPBR
BR4
NO DST
BR WR TE
ALWAYS

BR,INCA,SPO
~PDATEPAGENUMBER
DOA2
;ON OVERFLOW, EXIT THIS LOOP.
BR,SELA,SPO,LDMAPG
IMM,O
DOA!

BRWRTE
SP

IMM,O
BR,SELB,SPO

DOA:

DOAJ:

DOA2:

;LOOP UNTIL DONE.

;PICK UPCONSTANTS.

A-12

BR,SELA,SPO,LDMAPG
MEMX,SUBOC,SPO
;SEE IF CONTENTS AGREE
;WITH WHAT WAS EXPECTED
;FOR IT.
DOAS

OUT

BR,SELB,OBSEL3

BR WR TE
OUT
CERROR

MEMX,SELB
BR,SELB,OBSELS

DOA4:

ALWAYS

DOA4

DOAS:

SPBR
BR4
ALWAYS

BR,INCA,SPO
DOA6
DOA3

;UPDATE PAGE NUMBER.
;ON OVERFLOW EXIT.
;ESX

BR WR TE
OUT

IMM,305
BR,SELB,OBSEL6

;CODE SPECIFYING COMPLETION OF
;INTERNAL MICRO-DIAGNOSTICS.

DOA3:

NO DST
NO DST

;ERROR-PAGE NUMBER IN BSEL2
;FOR ALL TO SEE.
;READ BAD DATA
;PUT INTO BSELS
;PAGE DUAL ADDRESS ERROR #60

DOA6:
DIADON:

Microdiagnostics END, user INIT code starts.
A.5.9 Field Branch Extended Tests
The following tests are used by the Extended Branch Tests (Section A.5.3). If each test does not return
to the relevant Extended Branch Test given in Section A.5.3, the program will loop indefinitely.
FIELD 0 Branch Extended Test
DFLDO:
5$:

JMPEXT DBREXI
CERROR
ALWAYS 5$

;RETURN TO TEST
;ERROR #61 IF OBREX I FAILS
;LOOP ON ERROR

This routine is placed in address range 000 - 777.
FIELD I Branch Extended Test
DFLDI:
5$:

JMPEXT DBREX2
CERROR
ALWAYS 5$

;RETURN TO TEST
;ERROR #62 IF DBREX2 FAILS
;LOOP ON ERROR

This routine is placed in address range 1000 - 1777.
FIELD 2 Branch Extended Test
DFLD2:
5$:

;RETURN TO TEST
;ERROR #63 IF DBREX 3 FAILS
;LOOP ON ERROR

JMPEXT DBREX3
CERROR
ALWAYS 5$

This routine is placed in address range 2000 - 2777.
A-13

FIELD 3 Branch Extended Test
DFLD3:
5$:

JMPEXT DBREX4
CERROR
ALWAYS 5$

;RETURN TO TEST
;ERROR #64 IF DBREX4 FAILS
;LOOP ON ERROR

This routine is placed in address range 3000 - 3777.
FIELD 4 Branch Extended Test
DFLD4:
5$:

JMPEXT DBREX5
CERROR
ALWAYS 5$

;RETURN TO TEST
;ERROR #65 IF DBREX5 FAILS
;LOOP ON ERROR

This routine is placed in address range 4000 - 4777.
FIELD 5 Branch Extended Test
DFLD5:
5$:

JMPEXT DBREX
CERROR
ALWAYS .5$

;RETURN TO TEST
;ERROR #66 IF DBREX FAILS
:LOOP ON ERROR

This routine is placed in address range 5000 - 5777.
A.6 INTERFACE DIAGNOSTICS
Interface diagnostics are only run after completion of internal diagnostics. These diagnostics are
started by an external exercisor, the CPU code designed to interface with this code. Any attempt to run
the interface diagnostic code without the proper external software could prove fatal to these tests. All
DMPJ I UNIBUS registers are redefined.
TEST A - UNIBUS Window Register Test
•
•
•
•

Write all ones in the registers
Enter after call
Exit when CPU puts a zero into BSEL 0
11 code should look at data when BSEL 7 is equal to 377

DTSTA:

BRWRTE
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IMM,377
BR,SELB,OINCON
BR,SELB,OOCON
BR,SELB,OLIN EN
BR,SELB,OPORTI
BR,SELB,OPORT2
BR,SELB,OPORT3
BR,SELB,OPORT4

:PICK UP ALL ONES CONSTANT
;PUT INTO ALL WINDOWS

DTSTAL:

IBUS,INCON,SPO
DTSTAL

:READ BSELO
;LOOP WHILE= 377

TEST B - UNIBUS Under Register Test
•

Write all zeros into the register

•

Enter from last test completion
A-14

•

Write all registers to zero (except main)

•

Loop until PDP-11 verifies data, and either puts code 377 into bit 7 set (remaining bits = 0),
or into BSEL 0 to loop on the last two tests

DTSTB:

BRWRTE
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IMM,O
BR,SELB,OINCON
BR,SELB,OOCON
BR,SELB,OLINEN
BR,SELB,OPORTI
BR,SELB,OPORT2
BR,SELB,OPORT3
BR,SELB,OPORT4

;PATTERN=O
;WRITE EACH WINDOW TO ZERO

DTSTBL:

SPBR
BR7
ALWAYS

IBUS,INCON,SPO
DTSTBE
DTSTBL

;READ BSELO
;IF
;LOOP UNTIL BIT 7 SET

SPBR

I BUS,INNCON ,SPO
DTSTC
DTSTA
DTSTBL

;REREAD BSELO IN CASE OF CHANGE
;IF 377THEN NEXT TEST
;IF BIT7 SET LOOP LAST TWO TESTS
;ELSE, LOOP FOR PDP-I I INDICATOR

DTSTBE:

BR7
ALWAYS

TEST C - Interrupt the PDP-11 at Vector XXO
•
•
•
•
•
DTSTC:

DTSTCI:

To enter this test, the PDP-11 code must have exited Test B
The PDP-11 must set up interrupt vector XXO
The PDP-11 must set BSEL 3 equal to 377
The. microcode, upon seeing 377, generates an interrupt
The microcode then exits test
SPBR
Z

IBUS,LINENM,SPO
DTSTCI

ALWAYS

DTSTC

BRWRTE

IMM,200

OUT

BR,SELB,OBR

;READ BSEL3
;WHEN PDP-I I WRITES ITT0377,
;THEN ADVANCE
;ELSE, LOOP PDP-I I NOT READY!
;PICK UP INTO ENABLE BIT
;WRITE INTERRUPT ENABLE
;PUT IT IN INTERRUPT REG
;UCPU NOW INTERRUPTS

TEST D - Interrupt the CPU at Vector XX4
•
•
•
•
•
DTSTD:

To enter this test, the CPU must have exited Test C
The PDP-11 must set up the interrupt vector at XX4
The 11 code must set BSEL 3 equal to 0
The microcode upon seeing BSEL 3 equal to 0, generates an interrupt at XX4
The microcode then exits test
SPBR

IBUS,LINENM,SPO
DTSTD

;LOOK AT BSEL3
;WAIT TILL IT TURNS ZERO (OR NON-377)

A-15

DTSTD (Cont):
BRWRTE
OUT

;PICK UP I.E. AND INTR 4 BITS
;PUT IN INTERRUPT REG
;RUCPU NOW INTERRUPTS

IMM,300
BR,SELB,OBR

TEST E - Non-Processor Request (NPR) IN/OUT Test
•

To enter this test, the CPU must first have run Test D

•

The PDP-11 code must set the address of the input data area in BSEL 4 and 5
(ADDRXXXXX4)

•

The PDP-11 code must set the address of the out data area in BSEL 6 and 7
(ADDRXXXXX6)

•

The PDP-11 code must set BSEL 0 to a 0

•

The micro-CPU reads the data from one address in the block via NPR, and outputs the data
to one location equal to the OUT BLOCK

•

The micro-CPU performs the previous step 16 times

•

When completed, the micro-CPU will put a 377 into BSEL 0. If an error is detected, the
microcode will "hang"

•

The PDP-11 puts a 260 into BSEL 0 to exit test, (or) goes back to Step 4 (CPU code i;nust set
BSEL 0 to 0)

DTSTE:

SPBR
SPBR
BR7
OUT
OUT
BR WR TE
OUT

IBUS,INCON,SPO
DTSTE
I BUS,INCON ,SPO
DTSTF5
IBUS,PORTI,IBAI
IBUS,PORT2,IBA2
IMM.I
BR,SELB,ONPR

;WAIT TILL PDP-I I IS READY
;IF= 377, THEN LOOP
;IT CHANGED! REREAD, IF=200THEN
;EXIT TEST
;READ IN NPR REG, PUT INTO
;ADDR REG
;PICK UPNPR REQUEST BIT
;CAUSENPR

BR WR TE
BRO

IBUS,NPR
DTSTEI

;READ BACK NPR REG
;LOOP WHILE NPR

OUT
OUT
BRWRTE
OUT

I BUS,PORT3,0BA I
IBUS,PORT4,0BA2
IBUS,INDA TI
BR,SELB,OUTDA I

;WRITE OUTPUT ADDRESS

BR WR TE
OUT

IBUS INDAT2
BR,SELB,OUTDA2

BR WR TE
OUT

IMM,2I
BR,SELB,ONPR

DTSTEI:

;READ LOW BYTE OF INPUT DATA
;PUT IN LOW BYTE OF DATA
;TO BE OUTPUTTED
;READ HIGH BYTE OF INPUT DATA
;PUT IN HIGH BYTE OF DATA
;TO BE OUTPUTTED
;SETOUTNPR
;DOIT

A-16

DTSTE2:

DTSTFS:

BR WR TE
BRO
BRWRTE
OUT

IBUS,NPR
DTSTE2
IMM,377
BR,SELB,OINCON

ALWAYS

DTSTE

ALWAYS

INIT

;READ BACK NPR REG
;LOOP WHILE NPR IN PROGRESS
;PICK UP 377

;END TO TESTS.

A-17

APPENDIX B
INTEGRATED CIRCUIT DESCRIPTIONS

Selected Integrated Circuits (ICs) shown in the M8207 Print Set are provided in this Appendix as an
aid in troubleshooting to the IC level. The descriptions include one or more of the following:
pin/signal designations, equivalent logic block diagrams, logic symbols, and truth/function tables.
The following ICs are included:

2147 - 4096 XI-BIT STA TIC RAM
74Sl38- DECODER MULTIPLEXER
74Sl51 - DATA SELECTOR/MULTIPLEXER
74LS153 - DUAL4-LINE-TO-l-LINE DATA SELECTOR/MULTIPLEXER
74Sl57 - QUAD 2-LINE-TO-l-LINE DATA SELECTOR/MULTIPLEXER
74Sl58 - QUAD 2-LINE-TO-l-LINE DATA SELECTOR/MULTIPLEXER
74LS174 - HEX D-TYPE FLIP-FLOPS WITH CLEAR
74Sl75 - QUAD D-TYPE FLIP-FLOPS WITH CLEAR
74Sl81 - 4-BlT ARITHMETIC LOGIC UNIT, ACTIVE HIGH DATA
74Sl89 - 64-BIT RANDOM ACCESS MEMORY 16 X 4
74LSI94 - 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
74S240-0CTAL INVERTER AND LINE DRIVER WITH 3-STATEOUTPUT
74S241 - OCTAL BUFFER AND LINE DRIVER WITH 3-STATE OUTPUT
74S251- DATA SELECTOR/MULTIPLEXER WITH 3-STATEOUTPUTS
74LS257- QUAD2-LINE-TO-l-LINE DATA SELECTOR/MULTIPLEXER
74S273 - OCTAL D-TYPE FLIP-FLOP WITH CLEAR
74LS374- OCTAL D-TYPE TRIGGERED FLIP-FLOPS
8136 - 6-BIT UNIFIED BUS COMPARATOR
82SI 12- HIGH SPEED 8 X 4 MULTIPORT RAM
82Sl91 - 16,384-BIT2K X 8 BIPOLAR PROM
93Sl6 - 4-BIT BINARY COUNTER
DCOI3 - DEC UNIBUS CHIP

B-1

2147 - 4096 X I-BIT STATIC RAM
The 2147 is a 4096-bit static random access memory organized as 4096 words by I-bit using HMOS
technology. The data is read out nondestructively and has the same polarity as the input data. A data
input and a separate three-state output are used.

BLOCK DIAGRAM

Ao----1

LOGIC SYMBOL

2147

_ _1-iAQ

- -2-iAl

4---Vcc

---GND

A2----1

---3~A2

MEMORY ARRAY
64 ROWS
64 COLUMNS

ROW
SELECT

- -4-iAJ
_ ......5~A4

A3----1

A4 _ __

......6~A5
17 A6

7-OUT-..

16 A7
15 AS

14 A9

A"----i

__
13-iA10
12-tA11
--

DIN

>---Dour

COLUMN 1/0 Cl RCUITS

@
A6

@
A'

@
AB

@
A9

" Ya j10

COLUMN SELECT

@
AIO

@
A' I

TRUTH TABLE

cs WE

MODE

OUTPUT

POWER

NOT SELECTED

HIGH Z

STANDBY

WRITE

HIGH Z

ACTIVE

READ

Dour

ACTIVE
MK-0688

B-2

BLOCK DIAGRAM

74Sl38 - DECODER MULTIPLEXER

l1 5) DO

The 74S 138 decodes one of eight lines depending on the conditions at the three binary select inputs and
the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external
gates or inverters when expanding.

LOGIC SYMBOL
G1

74S138

(13) D2

ENABLE
INPUTS

D1
D2

SELA
2
3

G2A
G2B

(12) 03

SELB

DATA
OUTPUTS

D4
SELC

G2A
G2B
G1

Vee= PIN 16
GND =PIN 8
(9)

SELECT
INPUTS

FUNCTION TABLE
INPUTS
ENABLE
G1

G2*

L
H
H
H
H
H
H
H
H

x x x
x x x

L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

(7)

OUTPUTS

SELECT
A

L
H
L
H
L
H
L
H

DO D1

D2 D3 D4 D5 D6 D7

H
H
L
H
H
H
H
H
H
H

H
H
H
H
L
H
H
H
H
H

H
H
H
L
H
H
H
H
H
H

H
H
H
H
H
L
H
H
H
H

H
H
H
H
H
H
L
H
H
H

H
H
H
H
H
H
H
L
H
H

H
H
H
H
H
H
H
H
L
H

H
H
H
H
H
H
H
H
H
L

IC-741388

*G2 = G2A + G2B
H =HIGH LEVEL, L =LOW LEVEL, X =IRRELEVANT

B-3

74Sl51 - DATA SELECTOR/MULTIPLEXER
The 74S 15 l monolithic data selector /multiplexer contains full on-chip binary decoding to select the
desired data source. The 74S l 51 selects one of eight data sources and has a strobe input which must be
at a low logic level to enable the device. A high level at the strobe forces the fO output high, and the fl
output (as applicable) low.

74$151 TRUTH TABLE
Inputs

Outputs

STB

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1

x
x
x

x
x
x
x

x
x

0
1

x
x
x
x
x
x

x
x
x

x
x

x
x
x
x

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
0
1
0
1
0
1
0
1
0
1
0
1

x
x
x

x
x
x
x
x

x
x
x
x

x
x

x
x
x
x
x

x
0
1

x
x
x
x

0
1

x
x

x
x
x

x
x

0
1

x
x
x
0
1

x
x

x
x
x
x

x
x
x

When used to indicate an input. X = irrelevant.

B-4

x
x
x

x
x

x
x
x
x
x
0
1

x
x

x
x
x
x
x
x
x
x
x

x
x
0
1

y
1

1
0
1
0
1
0
1
0
1

0
1
0
1
0
1
0

BLOCK DIAGRAM
STROBE (7)_,.~
(ENABLE ) v

--!/"

J4)

Do ..,

- ( 3)

Dt'-'

LOGIC SYMBOL

,..(2)

...,.

STB

12
13
14
15

07
- ( t)

5
DATA
INPUTS

...,,

( 15)

r-1f-4

3
4

v -. ,

745151
2

~~ OUTPUT W

1---1f-4

r=J

,..(14)

....

(6),..
"" OUTPUT

,.._( t 3)
...,,

r-1f-4

52
9

Sl
10

_(12)

I-+-

IC-741518

.. ~
v ..
j11)

Vee= PIN 16
GND=PIN 8

DATA
SELECT

.., v

(10) " " '

~
V""

(BINARY)

IC-74151A

B-5

74LS153 - DUAL 4-LINE-T0-1-LINE DATA SELECTOR/MULTIPLEXER
The 74LS 153 monolithic data selector/multiplexer contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR invert gates. Separate strobe
inputs are provided for each of the two four-line sections.

LOGIC SYMBOL

74153
03
04

74153
13

05
BO
06

51 so

Vee
PIN 16
GND =PIN 08

02 14 01

S1 SO

02 14 15

STBO

ADDRESS
INPUTS

STB1

DATA INPUTS STROBE OUTPUT

A B

STB

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

x x x x
L x x x

H
L
L

L
L
H
L
H
L
H
L
H

x x x
x L x x
x H x x
x x L x
x x H x
x x x L
x x x H

l
L
L
l

l
L

ADDRESS INPUTS SO AND S1 ARE COMMON TO BOTH
SECTIONS: H=HIGH LEVEL, L=LOW LEVEL, X=IRRELEVANT

B-6

STROBE 0
(1)
(ENABLE) o-AO-(S-)--.a1

BO (5)
DATA 1

co (4)

(l)

DO (3)

OUTPUT~

A1 (10)

B 1 ( 11)

DATA 2

(S)

C1 (12)

VCC =PIN 16
GND =PIN 08

D1 (13)

STROBE 1
(ENABLE)

(15)

IC-74153

B-7

74Sl57 - QUAD 2-LINE-TO-l-LINE DATA SELECTOR/MULTIPLEXER
The 74Sl57 monolithic data selector/multiplexer contains inverters and drivers to supply full on-chip
data selecti<:m to the four output gates. A separate strobe input is provided. A 4-bit word is selected
from one of two sources, and routed to the four outputs (true data).
BLOCK DIAGRAM
AO

11
f2

B2o-~~-t-~~-+--+--t

B3o-~~-+~~-+-+--t

so
Vee= PIN 16
GND =PIN 8

LOGIC SYMBOL
74S157
13
B3
E f3 12
14 A3
10

B2
11
A2

6
B1
5 A1

BO
2 AO
STB

TRUTH TABLE

INPUTS

OUTPUT.

STROBE

SELECT

H
L
L
L
L

L
L
H
H

LX
HX
XL
XH

7
4

L
L
H
L
H

H =HIGH LEVEL, L =LOW LEVEL
X =IRRELEVANT

·,5
IC-74157

B-8

74Sl58 - QUAD 2-LINE-T0-1-LINE DATA SELECTOR/MULTIPLEXER
The 74S158 monolithic data selector/multiplexer contains inverters and drivers to supply full on-chip
data selection to the four output gates. A separate strobe input is provided. A 4-bit word is selected
from one of two sources, and routed to the four outputs (inverted data).
BLOCK DIAGRAM
SELECT
(SO)
(1)

ENABLE
(STB)

(1 S)

(2)

BO
(3)

(5)

(6)

( 11 l

A3
(14)

(10)

B3
(13)

PIN 16 =Vee
PIN B=GND

FUNCTION TABLE

LOGIC SYMBOL
13
14

74S158
B3
A3

STROBE

SELECT

x
x
x

x
x

4-BIT
WORD
INPUTS

OUTPUTS

B1
5
3

OUTPUT Y

INPUTS

H
L..

H =HIGH LOGIC LEVEL
L =LOW LOGIC LEVEL
X =IRRELEVANT
MK-0658

B-9

74LS174 - HEX D-TYPE FLIP-FLOPS WITH CLEAR
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop
logic. All have a direct clear input.
BLOCK DIAGRAM
lnformatipn at the D inputs meeting the setup time requirements is transferred to the R outputs on the positive-going DO
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition ·
time of the positive-going pulse. When the clock input is at
either the high or low level, the D input signal has no effect at
the output.

(3)

(2)

CLOCK
CLEAR

(4)

LOGIC SYMBOL

R0(1)

(5)
R 1( 1)

74LS174
14
13
11
6
4
3

R5(1)

D4 R4(1)
D3

R3(1)

D2 R2(1)
D1

R1(1)

RO(l)

CLOCK
CLEAR

10
7
5

(6)

R2(1)

2
CLOCK
CLEAR

CLK CLK

D~·

FUNCTION TABLE
(EACH FLIP-FLOP)

~-1--t""JCLOCK

OUTPUTS

INPUTS
CLEAR CLOCK D

CLEAR

H
H

t
t

H
L

(10)
......--... R3(1)

( 111

n--+---+--1

H-HIGH LEVEL (STEADY STATE)
L-LOW LEVEL (STEADY STATE)
X-IRRELEVANT
t-TRANSITION FROM LOW TO HIGH
Oo-THE LEVEL OF R BEFORE THE INDICATED
STEADY STATE INPUT CONDITIONS WERE
ESTABLISHED

(13)

R4(1)

1---+--<:"J CLOCK
CLEAR

D51.J-_
(14) _ _ _.....

.-(_15_1\ J R5(1)

PIN (16) =Vee. PIN (8) = GND
MK-0660

B-10

74Sl75 - QUAD D-TYPE FLIP-FLOPS WITH CLEAR
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop
logic. All have a direct clear input and feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the R outputs on the positive-going of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse. When the clock input is at either the high or
low level, the D input signal has no effect at the output.
BLOCK DIAGRAM

LOGIC SYMBOL
13

R3 ( 1 l

R2( 1 l

DATA
INPUTS

R2(0)

R 1( 1 l

RO( 1 l

CLK

OUTPUTS
Dt (5 l

R1
CLK (0)
CLEAR

D2 n.(_12_)~_.__--11

FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
CLEAR CLOCK
L

H
H

H
L

L
H
L

Oo Oo

R 2 ( 10)
(1)

R2
..----+.--4n1CLK ( O)
CLEAR

OUTPUTS
D
R
R

RO(O)
CLR

RO (3)
CLK (0)
CLEAR

R1(0)
4

74Sl75
Dl

(4)

R3(0)
12

H
L

D3 (13)

R3
( 1)

H=HIGH LEVEL (STEADY STATE)
R3
L=LOW LEVEL (STEADY STATE)
CLOCK (g)
X>-------~-CJCLK (0)
X= IRRELEVANT
CLEAR
t =TRANSITION FROM LOW TO
HIGH LEVEL
Q =THE LEVEL OF R BEFORE
(1)
O THE INDICATED STEADY-STATE CLEAR o--~
INPUT CONDITIONS WERE
ESTABLISHED.
Pin (16)= Vee. Pin (8)=GND
IC- 741759

B-11

74Sl81 - 4-BIT ARITHMETIC LOGIC UNIT, ACTIVE HIGH DATA
The 74Sl81 performs up to 16 arithmetic and 16 logic functions. Arithmetic operations are selected by
four function-select lines (SO, Sl, S2, and S3) with a low-level voltage at the mode control input (M),
and a low-level carry input. Logical operations are selected by the same four function-select lines
except that the mode control input (M) must be high to disable the carry input.

OUTPUTS
CARRY
GENERATE

COM PAR ATOR

CARRY
PROPAGATE

CARRY
14

A= B

COUT

15
p

83
19

20
21
WORD
INPUTS

A3
82

f2 11

A2
745181

22
23
01
02

FUNCTION
OUTPUTS

A1
BO

S3
03

S2
04

S1
05

CIN

VCC=PIN24
GND=PIN12

MODE
CARRY
INPUT
FUNCTION
SELECT
INPUTS
IC-74181A

B-12

74181

74181
TABLE OF ARITHMETIC OPERATIONS

TABLE OF LOGIC FUNCTIONS

Function Select
S1
so
S2

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

Output Function
Positive Logic
Negative Logic
t =A
f =AB
t=A+B
f =Logical 1
f=A+B
t =8
f=A@B
f =A+ B
t =AB
f=A(±)B
f =B
f =A+B
f =Logical 0
f =AB
f =AB
f =A

With mode control (M) high: Cin irrelevant
For positive logic: logical 1 = high voltage
logical 0 = low voltage
For negative logic: logical 1 = low voltage
logical 0 = high voltage

S3
L
L
L
L
L
L
.L
L
H
H

H
H
H
H
H
H

Function Select
S1
so
S2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L

H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L

Output Function
Low Levels Active
f =A minus 1
f =AB minus 1
f =AB minus 1
f = minus 1 (2's complement)
f = A plus [A + BJ
f = AB plus [A + BJ
f = A minus B minus 1
f=A+B
f =A plus [A + BJ
f =A plus B
f =AB plus [A+ B]
f =A+ B
f =A plus At
f =AB plus A
f =AB plus A
f=A

High Levels Active
f =A
f=A+ B
f=A+ii
f = minus 1 (2's complement)
f =A plus AB
f =[A+ BJ plus AB
f = A minus B minus 1
f =AB minus 1
f =A plus AB
f =A plus B
f = [A + B] plus AB
f =AB minus 1
f =A plus At
f = [A + BJ plus A
f = [A + B] plus A
f =A minus 1

With mode control (M) and Cin low
t Each bit is shifted to the next more significant position.

IC-741818

B-13

74Sl89 - 64-BIT RANDOM ACCESS MEMORY 16 X 4
The 74Sl 89 is a 64-bit random access memory organized as 16-words by 4-bits providing inverted
three-state outputs.

CLOCK

ENABLE

()

_o_

4 ,.,J

""'I DO

6,..
INPUT

.... Dl

74S189

--1!!.d
....., D2
12 ....
.... D3

M2
M3

Al
15

A2
14

5
7

OUTPUT

( INVERTED)
INPUT

A3
13
ADDRESS

0-7

ADDRESS

8-15
MK-0684

B-14

74LS194 - 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
The 74LS194 bidirectional shift register features parallel inputs, parallel outputs, right-shift and leftshift serial inputs, operating mode control inputs, and a direct overriding clear line. The register has
four distinct modes of operation:
•
•
•
•

Parallel (broadside) load
Shift right (in the direction RO toward R3)
Shift left (in the direction R3 toward RO)
Inhibit clock (do nothing)

LOGIC SYMBOL
74LS194
6

5
PARALLEL {
INPUTS

4
3

12
13
14
15

1 ... 1 - - - - - - - - - CLR

SHIFT
{
SERIAL INPUTS
MODE {
CONTROL
INPUTS

DSR

7
9

DSL

so
Sl

CLK

8-15

}

PARALLEL
OUTPUTS

74LSJ94 - 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER (Cont):

PARALLEL INPUTS

BLOCK DIAGRAM
01
4

02
5

03
6

SHIFT
RIGHT _ _
2 _ __
SERIAL

SHIFT
LEFT
r--+-++-----1--- SERIAL
7

INPUT

>---IS

.----OC>CK
"---~--tR

"----+---1R
CLEAR

CLEA
CLOCK
CLEAR

13
R2

12
R3

PARALLEL INPUTS
FUNCTION TABLE
OUTPUTS
CLEAR

MODE

CLOCK

SERIAL
LEFT

RIGHT

x
x
x
x
x

x
x
x

x
x

x x
x x

H
L

x
x

x
x
x

x
x
x
x
x

x x
x x
x x
x x
x x

x x
x x

H
H

H
L
L

H
H
H

t
t
t

L
H
H

PARALLEL

x
x

oAo oso Oco ooo
d
a
b
c
H OAn Oen Oen
L
OAn Osn Oen
Oen Oen ODn H
Oen Oen ODn L
oAo Oso Oco oDo

H =HIGH LEVEL (STEADY STATE)
L =LOW LEVEL (STEADY STATE)
X =IRRELEVANT (ANY INPUT, INCLUDING TRANSITIONS)
t =TRANSITION FROM LOW TO HIGH LEVEL
a, b, c, d =THE LEVEL OF STEADY STATE INPUT AT
INPUTS DO, 1, 2, 3 RESPECTIVELY
OAo Oso Oco Ooo - LEVEL OF RO, Rl, R2, R3
RESPECTIVELY BEFORE THE INDICATED
STEADY STATE INPUT CONDITIONS WERE
ESTABLISHED
OAn, Oen, Oen, ODn, =THE LEVEL OF RO, R1, R2,
R3 RESPECTIVELY BEFORE THE MOST RECENT
TRANSITION OF THE CLOCK
i\/IK-0676

B-16

74S240 - OCTAL INVERTER AND LINE DRIVER WITH 3-STATE OUTPUT
These octal inverters and line drivers provide inverting outputs, and G (active-low output control)
inputs. G selects four inverting buffers.

r--------,

TYPICAL OF ALL
OUTPUTS

----.-Vee
R

OUTPUT
PORTS

FROM
DATA
BUS

OUTPUT

R = 2!:,; Il NOM
___.._.. OUTPUT PORT
CONTROL
EQUIVALENT OF
EACH INPUT

Vee---...--

INPUT
PORTS

1A1

TOP VIEW
2A3 1Y3

2Y4 ,1A2 2Y3 1A3

2A2

TO
DATA
BUS

·2A1

2Y2 1A4 2Y1

MK0674

B-17

74S241 - OCTAL BUFFER AND LINE DRIVER WITH 3-STATE OUTPUT
These octal buffers and line drivers provide noninverting outputs, and complementary G and G selects
for each of four buffers.

(TOP VIEW)

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

TYPICAL OF ALL
OUTPUTS

EQUIVALENT OF
EACH INPUT

- - ----------Vee

Vee-----------

R = 25IlNOM
MK-0686

B-18

74S25l - DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS
The 74S25l monolithic data selector/multiplexer contains full on-chip binary decoding to select one of
eight data sources, and features a strobe-controlled three-state output. The strobe must be at a low
logic level to.enable the device. The three-state outputs permit a number of outputs to be connected to
a common bus. When the strobe input is high, both outputs are in a high-impedence state in which
both the upper and lower transistors of each totem pole output are off, and the output neither drives
nor loads the bus significantly. When the strobe is low, the outputs are activated and operate as
standard TTL totem pole outputs.
LOGIC SYMBOL

BLOCK DIAGRAM
STROBE
(ENABLE)
DO

(7)

STROBE

....

7
(4)

D2
DATA
INPUTS

DI
D-

15
DATA
SOURCE

r--

(2)

3
4

Pi
D

..-+-

i---1

(15)

r,_.

(6)

DD-

I-I-I--

(12)

1--1

DATA
SELECT
(BINARY)

(10)

(9)

D5
D4

3-STATE
OUTPUT

74S251

D1
DO

OUTPUTW

BINARY
DECODE
INPUTS
FUNCTION TABLE

t--1

(13)

t-t,___

t--!

(14)

( 11)

OUTPUT Y

t--t---<

1
2

r--

( 1)

(3)

L../

r--

STB

,
~r
.....,
....,__l
"Y"
.....,

r ....

A
B
B

INPUTS
SELECT

OUTPUTS
STROBE

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

H
L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

DO
D1
D2
D3
D4
D5
D6
D7

iSl
D"2

04
D5

i5"J

c
c

H =HIGH LOGIC LEVEL, L =LOW LOGIC LEVEL
X =IRRELEVANT, Z =HIGH EMPEDANCE (OFF)
DO, D1, THRU D7= THE LEVEL OF THE RESPECTIVE D INPUT

MK-oe1a

8-19

74LS257 - QUAD 2-LINE-T0-1-LINE DATA SELECTOR/MULTIPLEXER
The 74LS257 multiplexer features three-state outputs that can interface directly with and drive data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance
state) the low impedance of the single enabled output will drive the bus line to a high or low logic level.

LOGIC SYMBOL

BLOCK DIAGRAM

2
BO

(3)

A1~}

6
DATA
LINES

5
10

11
81

(6)

AO
81
A1

15'

SELECT

(10)

OUTPUTS
F2

A 30UT
CONT

( 11)

74LS257

14
A2

1,so

9
12

OUTPUT SELECT
CONTROL

(14)

(13)

J.!.l
MK-0687

B-20

74S273 - OCTAL D-TYPE FLIP-FLOP WITH CLEAR
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop
logic with a direct clear input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going pulse. When the clock input is at either the
high or low level, the D input signal has no effect at the output.

BLOCK DIAGRAM
2D

10
(3)

(4)

CLEAR

(2)
10
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OUTPUT
CLEAR CLOCK D
0
L
L
H
H
t H
L
H
t L
L
Oo
H

x x
x

(5)
20

(13)

(7)

(8)

CLEAR

(6)
30

( 14)

CLEAR

(9)
40

( 17)

CLEAR

(12)
50

( 18)

CLEAR

(15)

CLEAR

(16)

(19)
80

H =HIGH LEVEL (STEADY STATE)
L =LOW LEVEL (STEADY STATE)
t =TRANSITION FROM LOW TO HIGH LEVEL
X =IRRELEVANT (ANY INPUT, INCLUDING TRANSITIONS)
0 0 =LEVEL OF 0 BEFORE THE INDICATED STEADY-STATE INPUT
CONDITIONS WERE ESTABLISHED
MK-0683

B-21

POSITIVE EDGE TRIGGERED FLIP-FOOP
ENABLE
07

74LS374 - OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

(1)

The eight flip-flops of the 74LS374 are edge-triggered, D-type flip-flops. On the positive transition of
the clock, the R outputs will be set to the logic states that were set up at the D inputs. A buffered
output control input can be used to place the eight outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The output control does not affect the internal operation of the flip-flops;
the old data can be retained, or new data can be entered, while the outputs are off.

(3)

- " " ' (2)
~

(4)
D

....... CK
Q

-"'-.. (5)

LOGIC SYMBOL
R6
74LS374

(7)
05

........ >CK
Q

~(6)

7
R5

8
INPUTS

(8)

........

~(9)

18
R4

CLK
03

(13)

111

- a

(14)

- a
(17)

( 18)

( 11)

OUTPUTS

15
16
19

OUTPUT
CONTROL

FUNCTION TABLE
~ (15)
:JI

.j'... (16) R1

....

CLOCK

>CK

- " " ' (12)

_......... (19)
~

OUTPUT
CONTROL CLOCK

OUTPUT

x
x

H =HIGH LEVEL
L= LOW LEVEL
t =TRANSITION FROM LOW TO HIGH LEVEL
X =IRRELEVANT (ANY INPUT INCLUDING TRANSITIONS)
Z =OFF (HIGH IMPEDANCE) STATE OF A THREE-STATE OUTPUT
0 0 =LEVEL OF R BEFORE THE INDICATED STEADY-STATE INPUT
CONDITIONS WERE ESTABLISHED
MK-0682

B-22

8136 - 6-BIT UNIFIED BUS COMPARATOR
The 8136 compares two binary words of 2- to 6-bits in length, and indicates matching (bit for bit) of
the two words. The 8136 has open-collector outputs which go to the high state upon equality, and it is
expandable to n bits by collector-ORing. The device has an output latch which is strobe controlled.
The transfer of information to the output occurs when the STROBE input goes from a logic "I" to a
logic "O" state. Inputs may be changed while the STROBE is at the logic "l" level, without affecting
the state of the output.

LOGIC SYMBOL

BLOCK DIAGRAM

8136
1
2
3
4
5
6

TWO-WORD
INPUT

10
13
12
15
14

~~-'-(g~)~~-OUTPUT

Bl
Dl
B2
D2
B3
D3

OUT

OUTPUT

D4
B5
D5
86
D6
STB

1
TRUTH TABLE

R = HIGH IMPEDENCE
BUS RECEIVER
(7)

CONDITION

STROBE

OUTPUT

D = B, D f. B
D=B
D JI! B

H
L
L

ON 1*
H
L

STROBE
*LATCHED IN PREVIOUS STATE
MK-0667

B-23

82SI 12 - HIGH SPEED 8 x 4 MULTIPORT RAM
The 82S 112 is a Schottky TTL 32-bit multiport memory organized in eight words of 4-bits each. The
device is ideally suited for high speed accumulators and buffer memories.
Stored data is addressed through two independent sets of three input decoders, and read out when the
corresponding output enable line is low. Two separate word locations can, therefore, be read at the
same time by enabling both the A and B output drivers. In addition, data can be read and written at
the same time by utilizing the "A" address to specify the Iaction of the word to be written, and the "B"
address to specify the word to be read.

LOGIC SYMBOL
82S112

A1
3

OATA {
INPUT
LINES

2
22
21

10 }A OUTPUTS
11
13

14}
15

B2
'::'

B OUTPUTS

B3
AA2 AA 1 AAO BA2 BA 1 BAO
4
6
5
18 19
20

/
A DECODER
..,
B DECODER
ADDRESS LINES ___J
L__ADDRESS LINES
(READ/WRITE)
TRUTH TABLE
(READ ONLY)

- -

A
B
R/W R/W OUTPUT OUTPUT
ENABLE ENABLE
0

0
0

x
x
x

1
1
1
1
1
1

1
1
1
1
0
0

0
1
0
1
0
1
0

0
0
1
1
0
0
1
1

1
0

MODE
Outputs
Disabled
Read
Read
Read
Read
Read
Read
Read
Write
Write

OUTPUTS
A

"1"

''1 ''

"1"

Data

Data
Data

Data

111 ''

"1"

''1"
Data
Data
''1"

Data

"1"

"1 ''
Data

"1"
Data

"B"
Address
1

Write

'Write

Data
Being
Written
Data
Being
Written

"1 ''

Data

"B"
Address
MK-0673

B-24

82S191 - 16,384-BIT 2K X 8 BIPOLAR PROM
The 82S191 is field programmable, supplied with all outputs at logical low. Outputs are programmed
to a logic high level at any specified address by fusing a Ni-Cr link matrix. This device includes on-chip
decoding and three chip enable inputs.
BLOCK DIAGRAM

Ao ...,
ADORESs
LINE s
A10 c,

1.128DECODER

i--r--1

126X126
MATRIX

W--

J--------3
c,

....,

1: 16
MUX

()

1: 16
MUX

\.,r

CE 1c,
A12/ CE 2 ...,
A 11/ CE3 c,

03
04
05
OUTPUT LINES

)

LOGIC SYMBOL
8
76
5
4
ADDRESS
LINES

3
2
1
23
22
21
18

ENABLE{
LINES

19
20_,..i
~

82S191
AO
A1
A2
A3

A10

9
10
11
13
14

OUTPUT
LINES

15
16
17

CE/A11
CE/A12
CE
MK-0677

B-25

93S16 -4-BIT BINARY COUNTER
The 93S16 is a fully synchronous 4-bit binary counter. With the parallel enable (LD) low, data on the
inputs is parallel loaded on the positive clock transition. When LD is high and both count enables are
also high, counting will occur on the low-to-high clock transition.
The terminal count state 111 l is decoded and ANDed with CRY EN in the terminal count (CO)
output. If CRY EN is high and the counter is in its terminal count state, then CO is high.
The counter has an asynchronous master reset (CLR). A low on the CLR input forces the outputs low
independent of all other inputs. The only requirements on the LD, CNT EN, CRY EN, and DO - 03
inputs is that they meet the setup time requirements before the clock low-to-high transition.

LOGIC SYMBOL
PARALLEL
DATA
INPUTS
PARALLEL
ENABLE
1
MASTER RESET_j7 2

00 93S16RO 14
13
01
R1
}
12
D2
R2
11
R3

CLK

CLR

L
H
H
H
H
H

+
+
+
+
+

L
H
H
H
H

TERMINAL
COUNT

co 15

COUNT
ENABLE

ENT

FUNCTION TABLE
INPUTS
EN
D1
02
DO

..1Q_

PARALLEL
OUTPUTS

L
L
D2
01
NC
NC
NC
NC
NC
NC
COUNT

x
x

L
L
H
H

L
H
L
H

x
x
x
x

x
x

Do
NC
NC
NC

x
x
x

= HIGH
= LOW
x = DON'T CARE
NC = NO CHANGE
DJ = MAY BE EITHER HIGH OR LOW
+ = LOW-TO-HIGH TRANSITION
H
L

B-26

OUTPUTS
R2
R3

L
D3
NC
NC
NC

BLOCK DIAGRAM
CLRO 1

CLKO 2

R2Q
12

R1Q

ROQ

CP MR

a--

CP MR

a---.

01---1

R3Q

Cit-

Qt-

CP MR
O.t----i

r--d5

ch--

..----

------.

~~) l~l
0
A
(
LJ_
llL
DO

OJ"

--t-+---+--1

LDC 9 ~~._.J--............ ~
CNTENl"" 7

~
'-J-......----..........1.-~-------·..___-+----------'-----I~----------'
.___ _ _ _ _ _ _ _ _ _ _
.......
co
.--::::::J-------~
--r15

'----------------------------------------------------~r--

'
IC-93516

B-27

DCOIJ - DEC UNIBUS CHIP
The DEC DCOIJ UNIBUS chip is an LSI integrated circuit designed specifically for the UNIBUS and
is useful in performing interrupt and NPR control. Its main function permits a device to make bus
requests and to gain control of the UNIBUS (become bus master).
BUS NPR L

---o a---'""'

STEAL
GRANT L

STEAL
GRANT

1-----1

c NPR

LOGIC SYMBOL

STEAL
GRANT

BUSY

SSYN

BSACK

REO
OUT

MASTER
INTR
DONE
1

SACK

BG OUT

REOIN
BGIN

10
REQUEST L

1--t--r----tO

a--~

TAKE
GRANT

. > - - - - - - t 12 SACK H

11
12

'-------ao

a......,i--------J

MASTER l

SACK

SACK
CLR CLR EN
13

BUS BG/NPG
OUT H

DC013

BUS/BG/NPG
IN H

BUS BBSY l

Ot--t--P.--+----'
CLR

MK·0659

CLR SACK
ENB L

vcc

MASTER
14
CLR H

Q
BBSY

IN IT H 13 1--------..--:__

_.PIN 8
PIN 16

GNO
VCC
MK-0665

B-28

OPERATION - Refer to the logic diagram on page B-28.
REQUEST (pin l) is asserted to initiate a BR or NPR. The request latch ensures only one priority
transfer sequence is initiated for each assertion of REQUEST. Once the latch is set, REQUEST must
be negated and asserted again before another cycle may begin, provided MASTER CLR (pin 14) is not
grounded.
If the device is not asserting BUS BBSY (pin 10), the device is not already bus master, the D input
to the TAKE GRANT flip-flop is asserted and one input to the BUS REQUEST driver is enabled.

BUS REQUEST (pin 9) is asserted while SACK flip-flop is in the reset state and at the same time as
REQUEST is asserted by the device.
BUS BBSY (pin 10) is input to the grant circuitry; any grant received while this device is asserting BUS
BBSY is passed.
TAKE GRANT AND STEAL GRANT flip-flops are clocked by the assertion of BUS GRANT IN
{pin 5).
If the device is asserting BUS REQUEST, the next assertion of BUS GRANT IN causes the

TAKE GRANT flip-flop to become set.
or
If STEAL GRANT (pin 3) is asserted and some device is asserting BUS NPR (pin 4) while the
BBSY flip-flop is reset, the STEAL GRANT flip-flop is set
Either flip-flop (TAKE GRANT or STEAL GRANT) set disables an input to the BUS GRANT
OUT driver, preventing the grant from being passed and enabling the D input to the SACK flipflop.
If the TAKE GRANT and SACK flip-flops are set, one input to the clock of the BBSY flip-flop is
enabled.
If the device is not requesting the BUS, the REQUEST from the previous grant has not been
negated and reasserted.
or
If the device is already asserting BUS BSSY, the TAKE GRANT flip-flop is cleared by the next
assertion of BUS GRANT IN.
If the STEAL GRANT flip-flop is also cleared by the assertion of BUS GRANT IN, the grant is
passed as an assertion of BUS GRANT OUT (pin 6).

The delay (Dl) at the input to the BUS GRANT OUT driver ensures that the TAKE GRANT
and STEAL GRANT flip-flops have had time to settle before any grants are passed to the next
device of the system.
Assertion of BUS GRANT IN is also used to clock the SACK flip-flop. Delay (02) at the input
of the SACK flip-flop ensures that the TAKE GRANT and STEAL GRANT flip-flops have had
time to respond to the assertion of BUS GRANT IN before the SACK flip-flop is clocked.
If either flip-flop (TAKE GRANT or STEAL GRANT) are set when the SACK flip-flop is
clocked, the SACK flip-flop will set. When this occurs, BUS SACK (pin 7) is asserted, allowing
the arbitrator to negate the grant after a minimum of 75 ns delay, and BUS REQUEST is negated.

B-29

I/the TAKE GRANT flip-flop is set when the SACK flip-flop is set, one input to the clock input
of the BBSY flip-flop is enabled. The SACK (pin 12) output is also asserted; it is available to the
device as an inversion of BUS SACK.
SACK flip-flop may be reset by asserting CLR SACK ENB (pin 15) at the same time that BUS BBSY
is asserted and BUS GRANT IN is negated. Delay (D3) at the output of the CLR SACK ENB gate
ensures that the BUS INTR (external signal) driven by the MASTER signal (pin 11) is asserted before
SACK flip-flop is cleared.
The SACK flip-flop may be cleared by the negation of BUS GRANT IN while the TAKE GRANT
flip-flop is reset. The SACK flip-flop remains set while CLR SACK ENB is negated, keeping the
arbitrator disabled.
BBSY flip-flop will set when the following clock input conditions are satisfied:
•

TAKE GRANT and SACK flip-flops are set

•

BUS GRANT IN, BUS SSYN (pin 2) and BUS BSSY are negated (not necessarily in that
order)

BUS BSSY is asserted when the BBSY flip-flop is set. The BBSY driver input enables the MASTER
output to:
•
•

Disable the D inputs to the TAKE GRANT and STEAL GRANT flip-flops
Allow the SACK flip-flop to be cleared

MASTER may be used by the master device to initiate a data transfer or an interrupt sequence. The
MASTER signal is asserted when BUS BSSY has been asserted and is negated before the negation of
BUS BSSY. Once BUS BSSY has been asserted, the device has gained control of the UNIBUS and the
data transfer or interrupt sequence may proceed.
The MASTER signal is available to drive external gating, e.g., it may be used to enable the appropriate
data lines and BUS INTR in an interrupt sequence.
When the requesting device has completed its transfer, it asserts MASTER CLR. When both BUS
SSYN and MASTER CLR are asserted (signifying that the transfer is completed), the BBSY flip-flop
is reset and the latch on the REQUEST signal is returned to the state which disabled the REQUEST
input to the DC013. The MASTER signal is negated as soon as the BBSY flip-flop is reset.
The delay (D4) at the Q output of the BBSY flip-flop ensures that the negation of BUS BSSY is
delayed for negation of the MASTER signal which is used to drive BUS INTR. Delay (D4) is guaranteed to a minimum of 80 ns.

B-30

APPENDIX C
M8207 MICROPROCESSOR
JUMPER CONFIGURATION
The M8207 microprocessor jumper configurations for both the DMPll and DMRll options are
provided in this appendix. The M8207 module comes in two versions:
•
•

M8207-YA for DMPll options, and
M8207-RA for DMRl 1 options.

Jumper locations are shown in Figure C-1 and functions are discussed in Table C-1.

11111111111
E127

Ow2
[2=1 :~~~RITY

DITO
E85

l 111111111 I

Owa

E28

w10D Ow9
MK-3922

Figure C-1

M8207 Microprocessor Jumper Locations

Table C-1 M8207 Jumper Chart
Jumper
Number

Normal
Configuration

VVl

Always IN

Microprocessor Clock Enable - VVhen removed it
disables the microprocessor clock. Removed only
for automatic module testing at factory.

VV2

Always IN

Bus ac Low Enable - VVhen removed it disables a
program-asserted ac low signal passed onto the
UNIBUS.

VV4, VV6,
VV7, VV9

IN for this option only

For DMPl 1 option (M8207-YA).

VV3, VV5,
VV8, VVlO

IN for this option only

For DMRl 1 option (M8207-RA).

Function

C-1

GLOSSARY

A Port
Read/write input to the Multiport Random
Access Memory.

Control ROM (CROM)
Plug-in Control Read Only Memory, used
as the instruction memory for the microprocessor.

Arithmetic Logic Unit (ALU)
Allows the microprocessor to perform
arithmetic and logic operations.

CPU
Central Processing Unit.
CSR

BERG Port
An 8-bit port that allows the microprocessor to communicate with other devices without using the UNIBUS.
Bit-Stuff Protocol
Zero insertion by the transmitter after any
succession of five continuous ones designed
for bit oriented protocols such as IBM's
Synchronous Data Link Control (SDLC).
B Port
Read address input of the Multiport Random Access Memory (Read Only Port).
Branch Register (BRG)
Temporary data storage register used for
branch determination and shifting right.
Buffered Arithmetic Logic Unit (BALU)
Operations performed by the ALU are buffered by the BALU and directed to data
memory, respective registers, and the
BERG Port.
Comite Consultatif Internationale de Telegraphie
et Telephone (CCITT)
An international consultative committee
that sets international communications usage standards.

Control and Status Registers.
Data Multiplexer (DMUX)
An 8-bit wide, 8-to-I multiplexer used to select data for the B input of the ALU.
DATI
Data In Transactions (Read).
DATO
Data Out Transactions (Write Word).
DATOB
Data Out Byte Transactions (Write Byte).
Destination ROM (DROM)
Controls the operand as defined by the destination of the instruction in the instruction
register.
Digital Data Communications Protocol
(DDCMP)
DIGIT A L's standard communications
protocol for character oriented protocol.
Direct Memory Access (OMA)
Permits input/output transfers directly into
or out of memory without passing through
the processor's general registers.
Electronic Industries Association (EIA)
Sets electronic industry standards for interfacing signals between units in the U.S.

GLOSSARY-I

Field Replaceable Unit (FRU)
Refers to a faulty unit not to be repaired in
the field. Unit is replaced with a good unit,
and faulty unit is returned to predetermined
location for repair.
f<'ull Duplex
Simultaneous two-way independent transmission in both directions.
Function ROM (FROM)
Controls up to 16 functions performed by
the ALU.
Half Duplex
An alternate, one way at a time independent transmission.
·
IBUS/OBUS
Microprocessor NPR data, NPR address
registers, and BERG Port registers.

Multiport RAM (MP RAM)
Contains all M8207 control and status registers between the microprocessor and the
CPU processor.
Non-Processor Request (NPR)
Direct memory access type transfers. See
OMA.
Program Counter (PC)
A 14-bit counter used to control the address
of the Control ROM directly.
Program Counter Register (PCR)
· Contains upper six bits to be loaded into
the PC on a branch condition, and provides
extra field addressing with future expansion
capability.
RAM
Random Access Memory.
ROM
Read Only Memory.

IBUS* /OBUS*
Microprocessor NPR control and miscellaneous registers, and CSRs.

R232C
EIA Standard single-ended interface levels
to modem.

Instruction Register (IR)
Contains the instruction that is being executed. Outputs are used to control the microprocessor.

RS 422
EIAStandard differential interface levels to
modem.

Line Unit Input Data Bus (LU IBUS)
Provides a path to the DMUX via the
BERG Connector.
Main Memory (MEM)
Data storage area for the microprocessor
4K X 8 RAM; cannot be accessed directly
by the CPU.
Maintenance Instruction Register (MIR)
Provides a destination for an instruction
that can be loaded by the CPU during
maintenance.
Memory Address Register (MAR)
Controls the data memory for buffered
arithmetic and logic operations to main
memory.

RS 423
EIA Standard single-ended interface
modem.
RS 449
EIA Standard connections for RS 422 and
RS 423 to modem interface.
Scratchpad Memory (SP)
Read/write memory used for temporary
storage of data.
Source ROM (SROM)
Defines the type of instruction to be executed and the source of the data used for
the instruction.
System Clock
Basic timing generated by a 33.33MHz
crystal providing microprocessor timing
functions.

GLOSSARY-2

V .35 - CC ITT Standard

Differential current mode type signal interface for high speed modems.

"Y" Version
Defines microcode stored in the Control
RO Ms.

GLOSSARY-3

INDEX
A
AC LO, 1-2,2-19,2-20
A Port Address, 1-4,2-12
Arithmetic Logic Unit,1-2,1-4,2-9,2-12,2-14

B
BALU Description, 2-12
B Port, 1-4,2-2,2-11,2-12
BERG Port, 1-1,2-20,2-21
Bit Functions
CSR0,2-23
Miscellaneous Register 11, 1-5,2-19
N PR Control Register I0, 1-5,2-16
Branch
Conditions, 2-6,2-9
Control, 1-5,2-21,2-22
Register, 1-2,2-23,2-24
Bus Timing,2-21

Incrementing MAR, Data MEM, 2-14
Inhibit Clock, 2-23
Instruction Register, 1-3, 1-4,2-8
Instruction Set, 1-1
Interface Diagnostics, A-14
Interrupt, 1-5,2-20

Line Unit, 3-2
Loading MAR, 2-14

M
Maintenance
Corrective, 3-1
Instruction Register, 1-4,3-1
Philosophy, 3-1
Preventive, 3-1
Main Timing Chain, 2-6,2-2
Major Functional Areas, 1-2
M icrodiagnostics
Interface, A-14
Internal, A-2
Microprocessor Features, 1-2
Microprogram, 1-1
Miscellaneous Registers, 1-5,2-19
MSYNC Flip-flop, 2-1
Multiport RAM, 1-3,1-4,2-12

c
C Bit (ALU),1-4,2-11
C Flip-flop,2-11,2-12
Chip Address Range, 3-3
Control Register,2-23
Control ROM,1-4,2-2,2-8,3-1
Corrective Maintenance, 3-1
Crystal (33.33 M Hz), 2-1,2-2
CSRO Address, 2-3,2-4,2-23
CSR6 Address, 2-2,2-4,2-23,2-26
CSR Map,2-3,2-4
D
Data Memory,1-1,2-14,2-15
Data Multiplexer, 1-3,1-4,2-2,2-9,2-IO
Data Transfer from NPR, 2-12
Destination ROM,1-5,2-2
Diagnostics, 3-1
Interface, A-14
Internal, A•2
DMA Device, 1-5

N
N PR Registers, 1-5,2-16
Address Bits, 2-16,2-17
Control, 2-23,2-26

F
FRU, 3-1
Functional Location of Microprocessor, 1-2
Function ROM, 1-4,2-2,2-9

p
Parallel Loading, 2-24
Port Cable, 3-2
Preventive Maintenance, 3-1
Program Counter, 1-6,1-8,2-8,2-14
Programming, 1-1
-

INDEX-I

R
RAM, 1-4,2-12
Read Transactions, 2-20
Register IO Bits Definitions, 2-16,2-17
Register 11 Bits Definitions, 2-19,2-20
ROM Replacement, 3-3
Run Inhibit Switch, 2-23
RUN SYNC Flip-flop, 2-6

s
Scratchpad, l-l,l-4,1-6,2-11
Shift Right, 2-24
Source ROM, 1-4,2-9
Status Register, 2-23
System Clock, 1-3,2-1
T

Timing, 2-1,2-7

v
Vector
Address, 1-5
Interrupt, 2-20

w
WAIT SYNC Flip-flop, 2-1
Write Transactions, 2-20

z
Z (Bit) Flip-flop,2-11,2-12

INDEX-2

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M8207 Microprocessor
Technical Manual
EK-M8207-TM-002
(MK)

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