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Document:	M8203 Line Unit Technical Manual 198103
Order Number:	EK-M8203-TM
Revision:	002
Pages:	130
Original Filename:	EK-M8203-TM-002_M8203_Line_Unit_Technical_Manual_198103.pdf

OCR Text

EK-M8203-TM-002

M8203 Line Unit
Technical Manual

EK-M8203-TM-002

M8203 Line Unit
Technical Manual

digital equipment corporation • merrimack, new hampshire

1st Edition, August 1979
2nd Edition (Rev), March 1981

Copyright © 1979, 1981 by Digital Equipment Corporation
The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS

D ECsystem-lO
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS

CONTENTS
Page
PREFACE
CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.4

PURPOSE .......................................................................................................... .1-1
DESCRIPTION ................................................................................................. .1-1
MAJOR FUNCTIONAL AREAS ..................................................................... .1-3
M8203 LINE UNIT/MICROPROCESSOR INTERFACE ............................... .1-6

CHAPTER 2

INTERFACE

2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.5
2.6
2.7

SCOPE ............................................................................................................... 2-1
FULL-DUPLEX/HALF-DUPLEX OPERATION ........................................... 2-1
STANDARD APPLICA TIONS ......................................................................... 2-3
COMPATIBLE STANDARDS .............................................................................. 2-4
RS-232-C/CCITT V.28 (ISO 2110) Modem Interface .................................. 2-5
EIA Standard RS-423-A .................................................................................. 2-6
EIA Standard RS-422-A .................................................................................. 2-6
EIA Standard RS-449 ................................................................................... ,.. 2-7
CCITT V.35/ISO 2593 .................................................................................... 2-9
INTERFACE SIGNALS ......................................................................................... 2-9
ADDITIONAL LINE UNIT OPTIONS ................................................................ 2-9
HARDWARE VARIABLES ................................................................................... 2-9

CHAPTER 3

TECHNICAL DESCRIPTION

3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.3.1
3.3.2
3.4
3.5
3.6
3.7
3.8
3.8.1
3.8.2

SCOPE ............................................................................................................... 3-1
BERG PORT INTERFACE ............................................................................... 3-1
Read IBUS Registers ................................................................................... 3-4
OBUS Registers ....................................................... ,.................................. 3-5
IBUS/OBUS Registers Bit Descriptions ..................................................... 3-6
Extended Registers/Indirect Addressing .................................................... 3-19
SILOS ............................................................................................................... 3-27
Transmit Silo ............................................................................................ 3-27
Receive Silo ............................................................................................... 3-29
SEQUENCER .................................................................................................. 3-29
DATA RATE GENERATOR .......................................................................... 3-32
USYRT ............................................................................................................ 3-32
MODEM INTERFACE ................................................................................... 3-32
INTEGRAL MODEM SPECIFICATIONS ..................................................... 3-39
Receiver .....................................................................................................3-40
Transmitter ............................................................................................... 3-44

CHAPTER 4

SERVICE

4.1
4.2
4.2.1
4.2.2

SCOPE ............................................................................................................... 4-1
MAINTENANCE PHILOSOPHY ................................................................... .4-1
Preventive Maintenance .............................................................................. 4-1
Corrective Maintenance .............................................................................. 4-3

iii

CONTENTS (CONT)
APPENDIX A

MICRODIAGNOSTIC TESTS

A.1
A.2
A.3
A.4

INTRODUCTION .............................................................................................. A-l
HARDWARE REQUIREMENTS .................................................................... A-l
INTERNAL MICRODIAGNOSTICS ............................................................... A-l
LINE UNIT TESTS ........................................................................................... A-l

APPENDIX B

RECOMMENDED CABLES/CONNECTORS

B.1
B.2
B.3
B.3.1
B.3.1.1
B.3.1.2
B.3.2
B.3.3
B.3.4
B.4
B.6

SCOPE ............................................................................................................... B-l
CABLING RECOMMENDATIONS ................................................................ B-l
CABLE SPECIFICATIONS .............................................................................. B-1
Cable Resistance Versus Distance ................................................................ B-4
Twinax Cables ..................................................................................... B-4
Triax Cables ........................................................................................ B-4 '
75 Ohm Systems .......................................................................................... B-4
150 0 hm Systems ........................................................................................ B-5
Cable Attenuation ....................................................................................... B-6
INSTALLATION CONSIDERATIONS ........................................................... B-6
RECOMMENDED CONNECTORS ................................................................ B-7
GROUNDING RECOMMENDATIONS ......................................................... B-9

APPENDIX C

INTEGRATED CIRCUIT DESCRIPTIONS

C.1
C.2

INTRODUCTION ............................................................................................. C-l
SELECTED INTEGRATED CIRCUITS .......................................................... C-2

B.5

GLOSSARY
INDEX

Page

FIGURES

Figure No.
1-1
1-2
1-3
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37

Title

Page

Major Functional Areas ...................................................................................... 1-4
Typical PDP-II Applications ................................................................................... 1-6
Typical VAX-II /780 Applications .......................................................................... 1-7
Full-Duplex/Half-Duplex Connections ............................................................... 2-2
Standard (Common) Interfaces ........................................................................... 2-3
Special Application ............................................................................................. 2-4
CCITT V.35 (ISO 2593) Interface ........................................................................... 2-5
Input/Output Registers ....................................................................................... 3-2
IBUS Register Select ........................................................................................... 3-5
OBUS Register Select. ......................................................................................... 3-5
IBUS Register 10 ................................................................................................ 3-6
OBUS Register 10 ............................................................................................... 3-7
IBUS Register 11 ................................................................................................ 3-8
OBUS Register 11 ............................................................................................... 3-9
IBUS Register 12 ............................................................................................... 3-10
OBUS Register 12 ............................................................................................. 3-11
IBUS Register 13 .............................................................................................. 3-12
OBUS Register 13 ............................................................................................. 3-13
IBUS Register 14 .............................................................................................. 3-14
OBUS Register 14 ............................................................................................. 3-15
IBUS Register 15 .............................................................................................. 3-15
OBUS Register 15 ............................................................................................. 3-16
IBUS Register 16 .............................................................................................. 3-16
OBUS Register 16 ............................................................................................. 3-17
IB US Register 17 .............................................................................................. 3-17
OBUS Register 17 ............................................................................................. 3-18
AXO-15 Register ............................................................................................... 3-20
AXO-16 Register ............................................................................................... 3-21
AX 1-15 Register ............................................................................................... 3-22
AX 1-16 Register ............................................................................................... 3-23
AX2-15 Register ............................................................................................... 3-24
AX2-16 Register ............................................................................................... 3-24
AX3-15 Register ............................................................................................... 3-25
AX3-16 Register ............................................................................................... 3-27
Transmit Silo .................................................................................................... 3-28
Receive Silo ...................................................................................................... 3-30
Load Silo .......................................................................................................... 3-31
Data Rate Generator ........................................................................................ 3-33
Typical Start Sequence for the USYR T Bit Oriented
Protocol Transmission Flowchart ..................................................................... 3-34
Typical Start Sequence for the USYRT Character Oriented
Protocol Transmission Flowchart ..................................................................... 3-35
Typical Receive Sequence for the USYRT Bit Oriented
Protocol Flowchart ........................................................................................... 3-36
Typical Receive Sequence for the USYR T Character
Oriented Protocol Flowchart ............................................................................. 3-37
Data Rate Select...................... .................... ................................... . ............... 3-38
Modem Receiver Block Diagram ...................................................................... 3-40

FIGURES (CONT)
Figure No.
3-38
3-39
3-40
3-41
3-42
4-1
4-2
4-3
B-1
C-l
C-2
C-3
C-4
C-5

Title

Page

Modem Receiver Timing Diagram - Start-Up .................................................... 3-41
Modem Receiver Timing Diagram - Normal Data ............................................. 3-42
Modem Transmitter Block Diagram .................................................................. 3-45
Modem Transmitter Timing Diagram - Start-Up ............................................... 3-46
Modem Transmitter Timing Diagram - Normal Data ........................................ 3-47
Received Signal Measurement. ............................................................................. 4-2
Open and Short Circuit Resistance ...................................................................... .4-2
Signal Reflections from a Line Fault ................................................................... .4-3
Local Link Cable Connectors .............................................................................. B-8
Terminal Connection (Identification)
Diagram (2112517-01 Variation) ......................................................................... C-8
Suggested Block Diagram ................................................................................. C-l 0
Receive Signal Timing Waveforms .................................................................... C-12
Transmit Signal Timing Waveforms .................................................................. C-13
Tri-State Output Waveforms ............................................................................. C-14

TABLES
Table No.
1-1
2-1
2-2
B-1
B-2
C-l

Title

Page

M8203 Line Unit Interfaces ................................................................................. 1-2
Interface Signals/Pins at the Modem .................................................................. 2-11
Equivalency Table ............................................................................................. 2-14
Belden Twinax Cable Specifications .................................................................... B-2
Belden Triax Cable Specifications ....................................................................... B-3
2652 Internal Register Bit Map (2112517-01 Variation) ....................................... C-9

PREFACE

The M8203 Technical Manual is a stand-alone document that describes typical line unit applications,
circuit functions, and maintenance procedures based on a module replacement philosophy. Recommended cables and connectors, and installation considerations are provided in Appendix B. Detailed
installation is provided in relevant systems documentation in which the line unit is implemented (such
as the DMPll-AD Technical Manual - EK-DMPII-TM-OOI or DMRll Technical Manual - EKDMRll-TM-002).
A Glossary of terms and abbreviations, selected integrated circuit descriptions, and microdiagnostic
tests l:lre also provided.
The following documents contain necessary reference information:

•

M8207 Technical Manual (EK-M8207-TM-OOl)

•

M8207 Print Set (D-CS-M8207-XX)

•

M8203 Print Set (D-CS-M8203-XX)

•

DMPll-AD Technical Manual (EK-DMPII-TM-OOI)

•

DMRll Technical Manual (EK-DMRII-TM-002)

•

Electronic Industries Association (EIA) Specifications

vii

CHAPTER 1
INTRODUCTION

1.1

PURPOSE

The M8203 is a high performance line unit designed for multipoint or point-to-point systems. The line
unit is capable of cyclic redundancy check (CRC) or parity checking for both character and bit oriented protocols. Receive and Transmit Silos buffer the data to allow UNIBUS delays during transmission. However, for special bit and character oriented protocols, the line unit can be run without using
the silos. Character oriented protocols use three types of error checking; CRC 16, even and odd, and
vertical parity. The bit oriented protocols use two types of Comite Consultatif Internationale de Telegraphie et Telephone (CCITT) CRC 16 error checking; initialized to 0 and 1. Both protocols can be
run without error checking for transparent or special operations.

1.2

DESCRIPTION

The M8203:
•

is a full multilayer hex module containing three 40-pin berg connectors.

•

has no cables permanently attached.

•

contains three switch packs that must be set up when the module is installed.

•

power consumption is +5V at 3 AMPS, + 15V at 180 milliamps, and -15V at 150 milliamps.

•

fits into any hex Small Peripheral Controller (SPC) slot or in a powered backplane (microprocessors are restricted to non-processor request (NPR) SPC slots DDII-C or D).

•

is not a stand alone device; the line unit must be controlled by a microprocessor.

•

provides no ac or dc loading to any UNIBUS signals.

All data going to the line must go through the Universal Synchronous Receiver/Transmitter
(USYRT). Transmit and Receive Silos are used to interface between the USYRT and the microprocessor.
M8203 Features:
•

Addressing - Addressed through the microprocessor IBUS and OBUS eight bit byte registers 10-17.

•

Indirect Addressing - Used to address the USYRT; bypasses the silos and standard hardware to run special protocols and variable character length operations.

•

Berg Port - The main interface to the microprocessor for all data and control of the line
unit.

1-1

•

Integral Modem - Runs at 56K bps, 250K bps, 500K bps, and 1M bps. (Integral Modem
specifications are provided in Chapter 3, Technical Description.)

•

Interfaces are listed in Table 1-1.
Table 1-1 M8203 Line Unit Interfaces

INTERFACE

SPEED

MODEM

CABLE

EIA RS-232-C*
CCIrr V.28/ISO 2110*

Up to 19.2K bps

Bell 208,
209

Panel Cable
BC55C-tO
Modem Cable
BC05D-25

EIA RS-423-A

Up to 56K bpst

Panel Cable
BC55C-tO
Modem Cable
BC55D-33

Up to 1M bps

Panel Cable
BC55B-I0
Modem Cable
BC55D-33

Compatible with
Federal t030;
CCITT V.I0/ISO
4902 and X.26
EIA RS-422-A
Compatible with
Federal 1020;
CCITT V.II/ISO
4902 and X.27
CCIrr V.35/ISO 2953

Up to 250K bps

Be1l500A

BC05Z-25

INTEGRAL MODEM
using Twinax/Triax

56, 250, 500K bps
1M bps

Integral

BC55A-IO

*Drivers are protected to ± 10 Volts not ± 15 Volts
tLimited to 20K bps by RS-449 and 9600 bps by ISO 4902

1-2

1.3 MAJOR FUNCTIONAL AREAS
A simplified block diagram of the M8203 is provided in Figure 1-1. A brief description of the subject
areas is as follows:
•

INBUS Registers 10-17 Functions (as seen by the microprocessor):
Read data and status in the Receive Silo and Shift Silo
Microcode uses switches for line status (switches set up at installation time)
Receiver status
Status and control of the Modem Interface
Extended address bits
Maintenance functions
Full or half-duplex on all interfaces

•

OUTBUS Registers 10-17 Functions (loaded by the microprocessor):
Load data and status into Transmit Silo and Shift Silo
Control transmit circuitry
Enable maintenance mode
Status and control of Modem Interface
Extended address bits
Load data into data registers (only in extended mode)
Maintenance functions

•

Switch Packs:
Defined by microcode (see specific options manual)

•

Receive Silo:
First in first out (FIFO) 64 X 12
Loaded from the USYRT via a crystal controlled sequencer.

•

Transmit Silo:
FIFO 64 X 12
Loaded from the microprocessor

1-3

*
INBUS
REGS

SWITCH
PACKS

-- ,..

5 LINES

I
16 LINES

f01. 02

REC
SILO

USYRT 2652
(VERSION 01)

I-

*
I-'
I

08&09

5 LINES

05
"-12 LINES

OUTBUS
REGS

RS-449
RS-232C

f-.

XMIT
SILO

SEQUENCER
CRYSTAL
CONTROLLED
&

12 LINES

DATA RATE
GENERATOR

5 CONTROL LINES

V.35

f-.

08 & 09

< 16 BIT BUS>

06,07

I
03,01

INTEGRAL
MODEM

.-..

16 LINES
05
CLOCK

* SEE CHAPTER 3 FOR DETAILED DESCRIPTIONS

D10&011

TRISTATE CONNECTION

OF INBUS AND OUT REGISTERS.

MK·0944

Figure 1-1

Major Functional Areas

•

Sequencer:
Controls all data in and out of the USYRT and all clear functions on the module
Timing is controlled by a crystal (20 MHz for 100 ns increments)

•

USYRT:
All received data to the line unit must go through the USYRT
Handles the basic protocol and error detection
Character Oriented Protocol:
1.
2.
3.
4.
5.

Parallel to serial conversion
Synchronous (Sync) character recognition and generation
Sync character stripping
CRC checking if enabled
Vertical parity if enabled

Bit Oriented Protocol:
1.
2.
3.
4.
5.
6.
•

Parallel to serial conversion
Zero stuffing (insertion) and stripping
CRC checking if enabled
Flag recognition and generation
Abort recognition and generation
Go-Ahead recognition and generation

Modem Interface
A summary of the Modem Interfaces is provided in this section. Detailed descriptions are
contained in Chapter 2, Interface.
RS-449/lnternational Standards Organization (ISO) 4902/CCITT V.24: Common interface defined by all Electronic Industries Association (EIA) interfacing cables used
with RS-422-A and RS-423-A.
RS-232-C: EIA defined signals and characteristics for older modems (drivers are not
protected from shorts to signals over 10 volts).
RS-422-A (Federal Standard 1020) (ISO 4902/CCITT V.ll and X.27): Differential
balanced interface used in conjunction with RS-449.
RS-423-A (Federal Standard 1030) (ISO 4902/CCITT V.lO and X.26): Single-ended
(unbalanced) signal levels used with RS-449 cables.
V.35: CCITT Standard/ISO 2593 Standard

1-5

Integral Modem:

Diphase-space modulation compatible with the DMCll Integral Modem and the encoding/decoding of the DIGITAL
DCOl7 IC chip.
Transmitter output = 5.6 volts peak-to-peak minimum into a
30-ohm load.
Receiver signal = 150mV peak-to-peak minimum @ 20% maximum distortion.
Transformer coupled 500 volt common mode.

NOTE
Modules do not include any modem or Modem Interface cables.
1.4 M8203 LINE UNIT/MICROPROCESSOR INTERFACE
The M8203 Line Unit connects to the network via (I), the twinax or triaxial cables in local network
applications or (2), the modems and common carrier facilities in remote network applications. The
M8203 runs up to 1M bps on both Modem Interface and Integral Modems.

BC55B-10
BC55C-10
BC08S-1
COMMUNI- BC05Z-25
CATIONS
MICROPROCESSOR
LINE
UNIT
SYNCHRO8-BIT
(M8203)
NOUS
DATA
SERIAL
(BIDIRECTIONAL)
DATA
(REMOTE)

SYNCHRONOUS
SERIAL DATA

TO REMOTE STATION
VIA TELEPHONE LINES

(LOCAL)

MICROPROCESSOR
BC08S-1

COMMUNICATIONS
LINE
UNIT
(M8203)

BC55A-10
INTEGRAL
MODEM

SYNCHRONOUS
SERIAL DATA
TO LOCAL STATION
VIA TWINAX OR
TRIAXIAL CABLES

PDP11

MEM

MK-2426

Figure 1-2

Typical PDP-II Applications

1-6

Figure 1-2 shows typical PDP-ll local/remote applications, while Figure 1-3 illustrates similar VAX11/780 applications. Local stations are connected by a single twinaxial or triaxial cable for half-duplex
operation or two cables for full-duplex operation. Remote stations are connected via modems that use
common carrier facilities.

VAX
CPU

(REMOTE)
~-----,

MICROPROCESSOR

B
VAX
MEM

SC08S-1
LINE UNIT
M8203

MEM
CONT.

U
N
MASSBUSS
ADAPTER

S
TELE.
(LOCAL)

~-----, SC08S-1 ,.....;.----'-r---""'I

MICROPROCESSOR

LINE UNIT: INTEGRAL
M8203 I MODEM

/'C55A-10
SYNCHRONOUS
SERIAL DATA
TO LOCAL
STATION VIA
TWINAX OR
TRIAXAL CABLE
MK-2425

Figure 1-3

Typical VAX-l1/780 Applications

1-7

CHAPTER 2
INTERFACE

2.1 SCOPE
The M8203 Line Unit is used in a wide range of synchronous communications applications. The
M8207 or M8204 Microprocessors can be used with the line unit and can be programmed to handle a
variety of protocols and interfaces. This section presents full and half-duplex connections, standard
and special applications, compatible standards, and interfacing information.
2.2 FULL-DUPLEXjHALF-DUPLEX OPERATION
The M8203 Line Unit is capable of either full-duplex or half-duplex operation. The microprogram
controls selection of half-duplex mode; the line unit controls and eliminates contention problems.
Operation of the M8203 Line Unit requires hardware considerations. The full-duplex operation requires two separate local link cables while half-duplex operation requires only one.
Although full-duplex operation requires two cables, it also provides full throughput potential. Halfduplex operation implies half the throughput potential but requires only one cable. The following
questions should be considered when selecting full-duplex or half-duplex operation.
1.

Traffic Flow - Is most of the data going one way or is data flow nearly equal in both
directions?

Data Rate
a.

Is it necessary to use maximum data rate now and in the foreseeable future?

Will the maximum data rate cause UNIBUS latency problems?
NOTE
Each UNIBUS system has a maximum NonProcessor Request (NPR) activity rate. Consider all
NPR devices on the UNIBUS using the maximum
activity rating.

Cable Expense - Is the two cable full-duplex operation worth the expense?

Wiring for half-duplex operation is done by connecting the transmitter and receiver together. A switch
setting, defined by microcode, must be selected on the line unit to inform the microprocessor that the
line unit is installed (Figure 2-1).
NOTE
Refer to the appropriate option Technical Manual
for switch definitions and jumper configurations.

2-1

FULL-DUPLEX

BC08S-1

INSTALL 75Q
TERMINATOR
CONNECTOR (H3257)

BC55A-10

CJ 1211

I!!!!l
MICROPROCESSOR

J1
MICROPROCESSOR

rm:rmJ
80

BC55A-10
TERMINATOR
CONNECTOR
(H3258)

BC08S-1

• FOR 56K bps USE CABLE BC55N-98
FOR 250K bps to 1 M bps USE CABLE BC55M-98
MK-2427

HALF-DUPLEX
BC08S-1

BC55A-10

INSTALL 75
TERMINATOR
CONNECTOR (H32571

Ii!ii!D
MICROPROCESSOR
J1

J1
MICROPROCESSOR

BC55A-10

BC08S-1

• FOR 56K bps USE CABLE BC55N-98
FOR 250K bps to 1 M bps USE CABLE BC55M-98
MK-2428

Figure 2-1

Full-DuplexjHalf-Duplex Connections

2.3 STANDARD APPLICATIONS
The most common application is the Integral Modem which runs at four switch selectable speeds. The
system should be designed in accordance with the guidelines provided in the description of the Integral
Modem in Chapter 3, Technical Description.
There are three interfaces (RS-423-A, RS-422-A, and RS-232-C) that use RS-449 common interface
and standard cables to meet Electronic Industries Association (EIA) specifications. See Figure 2-2 and
Table 1-1.

RS-232-C/CCITIV.2B( ISO 2110)

oO~ ~C05D.25 n=:l
~B""'C5"""5=-=C---JI~
~

BCOBS-1

PANEL
H325

CABLE TEST
CONNECTOR
H325

J2 TEST
CONNECTOR
H3255

J1
MICROPROCESSOR

DiD CJ

IiIIIiD
MK-2429

RS-422-A (RS-449)/CCITIV.ll (ISO 4902)

'- - - -j~k_' ~B

BCOBS-1

H3251

Jl
MICROPROCESSOR

IllD CJ

IiIIIiD
MK-2430

Figure 2-2

Standard (Common) Interfaces (Sheet 1 of 2)
2-3

RS:23_AI:S-~~IIC~Clnv_1PIIS049P~ MODEM I

BCOBS-l

BC55C-l0
~-..,

BC55C
PANEL

BC550-33·
.

H3251

J2 TEST
CONNECTOR
H3255
Jl
MICROPROCESSOR

DID CJ

IliDlD
MK-2431

Figure 2-2

Standard (Common) Interfaces (Sheet 2 of 2)

2.4 COMPATIBLE STANDARDS
All cables used with the Modem Interfaces are described in the following sections and must be ordered
separately. (See Figures 2-3 and 2-4.)

J2
C
M8203
0
EIA
N
SELECTED
N

MICROPROCESSOR

SPECIAL CABLE:
RS 232C/RS422/423
SPECIFICATION
OR NULL MODEM

C
M8203
.0
EIA
N
SELECTED

MICROPROCESSOR

MK-0925

Figure 2-3

Special Application

2-4

n::I

V.35 INTERFACE

BC08S-1

BC05Z-25

Jl TEST
CONNECTOR
H3254

CABLE TEST
CONNECTOR
H3250

Jl
MICROPROCESSOR

MK·2432

Figure 2-4

CCITT V.35 (ISO 2593) Interface

2.4.1 RS-232-CjCCITT V.28 (ISO 2110) Modem Interface
The RS-232-C interface uses the BC55C-I0 panel cable, the BC05D-25 modem cable, and the H325
test connector or alternate. (See Figure 2-2.) M8203 implementation meets RS-232-C standards except
driver protection against shorts to other lines over 10 volts and the drive impedance. RS-232-C states
minimum drive impedance of 300 ohms without controlled rise and fall times. The new drivers have a
500 ohm impedance on the line accomplishing the same effect. A switch in the Modem Interface Selection Circuitry of the M8203 Line Unit (D7 of the M8203 Print Set) must be set to the single-e:tded
output.
RS-232-C interfacing is limited to a maximum speed of 19.2K bps and is designed to interface to existing modems. The new EIA interface specifications RS-449 and RS-422-AjRS-423-A should be implemented.
The speed of the NULL clock is switch selectable and should not be set above 19.2K bps (see Section
3.5, Data Rate Generator). The maximum cable length for the RS-232-C interface is 15.24 meters (50
feet).

NOTE
1.

In some configurations, the BCOSC-2S cable
can be used in place of the BCOSD-2S cable for
RS-232-C applications. However, some options
such as the DMRll do not support using the
alternate cable. Refer to specific options man·
ual for use of the BCOSC·2S.

In configurations where the BCOSC-2S cable is
used, removal of certain M8203 jumpers may
be necessary to ensure acceptable operation.

2-5

Jumper

Condition

To disable Signal Rate (on some modems
used as a test clock)

To disable Data Mode- May cause problems with some modems where pin 18 is
used for dibit clock

To disable Null Clock- May cause problems with some modems

W10

To disable Terminal Ready- May cause
problems with some modems where pin
lOis used for a negative test voltage

W12

To disable Terminal in Service - May
cause problems on some modems

2.4.2 EIA Standard RS-423-A
The RS-423-A is compatible with the Federal Standard 1030 and the Comite Consultatif Internationale
de Telegraphie et Telephone (CCITT)V.10 and X.26/lnternational Standards Organization (ISO)
4902. RS-423-A interface is single-ended and is subject to the RS-449 and Federal Standard 1031 interface with a new cable and test connector. Panel cable BC55C-10, modem cable BC55D-33, and test
connector H3251 are used. The BC55C panel cable is a flat cable and the BC55D-33 modem cable is a
round extension cable used for unprotected external runs.
A switch (E39-7) in the Modem Interface Selection Circuitry of the M8203 Line Unit (D7 of the
M8203 Print Set) must be set to the single-ended mode. Signal levels are provided in Section 2.4.4. The
maximum speed is limited to 56K bps by the rise time (limited to 20K bls by RS-449 and 9600 bls by
ISO 4902). (Refer to the RS-423-A specification for more detail.) The maximum cable length is 60.48
meters (200 feet) as defined by the rise time used in the RS-423-A specification.
The RS-423-A interface standard specifies unbalanced circuits, but the M8203 uses a balanced differential receiver (26LS32) with a common return for improved performance at greater distances. The
speed limitation of the M8203 electrical circuits under RS-423-A implementation without RS-449 implementation is limited to 56K bps which is imposed by software and other factors.
Applications using RS-423-A with. RS-449 implementation are limited to a maximum speed of 20K bps
and for ISO 4902 the speed is limited to 9600 bps.
2.4.3 EIA Standard RS-422-A
RS-422-A is compatible with Federal Standard 1020 and CCITT V.ll and X.27/1S0 4902. It is a
differential interface and subject to EIA specification RS-449 and Federal Standard 1031 (signal levels
are provided in Section 2.4.4). RS-422-A uses the panel cable BC55B-10, modem cable BC55D-33, and
test connector H3251.
A switch (E39-7) in the Modem Interface Selection Circuitry of the M8203 Line Unit (D7 of the
M8203 Print Set) must be set to the differential mode as defined in the RS-449 specification. The
maximum data rate for the RS-422-A interface is limited to 1M bps by the line unit. The rise time is
less than 200 ns. Maximum cable length is defined by RS-422-A.

2-6

The balanced circuits of RS-422-A use differential generators and receivers over a pair of wires for
each signal. This type of circuit requires more wires·in a cable to support all the signals, but only circuits that are speed sensitive generally use this interface standard. The circuits which are speed sensitive are defined as Category I type circuits under the RS-449 Interchange Standard, and those that are
not speed sensitive as Category II type circuits. The speed sensitive circuits are data signals, timing
signals, and any control signal that must respond quickly. These speed sensitive circuits (Category I
type) usually implement balanced type circuits using the RS-422-A Electrical Standard. Terminating
resistors (RT) are used at the receiver to achieve top performance for distance and speed.
NOTE
Terminating resistors of 100 ohms are built into the
BCSSB-I0 cable.
If properly terminated, the maximum cable length is 1.22 km (3865 feet); if terminating resistors are
not used, the maximum cable length is 12.19 meters (40 feet).

2.4.4 EIA Standard RS-449
The RS-449 is compatible with CCITT Standards V.24, ISO Standard 4902, and Federal Standard
1031. RS-449 is used by all EIA interfacing cables, either single-ended or differential. The switch (E397) in the Modem Interface Selection Circuitry of the M8203 Line Unit (D7 of the M8203 Print Set)
can be set to single-ended (unbalanced) or differential (balanced) mode with no interlock between the
cable and the interface. The maximum speed for each ElA interface is specified in rei event sections of
this manual and in more detail in the ElA specifications.
NOTE
EIA Specifications may be obtained from:
EIA Engineering Department
Electronic Industries Association
2001 Eye Street N.W.
Washington, D.C. 20006
RISE TIMES:
•

Single-ended = 5 microseconds

•

Differential = 200 nanoseconds

RISE TIME LIMITATIONS:
•

Provides a means of calculating maximum cable length for use with each EIA interfacing level

•

Rise times may be adjusted for specific variations of the M8203

CABLE LENGTHS:
•

RS-232-C limited to 15.24 meters (50 feet) by specification

•

RS-423-A limited to 60.48 meters (200 feet) by rise time

2-7

•

RS-422-A must be terminated with a maximum limit of 1.22 km (3865 feet) if all the
guidelines in the RS-422-A specification are followed

•

Standard cables are all modem interfaces of 7.62 meters (25 feet) for older cables and 10
meters (33 feet) for new cables

•

Special cable or NULL modem arrangements (Contact Computer Special Systems
(CSS»

SIGNAL LEVELS (New RS-449 Specifications):
•

Maximum output voltage = ± 6 volts

•

Minimum output voltage with no load = ± 5 volts (single-ended outputs)

•

A 450 ohm resistor used as a load will not drop the output voltage more than 10 percent

•

The differential outputs maximum output = ± 5 volts (referenced between the outputs
with no load). With a balanced 100 ohm load, the output will not drop more than 10
percent

•

The minimum output with no load = ± 2 volts

•

The balance error will not exceed 0.4 volts

•

System ground differences cannot exceed 3 volts

•

The output is protected to ± 10 volts at 150 milliamps from voltages applied to the
wrong pins when the modem is connected

•

RECEIVE COMMON is tied to ground by a 100 ohm resistor for a fail-safe condition
when no receiver ground is supplied to the interface

•

SEND COMMON is tied directly to ground and is not current limited

•

The shield grounds also tie directly to ground and are not current limited

The receivers are set up to accommodate differential inputs for the RS-422-A (see Section 2.4.3). Resistors are provided for fail-safe operation. The differential signals can be changed to single-ended (or
when not connected) and allow the receivers to go to the fail-safe state. The receivers also go to the failsafe state when power is off on the modem. The maximum signal off-set is 3 volts. The receivers can
withstand a maximum voltage of plus or minus 25 volts without damage to the components. The operating range is ± 15 volts. The RS-449 is a fail-safe interface when no signal is provided or the wire is
open for that particular receiver. The Integral Modem Cable selects the interface when the cable is
plugged in.
NOTE
The software is unable to tell if the cable is not connected or if the modem is not operating.
The M8203 reports that the RS-449 interface is enabled for either single-ended or differential mode.
The RS-449 interface is made as fail-safe as possible. If a ground line or return line is open, there are
pull-up resistors that compensate for the open-line. The signals received are pulled to a fail-safe state
when power is off on the modem or when any of the lines except data and timing are open or left unterminated.
2-8

The M8203 supports the following RS-449 category 1 signals:
Circuit

Description

Send Data

Receive Data

Terminal Timing (Null Clock)

Send Timing

Receive Timing

Request to Send

Clear to Send

Receiver Ready (Carrier)

Terminal Ready (Data Terminal Ready = DTR)

Data Mode (Modem Ready)

These circuits are supported in differential and single-ended mode for RS-449. The receivers and drivers are all fail-safe circuits so the differential receivers handle single-ended lines. Drivers are selected
by a switch and must match the interface cable.
2.4.5 CCITT V.35/ISO 2593
The V.35 interface uses the BC05Z-25 cable and the H3250 test connector (the same connector used
by the Integral Modem). When the cable is plugged in, a bit is set in the extended registers (see Chapter 3, Technical Description) that indicates that the V.35 mode has been selected. The maximum speed
is 250K bps. The NULL clock is switch selectable from 2.4K bps to 1M bps (see Chapter 3, Technical
Description).
2.5 INTERFACE SIGNALS
Table 2-1 lists all the signals handled by the standards described in the previous sections and the associated pins at the modem.
A list of interchange circuits showing the nearest equivalent RS-232-C, RS-449, and CCITT identification in accordance with recommendation V.24 is presented in Table 2-2. It should not be inferred
that circuit definitions given are in exact accord with RS-232-C, RS-449, and CCITT recommendations.
2.6 ADDITIONAL LINE UNIT OPTIONS
The M8203 Line Unit is set up so the CRC 32 chip can be used with the Universal Synchronous Receiver/Transmitter (USYRT) by cutting four etches and installing the chip.
NOTE
This option must be factory installed. It may not be
installed in the field.
2. 7 HARDWARE VARIABLES
The M8203 contains three switch packs (E39, E121, and E134) and 17 jumpers (WI through W17)
which are used to select certain features and/or configuration variations. Some of these switches and

2-9

jumpers may be used differently in specific options such as the DMRl1. For a more detailed description of each switch and jumper, refer to the specific options manual.
The purpose of this section is to identify each switch and jumper, and to provide a general description
of each.
•

Jumper Functions - Jumpers WI-W17 are used to select various interface standard parameters and modem interface signals, depending on application and modem type. Additional
jumpers are available on the BCSSC (panel) cable for additional interface signal selection.

•

Switch Pack E39 Functions - This switch pack allows proper selection of interface driver and
receiver control logic and different line speeds for various applications.

•

Switch Pack E121 Functions - This switch pack is physically connected to internal registers.
The function of each switch is microprogram dependent and may be different depending on
the option selected. Refer to specific option manual for details.

•

Switch Pack E134 Functions - This switch pack is physically connected to internal registers.
The function of each switch is microprogram dependent and may be different depending on
the option selected. Refer to specific option manual for details.

2-10

Table 2-1 Interface Signals/Pins at the Modem
SIGNALS

PIN AT MODEM
RS-449

CLEAR TO SEND (+)

RS-232-C

RS-423-A

RS-422-A

V.35

CLEAR TO SEND (-)
DATA MODE(+)

DATA MODE(-)
(Modem Ready)

INCOMING CALL
(Ring)

LOCAL LOOP

18*

NEW SIGNAL
PROTECTIVE GROUND

RECEIVE COMMON
RECEIVE DATA (+)

RECEIVE DATA (-)
RECEIVER READY (+)

RECEIVER READY (-)
(Carrier)
*Selected by a jumper on the BC55C-10 cable.

2-11

Table 2-1 Interface Signals/Pins at the Modem (Cont)
PIN AT MODEM

SIGNALS

RS-449

RECEIVE TIMING (+)

RS-232-C

RS-423-A

RS-422-A

V.3S

17*

RECEIVE TIMING (-)
REMOTE LOOP

21*

REQUEST TO SEND (+)

REQUEST TO SEND (-)
SELECT STANDBY

SEND COMMON

SEND DATA(+)

SEND DATA (-)
SEND TIMING (+)

15*

SEND TIMING (-)
*Selected by a jumper on the BCSSC-I0 cable.

2-12

Table 2-1 Interface Signals/Pins at the Modem (Cont)
PIN AT MODEM

SIGNALS

RS-449
RS-232-C

RS-423-A

RS-422-A

SHIELD GROUND

SIGNAL GROUND

SIGNAL QUALITY

21*

SIGNAL RATE INDICATOR

23*

SIGNAL RATE SELECT

23*

STANDBY INDICATION

25*

TERMINAL IN SERVICE

25*

TERMINAL READY (+)

TERMINAL TIMING (-)
(Null Clock)
TEST MODE

TERMINAL READY (-)
(Data Terminal Ready = DTR)
TERMINAL TIMING (+)

V.35

25*

*Selected by a jumper on the BC55C-I0 cable.

2-13

Table 2-2 Equivalency Table

EIARS-449

EIA RS-232-C

CCITT
RECOMMENDATION
V.24

AA SHIELD GROUND
SG SIGNAL GROUND

AB SIGNAL GROUND

UU
102 SIGNAL GROUND

AA PROTECTIVE GROUND

VV
A/B

SC SEND COMMON

102a DTE COMMON

RC RECEIVE COMMON

102b DCE COMMON

IS TERMINAL IN SERVICE

J2
BERG CONN
PIN

IC INCOMING CALL

CE RING INDICATOR

125 CALLING INDICATOR

TR TERMINAL READY ( + )

CD DATA TERMINAL
READY

108/2 DATA TERMINALREADY

tv
I

TR TERMINAL READY (-)
DM DATA MODE (+)

CC DATA SET READY

107 DATA SET READY

DM DATA MODE (-)
SD SEND DATA (+)

U
BA TRANSMITTED DATA

103 TRANSMITTED
DATA

SD SEND DATA (-)
RD RECEIVE DATA (+)
RD RECEIVE DATA (-)

F
KK

BB RECEIVED DATA

104 RECEIVED DATA

Table 2-2 Equivalency Table (Cont)

EIARS-449

EIA RS-232-C

TT TERMINAL TIMING

DA TRANSMITTER SIGNAL
ELEMENT TIMING
(DTE SOURCE)

CCITT
RECOMMENDATION
V.24

J2
BERG CONN
PIN

113 TRANSMITTER
SIGNALELEMENTTIMING
(DTE SOURCE)

TT TERMINAL TIMING (-)
ST SEND TIMING ( + )

EE
DB TRANSMITTER SIGNAL
ELEMENT TIMING
(DCE SOURCE)

114 TRANSMITTER
SIGNAL ELEMENTTIMING
(DCE SOURCE)

ST SEND TIMING (-)

tv
I

RT RECEIVE TIMING ( + )

t il

TT
DD RECEIVER SIGNAL
ELEMENT TIMING

115 RECEIVER SIGNAL
ELEMENT TIMING
(DCE SOURCE)

RT RECEIVE TIMING (-)
RS REQUEST TO SEND ( + )

CA REQUEST TO SEND

105 REQUEST TO SEND

CB CLEAR TO SEND

106 READY FOR SENDING

CF RECEIVED LINE SIGNAL DETECTOR

109 DATA CHANNEL RECEIVED LINE SIGNAL
DETECTOR

RR RECEIVER READY (-)
SQ SIGNAL QUALITY

V
AA

CS CLEAR TO SEND (-)
RR RECEIVER READY ( + )

SS
R

RS REQUEST TO SEND (-)
CS CLEAR TO SEND ( + )

H
CG SIGNAL QUALITY DETECTOR

lIO DATA SIGNAL QUALITY DETECTOR

Table 2-2 Equivalency Table (Cont)

EIARS-449

EIA RS-232-C

CCITT
RECOMMENDATION
V.24

NS NEW SIGNAL

J2
BERG CONN
PIN
HH

SF/SR * SELECT FREQUENCY/
CH DATA SIGNAL RATE
SELECTOR (DTE
SOURCE

126 SELECT TRANSMIT FREQUENCY
III DATA SIGNALING
RATE SELECTOR
(DTE SOURCE)

CI DATA SIGNAL RATE
SELECTOR (DCE
SOURCE)

112 DATA SIGNALING
RATE SELECTOR
(DCE SOURCE)

LL LOCAL LOOPBACK

141 LOCAL LOOPBACK

RL REMOTE LOOPBACK

140 REMOTE LOOPBACK

TMTESTMODE

142 TEST INDICATOR

SS SELECT STANDBY

116 SELECT STANDBY

SB STANDBY INDICATOR

117 STANDBY INDICATOR

SIGNALING RATE SELECTOR
SI SIGNALING RATE INDICATOR

DTE = Data Terminal Equipment
DCE = Data Circuit-terminating
Equipment

* SF and SR share the same pin.

CHAPTER 3
TECHNICAL DESCRIPTION

3.1 SCOPE
The technical description and programming of the M8203 Line Unit Circuitry is presented at the
functional level. The intent is to provide the Field Service representative with enough information to
troubleshoot the line unit. Logic block diagrams supplement the text and make reference to the M8203
Print Set thereby providing the additional information required to troubleshoot to the gate level.
Definition of the register bits and special chips may be useful to the programmer as well as the technician.
The major functional areas shown in Figure 1-1 are described in the following sections in the sequence
given below.
•
•
•
•
•
•
•

Berg Port Interface
Silos
Sequencer
Data Rate Generator
Universal-Synchronous Receiver/Transmitter (USYRT) Device
Modern Interface
Integral Modern

NOTE
D( x) references in the text are based on the signal
map rather than actual sheet numbers of the M8203
Print Set.
3.2 BERG PORT INTERFACE
The Berg Port Interface has eight basic input and output registers expanded by second level addressing
to eight more registers (See Figure 3-1).

3-1

WRITE
OUT REG

I 6 I 5 I 4 I 3 I 2 I 1 I 0

POLL

GO AH ABORT

I 5 I 4 I 3 I 2 I 1 I 0

IBUS REG.

TRANSMIT DATA SILO

READ

EOM

SaM

LULP

DTR

SEL
FREQ

HDX

MAIN
1

MAIN
2

SEL
STBY

TXU
ENA

DISSI

RDAX

WAX

ENAX

AX2

AX1

RECEIVER DATA SILO

OACT

SW
E134

ORDY

SW
E134

SW
E121

SW
E12l

UNDR

IACT

LULP

IRDY

OVRR

RAB

EBLK

BCC

RING

DTR

HDX

MOOR

STBY

CARR

ROY

TXU
ENA

DISSI

RDAX

WAX

ENAX

AX2

AX1

ECS

DDCMP

REaM

RSOM

TEaM

TSOM

(OX) 15

LOW BYTE EXT REG

SWITCH (X)I LOW BYTE EXT

(OX) 16

HI BYTE EXT REG

SWITCH (Y) I HI BYTE EXT

CRC TYPE

IDLE

SECA

STRIP

RDALL

NOT USED

AXO-16

NOT USED

AX1-15

TRANSMIT DATA USYRT

TXGA

RERR

TXAB

AX2-15

SYNC CHARACTER

AX2-16

NOT USED

AX3-15

AX3-16

422

XYZ

BCC
C32

TX CH LENGTH

SIG R

SIG Q

OCOR

ICIR

TEST
MODE

RECEIVER DATA USYRT

AXO-15

AX1-16

IERR DDCMP

BITS ASSEMB

ROR

RAB

TRANSMIT DATA USYRT

TEOM TSOM

TERR

TXGA

TXAB

SYN CHARACTER

APA

V35

INT

EN
C32

TX
CLE

RX
CLE

REC CH LENGTH

TEST

422

ODCMP STRIP

SECA

IDLE

BCC
C32

V.35

INT

EN
C32

TX
CLE

RX
CLE

REC CH LENGTH

XYZ

TX CH LENGTH

CRC TYPE

TEST

MK-0916

Figure 3-1

Input/Output Registers

3-2

INBUS/OUTBUS and INBUS* /OUTBUS* refer to two register groups or categories within, and
accessed by, the microprocessor. This terminology is used in microinstruction formatting. It defines
the group of registers to be accessed by the microprocessor and whether the particular register is used
as a source or destination for data.
•

The "*,, indicates one register group; the absence of the "*,, indicates the other register
group.

•

The "IN" portion of the term identifies the specific register as the data source.

•

The "OUT" portion of the term identifies the specific register as the destination for data.

•

The "BUS" portion of the term does not refer to a physical BUS.

•

The following terms are synonymous:
OUTBUS and OUT
INBUS* and IBUS*
OUTBUS* and OUT*
INBUS and IBUS

Registers in the "*,, group (lBUS* /OUT*) are located in the Microprocessor Multiport Random
Access Memory (RAM):
CSR Bytes 0-7
NPR Control
#-,p Miscellaneous

(Registers 0 to 7 are R/W)
(Register lOis R/W)
(Register II is R/W)

Registers in the INBUS/OUTBUS group located in the microprocessor:
IN DATA LB

IN DATA HB

OUT DATA LB

OUT DATA HB

INBA <7:0>

IN BA <15:8>

OUTBA <7:0>

OUT BA < 15:8>

3-3

DMA data from
memory to the
microprocessor
DMA data from the
microprocessor to
memory
DMA address for
data from memory
to the microprocessor
DMA address for
data from the
microprocessor to
memory

Registers in the INBUS/OUTBUS group located in the line unit:
RECEIVER DATA SILO

TRANSMIT DATA SILO

OUT CaNT

IN CaNT

MODEM CaNT

SYNC REG

SW PACK (X)

Register 15 - Read only - Contents = Switch Pack
X/Low Byte of Extended Register.
Register 16 - Read only - Cont~nts = Switch Pack
Y /High Byte of Extended Register.

SW PACK (Y)

MAINT REG
I.

NOTE
Address Extended (AX) registers are indirectly
addressed by using AXI and AX2 for address,
Write to Extended registers (WAX) for write,
Read to Extended registers (RDAX) for read,
registers IS and 16. for data, Enable Extended
registers (ENAX) going to a one to start the
operation, and Ready (RDY) to tell when the
operation is complete.
The bit map as seen by the KMCll and
DMCII Microprocessors.

3.2.1 Read IBUS Registers
The line unit input registers are 12 tristate D-Type flip-flops (74LS374s). Extended registers are primarily used to load or verify USYRT registers~ They can also be used for special protocols. IBUS and
extended IBUS register selection is done by the microprocessor Control Read Only Memory (CRaM)
lines 4-7. The lines are decoded via a 74S 138 decoder/multiplexer and used to enable the selected input
register (See Figure 3-2). INBUS Read (IBR H) is used to shift data out of the receive silo (D5 of the
M8203 Print Set).

3-4

BERG PORT
CONN, J3
CROM
7

74S138

IREG's
17
16
15
14
13
12
11
10

SElA
SEl B

6 CC

SEl C

5 AA
4

RR
+3

INPUTS
EN

':'

Q 'Q'
IBR l

IBR H

(REC SilO)

OUTPUTS
IREG EN

SELECT
CBA
000

001

01 0

011

1 00

10 1

1 10

1 1 1

MK·0924

Figure 3-2

IBUS Register Select

3.2.2 OBUS Registers
The buffered Arithmetic Logic Unit (ALU) lines from the microprocessor are inverted via a 74S240
then routed to the output register inputs. Selection of the output registers is done by the microprocessor CROM lines 3-0 which are decoded via a 74S 138 decoder jmuItiplexer (See Figure 3-3).
OUTBUS Write (OBWL) is used to gate the load pulse to the registers (D3 of the M8203 Print Set).

INPUTS

OUTPUTS

SELECT
CBA

OUT REG ClK

0
0
0
0

000
001
01 0
o1 1

17
16
15
14

0
0
0
0

1 00
10 1
1 10
1 1 1

13
12
11
10

EN = OUT*l
OBW l
CROM 3 l
SELECT
CROM 2 = C
CROM 1 = B
CROM 0 =A
MK·0929

Figure 3-3

aBUS Register Select

3-5

3.2.3 IBUS/OBUS Registers Bit Descriptions
Figures 3-4 through 3-19 provide the input and output registers, bit descriptions, and qualifications for
read and write operations.

-RE-CEIV-E S-ILOI

I
I

3341

1--_1_ _ _ _ _ _ _ _ __.
SILO

< 3: 0> H

DATA

I
DATA

I
I

3341

I
I
I

3341

SILO

< 7:4> H

RECEIVER DATA SILO

IBUS REGISTER 10

I STATUS

IL ____ I

51 LO < 11 :8> H
REGISTER 12

IN RDY H

TRUE
INDICATES
VALID DATA AT
OUTPUT OF SILO

SEE FIGURE 3-12
FOR BIT DESCRIPTION

,'7'6'5'4'3'2'1'0'
I I , , , I I ,
REGISTER BITS
MK-0946

Figure 3-4

IBUS Register 10

Read Operation:
•

Reads data in and shifts the silo.

•

Status bits (register 12) are read first.

•

3-6

LOAD DATA TO BE TRANSMITTED

TRANSMIT DATA SILO
BALU BITS

)

OBUS REGISTER 10

DATA

rTRANSMI
SILO

RE~T~~~

BITS

3341

I
I

I II
I

3341

I
I

3341

I _ _ _ _ ...JI
L
MK-0898

Figure 3-5

OBUS Register 10

Write Operation:
•

Loads data to be transmitted into and shifts the silo.

•

Status bits (BALU 3-0) from OBUS register 11 are also loaded into the silo when OBUS
register 10 loads the silo. The status bits, if they are required, should be loaded first.

•

All bits are cleared when the silo is shifted.

•

Data should not be written into register 10 unless status Bit 4 of read IBUS register 11 (Out
Ready) is set.

3-7

LINE STATUS
USYRT
WRITE OUT REG 11
SWITCHES
USED BY
IJ.CODE
FOR LINE
STATUS

- - - - ( USYRT

IBUS REGISTER 11

1 7 I 6 I 5 I 41

12 I 1

BITS

SWITCH OFF = LOGICAL 1
MK·0947

Figure 3-6 IBUS Register II
Read Operation:

•

Bits 1-3 and 5 (switch) have no hardware control. They should be set up when the module is
installed in the field according to the customer link (the microcode and microprocessor
used). Refer to the appropriate Options Technical Manual.

•

Bit 0 = a transmitter underrun has occurred meaning characters have not been supplied to
the transmitter fast enough, causing the USYRT to go to the IDLE state. (Can only be
cleared by the next Start of Message (SOM) or by clearing the transmitter.)

•

Bit 4 = Out Ready - the silo is ready for another character. If the silo is disabled, it indicates
that the USYRT is ready for another character.

•

Bit 6 = Out Active - the USYRT is in the process of transmitting data. If Out Active is set
and Request to Send is not set, no characters are processed (check Modem Ready and Clear
to Send bits in IBUS register 13).

•

Bit 7 = Out Clear - transmitter is in the process of being cleared and should not be addressed. This bit must not be set until In Clear (IBUS register 12, bit 7) is clear; that is, Out
Clear should not be set when an In Clear is in progress.

3-8

CONTROL TRANSMIT CIRCUITRY
BALU BITS

I7
OBUS REGISTER 11

TO TRANSMIT
SILO (FIGURE 3-17)

IBUS REG 11

MK-0899

Figure 3-7

OBUS Register II

Write Operation:
•

Bits 0 to 3 are loaded into the silo before register lO loads the silo and are used to transmit
characters or cyclic redundancy check (CRC).
Bit 0 = Start of Message (SOM) - used to transmit flags (OllllllO) in bit oriented protocols or is loaded with a sync character to set up the transmitter and receiver
for data that is to follow.
Bit 1 = End of Message (EOM) - used to send the CRC character, if CRC is
enabled in both protocols, and the trailing flag or sync character.
NOTE
A minimum of two SOMs must be sent at the start of
a character oriented message.
Bit 2 = Send Abort - used in bit oriented protocol (11111111).
Bit 3

•

= Send Go-Ahead -

used in bit-oriented protocols only (01111111).

Bit 7 = Clear the Transmit Circuitry - Out Clear (OC, IBUS register 11) must be 0 before
loading the transmitter.
NOTE
If the transmit silo is full, the Out Clear function
will not clear the transmitter.

3-9

RECEIVER STATUS

WRITE OUT

TRANSMIT

::~~~ ~

WRITE OUT REG. 12

SIL((

(

< 11 : 8> H

RECEIVE

SILO

IC IIACT ILULPIIRDVIOVRRI RAB I EBLKI BCC

IBUS REGISTER 12

I 6 I 5 I 4 I 3·1 2 1 1 1 0 I BITS
MK-0903

Figure 3-8

IBUS Register 12

Read Operation:
•

Bits 0-3 = status of the USYRT (data character in IBUS register 10). When IBUS register 10
is read, bits 0-3 are updated to the next character.

o = Block Check Character (BCC) match - only valid at the end of the message or after the
last data character (bit oriented protocol when EOM is set).
NOTE
BCC match is valid two characters before the previous DMCll Line
Units (M8201 and M8202).
One = correct CRC or match in character oriented protocol.
Zero = correct CRC or match in bit oriented protocol.
Bit 1 = End of Block in bit oriented protocol - indicates End of Message & Bec match
is valid.
Bit 2 = Received Abort - bit oriented protocol, 7 ones received.
Bit 3 = Receiver Overrun - data is not being removed fast enough from the receiver silo
meaning data for this message is not valid and should be discarded. OVRR will clear
when receiver is cleared (lC).
•

Bit 4 = In Ready - the next character is ready to be read from the receiver silo. If the silo is
disabled, a character is ready to be read from the USYRT.

•

Bit 5 = Line Unit Loop -line unit is in maintenance mode and transmit data is being turned
around in the USYRT. *

*Strictly internal to the USYRT; not to be confused with the line unit loop set in the microprocessor
CSR 0 which is a loop back mode that is external to the USYRT. If RUN on the microprocessor:
(1)
(2)

is set, the USYRT is run at 24K bps.
is not set, the clock is generated from the Step Line Unit bit 12 of CSR O.

3-10

•

Bit 6 = Receiver Active - receiver has started to process data. The carrier bit M IBUS
register 13 must be set or the receiver will not become active.

•

Bit 7 = In Clear - receiver circuit of USYRT and the silos are in the process of being cleared.
LINE UNIT LOOP & RECEIVER CLEAR

BALU BITS

I7 I6 I5 I4 I 3 I2 I1 I0 I
OBUS REGISTER 12

IBUS REG. 12
MK-0896

Figure 3-9 OBUS Register 12
W rite Operation:

•

Bit 5 = Line Unit Loop - enables the maintenance mode of the USYRT which loops the
data back internally to the USYRT. Selects internal clock if RUN is set or Step Line Unit if
R UN is not set.

•

Bit 7 = Clear the Receiver Circuit of the USYRT (silos also cleared) - used to clear the
receiver CRC in byte oriented protocol. In Clear must not be set until Out Clear (IBUS register 12, Bit 7) is clear; that is, In Clear should not be set when Out Clear is in progress.

3-11

STATUS AND CONTROL OF
MODEM INTERFACE

\.
MODEM
RECEIVERS

OUTPUT REG
13

IBUS REGISTER 13

I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I BITS
MK-0901

Figure 3-10 IBUS Register 13
Read Operation:
•

Bit 0 = Carrier (Receiver Ready) - indicates that the Integral Modem or Modem Interface is
active. The carrier signal must be set before the USYRT receiver processes characters. The
carrier is used by the USYRT to clear the CRC registers between messages.

•

Bit 1 = Standby - references standby indication from the modem (see EIA specification).

•

Bit 2 = Clear to Send - a reply from the modem used by hardware to start sending data.
Clear to Send must be low for Request to Send to set. With the Integral Modem, a 100 ILS
delay occurs before Clear to Send is set.

•

Bit 3 = Modem Ready (Data Mode) - modem is in service. Used with Modem Interface and
is a hardware lockout of Request to Send until modem ready is set (see EIA specification).

•

Bit 4 = Half-Duplex - the line unit logic is set in the half-duplex mode.

•

Bit 5 = Request to Send - the USYRT is ready to start transmitting data and will start as
soon as Clear to Send is true. Request to Send does not set unless Out Active is set, Modem
Ready is set, and Clear to Send is not set.

•

Bit 6 = Data Terminal Ready (Terminal in Service) - signal to modem from the line unit
indicating that the line unit is available and on line (see EIA specification).

•

Bit 7 = Ring or Incoming Call - the modem has just been dialed and data is forthcoming
(see EIA specification).

3-12

STATUS AND CONTROL OF MODEM
BALU BITS
OBUS REGISTER 13*
MODEM
INT. DRIVER
IBUS REG 13
& MODEM INTERFACE
MODEM INTER
IBUS REG 13
& INTERLOCK

~ MODEM INTERFACE

MK-0952

Figure 3-11

OBUS Register 13

Write Operation:

•

Bit 1 = Select Standby when a modem interface is used (see EIA specification).

•

Bit 2 = Maintenance Mode 2 - remote loopback using the modem interface and the external
modem. It is used to test the modem (see EIA specification).

•

Bit 3 = Maintenance Mode 1 - local loop using the Modem Interface and the external
modem - tests the interface to the modem (see EIA specification).

•

Bit 4 = Half-Duplex - sets the line unit in the half-duplex mode; the line unit either transmits or receives at any given time (hardware interlocked controlling the line unit).

•

Bit 5 = Select Frequency - used on Modem Interface to change modem data rates (see EIA
specification).

•

Bit 6 = Data Terminal Ready (Terminal Ready) - indicates to the modem that the line unit
is ready to receive or transmit data. It must be set when the Modem Interface is used,
otherwise, the modem ignores other control signals from the line unit.

•

Bit 7 = Polling - a new function for RS-422-A, RS-423-A, and RS-449 (not clearly defined).
Intended for use with multidrop modems.

*For switched line booting, OBUS Register 13 is not cleared by a Master Clear or Initialize.

3-13

WRITE OUT
OBUS REGISTER 14

SEQUENCER

AX1

IBUS REGISTER 14

BITS
MK·0897

Figure 3-12

IBUS Register 14

Read/Write Operations:
NOTE
Sync character or secondary address must be loaded
through the extended registers. Register 14 is used
for extended register control (unlike previous
DMCII line units).
•

Bit 0 = Extended Address Bit 1 - used to select the USYRT register that is being written to
or read from.

•

Bit 1 = Extended Address Bit 2.

•

Bit 2 = enables the extended registers - starts the extended operation when set.

•

Bit 3 = selects a write operation through the extended registers.

•

Bit 4 = selects a read operation through the extended registers.

•

Bit 5 = disables the silos so that the USYRT can be loaded and read directly.

•

Bit 6 = Transmitter Enable - must be set before characters are loaded into the USYRT
when the line unit is programmed with the silos disabled. When the silo is enabled, keeps
Request to Send set.

•

Bit 7 = Ready (Read only) - the operation executed through the extended registers is completed. Other bits in registers 14, 15, and 16 should not change unless the Ready bit is set.

The normal operation using extended registers:
•

Extended address must be loaded first.

•

If a write: data must be loaded in write out (OBUS) registers 15 & 16. Set WAX and the
enable bit.

•

If a read: Set RDAX and the enable bit.

•

The operation is complete when Bit 7 becomes true.

3-14

LOADING THRU EXTENDED REGISTERS

BALU BITS
OBUS REGISTER 14

IBUS REG 14
74S174 FUNCTION LATCH
(06 OF M8203
PRINT SET)

<3: 0 >

MK-0958

Figure 3-13

OBUS Register 14

Read/Write Operations:
Refer to Figure 3-13 for bit definitions.

SW"X"
(E134)

IBUS REGISTER 15

SWITCH PACK (X) LOW BYTE EXT
SWITCH OFF

= LOGICAL 1
MK-0934

Figure 3-14

IBUS Register 15

Read Operation:
•

A normal read from register 15 is a switch pack defined by microcode. Refer to the appropriate Options Technical Manual.

•

In extended addressing mode, IBUS register 15 is the low byte of data read from the extended register defined by the extended address bits. (See Extended Register Description,
Section 3.2.4.)

•

The extended address data is only true when the relevant bits are set for the extended address
and Bit 7 of register 14 is set. (See Extended Register Description, Section 3.2.4.)

3-15

BALU BITS

LOW BYTE EXT REG

DIP

<7:0 >H

OBUS REGISTER 15

)

----------~()~------TRISTATE
CONNECTION
(TO USYRT)

(SEE

04 OF M8203 PRINT SET)
MK-0951

Figure 3-15

OBUS Register 15

Write Operation:
•

A write to OBUS register 15 in normal mode is not val~d.

•

A write to OBUS register 15 is only valid in extended mode.

•

Any write to OBUS register 15 is loaded in the extended data register (low byte), but data is
not used until the extended address is set up and WAX and EN AX are set, except AX3-15,
which must be selected before data is written into OBUS register 15.

•

See Extended Register Description, Section 3.2.4.

86 76 66 56 4b 36 26 16
d' (( (( ({ ({ ({ if ((
1716151413121110

SW"Y"
(E 121)

IBUS REGISTER

SWITCH PACK (y)' HI BYTE EXT
SWITCH OFF = LOGICAL 1
MK-0932

Figure 3-16

IBUS Register 16

Read Operation:
•

Similar to Register 15.

•

A normal read is from the switch pack defined by microcode.

•

In extended mode, the register is the high data byte for extended addressing, whose data is
only valid when Bit 7 of register 14 is set.

•

Refer to Extended Register Description, Section 3.2.4.

3-16

BALU BITS

1 7

1 6

1 5 141 3

1 I

HI BYTE EXT REG

OBUS REGISTER 16

DIP<15:8>H
)
---------~~~--------TRISTATE
CONNECTION
TO USYRT (HIGH BYTE)

(SEE D4 OF M8203 PRINT SET)

MK-0957

Figure 3-17

OBUS Register 16

Write Operation:
•

A write to register 16 loads data only into the data register for the extended addressing
function.

•

The data is used after the address is set up and WAX and ENAX are set.

•

Refer to Extended Register Description, Section 3.2.4.
MAINTENANCE FUNCTIONS

TRANSMIT
SILO

~----------<

RECEIVE SilO
EIA MODEM
RECEIVERS
_ - - - < MAINTENANCE
ClK
OUT REG. 17

-------<

USYRT
EIA MODEM
INTERFACE

OCOR

ICIR

IBUS REG. 17

ECS

2·

BITS
MK-0959

Figure 3-18

IBUS Register 17

Read Operation:
•

Bit 0 = Line unit mode
o = Bit oriented protocol
1 = Character oriented protocol (initializes to a 1).

•

'Bit 1 = Maintenance clock step line unit or 48 KHz.

•

Bit 2 = Test mode, modem attached to EIA interface is in the test mode (see EIA specification).

3-17

•

Bit 3 = In composite ready, the receive silos are ready to receive another character (maintenance mode only).

•

Bit 4 = Out composite ready. data is present at the bottom of the transmit silo for transfer to
the USYRT (maintenance mode only).

•

Bit 5 = indicates that a data bit is present on the output of the USYRT serial data stream
(maintenance mode only).

•

Bit 6 = Signal quality indication from the EIA Modem Interface (see EIA specification).

•

Bit 7 = Signal rate from EIA Modem Interface (see EIA specification).
MAINTENANCE AND PROTOCOL FUNCTIONS

BALU BITS

o
OBUS

"'--------,

r------~

23038 B1
ROM

(SEE D4 OF M8203 PRINT SET)
MK-0900

Figure 3-19 OBUS Register 17
Write Operation:
•

Bit 0 = Mode of line unit - initializes to a I.
I = Character oriented protocol .
o = Bit oriented protocol

•

Bit 1 = Insert error when line unit loop is set in microprocessor CSR; all bits are shifted into
the USYR T when this bit is set to 1.

•

Bit 2 = Read All Parties - used in bit oriented protocol; all parties address (11111111) and
the normal secondary address.

•

Bit 3 = Strip sync character in character oriented protocol after the first two characters.

•

Bit 4 = Secondary address mode for bit oriented protocol. Enables auto detection of the
secondary address and accepts messages with its secondary address or the all parties address
if bit 3 is set.

•

Bit 5 = Idle - Uses the 23038BI ROM, which normally sets Idle in the USYRl (sync
characters must be loaded by the microprocessor). With Idle clear the USYRT will MARK
when underrun occurs.

3-18

,I
\

•

Bits 6 & 7 = Determine the type of error checking being used:
Bits
7 6

Character Oriented
Protocol

Bit Oriented
Protocol

CRC 16

CCITT 16 initialized
to one
CCITT 16 initialized
to zero
Not used
No error checking

Odd vertical parity

1 0
1 1

Even vertical parity.
No error checking

Register 17 initializes to character oriented protocol with CRC 16.
3.2.4 Extended Registers/Indirect Addressing
Indirect addressing is used to address the USYRT directly, thereby bypassing the silos and standard
hardware to run special protocols and variable word lengths. Indirect addressing is accomplished by
setting up address AX in OUT /IBUS register 14, then the data in extended registers 15 and 16.
•

Extended address must be loaded first.

•

For a write operation, set Enable AX and WAX. Data must be loaded in OBUS registers 15
and 16.

•

For a read operation, set Enable AX and RDAX.

When bit 7 of IBUS register 14 is set, the operation is complete.
Figures 3-20 through 3-27 provide the write IBUS/OBUS register bit descriptions and qualifications
for read operations.

3-19

----I 7

I
USYRT

I 51413 I 2

~ECEIV:ER OArA

I
IBUS REGISTER AXO-15
READ ONLY

BIOI RECTIONAL
OATABUS

, , ~I

-I

OP BITS

LU IBUS

(74LS244)

(74LS374)

< 7 :0 > H

(02 OF M8203)
(PRINT SET)
MK-0902

Figure 3-20 AXO-15 Register
Read only:
•

Receiver data is directly from the USYRT.

•

The silo must be disabled (DISSI must be set).

•

Set RDAX and Enable AX.

•

ISUS register 15 is the low byte of the data read from AXO-15 as defined by the extended
address bits.

•

The operation is complete when Ready bit 7 (ISUS register 14) becomes true.

3-20

1 7

1 6

1 5 14131211101

LINE UNIT BITS·

------115114113112111(101-9-1-8-1------IRERRI

USYRT

115

BIT~ ASS;EMB I ROR RAB IREOMIRSOMI
~

DOP

BITS

I
I

IBUS REGISTER AXO-16
READ ONLY

BIDIRECTIONAL
DATA BUS

SILO DISABLED
LU IBUS
(74LS374)

<7:0 >H

D2 OF M8203
PRINT SET
MK-0948

Figure 3-21

AXO-J6 Register

Read only: Receiver status of each character from USYR T.
•

Bit 0 = Received Start of Message (bit oriented protocol). A flag has been received followed
by a non-flag character.

•

Bit 1 = Received End of Message (bit oriented protocol). The closing flag has been received.
The RERR bit is valid if eRe is enabled.

•

Bit 2 = Received Abort (bit oriented protocol). Seven or eight ones have been received.
Invalid character in bit oriented protocol.

•

Bit 3 = Receiver Overrun (data is invalid, the message should be discarded indicating that
the data characters have not been removed fast enough).

•

Bits 4, 5, 6 = Number of bits assembled in the last data character when the closing flag was
received (used in variable length bit oriented protocols).

•

Bit 7 = Receiver Error (Bee match or parity error). Valid with the last character when eRe
is enabled. A one indicates an error in bit oriented protocol.

*USYRT bits < 15:8> are interpreted (seen) by the microprocessor as line unit bits <7:0>.

3-21

----I
USYRT

I4 I3 I2

IBUS/OBUS
REGISTER AX1-15
READ/WRITE

TRANMSIT DATA

t t t t t t tI

I 1 1
----l
7

)

1 3 1 21

BITS

)

BIDIRECTIONAL
DATA BUS

(LOW BYTE)

<7:0> H
BALU

LU IBUS -----I

(74LS374)

(74 LS244)

(74LS244)

< 7: 0 > H

(74LS374)
MK-0956

Figure 3-22

AXl-lS Register

Read/Write:
•

Transmit data loaded into USYRT should only be used with the silos disabled (DISSI) and
only read when the clock is disabled as a maintenance function.

•

With the silos disabled, OUT RDY Bit 4 (ORDY) in IBUS register 11 indicates when the
next register can be loaded into AXl-lS.

•

AXl-IS should not be read unless IN RDY Bit 4 of IBUS register 12 is set.

•

IBUS register 16 is the high byte of the data read from AXl-IS.

3-22

(

I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I

LINE UNIT BITS**

N~T USfD ITXGAITXAB~EOMITSOMI

IBUS/OBUS
REGISTER AX1-16
READ/WRITE

------~1~1~1~1-1-1 1~1-9-1-8-1------ITERRI
.
.

USYRT

I !*

115114
______ "-

1 1 t 1t
12

DP BITS

1 8

~
D
5

(74LS244)

BIDIRECTIONAL

AX16

D
4

DATA BUS
(HI BYTE)

BALU

<7:0 >H

(74LS374)
MK·0909

Figure 3-23

AXl-16 Register

Read/Write (Transmitter Control):
•

Bit 0 = Transmit Start of Message generates sync or flag character and starts CRC calculation.

•

Bit 1 = Transmit End of Message ends CRC generation, transmits CRC 16-bit character
and flag or sync character.

•

Bit 2 = Transmit Abort, (bit oriented protocol) transmits an abort character ifIDLE Bit 5
of OBUS register 17 is cleared, or a flag character if IDLE is set.

•

Bit 3 = Transmit Go Ahead; special for bit oriented protocol (0111111).

•

Bit 7 = Transmitter Underrun (read only). Characters have not been supplied to the transmitter fast enough.

*READ ONLY
**USYRT bits <15:8> = line unit bits <7:0> as seen by the microprocessor

3-23

------1 7

I 4 13 I 2

0
IBUS/OBUS
REGISTER AX2-15
READ/WRITE

I I I SY~C C~ARAC~ER I I I
I t ~ t f t t ttl

USYRT

BIDIRECTIONAL DATA
BUS

17161514131211101
DP BITS
AX15
OBUS REG 14

(SYNC

<7 :0 >)

IBUS REG.14
(74 LS374)

(74LS244)

(74 LS244)

(74LS374)
MK..Q962

Figure 3-24 AX2-15 Register
Read/Write:
•

Sync character in character oriented protocol or secondary address for bit oriented protocol.

I 7 1 6 I 5 1 4 1 3 I 2 I 11 0 I LINE UNIT BITS·
115 114 113 112 1 11 I 10 I 9 I 8 I

I §M~STRIPISECAIIDLE c~c TY~E I
~ ~ ~ l ~ ~ ~ ~ I
I
I
APA

USYRT

IBUS REGISTER AX2-16
READ

",READ ONLY
DATA BUS

DP BITS

AX16
OBUS REG. 17
(74LS244)
MK..Q963

Figure 3-25 AX2-16 Register
Read: (Functions set via OBUS register 17)
•

Bits 2, 1, 0 = CRC/Error Checking

*USYRT bits < 15:8> = line unit bits <7:0> as seen by the microprocessor.

3-24

(

Bits
2 1 0

Character Oriented
Protocol

Bit Oriented Protocol

0 0 0

CCITT 16 initialized
to a one.
CCITT 16 initialized
to a zero.
Not used.

0 0
0
0
1
1
1
1

1
1
0
0
1
1

0
1
0
1
0
1

Not used
CRC 16
Odd parity
Even parity
Not used
No error checking

Not used.
No error checking.

•

Bit 3 = Idle: Determines what will be sent when an underrun occurs or when Transmit
Abort Bit 2 of AX1-16 is set (0 = marks are sent, 1 = flags or syncs are sent in transparent
modes, usually run with CRC disabled).

•

Bit 4 = Secondary address enable for bit oriented protocol.

•

Bit 5 = Strip sync characters for character oriented protocols.

•

Bit 6 = 1 for character oriented protocol
= 0 for bit oriented protocols.

•

Bit 7 = Receive all parties (SEC address 377).

BALU

(7 I I I I I I
6

USYRT
REG

14221 XYZ 1

1 0

~~~ 1V.3511NT 1 ~~ 1 0 ITESTI

)

IBUS/OBUS
REGISTER AX3-15
READ/WRITE

(;
MODEM INTERFACE
SELECTION (07 OF M8203 PRINT SET)
MK·0923

Figure 3-26 AX3-15 Register

Read/Write:
AX3-15 is a test register for the Modem Interface and does not affect the USYRT. This register is used
only for maintenance purposes. When addressing this register do not set WAX or RDAX. It is used to:
1.

Read which interface is selected, or

3-25

Select the interface when test connectors are used.

•

Bit 0 = Select Interface Bit; when a I, the Modem Interface is selected by other bits in
the register (via 74LS157-D7 of the M8203 Print Set). Used when H3254 and H3255
test connectors are installed.

•

Bit 1 = Reserved.

•

Bit 2 = Enables CRC 32 chip if installed (E124).t

•

Bit 3 = Integral Modem has been selected.*

•

Bit 4 = V.35 Interface selected by appropriate cable if bit 0 is not set (BC05Z cable is
connected to Jl connector) or if bits 0 and 4 are set (diagnostic selection).

•

Bit 5 = Enables CRC 32 BCC match,-if installed. t

•

Bit 6 = EIA single-ended (unbalanced) interface (includes RS-232-C and RS-423-A;
default when bit 0 is not set; true when bits 0 and 6 are set).

•

Bit 7 = RS-422-A Differential (balanced) Interface - must be switch selected in normal mode.

NOTE
Selects the maintenance function when bit 0 is set
and read back true for the function selected.
*Bit 3 - Write when bit 0 is set, selects the Integral Modem. Does not select speed or filter for the
Integral Modem. The proper cable or test connector must be used and correct data rate must be
selected by switch pack number E39, switches 8, 9 and 10.
t All bits are active low except bits 2 and 5.

3-26

I 0 I
115 114 1 13 112 111 110 1 9
1 TX fH
USYRT
*STANDARD
2652
CHIP

I 8 I

LE~GTH I~~ I;:E IREC fH LE~GTH I

Itt t f*
115114113

IBUS/OBUS
REGISTER AX3-16
READ/WRITE

ttl

112111110 1 9

LINE UNIT BITS**

USYRT

Figure 3-27

MK-0960

AX3-16 Register

Read/Write:
AX3-16 is for special protocols handled by the USYRT (directly address the USYRT). When the
module is initialized, zero is loaded into the register.
•

Bits 2, 1, 0 = Receiver character length control bits.
001 through 111 are the number of bits for special protocols.
000 is for standard eight-bit character.

•

Bit 3 = Receiver character length enable.**

•

Bit 4 = Transmitter character length enable.**

•

Bits 7, 6, 5 = Transmitter character length control bits.
001 through 111 are the number of characters for special protocols.
000 is for standard eight-bit character.

USYRT bits < 15:8> = line unit bits <7:0> as seen by the microprocessor.

3.3 SILOS
The silos are used to buffer transmit and receive data of up to 64 bytes plus 4 status bits per byte. This
feature provides time for the microprocessor and the UNIBUS to handle characters at speeds above
56K bps and decrease the possibility of overruns and underruns. The silos are 12 bits wide with eight
data bits and four status bits. Each silo is composed of three 3341 sixty-four by four bit first in first out
(FIFO) chips that are used to interface the USYRT and the microprocessor.
3.3.1 Transmit Silo
Data and status should not be loaded unless outready (ORDY) bit 4 of register II is high. Register II,
transmit status bits 0-3, must be loaded first followed by loading data bits into register 10. The loading
of register 10 will shift the four status bits from register II followed by the eight data bits from register
10, into the Transmit Silo. Termination of the shift cycle clears register II, bits 0-3 and all of register
10. ORDY will set when the silo is ready for the next character. (See Figure 3-28.)
**With Signetics 2652 or equivalent.

3-27

DIP<15:12>H
AT GRD
74LS174

FIFO INPUT STAGE

.,..
4
OUT REG
11

= 3 - 3341'5

6
7

5
6
7
OUT REG
10

64 WORD X 4 BIT
MAIN REGISTER

FIFO OUTPUT STAGE
10
11
12
13

74 LS244

10
11
12
13

5
6
7

74LS273

INPUT READY

SHIFT IN

DIP
<15:8>H
TO USYRT
VIA
74LS241

10
11
12
13
74 LS244

w
I

SILO

FROM J1 P
VIA CONN
J3 AND 74S240

·15

DIP
< 7: 0> H

SHIFT OUT
INPUT
CONTROL
LOGIC

MAIN REGISTER
CONTROL LOGIC

OUTPUT
CONTROL
LOGIC
14

I
I
L

OUTPUT READY

- --- --- -- ----9
MASTER RESET
OCPL

Figure 3-28

REFERENCE
03 OF M8203
PRINT SET
MK-0943

Transmit Silo

The output of the silo is shifted into the USYRT by the sequencer when the USYRT is looking for the
next character and both Output Ready and Shift Out are asserted. Transfer Enable (TXENA) activates
the transmit section of the USYRT when the silos are disabled. TXENA keeps Request To Send set
when the silos are enabled. If the transmit section of the USYRT is not disabled between message
transmissions, the CRC register is not cleared and causes a CRC error at the receiver. Control logic for
the Transmit Enable signal of the USYRT automatically clears when (I), EOM is set with abutted
messages and (2), the silos are enabled.
The USYRT generates Transmitter Buffer Empty (TBMTY) when it is ready for the next character.
TBMTY is routed through buffer circuitry (74L244), whose output TXBMT H is ANOed with Out
Composite Ready (OCOR H) from the silos generating the load signal (Load H) to the sequencer.
The sequencer uses the load signal to generate the timing for transferring a character from the silo to
the USYRT. Completion of the sequencer cycle effectively shifts the characters out of the silo (the
sequencer is defined in Section 3.4).

3.3.2 Receive Silo
The Receive Silo is loaded from the USYRT with timing provided by the sequencer. USYRT generates
a data ready signal when the next character is ready to be transferred into the silo. If the silo is full and
the next character cannot be loaded, a receive overrun may occur. (See Figure 3-29.)
If an overrun occurs, the next time a character is loaded into the silo, the status flag is loaded for a
receiver overrun. The overrun bit (IBUS register 12, bit 3) remains set until the receiver is cleared. The
sequencer looks for Input Ready from the silo and Data Ready from the USYRT (See Figure 3-30) to
generate the timing sequence to load the silo (if the silo is full, it will not return Input Ready). The
status bits (bits 11-8) are routed in IBUS register 12 and read, The data is taken from the silo when a
character (bits 7-0) is read in IBUS register 10 where the data is buffered and the silo is shifted out. If
the valid data flag register 12 bit 4 (Input Ready) is not set, IBUS registers 10 and 12 should not be
read.

3.4 SEQUENCER
The Sequencer controls all data in and out of the USYRT. Two IK by 4 bit ROMs determine the
priority of the tasks performed (06 of the M8203 Print Set). Timing is generated by a 20 M Hz crystal
to generate 100 ns increments (07 of the M8203 Print Set). The ROMs can be set up to mask out any
operation or to create different versions of the line unit for the utilization of special functions. This
flexibility allows the line unit to create several versions, e.g., depopulating the module with special
protocol functions. A 20-pin space socket is included on the module for special function chips such as
the CRC 32 chip. This section discusses only the standard set of ROMs used with the M8203 Line
Unit. Other options will require a "Y" version and will be described in the documentation relevent to
the option implemented.
The Sequencer controls all clear functions on the module with the ability to load the USYRT status
registers following execution of a clear and before any other operations are performed. The line unit
should not be addressed until two microseconds after the clear is initiated to allow the line unit time to
initialize. The basic clear operation is controlled by the ROMs after all registers and the USYRT have
been cleared. The ROMs clear the transmit and receive circuits and then load the USYRT status
registers to a default value specified by the 23038B 1 ROM. The line unit is then ready to handle status
and data.
The 20 MHz crystal that provides the timing to the sequencer is also used by the data rate generator. A
main counter is preset at the beginning of a task and cannot be interrupted. The task continues until
the counter overflows. The overflow state is held until a new task is initiated. This is accomplished by
clocking the two function registers every 100 ns until a task is assigned. Ifmore than one task is ready,
the FI ROMs will execute the Task with the highest priority. The output of the function registers
address the two ROMs that control the sequencer.

3-29

(DP< 15: 8 »
USYRT

j
DIP
<15:8>

74LS
244

74LS
244
DOP 9, 10, 11, 15

9,10,11,15
STATUS
DATA

W
I

DIP

< 7: 0 >

74LS
244

RECEIVE
SILO
(SEE FIGURE 3-1)
3-3341's

74LS
244
DOP

< 7: 0 >

74 LS374's

SILO

< 7: 0 >

IREG
10
DATA

LUIBUS
< 7: 0 >
CONN
J3

---- --

STATUS
BITS
OVERRUN
ABORT
END BLK
BCC

IREG
12
STATUS

MASTER RESET
ICP L
' - - - - . / USYRT
(DP < 7: 0 »

REFERENCE
D5 OF M8203
PRINT SET
MK-0945

Figure 3-29

Receive Silo

(OUT REG 14) DISSI L

SHIFT IN (SILO)

+3V
LD SILO
(SEQUENCER)
DATA
ROY
(USYRT)

READ H (SEQUENCER)

ICP L
ICIR H

VALID
DATA
FLAG

MASTER RESET (SILO)

INPUT
READY
(SILO)

REFERENCE
05 OF M8203
PRINT SET
MK-0961

Figure 3-30

Load Silo

Sequencer output is a 23042Bl ROM used to generate the clocks for moving data. ROM output is
clocked every 100 ns via the master clock.
Priority is set in the ROMs in the basic M8203 module to:
1.

Initialize - Set the character length for both the transmitter and receiver to eight bits.

I/O Clear - Input/Output clear (clears the silos and receive/transmit logic).

Load Mode - Sets the mode to character oriented protocol with CRC 16 selected on INIT
and parameter adjustment when OBUS register 17 is loaded.

Read - Read data and status from the USYRT.

Load EOM - Load the End of Message into the transmit status register.

Load Data - Load data and transmit status into the USYRT.

Extended Registers Read the USYRT - Read the USYRT and load the data into the extended registers.

Extended Registers Write Data - Write data from the extended registers into the USYRT.

3-31

The first three are done automatically on a Master Clear or INIT to the microprocessor and line unit.
The functions are executed in the priority shown following the clear sequence of the line unit. The
priority structure in ROM can be changed to accommodate the special variations to be implemented.
3.5 DATA RATE GENERATOR
The data rates are generated via two counters. The first counter is a Schottky Binary Counter (93S 16)
that is loaded on overflow and clocked from the 20 MHz crystal that provides the master clock to the
M8203 module. The 1M bps rate does not use the counter (is common to the Master clock). The 500K
bps and 250K bps rates use the counter as a binary divider. The 56K (55.5556K) data rate uses an
additional flip-flop (74LS74) to create a divide by 18 function. The second counter (74LSI61) is a pure
binary counter which generates four clock speeds directly: 19.2K bps, 9.6K bps, 4.8K bps, and 2.4K
bps rates. The speeds below 56K bps are generated by the overflow to the first counter for a divide by
26 and a flip-flop (74LS74) which provides the clock input to the second counter. (See Figure 3-31.)
The outputs go to an eight-to-one multiplexer (74S 151) whose select inputs are controlled by a switch
(See Figure 3-36). The multiplexer output (20X CLK) is input to a divide by 10 counter (74LS161 shift
register for the 20X CLK). The Integral Modem 74S 112 flip-flop is the last divider for the data rate or
NULL clock.
3.6 USYRT
The Universal Synchronous Receiver/Transmitter (USYR T) functions as a Large Scale Integration
(LSI) subsystem for synchronous communications. All data to the line unit must go through the
USYRT. The USYR T provides the necessary logic support via program parameter registers for basic
protocol handling and error detection. Protocol handling conforms to standards but is slightly different in each version. The 2652 chip, version 01, is implemented in the M8203. Replacement of the
USYRT changes about half of the logic on the M8203 in one chip. In many cases, this chip or the
timing going into this chip will be a problem area.
Typical start and receive sequences in bit and character oriented protocols are provided in Figures 3-32
through 3-35.
Troubleshooting of the M8203 module should be done in both direct and indirect modes before determining where the problem area exists. Refer to A-PS-2112517-0-0 Purchase Specification for detailed
information on the USYRT.
Timing diagrams, terminal connections and an internal bit map are provided in Appendix C, Integrated Circuit Descriptions.
3.7 MODEM INTERFACE
The modem contains several interfaces as described below.
•

EIA levels are based on:
EIA RS-449 specifications that use the 12 connector for plugging in the BC55C cable
for RS-423-A/CCITT V.1O (ISO 4902)/X.26 and Federal Standards 1030/1031,
The BC55B cable for RS-422-A/CCITT V.11 (ISO 4902)/X.27 and Federal Standards
1030/1031, and
The BC55C cable for RS-232-C/CCITT V.28 (ISO 2110).

•

The 11 connector can be used for plugging in the BC05Z cable for the CCITT V.35 (ISO
2593) interface or the BC55A-10 cable for the Integral Modem interface.

3-32

+5-vvv----,-----~

20 MHZ
CRYSTAL

~>-------...__-I-___4n11

74S112

MASTER ClK

50ns

100ns
200ns

TO 74S151
(SEE FIGURE 3-36)

900ns
'-----I~ 74lS74

DIVIDE BY
18

x....----o(..JI lD
r - - -.... ClK

74lS161
CNT

DIVIDE BY 26

CONN\..
J3

J BClR l
L..-.-RTS ClK

+3V-~

ClR L

REFERENCE
D7 OF M9203
PRINT SET

+3V
MK-0920

Figure 3-31

Data Rate Generator

3-33

MASTER RESET
TRANSMITTER ENABLE:
CONTROLS OPERATION OF
THE TRANSMIT DATA
PATH, IF THE SILOS
ARE DISABLED. SILOS
ARE ENABLED AUTOMATICALLY VIA
SILO CONTROLS.

SET UP PARAMETERS

""r------------.
TXENA .....~-

TRANSMIT START OF
MESSAGE

TSOM .............-

TRANSMITTER BUFFER
EMPTY

""INCREMENT FLAG COUNT

ERROR TYPE SELECTION MUST BE SET
TSOM~O

TRANSMIT
DATA
REGISTER

~.r-----------~----------~
15t BYTE
TXDATA REG .....
f---

/..------~
NO

TXDATA REG 4 - - NEXT BYTE
DATA LENGTH SELECTION MAY BE
DONE AT ANY TIME
MK·0955

Figure 3-32 Typical Start Sequence for the USYRT Bit
Oriented Protocol Transmission Flowchart

3-34

MASTER RESET
CCP + BCP _

1 (CRC)

CHARACTER
ORIENTED

r---------_""

PROTOCOLS

SET UP PARAMETERS

,,~------~------~
TXENA...-1

TRANSMITTER
ENABLE
/'

~------~------~~
TRANSMIT START
TSOM
~1

"
ERROR TYPE IDLE MODE
STRIP SYNC MODE
LOOP MODE
SYNC CHARACTER
THESE MAY BE SELECTED AT
THIS TIME IF DESIRED

OF MESSAGE

INCREMENT SYNC COUNT

TSOM-4--Q

TRANSMIT
DATA REGISTER

TXDATA REG .....1 - - _ 1 st BYTE

TX DATA REG ......~-- NEXT BYTE

MK-0921

Figure 3-33 Typical Start Sequence for the USYR T Character
Oriented Protocol Transmission Flowchart

3-35

MASTER RESET

(

SET PARAMETERS

RXENA.-- 1

/RECEIVER
",ENABLE

SYNC FLAG
RECEIVE

"
/
NO

RECEIVER ACTIVE
READ DATA ACTIVE

READ STATUS FROM DP (DATA PATH)

READ START
OF MESSAGE

READ 1 st BYTE FROM DP (DATA PATH)

READ 1 st BYTE FROM (DATA PATH)

MK-0953

Figure 3-34 Typical Receive Sequence for the USYRT
Bit Oriented Protocol Flowchart

3-36

MASTER RESET

/ CHARACTER OR

SET PARAMETERS
CCP + BCP -4-1

BIT ORIENTED
PROTOCOL

RXENA~1

RECEIVER ENABLE

/
SYNC FLAG
RECEIVE

RECEIVER ACTIVE
READ DATA ACTIVE

READ STATUS FROM DP (DATA PATH)

/
READ START
OF MESSAGE

READ 1 st BYTE FROM DP (DATA PATH)

READ NEXT BYTE FROM DP (DATA PATH
MK-0954

Figure 3-35 Typical Receive Sequence for the USYRT
Character Oriented Protocol Flowchart

3-37

•

The M8203 module will be shipped with two test connectors (H3254 and H3255) that will
turn around the Modem Interface and the Integral Modem signals for test purposes only. (
This allows the logic to select any interface and test it in a loop back mode. The cables are \.
options and must be ordered separately with the test connectors.

•

The Modem Interfaces all have a NULL clock controlled by a counter that is switch selectable from 2400 bps to one Mbps. The speed must be matched to the interfacing level used for
maintenance or null modem speeds. (Refer to Figure 3-36.)

50ns

DO
STB
D1 74S151

100ns

COUNTERS
F1

20X DATA RATE

20X ClK H
(TO DIVIDE X 10)
(COUNTER)

20X elK L
S2

SELECT
S1
SO

REFERENCE
D7 OF
M8203
PRINT SET

E39 SWITCH

ON =0
OFF = 1

E39 SWITCH

INPUTS
SELECT/SWITCH

STROBE

BAUD
RATE

0
0
0
0
0
0
0
0

1 MBPS
500 KBPS
250 KBPS
56 KBPS
19.2 KBPS
9.6 KBPS
4.8 KBPS
2.4 KBPS

S2/10 S1/9 SO/8
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

MK-0933

Figure 3-36

Data Rate Select

3-38

•

The EIA interface accepts three cables but cannot distinguish one from the others. The
interface requires that switch E39, position 7, be set to select either the single-ended (unbalanced) or differential balanced drivers. Switch position 7 "ON" selects the differential interface. The program can read the switch setting, without opening the cabinet to check the
module, to determine if the setting is correct. Differential interface is only used with the
BC55B cable and the EIA RS-422-A interface level.

•

The Modem Interface receivers (08 of M8203 Print Set) are fail-safe and can operate with
either single-ended or differential interfaces. The receivers also have space for inserting terminating resistors to accommodate differential signals. These resistors are built into the cable
to allow swapp~ng of modules without adding components.

•

The V.35 interface is a special interfacing level with balanced termination at both ends of the
line. It is a high speed interface that can operate at up to 250K bps.
Qualifications for using a V.35 Interface:

•

A BC05Z cable with an H3250 test connector must be plugged into the 11 connector on
the M8203 module.

•

Switch E39 position 5 ON selects the correct interface chips for V.35.

•

The interface level can be read by the program through the extended registers.

•

The cable or test connector must be removed from connector 12.

3.8 INTEGRAL MODEM SPECIFICATIONS
The Integral Modem may be used for a point-to-point multi-point unit, master/slave, or a multimaster
system and:
•

Is compatible with previous versions of the Integral Modem such as the OMCll-M(X) and
can be connected using triax/twinax cable. Oata and sync sequence are compatible.

•

Is connected through a Berg connector and the interlock selects the Integral Modem using a
BC55A-I0 interlock cable.

•

Runs at four switch selectable speeds (56K bps, 250K bps, 500K bps, and 1M bps).

•

Is transformer coupled to a 70 to 150 ohm line which must be a twinax or triax cable for high
common mode rejection and common mode voltages of up to 500 volts.

•

Requires two intersystem cables for full-duplex and one intersystem cable for half-duplex operation.

•

The line unit must be terminated with a 75 ohm line or a line matching resistor on each end.
Other impedance lines can be used if properly terminated, e.g., the 150 ohm OECdataway.

•

The line must be terminated at both ends with the characteristic impedance.

3-39

3.8.1 Receiver
The received data enters the modem through an isolation transformer whose output is directed to a /
differential amplifier to eliminate common mode noise. The amplifier's second stage uses an active "
Butterworth filter with an added passive filter which provides high and low-cut off. The filter complementary outputs are input to a comparator which detects zero crossover. Positive and negative
transitions from the comparator clock the UP and DOWN flip-flops. All clocking is done at a clock
rate 20 times the bps rate and the UP and DOWN flip-flops latch until cleared by the TRANS flipflop. (Refer to Figure 3-37 for the block diagram and Figures 3-38 and 3-39 for timing considerations.)

FF's

DIFFERENTIAL
AMPLIFIER
REC
DATA
IN

ZERO
DETECT
CROSSOVER

ISOLATION
TRANSFORMER

TRANS

COMPARITOR
150 MV MIN.
25V PEAK-TOPEAK

QUAD D TYPE
FFs

REC
CNTR

ClK
CO

SYNC
UP
&
DATA

D1
ClR l
20X ClK H

RI DATA

I CARRIER

1/10 T
FF

REFERENCE
DIO OF
M8203
PRINT SET
MK-0991

Figure 3-37

Modem Receiver Block Diagram

3-40

INTEGRAL MODEM RECEIVER TIMING
START UP

LINE

75%FF
RIDATA

LSI

L-

RICLK

.....
CARRIER
MK-0966

Figure 3-38

Modem Receiver Timing Diagram - Start-Up

INTEGRAL MODEM RECEIVER TIMING
NORMAL DATA

LINE

UP
3603 OUT
DOWN

TRANS FF

J
1
~

.Jl

_____ ___________

___________

_____ ______

20X CLK

w
I

CNTR LD

CNTR
OVERFLOW

____________ ____________ ____________ ____________ ____

75%FF

--,

3/4T

~n~

-.l

RIDATA

RICLK

~n~

DATA TO USYRT

..J

RICLK POSITIVE TRANSITION CLKS DATA INTO THE USYRT
MK-0964

Figure 3-39

Modem Receiver Timing Diagram - Normal Data

When either the UP or DOWN flip-flop is set, the next clock pulse loads the transitions (TRANS) flipflop which then clears the UP or DOWN flip-flop, and holds it clear for one clock time. The clock
input to the TRANS flip-flop and REC CNTR is 20 times the data rate clock time.
The next clock loads the 1/10 time flip-flop which in turn clears the TRANS flip-flop. The output of
the 1/10 time flip-flop controls the load (LD) input to the receive counter (REC CNTR).
When the 3/4 time flip-flop is set, and the time between transitions is less than 16 clock times, the
DATA I flip-flop (SYNC UP & DATA chip, D3 input) is clocked to zero. If the transition time at the
3/4 time flip-flop is greater than 16 clock times, the DATA I flip-flop is clocked to a one. The minimum time between transitions is .05 to .10 bit times, which is accomplished by the TRANS flip-flop
clearing the UP and DOWN flip flops.
The REC CNTR is clocked at half clock time (or inverted 20X clock). The counter is loaded if the 1/10
time flip-flop is set and 16 clocks have occurred since the last load. The count control is true except in
an overflow condition or when operating in half-duplex mode with the transmitter active.
The overflow flip-flop clears the CARRIER SYNC UP & DATA register until the next one followed
by two zeros sequence. Overflow occurs when no transition has occurred in one and one-half bit times.
The SYNC UP & DATA register is clocked at three quarter time and loads DATA I into the first flipflop of the register. The next three quarter time clock causes DATA I to be ANDed with the output of
the first flip-flop, provided that this output is a zero, and sets the second flip-flop. The next clock sets
the third flip-flop from an ORed input that latches this flip-flop once it is set. The third flip-flop is
cleared at one and one-half bit times (overflow) which then clears the SYNC UP & DATA register.
•

The low output of the first flip-flop presents data.

•

The output of the third flip-flop presents an I CARRIER signal which enables the receiver
clock for serial data bits (first data character) to be transferred to the USYRT and indicates
the receiver is in SYNC with the transmitter.

Receiver specifications are shown below:
•

Rec,eiver sensitivity
150 MV P-P
200MVP-P·
150 MV P-P

•

with 12% distortion on the line at 250K bps
to 1M bps
with 15% distortion on the line at 250K bps
to 1M bps
with 20% distortion on the line at 56K bps

Protection
500 volts dc common mode voltage
15 volts P-P normal mode voltage

•

Line loading Power on or off
2500 ohms at 1M bps
6000 ohms at 500K bps
10000 ohms at 250K bps
10000 ohms at 56K bps

3-43

NOTE
Jumpers W14 and W15 can be installed to reduce
the bandwidth of the Integral Modem receiver filter
for 56K bps operation only. These jumpers usually
are not installed.
3.8.2 Transmitter
The transmitter creates a simulated sync wave by step reproduction. A crystal controlled oscillator
(with no adjustments) supplies the transmitter clocking signal (XMIT eLK). The data rate select clock
(lOX eLK or 5X eLK) and the data to be transmitted are gated through clock phase data ANDing
circuitry to provide the clocking signal to the SINE GEN. Sine generator output goes to a bipolar line

driver that generates an ac signal with zero crossover points. (Refer to Figure 3-40 for the block diagram
and Figures 3-41 and 3-42 for timing considerations.)
Line driver output is connected to the protection transformer through two VMOS transistors. The
VMOS transistors are switched off with the beginning of the start up sequence and the end of the shut
down sequence. The + 5V low circuit turns off the VMOS transistors on low logic power to keep the
line from generating noise or from loading the line. During power-up this circuit keeps the modem in
the disabled state for several milliseconds to prevent the transmission of nonsense characters that
would interfere with transmission in progress on a multipoint line~
The transmitter is disabled or tristated when line units are not transferring data. The transmitter does
not load the line when power is off.
Transmitter specifications are shown below:
•

Transmitter drive
5.6 volts P-P minimum into a 30 ohm load

•

Protection
500 volts de common mode on the line
30 volts normal mode on the line when the transmitter is disabled
Will withstand a shorted line without damage to the circuitry

•

Transmitter loading disabled or power off
3000 ohms at 1M bps
5000 ohms at 500K bps
10000 ohms at 250K bps
15000 ohms at 56K bps

NOTE
Signals above 200 volt microseconds saturate the
transformers. This causes noise problems on the line
when the transformers collapse as well as possible
errors in the recover circuit.

3-44

(

XMIT ClK

USYRT
ClK
FF

NUll
ClK

IT ClK
RTS
DELAY

ICS
TX DATA

RTS
DELAY

ITClK

SINE
GEN

10X ClK H

ROTS ClK

5X
ClK

DATA
AND

ClK

BI POLAR
LINE
DRIVER
VN 35 AK

n
XFORMER
CABLE H
+5V lOW &
ENABLE

+5V - - - - - - '

DATA
OUT

u
REFERENCE
DIO OF
MB203
PRINT SET
MK-0992

Figure 3-40 Modem Transmitter Block Diagram

3-45

TRANSMITTER TIMING
START UP SEQUENCE
RTS

QE
RTS DELAY

ICS

~----~SS~----------------------------------------

_---I

---------4S5~------~
--------~SS~--------~

ITClK
T DATA

!.f
~

--------~5~~----------~

FOllOWSUSYRTDATA

ENABLE
OUTPUT

FOllOWS T DATA
ANALOG
OUTPUT

RTS TO ICS TIME IS
116-145 NS DEPENDING
ON THE PHASE RELATION
OF RTS ClK + ITClK

Figure 3-41

MK-0965

Modem Transmitter Timing Diagram - Start-Up

TRANSMITTER TIMING
NORMAL DATA
USVRT ClK
(IT ClK)
TDATA

XMIT ClK

5X ClK

lOX ClK

.-J

----1

.j::..

-....l

QC
QD
QE
QF

SUMING
AMP
OUTPUT

MK-0967

Figure 3-42

Modem Transmitter Timing Diagram - Normal Data

CHAPTER 4
SERVICE

4.1 SCOPE
Servicing information for the M8203 module consists of preventive maintenance procedures which are
based on established system preventive maintenance schedules and corrective maintenance via the use
of line unit microdiagnostics. Cable specifications and recommendations are provided in Appendix B,
Recommended Cables/Connectors.
4.2 MAINTENANCE PHILOSOPHY
The M8203 is the Field Service Field Replacable Unit (FRU). Isolation to the module level must be
done through the use of DIGITAL Diagnostics and/or any microdiagnostics that may have been
incorporated in the microprocessor Control Read Only Memory (CROM).
4.2.1 Preventive Maintenance
Preventive maintenance (PM) for the M8203 module is recommended for voltages and connections
during system PM or when problems exist. Keep a record of the initial local link cable characteristics,
particularly the propagation time delay and short circuit line resistance as indicated in this section.
Once the system is operational, record the received signal amplitude at the M8203 (See Figure 4-1).
Repeat this measurement at every scheduled system PM date (should be at least four times a year). If a
deviation of 20 percent is observed in signal amplitude, disconnect both ends of the cable from the
M8203 and measure both open and short circuit resistance of the line (See Figure 4-2).
If a measured open circuit resistance is less than 20 megohms, inspect the cable for contamination of
the dielectric, adverse effects of sharp bends at stress points, elevated temperatures, or aging. If the line
resistance with a shorted end increases above the value measured at installation, inspect the cable
connectors for loose fits, contamination, and excessive tension on the cable.

To locate a defective section, an ohmeter can be used to diagnose an open line or a low impedance
shorted line by checking one section at a time until the faulty section is located. If the cable is not
partitioned into small enough sections, the distance to the fault can be measured by making use of time
domain reflectometry (TDR).
Although TOR cable testers are available from Tektronix and other manufacturers, a pulse generator
and oscilloscope can be used for approximate measurements. Disconnect both ends of the cable, and
drive one end with a 5V peak and a 100 ns wide pulse with a repetition rate below 10 kHz. Measure the
time interval between the leading edge of the driven pulse and the leading edge of the first reflection.
The reflected pulse will be in the 10 mV to IV range. This range is normal for an open line, but inverted
for a shorted line. Figure 4-3 shows typical oscilloscope traces for both cases. The time interval represents the propagation time delay for a round trip from the signal generator to the fault and back. The
distance 0 to the fault in feet (meters) is:

o = T p /2p
where T P is the measured time delay in nanoseconds, and p is the propagation time in nanoseconds per
foot (meter) recorded before the cable was installed.

4-1

THE VOLTAGE CAN BE MEASURED BY RUNNING THE DIAGNOSTIC LOOPING ON TEST #17 ofCZDMS.*
THE PEAK TO PEAK VOLTAGE CAN THEN BE MEASURED WITH A SCOPE ACROSS THE
TERMINATING RESISTORS AT EACH END OF THE CABLE SYSTEM. BOTH THE TRANSMITTED AND
RECEIVED VOLTAGE SHOULD BE RECORDED FOR REFERENCE.

C=
C=

BC55A
PANEL

M8203

BC55A
PANEL

M8203

BC55A

PANEL

(
'"

n ¢
F;]

SCOPE

750H M
TERMI NATING
RESISTORS

M8203

MK-0892

Figure 4-1

Received Signal Measurement

OHMS

~--~------------------------------------------~~JUMPERPIN1
~
UjjTOPIN2
MK-0893

Figure 4-2

Open and Short Circuit Resistance

4-2

f- 2V
I-I-i'"

I-lI--

500NS

I-

--------TP--------

SHORTED LINE

OPEN LINE
MK·0906

Figure 4-3

Signal Reflections from a Line Fault

4.2.2 Corrective Maintenance
Standard test equipment may be used during corrective maintenance (CM). M8203 Line Unit microdiagnostics are provided in Appendix A of this document. The line unit microdiagnostic tests are run
following completion of the microprocessor microdiagnostics.
NOTE
Modem status can be checked quickly by observing
LEDs mounted on the board.

DIO

Dll
DI2
Dl3
DI4
DI5

Signal Quality
Carrier
Receiver Data
Transmit Data
Request to Send
Been Polled

Not used with the Integral Modem
Indicates receiver is in sync

From microprocessor indicating that the slave unit has been polled.
This LED may be used differently depending on the option selected.
For example, in the DMRII option, it is referred to as the heartbeat
LED. Refer to specific options manual for detailed use of this LED.

4-3

APPENDIX A
MICRODIAGNOSTIC TESTS

A.I INTRODUCTION
The M8203 Line Unit microdiagnostic tests have been implemented in the M8207-Y A and RA modules. Developers using other versions of the M8207 Microprocessor (or similar microprocessor) should
include this microprogram with the microcoded diagnostics they generate for their application.
A.2 HARDWARE REQUIREMENTS
The following hardware is required to run the diagnostics:
•

Central Processing Unit (CPU)

•

M8207 Microprocessor

•

M8203 Line Unit

A.3 INTERNAL MICRO DIAGNOSTICS
Internal microdiagnostics need no supporting software; they are written in KDA Assembler format that
runs on initialization within the Microprocessor subsystem. These diagnostics are Go/No Go types and
are specifically developed to test the M8203 depending on the application. The example shown on the
following pages is provided as a typical routine, but not necessarily the only possibility. Developers can
use this example to create different variations of microdiagnostics to suit special needs. Errors are isolated to the module level. When an error is detected, the microcode attempts to insert an error number
in BSEL 4, and enters an indefinite loop. CPU software may visually inspect the RUN bit at the end of
the test. The current test number is entered in BSEL 6.
NOTE
Some options may use registers other than BSEL 4
to indicate microdiagnostic test results.
A.4 LINE UNIT TESTS
Line unit microdiagnostic tests are run when the microdiagnostic tests are completed on the M8207
Microprocessor. A brief message is sent through the line unit. Observe and ensure that the message
returns correctly. Also observe the block check character (BCC) bit and cyclic redundancy check
character (CRC) 16 word.

A-I

In the following tests, CERROR is a macro that when expanded generates an error number (current
error number), inputs this number into BSEL 4, and increments the error number to identify the next (
error.
\
EXAMPLE:

EXPANSION OF

I CERROR I

.............

BWRITE
OUT

IMM#
B R,SE LB,OBSE L4
MK·0907

DLUT:

BRWRTE IMM,264
OUT

;INDICATE THAT YOU'RE IN LINE UNIT
;TEST

BR,SELB,OBSEL6
;PICK UP CONSTANTS

BRWRTE IMM,40
OUT
BR,SELB,OXREG2

;SET LOOP BACK.

;NOW LOAD UP SILO
DLUTO:

1$:

2$:

BRWRTE
OUT
BRWRTE
OUT
BRWRTE
OUT
BRWRTE
OUT
BRWRTE
BR7
CERROR

IMM,51
BR,SELB,OXREG7
IMM,2
BR,SELB,OXREG4
IMM,226
BR,SELB,OXREG5
IMM,16
BR,SELB,OXREG4
IBUS,XREG4
2$

;SET CRC16,IDLE,STRIP" AND DDCMP
;YOU ARE GOING TO SET
;THE RECEIVER SYNC CHAR AT 226.
;WAIT TILL READY.
;ERROR-DID NOT BECOME READY,
;ERROR#61

ALWAYS 1$
BRWRTE IMM,O
BR,SELB,OXREG4
OUT

;CLEAR EXTENDED REG ENABLE

DSHAME:
NODST
NODST

IMM,O,LDMAR
IMM,O,LDMAR

MEMINC
MEMINC
MEMINC
MEMINC
MEMINC
MEMINC
MEMINC
MEMINC
M-EMINC
MEMINC
MEMINC

IMM,1
IMM,226
IMM,1
IMM,226
IMM,O
IMM,41
IMM,O
IMM,125
IMM,O
IMM,252
IMM,O

;NOW LOAD ADDR. 0
;PUTALL THE
;CHARACTERS THAT YOU
;WANTTO SEND IN MEMORY.
;1STSYNC
;2NDSYNC
;1STCHAR.
;2NDCHAR.
;3RDCHAR.

A-2

MEMINC
MEMINC
MEMINC
MEMINC
MEMINC
MEMINC
MEMINC
MEMINC
MEMINC
NODST

IMM,377
IMM,2
IMM,O
IMM,2
IMM,O
IMM,2
IMM,O
IMM,2
IMM,O
IMM,O,LDMAR

;4THCHAR.
;SETSEOM
;2NDEOM
;3RDEOM
;4TH EOM.
;LOAD ADDR. 0

BRWRTE IMM,lO.
2$:

3$:

;NUMBER OF CHARACTER STORED MINUS
;ONE.

SP
CERROR

BR,SELB,SP6

BRWRTE
BR4
ALWAYS
BRWRTE
OUT
BRWRTE
OUT

IBUS,XREGI
3$
2$
MEMI,SELB
BR,SELB,OXREG 1
MEMI,SELB
BR.SELB,OXREGO

;OUTPUT FAILED TO BECOME
;READY IF FAILS HERE, ERROR #62
;CHECK FOR SILO READY.

SPBR
BR,DECA,SP6
Z
4$
ALWAYS 2$

;GETDATA FOROXREGI
;GETCHAR.
;DONE ENOUGH?
;DONE ENOUGH

4$:
;SILO IS NOW LOADED.

BRWRTE IMM,256

DLUTL:

BR"SELB,SPO

SPBR
Z
ALWAYS

BR,DECA,SPO
DLUT2
DLUTL

ALWAYS

DLUT2

;AFTER SILO IS LOADED IT TAKES
;3 CLOCK CYCLES TO ACTIVATE, THEN
;8 CYCLES TO OUTPUT 1ST SYNC CHAR
;AS 1ST SYNC CHAR IS OUTPUTTED
;THE NEXT ONE IS BEING LOADED INTO
;THE USYRT (DOUBLE BUFFERED) 1ST
;REALCHAR
;ISN'T REALIZED (INPUT RDY-I) UNTIL
;APP: 46 CLOCK CYCLES AFTER LOADED
;APP: 1.9 MILLISEC

DLUT2:
CERROR
CALLSB

SPO,DINRDY

;ERROR #63 IF NOT READY FOR FIRST
;CHARACTER
;WAIT FOR READY

IBUS,XREGO,SPI

;READ 1ST CHAR FROM SILO

A-3

BRWRTE
NODST
Z
CERROR
ALWAYS
DLUT20:

CERROR
CALLSB
SP
BRWRTE
NODST
Z
CERROR

ALWAYS
DLUT2A: CERROR
CALLSB
CERROR
SPBR
BRO
DLUT2B:
SP
BRWRTE
NODST
Z
CERROR

IMM,41
BR,SUBOC,SPI
DLUT20
DLUTER
SPO,DINRDY
IBUS,XREGO,SPI
IMM,125
BR,SUBOC"SPI
DLUT2A
DLUTER
SPO,DINRDY
IBUS,XREG2,SP2
DLUTER
IBUS,XREGO,SPI
IMM,252
BR,SUBOC,SPI
DLUT2C

ALWAYS DLUTER
DLUT2C: CERROR
CALLSB
BRWRTE
BRO
CERROR
ALWAYS
DLUT3:

SPO,DINRDY
SELB,XREG2
DLUT3
DLUTER

SP
IBUS,XREGO,SPI
Z
DLUT4
CERROR
ALWAYS DLUTER

DLUT4:

CERROR
BRWRTE
SP
CALLSB
SP
BRWRTE
NODST
Z
CERROR
ALWAYS

;IF 1ST CHAR=O THEN IT WILL BE 377
;BR IFOK
;ERROR #64 IF FIRST CHAR DATA BAD
;ELSE GO TO ERROR
;W AITING FOR 2ND CHAR, ERROR #65
;WAIT FOR READY
;READ SECOND CHAR FROM SILO
;SHOULD BE BACK = 125
;DO ONE'S COMP SUB = 377 EQUAL
;BRIFOK
;ERROR #66 IF SECOND CHARACTER DATA
;ERROR
;ELSE GO TO ERROR
;W AITING FOR 3RD CHAR, ERROR #67
;W AIT FOR RDY
;ERROR #10 IF BCC DATA ERROR
;LOOK AT BCC BIT, SIB CLEAR
;IF SET GO TO ERROR
;READ THIRD CHAR FROM SILO
;S/B A 252
;DO ONE'S COMPSUB = 377 IF EQUAL
;BRIFOK
;ERROR #70 IF THIRD CHARACTER DATA
;ERROR
;ELSE GO TO ERROR
;WAITING FOR 4TH CHAR, ERROR #71
;WAIT FOR CHAR
;READREG 12
;BIT 0 SIB SET (BCC BIT)
;ERROR #72 IF BCC BIT NOT CLEAR
;IFNOT, ERROR
;READ 4TH CHAR
;IF 377 EXIT
;ERROR #73 IF FOURTH CHAR DATA
;ERROR
;ELSE REPORT ERROR
;WAITING FOR 1ST CRC CHAR,
;ERROR#74

IMM,377
BR,SELB,SP7
SPO,DINRDY
IBUS,XREGO,SPI
IMM,44
BR,SUBOC,SPI
DLUT5

;INDICATE PAGE 2 RETURNS.
;W AIT FOR CHAR
;READY 1ST CRC CHAR
;S/B 44
;COMPARE IF EQUAL, RESULTS =377
;ERROR #75 IF FIRST CRC CHAR BAD
;IST CRC CHAR WRONG!

DLUTER

A-4

(
\.

DLUT5:

CERROR
CALLSB
SP
BRWRTE
NODST
Z
CERROR
ALWAYS

;W AITING FOR 2ND CRC CHAR,
;ERROR#76
;W AIT FOR NEXT CHAR
;READ LAST CRC CHAR
;SjB 314
;COMPARE IF EQUAL, RESULTS = 377
;IF=,EXIT
;2ND CRC CHAR WRONG, ERROR #77
;ELSE, ERROR

SPO,DINRDY
IBUS,XREGO,SPI
IMM,314
BR,SUBOC,SPI
DLUTE
DLUTER

DLUTE:
BRWRTE IMM,200
OUT BR,SELB,OXREG 1

;NOW CLEAR XMITTER AND RECEIVER
;FIRST CLEAR THE XMITTER.
;THIS WILL RESULT IN THE
;UNUSEABILITY OF THE XMITTER FOR
;8 MICRO-SECONDS

OUT

;NEXT CLEAR THE RECEIVER.
;NOW THE LINE UNIT IS IN THE STATE IT
;W AS IN BEFORE YOU
;CAMETOIT.

BR,SELB,OXREG2

DLUTER: ALWAYS DIADON
DINRDY-

;END OF TESTS GO TO DMP CODE

ROUTINE USED BY LINE UNIT
TEST TO WAIT FOR "RDY"
PROGRAM COULD HANG HERE

DINRDY:
1$:
SPBR
IBUS,XREG2,SP2
BR4
DINEX
ALWAYS 1$
DINEX:
DINEXO: RTNSUB

SPO,P2

DIADON: BWRITE
OUT

IMM,305
BR,SELB,OBSEL6

;CODE SPECIFYING COMPLETION OF
;INTERNAL MICRO-DIAGNOSTICS

MICRODIAGNOSTICS END, USER INIT CODE STARTS

A-5

APPENDIX B
RECOMMENDED CABLES/CONNECTORS

B.l SCOPE
Twinax and Triax cable specifications are provided in this appendix. The customer must purchase
cables that adhere to the specifications presented. Cabling and wiring practices and associated connectors necessary for successful installation of the M8203 are discussed in detail.
B.2 CABLING RECOMMENDATIONS
The line unit is set up for use with the seven standard cables indicated in Table 1-1. DIG IT AL does not
sell cables of over 100 feet for use with Integral Modem Line Units. DIGITAL sells (1), the BC55N 30 meter (98 ft) cable for all speeds in point-to-point operation or 56K bps in multipoint operation and
(2), the BC55M - 30 meter (98 ft) cable for 250K bps, 500K bps, and 1M bps in multipoint operation.
NOTE
The cable should be provided and installed by the
customer.
B.3 CABLE SPECIFICATIONS
The M8203 runs on multidrop or point-to-point lines from 75 to 150 ohms. All terminations of the line
must be done in the cabling of the system.
Point-to-point lines should be terminated at the receiver end while multidrop lines should be terminated at both ends of the line.
There is no interlock between the cable and the line unit for half-duplex operation. A bit must be set in
the line unit to inform the microcode to select the half-duplex mode.
The total loading effect of the units on the line for a multidrop system should not be lower than the
impedance on the line. Both the driver and receiver on the M8203 can withstand a 30 decibel (dB) drop
on the line, with restrictions of 20% maximum distortion.
Refer to Table B-1, Belden Twinax Cable Specifications and Table B-2, Belden Triax Cable Specifications.

B-1

Table B-1

Belden Twinax Cable Specifications

(

""PARAMETER

BELDEN CABLES
9182 (or equivalent)
9212

Impedence

150 ohms

78 ohms

DC Resistance
Conductors

22 A WG stranded tinned
copper (19 strands of
34 AWG) 46 ohms/km (14
ohms/1000 ft)

20 A WG stranded
tinned copper (7
strands of 28
A WG) 31.2 ohms/km
(9.5 ohms/lOOO ft)

Shield

Foil with drain wire
100% coverage
20.7 ohms/km (6.3 ohms/
1000 ft)

Copper braid 93%
coverage 12.5
ohms/km (3.8 ohms/
1000 ft)

28.9 pF /m (8.8 pF /ft)

64.6 pF /m (19.7
pF /ft)
129.3 pF /m (39.4
pF /ft)

Capacitance
Between wires in
a pair
One wire to shield

57.8 pF /m (17.6 pF /ft)

Voltage Rating

300 volts

Velocity of Propagation

78%

66%

Insulation

Polypropolalene

Polyethylene

Jacket

Polyvinal chloride
(PVC)

B-2

Table B-2

Belden Triax Cable Specifications
BELDEN CABLES
8233

PARAMETER
8232
75 ohms

75 ohms

20 A WG Copperweld
1120hms/Km
(35 ohms/lOOO ft)

14 A WG Solid Copper
8.50hms/km
(2.6 ohms/ 1000 ft)

8.53 ohms/km
(2.6 ohms/ 1000 ft)

4.60hms/km
(1.4 ohms/ 1000 ft)

Capacitance

56.7 pF /m
(17.3pF/ft)

same

Inductance

0.318 micro henry /
meter (0.097 microhenry/ft)

same

Velocity of Prop agation

78%

same

Voltage Rating

175 Vrms

same

Sweep Test

22 dB minimum

same

Physical Requirements

Triaxial, cellular
polyethylene insulation and minimum of:

Impedance
DC Resistance
Center Conductor

Shield

Center Conductor

20AWG

B-3

14AWG

B.3.1

Cable Resistance Versus Distance

(

B.3.1.1 Twinax Cables - The cable must have a characteristic impedance of 72 to 150 ohms. The two· \.
conductors must be tied together at one end of the cable and the dc resistance measured between the
two conductors at the other end. The maximum total capacitance between conductors for the Belden 9182
must be less than .07 uF for a cable length of 2 km (6562 ft.) and .21 uF for 6 km (19,865 ft).
The jacket for both cables is polyvinal chloride (PVC). These cables may not be suitable for outdoor or
direct inground installations (check manufacturer's recommendations).
B.3.1.2 Triax Cables - The cable used must have a characteristic impedance of 75 ohms. The shield
and center conductor should be shorted at one end of the cable and the dc resistance measured between
the shield and center conductor at the other end. The maximum total dc resistance for the Belden 8232
cable shield and center conductor must be less than 200 ohms for a cable length of 2 km (6562 ft), and
400 ohms for a cable length of 6 km (19,685 ft). The maximum total resistance for the Belden 8233
cable shield and center conductor must be less than 30 ohms for a cable length of2 km (6562 ft) and 90
ohms for 6 km (19,865 ft).
The maximum total capacitance from the shield to the center conductor must be less than 0.14 uF for
the 2 km (6562 ft) cable and 0.4 uF for the 6 km (19,685 ft) cable. The double shield provides excellent
noise rejection when properly grounded. The cellular polyethylene dielectric provides low signal loss
and low distortion. The polyethylene jacket has excellent weather and abrasion resistance. However,
this does not mean that these cables are suitable for outdoor or direct inground installations (check
manufacturer's recommendations).
NOTE
Typical cables using 20 AWG copper weld center
conductors vary from 35 to 70 ohms dc resistance.
Use of dc resistance over 112 ohms per km (35 ohms
per 1000 ft) severely derates the maximum length of
the cable. The longer cable must use solid copper, 14
AWG.
B.3.2 75 Ohm Systems
For 75 ohm systems, the cable must be twinax or triax. The recommended cable for 56K bps is a
twinax cable, Belden 9272. For higher speed, triax cables should be used.
BELDEN 9272
•

56K bps, 6 km (18K ft) point-to-point and up to 24 loads multidrop.

•

Over 24 loads, the maximum distance is derated by 73 meters (240 ft) per M8203 transformer loads and 25 meters (80 ft) per DMVll transformer loads.

•

Higher speeds can be run with Belden 9272 with no derating for loads.

•

250K bps, point-to-point or multipoint maximum distance is 2 km (6K ft) (maximuml28
transformer loads).

•

500K bps, point-to-point or multipoint maximum distance is 1.2 km (4K ft) (maximum 128
transformer loads).

•

1M bps, point-to-point or multipoint maximum distance is 600 Meters (2K ft) (maximum 64
transformer loads).

B-4

(

There are two recommended triax cables: (1), the Belden 8232 is easy to work with and (2), the Belden
8233 for long runs which, however, is difficult to work with (the center conductor is 14 A WG). Triax
cables work best in higher speeds of 250K bps to 1M bps.
BELDEN 8232
•

56K bps, point-to-point and multipoint up to 20 transformer loads with a maximum distance of 4.3 km (14K ft). Above 20 transformer loads derate at 76 meters (250 ft) per M8203
transformer load. (DMVll loads derate the maximum length by 37 meters (120 ft).)

•

250K bps, point-to-point or multipoint maximum distance is 3 km (10K ft) and no derating
(maximum 128 transformer loads).

•

500K bps, point-to-point or multipoint maximum distance is 3 km (10K ft) and no derating
(maximum 128 transformer loads).

•

1M bps, point-to-point or multipoint maximum distance is 2 km (6K ft) and derating (maximum 128 transformer loads).

BELDEN 8233
•

56K bps, point-to-point and multipoint up to 20 transformer loads maximum length is 6 km
(18K ft). Above 20 transformer loads derating is at 55 meters (180 ft) per transformer load.

•

250K bps, point-to-point or multipoint maximum length is 5 km (l6K ft) and no derating
(maximum 128 transformer loads).

•

500K bps, point-to-point or multipoint maximum length is 3.7 km (12K ft) and no derating
(maximum 128 transformer loads).

•

1M bps, point-to-point or multipoint maximum distance is 3 km (10K ft) and no derating
(maximum 128 transformer loads).
NOTE
All derating for transformers relates only to the
transformers used on the M8203. All others must be
characterized and specified on an individual basis .

. B.3.3 150 Ohm Systems
The cable is the Belden 9182 or equivalent, which is a twin ax point of sale cable developed for the
DECdataway.
This cable should only be used for 56K bps. The twinax cable produces a higher level of distortion than
the triax, with the major limiting factor of distortion not attenuation. The 9182 cable is harder to work
with because it is not as flexible as the 9272 or 8232. It also uses a polypropolene base inner insulation
which is highly flammable when the ends of the cable are stripped back and the inner insulation is
exposed.
•

56K bps, point-to-point and multipoint up to 10 M8203 loads maximum length is 4.5 km
(15K ft) without derating for loads. Derating for loads is 110 meters (360 ft) per M820310ad.
(DMVII derates the maximum length by 23 meters (75 ft) per load).

•

250K bps, point-to-point and multipoint maximum length is 3 km (10K ft) with no derating
for loads.

B-5

•
•

SOOK bps, point-to-point and multipoint maximum length is 2.S km (8K ft) with no derating
for loads.
1M bps, point-to-point and multipoint maximum length is 1.2 km (4K ft) with no derating
for loads but with a maximum of 64 loads.

B.3.4 Cable Attenuation
When selecting a cable, several factors must be considered in determining cable attenuation. The value
given by the cable vendor is for room temperature and is nominal, being subject to deviations of up to
20 percent. The attenuation increases with temperature at approximately 0.20 percent per degree Celsius (0.11 percent per degree Fahrenheit). At SO° C (122° F) an additional loss of S percent over the
room temperature specification can be expected. Finally, use at elevated temperatures causes aging at a
faster than normal rate and, after S years, could produce yet another permanent 10 percent increase in
attenuation. Thus, the initial nominal8.S3 dB/km (2.6 dB/WOO ft) loss could become, after S years use
at high temperature, 17.06 dB/km (S.2 dB/WOO ft).
B.4 INSTALLATION CONSIDERATIONS
The characteristics of the local link cable should be measured prior to installation. In particular, there
are two parameters that the user should measure and note for future reference. These are the propagation time delay, which can be measured with a pulse generator and an oscilloscope, and the dc resistance of the cable with the far end of the center conductor shorted to the inner shield. For the Belden
8232, these parameters can be expected to be nominally 4.26 ns/m (1.30 ns/ft) and lOS ohms/km (32
ohms,IOOO ft). For Belden 8233, these parameters can be expected to be nominally 4.26 ns/m (1.30
ns/ft) and 13 ohms/km (4 ohms/WOO ft). Once the cable is installed, and both ends are therefore not
available at the same place, the latter parameter can still be measured easily, and the former can be
measured by use of the time domain reflectometry (TDR) method described in Chapter 4, Service.

While installing the cable, a complete map of its layout should be made showing the position of the
cable with respect to buildings, equipment and so forth, and also the locations of all access points,
including not only splices and in-line connectors, but pull boxes as well. Cable lengths between landmarks should be carefully measured and recorded. Such a map greatly facilitates maintenance.
The following factors must be taken into account when installing the local link cable.
TEMPERATURE - The polyethylene used as the dielectric material in most coaxial and triaxial
cables begins to soften at temperatures above 80° C. As the conductor moves off center, variations in
cable characteristics occur. If installed under tension with sharp bends, the conductor may short to the
shield. Additionally, the open circuit resistance should be measured after installation to ensure against
shorts incurred during installation. This resistance should be ~20K ohms. The closed circuit resistance
should be 118.4 ohms/km (36.1 ohms/1000 ft).
MOISTURE - Moisture, or moisture related impurities, may enter the cable through cuts or scratches
in the outer jacket or through improperly installed connectors. Minute amounts of water vapor will
condense into water, which can migrate along the braid. Water condensed from a polluted atmosphere
can contaminate the entire length of cable, shorten its lifetime, and seriously degrade performance.
PULLING TENSION - For most environmental conditions, it is generally preferred that the cable be
installed in a conduit, through which the cable must be pulled. During installation, the total pulling
tension on the 2.0 AWG center conductor must not exceed 8.8N (2 pounds).
For ease in maintenance, it is best to divide the cable into sections. For long cable runs in a conduit, it
is convenient to have a pull box every 30.48 meters (100 ft). A 90 degree conduit bend is equal to 9.1S
meters (30 ft) of straight level conduit. It is also recommended that an antifriction agent be used during
pulling, providing that the agent is compatible with the cable jacket material.

B-6

(
!
'..,

SPLICES AND CONNECTORS - The cable layout should provide access points for test purposes
and for replacing defective sections. Strain relief must be provided at all splices and in-line connectors.
RECOMMENDED WIRING PRACTICES - Chapter 8, Article 800 of the National Electric Code
defines wiring rules for communications circuits. These rules must be observed for safe operation of
the line unit. In particular, the following provisions of the code should be noted.
"Communication conductors shall not be placed in a raceway, compartment, outlet box, junction box
or similar fitting with conductors for light and power. .. "
"Communication conductors may be run in the same shaft with conductors for light and power provided the conductors of the two systems are separated by at least two inches."
"Suitable protective devices must be employed for wiring between buildings."
SURGE WITHSTAND CAPABILITY - The receiver has no provision for protection against normal
mode voltage (voltage across the receiver input) surges exceeding 30 volts. If surge withstand is required, a separate circuit must be installed to condition signals to the receiver.
NOISE - The M8203 is designed to operate with a common mode rejection ratio 500: I. Cable selection, installation grounding and noise suppression are means of reducing line error rates.

D.S RECOMMENDED CONNECTORS
The following components are recommended for use in joining cable sections and also for connecting
the cable to the M8203 BC55A panel. All of these components, which are shown in Figure B-1, are
manufactured by AMP Inc., Harrisburg, Pennsylvania.
Component

DIGITAL Part Number

AMP Part No.

Small cable clamp
Large cable clamp
Male housing
Male pin
Female housing
Female pin
14 ga male pin

12-11430-00
12-11430-01
12-12527
12-12001
12-12526
12-12000
12-12001-1

206062-1
206358-1
206153-1
66589-2
206060-1
66590-2
66587-2

B-7

TWINAX
OR

FEMALE
CONNECTOR

~LE
PINS

CLAMP
FEMALE

MALE
CONNECTOR

MALE

~
~
~MALE

FOR TRIAX
CABLE AND
9182 TWINAX

PINS

Figure B-1

Local Link Cable Connectors

B-8

MK-0895

The connectors are installed by crimping the pins to the cable; the recommended crimper is the AMP
Type VI, 90277-1. It is very unlikely that one can install a set of connectors without requiring the use
of an ejector, to remove pins that have been inserted incorrectly. The proper ejector for the above pins
is the AMP 305183.
The pin holes in the housing and receptacle are numbered. When working with a connector, it should
always be oriented so that hole 1 (signal +) is at the top, hole 4 (outer shield) is at the bottom, and the
holes on either side are 2 (signal -) and 3 (second signal -, used with triax only).
NOTE
The system should be polarized and must be terminated at both ends. The system should be such so that
any computer system can be removed and the connectors tied together without the need for additional
ports.
1.

The cable clamp assembly is supplied as a shell, with two screws and three clamps, of which
the one for the largest cable size should be used. The shell slides on the cable.

The center conductor must be dressed back enough so it will fit into a pin with the pin
crimped back to its insulation as well as to the conductor. Both shields must be dressed back
about another half inch, and the final half inch of the inner insulation tapered so that its tip
fits into the pin, and about a quarter inch fits into the connector along with the center
conductor. The appropriate male/female pin must then be crimped to both the conductor
and its insulation, and inserted in the hole.
a.

For twin ax cables, appropriate pins are simply crimped, as indicated in the previous
statement, to the colored wire of the pair.

For triax cables, the inner shield must be separated into two parts, the pins attached to them,
and inserted into holes 2 and 3. For twinax cables, the pins are attached to the transparent or
black wire and inserted into hole 2.

The outer shield is then pulled together, insulated from the inner shield, a pin crimped to it,
and inserted in hole 4 for splicing connections.

The shell must be screwed into the housing, and the clamp screwed to the shell.

After male and female connectors have been plugged together, the other ring of the female
housing must be screwed over the male housing.

B.6 GROUNDING RECOMMENDATIONS
This paragraph describes the proper grounding techniques that must be used to prevent the possibility
of personal injury.
There is a possibility of a difference in ground potential between two computers that are separated by
some distance, especially if they are powered from different sockets.
If in doubt about the recommendations in this paragraph, consult a competent professional (Electrical/Electronic Engineer) for advice.

B-9

The following warnings should be adhered to:

(

WARNING
1. The outer shield of the local link cable is connected to the computer cabinet by the BC55A at
each drop.
2. The difference in grounds must be checked before connecting the cable to the BC55A panel.
Ideally, the potential difference should be near
zero. If a potential difference does exist, it is advisable to check with higher levels of Field Support authority.
The computer system chassis must be grounded. The grounding conductor should be connected to a
water pipe electrode, or if none is available, to the power service conduit, service equipment closure, or
grounding electrode conductor where the grounding conductor of the power service-is connected to a
water pipe electrode at the building.
When neither of the above means of grounding is available, it is permissible to connect the grounding
conductor to the service conduit, service equipment enclosure, grounding electrode conductor, or
grounding electrode of the power service of a multigrounded neutral power system.
If it is impossible to ground the computer system chassis by one of the above methods, the grounding
conductor must be connected to one of the following:
1.

A concrete-encased electrode of not less than 6.09 meters (20 ft) of bare copper conductor,
no smaller than 4 A WG, encased in at least 5.08 cm (2 in) of concrete, and located within
and near the bottom of a concrete foundation footing that is in direct contact with the earth.

An effectively grounded metal structure.

A continuous and extensive underground gas-piping system, where acceptable to both the
servicing gas supplier and to the authority having jurisdiction.

A ground rod or pipe driven into permanently damp earth.

NOTE
The minimum ground wire size is 4 AW G.
WARNING
V nder no circumstances shall the grounding conductor be connected to a steam or hot water pipe, a
lightning rod conductor, or pipe or rod electrodes
grounding other than multiground neutral power circuits.

B-lO

APPENDIX C
INTEGRATED CIRCUIT DESCRIPTIONS

C.l INTRODUCTION
Selected integrated circuits (lC) shown in the M8203 Print Set are provided in this appendix as an aid
in troubleshooting to the IC level. The descriptions include one or more of the following: pin/signal
designations, equivalent logic block diagrams, logic symbols, and truth/function tables.

The following ICs are included:
26LS29
26LS30
26LS31
26LS32
2652
3341
3603
74S138
74S151
74LS161
74S174
74S240
74LS244
74LS374
75110
93S16

Quad Three-State Single Ended RS-423-A Line Driver
Quad Driver RS-422-A/RS-423-A
Quad Driver RS-422-A High Speed
Quad Differential Line Receiver RS-422-A/RS-423-A
USYRT, Universal Synchronous Receiver/Transmitter
Four-Bit X 64 Word Propagable Register (FIFO)
High Speed Dual Line Receivers
Decoder Multiplexer
Data Selectors/Multiplexers
Synchronous Four-Bit Counter
HEX/QUAD D-Type F-F with Clear
Octal Inverter and Line Driver with 3-State Output
Octal Three-State Buffer
Octal D-Type Transparent Latches & Edge-Triggered FF
Dual Line Driver
BCD Decade/Four-Bit Binary Counter

C-l

C.2

SELECTED INTEGRA TED CIRCUITS

26LS29 - Quad Three-State Single-Ended RS-423-A Line Driver
The 26LS29 is a quad single-ended line driver which meets all requirements of the Electronics Industries Association (EIA) Standard RS-423-A and Federal Standard 1030. This line driver features
four buffered outputs with high source and sink current, and output short circuit protection.
A slew rate control pin allows the use of an external capacitor to control slew rate for suppression of
near end cross talk to receivers in the cable.
LOGIC DIAGRAM
26LS29

CONNECTION DIAGRAM
TOP VIEW

r-------,
I
I
I
I INPUT D
I

I
I INPUT C

I 56 PF

Vee

I
110

I
I
I
I INPUT B

INPUT A

OUTPUT A

INPUT B

OUTPUT B

-6

>t-'-'---'-- OUTPUT C

I INPUT A

SLEW RATE
CONTROL A

>1-;":;""'--'-- OUTPUT D

1·

~"":"'--'--

OUTPUT A

~:"":"-......L._

OUTPUT B

ENABLE

SLEW RATE
CONTROL B

GND

SLEW RATE
CONTROL C

INPUT C

OUTPUT C

INT D

OUTPUT D

VEE

SLEW RATE
CONTROL D

NOTE: PIN 1 IS MARKED FOR ORIENTATION.
MK-0950

----,

SLEW RATE CONTROLS

I
9,12,16,13
I
I_ _ENABLE
=
PIN
4
I
_ _ _ _ _ _ _ _ ....J

C-2

26LS30 - Quad Single-Ended RS-423-A Line Driver
The 26LS30 is a single-ended line driver which meets all of EIA Standard RS-423-A. The line driver
features four independent single-ended outputs. A slew rate control pin allows the use of an external
capacitor to control slew rate for suppression of near end cross talk to receivers in the cable.

LOGIC DIAGRAM

CONNECTION DIAGRAM -

TOP VIEW

26LS30

INPUT D

OUTPUTD

Vee

SLEW RATE
CONTROL A

INPUT A

OUTPUT A

INPUT/ENABLE B

OUTPUT B

MODE

SLEW RATE
CONTROL B
SLEW RATE
CONTROL C

GND
TYPICAL
APPLICATION

INPUT C

INPUT A

OUTPUT C

INPUT/ENABLE C

OUTPUT C

INPUT D

OUTPUT D

VEE

SLEW RATE
CONTROL D

OUTPUT A
NOTE:
PIN 1 IS MARKED
FOR ORIENTATION.

INPUT B

OUTPUT B

9. 12. 16. 13

= PIN 4
I
L __C~T!9~ _ _ _ _ ~
MODE

C-3

MK-0949

26LS31 - Quad High Speed Differential Line Driver
The 26LS31 is a quad differential line driver which meets all of the requirements of EIA Standard RS422-A and Federal Standard 1020. This line driver provides unipolar differential drive to twisted-pair
or parallel-wire transmission lines. The circuit also provides an enable and disable function common to
all four drivers.
LOGIC DIAGRAM

ENABLE

INPUT D
15

GND

INPUT C

INPUT B

OUTPUT OUTPUT
D+
D-

OUTPUT
C+

INPUT A

OUTPUT
C-

6
OUTPUT
B+

5
OUTPUT
B-

2
OUTPUT

A+

CONNECTION DIAGRAM
(TOPVIEW)

+5.0V

INPUT A

INPUT D
A OUTPUTS!

} a OUTPUTS
ENABLE
ENABLE
B OUTPUTS!
}

C OUTPUTS

INPUT B
INPUT C

GND
26LS31

NOTE: PIN 1 IS MARKED FOR ORIENTATION.
MK-0938

C-4

3
OUTPUT
A-

26LS32 - Quad Differential Line Receiver

The 26LS32 is a quad line receiver which meets the requirements of EIA Standards RS-422-A, RS423-A, and Federal Standards 1020 and 1030. The circuit provides an enable and disable function common to all four receivers. The 26LS32 features 3-State outputs and incorporates a failsafe input-output
relationship which keeps the outputs high when the inputs are open.
LOGIC DIAGRAM

ENABLE
12

INPUT INPUT
0+
0-

INPUT INPUT

INPUT INPUT
B+
B-

11
GND

OUTPUT D

INPUT INPUT

A-

OUTPUT C

OUTPUT B

OUTPUT A

CONNECTION DIAGRAM
TOP VIEW

INPUTS A

Vcc
}

INPUTS 8

OUTPUT A
ENABLE

OUTPUT B

OUTPUT C

INPUTS C

ENABLE

OUTPUT D

}

INPUTS D

GND
26LS32
NOTE: PIN 1 IS MARKED FOR ORIENTATION
MK-0937

C-5

This page intentionally left blank.

C-6

2652 - Universal Synchronous Receiver/Transmitter (USYRT)
Complete serialization, deserialization and buffering is provided by the data paths of the USYRT.
Output signals are provided to the USYRT controller to indicate the state of the data paths. The
internal logic does not provide the intelligence to make higher level decisions such as incorporation of
command fields or recognition of extended address fields. These tasks must be performed by the
USYRT controller.
The USYRT is a dual-in-line package (DIP). A terminal connection (identification) diagram is presented
in Figure C-l.
Data port bits DP07:DPOO are dedicated to service four eight-bit wide registers. Bits DPI5:DP08
service either control information or status registers. The PCSCR register is reserved and the M8203
Line Unit uses this register as a test register for the modem interface (does not affect the USYRT). (See
Table C-l.)
A suggested block diagram is shown in Figure C-2 and receive and transmit signal timing waveforms
are given in Figures C-3 and C-4 respectively. Figure C-5 shows the timing waveforms at the tri-state
outputs.

C-7

(

TSO 38

03 RSI

'-.

02 RXCLK
TBEMTY 35
39 TXCLK
TXACT 34
TERR

RSTARY 07
RXACT 05
08 RXENA
SYNC + 04
ADR COMP

01 CE

DP 15
DP 14

23 DPENA

DP 13
DP 12
DP 11
DP 10

19 ADR SEL 2

DP 09
DP 08

20 ADR SEL 1
21 ADR SEL 0
BYTE GP

DP 07

BIDIRECTIONAL
I/O TRI STATE
LINES

DO 06
DP 05
DP 04

WR TO LSI

DP 03
DP 02

MAINT SEL
33 RESET
GND
09

DP 01
DP 00

NOTE: A) PIN 32 +5V POWER SUPPLY
! 10% AT 1 50mA.
B) PIN 01 -CHIP ENABLE WILL
WITHSTAND +13.2V.
C) PIN 9 = GROUND
MK-0919

Figure C-l Terminal Connection (Identification) Diagram
(2112517-01 Variation)

C-8

RCV SERIAL IN

15
MUX &
TR ANS
SE RIAL __ L... BSP
CTL
OUT

TRNS CRC
REG

I---

RCV CRC
REG ERR DET

RCV DATA
SHIFT REG

MAINT SEL

j
J

~
SYNC/FLAG DET

TRNS SHIFT
REG

SYNC + FLAG CMP -

PCV COMP
(REOM)

(RSOM)

TRANS DATA
BUF

TRANS CTL

(TOSR)

PCSR7-0

PCSAR7-0

SPCL CHAR.
REG

R-T/SNYC +
SEC'D RCV
ADRS REG

~
RCV DATA

Figure C-2 Suggested Block Diagram (Sheet 1 of 2)

C-lO

RCV CTL

BUF

(RDSR)

RCV
BSP
CTL

I---

)

12
MK-0915
(SHEET 1 OF 2)

RXCLK

50% DUTY CYCLE ±10%

1.4MHz MAX.

t286NSMIN-+286NSMIN\
RSI

~ 200NS I-- I'------'
SAMPLE TIME

\----~

~r--------------------~)(~___________

-t~~y=
R DATRY

D_PE_N_A____________________________________

I-

300NS MAX

r---------~
2~~S
~
J;L=250NSMIN~~

_________

RXACT
MK·0894

Figure C-3 Receive Signal Timing Waveforms

C-12

;C=2~~S~~R_ES_E_T_____________________________________________________
TX ClK

1.4 MHz MAX.

50% DUTY CYCLE ±10%

j--286NS MIN

____D_PE_N_A________________________

J~250NSMIN~~__________________________
I 200NS I--1 MAX I

---T~BE-M-T-Y----------------y--r---------------------~\
--~

TXENA

2~~~S

-------------------------~yl~TXACT

----1' ~~S

TSO

r--

\~
MK-0922

Figure C-4 Transmit Signal Timing Waveforms

C-13

(
I

WR TRANSFER TO USYR/T

=L :'O~S_

SO NS \;=_T_s_E_TU_P_ _ _ _ _ _ _ _ _ _

_ _ ~~~LD

~----------_~2S0NS----------~~--~--OV

__________________

_J~

--------------------~><===:~

Lov

-------------------------------><===:~
T SETUP
RD TRANSFER

30NS

)

. I-

DPENA

~ 250NS

DPO-7,8-1S

OV
3V

'\.

I
ADRS 0,1,2

I - TOLD
H

VALID DATA

SONS ilS0NS

--.J

WR LSI
BYTE OP

\,1
j\.

--' \

3V
OV
MK-0927

Figure C-5 Tri-State Output Waveforms

C-14

3341 - Four-Bit X 64-Word Propagable Register (FIFO)
The 3341 is a 64-word X 4-bit memory that operates in a first in first out (FIFO) mode. Inputs and
outputs are completely independent (no common clocks). When both INPUT READY and SHIFT IN
are high, the four bits on DO-D3 are loaded into the first bit position where they stay until INPUT
READY and SHIFT IN go low. This causes the bits to propagate to the second bit position (if empty)
where they are propagated to the bottom of the silo by internal control signals.
When data has been transferred to the bottom of the memory, OUTPUT READY goes high indicating the presence of valid data. When both OUTPUT READY and SHIFT OUT are high, data is
shifted out of the silo. This causes OUTPUT READY to go low. Data is maintained until both
OUTPUT READY and SHIFT OUT are low. At this time, the bits in the adjacent upstream cell are
transferred into the last cell causing OUTPUT READY to go high again. If the silo has been emptied,
OUTPUT READY stays low.
LOGIC BLOCK DIAGRAM
.....---..,13
FIFO
INPUT
STAGE

INPUT
READY

64 WORD x 4 BIT
MAIN REGISTER

INPUT
CONTROL

SHIFT IN

VSS=PIN 16
VDD=PIN 8

OUTPUT
READY

VGG =PIN 1

PIN COFIGURATION
(TOP VIEW)

MASTER RESET
LOGIC SYMBOL

SHIFT
OUT

OUTPU:r
CONTROL
LOGIC

MAIN REGISTER
CONTROL LOGIC

INPUT
READY

SHIFT OUT

VGG

SHIFT OUT

INPUT READY
3

OUT PUT
READY

SHIFT IN
3341

MASTER RESET

Vss = PIN 16 +5V

OUTPUT
READY

SHIFT IN

VSS

V DD

Q2
Q3

MK·0942

V DD = PIN 8 GND
VGG = PIN 1 -12V

C-15

3603 - High Speed Dual Line Receivers
The 3603 line receivers are used to receive data in balanced, unbalanced or party-line transmission
systems. The two receivers share the common voltage and ground busses and have a three-state output
for bus organized systems.
LOGIC SYMBOL
CONNECTION DIAGRAM

(TOP VIEW}

6
1A

1B
NC

1Y
1G

11
5

2B
NC

GND

NOTE: PIN 1 IS MARKED FOR ORIENTATION.

Vcc_ = PIN 13

NC = NO CONNECTION.

VCC+ = PIN 14
GND = PIN 7

FUNCTION TABLE
INPUTS

DIFFERENTIAL

OUTPUT

GATE

DISABLE

V ID > +25mV

-25mV < V ID < +25mV

V ID < -25mV

INPUT VOLTAGE
V ID =VA -

H = HIGH

Z = HIGH-IMPEDANCE STATE

L= LOW
X = DON'T CARE
MK-0931

? = DON'T KNOW

C-16

74S138 - Decoder Multiplexer
The 74S138 decodes one of eight lines dependent on the conditions at the three binary select inputs and
the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external
gates or inverters when expandng.

15
DO

BLOCK DIAGRAM

ENABLE
INPUTS

DATA
OUTPUTS
11

- Il -1
A-

>
">
..... ~

- -

f',

,C -

- -

B2~

SELECT
INPUTS

,..,
..... ~

--'

-1

,..,

...V

FUNCTION TABLE
INPUTS

OUTPUTS
ENABLE

SELECT

G1 G2

DO 01 02 03 04 05 06 07

G2 = G2A+G2B
H = HIGH LEVEL, L = LOW LEVEL, X = IRRELEVANT

C-17

VCC
GNO

= PIN 16
= PIN 8
MK-0904

74S1S1 - Data Selector/Multiplexer
The 74S151 monolithic data selector/multiplexer contains full on-chip binary decoding to select the
desired data source. The 74S 151 selects one of eight data sources and has a strobe input which must be
at a low logic level to enable the device. A high level at the strobe forces the W output high, and the Y
output (as applicable) low.

STRO BE (7)
(ENAB LE)
DO (4)

,... ~

-V

D1 (3)

))-

I--

02 (2)

D3 (1 )

DATA
INPUTS

D4 (15)

,7
(6 )

r-:=::I
-;;;J
-fi--

D5 (14)

-rr-

f-rf-

06 (13)

07 (12)

f-f'--

~[>r~>DATA
SELECT
(BINARY)

-Sl ~~~
/ - -V
C ..£.

~ ~~

V- -V

MK·0917

C-18

OUTPUTY
OUTPUTW

74S151 - Data Selector/Multiplexer (Cont)
LOGIC SYMBOL
7
STB
12
13
14
15

07
06

W 5

05
04

745151

03
2
3
4

Y 6

02
01
00

745151 TRUTH TABLE
INPUTS
S2

0
0
1
0
1
0
1
0
1
0
1

1
1

1
0

0
1

x
X

0
1

x
x

0
1

x
x

0
1

x
x

0
1

0
0
1
1
0

1
1
1
1
1
1
1

0
0
0

0
0
0
0
1
1
1
1

STB

0
1
1
1
1

0
0
0
0
0
0
0
0
1

0
1
1
0
0
1
1
0
0
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

OUTPUTS
03

WHEN USEO TO INOICATE AN INPUT X

0
1

0
1
0
1
0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

= IRRELEVANT.
MK·0918

C-19

74LS161 - Synchronous 4-Bit Counter
The 74LS161 is a synchronous, presettable binary counter which features an internal carry look-ahead ('
for application in high-speed counting
.",

3
4
DATA
INPUTS

14
13
12

OUTPUTS

----

CLR 74lS161
lD
ClK
ENABLE P
ENABLE T

CNT EN
CRY EN

15 CARRY
OUTPUT

GND = PIN 8
+5V = PIN 16
MK-0908

C-20

74LS161 - Synchronous 4-Bit Counter (Cont)
TYPICAL. CLEAR. PRESET. COUNT. AND INHIBIT SEQUENCE:
ILLUSTRATED BELOW IS THE FOLLOWING SEQUENCE:
1. CLEAR OUTPUT TO O.

2. PRESET TO BINARY 14.

CLEAR

3. COUNT TO 15.16. 17. 0.1. AND 2.
4. INHIBIT

(ASYNCH RONOUS)

LOAD

r------------------r-------------------

A _ _ _--,_ _ _ _11- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

DATA
INPUTS

B _ _ _---!_ _ _ _IL.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
C

11""""--+---.,-.------------------L __________________ _

,r----:---,r-------------------L __________________ _

CLOCK

ENABLE P

I
I

ENABLE T

I•
I

----1
-

- -

II
•I
I

-!---!--~

------,

QB _____ ..&I----.r-------J
OUTPUTS

-----,

QC _____ ...I_---!

------,

QD ______I___~

•
1
RIPPLE CARRY
...."
--------~-----~I
I~----~I---------OUTPUT
14

(CO)

2 •

It-o-----COUNT----.+I...- - INHIBIT -----<..

CLEAR
PRESET

MK·0910

C-21

74S174 - Hex D-Type Flip-Flops with Clear
(
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop
logic. All have a direct clear i n p u t . \ '
Information at the D inputs meeting the setup time requirements is transferred to the R outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going pul~e. When the clock input is at either the
high or low level, the D input signal has no effect at the output.
BLOCK DIAGRAM

CLOCK
CLEAR

LOGIC SYMBOL

04
03
02
01

CLR

CLOCK
CLEAR

5
15
02

CLOCK
CLEAR

CLK

CLOCK
CLEAR
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
CLEAR

CLOCK

OUTPUTS
D

1--...f-..4[J CLEAR

x
t
t

CLOCK

L
H

H = HIGH LEVEL (STEADY STATE)
L = LOW LEVEL (STEADY STATE)
X = IRRELEVANT
t = TRANSITION FROM LOW TO HIGH LEVEL

05 0 ..,;.1_1+--+--1

CLOCK
CLOCK

X~"""'-+-a

CLEAR

00 = THE LEVEL OF a BEFORE THE INDICATED
STEADY STATE INPUT CONDITIONS WERE
ESTABLISHED.
CLEAR
PIN (16)

= VCC. PIN (8) = GND
MK-0930

C-22

74S240 - Octal Inverter and Line Driver with 3-State Output
These octal inverters and line drivers provide inverting outputs, and G (active-low output control)
inputs. G selects four inverting buffers.

TYPICAL OF ALL
OUTPUTS

FROM
DATA
BUS

OUTPUT
PORTS

----.--VCC
..-_---t R

OUTPUT

EQUIVALENT OF
EACH INPUT
VCC--

h .. -

- - -......---t- GN D

---.

INPUTf4J---

8
11
6
13
4
15

-2
17

TO
DATA
BUS

INPUT
PORTS

74S240
A

Y19

12
9

(TOP VIEW)

Vee

2(3

2A3

1Y3 2A2

1Y4

1A3

2Y2

2Y1

7
16
5
18
3

1A1

C-23

2Y4

1A2

2Y3

1A4

GND

(
\

This page intentionally left blank.

C-24

74LS244 - Octal Buffer and Line Driver with 3-State Output
These octal buffers and line drivers provide selection of inverting and non-inverting outputs, symmetrical G (active-low output control) inputs and complementary G and G inputs.

74LS244

SCHEMATIC OF INPUTS
EQUIVALENT OF
EACH INPUT

---

Vcc

+INPUT

1",

---

,..7

F~
F
F
F
F
F
F

14
7
16
5

18
3

(TOP VIEW)

SCHEMATIC OF OUTPUTS
TYPICAL OF ALL
OUTPUTS

Vcc

2<3

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

- - - -......-VCC
R

OUTPUT

.......-

.....--I--GND

MK-0911

C-25

74LS374 - Octal D-Type Edge-Triggered Flip-Flops
The eight flip-flops of the 74LS374 are edge-triggered D-type flip-flops. On the positive transition of
the clock, the R outputs will be set to the logic states that were setup at the D inputs.
A buffered output control input can be used to place the eight outputs in either a normal logic state
(high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly.
The output control does not affect the internal operation of the flip-flops. That is, the old data can be
retained or new data can be entered while the outputs are off.

BLOCK DIAGRAM
POSITIVE·EDGE TRIGGERED FLlP·FLOPS

LOGIC SYMBOL
13

(1 )

ENABLE

14
07 _13_ _ _--1
7
Q7

INPUTS

06 .;;;.8_ _-+---1

74lS374
07

05 _14
_ _-t----f

15
6

5
19
2

OUTPUTS

ClK

OUTPUT
CONTROL

04 _7_ _-t----f

FUNCTION TABLE

04
OUTPUT
CONTROL

03 _1_7_----11----1

CLOCK

OUTPUT

t
t

L
00

X
X

-+_-1

02 _4_ _

18
01";"";;"--+---I

H = HIGH LEVEL
L = LOW LEVEL

t = TRANSITION FROM LOW TO HIGH LEVEL
X = IRRELEVENT (ANY INPUT INCLUDING TRANSITIONS)
01

-+_-1

00 _3_ _

..... ..

ot--~[]
......;;

Z = OFF (HIGH IMPEDANCE) STATE OF A THREE·STATE
OUTPUT
0 0 = lEVEL OF R BEFORE THE INDICATED STEADY·STATE
INPUT CONDITIONS WERE ESTABLISHEO

MK·0941

CLOCK

C-26

75110 - Dual Line Driver

The 75110 driver circuits feature a constant output current that is switched to either of two output
terminals by the appropriate logic levels at the input terminals. The output current can be switched off
(inhibited) by low logic levels on the inhibit inputs.

(TOP VIEW)

VCC+

(2A)

(2B)

OUTPUT OUTPUT
lY
1Z
VCC.

INH OUTPUT OUTPUT
D
2Z
2Y

5
8

(i'NH 2C)4

(2Y)
(2Z)

(INH D)

(TI\fFI D)
(1A)

(1 B)

13
2

(1Y)

INPUT INPUT
1B
lA

INH
1C

INH
2C

INPUT INPUT
2A
2B

GND

(1 Z)
FUNCTION TABLE
LOGIC INPUTS

INHIBITOR
INPUTS

OUTPUTS

OFF

H = HIGH LEVEL, L = LOW LEVEL, X = IRRELEVENT
MK-0940

C~27

93S16 - BCD Decade/Four-Bit Binary Counter

The 93S16 is a fully synchronous 4-bit decimal and binary counter. With the parallel enable (LD) low,
data on the inputs is parallel loaded on the positive clock transition. When LD is high and both count ."
enables are also high, counting will occur on the low-to-high clock transition.
The terminal count state 1111 is decoded and ANDed with CRY EN in the terminal count (CO)
output. If CRY EN is high and the counter is in its terminal count state, then CO is high.
The counter has an asynchronous master reset (CLR). A low on the CLR input forces the outputs low
independent of all other inputs. The only requirements on the LD, CNT EN, CRY EN, and DO-D3
inputs is that they meet the setup time requirements before the clock low-to-high transition.
FUNCTION TABLE
INPUTS

OUTPUTS

CLK CLR

CNT
7

EN
10

COUNT

H = HIGH

NC = NO CHANGE

L = LOW

0 1 MAY BE EITHER HIGH OR LOW

X = DON'T CARE

LOW-TO-HIGH TRANSITION

LOGIC SYMBOL

r
PA RALLEL
DATA
IN PUTS

93S16
3
4

6
9~

PAR ALLEL LOAD
ENA BLE
MASTER RESET

13
12

PARALLEL
OUTPUTS

r------

1,.,

CLK

LD
CLR
CLR

COUNT
ENABLE

7
10

'\
~

CNT EN

TERMINAL
COUNT

CRY EN
MK-0914

C-28

GLOSSARY

ABORT
In bit oriented protocol, a character with
eight ones/non-valid character. It is usually
used to terminate a message that cannot be
completed with valid data, or transmitter
shutdown after a valid flag has been sent
for the end of the message.

AX
Address extended registers on the M8203.
BCC

DISSI
Used on the M8203 to disable the silos to
access the Universal Synchronous Receiver /Transmitter (USYR T) directly.
DMC
Data communications microcontroller option designation for the read only memory
(ROM) controlled microprocessors and
line units that are run by the microcontroller.
DTR

Block check character, error checking, usually a cyclic redundancy check character
(CRC) status bit.

Electronic Industries Association (EIA)
signal indicating that the data terminal is
ready to accept data.
EBLK
Bit oriented protocol, indicates that the end
flag is to be transmitted or the receiver has
received a valid flag character to terminate
the message.

BOP
Bit oriented protocol.
BPS
Bits per second.
CARR
Carrier, indication from the receiver that a
signal is present.

ECS
Maintenance clock, 24 KHz on the M8203.

ENAX
Enable extended registers on the M8203.

CCP
Character oriented protocol.

EOM
End of Message flag.

Cyclic redundancy check character.

GOAH
In bit oriented protocol, seven ones followed by a zero, used for stuffing or abutting messages.

CRC

CS
Clear to send from the Integral Modem or
Modem Interface, used for controlling the
data flow on the start of the transmission.
ThIs is normally a reply to Request to Send
being sent.

HDX
Half-duplex, indicates transmission of data
in one direction at a time.

GLOSSARY-l

POLL

IC
In Clear or receiver clear on the M8203.
ICIR
In Composite Ready, indicates that the Receiver Silo is ready to receive another character from the USYRT.
IDLE
A state when no valid data or flags are
available to be sent. This is a character determined by the protocol being used and
can be abort, go ahead, flag or sync characters.

This is a new signal under RS449 that is not
defined, but is to be used to multidrop configurations for modern control.
RACT
Receiver active, this indicates that the receiver is synced up and receiving characters.
RDAX
Read extended registers, this is used in the
M8203 to start the read cycle of the extended registers.

IERROR
Maintenance function that allows ones to
be inserted in the data that is looped back
between the transmitter and receiver in the
maintenance mode.

READY

I RDI
In Ready indicates that a valid character is
ready to be read from the receiver silo.

RING
Incoming Call, this is used by the Modern
Interface to indicate that the modern has
been called or dialed by another modern
and start up will be corning.

KMC
Random Access Memory (RAM) controlled
rnicrocontroller, K indicates the general use
option.

Read~ indicates that the extended register
functIOn has been completed and data is
ready or the out registers are ready to be
loaded for the next transfer.

RTS
Request to Send, this is used to start the
transmitter section of the modern and indicates that the USYR T is ready to start
transmitting as soon as Clear to Send is returned from the modern.

LULP
Line unit loop, this is a maintenance function that loops back data internally in the
USYRT.

SEC A
Secondary address mode, this is used for
multidrop environments in bit oriented
protocol to select the receiver on the line.

o ACT
Out Active, this means the transmitter is in
the process of transmitting data or control
characters.

SEL FR
Select frequency is used in the Modern Interface to select the data transmission
speed.

OC
Out Clear, this is used to clear the transmit
section of the M8203.
OCOR
Out Composite Ready, this indicates that a
valid character is ready to be loaded into
the USYRT.

SEL SBY

ORDO
Out Ready, this indicates that the Transmit
Silo is ready to receive another character
from the microprocessor.

Select standby is used by the Modern Interface to put the modern in the standby
mode.
This is used in maintenance to monitor the
data on a bit by bit shift of data out of the
USYRT.

GLOSSARY-2

SIGQ
Signal Quality, this comes from the modem
interface and is used to determine if the line
quality is good for the data being received.

STRIP
Strip is used to strip sync or flag characters
received.
SW

SIGR
Signal rate, this is an indication from the
Modem Interface of the speed at which the
modem is running.
SOM
Start of Message.

Switch.

TESTM
Test mode, this indicates that the modem is
in the test mode.
WAX

STBY
Standby, this indicates the modem is in the
standby mode.

Write to the extended registers on the
M8203.

GLOSSARY-3

INDEX
A
Addressing, 3-4, 3-14, 3-19
Applications, 1-6, 1-7, 2-2, 2-3, 2-4
PDP-11, 1-6
VAX-11 , 1-7

Register 16,3-16,3-17
Register 17,3-17,3-18
Register AXO-15, 3-20
Register AXO-16, 3-21
Register AX 1-15, 3-22
Register AX 1-16, 3-23
Register AX2-15, 3-24
Register AX2-15, 3-24
Register AX3-15, 3-25
Register AX3-16, 3-27
Selection, 3-4, 3-5
Summary, 3-2 through 3-4
Data Rate Generator, 3-32, 3-33
Integral Modem, 3-39
Receiver, 3-40
Transmitter, 3-44
Receive Silo, 3-29, 3-30
Sequencer, 3-29
Transmit Silo, 3-27, 3-28, 3-29
USYRT, 3-27, 3-29, 3-31, 3-32, C-7
through C-14

B
Berg Port Interface. See Functional Description.
Block Diagram, 1-4

c
Cables, 1-6, 1-7,2-1 through 2-8, B-1
Characteristics, B-4 through B-6
CRe. See Error Checking.
Diagrams, 2-2 through 2-5
Installation, B-6 through B-10
Specifications, B-1 through B-3
D

Data Rate Selection, 3-32, 3-38
Diagnostics. See Maintenance.
Differential Interface, 2-5 through 2-8

Half-Duplex, 1-7,2-1, 2-2

Error Checking, 1-1, 3-21, 3-23, 3-24, 3-27
Extended Registers. See Functional Description

Integral Modem. See Functional Description.
I ntegrated Circuit Descriptions, C-1 through C-29
I nterface Signals
Levels, 2-7, 2-8
Types, 2-9 through 2-16

F
Full Duplex Mode, 1-7,2-1,2-2
Functional Description
Berg Port Interface, 3-1
Input/Output Registers, 3-3
Bit Descriptions
Register 10, 3-6, 3-7
Register II, 3-8, 3-9
Register 12, 3-10, 3-11
Register 13,3-12, 3-13
Register 14,3-14, 3-15,
Register 15,3-15,3-16

Jumper Connections, 2-6, 2-9, 2-10, 3-44
M

Maintenance
Corrective, 4-3
Functions, 3-13, 3-17
LED Read-Out, 4-3

INDEX-l

M icrodiagnostics, A-I throu~h A-5
Philosophy, 4-1
Preventive, 4-1
Modem Interface, 3-32
Modem Standards
Integral, 1-2, 1-6, 2-2, 3-39 through 3-43

RS-232-C, 2-5
RS-422-A, 2-6
RS-423-A, 2-6
RS-449, 2-7 through 2-9
Summary, 1-5, 1-6, 2-3
V.35,2-9
p

Power Requirements, I-I
Preventive Maintenance. See Maintenance.
Protocols
Bit Oriented, 1-5, 3-32, 3-34
Character Oriented, 1-5 3-32, 3-35

s
Sequencer. See Functional Description.
Single-Ended Interface, 2-4 through 2-9, 3-39
Status
Line, 3-8
Modem, 3-12, 3-13,4-3
Receiver, 3-10
Switch Packs, 2-10, 3-15, 3-16, 3-26, 3-27,

3-39
T
Test Connectors, 2-3, 2-4, 2-5
Transmit Silo. See Functional Description.

u
USYRT. See Functional Description.

R
Receive Silo. See Functional Description.

INDEX-2

\,..

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M8203 LINE UNIT TECHNICAL MANUAL
EK-M8203-TM-002

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