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EK-LSIFS-SV-005

January 1985

416 pages

Original

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Document:	LSI-11 Systems Service Manual
Order Number:	EK-LSIFS-SV
Revision:	005
Pages:	416
Original Filename:	EK0LSIFS-SV-005_LSI-11_Systems_Service_Manual_Volume_3_Jan85.pdf

OCR Text

EK-LSIFS-SV-005

lSI-11 Systems
Service Manual
Volume III

Prepared by Educational Services
of
Digital Equipment Corporation

Preliminary, April 1978
1st Edition, March 1979
1st Edition (Rev), September 1979
2nd Edition, November 1980
3rd Edition, August 1982
4th Edition, November 1982
5th Edition, January 1985

Printed in U.S.A.

The material in this manual is for informational purposes and is subject to change
without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may
appear in this manual.
The manuscript for this book was created on a Digital Word Processing System
and, via a translation program, was automatically typeset on Digital's DECset
Integrated Publishing System. Book production was done by Educational Services
Development and Publishing in Marlboro, MA.
The following are trademarks of Digital Equipment Corporation:

mamaoma

DEC
DECmate
DECUS
DECwriter
DIBDL
LSI-11
MASSBUS

Micro PDP-11
MicroVAX
PDP

P/DS
Professional
Q-Bus
Rainbow
RSTS

RSX
RT
UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS
VOLUME I - SYSTEMS CONFIGURATIONS

GENERAL CONFIGURATION RULES ..................................................................... 1
GENERAL CONFIGURATION RULES ........................................................ 1
MEMORy ..................................................................................................... 6
REFRESH CONFIGURATION PROCEDURE ........................................... 11
MICRO/pDP-11 SYSTEM ...................................................................................... 21
GENERAL .................................................................................................. 21
PDP-11V03 AND PDP-11T03 SYSTEMS .............................................................. 35
PDP-11 V03 ................................................................................................. 35
PDP-11T03 ................................................................................................. 43
PDP-11T03-L AND PDP-11 V03-L SySTEMS ........................................................ 49
PDP-11 T03-L ............................................................................................. 49
PDP-11 V03-L ............................................................................................. 54
PDP-11V23 AND PDP-11T23 SYSTEMS .............................................................. 63
PDP-11 V23 SYSTEM ................................................................................ 63
PDP-11T23 SySTEM ................................................................................. 73
PDP-11/03-BASED MINC/DECLAB-11/MINC SYSTEMS .................................... 81
MODULAR INSTRUMENTATION COMPUTER (MINC) ........................... 81
DECLAB-11/MNC SYSTEM ...................................................................... 91
PDP-11/23-BASED MINC/DECLAB-11/MINC SYSTEMS .................................. 101
MINC ........................................................................................................ 101
DECLAB-11/MNC PDP-11 /23-BASED SYSTEM ................................... 112
PDP-11/23 PLUS SYSTEM .................................................................................. 123
GEN ERAL ................................................................................................ 123
COMPONENTS ........................................................................................ 124
PDP-11/23S SYSTEM .......................................................................................... 135
KDF11-B PROCESSOR MODULE (CPU) (M8189) ................................ 137
KDF11-B LED INDiCATORS ................................................................... 139
MSV11-D MOS RAM MEMORy ............................................................. 141
EXPANSION RULES ............................................................................... 145

iii

CONTENTS (Cont)
PDP-11/23 PLUS, MICROjPDP-11 AND MicroVAX EXPANSION ..................... 151
GENERAL ................................................................................................ 151
VT103 LSI-11 VIDEO TERMINAL ........................................................................ 157
GENERAL ................................................................................................ 157
LSI-11 BACKPLANE ................................................................................ 159
CONFIGURATION ................................................................................... 160
STANDARD TERMINAL PORT ............................................................... 160
VT1X3-MM MAINTENANCE MODULE (M8208) .................................... 162
11 MDS-A MICROCOMPUTER DEVELOPMENT SYSTEM ................................ 165
GENERAL ................................................................................................ 165
SPECiFiCATIONS .................................................................................... 167
CONFIGURATION ................................................................................... 169
SYSTEM VERIFICATION PROGRAM .................................................... 185
COMMERCIAL SYSTEMS ................................................................................... 189
D315 DATASYSTEM ............................................................................... 189
D322 ......................................................................................................... 211
D324 ......................................................................................................... 222
D325 ......................................................................................................... 232
D333C ...................................................................................................... 235
D335C ...................................................................................................... 237
D336C ...................................................................................................... 239
DPM23 DISTRIBUTED PLANT MANAGEMENT SySTEM .................... 243
LABORATORY SYSTEMS ................................................................................... 257
PDP-11 L03 ............................................................................................... 257
TELEPHONE COMPANY SYSTEM ..................................................................... 269
CC1 A PDP-11 V03 SYSTEM .................................................................... 269

OPTIONS

GENERAL MODULE INFORMATION .................................................................. 291
BA11-M MOUNTING BOX ................................................................................... 292
BA11-N MOUNTING BOX .................................................................................... 304
CONFIGURATION ................................................................................... 306

CONTENTS (Cont)
BA11-S MOUNTING BOX .................................................................................... 325
GENERAL ................................................................................................ 325
POWER SUPPLy ..................................................................................... 328
FRONT PANEL SWITCHES AND INDiCATORS .................................... 333
FRONT PANEL BEZEL ........................................................................... 334
H9276 BACKPLANE ................................................................................ 335
EXPANSiON ............................................................................................. 338
BA11-VA MOUNTING BOX .................................................................................. 341
GENERAL ................................................................................................ 341
H349 DISTRIBUTION PANEL .............................................................................. 345
GENERAL ................................................................................................ 345
H780 POWER SUPPLY ........................................................................................ 347
H786/H7861 POWER SUPPLiES ......................................................................... 352
SPECiFiCATIONS .................................................................................... 352
H7864 POWER SUPPLy ......................................... ,............................................ 355
SPECiFiCATIONS .................................................................................... 355
H9275 BACKPLANE ............................................................................................. 358
GENERAL ................................................................................................ 358
SPECiFiCATIONS .................................................................................... 359
CONFIGURATION ................................................................................... 360
INSTALLATION ........................................................................................ 362
H9276 BACKPLANE ............................................................................................. 364
GENERAL ................................................................................................ 364
SPECiFiCATIONS .................................................................................... 365
CONFIGURATION ................................................................................... 366
H9278-A BACKPLANE ......................................................................................... 368
GENERAL ................................................................................................ 368
MMV11-A CORE RAM MEMORy ........................................................................ 377

CONTENTS (Cont)
VOLUME II - MODULE OPTIONS

AAV11-A DIGITAL-TO-ANALOG CONVERTER .................................................. 381
AAV11-C DIGITAL-TO-ANALOG CONVERTER .................................................. 386
CONFIGURATION ................................................................................... 386
PROGRAMMING THE AAV11-C ............................................................. 388
I/O INTERFACE ....................................................................................... 390
ADV11-A ANALOG-TO-DIGITAL CONVERTER .................................................. 392
ADV11-C ANALOG-TO-DIGITAL CONVERTER .................................................. 397
CONFIGURATION ................................................................................... 399
CSR BITS ................................................................................................ 402
DATA BUFFER REGiSTER ..................................................................... 403
I/O INTERFACE ....................................................................................... 404
AXV11-C ANALOG INPUT/OUTPUT ................................................................... 405
CONFIGURATION ................................................................................... 407
CSR BITS ................................................................................................ 411
DATA BUFFER REGiSTER ..................................................................... 413
DAC A AND DAC B REGiSTERS ........................................................... 414
I/O INTERFACE ....................................................................................... 414
BCV1X BUS TERMINATOR, DIAGNOSTIC AND
BOOTSTRAP MODULES ..................................................................................... 415
BDV11 BUS TERMINATOR, BOOTSTRAP AND
DIAGNOSTIC ROM .............................................................................................. 425
BDV11 HALT/ENABLE, RESTART,
AND BEVNT SWITCHES ........................................................................ 431
DEQNA INTERFACE (ETHERNET) ...................................................................... 441
GENERAL ................................................................................................ 441
PREINSTALLATION VERIFICATION ...................................................... 444
M7504 MODULE ..................................................................................... 446
DEQNA BOOT SEQUENCE .................................................................... 450
DHV11 8-LlNE ASYNCHRONOUS MULTIPLEXER ............................................ 453
GENERAL ................................................................................................ 453
MODULE INSTALLATION ....................................................................... 461
CABLES AND CONNECTORS ................................................................ 463
DLV11 SERIAL LINE UNIT .................................................................................. 473

CONTENTS (Cont)
DLV11-E ASYNCHRONOUS SERIAL LINE INTERFACE ................................... 483
DLV11-F ASYNCHRONOUS SERIAL LINE INTERFACE ................................... 498
DLV11-J SERIAL LINE UNIT ............................................................................... 511
DLV11-KA EIA TO 20 MA CONTROLLER .......................................................... 533
CONFIGURATION ................................................................................... 533
DMV11 SYNCHRONOUS CONTROLLER ........................................................... 539
DMV11 OPTIONS .................................................................................... 539
CONFIGURATION ................................................................................... 542
CSR BITS ................................................................................................ 556
DPV11 SERIAL SYNCHRONOUS INTERFACE .................................................. 563
CONFIGURATION ................................................................................... 565
RECEIVE CONTROL STATUS REGISTER (RXCSR) ............................ 568
RECEIVE DATA AND STATUS REGISTER (RDSR) .............................. 574
PARAMETER CONTROL SYNC/ADDRESS REGISTER (PCSAR) ....... 579
PARAMETER CONTROL AND CHARACTER
LENGTH REGISTER (PCSCR) ................................................................ 583
TRANSMIT DATA AND STATUS REGISTER (RDSR) ........................... 590
DRV11 PARALLEL LINE UNIT ............................................................................ 595
DRV11-B GENERAL PURPOSE DMA INTERFACES ......................................... 601
DRV11-J GENERAL PURPOSE PARALLEL LINE INTERFACE ........................ 605
DRV11-P FOUNDATION MODULE ...................................................................... 619
DUV11-DA SYNCHRONOUS SERIAL LINE INTERFACE .................................. 632
DZV11 ASYNCHRONOUS MULTIPLEXER ......................................................... 644
FPF11 FLOATING POINT PROCESSOR ............................................................ 655
GENERAL ................................................................................................ 655
CONFIGURATION ................................................................................... 655
G7272/M8659 LSI-11 GRANT CARDS ................................................................ 659
IBV11-A LSI-11 INSTRUMENT BUS INTERFACE .............................................. 661
KD11 LSI-11 PROCESSOR MODULES .............................................................. 667

vii

CONTENTS (Cant)
KDF11-AX 11/23-A M ICROCOM PUTER ............................................................. 680
. KDF11-BA 11/23-B MiCROPROCESSOR ........................................................... 692
GENERAL ................................................................................................ 692
CONFIGURING THE KDF11-BA ............................................................. 693
FACTORY SWITCH AND JUMPER CONFIGURATIONS ...................... 716
KPV11-A POWER FAIL/LINE TIME CLOCK (LTC) ............................................. 720
-B 120 Q TERMINATOR
-C 250 Q TERMINATOR
KUV11-AA WRITABLE CONTROL STORE ......................................................... 725
KWV11-A PROGRAMMABLE REAL-TIME CLOCK ............................................ 730
KWV11-C PROGRAMMABLE REAL-TIME CLOCK ............................................ 740
CONFIGURATION ................................................................................... 741
CSR BITS ................................................................................................ 747
BUFFER/PRESET REGISTER ................................................................ 751
I/O INTERFACE ....................................................................................... 751
KXT11-A SBC-11/21 SINGLE-BOARD COMPUTER .......................................... 752
GENERAL ................................................................................................ 752
CONFIGURATION ................................................................................... 753
ODT ROMs .............................................................................................. 761

VOLUME III - MODULE OPTIONS

LAV11 PRINTER INTERFACE ............................................................................. 767
LPV11 LP05/LA180 INTERFACE MODULE ........................................................ 772
LSI-11/2 PROCESSOR MODULE DESIGNATIONS ........................................... 779
MCV11-D CMOS READ/WRITE MEMORY ......................................................... 783
GENERAL ................................................................................................ 783
CONFIGURING THE MCV11-D MEMORY MODULE ............................ 784
MRV11-AA READ-ONLY MEMORY .................................................................... 789
MRV11-BA ULTRAVIOLET PROM-RAM ............................................................. 793
MRV11-C READ-ONLY MEMORY MODULE ...................................................... 803

viii

CONTENTS (Cont)
MRV11-D UNIVERSAL PROM MODULE ............................................................ 815
GENERAL ................................................................................................ 815
MSV11-B READ/WRITE MEMORY ..................................................................... 825
MSV11-C MOS READ/WRITE MEMORy ............................................................ 828
MSV11-D,E MOS READ/WRITE MEMORY ........................................................ 833
MSV11-L MOS READ/WRITE MEMORY ............................................................ 838
GENERAL ................................................................................................ 838
MSV11-L POWER .................................................................................... 838
CONFIGURATION ................................................................................... 841
MSV11-P MOS MEMORy .................................................................................... 849
GENERAL ................................................................................................ 849
CONFIGURATION ................................................................................... 851
CONTROL STATUS REGISTER (CSR) BIT ASSiGNMENT .................. 857
MXV11-AA,AC MULTIFUNCTION MODULE ....................................................... 860
CONFIGURING THE SERIAL LINE UNITS ............................................ 872
MXV11-B MULTIFUNCTION OPTION MODULE ................................................ 884
GENERAL ................................................................................................ 884
RKV11-D BUS INTERFACE FOR RKV11-D DISK
DRIVE CONTROLLER .......................................................................................... 914
RLV11 CONTROLLER MODULES ...................................................................... 930
RLV12 DISK CONTROLLER ................................................................................ 943
CONFIGURATION ................................................................................... 945
CONTROL STATUS REGISTER (CSR) .................................................. 949
BUS ADDRESS REGISTER (BAR) ......................................................... 952
DISK ADDRESS REGISTER (DAR) ........................................................ 953
MULTIPURPOSE REGISTER (MPR) ...................................................... 956
BUS ADDRESS EXTENSION REGISTER (BAE) ................................... 960
RODX1 AND EXTENDER CONTROLLER MODULE
(RX50, RD51, RD52) ............................................................................................. 961
LOGICAL UNIT NUMBER SELECTION ................................................. 963
RODX1 EXTENDER MODULE INSTALLATION ..................................... 966
RODX1-E EXTENDER MODULE OPTION ............................................. 966
RODX1-E EXTENDER MODULE INSTALLATION ................................. 966

CONTENTS (Cont)
RXV11 FLOPPY DISK INTERFACE ................................................. " .................. 973
RXV21 FLOPPY DISK CONTROLLER ................................................................ 982
TSV05 TAPE TRANSPORT AND BUS
INTERFACE/CONTROLLER ................................................................................ 996
GENERAL ................................................................................................ 996
VSV11 RASTER GRAPHICS SYSTEM .............................................................. 1007
GENERAL .............................................................................................. 1007
M7061-YA SYNC GENERATOR/CURSOR
CONTROL BOARD ................................................................................ 1009
M7062 MEMORY BOARD .................................................................... 1016
M7064 DISPLAY PROCESSOR MODULE ........................................... 1019

PERIPHERAL OPTIONS

RC25 8-INCH DISK DRIVE SUBSySTEM ......................................................... 1023
GENERAL .............................................................................................. 1023
SPECiFiCATIONS .................................................................................. 1029
HOW TO MODIFY THE UNIT SELECT
NUMBER PLUG .................................................................................... 1038
RD51 11 Mb WINCHESTER DISK DRIVE SUBSYSTEM ................................. 1043
GENERAL .............................................................................................. 1043
VARIOUS CONFIGURATIONS FOR EXPANSION
OF THE RD51 ........................ ;............................................................... 1046
RD5231 Mb WINCHESTER DISK DRIVE SUBSYSTEM ................................. 1053
GEN ERAL .............................................................................................. 1053
RK05 DISK DRIVE SUBSYSTEM ...................................................................... 1064
RL01/RL02 5.2/10.4 Mb CARTRIDGE DISK DRIVE UNIT ............................... 1070
RX01 FLOPPY DISK DRIVE. .............................................................................. 1074
RX02 FLOPPY DISK DRIVE. .............................................................................. 1077
RX50 FLOPPY DISK DRIVE SUBSYSTEM ....................................................... 1082
GENERAL .............................................................................................. 1082
SYSTEM AND EXTERNAL SUBSYSTEM
INTERCONNECT ................................................................................... 1087

CONTENTS (Cont)
TU58 TAPE CASSETTE UNIT ........................................................................... 1098
GENERAL .............................................................................................. 1098

APPENDICES

DIAGNOSTIC MEDIA AVAILABILITy ................................................................ 1105
FLOATING ADDRESSES/VECTORS ................................................................. 1125
LSI-11 BUS SPECIFICATION ............................................................................ 1127
GENERAL .............................................................................................. 1127
DATA TRANSFER BUS CyCLES ......................................................... 1137
DATI ....................................................................................................... 1139
DATOB ................................................................................................... 1142
DATIOB .................................................................................................. 1145
DMA PROTOCOL .................................................................................. 1148
INTERRUPTS ........................................................................................ 1151
CONTROL FUNCTIONS ........................................................................ 1157
BUS ELECTRICAL CHARACTERISTICS ............................................. 1160
SYSTEM CONFIGURATIONS ............................................................... 1164
FCC INFORMATION ........................................................................................... 1168
GENERAL .............................................................................................. 1168

LA V11 /M7949

LAV11 PRINTER INTERFACE

Amps
+5
0.5

Bus Loads
+ 12
0

AC
1.8

DC
1.0

Cables

BC 11 S (for LA 180)
7009087 (for Centronics line printer'''' models
101, 101A, 1010, 102A, and 303)

Standard Addresses
LACS
LADB

177514
177516

Vectors
200

Diagnostic Program
Refer to Appendix A.

Related Documentation

MRV11-BA LSI-11 UV PROM-RAM User's Manual (EK-MRV11-TM)
Field Maintenance Print Set (MP00354)
Microcomputer Processor Handbook (EB-18451-20)

Recommended PROM Types
DEC MRV11-BC Intel 2708
(DEC PN 23-00087-01)

1024 X 8-bit, MaS, tri-state, erasable,
ultraviolet (24-pin DIP)
793

MRV11-BA/M8021

"-l"J'1-"'L1'-'
0

HIGH BYTE
PROMS

~~::SYTE_

1ST 1K
PROMS

3RD ik
PROMS

2ND1K
PROMS

4TH 1K
PROMS

GGGO 0
GGGO
o-=.oW22

oc:J-o W20 } RAM ADDRESS
C>Cj<)W19
C>Cj<) W18 BANK 7 ENABLE.

PROM
ADDRESS
PROM
eNABLE

MRV 11·BA RAM Addressing

794

{o-c::::J-o W17

g:g:g=~~

~W14

{ o-c::::J-o W13
~:~~

MRV11-BA/M8021

JUMPER~

CIRCUITS
1256 10 [377 8 1 WORDS)

~~~~~~~~~
I

BYTE POINTER

0'" WRITE LOW BYTE (0:7 )

~~~~~~~
4K AND lK
SELECT

256 WORD
SELECT

1=0
R = I

R=O

}

[DATOS BUS CYCLES ONLY)

1 = WRITE HIGH
DECODEO BY ADDRESSING
AND CONTROL LOGIC

NOTES

1, Factorv configured address Hinge 20000 - 20377
2. I = Jumper Installed; R = Jumper removed
3. Wl0 romovtW '" RAM ENABLE
W10 instalhld '" RAM DISABLE

MRV 11-BA RAM Addressing

BITS ____ 17

'---y----"

•
DECODED BY PROM
INTEGRATED CIRCUITS

PROM SIZE 11K WITHIN 4K BANK)

DECODED BY ADDRESSING AND
CONTROL lOGIC. 1 K SEGMENTS
ARE ENABLED VIA Wl1-W14:

':ACTORY

PROM
SIZE
I'" 1

R=Q

NOTES:

JUMPER CONFIGURATION
Wll

W12

W13

W14

, ,

1. Factory configured addre$~ range = 140000·157777
2. I = Jumper installect R '" Jumper removed

MRV 11-BA PROM Addressing

795

,
,

,
,
,
,

MRV11-BA/M8021
RAM Addressing Summary
Memory Jumper Configuration
(I = Installed; R = Removed)
Address
Range (Octal)

000000-000777
001000-001777
002000-002777
003000-003777
004000-004777
005000-005777
006000-006777
007000-007777
010000-010777
011000-011777
012000-012777
013000-013777
014000-014777
015000-015777
016000-016777
017000-017777
020000-020777
021000-021777
022000-022777
023000-023777
024000-024777
025000-025777
026000-026777
027000-027777
030000-030777
031000-031777
032000-032777
033000-033777
034000-034777
035000-035777
036000-036777
037000-037777
040000-040777
041000-041777
042000-042777
043000-043777
044000-044777
045000-045777
046000-046777
047000-047777

Bank W3 W4 W5 Wfo W7 W8 W9 W19 W20

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
2
2
2
2
2
2
2
2

R
R
R
R
R
R
R
R

796

I
I
I
I
I
I
I
I

I
I
I
I

R
R
R
R
R
R
R
R

I
I
I
I

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

I
I
I
I
I
I
I
I

R
R
R
R
R
R
R
R

R
R
R
R

R
R

I
I

R
R

I
I

R
R

I
I

R
R
R
R
R
R
I

R
R

I
I

I
I
I
I

R
R

I
I

R
R
R
R

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

R
R
R
R
I
I
I
I

R
R
R
R

R
R
R
R
R
R
R
R
R
R
R
R
R

MRV11-BA/M8021
RAM Addressing Summary (Cont)
Address

Memory Jumper Configuration
(I = Installed; R = Removed)

Range (Octal)

Bank W3 W4 W5 W6 W7 we W9 W19 W20

050000-050777
051000-051777
052000-052777
053000-053777
054000-054777
055000-055777
056000-056777
057000-057777
060000-060777
061000-061777
062000-062777
063000-063777

2
2
2
2
2
2
2
2
3
3
3
3

064000-064777
065000-065777
066000-066777
067000-067777
070000-070777
071000-071777
072000-072777
073000-073777
074000-074777
075000-075777
076000-076777
077000-077777
100000-100777
101000-101777
102000-102777
103000-103777
104000-104777
105000-105777
106000-106777
107000-107777
110000-110777
111000-111777
112000-112777
113000-113777
114000-114777
115000-115777
116000- 116777
117000- 117777

3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

R
R
R
R
R
R
R
R
I
I

I
I
I
I
I
I
I
I

R
R
R
R
R
R
R

R
R
R

R
I
I

R
R
R
R
R
R
R
R
R

I
I
I
I

R
R
R
R
I
I
I
I

R
R

I
I
I
I
I
I
I
I
R
R

I
I
I
I

R
R
R

R
R

I
I

R
R
I
I
R
R

R
R
R

R
R
R
R

R
R
R

R
R
R
R
R

R
R
R

797

R
R

R
R
R

R
R
R
R
R

R
R

R
R
R
R
I
I
I
I

R
R
R
R

R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R
I

R
R
R
I
R
I
R
I
R
I
R
I

R
I
R
I
R
I
R
I

R
I
R
I

R
I
R
I
R
I
R
I
R
I

R
I
R
I

MRV11-BA/M8021
RAM Addressing Summary (Cont)
Address

Memory Jumper Configuration
(I = Installed; R = Removed)

Range (Octal)

Bank W3 W4 W5 W6 W7 W8 W9 W19 W20

120000-120777
121000-121777
122000-122777
123000-123777
124000-124777
125000-125777
126000-126777
127000-127777
130000-130777
131000-131777
132000-132777
133000-133777
134000-134777
135000-135777
136000-136777
137000-137777

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

140000-140777
141000-141777
142000-142777
143000-143777
144000-144777
145000-145777
146000-146777
147000-147777
150000-150777
151000-151777
152000-152777
153000-153777
154000-154777
155000-155777
156000-156777
157000-157777
160000-160777
161000-161777
162000-162777
163000-163777
164000-164777
165000-165777
166000-166777

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7"
7"
7"
7"
7"
7"
7"

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

I
I
I
I
I

R
R
R
R
R
R
R
R

I
I

R
R
R
R
R
R
R

I
I
I
I

R
R
R
R
I
I
I
I

R
R
R
R

R
R

I
I

R
R

I
I

R
R

I
I

R
R

R
R
R
R
R
R
R
R
I

R
R

I
I

R
I

R
R
R
R

R
R

I
I

R
R

I
I

R
R

R
R
R
R
R
R
R
R

I
I
I
I

R
R
R
R

R
R

I
I

I
I
I
I
I
I

I
I
I
I

R
R

I
I

R
R

R
R
R

R
R
R
R
R
R
R

"The bank 7 enable jumper W 18 is factory installed to allow addressing in
bank 7.
798

MRV11-BA/M8021
RAM Addressing Summary (Cont)
Address

Memory Jumper Configuration
(I = Installed; R = Removed)

Range (Octal)

Bank W3 W4 W5 W6 W7 W8 Wg W19 W20

167000-167777
170000-170777
171000-171777
172000-172777
173000-173777
174000-174777
175000-175777
176000-176777
177000-177777

7'
7'
7'
7'
7'
7'
7'
7'
7'

R
R
R
R
R
R
R
R
R

R
R
R
R
R
R
R
R

I
I
I
I

R
R

I
I

R
R

R
R
R
R

I
I

R
R
R
R

'The bank 7 enable jumper W 18 is factory installed to allow addressing in
bank 7.

799

MRV11-BA/M8021
NOTE
The following jumper configurations illustrate configuring the
address range in banks above bank 7 (not implemented in present LSI-11 system configurations). W8, W9, W19, and W20
can be configured as shown in the preceding pages to select
the desired segment within the bank.
Address

Memory Jumper Configuration
(1=lnstalled; R=Removed)

Range (Octal)

Bank

200000-217777
220000-237777
240000-257777
260000-277777
300000-317777
32000D-337777
340000-357777
360000-377777
400000 - 4177 77
420000-437777
440000-457777
460000-477777
500000-517777
520000-537777
540000-557777
560000-577777
600000-617777
620000-637777
640000-657777
660000-677777
700000-717777
720000-737777
740000-757777
760000-777777

10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

I
I
I
I
I
I
I
I

R
R
R
R
R
R
R
R

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

I
I
I
I
I
I
I
I

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

R
R
R
R
R
R
R
R

I
I
I
I

I
I

R
R

R
R
R
R

I
I

R
R

800

R
R

R
R
R

I
R
R
R
R
R
R
R
R
R

MRV11-BA/M8021
PROM Addressing Summary
Address

Memory Jumper Configuration
(I = Installed; R = Removed)

Range (Octal)

Bank

000000-017777
020000-037777
040000-057777
060000-077777
100000-117777
120000-137777
140000-157777
160000-177777
200000-217777
220000- 237777
240000-257777
260000- 277777
300000-317777
320000-337777
340000-357777
360000-377777
400000 - 4 17777
420000-437777
440000-457777
460000-477777
500000- 517 7 77
520000-537777
540000-557777
560000-577777
600000-617777
620000-637777
640000-657777
660000-677777
700000-717777
720000-737777
740000-757777
760000-777777

0
1
2
3
4
5
6
7"
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

W15

Wl7

W16

I
I
I
I
I
I
R
R
R
R
R
R
R
R
I
I
I
I
I
I
I
I
R
R
R
R
R
R
R
R

R
R
R
R
I
I
I
I
R
R
R
R
I
I
I
I
R
R
R
R
I
I
I
I
R
R
R
R
I
I
I
I

R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I

R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I

"The bank 7 enable jumper W18 is factory installed to allow
addressing in bank 7.

801

MRV11-BAjM8021
PROM Addressing
Address*
Octal Binary

0
2
4
6

10
12
14

10090807060504030201 Address Bits
2223 1 2 3 4 5 6 7 8 PROM Pins

00000000000 L
00000000010 L
00000000100 L
00000000110 L
00000001000 L
00000001010 L

L
L
L
L
L
L

3776 11111111110 H H

L
L
L
L
L
L

H H H H H

L
L
L
L

L L
L H
H L Actual Logic

H
H

L L (1024 10
L H Locations)

H H

Levels Required

H H H

'Bus address bit 0 is not used. Therefore, only even-numbered addresses
are shown.

802

MRV11-C/M8048

MRV11-C READ-ONLY MEMORY MODULE

The MRV11-C is a flexible, high-density ROM module used with the LSI-11
bus. The module contains 129 wirewrap pins and 16 24-pin ROM chip sockets that use a variety of user-supplied ROM chips. Masked ROMs, fusible
link ROMs and ultraviolet erasable PROMs are acceptable to use. The
MRV11-C is shipped without jumpers installed.
Using 4K X 8 ROM chips, the total capacity of one M8048 module can be
64K bytes, accessible either by direct access or window mapping.

Amps
+5
0.8

+12

Bus Loads

Cables

AC
2

None

(plus ROM chip power)

Standard Addresses
Recommended window starting address 760000
Bootstrap starting address: 16-bit system 173000; 18-bit system 773000
Technical detailed information is beyond the scope of this manual. Additional information can be found in the Microcomputer Processor Handbook,
EB-18451-20.

Related Documentation
MRV11-D Universal PROM Module User Guide (EK-MRV1D-UG-001)
Field Maintenance Print Set (MP-00871)

803

MRV11-CjM8048
Compatible UV PROMs (Ultraviolet)
UV PROMs

Chip Array Size

Maximum Memory Size

Intel 2758
Intel 2716
Intel 2732
Mostek MK2716
T.I. TMS 2516
T.I. TMS 2532

1K X 8
2K X 8
4K X 8
2K X 8
2K X 8
4K X 8

16K bytes
32K bytes
64K bytes
32K bytes
32K bytes
64K bytes

Compatible PROMs
PROM

Chip Array Size

Maximum Memory Size

Intel 3628
Signetics 82S 2708
Signetics 82S 181
Signetics 82S 191

1K X 8
1K X 8
1K X 8
2K X 8

16K bytes
16K bytes
16K bytes
32K bytes

804

MRV11-CjM8048

J129
J128
J127
J126
J125
J124
J123
J122
J121
J120
J119
J11B
J1 17
J116
J115
J114
J113
J112
J111
Jll0
J109
J108
J107
J100
J105
J104
J103
J102
J101
J100
J99
J98

J97
J96
J95
J94
J93
J92

mDmDomo
J89"

""
"
""
"
)..

J88~
J85~ K

J87
XE44
CHIP
SET 0
HIGH
BYTE

XE38
CHIP
SET 1
HIGH
BYTE

XE26
CHIP
SET 3
HIGH
BYTE

XE32
CHIP
SET 2
HIGH
BYTE

)..

J83'-.." "

J81~ ~

J79_).. )..

J77-~ ~
J75-;;).. )..
J73
).;

)..
)..
)..

"
)..

)..

)..
)..

XE43
CHIP
SET 0
LOW
BYTE

XE37
CHIP
SET 1
LOW
BYTE

)..

XE31
CHIP
SET 2
LOW
BYTE

XE25
CHIP
SET 3
LOW
BYTE
)..

)..
)..
)..

)..
)..

)..
)..
)..
)..

J52

J55 )..)..
)..

J50=::::::::::)..)..
XE42
CHIP
SET 4
HIGH
BYTE

XE36
CHIP
SET 5
HIGH
BYTE

XE24
CHIP
SET 7
HIGH
BYTE

XE30
CHIP
SET 6
HIGH
BYTE

J48_~~

J46-)..)..

J44--~~
J42~

)..

J38

)..

)..1

J35)"~

)..

J32A~

J78
J76
J74
J72
J71
J70
J69
J65
J63
J61
J59
J57
J56
J54
J53
J51
J49
J47
J45
J43
J41
J40
J39
J37
J36

J29)"*
XE41
CHIP
SET 4
LOW
BYTE

XE35
CHIP
SET 5
LOW
BYTE

XE29
CHIP
SET 6
LOW
BYTE

XE23
CHIP
SET 7
LOW
BYTE

J24

J26)"~

J23~
J22_~
J21--)..
J20---)..
J19::::=:{
J18.-/').. A
J17
)..
J15/).. h

J13/~ 1

J11/
J9

)..
)..
)..

)..
)..

J14
J12
J10
J8
J7
J6

J5---;.
J4-)..

)..

,,_J91
)..-J90

A
h

)..

NOTE:

J86
J84
J82
J80

SEE TABLE 16 FOR WIREWRAP PIN IDENTIFICATION.

MRV 11-C Wirewrap Pin Locations

805

J3
J2
J1

MA-3083

s:
lJ

DAL 0-15

J24

J22

~ DBl

+5 VDC---O

Y85

BOOT

J23

YB4!

DRIVERS

::~I I

J113

J112

J115

J116

All

A12
+5

J f 17
VDC~

J111

'All

~ENABLE

......

MEMORY

CSA ADDRESS

J93

A12

<
......

o,J:Io

J92 _
BIT 1

BIT 2
BIT 3

BIT 4

BUS
ADDRESS
INTERFACE

~ I

BINARY
DECODE R

BIT 12
BIT 11

BIT 10

SELC

CEO

BIT 9

SELB

CEl

BIT 8

SELA

CE2

~ CONTROL
DAL 0-15

CE3

STATUS

REG.

BIT 4

CE4

CE5

m
DBl

LOW

YB5

DB2

!~6E

YB4

DB3 DIRECT

JB7

J86

CEO
CEl
CE2

J81

J80

J79

J78

CE3
CE4
CE5

CE6

CE7

YBl

OB4 ADDRESS YB21----..J
OB5
WINDOW

DRIVERS

E~I~~~~~
DIRECT

YB31-------'

J69

J71

ENABLE

ADDRESS~A~>:~(O

LATCH

MRV 11-C Configuration Interconnections

MRV11-C/M8048

WINDOW
MAPPING

END
MA-3879

Configuration Procedure

807

MRV11-C/M8048
Wirewrap Pin Identification
Wirewrap Pin
Designation

Function

J1
J2
J3
J4
J5
J6
J7
J8
J9
J 10
J 11
J 12
J 13
J 14
J 15
J 16
J 17
J 18
J 19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
J41
J42
J43

RXGX pull-up resistor
RXGX optional capacitor
RXGX signal
LMATGH input for BDOUT control
LMATGH for BDOUT control
Window address enable ground
Window address enable
High byte chip enable bit A 11
GSR high byte bit 8 chip enable output
High byte chip enable bit A 12
GSR high byte bit 9 chip enable output
High byte chip enable least significant bit
GSR high byte bit 10 chip enable output
High byte chip enable intermediate bit
GSR high byte bit 11 chip enable output
High byte chip enable most significant bit
GSR high byte bit 12 chip enable output
Boot address chip enable bit A 11
Boot address chip enable bit A 12
Boot address chip enable least significant bit
Boot address chip enable intermediate bit
Boot address chip enable most significant bit
Boot address chip enable ground reference
Boot address chip enable 5 V reference
Direct address bit 11 chip enable output
Low byte chip enable A 11 bit
GSR low byte bit 0 chip enable output
Direct address bit 12 chip enable output
Low byte chip enable A 12 bit
GSR low byte bit 1 chip enable output
Direct address bit 13 chip enable output
Low byte chip enable least significant bit
GSR low byte bit 2 chip enable output
Direct address bit 14 chip enable output
Low byte chip enable intermediate bit
GSR low byte bit 3 chip enable output
Direct address bit 15 chip enable output
Low byte chip enable most significant bit
GSR low byte bit 4 chip enable output
Reserved for future DIGITAL use.
Window address bit 15 compare ground
Window address bit 13 compare input
Window address bit 12 compare ground

808

MRV11-C/M8048
Wirewrap Pin Identification (Cont)
Wirewrap Pin
Designation

Function

J44
J45
J46
J47
J48
J49
J50
J51
J52
J53
J54
J55
J56
J57
J58
J59
J60
J61
J62
J63
J64
J65
J66
J67
J68
J69
J70
J71
J72
J73
J74
J75
J76
J77
J78
J79
J80
J81
J82
J83
J84
J85
J86

Window address bit 14 compare input
Window address bit 14 compare ground
Window address bit 15 compare input
Window address bit 16 compare ground
Window address bit 16 compare input
Window address bit 13 compare ground
Window address bit 17 compare input
Window address bit 17 compare ground
Window address bit 12 compare input
Direct address 32K memory limit output
Direct address 16K memory limit output
Direct address memory limit input
Direct address 8K memory limit output
Direct address bit 17 compare ground
Direct address bit 16 compare input
Direct address bit 16 compare ground
Direct address bit 17 compare input
Direct address bit 15 compare ground
Direct address bit 15 compare input
Direct address bit 14 compare ground
Direct address bit 14 compare input
Direct address bit 13 compare ground
Direct address bit 13 compare input
CSR high byte bit 15 enable ground
CSR high byte bit 15 enable input
High byte chip enable window address function
High byte chip enable direct address function
High byte chip enable function select drivers
Bit 7 chip select enable input
Bit 7 chip enable decoder output
Bit 6 chip select enable input
Bit 6 chip enable decoder output
Bit 5 chip select enable input
Bit 5 chip enable decoder output
Bit 4 chip select enable input
Bit 4 chip enable decoder output
Bit 3 chip select enable input
Bit 3 chip enable decoder output
Bit 2 chip select enable input
Bit 2 chip enable decoder output
Bit 1 chip select enable input
Bit 1 chip enable decoder output
Bit 0 chip select enable input

809

MRV11-C/M8048
Wirewrap Pin Identification (Cont)
Wirewrap Pin
Designation

Function

J87
J88
J89
J90
J91
J92
J93
J94
J95
J96
J97
J98
J99
J100
J101
J102
J103
J104
J105
J106
J107
J108
J109
J110
J 111
J112
J113
J114
J115
J116
J117
J118
J119
J120
J121
J122
J123
J124
J125
J126
J127
J128
J129

Bit 0 chip enable decoder output
Boot address enable ground
Boot address enable
DAL 4 CSR address select signal
DAL 4 CSR address select ground
DAL 1 CSR address select signal
DAL 1 CSR address select ground
DAL 2 CSR address select signal
DAL 2 CSR address select ground
DAL 3 CSR address select signal
DAL 3 CSR address select ground
Pin 18 input for chip set 5
Chip wirewrap interconnection for chip set 5
Pin 20 input for chip set 5 (chip enable 5)
Pin 18 input for chip set 4
Chip wirewrap interconnection for chip set 4
Pin 20 input for chip set 4 (chip enable 4)
Pin 18 input for chip set 6
Chip wirewrap interconnection for chip set 6
Pin 20 input for chip set 6 (chip enable 6)
Pin 18 input for chip set 7
Chip wirewrap interconnection for chip set 7
Pin 20 input for chip set 7 (chip enable 7)
Reserved for future DIGITAL use.
ROM interconnection, ground reference
Chip enable bit bus input
Address bit A 11, used as chip input A 10
Chip interconnection loop (to wirewrap pins)
Address bit A 12, used as chip input A 11
Chip interconnection loop for chip pin 21
ROM interconnection +5 Vdc voltage reference
Pin 18 input for chip set 0
Chip wirewrap interconnection for chip set 0
Pin 20 input for chip set 0 (chip enable 0)
Pin 18 input for chip set 1
Chip wirewrap interconnection for chip set 1
Pin 20 input for chip set 1 (chip enable 1)
Pin 18 input for chip set 2
Chip wirewrap interconnection for chip set 2
Pin 20 input for chip set 2 (chip enable 2)
Pin 18 input for chip set 3
Chip wirewrap interconnection for chip set 3
Pin 20 input for chip set 3 (chip enable 3)

810

MRV11-C/M8048
Control and Status Register
Each MRV 11-C board uses one 16-bit control and status register located in
the system I/O page to determine mapping of ROM segments into windows
in the window mapped mode. The default address for this CSR is 177000
(777000 in the PDP-11 /23 system). The valid address range for CSRs is
177000 to 177036 (777000 to 777036 on PDP-11 /23s).
The CSR contains a 5-bit read/write field for each window. The number
stored in this field (0 to 31 10) selects the desired 2Kb region from the
MRV 11-C board to be associated with the window in question. CSR bits 0
through 4 control the mapping of the low address window, window O. The
low five bits of the upper byte (bits 8 through 12) control the mapping of
window 1.
The MRV 11-C optionally provides a window enable/disable capability.
When this option is selected, bit 15 of the CSR is used to enable or disable
window response under program control. When bit 15 is a 0, the board will
respond to references to the CSR or DATI or DATIO references to either of
the windows. When bit 15 is a 1, only the CSR will respond. If the enable/disable option is not selected, bit 15 of the CSR will be read only and
will always be O. The enable/disable bit has no effect on direct mode addressing or the bootstrap window capability. If enable/disable option is
used, bit 15 on system initializes, disabling the board.
Control and Status Register Addresses
CSR
Address

Bit 4
J90 to J91

Bit 3
J96 to J97

Bit 2
J94 to J95

Bit 1
J92 to J93

177000'
177002
177004
177006
177010
177012
177014
177016
177020
177022
177024
177026
177030
177032
177034
177036

R
R
R
R
R
R
R
R
I
I
I
I
I
I
I
I

R
R
R
R
I
I
I
I
R
R
R
R
I
I
I
I

R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I

R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I

R = jumper removed.

I = jumper installed .

• Default address

NOTE
Install J67 to J68 to allow the use of bit 15 of the CSR.
811

MRV11-C/M8048
MRV11-C Direct Addressing Starting Address
Starting
Address

Bit 17
Bank 57 to 60

Bit 16
59 to 58

Bit 15
61 to 62

Bit 14
63 to 64

Bit 13
65 to 66

0
20000
40000
60000
100000
120000
140000
160000

0
1
2
3
4
5
6
7

I
I
I
I
I
I
I
I

I
I
I
I
R
R
R
R

I
I
R
R
I
I
R
R

I
R
I
R
I
R
I
R

200000
220000
240000
260000
300000
320000
340000
360000

10
11
12
13
14
15
16
17

I
I
I
I
I
I
I
I

R
R
R
R
R
R
R
R

I
I
I
I
R
R
R
R

I
I
R
R
I
I
R
R

I
R
I
R
I
R
I
R

400000
420000
440000
460000
500000
520000
540000
560000

20
21
22
23
24
25
26
27

R
R
R
R
R
R
R
R

I
I
I
I
I
I
I
I

I
I
I
I
R
R
R
R

I
I
R
R
I
I
R
R

I
R
I
R
I
R
I
R

600000
620000
640000
660000
700000
720000
740000
760000

30
31
32
33
34
35
36
37

R
R
R
R
R
R
R
R

R
R

I
I
I
I
R
R
R
R

I
I
R
R
I
I
R
R

I
R
I
R
I
R
I
R

R
R
R
R
R
R

R = jumper removed.
I = jumper installed.

812

MRV11-C/M8048
Using Multiple Boards
Up to 16 MRV11-C boards may be configured in a single system. When multiple boards are present, each board has a unique control and status register address assigned in increasing order from 177000 (777000 in PDP11/23 systems). Each board can have a unique 4Kb area of the physical
address space set aside for its windows, but it is also possible to share
one 4Kb area of the address space among all MRV 11-C boards installed in
the system. This is done by using the enable/disable capability discussed
earlier. When enable/disable is implemented, the disable bit in the CSR will
be set automatically by BINIT on the bus or by execution of the RESET instruction. Therefore, the initial state of the system will have all boards disabled. To access a particular segment of ROM in this multiboard configuration, the programmer first enables the desired board and maps the
segment. When access to that segment is completed, the board is again
disabled to allow another board to be selected some other time.

Chip Enable Jumpers
Sockets Enabled

Chip Enable Signal Wirewrap Jumpered Pins

XE43, XE44
XE37, XE38
XE31, XE32
XE25, XE26
XE41, XE42
XE35,XE36
XE29,XE30
XE23,XE24

CE1
CE2
CE3
CE4
CE5
CE6
CE7

CEO

J86 to J87
J84 to J85
J82 to J83
J80 to J81
J78 to J79
J76 to J77
J74 to J75
J72 to J73

NOTE
J40 and J 110 are unused at this time.
ROM Chips
The ROM is provided by the user and consists of up to 16 chips that are
inserted into prewired sockets. The chips will be either 1K X 8 bit, 2K X 8
bit, or 4K X 8 bit ROMs. When the MRV11-C is fully populated, the result
will be either 16K, 32K, or 64K bytes of memory. These ROMs can be supplied by a variety of vendors and the basic configuration for many of the
ROMs is standardized except for pins 18, 19, 20, and 21. The configuration
of these pins will vary depending upon the size of the ROM and the vendor
who supplies them. The user should verify the vendor's specifications in
order to determine if a particular ROM can be used on the MRV 11-C.

813

MRV11-C/M8048
The MRV 11-C module is configured so that the user can select the signals
that are applicable to pins 18, 19, and 21. The board provides wirewrap
pins for the user to select the A 11, A 12, 5 Vdc or ground. There are three
individual loops that interconnect all chips and three wirewrap pins available for each individual chip. Wirewrap pin J 112 interconnects pin 19 of all
the chips and pin J 116 interconnects pin 21 of all the chips; these are normally designated as the A 10 or A 11 inputs to the chips.
Wirewrap pin J 114 interconnects wirewrap pins that are individually associated with each chip. Pin 18 of each chip is individually wired to a wirewrap pin and chip pin 20 is wired to the chip enable signal. Chip pin 20 is
also individually wired to a wirewrap pin. The user must determine from the
vendor's specifications which signals apply to which pins and must install
jumper wires as needed to configure an operational module.

INTEL 2716

INTE L 2732

PIN CONFIGURATION

Vee

All

____ TO A12 H

Vpp ___ TO +5 VDC

__ TO CE

OE ---- TO CE

OElVpp

A l O - TO All H

AlO

a _ TOGE

u - TO DE
07

___ TO All H

GND

2K X 8 ROM

4K X 8 ROM

MRV 11-C ROM Pin Configuration Sample

814

MRV11-D/M8578

MRV11-D UNIVERSAL PROM MODULE

GENERAL

The MRV11-D is a flexible, high density, dual size module used with the LSI-11
bus. The module contains 41 jumper posts, 2 switch packs, and 16 28-pin memory
chip sockets. A variety of user ROMs, such as fusible link PROMs, ultraviolet
eraseable (UV E) PROMs, and masked ROMs are acceptable to use. The module
is shipped from the factory with all jumpers installed.
The MRV11-D accepts several densities, up to and including 32K by 8; with 16 32K
devices, memory capacity is 512K bytes.
Amps

+5
1.6

Bus Loads

+12

AC
2

(plus ROM chip power)
Standard Addresses

Recommended page mode
Window 0 is addressed between 17773000 and 17773776
Window 1 is addressed between 17765000 and 17765776
PCR address is fixed at location 1777520
Page mode PCR is used configured between 17777000 and 1777036.
Console octal debugging technique (ODT)
Terminal addresses used by console ODT addresses
16-bit addressing = 177560 - 177566
18-bit addressing = 777560 - 777566
22-bit addressing = 1777560 - 1777566
Detailed technical information is beyond the scope of this manual. For more
information, refer to the Microcomputer Processor Handbook, EB-18451-20.

815

MRV11-D/M8578
Diagnostic Programs
None
Related Documentation
MRV11-0 Universal PROM Module User Guide (EK-MRV1D-UG)
Field Maintenance Print Set (MP-00566)
PROM Sizes and Pinouts
The MRV11-0 contains 16 28-pin sockets to house the various PROMs and static
RAM devices that can be used in the module. The sockets can house 2K by 8, 4K
by 8, 8K by 8, 16K by 8, and 32K by 8 PROMs. In addition, the bottom half of the
socket array (chip sets 0 through 3) can accommodate static RAM. The 2K by 8
and 4K by 8 PROMs contain 24 pins while the others contain 28 pins.
F.
POWER JUMPERS

~-"-"'-'-·E.

DEVICE SIZE JUMPERS*

STANDARD DECODER
~n"c;;-.l'- PATTERN SELECT
JUMPERS

XE4Q

XE42

XE41

XE43

K.
STARTING ADDRESS
SWITCHES

B.
SYSTEM SIZE JUMPER

A.
-_-'=d...'==-.!..BATTERY BACKUP

r~~UNT

READ TIMING
JUMPER

DATO JUMPER

04-- J14
0+-- J13

*04-J12
04-Jl1
0+-- J10

MRV11-0 (M8578) Jumper and Switch Locations
816

MRV11-D/M8578
A.
BATTERY BACKUP SHUNT
DESCRIPTION

JUMPER CONNECTION
~OOHMSHUNT

0606
r&--

SHIPPED CONFIGURATION. NO BATTERY BACKUP ON
SYSTEM; +5V ONLY

0 OHM SHUNT

6060

BATTERY BACKUP PROTECTION FOR RAMS

NOTE
INSTALL Wl OR W2 BUT NOT BOTH.

1j I "m:~'" """""

B.
SYSTEM SIZE JUMPERS (W3)
JUMPER CONNECTION

DESCRIPTION

66 0

J22
SPECIFIES 16·BIT OR lB·BIT SYSTEM.

J21

J21 J22 J23
W3

066

SPECIF IES 22·BIT SYSTEM.

J21 J22 J23

JUMPER CONNECTION

DESCRIPTION

C.
ROM/RAM SELECTION JUMPERS (W4. W5)
HI BYTE
W5

J3B

J37

OJ36
LO BYTE
W4

THIS CONFIGURATION IS USED FOR ALL ROM MEMORY
(NO RAM). BOTH JUMPER CLIPS (W4 AND W5) MUST BE
INSERTED IN THE UPPERMOST PINS.

J32

J31

OJ30
HI BYTE
OJ3B
W5

J37

J36

LO BYTE
OJ32
J31

~ J30
817

THIS CONFIGURATION IS FOR ROM/RAM MEMORY.
RAM IS INSTALLED IN CHIP SETS 0 THROUGH 3
(BOTTOM HALF OF ARRAY). WHEN RAM IS INSERTED.
BOTH JUMPER CLIPS MUST BE INSTALLED IN THE
LOWER PINS.

MRV11-D/M8578
D.
DATOJUMPER CONNECTION (W6)
JUMPER CONNECTION

DESCRIPTION

660

CAUSES BUS TiMEOUT WHEN ACCESSED BY DATD
CYCLE. NOT USED WHEN RAM IS INSTALLED.

J15 J16 J17
W6

WITH RAM INSTALLED, USE THIS CONFIGURATION
WHICH WILL RESPOND TO DATD CYCLES.

066

J15 J16 J17
NOTE
THE PCR OR THE BOOTSTRAP PCR WILL NOT
TIMEOUT IN EITHER CONFIGURATION WHEN
ACCESSED BY DATO CYCLES. EITHER JUMPER
CONNECTION MAY BE USED, BUT THE CLIP
MUST BE INSTALLED TO ALLOW ANY DATO
CYCLE ON THE MODULE.

E.
DEVICE SIZE JUMPERS (W7, WB)

THE TABLE BELOW REFLECTS THE REV C AND REV 0 ETCH CONFIGURATION. THE ETCH AND
BOARD NUMBER IS LOCATED ON THE COMPONENT SIDE OF THE MODULE ALONG THE LEFT HAND SIDE.
501521 3C 50152130 -

REV C ETCH
REV 0 ETC

JUMPER CONNECTION
REVC
ETCH

REV D
ETCH
CHOOSES 2K BY B DEVICE ONLY

J14 0
TO PIN 41 (+5V)}
0
(WIRE WRAP)
---0 J13

0 J12
J11

W7
C

J10

:J
:J

J14
WBC:

J13

:JW8

0 J12
J11
W7C

CHOOSES 4K BY 8, 8K BY
8, OR 16K BY 8 DEVICES.

W7
:J

J10 0
CHOOSES 32K BY 8 DEVICES

J14
W8e

DESCRIPTION

J13 : J
J12 0

W7C

J11
J10

NOTE: A NEW ARRAY DECODER IS REQUIRED IF YOU USE 32K AND 16K
BY 8 DEVICES. USE DIFFERENT QUANTITIES THAN THOSE DESIGNATED
BY THE STANDARD DECODER, OR MIX 4K, 8K OR 16K BY 8 DEVICES.
TO MIX 4K, 8K OR 16K BY 8 DEVICES WITH 32K BY 8 DEVICES
YOU MUST PROPERLY CONFIGURE THE POWER JUMPERS FOR EACH ROW.
ROWS CONTAINING 32K BY 8 DEVICES MUST BE JUMPERED FOR ADDRESS
RATHER THAN POWER. (SEE TABLE 3-6)

818

MRV11-D/M8578
F.
POWER JUMPER CONNECTIONS
(W9,WlO,Wl1,Wl2)
DESCR IPTION

JUMPER CONNECTION
J41 gJ
W12·ROW4
J40
J390
J35 gJ W11·ROW3
J34
J330
J29gJ W10·ROW2
J2B
J270

THIS CONFIGURATION IS FOR 2K BY BAND 4K BY B ROMS
AND 8K BY 8 STATIC RAM. THE POWER JUMPER MAY BE IN
EITHER POSITION FOR THE 8K BY B ROM. THE POSITION
SHOWN PROVIDES +5V POWER TO PIN 26. THE CONFIGURING
IS DONE ON A ROW BY ROW BASIS. FOR EXAMPLE, IF 4K BY
B ROMS ARE INSTALLED IN ROWS 1,2,3 AND 16K BY B ROMS
ARE INSTALLED IN ROW 4, THE ROW 4 JUMPER WOULD BE
CONNECTED BETWEEN THE TWO LOWER PINS WHILE ALL
THE OTHER JUMPERS ARE CONNECTED AS SHOWN.

J26 gJ W9·ROW 1
J25
J240

J41 0
J40 gJ W12·ROW 4
J39
J350
J34
J33

W11ROW 3
FOR 16K BY 8 OR 32K BY B DEVICES, THE POWER JUMPER MUST
BE IN THIS POSITION. IN THIS POSITION, PIN 26 IS CONNECTED
BY AN ADDRESS LINE.

J290
J2B
J27

W10·ROW 2

J260
J25
J24

W9-ROW 1

G.
READ TIMING JUMPER (W13)
JUMPER CONNECTION

DESCRIPTION

W13

660

450 ns READ TIME (NORMAL).

J1BJ19J20

W13

066

J1BJ19J20

200 ns READ TIME (FASTl.IN THIS CONFIGURATION,
SPEED ADVANTAGE IS OBTAINED BUT THE SLOWEST
DEVICE INSTALLED ON THE BOARD MUST MEET THE
200 ns ACCESS TIME REOUI R EMENT.

819

MRV11-D/M8578
H.
ENABLE BOOTSTRAP JUMPER (W14)
DESCRIPTION

JUMPER CONNECTION

ENABLES BOOTSTRAP. ALLOWS 512 BYTES AT 17773000
(WINDOW 0). AND 512 BYTES AT 17765000 (WINDOW 1) TO
BE USED AS BOOTSTRAP. BOOTSTRAP PCR ADDRESS IS
17777520.

J6 cr-,
J5Q-JW14
J40
J60

DISABLES BOOTSTRAP ON MRVll·D. NONE OF THE ABDVE
LOCATIONS RESPOND.

J5cr-,W14
J4 o--J

MR·12881

I.
STANDARD DECODER PATTERN
SELECT JUMPERS (W15.W16)
DESCRIPTION

JUMPER CONNECTION
J9

J30

~W16

J9 0
JB
J7

J9
JB

~ W16

~W16

J7 0

J9
JB

~W16

J70

J2~ W15

2K BY B RDMS. 1/2 POPULATED

J3 ~W15
J2

2K BY B ROMS. FULLY POPULATED

Jl 0

J30
J2 ~
Jl
W15

J3
J2

4K BY B ROMS, FULLY POPULATED

~W15

BK BY B ROMS, FULLY POPULATED

Jl 0
MR-12882

J.
PCR ADDRESS SWITCHES
DESCRIPTION

SWITCH

NOTE
ORIENT MODULE WITH HANDLES FACING AWAY
AND FINGERS TOWARD YOU.

ON~DIR

[IJ[TI" PCR4
[TI'" PCR3
[TI .. PCR2
[TI .. PCRl

OF~PAGE

DIRECT/PAGE

PCR4,

PCR3,

PCR2,

PCRl

TO SELECT DIRECT MODE ADDRESSING, PUSH RIGHT
SIDE OF ROCKER SWITCH DOWN (SWITCH ON). TO
SELECT PAGE MODE ADDRESSING, PUSH LEFT
SIDE OF ROCKER SWITCH DOWN (SWITCH OFF).
THESE SWITCHES CONTROL THE ADDRESS OF THE
PAGE CONTROL REGISTER. THE SWITCHES ALLOW
ANY ADDRESS FROM 17777000 TO 17777036 TO BE
SELECTED ON EVEN WORD BOUNDARIES.
PUSHING DOWN THE RIGHT SIDE OF THE ROCKER
SWITCH PRODUCES A LOGICAL 0 (SWITCH ON).
PUSHING DOWN THE LEFT SIDE PRODUCES A
LOGICAL 1 (SWITCH OFF).

Default:

177770368

820

MRV11-D/M8578
K.
STARTING ADDRESS SWITCHES
SWITCH

[TI- SA21 MSB
[TI'" SA20

o:::J'" SA19
[TI ... SA18
[TIen SA17
[TI'" SA16
[TI . . . SA15
[TIm SA14

SA1··SAlO ROCKER SWITCHES.
PUSHING THE RIGHT SIDE OF THE
SWITCH DOWN TURNS THE SWITCH
ON (LOGIC 11. PUSHING THE LEFT
SIDE OF THE SWITCH DOWN TURNS
THE SWITCH OFF (LOGIC 01.

DESCRIPTION
SETS UP STARTING ADDRESS OF THE
MODULE. PERMITS ANY STARTING
ADDRESS FROM 0 TO 17770000 ON
4K BYTE BOUNDARIES ..

NOTE
MODULE IS ORIENTED WITH HANDLES FACING
AWAY AND FINGERS TOWARD YOU.

o:::J'" SA13
o:::Je SA12 LSB

The basic differences on the 2764, 27128, 27256, and static RAM are in the
functions of pins 26 and/or 27. The figure below shows these differences. For
example, on the 16K by 8 PROM (27128), pin 26 is used as an address pin (A13).
On the 32K by 8 PROM (27256), pins 26 and 27 are used as address pins (A 13 and
A14, respectively).

821

INTEL 2764 PIN CONFIGURATION
8K 8Y 8 PROM
INTEL 2716 PIN CONFIGURATION
2K BY 8 PROM
A,
A,

Vee
A,

Vee
PGM

Vee
A,

A,
A,
A,

A,
A"

A,
A,

A,
Ao

0,
0,
0,
0,
0,

00
0,
0,

0,
0,
0,
0,
0,

00
0,
0,
GND

eX)
I\)
I\)

INTEL 2732A PIN CONFIGURATION
4K BY 8 PROM

27128 PIN CONFIGURATION
16K BY 8 PROM

.---..

26PA"
As
A,

00
0,
0,
GND

GND

27256 PIN CONFIGURATION
32K 8Y 8 PROM

STATIC RAM

r--I

Vee
PGM

A,q3

GND

V"
A"
A,

Vee

A"
A13

CE,OR N.C.

As
A,

A,
A,

DE
A"

A,
A,

0,
0,
0,
0,
0,

00
0,
0,
GND

Compatible PROM Types

s:::D
<

-"
-"

......

MRV11-D/M8578
When installing a 24-pin PROM (2K by 8, 4K by 8) in a 28-pin socket, install it with
the notch on top and bottom justified. Pin 1 of the PROM inserts into pin 3 of the
socket. On 28-pin devices, pin 28 is the power pin. For 24-pin devices, pin 28 of
the socket must be strapped to pin 26 of the socket to provide power to the
device. The power jumpers strap these pins together, as shown in the following
figure.

Insertion of 24-Pin PROM Chips
NOTE
If you are using 24-pin devices such as the 2716 (2K by 8 PROM) on a
revision C etch board, you must wire-wrap J13 (Vpp) to J40 (pin 26 of
row 4). It is also necessary to jumper J40 to J41 (+S V). However, you
cannot use the jumper clip because a wire-wrap exists on J40. Therefore, you must wire-wrap, rather than jumper, J40 to J41. This procedure ensures proper read mode operation. On a revision 0 etch board,
you can install 2K by 8 PROMs without wire-wrap.

823

MRV11-D/M8578
Storage Capacity per ROM Chip Size and Number of Chips
Number of
Chips
Installed

(Capacity Measured in Kbytes)
2K by 8

4K by 8

8K by 8

16K by 8

32K by 8

2
4
6
8
10
12
14
16

4
8
12
16
20
24
28
32

8
16
24
32
40
48
56
64

16
32
48
64
80
96
112
128

32
64
96
128
160
192
224
256

64
128
192
256
320
384
448
512

Typical EPROMs
Chip Array
UV PROMs

Size

Maximum
Memory
Array Size

Intel 2716
Intel 2732
Intel 2764
Intel 27128

2K by 8
4K by 8
8K by 8
16K by 8

32 Kbytes
64 Kbytes
128 Kbytes
256 Kbytes

8K by 8
16K by 8
32K by 8
8K by 8
16K by 8
8K by 8
8K by 8
2K by 8
4K by 8

128 Kbytes
256 Kbytes
512 Kbytes
128 Kbytes
256 Kbytes
128 Kbytes
128 Kbytes
32 Kbytes
64 Kbytes

Masked ROMS
Mostek MK3700
NCR 23128
NEC 23256
National 52364
Signetics 23128
Synertek 2365
Synertek 2365A
Synertek 23168
Synertek 2333-3

824

MSV11-B/M7944

MSV11-B READ/WRITE MEMORY

Amps

+ 12

0.6
(1.12 max.)

0.3
(0.7 max.)

Bus Loads

Cables

AC
DC
1.89 1.0

none

Standard Addresses
Module is shipped with all jumpers installed, selecting bank 0 (0-17776).

Vectors, DEC/X11 Exerciser Program
None

Diagnostic Programs
Refer to Appendix A.

Related Documentation
Field Maintenance Print Set (MP00067)
Microcomputer Processor Handbook (EB-18451-20)

NOTES
1.

Only one dynamic memory module in a system is needed
to reply to the refresh bus functions initiated by the processor. The module selected should be the one with the
longest access time (usually the module electrically farthest from the refreshing device).

825

MSV11-B/M7944
NOTES (Cont)
2.

If a REV11 (M9400VA or VC) provides refresh, only the processor-resident memory (if present) should reply to refresh. If the processor board has no resident memory, the
memory module electrically farthest from the REV11
should reply.

Refer to the Refresh Configuration Procedures in the"Systems Configurations" section.

M7944 ETCH REV B

M7944 Etch Rev B

826

MSV11-B/M7944
BDAL

BITS

4096 LOCATION ADDRESS
W1

BYTE
POINTER

'-----'

4K ADDRESS
SPACE J UMPE RS
/

Bank

No.

Address
Range

Octal Address
Ri:\nge

0-4K

000000-017776

4-BK

020000-037776
040000-057776

8·12K
12-16K

16·20K
20-24K
24-28K
28·32K
NOTE:

I ~ Installed,

060000-077776
100000-117776
120000-137776
140000·157776
160000·177776

Removed

MR-5429

MSV11-B Address Format/Jumpers

NOTE
Because of addressing limitations, this module is not compatible with PDP-11/23 systems with more than 64K bytes of
memory_

MSV11-B Address Format/Jumpers
Reply to Refresh
Function

Reply
Don't reply

827

MSV11-C/M7955

MSV11-C MOS READ/WRITE MEMORY

Module

Model

Description

M7955-YA
M7955-YB
M7955-YC
M7955-YD

MSV11-CA
MSV11-CB
MSV11-CC
MSV11-CD

4K by 16-bit read/write memory
8K by 16-bit read/write memory
12K by 16-bit read/write memory
16K by 16-bit read/write memory

Amps

Bus Loads

Cables

+ 12
+5
1. 1
0.54
(2.0 max.) (0.56 max.)

AC
2.32

None

Standard Addresses
Module is shipped configured to start at bank O.

Vectors
None

Diagnostic Programs
Refer to Appendix A.

Related Documentation
MSV11-C User's Manual (EK-MSV11-0P)
Field Maintenance Print Set (MP00259)
Microcomputer Processor Handbook (EB-18451-20)

828

MSV11-C/M7955

S1
S2

S3 - 1 - - - - - l r - l
S4 _+---"n-l
S5
OFF~ON

W14 W15

W6 W2 W1 W5
W12

M7955/MSV11-C Jumpers
NOTES
1.

Only one dynamic memory module in a system is needed
to reply to the refresh bus transactions initiated by the
processor. The module selected should be the one with
the longest access time.

If a REV11 (M9400-YA or M9400-YC) provides refresh, only
the processor-resident memory (if present) should reply to
refresh. If the processor board has no resident memory,
the memory module electrically farthest from the REV11
should reply.

If MSV11-Cs are mixed with MSV11-Bs, the MSV11-Cs
should use internal refresh. Again, the memory electrically
farthest from the refreshing device should reply. Refer to
the "Refresh Configuration Procedure" in the "Systems
Configurations" section.

829

MSV11-C/M7955
MSV11-C Jumper Configuration When Shipped
Jumper
Name
W1
W2
W3
W5

Jumper
State

Function Implemented
Battery backup power connected to system power.

Battery backup power only.

W1 W2 W3 W5
R I
I
R
I
R R I

Battery backup power available but not desired for this
MSV11-C module.
W6
W7

Internal refresh enabled.
Reply to refresh disabled.
W6 W7

External refresh; no reply.

External refresh; reply enabled.
W4
W8
W12
W16

W14

Factory configured to enable the memory banks appropriate to the memory model. These are normally not
changed except for:
1.

Maintenance - Refer to chapter 4 of MSV11-C
User's Manual, EK-MSV11-0P.

Configuring for 28K system: Remove W 16 to disable upper 4K.See configuration rules in the
"Systems Configurations" section.

Bus grant continuity provided.

W15
"Memory bank enable jumpers when supplied.

830

MSV11-C/M7955
Module
Number

Option
Designation

Memory
Size

W4 we W12 W16

M7955-YD
M7955-YC
M7955-YB
M7955-YA

MSV11-CD
MSV11-CC
MSV11-CB
MSV11-CA

16K
12K
8K
4K

I
I
I
I

I
I
I

I
I

R
R
R

R
R

MSV11-CD Addressing Summary

Starting
Address

MSV11-CD
Banks

Address Range

0
20000
40000
60000
100000
120000
140000
160000
200000
220000
240000
260000
300000
320000
340000
360000
400000
420000
440000
460000
500000
520000
540000
560000
600000
620000
640000
660000
700000
720000'
740000
760000

0-3
1-4
2-5
3-6
4-7
5-10
6-11
7-12
10-13
11-14
12-15
13-16
14-17
15-20
16-21
17-22
20-23
21-24
22-25
23-26
24-27
25-30
26-31
27-32
30-33
31-34
32-35
33-36
34-37

0-77777
20000-117777
40000-137777
60000-157777
100000-177777
120000-217777
140000-237777
160000-257777
200000-277777
220000-317777
240000-337777
260000-357777
300000-377777
320000-417777
340000-437777
360000-457777
400000-477777
420000-517777
440000-537777
460000-557777
500000-577777
520000-617777
540000-637777
560000-657777
600000-677777
620000-717777
640000-737777
660000-757777
700000-777777

x
x
x

x-x
x-x
x-x
831

Switch
Setting
S1 S2 S3 S4 S5

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1

1
0
0
0
0

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1

1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

MSV11-C/M7955
NOTES
1.

Switch setting:
1 = ON

0= OFF
2.

Each memory bank = one 4K address space.

Switches 6, 7, and 8 are not used.

NOTE
When used in PDP-11/23 systems, the MSV11-C memory can·
not be configured in the 56K-64K byte (28K-32K word) range
or in the 248K-256K byte (124K-128K word) range.

832

MSV11-D,E/M8044,5

MSV11-D,E MOS READ/WRITE MEMORY

Model

Memory Capacity

Module

Parity Bits

MSV11-DA
MSV11-DB
MSV11-DC
MSV11-DD
MSV11:ED

4K by 16 bits
BK by 16 bits
16K by 16 bits
32K by 16 bits
32K by 1B bits

MB044-AA
MB044-BA
MB044-CA
MB044-DA
MB045-DA

No
No
No
No
Yes

Amps

Bus Loads

Cables

AC
2

None

+5
2.0

+ 12
0.41

Standard Addresses
Module is shipped configured to start at bank O.

Vectors
None

Diagnostic Programs
Refer to Appendix A.
NOTE
DEC diagnostic will not check parity.

Related Documentation
MSV11-D, -E User's Manual (EK-MSV1O-0P)
Field Maintenance Print Set (MP00259)
Microcomputer Processor Handbook (EB-1B451-20)

833

MSV11-D,E/M8044,5
Address Selection
The MSV 11-0 or MSV 11-E address can start at any 4K bank boundary. The
address configured is the starting address for the contiguous portion of
memory (4K, 8K, 16K, or 32K) contained on the module.

ADDRESS
SWITCHES

{~~~=~

MEMORY (

S1-4

•••

SIZE
• ••
6e
PARITY/NO
5.." PARITY
7'< OPERATION

SEE NOTE 1

S1-1

51-5
12 14 10
17 15 16

SEE NOTE 2

NOTES:
1. JUMPER 1 TO 2 ~ 30K OPTION (MINC)1 TO 3 FOR NO 30K OPTION
2. JUMPER 5 TO 7 FOR MSV11·Q OR 5 TO 6 FOR MSV11·E

MSV 11-0, MSV 11-E Switch and Jumpers M8044,45

Set the switches to the desired starting address as listed in the table. Note
that the module is designated to accommodate a 128K system addressing
capability. However, the present addressing capability of the LSI-11 system, including all POP-11j03, POP-11V03 and POP-11T03 systems, is 32K.
POP-11j23 systems, however, can address within the full 128K word
range. By POP-11 convention, the upper 4K address space is normally reserved for peripheral device and register addresses. Thus, with the present
LSI-11 maximum addressing capability of 32K, bank 7 (address
160000-177777) normally should not be used for system memory.

834

MSV11-D,E/M8044,5
Factory-configured modules will not respond to bank 7 addresses. In special applications that permit the use of the lower 2K portion of bank 7 for
system memory (Le., MINC), enable the lower 2K portion of bank 7 by removing the jumper from wirewrap pins 1 and 3 and connecting a new jumper from 1 to 2.

NOTE
If 30K option is enabled, some diagnostics may not run.

Battery Backup Power
MSV 11-0 and MSV 11-E modules are factory configured with power jumpers
installed for normal system power only. If the system uses a battery backup
power source, remove jumpers W2 and W3. Install new jumpers W4 and
W5. (Two jumpers are removed and two new jumpers are installed.)
Parity
One jumper is factory installed for nonparity (MSV11-D) or parity (MSV11E) operation, depending on the model. Do not reconfigure this jumper.
Standard jumper configurations are listed below .
• All MSV11·0 models: jumper installed from pin 7 to pin 5.
• All MSV 11-E models: jumper installed from pin 6 to pin 5.

NOTE
This memory parity feature is not supported by DEC diagnostics or CPUs.

Memory Size
Two jumpers are factory installed to configure addressing logic for memory
size (number and type of memory-integrated circuits). Do not reconfigure
these jumpers. Standard jumper configurations are listed below.

Models

Jumpers (Two Installed)
Memory Select Pins
Memory Range Pins

MSV11-0A
MSV11·0B
MSV11-DC
MSV11-DD, ED

From 17 to 14
From 12 to 14
From 16 to 14
From 10to 14

835

From 17 to 15
From 17 to 15
From 16to 15
From 16to 15

:s:

MSV11-D, MSV11-E Addressing Summary

(J)

MSV11-DA,
MSV11-EA

4K Memory Bank(s) Selected
MSV11-DB,
MSV11-DC,
MSV11-EB
MSV11-EC

N
F
N
F
N

0
1
2
3
4

0-1
1-2
2-3
3-4
4-5

0-3
1-4
2-5
3-6
4-7

0-7
1-10
2-11
3-12
4-13

N
F
F
N
N

F
N
F
N
F

5
6
7
10
11

5-6
6-7
7-10
10-11
11-12

5-10
6-11
7-12
10-13
11-14

5-14
6-15
7-16
10-17
11-20

N
N
F
F
F

F
F
N
N
F

N
F
N
F
N

12
13
14
15
16

12-13
13-14
14-15
15-16
16-17

12-15
13-16
14-17
15-20
16-21

12-21
13-22
14-23
15-24
16-25

F
N
N
N
N

F
N
N
F
F

F
N
F
N
F

17
20
21
22
23

17-20
20-21
21-22
22-23
23-24

17-22
20-23
21-24
22-25
23-26

17-26
20-27
21-30
22-31
23-32

Switch Settings

Starting
Address

S1-1 S1-2 S1-3 S1-4 S1-5

0
20000
40000
60000
100000

N
N
N
N
N

N
N
N
N
F

N
N
F
F
N

120000
140000
160000
200000
220000

N
N
N
N
N

N
N
N
F
F

F
F
F
N
N

240000
260000
300000
320000
340000

N
N
N
N
N

F
F
F
F
F

360000
400000
420000
440000
460000

N
F
F
F
F

F
N
N
N
N

MSV11-DD,
MSV11-ED

<
.....
.....
I

:CDs:

0l:Io
0l:Io

'in

MSV11-D, MSV11-E Addressing Summary (Cont)

MSV11-DA,
MSV11-EA

4K Memory Bank(s) Selected
MSV11-DC,
MSV11-DB,
MSV11-EB
MSV11-EC

MSV11-DD,
MSV11-ED

N
F
N
F
N

24
25
26
27
30

24-25
25-26
26-27
27-30
30-31

24-27
25-30
26-31
27-32
30-33

24-33
25-34
26-35
27-36
30-37

N
F
F
N
N

F
N
F
N
F

31
32
33
34
35

31-32
32-33
33-34
34-35
35-36

31-34
32-35
33-36
34-37

X
X
X
X
X

F
F

N
F

36
37

36-37

X
X

Switch Settings

Starting
Address

S1-1 S1-2 S1-3 S1-4 S1-5

500000
520000
540000
560000
600000

F
F
F
F
F

N
N
N
N
F

F
F
F
F
N

N
N
F
F
N

620000
640000
660000
700000
720000

F
F
F
F
F

N
N
N
F
F

740000
760000

F
F

CJ)

NOTES
1.

Switch settings:
N = ON
F = OFF
In unmapped systems, bank 7 cannot be selected as factory configured; however, the user can enable the lower
2K portion of bank 7.
X = Do not use.

<
...a.
...a.
I

U'I

MSV11-L/M8059

MSV11-L MOS READ/WRITE MEMORY

GENERAL
MSV11-l Modules

Model

Memory
Capacity

MOS
Chips

Module

Number
of Chips

MSV11-lF
MSV11-lK

128K bytes
256K bytes

64K X 1
64K X 1

M8059-FA
M8059-KA

18
36

MSV11-l POWER
Power Requirements

+5 V 5% Power (Watts)

+5 V ± 5%
Current (Amps)
Standby

Active

Standby

Active

Type

Meas

Max

Meas

Max

Meas
(+5 V)

Max
(5_25 V)

Meas
(+5 V)

Max
(5_25 V)

64K
(IF)
128K
(lK)

140

2.05

1.45

2.05

7.0

10.76

7.25

10.76

1.50

2.05

1.60

2.05

7.5

10.76

8.0

10.76

838

MSV11-L/M8059
Power Requirements (Cont)
+5 V BBU 5%
Current (Amps)
Standby

+ 5 V BBU 5% Power (Watts)

Active

Standby

Active

Type

Meas

Max

Meas

Max

Meas
(+5 V)

Max
(5.25 V)

Meas
(+5 V)

Max
(5.25 V)

64K
(LF)
128K
(LK)

0.9

1.26

1.35

1.85

4.5

6.62

6.75

9.71

1.0

1.38

1.40

1.97

5.0

7.25

7.0

10.34

+5 V Total 5%
Current (Amps)
Standby

+5 V Total 5% Power (Watts)

Active

Standby

Active

Type

Meas

Max

Meas

Max

Meas
(+5 V)

Max
(5.25 V)

Meas
(+5 V)

Max
(5.25 V)

64K
(LF)
128K
(LK)

2.3

3.31

2.8

3.90

11.5

17.38

14.0

20.48

2.5

3.43

3.0

4.02

12.5

18.01

15.0

21.11

Meas = measured
Max = maximum
NOTE

Use the total table above for power requirements for factory can·
figured option modules.

Diagnostic Programs
Refer to Appendix A.
Related Documentation
MSV11-L User's Guide (EK·MSVOL·UG)
MSVll·L Memory Module Configuration Guide (EK·MSV 1L·CG)
Field Maintenance Print Set (Mp·O 1238)

839

MSV11-L/M8059

NOTE
CHIPS ARE POSITIONED 180' OUT OF PHASE
WITH TRAOITIONAL OIGITAL MEMORIES.
DOTTED BLOCK DENOTES

GROUP 1

GROUP 1 JUMPERS - GENERAL
GROUP 2. 3 JUMPERS - START/CSR ADDRESS
GROUP 4 JUMPERS - POWER
o NO BATTERY BACKUP
o BATTERY BACKUP
WIREWRAP GUIDELINES - MAXIMUM. 2 WIREWRAPS PER PIN.
GROUP 2 AND 3 JUMPERS MAY HAVE MAXIMUM NUMBER OF WIREWRAPS.
o EACH WIREWRAP MUST BE DAISY·CHAINED TO ITS OWN GROUND.

rBOARD--'

I POPULATION I

034

~ ~~

02
oY
oX

•oVW

/ ..rGROUP2
JUMPERS

SYSTEM
JUMPER

~y~ ;E;O;y'l
~9~8

r wRiTEwRoNG 1

c. -t

-;
PARITY IBIT 21 I
I
I
171615 I
.h
I
I
NORMAL OR
876....J
I:~
I REMOVAL OF
L.. _ _ _ ....J THE LOWER
1
oS
1OR UPPER
op
I
8A NK IF IT
ON
SA FAUL:4oM
7E;
TY
°L
11109
POINT
I

r- --

.f"K

._ _

'wITHOUT CSR J 0 1

He,1

p~ ~M~RYI T~;;G

.,..R -

VO
-

GROUP'3 _
JUMPERS

r"E
~OC

'16K

I PARITY ERROR

L.::_....J
t

;31

-3D -13

"1. I
t-: - - - ::"'1

-1

L WITH C S 1 U F - ' fFo"'iic'El
-

~ 4

I REPORT
321
I

~U_ _

...J

014

PERIPHERAL
I .29
012
PAGE SELECTION: ,.28 25 024
.....17 CO 26

....-GROUP4
JUMPERS

IWlI +5 NON8ATTERY BACKUP

MSV 11·L Memory Module Layout

840

MSV11-L/M8059
CONFIGURATION
There are four groups of jumpers that alter the memory operation for a specific system application. The jumper groups are named as follows.
Group 1 Group 2 Group 3 Group 4 -

General jumpers
Starting address jumpers
GSR address jumpers
Power jumpers

General Jumpers
The general configuration jumpers are described in the following table, and
the normal or factory configuration is designated by being installed or removed.

General Jumpers (Group 1)

Function

Jumper
Configuration

Normal
Condition

9 to 10
11 to 10
18 to 19
20 to 19

OUT
IN
OUT
IN

3 to 2
1 to 2

OUT

8 to 7

OUT
IN

Type Memory
Nonparity
With parity
Parity non-GSR
Parity with GSR

Parity Error Report
Reported BDAL 16 non-GSR
Reported BDAL 16 and BDAL 17 with
GSR

Write Wrong Parity
Diagnostic bit for tester use:
Disable
Enable

6 to 7

841

MSV11-L/M8059
General Jumpers (Group 1) (Cont)
Jumper
Configuration

Normal
Condition

J to H
F to H

OUT
IN

29 to 28
27 to 28

OUT
IN

32 to 33
34 to 33

OUT
IN

17 to 16
15 to 16

OUT
IN

Small system normal operation
(128K)

R to T

OUT

Large system extended operation
(2 megawords)

R to T

Function
CSR Selection
Non-CSR
With GSR

Peripheral Page Selection
2K peripheral page
4K peripheral page

Full or Half Memory Selection
Half memory selection
Full memory selection

Removal of Lower or Upper Bank
(with a Fault)
Lower bank has failed
Normal operation or upper bank
has failed

Extended or Normal Memory
Selection

842

MSV11-L/M8059
Starting Address Jumpers
Each MSV 11-L memory module installed in a system is jumpered for its
own starting address. The starting addresses are always on 4K boundaries. The module's starting address can be found by answering the question "How much memory does the system already have?" The value obtained
is the module starting address in decimal k words. Module starting addresses and jumpers consist of two groups.
1. First address of the range (FAR) - Selects the first address of the
128K range that the starting address falls in.
2. Partial starting address (PSA) - Selects which 4K boundary within a
specific multiple of 128K words the starting address falls in.
The module starting address (MSA) is determined by how much memory
the system has in decimal k words. First address of the range plus partial
starting address equals module starting address.

Known

PSA = MSA -

•

FAR

First Address of Range

Partial Starting Address

First Address of Range (FAR)
Jumpers In (X) to Ground (K)
P
N
M
L

Decimal (K)

Octal

000-124
128-252
256-380
384-508
512-636
640-764
768-892
896-1020
1024-1148
1152-1276
1280-1404
1408-1532
1536-1660
1664-1788
1792-1916
1920-2044

843

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X

X
X
X
X
X
X

X
X

MSV11-L/M8059
Partial Starting Address (PSA)
Jumpers in (X) to Ground (U)

Decimal

Octal

DAL
Pins

17
Z

16
Y

15
X

14
W

(K)
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
104
108
112
116
120
124

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

844

X
X

X
X
X
X
X
X

X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X

X
X
X
X
X
X

X
X

MSV11-L/M8059
Module Starting Address (Example - 352K Words)

Names

First Address
of Range (FAR)

Partial Starting
Address (PSA)

1Meg 512K 256K 128K

64K 32K 16K 8K

Decimal k words
binary address
BDAL values

BDAL bits

Jumper pin names P

Jumper pins

0
M

Z to Y, Y to U

Mto K

eSR Address Selection
There are three addresses reserved for the eSA. Every MSV11-L memory
module has one eSR. By convention the eSR addresses are assigned as
follows. The memory module with the lowest starting address should be
jumpered for the lowest eSR address. The remaining memory modules will
be jumpered in sequence.

eSR Address Jumpers (Group 3)
22-Bit eSR
Address

18-Bit eSR
Address

17772100
17772102
17772104
17772106
17772110
17772112
17772114
17772116

772100
772102
772104
772106
772110
772112
772114
772116

X
X
X
X
X
X
X

X
X

Note: To obtain any 1 of 8 eSR addresses,
wirewrap daisy-chain fashion from pin E,
which is grounded, to each successive pin
labeled X for that address.

845

MSV11-L/M8059
Power Jumpers
Power jumpers allow the MSV 11-L memory module to use battery backup or
nonbattery backup power.

Power Jumpers (Group 4)
Voltage Connection

Jumper Configuration

+5 V Nonbattery backup

26 to 25 (W1)

+ 5 V Battery backup

24 to 25 (W2)
14 to 13 (W3)'
or
12 to 13 (W4)'

• Availability for the +5 V battery backup.

CSR Bit Assignment
The eSR allows program control of certain parity functions and contains
diagnostic information if a parity error has occurred. The eSR is assigned
an address and can be accessed by a bus master via the LSI-11 bus. Some
eSR bits are cleared by the asssertion of BUS INIT (L). The eSR bit assignments are as follows.

~--------~y~--------~
ERROR ADDRESS
WRITE
WRONG
PARITY

EXTENDED
CSR READ
ENABLE

MR·8644
MA·7169

eSR Bit Assignments

846

MSV11-L/M8059
CSR Bit Descriptions
Bit

Name

Description

Parity error

If a parity error occurs on a DATI or
DATIO(B) cycle, this bit will be set to a 1.
This is a read /write bit and is reset to 0
via a power up or BUS INIT. Bit 15 will remain set unless rewritten or initialized.

Extended GSR Read
Enable

This bit is not used on 12SK word machines. It will be read as a O. Bit 14 can
be set to a 1 in a 204SK word machine
only. In a 204SK word machine bit 14 is a
read 1 write bit and is reset to 0 by power
up or BUS INIT. When set, bit 14 allows
retrieval of failed address bits of A 1S
through A21 stored in GSR bits 05
through OS respectively.

13, 12

Not used

11-05

Error address

If a parity error occurs on a DATI or
DATlO(B) cycle, then A11-A17 are
stored in GSR bits 05- 11 and bits
A1S-A21 are latched. The 12SK word
machines (1S-bit address) require only
one read on the GSR to obtain the failed
address bits. GSR bit 14 = 0 allows the
logic to pass A 11-A 17 to the LSI-11 bus.
A 204SK word machine (22-bit address)
requires two reads. The first read GSR bit
14 = 0 sends contents of GSR bits
05-11. Then the program must set GSR
bit 14 = 1. This enables A1S-A21 to be
read from GSR bits 05-0S.
The parity error addresses locate the
parity error to a 1K segment of memory.
These are read /write bits and are not reset to zero via power up or BUS INIT. If a
second parity error is encountered, the
new failed address will be stored in the
GSA.

04, 03

Not used

847

MSV11-L/M8059
CSR Bit Descriptions (Cont)
Bit

Name

Description

Write wrong parity

If this bit is set to 1 and a DATO or
DATOB cycle to memory occurs, wrong
parity data will be written into the parity
MOS RAMs. This bit may be used to
check the parity error logic as well as
failed address information in the CSR.
The following diagnostic is applicable.
1. With bit 02 set, write entire memory
with any pattern.
2. Read first location in memory. If bit 00
of the CSR is set, then a parity error
indication will be detected on the LSI11 bus and the failed address (location 0) will be stored in the CSR.
3. Read the CSR and obtain the failed
address. CSR bit 14 = 1 implies
A11-A17 on CSR bits 05-11. CSR bit
14 = 1 implies A18-A21 on CSR bits
05-08. Bit 02 is a read /write bit reset
to zero on power up or BUS INIT.

Not used

Parity error enable

If a parity error occurs on a DATI or
DATIO(B) cycle to memory and bit 00 is set
= 1, then BDAL 16 (L) or BDAL 16 (L) and
BDAL 17 (L), jumper selectable, will be asserted on the bus simultaneously with data.
This is a read / write bit reset to zero on
power up or BUS INIT.

848

MSV11-P/M8067

MSV11-P MOS MEMORY

GENERAL
MSV11-P Modules

Model

Memory
Capacity

MOS
Chips

Module

Number
of Rows

Number
of Chips

MSV11-PL
MSV11-PK
MSV11-PF

512K bytes
256K bytes
128K bytel'l

64K X 1
64K X 1
64K X 1

M8067-LA
M8067-KA
M8067-FA

8
4
8

72
36
72

MSV11-PF (Multivoltage MOS RAMs) MS067-FA Power Requirements

Voltage

Standby Current(A)
Measure
Typical
Maximum

Active Current(A)
Measure
Typical Maximum

+ 5 V Noncritical
+5 VBBU
Total +5 V
+12V

1.40
1.15
2.55
0.10

1.45
1.20
2.65
0.35

Voltage

Standby Power(W)
Measure
Typical
Maximum

Active Power(W)
Measure
Typical Maximum

+5 V Noncritical
+5 VBBU
Total +5 V
+12V
Total Power

7.00
5.75
12.75
1.20
13.95

7.25
6.00
13.25
4.20
17.45

2.21
1.55
3.76
0.12

11.60
8.14
19.74
1.51
21.25

849

2.21
1.55
3.76
0.53

11.60
8.14
19.74
6.68
26.42

MSV11-P/M8067
MSV11-PK (Single Voltage, Half Populated) MS067-KA Power

Voltage

Standby Current(A)
Measure
Typical
Maximum

+ 5 V Noncritical
+5 VBBU
Total +5

1.65
1.35
3.00

2.10
1.80
3.90

Active Current(A)
Measure
Typical Maximum
1.70
1.75
3.45

2.10
2.10
4.20

Standby Power(W)
Measure
Typical
Maximum

Active Power(W)
Measure
Typical Maximum

Voltage

(5.0)

(5.25)

(5.0)

(5.25)

+ 5 V Noncritical
+5VBBU
Total Power

8.25
6.75
15.0

11.00
9.45
20.45

8.50
8.75
17.25

11.0
11.0
22.0

MSV11-PL (Single Voltage, Fully Populated) MS067-LA Power

Voltage

Standby Current(A)
Measure
Typical
Maximum

Active Current(A)
Measure
Typical Maximum

+ 5 V Noncritical
+5 VBBU
Total +5 V

1.65
1.45
3.10

1.70
1.85
3.60

2.10
1.90
4.0

2.10
2.20
4.30

Standby Power(W)
Measure
Typical
Maximum

Standby Power(W)
Measure
Typical Maximum

Voltage

(5.0)

(5.25)

(5.0)

(5.25)

+5 V Noncritical
+5 VBBU
Total +5 V

8.25
7.25
15.5

11.0
10.0
21.0

8.50
9.25
17.75

11.00
11.55
22.55

NOTE
Use the +5 V table (BOLD) for current requirements for factory configured modules.

850

MSV11-P/M8067
Diagnostic Programs
Refer to Appendix A.

Related Documentation
MSV11-P User's Guide (EK-MSVOP-UG)
Field Maintenance Print Set (MP-O 1239)

CONFIGURATION
The jumpers on the MSV11-P memory module are divided into the following
five groups.
1.
2.
3.
4.
5.

Starting address jumpers
CSR address jumpers
Power jumpers
Bus grant continuity jumpers
General jumpers

The location of the five jumper groups, four of which are enclosed in solid
boxes and labeled, is shown in the following figure. The remaining jumpers
are classified as general jumpers. The general jumpers are enclosed in
dotted boxes.

Configuring the Starting Address
The starting addresses for each module in the system is always selected
on 4K boundaries. The memory size of the system is determined first by its
byte content. This determines the module starting address (MSA). The first
address of range (FAR) selects the 256K word range the starting address
will fall into. This selection is described under FAR selection. The partial
starting address (PSA) selects the 8K boundary within the 256K range selected. The selection is described under the PSA selection. The following
equation is used for selecting the FAR and PSA.
Known

PSA = MSA -

•
Partial Starting Address

FAR

First Address of Range

851

MSV11-P/M8067

INf-IlBIT

[£?~~J

-------

GRANT CONTINUITY

W1 AND W2 IN FOR
NONBATTERY BACKUP

BATTERY BACKUP

'1'13

'1'111
'1'113

'1'110
'1'112

VOLTAGES

~2Cr;:;';tNE a22/a22
W1 AND W2 OUT FOR
OICO AND 022 CD
MACHINE PASS CD

-.---.u----- POWER

JUM~EA IN FOR BOTH 64~fI6K CHIPS

PRIORITIES
lEOMG. CIAK)

w,
W,
W12
W14

+{iCR
+5 VDO

MSV11-P Memory Module Layout
FAR Starting Address Configurations (Part 1)
Jumpers to Ground (Pin Y)

First Address Ranges (FAR)

Decimal K words

Octal K words

000-248
256-504
512-760
768-1016
1024-1272
1280-1528
1526-1784
1742-2040

00000000-01740000
02000000-03740000
04000000-05740000
06000000-07740000
10000000-11740000
12000000-13740000
14000000-15740000
16000000-17740000

852

Pin X
(A21)

PinW
(A20)

Pin V
(A19)

OUT
OUT
OUT
OUT

OUT
OUT

OUT

IN
IN

OUT

IN
IN
IN
IN

OUT
OUT

OUT

IN
IN

OUT

IN
IN
IN
IN

MSV11-PIM8067
PSA Starting Address Configurations (Part 2)
Partial Starting Address
(PSA)

Jumpers to Ground (Pin R)

Decimal K

Octal

Pin P
(A18)

Pin N Pin M Pin L
(A 17) (A16) (A15)

Pin T
(A14)

0
8
16
24
32
40
48
56

00000000
00040000
00100000
00140000
00200000
00240000
00300000
00340000

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
IN
IN
IN
IN

OUT
OUT
IN
IN
OUT
OUT
IN
IN

OUT
IN
OUT
IN
OUT
IN
OUT
IN

64
72
80
88
96
104
112
120

00400000
00440000
00500000
00540000
00600000
00640000
00700000
00740000

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
IN
IN
IN
IN

OUT
OUT
IN
IN
OUT
OUT
IN
IN

OUT
IN
OUT
IN
OUT
IN
OUT
IN

128
136
144
156
160
168
176
184

01000000
01040000
01100000
01140000
01200000
01240000
01300000
01340000

IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
IN
IN
IN
IN

OUT
OUT
IN
IN
OUT
OUT
IN
IN

OUT
IN
OUT
IN
OUT
IN
OUT
IN

192
200
208
216
224
232
240
248

01400000
01440000
01500000
01540000
01600000
01640000
01700000
01740000

IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
IN
IN
IN
IN

OUT
OUT
IN
IN
OUT
OUT
IN
IN

OUT
IN
OUT
IN
OUT
IN
OUT
IN

853

MSV11-PIM8067
Control Status Register (CSR) Jumpers
Each MSV 11-P memory module has a control status register. The bus master can read or write the CSR via the LSI-11 bus. The CSR is a 16-bit register whose address falls in the top 4K of system address space.
Each memory module has four CSR jumper pins (A, B, C, and D) that can be
daisy-chained to pin E (the ground pin). The jumpers allow logic to detect a
specific CSR address that has been assigned to a CSR memory module.
The user determines which type of bus the module is being installed and
connects the jumpers for each address as described in the following table.

CSR Address Selection

LSI-11
Bus
Address

Jumper to Ground (Pin E)

Module
Number

Extended
LSI-11
Bus
Address

1
2
3
4
5
6
7
a
9
10
11
12
13
14
15
16

17772100
17772102
17772104
17772106
17772110
17772112
17772114
17772116
17772120
17772122
17772124
17772126
17772130
17772132
17772134
17772136

772100
772102
772104
772106
772110
772112
772114
772116
772120
772122
772124
772126
772130
772132
772134
772136

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN

OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN

OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN

Power Jumpers
The power jumpers are divided into the following two groups.
1. 16K multiple voltage devices (Ma067-FA) with or without battery
backup
2. 64K single voltage devices (Ma067-LA and Ma067-KA) with or without
battery backup

854

MSV11-PjM8067
Power Jumpers
16K Multiple Voltage Devices
Nonbattery Backup

Battery Backup

Voltages

W3
W11
W13

W3
W10
W12

-5
+12 VDD
+5CR

64K Single Voltage Devices
Nonbattery Backup

Battery Backup

Voltages

W4
W5
W9
W13/W15

W4
W5
W12
W14

Decouple +5
Decouple +5
+5CR
+5VDD

Bus Grant Continuity Jumpers
To install W1 and W2 in your system, identify the backplane bus structure
as AB/ AB or AB/CD. The jumpers are installed for an AB type backplane
and removed for a CD type backplane as described below.

Bus Grant Continuity
Backplane

Bus Type

H9270 (4 slot backplane)
H9275 (9 slot backplane)
H9273 (4 slot backplane)
H9276 (9 slot backplane)

AB/AB
AB/AB
AB/CD
AB/CD

IN
IN
OUT
OUT

855

MSV11-P/M8067
General Jumpers
The general jumper group and their functions that have not yet been covered are described below.

General Jumpers
Pin
~Numbers

Function

6 to 7

In - write wrong parity

8 to 7

In - disables wrong parity

2 to Y

2 to Y out - 22-bit machine
2 to Y in - 18-bit machine

43 to 44

In - single voltage MOS RAM access time (150 ns
device)

45 to 44

In - multiple voltage MOS RAM access time (200
ns device)

22 to 23

Not used

21 to 23

Not used

F to H

F to H in - connected to force the starting address
to 16K
F to H out - disables force function

3 to 9

3 to 9 in - connected on 16K and 64K MOS chip

13 to 15

Connected on 16K and 64K MOS chip

4 to 10

Connected only on 64K MOS chip

14 to 16

Connected only on 64K MOS chip

856

MSV11-P/M8067
CONTROL STATUS REGISTER (CSR) BIT ASSIGNMENT
The control status register (GSR) in the MSV 11-P allows program control of
certain parity functions and contains diagnostic information if a parity error
has occurred. The GSR is assigned an address and can be accessed by a
bus master via the LSI-11 bus. Some GSR bits are cleared by assertion of
BUS INIT L. The GSR bit assignments are as follows.

WRITE
WRONG
PARITY

EXTENDED
CSR READ
ENABLE

(GSR) Bit Assignment

CSR Bit Descriptions
Bit

Name

Description

Parity error

This bit set indicates that a parity error has occurred. The bit then turns on a red LED on the
module. This provides visual indication of a
parity error.
Bit 15 is a read / write bit. It is reset to zero via
power-up or BUS INIT and remains set unless
rewritten or initialized.

Extended GSR
read enable

The use of this bit is explained in the error address description.
Bit 14 = 0, always for 128K word machine
Bit 14 = 0, first read on 2048K word machine
Bit 14 =
machine

13, 12

Not used

857

1, second read on 2048K word

MSV11-P/M8067
CSR Bit Descriptions (Cont)
Bit

Name

Description

11-05

Error address

If a parity error occurs on a DATI or DATIO(B)
cycle, then A 11-A 17 are stored in GSR bits
05-11 and bits A1B-A21 are latched. The
12BK word machines (1B-bit address) require
only one read of the GSR register to obtain the
failed address bits. GSR bit 14 = 0 allows the
logic to pass A 11-A 17 to the LSI-11 bus. A
204BK word machine (22-bit address) requires
two reads. The first read GSR bit 14 = 0 sends
contents of GSR bits 05-11. Then the program
must set GSR bit 14 = 1. This enables
A 1B-A21 to be read from GSR bits 05-08.
The parity error addresses locate the parity error to a 1K segment of memory. These are
read I write bits and are not reset to zero via
power-up or BUS INIT. If a second parity error
is encountered, the new failed address is
stored in the GSR.

04, 03

Not used

Write wrong
parity

If this bit is set equal to 1 and a DATO or
DATOB cycle to memory occurs, wrong parity
data is written into the parity MOS RAMs. This
bit can be used to check the parity error logic
as well as failed address information in the
GSR. The following diagnostic is applicable.
1. With bit 02 set, writes entire memory with
any pattern.
2. Read first location in memory, if bit 00 of
the GSR is set, then a parity error indication is detected on the LSI-11 bus, and
the failed address (location 0) is stored in
the GSA.
3. Reads the GSR and obtains the failed address; GSR bit 14 = 0 implies A 11-A 17 on
GSR bits 05-11. GSR bit 14 = 1 implies
A1B-A21 on GSR bits 05-0B. Bit 02 is a

858

MSV11-P/M8067
CSR Bit Descriptions (Cont)
Bit

Name

Description
read/write bit reset to zero on power-up or
BUS INIT.

Not used

Parity Error
Enable

If a parity error occurs on a DATI or DATIO(B)
cycle to memory, and bit 00 is set equal to 1,
then BDAL 16 Land BDAL 17 L are asserted
on the bus simultaneously with data. This is a
read / write bit reset to zero on power-up or
BUS INIT.

859

MXV11-AA,AC/M8047

MXV11-AA,AC MULTIFUNCTION MODULE

The MXV 11 is a multifunction option module used for the LSI-11, LSI-11/2,
or LSI-11 /23 systems. It contains read/write memory provisions for readonly memory, two asynchronous serial line interfaces and a 60 Hz clock
derived from a crystal oscillator.
Detailed technical information is beyond the scope of this document. Additional information can be found in the Microcomputer Processor Handbook,
EB-18451-20.

Model Designations
• MXV11-AA contains 8K bytes of random access memory.
• MXV 11-AC contains 32K bytes of random access memory.
Both models have two 24-pin sockets that provide for +5 V read-only memories in which 1K X 8, 2K X 8, or 4K X 8 ROMs may be used. These sockets may also be used for 256 words of bootstrap code.

Bus Loads

Amps
+5
1.2

+12
0.1

AC
2

Cables

DC
2

BC20M-XX
BC20N-XX (Refer to DL V 11-KA)
BC21B-XX

Standard Addresses
RAM - Starts on any 8K boundary below 64KB.
SLU

Channel 0
176500

Channel 1
177560

To disable RAM
MXV11-AC = Remove W4
MXV11-CA = Remove W5

860

MXV11-AA,AC/M8047
Standard Vectors
SLU

300

Diagnostic Programs
Refer to Appendix A.
Requires wraparound connectors to completely exercise SLU.
Related Documentation
MXV11-A Memory and Asynchronous Serial Line Interface User Guide (MB047)
(EK-MXV1 A-UG)
Field Maintenance Print Set (MP-00730)

Options
MXV11-A2 Boot ROMs for RX02, RX01, or TU58
PNs: 23-131 F3-00, 23-132F3-00
ROMs
Power:

+5 V ± 5%

Pins:

24-Pin DIP

Access Time:

Up to 450 nanoseconds

Array Size:

1K X 8, 2K X 8, or 4K X 8 bits

Type:

Typical PROM types:

UV PROMs

Chip
Array Size

Memory Size

Intel 2758
Intel 2716
Intel 2732
Mostek MK2716
T.I. TMS 2516
T.I. TMS 2532

1K X 8 bits
2K X 8 bits
4K X 8 bits
2K X 8 bits
2K X 8 bits
4K X 8 bits

1K words
2K words
4K words
2K words
2K words
4K words

1K X 8 bits
1K X 8 bits
1K X 8 bits
2K X 8 bits

1K words
1K words
1K words
2K words

Bipolar PROMs
Intel 3628
Signetics 82S 2708
Signetics 82S 181
Signetics 82S 191

861

MXV11-AA,AC/M8047

CHANNELl

J6BA
J67A

/!t\~

J64 J63 J62 J6l J60 J59

AJ5B
AJ57
AJ56
AJ55
AJ54
AJ53
AJ52
AJ5l
AJ50
AJ49
·AJ4B
AJ47
AJ46
AJ45
AJ44
AJ43
AJ42
AJ4l

1--1 W4
t--t W5

AJ40

AJ39

AJ3B
AJ37
AJ36
AJ35
AJ34
AJ33
AJ32
AJ3l
AJ30

AJ29
AJ2B
AJ27
AJ26
AJ25
AJ24
AJ23
AJ22
AJ2l
AJ20
AJ19
AJ18
AJ17
AJ16
AJ15
AJ14
AJ13
AJ12
AJll
AJ10
AJ9
AJ8

Jl
AA AA
J6J5 J4J3

MXV11-A Jumper Locations

862

MXV11-AA,AC/M8047
MXV11-A Jumper Functions
Pin

Function

Option

Clock L. Open collector output of the clock.
Connected to pin AF 1 (SSpare 2). Wirewrap to J4
to implement the clock option.

60 Hz

BEVNT L. Event interrupt (pin BR 1) used for the
clock option.

60 Hz

BDCOK H. DCOK (pin BA 1) when high allows the processor to operate; when low initializes the system.
Connected to J6 to use the boot option.

Boot

Framing Error. Open collector output of framing
error from serial line one. Connected to pin AE 1
(SSpare 1). Wirewrap to J5 to implement the boot
option. Reset by bus initialize or reception of
a valid character.

Break

BHAL T L. Halt (pin AP 1) when low will stop program execution and cause the processor to enter
ODT microcode. Connected to J6 to implement the
halt option.

Halt

GND. A ground signal that can be used to disable
ROM by wirewrapping to J21 or to disable a serial
line by wirewrapping to an address input pin (J23
or J24 for serial line 0; or J25, J26, J27, or J28
for serial line 1).

ROM

A 13 L. Address bit 13 asserted low. Wirewrap to
J 11 to select bank 1 with the ROM address decoder.

ROM

J lOA 13 H. Address bit 13 asserted high. Wirewrap to
J 11 to select bank 0 with the ROM address decoder.

ROM

J 11

A 13 M. Address bit 13 input to the ROM address
decoder. See J9 and J 1O. Used only if J20 is
wirewrapped to J21.

ROM

J 12

A03 H. Address bit 03 asserted high. Wirewrapped
to the serial line address decoders (J23 or J24 for
serial line 0, J25, J26, J27 or J28 for serial line
1) when address bit 03 is to be decoded as a 1.

SLU

863

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J13

A04 H. Address bit 04 asserted high. Wirewrapped
to the serial line address decoders when address
bit 04 is to be decoded as a 1.

SLU

J14

A05 H. Address bit 05 asserted high. Wirewrapped
to the serial line one address decoder when address
bit 05 is to be decoded as a 1.

SLU

J15

A09 H. Address bit 9 asserted high. Wirewrapped
to the serial line one address decoder when address
bit 09 is to be decoded as a 1.

SLU

J16

A09 L. Address bit 09 asserted low. Wirewrapped
to the serial line one address decoder when address
address bit 09 is to be decoded as a o.

SLU

J17

A05 L. Address bit 05 asserted low. Wirewrapped
to the serial line one address decoder when address
bit 05 is to be decoded as a o.

SLU

J18

A04 L. Address bit 04 asserted low. Wirewrapped
to the serial line address decoders when address
bit 04 is to be decoded as a o.

SLU

J19

A03 L. Address bit 03 asserted low. Wirewrapped
to the serial line address decoders when address
bit 03 is to be decoded as a o.

SLU

J20

ROM address. Output of the ROM address decoder.
Connected to J21 when ROM is to be used in bank 0
or bank 1.

ROM

J21

ROM select. ROM address selection enable asserted
high. Wirewrapped to J8 (GND) to disable ROM, to
J20 for bank 0 or bank 1, or to J22 for bootstrap.

ROM

J22

Boot address. Output of the bootstrap address
decoder. Connected to J21 when ROM is to be used
in the bootstrap range from 173000-173776 (773000773776 for LSI-11/23).

BOOT

J23

Serial line 0 address decoder input asserted high.
May be wirewrapped to A03 H (J12), A03 L (J19),
A04 H (J13), or A04 L (J18).

SLU

864

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J24

Serial line 0 address decoder input asserted high.
May be wirewrapped to A03 or A04, whichever bit is
not wired to J23. May be wirewrapped to GND (J8)
to disable serial line O.

SLU

J25J28

Serial line 1 address decoder input asserted high.
Four address decoder inputs to be connected to
address bits A03, A04, A05, and A09. Whether the
high or low assertion state of a bit is wirewrapped
to an input determines if that bit is decoded as a
1 or a o. See J 12 through J 19. May be wirewrapped
to GND (J8) to disable serial line 1.

SLU

J29

ROM address bit 09 input. Wirewrapped to A09 H
(J 15) for normal ROM addressing and also for the
MXV 11-A2 option when the TU58 bootstrap is desired.
Wirewrapped to A09 L (J 16) for the MXV 11-A2 option
when the disk bootstrap is desired.

ROM

J30J32

RAM starting address selection. These pins are
wirewrapped to J33 (logic 0) or J34 (logic 1) to
select the RAM starting address (see the following).

RAM

J32

J31

J30

Bank

0
0
0
0
1

0
0
1
1
0
0

0
1
0
1
0
1
0

0
1
2
3
4
5
6
7

Starting
Address
000000
020000
040000
060000
100000
120000
140000
160000

J33

GND. Logic 0 level signal used for selecting the
RAM starting address and for enabling some ROM ICs
in the ROM sockets.

RAM,
ROM

J34

+3 V. Logic 1 level signal used for selecting the
.RAM starting address and for enabling some ROM ICs
in the ROM sockets.

RAM,
ROM

865

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J35

A 12 H. Address bit 12 asserted high. Used for
addressing 4K X 8 bit ROMs. Wirewrapping to J37,
J38 or J39, depending on the ROM used.

ROM

J36

A 11 H. Address bit 11 asserted high. Used for
addressing 2K X 8 and 4K X 8 bit ROMs. Wirewrapping to J37, J38, or J39, depending on the ROM.

ROM

J37

Pin 18 on both ROM sockets. Used for addressing
or enabling ROM. Wirewrapped to J33 for ground,
to J34 for + 13 V, to J35 for A 12, or to J36 for A 11 .

ROM

J38

Pin 19 on both ROM sockets. Used for addressing
or enabling ROM. Wirewrapped to J33 for ground,
to J34 for + 3 V, to J35 for A 12, or to J36 for A 11.

ROM

J39

Pin 21 on both ROM sockets. Used for addressing
or enabling ROM. Wirewrapped to J33 for ground,
to J34 for + 3 V, to J35 for A 12 to J36 for A 11 or
to J40 for +5 V.

ROM

J40

+ 5 V. Used to power some ROMs on pin 21.

ROM

J41

Used for 150 baud. Wirewrapped to J45 for serial
line 0, to J46 for serial line 1. (See following
table.)

SLU

J42

Used for 1200 baud.

SLU

J43

Used for 300 baud.

SLU

J44

Used for 2400 baud.

SLU

J45

Clock o. The clock input for serial line 0 transmit
and receive, 16 times the baud rate. Wirewrapped to
either J41, J42, J43, J44, J47, J48, J49, or J50.

SLU

J46

Clock 1. The clock input for serial line 1 transmit
and receive, 16 times the baud rate. Wirewrapped to
either J41, J42, J43, J44, J47, J48, J49, or J50.

SLU

J47

Used for.4800 baud.

SLU

J48

Used for 9600 baud.

SLU

866

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J49

Used for 19.2K baud.

SLU

J50

Used for 38.4K baud.

SLU

J51

Vector O. Vector enable for channel O. Used to
drive vector bits that pass the test: logic 1 for
channel 0, and logic 0 for channel 1. Wirewrapped
to J53 for bit 03, to J54 for bit 04, to J55 for
bit 05, to J56 for bits 06 and 07.

SLU

J52

Vector 1. Vector enable for channel 1. Used to
drive vector bits that pass the test: logic 0 for
channel 0 and logic 1 for channel 1. Wirewrapped
to J53 for bit 03, to J54 for bit 04, to J55 for
bit 05, to J56 for bits 06 and 07.

SLU

J53

Vector bit 03. Selects how bit 03 is to be driven
for interrupt vectors. Wirewrapped to J51 if a
logic 1 for channel 0 and a logic 0 for channel 1;
to J52 if a logic 0 for channel 0 and a logic 1 for
channel 1; to J57 if a logic 0 for both channel 0
and channel 1; or to J58 if a logic 1 for both
channel 0 and channel 1.

SLU

J54

Vector bit 04. Selects how bit 04 is to be driven
for interrupt vectors. Wirewrapped the same as J53.

SLU

J55

Vector bit 05. Selects how bit 05 is to be driven
for interrupt vectors. Wirewrapped the same as J53.

SLU

J56

Vector bits 06 and 07. Selects how bits 06 and 07
are to be driven for interrupt vectors. Wirewrapped the same as J53.

SLU

J57

GND. Logic 0 signal for configuring vector bits.
Wirewrapped to J53, J54, J55 and/or J56 when the
corresponding vector bites) will be logical 0 for
both serial line channels.

SLU

J58

+3 V. Logic 1 signal for configuring vector bits.
Wirewrapped to J53, J54, J55 and/or J56 when the
corresponding vector bites) will be logical 1 for
both serial line channels.

SLU

867

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J59

Seven bits parity, eight bits no parity, channel 1.
Wirewrapped to ground (J65) for seven bits with
parity or to +3 V (J66) for eight bits with no
parity.

SLU

J60

Two stop bits. Selects one or two stop bits for
channel 1. Wirewrapped to ground (J65) for one
stop bit or to +3 V (J66) for two stop bits.

SLU

J61

Even parity. Selects odd or even parity for
channel 1 when seven bits with parity (J59 wirewrapped to ground) is selected. Wirewrapped to
ground (J56) for odd parity or to +3 V (J66) for
even parity.

SLU

J62

Seven bits parity, 8 bits no parity, channel o.
Wirewrapped to ground (J65) for seven bits with
parity or to + 3 V (J66) for eight bits with no
parity.

SLU

J63

Two stop bits. Selects one or two stop bits for
channel o. Wirewrapped to ground (J65) for one
stop bit or to +3 V (J66) for two stop bits.

SLU

J64

Even parity. Selects odd or even parity for
channel 0 when seven bits with parity (J59 wirewrapped to ground) is selected. Wirewrapped to
logic 0 (J65) for odd parity or to logic 1 (J66)
for even parity.

SLU

J65

Logic O. Ground signal used for configuring
serial line interfaces.

SLU

J66

Logic 1. +3 V signal used for configuring line
interfaces.

SLU

J67

Clock in. Clock input for baud rates, memory
refresh and negative voltage generator. Wirewrapped to J68. Not a user option.

SLU

J68

Clock out. Crystal oscillator output at 19.6608
MHz. Wirewrapped to J67. Not a user option.

SLU

868

MXV11-AA,AC/M8047
Standard Factory Configuration
Wirewrap
From

Pins
To

Wirewrap
Level

J30
J32
J31

J31
J33
J32

L1
L1

SLU Channel 0 Address 176500

J23
J24

J18
J19

L1
L1

SLU Channel 1 Address 177560

J28
J26
J25
J27

J19
J15
J14
J13

L2
L1
L1
L1

ROM Bootstrap (TU58)

J37
J21
J34
J33
J29

J38
J22
J37
J39
J15

L1
L1
L2
L2
L2

SLU Vectors CHO (300)
CH1 (60)

J53
J54
J56
J54

J57
J52
J51
J55

L1
L1

J59
J62
J60
J61
J59
J63

J61
J64
J63
J62
J66
J65

L1
L2
L2
L2

Baud Rates CHO (38.4K)
CH1 (9600)

J45
J46

J50
J48

Break Generation
(Halt Option)

Crystal Clock

J68

J67

Function

RAM Bank 0

SLU Parameters (8 Data Bits,
No Parity, 1 Stop Bit)

869

L1
L2
L1
L1

MXV11-AA,AC/M8047
Configuring the RAM
The RAM can be configured to start on any 8KB boundary below 64KB. Because of this restriction, the MXV 11 (8KB version) is not usable for memory
above 56KB. The MXVll can be used in 18-bit memory address systems,
but it is restricted to being assigned to the memory area at or below 56KB.
Five wirewrap terminals, J30 through J34, select the starting address. The
following figure shows the jumper configurations required to obtain the desired starting addresses.
17

><
13

I :':
I 1 1

J32

J30

0 ~ FACTORY CONFIGURED

1 = CONNECT JUMPER TO J34
2 = CONNECT JUMPER TO J33

RAM Starting Address Selection
Configuring the ROM
Depending on the ROM type, the module's capacity is 1K, 2K, or 4K words
using a pair of 1024 X 8-, 2048 X 8-, or 4096 X 8-bit ROMs respectively.
The user configures jumpers on the module for the ROM type being used.
The actual procedure for loading data into EPROMs, PROMs (or writing
specifications for masked ROMs) will vary depending on the manufacturer,
and is beyond the scope of this section. The user must refer to the manufacturer's data sheets and to the chapter, "Using PROMs" in the Microcomputer Processor Handbook, EB-18451-20. The user must be aware of
the relationship of the EPROM, PROM, or ROM pins to the LSI-ll data bits,
and the relationship of the pins to the memory address bits. Refer to the
following figure for ROM socket pin assignments. All ROMs used on the
MSV ll-A must conform to these pin assignments.
The factory configuration allows for using the MSVll-A2 bootstrap ROMs.

Configuring the Bootstrap ROM - The ROM can be configured to operate
in the I/O page to support bootstrap programs. The address area contains
256 words from 173000 to 173776 (773000 to 773776 for the LSI-ll/23).
The MXV ll-A is configured at the factory to allow for using the MXV 11-A2
TU58 bootstrap. To reconfigure the MXV ll-A to use the disk bootstrap, remove jumper J29 to J 15 and install jumper J29 to J 16.

870

MXV11-AA,AC/M8047
A08 H

VCC

A07 H

J29
Al0 H

A06 H
A05 H

J39
ROM L

A04 H
A03 H

J38
J37

A02 H
AOl H

D07 H

(D15 HI

ID08 HI DOO H

D06 H

(D14 HI

ID09 HI DOl H

D05 H

(D13 HI

(D1O HI D02 H

D04 H

ID12 HI

GND

D03 H

(Dll HI

NOTE:
DATA OUT PINS SHOWN IN PARENTHESES
REFER TO THE HIGH BYTE SOCKET XE67.
DATA OUT PINS DOO H THROUGH D07 H
REFER TO THE LOW BYTE SOCKET XE57.

MXV 11-A ROM Socket Pin Assignment

ROM Bank Selection - If the MXV 11-A sockets are used for program ROM
instead of a bootstrap ROM, the memory must be selected by a jumper connecting J20 to J21. When main ROM memory is selected, the entire 4K
word bank is enabled. If a 1K or 2K ROM is used, it will "wraparound" and
give invalid data, depending on how the address lines are configured when
the nonexisting ROM area is addressed. Main memory may be positioned in
bank 0 or bank 1. To position the ROM in bank 0, jumper J10 to J11. To
position the ROM in bank 1, jumper J9 to J 11.
Configuring the Specific ROM Types - Additional jumpers must be connected depending on the type of ROM used. The "EPROM Address Jumpers" table describes the jumper configuration when using typical ROMs
such as the Intel 2716 (2K X 8) or 2732 (4K X 8) EPROMs. The user must
refer to the manufacturer's data sheets when configuring jumpers for other
ROM types.
The function of wirewrap pins J29, J38, J37, and J39 are shown in the following table. These pins are to be connected as required to pins J33
through J40.
ROM Upgrade Part Numbers
23-131 F3-00
23-132F3-00
871

MXV11-AA,AC/M8047
EPROM Address Jumpers
2716 ROM

2732 ROM

Function

Bank 0 Bank 1 Bank 0 Bank 1
From to
to
to
to

Bank Enable
Bit 09 Input
Address or Enable
Address or Enable
Address or Enable

J20
J29
J38
J37
J39

J21
J15
J36
J33
J40

J21
J15
J36
J35
J33

J21
J15
J36
J35
J34

CONFIGURING THE SERIAL LINE UNITS
Serial line Register Address Selection
Four device registers (RCSR, RBUF, XCSR, and XBUF) are provided for
each of the two serial lines. Jumpers are configured to establish separate
base addresses for each serial line as shown.
• Serial port 0 may be assigned to one of the four starting addresses:
176500, 176510, 176520, 176530.
• Serial port 1 may be assigned addresses in two ranges. The first range
starts at 176500 and covers the eight starting addresses from 176500
to 176570. The second range starts at 177500 and also contains eight
possible starting addresses, including the standard console address,
177560. Since several other standard DIGITAL devices use addresses
in this second range, it is recommended that only the console address
be used.
The format of an SLU address is shown in the following figure. Note that bits
13-17 are neither configured nor decoded by the MXV 11-A module. These
bits are decoded by the bus master module as the bank 7 select (BBS7 L)
bus signal. This signal becomes active only when the I/O page is accessed. Bit 0 is used as the byte pointer.

00 = RCSR
01 = RBUF
10'" XCSR
11 "'XBUF

1 eo RANGE 2
0'" RANGE 1

BANK SE LEeT 7

JUMPER POSTS ARE WIRED TO A HIGH
ADDRESS LINE FOR A 1 AND TO A LOW
ADDRESS LINE FOR A O. REFER TO

TABLES 7 AND 8 FOR JUMPER CONFIGURATIONS.

J26

SERIAL LINE 1

J2&

MXV 11-A SLU Address Format
872

MXV11-AA,AC/M8047
Bits 1 and 2 select one of the four device registers within the addressed
serial line. Bits 3 and 4 are used to select one of four possible device addresses for serial line O. Bits 3, 4, 5, and 9 are used to select the device
addresses in two ranges for serial line 1 (console). The following table describes the jumper combinations to select one of four device addresses for
serial line 0 (I/O).
Serial Line 0 Address Jumpers
Address
(Octal)

Jumper Posts
J23 to

J24 to

176500

J 18 (Logic 0)

J 19 (Logic 0) Factory Configuration

176510

J 18 (Logic 0)

J12 (Logic 1)

176520

J 13 (Logic 1)

J 19 (Logic 0)

176530

J 13 (Logic 1)

J12 (Logic 1)
NOTE

Logic 1
J13 (A04 H)
J12 (A03 H)

Logic 0
J18 (A04 L)
J19 (A03 L)

Serial line 1 may have 16 possible device addresses in two ranges. The
following table describes the jumper combinations to select the eight device registers available in range 1. Only one device address is used in
range 2.
Serial Line 1 Address Jumpers
Address
(Octal)
Range 1

Jumper Posts
J26
J25
J27
to
to
to

J28
to

176500
176510
176520
176530
176540
176550
176560
176570

J16
J16
J16
J16
J16
J16
J16
J16

J17
J17
J17
J17
J14
J14
J14
J14

J18
J18
J13
J13
J18
J18
J13
J13

J19
J12
J19
J12
J19
J12
J19
J12

J15

J14

J13

J19

Range 2
177560

(See the following Note.)
873

MXV11-AA,AC/M8047
NOTE
Factory configurations use only one address in range 2 to
avoid possible device conflicts. The remaining addresses are
pre-assigned to other devices.

Logic 0
J16 (A09 L)
J17 (A05 L)
J18 (A04 L)
J19 (A03 L)

Logic 1
J15 (A09 H)
J14 (A05 H)
J13 (A04 H)
J12 (A03 H)

Control/Status Register
The MXV 11-A has two control/status registers (CSRs) for each of its two
serial line units. The following figure shows the control/status registers
and the read/write data registers. Transmitter control/status registers 0
and 1 (XCSRO and 1) and receiver control/status registers 0 and 1 (RCSRO
and 1) operate with serial lines 0 and 1, respectively.

Both serial line units have the same bit assignments. There are four registers for each serial line. They are sequential in this order: 0, receiver status; 2, receiver data; 4, transmitter status; and 6, transmitter data. All
unused bits are read as O.

874

MXV11-AA,AC/M8047

RCSR

(NOT USED)

RECEIVER
DONE
(READ ONLY)
RECEIVER

INTERRUPT
ENABLE
(READ/WRITE)

RBUF

RECEIVE DATA

(7,8 BIT DATA IS RIGHT JUSTIFIED.)
IF BIT UNUSED = 0
(READ ONLY)

XCSA

(NOT USED)

TRANSMIT

TRANSMIT BREAK
(READ!WRITE)

READY
(READ ONLY)

TRANSMIT
INTERRUPT
ENABLE
(REAO/WRITE)

XBUF

I : : :
0

: :
0

: I

(NOT USED)

TRANSMIT DATA
(7.8 BIT DATA IS RIGHT JUSTIFIED.)
(WRITE ONLY) ON READ = 0

NOTE

ONE OF FOUR CHANNELS SHOWN.
FORMAT THE SAME FOR ALL CHANNELS.

MXV11-A SLU CSR Formats

875

MXV11-AA,AC/M8047
Bit Assignments for the Receiver Status Register
Bit

Function

Interrupt enable, read/write. A 1 enables receiver interrupts, a 0
disables interrupts. Cleared by initialize.

Receiver done, read only. A 1 indicates that the serial interface
has received a character. If enabled by bit 6, receiver done will
request an interrupt. Receiver done is cleared by reading the receiver data register or by initialize.

0-7

Data bits, read only. Bit 0 is the least significant bit and bit 7 is
the most significant. If seven data bits plus parity is selected, bit
7 will always read as a o.

Parity error, read only. A 1 indicates that the word being read in
bits 0 through 6 has a parity error. Bit 12 will always read 0 when
eight data bits and no parity are selected. Cleared when read, or
by initialize.

Framing error, read only. A 1 indicates that a start bit was detected, but there was no corresponding stop bit. A framing error
will be generated when a break is received. Cleared when read,
or by initialize.

Overrun error, read only. A 1 indicates that a word in the receiver
buffer had not been read when another word was received and
placed in the receiver buffer. Cleared when read, or by initialize.

Error, read only. A 1 indicates that one or more of bits 12, 13, and
14 are 1. Cleared when read, or by initialize.

876

MXV11-AA,AC/M8047
Bit Assignments for the Transmitter Status Register
Bit

Function

Break, read/write. When set to a 1, bit 0 causes the serial output
signal to go to a space condition. A space condition longer than
a character time causes a framing error when it is received and
is regarded as a break. Cleared by writing a 0, or by bus initialize.
Interrupt enable, read/write. A 1 enables transmitter interrupts; a

o disables interrupts. Cleared by initialize.

Transmitter ready, read only. A 1 indicates that the serial interface is ready to accept a character into the transmitter data register. If enabled by bit 6, transmitter ready will request an interrupt. Transmitter ready is cleared when data is written into the
transmitter data register. It is set by initialize.

0-7

Data bits, write only. Bit 0 is the least significant bit and bit 7 is
the most significant bit. If seven data bits plus parity are selected, bit 7 will not be transmitted. The transmitter data register
will read all Os.

Interrupt Vector Selection
Two consecutive interrupt vectors (one for receive and one for transmit)
are provided for each of the two serial lines. The interrupt vector format is
shown in the following figure. Each SLU port can be independently configured to operate in one of two ranges: 000 to 074, or 300 to 376.

NOTE
BITS 3 THROUGH 7 MAY BE WIRED
TO ONE OF FOUR WIREWRAP POSTS
J51 (VEe 0), J52 (VEe 1). J57 (GND)
OR J58 (+3 V)

:y
07

J56

I :

I I I I

J55

J54

J53

1 = TX

2 '" Rev

MXV11-A Interrupt Vector Format
The following table lists the vector addresses that may be assigned to the
serial lines. Note that all vector addresses in the 000 to 074 range, except
060, are reserved vector locations. The jumper selectable bits are 3
through 7. Bits 6 and 7 are wired together.

877

MXV11-AA,AC/M8047
Serial Line Vector Addresses
Serial Line 1 (Console)

Serial Line 0 (I/O)

000
010
020 DIGITAL Reserved
030 Do not use
040
050
060 Console
070 DIGITAL Reserved

300
310
320
330
340
350
360
370

The following example illustrates the procedure for configuring the vector
addresses. Assume that 60 is the address for serial line 1 (console) and
310 is the address for serial line 0 (I/O). The example describes the relationship between the vector bases, vector address bits, and the jumper
posts. The jumpers are configured using the following four rules.
1. If a bit =

1 in both vector bases, it is tied to J58 (logic 1).

2. If a bit = 0 in both vector bases, it is tied to J57 (logic 0).
3. If a bit = 1 for serial line
(vector 1).

and a 0 for serial line 0, it is tied to J52

4. If a bit = 0 for serial line
(vector 0).

and a 1 for serial line 0, it is tied to J51

Interface Connector Pins
Two 10-pin connectors (one for each serial line) are provided on the
MXV 11-A module. Connector pins and signal functions are described in the
following table and shown in the following figure.
TYPICAL INTERFACE
CONNECTOR
1 OF 2

NO PIN
(FOR CABLING
INDEXING)

MXV 11-A Connector Pins
878

TOP OF
MXVll·A
MODULE

MXV11-AA,AC/M8047
MXV11-A I/O Connector Pin Functions
Pin

2
3
4

5
6
7

8
9
10

Signal

Function

UART CLOCK The baud rate clock appears on this pin. When an internal baud rate is selected, this pin is a TTL output.
When no baud rate is selected on the module, this is
an external baud rate input. The high level for the
clock> 3.0 V.
GND
Transmitter output
XMIT+
GND
GND
Key, pin not provided
NC
Receiver input most negative
RCVReceiver input most positive
RCV+
GND
Power for the DL V 11-KA option
+12 V

Current Loop
The MXV 11-A module can interface with 20 mA active or passive current
loop devices when used with the DLV11-KA option. This option consists of
a DL V 11-KB (EIA to 20 mA current loop converter) and a BD21 A-03 interface cable. The MXV 11-A does not have the capability to support the reader-run portion of the DLV11-KA option. The DLV11-KA option is placed between the MXV 11-A serial line output and the 20 mA current loop
peripheral device.
MXV11-A Interface Cables
Cable

Application

Length

BC21B-05

EIA RS-232C modem cable to interface with
modems and acoustic couplers (2 X 5-pin
AMP female to RS-232C male).

1.5 m (5 ft)

BC20N-05

EIA RS-232C null modem cable to directly
interface with a local EIA RS-232C terminal
(2 X 5-pin AMP female to RS-232C female).

1.5 m (5 ft)

BC20M-50

EIA RS-422 or RS-423 cable for high-speed
transmission (19.2K baud) (2 X 5-pin AMP
female to 2 X 5-pin AMP female).

15 m (50 ft)

BC05D-10

Extension cable used in conjunction with
BC21B-05.

3 m (10 ft)

BC05D-25

Extension cable used in conjuntion with
BC21B-05.

7.6 m (25 ft)

BC03M-25

"Null modem" extension cable used in
conjunction with BC21B-05.

7.6 m (25 ft)

879

MXV11-AA,AC/M8047
NOTE
"Strapped" logic levels are provided on Data Terminal Ready
(OTR) and Request To Send (RTS) for operation of modems
with manual provisions (such as Bell 103A data set with 804B
auxiliary set).

The MXV 11·A may operate with several peripheral device cables and op·
tions for flexibility when configuring systems. A variety of cables and options, as well as the primary application of each, are shown with the
MXV11-A.
1. The receivers on the MXV 11 have differential inputs. Therefore, when
designing an RS-232C or RS-423 cable, receive data (pin 7 on the 2 X
5-pin AMP connector) must be tied to signal ground (pins 2, 5, or 9) in
order to maintain proper EIA levels (see the following figure).
2. To connect directly to a local EIA RS-232C terminal, it is necessary to
use a null modem. To design the null modem into the cable, one must
switch received data (pin 2) with transmitted data (pin 3) on the RS·
232C male connector as shown in the following figure.
To mate to the 2 X 5-pin connector block, the following parts are needed:
Cable Receptacle (OTY 1)

AMP PN 87133-5
DEC PN 12-14268-02

Locking Clip Contacts (OTY 9)

AMP PN 87124-1
DEC PN 12-14267-00

Key Pin (pin 6) (OTY 1)

AMP PN 87179-1
DEC PN 12-15418-00

880

MXV11-AA,AC/M8047

ElA
MXV11 A

AS 232C

<5 f- -, CLEAR TO SEND (CB)
4

GND> 9

Rev DATA> 7

6 f- I

7500

+12 VDV

DATA SET READY (CC)

1/2W

F1~10

f- ~ REQUEST TO SEND (CA)

f- ......J DATA TERMINAL READY (CD)

<RECEIVE DATA (BB)
2 <TRANSMITTED DATA IRAI
7 <SIGNAL GROUND (AB)
1 <PROTECTIVE GROUND (AA)

ACV DATA> B

XMIT DATA> 3

GAD> 2

CABLE
EIA
AS-232C
CONNECTOR

MXV11-A
CONNECTOR

8218-05 Modem Cable

881

MODEM

MXV11-AA,AC/M8047

MXV11-A TO MODEM OR ACOUSTIC COUPLER

BC21B-05

' -_ _ _~" _ 1 . 5 M (5 FT)---~~~~~

ID
jB

15.2 M (50 F T ) - - - - - - · '
BC20M-50

DLV11.J )

-2.7M (9 FT)
(NOTE 2)

NOTES:
1. MODEM USED IS A "MANUAL TYPE"
SUCH AS BELL 103A WITH B04B.
2. DEC EIS RS-232C TERMINALS (VT52,
LA36, LS120, ETC.) COME EQUIPPED
WITH A 9 FT CABLE. NON-DEC EIA
RS-232C TERMINALS ARE CONNECTED
SIMILARLY EXCEPT 9 FT OF LENGTH
MUST BE DEDUCTED FROM THE TOTAL
CABLE LENGTH.
3. XX • CABLE LENGTH WH ICH MUST BE
SPECIFIED WHEN ORDERING_
MR-3270

MXV 11-A EIA Cable Configurations

882

MXV11-AA,AC/M8047

MXV11-A TO 20 MA TERMINAL

NOTES:
1. PRIS01 IS A SERIAL LINE PAPER TAPE
LOADER.
2. MXV11-A WILL NOT SUPPORT DLV11-KA
READER RUN CIRCUITS.
3. XX = CABLE LENGTH WHICH MUST BE
SPECIFIED WHEN ORDERING.

MXV 11-A 20 rnA Cable Configurations

883

MXV11-B/M7195

MXV11-B MULTIFUNCTION OPTION MODULE

GENERAL

The MXV11-B is a multifunction option module used with the PDP-11/23 and
KDJ11 processor systems. The MXV11-B read/write memory contains 128K bytes
of dynamic MOS RAM without parity. The MXV11-B is configured from 64K SIPS
(single in line package). Four SIPS provide 128K bytes (64K words) of memory
storage. Battery backup is supplied when jumpers are configured to enable that
feature and system supplied power is connected. This dual-height, multifunction
module option can operate on a 22-bit Q-Bus system, (up to 316 words) on an 18and 16-bit Q-Bus system unit.
Features

W/R MOS RAM memory
5 V battery backup for MOS RAMs
Read only memory (ROM)
ROM window map logic (page control register)
Two asynchronous, serial line ports (SLUO and SLU1)
Multiple LTC frequencies
LED diagnostic display register
Electrical· Specifications
Power Requirements - The following voltages are used by this module.
Voltage

Tolerance

Pins

+5 V
+12 V
+5 VB

±5%
±5%
±5%

AA2 BA2, BV1
AD2, BD2
AV1

Power dissipated in each power supply configuration is as follows.
No battery backup

+5V
Typ
Max

17.25 W
24.57 W

+12 V
Typ
Max

0.67W
0.71 W

884

MXV11-B/M7195
BaHery backup configuration
+5V
+5 VB
12.90 W
Typ
Typ
Max
15.95 W
Max

4.35 W
8.60 W

+12 V
0.67 W
Typ
Max 0.71 W

Data retention mode
VCC = 0 V, +12 V supply = 0
+5 VB
Typ
Max

4.35W
5.54W

Related Documentation
MXV11-B Technical Manual (EK-MXV1 B-TM)
MXV11-B User Guide (EK-MXV1 B-UG)
MXV11-B2 ROM Set User Guide (EK-MXVB2-UG)
MXV11-B Multifunction Option Module User Guide (EK-MXV1B-UG)
MXV11-B Field Maintenance Print Set (MP-01469-00)

Program Options and Defaults
Address/Vector
One MXV11-B

Channel 0
Channel 1

776500/300
777560/60

Two MXV11-Bs

Channel 2
Channel 3

776510/310
776520/320

Diagnostic Programs

CVMX.BAO

Test Functions
Serial lines
ROM
Clock option
Page Control Register (PCR)
Diagnostic Display Register (DDM)
Random Access Memory (RAM)

885

MXV11-B/M7195
Default Jumpers

The default jumpers are as shown below.

Default Configuration of Push-On Connectors

886

MXV11-B/M7195
Interface Connector Pins
Two 10-pin connectors, one for each serial line, are provided on the MXV11-B
module. The connector pins and signal functions are described below.

MXV11-B I/O Connector Pin Functions
Pin

Signal

Function

BRCLK

Baud rate clock. This output provides a clock signal at a frequency of 16 times the selected baud
rate. This pin is used as an output from the
MXV11-B and does not accept external clock
inputs.

Ground

XMIT+

Ground

Key, pin not provided

RCV-

Receiver input most negative

RCV+

Receiver input most positive

Ground

+12 V

Transmitter output

Power for the DLV11-KA option

Jumpers are used to configure:
Console mode
Reboot
MXV11-B2 boot ROM set Line time clock
System size
EVENT line
Boot and diagnostic ROMs Software programmed baud rates
Clock
Battery
Halt
User-supplied ROMs

887

MXV11-B/M7195
Baud Rates
Each serial line can be software programmed or strapped to 300, 1200, 9600, or
38,400 baud and is compatible with EIA RS-423 or RS-232 signal levels.
When bit 06 is set, the BEVENT line clamp is removed and LTC is functional. The
LTC address is 777546.
CAUTION
There should be only one source drive on the BEVENT line in any
system. On most systems, the system power supply provides the
bevent signal. this source must be disabled if the mxv11-b is used to
drive the line clock.
This register is a write-only register, but generates a reply on DATIO and DATIO B
lines. The DDR resides in location 777524 on the I/O page and is enabled when
the MXV11-B has its boot and console functions enabled.
Serial Line Unit Baud Rates

J11
J10
J9

JOB
JOB
GND

JOB to
GND
(J10 to J9)

SLUO (See Note)
JOA to
GND
(J11 to J9)
Baud Rates

R
R

R
I

300'
1200
9600
38.4K

J1A to
GND
(J8 to J9)
J9
J8
J7

GND
J1A
J1B

R
R

SLU1 (See Note)
J1B to
GND
J7 to J9)
Baud Rates

9600'
38.4K
300
1200

I
R

I
R = jumper removed
I = jumper inserted to ground
'Shipped configuration

NOTE
SOFT EN to GND jumper (J14 to J13) must be removed; otherwise
these jumpers have no effect. If the SOFT EN to GND jumper (J14 to
J13) is installed and PBRE bit 1 is set, baud rates are software
controlled.
888

MXV11-B/M7195
LED Diagnostic Display Register
The MXV11 has a diagnostic display register (DDR) which has four red LEDs to
show system diagnostics and one green LED to indicate power-on.

MXV11 B
MODULE

LEOs

,....----'---,

DIAGNOSTIC DISPLAY REGISTER
MR-12855

MXV11-B Diagnostic Register (LEDs)

UNUSED

08
WINDOW #1

UNUSED

00
WINDOW #0

Page Control Register
ROM Window Addresses for 16-,18-, and 22-bit Q-Bus

Q-Bus

Window 1
Start Addr
(octal)

End Addr
(octal)

Window 0
Start Addr
(octal)

End Addr
(octal)

16-bit

165000

165777

173000

173377

18-bit

765000

765777

773000

773377

22-bit

17765000

17765777

17773000

17773377

889

MXV11-B/M7195
ROM Window Map
Normalized
Window 0 ROM
Field
Address

0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

00000
01000
02000
03000
04000
05000
06000
07000
10000
11000
12000
13000
14000
15000
16000
17000
20000
21000
22000
23000
24000
25000
26000
27000
30000
31000
32000
33000
34000
35000
36000
37000

Maximum address for 2K by 8 PROM

Maximum address for 4K by 8 PROM

Maximum address for 8K by 8 PROM

890

MXV11-B/M7195

15
RCSR

UNUSED

INTERRUPT
EII1ABLE

OVERRUN
ERROR

UNUSED

XCSR

UNUSED

TRANSM ITIE R
READY

PROG.
BAUD
RATE 2

INTERRUPT
ENABLE
15
XBUF

PCR

UNUSED

WINDOW#l

WINDOW #0

LEDs (4)

UNUSED

DATA

DDRI

PROG.
BAUD
RATE
ENABLE
MAINTENANCE
BREAK

PROG.
BAUD
RATE 0

PROG.
BAUD
RATE 1

UNUSED

LTC

DATA

RBUF

UNUSED

ENABLE
CLOCK
MR·12854

MXV11-B Register Bit Formats

891

MXV11-BjM7195

Receiver Status Register Bit Assignments (RCSR)
Bit

Description

15-12

Unused

RA
Receiver active
read only

10-8

Unused

IE
Interrupt enable
read/write

5-0

A logic one indicates that the receiver is active.
Set at the center of the start bit of the input serial
data. Cleared at the expected center of the stop
bit at the end of the time prior to the leading
edge of RCV DONE. Also cleared by power up
sequence.

A logic one indicates that the serial interface has
received a character. If enabled by bit 6, receiver
done requests an interrupt. Receiver done is
cleared by reading the receiver data register or
by power-up sequence.

A logic one enables receiver interrupts; a zero
disables interrupts. Cleared by initialization.
Unused

892

MXV11-B/M7195
Receiver Data Buffer Bit Assignments (RBUF)
Description

Bit

ER
Error
read only

A logic one indicates that bit 13 and/or bit 14 is a
one. Cleared when the bit is read or cleared by
power-up sequence.

OE
Overrun error
read only

A logic one indicates a word in the receiver buffer had not been read when another word was
received and placed in the receiver buffer.
Cleared when read or by power-up sequence.

FE
Framing error
read only

A logic one indicates that a start bit was
detected, but there was no corresponding stop
bit. A framing error is generated when a break is
received. Cleared when read or by power-up
sequence.
Unused

12
11

RB
Receiver break
read only

10-8
7-0

This bit is set when serial-in (51) signal goes
from a mark to a space and stays in the space
condition for 11 bit times after serial reception
starts. This bit is cleared when the 51 signal
returns to the mark condition, or by power-up
sequence.
Unused

DATA
read only

These eight bits hold the most recent byte
received. When a new byte is transferred to the
data buffer, the RCV DONE in the RC5R is set.
Bit 0 is the L5B and bit 7 is the MSB. Cleared by
power-up sequence.

893

MXV11-B/M7195
Transmitter Status Register Bit Assignments (XCSR)
Bit

Description

15-8

Unused

TR
Transmitter read
read only

A logic one indicates the serial interface is ready
to accept a character into the transmitter data
register. If enabled by bit 6, transmitter ready
requests an interrupt. Transmitter ready is
cleared when data is written into the transmitter
data register. It is set by power-up sequence.

IE
Interrupt enable
read/write

A logic one enables transmitter interrupts. A logic zero disables interrupts. Cleared by
initialization.

5-3

BR2-BRO'
Programmable baud
rate select
read/write

When PBR-bit 1 in XCSR is set, these baud bits
determine the baud rate (set by software if SOFT
jumper connected to GND). If SOFT jumper is
connected to OPEN, baud rate is obtained via
wire-wrap. Bits BR2-BRO are cleared by PBR
inhibit (SOFT EN) or by power-up sequence.

MAINT
Maintenance
read/write

This bit facilitates a maintenance self-test. When
the bit is set, the the transmitter serial output is
connected to the receiver serial input and the
external serial input is disconnected. This bit is
cleared by initialization.

• Read only as a zero when programmable baud rate inhibit (PBRI) is asserted
low. PBRI is asserted low by connecting the SOFT EN to OPEN jumpers (J14 to
J15). In this case, the baud rate is determined by the wire-wrap jumpers
(J7-J11). Otherwise, with SOFT EN to GND (J14-J13), the bit is read/write. This
bit is cleared by power-up sequence or PBRI (SOFT EN to OPEN jumper -

J14-J15).

894

MXV11-B/M7195
Transmitter Status Register Bit Assigments (XCSR) (Cont)
Bit

Description
PBR·
Programmable baud
rate enable
Read/write when
software
programmable baud
rates enabled
(SOFT to GND
jumper); else read
only as O.

This bit selects between internal and external
baud rate selection. When set (enable), the baud
rate is determined by the PBR2-0 bits in this
register. When clear (inhibit), the baud rate is
determined by the J1, JO wire-wrap pins. This bit
is cleared by power-up sequence or SOFT to
OPEN jumper connected (programmable baud
rate inhibit (J14 to J1S).

When this bit is set, it causes the serial output
signal to go to a space condition. A space condition longer than a character time causes a framing error when it is received and is regarded as a
break. Cleared by bus initialization.

Break
read/write

895

MXV11-B/M7195
Transmitter Data Buffer Bit Assignments (XBUF)
Bit

Description

15-8

Unused

7-0

XMIT DATA

BUFFER
read/write

Transmitter data buffer - this byte register holds
a copy of the most recent byte written into it.
When a byte is written into this register, the
transmit ready (TR) bit in the XCSR register is
cleared. This byte is copied into the transmitter
serial output register whenever that register is
empty and the bit is clear. The TR bit is set when
a byte is copied from the transmitter data buffer
into the serial output register. Reading the contents of this register causes no other effect.
Cleared by power-up sequence.

896

MXV11-B/M7195
Definition of Cables
Cable

Application

Length

BC21B-05

EIA RS-232C modem cable to
interface with modems and
acoustic couplers (2 x 5 pin
AMP female to RS-232C male)

1.5 m (5 tt)

BC20N-05

EIA RS-232C null modem cable
to directly interface with a
local EIA RS-232C terminal
(2 x 5 pin AMP female to
RS-232C female)

1.5 m (5 tt)

BC20M-50

EIA RS-422 or RS-423 cable for
high-speed transmission
(19,200 baud) (2 x 5 pin AMP
female to 2 x 5 AMP female)

15 m (50 tt)

BC050-10

Extension cable used in
conjunction with BC21 B-05

3 m (10 tt)

BC050-25

Extension cable used in
conjunction with BC21 B-05

7.6 m (25 tt)

BC03M-25

Null modem extension cable
used in conjunction with
BC21B-05

7.6 m (25 ft)

NOTE

Strapped logic levels are provided on data terminal ready (DTR) and
request to send (RTS) to all operation of modems with manual provisions (such as Bell 103A data set with 804B auxiliary set).

897

MXV11-B/M7195

*ENGINEERING TEST POINTS

MXV11-B Jumper Locations

898

MXV11-B/M7195
Jumper Connections for MXV11-8 Summary
Jumper Name

Function

J1
J2

Connector for SLUO
Connector for SLU1

SLU connectors

J3
J4
J5

HALT
GND
RBOOT

OPEN

J7
J8
J9
J10
J11

J1B
J1A
GND
JOB
JOA

J12
J13
J14
J15

TP2
GND
SOFT EN
OPEN

Software programmable
baud rates

POC (W4)

J16
J17
J18

GND
PG L/DIR H
OPEN

Enables or disables direct
mode addressing

POC (W5)

J19
J20
J21

AL12H
NA12H
+5 V

PROM size and type in
direct mode addressing

POC (W6)

J22
J23
J24
J25

LTC COMM
50 Hz
60 Hz
800 Hz

Line time clock frequency

J26
J27
J28

OPEN
LTC EN IN
LTC EN OUT

Software control of line
time clock

POC (W7)

J29

TP3

For engineering use

J30
J31
J32

SLUA3
GND
SLUA2

Serial line unit starting
address

J33

SLUA1

Connection"

Halt and reboot functions

POC (W3)

Serial line unit baud rates

For engineering use

899

MXV11-B/M7195
Jumper Connections for MXV11-B Summary (Cont)
Jumper Name

Function

Connection*

J34
J35
J36
J37

DIR MODE BOOT
OPEN
GND
SM/LG

Direct mode boot and
small or large system

J38
J39
J40
J41
J42
J43

JU1
JU2
GND
JL1
JL2
JL3

Serial line unit vector
address

J44
J45
J46

BOOT L/PROM H
GND
OPEN

Boot ROM or user ROM

POC (W9)

J47
J48

CLOCK IN
CLOCK OUT

Master clock

POC (W10)

J49
J50
J51
J52
J53

PROM 1
PROM 2
GND
BSK1
BSK2

PROM size and PROM
start address

J54
J55
J56
J57
J58
J59
J60

AJ13
AJ14
AJ15
GND
AJ16
AJ17
AJ18

RAM starting address

J61
J62
J63

OPEN
GND
CONSOLE

Console mode

POC (W8)

·POC = Push-on connector
WW = Wire-wrap
NOTE
W1 and W2 are 0 ohm resistors associated with battery backup
option. Either one may be inserted but not both. The module is
shipped with W2 inserted.
900

MXV11-B/M7195
Miscellaneous Jumper Configurations
Connector

Connection

Description

J63
J62
J61

CONSOLE
GND
OPEN

GND to OPEN
(J62 to J61)

Enables console mode. SLU is
fixed at address 77560 and vector address at 60. Select SLU 0
address from Table B and vector
from Table C.

J63
J62
J61

CONSOLE
GND
OPEN

CONSOLE to GND Disables console mode. For SLU
(J63 to J62)
addresses, refer to Table Band
vectors from
Table C.

J46
J45
J44

OPEN
GND
BOOT L/PROM H

BOOT LtpROM H
to GND
(J44 to J45)

Inserted when MXV11-B2 boot
ROM set is installed in sockets
XE19 and XE29. Enables the following registers to be addressed
if the console GND to OPEN
jumper (J62 to J61) is installed:
Page control register
Line time clock control
Diagnostic display register.

J46
J45
J44

OPEN
GND
BOOT L/PROM H

GND to OPEN
(J45 to J46)

Inserted when ROMs are for user
code (not bootstrap code). See
Table A for addresses.

J37
J36
J35

SM/LG SYS
GND
OPEN

SM/LG SYS to
GND
(J37 to J36)

This is installed when the
MXV11-B is connected in a 022
bus backplane. Recognizes
BDAL <21 :00> L. This jumper
must be installed if RAM is
addressed above 128K words.

J37
J36
J35

SM/LG SYS
GND
OPEN

GND to OPEN
(J36 to J35)

Installed when the MXV11-B is
connected to a 16- or 18-bit 0BUS. Recognizes BDAL <17:00>
L only.

J36
J35
J34

GND
OPEN
DIRECT MODE
BOOT

DIR MODE BOOT
to OPEN
(J34 to J35)

Module not wired for direct mode
boot.

901

MXV11-B/M7195
Miscellaneous Jumper Configurations (Cont)
Connector

Connection

Description

J36
J35
J34

GND
OPEN
DIRECT MODE
BOOT

DIR MODE BOOT
to GND
(J34 to J36)

Module enabled for direct mode
boot. This jumper must be
installed when the user boot is
directly addressed.

J18
J17
J16

OPEN
PG LIDIR H
GND

PG LIDIR H to
GND
(J17 to J16)

Enables ROM boot map option
and page mode on the MXV11-B.
Disables user PROM addresses
below 16K.

J18
J17
J16

OPEN
PG L/DIR H
GND

PG L/DIR H
to OPEN
(J17 to J18)

Enables PROM sockets XE19
and XE28 to be used for user
defined PROMs. In this case,
these sockets can only be
addressed in memory locations
below the 16K word boundary.

J48
J47

CLOCK OUT
CLOCK IN

CLOCK OUT to
CLOCK IN
(J48 to J47)

Factory test. Do not remove. This
is the master clock, and provides
on-board refresh and the charge
pump to generate -12 V.

J3
J4
J5
J6

HALT
GND
RBOOT
OPEN

HALT to GND
(J3 to J4)

Enables SLU 1 (console port) to
halt the processor upon receiving
a break character.

J3
J4
J5
J6

HALT
GND
RBOOT
OPEN

HALT not connected to GND

Disables CPU halt function.

J3
J4
J5
J6

HALT
GND
RBOOT
OPEN

RBOOTto GND

Causes a system reboot when a
break condition is received from
SLU 1. Forces BDC OK-H low on
the bus.

NOTE
HALT to GND (J3 to J4) and RBOOT to GND (J5 to J4) cannot be
simultaneously jumpered.

902

MXV11-B/M7195
Miscellaneous Jumper Configurations (Cont)
Connector

Connection

Description

J3
J4
J5
J6

HALT
GND
RBOOT
OPEN

GND to OPEN
(J4 to J3)

Disables reboot function.

J26
J27
J28

OPEN
LTC EN IN
LTC EN OUT

LTC EN IN to
LTC EN OUT
(J27 to J28)

Allows LTC to be software controlled. Enables control of
BEVENT L on the bus via bit 06
of the LTC register. When bit 6 of
LTC register is 0, BEVENT L will
be asserted constantly low. This
inhibits LTC interrupts. To
address the LTC register
(777546), the MXV11-B must be
in boot mode (BOOT LtpROM H
to GND) (J44 to J45) and SLU1
must be the console port (CONSOLE to GRD removed).

J26
J27
J28

OPEN
LTC EN IN
LTC EN OUT

LTC EN IN
to OPEN
(J27 to J26)

Prevents bits 06 of the LTC register from controlling the BEVENT
L line.

J22
J23

LTC COMM
50 Hz

LTC COMM to
50 Hz
(J22 to J23)

When installed, the BEVENT line
is driven from a 50 Hz crystal
derived clock. If the line time
clock jumper is installed, the
clamp has to be turned off by the
software for the clock to drive the
BEVENT line.

J24

60 Hz

LTC COMM to
60 Hz
(J22 to J24)

When installed, the BEVENT line
is driven from a 60 Hz crystal
derived clock. If the line time
clock jumper is installed, the
clamp has to be turned off by the
software for the clock to drive the
BEVENT line.

CAUTION
LTC EN IN to LTC EN OUT (J27 to J28) should not be connected if the
CPU has an LTC control register.

903

MXV11-B/M7195
Miscellaneous Jumper Configurations (Cont)
Connector

Connection

Description

J25

800 Hz

LTC COMM to
800 Hz
(J22 to J25)

When installed, the BEVENT line
is driven from an 800 Hz crystal
derived clock. If the line time
clock jumper is installed, the
clamp has to be turned off by the
software for the clock to drive the
BEVENT line.

J15
J14
J13

OPEN
SOFT EN
GND

SOFT EN to GND
(J14 to J13)

Enables software programmable
baud rates for both SLU1 and
SLUO via the CSR. The baud rate
jumpers in Table B have no effect
if the PBRE bit is set.

J15
J14
J13

OPEN
SOFT EN
GND

SOFT EN to OPEN Baud rates are selected from
Table B.
(J14 to J15)

W1
(0 ohm resistor)
connected

Battery backup. +5 V is supplied
by user on backplane pin AV1.
DIGITAL does not supply battery
backup.

W2
(0 ohm resistor)
connected

No battery backup.

J21
J20
J19

+5 V
NA12H
BA12H

NA12H to +5 V
(Normalized
address 12)
(J20 to J21) to
(Buffered Address
line 12)

Specifies 2K user UVROMs
(2716) installed and direct mode
addressing

J21
J20
J19

+5 V
NA12H
BA12H

NA12H to BA12H
(J20 to J19)

Specifies 4K or 8K user-supplied
ROM in direct mode addressing.

NOTE
One of these jumpers (50, 60, or 800 Hz) should be installed: 1) If no
external BEVENT source is provided in the system, and 2) If the user
desires this source. Power supplies manufactured by DIGITAL normally supply BEVENT L to the backplane.
904

MXV11-B/M7195
NOTE
There are cases where none of these jumpers (+5 V, NA4H, and
AL12H) should be connected. In these cases, the push-on connector
must be completely removed or must be connected to one of the
outside pins to hold the connector. There is no open pin associated
with these jumpers. For example, if 2K non-UV PROMs or the MXV11B2 ROM is to be installed, these jumpers are all disconnected.

Table A.

JS1
JS2
JS3

GND

BSK1
BSK2
I

Jumpers for PROM Starting Address

BSK2 to
GND
(J53 to J51)

BSK1 to
GND
(J52 to J51)

User PROM
Starting Address (octal)
(Note)

R
R
I
I

R
I
R
060000

000000'
020000
040000

R = jumper removed
I = jumper inserted to ground
• Shipped configuration. Remove all jumpers from BSK1 (JS2) and BSK2 (JS3) if
not in user mode.

NOTE
These addresses are for user supplied ROMs only. Jumpers BOOT
L/PROM H to GND (J44 to J45) and PG L/DIR H to GND (J17 to J16)
must be removed.

90S

MXV11-BjM7195
Table B.

J33
J32
J31
J30

SLUA1
SLUA2

GND
SLUA3

Serial Line Unit Starting Address Jumpers

SLUA3
to GND
(J30 to
J31)

SLUA2
to GND
(J32 to
J31)

SLU1
to GND
(J33 to
J31)

R
R
R
R
I

R
R
I
I
R
R

R
I
R
I
R
I
R

Starting
Address
SLUO

SLU1
(See
Note)

776500·
776510
776520
776530
776540
776550
776560
776570

776510·
776520
776530
776540
776550
776560
776570
776600

R = jumper removed
I = jumper inserted to ground
·Shipped configuration

NOTE
If the GND to OPEN jumper (J62 to J61) is installed (console enabled).
the SLU1 address is fixed at the standard console address of 777560
and this column does not apply.

906

MXV11-B/M7195
Table C.

J43
J42
J41
J40
J39
J38

JL3
JL2
JL1
GND
JU2
JU1

Jumpers for SLU Vector Addresses

JU2
to GND
(J39 to
J40)

JU1
to GND
(J38 to
J40)

JL3
to GND
(J43 to
J40)

JL2
to GND
(J42 to
J40)

JL1
to GND
(J41 to
J40)

SLUO

SLU1
(See
Note)

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

R
R
R
R
R
R
R
R
I
I
I
I
I

R
R
R
R
I

I
R
R
R
R
I
I

R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R

R
R
R
R
I
I

R
R
I
I
R
R

R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R
t
R
I
R
I
R
I
R
I

300'
010
020
030
040
050
060
070
100
110
120
130
140
150
160
170
200
210
220
230
240
250
260
270
300
310
320
330
340
350
360
370

310'
020
030
040
050
060
070
100
110
120
130
140
150
160
170
200
210
220
230
240
250
260
270
300
310
320
330
340
350
360
370
Undefined

I
R
R
R
R
R
R
R
R
I

I
R
R
R
R
I

jumper inserted from specified pin to ground. Where multiple connections are
made, they are daisy-chained.
R = jumper removed
'Shipped configuration
=

NOTE
If the GND to OPEN jumper (J62 to J61) is installed (console enabled).
SLU1 vector address is fixed at 60 and this column does not apply.
907

MXV11-B/M7195
PROM Jumpers

J19
J20
J21

BA12H
NA12H
+5 V

NA12H to
BA12H
(J20 to J19)

NA12H
to +5 V
(J20 to J21)

R
I

R
R

Description

Page mode - Boot ROM
for 2K by 8 non-UV
PROMs, 4K by 8 or 8K by
8 PROMs
Direct mode - for 2K by 8,
non-UV PROMs, 4k by 8,
or 8K by 8 PROMs'
Direct mode - for 2K by 8
UV PROMs

R = jumper removed
I = jumper inserted
'Shipped configuration

Jumpers to Configure PROM Size

J51
J50
J49

GND
PROM 2
PROM 1

PROM 2
to GND
(J50 to J51)

PROM 1
to GND
(J49 to J51)

R
R
I

R
R

PROM Size
No ROMs'
2K by 8
4K by 8
I

8K by 8t

R = jumper removed
I = jumper inserted
• Shipped configuration. Additional jumpers are required depending on user
mode/boot mode and direct addressing page addressing. Refer to the last three
tables in this section.
t If the MXV11-B2 Boot Diagnostic ROM set is installed, install PROM 2 to PROM
1 to GND jumper (J50 to J49 to J51).

908

MXV11-B/M7195
RAM Starting Address Jumpers
AJ18
AJ16
AJ14
AJ13
AJ17
AJ15
RAM
to GND to GND to GND to GND to GND to GND Starting
(J60 to (J59 to (J58 to (J56 to (J55 to (J54 to Address
J57)
J57)
J57)
J57)
J57)
J57)
(Words)

J60
J59
J58
J57
J56
J55
J54

AJ18
AJ17
AJ16

00
01
02
GND 03
AJ15 04
AJ14 05
AJ13 06
07
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
40
41
42
43
44
45
46
47

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

R
R
R
R
R
R
R
R

R
R
R
R

R
R
R
R
I

I
I

R
R

I
I

R
R

I
I

R
R

I
I
I
I

R
R
R
R
R
R
R
R

909

R
R
R
R
R
R
R
R

I
I

R
R
R
R
R
R
R
R

R
R

R
R
R
R

R
R

I
I

R
R

I
I

R
R
R
R

R
R

R
R
R
R
R
I

R
R

I
I

R
R
R
R

R
R

I
I

R
R

R
R
R
R
R
R

O'
4K
8K
12K
16K
20K
24K
28K
32K
36K
40K
44K
48K
52K
56K
60K
64K
68Kt
72Kt
76Kt
80Kt
84Kt
88Kt
92Kt
96Kt
100Kt
104Kt
108Kt
112Kt
116Kt
120Kt
124Kt
128Kt
132Kt
136Kt
140Kt
144Kt
148Kt
152Kt
156Kt

MXV11-B/M7195
RAM Starting Address Jumpers (Cont)
AJ17
AJ18
AJ16
AJ15
AJ14
AJ13
RAM
to GND to GND to GND to GND to GND to GND Starting
(J60 to (J59 to (J58 to (J56 to (J55 to (J54 to Address
J57)
J57)
J57)
J57)
J57)
J57)
(Words)
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77

R
R
R
R
R
R
R
R

R
R
R
R

I
I

R
R
R
R
R
R
R
R

I
I
I

R
R
R
R
I
I
I
I

R
R
R
R

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

I
I

R
R

R
R
R
R
R
R
R
R
R
I

160Kt
164Kt
168Kt
172Kt
176Kt
180Kt
184Kt
188Kt
192Kt
196Kt
200Kt
204Kt
208Kt
212Kt
216Kt
220Kt
224Kt
228Kt
232Kt
236Kt
240Kt
244Kt
248Kt
252Kt

jumper inserted from designated pin to GND. Where multiple connections are made, they are daisy-chained.
jumper removed .

• Shipped configuration
t To use address above 64K words, SM/LG SYS TO GND jumper (J37 to J36)
must be installed

910

MXV11-B/M7195
NOTE
Be careful when configuring the MXV11-B RAM when ROM is used in
the USER ROM address space. USER ROM address space is defined
as bus addresses 0-16K, (00000-100000) on 4K boundaries. The RAM
start address must be higher than the last location of the ROM or dual
responses from both the RAM and ROM will occur. The chart below
shows several examples of right and wrong ways of assigning RAM
memory start addresses.

ROM
Size

ROM
Start

RAM
Start

RAM
End

Comments

8K
8K
4K
4K
8K

OK
4K
OK
OK
4K

4K
OK
4K
12K
12K

68K
64K
68K
76K
76K

Wrong, 4K overlap (4K--.8K)
Wrong, 8K overlap (4K--.12K)
Right, no overlap
Right, no overlap:j:
Right

:j: Address space gap usually not recommended but up to user to decide
depending on application.
Jumper Connections for PROM Sizes in User Mode
Jumpers

No PROMs

2K by 8

4K by 8

8K by 8

J16
J17
J18

(GND)
(PG L/DIR H)
(OPEN)

J17 to J18

J17toJ18

J19
J20
J21

(BA12H)
(NA12H)
(+5 V)

J19 to J20

J20 to J21

J19 to J20

J19toJ20

J44
J45
J46

(BOOT L/PROM H) J45 to J46
(GND)
(OPEN)

J45 to J46

J49
J50
J51

(PROM1)
(PROM2)
(GND)

J49 to J51

J50 to J51

J49 to J50
to J51

NOTE
Jumper connections are indicated. For example, in the 2K by 8 PROM,
J17 is connected to J18, J20 is connected to J21, J45 is connected to
J46, and J49 is connected to J51.
911

MXV11-B/M7195
Jumper Connections for PROM Sizes in Boot Mode (Page Addressing)
Jumpers

No PROMs

2K by 8'

4K by 8

8K by 8

J16 to J17

J16toJ17

J16 to J17

J19 to J20

J16
J17
J18

(GND)
(PG L/DIR H)
(OPEN)

J17 to J18

J19
J20
J21

(BA12H)
(NA12H)
(+5 V)

J19 to J20

J44
J45
J46

(BOOT LtpROM H) J45 to J46
(GND)
(OPEN)

J44 to J45

J49
J50
J51

(PROM1)
(PROM2)
(GND)

J49 to J51

J50 to J51

J49 to J50
to J51

*2K by 8 UV PROM cannot be used in page mode.
NOTE
Jumper connections are indicated. For example, in the 8K by 8 PROM,
J16 is connected to J17, J19 is connected to J20, J44 is connected to
J45 and J49, J50 and J51 are connected.

912

MXV11-B/M7195
'Jumper Connections for PROM Sizes in Boot Mode (Direct Addressing)
Jumpers

No PROMs

2K by 8

4K by 8

8K by 8

J16
J17
J18

(GND)
(PG L/DIR H)
(OPEN)

J17 to J18

J17toJ18

J17 to J18

J19
J20
J21

(BA12H)
(NA12H)
(+5 V)

J19 to J20

J20 to J21

J19 to J20

J44
J45
J46

(BOOT L/PROM H) J45 to J46
(GND)
(OPEN)

J44 to J45

J49
J50
J51

(PROM1)
(PROM2)
(GND)

J49 to J51

J50 to J51

J49 to J50
to J51

J34
J35
J36

(DIR MODE BOOT)
(OPEN)
(GND)

J34 to J36

NOTE
Jumper connections are indicated. For example, in the 2K by 8 PROM,
J17 is connected to J18, J20 is connected to J21, J44 is connected to
J45, J49 is connected to J51, and J34 is connected to J36.

913

RKV11-D/M7269

RKV11-D BUS INTERFACE
FOR RKV11-D DISK DRIVE CONTROLLER
Amps

Bus loads

Cables

+5
+12
1.8 max.
0

AC
DC
1.93 1

(2) BC05l + M993-Y A

Standard Address
RKDS
RKER
RKCS
RKWC
RKBA
RKDA
RKDB

(Drive Status)
(Error)
(Control/Status)
(Word Count)
(Bus Address)
(Disk Address)
(Data Buffer)

177400
177402
177404
177406
177410
177412
177416

Vector
220
Diagnostic Programs
Refer to Appendix A.
NOTE
The logic test programs should be run first, then the dynamic
test, and finally the performance exerciser.
Related Documentation
RKV11-D Disk Drive Controller User's Manual (EK-RKV11-0P-001)
RKV11-Disk Drive Controller Technical Manual (EK-RKV11-TM-001)
Field Maintenance Print Set (MP00223)
RK05/RK05J/RK05F Disk Drive Maintenance Manual (EK-RK5JF-MM-00 1)
RK05/RK05J Disk Drive Preventive Maintenance Manual
(EK-HK05J-PM- 001)
RK05F DEC Disk Drive Preventive Maintenance Procedure
(ED-RK05F-PM- 001)
Microcomputer Interfaces Handbook (EB-20 175-20)

914

RKV11-D/M7269

c
c

1
JUMPER SETTINGS

INSTALLED - Wl, W2, W3, W6, W7, Wll, W17
REMOVED - W4, W5, WB, W9, Wl0, W12, W13, W14, W15, W16

INTERRUPT
VECTOR
JUMPERS

r:::::I~IIIII::::
BUS
ADDRESS
JUMPERS

NOTE,
NORMALLY INSTALLED
JUMPERS ARE SHOWN AS
SOLID LINES.

M7269 Jumpers

915

RKV11-D/M7269
7

~~.~--"-~.~~
15

I, I .; .: ' I .: .; , I .;
::::~ULE -

CONFIGURED ---+
ADDRESS (1714001

I .: < I .: .: I
06

TT T TiT TTT
I

I I I I I I I I I
I

I = INSTALLED
R = REMOVED

DEVICE ADDRESS
MR-0803

2
15

~~~
08

JUMPER
I I I I I I I I
::::OULE-T TiT TTTT
ON

CONFIGURED - - - - - - . R

I" INSTALLED
R eREMOVED

ADDRESS (2201
VECTOR ADDRESS

Jumper settings on the three RKV 11-0 modules are identical to those in
the standard RK 11-0 configuration. A breakdown is given below for reference. There are no jumpers on M7268.

Module

Installed

Removed

M7254*
M7255* *
M7256

W1, W4, W6, W7
W1, W2, W6
W2, W5, W7

W2, W3, W5
W3, W4, W5
W1, W3, W4, W6, W8

Interrupt priority jumper (BR4-7) in socket E8 is not required
since the RKV11-0 was designed for single-line interrupt
scheme only.
2.88 MHz crystal used DEC PN 18-10694-3.

916

RKV11-D/M7269

0---00

0--0

M7254

917

RKV11-D/M7269

0---0

~W6

M7255

918

RKV11-0 /M7269

100
W1

W3
00

W4 W7

M7256

919

RKV11-D/M7269

M7254

STATUS
CONTROL

M7255

DISK
CONTROL

M7256

DATA
PATHS

M7268

BUS
ADAPTER

H78DPOWER
SUPPLY

MR-0762

RKV 11-0 Module Utilization
Drive Status Register (RKDS)
Address =

177400

NOTE
This register is a read-only register, and contains the selected
drive status and current sector address_

Bit Definitions
Bit

Function

00-03

Sector Counter (SC) - These four bits are the current sector address of the selected drive. Sector address 00 is defined as the
sector following the sector that contains the index pulse.

Sector Counter Equals Sector Address (SC = SA) - Indicates
that the disk heads are positioned over the disk address currently held in the sector address register.

Write-Protect Status (WPS) - Sets when the selected disk is in
the write-protected mode.

Read/Write/Seek Ready (R/W /S ROY) - Indicates that the selected drive head mechanism is not in motion, and that the drive
is ready to accept a new function.
Drive Ready (DRY) - Indicates that the selected disk drive com·
plies with the following conditions.

920

RKV11-D/M7269
Bit Definitions (Cont)
Bit

Function
1,
2,
3,
4,
5,
6,
7,

The drive is properly supplied with power.
The drive is loaded with a disk cartridge,
The disk drive door is closed,
The LOAD/RUN switch is set to RUN,
The disk is rotating ,at a proper speed,
The heads are properly loaded,
The disk is not in a DRU (bit 10 or RKDS) condition,

Sector Counter OK (SOK) - Indicates that the sector counter
operating on the selected drive is not in the process of changing, and is ready for examination, If this bit is not set, the sector
counter is not ready for examination, and a second attempt
should be made,

Seek Incomplete (SIN) - Indicates that due to some unusual
condition, to seek function cannot be completed, Can be accompanied by RKER 15 (drive error), Cleared by a drive reset
function,

Drive Unsafe (DRU) - Indicates that an unusual condition has
occurred in the disk drive, and it is unable to properly perform
any operations, Reset by setting the RUN/LOAD switch to
LOAD, If, when the switch is returned to RUN, the condition recurs, an inoperative drive can be assumed, and corrective maintenance procedures should begin, Can be accompanied by
RKER 15 (drive error),

RK05 Disk on Line (RK05) - Always set, to identify the selected
disk drive as RK05,

Drive Power Low (DPL) - Sets when an attempt is made to initiate a new function, or if a function is actively in process when
the control senses a loss of power to one of the disk drives, Can
be accompanied by RKER 15 (drive error), Reset by a BUS INIT
or a control reset function,

13-15

Identification of Drive (lD) - If an interrupt occurs as the result of
a hardware poll operation, these bits will contain the binary representation of the logical drive number that caused the interrupt.

921

RKV11-D/M7269
Error Register (RKER)
Address = 177402
NOTE
This ilS a read-only register.

CP-3138

Bit Definitions
Bit

Function

Write Check Error (WCE) - Indicates that an error was encountered during a write check function as a result of a faulty bit
comparison between disk data and memory data. Clears upon
the initiation of a new function. This is a soft error condition.

Checksum Error (CSE) - Sets while performing a read function
as a result of a faulty recalculation of the checksum. Cleared
upon the initiation of any new function. This is a soft error condition.

02-04

Unused.

The remaining bits of the RKER are all hard errors, and are cleared only by
a BUS INIT or a control reset function.

Bit Definitions
Bit

Function

Nonexistent Sector (NXS) - Indicates that an attempt was
made to a sector address greater than 138 .

Nonexistent Cylinder (NXC) - Indicates that an attempt was
made to initiate a transfer to a cylinder address greater than
3128 .

Nonexistent Disk (NXD) - Indicates that an attempt was made
to initiate a function on a nonexistent drive.

Timing Error (TE) - Indicates that a loss of timing pulses for at
least 5 itS has been detected.

922

RKV11-D/M7269
Bit Definitions (Cont)
Bit

Function

Oata Late (OL T) - Sets during a write or write check function
when the multibuffer file is empty and the operation is not yet
complete. Sets during a read function when the multibuffer file is
filled and the operation is not yet complete.

Nonexistent Memory (NXM) - Sets if memory does not respond
with a RPLY within 20 f.Ls of the time when the RKV11-0 becomes bus, master during a OMA sequence. Because of the
speed of the RK05 disk drive, it is possible that NXM will be accompanied by RKER 09 (data late).

Programming Error (PGE) - Indicates that RKCS 10 (format)
was set while initiating a function other than read or write.

Seek Error (SKE) - Sets if the disk head mechanism is not properly positioned while executing a normal read, write, read
check, or write check function. The control checks 16 times before flagging this error. A simple jumper change will force the
control to check just once.

Write Lockout Violation (WLO) - Sets if an attempt is made to
write on a disk that is currently write protected.

Overrun (OVR) - Indicates that during a read, write, read check,
or write check function, operations on sector 138, surface 1 of
cylinder address 3128 were finished, and the RKWC has not yet
overflowed. This is essentially an attempt to overflow out of a
disk drive.

Orive Error (ORE) - Sets if a function is either initiated or in process, and
a.

one of the drives in the system senses a loss of either ac or
dc power; or

the selected drive is not ready, or is in some error condition.

923

RKV11-D/M7269
Control Status Register (RKCS)
Address =

177404

UNuseo

UNUSED

Bit Definitions
Bit

Function

Go - This bit can be loaded by the operator and causes the control to carry out the function contained in bits 01-03 of the
RKCS (functions). Remains set until the control actually begins
to respond to go, which may take from 1 itS to 3.3 ms, depending on the current operation of the selected disk drive (to protect the format structure of the sector). Write only.

01-03

Function - The function register, or function bits, are loaded
with the binary representation of the function to be performed by
the control when a GO command is initiated. These bits are
loaded by the program and cleared by BUS INIT. Read/write.
The binary codings are as follows.

04, 05

Bit 3

Bit 2

Bit 1 Operation

0
0
0
0

0
0

0
1
0
1
0
1
0

1
0
0
1

Control Reset
Write
Read
Write Check
Seek
Read Check
Drive Reset
Write Lock

Unused. The RK 11-0 uses these bits. Since the POP-11/03 bus
structure has no provision for extended addressing, no connection is made to the bus from these bits on the RKV 11-0.
They will respond as two unused read/write bits in the status
register; but, like the RK 11-0 they, will increment should the
RKBA overflow.

924

RKV11-D/M7269
Bit Definitions (Cont)
Bit

Function

Interrupt on Done Enable (IDE) - When set, causes the control
to issue a bus request and interrupt to vector address 220 if:
a.
b.
c.
d.

a function has completed activity
a hard error is encountered
a soft error is encountered and bit 08 of the RKCS (SSE) is
set
RKCS 07 (ROY) is set and go is not set.

Read/write.
07

Control Ready (ROY) - Indicates that the control is ready to
perform a function. Set by INIT, a hard error condition, or by the
termination of a function. Cleared by go being set. Read only.

Stop on Soft Error (SSE) - If a soft error is encountered when
this bit is set:
a.

all control action will stop at the end of the current sector if
RKCS 06 (IDE) is reset, or

all control action will stop and a bus request will occur at
the end of the current sector if RKCS 06 (IDE) is set.

Read/write.
09

Unused.

Format (FMT) - FMT is under program control, and must be
used only in conjunction with normal read and write functions.
Used to format a new disk pack or to reformat any sector
erased due to control or drive failure. Alters the normal write operation, under which the header is rewritten each time the associated sector is rewritten, in that the head position is not checked for proper positioning before the write. Alters the normal read
operation in that only one word, the header word, is transferred
to memory per sector. For example, a three-word read function
in format mode will transfer header words from three consecutive sectors to three consecutive memory locations for
software checking. Read/write.

Inhibit Incrementing the RKBA (IBA) - Inhibits the RKBA from incrementing during a normal transfer function. This allows data
transfers to occur to or from the same memory location throughout the entire transfer operation. Read/write.

Unused.

925

RKV11-D/M7269
Bit Definitions (Cont)
Bit
13

Function
Search Complete (SCP) - Indicates that the previous interrupt
was the result of some seek or drive reset function. Cleared at
the initiation of any new function. Read only.

Hard Error (HE) - Sets When any of RKER 05-15 are set. Stops
all control action, and processor reaction is dictated by RKCS
06 (IDE), until cleared, along with RKER 05-15, by INIT or a control reset function. Read only.

Error (ERR) - Sets when any bit of the RKER sets. Processor
reaction is dictated by RKCS 06 and RKCS 08 (IDE and SSE).
Cleared if all bits in the RKER are cleared. Read only.

Word Count Register (RKWC)
Address =
15

177406
14

Bit Definition
Function
WCOO-WC15 - The bits in this register contain the 2's complement of words to be affected or transferred by a given function. The register increments by 1 after each word transfer.
When the register overflows (all WC bits go to 0), the transfer is
complete and RKV 11-0 operation is terminated at the end of the
present disk sector. However, only the number of words specified in the RKWC are transferred. Read/write.

Bit
00-15

Current Bus Address Register (RKBA)
Address = 177410
15

Bit
00-15

Bit Definition
Function
BAOO-BA 15 - The bits in this register contain the bus address
to or from which data will be transferred. The register is incremented by two at the end of each transfer. Read/write.
926

RKV11-D/M7269
Disk Address Register (RKDA)
Address =

177412

CYLINDER ADDRESS

NOTE
This register will not respond to commands while the controller
is busy. Therefore, RKDA bits are loaded from the bus data
lines only in the control ready (RDY - bit 07 of the RKCS) state,
and are cleared by BUS INIT and control reset. The RKDA is incremented automatically at the end of each disk sector.

Bit Definitions
Bit

Function

00-03

Sector Address (SA) - Binary representation of the disk sector
to be addressed for the next function. The largest valid address
(or number) for the sector address is 138 .

Surface (SUR) - When set, enables the lower disk head so that
operation is performed on the lower surface; when reset, enables the upper disk head.

05-12

Cylinder Address (CYL ADDR) - Binary representation of the
cylinder address currently being selected. The largest valid address or number for the cylinder address is 312 .

13-15

Drive Select (DR SEL) - Binary representation of the logical
drive number currently being selected.

927

RKV11-D/M7269
Data Buffer Register (RKDB)
Address = 177416

ID::.:. ,. : 13 : 12: 11 : I. : .. : 08 : .7 : .. : : : : :
06

Bit Definition
Bit

Function

00-15

0800-0815 - The bits of this register work as a general data
handler in that all information transferred between the control
and the disk drive must pass through this register. Loaded from
the bus only while the RKV11-0 is bus master during a OMA sequence. Read only.

NOTE
Address 177414 is unused.

928

RKV11-D/M7269

TO M993-VA
IRKOS)

TO M7269
(LSI-11 BUS)

M7268

M993-YA
TOP

GROOVE

~ ~~---------------~--J4~~N
TOP

M1268
M7269

L-_ _ _ _-r~~,--~TOP
BC05L

BC05L

TOPL-_ _ _ _ _ _ _ _ _- l
MR-0763

RKV 11-0 Cable Connection

929

RL V11/M8013,4

RLV11 CONTROLLER MODULES

Amps
+5
6.5

Bus Loads
+12
1.0

AC
3.2

Transition Bracket Assembly
Terminator

Cables
BC08R-XX
70-12122 (1 per drive)
70-12415-00
70-12293-00

Standard Addresses
CSR
BAR
DAR
MPR

174400
174402
174404
174406

Standard Vectors
160

Diagnostic Programs
Refer to Appendix A.

930

RLV11/M8013,4
1

rA-.,....----A----, ,~-~-~.,.-----A-----, ,,....-~---.. , - - - " " - - - ,

ADDRESS SWITCH
1 '" SWITCH ON
0;; SWITCH OFF

Address Selection

,----'-----, ,.....--A------ ,--------'----15

09
NOT USED

I I I I
0

HARDWIRED

VECTOR SWITCH
N

SWITCH POSITION

N=ON
F = OFF

Vector Selection

Related Documentation
RL VII Controller Technical Description Manual (EK-RLV 11-TD)
RLV11 Field Maintenance Print Set (MP00635)
RL01 Field Maintenance Print Set (MP00347)
RL02 Field Maintenance Print Set (MP00553)
RL01 Disk Drive IPS (EK-ORL01-IP)
RL02 Disk Drive IPS (EK-ORL02-IP)
RLOI/RL02 User's Guide (EK-RL012-UG)
RLOI/RL02 Pocket Service Guide (EK-RL012-PG)
Microcomputer Interfaces Handbook (ES-20 175-20)

NOTE
The M8013 must be installed above the M8014. The RLV11
controllers can only be used in a backplane built as an H9273
(slots A and B = LSI bus and slots C and D = interboard bus).
The BA 11-N box currently Is the only box that contains an
H9273 backplane.

931

RL V11 /M8013,4

BC06R CABLE

RED STRIPE

W2 Q

rn vco

POT 15 K)

GND TP

TO DRIVE

0 VCI TP

o VCO TP

COMPONENT SIDE 1
RLVll DRIVE BOARD M8013
JUMPERS W2 & W4 IN PLACE FOR E PROM USE
JUMPERS Wl & W3 IN PLACE FOR MASKED ROM USE
Wl

R~4~D
0~
OR
W4 W3
EPROM

D
DVl

DAl

C
CYl

CAl

BYl

8Al

NOTE
JUMPERS ARE O~OHM COMPOSITION RESISTORS

RL V 11 Drive Module (MBO 13)

932

AYl

AAl

RLV11/M8013,4

COMPONENT SIDE 1
RLVll BUS INTERFACE BOARD M8014

MSBI
BUS ADDRESS SWITCH
LSB

MSB~ VECTOR SWITCH
LSB

OAl

OYl

CYl

CAl

BYl

BAl

AYl

AAl

RL V 11 Bus Interface Module (MaO 14)

CONTROL STATUS REGISTER ICSR)

OCRC
,----...,
11

774400

HCRC

~----R-EA-OO~N-Ly----~A-------RE-A~Dm~R-IT-E------~~
ONLY

Control Status Register

933

RLV11/M8013,4
CSR Bit Definitions
Bit

Function

Drive Ready (DRDY) - When set, this bit indicates that the selected drive is ready to receive a command (no seek operation
in progress). The bit is cleared when a seek operation is initiated and set when the seek operation is completed.

1-3

Function Code - These bits are set by software to indicate the
command to be executed.
F2 F1 FO Command

WRITE CHECK

0
0

MAINTENANCE MODE

Octal Code

0
0

GET STATUS

SEEK

READ HEADER

WRITE DATA

READ DATA

READ DATA WITHOUT
HEADER CHECK

Command execution starts when CRDY (bit 7) of the CSR is
cleared by software. In a sense, bit 7 can be considered a negative go bit.
4-5

Bus Address Extension Bits (BA 15, BA 17) - Two most significant bus address bits. Read and written as bits 4 and 5 of the
CSR, they function as address bits 16 and 17 of the BAR.

Interrupt Enable (IE) - When this bit is set by software, the controller is allowed to interrupt the processor at the assertion of
CRDY. This occurs at the normal or error termination of a command. Once an interrupt request is posted on the LSI bus, it is
not removed until serviced even if IE is cleared.

934

RL V11 /M8013,4
CSR Bit Definitions (Cont)
Bit

Function

Controller Ready (CRDY) - When cleared by software, this bit
indicates that the command in bits 1-3 is to be executed. Software cannot set this bit because no registers are accessible
while CRDY is o. When set, this bit indicates that the controller
is ready to accept another command.

8-9

Drive Select (DSO, DS1) - These bits determine which drive will
communicate with the controller via the drive bus.

Operation Incomplete (OPI) - When set, this bit indicates that
the current command was not completed within the OPI timer
period.

Data CRC (OCRC) or Header CRC (HCRC) or Write Check
(WCE) - If OPI (bit 10) is cleared and bit 11 is set, the CRC error
occurred on the data (DCRC). If OPI (bit 10) is set and bit 11 is
also set, the CRC error occurred on the header (HCRC).
If OPI (bit 10) is cleared and bit 11 is set and the function command was a write check, a write check error (WCE) has occurred.

NOTE
Cyclic redundancy checking is done only on the desired head·
er. It is performed on the first and second header words, even
though the second header word is always O.
12

Data Late (DL T) or Header Not Found (HNF Error) - When OPI
(bit 10) is cleared and bit 12 is set, it indicates that a data late
condition occurred on a read without header check operation.
One of two conditions exists:
Write Operation - The silo is empty, but the word count has not
reached zero. (Bus request was ignored for too long.)
Read Operation - The silo is full (word being read could not enter the silo and the bus request was ignored too long.)
When OPI (bit 10) is set and bit 12 is also set, it indicates that a
timeout occurred while the controller was searchjngJor the correct sector to read or write (no header; compare [NHF]).

935

RL V11 /M8013,4
CSR Bit Definitions (Cont)
Bit

Function
Error Summary
Error

Bit 12

Bit 11

Bit 10 Comments

OPI
DCRC
WCE

0
0
0

1
0
0

HCRC
DLT
HNF

1
0
0

200 ms timeout
Function command is a write
check.

1
0

Nonexistent Memory (NXM) - When set, this bit indicates that
during a DMA data transfer, the memory location addressed did
not respond within 14 ms.

Drive Error (DE) - This bit is buffered from the drive error interface line. When set, it indicates that the selected drive has
flagged an error, the source of which can be determined by executing a GET STATUS command.
To clear the drive error bit, execute a GET STATUS command
with bit 3 of the DAR.

Composite Error (ERR) - When set, this bit indicates that one or
more of the error bits (bits 10-14) is set. When an error occurs,
the current operation terminates and an interrupt routine is initiated if the interrupt enable bit (bit 6 of the CSR) is set.
BUS ADDRESS REGISTER (BARI

774402

BA14

BA12

BA10
READIWRITE

Bus Address Register
BAR Bit Definitions
The Bus Address Register (BAR) is a 16-bit word-addressable register with
an address of 774 402. Bits 0 through 15 can be read or written; bit 0
should normally be written O. Expansion bits 16 and 17 are programmable
via bits 4 and 5 of the CSR.

936

RL V11 /M8013,4
The bus address register indicates the memory location involved in the
DMA data transfer during a read or write operation. The contents of the
BAR are automatically incremented by 2 as· each word is transferred between system memory and controller in either direction. Clear the BAR by
executing a BUS INIT.
Disk Address Register (DAR)
The Disk Address Register (DAR) is a 16-bit read/write word-addressable
register with an address of 774 404. Its contents can have one of three
meanings, depending on the function being performed. Clear this register
by executing a BUS INIT.
DAR During a SEEK Command - To perform a seek function, it is necessary to provide address difference, head select, and head directional information to the selected drive.
DAR DURING SEEK COMMAND

DAR SEEK Command
Bit Definitions
Bits

Function

Marker (MRKR) - Must be a 1.
Must be a 0, indicating to the drive that a SEEK command is
being requested and that the remaining bits in the register will
contain the seek specifications.

Direction (DIR) - This bit indicates the direction in which a seek
is to take place. When the bit is set, the heads move toward the
spindle (to a higher cylinder address). When the bit is cleared,
the heads move away from the spindle (to a lower cylinder address). The actual distance moved depends on the cylinder address difference (bits 7-14).

Must be a O.

Head Select (HS) - Indicates which head (disk surface) is to be
selected. Set = lower; clear = upper.

5-6

Reserved.

7-14

Cylinder Address Difference (DF<8:0» - Indicates the number
of cylinders the heads are to move on a seek.

Must be a o.

937

RLV11/M8013,4
DAR During READ or WRITE DATA Command - For a read, write, or write
check operation, the DAR is loaded with the address of the first sector to
be transferred. Thereafter, as each adjoining sector is transferred, the DAR
is automatically incremented by 1. If the DAR increments to the nonexistent
sector address 50 8 , an OPI timeout will occur. The drive must then seek to
a new track if the transfer is to continue.

DAR DURING READING OR WRITING DATA COMMANDS

DAR READ/WRITE DATA Command
Bit Definitions
Bit

Function

0-5

Sector Address (SA<5:0» - Address of one of the 40 sectors
on a track. (Octal range is 0 to 47.)

Head Select (HS) - Indicates which head (disk surface) is to be
selected. Set = lower; clear = upper.

7-14

Cylinder Address (CA<8:0» - Address of one of the 256 cylinders. (Octal range is 0 to 377.)

Must be a O.

DAR During a GET STATUS Command - After the GET STATUS command
is deposited in the CSR, it is the DAR's responsibility to get the command
transferred to the drive. Therefore, the DAR must also be programmed
along with the CSR to do the GET STATUS command.

DAR DURING GET STATUS COMMAND
15

7744041 x 1 x I x I x I x I x I x I x I 0 I 0 I 0 I 0 IRST 1 0 I 1 11 I
MR-2396

DAR GET STATUS Command

938

RLV11/M8013,4
For a GET STATUS command, the DAR register bits must be programmed
as follows.
DAR Register Bits for a GET STATUS Command
Bit

Function

Marker (MRKR) - Must be a 1.
Get Status (GS) - Must be a 1, indicating to the drive that its
status word is being requested. At the completion of the GET
STATUS command, the drive status word is read into the controller multipurpose (MP) register (output stage of FIFO). With
this bit set, bits 8-15 are ignored by the drive.

Must be a O.

Reset (RST) - When this bit is set, the drive clears its error register of soft errors before sending a status word to the controller.

4-7

Must be a O.

8-15

Not used.

Multipurpose Register (MPR)
The MPR is two registers bearing the same base address. When writing
into that location, the word counter accepts the data. When reading from
that location, the FIFO output buffer provides the data.

MPR AFTER GET STATUS COMMAND

774406
SKTO

MPR Status Word

MPR After a GET STATUS Command - When a GET STATUS command is
executed and a status word is returned to the controller, the contents of
the MPR (FIFO output stage) are defined as follows.

939

RL V11 /M8013,4
Bits 0-2 - State<C:A) (ST <C:A» - These bits define the state of the
drive.
Definition

Bits
C

a
a
a
a

a
a
1
1
a
a

a
1
a
1
a
1
a
1

Load Cartridge
Spin Up
Brush Cycle
Load Heads
Seek Track Counting
Seek Linear Mode (Lock On)
Unload Heads
Spin Down
Bit Definitions

Bit

Function

Brush Home (BH) - Asserted when the brushes are not over the
disk.

Heads Out (HO) - Asserted when the heads are over the disk.

Cover Open (CO) - Asserted when the cover is open or the dust
cover is not in place.

Head Select (HS) - Indicates the currently selected head.

Drive Type (DT) - Set = lower; clear = upper. Set = RLa2;
clear = RLa 1.

Drive Select Error (DSE) - Indicates that multiple drive selection was detected.

Volume Check (VC) - vc is set every time the drive goes into
load heads state. This asserts a drive error at the controller but
not on the front panel. VC is an indication that the program does
not really know which disk is present until it has read the serial
number and bad sector file. (The disk might have been changed
while the heads were unloaded.)

Write Gate Error (WGE) - Indicates that the drive sensed that
write gate was asserted when sector pulse was asserted, or
write gate was set with the drive not ready, or the drive was
write locked.

940

RLV11/M8013,4
Bit Definitions (Cont)
Bit

Function

Spin Error (SPE) - Indicates that the spindle did not reach
speed in the required time; or indicates over speeding.

Seek Time Out (SKTO) - Indicates that the heads did not come
on track in the required time during a SEEK command or loss of
"ready to read/write during lock on" mode.

Write Lock (WL) - Indicates write lock status of selected drive.
Set = write protected.

Head Current Error (HCE) - Indicates that write current was detected in the heads when write gate was not asserted.

Write Data Error (WDE) - Indicates that write gate was asserted
but no transitions were detected on the write data line.
MPR DURING READ HEADER COMMAND

WJ>RDI 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I
3RD

WORDL,~~.-L,~~.-L,~~.-L,~~.-L,~~.-~
CRC14

CRC12

CRC10

CRCS

CRC6

CRC4

CRC2

CRCO

MPR Three Header Words

MPR After a Read Header Command - When a READ HEADER command
is executed, three words will be stored in the multipurpose register (FIFO
output buffer). The first header word will contain sector address (SAO:SA5),
head select (HS - set = lower; clear = upper), and cylinder address information (CAO:CA8). The second word will contain all Os. The third word will
contain the header CRC information. All three words are readable by the
main program.

941

RLV11/M8013,4
MPR DURING READIWRITE COMMANDS FOR WORD COUNT

well

MPR Used As Word Counter
Bit Definitions
Bit

Function

0-12

Word Count (WC<12:0» - 2's complement of total number of
words to be transferred.

13-15

Must be a 1 for word count in correct range.

MPR During READ/WRITE DATA Commands - When transferring data via
DMA, the MPR functions as a word counter and is loaded by program with
the 2's complement of the number of words to be transferred. It is then incremented by 1 by the controller as each word is transferred. The reading
or writing operation generally is terminated when the word counter overflows. The word counter can keep track of from one data word to the full 40sector count of 5120 data words (decimal). The maximum number of words
that can be transferred in a single operation is limited by the number of sectors available to be written in the track.

NOTE
The RLO 1/RL02 disk drive will not do spiral read/writes. If
data is to be transferred past the end of the last sector of a
track, it is necessary to break up the operation into the following steps.

Program the data transfer to terminate at the end of the
last sector of the track.

Program a seek to the next track. This can be accomplished either by a head switch to the other surface but
the same cylinder, or a head switch to move to the next
cylinder.

Program the data transfer to continue at the start of the
first sector on the next track.

942

RLV12/M8061

RL V12 DISK CONTROLLER

Power Requirements
+5 Vdc ± 5% at 5.0 A
+ 12 Vdc ± 5% at 0.1 A

Bus Loads
DC

AC
2.7

Optional Drive Cables
Cable

Part No.

Length

BC20J-20
BC20J-40
BC20J-60

7012122-20
7012122-40
7012122-60

6 m (20 ft)
12 m (40 ft)
18 m (60 ft)

NOTE
Total length of cable(s) from controller to the last drive must
not exceed 30 m (100 tt).
FCC Cable Information
Order Number
RLV12-AP

Factory installed shielded cable and filter connector assembly.
plus RLV12 option.

RLV12

Disk Controller option only.

CK-RLV1A-KA
CK-RLV1A-KB
CK-RLV1A-KC

Cabinet Kit for BA23/Micro
Cabinet Kit for H3012fPDP-11 /23S
Cabinet Kit for H349/PDP-11 /23-PLUS

943

RLV12/M8061
Standard Addresses

Standard Address Assignments
18-Bit
Addressing

22-Bit
Addressing'

Starting
160000-177770
address range

760000-777770

17760000-17777760

Starting
address

174400

774400

17774400,

Number of
registers

8 (5 are used;
3 are not)

Registers
used

CSR (174400)
BAR (174402)
DAR (174404)
MPR (174406)

CSR (774400)
BAR (774402)
DAR (774404)
MPR (774406)

CSR (17774400)
BAR (1777 4402)
DAR (17774404)
MPR (17774406)
BAE (17774410)

Vector range

0-774

Standard
vector

160

Device
Address

16-Bit
Addressing

Interrupt
Vector

'Factory configuration (FCO MB061-002)
Diagnostic Programs
Refer to Appendix A.
Related Documentation
RLV12 Disk Controller User's Guide (EK-RLV12-UG)
RLO 1 Field Maintenance Print Set (MP00347)
RL02 Field Maintenance Print Set (MP00553)
RLO 1 Disk Drive IPB (EK-ORLO 1-IP)
RL02 Disk Drive IPB (EK-ORL02-IP)
RL011RL02 User's Guide (EK-RL012-UG)
RLO 1IRL02 Pocket Service Guide (EK-RLO 12-PG)

944

RLV12/M8061
CONFIGURATION
The user or installer can configure and install the RLV12 in a 16-, 18-, or
22-bit LSI-11 bus. The user can select the device address, interrupt vector,
and memory parity error abort feature.
Device Address Selection
Software control of the RL V 12 is by means of four or five device registers
- CSR, BAR, DAR, MPR, and BAE. Four registers are used for 16- or 18-bit
addressing; five registers are used for 22-bit addressing. The bus address
extension register (BAE) is added for upper address bit selection for 22-bit
addressing. The usual device starting address is as follows.

Device Starting Address
Addressing Mode

Starting Address (Octal)

16-bit
18-bit
22-bit

174400
774400
17774400

The first register, the CSR, is assigned the starting address, and the other
registers are incremented by 2.
The device starting address is selected by jumpers for bits 03 through 12. A
jumper from the selected bit to ground (M22) decodes a 1; no jumper decodes a 0; and a jumper to +5 V (M11) decodes an X (don't care) condition. The following figure shows the RL V 12 device starting address format.
NOTE
For 22-bit addressing, bit A3 is not decoded in the starting address.

945

<
.....

I\)

o
en
.....

FACTORY
CONFIGURATION
CSR
BAR
DAR
MPR
BAE

774400
774402
774404
774406
774410

BANK SELECT 7 FOR
nBIT ADDRESSING
(CONNECT Ml TO M21

ADDRESSING

,M21

M20

M19

M18

M17

M16

M15

! I J

M14

M13

M12

BUS ADDRESS PINS
CONNECT TO GROUND (PIN M221 TO DECODE A LOGICAL ONE. CONNECT
TO +5V (PIN Mll1 FOR A DON'T CARE (XI CONDITION. NO CONNECTION
DECODES A LOGICAL ZERO.

RLV12 Device Address Format

RLV12/M8061

III

ENABLE CRYSTAL
,..-M29
!J+-M28
ENABLE
VCO CLK
M27 M26

\1
\

•

TEST POINT
M30
W3

-=-

Mll ·+5V
M12·A3
M13·A4
M14·A5
M15·A6
OEVICE
M16. A7
ADDRESS M17. AS
PINS
A9
M19·Al0
M1S.
M20·All
M21 . A12
M22·· GND
Wl

{

MEMORY PARITY ERROR
ABORT SELECTION
M23
M24 SEE NOTE
M25

Ml0 M9 MS M7 M6 M5 M4 M3
,VS V7 V6 V5 V4 V3 V2 VEf TO BUS H

C:.

PASS CD PRIORITIES
(CDMG, CIAK)

CONNECTION

FUNCTION
NO PAR ITY
PARITY ERROR ABORT

E23

••

M2
Ml
ENABLE
22·BIT ADDRESSING

NOTE:
THE MEMORY PARITY ERROR ABORT
FEATURE IS AVAILABLE FOR USE
WITH MEMORIES THAT HAVE PARITY
ERROR CHECKING.
THIS FEATURE DOES NOT HAVE TO
BE DISABLED FOR MEMORIES THAT
DO NOT HAVE PARITY ERROR
CHECKING. THE PINS ARE
CONNECTED AS FOLLOWS:

M23 . M24
M24· M25

Rl V 12 Module layout

947

RLV12/M8061
Interrupt Vector
The interrupt vector has a range of 0 to 774. The interrupt vector is preset
at the factory to 160. The user may select another vector by changing the
jumpers for bits V2-VS. A connection to M3 generates a 1 for that bit; no
connection generates a O. The RL V 12 interrupt is at priority level 4.

\ \

I I I I I~ ~ I I I

CON~~~~;:~ION

I I

00
0

11 I I I 1I

IIl11I1

,M10

M4.

INTERRUPT VECTOR PINS
CONNECT TO PIN M3 TO DECODE A LOGICAL ONE.
NO CONNECTION DECODES A LOGICAL ZERO.

RL V 12 Interrupt Vector Format

Bus Selection
The RLV12 module can be used on 16-, 1S-, or 22-bit LSI-11 buses. When
sent from the factory, the module operates on a 22-bit bus. Jumper M 1 to
M2 is installed, which enables bank select 7 (BBS7) to be determined by the
upper address bits (13-21). When the jumper is removed, the RLV12 has
an 1S-bit mode bank select 7.
NOTE
TheRLV12 may be used in a 16- or 18-bit system while configured to a 22-bit operation (factory-shipped configuration)
provided it is the only RLV12 in the system.
Memory Parity Error Abort Feature
When reading the system's optional memory with parity error detection, a
parity error will set OPI and NXM of the CSR. This is a unique error condition that aborts the current command to the RL V 12. This error abort feature
is possible only with memories that have parity data bits.
The RL V 12 is sent from the factory with the memory parity error abort feature enabled. To disable parity error abort, remove the jumper between pins
M24 and M25 and install a jumper between pins M23 and M24. This feature
does not have to be disabled for nonparity memories, as parity errors are
not generated. Parity error abort uses data bits 16 and 17.

948

RLV12/M8061
Jumpers That Remain Installed
The module has two jumpers, W 1 and W2, that enable priority signals to
pass through the module. The module has these jumpers installed, and
they should be left in.
Jumper

Signal

W1
W2

CIAKI to CIAKO
CDMGI to CDMGO

One jumper, W3, enables the word count register to automatically increment during a DMA operation. This jumper is used for factory testing
and should be left in.
Two jumpers on the module disable the crystal oscillator and the voltagecontrolled oscillator (VCO) during factory testing. These jumpers should be
left in.
Jumper

Oscillator

M26-M27
M28-M29

VCO
Crystal

CONTROL STATUS REGISTER (CSR)
The control status register is a 16-bit, word-addressable register with a
standard address of 774400 for 18-bit addressing, and 17774400 for 22-bit
addressing. Bits 01 through 09 can be read or written; the other bits can
only be read. The bit functions are described in the following table.
When the LSI-11 bus is initialized with BINIT L, bits 01-06 and 08-13 are
cleared, and bit 07 (CRDY) is set. Bit 00 (DRDY) is set when the selected
drive is ready to accept a command; otherwise, this bit is cleared. Bit 14
(DE) is clear as long as there is no drive error. Otherwise, this bit is set and
stays set until the drive error is corrected; or if bit 03 (drive reset) is set in
the DAR and the controller is sent a get status command, the DE bit is
cleared.
Bit 15 (ERR) is set when there is a drive or controller error in bits 10-14.
CONTROL STATUS REGISTER [CSRI

BA16

~----R-EA-D~O-N-Ly----A----------RE-A-Dtw-R-IT-E------~~
ONLY

Control Status Register (CSR)
949

RLV12/M8061
RLV12 Control Status Register Bit Assignments
Bit

Name

Description

DRDY

Drive ready - When set, this bit indicates that the
selected drive is ready to receive a command or
supply valid read data. The bit is cleared when a
seek or head select operation is started and set
when the seek operation is completed.

01-03

FO-F2

Function code - These bits are the function code set
by software to indicate the command to be executed.
Function
F2 F 1 FO
0
0
0
0
1

0
0
1
1
0
0

0
1
0
1
0
1
0
1

Command
Maintenance mode
Write check
Get status
Seek
Read header
Write data
Read data
Read data without
header check

Octal
Code
0
1
2
3
4
5
6
7

Command execution starts when CRDY (bit 07) of
the CSR is cleared by software. The function code is
cleared by initializing the bus (BINIT L).
04,05

BA16,
BA17

Extended address bits - These two bits are the upper-order bus address bits for 18-bit buses. These
bits are read and written as bits 04 and 05 of the
CSR. They function as address bits 16 and 17 of the
BAR. Writing bits 04 and 05 of the CSR also writes
bits 0 and 1 of the BAE.

Interrupt enable - When CRDY is asserted,bit 06 allows the controller to interrupt the processor. This
interrupt occurs at the termination of a command.
Once an interrupt request is placed on the LSI-11
bus, it is not removed until acknowledged by the LSI11 processor even if IE (bit 06) is cleared. This bit is
cleared by initializing the bus.

950

RLV12/M8061
RLV12 Control Status Register Bit Assignments (Cont)
Bit

Name

Description

CRDY

Controller ready - When cleared by software, this bit
indicates that the command in bits 01-03 is to be executed. This bit is set by the controller at the completion of a command, at the detection of an error, or
by initializing the bus. Software cannot set this bit
because registers are not accessible while CRDY
is O.

08, 09

DSO,
DS1

Drive select - These bits determine which drive will
communicate with the controller via the drive bus.
These bits are cleared by initializing the bus.

10-13

EO-E3

Controller status errors - These bits are the error
code set by the controller to indicate one of the following errors.
Error Code
E3 E2 E 1 EO Error
0
1
1
0

0
0
0
1
1

0
0

0
0
0
0

1
0
1
0
1
0

Operation incomplete (OPI)
Data CRC (DCRC)
Header CRC (HCRC)
Data late (DL T)
Header not found (HNF)
Nonexistent memory (NXM)
Parity error abort (PAR ERR)

Octal
Code
1
2
3
4
5
10
11

Operation incomplete indicates that the current
command was not completed within the OPI timeout
period of 550 ms.
A data CRC error indicates that while reading the
data field from the disk an error was found.
A header CRC error indicates that while reading
the header from the disk an error was found. The
CRC check is performed on the first and second
header words, although the second header word is
always O.
Data late indicates that the FIFO RAM was more
than half full and the controller was not able to read
the next sequential sector. This error may occur during a read without header check command.

951

RLV12/M8061
RLV12 Control Status Register Bit Assignments (Cont)
Bit

Name

Description
Header not found indicates that an OPI timeout occurred while the controller was searching for the
correct sector to read or write. A header compare
did not occur.
A nonexistent memory error indicates that during a
DMA transfer the memory location addressed did not
respond with RPL Y within 10 p,s.
A memory parity error abort indicates that a parity
error was detected while reading the system's optional memory that has parity error checking. If an
error was detected, the current command to the
RL V 12 is aborted.

Drive error - This bit is buffered from the drive error
interface line. When set, it indicates that the selected drive has flagged an error, the source of
which can be determined by executing a get status
command. DE will not set ERR (bit 15) or CRDY (bit
07) until the usual occurrence of CRDY.

ERR

Composite error - When set, this bit indicates that
one or more of the error bits (bits 10-14) are set.
When an error occurs, the current operation terminates and an interrupt routine is started if the interrupt enable bit (bit 06 of the CSR) is set.
All error bits are cleared by initializing the bus by
starting a new command, with the exception of DE
and ERR if they were caused by a drive error.

BUS ADDRESS REGISTER (BAR)
The bus address register is a 16-bit, word-addressable register with a
standard address of 774402 for 18-bit addressing, and 17774402 for 22-bit
addressing. Bits 00 through 15 can be read or written; bit 00 is usually written as O. The bus address register indicates the memory location for the
DMA data transfer during a read or write operation. The register's contents
are automatically incremented by 2 as each word is transferred between
the system memory and the controller.

952

RLV12/M8061
The bus address can be expanded for an 18-bit LSI-11 bus by using bits 04
and 05 (BA 16 and 17) of the CSR or by using bits 00 and 01 of the BAE
register.
The bus address can be expanded for a 22-bit LSI-11 bus by using the BAE
register (BAE 16-21).
NOTE
When using 22-bit mode, writing CSR bits 04 and 05 modifies
BAE bits 00 and 01 and vice versa.
The BAR is cleared by initializing the bus (BINIT L).

BUS ADDRESS REGISTER IBARI

BA10

~----------------~~------------------~
READIWRITE

Bus Address Register (BAR)

DISK ADDRESS REGISTER (DAR)
The disk address register is a 16-bit, read / write, word-addressable register
with a standard address of 774404 for 18-bit addressing, and 17774404 for
22-bit addressing. Its contents have one of three meanings, depending on
the command being performed.

Disk Address Commands
Command

DAR Function

Seek

Head selected, number of cylinders to move,
direction.

Read data or write data

Head selected, cylinder address, sector address.

Get status

Send drive status to MPR; reset the error
registers.

The DAR is cleared by initializing the bus (BINIT L).

953

RLV12/M8061
DAR During a Seek Command
To perform a seek command, the program must provide the head selected
(HS), direction to move (DIR), and the cylinder address difference (OF). The
bits are as follows.
DAR DURING SEEK COMMAND

(Rl02 ONl YI

DAR During a Seek Command

DAR Seek Command Word Format
Bit

Name

Description

MRKR

Marker - Must be a 1.

None

Must be a 0, indicating to the drive that a seek command is being issued and that the other bits in the
register hold the seek specifications.

DIR

Direction - This bit indicates the direction in which
the seek is to take place. When the bit is set, the
heads move toward the spindle (to a higher cylinder
address). When the bit is cleared, the heads move
away from the spindle (to a lower cylinder address).
The actual distance moved depends on the cylinder
address difference (bits 07-15).

None

Must be a O.

Head select - Indicates which head (disk surface) is
to be selected: 1 = lower, 0 = upper.

05, 06

None

Reserved.

07-15

Cylinder address difference - Indicates the number
of cylinders the heads are to move on a seek.

954

RLV12/M8061
DAR During a Read, Write, or Write Check Command
For a read, write, or write check command, the DAR provides the head selected (HS) and the address of the first sector to be transferred (SA). The
bits are described below. As each sector is transferred, the DAR sector address increments by 1.
DAR DURING READ DR WRITE DATA COMMANDS
06

DAR During a Read, Write, or Write Check Command

DAR Read/Write Data Command Word Format
Bit

Name

Description

00-05

Sector address - Address of one of the 40 sectors
on a track. (Octal range is 0 to 47.)

Head select - Indicates which head (disk surface) is
to be selected: 1 = lower; 0 = upper.

07-15

Cylinder address - Address of one of the 256 cylinders for RL01 or 512 cylinders for RL02. (Octal
range is 0 to 777.)

DAR During a Get Status Command
Both the CSR and the DAR must be programmed to perform a get status
command. Then a get status command is placed in the CSR. The DAR bits
are as follows.

DAR DURING GET STATUS COMMAND
15

RST

I x I x I x I x Ix I x Ix I x I I I I I I I I I
DAR During a Get Status Command

955

RLV12/M8061
DAR Get Status Command Word Format
Bit

Name

Description

MRKR

Marker - Must be a 1.

Get status - Must be a 1, indicating to the drive to
send its status word. At the completion of the get
status command, the drive status word is read into
the controller multipurpose register (MPR). With this
bit set, bits 08-15 are ignored by the drive.

None

Must be a O.

RST

Reset - When this bit is set, the disk drive clears its
error register of soft errors before sending a status
word to the controller.

04-07

None

Must be a o.

08-15

None

Not used.

MULTIPURPOSE REGISTER (MPR)
The multipurpose register is a 16-bit, read/write, word-addressable register. It is accessed using the standard address of 774406 for 18-bit addressing, and 17774406 for 22-bit addressing. Following a read header command or a get status command, reading the MPR obtains sector header or
drive status information.
Writing to the MPR is used to set the word count. The word count is cleared
by initializing the bus (BINIT L).

Writing the MPR to Set the Word Count
Before starting a DMA transfer, the MPR is loaded with the word count. The
program must load the MPR with the 2's complement of the number of
words to be transferred. The bits are described below. As each word is
transferred, the MPR is automatically incremented by 1. The reading or
writing operation continues until a word count overflow occurs, indicating
that all words have been transferred.
The word count can range from 1 to 5120 data words. The maximum word
count is limited by the maximum number of sectors available (40) and the
maximum words per sector (128).

NOTE
Once written, the word count cannot be read back. Reading
the MPR does not change the word count.

956

RLV12/M8061

WC11

Writing the MPR to Set the Word Count

MPR Word Count Format
Bit

Name

Description

00-12

Word count - This is the 2's complement of the total
number of words to be transferred.

13-15

None

Must be all ones for word count in correct range.

Reading the MPR After a Read Header Command
When a read header command is executed, three words can be sequentially read from the MPR, as the following figure shows. The first word includes the sector address, the head selected, and the cylinder address.
The second word is all zeros. CRC information is the header for the third
word.

READING MPR AFTER READ HEADER COMMAND
06

~~~D I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I
3RD

WORD~-L~~-L~~-L~-r~~-r~~-r~~-r~~-r~~
CRC14

CRC12

CRC10

CRCS

CRC6

CRC4

CRC2

CRCO

Reading the MPR After a Read Header Command
(Three Header Words)

957

RLV12/M8061
Reading the MPR After a Get Status Command
After a get status command is executed, a status word is stored in the
MPR. The status word from the selected disk drive includes information on
the functional state of the drive and any drive errors. The bits are described
in the following table.

Reading the MPR After a Get Status Command

MPR Status Word Format
Bit

Name

00-02

STA,
STB,
STC

Description

These bits (A, B, and C) define the state of the drive
as follows.
C

State of Drive

0
0
0
0
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0

Load state
Spin up
Brush cycle
Load heads
Seek track counting
Seek linear mode (lock on)
Unload heads
Spin down

Brush home - Asserted when the brushes are not
over the disk.

Heads out - Asserted when the heads are over the
disk

Cover open - Asserted when the cover is open or
the dust cover is not in place.

Head select - Indicates the head selected: 1
lower, 0 = upper.

958

RLV12/M8061
MPR Status Word Format (Cont)
Bit

Name

Description

Drive type - Indicates the type of disk drive: 0
RL01, 1 = RL02.

DSE

Drive select error - Indicates multiple drive selection
is detected.

Volume check - VC is set every time the drive goes
into load heads state. This asserts a drive error at
the controller, but not on the front panel. VC is an indication that the program does not know which disk
is present until it has read the serial number and bad
sector file. (The disk might have been changed while
the heads were unloaded.)

WGE

Write gate error - Indicates that the write gate was
asserted when the drive was not ready, the sector
pulse was asserted, or the drive was write locked.

SPE

Spin error - Indicates that the spindle did not reach
full speed within a specific time, or that it is turning
too fast.

SKTO

Seek time out - Indicates that the heads did not
come onto track within a specific time during a seek
command.

Write lock - Indicates write lock status of selected
drive: 0 = unlocked; 1 = protected.

HCE

Head current error - Indicates that write current was
detected in the heads when write gate was not asserted.

WDE

Write data error - Indicates write gate was asserted,
but no pulses were detected on the write data line.

959

RLV12/M8061
BUS ADDRESS EXTENSION REGISTER (BAE)
The bus address extension register is a 6-bit read / write register used. to
drive address bits 16-21 for a 22-bit LSI-11 bus. The BAE has a standard
address of 17774410 for 22-bit addressing. A write to the BAE loads TS
DAL 0-5 into BAE 0-5. Reading the BAE enables bank select 7 (BBS7 L) to
the LSI-11 bus. (A jumper must be connected between M 1 and M2 on the
controller to enable 22-bit addressing.) When address bits 13-21 are all
ones, the RL V 12 drives BBS7 L to direct data to the I/O page.
The two least significant bits of the BAE (bus address lines 16 and 17) are
mirrored in bits 04 and 05 of the CSR. The same bits can be read or written
as CSR bits 04 and 05 or BAE bits 00 and 01.
NOTE
Writing CSR bits 04 and 05 modifies BAE bits 0 and 1 and vice
versa.
The BAE register is cleared by initializing the bus (BINIT L).
8AE DURING 22-81T ADDRESSING MODE

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
101010101010101010101

I I I I I I

I 8d20 I

8A2l

8A19

BAE Register Word Format

960

81,8

8A17

8d16

RQDX1/M8639

RQDX1 AND EXTENDER CONTROLLER MODULE
(RX50, RD51, RD52)

Bus Loads

Amps

+12 Vdc
7.3 mA
10 mA (max.)

+5 V
6.4 A
8 A (max.)

AC
2.5

DC
1

Standard Addresses

Address Mode

Octal Address

16-bit
18-bit
22-bit

172150
772150
17772150

Vectors

Software selectable (normally set to 154)
Diagnostic Programs

ZRQA??
ZRQB??

BIN RDRX Performance Exerciser
BIN RDRX Formatter (RD51)

Related Documentation

RQDX1 Field Maintenance Print Set (MP01731-01)
UDA50 Programmers Document Kit (QP-905-GZ)
RQOX1 Controller Modules User's Guide (EK-RQDX1-UG)

961

><
......

:s:

CD
1

1 11

1 1 11

BANK SELECT7
FOR 18-BIT
ADDRESSING
BANK SELECT 7FOR
22.BIT ADDRESSING

11 1 1 1
I
I
I
+ ! l + +
1

A12

All

Al0

1 11 1
1

l l l l

BUS ADDRESS JUMPERS

I\)

CONNECT TWO POSITION JUMPER CLIPS (PART NO. 12·18783-001
TO DECODE A 1.

1 0

NO CONNECTION DECODES A O.
'FACTORY
CONFIGURATION
MR-11287

RQDX1 Address Selection Jumper Format

RQDX1/M8639
RQOX1 Standard Address Jumper Configuration
Jumper

State

OUT

IN
IN

A6
A7

AS
A9

A10
A11
A12

Address selection (772150)

OUT
OUT
OUT

IN
OUT

LOGICAL UNIT NUMBER SELECTION
The location of the RODX1 controller module logical unit number jumpers is shown
below. These jumpers are set to the lowest logical unit number assigned to any
disk/diskette drive controlled by the module. The controller module automatically
sizes the logical unit configuration during initialization to determine how many (of
four possible units) are actually present. This automatic sizing eliminates the need
for the reconfiguration of jumpers when units (RD51 or RX50 drives) are added to
or removed from the controller module. The standard configuration for the logical
unit number jumpers (selecting logical unit number 0) is listed. To configure the
module for logical unit numbers beginning with other than unit number 0, use the
format shown below to determine the appropriate jumper configuration.
LOGICAL
LUN
UNITS
JUMPER· SPECIFIED
7
32-35
28-31

24-27
20-23
16-19
12-15
8-11

4-7

ONLY ONE JUMPER IS
INSTALLED AT ANY
TIME
ALL JUMPERS REMOVED
SPECIFIES LDGICAL
UNITS 0- 3

RODX1 Logical Unit Number Jumper Format

963

RQDX1/M8639
RQOX1 Standard Logical Unit Number Jumper Configuration
Jumper

State

LUN1
LUN2
LUN3
LUN4
LUN5
LUN6
LUN7
LUN8

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

Logical unit number (0)*

This indicates that logical unit numbers 0-3 are assigned to this controller module.
The controller wi" automatically determine if less than four logical units are
present.
RQOX1-E Extender Module Jumper Configuration
The RQDX1-E extender module is a dual-height module that provides signal connectors and requires appropriate jumper configurations. The J2 connector
receives signals from the RQDX1 controller module. The other connectors (J1 and
J3) distribute these signals to the disk and diskette drives. Jumper functions for
the RQDX1-E extender module, as we" as the jumpers installed in the factory
configuration, are listed.

J J J
BAC
• •• 1
• •• 2

• •• 3
• •• 4
• • ·5
• •• 6
• •• 7
• •• 8
-=- Wl
-=-W2
-=-W3
-=-W4

J
J
RJ R

DDX
•

•• 1

• •• 2
• •• 3

RQDX1-E Extender Module Jumper Locations
964

RQOX1/M8639
RQOX1-E Extender Module Jumper Configuration
Factory
Configuration"

Jumpers

Functions

W1-W4

Must be instalied
(Manufacturing use only)

W1-W4

JRD1-JRD3
JD1-JD3
JRX1-JRX3

Select the external drive to be
connected to the J3 connector

JD1 to JRD1
JD2 to JRD2
JD3 to JRD3

JB1-JBB
JA-JAB
JC-JCB

Determine which connector (J2 or J3)
the RD read/write will connect to

JA2 to JC2
JA2 to JC2
JA3 to JB3
JA4 to JB4
JA5 to JB5
JA6 to JB6
JA7 to JC7
JAB to JCB

" Factory configuration is set to connect an external RD51 disk drive to connector
J3. To configure the module for an external RX50 (connected to J3), jumpers
JD1 through JD3 are connected to JRX1 through JRX3 and jumpers JA 1
through JAB are connected to JB1 through JBB.
Interrupt Vector

The interrupt vector has a range of 0 to 774 and is software selectable. A vector
selected by software must be greater than O. The normal interrupt vector used by
the RQDX1 controlier module is 154.
Interrupt Request Level

The RQDX1 controlier module interrupts at priority level 4 are determined by E3, a
DC003 chip.

965

RQOX1/M8639
RQDX1 CONTROLLER MODULE INSTALLATION
The RQDX1 module (M8639) is typically installed in the last occupied slot of the
backplane. If empty slots are left between the other modules and the M8639
module, install grant cards (part no. G7272) in those empty slots to accommodate
the interrupt and direct memory access structure of the backplane.
Before installing the module, make sure that the address and logical unit number
jumpers are properly configured.
Install the SO-conductor signal cable (part no. BC02D-1D) to the J1 connector on
the M8639 module. This cable must be connected to a signal distribution panel
that will connect the appropriate signals to the RDS1 and/or RXSO drives. An
example of the MICRO/PDP-11 signal distribution panel connecting the M8639
module to an RDS1 disk drive and an RX50 diskette drive is on the next page. The
RDS1 disk drive requires two signal cable connections. One is a 20-conductor
cable (part no. 17-00282-00), the other is a 34-conductor cable (part no. 17-0028600). The RXSO diskette drive requires a single 34-conductor signal cable (part no.
17-00285-02).
RQDX1-E EXTENDER MODULE OPTION
Typically, in the MICRO/PDP-11, the RQDX1 controller module is located in the
same mounting box as the disk and/or diskette drives that it controls. However, if
the system mounting box cannot hold all of these drives, the optional RQDX1-E
extender module may be used to connect the RQDX1 controller module signals to
any drive that is external from the system mounting box.
NOTE
Jumper selection (for configurations listed) is made by attaching twoposition jumper clips (part no. 12-18783-00).
RQDX1-E EXTENDER MODULE INSTALLATION
Installation of the RQDX1-E extender module option in the MICRO/PDP-11 system
(BA23 mounting box) is as follows. The M7S12 dual-height module is installed in
the backplane slot directly below the M8639 (RQDX1) module, in connectors A and
B. A cable (part no. BC02D-OK) connects the RQDX1 controller module to the
RQDX1-E extender module through the J2 connector. Another cable (part no. 70186S2-01), attached to the J3 connector, connects the RQDX1-E extender module
to a mounting plate (part no. 74-2866-01). This is mounted to the system's patch
and filter panel assembly. The entire cable and mounting plate assembly may be
ordered as part number 70-20691-01. This external plate provides the signals to
be sent to the external drive. A third cable (part no. BC02D-1 D - attached to the J1
connector on the RQDX1-E extender module) is connected to the signal distribution panel in the mounting box, providing signals to the disk or diskette drives that
are installed in the system mounting box.
Cable Signals
RQDX1 controller module signals on the J1 connector.

966

RQDXl
M8639

......

MR- 11

RQDX1 MICRO/PDP-11 Signal Distribution Connections

785

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...L

en
Co)

:xl

"....><
C

3:
(IC)
en
Co)
CD

OJ
CD

'MOUNTING PLATE INSTALLED IN SYSTEM
PATCH AND FILTER PANEL ASSEMBLY

RQDX1-E Extender Module Connections

RQOX1/M8639
J1 Connector Signals
J1 Pin

Signal Name

1
2
3
4
5
6
7
8
9

MFMWRTDT1 (H) (RD51 only signal)
MFMWRTDT1 (L) (RD51 only signal)
GROUND
HEAD SEL 2 (L) (RDXX only signal)'
GROUND
SEEKCPLT (L) (RD51 only signal)
RD1 ROY (H) (RD51 only signal)
WRT FAULT (L)
DRVBUSOE (L)

10
11
12
13
14
15
16
17
18
19

HEAD SEL 1 (L) (RD51 only signal)
RXOWPTLED (L) (RX50 only signal)
ROO ROY (H) (RD51 only signal)
RX1 WPTLED (L) (RX50 only signal)
DRVSLOACK (L) (RD51 only signal)
MFMRDDATO (H) (RD51 only signal)
MFMRDDATO (L) (RD51 only signal)
MFMWRTDTO (H) (RD51 only signal)
MFMWRTDTO (L) (RD51 only signal)
MFMRDDAT1 (H) (RD51 only signal)

20
21
22
23
24
25
26
27
28
29

MFMRDDAT1 (L) (RD51 only signal)
GROUND
REDUCWRTI (L)
RDOWRTPRO (L) (RD51 only signal)
DRV SEL 4 (L)
GROUND
INDEX (L)
RD1WRTPRO (L) (RD51 only signal)
DRV SEL 1 (L)
DRV SEL 2 (L)

30
31
32
33
34
35
36
37
38
39

DRV SEL 3 (L)
RX2WPTLED (L) (RX50 only signal)
RXMOTORON (L) (RX50 only signal)
GROUND
DIRECTION (L)
GROUND
STEP (L)
GROUND
RXWRTDATA (L) (RX50 only signal)
GROUND

'Reserved for future use.
969

RQDX1/M8639
J1 Connector Signals (Cont)
J1 Pin

Signal Name

40
41
42
43
44
45
46
47
48
49
50

WRT GATE (L)
GROUND
TRACK 00 (L)
RX3WPTLED (L) (RX50 only signal)
DRVSL 1ACK (L) (RD51 only signal)
GROUND
READ DATA (L) (RX50 only signal)
GROUND
HEAD SEL 0 (L)
GROUND
READY(L)

RD51 Disk Drive J1 Signal Connector Pin Assignments
GND Return
Pin

Signal
Pin

Signal
Name

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

Reserved
Head select 2
Write gate
Seek complete
Track 0
Write fault
Head select 0
Reserved (to J2 pin 7)
Head select 1
Index
Ready
Step
Drive select 1
Drive select 2
Drive select 3
Drive select 4
Direction in

970

RQOX1/M8639
RD51 Disk Drive J2 Signal Connector Pin Assignments
GND Return
Pin

Signal
Pin

Signal
Name

2
4
6
8

1
3
5
7
9,10
11
13
14
15
17
18
19

Drive selected
Reserved
Reserved
Reserved (to J1 pin 16)
Reserved
GND
+MFM write data
-MFM write data
GND
+MFM read data
-MFM read data
GND

RD51 Disk Drive J3 Power Connector Pin Assignments
GND Return
Pin

Signal
Pin

Signal
Name

2
3

1
4

+12 V
+5 V

971

RQDX1/M8639
RX50 Diskette Drive J1 Connector Pin Assignments
GND Return
Pir.

Signal
Pin

Signal
Name

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

TK43L (controls write current level)
Reserved
Drive select 3 L
Index L
Drive select 0 L
Drive select 1 L
Drive select 2 L
Motor on L
Direction (head movement direction)
Step L (head movement distance)
Write data L
Write gate L
Track 0 L
Write protect L
Read data L
Reserved
Ready L

RX50 Diskette Drive J3 Power Connector Pin Assignments
GND Return
Pin

Signal
Pin

Signal
Name

2
3

1
4

+12 V
+5 V

972

RXV11/M7946

RXV11 FLOPPY DISK INTERFACE

Amps
+5
1.5 max.

+12
0

Bus Loads

Cables

AC
1.74

BC05L

Standard Addresses

RXCS
RXDB
Vector

First Device

Second Device

177170
177172
264

177150
177152
270

Diagnostic Programs
Refer to Appendix A.

NOTE
Run DZRXB before DZRXA.

Related Documentation
RXV 11 User's Manual (EK·RXV 11·0P·00 1)
Field Maintenance Print Set (MP00024)
Microcomputer Interfaces Handbook (EB·20175·20)

973

:xJ

C " 1

Wl _ _ W3
W2 _ _ WS

W4 _ _ we

W1 _ _ WI3
Wa _ _ WI4
W16 _ _ W9

Wl0 _ _ W17
W1' _ _ WI5

_WID
_WI'

_W12

WI3 _ _ W16

W1C _ _ Wl1

ETCH REV B - MACHINE INSERTED JUMPERS

eTCH REV C - WIRE-WRAP JUMPERS

RXV11 Jumpers

><
<
.....

......

-D-

......

CD
~
Q)

DEVICE
ADDRESS

FACTORY-

CONFIGURED ____ R
ADDRESS
RXCS-177170
RXOB:177172

Device Address

:~~~;;r~5 I

<D: I >
0

0 : 07

: :

I I I I I I
I I I I I I

JUMPER ON
M7946 MODULE ---"'w6
FACTORY-CONFIGURED
VECTOR ADDRESS.264 - R

NOTE:

I - Jumper installed =LOQical ,
R"'Jumper removed'" Lat,licol I
X= Don't care

~
~

MR-0814

Vector Address

3:
.....
CD

.c:.
en

:IJ

><
<

Unit

s::
.....

I Address I Address Jumpers

W17 W16 W15 W14 W13 W12 W11 W10 W9

First
177170
(Drives 0, 1)

Second
177150
(Drives 2, 3)

~
en
Unit

I Vector I Vector Jumpers
W6

First
264
(Drives 0, 1)

Second
270
(Drives 2, 3)

R
R

.j:Io

RXV11/M7946
NOTES
1.

When inserting the cable in the RXV11 interface module,
the red edge of the cable should be at the center of the
module (near the pin A end of J1).

BUS INIT - Install W18 to pass bus INIT to the RX01 as in·
itialize.

I [
I

NOT USED

RX
INIT

DONE

INT
ENO

ERROR

UNIT

SEL

000

001
010
011
100
101
110
111

FilL BUFFER
EMPTY BUFFER
WRITE

SECTOR

READ SECTOR
NOT USED
READ STATUS

WRITE DELETED
DATA SECTOR
REAO ERROR

Receiver Control/Status Register (RCSR)
Bit Definitions
Bit

Function

Go - Initiates a command to RXO 1. Write only.

1-3

Function Select - These bits code one of the eight possible
functions. Write only.

Unit Select - This bit selects one of the two possible disks for
execution of the desired function. Write only.

Done - This bit indicates the completion of a function. Done will
generate an interrupt when asserted if interrupt enable (RXCS
bit 6) is set. Read only.

Interrupt Enable - This bit is set by the program to enable an
interrupt when the RX01 has completed an operation (done).
The condition of this bit is normally determined at the time a
function is initiated. This bit is cleared by the LSI·11 bus in·
itialize (BINIT L) signal, but it is not cleared by the RXV 11 in·
itialize bit (RXCS bit 14). Read/write.
977

RXV11/M7946
Bit Definitions (Cont)
Bit

Function

Transfer Request - This bit signifies that the RXV 11 needs data
or has data available. Read only.

8-13

Unused.

RXV 11 Initialize - This bit is set by the program to initialize the
RXV 11 without initializing all of the devices on the LSI-11 bus.
Write only.

CAUTION
1.

Loading the lower byte of the RXCS will also load the upper byte of the RXCS.

Setting this bit (BIS instruction) will not clear the interrupt enable bit (RXCS bit 06).

Upon setting this bit in the RXeS, the RXV 11 will negate done
and move the head position mechanism of drive 1 (if two are
available) to track o. Upon completion of a successful initialize,.
the RXO 1 will zero the error and status register, set initialize
done, and set RXES bit 7 (DRV RDY) if unit 0 is ready. It will also
read sector 1 of track 1 and drive O.
15

Error - This bit is set by the RXO 1 to indicate that an error has
occurred during an attempt to execute a command. This readonly bit is cleared by the initiation of a new command or·by setting the initialize bit. When an error is detected, the RXES is
automatically read into the RXDB.

The RXDB register serves as a general purpose data path between the
RXO 1 and the RXV 11 interface. It may represent one of five RXO 1 registers
according to the protocol of the command function in progress. The RXO 1
registers include RXDB, RXTA, RXSA, RXES, and RXER.

CAUTION
Violation of protocol in manipulation of this register may cause
permanent data loss. Refer to RXV11 User's Manual.

978

RXV11/M7946
RXDB-RX Data Buffer - All information transferred to and from the floppy
media passes through this register and is addressable only under the protocol of the function in progress.
15

v
READ/WRITE OATA

NOT USED

RXDB Format
RXTA-RX Track Address - This register is loaded to indicate on which of
the 114 tracks a given function is to operate. It can be addressed only under the protocol of the function in progress. Bits 8 through 15 are unused
and are ignored by the control.
15

I I

()'114,

NOT USED

RXTA Format
RXSA-RX Sector Address - This register is loaded to indicate on which of
the 32 sectors a given function is to operate. It can be addressed only under the protocol of the function in progress. Bits 8 through 15 are unused
and are ignored by the control.
15

I I I I
0

NOT USED

1·32,
cp·,!!"

RXSA Format
RXES-RX Error and Status - This register contains the current error and
status conditions of the drive selected by bit 4 (unit select) of the RXeS.
This read-only register can be addressed only under the protocol of the
function in progress. The RXES is located in the RXDB upon completion of
a function.
15

I~~~ I I

02
ID

•

PAR

CRC

I I I

NOT USED

MR·6313

RXES Format

979

RXV11/M7946
RXDB Bit Definitions
Bit

Function

CRC Error - A cyclic redundancy check error was detected as
information was received from a data field of the diskette. The
RXES is moved to the RXDB, and error and done are asserted.
Parity Error - A parity error was detected on command or on address information being transferred to the RXO 1 from the LSI-11
bus interface. A parity error indication means that there is a
problem in the interface cable between the RX01 and the interface. Upon detection of a parity error, the current function is terminated; the RXES is moved to the RXDB, and the error and
done are asserted.

Initialize Done - This bit is asserted in the RXES to indicate
completion of the initialize routine, which can be caused by
RX01 power failure, system power failure, or programmable or
LSI-11 bus initialize.

3-5

Unused.

Deleted Data Detected - During data recovery, the identification mark preceding the data field was decoded as a deleted data mark.

Drive Ready - This bit is asserted if the unit currently selected
exists, is properly supplied with power, has a diskette installed
correctly, has its door closed, and has a diskette up to speed.
NOTES
1. The drive ready bit is valid only when retrieved via a read
status function or at completion of initialize when it indicates status of drive O.
2. If the error bit was set in the RXCS but error bits are not set
in the RXES, then specific error conditions contained in the
RXER can be accessed from the RXDB via a read error register function.

RXER-RX Error - This register is located in the RX01 and contains specific
RX01 error information. This information is normally accessed when the
RXCS error bit 15 is set but RXES error bits 0 and 1 are not set. This is a
read-only register.

980

RXV11/M7946
15

NOT USED

RXER Format

Octal Code

Error Code Meaning

0010
0020
0030
0040
0050
0060
0070

Drive 0 failed to see home on initialize.
Drive 1 failed to see home on initialize.
Found home when stepping out 10 tracks for INIT.
Tried to access a track greater than 77.
Home was found before desired track was reached.
Self-diagnostic error.
Desired sector could not be found after looking at 52 headers (two revolutions).
More than 40 microseconds and no SEP clock seen.
A preamble could not be found.
Preamble found but no I/O mark found within allowable time
span.
CRC error on a header; no flag.
The header track address of a good header does not compare with the desired track.
Too many tries for an ID address mark.
Data mark not found in allotted time.
CRC error on reading the sector from the disk. No code appears in the ERREG.
Parity error on some word from interface.

0110
0120
0130
0140
0150
0160
0170
0200
0210

981

RXV21/M8029

RXV21 FLOPPY DISK CONTROLLER

Amps
+5
1.8

+12

Bus Loads

Cables

AC
3.0

BC05L-15

DC
1.0

Standard Addresses

RXCS
RXDB

First Controller

Second Controller

177170
177172

177200
177202

Standard Vectors
264

270

Diagnostic Programs
Refer to Appendix A.

Related Documentation
RXV21 Field Maintenance Print Set (MP00628)
RX02 Floppy Disk System User's Guide (EK-RX02-UG)
RXO 1/RX02 Reference Card (EK-RX 102-RC)
RX02 Technical Manual (EK-ORX02-TM)
Minicomputer Interfaces Handbook (EB-20 175-20)
RX02 Field Maintenance Print Set (MP-00629-00)

CAUTION
PDP-11/23 systems require the M8029 to be at CS revision E1
or higher.

982

RXV21/M8029

BC05L-15
CABLE CONNECTION

O--OA3
0--0 A 120--0 A4
0--0 V2 0--0 A5
OV3 O--OA6
O--OV40
OA7
O--OV5 0
OA8
o OV6 O--OA9
0--0 V7 0--0 A 10
OV80--0A11

M8029 Module Address and Vector Jumpers

983

RXV21/M8029
STANDARD ADDRESSES

15
177170

~12

OTHE R 177200

: :
1

: : :
0

: : :
1

: : :

STANDARD VECTOR ADDRESS

26'

: : :
0

OTHER 270

RX2BA 177172
STARTING ~EMORY ADDRESS OF DATA

AXDS

177172
DATA BYTE

NOT USED

RXV21 Error Codes
Error Reg

Error Codes

15141312111098

Track addr sel DV

DV
DEN HD DEN
SEL DV1 LD DVO

3 2

Target Sector

Target Track

Current Track DV 1

Current Track DVO

Word Count Reg

Error Code

1 0
DEN
CMD

The following sequence is used to get definitive error information following
a bootstrap operation. (It is assumed that the bootstrap program has halted
and the CPU is in ODT.)
1. Examine R5 (RF will contain RXES after an error).
2. Examine RXER by:
• Loading the READ ERROR REGISTER command into RX2CS
(777170/XXXXXX 17<CR».
• Examining the four words of error information that will be transferred
into locations 2000, 2002, 2004, and 2006.
• Reading and decoding this information using the format shown below. The error code can be used to help identify the failing FRU.

984

RXV21/M8029

RX2CS Format RXV21

Bit Definitions
Bit

Function

Go - Initiates a command to RX02. Write only.

1-3

Function Select - These bits code one of the eight possible
functions described below. Write only.

Code

Function

000
001
010
011
100
101
110
111

Fill Buffer
Empty Buffer
Write Sector
Read Sector
Set Media Density
Read Status
Write Deleted Data Sector
Read Error Code

Unit Select - This bit selects one of the two possible disks for
execution of the desired function. This bit is readable only when
done is set, at which time it indicates the unit previously selected. Read/write.

Done - This bit indicates the completion of a function. Done will
generate an interrupt when asserted if interrupt enable (RX2CS
bit 6) is set. Read only.

Interrupt Enable - This bit is set by the program to enable an
interrupt when the RX02 has completed an operation (done).
The condition of this bit is normally determined at the time a
function is initiated. Read/write; cleared by initialize.

Transfer Request - This bit signifies that the RXV21 needs data
or has data available. Read only.

Density - This bit determines the density of the function to be
executed. This bit is readable only when done is set, at which
time it indicates the density of the function previously executed.
Read/write.

985

RXV21/M8029
Bit Definitions (Cont)
Bit

Function

Head Select - This bit selects one of two heads for double-sided
operation, readab.le only when done is set. At that time the side
that was previously selected is not valid.

Reserved for future use. Must be written as a O.

RX02 - This bit is set by the interface to inform the programmer
that this is an RX02 system. Read only.

12-13

Extended Address - These bits are used to declare an extended bus address. Write only.

RXV21 Initialize - This bit is set by the program to initialize the
RXV21 without initializing all devices on the UNIBUS. Write only.

CAUTION
Loading the lower byte of the RX2CS will also load the upper
byte of the RX2CS.
Upon setting this bit in the RX2CS, the RXV21 will negate done
and move the head position mechanism of both drives (if two
are available) to track O. Upon completion of a successful initialize, the RX02 will zero the error and status register, and set
initialize done. It will also read sector 1 of track 1 on drive 0 into
the buffer.
15

Error - This bit is set by the RX02 to indicate that an error has
occurred during an attempt to execute a command. Read only;
cleared by the initiation of a new command or an initialize.

I I
0

()'114,

NOT USED

RX2TA Format (RXV21)

RX2TA (RX Track Address) - This register is loaded to indicate on which
of the 1148 (0-76 10) tracks a given function is to operate. It can be addressed only under the protocol of the function in progress. Bits 8-15 are
unused and are ignored by the control.

986

RXV21/M8029
15

~------~y~--------~

NOT USED

RX2SA Format (RXV21)

RX2SA (RX Sector Address) - This register is loaded to indicate on which
of the 328 (1-26 10) sectors a given function is to operate. It can be addressed only under the protocol of the function in progress.
15

1~lol

II
0-128[0

RX2WC Format (RXV21)

RX2WC (RX Word Count Register) - For a double-density sector, the maximum word count is 128 10 , For a single-density sector the maximum word
count is 64 10 , If a word count is beyond the limit for the density indicated,
the control asserts word count overflow (bit 10 of RX2ES). This is a writeonly register. The actual word count, and not the 2's complement of the
word count, is loaded into the register.
15

RX2BA and RX2DB Format (RXV21)

RX2BA (RX Bus Address Register) - This register specifies the bus address of data transferred during fill buffer, empty buffer, and read definitive
error operations. Incrementation takes place after a memory transaction
has occurred. The RX2BA, therefore, is loaded with the address of the first
data word to be transferred. This is a 16-bit, write-only register.
RX2DB (RX Data Buffer) - All information transferred to and from the floppy media passes through this register and is addressable only under the.
protocol of the function in progress.
RX2DB (Data Buffer Register [177172]) - This register serves as a general purpose data path between the RX02 and the interface. It may represent
one of six RX02 registers according to the protocol of the function that is in
~rogress.

987

RXV21/M8029
This register is read/write if the RX02 is not in the process of executing a
command; that is, it may be manipulated without affecting the RX02 subsystem. If the RX02 is actively executing a command, this register will only
accept data if RX2CS bit 7 (TR) is set. In addition, valid data can only be
read when TR is set.
CAUTION
Violation of protocol in manipulation of the data buffer register
may cause permanent data loss_

HD
SEL

RX2ES Format (RXV21)

RX2ES (RX Error and Status) - This register contains the current error and
status conditions of the drive selected by bit 4 (unit select) of the RX2CS.
This read-only register can be addressed only under the protocol of the
function in progress. The RX2ES is located in the RX2DB upon completion
of a function.
RXES bit assignments are as follows.
Bit Definitions
Bit

Function

CRC Error - A cyclic redundancy check error was detected as
information was retrieved from a data field of the diskette. The
data collected must be considered invalid. The RX2ES is moved
to the RX2DB, and error and done are asserted. It is suggested
that the data transfer be tried up to 10 times, as most errors are
recoverable (soft).
Side 1 Ready - This bit, when set, indicates that a double-sided
diskette is mounted in a double-sided drive and is ready to execute a function. This bit is valid only at the termination of an initialize sequence or a maintenance READ STATUS command.

988

RXV21/M8029
Bit Definitions (Cont)
Bit

Function

Initialize Done - This bit is asserted in the RX2ES to indicate
completion of the initialize routine which can be caused by
RX02 power failure, system power failure, or programmable or
bus initialize.

RX AC LO - This bit is set by the interface to indicate a power
failure in the RX02 subsystem.

Density Error - This bit indicates that the density of the function
in progress does not match the drive density. Upon detection of
this error the control terminates the operation and asserts error
and done.

Drive Density - This bit indicates the density of the diskette in
the drive selected (indicated by bit 8). The density of the drive is
determined during read and write sector operations.

Deleted Data - This bit indicates that in the course of recovering data, the "deleted data" address mark was detected at
the beginning of the data field. The DRV DEN bit indicates
whether the mark was a single- or double-density deleted data
address mark. The data following the mark will be collected and
transferred normally, as the deleted data mark has no further
significance other than to establish drive density. Any alteration
of files or actual deletion of data due to this mark must be accomplished by user software.

Drive Ready - This bit indicates that the selected drive is ready
if bit 7 = 1 and all conditions for disk operation are satisfied,
such as door closed, power OK, diskette up to speed, etc. The
RX02 may be presumed to be ready to perform any operation.
This bit is only valid when retrieved via a read status function or
initialize.

Unit Select - This bit indicates that drive 0 is selected if bit
8=0. This bit indicates the drive that is currently selected.

Head Select - This bit indicates which side of a double-sided
drive performed the last operation.

Word Count Overflow - This bit indicates that the word count is
beyond sector size. The fill or empty buffer operation is terminated and error and done are set.

Nonexistent Memory Error - This bit is set by the interface when
a DMA transfer is being performed and the memory address
specified in RX2BA is nonexistent.

989

RXV21/M8029
Function Codes
Following the strict protocol of the individual function, data storage and recovery on the RXV21 occur with careful manipulation of the RX2CS and
RX2DB registers. The penalty for violation of protocol can be permanent
data loss.
A summary of the function codes is presented below.
000
001
010
011
100
101
110
111

Fill Buffer
Empty Buffer
Write Sector
Read Sector
Set Media Density
Read Status
Write Deleted Data Sector
Read Error Code

The following paragraphs describe in detail the programming protocol associated with each function encoded and written into RX2CS bits 1-3 if
done is set.
Fill Buffer (000) - This function is used to fill the RX02 data buffer with the
number of words of data specified by the RX2WC register. Fill buffer is a
complete function in itself: the function ends when RX2WC overflows, and if
necessary, the control has zero-filled the remainder of the buffer. The contents of the buffer may be written on the disk by means of a subsequent
WRITE SECTOR command or returned to the host processor by an EMPTY
BUFFER command. If the word count is too large, the function is terminated, error and done are asserted, and the word count overflow bit is set
in RX2ES.
To initiate this function the RX2CS is loaded with the function. Bit 4 of the
RX2CS (unit select) does not affect this function since no disk operation is
involved. Bit 8 (density) must be properly selected since this determines
the word count limit. When the command has been loaded, the done bit
(RX2CS bit 5) goes false. When the TR bit is asserted, the RX2WC may be
loaded into the data buffer register. When TR is again asserted, the RX2BA
may be loaded into the RX2DB. The data words are transferred directly from
memory and when RX2WC overflows and the control has zero-filled the remainder of the sector buffer, if necessary, done is asserted, ending the operation. If bit 6 RX2CS (interrupt enable) is set, an interrupt is initiated. Any
read of the RX2DB during the data transfer is ignored by the interface. After
done is true, the RX2ES is located in the RX2DB register.
Empty Buffer (001) - This function is used to empty the contents of the
internal buffer through the RXV21 for use by the host processor. This data
is in the buffer as the result of a previous FILL BUFFER or READ SECTOR
command.

990

RXV21/M8029
The programming protocol for this function is identical to that for the FILL
BUFFER command. The RX2CS is loaded with the command to initiate the
function. (This function will ignore bit 4 RX2CS, unit select.) RX2CS bit 8
(density) must be selected to allow the proper word count limit. When the
command has been loaded, the done bit (RX2CS bit 5) goes false. When
the TR bit is asserted, the RX2WC may be loaded into the RX2DB. When TR
is again asserted the RX2BA may be loaded into the RX2DB. The RXV21
assembles one word of data at a time and transfers it directly to memory.
Transfers occur until word count overflow, at which time the operation is
complete and done goes true. If bit 6 RX2CS (interrupt enable) is set, an
interrupt is initiated. After done is true, the RX2ES is located in the data
buffer register.
Write Sector (010) - This function is used to locate a desired sector on
the diskette and fill it with the contents of the internal buffer. The initiation
of the function clears RX2ES, TR, and done.
When TR is asserted, the program must load the desired sector address
into RX2DB, which will drop TR. When TR is again asserted, the program
must load the desired track address into the RX2DB, which will drop TR. TR
will remain unasserted while the RX02 attempts to locate the desired sector. The diskette density is determined at this time and is compared with
the function density. If the densities do not agree, the operation is terminated; bit 4 RX2ES is set, RX2ES is moved to the RX2DB, error (bit 15
RX2CS) is set, done is asserted, and an interrupt is initiated, if bit 6 RX2CS
(interrupt enable) is set.
If the densities agree but the RX02 is unable to locate the desired sector
within two diskette revolutions, the interface will abort the operation, move
the contents of RX2ES to the RX2DB, set error (bit 15 RX2CS), assert
done, and initiate an interrupt if bit 6 RX2CS (interrupt enable) is set.
If the desired sector has been reached and the densities agree, the RXV21
will write the 128 10 or 6410 words stored in the internal buffer followed by a
CRC character which is automatically calculated by the RX02. The RXV21
ends the function by asserting done and, if bit 6 RX2CS (interrupt enable) is
set, initiating an interrupt.

CAUTION
The contents of the sector buffer are not valid data after a
power loss has been detected by the RX02. However, write
sector will be accepted as a valid instruction and the (random)
contents of the buffer will be written, followed by a valid CRC.
NOTE
The contents of the sector buffer are not destroyed during a
write sector operation.

991

RXV21/M8029
Read Sector (011) - This function is used to locate the desired sector and
transfer the contents of the data field to the internal buffer in the control.
This function may also be used to retrieve rapidly (5 ms) the current status
of the drive selected. The initiation of this function clears RX2ES, TR, and
done.
When TR is asserted the program must load the desired sector address
into the RX20B, which will drop TR. When TR is again asserted, the program must load the desired track address into the RX20B, which will drop
TR.
TR and done will remain negated while the RX02 attempts to locate the desired sector. If the RX02 is unable to locate the desired sector within two
diskette revolutions for any reason, the RXV21 jRX211 will abort the operation, set done and error (bit 15 RX2CS), move the contents of the RX2ES
to the RX20B, and if bit 6 RX2CS (interrupt enable) is set, initiate an interrupt.
If the desired sector is successfully located, the control reads the data address mark and determines the density of the diskette. If the diskette
(drive) density does not agree with the function density the operation is terminated and done and error (bit 15 RX2CS) are asserted. Bit 4 RX2ES is
set (density error) and the RX2ES is moved to the RX20B. If bit 6 RX2CS
(interrupt enable) is set, an interrupt is initiated.
If a legal data mark is successfully located, and the control and densities
agree, the control will read data from the sector into the internal buffer. If a
deleted data address mark was detected, the control will set bit 6 RX2ES
(~O). As data enters the internal buffer, a CRC is computed based on the
data field and the CRC bytes previously recorded. A nonzero residue indicates that a read error has occurred and the control sets bit 0 RX2ES
(CRC error) and bit 15 RX2CS (error). The RXV21 ends the operation by
asserting done and moving the contents of the RX2ES into the RX20B. If bit
6 RX2CS is set, an interrupt is initiated.
If the desired sector is successfully located, the densities agree and the
data is transferred with no CRC error; done will be set and if bit 6 RX2CS
(interrupt enable) is set, the RXV21 initiates an interrupt.

Set Media Density (100) - This function causes the entire diskette to be
reassigned to a new density. Bit 8 RX2CS (density) indicates the new density. The control reformats the diskette by writing new data address marks
(double or single density) and zeroing all of the data fields on the diskette.

992

RXV21/M8029
The function is initiated by loading the RX2CS with the command. Initiation
of the function clears RX2ES and done. When TR is set, an ASCII "I" (111)
must be loaded into the RX2DB to complete the protocol. This extra character is a safeguard against an error in loading the command. When the
control recognizes this character it begins executing the command.
The control starts at sector 1, track 0 and reads the header information,
then starts a write operation. If the header information is damaged, the control will abort the operation.
If the operation is successfully completed, done is set and if bit 6 RX2CS
(interrupt enable) is set, an interrupt is initiated.
CAUTION
This operation takes about 15 seconds and should not be interrupted. If for any reason the operation is interrupted, an illegal diskette will be generated which may have data marks of
both densities. This diskette should be completely reformatted.
Maintenance Read Status (101) - This function is initiated by loading the
RX2CS with the command. Done is cleared. The drive ready bit (bit 7
RX2ES) is updated by counting index pulses in the control. The drive density is updated by loading the head of the selected drive and reading the
first data mark. The RX2ES is moved into the RX2DB. The RX2CS may be
sampled when done (bit 5 RX2CS) is again asserted and if bit RX2CS (interrupt enable) is set, an interrupt will occur. This operation requires approximately 250 ms to complete.
Write Sector with Deleted Data (110) - This operation is identical to function 010 (write sector) with the exception that a deleted data address mark
is written preceding the data rather than the standard data address mark.
The density bit associated with the function indicates whether a single- or
double-density deleted data address mark will be written.
Read Error Code (111) - The read error code function implies a read extended status. In addition to the specific error code, a dump of the control's
internal scratch pad registers also occurs. This is the only way that the
word count register can be retrieved. This function is used to retrieve spe·
cific information as well as drive status information depending upon detection of the general error bit.
The transfer of the registers is a DMA transfer. The function is initiated by
loading the RX2CS with the command; then done goes false. When TR is
true, the RX2BA may be loaded into the RX2DB and TR goes false. The registers are assembled one word at a time and are then transferred directly to
memory.

993

RXV21/M8029
F,oLl-OW1NG IS THE REGISTER PROTOCOL.
15

WORD 1

WORD COUNT REGISTER

DEFINITIVE ERROR CODE

CURRENT TRACK ADDR DRV 1

CURRENT TRACK ADDR DRV 0

TAAGET SECTOR

T AAGET TRACK

BAD TRACK

SOFT STATUS

15
WOAD 2

15
WORD3

WORD4

Definitive Error Codes
10

Drive 0 failed to see home on initialize.

Drive 1 failed to see home on initialize.

Tried to access a track greater than 76.

Home was found before desired track was reached.

Desired sector could not be found after 52 tries.

110

More than 40 J.ls and no SEP clock seen.

120

A preamble could not be found.

130

A preamble found but no 10 mark found within allowable time.

150

The track address of a good header does not compare with desired track.

160

Too many tries for lOAM.

170

Data was not found in allotted time.

200

CRC on reading the sector from the disk.

220

Failed maintenance wraparound check.

230

Word count overflow.

994

RXV21/M8029
240

Density error.

250

Incorrect key word on SET DENSITY command.

Register Protocol
Word 1<7:0>
Word 1< 15:8>
Word 2<7:0>
Word 2<15:8>
Word 3<7:0>
Word 3< 15:8>
Word 4<7>
Word 4<5>
Word 4<6><4>
Word 4<0>
Word 4< 15:8>

Definitive error codes
Word count register
Current track address of drive 0
Current track address of drive 1
Target track of current disk access
Target sector of current disk access
Unit select bit'
Head load bit'
Drive density bit of both drives'
Density of READ ERROR REGISTER command'
Track address of selected drive' •

RX02 Power Fail or Initialize
When the RX02 control senses a loss of power within the RX02, it will unload the head and abort all controller action. The RXAC L line is asserted to
indicate to the RXV21 that subsystem power has gone. The RXV21 asserts
done and error and sets the RXAC L bit in the RXZES.
When the RX02 senses the return of power, it will remove done and begin a
sequence to:
1. Move each drive head position mechanism to track 0
2. Clear any active error bits
3. Read sector 1 of track 1, on drive 0
4. Assert initialize done in the RXES.
Upon completion of the power-up sequence, done is again asserted. There
is no guarantee that information being written at the time of a power failure
will be retrievable; however, all other information on the diskette will remain
unaltered.
For DMA interfaces, the controller status soft register is sent to the
interface at the end of the command. The four status bits are included
in an 8-bit word. Unit select = bit 7; density of drive 1 = bit 6; head
load = bit 5; density of drive 0 = bit 4; density of READ ERROR REGISTER command = bit O.
The track address of the selected drive-error is only meaningful on a
code 150 error. The register contains the address of the cylinder that
the head reached on a seek error.

995

TSV05/M7196

TSV05 TAPE TRANSPORT AND BUS
INTERFACE/CONTROLLER

GENERAL

The TSV05 tape transport subsystem provides magnetic tape storage capabilities
to computer systems using quad-sized LSI-11 bus backplanes. The subsystem
reads or writes up to 160,000 bytes per second in ANSI standard format. Data is
recorded by phase encoding 1600 bits per inch on nine-track tape. Reading and
writing are performed at either 25 or 100 inches per second: The TSV05 subsystem is hardware compatible with 18- and 22-bit addressing versions of the LSI-11
bus quad backplane. It is software compatible with system and application programs written for the TS11 tape transport subsystem (as long as such programs
use the DIGITAL-supplied device handler). Tape formatting, error detection and
correction, and self-test diagnostics are included as integral components of the
TSV05 subsystem.
Voltage

+5 Vdc @ 6.5 A (max.)

Bus Loads
AC

3.0 (max.)

Standard Addresses

772520/772522
772524/772526
772530/772532
772534/772536

1st unit
2nd unit
3rd unit
4th unit

Vectors

224

1st unit
2nd unit
3rd unit
4th unit

100 IPS operating speed requires enabling special features and the appropriate software.
** Rank of 37 in the floating vector area starting at 300.

996

TSV05/M7196
Diagnostic Programs
CVTSAA
CVTSBA
CVTSCA
CVTSDA
CVTSEA
XTSAAO

Logic Test
Advanced Logic Test
Transport Test
Advanced Transport Test
Data Reliability Test
DEC-X11

Related Documentation
TSVD5 Tape Transport Pocket Service Guide (EK-TSV05-PS)
Operation and Maintenance Instructions for Model F88D Tape
Transport (799816- 000*)
TSVD5 Tape Transport Subsystem Installation Manual (EK-TSV05-IN)
XXDP User Guide (AC-90931-MC)
TSD5 Tape Transport Operation and Acceptance Preventive Maintenance
Remove/Replace (EY -D3142-PS)
TSV05 Field Print Set (MP-01157)
TSVD5 Subsystem Technical Manual (EK-TSV05-TM)
Microcomputers and Memories (EB-18451-20)
Microcomputer Interfaces Handbook (EB-17723-20)
TSV05 Hardware
TS05 tape transport
M7196 LSI-11 bus interface/controller module
H9642-series cabinet, including 874 power controller and remote power control
cable
Pair of 7016855 bus cables for connecting tape transport input and output to the
bus interface/controller module
The bus interface/controller module plugs into the LSI-11 bus. The two cables
connect the module with the tape transport.

TSV05-BA
TSV05-BB
TSV05-BD

Nominal, Vdc

Low Limit, Vdc

High Limit, Vdc

120
240
220

102

204

128
256
235

187

Electromagnetic Interference (EMI)
The TSV05 subsystem complies with FCC Part 15, Subpart J, Class A and is
designed to comply with VDE 0871 B requirements.

997

TSV05/M7196
NOTE

The TSV05 subsystem has been designed and tested to meet DIGITAL
standards, including FCC requirements. The specifications in this
chapter are based on this testing. DIGITAL cannot guarantee the
TSV05 subsystem will meet these specifications if nontested equipment is installed into the TSV05 cabinet or the TSV05 cabinet is
installed in nontested configurations.

~D~DDmD T805

00000

LOAD UNLOAD ON LINE WRITE
REWIND
TEST

ENTER

Operator Front Panel

998

TSV05/M7196
Controls and Indicators
Controll
Indicator

POWER

LOAD
REWIND

Type

Function

ONIOFF rocker switch
and indicator

Switches line power ON and OFF.

Tactile switch and
indicator

1. Blinks when the tape drive is
executing a load or rewind
sequence.
2. Lit continuously when the beginning of tape (BOT) marker is
sensed.
3. Pressing the switch:
a. Initiates load sequence and
advances tape to load point.
b. Rewinds the tape to load
point.

UNLOAD

Tactile switch and
indicator

1. Pressing the switch causes the
tape to be unloaded regardless
of tape position.
2. Blinks when the tape drive is
executing an unload sequence.
3. Lit continuously when the tape
drive has completed its unload
sequence and the front access
door is unlocked. At this time,
the tape may be removed and
another tape inserted into the
drive.
4. Lit continuously after a successful power up, indicating a tape
may be loaded.

999

TSV05/M7196
Controls and Indicators (Cont)
Controll
Indicator

ON-LINE

Type

Function

Tactile switch and
indicator

1. Lit when drive is ready and online.
2. Pressing the switch:
a. Takes the tape drive off-line
and extinguishes the
indicator.
b. Puts the tape drive on-line
and lights the indicators.

NOTE
Pressing the switch during a load sequence puts the tape drive on-line
when the BOT marker is sensed.

TEST

Tactile switch

Operational only in the test mode.
Selects alternative operational
mode for other switches.

WRITE

Indicator

1. Lit when the write ring is
installed and data may be written on tape.
2. When indicator is off, write ring
is not installed and tape is file
protected.

ENTER

Tactile switch

This control is used for manual
loading and controlling the test
mode.

1000

TSV05/M7196

. - - - - - THESE 14 ROMS ARE FACTORY

INSTALLED AND SHOULD NOT
BE REMOVED.

o
W2

VECTOR SWITCH PACK

~W5

ADDRESS

SWITCH~

El09

VECTOR SWITCHPACK

10
ON
V8

A121 E58

OFF

ADDRESS SWITCHPACK

4
::F

I I I
All

Ala

8
A7

10
A3

v = VECTOR BIT

51 = BUFFERING

A ~ ADDRESS BIT

SO~EXTENDEDFEATURES

JUMPERS
Wl

W2
W3

W4
W5
W6

E57

AS SHIPPED
BIR05
BIRQ7
BIR06
BUS GRANT CONTINUITY
BUS GRANT CONTINUITY
SCLOCK ENABLE (USED DURING FACTORY REPAIR ONLY)

M7196 Switch and Jumper Identification

1001

OUT
OUT
OUT
IN
IN
IN

TSV05/M7196

M7196 VECTOR AND ADDRESS SWITCHES

......_0 .L..I---,O1~~~~~~
1....°--,-1_0.L..I_O..1.1_°-LI_O--,I_O--,I_O_I1-°,-L-1,1.L. I,0. 1.1,°--,1,1--,1,°,11-1

IIIIIIII

STANDARD VECTOR
CONFIGURATION
(224)

OFF

OFF OFF

OFF

: ~~

OFF OFF

I I I I I I I I I

i~F~~ 11 1

13 1 4 1 5 1 6 17 1

STANDARD ADDRESS

CONFIGURATION
(172520)

1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 11 ° 1~~~;~~S

I I I I I I I I I I

OFF

E57

OFF OFF

BDAl BIT

L-",.--l-,-:--'--;-:-...L.,.,,-L.,..-L-:-::-1-=.J....,:-:-'-:::-'--::-::-'-=...L.::-:-'-:::-'-;:;:-'-=..L..::::-l POSITION

so = EXTENDED FEATURES (MUST BE "ON" FOR 22 BIT ADDRESSING)
51

= BUFFERING ("ON" INCREASES THROUGHPUT BUT DATA WILL BE LOST IF POWER FAilS, NORMALLY
NOT USED)

M7196 Vector and Address Switches

1002

TSV05/M7196
TAPE TRANSPORT
UNIT SELECT
SWITCH

JODeD 0 0000 D~ ~
00000000000000 8 Y

i~~ 000'000 o@o;:, ~ II
a y.

,. 0000000 0

O~~~0 ~oo~
i
00, '

r. ~~~ ~ .00000 ~W

~§:no 8 0
~~F::"3 ffiIIl#

II I,

000

@li

·NOTE: THE LAST (OR ONLY) TRANSPORT ON THE
BUS MUST HAVE THESE TWO DIP RESISTOR
PACKS INSTALLED. OTHER JUMPERS WITHIN
THE TRANSPORT ARE FACTORY-CONFIGURED
AND SHOULD NOT BE CHANGED. JUMPER
CONFIGURATION VARIES FROM BOARD TO
BOARD, DEPENDING ON THE EPROM TYPES IN
USE. HOWEVER, THIS DOES NOT AFFECT THE·
INTERCHANGEABILITY OF THE BOARO.

TAPE TRANSPORT UNIT SELECT SWITCH

OFF

UNIT SEL 0

UNIT SEL 1
SPECIAL IRG

220/
/330n

UNIT SEl 2

22~330n

EXT PARITY SEL
INT PARITY GEN
RESERVED
RESERVED

Ul0W

U3W

U8W

Transport Switch and Terminator Identification

1003

TSV05/M7196
MODEl

PLUG

{jj)

SILVER~
TSV05-BA

BRASS

NEMA # L5-30P
DEC # 1 2-11193

TSV05-BB

-BD

CIRCUIT RATING

RECEPTACLE

g==

BRASS2~
BRASS 1

NEMA #6-15P
DEC #90-08853

120 V
24A

L5-30R
12-11194

220/240 V
12A

6-15R

12-1 t 204

Power Line Connections

Power Cord Color Code
Color
Function

Brown
Blue
Green/yellow

Hot
Neutral
Ground

1004

Pin connection

LS-30P

6-1SP

Brass
Silver
Ground

Brass 1
Brass 2
Ground

TSV05/M7196

M7196
INTERFACE/CONTROLLER

MODULE

TRANSPORT
BUS

T505
TAPE TRANSPORT

M7196

M7196 Interconnection
1005

TSV05/M7196
M7196 MODULE

·FF

::~

PROFILE

CONNECTOR
RED STRIPE

Cabling the M7196 Module

TAPE TRANSPORT UNIT

Cabling the Tape Transport

1006

VSV11/M7061,2,4

VSV11 RASTER GRAPHICS SYSTEM

GENERAL
The VSV11 raster graphics system is a basic Q-Bus system designed for color
graphics operation with LSI-11 hosts.
This raster graphics module set is installed in a LSI-11 bus and a C-D
interconnect.
The first slot is reserved for either a CPU module or a connector which extends
the Q-Bus from another backplane. If slot 1 contains a CPU module, jumpers W1
and W3 must be removed in an H9273-A backplane used in a BA 11-S mounting
box. Rows C and D carry the video bus signals of the VSV11 system. This is
modified for 22-bit bus addressing. (backplanes H9273 and H9276).
The basic module set includes:
N7061-YA SYNC generator module
M7062 image memory
M7064 display processor module
Power Requirements

AC Power - The VSV11 system has one ac load, that being the M7064
(display process module), which is the only module in the VSV11 syst~m that
communicates with the CPU.

DC Power - To determine how many dc loads a VSV11 system has, count
the number of VSV11 modules (M7061, M7062, M7064) that reside on the LSI
bus. The total number is the number of dc loads. For example: a VSV11-AH
consists of:
1-M7061
2-M7062
1-M7064
4=dc loads

1007

VSV11 /M7061 ,2,4
Module
M7061

+5 V @ 2.8 A
+12 V @ 0.11 A

M7062

-5 V' @ 0.006 A
+5 V @ 1.7 A
+12 V @0.45A

M7064

+5 V @ 6.0 A

Standard Device Address

767010
Vector

720 (octal)
Diagnostic Program

CVVSA?
Related Documentation

VSV11 Raster Graphics System User Guide (EK-VSVFQ-UG)
DW11 Installation Guide (EK-DW11A-INO)
VSV11 Field Maintenance Print Set (MP-01012)
VRV02 Hitachi Monitor Maintenance Manual
VT101 Series Technical Manual (EK-VT1 01-TM)

'Supplied by M7061 module.

1008

VSV11 /M7061 ,2,4
M7061-YA SYNC GENERATOR/CURSOR CONTROL BOARD

Jumpers and switches are configuration dependent and are located as shown.

TI ~

M7061·YA

~~
~~

'V ~ R9
'V III

SET OPTIONS

~~----------~--~riW3

~li~[]]II
10

W17
W16

JO wi:rn
~

"w21

E21 SWITCH W14
PACK
W19

M7061-YA Switches and Jumpers

1009

VSV11 /M7061 ,2,4
H9271-A
OR

H9276
BACKPLANE

LEFT OPEN FOR CPU OR M9401

========:::::l...

3CI

M7061·YA
M7062

M7Q62

M7062
M7062
M7064

Module Placement Example, Four (Extended) Memory Systems

IN ONE MEMORY
SYSTEM,
OCCUPIES SLOT 3
ROWS C-F
IN TWO MEMORY

ROWS C-F

...4JI6IN TWO MEMORY

r1SYSTEMS,

",'"

I OCCUPIES SLOT 3
I ROWS C-F
I

. OCCUPIES SLOT 2

I
OCCUPIES SLOT 1
ROWS C-F

SYNC BOARD

M7061-YA

NOTE
IN SINGLE MEMORY
SYSTEM, THIS
CONNECTOR NOT
USED.

Intermodule Cabling Example, One or Two Memory Systems

1010

VSV11/M7061,2,4
M7061-YA Cable Connectors
The three cable connectors located on the M7061-YA module are:

J1 -

Accepts the drive board cable

J3 -

Accepts the driver board cable with the read stripe toward J4

J4 -

Accepts the beginning end of the daisy chain to memories and display
processor.

H349 BULKHEAD

FRAME

M7061-YA Interconnecting Cables

1011

VSV11 /M7061 ,2,4
M7061-YA Switch Selections
Selection

Switch Settings

60 Hz'
50 Hz

E21-1
OFF
ON

E21-2
ON
OFF

Interlaced'
Noninterlaced
Special

E21-3
OFF
ON
OFF

E21-9
ON
ON
OFF

Normal Scan'
Special Scan

E21-4
OFF
ON

E21-5
ON
OFF

Master'
Slave

E21-6
ON
OFF

External Sync·t
Internal Synct

E21-7
ON
OFF

E21-8
OFF
ON

'These are factory settings.
tUse external sync when doing adjustments.

1012

E21-10
OFF
ON

VSV11 /M7061 ,2,4
M7061-YA Jumper Selections
Selection

Jumper State
W19

Master·
Slave

IN
OUT
W3

External Sync·
Internal Sync

Channel 0
Channel 1
Channel 2
Channel 3

White Cursor·
Green and Blue Cursor
Green and Red Cursor
Green Cursor

Small Cursor·
Large Cursor

16 Shades/Colors
8 Shades/Colors

IN
OUT
W5

OUT
OUT
IN
IN

IN
IN
OUT
OUT

OUT
IN
OUT
IN

IN
OUT
IN
OUT

W10

W11

IN
IN
OUT
OUT

IN
OUT
IN
OUT

W16

W17

IN
OUT

W21

W22

OUT
IN

IN
OUT

·These are factory settings.

1013

VSV11 /M7061 ,2,4
VSV11 Module M7061-YA - E21 Factory Switch Settings
E21 Switch No.
Selection

60 Hz'

OFF ON

50 Hz

OFF

Interlaced"

OFF

Noninterlaced

Special

OFF

Norm Scan"

OFF ON

Special
Scan

OFF

Master"

Slave

OFF

External
Sync"

OFF

Internal
Sync

OFF ON

"These are factory settings.

1014

Customer
Selection

VSV11 /M7061 ,2,4
VSV11 Module M7061-YA Factory Set Jumper W - States
Jumper
W
Selection

Customer

Master'
Slave

External
Sync'
Internal
Sync

Channel 0

Channel 1

a
a

Channel 2

Channel 3

a
a

White
Cursor'
Gr+B1
Cursor

GR+Rd
Cursor

Green
Cursor

Small
Cursor'
Large
Cursor

16 Colors'

a
a

8 Colors

'These are factory settings.
a = aut
I = In
1015

Selection

VSV11 /M7061 ,2,4
M7062 MEMORY BOARD
The M7062 memory board is used in all VSV11 system configurations. The number of memory boards installed can vary depending on the number of memory
modules in the systems configuration. One, two, or four memory modules can be
present in a VSV11 system configuration. A three memory module system does
not exist.
Switches and Jumpers
There are two switch packs located on the M7062 module, E59 and E49, which are
the data size and memory organization. These switches must be configured for
the number of memory modules present in a systems configuration. Set the switch
and jumpers as listed below.
NOTE
Cut pin 9 on resistor pack E77 on the first memory module only, in any
configuration including a one memory module configuration.

M7062
SWITCH PACK

E59
J1

En E = : ]

!~~~~~ARTOR 0Wl

E76E=:] PACKS

SET NUMBER
OF MEMORIES

SET DATA SIZE
AND MEMORY
ORGANIZATION
(TABLE 2-3)

(TABLE 2-41

ON 1

1111111111 SWIT~4~PACK
OFF

M7062 Memory Board

1016

VSV11 /M7061 ,2,4
M7062 E49 and E59 Switch Settings· and
E76/77 Terminator Configuration
One Memory

Two Memories

Four Memories

Noninterlaced

Interlaced

1st

2nd

Channel 0 Channel 1
1st 2nd 3rd 4th

OFF

OFF ON

OFF

OFF ON

OFF

OFF ON

OFF

OFF ON

OFF

OFF OFF OFF OFF

OFF

OFF OFF OFF OFF

OFF

OFF OFF OFF OFF

OFF

OFF OFF OFF OFF

OUT

OUT OFF OFF

77t

OUT

OUT OUT OUT

TRM

'Note that both switches are set identically.
tAlways remove and cut pin 9 and reinstall when IN.

1017

VSV11 /M7061 ,2,4
M7062 Jumper Selections

One Memory

Two Memories

Channel 0

Four Memories
Channel 1

OUT

1018

VSV11 /M7061 ,2,4
M7064 DISPLAY PROCESSOR MODULE
The M7064 display processor module controls transactions between the control
logic and the LSI-11 bus logic. Switches on this module accommodate the host
system.

M7064

1
SET\
DEVICE

~r,r
~"~:'~~
0

BIT
NO

SWITCH

STATE

•

VECTOR

OFF OFF OFF ON ON OFF ON OFF

SWITCH

I I u-u
I I I I I n..n

STATE

OFF OFF ON ON ON OFF ON OFF

SLIDER
SWITCH

ROCKER

~~~;~H !...J...J

~~~~~~

I I L..J"\..J

r-n I I n..n

DEVICE ADDRESS

BIT
NO
SWITCH

PDp·11

PDP-l1

320

772010

(OCTAL)

{OCTAL}

STATE

VAX

720

767010

(OCTAL)

(OCTAl)

~
•
5

ON OFF ON OFF OFF OFF OFF OFF OFF ON

~~~;CAH n..,J'!

~~~~~~ ~
STATE

VAX

I I I I I Ll
I I I I I !;;;;J

OFF ON ON ON OFF OFF OFF OFF OFF ON

~~~,';H CJ""t"M
~0~~;~ U

I I I I r::J
I I I I I I ~

NOTE: TWO SWITCH TYPES MAY BE USED. BOTH HAVE THE SAME PART NUMBER.

Address and Vector Switch Settings for Module M7064

Install the sync generator module (M7061-YA) in slot 2 with either the CPU module
or an M9401 bus extender card occupying slot 1. Next, insert the M7062 memory
module(s) (up to 4). The last module to be inserted is the M7064 display processor
module, next to the last memory module.

1019

VSV11/M7061,2,4
VSV11 Module M7064 - Switch Settings

Selection

System

Octal

Switch
Pack
No.

Factory
Setting

Vector

PDP-11

320

E43

OFF
OFF
OFF
ON
ON
OFF
ON
OFF

1
2
3

4
5
6
7

8
VAX

E43

720

1
2
3

4
5
6
7

8
Device
Address

PDP-11

772010

E31

1
2
3

4
5
6
7

8
9
10
VAX

767010

E31

1
2
3

4
5
6
7

8
8
10

1020

OFF
OFF
ON
ON
ON
OFF
ON
OFF

ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ON

Customer

VSV11 /M7061 ,2,4
Task Module 5 - Joystick

The joystick is used in this system to move and mark the cursor on the screen.
The equipment to be installed consists of the joystick itself, its cable, and an
extension cable as shown below.

JOYSTICK

JOYSTICK
ASSEMBLY

JOYSTICK

HORIZONTAL BALANCE AOJ

Joystick Components

1021

VSV11 /M7061 ,2,4
CAUTION
Never connect the joystick to a system while power is on. To do this
can damage the M7061-YA Sync Gen/Cursor Ctrl module.
Shown below are the joystick and 4-conductor cable connections.
JOYSTICK

H349 BULKHEAD

FRAME

VRV02

Joystick Installation and 4-Conductor Cable Connection

1022

RC25

RC25 8-INCH DISK DRIVE SUBSYSTEM

GENERAL
The RC25 is a self-contained mass storage device that is used with a host to store
up to 52 million characters on two, hard, 8-inch disk platters.
One disk platter is fixed and the other is removable. Both platters are mounted on
the same spindle. The RC25 is available as a table top or rack mounted subsystem. The two types of RC25 units are the master and the slave. The disks on the
master and slave units are interchangeable.
The master, containing the controller module, can drive two spindles (one master
and one slave), and must be the first drive in a subsystem.

Related Documentation
RC25 Disk Subsystem User Guide (EK-ORC25-UG)
RC25 Slave Disk Drive Customer Installation Guide (EK-RC25S-IN)
RC25 Disk Subsystem Installation Guide (EK-ORC25-IN)
RC25 Disk Subsystem Pocket Service Guide (EK-ORC25-PS)
Illustrated Parts Breakdown (EK-ORC25-IP)
RC25 Field Maintenance Print Set (MP-01612-00)
MSCP Basic Disk Functions Manual (AA-L619A-TK)
Storage Systems UNIBUS Port Description (AA-L621A-TK)

1023

RC25

HOST COMPUTE R
SYSTEM BUS
(UNIBUS, LSI-ll1

•

RC25 Disk Subsystem Components

1024

•

RC25

DIMENSIONS

CENTIMETERS

INCHES

A. HEIGHT

26.5

10.5

B. WIDTH

48.3

19.0

C. DEPTH

56.2

22.1

Space Planning for the Rack-Mount Unit

1025

RC25

DOES NOT
CONTAIN
CONTROLLER

MR·12913

RC25 Master and Slave Disk Drives

1026

RC25

EXHAUST

COOLING
AIR IN

DIMENSIONS

CENTIMETERS

INCHES

A. HEIGHT

25.6

10.1

B. WIDTH

25.4

10.0

C. DEPTH

52.1

20.5

Space Planning for the Tabletop Unit

1027

RC25

.~~A~~j'ee\
~

C
j'eeS'"

INTERFACE CONNECTORS

1111111111111111

!~~e~~~

MA-12915

Voltage Selector Switch and ON/OFF Circuit Breaker

1028

RC25
SPECIFICATIONS
The following list names the primary performance, power, environmental, and

physical characteristics of the RC25.
Size

Tabletop model
Height
Width (master or slave)
Depth

25.6 cm (10-1/8 in)
25.4 cm (10 in)
52.1 cm (20-1/2 in)

Rackmount model
Height
Width
Depth

26.5 cm (10-1/2 in)
48.3 cm (19 in) centers
56.2 cm (22-1/8 in)

Weight

Tabletop model

22.7 kg (50 Ib)

Rackmount model
Single disk
Dual disk

29.5 kg (65 Ib)
54.4 kg (120 Ib)

Environment

Temperature
Operating

10°-40°C (50°-104°F) ambient with a gradient of 10°C (18°F)/hr

Nonoperating
(storage/shipping)

-40°-66°C (-40°-151° F) ambient with a
gradient of 20°C (36°F)/hr

Relative humidity
Operating

10% - 90% with maximum wet bulb temperature of 28°C (82°F) and a minimum dew
point of 2°C (36°F) with no condensation

Nonoperating
(storage/shipping)

5% - 95% with no condensation

Altitude
Operating

Sea level to 2.4 km (8000 tt)
Maximum operating temperatures decrease
by a factor of 1.8°C/1 OOO-WF /1000 ft) for
operation above sea level.

Nonoperating
(storage/shipping)

Up to 9.1 km (30,000 tt) above sea level
(actual or effective by means of cabin
pressurization)

1029

RC25
Shock

5 g peak at 7-13 ms duration in three axes
mutually perpendicular (maximum)

Heat Dissipation
Single disk drive
Dual disk drive

1091 Btu/h
1828 Btu/h

Noise level (single disk)

53 dB at 1 m

Electrical
Voltage/frequency
(single phase)

90-128 Vac, 6.6 A, 47-63 Hz
180-256 Vac, 3.5 A, 47-63 Hz

Power (operating)
Single disk
Dual disk

320 W
536 W

Line cord length
(from enclosure)

1.83 m (6 ft)

Plug type
120 Vac
220-240 Vac
Data Capacity (Formatted)
Single disk drive

Dual disk drive

Media
Fixed

Removable

Seek Time
Average seek
One track seek
Maximum seek

NEMA 5-15P
NEMA 6-15P

26.061824 Mb fixed disk
26.061824 Mb removable cartridge disk
52.123648 Mb total
(50,902 512-byte blocks/platter)
52.123648 Mb fixed disk
52.123648 Mb removable cartridge disks
104.247296 Mb total
(101,804 512-byte blocks/platter)

One 20 cm (7-7/8 in) double-sided nonremovable disk platter per drive
One 20 cm (7-7/8 in) double-sided disk platter in cartridge per drive

35 ms maximum
10 ms maximum
55 ms maximum
1030

RC25
Latency
Speed
Average rotational latency
Maximum rotational latency
Average access

2850 r/min ± 9 r/min
10.5 ms
21.0 ms
45.5 ms (overlapped seeks with double disk
drive configuration)

Data Rates
Average long transfer rate

0.57 Mb/sec typical

Spiral Read time
Per track
Per disk
Per drive

31 ms typical
50 s typical
1 min, 40 s typical

Start/Stop Time
Start time

Stop time

60 sec maximum (includes purge and selftest time)
30 sec maximum

Safety precautions are listed with the following agencies.
UL

Underwriter Laboratories

CSA

Canadian Standards Association

VDE

Verband Deutscher Electrotechniker (German Electrical Engineering Society)

IEC

International Electrotechnical Commission

1031

RC25
Indicator States and Their Meaning

Run

Write Protect
Removable Fixed Fault

OFF

The drive is not running and the cartridge receiver door is unlocked.

Slow
flash*

OFF

The disk platters are spinning up or
down.

OFF

The drive is ready to accept
commands.

Eject Meaning

OFF

The removable disk cartridge is write
enabled.

OFF

The removable disk cartridge is in the
read-only state. Writing is prevented.

OFF

The fixed disk platter is write
enabled.

OFF

The fixed disk platter is in the readonly state. Writing is prevented.

The drive has detected a failure.
Press FAULT briefly and refer to the
fault codes in Chapter 5 to determine
what went wrong.

slow
flash*

The drive is in maintenance mode
and is running a test.

*Slow flash is once per second.

1032

RC25

CONTROLLER
FAIL
INDICATOR
-RED(MASTER DRIVE
ONLY)

mamaD~D
CARTRIDGE
DISK
RECEIVER
DOOR

RC25

Write Protect
Run

Removable Fixed

Fault

[CJ]DJC][[JJ
Unit Select

000/001

Eject

[[JJ

OPERATOR
PANEL

RC25 Front View Showing Operator Panel

Cartridge Loading
The RC25 is designed to make correct loading easy. To load the cartridge disk,
hold it label (writing) side up with the tapered end toward you. The opposite end
has a small trap door through which the read/write heads enter. This end enters
the cartridge receiver first.
If the cartridge receiver door is not open, press the EJECT button. The door opens
and swings down. Slide the cartridge straight in with a firm push until it locks into
place. Close the receiver door firmly by swinging it back up and latching it into
place.
Cartridge Unloading
Unloading the cartridge is as simple as loading. With the spindle stopped and the
receiver door unlocked (EJECT indicator on), press the EJECT button. The door
opens and the cartridge disk ejects. Once the door is open, grasp the cartridge
and pull it straight out of the receiver.
NOTE
Keep the cartridge receiver door closed when not in use to prevent
atmospheric contaminants from entering the disk enclosure.

1033

RC25

Inserting
. t he Disk Cartridge

1034

RC25
Disk Operating Procedures
The procedures in this section are for starting and stopping the RC25.
Starting Procedure
Operator Action

Disk Drive Response

None.

Initial state of disk drive:
RUN button is released (out).
RUN indicator is off.
EJECT indicator is on.

Spindle is stoppled
Press EJECT.

Cartridge receiver door opens and disk cartridge partially ejects.

Reload cartridge or
replace with new cartridge.

None.

Close cartridge receiver
door.

None.

Set WRITE PROTECT buttons.

Press RUN in to lock it in.

Corresponding WRITE PROTECT indicator
lights or goes off.
Receiver door locks.
EJECT indicator goes off.
RUN indicator flashes slowly.

Disk platters spin up.
RUN indicator lights continuously.

Disk is ready for operation.

NOTE
A disk cartridge must be installed to spin up and operate the disk
drive. The fixed disk does not spin up and run without a removable
cartridge in place. The spin-up cycle takes approximately 1 minute. It
involves spinning the disk platters up to operating speed, cleaning the
internal air system, loading the read/write heads, and performing a
self-test.

1035

RC25
Stopping Procedure
Operator Action

Disk Drive Response

None.

Initial state of disk drive:
RUN button is pressed in.
Disk platters are spinning.
RUN indicator is on.
EJECT indicator is off.

Press RUN in to release it.

RUN indicator flashed slowly.
Disk platters slow down.

When disk platters stop spinning:
RUN indicator goes off.
EJECT indicator lights.

Receiver door unlocks.
Press EJECT.

Receiver door opens partially. Push down
door to eject cartridge fully.

Remove disk cartridge.
Close receiver door.
CAUTION
Do not try to open the receiver door until the EJECT indicator lights
and the EJECT button is pressed; you can damage the disk drive and
cartridge.

1036

RC25
Unit Select Number

The host computer system (or computer network) locates a peripheral device via a
unit select number. The RC25 can have any number pair from 0/1 to 252/253. It
has a pair of numbers because both disk platters have a unique number. The
removable disk platter always has an even number and the fixed disk platter
always has an odd number. The unit select number is chosen during installation,
but may be changed any time thereafter.
The unit select number is determined by a factory wired plug. This plug can be
removed and replaced to change the number. However, the RC25 cannot function
without a plug in place. The result is a fault indication. Two disk drives with the
same unit select number also cause a fault.
Change the unit select number plug by grasping the plug handle and pulling it
straight out of the operator panel. Install the new number plug by pushing it
straight into the empty, recessed socket. When installing the new plug, be sure to
hold it so the numbers are right side up. Do not try to force an upside down plug
into the socket. This mistake creates a false number and destroys the electronic
components inside the operator panel.

Changing the Unit Select Number Plug

1037

RC25
HOW TO MODIFY THE UNIT SELECT NUMBER PLUG
If you want to use a unit select number pair of 8/9 or higher for your RC25, you
must open and modify the unit select number plug. The procedure in this appendix
shows you how to make the modification.

Remove the plug on the operator panel by grasping the plug handle and
pulling it straight out.

The plug contains a small, eight-position DIP switch. Remove this switch from
the handle by spreading apart the two plastic retaining tabs and pulling
straight out.

When working with the switch, hold it so the number 1 position is on the left,
as shown below.

BBBBBBB:
6

Unit Select Number Switch

Find the number pair you want and set the seven switches as indicated.
Three different types of switches are used in the RC25: one slide switch and
two types of rocket switches. It is important to identify which type of switch
your drive has before trying to change the number. To change the number
with a slide switch, push the switch tab to OFF or ON (up or down) as
indicated in the table. To change the number with a rocket switch, press in on
the corresponding side of the switch.

After setting the new number, press the DIP switch back into the plug handle
and insert the plug back into the operator panel.

1038

RC25
Unit Select Number Switch Settings
Unit
Number

DIP Switch Position Number

0/1
2/3
4/5
6/7
8/9

ON
ON
ON
ON
ON

ON
ON
ON
ON
OFF

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

10/11
12/13
14/15
16/17
18/19

ON
ON
ON
ON
ON

ON
ON
ON
OFF
OFF

OFF
OFF
OFF
ON
ON

ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF

20/21
22/23
24/25
26/2.7
28/29

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
OFF

ON
OFF
ON
OFF
ON

30/31
32/33
34/35
36/37
38/39

ON
ON
ON
ON
ON

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
ON
ON

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

40/41
42/43
44/45
46/47
48/49

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
OFF

OFF
OFF
OFF
OFF
ON

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

50/51
52/53
54/55
56/57
58/59

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF

60/61
62/63
64/65
66/67
68/69

ON
ON
ON
ON
ON

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
ON

OFF
OFF
ON
ON
OFF

ON
OFF
ON
OFF
ON

1039

RC25
Unit Select Number Switch Settings (Cont)
DIP Switch Position Number

Unit
Number

70/71
72/73
74/75
76/77
78/79

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

80/81
82/83
84/85
86/87
88/89

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
OFF

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

90/91
92/93
94/95
96/97
98/99

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
OFF
OFF

OFF
OFF
OFF
ON
ON

ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF

100/101
102/103
104/105
106/107
108/109

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
OFF

ON
OFF
ON
OFF
ON

110/111
112/113
114/115
116/117
118/119

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
ON
ON

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

120/121
122/123
124/125
126/127
128/129

ON
ON
ON
ON
OFF

OFF
OFF
OFF
OFF
ON

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

130/131
132/133
134/135
136/137
138/139

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF

1040

RC25
Unit Select Number Switch Settings (Cont)
DIP Switch Position Number

Unit
Number

140/141
142/143
144/145
146/147
148/149

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
ON

OFF
OFF
ON
ON
OFF

ON
OFF
ON
OFF
ON

150/151
152/153
154/155
156/157
158/159

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

160/161
162/163
164/165
166/167
168/169

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
ON
ON
ON
OFF

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

170/171
172/173
174/175
176/177
178/179

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
OFF
OFF

OFF
OFF
OFF
ON
ON

ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF

180/181
182/183
184/185
186/187
188/189

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
OFF

ON
OFF
ON
OFF
ON

190/191
192/193
194/195
196/197
198/199

OFF
OFF
OFF
OFF
OFF

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
ON
ON

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

200/201
202/103
204/205
206/207
208/209

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
ON
ON
ON
OFF

OFF
OFF
OFF
OFF
ON

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

1041

RC25
Unit Select Number Switch Settings (Cont)
Unit
Number

DIP Switch Position Number

210/211
212/213
214/215
216/217
218/219

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF

220/221
222/223
224/225
226/227
228/229

OFF
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
ON

OFF
OFF
ON
ON
OFF

ON
OFF
ON
OFF
ON

230/231
232/233
234/235
236/237
238/239

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

240/241
242/243
244/245
246/247
248/249

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
OFF

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

250/251
252/253

OFF
OFF
OFF

ON
OFF
OFF

OFF
ON
OFF

ILLEGAL

1042

RD51

RD51 11 Mb WINCHESTER DISK DRIVE SUBSYSTEM

GENERAL

The RD51 fixed Winchester single element disk subsystem, found inside the
MICRO/PDP-11 and the MICRO VAX, can be attached to an existing 22-bit
MICRO, MICRO VAX, or a PDP-11/23 PLUS system.
The RD51 controller interface is used for both the RD51 and the RX50 disk and
diskette drives.
Related Documentation

MICRO/PDP-II Technical Manual (EK-OLCP5-TM)
MICRO/PDP-II Owner's Manual (EK-OLCP5-0M)
MICRO/PDP-11 Unpacking and Installation (EK-OLCP5-IN)
RQDXI Controller Module User Guide (EK-OLCP5-UG)
MICRO/PDP-II System Option Manual (EK-OLCP5-0D)
H9302 Rack Mount Adapter Kit Instruction Manual (EK-LEP03-IN)
RD51 Subsystem Component Specification

Unit Storage Capacity
11 megabytes (formatted data) 18 sectors
Power Supply Assembly
Inputs
Switch able line voltage
Line frequency
Line current

100-120 Vac (normal)
200-240 Vac (normal)
47-63 Hz either input range
120 Vac @ 2 A RMS (max)
240 Vac @ 1 A RMS (max)

Output
Power

65 watts (max)

DC Voltage

+ 12A Vdc +5% 1 A min. (4.5 A max.)
+128 Vdc ±10% .12 A (max.)
+5 Vdc ±5% @ .3 A min to 2 A (max.)

1043

RD51
Dimension

12 in long
9 in wide
3 1/2 in high

Weight

141bs

Controls and Indicators
Switch ON/OFF (1 or 0) rocker switch - connects ac power to the subassemblies
internal dc power supply.
Front Panel LEDs

Lit

Not lit

Top Green LED

RD51 ready

RD51 not ready

Middle Green LED

DC power present

DC power not present

Amber LED

RD51 write protect

RD51 not write protected
LED RD51 DRIVE
READY

LED + 5 V
LED SWITCH

AC POWER

~
~

RD5~

-----,

"'I

MR-13097

Front Panel, Switches and Indicators

1044

RD51
Rear Panel Connectors
J1 - DUO
J2 - DU1
J3 - DU2
Inside the BA23 system chassis (MICRO/PDP-11 and MICRO VAX 1) an RQDX1
drive controller, RQDX1-E extender module and cables are used. (Cabinet kit CKRQDX1-KA)
PRIMARY VOLTAGE
SELECT SWITCH

120/240
AC LINE
CIRCUIT B,EAKER

.y
@

I ®

~ IJ1i o~·:::::::::::.~o

I
I

[3 I

J2i or:;,:::::::::::.~o

r; I

J3i or:;,:::::::::::.~o I

'-'

PRIMARY VOLTAGE
INPUT
MR-13099

Rear Panel Assembly

1045

RD51
VARIOUS CONFIGURATIONS FOR EXPANSION OF THE RD51

PATCH AND FILTER
PANEL ASSEMBLY

EXTERNAL CABLE

CABINET KIT CABLE
(30" FOR H349 ENCLOSURE)
CK-RODXI-KC

Single Expansion Configuration

PATCH AND FILTER

PANEL ASSEMBLY

EXTERNAL CABLE

CABINET KIT CABLE
(30" FOR H349 ENCLOSURE)
CK-RQDXI-KC

-I

Double Expansion Configuration

1046

RD51

INBOARD
DRIVES

BULKHEAD

Maximum Expansion Configuration

1047

RD51
J1, J2 and J3 Pin Numbers and Signal Names

Connectors J1, J2, and J3 have identical signal names and pin numbering.

Pin No.

Signal Name

Pin No.

Signal Name

J1-01
J1-34
J1-18
J1-02
J1-35
J1-19
J1-03
J1-36
J1-20
J1-04
J1-37
J1-21
J1-05
J1-38
J1-22
J1-06
J1-39
J1-23
J1-07
J1-40
J1-24
J1-08
J1-41
J1-25
J1-09

MEMWRTDT1 (H)
MEMWRTDT1 (L)
GROUND
HEAD SET 2 (L)
GROUND
SEEKOPLT
RD1 RDY (H)
WPT FAULT (L)
GROUND
READ SEL 1 (L)
RXOWPTLED (L)
RDO RDY (H)
RX1WPTLED (L)
DRVSLOACK (L)
MEMRDDATO (H)
MFMRDDATO (L)
MFMWRTDTO (H)
MFMWRTDTO (L)
MFMRDDAT1 (H)
MFMRDDAT1 (L)
GROUND
RFDUCWRTI (L)
RDOWRTPRO (L)
DRV SEL 4 (L)
GROUND

J1-42
J1-26
J1-10
J1-43
J1-27
J1-11
J1-44
J1-28
J1-12
J1-45
J1-29
J1-13
J1-46
J1-30
J1-14
J1-47
J1-31
J1-15
J1-48
J1-32
J1-16
J1-49
J1-33
J1-17
J1-50

INDEX (L)
RD1 WRTPRQ (L)
DRV SEL 1 (L)
DRV SEL 2 (L)
DRV SEL 3 (L)
RX2WPTLED (L)
RXMOTORON (L)
GROUND
DIRECTION (L)
GROUND
STEP (L)
GROUND
RXWRTDATA (L)
GROUND
WRT GATE (L)
GROUND
TRACK 00 (L)
RX3WPTLED (L)
DRVSL 1ACK (L)
GROUND
READ DATA (L)
GROUND
HEAD SEL 0 (L)
GROUND
READY (L)

1048

RD51
Power Supply Connectors

AC Power Input Connector

Pin No.

Signal

Ground
ac phase
ac neutral

2
3

DC Power Output Connector

Pin No.

Signal

1
2

+5 V
+5 V
+5 V
Return
Return
Return
Return
12 VA
12 VA
12 VB
No pin
No connection

3
4
5

6
7
8
9
10
11
12

1049

RDS1
Logical Unit Number Selection

The logical unit number (LUN) selection is set by jumpers on the RODX1 Controller
module. These jumpers are set to the lowest LUN assigned to any RD51 or RX50
drive subsystem that is controlled by the RODX1. The RODX1 module automatically senses the logical unit configuration during initialization of the system to determine how many of the four possible units are actually present.
The LUN jumper format allows only one jumper to be installed at a time, and each
individual jumper specified a group of four logical units as follows.

LUN Jumper

LUNs Specified

No jumper installed
1

0-3
4-7
8-1
12-15
16-19
20-23
24-27
28-31
32-35

2
3
4

5
6
7
8

Within the context of RODX1 configurations as shown below, if number 4 jumper is
connected and using configuration number 2, then:
16 = unit 0
17 = unit 1
18 = unit 2
19=unit3

Configuration

External subsystem
disk drives

Logical numbers
for disk drives

One RD51, one RX50

Unit 0 = RD51
Units 1, 2 = RX50
Units 0, 1 = RX50
Units 2, 3 = RX50

Two RX50s

Two RD51 s, one RX50

Unit 0 = RD51
Unit 1 = RD51
Units 2, 3 = RX50

Two RD51s

Unit 0 = RD51
Unit 1 = RD51

One RX50

Units 0, 1 = RX50
1050

RD51
Expansion
MICRO/PDP-11 and MICRO VAX I systems contain inboard RD51-A and RX50-AA
drives and both systems are housed in BA23 enclosures. Each system also contains an RQDX1 controller. The controller has a capacity of four LUNs, three of
which are used internally. Thus, only one RD51 drive can be added externally to
the MICROjPDP-11 and MICRO VAX I.
A BA23 enclosure (MICROjPDP-11 and MICRO VAX I) prior to any add-on RD51,
contains:
1 RQDX1 controller
1 CK-RQDX1-KA cabinet kit
1 RD51-A (drive only)
1 RX50-AA (drive only)
To accommodate an external add-on drive, an RQDX1-E bus extender and cable
must be added internally and connected to the patch and filter panel assembly.
A PDP-11/23 PLUS system, to accommodate external add-on drives, requires
internally an RQDX1 controller and a cabinet key cable CK-RQDX1-KC connected
to the H349 distribution panel.

REMOVABLE
INSERT

50-PIN CONNECTOR
EXPANSION SLOTS
MF't-9529

BA23 Patch and Filter Panel Assembly

1051

RD51

DZVll

DRVll-J

(SYNC LINE INTERFACE)

DRVll-J
PARALLEL
LINE INTERFACE

~:EJ1 ,:t-l~

0"0 t::::b--- """

DZVll

DLVll-J

PDP-11/23 PLUS/H349 Distribution Panel (Bulkhead)

1052

RD52

RD52 31 Mb WINCHESTER DISK DRIVE SUBSYSTEM

GENERAL

The RD52 fixed disk drive uses an RQDX1 controller and contains three nonremovable 5-1/4 inch disks as storage media. The three 5-1/4 inch disks can store
up to 31 megabytes of formatted data.
The interface between the disk drive and the host controller consists of four
connections:
11 - Control Signals
12 - ReadfWrite Signals
13 - DC power
14 - Frame ground

Jl - CONTROL SIGNALS
J2 - READIWRITE SIGNALS
J3 - DC POWER
J4 - FRAME GROUND

J4
J2

PIN 1

RD52 Connector Locations

1053

RD52
Power Requirement
+5 Vdc +5% @ 1.0 A
+12 Vdc +5% @ 2.5 A (4.5 A max.)

VOLTAGE
MAX
START

TYP
START

MAX
SEEKING

TYP
SEEKING

MAX
STEADY
STATE

TYP
STEADY
STATE

1.5AMP

1 AMP

1.5AMP

1 AMP

1.5 AMP

1 AMP

50mV

+12

4.5 AMP

3.8 AMP

3AMP

2.5 AMP

2 AMP

1.5AMP

50mV

MAX
RIPPLE
P- P

CURRENT REQUIRMENTS

5
MAXIMUM

TYPICAL

AMPS

TIME (SEC)
+12V STARTING CURRENT

+12 V Starting Current
Related Documentation
RDS2-D,R Disk Drive Subsystem Owners Manual (EK-LEP03-0M)
Physical Size
Height - 3.25 in
Width - 5.75 in
Depth - 8.0 in
Weight - 14 Ibs

1054

RD52
Connectors
J1 - 34 pin - control signal
J2 - 20 pin +12 Vdc data signals
J3 - 4 pin +5 Vdc dc power
J4 - single log - frame ground

TERMINATOR
RESISTOR PACK

+5V
RETURN

DRIVE SELECT
JUMPERS
4 3 2 1 R

RD52 Power Connector (J3)

CAUTION
Damage will occur to the drive if the +5 V and +12 V connections are
reversed.

CAUTION, DAMAGE WILL OCCUR TO THE DRIVE IF THE +5V AND +12V
CONNECTIONS ARE REVERSED.

+12V

+12V
RET

+5V
RET

+5V

NOTE,

THIS IS THE DRIVE END OF THE CONNECTOR

Selectable Address Internal

NOTE
This is the drive end of the connector.

1055

RD52
Environmental Limits

Operating temperature
Non operating temperature
Operating humidity
Non operating humidity
Maximum wet bulb
Thermal gradient
Operating altitude
Operating vibration
Non operating shock

10° to 50 ° C
-40° to 60° C
10% to 80%
5% to 95%
25° C (Non-condensing)
10°C per hour
o to 10,000 feet
.5 G at 10-500 Hz
30 Gs

Capacity Unformatted (+10 space cylinders)
Per drive
Per surface
Per track

33.07 MB
6.61 MB
10.416 KB

Capacity Formatted (+10 Spare Cylinders)
Per drive
Per surface
Per track
Per sector
Sectors/Track
Transfer rate

26.00 MB
5.20 MB
8.192 KB
256 bytes
32
5 Mbitfsec

Seek Time
Track to track
Average
Maximum
Settling
Average latency
Start time

3.0 ms
30.0 ms
60.0 ms
3.0 ms
8.33 ms
15 sec

Functional Summary

Rotation ±1%
Recording max
Flux density
Track density
Data cylinders
Tracks
RfW heads
Disks
Index

3600 rpm
8780 bpi
8780 fci
800 tpi
645
3175
5

3
1

1056

RD52
15 SEC MAX - - - _
DC DN
4 - 11

SECTYP ....

DISK UP
TO SPEED

1 SEC
TYP

AUTD RECAL
-TRACK 0

-READY

-SEEK
COMPLETE

30l'SEC

l.... I-I+-

TYP 1 SEC

-TRACK 0, -READY AND -SEEK COMPLETE WILL NOT BE PRESENT AT THE INTERFACE
UNLESS THE DRIVE IS SELECTED.

Power-Up Sequence

FLAT CABLE OR TWISTED PAIR
20 FEET MAXIMUM
HOST SYSTEM

DISK DRIVE
DRIVE SELECTED
1
2RESERVEO

3
4-

SPARE

5
6-

RESERVED (TO Jl PIN 16)
7

8SPARE
9
SPARE
10
J2/P2

11 +MFM WRITE DATA
-MFM WRITE DATA

12 13
14

GND

15 16 -

+MFM READ DATA
-MFM READ DATA
GND

17
18
19 20 -

Data Signals
1057

RD52

FLAT RIBBON OR TWISTED PAIR MAX 20 FEET
HOST SYSTEM

DISK DRIVE
1RESERVED

2
3-

-HEAD SELECT 22

4
5-

-WRITE GATE

6
7-

-SEEK COMPLETE
8

9-TRACK 0

10
11-

-WRITE FAULT
-HEAD SELECT 2 0

12
1314
15-

RESERVED (TO J2 PIN 7)
16

17-HEAD SELECT 2'

J1/P1

18
19-

-INDEX
20

21-

-READY

22
23 -

-STEP

-DRIVE SELECT 1

2526
27 -

-DRIVE SELECT 2

-DRIVE SELECT 3

28
2930
31 -

-DRIVE SELECT 4

32
33 -

-DIRECTION IN
34
+5VDC

+5V RETURN

+12V RETURN

J3/P3

1
2

FRAME GND

}

+12VDC

DC
GND

m
FRAME GROUND

TWISTED PAIR 120 GA OR LARGER)

Control Signals

1058

J4/P4

RD52

h
f---I
h

CONTROL

/ L Jl

DATA

L-

DRIVE #1

L- J3

CONTROLLER

--,

DATA

--.l

r- J2

DRIVE #2

L-

I
L-

J3
J4

Y
-,

»C

r- J2

DATA

DRIVE #3

L-

--.J

rL- J3
J4

Y
-C
-,

DATA

0L-

r-'

«
z

DRIVE #4

0L-

w
r-

c...:..-.
J4

y
DC, VOLTAGES
FRAME GROUND
'THE LAST OR ONLY DRIVE IN THE CONTROL CABLE STRING MUST HAVE THE TERMINATOR
RESISTOR PACK INSTALLED. ALL OTHER DRIVES MUST HAVE THEIR TERMINATORS REMOVED.

Typical Connection, Four Drives

1059

RD52

A. RD52 SUBSYSTEM,
DESK TOP MODEL
1. FRONT BEZEL
2. COVER
3. CHASSIS
4. REAR BEZEL

B. RD52 SUBSYSTEM,
RACK MOUNT MODULE

RD52 Desk-Top and Rack Mounting Housings

1060

RD52
LED RD52 DRIVE
READY

LED SWITCH
WRITE-PROTECT
RD52 DRIVE

MR·13098

Front Panel, Switches and Indicators

PRIMARY VOLTAGE
SELECT SWITCH

120/240
AC LINE
CIRCUIT B,EAKER

I @

IJ11 O~o:::::::::::o~O I

[J I

J21 O~:::::::::::o~O I

[J31 O~::::::::::::~O

I
~

PR I MARY VO LTAG E
INPUT
MR-13099

Rear Panel
1061

RD52

Removal of Flexible Disk Drive Signal and Power Cable

1062

RD52
PATCH AND FILTER
PANEL ASSEMBLY

1 RODXl CONTROLLER
1 CK-RODX1-KC CABINET KIT
1 RD52 SUBSYSTEM
OR
1 RX5D SUBSYSTEM
1 H9302 RACK MOUNT KIT

EXTERNAL CABLE

CABINET KIT CABLE
{3D" FOR H349 ENCLOSURE)
CK-RODX1-KC

"I
One Subsystem Add-On to a PDP-11/23 PLUS

PATCH AND FILTER
PANEL ASSEMBLY
RD52
OR
RX50
OR
RD5l
SUBSYSTEM
INTERCONNECT
CABLE BC17Y-1J
EXTE RNAL CABLE

CABINET KIT CABLE
{3D" FOR H349 ENCLOSURE)
CK-RODXI-KC

-I

Two Subsystem Add-Ons to H349 Distribution Panel

INBOARD
DRIVES

BULKHEAD

Maximum Expansion Configuration
1063

RK05

RK05 DISK DRIVE SUBSYSTEM

RK05 Disk Drive
The RK05-J disk drive uses a removable disk cartridge and the RK05-F
uses a fixed, dual-density disk cartridge. Both drives are interfaced by the
RKV 11-0 option. The RKV 11-0 is set at address 177400 and vector 220.
Applicable diagnostic programs are found in Appendix A.

Related Documentation
RKV 11-0 Field Maintenance Print Set (MP-00223-00)
RK05-J Field Maintenance Print Set (MP-ORK05-0J)
RK05-F Field Maintenance Print Set (MP-ORK05-0F)
RKVII-D User's Guide (EK-RKV11-0P)
Microcomputer Interfaces Handbook (EB-20 175-20)
RK05 Disk Drive User's Guide (EK-ORK05-0P)
RK05/05J/05F Maintenance Manual (EK-RK5JF-MM)
RK05 Exercisor Maintenance Manual (EK-RK05X-MM)

1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111

RK05 Disk Drive

1064

RK05
Controls and Indicators for the RK05, RK05-J, and RK05-F
Controls and
Indicators

Description

RUN/LOAD
(Rocker Switch)

Placing this switch in the RUN position (provided
that all interlocks are safe):
a.
b.
c.
d.

locks the drive front door
accelerates the disk to operating speed
loads the read/write heads
lights the ROY indicator.

Placing this switch in the LOAD position:
a.
b.
c.
d.

unloads the read/write heads
stops the disk rotation
unlocks the drive front door when the disk has
stopped
lights the LOAD indicator.

CAUTION
Do not switch to the LOAD position during a write operation;
this results in erroneous data being recorded.
WT PROT
(Rocker Switch
Spring-Loaded Off)

Placing this momentary contact switch in the PROT
position lights the WT PROT indicator and prevents
a write operation; it also turns off the FAULT indicator, if that is lit.
Depressing this switch in the WT PROT position a
second time turns off the WT PROT indicator and allows a write operation.

PWR (Indicator)

Lights when operating power is present. Goes off
when operating power is removed.

RDY (Indicator)

Lights when:
a.

the disk is rotating at the correct operating
speed

the heads are loaded

no other conditions are present (all interlocks
safe) to prevent a seek, read, or write operation.

Goes off when the RUN/LOAD switch is set to
LOAD.

1065

RK05
Controls and Indicators for the RK05, RK05-J, and RK05-F (Cont)
Controls and
Indicators

Description

ON CYL (Indicator)

Lights when:
a.

the drive is in the ready condition

a seek or restore operation is not being performed

the read/write heads are positioned and settled.

Goes off during a seek or restore operation.
FAULT (Indicator)

Lights when:
a.

erase or write current is present without a write
gate

the linear positioner transducer lamp is inoperative.

Goes off when the WT PROT switch is pressed, or
when the drive is recycled through a run/load sequence.
WT PROT (Indicator) Lights when:
a.
b.

the WT PROT switch is pressed
the operating system sends a WRITE PROTECT
command.

Goes off when the WT PROT switch is pressed a
second time, or when the drive is recycled through a
run/load sequence.
LOAD (Indicator)

Lights when the read/write heads are fully retracted
and the spindle has stopped rotating.

WT (Indicator)

Lights when a write operation occurs. Goes off when
the write operation terminates.

RD (Indicator)

Lights when a read operation occurs. Goes off when
the read operation terminates.

1066

RK05
Performance Specifications
Storage Medium
Type

Single-disk magnetic cartridge (RKOS, RKOSJ - removable; RKOSF - nonremovable)

Disk Diameter

S.S1 cm (14 inches)

Magnetic Heads
Number

Bit Transfer
Transfer Code
Transfer Rate

Double frequency, NRZ recording
1.44 m bit/s

Electrical Requirements
Voltage
Power
Starting Current

11S/230 Vac @ SO/60 Hz ± .OS Hz
2S0 VA
Power only: 1.8 A
Start spindle: 10 A (for 2 seconds)

Model Designation
RKOS-AA, RKOSJ-AA, RKOSF-AA, RKOSF-FA 9S - 130 Vac @ 60 ± O.S Hz
RKOS-AB, RKOSJ-AB, RKOSF-AB, RKOSF-FB 290 - 260 Vac @ 60 ± O.S Hz
RKOS-BA, RKOSJ-BA, RKOSF-AC, RKOSF-FC 9S - 130 Vac @ SO ± O.S Hz
RKOS-BB, RKOSJ-BB, RKOSF-AD, RKOSF-FD 190 - 260 Vac@ SO ± O.S Hz

Dimensions and Weight
Width:
Depth:
Height:
Weight:

48 cm (19 in)
67 cm (26.S in)
27 cm (10.S in)
SO kg (110 Ib)

1067

RK05
Unit Selection
An RK05 disk drive may be configured to respond to a desired unit designation by selecting the appropriate setting on a rotary switch. The rotary
switch is located on the second module in the card cage. The circuit cards
are located behind the prefilter, and may be accessed by removing the rear
cover panel on the bottom side of the disk drive unit. In the RK05-J, the
rotary switch is on the M7700 module. In the RK05-F it is on the M7680.
M7700 OR M7680

r-r/==~';
/
M7700 or M7680 Placement

Bootstrap Program for RK05
If an RK05 is used in a system that has no hardware bootstrap module, the

disk drive may be booted by entering the fol/owing program manual/y.
@RO/OOOOOO OnOOOO<CR>'
@R1/000000 177404<CR>
@1000/000000 000005<LF>
001002/000000010061<LF>
001004/000000 000006<LF>
001006/000000012761<LF>
001010/000000 177400<LF>
001012/000000000002<LF>
001014/000000012711<LF>
001016/000000000005<LF>
001020/000000105711<LF>
001022/000000 100376<LF>
001024/000000 005007 <CR>
@1000G
• n = 0 for drive 0; 2 for drive 1; and 4 for drive 2.
1068

RK05

o 0 00
DISK DRIVE
UNIT NUMBER
SELECTOR SWITCH

Controller Switches

1069

RL01/RL02

RL01/RL02 5.2/10.4 Mb CARTRIDGE DISK DRIVE UNIT

RL01jRL02 Disk Drive
The RL01 is a 5,000,000 byte disk drive that uses a modified, removable,
5440-style cartridge (RLO 1K-OC). The RL02 is a dual-density version of the
RL01. The RL02 uses an RL02K-OC cartridge. Both the RL01 and RL02 use
the RL V 11 interface module. Up to four drives of either type in any combination can be connected to an RLV11 interface. The RLV11 is normally
configured for a bus address of 77 440X octal with a vector address of 160
octal. For more in-depth information, refer to the RLV11 (M8013j8014)
section. Additional information can be found in the following manuals.
RL01jRL02 Disk Drive Technical Manual (EK-RL012-TM)
RLV11 Technical Description (EK-RLV11-TO)
RLO 1/RL02 Pocket Service Guide (EK-RLO 12-PG)
RL01jRL02 Disk Subsystem User's Guide (EK-RL012-UG)
RLO 1 Illustrated Parts Breakdown (EK-ORLO 1-IP)
RL02 Illustrated Parts Breakdown (EK-ORL02-IP)
RLO 1 Field Maintenance Print Set (MP-00527 -00)
RL02 Field Maintenance Print Set (MP-00698-00)
RL V 11 Field Maintenance Print Set (MP-00635-00)
Microcomputer Interfaces Handbook (EB-20 175-20)

Specifications RL01jRL02
Medium
Type:

Single platter, top-loading cartridge (similar to IBM 5440).
Embedded servo information.

Capacity:

RLO 1K-OC = 5.2 Mb
RL02K-OC = 10.4 Mb

Cylinders:

RL01 = 256
RL02 = 512

Sectors:

Heads:

1070

RL01/RL02

(AI
LOAD
SWITCH AND
INDICATDR
(61
UNIT SELECT
PLUG/READY
LIGHT

(DI
WRITE
PROTECT AND
SWITCH INDICATOR

RL01/RL02 Controls and Indicators

Data Transfer
MFM (Miller coding) recording; 244 ns cell time; 4.1 megabytes/s (4.9
~s/word).

RL01/RL02 Bootstrap
Ensure that the heads are over cylinder 0 and head 0 is selected by releasing the LOAD switch, waiting for the LOAD indicator to light, then depressing the LOAD switch. After the drive is ready, initialize the controller with a
system initialize. Perform a bit status clear. Load the following program into
memory.
LOC

Contents

Comments

10000
10002
10004
10006

012737
000014
174400
000001

Load CSR

Wait

Start the program at 10000 and allow it to run for a few seconds, halt the
program and restart at 00000.

1071

RL01/RL02
RL01/RL02 Controls and Indicators
Switches

Function

Power ON/OFF
Circuit Breaker
(Located in the
rear of the drive)

In the OFF position, ac power is removed from the
drive.

(A) LOAD

This is a PUSH/PUSH alternating action switch.
When depressed, the RL01/RL02 begins a "cycle
up" sequence, provided that:

In the ON position, ac power is supplied to the drive.

•
•
•
•
•
•

the RLO 1/RL02K cartridge is installed
the cartridge cover is in place
the access door is closed
all ac and dc voltages are within spec
the R/W heads are retracted
the brushes are in the "home" position.

When released, the RL01/RL02 will begin a "cycle
down" sequence.
(B) UNIT SELECT
PLUG

This is a cam-operated switch that is activated by inserting a numbered, cammed button. The switch
contacts are binary encoded so that the drive assumes the logical unit number that is printed on the
button.

(D) WRITE PROTECT This is an alternating action PUSH/PUSH switch.
When depressed, the drive assumes a write protect
status (during a write operation). When released,
the drive is no longer write protected.

1072

RL01/RL02
RL01/RL02 Controls and Indicators (Cont)
Indicators

Function

(A) LOAD (Yellow)

Indicates that the drive is ready to have a cartridge
loaded (or unloaded). The LOAD indicator will light
when:
•
•
•

the spindle is stopped
the R/W heads are "home"
the brushes are "home."

(8) READY (White)

When lit, indicates a "drive ready" condition; i.e.,
the heads are loaded and detented.

Indicates when one of the following has occurred.
•
•
•
•
•
•
•

drive select error
seek timeout error (1.5 second)
write current in heads during "sector time"
loss of system clock from RL V 11
write data error (no transitions)
spin error (over speed or 40 sec timeout)
write gate error (attempting to write when not
ready, when write protected, or during sector
time)

(D) WRITE PROTECT Indicates that drive is write protected. That is, write
(Yellow)
operations to the cartridge will be inhibited (and the
FAULT indicator will light).

1073

RX01

RX01 FLOPPY DISK DRIVE

RX01 Floppy Disk Drive
The RXO 1 floppy disk drive is part of the RXV 11 floppy disk system, and is
interfaced by the RXV 11 interface module (M7946). The disk system uses
address 177170 and vector 264 for the first option, and address 177174
and vector 270 for a second option.

[1111111111111

~llllllllli I11I1I ~ 111111111100 I I I IIIIII[
RXO 1 Floppy Disk

Model Designations
RXV11-AA Single Drive System, 115 V/60 Hz
RXV11-AC Single Drive System, 115 V/50 Hz
RXV 11-AD Single Drive System, 230 V/50 Hz
RXV 11-BA Dual Drive System, 115 V/60 Hz
RXV 11-BC Dual Drive System, 115 V /50 Hz
RXV 11-BD Dual Drive System, 230 V /50 Hz

1074

RX01
Related Documentation
RXV11 User's Manual (EK-RXVll-00)
RXO 1/RXB/RX 11 Floppy Disk System Maintenance Manual (EK-RXO 1-MM)
RXVll Field Maintenance Print Set (MP-00024-00)
RXO 1 Field Maintenance Print Set (MP-00296-00)
RX01/RX02 Reference Card (EK-RX01-RC)
Microcomputer Interfaces Handbook (EB-20 175-20)

NOTE
50 Hz versions are available in voltages of 105, 115, 220, and
240 Vac by field-pluggable conversion. Refer to the
RX01/RXB/RX11 Floppy Disk System Maintenance Manual for
complete input power modification details_

AC Power
The RXV 11 floppy disk system is available in the following three ac voltage/model configurations.

Models

Voltage/Frequency

RXV ll-AA, -BA
RXV ll-AC, -BC
RXVll-AD, -BD

100 Vac-132 Vac, 60 Hz
100 Vac-132 Vac, 50 Hz
180 Vac-264 Vac, 50 Hz, in one of two voltage
ranges. The actual voltage range is user-selected by
installing the appropriate power harness during system installation, as follows.
Voltage
Range

Power Harness
PN

180-240
200-264

70-10696-04
70-10696-03

Power Consumption
RXOl

RXV 11 interface (M7946)
Power input (ac)

3 A at 24 V (dual), 75 W;
5 A at 5 V, 25 W
Not more than 1.5 A at 5 Vdc
4Aat 115Vac
2 A at 230 Vac

1075

RX01
Bootstraps for Manual Entry
Full Length Version

Abbreviated Version
(Drive 0 Only)

@1000/000000 12702<LF>
001002/0000001002n7<LF>*
001004/000000 12701 <LF>
001006/000000 177170<LF>
001010/000000 130211<LF>
001012/000000 1776<LF>
001014/000000 112703<LF>
001016/0000007<LF>
001020/00000010100<LF>
001022/000000 10220<LF>
001024/000000402<LF>
001026/000000 12710<LF>
001030/000000 1 <LF>
001032/000000 6203<LF>
001034/000000 103402<LF>
001036/000000 112711<LF>
001040/000000 111 023<LF>
001042/00000032011 <LF>
001044/000000 1776<LF>
001046/000000 100756<LF>
001050/000000 103766<LF>
001052/000000 105711<LF>
001054/000000100771<LF>
001056/0000005000<LF>
001060/000000 2271 O<LF>
001062/000000 240<LF>
001064/000000 1347<LF
001066/000000 122702<LF>
001070/000000 247 <LF>
001072/000000 5500<LF>
001074/0000005007<CR>

@1000/000000 5000<LF>
001002/000000 12701<LF>
001004/000000 177170<LF>
001006/000000105711<LF>
001010/000000 1776<LF>
001012/000000 12711<LF>
001014/0000003<LF>
001016/000000 5711<LF>
001020/000000 1776<LF>
001022/000000 100405<LF>
001024/000000105711<LF>
001026/000000 100004<LF>
001030/000000 116120<LF>
001032/0000002<LF>
001034/000000 770<LF>
001036/0000000<LF>
001040/0000005007<CR>

*n = 4 for unit 0
n = 6 for unit 1
<LF> = Line Feed
<CR> = Carriage Return
Starting address = 1000

1076

RX02

RX02 FLOPPY DISK DRIVE

RX02 Floppy Disk Drive
The RX02 is part of the RXV11-XX floppy disk system. The RXV21-8X options use the RX02 in double-density mode with the RXV21 (M8029) interface module. The RXV21-DX options use the RX02 in single-density mode
with the RXV11 (M7946) interface module.

I!IImBD!lII RX02

Front View of the Floppy Disk System
The density mode of the RX02 is selected by switches on the M7744 controller module. This module is located in the RX02 floppy disk drive. The
following switch settings define the mode of the RX02.

Controller Configuration Switch Settings
(Located on M7744 Module)
Interface

S1-1

RX211 jRXV21
RX8EjRX11jRXV11
RX28

OFF

OFF
OFF

OFF

S1-2

NOTE
The subject of the RX02 as used in a PDP-B system is beyond
the scope of this document.
Detailed configuration and diagnostic information is contained in this manual. Refer to the section covering the applicable interface (M7946 or
M8029).
1077

RX02
Related Documentation
RX02 Floppy Disk System User's Guide (EK-ORX02-UG)
RX01/RX02 Reference Card (EK-RX102-RC)
Microcomputer Interface Handbook (EK-20 175-20)
RX02 Print Set (MP-00629-00)

Module Designations
RXV21

-DA
-DC
-DD

M7946
M7946
M7946

RX02-DA
RX02-DC
RX02-DD

115 V, 60 Hz
115 V, 50 Hz
230 V, 50 Hz

-BA
-BC
-BD

M8029
M8024
M8027

RX02-BA
RX02-BC
RX02-BD

115 V, 60 Hz
115 V, 50 Hz
230 V, 50 Hz

Power Requirements
The RX02 is designed to use either a 60 Hz Vac or a 50 Hz power source.
The 60 Hz version will operate from 90 Vac-128 Vac, without modifications,
and will use less than 4 A operating. The 50 Hz version will operate within
four voltage ratings and will require field verification/modification to ensure
that the correct voltage option is selected. The voltage ranges of 90
Vac-120 Vac and 184 Vac-240 Vac will use less than 4 A operating. The
voltage ranges of 100 Vac-128 Vac and 200 Vac-256 Vac will use less
than 2 A. Both versions of the RX02 will be required to receive the input
power from an ac source (e.g., 861 power control) that is controlled by the
system's power switch.

Input Power Modification Requirements
The 60 Hz version of the RX02 uses the H771-A power supply and will operate on 90 Vac-128 Vac, without modification. To convert to operate on a
50 Hz power source in the field, the H771-A supply must be replaced with
an H771-C or -D and the drive motor belt and drive motor pulley must be
replaced. The H771-C operates on a 90 Vac-120 Vac or 100 Vac-128 Vac
power source. The H771-D operates on a 184 Vac-240 Vac or 200
Vac-256 Vac power source. To convert the H771-C to the higher voltage
ranges or the H771-D to the lower voltage ranges, the power harness ·and
circuit breaker must be changed. The appropriate jumper and circuit breaker are shown in the following figure.

1078

RX02
JUMPER P1

POWER PLUGS

SHIPPING
RESTRAINT (REDI
VOLTAGE (VACI

JUMPER

CIRCUIT BREAKER

90-120
100·128
184·240
200·256

70-10696·02
70-10696·01
70-10696·04
70-10696·03

1.75 A, J2.12301·00
1.75 A, 12·12301·00

3.5 A, J2.12301·01
3.5 A, J2.1230J.01

RX02 (Rear View)
Bootstrap for Manual Entry (OOT)
RX02/RXV11 (M7946)
@1000/XXXXXX
1002/XXXXXX
1004/XXXXXX
1006/XXXXXX
1010/XXXXXX
1012/XXXXXX
1014/XXXXXX
1016/XXXXXX
1020/XXXXXX
1022/XXXXXX
1024/XXXXXX
1026/XXXXXX
1030/XXXXXX
1032/XXXXXX
1034/XXXXXX
1036/XXXXXX
1040/XXXXXX
1042/XXXXXX
@1000G

SOOO<LF>
12701<LF>
177170<LF>
10S711<LF>
1776<LF>
12711<LF>
3<LF>
S711<LF>
1776<LF>
10040S<LF>
10S711<LF>
1000004<LF>
116120<LF>
2<LF>
770<LF>
O<LF>
SOOO<LF>
110<CR>

<LF> = Line Feed.
<CR> = Carriage Return.
XXXXXX = Original contents of location opened
1079

RX02
RX02/RXV21 (M8029)
@2000/XXXXXX
2002/XXXXXX
2004/XXXXXX
2006/XXXXXX
2010/XXXXXX
2012/XXXXXX
2014/XXXXXX
2016/XXXXXX
2020/XXXXXX
2022/XXXXXX
2024/XXXXXX
2026/XXXXXX
2030/XXXXXX
2032/XXXXXX
2034/XXXXXX
2036/XXXXXX
2040/XXXXXX
2042/XXXXXX
2044/XXXXXX
2046/XXXXXX
2050/XXXXXX
2052/XXXXXX
2054/XXXXXX
2056/XXXXXX
2060/XXXXXX
2062/XXXXXX
2064/XXXXXX
2066/XXXXXX
2070/XXXXXX
2072/XXXXXX
2074/XXXXXX
2076/XXXXXX
2100/XXXXXX
2102/XXXXXX
2104/XXXXXX
2106/XXXXXX
2110/XXXXXX
2112/XXXXXX
2114/XXXXXX
2116/XXXXXX
2120/XXXXXX
2122/XXXXXX
2124/XXXXXX

12701<LF>
177170<LF>
12700<LF>
100240<LF>
5002<LF>
12705<LF>
200<LF>
12704<LF>
401<LF>
12703<LF>
177172<LF>
30011<LF>
1776<LF>
100436<LF>
12711<LF>
407<LF>
30011<LF>
1776<LF>
100431 <LF>
110413<LF>
304<LF>
30011<LF>
1776<LF>
110413<LF>
304<LF>
30011<LF>
1776<LF>
1100420<LF>
12711<LF>
403<LF>
30011<LF>
1776<LF>
100413<LF>
10513<LF>
30011<LF>
1776<LF>
100407<LF>
10213<LF>
6052<LF>
60502<LF>
122424<LF>
120427<LF>
7<LF>

1080

RX02
RX02/RXV21 (M8029) (Cont)
2126/XXXXXX
2130/XXXXXX
2132/XXXXXX
2134/XXXXXX
@2000G

3737<LF>
5000<LF>
5007<LF>
O<CR>

1081

RX50

RX50 FLOPPY DISK DRIVE SUBSYSTEM

GENERAL
The RX50 RID (rack or desk mount) uses an RQDX1 controller interface which
controls up to four logical units. The RX50 uses two logical units and the RD51
uses one logical unit. With a system using an RQDX1 controller, the maximum
configuration that can be used is two RX50 disk drive units or one RX50 and one
RD50 disk unit, expandable by one RD51 drive unit by using an RQDX1-E bus
extender option.
RX50 Flexible Disk Drives - 120 Vac or 240 Vac Voltage Selectable

Power Supply
+12 Av
.1 A
Minimum
Maximum 1.3 A

+5 V
.3 A
S.O A

+12 Battery voltage

.8 A
.S A

.12 A
.12 A
.12 A

OA
.12 A

RXSO Voltage
Maximum 3 A
Minimum 1.3 A
Standby 0.1 A

.S A

Capacity (diskette)
800K bytes
Related Documentation

MICRO/PDP-tt System, Technical Manual (EK-OLCPS-TM)
MICRO/PDP-tt System, Owner's Manual (EK-OLCP5-0M)
MICRO/PDP-tt System, Unpacking and Installation Guide (EK-OLCP5-IN)
MICRO/PDP-tt System Option Manual (EK-OLCP5-0D-001)
RQDXt Controller Module User's Guide (EK-RQDX1-UG)
(includes RQDX1-E Bus Extender)
H9302 Rack Mounting Kit Installation Manual (EK-LEP03-IN)
Compatibility
RXSO RID units are used as add-ons in the PDP-11/23 PLUS, MICRO/PDP-11,
MICRO VAX I, and other Q-BUS hosts.

1082

RX50
Front Panel Controls and Indicators
AC power ON/OFF switch - connects ac power to the internal power supply.
TOP THREE LEDs

LIT

1 st (yellow) LED

When top drive is write protected

2nd (green) LED

+5 Vdc is being supplied to the drive

3rd (yellow) LED

When bottom drive is write protected

NOTE
Never open a disk drive door when either drive's light is on (active
drive).
LED WRITE· PROTECT
DRIVE 2 (BODOM)

LED +5 V
LED WRITE· PROTECT
DRIVE 1 (TOP)

AC POWER

ACTIVE DRIVE
LIGHT 1

ACTIVE DRIVE
LI GHT 2
-:---;t+-.-::::

DRIVE 2 DOOR

DRIVE 1 DOOR
MR12200

Front Panel, Switches and Indicators

1083

RX50
PRIMARY VOLTAGE
SELECT SWITCH

120/240
AC LINE
CIRCUIT B\EAKER

ITdJ IJ11

I @
O~o:::::::oo::::~ 0

IJ2[ O~::::::::::::}/O I

1: I

J31 Oif,;,:::::::::::o~O

'-'

'-T

PRIMARY VOLTAGE
INPUT
MR-13099

RX50 Rear View

RXSO Subsystem Dimensions and Weights
Dimensions
Desk top configuration and
rack mount configuration

Approximately 12 inches long 9
inches wide, 5-1/2 inches high

Weights
Desk top configuration and
rack mount configuration

Approximately 14 pounds

The hardware requirements for the BA23 enclosure are:
1
1
1

RODX1 Controller
CK-RODX1-KA cabinet kit
RX50-D subsystem

or
RX50-R subsystem
H9302 rack adapter kit.

1084

RX50
The hardware requirements for the H349 enclosure are:
RODX1 controller
CK-RODX1-KC cabinet kit
RX50-D subsystem
or
RX50-R subsystem
H9302 rack adapter kit.
The figure below illustrates how to add two subsystems, RD51 and RX50, to a
BA23 or an H349 enclosure.

PATCH AND FI LTER
PANEL ASSEMBLY

1 RQDX1 CONTROLLER
1 CK·RQDX1-KC CABINET KIT
1 RD52 SUBSYSTEM
OR
1 RX50 SUBSYSTEM
1 H9302 RACK MOUNT KIT

EXTERNAL CABLE

CABINET KIT CABLE
(30" FOR H349 ENCLOSURE)
CK·RQOX1·KC

·1
Single Expansion Configuration

PATCH AND FILTER
PANEL ASSEMBLY

EXTERNAL CABLE

CABINET KIT CABLE
(30" FOR H349 ENCLOSURE)
CK·RQDXI·KC

Double Expansion Configuration
1085

RX50
The hardware requirements for the BA23 enclosure are:
RQOX1 controller
CK-RQDX1-KA cabinet kit.
The two subsystems can be either:
2
1

RDS1-D subsystems or 2 RDS1-R with 1 H9302 adapter kit or
RDS1-D or -R with 1 H9302
RXSO-D or -R with H9302
BC17Y -1 J subsystem interconnection cable.

The hardware requirements for the H349 enclosure are:
RQDX1 controller
CK-RQDZ1-KC cabinet kit
and the two subsystems can be either:
2

RDS1-D subsystems or 2 RDS1-R with 1 H9302 rack adapter kit or:
RDS1-D or 1 RD51-R with 1 H9302 rack adapter kit
RXSO-D or RX50-R
BC17Y-1J subsystem interconnection cable.

The hardware requirements are:
RQDX1-E RQDX1 extender
CK-RQDXE-KA cabinet kit RD/RX controller EXT BA23
RDS1-D
or
RDS1-R with 1 H302 rack adapter kit.

1086

RX50
SYSTEM AND EXTERNAL SUBSYSTEM INTERCONNECT
System enclosures such as the BA23 and H349 have a patch and filter panel
assembly, attached to the rear of the unit. This panel has an unused area that can
be used for system expansion. The internal system cabling for the external subsystem is contained in the cabinet kits and will be connected to a proper connector
on the internal side of the patch panel. The subsystem user can simply connect to
the external connector of the port used.
J1, J2 and J3 Pin Numbers and Signal Names
Connectors J1, J2 and J3 have the same signal names and pin numbering.

Pin Numbers

Signal Names

Pin Numbers

Signal Names

J1-01
J1-34
J1-18
J1-02
J1-35
J1-19
J1-03
J1-36
J1-20
J1-04
J1-37
J1-21
J1-05
J1-38
J1-22
J1-06
J1-39
J1-23
J1-07
J1-40
J1-24
J1-08
J1-41

MEMWRTDT1 (H)
MEMWRTDT1 (L)
GROUND
HEAD SET 2 (L)
GROUND
SEEKOPLT
RD1 RDY (H)
WPT FAULT (L)
GROUND
READ SEL 1 (L)
RXOWPTLED (L)
RDO RDY (H)
RX1 WPTLED (L)
DRVSLOACK (L)
MEMRDDATO (H)
MFMRDDATO (L)
MFMWRTDTO (H)
MFMWRTDTO (L)
MFMRDDAT1 (H)
MFMRDDAT1 (L)
GROUND
RFDUCWRTI (L)
RDOWRTPRO (L)

J1-25
J1-09
J1-42
J1-26
J1-10
J1-43
J1-27
J1-11
J1-44
J1-28
J1-12
J1-45
J1-29
J1-13
J.1-46
J1-30
J1-14
J1-47
J1-31
J1-15
J1-48
J1-32
J1-16
J1-49
J1-33
J1-17
J1-50

DRV SEL 4 (L)
GROUND
INDEX (L)
RD1WRTPRO (L)
DRV SEL 1 (L)
DRV SEL 2 (L)
DRV SEL 3 (L)
RX2WPTLED (L)
RXMOTORON (L)
GROUND
DIRECTION (L)
GROUND
STEP (L)
GROUND
RXWRTDATA (L)
GROUND
WRT GATE (L)
GROUND
TRACK 00 (L)
RX3WPTLED (L)
DRVSL 1ACK (L)
GROUND
READ DATA (L)
GROUND
HEAD SEL 0 (L)
GROUND
READY (L)

1087

RX50
Power Supply Connectors
AC Power Input Connector
Pin No.

Signal

1
2
3

Ground
AC phase
AC neutral

DC Power Output Connector
Pin No.

Signal

+5 V
+5 V
+5 V

3
4
5
6
7
8
9

10
11
12

Return
Return
Return
Return
12 VA
12 VA
12 VB
No pin
No connection

Logical Unit Number Selection
The logical unit number (LUN) selection is set by jumpers on the RQDX1 controller
module. These jumpers are set to the lowest LUN logical unit number assigned to
any RD51 or RX50 drive subsystem that is controlled by the RQDX1. The RQDX1
module automatically senses the logical unit configuration during initialization of
the system to determine how many of the four possible units are actually present.

1088

RX50
The LUN jumper format allows only one jumper to be installed at a time, and each
individual jumper specifies a group of 4 logical units as follows.

LUN Jumper

LUNs Specified

No jumper installed
1

0-3
4-7
8-11
12-15
16-19
20-23
24-27
28-31
32-35

2
3
4
5
6
7
8

Within the context of RQDX1 configurations as shown below, if the number 4
jumper is connected and configuration number 2 is being used, then:
16 = unit 0
17 = unit 1
18 = unit 2
19 = unit 3

Configuration
Number

External Subsystem
Disk Drives

Logical Unit Numbers
for Disk Drive

One RD51, one RX50

Unit 0 = RD51
Units 1, 2 = RX50

Two RX50s

Units 0, 1 = RX50
Units 2, 3 = RX50

Two RD51 s, one RX50

Unit 0 = RD51
Unit 1 = RD51
Units 2, 3 = RX50

Two RD51s

Unit 0 = RD51
Unit 1 = RD51

One RX50

Units 0, 1 = RX50

One RD51

Unit 0 = RD51

1089

RX50
System Controller Options
Description

Model

RQDX1

RX50 and/or RD51 MSCP controller.

Controller/Interface,
MSCP Q-BUS

One controller handles up to four logical units. No more than two RX50s per
controller. One RX50L is equal to two
LUNs.
RQDX1-E

Bus EXTENDER w/cable

Enables external drive (RX50, RD51)
to connect to MICRO/PDP-11 internal
controller-to-drive bus. Allows either
one external RX50 or one external
RD51 to be connected to the
MICRO/PDP-11 controller depending
on the RQDX1 configuration
guidelines.

CK-RQDX1-KA Cabinet kit for installing the RQDX1 controller in a BA23 enclosure
(MICRO/PDP-11 ).
CK-RQDX1-KC Cabinet kit for installiing the RQDX1 controller with the H349 I/O
panel (PDP-11 /23 PLUS).
CK-RQDXE-KA Cabinet kit for installing the RQDX1-E extender in a BA23 enclosure (MICRO/PDP-11).
BQ01-C

Country kit, Doc, for RQDX1 Controller and Extender.

RQ01-D

Country kit, Doc, Labels, Diagnostic for RX50-R, -D.

BQ01-E

Country kit, Doc, Labels for RD51-R, -D.

1090

RX50

n
GROOVE FOR
CHANNEL GUIDE

BASIC CHASSIS
FRONT VIEW

~l====;j!;==~21rr====;G=~..i====~~_QUICK RELEASE TAB
A. SUBSYSTEM MOUNTING ARRANGEMENT.
UNDERSIDE OF BASIC CHASSIS.
CATCH FOR
QUICK RELEASE

~~=C=H=A=N=N=E\=L=G~U~'D~nE~D'====j=P=R~'N=G====~(

WALL OF EXTRUDED COVER

(DESK TOP) FRONT VIEW

B. MATING MOUNTING ARRANGEMENT.
ON FLOOR OF EXTRUDED HOUSING.

RACK MOUNT HOUSING
FRONT VIEW

C. MATING MOUNTING ARRANGEMENTS (21ON FLOOR OF RACK MOUNTING HOUSING.

Mounting Channel and Quick Release Latch

1091

RX50

A. RX5().R RACK MOUNTED MODEL

1. FRONT BEZEL
2. COVER
3. CHASSIS
4. REAR BEZEL

B. RX5().D DESK TOP MODE L

RX50 Desk-Top and Rack Mounting Housing

1092

RX50

Opening the Drive 1 Door

WRITE-PROTECT
NOTCH TO LEFT

Inserting a Flexible Disk in Drive 1
1093

RX50

Opening the Dr'Ive 2 Door

Inserting a Flexible 0'ISk In
' Drive 2

1094

RX50

Removal of Flexible Disk Drive Signal and Power Cable

1095

RX50

DRVll~J

DZVll
DRVll~J

(SYNC LINE INTERFACE)

PARALLEL
LINE INTERFACE

"'EJ~t nnf'"'fur'"

"'"

CDNDOLE

0 ======= ~:~ -------

DZVll

H349 Distribution Cable

1096

RX50
REMOVABLE
INSERT

50-PIN CONNECTOR
EXPANSION SLOTS

BA23 Patch and Filter Panel Assembly

PATCH AND FILTER
PANEL ASSEMBLY

1 RODX1 CONTROLLER
1 CK·RQDX1·KC CABINET KIT
1 RXSO SUBSYSTEM
OR
1 RX50 SUBSYSTEM
1 H9302 RACK MOUNT KIT

EXTERNAL CABLE

01 - - - - -

""1

~;~~ ----·~I

One Subsystem Add-On to a PDP-11/23 PLUS

1097

TU58

TU58 TAPE CASSETTE UNIT

GENERAL
The TU58 DECtape II is a random access, fixed length block, mass storage tape
unit. Tape cartridges are DIGITAL's preformatted reel-to-reel packages containing
42.7m (140 tt) long by 3.91 mm (0.150 in) wide tape. The TU58 processor consists
of an 8095 processor, supported by firmware in a 2Kb, read only memory (ROM).
Power Consumption
Board plus 1 and 2 drives
11 W typical, drive running
+5 V ± 5% @ 0.75 A (max.)
+12 V +10, -5% @ 1.2 A, peak
0.6 A average running
0.1 A idle
Rackmount
90-128 Vac 180-256 Vac
47-63 Hz, 35 W (max.)

1098

TU58

Installing the Bezel

1099

TUS8
Related Documentation
TUS8 DECtape II User's Guide (EK-OTU58-UG)
TUS8 DECtape II Pocket Service Guide (EK-OTU58-PS)
TUS8 DECtape II Technical Manual (EK-OTU58-TM)
TUS8DECtape II Illustrated Parts IPB (EK cOTU58-IP)
Field Maintenance Print Set (MP00747-CA)
Field Maintenance Print Set (MP01014-EA)
Field Maintenance Print Set (MP01013-VA)
Field Maintenance Print Set (MP01063-DB)
Model Distinctions
CA Rackmount
Large chassis
Two drives
Serial interface controller board
Switch selectable 120/240 Vac
Detachable line cord
2 cartridges
Boot ROM for MR11
Two I/O cables (BC17 A/BC178-18)
Diagnostic kit (ZJ278-RG)

CABLE SHIELD
GROUND SCREW

o ~ 0

110/220 V SWITCH

INTERFACE
CABLE
CONNECTOR

FUSE POST

~r (00 [I) I~ LINE CORD RECEPTACLE

TU58-CA Rear Panel

1100

TU58
DA Rackmount
Tabletop chassis
TU58-CA features with additional accessory assembly hardware kit (7016753-00)

INTERFACE CABLE
CONNECTOR

CABLE SHIELD
GROUND SCREW

000

POWER
SWITCH

LINE CORD
RECEPTICAL

TU58-DA Rear Panel

EA Tabletop
Two drives
Serial interface controller board
EB Tabletop
Two orives
Serial interface controller board
Two I/O cables (BC17A-18/ BC17B-18)
Boot ROM for MR11-EA
Accessory assembly hardware kit (70-16753-00)
Field Maintenance Print Set (MP01014)
VA Tabletop
Two drives
Serial interface controller
DC Power cable (70-17569-00)
I/O interface cable (70-17568-1 F)
Two cartridges
MXV11-A2 boot ROM
Field Maintenance Print Set (MP01013)
Accessory assembly hardware kit (70-16753-01)

1101

TU58
BAll-VA OR
SBll BOX

DC
POWER

'4 MOUNTING BRACKETS
AND 10-32 X 1/2 INCH
SCREWS FOR MOUNTING
TOBAll-VAORTO
HANG MOUNT

i :- - c;E ;;T-:;;: B-;A;;E~S~TI:;l
I

¥_._D:':

__.1.._1-,

I
I

10-32 x 1/2 INCH SCREWS
FOR SOLID MOUNTING

HARDWARE KIT

USE RUBBER FEET
WITH 10-32 X 1/2 INCH
SCREWS FOR TABLE
TOP MOUNTING

I
I

P~ 7~6:3~ _ .J

SUPPLIED WITH BAll-VA
AND SBll UNITS

'TO ATTACH BRACKETS TO BAll-VA OR SB11,
MOUNT BRACKETS TO BA11-VA ISBll) FIRST_

Mounting Choices for the TU58-VA

SBll OR
CPU SLOT
KDll-HA
/
.-/
/' A

SERIAL LINE
UNIT ISLU)
GROUND
SCREW

MXV11-AC
10REQUIV--ALENT)

_OPTION
SLOT3
OPTION
SLOT 4

I/O
INTERFACE
GROUND WIRE

TU5B-VA

Interfacing the TU58-VA

1102

rUS8
Accessories
TU58-DB
Rackmount kit for tabletop versions
TU58-EC
Accessory kit with detachable line cord for hardware kit (70-16753-00)
User's guide
Field Maintenance Print Set (MP01014)
TU58-ED
Accessory kit with 120V/240V detachable line cord
Fuse for 230 Vac
Two cartridges
Two I/O cables (70-BC17A-18/BC178-18)
Boot ROM for MR11-EA
Accessory assembly hardware kit (70-16753-00)
User guide
Field Maintenance Print Set (MP01014)
TU58-VB
Accessory kit with dc power cable (70-17569-1 C)
I/O cable (70-177568-1 F)
Two cartridges
MXV11-A2 boot ROM
User's Guide
Field Maintenance Print Set (MP01013)
Configuration Guide

1103

TU58
Serial Interface Standards
To interface with the TU58, options with their appropriate cables are listed below.
In accordance with RS422 (balanced) and RS423 (unbalanced) signal standards,
the TU58 is compatible with devices complying with RS232-C.
NOTE
BC22D-10 replaces BC17A-18 and BC17B-18. The new cable has an
improved shield connection to comply with FCC regulations.
DL11 or
DLV11

5.4 m (18 ft) 10 to 40 pin connector = BC17 A-18

DLV11-J
or
MXV11

5.4 m (18 ft) 10 to 10 pin connector = BC178-18

EIA

1.5 m (5 ft) 10 pin to DB25S female = BC20N-05
(null modem cable)

5.4 m (50 ft) 10 to 10 pin connector = BC20M-50

1.5 m (5 ft) 10 pin to DB25P male = BC21 B-05
(Modem cable)

TU58/PDP-11 Toggle-in Boot
This boots drive 0 only.
1000/012701
1002/176500
1004/012701
1006/176504
1010/010100
1012/005212
1014/105712
1016/100376
1020/006300
1022/001005

1024/005012
1026/012700
1030/000004
1032/005761
1034/000002
1036/042700
1040/000020
1042/010062
1044/000002
1046/001362

1050/005003
1052/105711
1054/100376
1056/116123
1060/000002
1062/022703
1064/001000
1066/101371
1070/005007

1104

APPENDIX A
DIAGNOSTIC MEDIA AVAILABILITY
Diagnostic
and DEC/X11
File Names
Notes

Diagnostic and
DEC/X11 Module Titles

M4002-XX KWVll-C

VKWA??BI?

KWVll-A Diagnostic

M7264-XX KDll-FI
KDll-HI
KDll-HW
(LSI-ll)

VKAA??BI?

LSI-ll Basic Instruction Test

VKAB??BI?

LSI-ll EIS Instruction Set Test

Module
Number

Option
Name

17,18
19,20,
21

VKAC??BI?

LSI-ll FIS Instruction Set Test

VKAD??BI?

LSI-ll Traps Test

VKAH??BI?

LSI-ll 4K System Exerciser

VKAI??BI?

LSI-ll DIS Move & String Test

VKAJ??BI?

LSI-ll DIS Decimal Instructions

VKAL??BI?

LSI-ll Trap Test (30K + FIS)

XCPA??OBJ

DEC/X11 Processor Test Module

XCPB??OBJ

DEC/X11 EIS Exerciser Module

0
1

0
2

R
K
0
5

AC-8222C-MC
AK-8225C-MC

19 20

AC-8186C-MC
AK-8188C-MC
AC-8190A-MC
AK-8192A-MC
AC-8194C-MC
AK-8197C-MC
AC-8198C-MC
AK-8-IC-MC
AC-8210A-MC
AK-8212A-MC
AC-8214A-MC
AK-8217A-MC
AC-8218A-MC
AK-8221A-MC
AC-F012A-MC
AK-F014A-MC
AC-E664G-MC
AK-E665G-MC
EC-E667 J-MC
AK-E668J-MC

19 20

Listing
and
Paper Tape
PNs

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

0
2

Module
Number

Option
Name

Diagnostic
and DEC/X11
File Names
Notes

M7269

RKV11-D

ZRKH??BI?

7,8

RK11 IRK05 Performance Exerciser

ZRKI??BI?

RK 11 Utility Package

ZRKJ??BI?

RK 11 Basic Logic Test No. 1

ZRKK??BI?

7,9

RK11 Basic Logic Test NO.2

ZRKL??BI?

7,10

RK11 IRK05 Dynamic Test

XRKA??OBJ

DEC/X11 RK11 Exerciser Module

Diagnostic and
DEC/X11 Module Titles

R
L
0

Listing
and
Paper Tape
PNs

R
X
0
1

R
X
0

0
5

R
L
0
1

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-9232G-MC
AK-9235G-MC
AC-9236F-MC
AC-9239F-MC
AC-9240E-MC
AK-9243E-MC
AC-9244F-MC
AK-9247F-M1
AC-9248E-MC
AK-9251E-MC
AC-E676G-MC
AK-E677G-MC

19 20

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8186C-MC
AK-8188C-MC
AC-8190A-MC
AK-8192A-MC
AC-8194C-MC
AK-8197C-M1
AC-8198C-MC
AK-8201C-MC
AC-8210A-MC
AK-8212A-MC
AC-E664G-MC
AK-E665G-MC
AC-E667 J-MC
AK-E668J-MC

19 20

113

19 20

M7270

KD11-HA

VKAA??BI?

LSI-11 Basic Instruction Test

VKAB??BI?

LSI-11 EIS Instruction Set Test

VKAC??BI?

LSI-11 FIS Instruction Set Test

VKAD??BI?

LSI-11 Traps Test

VKAH??BI?

LSI-11 4K System Exerciser

XCPA??OBJ

DEC/X11 Processor Test Module

XCPB??OBJ

DEC I X 11 EIS Exerciser Module

Module
Number

Option
Name

Diagnostic
and DEC/X11
File Names
Notes

M7940

DLV11

VKAE??BI?

11a,12 DLV11 Test

XDLA??OBJ

11a

DEC/X11 DL 11 Exerciser Module

VKAF??BI?

DRV11 Test

XDRA??OBJ

DEC/X11 DR11-A Exerciser Module

M7941

....

o-..j

DRV11

Diagnostic and
DEC/X11 Module Titles

M7942

MRV11-AA

M7944

MSV11-B

ZKMA??BI?

MOS / Core 0-124K Exerciser

ZQMC??BI?

0-124K Memory Exerciser (16K)

ZRXA??BI?

7,14

RX11 System Reliability TEST

ZRXB??BI?

RX11 Interface Diagnostic

XRXA??OBJ

DEC/X11 RX01 Exerciser Module

M7946

M7948

RXV11

DRV11-P

listing
and
Paper Tape
PNs

0
2

19 20

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8202B-MC
AK-8205B-MC
AC-E709J-MC
AK-E710J-MC

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8206D-MC
AK-8208D-MC
AC-E854D-MC
AK-E855D-MC

19 20

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048F-MC

19 20

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-9334E-MC
AK-9337E-MC
AC-9339F-MC
AK-9343F-MC
AC-E736E-MC
AK-E737E-MC

19 20

----

- -

Module
Number

Option
Name

Diagnostic
and DEC/X11
Notes
File Names

M7949

LAV11

ZLAE??BI?

LA 180 Printer Diagnostic

XLPA??OBJ

DEC/X11 LP11 Exerciser Module

M7950

DRV11-B

VDRA??BI?

13,15

Diagnostic and
DEC/X11 Module Titles

DRV11-B DMA Interface Diagnostic
DRV 11-B Interprocessor Exerciser

VDRB??BI
XDRF??OBJ

DEC/X11 DRV11-B Exerciser Module

ZDUQ??BI?

DUV11 Off-Line Logic Tests

ZDUR??BI?

DUV 11 Off-Line Receiver Tests

ZDUS??BI?

DUV 11 Off-Line Receiver Timing

ZDUT??BI?

DUV 11 Off-Line Transmitter Tests

ZDUU??BI?

DUV 11 Off-Line Timing & Interrupt

ZDUV??BI?

DUV11 Off-Line Combined Tests

Listing
and
Paper Tape
PNs

R
X

R
K

R
L

0
2

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8906B-MC
AK-8908B-MC
AC-E670F-MC
AK-E671 F-MC

19 20

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8178A-MC
AK-8180A-MC
AC-8182A-MC
AK-8184A-MC
AC-E739C-MC
AK-E740C-MC

19 20

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary pT)
(Listing)
(Binary PT)
(Listing)
(Binary pT)
(Listing)
(Binary PT)

AC-8704C-MC
AK-8707C-MC
AC-8708B-MC
AK-8711B-MC
AC-8712B-MC
AK-8715B-MC
AC-8716B-MC
AK-8719B-MC
AC-8720B-MC
AK-8723B-MC
AC-8724B-MC
AK-8727B-MC
AC-E7181-MC
AK-E7191-MC

19 20

M7951

DUV11-DA

XDUA??OBJ

DEC/X11 DU11 Exerciser Module

Module
Number

Option
Name

Diagnostic
and DEC/X11
File Names
Notes

M7952

KWV11-A

VKWA??BI?

17,18
19,20,
21

XKWE??OBJ

M7954

IBV11-A

M7957

DZV11

19 2 o

AC-E920B-MC
AK-E921B-MC

19 2o

R
X

0
1

(Binary pT)

AC-8222CMCM
AK-8225C-MC

DEC/X11 KWV11-K Exerciser Module

(Listing)
(Binary pT)

Diagnostic and
DEC/X11 Module Titles
KWV11-A Diagnostic

(Listing)

R
L
0

22,23,
24

IBV11-A Diagnostic

(Listing)
(Binary PT)

AC-A880A-MC
AK-A882A-MC

19 2

VIBB??BI?

22,23,
24

IBV11-A (30K) Diagnostic

(Listing)
(Binary PT)

AC-F015A-MC
AK-F017A-M1

19 2

XIBA??OBJ

IBV 11-A Exerciser Module

(Listing)
(Binary PT)

AC-E914D-MC
AK-E915D-MC

19 2

ZKMA??BI?

MOS / Core 0-124K Exerciser

19 2

0-124K Memory Exerciser (16K)

19 2

VDZA??BI?

26,27

DZV 11 4 Line Asynch MUX 1 OF 2

19 2

VDZB??BI?

26,27

DZV 11 4 Line Asynch MUX 2 OF 2

19 2

VDZC??BI?

26,27

DZV11 Cable and Echo Test

AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048F-MC
AC-A877 A-MC
AK-A879A-MC
AC-A938A-MC
AK-A940A-MC
AC-A941 A-MC
AK-A943A-MC

ZQMC??BI?

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

19 2

MSV11-C

R
L
0
1

R
X

VIBA??BI?

M7955

0
2

R
K
0
5

Listing
and
Paper Tape
PNs

Module
Number

M8012

M8013/
M8014

....
~

Option
Name

BDVll-AA

RLVll

Diagnostic
and DEC/X11
Notes
File Names

Diagnostic and
DEC/X11 Module Titles

VDZD??BI?

DZV 11 Overlay for ITEP

XDZB??OBJ

DEC/Xll DZVll Exerciser Module

VM8A??BI?

28,29,
30

BDV ll-AA Diagnostic

XBMD??OBJ

DEC / X 11 LSI-ll BDV 11 Exerciser

VRLA??BI?

RLVll RLOl Diskless Test

ZRLG??BI?

7,31

RL 11 /RLVll Controller Test 1

ZRLH??BI?

7,32,
33
7,34,
35
7,36

RL 11/ RLV 11 Controller Test 2

ZRLI??BI?
ZRLJ??BI?
ZRLK??BI?
ZRLL??.BI?
ZRLM??BI?

7,35,
37
7,35
7,35,
38

RLOl /02 Drive Test 1
RLOl /02 Drive Test 2
RLOl /02 Performance Exerciser
RLOl /02 Drive Compatibility Test
RLOl /02 Bad Sector File Tool

Listing
and
Paper Tape
PNs
(Listing)
(Binary PT)
(Listing)
(Binary pT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-A935A-MC
AK-A937A-MC
AC-E911C-MC
AK-E912C-MC
AC-B061 C-MC
AK-B063C-MC
AC-F060C-MC
AK-F061C-MC
AC-Bl07B-MC
AK-Bl09B-MC
AC-FlllB-MC
AK-Fl08B-MC
AC-F 115B-MC
AK-Fl12B-MC
AC-F 119C-MC
AK-Fl16C-MC
AC-F 123B-MC
AK-F120B-MC
AC-F 127B-MC
AK-F124B-MC
AC-F131B-MC
AK-F128B-MC
AC-F 135B-MC
AK-F132B-MC

If!

0
2

19 20

113

19 20

113

19 20

Module
Number

Option
Name

R
X
0

K
0

R
L
0
1

(Listing)
(Binary PT)

AC-F843A-MC
AK-F844-MC

19 20

(Listing)
(Binary PT)
(Listing)
KPV 11-A Diagnostic
(Binary PT)
DLV11-E Off-Line Test
(Listing)
(Binary PT)
DEC/X11 DL 11 Exerciser Module
(Listing)
(Binary PT)
(Listing)
KUV 11-AA (LSI WCS) Diagnostic
(Binary PT)
DEC/X11 KUV11-AA Exerciser Module (Listing)
(Binary PT)
DPV11 Functional Diagnostic
DPV11 Module

AC-E965D-MC
AK-E966D-MC
AC-A883A-MC
AK-A885A-MC
AC-B150B-MC
AK-B152B-MC
AC-E709J-MC
AK -E7 10J-MC
AC-E102A-MC
AK-E104A-MC
AC-E992B-MC
AK-E993B-MC
AC-S039?-M?

19 20

LSI-11 UVPROM-RAM (MRV11-BA) Test (Listing)
(Binary PT)
(Listing)
MOS 1Core 0-124K Exerciser
(Binary PT)
0-124 K Memory Exerciser (16K)
(Listing)
(Binary PT)

AC-B153A-MC
AK-B155A-MC
AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048F-MC

19 20

ZRLN??BI?

7,39,
40

RL01 102 Drive Test 3

XRLA??OBJ

KPV11-X

VKPA??BI?

M8017

DLV11-E

VDVA??BI?

41,42,
43
11b

XDLA??OBJ

11b

VKUA??BI?

XKUA??OBJ

KUV11-AA

R
X
0
1

Diagnostic and
DEC/X11 Module Titles

M8016

M8018

Listing
and
Paper Tape
PNs

Diagnostic
and DEC/X11
File Names
Notes

M8020

DPV11-XX

VDPV??BI?
XDPV??OBJ

M8021

MRV11-BA

VMRA??BI?
ZKMA??BI?

4a,46

ZQMC??BI?

4b,46

RL 11 1RL V 111 RLO 1 1RL02 Exerciser

R
L
0

Module
Number

Option
Name

Diagnostic
and DEC/X11
Notes
File Names

M8027

LPV11

ZLAE??BI?

LA 180 Printer Diagnostic

XLPA??OBJ

DEC / X 11 LP 11 Exerciser Module

M8028

M8029

DLV11-F

RXV21

Diagnostic and
DEC/X11 Module Titles

VDVC??BI?

11a

DL V 11-F Off-Line Test

XDLA??OBJ

11a

DEC/X11 DL 11 Exerciser Module

ZRXC??BI?

RX02 Utility Driver

ZRXD??BI?

RX02 SS Performance Exerciser

ZRXE??BI?

RX02 Formatter Program

ZRXF??BI?

RX02 FCTN / Log

XRXB??OBJ

DEC/X11 RX02 Exerciser Module

VDLA??BI?

47,48

DLV11-J Test

XDLA??OBJ

DEC/X11 DL 11 Exerciser Module

I\:)

M8043

DLV11-J

Listing
and
Paper Tape
PNs

R
X

R
K

R
L

0
2

19 2 o

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8906B-MC
AK-8908B-MC
AC-E670F-MC
AK-E671F-MC

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-E0068-MC
AK-E008B-MC
AC-E709J-MC
AK-E710J-MC

19 2 o

19 2o

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-E509A-MC
AK-E511A-MC
AC-E512B-MC
AK-E514B-MC
AC-E622A-M2
AK-E624A-M2
AC-E625A-MC
AK-E627A-M1
AC-F098C-MC
AK-F100C-MC

19 2 o

19 2o

19 2 o

19 2o

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-E 188B-MC
AK-E190B-MC
AC-E709J-MC
AK-E71OJ-MC

19 2 o

Diagnostic
and DEC/X11
Notes
File Names

Option
Name

M80441
M8045

MSV11-DXI ZKMA??BI?
MSV11-EX
ZQMC??BI?

MOS I Core 0-124K Exerciser

0-124K Memory Exerciser (16K)

MXV11-AX

VMXA??BI?

MXV11-AX Diagnostic

ZKMA??BI?

MOS I Core 0- 124K Exerciser

ZQMC??BI?

0- 124K Memory Exerciser (16K)

XDLA??OBJ

DEC/X11 DL 11 Exerciser Module

c.l

M8048

MRV11-C

M8049

DRV11-J

VDRC??BI?

DRV 11-J Diagnostic Test Part 1

VDRD??BI?

DRV 11-J Diagnostic Test Part 2

M8053

DMV11

VDMA??BI
VDMB??BI
VDMC??BI
VDMD??BI

R
X
0
1

R
X

0
2

0
5

R
L
0
1

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048F-MC

19 2

19 2o

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-E656A-MC
AK-E658A-MC
AC-8850F-MC
AK-8854F-MC
AC-9045F-MC
AK-9048F-MC
AC-E709J-MC
AK-E710J-MC

19 2

(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-F756A-M 1
AK-F757 A-M 1
AC-F759A-MC
AK-F760A-MC

19 2

Diagnostic and
DEC/X11 Module Titles

Module
Number

M8047

Listing
and
Paper Tape
PNs

DMV11 MCTRL Diagnostic No.1
DMV 11 MCTRL Diagnostic No.2
DMV11 Line Unit Diagnostic No.1
DMV11 Line Unit Diagnostic No.2

R
L
0
2

Module
Number

M8059

Option
Name

MSV11-L

Diagnostic
and DEC/X11
Notes
File Names

Diagnostic and
DEC/X11 Module Titles

Listing
and
Paper Tape
PNs

VDME??BI
XDMD??OBJ
XDMF??OBJ

DMV11 Line Unit Diagnostic No.3
DEC/X11 DM11 Exerciser
DEC/X11 DM11 Exerciser

AC-F805?-M?
AC-F807?-M?

VMSA??BI

Memory Exerciser

ZKMA??BI

MOS 0-124K Exerciser

M8061

RLV12

VRLB??BI
ZRLG??BI
ZRLH??BI
ZRUnBI
ZRLJ??BI
ZRLN??BI
ZRLK??BI
ZRLL??BI
ZRLM??BI

Diskless Diagnostic
Controller Test Part 1
Controller Test Part 2
Drive Test Part 1
Drive Test Part 2
Drive Test Part 3
Performance Exerciser
Compatibility Test
Bad Sector File

M8063

KXT11-AA

NKXAA

KXT11-AA Exerciser

M8064

(See
M8053)

.....
.j>.

AC-S435A-MC
AK-S436A-MC
AC-8850F-MC
AK-8854F-MC

X
0
1

X
0
2

K
0
5

L
0
1

0
2

Module
Number

Option
Name

Diagnostic
and DEC/X11
File Names
Notes

M8067·

MSV11-P

VMSA??BI

Memory Exerciser

ZKMA??BI

MOS 0-124K Exerciser

M8186

KDF11-A

Diagnostic and
DEC/X11 Module Titles

0
2

0
5

0
2

AC-S435A-MC
AK-S436A-MC
AC-8850F-MC
AK-8854F-MC
AC-F138C·MC
AK-F136C-MC

19 20

JKDB??BI?

DCF11-AA Diagnostic

19 20

KEF 11-AA Diagnostic No. 1

AC-F141C-M1
AK-F139C·MC
AC-F241B-MC
AK-F240B-MC
AC-F244B-MC
AK-F243B-MC
AC-E664G-MC
AK-E665G-MC
AC-E667 J-MC
AK-E668J·MC
AC-E742G-MC
AK-E743G-MC

JKDC??BI?

(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

19 20

JKDD??BI?

FPF11

R
X

(Listing)
(Binary PT)

C1I

M8188

R
X

KTF11-AA Diagnostic

JKDA??BI?

Listing
and
Paper Tape
PNs

KEF11-AA Diagnostic No.2

XCPA??OBJ

DEC/X11 Processor Test Module

XCPB??OBJ

DEC/X11 EIS Exerciser Module

XFPA??OBJ

DEC/X11 FP11 Exerciser Module

JFPA??BI

FL T PNT Diagnostic No. 1

JFPB??BI

FL T PNT Diagnostic No.2

AC-F405C-MC
AH-F406C-MC
AC-S442A-MC
AK-S443A-MC

Module
Number

Option
Name

Diagnostic
and DEC/X11
Notes
File Names

M8189

KDF11-BA

JKDA??BI?

Diagnostic and
DEC/X11 Module Titles
KTF11-AA Diagnostic

JKDB??BI?

DCF11-AA Diagnostic

JKDC??BI?

KEF11-AA Diagnostic No.1

JKDD??BI?

KEF11-AA Diagnostic No.2

XCPA??OBJ

DEC/X11 Processor Test Module

XCPB??OBJ

DEC/X11 EIS Exerciser Module

XFPA??OBJ

DEC/X11 FP11 Exerciser Module

VM8A??BI

28,29,
30

BDV11-AA Diagnostic

M8631

MCV11

VMSA??BI

Memory Exerciser

M9400/
M9401

REV11-X/
TEV11/
BCV1X

ZM9A??BI?

Bootstrap /Terminator Test

XBMC??OBJ

DEC/X11 Bootstrap/Terminator

Listing
and
Paper Tape
PNs
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-F138C-MC
AK-F136C-MC
AC-F141C-M1
AK-F139C-MC
AC-F241B-MC
AK-F240B-MC
AC-F244B-MC
AK-F243B-MC
AC-E664G-MC
AK-E665G-MC
AC-E667 J-MC
AK-E668J-MC
AC-E742G-MC
AK-E743G-MC
AC-B061 C-MC
AK-B063C-MC

19 20

AC-S435A-MC
AK-S436A-MC
(Listing)
(Binary PT)
(Listing)
(Binary PT)

AC-8954E-MC
AK-8957E-MC
AC-F057N-MC
AK-F058N-MC

Module
Number

Option
Name

Diagnostic
and DEC/X11
File Names
Notes

A012

ADV11-A

VADA??BI?

ADV11 Pertormance Test

XADC??OBJ

2,3

DEC/X11 ADV11 Exerciser Module

Diagnostic and
DEC/X11 Module Titles

A0026

AXV11-C

VAXA??BI

AXV11 Diagnostic Test

A6001

AAV11-A

VAAA??BI?

AAV11 Diagnostic Test

XAAC??OBJ

DEC / X 11 AAV 11 Exerciser Module

--J

A6006

AAV11-C

VAAA??BI

AAV11-C Diagnostic Test

ABOOO

ADV11-C

VAXA??BI

ADV11-C Diagnostic Test

G653/
H223

MMV11-A

ZKMA??BI?

MOS / Core 0- 124K Exerciser

ZQMC??BI?

0- 124K Memory Exerciser (16K)

Listing
and
Paper Tape
PNs

R
X
0
1

R
X

R
K

R
L

0
2

(Listing)
(Binary PT)
(DOC/
PT Kit)
(Listing)
(Binary PT)

AC-8174C-MC
AK-8176C-MC
ZJ250-RB

19 2 o

AC-E923B-MC
AK-E924B-MC

19 2 o

(Listing)
(Binary PT)
(DOC/PT
KIT)
(Listing)
(Binary PT)

AC-8169A-MC
AK-8172A-MC
ZJ248-RB

19 2o

AC-E917B-MC
AK-E918B-MC

19 2 o

(Listing)
(Binary pT)
(Listing)
(Binary PT)

AC-8850F-MC
AK8854F-MC
AC-9045F-MC
AK-9048G-MC

19 2 o

Notes
1.

Wraparound test and auto-tests require Berg test connector 7012894-00.

Requires an analog ground on any channel to be tested.

May be run asynchronously if KWV 11 is present in system. If run
asynchronously, XKWE??OBJ must be deselected from the
DEC/X 11 run.

4a.

Memory space under test should be contiguous and read/write.
For systems having noncontiguous memory, the memory boundaries must be defined by the operator before running the program.
This diagnostic requires 8K of memory space to run in.

4b.

This test will run successfully only on an 11/23 processor with a
minimum of 16K of memory.

LTC must be disabled.

VKAA??BI? and VKAD??BI? should be run on the CPU prior to
running this test.

Scratch media must be mounted in drives to be tested before
starting the diagnostic.

ZRKJ??BI?, ZRKK??BI?, ZRKL ??BI?, and ZRKI??BI? (if needed)
should be run on subsystem before running this test.

ZRKJ??BI? should be run on the sybsystem before running this
test.

10.

ZRKJ??BI? and ZRKK??BI? should be run on the subsystem before running this test.

11 a.

A wraparound test connector must be installed to run this test.
The connector is not available from stock. The F.E. must make
one up himself. The following instructions (excerpted from Tech
Tip PDP-11/03 TT-11) tell how this is done. The following items
are required:
1 Berg connector
4 Berg pins
#22 wire

(12-10918-15)
(12-10089-07)
(90-07350-00).

Crimp a short length of wire between two Berg pins. Make up two
sets of these. Install one set from pin F to pin J, and one set from
pin E to pin M of the Berg connector.

1118

11 b.

To completely exercise the modem control portion of the DL V 11E, a special wraparound connector (H315) must be installed on
the modem end of the I/F cable. This test connector loops back
certain control lines as well as the data lines.

12.

The test has baud rate dependent configuration requirements.

Baud Rate

No. of Stop Bits No. of Bits

110
All others

2
1

8
8

13.

Requires BC08R test cable for full test of module's data lines.

14.

ZRXB??BI? should be run on the subsystem before running this
test.

15.

If a REV 11 is in the system, DMA refresh must be disabled and
CPU refresh must be enabled.

16.

H315A connector required for external loopback testing.

17.

If customer hardware is connected to the KWV 11 which could inject signals on ST1, ST2 or slave in inputs, it must be disconnected from the inputs.

18.

All switches in switch pack 2 should be left off unless you are instructed otherwise.

19.

I/O signal test no. 1 (ST1 in, ST2 out); install a jumper between
J1-SS (ST2 out) to J1-VV (ST1 in).

Switch Pack 2
Switch

State

2
3
4
5
6
7

Off
On
Off
Off
On
On
Not used.

Use a program starting address of 210.

1119

20.

I/O signal test no. 2 (clock overflow tests); install a jumper between J 1-RR (clock overflow) to J 1- TT (ST2 in).

Switch Pack 2
Switch
2
3

4
5
6
7

State
Off
Off
Off
On
Off
On
Not used.

Use a program starting address of 214.
21.

I/O signal test no. 3 (ST1 out, ST2 in); install a jumper between
J1-UU (ST1 out) to J1-TT (ST2 in).

Switch Pack 2
Switch

State

Off
Off
Off
On
On
On
Not used.

2
3
4
5
6
7

Use a program starting address of 220.
22.

Test may be run with a "known good module" in the system for
comparison. The good module' should be located second (electrically) on the bus, with a cable connecting it and the module undertest.
"known good module" address - 760160
"known good module" vector - 660

23.

Starting restrictions:
If a free-running clock, such as 60 Hz from the power supply, is

attached to the BEVNT bus line on REV C/D/E systems, an interrupt to location 100 will occur when using the ODT "G" and "L"
commands. This will happen prior to the program executing the
first instruction. This program cannot disable the BEVNT bus line
by inhibiting interrupts.

1120

User systems requIring a free-running clock attached to the
BEVNT bus line can temporarily avoid this situation by setting the
PSW to 200, loading the PC with the starting address, and then
using the "P" command, instead of using the starting address and
the "G" command.
Before using the "L" command, the PSW can be set to 200 to inhibit interrupts after loading the absolute loader.
24.

Possible program bombs:
The first two tests check to see if the IBV 11-A responds to the address the program thinks it is at. If not, a bus error occurs.
Bus errors may alter the preset contents of location 4 before the
trap is executed. Program control may be transferred to an area of
the program which is not set up to handle the trap. Or, control may
be passed to some totally unknown and irrelevant p.iece of code
residing accidently in memory. If this occurs, the program will
most probably bomb, and it may also overwrite parts of itself. If this
occurs, the program must be reloaded before proceeding.

25.

If the IB-bus cable is not removed from the module under test, any
errors which are detected could be from some device out on the
IB-bus and not necessarily from the IBV11-A.

26.

If run in staggered maintenance mode, an H329 staggered turnaround connector is required.

27.

If run in external maintenance mode, an H325 cable turn-around
connector is required on all lines which have been selected to be
tested.

28.

This test assumes that the module under test resides in the same
backplane where the line time clock is generated.

29.

Test 3 assumes that switch no. 5 of E21 is in the ON position.

30.

For the rocker switch test, the operator should specify the configuration for the module under test.

31.

VRLA??BI? should be run on the subsystem before running this
test.

32.

VRLA??BI? and ZRLG??BI? should be run on the subsystem before running this test.

33.

A KWV11 programmable line clock is required to run test no. 7.
1121

34.

VRLA??BI?, ZRLG??BI?, and ZRLH??BI? should be run on the
subsystem before running this test.

35.

A KWV 11 programmable line clock is required for some tests.

36.

VRLA??BI?, ZRLG??BI?, ZRLH??BI?, and ZRLI??BI? should be
run on the subsystem before running this test.

37.

VRLA??BI?, ZRLG??BI?, ZRLH??BI?, ZRLI??BI?, ZRLJ??BI?,
and ZRLN??BI? should be run on the subsystem before running
this test.

38.

VRLA??BI?, ZRLG??BI?, ZRLH??BI?, ZRLI??BI?, ZRLJ??BI?,
ZRLK??BI, and ZRLN??BI? should be run on the subsystem before running this test.

39.

VRLA??BI?, ZRLG??BI?, ZRLH??BI?, ZRLI??BI?, and ZRLJ??BI?
should be run on the subsystem before running this test.

40.

A KWV 11 programmable line clock is required for tests 1 and 4.

41.

To check the power fail circuitry, nonvolatile memory must be in
the first 4K of memory.

42.

Power up option no. 1 should be selected on the CPU module for
power fail testing.

43.

The module should be in the standard factory configuration.
jumpers in:
jumpers out:

W1-W5, W7, W8, W11, W13-W15
W6, W9, W10, W12

44.

If the test is to be run in all address modes, then an extender card
and a special test cable (17-00124-01) are required.

45.

The exerciser may be run with the module in address modes 1 or 3
only.

46.

This test may be run only if RAM is present on the board.

47.

All channels must be configured to the same bit-word length.

48.

A wraparound connector (H3270) is required for the data
wraparound tests for each of the lines to be tested.

49.

Requires a BC05W-02 cable to be installed between the Berg connectors. The cable should have a half twist in it.

1122

50.

JKDB?? .BI? should be run on the first 16K of memory before running this test.

51.

JKDC??BI? should be run on the module before running this test.

1123

Media Availability

I\)
~

No.

Media Package
Identifier

Title

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

CZZGG??
CZZGL??
CZZGO??
CZZGY??
CZZGZ??
CZZHD??
CZZHE??
CZZHG??
CZZHQ??
CZZHZ??
CZZID??
CZZIH??
CZZMC??
CZZMD??
CZZMT??
CZZMU??
CZZMZ??
CZZZD??
CZZLA??
CZZLN??

DXDP+ 7 DEC/X11 EXEC 1
1
DXDP+ 12 RC,RF,RK11
DXDP+ 15 RX11 DIAG
1
DXDP+ 25 LSI FLP 1
DXDP+ 26 DEC/X11 EXEC 2
1
1
DXDP+ 30 DEC/X11 EXEC 3
1
DXDP+ 31 LSI FLP 2
DXDP + 33 LSI FLP 3
1
1
DXDP+ 43 LSI FLP 4
1
DXDP + 52 RL02 DIAG no. 1
DXDP + 56 RL02 DIAG no. 2
1
1
DXDP+ 60 LSI FLP 5
DYDP+ 3 LSI-11 no. 1
2
2
DYDP+ 4 DEC/X11 no. 1
2
DYDP + 20 LSI-11 no. 2
2
DYDP+ 21 DEC/X11 no. 2
DYDP+ 26 LSI-11 no. 3
2
LSI-11 DKDP + Diagnostic PKG
DLDP+ (RL01) Diagnostic PKG no. 1
DLDP+ (RL02) Diagnostic PKG

Notes

Media PNs
AS-9645?-M?
AS-9650?-M?
AS-9653?-M?
AS-9663?-M?
AS-9664?-M?
AS-9668?-M?
AS-9669?-M?
AS-9671 ?-M?
AS-C638?-M?
AS-F547?-M?
AS-F753?-M?
AS-F804?-M?
BA-F021 ?-M?
BA-F022?-M?
BA-F048?-M?
BA-F049?-M?
BA-F558?-M?
AN-9696?-M?
AX-E380?-M?
BC-F916?-M?

Documentation
Media Kit PNs
ZJ271-RY

ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RY
ZJ271-RX
ZJ271-RX
ZJ271-RX
ZJ271-RX
ZJ271-RX
ZJ278-RE
ZJ278-RQ
ZJ278-RH

Notes
1.
2.

Documentation/media kit ZJ271-RY contains all of these floppies as well as all of the applicable documentation.
Documentation/media kit ZJ271-RX contains all of these floppies as well as all of the applicable documentation.

APPENDIX B
FLOATING ADDRESSES / VECTORS
FLOATING ADDRESSES
The conventions for the assignment of floating addresses for modules on
the LSI-11 bus are the same as UNIBUS devices. UNIBUS devices are used
to explain the ranking sequence.
The floating-address convention used for communications and for other devices that interface with the PDP-11 series of products assigns addresses
sequentially starting at 760 a 1a (or 160 a 10) and proceeds upward to 763
776 (or 163 776). For the sake of compatibility with UNIBUS conventions,
addresses are expressed as consisting of 18 bits (7XX XXX) rather than 16
bits (1XX XXX).
Floating addresses are assigned in the following sequence.

Rank

UNIBUS
Device

1
2
3
4
5
6
7
8
9
10

DJ 11
DH11
DQ11
DU11
DUP11
LK11A
DMC11
DZ11
KMC11
RL 11 (extras)

LSI-11
Device

DUV11

DZV11
RL V 11 (extras)

FLOATING VECTORS
The conventions for the assignments of floating vectors for modules on the
LSI-11 bus will adhere to those established for UNIBUS devices. UNIBUS
devices are used to explain the priority ranking for floating vectors and are
included in the subsequent table of trap and interrupt vectors as a guide for
the user.
The floating-vector convention used for communications and for devices
that interface with the PDP-11 series of products assigns vectors sequentially starting at 300 and proceeding upward to 777. (Some LSI-11 bus
modules, such as the DL V 11 and DRV 11, have an upper vector limit of
377.) The following table shows the sequence for assigning vectors to modules. It can be seen that the first vector address, 300, is assigned to the
first DLV11 in the system. If another DLV11 is used, it would then be assigned to all the DL V 11 s (up to a maximum of 32); addresses are then assigned consecutively to each unit of the next highest-ranked device
(DRV 11 or DLV 11-E, and so forth), then to the other devices according to
their rank.
1125

Ranking for Floating Vectors
(Start at 300 and proceed upward.)
Rank

UNIBUS

1
2
3
4
5
6

DC11
KL 11, DL 11·A, ·B
DP 11
DM11·A
DN11
DM11·BB
DR 11·A
DR 11-C
PA611 Reader
PA611 Punch
DT11
DX11
DL 11-C, -D,-E
DJ11
DH11
GT40
LPS11
DQ11
KW11-W
DU11

7
8
9
10
11
12
13
14
15
16
17
18
19
20

LSI-11 Bus

1126

DL V 11, ·F, .J

DRV11·B
DRV11

DLV11-E

KWV11
DUV11

APPENDIX C
LSI-11 BUS SPECIFICATION

GENERAL
NOTE
This is not the complete LSI-11 bus specification, but is included to
permit users to design and implement typical interfaces to the LSI-11
bus.
The processor, memory, and I/O devices communicate via 38 bidirectional signal
lines that constitute the LSI-11 bus. Addresses, data, and control information are
sent along these signal lines, some of which contain time-multiplexed information.
The lines are functionally divided as follows:
18
6
3
6
5

Data/address lines - BDAL<17:00>
Data transfer control lines - BBS7, BDIN, BDOUT, BRPLY, BSYNC,
BWTBT
Direct memory access control lines - BDMG, BDMR, BSACK
Interrupt control lines - BEVNT, BIAK, BIR04, BIR05, BIR06, BIR07
System control lines - BDCOK, BHALT, BIN IT, BPOK, BREF

Most LSI-11 bus signals are bidirectional and use terminations for a negated (high)
signal level. Devices connect to these lines via high-impedance bus receivers and
open collector drivers. The asserted state is produced when a bus driver asserts
the line low. Although bidirectional lines are electrically bidirectional (any point
along the line can be driven or received), certain lines are functionally unidirectional. These lines communicate to or from a bus master (or signal source), but not
both. Interrupt acknowledge (BlACK) and direct memory access grant (BDMG)
signals are physically unidirectional in a daisy-chain fashion. These signals start at
the processor output signal pins. Each is received on device input pins (BIAKI or
BDMGI) and conditionally retransmitted via device output pins (BIAKI or BDMGI)
and conditionally retransmitted via device output pins (BIAKO or BDMGO). These
signals are received from higher priority devices and are retransmitted to lower
priority devices along the bus.

1127

Master/Slave Relationship

Communication between devices on the bus is asynchronous. A master/slave
relationship exists throughout each bus transaction. At any time, there is one
device that has control of the bus. This controlling device is called the "bus
master." The master device controls the bus when communicating with another
device on the bus, called the slave. The bus master (typically the processor or a
DMA device) initiates a bus transaction. The slave device responds by acknowledging the transaction in progress and by receiving data from, or transmitting data
to, the bus master. LSI-11 bus control signals transmitted or received by the bus
master or bus slave device must complete the sequence according to bus
protocol.
The processor controls bus arbitration (Le., who becomes bus master at any given
time). A typical example of this relationship is the processor, as master, fetching
an instruction from memory (which is always a slave). Another example is a disk,
as master, transferring data to memory as slave. Theoretically, any device can be
master or slave, depending on the circumstances. Communication on the LSI-11
bus is interlocked so that for each control signal issued by the master device,
there must be a response from the slave in order to complete the transfer. It is this
master/slave signal protocol that makes the LSI-11 bus asynchronous. The asynchronous operation precludes the need for synchronizing with clock pulses.
Since bus cycle completion by the bus master requires response from the slave
device, each bus master must include a timeout error circuit that will abort the bus
cycle if the slave device does not respond to the bus transaction within 10
microseconds.
The actual time before a timeout error occurs must be longer than the reply time of
the slowest peripheral or memory device on the bus.
The signals and pin assignments are tabulated as shown below. The pin nomenclature is for reference and is only required when examining DIGITAL modules and
circuit schematics. A functional description of the LSI-11 bus pins and signals is
also found below.

1128

Categories of LSI-11 Bus Signal Lines
Number Functional
Category

of Pins

DIGITAL's
Nomenclature

Datal Address BDALO,

(Name)
(Pin)

AU2

BDAL1,
AV2

BDAL2,
BE2

BDAL15,
BV2

BDAL 16,
AC1

BDAL17,
AD1

Data Control

BDOUT,
AE2

BRPLY,
AF2

BDIN,
AH2

BSYNC,
AJ2

BWTBT,
AK2

BBS?,
AP2

Interrupt
Control

BIRO?,
BP1

BIR06,
AB1

BIR05,
AA1

BIR04,
AL2

BIAKO,
AN2

BIAKI,
AM2

DMA Control

BDMR,
AN1

BDMGO, BDMGI,
AS2
AR2

BSACK,
BN1

System
Control

BHALT,
AP1

BREF,
AR1

BPOK,
BB1

BEVNT,
BR1

BINIT,
AT2

+5 Vdc

AA2, BA2, BV1

+12 Vdc

AD2, BD2

-12 Vdc

AB2, BB2

+12 B*

AS1, BS1

+5 B*

AV1, (AE1, AS1 alternates)

GND

AC2, AJ1, AM1, AT1, BC2, BJ1, BM1, BT1

S SPARES

AE1, AAF1, AH1, BC1, BD1, BE1, BF1,
BH1

M SPARES

AK1 - AL 1, BK1 - BL 1 (pairs connected)

PSPARES

AU1, BU1

BDCOK,
BA1

* Battery

1129

Functional Descriptions
Bus
Pin

Signal
Mnemonic

Signal Function

AA1

BIR05 L

Interrupt request priority level 5

AB1

BIR06 L

Interrupt request priority level 6

AC1

BDAL16 L

Address line 16 during addressing protocol; memory
error line during data transfer protocol.

AD1

BDAL17 L

Address line 17 during addressing protocol; memory
error enable during data transfer protocol.

AE1

SSPARE1
(alternate +5 B)

Special spare - not assigned or based in DIGITAL
cable or backplane assemblies; available for user
connection. Optionally. this pin may be used for +5
V battery (+5 B) backup power to keep critical circuits alive during power failures. A jumper is
required on LSI-11 bus options to open (disconnect)
the +5 B circuit in systems that use this line as
SSPARE1.

AF1

SSPARE2

Special spare - not assigned or bused in DIGITAL
cable or backplane assemblies; available for user
interconnection. In the highest priority device slot.
the processor may use this pin for a signal to indicate its RUN state.

AH1

SSPARE3
SRUN

Special spare - not assigned nor bused in DIGITAL
cable or backplane assemblies; available for user
interconnection.

AJ1

GND

Ground - System signal ground and dc return.

AK1
AL1

MSPAREA
MSPAREB

Maintenance Spare - Normally connected together
on the backplane at each option location (not bused
connection).

AM1

GND

Ground - System signal ground and dc return.

1130

Functional Descriptions (Cont)
Bus
Pin

Signal
Mnemonic

AN1

BDMRL

Direct memory access (DMA) request - device
asserts this signal to request bus mastership. The
processor arbitrates bus mastership between itself
and all DMA devices on the bus. If the processor is
not bus master (it has completed a bus cycle and
BSYNC L is not being asserted by the processor), it
grants bus mastership to the requesting device by
asserting BDMGO L. The devices responds by
negating BDMR L and asserting BSACK L.

AP1

BHALT L

Processor halt - When BHALT L is asserted, the
processor responds by going into console ODT
mode.

AR1

BREF L

Memory refresh - used to refresh dynamic memory
devices. The LSI-11 processor microcode features
automatic refresh control. BREF L is asserted during this time to override memory bank selection
decoding. Interrupt requests and BBS7 are blocked
out during this time.

AS1

+5 B or +12 B
(battery)

Signal Function

+ 12 or +5 Vdc battery backup power to keep critical
circuits alive during power failures. This signal is not
bused to BS1 in all DIGITAL backplanes. A jumper is
required on all LSI-11 bus options to open (disconnect) the backup circuit from the bus in systems that
use this line at the alternate voltage.

AT1

GND

Ground - system signal ground and dc return.

AU1

PSPARE1

Power spare 11 (not assigned a function; not recommended for use) - If a module is using -12 V (on
BB2) and if the module is accidentally inserted backward in all the backplane, -12 Vdc appears on pin
AU1.

AV1

+5 B

+5 V battery power - secondary +5 V power connection. Battery power can be used with certain
devices.

1131

Functional Descriptions (Cont)
Bus
Pin

Signal
Mnemonic

BA1

BDCOK H

DC power OK - Power supply-generated signal that
is asserted when there is sufficient dc voltage available to sustain reliable system operation.

BB1

BPOK H

AC power OK - Asserted by the power supply when
primary power is normal. When negated during
processor operation, a power fail trap sequence is
initiated.

BC1
BD1
BE1
BF1
BH1

SSPARE 4
SSPARE 5
SSPARE 6
SSPARE 7
SSPARE 8

Special spares - not assigned or bused in DIGITAL's cable and backplane assemblies; available for
user interconnections. Caution. These pins may be
used as test pOints by DIGITAL in some options.

BJ1

GND

Ground - system signal ground and dc return.

BK1
BL1

MSPAREB
MSPAREB

Maintenance spares - Normally connected together
on the backplane at each option location (not a
bused connection).

BM1

GND

Ground - system signal ground and dc return.

BN1

BSACK L

This signal is asserted by a DMA device in response
to the processor's BDMGO L signal, indicating that
the DMA device is bus master.

BP1

BIRQ7 L

Interrupt request priority level 7

BR1

BEVNT L

External event interrupt request - When the processor latches the leading edge and arbitrates as a
level 6 interrupt. A typical use of this signal is a line
time clock interrupt.

BS1

+12 B

+12 Vdc battery backup power (not bused to AS1 in
all DIGITAL backplanes)

BT1

GND

Ground - system signal ground and dc return.

BU1

PSPARE2

Power spare 2 (not assigned a function, not recommended for use) -If a module is using -12 V (on pin
AB2) and if the module is accidentally inserted backwards in the backplane, -12 Vdc appears on pin
BU1.

Signal Function

1132

Functional Descriptions (Cont)
Bus
Pin

Signal
Mnemonic

Signal Function

BV1

+5 V power - Normal +5 Vdc system power

AA2

+5 V power - Normal +5 Vdc system power

AB2

-12

-12 V Power - -12 Vdc (optional) power for devices
requiring this voltage.

AC2

GND

Ground - system Signal ground and dc return

AD2

+12

+ 12 V Power - +12 Vdc system power

AE2

BDOUT L

Data Output - BDOUT, when asserted, implies that
valid data is available on BDAL <0: 15> L and that an
output transfer, with respect to the bus master
device is taking place. BDOUT L is deskewed with
respect to data on the bus. The slave device
responding to the BDOUT L signal must assert
BRPLY L to complete the transfer.

AF2

BRPLY L

Reply - BRPL Y L is asserted in response to BDIN L
or BDOUT L and during IAK transaction. It is generated by a slave device to indicate that it has placed
its data on the BDAL bus or that it has accepted
output data from the bus.

AH2

BDIN L

Data Input - BDIN L is used for two types of bus
operation:
1. When asserted during BSYNC L time, BDIN L
implies an input transfer with respect to the current bus master, and requires a response (BRPLY L). BDIN L is asserted when the master
device is ready to accept data from a slave
device.
2. When asserted without BSYNC L, it indicates
that an interrupt operation is occurring.
The master device must deskew input data from
BRPLY L.

1133

Functional Descriptions (Cont)
Bus
Pin

Signal
Mnemonic

AJ2

BSYNC L

Synchronize - BSYNC L is asserted by the bus
master device to indicate that it has placed an
address on the bus. The transfer is in process until
BSYNC L is negated.

AK2

BWTBT L

Write/Byte - BWTBT L is used in two ways to control a bus cycle:

Signal Function

1. It is asserted during the leading edge of BSYNC
L to indicate that an output sequence is to follow
(DATO or DATOB), rather than an input
sequence.
2. It is asserted during BDOUT L, in a DATOB bus
cycle, for byte addressing.
AL2

BIRQ4 L

Interrupt request priority level 4

AM2
AN2

BIAKI L
BIAKO L

Interrupt acknowledge - In accordance with interrupt protocol, the processor asserts BIAKO L to
acknowledge the honoring of an interrupt. The bus
transmits this to BIAKI L of the next priority device
(electrically closest to the processor). This device
accepts the interrupt acknowledge under two
conditions:
1. The device requested the bus by asserting an
interrupt, and
2. The device has the highest priority interrupt
request on the bus at that time.
If these conditions are not met, the device asserts
BIAKO L to the next device on the bus. This process
continues in a daisy-chain fashion until the device
with the highest interrupt priority receives the interrupt acknowledge (IAK) signal.

AP2

BBS7 L

Bank 7 select - The bus master asserts this signal
to reference the I/O page (including that portion of
the I/O page reserved for nonexistent memory). The
address in BDAL<O:12> L when BBS7 L is asserted
is the address within the I/O page.
1134

Functional Descriptions (Cont)
Bus
Pin

Signal
Mnemonic

AR2
AS2

BDMGI L
BDMGO L

Direct memory access grant - The bus arbitrator
asserts this signal to grant bus mastership to a
requesting device, according to bus mastership protocol. The signal is passed in a daisy-chain from the
arbitrator (as BDMGO L) through the bus to BDMGI
L of the next priority device (electrically closest
device on the bus). This device accepts the grant
only if it requested to be bus master (by a BDMR L).
If not, the device passes the grant (asserts BDMGO
L) to the next device on the bus. This process continues until the requesting device acknowledges the
grant.

AT2

BINIT L

Initialize - This signal is used for system reset. All
devices on the bus are to return to a known, initial
state; i.e., registers are reset to zero, and logic is
reset to state O. Exceptions should be completely
documented in programming and engineering specifications for the device.

AU2

BDALO L

Data/address line 00.

AV2

BDAL1 L

Data/address line 01.

BA2

+5 Vdc power.

BB2

-12

-12 Vdc power (optional, not required for DIGITAL
LSI-11 hardware options).

BC2

GND

Power supply return.

BD2

+12

+ 12 Vdc power.

BE2

BDAL2 L

Data/address line 02.

BF2

BDAL3 L

Data/address line 03.

BH2

BDAL4 L

Data/address line 04.

BJ2

BDAL5 L

Data/address line 05.

Signal Function

1135

Functional Descriptions (Cont)
Bus
Pin

Signal
Mnemonic

Signal Function

BK2

BDAL6 L

Data/address line 06.

BL2

BDAL7 L

Data/address line 07.

BM2

BOALS L

Data/address line OS.

BN2

BDAL9 L

Data/address line 09.

BP2

BDAL10 L

Data/address line 10.

BR2

BDAL11 L

Data/address line 11.

BS2

BDAL12 L

Data/address line 12.

BT2

BDAL13 L

Data/address line 13.

BU2

BDAL14 L

Data/address line 14.

BV2

BDAL15 L

Data/address line 15.

1136

DATA TRANSFER BUS CYCLES
Data transfer bus cycles are as follows:

Bus Cycle
Mnemonic

Description

Function (with respect
to the bus master)

DATI
DATO
DATOB
DATIO
DATIOB

Data word input
Data word output
Data byte output
Data word input/output
Data byte input/byte output

Read
Write
Write byte
Read-modify-write
Read-modify-write byte

These bus cycles, executed by bus master devices, transfer 16-bit words or 8-bit
bytes to or from slave devices. The following bus signals are used in a data
transfer operation.

Mnemonic

Description

Function

BDAL<17:00> L

18 Data/address lines

BDAL<15:00> L are used
for word and byte transfers.
BDAL<17:16> L are used
for extended addressing,
memory parity error, and
memory parity error enable
functions.

BSYNC L
BDIN L
BDOUT L
BRPLY L
BWTBT L
BBS7 L

Synchronize
Data input strobe
Data output strobe
Reply
Write/byte control
Bank select 7

Strobe signals

Control signals

Data transfer bus cycles can be reduced to three basic types: DATI, DATOB and
DATIOB. These transactions occur between the bus master and one slave device
selected during the addressing portion to the bus cycle.
Bus Cycle Protocol
Before initiating a bus cycle, the previous bus transaction must have been completed (BSYNC L negated) and the device must become bus master. The bus cycle
can be divided into two parts, an addressing portion and a data transfer portion.
During the addressing portion, the bus master outputs the address for the desired
slave device (memory or device register). The selected slave device responds by
latching the address bits and holding this condition for the duration of the bus
cycle (until BSYNC L becomes negated). During the data transfer portion, the
actual data transfer occurs.

1137

Device Addressing
The device addressing portion of a data transfer bus cycle comprises an address
setup and deskew time and an address hold/deskew time. During the address
setup and deskew time, the bus master does the following:
Asserts BDAL<17:00> L with the desired slave device address bits
Asserts BBS7 L if a device in the I/O page is being addressed
Asserts BWTBT L if the cycle is a DATO(B) bus cycle
Asserts BSYNC at least 150 ns after BDAL<17:00> L, BBS7 L, and BWTBT L
are valid.
During this time the address, BBS7 L, and BWTBT L signals are asserted at the
slave bus receiver for at least 75 ns before BSYNC goes active. Devices in the I/O
page ignore the five high-order address bits BDAL<17:13> and instead decode
BBS7 along with the 13 low-order address bits. An active BWTBT L signal indicates that a DATO(B) operation follows, while an inactive BWTBT L indicates a
DATI or DATIO(B) operation.
The address hold/deskew time begins after BSYNC L is asserted. The master
must hold the address at BDAL at least 100 ns after the assertion of BSYNC.
The slave device uses the active BSYNC L bus receiver output to clock BDAL
address bits, BBS7 Land BWTBT L, into its internal logic. BWTBT L, BBS7 L, and
BDAL<17:00>L will remain active for a minimum of 25 ns after the BSYNC L bus
receiver goes active. BSYNC L remains active for the duration of the bus cycle.
Device selected logic must be reset at the end of the current bus cycle. The device
should not wait until the next BSYNC L signal to reset the device selected logic.
Memory and peripheral devices are addressed similarly, except for the way the
slave device responds to BBS7. Addressed peripheral devices must not decode
address bits on BDAL<17:13> L. Addressed peripheral devices may respond to a
bus cycle only when BBS7 is asserted (low) during the addressing portion of the
cycle. When asserted, BBS7 L indicates that the device address resides in the I/O
page (the upper 4K address space). Memory devices generally do not respond to
addresses in the I/O page; however, some system applications may permit memory to reside in the I/O page for use as DMA buffers, read-only-memory bootstraps
or diagnostics, etc.

1138

DATI
The DATI bus cycle is a read operation. During DATI, data is input to the bus
master. Data consists of 16-bit word transfers over the bus. During the data
transfer portion of the DATI bus cycle, the bus master asserts BDIN L, 100 ns
minimum, 8 ns maximum, after BSYNC L is asserted. The slave device responds
to BDIN L active in the following ways:
Asserts BRPLY L after receiving BDIN Land 125 ns (maximum) before BDAL
bus driver data bits are valid
Asserts BDAL<17:00> L with the addressed data and error information.

BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE
(MEMORY OR DEVICE)

ADDRESS DEVICE MEMORY
• ASSERT BDAL <21,00> L WITH
ADDRESS AND
• ASSERT BBS7 IF THE ADDRESS
IS IN THE 1/0 PAGE
• ASSERT BSYNC L

----

--- ---------

DECODE ADDRESS
STORE··DEVICE SELECTED"
OPERATION

REOUEST DATA
• REMOVE THE ADDRESS FROM
BDAL <2LOO> L AND NEGATE BBS7
L
• ASSERT BDrN l

---------.

TERMINATE INPUT TRANSFER
• ACCEPT DATA AND RESPOND
BY NEGATING BDIN L

-- - --

TERMINATE BUS CYCLE
• NEGATE BSYNC L

INPUT DATA
• PLACE DATA ON BDAL < 15,00> L
_ _ • ASSERT BRPLY L

OPERATION COMPLETED
- - - - - - - - _ . NEGATE BRPl Y l

DATI Bus Cycle

1139

T/R DAl

~__R_D_AT_A____J)(~_________'4_'___________

T ADDR

200 NS MINIMUM

TSYNC

100 NS MINIMUM
8 liS MAXIMUM

20QNSMINIMUM

---+--------------

CLOCKDATA

T DIN

R RPl Y

T 857

TWTST

150 NS
MINIMUM

141

~~______~;(L_____________________

'_4}_____________________________

TIMING AT MASTER DEVICE

RfT DAL

R SYNC

R DIN

TRPLY

R BS7

R WTST

TIMING AT SLAVE DEVICE
NOTES
1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "8" PREFIX.
4. DON'T CARE CONDITION.

DATI Bus Cycle Timing

When the bus master receives BRPLY L. it does the following:
Waits at least 200 ns deskew time and then accepts input data at
BDAL<17:00>L bus receivers. BDAL<17:16>L are used for transmitting parity errors to the master.
Negates BDIN L no less than 150 ns and no more than 2 microseconds after
BRPLY L goes active.

1140

The slave device responds to BDIN L negation by negating BRPLY L and removing read data from BDAL bus drivers. BRPLY L must be negated no more than 100
ns prior to removal of read data. The bus master responds to the negated BRPL Y
L by negating BSYNC L.
Conditions for the next BSYNC L assertion are as follows:
BSYNC L must remain negated for 200 ns (minimum)
BSYNC L must not become asserted within 300 ns of previous BRPLY L
negation.

NOTE
Continuous assertion of BSYNC L retains ccontrol of the bus by the
bus master, and the previously addressed slave device remains
selected. This is done for DATIO(B) bus cycles where DATO or DATOB
follows a DATI without BSYNC L negation and a second device
addressing operation. Also, a slow slave device can hold off data
transfers to itself by keeping BRPLY L asserted, which will cause the
master to keep BSYNC L asserted. Exceeding 15 psec hold time will
cause loss of memory if bus refresh is being used.

1141

DATOB
DATOB is a write operation. Data is transferred in 16-bit wOids (DATO) or 8-bit
bytes (DATOB) from the bus master to the slave device. The data transfer output
can occur attar the addressing portion of a bus cycle when BWTBT L had been
asserted by the bus master, or immediately following an input transfer part of a
DATIOB bus cycle.
BUS MASTER
(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY
• ASSERT BDAL <21 :00> L WITH
ADDRESS AND
ASSERT BBS7 L IF ADDRESS IS
IN THE 110 PAGE
ASSERT BWTBT L IWRITE
CYCLE)
ASSERT BSYNC L

SLAVE
(MEMORY OR DEVICE)

- -- ---

-- --- ----- ---

OUTPUT DATA
• REMOVE THE ADDRESS FROM
BDAL <21 :00> L AND NEGATE BBS7 L
• NEGATE BWTBT L UNLESS DATOB
PLACE DATA ON BDAL < 15:00> L
• ASSERT BDOUT L
_

_____

DECODE ADDRESS
_____ • STORE ··DEVICE SELECTED··
OPERATION

-- - ------- -- ----

TERMINATE OUTPUT TRANSFER
NEGATE BDOUT L (AND BWTBT L
IF A DATOB BUS CYCLE)
• REMOVE DATA FROM BDAL<15:00> L ____

TERMINATE BUS CYCLE
• NEGATE BSYNC L

_ . ASSERT BRPLY L

-- --

....--------- --DATO or DATOB Bus Cycle

1142

TAKE DATA
• RECEIVE DATA FROM BDAL
LINES

OPERATION COMPLETED
NEGATE BRPLY L

T DAL

==__~x

TDATA

1=100 NS MINIMUM
TSYNC

T DOUT

R RPL Y

T BS?

141

TWTBT

141
100 NS
MINIMUM

TIMING AT MASTER DEVICE

~_ _ _ _R_D_A_T_A_ _ _~X

\:=::25

(41
NS MINIMUM

R SYNC

R DOUT

T RPLY

R BS?

141

R WTBT

3_ BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A' B" PREFIX
4. DON'T CARE CONDITION

DATO or DATOB Bus Cycle Timing

The data transfer portion of a DATOB bus cycle comprises a data set-up and
deskew time and a data hold and deskew time.
During the data set-up and deskew time, the bus master outputs the data on
BDAL<16:00> L at least 100 ns after BSYNC L is asserted. If it is a word transfer,
the bus master negates BWTBT L at least 100 ns after BSYNC L assertion and
BWTBT L remains negated for the length of the bus cycle. If the transfer is a byte
transfer, BWTBT L remains asserted. If it is the output of a DATIOB, BWTB L
becomes asserted and lasts the duration of the bus cycle. During a byte transfer,
1143

BDAL 00 L selects the high or low byte. This occurs while in the addressing
portion of the cycle. If asserted, the high byte (BDAL<15:08> L) is selected;
otherwise, the low byte (BDAL<07:00> L) is selected. An asserted BDAL i6 L at
this time will force a parity error to be written into memory if the memory is a
parity-type memory. BDAL 17 L is not used for write operations. The bus master
asserts BDOUT L between 100 ns and 8 usec after BDAL and BWTBT L bus
drivers are stable. The slave device responds by asserting BRPLY L within 10
microseconds to avoid bus timeout. This completes the data setup and deskew
time.
During the data hold and deskew time, the bus master receives BRPLY Land
negates BDOUT L. BDOUT L must remain asserted for at least 150 ns from the
receipt of BRPLY L before being negated by the bus master. BDAL<16:00> L bus
drivers remain asserted for at least 100 ns after BDOUT L negation. The bus
master then negates BDAL inputs.
During this time, the slave device senses BDOUT L negation. The data is accepted
and the slave device negates BRPLY L. The bus master responds by negating
BSYNC L. However, the processor will not negate BSYNC L for at least 175 ns
after negating BDOUT L. This completes the DATOB bus cycle. Before the next
cycle BSYNC L must remain unasserted for at least 200 ns.

1144

oAT/OB

The protocol for a DATIOB bus cycle is identical to the addressing and data
transfer portions of the DATI and DATOB bus cycles. After addressing the device,
a DATI cycle is performed as explained above; however, BSYNC L is not negated.
BSYNC L remains active for an output word or byte transfer (DATOB). The bus
master maintains at least 200 ns between BRPL Y L negation during the DATI cycle
and BDOUT L assertion. The cycle is terminated when the bus master negates
BSYNC L, which is the same as described for DATOB.
SLAVE
(MEMORY OR DEVICE)

BUS MASTER
(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY
•
ASSERT BDAl <21 :00> l WITH
ADDRESS
•
ASSERT BBS7 l IF THE
ADDRESS IS IN THE I/O PAGE
•
ASSERT BSYNC l

REOUEST DATA
REMOVE THE ADDRESS FROM
BDAl <21 :00> l
•
ASSERT BDIN l

---

- - - - DECODE ADDRESS
•
STORE "DEVICE SELECTED"
OPERATION

---

.... -

- - - - - --"'INPUT DATA

TERMINATE INPUT TRANSFER
•
ACCEPT DATA AND RESPOND BY
TERMINATING BDIN l

-----

•

---

PLACE DATA ON BDAl < 15:00 > l
ASSERT BRPl Y l

COMPLETE INPUT TRANSFER
REMOVE DATA
NEGATE BRPlY l

OUTPUT DATA
PLACE OUTPUT DATA ON BDAl < 15:00> l
(ASSERT BWTBT l IF AN OUTPUT
BYTE TRANSFER)
ASSERT BDOUT l

--- -- -

- - - .... TAKE DATA

TERMINATE OUTPUT TRANSFER
•
REMOVE DATA FROM BDAl LINES
NEGATE BDOUT l
•

TERMINATE BUS CYCLE
NEGATE BSYNC l
(AND BWTBT l IF IN
A DATIOB BUS CYCLE)

......

•

RECEIVE DATA FROM BDAl LINES
ASSERT BRPLY L

---

-- --

OPERATION COMPLETED
NEGATE BRPLY L

DA TIO or DA TIOB Bus Cycle

1145

rR/T DAL

0 NS MINIMUM

141

TSYNC

T DOUT

T DIN

R RPLY

T 8S7

141

TIMING AT MASTER DEVICE

RT/DAL

TDATA

I"'" 25 NS

141

'------'

t--MINIMUM
R SYNC

R DOUT

R DIN

T RPLY

R BS7

141
25 NS MINIMUM

TIMING AT SLAVE DEVICE
NOTES
1. TIMING SHOWN AT REQUESTING DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T - BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "8" PREFIX
4. DON'T CARE CONDITION

DATIO or DATIOB Bus Cycle Timing

Parity Protocol
The KDF11-AA recognizes memory parity errors and traps to location 1148 if one
occurs. A parity error detection occurs during every DATI or DATI portion of a
DATIOB cycle. The processor samples BDAL 16 Land BDAL 17 L after the 200 ns
REPLY deskew time similar to BDAL <15:00> L. BDAL 16 L is interpreted as a
parity error signal from memory and BDAL 17 L is interpreted as a parity error
enable signal from an external parity controller module. BDAL 17 L is used by

1146

software to enable parity detection which is done by addressing a parity status
register on the LSI-11 bus. Parity status register hardware then asserts BDAL 17 L
during the BDIN L portion of DATI cycles to inform the processor or bus master
that detection is enabled. BDAL 16 L is used to indicate a parity error and is
asserted by the selected memory at REPLY time. Upon system power-up, memory
may contain random data and erroneous parity error signals may be used (BDAL
16 L asserted). Until known data is written into memory, software keeps BDAL 17
L negated, to avoid false traps. After known data and correct parity have been
written into memory, software can enable parity detection in the parity status
register. If both BDAL 16 Land BDAL 17 L are asserted at REPLY time, an abort
and trap to location 1148 will occur. The assertion of BDAL 16 L during BDOUT L
will cause memory to write wrong parity as a diagnostic tool for maintenance
purposes.
Direct Memory Access
The direct memory access (DMA) capability allows direct data transfers between
I/O devices and memory. This is useful when using mass storage devices (e.g.,
disks) that move large blocks of data to and from memory. A DMA device only
needs to know the starting address in memory, the starting address in mass
storage, the length of the transfer, and whether the operation is read or write.
When this information is available, the DMA device can transfer data directly to (or
from) memory. Since most DMA devices must perform data transfers in rapid
succession or lose data, DMA devices are provided the highest priority.
DMA is accomplished after the processor (normally the bus master) has passed
bus mastership to the highest priority DMA device that is requesting the bus. The
processor arbitrates all requests and grants the bus to the DMA device located
electrically closest to the processor. A DMA device remains bus master indefinitely
until it relinquishes its mastership. The following control signals are used during
bus arbitration:
BDMGI L
BDMGO L
BDMR L
BSACK L

DMA Grant Input
DMA Grant Output
DMA Request Line
Bus Grant Acknowledge

1147

DMA PROTOCOL
A DMA transaction can be divided into three phases: the bus mastership acquisition phase, the data transfer phase, and the bus mastership relinquish phase.

BUS MASTER
(CONTROLLER)

KDJll·A PROCESSOR
(MEMORY IS SLAVE)

REQUEST BUS
_

• ASSERT SOMR L

GRANT BUS CONTROL
• NEAR THE END OF THE

...-

CURRENT BUS CYCLE
(BRPLY L IS NEGATED).
ASSERT BDMGO LAND

INHIBIT NEW PROCESSOR
GENERATED BYSNC L FOR
THE DURATION OF THE
DMA OPERATION

--...

TERMINATE GRANT
SEQUENCE
• NEGATE BDMGO LAND
WAIT FOR DMA OPERATION ~
TO BE COMPLETED

ACKNOWLEDGE BUS
MASTERSHIP
• RECEIVE BDMG
• WAIT FOR NEGATION OF
BSYNC LAND BRPLY L
• ASSERT BSACK L
• NEGATE BDMR L

EXECUTE A DMA DATA
-.. TRANSFER

____

RESUME PROCESSOR
OPERATION

• ADDRESS MEMORY AND
TRANSFER UP TO 4 WORDS
OF DATA AS DESCRIBED
FOR DATI. OR DATO BUS
CYCLES
• RELEASE THE BUS BY
TERMINATING BSACK L
(NO SOONER THAN
NEGATION OF LAST BRPLY
LI AND BSYNC L

• ENABLE PROCESSOR-

GENERATED BSYNC L
(PROCESSOR IS BUS
MASTER) OR ISSUE
ANOTHER GRANT IF BDMR
L IS ASSERTED

WAIT4"SOR UNTIL
ANOTHER FIFO TRANSFER
IS PENDING BEFORE
REQUESTING BUS AGAIN.

DMA Request/Grant Sequence

1148

SECOND
REOUEST

r-~~r-rrTT77f7f

/1/////////1.

T DMR

NS MINIMUM

R DMG

TSACK

RfT SYNC

....
./>.

RfT RPLY

rrT DAL
(ALSO BS7,
WTBT, REFI

;(

----------------

---..j

0 NS MINIMUM

0 NS MI NIMUM r - - - - - - - - - - - - - i
ADDR)(

NOTES:
1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER INPUTS
AND BUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T: BUS DRIVER INPUT
R: BUS RECEIVER OUTPUT
3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT SIGNAL NAMES
INCLUDE A "B" PREFIX.

DMA Request/Grant Timing

DATA

100 NS MAXIMUM

During the bus mastership acquisition phase, a DMA device requests the bus by
asserting SDMR L. The processor arbitrates the request and initiates the transfer
of bus mastership by asserting BDMGO L. The maximum time between BDMR L
assertion and BDMGO L assertion is DMA latency. This time is processor-dependent. BDMGO L/BDMGI L is one signal that is daisy-chained through each module
in the backplane. It is driven out of the processor on the BDMGO L pin, enters
each module on the BDMGI L pin, and exits on the BDMGO L pin. Propagation
delay from BDMGI L to BDMGO L must be less than 500 ns per LSI-11 bus slot.
Since this delay directly affects system performance, it should be kept as short as
possible. This signal passes through the modules in descending order of priority
until it is stopped by the requesting device. The requesting device blocks the
output of BMDGO L and asserts BSACK L if BRPLY Land BSYNC L are negated.
Propagation delay from BDMGI L to BSACK L must be less than 500 ns.
During the data transfer phase, the DMA device continues asserting BSACK L.
The actual data transfer is performed as described in the sections on DATI, DATO,
and DATIO.
NOTE

If multiple-data transfers are performed during this phase, consideration must be given to the use of the bus for other system functions,
such as memory refresh (if required).
The DMA device can assert BSYNC L for a data transfer no less than 250 ns after
it receives BDMGI L and its BSYNC Land BRPLY L become negated.
During the bus mastership relinquish phase the DMA device relinquishes the bus
by negating BSACK L. This occurs after completing (or aborting) the last data
transfer cycle (BRPLY L negated). BSACK L may be negated no more than 300 ns
before negating BSYNC L.

1150

INTERRUPTS
The interrupt capability of the LSI-11 bus allows any I/O device to temporarily
suspend (interrupt) current program execution and divert processor operation to
service the requesting device. The processor inputs a vector from the device to
start the service routine (handler). Like the device register address, hardware fixes
the device vector at locations within a designated range (below location 001000).
The vector is used as the first of a pair of contiguous addresses. The content of
the first address is read by the processor and is the starting address of the
interrupt handler. The content of the second address is a new processor status
word (PS). The new PS can raise the interrupt priority level, thereby preventing
lower level interrupts from breaking into the. current interrupt service routine.
Control is returned to the interrupt program when the interrupt handler is ended.
The original (interrupted) program's address (PC) and its associated PS are stored
on a stack. The original PC and PS are restored by a return from interrupt (RTI or
RTT) instruction at the end of the handler. The use of the stack and the LSI-11 bus
interrupt scheme can allow interrupts to occur within interrupts (nested interrupts),
depending on the PS.

Interrupts can be caused by LSI-11 bus options. Interrupt operations can also
originate from within the processor. These interrupts are called traps. Traps are
caused by programming errors, hardware errors, special instructions, and maintenance features.
The LSI-11 bus signals that are used in interrupt transactions are as follows:
BIR04 L
BIR05 L
BIR06 L
BIRO? L
BIAKI L
BIAKO L
BDAL<15:00> L
BDIN L
BRPLY L

Interrupt request priority level 4
Interrupt request priority level 5
Interrupt request priority level 6
Interrupt request priority level?
Interrupt acknowledge input
Interrupt acknowledge output
Data/address lines
Data input strobe
Reply

There are two classes of LSI-11 CPUs. One, the 11/03 CPU class, treats all
interrupts as level 4. The other, the 11/23 CPU class, can distinguish between the
four interrupt levels.
Device Priority
The LSI-11 bus supports the following two methods of device priority:
Distribution arbitration - Priority arbitration is implemented in logic on the
interrupting device based on request priority information on the bus. When
devices of equal priority level request an interrupt, priority is given to the
device electrically closest to the processor.

1151

Position-defined arbitration - Priority is determined solely by electrical position on the bus. The closer a device is to the processor, the higher its priority
is.
Interrupt Protocol
Interrupt protocol has three phases: interrupt request phase, interrupt acknowledge and priority arbitration phase, and interrupt vector transfer phase.

DEVICE

PROCESSOR

-------- ---- --

INITIATE REQUEST
__ • ASSERT BIRO L

....--

STROBE INTERRUPTS
• ASSERT BDIN L

I
I

GRANT REQUEST
• PAUSE AND ASSERT BIAKD L

------- ----

RECEIVE BDIN L
• STORE "INTERRUPT SENDING"
IN DEVICE

RECEIVE BIAKI L
• RECEIVE BIAKI L AND INHIBIT
BIAKD L
• PLACE VECTOR ON BDAL < 15;00 > L
• ASSERT BRPLY L

_ _ .....__-. NEGATEBIRQL

RECEIVE VECTOR & TERMINATE
REQUEST
• INPUT VECTOR ADDRESS
• NEGATE BDIN LAND BIAKO L

PROCESS THE INTERRUPT
• SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK
• LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION
• EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE

-.....--

----------- ---

-----

.....--

COMPLETE VECTOR TRANSFER
• REMOVE VECTOR FROM BDAL BUS
.....___. NEGATEBRPLYL

Interrupt Request/Acknowledge Sequence

1152

--+f
I

INTERRUPT LATENCY
MINUS SERVICE TIME

T IRQ

R DIN

R IAKI

T RPLY

------------12-5-N-S-M-A-X-IM-UM-~~f

T DAL

(4)

R SYNC

IUNASSERTED)

0'1

Co)

R BS7

IUNASSERTED)
NDTES,
1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER INPUTS
AND BUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW,
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT
3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT SIGNAL NAMES
INCLUDE A "B" PREFIX.
4. DON'T CARE CONDITION.

Interrupt Protocol Timing

j
VECTDR

r-lOO NS MAXIMUM

x=;--

The. interrupt request phase begins when a device meets its specific conditions for
interrupt requests. For exarnpie, the device is ready, done, or an error has
occurred. The interrupt enable bit in a device status register must be set. The
device then initiates the interrupt by asserting the interrupt request line(s). BIR04
L is the lowest hardware priority level and is asserted for all interrupt requests for
compatibility with previous LSI-11 processors. The level a device is configured at
must also be asserted. A special case exists for level 7 devices which must also
assert level 6. See item 2 of the arbitration discussion involving the 4-level scheme
(below) for an explanation.

Interrupt Level

Lines Asserted by Device

BIR04 L
BIR04 L, BIR05 L
BIR04 L, BIR06 L
BIR04 L, BIR06 L, BIR07 L

5
6
7

The interrupt request line remains asserted until the request is acknowledged.
During the interrupt acknowledge and priority arbitration phase the processor will
acknowledge interrupts under the following conditions:
On the 11/03 class processors, the PS bit 7 is cleared. On 11/23 class
processors, the device interrupt priority is higher than the PS<07:05>
The processor has completed instruction execution and no additional bus
cycles are pending.
The processor acknowledges the interrupt request by asserting BDIN L, and no
less than 225 ns later asserting BIAKO L. The device electrically closest to the
processor receives the acknowledge on its BIAKI L bus receiver.
At this point, the two types of arbitration must be discussed separately. If the
device that receives the acknowledge uses the 4-level (distributed) interrupt
scheme, it reacts as described below:
1.

If not requesting an interrupt, the device asserts BIAKO L and the acknowledge propagates to the next device on the bus.

If the device is requesting an interrupt it must check to see that no higher
level device is currently requesting an interrupt. This is done by monitoring
higher level request lines. The table below lists the lines that need to be
monitored by devices at each priority level.

In addition to asserting levels 4 and 7, level 7 devices must drive level 6. This
is done to simplify the monitoring and arbitration by level 4 and 5 devices. In

1154

this protocol, level 4 and 5 devices need not monitor level 7, since level 7
devices assert level 6. Level 4 and 5 devices will become aware of a level 7
request since they monitor the level 6 request.

Device Priority Level

Line(s) Monitored

4
5
6
7

BIR05, BIR06
BIR06
BIR07

If no higher level device is requesting an interrupt, the acknowledge is
blocked by the device (BIAKO L is not asserted). Arbitration logic within the
device uses the leading edge of BDIN L to clock a flip-flop that blocks BIAKO
L. Arbitration is won and the interrupt vector transfer phase begins.

If a higher level request line is active, the device disqualifies itself and asserts
BIAKO L to propagate the acknowledge to the next device along the bus.

Signal timing must be carefully considered when implementing 4-level interrupts.
Refer to the previous figure for interrupt protocol timing.
If a single-level interrupt (position defined) device receives the acknowledge, it
reacts as follows:
1.

If not requesting an interrupt, the device asserts BIAKO L and the acknowledge propagates to the next device on the bus.

If the device was requesting an interrupt, the acknowledge is blocked using
the leading edge of BDIN L and arbitration is won. The interrupt vector
transfer phase begins.

The interrupt vector transfer phase is enabled by BDIN Land BIAKI L. The device
responds by asserting BRPLY L and its BDAL<15:00> L bus driver inputs with the
vector address bits. The BDAL bus driver inputs must be stable no more than 125
ns after BRPL Y L is asserted. The processor then inputs the vector address and
negates BDIN Land BIAKO L. The device then negates BRPL Y L and no more
than 100 ns later removes the vector address bits. The processor then enters the
device's service routine.
NOTE
Propagation delay from BIAKI L to BIAKO L must be no greater than
500 ns per LSI-11 bus slot.
The device must assert BRPL Y L no more than 10 microseconds after
BIAKI L is asserted at the input to the module. Since the magnitude of

1155

both these times directly affects system performance, they should be
kept as short as possible. Typical DIGITAL designs have less than 55
ns propagation delay from BIAKI L to BIAKO L.
4-Levellnterrupt Configurations (LSI-11/21)
Users who have high-speed peripherals and desire better software performance
can use the 4-level interrupt scheme. Both position-independent and positiondependent configurations can be used with the 4-level interrupt scheme.
The position-independent configuration is shown below. This allows peripheral
devices that use the 4-level interrupt scheme to be placed in the backplane in any
order. These devices must send out interrupt requests and monitor higher level
request lines as described above. The level 4 request is always asserted by a
requesting device regardless of priority, to allow compatibility if an LSI-11/2 or
LSI-11 processor is in the same system. If two or more devices of equally high
priority request an interrupt, the device physically closest to the processor will win
arbitration.

KDJl1

BIAK (INTERRUPT ACKNOWLEDGE)

BIRQ4 (LEVEL4INTERAUPT REQUEST)
BIR05 (LEVEl5 INTERRUPT REQUEST)
BI RQ 6 (LEVE l 6 INTE R RUPT REQUEST)
BIRO 7 (lEVEL 7 INTERRUPT REQUEST)

Position-Independent Configuration (LSI-11/23)

KDJ11

BIAK (INTERRUPT ACKNOWLEDGE)

BI RQ 4 (LEVEL 4 INTERRUPT REQUEST)
Bt RQ 5 (LEVE L 5 INTE R RUPT REQUEST)
BIRO 6 (LEVEL 6 INTERRUPT REQUEST)
BIRO 7 (LEVEL 7 INTERRUPT REQUEST)

Position-Dependent Configuration (LSI-11/23)
The position-dependent configuration is shown above. This configuration is simpler to implement. A constraint is that peripheral devices must be inserted with the
highest priority device located closest to the processor and the remaining devices
placed in the backplane in decreasing order of priority, with the lowest priority
devices farthest from the processor. With this configuration, each device only has
to assert its own level and level 4 (for compatibility with an LSI-11 or LSI-11/2).
Monitoring higher level request lines is unnecessary. Arbitration is achieved
through the physical positioning of each device on the bus. Devices which use the
pOSition dependent scheme must be placed on the bus behind all position independent devices and in order of decreasing priority.
1156

CONTROL FUNCTIONS

The following LSI-11 bus signals provide control functions.
BREF L
BHALT L
BINIT L
BPOK H
BDCOK H

Memory refresh
Processor halt
Initialize
Power OK
DC power OK

Memory Refresh
If BREF is asserted during the address portion of a bus data transfer cycle, it
causes all dynamic MOS memories to be simultaneously addressed. The
sequence of addresses required for refreshing the memories is determined by the
specific requirements for each memory. The complete memory refresh cycle consists of a series of refresh bus transactions. A new address is used for each
transaction. The effect of multiple data transfers by DMA devices must be carefully
considered since they could delay memory refresh cycles.
Halt
Assertion of BHALT L stops program execution and forces the processor unconditionally into console ODT mode.
Initialization
Devices along the bus are initialized when BINIT L is asserted. The processor can
assert BINIT L as a result of executing a RESET instruction or as part of a powerup sequence. BINIT L is asserted for approximately 10 I-IS when RESET is
executed.
Power Status
Power status protocol is controlled by two signals, BPOK Hand BDCOK H. These
signals are driven by some external device (usually the power supply) and are
defined as follows.
BOCOK H

The assertion of this line indicates that dc power has been stable for at least 3 ms.
The negation of this line indicates that only 5 I-IS of dc power reserve remains.
Once BOCOK H is negated it must remain in this state for at least 1 I-IS before
being asserted again. BOCOK H may be pulsed low for a minimum of 1 I-IS to
cause the CPU to restart.
BPOK H

The assertion of this line indicates that there is at least an 8 ms reserve of dc
power and that BOCOK H has been asserted for at least 70 ms. Once BPOK H has
been asserted, it must remain asserted for at least 3 ms. The negation of this line
indicates that power is failing and that only 4 ms of dc power reserve remains.

1157

Power-Up/Down Protocol

Power-up protocol begins when the power supply applies power with BOCOK H
negated. This forces the processor to assert BINIT L. When the dc voltages are
stable, the power supply or other external device asserts BOCOK H. The power
supply asserts BPOK H no less than 70 ms after BOCOK H is asserted. The
processor then performs its power-up sequence. Normal power must be maintained at least 3 ms before a power-down sequence can begin.
A power-down sequence begins when the power supply negates BPOK H. The
current bus master, if not the processor, should relinquish the bus as soon as
possible (maximum 1 ms). When the current instruction is completed, the processor traps to a power-down routine. The processor traps to location 248 which
contains the PC that pOints to the power-down routine. The end of the routine is
terminated with a HALT instruction to avoid any possible memory corruption as
the dc voltages decay. The power fail routine has 4 ms to execute and HALT from
the time BPOK L is negated.

1158

BINIT L

B POK H

BDCOK H

01
CO

DC POWER

.1.

~~~~~~gtN

NOTE:
ONCE A POWER-DOWN SEOUENCE IS STARTED,
IT MUST BE COMPLETED BEFORE A POWER-UP
SEOUENCE IS STARTED.

Power-UpfPower-Down Timing

-I.

POWER-UP
SEQUENCE

NORMAL
POWER

BUS ELECTRICAL CHARACTERISTICS

This section contains information about the electrical characteristics of the LSI-11
bus.
AC Load Definition

AC load is a unit of measure of capacitance between a signal line and ground, as
specified below. A unit load is defined as 9.35 pF of capacitance.
DC Load Definition

DC load is a unit of measure of the dc current flowing in a signal line. A unit load is
defined as 105 IJ.A flowing into a device when the signal line is in the high state.
120 Ohm LSI-11 Bus

The electrical conductors interconnecting the bus device slots are treated as
transmission lines. A uniform transmission line, terminated in its characteristic
impedance, will propagate an electrical signal without reflections. Insofar as bus
drivers, receivers and wiring connected to the bus have finite resistance and
nonzero reactance, the transmission line impedance becomes nonuniform, and
thus introduces distortions into pulses propagated along it. Passive components
of the LSI-11 bus (such as wiring, cabling and etched signal conductors) are
designed to have a nominal characteristic impedance of 120 ohms.
The maximum length of interconnecting cable, excluding wiring within the backplane, is limited to 4.88 m (16 tt).
Bus Drivers

Devices driving the 120 ohm LSI-11 bus must have open collector outputs and
meet the following specifications.
DC Specifications
Output low voltage when sinking 70 mA of current: 0.7 V maximum
Output high leakage current when connected to 3.8 Vdc: 25 IJ.A (even if no
power is applied to them, except for BDCOK Hand BPOK H)
These conditions must be met at worst-case supply voltage, temperature,
and input signal levels.
AC Specifications
Bus driver output pin capacitive load: Not to exceed 10 pF
Propagation delay: Not to exceed 35 ns

1160

Skew (difference in propagation time between slowest and fastest gate): Not
to exceed 25 ns
Rise/Fall Times: Transition time from 10 percent to 90 percent for positive
transition, and from 90 percent to 10 percent for negative transition, must be
no faster than 10 ns and no slower than 1 /.Is.
Bus Receivers

Devices that receive signals from the 120 ohm LSI-11 bus must meet the following
requirements.
DC Specifications
Input low voltage (maximum): 1.3 V
Input high voltage (minimum): 1.7 V
Maximum input current when connected to 3.8 Vdc: 80 /.IA even if no power is
applied to them.
These specifications must be met at worst-case supply voltage, temperature,
and output signal conditions.
AC Specifications
Bus receiver input pin capacitance load: Not to exceed 10 pF
Propagation delay: Not to exceed 35 ns
Skew (difference in propagation time between slowest and fastest gate): Not
to exceed 25 ns
Bus Termination

The 120 ohm LSI-11 bus must be terminated at each end by an appropriate
terminator. This is to be done as a voltage divider with its Thevenin equivalent
equal to 120 ohms and 3.4 V nominal. This type of termination is provided by an
REV11-A refresh/boot/terminator, or the BDV11-AA.
+5 V

+5 V

330n

17sn

383 n

120 n

250n

BUS LINE
TERMINATION

680n

Bus Line Terminations
1161

Each of the several LSI-11 bus lines (all signals whose mnemonics start with the
ietter 8) must see an equivalent network with the following characteristics at each
end of the bus.
Input impedance (with respect to ground): Z = 120 ohm ±10%.
Open circuit voltage: 3.4 Vdc +5%
Capacitance Load: Not to exceed 30 pF
NOTE
The resistive termination may be provided by the combination of two
modules (i.e., the processor module supplies 220 ohms to ground).
Both of these two terminators must be physically resident within the
same backplane.
Bus Interconnecting Wiring

This section contains the electrical characteristics of the bus transmission lines.
Backplane Wiring

The wiring that interconnects all device interface slots on the LSI-11 bus must
meet the following specifications:
1.

The conductors must be arranged such that each line exhibits a characteristic
impedance of 120 ohms (measured with respect to the bus common return).

Crosstalk between any two lines must be no greater than 5 percent. Note that
worst-case crosstalk is manifested by simultaneously driving all but one
signal line and measuring the effect on the undriven line.

DC resistance of signal path, as measured between near-end terminator and
far-end terminator module (including all intervening connectors, cables, backplane wiring, connector-module etch, etc.) must not exceed 2 ohms.

DC resistance of common return path, as measured between near-end terminator and far-end terminator module (including all intervening connectors,
cables, backplane wiring, connector-module etch, etc.) must not exceed an
equivalent of 2 ohms per signal path. Thus, the composite signal return path
dc resistance must not exceed 2 ohms divided by 40 bus lines, or 50 milliohms. Note that although this common return path is nominally at ground
potential, the conductance must be part of the bus wiring; the specified low
impedance return path must be provided by the bus wiring as distinguished
from common system or power ground path.

1162

Intra-Backplane Bus Wiring
The wiring that interconnects the bus connector slots within one contiguous backplane is part of the overall bus transmission line. Due to implementation constraints, the nominal characteristic impedance of 120 ohms may not be achievable.
Distributed wiring capacitance in excess of the amount required to achieve the
nominal 120 ohm impedance may not exceed 60 pF per signal line per backplane.
Power and Ground
Each bus interface slot has connector pins assigned for the following dc voltages.·

+5 Vdc - Three pins (4.5 A maximum per bus device slot)

+12 Vdc - Two pins (3.0 A maximum per bus device slot)
Ground - Eight pins (shared by power return and signal return).

NOTE
Power is not used between backplanes on any interconnecting bus
cables.

• The maximum allowable current per pin is 1.5 A. +5 Vdc must be regulated to
±5%; maximum ripple: 100 mV pp. +12 Vdc must be regulated to ±3%; maximum ripple: 200 mV pp.

1163

SYSTEM CONFIGURATIONS

LSI-11 bus systems can be divided into two types:
Systems containing one backplane
Systems containing multiple backplanes
Before configuring any system, three characteristics for each module in the system must be known. These characteristics include:
Power consumption - +5 Vdc and +12 Vdc current requirements.
AC bus loading - the amount of capacitance a module presents to a bus
signal line. AC loading is expressed in terms of ac loads where one ac load
equals 9.35 pF of capacitance.
DC bus loading - the amount of dc leakage current a module presents to a
bus signal when the line is high (undriven). DC loading is expressed in terms
of dc loads where one dc load equals 105 microamperes (nominal).
Power consumption, ac loading, and dc loading specifications for each module are
included in the Microcomputer Handbook Series.
NOTE
The ac and dc loads and the power consumption of the processor
module, terminator module, and backplane must be included in determining the total loading of a backplane.
Rules for Configuring Single Backplane Systems

The bus can accommodate modules that have up to a total of 20 ac loads
(total) before an additional termination is required. The processor has onboard termination for one end of the bus. If more than 20 ac loads are
included, the other end of the bus must be terminated with 120 ohms.

A single backplane, terminated bus can accommodate modules comprising
up to a total of 35 ac loads.

The bus can accommodate modules up to a total of 20 dc loads.

The bus signal lines on the backplane can be up to 35.6 cm (14 in) long.

1164

OPTIONAL
250l.l

120n

+
3.4 V

3.4 V
35 AC LOADS
20 DC LOADS

TERM

PROCESSOR

Single Backplane Configuration

Rules for Configuring Multiple Backplane Systems

Up to three backplanes may compose the system. The signal lines on each
backplane can be up to 25.4 cm (10 in) long.

Each backplane can accommodate modules that have up to a total of 20 ac
loads. Unused ac loads from one backplane may not be added to another
backplane. It is desirable to load backplanes equally, or with the highest ac
loads in the first and second backplanes.

DC loading of all modules in all backplanes cannot exceed a total of 20 loads.

Both ends of the bus must be terminated with 120 ohms. This means that the
first backplane must have an impedance of 120 ohms (obtained via the
processor 220 ohm terminations and a separate 220 ohm terminator), and the
last backplane must have a termination of 120 ohms.

The cables used to connect the backplanes should adhere to the following
rules.
a.

The cable(s) connecting the first two backplanes is 61 cm (2 tt) or
greater in length.

The cable(s) connecting the second backplane to the third backplane
is 22 cm (4 tt) longer or shorter than the cable(s) connecting the first
and second backplanes.

The combined length of both cables cannot exceed 4.88 m (16 tt).

The cables used must have a characteristic impedance of 120 ohms.

1165

I250U

+
3.4 V

20 AC LOADS MAX

PROCESSOR

ADDITIONAL
CABLES AND
BACKPLANE

20 AC LOADS MAX

"'1-0---- ~~~~~L~~~~I~!X ----.0.11

20 AC LOADS MAX
NOTES,
1. TWO CABLES (MAX) 4.BB M (16 FTI (MAX)
TOTAL LENGTH.
2.20 DC LOADS TOTAL (MAX).

Multiple Backplane Configuration

1166

Power Supply Loading
Total power requirements for each backplane can be determined by obtaining the
total power requirements for each module in the backplane. Obtain separate totals
for +5 V and +12 V power. Power requirements for each module are specified in
the Microcomputer Handbook Series.

When distributing power in multiple backplane systems, do not attempt to distribute power via the LSI-11 bus cables. Provide separate, appropriate power
wiring from each power supply to each backplane. Each power supply should be
capable of asserting BPOK Hand BOCOK H signals according to bus protocol;
this is required if automatic power fail/restart programs are implemented, or if
specific peripherals require an orderly power-down halt sequence. The proper use
of BPOK H and BOOK H signals is strongly recommended.
NOTE
Timing diagrams reference signals at driver inputs (eg. TSYNC) and
receiver outputs (eg. RSYNC). However, the accompanying text refers
to the signals names in their bus specific form (eg. BSYNC). The
relationship between the three signal names are shown below. Most
timing numbers indicated in the text are given with respect to the R
and T versions of the signals shown in the timing diagrams. In all
cases the timing diagrams are the overriding authority.

RSYNC

Signal Naming Conventions

1167

APPENDIX D
FCC INFORMATION

GENERAL

To meet Federal Communications Commission (FCC) and Verband Deutscher
Elektroteckniker (VDE) mission requirements, it is necessary to prevent excessive
electromagnetic interference from escaping from a computer systems enclosure.
DIGITAL has designed the LSI-11 cabinet kit system options to reduce interference by shielding cabinets and cables.
Grandfather Terms

Products produced before October 1, 1981 and which would normally fall into the
FCC verified category (commercial, industrial, and/or business use) were given
"Grandfather Status", which means that they could continue to be built and
labeled "untested" through September, 1983. Units built after September, 1983
must meet the applicable technical electromagnetic interference (EM I) limits of the
FCC regulations, and must be labeled as such.
Date of Manufacture

The date of manufacture for FCC purposes, is the date on which a product
completes its volume build, receives its identity and labels, and moves into the
finished goods category.
It is not necessary that all products be fully configured as they would be shipped in
order to comply with the date of manufacture (DOM) requirements.
For instance, if a PDP-11 /23 processor could be inventoried as a basic machine,
after October, 1983 additional communications options, memory and floating point
processor (FPP) might be added.
Exempt

Exempt means that when a computing device is intended for several end-user
applications, the device is exempt from part 15J testing/labeling/marketing rules.
There are no exemptions from general prohibitions against interfering with
licensed communications, both existing and proposed.
Mixed Systems

Individual products maintain their identity and FCC label status in a mixed system.
FCC rules applying to each individual product will apply.

1169

When DIGITAL sells a product or products which create a mixed system, either as
a sale or field add-on to another DIGITAL product, DIGITAL is responsible for the
ability for each DIGITAL Class A or B product involved to continue to apply.
Interconnection of DIGITAL products with non-DIGITAL products is the responsibility of the purchaser of the products.
Specific FCC Related Labels
Class B Certified

These labels are for use on products marketed for use in the home or in
residential areas.
Untested
These labels are used on "Grandfather" units. The use of these labels ends
30 September 1983, which is when production of all "Grandfather" products
must cease.
Class A Verified
These labels are used on products marketed for end use in industrial, commercial, and business applications.
Class B Verified
Can be used on the same types of products as above (Class A Verified), if the
product passed the stricter test limits of Class B.
FCC Module List

The FCC does not require labeling of subassemblies, modules, cables, etc. They
do require that manufacturers inform their customers of "the interference potential" of such products. The method used to determine this information at the point
of sale is to separate the products by generating a list for those which have
successfully been integrated into Class A or Class B products.

1170

\'¢i