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EK-MSV0P-UG-001

August 1981

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Document:	MSV11-P User Guide
Order Number:	EK-MSV0P-UG
Revision:	001
Pages:	55
Original Filename:	EK-MSV0P-UG-001_MSV11P_Aug81.pdf

OCR Text

EK-MSVOP-UG-001

MSV11-P
User Guide·

EK- MSVOP-UG-001

MSV11- P User Guide

Prepared by Education Services
of
Digital Equipment Corporation

1 st Edition, August 1981

The reproduction of this material, in part or whole, is strictly prohibited. For copy
information, contact the Educational Services Department, Digital Equipment
Corporation, Maynard, Massachusetts 01754.
The information in this document is subject to change without notice. Digital Equipment
Corporation assumes no responsibility for any errors that may appear in this document.

Printed in U.S.A.

The following are
Massach usetts.

DEC
DECUS
DIGITAL
Digital Logo
PDP
UNIBUS
VAX

trademarks

Digital

DECnet
DECsystem-10
oECSYSTE M-20
DECwriter
DIBOL
EduSystem
lAS
MASSBUS

Equipment

Corporation,

OMNIBUS
OS/8
PDT
RSTS
RSX
VMS

Maynard,

CONTENTS

CHAPTER 1

CHARACTERISTICS AND SPECIFICATIONS

1.1
Introduction ....................................................
1.2
General Description ............................................
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
1.3.1
Functional Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2.1
Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2.2
Power Requirements .....................................
1.3.3
Environmental Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.3.1
Temperature .............................................
1.3.3.2
Relative Humidity ........................................
1.3.3.3
Operating Airflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.3.4
Altitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.4
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.5
Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.6
Backplane Pin Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Related Documents ............................................

CHAPTER 2

1
1
2
2
2
3
3
3
4
4
4
6
6
6
6
7

INSTALLATION

General ........................................................ 9
2.1
2.2
Wire Wrap Guidelines .......................................... 9
2.3
Configuring the MSV11-P ...................................... 10
Configuring the Module Starting Address ................... 10
2.3.1
2.3.1.1
Determining Starting Address ............................ 10
Determining Pins to be Jumpered ........................ 10
2.3.1.2
2.3.1.3
Wire Wrap Pins for the Starting Address .................. 14
Control and Status Register ................................. 14
2.3.2
Power Jumpers .............................................. 16
2.3.3
Bus Grant Continuity Jumpers ............................... 16
2.3.4
General Jumpers ............................................ 16
2.3.5

CHAPTER 3
3.1
3.2
3.2.1

FUNCTIONAL DESCRIPTION

Introduction ..... ~ .............................................. 21
LSI-11 Bus Signals and Definitions ............................. 22
LSI-11 Bus Dialogues ....................................... 24

iii

CONTENTS

Functional Description of Memory Module ..................... 30
3.3
Xcvers (Transmit-Receives) .................................. 30
3.3.1
Address Logic ............................................... 30
3.3.2
Board Selection Decode Logic ........................... 30
3.3.2.1
MOS Memory Address Logic ............................. 32
3.3.2.2
CSR Address Logic ....................................... 32
3.3.2.3
CSR Write ................................................... 32
3.3.3
CSR Read ................................................... 34
3.3.4
Memory Array ............................................... 34
3.3.5
Timing and Control Logic .................................... 35
3.3.6
Parity Logic ................................................. 37
3.3.7
Parity Generation ........................................ 37
3.3.7.1
Parity Checker ........................................... 38
3.3.7.2
Refresh
...................................................... 38
3.3.8
Charge Pump Circuit ........................................ 40
3.3.9
Control and Status Register (CSR) Bit Assignment ............. 40
3.4
CHAPTER 4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3

MAINTENANCE

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43
Preventive Maintenance ........................................ 43
\/iC:II!:41
•. ____ In.c:nAr.tinn
11._,- __ "'_'. a_ . . . . . . . . . . . . ____
; _; ;
"'" '"""" 43
Power Voltage Check ....................................... 43
Diagnostic Testing .......................................... 44
DIGITAL's Services ............................................. 44
~

APPENDIX A

= ;;

SIGNAL SEQUENCES

FIGURES
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-1 3
3-14

Memory Board ................................................. 11
Triple Voltage MOS RAM with Battery Backup .................. 17
Triple Voltage MOS RAM without Battery Backup .............. 17
Single Voltage MOS RAM without Battery Backup .............. 18
Single Voltage MOS RAM with Battery Backup. . . . . . . . . . . . . . . .. 18
Typical System ................................................. 21
MSV11-P Memory Interface .................................... 22
Dialogue DATO(B) .............................................. 25
Dialogue DATI .................................................. 26
Dialogue DATIO(B) ............................................. 28
Logic Functions ................................................ 31
Overview of Memory Logic .......... ;.......................... 33
CSR Write .................................. . . . . . . . . . . . . . . . . . . .. 34
CSR Read ...................................................... 35
64K MOS RAM Chip ............................................ 36
16K MOS Chip ................................................. 36
Timing and Control ............................................. 37
Parity Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 38
Parity Checkers ................................................ 39

CONTENTS

3-15
3-16
A-1
A-2
A-3
A-4

Refresh Logic and Charge Pump Circuit ........................ 39
CSR Bit Allocation .............................................. 40
Memory Operation Cycle ....................................... 46
DATO(B) Signal Sequence ...................................... 47
DATI Signal Sequence .......................................... 47
DATIO(B) Signal Sequence ..................................... 48

TABLES
1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
2-4
2-5
2-6
3-1
3-2
3-3
3-4
3':5
3-6
3-7
4-1

MSV11-P Versions ............................................. 1
Access and Cycle Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Multi/Single Voltage MOS RAM ................................ 4
MSV11-P Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Backplane Pin Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MSV11-P Jumper Check List ................................... 12
Starting Address Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13
CSR Address Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15
Power Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16
Bus Grant Continuity ........................................... 19
General Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19
Summary of Bus Cycles ........................................ 21
LSI-11 Bus Signals and Definitions ............................. 22
Dialogues to Perform Memory Data Transfers .................. 24
Dialogue DATO(B) Cycle ........................................ 25
Dialogue DATI .................................................. 27
Dialogue DATIO(B) Cycle ....................................... 28
PROM Output for M8067-LA (Starting Address Zero) ........... 31
Voltage Margins ................................................ 44

CHAPTER 1
CHARACTERISTICS
AND SPECIFICATIONS

1. 1 INTRODUCTION
This manual describes the MSV 11-P family of memory modules. The
MSV 11-P memory modules are metal oxide semiconducters (MOS), random access memory (RAM). They are designed to be used with the LSI-11
bus. The MSV 11-P provides storage for 18-bit words (16 data bits and 2
parity bits) and also contains parity control circuitry and a control and status register (CSR). There are three versions of the MSV 11-P memory
modules as shown in Table 1-1.

Table 1-1

MSV11-P Versions

MaS

Option
Designation

Module
Designation

Storage
Capacity

MSV11-PL
MSV11-PK
MSV11-PF

M8067-LA
M8067-KA
M8067-FA

256K words by 18 bit 64K
128K words by 18 bit 64K
64K words by 18 bit 16K

Chips

Module
Population

Number
of
Rows

Full
Half
Full

8
4
8

1.2 GENERAL DESCRIPTION
The MSV 11-P memory module consists of a single, quad-height module
(M8067) that contains the LSI-11 bus interface, timing and control logic,
refresh circuitry, and a MOS storage array. The module also contains circuitry to generate and check parity, and a control and status register.
The memory module's starting address can be set on any 8K boundry
within the 2048K LSI-11 address space or 128K LSI-11 address space.
The MSV 11-P allows the top 4K of the LSI-11 address space to be reserved for the I/O peripheral page. Note that there is no address interleaving with the MSV 11-P.
The memory storage elements are 16,384 by 1 bit, MOS dynamic RAM devices or 65,536 by 1 bit MOS dynamic RAM devices. The MOS storage
array contains 18 of these devices for every 16K rows of memory or 64k
rows of memory. Unlike core memory, the read operation for MOS storage
devices is nondestructive; consequently the write-after-read operation
associated with core memory is eliminated. The MOS storage devices
must be refreshed every 14.5 jlS so that the data remains valid.

CHARACTERISTICS AND SPECIFICATIONS

The MSV 11-PF memory uses + 5 V, + 12 V and - 5 V. The positive voltages are received from the backplane and the negative voltage is generated from a charge pump circuit on the board. The MSV 11-PL and MSV 11PK require +5 V, which is received from the backplane.
There is a green LED on the module that stays on as long as + 5 V power
is supplied to the logic required for memory refresh, read/write request,
arbitration, and row and column addressing.
The control and status register in the MSV 11-P contains bits that are used
to store the parity error address bits. By setting a bit in the GSR you can
force wrong parity. This is a useful diagnostic tool for checking out the
parity logic. The GSR has its own address in the top 4K of memory. Bus
masters can read or write to the GSR.
The parity control circuitry in the MSV 11-P generates parity bits based on
data being written into memory during a DATO or DATOB bus cycle. One
parity bit is assigned to each data byte and is stored with the data in the
MOS storage array. When data is retrieved from memory during DATI or
DATIO bus cycles, the parity of the data is determined. If parity is good,
the data is assumed correct. If the parity bits do not correspond, the data
is assumed unreliable and memory initiates the follm,lJing action.
1. A red LED on the module lights. This provides a visual indication of a
parity error and sets GSR bit 15.
2. If bit 0 in the GSR is set, the memory asserts BDAL 16 and 17. This
warns the processor that a parity error has occurred.
3. Part of the address of the faulty data is recorded in the GSR.

1.3 SPECIFICATIONS
This section of the manual gives functional, electrical, and environmental
specifications and backplane pin utilization information.
1.3. 1 Functional Specifications
Table 1-2 provides MSV 11-P functional specifications.
1.3.2 Electrical Specifications
The electrical specifications state the voltage and power requirements for
the MSV11-P.
No adjustment or maintenance is required. Two LEOs are used to indicate
board status. A green LED indicates that + 5 V GR is present on the
board. This is useful on battery backed up systems where the boards
could be removed from the backplane with only +5 V shut off. A red LED
indicates the detection of a parity error.

CHARACTERISTICS AND SPECIFICATIONS

Table 1·2 Access and Cycle Times*
Cycle Timet

Access Timet
Bus
Cycles

Measure
Typical

Maximum

Notes

DATI
DATO(B)
DATIO(B)
REFRESH

240
90
660

260
120
690

2
2
3

Measure
Typical

Maximum

Notes

560
610
1175
640

590
640
1210
690

4
5
6
7

* Parity - CSR configurations, refer to notes 1, 8, and 9.
t Tacc (ns)
:j: Tcyc (ns)

NOTE 1: Assuming memory not busy and no arbitration.
NOTE 2: SYNCH to RPL YH with minimum times (25/50 ns) from SYNCH to (DINH/DOUTH).
The DATO(B) access and cycle times assume a minimum 50 ns from SYNCH to DOUTH inside
memory receivers. For actual LSI-11 bus measurements, a constant (K-50 ns) where K = 200
ns should be added to DATO(B) times, i.e., Tacc (Typical) = 90 + (200 - 50) = 240 ns.
NOTE 3: SYNCH to RPLYH [DATO(B)] with minimum time (25 ns) from SYNCH to DINH and
minimum (350 ns) from RPL YH (DA TI) asserted to DOUT asserted.
NOTE 4:

SYNCH to TlM250H negated.

NOTE 5:

SYNCH to TlM250H negated with minimum time (50 ns) from SYNCH to DOUTH.

NOTE 6: SYNCH to TlM250H [DATO(B)] with minimum times (25 ns) from SYNCH to DINH
and minimum (350 ns) from RPL YH (DA TI) asserted to DOUT asserted.
NOTE 7:

REF REO L to TlM250H negated.

NOTE 8:

REFRESH arbitration adds (90 ns) typical and (110 ns) maximum to access.

NOTE 9:
times.

REFRESH conflict adds (640 ns) typical and (690 ns) maximum to access and cycle

1.3.2.1 Voltages - The MSV11-PF memory modules require +5 V, +12 V,
and -5 V for the multivoltage MOS RAMs. The -5 V is generated from the
memory module. Single voltage MOS RAMs (MSV11-PK/PL) require only +5
V. Voltage margins for the +5 V and +12 V are ±5 percent (Table 1-3).
NOTE:
trol.

Latest MSI available and in use at DIGITAL will be used for con-

1.3.2.2 Power Requirements - Power requirements are provided in
Table 1-4.
1.3.3 Environmental Specifications
Environmental specifications cover storage and operating temperature,
relative humidity, altitude, and air flow specifications.

CHARACTERISTICS AND SPECIFICATIONS

Table 1-3

Multi/Single Voltage MOS RAM

Multivoltage MOS RAMs (MSV11-PF)

Non Battery
Backed Up

Battery
Backed Up

Voltage

Pins

Service

+5V
+12 V

AA2, BA2, BV1,CA2
AD2,BD2

TTL and MOS RAMs
MOS RAMs

+5 V

AA2, BA2, BV1,CA2

MOS RAMs and
noncritical TTL

+5 V BBU
+12 V BBU

AV1, AE1
AS1

Critical TTL
MOS RAMs

Single Voltage MOS RAMs (MSV11-PK/PL)
Voltage

Pins

Service

Non Battery
Backed Up

+5 V
+5 V (VDD)

AA2, BA2, BV1,CA2
DA2

TTL
MOS RAMs*

Battery
Backed Up

+5 V

AA2, BA2, BV1,CA2

noncritical TTL

+5 V

AV1, AE1

Critical TTL
and MOS RAMs

* For systems without +5 Von DA2, +5 V can be supplied from AA2, BA2, BV1,
and CA2.

1.3.3.1
groups.

Temperature - Temperature is separated into the following two

1. Operating Temperature Range - The operating temperature range is
+5 0 C to +60 0 C. Lower the maximum operating temperature by 1 0
C for every 1000 feet of altitude above 8000 feet.
2. Storage Temperature Range - The storage temperature range is
-40 0 C to +66 0 C. Do not operate a module that has been stored
outside the operating temperature range. Bring the module to an environment within the operating range and allow at least five minutes
for the module to stabilize.

1.3.3.2 Relative Humidity - The relative humidity for the MSV 11-P
memory modules must be 10 percent to 90 percent noncondensing for
storage or operating conditions.
1.3.3.3 Operating Airflow - Adequate airflow must be provided to limit
the inlet to outlet temperature rise across the module to 50 C when the
inlet temperature is +60 0 C. For operation below +55 0 C, airflow must
be provided to limit the inlet to outlet temperature rise across the module
to 10 0 C maximum.

CHARACTERISTICS AND SPECIFICATIONS

Table 1-4

MSV11-P Power

MSV11-PF (Multivoltage MOS RAMs)

Voltage

Standby Current (A)
Meas Typ
Max

+5 V Noncritical
+5 V BBU
Total +5 V
+12 V

1.40
1.15
2.55
0.10

Voltage

Standby Power (W)
Meas Typ
Max

+5 V Noncritical
+5 V BBU
Total +5 V
+12 V
Total Power

7.00
5.75
12.75
1.20
13.95

2.21
1.55
3.76
0.12

11.60
8.14
19.74
1.51
21.25

Active Current (A)
Meas Typ
Max
1.45
1.20
2.65
0.35

2.21
1.55
3.76
0.53

Active Power (W)
Meas Typ
Max
7.25
6.00
13.25
4.20
17.45

11.60
8.14
19.74
6.68
26.42

MSV11-PK (Single Voltage, Half Populated)

Voltage

Standby Current (A)
Meas Typ
Max

+5 V Noncritical
+5 V BBU
Total +5 V

1.65
1.35
3.00

Voltage

Standby Power (W)
Meas Typ
Max
(5.0)
(5.25)

+5 V Noncritical
+5 V BBU
Total Power

8.25
6.75
15.0

Active Current (A)
Meas Typ
Max

2.10
1.80

1.70
1.75

2.10
2.10

3.90

3.45

4.20

11.00
9.45
20.45

Active Power (W)
Meas Typ
Max
(5.0)
(5.25)
8.50
8.75
17.25

11.0
11.0
22.0

MSV11-PL (Single Voltage, Fully Populated)

Voltage

Standby Current (A)
Meas Typ
Max

Active Current (A)
Meas Typ
Max

+5 V Noncritical
+5 V BBU
Total +5 V

1.65
1.45
3.10

2.10
1.90

1.70
1.85

2.10
2.20

4.0

3.60

4.30

Voltage

Standby Power (W)
Meas Typ
Max
(5.0)
(5.25)

+5 V Noncritical
+5 V BBU
Total +5 V

8.25
7.25
15.5

8.50
9.25
17.75

11.0
10.0
21.0

11.00
11.55
22.55

NOTE: Typical power calculations are done at nominal voltages. Maximum power calculations are done with maximum currents at the highest
voltage (nominal +5 percent).

CHARACTERISTICS AND SPECIFICATIONS

1.3.3.4

Altitude - The module resists mechanical or electrical damage
at altitudes up to 50,000 feet (90 MM mercury) under storage or operating
conditions.
NOTE: Lower the maximum operating temperature by 1 0 C for every
1000 feet of altitude above 8000 feet.

1.3.4 Refresh
The MSV 11-P memory module uses a self-contained refresh rate that is
typically 650 ns every 14,500 ns. The refresh overhead maximum is 685
nsf 13,500 ns or about 5 percent.
1.3.5

Diagnostics
The diagnostics are CVMSAA (22-bit system) and CZKMAA (18-bit system).

1.3.6 Backplane Pin Utilization
MSV 11-P backplane pin utilization is shown in Table 1-5. Blank spaces indicate pins not used.

Table 1·5

Backplane Pin Utilization
B Connector

A Connector
Pin
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V

Side 1

BDAL16L
BDAL17L
+5 V BBU

GND
REFKILL
GND

BREF L
+12 V BBU
GND
SA16K§
+5 V BBU

Side 2

Side 1

Side 2

+5V

BDCOK H

+5V

GND
+12 V
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L

BDAL18L
BDAL19L
BDAL 20L
BDAL 21 L

B1AK1Lt
B1AKOL t
BBS7L
BDMG1 Lt
BDMGOLt
BINIT L
BDALOO L
BDAL01 L

GND
+12 V
BDAL 02L
BDAL 03L
BDAL 04L
GND
BDAL 05L
-5 V MEAS*
BDAL 06L
-5 V MARGIN* BDAL 07L
GND
BDAL 08L
BDAL 09L
BDAL10L
BDAL 11 L
BDAL12L
BDAL13L
GND
BDAL14L
BDAL15L
+5 V

C Connector

D Connector

Side 1 Side 2

+5 V

+5 V VDD

B1AK1L:t
B1 AKOL:t

BDMG1 L:t
BDMG1 L:t

* Must be hardwired on backplane or damage to MOS devices may result.
t Hardwired via etch on module.
:t Jumpered on module.
§ When SA16K (starting address 16K) jumper is removed, there is no connection to this pin (used in
memory test only).

CHARACTERISTICS AND SPECIFICATIONS

1.4 RELATED DOCUMENTS
Refer to the following documents for more information.
•
•
•
•

Field Maintenance Printset (MPO 1239)
Microcomputer and Memory Handbook (EB-18451-20)
Microcomputer Interface Handbook (EB-20 175-20)
LSI-11 System Service Manual (EK-LSI-FS-SV)·

These documents can be ordered from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
ATTN: Communications Services (NR2jM 15)
Customer Services Section

* Field Service Use Only

CHAPTER 2
INSTALLATION

2.1 GENERAL
This chapter contains information for configuring and installing the
MSV 11-P family of memory modules. This includes the M806? -LA, M806?KA, and M806?-FA.
The fully populated module, M806? -LA, has 512K bytes. The half populated module, M8G6? -KA, has 256K bytes. Both modules use 64K bit
chips. The M8G6?-FA module has 128K bytes of memory. This is a fully
populated module using 16K bit chips.
Installation includes the following procedures .
• Wire wrap guidelines
• Jumpers configuration
CAUTION
1. You must remove dc power from the backplane during module insertion or removal.
2.

You must install memories in sequential slots following the CPU.

3. Be careful when replacing the memory module. Make sure that the
component side of the module faces in the same direction as the other modules in the LSI-11 system. The memory module, backplane, or
both can be damaged if the module is installed backwards.
2.2 WIRE WRAP GUIDELINES
A pin can have no more than two wire wraps. The starting address and
control and status register (CSR) address pins may require two wire
wraps. Always follow this procedure to wire wrap these pins.
1. Find out how many pins must be wrapped.
2. Each wrap must be daisy chained to its own ground.
3. Always put lower wraps on the pins first and then the upper wraps.

INSTALLATION

2.3 CONFIGURING THE MSV11-P
The jumpers on the MSV 11-P memory module are divided into the following five groups.
•
•
•
•
•

Starting Address Jumpers
CSR Address Jumpers
Power Jumpers
Bus Grant Continuity Jumpers
General Jumpers

Figure 2-1 shows the location of the five jumper groups, four of which are
enclosed in solid boxes and labeled. The remaining jumpers are classified
as general jumpers. The general jumpers are enclosed in dotted boxes.
Table 2-1 shows all the jumpers and their function.

2.3. 1 Configuring the Module Starting Address
Each MSV 11-P memory module installed in a system is jumpered for its
own starting address. To configure the starting address, perform the following steps.
1. Determine the starting address.
2. Determine the pins to be jumpered for the starting address.
3. Wire wrap the pins for the starting address.

2.3. 1. 1 Determining Starting Address - The memory module starting
address can be found if you know how much memory the system has before the replacement module. Change the byte value (how much memory
the system has) to a word value. This word value is the module starting
address (MSA).

2.3. 1.2

Determining Pins to be Jumpered - Module starting address
jumpers consist of the following two groups:
1. First Address of the Range (FAR) - Selects the first 256K word
range address that the starting address falls in (Table 2-2, Part 1).
2. Partial Starting Address (PSA) - Selects which 8K boundry within a
specific multiple of 256K words the starting address falls in (Table 22, Part 2).
At this pOint you know your module starting address (MSA) and you must
find the FAR and PSA values. This is done in the following way.
1. Find the FAR value - This is done by looking at Table 2-2, Part 1 and
locating the address range the MSA falls in. The FAR value is the
first address of the selected address range. Associated with the FAR
value is a specific configuration of jumper pins (X, W, and V) that use
jumper pin Y (a ground pin).

INSTALLATION

M8067-LA
M8067-KA
ROW LATCH

i---;=-~31

r--i--04 I

L--09

L----o10 I

I
0
I
IL _____
0
---1I
COLUMN LATCH

1-----;:~141
I
r- I--015I

I L~161
l
I

I
I

L_~-=~~

16K MOS CHIPS
BITS

Rowa (

ROW1 {
BYTE

BITS

UDD880[][][]G]
UDD888DDDt]

M8067-FA
iTIM190-H
IL

ROW2 {

[IBD880[][][]G]

ROW3 {

Rowa {

ROW 1 {
BYTE
ROW2 {

~BGGGDB88
~BGGBDB0[]

:E.Y~-1

W3
W11
W13

JUMPERS
INHIBIT

VOroY

~----o 15 I

016 I

017 I

:~--n:
IL _
-= _
21 _23
22-1I
__

rR
-=- P
0

oM
o-L

Lir

[:B BGGB[J B 8 8
AO"'" 'UM""
[:B EJ EJ EJ EJ EJ EJ 0 0 "'-~W-4-V-DD--P-OW-ER-J-U-M-P-ER-S--~"""::"----'

GRANT CONTINUITY
W1 AND W2 IN FOR

16K MULTIPLE VOLTAGE DEVICES
NON-BAT BACK-UP

L __6 _7_ ~l

-= X 0

ROW3 {

T-0-11 [DALl6Hrl,- - -1

45
43_441
____
__
-l

18/22 BIT i-~~
SYSTEM rtl..,:;[=l=-;;'!--_...,STARTING ADDRESS

UD[J~80[][][]G]

WRITE WRONG
PARITY TESTING
PIN 6 TO 7

BITS

BAT BACKUP

VOLTAGES

W3
W10
W12

-5
+12 VDD
+5 CR

POWER JUMPERS FOR 16K MOS CHIPS
WITHOUT BATTERY BACKUP

010 MACHINE, Q22/Q22
MACHINE
W1 AND W2 OUT FOR
OICD AND Q22/CD MACHINE

_ _ _ _ POWER JUMPER IN FOR 64K CHIPS

-----CJ-- POWER JUMPER IN FOR 16K CHIPS
---.::J-- POWER JUMPER IN FOR BOTH 64Ki16K CHIPS

64K SINGLE VOLTAGE DEVICES
NON-BAT BACK-UP

BAT BACKUP

VOLTAGES

W4
W5
W9
W13IW15

W4
W5
W12
W14

DECOUPLE +5
DECOUPLE +5
+5 CR
+5 VDD

Figure 2-1

Memory Board

2. Find the PSA value - This is done by inserting the MSA and FAR values into the equation PSA = MSA - FAR. After you do the subtraction, find Table 2-2, Part 2 and locate the PSA value. Associated
with the PSA is a specific configuration of jumper pins (P, N, M, L,
and T) that use jumper pin R (a ground pin). Examples 1 and 2 show
how to use the equation to jumper a module.

INSTALLATION

Table 2-1

MSV11-P Jumper Check List

Jumper
Name
or Pin
to Pin

Jumper
In

6 to 7
3 to 7
2 to Y

43 to 44

Jumper
Out

Wire
Wrap

Solder

Check

Function

X
X
X

In - write wrong parity
In - disables wrong parity
2 to Y out - 22 bit machine
2 to Y in - 18 bit machine

Single voltage MOS RAM access time
(150 ns device)
Multiple voltage MOS RAM access
time (200 ns device)
Not used
Not used
F to H in - connected to force
starting address to 16 K
F to H out - disables force function

45 to 44

22 to 23
21 to 23
F to H

X
X
X

:3 to 9

13 to 15
4 to 10
14 to 16

X
X
X

3 to 9 in - connected on 16K and
64K MOS chip
Connected on 16K and 64K MOS chip
Connected only on 64K MOS chip
Connected only on 64K MOS chip

W3
'J'./11
W13

X
X
X

Power for 16K chips,
jumpers are in

W4
W5
W9
W13
W15

X
X
X
X
X

Power for 64K chips,
jumpers are in

W1
W2

X
X

Bus grant continuity

A
B
C

0
E

X
W
V
Y

P
N
M
L

T
R

X
X
X
X
X

CSR address

X
X
X
X
X
X
X
X
X

Starting address

INSTALLATION

Table 2·2

Starting Address Configurations (Part 1)

First Address Ranges (FAR)

Jumpers to Ground (Pin Y)

Decimal K Words

Octal K Words

Pin X
(A21)

PinW
(A20)

Pin V
(A19)

000 - 248
256 - 504
512-760
768 - 1016
1024-1272
1280 -1528
1526 -1784
1742 - 2040

0000 0000 - 01 74 0000
0200 0000 - 0374 0000
0400 0000 - 0574 0000
0600 0000 - 0774 0000
1000 0000 - 1174 0000
1 200 0000 - 1 374 0000
1400 0000 - 1574 0000
1 600 0000 - 1774 0000

out
out
out
out

out
out

out

in
in

out

in
in
in
in

out
out

out

in
in

out

Table 2·2

in
in
in
in

Starting Address Configurations (Part 2)

Partial Starting Address (PSA)

Jumpers to Ground (Pin R)

Decimal
K Words

Octal
K Words

Pin P
(A18)

Pin N
(A17)

Pin M
{A16}

Pin L
{A1S}

Pin T
(A14)

0000 0000
0004 0000
0010 0000
0014 0000
0020 0000
0024 0000
0030 0000
0034 0000

out
out
out
out
out
out
out
out

out
out
out
out

out
out

out

8
16
24
32
40
48
56

in
in

out

in
in
in
in

out
out

out

in
in

out

64
72
80
88
96
104
112
120

0040 0000
0044 0000
0050 0000
0054 0000
0060 0000
0064 0000
0070 0000
0074 0000

out
out
out
out
out
out
out
out

in
in
in
in
in
in
in
in

out
out
out
out

out
out

out

in
in

out

in
in
in
in

out
out

out

in
in

out

128
136
144
156
160
168
176
184

0100 0000
0104 0000
0110 0000
0114 0000
0120 0000
0124 0000
0130 0000
0134 0000

in
in
in
in
in
in
in
in

out
out
out
out
out
out
out
out

out
out
out
out

out
out

out

in
in

out

in
in
in
in

out
out

out

in
in

out

192
200
208
216
224
232
240
248

0140 0000
0144 0000
0150 0000
0154 0000
0160 0000
0164 0000
0170 0000
0174 0000

in
in
in
in
in
in
in
in

out
out
out
out

out
out

out

in
in

out

in
in
in
in

out
out

out

in
in

out

in
in
in
in
in
in
in
in
in
in
in
in
in
in
in
in

INSTALLATION

Example 1
The system has 512K bytes of memory. To jumper the memory module,
change this byte value (512K) to a word value (256K). This word value is
Galled the MSA.
Insert this value into the equation.
PSA = MSA - FAR
PSA = 256K - FAR
To find the value of FAR use Table 2-2, Part 1 to locate the address range
that the MSA value falls in. Take the first address of the address range
and insert it into the equation.
PSA = MSA - FAR
PSA = 256K - 256K
PSA = 0
Use Table 2-2, Part 1 - The FAR value equals 256K, this means wire wrap
pins V to Y.
Use Table 2-2, Part 2 - The PSA value equals OK, this means no wire
wraps on pins P, N, M, L, and T.
Example 2
The system has 672K bytes of memory. To jumper the memory module
change this byte value (672K) to a word value (336K). This word value is
called the MSA.
Insert this value into the equation.
PSA = MSA - FAR
PSA = 336K - FAR
PSA = 336K - 256K
PSA = 80K
Use Table 2-2, Part 1 - The FAR value equals 256K, this means wire wrap
pins V to Y.
Use Table 2-2, Part 2 - The PSA value equals 80K, this means wire wrap
pins L to Nand N to R.

2.3.1.3 Wire Wrap Pins for the Starting Address - Wire wrap the pins
according to the wire wrap procedures in Paragraph 2.2.
2.3.2 Control and Status Register (CSR) Jumpers
Each MSV 11-P memory module has a control and status register. The bus
master can read or write the CSR via the LSI-11 bus. The CSR is a 16-bit
register whose address falls in the top 4K of system address space.

INSTALLATION

Each MSV 11-P CSR is assigned to one of the 16 addresses shown in
Table 2-3. CSR addresses are assigned as follows.
1. Find out how many memory modules in your system have CSR registers.
2. List the memory modules sequential postion from the CPU.
3. The memory modules closest to the CPU have the lower module
starting address (MSA).
4. The memory module with the lowest MSA is assigned to the lowest
CSR address and jumpered according to Table 2-3.
5. The next sequential CSR memory module is assigned the next higher
CSR address.
Each memory module has four CSR jumper pins (A, B, C, and D) which can
be daisy chained to pin E (the ground pin). The jumpers allow logic to detect a specific CSR address that has been assigned to a CSR memory
module.
For example, assume the system has two memory modules with CSR registers. You are installing the third CSR memory. Refer to Table 2-3 and
find the column labeled module number three. The CSR jumper pin configuration is pin B wire wrapped to pin E. The memory module's CSR address is 17772104 for large systems or 772104 for small systems.

Table 2-3

Module
Number

2
3
4
5
6
7

8
9
10
11
12
13
14
15
16

CSR Address Selection
Large System
LSI-11 Bus
Address

Small System
LSI-11 Bus
Address

1777 2100
17772102
1777 2104
1777 2106
1777 2110
1777 2112
17772114
1777 2116
1777 2120
1777 2122
1777 2124
1777 2126
17772130
1777 2132
1777 2134
17772136

7721 00
7721 02
7721 04
7721 06
7721 10
7721 12
7721 14
7721 16
7721 20
7721 22
7721 24
7721 26
7721 30
7721 32
7721 34
7721 36

Jumper to Ground (Pin E)
A
B
0
C
out
out
out
out
out
out
out
out

out
out
out
out

out
out

out

in
in

out

in
in
in
in

out
out

out

in
in

out

in
in
in
in
in
in
in
in

out
out
out
out

out
out

out

in
in

out

in
in
in
in

out
out

out

in
in

out

in
in
in
in
in
in
in
in

INSTALLATION

2.3.3 Power Jumpers (Table 2-4)
The power jumpers are divided into the following two groups.
1. 16K multiple voltage devices (M8D67 -FA) with or without battery
backup
2. 64K single voltage devices (M8D67-LA and M8D67-KA) with or without battery backup
NOTE:

DIGITAL does not support battery backup.

Figure 2-1 shows all the possible power configurations. Figures 2-2
through 2-5 show the jumper conditions for 16K/64K devices (MOS memory chips), and the dual functions of pin 9, address or data.

2.3.4
Bus Grant Continuity Jumpers
To install W 1 and W2 in your system, identify the backplane and refer to
Table 2-5 for the W 1 and W2 configuration.
2.3.5 General Jumpers
The general jumper group is the catchall section. All jumpers and their
functions that have not yet been covered are described in Table 2-6.

Table 2-4

Power Jumpers

16K Multiple Voltage Devices
Non-bat Backup

Bat Backup

Voltages

W3
W11
W13

W3
W10
W12

+12 VDD
+5 CR

-5

64K Single Voltage Devices
Non-bat Backup

Bat Backup

Voltages

W4
W5
W9
W13/W15

W4
W5
W12
W14

Decouple +5
Decouple +5
+5 CR
+5 VDD

INSTALLATION

R38 OUT
---0

+5 CR

R39

AA8H
for Byte 0 ROM Chips

W13

R32 OUT

-----<>

R33
for Byte 1 ROM Chips
MA-71S2

Figure 2-2

Triple Voltage MOS RAM without Battery Backup

R38 OUT
---0

R39

AA8H
for byte 0 ROM Chips

R32 OUT

---<>

R33
for byte 1
MA-71S3

Figure 2-3

Triple Voltage MOS RAM with Battery Backup

INSTALLATION

R38
AA8H} FOR BYTE 0
ROM CHIPS

R39

0----

+5CR.

+5V
BA8 H~

R32

. ~FOR BYTE 1

O------j
R33
+5CR

ROM CHIPS

r-~-r--r--.--r--,-'+5VCR

+5V
GREEN LED
1.--_ _- ._ _ _ _---._ _ _ _- . - .

Figure 2-4

+5V

Single Voltage MOS RAM without Battery Backup

R38
AA8H} FOR BYTE 0
R39
R32.
.----'---0

R33

ROM CHIPS
0--

+5CR

BA8H~ FOR BYTE 1

ROM CHIPS

+5 BBU

~~-.r--r-.--,----+5VCR

lliMJLEO
Figure 2-5

Single Voltage MOS RAM with Battery Backup

MA~7329

INSTALLATION

Table 2-5

Bus Grant Continuity

Backplane

Machine Type

H9270 (4 slot backplane)
H9275 (9 slot backplane)
H9273 (4 slot backplane)
H9276 (9 slot backplane)

0/0
022/022

in
in
out
out

O/CD
022/CD

Table 2-6

General Jumpers

Pin
Numbers

Function

6 to 7

In - write wrong parity

8 to 7

In - disables wrong parity

2 to Y

2 to Y out - 22 bit machine
2 to Y in - 18 bit machine

43 to 44

In - single voltage MaS RAM access time (150 ns device)

45 to 44

In - multiple voltage MaS RAM access time (200 ns device)

22 to 23

Not used

21 to 23

Not used

F to H

F to H in - connected to force starting address to 16K
F to H out - disables force function

3 to 9

3 to 9 in - connected on 16K and 64K MaS chip

13 to 15

Connected on 16K and 64K MaS chip

4 to 10

Connected only on 64K MaS chip

14 to 16

Connected only on 64K MaS chip

CHAPTER 3
FUNCTIONAL DESCRIPTION

3. 1 INTRODUCTION
The MSV 11-P memory modules interface with the LSI-11 bus. The CPU
and DMA devices can become bus master of the LSI-11 bus to transfer or
obtain data from memory. The memory is always a slave to whatever device becomes bus master. Figure 3-1 shows the CPU and DMA devices
connected to memory via the LSI-11 bus.
Devices that are ready to use the LSI-11 bus must gain control of the bus
through the arbitration that takes place in the CPU. The device that wins
the arbitration is able to use the bus as soon as bus signals BSYNC and
BRPL Yare negated. This device is now bus master and can initiate a bus
cycle. The types of bus cycles that can be performed are shown in Table
3-1.

LSI-ll BUS

MA-7161

Figure 3-1

Table 3-1

Typical System

Summary of Bus Cycles

Bus Cycle
Mnemonics

Description

Function with Respect
to Bus Master

DATI

Data word input

Read word

DATO

Data word output

Write word

DATOS

Data byte output

Write byte

DATIO

Data word input/output

Read word, modify,
write word

DATIOS

Data word input/byte output

Read word, modify,
write byte

FUNCTIONAL DESCRIPTION

All bus cycles are divided into three sequential events.
• Address cycle
• Data cycle
• Bus cycle termination
3.2 LSI-11 BUS SIGNALS AND DEFIt-UTIONS
In order for the bus master to transfer data, it must generate the signals
shown in Figure 3-2. The slave device (memory) receives the signals and
initiates BRPL Y. This starts a chain reaction to terminate the bus cycle.
Table 3-2 gives the signal names and definitions of the bus signals. Appendix A contains the flow diagram and signal sequences for DATO(B),
DATI, and DATIO(B).

BDAL 21-00L
BBS7 L
BWTBT L
BSYNC L

INTERFACE

BDOUT L
BDIN L

BRPLY L
BDCOK L - - - - - - '
MA-7331

Figure 3-2

Table 3-2

MSV 11-P Memory Interface

LSI-11 Bus Signals and Definitions

Signal Name

Cycle

Definitions

Bus Data
Address Lines
(BDAL 21-00 L)

Address

BDAL 21-00 L is received and decoded as an
address by the slave (memory).

Data write

Whel1 the bus master does a memory write,
DATO(B) or DATIO(B), the data is transferred
on BDAL 1 5-00 L.

Data read

The bus master receives data on BDAL 1 5-00
L. The validity of the data is noted by the
condition of BDAL 16 and 17. If BDAL 16 and
17 are active then the data on BDAL 15-00 Lis
bad. If BDAL 16 and 17 are not active, then the
data on BDAL 15-00 L is good.

FUNCTIONAL DESCRIPTION

Table 3-2

LSI-11 Bus Signals and Definitions (Cont)

Signal Name

Cycle

Definitions

Bus Write/Byte
(BWTBTL)

Address

When BWTBT is active, a write operation is
enabled. When BWTBT is negated a read
operation is enabled.

Data

If BWTBT is active during the data cycle, the
write operation that is performed is write byte.
Address bit 0 tells the logic what byte will be
modified.
If BWTBT is negated during the data cycle, the
write operation that is performed is write word.

Bus Bank 7
Select (BBS7 L)

Address

The bus master generates BBS7 during the
address cycle and removes the signal at the
end of the address cycle. The memory, on
receiving the signal changes the name to
BSEL 7 H. BSEL H (BBS7 L) implies the
address on the LSI-11 bus is an I/O address. If
address bits 5-12 are correct for CSR, BSEL H
enables the CSR address decode logic and
inhibits the memory address decode from the
PROMs.
BSEL L (BBS7 H) implies the address on the
LSI-11 bus is a memory address. This allows
the memory address decode from the PROMs
and inhibits CSR address decode.

Bus Synchronize
(B SYNC L)

Address

B SYNC L is asserted by the bus master to
indicate that it has placed an address on the
LSI-11 bus.

Data

The transfer is in progress until B SYNC L is
negated. When memory receives B SYNC L it
does the following.
Latches address bits
Latches row address bits
Latches column address bits
Sets read or WT request flip-flop.

Bus Data Input
(BDIN L)

Data

When asserted during B SYNC L time, BDIN L
implies an input transfer with respect to the
current bus master and requires a response
(BRPL y) from the addressed slave (memory).
When the memory receives BDIN L it enables
the memory transmitters. This allows the data
to be sent out on the LSI-11 bus.

FUNCTIONAL DESCRIPTION

Table 3-2

LSI-11 Bus Signals and Definitions (Cont)

Signal Name

Cycle

Definitions

Bus Data Output
(BDOUT L)

Data

BDOUT, when asserted, implies that valid data
is available on BDAL 15-00 L and that an
output transfer, with respect to the bus master
device, is taking place. BDOUT L is deskewed
with respect to data on the LSI-11 bus. On
receiving BDOUT L the memory generates
write REQ L and if permitted, starts the
memory timing. Arbitration with refresh always
takes place with write or read request.

Bus Reply
(BRPLY L)

The slave (memory) asserts BRPL Y in response to BDIN Lor BDOUT L. BRPL Y L is
generated by a slave device to indicate that it
will place its data on the BDAL lines or that it
will accept data from the BDAL lines according
to proper protocol.

Termination

When the bus master receives BRPLY L, it
starts a chain of events that terminates the
transfer.

3.2. 1 LSI-11 Bus Dialogues
The MSV 11-P memory module responds to the following dialogues: DATI,
DATO(B) and DATIO(B). Table 3-3 explains which figure and table to use
with each dialogue.

Table 3-3

Dialogues to Perform Memory Data Transfers

Dialogue

Figure

Table

DATO(B)
DATI
DATIO(B)

3-3
3-4

3-4

3-5

3-5
3-6

FUNCTIONAL DESCRIPTION

ADDRESS CYCLE

ADDRESS BDAL <21-00>

..-

BWTBT (DATO)
DEVICE

B SEL 7 NEGATED

MEMORY

B SYNC

DATA CYCLE
B SYNC
BWTBT - YES IF DATOB
DATA - BDAL <15-00>

DEVICE

MEMORY

B DOUT

_ B RPLY

MA-7162

Figure 3-3

Table 3-4

Dialogue DATO(B)

Dialogue DATO(B) Cycle

Bus Master

Memory
Address Cycle

(BDAL) 21-00 L

Memory receives the address and accepts or rejects it according to how the board was jumpered. The memory board that
accepts the address generates MSEL provided BSEL 7 H is
negated.

(BBS7)L

BSEL 7 H negated enables the address decode logic to generate MSEL.

(BWTBT)L

Memory sets up to do a write cycle by preventing the setting of
the read request flip-flop.

(BSYNC)L

(BSYNC)L latches the following.
Address
Row address
Column address
Set write request flip-flop.

Data Cycle
Bus master takes
the address and
BBS7 L off-line.
(BSYNC)L

(BSYNC)L is still active.

(BWTBT)L

If BWTBT is active, it writes a byte.
If BWTBT is negated, it writes a word.

FUNCTIONAL DESCRIPTION

Table 3-4

Dialogue DATO(B) Cycle (Cont)

Bus Master

Memory
Data Cycle

(BDAL) 21-00 L

Data is received from BDAL 15-00 L and two parity bits are
generated. The 18 bits, 16 bits data and 2 bits parity, are inputs
to the MOS chips.
Memory receives (BDOUnL and generates write request. Write
request goes to the arbitration logic; if there is no refresh
request or refresh cycle in progress, write request initializes the
memory timing. The effects of timing enable the memory module
to write the data into the MOS chips and generate (BRPL y)L.
Termination of Bus Cycle

Bus master
receives (BRPL y)L
and removes data
and (BDOUnL from
the LSI-11 bus.

(BRPL Y)L

(BDOUnL negated

Memory receives BDOUT negated and negates (BRPLY)L.

Bus master
receives (BRPL Y)L
negated and
negates (BSYNC)L
which terminates
the transfer.

(BRPL y)L is negated.

ADDRESS CYCLE

ADDRESS BDAL <21-00>

BWTBT NEGATED (DATI)
B SEL 7 NEGATED

DEVICE

MEMORY

B SYNC

DATA CYCLE
BSYNC
BDIN
DEVICE

__ DATA BDAL <15-00>

MEMORY

BRPLY

MA-7163

Figure 3-4

Dialogue DATI

FUNCTIONAL DESCRIPTION

Table 3-5

Dialogue DATI Cycle

Bus Master

Memory
Address Cycle

(BDAL) 21-00 L

Memory receives the address and accepts or rejects it, according to how the board was jumpered. The memory module
that accepts the address generates MSEL, provided BSEL 7 H
is negated.

(BBS7)L negated

BSEL 7 H negated enables the address decode logic to generate MSEL.

(BWTBT)L negated

Memory sets up to set the read request flip-flop.

(BSYNC)L

(BSYNC)L latches address and row and column address bits,
and sets the read request flip-flop. The read request goes to the
arbitration logic. If there is no refresh request or refresh cycle in
progress, the read request initializes the memory timing.

Data Cycle
(BSYNC)L

(BSYNC)L is still active.

(BDIN)L

When memory receives (BDIN)L it enables the memory transmitters, for DAL 15-00, as soon as TRPL Y is active. Then the
read data can be sent out on the LSI-11 bus.

Bus master
receives (BRPL Y)L
indicating memory
will place its data
on the BDAL lines.

The memory generates (BRPL Y)L as a result of receiving
BDIN Land TRPLY L.

Bus master
receives the data.

Data read from memory goes to parity checking logic and is
latched and sent out through transceivers DAL 15-00. DAL 16
and 17 are Os if no parity error was detected, or 1 s if a parity error
was detected.

Termination Cycle
(BDIN)L negated
when bus master
receives BDIN L
this causes
(BDIN)L to be
negated.

The signal (BDIN)L negated causes memory to negate
(BRPL Y)L, which in turn prevents the transceivers from
placing data on BDAL 15-00.

Bus master
receives (BRPL y)L
negated which
terminates bus
cycle.

(BRPL y)L is negated.

FUNCTIONAL DESCRIPTION

ADDRESS CYCLE
ADDRESS - BDAL <21-00>

BWTBT (DATI)

DEVICE

BSYNC

MEMORY

READ DATA CYCLE

-..

B SYNC
B DIN

MEMORY

DEVICE
DATA BDAL <10-00>

B RPLY

---------------------

----------------~-

PAUSE

---------------------------------------------WRITE DATA CYCLE
B SYNC

BWTBT (DATOB)
DATA - BDAL <15-00>

DEVICE

MEMORY

B DOUT

______

~I·~B--RP-L-Y----------------~~

______

MA-7164

Figure 3-5

Table 3-6

Dialogue DATIO(B)

Dialogue DATIO(B) Cycle

Bus Master

Memory
Address Cycle

(BDAL) 21-00 L

Memory receives the address and accepts or rejects it according to how the board wasjumpered. The memory board that
accepts the address generates MSEL, provided BSEL 7 H is
negated.

(BBS7)L

BSEL 7 H negated enables the address decode logic to generate MSEL.

(BWTBT) L negated

Memory sets up to set the read request flip-flop.

(BSYNC)L

(BSYNC)L latches address and row and column address bits,
and sets the read request flip-flop. The read request goes to
arbitration logiC. If there is no refresh or refresh cycle in
progress, the read request starts the memory timing.

FUNCTIONAL DESCRIPTION

Table 3-6

Dialogue DATIO(B) Cycle (Cont)

Bus Master

Memory
Data Cycle (Read)

(BSYNC)L

(BSYNC)L is still active.

(BDIN)L

When memory receives (BDIN)L it enables the memory transmitter, for DAL 15-00, as soon as TR PLY is active. Then the read
data can be sent out on the LSI-11 bus.

Bus master
receives (BRPL y)L
indicating memory
will place its data
on BDAL 15-00 L
and negates
(BDIN)L.

The memory generates (BRPL Y)L as a result of receiving
BDIN Land TRPLY.

Bus master
receives the data.

Data read from memory goes to parity checking logic and is
latched and sent out through the transceivers DAL 15-00. DAL
16 is Os if no parity error was detected, or 1 s if a parity error was
detected.

Pause
(BDIN)L negated

Complete input transfer - remove data from BDAL 15-00
negate (BRPLY)L.

Bus master
receives (BRPL Y)L
negated and gets
ready to output
data.

(BRPL Y)L is negated.

Data Cycle (Write)
(BSYNC)L

(BSYNC)L is still active.

(BWTBT)L

Memory at this time uses the BWTBT line to write byte or word
into memory.
(BWTBT)L active means write byte.
(BWTBT)L negated means write word.

Data output
BDAL 21-00 L

Memory receives the data BDAL 15-00 L and two parity bits
are generated. The 18 bits, 16 bits data, and 2 bits parity, are
inputs to the MOS chips.

(BDOUT)L

Memory receives (BDOUT)L and generates write request. Write
request goes to the arbitration logic. If there is no refresh
request or refresh cycle in progress, write request initializes the
memory timing. The effects of timing enables the module, writes
the data into the MOS chips and generates (BRPL y)L.

FUNCTIONAL DESCRIPTION

Table 3-6

Dialogue DATIO(B) Cycle (Cont)

Bus Master

Memory
Termination of Bus Cycle

Bus master
receives (BRPL Y)L
and removes data
and (BDOUl)L from
the LSI-11 bus.

(BRPL Y)L

(BDOUl)L negated

Memory receives BDOUT negated and negates (BRPLY)l.

Bus master
receives (BRPL Y)L
negated and
negates (BSYNC)L,
which terminates
the transfer.

(BRPL y)L is negated.

3.3 FUNCTIONAL DESCRIPTION OF MEMORY MODULE
All MSV 11-P memory modules have the logic functions shown in Figure 36. The charge pump circuit is used oniy with the Ma067 -FA rnodule (16K
chips). The functions shown in Figure 3-6 are discussed in detail in the
following paragraphs.
3.3.1 Xcvers (Transmit-Receives)
The Xcvers allow memory to transmit or receive: address, data, and control, via the LSI-11 bus. The LSI-11 bus signals are defined in Table 3-2.
3.3.2

Address Logic

1. The modules are jumpered for a starting address and a GSR address.
2. MSV 11-P memory modules receive all addresses from the LSI-11
bus.
3. The address decode logic on each memory module checks to see if
the board is selected (memory select) or the GSR is selected.

3.3.2.1 Board Selection Decode Logic - This consists of two PROMs
that monitor BOAL 21-14 and compare the address received against the
starting address jumpers. The PROMs are programmed to enable the logic to generate memory select (MSEL) and row enables (NA 16/18 and NA
15/ 1?). Table 3-? shows the output of the PROMs programmed for module M8C6? -LA with a starting address of zero. There are three different
types of PROMs.
1. M8C6? -LA PROMs programmed for 256K addresses per module
2. M8C6? -KA PROMs programmed for 128K addresses per module
3. M8C6? -FA PROMs programmed for 64K addresses per module

FUNCTIONAL DESCRIPTION

DAL <15-00>

PARITY
GENERATOR
LOGIC

PARITY
CHECKER
LOGIC

....

....
ADDRESS
LATCH

CSR
LOGIC

lAT CSR SElj

......

CSR
LATCH

I--

PR ERR ClK

•J

CSR SEL

ADDRESS
SWITCHES
BDAL
<21-00>

XCVERS
ADDRESS
- DATA

-------

rADDRESSING
LOGIC

DATA
LATCH

MSEL ROW AND
COLUMN ADR.

MOS
MEMORY
ARRAY

RSYNC
B SYNC
B WTBT
B SEL 7
B DIN

XCVER
CONTROL

B DOUT

TIMING
AND
CONTROL
LOGIC

DATA LATCH L

B RPLY

REFRESH CLOCK
AND
ADDRESS
COUNTER

r--

VDD

CHARGE
PUMP
CKT

r----- -5V
MA-7160

Figure 3-6

Logic Functions

Table 3-7

PROM Output for M8067-LA (Starting Address Zero)
Octa I Add resses

NA18 NA17

Row Enable

01777776
3
0140 0000
01377776
Generates
MSEL L

0100 0000
00777776

a
0040 0000
00377776

a
0000 0000

FUNCTIONAL DESCRIPTION

The address range of the two PROMs begins with the starting address
(jumper-selectable). The top limit of the memory module is then determined by what type of PROMs are being used (e.g., 256K from starting
address).
3.3.2.2 MOS Memory Address Logic - Jumper consideration must be
taken for 16K or 64K MOS memories when loading the row and column
latches with the MOS RAM address. The logic also has a row latch used
for refresh addresses.
The MSV 11-P family of memory modules perform three basic operations.
• CSR read/write transfers
• Memory read/write transfers
• Refresh cycles
When CSR transfers take place, the row select signals (RAS 0-3) and
column select signals (CAS 0-3) are inhibited (Figure 3-7).
When read/write cycles take place, the PROM sends the row enable signals (RAS 0-3) to the MOS memory array in order to select the proper
row. All columns (CAS 0-3) are always selected (Figure 3-7). First the
row address, then the coiumn address is loaded into internal registers in
the MOS RAM chips. One 18 bit location in memory is now selected.
When refresh cycles take place, the column select logic is inhibited. Ali
rows are selected (RAS 0-3). The refresh row address is loaded into an
internal register in the MOS RAM chips (Figure 3-7), and that address is
refreshed.
3.3.2.3 CSR Address Logic - Memory receives a CSR address and
compares (XOR) DAL 1-DAL4 with the CSR jumpers. If there is a match,
CSR selected (CSR) is generated. CSR generates MSEL, which enables a
read/write request to start the memory timing. RAS and CAS are inhibited; therefore, no memory addressing occurs.
3.3.3 CSR Write (Figure 3-8)
CSR address and signals BBS7 and BWTBT are received by the memory. If
the CSR address matches the CSR jumpers, CSR SEL and MSEL are generated. When BSYNC is received, the address and CSR SEL are latched,
and the WT REO flip-flop is set. During the data cycle the memory receives the data to be stored in the CSR register. Then, BDOUT is received
and write request starts memory timing. The signal LAT CSR SEL selects
the received data to be passed through the multiplexed inputs to the CSR
register. The CSR clock logic generates the CSR clock pulse which, in
turn, loads the CSR register.

RI:FRESH
Ri"O
TIMO
WRITE
REO
ARBITRATION
BDAL
<21 :00>

READ
REO

TIM 250
TIM 180
TIM 160

TIM 120
TIM 60
DATA BDAL<15-00>

DATA
LATCH

T120+T16

TOH + T60H
NA 16/18,.---''---....,
NA15/17

RASO L

ROW

B DOUT

SELECT I-.!.!R!::!AS~2-=L-+I

REF SELECT
ALL ROWS

16KIWDS

RAS 1 L

B SYNC

B DIN

ROW

16KIWDS
16KIWDS

RAS3L

16K/WDS

B RPLY

SELECT
ALL
COLUMN

CAS 0 L
CAS 1 L
CAS 2 L
CAS 3 L

TRPLY

COL
SELECT
REF
INHIBIT
COLUMN

"Tl

()

CSR-INHIBIT
ROW SELECT

o
z
»
r
o

(f)

()
REF CLK

8 9 1011 12
DAL 13

3 4
15

5 6

:IJ
-U
-I

6
z

Figure 3-7

Overview of Memory Logic

FUNCTIONAL DESCRIPTION

o BUS
BDAL <15:00>

- - - - -

ADR
LATCH

r---

r:R SELECTED

ADR
DECODE

e-LQMSEl

BWTBT •

- - - - -- - - - - - -

START

WRT
REO E

DMEMDRY
TIMING

MEMORY}TIMING

B SYNC

•

REFRESH

RD REO

CPU

I
BDAL <12:00>

B DOUT

DAL

-.
J.

<0,2>
< 5:11>
<14,15>

I
I
B RPLY

I--RPLY

lOGIC

ADR
LATCH
REFRESH

L/\T CSR

SEL

L
Figure 3-8

CSR Write

3.3.4 CSR Read (Figure 3-9)
GSR address, BBS7, and BWTBT negated are received by the memory. If
the GSR address matches the GSR jumpers, GSR SEL and MSEL are generated. When BSYNG is received, the address and CSR SEL are latched,
and the RD REQ flip-flop is set, starting the memory timing. As soon as
TRPL Y is generated, the contents of the GSR is latched. Memory receives
BDIN L, which enables the memory to transmit the latched GSR data onto
the LSI-11 bus.
3.3.5 Memory Array
The MSV 11-P family of memory modules uses early writes. Early writes
are achieved by a write going low prior to GAS going active. Data in is
strobed into the MOS chips by GAS going active.
The following MOS RAM chips are used in the MSV 11-P memory modules.
M8067-LA

11 LINES"

(64K chips) - A fully populated module that consists of
four rows of MOS RAM chips (512K bytes)

L~
1\

7 LINES

CSR CLOCK]
LOGIC

(ENABLES II
TO BE eLK IN)

._J
MA-7159

FUNCTIONAL DESCRIPTION

r--~~-------------------------~
BDAL <21 :00>

ADR
LATCH

LATCHED CSR SEL

CSR SEL
E35
E18
ADR
'-----1-. . DECODE

M SEL
RD REO

BSYNC

E2, Ell
CPU

B RPLY

RD REO
RPLY
LOGIC

REF
TIM 190

TRPLY

LATCHED CSR SEL
E15, El0, E16, E3

CSR REG

______ ..J
MA-9226

Figure 3-9

CSR Read

M8067-KA

(64K chips) - A half populated module that consists of
two rows of MOS RAM chips (256K bytes)

M8067-FA

(16K chips) - A fully populated module that consists of
four rows of MOS RAM chips (128K bytes)

The MOS RAM chips used in the M8067 -LA and M8067 -KA memory modules are dynamic random access memory circuits organized as a 65,536
by 1 bit (Figure 3-10). The MOS chips used in the M8067-FA memories are
dynamic random access memory circuits organized as a 16,384 by 1 bit
(Figure 3-11).

3.3.6 Timing and Control Logic
The memory responds to the asynchronous read/write commands or the
synchronous refresh cycle that takes place every 14.5 p,s. All requests go
to the memory timing lockout gate. When timing lockout is negated, the
request goes to arbitration and the winner gains control of the memory
timing (Figure 3-12).

FUNCTIONAL DESCRIPTION

PIN FUNCTIONS

PIN OUT

PIN 1

16 Vss

DIN42

15 CAS

WRITE 3

14 Dout

RAS4

13 A6

Ao 5

12A3

A2 6

11 A4

AI7

10A s

Vee 8

9A7

Ao A7

ADDRESS INPUTS

CAS

COLUMN ADDRESS STROBE
DATA IN

Din
Dout

DATA OUT

RAS

ROW ADDRESS STROBE

WRITE

READ/WRITE INPUT

Vee

NOT USED
POWER (+5V)

Vss

GND

MA-7332

Figure 3-10

64K MOS RAM Chip

PIN CONNECTIONS
V BB

Vss

CAs

DIN

WRITE

DouT

RAS

A3
~

Voo

Vee

PIN NAMES
Ao-A6

ADDRESS INPUTS

CAS

COLUMN ADDRESS STROBE

DIN

DATA IN

DouT
RAS

DATA OUT
ROW ADDRESS STROBE

iAi'RiTI

READ/WRITE INPUT

V BB

POWER (-5V)

Vee

POWER (+5V)

Voo

POWER (+12V)

Vss

GROUND

Figure 3-11

MA-7151

16K MOS Chip

FUNCTIONAL DESCRIPTION

COMMAND
DECODER

RWTBT

RD
FUNCT
LOGIC

RWTBT

WRITE REO L

HANDLER
OF
MEMORY

RD REO L

REQUEST

REF REO L

LOGIC

LATCHED ROW ADR TO MOS CHIP

ARBITRATION
CIRCUITRY

LATCHED COL ADR TO MOS CHIP

MEMORY

C
0
N
R
0

TIM 0 H

RAS - ROW ADDRESS STROBE
CAS - COLUMN ADDRESS STROBE
TRPLY - WILL GENERATE BRPLY
RD CLR -

RD END

WT END
DATA LATCH

MEMORY

CSR PR CLK
TIM 160 H

LOCKOUT

TIM 250 H

LOGIC

REF CLK
14.5 us

Figure 3-12

ENABLES CLEARING OF FLIP-FLOPS

REFRESH r - - - - - - - - - - '
CIRCUITRY

Timing and Control

3.3.7

Parity Logic

The parity logic performs the following two functions.
1. Parity generation - when the bus master is doing a OATO(B)
2. Parity checking - when the bus master is doing a DATI

3.3.7.1 Parity Generation - The data received from the bus master on
the LSI-11 bus (DALOO-15) goes to the parity generators (Figure 3-13).
The low byte parity generator generates odd parity (PDI 16 H). The high
byte parity generator generates even parity (POI 17 H).
CSR02 enables the diagnostic to force wrong parity. This enables the diagnostic to check out the parity logic.

FUNCTIONAL DESCRIPTION

E47

E53

DAL 00 H
DAL 01 H

DAL 08 H

DAL 09 H
DAL 10 H

DAL 02 H
DAL 03 H
DAL 04 H

PDI 17 H

DAL 11 H
DAL 12 H
DAL 13 H

DAL 05 H
DAL 06 H
DAL 07 H

DAL 14 H
DAL 15 H

ODD

PDI 16 H

ODD

CSR 02 H - - - - \

DAL 16~~-o--L--,

Figure 3-13

MA-7157

Parity Generators

3.3.7.2 Parity Checker - The MSV 11-P memory modules detect parity
errors, report parity errors, and save the address of the parity error in the
CSR register. Parity detection logic always expects byte 0 to have an
even number of one bits and byte 1 to have an odd number of one bits. If
this does not happen, T PAR ERR l is generated (Figure 3-14).
Parity reporting is done if the program has set CSR bit 0, the parity error
enable bit, T PAR ERR l, and RDIN negated. This allows BDAl 16 and
BDAl 17 to be sent out on the lSI-11 bus to flag a parity error.
Parity address is saved in the following way.
• After the data is read from memory, it goes to the parity checkers
and a holding register.
• When the data is latched, the signal CSR ClK is generated if there is
a parity error (Figure 3-14).
• CSR ClK latches the address in the CSR register.
CSR cycles or refresh cycles inhibit the parity logic.

3.3.8 Refresh
The MSV 11-P memory modules are MOS RAM chips which are refreshed
every 2 ms. The logic refreshes a row at a time; 128 rows are refreshed in
a 2 ms period.
Figure 3-15 shows that a refresh timer generates a pulse every 14.5 J,ls.
This pulse, called REF ClK, does the following.
• Generates a refresh request
• Increments the refresh address CTR
The address counter produces row address bits A 1 through A 7 for 16K
chips, and A 1 through A8 for 64K chips.

FUNCTIONAL DESCRIPTION

LAT SEl CSR H
REF H

E57
DO 00 H

DO 01 H
DO 02 H
0003 H
0004 H

BYTE 0

0005 H
0006 H

0007 H
PDO 16 H

ODD~----+-------------~

E63

TIM 160 H

DO 08 H
DO 09 H

EV~----4-----------~~

BDAl16

DO 10 H
DO 11 H
DO 12 H

BYTE 1
BDAl17

DO 13 H
DO 14 H
DO 15 H
PDO 17 H

ODD

JUf----- CSR ClK l
3CR

E15
DATA LATCH

______________~

Qr-~6

BlK END

Figure 3-14

MA·7156

Parity Checkers

VDD +12V

+12V
14.5 us
PULSE
REFRESH
TIMER

-11V

RECTIFIER

3-TERMINAl
REGULATOR

-5V

FilTER
CAPACITORS

REF ClK

REFRESH
ADDRESS
CTR

' - - - - - - - - - - . REF ClK

Figure 3-15

Refresh Logic and Charge Pump Circuit

REF <AO-A6> H
REFRESH ADDRESS
TO ADDRESS lOGIC

MA·7158

FUNCTIONAL DESCRIPTION

3.3.9 Charge Pump Circuit
The purpose of the charge pump circuit is to generate a filtered regulated
-5 V. The M8067-LA and M8067-KA modules, which use 64K chips, do
not require - 5 V. If W3 is removed (Figure 3-15), then the memory modules mentioned above will not receive -5 V. The M8067-FA modules,
which use 16K chips, require - 5 V; therefore, W3 must be installed.
The -5 V is generated in the following manner (Figure 3-16). The output
of the timer is a + 12 V pulse that occurs every 14.5 J,Ls. The + 12 V pulse
goes to a rectifier whose output is - 11 V. A three terminal regulator
takes the -11 V and produces a regulated -5 V. The -5 V regulator
output goes to module pin connection BK 1, which is connected to BL 1 on
the backplane. Filter capacitors receive the - 5 V and pass the filtered
-5 V to the output, if W3 is installed.
3.4 CONTROL AND STATUS REGISTER (CSR) BIT ASSIGNMENT
The control and status register (eSR) in the MSV 11-P allows program
control of certain parity functions, and contains diagnostic information if a
parity error has occurred. The eSR is assigned an address and can be
accessed by a bus master via the LSI-11 bus. Some eSR bits are cleared
by assertion of BUS INIT L. This signal is asserted for a short time by the
processor after system power has come up, or in response to a reset instruction. The eSR bit assignments are shown in Figure 3-17 and are described as follows.
Bits 1,3,4, 12, and 13

These bits are not used and are always
read as logical zeros. Writing into these
bits has no affect on the eSR.

Bit 0

Parity Error Enable - If a parity error
occurs on a DATI or DATIO(B) cycle to
memory, and bit 0 is set = 1, then BDAL
16 Land BDAL 17 L are asserted on the
bus simultaneously with data. This is a
read / write bit reset to zero on power up
or BUS INIT.

PARITY
ERROR

y
ERROR ADDRESS
WRITE
WRONG
PARITY

EXTENDED
CSR READ
ENABLE

Figure 3-16

CSR Bit Allocation

PARITY
ERROR
ENABLE

MA-7169

FUNCTIONAL DESCRIPTION

Bit 2

Bits 05-11

Write Wrong Parity - If this bit is set = 1
and a DATO or DATOB cycle to memory
occurs, wrong parity data is written into
the parity MOS RAMs. This bit can be
used to check the parity error logic as
well as failed address information in the
CSR. The following diagnostic is applicable.
•

With bit 2 set, writes entire memory
with any pattern.

•

Read first location in memory, if bit a
of the CSR is set, then a parity error
indication is detected on the LSI-11
bus, and the failed address (location
0) is stored in the CSR.

•

Reads the CSR and obtains the failed
address, CSR bit 14 = a implies
A 11-A 17 on CSR bits 5-11. CSR bit
14 = 1 implies A 1B-A21 on CSR bits
5-B. Bit 2 is a read/write bit reset to
zero on power up or BUS INIT.

Error Address Bits - If a parity error occurs on a DATI or DATIO(B) cycle, then
A 11-A 17 are stored in CSR bits 5-11 and
bits A 1B-A21 are latched. The 12BK word
machines (1B-bit address) require only
one read of the CSR register to obtain the
failed address bits. CSR bit 14 = a allows
the logic to pass A 11-A 17 to the LSI-11
bus. A 204BK word machine (22-bit address) requires two reads. The first read
CSR bit 14 = a sends contents of CSR
bits 5-11. Then the program must set CSR
bit 14 = 1. This enables A 1B-A21 to be
read from CSR bits 05-0B.
The parity error addresses locate the parity error to a 1K segment of memory.
These are read/write bits and are not reset to zero via power up or BUS INIT. If a
second parity error is encountered, the
new failed address is stored in the CSR.

Bit 14

Extended CSR Read Enable - The use of
this bit was explained in the error address
description.

FUNCTIONAL DESCRIPTION

Bit 14 = 0, always for 128K word machine
Bit 14 = 0, first read on 2048K word machine
Bit 14
1, second read on 2048K word
machine
Bit 15

Parity Error - This bit set indicates that a
parity error has occurred. The bit then
turns on a red LED on the module. This
provides visual indication of a parity error.
Bit 15 is a read/write bit. It is reset to zero
via power up or BUS INIT and remains set
unless rewritten or initialized.

CHAPTER 4
MAINTENANCE

4.1 GENERAL
The maintenance procedures in this chapter apply to both versions of the
MSV 11-P memory module. To perform corrective maintenance on this
product, the user must understand basic operation of the MSV 11-P memory module as described in the previous chapters. This knowledge, together with diagnostic testing knowledge, should help the user isolate
MSV 11-L malfunctions.
CAUTION: ALL power must be off before installing or removing modules.
Always be sure the component side of the memory faces in the same direction as the other modules within the LSI system.
4.2 PREVENTIVE MAINTENANCE
Preventive maintenance pertains to specific tasks, performed at intervals,
to detect conditions that may lead to performance deterioration or malfunction. The following tasks can be performed along with other scheduled preventive maintenance procedures for the LSI computer system.
1. Visual inspection
2. Voltage measurements
3. Diagnostic testing
4.2.1 Visual Inspection
Inspect the modules and backplane for broken wires, connectors, or other
obvious defects.
4.2.2 Power Voltage Check
Once primary power has been turned on, check the dc power voltage at
the backplane (Table 4-1).

MAl NTENANCE

Table 4·1

Voltage Pins

Voltage

Backplane Pins

+ 5V

AA2, BA2, BV1, CA2, and DA2
AV1 and AE1 *
or
AV1 and AS1 *

+ 5 V BBU

+ 5V
+12 V
+ 5 V BBU
+12 V BBU

AA2, BA2, BV1, and CA2
AD2 and BD2
AV1 and AE1
AS1

Single Voltage
MOS RAMs

Multi Voltage
MOS RAMs

*Check backplane voltages to ensure proper configurations.

4.2.3 Diagnostic Testing
Memory diagnostic programs are available from DIGITAL for testing the
MSV 11-PF /PK/PL memory modules.
For fault isolation in 22-bit systems and 18-bit systems use the following
diagnostics.
MAINDEC-11 CVMSA
MAINDEC-11 CZKMA

(22-bit system)
(18-bit system)

In most cases a bad memory module can be detected by using the error
printout and program listing.
Detailed operating instructions and program listings are included with
each diagnostic software kit.

4.3 DIGITAL'S SERVICES
Maintenance services can be performed by the user or by DIGITAL.
DIGITAL's maintenance and on-site services are described in Chapter 1 of
the Microcomputer Processor Handbook (EB-18451-20).

APPENDIX A
SIGNAL SEQUENCES

Figures A-1, A-2, A-3, and A-4 provide the flow diagram and signal sequences for DATO(B), DATI, and DATIO(B).

"'U
"'U

r -__

z
o

~ ~r---------------~
__

FINISH
REF CYCLE

NOT MY JOB

LATCH
ADDRESS
NEGATE
LOCKOUT L
LATCH RDW
ADDRESS
WRITE DATA
BYTE AND
ASSERT BRPLY L

LATCH COM
ADDRESS

FINISH
REF CYCLE

A REF CYCLE
NEGATE
LOCK OUT L

Figure A-1

Memory Operation Cycle

- ROW ADDRESS
- COL ADDRESS

APPENDICES

SYNC H

RASO L

CASO L
MUX <A 1 :A7> H

COLUMN

WTBTO L
DATO REQ L

,~--------------------~

"~-------------------~ORY
'!- ~~;L~~~AB LED

LOCKOUT L

REPLYH
DATA IN

_---"":'~_-

_ _- - : - _ /

WRITE DATA-

MR.0352

Figure A-2

DATO(B) Signal Sequence

SYNC H

RASO L
CASO L

MUX<Al:A7> H

COLUMN

DATI REQ L

LOCKOUT L

NEW MEMORY
CYCLE ENABLED

RPLY H
BUS MASTER READS DATA
DATA OUT

--~--------------------------~

LATCHED DATA VALID
MR-03S1
MA-7219

Figure A-3

DATI Signal Sequence

»
"'U
"'U

~SCYCLE

SYNC H --"V

~~----------~/

RASO L

,,'--------"/

CASO L
MUX <Al:A7> H
REQL

=t><
-~

COMPLETED

COLUMN

ROW

~___________R_O_W________ ~

DATI

------------------~~
"k

REPLY H

><===><______

~___________D_A_T_O__________"~

~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

LOCKOUT L

COLUMN

"~----------_______~NEWMEMORY
CYCLE
/
"ENABLED

~I--B-U-S-M-A-S-T-E-R-R-E-A-DS--D-AT-A--·-------------------~

DATA

----+---------------------------j

WTBTO L

LATCHED DATA VALID

WRITE DATA

----------------~

,------------------------/
MR-0353
MA-7220

Figure A-4

DATIO(B) Signal Sequence

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Digital Equipment Corporation • Bedford, MA 01730