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EK-DUV11-TM-001

August 1977

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Document:	DUV11 Line Interface Technical Manual Aug77
Order Number:	EK-DUV11-TM
Revision:	001
Pages:	104
Original Filename:	EK-DUV11-TM-001_DUV11_Line_Interface_Technical_Manual_Aug77.pdf

OCR Text

DUV11
line interface
technical manual

EK-OUV11-TM-001

DUV11
line interface
technical manual

digital equipment corporation. maynard, massachusetts

Preliminary Edition, April 1977
I st Edition, August 1977

Copyright 't., 1977 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes: no responsibility for any ~rrors which ,may appear in this
manuaL
Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-lO
DECSYSTEM-20

DEC"tape
DECUS
DIGITAL
MASSBUS

PDP
RSTS
TYPESET-8
TYPESET-II
UNIBUS

CONTENTS
Page
CHAPTER 1

INTRODUCTION

1.1
1.2
1.2.1
1.2.2
1.2.2.1
1.2.2.2
1.2.2.3
1.3
1.3.1
1.3.2
1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.3.1
1.5.3.2
1.6
1.6.1
1.6.2

SCOPE ................................................................................................................ 1-1
DATA COMMUNICATION TECHNIQUES, ........ , .......................................... 1-1
Pulse Coding ....................................................................... '" ...................... 1-1
Pulse Code Transmission ........................................ , ............................... ,..... 1-1
Asynchronous Serial Transmission ......................... ~ ............................. 1-2
Synchronous Serial Transmission ......................................................... 1-3
Isochronous Serial Transmission .......................................................... 1-4
COMMUNICATION SYSTEMS ....................................................................... 1-4
Synchronous Systems ................................................................................... 1-4
Computer Application .................................................................................. 1-6
GENERAL DESCRIPTION ............................................................................... 1-6
SPECIFICATIONS ............................................................................................. 1-8
Environmental ............................................................................................. 1-8
Electrical ...................................................................................................... 1-9
Performance ................................................................................................. 1-9
Baud Rates for Synchronous Communications ..................................... 1-9
Baud Rates for Isochronous Communications ...................................... 1-9
ENGINEERING DRAWINGS .......................................................................... 1-9
Basic Signal Names ........................................... ~ .......................................... 1-9
Flip-Flop Signal Names .............................................................................. 1-1 0

CHAPTER 2

INSTALLATION

2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.2

INSTALLATION ................................................................................................ 2-1
Mounting the DUVl1 in the Computer .............. ,......................................... 2-1
Installing the Modem Cable Harness ............................................................ 2-2
Installing DUVII to Null Modem ................................................................ 2-3
Q BUS and Interrupt Vector Address Assignments ....................................... 2-6
Jumper Functions ............................ ,............................................................ 2-7
Option Switches ................................................ ,.......................................... 2-8
INITIAL TESTING ........................... ,........ ,....................................................... 2-8

CHAPTER 3

DEVICE REGISTERS AND INTERRUPT REQUESTS

3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.3

SCOPE ............................................... ,....................................... ,........................ 3-1
DEVICE REGISTERS ......... , .............................................................................. 3-1
Register Address Assignments ,............................... ,..................................... 3-1
Register Title and Bit Assignments ......................... " .................................... 3-1
Title Assignments ....................................... ,.......................................... 3-1
Bit Assignments .................................................... ,............................... 3-2
INTERRUPT REQUESTS ................................................................................ 3-12

iii

CONTENTS (CONT)
CHAPTER 4

THEORY OF OPERATION

4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.11

SCOPE ...... ;......................................................................................................... 4-1
INITIALIZATION AND PROGRAMMING ........................ ~:......................... .4-1
OVERALL DATA FLOW .................................................................................. 4-1
FUNCTIONAL BLOCK DESCRIPTION ......................................................... .4-2
Address Comparator and Command Decoder ...... ~ ...................................... .4-2
Data Multiplexer ......................................... :.......
4-2
Modem Interface Logic ................................. ~ .............................................. 4-2
Receiver Logic .............................................................................................. 4-2
Transmitter Logic .......................................................................................... 4-5
Interrupt Control Logic ................................................................................ 4-5
DETAILED FUNCTIONAL DESCRIPTION .................................................. .4-5
Address Comparator (Engineering Drawing D 1) ......................................... .4-5
Command Decoder (DC004 Chip as Shown on Engineering Drawing D 1) ... .4-5
Data Multiplexer (Engineering Drawing D2) ................. :............................. .4-5
Modem Interface Logic ............................ :................................................... 4-5
Receiver Control Logic ................................................................................. 4-6
Transmitter Control Logic .......................................................................... 4-13
Interrupt Contiol Logic ............................................................................... 4-19
Clear Logic .................................................................................................. 4-19
Clock Control Logic .................................................................................... 4-19
+ 12 to -12 Power Converter ........................................................................4-19
. Maintenance Indicators .............................................................................. 4-19

CHAPTER 5

PROGRAMMING REQUIREMENTS AND RECOMMENDATIONS

5.1
5.2

INTRODUCTION .............................................................................................. 5-1
PROGRAMMING TH.E TRANSMITTER IN THE
SYNCHRONOUS MODE .................................................................................. 5-1
Loading the PARCSR .................................................................................. 5-1
Handshaking Sequence ................................................................................. 5-1
Enabling the Transmitter: ............................................................................. 5-3
Detecting the Last Character of the Message ................................................. 5-3
Transmitting Initial Sync Characters to Establish Synchronization ............... 5-4
Transmitting Sync Characters to Maintain Synchronization ......................... 5-4
PROGRAMMING THE RCVR IN THE INTERNAL
SY·NCHRONOUS MODE .................................................................................. 5-5
PROGRAMMING THE RCVR IN THE EXTERNAL
SYNCHRONOUS MODE .................................................................................. 5-6
PROGRAMMING THE XMTR·IN THE ISOCHRONOUS MODE ................. 5-6
Loading the PARCSR .................................................................................. 5-6
Enabling the XMTR ..................................................................................... 5-6
PROGRAMMING THE RCVR IN THE ISOCHRONOUS MODE .................. 5-6

5.2.1
5.2.2
5.2.3
502.4
5.2.5
5.2.6
5.3
5.4
5.5
5.5.1
5.5.2
5.6

O"O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONTENTS (CONT)
CHAPTER 6

MAINTENANCE

6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.1.1
6.5.1.2
6.5.1.3

SCOPE ................................................................................................................ 6-1
MAINTENANCE PHILOSOPHY .......................................... , ........................... 6-1
PREVENTIVE MAINTENANCE ...................................................................... 6-1
TEST EQUIPMENT REQUIRED ...................................................................... 6-1
CORRECTIVE MAINTENANCE ........... ,......................................................... 6-1
Maintenance Modes ........................................................ ,............................. 6-2
System Test Mode ................................................................................ 6-2
Internal Loop Mode ............................................................................. 6-2
External Loop Mode ...................................... ,..................................... 6-7

APPENDIX A

REPRESENTATIVE MODEM FACILITIES AVAILABLE

APPENDIX B

LSI INTEGRATED CIRCUIT DESCRIPTIONS

B.l
B.2
B.2.1
B.3
B.3.1
B.4

INTRODUCTION ............................................................................................. B-l
PR 1472B SYNCHRONOUS RECEIVER (P /SAR) ............................................ B-l
Synchronous Mode Operation ............... ,..................................................... B-9
PT1482B SYNCHRONOUS TRANSMITTER (P/SAT) .................................. B-l1
Synchronous Mode Operation .................... ,.............................................. B-ll
DC003 INTERRUPT CHIP .............................................................................. B-21

APPENDIX C

INTEGRA TED CIRCUITS

FIGURES
Figure No.
1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-2
3-3
3-4
3-5

Title

Page

Asynchronous Technique Format ......................... ., ............................................. 1-2
Synchronous Format ............................................................................... ,............ 1-3
Typical Communications System .......................... ;.~ ............................................. 1-7
DUVII (M7951) Major Components ....................................... ,........................... 1-8
Flip-Flop Signal Names ...................................................................................... 1-10
DUVI1-DA Mounted in H9270 ........................................................................... 2-1
BC05C-25 Cable Harness .............. ,...................................................................... 2-2
DUV11 to Modem Connection .................................... ,....................................... 2-3
DUV11 to Null Modem Connection ..................................................................... 2-3
Null Modem Connector (H312A) ......................................................................... 2-4
Null Modem (H312A) Jumper Connections .. ,............. ,........................................ 2-5
Modem Test Connection Installation ............................ ,......... , .......... ,................. 2-9
DUV11 Register Configurations and Bit Assignments .......................................... 3-2
Receiver Status Register (RXCSR), ...................................................................... 3-3
Receiver Data Buffer (RXDBUF) ................................... , .......... ,....... ,................. 3-6
Parameter Status Register (PARCSR) ................ ~ ................................................. 3-8
Transmitter Status Register (TXCSR) .................................................................. 3-9
v

FIGURES (CONT)
3-6
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
6-1
B-1
8-2

B-3
B-4
B-5
8-6
8-7
8-8
8-9

Transmitter Data Buffer (TXDBUF) .................................................................. 3-12
D UV 11 Functional Block Diagram ............... ,...................................................... 4-3
Receiver Internal Timing Diagram ....................................................................... 4-7
Receiver External Synchronous Timing Diagram ................................................ .4-9
Receiver Isochronous Timing Diagram .................................................. ,............ 4-ll
Transmitter Synchronous Timing Diagram ................................................... ,.... .4-15
Transmitter Isochronous Timing Diagram ......................................................... .4-17
External Loop Maintenance Mode Interconnection Diagram ............................ .4-20
DUVl1 to Modem Interface Diagram .................................................................. 5-2
Handshaking Sequence Timing Diagram ............................................................... 5-2
Maintenance Diagram .......................................................................................... 6-3
PR1472B Programmable Synchronous Receiver (P /SAR) ................................... B-l
P /SAR.Pin Connections ...................................................................................... B-2
Synchronous Timing Example (P /SAR) ............................................................. B-I0
PT1482B Programmable Synchronous Transmitter (P /SAT) ............................. B-12
P/SAT Pin Connections ................................................................................... ,.B-12
Synchronous Timing Example (P /SA T) ............................................................. B-19
DCaa3 Logic Symbol Diagram .......................................................................... B-21
DCOO3 Timing Diagram (Section A Only) .......................................................... B-25
DCa03 Timing Diagram (Sections A & B) .......................................................... B-27

TABLES
Table No.

I-I
1-2
2-1
2-2

2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
6-1
B-1
B-2
B-3
B-4
B-5
B-6
B-7

Title

Page

Representative M·essage Codes ............................................................................. 1-4
Computer Communications Applications ............................................................. 1-6
Signal List for Jumper Connections of Null Modem H312A ................................. 2-5
Guide for Setting Switches to Select Device Address ............................................ .2-6
Guide for Setting Switches to Select Vector Address ............................................. 2-7
Switch Assignments .............................................................................................. 2-8
D UV 11 Register Address Assignments ................................................................. 3-1
Receiver Status Register Bit Description ............................................................... 3-4
Receiver Data Buffer Bit Description ................................................................... 3-7
Parameter Status Register Bit Description .............. ~ ............................................. 3-8
Transmitter Status Register Bit Description ........................................................ 3-10
Transmitter Data Buffer Bit Description ............................................................. 3-12
Test Equipment Required ..................................................................................... 6-2
P /SAR Signal Mnemonics.~ ................................................................................. B-3
P /SAR Signals .................................................................................................... B-4
Sync Mode Control Definition ........................................................................... B-1 0
P /SA T Signal Mnemonics ................................................................................. B-13
P /SAT Signals .......................................... ,........................................................ B-14
SYNC Mode Control Definitions ...................................................................... B-20
DC003 Signals ................................................................................................... B-22
vi

CHAPTER 1
INTRODUCTION

1.1 SCOPE
This manual provides a complete description of the DUVll Line Interface including installation,
theory of operation, programming and maintenance. The material is presented with the understanding
that the reader is familiar with basic digital computer theory.
This chapter contains introductory information. Data communication techniques and systems are
discussed. The DUVII is presented in terms of its general and physical description and specifications.
Also, an explanation of engineering drawing conventions is provided.

1.2 DATA COMMUNICATION TECHNIQUES
There are several techniques used for the transfer of data communication signals. Each has its particular advantages and disadvantages.
1.2.1 Pulse Coding
Standard data communication messages are sent in some form of pulse code. There are several varieties of pulse codes used in the transferral of data in digital form. Binary signals, by their very nature,
are natural elements for digital data codes. Such codes are said to be in binary format.
A formatted binary code can represent different symbols only by allowing sufficient binary elements
for each symbol. If we think of one binary digit (or bit) representing each symbol, we have only two
choices: one symbol represented by the on state, the other represented by the off state. With such an
arrangement, we could let the on or one state represent no and the off or zero state represent yes. While
it would be difficult with such an arrangement, we could convey messages of a very limited nature from
a remote station (such as the answer to "Is the temperature at your station over 70 0 F?").

If, instead of using one binary digit for our character, we use two, we have more characters to choose
from. Our choice for a I-bit code was limited to two: or 1. Our choice for a 2-bit code is four: 00, 01,
10, or 11. If we choose a 3-bit code, our choice is eight: 000,001, 010, 011, 100, 101, 110, and 111. It can
be shown that for a code with a character makeup of n bits, the number of characters available will be
2n.
In communications pai'lance, instead of calling these codes I-bit codes, 2-bit codes, etc., they are called
I-level codes, 2-level codes, etc. Although any arbitrary meaning can be assigned to a code character, it
is more practical for the majority of operations to let the characters represent numbers, punctuation
marks, spaces, and letters of the alphabet. In addition to these, some special codes use characters for
other meanings.

1.2.2 Pulse Code Transmission
I n order to transmit code characters, it is necessary to arrange their elements in a way that will allow
their reception without uncertainty.

1-1

There are two basic techniques of serial data transmission: asynchronous and synchronous. These two
techniques, as well as a third, isochronous, will be discussed in the following paragraphs.
1.2.2.1 Asynchronous Serial Transmission - This technique enables data to be transferred as it
becomes available. This is possible by framing each data character with a begin signal (START bit)
and an end signal (STOP bit), so that the equipment receiving the data (the interface receiver) knows
when a data character is being presented on the communication line and when the line is inactive.

Hence, each character consists of three parts: a START bit, the data bits, and a STO P bit (Figure 1-1).
A START bit is a line state (usually a zero) that lasts for 1 bit time. The data bits represent the actual
binary character being transferred. In many applications the characters are 8 bits long with the least
significant bit being sent out and received first. A STOP bit is a line state (usually a one) that lasts for 1,
1.42, or 2 bit times; it indicates that character transmission is complete. The STOP bit enables the
interface receiver to check synchronization after each character transmission. If the STOP bit is not
received properly, i.e., it is not presented on the line immediately after the last data bit, the character
received is considered erroneous and retransmission is necessary.
s

(LlNE= 1) - -......
DATA
(LINE=O)

i,-__

L-_ _ _ _ _ _ _ _ _

STOP BITS
DATA BITS

' - - - - - - - - - - - - - - - - - START BIT
11-2233

. Figure 1-1

Asynchronous Technique Format

Clocking for the interface transmitter and interface receiver during asynchronous transmission is provided by two different sources that ate asynchronous to one another. The transmitter clock is enabled
when data is available for transmission and clocks the character onto the line. The receiver clock is
enabled when a START bit is detected on the line and samples the data bits as they are presented on
the line. The receiver is also equipped with a counter that counts the character bits received. When a
complete character and a STOP bit are received (the receiver must know the number of bits per
character), the receiver clock is disabled until the next START bit is detected.
The asynchronous serial data transmission technique has the following advantages:
1.

Can be generated easily by electromechanical equipment (e.g., Teletype® keyboard)

Can be used easily to drive mechanical equipment (e.g., Teletype printer)

Characters can be sent asynchronously (as they become available) because each character
has its own synchronizing information.

The disadvantages of the asynchronous serial transmission technique are:

Separate timing is required for both transmitter and receiver.

It is distortion sensitive because the receiver depends on incoming signal sequences to become synchronized. Any distortion in these sequences will affect the reliability with which
the character is assembled

®Teletype is a registered trademark of Teletype Corporation

1-2

Speed is limited because a reasonable margin between characters must be built-in to accommodate distortion.

It is inefficient because at least 10 bit times are required to send 8 bits of data. If a 2 bit time

STOP bit is used, it takes 11 bit times to transfer 8 bits of data.
1.2.2.2 Synchronous Serial Transmission - This technique does not use START and STOP bits to
accomplish synchronization. Instead, the entire block of data (message) is preceded on the line by a
synchronizing code. When the interface receiver recognizes this code (henceforth referred to as sync
characters), it locks in and, using a counter, assembles the data characters which follow. Hence, as in
the asynchronous technique, the receiver must know the number of bits per character.

This technique requires that the clock for the interface transmitter be identical to the clock used at the
receiver. The clock signal is provided to the transmitter and receiver on lines separate from the data
line. At the transmitter, the clock signal serves to clock the data onto the line. At the receiver, the clock
signal gates the data in. Figure 1-2 illustrates the timing for a synchronous communication system
using modems.
I~ 1 BIT TIME
MODEM CLOCK

o
DATA

000

0
r - - -.....

LSB

I - S Y N C CHARACTER-I-DATA CHARACTER--+l

I
11-2234

Figure 1-2

Synchronous Format

As shown in Figure 1-2, the modem provides the clock, the transmitter presents the data to the line on
the positive going edge of the clock, and the receiver samples the data on the negative going edge. If the
transmitter pauses at any time and fails to inhibit the clock, the receiver will continue to sample the
line, synchronization is lost, and the remainder of the message will be erroneous.
The advantages of the synchronous serial data transmission technique are:
l.

Modem timing sources can be used for both transmitter and receiver.

If modem timing is used, interface receiver does not require clock-synchronizing logic as
does the asynchronous technique.

It is highly efficient because there are no bit times wasted with the use of START and STOP

bits. All bits on the line are data with the exception of the sync characters at the beginning of
the bit stream.
4.

Low distortion sensitivity because the timing is provided along with the data.

Higher speeds are achievable because of the low distortion sensitivity.

The disadvantages of the synchronous serial data transmission technique are:
l.

Characters must be sent synchronously, not asynchronously (asynchronous transmission is
desirable for most real-time and mechanical applications).
1-3

One bit time added to or missing from the data-bit stream can cause the entire message to be
faulty.

The common-carrier equipment required to accommodate this mode of operation is more
expensive than the equipment required for asynchronous modes of operation.

Mechanical equipment cannot transmit or receive this format directly.

1.2.2.3 Isochronous Serial Transmission - This technique is essentially the transmission of asynchronous data over a synchronous modem. Character synchronization is achieved via START and STOP
bits; a common timing source is used for both the transmitter and receiver.
The isochronous technique does have advantages over the asynchronous technique. Clocking for
isochronous operations emanates from the modems and is synchronous to the data; hence, the receiver
does not require clock-synchronizing logic and distortion sensitivity is low, making higher speeds
possible.

1.3

COMMUNICATION SYSTEMS

1.3.1 Synchronous Systems - Synchronous modulator-demodulators (modems) have permitted a
higher rate of data transmission than asynchronous modems over a voice grade facility. The nature of
these transmission techniques has also resulted in higher efficiency by eliminating the need for synchronizing information with every character.
Most synchronous modems supply all the timing necessary to receive each bit as it is made available
from the modem. The difficulty in designing a synchronous modem interface is to design the capability
of communicating in the rnessage formats used in synchronous communications.

Table 1-1

Representative Message Codes

Character

Meaning

Function

**SYN
**SOH

Synchronizing signal
Start of heading signal

**STX
**ETX

Start of text signal
End of text signal

**ACK

Acknowledge signal

**NAK

Negative acknowledge signal

Establish character framing
Precedes block message heading
characters
Precedes block of text characters
Terminates a block of characters
started with STX
* Affirmative acknowledgment of
message received
*Negative acknowledgment of
message received

*ACK and NAK are sent by the station that received the message to the station that originated the message.
**Software protocol

It is not the purpose of this manual to discuss the format for synchronous communication in detail.
However, a brief description of these formats is outlined to facilitate the reader's understanding of
synchronous interface design.

Because the synchronous transmission technique provides only bit recovery timing, there must be a
way to establish character framing and message framing. This is accomplished by using codes (usually
ASCII) that are assigned for synchronous message formatting purposes. Representative message codes
are listed in Table 1-1.
1-4

A typical message that might be sent between two devices (a terminal and a processor) follows.
Terminal To Processor
SYN
SYN
SYN
SOH
User Terminal
No.4
STX
Req. Balance
of Account
No. 14325
ETX
BCC (check character)
Idle Line
Processor To Terminal
SYN
SYN
SYN
ACK
SYN
SYN
SYN
SOH
To Terminal
No.4
STX
Balance is
$100
ETX
BCC (check character)
Idle Line
Terminal To Processor
SYN
SYN
SYN
ACK
Idle Line
1-5

1.3.2 Computer Application - Electronic computers are often connected into communication systems
to help transmit and process digital data. By using computer systems to concentrate data from many
low-speed terminals over one voice grade facility, significant improvements can be made in the efficiency of a data communication system. Since most long-range communication systems are connected
through common carrier facilities, a communication system using a computer should be interfaced to
the correct type facility. There are two basic types of common carrier facilities to which computers
must be interfaced: asynchronous serial and synchronous serial. We have already pointed out the
advantages and disadvantages of these two types of facilities. Table 1-2 shows typical speeds and
applications of these two techniques based on these advantages and disadvantages.
As shown in Table 1-2, there are three basic communication applications to be solved by the computer
communications engineer:
Low speed terminal equipment, such as Teletypes
Medium speed terminal equipment
Intercomputer communications.

Table 1-2

Computer Communications Applications

Speed

Asynchronous

Synchronous

Low 0 to 300 baud

Electromechanical terminals
such as keyboard printers and
teletypes.
Unbuffered terminals such as paper tape readers and punches,
card readers and line printers.
Not frequently used.

Operations tend to be asynchronous
at these speeds.

Medium 300 to 3000
baud
High 5000 baud
and up

Buffered terminals such as displays,
buffered card readers, and line printer
configurations.
Intercomputer communications.

1.4 GENERAL DESCRIPTION
The DUVII is a single line, program controlled, double buffered communication interface. The purpose of this interface is to establish a data communication line between an LSI-II computer (a parallel
input/output device) and a Bell 201 or equivalent modem (a serial input/output device). The DUVll
provides serial-to-parallel and parallel-to-serial data conversion, EIA *-to-TTL (transistor-transistor
logic) and TTL-to-EIA voltage level conversion and modem control for full or half duplex communication systems.
The DUVll is compatible with all LSI-II family computers and the Bell 201 synchronous modem or
equivalent. DUVII-DA is the only version and is completely contained on the M795I quad integrated
circuit module. This module can be easily mounted in any standard LSI-II series backplane. A typical
communication system using the DUVII is shown in Figure 1-3.
Interface operation is entirely program controlled. The mode of operation (synchronous or isochronous), character length (5, 6, 7, or 8 bits plus parity if selected), parity enable and sense (odd or
even), sync character configuration, and duplex mode (full or half) are all selected via the program.

*EIA RS232C - A standardized set of signal characteristics (time duration, voltage, and current) specified by the
Electronic Industries Association.

1-6

COMMUNI CATION FACILITIES;\
SERIAL DATA AND MODEM CONTROL SIGNALS
PARALLEL
DATA

LSI-II

SERIAL DATA AND MODEM CONTROL SIGNALS

\
DUVll

COMPUTER ~=....I'.---.....,/ lNTERFACE
(SYSTEM No. I )

BELL

BELL
201 or
EQUIVALENT

1 EQ~?JA~ENT

50ft max

(15 M)

DUVll

LSI-11
COMPUTER

INTERFACE

(SYSTEM No.2)

11-4901

Figure 1-3

Typical Communications System

The interface has the following capabilities:
1.

Handles synchronous and isochronous communication data

Operates in half duplex or full duplex mode

Handles variable length characters (5, 6, 7, or 8 bits plus parity)

Generates a parity bit (odd or even) which is transmitted with the data character to the
modem

Verifies received character parity (odd or even)

Inhibits the transmitter data output for maintenance purposes

Controls the modem.

In line with these capabilities, the interface performs the following operations:
1.

Converts parallel data inputs (from the computer) to serial data outputs (to the modem)

Converts serial data inputs (from the modem) to parallel data outputs (to the computer)

Inhibits receiver operation when transmitting in the half duplex mode

Establishes synchronization prior to allowing received data to be transferred to the
computer

Provides control signals to the modem and monitors modem status lines

Generates interrupt requests to the program in response to anyone of the following conditions:
a.

Synchronized data received from the modem

Transmitter ready to accept another character for transmission

Modem status change

Sync (fill) character being transmitted to the modem.

All DUVII operating power is provided by the mounting panel in which it is installed. For proper
operation, the module requires +5 V at 1.2 A (max) and + 12 V at 0.45 A (max).
1-7

The H9270 or equivalent mounting panel connects the DUVll to the LSI-II (Q BUS). All Q BUS
input! output signals enter and leave the module via the mounting panel pins. Refer to Chapter 2 for Q
BUS to mounting panel connection. Figure 1-4 shows the major DUVll components; the rocker
switches which are used to select the interface Q BUS address, the SAT (Synchronous! Asynchronous
Transmitter) chips and option switches. (A, complete description of the option switches is provided in
Table 2-1.)

CARRIER - - - - - - ,
SERIAL DATA OUT - - - - - - ,

r - - - - DATA SET ROY
. - - - - CLR TO SEND

SERIAL DATA IN - - . . . . ,

y---

RING

TRANSMITTER
CHIP

R~CEIVER

CHIP

OPTION
SWITCHES

ADD R ESS/VECTO R
ROCKER SWITCHES
8352·1

Figure 1-4

DUVll (M7951) Major Components

1.5 SPECIFICATIONS
Environmental, electrical and performance specifications for the DUVll are contained in the following paragraphs.

1.5.1

Environmental

Ambient temperature

50 to 50 0 C (41 0 to 122 0 F)

Relative humidity

10% to 95% (without condensation)
with max wet bulb 32 0 C (90 0 F)
and min dewpoint 2 0 C (36 0 F)
1-8

1.5.2 Electrical
DC voltage requirements

+ 5 V @ 1.2 A max
+12 V @ 0.45 A max

Electrical characteristics
Electrical characteristics of this interface meet EIA standard RS-232C and LSI-II Q BUS interface
specifications.
1.5.3 Performance
The following paragraphs discuss the baud rate limitations of the DUVII and related program
response time.
1.5.3.1 Baud Rates for Synchronous Communications - EIA/CCITT* baud rate (10K baud maximum) is limited by modem and data set interface level converters. Even though the DUVII can
receive and transmit at a high rate, it may in most cases be impractical. Since the service of the data
buffers relies solely on the program, little time, if any, would be left for other events. This problem
would be compounded if the interface were operating in the full duplex mode.
1.5.3.2 Baud Rates for Isochronous Communications - EIA/CCITT baud rate (10K baud maximum)
is limited by data set interface level converters.
1.6 ENGINEERING DRAWINGS
A complete set of engineering drawings is provided with each interface. The general logic symbols used
on these drawings are described in the DEC Logic Handbook. Specific symbols and conventions are
also included in the LSI-II system manuals. The following paragraphs describe the signal nomenclature used in the drawing set.
1.6.1 Basic Signal Names
Signal names in the DUVII print set are in the following form:
SOURCE

(ASSERTION)

SIGNAL NAME

(STATE)

POLARITY

SOURCE indicates the drawing number of the print from which the signal originates. The drawing
number of a print is located in the lower right hand corner of the print title block (Dl, D2, D3, D4, D5,
and D6).
ASSERTION, normally blank (indicating true assertion), however the"" (not, negate) symbol, may be
used when appropriate.
SIGNAL NAME is the proper name of the signal. The names used on the print are also used in this
manual for correlation between the two.
STA TE is present when the signal source is a flip-flop, it is either (0) or (1).
POLARITY is either H or L to indicate the voltage level of the signal: H means + 3 V; L means
ground.

*CCITT - the Consultive Committee International Telegraph and Telephone is an advisory committee established under the United Nations to recommend worldwide standards.

1-9

For example, the signal
05 TX DONE H
originates on sheet 5 of the drawings and is read "when TX DONE is true, this signal is at +3 V."
Q BUS signal lines carry a dual source indicator. These signal names represent a bidirectional wireORed bus; as a result multiple sources for a particular bus signal exist.
1.6.2 Flip-Flop Signal Names
Flip-flop signal names add an extra dimension. Although flip-flops have only two outputs, four signal
names are possible (Figure 1-5). The two real outputs are RX DONE (1) H on pin 5 and RX DONE
(0) H on pin 6. The two additional outputs are simply the two real outputs reidentified. RX DONE (1)
L is electrically the same as RX DONE (0) Hand RX DONE (0) L is electrically the same as RX
DONE (1) H.

5
D

RX DONE (1) H
RX DONE (1) L

F/F

5
C

Figure 1-5

RX DONE (0) L
RX DONE (0) H

Flip-Flop Signal Names

1-10

CHAPTER 2
INSTALLATION

2.1
2.1.1

INSTALLATION
Mounting the DUV11 in the Computer

There is one DUVII installation configuration. This is where the DUVII-DA interfaces with the Bell
201 synchronous modem or equivalent. In this configuration the DUVll .. DA can be mounted in the
H9270, H9273 or equivalent LSI-II backplane (Figure 2-1).

POWER AND
SIGNAL CONNECTIONS

SLOTS
NOTE 2

NOTE 2

MODULE SIDE VII2W
NOTES:

1. Usually mounted in slQt 2 but could b~ in slot 3 Of 4.
2. I"SI·11 options can be mounted in any S4'ction or sections of slots;3 and 4.
11-4902

Figure 2-1

DUVII-DA Mounted in H9270

2.1.2 Installing the Modem Cable Harness
The BC05C-25 cable harness (Figure 2-2) is used to connect the DUVII-DA to the Bell 201 modem.
To install the cable, refer to Figure 2-3 and proceed as follows:

Position the Berg connector such that the connector name and pin number markings are
visible and made fully and squarely with the Berg connector on the M7951 module.

Align the cinch connector to the receptacle located on the rear of the modem.

Mate the cinch connector and tighten the two hold-down screws using a flat blade screwdriver.

,."..-

---- ------ .---

.............

25 FT HARNESS

'" "\

\
\

..
FEMALE
BERG
CONNECTOR
(DEC NO. 1209941)

(CONNECTS TO
M7951 MODULE)

MALE
CINCH
CONNECTOR
(DB-51226-1)

(CONNECTS TO
MODEM)

6808-3

Figure 2-2

BC05C-25 Cable Harness

2-2

BELL 201 MODEM
( .......) (REAR)

FEMALE CINCH CONNECTOR
MALE CINCH CONNECTOR

BC05C-25 CABLE

•

FEMALE BERG CONNECTOR
MALE BERG CONNECTOR

DUVll M7591 MODULE

11-4898

Figure 2-3

DUVII to Modem Connection

2.1.3 Installing DUVll to Null Modem
When running two systems back-to-back (without Bell 201), a null modem connector, part number
H312A, is used. This set-up is shown in Figure 2-4.

BC06C-26 CABLE HARNESS

NULL
LSI-11

MODEM

DUV11

(H312A)

DUV11
OR
( EQUIVALENT

11-5144

Figure 2-4

DUVII to Null Modem Connection

2-3

The DUVII connected to section A of the null modem (Figure 2-5) provides the clock source. This
DUVII has option switch 5 set to ON, and switch 7 set to OFF. Connection to section B of the null
modem by other than a DUVII is allowed providing the following is true:
1.

The device only takes one DEC 1489 (lC type) input unit load each at the SCT and SCR
leads.

The device must be compatible with the same series modem.

Jumper wires are connected as illustrated in Figure 2-6, and a jumper connection list is provided in
Table 2-1.

SECTION A

22 17 15

([)

(])

([)

([) ([) ([)

([)

20 16

([)

([) ([) ([)

([)

2
3

17 15

([)

(J) ([) ([)

([)

4
5

20 16

([)

([) ([) ([)

SECTION B

11·5145

Figure 2.. 5 Null Modem Connector (H312A)

2-4

11-5146

Figure 2-6

Table 2-1

Null Modem (H312A) Jumper Connections

Signal List for Jumper Connections of Null Modem H312A

Section A

Section B
Signal

Signal

EXTCLK
SCR
SCT

~~ :
...-----'-----.: SCT

SCR

17
15

RING IND
DSR

22
6

DTR

•

.,.------~------~

DTR

RINGIND
20 ••------~------~
• DSR

REQTO SD
CLR TOSD

•

5 ••- - - - - - - - - - - •. CARRIER DET

22
6
8

CARRIER DET

REQTOSD
8 . , . - - - - - - - - - •. CLR TOSD

4
5

SIG GND

7 ••-------~
• SIGGND

TRANS DATA

RECDATA

3 ••- - - - - - - - - - TRANS DATA

GND

• RECDATA

.,.---------~
•

2-5

GND

2
1 (connected internally)

2.1.4 Q BUS and Interrupt Vector Address Assignments
The Q BUS and interrupt vector addresses must be determined prior to operating the DUVll. The Q
BUS address is switch selectable as are the interrupt vector addresses (Figure 1-4 for location).
The Q BUS address (also referred to as the device address) is controlled by ten rocker switches contained in two dip switch banks E38 and E39, located in the address comparator logic. The position of
these switches determines the required address state (0 or 1) of bus address bits 12-03. If a rocker
switch is set to ON the switch contacts are closed and an address state of 1 is required on the related
address bit to address the DUV11. Hence, electrically the DUVll can have any device address within
the range of 760000 to 777777; however, Digital Equipment Corporation software requires that the
device address fall within the floating address range of 760010 to 763776. The device address is set to
160010 (760010) at the factory tofacilitate manufacturing testing. The switch setting for address selection is given in Table 2-2.
NOTE
If a device address is selected which falls outside the
floating address range, the software must be modified accordingly.

Table 2-2
Module
Switch No. 1
Bit No.
12

2
11

Guide for Setting Switches to Select Device Address

3
10

E38
4
9

5
8

6
7

7
6

E39
1
4
ON
ON

ON
ON
ON
ON

2
3

Device
Address

760010
760020
760030
760040
760050
760060
760070
760100
760200
760300
760400
760500
760600
760700
761000
762000
763000
764000

ON
ON

ON
ON
ON
ON
ON
ON
ON

ON
ON

ON
ON
ON

NOTES
1. ON means switch closed to respond to logical 1 on the Q BUS.
2. Switch numbers are physical in switch package at E38 and E39.

2-6

The interrupt vector addresses are also floating and are set to 770 8 at the factory to facilitate manufacturing testing. If it is necessary to change the vector address, simply change the six vector select
switches contained in one dip switch bank E39 as required. These switches control vector address bits
08-03, hence, vector addresses can be generated within the range of 000 to 774; however software
requires that the vector address fall within the floating address range of 300 to 777. The switch setting
for vector address selection is given in Table 2-3.
NOTE
If a vector address is selected which falls outside the
floating address range, the software must be modified accordingly.

Table 2-3

Guide for Setting Switches to Select Vector Address

Switch No. 3
8
Bit No.

ON
ON
ON
ON
ON
ON
ON
ON

ON
ON
ON
ON

8
3

ON
ON
ON
ON

Vector
Address
300
310
320
330
340
350
360
370
400
500
600

700

NOTES
1. ON means switch closed to produce a logical 1 on the Q BUS.
2. Switch numbers are physical positions in switch package at E39.

The address and vector selection switch banks E38 and E39 respectively are shown on engineering
drawing Dl.
2.1.5 Jumper Functions
Jumpers are used in the DUVII to increase flexibility and to provide optional input/output points for
the EIA signals via the backplane. This is an expansion feature and is not implemented to the basic
DUVII-DA.

2-7

MODEM
CABLE
(BC05C·25)

CINCH
CONNECTOR

iI1lk. . . . . .IIIiIII\IIfIlII~~!f!tf

INSTALl... CINCH
CONNECTOR
HERE
MODEM
TEST
CONNECTOR
H315A
6808·2

Figure 2-7

Modem Test Connection Installation

2-9

CHAPTER 3
DEVICE REGISTERS
AND INTERRUPT REQUESTS

3.1 SCOPE
This chapter provides a complete description of the DUVII device registers and the interrupt requests
employed to service those registers.
3.2 DEVICE REGISTERS
All software control of the DUVII is performed by means of five device registers. These registers have
been assigned bus addresses and can be read or loaded (with the exceptions noted) using any LSI-II
instruction referring to their addresses. Address assignments can be changed via the rocker switches to
correspond to any address within the floating address range of 160010 to 163776.
3.2.1 Register Address Assignments
The five device registers and associated DUVII addresses are listed in Table 3-1. Note that these
registers are byte addressable.
Table 3-1

DUVll Register Address Assignments

Mnemonic

Address

Program Capability

Receiver Status Register
Receiver Data Buffer
Parameter Status Register
Transmitter Status Register
Transmitter Data Buffer

RXCSR
RXDBUF
PARCSR
TXCSR
TXDBUF

16XXXO
16XXX2
16XXX2
16XXX4
16XXX6

Read/Write
Read Only
Write Only
Read/Write
Write Only

xxx = Selected in accordance with floating device address scheme.
3.2.2 Register Title and Bit Assignments
Each of the five device registers plays a specific role in controlling and monitoring DUVII operation.
Register titles, bit titles, and read/write capability labeling are intended to facilitate the programmer's
understanding of the purpose of each register relative to interface operation and to simplify software
preparation.
3.2.2.1

Title Assignments - Register titles and functions are listed below:

RXCSR - Programmed and monitored (read/write) to control the RCVR (receiver) portion
of the interface; to communicate interface status, requests, and supervisory data to the
modem; and to monitor status and supervisory data inputs from the modem.

RXDBUF - Monitored (read only) to detect interface RCVR status flags and RCVR parallel data outputs.
3-1

PARCSR - Programmed (write only) to establish the overall operating parameters of the
DUVll, i.e., the mode of operation (synchronous or isochronous), word length (5, 6, 7, or 8
bits plus parity), parity (enabled or disabled), parity sense (odd or even), and sync character
configuration.

TXCSR - Programmed and monitored (read/write) to control the XMTR (transmitter)
portion of the interface, to control the resetting and initialization of the interface, and to
control and monitor the maintenance mode operation of the interface.

TXDBUF - Programmed (write only) to provide parallel data to the interface XMTR for
serial transmission to the modem.

3.2.2.2 Bit Assignments - Bit assignments for the five DUVII registers are shown in Figure 3~1. The
bit names indicate the function of the bit. The bits that are defined as not used or write~only are always
read as O. In the same respect, attempts to program the not used bits or read-only bits have no effect on
the bit.

11-4900

Receiver Status Register (RXCSR)

11 ....- - - -... 08

07··-------------------------.·00

NOT USED

RCVR DATA

~I..~-----------------------------READ ONLy------------------------------~.1
11- 2240

Receiver Data Buffer (RXDBUF)

07 ...--------------------+. 00

SYNC REGISTER
1...- - - - - - - - - - - - - - - - - - - - - - WR ITE ON Ly ------------------------~.I
11-2241

Parameter Status Register (PARCSR)
Figure 3-1

DUVII Register Configurations and Bit Assignments (Sheet 1 of 2)

3-2

NOT USED
R/W
11-4899

Transmitter Status Register (TXCSR)

. 4 - - - - - - - - - - - - - - - . . 08

07 ...- - - - - - - - - - - - - -•• 00

XMTR DATA

NOT USED

\ . 4 - - - - - - - - - - - - - - - - W R I T E ONLY------------------------.~\
11- 2243

Transmitter Data Buffer Register (TXDBUF)
Figure 3-1

DUVII Register Configurations and Bit Assignments (Sheet 2 of 2)

The following figures and tables describe register content. Figures 3-2 through 3-6 illustrate the register
formats. Tables 3-2 through 3-6 list bit descriptions.
The mnemonic INIT is used frequently in the tables and refers to the initialization signal generated by
the processor. The processor will issue an INIT signal for anyone of the following conditions:
1.
2.
3.

A programmed RESET instruction is processed.
The processor GO function is activated.
The power fail sequence occurs.

During a power fail sequence, IN IT is asserted when power is going down and again when power is
coming up.

11-4900

Figure 3-2

Receiver Status Register (RXCSR)

3-3

Table 3-2

Receiver Status Register Bit Description

Bit

Name

Description

DAT SET CH
(Data Set Change)

When set, this bit indicates a modem status change.
This bit is set by a transition of any of the following
lines:
•
•
•
•
•

Ring
Clear To Send
Carrier
Secondary Received Data
Data Set Ready

If bit 05 of this register is set, the setting of this bit
will cause a RCVR interrupt.
Read-only bit; cleared by INIT, master reset, and
the DTI SEL 0 (RXCSR read strobe).
14

RING
(Ring)

This bit reflects the state of the modem ring line.
When set, this bit indicates that a ring signal is
being received from the modem. Read-only bit.

CLR TO SD
(Clear to Send)

This bit reflects the state of the clear to send line
from the modem. When set, this bit indicates that
the modem is ready to accept data from the interface for transmission. Read-only bit.

CARRIER
(Carrier)

This bit reflects the state of the modem carrier.
When set, this bit indicates the carrier is up. Readonly bit.

REC ACT
(Receiver Active)

When the internal synchronous mode is selected,
this bit is set when the proper number of contiguous sync characters (either 1 or 2, normally set
for 2) have been received. If external synchronous
or isochronous mode is selected, this bit follows the
state of the search sync bit (bit 04 of this register).
Refer to Paragraph 5.3 for RCVR synchronization
information.
Read-only; cleared by INIT, master reset, and
SCH SYNC (1) H (search sync) making 1 to 0 transition.

SEC RCV DAT
(Secondary Receive Data)

This bit reflects the state of the secondary receive
data line from the modem.
This bit provides a receive channel for supervisory
data from the modem to the processor. Read-only
bit.

3-4

Table 3-2

Receiver Status Register Bit Description (Cont)

Bit

Name

Description

DAT SET RDY
(Data Set Ready)

This bit reflects the state of the data set ready line
from the modem. When set, this bit indicates that
the modem is powered up and ready. Read-only
bit.

STRIP SYNC
(Strip sync)

This bit determines whether sync characters
received from the modem are to be presented to the
program for reading. When this bit is set, receive
characters that match the contents of the sync register do not cause a RCVR interrupt provided no
errors are detected, i.e., bit 15 of the RXDBUF is
clear.
Read/write bit; cleared by INIT and master reset.

RX DONE
(Receiver Done)

This bit is set when synchronization has been
achieved and a character has been loaded into the
RXDBUF, provided the STRIP SYNC bit is not
set. If the STRIP SYNC bit is set and the received
character is a sync character without errors, i.e., bit
15 of the RXDBUF is clear, this bit will not be set.
When set, this bit will cause a RCVR interrupt
request provided bit 06 of this register is set.
Read-only bit; cleared by INIT, master reset, and
the DTI SEL 2 (RXDBUF read strobe).

RXINTEB
(Receiver Interrupt Enable)

When set, allows a RCVR interrupt request to be
generated when the RX DONE bit is set.
Read/Write bit; cleared by INIT and master reset.

DAT SET INTEB
(Data Set Interrupt Enable)

When set, allows a RCVR interrupt request to be
generated when the DAT SETCH bit is set.

SCH SYNC
(Search Sync)

When set in the internal synchronous mode,
enables the RCVR synchronization logic and
causes the RCVR to start comparing incoming
data bits to the contents of the sync register in an
attempt to recognize a sync character.
When set in the isochronous mode, enables the RX
DONE flag generation logic.
When set in the external synchronous mode,
enables the RX DONE flag generation logic and
causes the RCVR to start framing incoming characters.
Read/write bit; cleared by IN IT and master reset.
3-5

Table 3-2

Receiver Status Register Bit Description (Cont)

Bit

Name

Description

SEC XMIT
(Secondary Transmit Data)

This bit reflects the state of the secondary transmit
data line to the modem. This bit provides a transmit channel for supervisory data from the processor to the modem.
Read/write bit; cleared by IN IT and master reset.

REQ TO SD
(Request to Send)

When set, this bit causes the request to send line to
the modem to be asserted. The request to send line
is a control lead to the modem. This line must be
asserted before the interface can transmit data to
the modem.
Read/write bit, optionally cleared by INIT and
master reset.

DATA TERM RDY
(Data Terminal Ready)

When set, this bit indicates the interface is powered
up, programmed, and ready to receive data from
the modem.
Setting this bit causes the data terminal ready line
to the modem to be asserted. The data terminal
ready line is a control lead for the modem communication channel. When asserted, it permits the interface to be connected to the channel.
Read/write bit; optionally cleared by INIT and
master reset.

11 .4----.~ 08

07.4----------------.~

NOT USED

RCVR DATA

I~4~------------------------~READ ONLY----------------------------~~I
11- 2240

Figure 3-3

Receiver Data Buffer (RXDBUF)

3-6

Table 3-3

Receiver Data Buffer Bit Description

Bit

Name

Description

RX ERR
(Receiver Error)

This bit is set whenever one of the three receiver
error bits is set (logical OR of bits 14, 13, and 12).
Read-only bit; cleared only when bits 14, 13, and
12 are cleared.

OVRN ERR
(Overrun Error)

When set, this bit indicates that the processor has
failed to service the RX DONE flag within the time
required to load another character into the
RXDBUF, i.e., O/baud rate) X (bits per character) seconds. Hence, the previous character was
overwritten (lost). This condition indicates the loss
of at least one character.
Read-only bit; cleared by INIT, master reset, and
DTI SEL 2 (RXDBUF read strobe).

FRM ERR
(Framing Error)

When set, indicates that character received was not
followed by a valid STOP bit. This error only
occurs in the isochronous mode of operation.
Read-only bit; cleared by IN IT , master reset, and
DTI SEL 2.

PAR ERR
(Parity Error)

When set, indicates that the parity of the received
character does not agree with the parity programmed (odd or even). If parity is not programmed,
this bit is always cleared.
Read-only bit; cleared by IN IT , master reset, and
DTI SEL 2.

07-00

RCVR DATA
(Receiver Data)

This register holds the received character for transfer to the program. The buffer is right justified for
5, 6, 7, or 8 bits. If parity is received it is also
loaded into the buffer at the next vacant higher
order bit position. Therefore, if a 5-bit character
plus parity is framed by the RCVR, the parity bit
would be loaded into bit position 05 in the
RXDBUF and presented to the program for reading. If an 8-bit character plus parity is framed, the
parity bit would not be presented to the program
for reading.
Read-only buffer; cannot be cleared, IN IT or master reset sets the buffer to all ones. Reading the
RDXBUF causes the RXDONE bit in the RXCSR
to clear.

3-7

0 7 . 4 - - - - - - - - - - - - - - - - - - - - - - - -•• 00
SYNC REGISTER

I...- - - - - - - - - - - - - - W R I T E O N L Y - - - - - - - - - - - - - - - - + t · 1
11-2241

Figure 3-4

Parameter Status Register (PARCSR)

Table 3-4

Parameter Status Register Bit Description

Bit

Name

Description

13 and 12

MODE SEL
(Mode Select)

These bits control the mode of operation. Modes
are selected as follows:
Mode

Bit 13

Bit 12

Internal
Synchronous

External
Synchronous
Isochronous

Illegal (Not Used)

Write-only bits.
11 and 10

WORD LENSEL
(W ord Length Select)

These bits control the length of characters received
and transmitted by interface. Word length (not
induding parity) is selected as follows:
Bits per Character

Bit 11

Bit 10

0
0
1
1

0
1
0
1

6
7
8
Write-only bits.
09

PAR ENB

If this bit is set, parity for each character will be
(parity enable) generated by the XMTR and
checked by the RCVR. If character length is less
than eight bits, the parity bit for received data is
loaded into the RXDBUF for reading by the program. If bad parity is detected at the RCVR, the
parity error flag is set (bit 12 of the RXDBUF).
Write-only bit.

3-8

Table 3-4

Parameter Status Register Bit Description (Cont)

Bit

Name

Description

PAR SEN SEL
(Parity Sense Select)

When the parity enable bit (bit 09 of this register) is
set, the sense of the parity (odd or even) is controlled by this bit. When this bit is set, even parity
is generated by the XMTR and checked for by the
RCVR (the program does not have to provide a
parity bit to the XMTR). When this bit is cleared,
odd parity is generated and checked.
Write-only bit.

07-00

Sync Register

This register contains the sync character. The sync
character is used by the RCVR to detect received
sync characters and thereby achieve synchronization.
The sync character is used as a fill character by the
XMTR when operating in the synchronous mode.
Fill characters are operating in the synchronous
mode. Fill characters are transmitted when the
program fails to provide characters to the XMTR
fast enough to maintain continuous transmission,
i.e., (l/baud rate) X (bits per character) seconds 1/2 (bit time).

11-4899

Figure 3-5

Transmitter Status Register (TXCSR)

3-9

Table 3-5

Transmitter Status Register Bit Description

Bit

Name

Description

DNA
(Data Not Available)

This bit is set by the XMTR when a fill character is
transmitted. This applies only to the synchronous
mode of operation and is caused by late program
response to a TX DONE interrupt request.
The processor response to TX DONE must be
within (l/baud rate) X (bits per character) seconds
- 1/2 (bit time). If not, the fill character is transmitted.

If bit 05 of this register is set, setting this bit causes
an XMTR interrupt request.
Read-only bit; cleared by INIT, master reset, and
DTI SEl 4 (TXCSR read strobe).
14

MAINT DATA
(Maintenance Data)

This bit is used in the internal loop and external
loop maintenance modes by the diagnostic program to simulate serial input to the RCVR. Refer
to Chapter 6 for more detailed information on the
use of this bit.
Read/write bit; cleared by INIT or master reset.

SS ClK
(Single Step
Maintenance Clock)

This bit is used in the internal loop and external
loop maintenance modes by the diagnostic program to simulate the XMTR and RCVR clocks.
Refer to Chapter 6 for more detailed information
on the use of this bit.
Read/write bit; cleared by IN IT or master reset.

12 and 11

MSOI/MSOO
(Maintenance Mode
Select 01 & 00)

These bits are used to select the normal mode of
operation or one of three maintenance modes.
Modes are selected as follows:
Mode

Bit 12

Bit 11

Normal

Internal Maintenance
loop

External Maintenance
loop

System Test
Refer to Chapter 6 for more detailed information
on the maintenance modes and their use.
Read/write bits; cleared by INIT and master reset.
3-10

Table 3-5

Transmitter Status Register Bit Description (Cont)

Bit

Name

Description

RXINP
(Receiver Input)

This bit monitors the RCVR input in the internal
loop and external loop maintenance modes.
Read-only.

MSTRST
(Master Reset)

This bit is used to generate a CLR (clear) pulse,
which initializes the registers and the XMTR and
RCVR and inhibits the BRPL Y L (bus reply) signal. Refer to Chapter 4 for more detailed information on the effects of the CLR pUlse. This bit
remains at a (1) for only 3 J.Ls after being set
Read/write.

TX DONE
(Transmitter Done)

This bit is set by INIT and master reset and when
the first bit of the character contained in the
XMTR register is placed on the XMTR output
line. If bit 06 of this register is set when this bit is
set, an XMTR interrupt request is generated.
Read-only bit; cleared by LD TXDBUF
(TXDBUF load strobe).

TXINTEB
(Transmitter Interrupt
Enable)

When set, this bit allows an XMTR interrupt
request to be generated by the TX DONE bit.
Read/write bit; cleared by IN IT and master reset.

DNA INTEB
(Data Not Available
Interrupt Enable

When set, this bit allows a XMTR interrupt
request to be generated by the DNA bit.
Read/write bit; cleared by IN IT and master reset.

SEND
(Send)

When set, this bit enables the XMTR and transmission will start when a character is loaded into
the TXDBUF. This bit must remain set until the
entire message is transmitted. If not, transmission
of the character currently in the XMTR register is
completed and the XMTR will enter the idle state.
Read/write bit; cleared by INIT and master reset.

HALF DUP
(Half Duplex)

When this bit is set, operation will be in the half
duplex mode. In this mode the RCVR is disabled
whenever bit 04 of this register is set.
Read/write bit; cleared by INIT and master reset.

3-11

Table 3-5

Transmitter Status Register Bit Description (Cont)

Bit

Name

Description

BREAK
(Break)

When this bit is set, the serial XMTR output D5
SERIAL DATA OUT H is held in the space (constant low) condition; otherwise, operation is normal. This bit is used by the diagnostic program in
the internal loop or external loop maintenance
modes to inhibit the XMTR output while inputting
data to the RCVR via bit 14 of this register.
Read/write bit; cleared by INIT and master reset.

15 ...- - - - - - - - - - - -.... 08

07 ...- - - - - - - - - - - - - - + . 00

NOT USED

XMTR DATA

I...-------------------------WRITE ONLY--------------------~·i
11- 2243

Figure 3-6

Transmitter Data Buffer (TXDBUF)

Table 3-6

Transmitter Data Buffer Bit Description

Bit

Name

Description

07-00

XMTR DATA
(Transmitter Data)

This register is loaded by the program with the
character to be transmitted. Character length is
from 5 to 8 bits. The character is right-hand justified. If a parity bit is enabled, it is generated by the
interface.
Write-only bits; an IN IT or master reset places all
ones in this register.

3.3 INTERRUPT REQUESTS
The DUV11 uses interrupts to gain control of the bus, thereby causing the processor to branch to a
service subroutine.
The interface uses two interrupt vectors: one for the RCVR section and one for the XMTR section. If
simultaneous RCVR and XMTR interrupt requests occur, the RCVR has priority.

3-12

Both the XMTR and RCVR sections of the interrupt control logic handle interrupt requests from two
sources. A XMTR interrupt request is generated by the setting of the TX DONE bit or the DNA bit
provided the TX INTEB and the DNA INTEB bits are set. A RCVR interrupt request is generated by
setting the RXDONE bit or the DA T SET CH bit, provided the RX INTEB and DA T SET INTEB
bits are set.
The DUVll interrupt vector addresses are floating. The vector addresses can be changed via switches
E39-3 to E39-8 in the interrupt control logic.

NOTE
If the DUVll interrupt vector address is changed, all
DEC programs or other software referring to the
interrupt vector addresses must also be changed.

3-13

CHAPTER 4
THEORY OF OPERATION

4.1 SCOPE
This chapter contains both general data flow and specific logic interactions that allow the DUVII
interface to function. As the discussions develop, frequent reference will be made to the DUVII engineering drawing set provided with each unit.
4.2 INITIALIZATION AND PROGRAMMING
Before the DUVII interface can begin to handle data, it must be initialized and programmed.
Initializing the interface prepares it to be programmed. All registers are initialized, all flip-flops are
cleared, and the RCVR and XMTR are forced to the idle state. When the RCVR is in the idle state, the
RXDBUF (receiver data buffer) is set to all Is, the RCVR sync register is cleared, and the RCVR
timing and control logic and output flags are cleared. When the XMTR is in the idle state, the XMTR
output is a constant MARK (high), the XMTR timing and control logic is cleared, and the XMTR
output flags are set.
Programming the DUVII establishes its operating parameters. General operating parameters are controlled by the PARCSR (parameter status register), while specific operating parameters pertaining
directly to the RCVR, XMTR, and maintenance circuitry are controlled by the RXCSR (receiver
status register) and the TXCSR (transmitter status register). The PARCSR is programmed to select the
mode of operation (isochronous, internal synchronous, or external synchronous), word length (5, 6, 7,
or 8 bits plus parity), (enable or disable), parity sense (odd or even), and sync character configuration.
The RXCSR is programmed to enable or disable the RCVR data handling logic, strip sync logic and
interrupt logic, and to communicate interface status, requests and supervisory data to the modem. The
TXCSR is programmed to select the maintenance mode (normal, internal loop, external loop, and
system test); drive the maintenance clock; provide a maintenance data input; reset and initialize the
overall interface; enable or disable the XMTR data handling logic, data output logic, and interrupt
logic; and select the interface duplex mode (half or full).
4.3 OVERALL DATA FLOW
Once the interface is programmed, data communication can commence. Data communication can be
initiated by the program or by the modem operator. The program initiates communication simply by
loading a character into the TXDBUF. The XMTR then outputs that character to the modem, which
transmits it to the modem at a remote station. The modem operator initiates data communication by
dialing a remote station on the modem. The modem at the remote station detects the call and responds
by asserting ring to its own interface. The interface then generates a RCVR interrupt which causes the
processor to branch to an interrupt service subroutine. The service subroutine directs the processor to
execute the handshaking sequence and load a character into the TXDBUF. If the XMTR is enabled
[SEND (l) H asserted], the XMTR begins to output the character to the modem and asserts TX
DONE H to request the next character of the message. The modem transmits the character to the
modem that placed the call. If more characters are to be transmitted, the program responds to the TX
DONE H flag and loads the next character into the TXDBUF. When transmission of the current
character is complete, transmission of the next character begins. When all characters comprising the
message have been loaded into the TXDBUF and TX DONE H is asserted, the program clears SEND
(1) H.
4-1

As soon as transmission of the current character is complete, the XMTR output marks (constant
high). Note that TX DONE H will not change state after SEND (1) H is cleared.
If during message transmission, the program fails to load the TXDBUF before current character
transmission is complete, one of two operations will result, depending on the mode of operation. If the
XMTR is programmed for the synchronous mode, a sync character will be output to maintain synchronization with the RCVR (synchronous mode requires continuous transmission). If the isochronous mode is programmed,· the XMTR will simply pause until the next character is loaded into the
TXDBUF and then resume operation.

Data reception is initiated when input data is provided to the RCVR, provided SCH SYNC(l) H is
asserted. Before the RCVR can begin framing characters for reading by the program, however, REC
ACT( 1) H must assert indicating that the RCVR at the receiving station is synchronized with the
XMTR at the sending station. Once REC ACT(l) H asserts, the RCVR frames the very next character,
transfers the character to the RXDBUF, and asserts RX DONE(l) H. This assertion causes a RCVR
interrupt request to be generated. The processor branches to an interrupt service subroutine and ultimately reads the RXDBUF. If the program fails to read the RXDBUF before the next character is
framed and transferred to the RXDBUF, the character previously framed is lost and OVRN ERR H
(overrun error) is asserted.
4.4 FUNCTIONAL BLOCK DESCRIPTION
The DUV 11 can be divided into six functional blocks, each performing a specific task within the
interface. A brief description of each of these blocks is provided in the following paragraphs (Figure
4-1).

4.4.1 Address Comparator and Command Decoder
This block provides the actual interface with the LSI-II Q BUS. Preset address selection rocker
switc.hes are compared to the addressing lines from the Q BUS. If the addresses compare, information
in the form of controls and data are exchanged by transceivers within this functional block.
Control of data to and from the QDL BUS of the DUVII to the Q BUS linking the LSI-II is under the
gating of the command decoder. The command decoder receives its controls from the Q BUS via the
address comparator and direct connection.
4.4.2 Data Multiplexer
The data multiplexer controls the data and status information to the transceivers which is outputted
onto· the Q BUS. The multiplexer receives status data from the modem interface logic, the receiver
logic and transmitter logic. This information is released to the QDL BUS for transfer to the transceivers under control of the command decoder.
4.4.3 . Modem Interface Logic
This block contains the EIA level converters which convert the logic level signals to the voltage levels
of the Bell 201 modem. This block contains the transmit data line to the modem and serial data in, as
well as access to all the modem control signals.
4.4.4 Receiver Logic
The logic necessary to receive the serial data from another communications system and convert it to
parallel data is contained in this block. This includes the receiving section of the parameter control
status register, the receiver control status register, the receiver data buffer and other associated receiver
logic. This block contains the SAR chip.

4-2

RX DONE
CONTROL
LINES

INTERRUPT
CONTROL LINES
DATA AND
CONTROL

(06)

RCVR LOGIC

SERIAL DATA IN

(04)

DATA SET CH
TX DONE, DNA

MODEM
INTERFACE
LOGIC

VECTOR
ENABLES

DATA
AND
CONTROL

TO
MODEM
( BELL 201
OR
EQUIVALENT)

IX!

~L BUS (QDLOO THROUGH 15)

V1DDRESS~
NONTROLV

ADDRESS
COMPARATOR!
COMMAND
DECODER
SEL 2, SEL 4

(01)

DATA AND
CONTROL

)

XMIT LOGIC
(05)

SERIAL DATA OUT
(03)

DATA
MUL TIPLEXER
(02)

NOTE:

( ) indicates engineering drawing sheet of logical block.
11·5151

Figure 4-1 DUVl1 Functional
Block Diagram
4-3

4.4.5 Transmitter Logic
The logic necessary to change the parallel data from the Q BUS to serial data for transmission over
communication lines is contained in this block. This includes the transmission section of the parameter
control status register, the transmitter control status register, the transmitter data buffer and other
associated transmitter logic.
4.4.6 Interrupt Control Logic
The interrupt control logic enables the DUVII to become bus master, and causes a program interrupt
to an interrupt address vector. When an interrupt request is generated the interrupt control logic is
enabled, the bus is requested and granted, the interrupt is identified and acknowledged, the processor
branches to the subroutine identified by the vector address and then services the interrupt.
4.5 DETAILED FUNCTIONAL DESCRIPTION
The following paragraphs contain further details on the signal flow and functions of the major components comprising the DUVII.
4.5.1 Address Comparator (Engineering Drawing Dl)
The address comparator logic is made up of the bus transceivers and address/vector rocker switches.
The rocker switches are set before operating the DUVl1. When the LSI-II addresses the DUVll, the
bus transceivers compare the preset address with the address on the Q BUS (BDAL 00 through 15 as
shown on engineering drawing D 1). If they compare, the MATCH signal is asserted which enables the
command decoder (DC004 chip). Information then received at the transceivers is passed from the Q
BUS to the QDL BUS (QDL 00 through QDL 15) under control of the command decoder. Signal
INWDB H enables the transceivers to receive data from the Q BUS and place that data onto the QDL
BUS. This signal originates from the Q BUS as BDIN L (engineering drawing D6), which is driven to
become DIN L. DIN L is applied to the command decoder and is output as INWD L when MATCH
is asserted by the address comparator. INWD L is then gated to become INWDB L. Similarly, the
signals SEL 0 L, SEL 2 L, and SEL 4 L which are functions of QDL 00, QDL 01 and QDL 02, when
MATCH is asserted to the command decoder, are gated to become EN QDL TO BDAL. This signal
enables data from the QDL BUS which is applied to the transceivers to pass on to the Q BUS.
During an interrupt sequence the address comparator circuitry provides passage of the preset interrupt
vector address to the Q BUS.
4.5.2 Command Decoder (DC004 Chip as Shown on Enginering Drawing Dl)
The command decoder logic controls the flow of data into the status registers within the DUV11 and
the passage of status information and data back out to the CPU.
The signals which enable the registers of the DUVII such as LD PARCSR, LD TXDBUF etc., are
generated by gating the outputs of the command decoder (refer to engineering drawing D 1). This logic
receives bits 00 through 02 from the QDL BUS. When the address comparator outputs MATCH, these
bus bits cause the command decoder logic to output the proper select signal. For example if the control
logic selector asserts SEL 6 L along with OUTLB L the resultant gated output is LD TXDBUF (1) L,
which causes the transmitter data buffer to load parallel data from the QDL BUS.
4.5.3 Data Multiplexer (Engineering Drawing D2)
As mentioned earlier, the data multiplexer controls the passage of DUVll status signals and data to
the bus transceivers for output to the CPU. Two signals, SEL 2 Land SEL 4 L enable the selection of
status signals and data which will pass on to the QDL BUS. A truth table containing these enables and
resultant outputs are shown in the legend at the top of engineering drawing D2.
4.5.4 Modem Interface Logic
The modem interface logic contains level converters to change the logic level signals to the operating
voltage levels of the Bell 201 modem. All logic signals ranging from 2.4 to 3.5 V are converted to +6 V.
All ground (0 V) logic signals are converted to -6 V. This circuitry is shown on engineering drawing
D3.
4-5

4.5.5 Receiver Control Logic
The receiver circuitry contains the synchronous/ asynchronous receiver chip (SAR) and its supportive
logic. Within the SAR, serial data received from the modem is converted to parallel data for output
onto the QDL BUS. Parameter data is supplied via the QDL BUS. PARCSR (1) L loads this data into
SAR (engineering drawing D4). Having stored these parameters, the receiver detects the serial received
character, accomplishes synchronization, frames the received character, detects errors, raises the
RXDONE flag and holds the framed character (for program reading) until the next character is
framed.
Once the RCVR logic is enabled, it operates as programmed. The SCH SYNC input enables the
RCVR logic. The contents of the PARCSR determine:
I.

Mode of operation (internal synchronous, external synchronous, or isochronous)

Length of character to be framed (5, 6, 7, or 8 bits plus parity)

Parity (enabled or disabled)

Parity sense (odd or even)

Sync character configuration.

The method of achieving synchronization is the principle difference between the modes of operation.
I.

In the internal synchronous mode, two contiguous sync characters must be recognized by
the RCVR logic to achieve synchronization. Once synchronization is achieved, the RCVR
starts framing on the very next character bit. The received characters must arrive at the
RCVR in a continuous serial bit stream or synchronization will be lost.

The external synchronous mode is designed for UEe with communication equipment which
accomplishes synchronization external to the DUVII interface. The external synchronization logic prohibits RCVR operation by inhibiting the assertion of SCH SYNC until
synchronization with the XMTR has been achieved. When external synchronization is
achieved, SCH SYNC asserts, forcing the RCVR logic to the synchronized state. The
RCVR then starts framing immediately, beginning with the very next character bit.

In the isochronous mode, each received character is preceded by a start bit and succeeded by
a stop bit, which serves to synchronize the RCVR. In this mode, the receiver simply does not
start framing until it recognizes a start bit. It then frames the character following the start bit
and looks for a stop bit. If a stop bit is not detected, the character received is considered
invalid, flagged as such, and held for reading by the program. Hence, in the isochronous
mode, characters need not be preceded by sync characters and need not arrive contiguously
at the RCVR.

The strip synchronization character (STRIP SYNC) input determines whether received sync characters are to be permitted to set the RX DONE flag. If STRIP SYNC is asserted, all sync characters are
discarded provided no errors are detected.
For an illustration of receiver timing involved in internal and external synchronous and isochronous
modes of operation refer to Figures 4-2, 4 .. 3, and 4-4. For a more detailed description of the SAR chip
refer to Appendix B.

4-6

CLR H $ ( R C V R INITIALIZED)

LDPARCSRIO)H

---------------------------------------------------------------------------------------------------------------------------------------------------

SYNC INTR H

LDTXCSRHB/LBH ____________~r__l~

LD RXCSR HB/LB H _____________
5CH SYNC (1) H

______________________________________________________________________________________--------------------------------------------------------------______~----------________-------------------------

-+~.. IRCVR PROGRAMMING COMPLETE)
___

STRIP SYNC (1) H _ - - - - - - - - - - - - - - - - '
SYNC (I) L

RX CLK H

(RCVR ENABLED)

----'

M DET H

400nS

MATCH L

--------------------------------+-------------------~~/

DATA ROY L

RST CHAR L

PAR ERR H

1\\

RX ERR H

REC

------------------------------------------------------------------------\~--------------------------------------------------------------------------~~--_r_7~------------------------~

ACT(I)H~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~:jI~:~~~~:\\\~~::~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~:~~~~~~~~~~~~~~~~~~:~~:::::-(-R-C-V-R--LO-G-I-C-S-Y-N-C-H-R-O-N-IZ-E-D-)----~/

RXDONE(I)H _________________________________________

I
I

-----------------------------tl ----------~I------_----------------------------------------------------------------------~--~----------------____~__--'

DTl SEL 2L

CLR STA·DRL

SYNC CHARACTER
RECOGNIZED

SYNCHRONIZATION
NOT ACH IEVED

~r~-4-0-0-ns----------------------------------------------------------------------------~-,

SYNC CHARACTER
NOT RECOGNIZED

SYNC CHARACTER
RECOGNIZED

SYNCHRONIZATION
ACHIEVED

PARITY ERROR AND RX
DONE FLAGS RAISED

PROGRAM READS
RXDBUF
11-2322

Figure 4-2 Receiver Internal
Timing Diagram
4-7

CLR H

lD PA RCSR (O)H

SYNC INTR H

lD TXCSR HB/lB H

______~Il~____________________________________________________

lD RXCSR HB/l B H

(RCVR PROGRAMMING COMPLETE)

SCH SYNC (1) H

STRI P SYNC (1) H

(RCVR ENABLED)

SYNC (1) l

SERIAL RCVR
INPUT

RX elK H

REC ACT (1)H

_ _ _ _ _ _ __ _--J(RCVR SYNCHRONIZED)

MDET H

MATCH l

DATA ROY l

RST CHAR l

RX DONE (1) H

DTI SEl 2 l

ClR STA· DR l
400ns

SYNC CHARACTER
STRIPPED

RX DONE
FLAG RAISED

PROGRAM READS
RXDBUF
"-23 Z4

Figure 4-3 Receiver External
Synchronous Timing Diagram

4-9

CLRH;f

LD PARCS. (lIH ~
SYNC INTR H

L_______________________________________________________________________________________________________________________________________________________________________________________________

ISOC H
LDTXCSR HB/LBH

r--lL______________________________________________________________________________________________________________________________________________________________________________________

LD RXCSR HB/LB H

SCH SYNC(1l H

--------------+-~
STRIP SYNC (1lH

---------------rl~

SYNC (IlL

SERIAL RCVR INPUT

-------+-------,

RX CLK H
RECACT(llH

MDET H

----------------------------------------------------------------------------------~
MATCH L

--------------------------------------------~
DATA ROY L

RST CHAR L

FRM ERR H

PAR ERR H

------------------------------------------------------~----------------~~----------------------------i_------r-------------------~----7_--------------~~~--T_----------------~

RX ERR H _____________________________________________________~------------------~--------------------------+_--

____-+______________________

~--~

RX DONE(1 1 H

--------------------------------------------~
DTI SEL 2 L
CLR STA 'DRL

RX DONE
FLAG RAISED

PROGRAM READS
RXDBUF
AND SYNC CHARACTER STRIPPED

RX DONE
AND FE FLAGS RAISED

PROGRAM READS
RXDBUF, RX DONE
AND PE FLAGS RAISED
11- 2325

Figure 4-4 Receiver Isochronous
Timing Diagram
4-11

4.5.6 Transmitter Control Logic
The transmitter circuitry contains the synchronous/asynchronous transmitter chip (SAT) and its supportive logic. The SAT accepts parallel characters from the program, raises the TX OON E flag to
request the next character, and serially outputs the current character to the modem. Before transmitter
operation can begin, the transmitter logic must be initialized and the PARCSR and TXCSR registers
programmed (engineering drawing 05).

The high order bits from the QOL BUS are loaded into the TXCSR when signal LO TXCSR HB H is
asserted. The low order bits are loaded into the TXCSR when LO TXCSR LB H is asserted. The signal
LD PARCSR (I) L asserted enables parameter data into the SAT.
The signal SEND (I) H enables the transmitter logic. Once the transmitter is enabled, it operates as
programmed. The contents of the PARCSR determine:
I.

Mode of operation (synchronous or isochronous)

Length of character to be transmitted (5, 6, 7, or 8 bits plus parity)

Parity (enabled or disabled)

Parity sense (odd or even)

Sync character configuration (used as fill character in synchronous mode).

There are distinct differences between the two modes of operation:
1.

In the synchronous mode, the XMTR receives a parallel transmit character from the program, generates parity if programmed, serially outputs the character plus parity to the
modem, and raises the TX DONE flag to request the next character. If the program fails to
provide the next character before transmission of the current character is complete, the
XMTR outputs fill characters to maintain continuous transmission until another data character is provided. Whenever a fill character is transmitted the data not available (DNA) flag
is raised to notify the program of fill character transmission.

In the isochronous mode, the XMTR receives a parallel transmit character from the program, generates parity if programmed, outputs a start bit, serially outputs the character plus
parity, outputs a stop bit, and raises the TX DONE flag to request the next character.
However, in the isochronous mode, if the program fails to provide the next character before
transmission of the current character is complete, the XMTR simply pauses until the next
character is provided. Hence, the DNA flag is never used in the isochronous mode.

The BREAK input inhibits the XMTR output. Whenever the TXCSR BREAK bit is set, the BREAK
input to the XMTR logic asserts and inhibits the XMTR output. This input enables the program to
inhibit the XMTR output, while inputting data directly to the RCVR via the RCVR input select logic
in the internal and external loop maintenance modes.
For an illustration of transmitter timing involved in synchronous and isochronous modes of operation
refer to Figures 4-5 and 4-6. For a more detailed description of the SAT chip refer to Appendix B.

4-13

CLR H ~______________________________________________________________________~_________________________________________________

LD PARCSR (0) H

ISOC H ~~______________________________________________________________________________________________________________________

LD T XCSR HB/LS H

SEND (1) H

BREAK (I)H

LD TXDBUF (O)H

XMTR SERIAL DATA OUT H
TX CLK H

TX DONE H

TX INTEB (l)H

DNAINTEB(I)H

EOC L

~~-------------------------------------------------------------------------------------------------------------

1 . . ______________________--""

DNA H

DTISEL4L

RST DNA L
11-2327

Figure 4-5 Transmitter Synchronous
Timing Diagram
4-15

CLR H

.5l

LD PARCSR (0) H

1SOC H

--1

~f------+'f

lD TXCSRHB/lB H

SEND (i)H

BREAK (I) H

""I
I

LD TXDBUF (0) H

XMTR SERIAL DATA OUT H

TX ClK H

TX DONE H

TX INTEB (I J H

EOC

DTI SEL 4 L

u
11-2328

Figure 4-6

Transmitter Isochronous
Timing Diagram
4-17

4.5.7 Interrupt Contr.ol Logic
The interrupt control logic consists of two DC003 chips and associated driving circuitry. When the
interrupt control logic receives either RXDONE (l) H, TXDONE (l) H , DATA SET CH (I) H or
DNA H with their associated interrupt enable signal, it generates BIRQ L (interrupt request) to the
processor (engineering drawing D6). The processor responds with BIAKI L (interrupt acknowledge in)
which searches the logic for the originator of the interrupt. If the interrupt was not originated at the
DUV11 the signal BIAKO L (interrupt acknowledge out) is passed through with no action taken. If
the DUVII had originated the request EN VEC to BUS H is asserted and depending on the particular
interrupt EN UPPER VEC H may also be asserted. This signal asserted then causes the addressing
logic to load, onto the Q BUS, the contents of the preset vector address rocker switches. The processor
will then perform the preprogrammed subroutine for that interrupt vector address. For a more
detailed description of DC003 refer to Appendix B.
4.5.8 Clear Logic
The clear logic generates clear (CLR) and optional clear (OPT CLR) which initialize all DUVII logic.
As shown at the bottom of engineering drawing D3, the INIT signal or MSTRST asserted will activate
the clear signals. INIT is a function of BINIT which is received by the interface whenever the computer
activates the go function, the processor executes a reset instruction, or the power fail sequence occurs.
The clear logic outputs are asserted as long as the BIN IT signal remains low. MSTRST is program
controlled and is generated by setting bit 08 of the TXCSR. When bit 08 of the TXCSR is set and LD
TXCSR HB goes low, a 3 f.,LS one-shot asserts MSTRST and the clear signals remain active for the
duration of the one-shot.
The OPT CLR output resets RXCSR bits I, 2, and 3 and thereby clears the control lines to the modem.
By not selecting SWI option switch, OPT CLR is disabled allowing the DUV11 to be cleared without
having to repeat the handshaking sequence. BRPL Y is also inhibited as long as CLR is asserted.

4.5.9 Clock Control Logic
The clock control logic decodes the maintenance mode select bits and assigns the transmitter and
receiver clocks. There are three possible clock sources, the modem, the programmable SS CLK (single
step clock) and the system test clock. (engineering drawing D5.) If the normal operating mode is
decoded, the modem clocks are selected. MSOO (0) H is asserted enabling the modem clock inputs
(TRS CLK and REC CLK). If the internal loop or external loop maintenance mode is decoded, the SS
CLK is selected. This program controlled clock can be operated very slowly to facilitate troubleshooting. In the internal loop mode, MSOO (1) H is asserted enabling the SS C LK (1) H. I n the external
loop mode, MSOI (1) Hand MSOO (0) H are asserted enabling SS CLK (0) H, TRS CLK and REC
CLK. SS CLK (0) H drives CLK EXT, which is routed to the modem test connector, looped back and
applied to the TRS CLK and REC CLK inputs (Figure 4-7). If the system test mode is decoded, the
system test clock is selected. This output provides an asynchronous clocking source for the system test
mode. MSOI (1) Hand MSOO (0) H are asserted enabling the internal system test clock to drive the
transmitter and receiver. In this mode, the modem clock inputs (TRS CLK and REC CLK) are inhibited. When the DUVII is transmitting in the half duplex mode, REC CLK is inhibited. HALF DUP
(0) L and SEND (0) L go high in this condition, inhibiting REC CLK from reaching the receiver.
4.5.10 + 12 to -12 Power Converter
As shown on engineering drawing D6, circuitry is provided to produce -12 V dc for use by the EIA
drivers, the SAT and the SAR chips. A 600 KHz clock is used to switch + 12 V into a capacitor
network to produce approximately -20 V unregulated. This unregulated voltage is then regulated to
-12 V at the output of two twin zener diode networks. The zeners keep the -12 V to within ±5%.
4.5.11 Maintenance Indicators
Indicators in the form of light emitting diodes are provided to display data lines and modem control
states for maintenance purposes. Any of the following lines asserted will cause its respective LED to
illuminate; RING H, CLR TO SEND H, DATA SET RDY H, CARRIER H, SERIAL DATA OUT
H, and SERIAL DATA IN H. These indicators are shown on Figure 1-4 and engineering drawing D6.
4-19

TXCSR

MODEM
TEST
CONNECTOR

RX INP H
RCVR
INPUT
SELECT
lOGIC

E IA SERIAL DATA IN

SERIAL DATA IN

RCVR
lOGIC

RX ClK H

RECClK

CLOCK
CONTROL
lOGIC
TX ClK H

EIA
lEVEL
CONVERTER

EIA

REC elK

ClK EXT

EIA ClK EXT

TRS.ClK

EIA TRS ClK

XMTR
lOGIC
SERIAL DATA OUT H

EIA XMIT DATA

>3
»_J
11- 2316

Figure 4-7

External Loop Maintenance Mode Interconnection Diagram

4-20

CHAPTER 5
PROGRAMMING REQUIREMENTS
AND RECOMMENDATIONS

5.1 INTRODUCTION
To program the DUVII in the most efficient manner, the programmer must fully understand the
control signal and timing requirements for the device. The following paragraphs discuss DUV II operation from a programming point of view and describe recommended programming methods. It is
beyond the scope of this manual to provide detailed programming information. For more detailed
information on programming in general, refer to the Paper- Tape Software Programming Handbook
DEC-II-GGPB-D, and the individual program listings.
5.2

PROGRAMMING THE TRANSMITTER IN THE SYNCHRONOUS MODE

5.2.1 Loading the PAR CSR
Once the transmitter is initialized via the BUS INIT pulse or MSTRST, the PARCSR register must be
programmed (loaded) to select the mode of operation (synchronous in this case), character length, and
parity. At this point the sync register will contain all ones. Before any necessary handshaking is done
with the modem, the program must load the sync register with the desired character. When the sync
register is loaded, the character will be used for both XMTR and RCVR operation.
5.2.2 Handshaking Sequence
Handshaking sequences serve to establish the data communications channel. This is necessary when
the interface is connected to a modem. If the interface is connected to something other than a modem,
e.g., a limited distance adapter, handshaking may not be required; the program simply initiates data
communication by loading a character into the TXDBUF.
If a handshaking sequence is necessary, the program must be written accordingly. The following paragraphs explain a typical handshaking sequence.

The handshaking sequence is initiated when the modem at one data communication station places a
call to a modem at another data communication station. A call may be placed simply by pressing the
modem ring button if only two stations are linked in the communication system or dialing-up station 1
on the modem at station 2, if more than two stations are linked.
Once initiated, the handshaking sequence will be executed as programmed. Figure 5-1 illustrates a
DUVII to modem interface; Figure 5-2 illustrates the h~.ndshaking sequence.

5-1

DATA TERM RDY

REO TO SD

RE;O TO SD

SEC

lSI-II

DUVll
INTERFACE
#1

XMIT

SEC XMIT

RING

ClR TO SD

CARR IER

CARRIER
MODEM
#1

SEC REC

t--

COMMUNICATION
~
FACiliTIES

MODEM
#2

SEC REC

DUVll
INTERFACE
#2

f-- lSI-II

DATA SET RDY

DATA SET RDY
RECEiVE DATA

XM IT DATA

XMIT DATA

RECEIVE DATA

RX ClK

TX ClK

11-5170

Figure 5-1

DUVll to Modem Interface Diagram

RING H

DTR (0)

(OUV11 No.1)

H (DUV11 No.n

CARRIER H (DUVll No.2)

SCH' SYN (I) H (DUVll No,2)

'cARRIER H (DUV11 No, 1)

RTS (0) H (DUV11 No.1)

ClR TO SD H (DUV11 No.1)

SEND (1) ,H (DUVll NO.1)

TX INTEB (1) H (DUVII No.n
11- 5171

Figure 5-2

Handshaking Sequence Timing Diagram

5-2

When modem 2 places a call to modem 1:
1.

Modem 1 asserts ring to DUVII 1.

DUVII 1 asserts DATA TERM RDY (data terminal ready).

Modem 1 sends CARRIER to modem 2.

Modem 2 asserts CARRIER to DUVII 2 and sends CARRIER back to modem 1.

Modem 1 then asserts CARRIER to DUVII 1 and SCH SYNC (search sync) bit is set at
DUVII 2 to enable the RCVR.

D UV 11 1 asserts REQ TO SD (request to send) to modem 1.

Modem 1 asserts CLR TO SD (clear to send) to DUVII 1.

The SEND and TX INTEB (XMTR interrupt enable) bits are set at DUVII 1 to enable the
XMTR.

Note that the modem DATA SET RDY (data set ready) output must be asserted before any data
communication can actually take place. The DATA SET RDY line indicates that the modem is
powered up and conditions are go.
Supervisory data may also be transmitted simultaneously with the normal communication data. The
SEC XMIT (secondary transmit) and SEC REC (secondary receive) lines provide a supervisory data
communication channel.
All data communications can be terminated by simply clearing the data terminal ready bit in the
RXCSR.
5.2.3 Enabling the Transmitter
Once handshaking is complete, the program can assert the SEND bit in the TXCSR. When SEND is
asserted, the XMTR is enabled but will not start transmitting data until the first character is loaded
into the TXDBUF. If SEND is cleared during transmission, the character currently being transmitted
will be completed, the transmit line will go to a mark hold state, the internal XMTR logic will enter the
idle state, and synchronization with the RCVR will be lost. When SEND is cleared, there is no guarantee that the TX DONE bit will be asserted when current character transmission is complete.
5.2.4 Detecting the Last Character of the Message
When it is necessary to know when the entire message has been transmitted, the DUVl1 may be
programmed as follows:
1.

Just prior to loading the last character of the message into the TXDBUF, clear the TX
DONE INTEB bit and set the DNA INTEB bit.

When the last character is loaded into the register, the TX DONE bit will set but will not
cause an interrupt request.

After the last character is transmitted, the transmitter will transmit the sync character and
assert DNA,which causes an interrupt request.

The DNA interrupt is notification to the program that the entire message has been transmitted.
5-3

5.2.5 Transmitting Initial Sync Characters to Establish Synchronization
The transmission of initial sync characters can be accomplished in one of two ways:
1.

The program may arrange its data buffer such that the required number of sync characters
precede any messages. In this case, the sync register mayor may not contain the sync character. If the sync register is not loaded, it will contain all ones subsequent to a BUS INIT or
MSTRST.
Assuming that any necessary handshaking has been completed and that SEND had been
asserted, the program can commence transmission by loading a sync character into the
TXDBUF. When the first data bit is transferred to the communication line, the TX DONE
bit will be asserted. If the TX INTEB bit is set, an interrupt request will be generated and the
program must load another sync character into the TXDBUF.

If the sync character was not initially loaded into the sync register, then synchronization
cannot be guaranteed unless the program response time to the TX DONE bit is less than
(l/baud rate X bits per char) seconds - 1/2 (bit time). This can be verified by the absence of
the DNA bit in the TXCSR.
2.

The program can also enable transmission of initial sync characters from the sync register.
Assuming any necessary handshaking is complete and SEND is asserted, the program loads
the sync register with a sync character, sets the DNA INTEB bit, and clears the TX INTEB
bit. The program then loads a sync character into the TXDBUF and transmission begins.
The TX DONE interrupt is inhibited so the contents of the sync register are transferred to
the XMTR register upon the completion of transmission of the first sync character.

The second sync character is then transmitted and a DNA interrupt is generated notifying the program. The program then allows the transmission of sync characters to continue by simply monitoring
the DNA until the desired number have been transmitted. Note that DNA is reset each time the
program reads the TXCSR and set again when the first bit of the next sync character is placed on the
communication line.
NOTE

It is suggested that a minimum of 5 sync characters
be transmitted. In systems that are prone to error
because of lost synchronization, as many as 12 sync
characters may be desirable.
When the desired number of sync characters have been transmitted, the program sets the TX INTEB
bit, thereby enabling the TX DONE interrupt, and responds to the interrupt by loading a message
character into the TXDBUF.
5.2.6 Transmitting Sync Characters to Maintain Synchronization
After synchronization has been achieved, it can be maintained by the program by inserting sync characters into the message or by ignoring the TX DONE bit, thereby allowing sync characters from the
sync register to be transmitted.

If the latter method is chosen, it can be programmed in one of two ways. The first way would be to set
the DNA INTEB bit and clear the TX INTEB bit. The program would then ignore the TX DONE bit
and the XMTR would transmit a sync character and assert DNA. The program would monitor the
DNA bit and, when the desired number of sync characters are transmitted, set the TX INTEB bit
thereby enabling the TX DONE interrupt. The program would then respond to the TX DONE interrupt by loading a message character into the TXDBUF, thereby terminating the transmission of sync

5-4

characters. The second way would be to clear the TX INTEB and DNA INTEB bits for a given period
of time during message transmission thereby allowing sync characters from the sync register to be
transmitted.
NOTE
The SEND bit in the TXCSR must remain set for
the duration of the message; any on to off transition
will cause the XMTR to enter an idle state after
completion of current character transmission.
5.3 PROGRAMMING THE RCVR IN THE INTERNAL SYNCHRONOUS MODE
Once the program has completed any necessary handshaking (Paragraph 5.2.2), the receiver logic can
be enabled. The program enables the receiver logic by setting the SCH SYNC (search sync) bit in the
RXCSR. Assuming a sync character has been loaded into the sync register (this must be done in the
internal synchronous mode), the receiver begins to compare incoming character bits with the character
held in the sync register.
NOTE
For the receiver to become synchronized with XMTR
either one or two contiguous sync characters must be
received. The number of sync characters required is
SWITCH selectable. The standard configuration
reqoires two sync characters.
Though the DUVll may be switched to synchronize
on two contiguous sync characters, there is a situation which, if it develops, will prevent RCVR, synchronization on only two contiguous sync characters.
If, while the DUVll is searching for synchronization, it recognizes a sync character that is not
followed contiguously by a second sync character,
the RCVR internal logic resets, thereby inhibiting
the R CVR bit detection logic for two bit times.
Should the first bits of a proper sync character
sequence occur during that two bit time period, the
R CVR will fail to achieve synchronization.
When two contiguous sync characters are received, the REC ACT (receiver active) bit is set and any
characters received after that will cause RX DONE interrupt requests, provided the RX INTEB bit is
set and the STRIP SYNC bit is cleared.
NOTE
The SCH SYNC bit must remain set for the duration
of the message. If not, the character being received at
the time of the on to off transition will be lost along
with synchronization.
If the programmer wishes the RCVR to discard all sync characters after synchronization is achieved,
the STRIP SYNC bit in the RXCSR must be set. The STRIP SYNC bit inhibits the RX DONE
interrupt whenever a sync character is received with no errors; however, the sync character is still held
in the RXDBUF until the next character is received.

5-5

If the program fails to read the RXDBUF in response to a RX DONE interrupt, overrun errors wiIl
occur. When the RXDBUF is not serviced in the time required to receive the next character, i.e.,
(I jbaud rate X bits per character) seconds, the character presently being held in the RXD BUF is
overwritten by the next received character and the OVRN ERR (overrun error) bit is set in the
RXCSR.
NOTE
The information in the following paragraph must be
strictly adhered to or R CVR synchronization problems will be encountered.

If the DUVII is configured to achieve synchronization on two contiguous sync characters then
receiver operation may be terminated (after the entire message is received) by simply clearing the SCH
SYNC bit in the RXCSR. However, if only one character is required to achieve synchronization,
receiver termination is a little more complex. If the SCH SYNC bit is cleared while a sync character is
present in the RXDBUF, false synchronization will occur when the receiver is enabled (SCH SYNC
bit set) to receive the next message. The program must ensure that this does not happen by transmitting a pad character, i.e., a non-sync character, immediately after the transmission of the terminating control character.
5.4 PROGRAMMING THE RCVR IN THE EXTERNAL SYNCHRONOUS MODE
The external synchronous mode enables the R CVR logic to set to the synchronize state immediately
upon the assertion of the SCH SYNC (1) H input. This mode is designed for use with comm unication
equipment capable of accomplishing synchronization external to the DUVII. When the program sets
the SCH SYNC bit, the REC ACT bit sets and the RCVR starts framing characters on the very next
bit received. When the selected number of bits are received, the received character is transferred into
the RXDBUF and the RX DONE bit is set causing an interrupt request. All other features and
parameters of the internal synchronous mode apply to this mode also.
5.5

PROGRAMMING THE XMTR IN THE ISOCHRONOUS MODE

5.5.1 Loading the PAR CSR
Once the XMTR is initialized via BUS INIT or MSTRST, the PARCSR must be programmed to
select the mode of operation (isochronous in this case), character length, and parity. It is not necessary
to load the sync register in this mode as sync characters are not required to achieve synchronization
and the transmitter is not required to transmit continuously.
5.5.2 Enabling the XMTR
When the required handshaking is complete, the program sets the SEND and TX INTEB bits and
loads a character into the TXDBUF. The XMTR adds the START and STOP bits and transmits the
character to the modem. As soon as the first character bit is placed on the communication line by the
XMTR, the TX DONE bit is asserted and remains asserted until the XMTR services the TXDBUF or
clears the SEND bit.
5.6 PROGRAMMING THE RCVR IN THE ISOCHRONOUS MODE
RCVR operation is initiated by the assertion of SCH SYNC. When the program sets the SCH SYNC
bit, the REC ACT bit sets and the RCVR starts framing characters upon receipt of the START bit
from the XMTR. When the selected number of character bits are received, the RCVR tests the line for
a valid STOP bit, transfers the received character into the RXDBUF (minus the start and stop bits),
and sets the RX DONE bit. If the STOP bit is not detected, the FRM ERR (framing error) bit is also
set. If the program fails to service the RXDBUF before the next character is framed, the OVRN ERR
bit is set.

5-6

CHAPTER 6
MAINTENAN CE

6.1 SCOPE
This chapter lists required test equipment and provides a complete description of DUVII preventive
and corrective maintenance procedures.
6.2 MAINTENANCE PHILOSOPHY
Basically, DUVII maintenance consists of preventive and corrective maintenance procedures, diagnostic programs, and a maintenance log. The preventive maintenance procedures are performed regularly in an attempt to detect any deterioration due to aging and any damage caused by improper
handling of the module. The corrective maintenance procedures are performed to isolate and repair
faults in module circuitry only after it has been determined that the module is faulty. The maintenance
log is used to record all maintenance activities for future reference and analysis; hopefully, the log will
facilitate future maintenance action and aid in detecting any component failure pattern that may
develop.
6.3 PREVENTIVE MAINTENANCE
Preventive maintenance consists of tasks performed at periodic intervals to ensure proper equipment
operation and minimum unscheduled downtime. These tasks consist of running diagnostics, visual
inspection, operational checks, and replacement of marginal components.
NOTE
There will be no scheduled PM specifically for the
DUVI1-DA. Preventive maintenance should be done
in conjunction with scheduled system PMs.
The preventive maintenance schedule depends on the environmental and operating conditions that
exist at the installation site. Under normal conditions, recommended preventive maintenance consists
of inspection and cleaning every 600 hours of operation or every 4 months, whichever occurs first.
However, relatively extreme conditions of temperature, humidity, dust, and/or abnormally heavy
work loads demand more frequent maintenance. In any case, the diagnostic programs should be run
once per week as part of the normal preventive maintenance schedule.
6.4 TEST EQUIPMENT REQUIRED
Maintenance procedures for the DUVII require the standard test equipment and diagnostic programs
listed in Table 6-1, in addition to standard hand tools, cleaners, test cables, and probes.
6.5 CORRECTIVE MAINTENANCE
The corrective maintenance procedures are designed to aid the maintenance technician in isolating and
repairing faults within the DUVl1 module. Hence, the technician must be otherwise equipped to
determine that the D UV 11 is, in fact, at fault.

6-1

Table 6 ... 1 Test Equipment Required
Equipment

Designation

Manufacturer

Triplett or Simpson
M ultimeter
Oscilloscope
Tektronix
X 10 Probes (2)
Tektronix
Module Extender
DIGITAL
Modem Test Connector DIGITAL
Diagnostic (Maindecs) DIGITAL

Model 630-NA or 260
Type 453
P6008
W984 (Quad Height)
H315A
MAINDEC-II-DZDUQ through
MAINDEC-II-DZDUV

The diagnostic programs comprise the basic tool used by the technician to isolate faults. The diagnostics exercise the DUVII in three distinct maintenance modes and provide printouts indicating the
results. The printouts point the technician to a p'l-rticular logic area such as the XMTR or RCVR logic.
The technician uses standard test equipment (scope and probe) to further isolate the fault to a specific
circuit component.
6.5.1 Maintenance Modes
The three maintenance modes are:
I.
2.
3.

System Test
Internal Loop
External Loop.

6.5.1.1 System Test Mode - This mode is selected by the system test diagnostic program. The system
test diagnostic exercises all devices and interfaces connected to the Q BUS and is run with the DUVII
connected to the modem. The following operations are performed to ex~rcise the DUVII (Figure 6-1):
1.

The system test clock located within the DUVII is enabled [MSOI (1) Hand MSOO (I) H
asserted] and provides clock pulses to the RCVR and XMTR.

The XMTR and RCVR are enabled [SEND (1) Hand SCH SYNC (l) H asserted].

A character is loaded into the TXDBUF.

The XMTR output (SERIAL DATA OUT H) is routed to the RCVR via the RCVR input
select logic.
.

The program monitors the RX DONE and the RXDBUF for errors.

6.5.1.2 Internal Loop Mode - This mode is designed to isolate the faults within the DUVII to one of
the following logic areas:

1.
2.
3.
4.
5.
6.

XMTR
RCVR
DNA
TX DONE
RX DONE
Synchronization.

6-2

DUV11

MODULE

[CLOCK CON TRoLL"OG'iC (D5i - - - - - - - - - - - - - - - - - - - ,
55

CLK (0) H

CLK

EXT

I
I
TXCSR

DATA
TXCSR

M50f

(1)

MSOO

(1) H

MSOO

(0) H

CLK (1) H

I
I

HALF DU P (1) H

RX INP H
MAINT DATA (1) H
BREAK (1) H

XMTR LOGIC
TXDBUF DATA

(f)

:::>

I
J

iVRINP~DTLOffiC

I
I
I

RXCSR

DATA

I
I
I
I
I

ClK

RX CLK H

- - - - - - - - - --------- - -

LSI-II
COMPUTER

---1\.

r-----L-

-0

I
TX ClK

":l
;::J

REC

(D5 )

BUS
TRANSCEIVERS

D I
I

- -

TRS CLK

- ___ J

RX INP H

TRO~
-

PARCSR DATA

I
I

TX CLK H

SEND(1)H

.
L

SEND (1) H

----

5KC

SEND (f) H

(D5)

I
I

I SERIAL DATA OUT H

<o.:=- - - - --l

-R-)

I~
-~
~

RX CLK H

RcvR LOGIC

RXDBUF DATA

' - - - - - - 1 - ~------- ..J

TXCSR DATA

-,.

PARCSR DATA

RX DONE (f) H

( D4)

TX DONE H

e
DNA H

(01)

RXCSR

DATA

STRIP

SCH

SYNC (1) H

SYNC (f) H

SEC TX (0) H

DATA
MULTIPLEXER

RTS

(0) H

DTR (0)

(04)
RX DONE (f) H
RXDBUF DATA
(D2)
RING

CLR TO SD
DATA SET
CHANGE
DETECTOR

CARRIER
SEC

REC

DATA SET

m
RDY

'---

(D3)

1 I -5 035

Figure 6-1

Maintenance Diagram
(Sheet 1 of 2)
6-3

I
I

a }--------,

b )-------,

c t----.

MODEM TEST CONNECTOR
(WIRING SHOWN) (SEE NOTE 1)
24' EIA ClK EXT

,~ EIA TRS ClK _ _ _-.
CINCH

17' EIA REC ClK
~EIA

CONNECTOR

r -,- I
,.---t,
----1

XMIT DATA

23 EIA SERIAL DATA IN

---~

6,EIA DATA SET R.;,:D:.,:.Y_ _-.
1 ;( EIA SEC XMIT

I (I'
I

EIA SEC REC

I I '- --..__ 20,EIA DATA TERM-cRc:..:D:...;Y_-.
II II
I I

ClK EXT

EIA ClK EXT

I I

25,NOT USED

EIA TRS ClK

I I

22' EIA RING

REC ClK

EIA

I I

~------------------

EIA

REC

I I

ClK

XMIT DATA

MSOO (0) H

SERIAL DATA IN

g
i

SEC TX (0) H
RTS (0) H

EIA lEVEL
CONVERTER

DTR (0) H

EIA

SERIAL DATA IN

EIA

SEC XMIT

EIA

REQ TO SO

EIA

BERG

DATA TERM ROY

CONNECTOR:

1'\

m
lD3l

EIA

RING 1

EIA

CLR TO SO

EIA

CARRIER

EIA

SEC REC

EIA

DATA SET RDY

DUVll-DA

I I CONFIGURATION
I I
CINCH
I
I

: CO~
I!

--~r;

MODEM
CABLE
I ( / / (BC05C-25)

r---

--=::~)

I ..///,

5' EIA ClR TO SD_ _ _-'

~/ EIA REQ TO 50 _ _ _,

TRS ClK

SERIAL DATA OUT H

a,EIA CARRIER

lv
...

BEll
201
MODEM

~----~

,---.--_

NOTE 1
Modem test connector
must be installed when
test ing in external
loop maintenance mode

L
I

11-5035

Figure 6-1

Maintenance Diagram
(Sheet 2 of 2)

The internal loop maintenance mode enables the program to exercise the interface logic without physically disconnecting the interface from the modem. This is made possible by maintenance mode logic
that electrically inhibits the clock and data channels [MSOO (0) H cleared] between the interface and
the modem. Note, however, that the modem control lines are not inhibited; therefore, care must be
taken when this mode is programmed not to activate any of the modem control lines.
When the internal loop maintenance mode is programmed, the maintenance mode select bits (MSOl,
MSOO) establish the required operating conditions as follows (Figure 6-1 and engineering drawings D4
and D5):
1.

MSOO (0) H is cleared thus inhibiting the modem clock inputs (TRS CLK and REC CLK),
the modem input to the RCVR input select logic (SERIAL DATA IN), and the XMTR
output to the modem (SERIAL DATA OUT H).

2.·

MSOI (1) Hand MSOO (0) H are cleared thus enabling the program input to the RCVR via
the RCVR input select logic [MAINT DATA (1) H] and the RX INP H input to the
TXCSR.
NOTE
When programming the internal loop maintenance
mode, ensure that SERIAL DATA OUT H is disabled (BREAK bit set) whenever the MAINT DATA
(1) H input to the R CVR input select logic is active.

MSOO (1) H is asserted thus enabling the programmable single step clock input [SS CLK (1)
H] to drive the RCVR and XMTR and the XMTR output to the RCVR via the RCVR
input select logic (SERIAL DATA OUT H).

Once the operating conditions are established, the program performs the following operations:
I.

The single step clock is programmed (by alternately setting and clearing the SS CLK bit) to
provide clock pulses to the RCVR and XMTR.

The RCVR and XMTR are enabled.

A character is loaded into the TXDBUF.

The XMTR then serially outputs the character to the RCVR via the SERIAL DATA OUT
H line.

6.5.1.3 External Loop Mode - This mode is designed to isolate faults occurring in the cabling connecting the DUVII to the modem, as well as faults within the DUVII level converters and data set
change detector logic. Before this mode can be executed the interface must be physically disconnected
from the modem and the modem test connector (H315A) installed at the modem end of the BC05C
modem cable. Figure 6-1 illustrates the proper installation of the modem test connector.

6-7

When the external loop maintenance mode is programmed, the maintenance mode select bits establish
the required operating conditions as follows (Figure 6-1 and engineering drawings D4 and D5):
I.

MSOO (0) H is asserted thus enabling the TRS eLK and REC CLK inputs to the clock
control logic, the SERIAL DATA IN input to the RCVR input select logic and the XMTR
output to the modem test connector (SERIAL DATA OUT H).

MSOI (1) Hand MSOO (0) H are asserted thus enabling the program input to the RCVR via
the RCVR input select logic [MAINT DATA (1) H] and the RX INP H input to the
TXCSR.
NOTE
When programming the external loop maintenance
mode, care must be taken to ensure that SERIAL
DA T A OUT H is disabled (break bit set) whenever
the MAINT D A T A (1) H input to the R CVR input
select logic is active.

MSOI (1) H is asserted thus enabling the programmable single step clock input [SS CLK (0)
H] to drive the RCVR and XMTR via CLK EXT output to the modem test connector.

Once the operating conditions are established, the program performs the following operations to check
out the modem cabling.
I.

The single step clock is programmed to activate the EIA CLK EXT output which is looped
back by the modem test connector and applied to the TRS CLK and REC CLK input lines.

The RCVR and XMTR are enabled.

A character is loaded into the TXDBUF.

The XMTR then serially outputs the character to the modem test connector, which loops it
back to the interface where it is applied to the RCVR via the SERIAL DATA IN line.

The program then monitors the RX INP bit, the RX DONE bit, and the RXDBUF for errors. To
further isolate any errors that may be detected, the program sets the BREAK bit and inputs data
directly to the RCVR via the MAINT DATA (1) H line.
To check out the modem control lines, the program individually sets and clears the modem control bits
(bits 01, 02, and 03 in the RXCSR) and monitors the modem control lines and the DATA SET CH bit
for errors.

6-8

2.1.6 Option Switches
The DUVII contains a set of switches which control additional system functions and optional features. Table 2-4 lists these switches (all contained in switch bank E55), and explains their use.
Table 2-4

Switch Assignments

Switch Number*

Function

SWI

Optional Clear - Switch ON enables CLR OPT, which is used to clear
RXCSR bits 03, 02, and 0 I.

SW2

Secondary Transmit - Switch ON enables secondary data channel between
the modem and DUVll.

S\V3

Secondary Receive - Switch ON enables secondary data channel between the
modem and DUVII.

SW4

Sync Characters - Switch ON enables the receiver to synchronize internally
upon receiving one sync character. The normal condition of receiving two
sync characters exists when SW 4 is off.

SW5

Special Feature - Switch ON allows external clock to be internally generated,
used when a modem is not being utilized.

SW6

Special Feature - Optional feature is switched ON for program control of
data rate selection.

SW7

Maintenance Clock - Switch ON enables the clock that is used for maintenance purposes only.

SW8

Not Used.

*All switches are located on component reference designation E55.
2.2 INITIAL TESTIN G
The DUVII-DA must be tested prior to placing the unit into operation. For initial test procedures,
refer to the engineering specification, A-SP-DUVII-0-2, provided with each DUVII delivered.
NOTE
Before running diagnostics on interface, disconnect
the modem cable (BC05C-25) from the rear of the
modem and install the modem test connector H315A
as shown in Figure 2-7.
Testing may be performed without removing the
BC05C-25 cable from the modem. However, in this
mode the EIA line receivers and drivers cannot be
tested.

2-8

APPENDIX A
REPRESENTATIVE MODEM
FACILITIES AVAILABLE

Type of Line Comments

Manufacturer

Model

Speed
(Maximum)

Sync or
Half or
Full Duplex .Async

Bell System
Bell System
Bell System
Bell System
Bell System
Bell System

103A
103E
103F
113A
113B
201A

300 baud
300 baud
300 baud
300 baud
300 baud
2000 baud

Full Duplex
Full Duplex
Full Duplex
Full Duplex
Full Duplex
Either

Async
Async
Async
Async
Async
Sync

DDD
DDD
Private
DDD
DDD
DDD

Bell System
Bell System
Bell System

201B
202B
202C

2400 baud
1800 baud
1200 baud

Either
Either
Either

Sync
Async
Async

Private
DDD
DDD

Bell System
Bell System

202D
205B

Async
Either
Full Duplex Sync

Private
Private

Bell System

202E
Series
301B

1800 baud
600 baud
1200 baud
2400 baud
1200 baud

Bell System

Trans Only

Async

Either

Sync

Either

Sync

Either

Async

Bell System

303B,
C,D,E

Bell System

811B

40,800
baud
19,000 to
230,400
baud
110 baud

Western Union
Western Union
Western Union

118-1A
1601-A
2121-A

180
600
1200

Western Union
Western Union
Western Union
Western Union

2241-A
100
100
300

Either
Either
Either
Either

Either
Async
Async
Sync

Rixon

FM-12

2400
200
2400
18,000
40,000
1200

Either

Rixon

Sebit 48

4800

Either

Sync

General
Electric

TDM
220

2400

Either

A-I

DDD
Private
Private
Wire Band
Private
Wide Band
TWX
Network
Telegraph
Voice
Voice
Broad Band
Broad Band
Voice
Voice
Broad Band
Voice
Be1l4A
Voice
Be1l4C
Private
Be1l4B

Similar to 103A
Originate Only
Answer Only
Full Duplex on
2 calls
Full Duplex on
2 calls

APPENDIX B
LSI INTEGRATED CIRCUIT DESCRIPTIONS

B.I INTRODUCTION
LSI integrated circuits (lCs) shown in the engineering drawings for the DUVll are covered in this
appendix. These descriptions are intended as maintenance aids for troubleshooting to the IC level.
B.2 PRI472B SYNCHRONOUS RECEIVER (P/SAR)
The P /SAR is a programmable receiver that interfaces variable length, serial-to-parallel data channel.
The receiver converts a serial data stream into parallel characters with a format compatible with all
standard synchronous, asynchronous, or isochronous data communications media.
Figure B-1 is a block diagram of the P /SAR. The P /SAR internal control memory, programmable
from the device terminals, consists of a control register and a match-character holding register. Contiguous synchronous serial characters are compared in a programmable match-character holding register, character synchronized and assembled.
RRC

CRL

DRR

SFR

FE/SS

- - - INPUT FOR
SYNCHRONOUS

~VSS

MODE ONLY
--G]VGG
EPE

-----B
TIMING

V DD

~CD*

a CONTROL

~MR

COMPARATOR

RECEIVER REGISTER

CJ
RECEIVER

HOLDING REGISTER

DENOTES SIGNAL PIN
UNDER CONTROL BY CHIP
DISABLE (CD PIN 6)*

MATCH CHARACTER HOLDING REGISTER

MHR

11- 2938

Figure B-1

PR1472B Programmable Synchronous Receiver (P/SAR)
B-1

The receiver holding register, a buffer storage register with an associated data received flag, provides.
an entire serial character time for servicing (unloading) the receiver. The match-char.acter holding
register, in conjunction with the comparator, compares the serial data stream, provides an output
when the input bit pattern matches the contents of the match-character holdjn~ register and causes
character synchronization. A master reset is provided.
P /SAR signal mnemonics are listed in Table B-1 and described in detail in Table B-2. Pit; conn~ctions
are shown in Figure B-2.

•

MHRe

RMS 7

MHR 5

MHR6

MHR 7

RMS 1

WLS

MHR4

RR 9

MHR

RR 8

CRL

RR 7

RR6

RRC

RR 5

MDET

FE/SS

VSS

RMS 3

RR 3

ORR

SFR

MHR 1

WLS 2

MHR 2

Voo

e: PE

2
1

VGG
MHR

11-2933

Figure B-2

P /SAR Pin Connections

B-2

Table B-1

P /SAR Signal Mnemonics

Input/Output Name

Input/Output Symbol

Power Supply

VSS, VDD, VGG

Receiver Mode Select

RMS 1, RMS 2 , RMS 3

Match-Character
Holding Register

MHRI-MHRg

Word Length Select

WLS 1-WLS 2

Chip Disable

Receiver Holding
Register Data

RRI-RR9

Parity Inhibit

Even Parity Enable

EPE

Status Flag Reset

SFR

Data Received Reset

DRR

Data Received

Overrun Error

Framing Error

Sync Search

Parity Error

Match Detect

MDET

Receiver Register Clock

RRC

Master Reset

Control Register Load

CRL

Match-Character
Holding Register

MHRL

Load Receiver Input

B-3

-Table B-2

P /SAR Signals

Symbol

Function

Vss POWER SUPPLY

Vss

+5 V Supply

37, 39, 2

RECEIVER MODE
SELECT

RMS[,RMS 2,
RMS 3

A low-level input. voltage, VIL, applied to CD (pin 6) enables RMS"
RMS 2, and RMS 3 inputs. The Receiver Mode Select Inputs, in conjunction with the Control Register
Load Strobe selects the Receiver operating mode. RMS" RMS 2, and RMS 3
are left high (connected internally to
VIH via a pull-up resistor) to select the
sync-internal operating mode.

18,22
17,36,3
38,4,40

MA TCH-CHARACTER
HOLDING REGISTER
DATA

MHR"MHR2,
MHR 3,MHR 4 ,
MHRs,MHR6,
MHR7,MHRg

A low-level input voltage, VIL, applied to CD (pin 6) enables the inputs
to the match-character holding register and load strobe, MHRL. Parallel
8-bit characters are input into the
match-character holding register with
the MHRL strobe (pin 34). If a character of less than 8 bits has been selected (by WLS, and WLS 2), only the
least significant bits are accepted.
These inputs are switch selectable to
the appropriate input voltage.

5,23

WORD LENGTH
SELECT

Pin Number I/O Name

A low-level input voltage, VIL, applied to CD (pin 6) enables the inputs
of the control register and load strobe,
CRL. Parallel 8-bi't characters are input into the control register with the
CRL strobe (pin 33), WLS, and WLS 2
select the transmitted character length
from five to eight bits defined by the
following truth table.
WLS,

WLS 2

Selected Word
Length

VIL
VIL
VIH
VIH

VIL
VIH
VIL
VIH

5 bits
6 bits
7 bits
8 bits

WLS 1 and WLS 2 are switch selectable
to the appropriate input voltage.

B-4

Table B-2
Pin Number I/O Name
6

CHIP DISABLE

P /SAR Signals (Cont)
Symbol

Function

This line controls the disable associated with busable inputs and tristate
outputs. A high-level input voltage,
VIH, applied to this line disables inputs and removes drive from pushpull output buffers causing them to
float. Drivers of disables outputs are
not required to sink or source current.
The I/O lines controlled by chip disable are defined below.
Input Lines
CRL
EPE
PI
WLS\-WLS 2
RMS\-RMS 3
DRR
SFR
MHRL
MHR\-MHRs

Tristate
Output Lines
PE
FE
OE
RR\-RRs

7-15

RECEIVER HOLDING
REGISTER DATA
OUTPUT

RR9-RR\

A low-level input voltage, VIL, applied to CD (pin 6) enables the receiver holding register outputs,
RR\-RR 9. The parallel data character, including parity (RR 9), appears
on these lines. Program control selection of a word length less than eight
bits will cause the most significant bits
of the character to be forced to a lowlevel output voltage, VOL. The character will be right justified RR\ (pin 15)
is the least significant bit of the character.

VGG POWER SUPPLY

VGG

-12 V Supply.

PARITY INHIBIT

A low-level input voltage, VIL, applied to CD (pin 6) enables the EPE
and PI inputs.

B-5

Table B-2
Pin Number I/O Name

P /SAR Signals (Cont)
Symbol

Function

---------+----------------------~~-----------+-------------------------------------

EVEN PARITY
ENABLE

EPE

The even parity enable input and parity inhibit input to the control register,
in conjunction with the control register load strobe, select even, odd or no
parity to be verified by the receiver. A
high-level input voltage, VIH, applied
to EPE selects even parity if a lowlevel input voltage, VIL, selects odd
parity if a low-level input voltage is
applied to parity inhibit. PI and EPE
are switch selectable to the appropriate input voltage.
PI

EPE

Selected Parity
ODD
EVEN
NONE

x - either VIL or VIH. When programmed, the appropriate parity is
verified following the last data bit of a
character.
24

STATUS FLAG RESET

SFR

A low-level input voltage, VIL, applied to CD (pin 6) enables the SFR
input. A low-level input voltage, VIL,
applied to this line resets the PE and
OE status flags.

DATA RECEIVED
RESET

DRR

A low-level input voltage, VIL, applied to CD (pin 6) enables the SFR
input. A low-level input voltage, VIL,
applied to this line resets the DR flag.

DATA RECEIVED
FLAG

A high-level output voltage, VOH, indicates that an entire character has
been received and transferred to the
receiver holding register. When operating in the synchronous mode, the
first SYN character, when located and
transferred to the receiver holding register, will not cause DR to go to a
high-level output voltage, VOH, but
will cause MDET to go to a high-level
output voltage. Character transfer to
the receiver holding register occurs in
the center of the last bit of a synchronous character, at which time this flag
is updated.

B-6

Table B-2

P /SAR Signals (Cont)

Pin Number I/O Name

Symbol

Function

OVERRUN ERROR
FLAG

A low-level input voltage. VIL, applied to CD (pin 6) enables the OE
output. A high-level output voltage,
VOH, indicates that the previously received character was not read (DR
line not reset) and was, therefore, lost
before the present character was
transferred to the receiver holding register. This transfer occurs in the center
of the last bit of a received synchronous character, at which time this flag
is updated.

FRAMING ERROR/
SYN SEARCH

FE/SS

FE/SS is a two-way (I/O) bus. When
programmed for the SYNCHRONOUS MODE, this line is an input
and is not under control of CD. This
line should be driven by a tristate or
an open collector device.
If programmed for INTERNAL
CHARACTER SYNCHRONIZA TION, a transition from a lowlevel input voltage, VIL, to a high-level
input voltage, VIH, initiates the automatic internal SYN character search
operation.
Prior to initiation of this operation,
the receiver holding register is transparent so that its contents are identical to that of the RECEIVER
REGISTER. Upon receipt of a SYN
character, (previously loaded into the
match-character holding register during initialization), the receiver holding
register becomes non-transparent, the
MATCH DETECT output (MDET)
goes to a high-level output voltage,
VOH, but, the data received (DR) flag
does not assume a high-level output
voltage, VOH. The P/SAR is now in
character synchronization. Subsequent SYN or data character will be
transferred to the RECEIVER
HOLDING REGISTER as they are
assembled (at the center of the last bit)
and the DR FLAG will be raised. A
transition from a high-level input voltage, VIH, to a low-level input voltage,
VIL, causes the P /SAR to lose character synchronization and forces the receiver holding register to become
transparen t.

B-7

Table B-2

P /SAR Signals (Cont)

Pin Number I/O Name

Symbol

Function

PARITY ERROR
FLAG

A low-level input voltage, VIL, applied to CD (pin 6) enables the PE
output. Parity, if programmed, is verified upon receipt of the center of the
parity bit which is the last bit of a synchronous character. If a parity error
exists, the associated PE register is set
to a high-level output voltage, VOH.

MATCH DETECT
FLAG

MDET

A high-level output voltage, VOH, indicates that the contents of the receiver register are identical to the
contents of the match-character holding register. This flag is set to a highlevel output voltage, VOH, at the center of the last bit of a synchronous
character.

RECEIVER REGISTER
CLOCK

RRC

This fifty percent duty cycle clock provides the basic receiver timing. The
negative transition from a high-level
input voltage, VIH, to a low-level input voltage, VIL, shifts data into the
RECEIVER REGISTER at a bit rate
determined by RMS 1, RMS 2, and
RMS 3 • Synchronous operation requires that this negative transition occur at the center of each data bit.

MASTER RESET

A high-level input voltage, VIH, applied to this line resets timing and control logic to an idle state, sets the
contents of the receiver holding register to a high-level output voltage,
VOH, resets the contents of the matchcharacter holding register, the
MDET, DR, PE, FE, and OE outputs
to a low-level output voltage, VOL,
but does not effect the contents of the
control register.

CONTROL REGISTER
LOAD STROBE

CRL

A low-level input voltage, VIL, applied to CD (pin 6) enables the CRL
input. A low-level input voltage, VIL
applied to this line enables inputs to
dc D type Latches of the control register and loads it with control bits (EPE,
PI, RMS 1, RMS 2, RMS 3 , WLS 1,
WLS 2). This line is hard-wired to a
low-level input voltage, VIL.

B-8

Table B-2

P /SAR Signals (Cont)

Pin Number I/O Name

Symbol

Function

MATCH CHARACTER
HOLDING REGISTER
LOAD STROBE

MHRL

A low-level input voltage, VIL, ap-

RECEIVER INPUT

plied to CD (pin 6) enables the
MHRL input. A low-level input voltage, VIL, applied to this line enables
input to dc D Type latches of the
match-character holding register and
loads it with the match-character register data, MHR\-MHR g• A highlevel voltage; VIH, applies to this line
disables the match-character holding
register. This line may be strobed or
hard-wired to a low-level input voltage, VIL.
The serial input data stream received
on this line enters the receiver register
determined by the character length
and parity programmed.

B.2.1 Synchronous Mode Operation
Synchronous data appears as a continuous bit stream of contiguous characters at the input to the
receiver with no start or stop bits. Character synchronization (the framing of this continuous bit
stream into characters of a predetermined fixed length), must be accomplished by a comparison of this
hit stream and a synchronization sequence. The P jSAR is designed to accommodate internal or external character synchronization by program control. Internal character synchronization is used by the
DUVII.

An example of synchronous timing is shown in Figure B-3. Device operation is programmed subsequent to being forced into its idle state. The P jSAR will enter a defined idle state when the master
reset (MR) line is strobed to a high-level input voltage. In this state, all timing and control logic are
reset, the contents of the receiver holding register is set to a high-level output voltage and all output
flags are reset to a low-level output voltage. The MR also causes the contents of the match-character
holding register to be reset to a low-level voltage.
The control register is loaded by hard-wiring CRL to a low-level input voltage, which defines the
internal synchronous mode of operation and times one clock rate selection, character length and
selected parity if required. Table B-3 illustrates all programmable synchronous formats.
Character synchronization from the data stream requires receiver recognition of specific bit pattern(s)
which define the relative position of synchronous characters in the data stream and subsequent character assembly.

B-9

TCO
MRJl____________- - - - - - - - - - - - - -_______________________________

TR I TR

THRL

CTS

THRE

==><________- ____----'X'---_--_,.......,X'-_ _ _ _ _ _---.___

--w

-.....---'

L--.-J

DD/EOC _ _----'

NOTE: PI =V IL

CLOCK SHOWN IS BIT RATE CLOCK (1Xl.

MS=VIL
MS=VIH
WLS=VIH
WLS=V IH
11-2901

Figure B~3

Synchronous Timing Example (P /SAR)

Table B-3

Sync l\tlode Control Definition
Character Format

Control
R
M
S

W
L
S

W
S

I
I
I
I
I

0
0
0
1
1

I
I

0
0
1
0
0
1
0
0
1
0
0

0
1

1
1

0
0
0
0
0
0
1

1
I
1

I
I
I
I

0
0
0
I

1
1

E
P
E

0
1
X

0
I
X

0
1

Data
Bits

Parity Bit
Checked

5
5
5
6
6
6
7
7
7
8
8
8

Odd
Even
None
Odd
Even
None
Odd
Even
None
Odd
Even
None

Sets to SYNC Mode
(When RMS 1 = 1, the receiver operates in the internal character SYNC mode.)

B-I0

Programmed for internal character synchronization, with a high-level input voltage on the sync search
line, the receiver holding register is transparent and its contents are identical to the receiver register.
The data stream, gated into the receiver input (RI) by the negative transition of the receiver register
clock (RRC), shifts through the receiver register and is compared with the preprogrammed character
in the match-character holding register.
A match, indicated by a high-level output voltage on match detect (MDET), returns the receiver
holding register to its non-transparent state and initializes timing and control logic, but does not set
the data received flag to a high-level output voltage. The character following the match will be transferred to the receiver holding register at the receipt of the center of its last bit and the data received flag
is set to a high-level output voltage. Depending on line discipline, this last character may also be a
synchronizing character, in which case, MDET will continue to be a high-level output voltage when
the data received flag is set. Therefore, sequence verification can be performed by the system. Selection
of a word length of less than eight bits causes the most significant bits of the character to be forced to a
low level output voltage.
I f programmed, parity is verified upon receipt of the center of the parity bit which is the last bit of
synchronous character. For word lengths less than eight bits, the parity bit appears immediately to the
left of the last bit in the character. If a parity error exists, the associated PE register is set to a high-level
output voltage.
Transfer of a character to the receiver holding register sets the associated data received register flag
(DR) to a high-level output voltage. If the data received register flag has already been set to a highlevel output voltage and has not been cleared by external logic, the transfer of a character to the
receiver holding register causes the previous character to be lost (written over) and is alerted by overrun error flag, which is a high-level output voltage. In normal operation, the data received flag is reset
by DRR when the receiver holding register is serviced (unloaded). The status flags, PE and OE, are
also provided with an external reset SFR. A low-level input voltage on sync search during the negative
transition of the RRC causes character synchronization to be lost and initiates transparency of the
receiver holding register.
B.3 PTI482B SYNCHRONOUS TRANSMITTER (P/SAT)
The P /SA T is a programmable transmitter that interfaces variable-length, parallel-input data to a
serial channel. The transmitter converts parallel characters into a serial data stream with a format
compatible with all standard synchronous, asynchronous or isochronous data communications media.
Figure B-4 is a block diagram of the P /SAT. The P /SAT internal control memory, programmable
from the device terminals, consists of a control register and a fill (idle) character holding register.
Contiguous, serial characters are transmitted, in the synchronous mode, with the automatic insertion
of a programmable fill (idle) character during the absence of parallel input data.
The transmitter holding register, a buffer storage register with an associated transmitter holding register empty flag, provides an entire character time for servicing (loading) the transmitter (shift) register.
Under internal logic control, the (P /SA T) multiplexer loads data from the transmitter holding register
or the fill (idle) character holding register into the transmitter register. A master reset is provided.
P /SAT signal mnemonics are listed in Table B-4 and are described in detail in Table B-S. Pin connections are shown in Figure B-S.
B.3.1 Synchronous Mode Operation
Synchronous transmission requires that characters (programmably variable from S to 8 data bits plus
parity) are contiguous with no start or stop bits. Since the requirement that characters are contiguous
does not imply that the system servicing the transmitter always has ample time to load the transmitter
holding register, it is necessary that a character be transmitted when data has not been loaded into the
transmitter holding register. This character is defined as the fill or idle character and a separate register
has been provided to load this character upon initialization. The fill character holding register is
loaded by strobing the fill character holding register load (FHRL) line to a low-level input voltage.
B-ll

THRE

CRL

EPE
MULTIPLEXER

TRANSMITTER REGISTER

~----i 15

TRO

~-D VSS

)-8
MS,

VGG

)~VDD
TIMING 8

MS 2

CONTROL

)-G

WLS,

~--G CD

WLS 2

DENOTES SIGNAL PIN UNDER
CONTROL BY CHIP DISABLE
(CD PI N 22) SEE ELECTRIC AL
CHARACTERISTICS.
11- 2939

Figure B-4

PT 1482B Programmable Synchronous Transmitter (P /SA T)

VSS

WLS 2

EPE

WLS 1

TRS

CRL

FRS

CLK

TR7

CS,

FR7

CS2

TRS

MS 1

FRS

MS2

TRS

DAR

FRS

TCO

TR4

FR4

TR3

THRE

FR3

TRO

TR2

VGG

FR2

CTS

TR,

FR1

THRL

FHRL

VDO
11-2902

Figure 8-5

P /SA T Pin Connections

B-12

Table B-4P /SAT Signal Mnemonics
Input/Output Name

Input/Output Symbol

Power Supply

Vss, VDD, VGG

Even Parity Enable

EPE

Parity Inhibit

Control Register Load

CRL

Clock

CLK

Clock Rate Select
Mode Select

MS18-MS 2

Data Not Available Reset

DAR

Transmitter Clock Out

Teo

Data Not Available

Data Delimit/End of Character

DD/EOC

Transmitter Holding
Register Empty

THRE

Transmitter Register Output

TRO

Clear-To-Send

CTS

M aster Reset

Transmitter Holding
Register Load

THRL

Fill-Character Holding
Register Load

FHRL

Chip Disable

....-

Fill-Character Holding
Register Data
Transmitter Holding
Register Data
Word Length Select

B-13

Table B-5
Pin Number I/O Name

P /SAT Signals

Symbol

Function

Vss POWER SUPPLY

Vss

+5 V Supply

EVEN PARITY ENABLE

EPE

A low-level input voltage, VIL,
applied to CD (pin 22) enables the
EPE and PI inputs.

PARITY INHIBIT

The even parity enable input and the
parity inhibit input to the control register load strobe, select even, odd or
no parity to be generated by the transmitter. A high-level input voltage,
VIH, applied to EPE selects even parity and a low-level input voltage is applied to parity inhibit. PI and EPE are
switch selectable to the appropriate
input voltage.
PI

EPE

Selected Parity
ODD
EVEN
NONE

x - either VIL or VIH. When programmed, the appropriate parity is
generated fo11owing, and is contiguous with, the last data bit of a
character.
4

CONTROL REGISTER
LOAD STROBE

CRL

A low-level input voltage, VIL,
applied to CD (pin 22) enables the
CRL input. A low-level input voltage,
VIL, applied to this line enables dc
latches of the control register and
loads it with control bits (EPE, PI,
CS 1, CS 2, MS 1, MS 2 , WLS 1, WLS 2).
This line is hard-wired to a low-level
input voltage VIL.

TRANSMITTER
REGISTER CLOCK

TRC

This is a 50 percent duty cycle clock.
The positive going edge of this clock
shifts data out of the transmitter register at a times one rate bit as determined by the control bits CS 1 and
CS 2 , and provides the basic time reference for all device functions.

B-14

Table 8-5
Pin Number I/O Name

6-7

P/SAT Signals (Cont)
Symbol

CLOCK RATE SELECT

Function
A low-level input voltage, VIL,
applied to CD enables the CS 1 and
CS 2 inputs. These two lines select the
internal clock rate divider ratio to
produce the transmitter bit rate
defined by the truth table below:
CS 2

CS 1

Selected Clock
Input Rate

VIL
VIL
VIH
VIH

VIL
VIH
VIL
VIH

1 X Bit Rate
16 X Bit Rate
32 X Bit Rate
64 X Bit Rate

These lines are hard-wired to a lowlevel input voltage.

8-9

MODE SELECT

DATA NOT AVAILABLE
RESET

DAR

A low-level input voltage, VIL,
applied to CD (pin 22) enables the
DAR input. A low-level input voltage,
VIL, applied to this line resets the data
not available flag.

TRANSMITTER
CLOCK OUTPUT

TCO

This output is a clock at the transmitted bit rate. The negative going
edge of this clock corresponds to the
center of each transmitted data bit.
The positive going edge corresponds
to the start of each data bit transition.
All waveforms in this specification are
referenced to TCO.

DATA NOT AVAILABLE
FLAG

A low-level input voltage, VIL,
applied to CD (pin 22) enables the DA
input. A high-level output voltage,
VOH, on this line indicates that a fillcharacter has been transmitted, since
a character was not loaded into the
transmitter holding register by the
center of the last bit of a synchronous
character.

A low-level input voltage, VIL,
applied to CD (pin 22) enables the
MS 1 and MS 2 inputs. These lines
select the transmitter operating mode.

B-15

Table 8.;.5

P /SAT Signals (('ont)

Pin Number I/O Name

Symbol

Function

DATA DELIMIT/
END OF CHARACTER

DD/Eoe

A low-level output voltage during synchronous transmission indicates that
the last bit of a character is being
transmitted.

TRANSMITTER
HOLDING REGISTER
EMPTY

THREE

A low-level input voltage applied to
CD (pin 22) enable the THRE input.
A high-level output voltage, VOH, on
this line indicates the transmitter
holding register IS empty and has
transferred its contents to the transmitter register and may be loaded with
a new character. This line goes to a
low-level output voltage, VOL, when
THRE goes to a low-level input voltage, V,L.

TRANSMITTER
REGISTER OUTPUT

TRO

The contents of the transmitter holding register are serially shifted out as
an NRZ waveform on this line provided that a character was loaded into
the transmitter holding register prior
to DA flag (in synchronous mode). If
a character was not loaded prior to a
DA flag, the contents of the fil1-character register are transmitted as the
next character.

VGG POWER SUPPLY

CLEAR-TO-SEND

CTS

The clear-to-send control initiates or
disables transmission as a function of
the state of this line. A high-level input voltage, VIH, initiates serial data
transmission provided a character has
been loaded into the transmitter holding register. A low-level input voltage,
VIL, applied to this line during transmission al10ws completion of that
character only, after which the output
will continue to mark until a highlevel input voltage is applied.

MASTER RESET

The rising edge of a high-level input
voltage, V IH, applied to this line resets
timing and control logic to an idle
state, sets THRE, the contents of the
fill-character holding register. and
TRO to a high-level output voltage.

-]2 V supply

VOH.

8-16

Table 8-5
Pin Number I/O Name

P /SAT Signals (Cont)
Symbol

Function

TRANSMITTER
HOLDING REGISTER
LOAD STROBE

THRL

A low-level input voltage, VIL, applied to CD (pin 22) enables the
THRL input. A low-level input voltage, VIL, applied to this line enables
dc latches of the transmitter holding
register and loads it with the transmitter holding register data and forces
THRE to a low-level output voltage,
VOL. A high-level input voltage, VIH,
applied to this line disables the transmitter holding register.

FILL-CHARACTER
HOLDING REGISTER

FHRL

A low-level input voltage, VIL, applied to CD (pin 22) enables the
FHRL input. A low-level input voltage, VIL, applied to this line enables
dc latches of the fill-character holding
register and loads it with the fill-character register data, FR 1-FR 8 • A highlevel input voltage, VIH, applied to
this line disables the control register.
This line may be strobed or hardwired to a low-level input voltage,
VIL.

VDD PO\VER SUPPLY

Voo

Ground.

CHIP DISABLE

This line controls the disconnect associated with busable inputs and tristate
outputs. A high-level input voltage,
VIH, applied to this line removes drive
from push-pull outputs causing them
to float. Drivers of disabled inputs are
required to sink or source current.
The I/O lines controlled by chip disable are defined below.
Input Lines
CRL
EPE
PI
CS 1-CS 2
MS 1-MS 2
DAR
THRL
FHRL
FRI-FRg
TRI-TR2
WLS 1-WLS 2

B-I7

Tristate
Output Lines
DA
THRE

Table 8-5

P /SAT Signals (Cont)

Pin Number I/O Name

Symbol

Function

23,25
27,29
31, 33
35,37

FRI-FRx

A low-level input voltage, VIl., applied to CD (pin 22) enables the inputs
of the fill-character holding register
and associated load strobe, FHRL.
Parallel 8-bit characters are input into
the fill-character holding register with
the FHRL strobe (pin 20). If a character of less than 8 bits has been selected
(by WLS 1 and WLS 2) only the least
significant bits are accepted. These inputs are switch selectable to the appropriate input voltage.

FILL-CHARACTER
HOLDING REGISTER
DATA INPUTS

During synchronous transmission, the
fill-character is transmitted if a character was not loaded into the transmitter holding register prior to a DA
f1ag~ i.e., the transmitter holding register did not contain a character at the
center of the last bit being transmitted
from the transmitter register. A highlevel input voltage, YIL, will cause a
high-level output voltage, YOH, to be
transmitted, least significant bit (FR I)
to most significant bit (FRn) order.
24, 26
28, 30
32, 34
36,38

TRANSMITTER
HOLDING REGISTER
DATA INPUTS

TRI- TR 8

A low-level input voltage, VIL, applied to CD (pin 22) enables the inputs
to the transmitter holding register and
associated load strobe~ THRL. If a
character of less than 8 bits has been
selected (by WLS 1 and WLS 2), only
the least significant bits are accepted.
A high-level output voltage, VIH, will
cause a high-level output voltage to be
transmitted, least significant bit (TR I)
to most significant bit (TRn) order.

39-40

WORD LENGTH

WLS j -WLS 2

A low-level input voltage, YIL, applied to CD (pin 22) enables the inputs
of the control register and load strobe,
CRL. Parallel 8-bit characters are input into the control register with the
CRL strobe (pin 4), WLS and WLS
select the transmitted character length
from five to eight bits defined by the
following truth table.

8 .. 18

Table 8-5

P/SAT Signals (Cont)
Symbol

Pin Number I/O Name

Function
WLS 2

WLS 1

Selected Word
Length

VIL
VIL
VIH
VIH

VIL
VIH
VIL
VIH

5 bits
6 bits
7 bits
8 bits

WLS I and WLS 2 are switch selectable
to the appropriate input voltage.
The P /SA T will enter a defined idle state when the MR is strobed to a high-level input voltage. In this
state, all timing and control logic are reset, the transmitter register output continues to mark, the
transmitter holding register flag is set to a high-level output voltage, the data delimit/end of character
(DO /EOC) flag is set to a low-level output voltage, and the contents of the fill character holding
register are forced to a high-level voltage.
An example of synchronous timing is shown in Figure B-6. The control register is loaded by hardwiring CRL to a low-level input voltage which defines synchronous mode of operation, character
length. selected parity if required, and the times one clock rate selection. Table B-6 illustrates all the
programmable synchronous character formats.

MR-Il~

MHRL

_____________________________________________________________ _

--U

RRC*

RI
~~~'~--~-::----'

CHARACTER #"1
MDET

CHARACTER#"2

CHARACTER#"3

CHARA'CTER#"4

------------------~

DR ______________________________~r_l~

______~

DRR

RR,RR __________________~IS~ly~I~NI~lc~IH~I_AI~R~IS~ly~I_N~1~lc~IH~I~AI_R~ls~ly~I_N~1~lc~IH~I_A~IR~11~1~21_3~14~15~16~1_7~lp~I___
~--......J~~~

CHARACTER#"'
CHARACTER#"2
CHARACTER#"3
CHARACTER#"4
~I
OE ________________________________________________________~I

______

SFR

CLOCK SHOWN IS BIT RATE CLOCK (1 X)
11-2900

Figure B-6

Synchronous Timing Example (P /SA T)
B-19

Table 8-6

SYNC Mode Control Definition
Character Format

Control
W
L
S

M
S
2

M
S
I

I
I
I
I
I
I
I
I
I
I
I
I

0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
I
I
I
I
I
I

W
L
S
I
0
0
0
I
I
I
0
0

0
I
I
I

P
I
0
0
I
0
0
I
0
0
I
0
0

E
P
E
0
I

X
0

1
X
0
I

X
0
1
X

Data
Bits

Added
Parity
Bit

5
5
5
6
6
6
7
7
7
8
8
8

Odd
Even
None
Odd
Even
None
Odd
Even
None
Odd
Even
None

Sets to SYNC mode

The character transferred into the transmitter register (from the transmitter holding register or the fill
character holding register) is determined at the center of the last bit of the character being transmitted.
If, at this time, no character has been loaded into the transmitter holding register, the fill character is
loaded into the transmitter register at the end of the bit being transmitted and a data not available
(DNA) flag is set to a high-level output voltage. This fill character is loaded into the transmitter
holding register, at which time, the DNA flag is reset, the fill character will be completed and the
newly-loaded synchronous character will follow contiguously.
A high-level output voltage, on the THRE flag indicates that the transmitter holding register is empty
and may be loaded with a character. Data on the inputs of the transmitter holding register is loaded
when the transmitter holding register load (THRL) line is strobed to a low-level output voltage. This
data must be stable prior to THRL going to a high-level input voltage, since this register is a set of dc
latches which are enabled by THRL.
If the clear-to-send (CTS) line is at a low-level input voltage, or if the transmitter register is in the
process of transmitting a character, the character in the transmitter holding register will not be transferred down to the transmitter register and the THRE flag will remain at a low.. level output voltage.

B-20

Raising the CTS line to a high-level input voltage, or completion of transmission of a character from
the transmitter register, causes the automatic transfer of the character in the transmitter holding register to the transmitter register which forces the THRE flag to be set to high-level output voltage. The
selected parity is added to the data during the transfer to the transmitter register and serial transmission is initiated as an NRZ waveform. A low-level input voltage applied to CTS during transmission
allows completion of that character only, after which the device enters the idle state and the output will
continue to mark until a high-level input voltage is applied.
The data delimit/end of character flag has been provided to indicate the transmission of serial data on
the transmitter register output.
The data delimit/end of character flag is defined as a low-level output voltage during transmission of
the last bit of a synchronous character and when the P /SA T is in the idle state.
B.4 DC003 INTERRUPT CHIP
The interrupt chip as shown in Figure B-7 is an 18 pin, 300 center, dip device that provides the circuits
to perform an interrupt transaction in a computer system that uses a pass-the-pulse type arbitration
scheme. The device is used in peripheral interfaces and provides two interrupt channels labeled A and
B, with the A section at a higher priority than the B section. Bus signals use high-impedance input
circuits or high-drive-open-collector outputs, which allows the device to directly attach to the computer systems bus. Maximum current required from the Vee supply is 140 rnA.
Signal mnemonics are listed in Table B-7. Timing diagrams are illustrated in Figures B-8 and B-9.

DC003
17
RQSTA H
15

16
ENA DATA H

ENA ST H

ENA ClK H

BIRQ l

07 J'O
05

1'0

03 J'O

BIAKI l

BIAKO l

BINIT l

INITO l

BDIN l

VECTOR H

I:or

I-

... 04
01

02
ENB ClK H

VEC RQSTB H

12
ENB DATA H
11

10
ENB ST H

RQSTB H

11 5042

Figure B-7

De003 Logic Symbol Diagram

B-21

Table B-7

DC003 Signals

Symbol

Function

INTERRUPT VECTOR
GATING SIGNAL

VECTOR H

This signal should be used to gate the
appropriate vector address onto the
bus and to form the bus signal called
BRPLY L.

VECTOR REQUEST
B SIGNAL

VEC RQSTB H When asserted indicates RQST B service vector address is required. When
un asserted indicates RQST A service
vector address is required. VECTOR
H is the gating signal for the entire
vector address; VEC RQST B H is
normally bit 2 of the address.

BUS DATA IN

BDIN L

The BDIN signal always precedes a
BIAK signal.

INITIALIZE OUT

INITO L

This is the buffered BINIT L signal
used in the device interface for general
initialization.

BUS INITIALIZE

BINIT L

When asserted, this signal brings all
driven lines to their un asserted state
(except INITO L).

BUS INTERRUPT
ACKNOWLEDGE

BIAKO L

This signal is the daisy-chained signal
that is passed by all devices not
requesting interrupt serVIce (see
BIAKI L). Once passed by a device, it
must remain passed until a new
BAIKI L is generated.

BUS INTERRUPT
ACKNOWLEDGE

BIAKI L

This signal is the processor's response
to BIRQ L true. This signal is daisychained such that the first requesting
device blocks the signal propagation
while non-requesting devices pass the
signal on as BIAKO L to the next
device in the chain. The leading edge
of BIAKI L causes BIRQ L to be
un asserted by the requesting device.

Pin Number I/O Name

B-22

Table B-7

DC003 Signals (Cont)

Pin Number I/O Name

Symbol

Function

ASYNCHRONOUS BUS
INTERRUPT REQUEST

BIRQ L

The request is generated by a true
RQST signal along with the associated true interrupt enable signal. The
request is removed after the acceptance of the BDIN L signal and on the
leading edge of the BAIKI L signal or
the removal of the associated interrupt enable or due to the removal of
the associated request signal.

17
10

DEVICE INTERRUPT
REQUEST SIGNAL

RQSTA H
REQSTB H

When asserted with the enable A flipflop asserted will cause the assertion
of BIRQ L on the bus. This signal line
normally remains asserted until the
request is serviced.

16
11

INTERRUPT ENABLE

ENA ST H
ENB ST H

This signal indicates the state of the
interrupt enable A internal flip-flop
which is controlled by the signal line
ENA DATA H and the ENA CLK H
clock line.

15
12

INTERRUPT ENABLE

ENA DATA H The level on this line, in conjunction
ENB DATA H with the EN A CLK H signal, determines the state of the internal interrupt enable A flip-flop. The output of
this flip-flop is monitored by the ENA
ST H signal.

14
13

TNTERRUPT ENABLE

ENA CLK H
ENB CLK H

B-23

When asserted (on the positive edge),
interrupt enable A flip-flop assumes
the state of the ENA DATA H signal
line.

----,
BINIT l

300

MIN _

300 '---MIN

H"-----""

INITO l

7-35

-.J

ENA DATA H

30 MIN ----,

ENA elK H

------------~~'~--~-----------------------------t
7-30

ENA ST H

--------------~~~--------------------------------~-----------------

RQSTA H

BIRQ l

15-65

20-90

31'----·~--'

BDIN l

35 MIN

VECTOR H

;:::f. . . ._",-,

BIAKI l

--1

_____________________

.......- - - - - a

10-45

35 MIN

~ 10-45

BIAKO l

12-55

r-=
H _____~---'
--1

12-55

NOTE: All speeds in nanoseconds.
11-5043

Figure B-8 DC003 Timing Diagram
(Section A Only)

B-25

BINIT L

INITOL

~ ~~~

+r-==
~?~ r-

R H

12-50

t.= 7-35

ENB DATA H
30 MIN----,
ENB ClK H

___________~~
t~--~________________- -____________________________________________
7-30 - - - .

ENB ST H

BIRO L
15-65

~-----------------------------------------------

----1

RQSTB H

ENA DATA H
30MIN.

ENA ClK H

ENA ST H

ROSTA H

B DIN l

F1 r----I

BIAKI l

35 MIN - '
VECTOR H

10-45

t=4-J.;:=====~-10-45

,
35MIN - - J

•

--------------------------------~~ ---1~~--------------~~
10-45

VECCOSTB H

~t=

15-65 - - - .

10-45

~-15---65--

NOTE: All speeds in nanoseconds.
11-5041

Figure B-9 DC003 Timing Diagram
(Sections A & B)

B-27

APPENDIX C
INTEGRATED CIRCUITS

The following pages contain reference information for integrated circuits used within DUVl1. Logic
diagrams, and truth tables in most cases shown. The integrated circuits found in this appendix are:
74LS74
74LS174
74LS 175
74LS253
DC004
DC005
In the case of the DC004 protocol chip and DC005 transceiver, a pictorial of the chip with pin designations is provided.

C-l

74LS74

D-TYPE FLIP-FLOP

TRUTH TABLE FOR
7474 STANDARD CONFIGURATION
(EACH FLIP· FLOP)

t n +1

tn
Preset
Pin 4(10)

Clear
Pin 1(13)
High
High
L0w
High
Low

Hi~h

High
High
Low
Low

D I,lput
Pin 2(12)
Low
High
X
X
X

o Side
Pin 6
High
Low
High
Low
High

1 Side
Pin 5
Low
High
Low
High
High

tn = bit time before clock pulse.
tn+1 = bit time after clock pulse.
X = irrelevant

STANDARD CONFIGURATION

REDIFINED CONFIGURATION
PRESO

PRESET

01
02

7474

7474
03

03 C

0 06

04
CLEAR

CLEAR
PRESET
12

11
10

CLEAR

Vce PI N 14
GND=PIN07

IC-7474

Note: 7474 is shown. LS only signifies low power Schottky.

C-2

74LS174

HEX D FLIP-FLOP REGISTER

DO (3)

(2) RO( 1)

r--~CLOCK

TRUTH TABLE

OUTPUT
tn +1

R(11

H
L

INPUT

CLEAR

(5)

(4)

tn = Bit time before

R1 (1)

..--+--(,CLOCK

clock pulse.
t n +1 =Bit time ofter
clock pulse.

CLEAR

(6)

(7) R2( 1)

CLOCK
CLEAR

R5(1 )

R4(1 )

R3(1 )

15
(10)

03 (11)
13
11

74174

6
02

R2 (1)

Rl (1)

RO(l )

CLR

R3(1 )

12
CLOCK

CLEAR
7

(13)

(12)

R4(1)

2
CLOCK
CLEAR

CLK

9
(14)
,05

(15)
R5( 1)

Pin (16) = VCC. Pin (8)= GNO
IC-74174

Note: 74174 is shown. LS only signifies low power Schottky.

C-3

74LSI75

QUAD STORAGE REGISTER

TRUTH TABLE
INPUT
tn

OUTPUTS
tnT 1

R{1 }R{O}

H
l

(2)

(4)

(3)

tn = Bit time before
cloc k pulse.
tn+1 = Bit time ofter
clock pulse.

(5)

(7)

(1 )

elK {O}

(6)

CLEAR

(12)

R3 {1}
R3{O}

12
DATA
INPUTS

R2{ 1}

R2{O}

R 1{ 1}
RHO}

RO{1 }
RO{O}

(11)

CLEAR

10
11
7

OUTPUTS
03 (13)

CLOCK
4

R2 (10)
{1 }

ClK {O}

74175

02 C>----+--4-----l 02

~--.........--+-nClK

R3 {14}

{O}

CLEAR
3
CLEAR

elK
Pin (16)= Vee. Pin (8) =GNO
IC-74175

Note: 74175 is shown. LS only si~nifies low power Schottky.

C-4

74tS253 4:1 MULTIPLEXER
The 74LS253 is a dual, 4-line to I-line data selector/multiplexer.

CONT0
A0

DATA
INPUTS

OUTPUTS

DATA
INPUTS

D1 13

CONT1

15
-----------------0

Vcc=(16)
Gnd = (8)
LOGIC DIAGRAM

C:l

CON Tn

F'l

X
X
X

X
X
X
X
X

X
X
X
X
X
X
X

X
X

X
X
X
X
X
X

LO
HI

X
X
X
X

X = DON'T CARE
Z = HI IMPEDANCE
TRUTH TABLE
Ie -74LS253

C-5

DC004

PROTOCOL CHIP

VECTOR H
BOAL2 L
BOALl L
BOALO L
SWTBT L
BSYNC L
BOIN L
BRPLY L
BOOUT L
GNO

,......"VVIr-

ENS H

VCC
ENS H
RXCX H
SEL6 L
SEL4 L
SEL2 L
SELO L
OUTHS L
OUTlB L
INWO L

+vcc

19~~----------~O

1~------~------------~---------,

~ VCC

ENS

LATCH

BSYNC L

S OA l2 L

~~~~G

@}- GNO

02~-------+----!

OAl2

SEL 6 l
DECODER
SEL 4 L

BOAL1 L

03~------+----IO

SEL 2 L

01
LATCH

OAL 1

G O~------+--------------------------i
BOALO L

SEL 0 L

04·~--------+----IO

00
LATCH

OUTHB L

OUTlS L

O~-----~----+-~

RXCX H

BRPLY L
BDOUT L

VECTOR H

BDIN L

INWD L
IC-0174

C-6

D(,005

BUS TRANSCEIVER

JA1 L
JA2 L

20
2

18 DATO H

MATCH H 3

BUSO

BUS1

Vee

19 JA3 L

REC H

17 DAT1 H

XMIT H

DAT3 H

15 JV2 H

JV3 H

DAT2 H

JV1 H

BUS3 L

MENB L

BUS2 L

BUSO L

GND

BUS1 L

DATO

JV1

DAT1

JV2

DAT2

JV3

DAT3

MATCH

-=
JA1

BUS2

JA2

BUS3

JA3

MENB

L~-

XMIT

REC

~~-----------------+--~03

'-----L~

¥--~-20- -V-c-C- - ITQ]- 1-0- G-N-D-L- I
IC-DC005

C-7

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DUVll LINE INTERFACE
TECHNICAL MANUAL
EK-DUVII-TM-OOI

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