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EK-DPV11-TM-002

November 1980

106 pages

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Document:	DPV11 Serial Synchronous Interface Technical Manual
Order Number:	EK-DPV11-TM
Revision:	002
Pages:	106
Original Filename:	EK-DPV11-TM-002_Nov80.pdf

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DPV 11 serial synchronous
interface technical manual

EK-DPV11-TM-002

DPV 11 serial synchronous
interface technical manual

digital equipment corporation • merrimack, new hampshire

1st Edition, July 1980
2nd Printing (Rev), November 1980

The material in this manual is for informational purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS
DECLAB

DECsystem-IO
DECSYSTEM-20
DIBOL
EduSystem
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS

MINC-II

CONTENTS
Page
CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.6
1.7

SCOPE ........................................................................................................................ 1-1
DPVll GENERAL DESCRIPTION ...................................................................... 1-1
DPVll OPERATION ............................................................................................... 1-2
DPVll FEATURES .................................................................................................. 1-2
GENERAL SPECIFICATIONS ............................................................................. 1-2
Environmental Specifications ............................................................................ 1-2
Electrical Specifications ..................................................................................... 1-3
Performance Parameters .................................................................................... 1-3
DPVll CONFIGURATIONS .................................................................................. 1-3
EIA STANDARDS OVERVIEW ............................................................................ 1-3

CHAPTER 2

INSTALLATION

2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.5

INTRODUCTION .................................................................................................... 2-1
UNPACKING AND INSPECTION ....................................................................... 2~1
PRE-INSTALLATION REQUIREMENTS .......................................................... 2-1
INSTALLATION ....................................................................................................... 2-6
Verification of Hardware Operation .................................................................. 2-7
Connection to External Equipment/Link Testing ............................................ 2-8
TEST CONNECTORS ............................................................................................. 2-8

CHAPTER 3

3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.4.1
3.4.2
3.5

INTRODUCTION .................................................................................................... 3-1
DPVll REGISTERS AND DEVICE ADDRESSES ............................................. 3-1
REGISTER BIT ASSIGNMENTS ......................................................................... 3-2
Receive Control and Status Register (RXCSR) ............................................... 3-2
Receive Data and Status Register (RDSR) ...................................................... 3-2
Parameter Control Sync/Address Register (PCSAR) ..................................... 3-2
Parameter Control and Character Length Register (PCSCR) ........................ 3-2
Transmit Data and Status Register (TDSR) ..................................................... 3-2
DATA TRANSFERS .............................................................................................. 3-19
Receive Data .................................................................................................... 3-19
Transmit Data .................................................................................................. 3-20
INTERRUPT VECTORS ....................................................................................... 3-21

iii

CONTENTS (Cont)
Page
CHAPTER 4

TECHNICAL DESCRIPTION

4.1
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.1.3
4.2.1.4
4.2.1.5
4.2.1.6
4.2.1.7
4.2.1.8
4.2.1.9
4.2.1.10
4.2.2
4.2.2.1
4.2.2.2
4.3
4.3.1
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
4.3.2
4.3.2.1
4.3.2.2
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10

INTRODUCTION .................................................................................................... 4-1
FUNCTIONAL DESCRIPTION ............................................................................ 4-1
Logic Description ............................................................................................... 4-1
Bus Transceivers ........................................................................................ 4-1
Read/Write Control .................................................................................. 4-1
USYNRT and Bidirectional Buffer .......................................................... 4-1
Receive Control and Status Register ........................................................ 4-1
Transmit Control and Status Register ...................................................... 4-1
Interrupt Logic .......................................................................................... 4-3
Data Set Change Logic ............................................................................. 4-3
Clock Circuit .............................................................................................. 4-3
EIA Level Converters ................................................................................ 4-3
Charge Pump ............................................................................................. 4-3
General Operational Overview .......................................................................... 4-3
Receive Operation ..................................................................................... 4-3
Transmit Operation ................................................................................... 4-5
DETAILED DESCRIPTION ................................................................................... 4-5
Bus Transceivers ................................................................................................. 4-5
Address Selection ...................................................................................... 4-5
Address Decode ......................................................................................... 4-6
Bus Data Transfers .................................................................................... 4-6
Vector Generation ...................................................................................... 4-6
Read/Write Control Logic ................................................................................ 4-6
Register Decode ......................................................................................... 4-6
USYNRT Control ..................................................................................... 4-7
USYNRT, RXCSR and PCSCR ...................................................................... 4-7
USYNRT ................................................................................................. 4-10
Receive Control and Status Register ...................................................... 4-10
Parameter Control and Character Length Register ............................... 4-10
Interrupt Logic ................................................................................................. 4-10
Data Set Change Circuit. ................................................................................. 4-11
Clock Circuit .................................................................................................... 4-11
USYNRT Timing ........................................................................................... 4-12
EIA Receivers ................................................................................................ 4-12
EIA Drivers ....................................................... ...... ..... ................... ....... ........ 4-12
Maintenance Mode ....... ..... .............................. ......... ... .... ... .... .......... ......... ..... 4-12

CHAPTERS

MAINTENANCE

5.1
5.2
5.3
5.4
5.5
5.5.1
5.5.2
5.5.3
5.5.3.1
5.5.3.2
5.5.3.3

SCOPE ........................................................................................................................ 5-1
TEST EQUIPMENT RECOMMENDED .............................................................. 5-1
MAINTENANCE PHILOSOPHY ......................................................................... 5-2
PREVENTIVE MAINTENANCE .......................................................................... 5-2
CORRECTIVE MAINTENANCE ......................................................................... 5-2
Maintenance Mode ............................................................................................. 5-2
Loopback Connectors ......................................................................................... 5-2
Diagnostics .......................................................................................................... 5-2
CVDPV* Functional Diagnostic ............................................................... 5-3
DEC/XII CXDPV Module ...................................................................... 5-4
Data Communications Link Test CVCLH* (DCLT) .............................. 5-4

CONTENTS (Cont)
Page
APPENDIX A

DIAGNOSTIC SUPERVISOR SUMMARY

A.1
A.2
A.3
A.4
A.4.1
A.4.2
A.S

INTRODUCTION .................................................................................................. A-I
VERSIONS OF THE DIAGNOSTIC SUPERVISOR ........................................ A-I
LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC ..................... A-I
SUPERVISOR COMMANDS ............................................................................... A-3
Command Switches .......................................................................................... A-4
Control/Escape Characters Supported ........................................................... A-4
THE SETUP UTILITy........................................................................................... A-S

APPENDIXB

USYNRT DESCRIPTION

APPENDIXC

IC DESCRIPTIONS

C.l
C.2
C.3
C.4
C.S
C.6
C.7
C.8
C.9

GENERAL ............................................................................................................... C-l
DC003 INTERRUPT CHIP ................................................................................... C-l
DC004 PROTOCOL CHIP ..................................................................................... C-3
DCOOS BUS TRANSCEIVER CHIP..................................................................... C-3
26LS32 QUAD DIFFERENTIAL LINE RECEIVER ........................................ C-6
8640 UNIBUS RECEIVER.................................................................................... C-6
8881 NAND ............................................................................................................. C-6
9636A DUAL LINE DRIVER ............................................................................... C-6
9638 DUAL DIFFERENTIAL LINE DRIVER ................................................... C-6

APPENDIXD

PROGRAMMING EXAMPLES

GLOSSARY

ILLUSTRATIONS
Figure No.
1-1
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-S
3-6
4-1
4-2
4-3
4-4
4-S
A-I

Page

Title

DPVll System ............................................................................................................ 1-1
DPVll Jumper Locations .......................................................................................... 2-4
H32S9 Turn-Around Test Connector ......................................................................... 2-8
RS-423-A with H32S9 Test Connector ................................................................... 2-10
H3260 On-Board Test Connector ............................................................................. 2-11
DPVll Register Configurations and Bit Assignments .............................................. 3-3
Receive Control and Status Register (RXCSR) Format .......................................... 3-4
Receive Data and Status Register (RDSR) Format. ................................................. 3-8
Parameter Control Sync/Address Register (PCSAR) Format. .............................. 3-11
Parameter Control and Character Length Register
(PCSCR) Format ...................................................................................................... 3-13
Transmit Data and Status Register (TDSR) Format .............................................. 3-17
DPVll Block Diagram ............................................................................................... 4-2
Simplified Functional Diagram .................................................................................. 4-4
Register Decode .......................................................................................................... 4-8
Timing for Read Operation ........................................................................................ 4-9
Timing for Write Operation ..................................................................................... 4-10
Typical XXDP + /Diagnostic Supervisor Memory Layout..................................... A-2

ILLUSTRATIONS (Cont)
Figure No.
B-1
B-2
C-l
C-2
C-3
C-4
C-5
C-6
C-7
C-8

Title

Page

Terminal Connection Identification Diagram
(2112517-0-0 Variation) ........................................................................................... B-2
5025 Internal Register Bit Map (2112517-0-0 Variation) ....................................... B-3
DC003 Logic Symbol ............................................................................................... C-l
DC004 Simplified Logic Diagram ........................................................................... C-4
DC005 Simplified Logic Diagram .... .......... ......................... .................... ......... ....... C-7
26LS32 Terminal Connection Diagram and Terminal
Indentification ........................................................................................................... C-9
8640 Equivalent Logic Diagram ..............................................................................C-l 0
8881 Pin Identification .............................................................................................C-l 0
9636A Logic Diagram and Terminal Identification ................................................ C-ll
9638 Logic Diagram and Terminal Identification ................................................... C-12

TABLES
Table
No.
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
3-6
4-1
4-2
5-1
C-l
C-2
C-3

Title

Page

Configuration Sheet .................................................................................................... 2-1
Vector Address Selection ............................................................................................ 2-5
Device Address Selection ........................................................................................... 2-6
Voltage Requirements ................................................................................................ 2-7
H3259 Test Connections ............................................................................................. 2-9
DPV11 Registers ......................................................................................................... 3-1
Receive Control and Status Register (RXCSR) Bit
Assignments ................................................................................................................ 3-5
Receive Data and Status Register (RDSR) Bit Assignments ................................... 3-8
Parameter Control Sync/Address Register (PCSAR)
Bit Assignments ........................................................................................................ 3-11
Parameter Control and Character Length Register
(PCSCR) Bit Assignments ....................................................................................... 3-14
Transmit Data and Status Register (TDSR) Bit Assignments ............................... 3-17
Register Selection ....................................................................................................... 4-9
USYNRT Register Select .......................................................................................... 4-9
Test Equipment Recommended ................................................................................. 5-1
DC003 Pin/Signal Descriptions .................................................................................C-2
DC004 Pin/Signal Descriptions .................................................................................C-5
DC005 Pin/Signal Descriptions .................................................................................C-8

PREFACE
This manual was written to satisfy the needs of Field Service and Educational Service Training personnel.
It contains the following categories of information.

•

General description including features, specifications, and configurations

•

Installation

•

Programming

•

Technical Description

•

Maintenance

The manual also contains four appendixes which include diagnostic information, integrated circuit descriptions, and programming examples.
The DPVll Field Maintenance Print Set (MP00919) contains useful additional information.

vii

CHAPTER 1
INTRODUCfION
1.1 SCOPE
This chapter contains introductory information about the DPVll. It includes a general description,
and a brief overview of the DPVll operation, features, general specifications, and configurations.
1.2 DPV11 GENERAL DESCRIPTION
The DPVll is a serial synchronous line interface for connecting an LSI-II bus to a serial synchronous
modem that is compatible with EIA RS-232-C interface standards and EIA RS-423-A and RS-422-A
electrical standard~. EIA RS-422-A compatibility is provided for use in local communications only
(timing and data leads only). The DPVll is intended for character-oriented protocols such as BISYNC,
byte count-oriented protocols such as DDCMP, or bit-oriented data communication protocols such as
SDLC. The DPVl1 does not provide automatic error generating and checking for BISYNC.
The DPVll consists of one double-height module and may be connected to an EIA RS-232-C modem
by a BC26L-25 (RS-232-C) cable.
The DPVll is a bus request device only and must rely on the system software for service. Interrupt
control logic generates requests for the transfer of data between the DPVll and the LSI-II memory by
means of the LSI-II bus. (Figure 1-1 shows the DPVll system.)

TELEPHONE
DPV11

BC26L- 25

RS-232-C t - -L_1N_E_ _.,
MODEM

CJ)

co
I

CJ)

CPU

....J

MEM

MK-1320

Figure I-I

DPVll System

1-1

1.3 DPVll OPERATION
The DPVll is a double-buffered program interrupt interface that provides parallel-to-serial conversion
of data to be transmitted and serial-to-parallel conversinn of received data. The DPVll can operate at
speeds up to 56K b/s.* It has five 16-bit registers which can be accessed in word or byte mode. These
registers are assigned a block of four contiguous LSI-II bus word addresses that start on a boundary
with the low-order three bits being zeros. This block of addresses is jumper-selectable and may be
located anywhere between 1600008 and 1777768. Two of these registers share the same address. One is
accessed during a read from the address, the other during a write to the address. For a detailed description of each of the five registers, refer to Chapter 3. These registers are used for status and control
information as well as data buffers for both the transmitter and receiver portions of the DPVll.
1.4 DPVll FEATURES
Features of the DPVll include:
•

Full-duplex or half-duplex operation

•

Double-buffered transmitter and receiver

•

EIA RS-232-C compatibility

•

All EIA RS-449 Category I modem control

•

Partial Category II modem control to include incoming call, test mode, remote loopback,
and local loop back

•

Program interrupt on transitions of modem control signals

•

Operating speeds up to 56K bls (may be limited by software or CPU memory)

•

Software-selectable diagnostic loopback

•

Operation with bit-, byte count-, or character-oriented protocols

•

Internal cyclic redundancy check (CRC) character generation and checking (not usable
with BISYNC)

•

Internal bit-stuff and detection with bit-oriented protocols.

•

Programmable sync character, sync insertion, and sync stripping with byte count-oriented
protocols.

•

Recognition of secondary station address with bit-oriented protocols.

1.5 GENERAL SPECIFICATIONS
This paragraph contains environmental, electrical, and performance specifications for the DPVll.
1.5.1 Environmental Specifications
The DPVll is designed to operate in a Class C environment as specified by DEC Standard 102 (extended).
50 C (41 0 F) to 60 0 C (140 0 F)
Operating Temperature
Relative Humidity

10% to 90% with a max. wet bulb temperature of 28 0 C (82 0
F) and a min. dew point of 2 0 C (36 0 F)

*Tbe actual speed realized may be significantly less because of limitations imposed by the software and/or CPU memory
refresh.

1-2

1.5.2 Electrical Specifications
The DPVll requires the following voltages from the LSI-II bus for proper operation.
+ 12 V at 0.30 A max. (0.15 A typical)
+5 V at 1.2 A max. (0.92 A typical)
The interface includes a charge pump to generate a negative voltage required to power the RS-423-A
drivers.
The DPVll presents 1 ac load and 1 dc load to the LSI-II bus.

1.5.3 Performance Parameters
Performance parameters for the DPVll are listed as follows.
Operating Mode

Full or half-duplex

Data Format

Synchronous BISYNC, DDCMP, and SDLC

Character Size

Program-selectable (5-8 bits with character-oriented
protocols and 1-8 bits with bit-oriented protocols)

Max. Configuration

16 DPVll modules per LSI-II bus

Max. Distance

15 m (50 ft) for RS-232-C. 61 m (200 ft) for RS-423AjRS-422-A (Distance is directly dependent on speed,
and 200 ft is a suggested average. See RS-449 specification for details.)

Max. Serial Data Rates

56K bjs (May be less because of software and memory
refresh limitations.)

1.6 DPVll CONFIGURATIONS
There are two DPVll configurations, the DA and the DB.
DPVII-DA
Unbundled version consists of:
M8020 module
Module Configuration Sheet (EK-DPVII-CG)
DPVII-DB
Bundled version consists of:
M8020 module
H3259 turn-around connector
BC26L-25 cable
DPVll User Manual (EK-DPVII-UG)
LIB kit (ZJ314-RB)
Field Maintenance Print Set (MP00919)
Turn-around connectors, cables and documentation may be purchased separately.

1.7 EIA STANDARDS OVERVIEW (RS-449JRS-232-C)
The most common interface standard used in recent years has been the RS-232-C. However, this standard has serious limitations for use in modern data communication systems. The most critical limitations
are in speed and distance.
1-3

For this reason, RS-449 standard has been developed to replace RS-232-C. It maintains a degree of
compatibility with RS-232-C to accommodate an upward transition to RS-449.
The most significant difference between RS-232-C and RS-449 is in the electrical characteristics of
signals used between the data communication equipment (DCE) and the data terminal equipment
(DTE). The RS-232-C standard uses only unbalanced circuits, while the RS-449 uses both balanced
and unbalanced electrical circuits. The specifications for the types of electrical circuits supported by
RS-449 are contained in EIA standards RS-422-A for balanced circuits and RS-423-A for unbalanced
circuits. These new standards permit much greater transmission speed and will allow greater distance
between DTE and DCE. The maximum transmission speeds supported by RS-422-A and RS-423-A
circuits vary with cable length; the normal speed limits are 20K bls for RS-423-A and 2M bls for RS422-A, both at 61 m (200 feet).
Another major difference between RS-232-C and RS-449 is that additional leads are needed to support
the balanced interface circuits and some new circuit functions. Two new connectors have been specified
to accommodate these new leads. One connector is a 37-pin Cinch used in applications requiring secondary channel functions. Some of the new circuits added in RS-449 support local and remote loop back
testing, and stand-by channel selection.

1-4

CHAPTER 2
INSTALLATION
2.1 INTRODUCTION
This chapter provides all the information necessary for a successful installation and subsequent checkout of the DPVll. Included are instructions for unpacking and inspection, pre-installation, installation
and verification of operation.
2.2 UNPACKING AND INSPECfION
The DPVll is packaged in accordance with commercial packing practices. Remove all packing material and verify that the following are present.
M8020 module
H3259 turn-around connector
BC26L-25 cable
DPVll User Manual (EK-DPVII-UG)
LIB kit (ZJ314-RB)
Field Maintenance Print Set (MP00919)
Inspect all parts carefully for cracks, loose components or other obvious damage. Report damages or
shortages to the shipper immediately, and notify the DIGITAL representative.

2.3 PRE-INSTALLATION REQUIREMENTS
Table 2-1 (Configuration Sheet) provides a convenient, quick reference for configuring jumpers.
Table 2-1

Configuration Sheet

(WI-W2) Driver Attenuation Jumper
Driver
Terminal
Timing

Normal*
Configuration

Alternate*
Option

WI to W2

Not connected

Description
Bypasses
attenuation
resistor.
Jumper must be removed for certain modems to operate properly.

(W3-Wll) Interface Selection Jumpers
Input
Signals

Normal*
Configuration

SQ/TM
(PCSCR-5)

W5 toW6

DM (DSR)
(RXCSR-9)

Not connected

Alternate*
Option

Description
Signal quality

W7 toW6

Test mode

WIO to W9

Data mode return for RS-422-A

*Normal configuration is typically RS-423-A compatible. Alternate option is typically RS-422-A compatible.

2-1

Table 2- t

Configuration Sheet (Cont)

(W3-W II) Interface Selection Jumpers (Cont)
Output
Signals

Normal*
Configuration

SFjRL
(RXCSR-O)

W3 toW4

Local
Loopback

Alternate *
Option

Description
Select frequency

W5 toW3

Remote loopback

W8 toW9

Not connected

Localloopback

Not connected

W8 to Wll

Localloopback (alternate pin)

Description

(WI2-WI7) Receiver Termination Jumpers
Receiver

Normal*
Configuration

Alternate *
Option

Receive Data

Not connected

W12 to WI3

Send Timing

Not connected

W14 to W15

Receive
Timing

Not connected

W16 to WI7

Connects terminating resistor for
RS-422-A compatibility

(WIS-W23) Clock Jumpers
Function
NULL MODEM
CLK

Clock Enable

Normal*
Configuration

Alternate*
Option

Sets NULL ClK MODEM CLK
to 2 kHz.

W20 to WI8

WI9 to W21
W22 to W23

Description

W21 to WI8

Sets NULL MODEM CLK to
50 kHz.

WI9 to W2I
W22 to W23

Always installed except for factory
testing.

Description

(W24-W2S) Data Set Change Jumpers
Modem Signal
Name

Normal*
Configuration

Alternate *
Option

Data Mode (DSR)

W26 to W24

Not connected

Clear to Send

W26 to W25

Not connected

Incoming Call

W26 to W27

Not connected

Receiver Ready
(Carrier Detect)

W26 to W28

Not connected

Connects the DSCNG flip-flop to
the respective modem status signal
for transition detection.
Note: W26 is input to DSCNG flipflop

*Normal configuration is typically RS-423-A compatible. Alternate option is typically RS-422-A compatible.

2-2

Table 2-1

Configuration Sheet (Cont)

Device Address Jumpers
GND AI2
W29 W31

All
W30

AIO
W36

A9
W33

A8
W32

A7
W39

A6
W38

A5
W37

A4
W34

A3
W35

NOTE
The address to which the DPVll is to respond is
daisy-chain jumpered to W29 (GND).
Vector Address Jumpers
D8
W43

D7
W42

D6
W41

D5
W40

D4
W44

D3
W45

Source
W46

NOTE
Vector address to be asserted is daisy-chain jumpered to W46.
NOTE
Table 2-1 shows the recommended normal and alternate jumpering schemes. Any deviation from these
will cause diagnostics to fail and require restrapping
for full testing and verification. It is recommended
that customer configurations that vary from this
scheme not be contractually supported.
Prior to installing the DPVII, perform the following tasks.
1.

Verify that the following modem interface wire-wrap jumpers are installed (Figure 2-1).
W26 to W25 to W24 to W28 to W27
W22 to W23 and WI9 to W21
WI8 to W20
W5 to W6
W3 to W4
W8 to W9
WI to W2
This is the shipped configuration. Some of these jumpers may be changed when the module is
connected to external equipment for a specific application. The RS-423-A NULL MODEM
eLK is set to 2 kHz as shipped.

Based on the LSI-II bus floating vector scheme or user requirements, determine the vector
address for the specific DPVII module being installed and configure W40 through W46
accordingly (Table 2-2). The floating vector ranking is 22.

Based on the LSI-II bus floating address scheme or user requirements, determine the device
address range for the DPVII module and configure W30 through W39 accordingly (Table
2-3). Devices may be physically addressed starting at 160000 and continuing through
177776; however, there may be some software restrictions. The normal addressing convention is as shown in Table 2-3. The floating address ranking is 44.

2-3

0-0

TERMINAL
TIMING

O'O<YOO

0000

/~~~
~
012}
013 (TERMINATING
0 14
RESISTOR
JUMPERS
O 15
FOR RS-422-A
016
017

INTERFACE
SELECTION
JUMPERS

c500b em
W18 20

CLOCK JUMPERS

~
24

26* 28

DATA SET CHANGE JUMPERS
*W26 IS INPUT TO DSCNG FLIP FLOP

SHIPPED
ADDRESS
160010

SHIPPED
VECTOR
300

W2930 32 34 36 38

40 42 44 46

00000

0000
000

31 33 35 37 39

41 43 45

~OOOOO

JUMPERS ARE
DAISY CHAINED

,..--..rB

I""

MK-1338

Figure 2-1

DPVll Jumper Locations

2-4

Table 2-2

Vector Address Selection

DPV11 (M8020) VECTOR ADDRESSING
MSB
15

JUMPER
NUMBER

1 6

LSB
5

I 4

I 3

JUMPERS

1/0

W43 W42 W41 W40 W44 W45

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X

X
X

VECTOR
ADDRESS
300
310
320
330
340
350
360
370
400

--X

500

--X

600

--X

700

---

"X" INDICATES A CONNECTION TO W46.
W46 IS THE SOURCE JUMPER FOR THE VECTOR ADDRESS
JUMPERS ARE DAISY CHAINED.
MK-1341

2-5

Table 2-3

Device Address Selection

DPV11-XX (M8020) DEVICE ADDRESSING
MSB
15

12111110 1 9

...
I

•

W31

•

•I

I
JUMPER
NUMBER

18 1 7 1 6 15 I 4 I 3
JUMPERS

LSB

I
I

W30 W36 W33 W32 W39 W38 W37 W34 W35
X
X
X
X
X
X
X
X

X
X

DEVICE
ADDRESS
760010
760020
760030
760040
760050
760060
760070
760100

--X

760200

--X

760300

---

760400

--X

760500

--X

760600

--X

760700

--X

761000

---

762000

--X

763000

--X

764000

"X" INDICATES A CONNECTION TO W29. W29 IS TIED TO
GROUND. JUMPERS ARE DAISY CHAINED.
MK-1339

2.4 INSTALLATION
The DPVII can be installed in any LSI-II bus-compatible backplane such as H9270. LSI-II configuring rules must be followed. Proceed with the installation as follows. For additional information
refer to PDP-I 1/03 User Manual EK-LSIII-TM or LSI-II Installation Guide EK-LSI11-IG.
1.

Configure the address and vector jumpers at this time if they have not been previously done
(Paragraph 2.3).
WARNING
Turn all power OFF.
2-6

Connect the female Berg connector on the BC26L-25 cable to J 1 on the M8020 module t
and plug the module into a dual LSI-II bus slot of the backplane.
CAUTION
Insert and remove modules slowly and carefully to
avoid snagging module components on the card
guides.

Connect the H3259t turn-around connector to the EIA connection on the BC26L-25 cable.
The jumper WI on the H3259 turn-around connector must be removed.

Perform resistance checks from backplane pin AA2 ( + 5 V) to ground and from AD2 (+ 12
V) to ground to ensure that there are no shorts on the M8020 module or backplane.

Turn system power on.

Check the voltages to ensure that they are within the specified tolerances (Table 2-4). If
voltages are not within specified tolerances, replace the associated regulator (H780 P.S;)
Table 2-4

Voltage Requirements

Voltage

Max.

Min.

Backplane Pin

+5V
+I2V

+5.25
12.75

+4.75
+ 11.25

AA2
AD2

2.4.1 Verification of Hardware Operation
The M8020 module is now ready to be tested by running the CVDPV* diagnostic. Additional information on the DPVII diagnostics is contained in Appendix A and Chapter 5. Proceed as follows.
NOTE

The
tic.
1.

* represents the revision level of the diagnos-

Load and run CVDPV*. Three consecutive error-free passes of this test is the minimum requirement for a successful run. If this cannot be achieved, check the following.
Board seating
Jumper connections
Cable connection
Test connector
If a successful run is still unachievable, corrective maintenance is required (see Chapter 5).

Load and run the DEC/XII System Exerciser configured to test the number of DPVlls in
the system.
Each DEC/XII CXDPV module will test up to eight consecutively addressed DPVlls.
CXDPV uses a software switch register. Refer to the nEC/Xii Cross-Reference (ASF055C-MC) for switch register utilization.

t If a BC26L-25 cable and H3259 turn-around connector are not available, an on-board test connector (H3260) can be ordered separately. See Paragraph 2.5.

2-7

The DEC/XII System Exerciser is designed to achieve maximum contention with all devices that make up the system configuration. It is within this environment that the CXDPV
module runs. Its intent is to isolate DPVlls which adversely affect the system operation.
For information on configuring and running the DEC/XII System Exerciser, refer to
DEC/XII User Manual (AS-F0503B-MC) and DEC-XII Cross Reference (AS-F055CMC).
2.4.2 Connection to External Equipment/Link Testing
The DPVll is now ready for connection to external equipment.
If the DPVll is being connected to a synchronous modem, remove the H3259 connector and install the
EIA connection of the BC26L-25 cable into the connector on the modem.
Configure jumpers Wl-W28 in accordance with operating requirements (Table 2-1).
Load and run DCLT (CVCLH*) if a full link is available. This will check the final configuration and
isolate failures to the CPU, the communications link, or the modem.
If the connection to external equipment uses RS-422-A, the user must provide the cable and test support.
2.5 TEST CONNECTORS
The only test connector provided with the DPVll is the H3259 turn-around connector (Figure 2-2).
Table 2-5 and Figure 2-3 show the relationship between pin numbers, signal names and register bits
when the H3259 is connected by means of the BC26L-26 cable to the M8020 module.
NULL MODEM

TCP

RCP

SEC XMIT

WI·

14
19
SELECT FREQ

23
12

SEC REC

REMOTE LOOP
(SIGNAL QUALITY)

21
25

TEST MODE

:: :

WI" 0 - - - _____

XMIT DATA
REC DATA

RTS
C.T.S
RR

LOCAL LOOP
1::

•

DATA MODE

•• ••• •• •• •• • 0
0 •••••••••••••
H3259

• WI IS CUT FOR TESTING DPV11

20 ••_____
D._T._R.____~,,__
•

22.

INCOMING CALL

•
MI(.1329

Figure 2-2

H3259 Turn-Around Test Connector
2-8

Table 2-5

H3259 Test Connections
To

From
Pin No.
83259

Pin No.

Signal Name

Pin No.
83259

Signal Name

SEND DATA

RECEIVE DATA

REQUEST TO SEND
(RTS) (RXCSR-2)

BB&T

5&8

CLEAR TO SEND
(CTS)(RXCSR-13),
RECEIVER READY
(RR) (RXCSR-12)

LOCAL LOOPBACK
(ltL) (RXCSR-3)

DATA MODE
(DM) (RXCSR-9)

RR/MM

MM/C

21/25

SIGNAL QUALITY /
TEST MODE
(SQ/TM) (PCSCR-5)

SELECT FREQ/REMOTE 23/21
LOOPBACK
(SF /RL) (RXCSR-O)
NULL MODEM

N&R

15&17

RCVCLOCK
TXCLOCK

DATA TERMINAL
READY (DTR)
(RXCSR-l)

INCOMING CALL
(lC) (RXCSR-14)

The following accessories are available for interfacing and may be ordered separately.
•

BC26L-X cable. Available in lengths of .3, 1.8, 2.4, 3.0, 3.6, 6.1, and 7.6 meters (1, 6, 8, 10,
12, 20 and 25 feet). When ordering, the dash number indicates the desired cable length in
feet; e.g., BC26L-25 or BC26L-1.

•

H3259 cable turn-around connector

•

H856 Berg connector. Includes H856 Berg connector and 40 pins. Crimping tools are available from:
Berg Electronics, Inc.
New Cumberland, PA

•

17070

H3260 on-board test connector (includes RS-422-A testing)

The H3260 on-board test connector (Figure 2-4) may be used to test the M8020 circuitry in its entirety.
RS-422-A circuitry is not tested with the H3259 cable turn-around connector. The H3260 on-board test
connector is shipped configured for testing RS-422-A. It may be configured to test RS-422-A or RS423-A as follows.
RS-422-A

RS-423-A

W1-W2 installed
W1-W2 out
W3-W60ut
W3-W6 installed
The connectot is installed into J1 with the jumper side up.
Since the H3260 on-board test connector does not test the cable, it is recommended that the DPV11 be
tested with a turn-around connector at the modem end of the cable if possible.
2-9

SEND DATA

TX CLOCK
TCP

RECEIVE DATA

7
5

2
3

•

RCV CLOCK
RCP

•

L
2

LOCAL CLK

P
W7

SQ/TM
PCSCR-5

r THIS JUMPER

MM
SF/RL
RXCSR-O

W3//

23
PP

DATA SET

•

READY
W10

U
LL

RXCSR-3 (LL)

14
K

LOCAL LOOP BACK

RXCSR-14 (INCOMING 11
CALL)

22
20

Y
10

W
RSCSR-l (DTR)

MUST BE
REMOVED WHEN
TESTING A DPV11

DATA TERMINAL
READY

RSCSR-13 (CTS)
CLEAR TO SEND

V
RSCSR-2 (RTS)
REQUEST TO SEND

SB
M

E
M

RXCSR-12 (RR)
RECEIVER READY

NEGATIVE INPUT TO DIFFERENTIAL
RECEIVERS OMITTED FOR CLARITY

Figure 2-3

RS-423-A with H3259 Test Connector

2-10

TEST MODE
SIGN QUAL
SF/RL

SEND DATA
RX DATA
SEND DATA
(RS422)
TERM TIMING
SEND TIMING
RX TIMING
TERM TIMING
(RS422)
CLEAR TO SEND
REQ TO SEND
RX RDY
INCOMING CALL
TERM RDY
DATA MODE
DATA MODE RET
(LOCAL LOOP)
SEND TIM RET
RX TIM RET
TERM TIM RET
(RS422)

~~~

____
r?=:J
~~
W1

~'--rJ

;:
B~:

5013970A
RS422
W60-C:J-0

RS423

D~:
B

E~
W6

SEND DATA RET
RX DATA RET

r:J

K~:

H3260 TEST CONNECTOR
NOTE: 1. W1 & W2 IN
W3-W6 OUT
2. W1 & W2 OUT
W3-W6 IN

RS-423-A TESTING

RS-422-A TESTI NG
MK·1464

Figure 2-4

H3260 On-Board Test Connector

2-11

CHAPTER 3
REGISTER DESCRIPTIONS
AND PROGRAMMING INFORMATION
3.1 INTRODUCTION
This chapter describes the bit assignments and programming considerations for the DPV11. Some typical start and receive sequences for both bit- and character-oriented protocols are included.
3.2 DPVll REGISTERS AND DEVICE ADDRESSES
The five registers used in the DPV11 are shown in Table 3-1. Note that two of the registers (PCSAR
and RDSR) have the same address. This does not constitute a conflict, however, because the PCSAR
is a write-only register and the RDSR is a read-only register. These five registers occupy eight contiguous byte addresses which begin on a boundary where the low-order three bits are zero, and can be
located anywhere between 1600008 and 1777768.

Table 3-1

DPVll Registers

Mnemonic

Address

Comments

Receive Control and Status

RXCSR

16xxxO

Word or byte* addressable.
Read/write.

Receive Data and Status

RDSR**

16xxx2

Word or byte* addressable.
Read-only.

Parameter Control Sync/Address

PCSAR**

16xxx2

Word or byte addressable.
Write-only. t

Parameter Control and Character
Length

PCSCR:I:

16xxx4

Word or byte addressable.
Read/write.

Transmit Data and Status

TDSR**

16xxx6

Word or byte addressable.
Read/write.

* Reading either byte of these registers, clears data and certain status bits in other bytes. See Paragraphs 3.3.1
and 3.3.2.

** Registers contained within the USYNRT.
t It is not possible to do bit set or bit clear instructions on this register.

The high byte of this register is internal to the USYNRT.

The DPV11 uses a universal-synchronous receiver/transmitter (USYNRT) chip which accounts for a
large portion of the DPV11 's functionality. The USYNRT provides complete serialization, deserialization and buffering of data to and from the modem.
3-1

Most of the DPVll registers are internal to the USYNRT. Only the receiver control and status register (RXCSR) and the low byte of the parameter control and character length register (PCSCR) are
external.
NOTE
When using the special space sequence function, all
registers internal to the USYNRT must be written
in byte mode.
3.3 REGISTER BIT ASSIGNMENTS
Bit assignments for the five DPVl1 registers are shown in Figure 3-1. Paragraphs 3.3.1-3.3.5 provide a
description of each register using a bit assignment illustration and an accompanying table with a detailed description of each bit.
3.3.1 Receive Control and Status Register (RXCSR) (Address 16xxxO)
Figure 3-2 shows the format for the receive control and status register (RXCSR). Table 3-2 is a detailed description of the register. This register is external to the USYNRT.
NOTE
The RXCSR can be read in either word or byte
mode. However, reading either byte resets certain
status bits in both bytes.
3.3.2 Receive Data and Status Register (RDSR) (Address 16xxx2)
Figure 3-3 show the format for the receive data and status register (RDSR). It is a read-only register
and shares its address with the parameter control sync/address register (PCSAR) which is write-only.
Table 3-3 is a detailed description of the RDSR.
NOTE
The RDSR can be read in either word or byte mode.
However, reading eitber byte resets data and certain
status bits in both bytes of this register as well as
bits 7 and 10 of the RXCSR.
3.3.3 Parameter Control Sync/Address Register (PCSAR) (Address 16xxx2)
The parameter control sync/address register (PCSAR) is a write-only register which can be written in
either byte or word mode. Figure 3-4 shows the format and Table 3-4 is a detailed description of the
PCSAR. This register shares its address with the RDSR.
NOTE
Bit set (BIS) and bit clear (BIC) instructions cannot be executed on the PCSCR, since they execute
using a read-modify-write sequence.
3.3.4 Parameter Control and Character Length Register (PCSCR) (Address 16xxx4)
The parameter control and character length register (PCSCR) can be read from or written into in
either word or byte mode. The low byte of this register is external to the USYNRT and the high byte is
internal. Figure 3-5 shows the format and Table 3-5 is a detailed description of the PCSCR.
3.3.5 Transmit Data and Status Register (TDSR) (Address 16xxx6)
The format for the transmit data and status register (TDSR) is shown in Figure 3-6 and Table 3-6 is a
detailed description. The TDSR is a read/write register which can be accessed in either word or byte
mode with no restrictions. All bits can be read from or written into and are reset by Device Reset or
Bus INIT except where noted.

3-2

RXCSR
16XXXO
READ/WRITE
15

R/W

RIW

R/W

RIW

R/W

RIW

DATA
SET
CHANGE

CLR
TO
SEND

RCV
ACTIVE

DATA
MODE

RCV
DATA
READY

DATA
SET
INTR
EN

LOCAL
(LL)
LOOP

DATA
TERM
RDY

INCOMING
CALL

RCVR
STATUS
READY

RCVR
READY

SYNC
OR
FLAG
DETECT

REQ
TO
SEND

RX
ENA

RCV
INTR
EN

SF/RL

RDSR
16XXX2
READ ONLY
15

MK·1504

ASSEMB~ED

00
I

RECEIVE DATA BUFFER

BIT COUNT
I

ERROR
CHECK

RCVR
OVER
RUN

END
OF
MESG

START
OF
MESG

RCV
ABORT

PCSAR
16XXX2
WRITE ONLY
15

MK·1505

07
I

ERROR DETECTION
SELECTION
I

ALL
PARTIES
ADDR

SECONDARY STATION
~

RECEIVER SYNC
I

STRIP
SYNC OR
LOOP
MODE

PROTOCOL
SELECT

IDLE
MODE
SELECT
SECD
ADRS
MODE
SEL
MK·1506

Figure 3-1

DPV11 Register Configurations and Bit Assignments (Sheet 1 of 2)

3-3

''<c'''''-

pestR
16XXX4
REAOIWRITE
15

R/W

RIW

R/W

RIW

RECEIVER
RSVD
CHARACTER LENGTH

EXTD
ADDR
FIELD

TRANSMITTER
CHARACTER LENGTH

08
I

R/W

14
I

EXTD
CONT
FIELD

SQ/TM

MAINT
MODE
SELECT

XMTR
ACTIVE

XMIT
INTR
EN

DEVICE
RESET

XMTR
BUFFER
EMPTY

XMTR
ENAB

MK·1507

TOSR

16XXX6
REAOIWRITE
15
R

XMIT
DATA
LATE

R/W

RIW

XMIT
GO
AHEAD

END
OF
MESG

RESERVED

ABORT

RIW

R/W

R/W
I

I
,

R/W

RIW
I

R/W
I
I

TRANSMIT DATA BUFFER

START
OF
MESG
MK·150B

Figure 3-1 DPVll Register Configurations and Bit Assignments (Sheet 2 of 2)

RDAT
RY**

RX
ITEN

*
* *

ITEN

RTS

SF/RL

ENA

SFD

OS'

CNG

ACT

THIS BIT IS RESET BY READING EITHER BYTE OF THIS REGISTER.
THESE BITS ARE RESET BY READING EITHER BYTE OF RSDR,
MK·1327

Figure 3-2 Receive Control and Status Register (RXCSR) Format

3-4

Table 3-2 Receive Control and Status Register (RXCSR) Bit Assignments
Bit

Name

Description

Data Set Change
(DSCNG)

This bit is set when a transition occurs on any of the following
modem control lines:
Clear to Send
(. "1'" ~
Data Mode
~
Receiver Ready
Incoming Call R1

t,JJ

Transition detectors for each of these four lines can be disabled
by removing the associated jumper.
Data Set Change is cleared by reading either byte of the
RXCSR or by Device Reset or Bus INIT.
Data Set Change causes a receive interrupt if DSITEN (bit 5)
and RXITEN (bit 6) are both set.
14

Incoming Call
(IC)

This bit reflects the state of the modem Incoming Call line. Any
transition of this bit causes Data Set Change bit (bit 15) to be
asserted unless the Incoming Call line is disabled by removing
its jumper. This bit is read-only and cannot be Gleared by software.

Clear to Send
(CTS)

This bit reflects the state I: of the Clear to Send line of the
modem. Any transition of this line causes Data Set Change (bit
15) to be set unless the jumper enabling the Clear to Send signal
is removed.
Clear to Send is a program read-only bit and cannot be cleared
.
by software.

Receiver Ready
(RR)

This bit is a direct reflection of modem Receiver Ready lead. It
indicates that the modem is receiving a carrier signal. For external maintenance loopback, this signal must be high. If the line is
open, RR is pulled high by the circuitry.
Any transition of this bit ,causes Data Set Change (bit 15) to be
asserted unless the jumper enabling the Receiver Ready signal
is removed.
Receiver Ready is a read-only bit and cannot be cleared by software.

Receiver Active
(RXACT)

This bit is set when the USYN~.T presents the first character of
a message to the DPVll. It remains set until the receive data
path of the USYNRT becomes idle.
Receiver Active is cleared by any of the following conditions: a
terminating control character is received in bit-oriented protocol
mode; an off transition of Receiver Enable (RXENA) occurs; or
Device Reset or Bus INIT is issued.

3-5

Table 3-2

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Name

Bit

Description
Receiver Active is a read-only bit which reflects the state of the
USYNRT output pin 5.

Receiver Status
Ready (RSTARY)

This bit indicates the availability of status information in the
upper byte of the receive data and status register (RDSR). It is
set when any of the following bits of the RDSR are set: Receiver
End of Message (REOM); Receiver Overrun (RCV OVRUN);
Receiver Abort or Go Ahead (RABORT); Error Check
(ERRCHK) if VRC is selected.
Receiver Status is cleared by any of the following conditions:
reading either byte of the RDSR; clearing Receiver Enable (bit
4 of RXCSR); Device Reset, or Bus Init.
When set, Receiver Status Ready causes a receive interrupt if
Receive Interrupt Enable (bit 6) is also set.
Receiver Status Ready is a read-only bit which reflects the state
of USYNRT pin 7.

Data Mode (DM)
(Data Set Ready)

This bit reflects the state of the Data Mode signal from the
modem.
When this bit is set it indicates that the modem is powered on
and not in test, talk or dial mode.
Any transition of this bit causes the Data Set Change bit (bit
15) to be asserted unless the Data Mode jumper has been removed.
Data Mode is a read-only bit and cannot be cleared by software.

Sync or Flag
Detect (SFD)

This bit is set for one clock time when a flag character is detected with bit-oriented protocols, or a sync character is detected with character-oriented protocols.
SFD is a read-only bit which reflects the state of USYNRT pin
4.

Receive Data
Ready (RDATRY)

This bit indicates that the USYNRT has assembled a data character and is ready to present it to the processor.
If this bit becomes set while Receiver Interrupt Enable (bit 6) is
set, a receive interrupt request will result.
Receive Data Ready is reset when either byte of RDSR is read,
Receiver Enable (bit 4) is cleared, or Device Reset or Bus INIT
is issued.

RDATRY is a read-only bit which reflectes the state of USYNRT pin 6.

3-6

Table 3-2

Receive Control and Status Register (RXCSR) Bit Assignments (Cont)

Bit

Name

Description

Receiver Interrupt
Enable (RXITEN)

When set, this bit allows interrupt requests to be made to the
receiver vector whenever RDATRY (bit 7) becomes set.
The conditions which cause the interrupt request are the assertion of Receive Data Ready (bit 7), Receive Status Ready (bit
10), or Data ;Set Change (bit 15) if DSITEN (bit 5) is also set.
RXITEN is a program read/write bit and is cleared by Device
Reset or Bus INIT.

Data Set Interrupt
Enable (DSITEN)

This bit, when set along with RXITEN, allows interrupt
requests to be made to the receiver vector whenever Data Set
Change (bit 15) becomes set.
DSITEN is a program read/write bit and is cleared by Device
Reset or Bus INIT.

Receiver Enable
(RXENA)

This bit controls the operation of the receive section of the USYNRT.
When this bit is set, the receive section of the USYNRT is enabled. When it is reset the receive section is disabled.
In addition to disabling the receive section of the USYNRT, resetting bit 4 reinitializes all but two of the USYNRT receive
registers. The two registers not reinitialized are the character
length selection buffer and the parameter control register.

Local Loop back
(LL)

Asserting this bit causes the modem connected to the DPVll to
establish a data loopback test condition.
Clearing this bit restores normal modem operation.
Local Loopback is program read/write and is cleared by Device
Reset or Bus request to Send is program read/write and is
-Cleared -by Device~Reset'-or Bus INIT.

Request to Send
(RTS)

Setting this bit asserts the Request to Send signal at the modem
interface.
Request to Send is program read/write and is cleared by Device
Reset or Bus INIT.

Terminal Ready (TR)
(Data Terminal
Ready)

When set, this bit asserts the Terminal Ready signal to the
modem interface.
For auto dial and manual call origination, it maintains the established call. For auto answer, it allows handshaking in response to
a Ring signal.

3-7

Table 3-2 Receive Control and Status Register (RXCSR) Bit Assignments (Cont)
Bit

Name

Description

Select Frequency
or Remote
Loopback (SF jRL)

This bit can be wire-wrap jumpered to function as either select
frequency or remote loopback. When jumpered as select frequency (W3 to W4), setting this bit selects the modem's higher
frequency band for transmission to the line and the lower frequency band for reception from the line. The clear condition selects the lower frequency for transmission and the higher frequency for reception.
When jumpered for remote loopback (W5 to W3), this bit, when
asserted, causes the modem connected to the DPVll to signal
when a remote loopback test condition has been established in
the remote modem.
SF /RL is program read/write and is cleared by Device Reset or
Bus INIT.

; :
15

ERR

ASSEMB~ED

IREC

CHK

BIT COUNT

!OVRUN

ABORT REOM

8
RSOM

MK-1326

Figure 3-3

Receive Data and Status Register (RDSR) Format

Table 3-3 Receive Data and Status R~gister (RDSR) Bit Assignments
Bit

Name

Description

Error Check
(ERR CHK)

This bit when set, indicates a possible error. It is used in conjunction with the error detection selection bits of the parameter
control sync/address register (bits 8-10) to indicate either an
error or an all zeros state of the CRC register.
With bit-oriented protocols, ERR CHK indicates that a CRC
error has occurred. It is set when the Receive End of Message
bit (RDSR bit 9) is set.
With character-oriented protocols ERR CHK is asserted with
each data character if all zeros are in the CRC register. The
processor must then determine if this indicates an error-free

3-8

Table 3-3
Bit

Receive Data and Status Register (RDSR) Bit Assignments (Cont)

Name

Description
message or not. If VRC parity is selected, this bit is set for every
character which has a parity error.
ERR CHK is cleared by reading the RDSR, clearing RXENA
(RXCSR bit 4), Device Reset or Bus INIT.

14-12

Assembled Bit
Count (ABC)

Used only with bit-oriented protocols, these bits represent the
number of valid bits in the last character of a message. They are
all zeros unless the message ends on an unstated boundary. The
bits are encoded to represent valid bits as shown below.
14

Number of Valid Bits

0
0
0
0

0
0

1
1

1
1
1
1

0
0

1
1

All bits are valid
One valid bit
Two valid bits
Three valid bits
Four valid bits
Five valid bits
Six valid bits
Seven valid bits

1
1
1
1

These bits are presented simultaneously with the last bits of
data and are cleared by reading the RDSR or by resetting
RXENA (bit 4 of RXCSR).
11

Receiver Overrun
(RCV OVRUN)

This bit is used to indicate that an overrun situation has occurred. Overrun exists when the data buffer (bits 0-7 of RDSR)
has not been serviced within one character time.
As a general rule, the overrun is indicated when the last bit of
the current character has been received into the shift register of
the USYNRT and the data buffer is not yet available for a new
character.
Two factors exist which modify this general rule and apply only
to bit-oriented protocols.
The first factor is the number of bits inserted into the data
stream for transparency. For each bit inserted during the formatting of the current character, the controller's maximum response time is increased by one clock cycle.
The second factor is the result of termination of the current
message. When this occurs, the data of the terminated message
which is within the USYNRT is not overrunable. If an attempt
is made to displace this data by the reception of a subsequent
message, the data of the subsequent message is lost until the
data of the prior message has been released.

3-9

Table 3-3

Receive Data and Status Register (RDSR) Bit Assignments (Cont)

Bit

Name

Description

Receiver Abort or
Go Ahead (RABORT)

This bit is used only with bit-oriented protocols and indicates
that either an abort character or a go-ahead character has been
received. This is determined by the Loop Mode bit (PCSAR bit
13). If the Loop Mode bit is clear, RABORT indicates reception
of an abort character. If the Loop Mode bit is set, RABORT
indicates a go-ahead character has been received.
The setting of RABORT causes Receiver Status Ready (bit 10
of RXCSR) to be set.
RABORT is reset when the RDSR is read or when Receiver Enable (bit 4 of RXCSR) is reset.
The abort character is defined to be seven or more contiguous
one bits appearing in the data stream. Reception of this bit pattern when Loop Mode is clear causes the receive section of the
USYNRT to stop receiving and set RSTARY (bit 10 of
RXCSR). The abort character indicates abnormal termination
of the current message.
The go-ahead character is defined as a zero bit followed by seven consecutive one bits. This character is recognized as a normal
terminating control character when the Loop Mode bit is set. If
Loop Mode is cleared this character is interpreted as an abort
character.

Receiver End of
Message (REOM)

This bit is used only with bit-oriented protocols and is asserted if
Receiver Active (bit 11 of RXCSR) is set and a message is terminated either normally or abnormally. When REOM becomes
set, it sets RSTARY (bit 10 of RXCSR).
REOM is cleared when RDSR is read or when Receive Enable
(bit 4 of RXCSR) is reset.

7-0

Receiver Start of
Message (RSOM)

Receive Data
Buffer

Used only with bit-oriented protocols. This bit is presented to
the processor along with the first data character of a message
and is synchronized to the last received flag character. Setting
of RSOM does not set RSTARY (RXCSR bit 10).
RSOM is cleared by Device Reset, Bus IN IT, resetting Receiver Enable (RXCSR bit 4), or the next transfer into the Receive Data buffer (low byte of RDSR).
The low byte of the RDSR is the Receive Data buffer. The serial data input to the USYNRT is assembled and transferred to
the low byte of the RDSR for presentation to the processor.
When the RDSR receives data, Receive Data Ready (bit 7 of
RXCSR) becomes set to indicate that the RDSR has data to be
picked up. If this data is not read within one character time, a
data overrun occurs.
The characters in the Receive Data buffer are right-justified
with bit 0 being the least significant bit.
3-10

APA

PROT STRIP
SEL SYNC

SEC
ADR
MDE

I
IDLE

ERR DET SEL

I
MK-1330

Figure 3-4

Table 3-4

Parameter Control Sync/Address Register (PCSAR) Format

Parameter Control Sync/Address Register (PCSAR) Bit Assignments

Bit

Name

Description

All Parties
Addressed (APA)

This bit is set when automatic recognition of the All Parties Addressed character is desired. The All Parties Addressed character is eight bits of ones with necessary bit stuffing so as not to be
confused with the abort character.
Recognition of this character is done in the same way as the secondary station address (see bit 12 of this register) except that
the broadcast address is essentially hardwired within the receive
data path. The logic inspects the address character of each
frame for the broadcast address. When the broadcast address is
recognized, the USYNRT makes it available and sets Receiver
Start of Message (bit 8 of RDSR).
If the broadcast address is not recognized, one of two possible
actions occurs.
1. If the Secondary Address Select mode bit (bit 12) is set, a
test of the secondary station address is made.
2. If bit 12 is not set or the secondary station address is not
recognized, the receive section of the USYNRT renews its
search for synchronizing control characters.

Protocol Select
(PROT SEL)

This bit is used to select between character- and byte count-oriented or bit-oriented protocols. It is set for character- and byte
count-oriented protocols and reset for bit-oriented protocols.

Strip Sync or
Loop Mode
(STRIP SYNC)

This bit serves the following two functions.
1. Strip Sync (character-oriented protocols) - In character-oriented protocols, all sync characters after the initial synchronization are deleted from the message and not included in the
CRe computation if this bit is set. If it is cleared, all sync characters remain in the message and are included in the eRC computation.
3-11

Table 3-4
Bit

Parameter Control Sync/Address Register (PCSAR) Bit Assignments (Cont)

Name

Description

2. Loop Mode (bit-oriented protocols) - With bit-oriented protocols, this bit is used to control the method of termination. If it
is set, either a flag or go-ahead character can cause a normal
termination of a message. If it is cleared, only a flag character
can cause a normal termination.
12

Secondary
Address Mode
(SEC ADR MDE)

This bit is used with bit-oriented protocols when automatic recognition of the secondary station address is desired. If it is set,
the station address of the incoming message is compared with
the address stored in the low byte of this register. Only messages
prefixed with the correct secondary address are presented to the
processor. If the addresses do not compare, the receive section
of the USYNRT goes back to searching for flag or go-ahead
characters.
When SEC ADR MDE is cleared, the receive section of the
USYNRT recognizes all incoming messages.

Idle Mode Select
(IDLE)

This bit is used with both bit- and character-oriented protocols.
With bit-oriented protocols, IDLE is used to select the type of
control character issued when either Transmit Abort (bit 10 of
TDSR) is set or a data underrun error occurs. If IDLE is set,
flag characters are issued. If IDLE is clear, abort characters are
issued.
With character-oriented protocols, IDLE is used to control the
method in which initial sync characters are transmitted and the
action of the transmit section of the USYNRT when an underrun error occurs. IDLE is cleared to cause sync characters from
the low byte of PCSAR to be transmitted. When IDLE is set,
the transmit data output is held asserted during an underrun error and at the end of a message.

10--8

Error Detection
Selection
(ERR DEL SEL)

These bits are used to determine the type of error detection used
on received and transmitted messages. In bit-oriented protocols,
the selection is independent of character length. In characterand byte count-oriented protocols, CRC error detection is usable only with 8-bit character lengths. The maximum character
length for VRC is seven. The bits are encoded as follows.

CRC Polynomial

000

x16+x12+x5+ 1 (CRC CCITT) (Both CRC
data registers in the transmit and receive sections are set to all ones prior to the computation.)

X16+X12+x5+ 1 (CRC CCITT) (Both CRC
data registers set to all zeros.)

3-12

Table 3-4
Bit

7-0

Parameter Control Sync/Address Register (PCSAR) Bit Assignments (Cont)
Description

Name

Sync Character
or Secondary
Address

Not used

x16+x15+x2+ 1 (CRC 16) (Both CRC registers set to all zeros.)

Odd VRC Parity (A parity bit is attached to
each transmitted character.) Should be used
only in character-oriented protocols.

Even VRC parity (Resembles odd VRC except that an even number of bits are generated.)

Not used.

All error detection is inhibited.

The low byte of PCSAR is used as either the sync character for
character-oriented protocols or as the secondary station address
for bit-oriented protocols.
The bits are right-justified with the least significant bit being bit

EXTERNAL TO THE USYNRT

--------------~A-----------6
5
4
3
2
TX
INT
EN

RSVD

SQ/TM TXENA

MM
SEL

_____

TB
TXACT RESET
EMTY

INTERNAL TO THE USYNRT

(

__----------------A~--------------__
15

8 "

TRANSMITTER'
RECEIVER
EXADD EXCON
CHARACTER LENGTH
CHAR~CTER LfNGTH
I

MK-1325

Figure 3-5

Parameter Control and Character Length Register (PCSCR) Format
3-13

Table 3-5

Parameter Control and Character Length Register (PCSCR) Bit Assignments

Bit

Name

Description

15-13

Transmitter
Character Length

These bits can be read or written and are used to determine the
length of the characters to be transmitted.
They are encoded to set up character lengths as follows.
15

Character Length

000

Eight bits per character

111

Seven bits per character

110

Six bits per character

101

Five bits per character (bit-oriented protocol
only)

100

Four bits per character (bit-oriented protocol
only)

Three bits per character (bit-oriented protocol
only)

Two bits per character (bit-oriented protocol
only)

001

One bit per character (bit-oriented protocol
only)

These bits can be changed while the transmitter is active, in
which case the new character length is assumed at the completion of the current character. This field is set to a character
length of eight by Device Reset or Bus INIT. When VRC error
detection is selected, the default character length is eight bits
plus parity.
12

Extended Address
Field (EXADD)

This bit is used with bit-oriented protocols and affects the address portion of a message in receiver operations. When it is set,
each address byte is tested for a one in the least significant bit
position. If the least significant bit is zero, the next character is
an extension of the address field. If the least significant bit is
one, the current character terminates the address field and the
next character is a control character.
EXADD is not used with Secondary Address Mode (bit 12 of
PCSAR).
EXADD is read/write and is reset by Device Reset or Bus
INIT.

Extended Control
Field (EXCON)

This bit is used with bit-oriented protocols and affects the control character of a message in receiver operations. When EX3-14

Table 3-5
Bit

Parameter Control and Character Length Register (PCSCR) Bit Assignments (Cont)

Name

Description
CON is set it extends the control field from one 8-bit byte to
two 8-bit bytes.
EXCON is not used with Secondary Address Mode (bit 12 of
PCSAR)
EXCON is read/write and is reset by Device Reset or Bus
INIT.

10-8

Receiver
Character Length

These bits are used to determine the length of the characters to
be received.
They are encoded to set up character lengths as follows.
10

Character Length

Eight bits per character

Seven bits per character

Six bits per character

Five bits per character

Four bits per character (bit-oriented protocols
only)

Three bits per character (bit-oriented protocols only)

Two bits per character (bit-oriented protocols
only)

One bit per character (bit-oriented protocols
only)

Reserved

Not used by the DPVll

Transmit Interrupt
Enable (TXINTEN)

When set, this bit allows a transmitter interrupt request to be
made to the transmitter vector when Transmit Buffer Empty
(TBEMTY) is asserted. Transmit Interrupt Enable (TXIN. TEN) is read/write and is cleared by Device Reset or Bus
INIT.

Signal Quality or
Test Mode (SQ/TM)

This bit can be wire-wrap jumpered to function as either Signal
Quality or Test Mode.
When jumpered for signal quality (W5 to W6), this bit reflects
the state of the signal quality line from the modem. When asserted, it indicates that there is a low probability of errors in the
received data. When clear it indicates that there is a high probability of errors in the received data.
3-15

Table 3-5
Bit

Parameter Control and Character Length Register (PCSCR) Bit Assignments (Cont)

Name

Description
Whenjumpered for the test mode (W6 to W7), this bit indicates
that the modem has been placed in a test condition when asserted. The modem test condition could be established by asserting Local Loopback (bit 3 of RXCSR), Remote Loopback (bit 0
of RXCSR) or other means external to the DPVll.
When SQ/TM is clear, it indicates that the modem is not in test
mode and is available for normal operation.
SQ/TM is program read-only and cannot be cleared by software.

Transmitter
Enable (TXENA)

This bit must be set to initiate the transmission of data or control information. When this bit is cleared, the transmitter will
revert back to the mark state once all indicated sequences have
been completed. TXENA should be cleared after the last data
character has been loaded into the transmit data and status register (TDSR). Transmit End of Message (bit 9 of TDSR) should
be asserted when TXENA is reset (if it is to be asserted at all)
and remain asserted until the transmitter enters the idle mode.
TXENA is connected directly to USYNRT pin 37. It is a
read/write bit and is reset by Device Reset or Bus INIT.

Maintenance Mode
Select (MM SEL)

When this bit is asserted, it causes the USYNRT's serial output
to be internally connected to the USYNRT's serial input. The
serial send data output line from the interface is asserted and
the receive data serial input is disabled. Send timing and receive
timing to the USYNRT are disabled and replaced with a clock
signal generated on the interface. The clock rate is either
49.152K b/s or 1.9661K b/s depending on the position of a
jumper on the interface board.
Maintenance mode allows diagnostics to run in loop back without disconnecting the modem cable.
MM SEL is a read/write bit and is cleared by Device Reset or
Bus INIT. When it is cleared, the interface is set for normal operation.

Transmitter Buffer
Empty (TBEMTY)

This bit is asserted when the transmit data and status register
(TDSR) is available for new data or control information. It is
also set after a Device Reset or Bus INIT.
The TDSR should be loaded only in response to TBEMTY
being set. When the TDSR is written into, TBEMTY is cleared.
If TBEMTY becomes set while Transmit Interrupt Enable (bit
6 of PCSCR) is set, a transmit interrupt request results.
TBEMTY reflects the state of USYNRT pin 35.

3-16

Table 3-5 Parameter Control and Character Length Register (PCSCR) Bit Assignments (Cont)
Bit

Name

Description

Transmitter
Active (TXACT)

This bit indicates the state of the transmit. section of the USYNRT. It becomes set when the first character of data or control information is transmitted.
TXACT is cleared when the transmitter has nothing to send or
when Device Reset or Bus IN IT is issued.
TXACT reflects the state of USYNRT pin 34.

When a one is written to this bit all components of the interface
are initialized. It performs the same function as Bus INIT with
respect to this interface. Modem Status (Data Mode, Clear to
Send, Receiver Ready, Incoming Call, Signal Quality or Test
Mode) is not affected. RESET is write-only; it cannot be read
by software.

Device Reset
(RESET)

: :
9

MK-1331

Figure 3-6 Transmit Data and Status Register (TDSR) Format

Table 3-6 Transmit Data and Status Register (TDSR) Bit Assignments
Bit

Name

Description

Transmitter
Error (TERR)

This is a read-only bit which becomes asserted when the Transmitter Buffer Empty (TBEMTY) indication has not been serviced for more than one character time.
When TERR occurs in bit-oriented protocols, the transmit section of the USYNRT generates an abort or flag character based
on the state of the IDLE bit (PCSAR bit 11). If IDLE is set, a
flag character is sent. If it is reset, an abort character is sent.
When TERR occurs in character-oriented protocols, the state of
the IDLE bit again determines the result. If IDLE is set, the
transmit serial output is held in the MARK condition. If it is
cleared, a sync character is transmitted.

3-17

Table 3-6 Transmit Data and Status Register (TDSR) Bit Assignments (Cont)
Bit

Name

Description
TERR is cleared when TSOM (TDSR bit 8) becomes set or by
Device Reset or Bus INIT.
Clearing Transmitter Enable (PCSCR bit 4) does not clear
TERR and TERR is not set with Transmit End of Message.

14-12

Reserved

Not used by the DPVll

Transmit Go
Ahead (TGA)

This bit, when asserted, modifies the bit pattern of the control
character initiated by either Transmit Start of Message
(TSOM) or Transmit End of Message (TEOM). TSOM or
TEOM normally causes a flag character to be sent. If TGA is
set, a go-ahead character is sent in place of the flag character.
TGA is only used with bit-oriented protocols.

Transmit
Abort (TXABORT)

This bit is used only with bit-oriented protocols to abnormally
terminate a message or to transmit filler information used to establish data link timing.
When TXABORT is asserted, the transmitter automatically
transmits either flag or abort characters depending on the state
of the IDLE mode bit. If IDLE is cleared, abort characters are
sent. If IDLE is set, flag characters are sent.

Transmit End of
Message (TEOM)

This control bit is used to normally terminate a message in bitoriented protocol. It also terminates a message in character-oriented protocols when CRC error detection is used. As a secondary function, it is used in conjunction with the Transmit Start of
Message (TSOM) bit to transmit a SPACE SEQUENCE. Refer to the TSOM bit description (bit 8 of this register) for information regarding this sequence.
With bit-oriented protocols, asserting this bit causes the CRC
information to be transmitted, if CRC is enabled, followed by
flag or go-ahead characters depending on the state of the Transmit Go Ahead (TGA) bit. See bit 11 of this register.
With character-oriented protocols, asserting this bit causes
CRC information, if CRC is enabled, to be transmitted followed
by either sync characters or a MARK condition depending on
the state of the IDLE bit. If IDLE is cleared, sync characters
are transmitted.
The character following the CRC information is repeated until
the transmitter is disabled or the TEOM bit is cleared.
A subsequent message may be initiated while the transmit section of the USYNRT is active. This is accomplished by clearing
the TEOM bit and supplying nev~T message data without setting

-----

3-18

Table 3-6 Transmit Data and Status Register (TDSR) Bit Assignments (Cont)
Bit

Name

Description
the Transmit Start Of Message bit. However, the CRC cllracter for the prior message must have completed transmission.

Transmit Start
of Message
(TSOM)

This bit is used with either bit- or character-oriented protocols.
As long as it remains asserted, flag characters (bit-oriented protocols) or sync characters (charaeter-oriented protocols) are
transmitted.
With bit-oriented protocols, a space sequence (byte mode only)
of 16 zero bits can be transmitted by asserting TSOM and
TEOM simultaneously provided the transmitter is in the idle
state and Transmit £nable is cleared. This should not be done
during the transfer of data, and must only be done in byte mode.
NOTE
When using the special space sequence function, all registers internal to the USYNRT must be written in byte mode.
Normally at the completion of each sync, flag, go-ahead or
Abort character, the TBEMTY indication is asserted. This allows the software to count the number of transmitt~d characters. In certain applications, the software may elect to ignore the
service of the Transmitter Buffer Empty (TBEMTY) indication.
Normally during data transfers, this would cause a transmit
data late error. The TSOM bit asserted suppresses this error
and provides the necessary synchronization to automatically
transmit another flag, go-ahead or sync character.

7-0

Transmit Data
Buffer

Data from the processor to be transmitted on the serial output
line is loaded into this byte of the TDSR when Transmitter Buffer Empty (TBEMTY) is asserted. If the transmitter buffer is
not loaded within one character time, an underrun error occurs.
The characters are right-justified, with bit 0 being the least significant bit.

3.4 DATA TRANSFERS
Paragraphs 3.4.1 and 3.4.2 discuss receive and transmit data transfers as they relate to the system
software.
3.4.1 Receive Data
Serial data to be presented to the DPVll from the modem enters the receiver circuit and is presented
to the USYNRT. Recognition by the USYNRT of a control character initiates the transfer. When a
transfer has been initiated, a character is assembled by the USYNRT and then placed in the low byte
of the receive data and status register (RDSR) when it is available. If the RDSR is not available, the
transfer is delayed until the previous character has been serviced. This must take place before the next
character is fully assembled or an overrun error exists. Refer to the description of bit 11 in Table 3-3
for more details on Receiver Overrun.

3-19

Servicing of the RDSR is the responsibility of the system software in response to the Receive Data
Ready (RDATRY) signal. This signal is asserted when a character has been transferred to the RDSR.
The setting of RDATRY would also cause a receive interrupt request if Receive Interrupt Enable
(RXITEN) is set. The software's response to RDATRY is to read the contents of the RDSR. At the
completion of this operation, the new information is loaded into the RDSR and RDATRY is reasserted. This operation continues until terminated by some control character. The upper byte of the
RDSR contains status and error indications which the software can also read.
The DPVll will handle data in bit-, byte count- or character-oriented protocols.
With bit-oriented protocol, only flag characters are used to initiate the transfer of a message. Information inserted into the data stream for transparency or control is deleted before it is presented to the
RDSR. This means that only data characters are available to the software. The first two characters of
every message or frame are defined to be 8-bit characters and the USYNRT will handle them as such
regardless of the programmed character length. All subsequent data is formatted in the selected character length. When CRC error detection is selected, the received CRC check characters are not presented
to the software, but the error indication will be presented if an error has been detected.
If the secondary address mode is implemented, the first received data character must be the selected
address. If this is not the case, the USYNRT will renew its search for flag or go-ahead characters.
Refer to the description of bit 12 of the PCSAR in Table 3-4.
With byte count- or character-oriented protocols, two consecutive sync characters are required to synchronize the transfer of data. The sync characters used in the message must be the same as the sync
character loaded by the software into the low byte of the parameter control sync/address register
(PCSAR). If leading sync characters subsequent to the initial two syncs are to be deleted from the
data stream, the Strip Sync bit (bit 13) must also be set in the upper byte of the PCSAR. The character length of the data to be received should also be set in bits 8, 9, and 10 of the parameter control and
character length register (PCSCR). Sync characters and data must have the same character length
and only characters of the selected length will be presented to the receive buffer. Sync characters
following the initial two will be presented to the buffer and included in the CRC computation unless
the Strip Sync bit is set. If vertical redundancy check (VRC) parity checking is selected, the parity bit
itself is deleted from the character before it is presented to the buffer.

3.4.2 Transmit Data
System software loads information to be transmitted to the modem into the transmit data and status
register (TDSR). This does not ordinarily include error detection or control character information.
Loading of the TDSR occurs in response to the Transmitter Buffer Empty (TBEMTY) signal from the
USYNRT. The character length of information to be transmitted is established by the software when
it loads the transmit character length register (bits 13, 14, and 15 of the PCSCR). The default length
of eight is assigned when the transmit character length register equals zero. The length of characters
presented to the TDSR should not exceed the assigned character length. When the information in the
TDSR is transmitted, the TBEMTY signal is again asserted to request another character. The setting
of TBEMTY also causes a transmit interrupt request if Transmit Interrupt Enable is set.
Byte count- or character-oriented protocols require the transmission of synchronizing information normally referred to as sync characters. The sync characters can be transmitted when Transmit Start of
Message (TDSR bit 8) is set. This happens in one of two ways depending on the state of the IDLE bit
(PCSAR bit 11). When the IDLE bit is cleared, the sync character is taken directly from the common
sync register (PCSAR bits 7-0). The sync register would have been previously loaded by the software.
If the IDLE bit is set, the sync character must be loaded into the TDSR by the software when it is to
be transmitted. If multiple sync characters are to be transmitted, the TDSR must only be loaded with
the first one of the sequence. This character will be transmitted until data information is loaded into
the TDSR. The TBE~1TY signal is asserted at the end of each sync character but the TSOl'vl signal
aHows it to be ignored without causing a data iate error.

3-20

With bit-oriented protocols, the USYNRT automatically generates control characters as initiated by
the software and inserts necessary information into the data stream to maintain transparency.
Typical programming examples in bit- and byte count-oriented protocols appear in Appendix D.
3.5 INTERRUPT VECfORS
The DPY11 generates two vector addresses, one for receive data and modem control and the other for
transmit data.
The receive and modem control interrupt has priority over the transmit interrupt and is enabled by
setting bit 6 (RXITEN) of the receiver control and status register (RXCSR).
If bit 6 of the RXCSR is set, a receiver interrupt may occur when anyone of the following signals is
asserted.
•
•
•

Receive Data Ready (RDATRY)
Receive Status Ready (RSTARY)
Data Set Change (DAT SET CH)

The signal DAT SET CH only causes an interrupt if bit 5 (DSITEN) of the RXCSR is also set.
It is possible that a data set change interrupt could be pending while a receiver interrupt is being
serviced, or the opposite could be true. In either case, the hardware ensures that both interrupt
requests are recognized.

NOTE
The modem status change circuit interprets any
pulse of two microseconds or greater duration as a
data set change. This ensures that all legitimate
transitions of modem status will be detected. However, on a poor line, noise may be interpreted as a
data set change. Software written for the DPVll
must account for this possibility.
A transmitter interrupt request occurs if Transmit Interrupt Enable (TXINTEN) is set when Transmit
Buffer Empty (TBEMTY) becomes asserted.

3-21

CHAPTER 4
TECHNICAL DESCRIPTION
4.1 INTRODUCTION
This chapter provides a 2-level discussion of the DPVl1. Paragraph 4.2 includes a description of the
DPVll logic in functional groups at the block diagram level. At this level, a general operational overview is also discussed. The second level of discussion is the detailed description, which covers the complete DPVll logic at the circuit schematic level, as shown in the DPVll print set.
4.2 FUNCTIONAL DESCRIPTION
4.2.1 Logic Description
For discussion purposes, the DPVll logic is divided into the ten sections shown in Figure 4-1. The
sections are described in Paragraphs 4.2.1.1 through 4.2.1.10.
4.2.1.1 Bus Transceivers - The interface for data, and address on the LSI-II bus consists of four bus
transceiver chips (DC005). These function as bidirectional buffers between the LSI-II bus and the
DPVll Logic. These transceivers provide isolation, address comparison, and vector generation.
4.2.1.2 Read/Write Control- The read/write control logic consists of a DC004 protocol chip and its
associated logic. It provides the control signals for accessing registers and strobing data. It controls
reading from and writing into registers in both word and byte mode, and provides the deskew delays for
these operations. When data has been placed on or picked up from the LSI-II bus or when vector
information has been placed on the LSI-II bus, the read/write control logic notifies the processor by
asserting BRPLY.
4.2.1.3 USYNRT and Bidirectional Buffer - The USYNRT provides a large portion of the functionality of the DPVll. The USYNRT is installed in a socket for ease of replacement. It provides complete serialization, deserialization and buffering of data between the modem and the LSI-II bus. The
USYNRT also provides logic support, via program parameter registers, for basic protocol handling and
error detection.
The tri-state bidirectional buffer provides the fan-out drive to accommodate the number of circuits the
USYNRT feeds.
4.2.1.4 Receive Control And Status Register (RXCSR) - This register contains most of the control
and status information pertaining to receiver operation, including the status of the lines to and from the
data set. The receive and data set interrupt enable bits are also contained in this register, but the receive interrupt enable is actually generated by the interrupt logic. The high byte of the RXCSR is
read-only and the low byte is read/write. RXCSR is both word- and byte-addressable.
4.2.1.5 Transmit Control And Status Register - This register is the low byte of the parameter control
and character length register (PCSCR). (The high byte is internal to the USYNRT). It contains most
of the control and status information pertaining to transmit operations. The maintenance mode bit is
also a part of this register. The register is read/write and can be accessed separately as the low byte of
the PCSCR or in word mode when the entire PCSCR is accessed.

4-1

. - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1 _ _ _ _ _ _

-"
)

RECEIVE
STATUS

~----------Vy

...

~-----ify/

REG

,-----------,

'------'I~

t--

~ DIRECTIONALl/'--'\
~TRI STATE

~USYNRT

f.--

BUFFER

EIA
LEVEL
CONVERT

40 PIN
BERG

"'-

r
CHARGE
PUMP

TO
MODEM

(f)

:::>

:: K I
(f)

...J

I
I
I
I
I
I
I
I
I

V"-

...
BUS
; TRANSCEIVERh
y
DC005

'-----------v
../

XMIT
STATUS
REG

f--

INTERRUPT

1---"1'---" LOG I C

I
I
I
I

.)0.

DC003

DATA
SET
CHANGE
LOGIC

READ
fWRITE
CONTROL
LOGIC
DC004

CLOCK

~------------------------------~

~---------------------------------------Figure 4-1

D PV 11 Block Diagram

MK-1334

4.2.1.6 Interrupt Logic - Most of the logic for interrupts is contained in a single DC003 interrupt
chip. The chip contains two interrupt channels: one for receive and one for transmit interrupts. The
circuit generates a receive interrupt when the Receiver Interrupt Enable bit (RXITEN) is set and one
of the following signals becomes asserted.
Receive Status Ready (RSTARY)
Receive Data Ready (RDATRY)
Modem Control Interrupt Request (MCINT)
MCINT requires that DSITEN (RXCSR bit 5) also be set.
If the Transmit Interrupt Enable bit (PCSCR bit 6) is set, a transmit interrupt is generated when the
Transmit Buffer Empty signal (TBEMTY) is asserted.
Receive interrupts have priority over transmit interrupts.
4.2.1.7 Data Set Change Logic - This logic is used to determine if the modem had a change in status.
Jumpers can be removed or installed to allow any or all of the following signals to set the Data Set
Change bit (RXCSR bit 15).
RS-232-C

RS-449

Clear to Send (CTS)

Carrier Detect (CD)

Receiver Ready (RR)

Data Set Ready (DSR)

Data Mode (DM)

Ring Indicator (RI)

Incoming Call (IC)

If the Data Set Interrupt Enable bit and Receiver Interrupt Enable (RXCSR bits 5 and 6) are both
set, Data Set Change causes the interrupt logic to generate an interrupt request.
4.2.1.8 Clock Circuit - The clock circuit consists of a 19.6608 MHz off-the-shelf oscillator and two
74LS390 dividers to provide the clock signals for the DPVl1.
4.2.1.9 EIA Level Converters - These circuits contain drivers and receivers necessary for converting
from TTL levels to EIA levels and from EIA levels to TTL levels. There are drivers and receivers to
accommodate both RS-422-A (RS-449 compatible: limited to clock and data) and RS-423-A (RS-232C compatible) electrical standards. Selection of RS-422-A or RS-423-A interface standard is provided
by wire-wrap jumpers.
4.2.1.10 Charge Pump - This circuit converts the + 12 volts to a negative voltage to power the RS423-A drivers.
4.2.2 General Operational Overview
This discussion describes the relationships between the different sections of the block diagram from a
simplified operational viewpoint. It is assumed for the purpose of this discussion that the DPVll will
be operated with the interrupts enabled. A simplified diagram which emphasizes the functions of the
USYNRT (Figure 4-2) is referenced for both the receive and transmit operations. Bit-oriented protocol
(BOP) and byte count-or character-oriented protocols (BCP) are not discussed in detail here.
4.2.2.1 Receive Operation - Serial data from the modem enters the EIA receiver where it is converted from EIA to TTL level. This TIL data is then presented directly to the receive serial input of

4-3

BIRO

- - - ------ - - - - - - - - - - MAsTER-R~~ -- - - - - - - - - - -- - - ---2-:-':~ ~

-------,

USYNRT
TB EMTY
TIMING

RXENA
RDATRY
EIA
RCVRS

~----------------------~OTXENA

TIMING AND
CONTROL

RXACT

- - - - - - - - - - - - - - - 0 TXACT

_FlSTA~ _________ _

TX SERIAL DATA OUT

S~RIAL

DATA

~---~------,

SYNC AND
ADDRESS
DETECT

MAINT
SEL

rso
FLAG

----1--

TX SERIAL
OUTPUT

DETECT

EIA
DRIVERS

+ 12VO--+ 5V 0---.
GND 0---.

CRe ~HROR

GA
FLG
ABRT

~
10 TIMING AND CONTROL

BD14

BD13

BD12

I I I 1

BOll

BOlO

BD09

BOOB

Moe," D'
AO

A'l

COn

DPENA

BYTE OP DB07

DB06

DB05

DB04

DB03

DB02

DBOI

DBOO

~---------------------BIDIRECTIONAL
PARALLEL
DATA

MK-1337

Figure 4-2

Simplified Functional Diagram

the USYNRT. At the same time the EIA receiver converts the receive timing signal from the modem
to TTL level and presents it to the USYNRT. The USYNRT uses the timing signal to control the
assembling of the incoming data characters. As the information enters the USYNRT, sync~detect and
flag-detect circuits check for FLAG (BOP) or SYNC (BCP) until there is a match. When a match
occurs, assembling of data characters begins. Error circuits check for errors while the data is being
assembled. When a character is assembled in the receive data shift register, it is then transferred to the
receive data buffer, and the USYNRT timing and control logic generates the signal receive data ready
(RDATRY). Interrupt logic uses this signal to produce an interrupt request to the processor. When the
processor responds to the interrupt request, the interrupt logic causes the bus transceiver circuits to
assert the associated vector and the interrupt sequence takes place.
The processor now retrieves the data from the receive data buffer which resets the interrupt condition.
To do this the processor asserts the address of the buffer and the necessary control signals on the bus.
The bus transceivers recognize the address and enable the read/write control logic. The read/write
control logic then generates the necessary control signals to select and read from the receive data buffer (low byte of RDSR). Data in the buffer is sent through the bidirectional tri-state buffer to the LSI·
11 bus transceivers where it is enabled onto the LSI-II bus and picked up by the processor. The USYNRT is double-buffered so that while the processor is picking up the character from the receive data
buffer, the receive data shift register is already assembling a second character. This process is repeated
until the entire message is received.
4.2.2.2 Transmit Operation - When the processor wishes to send data to the modem, it first places
the address of the transmit buffer (low byte of TDSR) and the necessary control signals on the LSI-II
bus.
The bus transceivers recognize the address and enable the read/write control logic which selects the
register. The processor then places the parallel data on the LSI-II bus and the read/write control logic
gates it through the bus transceivers and writes it into the transmit buffer. When a character is written
into the transmit data buffer, the USYNRT transfers it to its transmit shift register and asserts
TBEMTY. Once the character is in the shift register, the USYNRT begins to serialize and send it by
means of the serial output line to the EIA drivers. Here it is converted from TIL to EIA level and sent
to the modem.
TBEMTY causes the interrupt logic to generate an interrupt request to the processor. At the completion of the interrupt sequence, the processor repeats the process of addressing the transmit buffer
and sending another character. This operation continues until the entire message has been sent.
4.3 DETAILED DESCRIPTION
The circuit operation is described in Paragraphs 4.3.1 through 4.3.9.
4.3.1 Bus Transceivers
Data, address and control signals move between the LSI-II bus and the DPVII by means of a group of
bus transceivers. The bus transceivers are contained in four DeDD5 transceiver chips and perform the
following functions.
•
•
•

Address selection/ decode
Data transfers to and from the LSI-II bus
Vector generation

4.3.1.1 Address Selection - Each DPVII is assigned four consecutive addresses that are decoded to
generate control signals to enable five registers in the DPVIl. Four addresses are able to access five
registers because two of the registers (RDSR and PCSAR) share the same address. RDSR is a readonly register and PCSAR is a write-only register. Refer to Chapter 2 for address assignments.

4-5

When the software communicates with the DPVll, it does so by placing the address of the register it
wishes to access and the necessary control signals on the LSI-II bus. The DPVll checks the address to
see if it is within the range assigned to it. If so, access to the register is allowed. Paragraphs 4.3.1.2
through 4.3.1.4 describe the decoding of the address.
4.3.1.2 Address Decode - Address decoding is accomplished in the DCOOS chips where a comparison
is made of the BDAL03 through BDAL12 lines wi~h the states selected by the address jumpers W29
through W39. (Refer to Chapter 2 for address selection and jumper connections). Each DCOOS chip
looks at three address lines and compares each of them against a corresponding jumper connection.
When each address line agrees with its jumper input, the DCOOS asserts pin 3 high. If all four DCOOS
chips have pin 3 asserted, the address on the bus is within the range assigned to this DPVll. When this
condition exists, the register decode circuit is enabled to allow access to the specific register being
addressed. Notice that BDALOO through BDAL02 are not used in the address compare. Line zero is
used in byte selection and lines one and two are used to select a particular register. Register selection
and byte operation are discussed in Paragraph 4.3.2.
4.3.1.3 Bus Data Transfers - Once the address has been accepted and access to the selected register
has been granted, data transfers can take place on the bus. The DCOOS chips handle this function too.
Consider first the operation in which the processor is sending data to a register in the DPVl1. In this
case, the DC005s would be placed in receive mode by a high on pin 4. This is a result of control signals
placed on the bus by the processor. In the receive mode, data on the BDALO through BDALlS lines is
passed through the Deoos and made available to the register on the DAG through DAI5 lines.
When the processor is requesting information from one of the DPVll registers, the DCOOSs are placed
in transmit mode by a high on pin S. In the transmit mode, data from the selected register is presented
to the DCOOSs on the DAO through DAIS lines. The DCOOSs then pass this data to the bus on the
BDALO through BDAL IS lines.
4.3.1.4 Vector Generation - A third function of the DCOOS chips is vector generation. This is accomplished by daisy-chain strapping W40 through W4S to W46 in the proper configuration for the vector
address desired. Refer to Chapter 2 for information on vector assignments and jumper connections.
W46 is high when the vector is to be sent to the processor. The signal VECTOR H is asserted by the
interrupt logic during an interrupt sequence. W 4S corresponds to BDAL3 and W 43 corresponds to
BDAL8.
4.3.2 Read/Write Control Logic
The read/write control logic contains circuits for controlling register decoding, USYNRT operations,
and BRPLY. A description of each follows.
4.3.2.1 Register Decode (Figure 4-3) - The selection of individual registers within the DPVll is accomplished by a DC004 protocol chip and its associated logic. This circuit is enabled by an address
match from the DCOOSs. When enabled, the DC004 decodes address lines 1 and 2 to produce one of
four select signals. These select lines, however, do not directly select the registers. Two registers share
the same address, one being a read-only and the other, a write-only register. One entire register and the
low byte of another are external to the USYNRT. For these reasons, additional gates are used with the
select lines to properly select the one register in five to be accessed. These gates use byte and write
signals to aid in the register selection. Table 4-1 shows the register selection based on the three loworder address bits.

NOTE
All registers can be accessed in either word or byte
mode. However, reading either byte of the RXCSR
resets certain status bits in both bytes.

4-6

Reading either byte of the RDSR resets data and
certain status bits in both bytes of this register as
well as bits 7 and 10 of the RXCSR.
NOTE
The address inputs to the DC004 are inverted,
thereby causing a reverse order on the select lines.
Pin 17 corresponds to select 0 and pin 14 corresponds to select 6. This applies also to the OUTLB
(pin 13) and OUTHB (pin 12).
4.3.2.2 USYNRT Control - Most of the control signals for the USYNRT are generated by the
DC004 and its associated logic. This paragraph describes the control signals and their functions.
ADRO, ADR1, and ADR2 are used to select a register within the USYNRT. They are encoded as
shown in Table 4-2. ADRO is used in conjunction with BYTE OP to select a byte.
WRITE USYNRT is used to control writing into or reading from registers within the USYNRT.
When it is asserted, a write operation is indicated. When it is not asserted, a read operation is indicated. WRITE USYNRT is generated by ORing the OUTLB and OUTHB signals from the DC004.
OUTLB and OUTHB are used to write data into the low byte, high byte or both bytes of a selected
register. They are generated by the DC004 in response to the bus signals BWTBT, BDOUT, and
BDALO. OUTLB and OUTHB do not directly control byte selection for the USYNRT but are used to
generate ADRO and BYTE OP.
BYTE OP is used to indicate to the USYNRT that a byte operation is to be performed on the selected
register. It is generated during a write operation when either OUTLB or OUTHB but not both are
asserted.
DPENA (Data Port Enabled) is used to enable the tri-state data bus of the USYNRT and supply the
necessary timing for transactions between the USYNRT and the external circuits. DPENA strobes the
data for write or read operations. It is generated from the register select signals and the output of pin 8
of the DC004 chip which results directly from BDIN or BDOUT. Deskew delay is accomplished by
using a 74LS164 serial to parallel shift register. Pin 8 of the DC004 is used as the serial input to the
shift register which is clocked by a 100 ns clock. Initially the serial input is high and the shift register
outputs are all high. 100 to 200 ns after the serial in goes low, DPENA becomes asserted to strobe the
USYNRT. DPENA remains asserted for at least 300 ns as determined by pin 10 of the shift register.
For read operations, DPENA will remain asserted until BDIN becomes not asserted. This is to ensure
that the data is on the bus when the processor strobes it. For write operations DPENA will be asserted
for 300 ns.
BRPLY (Bus Reply) indicates to the processor that the DPV11 has placed data on the bus or has
received data from the bus. It is generated from the same circuit as DPENA and is asserted 300 ns
after DPENA. BRPLY remains asserted until the processor responds by negating BDIN or BDOUT.
Figure 4-4 shows the timing for the generation of DPENA and BRPLY for a read operation. Figure 4-5
shows the timing for a write operation.
4.3.3 USYNRT, RXCSR, and PCSCR
Most of the registers used in the DPV11 are contained within the USYNRT. The receive control and
status register (RXCSR) and the low byte of the parameter control and character length register
(PCSCR) are external to the USYNRT. The USYNRT and the external registers are discussed in
Paragraphs 4.3.3.1 through 4.3.3.3.

4-7

v ' - - - - +Vcc

EN B H

19 I-----.J-------I D
ENB
LATCH

BSYNC L

ENB ,.---_

'------I

SYNC

BDAL2 H

02 r - - - - - - + - - l D
02
LATCH
DAL2
o ~-+---------~

BDALl H

&----t----i

DECODER

01
LATCH
DALl

=-Dr-----------S EL 0 -+---'--+----{~L....._ _

WRITE REG 0

L r - - - - - - - - - - READ REG 0

S EL 2 - + _ _ - + _ _ - {
WRITE
USYNRT

S EL 4 -+--+--------t-----l
ADR

SELECT USYNRT REGISTERS

- - - - - - - ADR 1
SEL6 --+--+-------~~

r - - - - - - - - - - - WRITE REG4
WR ITE --'---+-------~--(

Figure 4-3

4-8

Table 4-t

0
0
0
0

0
0

1
1

1
1
1
1

0
0

1
1

RXCSR (word or low byte)
RXCSR (high byte)
RDSR (read) or PCSAR (write)
RDSR or PCSAR (high byte)
PCSCR (word or low byte)
PCSCR (high byte)
TDSR (word or low byte)
TDSR (high byte)

1
1
1
1

Table 4-2 USYNRT Register Select
ADR2

ADRt

o
o

RDSR (read only)
TDSR
PCSAR (write only)
PCSCR (high byte)

1
1

B SYNC L
REGISTER
SELECT

BDIN L

E16-10

--------------~

E16-13

DPENA

BRPLY L

READ
MK-1333

Figure 4-4

Timing for Read Operation

4-9

B SYNC : - - ,
.

I L - - ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _
,

B DOUT L

E 16-10

E 16-13
DPENA
----------------44~-----300ns------~.~~-----------------------------

BRPLY L

WRITE
MK·1332

Figure 4-5

Timing for Write Operation

4.3.3.1 USYNRT - The universal synchronous receiver/transmitter (USYNRT) functions as a large
scale integration (LSI) subsystem for synchronous communications. The USYNRT provides the logic
support, via program parameter registers, for basic protocol handling and error detection. Protocol
handling by the USYNRT conforms to standards imposed by these protocols, but is slightly different
in each version of the USYNRT. The 5025 (2112517-00) is implemented in the DPVll. For more
details on the USYNRT, refer to Appendix B or to A-PS-2112517-0-0 Purchase Specification.
4.3.3.2 Receive Control and Status Register (RXCSR) - The RXCSR is described in detail in Chapter 3. It is a buffer and line driver consisting of two 74LS244 chips and one 74LS174 hex D flip-flop.
The low byte can be read or written into but the high byte can only be read. The write operation occurs
on the positive transition of WREGO. The register can be read when RREGO is asserted low.
4.3.3.3 Parameter Control and Character Length Register (PCSCR) - This register is described in
Chapter 3. Its upper byte is internal to the USYNRT and its low byte is external. Three bits (0, 3, and
4) of the low byte of this register are directly program-writable with bit zero being write-only. Bit 6 is
program writable but is a function of the interrupt circuit.
4.3.4 Interrupt Logic
Most of the logic for interrupts is contained in a single DC003 interrupt chip. The chip contains two
interrupt channels: one for receiver and modem control interrupts and one for transmitter interrupts.
The receive and modem control interrupt has the higher priority and may occur when receive interrupt
enable (RX INT ENA) is set and any of the following signals become asserted.
Receive Data Ready (RDATRY)
Receive Status Ready (RSTAR Y)
Data Set Change (DAT SET CH)
Notice that DAT SET CH requires that Me INT ENA (RXCSR bit 5) also be asserted,

4-10

When a register in the receive section (RXCSR or RDSR) is accessed; i.e., when servicing a receive
interrupt request, the receive interrupt request is disabled for 600 ns by the output on pin 5 of the
74LS74 flip-flop. This is done to ensure that any modem control interrupt request that might have
occurred while servicing the receive interrupt request, is recognized. When the flip-flop is reset by the
600 ns signal, a negative to positive transition is recognized on pin 17 of the DC003 if a modem control
interrupt request is present.
A transmitter interrupt is generated by the DC003 if the TBEMTY signal is asserted when transmitter
interrupt enable (bit 6 of PCSCR) is set.
Both the TX INT ENA and RX INT ENA bits are located physically in the DC003 interrupt chip
although they are functionally part of the PCSCR and RXCSR respectively.
The bus interrupt request (BIRQ) is asserted by the DC003 for either a receive or transmit interrupt
request. The processor responds to BIRQ by asserting BIAKI and BDIN. BIAKI is the interrupt acknowledge signal. It is passed down the priority chain until it reaches the section of the interrupt chip
that initiated the request.
When the interrupt logic receives both BDIN and BIAKI, it asserts the signal VECTOR. VECTOR
enables the assertion of the vector address by the DS005s. If the interrupt is a transmitter interrupt,
the RQSTB signal would assert vector address bit 2.
4.3.5 Data Set Change Circuit (Transition Detector)
The data set change circuit consists of a 74LS273 D-register, exclusive NOR gates and two flip-flops.
Setting of the Data Set Change bit (DAT SET CH) is determined by the configuration of jumpers
W24 through W28. Any or all of the following modem signals can set DAT SET CH if its associated
jumper is installed.
RS-232-C

RS-449

Clear to Send (CTS)

Carrier Detect (CD)

Receiver Ready (RR)

Data Set Ready (DSR)

Data Mode (DM)

Ring Indicator (RI)

Incoming Call (IC)

NOTE
The modem change circuit interprets any pulse of
two microseconds or greater duration as a modem
status change. This ensures that all legitimate
modem status changes will be detected. However, on
a poor line, noise may be interpreted as a modem
status change. Software written for the DPVll
must account for this possibility.
4.3.6 Clock Circuit
The clock circuit consists of an off-the-shelf 19.6608 MHz crystal oscillator, and two 74LS390
counters. The 19.6608 MHz signal is divided by the counter circuits to produce the following four
clock signals.
1.

LOCAL CLK (49.152 kHz) - Normally jumpered to NULL MODEM CLK (W18 and
W21) and used as the data clock.

4-11

DIAG CLK (1.9661 kHz) - Nonsymmetrical clock available for diagnostic purposes (not
recommended for local communications). It becomes the transmit clock when the DPVll is
placed in diagnostic mode. DIAG CLK can also be jumpered to LOCAL CLK for 50 kHz
operation but some of the tests must be omitted.

SR CLK (9.8304 MHz) - Used to clock the shift register to establish delays for DPENA
and BRPLY.

Charge PUMP CLK (491.52 kHz) - Used by the charge pump circuit and transition detector.

4.3.7 USYNRT Timing - USYNRT timing for the transmit and receive sections originates with the
modem and is gated through the AND-OR inverter to the USYNRT.
During normal receive data transfers, the 74LS51 gates receiver timing from the modem as receive
clock pulse (RCP) to the USYNRT. If the modem clock stops with the last valid data bit, Receiver
Ready becomes not asserted. The next positive transition of the NULL MODEM CLK causes 74LS74
pin 8 to go high, thus substituting NULL MODEM CLK for modem receive timing. In this way, the
USYNRT receives the necessary 16 clock pulses to complete its operation after the modem has
stopped sending.
During normal transmit data transfers, timing for the USYNRT is gated from the modem through the
74LS51 pin 6 to the USYNRT.
In maintenance mode, the signal MSEL disables the modem timing and enables the DIAG CLK as the
clock for the USYNRT.
4.3.8 EIA Receivers
26LS32 quad differential line receivers are used to accept signals and data from the modem. Jumpers
W12 through W17 are terminating resistors which may be connected for RS-422-A but must be disconnected for RS-423-A.
4.3.9 EIA I>rivers
Two types of drivers are used to send signals and data to the modem. 9638 drivers are used for RS-422A and 9636 drivers are used for RS-423-A.
4.3.10 Maintenance Mode
The USYNRT is placed in maintenance mode by setting Maintenance Mode Select (bit 3 of the
PCSCR). When this happens, the serial output of the transmit section is internally looped back as
serial input and the transmit serial output is held asserted. All clocking of both the receive and transmit sections is controlled by the transmitter clock input. This signal is derived from the 2 kHz clock as
determined by the 74LS51 AND-OR inverter.

4-12

CHAPTER 5
MAINTENANCE
5.1 SCOPE
This chapter provides a complete maintenance procedure for the DPV11 and includes a list of required
test equipment and diagnostics. The maintenance philosophy and procedures for preventive and corrective maintenance are discussed.
5.2 TEST EQUIPMENT RECOMMENDED
Maintenance procedures for the DPV11 require the test equipment and diagnostic programs listed in
Table 5-1.

Table 5-1

Test Equipment Recommended

Equipment

Manufacturer

Designation

Multimeter

Triplett or Simpson

Model 630-NA or 260 or
equjvalent

Oscilloscope

Tektronix

Type 453 or equivalent

X10 Probes (2)

Tektronix

P6008 or equivalent

Module extenders

DIGITAL

W984 (double)

Cable turn-around
connector

DIGITAL

H3259

On-board test
connector

DIGITAL

H3260

Breakout box

IDS

LIB kit

DIGITAL

ZJ314-RB

Document only

ZJ314-RZ

Document and
paper tape

ZJ314-RB

Paper tape only

ZJ314-PB

Fiche

ZJ314-FR

5-1

5.3 MAINTENANCE PHILOSOPHY
The basic approach to DPVll fault isolation is the use of stand-alone diagnostic programs and maintenance mode features supported by the hardware.
Typical applications of the DPVll do not allow lengthy troubleshooting sessions; therefore, the maintenance philosophy in the field is module swapping. The defective module is returned to the factory for repair.
5.4 PREVENTIVE MAINTENANCE
There is no scheduled preventive maintenance for the DPVll. Preventive maintenance for the DPVll
is integrated into its corresponding system preventive maintenance and consists of checking the power
supply voltage. Whenever the module or cables have been disturbed, diagnostics (specifically
DEC/Xll and DCLT) should be run to verify proper operation.
5.5 CORRECfIVE MAINTENANCE
Since the field replaceable units are the M8020 and the cables, all diagnosis should be directed to
isolation of one of these components.
NOTE
The operating jumper configuration of the DPVll
module being serviced should be recorded prior to
any changes for maintenance purposes. This will facilitate reconfiguring the module when the service activity is complete.
5.5.1 Maintenance Mode
To aid in troubleshooting, the DPV11 has a software-selectable maintenance mode which causes the
serial output of the USYNRT to be internally connected to its serial input. When in maintenance
mode, serial data from the modem is disabled and the send and receive timing from the modem are
replaced with a clock signal generated on the M8020 module. The clock rate is 2K b/s.
The diagnostics normally operate with and without the Maintenance Mode Select (MSEL) bit set. In
this way the USYNRT chip can be isolated from the remainder of the circuitry.
5.5.2 Loopback Connectors
The cable loopback connector shipped with the DPV11-DB (bundled version) is the H3259. This connector is connected to the modem end of the BC26L cable when it is used. No cables or test connectors
are shipped with the DPVl1-DA (unbundled versions). An on-board connector (H3260) can be purchased separately (see Paragraph 2.5 and Figure 2-4) for connecting to J1 on the M8020 module. It
provides for testing of all M8020 logic.
5.5.3 Diagnostics
DPV1l diagnostics aid in the isolation process and should be run when a malfunction is indicated.
Diagnostics should also be run to verify operation after repair.
NOTE
To ensure that all M8020 logic circuits are checked, on-board test connector H3260 must be used.
However, the DPVll system cannot be assumed to
be thoroughly checked unless the DIGITAL-supplied cable is also tested.
Diagnostics must be run with a cable turn-around
connector (H3259) at the modem end of the
BC26L-25 cable.
5-2

The following diagnostics are available to aid in the isolation and verification process.
5.5.3.1 CVDPV* Functional Diagnostic - CVDPV* is designed to verify the functionality of the
DPVII. No resolution to the chip is intended. CVDPV* is a stand-alone program that must be executed under control of the PDP-II diagnostic supervisor (DS). Errors are reported as they occur in the
program~ unless they are inhibited, and conform to the DS error report format. For information on
loading and running of the DS, see Appendix A.
CVDPV* is compatible with XXDP+ , ACT/SLIDE, APT or ABS. It consists of a number of tests
which function as follows.
Test No.

Description

Verifies that addressing the RXCSR does not cause a nonexistent memory trap.

Verifies that the DPVII may be properly initialized by a Master Clear or LSI-II Reset.

Writes and reads data patterns into all writable bits to verify hit validity and addressing paths.

Enables and ensures that the transmitter is activated.

Verifies that TBEMTY is asserted and cleared properly for all possible conditions.

Verifies proper operation of the transmit interrupt.

Enables and ensures that the receiver is activated, and RDATRY is asserted properly.

Verifies proper operation of the receive interrrupt for the reception of data.

Verifies proper operation of RSTARY for all possible conditions.

Verifies proper operation of the receive interrupt for status.

Ensures that both transmit and receive interrupts are recognized.

Verifies proper operation of all modem status bits and ensures that DSCNG is set when
a transition occurs.

Verifies that an interrupt is received when DSCNG is set.

Verifies that if a DSCNG occurs during a receive interrupt, it will be recognized.

15-20

Verifies proper operation with bit-oriented protocols (BOP).

21-23

Verifies proper operation with byte count-oriented protocols (BCP).

24-28

Verifies CRC and VRC functions.

Verifies maintenance mode noninterrupt data operations.

30-36

Verifies BOP data operation.

37-40

Verifies BCP data operation.

5-3

Verifies D DCMP message protocol and message transmission.

Verifies high-speed BCP data operation.

Verifies high-speed BOP data operation.

5.5.3.2 DEC/XII CXDPV Module - CXDPV exercises up to six consecutively addressed DPVll
synchronous interfaces as they relate to the total system configuration. It is very useful in determining
whether a DPVll is the failing component among other system components in a system environment.
It is a system exerciser and does not operate as a stand-alone test. It must be configured and run as
part of a total system exerciser.
The DEC/XII System Exerciser must be run after the stand-alone diagnostic CVDPV* has been run.
It determines if the DPVll or another device adversely affects the total system operation. For more
information on DEC/XII, refer to the DEC/X11 User Manual (AC-F053B-MC) and DEC/X11
Cross-Reference (9AC-F055C-MC)

5.5.3.3 Data Communications Link Test CVCLH* (DCLT) - DCLT is a communications equipment
maintenance tool designed to isolate failures to either the interface, the telephone communication line,
or the modem. It exercises DPVll to DPVl1 links,
DCLT is XXDP+ or APT compatible and runs under control of the diagnostic supervisor (DS) (see
Appendix A). It requires 24K of memory. For more information on DCLT refer to CVCLH* document AC-F582A-MC.

5-4

APPENDIX A
DIAGNOSTIC SUPERVISOR SUMMARY
'A.I INTRODUCfION
The PDP-II diagnostic supervisor is a software package that performs the following functions.

A.2

•

Provides run-time support for diagnostic programs running on a PDP-II in stand-alone mode

•

Provides a consistent operator interface to load and run a single diagnostic program or a
script of programs

•

Provides a common programmer interface for diagnostic development

•

Imposes a common structure upon diagnostic programs

•

Guarantees compatibility with various load systems such as APT, ACT, SLIDE, XXDP+,
ABS Loader

•

Performs nondiagnostic functions for programs, such as console I/0, data conversion, test
sequencing, program options

VERSIONS OF THE DIAGNOSTIC SUPERVISOR
FileName

Environment

HSAA **.SYS

XXDP+

HSAB **.SYS

APT

HSAC **.SYS

ACT/SLIDE

HSAD **.SYS

Paper Tape (Absolute Loader)

In the above file names, "**,, stands for revision and patch level, such as "AO".
A.3 LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC
A supervisor-compatible* diagnostic program may be loaded and started in the normal way, using any
of the supported load systems. Using XXDP+ for example, the program CVDPVA.BIN is loaded and
started by typing .R CVD PVA.
The diagnostic and the supervisor will automatically be loaded as shown in Figure A-I and the program started. The program types the following message.
DRS LOADED
DIAG.RUN-TIME SERVICES
CVDPV-A-O

* To determine if diagnostics are supervisor-compatible, use the List command under the Setup utility (see Paragraph A.5.).

A-I

XXDP+ / DIAGNOSTIC SUPERVISOR MEMORY LAYOUT
ON A 16KW (MIN MEMORY) SYSTEM
ADDRESS
100000 (0)
XXDP+

070000 (0)

DIAGNOSTIC
SUPERVISOR
( 6KW)

040000 (0)

DIAGNOSTIC
PROGRAM
( 7.5KW)

002000 (0)
000000 (0)
MK-2216

Figure A-I

Typical XXDP+ /Diagnostic Supervisor Memory Layout

DIAGNOSTIC TESTS
UNIT IS DPVll
DR>
DR> is the prompt for the diagnostic supervisor routine. At this point a supervisor command must be
entered (the supervisor commands are listed in Paragraph AA).
Five Steps to Run a Supervisor Diagnostic
1.

Enter Start command.
When the prompt DR> is issued, type:
STA/PASS:l/FLAGS:HOE <CR>
The switches and flags are optional.

Enter number of units to be tested.
The program responds to the Start command with:

# UNITS?
At this point enter the number of devices to be tested.

A-2

Answer hardware parameter questions.
After the number of devices to be tested has been entered, the program responds by asking a
number of hardware questions. The answers to these questions are used to build hardware
parameter tables in memory. A series of questions is posed for each device to be tested. A
"Hardware P-Table" is built for each device.

Answer software parameter questions.
When all the "Hardware P-Tables" are built, the program responds with:
CHANGESW?
If other than the default parameters are desired for the software, type Y. If the default parameters are desired, type N.
If you type Y, a series of software questions will be asked and the answers to these will be
entered into the "Software P-Table" in memory. The software questions will be asked only
once, regardless of the number of units to be tested.

Diagnostic execution.
After the software questions have been answered, the diagnostic begins to run.
What happens next is determined by the switch options selected with the Start command, or
errors occurring during execution of the diagnostic.

A.4 SUPERVISOR COMMANDS
The supervisor commands that may be issued in response to the DR> prompt are as follows.
•

Start - Starts a diagnostic program.

•

Restart - When a diagnostic has stopped and control is given back to the supervisor, this
command restarts the program from the beginning.

•

Continue - Allows a diagnostic to continue running from where it was stopped.

•

Proceed - Causes the diagnostic to resume with the next test after the one in which it halted.

•

Exit - Transfers control to the XXDP+ monitor.

•

Drop - Drops units specified until an Add or Start command is given.

•

Add - Adds units specified. These units must have been previously dropped.

•

Print - Prints out statistics if available.

•

Display - Displays P-Tables.

•

Flags - Used to change flags.

•

ZFLAGS - Clears flags.

All of the supervisor commands except Exit, Print, Flags, and ZFLAGS can be used with switch options.
A-3

A.4.1 Command Switches
Switch options may be used with most supervisor commands. The available switches and their function
are as follows.

•

./TESTS: - Used to specify the tests to be run (the default is all tests). An example of the
tests switch used with the Start command to run tests 1 through 5, 19, and 34 through 38
would be:
DR> START/TESTS: 1-5 : 19 : 34-38 <CR>

•

.jPASS: - Used to specify the number of passes for the diagnostic to run. For example:
DR> START/PASS: 1
In this example, the diagnostic would complete one pass and give control back to the supervisor.

•

.jEOP: - Used to specify how many passes of the diagnostic will occur before the end of pass
message is printed (the default is one).

•

.jUNITS: - Used to specify the units to be run. This switch is valid only if N was entered in
response to the CHANGE HW? question.

•

./FLAGS: - Used to check for conditions and modify program execution accordingly. The
conditions checked for are as follows.
:HOE -Halt an error (transfers control back to the supervisor)
:LO E - Loop on error
:IER - Inhibit error reports
:IBE - Inhibit basic error information
:IXE - Inhibit extended error information
:PRI - Print errors on line printer
:PNT - Print the number of the test being executed prior to execution
:BOE - Ring bell on error
:UAM - Run in unattended mode, bypass manual intervention tests
:ISR - Inhibit statistical reports
:IOU - Inhibit dropping of units by program

A.4.2 Control/Escape Characters Supported
The keyboard functions supported by the diagnostic supervisor are as follows.

•

CONTROL C (TC) - Returns control to the supervisor. The DR> prompt would be typed in
response to CONTROL C. This function can be typed at any time.

A-4

•

CONTROL Z (iZ) - Used during hardware or software dialogue to terminate the dialogue
and select default values.

•

CONTROL 0 (iO) - Disables all printouts. This is valid only during a printout.

•

CONTROL S (is) - Used during a printout to temporarily freeze the printout.

•

CONTROL Q (iQ) - Resumes a printout after a CONTROL S.

A.5 THE SETUP UTILITY
Setup is a utility program that allows the operator to create parameters for a supervisor diagnostic
prior to execution. This is valid for either XXDP+ or ACT jSLIDE environments. Setup asks the
hardware and software questions and builds the P-Tables.
The following commands are available under Setup.
List - list supervisor diagnostics
Setup - create P-Tables
Exit - return control to the supervisor
The format for the List command is:
LIST DDN:FILE.EXT
Its function is to type the file name and creation date of the file specified if it is a revision C or later
supervisor diagnostic. If no file name is given, all revision C or later supervisor diagnostics are listed.
The default for the device is the system device, and wild cards are accepted.
The format for the Setup command is:
SETUP DDN:FILE.EXT= DDN:FILE.EXT
It reads the input file specified and prompts the operator for information to build P-Tables. An output
file is created to run in the environment specified. File names for the output and input files may be the
same. The output and input device may be the same. The default for the device is the system device
and wild cards are not accepted.

A-5

APPENDIX B
USYNRT DESCRIPTION

5025 Universal Synchronous Receiver jTransmitter (USYNRT)
The data paths of the USYNRT provide complete serialization, deserialization and buffering. Output
signals are provided to the USYNRT controller to indicate the state of the data paths, the command
fields or recognition of extended address fields. These tasks must be performed by the USYNRT controller.

The USYNRT is a 40-pin dual-in-line package (DIP). Figure B-1 is a terminal connection (identification) diagram.

Data port bits DP07:DPOO are dedicated to service four 8-bit wide registers. Bits DP15:DP08 service
either control information or status registers. The PCSCR register is reserved. (See Figure B-2.)
Purchase Specification 2112517-0-0 provides a detailed description of the 5025 USYNRT.

B-1

RSI

RXCLK

TSO

TBEMTY

TXACT

TERR

39 TXCLK
37 TXENA

RDATRY 06
RSTARY 07
RXACT 05
08 RXENA
SYNC + 04
ADR COMP

DP 15
DP14
23

DP13

DPENA

DP 12
DP 11

DP 10 12
19

ADR SEL 2

DP 09

DP 08

ADR SEL 1

ADR SEL 0

DO 06 25

BYTE GP

DP 05

BIDIRECTIONAL
I/O TRI STATE
LINES

DP 07 24

DP 04
WR TO LSI

DP 03 28
DP 02 29

MAINT SEL

GND

DP 01 30
DP 00 31

33 RESET
V CC

09
+5

+12

NOTE: A) PIN 32 +5V POWER SUPPLY
±10% AT 100mA.
B) PIN 01 +12V POWER SUPPLY
±10% AT 100mA.
C) PIN 9 = GROUND
MK-141f)

Figure B-1

Terminal Connection Identification Diagram (2112517-0-0 Variation)

B-2

DP15

ERR
CHK

ASSY BIT ACCOUNT

RIO

OVER
RUN

ABORT
OR
GA

REOM

RSOM

RIO

2
I

DPOO

RX DATA

I
RIO

RIO

RDSR

TGA

TABORT

TEOM

TSOM

R/W

TERR

ADRO

I
RIO

TX DATA

-""

I
R/W

R/W

TDSR
MK-1S02

Figure B-2 5025 Internal Register Bit Map (2112517-0-0 Variation) (Sheet 1 of 2)

B-3

14
CCP

RIO

R/O

RIO

I
IDLE
SEL

MODE

SEC
ADRS
MODE

STRIP
SYNC

LOOP

ERR TYPE SEL
02

R/O

TX RX SYNC

"OR"RX SEC ADRS

I
R/W

R/W

I
R/W

R/W

R/W
ADR4

~TS DATA LEN SEL~

R/W

1 8

I
I
i
i
EXADD i EXCON ~RX DATA LEN SEL~

I
I

R/W

I 01 !
I R/W I

I
I

RESERVED

I
PCSCR

!
ADR 6
MK·1503

Figure B-2 5025 Internal Register Bit Map (2112517-0-0 Variation) (Sheet 2 of 2)

B-4

APPENDIX C
IC DESCRIPTIONS
C.I GENERAL
This appendix contains data on the LSI-II chips and some of the unusual ICs used by the DPVII. The
other ICs are common, widely-used logic devices. Detailed specifications on these chips are readily
available, and hence are not included here.
C.2 DC003 INTERRUPT CHIP
The interrupt chip is an I8-pin DIP device. It provides the circuits to perform an interrupt transaction
in a computer system that uses a "pass-the-pulse" type arbitration scheme. The device provides two
interrupt channels labeled A and B, with the A section at a higher priority than the B section. Bus
signals use high-impedance input circuits or high-drive open-collector outputs, which allow the device
to directly attach to the computer system bus. Maximum current required from the Vcc supply is 140
rnA.

Figure C-I is a simplified logic diagram of the DC003 IC. Table C-I describes the signals and pins of
the DC003.

DC003
17

ROSTA H

15
14

05
03

""
""

13
12
10

ENA DATA H

ENA ST H

ENA ClK H

BIRO l

BIAKI L

BIAKO l

i"""

BINIT l

INITO l

BDIN l

VECTOR H

VEC ROSTB H

ENB ClK H

ENB DATA H
ROSTB H

ENB ST H

MK0164

Figure C-I

DC003 Logic Symbol
C-I

Table C-l DC003 Pin/Signal Descriptions

Signal

Description

VECTORH

Interrupt Vector Gating Signal - This signal gates the appropriate vector address onto the bus and forms the bus signal
BRPLY L. Not used in the DPVl1.

VEC RQSTB H

Vector Request B Signal - When asserted, this signal indicates
RQST B service vector address is required. When negated, it
indicates RQST A service vector address is required. VECTOR
H is the gating signal for the entire vector address; VEC RQST
B H is normally bit 2 of the address.

BDINL

Bus Data In - THE BDIN signal always precedes a BIAK signal.

INITO L

Initialize Out - This is the buffered BINIT L signal used in the
device interface for general initialization.

BINIT L

Bus Initialize - When asserted, this signal brings all drive lines
to their negated state (except INITO L).

BIAKO L

Bus Interrupt Acknowledge - This signal is the daisy-chained
signal that is passed by all devices not requesting interrupt service (see BIAKI L). Once passed by a device, it must remain
passed until a new BAIKI L is generated.

BIAKI L

Bus Interrupt Acknowledge - This signal is the processor's response to BIRQ L true. This signal is daisy-chained such that
the first requesting device blocks the sIgnal propagation while
nonrequesting devices pass the signal on as BIAKO L to the
next device in the chain. The leading edge of BIAKI L causes
BIRQ L to be unasserted by the requesting device.

BIRQ L

Asynchronous Bus Interrupt Request - The request is generated
by a true RQST signal along with the associated true Interrupt
Enable signal. The request is removed after the acceptance of
the BDIN L signal and on the leading edge of the BAIKI L signal, or the removal of the associated interrupt enable, or due to
the removal of the associated request signal.

17
10

RQSTA H
RQSTB H

Device Interrupt Request Signal - When asserted with the enable AjB flip-flop asserted, this signal causes the assertion of
BIRQ L on the bus. This signal line normally remains asserted
until the request is serviced.

16
11

ENASTH
ENB ST H

Interrupt Enable - This signal indicates the state of the interrupt enable AjB internal flip-flop which is controlled by the signalline ENAjB DATA H and the ENAjB CLK H clock line.

C-2

Table C-l

DC003 Pin/Signal Descriptions (Cont)

Signal

Description

15
12

ENADATAH
ENB DATA

Interrupt Enable Data - The level on this line, in conjunction
with the ENA/B CLK H signal, determines the state of the internal interrupt enable A flip-flop. The output of this flip-flop is
monitored by the ENA/B ST H signal.

14
13

ENA CLK H
ENB CLK H

Interrupt Enable Clock - When asserted (on the positive edge),
interrupt enable A/B flip-flop assumes the state of the ENA/B
DATA H signal line.

C.3 DC004 PROTOCOL CHIP
The protocol chip is a 20-pin DIP device that functions as a register selector, providing the signals
necessary to control data flow into and out of up to four word registers (8 bytes). Bus signals can
directly attach to the device because receivers and drivers are provided on the chip. An RC delay
circuit is provided to slow the response of the peripheral interface to data transfer requests. The circuit
is designed such that if tight tolerance is not required, then only an external 1K X 20 percent resistor is
necessary. External RCs can be added to vary the delay. Maximum current required from the Vee supply
is 120 rnA.
Figure C-2 is a simplified logic diagram of the DC004 IC. Signal and pin definitions for the DC004
are shown in Table C-2.

C.4 DCOOS BUS TRANSCEIVER CHIP
The 4-bit transceiver is a 20-pin DIP, low-power Schottky device for primary use in peripheral device
interfaces, functioning as a bidirectional buffer between a data bus and peripheral device logic. In
addition to the isolation function, the device also provides a comparison circuit for address selection
and a constant generator, useful for interrupt vector addresses. The bus I/O port provides high-impedance inputs and high-drive (70 rnA) open-collector outputs to allow direct connection to a computer's
data bus. On the peripheral device side, a bidirectional port is also provided, with standard TTL inputs
and 20 rnA tri-state drivers. Data on this port is the logical inversion of the data on the bus side.
Three address jumper inputs are used to compare against three bus inputs and to generate the signal
MATCH. The MATCH output is open-collector, which allows the output of several transceivers to be
wire-ANDed to form a composite address match signal. The address jumpers can also be put into a
third logical state that disconnects that jumper from the address match, allowing for "don't care" address bits. In addition to the three address jumper inputs, a fourth high-impedance input line is used to
enable/disable the MATCH output.
Three vector jumper inputs are used to generate a constant that can be passed to the computer bus.
The three inputs directly drive three of the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three operational states: receive data, transmit data, and disable.

C-3

VECTOR H

VCC

BDAL 2

ENB H

BDAL1

RXCX H

BDALO

SEL6 L

BWTBT L

SEL4 L

BSYNC L

SEL2 L

BDIN L

SELO L

BRPLY L

OUTHB L

BDOUT L

OUTLB L

GND

INWD L

+VCC

0
ENB
LATCH
G

ENB

§-VCC

SYNC
BDAL2 L 02

§-GND

0
02
LATCH
G

BDAL 1 L 03

DAL2

DECODER

0
01
LATCH
G

BDALO L 04

DAL1

13 OUTHB L

0
00
LATCH
0

L - - - - - - - - - - - - - - - - - - - - 1 0 1 VECTOR H
[~---------------------------~11

INWDL
MK-0171

Figure C-2

DC004 Simplified Logic Diagram
C-4

Table C-2

DC004 Pin/Signal Descriptions

Signal

Description

VECTORH

Vector - This input causes BRPLY L to be generated through
the delay circuit. Independent of BSYNC Land ENB H.

2
3
4

BDAL2 L
BDALIL
BDALO L

Bus Data Address Lines - These signals are latched at the assert
edge of BSYNC L. Lines 2 and 1 are decoded for the select outputs; line 0 is used for byte selection.

BWTBTL

Bus Write/Byte - While the BDOUT L input is asserted, this
signal indicates a byte or word operation: asserted = byte, unasserted = word. Decoded with BDOUT L and latched BDALO
L, BWTBT L is used to form OUTLB Land OUTHB L.

BSYNC L

Bus Synchronize - At the assert edge of this signal, address information is trapped in four latches. While unasserted, this signal disables all outputs except the vector term of BRPLY L.

BDINL

Bus Data In - This is a strobing signal to effect a data input
transaction. BDIN L generates BRPLY L through the delay circuit and INWD L.

BRPLY L

Bus Reply - This signal is generated through an RC delay by
VECTOR H, and strobed by BDIN L or DBOUT L, and
BSYNC L and latched ENB H.

BDOUTL

Bus Data Out - This is a stobing signal to effect a data output
transaction. Decoded with BWTBT Land BDALO, it is used to
form OUTLB Land OUTHB L. BDOUT L generates BRPLY
L through the delay circuit.

INWDL

In Word - Used to gate (read) data from a selected register onto
the data bus. It is enabled by BSYNC L and strobed by BDIN
L.

12
13

OUTLB L
OUTHB L

Out Low Byte, Out High Byte - Used to load (write) data into
the lower, higher, or both bytes of a selected register. It is enabled by BSYNC L and the decode of BWTBT L and latched
BDALO L. It is strobed by BDOUT L.

14
15
16
17

SELO L
SEL2 L
SEL4 L
SEL6 L

Select Lines - One of these four signals is true as a function of
BDAL2 Land BDALI L if ENB H is asserted at the assert
edge of BYSNC L. They indicate that a word register has been
selected for a data transaction. These signals never become asserted except at the assertion of BSYN L (then only if ENB H
is asserted at that time) and, once asserted, are not negated until
BSYNC L is negated.

RXCX

External Resistor Capacitor Node - This node is provided to
vary the delay between the BDIN L, BDOUT L, and VECTOR
H inputs and BRPLY L output. The external resistor should be
tied to Vcc and the capacitor to ground. As an output, it is the
logical inversion of BRPLY L.
C-5

Table C-2 DC004 Pin/Signal Descriptions (Cont)
Pin

Signal

Description

ENBH

Enable - This signal is latched at the asserted edge of BSYNC
L and is used to enable the select outputs and the address term
of BRPLY L.

Maximum current required from the Vee supply is 100 rnA.
Figure C-3 is a simplified logic diagram of the DC005 IC. Signal and pin definitions for the DC005
are shown in Table C-3.
C.5 26LS32 QUAD DIFFERENTIAL LINE RECEIVER
The 26LS32 line receiver is a 16-pin DIP device. Terminal connections are shown in Figure C-4.
C.6 8640 UNIBUS RECEIVER
The 8640 is a quad 2-input NOR. Its equivalent circuit is shown in Figure C-5.
C.7 8881 NAND
The 8881 is a quad 2-input NAND. The schematic and pin identifications are shown in Figure C-6.
C.8 9636A DUAL LINE DRIVER
The 9636A is an 8-pin DIP device specified to satisfy the requirements of EIA standards RS-423-A and
RS-232-C. Additionally, it satisfies the requirements of CCIIT V.28, V.10 and the federal standard
FIPS 1030.
The output slew rates are adjustable by a single external resistor connected from pin 1 to ground.
The logic diagram and terminal identification are shown in Figure C-7.
C.9 9638 DUAL DIFFERENTIAL LINE DRIVER
The 9638 is an 8-pin DIP device specified to satisfy the requirements of EIA RS-422-A and CCITT
V.11 specifications.
The logic diagram and terminal identification are shown in Figure C-8.

C-6

DC005 TRANSCEIVER

1
JA1 L
JA2 L 2
MATCH H 3
REC H 4
XMIT H 5
DAT3 H 6
DAT2 H 7
BUS3 L 8
BUS2 L 9
GND
10

20VCC
19 JA3 L
18 DATO H
17 DAT1 H
16 JV3 H
15 JV2 H
14 JV1 H
13 MENB L
12 BUSO L
11 BUSl L

DATO

JV 1

=
JA1
H

BUS2

=
JA2

JA3

MENB

XMIT

~~------------~~03

L-----i......J

MK-0170

REC

[2Q]- VCC

Figure C-3

ITQ}-- GND

DC005 Simplified Logic Diagram
C-7

MATCH H

Table C-3

DCOOS Pin/Signal Descriptions

Signal

Description

12
11
9
8

BUS 0 L
BUS 1 L
BUS2L
BUS 3 L

Bus Data - This set of four lines constitutes the bus side of the
transceiver. Open-collector output; high-impedance inputs. Low
=1.

18
17
7
6

DATOH
DATIH
DAT2H
DAT3H

Peripheral Device Data - These four tri-state lines carry the inverted received data from BUS (3:0) when the transceiver is in
the receive mode. When in transmit data mode, the data carried
on these lines is passed inverted to BUS (3:0). When in the disabled mode, these lines go open (high impedance). High = 1.

14
15
16

JV 1 H
JV 2H
JV 3 H

Vector Jumpers - These inputs, with internal pull-down resistors, directly drive BUS (3:1). A low or open on the jumper pin
causes an open condition on the corresponding BUS pin if
XMIT H is low. A high causes a one (low) to be transmitted on
the BUS pin. Note that BUS 0 L is not controlled by any jumpr
input.

MENBL

Match Enable - A low on this line enables the MATCH output.
A high forces MATCH low, overriding the match circuit.

MATCHH

Address Match - When BUS (3:1) matches with the state of JA
(3:1) and MENB L is low, this output is open; otherwise, it is
low.

1
2
19

JA 1 L
JA 2 L
JA 3 L

Address Jumpers - A strap to ground on these inputs allows a
match to occur with a one (low) on the corresponding BUS line;
an open allows a match with a zero (high); a strap to Vee disconnects the corresponding address bit from the comparison.

5
4

XMITH
RECH

Control Inputs - These lines control the operational of the transceiver as follows.
REC XMIT

o
o
1
1

o
1
o

DISABLE: BUS and DAT open
XMIT DATA: DAT to BUS
RECEIVE: BUS to DAT
RECEIVE: BUS to DAT

To avoid tri-state overlap conditions, an internal circuit delays
the change of modes between Transmit data mode, and delays
tri-state drivers on the DAT lines from enabling. This action is
independent of the disable mode.

C-8

NOTE: PIN 1 IS MARKED FOR ORIENTATION. NUMBERS INDICATED DENOTE TERMINAL NUMBERS.
TERMINAL IDENTIFICATION
1.INPUT A
2. INPUT A
3. OUTPUT A
4. ENABLE
5. OUTPUT C
6. INPUT C
7. INPUT C
8. GROUND

16. POSITIVE SUPPLY VOLTAGE (Vee)
15. INPUT B
14. INPUT B
13. OUTPUT B
12. ENABLE
11. OUTPUT D
10. INPUT D
9. INPUT D
MK·1340

Figure C-4

26LS32 Terminal Connection Diagram and Terminal Identification

C-9

6
7

D
D

3
10

Vee = PIN 8

GND = PIN 1
MK-1321

Figure C-5

8640 Equivalent Logic Diagram

vee

GND
MK-1322

Figure C-6

8881 Pin Identification

C-IO

(1 )

(6)

(3)

(4)

(8)

NOTE: NUMBERS IN ( ) DENOTE TERMINAL NUMBERS.
TERMINAL IDENTIFICATION
(1) WAVESHAPE CONTROL (RISE AND FALL TIME)
(2) INPUT A
(3) INPUT B
(4) POWER AND SIGNAL GROUND
(5) NEGATIVE SUPPLY VOLTAGE
(6) OUTPUT B
(7) OUTPUT A
(8) POSITIVE SUPPLY VOLTAGE (Vee!
MK-1323

Figure C-7

9636A Logic Diagram and Terminal Identification

C-ll

CH.1
OUT A

V+

(7)

CH.1

IN CH. 1

OUT B
(6)

CH.2

IN CH.2

OUTA

CH.2
OUT B

GND

NOTE: NUMBERS IN ( ) DENOTE TERMINAL NUMBERS.

TERMINAL IDENTIFICATION
1. POSITIVE SUPPLY VOLTAGE
2. CHANNEL 1 INPUT
3. CHANNEL 2 OUTPUT
4. SUPPLY AND SIGNAL GROUND
5. CHANNEL 2 INVERTED OUTPUT
6. CHANNE:L 2 NON INVERTED OUTPUT
7. CHANNEL 1 INVERTED OUTPUT
8. CHANNEL 1 NON INVERTED OUTPUT
MK·1324

Figure C-8

9638 Logic Diagram and Terminal Identification

C-12

APPENDIXD
PROGRAMMING EXAMPLES
Two examples are included in this appendix. The first is an example for bit-oriented protocols, and the
second is an example for byte count-oriented protocols.
These are only examples and are not intended for any other purpose.

D-l

.TITLE
.IDENT

DPV11
/X00/

DPV-11 DDM FOR BIT ORIENTED PROTOCOLS

COPYRIGHT (C) 1980 BY
DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
EXAMPLE OF AN APPLICATION RSX-11M BIT ORIENTED DPV-11 DEVICE DRIVER
*** NOTE - THIS IS NOT A RUNNING DRIVER
.MCALL
HWDDF$
CCBDF$
MDCDF$
TMPDF$

HWDDF$,$INTSX,$INTXT,MDCDF$,CCBDF$,TMPDF$,ASYRET,SYNRET
DEFINE THE HARDWARE REGISTERS
DEFINE THE CCB OFFSETS
DEFINE THE MODEM CONTROL SYMBOLS
DEFINE LINE-TABLE TEMPLATE OPERATORS

DEVICE CHARACTERISTICS DEFINED IN
DC.HDX
DC.PRT
DC.MPT
DC.SEC
DC.ADR
DC.SPS
DC.SSS

000001
00013137
(2J0aC1(2J
130131320
(2J0C(2J40
01313013
0130033

HALF-DUPLEX LINE INDICATOR
PROTOCOL SELECTION FIELD
MULTI-POINT CONFIGURATION
MULTI-POINT SECONDARY MODE
STATION ADDRESS IS 1(, BITS
SDLC PRIMARY STATION
SDLC SECONDARY STATION

DEVICE STATUS FLAGS DEFINED IN
DD.ENB
DD. s'rR
DD.EOM
DD.SOM
DD. ABT ,
DD.SYN
DD.TRN
DD.ACT
DD.DIS

-D.DCHR(WORD #(3)
(WORD #1)
(WORD #1)
(WORD #1)
(WORD ft 1)
(COMPOSITE)
(COMPOSITE)

-D. FLAG-

IF ZERO, LINE HAS BEEN ENABLED
0131
IF ZERO, LINE HAS BEEN STARTED
002
CF.EOM
--(UNUSED)-CF.SOM
--(UNUSED)-TRANSMIT ABORTED DUE TO UNDERRUN
1320
CF'.SYN
TRANSMIT SYNC-TRAIN REQUIRED
CF.TRN
TRANSMIT LINE TURN-AROUND REQUIRED
21313
i TRANSMITTER READY FOR NEXT FRAME
DD.ENB!DD.STR ; INITIAL STATUS = DISABLED, STOPPED
SEL 0 ]

MODEM CONTROL BITS

;

DSCHG
DSRING
DSCTS
DSCARY
DSMODR
DSITEN
DSLOOP
DSRTS
DSDTR
DSSEL

100131313
1341301313
02001313
0113000
131310130
000040
000010
000004
000002
0013001

SEL " ]
RXACT
RXSRDY
RXFLAG
RXDONE
RXITEN
RXREN

004000
002000
000400
000200
000100
000020
SEL 2 ]

RXERR
RXABC
RXBFOV
RXOVRN

100000
070kHH~

010000
004000

DATA SET CHANGE
RING INDICATOR
CLEAR TO SEND
CARRIER INDICATOR
MODEM READY
DATA SET INTERRUPT ENABLE
DATA SET LOOPBACK
REQUEST TO SEND
DATA TERMINAL READY
SELECT FREQUENCY OR REMOTE LOOPBACK
RECEIVER CONTROL BITS
RECE IVER AC'l'IVE
RECEIVER STATUS READY
RECEIVER FLAG DETECT
RECEIVER DONE
RECEIVER INTERRUPT ENABLE
RECEIVER ENABLE
RECEIVER STATUS INPUTS
RECEIVER CRC ERROR
RECEIVER ASSEMBLED BIT COUNT
RECEIVER BUFFER OVERFLOW (SOFTWARE ERROR)
RECEIVER DATA OVERRUN

0-2

RXABRT
RXENDM
RXSTRM

RECEIVED ABORT
RECEIVED ENP OF MESSAGE
RECEIVED START OF MESSAGE

002000
001000
000400
SEL 2 ]

MODE CONTROL OUTPUTS

;

DPAPf\.
DPDECM
DPSTRP
DPSECS
DPIDLE
DPCRC
DPADRC
INPRM

ALL PARTIES ADDRESSED
DDCMP / BISYNC OPERATION
STRIP SYNC OR LOOP MODE
SDLC / ADCCP SECONDARY STATION SELECT
IDLE MODE SELECT
USE CRC 16 ERROR DETECTION
STATION ADDRESS OR SYNC CHARACTER
INITIAL STARTUP PARAMETERS

10000"

= 040000

020000
0100130
1304000
3*400
000377
DPSTRP!DPCRC

SEL 4 ]

TRANSMITTER STATUS AND CONTROL

1&;0000
010000
"04000
003400
000100
000020
000010
000004
000002
000001

TRANSMlT CHARACTER LENGTH
EXTENDED ADDRESS FIELD
EXTENDED CONTROL FIELD
RECEIVE CHARACTER LENGTH
TRANSMITTER INTERRUPT ENABLE
TRANSMITTER ENABLE
MAINTENANCE MODE SELECT
TRANSMITTER DONE
TRANSMITTER ACTIVE
DEVICE RESET

;

TCLEN
EXADD
EXCON
RCLEN
TXITEN
TXREN
TXMAI
TXDONE
TXACT
TXRES

SEL 6 ]

TRANSMITTER OUTPUT CONTROLS

;

TXLATE
TXGO
TXABRT
TXENDM
'rXSTRM

100000
004000
002000
001000
000400

TRANSMITTER DATA LATE (UNDERRUN)
TRANSMITTER GO AHEAD
TRANSMITTER ABORT
TRANSMIT END OF MESSAGE
TRANSMIT START or MESSAGE

;

; PROCESS DISPATCH TABLE
;

$DXPTB: :
.WORD
.WORD
.WORD
.WORD
.WORD

$SDASX
$SDASR
$SDKIL
$SDCTL
$SDTIM

.SBTTL

$SDPRI

TRANSMIT ENABLE
RECEIVE ENABLE (ASSIGN BUFFER)
KILL I/O ENABLE
CONTROL ENABLE
TIME OUT
RECEIVE INTERRUPT SERVICE ROUTINE

;+
FUNCTION:
THE DEVICE INTERRUPT IS VECTORED BY THE HARDWARE TO THE
DEVICE LINE TABLE. THE '$SDPRI ' LABEL IS ENTERED VIA A
CALLING SEQUENCE IN THE LINE TABLE AT OFFSET 'D.RXIN'.
ON ENTRY:
R5
0{SP)
2 (SP)
4(SP)

= ADDRESS OF 'D.RDBF ' IN THE LINE TABLE
SAVED R5
= INTERRUPTED PC
= INTERRUPTED PS

OUTPUTS:
R5 = ADDRESS OF 'D.RDB2 1 IN THE LINE TABLE
D.RVAD = RECEIVER STATUS BITS FROM CSR [SEL 2]
;-

0-3

$SDPRI: :
MOV
R3,- (SP)
MOV
R4,- (SP)
MOV
@(RS)+,R4
BIC
#RXABC,R4
.IF DF M$$MGE
MOV
KISAR6,-(SP)
MOV
(RS)+,KISAR6
.IFTF
DEC
(RS)+
BMI
DPRBO

iii

SAVE REGISTERS

; ; ;

iii GET CHARACTER AND FLAGS
;ii DON'T WORRY ABOUT ASSEMBLED BIT COUNT
iii
;i;

SAVE CURRENT MAP
MAP TO DATA BUFFER

i ; ; DECREMENT BUFFER BYTE COUNT
;;; BUFFER OVERFLOW - POST COMPLETE

MOV
BIT
BNE

2 (RS) , R3
#RXSRDy,-(R3)
DPRCP

iii GET CSR+2 ADDRESS
;;; ERROR OR END-OF-MESSAGE ?
;;; YES - POST RECEIVE COMPLETE

MOVB

R4,@(RS)+

;i;

STORE CHARACTER IN RECEIVE BUFFER

(SP)+,KISAR6

ii;

RESTORE PREVIOUS MAPPING

-(RS)
(SP)+,R4
{SP)+,R3

;;; ADVANCE BUFFER ADDRESS
;;; RESTORE REGISTERS

.IFT
MOV
.IFTF
INC
MOV
MOV
$INTXT
DPRBO:
BIS

#RXBFOV,R4

DPRCP:
.IFT
MOV
.ENDC
MOV
MOV
BIC
MOV
MOV
$INTSX

; ; ;

;;; EXIT THE INTERRUPT
i;;
ii;

BUFFER OVERRUN HAS OCCURRED
SET (SOFTWARE) ERROR INDICATOR

i;i

END-OF-MESSAGE OR ERROR INDICATION

(SP)+,KISAR6

, , , RESTORE PREVIOUS MAPPING

R4, (RS) +
(RS)+,R4
#RXITEN,-{R4)
(SP)+,R4
(SP)+,R3

; ; ;
; ; ;
; ; ;
; ; ;

SAVE STATUS FLAGS IN 'D.RVAD'
GET CSR+2 ADDR + POINT TO 'D.RPRI'
CLEAR RECEIVER INTERRUPT ENABLE
RESTORE R4 SO '$INTSV' IS HAPPY
, , , AND R3
; ; ; DO A TRICKY $INTSV (RS SAVED BUT NOT R4)

CHECK FOR ERRORS, POST RECEIVE COMPLETE, ASSIGN NEW BUFFER
MOV
MOV
ADD
SUB
CLR

40$:

R3,-{SP)
(RS) , R4
#D.RCNT-D.RCCB,RS
(RS)+,C.CNTl{R4)
R3

;; SAVE AN ADDITIONAL REGISTER
CCB ADDRESS TO R4 (RS POPPED)
; i BACK UP TO THE RESI DUAL COUNT
;i COMPUTE RECEIVED FRAME BYTE COUNT
i; SET R3 FOR COMPLETION STATUS
i;

BIC
BEQ
ASR
ASR
ASRB
MOVB
MOV
BCC
INC
CALL
BR

-(R5)
;i SHIFT ERROR INDICATORS •.•
(R5)+
i; ••• TWO PLACES RIGHT
-(RS)
i i SHIFT 'RXABRT' INTO C-BIT
(RS)+,R3
i i USE INDICATORS AS TABLE INDEX
RCVERR-2(R3) ,R3 ;; R3 NOW = CCB STATUS FLAGS
40$
; i FRAME NOT ABORTED - POST COMPLETE
D.RABT-D.RDB2(R5) iCOUNT NUMBER OF ABORTED FRAMES
RBFUSE
;; RE-INITIALIZE WITH THE SAME BUFFER
60$
;; RE-ENABLE INTERRUPTS FOR NEXT FRAME

BIS
MOV
CALL
MOV
CALL

C.STS(R4) ,R3
R3,-(SP)
$DDRCP
(SP)+,R3
RBFSET

#61777,(RS)+

40$

ii NO -- POST RECEIVE COMPLETE O.K.

ANY ERRORS REPORTED?

;; INCLUDE RE-SYNC STATUS, IF ANY
SAVE STATUS REPORTED TO DLC
;; POST RECEIVE COMPLETE
;; RECOVER COMPLETION STATUS
;i ASSIGN NEW CCB TO THE RECEIVER

D-4

60$:

FAILED - LEAVE RECEIVER INACTIVE
WAS AN ERROR REPORTED TO DLe ?
; ; YES - DISABLE RCVR FOR RE-SYNC

BCS
TST
BMI

DREXIT
R3
DRCLRA

MOV
SIS

- (R5) , R3
iRXITEN,-(R3)

MOV
RETURN

(SP)+,R3

; ;
; ;

; ; RECEIVER CSR [SEL 2] TO R3
RE-ENABLE RECEIVER INTERRUPTS

; ;

DREXIT:
; ;
; i

RESTORE REGISTER R3
EXIT TO THE SYSTEM

;+
DRCLRA:
MOMENTARILY RESET 'RXREN' FLAG IN ORDER TO FORCE RECEIVER
RE-SYNCHRONIZATION. THIS IS REQUIRED FOR ANY ERROR WHICH
TERMINATES THE RECEIVE OPERATION IN MID-FRAME.
ON ENTRY:
R5 = ADDRESS OF 'D.RCCB' IN THE LINE TABLE
R4 = ADDRESS OF 'C.STS' IN THE NEWLY-ASSIGNED CCB
(SP)= SAVED R3 VALUE
i-

DRCLRA:
MOV
BIC
BIS
SIS
BR

- (R5) , R3
iRXREN,-(R3)
iCS.RSN, (R4)
iRXREN!RXITEN,(R3)
DREXIT

.SBTTL

$SDPTI

RCVR CSR ADDRESS [SEL 2] TO R3
RESET RCVR ENABLE FOR RE-SYNC
SET RE-SYNC IN CCB 'C.STS'
i ; RE-ENABLE THE RECEIVER
; ; RESTORE R3 AND EXIT

; ;
; ;
; ;

TRANSMIT INTERRUPT SERVICE ROUTINE

;+
FUNCTION:
THE DEVICE INTERRUPT IS VECTORED BY THE HARDWARE TO THE
DEVICE LINE TABLE. THE '$SDPTI' LABEL IS ENTERED VIA A
CALLING SEQUENCE IN THE LINE TABLE AT OFFSET 'D.TXIN'.
ONCE FRAME TRANSMISSION IS INITIATED, EACH INTERRUPT IS
HANDLED BY THE ROUTINE ADDRESSED VIA THE 'D.TSPA' WORD.
ON ENTRY:
R5
0(SP)
2 (SP)
4(SP)

ADDRESS OF 'D.TCSR' IN THE LINE TABLE
SAVED R5
INTERRUPTED PC
INTERRUPTED PS

ON EXIT:
R5

ADDRESS OF 'D.TCCB' IN THE LINE TABLK

$SDPTI::

MOV
MOV
TST
JMP

R4,-(SP)
(R5)+,R4
(R4)+
@ (R5) +
-

CURRENT STATE =
i- -

SAVE R4
GET TRANSMITTER CSR ADDRESS
;;; POINT TO [SEL 6] + TEST UNDERRUN
; i i GO TO CORRECT STATE PROCESSOR
i;;
;ii

-i

MONITOR CSR FOR 'CLEAR TO SEND' ;

-i

'I'ISCTS:
BIT
BNE
BITB
BEQ

iDSCTS,-6(R4)
TISIFL
iDD.SYN,D.FLAG-D.TCNT(R5)
TISIFX

D-5

;;; IS 'CLEAR TO SEND' ACTIVE YET?
YES - START TO SEND THE FRAME
SYNC-TRAIN REQUIRED?
NO -- SEND FLAGS UNTIL 'CTS'

;i;
iii
i;i

MOV
BR

#TXSTRM!TXENDM,{R4}
TISEXT

CURRENT STATE

START + END SENDS SYNC STRING

ii;

- - - -

- - - - - - -;

- - - -

- - - - - - - - - - - -;

SEND INITIAL FRAME 'FLAG'

TISIFL:
MOV

#TISTRT,-(R5}

; ; ;

NEXT STATE

SEND ADDRESS BYTE

MOV
BR

#TXSTRM,{R4}
TISEXT

; i ;

SEND AN SDLC FLAG CHARACTER

'rISIFX:

CURRENT STATE
j-

- - - - - - - - - - - - - -;
SEND ADDR BYTE FOLLOWING 'FLAG' ;

-i

TISTRT:
DEC
MOV
MOV
BR
i-

{R5}
D.TADC-D.TCNT{R5), (R4)
#TISDAT,-{R5)
TISEXT

CURRENT STATE

; i ; DECREMENT COUNT FOR ADDR BYTE
;;; SEND ADDR, CLEAR 'TXSTRM'
;;; NEXT STATE
DATA TRANSFER
-

-i

TRANSFER FRAME DATA BYTES

'l'ISDAT:
BMI
TISLAT
DEC
(R5) +
BMI
TISEND
.IF DF M$$MGE
MOV
KISAR6,-(SP)
MOV
(R5)+,KISAR6
• 1FTIi'
(R5)
INC
@ (R5) + , (R4)
MOVB
.IFT
MOV
(SP)+,KISAR6
.ENDC

;;; UNDERRUN - ABORT AND RE-TRANSMIT
;;; DECREMENT DATA BYTE COUNT
;;; ALL DONE - SEND END-MSG SEQUENCE
;ii SAVE CURRENT MAPPING
;i; MAP TO THE TRANSMIT BUFFER
i i ; ADVANCE THE BUFFER ADDRESS
;;; NEXT CHARACTER TO BE SENT

TISEXT:
MOV
$INTXT
i-

RESTORE PREVIOUS MAPPING

;i;

; i ; COMMON LEVEL-7 INTERRUPT EXIT
;;; RESTORE R4
;;; EXIT INTERRUPT SERVICE

(SP)+,R4

CURRENT STATE =

-i

DATA BYTE-COUNT EXHAUSTED

;- -

TISEND:
MOV
INC
MOV
ASLB
BPL
MOV
BR

#TXENDM, (R4)
- (R5)
# TIS F LG , - (R 5 )
D.FLAG-D.TSPA(R5}
TISEXT
#TISPAD, (R5)
TISEXT
-

CURRENT STATE =

; ; i TRANSMIT END-OF-MSG SEQUENCE
i ; ; ADJUST R5 AND CLEAR 'D.TCNT'
; ; i NEXT STATE
IDLE FLAGS (ASSUMED)
; i ; TEST FOR LINE TURN-AROUND

ii; NO -- IDLE THE LINE WITH FLAGS

YES - SEND PADS, THEN DISABLE

;ii
-

-i

SEND 'ABORT' AS PAD AFTER 'FLAG';

-i

TISPAD:
CLRB
MOV
MOV
BR
i-

D.FLAG-D.TCNT(R5)
#TISCLR,-(R5)
#TXABRT, (R4)
TISEXT

- -

CURRENT STATE

;;; RESET THE DEVICE FLAG BYTE
NEXT STATE = SEND SECOND PAD
SET 'TXABRT' TO SEND A PAD

i;i
ii;

-j

-i

SEND SECOND 'ABORT' AS PAD

TISCLR:
MOV

#TISRTS,-(R5)

;i;

NEXT STATE

D-6

DROP 'REQUEST TO SEND'

TISCLX:
MOV
BIC
BR
i-

#TXABRT, (R4)
#TXREN,-(R4)
TISEXT

CURRENT STATE =

;ii SETUP TO SEND ANOTHER 'ABORT'
i;i DISABLE THE TRANSMITTER

-i

-j

CHAR

DROP REQUEST TO SEND + EXIT

TISRTS:
BIT
BEQ
BIC
BR
i- -

#DC.HDX,D.DCHR-D.TCNT(RS)
TISDON
#DSRTS,-6(R4)
TISDON

i;;
iii
iii
iii

HALF-DUPLEX CHANNEL?
NO -- LEAVE 'RTS' ACTIVE
DROP 'REQUEST TO SEND' LINE
POST TRANSMIT COMPLETE

- _.,

CURRENT STATE =

TRANSMITTER DATA UNDERRUN

-j

TISLAT:
MOV
MOVB
INC
BR

#TISDON,-(RS)
#DD.ABT,D.FLAG-D.TSPA(RS)
D.TURN-D.TSPA(RS)
TISCLX

NEXT STATE
RE-TRANSMIT
THIS FRAME WAS ABORTED
, , , COUNT THE ERROR EVENTS
i ; i SEND PAD, DISABLE TRANSMITTER
; ; ;

; ; i

i- -

; -

- -

CURRENT STATE =

-i

IDLE FLAGS BETWEEN FRAMES

TISFLG:
MOV
MOVB

#TXSTRM,(R4)
ii; CLEAR 'TXENDM', IDLE FLAGS
#DD.ACT,D.FLAG-D.TCNT(RS) iii TRANSMITTER IS ACTIVE

i; -

CURRENT STATE

-j

POST COMPLETE OR RE-TRANSMIT

TISDON:

; -

ADD
BIC
MOV
$INTSX

#D.TPRI-D.TCNT,RS iii ADJUST LINE TABLE POINTER
#TXITEN,-(R4)
i;i DISABLE 'TXDONE' INTERRUPTS
(SP)+,R4
i;i RESTORE R4 FOR PRIORITY DROP
i ; ; '$INTSV' WIO R4 SAVED (POPS RS)

MOV
MOV
CLR
BITB
BNE
TST
BNE
CLR
CALL
MOV
BEQ
MOV

R3,-(SP)
;; SAVE AN ADDITIONAL REGISTER
(RS) , R4
;; ACTIVE CCB ADDRESS TO R4
(RS)+
;; THIS CCB IS NO LONGER ACTIVE
#DD.ABT,D.FLAG-D.TCBQ(RS) ;; WAS THE FRAME ABORTED?
TRSTRT
;; YES - SETUP RE-TRANSMISSION
D.KCCB-D.TCBQ(RS)
II
TRANSMIT KILL IN PROGRESS?
CKILLT
;; YES - RETURN CCB'S TO THE DLC
R3
;; SET COMPLETION STATUS = SUCCESS
$DDXMP
;; POST TRANSMIT COMPLETE TO THE DLC
(RS) , R4
;; FIRST CCB ON SECONDARY CHAIN
TREXIT
;; NONE THERE - TRANSMITTER IDLE
(R4) , (RS)
ii REMOVE CCB FROM SECONDARY CHAIN

CURRENT STATE =

-i

-j

START UP FRAME TRANSMISSION

TRSTRT:
CLR
MOV
TST
ADD
BISB
SICB

(R4)
ii CLEAR CCB LINKAGE WORD
R4,-(RS)
ii SETUP AS THE ACTIVE CCB
-(RS)
i i SKIP BACK OVER 'D.TPRI'
#C.FLGl,R4
ii POINT TO THE CCB BUFFER FLAGS
(R4) ,D.FLAG-D.TPRI(RS)
II
SAVE FLAGS FOR LEVEL-7 USE
#DD.ABT,D.FLAG-D.TPRI(RS) iMAKE SURE 'ABORT' FLAG IS OFF

MOV
CLR
MOV

-(R4) ,D.TCNT-D.TPRI(RS) ; i SET TRANSMIT BYTE COUNT
-(RS)
;; INITIALIZE 'D.TADC' WORD
-(R4) ,-(RS)
ij SET TRANSMIT BUFFER ADDRESS

D-7

.IF DF M$$MGE
MOV
- (R4) ,- (RS)
MOV
KISAR6,-(SP)
(RS)+,KISARfi
MOV
.IFTF
@(RS) + , (RS)
MOVB
.IFT
MOV
(SP)+,KISAR6
.ENDC

20$:

40$:

; ;
; ;
; ;

SET TRANSMIT BUFFER RELOCATION
SAVE THE CURRENT APR6 MAPPING
MAP TO THE TRANSMIT BUFFER

; ; MOVE ADDRESS BYTE TO 'D.TADC'
; ;

RESTORE PREVIOUS APR6 MAPPING

; ;

BACK UP TO STATE PROCESSOR CELL
IS THE TRANSMITTER READY NOW ?
NO -- ENABLE IT, THEN START

ADD
TSTB
BPL

#D.TSPA-D.TADC,RS
D.FLAG-D.TSPA(RS)
20$

MOV
BR

#TISTRT, (RS)
40$

; ;

MOV
BIS
BIS

-2 (RS) , R3
#DSRTS ,-4 (R3)
#TXREN, (R3) +

; ;
i ;
; i

TRANSMITTER CSR [SEL 4] TO R3
ASSERT 'REQUEST TO SEND'
ENABLE THE TRANSMITTER

MOV

#TISCTS, (RS)

; ;

INITIAL STATE

BIS

#TXITEN,@-(RS)

; ; RE-ENABLE TRANSMIT INTERRUPTS

MOV
ASYRET

(SP)+,R3

; ;
; ;

; ;

INITIAL STATE = SEND ADDR BYTE
ENABLE INTERRUPTS AND EXIT

= WAIT FOR 'CTS'

TREXIT:

i- -

CURRENT STATE
i- -

RESTORE R3 FROM ENTRY
EXIT WHEREVER APPROPRIATE, ASYNC
-;

TRANSMIT KILL OR TIMEOUT
-

CKILLT:
MOV

#CS.ERR!CS.ABO,-(SP);; TRANSMIT COMPLETION STATUS

BIC
MOV
CLR

#TXREN,@D.TCSR-D.TCBQ(RS);; DISABLE TRANSMITTER
(RS) ,(R4)
;; ADD SECONDARY CHAIN TO PRIMARY
(RS)+
;; CLEAR SECONDARY CHAIN POINTER

MOV
MOV
CLR
CALL
MOV
BNE
TST

(SP) ,R3
(R4) ,-(SP)
(R4)
$DDXMP
(SP)+,R4
20$
(SP)+

;;
;;
;;
;;
;;
;;
;;

COMPLETION STATUS TO R3
NEXT CCB ADDRESS TO STACK
MAKE SURE LINK WORD IS ZERO
POST A CCB COMPLETE W/ERROR
NEXT CCB ADDRESS TO R4
MORE TO GO - CONTINUE
CLEAN STATUS OFF THE STACK

MOV
BEQ
CLR
CLR

(RS) , R4
TREXIT
(RS)
R3

;;
;;
;;
;;

KILL CCB ADDRESS TO R4
NONE - RESTORE R3 AND EXIT
KILL NO LONGER IN PROGRESS
STATUS = SUCCESSFUL

CMPB
BNE
CALL
BR

#FC.KIL,C.FNC(R4)
40$
$DDKCP
TREXIT

CALL
BR

$DDCCP
TREXIT

.SBTTL

$SDASX

CKTTMO:

20$:

40$:

;;
;;
;;
;;

KILL-I/O OR CONTROL FUNCTION?
CONTROL - POST IT COMPLETE
POST KILL-I/O COMPLETE
RESTORE R3 AND EXIT

;; POST CONTROL COMPLETE
;; RESTORE R3 AND EXIT
TRANSMIT ENABLE ENTRY

;+
FUNCTION:
'$SDASX'

IS ENTERED (VIA THE DISPATCH TABLE) TO QUEUE A

D-8

CCB CONTAINING AN SDLC FRAME TO BE TRANSMITTED.
IF THE
TRANSMITTER IS BUSY, THE CCB !S QUEUED TO THE SECONDARY
CCB CHAIN.
IF NOT, THE TRANSMITTER IS ENABLED TO START
TRANSMITTING THE NEW FRAME.
ON ENTRY:
R4
RS
PS

ADDRESS OF TRANSMIT ENABLE CCB
ADDRESS OF DEVICE LINE TABLE
PRIORITY OF CALLING DLC PROCESS

ON EXIT:
ALL REGISTERS ARE UNPREDICTABLE
;-

$SDASX: :

20$:

MOV
MOV
BIC
ADD

R3,-(SP)
D.TCSR(RS) ,R3
:f/:TXITEN, (R3)
:f/:D.TCCB,RS

; ; SAVE R3 FOR EXIT VIA 'TRSTRT'
; ; TRANSMIT CSR ADDRESS [SEL 4] TO R3
; ; DISABLE TRANSMITTER INTERRUPTS
; ; POINT TO ACTIVE CCB ADDRESS CELL

TST
BEQ
MOV

(RS)+
TRSTRT
R4,-(SP)

i ;
; i

MOV
MOV
BNE

RS,R4
(R4) , RS
20$

; ; COpy THE CCB ADDRESS TO R4
i ; ADDRESS OF THE NEXT CCB TO RS
; ; LOOP UNTIL WE FIND THE END

(SP)+,(R4)

MOV
CLR
BIS
BR

@ (R4) +

:f/:TXITEN, (R3)
TREXIT

.SBTTL

$SDASR

; ;

IS THERE AN ACTIVE CCB ?
NO -- START UP THE TRANSMITTER
SAVE POINTER TO FIRST CCB

LINK NEW CCB TO END OF CHAIN
MARK NEW END OF CCB CHAIN
i i RE-ENABLE TRANSMITTER INTERRUPTS
; ; RESTORE R3 AND EXIT
; i

; ;

RECEIVE ENABLE AFTER BUFFER WAIT

;+
FUNCTION:
THIS ROUTINE IS CALLED BY THE BUFFER POOL MANAGER WHEN
A BUFFER ALLOCATION REQUEST CAN BE SATISFIED, FOLLOWING
AN ALLOCATION FAILURE AND A CALL TO '$RDBWT'.
ON ENTRY:
R4
RS

ADDRESS OF CCB AND RECEIVE BUFFER
ADDRESS OF DEVICE LINE TABLE

ON EXIT:
RS
ADDRESS OF 'D.RCCB' IN THE LINE TABLE
R4
ADDRESS OF 'C.STS' IN THE CCB
(SP)= SAVED VALUE OF R3
;-

$SDASR: :

;+
; $SDSTR

ADD
CALL
BIS

:f/:D.RDB2,RS
RBFUSE
:f/:CS.BUF, (R4)

ii
;i

MOV
JMP

R3,-(SP)
DRCLRA

;; PUSH R3 FOR EXIT AT 'DREXIT', ABOVE
i; RESET AND ACTIVATE THE RECEIVER

;; POINT TO SECOND RCVR-CSR WORD
ASSIGN BUFFER TO THE RECEIVER
PREV. ALLOC. FAILURE TO CCB 'C.STS'

START UP DEVICE AND LINE ACTIVITY

D-9

$SDSTR: :

20$:

60$:

BITB
BNE

#DD.ENB,D.FLAG(R5)
60$

MOV
MOV
BIS

D. RDBF(R5) , R3
D. STN (R5) , (R3)
#RXREN,-{R3)

; i RECEIVER CSR ADDR [SEL 2] TO R3
; ; SET ADDRESS BYTE + OPERATING MODE
; ; ENABLE THE RECEIVER

MOV
ADD
CALL
BCS
BIS

R5,-(SP)
#D.RDB2,R5
RBFSET
20$
#RXITEN, t R3)

SAVE LINE TABLE START ADDRESS
ADJUST R5 FOR BUFFER ROUTINE
ASSIGN A RECEIVE CCB AND BUFFER
; ; FAILED - START THE TRANSMITTER
; ; ENABLE RECEIVER INTERRUPTS

MOV
CLRB
BIT
BNE
BIS
BR
MOV
BR

(SP) +, R5
D. FLAG (R5)
#DC.HDX,D.DCHR(R5)
CTLCMP
#DSRTS, (R3)
CTLCMP
#CS.ERR!CS.DIS,R3
CTLERR

HAS THE LINE BEEN ENABLED ?
NO -- REJECT THE 'START'

; ;
i ;

; ;
; ;
; ;

; ; RECOVER LINE TABLE START
; ; LINE HAS BEEN STARTED
; ; CHECK THAT ASSUMPTION
; ; CORRECT - STARTUP COMPLETE
; ; ASSERT 'REQUEST TO SEND' LINE
, , ••• AND POST START COMPLETE
; ; STATUS = LINE DISABLED
; ; RETURN ERROR W/COMPLETION

;; CONTROL FUNCTION = NO-OPERATION

DP.NOP:
CTLCMP:

= SUCCESSFUL

CLR

;; STATUS

MOV
SYNRET

(SP)+,R4

;; RECOVER SAVED R4 VALUE
;; SYNCHRONOUS RETURN

.SBTTL

$SDSTP

CTLERR:

STOP DEVICE AND LINE ACTIVITY

i---------------------------------------------------------------i
, S TOP

CON T R 0 L

FUN C T ION

i---------------------------------------------------------------i
$SDSTP: :

20$:

MOV
MOV
CLR

D. RDBF (R5) , R3
#DSDTR,-(R3)
4(R3)

;; RECEIVER CSR ADDR [SEL 2] TO R3
;; DISABLE RECEIVER, LEAVE 'DSDTR' ACTIVE
;; DISABLE TRANSMITTER

MOV
BEQ
CALL

D.RCCB(R5) ,R4
20$
$RDBRT

; ;

CLR
CLR
BISB
CALL

D.RCCB(R5)
R4
D. SLN (R5) , R4
$RDBQP

; ;
; ;
; ;
; ;

BISB
TST
BEQ

#DD.STR,D.FLAG(R5)
D.TCCB(R5)
CTLCMP

; ; LINE IS NO LONGER STARTED
; i IS THERE AN ACTIVE TRANSMIT CCB ?
; i NO -- POST CONTROL COMPLETE

MOV
MOVB
ASYRET

(SP)+,D.KCCB(R5)

#1, (R5)

; ;
; ;
; ;

.SBTTL

$SDENB

ACTIVE RECEIVE CCB TO R4
; ; NONE THERE - SKIP IT
; ; RETURN BUFFER TO THE POOL
NO RECEIVE CCB ASSIGNED
CLEAR R4 FOR PARAMETER USE
SET SYSTEM LINE NUMBER IN R4
PURGE BUFFER WAIT QUEUE REQUESTS

SAVE THE CONTROL CCB FOR TIMEOUT
MAKE SURE THE TIMER IS ACTIVE
RETURN WITH ASYNCHRONOUS COMPLETION

ENABLE THE LINE AND DEVICE

i---------------------------------------------------------------i
E NAB L E

LIN E

AND

D E V ICE

i---------------------------------------------------------------i
$SDENB: :
MOV
BIS

D.RDBF(R5) ,R3
#TXRSET,2(R3)

;; RECEIVER CSR ADDRESS [SEL 2] TO R3
;; RESET THE DEVICE (I-US SINGLE-SHOT)

D-10

ADD
BIT
BEQ
SWAB
BIC
BIS
BIC
CMPB
BEQ
CMPB
BNE
BIS

;; POINT TO CHARACTERISTICS WORD #1
;; 16-BIT STATION ADDRESS?
20$
;; NO -- SHOULD BE ALL SET
(RS)
II
USE THE HIGH-ORDER BYTE IN DPV-11
#AC<DPADRC>,(RS) ;;CLEAR HIGH-ORDER BYTE OF 'D.STN' WORD
#INPRM,(R5)
;;SETUP INITIAL PARAMETERS
#DC.ADR,-(RS)
;; ADDRESS-SIZE NO LONGER SIGNIFICANT
#DC.SPS,(R5)
;; SDLC PRIMARY-STATION MODE?
40$
;; YES - FLAGS ARE SETUP AS IS
#DC.SSS,(RS)
;; SDLC SECONDARY-STATION MODE?
60$
i ; NO -- OPERATING MODE INVALID
#DPSECS,2(RS)
;; ENABLE STATION ADDRESS CHECKING

40$:

BIS
BICB
BR

#DSDTR,-(R3)
;; ASSERT 'DATA TERMINAL READY' LINE
#DD.ENB,D.FLAG-D.DCHR-2(R5) ;; LINE IS ENABLED
CTLCMP
;; POST CONTROL FUNCTION COMPLETE

60$:

MOV
BR

#CS.ERR!CS.DEV,R3 ;; ERROR STATUS - INVALID PROTOCOL
CTLERR
;; POST CONTROL COMPLETE WITH ERROR

.SBTTL

$SDDIS

MOV
BITB
BEQ

#CS.ERR!CS.ENB,R3
#DD.STR,D.FLAG(RS)
CTLERR

MOV
CLR
MOVB
BR

;; ADDRESS OF RECEIVER CSR [SEL 2]
D.RDBF(RS) ,R3
;; DISABLE RECEIVER + TURN DTR OFF
-(R3)
#DD.ENB!DD.STR,D.FLAG(RS) ;; LINE NO LONGER ENABLED
CTLCMP
;; CLEAR CARRY AND EXIT

.SBTTL

$SDMSN

20$:

#D.DCHR+2,RS

~DC.ADR,(RS)+

DISABLE THE LINE

;

$SDDIS::
II
ERROR CODE IF NOT STOPPED
;; IS LINE STATE CORRECT?
;; NO -- REJECT THE DISABLE

SENSE MODEM STATUS

i----------------------------------------------------- ----------;
SEN S E
MOD E M
S TAT U S
j---------------------------------------------------------------i
$SDMSN: :
CLR
;; CLEAR R4 FOR RETURN CODES
R4
MOV
D.RDBF(RS) ,R3
;; ADDRES~ OF RECEIVER CSR [SEL 2]
BIT
BEQ
BIS

#DSDSR,-(R3)
20$
#MC.DSR,R4

; ;
; ;
; ;

IS THE DATA-SET READY ?
NO -YES - SET INDICATOR IN R4

20$:

BIT
BEQ
BIS

#DSRING, (R3)
40$
#MC.RNG,R4

; ;
; ;
i ;

IS THE PHONE RINGING ?
NO -YES - SET INDICATOR IN R4

40$:

BIT
BEQ
BIS

#DSCARY, (R3)
60$
#MC.CAR,R4

; ; IS THERE CARRIER PRESENT ?
; ; NO -- POST COMPLETE
; ; YES - SET INDICATOR IN R4

60$:

MOV
BR

R4,(SP)
CTLCMP

; ;
; ;

.END
.TITLE
.IDENT

DPV - BYTE ORIENTED DPV-l1 DEVICE DRIVER MODULE
/X00/

RETURN RESULTS IN (SAVED) R4
POST CONTROL FUNCTION COMPLETE

D-ll

EXAMPLE OF AN APPLICATION RSX-IIM BYTE ORIENTED DPV-ll DEVICE DRIVER
.MCALL
.MCALL
.MCALL
.MCALL
MDCDF$
CCBDF$
TMPDF$
CHADF$

$INTSX,$INTXT,INHIB$,ENABL$
CCBDF$,TMPDF$,$LIBCL
MDCDF$
CHADF$
DEFINE MODEM CONTROL SYMBOLS
DEFINE THE CCB OFFSETS
DEFINE LINE TABLE OFFSET MACROS
DEFINE DEVICE CHARACTERISTICS

LOCAL SYMBOL DEFINITIONS
TRANSMITTER FLAGS
TINIT=
TXENA=
TXINT=
TXACT=
TS01'1=
TEOM=

000010
000020
000100
000002
000400
001000

INITIAL TRANSMIT STATUS (HALF DUPLEX)
TRANSMIT ENABLE
TRANSMIT INTERRUPT ENABLE
TRANSMIT ACTIVE
TRANSMIT START OF MESSAGE
TRANSMIT END OF MESSAGE

;

; RECEIVE CSR FLAGS
;

RCVEN=
RXINT=
CRC=
SSYN=
PROSEL=
RINIT=
INPRM=
;
;

RECEIVE ENABLERECEIVE INTERRUPT ENABLE
RECEIVE CRC CHECK
STRIP SYNC
PROTOCOL SELECTION (BYTE)
INITIAL RECEIVE STATUS
INITIALIZATION FLAGS

MODEI'1 STATUS FLAGS

RTS=
CTS=
DTR=
DSR=
RING=
i
;

000020
000100
3*400
020000
040000
RXINT!RCVEN!DTR
SSYN!PROSEL!CRC

000004
020000
000002
001000
040000

REQUEST TO SEND LEAD
CLEAR TO SEND
DATA TERMINAL READY
DATA SET READY
RING INDICATOR

DPV11 DEVICE DRIVER DISPATCH TABLE

TRANSMIT ENABLE
$DPVTB::.WORD
DPASX
RECEIVE ENABLE (ASSIGN BUFFER)
.WORD
DPASR
KILL I/O
DPKIL
.WORD
CONTROL INITIATION
.WORD
DPCTL
.WORD
TIME OUT
DPTIM
;+
**-$DPVRI-DPVll RECEIVE INTERRUPT SERVICE ROUTINE
THE DEVICE INTERRUPT IS VECTORED TO THE DEVICE LINE TABLE
BY THE HARDWARE AND THIS ROUTINE IS ENTERED BY A
'JSR R5,$DPVRI' INSTRUCTION AT THE BEGINNING OF THE LINE
'!'ABLE.
INPUTS:
R5 = ADDRESS OF DEVICE LINE TABLE + 4
STACK:
o (SP) = SAVED R5
2(SP)
INTERRUPTED BIAS
INTERRUPTED PC
4 (SP)
INTERRUPTED PS
6(SP)
OUTPUTS:

D-12

ETC.
;-

$DPVRI: :
SAVE R4
GET ADDRESS OF RECEIVER DATA BUFFER
GET CHARACTER AND FLAGS
; ; ; ANY ERROR IS RECEIVER OVERRUN

MOV
MOV
MOV
BMI

R4,-(SP)
(R5)+,R4
(R4) , R4
DPRHO

.IF DF

M$$MGE

MOV
MOV

KISAR6,- (SP)
(R5)+,KISAR6

; ; ;
; ; ;

SAVE CURRENT MAP
MAP TO DATA BUFFER

R4,@(R5)+

; ; ;

STORE CHARACTER IN RECEIVE BUFFER

(SP)+,KISAR6

; i ;

RESTORE PREVIOUS MAPPING

(R5)
DPRCP
-(R5)
(SP)+,R4

;;; DECREMENT REMAINING BYTE COUNT
IF EQ RECEIVE COMPLETE
;;; ADVANCE BUFFER ADDRESS
;;; RESTORE REGISTERS
;;; EXIT THE INTERRUPT

; ; ;
; ; i
; ; i

.IFTF
fvIOVB
.IFT
MOV
.ENDC
DEC
BEQ
INC
MOV
$INTXT

;i;

EXCEPTIONAL RECEIVE SERVICE ROUTINES
HARDWARE OVERRUN

DPRHO:

.ENABL

LSB

ADD
MOV

#<RCNT-RDBF-2),R5 i i ; POINT TO COUNT CELL
#100001,RFLAG-RCNT(R5) ; ; i SET FLAGS TO COMPLETE REQUEST AND
i ; ; CLEAR RECEIVE ACTIVE ON EXIT
#CS. ERR+CS.ROV,RSTAT-RCNT (R5) ; ; i SET OVERRUN STATUS

MOV

RECEIVE BYTE COUNT RUNOUT
DPRCP:

R4,(R5)+
;;; SAVE CRC FLAG AND POINT TO PRIORITY
MOV
RDBF-RPRI(R5) ,R4 ;;; GET RECEIVE DATA BUFFER ADDRESS
MOV
BIC
#RXINT,-(R4)
; ; i CLEAR RECEIVER INTERRUPT ENABLE
MOV
(SP)+,R4
; i ; RESTORE R4 SO '$INTSV' IS HAPPY
$INTSX
i ; ; DO A TRICKY $INTSV (R5 PRESAVED BUT NOT R4)
MOV
R3,-(SP)
;; SAVE AN ADDITIONAL REGISTER
TST
(R5) +
POINT TO FLAGS WORD
; ;
ASR
(R5)+
, , LOAD C-BIT FROM FLAGS (BIT 0)
BCS
20$
IF CS DATA, POST COMPLETION
; ;
MOV
(R5),R4
GET PRIMARY CCB ADDRESS
; ;
.LIST MEB
$LIBCL HDRA-RPRIM,R5,$DDHAR,SAV;; CALL DDHAR THROUGH LINE TABLE
.NLIST MEB
SAVE 'FINAL SEEN' IN FLAGS (BIT 15 SET)
ROR
-2(R5)
i;
TST
R3
;; EXAMINE BYTE COUNT FOR THIS MESSAGE
IF MI AN INVALID HEADER RECEIVED
BMI
10$
;;
IF EQ SET TO RECEIVE REST OF HEADER
BEQ
7$
;;
ADD
#2, R3
;; ACCOUNT FOR BCC IN CURRENT COUNT
MOV
R3,RPCNT-RPRIM(R5) ;; SAVE DATA COUNT UNTIL HEADER CRC

0-13

7$:

IS CHECKED
;;
; ; GET REMAINING HEADER
MARK DATA IN PROGRESS IN FLAGS (BIT 0 SET)
; ;
INCLUDE CURRENT COUNT IN TOTAL COUNT
; ;
POINT TO CURRENT COUNT
; ;
SET UP CURRENT BYTE COUNT
; ;
; ; MOVE BUFFER ADDRESS PAST BCC

MOV
INC
ADD
ADD
MOV
INC

#5,R3
-(R5)
R3,@-(R5)
#RCNT-RTHRD,R5
R3,(R5)
-(R5)

.IF DF

M$$MGE

MOV

-4 (R5) , R3

;;

GET ADDRESS OF RECEIVE DATA BUFFER

- (R5) , R3

GET ADDRESS OF RECEIVE DATA BUFFER

REXT0

; ;

FINISH IN COMMON CODE

.IFF
MOV
.ENDC
BR

INVALID HEADER RECEIVED
10$:

BIT
BNE
MOV
CALL
MOV
BR

#CS.MTL,R3
;; MESSAGE TOO LONG?
31$
;;
IF NE YES, POST COMPLETION
(R5)+,R4
;; RECOVER PRIMARY CCB ADDRESS
BUFUSE
;; SET UP THIS CCB AGAIN (CLEARS 'RSTAT')
RDBF-RPRIM(R5) ,R3 ;; SET POINTER TO REC. DAT. BUFF.
40$
;; CLEAR RECEIVE ACTIVE TO FORCE RESYNC

POST COMPLETION ON RECEIVE COMPLETE
R5
20$:

25$:

30$:
31$:

REXT:
REXT0:
REXT1 :

TST
BMI
MOV
BR
MOV
BEQ
ADD
SEC
ROL
INC
MOV
BR
CLR
MOV
BIS
CALL
MOV
CALL
BCS
BNE
CLR
BIS
MOV
RETURN

POINTS TO PRIMARY CCB ADDRESS
RCNT-RPRIM(R5) ;;
IS CRC ERROR FLAG SET?
25$
;;
IF MI, YES - CRC IS VALID
#CS.ERR+CS.DCR,R3;;
ELSE SET CRC ERROR STATUS FOR DLC
31$
;; GO RETURN BUFFER
RPCNT-RPRIM(R5) ,RCNT-RPRIM(R5) ;; SET REMAINING COUNT
30$
;; NONE SO END OF MESSAGE
RPCNT-RPRIM(R5) ,@RTHRD-RPRIM(R5) ;; SET TOTAL COUNT IN CCB
;; FORCE C BIT
RFLAG-RPRIM(R5) ;; PUT Q SYNC BACK & MARK NON HEADER
RADD-RPRIM(R5)
;; INCLUDE LAST CHAR IN BUFFER
RDBF-RPRIM(R5) ,R3 ;; GET CSR FOR EXIT
REXT
;; TAKE COMMON EXIT
R3
;; GET GOOD STATUS
(R5)+,R4
;; GET PRIMARY CCB ADDRESS
(R5) ,R3
;; PICK UP ADDITIONAL STATUS
$DDRCP
II
POST RECEIVE COMPLETION
RDBF-RSTAT(R5) ,R3;; GET ADDRESS OF RECEIVE DATA BUFFER
BUFSET
;; SET UP NEXT RECEIVE BUFFER
REXT1
;;
IF CS NO BUFFER AVAILABLE TURN OFF RECEIVER
40$
;;
IF NE CLEAR RECEIVE ACTIVE TO RESYNC
RPCNT-RPRIM(R5) ;; RESET PARTIAL COUNT
#RXINT,-(R3)
;;
ENABLE RECEIVER INTERRUPTS
(SP)+,R3
;; RESTORE R3
;; RETURN TO SYSTEM
;;

40$:

REF LABEL

CLEAR RECEIVE ACTIVE TO FORCE RESYNC
R3

= ADDRESS OF RECEIVE DAT BUFFER
0-14

R5
DPCRA:

ADDRESS OF 'RPRIM'

CLR
BIC
CLR
BIS
BIS
BR

CLEAR FLAGS WORD
-(R5)
; ;
CLEAR RECEIVE ACTIVE FOR RESYNC
#RCVEN,- (R3)
; ;
RPCNT-RFLAG (R5) i ; RESET PARTIAL COUNT
INDICATE A RESYNC
#CS.RSN,RSTAT-RFLAG(R5) ; ;
#RINIT, (R3)
ENABLE RECEIVER
i ;
REXT1
FINISH IN COMMON CODE
; ;

.DSABL

LSB

;+
**-$DPVTI-DPV11 TRANSMIT INTERRUPT SERVICE
THIS ROUTINE IS ENTERED ON A TRANSMITTER INTERRRUPT VIA
A 'JSR R5,DPVTI' WITH R5 CONTAINING THE ADDRESS OF THE
DEVICE LINE TABLE OFFSET BY 'TCSR'.
INPU'l'S:
R5 = ADDRESS OF DEVICE LINE TABLE + 'TCSR'
STACK CONTAINS:
0(SP)
INTERRUPTED R5
2(SP)
INTERRUPTED BIAS
4(SP)
INTERRUPTED PC
6(SP)
INTERRUPTED PS
OUTPUTS:
ETC.
;-

.ENABL

LSB

MOV
MOV
TST
BMI
DEC
BEQ

R4,-(SP)
i i ; SAVE R4
(R5)+,R4
; ; ; GET TRANSMITTER CSR ADDRESS
(R4)+
i i ; TEST FOR UNDERRUN
10$
; ; ; IF MI, UNDERRUN - WAIT FOR TIMEOUT
TCNT-TCSR-2 (R5) ; ; ; DECREMENT COUNT
20$
; ; ; IF EQ, BYTE COUNT RUNOUT

.IF DF

M$$MGE

MOV
MOV

KISAR6,-(SP)
(R5)+,KISAR6

iii SAVE CURRENT MAPPING
i;i MAP TO DATA BUFFER

@ (R5) + , (R4)

i;i OUTPUT A CHARACTER

(SP)+,KISAR6

iii

-(R5)
(SP)+,R4

ii; UPDATE BUFFER ADDRESS
ii; RESTORE R4

$DPVTI: :

.IFTF
MOVB
.IFT
MOV

RESTORE PREVIOUS MAPPING

.IFTF
INC
MOV
$INTXT

TRANSMITTER UNDERRUN
DISABLE TRANSMITTER INTERRUPTS AND WAIT FOR A TIMEOUT

D-15

10$:

BISB
MOV

#TSOM/4 0" , 1 (R4) ;;; CLEAR UNDERRUN BIT
#TUNST,TSTAT-TCSR-2(R5) ;;; SET STATE TO DISABLE TRANSMITTER

TRANSMIT BYTE COUNT RUNOUT
OUTPUT TO STATE PROCESSING ROUTINES:
R3
R5
20$:

ADDRESS OF TRANSMITTER CSR
ADDRESS OF THREAD WORD CELL

ADD
BIC
MOV
$INTSX

#TPRI-TCSR-2, R5 ; ; i POINT TO PRIORITY DATA
#TXINT,-(R4)
; ; i CLEAR INTERRUPT ENABLE
(S P) +, R4
;;; RESTORE R4 SO '$INTSV' IS HAPPY
;SAVE WITH R5 ON STACK BUT NOT R4

.IFT
KISAR6,-(SP)

MOV

SAVE CURRENT MAPPING

.IFTF
MOV
MOV
CALLR

R3,-{SP)
ii
SAVE AN ADDITIONAL REGISTER
TCSR-TSTAT(R5) ,R3;; GET TRANSMITTER CSR ADDRESS
@(R5)+
;; DISPATCH TO PROCESSING ROUTINE

.DSABL

LSB

;+
**-DPASX-ASSIGN A TRANSMIT BUFFER
THIS ROUTINE IS ENTERED VIA THE MATRIX SWITCH TO
QUEUE A CCB FOR TRANSMISSION.
INPUTS:
R4
R5

ADDRESS OF CCB TO TRANSMIT
ADDRESS OF DEVICE LINE TABLE

OUTPUTS:
IF THE TRANSMITTER IS IDLE, TRANSMISSION IS
INITIATED; OTHERWISE, THE CCB (OR CHAIN) IS QUEUED TO
THE END OF THE SECONDARY CHAIN.
REGISTERS MODIFIED:
R3, R4, AND R5
;-

DPASX:
MOV
BIC
ADD

TCSR(R5) , R3
iTXINT, (R3)
#TPRIM,R5

GET TRANSMITTER CSR ADDRESS
DISABLE TRANSMITTER INTERRUPTS
POINT TO PRIMARY CELL

KISAR6,-(SP)

SAVE CURRENT MAPPING

R3,-(SP)
(R5)+

SAVE R3
PRIMARY ASSIGNED ?

.IFT
MOV
. I F'TF

MOV
TST

D-16

10$:
20$:

BNE
CALL
BIT
BEQ
MOV
BR

10$
TBSET
#TXACT, (R3)
STSTR
#STSTR,-(R5)
WAITI

IF NE, YES - QUEUE TO SECONDARY CHAIN
SET UP PRIMARY
TRANSMITTER ACTIVE ?
IF EQ, NO - START IMMEDIATELY
SET STATE FOR STARTUP
WAIT FOR INTERRUPT

MOV
MOV
MOV
BNE
MOV
BR

R4,-(SP)
R5,R4
(R4) , R5
20$
(SP)+,(R4)
TEXT2

SAVE POINTER TO FIRST CCB
COpy POINTER TO CCB
GET NEXT CCB
IF NE, KEEP GOING
LINK NEW CCB CHAIN TO LAST CCB
FINISH IN COMMON CODE

;+
; **-STSTR-STARTUP STATE PROCESSING
;-

STSTR:

BIS
BIS
MOVB

#RTS, -4 (R3)
; ASSERT REQUEST TO SEND
#TXENA, (R3)
; ENABLE TRANSMITTER
TIMS-TTHRD(R5) ,TIME-TTHRD(R5) ; START TIMER

; **-STCTS-WAIT FOR CLEAR TO SEND STATE PROCESSING
i-

STCTS:

BIT
BNE
MOV
MOV
MOV
BR

#CTS ,-4 (R3)
STSYN
#STCTS,-(R5)
#$PADB,R4
#T S OM , - ( S P)
TEXT1

IS CLEAR TO SEND UP ?
IF NE, YES - START SYNC TRAIN
SET STATE FOR CTS
SET ADDRESS OF PAD BUFFER
SET TSOM, CLEAR TEOM
FINISH IN COMMON CODE

;+
; **-STSYN-SYNC TRAIN REQUIRED STATE PROCESSING
;-

STSYN:

MOV
MOV
MOV
BR

# S TDA T , - (R 5 )
#$SYNB,R4
#'rSOM,- (SP)
TEXT0

SET STATE FOR DATA
SET ADDRESS OF SYNC BUFFER
SET TSOM, CLEAR TEOM
FINISH IN COMMON CODE

;+
i

**-STCRC-SEND CRC STATE PROCESSING

.ENABL

LSB

STCRC:

BIS
CALL
BNE
MOV
BIT
BEQ
MOV
BR

#TEOM,2(R3)
SEND CRC
TPOST
POST COMPLETION AND SET UP NEXT CCB
10$
IF NE, NOTHING MORE TO SEND
#STDAT, - (R5)
i ASSUME NEXT STATE I S SEND SYNC'S
ICF.SYN,C.FLG-C.BUF(R4) ; ARE SYNC'S REQUIRED?
20$
IF EQ, NO - LEAVE ASSUMED STATE
#STSYN,(R5)
ELSE CHANGE STATE TO SEND SYNC'S
20$
WAIT FOR CRC TO BE SENT

10$:

MOV
EIC

#TXENA, (R3)

~S'I'IDL,-(R5)

SET STATE TO IDLE
SHUT DOWN TRANSMITTER

20$ :
i+

D-17

; **-WAITI-WAIT FOR INTERRUPT
;-

WAITI:

MOV
i'10VB

11,TCNT-TSTAT(RS) ; WAIT FOR ONE INTERRUPT
TIMS-TSTAT(RS) ,TIME-TSTAT(RS) ; START TIMER
TEXT2
FINISH IN COMMON CODE

;+
; **-STIDL-IDLE STATE PROCESSING
i-

STIDL:

BIC
'fST

#RTS,-4(R3)
- (RS)

DROP REQUEST TO SEND

CLRB
BR

T IME-TSTAT (RS)
TEXT3

CLEAR TIMER
FINISH IN COMMON CODE

.DSABL

LSB

30$:

;+
**-TUNST-TRANSMIT DATA UNDER RUN STATE
RETURN ALL TRANSMIT BUFFERS TO HIGHER LEVEL
i-

TUNST:

;"T

ADD
CLRB
CALL
MOV
BR

;;TIMEOUT EXPECTS DDM LINE TABLE POINTER
i;RESET TIMER
;;FAKE A TIMEOUT TO RETURN BUFFERS
DPTI1'1
;;SET STATE TO IDLE
#STIDL,TSEC-TSTAT(RS)
;;TAKE COMMON EXIT
TEXT3
#-TTHRD,RS
(RS)

; **-STDAT-DATA STATE PROCESSING
i-

STDAT:

10$:

20$:

MOV
ADD
TST
BPL
CALL
MOV
BIT
BEQ
MOV
CLR

(RS) ,R4
; GET ADDRESS OF FLAGS WORD FROM THREAD
IC.FLG-C.STS,(RS) i UPDATE THREAD POINTER
(R4)+
LAST BUFFER THIS CCB ? (BIT IS SET)
10$
IF PL, NO
TPOST
POST COMPLETION AND SET UP NEXT CCB
ISTDAT,-(RS)
; ASSUME DATA CONTINUES
ICF.EOM,C.FLG-C.BUF(R4) ; SEND CRC FOLLOWING THIS BUFFER?
20$
IF EQ, NO - LEAVE ASSUMED STATE
ISTCRC, (RS)
ELSE CHANGE STATE FOR CRC TO BE SENT
-(SP)
CLEAR TSOM, CLEAR TEOM

;+
**-TEXT0-COMMON EXIT ROUTINES
**-TEXT1**-TEXT2**-TEXT3;TEXT0:
TEXT1:

MOVB
ADD

TIMS-TSTAT(RS) ,TIME-TSTAT(RS) ; START TIMER
#TCSR-TSTAT+2,RS ; POINT TO CURRENT BUFFER CELL

.IFT
MOV

(R4) +, (RS) +

COPY RELOCATION BIAS

(R4)+

SKIP OVER RELOCATION BIAS IN CCB

.IFF
TST

D-18

.IFrfF
MOV
MOV

(R4)+,(R5)+
(R4) , (R5)

COpy VIRTUAL ADDRESS
AND THE BYTE COUNT

-4 (R5) ,KISAR6

MAP TO DATA BUFFER

@-2 (R5) , (SP)
-2 (R5)
(SP)+,2(R3)
#TXINT, (R3)
(SP) +, R3

BUILD CHARACTER TO OUTPUT
UPDATE VIRTUAL ADDRESS
OUTPUT CHARACTER AND FLAGS
ENABLE TRANSMITTER INTERRUPTS
RESTORE R3

.IFT
MOV
.IFTF

TEXT2:
TEXT3:

BISB
INC
MOV
BIS
MOV
.IFT

D-19

GLOSSARY
Asynchronous Transmission
Transmission in which time intervals between transmitted characters may be of unequal length.
Transmission is controlled by start and stop elements at the beginning and end of each character.
Also called start-stop transmission.
BDIN
Data Input on the LSI-II bus.

BOOUT
Data Output on the LSI-II bus.
BIAKI
Interrupt Acknowledge.
Bit-Stuff Protocol
Zero insertion by the transmitter after any succession of five continuous ones designed for bitoriented protocols such as IBM's Synchronous Data Link Control (SDLC).
Bits per Second (b / s)
Bit transfer rate per unit of time.
BIRQ
Interrupt Request priority level for LSI-II bus.
BRPLY
LSI-II Bus Reply. BRPLY is asserted in response to BDIN or BDOUT.
BSYNC
Synchronize - asserted by the bus master device to indicate that it has placed an address on the
bus.
Buffer
Storage device used to compensate for a difference in the rate of data flow when transmitting
data from one device to another.
BWTBT
Write Byte.

ccrIT
Comite Consultatif Internationale de Te1egraphie et Telephonie - An international consultative
committee that sets international communications usage standards.
Control and Status Registers (CSRs)
Communication of control and status information is accomplished through these registers.

G-I

Cyclic Redundancy Check (CRC)
An error detection scheme in which the check character is generated by taking the remainder
after dividing all the serialized bits in a block of data by a predetermined binary number.
Data Link Escape (DLE)
A control character used exclusively to provide supplementary line control signals (control character sequences or OLE sequences). These are 2-character sequences where the first character is
OLE. The second character varies according to the function desired and the code used.
Data-Phone DIGITAL Service (DDS)
A communicaitons service of the Bell System in which data is transmitted in digital rather than
analog form, thus eliminating the need for modems.
DIGITAL Data Communications Protocol (DDCMP)
DIGITAL's standard communications protocol for character-oriented protocol.
Direct Memory Access (DMA)
Permits I/O transfer directly into or out of memory without passing through the processor's general registers.
Electronic Industries Association (EIA)
A standards organization specializing in the electrical and functional characteristics of interface
equipment.
Full-Duplex (FDX)
Simultaneous 2-way independent transmission in both directions.
Field-Replaceable Unit (FRU)
Refers to a faulty unit not to be repaired in the field. Unit is replaced with a good unit and faulty
unit is returned to predetermined location for repair.
Half-Duplex (HDX)
An alternate, one-way-at-a-time independent transmission.

LARS
Field Service Labor Activity Reporting System.
Non-Processor Request (NPR)
Direct memory access-type transfers, (see DMA).
Protocol
A formal set of conventions governing the format and relative timing of message exchange between two communicating processes.
RS-232-C
EIA standard single-ended interface levels to modem.
RS-422-A
EIA standard differential interface levels to modem.
RS-423-A
EIA standard single-ended interface levels to modem.

G-2

RS-449

EIA standard connections for RS-422-A and RS-423-A to modem interface.
Synchronous Transmission

Transmission in which the data characters and bits are transmitted at a fixed rate with the transmitter and receiver synchronized.
V.35

(CCITT Standard) - Differential current mode-type signal interface for high-speed modems.

G-3

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DPV11 SERIAL SYNCHRONOUS
INTERFACE TECHNICAL MANUAL
EK-DPV11-TM-002

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