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DEC-15-H2XB-D

August 1971

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Document:	MX15 Memory Bus Multiplexer
Order Number:	DEC-15-H2XB-D
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Pages:	70
Original Filename:	DEC-15-H2XB-D_MX15_Aug71.pdf

OCR Text

Digital Equipment Corporation
Maynard, Massachusetts

PDP-15 Systems
Maintenance Manual
Volume 1

MX15
Memory Bus Multiplexer

DEC-lS-H2XB-D

PDP-15 SYSTEMS
MX15
MEMORY BUS MULTIPLEXER
MAINTENANCE MANUAL
VOLUME1

DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS

1st Edition December 1970
2nd Printing (Rev) August 1971

Copyright © 1970, 1971 by Digital Equipment Corporation
The material in this manual is for information purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

CONTENTS
Page
CHAPTER 1

BASIC DESCRIPTION

1.1

Description and Purpose

1-1

1.2

System Description

1-2

1 .2. 1

Single and Multiprocessor System Description

1-2

1.2.1.1

Location of Equipment Bays

1-2

1.2.1.2

Memo ry Bus Load i ng

1-5

1.2.1.3

Addresses of MM15 Attached Directly to Processor Bus

1-5

1.2.1.4

MX15-A Output Bus Loading

1-5

1.2.1.5

Block Number of a Bank Attached to an MX 15-A

1-5

1.2. 1.6

Bank Numbers of MM15s Attached to MX15-As

1-5

1.2.1.7

Bank Disable (SELECT)

1-5

1.2.1.8

Bank Rotation

1-6

1.2.1.9

Address Restriction

1-6

1.2.1.10 Order of Filling MM15 Slots in MX15

1-6

1.2.1.11 Cable Length Limitation

1-6

1.2.1.12 Indicator Bus Restriction

1-6

1.2.2

Multiprocessor System Rules

1-7

1.2.2.1

MX15-A Priority Types

1-7

1.2.2.2

Processor Bus Priori ty

1-7

1.2.2.3

Proper Port Connection for PDP-15s

1-8

1.2.2.4

Direct Memory Access (DMA) Port

1-8

1.2.2.5

Power Fail Protection Configurations

1-8

1.3

MX15-A Specifications

1-8

1 .3. 1

Physical

1-8

1.3.2

Environmental

1-9

1.3.3

Electrical

1-9

1.3.3.1

Power

1-9

1.3.3.2

Delay and Cycle Times

1-9

1.3.3.3

Latency

1-9

1.4

Equipment Suppl ied

1-9

1.5

Reference Documents

1-11

CONTENTS (Cont)
Page
CHAPTER 2

INSTALLATION

2. 1

Shipping Check List

2-1

2.1.1

Customer Acceptance Procedure

2-2

2.1.2

Mul tipl e Processors

2-2

2.2

MX15 Configurations

2-2

2.3

Cabling

2-3

2.4

Block and Bank Assignments

2-7

2.5

Connection of Jumper Wires in Wirewrap Field

2-7

2.6

Adjustment of Priority Margin in Multiprocessor
and DMA Systems

2-9

2.7

Power

2-10

2.7.1

Adjustments

2-11

2.8

Field Add-Ons

2-11

2.8. 1

Processor Status

2-11

2.8.2

Memory Status

2-11

CHAPTER 3

OPERATION

3. 1

Memory Distribution

3-1

3.2

Priority

3-1

CHAPTER 4

PRINCIPLES OF OPERATION

4. 1

Block Diagram Analysis

4-1

4.2

Detailed Circuit Analysis

4-12

4.2.1

Bidirectional Switches

4-12

4.2.2

Address Decode Gates

4-13

4.2.3

Two-Bit Adder

4-13

4.2.4

Priority Control Ci rcuits

4-13

4.2.5

Inhibit Logic

4-19

4.2.6

M REQ Logic Timing

4-20

CHAPTER 5

DMA INTERFACE DESIGN

5. 1

MX15-A Advantages

5-1

5.1.1

Transfer Rate

5-1

CONTENTS (Cont)
Page
5.1.2

Latency

5-1

5.2

Signal Timing Considerations

5-2

5.3

Miscell aneous Signals

5-3

5.4

Back-to-Back DMA Breaks

5-3

5.4.1

Singl e Processor System

5-3

5.4.2

Dual Processor Systems

5-4

5.5

Wiring Guidelines

5-4

5.6

Ivbdules for Designing DMA Interface

5-4

CHAPTER 6

MAINTENANCE

6. 1

Preventive Maintenance

6-1

6.1.1

Vo I tage Checks

6-1

6.1.2

Margin Checks for Mul tiprocessor and DMA Systems

6-2

6.2

Corrective Maintenance

6-2

6.2. 1

Test Equipment Required

6-2

6.2.2

Specific Troubleshooting Techniques

6-3

6.2.2.1

Checking Priority Multiple Port Jumping Test

6-3

6.2.2.2

Indications of Cable Problems

6-3

6.2.2.3

Indications of Driver/Receiver Mal function

6-5

6.2.2.4

Add-to-Memory and Read Ivbdify Write RMW Malfunctions

6-5

6.2.2.5

Processor-Memory Lockup

6-5

6.3

Spare Ivbdule Requirements

6-5

6.4

Engineering Drawings

6-5

ILLUSTRA TIONS
Figure No.

Title

Art No.

Page

1-1

MX15-A Simplified Block Diagram

15-0386

1-2

Extended Memory Block Diagram

15-0387

1-3

Direct Memory Access Block Diagram

15-0388

1-3

1-4

Mul tiprocessor System Block Diagram

15-0389

1-4

1-5

128K CP/Memory Cable Lengths

15-0390

1-7

2-1

Maximum System Configuration Diagram

15-0410

2-3

ILLUSTRA no NS (Cont)

Title

Art No.

Page

2-2

MX15-A Configuration Diagram

15-0391

2-5

2-3

M628 Modul e, Block Sel ect Jumpers

15-0392

2-8

2-4

M628 and W714 Modules, Switch Functions

2-5

MX15 Power Distribution Block Diagram

15-0394

2-10

3-1

Memory Distribution in Multiprocessing Systems

15-0395

3-2

4-1

MX15-A Block Diagram (Sheet 1)

15-0396

4-3

4-1

MX15-A Block Diagram (Sheet 2)

15-0397

4-5

4-1

MX15-A Block Diagram (Sheet 3)

15-0398

4-7

4-2a

MX15-A Timing Diagram

15-0399

4-9

4-2b

MX15-A Timing Diagram

15-0400

4-9

4-2c

MX15-A Timing Diagram

15-0401

4-10

4-3

Bidirectional Switch

15-0402

4-12

4-4

Address Decode Gate

15-0403

4-14

4-5

Two-Bit Adder

15-0404

4-15

4-6

Priority Control Circuits

15-0405

4-17

4-7

Inhibit Logic

15-0406

4-19

4-8

Priority and M REQ Timing

15-0407

4-20

6-1

Mul tipl e Port Jumping Test Interconnections

15-0408

6-4

Figure No.

2-9

TABLES
Table No.

Title

Page

1-1

Equipment Suppl ied

1-10

5-1

Modules for DMA Interface Design

5-5

6-1

Voltage Tolerances

6-2

Test Equipment Required

6-3

Spare Module Recommendations

6-6

6-4

MX15 Engineering Drawings

6-6

CHAPTER 1
BASIC DESCRIPTION

1. 1

DESCRIPTION AND PURPOSE

The MX 15 Memory Bus Multiplexer option is designed for use with the PDP-15 computer system. The
option adds three important capabilities to the PDP-15:
a.

extended memory

direct memory access (DMA)

mu Itiprocessor systems appli cation

The option may include up to four MX 15-A Memory Bus Multiplexers, with appropriate MM 15XD
memory banks, power supplies and equipment bays.
The MX15-A is a high-speed hybrid switch with three input ports and one output port that can establish
one of three communication paths (see Figure 1-1) on a priority basis. Up to three memory data lines,
each from a separate processor or DMA device, can be connected to 32K of core memory via the
multiplexer. Logic within the MX 15-A governs the granting of priorities for processor access to the
multiplexer, thereby gaining access to the core memory. Port 1 has the highest priority, and port 3
has the lowest priority. Memory data line loading enables the PDP-15 processor to drive as many as
four MX15-As. In turn, each MX15-A is capable of driving 32K of core memory. Thus, by using four
MX15-As, core memory can be extended to 128K. Figures 1-2 through 1-4 illustrate three typical
configurations emphasizing extended memory, direct memory access, and multiprocessor applications.
Figure 1-2 illustrates the configuration for an extended memory system; it also emphasizes direct memory
access and simultaneous memory access features afforded by the MX15-A. The DMA device has direct
access to any memory block, because the DMA device is connected to the highest priority port of each
multiplexer. While the DMA device is accessing a specific memory block, the IPU or CPU of a KP15A
equipped with the KT15 Memory Protect and Relocate option can access a different memory block via
the two lower priority ports. The direct memory access capability of the MX15-A is illustrated in
Figure 1-3. Any device with the proper control circuitry can gain access to an MM15 memory through
one of the input ports of an MX 15-A. Chapter 5 describes how to design a DMA interface. The KT 15
memory relocation is required to jump blocks of memory, because user programs are restricted to 32K.
Figure 1-4 illustrates a multiprocessor system, emphasizing the bank rotate feature of the MX 15-A.
The bank rotate feature a Iters bank address bits 03 and 04 to preserve contiguous addressing
1-1

TO MEMORY (32K MAX)
~

________________

~A~

__________________

CONTROL
MPO

MOL
MPO

MX15-A
MEMORY BUS MULTI PLEXER

OUTPUT PORT

SWITCH

INPUT PORT 2

INPUT PORT 1

MOL
MPI

MOL
MP2

CONTROL
MPI

CONTROL

INPUT PORT

MOL
MP3

CONTROL
MP2

CONTROL
MP3

L-------------------~v~--------------------~

TO PROCESSORS OR OMA
15 - 0386

Figure 1-1

MX15-A Simplified Block Diagram

and to enabl e all memory banks to be accessed by both K P15 processors. Addresses that do not correspond to an existing memory bank are inhibited by the MX15-A. Without the bank rotate feature, a
multiprocessor system cannot be assembled using one block of core memory. Other multiprocessor systems can be configured using more than one multiplexer, if each is connected to a block of memory.
In these configurations, the bank rotate feature is not needed. In the configuration ill ustrated by
Figure 1-4, the processor connected to the high priority port could be used for high-speed I/O transfers;
simultaneously, the other processor can execute complex calculations on the data stored in the directlyconnected memory bank.

1.2 SYSTEM DESCRIPTION
1 .2.1

Single and Multiprocessor System Description

1.2.1. 1 Location of Equipment Bays - The MX 15 equipment bays are located immediately to the
left of the processor bay. Other options, such as disks that normally are located to the left of the
processor, must be located to the immediate left of the MX15 equipment bays.
1-2

BLOCK II

BLOCK 10

BLOCK 01

BLOCK 00

81(

NOTE 2

MOL AND
CONTROL

MPI

MOL AND
CONTROL

MPO

MX 15-A

MX15-A

MX15 -A

MX15-A

MP2

MP3

MPI

MP2

MP3

MP2

MPI

MP3

MPI

MP2

MP3

MOL AND CONTROL

MOL AND
CONTROL
DMA
DEVICE

IPU

CPU

KP15-A

NOTES:
I. MONITOR (I/O) PROGRAMS CAN JUMP
BLOCKS WITHOUT KT15 OPTION, BUT
USER PROGRAMS CANNOT.
2. EACH 8K MEMORY BANK IS MM15XD IN
MX15 CABINET OR MMI5-A AND MKI5-A
IN PROCESSOR CABINET.

15-0387

Figure 1-2

Extended Memory Block Diagram

MOL AND
CONTROL

J
MPO

MX15-A
MPI

MP2

MOL AND/
CONTROL

MP3
MOL AND
CONTROL

I
MEMORY
PORT
SWI TCH
OMA
DEVICE
IPU

CPU

KP15
15- 0388

Figure 1-3

Direct Memory Access Block Diagram

1-3

METHOD 1 METHOD 2 -

BANK 10
BANK 11

BANK 01
BANK10

BANK OO(B)
BANK 01

MDL AND
CONTROL

BANK OO(Al }AS SELECTED BY BANK
SELECT SWITCHES ON
BANK 00
REAR OF MM15
8K

MPO

MPI

MP2

MP3

IMDL AND CONTROL

MDL AND CONTROL

I
MEMORY
PORT
SWITCH
IPU

MEMORY
PORT
SWITCH

CPU

IPU

KPI5

CPU

KP15

METHOD l' MP3 ROTATED 24K
BANK SELECT BITS
MP2

MP3

MPO

PHYSICAL BANK SELECTED

NONE

OO(A)

OO(B)

NONE

METHOD 2' MP2 ROTATED 8K
BANK SELECT BITS
MP2

MP3

MPO

PHYSICAL BANK SELECTED

NONE

15-0389

Figure 1-4

Multiprocessor System Block Diagram

1-4

In multiple processor systems, MX15 equipment bays are located between the processors (if there are
two) with no other bays between processors. In 3-processor systems, care must be taken to keep the
longest memory bus length below the maximum length allowed.

1.2.1.2 Memory Bus Loading - A PDP-15 memory bus can accept as many as four loads. An MX15-A
is considered one load, as is an MM15. Thus, electrically, a PDP-15 memory bus may be connected
to any combination of four MM15s and MX15-As.

1.2.1.3 Addresses of MM15 Attached Directly to Processor Bus - Banks of core memory (MM15s)
attached directly to a processor bus can only have addresses in the lowest block of core (block OO).

1.2.1.4 MX15-A Output Bus Loading - The MX15-A can drive as many as four PDP-15 memory bus
loads. Because each MM15 is one load, the MX15-A can drive 32K of core.

1.2.1.5 Block Number of a Bank Attached to an MX15-A - The block number of a bank (MM15)
attached to the output bus of an MX15-A is determined by the MX15-A. Block numbers are specified
by MDL bits 01 and 02. Each MM 15 attached to an output bus can be addressed as any block number (0
through 3) independent of the block number the other banks of memory attached to that MX15-A
respond to. Each input port having access to that bank can, in addition, address the bank with its
own block number. In summary, each input port can address a fixed bank of core attached to an
MX15-A with a block number that is independent of the block numbers other ports addressed it and
the block numbers of the other banks attached to the MX15-A.
The method of selecting block number is described in Paragraph 2.4, Selecting Block Numbers (M628
Jumpers). The physical process consists of cutting jumpers on the M628 modules in the MX15-A.

1 .2.1.6 Bank Numbers of MM15s Attached to MX15-As - Each bank attached to the output bus of
an MX15-A must have its bank select switches set to a unique number: one bank 00, one bank 01,
one bank 10, and one bank 11 attached to a given MX15-A.

1 .2.1.7 Bank Disable (SELECT) - An input port can be prevented from using any combination of
MM15s attached to an MX15-A. The bank select switches associated with each port on the MX15-A
prevent illegal use. Each input port has four bank select switches, one for each bank (00, 01, 10, 11).
By setting a bank select switch to its zero position, the port associated with that switch will be

1-5

prevented from using the MM15 whose bank switches are set to the same number. For example, if the
bank 10 switch associated with memory port 3 is set to zero, then memory port 3 is prevented from
reading or writing in the bank whose switches are set to 10.

1.2.1.B Bank Rotation - In multiprocessor systems using the MX15-A, each processor must have its
own unique bank 00. ConsequE'ntly, the MX15-A has the capability to rotate the bank addresses it
receives before transferring them to individual memories. Each memory port has two bank rotate
switches that can add BK, 16K, or 24K to the address it receives. All addresses received by that port
are rotated the amount set on the bank rotate switches. The rotation is always within a given block.
The rotation logic does not propagate carries from memory address bit 03 to memory address bit 02.

1 .2.1 .9 Address Restriction - When configuring mul tiprocessor systems, only one bank must respond
to each address sent from a processor. Also, the user must make certai n that the address space of
each processor is contiguous.

1.2.1.10 Order of Filling MM15 Slots in MX15 - The MM15 slots in the MX15 must be filled from
bottom to top. No blank slots may be left between MM15s because the MM15XD designation numbers
include cables that assume the MM15 slot, just below the one to be filled, is already filled.

1 .2. 1 • 11 Cabl e Length Limitation - The PDP-15 memory bus cabl e is designed to operate satisfactori Iy
at a I ength of 21 ft. This length must not be exceeded. Figure 1-5 shows five different buses that
constitute a 12BK PDP-15 System that includes the BB15 option.

1 .2.1. 12 Indicator Bus Restriction - The MMA {memory address} and MMB {memory data} register
positions on the indicator bus have several limitations on MX15-A Systems that are not present on
normal PDP-15 Systems. In single-processor systems, these positions contain the inclusive OR of the
contents of the MMA and MMB of all the memories. This will be the OR of the last memory operation
to each MX15-A, because the MMB and MMA retain their contents until the memory is addressed
again. Hence, the MM15s change their MMA and MMB by "MX15-A blocks", and one set of ADDRESS
and DATA will be present for each MX15-A on the bus. In multiprocessor systems, the MMA and MMB
positions reflect the operations of the other processor, if it is running. It is not possible to examine
the MMA and MMB unless both processors are hal ted. These I imitations can be partly overcome by
carefully configuring the indicator buses in multiprocessor systems and by making deposits of 0 to
location 0 of each MX15-A block of core not of interest.

1-6

MEM

0----

17fl - - - - - - - - . . - 1 " 1

I+--1

I
I
I

0-----0----0--0

1---6fl---l

I
I

I
MX
I

MX
2

MX
4

o----~o-------~~

8815

20fl

.. :

I
I
I
I

MEM MEM MEM MEM

0----0------0--

1 - - 6 fl -----I

MEMMEM MEM MEM
0----0--0---0-1

I--- 6 fl ----I

15 - 0390

Figure 1-5

128K CP/Memory Cable Lengths

When a processor is turned off, all memory lines go to their true level of ground, including PWR CLR
(power cl ear to the memory). Therefore, the MMA, MMB, and MST indicator positions return to a
cleared state at the end of each memory cycle.

1 .2.2 Multiprocessor System Rules
The PDP-15 IPU logic system is designed to operate with the increased delays caused by the MX15-A.
Certain configurations of large mul tiprocessor systems with many peripherals can congest the I/O bus.
Note that a second processor using memory and using the same MX15-A as the IPU must be considered
as an I/O device when calculating latency and I/O bus utilization.

1 .2.2.1 MX15-A Priority Types - The MX15-A honors requests in the order in which they occur,
except if two or more requests occur simultaneously or are waiting at the end of the current cycle,
a hardware priority feature gives memory port 1 service before memory port 2, and memory port 2
before memory port 3.

1 .2.2.2 Processor Bus Priority - A processor connected to several MX15-As may have its bus connected into a different priority port in each MX15-A. Thus, a given processor can have higher
priority access to some memory and lower priority access to other memory.

1-7

1.2.2.3 Proper Port Connection for PDP-15s - A PDP-15 that can process DCH or back-to-back
sing le-cycl e I/o breaks, must be connected to port 2 or port 3. Each of these ports has special logic
that detects a special memory bus signal, which gives the I/O sequence absolute priority when it is
initiated. Consequently, when a three- or four-cycle break is initiated in port 3 for example, neither
port 1 or port 2 can interrupt it until the entire break is completed. This is a requirement for the
PDP-15 I/o processor. A PDP-15 must not be connected into port 1 unless no I/o activity other than
"single" single-cycle breaks is expected.

1 .2.2.4 Direct Memory Access (DMA) Port - Port 1 is designed for use with custom equipment, e.g.,
the DMA channel. With careful programming, the DMA facility can be used concurrently with the
processor with no cycl e steal ing. Other ports can also be used for DMA channels. For a further explanation see the detailed discussion of Direct Memory Access in Chapter 5.

1 .2.2.5 Power Fail Protection Configurations - The logic associated with memory power failure is
designed to notify all processors, connected to the particular MX15-A whose memory is issuing the
memory power fail ure signal, that a power fail ure has occurred. Consequently, in systems where the
user must be abl e to turn off power on any processor without affecting the rest of the system, only
PRIVA TE memory can be located in a processor cabinet where it is powered by the processor power
supply. All shared memory must be located in independently-powered MX15 cabinets. A power failure in any memory attached to a given MX15-A is sent to all processors connected to the MX15 multiprocessor system. Thus, in a PDP-15, a power fail signal in a shared memory will power down all
processors connected to it.

1.3 MX15-A SPECIFICATIONS
1.3.1 Physical
MX15-A
Dimensions:
Width
Height
Depth

19-1/8 in.
5-2/8 in.
7-2/8 in.

Mounting Space: 5-2/8 in. of rack space
Finish = Aluminum conversion (Chromicoat)
MX15 Bay
Weight - 500 Ib

1-8

1 .3.2 Environmental
Recommended Ambi ent:
Temperature - 70° to 85°F
Humidity - 30% to 80%
Factory Tested Ambient:
Temperature - 50° to 122°F
Humidity - 20% to 90%

1 .3.3 EI ectrical
1.3.3.1 Power
MX15-A

4.4A @ +5V

MX15 Bay implemented with 32K of memory

lOA @ 117V 60 Hz
5A @ 240V 50 Hz

1 .3.3.2 Delay and Cycle Times
Circuit delay in MX15-A
Typical
Worst Case

240 ns
300 ns

Cycle Times of PDP-15 Systems with MX15-As are as follows:
Cycle

No Option

KM15

KM15andKTl5

READ

1080 ns

1120/1120 ns

1150/1160 ns

WRITE

1105 ns

1120/1230 ns

1150/1260 ns

1.3.3.3 Latency - Memory access time in the MX15-A varies from 730 ns to 5.06 jJS. See Paragraph 5.1.2 for a detailed explanation of the latency specifications of the MX15-A and the latency
for different system states.

1.4 EQUIPMENT SUPPLIED
The MX15-A is mounted in a standard H963 19-in. equipment bay with as many as four MM15XD core
memory banks and all necessary power supply and power control circuitry. Two MX15-As can be installed in one equipment bay. Any configuration within the limitations specified above can be created
and designated an MX15 equipment bay. Typically, three MX15s are required to assemble a maximum
configuration. The power supplies and control units included in an MX15 equipment bay are powered
for maximum utilization, and all the modules comprising an MX15-A are listed in Table 1-1. The

1-9

MM15XD modules are not listed in this table; they are described in the PDP-15 Maintenance Manual.
The MM15XD core memory banks located in the MX15 equipment bays differ from the banks (MM15-A
and MK15-A) located in the KP15 equipment bay in that the MM15XD banks use a G829 +5V power
connector module instead of a G821 +5V regulator module. This difference exists because regulation
of the +5V power in the MX15 equipment bay is controlled by the power supplies.

Table 1-1
Equipment Supplied

Name

Type/Part No.

Quantity

MX15

Multiplexer Equipment Bay

3 (max)

MM15XD

Core Memory

4 (max per bay)

MX15-A

Memory Multiplexer

2 (max per bay)

G827

Power Sequence Detector and Delays

G829

Power Connector

M111

Inverters

M133

NAND Gates

M135

NAND Gates

M139

NAND Gates

M311

Tapped Delay Lines

M312

Delay Lines

M602

Pulse Ampl ifiers

M622

I/o Bus Drivers

M627

NAND Power Ampl ifiers

M628

Block-Bank Address Card

M902

Terminator Card

6 (max)

M904

Coaxial Cable Connector

14 (max)

M911

Memory Bus CP Terminator Card

6 (max)

W714

Switches

841-B

Power Control

H721

Power Supply

798-A

Power Supply

856

Power Control

7006862-0-0

Flat Coaxial Cable (13.25 in.)

12 (max)

BC08B-1

Flat Coaxial Cable (l ft)

6 (max)

1-10

Table 1-1 (Cont)
Equipment Supplied

Name

Type/Part No.

Quantity

BC08B-2

Flat Coaxial Cable (2 ft)

22 {max}

BC08B-3

Flat Coaxial Cable (3 ft)

12 (max)

BC08B-7

Flat Coaxial Cable (7 ft)

2 (max)

7006414-1

Cable (8 in.)

6 {max}

7006414-2

Cable (6 ft)

7006437-2

Dual Mylar Cable (2 ft)

3 (max)

7006437-6

Dual Mylar Cable (6 ft)

7006437-10

Dual Mylar Cabl e (lOft)

BC08A-*

MX-A Input Port Cables

1.5 REFERENCE DOCUMENTS
The complete set of PDP-15 manuals are identified and described in the family tree and accompanied

I isting in the front of this manual. In addition, the following diagnostic programs are essential to
establish the performance of the MX15 equipment bays. Only the last program is supplied with an
MX15-A System and then only if the system exceeds 32K.
Memo ry Add ress

MAINDEC-15-DOCA-D(D}

Extended Memory Address Test

MAINDEC-15-DIFA-D(D}

Memory Checkerboard Test

MAINDEC-15-D1AO-D(D}

External Memory Checkerboard Test

MAINDEC-15-D1 BB-D(D}

Extended Memory Key Instructions,
PI, A PI, and Auto Index Test

MAl N DEC-15- D1C B- D(D)

MX15 Memory Multiplexer Test

MAINDEC-15-D1 MA-D{D}

1-11

CHAPTER 2
INSTALLATION

Basic PDP-15 installation information such as unpacking, special handling, inspection, and mounting
procedures is contained in the PDP-15 Installation Manual. Information related to the MX15-A is
incl uded in this chapter.

2.1 SHIPPING CHECK LIST
The following list of items should be included with your MX15. Any shortages should be immediately
reported on the DEC Customer Acceptance form (DEC-12-1015).
A.

DOCUMENTATION
MX 15 Maintenance Manual (Engineering Specification Part B)
D-UA-7006863-0-0
D-UA-H963-N
A-ML-MX 15-A
D-UA-841B
D-CS-H721-0-1
B-CS-798-0-1
B-CS-856-0-1

MX 15 Maximum Configuration
H963-N Cabinet Assembly
MX 15-A Logic Assembly
841-B Power Control
H721 Power Supply
798 Power Supply (798-A in 50 cycle systems)
856 Power Control (see Figure 7-1)

CABLES
7006437-10 fl exprint cable (indicator bus)
2

FUSES, SPARE
5
5
5
5

BC08B-* flat coax cables (min). The appropriate length can be determined
by bay location in the system configuration.

AGC 3
AGC 5
MDA 12
GBB 25

MODULES, LOOSE
The M902 and M911 modules, not used in the MX15-A configuration, are shipped
with the equipment as a maintenance aid.

2-1

FILTER
H950S Filter

DIAGNSOTICS
(Systems with greater than 32K only)
DEC-15-D1MA-D{D) MX15 Memory Multiplexer

2. 1 • 1 Customer Acceptance Procedure
The following acceptance procedure is designed to demonstrate that the MX15-A is operating correctly.
Several specific tests are described that relate directly to the MX15-A. However, no diagnostic will
confirm that the MX15-A is operating correctly, because the MX15-A is "transparent" to the processor.
Thus, the correct functioning of the total system demonstrates the correct functioning of the MX15-A.
The procedure duplicates steps previously performed at the factory.
CAUTION
Make certain that all modules and memory core stacks
are firmly seated before turning on power.

POWER UP/DOWN

Turn the power 0 FF and then 0 N in the MX 15-A option.
Simultaneously, depress STOP and RESET on the PDP-15 console.
It must be possible to deposit and examine the core attached to
each MX 15-A.

BANK SELECT

One at a time, set the bank sel ect switches to 0; with the switch
in the 0 position, the processor associated with the corresponding
input port must not be able to either write into or read from that
bank.

BANK ROTATE

Set a unique number into any location of each bank. Read from this
location with the bank rotate switches set for 8K, 16K, and 24K.
NOTE
For systems equipped with greater than 32K of core memory ,
the system must pass the MX15 Memory Multiplexer Test.

2.1.2 Multiple Processors
With multiple processors, the priority arrangement of the MX15-A can be confirmed by keying aJMP.
instruction into the memory, from the console. Both processors should simultaneously execute theJMP.

2.2 MX15 CONFIGURATIONS
The design of the MX15 enables a variety of configurations to be created, each custom built for a
customer's specific need. A maximum system configuration is illustrated in Figure 2-1. Figure 2-2

2-2

H963

FANS

MM15XD
8K MEMORY

FANS

MM15XD
8K MEMORY

FANS

MXI5-A
MULTIPLEXER

BLANK

MXI5-A
MULTIPLEXER
BLANK
15-0410

Figure 2-1

Maximum System Configuration Diagram

locates the modules within the MX1S-A (viewed from the module side). Each MX1S equipment bay
can contain as many as four MM1SXD core memolY banks and one MX1S-A multiplexer.

Equipment

bay 1 is equipped to handle one additional multiplexer. In addition, each equipment bay contains
all the power supply and power control equipment required to power the MM lSXD memory banks and
MX1S-A multiplexer. Power supplies are installed only to the extent needed for the amount of memory
ordered.

2.3 CABLING
All interconnecting cables required for a customer1s installation are supplied with the equipment.
Cables for connecting a customer-supplied DMA device must be ordered separately. There are two
additional BC08B-* cables (per MX1S-A) required for connecting this device. The cable complement
for a maximum MX1S configuration is listed in Table 1-1 of Chapter 1. For specific cabling informaNon, refer to drawing D-UA-7006863-0-0 in Chapter 6.
NOTE
The end of a memory bus must be terminated with M902
modules. Unused input ports must be terminated with
M911 modules.

2-3

CABLES BC08A-* FROM KP\S
OR
TERMiNATE WiTH M911
r -________________

~A~

MP3

MP2

MPI

CABLE BC08B-X FROM MMI5

________________

CONT

MOL

M311

Mil \

M602

M627

Mill

M904

M904
OR
M911

M904
OR
M91\

M904
OR
M911

M622

M904

M628

W714

M628

W714

W7\4

M628

W714

G827

MI35

MI33

M312

Mill

M904
OR
M902

M622

M911

M627

I M133

MI39

M139

MI39

M139

CONT

MOL

CONT

MOL

CONT

MOL

~-----------------vr-----------------TERMINATE WiTH M902 OR CHAIN TO
NEXT MXI5A WITH M904 (CABLE BCOBA-*)
iF CABLE is iN SLOT ABOVE,OTHERWiSE
LEAVE SLOT BLANK.

W714

G829

M139

G829

~
TERMiNATE WITH M911

Figure 2-2

MX15-A Configuration Diagram
2-5

2.4 BLOCK AND BANK ASSIGNMENTS
After a system is installed and before power is turned on for the first time, block and bank numbers
must be assigned to the memory. These numbers can be assigned by physically cutting jumpers in the
M628 modules of the MX15-A, setting switches on the W714 and M628 modules of the MX15-A, and
setting switches on the W714 modules of the MM15XD.
NOTE
In factory-assemb I ed systems, these operations have been
performed to customer spec ifi cations.

Three M628 modules and six W714 modules are contained in each MX15-A. One M628 module and
two W714 modules provide the block and bank address identity for each input port. Cutting specific
combinations of jumpers (see Figure 2-3) in the M628 module causes the corresponding input port of
the mul tiplexer to respond to one or more block address.
Normally, the jumpers are cut so that a given input port of the multiplexer responds to only one block
address. However, in some configurations it may be necessary to have the MX 15-A respond to more
than one block address. If a bank does not exist on a particular MX 15-A, cut all four jumpers.
The BANK ADDR ROTATION switches on the M628 module (see Figure 2-4) should be set to 0, unless
the memory bank address bits are to be altered for the corresponding input port. If all memory banks
are to respond to a specifically addressed port, the BANK SELECTION switches should be set to 1.
Those switches that correspond to a nonexistent bank or to a private bank for anothe:- processor must
be set to O. The memory BANK SELECTION switches in the MM15XD must also be set so that each
bank wi II respond to a different address, starting with 00 to ensure contiguous addressing. This procedure is described in the PDP-15 Operator's Guide.

2.5 CONNECTION OF JUMPER WIRES IN WIREWRAP FIELD
Jumper wires are used in the wirewrap field to disable unused input memory ports. To prevent the
MX15-A from IIlocking Upll when powering up, all memory ports that are not used in a particular
installation must be disabled. A memory port is disabled by preventing the REQ ACTIVE fl ip-flop
from being set (true).

To disable a memory port that is not in use, connect a jumper as listed below:

Memory port 1: pin B06P2 to pin B06 Tl
Memory port 2: pin B04P2 to pin B04Tl
Memory port 3: pin B02P2 to pin B02Tl

2-7

CONNECTOR END

t
UI

SI
RI
PI

,....

BANK 10

I
~

,...

,....

I
~

4
~

,....

P2
BANK II

,....

I
~

,..

TO BANK ADDR
DECODE GATES

,....

S2
BANK 00

3
~

,..

I
2

I
,...

U2
BANK 01

3
~

BLOCK*

00
01
10
II

JUMPER TO BE CUT
I AND 3
I AND 4
2 AND 3
2 AND 4

* IF A BANK DOES NOT EXIST,CUT ALL JUMPERS ( 1,2,3 AND 4)
15-0392

Figure 2-3

M628 Module, Block Select Jumpers

2-8

SWITCH FUNCTIONS MX15 MEMORY BUS MULTIPLEXER
INPUT MEMORY BUS 1
, BANK ADDR
ROTATION

INPUT MEMORY BUS 2

BANK SELECTION

BANK ADDR
ROTATION

BANK SELECTION

INPUT MEMORY BUS 3
BANK ADDR
ROTATION

BANK SELECTION

0 0 0 0
00

0
BANK
01

0
ADD 16K TO
ADDRESS

0
BANK

Q 0 0

0
ADD 8K TO
ADDRESS

0
BANK
10

() 0

0 0 0

0
ADD 16K TO
ADDRESS

0
BANK

0
BANK
01

0
BANK

0 0 0 G 0 0
,,-..-j"

0
BANK
11

Figure 2-4

0
ADD 8K TO
ADDRESS

0
BANK
10

0
BANK
11

0
ADD 8K TO
ADDRESS

0
BANK
10

0
BANK
11

M628 and W714 Modules, Switch Functions

2.6 ADJUSTMENT OF PRIORITY MARGIN IN MULTIPROCESSOR
AND DMA SYSTEMS
The alternating sequence of memory accesses is maintained by properly setting the TS01 in each
processor. The I ength of the TS01 is measured at pin E30K2 of the KP15 processor.

The TS01 is

adjusted by turning the potentiometer on the rear of the M775 module in slot E30 in the processor.

The margin available in the system can be checked by following the procedures outlined below.
Procedure

Step

Set both processors to a JMP. -1 in the bank at the end of the memory bus that services the processor bay.

Attach channel 1 of the oscilloscope to PRIORITY RESET (Pin A30F2)
in the MX15-A serving the processor cabinet.

Put the channel 2 probe on signal M REQ DL Y of the port being
checked.

Sync the oscilloscope to channell in the processor. The difference
in time from the trailing edge of PRIORITY RESET to the leading
edge of M REQ DLY plus 10 ns is the low side margin available in
the specific processor. The high side margin is determined by
factors in the processor. TS01 should be adjusted so that the margin
seen on the osc ill oscope is no I ess than 15 ns. However, TSO 1
should never be reduced below the nominal setting (260 ns) recommended in the PDP-15 engineering specifications.

2-9

2.7 POWER
Two primary power sources are available at each equipment bay: local and remote. Local power
enables the user to power-up each MX15 equipment bay, independently. Remote power is chained
from one cabinet to another and is controlled at the PDP-15 console. Each equipment bay contains
all the control circuits and power supplies to convert the local or remote primary ac power to the dc
voltages required by the MM15XD banks and MX15-As. Power is automatically turned on by a threestep sequence that stabilizes all power at the correct level. Interlock protection for overtemperature,
overvoltage, undervoltage, and overcurrent is also included in the power supplies. A simplified
block diagram illustrating the distribution of power within an equipment bay is shown in Figure 2-5.
For detailed information concerning distribution and control of ac and dc power, refer to the engineering drawings provided in Chapter 6.

NOTE:
THIS ILLUSTRATION SHOWS A MAXIMUM POWER SOURCE CONFIGURATION
IN AN MX15 EQUIPMENT BAY. FOR A SPECIFIC CUSTOMER CONFIGURATION,
ONLY THOSE POWER SUPPLIES REQUIRED FOR THAT INSTALLATION ARE
INCLUDED IN THE MX15 EQUIPMENT BAY.
15-0394

Figure 2-5

MX15 Power Distribution Block Diagram

2.7.1 Adjustments
Adjust the -15V power level of the H721 power supply to -13V as measured at the output connector.
This adjustment is accomplished by removing the top of the H721 power supply and adjusting R204,
which is the fourth potentiometer from the left. The +5V power level in the H721 is adjusted to +5V
measured on pin A2 of the logic. A screwdriver adjustment through the hole in the top of the H721
power supply performs this adjustment.

2.S FIELD ADD-O NS
2 .8. 1 Processor Status
A PDP-15 processor that has an MX15-A added to it must have its wirewrap fi eld updated to at I east
revision AJ. It must also include the following ECO (engineering change order). Without this ECO,
DCH and Real-Time Clock breaks may not function properly. The ECO consists of the following wiring
changes:
Signal

Pins

Action

KD06 STB MRLS DLY L

M1SVl - M12T2

delete

KP32 I/o MRLS ACK L

M1SS2 - M12T2

add

KD06 M1SL1

M1SL1 - L1SA 1

delete

KD06 M1SNl

M1SNl - LlSA 1

add

2. S. 2 Memory Status
A memory bank originally located in the processor cabinet can be relocated in an MX15 cabinet if
the following steps are taken:
Procedure

Step

Remove the GS21 module in slot A01 and B01, and replace it with
a GS29 module.

Be sure the GS22 modules in slots COl and DOl are revision F, or
later.

Before initial power-up of the relocated memory, adjust potentiometer R3 (the center potentiometer) on the GS22 module approximately five turns counterclockwise. Fail ure to make this
adjustment will cause the -15V fuse to blow because of the crowbar overvoltage protection in the GS22 module. After power is
appl ied, adjust R3 to obtain -6 Vdc output, as described in engineering drawing D-B5-MM15-0-20 in the PDP-15 Maintenance
Manual Engineering Drawings.

2-11

CHAPTER 3
OPERATION

There are no front panel controls or indicators on the MX15-A; consequently, there are no
conventional operating procedures. There are, however, switch modules in the MX15-A whose
switches must be properly set, and jumper wires in the wirewrap field that must be connected properly
when installing a system (refer to Paragraphs 2.5 and 2.6). These switches and jumper wires can also
be changed periodically to change the priority mode, to change distribution of the MM15 memory between two KP15 processors, or to create private banks in a multiprocessor system.

3."1 MEMORY DISTRIBUTIO N
Figure 3-1 illustrates three ways of distributing four banks of core memory between two processors.
The bank address rotation and the bank selection switches enable the user to create or change the
distribution. The switch settings required for the illustrated distribution, and the address of each
bank (as seen by the processor) is also shown in Figure 3-1. A private bank is created for the other
processor by not selecting the high-order bank associated with a specific processor.
These exampl es do not depict the only method four MM15s may be configured with two processors.
It is, however, a successful method for creating a physically separate bank 00 for each processor,

which is a necessary prerequisite for multiprocessor systems. A physically separate bank 00 is necessary because the first bank (bank OO) contains the PI, API, Data Channel, and Real-Time Clock
locations that must not be shared.

3.2 PRIORITY
The term IIpriorityll is meaningful only in a multiprocessor or direct memory access (DMA) configuration.
The equal priority mode enables two processors to equally share common core memory on a cyclestealing basis; this mode also enables a DMA channel to steal single memory cycles from the two processors. Because of the unique design of the PDP-15 IPU and the special logic included in memory
ports 2 and 3, back-to-back single-cycle I/O transfers from the processors connected to memory
port 2 or 3 will occur back-to-back, without processors connected to the other memory ports stealing
cyel es during the block transfer.
3-1

MEM BUS 2

MMI5s ON MXI5-A NO.1

MMI5 s ON MXI5-A NO.2

MEM BUS I

BANK

SEL

ROTATE

SEL

24K

00
01
10

00
01

16K

~ ~

16K

00
01

00
01
10

CZJ ~ ~

24K

[2fJ ~ ~
00

r] ~ ~
3

OUTPUT
MEM BUS

~
00

tOUTPUT
IMEM BUS

MXI5-A
NO.1

MXI5-A
NO.2

INPUT
MEM BUS I

INPUT
MEM BUS 2

PROCESSOR
NO.1

PROCESSOR
NO.2

INDICATES PROCESSOR NO.2.
ADDRESS IS ROTATED IN MXI5-A NO.1 FROM A TO B.
A IS THE ASSIGNED BANK ADDRESS.
PROCESSOR NO.2 ADDRESSES ARE NOT ROTATED
IN MXI5-A NO.2.

INDICATES PROCESSOR NO. I.
ADDRESS IS ROTATED IN MXI5-A NO.2 FROM A TO B.
A IS THE ASSIGNED BANK ADDRESS.
PROCESSOR NO.1 ADDRESSES ARE NOT ROTATED
IN MXI5-A NO.1.
15- 0395

Figure 3-1

Memory Distribution in Multiprocessor Systems

3-2

Similarly, DCH transfers will be completed without the processors connected to other memory ports
stealing cycles during the 3-cycle transfer. In other words, in the equal priority mode, back-to-back
single-cycle transfers and DCH transfers are communicated to memory in the absolute priority mode.

All other transfers have equal priority.

3-3

CHAPTER 4
PRINCIPLES OF OPERATION

Chapter 4 describes the internal operations of the MX15-A multiplexer. Block diagrams and
simplified diagrams are included in this chapter; detailed block schematics are included in Volume 2
(see drawings D-BS-MX 15-A-O-12 through 23). For information pertaining to the PDP-15 computer
system, such as a description of the address and data formats, memory cycles, or the KTl5 option,
refer to the PDP-15 Maintenance Manual.

4.1 BLOCK DIAGRAM ANALYSIS
A block diagram of the MX15-A multiplexer is shown in Figure 4-1. Each sheet illustrates a set of
bidirectional switches, address decode logic, and control circuits for one input port of the MX15-A.
Sheet 1 includes the control circuits common to all input ports.
Communication between processor and memory involves two types of data transfers: memory-to-processor
and processor-to-memory. In both cases, an address (in the form of a memory reference instruction) to
identify the desired core memory location must precede the transfer of data.
For the MX15-A to properly direct communication traffic between the processor and memory, it must
recognize whether the transfer is the address or the data and the type (direction) of data transfer.
The MX15-A must know the direction of the transfer because the data to be transferred can appear
either in the MO register of the processor or in the MB register of the memory. The MX15-A must also
know whether the transfer is an address or actual data so that the multiplexer will not alter the address
bits in the case of data transfers. Timing of the read, the write, and the read-pause-write memory
cycl es is shown in Figure 4-2.
The MX15-A remains idle until a memory request and an address is received and recognized by one
of the three input ports. The address is placed onto the memory data lines (MDL) by the processor.
This address is received by the bidirectional switches in the MX15-A, and if the address is not recognized, the MX15-A continues to remain idle. The block select jumpers, bank rotate switches, and
bank select switches are set when the system is installed to recognize a number of specified block and

4-1

ADDR TO MEM MPI

DATA TO MEM MPI
PTOMMPI
M TO P MPI
MRD MPO

1 MEM TO PROC

ADDR ACK MPO

I
I

DIRECTION

MEM BUSY MPI ---~
DATA ACK MPO

o PROC TO MEM

)------lR

PWR CLR MPI

PWR CLR

ADDR ACK MPO

1 EN DATA XFER

BLOCK XX

01
BLOCK
SELECT
JUMPER
NETWORK

MDL MPI
BITS 00-17
TO
PROCESSOR
NO.1

EN
DATA
XFER

BLOCK XX
BLOCK XX
BANK SELECT
R

BLOCK XX

0 EN ADDR XFER

BANK 00

MPI
BI-DIRECTIONAL
SWITCHES

MPI
DECODE
GATES

BANK ROTATE (16K)

BANK 10

+3V-o
MDL MPO
BITS 00-17
TO MEMORY
BLOCK XX

ADDR TO MEM
MPI

BANK 11

ALT 03

ALT 04

DATA TO MEM
MPI

'''----'REQ ACTIVE
MPI

BANK 01

2-BIT
ADDER

;'=~~':"':"'::"":::':""::-SH. 2

NO ADDR CLR
INHIBIT MPI

ALT 04

INHIBIT MP2

ALT 04

MEM REO MPO

FROM
SHEET 2
+3V-o
BANK ROTATE [BK)

ADDR
ACK
MPO

MRLS ACK MPO

PRIORITY RESET
ACTIVE

MEM REO DLY MPI
MEM REO MPI

REO MPX
I

125 NS

MEM REO MP2

MEM REO EN

MEM
REO
EN

50 NS
ACTIVE MP2

~_ _ _~_ _~E~N~D~M~E~M~R~E~O~_ _ _~R

L.-_ _.....J

MEM REO MP3

50 NS
ACTIVE MP3

5- 0396

Figure 4-1

MX15-A Block Diagram (Sheet 1)

4-3

ADDR TO MEM MP3

DI ATApl1 T: : : : : : ,
p
I
I

~I~~~~---------------------------------------------------------------------------------------------------------------M-E-M--TO--P-R-O-C--------------------~

MEM BUSY MP3 --------,
PROC TO MEM

MP3
P TOM

PWR CLR MP3
SEE SHEET 1
EN DATA XFER
BLOCK XX
01
BLOCK
SELECT
JUMPER
NETWORK

MDL MP3
BITS 00-17
TO
PROCESSOR
NO.3

BLOCK XX
BLOCK XX

BANK SELECT
EN ADDR XFER

BLOCK XX
BANK 00

TO SHEET 2

MP3
BI-DIRECTIONAL
SWITCHES

MP3
DECODE
GATES

BANK ROTATE (16K)

BANK 10
REO
ACTIVE
MP3

BANK 11

ADDR TO MEM
MP2

R
ALT 03
ALT 04

DATA TO MEM
MP3

' , , - - - ' ' ' ' , REO ACTIVE MP3

BANK 01

~::..::....:...:.::..:....:...:....=...""-"'-- SH. 1

ALT 03
2-BIT
ADDER

INHIBIT MP2

ALT 04
ALT 04

PRIORITY
RESET

MEM REO MPO

NO ADDR
CLR

~
SEE SHEET 1
+3V-{)
BANK ROTATE (8K)

ACTIVE

MEM REQ
DLY MP3
SEE SHEET 1

REO MPX
MEM REO EN
SEE SHEET 1 =---...:.------t
15-0~98

Figure 4-1

MX15-A Block Diagram (Sheet 2)

4-5

ADDR TO MEM MP2

AT:I T:O :E: p:P2
~M~T~0~P~M~P~2

I
I

__________________________________________________________________________________________________________________________________________~

I
I

MEM TO PROC

MEM BUSY MP2 --------,
PROC TO MEM
PWR CLR MP2
SEE SHEET I
EN DATA XFER
BLOCK XX
01
BLOCK
SELECT
JUMPER
NETWORK

MOL MP2
BITS 00-17
TO
PROCESSOR
NO.2

BLOCK XX
BLOCK XX

BANK SELECT
EN ADDR XFER

BLOCK XX
BANK 00

TO SHEET'

MP2
BI-DIRECTIONAL
SWITCHES

MP2
DECODE
GATES

BANK ROTATE ( '6 K )

BANK 10

+3V-0~

REO
ACTIVE
MP2

BANK 11

ALT 03

ALT03

ALT 03

ALT 04

2-BIT
ADDER

DATA TO MEM
MP2

.--------., REO ACTIVE MP2

BANK 01

ADDR TO MEM
MP2

o
;..:..=-=---'--------SH.3

INHIBIT MP3

ALT 04

PRIORITY
RESET

MEM REO MPO

NO ADDR
CLR

"---y--J

FROM SHEET 3

SEE SHEET I
+3V-o
BANK ROTATE (8K)

ACTIVE

MEM REQ
DLY MP2
SEE SHEET 1

REO MPX
MEM REO EN
SEE SHE E T 1 "---------------1
15-0397

Figure 4-1

MX15-A Block Diagram (Sheet 3)

4-7

M REQ

-----~

MRD
MWR
ADDR ACK
MRLS ACK
DATA ACK MRLS

------------~~~~~~-~---~~

------------------~~~--~

BUFFER
ACTIVE
M-P
DIRECTION
EN DATA

-------------~

P-M --------------------------~~
DATA
ADR -----------------------~

ADR-M
DATA-M
DATA-P

----------------------~

Figure 4-2a

15-0399

MX1S-A Timing Diagram

M REQ
MWR·
MRD
ADDR ACK
MRLS ACK

MRLS
BUFFER
ACTIVE
M-P
DIRECTION
P-M
DATA
EN DATA
ADR
ADDR-M
DATA-M
DATA-P

15-0400

Figure 4-2b

MX1S-A Timing Diagram

4-9

M REQ
MRD

ADDR ACK

__________

~-----------J

DATA ACK

----------~_r----------~~
MRLS ____________~----------+_----~~
MRLSACK ____________~~------_#------_r----~
ACTIVE
--------------~

M-P
DIRECTION
EN DATA

P-M -------------------~---'
DATA
r-------------~__,

ADDR ------------------~

ADDR-M
D~A-M _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _r___l~

__________

DATA-P

--------------------~
15-9401

Figure 4-2c

MX15-A Timing Diagram

bank addresses. When anyone of these addresses is received by the MX15-A, the REQ ACTIVE
flip-flop is set. Setting the REQ ACTIVE flip-flop initiates a timing sequence for generating a
secondary memory request signal for the core memory and enables the control circuits; consequently,
the address and the data can be orderly transferred through the multiplexer.
The secondary memory request signal is derived from the MEM REQ EN (memory request enable) and
the REQ ACTIVE signals. The MEM REQ EN flip-flop is set at the end of the previous memory cycle
by the MRLS ACK (memory release acknowledge) signal. Therefore, when the processor currently
accessing memory issues the next M REQ (memory request) signal, the MEM REQ EN fl ip-flop has
already been set. Setting an REQ ACTIVE fl ip-flop starts the sequence for generating the secondary
memory request signal and also inhibits the address decode logic for all three input ports for the duration of the memory cycle. If more than one input memory port receives a memory request at the time
the MX15-A is reset by the MRLS ACK signal, the corresponding REQ ACTIVE flip-flop will be set,
and the priority logic will pass only the higher priority request. After the secondary memory request
signal is issued by the MX15-A, the M REQ signal from the processor is terminated in response to the
ADR ACK (address acknowledge) signal from the memory. The termination of the M REQ signal causes
the MEM REQ EN flip-flop to be reset, thereby terminating the secondary memory request signal.

4-10

Two flip-flops are included in the control circuits: DIRECTION and EN DATA XFER {enable data
transfer}. Both of these fl ip-flops are in the reset state at the start of the memory request cycl e.
When these fl ip-flops are reset and when the REQ ACTIVE fI ip-flop is set, the address-to-memory
control signal is applied to the bidirectional switches. This signal causes the address on the input
memory bus MDL to be transferred to the output bus MDL and distributed to the core memory. The
address is gated through the multiplexer in this manner whether the subsequent data transfer is from
memory-to-processor or from processor-to-memory. If the memory responds with an ADR ACK signal,
either one or both of the control flip-flops (direction and enable data transfer) are set. The memory
replies with an ADR ACK signal only if the bank address is valid. One flip-flop, EN DATA XFER,
will always be set in response to an ADR ACK signal. Setting this flip-flop indicates the address
transfer is complete and a subsequent data transfer is beginning. The EN DATA XFER state is required
because address bits can be rotated; however, data bits must not be rotated. The direction of the
data transfer is determined by the state of the direction flip-flop. This flip-flop is set in response to
the ADR ACK signal only when a MRD {memory read} signal from the processor is present. The MRD
and ADR AC K signals are ANDed at the input of the direction fl ip-flop. If the MRD signal is present,
the fl ip-flop is set, and a memory-to-processor control signal is generated to gate the data from the
memory through the bidirectional switches to the processor. If, however, the MRD signal is not present,
the flip-flop remains in the reset state and generates a processor-to-memory signal, which in turn, produces the data-to-memory signal that gates data from the processor through the bidirectional switches
to the memory. To reset the multiplexer in preparation for the next memory request cycle, the
control and REQ ACTIVE flip-flops are reset, and the MEM REQ EN flip-flop is set by the DATA
AC K and the MRLS ACK signals. These signals are produced in indirect response to the ADR ACK
signal and are delayed until the data transfer is completed. The DATA ACK signal occurs before the
MRLS ACK signal and resets the DIRECTION flip-flop. The MRLS ACK signal is shaped, delayed,
and inverted in the multiplexer to provide an early and a late priority reset signal to reset the EN
DATA XFER and REQ ACTIVE flip-flops, and to set the MEM REQ EN flip-flop. The early or late
priority reset signal can be manually selected by specific jumper wire connections in the wirewrap
field; these jumper connections enable an equal or an absolute priority mode, respectively. The
equal priority mode affords interleaving access to memory by any two input ports.
An invalid memory address is indicated to the multiplexer when the memory does not respond with an
ADR ACK signal, which should occur in direct response to the M REQ signal. If no ADR ACK signal
is received by the multiplexer before the M REQ signal times out, a NO ADDR CLR (no address clear)
signal is generated to reset the REQ ACTIVE fl ip-flop and to set the MEM REQ EN fl ip-flop. The
M REQ signal is not removed unless the processor requesting memory is equipped with the memory
protect option that is included in the KT15 Memory Protect/Relocate option. Failure to remove the
M REQ signal causes the entire PDP-15 multiprocessor system, including the multiplexer, to lock up.

4-11

The RESET switch on the console of the processor requesting memory must be pressed to produce a
PWR CLR {power clear} signal for resetting the system. If the processor is equipped with the KM
Memory Protect option 1 the MEM REQ signal wi II be removed approximptely SOO ~ after it is passed
by the MX1S-A to the memory. The time is determined by setting a delay in the KM15 Memory
Protect option.

4.2 DETAILED CIRCUIT ANALYSIS
4.2. 1 Bidirectional Switches
All address and data transfers between processor and memory are accomplished via the bidirectional
switches in the mul tiplexer. The basic switch configuration for one bit is illustrated in Figure 4-3.
This switch configuration is used for transferring bits 05 through 17 of the address and the data. Two
other variations of this switch configuration are employed for transferring bits 00 through 04; these
bits are also used in the multiplexer to recognize and modify the address. The bidirectional switches
PROC TO MEM MPI

MDLXX MPO
~--""""---I------ MEM

MDLXX MPI
PROCNQ1~----~~-------------'

MEM TO PROC MPI

PROC TO MEM MP2

MDLXX MP2
PROC NO.2~----4---------'

MEM TO PROC MP2

PROC TO MEM MP3

MDLXX MP3
PROC NO.3~----4---------'

MEM TO PROC MP3
15- 0402

Figure 4-3

Bidirectional Sv.titch
4-12

for bits 00 through 02 respond to data transfers in both directions but do not transfer the address bits
to memory, and the switches for bits 03 and 04 incorporate a two-bit adder to rotate the bank address
prior to transfer. A detailed description of the two-bit adder and associated bidirectional switches
is presented in Paragraph 4.2.3. The bidirectional switches transfer the address and data in response
to multiplexer control signals and also provide sufficient drive for the processor and memory MDLs.

4.2.2 Address Decode Gates
The block and bank address are recognized in the multiplexer by combinational logic. The combinational logic includes four NAND gates for each input port. Each NAND gate responds to one bank
address (bits 03 and 04) and to the block address the bank is assigned (see Figure 4-4). Banks are assigned to a block on installation or in the factory by cutting two jumpers in a set of four. There is a
set of four.. jumpers for each of the four NAND gates; consequently, each bank connected to the multiplexer output port can be assigned to a different block. The address decode circuits for each input
port can be set up differently. The bank address can be rotated so that different input ports can access
the same memory bank using a different bank address. Rotation of the bank address is accomplished
by a two-bit adder that suppl ies the altered bank address bits to the address decode logic. By presetting
the two-bit adder using the bank rotation switches, the bank address bits on the MDL can be rotated
8K, 16K, and 24K.

4.2.3 Two-Bit Adder
The two-bit adder presents the altered bank address bits to the address decode logic of the multiplexer
and also to the memory output bus (MPO) via the associated bidirectional switches. A simplified logic
diagram of the two-bit adder and the associated bidirectional switches is shown in Figure 4-5. The
gates comprising the bidirectional switches are: A and B for bit 04, and C and D for bit 03. The
binary adders are connected in seri es with the cross-coupled bidirectional switches; therefore, the
altered bank address bits can be strobed onto the output memory bus (MPO) when an address is transferred to memory. Carries resulting from the two-bit adder are not propagated to address bit 02;
therefore, the operation is termed "rotation" rather than translation or shifting. When data is strobed
onto the MPO the binary adders are bypassed to transfer bits 03 and 04 unaltered.

4.2.4 Priority Control Circuits
The level of priority each input port assumes is determined by the output logic for the REQ ACTIVE
fl ip-flops. Figure 4-6 ill ustrates the output logic for these fl ip-flops. The Ievels of priority are
establ ished by the request active output logic because the REQ ACTIVE MP1 fl ip-flop inhibits the

4-13

MEM BUSY

MOL 01

MDL02

TO REQ
ACTIVE
FLIP-FLOP
JUMPER 2

FROM
BI-DIRECT SWITCHES

JUMPER 4

BANK ROTATE
ADD 16K

~
ALT 03
MOL 03

ALT03

BANK
SELECT

ALT 04
MDL04

ALT04

+3V
---0
BANK ROTATE
ADD BK
MOL BANK ADDRESS BITS
BANK ROTATE
16K BK

o
o

ALTERED BANK

~ ADDRESS BITS

15-0403

Figure 4-4

Address Decode Gate

4-14

M TO P

DATA TO MEM ______--.r-_
MDL03

ALT MOL 03

MOL 03

BANK

CARRY

MPI
MP2
OR
MP3

DECODE
GATES

MPO

MDL04
MOL 04

ALTMDL04
ADRTOMEM----~~

M TO P
15-0404

Figure 4-5

Two-Bit Adder

outputs of the REQ ACTIVE MP2 and MP3 fl ip-flops, and the REQ ACTIVE MP2 flip-flop inhibits the
output of the REQ ACTIVE MP3 fl ip-flop. When an REQ ACTIVE fl ip-flop is set, the address decode
gates for al I input ports are disabled for the duration of the memory cycl ei thus, no other REQ ACTIVE
flip-flops can be set. In equal priority mode, the multiplexer is cleared before the next M REQ is
received from the processor currently accessing memory, allowing a lower priority port to gain access
to memory. This sequence allows two processors to alternately access memory (cycle steal ing) on an
equal priority basis for all data transfers except the back-to-back single-cycle I/O transfers and DCH
transfers over the data channel. For back-to-back single-cycle I/O transfers and DCH transfers,
special logic in memory ports 2 and 3 detects signal DCH SYNC, which locks out other processors.
This logic is described in detail in Paragraph 4.2.5.

4-15

ACTIVE
REQ ACTIVE MP3

ACTIVE

PRIORITY RESET

MRLS
ACK
MPO

15-0405

Figure 4-6

Priority Control Circuits
4-17

4.2.S Inhibit Logic
The PDP-1S I/O processor must have continuous access to memory during its word count and current
address cycles. Continuous access is enabled by the inhibit logic shown in Figure 4-7. The INHIBIT
flip-flop is set in the following manner:
a.

DCH SYNC becomes true prior to the beginning of a memory cycle;

When the MX1S-A recognizes the correct address, MP* ACTIVE becomes
true; and

REQ MPX becomes true producing the AND condition that sets the INHIBIT
fl ip-flop.
NOTE
The INHIBIT flip-flop is set only after the MX lS-A has
processed the first of the sequential cycles. The INHIBIT
flip-flop is reset with ADR ACK. During every cycle,
ADR ACK tests the condition of SET INHIBIT to determine
if it is true; if it is false, the INHIBIT fl ip-flop is reset.

SET INHIBIT is not true during two conditions:
a.

The sequential transfer may have been completed, in which case, DCH SYNC
is not true, and

The MP* ACTIVE flip-flop is not true because the data cycle is from the processor
to a memory attached to a different MX1S-A. In both cases, the INHIBIT flipflop is reset.

The INHIBIT flip-flop is also direct reset by DCH SYNC becoming false. PWR CLR also resets the
flip-flop. The logic in Figure 4-7 is duplicated in the MX1S-A for memory ports 2 and 3.

NOTE
Normally the ADR ACK of the memory cycle following the
completion of the transfer clears out the inhibit logic. When
the inhibit logic is cleared following a transfer the processor
that has just completed an I/o transfer continues to hold
memory for one additional cycle.

SET INHIBIT

INHIBIT

REQ MPX
EN DATA XFER
SET INHIBIT
DCH SYNC

ADR ACK

PWR CLROUT
15 -0406

Figure 4-7

Inhibit Logic

4-19

4.2.6 M REa Logic Timing
The M REa signal and the proper address bits at an input memory port trigger the MX15-A to its active
state. After a delay to ensure proper operation of the priority network, the M REa signal is sent to
the memory. When ADR ACK is received by the processor, the processor sets its M REa signal false.
The MX15-A detects this change in condition and sets the M REa signal to memory false.
A timing and control flow diagram of the M REa signals is shown in Figure 4-8. The M REa signal
from a processor causes an REa ACTIVE flip-flop to be set in the MX15-A. An ACTIVE signal is
generated, which is delayed 100 ns and ANDed with M REa EN to become the MPO M REa to memory.
When the M REa signal at the processor becomes false, this condition is detected in the MX15-A
causing a 50 ns pulse in the MX15-A called END M REa L. END M REa L resets M REa EN, which
sets MPO M REa to memory false.

22 M REQ MPIL

- - - - - - - - - - - - 1 ~.--------------

(FROM PROCESSO,RF_)

;------4;
---11 --------------1:

;F-------------'~L__

13 M REQ MP2H _ _ _

13 M REQ DLY MP2H _ _ _ _ _

;1'-'

13 REQACTIVE MP2 (1) L
EARLIEST TIME

___________

__ L.I---.......I~---------__I:,F_<_ _ _ _ _ _ _ _ _ _ _ _ __

TYPICAL~
.
LATEST TIME A - - - - ; : : : : . . ._ _ _ _ _ _ _ _ _ _~: <

f----------------

15 ACTIVE H SEC~~~~~i5~e~
13 ACTIVE MP2 B (1) H

---------4-J - - ..I
-..I

DECISION FINAL IN MULTIPLE
PROCESSOR CONFIGURATIONS
ADDRESS ON
MDLS TO MEMORY _ _ _ _ _ _ _ _+-_ _ _---.

M REQ MPO L

(REQ TO MEMORY)

I.
------------1

TYPICALLY 200n5

14 M REQ H (A29Ell

__-l
__-..I...!h 40n5 WORST CASE

-I

"-...

1-----...,

~~--~-----

12 END M REQ L (A30L2)
16 ADR ACK NPO (1)

(ADR ACK TO PROCESSOR)
NOTE: MEMORY PORT 2 USED FOR ILLUSTRATION
15- 0407

Figure 4-8

Priority and M REa Timing

4-20

CHAPTER 5
DMA INTERFACE DESIGN

Chapter 2 of the PDP-1S Maintenance Manual describes the PDP-1S memory system. The chapter
contains a definition of the control signals on the memory bus, a description of the control logic flow,
and a description of the storage el ements in the memory control logic. The user must understand these
sections before proceeding.
Chapter S provides information for users who wish to connect their own devices directly to memory,
using one of the MX1S-A ports as a DMA channel.

S.l MX1S-A ADVANTAGES
S. 1 • 1 Transfer Rate
Transfer rates of 92S kHz are possible; transfers at this rate may be any combination of read and write
cycl es. The read/pause/write transfer rate depends on the time spent in the pause (or modify) state.
Rates exceeding 700 kHz are possible with conventional interfaces.

S. 1.2 Latency
The waiting time required to gain access to memory is based on the following assumptions:
a.

The processor is a KP1S equipped with KM1S and KT1S options.

The DMA device is assumed to have 12 ft of cable to the most remote MX1S-A,
and additional 12 ft to last memory (24 ft total device to memory length).

Times are specified as will appear on DMA to MX1S-A cable at the DMA interface
and do not include any buffer delay within the DMA device.

Read and Read-Modify-Write Cycles - leading edge of M REQ to leading edge
of RD RST measured at DMA interface. This is time to access a memory location.

Write Cycles - leading edge of M REQ to leading edges of MRLS ACK. This
is the time required to deposit a word in memory.

S-l

5.1 .2. 1 No Processor Activity to MX15-A of Interest
Read
M REQ - RD RST = 730 ns
Write
M REQ - MRLS ACK = 790 ns

5.1.2.2 Processor Activity Only (JMP. in user mode)
Read
M REQ - RD RST = 1.8 !.IS
Write
M REQ - MRLS ACK = 1.86 !.IS

5.1.2.3 Processor with DCH OUT transfer, DMA, WC, and CA all located in memory attached
to same MX15-A.
Read
M REQ - RD RST = 4. 13 !.IS
Write
M REQ - MRLS ACK = 4.2 !.IS

5.1.2.4 Processor with DCH OUT transfer, DMA, WC, CA, and DATA all located in memory
attached to same MX 15-A.
Read
M REQ - RD RST = 5.0 I.IS
Write
M REQ - MRLS ACK = 5.06 I.IS

5.2 SIGNAL TIMING CONSIDERATIONS
To start a memory operation, a 17-bit address must be placed on the MDLs, and MRD, MWR, or both
must be set true. A minimum of 50 ns after these signals are set true, M REQ can be set true. All
these signals must remain asserted until ADR ACK is received by the DMA device. The M REQ, address and MWR/MRD signals should be removed from the bus on the I eading edge of ADR ACK. ADR
ACK is received approximately 340ns after the MX15-Ahas accepted M REQ.

From this point on, each

type of memory transfer requires a slightly different communications sequence. If the cycle is a read
or read/pause/write cycle, the memory automatically sends RD RST to the DMA device, approximately
245 ns after sending ADR ACK. The leading edge of the RD RST should be used as a strobe to bring
data into the device. RD RST will be de-skewed from the data by a minimum delay of 50 ns. When

5-2

the DMA device has strobed in the data, the DMA device sends DATA ACK. If it is a read cycle,
MRLS can be sent simultaneously with DATA ACK. If it is a read/pause/write cycle, the DMA device places the new data on the bus after it has manipulated the data (no time limitation). A minimum
of 100 ns later, the DMA devi ce sends MRLS to the memory; the memory responds wi th MRLS AC K, at
which time, data can be removed from the bus, the MRLS can be directly reset, and the next address
can be pi aced on the bus.
If it is to be a write cycle, the data to be written into the memory can be placed on the MDLs
after ADR ACK and the address are removed from the MDLs. A minimum of 100 ns later, the MRLS
can be sent to memory, and the memory responds with MRLS ACK, at which time the data can be
removed and MRLS reset.

5.3 MISCELLANEOUS SIGNALS
The paragraphs below list a variety of miscellaneous signals used in the DMA bus.
M BUSY B

This signal is an intermemory communications signal and has no function
in a DMA interface.

M PAR

Parity is not offered with the MX15 option; therefore, this signal cannot
be used with a DMA interface.

M PYVR-OK

A ground on this signal indicates that the G829 module (in either one
of the memories attached to an MX15-A) has detected a power malfunction and has shut down memory power. This signal can be used to shut
down the DMA device.

PWR CLR

This signal goes to ground when power is removed from the DMA device.
The PYVR CLR signal should also be at ground until the DMA device is
stabilized when powering up. The MX15-A is designed to reject any
control signals that originate from a DMA device, when PWR CLR has
been grounded. The MX15-A resets .itself and the memory attached to
it to the idle state from PWR CLR, if the REQ ACTIVE flip-flop from
that port is set. If another REQ ACTIVE flip-flop is set, the PWR CLR
is inhibited.

5.4 BACK- TO-BACK DMA BREAK S
5.4. 1 Si ngl e Processor System
The PDP-15 processor is connected to memory port 3 on the MX15-A, and the DMA device is connected to memory port 2. Use the inhibit signal DMA SYNC (pin M2 on the control cable of the
memory bus) and referred to as DCH SYNC on the MX15-A prints. The DMA SYNC signal, unlike
the rest of the memory bus, has a high true value. To ensure back-to-back breaks, the DMA SYNC
should go high with the first address of the block sent to memory; however, if DMA SYNC does not
go high on the first address, it must go high no later than simulataneously with the MRLS of the first

5-3

cycle. DMA SYNC must remain high until the last cycle of the back-to-back set of breaks.
DMA SYNC is lowered with the leading edge of ADR ACK of the last cycle. See Paragraph 4.2.5
for a description of inhibit logi c in the MX 15-A.

NOTE
If a system contains several MX15-As, the back-to-back
guarantee only appl i es as long as the block addresses stay
in the memory attached to a single MX15-A. If an MX15-A
address boundary is crossed, the normal latency for the first
access to that MX15-A occurs. Subsequent cycles will be
back-to-back •

5.4.2 Dual Processor Systems
Memory port 1 must not be used for any DMA device that requires back-to-back facilities. Also,
PDP-15 processors that have either DCH or back-to-back I/O transfers must be connected to memory
ports 2 and 3.

5.5 WIRING GUIDELINES
The user must give careful attention to creating a solid ground mesh as described in Paragraph 5.3 of
the PDP-15 Systems Interface Manual. Each MDL or control line should be buffered, and an M510
Positive Receiver module should be used to obtain maximum noise margins. An M611 or M111 module
can be used with somewhat degraded noise margins but with less delay. The receivers should be
located as close as possible to the DMA/memory bus cable slot locations. Maximum cable length
from the DMA device to the furthest MX15-A is 21 ft. Custom interfaces to the MX15-A can be
easily designed from standard modules, connectors, cables, and power supplies available from DEC.
The PDP-15 Systems Interface Manual, PDP-15 Systems Module Manual, and the DEC Logic Handbook
provide extensive information on specific parts available.

5.6 MODULES FOR DESIGNING DMA INTERFACE
Table 5-1 lists a summary of modules useful in the design of a DMA interface. These modules are
described in detail in the PDP-15 Module Manual.

5-4

Table 5-1
Modul es for DMA Interface Design

Module Type

Description

M311 Tapped Del ay li nes

Contains two tapped delay lines. Each has a 250-ns
maximum delay, with taps every 25 ns.

M312 Delay lines

Contains six delay lines, including four 50-ns delays,
one 30-ns delay, and one 0-40 ns delay. These are
useful for setting timing within DMA interfaces and
providing skew between data and strobes.

M621 Data Bus Driver

An inverting driver that has two inputs. Ideal for
switching between address and data source registers.

M622 I/o Bus Driver

A noninverting driver, useful for control signal
driving.

M902 Terminator

Must be used to terminate both the MDl and control
cable at the MX15-A.

M911 Memory Bus CP
Terminator

Provides a source of current to both the M621 and
M622 open-co II ec tor dri vers •

G829 Power Connector

Provides power control and protection.

G827 Power Sequence and
Delays

Used to create a DMA PvVR-OK signal.

5-5

CHAPTER 6
MAINTENANCE

The maintenance procedures presented in this chapter are limited to those procedures required for
maintaining and testing the MX 15 multiplexer equipment bays. Procedures for maintaining the PDP-15
computer system are contained in the PDP-15 Maintenance Manual. The maintenance phi losophy to
be followed for the MX 15 should be preventive in nature, that is, an optimum amount of preventive
procedures performed on a routine schedule will eliminate many costly equipment breakdowns and
forecast impending fai lures before they occur. If a fai lure does occur, the modular design of the
MX 15-A minimizes repair and down-time.

6.1 PREVENTIVE MAINTENANCE
The MX15-A option contains no special mechanical devices and is housed in a standard PDP-15 equipment bay; only standard computer system maintenance procedures are required to ensure rei iable operation of the equipment. Troubles encountered in the MX15-A should be recorded in the established
PDP-15 maintenance log for future reference. ' Regular entries in the maintenance log of maintenance
performed, troubles encountered, and corrective measures taken can serve as a powerful tool in maintaining system reliability.

6.1.1 Voltage Checks
Diagnostic programs referenced in Paragraph 1.4 and power supply voltage checks should be performed
at regular intervals to verify proper operation of the MX15-A and associated core memory banks.
Power supply output voltages and tolerances are listed in Table 6-1. Because each equipment bay has
its own power supplies, the voltage checks must be performed on each bay. Perform the voltage checks
on the core memory banks in accordance with the PDP-15 Maintenance Manual.

6-1

Table 6-1
Voltage Tolerances

Voltage

Tolerances

+5V

±100 mV (output of G829)

+10.5V

±10%

-13V

±O.2V

-30V

±2.0V

-6V

±200 mV

-25V (Memory +V and -V)

±1.0V

6. 1.2 Margin Checks for Mul tiprocessor and DMA Systems
Periodically check the equal priority margins to confirm that margins exist as described in Paragraph
2.6.

6.2 CORRECTIVE MAINTENANCE
The simpl icity of the MX15-A multiplexer and the logic description provided in this manual, in addition to the results of the diagnostic tests, normally permit the use of standard troubleshooting techniques
for isolating a malfunction quickly and efficiently. If the priority circuits of the MX15-A multiplexer
are suspected to be the malfunction, perform the multiple port jumping test described in Paragraph
6.3.3.1 to verify the operation of these circuits.

For economical maintenance under most conditions,

replace the inoperative module with a spare module, and return the defective module to DEC for repair or replacement.

DEC offers an optional spare modules kit containing one spare of each infre-

quently-used module and two of each frequently-used module. Recommended spare modules are listed
in Table 6-3. All modules except the DEC type M628 are included in the basic PDP-15 computer
spare modules kit; therefore, the M628 module should be considered as an additional spare requirement for an MX15 installation.

6.2.1 Test Equipment Required
Maintenance activities for the MX15 require standard hand tools, test cables, and probes and the
standard test equipment and special materials listed in Table 6-2.

6-2

Table 6-2
Test Equipment Required

Manufacturer

Designation

Multimeter

Tripi ett or Simpson

Model 630- NA or 260

Osci Iloscope

Tektronix

Type 453 or equivalent

Probe (2)

Tektronix

P6010

X10 Probe (2)

Tektronix

P6008

Module Extender

DEC

Type W982

Equipment

6.2.2 Specific Troubleshooting Techniques
If a malfunction occurs in the MX15 system, the following paragraphs can be used as guidelines for
tracing and isolating the malfunction.

6.2.2.1 Checking Priority Multiple Port Jumping Test
Step

Procedure
Connect PDP-15 computer system as shown in Figure 6-1.

Connect the oscilloscope to monitor the output of the REQ ACTIVE
MP1 gate.

Set the address and data switches on one console to access memory
and to start a jumpself loop or a short program (JMP . -1). ACTIVE MPl
should become high.

Connect the oscilloscope to monitor the REQ ACTIVE MP2 gate.

Set the MP1 Bank Select switches on the MX15-A to O. ACTIVE
MP2 should become high.

Connect the oscilloscope to monitor the REQ ACTIVE MP3 fl ip-flop.

Set the MP2 Bank Select switches on the MX15-A to O. ACTIVE
MP3 should become high.

6.2.2.2 Indications of Cable Problems - The most common cable fault is an open connection.
Generally, a single wire will open. If an MDL cable opens the indications of a malfunction are:
a.

a given bit position (both address and data) will always be read into the MMA and
MMB as a 1 (as seen on the indicator bus),

when the location is read, the MB on the console will show a 0 in that bit position.

A grounded cable connected to the processor is indicated by a 1 that cannot be cleared from the
MDL Iines (as examined on the indi cator bus). Opens and shorts on the control Iine cable are more
difficult to detect.
6-3

MM15

BCOSB-l,2 OR 7

All

AI2

' - - - - - - - MPO - - - - - - '

B09

REQ ACTIVE
A17M2 (MP1)
A 19M2 (MP2)
A21 M2 (MP3)

MX15-A

~--- M P I - - - - - .

~----MP2-----'

~------MP3--------~

OUT

SCOPE

KP15

15 - 0408

Figure 6-1

Multiple Port Jumping Test Interconnections

6-4

6.2.2.3 Indications of Driver/Receiver Malfunction - A malfunction in the drivers is usually an
open, i.e., the driver can no longer pull the bus to ground. When a driver in the processor-to-memory
direction is defective, it is indicated by:
a.

the MMB and MMA in the bit position is always a 0, regardless of what is attempted
to be deposi ted,

the contents of the MB will also be a

when the location is examined.

A driver in the memory-to-processor direction that is open has the following characteristi cs:
a.

MMA and MMB always obtain the correct data and address, however, when the
location is examined, the MB receives a at the bit position.

Failures in the control signal drivers are more difficult to trace.

6.2.2.4 Add-to-Memory and Read Modify Write RMW Mal functions - Because the real-time clock
uses the RMW cycles and the add-to-memory feature, the real-time clock is a convenient test feature
for examining any problems that may occur with add-to-memory, word count, and current address
cyc I es of DC H breaks.

6.2.2.5 Processor-Memory Lockup - The MST, MDL, MMA, and MMB positions on the processor
indicator bus can be used to determine the state of the memory and processor. Monitoring these four
positions can provide extensive troubl eshooting information.
NOTE
Ensure that these four positions do not contain the OR of
several memory blocks {refer to Paragraph 1.2.1.12}.
To troubleshoot the MX15-A, the procedures below should be followed:
Procedure

Step

Examine the ACTIVE MP* signal for the memory port in question.

Check the M REQ signal from the processor at the input and output
to the MX15-A.

Check ADR ACK {on the MST position}.

Check the MRLS and MRLS ACK •

A complete understanding of the control logic in this manual will aid in tracing problems.

6.3. SPARE MODULE REQUIREMENTS
Table 6-3 lists recommended spare modules for the MX15-A. The logic layout of the MX15-A is
sectionalized so that certain modules are used only with a single memory input port. If the port is
6-5

not used in a particular system, then the set of modules exclusively associated with that port can be
temporarily removed and used as spares, as needed for the other two ports in the MX15-A. The table
indicates the modul es that can be used as spares if memory port 1 is not used.

Table 6-3
Spare Module Recommendations

Recommended Spare Ivbdules for MX15-A

6.4

Type

Quantity

G827
G829
Mlll
M133
M135
M139
M3ll
M3l2
M602
M622
M627
M628
M902
M91l
W714

1
1
1
1
1
1
1
1
1
3
1
1
1
1
1

Spares Available if Memory Port 1 is Not Used
Quantity

Location

B06, B07

A l5,A20 ,A2l

Al0

1
2

A26 or B26
A08, A09

ENGINEERING DRAWINGS

A complete set of MX15 Memory Bus Multiplexer enginerring drawings is provided in Volume 2 of this
maintenance manual. These drawings are under DEC revision control and are updated as required by
ECOs (Engineering Change Orders). The Drawing Index List, Table 6-4, lists all the drawings that
are inc luded in Vol ume 2 in the order that they appear.

Table 6-4
Drawing Index List
Size

Type

Number

Title

7006863-0-0

MX 15 Maximum Configuration

MX15-0-0

MX15 Assembly

MX15-A-12

Priority Logic Input Port 1

MX15-A-13

Priority Logic Input Port 2

MX15-A-14

Priority Logic Input Port 3

MX15-A-15

MDL 03, 04 Drivers, M REQ Logic
(continued on next page)
6-6

Table 6-4 (Cont)
Drawing Index list
Size

Type

Number

Title

MX15-A-16

Control Li nes

MX15-A-17

MDL 0-8

MX15-A-18

MDL 9-17, Parity

MX15-A-19

Inhibit Logic

MX15-A-20

Memory Port Out

MX15-A-21

Memory Port 1

MX15-A-22

Memory Port 2

MX15-A-23

Memory Port 3

7006862-0-0

Wired Assembly (MX15-A)

841-B-0

Power Con trol 841 -B, 841-C

H721-0-1

H721 Power Supply Circuit Schematic

798-0-1

798 Dual 15-Vol t Power Supply Schematic

15-0409

856 Power Control

6-7

Digital Equipment Corporation
Maynard, Massachusetts