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EK-86XV1-MG-003

December 1987

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Document:	VAX 86XX System Maintenance Guide
Order Number:	EK-86XV1-MG
Revision:	003
Pages:	668
Original Filename:

OCR Text

EK-86XV1-MG-003

VAX 86XX System
Maintenance Guide

For Intemal Use Only

Prepared by Educational Services
of Digital Equipment Corporation

-First

Edition, December 1985
Second Edition, Septemhaesw 1986
Third Edition, March I¥87

U.S.A.

The reproduction of
prohibited.

For copy

Department,

Digital

01754.

1987 by Digital Eguifiment Corporation.

this material,
information,

in part or whole,

is strictly

contact the Educational Services
Equipment Corporation, Maynard, Massachusetts

The information in this document
is subject to change without

notice. Digital Equipment Corporation assumes no responsibil
ity
for any errors that may appear in this document.

The

following are

Maynard,

BhennEn

trademarks of Digital

Massachusetts.

DIBOL

Rainbow

DEC

MASSBUS

DECmate
DECUS

RSTS

PDP
P/0S

DECwriter

RSX
RT

Professional

UNIBUS

Equipment Corporation,

VAX
VMS
vT
Work Processor

CONTENTS

PREFACE

GENERAL

INFORMATION

Directory

Number.

Specifieéwthe top level directory number for system disks

with multiple

systems.

The

hardware or the CONSOLE program sets up the next
registers after a system crash or power failure:

R10

- halt

R1l1

- halt PSL

halt

<baseaddress

code
+

X200>

good

memory

CHAPTER
ERRORS

5.1

SYSTEM

FAULT

AND

ERROR ANALYSIS

ISOLATION

The information which follows is extracted
from
the
KA86
System
Fault
Isolation
Manual (EK-8600S-MM).
Refer to this manual for a
detailed description,

required.

The following
figure
shows
the
overall
organization
detection,
error
handling,
and
error
reporting
for
processor.
As shown in the figure, each box (MBox, IBox,

of
error
the
KA86
EBox, and

FBox)
has
1its
own
error
detection
network.
These
detection
networks constantly monitor for error conditions
and
report
them
directly
to the EBox (except for the SBIA).
The SBIA monitors for
external and internal detected errors:
external
detected
errors
are
reported to the EBox Interrupt Arbitration Logic, and internal

detected errors are reported to the MBox,

which sends them

the

EBox.

5.1.1

EBox Interrupt and Exception Arbitration Logic

All errors,

except

for MBox and EBox control store

parity

errors,

are reported to the EBox Interrupt and Exception Arbitration Logic.
This logic prioritizes the errors and generates a micro-trap vector
address
which
1is the starting address of a special EBox microcode
routine designed to handle error conditions.

5.1.2

Error Handling Microcode

(EHM)

The EHM reads the state of major CPU Control and
Status
Registers
and
places
the
result in the EBox Scratch Pad RAM.
This data is
referred
to
as
the
Machine
Check
Stack
Frame.
The
Interrupt/Exception
micro-routine
(not
shown) pushes the Machine
Check Stack Frame onto
the
interrupt
stack
and
calls
the
VMS
Machine Check Handler

5.1.3

VMS Machine

(MCHK).

Check Handler

The MCHK pops the Machine Check Stack Frame off the interrupt stack
and
puts
it
in
the System Event Buffer, queues the buffer to be
appended
to
the
System
Event
File
(ERRLOG.SYS),
and
either
Bugchecks or REIs depending on the severity of the error.

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ANV

ERRORS

AND ERROR ANALYSIS

SPEAR (Standard Package for Error Analysis and Reporting)

5.1.4

the contents of the System Event Files.

display

/r‘"

SPEAR is a maintenance tool designed to sort, analyze, and

Keep Alive Fail

5.1.5

(KAF)

The CPU has two KAF mechanisms; one

monitor

1is

the

used

console

operation of the CPU, and the other is used by VMS to

the

monitor operation of the console.

5.2

CONSOLE SNAPSHOT FILE INFORMATION

Upon detection of a Keep Alive Failure, the Console will read and
log the status of the machine into a snapshot file on the console
is transferred
Upon VMS system reboot, the snapshot file
RL0O2.
from the console to the system error log on the system disk. Since
not
does
(ERF)
the current system Error Reporting Facility
recognize the format of this snapshot error file, there are a
number of additional wutility programs that must be wused to
The following text
interpret and analyze the snapshot file.
describes how they operate and the flow chart which follows
illustrates the utilities.

NOTE

If you need to

decode/translate

that is on the RL02 disk, you can:

file

SNAPSHOT

which will transfer the
Reboot the system,
VSR may be
valid SNAPSHOTs to the system disk.
used to translate the SNAPSHOT.

and

Call the RDC and ask them to

Print the SNAPSHOT file using the Console
command “SHOW SNAPn.DAT" where n is 1 or 2.
Use the System Fault Isolation manual, Appendix

translate the SNAPSHOT.

5.2.1

dump

upline

to decode the conscle printout.

Guide to Decoding/Analysis of a SNAPSHOT

There is a command procedure that may be run which automatically
performs many of the functions shown on the chart. A simplified
Note that this
method using this command procedure follows.
procedure

assumes

that

you

have

programs and defaults to run VSRBLD.

reloaded,

the

set

already

snapshot

After VMS is

Rename the ERRSNAP.LOG;nn file to a

1is

wup the necessary

transferred

such

ERRSNAP.LOG;nn

LOG
FILENAME.

wunique

name

ERRORS

AND

ERROR ANALYSIS

From

the

$§

FIELD account,

enter

the

command:

@VSRBLD sysS$error:FILENAME.LOG

Either:
a.

Read

and

decode

FILENAME.SIG

VAX

the RDC and
analysis)

Reference

8600

the

output

FILENAME.REG;

Contact

file

5.2.2

and

request

FILENAME.HDR,

assistance

(for

Console

Software

Specification,

SNAPSHOT File

Flowchart

Revision

8.1

EK-8600S-MM

Notes

The following notes support the ’‘Console SNAPSHOT File
Flow Chart'.
The note number in brackets [n] refers to
numbers on the chart.
1.

Console

SNAPSHOT

Documentation

VSR Package Documentation
KA86 System Fault Isolation Manual,

5.2.3

files
or

RLO2

snapshot

files:

SNAP1.DAT

Information
the circled

and

SNAP2.DAT.

These
are
the
original
snapshot
files
as taken by the
console
hardware
upon
the
detection
of
a
Keep
Alive
Failure.
These files reside on the console RL02.
Refer to
KABb6 System Fault Isolation Manual for a description of the
format of these files.
Transferring
remote

the

remote

and

the
This

system

Filenm.TXT

method
is

using

(it will

down

the

snapshot
file
SNAPn.DAT/ASCIL'

Note

from the

remote

the

console

system

also

'SHOW

.TXT

file

binary

This

step
control.

SNAPTO.EXE

for

the

8600

file,

'SET

via

the

SNAPn.DAT/ASCII'

will in effect
to
the
remote

accessing

output
file
created
when
upline
loaded
using

run

to convert

interim step
a

.DMP
to

program which

file
(created via the
a binary file which is
VSA programs.

logging

the

snapshots

the
the

command.
This file will not have
contain embedded <CR>s,<LF>s).

converted to
is
necessary

solid.

that when SNAPTO.EXE

into

useful

RL02

has

DFO03 using

the
snapshot
file.
This
snapshot,
in
ASCII
format,

transfer

control

file

the

type

system.
a

(e.g., VMS with an autodial
command),
it
<can
connect

port

command,

when

snapshot

system.

capability
HOST/DTE'

carriage

this ASCII

takes place where

file
create
a

converts

ASCII
'SHOW

file

the

using

VSRGET.FDL.
file with carriage

the

ASCII

snapshot

'SHOW SNAPn.DAT/ASCIL' command) into
suitable for input to the VSRBLD and

ERRORS

AND

ERROR

ANALYSIS

® Console RLO2
SNAPn.DAT

“SHOW SNAPn.DAT/ASCII”

>¥

EXECUTED FROM A REMOTE VAX

SYSTEM WITH LOGGING CAPABILITY

VIA THE REMOTE PORT.

ERRFMT.COM
ERRFMT.EXE

RUN BY
VMS AT

STARTUP

TIME

[ SNAPTO.EXE }—————{ VSRGET.FDL l

.SNP

.LOG

USED FOR FORMATTED
G§

l VSROLD.EXE

—
S

BIT-TO-TEXT
TRANSLATION
O-TE:

VSRBLD.EXE l

USED FOR INTERACTIVE
BIT-TO-TEXT TRANSLATION

USED TO ANALYZE THE SNAPSHOT
l

USING PRE-DEFINED RULES

ANALYSIS OUTPUT FILES

VSA.EXE

AVAILABLE FROM THE RDC ONLY.
NOT AVAILABLE ON-SITE.
NOTE

THECIRCLEDNUMBERS REFERTONOTES ON
THE PRECEDING PAGES.

Figure 5-2

MR-15993

Console Snapshot File Information Flow Chart

Filenm.BIN, Filenm.SNP, or ERRSNAP.LOG;nnn.
These are
the
binary
snapshot files.
These files may be the output from
the SNAPTO.EXE program or they may
be
part
of
a
system
errorlog.
In
the
1latter case, the binary snapshot files
are actually not part of the system error log, rather
each
snapshot
file
is
a
separate
file (ERRSNAP.LOG;nn) with
linkages to the system errorlog file.

ERRORS

AND

ERROR

VMS

ANALYSIS

system

startup

determines whether
console RLO2 pack.
transferred

ERRSNAP.LOG;nn),

time,

ERRFMT.COM

executed

and

or not valid snapshot files exist on the
If a valid file is present, the file is
the

SYSSERROR

entry

with

area

pointer

(filename:

the

snapshot

file
is
made in the system errorlog file (this is done
ERRFMT.EXE), and the console RL02
snapshot
file
will
invalidated.
VSROLD.EXE

that

used

was

the

original
to

bit-to-text

translate

these

translation
snapshot

by
be

package

files.

This

program is menu
driven
and
can
bhe
used
for
selective
translation
of
the
snapshot
files.
Note
that
the
translation options include only
signal
names
and
block
dumps;
there
are
no
register decodes or sorting done by
VSROLD.EXE.

The

input

file

snapshot
files and the
file oriented (refer to
The

ASCII

input

file

signal

for

VSROLD.EXE

the

output may be either TT:
the VSROLD menu for more

name

tables

(*.CDF)

are

binary

driven or
details).

also

required

to VSROLD.EXE.

VSRBLD.EXE is used to provide formatted ASCIT output from a
binary
snapshot
file.
Using
a
binary snapshot file as
input, and the .CDF files as data, VSRBLD
generates
three
output files:
o

"Filenm.HDR"

record
record.
0o

Two

containing
snapshot

information

file,

including

files which contain
wvisibility
points
recorded in
second version of this file will

sorted
A

the

"Filenm.SIG"

the
The

file

within

on
the

a list of
all
of
the snapshot file.

have

the

signals

alphabetically.

"Filenm.REG"

file

containing

formatted

bit-to-text

translation
of
all
records
(except
the
visibility channels) within the snapshot file.
The

each
HEADER

combination

represents

all

the

information

no error

three

analysis

these

available

done

module

output
in

during

the

files
snapshot

file.

There

creation

files,
rather it is up to the Field Engineer to
and analyze the snapshot or to contact
the
Diagnosis Center for assistance.

these

manually
Remote

VSA.EXE
VSA.EXE

decode

used

to ANALYZE snapshot files.
the
ASCII
signal
file

includes

The
input
generated

to
by

VSRBLD.EXE (*.SIG) as well as the original binary
snapshot
file
(ERRSNAP.LOG;nnn).
VSA.EXE
will generate two ASCII
output files, one containing stall analysis (if applicable)
and
signals
of importance, the second file containing the
analysis of embedded stack frames within the snapshot file.
NOTE

VSA.EXE

Company Confidential

NOT AVAILABLE

to contact

the

SITE.

Remote

upline
1load
the
the remote site.

and

the

program

To run VSA, it is necessary
Diagnosis Center, which
will

SNAPSHOT

File

then

run VSA.EXE

ERRORS

10.

A list of

STALL

Signals of importance (includes error signals
found in the true state)

applicable STALL theories

theory

descriptions

Default

signal

such

UPCs

list

and

CONTROL STORE

1list

that were

nice-to-know

signals

etc.).

stack

frame

was

found

these

three

the

EBox

analyze
file.

scratch

pad

the

stack

frame

the
The

EBox,
and
presence of

PARITY ERROR CORRECTION

Control store parity
errors
transmitted
as
a
three-bit
of

(if any)

(optional)

registers, VSA.EXE will extract and
and then output the results to this

any

program,

"Filenm.MC", the second output
of
the
SNAPSHOT
analysis
program, includes the output of a machine check stack frame
if
one
was
found
embedded
within
the
snapshot.
For
example,
1if
the snapshot was the result of a Double Error
Halt

5.3

ERROR ANALYSIS

"Filenm.ANL", the output of the SNAPSHOT analysis
will contain the following information:

11.

AND

bits

will

are
code

prioritized
by
to the console.

generate

console

interrupt,

the

code

indicating
which
control
store
is
in
error.
The console will
disable external interrupts and suspend the KAF
timer
to
prevent
the
EBox from interrupting the console and to prevent a keep alive
fail condition whilec the EBox is not executing macro
instructions.
The

console

will

correct

the

control

store

possible, and set up the information for the
the
RAM
1ID,
syndrome,
CS or DRAM address,
bit, if correction fails.

parity

error,

EBox
CSES
register;
and the uncorrectable

If the control store parity error occurs in the EBox, the clock
the
control
store
data
register is disabled preventing
from executing any more micro-instructions.

the

to
EBox

After

the console corrects the control store parity error and
sets
up
the CSES register, it will reset the control store parity error
and generate an EBox microtrap (CSPE RST LST CYC) with the CSB
SDB
control
channel
and "CL UNHANG RESET H".
The microtrap will call
the EBox error handling microcode.

If the control store parity error is in the IBox or FBox, the
EBox
will
have been informed by the error handling microcode.
The EBox
will transfer the EHSR to EBCS, which will provide the stimulus
to
generate
the
three-bit
code for the console.
The EBox microcode
will then clear RBUFC <07> (DONE) and loop while waiting
for
DONE
to

set.

After the console has corrected the parity error
and
set
up
the
CSES,
it
will clear the DONE bit, which will allow the EBox error
handling microcode to proceed with error logging.
If

the

attempt

the

control
to

store

restart

parity

the

error

system

faulty microinstruction.

because

the

MBox,

MBox

has

there will
already

executed

ERRORS

AND

ERROR ANALYSIS

CONTROL STORE
PARITY ERROR
INTERRUPT

VALID
INTERRUPT

INTERR

CODE

c SPERR

}——

INCREMENT UCODE SCQREBQARD
PARITY ERROR COUNT

READ uADDR AND uDATA
CALCULATE ECC
GET ECC FROM TABLES
GENERATE SYNDROME

ALL

RELOAD l

FORAM

YES

NO ECC

AN ERROR

Founp N |
TABLES

FLIP BIT IN ERROR
REWRITE puWORD
REREAD uWORD

|OCCURRED |
READING
VIA SDB

‘

ML LAl

SYNDROME

1equacTo
ZERO
'

MULTIPLE

BIT
ERROR
'

|
SYNDROME

INDICATES
NONEXISTENT
|er

{

( NOEééaCUPCEflR ) ( SYNZRO ) C MBTERR ) ( SYNGTR )
C

MUNREC

SEND CSES TO EROX
UPDATE UCODE

:RESET CSPE AND FORCE EBOX uTRAP.

SCOREBOARD

CORRECTED

PRINT CSPERR MESSAGE
PRINT "REASON" MESSAGE

PRINT GOOD/BAD/SYNDOME

iF PCFAIL, PRINT DATA XOR

NOTE

{F ERROR WAS CORRECTED, ENTRY WILL BE
MADE

SYSTEM

ERROR

LOG AND

CONSOLE MESSAGE WILL OCCUR.
iF ERROR WAS NOT CORRECTABLE, A
CONSOLE MESSAGE WILL OCCUR FOLLOWED BY A KEEP ALIVE FAILURE.
MA-16385

Figure

5-3

Control

Store

Simplified

Parity Error

Flow Chart

ERRORS

5.4

SYSTEMATIC

You should first try to use
procedure
due to something

Method
1.
being hung,

When doing specialized initializes,
more and more information.

Method

ERROR

ANALYSIS

INFORMATION GATHERING PROCEDURES

The following methods can be used to gather
the hardware status after an error.

5.4.1

AND

concerning

information

If
unable
to
try Methods 2,

use

this

each succeeding method destroys

NOTE

SNAP must have been

set

"off"TM

prior

the

failure.
>>>

DEB

>>>>

STOP

CPU

>>>> MIC or TMIC
SBSM>>>>

SPACE

SBSM>>>>

SPACE

SBSM>>>>

SPACE

SBSM>>>> SPACE

Find

the

hung microcode

(etc.)

SBSM>>>> CR

To get

>>>> UNHANG

Restarts CSM without disturbing anything

»>>>

SET

QUIET

out of

step mode

>>>> @STKFRM

Execute the command file that dumps
the
ESC
locations which may contain a Machine Check

»>>>>

MAPEN

>>>>

Use

the

appropriate

If MAPEN = 1
>>>> E/V/NEXT:100
If

MAPEN

>>>>

——

space bar

OFF

Memory

Management

turned

on?

command,

depending

upon

the

"MAPEN".

loop

|
Dump

the

STACK

Dump

the

STACK

E/P/NEXT:100

contents

ERRORS

AND

ERROR

ANALYSIS

Continue

dumping
other
registers.
configuration dependent.

system
»>22>>

@RDSBIO

Execute the
registers

>>>>

@RDSBI1

Execute

>>>>

E/X

5.4.2
>>>

following

command

file

examines

dump

Execute

the

appropriate

examine

the

SBI

NEXUS

console

and

are

SBIA

commands

the command
file
to
dump
registers if the system has two SBIs

XXXXXXXX

Method

The

peripherals

DEB

>>>>

RESET

This

>>>>

UNHANG

Restart

>>>>

SET

>>>>

@STKFRM

will

reset

CSM

>>>>

@RDSBIO

>>>>

@RDSBI1

Dumps

ESC

5.4.3

the TB

disturbing

lost

anything

XXXXXXXX

Method

which

1locations

may

contain

Check

Execute the
registers

command

file

dump

SBIA

Execute

command

file

dump

SBIA

appropriate console
commands
SBI NEXUS and peripherals

the

registers
E/X

without

MBox,

QUIET OFF

Machine

>>>>

the

Execute
examine

the
the

the

system has

two

SBIs

>>>>INIT/CPU

Resets

the

Only the

CPU.

I/0 registers

will

valid

>>>>

@RDSBIO

Execute the
registers

command

file

dump

SBIA

>>>>

@RDSBI1

Execute

command

file

dump

SBIA

commands

the

registers
>>>>

5.4.4

E/X

XXXXXXXX

Method

two

SBIs

Execute

the

appropriate

the

SBI

NEXUS

and

peripherals

CPU.

Only

the

I/0

console

4
Resets the
be valid

>>>>INIT/PAMM

SBIA

E/X

system has

examine

>>>>INIT/CPU

>>>>

the

XXXXXXXX

registers

are

longer

Execute

the

appropriate

examine

the

SBI

5-10

NEXUS

registers

will

valid

console

commands

and peripherals

ERRORS

Method

ERROR ANALYSTIS

>>>>INIT/CFPU

Resets the CPU.

>>>>INIT/PAMM

SBIA registers are

>>>>

The

Only the

valid

I/O registers

will

5.4.5

AND

UNJAM

UNIBUS and MASSBUS peripheral
contain
wvalid
information,
but
else is lost

>>>>

E/X

5.5

DUMP.COM

XXXXXXXX

Execute
examine

The following command
System RL0O2 pack.
The

no longer valid

purpose

the

file

the
the

devices may

everything

appropriate console
commands
SBI NEXUS and peripherals

should

put

to provide

quick

each

VAX

method of

8600/8650

executing

hardware dump for keep-alive failures, and whenever you
not to use the "SNAP and VSR/VSA" facilities.

have

chosen

NOTE

The portion

this

command

file

that

examines

the

I1/0
controllers, and peripheral devices, is system
configuration dependent.
Therefore, it
will
have
to
be modified to reflect the configuration of the
system it is to be used on.

After
copy

this file is dumped onto the
command)
you
can use it by

prompt.

For

this

prior

the

failure.

This

file must

information

typed

RL02 pack
typing in

in exactly

valid,

is,

(using
"@DUMP"

"SNAP"

except

the
EXCHANGE
to the console

must

for

the

set

"OFF"

comments,

which may be left out.
If you do not wish to type all this in, the
command file is available on the ENET.
You can
then
dump
it
on
tape
for
transporting
to
the
different
sites.
To have a copy

mailed

to your node,

Hardware

contact your

DEBUG

QUIET

SET

ABORT

SET

BASE

STOP

OFF
OFF

Get microcode

SET

éICRD
MICRO
MICRO

MICRO

CPU

loop

PCs

local

Stack

dump

support organization.

command

file

ERRORS

AND

ERROR ANALYSIS

MICRO
MICRO

MICRO
MICRO
MICRO
MICRO

UNHANG
HALT

1 Examine SCRATCH PADS - data is as indicated only if
i

1
!

a machine check was detected and the CPU was halted
prior to re-entering MACROCODE program.

E/ESC 17
E/ESC 18
E/ESC 19
E/ESC 1A
E/ESC 1B
E/ESC 1C
E/ESC 1D
E/ESC 1E
E/ESC

!
!
!
!
!
!
!
!
!
|
!
!
!

E/ESC 20
E/ESC 21
E/ESC
E/ESC
E/ESC
E/ESC
E/ESC
E/ESC
E/ESC
E/ESC
E/ESC
E/ESC
E/ESC
E/ESC

22
23
24
25
26
27
28
29
2A
2B
2C
2D

E/ESC
E/ESC

2E
2F

!
!

!
!
!
!
!
!
!
!
!
!
!
!
!
!

Byte count
EHM.STS VMQSAV
EBCS
EDPSR
-~
CSLINT
IBESR
EBXWD1l
EBXWD2

IVASAV
-~
VIBASAV -~
ESASAV
ISASAV
CPC
MSTAT1
MSTAT2
MDECC
MERG
CSHCTL
MEAR
MEDR
FBXERR
CSES

-~
-

PC
PSL

-~
-

in Stack Frame
Error Handling Microcode Status
sometimes holds VMA for EBox port
EBox Control and Status
EBox Data Path Status
Console Interrupt Word
IBox Error Summary
Last (or 2nd to last) word sent to
MBox (write)
Last (or 2nd to last) word sent to
MBox (write)
1IBox Virtual Address
VA of next IBUF Port request to fill
IBuffer
EBox Execution/Result storage PC
PC of instruction Op Port is working on
PC of instruction be evaluated in IBUFF
MBox Status
MBox Status
MBox ECC status
Memory error status
Cache control
Address in PA latch when error occurred
Data word in use when error occurred
FBox Error (will be FFFFFFFF if no errors)
€S correction (will
be FFFFFFFF if no
errors)
Program PC when error occurred
Processor Status Longword

!
!

Examine all Scratch Pads, CPU registers, and I/0 registers.
Also verify contents of all Control Store RAMs.

!
E/ESC/N:FF

Dump

all EBox Scratch

General

Internal Registers

locations

E/G/N:F

Purpose

Registers

E/I/N:24
i

e
foss
R
Bese
o

EBox
IBox
IBox
IBox

ISA.SAV in
IVA.SAV in

IBox

Error

Data

Error Address
Status Register

MBox

Status

VIBA.SAV

MSTAT2

fown

MSTAT1

MBox
MBox

Control

VIBASAV

MBox

MEAR

MEDR

deo

IVASAV

Baew

ISASAV

IBox

Valid

VPCBITS

Examine

the

Store Error Status
Interrupt Status

EBox

Men

DD EDONDDDEDEDDEEDEOEEREEEDENENS
=M~
HND

IBESR

ESASAV

and

Data
EMD

ESA.SAV
Error

AND ERROR ANALYSIS

Control

Control
Console

EMD

Cache

Bome

CSES
CSLINT

EBCS
EDPSR

current

IBox

MBox

CPC
CSHCTL

ODDONEDNE

ERRORS

Path

summary

Status

IBox

bits

STACK

/V/NEXT:100

Examine
20080000

20080004
20080008
2008000C
20080010
20080014
20080018
2008001C
20080020
20080024
20080028
2008002C
20080030
20080030
20080030
20080030
20080030
20080030
20080030
20080030
20080030
20080030
20080030
20080030
20080030
20080030

20080030
20080030
20080034
20080038
2008003C
20080040
20080044
20080048

2008004cC

all

ABus

ISBIA
ISBIA
ISBIA
ISBIA
!SBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
!SBIA
!SBIA
ISBIA
!SBIA
!SBIA
ISBIA
!SBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
!SBIA
ISBIA
!SBIA
ISBIA
ISBIA
ISBIA
ISBIA
!SBIA
ISBIA

adapter,

#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
#0
40
#0
#0
#0
#0
#0

SBI

Nexus,

Configuration
Control and Status
Error

Summary

Diagnostic Control
DMAI Command/Address
DMAI

DMAA Command/Address
DMAA

DMAB

Command/Address

DMAB

DMAC
DMAC

Command/Address
ID

SILO

SILO
SILO

SILO
SILO
SILO
SILO
SILO

SILO

SILO
SILO
SILO

SILO
SILO

#0 SILO
#0
#0

and

SILO
Error

#0 Timeout Address
#0 Fault/Status
#0 SILO Compare
#0 Maintenance
#0 UNJAM
#0 Quadclear

peripheral

registers

ERRORS

AND

ERROR

ANALYSIS

E
E
E
E
E
E
E

22080000
22080004
22080008
2208000C
22080010
22080014
22080018

ISBIA
ISBIA
!SBIA
ISBIA
ISBIA
ISBIA
ISBIA

#1
#1
#1
#1
#1
#1
#1

Configuration
Control and Status
Error Summary
Diagnostic Control
DMAI Command/Address
DMAI ID
DMAA Command/Address

2208001C

ISBIA

DMAA

E
E

22080020
22080024

ISBIA
ISBIA

#1
#1

DMAB
DMAB

Command/Address
1ID

E
E
E
E
E
E
E
E
E
E

22080028
2208002C
22080030
22080030
22080030
22080030
22080030
22080030
22080030
22080030

ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
ISBIA
{SBIA

$1
#1
#1
#1
#1
#1
#1
#1
#1
#1

DMAC Command/Address
DMAC ID
SILO
SILO
SILO
SILO
SILO
SILO
SILO
SILO

E
E
E

22080030
22080030
22080030

ISBIA
ISBIA
ISBIA

#1
#1
#1

SILO

SILO
SILO

22080030

ISBIA

SILO

22080030

ISBIA

SILO

22080030

!SBIA

22080030

ISBIA

#1
#1
#1

SILO
SILO
SILO

#1
#1
#1
#1
#1
#1
#1

Error
Timeout Address
Fault/Status
SILO Compare
Maintenance
UNJAM
Quadclear

E
E
E
E
E
E
E
E
E
E

22080030

ISBIA

22080034
22080038
2208003C
22080040

ISBIA
ISBIA
ISBIA
ISBIA

22080044

ISBIA

22080048

ISBIA

2208004cC

ISBIA

E 20006000
E 20006004
E 20006008
E 2000600C
E 20006010
E 20006014
E/N:7 20006020
E/N:3 20006030
E/N:F 20006040

!
!
!
!
!
!
!
!
!

UBA
UBA
UBA
UBA
UBA
UBA
UBA
UBA
UBA

Configuration

Contrel
Status
Diagnostic Control
Failed MAP Entry
Failed UNIBUS Address
Buffer Selection Verification Registers
BR Receive Vector Registers 4-7
Data Path Registers 0-15

2001C000

Configuration

2001C004

Control

and

Status

E/PAMM/N:FF

SHOW POWER
SHOW

PANEL

SHOW

UCODE

SHOW VERSION
SHOW CLOCK

This

step will

take

few minutes.

VERIFY

SET

Verify

the

contents

all
L

QUIET

Control

Stores

0-7

ERRORS

PROGRAM TO SCAN MEMORY FOR PARITY ERRORS

>>>

DEB

>>>>

SET

>>>>

DEP RO

>>>>

DEP R1

ERROR ANALYSIS

(SCAN.COM)

SNAP OFF
Ll
L2]

DEP

100

175180DO0

MOVL

(RO)+,R1

DEP

104

0001009F

;

JUMP

@#100

>>>>

DEP

108

>>>>
>>>>

HALT

temporary storage

place SCB starting at location 200

>>>>

DEP

204

207

setup starting address

5.6

AND

setup Machine

>>>>

DEP

254

257

setup SBE trap catcher.

>>>> DEP SCBB 200

>>>> DEP EHSR 0.

>>>>

interrupts from "1D" up.

MBox

interrupt

;

setup Stack

"1F".

Clears all CPU error bits.

Pointer.

100

Should halt with ESC #12, and ESC #C4, containing a 207.
This indicates that a machine check has occurred. Verify
that the Machine Check was the result of a NXM by dumping
ESC

and

checking errors.

If ESC #12 contains 254 and ESC #C4 contain a
problem was a single-bit error (SBE).

>>>>

E/ESC

>>>>

@STKFRM

;

catcher.

>>>> DEP SP 1000

allows

trap

>>>> DEP PSL 41C0000

Check

257,

the

or dump all

ESC

locations with

the

>>>>

E/ESC/N:FF

5.7

VMS AND THE SYSTEM EVENT FILE

following command:

(ERRLOG.SYS)

The VMS Operating System
maintains
a
System
Event
File
called
ERRLOG.SYS.
The
file
1is
located
in
the
SYS$SYSROOT:[SYSERR]
directory and is
and other events

used to record errors, status
changes,
that occur during system operation.

messages,

ERRORS

AND

ERROR ANALYSIS

Each time one of these events occur, the normal operation of VMS is
interrupted
and
a
special routine is called to handle the event.
The routine
requests
a
System
Event
Buffer
and
then
gathers
pre-defined
information
about
the
event
(e.g.,
system status,
hardware and software registers, etc.) and puts it in
the
buffer.
Once the buffer is built the routine queues a request to append the
buffer to the System Event File.
When the queue is
processed
the
buffer is appended to SYS$SYSROOT: [SYSERR]ERRLOG.SYS.
Two programs (ANALYZE/ERRORLOG
and
RETRIEVE
a
Spear
Library
function)
are
available
to
translate the contents of the System
Event File into ASCII reports.
Both
of
these
programs
use
the
Event
Record Formatter (ERF) to translate the entries in the Event
File.
Therefore, regardless of which program you use the format of
the
translated
entries
will
be
the
same.
The main difference
between the two programs
1is
the
command
syntax,
the
selection
criteria,
and
the format of the summary reports they produce.
In
addition to translating system event file entries Spear is
capable
of
analyzing the contents of the event file and calculating system
availability.

5.7:1

ANALYZE/ERRORLOG

ANALYZE/ERRORLOG uses a non-interactive command syntax.
That
is,
the
Command,
Qualifiers
and
Arguments,
are entered in a single
string.
The Qualifiers allow you to select specific entries from a
binary System Event File and either produce a separate binary event
file that contains only those entries, or translate the entries and
produce
an
ASCII
Report.
For- a
complete
description of this
utility, including
more
information
about
the
ANALYZE/ERRORLOG
command
and
its
qualifiers , see the VAX/VMS Utilities Reference
Volume.,

5.7.2

SPEAR Library Functions

SPEAR is a maintenance tool specifically
designed
to
help
Field
Service
Engineers
sort
and analyze the contents of System Event
Files.
There
Extended.

are

two

versions of

Spear:

SPEAR

Basic

and

SPEAR

5.7.2.1
SPEAR Basic - SPEAR Basic is available at all
sites
that
have a DEC Maintenance Contract.
This version of SPEAR consists of
five programs:

1nstruct - Instruct is a computer based
instructional
program
that
is
designed
to
help
new
users learn to use the SPEAR
Library
Programs.
In
addition
to
explaining
the
SPEAR
Programs,
instruct
also
describes the organization of system
event files and includes a review of some of
the
most
common
troubleshooting approaches.
Compute - Compute is designed to use the contents of the System
Event
File to calculate system availability and effectiveness.

The Compute report can be used (in part) to
determine
1if
the
system
is
approaching
the point where corrective maintenance
will

soon be

required.

5~16

ERRORS

AND

ERROR ANALYSIS

Summarize = Summarize is designed to summarize the contents
of
the
system
event
file.
The Summarize report can be used to
determine whether the CPU or one of the
I/0
subsystems
needs
further
Retrieve

investigation.
-

Retrieve

:
1is

bit-to-text

translator.

1is

designed to extract specific entries from the System Event File
and produce either a brief or full translation
of
the
event.
This
information
can
be used to investigate the cause of CPU
and I/0 failures.
VSR (Venus Snap File Report Builder) - This program
was
added
to
the
Basic
SPEAR
Library
specifically
to
support
VAX
8600/8650
Systemns.
Like
Retrieve,
VSR
1is
a
bit-to-text
translator.
VSR, however, is designed to translate SNAP Files.
A SNAP file is a file built by the console as
a
result
of
a
Keep Alive Fail condition.

5.7.2.2

SPEAR

Extended - SPEAR

Extended

1is

only

available

Remote
Diagnosis
Centers.
In
addition to the programs
available in SPEAR Basic, Spear Extended includes:

Analyze - Analyze

that

is designed to analyze the contents of

are

large

System
Event
Files
and
identify
the most probable cause of
certain failures.
Analyze evaluates the
events
in
a
System
Event File against a set of If-Then Isolation Theories.
If the
Events support a
theory
then
the
theory
1is
displayed
for

consideration by the Engineer at the RD center.

VSA (Venus Snap File Analysis Builder)
VSA
1is
similar
to
Analyze except it is designed to analyze the contents of System
SNAP Files.

5-17

CHAPTER

DIAGNOSTICS

NOTE

Chapter

6 will

EMM

SELF

T11l

(PROM)

cover:

TEST

SELF

TEST

PROM COMMAND SET

CONSOLE MODULE

DIAGNOSTIC

MICRO-HARD-CORE

MHC

DIAGNOSTIC

(EDKAA)

COMMAND SET

MICRO

DIAGNOSTICS

MICRO

DIAGNOSTIC

COMMAND SET

MICRO

DIAGNOSTIC

COMMAND FILES

DIAGNOSTIC

MACRO

SUPERVISOR

(EDSAA)

DIAGNOSTICS

The remaining command sets, GENERAL,
in Chapter 10, Console Commands.

e ——

(EDOBA)

MACRO,

and

HEX

are

located

DIAGNOSTICS
EMM SELF TEST

6.1

EMM SELF TEST

When the VAX 86xx is first turned on and power is applied to the
EMM, the EMM will automatically run a set of Self Tests. The
tests are listed in Table 6-1. The EMM uses the Error Codes
listed in Table 6-=2 to inform the console of error conditions.

6.1.1

Prerequisites

None

6.1.2

EMM Self Test Descriptions
Table

TEST

ROMCHK
UTEST1

6=-1

EMM Self Test

DESCRIPTION

ROM Checksum Verification - Compute the ROM checksum

verify that

and

is correct.

Data test for MODE registers - Tests that MODEl, MODE2,
and COMMAND registers can hold 125 and 252 This test
See
doesn't verify that they are separately addressable.
Note

UTEST2

Test Addressability of USART Registers - Verifies that
MODE and COMMAND registers are independently addressable
Sece
and that they can hold data without interfering.

UTEST3

Test USART in Local Loopback - Tests status register and
(We don’'t test for some
data registers at 9600 baud
errors, e.g., framing and overrun, which could be forced,

Note

incorrect
exclude
protocol will
the
since
because they don't checksum.) See Note 1.

RTEST1

messages

Parity Circuit, Part 1 - The following algorithm is

wused

to test parity for each RAM.

If a RST 0 occurs
Disable RST 0 ON PARITY ERROR.
because of a parity error it indicates that the RST 0

ON PARITY ERROR circuit could not be disabled.

Select parity to be generated (GEN PAR)

Write DATA pattern to first RAM location (2000H)

GEN
PAR

TEST
DATA

PAR

ODD
ODD
EVEN
EVEN

10001010
01010101
11101100
00110011

YES
YES
NO
NO

ERR

Read pattern back from first RAM location

DIAGNOSTICS
EMM

Test
e

returned
BAD

Test

DATA

for

DATA pattern.
RAM

error,

SELF

TEST

report:

LOCATION

expected

PAR

ERR

condition.

error,

report:

RTEST2

BAD

PARITY

GENERATOR

BAD

PARITY

RAM

BAD

PARTTY-CHECK

Repeat

above

steps

for

all

Circuit, Part 2 - The
test parity for each RAM.

Enable

Set

RST

indicator

PARITY

Select

"RST 0"

Write

ODD parity
something

TEST

DATA

following

algorithm

routine will

know

RTEST3

RAM

into FIRST

occurs,

this

RAM

location

and

read

Test

The

following

Disable

Select

Write data pattern

RST

PARITY

EVEN parity

TEST

PAR

DATA

BIT

ERR

00110011

01010101

0
1

NO
NO
NO

10101000

Read RAM
@

report:

algorithm

used

for each RAM.

that

"PARITY ERROR FAILED TO RESET CPU"

Data

data

RST

used

generation

back
5.

ERROR

forced error.

CIRCUIT

Parity

CIRCUIT,

LOCATION,

compare

ERROR

generation

into RAM location:

location and

report:

test

fails
"BAD

compare

result.

low-order nibble
(bits
0-3)
DATA
RAM
LOCATION,
LOW-ORDER

NIBBLE"

compare

report:
NIBBLE"

fails

in high~order

"BAD

DATA

RAM

nibble

LOCATION,

(bits

4-7)

HIGH-ORDER

DIAGNOSTICS

EMM SELF TEST

RTEST4

"BAD

If PAR ERR report:

PARITY

Test PAR ERR flag.

Repeat steps for all patterns and all RAM locations

RAM LOCATION"

RAM Addressing and Cell Interference Test - The following
algorithm is used to test data for each RAM.

Disable RST 0 ON PARITY ERROR circuit

Generate RAM data pattern from column ‘a’.

For '-1' values, select ODD parity generation.

For '0' values, select EVEN parity generation.
DATA

TEST

RAM Location
0000

0-1-1-1-1-1
0~-1-1-1-1-1
0-1-1-1-1-1
0-1-1-1-1-1
0-1-1-1-1-+-1
0-1-1-1-1-1

0
0
0
0

0~-1-1-1-1-=1
0-1-1-1-1-1
0=1-1-1-1-1
0-1-1-1-1-1

0-1

0-1
0
0
-1-1
0
0-1
0
0
-1

-1-1

-1

Verify RAM data pattern.
e

0-1
-1 -1
0-1
0o-1
0-1
0
-1
0-1
0
o0
0
-1 -1-1
0
0-1-1

0-1

0 -1-1-1-1-1-1-1-1-=1
0-1-1-1-1-1=-1-1-1
-1
0-1-1-1-1-1-1-1-1
o
0-1-1-1-1-1-1-1
-1 =1
0-1-1-1=-1-1-1-1
0-1
0-1-1-1-1~-1-1-1
0
-1
0-1-1-1-1-1-1-1
0
o
0-1-1-1-1-=1-1
-1 -1-1
0-1-1-1-1-1-1
0-1-1
0-1-1-1-1-1-1
0-1
-1
0-1-1-1-1-1-1
0-1
0o
0-1-1-1-1-1-1
0
-1-1
0-1-1-1-1-1-1
0
0o-1
0-1-1-1-1-1-1
0
0
-1
0~-1-1-1-1-1-1
0
0o
o
0-1-1-1-1-1
-1 ~-1-1-1
0-1-1-1-1-1
0-1-1-1
0-1-1-1-1-1
0-1-1
-1
0-1-1-1-1-1
0-1-1
o

etc.

1023

-1 -1-1-1-1-1-1-1-1-=1

-1

0031

0-1-1-1-1-1

0-1-1-1-1-1
0

If error, report:

"BAD DATA RAM ADDRESS SELECT"

DIAGNOSTICS

EMM

Check

for

should
ERR).

1If

expected

have

PAR

ERR

ERR),

failure,

condition:
data

should

TEST

(-1

data

not

have

PAR

the

LAT

report:

,()flj

SELF

"BAD

PARITY

RAM

ADDRESS

SELECT"

5.
IS55TST

Repeat

Test

5.5

flip

interrupt
occur.

is
I75TST

steps

This

7.5

USART

flop

request

fault

Test

for

Interrupt

not

each

column

Tests

that

the

Interrupt

and

the

CPU

and

meant

cvonsidered

asserted,

to be

Tests

bit

CTR

the

that

output

generates

interrupt

comprehensive

test,

5.5

will

nor

fatal.
that

work

the
to

RX CLK

cause

output

interrupts

of
at

the
840

microsec
intervals.
Failures
are
either
that
no
interrupt request could be seen at the CPU when it should
have existed, that when
it
did
exist
at
the
CPU
no
interrupt occurred, or that it did not time correctly.
NOTE

UERR
If

Disk
In

(Error
a

Handler

for

Test

fails,

USART

Display
order

once

regulators

have

the
have

error
1is
to relatch
again after LAT

The
Any

self

test

errors

reported

test

loop

the

USART

toggle

disks,

Errors)
the

failing
LAT AC

Magnetic

test.
LO must

In a power up situation,
the
main
CPU
because
not been turned on
vet.

this
the

If
intermittent, the console may
the AC LO and then unlatch it
DC LO has been deasserted.

checks

the

USART,

detected

during

HDCODE,

which

character
for
below), waits 5

Failing

then

toggle

be deasserted.
will
not
hurt

all

the

each
error
seconds, and

(Loop on Error).

ROM,

and

self-test

sends

RAM.
are

unique

(see
Table
returns
to

6-=2
the

DIAGNOSTICS
EMM SELF TEST

T-11

SELF TEST

(PROM)

EMM Error Code Descriptions

6.1.3

EMM Error Code Descriptions

Code

Error Code Description

!OZ e )N G TOmEoO0 W

Table 6-2

Module A not OK, sent at end of self-test
Completed self test successfully

6.2

Parity

Parity ERROR, either due

Checker or BAD Parity RAM
RAM Data ERROR - LOW order nibble

Parity

Generator

RAM Data ERROR - BOTH nibbles (might be addressing problem)

RAM Data ERROR - HIGH order nibble

Parity Error did not cause RESET to PC = 0

Parity RAM Data ERROR

accessing

RAM

(in

loop

No loop

1/2 CHAR timer did not set interrupt request (or set it

indication

ERROR

Parity

Had

before

SETCODE)
ROM had Checksum ERROR

LAT DC LO did not set 5.5 Interrupt request.

error

5.5 Interrupt request did not cause interrupt.
‘

error

7.5

Interrupt set after CPU reset

the wrong

rate)

7.5 Interrupt request did not cause interrupt
7.5

T-11

During

reset

Interrupt did not

(PROM)

SELF TEST

power-up,

executes

microprocessor

T-11

the

PROM

If the
self-tests to validate the console module hardcore logic.
Self Test runs successfully then the PROM Code will sound the
seconds
5
If the operator responds within
Bell on the CTY (RTY).
by pressing a any key on the keyboard the PROM Code will display
The PROM Command
the PROM Prompt; ROM> and enter Command Mode.
individual tests are
The
is described in Table 6-3.
set
described

in Table

6-4.

Prequisites

6.2.1

Successful EMM Self Test and Power-up.

PROM Command Set

6.2.2

The PROM code signals the completion of the self-tests by sending
character

the

bell

ROM>

prompt.

to the CTY.

At that point the operator can

The
type any key to signal the PROM to enter its command loop.
PROM code indicates 1its readiness for input by displaying the
While in the null loop, the PROM code may service the CTY as well |
as the RTY (provided the front panel switch is in the REMOTE !
The command
position and a remote connection has been made) .
parser

the

single-character

PROM

commands

and

extremely

simple.

alphanumeric

available commands are listed in Table 6-3.

arguments.

accepts

The

DIAGNOSTICS

T-11

Table
Command
B

6-3

PROM

(PROM)

SELF

TEST

Command Set

Description
B<cr>

Boot the
command

console software from the
RLO2.
This
begins by testing the interface between
the console
and
the
RL02
controller.
The
sequence of tests follows.

Checks

for AC

LOW and

LOW

conditions

the BAll.

Checks

that

reaches

the

RLO2

controller

Checks
a full

console-generated
RL02

controller
registers.

that RLCS,
complement

Performs an
verify
DMA
RL02,

and

BUS

and

clears

RLBA, and RLDA will
of patterns.

INIT
all

retain

RL02
MAINTENANCE
TRANSFER
to
1logic
between
the console and
other

logic

the

RLV12

controller.

Checks

RLO2
If

any

that

the

boot

block

first word read in from
contains "240" (NOP).

the

abhove

checks

both

the

reported

fail,
CTY
and

the

a
message
is
RTY, and the B

command
aborts.
There
1is
no
test
looping
capability.
If
a
drive
or controller status
error is detected during the actual
booting
of
the device, a number of retries are made.
D

D addr

data<cr>

Deposit
The
E

the

address

data word
must

to the

even

specified

address.

number.

addr<cr>

Examine
O0dd

the data word at

addresses

are

made

the
even

specified
by

address.

dropping

the

low

order bit.
]

addr<cr>

Start
the
address.

The
T

T-11
The

execution
at
must be

address

command-argument

delimiter

the
an

specified
number.

even

optional.

file.ext<cr>

Without
PROM

any

argument,

self-tests

console
passes.

and

diagnostic
If

self-tests are not
and
started
at
filename extension

this
then

program
filename

command
1loads

reruns
and

(EDOBA)
1is

runs

two
the

run and the
file
is
1location
200.
The
is .SAV.

1loaded
default

console
diagnostic
EDOBA
the
PROM
T command tests

invoked
the RTY

interface which causes the
remote
port
to
be
disconnected.
This
prevents
running EDOBA from the remote port.

6-7

the

for

specified,

NOTE

The
with

the

DIAGNOSTICS
T-11 (PROM)

SELF

TEST

Q addr data<cr>

This command allows direct deposits to QBus
174402,
174400,
addresses
The
registers.
174404, and 174406 are the RLCS, RLBA, RLDA, and
All other
respectively.
registers,
RLMPR
addresses are rejected.
R addr<cr>

allows

This command

direct

OQBus

examines

174402,
174400,
addresses
The
registers.
174404, and 174406 are the RLCS, RLBA, RLDA, and
All other
respectively.
registers,
RLMPR
addresses are rejected.

v<cr>

With this command, the PROM code enters a loop
which allows characters to pass directly between
CTY

the

and

RTY.

The

"¢(CTRL/P><CTRL/X>XCTRL/P>"

can

seguence

escape

either input device to force the

be entered from

code

PROM

exit this mode.
X<cr>

This command complies (less any switches) with
the description of same in Chapter 1l of Digital
Standard 032. It is intended to be wused for
binary data transfers between T-11 memory and a
It is not
computer using the remote port input.
intended for human use and will work properly
only when issued from the RTY device.

6.2.3

T-11 (PROM) Self Test Descriptions
NOTE

indicated

Failures in tests 1 through 10 are
the System Control Panel LEDs.

From test 11 onm, test failures are reported on
the CTY (RTY) because the CTY interface, the
be
to
cable, and the printer are assumed
operational.

Table 6-4
TEST

T-11 (PROM) Self Test Descriptions

DESCRIPTION

PROM CHECKSUM TEST - An additive checksum of both the lower
and upper segments of the PROM is calculated. The result
should be 377(8).

On error, a "BR ." is executed.

LED state = 1111

SCP SDB CHANNEL TEST through

floating

pattern

shifted

the LEDs at a fairly slow speed so the operator can

tell if there is a LED failure. The test checks most of the
SDB control logic and the SCP LED logic which is used by
The test 1is
subsequent tests to report test numbers.

open-ended and cannot fail.

LED state = 0001 --> 0010 --> 0100 --> 1000
6-8

DIAGNOSTICS

T-11

TEST

0010

CTY
INTERFACE
MODE
REGISTER
2
BIT
TEST
Alternating
01010101 and 10101010 patterns are written and read from the
CTY's PCI_MODE_REGISTER_2.
LED state

SELF

CTY
INTERFACE
MODE
REGISTER
1
BIT
TEST
Alternating
01010101 and 10101010 patterns are written and read from the
CTY's PCI_MODE_REGISTER_1.
LED state

(PROM)

0011

CTY INTERFACE COMMAND REGISTER BIT TEST Both
a
01010101
and
a
10101010 pattern are written and read from the CTY's
PCI_COMMAND REGISTER.

LED state
05

= 0100

CTY INTERFACE RESET TEST - A
pattern
1is
loaded
1into
the
PCI_COMMAND REGISTER
and
a PCI RESET is performed.
If the
command register clears,
then
the
PCI's
RESET
input
is
connected

and working.

LED state

0101

CTY INTERFACE TXRDY BIT TEST - The local PCI
is
configured
to
run
in
1its normal operating mode (9600 baud, 8-bit, no
parity, 1 stop bit).
The
TXRDY
bit
in
the
PCI
status
register
1is then expected to set within 100 ms.
If ok, the

PCI transmit

expected

LED state

CTY

1loaded

and

immediately.

the

TXRDY

bit

PCI

0110

RXRDY

BIT

TEST

The

local

reinitialized,
but
this
time
in local loop back mode.
A
character is transmitted and the RXRDY bit in the PCI status
register
is
expected
to
set.
When
the
RECEIVED CHARACTER_REGISTER
is
read,
the
RXRDY
bit
is
expected to clear.
=

0111

CTY INTERFACE LOOPBACK TEST LED
state
=
1000
This
is
essentially
the
same
as
the
previous
test
except that
several loopback transmissions are performed to
ensure
the
PCI

and

crystal can handle

LED state
11

INTERFACE

LED state
10

to clear

it.

0111

CTY BANNER TEST - LED state
test
that
relies
on
the

1001
This
1is
an
open-ended
operator
to observe the system

banner.

LED state
12

0111

PARITY
ERROR
LATCH
TEST
-~
Tests
responsible
for
indicating
parity

cleared directly.
13

PARITY CIRCUIT TEST,

whether
the
latch
errors
can be set and

PART 1 - Simultaneously tests

that

RAM

location
0
will
hold
a
01010101 pattern.
If all right,
parity RAM location 0 is expected to contain 1.

DIAGNOSTICS

T-11

(PROM)

SELF

PARITY

RAM

TEST

CIRCUIT

location

TEST,

PART

Simultaneously

tests

will

hold

10101010 pattern.

parity RAM location 0 is
"force
parity
error"
depositing the pattern).
15

RAM

right,
0
(since
the
set
prior
to

expected to contain
bit
in
MCSRU0
was

DATA/ADDRESS

TEST,

BOTTOM-UP

whether

all

modified

moving-inversions
test
is performed on the first 58 Kbytes
of physical RAM.
The test verities all data faults that are
likely to occur in the console RAM configuration, as well as
verifying

all

addressing

(incrementing)
direction.
data, and received data are

faults

On error,
displayed.

the

positive

the

address,

expected

58
KB
RAM
DATA/ADDRESS
TEST,
TOP-DOWN
A
modified
moving-inversions
test
is performed on the first 58 Kbytes
of physical RAM.
The test verifies all data stuck-at faults
likely to occur in the consocle RAM configuration, as well as
all
addressing
faults
in
the
negative
(decrementing)
direction.
On
error,
the
address,
expected
data,
and
received data are displayed.

MAP

RAM

LOCATION

QV TEST

loop

first

performed

that

uses
the
first mapping RAM location (MAPRO0O) to initialize
all of physical memory with 0's and good parity, and
places
each

Kbyte

page

the
20

Kbyte page

first

MAPPING

byte

RAM

pattern

number

boundary.

TEST,

verified

MAPPING

RAM

pattern

DATA

MAPPING

RAM

pattern
mapping

verified
by
RAM locations

the

The

memory mapper

TOY

CHIP

ACCESS

TEST

This

turned

This

test

BBU.

RTY

INTERFACE

patterns

are

MODE

1loaded

into

the

check

test

uses

test

uses

memory

that

all

the

check

uniquely,

that

memory

that

all

the

memory

tests to check that all
uniquely
addressable.

off.
checks

1-BIT

the

value.

uses

uniquely,

that

the
console's
TOY
chip can be accessed
TOY chip is receiving power from the +5 B
the

correct
test

pages

the
previous
are themselves
then

TEST

own

check

pages

access

its

test

can

ADDRESSING

the

This

access

TOP~-DOWN

location of

repeated

can

TEST,

contains

the

mapping RAM locations
negative direction.
22

first

BOTTOM-UP

verified

the

process

each page

DATA

mapping RAM locations
positive direction.
21

The

TEST

RTY's

registers

to verify that the
signal input
from

Normal

operation

PCI_MODE_REGISTER_1

and

checked.
25

RTY

INTERFACE

patterns

MODE

are

loaded

INTERFACE

COMMAND

into

2-BIT

the

TEST

RTY's

Normal

opeération

PCI_MODE_REGISTER_2

and

checked.
26

RTY

and

10101010 pattern

are

BIT

TEST

written

and

Both

read

from

01010101

the

RTY's

PCIgfiQHMAKD_REGISTER.

RTY

INTERFACE

PCI_COMMAND

command

RESET

connected

and

TEST

and

clears,

working.

pattern

1loaded

PCI

RESET

means

the

PCI's

1into

performed.

RESET

input

the

DIAGNOSTICS

T-11
30

(PROM)

SELF TEST

RTY INTERFACE TXRDY BIT TEST - The remote PCI is configured
to run in its normal operating mode (1200 baud, 8-bit, no
The TXRDY bit in the PCI status
parity, 1 stop bit).
register 1is then expected to set within 100 ms. If ok, the
PCI transmit register is loaded and the TXRDY bit is
expected to clear immediately.

is
PCI
remote
RTY INTERFACE RXRDY BIT TEST =~ The
reinitialized, but this time in local loopback mode. A
character is transmitted and the RXRDY bit in the PCI status
the
When
set.
to
expected
is
register
is
RECEIVED_CHARACTER_REGISTER is read, the RXRDY bit
expected to clear.

RTY INTERFACE LOOPBACK TEST - This test duplicates the
function of the previous test in order to verify that the
remote PCI can handle consecutive character transmissions.

SCP SDB LOGIC TEST - This test checks the continuity of the
SDB control channel on the SCP. This test will affect the
state of the front panel LEDs, but is done so quickly it is
unnoticeable.

"cL15 TSTRT" INTERRUPT TEST = This test checks that the
TSTRT interrupt input to the console is not asserted. This
interrupt is not maskable through the PSW, so it must be
cleared before the console program will run.

UNEXPECTED INTERRUPT TEST - This test checks that after a
reset there are no pending (or stuck)
console
full
This ensures the
interrupts to the T-11 microprocessor.
proper start-up of RT and the console kernel. <CTRL/E> Exit failed test loop is also available.
NOTE

Allowable control characters for tests 12 - 35 are:
®
e

<CTRL/S> - Stop test execution.
<CTRL/Q0> - Resume test execution.
<CTRL/0> - Suppress Error Report

DIAGNOSTICS

CONSOLE

6.3

MODULE

CONSOLE

EDOBA
all

the

sections

DIAGNOSTIC

MODULE

6.3.1
The

DIAGNOSTIC

T-11

based

1logic

the

console
the

clock,

interface
logic.
logic itself.

(EDOBA)

(EDOBA)
module

console

SDB,

EDOBA

diagnostic

module,

CBus,

and

local

and

not

test

any

logic

have

run

error

does

Q-Bus,

designed

including

the

test

console

remote

PCI

the VAX CPU

Prerequisite

T-11

6.3.2

(PROM)

EDOBA

Self

Switch

Test

must

BIT

SWITCH

DESCRIPTION

<15>

100000

Exit

subtest

<14>

040000

Loop

<13>

020000

TInhibit

<12>
<11>

010000
004000

Enable trace
Inhibit test

<09>
<07:00>

001000

Loop

000xxx

Select

6.3.3

EDOBA Control

Control

Options

loop

failing
error

and

proceed

subtest

display

iterations
in <07:00>

test
test

free.

number
xxx

for

loop

Characters

Function

Key

Restart

EDOBA

Suspend

output

Resume

output

Erase

command

Exit

EDOBA Test

line

SWR-~-CHANGE mode
the PROM CLI

Descriptions

TEST

NO.

DESCRIPTION

SDB

Control

001
002
003
004
005
006
007

SDMS
SDDB
SDCS
CL18

Logic

Tests
oW

DB Single Step Mode Test (CL19)
SDB Normal Mode Test (CL19)
SDB

Loopback

SUBTESTS

Ll RO LD

NO.

Test,

Normal

Mode

6-12

(CL19)

6.3.4

Enter

DIAGNOSTICS

CONSOLE MODULE

DIAGNOSTIC

(EDOBA)

SDB

SDB
SDB

SDB

Channel
Channel
Channel
Channel
Channel

00
01
02
03
04

SDB

Channel
Channel

SDB

Channel

SDB

Channel

SDB

Channel
Channel
Channel
Channel
Channel
Chanhel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel

SDB

SDB
SDB

SDB

SDB
SDB
SDB
SDB

SDB

10
11
12

13
14
15
16

18
19
20

2]
22

Continuity
Continuity
Continuity
Continuity
Continuity
Continuity

Test

(CT.21)

Test

(CL21)
(CL21)

Test

(CL21)
(CL21)

Test

(CL21)

Test

(CL21)

Test

(CL21)

Test

Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity
Continuity

(CL21)

Test

Test
Test

(CL21)

Test

(CL21)

Test

(CL21)
(CL21)
(CL21)

Test
Test
Test

(CL21)
(CL21)

Test

(CL21)

Test

(CL21)

Test

(CL21)
(CL21)

Test

Test
Test

(CL21)

Continuity Test
Continuity Test

(CL21)
(CL21)

B BN

SDB

Pk pot o ot ol o ot ok o N DD bt ot ot d et e D

010*
011*
012*
013*
014*
015*
0le6*
017*%
020%
021*%*
022*
023*
024%*
025%*
026*
027%
030%
031*
032*
033*
034%*
035*
036*
037*

e BB b

Tester SDB Channel Continuity Tests

MCSR0O
MCSR1
MCSR2
MCSR2

(C108 )
(C108 )
Test, Part 1
Test, Part 2
Test
Test

(CLOS8)

(CLO0O8)

Miscellaneous Console Functions Tests
044*
045*
046*
047%*
050%
051*%*
052*
053*
054%*
055*
056%*
057*
060%*
061*
062*
063*
064*
065*
066*
067*
070*
071%
072%*
073*
074*

CL09 DC Low Test (CL20)
CL CSM Request Test (CLO09)

EMM3 CPU AC Low Test (CLO08)
CL09 System AC Fault Test (CLO08)
CL CPU Power Fail Interrupt Test
CL Unhang Reset Test (CL18)

(CL09)

CL Master Reset Test (CLO09)
CL ABus Enable Test (CL09)
CL Array DC OK Test (CLO9)
CLO9 CPU Alive Test (CLO8)
CLO9
CLO9

CLO9
CLO9
CLO9
CLO9
CLO9
CLO9
CLO9
SIDO
SID1
SID2

Error 0 Test
Error 1 Test
Error 2 Test

(CLO8)
(CLO08)
(CLO8)

ABus Request
ABus Request
ABus Request
ABus Request

0
1
2
3

CPU Control Store PE Test

ABus

Dead

Test
Test
Test
Test

Interrupt

Register Test (CL12)
Register Test (CL12)
Register Test (CL12)
CL IDO Bit Test (CLO8)
CL ID1 Bit Test (CL08)
CL ID2 Bit Test (CLO0S8)

(CLO08)

(CLO8)

(CLO8)
Test (CLOS8)

W Wb

040
041
042
043

Miscellaneous Register Tests

DIAGNOSTICS

PCI
PCT

Mode
Mode

Test

(CL10)

Test

(CL10)

077

EMM

PCI

Command

100

EMM

PCI
PCI

Status

(CL10)

Local

Baud

101

EMM

102

EMM

PCI

EMM

PCI

Bus

Loopback

EMM

PCI

Bus

Inhibit

103

104
Remote

PCI

Tests,

Loopback

Part

Test,

19.2K

Tests

(CL10)

Test, 19,2K Baud (CL10)
Test (RTS Deasserted)
(CL10)

105

Remote

PCI

Mode

106

Remote

Mode Register 2 Test (CL10)
Command and Status Register Tests
Register Addressing

107

Remote

PCI
PCI

110

Remote

PCI

Remote

111*
112*
113*
114*
115*
116*
117*
120*
Remo

PCI

Tests,

Remote
Remote
Remote
Remote

123
124
Remote

SCP

Tests,

Part

PCI

Part

PCI
PCI
PCI
PCI

Local
Local
Local
Local

Test,

Part

1800

Test,

Remote PCI Split Baud Rate Test
Interface

Tests,

Part

SCP

Channel

Init

SCP

LED Drive/Sense
Tests,

SCP Switch

CBUS

Tests,

132

CL15

Part

Test

Part

Test (SCP1)
(SCP1l)

Test

(CL10)

(SCP1l)

Input Test

(SCP1)

TSEL Test

CL15 TXCS

Baud

127

Interface

b b bt N B R N RO

Loopback

(CL10)
(CL10)
(CL10)

130

135*
136

(CL10)

75 Baud
110 Baud
150 Baud

Continuity

134*

Tests

Loopback Test,
Loopback Test,
Loopback Test,

Channel

133*

(CL10)

SCP

131*

Test

126

SCP

CDSRS Test (CL1l1)
CL11 RTERM Carrier Test (CL10)
CL11 RTERM DSR Test (CL10)
CRTS Test (CL10)
Assert CDTR Test (CL10)
REMOTE PCI TXEMT/DSCHG Test (CL10)
CL RTERM DSC Test (CL10)
REMOTE PCI TXRDY Test, Part 1 (CL10)

121
122

125%*

PCI

Nl
RN
SR

EMM
EMM

L abe L) 1)

Tests

PCI

075
076

(EDOBA)

bk ot fod ot

EMM

DIAGNOSTIC

MODULE

(CL13)

RDY Test,

CL15 RXCS DNE Test,

Part

(CL13)

CL15 STOR RDY Test, Part
CL1S5 TSTRT Test (CL13)

(CL13)

LCL R VIR VS 3 VA R Y

CONSOLE

DIAGNOSTICS

CONSOLE MODULE DIAGNOSTIC
CBUS Tests,

) ’%me"'y

137*

Part 2

CBus RAM Data Test, TTL Port, Part 1 (CL16)

140*

CBus RAM Addressing Test, TTL Port (CL16/CL17)

142*

CBus RAM Addressing Test, ECL Port (CL16/CL17)

144*

CL15 RXCS

147*
150*

CL15 TXCS RDY Test, Part 2 (CL13)
CL15 TXCS RDY Test, Part 3 (CL13)

141*
143*

145*
146*

151*

152*
153*
154*
155*
156*
157*
160*

(EDOBA)

CBus Access Test, ECL Port (CL16)
CL15 TXCS IE Test
IE Test

(CL13)

CL15 STOR TIE Test (CL13)
CL15 TSTRT Test (CL13)
CL15 RXCS DNE Test,

Part 2

(CL13)

CL15 RXCS DNE Test, Part 3 (CL13)
(CL15 STOR RDY Test, Part 2 (CL13)
CL15 STOR RDY Test, Part 3 (CL13)
CL15 TSEL Sensed by ECL Port Test (CL13)
Interrupt Test (CL15)
CIL TTX
Interrupt Test (CL15)
CL TRX
CL RL0O2 Interrupt Test

(CL15)

171

CL22 TOY 15 Out Test

(CL22)

TOY Software-Master-Reset Test (CL22)
TOY Counter Group 1 Register Test (CL22)
TOY Counter Group 2 Register Test (CL22)
TOY Counter Group 3 Register Test (CL22)
TOY Counter Group 4 Register Test (CL22)
TOY Counter Group 5 Register Test (CL22)
TOY Master Mode Register Test (CL22)
TOY Counter Register Count Test (CL22)

161
162
163
164
165
166
167
170

Pt A1 B O 00 0O 00 00 O

TOY Clock Tests

RAM Parity Tests
172

RAM

Data Parity Tests

(CL06)

Mapped RAM Data and Addressing Tests (64 TO 256 Kbytes)

Interrupt Tests

202
203
204
205
206
207
210
211
212

CLO09
CL09
CL22
CL15
CL15
CL31
CL10
CL1l1
CL10
CL30

T-11

Interrupt Tests

213*
214*

CL09
T-11

(CLO2)

System AC Fault Interrupt Test, Part 1 (CLOZ2)

ABus Dead Internal Interrupt Test (CLO2)
TOY 1MS Internal Interrupt Test (CL02)
TXCS RDY Interrupt Test (CLO02)
STOR RDY Interrupt Test

(CLO2)

OBA Internal Interrupt Test (CL02)
ETERM RDY Interrupt Test

(CL02)

RTERM Internal Interrupt Test (CLO02)
Local RDY Interrupt Test (CLO02)
RPLY Timeout Interrupt Test (CLO02)

CPU Control Store PE Interrupt Test (CLO2)
‘Manual Restart Interrupt Test (CL02)

s U O

201*

Unsolicited Interrupt Test (CL02)
CL15 TSTRT Interrupt Test (CLO2)
CLO4 CSL PE Internal Interrupt Test

CL19
CL19

ENA TXRDY Test (CL20)
ENA STOR RDY Test (CL20)

174
175
176
177
200

B A O U S U1 O

T-11

Mapped RAM Data/Addressing Test (CLO04)

173

DIAGNOSTICS

CONSOLE
OBUS

MODULE

DIAGNOSTIC

Adapter

Tests

215

QCSR0O

216

QCSR1

217
220
221

OBA

223

CL30

224

OBA

225

OBA
OBA

227

OBA

230

OBA

231
232
233
234

235

Timeout

Counter

Test

RPLY Timeout Test,

3
2
2
5

(CL20)

Part

Simulated-Read-Cycle Test,
Simulated-Read-Cycle Test,
Simulated-Write-Cycle Test

(CL20)
Part

(CL23)

Part 2
(CL23)

(CL23)

2
13

Simulated-Intr-Ack-Cycle

Test,

Simulated-Intr-Ack-Cycle
CL32 SREC SACK Test (CL29)
QBA Simulated-DMA-Read Test,
OBA Simulated-DMA-Read Test,
QBA Simulated-DMA-Write Test

Part

(CL23)

Test,

Part

(CL23)

3
3
24

CL30

RPLY Timeout Test,

RLO2-specific

Part

(CL23)

2
(CL23)

(CL23)

Part

(CL29)

QOBA Tests

236

RLO2

237

RLO2

240
241

RL0O2
RLO2

(CL29)

222

226

Test

(EDOBA)

Read Test (CL23)
Write Test (CL23)
Write/Read Test (CL23)
Test (CL23)

Indicates a special test fixture is
required;
ignored unless the fixture is installed.

10
10
2
3

the

test

DIAGNOSTICS

EDKAA

6.4

MICRO-HARD-CORE

EDKAA - MICRO-HARD-CORE DIAGNOSTIC

OVERVIEW -

(MHC)

1is

T-11

(MHC)

based

Prerequisites

Successful

execution

CDF860.DAT or

EDOBA.

CDF865.DAT

and CDF865.dat contains
signal

name

6.4.2

(MHC)

diagnostic.,
It
is
designed
to
verify the proper operation of the VAX CPU hardcore
logic required to successfully load and run micro-diagnostics.

6.4.1

EDKAA

DIAGNOSTIC

load

and

file

EDKAA

the

also

RL02

the names and

assumes

that

correct.

revision

the

CDF860.DAT

levels of

the

SDB

files.

and

start

Starting

MHC

type:

MHC<cr>

either

the

Macro

Context Prompt:
the version name
MHC

then

6.4.3

waits

Context

Prompt:

>>>,

DC>.
Once MHC has been
and number, followed by

for

the

user

type

the

started,
the
MHC

command.

Diagnostic

it will display
Prompt:
MH>.

See

Table

6-5.

Micro-Hard-Core Control Characters

Character

Function

“C

Control C
Each sub test
may
be
will
abort at
and return to

program
sub test

exited
by
typing
°C.
The
the completion of the current
the
Micro-Hard-Core
Prompt:

MH>.

Control T
If the "/PRintmode:Quiet”

“T
of

6.4.4
The
to

will
report the next
the current sub test.

Micro-Hard-Core Control

user may
change

the

SWITCH

/Bell:

append

the

switches
the

command

order

program execution.

FUNCTION

STARTQ/BELL:arg<cr>
Control

the

arguament.
OFF
ON

/ERROR DUMPS:

Switches

following

characteristics

switch was selected, typing
sub test name at completion

action
Valid

(default)
-

Sound

the

BELL

arguments

not

bell

error.

sound

STARTQ/ERROR DUMPS:arg #<CR>

Report only ~the

specified

the

number

specified

bell

Errors

argument
#.

6-17

the

are:
on

(per

error.

sub

test)

DIAGNOSTICS

EDKAA - MICRO-HARD-CORE DIAGNOSTIC (MHC)
7

STARTQ/FAULT:arg<cr>

/Fault:

action
the
take
error
a
of
detection
Upon
Valid arguments are:
specified by the argument.
CONTINUE -

ISOLATE

(default) Continue on error.

LOOP

PAUSE

error to RAM Chip.
- Loop on failing test.

and

- Pause on error

STARTI/PASS:arg_#<CR>

/PRINT MODE:

START/PRINT_MODE:arg<cr>
Control the error reporting as

the

for
tests
selected
Run
specified by argument_#.

BRIEF

the

exit

"MH>".

number

passes

See CONTINUE Command.

/PASS:

argument.

cause

Isolate the

-~ (default)

Valid

arguments

- Cancel

errors

specified

the

are:

“/PRINT_MODE:QUIET“ and report

1in

short

form,

no RAM chip

callout.

QUIET

VERBOSE -

- Suppress all but error typeouts.

"/PRINT MODE:QUIET"TM

(default) Cancel

and report errors in long form (i.e.,
RAM chip callout)

/QUICKVERIFY

STARTE/QUICKVERIFY<CR>

/NUMBER

START/Number:nl,n2<cr>
Run only tests "nl" thru

6.4.5

Run selected test with Quick Verify Flag set.
"n2".

Micro-Hard-Core Commands

The following Table describes the commands

associated

with

the

return

Micro-Hard-Core Diagnostic.

Table 6=5
COMMAND

DESCRIPTION

START

Start<cr>

Micro~Hard=Core Commands

Run one complete pass of all tests and then
the Micro-Hard-Core Prompt

STARTQ

(MH>).

STARTQLcr>

Run one pass of all tests in Quick Verify Mode (shorter
run time).

When the OQuick Verify suffix is
QUICK VERIFY MODE:
appended to either the START or LOOP command only the
RAM addresses that cross physical chip boundaries are
each bit of the EBox Control
For example,
checked.
Store is 8192 addresses deep.
1024

addresses.

The memory chip used has

DIAGNOSTICS

EDKAA - MICRO-HARD-CORE DIAGNOSTIC

(MHC)

the
specified
is
LOOPQ Command
When the STARTQ or
each address.
through
increment
not
will
program
Instead it will update uPC <02:00>, which will select a
Each bank represents 1K microwords of
RAMs.
bank of
until
wuncremented
The uPC bits will be
the total 8K.
all 8 banks have been selected at least once.

The STARTO and LOOPQ commands also executes certain sub
the default number of times.
instead of
tests once
the
reduced
(See list below.) These two differences
to run the Micro-Hard-Core
required
time
of
amount
In addition, however, they also reduce the
Diagnostic.
In other words, you cannot be
1level.
fault detection
run
sure the RAMs are functioning properly unless you
at

least one full pass of MHC.

GROUP

TESTS

FBox

F-8,

IBox
MBox
EBox
STARTC

STARTC<Lcr>

STARTD<cr>

STARTF

STARTF<cr>

Run Disk Tests only.

Run FBox Tests only.

STARTIKCr>

Run IBox Tests only.

STARTL

STARTL<Lcr>

STARTM

STARTM<cr>

STARTN

STARTN<cr>

STARTR

STARTRLcr>

STARTU

LOOP

LOOFPQ

F-B,

F-E,

and F-F

I-D

See Table

6-6

See Table 6-7.

See Table 6-8.
See Table 6-9.

Run Last Multi Box Access Tests only.
Run MBox Logic Tests only.
Run MBox UCODE Tests only.

See Table 6-10.

See Table 6-11.
See Table 6-12.

Run EBox MCF-CTX RAM and Basic UCODE Tests

Table
STARTS

F-A,

Run Clock Tests only.

STARTD

STARTI

F-9,

I-A, I-B, and
M-5 and M-6
S-C and S-D

STARTS<cr>

Run EBox SDB and CS Tests only.

See Table 6-14.

STARTU<Lcr>

Run EBox Expanded UCODE Tests only.

See Table 6-15.

LOOPLcr>

Loop on all tests continuously until stopped by R
LOOPQ<cr>

Continuiously loop on all tests in
See QUICK
(shorter run time).
LOOPC<cr>

LOOP on Clock Tests only.

Quick Verify Mode
VERIFY MODE under

STARTQ.

LOOPC

See

only.

6-13.

See Table 6-6.

DIAGNOSTICS

EDKAA - MICRO-HARD-CORE
LOOPD

DIAGNOSTIC

(MHC)

LOOPD<Lcr>

Loop on
LOOPF

Disk Tests

only.

See Table

6-7.

FBox Tests only.

See Table

6-8.

See

6-9.

LOOPF<Lcr>

Loop on
LOOPI

LOOPI<cr>
L.oop on TBox

LOOPL

Tests

only.

Table

LOOPL<Lcr>

Loop on Last Multi Box Access Tests

only.

See

Table

6-10.
LOOPM

LOOPM<cr>

Loop on MBox
LOOPN

Logic Tests

only.

See Table

6-11.

UCODE

only.

See

6-12.

LOOPN<cr>

Loop
LOOPR

MBox

Tests

LOOPR<cr>

Loop on EBox MCF-CTX RAM and Basic
See
LOOPS

Table

UCODE

Tests

only.

6-13.

LOOPS<cr>

Loop
LOOPU

EBox SDB

and CS Tests

only.

See Table

Tests

only.

6-14.

LOOPU<cr>

Loop on
6-15.
CONTINUE

EBox

Expanded

only

necessary

selected
REPORT

UCODE

See

Table

CONTINUE<cr>

Continue on to the
and

sub test.

the

error was

This

command

"/FAULT:PAUSE"

should

switch was

detected.

REPORT<cr>

Retype

6.4.6

Table

the

end of pass

report.

See

Example

6-1

Micro-Hard-Core Test Descriptions

The following set of Tables list the subtests that can be run via
the Micro-Hard-Core

Diagnostic.
Table

TEST

6-6

Clock

Subtests

MODULE

AND DESCRIPTION

SDB SHIFT
SDB SHIFT CHAIN LOAD FUNCTION
VIS MUX SELECTS
VIS DATA AND LDFUNC_REG
B
LOAD FREQUENCY REG
CLK2 START H CIRCUIT

(CLK)
(CLK)

CLK
CLK
CLK
CLK

(C-1)
(C-2)
(C-3)
(C-4)

L0217
L0217
L0217
©LO0217

CLK

(C-5)

L0217

CLK

(C-6)

L0217

(CLK)
(CLK)
(CLK)
(CLK)
(CLK)
(CLK)

CLK
CLK
CLK
CLK

(C=8)
(C-9%)
(C-A)
(C-B)

L0217
L0217
L0217
L0217

(CLK)
(CLK)

BURST COUNTER READ AND WRITE
CPU CLOCK STOP
MARK BIT STOP CONDITION
BURST COUNTER ABILITY TO COUNT

CLK
CLK
CLK

(C-C)
(C-D)
(C-E)

L0217
L0217
L0217

(CLK)
(CLK)
(CLK)

WBUS AND FBOX T3 TO T3 SHIFT LOOP
WBUS T2 CLK-EBE,EDP,FBA,IDP WBUS ENABLE
STOP FBOX IN PHASE 0 AND PHASE 1

CLK

(C-7)

L0217

(CLK) CLK3 MARK BIT

DIAGNOSTICS
EDKAA

Table

TEST

MODULE

and

6-7

MICRO-HARD-CORE

RL0O2

Disk

Subtests

DESCRIPTION

DSK

(D-1)

Disk

(non-destructive)

DSK

(D-A)

Disk

Oscillation

seek

Write-Read
1

1-1

1-85

NDSK

(D-B)

Disk

Oscillation

seek

DSK

(D-C)

Disk

Oscillation

seek

DSK

(D-D)

1-170

Disk

Oscillation

seek

DSK

1-255

(D-E)

Disk

Oscillation

DSK

(D-F)

Disk

6-8

FBox

Subtests

MODULE

and

FBOX

(F-1)

L0213

(FBM)

FBOX

(F=2)

L0212

(FBA)

SDB

SHIFT

AND

FBOX

(F-3)

L0213

(FBM)

SDB

SHIFT

AND

FBOX

(F-4)

FBOX

MODULES

FBOX

(F-5)

L0217

(CLK)

CLK

FBOX

(F-6)

L0212

(FBA)

UPC

FBOX

(F=7)

TESTS

L0213

(FBM)

UPC

TESTS

FBOX

(F=8)

Exerciser

seek 1 = 1-511
(DESTRUCTIVE) Write-Read Exerciser
Table

TEST

L0212

DESCRIPTION

(FBA)

BOX

Present

SDB

SELECT

141

VSTERM

LOOPBACK
LOOPBACK
LINE

AND

RESET

CONTROL

STORE

FBOX

(F-9)

L0212

(FBA)

CONTROL

STORE

FBOX

(F-A)

L0213

(FBM)

CONTROI. STORE

DATA

TEST

"AA"TM

DATA

TEST

DATA

TEST

"55"

DATA TEST

FBOX

(F-B)

L0213

(FBM)

CONTROL

STORE

"AA"

(F-C)

L0213

(FBM)

CONTROL

FBOX

STORE

(F-D)

ADDRESS

L0212

(FBA)

CONTROL

STORE

ADDRESS

FBOX

(F-E)

L0213

(FBM)

DECODE

RAM

"55"
"AA"

(F-F)

L0213

(FBM)

DECODE

RAM

FBOX

(F-10)

L0213

(FBM)

DECODE

ADDRESS

FBOX

(F-11)

L0213

ENARLE

"55"

FBOX

DIAGNOSTIC

TEST
TEST

DATA

TEST

DATA

TEST

(FBM)

BASIC

MICRO-CODE

FBOX

(F-12)

TEST

(EDKAF1)

L0212

(FBA)

BASIC

MICRO-CODE

FBOX

(F-~13)

TEST

L0213

(EDKAB1)

(FBM)

EXPANDED

UPC

UPDATE

TEST

(EDKAF2)

UPC

UPDATE

TEST

(FDKAR2)

FBOX

(F-14)

©L0212

(FBA)

EXPANDED

FBOX

(F-15)

L0212

(FBA)

MICRO-CODE

TEST

Table

6-9

Subtests

TEST

IBOX

MODULE

(I-1)

and

IBox

(EDKAB3)

DESCRIPTION

SDB

IBOX

(I-2)

IBOX

(I-3)

SHIFT AND LOOPBACK
SDB SELECT LINE AND ENABLE
L0208 (IBD) MODULE SDB CONTROIL

IBOX

(I-4)

L0207

(ICA)

MODULE

IBOX

(I-5)

L0217

(CLK)

CLK

141

IBOX

RESET

(I-6)

L0207

(ICA)

ICS

UPC

(ICA)

ICS

"55"

DATA

DATA TEST

IBOX

(1I-7)

L0207

IBOX

(I-8)

L0207

(ICA)

SDB

CONTROL

CHANNEI.
CHANNEL

TEST

ICS

"AA"TM

IBOX

(I-9)

L0207

(ICA)

ICS

IBOX

ADDRESS

(I-A)

L0208

(IBD)

IDRAM

"55"

IBOX

DATA

(I-B)

TEST

L0208

(IBD)

IDRAM

"AA"

DATA

TEST

IBOX

(I-C)

L0208

(IBD)

IDRAM ADDRESS

IBOX

(I-D)

L0207

(ICA)

ICS

IBOX

RAM

PARITY

(I-E)

QUIESCENT

STATE

IBOX

FOR

(I-F)

L0207

(ICA)

UJUMP

TEST

TEST
BOX CONTROL

MICRO-CODE

TEST

SIGNALS
(EDKAIL)

NOTE

When executed on
reported in place

VAX-8650
of

L0217.

6-21

CPU,

L0231

will

(MHC)

DIAGNOSTICS

EDKAA - MICRO-HARD-CORE DIAGNOSTIC (MHC)
Last Box Subtests

Table 6-10

MODULE and DESCRIPTION

TEST

(L-1)

VAX-8600

(L-2)

VAX-8650

(L-2)

(L-1)

vAX=8650

CLK and E,I,M boxes Uword MARK BIT
VSTERM MASTER RESET TEST

CLK and E;I;M boxes Uword MARK BIT

VSTERM MASTER RESET TEST
NOTE

When executed on

VAX-8650

CPU,

L0231

will

When executed on

VAX-8650

CPU,

L0230

will

reported in place of L0217

reported in place of L0220

Table 6-11

MODULE and DESCRIPTION

TEST

MBOX

(M-=1)

MBOX (M=-2)

MBOX (M-3)
MBOX (M-4)
MBOX (M-5)

MBOX (M-6)

MBOX (M=7)
MBOX
MBOX
MBOX
MBOX
MBOX

MBox Logic Subtests

(M-8)
(M-9)
(M-A)
(M-B)
(M-C)

SDB SHIFT AND LOOPBACK

L0222 (MTM) SDB SHIFT AND LOOPBACK

SDB SELECT LINE AND ENARLE
L0217 (CLK) CLK 141 RESET
L0220 (MCC) MCS "55" DATA TEST

L0220 (MCC) MCS "AA" DATA TEST

L0220 (MCC) CYCLE RAM "55" DATA TEST

L0220
L0220
L0220
L0220
L0220

(MCC)
(MCC)
(MCC)
(MCC)
(MCC)

CYCLE RAM "AA" DATA TEST
ACCESS RAM DATA TEST
CYCLE RAM ADDRESS TEST
MCS RAM ADDRESS TEST
ACCESS RAM ADDRESS TEST

Table 6-~12

MBox Ucode Subtests

TEST

MODULE and DESCRIPTION

MBOX (N-1)
MBOX (N-2)
MBOX (N-3)

L0220 (MCC) BASIC UCODE FUNCTION (EDKAM1)
L0220 (MCC) BASIC STACK UCODE (EDKAM2)
L0220 (MCC) STACK PUSH LEVEL (EDKAM3)

MBOX (N-4)

L0220 (MCC) STACK POP LEVEL (EDKAM4)

Table 6-=13

MCF, CTX, and MISC EBox Subtests

TEST

MODULE and DESCRIPTION

EBOX (R-1)
EBOX (R-2)
EBOX (R-3)

L0216 (CSB) UPC+UPC SAVE INITILIZATION
LO0215/L0216 (ECS) "55"TM 1 WORD (VSTERM) TEST
L0215/L0216 (ECS) "AA"TM 1 WORD (VSTERM) TEST

EBOX (R=7)

L0210 (EBC) CONTEXT RAM DATA TEST
L0210 (EBC) CONTEXT RAM ADDRESS TEST

EBOX (R-4)
EROX (R=-5)
EBOX (R-6)
EBOX

(R-8)

EBOX (R-9)

EBOX (R-A)

L0210
L0210

(EBC) MCF RAM DATA TEST
(EBC) MCF RAM ADDRESS TEST

LO0215/L0216

L0210

(ECS)

RAM PARITY

(EBC) MCF RAM PARITY TEST

OQUIESCENT STATE FOR UTRAP + STALL (EDKAU2)

DTAGNOSTICS

EDKAA

(R-B)
(R-C)
(R-D)

L0216
L0216
L0216

(CSB)
(CSB)
(CSB)

DIAGNOSTIC

(MHC)

BASIC UPC UPDATE TEST (EDKAU1)
EXPANDED UPC UPDATE TEST (EDKAU1l)
UJUMP REGISTER TEST (EDKAU2)

EBOX
EBOX
EBOX

-~ MICRO~HARD-CORE

NOTE

When executed on
VAX-8650
reported in place of L0217

TEST

Table

6-14

MODULE

and

EBox,

CPU,

SDB,

L0231

DESCRIPTION

(S-1)
(S-2)

MODULES SDB SHIFT AND LOOPBACK
L0215 (CSA) MODULE SDB SHIFT AND LOOPBACK

EBOX

(S-3)

SDB

EBOX
EBOX
EBOX
EBOX
EBOX

(S-4)
(S-5)
(S-6)
(S-7)
(S-8)

L0215
L0209
L0210
L0219
©L0219

(CSA)/L0216 (CSB) SDB CONTROL CHANNEL
(EDP) MODULE SDB CONTROL CHANNEL
(EBC) MODULE SDB CONTROL CHANNEL
(EBE) MODULE SDB CONTROL CHANNEL
(EBE) MODULE ICR TIME BASE COUNTER

EBOX
EBOX
EBOX
EBOX

(S-A)
(S-B)
(S-C)
(s-D)

L0210
L0217
L0215
L0215

(EBC) MODULE MCF RAM CLK3
(CLOCK) CLK 141 RESET
(CSA)/L0216 (CSB) ECS "55"
(CsA)/L0216 (CSB) ECS "AA"

(CSA)/L0216

(CSB)

ECS Addr

DATA TEST
DATA TEST

EBOX

(S-F)

L0215

(CSA)/L0216

(CSB)

ECS Addr

(EDKBU)

(S-9)

EBOX (S=-E)

SELECT LINE

L0210

L0215

AND ENABLE

(EBC) MODULE DIAG & EIS REG CLK3

Table

TEST

and C/S Subtests

EBOX
EBOX

EBOX

6-15

EBox

Ucode

(KA8600)

Subtests

MODULE and DESCRIPTION

EBOX
EBOX
EBOX
EBOX
EBOX
EBOX
EBOX
EBOX
EBOX

(U-1)
(U-2)
(U-3)
(U-4)
(U-5)
(U-6)
(U-7)
(U-8)
(U-9)

Below

L0216

(CSB) MICROSTACK TEST (EDKAU2)
L0209 (EDP)/LO210(EBC)WBUS REQ CTX (EDKAU2)
L0209 (EDP) SHIFT COUNTER FUNCTION (EDKAU2)
L0209/L0206/L0212/L0205 DATA PATH (EDKAU2)
L0216 (CSB)/L0209 (EDP) BRANCH COND. (EDKAU2)
L0209 (EDP) ALU FUNCTION (EDKAU2)
L0209 (EDP) SCRATCH PADS DATA (EDKAU2)
LO219(EBE)/L0201(CSL) CBUS/CSL-INT (EDKAU2)
L0219 (EBE) EBCS REGISTER <31:27> (EDKAU2Z)

an example

the

End

Pass

report

occurred.

Example

will

6-~1l:

End of
OF

Pass

SECTION

TOTAL

CLOCK
E SDB/CS
E RAMS
E UCODE
I BOX
M LOGIC
M UCODE
F BOX
RLO2 DSK

(sC)
(S85) =

= 00000
00000

(SR)

00000

(sSu)

(SI)
(sM)
(SN)
(SF)
(SD)

=
=
=
=
=

00009
00000
00000
00000
00000
00000

VAX-86xx

(SL)

= 00000

PASS COUNTER-= 00001
# OF ERRORS = 00009,

Report

ERRORS

TOTAL # OF ERRORS
6-23

= 00009

when

error

DIAGNOSTICS

(DCP)

MICRO DIAGNOSTIC CONTROL PROUGRAM
6.5

MICRO DIAGNOSTIC CONTROL PROGRAM

6.5.1

(DCP)

Overview

DCP is a Tl1ll based Diagnostic Utility progam designed to
control
the running of the micro diagnostics.
It is evoked by typing the
DIAGNOSE
Command
at
either
the
MACRO
Prompt
(>>>)
or
the

Micro-Hard-Core

Prompt

(MH>).

the system to the point where

executed,

and monitored.

procedure are

can

initialize

loaded,

Take

Submit
the
DCP
initialization
file,
DCLOAD.COM,
internally in order to perform the following steps.

vector.

perform a master

Enable the console's external logic
SET

EXTI

(DSM)

into

the

necessary,

interrupt,

using

command.

Force the EBox to begin executing at
address

reset.

store.

Load
other
control - stores,
initialize parity logic, etc.

the

and

interrupt

Load the Diagnostic Support Microcode
control

clock

RDY

TXCS

Stop

CPU

the

EBox

the

DCP will

The steps taken by this initialization

follows:

control

Once evoked,

microdiagnostics

and start

the

DSM

start

CPU clocks.

Pass the default diagnostic switch settings to

DSM

(via

(DC>)

and

the CBus).

Display the diagnostic context command prompt
await

commands.

NOTE

DCLOAD.COM

contains

DEBUG

command

that

leaves
the
HEX
command set enabled when it
terminates, as evidenced by the DC>> prompt.

6.5.2

DCP Control

Characters

Control

Character

Description

Interrupts the currently running micro- diagnostic and
returns
control
to
the
user.
This
places
the
microdiagnostic in the
“"pause"
state,
allowing
the
user
to examine or modify the state of the diagnostic
test environment, and then
resume
execution
of
the
microdiagnostic.

Aborts the current command, which may include the need
to
abort
a
currently
running
microdiagnostic, and
returns

control

the

user.

DIAGNOSTICS

MICRO DIAGNOSTIC CONTROL PROGRAM
<CTRL/T>

(DCP)

Commands DCP to display information about the state of
without
microdiagnostic
running
currently
the
its execution.

disturbing

6.5.3

DCP Command Summary

Command
CLEAR
DATA

Description
CLEAR DATALcr>

Clear the table of pointers defined by the SET DATA
command and should be used prior to redefining a new
set of EBox scratchpad locations for error reporting
purposes.

CONTINUE

CONTINUELcr>

This

allows

command

microdiagnostic
paused by

either

currently

the

loaded

to resume test execution after being
a

switch

setting

(/FAULT:PAUSE,

issued, single

The microdiagnostic
/FAULT:ISOLATE) or <CTRL/P>.
resumes at the test following the one that was being
executed when the pause occurred. If /SINGLE_STEP is

in effect and

CONTINUE

command

is stopped and the remaining tests are run.
stepping
A CONTINUE command, issued prior to giving either a
RUN or START command, will result 1in an error
message.

DEPOSIT

DEPOSIT/switch hex_ addr hex_ data<cr>

This command allows the user to modify the EBox
the system cache, or the WBus RAM.
scratchpad RAM,
The 32-bit hexdata 1is deposited into the hexaddr
location of the specified RAM. The CPU clock must be
running.

Valid Switches:
EXAMINE

/CACHE

/ESCRATCH

/WBUS

EXAMINE/switch hex addr<cr>

This command allows the user to examine the

contents

locations, cache
scratchpad
EBox
specific
of
locations, or WBus locations. The CPU clock must be
running.

vValid Switches:
GENERATE

/CACHE

/ESCRATCH

GENERATE file.ext<cr>

is wused to evoke the DCP
Generate command
generate/verify process for generation and validation
is not for field
of isolation data. This command
It is used to support the in-house development
use.
There are no switches
of 1isolation algorithms.
associated with this command. The only option is the
for loading the
responsible
file
name of the command

The

microdiagnostic to be generated.

oy,

/WBUS

DIAGNOSTICS
MICRO

RUN

DIAGNOSTIC

CONTROL

PROGRAM

(DCP)

RUN/switch file.ext<cr>
This command initiates the
execution
of
a
command
file
whose
purpose
is
to
load
and
start
a
microdiagnostic program.
Execution begins
with
the
first number specified in the /NUMBER switch
and ends
with
either
the
last
test
in
the
group
of
microdiagnostic tests or with the last test specified
in the /NUMBER switch.
NOTE

The CPU clock must
command to work.

Switches
provided

Switches

exceed

Switches:

upper

case)

/BELL:{GN,
Note

the

RUN

be
that

combined
in
any
order
the command line does not
characters.

BSWITCH

this

RUN

command
command

the

Command

for

switch.

(SWITCH

DEFAULTS

are

noabort,

loop,

pause,

printed

OFF1
4.

/FAULT: {ISOLATE,

ignore}
Note

continue,

/LINES:{ON,
See

for

can

Refer
to
the
description of

Valid

See

running

appended
to
the
remain
in
effect
until
completes.

See

Note

OFF}

/NUMBER:FIRST_TEST, [{<space>,<comma>}LAST TEST]
This switch is
used
to
specify
the
starting
and
ending
test.
Numbers
in
hex.
If
the switch is

omitted,

the

default

01,FF).

values

are

used

/PASSES:decimal number
(default =
The decimal
number
indicates
the
passes

execute

attempting

before

isolation.

100)
number

continuing

1If

the

(default

the

/PASSES

test

switch

not
specified, the default value (100) will be used.
A special case of /PASSES:0 modifies
the
sequencing
of
the tests so that a particular group of tests
can
be run indefinitely.
1If the user specifies a 0
pass

count,

DCP

will

run

each

the

tests

indefinitely

(fErom FIRST
to
LAST)
until
<CTRL/C>
or
interrupts
or
a fault is detected.
When a
detected, the action will be governed by the
setting of the /FAULT switch.

/PRINT_MQDE:Zbrief,
See

Note

VERBOSE?

<CTRL/P>
fault is
current

DIAGNOSTICS

MICRO DIAGNOSTIC CONTROL PROGRAM (DCP)
/SINGLE_STEP
stic execution is
when single step is enabled,ingdiagno
the proper number of
interrupted” after complet
e, along with
passes of an individual test. A messag
is displayed and the
the test number just completed, The
STEP command can
operator is prompted for input.
is followed by
be used to run the next test and The
CONTINUE
another pause when it completes.
command can be used to clear this mode and resume

full speed test execution.

SET
DATA

SET DATA escratchfiadfiress flatafiname<cr>

Where:

e '"escratch address"

"data name" is a

1-30

hexadecimal

within the EBox scratchpad RAM (0 to FF)

character

string

address

assocTated with the specified Escratch data
to
This command allows a symbolic name to be assigned

a
a location in the EBox scratchpad RAM. When
is in
microdiagnostic test detects a fault andand DCP
data taken
verbose printing mode, the "data_name"
from the associated "escratch address"TM are included
in the error report.

d files
Set Data commands are normally used in comman
tics and setting
responsible for loading microdAiagnos
maximum of 16 SET
diagnostic control switches.
time. The CLEAR
DATA commands can be used toat one
initialize the SET
DATA command should be used
information.
DATA memory prior to defining set data displa
y the
to
The SHOW DATA command can be used
t
current settings of SET DATA, along with the curren
state of the Escratch variables.

SET

ISOLATION

SET ISOLATION/switch<cr>

to modify default
This command provides a way isolat
Once the
ion.
parameters associated withremain
1in effect until
defaults are modified, they
d) .
DCP is reloaded (i.e., DIAG comman

vValid Switches:

mber

/PASSES:decimal_nu
of times each
The decimal number indicates the number
continuing to the next
test will be executed before(defau
lt = 100). It is
test or attempting isolation
be altered in the
not recommended that this number
of any
field, as it affects the confidence ylevel
Factor settings are
isolation data that may follow. always
be greater than
preferred. This number should
zero

(0).

/ERRQR*EUHPS:decimal_fiumber

m number of
The decimal number indicates the maximu
to faults with
error printouts that will occur due
test (default =
different syndromes within a given
of reducing
10). Lowering this number has theat effect
the expense of
the amount of error printouts
data for tracking
throwing away what may be useful
This number has a maximum
down an intermittent.
value of

10.

6-27

DIAGNOSTICS

MICRO

DIAGNOSTIC

SET

NAME

This

CONTROL

FROGRAM

(DCP)

NAME microdiagnostic

command

filename<cr>
normally used within a

specifies

currently

the

being

name

loaded.

in
the
fault
report
associated
files
with
extensions).
SET

SET

SWITCH

This
that

This

the

command

and
the

file.

microdiagnostic

information

1is
used to
same
name

included

locate other
(different

SWITCH/switch<cr>

command
govern

control

redefines the
the
behavior

and

running

description
including the
DIAGNOSTIC

default
of
DCP

of
each
switch
default
setting

context

switch
settings
and
DSM in the

microdiagnostics.

1is
of

provided
below,
the
switch
when

entered.

NOTE

Switches

can

combined

provided

that

exceed

characters.

the

command

any

line

order

does

not

Switches

altered with this command retain
new setting until changed again with
SET SWITCH command, or until
DCP
is

the
the

‘'reloaded.

Valid

Switches:

/BELL:{ON,OFF}
When

"ON,"

ring

each

this
time

switch
a

new

causes

fault

the
terminal
bell
to
detected and reported.

/FAULT:{ISOLATE,nQabcrt,1ocp,pause,ccntinue;igncre}

This

switch controls the action
microdiagnostic
test
detects
the

above

mutually

arguments

ISOLATE

faults

This

DCP

setting,

takes
after
a
fault.
Only one of

specified;

CONTINUE

DCP

STEP
execution.

NOABORT

This

isolation

on
the
isolation
continue
onto
continue

commands

setting

all

solid

attempt
the

with

the

1is

isolation

its

command

can

directs

faults

LOOP

Tests

within

run

/PASSES

times.

standard

error

report

CONTINUE

This

setting

prompt
or

execution.

after

STEP

solid

attempt
to

attempt

encountered.

diagnostic

After

execution

diagnostic

is
The

resume

is
completed,
DCP
test, thus providing

will
a way
after

are

targeted

When

an error

detected,

the

displayed

and

instructed
to
loop
forever
Only <CTRL/C> or <CTRL/P> can

command

all

prompt.

used

DCP

are

default,

the

isolating.

PAUSE

they

the

isolation

After

returns

which

attempt

encountered.

completed,

DCP

exclusive.

directs

test

may

causes
can

DSM

on the failing test.
terminate the loop.

DCP

reporting

command

then

to
a

return

test
used

its

failure.

The

resume

test

DIAGNOSTICS

MICRO DIAGNOSTIC CONTROL PROGRAM

(DCP)

DCP will
effect,
in
CONTINUE - With this switch
After
of its normal error reporting.
perform all
normal
its
continue
each error rcport, DCP will
occurred.
had
error
no
1if
as
sequencing
test
Isolation will not

take place.

IGNORE - This is a special switch intended only for
has no useful application in
It
microcoder use.
It directs DSM never to signal DCP that

the field.

No hardware errors
an error has occurred.
be detected or reported.
/LINES:iON,

can ever

OFF}

This switch is used by microcoders to debug isolation
If

code.

the

switch has been set to ON and DCP is

processing isolation statements, a source line number
statement is processed.
the
as
displayed
be
will
the
number of
1line
the
This line number matches
that is currently being
statement
isolation source
processed.

/PRINT MODE:{brief,

VERBOSE]}

This switch controls the level of dctail included
an

SHOW
DATA

error

1in

report.

SHOW DATA<Lcr>

and
names
symbolic
all
displays
command
This
by the SET DATA
defined
«currently
data
associated

with
The range of dlagnostlc test numbers,
command.
passes, is also displayed under this
number of
the
command for the user's information.

SHOW
SWITCHES

SHOW

SWITCHES<cr>

This command displays the current switch settings and
The default settings
switch settings.
default
the

are either those settings that were in place when DCP
loaded or those that have been modified via the
was
SET SWITCH command.

as
The current switch settings are normally the same
local settings (i.e.,
settings since
default
the
to
return
START)
or
RUN
to
switches
appending
defaults when the command completes.

defaults
from the
The current switches will differ
they are examined from within another command.
when
from the
This could occur by examining the switches
paused state of a RUN or START command which uses the

/SINGLE_STEP switch. When proceeding from that point
with the CONTINUE or STEP command, the current switch
settings will remain in effect until the initial

or START command completes.

RUN

DIAGNOSTICS

MICRO

START

DIAGNOSTIC

CONTROL

PROGRAM

(DCP)

START/switch<cr>
This command initiates

the

group

within

tests

execution
an

test

already

loaded

microdiagnostic program.
Execution begins
with
the
first
number
specified
in
the /NUMBER switch.
It
ends with either
the
1last
test
in
the
group
of
microdiagnostic tests or with the last test specified
in the /NUMBER switch.
NOTE

The

CPU

START

clock

command

Switches

Switches
remain

running

for

the

to work.

can be

provided
exceed 80
3.

must

combined

that
the command
characters.
appended to
in
effect

the

in
any
order
line does not

START

command

the

command

until

completes.

Refer
to
the
description of

this

Refer
to
description

this

Valid

Switches:

upper

case)

/BELL:{ON,
See

Note

NolLe

RUN

Command

for

switch.

(SWITCH

DEFAULTS

are

noabort,

loop,

pause,

printed

continue,

4.,

OFF1}

/NUMBER:FIRST
TEST
See

for

OFF}

/LINES:{ON,
See

the

Command

switch.

/FAULT:{ISOLATE,
ignore}
See

SWITCH

[{<space>,<comma>}

LAST _TEST]

/PASSES:decimal number
See

Note

/PRINT_&ODE:{brief,
See

Note

VERBOSE }

/SI&GLE_STEP
See

STEP

Note

STEP<cr>

This command causes the next test
in
the
currently
loaded
microdiagnostic
to
be
executed.
The STEP
command is invalid unless the
microdiagnostics
have
been
started.
Once they have been started and there
is a pause in the diagnostic execution (/FAULT:PAUSE,
/FAULT:ISOLATE, or <CTRL/P>), the STEP command may be
used.
A STEP command issued prior to giving either a
RUN

START

command

will

result

error

message.

DIAGNOSTICS
VAX 86XX MICRODIAGNOSTICS

VAX 86XX MICRODIAGNOSTICS

Table 6-16 lists the Microdiagnostics for the VAX 86XX CPU. With
the exception of Micro-Hard-Core these diagnostics are designed
to run under control of the Diagnostic Control Program (DCP).

6.6

VAX 86XX Microdiagnostics

Table 6-16
NAME

DESCRIPTION

EDKAA

Micro-Hard-Core

EDKBA

EBox Series

EDKCA

MBox Series,

Part 1

MBox Series,

Part 2

EDKIA

MBox Array Go/No Go Control Test

EDKJA

Array Minimum Functionality Test

EDKDA

Series,
Series,
Series,
Series,

Part
Part
Part
Part

3
4

EDKGA
EDKHA

MBox
MBox
MBox
MBox

EDKOA
EDKPA
EDKQA
EDKRA
EDKSA
EDKTA
EDKUA
EDKVA
EDKWA

1IBox
1IBox
IBox
IBox
1IBox
1IBox
1IBox
IBox
IBox

Series,
Series,
Series,
Series,
Scries,
Series,
Series,
Series,
Series,

Part
Part
Part
Part
Part
Part
Part
Part
Part

1
2
3
4
5
6
7
8
9

EDK]1A
EDK2A
EDK3A
EDK4A
EDKZA

FBox
FBox
FBox
FBox
FBox

Series,
Series,
Series,

Part 1
Part 2
Part 3

Series,
Series,

Part
Part

4
5

EDK5A

Array Series

EDK6A
EDK7A

SBIA Series,
SBIA Series,

Part
Part

1
2

EDKEA
EDKFA

6.7

5
6

STANDARD MICRODIAGNOSTIC COMMAND FILES

Table 6-17 lists some common Command Files that can
under the

Table 6-17
Command File
TSTCPU.COM

executed

control of DCP.

Standard Microdiagnostic Command Files

Description
@TSTCPU<LcCr>

Run one pass of the Micro-Hard-Core Diagnostic then
individual
the
of
each
pass
one
run

Micro~diagnostics.
MICROS.COM

@MICROS<cr>

Run

one

pass

Micro-diagnostics.
first.

each

the

individual

Do not run the Micro-Hard-Core

DIAGNOSTICS
STANDARD

MICRODIAGNOSTIC

Table

Command

6-17

File

QVX##4#

COMMAND

Standard

FILES

Microdiagnostic

Files

(Cont)

@QVX###<cr>
Run

one

run

pass

the

test

the

Micro-Hard-Core

sequences

(Quick Verify) the CPU
The
1individual
Quick
module

QVL###

tested

that

are

module
Verify

Table

Diagnostic

necessary

specified
tests are

then
test

by
###.
listed by

6-18,.

@QVL###<cr>
Run

one

pass

test

necessary

specified

Command

Files

###.

individual Quick
in Table 6-19.

Table

COMMAND

Command

Description

FILE

QvX202.COM
QVX203.COM

6-18:

MHC/Module

MODULE

TESTED

L0202

(SBS)

L0203

(SBA)

QVX204.COM

L0204

QVX205.COM

(MCD)

L0205

QVX220.COM
QVX222.COM

(MAP)

L0220
L0220

(MCC)
(MTM)

QVX206.COM

L0206

(IDP)

QVX207.COM

L0207

(1ICA)

QVX208.COM

L0208

QVX214.COM

(IBD)

L0214

(ICB)

QVX209.COM

L0209

(EDP)

QVX210.COM

L0210

(EBC)

QVX211.COM

L0211

(EBD)

QVX215.COM
QVX216.COM

L0215

(CSA)

L0216

(CSB)

QVX219.COM

L0219

(EBE)

QVX212.COM

L0212

(FBA)

QVX213.COM

L0213

(FBM)

QVX218.COM
QVX223.COM

L0218

(FJM)

L0223

(FTM)

QvXx217.COM

L0217

(CLK)

the

test

(Quick

This

sequences
Verify)

series

will

not

run

Verify

are

listed

Quick

Verify

of
MHC

the

that
CPU

Quick
first.

by module

Command

Files

are

module

Verify
The

tested

STANDARD MICRODIAGNOSTIC

Table

6-19

CPU

Module

”3 COMMAND FILE

MODULE TESTED

" QVL202.COM

L0202 (SBS)

QOVL204 .COM

L0204 (MCD)

QVL203.COM

L0203

(SBA)

OVL205.COM

L0205

(MAP)

OVL220.COM

L0220

(MCC)

QVL222.COM

L0220

(MTM)

QVL206 .COM

L0206

(IDP)

QVL207.COM

L0207

(ICA)

QVL208.COM
QVL214.COM

L0208

(IBD)

L0214

(ICB)

OVL209.COM

L0209

(EDP)

OVL210.COM

L0210

(EBC)

QVL211.COM

L0211

(EBD)
(CSA)
(CSB)

OVL215.COM

L0215

OVL216.COM

L0216

OVL219.COM

L0219

(EBE)

QVL212.COM

L0212

(FBA)

L0213

(FBM)

L0218

(FJM)

_ QVL217.COM

L0217

(CLK)

e ——

OVL213.COM
OVL218.COM

Quick

Verify

Command

DIAGNOSTICS

COMMAND

Files

FILES

DIAGNOSTICS

DIAGNOSTIC SUPERVISOR

(EDSAA) OVERVIEW

DIAGNOSTIC SUPERVISOR (EDSAA) OVERVIEW

6.8

The Diagnostic Supervisor (EDSAA) is a utility program designed
running, and controlling the operation of
to simplify loading,

‘

the following types of diagnostics:

LEVEL 3 - Diagnostics that are designed to run under the
Diagnostic Supervisor in standalone mode only. Typically
Functional Level Peripheral Diagnostics,
these are:
and CPU Cluster
Diagnostics,
Peripheral
Repair Level

Diagnostics.

LEVEL 2 - Diaghostics that are designed to run under the
Diagnostic Supervisor 1in either standalone or on-line
mode. Typically these are: Bus Interaction Diagnostics
and Formatter/Reliability Peripheral Diagnostics.

LEVER 2R - Diagnostics that are designed to run under the
Diagnostic - Supervisor in on-line mode only. Typically
these are Diagnostic Control Programs such as File

Maintenance and Update Utilities.

6.8.1

Diagnostic Supervisor (EDSAA) Control

The operation of the Diagnostic Supervisor is effected by

either

Control Characters (Table 6-20) or Direct Commands entered at the
DS>

Diagnostic Supervisor Prompt:

Table 6-20

Diagnostic

(Table 6-21).

Control

Supervisor

Character

Summary

Control

Character

Description

Interrupt the execution of

the

diagnostic

currently

running.

Suspend terminal output.

“Q

Resume

Table 6-21

terminal output.

Diagnostic Supervisor Command Summary

Command

Description

SET LOAD

SET LOAD device:[directory]l<cr>
Sets the default load directory to a device
and directory where the diagnostics and other

maintenance

software

stored;

€.Q.,

DMAO: [SYSMAINT] .

SHOW LOAD

SET LOAD<cr>

Display the default device and directory.

See

LOAD filename.extension<cr>
Load but do not start the file specified.

The

the SET LOAD Command.

LOAD

default extension

.EXE.

DIAGNOSTICS

DIAGNOSTIC
ATTACH

SUPERVISOR

(EDSAA)

OVERVIEW

ATTACH

dev-type link-name dev-name parameters<cr>
Define a test path based on the
device
type,
the
1link
name,
the
device
name,
and
the
parameters specified.
Table 6-22
1lists
some
common
device
types, links, and device names
along with associated parameters.
NOTE

A device must
HUB as
itself

the link
be used

attached

using

name before it
as
a
1link.

can
For

example,
DS>

ATTACH

DW780

HUB

In this command DW0
a

DW780
Level

DWO

4<cr>

is defined

that

has, in this case, a
and a BR Level of 4.
DWO
can
now be used as a link to
further define the test path.
For
example,

DS>

ATTACH

400

5<cr>

this

VS100

DWO

case VBAO

that

via
DWO.
parameters

VBAO

760440

is defined as

connected

the

a
CPU

In
addition
the
specify that the Unibus

Control and Status Register

(CSR)

address
is
760440,
the
Vector
Address is 400, and the
BR
Level
is 4 for VBAO.
2.

The

test

selected

can

path

(device
before

tested.

name)
the

must

test path

See

SELECT

command.

SELECT

SELECT device=—-name<cr>

Add

the device

to
be
Command.
DESELECT

SHOW

DEVICE

specified

tested.

See

to the

list

ATTACH

and

DESELECT

the

units

to be

SHOW DEVICE

unit

from

the

1list

specified

]

SHOW SELECTED

tested.
device-name<cr>

characteristics of the
specified.
If
ALL
1is specified
characteristics of all devices.
3

units

DESELECT device—name<cr>
Remove

Display

the

device

name

display

the

SHOW SELECTED<Lcr>

Display the
devices.,

carac

istics

all

selected

DIAGNOSTICS

DIAGNOSTIC
START

SUPERVISOR

(EDSAA)

OVERVIEW

START/SWITCH/SWITCH...<cr>

Initialize the system and begin
execution
of
the
diagnostic
program
currently in memory.
Switches appended to the
c¢ommand
change
the
characteristics
the
program
execution
as
follows:

/SECTION:

START/SECTION:argument<cr>

Do not run the default sections
the
the

Instead run only
diagnostic.
section
specifed
by
the

sections
specific
The
argument.
diagnostic.
each
to
unique
are
document for
program
the
Consult
further
/PASS:

information.

START/PASS:arg<cr>

Run the program for
number (arg) times.

If
1.
program
/TEST:

specified
the
The default is

specified
1is
0
indefinitely.

run

the

START/TEST:argl:arg2<cr>

Beyin running the diagnostic at the
first test specified (argl) and run
last
the
through
diagnostic
the
test specified

/SUBTEST:

(arg2).

START/TEST:argl/SUBTEST:argZ<cr>
an
as
specifed
1is
/SUBTEST
If

the
run
then
/TEST
to
argument
test
first
the
from
diagnostic
the
through
(argl)
specified
subtest spccified
RUN

RUN

(arg2).

file.ext/switch/switch<cr>

Initialize the system, then load and
run
with
accordance
in
specified
program
switches specified.
If no file
wextension
specified
then
default
to
.EXE.
applicable switches are
described
wunder
START
SUMMARY

the
the
is
The
the

command.

SUMMARY<cr>

Display a statistical
report
describing
the
performance
of
the
diagnostic
to
date.
Normally you would ask for
a
summary
report
after
a diagnostic has run, or you would type

the
of
execution
the
interrupt
to
“C
diagnostic, ask for a summary report, and then
the
running
continue
to
CONTINUE
type
diagnostic.

CONTINUE

CONTINUE<cr>

Continue execution of the diagnostic currently
in memory.

DIAGNOSTICS

DIAGNOSTIC
ABORT

(EDSAA)

OVERVIEW

ABORT<Lcr>
Execute

the

clean

return

the

system

WMMOWMg

SUPERVISOR

the

state:

DS>.

Normally

the

you

known

necessary

state

Supervisor

This

aborting

routine

diagnostic

the

command

want

a
to

return

recommended

execution

would

and

wait
method

diagnostic.,
do

this

after

diagnostic execution has been interrupt either
because
of
a breakpoint or because you typed

“C.

SET

FLAGS

‘

SET

FLAGS

Set

the

arg,arg,arg<cr>

program

control

flags

specified

arguments.

Valid

control

HALT

flags

LOOP

are:

(DEFAULT : OFF )
execution

the

Stop

diagnostic

an error

(DEFAULT:OFF)

Loop

that
will

detects
break the

the

Diagnostic

detected.

the

first

test

an
error.
loop
and

Typing °C
return
to
Supervisor
prompt:

DC>.
BELL

IE1

(DEFAULT:0OFF)

Sound

time

an error

(DEFAULT:OFF)
except

those

the

Inhibit

all

forced

diagnostic program or
Supervisor.
IEZ2

the

Diagnostic

message.

(DEFAULT:OFF)

Inhibit

associated

(DEFAULT:OFF)

normally

1Inhibit

extended

with

(DEFAULT:OFF)

the

report

displayed

execution

when

each

summary

that

diagnostic

complete.
Run

the

Quick

the

any

message.

(statistical)

QUICK

messages
either

the

information
error

IES

each

(DEFAULT:0OFF) Inhibit
all
but
the
first
three
lines
(Header
Information)
associated
with
each
error

IE3

bell

detected.

Verify Mode.
diagnostic run

diagnhostic

This will reduce
time.
In
many

cases
the
diagnostic
does this by
shorting
test
algorithms
and
by
reducing- the
number
of passes per
test.

TRACE

(DEFAULT:OFF)

Report

(name)

each

executed.

OPERATOR

the

test

header

line

(DEFAULT:0N) When set indicates that
an
operator
1is
available
should
operator intervention be required.

DIAGNOSTICS

DIAGNOSTIC SUPERVISOR (EDSAA) OVERVIEW

extended
Enter
(DEFAULT:0N)
1limits and
all
Display
dialogue.
any
with
associated
defaults

PROMPT

questions
operator

(DEFAULT:OFF) Set all flags.

ALL

will

HALT

with

assocliated

response.

Note:

take presidence over the

LOOP.

SET FLAGS DEFAULT

SET FLAGS DEFAULTLcr>

Restore the Control Flags to their default
OPERATOR and PROMPT set, all others
state:
cleared.

SHOW FLAGS

SHOW FLAGS<cr>

the SET FLAGS command.

CLEAR FLAGS

listed

flag

Display the state of each

CLEAR FLAGS arg,arg,arg<cr>
Clear the flags specified by

the

wunder

arguments.

The flags and their effect on the execution of

a diagnostic are described under the SET FLAGS
the SET FLAGS DEFAULT
Also see
command.
command.

SET EVENT FLAGS

SET EVENT FLAGS arg,arg<cr>

the
by
specified
flags
Set the event
The arguments which range from 1
agruements.
through

are:

errors

detected

Directs VMS to log

retry
the
execute
to
Directs VMS
algorithms when an error is detected and

the diagnostics in the System Event.

reported by a diagnostic.

3-23

These are program specific event flags.
individual diagnostic
the
to
Refer
details.
specific
for
documents
ALL

CLEAR EVENT FLAGS

Set all Event Flags.

CLEAR EVENT FLAGS arg,arg<cr>

the
by
Clear the Event Flags specified
The flags and their effect on the
arguments.
execution of a diagnostic are described under
the SET EVENT FLAGS command.

SHOW EVENT FLAGS

SHOW EVENT FLAGS<cr>

Display the state of each

Event

under the SET EVENT FLAGS command.

SET BASE

SET BASE address<cr>

Flag

listed

Set the base address to the value specified by
Once the base address is
address argument.
set all address references will be offset by
For example,
the value of the base address.
if the base address was set to 200 and the
the
entered,
were
50
EXAMINE
command
the
display
would
Diagnostic Supervisor
contents of address 250.

DIAGNOSTICS

DIAGNOSTIC

SET BREAKPOINT

SET

BREAKPOINT

Insert

at the
argument.

address

attempts

specified
return to
Prompt:

OVERVIEW

execute

the

address

the

instruction

specified
program
in

the

address,
interrupt
execution
and
the
Diagnostic
Supervisor
Command
DS>.

the

(EDSAA)

address<cr>

breakpoint

the

see

SUPERVISOR

See

CLEAR

the

CONTINUE

BREAKPOINT

command.

Also

command.

NOTE

The
up
CLEAR BREAKPOINT

CLEAR

Diagnostic Supervisor will
to

the

address

SHOW BREAKPOINT

independent

BREAKPOINT

Remove

ALL

support

breakpoints.

address<cr>

breakpoint

specified

the

argument

ALL

the

an address

then

that

1is

address
is

set

specified

clear all

instead

breakpoints.

SHOW BREAKPOINT<cr>

Display
the
address
associated
with
breakpoints that are currently in effect.
SET

DEFAULT

the

argument.

SET

DEFAULT

Set

the

argl,arg2<cr>

default

DEPOSIT

all

qualifers

commands

where

for

the

argument

EXAMINE
1

and

represents

length
and
argument
2
represents
radix.
Valid data length arguments are:

the

“,

data

BYTE
WORD

08
16

bits
bits

LONG

bits

Valid

arguments

HEX
DEC

Hexadecimal
Decimal

OCT

Octal

are:

(default)

EXAMINE/argl/arg2

address<cr>
Display the contents of the address
specified
in
the
data
length specified by argument 1,
and in the radix specified by argument 2.
Valid data

length

/B - Byte
/W = Word
/L

(08

(16
Longword

Valid

arguments

radix arguments

ASCII

no arguments

contents
specified

of
by

are:

bits)
bits)
(32 bits)

/H - Hexadecimal (base
/D - Decimal (base 10)
/0 = Octal (base 8)
N

EXAMINE

Radix

(default)

are:
16)

bytes
are specified

then display

the

the
address
wusing* the
values
the last SET DEFAULT command.

DIAGNOSTICS

DIAGNOSTIC SUPERVISOR (EDSAA)

OVERVIEW

If the address is
proceeded
by
one
of
the
then interpret the address
symbols
following
in the

indicated.

radix

$Daddress
¢$Haddress
$0address

- Decimal
-~ Hexadecimal
- Octal

DEPOSIT/argl/arg2 address data<cr>
address
the
1in
specified
data
Deposit the
If no arguments are specified then
specified.
radix
and
length
interpret data in the data
DEFAULT
SET
1last
the
by
specified
values
those
The arguments are the same as
command.

DEPOSIT

for

the

EXAMINE

NEXT arg<cr>
Execute
the

instructions

command.

decimal

number

specified by the argument.

macro

display the new PC and the next 4 bytes.

Then

NOTE

Normally this command would be used in
conjunction with breakpoints.
Table 6-22

Device List for ATTACH,

SELECT,

and

DESELECT

Commands

Device
Type

Link

Device
Name

7
Additional Parameters

DWa

DWa
DWa

CRa

DMC11
DR11B

XMan
?7a

DR780

SBI

??a

DZ11
KA780

DWa
SBI

TTa
KAn

XMan
LPa

MS780

SBI

MSa

<tr>

RKO6
RKO7

DMa
DMa

DMan
DMan

CR11

DUP11
DW780

KMC11
LP11

PCL11
RH780

DWa
SBI

DWa
DWa

DWa
SBI

XJan
DWa

??a
RHa

DWa

DMa

RL11

Dwa

?7a

?7an

RMO3

RHa

DRan

RP0O4

RHa

DBan

RPO5
RPO6
RPO7
TEl6

RHa
RHa
RHa
MTa

DBan
DBan
DBan
MTan

TMO3
TS04

RHa
Dwa

MTa
MTan

TU45

MTa

MTan

TU77

MTa“

MTan

RK611
RLO2

?7a

6-40

DIAGNOSTICS

DIAGNOSTIC

SUPERVISOR

(EDSAA)

OVERVIEW

The definitions for the additional parameters are:

6.9

Parameter

Description

Radix

Range

Adapter TR Number
Adapter BR Level
Massbus Drive
Unibus CSR Address
Unibus Vector
Unibus BR Level

Decimal
Decimal
Decimal
Octal
Octal
Decimal

1-15
4-7
0-7
760000-777776
2-776
4-7

RLO2

RESIDENT VAX MACRO-DIAGNOSTICS

Table 6-23 lists the Macro-Diagnostics
RL02 load medium.
Table

that are

available on

RL0O2 Resident VAX Macrodiagnostics

6-23:

Name

Description

EVKAA.EXE

VAX Hardcore

EDSAA.EXE

VAX 8600 Diagnostic Supervisor

(8600/8650)

EDKAB.EXE
EVKAB.EXE
EVKAC.EXE

(8600/8650)

EVKAD.EXE
EVKAE.EXE

VAX
VAX
VAX
VAX
VAX

EVCAA.EXE
EVCBA.EXE

RH780 Diagnostic
DW780 Repair Diagnostic

DW780,

CI780,

EVCGA.EXE
EVCGB.EXE
EVCGD.EXE

CI780
CI780
CI780
CI780

Repair
Repair
Repair
Repair

EVGAA.EXE
EVGAB.EXE

CI780 Functional Diagnostic Part
CI780 Functional Diagnostic Part

EVMAA.EXE
EVMAB.EXE
EVMAC.EXE
EVMAE.EXE

VAX Generic Tape Exerciser
TMO3-TE16/TU45/TU77 Function Timing

EVMBB.EXE
EVMBD.EXE
EVMBE.EXE

TU81 Front End/Host Functional Diagnostic,
VAX TU80 Functional Diagnostic Part 1
VAX TU80 Functional Diagnostic Part 2

EVQTF.EXE
EVQTM.EXE
EVQTS.EXE

TM78 Loadable Driver
TMO3-TE16/TU77 Loadable Driver
VAX TS1l1l Standalone Driver

EVQUE.EXE

VAX UBE Driver/UBE QIO Driver

EVRLA.EXE

VAX UDA

EVRLB.EXE

VAX RA60/RA80/RA81

EVSBA.EXE

Autosizer

EDCLA.EXE

EVCGC.EXE

EDKAX.EXE

the

Instruction Test

Basic Instruction Exerciser
Basic Instruction Exerciser
Floating-Point Exerciser

Compatibility Mode Instructions Exerciser
Privileged Architecture Exerciser

DR780,

Level
Level
Level
Level

RH780 SBI Exerciser

Diagnostic
Diagnostic
Diagnostic
Diagnostic

(8600/8650)

Part 1
Part 2
Part 3
Part 4
1
2

Tests
TMO03-TE16/TU45/TU77 Control Logic Tests
VAX TM78/TU78 Control Logic Diagnostic

and

RA Drive

Level

Diagnostic

Formatter

VAX 8600 CPU Cluster Exerciser

(8600/8650)

e
-

CHAPTER
SYSTEM

7.1

INFORMATION

VAX 8600 TO 8650 DIFFERENCES/UPGRADE

The packaging,

reliability,

and features of the VAX

8650

are

the

same as
the VAX 8600.
The physical characteristics and footprint
The VAX 8650 delivers 1.44 times the performance of
are the same.
The performance improvement has been achieved by
the VAX 8600.
CPU
the
increasing the clock rate from 50 MHz to 72 Mhz, reducing

microcycle time

from 80 nsec to 55 nsec.

and requires
The increase in clock rate requires two new modules,
be at specified revisions as per the
other modules
certain
that
following table.
for

the

VAX

Note that the MCC and CLK modules are new modules

8650.

Modules Pertaining to VAX 8600/8650 Upgrade
VAX

VAX

8650

Revision

L0220

L0230

—

L0212
L0200
L0200
4 Mb
L0226
4 Mb
16 Mb L0225
64 Mb L0235

L0212
-===L0200
L0226
L0225
L0235

8600

Module Name
MCC--MBox Control

CLK==Clock
MCD--MBox Data Paths
MAP--MBox Address Paths
IDP--IBox Data Paths
EBD--EBox Data Paths

FBA=--FBox Adder
MOS Memory Array,

MOS Memory Array,

MOS Memory Array,
MOS Memory Array,
MOS Memory Array,

L0217
L0204
L0205
L0206
L0211

4 Mb

NOTES

(MCC) and L0231

L0231
L0204
L0205
L0206
L0211

make

(CLK)

F1l
El
H1
El

H1
<D1
=,>D1
Any
Any
Any

the

The L0230

The revision shown for the L0204, L0205, L0206,
L0211,
and
L0212
is
the
minimum
revision
required to upgrade
from
8600
to
8650.
If
are not up to minimum revision,
modules
these

861UP-AA upgrade kit.

the upgrade preregquisite kit,

861lUP-BA, must be

ordered.

L0226,
above,
The L0200, revision level D1 or
L0235 are backward compatible with
and
L0225,
the VAX 8600,

only

VAX/VMS

The L0200 below revision level D1 can

The minimum

used on the VAX 8600.

required

support the VAX 8650

version

is Version 4.3.
7-1

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INFORMATION

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SYSTEM

7.2

INFORMATION

KA8600/8650

and

Microcode

Listing

Information

Last

Size

Term

List

Module

Addr

(DxW)

Used

Name

Location

256x32

ECODE

EDP/209

ESC

1FF

CTX

1FF

512x4
512x48

CONTEXT

FADD

EBC/210
FBA/212

3FF

1Kx8

FADD

FBM/213

FDRAM

FMUL

FBM/213

FBMCS

MCF

EBC/210
ICA/207

MCF
ICS

FADD

FDRAM

FMUL

MCF
IBox

KA8600

1FF

512x40

Control

ESC

256x16

256x52

IBOX

Specific RAM and Microcode

Listing

Console
Label

FBACS

Information

Control

Last

List

Module

Addr

Size
(DxW)

Term

Store

Used

Name

Location

Label

1FFF

8Kx92

KA8600

ECS

FFF

4Kx20

KA8600

256x80

UCODEOQ

CSA/215
CSB/216
IBD/208
MCC/220
MCC/220
MCC/220

EBox

IDRAM

MBox

7;2.3

RAM

INFORMATION

Store

Context

7.2.2

Common

LISTING

I ve B i o

KA8600/8650

o BT

7.2.1

RAM AND MICROCODE

CYCLE

256x20

CYCLE

Access

256x1

ACCESS

Console

IDRAM

MCS

CYCLE
ACCESS

KAB650 Specific RAM--and ‘Microcede Listing Information
Control

Last

Sizer

Store

Addr

(DxW)

Term
Used

1FFF

8Kx92

EBox

IDRAM

Location

Console
Label

KA8650

CsSA/215

ECS

4K x20

REBESD

UCODES

H
N

Access

CYCLE

256x20

Module

FFF

256x80
256x1

MBox

List
Name

CSB/216

ACCESS

IBD/208
MCC/230
MCC/230

ACCESS

CYCLE

MCC/230

CYCLE

IDRAM

MCS

SYSTEM

Descriptions

Field
Control
Last

Store:

The

Address:

namc

the

control

store.

The last address within the range of the
control

Size

INFORMATION

Size of the control store:
Depth
(D,
locations) X Width (W, number of bits).

(DxW):

specified

store.

number

The term used in the listings files which indicates
store
control
specified
the
of
contents
the

Term Used:

location.
Listing

Name:

The
1listing
name
where
the
contents
of
the
specified
control store can be found.
Listing has
a

.MCR extension.

Module Location:The module mnemonic and
control store
Console

Label:

module

number

where

the

EXAMINE

and

located.

The console mnemonic
DEPOSIT commands.

used

Note

with

the

NOTES

With the exception of the ESC, the HEX debugger
to
stopped
clock
the
and
loaded
be

must

deposit/examine

CONTEXT RAMs

these control stores.

The

The file extension for
the -listing
files
|is
The actual source files
.MCR (e.g., FADD.MCR).
(for loading
from
the
console
disk
to
the
control

packed

stores)

are

have

normalized)

RAMs.

either

.PHY

.BPN

(binary

(physical/ASCII)

extension.

During

software

system

reads

initialization

KA86n.REV

(where

the

n=0

console
for

KA8600 and n=5 for a KA8650).
The contents
of
file
1is
used to assure that the correct
this
version of the microcode is loaded.

INTERRUPT

Level

Fault

IPR

SBI

0 Alert

SBI

1 Alert

1A
19

IPR

None

IPR

IPR 18
IPR
IPR

IPR

Timer

£l
L]
*

00C

Internal

064

External
External

264

«»

054

Internal

.
«

»
«

060
05C

External
External

«
.
.
«

260

25C

External
External

»
o

058
258

External
External

050

External

250

External

«
.
.
.
.
.
.

0CO

Internal
External
External
External
External
External
External
Internal
Internal
External
External

SBI

REQ

7/UNIBUS

SBI

REQ

7/UNIBUS

SBI

0
1

REQ

6/UNIBUS

REQ

6/UNIRUS

SBI

REQ

4/UNIBUS

SBI

REQ

4/UNIBUS

IPR

None

Assigned

None

Assigned

IPR

None

Assigned

.
.

IPR

Software
Software
Software

IPR
IPR

IPR

Software
Software
Software

IPR
IPR

Software
Software

IPR

Software

IPR

Software
Software
Software
Software
Software

IPR
IPR
IPR
IPR

7
7

AST

Request

only

from

two

Generally,

the

ABus

4
4

.
.

140-17C
340-37C
OF8
OFC
100-13C
300-33C

]

OF
Regquest 0E
Request 0D
Request 0cC
Request 0B
Request oA
Request 09
Request 08
Request 07
Request 06
Request 05
Request 04
Request 03
Request 02

represents

Future

180-1BC
380-~3BC

OBC

Software

.
.

.
«

OBS8
0OB4

Software

.
«

«
«

OBO
OAC

Software
Software
Software

Software

OAS8

OA4

Software

0AO

Software

.
.
.
«

«
»
»
«

09C
098
094
090

Software
Software
Software
Software

08C

Software

«»

088

Software

084

Software

Delivery

Software

the

1CO0-1FC
3C0-3FC

Request

originate
them.

the

Compare

Assigned

require

Silo

Source

SBI 0 REQ 5/UNIBUS BR 5
SBI 1 REQ 5/UNIBUS BR 5
Console Terminal Receive
Console Terminal Transmit

IPR

1E.

£l

Silo

None

table

IPR

SBI
SBI

Interval

*®

Assigned

.
Ccmpare

SBI

This

Error

SBI

SBIA

SBIA 0 Error
SBI 0 Fault .

Error

Box

IPR

.
.

CPU
SBI
SBI

Vector

Assigned .
Power Fail
0 Fail
. .
1 Fail
.
.

None

IPR

1F
1E

IPR

LEVEL ASSIGNMENTS/SOURCES

Condition

7.3

INFORMATION

SYSTEM

those
SBI

external

adapters

interrupts
SBI

devices

which

can

attached

supports hardware interrupt levels
10
through
attachments may make use of this capability and
assignment of additional locations in the SCB.
ABus

INFORMATION

SYSTEM

014

018
01cC
020
024
028
02C
030
034
038
03C

040
044
048
04cC

050
054
058
05C
060
064
068/080
084
088

Fault/Abort

Kernel Stack Not Valid
CPU Power Fail

Abort
Interrupt

DEC Reserved Opcodes &
1Instructions
Privileged
Reserved Customer Opcodes
Reserved Operands
Reserved Addressing Modes

Arithmetic
Unused

Single Bit

£
o}

Trap
Trap
Trap

Trap

Interrupt
Interrupt

Error

Interrupt

Interrupt
Interrupt
e

4/UNIBUS
5/UNIBUS
6/UNIBUS
7/UNTRUS

Interrupt
Interrupt

Interrupt
Interrupt
Interrupt
Interrupt
Interrupt

Interrupt

Interrupt
Interrupt
Interrupt
Interrupt

Interrupt
—— -

Interrupt

BR
BR

—

Interrupt
Interrupt

Console Terminal Receive
Console Terminal Transmit
0 REQ
0 REQ
0 REQ
0 REQ

Interrupt

Unused

SBI

Fault

T
T
.

Unused
CHMK Opcode
CHME Opcode
CHMS Opcode
CHMU Opcode
SBI O Silo Compare

100-13C SBI
140-17C SBI
180-1BC SBI

1CO0-1FC

Fault/Abort

Fault
Fault
Fault/Abort
Trap/Fault

OFC

Fault

Fault
Fault

Translation not Valid
Trace Pending
Breakpoint
Compatibility Mode

SBI O Alert
SBI 0 Fault
SBI O Error
SBI O Fail
Unused
Software Request 01
Scftware Request 02 or
AST Delivery
Software Request 03
08C
Software Request 04
090
Softwarc Request 05
094
Software Request 06
098
Software Request 07
09C
Software Request 08
0AO
Software Request 09
0A4
Software Request oA
0AS8
Software Request 0B
0AC
Software Request 0C
0BO
Software Request 0D
0B4
Software Request OE
0B8
Software Regquest oF
0BC
Interval Timer
0Cco
0C4/0EC Unused
Console Block Storage
0FQ
OF4
OF8

Fault

Access Control violation

Array

.
L

Unused

Machine Check

bt et e

004
008
00C
010

Interrupt

Interrupt
Interrupt
Interrupt
Interrupt

ok ot ot ok ok ok ok ot o ot o ol el O

000

Type

Name

Pt ok ot ok ok ek Aa) €D GAD B

Vector

~J O

e’

VAX 8600/8650 SYSTEM CONTROL BLOCK

SYSTEM

INFORMATION

Vector

Name

Type

200-24C

Unused

———

Code

250

SBI

Silo

Interrupt

254

SBI

Fail

Interrupt

258

SBI

Alert

Interrupt

25C

SBI

Fault

Interrupt

260

SBI

Error

Interrupt

Compare

264-2FC

Unused

300-33C
340-37C

SBI

REQ

4/UNIBUS

SBI

REQ

5/UNIBUS

380-3BC

SBI

Interrupt

REQ

6/UNIBUS

3C0-3FC
400-7FC

SRI 1 REQ
Unused

7/UNIBUS

Interrupt
Interrupt

1
1

————

Code

BR
BR

———

Interrupt

Description

Service

2
3

Service

via WCS

Reserved

Kernel

Stack

(Interrupt

Stack

selected)
Interrupt

(if

Stack

no WCS

HALT)

NOTE
The

Interrupt

from
SBI
is
added
microcode
determines

7.5

CONFIGURATION

7.5.1
The

Kernel

basic

end

The

all

parts

1.
2.

system

the

which

adapter

SBI

"Kernel"

needs

are

contains

are

offset

service.

make

are

the

CPU

base

derived.

the

following:

(1)

Adapter

(1)

DF1l12

modem

[(for

DW780

UNIBUS

adapter

ECC

Front

MOS memory
End

system

two parts

packages

CPU cabinet
DB86

SBI

GUIDELINES

These

system

kernel

for

by a page (200 words).
The offset
by
the
EBox
Interrupt
handling
after it examines CSLINT <22:21> and

System

cabinet.

which

Vectors

(up

Cabinet

systems

only

(1)
68

(FEC)

Megabytes)
(1)

(1)]

and

level

the

front

machine

from

SYSTEM

INFORMATION

‘
CPU CABINET

FRONT END
CABINET

RLO2-FK O

MS86

BA11-AL

260 MB

|@|Z2|e|lZ|ela 2

cjclelzjlalElE
1<

MAX

UBA O

@ | @
| »
»
<<

ee]

«<|<|<|E]l=|=2|<«

HEIEIEE
=

A
@

8o
|255
2188
o)
o
Qo
O
O
u
-

RESERVED

876
POWER CONTROL

BBU

FOR 50 Hz
TRANSFORMER

MR- 16591

KERNEL SYSTEM ~ FRONT VIEW

Figure 7-3

Kernel System - Front View

Nomenclature:

CI780-MA

SBI-based Computer Interconnect Adapter

DB86-AA

SBI Adapter

DW780-MA

SBI-based UNIBUS Adapter

FP86-AA

Floating Point Accelerator

(SBIA)

IDTC

(comprised

option

DW780-MA

RB86-AA

RES

Reserved for expansion

STD

Standard, part of basic KERNEL package

7.5.2

and

UDA50~-A)

CPU Cabinet Expansion

The CPU can accommodate the following:

CI780-MA

Computer Interconnect (1)

DB86-AA

SBI Adapters

(2)

DW780-MA, DW780-MB

UNIBUS adapters (2)

4.,

FP86-AA

Floating Point Accelerator (1)

MS86-AA, BA, CA,

(up to 260 megabytes with battery backup)

RB86-AA

IDTC option

(1)

These options have dedicated and pre-wired

cabinet.

Only

the

proper

variations

configured into the CPU cabinet.

7-9

slots

these

within

the

CPU

options can be

SYSTEM

INFORMATION

MODULAR POWER SUPPLIES (MPS)

MEMORY

cPU

(FPA)|

ABUS

«— IDTC—

MEMORY

260 MB

“wl|

o | @

KAB86

ABRIEIEIE
-

HHHHEHEHIEHEEEE
o181
@l
ldl%]lz]
3

MS86-AA

MS86-BA

§§§£~c§§§ma§§

876

BBU

POWER CONTROL

CPU CABINET — FRONT VIEW
MR-16583

Figure

7-4

CPU Cabinet

= Front View

The

CPU
has
enough
power
and
cooling
to
handle
configuration,
as
is
1illustrated
below,
without
additional power supplies.

The

CPU

Memory,

the

cabinet
CPU,

kernel

7.5.2.1

can

ABus,

and

divided
I/O.

All

into
four

four

the maximum
requiring any

separate

backplanes

are

backplanes:
standard

system.

with

CPU Backplane - The CPU backplane
contains
all
and the memory controller.
It also has reserved

the
CPU
slots for
the FP86-AA option.
The design of the KA86 CPU requires the use of
substitution
modules
1in the CPU backplane when the FP86-AA is not

modules

present.

the

FP86-AA

present,

(FBM)
and slot 8 an L0212 (FBA).
slot 7 will contain an L0218 (FJM)

7.5.2.2

slot

will

contain

L0213

If the FP86-AA is not installed,
and slot 8 an L0223 (FTM).

Memory

Backplane - The
memory
backplane
accepts
the
BA,
CA,
or
DA
ECC
MOS
memory
boards, for a maximum
of 260 megabytes.
The
MS86-AA
option
is
an
L0226
4
megabyte
module.
It
may
be used on both the VAX 8600 and 8650.
The MS86-BA option is an L0200
module
with
4
megabytes.
L0200
MS86-AA,
capacity

modules
below
revision
Dl
L0200 modules, with revision

can only be used
levels of D1 and

on the VAX 8600
upward, can
be
MS86-CA is an L0225

while
used
on
both
the
VAX
8600
and
8650.
The
16 Mb
memory board that takes up the space of two
backplane
slots.
It
may be used on both the VAX 8600 and 8650.
The MS86-DA is an L0235
64 Mb memory board that takes up the space of two backplane
slots.
It
may
also
be
wused
on both the VAX 8600 and 8650.
The system
memory backplane cannot be expanded to
any
external
memory.
No
other memory is supported on the system.

When

the

installing additional memory array modules, always start
from
1lowest
slot number and work your way up.
For example, if the

system currently has three 4 Mb array modules (12 Mb) in
slots
1,
2, and 3, install the fourth array module into slot 4.
This method
of module
wutilization
(contiguous
from
slot
1
through
8)
is
recommended but not mandatory.
In other words, you can interchange
memory modules in any slot (1-8) for troubleshooting procedures.

7-10

SYSTEM

TNFORMATTON

If memory modules of unlike sizes are installed in the same system,
install
the
larger
capacity
modules first.
If a combination of
four 64 Mb and 16 Mb modules have already been installed, one 4
Mb
module may be installed in slot 8.

Use

L9200

Memory

Load Modules

The L9200 is a memory array
load
module,
It
is
used
to
put
the
minimum
specified
1load on the
appropriate regulator.
This module is to
be
used
in
systems
that
have
an
insufficient number of
array modules for correct loading.
If there is
no
memory
array
module in slot 5 or 8, then an L9200
is required in those slots.
There is an
exception
to
this
rule
for
systems
that
are
wusing RL02
version

2 and 3 packs.
For these cases,
array
module
must
be installed in slot
slot 7 is empty, it must have an L9200.

memory

and

7.5.2.3
ABus Backplane - The ABus, which performs critical
timing
and
data
transfers
from
the
SBI
to
the
CPU,
1is
capable of
supporting two DB86-AA SBI Adapters (SBIA).
The first unit (SBIAOQO)
is
the SBI adapter for the I/0 backplane.
The second unit (SBIAl)
is used for additional SBI expansion capabilities.

7.5.2.4
1I/0
Backplane - The
1I/O
backplane
is
a
dedicated,
pre-wired
SBI, UNIBUS backplane than can support one CI780-MA, one
DW780-MA,

one

DW780-MB,

and

RB86-AA.

The
CI1780~-MA
1is
wused
for
connection
environment.
The CI cables connect to the
the CPU cabinet.

The DW780=MA is
included
with
the
Kkernel
system.
The
UNIBUS
for
this
DW connects to the BAll UNIBUS drawer in
the front end cabinet.
This adapter is dedicated for front
end use only.

The

I1/0

DW780-MB

designed

backplane,

for UNIBUS expansion

The UNIBUS

drawer in a UNIBUS expansion
the front end cabinet.
4.

to
a
cluster
rear bulkhead of

for this

out

DW connects

cabinet mounted

the

to a BAll

the

left

The RB86-AA is comprised
of
a
DW780-MA
and
a
UDAS5S0-A.
These options mount in a reserved area of the I/O backplane
which supports a TU81 controller module.
Note
that
these
three
SPC
UNIBUS
slots
are wired specifically for these

options

(UDA50 and TU81 controller)

and will not work

with

other
UNIBUS
options.
Furthecrmorc,
this
UNIBUS
is
terminated within the I/O backplane (M9302 in slot
1)
and
is
not intended to be expanded beyond the CPU cabinet on a
permanent

Contact

basis.

your

information

1local

field

expanding

support

organization

for

this UNIBUS for troubleshooting

purposes.

The M9040 module installed in slot 5
provides
termination
for
the
SBI.
This
module
must
be
removed if SBIO is
expanded

to an expansion cabinet.

7-11

INFORMATION

4— DDV 11-CK—#@—DD11-CK —sft————-DD11-DK

|3
19

18 17 16 156 14 13 12 11

RLv12

DMZ32-M

24 23 22 21

18U

09 08 07 06 05 04 03 02 01
DEUNA-AA

15U

DMZ32-M

29 28 27 26

DD 11 DK e

18U

DMZ32-M

15U

DMZ32-M

15U

18U

DMF32-M

SYSTEM

BA11-AL FRONT END CABINET
MR- 16595

Figure

7.5.3

The

7-5

Front

BAll-AL

End

Front

End

Cabinet

RLV12

controller,

Within

the

(FEC)

contains

DBAll-AL

FEC

there

1is

controlled

the

expansion

space

console

boxes

and

reserved

RL02
UNIBUS

for

disk,

the

backplanes.

mounting

50HZ

transformer.
The

BAll-AL

the

DW780-MA

(DWO)

the

CPU

cabinet

and 1is configured with five UNIBUS system units and one QBus
unit (for the console).
The standard kernel system,
shown
includes:
1.

DEUNA

(1)

DMF32

(1)

DMZ32

(4)

system
above,

This is the
MAXIMUM
configuration
allowed
within
this
BAll-AL
mounting
box
and
is not expandable.
You can, however, alter the
UNIBUS configuration within the BAll-AL by replacing
some
of
the
options.
Furthermore,
this
UNIBUS
may
be expanded to a second
BAll-A

drawer mounted

'BAl11-AL/AM

options

7.5.4

The

within

the

BAll-AL/AM

DD11-DK.

EXPANSION

The

UNIBUS

RULES'

Front

End

EXPANSION

can
maximum

expansion

for

cabinet.

details

Refer

c¢onfiguring

BAll-AL.

RULES

accommodate
output

six

power

system
the

units,

BAll-A

box

DD11-CK
cannot

exceed

500 watts.
The power supply in the BAll-A box is partitioned
into
two
areas;
the
first area containing the first four system units
and the second area containing the remaining two system units.
The

power

supply

rated

96 A.

follows:

System

unit

1-2

System

unit

3-4

System unit

1-4

+15 V

3 A

5-6

-15 V
+5 V
+15 V

3 A
32 A
5A

-15

1.5 A

System

unit

The

system units

are

SYSTEM

{331 1-DK

DD11-DKe—

+5 VOLTS

)

+15 VOLTS 5 AMPS

09 08 07 06 05 04 03 02 01

+5 VOLTS

32 AMPS

" +5VOLTS

32 AMPS

18U

19 18 17 16 15 14 13 12 11

29 28 27 26 25 24 23 22 21

D011 DK memmrsmmmii

18U

15U

1 SU

18U

15U

INFORMATION

32 AMPS

+15 VOLTS
3 AMPS

-~156 VOLTS 1.6 AMPS

~15 VQOLTS 2 AMPS

BA11-AL/AM BACKPLANE DIAGRAM

MR-165%4

BAl1-AL/AM Backplane Diagram

Figure 7-6

Configuration Rules for BAll-AL/AM

When adding an option or backplane to a BAll-A
following
1.

rules

box

expansion

the

apply:

rules on the
regular configuring
In addition to the
amperage available for the backplane, the BAll-A expansion
known

and

Locate hex-sized options in the backplane starting in

slot

box requires that the power drawn by options be

The total power drawn
a configuring requirement.
as
used
cannot
box
expansion
the
in
mounted
by UNIBUS options
exceed 500 watts (see discussion below).

only for use by
available
are
9
and
2,
1,
Slots
3.
guad-size options, unless configuring quad-sized options in
these

slots violates rule

40 watts
Any single module option that produces more than
slot adjacent to the component side of
the
that
requires
the option be unoccupied

(due

«cooling

restrictions).

that produce over 40
DEUNA)
(i.e.,
Dual-module options
the
watts can be mounted in consecutive slots, and require
side of the dual-module
component
to the
adjacent
slot
option be unoccupied.

Standard UNIBUS configuration rules apply to any UNIBUS

the

system.

Service

'PAULI'

Use

'PDP 11 BUS HANDBOOK' or the Field

the

program for assistance.

Example 7-1:

Power consumption for the DMF32

+5
The DMF32 Communications Controller draws 8 Amps @
Using
+15 V, and .50 Amps @ -15 V.
@
0.50 Amps
v,
following
the
formula
these figures as input to the
results are achieved:
8 X5

= 40

(watts)

.5 X 15 = 7.5
.5

Option total
7-13

(watts)

= 7.5

55 watts

SYSTEM

INFORMATION

This

result

DMF32

option

(slot

adjacent

important

produces

the

two
than

component

unoccupied.

Second,

DMF32

backplane

the

ways.
40

One,

because

the

watts,

side of
power

the

module)

consumed

the

the
slot

needs

DMF32

(55) is subtracted from the available
total of
500
watts,
Therefore,
to
add
the
DMF32
to
an unpopulated DD11-DK
backplane in
a
BAll-A
expansion
box,
the
option
will
require
two slots; slot 2 for the 40 watt rule,
slot 3 for
the module.
This leaves 445
watts
remaining.
Adding
a

second

4
remains
configured

Proceed in the
tracking
the

following
the
requirements.

7.5.5
There

the

UNIBUS

and

would

the

require

second

two

slots,

DMF32

module

slot

same manner for additional
total
power
consumption

slot

rule

UNIBUS
options,
for
the box, and
each
options
power

based

UNIBUS

expansion

Expansion

are

three ways
system.
Use

the

unoccupied
into slot 5.

the

to utilize

the

DW780-MB

(installed

The

the

capabilities

I/0 backplane).

DW780-MB mounts in the
H9652~-F
UNIBUS
expansion

I/0 backplane (DWl1).
Order
the
cabinet and DD11-DK backplanes.

(installed

These cabinets will mount to the left
side of the front end
cabinet.
See diagram of UNIBUS expansion configu
ration.
use
the
cabinet).

DW780-AA/AB

SBI

expansion

This variation mounts in an H9652-C
series
SBI
expansion
cabinet.
Order
H9652-F
series UNIBUS expansion cabinets

and

the
To
The

DD11-DK backplanes.
The UNIBUS cabinets will
right of the last H9652-C series SBI
cabinet.

expand
UNIBUS

expanded

the
in
to

cabinet.
and

the

front-end
the
a

Front
second

UNIBUS
End

may

(DWO).

BAll-A

mount

drawer

drawer
in

(DW0)
UNIBUS

expansion

Order H9652~F Series
UNIBUS
expansion
cabinets
DD11-DK backplanes.
The UNIBUS cabinets will mount
to
left of the Front End cabinet (see
diagram below).

The standard UNIBUS configuration rules
apply
(i.e.,
bus
loads,
bus length).
See the section 'BA11-AL/AM EXPANSION

RULES'

UNIBUS
system

for

expansion
may

used

information

box.

Also,

for

reference.

configuring

the

Field

the

BAll-A

Service

'PAULI'

SYSTEM

H9652-F

| |

JL__

FEC

VAX 8600 CPU

1
TUNIBU3 0

INFORMATION

' H9652-C

HO652-F

=
177 7]

| (2]

i iB

UNIBUS O

UNIBUS 1

UNIBUS 3

PART OF IDTC OPTION

(UNIBUS DOES NOT LEAVE THE CPU CABINET)

FEC
H9652-F

= FRONT END CABINET
= UNIBUS EXPANSION CABINET

H9652-C

= SBI EXPANSION CABINET
MH- 18542

Figure

7-7

UNIBUS

Expansion

7.5.6

SBI

Expansion

The system is capable
There are two ways to

Expand

the

Configurations

of supporting
utilize these

SBI

adapter

two
SBI

included

The configuration rule

independent
SBI
adapters.
expansion capabilities.

for

the

CPU.

first

SBI

allows

maximum
of one H9652-C SBI expansion cabinet
panel spaces) which mounts to
the
right
of
cabinet.

Refer

for

system

SBI

configuration

rules

a
option

the

CPU

details.

Order
a.

the

The

optional

SBI

configuration

maximum
NEXUS

two

slots)

which

adapter,
rule

for

DB86-AA.
the

H9652-C SBI
mount

second

SBI

allows

expansion cabinets
the

right

(8 SBI

the

CPU

cabinet.
b.

Refer
to
details.

system

SBI

configuration

rules

for

SYSTEM

INFORMATION

7.5.6.1

SBI

Configuration

one

SBI

can

Rules

Only

Maximum of two CI780s per system (either
on
SBI
or
the
optional
SBI).
See
cluster

expanded per

system.
the

internal

rules

for more

DR780

details.
3.

Maximum of

two

CI780s

per

SBI

(only

one

also

connected).
4.

Maximum

four

DR780s

per

SBI

(only

four

RH780s

per

SBI.

one

CI780

also

connected).

Maximum

Maximum of four DW780s per SBI.

When

expanding the
internal
cabinet
to
the
H9652-C SBI

remove

the SBI

terminator

SBI
(SBIA-0)
from
the
CPU
expansion cabinet, be sure to

(M9040)

from slot

the

I1/0

suggested

backplane.

7.5.6.2

SBI

guideline

separate

SBIs,

Absolute

levels
TR

Level

for

configure

levels

determine

levels

Assignments

assigning

mean

and

each

SBI

unused

low

priority

system with

and

not matter.

Relative

not

High

competing for
is the lowest

matter.

SBI access.
priority.

following

restrictions

TR 01 is reserved for DMA réturn (asserted by SBIA)

reserved

VAX

8600

level

0
1
2

3
4

SYSTEM

for

the

SBI

CPU

(actually SBIA)

(see

note

LEVEL ASSIGNMENT CHART
SBI

Nexus

HOLD
DMA
CPU

return
(SBIA)

first

UBA

second
third

UBA
UBA

fourth

UBA

(SBIA)
(see note

(DW780)

first

MBA

(for

disks)

second

MBA

(for

tapes)

third
fourth

MBA
MBA

(or

second

15
16

HOLD

number

apply:
for

11
12
13

two

independently.

The

highest

reserved

below

SBIs.

the

and

chart

levels

relative priority

priority

The

levels

first

CI780
first DR780
second DR780

CI780)

SYSTEM

INFORMATION

NOTES

7.5.7

Refer to section
SBI
NEXUS
and
INTERNAL
OPTIONS
for
information on setting the TR
level
for
a
particular
option.
This
section
will include information on jumper
settings.

Where the CPU(SBIA) TR level
ID number remains at 16.

The

CPU in
CPU.

common

star

CPU may

HSC50s

Disks

cluster must be able
CPU must have a

SBI

coupler.)

to communicate
with
every
least one CI connected to a

(Each

member

connected

coupler

the

Rules

other

DR780
and
CI780
TR
levels
may
be
interchanged,
however,
if
a
DR780 and a
CI780 exist on the same SBI then the
CI780
must be at the higher priority (as shown).

Cluster

Every

the

public

connected

only

CPU on

cluster
private

one

cluster

star

are

coupler

considered

HSC50s

cannot

time.

other

than the star
'private HSC50s’.
be

made

cluster

accessible.
VMS
are

can presently
possible in a

Only

Each

node

number

nodes

and

per

support only two
future release.
star

connected
node

CIs

per CPU.

wunique

node

coupler.

to a star coupler must have a

name.

Three

SYSTEM

7.6

INFORMATION

PM PROCEDURES

The following PM procedure has
been
developed
in
an
effort
to
increase
the
MTBF
for the VAX 8600/8650 systems.
This procedure
should be followed in the field on a
consistent
basis
to
ensure

maximum reliability.
-

recommended

that

error

logs

checked

prior
to
performing this procedure
injected into the system during this

7.6.1

Summary

Quarterly

Clean

air

Check

system
and

vents,

check

cables

Clean

Verify

replace

Check system power.

fans

for

systems

check

voltages

BA boxes.

voltages

in BA boxes.

PM Procedures

Run margins.

Run system diagnostics.

Replace

Quarterly

PMs.

exerciser.

Summary of Annual

RL02

filter

absolute

filter

PM Procedures

Clean air vents,

and

filters.

Perform scheduled device

run

are

revisions.

Run

no problems

damage.

7.6.3

diagnostics

Procedures

7.6.2

and

to ensure that
procedure.

Visually

Ensure
needed.

check

inspect

fans

are

fans

and

air vents

operating

check
and

clean

correctly

necessary.

and

replace

SYSTEM

Measure

voltages

the

BAll

box

using

INFORMATION

digital

volt

meter (DVM).
The table below lists the color code, and
associated backplane pin, used on
each
of
the
power
harnesses

within

the

BAll

expansion drawer.

Color

Voltage

Backplane

BLACK

GROUND

RED

VOLTS

GRAY

+15

VOLTS

Cul

WHITE
BLUE
GREEN
BROWN
VIOLET
YELLOW

+15 VOLTS
-15 VOLTS
-15 VOLTS
- 5 VOLTS
DC LOW
AC LOW

Cul
CB2
CB2
CD1
CN1
Cvl

NOTE

Log
and
retain
these
power
measurements
for
comparison at each PM performance, for indications
of power degradation.
The H7140 is
an
FRU
as
a
complete
unit
and
voltage
adjustments are to be
done at the factory only.

Check

cables

for

damage.

Visually inspect system cables
or any other types of damage.

Clean
a.

system

and

replace

for
fraying,
crimping,
Replace as necessary.

filters.

CPU card cage filter - Power down the system.
Turn the
two
black
catches
at
thc
bottom
of
the card cage
support assembly so they are parallel
to
the
support
assembly.
Slide
the
filter
out of the CPU cabinet.
Use a vacuum
to clean the filter,
then
reinstall
the
filter.
Front End cabinet - Open front and rear
doors
of
the
front
end
cabinet.
Remove the filters mounted on the
inside of the doors
by
peeling
them
away
from
the
velcro
strips
holding
them in place.
1Insert the new
filters, part numbers 12-11255-14 (1), 12-11255-08 (3),
and 12-11255-02 (1).

RLO2 prefilter - Remove the 6 screws holding the
front
bezel
in
place.
Remove the front bezel.
Replace the
prefilter located on the right front side of the
drive
(PN 74-15297-00).
CPU Air Mufflers - Insure that free air flow exists
1in
the air mufflers mounted on the rear doors of the CPU.

SYSTEM

TNFORMATTON

Verify
ds

revisions.

Check

system

revisions

Matrix

documents

the

8650

VAX

Install

any

Insure

that

used

Check

vreferencing

microfiche,

K-RM-8600-0-0

necessary
the

the

for

the

Revision

K-RM-8650-0-0

the

VAX

FCOs.

latest

RL0OZ2

Console

release

1is

being

system.

system power.

Measure

system

use

the

regulator

show power

power

command

and

ground

current

(>>>SHOW POWER).

Perform

scheduled

Refer

device

to microfiche

systems

exerciser

Run

VAX

the

for
5
listing

86XX

Retain

this
for
comparison
at
each
quarterly
PM,
indications of possible system power degradation.

Run

fsri

8600.

for

PMs.

listings.

<EDKAX>.
system

exerciser

diagnostic,

passes,
referring to the diagnostic
for specific operating instructions.

EDKAX,

microfiche

>>>@EDSAA
DS>

7.6.4

Annual

ATT

KA86

DS>

SEL

KAQ

DS>

HUB

KAO

EDKAX/PASS:5

PM Procedures

Replace

RL02

Locate

absolute

the

plenum

Lift
one
of
plenum spring,
from

the

filter
springs

the
plenum
squeeze the

bracket.

Remove

the procedure for
cover
may now be

the 2nd
removed

and plenum
latches.
latch and

the

plenum

cover

latches.

While
remove

holding the
the
latch

spring

then

repeat

latch and spring.
The plenum
by pulling the cover forward.

Use a screwdriver to pry the left side
of
the
filter
out
slightly.
The
filter
c¢an
then
be
removed by
rocking it from side to
side
until
it
slides
free.
Replace

the

filter

(PN

12-13097-00).

SYSTEM

Run

system diagnostics.

;

Execute
P

about

pass of the TSTCPU.COM file.
minutes and test the complete

“mmii’

INFORMATION

This
CPU.

will

>>>@TSTCPU

Run

margins.
Run

one

high.

pass

Repeat

the

with

TSTCPU

script

voltage

margins

with

voltage

margins

low,

>>>DIAG

DC>SET

MARG
DC>@TSTCPU

DC>SET

MARG

DC>@TSTCPU
DC>SET

Execute
a.

CPU

Load

the

MACRO

MARG

diagnostics.

Diagnostic

Supervisor

and ATTACH

the

>>>@EDSAA

Run

pass

DS>

ATT

KA86

DS>

SEL

KAQ

HUB

the

CPU macro

DS>

R diagnostic_ name
EVKAB

EVKAC
EVKAD
EVKAE

EDKAX

KAO

diagnostics.

Diagnostics

g“‘%

take

to be

run are:

CPU

SYSTEM

INFORMATION

7.6.5

VAX 8600/8650 PM Checklist

TASK

QUARTERLY

BA BOXES

Air vents cleaned

]

Fans operating correctly

Voltages checked

1.
2.

[

]

System cables inspected

CPU card cage filter cleaned

Door filters replaced

RL02 prefilter replaced

]

Revisions verified per RM

{

System power checked

All system PMs performed

EDKAX runs error free

KERNEL

FRONT

END

SYSTEM

DEVICES

TESTING

ANNUAL
FRONT

END

RLO2 absolute filter replaced

High margins performed

Low margins performed

TSTCPU runs at normal margin

MACRO diags run error free

TESTING

7-22

]

CHAPTER

SYSTEM CLOCKS

8.1

CLOCK

Two

types

INTRODUCTION

processors,

«clock

modules

are

and

L0231.

L0217

used

1in

main difference

the

«clock

between

signal.

The

oscillator,

lock

provides

loop

phase

lock

the

two

revision

loop,

clocking

revision E L0217 has no phase
an external clock.

There

the

L0217
C5

are

VAX

versions

clock

external

rates

between

locked

two

8600/8650

of the
L0217 module, revision (5, which will be phased out over time,
and
revision
E.
The VAX 8600 can use either revision of the L0217, or
the L0231, but with the L0231,
use
1is
restricted
to
the
lower
frequencies.
The VAX 8650 can only use the L0231.

The

the

loop,

but

versions

the

provided

source

clock.

The

and

has

four

of
MHz

phase

MHz.

The
oscillators

but

has

and

The

L0231

module

similar

the

L0217

oscillators
instead
of
four, and the
adjusted to the faster clocking rate of
also has an external clock input.

8.2
The

CLOCK
clock

CONSOLE
is

CLOCK

SET

SOMM

SHOW

the

following

the

General

console

commands:

CLOCK

START/STOP

CPU

START/STOP

SYSTEM

These

commands

found

are

Chapter

part

10,

Console

Software

Command
and

Set,

SET SOMM command works in
c¢onjunction
with
the
console
command
to
allow
stopping on a micro-mark.
command set (Chapter 10) for DEPOSIT/MARK.

Table

CLOCK

8-1

may

DEPOSIT/MARK

See

the

HEX

OUTPUTS

lists

clock
reset
VAX 8600/8650
Appendix

and

Commands.

The

8.3

six

being
L0231

COMMANDS

controlled

SET

rev.

delays are different,
the VAX
8650.
The

the

WBus

enable

signals

and

Table

8-2

signals.
For the remainder of the clock
System
Clocks
Technical
Description,

1lists

the

outputs, see
EK-KA86K-TD,

SYSTEM

CLOCKS

Table

8-1

WBus

Enable Signals

Source

Destination

Signal Name

Module Slot

Module B/P

Slot

CLK FBA WBUS ENABLE L
CLK EBE WBUS ENABLE L
CLK EDP WBUS ENABLE L
CLK ICP WBUS ENABLE L

CLK
CLK
CLK
CLK

B38
B36
B37
B34

FBA
EBE
EDP
IDP

08
09
10
14

B92
B45
Ccl0
A91

Table

11
11
11
11

8-2

Clock

02
02
02
02

Reset Signals

Source

Destination

Module Slot

Module B/P

Slot

CLK RESET
CLK RESET
CLK RESET

141 A
141 A L
141 A L

CLK
CLK
CLK

11
11
11

A85
A85
A85

MCD
MAP
MCC

02
02
02

16
17
18

B50
B50
B50

RESET 141 B L
RESET 141 B L
RESET 141 B L
RESET 141 B L

CLK
CLK
CLK
CLK

11
11
11
11

AB6
A86
A86
AB86

ICB
ICA
IDP
IBD

02
02
02
02

12
13
14
15

B50
B50
B50
BS50

CLK RESET 141 C L
CLK RESET 141 C L
CLK RESET 141 C L

CLK
CLK
CLK

11
11
11

AB7
A87
A87

EBD
EBE
EDP

02
02
02

06
09
10

B50
BS50
B50

CLK RESET
CLK RESET
CLK RESET

D L
D L
D L

CLK
CLK
CLK

11
11
11

A88
A88
A88

CSA
CSB
EBC

02
02
02

03
04
05

B50
B50
B50

CLK RESET 141 E L
CLK RESET 141 E L

CLK
CLK

11
11

A89
A89

FBM
FBA

02
02

07
08

B50
B50

CLK

CLK
CLK
CLK

11
11
11

A91
A93

SBA
SBA

03
03

03
05

CLK

B14
B15

C50
C50
-

clock

distribution

CLK
CLK
CLK
CLK

141
141
141

SBAO

RESET

141

CLK SBAl
CLK SBA2
CLK SBA3

RESET
RESET
RESET

141
141
141

8.4

CLOCK

BLOCK

[l Al

Signal Name

DIAGRAMS

Block

diagrams

L0217
clock

Rev.
C5 module, the L0231/L0217 Rev.
E modules,
distribution, and clock control logic, the CLC MCA.

are

included

for

the

NOTE

The CLC

MCA

the

same

for all

the modules.

systems,

the

backplane

SYSTEM

CLOCKS

VENUS CLOCK MODULE

5{3{ MHZ __
XTAL

»{

PHASE

LOCKED ~—

fgggr

LOOP

>0
MHZ
NOMINAL

CLOCK,

»|

PANEL

LEVEL 1
CLOCK

ONBOARD

DISTR.
(CPU
CLOCKS)

LOGIC

MODULE
CLOCK
DISTR.

CONTROL
LOGIC

LEVEL 1

EXT
0sC

»
[

[

CLOCK

DISTR.
(MEMORY

»|

CLOCKS)

ONBOARD
MEMORY

MODULE
CLOCK
DISTR.

SDB CONTROL LOGIC
4

SDB

CONSOLE

MR-15308

Figure

8-1

Clock

Distribution

System,

L0217

Rev.

L0231/L0217 CLOCK MODULE

L0231

L0217

XTALS

40 MHZ
50 MHZ

LEVEL 1

68 MHZ

53 MHZ s

SPARE 1 =

74 MHZ

7EMHZ

gi‘%;

CLOCK

40 MHZ —

56 MSZ 1

SPAREZ —

gg %ggz

gfiégi

NOMINAL

MODULE

(CPU

CLOCK

CLOCKS)

DISTR.

CLOCK
CONTROL

SHAPER

LOGIC

DESKEW CLOCK —

EXT VCO

LEVEL 1

ONBOARD

CLOCK
:

ONBOARD
LOGIC

DISTR.

50 MHZ —

72 MHZ

MEMORY

DISTR.

= MODULE

CLOCKS)

DISTR.

(MEMORY

CLOCK

SDB CONTROL LOGIC
f

SDB

l CONSOLE l
#AR-18330

Figure

8-2

Clock

Distribution

System,

L0231/L0217

Rev.

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SYSTEM
CLOCKS

)HWOiES

BEdE

CHAPTER 9

CONSOLE HARDWARE

RLO2
{10 MB)

SBI

SBi

M8400-vB

l {s /O SUBSYSTEMS

‘ A 17O 3UDSYSTEME ,J

BA11-AL
MBEB59

MBE59 l

ARRBAY BUS

MB081 {RLV12}

o¥

M8403

i I HER 1

TBI O

Jlpmy

EBOX

(CS}

T
|13
=

ARRAY

=
o
o

|I1BOX IMBOX

|FBOXjEBOX|

CBUS

[—

Tor
sib

JUMPER [;3

TTL 1 ECL
SERIAL
DIAGNOSTIC
BUS
{18 — 21}

ECL
CBUS

DUAL PORT
HEGISTER
FILE

32 X8

- 17}
{13

TTL

USART

usarT
sz 3° 1 (10—
11) |
~

O O O 0O O

{10~ 11)

SAL/DAL

— TOY
e (JBA

i?i ..
T-11

MICROPROCESSOR

TER]

L. PROM
CBUS

(3} P MiSC

~§

7oy

)

{22}
.

SENSORS

NOTE:

NUMRFRS IN PARENTHESES INDICATE PRINT PREFIX IN ENGINEERING PRINT SET.

Figure 9-1

Console Interconnect Block Diagram

AR-12983

CONSOLE

9.1

HARDWARE

SYSTEM CONTROL PANEL

The

system control panel, (SCP), is located on the top
right
hand
side
of
the
CPU
cabinet.
See
Figure 9-2.
It consists of two
switches and four status indicators (LEDs).
The
SCP
communicates
only
with the console by means of the Serial Diagnostic Bus (SDB).

The

console

can read the state of the switches and read
and
write
LED
register,
which
1is
the
input
to the indicators.
The
setting of the two switches combined with the current console
mode
determines
the response of the console program to various external
inputs.

the

The

right

remove,

for

the

switch,
DC

power

local

and

control

the

terminal

the

remote

CPU

control
and

for

terminals.

switch,
is
used
for
controlling automatic restarts.

switch,
setting

The

left

used

to apply,

the

mode

switch,

bootstrapping

the

operation

restart

system

and

The status indicators show the CPU run state,
remote
diagnostic link, and the occurrence of

other)

fault

(EMM)
.

9.1.1

that

Console

detected

Operating

the
status
of
the
an environmental (or
Environmental
Monitor
Module

the

Modes

The

console

operates

Console

I/O mode

(CIO):

Program I/0 mode (PIO):
VMS running, the
console
acts
slave to the VAX processor and services its requests.

9.1.2
The

SCP Switches

control

The

j
M

Remots
Enable

:
B's
GREEN

LEDs

two modes:

Operator command

input

accepted.
as

Indicators

panel

control
switches are

VAX
State

and

one

switches and indicators are shown in Figure
9-2.
panel
indicators
are described in Table 9-1 and the
described in Table 9-2.

Remoty
Active
!

Alert

Restart
—

Boot

estart
/" Halt

— N\

Boot wwea

2 1

Local

Disable TM\

Off e

.
RED

LED

RESTART CONTROL

Remot

emote
/" Disable

— Bemote

TERMINAL CONTROL

SWITCH

MR-13862

Figure 9-2

System Control

Panel

Switches

and

LEDs

CONSOLE

Table

9-1

System Control Panel

Control Panel
Indicators

State

Description

VAX State

OFF

HARDWARE

Indicators

CPU

is not

BLINKING

CPU

Remote Enable

Terminal Control Switch is in the
Remote or Remote Disable position.
Console program is in PIO mode.

Remote Active

Remote terminal is connected and
the line is actives

Alert

program

running,

not

executing

or the console

PIO mode.

a macro program.

EMM has detected a fault
condition, an error message

has

been printed on the console
terminal indicating a
"yellow—-zone" temperature

condition. LED is turned off when
violation has been eliminated, as
detected

BLINKING

the

EMM.

Flashed in 1 second
indicate "red-zone"

intervals to
condition, and

message is printed on the console
terminal. Total system power shut-

down occurs in 1 minute if
condition is not eliminated.
Conditions that border between
yellow and normal may cause LED
appear as flashing.

BLINKING

Flashes when an air flow fault is
pending. Automatic shutdown is
armed to trip in 3 minutes for a
single air flow violation.
Shortened for a double air flow
fault (2 sensors).

NOTE

These indicator descriptions are
wvalid
only
when
console software is up and running.
When PROM code
is
running,
the
indicators
may
have
different
meanings,

see

SCP

troubleshooting,

Chapter

Table 9-2 summarizes actions taken by the console for
all combinations of the Restart Control Switch (RCS) and the
Terminal Control Switch (TCS) on the System Control Panel (SCP).

CONSOLE

HARDWARE

Table

9-2

System Control

Panel

Switch

Summary

Action
Restart

Terminal

Control

After
Alive

Remote
Port

7
“P

Switch

Initialization

Enabled?

Any

Local

Restart

Yes

Boot

Disable

Keep
Fail

and

Boot

Local

Boot

Restart

Boot

Local

Restart

Boot

Yes

Restart

Halt

Local

Restart

Halt

Yes

Halt

Local

Halt

Yes

Boot

Remote

Boot

Yes

Disable

Restart

Boot

Remote

Disable

Restart

Boot

Restart

Halt

Remote

Disable

Restart

Halt

Yes

Halt

Remote

Disable

Halt

Yes

Boot

Remote

Boot

Yes

Restart

Boot

Remote

Restart

Boot

Restart

Halt

Remote

Restart

Halt

Remote

Halt

9.2

Remote

access

CONSOLE

Table 9-3
priority.

allowed

(T1l1l)

lists

the

Yes

PIO mode only.

INTERRUPT AND VECTOR

console

Yes

HALT

interrupt

INFORMATION

vectors

and

their

relative

CONSOLE

Tll

Table 9-3

Vector

“1

Device

Reserved trap 0

Breakpoint vector

Reserved trap 4
Reserved Instruction trap
IOT trap

Prom Restart (unmaskable) - EXT SW input
(power fail)

EMT Instruction trap
Trap Instruction trap

30
34

Remote PCI

Transmit/Receive/Modem

100

110

124
130

5
)

11
12

RXCS Done
QBus Adapter

140

Console RAM Parity Error

64
70
104

114
120

134

)

Interrupt Vectors

04
10

HARDWARE

4
4
6

6
5

144

150
154

7
7

02
03

Transmit/Receive
Local PCI
QBus Reply Timeout

Unused

TOY 1 Ms Interrupt

07
10

STOR Ready
TXCS Ready

13
15
16
17

CPU Control Store Parity Error

EMM PCI Transmit/Receive
Unused

System AC Low
ABus Dead

NOTE

VECTOR format:

VECTOR location

Interrupt
The new PC of the
stored
is
Routine
Service
here.

VECTOR + 2

here.

The new PSW is stored

Currently, this includes the
is
Processor priority which
.
set to PR7 (highest) and the
ORed
is
vector
the
ID of
into the least significant 4

bits.

2.
;

}

Self-Test numbers 34

will

set

the

interrupt vectors, enable interrupts then check
The object
that no spurious interrupts occur.
is to verify the integrity of the interrupt

system prior to booting RTll.

CONSOLE

HARDWARE

When
a
spurious
interrupt
following
message
will
be
console

terminal

back

PROM prompt):

?PROM

(and

does
occur,
the
printed
on
the
will
be
placed

control

ENTRY

THRU INTERRUPT VECTOR nnnnnn
..RO....R1....R2....R3....R4....R5,..

?REGS

Rsfi"’PsW‘.‘fiPCQ’
ROM>

CL15 TSTRT interrupt can be
CPU

and

causes

the

T1ll

address 172004.
This
the
console
1logic

generated

jump

restart

directly

will

the

PROM

reinitialize

and
reboot
the
console
software without affecting the
CPU
(basically
the
VMS
reboot
console
request).
Note that
this is interrupt vector 24.
5.

CLO02 MAN RESTART interrupt (which also
vectors
to
24)
1is
from
an external input on the CPU
backplane
(slot
2,
pin
C69...grounded
to
assert).
This
interrupt,
as
with the TSTRT
cannot
to

be masked.

PROM

address

Tll status
(prompt:
read

?PROM
?REGS

The

interrupt

172010 which

and returns to
"ROM>").
The

follows:

forces

simply

the

T11

prints

the

the
PROM
null
loop
console message will

ENTRY THRU

INTERRUPT VECTOR 000024
OiRGO.CfiRI‘il.RZQ‘.iRBCQ.iIR4QCQQRS§iO

...PWS....PC..

ROM>

The
Tll

interrupt system is controlled by "CL09 ENA
INTR
H" which must be asserted before ANY
of these interrupts can be
seen
by
the
T1l1..
The
signal
is
controlled
as
follows:
Interrupts are enabled by setting
bit
<0>
in

MCSRO,

176040.

clearing bit
9.3

CBUS

The

console

and

EBox

Interrupts

<0>

in MCSRO,

communicate

are

disabled

over

the

CBus,

interconnect between the two devices.
See Figure 9-3.
backplane connections are listed in Table 9-5, and the
described in Table 9-4.

Table

9-4

CBus

Signal

176040.

backplane
The 16 CBus
signals
are

Description

Signal
Name

Description

CBUS A<5:0>H

The Console Bus interface consists of a
dual
port
RAM
which
has
thirty-two
RAM plus Four external
eight bit
register
1locations.
The
CBUS
signal
lines enables the CPU to access the entire CSL CBUS
interface register space.

CONSOT.F.

Table 9-4

CBus Signal

Description

HARDWARE

(Cont.)

Description

CBUS

A CPU CBUS access involves the
transfer
of
eight
bits
of
data.
The
CBUS
data
path
1is
an ECL
bi-directional interconnect and it is controlled by

D<7:0>H

CPU

the
CBUS

WRITE

EBox.

When this CPU controlled signal

used
with
the
write access is

signal,

CBUS

CLOCK L

and

read

line

1is

and

the use of the CBUS Clock

initiates a

access.

This signal line is sourced by the CPU and is
used
in conjunction with the CBUS WRITE signal to enable
the timed sequencing of
either
a
read
or
write
access.

CONSOLE

<:z

MODULE
L0201

v:>

DATA LINES<07:00>

<::

I %

}

ADDRESS LINES <05:00>
=

CBUS CLOCK

PRINT:
N7

EBE

MODULE
L0219

PRINT:

CBUS WRITE

Figure 9-3

Table 9-5

EBED

CBus Block Diagram

CBus Signal Backplane Pin Location

Signal
Name

Ra———

set

generation
of a CBUS CLOCK a CBUS
executed.
The CPU clearing of this

CsL L0201
Slot 2

EBE L0219
Slot 9

cé68
Cé66
C70
C71
ce67
C73
C54
Cé4

C66
C65
Coe8
Cc71
ce7
C75
C55
Co2

C78
C74
C46
C76
C45
C44

c80
A25
C44
C76
Cc47
A74

EBE CBUS WRITE H

C53

EBE

C58

C56

CBUS
CBUS
CBUS
CBUS
CBUS
CBUS
CBUS
CBUS

DO
D1
D2
D3
D4
D5
D6
D7

EBE
EBE
EBE
EBE
EBE
EBE

CBUS
CBUS
CBUS
CBUS
CBUS
CBUS

CBUS

H
H
H
H
H
H
H
H
A0
Al
A2
A3
A4
A5

H
H
H
H
H
H

CLOCK

CONSOLE

9.4

HARDWARE

OQBUS

The console interface to the RL0O2 is through the QBus
adapter
and
over
the
OQOBus to the RLV12.
Figure 9=4 is a block diagram of the
QBus interconnect between the console and
RLV12
Disk
controller.
Table
9-6
1lists the QBus backplane pin connections, and Table 9-7
is a description of the QOBus signals.
For
more
information,
see
KA86 Console Technical Description, EK-KA86C-TD.

,/’xj1
\\\\J

DATA/ADDRESS
LINES
BDAL<15:0> L

r\\\\

Lz//f

BBS7 L

BWTBT L
BSYNC L

BDOUT L

BDIN L

CONSOLE (CSL)
. MODULE

RLV12 DISK
CONTROLLER
BUS INTERFACE

BRPLY L

L0201

BOMRL

B/P 2

MODULE

M8061

BA11 F/E

BDMG L

BSACK L
BIRO L
BIAK L

H
BDCOK
BPOK H
BINIT
L

MB- 15846

Figure

9-4

QOBus

Interconnect

Block

Diagram

CONSOLE

QBus Signal Backplane Pin Locations

Table 9-6

Signal
Name
BSPARE
BDAL O
BDAL 1
BDAL 2
BDAL 3

BDAL 4
BDAL 5
BDAL 6
BDAL 7
BDAL 8
BDAL 9
BDAL 10
BDAL 11
BDAL 12
BDAL 13
BDAL 14
BDAL 15
BWTBT L
BBS7
L

L
L
L
L
L
L
L
L
L

L
L
L
L
L
L

BDOUT L
BRPLY L
BDIN
L
BSYNC L
BIRQ
L
BIAKL L
BDMR
L
BDMG
L
BINIT L
BHALT L
BSPARE 3 L
BREF L
BSPARE 4 L
BDCOK L
BPOK
L
BSPARE 6 L
BSACK L
BEVNT L

HARDWARE

CPU Backplane

BAll

CSL
Slot 2

Cable

M9403
Cable

Backplane
Slot 26

A32

J7 04

Jl
J1
Jl1
Jl
Jl

B
D
F
J
L

AAl
AU2

N
R
T
v
X
AA
CC
EE
HH

AV2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2

KK
MM
PP
SS
UU

BT2
BU2
BVZ
AK2
AP2

D
F

AE2
AF2
AH2
AJ2
AL2
AN2,AV2
AN1
AS2,AR2
AT2
APl
ACl
AR1
AD1
BAl
BB1
BP1
BN1
BR1

A38
A30
A39
A34
A46
A4l
A36
AQ05
A20
AQ6
Al2
A08
AlS8
Al0
Ald

J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7
J7

06
0O
10
12
14
16
18
20
22
24
26
28

A94

A86
A8Y9 .
A88
A87
A62
A74
Ab4
A70
A78

J8 04
J8 06
Jg 08
J8 10
Jg 12
J8 14
J8 16
J8 18
J8 20

A76
A93

J8
J8

30
32

A68

30
32
34

Jl1
J1I
Jl1
Jl
Jl
J1l
Jl
Jl
Jl
J1l
J1l
J1l
Jl
Jl
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2

Front End

J
L

N
R
T
V
X
AA
CC
EE
HH
KK
MM
PP
SS
UU

NOTE

In
order
to
avoid
confusion
Dbetween
QBus
and
console
signals
that
have
the
same
name
but
different meanings, all QBus signals
are
prefixed
with
a
"B",
e.g.,
"BSYNC"TM
1is a QBus signal and
"SYNCTM is a console (QBA) signal.

Table 9-7

BDAL<15:0> L
BBS7

QBus Signal Descriptions

Sixteen multiplexed data/address
Bank

master)

(I/0 page)

during

select.

DATO

lines.

Asserted by console

DATI when address is a

controller
(I1I/0)
address.
(Needed
for
applications
in
other
systems
when
both I/O and
memory devices are connected to the bus.)

CONSOLE

HARDWARE

Table
BWTBT

9-7

Write/byte.

portion of
BSYNC

BDOUT

transfer

Data

out.

has

bus

master

placed

in progress

Asserted

in.

Descriptions

(Cont.)

by bus master
during
indicate write data is to

Asserted

data

Data

Signal

indicate

indicate
BDIN

DATO

Synchronize.

DATI

QBus

Asserted

bus

during

address

bus

master

SYNC

negated.

during

DATO

DATI

during

indicate slave may place data on bus.

by console during
controller
(the

bus.

has placed data on bus.

Asserted

follow.
DATO

until

master

address

The

Also asserted

interrupt acknowledge to
indicate
interrupting
device)
may
place

interrupt vector on bus.

BRPLY

Reply.

Asserted

slave

during

DATO

indicate

it
has
taken
data
on
bus,
and during a DATI to
indicate it has placed data on bus.
Also
asserted
by
controller
during
interrupt
acknowledge
(by
console) to indicate it has placed interrupt
vector
on bus.
BDMR

Direct

Memory

controller

Access

(DMA)

request

request.

bus

BDMG

Direct

Memory

Access

console

(bus

arbitrator)

controller
BSACK

acknowledged.

BDCOK

power

detects

controller

bus mastership

Asserted

following a

controller

console.

Indicates
there
is
sufficient
dc¢
reliable operation.
Negated by
controller
when
cabinet
power
supply
LOW condition.

power

OK.

Indicates

normal

controller

when

initial

power.

cabinet

Negated

power

LOW condition.

Initialize.

The
to

OK.

detects AC

9.5

Asserted
mastership

to maintain
or

DMA

Asserted

assumed

request.

the

console

BINIT

bus

Interrupt acknowledge.
Asserted by the
console
tell controller to place interrupt vector on bus.

voltage

BDPOK

grant.
grant

request.

Interrupt

has

for

transfers.

indicate

interrupt
BIAK

DMA

Selection

DMA

BIRQ

for

(DMA)

Asserted

mastership

transfers.

Asserted

console

reset

supply

controller

state.

SDB

console uses the SDB to load and verify system
microcode,
and
read
the
state of backplane signals for diagnostics and error

handling.
Figure 9-5 is a block
diagram
of
the
SDB
interface,
Table
9-8
1lists the SDB interface to the SCP, Table 9-9 lists the
SDB control signal interface, and Table 9-10 lists
the
SDB
clock
and
data
out
interface.
Figure
9-5
refers to signal charts A

(Table

9-8),

(Table

9-9),

and C

(Table

9-10

9-10).

CONSOLE

HARDWARE

_(5}

CONTROL
LOGIC

-(g}
o-(

SYSTEM

CONTROL
PANEL

CL SCP DATA
IN H

O SCP DATA OUT H
A

e (C)
_@

)

(TTL LOGIC)

nnn SDB DATA QUT nnn H

?}4

CLSDB VIS SHIFT X
H

<§> CLSDB CLOCK nnn H
Cl

VISIBILITY

CHANNELS

iDP/LO206

ICA/L0207
ICR/1 0214

CLK/NOTE 3
EDP/LD209

EBE/LD219
MCC/NOTE 4
MAP/LO205b

EBD/10211
EBC/LO210
CSB/L0O216

CSA/10215

10-13

I0AD-3

MTM/1L0222

SDB DATA IN X H,

(ECL LOGIC)

L0201
CONSOLE

CHANNEL NO.

MODULE

FBA/LO212

MODULE
&

sDB

]

cHANNELS

_{E} CL SDB CNTRL S2 X H

;§

2 I

CL18-21

'(E) CL SDB CNTRL 81 X H

W00 U1 L

CONTROL

(ECL LOGIC)

Lo}

PRINTS

MCD/L0204
IBD/L0208

...;@

SDB

MODULE

FBA/LD212
FBM/1L0O213

e (D

sbs

CLSCPCLKH

CL SCP CNTRL
$1/52 /VIS SHIFT H|
.

MMOODPOONSOU
D WN -

CHANNEL NO.

FBM/L0213
iBD/LOZ08
ICA/LO207

EDP/LO209
EBE/LO219
MCC/NOTE 4

EBC/LO210
C8B/L02186
VH
(MFG. ONLY)

NOTES:

= A B ORC- REFER TO SIGNAL CHARTS FOR VARIATION.

MODULE MNEMONIC. REFER TO CHARTS FOR VARIATION.
LETTER DESIGNATES SIGNAL CHART.

L0217 (VAX 8600)
L0231 (VAX 8650)

L022Q (VAX 8600)

L0230 (VAX 8650)
MR- 18597

Figure

9-5

SDB

Table

Interface

9-8

Signal

Name

CLK

SCP

SDB

Interconnect

Chart

A -

SCP

Interface

CSL

CPU B/P

SCP

B02-69

J11-04

J12-04

SCP CNTRL S1 H
CNTRL S2 H
DATA IN H
CL SCP VIS SHIFT

B02~-58
B02-66

J11-08
J11=10

J12-08
J12=10

B02~-64
B02-67

J11-02
J1l11-14

J12-02
J12-14

CL SCP

B02~-68

J11-06

J12~06

CL SCP
CL SCP

DATA OUT H

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20E1Z2T0O7TYJeIdW|v0SZ1--220023B6S0~~--8801896HY6rLA-TZA0LSL1&2e8-8100d2Y]5286-~~-220002515S--8801L80€gY£B€G9~--2Z00BL5S~--880180

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@0y6-6 @SITBUCDJBIU]3IJ4BYD8-@05|DJ3U0Dsteuiis
CONSOLE
HARDWARE

9~-12

CONSOLE

Table

9-10

Module

SDB
Out

Interconnect Chart C - SDB
Connections

CL SDB

CLK nnn

CSL

SDB

Clock

and
.

nnn

Module

CSL

DATA OUT nnn

Module

L0204 MCD

B02=-77

B16=77

B02=57

B16=57

L0205 MAP
L0206 IDP

c02-06
B02-75

B17-77
Al4-04

c02-31
B02-55

Al4-55

L0207
L0208

ICA
IBRD

B02-~74
B02-76

C13-25
Al15-50

B02-~52
B02-54

B13-25
Al5-57

L0209 EDP
L0210 EBC
L0211 EBD

Cc02-06
Cc02-05
C02-07

B17-77
Cc05-05
Cc06-07

c02~-57
Cc02-38
C02-36

Al10-03
C05-38
C06-36

L0212

FBA

B02-80

B08-60

B02-63

A08-30

B02-78

AQ07-91

B02-56

B07-=42

L0214 ICB
L0215 CSA

B12-28
Cc03-17
C04-11

B02-53
C02-40

Cl2-86
C03-40

L0216 CSB

B02-73
C02-18
Cc02~11

c02-35

C04-35

L0217/
L0231 CLK

B02-65

Cl1-84

B02-49

Cl1-87

L0219

EBE

Cc02-08

c09-10

Cc02-62

B09-20

L0230 MCC
L0222 MTM

CcC02-10
Cc02-29

B18-81
J06~-21

C02-34
C02=50

Cl18-34
J06~-27

Note

I0AOQ

C02-26

J14-12

CcC02-37

J14-42

Note

10A1

C02-28

J14-14

C02-42

J14-06

Note

I0A2
I10A3

Cc02-30
C02-32

J14-16
J14-18

c02-39
C02~-41

J14-02
J14-04

Note
Note

3
3

21
22
23

Cc02-27
C02-25
c02-214

Cc02~47
Cc02-29
Cc02-60

Note 4
Note 4
Note 4

NOTES

To determine

the

correct

signal

name,

replace

the "nnn" with the appropriate module mnemonic.
For example,
on
the
L0204
MCD
module,
the
signal
"CL
SDB
CLOCK
nnn H" becomes "CL SDB
CLOCK MCD H".
The connections in the ABus
MTM module are as follows:
CL sDB
MTM

SDB

CLOCK MTM
DATA

OUT

H
MTM

backplane

J06-22
J06-28

the

A09-59
AQ09-73

These connections are
reserved
for
the
SBIA
visibility modules, which are for manufacturing
use only.
e

Data

Cl17-45

L0213 FBM

L0220/

HARDWARE

These
reserved

connections
for

are

future use.

spare

connections

CONSOLE

9.5.1

HARDWARE

SDB Signal

Name

File

Information

To support the SDB channels,
Signal
Name
Files
or
CADIF
files
(Computer Aided Design Information Files) are required to translate
a given logical SDB signal name
or
symbol
to
the
physical
SDH
location.
The following text outlines some of the components used
in the visibility logic.

9.5.2
The

CADIF File Description

following

text

;CHASER Version

taken

1(31)=1,

from a

sample

January

1984.

CADIF

file:

Sources

CSBB02.CDF
LSCAD:<SDB>

/CADIF-VERSION/ 3(5)
/SUDS~SDB/

1(2)

$SUDS-CHANNEL-TO-SIGNAL
16000
16001
16002

VSE124
VSE125
VSE126

EDP BMUX 15 H
EBC DIAG BR COND 1
EBC TRAP EB WRT H

16345
16346
16347

VSE153
VSE154
VSE155

FBA CARRY TO EBOX H
EDP UCC
Z H
BRANCH CONDITION 23 B

$SUDS-SIGNAL~-TO-CHANNEL
16141
16200
16201
16115
16117
16105
16107
16150
16204

VSE101
VSE101
VSE101
VSE101
VSE101
VSE101
VSE101
VSE140
VSE166

16102

VSE186

MCC TRAP OP WCHK

16043

VSE135

MCC TRAP OP WRT H

-CSBR FLIP USTK

-CSBT CLK6

PAR H

PHASE

TOA H

NOTE

There

is one CADIF file for
each
module
that
has
a visibility channel and the file contains
a list of all signals
that
are
visible
(and
thus
terminated)
on
that
module.
The CADIF
file does not list all
the
signals
generated
from
the
module,
rather
it
1lists
all
the
signals that terminate on the module.

The

CADIF
file
1is
divided
into
two
equal
sections,
a
CHANNEL-TO-SIGNAL
section
and a
SIGNAL-TO-CHANNEL
section.
Each
section

contains

complete

1list

signals; the first section
ID, and the second section
name.

of all the visible

sorted
by
the
SDB
sorted by the signal

CONSOLE

The following is a
fields of an entry

description
in the CADIF

16345
SDB

ID---

SDB

Symbol

SDB Signal

9.5.3

SDB

physical
contained

channel

enable
system

three

FBA CARRY TO EBOX H

Name

This is the
information
SDB

VSE153

of
the
file:

HARDWARE

number,

(see
has

SDB

‘'address'
of
a
given
signal
within this 14-bit octal value

bit

1ID

unique

select,

one
revision
module
information from
the

VIERM

Format).

SDB

to
SDB
and

MUX

Every

code.

The

select
ID

another.

The

console

ID
code
SDCS).

program

registers

(SDDB,

This field
indicates

contains an OCTAL value.
If
the
that
there
is
no
physical

SDMS,

symbol/name.
This case occurs when a
visibility logic on a new revision of
The

SDB ID is not a
register
used
by

code

The
the

VTERM

MUX

and

visibility

SDB

name.
includes

point
may

within

change

software

the

actual

the
from

uses

the

SDB

entry
address

signal

is
the module.

1is
37777,
it
for
a
given
removed
from
the

hardware

register.
It is
simply
a
'logical’
console
software to identify the physical
location of a given visibility point.
1In general, the
SDB
ID
is
broken
down
into
two
parts.
The first part, the CHANNEL SELECT
field, identifies which channel (or module) we
want
to
look
at.
The
second
part,
consists
of
the BIT SELECT and MUX SELECT and
ENABLE fields, which is used to address one bit of a possible
512.
It
is
this
last
portion
which
is
implemented
differently on
different modules.
For the current
system,
the
following
table
indicates the number of visibility points per module.
Refer to the
appropriate technical description manual for a detailed
functional
description
of
how the SDB logic is implemented on the individual

the

modules.

Module(s)
FBA,

Maximum

FBM

ICA,

ICB,

All

others

Figure

defines

Number

Visibility
288

IBD,

9-6

the

IDP

shows

SDB

the

1ID.

bit

(12

Points

256

(

32)

192

(

24)

breakdown

the

Implemented

24)

SDB

and

Table

09-11

CONSOLE

HARDWARE

SDB ID FORMAT
15

HIT BELELTR30>
i

Figure

9-6

SDB

MUX GELECT<2:0>

ID Format

SDB ID Bit Descriptions

Table 9-11

Bit Description

SDB Bit
CHANNEL SELECT

BIT SELECT

l MUX ENABLE< 10> l

<4:0>

<3:0>

Select

one

possible

SDB

channels.

Currently used channels are:

Channel

Module

Mnemonic

00
01
02
03

L0212
L0213
L0204
L0208

FBA
FBM
MCD
IBD

L0206

IDP

L0207

ICA

06
07

L0214
L0217

ICB
CLK

L0209

EDP

09
0A

L0219
L0220

EBE
MCC

OB
ocC
0D
OE
OF

L0205
L0211
L0210
L0216
L0215

MAP
EBD

10
11
12
13

N/A
N/A
N/A
N/A

I0A0
10A1
I0AZ2
I0A3

14
15-1F

L0222
RESERVED

MTM

EBC
CSB
CSA

given

bit

is 8 bits wide, so the actual number of

bits

Select

one

bits

for

The FBA
on the visibility channel.
position
all
while
bits,
and FBM modules support 12
The SDDB register
support 8.
other modules

When reading
be a multiple of 8.
must
read
channels,
data on the FBA and FBM visibility
there will be 4 filler bits.

MUX ENABLE

<1:0>

MUX SELECT

<2:0>

Select which bank of SDB

visibility

multiplexers will be selected.
Select 1 of 8 inputs to
channel multiplexers.

the

SDB

channel

visibility
£

CONSOLE

9.5.4

SDB

HARDWARE

Symbol

The

SDB symbol is the logical symbol assigned
to
a
given
signal
name .
The
objective
1is
to
assign
a permanent code to a given
signal name which can be coded into the diagnostics (MHC and
Micro
diagnostics).
By
wusing
the
SDB
symbol, rather than the actual
signal name, less program space is required.
The SDB Symbol for
a
given signal name will not change.
The

format

for

the

SDB

symbol

- symbolizes

that

the

NNN

represents

VSCNNN,

SDB

visibility

=
=

ICB

EBE

FBA
IBD

1
4

where:

Symbol
channel

= FBM
= IDP

2
5

= MCD
= ICA

= CLK

= MCC

= MAP

EBD

EBC

CSB

CSA

IOAOQ

IOAl

I0OA2

IO0A3

= MTM

unique

DECIMAL number

module.

the

Signal

thus:

EDP

number

SDB

this
SDB

0
3

name

9.5.5

is:

identifying

given

signal

Name

This is the signal name which is
used
in
the
<circuit
schematic
drawings.
Although
the
signal
polarity
may
change within the
schematics (e.g., from MCC9 MAPPED H to -MCC9 MAPPED L) it
follows
a

common

convention

the

CADIF

files.

All

SDB

signal

names

contain the 'H' suffix.
Thus if the signal is actually a true
signal
such as 'MCC9 MAPPED L' it will be listed in the CADIF
as '-MCC9 MAPPED H'.
Thus,

1if
you
are
'"EXAMINE/SDB
SIGNAL

signal

such

'ICB

tracing

NAME'

ID FULL STALL

>>>>EXAMINE/SDB

You will

get

the

?DCN-W-EUSIG,

You

need

through
command

"ICB

HEX

and you

ID FULL STALL

set
using
the
and come across a

enter

the

command:

following error message:

signal

convert

>>>>EXAMINE/SDB
V$5196 -ICB

the
under

low
file

name

the

not

found

CAD

tables

signal

name

the

'H'

polarity

thus:

"-ICB ID FULL STALL H"
ID FULL STALL H =

QF’ 123

Efpp 1%
9.5.6

CADIF

File

Revisions

and

the

CONFIG:DAT

It is possible that for every
revision
related
CADIF
file may change.
Hence,
CADIF files were intended to reflect the

(For

example,

revision
rule and

not

CSBB02.CDF

B02).
This,
as a result,

followed.

the

file

of
a
given
module,
the
the names allocated to the
revision
of
the
module.

CADIF

file

for

however, became the exception
the naming canventlcn for the

the

CSB module,

rather than the
CADIF files was

CONSOLE

HARDWARE

To determine the correct CADIF file for any
revision
of
a
given
module within the system, use Table 9-12 for the VAX 8600 and Table
9-13 for the VAX 8650.
To ease the task of keeping
track
of
the
different
CADIF
files, the CONFIG.DAT file was implemented.
This
file contains a list of the .CDF files and is initially
loaded
by
the
console
software.
Thus,
for a given system, the CONFIG.DAT
file must be at a specific revision.
This is
taken
care
of
via
console RL0O2 pack revisions.
For example, if your system (KA86) is
at Rev.
H3, then you must use a Rev.
5.0 RLO2
pack
(which
will
have the appropriate CADIF and CONFIG.DAT files).
Note that if the correct RL0O2 pack revision
1is
used
on
a
given
revision
KA86
system,
it
should not be necessary to investigate
and/or alter these files as the
console
software
and
CONFIG.DAT
file should handle the configuration.
The

CONFIG.DAT file may contain a comment field
for
each
of
CADIF
files
which
indicates a module revision.
Beware that
field is information
only
and
may
not
accurately
reflect
revision(s) of the module(s) supported by the CADIF file.

Table

9-12

VAX 8600 CADIF
File

Module

File

Revision

Module

CADIF

L0217

CLKCO03.CDF

Revision C5 and earlier

Revisions

L0217
L0215
L0216

CLKEO1.CDF
CSAB02.CDF
CsBB02.CDF

Revision
ALL
ALL

L0210
L0211

EBCCO05.CDF
EBDDO02.CDF

ALL
ALL

L0219
L0209

EBEB02.CDF
EDPCO2.CDF

ALL
ALL

L0212
L0213

FBABO1l.,CDF
FBMCO1.CDF

L0208

IBDFO5,CDF

L0207

ICAHO2.CDF

ALL
ALL
ALL
ALL

El1

and

Supported

later

L0214

ICBF0l1.CDF

ALL

L0206
L0205
L0220

IDPF02.CDF
MAPDO2.CDF
MCCJ04.CDF

ALL
ALL
Revision

L0220
L0204
L.0222

MCCKQ01.CDF
MCDDO0O4.CDF
MTMBO1.CDF

Revision K01l and later
ALL
ALL

LONNN
LONNN

VBAAQl.CDF
VBBAO1.CDF

(SBIA VISIBILITY MODULE
(SBIA VISIBILITY MODULE

J04

and

Information

earlier

1)
2)

Mfg only
Mfg only

NOTE

This table reflects a VAX 8600 with Rev.
or hardware revision KA86 Rev.
H3.

5.0

RLO2

the
this
the

CONSOLE

Table

9-13

VAX

8650

Module

CADIF

L0231

CLKEO1.CDF

ALL

L0216
L0210

CsSBB02,.CDF
EBCCO5.CDF

ALL
ALL

L0211

EBDDO2.CDF

ALL

L0219

L0209

EBEB02.CDF
EDPCO2.CDF

ALL
ALL

L0212

FBABO1.CDF

ALL

L0213

FBMCO1.CDF

ALL

3 L0215

File

CSAB02.CDF

CADIF

Module

File

Revision

Revisions

HARDWARE

Information

Supported

ALL

L0208

IBDF05.CDF

ALL

L0207

ICAHO2.CDF

ALL

L0214

ICBFO1.CDF

ALL

L0206

IDPF02.CDF

ALL

L0205

MAPDO2.CDF

ALL

L0230
L0204

MCCKO01l.CDF
MCDDO0O4.CDF

ALL

L0222

MTMBO1.CDF

ALL

LONNN
LONNN

VBAAO1l.CDF
VBBAO1.CDF

(SBIA VISIBILITY MODULE
(SBIA VISIBILITY MODULE

ALL

Mfg

only

Mfg

only

NOTE

.
%

This table reflects a VAX 8650 with Rev.
or hardware revision KA86 Rev.
B.

9.6

REMOTE

9:;6:.1

1.2

RLO2

DIAGNOSIS

General

This
section
describes
the
use
of
remote
diagnosis
troubleshoot
the CPU.
Use remote diagnosis to help solve
with the system that you cannot isolate at your particular
RD

involves connecting the
(DDC), by telephone line.

system

the

Digital

DDC can find system failures to the device level
faulty
operational
problems
over
the
telephone.
allows you to run tests on the system, without having

and

the

site.

use

RD,

the

you

This

equivalent)

fi?,s,z

must

phone

full

have

1line

direct

must

dial

phone

line

connected

Center

identify

This service
an
engineer

site.

Diagnostic

The

room.

(RD)

problems

duplex modem.

computer

AT&T

103

(or

Setting—-up the DF112 Modem

" Remote Diagnosis
the

modem

modem,

and

connections
appropriate

involves setting up the

the

wusing

system

the

and

console

the

DF112

telephone

software

modem,

line,

make

the

to the DDC.
The DDC takes over from there,
diagnostic routines to isoclate the problem.

9-19

connecting

self-testing

the

necessary

running

the

CONSOLE

HARDWARE

For systems shipped to sites within the U.S.
modem will

included with

the

The
chapter
references
in
the
DF112 User's Guide
(EK-DF112-UG).
modem.

Install

the modem as

and Canada,

DF112

system.

following
steps
refer
to
the
This guide comes with the DF112

follows:

)

Unpack and inspect the DF112 modem (Chapter 2).

Set the switchpacks S1 - S4

If you are using a standalone modem, install the standalone
modem module in the DF112 modem (Chapter 2).

Connect the standalone
modem
to
the
telephone network service (Chapter 2).

Connect one end of the data terminal equipment (DTE)
cable
(BC22E-xx)
1into the DTE connector on the rear of the DF112
modem as shown in Figure 9-9.
Connect the other end of the

cable

the

connector

distribution panel
6.

(Refer to Figure 9-7)

required modem options.

Set the

DF112

marked

appropriate

REMOTE

panel

the

public

on the KA86 line

(refer to Figure 9-8).

front

for

pushbuttons

the

correct

positions.

Ensure that the VAX 8600/8650 system is in CIO mode
(i.e.,
at
the
">>>>" prompt) and the terminal control switch, on
the SCP,

10.

in the REMOTE ENABLE position.

Verify that all
"TR",

are

indicator lights on the DF112,

Test modem
operation
by
making
a
connection
alternate originating modem and terminal.
Call

except

fo\

off.

the RDC and reguest an

"RD install"

using

verify call.

CONSOLE

SWITCHPACK S1 (E20)

SWITCHPACK S4 (E5)
ggfi g&s}gi 85-6 FOR

SEE TABLE 53 FOR
SELECTIONS
OFF

1111 I

OFF ON

)

}

CIm
4
CIm 3

—

Taly

ml 5

IR TATI

CIm 7

mg
I

NOT

USED

m 4

SWITCHPACK 4 IS ONLY
INSTALLED ON REV C

SWITCHPACK S3 (E41)

MODULES AND ABOVE

SWITCHPACK S2 (E19)
SEE TABLE 54 FOR

SELECTIONS

OFF ON

@ 3

il i

SEE TABLE 55 FOR

SELECTIONS

OFF ON

o 1

CIm 2

o 2

@ 3

oD 4

s 5

mD) ¢

)

s 9
I 10

HARDWARE

o 3

CIm 4

Cm 5
I6

Cm 9
ol 10

NOTES:

1. STANDARD FACTORY SELECTIONS SHOWN
2. REFER TO DF112 MODEM FAMILY USER GUIDE (EK-DF112-UG)
FOR SWITCH SELECTIONS
MR-16141

Figure

9-7

DF112-AA Switchpack

Locations

LINE

DISTRIBUTION

PANEL

A\NAY

TUB1/UDASD

Ci1780

CONNECTORS

(OPTIONAL)

Figure

9-8

KA86

Line

Distribution

9-21

MR-146684

Panel

)

HARDWARE

CONSOLE

/’

N
DF1Y2

eeeeesee

OOOOOO
RL DL MS ?::?l
L

BD RDCD TAMROH HS TTMM

8 POSITION MODULAR JACs
FOR TELEPHONE HANDSEY

PRIVATE LINE

CONNECTION

]

{

TELEPHONE
SEY

AC LINE

AC POWER

8 POSITION MODULAR JACK

FUSE

CORD

FOR TELEPHONE LINE

RECEPTACLE

{D.54A)

DATA TERMINAL

EQUIPMENT {DTE)

CONNECTOR

L - BLE.

Figure

9.6.3

Using

Once you

have

9-9

the

DF112 Modem

Set Terminal

completed

steps

Command
1

through

above,

you may

use

SET TERMINAL command to change the communication parameters
modem.
Use the SET TERMINAL command for the following:

Change the baud rate for receive and transmit

Enter

the

DDC

9-14

sets terminal port characteristics
the system.
See Table 9-14.

Set Terminal

SET TERMINAL/switch,

the

for

the

password

The SET TERMINAL command
CTY or RTY interfaces on

Table

the

for

where

Syntax and Switch

"switch"

can be

any

Description

the

following

parameters.

Parameter

/BAUD:nnnn

Function

{

Sets the transmit and receive baud rate for the CTY

port.

CONSOLE

Table

9-14

SET TERMINAL

Parameter

Syntax

and

Switch

Description

HARDWARE

(Cont.)

Function

%’/RECEIVE:nnnn

Sets

the

receive

baud

rate

for

the

RTY port.

| /TRANSMIT:nnnn

Sets the transmit baud rate for the RTY port.
NOTE

The

possible
values
for
"nnnn"
in
the
above
switches
are:
50,
75,
110, 134, 150, 300, 600,
1200, 1700, 2000, 2400, 3600, 4800, 7200, 9600, and
19200.

/ [NO]PARITY

Enables

characters

disables

the use
transmitted from

bit

Selects

/0DD

Selects odd parity for RTY port transmissions.
Data Set
high
an

/ [NO]SCOPE

Rate
at

Specifies

the

port

(DSRS)

RTY

port

selects
This

that

the

transmissions.

1low

speed

switch generates

23.

type of terminal device used

characters

. /PASSWORD
%

Select

speed modem operation.

output

for RTY port

a
parity
RTY port.

/EVEN

/[NO]DSRS

even parity

of
the

device

handles

the

rubout

correctly.

Sets the login password
for
the
RTY
port.
The
password,
if
wused, must consist of no more than 6

characters

and

characters

must

contain

-z,

only

2).

alphanumeric

1If

no password
is used, the RTY port password feature is disabled.
With
no
password,
the setting of the front panel
Terminal Control Switch controls RTY access to
the
CPU.
NOTE

All

terminal

TERMINAL

characteristics

command

are

saved

set
in

console

the

SET

memory

and

lost

when the console reboots or fails.
Therefore,
it
important that the SET TERMINAL commands be
placed in the CPU initialization file, LOAD.COM

Example

SET

9=1

Set

Terminal

Command

TERMINAL/BAUD:9600<RETURN>

Set the
transmit
and
baud
rates to 9600 for

receive
the CTY

port.

SET/TERMINAL/TRANSMIT:4800<RETURN>

To set

SET/TERMINAL/RECEIVE :4800<RETURN>

receive baud rates
the RTY port.

the transmit and
to

4800

for

EAfter completing the above steps and using the SET TERMINAL command
/to

set

system.

the
See

communication
Figure

9-10

environment,
for

the

flowchart

port.

9-23

DDC

can

control

now
of

diagnose
the

the

remote

HARDWARE

CONSOLE

REMOTE HANDLER IDLE LOOP

REMOTE CONNECT SEQUENCE
REMOTE
A

YES

REMOTE DISABLE

DIR=
RIS =1
REMOTE LED ON

YES

SEC TIMER

WAIT 520 M5

NO
NO

YES

ves | START
-

PRINT "RTY

PRINT <CR><LF>

{4 “CONSOLE

2 MIN

PASSWORD 7

TIMER

DEASSERY
DTR AND
START 2

SEC TIMER

CONNECTED"

)

LOGICIAL
DTR =1

REMOTE ACTIVE

LED OFF

YES

LOGICAL

’

CARRIER

'RTY

DISCONNECTED |

)

TO CPu {RX)

W8 18333

Figure

9-10

Console

Remote

Port

Control

Flowchart

CHAPTER

CONSOLE

SOFTWARE AND COMMANDS

VAX CPU
PIO

»{

BASED MACRO

PROGRAM

CONSOLE

TTY

START OR

(LCL/REM)

CONTINUE

T11 BASED
CONSOLE
SOFTWARE

»|

MRB-15383

NOTE:

CONTROL-P DOES NOT SWITCH MODES
IF THE TERMINAL SELECT SWITCH IS

IN ONE OF THE TWO DISABLE POSITIONS.

Figure

10-1

Console

Software

Modes

PIO MODE
'(START)

(AP)

(CONTINUE)

Ci0 MODE

.
:

(PEBUG)

gggfigggg&%

DE>>

BOOT

(EXIT)

MACRO CONTEXT

(DIAG) |

(DEBUG)

(MACRO)|

CONTEXT
,

PROM

PROM CONTEXT
ROM>

(MHC)

(DIAG)

DIAGNOSTI

(EXIT)

MICROHAR

DCORE

| (muc)

-DC>

|CONTEXT
>

MH>

MR-13503

Figure

10-2

Console

Mode

Contexts

10-1

CONSOLE

10.1

SOFTWARE

CONSOLE

AND COMMANDS

COMMANDS

Chapter 10 will include the console commands not found
in
Chapter
6,
Diagnostic¢s, namely:
General commands, MACRO Context commands,
and HEX commands.
The PROM commands,
MHC
Context
commands,
and
Micro-Diagnostic Context commands are in Chapter 6.
If more help is
needed
on
any
console
command,
facility as shown in the following example.
Example

10-1:

the

Help

context

fcommandi",

Console

and

command

for

instance,

use

the

help

Commands

known,

type:

"HELP

{context]}

"HELP MACRO DEPOSIT".

If you are looking for a command and are
to
use,
you can find out what commands
context by
typing:
"HELP
f{context}",
MACRO".
The console will print out all
the MACRO Context.

not sure what
context
are available for each
for
instance,
"HELP
of the commands within

then

10.1.1

the

names

Control

The control
10-1.

DELETE

10-1

Rubout

contexts

escape

you,

for

the

Console

last

console

Command Control

character

Flush Command
Retype

CONTROL-P

Abort

current

are

listed

in Table

Characters

line

from RTY

command

Abort current command

Console Command

console

"HELP".

typed

Toggle output display ON/OFF

The

type

Line

CONTROL~-0

10.1.2

command

commands

CONTROL-R

CONTROL~-S

just

Characters

characters

Table

CONTROL-U

the

commands

use

Syntax
brackets

([

])

indicate

optional

switch
or keyword and braces (] 1) to show a list of choices where
one item must be selected.
For
example,
in
the
MACRO
command:
"EXAMINE
[/space]
[/next :hex_number]
[/data_type]
{[hex_adr,
reg name]}, the /space switch
is
optional
and will
default
to
/PHYSICAL
if not used.
The /next switch allows the examination of
the next "hex_number" locations if
used,
and
1if
not
used,
the
default
1is to examine only the addressed location.
The /data_type
switch is also optional, and the
default
is
/LONG.
Within
the
braces,
we
have
to
pick
one
of the two, either a hex_adr or a
reg_name to provide the location that we want to examine.

CONSOLE

10.1.3
Table

SOFTWARE

AND

COMMANDS

Architecturally Defined Commands and Switches
10-2 lists

Table 10-2

the architecturally defined commands and switches.

Architecturally Defined Commands and Switches
Short

Long

Short

Long

Form

B
C
D

BOOT
CONTINUE

N
S

NEXT
START

DEPOSIT

SET

EXAMINE

SHOW

H
I

HALT
INITIALIZE

A
W

VERIFY
WAIT

LOAD

/PHYSICAL

FIND

UNJAM

NOTE

The standard register names are
listed
under
the
MACRO Context DEPOSIT command.
For GPRs, see Table
10-7, IPRs, see Table
10-8,
and
1IRs,
see
Table
10-10.

10.2

GENERAL COMMANDS

Commands in the GENERAL COMMAND set are available to all
CIO
mode
contexts
(MACRO,
DIAG,
and
MHC).
It
provides
the
commands
necessary
to
change
context
and
control
the
basic
console
functions.

The control characters “C and “P are considered to be a part of the
general
command
set.
While in CIO mode, these control characters
are treated as equivalent and will abort most command lines and all
levels of command

files.

Table 10-3 is a complete
1list
of
the
commands
in
the
general
command
set
with
a
brief description of each command.
For more
information,

10.2.1

use

the

"HELP"

The General Command Set
Table

DEBUG

command.

10-~3

Enables
the
concatenated

command sets.
See

General

Commands

HEX
debugger
command
set
to
be
to
the
MACRO
and
DIAGNOSTIC context
All
trace
breakpoints
are
cleared.

HEX command

set,

Table

10-«11.

DIAGNOSE

Switch to CIO mode DIAGNOSTIC context with diagnostic
context initialization.
See Chapter 6.

HELP

This command provides on=-line
console

[Cond,

"Cond"

and

help

8650,

FPA,

the

various

commands.

Cond]

Cmd_string

is one or more of

"Cmd_string"

8600,

NOFPA,

is any command valid in the current

context.

10-3

CONSOLE

SOFTWARE

AND

COMMANDS

the

condition(s)

command,
INITIALIZE

otherwise

INITIALIZE

{/CLOCK,

(are) TRUE, then
execute
not execute the command.

/POWER,

/SDB}

This command performs
the
initialization
fundamental system components.

INIT/CLOCK -

CLOCK

three

Initializes
the
system
clock
1logic (10141 reset) and

clock
distribution
the clock parameters
SET

the

DEFAULT

those

saved

command.

For

with

the

console

and
sets
last

reboot,

the saved parameters are lost
and
this
command
will
wuse
normal frequency, and full speed.
The
state

the

SOMM

enables

1is

cleared

this

command.

INIT/POWER - This command
the
power
system.
At
voltage regulators are on
and

the

flow,

EMM

and

initializes the EMM and
command completion, all
with
normal
margins,

monitoring

temperature

INIT/POWER/ELEV:n
INIT/POWER
command,

regulator

outputs,

air

conditions.

An
it

optional
used to

form

of
the

adjust

the
EMM

yvellow

and red zone temperature limits to account
for
systems
at
sites
considerably
above
sea
level.
"n" is the site elevation in feet.

INIT/SDB

This

channels

the

state

The

control

operation.

command

forces

all

SDB

control

necessary

for

normal

system

channels

are

loaded

follows:

LOAD

(CS)

LOAD

CsB

0008;

-FLIP

USTK

PAR

EDP

0060;

¢.

EBC

= A000;

Set

-FLIP

DIAG

GPRA

EBC

C000;

Set

EIS

EBC

EQ000;

Set

control

~FLIP

FBA

0000;

Normal

FBM

0000;

Normal

operation

IBD

1000:

Normal

operation

ICA

0000;

Normal

operation

MCC

0000;

Normal

operation

VBA

0801;

Normal

SBIA

[filename

0
0

NOP

{/Switch}

GPRB

operation

(Optimize)

operation

[.BPN]]

"SwitchTM can
be
any
of
the
following:
/ACCESS,
/CONTEXT, /CYCLE, /ECS, /FBACS, /FBMCS, /FDRAM, /ICS,
/IDRAM, /MCF, or /MCS and "filename" is the
name
of
the
.BPN file to lovad.
If no filename is specified,
the

default

system microcode will

10-4

loaded.

CONSOLE SOFTWARE AND COMMANDS
The

This

command

console
RAM.

load

Not

loads

the

medium

all

having

been

command

(see

control

file

specified
can

10-4

Default

without

The INIT/MICRO
default system

8600

System Microcode

ACCESS

ACCESS.BPN

CONTEXT

CTX.BPN

ACCESS.BPN
CTX.BPN

CYCLE

CYCLE.BPN

ECS

KA8600.BPN

VAX

8650

KA8650.BPN

FBACS

FADDO.BPN

FADD5.BPN

FBMCS

FMUL.BPN

FDRAM

FADDO.BPN

FADDS5.BPN

ICS

IBOX.BPN

IDRAM

KAB8600.BPN

KA8650.BPN

MCF

MCF.BPN

MCF .BPN

MCS

UCODEO.BPN

UCODE5.BPN

LUPC

the

10-4.

VAX

10-2:

from
store

1loaded

INIT/MICRO console

RAM

Example

Set

(.BPN)

context commands).
KA86n.REV
to
1load the

Table

Command

control

MACRO

If the
specified
loaded,
and
has
terminate without

LUPC

the

stores

1initialized with the

command
used
microcode, see

Table

specified

General

control
store
has
already
been
not been modified, the command will
reloading the control store.

LOAD/ECS

KA8650

/Switch hex address

"Switch" is one of
/FBACS, or /FBMCS.

the

following:

/ECS,

/ICS,

/MCS,

This command will force the specified
microsequencer
to the address specified by hex_address.
MACRO

This

command switches to the CIO mode MACRO
context.
MACRO context will perform its own initialization
then prompt for command input.
See
Table
10-6
for

The

MACRO

MHC

This

context

command

CONTEXT.

commands.

switches

MHC

then prompt

for

will

the

CIO

mode

MICROHARDCORE

perform its own initialization,

command

input.

See

Chapter

commands.
ODT

The

Octal

Debugging

command.
The
command set is
ODT products.
PROM

PROM

[/RT

ODT

Tool,
prompt

similar

from
the

that

is invoked
with
this
asterisk, *.
The ODT
of
the
standard
DEC

pass
control
to
the
asked
to
confirm the

control is changed.
This
the
RTY, and the PROM will

command
continue

console
request

is
wvalid
to service

RTY.

If the /RT switch
the
RT
monitor,
not

for MHC

[filename]

The PROM command will
PROM.
The
wuser
1is

before

ODT,

recommended

nor

provided

for

supported.

10-5

allow

INTERNAL use

entry

only

and

CONSOLE

The

SOFTWARE

General

REBOOT

AND

Command

This
The

COMMANDS

Set

command will
console will

and

attempt

command

was

the CP was

reboot
follow

the
its

re-enter

issued

while

running

REPEAT

[Bec_num]

software.

normal power-up procedure
PIO

mode;
if the
MACRO context,

in the
the time.

When issued from
the
DIAG
command will not attempt to
REPEAT

console

or
MHC
re-enter

REBOOT

and

contexts,
PIO mode.

this

command

"Dec_num" specifies the number of times
the
command
is
to
be
repeated.
If not specified, the command
will be repeated indefinitely, or until a ~“C or “P is
entered.

Commands

The
“0
causing
RESET

This

requiring
character

the

performs

CPU

logic

initialization

follows:

The CPU clock
T3 state.

The

signal

"CL09

CPU

The

signal

"CL09

HOLD STATE RESET H"

The
for

CPU clock is
1024 steps.

burst

forced

"CLO9

CPU

The

CPU

The

signals

STATE

RESTART

input
cannot
be
repeated.
be used to bypass the output,
function to run faster.

may

repeat

command

sequence

user

clock

RESET"

are

stopped

and

RESET

state~stepped

RESET

the

asserted.

frequency

the

asserted.

MHz

state.
and

"CLO9

HOLD

deasserted.

This
command
will
force
a
console
program
initialization
and a restart of the console program,
without reloading the
console
software.
A
REBOOT
command is needed to reload the console software.
At
the end of the initialization, control is
passed
to
CIO mode MACRO context, followed by the MACRO context
initialization.

SET BASE

SET

BASE

The base,
and

or
SET

32-bit

value,

physical

memory
D/P commands.

SET Flag
"Flag"
BBU,

SNAP,

the

hex_number

{ON/OFF}

is added

addresses

[INVALID,

both

during

E/V,

/NOVERIFY,

NOW}

virtual
D/V,

E/P,

can be any of
the
following:
ABORT,
ABUS,
COLD,
EXTI,
FBOX, IOSAFE, LOCAL-COPY, MEMENA,
STXALT, WARM, or QUIET.
This command
controls

setting

console

of
software
subsystem.

10-6

and

hardware

flags

the

CONSOLE

SOFTWARE AND COMMANDS
The General Command Set

Setting the COLD, WARM, FBOX, and
STXALT
flags
are
applicable to the MACRO context only and result in no
ABORT
The
program.
immediate action by the console
and
QUIET
flags
control the handling of errors and
command line echoing during a command file.
The EXTI

(external interrupt) flag and the ABUS flags directly
control hardware signals on the console module.
Use
the
SHOW
FLAG
command
to examine the state of all
flags.
The
/INVALID,
/NOVERIFY,
and
NOW
options
apply

to the SNAP flag only.

During a console reboot, the ABORT flag is forced ON,
FBOX, and WARM flags are forced OFF.
COLD,
the
and
The remaining flags are restored
to
their
original
state or

Table

are

not

affected.

10-5 lists the flags and a brief description of

each.

ABORT -

Table

10-5

Console

This

flag

Flags

console

during

set

program initialization or whenever the console

rebooted.

limited

The ABORT flag provides a

handling

error

the

execution

file

Command

within

will

control

command

aborted

over

file.

wupon

detection of an error if the ABORT flag is on.
2.

ABUS -

program
reboots.

enabled.

and

1is

during

transition

from OFF

to be generated

pulse

to ON

causes

ABus

INIT

reboot.

When the BBU flag is on, the battery backup
is

enabled

power

unit

to provide power to the system if ac

lost.

COLD - The COLD flag is set
ON
by
the
console
program
during a CPU bootstrap.
The flag is set
to OFF when the bootstrap completes with success.
The

COLD

attempts

BBU - The BBU
flag
1is
set
ON
during
console
initialization and by the INIT/POWER command, and
is unaffected by a console

in the SBIA's.

The INIT/PAMM command
generates
the
sequence and leaves the ABus enabled.

console

unaffected

controls
the
signal
"CL09
ABUS
|is
ABus
the
on,
is
flag
this

The

INIT

OFF

set

initialization

The ABUS flag
If
ENABLE".

ABus

1is

flag

This

flag

1is

wused

at unsuccessful

inhibit

repeated

CPU bootstraps.

EXTI - The EXTI flag
controls
the
enabling
of
interrupts, interrupts from the EBox to
external
receive
will
When ON, the console
the console.
the

interrupts

from:

10-7

CONSQOLE

The

SOFTWARE

General

AND

Command

COMMANDS

Set

EBE

CPU

ERR

ADus

DEAD

EMM

CPU AC

The

EXTI

flag

remains
operation.
In

any of

FBOX

the

store

parity

errors)

and

(control

set

the
state

INIT/CPU
command
during
PIO
mode
this flag is turned
off
interrupts occur.

this

CIO mode,
three CBus

This

flag

DOES

This

flag

controls

NOT

turn
the
FBox
on
or
the action of the INIT,
commands.
If
the
FBox
flag
1is on, these commands will enable the FBox.
If the FBox flag
is
off,
these
commands
will
disable the FBox.

off.

INIT/CPU,

INIT/PAMM

This

flag is set
initialization.

IOSAFE

write
CPU.

The

to OFF

IOSAFE

during

flag

console

controls

program

software

protect feature for STX transfers from the
When OFF, the CPU can modify the RLO2 pack.

This

flag is set to OFF
during
console
initialization and its statc is preserved

console

reboots.

LOCAL-COPY

logged

console

- With

the

program

cannot

set

this

MEMENA

This

RIS

modules

flag

the

flag

ENABLE",

flag

on,

all

The

flag

console

activity

OFF

its

reboot,

during

state

and

the

RTY

off.

controls
which,

arrays

their

RTY

set

initialization,

during

access

this

CTY.

preserved

MEM

program
through

the

when

and

internal

state

off,

switches

refresh

"CL09

disables

all

write

array

state.

This flag is
set
ON
by
the
console
software
during CPU initialization and normally remains on
until a power failure or system shutdown occurs.
10.

SNAP

This

flag

set

program

initialization,

preserved

during

When

the

perform

SNAP
a

executing

ON/NOVERIFY
and

PAMM

console

flag

CPU

1is

OFF
and

during
its

on,

the

console

whenever

the

instructions.

may be

used

verification

console
state

reboot.

snapshot

macro

thereby providing

to disable
during

quicker

will
stops

SET

SNAP

control

store

the

snapshot

CPU

snapshot,

procedure.

SET SNAP
INVALID
1is
wused
to
invalidate
both .
SNAP1.DAT
and
SNAP2.DAT
snapshot
files on the
RL0O2.
This command has no
affect
on
the
SNAP

flag.

10-8

CONSOLE SOFTWARE AND COMMANDS
The

General

Command

Set

NOW may be used to force the creation of
a
snapshot
file
based upon the current machine
state.
If both SNAPl and SNAP2 are
valid,
this
command
will
rename SNAPZ2 to SNAPl and create a
new SNAP2.

_— MW ’

SET SNAP

11.

QUIET - When the QUIET
flag
1is
ON,
all
input
taken
from
a command file will not be echoed to
the CTY, only output
will
be
displayed.
When
OFF,
all commands in the command file are echoed
on the CTY before being executed.
This
flag
is
set
initialization, and
console reboots.

12.

STXALT

- This

flag

ON
during
console
program
its state is preserved during

intended

wused

manufacturing and is not for customer use.
It is
used to direct CPU data to the alternate
console
disk, Unit #1.
When this flag is on, all console
disk access will be to RL0O2
#0,
while
all
CPU
traffic will be to Unit #1.
This flag is set to OFF
during
initialization, and its state is
console

13.

console
program
preserved during

reboots.

WARM - The WARM flag is set
ON
by
the
console
program
when
a
CPU restart is being attempted.
The CPU sets this flag OFF when
the
restart
|is
successful.
The
purpose of the WARM flag is to
inhibit repeated
attempts
at
wunsuccessful
CPU
restarts.

14.

SET CLOCK

For

Rev

E01

and above

SET CLOCK Xn
Dec_num
This
command
assigns

clock modules

[{/NORMAL,

/HIGH}]

the
"Dec_num" (clock
frequency in MHz, 40 to 65 for a VAX 8600 and
40
to
90
for
a VAX 8650) to the specified
crystal mnemonic, X1,
X2,
etc.,
where
the
mnemonic
can
then
be used to set the clock

frequency.

Any of

the Xn

mnemonics

can

assigned
as
the
normal
or high clock rate
with the /NORMAL or
/HIGH
switches.
These
assignments should be done once in CLOCK.COM.
The Xn assignment is preserved during console
reboots.
‘
Example

10-3:

SET CLOCK

SET
SET
SET
SET
SET

CLOCK
CLOCK
CLOCK
CLOCK
CLOCK

X1
X2
X3
X4
X5

SET

CLOCK X6

40
50
68
72/NORMAL
74/HIGH
76

SET CLOCK FREQUENCY {NORMAL,
HIGH,
X1,
X2,
X3,
X4,
X5, X6, EXTERNAL} - This command is

used to select one of the previously assigned
values
(X1,
X2,
etc.)
as the system clock
frequency, or the
nominal
and
values
can
be
selected
with
NORMAL

HIGH.

10-9

high
margin
the keywords

CONSOLE SOFTWARE AND COMMANDS
The General Command Set

EXTERNAL

can

wused

specify

that

the

This

clock
be
taken
from
the
external
input
backplane pin.
The SET
CLOCK
Xn
"Dec_num"
command must have been executed prior to this
command.

SET CLOCK
command

{FULL,
sets

ONE-FIFTH,

the

c¢lock

console

save
FULL/ONE-FIFTH

and
subsequent
setting.

15.

SET CLOCK

This

Rev CO05

FREQUENCY

command

clock frequency
(NORMAL),
or
a

Or,

current

full

forces

the

base

information
INIT/CLOCK commands

SET CLOCK - For
a.

the

DEFAULT!
rate

one=fifth execution speed.

frequency

to be used
by
as the default

clock modules
[Dec_num,

selects the
source,
a

NORMAL,

QUIET}

source of
50
MHz

the CPU
crystal

variable control oscillator
(VCO), with frequencies in the range of 40 to
64
MHz (Dec_mum).
The QUIET argument can be

used to silence the warning messages
occur

SET

SOMM

SET

some

VCO

that may

settings.

SET CLOCK

[FULL, ONE-FIFTH, DEFAULT}!
This
command
sets
the
clock
rate
to
full
or
one-fifth speed, and forces the default clock
settings to become the present values used by
the INIT/CLOCK command.

SOMM

[/Switches]

SOMM means

Stop

[ON

OFF]}

MicroMark,

and

switches

can

any

combination
of
the following:
/ECS, /ICS, /MCS, or
/FIELD.
If no switch is specified when turfilng
SOMM
on,
when
off.

the
default is /ECS.
turning SOMM off, all

If no switch
SOMM
enables

specified
are
turned

This command controls the enabling and
disabling
of
micro-mark
breakpoint
detection
in
the
CPU clock
module.
When enabled for one or more control
stores
the
CPU
clocks
are
stopped in the TO state when a
mark breakpoint is encountered.
A microcode mark bit
has to have been previously set with the DEPOSIT/MARK
command.

See

HEX commands,

When the micro breakpoint
UPC

the

EBox,

IBox,

and

Table

10-11.

detected,

MBox

the

current

displayed.

If the
clock
rate
was
FULL,
the
UPC
data
will
be
2
microcycles past the breakpoint microinstruction.
If
clock rate is One-fifth, the UPC data will match
the
breakpoint
micro
address, and the micro instruction

will have already been executed.
For this
case,
it
is
necessary
to SET SOMM OFF to proceed with a TMIC
or

TSTATE.

All SOMM flags
are
initialized
to
the
during
console
program
initialization
INIT/CLOCK command.

10-10

OFF
and

state
by the

CONSOLE SOFTWARE AND COMMANDS
The General Command Set

Example

SET SOMM/ECS ON

SET TERMINAL /Switches

SET TERMINAL

10-4:

The defaults shown are the ones
software

set

during

console

initialization.

Switch

Initially Set

/BAUD:nnnn
/RECEIVE:nnnn
/TRANSMIT:nnnn
/PASSWORD [password]

As set in STARTF.COM
1200
1200
No password delined

/ [NO]SCOPE

SCOPE

/ [NO]PARITY
/ [NO]DSRS

NOPARITY
NODSRS

/0ODD

Default

if parity

1is enabled

/EVEN

The

value of

300,

600,

9600,

"nnnn"

1200,

can be:

1800,

50,

2000,

75,

2400,

110,

134,

150,

3600,

4800,

7200,

19200.

This command sets the terminal
port
characteristics
for
the
CTY
and RTY interfaces.
While in CIO mode
the most significant bit of characters received
from
the
CTY
or
RTY is stripped off, while in PIO mode,
full 8=bit character handling is supported.

The default
1

stop

for the RTY is

bit,

parity,

1200 BPS transmit/receive,
no

DSRS,

SCOPE,

and

password.

The /BAUD switch applies to the CTY while
switches apply to the RTY.

The RTY can enter only
other
switches must be

all

other

the
[NO]JSCOPE
switch.
All
issued from the CTY.
The CTY

[NO]SCOPE flag can only
be
done
by
modifying
the
STARTF.COM
command file and rebooting the console so
that RT executes the command file.
By
default,
the
CTY

SHOW CLOCK

NOSCOPE.

This command displays the current state
and

SHOW FILE

Example

SHOW FLAGS

the

CPU

SHOW filename[.DAT] [{/ASCII, /BINARY }] This command
displays the selected file on the console terminal in
a binary format (default)
or
in
a
straight
ASCII
format
if
the
/ASCII
switch is used.
The /BINARY
switch can only be
issued
from
the
RTY
with
the
remote
protocol running.
transferring binary files

system clock.

This

10-5:

c¢ommand

console

program

It is meant as a means
to a remote site.

for

SHOW SNAP1.DAT/ASCII

displays

the

control

flags.

10-11

current

state

the

CONSOLE

The
SHOW

SOFTWARE AND COMMANDS
General Command Set
PANEL

SHOW

PANEL

[/TEST]

This

command displays the current settings of the SCP
switches and indicator LEDs.
The /TEST switch causes
the command to loop while
shifting
a
floating
"1"
through
the
LEDs
and
reading back each pattern to
|
verify the LED logic.
Changes in either
SCP
switch
will be included in the updated display.
SHOW

POWER

This

command

power

SHOW

TERMINAL

This

displays

system,

command

and

the
the

current
CPU

status

cabinet

the

EMM,

environment.

displays

the

state

the

displays

the

state

all

control

file

name.

for

that

control

the

currently

loaded

the contents
modified since

CTY

and

RTY

ports.

SHOW

UCODE

This

command

and

RAMs

Thec

current

(last

loaded)

The

default

.BPN

file

stores

follows:
.BPN

name

store.

The
UCODE
microcode.

The

RAM

status

Bit

revision

Bit

follows:

the control
last load.

has

equals

has

discrepancies
c.

Bit

<13:00>

error

equals

store

command

the

- These

count,

and

ACC

the

control
bits

RAMs

This

command

following

shows

the

The

console

The

revision

the

console

The

revision

the

EMM

The

major

Various

program major

System

These

two

detected

store,

whether
MCF, CTX,

not.

The

show

"0"

1in

this

for

the

revision

address

revision

PROM

the

interest

(Hex

code

system microcode

value

fields)
START CPU
STOP CPU

parity

information

debuggers
6.

the

items:

data.

number

the

VERIFY

store

control

always

revision

the

one

indicate

total

field.
SHOW VERSION

"1",

detected

parity errors for the
they
were
corrected
CYC,

"1";

been

developers

and

broken

down

and

commands

provide ON/OFF control of the CPU
clock.
1If the SYSTEM clock is off,
then
the
START
CPU
command
will
start
it before starting the CPU
clock.
The STOP CPU command stops the CPU clock
but
does

not

affect

the

system

10-12

clock.

CONSOLE

SOFTWARE AND COMMANDS
The General Command Set

START

SYSTEM
STOP SYSTEM

These two commands provide ON/OFF control of the
SYSTEM clock.
If the CPU
clock
is
on,
then
STOP
SYSTEM will stop it before stopping the system clock.
The START SYSTEM
command
starts
the
system
clock
running
at
the
frequency last set by the SET CLOCK
FREQUENCY command.

UNHANG

The
UNHANG
command
will
reset
the
CPU
without
clearing latched error status or affecting the system
The command performs the UNHANG by:
cache.
1.

Stopping the CPU clocks

Asserting the console

signal

"CL09

HOLD

STATE

RESET"

VTERM

Bursting the CPU clock

Deasserting

"CL09 HOLD STATE RESET"

Loading the

EBox uPC with

Starting

VTERM

1024 ticks

100D

the CPU clock

{Symbol name,

Hex_ID}

Symbel name
is
the
V$
symbol
assigned
to
the
visibility
signal by the SDB CADIF (.CDF) files, and
Hex ID is a 16-bit SDB
1ID.
SDB
1IDs
are
hardware

visibility

addresses

files.

and

are

defined

in the

.CDF

This command provides a fundamental aid for isolating
faults
in
VTERM
and visibility logic.
The command
accepts a V$ symbol or SDB hex ID
and
sets
up
the
visibility control logic to select the specified bit.
The visibility bit is left selected
so
that
static
measurements
can
be
made.
Only a console RESTART,
REBOOT, or another VTERM command will reset the state
of
WATIT

the SDB control

WAIT

[Hex

logic.

count]

This
command
will
cause
processing
commands
for
millisecond intervals.
It
to

introduce

Hex_adr

Hex_adr
to be

the
console
to
"Hex count"
number
is used in
command

stop
of 20
files

delays.

Hex_count

is the address of main memory where

transferred

to/from.

data

Hex_count is a 32-bit integer count of the number
of
bytes
to
. be
transferred.
Bit
31
implies
the
direction of the
data
transfer.
If
a
"1",
read
.
memory

10-13

CONSOLE

The

SOFTWARE AND COMMANDS

General

Command

Set

Example

10-6:

examples

X
100
FF
writes
FF
bytes
starting at location 100

2.,

X 100 B80000OOFF
location 100

This command
the
console
(write)
and
memory.

X command

reads

FF bytes

into

main

memory

from main memory at

is for automatic
communication
between
and
other systems.
It is used to load
unlcad
(read)
the
c¢ontents
o¢f
main

Refer

DEC

STD

032.

@ filename[.COM]
The @ (at) command causes command input to
be
taken
from
the file indicated by "filename".
The commands
may or may not be echoed on the
CTY
depending
upon
the
QUIET flag.
Outputs generated from the commands
are always displayed.
Command files may be nested up to four
1levels
deep,
but
at
that
level, no command can be executed that
specifies access to a file on the disk (such as
LOAD
filename).

10-14

CONSOLE

SOFTWARE

AND COMMANDS
MACRO

10.3

CONTEXT

MACRO CONTEXT

MACRO context is the default context after a
power-on
or
console
reboot.
MACRO context provides console commands to initialize the
machine

as a VAX processor.
operation
of
the
console,
while the console acts as an
and the EMM.

10.3.1
Whenever

MACRO Context
MACRO

performed.

MHC

also
allows
access
to
which
allows VAX macrocode
interface for both
console

PIO

mode
to be run
terminals

Initialization

context

entered

DIAGNOSTIC

MACRO

context

initialization

desired,

MACRO

|is

context

initialization may be aborted by the “C or “P characters.
If
the
initialization
is
in
response
to
a
power-on,
wait
until
"Initializing CPU" has been printed on the CTY before aborting
the
MACRO context initialization.
The RLO2 file "LOAD.COM" performs a complete
CPU for use as a macrocode processor.
Below
of the MACRO context initialization.
1.

RESET performs

a master

INIT/POWER initializes
operational.

reset

initialization of
the
is a brief description

the

ensures

system.

that

the power

system

fully

INIT/SDB forces all SDB control
to allow microcode loading.

Using

the

ULOAD.COM,

default

INIT/SDB
channels

Unconditionally

this

found

the

initialize
clear
on

cache

the

first

the

memory

Monitor

Console

control

known

state

stores

with

force

all

SDB

and perform an

UNJAM on

initialization

after

Microcode
program to

the

power-on

not active, or
contexts, then

and

if this is a
clear
main

(CLEAR MEMORY).

the

terminal

control

Support

Microcode

and

restart

control

do a warm start,

cold

(CSM),
a
microcode
communicate with the

switches

start,

(CSM)

E Many of the functions of MACRO context depend upon Console
'

control

system.

to
determine
whether
to
enter the CIO null loop.

10.3.2

PAMM.

the
Dbattery
backup
unit
was
context switch from DIAG or MHC

all

command is again executed
to a NOP or RUN state.

INIT/PAMM will

loads

system microcode.

adapters

INIT/MICRO

channels

package
which
CPU.
Part
of

Support

allows the console
CSM
microcode
is

contained
in
the normal EBox microcode.
CSM is also divided into
microcode overlays which are loaded into EBox control store by
the
console
1in
response
to typed commands.
The console and CPU pass
data packets over the CBus interface.

10-15

CONSOLE
MACRO

SOFTWARE

Context

10.3.3

COMMANDS
Set

MACRO Context

Table
of

AND

Command

10-6 lists
each command.

the

BOOT

Set

MACRO context

Table
BOOT

Command

10-6

commands

MACRO Context

[/switches]

"Switches"

brief

description

Commands

[device]

can

/R5:Hex_num

and

combination of:

specify value té place in R5,

default

/NOSTART

specify
start

"Device"”

1is

mnemonic,

such

a
as

that

the

boot

operating

command

file

not

system

one
to
three
character
device
DUO or CS1l.
This is appended with

"BOO.COM" to locate the boot
file,
as
DUOBOO.COM.
If
"Device"TM
1is
more
than three characters, it is
as a filename with the default extension .COM.
file is used to boot the operating system.
If
"device"
1is
not
specified,
DEFBOO.COM
is
the
default.

taken
This

CONTINUE

the

“P,

PIO

CPU

running,

CONTINUE will
mode.

but

has

cause

CPU

the

been

interrupted

transition
not

from CIO mode

running

then

the

CONTINUE
command performs an IBUFF FLUSH and forces
instruction execution to begin from the current PC.
CLEAR

MEMORY

CLEAR

[MEMORY]

memory,

is
DEPOSIT

The

first

determined

block

the

contiguous

contents

array

the

PAMM,

cleared.

DEPOSIT

[/space]

fhex

reg

adr,

"Space" can
default

[/next:Hex num]

name}l

any

Hex data

one

the

[/data_type]l

following.

The

/PHYSICAL.

/ESCRATCH

access

EBox

scratch pad

RAM

space

/GENERAT.

access

/INTERNAL

See Table 10-7
access VAX processor

/ PAMM
/PHYSICAL

access the PAMM RAMs
the default, access VAX physical

/U
/VIRTUAL

access T-11 RAM address space
access VAX virtual memory space
if
the
memory
mapping
1is
enabled,
otherwise

See

VAX processor GPR register space.

Table

IPR register

space.

10-8

memory

space

access

physical

address
"Data_type
/space

/BYTE
/LONG

can

access

be
is

bits

address

and

space

any one
for

of the
following
/PHYSICAL, /VIRTUAL, or

access a single byte of data
the default, access a longword
data

/WORD

access

a word

10-16

and

bytes)

ignore

31.

data

the

/U.

bytes)

;

CONSOLE

SOFTWARE

AND COMMANDS

MACRO Context

Command

Set

"Hex_adr" is the numeric address of the register
or
address
being
deposited.
Any
of
the
following
positional operators can
"hex_adr" relative to the

The default address

be
wused
to
represent
last address accessed

is set

to 0

Access last specified address

Access

the

address

following

the

INIT command.

last

specified

Access the address preceding the last

specified

address

specified

Use the contents of the last

the

address

to be

address

accessed

"Reg name" is a valid register name
for
GPRs
(see
Table
10-7),
IPRs
(see
Table
10-8),
Internal
Registers
registers

"Hex_data"

(IR, see
Table
10-9),
(see Table 10-10).

is the hexadecimal data to

into the specified address space.

miscellaneous

deposited

NOTE

To deposit to Tll
space,
the
address
and
data
must
be
preceded
by a "%0" (percent
Octal) to define the address/data
as
octal
instead of hexadecimal, the default.

Table

10-7

Supported GPR Names

Name

Access

G Address

RO
R1
R2
R3
R4

E/D
E/D
E/D
E/D
E/D

00
01
02
03
04

Processor
Processor
Processor
Processor
Processor

R5
R6
R7
R8
R9
R10
R11

E/D
E/D
E/D
E/D
E/D
E/D
E/D

05
06
07
08
09
0A
OB

Processor
Processor
Processor
Processor
Processor
Processor
Processor

FP
SP

E/D
E/D

0D
0E

Processor Frame
Processor Stack

E/D

0cC

Purpose

O
1
2
3
4

Processor Argument Pointer

Processor

10-17

Pointer
Pointer

CONSOLE SOFTWARE AND COMMANDS
MACRO Context Command Set
Table

10-8

Supported

Address

Purpose

IPR Names

Name

Access

KSp
ESP
SSP
Usp

E/D
E/D
E/D
E/D

E/D

00
01
02
03

POBR
POLR
P1BR
P1LR
SBR
SLR
PCBB
SCBB
IPL
ASTLVL
SIRR
SISR
ICCS
NICR
ICR
TODR
RXCS
RXDB
TXCS
TXDB
ACCS
MAPEN

E/D
E/D
E/D
E/D
E/D
E/D
E/D
E/D
E/D
E/D
D
E/D
E/D
D
E
E/D
E/D
E
E/D
D
E/D
E/D

08
09
0A
0B
0c
0D
10
11
12
13
14
15
18
19
1A
1B
20
21
22
23
28
38

PO Base Register
PO Length Register
Pl Base Register
Pl Length Register
System Base Register
System Limit Register
Process Control Block Base
System Control Block Base
Interrupt Priority Level
AST Level
Software Interrupt Request Register
Software Interrupt Summary Register
Interval Clock Control
Next Interval Count Register
Interval Count Register
Time of Day Register
Receive Transfer Control status
Receive Transfer Data Buffer
Transmit Transfer Control Status
Transmit transfer Data Butfer
Accelerator Status Register
Memory Management enable

TBIA
TBIS
PME

D
D
E/D
E/D

39
3A
3D

Translation Buffer Invalid All
Translation Buffer Invalid Single
Performance Monitor Enable

Performance

ISP

PMR

Kernel Stack Pointer
Exec Stack Pointer
Supervisor Stack Pointer
User Stack Pointer

Interrupt Stack Pointer

as
SID

Monitor

(same

PME)

System

PAMACC

E/D

Physical Array Map access

PAMLOC

E/D

Physical

CSWP
MDECC
MENA
MDCTL
MCCTL
MERG
CRBT
DFI
EHSR
STXCS

E/D
E/D
E/D
E/D
E/D
E/D
D
D
E/D
E/D

42
43
44
45
46
47
48
49
4A
4C

STXDB

E/D

Array Map Location
Cache Sweep
MBox Data ECC
MBox Error Enable
MBox Data Control
MBox MCC Ctrl
MBox Error generation
Console Reboot
Diagnostic Fault Insertion Register
Error Handling Status Register
Storage Transfer Exchange Control
Status

Storage
Buffer

10-18

Transfer

Exchange

Data

CONSOLE

SOFTWARE

MACRO

Table

10-9

Supported

Access

CPC

IBox

Current

CSHCTL

E/D

MBox

Cache

CSES

Control

CSLINT
EBCS

E/D
E/D

Console Interrupt status Register
EBox Control Status Register

EDMC

EBox

Diagnostic

EDPSR

EBox

Data

EMD

IBox

EMD

ESASAV

IBox

ESASAV

IBESR

IBOx

érror

ISASAV

IBox

ISASAV

Control

Store

path

status

(EBox)

Control

(from

EBox)

IBox

MBox

Error

Data

MBox

Error

address

MSTAT1

MBox

status

MSTAT2

MBox

Status

VIBASAV

IBox

VIBASAV

VPCBITS

Valid

IVASAV

Bits

Supported

Miscellaneous

Names

Purpose

IBGPR

IBox

PSL

E/D

Program

Status

SPADR
STATE

E/D

Scratch

Pad

E/D

STATE

EVMQSAV

VMQ

EXAMINE

10~10

Status

Maintenance

IVASAV

Error

MEAR

Access

Set

Purpose

MEDR

Table

COMMANDS

Command

IR Names

Name

AND

Context

GPR

save

EXAMINE

[/space]

{[hex_adr,

reg_name]}

"SPACE"
default

Longword

Address

[/next:Hex

can
be
any
is /PHYSICAL.

one

num]

the

/ESCRATCH

access

EBox

/GENERAL

access

VAX processor

See

/INTERNAL

access
See

/PAMM

/PHYSICAL

Table

the

following.

scratch pad

RAM

The

space.

GPR

space.

IPR

space.

10-7.

VAX processor

Table

access

[/data_type]

10-8.

the

PAMM

default,

RAMs.

access VAX physical

memory

space.

/U
/VIRTUAL

access

Tll

RAM address

access

VAX virtual

memory
mapping
access physical
address bits 30

space.

memory

space

is
enabled,
address space
and 31.

/Data_type can be any ONE of the
following
if
/space access is for /PHYSICAL, /VIRTUAL, or /U.
/BYTE

access

10-19

single

byte

data.

the

otherwise
and ignore

the

CONSOLE SOFTWARE AND COMMANDS
MACRO Context Command Set

/LONG

the
of

/WORD

default,

access

"Hex adr"

address

the

being

a word

Access

last

longword

bytes)

(4 bytes)

of data.

numeric address of

The default address
©

examined.

positional operators
"hex adr"
relative

access

data.

can
to

Any

be
the

used
last

the

set to 0 by the

specified

the

following

to
represent
a
address accessed.

INIT command.

address

Access the address following the last

specified

address

Access the address preceding the

last

specified

address

Use the contents of the
as

the

address

"Reg name"

is a valid

last

specified

address

accessed

for

GPRs

(See

Table
10-7),
Registers (IR,

IPRs
(See
Table
10-8),
Internal
See
Table
10-9),
or
miscellaneous

registers

Table

(See

10-10).

"Hex_data" is the hexadecimal data
into the specified address space.

deposited

NOTE

To examine Tl1ll space, the address
and
data
must
be
preceded by a "%0" (percent Octal)
to define the address/data as octal
instead
of hexadecimal, the default.
FIND

FIND

[/RPB,

/MEMORY]}

The default is
main
memory,

FIND/RPB,
starting

and this
command
searches
at
location
0, for a page
aligned 64K block of
good
physical
memory,
or
a
Restart Parameter Block (RPB).
If the item is found
its address plus 200 (hex) is
loaded
1into
the
&P
register.

HALT

Halt

is used to halt

CSM wait

the CPU by forcing

the

loop.

The Macro PC is displayed and the
CSM
status
code
should be 11 (hex).
If the CPU is already halted, a
message to this effect will be printed, followed
by
the last recorded Macro PC and CSM status.
INITIALIZE

INITIALIZE

[/switch]

"/Switch" may be none, or any one of the
following:
/CPU,
/ESCRATCH, /MICRQ, or /PAMM.
This command is
used

initialize

various

10-20

facets of

the CPU.

CONSOLE

INIT

Without

any
requirements

performed

INIT/CPU

switch,

Context

Command

this

command

meets
the
The
steps

DEC

ACCS

RX,

ASTLVL

ICCS,

and

(enabled

STX

set

FBox

registers

are

SISR,

MCCTL is set to 0O to enable
if the CPU clock is running

Turns

The

the

off

MAPEN,

the

VAX

IBUFF and

and

It
with the

Stop

Master

Loads

and

runs

bSets

EXTI

flags

are

set

MBox
overlaps
full speed

not

affected

with
performs
a

system
full CSM

loaded

combines
steps for

the
CSM
the INIT/ESC

command

does

the

clocks

reset

CSM040

and

CSM041

overlays

Performs

INIT/ESCRATCH

Performs

INIT

This

command

pad

on)

lamp

The

following:

initialized

system cache are

commands.

CPU

PME

STATE

EBox
has
been
microcode,
this
command

INIT

flag

Set

and

co—

032.

initialization.
initialization

INIT/ESCRATCH

STD

include:

SOFTWARE AND COMMANDS

MACRO

uses CSM to
registers
with the

load

the

values

EBox

needed

scratch
to

start

the CPU.
Data is taken from ECODE.BPN,
unless
the
filename
is
specified
as
INIT/ESC
"filename.BPN".
This file will initialize GPRs

INIT/MICRO

INIT/PAMM

SP.

This

command will check KA86n.REV (n
=
0
for
8600
and
5
for
8650) the microcode revision
information.
It will then execute ULOAD.COM to
load
the
system
microcode
according
to the
loaded microcode revision.

This

command

memory

system

determines

and

the

and

After

"“M

e
—

an ABus INIT the
registers
are
loaded

megabytes

CYCLES
SBIA

the amount of

number

and

CONTROL

10-21

physical

adapters

on the
accordingly.

configuration

CYCLES

STATUS

PAMM

the

physical

SBI

IO adapter

configures

with
memory

OUT

the

number

present,

are

set

and

SBI

the

CONSOLE SOFTWARE AND COMMANDS
MACRO Context Command Set
LOAD

LOAD

[/start:hex_adr]

filename[.exe]

This command is used to load main memory with binary
data
taken
from the specified file.
If the /start
switch is used then the data is loaded
starting
at
the
specified
"hex_ adr",
otherwise,
the
data is
loaded starting at location zero.
START

START

[hex address]

This command is the same as a "CONTINUE" except that
if
a
"hex_address" is specified, it is used as
current PC at which to start the VAX processor.

the CPU is already running,

START/STEP

re~enters

PIO mode

CPU,

even

START/STEP

without

"hex_address"

the
If

then this command simply
affecting

the

running

included.

[hex address]

This command prepares
the
CPU
for
micro-stepping
macro
instructions.
It
loads a CSM overlay, sets
the PC if specified, and starts the CSM
idle
1loop.
The
HEX commands may then be enabled to MIC or TMIC

through the macro instructions.

When stepping is completed, the UNHANG
command
may
be
wused
to
reset the EBox to the start of the CSM
idle
1loop
without
affecting
the
state
of
the
machine.
NEXT

[Hex_count]

This command single
steps
the
VAX
processor
specified
number
of
macro
1instructions,
or
default of
one
if
no
count
is
given.
At
completion
of
the
full
step count, the PC of
next macro instruction is displayed and the
enters
space-bar-step-mode,
indicated
by
prompt at
the
end
of
the
1line
1instead
beginning

the

the
the
the
the

command
the >>>
of
the

line.

UNJAM

UNJAM [IOAO, IOAl, IOA2, IOA3]
,
An UNJAM sequence is generated by the SBIA selected.
SBI0 or SBIl may be used instead of IOAO or IOAl.

VERIFY

[/switch]

Switch is any of
the
following
values:
/CONTEXT,
/CYCLE,
/ECS,
/FBACS,
/FBMCS,
/I1Cs,

/IDRAM,

/MCF,

/MCS,

/ACCESS,
/FDRAM,

or /PAMM.

The contents of the selected CS/RAM is
verified
by
comparing
the
data
read
from the CS/RAM with the
contents of the .BPN file used to load
it.
If
no
switch
1is used, all the control stores and RAMs are
verified.
This

command

will

display

the

total

number

discrepancies if the HEX debugger command sel is nof
enabled.

HEX

1is

enabled,

reported with good/bad data.

10-22

each

failure

is*

CONSOLE

SOFTWARE

AND COMMANDS
HEX DEBUGGER

THE

10.4

THE

This
HEX,

which

HEX DEBUGGER

section discusses the hardware debug and
can be enabled frum either MACRO or

The

HEX commands

the

state

The

HEX command

the

allow
CPU.

set

the

operator

enabled

the

trace
facility,
or
DIAGNOSTIC contexts.

modify

"DEBUG"

and/or

console

command,
and
(>) to the end of
>>>> and the DIAG

is indicated by the addition of one angle bracket
the current prompt.
The MACRO prompt will become
prompt will become DC>>.

10.4.1

The

Table

10-11
description

HEX Command

Set

contains
of each.

1list

Table
CLEAR

BREAK

10-11

CLEAR

the

The

HEX Command

{ABREAK,

HEX

OBREAK!

interrogate

commands

and

brief

Hex

ID,

All}

Set

{Symbol,

Regq,

"Symbol is a V$XXXX visibility symbol name,
"Reg"
is
a
wvisibility
register
name,
"Hex ID"
is a
16-bit hexadecimal ID number (see EXAMINE/SDB) and
"A1l"
will
remove
all
breakpoints
from
the
specified table.
This

command removes the specified breakpoint from
the appropriate table.
If "All" is specified, all
of the breakpoints in that table are cleared.

Example

CLEAR COUNT

10-7:

>>>>CLEAR ABREAK

V$Al1l23

>>>>CLEAR OBREAK

ALL

This

command
keeps

(micro or

(CS)

BREAK

counter

DEPOSIT

CLEAR

state)

was

cleared.

you

enter

DEPOSIT

clears

the

step

the

number

since

the

last

time

counter

will

also

track
This

TSTATE

from

TMIC

[/NEXT:Hex_num]

counter.

vice

{/Switch]

This

machine

the
be

stcps

counter

cleared

versa.
Hex_adr

Hex data

"/Switch"
/CONTEXT,
/ICS,

can be any of the
following:
/ACCESS,
/CYCLE,
/ECS,
/FBACS, /FBMCS, /FDRAM,
/IDRAM, /MCF, or /MCS

"Hex_adr" can be a hexadecimal number
or
one
following
specifiers
that
determines

the

Seomgp

address

relative

the

last

Access

last

Access

address

followed

address

preceding

specified

of
the

address.

specified address
by

the

last

specified

last

specified

address
-

Access
address

10-23

the

CONSQOLE SOFTWARE AND COMMANDS
The HEX Command Set

"Hex_data" is any hexadecimal
range limits of the specified

number
control

within
the
store or RAM

This command allows the
operator
to
modify
the
contents
of control store or RAM locations in the
VAX 86XX CPU.
The /NEXT switch
<can
be
wused
1in
combination
with
any
other
switch
to
perform
successive
deposits
of
the
same
data
into
consecutive locations.
NOTE

The MCS, ACCESS, and
CYCLE
RAMs
can
deposited only if the system is out of

reset state.
This will
be
true
command "MICROSTEP 3" is executed.

Example

10-8:

location

;Deposit

EBCS

;Deposit O

>>>>DEPOSIT/CYCLE * OFA ;Deposit
presently addressed CPR location

FBA
- FBM
- IBD
- ICA
- EDP

ACCESS

the

OFA into

the

Hex_data

"Hex channel" is one of the
according to Table 10-12.
Table

into

locations

DEPOSIT/CHANNEL Hex channel

00
02
03
05
08

>>>>DEPOSIT/ECS/NEXT:10 0 O
first

DEPOSIT/CHANNEL

DEPOSIT

>>>>DEPOSIT/ACCESS 0 0
RAM

be
the
the

10-12

SDB

0A
0D

- MCC
- EBC

- CSB

SDB

channel

Control

Channels

numbers

EBE

VBA

"Hex_data" is a 16-bit
hexadecimal
deposited into the selected control

value
to
channel.

This command deposits the specified data inte
the
selected
SDB
control
channel.
Control channels
vary in length, so if the data exceeds the
length

the

channel,

the

shifted out of the
bit bucket.
Table
bit positions.

Table

10-13

high

order

control channel
10-13 lists the

Control Channel

Channel

Rit

Signal

MSQ4 SBDADR 0

01
02
03
04

MSQ4
MSQ4
MSQ4

SBDADR
SBDADR
SBDADR

1
2
3

L
L
L

MSQ4

SBDADR

(FBA)

10-24

Name

bits

will be

and
into
the
contreol channel

Bit Positions

CONSOLE

SOFTWARE

The

(FBM)

05
06
07
08
09

MSQ4 SBDADR 5
MSQ4 SBDADR 6
MSQ4 SBDADR 7
MSQ4 SBDADR 8
MSQ4 SDBCTL 0

MSQ4

SDBCTL

MSQ4

SDBCTL

00
01

FM02
FM02
FM02

SDB
SDB

(IBD)

(1ICA)

(EDP)

FDR A4
FDR A5
FDR A6

H
H

FMQ02

SDB

FDR

FM02

SDB

FM0O2

SDB

FDR A8
FDR A9

00
01

IBDH

SDB

DAOO

TBRDH

SDE

DAQl

02
03
04

IBDH SDBR
IBDH SDB
IBDH SDB

DAQO2
DAQO3
DAQO4

H
H
H

TRDH

SDB

DAQOS

06
07
08
09

IBDH SDB
IBDH SDB
IBDH SDB
IBDH SDB

DAO6
DAO7
DAO8
DAQ9

H
H
H
H

10
11
12
13
14

IBDH SDB
IBDH SDB
IBDH SDB
IBDH SDB
IBDH SDB

IBDH

SDB

ICA]l

ICS

CNTRL CHNL

01
02

ICAl1
ICAl

ICS
ICS

1
2

ICA1l

ICS

CNTRL CHNL
CNTRL CHNL
CNTRL CHNL

EDPI

DISA BYTE

PAR

01
02
03
04

EDPI

DISA

PAR

EDPI
EDPI
EDPI

FLIP WREG PAR H
DISA SCE AR BUS
DISA ALU AR BUS

07
(EBE)

L
L
L
L
L

05
06

SDB

HEX

DA10

DAll

DAlZ2
DAl13

DAl4

H
H
H

DA1lS5

BYTE

-EDPI

FLIP GPRA H
-EDPI FLIP GPRB H
EDPI SPARE 0 H

EBEH

DOO

01
02
03
04

EBEH SDB CTL D01
EBEH SDB CTL D02
EBEH SDB CTL D03
EBEH SDB CTL D04

H
H
H

05
06
07

EBEH SDB CTL D05
EBEH SDB CTL D06
EBEH SDB CTL DO7

H
H
H

EBEH

SDB

CTL

D08

EBEH

SDB

CTL

D09

10-25

SDB

CTL

H
H

AND

COMMANDS

Command

Set

CONSOLE

SOFTWARE AND COMMANDS

The HEX Command Set
OA

DEPOSIT/CSPE

(MCC)

(EBC)

00
01

MCCA LOAD ENA H
MCCA WRITE MICRO A L

Unused

MCCA SHIFT ENA H

MCCA WRITE MICRO B

05
06
07

Unused
MCCB DIAG INTR H
MCCB WRITE VIOL L

08
09

Unused
MCCB DIAG RAM WRITE

10
11

MCCB CPR WRITE
Unused

00
01
02
03
04

EBCl1 SDB CTL DOO H
EBC1 SDB CTL DOl H
EBC1 SDB CTL D02 H
EBC1 SDB CTL D03 H
EBCl1 SDB CTL D04 H

05
06
07
08
09

EBC1
EBC1
EBC1
EBC1
EBC1

10
11
12
13
14

EBC1 SDB CTL D10 H
EBC1 sDB CTL D11 H
EBC1 SDB CTL D12 H
EBC1 SDB CTL D13 H
EBC1 SDB CTL D14 H

EBC1 SDB CTL D15 H

SDB
SDB
SDB
SDB
SDB

CTL
CTL
CTL
CTL
CTL

D05
D06
D07
D08
D09

H
H
H
H
H

(CsB)

00
01
02
03

CSBR CNSL OPl FLAG H
CSBR CNSL OP2 FLAG H
CSBR LOAD DIAG CNTR H
-CSBR FLIP USTK PAR H

(vBA)

VB06 CLK CNTRL

DATA

01
02
03
04

VB06
VB06
VB06
VB06

CLK
CLK
CLK
CLK

CNTRL
CNTRL
CNTRL
CNTRL

DATA 1 H
DATA 2 H
DATA 3 H
DATA 4 H

05
06
07
08
09

VB06
VB06
VB06
VB06
VB06

CLK
CLK
CLK
CLK
CLK

CNTRL
CNTRL
CNTRL
CNTRL
CNTRL

DATA 5 H
DATA 6 H
DATA 7 H
8 H
9 H

10
11

VB06 CLK CNTRL 10 H
VB06 CLK REG LD ENA H

DEPOSIT/CSPE

[/Switch}

[/Nofile]

"Switch" can

/FBACS,

/FBMCS,

any

/ICS,

10-26

/MCS,

the

Hex_adr

following:

/IDRAM,

or FDRAM

/ECS,
%

CONSOLE

SOFTWARE

The

"Hex_adr"
selected

hexadecimal
address
stores address range.

control

This command allows
a

control

data

the

operator

AND

HEX

COMMANDS
Command Set

within

the

to re-deposit

store

1location
with bad parity.
The
from the .BPN file used to load
the
store, and modified to contain bad parity
bit(s)
are
flipped).
If
the
/Nofile

taken

control

(parity
switch
1is
specified,
but the actual data in

the .BPN file is
the RAM is used.

not

used,

Correct

parity can be restored by either reloading
the
entire control store (LOAD/ECS
for instance),
or by using the DEPOSIT command with the
original
control

store

DEPOSIT/MARK

the

data

Example

DEPOSIT/MARK

data.

the

and

For

the

EBox,

command

can

correct

10-9:

DEPOSIT

100D

>>>>DEPOSIT/CSPE/MCS

DEPOSIT/MARK

[/Switch}

"Switch"

can

either /ECS,

"Hexadr"

hexadecimal

bounds

the

selected

mark
location.

set

control
used

Hex_ adr

/ICS,

address

control

{On,

Off]}]

/MCS

within

the

store.

allows the operator to set
or
clear
bit
in
the
selected
control
store
On/Off determines whether the mark
bit

cleared.

store

switch

the

[/Nofile]

command

the

MBox,

restore

CSPE

>>>>DEPOSIT/CSPE/ECS

This

and

parity.

IBox,

used

load

The

location
the

used.

data deposited

taken

from

control

store

unless

Correct

parity

the

to the

.BPN

the

tile

/Nofile

is maintained.

the SOMM flag (Stop On Micro Mark) is
set
for
selected control store, the CPU clock will be

stopped

when

set

mark

bit

encountered.

When

running at full system clock speed, the
SOMM
flag
need not be cleared because the CPU clock is
actually
stopped
beyond
the
selected
micro-instruction.
But, if the system clock is at

1/5
the

speed, the CPU clock will be
selected micro-instruction.
TSTATE

will

not

stopped right
at
Attempts to TMIC

succeed

because

micro-instruction
being executed
has the mark
set.
Clearing
the
SOMM
flag
will
allow
micro-instructions to be stepped.

Example

10-~10:

DEPOSIT MARK

>>>>DEPOSIT/MARK/ECS

100D ON

>>>>DEPOSIT/MARK/ECS

100D OFF

10-27

the

bit
the

CONSOLE SOFTWARE AND COMMANDS
The

HEX

EXAMINE

Command

(CS)

Set

EXAMINE

[/Next:Hex num]

{/switch]

hex_adr

"Switch" can be any of
the
following:
/ACCESS,
/CONTEXT,
/CYCLE,
/ECS,
/FBACS, /FBMCS, /FDRAM,
/I1Cs, /1IDRAM, /MCF, and /MCS.
“Bex_adr“ can be a hexadecimal number or
to the last specified address as follows:
last

specified

relative

Access

Access
address
following
last
specified
address.
If "Hex_adr" is not specified, + is

address.

assumed.

Access

address

preceding

last

specified

address.

This c¢ommand allows the operator
to
examine
the
contents
of
the
selected
control
store at the
specified address, or an address relative
to
the
last
specified
address.
The
MCS,
ACCESS, and
CYCLE RAMs can only be examined if the
system
Iis
out of the reset state.
The command "MICROSTEP 3"
can be used to ensure that this is true.

NOTE

The EXAM/MCS command
performs
a
special
function
when the address is out of range
of
the
MBox
control
store
addresses
(greater
than FF).
The command will read
the
state
of
the
MCC
shift
path
and
convert
it to .ULD format (UCODE.ULD) and
display
the
result.
This
allows
the
operator
to
inspect
the data in the MCC

'shift path that has caused an MBox

parity

error.

Example

EXAMINE

CONTROL

STORE

>>>>EXAMINE/ECS/NEXT:10

;Examine

ECS

location

locations,

>>>>EXAMINE/ECS

starting

;Examine

ECS

(hex)

following

last

"Hex_channelTM is
the
SDB
channel
number.
Table 10-14 for the SDB channel numbers.

See

ECS

EXAMINE/CHANNEL

10-11:

access

EXAMINE/CHANNEL Hex channel

10-28

CONSOLE

pu—

:.\“‘wf /

Table

00
03
06
09
0C
OF
12
15

=
-

10-14

FBA
IBD
ICB
EBE
EBD
CSA
1I0A2
RESERVED

SDB

01
04
07
0A
0D
10
13
16

SOFTWARE AND COMMANDS
The HEX Command Set

Channel

FBM
IDP
CLK
MCC
EBC
I0A0Q
IOA3
RESERVED

Numbers

02
05
08
OB
OE
11
14
17

MCD
ICA
EDP
MAP
CSB
1I0Al
MTM
RESERVED

NOTE

The MTM visibility channel
would
have
a
"K"
in
the V$ symbol, as V$K123, whereas
channels 00 through OF would have 0 - F.

This command will display all visibility
bits
in
the
specified SDB channel.
The data is displayed
as a string of hexadecimal characters followed
by
a
three
character
checksum.
The
number
of
characters displayed is:

FBA/FBM

characters.

The

FBox

shift

channels
are
12
bits
in
1length.
There are 24 shifts
which
provides
288 bits.

IDP/IBD/ICB

64 characters.
The IBox shift paths
are
8 bits in length, and there are
32 shifts which provides 256 bits.

\
J

ALL OTHERS

characters.

The

rest

the

shift
paths
are also 8 bits.
With
24 shifts each,
this
provides
192
bits.

Example

EXAMINE/SDB

10-12:

EXAMINE/CHANNEL

>>>>EXAMINE/CHAN

>>»>>EXAMINE/CHAN

EXAMINE/SDB

{Symbol name,

Register_name,

Hex_ID,

"Signal name"}

"Symbol name" is the V$
symbol
assigned
to
the
particular visibility signal by the SDB CAD (.CDF)
files.

"Register name"

the

name

default

visibility
register
or
a
visibility
register
defined within HEX by the TRACE DEFINE command.
A
visibility
register
is
a
group
of
VTERM bits
joined together in a logical
arrangement.
Table
10-15

contains

registers.

the

See

names

also

the

the TRACE

default

visibility

DEFINE command.

list
of the default visibility registers wouldn't
be complete without the contents of
each
of
the
registers.
See Table 10-16.
Table 10-16 will be
located

the

end

length.

10-29

this

section

due

its

CONSOLE SOFTWARE AND COMMANDS
The HEX Command Set

Table

10-15

Names

Default

Visibility

Registers

ABUS
DBUS
EMCF
FABUS
IBUF
IOPSEL
MDBUSM
OPAR
OPPORT
PARITY

ARADR
EBFLSH
ESTALL
FAUPC
IBXERR
IUPC
MEMREQ
OPBUS
PAACK
PSL

UPCSAV

WBUS

ARBUS
EDPPE
LUPC
FMUPC
IDIAG
IVABUS
MUPC
OPCODE
PAMD
REGBUS

ARYDBUS
EFORK
EVABUS
IBDBUF
INCR
MDBUSI
NATRAM
OPMCF
PAMM
STALL

"Hex_ID" is a 16-bit SDB or register ID.
SDB_ID's
are
hardware
visibility-bit
addresses
and
are
defined
in
the
.CDF
files.
REG_IDs
are
software-defined
numerical
tags
for
visibility
registers.

"Signal name” is the full visibility signal
including the High/Low specified.

name,

NOTE

The signal name must be enclosed in quotes
("signal
name").
Also, the .CDF files do
not contain any LOW signal names i.e., the
signal
"THIS SIGNAL L" would be listed as
"-THIS SIGNAL H".

This command displays the
single visibility signal,
a visibility
Example

name

and

state

or the name and state of

10-13:

EXAMINE/SDB

>>>>EXAMINE/SDB V$A123

:Use symbol

>>>>EXAMINE/SDB WBUS

:Use register name

>>>>EXAMINE/SDB

;Use

D>>>>EXAMINE/SDB 800B

EXIT

This

MICROSTEP

command disables

SDR

name

;Use register ID

the HEX command

set.

[Hex_ number]

"Hex_number" is a hexadecimal step
range of 1 to 100.
The default is

count
1.

the

The
MICROSTEP
command
causes
"Hex number”
of
microinstructions
to
be
executed at full system
clock speed.
Before
stepping
begins,
the
CPU
clock
is
forced to T3 state.
CPU clocks must be
stopped for this command to function.
|

The
execution
of
a
MICROSTEP
command
invokes
space-bar-step-mode
(SBSM), which is indicated by
In
prompts.
SBSMDC>>
or
SBSM>>
the
space-bar-step-mode, the next step can be executed
by depressing the space-bar.
10-30

CONSOLE

SOFTWARE AND COMMANDS
The HEX Command Set

SBSM remains in effect until any
the space-bar is depressed.
After

stepping

has

finished,

key

all

other

than

UPC's

are

displayed.
REPORT

The REPORT command will display all default
trace
visibility
register
data.
REPORT is invoked on
completion of

any TMICRO or TSTATE.

The trace reported
assumes
that
all
visibility
registers
are
48
bits in length.
If a register
greater than 48 bits in length
is
added
to
the
trace
1list,
the
display will be truncated to 48
bits.
A "T" will
precede
the
register
in
the
trace

list to

indicate

the

truncation.

Any
register
or
signal
value
whose
value
is
different
from
that
observed
on
the
previous

SET

BREAK

SET

the

(*)

asterisk

report will be prefixed with an

denote

change.

OBREAK!

{ABREAK,

[Symbol,

[Span,

Hex”IDZ

Reg,

Value:vall

"Symbol"

assigned

from the

VSXXXX
.CDF

symbol

visibility

file.

name

"Reg" is the name of a visibility register defined
within HEX or by the TRACE DEFINE command.
l16-bit SDB or register ID.
vigsibility-bit
addresses
are
REG_IDs
defined in the .CDF files.
defined for visibility registers.
"Hex ID" is a
are hardware

“"Value:val"

"Span"” and

parameters.

Up to 4 breakpoints
ABREAK).
(OBREAK,

optional

are

SDB_IDs
and
are

software

breakpcint

set
in
each
table
register
or
signal
will
wuser
specified is already in the table, the

be
asked
that table

can
be
the
If

if
he wants
If
entry.

to alter the parameters of
are
parameters
new
so,

accepted.

The TMICRO or TSTATE commands will stop and report
the
current
machine
state
only
when
a
break

condition is met, when all of the "AND" conditions
are true, or any of the "OR" conditions are true.
The

that

what

The

"SPAN"

option causes a

signal

break

condition

when

or register is in a state other than

it was when

the

trace was

"Value:val" option causes

when
that signal
specified (1 or 0).

1is
option
neither
If
break
a
and
implied,

selected signal

10-31

started.

break

equals

condition
the value

is
"Change"
selected,
will occur every time the

CONSOLE

SOFTWARE

The

Command

HEX

AND COMMANDS

Set
Example

10-14:

SET

>>>>SET ABREAK

BREAK

V$123

changes
2.

SET

HISTORY

V$456

VAL:1

>>>>SET OBREAK WBUS SPAN
different than it is now

For

use

SET MARGIN
Alll]

This

engineering

during

{High,

Normal}

command

output

;Break

when

V$456

:Break

microcode.
SET MARGIN

V$123

when

>>>>SET ABREAK

equals

;Break

level

Low,

allows

the

power

the

WBus

development

[{A,

operator
supplies

DE,

FH,

adjust

the

for

purposes

of
marginal faults.
Margins can be set +5%
or
-5% (Low).
The outputs of the D and E
regulators and the F and
H
regulators
are
tied
together
so
these
regulators
must
be margined
together (DE, FH).

detecting

(High)

The

regulator

the

SHOW BREAK

This

command

ORREAK

SHOW

DEFINE

"Reg_name"

defined
See

shows

the

are

visibility
This

HEX or

for

the

ABREAK

ID,

namc;,

for

each

are

shown

a
the

visibility
TRACE DEFINE

1list

the

16-bit

SDB or Register 1ID.
visibility-bit
addresses
.CDF files.

software

defined

registers.

command

displays

Hex*IDI

name

registers.

conditions

10-15

are
hardware
defined in the
REG_IDs

contents
signal

{Reg“name,

within

visibility

the
The

break

Table

"Hex_ID"

to bec margined are specified
argument (A, B, C, DE, FH).
If no
specified, the default is "ALL".

tables.

and optional
table entry.

SHOW DEFINE

outputs

second

regulator

numerical

SDB_1IDs
and

are

tags

for

1list
of
all
visibility
used
to
construct
the
visibility register.
The display is
oriented
in
descending order (high order to low order, left to
right) with 12 (decimal) terms per line.
The last
four
characters
of
each VSNNNN (NNNN) symbol is
shown.
symbol

names

(VSNNNN)

10-32

CONSOLE

Example

SOFTWARE AND COMMANDS
The HEX Command Set

SHOW DEFINE

10-15:

>>>>SHOW DEFINE REGNAM

NNNN

REGNAM

13.

VSNNNN,
of

this
1001

2002

3003

4004

5005 6006 7007 8008
9009 1010 1111 1212
1313

SHOW HISTORY

SHOW

HISTORY

Name,

VTERMs

and number

that make

The symbols for the 13
VTERMs in this
register (VS$SNNNN)

[/Output:filename[.DAT]]

[Hex num]

[Hex_ num]

The behavior of this command is
unpredictable
if
the optional history module is not in place in the
system.
It is designed to be
wused
by
engineers
during the development of microcode.

SHOW NAME

SHOW
NAME
{Symbol name,
"Signal name"}

Reg name,

Hex_ ID,

"Symbolname" is the name of a visibility register
defined within HEX or by the TRACE DEFINE command.
See Table 10-16 on Page 38 for a list
of
default
visibility registers with bit definitions.
"Hex ID" is a 16-bit SDB or Register ID.
are
hardware
visibility-bit
addresses
defined in the .CDF files.
Reg IDs
are

SDB
1IDs
and
are
software

defined numerical tags for visibility registers.

"Signalname" is the full visibility signal
name,
including
the
"HIGH"
or
"LOW"
spec1fled.
The

signal name must be enclosed
name

quotes

("signal

name,

L").

This command looks up the

symbol

name,
1D,
or
signal
name
and
prints
the
corresponding V$ symbol, signal/register name
and
ID.
If displaying a register, the size (number of

VTERMs)

is also displayed.

Example

10-16:

>>>>SHOW NAME V$5163
5145
V$5163
IBD DRAM LAST H

Symbol name

>>>>SHOW NAME STALL

802C

STALL

29.

>>>>SHOW NAME 8000
8000

SHOW NAME

LUPC

13.

>>>>SHOW NAME "IBD DRAM LAST H"
5145
V$5163 IBD DRAM LAST H

10-33

Signal name

CONSOLE SOFTWARE AND COMMANDS
The HEX Command Set
SHOW REGISTER

This command displays a
1list
of
all
visibility
registers currently defined, whether within HEX or
the TRACE DEFINE command.
The display includes
each register'’'s ID_number, name, and size.
by

NOTE

A validity check is done
before it is displayed.
a register is found, the

on each
register
If a bad entry in
name
"~badreg-"
is
assigned
to the register.
Because of
the bad register definition, there
1is
no
way
for the code to display the true name
o0f the register.

SHOW TRACE

STATESTEP

This command displays a list of all registers
and
signals currently selected for tracing.
The trace
list may be changed by the user
using
the
TRACE

ADD

command.

also

included.

STATESTEP

The

current

breakpoint

The STATESTEP command
to be executed.
STATESTEP

count

MICROSTEP.

The

causes

count in the
is 1 step.

"Hex_num"

of
4
1is
micro-pc's

shown for STATESTEP.
full machine speed.

cause

SBSMDC>>

the

Statesteps

are

depressing the
character).

TSTATE

TMICRO

specified,
These

(TMIC),
a

for

the

TSTATE

then

initialize

clock

steps

1 clock phase for
trace
breakpoint

any

stops,

step

the
(1

trace
and

settings

invokes
by the
user

can

executed

trace

not

facility

and

cycle

for

TMICRO

of the
machine
accordance with

is
the

SHOW TRACE).

are

report

a brake condition is met.

TSTATE)
while
watching
condition, or until the

(see

breakpoints
the

given,
and
defined,
then
until either a
detected.

the

count.

trace

clock

expires.
The state
captured and reported in

trace

at:

[Hexhnum]

the default is 1.

CPU

executed

STATESTEP per
space
in
effect
until
a
space-bar is depressed.

a hexadecimal

count

current

commands

execute

step

steps

than

[Hexgnum};

"Hex num"”

one

not

space-bar (one
SBSM
remains

character other
TMICRO,

SBSM,

ticks

command

range

are

boxes

indicated

prompts.

additional

clock

equivalent

The execution of
the
STATESTEP
space-bar-step-mode
(SBSM)
as
SBSM>>

are

[Hex num]

"Hex num" is a hexadecimal step
of 1 to 400 (hex).
The default

options

set,

trace

generated,

stepping
as

soon

step count

trace
breakpoint
conditions
are
stepping
continues
indefinitely
breakpoint or “C input character is

10-34

CONSOLE

When

breakpoint

expires,

HEX enters

SOFTWARE

AND

COMMANDS

The

HEX

Command

the

step

detected,

SBSM.

Set

count

NOTE

If QUIET is ON, no
trace
information
is
displayed
until
the final trace step has
completed;

information

TMIC

1is

equivalent

REPORT.

TSTATE

followed
TRACE

ADD

QUIET

item

Item

any

1is

OFF,

for

then

each

MICROSTEP

trace

step.

followed

equivalent

STATESTEP

report.

TRACE ADD

registers
signals to

1is

is displayed

combination

to
the

the
trace
1list)
trace list).

"Regname"

(add

VSNNNN

This command is used to customize the register and
signal
trace lists (see SHOW TRACE).
The list of
items to add is included in the command
1line
and
may
specify
as
many
items
as
will fit on the
remainder

required.

available
Example

TRACE

DEFINE

that

Use

1line.

The

SHOW REGISTER

VS$

prefix

command

display

registers.

10-17:

>>>>TRACE

TRACE

DEFINE

TRACE

ADD

LUPC

USRREG

PARITY V$1001

V$2345

Reg name

"Reg name" is a unique name to be assigned to
the
new "user-defined" register.
Name strings must be
6 characters
or
1less
in
length,
and
will
be
truncated

characters

are

characters

names

than

entered.

This
command
1is
used
to
define
visibility
registers
1in
addition
to
those already defined
(See Table 10-15).
The command will check to
see
if the new name is not already defined and if not,
will prompt the user to enter a list of V$
symbol
last

four

characters

character VSNNNN (NNNN)
the
signals
beginning

names.

Only

the

need
with

be
the

Signals must be
but not both.

separated

with

the

six

entered.
Enter
most significant.

space

or a

comma,

Signal names may be continued
on
the
next
1line
with
a
CR
(Carriage
Return)
at the end of the
line.
Terminate the definition with an additional
carriage
return.
HEX
will
display
the
verification.
Note
in
the
example
NNNN,
the
register
number,
NEWREG,
(truncated to 6 characters),
signals
1in the register.
A
TRACE DEFINE is added to the
(SHOW TRACE).

10-35

the
register
name
and n, the number
of
register defined with
default

trace

1list

CONSOLE
The HEX

SOFTWARE AND
Command Set

COMMANDS

Example

10-18:

>>>>TRACE

TRACE

DEFINE

Enter V$ terms
1001 2002 3003
9009

1010

1111

DEFINE

newregister

separated with
4004 5005 6006

<SP>
7007

or <,>
8008<CR>

1212

1515

1616<CR>

1313

1414

<CR>
NNNN

TRACE

DELETE

TRACE

NEWREG

DELETE

Reg

name

This command will delete a user defined visibility
register established by TRACE DEFINE.
The command
will
ask
for
confirmation
before
taking
any
action.
If
the delete request is confirmed, the
named

and

removed

REMOVE).
may

not

the

trace

default

list

list
(TRACE

list

TRACE

DELETE

>>>>TRACE

TRACE

DELETE newreg
register NEWREG =--

Reg

name

VSNNNN

any of

the

following:

Remove

all

registers

signals

from the

Remove

all

Remove

named

registers

Remove

named

signal

This

command
signal trace
be

(Y/N)

Item

can be

confirm

response

REMOVE

"Item"

from

deleted.

;Confirm

REMOVE

the

10~-19:

Delete

TRACE

removed

Registers
be

Example

from

is used
list by

removed.

The

from

list

the

list

from

the

from

the

list

to customize the register and
allowing unwanted information
list

items

remove

included
in
the
command line and may specify as
many items (separated by a space) as will
fit
on
the remainder of the line.
The V$ is required for
signal names.
A default
register
will
just
be
removed

RESTORE

the

from

Example

10-20:

1.
TRACE

from

removed

This

list

and

>>>>TRACE

the

Lrace

TRACE

REMOVE

1list,

will

not

list.

REMOVE

V$1234

V$4567

NEWREG

command

is used to restore the default
trace
(including
all default visibility registers

signals)

and

zero all

10-36

counters

and

variables.

CONSOLE SOFTWARE AND COMMANDS
Default Visibility Registers

10.4.2

Default Visibility Registers

The HEX debugger
command
set
provides
access
(o
a
number
of
for tracing the machine
useful
registers
pre-defined visibility
state.
Most of these registers are part of the default TRACE
list
The TRACE ADD
TSTATE, and REPORT commands.
TMICRO,
the
by
used
command can be used to add a register to the TRACE list.
The TRACE
DEFINE
command
can be
used to define a new visibility register.
Table 10-15 lists the visibility registers present in

the

console

program.

Just the name of the register is not enough when trying to decipher
a
TMIC,
or
any
trace;
a
bit
breakdown
of
the
registers is
necessary.
Table 10-16 is a complete list of visibility
registers
and
the signal names that make them up.
Note that bits are listed
in order of the MOST-SIGNIFICANT BIT
FIRST.
The
special
filler
symbol
'XXXX'
is
used
to
O-pad a visibility register in places
where signals are no longer defined or where
nibble
alignment
is
desired.
Visibility register definition can be found in the source
listing for the HEXBOX module

Table 10-16

(HEXBOXT11.LST).

Default Visibility Registers

ABUS

V$ symbol

Bit

Nibble

Signal name

VSA223
VSA225
VSA215
VSA217

43
42
41
40

SB
SB
SB
SB

VSA130
V$SA226
VS$SA220

39
38

ABUS CPU BUF DONE H
ABUS CPU BUF ERROR H

VSA222

37
36

VvSaZll
VSA214
VSA219
VSA210

35
34
33
32

ABUS
ABUS
ABUS
ABUS

CMD
CMD
CMD
CMD

vV$B195
V$B203
V$B139
V$B128

31
30
29
28

ABUS
ABUS
ABUS
ABUS

DATA
DATA
DATA
DATA

ADDRS
ADDRS
ADDRS
ADDRS

V$B199
VSB197
V$B198
vV$B183

27
26
25
24

ABUS
ABUS
ABUS
ABUS

DATA
DATA
DATA
DATA

ADDRS 27 H
ADDRS 26 H
ADDRS 25 H
ADDRS 24 H

v$B200
VSB130
V$B204
V$B131

23
22
21

ABUS
ABUS
ABUS
ABUS

DATA ADDRS
DATA ADDRS
DATA ADDRS

vV$B189
VSB135
vV$SB138
V$SB136

19
18
17
16

ABUS
ABUS
ABUS
ABUS

DATA
DATA
DATA
DATA

ABUS
ABUS
ABUS
ABUS

IOA
IOA
IOA
IOA

REQUEST
REQUEST
REQUEST
REQUEST

3
2
1
0O

ABUS LEN STAT 1 H
ABUS LEN STAT 0O H

10-37

MASK
MASK
MASK
MASK

3
2
1
0

H
H
H
H
31
30
29
28

H
H
H
H

23 H
22 H
21 H

DATA ADDRS 20 H
ADDRS 19 H
ADDRS 18 H
ADDRS 17 H
ADDRS 16 H

H
H
H
H

CONSOLE

SOFTWARE

Default

Visibility

symbol

VS$B140

AND

Bit

Nibble

V$B190
VSB141
VSB191

14
13
12

V$B127

V$B196
V$B208
V$B193

10
09
08

V$B1924
V$SB169

07
06

V$B209
V$B206

VSB20S5

V$SB168

V$B176
VSB177

COMMANDS

Registers

name

ABUS DATA ADDRS 15 H

ABUS

DATA ADDRS

ABUS
ABUS

DATA ADDRS
DATA ADDRS

ABUS
ABUS

DATA ADDRS
DATA ADDRS
DATA ADDRS

ABUS
ABUS

DATA ADDRS

14
13
12

H
H
H

11
10
09
08

H
H

ABUS
ABUS

DATA ADDRS
DATA ADDRS

05 H
H

ABUS DATA ADDRS 03 H

ABUS DATA ADDRS 02 H

ABUS
ABUS

DATA ADDRS
DATA ADDRS

H
H

ARADR

V$ symbol

Bit

Nibble

Signal name

V$K103

MAP1

VSK105
V$K101

27
26

VS$K179
VSK174

VSK177

22
21
20

V$K162

V$K157

VS$K161

VS$K156

VSK155
V$K151

15
14

13
12

VSK147
V$K143

VSK146
VSK142

09
08

VS$SK145

V$K141
V$K140
V$K139

06
05
04

VS$K135
VS$XXXX

03
02

VSXXXX
VSXXXX

MAPl1 ARRAY ADR
MAP1 ARRAY ADR

27 H
26 H

MAP1

ARRAY ADR

MAP1 ARRAY ADR

MAP1 ARRAY ADR 22 H
MAP1 ARRAY ADR 21 H
MAP1 ARRAY ADR 20 H
5

MAP1 ARRAY ADR

MAPl1

ARRAY ADR

MAP2 ARRAY ADR
MAP2 ARRAY ADR

15
14

H
H

MAP2
MAP2
MAP2
MAP2

11
10
09
08

H
H
H
H

MAP1 ARRAY ADR 18 H

VS$K154
VS$SK148

ARRAY ADR

MAP1 ARRAY ADR 25 H

VS$K173
VS$K171
VS$SK159

H
H

ABUS DATA ADDRS 07 H
ABUS DATA ADDRS 06 H

05
04

Signal

MAP2 ARRAY ADR 16 H
4

MAP2 ARRAY ADR 13 H
MAP2 ARRAY ADR 12 H

ARRAY
ARRAY
ARRAY
ARRAY

ADR
ADR

MAP2 ARRAY ADR 07 H

MAP2 ARRAY ADR 06
MAP2 ARRAY ADR 05
MAP2 ARRAY ADR 04

H
H

MAP2 ARRAY ADR 03 H
Zero-Filler

01
00

Zero-Filler
Zero=Filler

10-38

CONSOLE

SOFTWARE

AND

COMMANDS

Default Visibility Registers

—

ARBUS

V$ symbol

Bit

Nibble

Signal

VSK113
VSK112
VSK106
VSK107

31
30
29
28

ARRAY BUS

D31

ARRAY BUS
ARRAY BUS

D30
D29

H
H

VSK108

V$SK102
VSK175
VSK178
VSK104

VSK100
VSK176

VSK172
VSK167

VS$SK169
VSK166

VS$K170
VSK131

VS$SK127
VSK129

11
10

BUS

D25

ARRAY BUS

D24

ARRAY BUS
ARRAY BUS

D23
D22

H
H

ARRAY BUS
ARRAY BUS

D21
D20

H
H

ARRAY BUS

D19

ARRAY BUS

D17

ARRAY

BUS

D15

ARRAY BUS

D13

ARRAY BUS
ARRAY BUS

D11
D10

H
H

ARRAY BUS D14 H
ARRAY BUS D12 H
3

09
08
07
06

D27

ARRAY

ARRAY BUS D16 H

VSK126
V$K125

ARRAY BUS

ARRAY BUS D18 H

VSK123
VSK124

21
20

D28 H

ARRAY BUS D26 H

VS$K130

V$SK128
VS$K119

ARRAY BUS

23
22

name

ARRAY BUS D09 H
ARRAY BUS D08 H
2

ARRAY BUS
ARRAY BUS

D07
D06

H
H

VS$K122
VS$K118

05
04

V$K121
VSK117

ARRAY BUS

D03

ARRAY BUS

D02

VSK116

ARRAY BUS

D00

VS$K120

ARRAY BUS D05 H
ARRAY BUS D04 H
1

ARRAY BUS DO1 H

DBUS

symbol

vV$3271
V$3262

vV$3272

Bit

Nibble

Signal

-DBUS D31 H

V$3266

v$3170

vV$3225

v$3240

Vv$3270

V$3263
V$3273
v$3275

22
21
20

vs$3241

-DBUS

D30

-DBUS

D28

-DBUS

D27

-DBUS

D26 H

-DBUS

D24

-DBUS

name

D29 H

-DBUS D25 H

~DBUS D23 H
-DBUS
-DBUS
-DBUS

10-39

D22
D21
D20

H
H
H

CONSOLE SOFTWARE AND COMMANDS
Default Visibility Registers

V$ symbol

Bit

Nibble

Signal name

V$3171
vs3187
V$3237
V$3236

19
18
17
16

-DBUS
-DBUS
-DBUS
-DBUS

V$3269
V$3268
v$3274
v$3267

15
14
13
12

-DBUS D15 H
-DBUS D14 H
-DBUS D13 H
-DBUS D12 H

v$3220
V§3222
V$3239
vV$3242

11
10
09
08

-DBUS
-DBUS
-DBUS
-DBUS

D11 H
D10 H
D09 H
D08 H

V$3176
V$3178
V$3105
v$3104

07
06
05
04

-DBUS
-DBUS
~-DBUS
-DBUS

D07
D06
D05
D04

H
H
H
H

V$3145

-DBUS

D03

v$31l44

~-DBUS D02 H

V$3243
V$3126

01
00

-DBUS
~-DBUS

D19
D18
D17
D16

D01
D00

H
H
H
H

H
H

EBFLSH

symbol

Bit

Nibble

Signal

name

v$3198

-ICA BUF FLUSH MRES3

v$5230

-ICAB

vs$5218
V$5242

02
01

-CSB UMCF 2 A H
ICA6 IFORK CTL 2

V$5194

-CSB UMCF

EFLSH

FR CPC

0 A H

EDPPE

symbol

Bit

Nibble

Signal

V$9104
V$D157
v$9102
V$D156

43
42
41
40

EDP
EDP
EDP
EDP

EDPE

EDPE
EDPE
EDPE

D3
D2
D1
DO

H
H
H

VSE138
VSE109
VSE177
VSE120

39
38
37
36

EDP
EDP
EDP
EDP

STATE
STATE
STATE
STATE

7
6
5
4

H
H
H
H

VSE184
VSE136
VSE110
VSE178

35
34
33
32

EDP STATE
EDP STATE
EDP STATE

3
2
1

H
H
H

EDP STATE

VS$A180

v$9103

Vv$9100
vs$olsgl

name
H

ICA ISTALL A H
EBD RSV MODE

29
28

ICB RLOG PE H
ICB IBUF PE H

10-40

LAT H

CONSOLE

SOFTWARE

Default
V$

symbol

AND COMMANDS

Visibility

Bit

Nibble

Signal

Registers

name

V$5123
V$9101
V$9176

ICA7

ICS

ICB

IDRAM

IDP

IAMUX

V$9182

IDP

IBMUX

VSXXXX
V§6127
V$5167
V$9162

21
20

v$§5221

V$5186
V$9110

18
17
16

V$D166

- 15

EBD EBOX ERR

LST CYC

v$4167
v$9170
V$9110

14
13

EBD

EBOX

EBD

ECS

FLAG

EBD

ECS

LST

CYC

EBD EDP

FLAG A H

FLAG

v$9170

v$D158
V$9169
v$9173
vV$9161

PAR ERR

Zero=Filler

MCC

IBF

PA ACK

MCC

MBOX

PA ACK

EBD ESTALL TO

ICA H

EBE

IBOX

EBD

ECS

FLAG

EBD

ECS

LST

CYC

EBD

EDP

EBD

EMCR

EBD

ERR

H
H

LTH A

ERR

H
H

IDP

FLAG

ETRAP

H
H

V59174
v$9143

EBD WBUS

V$C159
vsCclel

05
04

-EBC

MCF

RAM

PAR

EBD6

EVC

D09

V$4139
v$0131

- EBE

WBUS

OPAR B2

v$0129
v$4281

EBE

WBUS

OPAR

~-DBUS

EBD USTK PE FLAG H

FLAG

ERR

-ICA BMUX CHK WITH

D08

Bit

Nibble

Signal
-CS5B

EBOX

FORK

-CSB

EBOX

FORK

oo ftw e lie sl o o

symbol

-l NeoRw)

EFORK

V$6146

v$0100
v$8124
V$5159

H
H

name

-CSB

EBOX

FORK

~CSB

EBOX

FORK

V$C226

-CSB

EBOX

FORK

VSXXXX
V$Cl102
V$6101
V$1231

03
02
01
00

Zero~Filler

10-41

-CSB

EBOX

IRD A

-CSB
-CSB

EBOX
EBOX

IRD B
IRD C

H
H

CTX H

CONSOLE SOFTWARE AND COMMANDS
Default Visibility Registers
EMCF

Nibble

Sign al

v$D184
V$D186

37
36

CSA

UMCF

CSA

UMCF

v$D181
vV$D183
v$D180
v§$D182

CSA

UMCF

34
33
32

CSB

UMCF

CSB

UMCF

CSB

UMCF

VSXXXX
VSXXXX

31
30

tero -Filler

VSA153
VSA182

EBC

vS$al74
V$Al65
VSAl64
V$Al54

EBC
EBC

EBOX MCF

26
25

EBC

EBOX MCF

EBC

EBOX MCF

VSXXXX
V$D154
V$D153
V$D155

23
22
21
20

VS§D151
V$D146
Vv$D140
v$D150
VsCl1l79
v$C187
v$Cl84
V$C1l86

vV$Cl180
vV$C178
v$Ccl27
vV$C199

name
o
oomom
o

PV
gl NS

Lo I

EBOX MCF

oefiuefiieniinn

EBOX MCF
EBOX MCF

Zero -Filler

L
BN
S OV

symbol

B Un

Bit

tero -Filler

MCF-LOAD N H
MCF-LOAD T H
-EBC 9 MCF-REQUE N H

-EBC 9

MCF-REQUE T H
MBOX H
EBCA MCF-WCHK H
EBCS8 MCF-E DISP I H

-EBC 9

EBCA MCF-EN

17
16

MCF-ACK REQ LTH H
MCF-CLR EBPS LTH H
-EBC MCF-CLR IBPS LTH H
-EBC MCF-CLR OPPS LTH H

11
10

-EBC

MCF=EN OWSTL LTH O
MCF-MEM REQ LTH H
=EBC MCF-MEM WRT LTH H
=EBC MCF-OP WRT LTH H
=EBC

-EBCA MCF-ACK REQ H
-EBC 8 MCF-CLR EBPS H
~EBC 8 MCF-CLR IBPS H
-EBC 8 MCF-CLR OPPS H

V$D143
v$D138
V$D149
V$D137

06
05

V$D134
V$D139

03
02

=-EBC 7

MCF-EN

OWSTL

-EBC 7

MCF-MEM

REQ

V$D104

-EBC 7
—-EBC 7

MCF-MEM WRT H
MCF-OP WRT H

V$D105

10-42

H
H

CONSOLE

SOFTWARE

Default

AND COMMANDS
Visibility Registers

VS symbol

Bit

Nibble

Signal

name

VSE183
V$D171

11
10

-EBD ESTALL TO CSB H
EBD ESTALL TO EBC H

ESTALL

VS$9166

V$8160

vS$0190

vs1123

-EBD ESTALL TO IBD H

EBD ESTALL TO

FBM

v$5221

EBD

ESTALL TO

ICA

EBD

ESTALL TO

ICB

EBD
EBD

ESTALL TO MCC H
ESTALL 'TO MUD H

vV$3157

v$6138

V$S4126

VSA184
v$2114

01
00

EBD ESTALL TO EBE H
EBD ESTALL TO

EDP

EBD ESTALL TO IDP H

EUPC

symbol

Bit

Nibble

Signal

name

VSF122

CSB

UPC

VSF123

CSB

UPC

VSF111
VSF113
VSF107

10
09

CSB
CSB

UPC
UPC

10
09

H
H

CSB

UPC

VSF112
VSF115
VSF109
VSF110

CSB

UPC

06
05

CSB

UPC
UPC

CSB

UPC

VSF114
VSF126
VSF118
VSF127

03
02
01
00

CSB

UPC

CSB
CSB

UPC
UPC

02
01

A H
A H

CSB

UPC

00 A

Bit

Nibble

Signal

V$B222

V$B112

V$B187
V$SB182

29
28

EDP EVA A31
EDP EVA A30

H
H

v$B188
V$B132
VSB201

27
26
25

EDP EVA A27
EDP EVA A26
EDP EVA A25

EVABUS

symbol

VS$B119

V$B118
V$B133
VSB134
V$B123

23
22
21
20

EBD ESTALL TO FBA H

name

EDP EVA A29 H
EDP EVA A28 H
7

U
H

EDP EVA A24 H
6

EDP

10-43

EVA A23

EDP EVA A22
EDP EVA A2l

H
H

EDP EVA A20

CONSOLE SOFTWARE AND COMMANDS
Default Visibility Registers

V$ symbol

Bit

Nibble

Signal name

VSB126
VS$SB192
V$B122
V$B207

19
18
17
16

EDP
EDP
EDP
EDP

EVA AlY
EVA Al8
EVA Al7
EVA Al6

H
H
H
H

VSB215
V$B143
V$SB146
V$B145

15
14
13
12

EDP
EDP
EDP
EDP

EVA Al5
EVA Al4
EVA Al3
EVA Al2

H
H
H
H

V$B144
V$B216
V$B213
VSB175

11
10
09
08

EDP
EDP
EDP
EDP

EVA All
EVA AlQ0
EVA A09
EVA AQ08

H
H
H
H

vs$Bl71
V$B179
V$B173
V$SB174

07
06
05
04

EDP
EDP
EDP
EDP

EVA A07
EVA AQ06
EVA AQ5
EVA A04

H
H
H
H

v$éBle7

EDP EVA AO3 H

V$ symbol

Bit

Nibble

Signal name

V§1197
vV$1269
v$1138
v$1180

31
30
29
28

-FBA FA BUS
-FBA FA BUS
-FBA FA BUS
-FBA FA BUS

vS$11l71
v$lle7
v$1250
VS$1170

27
26
25
24

=FBA FA BUS D27 H
-FBA FA BUS D26 H
-FBA FA BUS D25 H

vs$1l1l98
v$1260
v$1139

23
22
21

Vv$1261
v$1248
VvS§1137
V51169

19
18
17
16

-FBA
-FBA
~-FBA
-FBA

FA
FA
FA
FA

V$1199
vs$1l262
vsll134
v$1183

15
14
13
12

-FBA
-FBA
-FBA
-FBA

FA BUS
FA BUS
FA BUS
FA BUS

V$B170
VSB159
VSB162

02
01
00

EDP EVA AQ02 H
EDP EVA A0l A H
EDP EVA AQ00 A H

FABUS

V$1165

V$1263

vV$1l244

v$1249
V$1164

H
H
H
H

-FBA FA BUS D24 H
-FBA FA BUS D23 H
-FBA FA BUS D22 H
-FBA FA BUS D21 H

-FBA FA BUS D20 H

D31
D30
D29
D28

BUS
BUS
BUS
BUS

D19
D18
D17
D16

H
H
H
H

D15 H
D14 H
D13 H

D12 H

-FBA FA BUS D11 H

-FBA FA BUS D10 H

-FBA FA BUS D09 H
-FBA FA BUS D08 H

09
08

10-44

{

CONSOLE

Default
V$

symbol

SOFTWARE AND COMMANDS

Visibility

Bit

Nibble

Signal

07
06
05

V$1133

V$1196

-FBA FA BUS
-FBA FA BUS
-FBA FA BUS
-FBA FA BUS

v$l2e4
v$1245
vs$1l251

03
02
01

v$1200
v$1265

VS$S1168

name

D07
DO6
D05

H
H
H

D04

-FBA FA BUS D03 H
=FBA FA BUS D02 H
-FBA FA BUS D01 H

-FBA FA BUS DOO H

FAUPC

symbol

Bit

Nibble

Signal name

v$0243

FAll

UPCA A8

v$0321
v$0320
v$0319

07
06
05

FAl1l

v$0325

FAll
FAl1ll

UPCA A7 H
UPCA A6 H
UPCA A5 H

FAll

UPCA A4

vVs0324
vs$0322

03
02

v$0242

vV$0335

FA1ll UPCA A3 H
FAll UPCA A2 H

FAll

UPCA Al

FAll UPCA AOQ0 H

FMUPC

symbol

Bit

Nibble

Signal

V$1152

FM11l

UPC A8

V$1149

07
06

FM11l
FM11

UPC A7
UPC A6

V$1179

vVs$1178

V§1155

V$1154

vS$1148
V$1153
V§1150

name

FM11 UPC AS H

FM11l

UPC A4

FM11

UPC

FM11

01
00

FM11
FM11

UPC A2 H
UPC Al H
UPC AOQO H

IBDBUF

symbol

v$4289
v$4288

Bit

Nibble

Signal

IBD DRAM CTX
IBD DRAM CTX

vV$4287

V$5117
V$5211
V$5116

39
38
37

VS$5214

name
2

IBD DRAM CTX 0O H

IBD DRAM TYPE 1 H
IBD DRAM TYPE 0 H
IBD DRAM REF 1 H

IBD DRAM REF

10-45

0 H

Registers

CONSOLE SOFTWARE AND COMMANDS
Default

Visibility

Registers

V$ symbol

Bit

Nibble

Signal name

Vv$5192

34
33
32

IBD BDEST NEXT H

V$5163
v$5171
V$5236

V$5245
V$5249
vV$6129
v$6128

31
30
29
28

IBD
IBD
IBD
IBD

vV$5270

IBD IFORK VALID H

v$5213

v85175
v$5172

26
25

v$5111

v$5101
v$5103

21
20

v$3193

IBD DRAM LAST H
IBD DRAM SUSP H
IBD DISABLE SB HIT H

BUF
EXT
BUF
BUF

FD INST H
OPC H
IBUF PE H
DRAM PE H

IBD DMUX VALID H
IBD EXC ONLY H
IBD EPC 0 OR 7 H

IBD ISEL B2 H

ICA LD IFORK DISP H

IBD BUF LD CTL 1 H
IBD BUF LD CTL O H

V$4286
v$4192
v$4187

19
18
17

~-IBD OPTIMIZED H
IBD BUF DELTA PC
IBD BUF DELTA PC

vV$6132

IBD IBGPR 3 H

v$4285

IBD IGPR

v$4283
v$4282

09
08

v$5161

IBD BUF FA

7 H

V$5136

IBD BUF

V$5253
V$5158

05
04

IBD BUF FA 5 H
IBD BUF FA 4 H

V$5179

V$6119
v$6l21

01
00

v$4193
V$6179
vV$6135
vV$6133

v$4284

vs$6123

2 H
1 H
IBD BUF DELTA PC O H

16
14
13
12

TRD TBGPR 2 H
IBD IBGPR 1 H
IBD IBGPR 0 H

IBD

IGPR

IBD IGPR 1 H
IBD IGPR 0 H
2

IBD BUF

FA 3

IBD BUF FA 2 H

IBD BUF FA 1 H
IBD BUF FA 0 H

IBUF

V$ symbol

Bit

Nibble

Signal name

V$5114
v$5208
v$5209
V$5210

15
14
13
12

IBD
IBD
IBD
IBD

IBUF DATA Bl
IBUF DATA Bl
IBUF DATA Bl
IBUF DATA Bl

7
6
5
4

H
H
H
H

vV$5237
v$5233
V$5246
v$5243

11
10
09
08

IBD
IBD
IBD
IBD

IBUF
IBUF
IBUF
IBUF

3
2
1
0

H
H
H
H

10-46

DATA
DATA
DATA
DATA

Bl
B1
Bl
Bl

CONSOLE SOFTWARE AND COMMANDS
Default Visibility Registers

V$ symbol

Bit

Nibble

Signal name

v$5104
vV$5106
vs$5108
Vv$5105

07
06
05
04

IBD IBUF DATA BO
IBD IBUF DATA BO
IBD IBUF DATA BO
IBD IBUF DATA BO

7 H
& H
5 H
4 H

vV$5250
v$5248
v$5247
vV$5252

03
02
01
00

IBD IBUF DATA BO
IBD IBUF DATA BO
IBD IBUF DATA BO
IBD IBUF DATA BO

3 H
2 H
1 H
0 H

V$ symbol

Bit

Nibble

Signal name

VSCl197

-EBE IBOX ERR LTH E H

vs$g8le3
vV$4166
V$6204
vV$5186

03
02
01
00

EBE
EBE
EBE
EBE

Bit

Nibble

Signal name

v$D102
vV$§5244

05
04

ICA IBOX DIAG DONE H
EBC E DISP I DLY H

vV$D150
V$5196
V$6116
v$4130

03
02
01
00

EBC8 MCF-E DISP I H
-ICB ID FULL STALL H
ICA PC ISTALL H
IDP5 ISTALL A H

V$ symbol

Bit

Nibble

Signal name

Vv$4175
v$31l3l
V$3150
V$3253

07
06
05
04

-IBD INCR VIBA BY 4 H
IBD9 SHIFT COUNT 2 B H
IBDD LAT CTX 1 H
IBD9 SHIFT COUNT O B H

vsS6171
v$el70
v$6174
vVs$S6206

03
02
01
00

IBD UNLAT CUR VAL
IBD UNLAT CUR VAL
IBD UNLAT CUR VAL
IBD UNLAT CUR VAL

IBXERR

IBOX ERR LTH
IBOX ERR LTH
IBOX ERR LTH
IBOX ERR LTH

D H
C H
B H
A H

IDIAG

V$ symbol

INCR

10-47

3
2
1
O

H
H
H
H

CONSOLE

SOFTWARE

Default

Visibility

AND

COMMANDS

Registers

IOPSEL

symbol

V$3163

vV$3206
vVS$81l46
v$8168

vVS$8143

v$8150

Bit

Nibble

04
03

Signal

CSB

name

UOPSEL

CSB UOPSEL 0 B H
1

CSA UMISC

3 H

CSA

UMISC

CSA UMISC

IUPC

symbol

Bit

Nibble

V$5120

V$5157

VS$5119
vss5121
V$5155

VS$5154

V$5150
V$5156

Signal

ICA8

LD OR SAV

ICA8

LD OR SAV

ICA8

LD OR

SAV

ICA8
ICA8

LD OR SAV
LD OR SAV

1
0

H
H

ICA8 LD OR SAV 6 H

name

ICA8 LD OR SAV 4 H

ICA8 LD OR SAV 2 H

01
00

IVABUS

symbol

V$SB160
V$B223
V8B202

Bit

Nibble

Signal

name

31
30
29

IVA BUS
IVA BUS
IVA BUS

31
30
29

H
H
H

IVA BUS

IVA BUS
IVA BUS
IVA BUS
IVA BUS

27
26
25

H
H
H

V$B185

V$B117
VSB186
VSB184
VSB115

27
26
25
24

V$B114

VSB116

VS$B129
VS$B125

VSB121

V$B124
VSB217

17
16

VSB214
VSB147
VSB149
VSB148

15
14
13
12

VS$SB218
VS$B219

11
10

VS$B120

VSB220

VSB211

IVA BUS

IVA BUS 22 H
IVA BUS 20 H
5

IVA BUS

18 H

IVA

BUS

IVA

BUS

IVA
IVA
IVA
IVA

BUS
BUS
BUS
BUS

15
14
13
12

H
H
H
H

IVA BUS 11 H
IVA BUS 10 H

10-48

IVA BUS

"oTMo

CONSOLE SOFTWARE AND COMMANDS
Default Visibility Registers

V$ symbol

Bit

Nibble

Signal name

véBl172
v$B210
V$B180
VSB166

07
06
05
04

IVA BUS
IVA BUS
IVA BUS
IVA BUS

07
06
05
04

VSB178
vV$Bl8l
V$B161
V$SB158

03
02
01
00

IVA BUS
IVA BUS
IVA BUS
IVA BUS

03 H
02 H
01 H
00 H

V$ symbol

Bit

Nibble

Signal name

v$3281
v$3232
V$3244
v$3251

31
30
29
28

MD BUS
MD BUS
MD BUS
MD BUS

D31
D30
D29
D28

H
H
H
H

vV$3252
vV$3282
v$3116
V83165

27
26
25
24

MD BUS
MD BUS
MD BUS
MD BUS

D27
D26
D25
D24

H
H
H
H

v$3280
vV$3234
v$3229
v$3235

23
22
21
20

MD BUS
MD BUS
MD BUS
MD BUS

D23
D22
D21
D20

H
H
H
H

v$3120
v$3279
v$3118
v$3283

19
18
17
16

MD BUS
MD BUS
MD BUS
MD BUS

D19
D18
D17
D16

H
H
H
H

V$3277
v$3230
v$3248
v$3233

15
14
13
12

MD BUS
MD BUS
MD BUS
MD BUS

D15
D14
D13
D12

H
H
H
H

v$31l21
V$3256
V$3119
v$3168

11
10
09
08

MD BUS
MD BUS
MD BUS
MD BUS

D11
D10
D09
D08

H
H
H
H

V$3276
v$3228
vV$3249
v$3250

07
06
05
04

MD BUS
MD BUS
MD BUS
MD BUS

D07
D06
DO5
D04

H
H
H
H

V$3254
v§3257
V$3135
vs$31l64

03
02
01
00

MD RUS
MD BUS
MD BUS
MD BUS

D03
D02
DOl
DOO

H
H
H
H

MDBUSI

10-49

CONSCLE

SOFTWARE

AND

COMMANDS

Default Visibility Registers
MDBUSM

symbol

v$§2130

Bit

Nibble

Signal

MD BUS D31 H

v$2131
v$2129

30
29

v$2132

V$2140
v$2139

27
26

vs$2135
v$2136

vS$2144

23
22
21

V$2154
v$2153
v$2162
v$2160

19
18
17
16

V$2166
v$2156
v$2167

Vv$2157
v$2158
v$2101
v$2195
vV$2100

vV$2103

D28

BUS

MD BUS
MD BUS

D27 H
D26 H

MD BUS

D24

MD BUS D23 H
D22

D21

MD
MD
MD
MD

BUS
BUS
BUS
BUS

D19
D18
D17
D16

H
H
H
H

15
14
13

MD BUS
MD BUS
MD BUS

D15
D14
D13

H
H
H

11
10
09
08

MD BUS D20 H

06
05
04

vV$2107

03
02

vV$2105

D30 H
D29 H

MD BUS
MD BUS

v$2102
v$2106
v$2198

v$2199
v$2200

MD BUS
MD BUS

MD BUS D25 H

v$2134
V$2155

vs$2161

name

MD BUS D12 H
MD
MD
MD
MD

BUS D11 H
BUS D10 H
BUS D09 H
RUS D08 H

MD BUS D07 H

MD BUS
MD BUS
MD BUS

D06 H
D05 H
D04 H

MD BUS DO3
MD BUS D02
MD BUS DOl

H
H
H

MD BUS DO0OO H

MEMREQ

symbol

vVS$C1l71
V$C172
V$5167

VS§C215
vs$Cl173
VS$SCl74
vsCl93

VSCl191

V$C190

V$C192

Bit

Nibble

24
23

22
21
20
19

Signal

name

MCC EBOX PA ACK A H

MCC OP PA ACK A H
6

MCC

IBF

MCC

PORT STAT CODE

MCC

PORT STAT CODE
PORT STAT CODE

1
0

PA ACK H

EBC EBD MAST RST DLY H
MCC DEST CODE 1 H
~-EBD9 MEM REQ LST CYC H
5

)

MCC PORT STAT CODE 2 H

MCC

10~50

CONSOLE

SOFTWARE

Default

AND COMMANDS

Visibility

Registers

V$ symbol

Bit

Nibble

Signal name

VSA180
VSAl167
v$C231

15
14
13

ICA ISTALL A H
ICA IBF REQUEST H
MCC STAT CODE OUT

V$SC226

V$Ale68
VS$SA179
VSA190
VSA186

11
10
09
08

VSA221
V$SAl84
V$A153

07
06
05

VSAl182

VSAL74
V$Al65
VSAl64
VSAL154

03
02
01
00

V$ symbol

Bit

Nibble

Signal

VSAl92
VSA231
VSA273
VSA274

07
06
05
04

MCC1
MCC1
MCC1
MCC1

UADR
UADR
UADR
UADR

B
B
B

VS$SA109
V$A11l0
VS$SA288
VSA279

03
02
01
00

MCC1
MCC1l
MCC1l
MCC1

UADR
UADR
UADR
UADR

A 3 H
A 2 H
A 1 H
A O H

V$ symbol

Bit

Nibble

Signal

v$3213
vs$3217
v$3209
v$3112

19
18
17
16

IBDC
IBDC
IBDC
IBDC

NAT
NAT
NAT
NAT

CTX 2 H
CTX 1 H
CTX 0O H
TYPE 1 H

V$3183
V$3167
v$3182
v$3210

15
14
13
12

IBDC
IBDC
IBDC
IBDC

NAT
NAT
NAT
NAT

TYPE 0 IO
REF 1 H
REF 0 H
CTL 1 H.

vV$3177

IBDC NAT CTL O I

v$3208
V$3109

10
09

IBDC
IBDC

NAT
NAT

SUSPEND H
BDEST NXT

V$3211

IBDC

NAT

LAST H

v$3184

IBDB

NAT

OPAR

-CSB

1 H

EBOX FORK A H

ICB OP MCF 3 H
ICB OP MCF 2 H
ICB OP MCF 1 H
ICB OP MCF 0

ICA
EBD
EBC
EBC

OP ABORT A H
ESTALL TO MCC
EBOX MCF 5 H

EBC
EBC
EBC
EBC

KEBOX
EBOX
EBOX
EBOX

EBOX MCF 4
MCF
MCF
MCF
MCF

3 H
2 H
1 H
0 H

MUPC

name
7 H
6 H
5 H

B 4 H

NATRAM

Vv$3101
v$3180
v$3103

06
05
04

name

IBDB NAT FPA H
IBDB NAT ADRS 05 H
IBDB NAT ADRS 04 H

10-51

CONSOILFE

SOFTWARE

Default

Visibility

symbol

Vs3278
v$3102
v$3108
V$3100

AND

COMMANDS

Registers

Bit

Nibble

03
02
01
00

Bit

Nibble

Signal

ICA

Signal

IBDB
IBDB

name

NAT ADRS

IBDB

NAT ADRS
NAT ADRS

IBDB

NAT ADRS

03 H
02 H
01 H
00 H

OPAR

symbol

V$4278
V$4102

VS$Cl44

v$3184
v$3221
V$5170

34
33
32

VSXXXX
V$4206

31
30

v$g8184
vs$8191

29
28

Vs$8154

V$8155
V$8153

ICA

26
25

23
22
21
20

V$4205
V$4123

19
18

vs$2127
vV$2125
V$2113

v$3153
V$3149
V83152

v$314s8

VSXXXX
VSXXXX

VSXXXX

11
10
09

02
01

OPAR B3
OPAR B2

B H
B H

OPAR

~-EBE WBUS OPAR

OPAR BO

WBUS

-EBE WBUS OPAR B2 H
-EBE WBUS OPAR Bl H

-EBE

WBUS

MCD MD BUS OPAR B3
MCD MD BUS OPAR B2
MCD MD BUS OPAR Bl

H
H
H

MCD MD BUS OPAR BO H
2

formerly
formerly

V$4101

V$4140

vV$4100

EBE WBUS
EBE WBUS
EBE

08
07

WBUS OPAR B3 C H
WBUS OPAR B2 C H
WBUS OPAR B1 C H
WBUS OPAR BO C H

EBE WBUS OPAR Bl B H

VSXXXX

VS$S4104

EBE
EBE
EBE
EBE

14
13

OPAR B2 A H
OPAR Bl A H

EBE WBUS OPAR BO A H

EBE WBUS OPAR B3 A H

EBE WBUS
EBE WBUS

v$0186
V$0131
v$0129
v$0180

V$2126

Zero-Filler
-ICA EN OP OPAR VAL

-IDP OP OPAR VALID H
IDP OP LWD OPAR H

V$4209

EDP OPR PAR ERR H

IBDB NAT OPAR H
IBDD LAT OPAR H
ICA5 ICS OPAR H

vVS$8156

VvS$4210

name

FORCE AMUX OPAR H
FORCE BMUX OPAR H

formerly

formerly
1

MCD MD BUS
MCD MD BUS
MCD MD BUS
MCD MD BUS

IBD DBUS

OPAR B3

IBD DBUS

OPAR

IBD DBUS OPAR B2 H
Bl

IBD DBUS OPAR BO H

10-52

OPAR B3

OPAR B2
OPAR Bl

OPAR BO

H
H

CONSOLE

SOFTWARE AND COMMANDS

Default Visibility Registers

M"”

OPBUS

V$ symbol

Bit

Nibble

Signal name

vs0178
V$0174
vs$0148
V$0106

31
30
29
28

OP
OP
OP
OP

BUS
BUS
BUS
BUS

D31
D30
D29
D28

H
H
H
H

vs$0203
V$0260
v$0153
vV$0232

27
26
25
24

OP
OP
OP
OP

BUS
BUS
BUS
BUS

D27
D26
D25
D24

H
H
H
H

vs$0202
vs$0261
vs$0149
v$0228

23
22
21
20

OP
OP
OP
OP

BUS
BUS
BUS
BUS

D23
D22
D21
D20

H
H
H
H

v$0285
vs$0172
v$0154
v$0229

19
18
17
’16

OP
OP
OP
OP

BUS
BUS
BUS
BUS

D19
D18
D17
D16

H
H
H
H

v$0295
vs$0198
V$0344
vs$0289

15
14
13
12

OP
OP
OP
OP

BUS
BUS
BUS
BUS

D15
D14
D13
D12

H
H
H
H

v$0301
v$0300
v$0293
vs$0271

11
10
09
08

OP
OP
OP
OP

BUS D11 H
BUS D10 H
BUS D09 H
BUS D08 H

vs$0286

OP BUS D07 H

vs$0103

vs$0274

vVs$0275

OP BUS D06 H

OP BUS DO5 H

Vvs$0179
vs$0264

03
02

V$0152
v$0233

01
00

OP BUS D04 H

OP BUS D03 H
OP BUS D02 H
OP BUS
OP BUS

DOl
DOO

H
H

OPCODE

V$ symbol

Bit

Nibble

Signal name

Vs$1101

ICA OPC BIT 7 A H

v$1103
v$1238

06
05

ICA OPC
ICA OPC

v$1l1l25

ICA OPC BIT 4 A H

v$1240
v$1237
vs$l1l4l
v$1l241

03
02

BIT
BIT

ICA OPC BIT
ICA OPC BIT

6 A H
5 A H

3 A H

2 A H
ICA OPC BIT 1 A H
ICA OPC BIT O A H

01
00

10-53

CONSOLE

SOFTWARE AND COMMANDS
Visibility Registers

Default

OPMCF

symbol

VS$SA168
VS$Al179
VSA190

Bit

Nibble

Signal

03
02

ICB OP MCF 3 H
ICB OP MCF 2 H

V$SA186

name

ICB OP MCF

ICB OP MCF 0 H

OPPORT

symbol

Bit

Nibble

Signal

VS$5149

63
62

ICA OPV CTL
ICA OPV CTL

V$5141

-ICB

V$6186
V$6190

v$61l58

VSXXXX

VS$6127

VSXXXX

VS$C212
vsC211
V$6155
VSXXXX

v$Cc1s8s

V$4206
v$8184
VSXXXX

39
38
37

VSXXXX
f

36
35

V$5148

V$6109

V$C213
v$C148
V$6134

=ICB ALWAYS OP VALID H

-ICB ALMOST OP VALID H
-ICB8 ALMOST SET OPV H
Zero=Filler

ICA OP ABORT A H

ICA OP ABORT B LAT H
ICA IBF OR OP FLUSH H
ICA MBOX FLUSH A H

~ICA OP FLUSH B H

-ICA EN OP OPAR VAL H
~-IDP OP OPAR VALID H
Zero=-Filler

Zero-Filler

ICB KILL OP WRT H
MCC NEXT OP WRT H
MCC TRAP OP WCHK H

V$5254

V$8C1l76

Zerov-Filler

EBD OPBUS VALID H
-FBA OPBU VAL TO FBM H
Zero-Filler

VSE135

OP PA ACK A H

Zero=-Filler

Zero-Filler

MCC

43
42
41

OPV

IMD OPV LAT H

MCC OP PA ACK B H

47
46
45

V$A221

VSE186

52
51
50
49

V$C183
V$1120
VSA264

SET

PEND IMD OPV H
Zero-Filler

V$0191
V$1206
VSXXXX

VSE102

-ICB9

VSXXXX

V$C201

-ICB9

V$C172

0 H
1 H

~-ICAG SET OPV FB H

V$6154
VSXXXX

name

MCC TRAP OP WRT H

-EBDY9 EN OP WRT STALL H

~-ICAG OP REQ CIP LAT
ICB SET OP WRT CIP H

-ICBA OP WRT CIP H

-EBD9 OP WRT IN PROG H

-EBD9

-ICA

10-54

OP WRT LST CYC
OP WRT LAT H

CONSOLE

SOFTWARE

Default

symbol

VSC170
V$6165
VSXXXX
VS$4147

p——

Bit

Nibble

Signal

23
22

-ICA EN OP WRT ACK H
-ICA

name

ENA

OP MD

Zero=Filler

-ICA

IVA

V54176
V$5131

19
18

IDP

v$5241
VS$SA186

IDP

ICB

VSA190
VSA179

15
14

V$Al68
VS$XXXX

V$SA185
V$A170
VSA183
V$3143

AND COMMANDS
Visibility Registers

-ICA

ENA OP VA
VA

BIT

MCF

OP MCF

ICB

MCF

ICB

MCF

Zero-Filler

ICB OP MEM

CTX

ICB

MEM

CTX

ICB

MEM

CTX

ICB

MEM

REQ

ICB

MEM

REQ A

Zero-Filler

V$Cl117

-ICA

ICB

VEXXXX

V$4172

02
01
00

SET

OPMEM

MEM

LD H
00

v$4148
VS$XXXX
vV$6182

v$4221
V$4108

ICB

SEL

RESP

REQ

Zero-Filler
IDPS5

IVA

SEL OP

VA A

IDP5

IVA

SEL

IDPS5

IVA

SEL OP

PAACK

V$ symbol

Bit

Nibble

VSD167
V$Cl171

MCC

EBOX

EBD

Signal
-MCC

name

EBOX

PA ACK
PA ACK

B
H

LTH

V$6142

VSXXXX

v$5167
V$C172
vs$6127

MCC

IBF

MCC

ACK

MCC

ACK

Zero-Filler
PA

ACK

PAMD

symbol

Bit

Nibble

Signal

V$D167

V$A184
V$C215
VSAl167

-MCC

EBOX

EBD

ESTALL

EBC

EBD

MAST

ICA

IBF

REQUEST

ICA

MBOX

FLUSH

ICA

ISTALL

. VSA264

Jvsa221

JV$A180

19
18
17

VSA277

10-55

name
PA ACK
TO

ABORT

FLUSH

ICA

MBOX

H
H

DLY

ICA

MCC

RST

CONSOLE
Default

SOFTWARE AND COMMANDS
Visibility Registers

V$ symbol

Bit

Nibble

Signal name

VSA168

ICB OP MCF 3 H

VS$C193
VsCl1l91
VS$SC190
V$C192

11
10
09
08

MCC
MCC
MCC
MCC

V$C172

V§5167
VS$SA153
VSA182

06
05
04

V$Al174

EBC EBOX MCF 3 H

Bit

Nibble

Signal name

VSAZ2]2

MAP9 PAMM CONF A H

V$A173
VSAl72
VSA224
VSAZ216

03
02
01
00

MAP9 PAMM CONF
MAP9 PAMM CONF
MAP9 PAMM CONF
MAP9 PAMM CONF

Bit

Nibble

Signal

name

EBD ECS

VSA179
V$A190
VSA186

VSAl65
VSAl64
VSAl54

14
13
12

02
01
00

ICB OP MCF 2 H
ICB OP MCF 1 H
ICB OP MCF O H

’

PORT
PORT
PORT
PORT

STAT
STAT
STAT
STAT

CODE
CODE
CODE
CODE

3
2
1
O

H
H
H
H

MCC OP PA ACK A H
MCC
EBC
EBC

IBF PA ACK H
EBOX MCF 5 H
EBOX MCF 4 H

EBC EBOX MCF 2 H
EBC EBOX MCF 1 H
EBC EBOX MCF 0 H

PAMM

symbol

8 H
4 H
2 H
1 H

PARITY

symbol

V$9170

vV$D158

V$9169
V$9173

63
62

VSXXXX
VSXXXX
VSXXXX
v$9110

59
58
57
56

Zerv=Filler
Zero=Filler
Zero-Filler
EBD ECS PE LST CYC

V$C219

-CSB

vV$9174
vs$91l43

FLAG H

EBD EDP PE FLAG A H
EBD EDP PE FLAG H
EBD EMCR PE FLAG H

61
60

EBD USTK PE FLAG H
EBD WBUS PE FLAG H

ECS

PAR

VSE1l64

CSA PAR ERR H

VSF104

CSAS

VSF124

v$Cl42

VSE140
VSE151
V$C144

50
49
48

ERR H

CSA PAR H
-CSB CS PAR OK A H

CSB USTK PAR ERR H

~CSBR FLIP USTK PAR H
CSBS DATA PAR H
EDP OPR PAR ERR H

10-56

{

CONSOLE

SOFTWARE

Default

symbol

Bit

Nibble

Signal

VS$Cl60
V$8134

-EDP

RESULT

DISA

BYTE

vV$8165
v$8126

EDPI

DISA

BYTE

EDPI

FLIP WREG

COMMANDS

Registers

name
PAR

ERR

PAR

v$9150

FLIP

VS$9149
v$9145

WBUS

PAR

ERC

FLIP

WBUS

PAR

41
40

EBC

FLIP WBUS

PAR

EBC

FLIP WBUS

PAR

AND

Visibility

ERR

V$9144
VSXXXX

V$C159
V§$D142
V$D133
VSXXXX
VS$0240

vV$0241
v$0122
v$0121
V$0169
v$0165
v$1275

VSXXXX
v$6128
V$6129
vV$4201

| V$6115

39
38
37

EBC

Zero-Filler

-EBC

MCF

RAM

PAR

EBCA

MCF

PAR

EBCH

FLIP

MCF

Zero-Filler

34
33

FA17

GPR

RAM

PPAR

FAl17 GPR PPAR
FAl7 GPR PPAR

01
02

H
H

31
30
29

FBM

FDRAM

FM16

FA19

PAR

ERROR

PAR

Zero~Filler
IBD

BUF

DRAM

IBD

BUF

IBUF

ICA

FORCE

GPR
RLOG

ICA

FORCE

ICA

ICS

v$9100
V$9176

IBUF

ICB

IDRAM

ICB

RLOG

IDP

IAMUX

VSXXXX

IDP

IBMUX

Zero-Filler

VS XXXX
VSXXXX

15
14
13
12

Zero-Filler
Zero-Filler
MAP2

<29:4> PAR H
formerly
MCC1l MMS

PAR H

MCCC

INV CACH

VSA201
VS$A251
VSA250
V$SA200

MCD3 ABUS

" v$9162

PAR ERR H

formerly
MCC2 ACCESS
U CPR PAR A H

MCCM

VSA204

) VSA148

v$2109

\2V$A232

ICB

VSXXXX
VSAllS8
vsalaeé

VSXXXX

ERROR

UWD PARITY

22
21
20

v$2165

UWD PARITY H

v$9179
v$9181
v$9101

v$9182

PAR

CACH

-MCDU

MAPZ2

03
02
00

MCC

PAR

PERR H

DAT

BYT

DAT

-MCDU

PERR H

PERR

ABUS ADR

PERR H

MAPL

TAG

PERR

MAPL

TAG

-MAPR

10-57

CPR

MBOX

PERR

PERR
CS

H
H

CONSOLE SOFTWARE AND COMMANDS

Default Visibility Registers
PSL

V$ symbol

Bit

Nibble

Signal name

VSE11l7

EBE PSL CM TO CSB H

V$Cl1l3

-EBE PSL TP H

VSAl62
VSXXXX
VSXXXX
v$D125

15
14
13
12

EBE CURMOD 0 TO MCC H
Zero-Filler
Zero-Filler
EBE PSL IPL 4 H

vs§Dl1l27
v$D1l26
v$D131

11
10
09

EBE PSL IPL 3 H
EBE PSL IPL 2 H
EBE PSL IPL 1 H

VSXXXX
VSXXXX
v§C109
VSXXXX

07
06
05
04

Zero~Filler
Zero-Filler
-EBE PSL IV TO EBD H
Zero~-Filler

Vv$9171
v$9172
v$9168
V59167

03
02
01
00

EDP
EDP
EDP
EDP

VS symbol

Bit

Nibble

Signal name

v$2205
v$2203
v$2227
vV$2226

07
06

REG BUS 7 H
REG BUS 6 H

v$2224
v$2225
v$2204
v$2223

03
02
01
00

REG BUS
REG BUS
REG BUS
REG BUS

V$ symbol

Bit

Nibble

Signal name

v$§6202

ICA IFORK NOP H

v$3189
vV$6185

Vv$5133
v$5132

27
26

25
24

ICA IFORK CYCLE H
ICA CTX UNALIGNED H

vs$also
vV$9107
v$C205
v$s6137

23
22
21
20

VSE112
VSE152
VSAl44

v$D130

18
17
16

EBD UTRAP VECTOR 4 H
EBE PSL IS TO CSB H
EBE CURMOD 1 TO MCC H

EBE PSL IPL 0 H

PSL
PSL
PSL
PSL

N
Z
V
C

BIT A
BIT A
BIT A
BIT A

H
H
H
H

REGBUS

REG BUS 5 H

REG BUS 4 H

3
2
1
0O

H
H
H
H

STALL

ICA6 UTRAP CTL 1 H
ICA6 UTRAP CTL O H
ICA
ICA
ICA
ICA

10-58

ISTALL A H
ISTALL B H
ISTALL BUF A H
ISTALL C H

CONSOLE SOFTWARE AND COMMANDS
Default Visibility Registers

symbol

Bit

Nibble

Signal

ICA

ISTALL

D H

ICA

ISTALL

V$3197
V$4156

V$5196
V§3190

17
16

V$9103
V$9100

15
14

V$5123
vV$9181

13
12

-ICB

ICA

name

FULL

STALL

ISTALL A

Vs$9101
V$9176
V$9182
VS$XXXX

EBD RSV MODE

ICS

PAR

ICB

IBUF

H
H

ERR

ICB

IDRAM

IAMUX

09
08

IDP IBMUX PE
Zero=Filler

v$5221
V$5186

03
02
01
00

Bit

Nibble

05
04

MCC

IBF

MCC

MBOX

IDP

07
06

V$9110

RLOG

ICA7

V$C172
vV$6127
V$5167
V$9162

v$9170

ICB

PA ACK A
B

H
H

PA ACK

PA ACK
CS

EBD

ESTALL TO

EBE

IBOX

EBD

ECS

EBD

ECS

ERR

ICA
LTH

FLAG

LST

CYC

UPCSAV

CSBQ

UPCSAVE

CSBQ UPCSAVE

10
09
08

VSE150
VSE171
VSE174
VSE170

VSE149
VSE141
VSE142
VSE148

03
02
01
00

CSBQ

UPCSAVE

CSBQ

UPCSAVE

CSBQ

UPCSAVE

CSBQ UPCSAVE

06
05

CSBQ

UPCSAVE

CSBQ

UPCSAVE

CSBQ

UPCSAVE

CSBQ UPCSAVE

10-59

CSBP

UPCSAVE

CSBP

UPCSAVE

CSBP

UPCSAVE

V§E172
VSE143
VSE157
VSE156

Signal name

DmInn

symbol

VSE173

LRI

CONSOLE

SOFTWARE

Default

Visibility

AND

COMMANDS

Registers

WBUS

symbol

V$4231

Bit

Nibble

Signal

WBUS

name

vV$4227

WBUS

D29 H

D30

V$4223

WBUS

D28

V$4107

WBUS

D27

vV$4257

WBUS

D26 H

V$4271
V$4256

25
24

WBUS
WBUS

D25
D24

H
H

WBUS

D23

WBUS
WBUS

D21
D20

H
H

v$4251

V$4266
V$4253

21
20

Vv$4157

V$4127
v$4128

17
16

vS4247

V$4243

WBUS D14 H

WBUS

D12

VS$4252

v$4131

VS$4244

V$4245

WBUS D22 H

WBUS D19 H

WBUS D18 H

vV$4122

V54274
V$4276
v$4202

10
09
08

v$4184
v$4182

07
06

V$4158
v$4177

05
04

VS$4194

V$4191
v$4178
v$4188

02
01
00

WBUS
WBUS

D17
D16

H
H

WBUS

D15

WBUS D13 H
3

WBUS

D11 H

WBUS
WBUS
WBUS

D10
D09
D08

WBUS
WBUS

D07 H
D06 H

WBUS
WBUS

DOS5
D04

H
H
H

H
H

WBUS D03 H
WBUS
WBUS
WBUS

10-60

D02
DOl

H
H

D00

“

CHAPTER 11
EBOX

11.1

WBUS

The WBus, or Write Bus, is used by the EBox, IBox, and FBox to
write GPR/Scratch Pads, or to transfer result or operand data.
Figure 11-2 shows how the GPR/SP registers receive WBus data and

figure

also

shows the print set

Figure 11-3 shows the WBus termination,

and

provides

parity

for

each

box.

This

location of where data is driven onto the WBus.

look at the WBus drivers and receivers.

closer

Table 11-1 lists the WBus pin location and VTERM for each of the
WBus data bits. Table 11-2 shows the WBus pin location and VTERM
for each of the WBus byte parity bits.

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4
H
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V
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W
O
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a , fi , SIHILVY - OWISNO4S"IY
EBOX

dVHLOUDIW

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X083

11-2

EBOX

NOuy L <00'1€>0SNEdO |

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11-3

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X$O038Y4{Lov4) vV.rHxLo‘h7Lzov4)(€f£l0v‘dZO0vs41HLTiLAavL4v3e83 ZSi|vnv4adLdm0HSM“4VHHLdL1OeTLl<0:€>H

Snam a <0 L:LE> H

Y407 e— |

SNEMSnamSHAY3SHAVI

avad | ] | dS/HdD

X084

B
LRLGL-HW

WBUS

EBOX

11-4

XCE0R8C3]dS/qdQ9a_|_AJ‘UdSHdovSNEMSHOV3I

bSNEMSHAVI do 4dQd1VOW\mW_| ] 204X081

1SNEMS934 ' (383) L, (w'e,dal)

HOY 3 _

,
HLT ,

| Hi1 SNEM1E>0<D0H SNEANI {1383) g! lz'1dail | WMLHiT|
X083

WBUS

EBOX

11-5

X0H1-IOvN8S1Id3NY

TM~

Z@=a-nTb1ta

EBOX

WBUS

FBA L0212

(FTM, L0223 TERMINATOR ONLY)

SLOT 8

VTERM

% L &2

(FTMa, 5)

FA24, 25

EBE L0219

SLOT 9

EDP L0209
SLOT 10

EDFA B

- 32
)

LTH

(SOP3) FAQ2.3

(SHFG) EDPA, 8

PC/PG

SEE

| —EBE WBUS OPAR B<3:0> H

NOTE

rae

EBE WEBUS OPAR B<3:0> B H

4;4 c !

EBE WBUS OPARB<3:0> CH

FA12

VTERM

FAZS

{FTMB5)

EBE WBUS OPARB<3:0> AH 4,

EBEE

P—

VTERM

EDPM

EDPY
ME I5850

Figure

11-3

WBus

Physical

Distribution

11-6

(Sheet

EBOX
WBUS

MCD L0204

IDP LO206

SLOT 16

SLOT 14

VTERM

‘

IDPB, C

LTH

(IAD1) IDP1.2

‘

LTH

(::]
B

VTE!RM

MCDW

MCDV

LTH
VTERM

IDP8

IDPC

ME-15851

Figure 11-3

WBus Physical Distribution
(Sheet 2 of

11-7

EBOX

WBus

Signal

11.1.1

WBus

Location

Signal

Location

Table

11-1

WBus

Signal

Location

WBUS

D<31:00>

VTERM

EBE

Signal
Name

WBUS

D<31:00>

EBE

FBA

EDP

IDP

VTERM

WBUS

DOO

A09

Al0Q

v$0230

WBUS

DO1

Al0

A63

A45

A64

V$0151

Al5

v$4188

WBUS
WBUS

D02
D03

co5
C57

A64

CcCo6
C58

A83

v$0263
vs0267

A21

v$4178

WBUS

D04

Co6
Cc58

All

Cc27
C69

Al2

A25
A3l

v$0294

vV$4191
vVS4194

WBUS

Al2

D05

A27

A65

A45

A66

V$4177

v$0345

A66

A67

A53

V$4158

WBUS

D06

co7

co8

WBUS

v$0197

D07

C59

co8

C60

Cll1

v$0272

C60

C55

A63
A7

v$4182
v$4184

A25
A65

A47
AS57

V$4202
VS$S4276

WBUS

D08

Al7

AlS8

WBUS

vs0268

D09

A75

AlS8

A76

v$0273

A76

WBUS D10
WBUS

Ccl1

D11

Cl2

Co64

v$0341

Cl2

V50288

Co09

C64

A67

Cc51

V$4274

C75

V$4122

WBUS

D12

Al9

A20

v$0231

WBUS

A20

D13

A49

B09

B32

v$0238

V$4245

A78

A87

B15

v$4244

WBUS

D14

C39

C40

v$0287

WBUS

C40

D15

Cc31

C69

B21

C70

v$4243

vsS0270

Cc70

C73

B31

V$S4247

WBUS

D16

A45

A46

v$0239

A46

WBUS

D17

A47

B49

B45

A89

v$4128

v$0117

B52

WBUS

A85

D18

B53

B57

C17

V$4127

v$0262

B54

C29

B69

WBUS D19

Cc73

C74

WBUS

D20

AS3

A54

WBUS

D21

A83

A84

v$0177

C74

v$0104

vs$01l67

B77

VS$4157

A54

A29

C09

Vv$4253

A84

A69

C19

VS$4266

WBUS D22
WBUS D23

c41
Cc77

Cc4?2
Cc78.

WBUS

V80196
V$0176

A55

C42
C78

A56

v$0107

Abb

D24

WBUS D25

A85S

A86

vV$0150

v$4131

c71

C1l5
C57

C25
C35

A4l

A86

V$4252
V$4251

C07

A81

v$4256

Cl7

V$4271

WBUS

D26

C45

C4e6

vs$0199

WBUS

D27

C46

Cc85

C25

C86

c27

v$0200

V$4257

Cc86

cé67

Cc37

vS4107

WBUS

D28

AS9

A60

V$0105

WBUS

A60

D29

A3l

A87

C45

A88

Cc51

V$0166

v$4223

WBUS D30

C52

A88

v$0175

A71

C52

C53

Cc1l7

v$4227

C65

v$4231

Cc87

C88

v$0201

c88

Cc59

c77

V$4232

Parity

Signals

WBUS

D31

WBUS

Signal

-EBE

WBUS

Table

11-2

Distribution

Name

OPAR

EBE

A52

EBE

WBUS

OPAR

AS57

EBE

WBUS

OPAR

A68

EBE

WBUS

OPAR

A71

-EBE

WBUS

OPAR

A62

A73

EBE

WBUS

OPAR

EBE

WBUS

OPAR

A69

EBE

WBUS

OPAR

A67

MCD

WBus
16

EDP

Byte
10

IDP

FBA

B32

Vterm
V$2113

C78

vVs$8157
A4l

v$4209
A75

B25

v$0180

vV$2125

Cc89

V$8154
A40

V$4210

A85

11-8

vs$0129

EBOX

WBus

Table

fi%é

11-2

Distribution

WBUS Signal Name

BO07

EBE

WBUS

OPAR

EBE

WBUS

OPAR

Bl8

EBE

WBUS

OPAR

Bl12

WBUS

OPAR

Byte

Parity Signals

Location

(Cont.)

EBE 09 MCD 16 EDP 10 IDP 14 FBA (08 Vterm

’ _-EBE WBUS OPAR B2 H

-EBE

of WBus

Signal

B27

BI10

WBUS

OPAR

BO0S8

WBUS

OPAR

B15S

EBE

WBUS

OPAR

Bll

v$8156

A49

vS$4123

A83

B04

EBE
EBE

v$2127

C85

v$0131

B30

V$2126
C80

v$8155
A39

VS$4205

A57

v$0186

NOTE

The

defined

visibility register
"B-side" of the WBUS (that
IDP module).

the
the

11.2

EBOX GPR/SCRATCH

Table

1l1-3

shows

the

"WBUS",
801A
is
is, terminated on

PAD USAGE

usage

EBox

GPR

Scratch

Pad

registers

the KA86.
If a more detailed listing is needed, refer to
in the EBox microcode listing, KA8600.MCR or KA8650.MCR.

| There are a total of 256 32-bit registers,

with

two

DEF.MIC

copies

each
to
provide
redundancy.
If there is a parity error in the
"A" set of the GPRs, the "B" set can be copied into the "A" set.

Table

11-3

Usage/Assignment

EBox GPR/Scratch

Pad Usage

Scratch

Adddress(es)

Pad

(EXAM/ESC)

General Purpose Registers

RO - R11

SP
Temporaries

Secondary

Temps

14
- TI1F

or Misc

Constants

Block

CSM
.

Zeros

Registers

Extra

Temps

/ KA86 Status Registers
VAX Architectural

DSM Mnemonic
Microcode

0 - 11

- AF

Co0

- C8

BF |

CF - DE

Registers

names

Stack

11-9

- EF

EBOX

EBOX MICROWORD

11.3

EBOX MICROWORD

A worksheet is provided for the EBox
microweord,
£followed
by
a
description
of the EBox microword.
The physical bit numbers are
determined by the RAM chips on
the
CSA
and
CSB
boards.
The
logical
bit
position
1is
the
bit
positions
as they would be
displayed for an E/ECS "Adrs" Console command.

11.3.1

EBox Control

Store

ADDRESE [HEN

DATA [HEX)

EBOX CONTROL STORE MICROWORD

{ULD FORMAT)

MICROWORD 8175 <91:00>

EXAMINE FROM CONSOLE >>>E/£CS ADDRESS

CSA CSB
91

SPARE <05:00>
05,

§
78

UMISC <03:00>

upT <0100

iéggf;a}

l
60

i
5%

i
45

i
i1

l
44

ki)

29
USMI

i
71

i
57

i
43

l
56

i
§9

]

l
40

l
28

UBMx

UAMX

i
£7

i
37

I
36

USCK <02:00>

UDEST <0500

jei]

UBRCY <07.00>
3

UYMOK<01.00>

83,

€8

§3

UMISC <03.00> l

UMCF <05:00>

UPAR <01:00>

UMARK

i
55

ULITCTL <01:00>

UBRCZ < 05:G0>

USRCI<07.00>

UFBOX <01:00>
F

l
72

UDEST <05:00>

ULIT <05:00>

UDPSEL £01.00>

l UCCSYNG UH(}DESTI

UCCK <03:00>

i
22

UALU <04:00>

UBEN <04:00>
i

]
%
UBEN
<04 00>

Figure

H
14

i
13

I
12

i
11

i
10

i
09

l
08

11-4

]

‘
LLIUMP <12:00>

UsSuB<0100>

EBox Control

[

Store Microword Worksheet

11-10

EBOX

EBox
EROX CONTROL STORE MICROWORD

Control

{ULD FORMAT}

Store

MICROWORD BITS <9180>

EXAMINE FROM CONSOLE >>>E/ECS ADDRESS

CSA.CS

SPARE <05.00>
05,

04,

03,

] UCCSYNG | UNODEST|
,

UMISC <03 00> l

0,00

UPAR <01:00>
21

PHYSICAL BIT NUMBERS

Figure

11-5

SPARE

FIELD

The

SPARE

are

EBox Microword

field

bits

(microword

contains

the

each

<85:00>)

<91:80>

free

bits

EBox microword.

are

used

control

the

microword.

Currently,

the

EBox

only

and

There

bits

the

PSL

CPU.

UCCSYNC<00>
The

MICRO CONDITION

condition
it

can

codes

use

the

are

CODE

SYNC

valid.

The

condition

codes

field

IBox
for

1indicates

uses

this

that

field

know when

branching.

UNODEST

This

field

notifies

the

hardware

that

the

EBox will

request

the

WBus.

UPAR<01:00>
The

MICRO

UPAR<K1>

PARITY
and

field

contains

UPARKO>

cover

the

parity

mutually

for

the

exclusive

sets

microword.
in

the

EBox

microword.

UMISC<03:00>

The

MICRO

MISCELLANEOUS

functions
which
for control.

not

field

require

provides
the

those

assignment

miscellaneous
an

entire

umisc
=

FBENER
810

@ |MOP

[

@ |SET PSLCFPD)

@18 |1 [CLEAR PMEM-GPR LRITE AND 10 READ FLAG

T JCLEAR PSL<FED>

]

@ |ENRBLE ERROR UTRAP

T IGISABLE EEROR UTRAP

]
]
o] 3]
o]
1] G0
wef e

O
e

]

e
e

]
]

P
OO

]
]

DO
(O
L

man ] n]

,mew;w

@ |Sc7 SIATE MODIFIED FLAG

T |CLEAR STATE MODIF
[ED FLAG
@ |IB0X.STHLC STHC WI11H 180X BFIER FLUSH
1

|FER0 EXTEMD 1 BTIE AT ALL BH.2ER0 Blisc3i:8>

@ |2CR0 EXTEMD 2 BYTES AT ALU B.2ERO BI15<31:167
T 12500 EXIEMND 3 O77TES AT AL B.£E30

-] {EfiEéx FOR INTEGEZ OVERFLOU

BlTa<d1:84%7

T UMW
IND BL0G

¥ |ENABLE FORK TRAP

7 (DIAGNOS; IC RESE] 10 EBDOX AND MBOX INITIALIZZ |

11-11

field

EBOX

EBox

Control

Store

EBOX CONTROL STORE MICROWORD

{ULD FORMAT)

MICROWORD BITS <7984>

EXAMINE FROM CONSDLE. >>>E/ECS ADDRESS

UMISE <03.00>
01

CSA CSB

UnT <0100>

[

UCCK <03:00>

UFBOX <01:00>
S

]

UMARK

UMCF <0500

PHYSICAL BIT NUMBERS

Figure

11-6

EBox Microword

<79:64>

UDT<01:00>
The

MICRO

data

DATA TYPE

type

1is

field

wused

for

the

EBox

condition code functions.
the instruction dependent

1If
data

EBox

data

type

initiated

data

type

must

specifier.

memory

OCTA or
be

The

references

QUAD

and

desired,

used.

-!-«m[m

1 JUSE

UCCK
The

INST

DEPENDEN

NTEXT

<03:00>
MICRO

CONDITION

microcondition
values

for

CODE

codes.

field

controls

the

following

condition

ALU.x

JOOK

le3lezlai[eal _ PSL.N

PSL.2

81418 |8 ALL.MUDT)

@18 11 JALL.MUDTS

8l21

PSL.N

ALLU.N(UDTY

PSL.V

| ALU.XLwDTI

aLU.2CUbTH

PSL.2

PSL

table,

and

the

current
latched from

PSL.C

1 @

ALU V(UDT )

PSL .V

| ALU.2CDTS

the

code

are a function of the ALU result in
cycle and are independent of the UCC condition codes
a previous cycle.

FSL.C

NOT .aLlu. 2CUbT)
PSL.C

| 8

NOT.ALL.CLLDT)

LU
. VeUpT)

@1118 (8 BLU.MUDTS | ALU.ZXUBTS 1 8

@171

18 (1 |ALU.NCUDTS | ALU.ZUDT) | ALLU.VC(UDTD

@111
@11

1111

IRLU.NCUDT

aLy.2eueT)

PEL.N

PEL.2

11810

IPSL.H

PEL .2

1108189

PSL.N

PSL .2

1{8 (1

ALU.MUDTY

| BLU.8(LDbTT

11811

IRLU.NUDT

aALLLL2CUDT S

[LOAD

BLU.VCUDT 2
1

AaLU.CLUbTYy
NOT .ALL.CCUDT S
PSL.C

NOT .ALU.ZCUDT01 PSL.C

PEL.V

BEL.C

| BLU. V(DTS

PSLLY

PSL.C

PsL.C

LAND
PSL .2

1111819
T

111811

THE

BMX

CONDITICN CODES AMD WREGCI1S BRANCH

|[LORD

THE

UCL

CONDITION CODES FROM ALLU RESLLIS

1111

IL0RD

ALl

THE

MICRO

011111

|LOAD

THE PSL COMDITIOM CODES FROH

UFBOX

The

CONDITION

CODES

(BOTH ULL

anD

AHxX)

THE E-80X

<01:00>

MICRO

FBOX

operations

with

field

the

FBox.

used

control

and

synchronize

EBox

UFBOxX

a1]ee]

]

UMARK<00>

The

MICRO

microcode

MARK

field

to assist

wused

for

setting

in micro program debug.

11-12

breakpoints

the

EBOX
EBox

Control

Store

FUNCTION
field
specifies
a
CONTROL
or a register select function <02:00>.

UrMCF
¢

]

|READ.VA.SAV
A

VIBAEAT

gie
RERL
CREBERE

CRCRERE
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aiti118
BB

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gAY

MICRO
MEMORY
function <05:00>,

..‘.._....‘_..............;.m..fl.fl....M““mm‘mmmwmmmlmmmmmmmmu,...........‘...‘..:“—.-u.‘...m_.

THE

[P QS QU QR

UMCF<05:00>

|REZUELUE
.OP .NDPAGE

.V LCHE

.V .HLHK

URITE .V.5IRING.SEC
.REF
LRITE.ECOY

WRITE.V.S5z(C .REF

WRITE

.V .NOPARGE

WRITE.P

LRITE .V.SIRING
WRITE
.V .NCHK

.REX
.OP UE
[REGUE

11-13

memory

EBOX

EBox Control Store
(ULD FORMAT)
EBOX CONTROL STORE MICROWORD
EXAMINE FROM CONSOLE: >>>E/ECS ADDRESS
57
58
59
&0
61
82
83
UuT <05:00>
UOPSEL <01.00>
UMCF

00 [l , 00 05 . 04 , 03 , 02 . 01 R 00

<{500>

53
54
ULITCTL <01:00>

50
51
USCR <0200

01 ; a0 g2 . ikl
30

MICROWORD BITS <83:48>
CS4 C58
48
49
UDEST =205 00>

o0 I 05 . 04 l
47

PHYSICAL BIT NUMBERS

EBox Microword <63:48>

Figure 11-7

UOPSEL<01:00>

The MICRO OPERAND SELECT field is used to control the
data the IBox will transfer over the OP Bus.

source

UOPSEL

|18

(@ |9

REG

% OF

[T] 7 [OPERANG _

UNCF<21@>

LREGSEL

SELECTED

@1 [END
BYTE 'T :i‘

fit

I
N
D BY UMISCC1:185)

-£

ULIT<05:00>

provides

field

LITERAL

MICRO

The

configuration of the ULITCTL field.

the

values

for

each

the

MICRO

ULITCTL<01:00>

THE MICRO LITERAL CONTROL field controls the

g —
Y
QU
(R

K]
K@) O

@) K] -] @)

LITERAL field.

ALU R

©f =

wf -

RIGHT

ALU LEFT

RS R

LEFT

24
HT 1,
IFT

iN?UT 1
INPUT @

2,
1,

INPU

INPUT 11

(OR CVTZP)

VIPN

]

€ FORMAT PALK—
LISE LIT FIELD AaS SHIFT

C&fl?tkfi?fifi LEFT

2 W 83 FL&EES

IELDS4: 8>
Ui
TQ SELE%:T THE HARDUARE REGISTER
TQ BE URITTEMN

OVER Ti-E W EGS
8
IELDC:
Ul
TO SELECT THE HARDUARE REGISTER
TO BE REARD

OVER ?Hfi u Bus

ROL IF Lfi.ET(E)sfi

T&H TH£ FEOY UILL SHAELE

b <

Qfi’{fl THE g_;gug

BOX RESLLT paTal

BOX CQ?&TRGL IF WIT(R=1
ySc.D F
THEN EBOX WILL ENABLE DATA ON WBUS

'to 8 GIVEN TO FBox (FBOX OPER DATAD

+ FORMAT PalKe

figf@f?fi&fififi?fi?fi&%fi?fi?

fif-&D STHC. THEN USE ULIT(4:8> AS MEM

'PC FOR FBOX MICRO SEQUENCER

11-14

use

EBOX
EBox

Control

Store

USCK<02:00>

——

fiw“'

The

MICRO
SHIFT
COUNTER
CONTROL
field
controls
functions
involving
the
SC
and
STATE
registers.
Incrementing
or
decrementing the SC, and loading
the
SC
from
the
ULIT
field
affect
shifting
operations
1in the current cycle.
Branch tests
always

use

beginning

the

value

the

c¢ycle.

UsCK

22101100
CRE]

,
CECRENEN

REGT

|IMCREMENT SC REGIGIER

2|1

ILOAD SC FROH AR BuS

2111
1

1917

|LORD STATE FROM AR BUS
|LOAD

SC FROM NVi,

|L08C SC FROM

WV2,

OVHER 8175 GET @

OTHER B115 UNAEEECTER
—

INOP

11111

JLORD SC ERDA ULIT<%:8>

11118

11-15

STATE

registers

the

EBOX

EBox

Control

Store

EBOX CONTROL STGRE MIGCROWORD

(ULD FORMAT)

EXAMINE FROM CONSOLE >>>E/ECS ADDRESS
47

MICROWORD BITS<47 32>
CSA CSB

UBEST <08 00>
03

Figure

USRG? <0500

PHYSICAL
BIT NUMBERS

11-8

EBox

01
i

Microword

USRCY <0700

<47:32>

UDEST<05:00>
USRC2<07:00>

USRC1<07:00>

The

MICRO

are

used

Also
and

SOURCE
to

the

EBox

UDEST

MICRO

fields

pointer

LOGICAL RES.

|80

ElB|EIX
|8

DEST.

6|18

[

zifieém A

CCEEBEICEEIRRLL

SOURCE

|PUSH RLGTP]

GBI

{Xi11

1|8

IX1i

fEAD B

|[READ &

pl1|@j@jaf1]1]i3

1%
5

1118

1181811111818

1id

BERERERCRERRE)

Ti@]118@

AE)

)

1118

I
ic

Ti@j1

T3]

111811110

BEEERERERERS

‘

17E

ilijej@je

@d|i@

111181818

111711

Tlijelelii@|rig

USRC1¢7:8)

4713

T1118

[Ti%

1{1

|PUSH R[S5TF
3

F 7 SiP¢3:87

71118111118

|[READ A

USRCi(7:85

T11]8]1

|READ B

B | USRL2{5:87

t{1Tj1j@(a|a|re

IRERERECRCRERR

NERERCEEREACE

)

17181111183

11111

1@i@

[RS

E]
]

ENEEERERCECIE

5
E

Nea

USRC2<5:8>

(RERE

11y

Ti@li1i18|@1iC

SPROR(3:8>

BERERERERERED]
1

1111

SiE<a:
ey

18
71

|@]ie

T1811.@

ND
L DEST

IF UDEST<S2=@ THEN USE UDEST<3> WITH USRC2¢1:8)

USRE?

B: 0

DECODE

ONE

THE

RELOU

FUMNCTIONS

FOR SPADE OR

1:4

BIX|[X[X

BIX

|[MCRENMENT

X187

XX}

BIX|BIXIX

|DECREMENT SPADR
T

Blx|1

XXX

1818

@IX

[AIXIX

!
!

;

SPADA

i8L0AD SPADR FROM ALUCT:
B>

IRV

STP

ERCNICEIEHENECIEREE]
DX

USRC2{5:8> SPADR<3: 07

nilejgjg|aja|rd

CRAL)

JUSRCICZi4)

USRE1<{7:a>

ofvja|eja|e|i|T1

1718

,
!

SPADRC3:0> | SPADR<3:@>

USRC2¢5:2> !
1

glijejajali

Bil

SPADR

USRLCI1C/
147 SPADRC3: 87

|87 [NO.0EST

RAN B ADDRESS

SOURCE

UDESTL1:8)

(X7

RaM A ADDRESS

DEST.

manipulate

gajiixjejiieiiz

fields

addressing.

UGRC2<(B:25 GPADR< 3:85

f:s NESCEANANAEN

functions

USRC2¢5:2>

Bix 111111 REAG B
moli|xjela|e|ie

Ti8

DESTINATION

destination

PHYSICAL REG.

@TUSRC1<3:8>

Bdl1ig

are

MICRO

and

THRU TIF

RERE

1X|118]0

and

BLARNURLEC UM
X111

source

(STP).

|8 |Re THRU RIS

ofgle(x|eje

811

SOURCE

scratchpad

these

stack

CEIEEICHER

mel@|Xx

control

encoded

I0R

INTO SPabRias

HOP

|LORD SPRADR FROM

10GPR

|8 | INCREMENT STP (STRLCK

POIMIERD

|1 |READ RLFS1P<1:3>1 AND DECBEMENT 37TP. POP STACK

11-16

EBOX

EBox Control Store

(ULD FORMAT)
STORE MICROWORD
EBOX CONTROL
EXAMINE FROM CONSOLE >>2>E/ECS ADDRESS
27

YSRC1 <07:00>

ySMi

UVMOK<01:00>

01 ) 00

UBMX

UAMX

4 i
70

UALY <04:00>

03 i u2 i of
7

04 3
18

MICROWORD BITS <31:16>
CSA CSB
17

UBEN <04:00>

03 i
18

02 4 o1
17

PHYSICAL BIT NUMBERS

EBox Microword <31:16>

Figure 11-9
SMI<00>

The START MACRO INSTRUCTION field is used to indicate the start
of a new macroinstruction. It is asserted low in the first cycle
of a macroinstruction, and deasserted at all other times.
UVMQK<01:00>

The MICRO VMO REGISTER CONTROL field
shifting of the VMQ register.

D
ALU RESULT
T1LOA

the

and

,H aLll.C.3t

]

controls

UBMX<00>

The MICRO B MULTIPLEXER field selects the scratchpad location
addressed by RB if "O" or the OP Bus (if "1") as the B input to
the

ALU.

UAMX<00>

The MICRO A MULTIPLEXER field selects the scratchpad location
addressed by RA if "0" or VMQ (if "1") as the A input to the ALU.
UALU<04:00>

The MICRO ARITHMETIC LOGIC UNIT field specifies
arithmetic or logic operations for the ALU.
uaLU

[@9| OPERATION
loula3/e2l01

LOGICAL

81010128 |R.AND.G

CARRT/-BORROU
X

%
X
X

8T89 (8] |A.XOR.3
CREAEREBEN]
316 8 1|1 |A.0R.B

? a%fa""‘.auo’*",mo?.a>

CRE

gieli

(1|1

101

[KNOT.A).AND.B
BRITHNETIC

Bl
BiT

- 2N

f“fi”’?“i‘e‘“}‘eDIVIOE R+rB

+@
)

10188 A+
e l8]1l A2

@1 (0|18 [a+p KORRECT (BCOD)
gai111811

g1T17i8/@8

81111

18]1

itoad,

|A-B

- HgT WCC.C
~PsL.C
PY:)

gii 1118 |a=8
231111111118
T T8 1810 a8
Ti@

]

@110

(A8

71718188

|A+8 (BLD)

TTT

19 |A-8 (BLD)

T8
T8

o
o

TUct.¢
*PSL.C

171 0 |A+8 (aCo)
7 |1 |A+8 (BLD)

T 114111811 {8=8 (800>
711111118 |A=a8 (BLD)

=25 .0

|A*8 (BLD)

TTT

TNOT UCC.C

1B=-9

TTT
TTT

=1
)

11110 8-a8

118111111
TTT

TUCC.C
+PSL.C

18 8

71818111 a8
T8 11180 |B-A
Tigit 18ttt |B=n

1717 [A-a8 (8Ch)

)

=@
- NOT LUCC.C

~PEL.C

11-17

any

one

EBOX

EBox

Control

Store

EBOX CONTROL STORE MICROWORD

EXAMINE FROM CONSOLE: >>>E/ECS ADDRESS
15

UBEN
<08:00>

(ULD FORMATD

MICROWORD BITS<15.00>

CSA.CS

o708

11-10

EBox Microword

)
,

PHYSICAL BIT NUMBERS

Figure

.
UJUMP <12:00>

USUB<O1:00>

0504

<15:00>

UBEN<04:00>
The

MICRO BRANCH

ENABLE field specifies one of
functions.
Each
branch
enable
can

enable

branch.

the

The

results

are ORed

into

the

uPC.

three

23 possible branch
provide
an 8-way

low—-order

bits

UBEN

[ev[e3[@2Tai[ee]
gjeje|e|el

dle|a|8

DIAG. MODE OMLY

1181

ONLY IF "EDPETM AND STATE = 2

upc c2>
]

UCC.N
ARG

11818

C
@i

Tl@

1|
11181

gigj1

uPC <@>
t.C

Ucc.2

DIAGT

118 | a.RAn.PE

elele|1]1]

uPc <1

uce.2

EsavaLip
OPCODED

sC.0.9

-RAM.PE

ucc.c

PaL.2

PSL.C

1sA.vALID
OPCODET

| URWING.BOE
| OPCODE®

BE
1

}

]

11118
IRERERT]
111

;

)
i

BERE
1

[

TielT

1 3¢

NERE

)

11
T

H
CRERE

gi1

1111811

111
1@ |1
1111118
¢

ERE-EE

IREERERERE:]
TR

EREREE

]

=x GEMERATES THE SIGMAL

IRD

USUB<01:00>
The

MICROSEQUENCER

formed.

UJUMP

CONTROL field specifies how the

uPC

will

<12:00>

The MICRO JUMP
Depending
on

that get
ORed
microaddress.

field generally

specifies the
next
microaddress.
USUB field content, there are other components
with
the
UJUMP
field
to
produce
the
actual

the

11-18

EBOX

EBox Context

11.3.2

SDB, and
The Context RAMs are loaded by the console over theFigure
11-11
contain native mode instruction dependent contexts.
| shows the format of the Context RAM microword. Table 11-4 lists
the bit description for the context RAM.

BATA {REXS

ABDRESS (HEX

llll

| |

EBOY CORTEXT [T MICROWORD

MICROWORD BITS <0300>
EBC 4

{ULD/PHYSICAL FORMAT

EXAMINE FROM CONSOLE >>>E/CTX ADDRESS

‘j

CONTEXT <30
g

Figure 11-11

]

the

EBox

EBox Context (CTX) Microword Worksheet
Context <3:0>

RO
L
W o

Wowonouwon

Table 11-4

Byte

Longword
= Quadword
Octaword
Word

Memory Control Function (MCF)

11.3.3

lookup

The MCF RAMs provide a

table

decode

MCF

The RAMs are addressed by the uMCF field, and
microcode field.
The decodes
are loaded and verified by the Console over the SDB. EBox.
Figure
provide various control functions throughout the
11-12 shows the layout of the MCF microword, and Table 11-5
contains the bit descriptions for the MCF RAM microwords

DATA {HEX)

ADBRESS {HEN

EXAMINE FROM CONSOLE >>>E/MCF ADDRESS
15

WRITE

—ACK

CHECK | REQUEST

£N

MBOX

Figure 11-12

2&5;

SARITY

WMICROWORD BITS <1500

(ULD/PHYSICAL FORMAT

£ROY MEMORY CONTHOL FIELD {MCF WMICROWORD

~LGAD

!:AGAD
"

~REQUE%§ERifi&}EUE flCLEAg

REQUES? REQUEST fig;

MCF Microword Worksheet

11-19

GL£AR

STNQS

ngfii £AR

giSP

;

—MEM

REQUEST

WRITE

- 0P
WRITE

HE?{}

EBL 7-A

EBOX

Memory

Control

Function

Table

<15> WRITE

(MCF)

11-5

MCF

Microword

CHECK

= This bit is
memory command for

specifies a
performed.

Bit

Description

asserted
which

write

the

uMCF
field
checking is

access

<14>
will

-ACK REQ - The default for this bit is no ACK
be asserted (low) for those encodings of the
for which EBox PA ACK is expected from the MBox.

<13>

EN MBox

This
bit
activity.

will

set

provokes

MBox

<12> MCF

PAR - 0dd parity over MCR RAM

for

any

-LOAD NEXT REQ - Asserted (low) for those
which must be loaded into the Next Register.
<10>

-LOAD TRAP
commands

which

<09>

-REQUEUE

NEXT REF

REQ

EBox

uMCF
field
Reference function.

<08>

REF

EBox

-CLR

Requeue

Port

11.

12.

code

the

-~ This

the

(low)

the

EBox

asserted

will
of

IBuffer

Port

asserted

Reference

IBuff)

=-REQUEUE

during

Requeue

the

the
Next

specifies

(low)
or

reset

1if

Port

bit,

those

(low)

Requeue

low

for

Trap

asserted

commands

the

Operand

memory

port

port.

bit will be asserted (low) if the uMCF
Requeue Operand Port Reference or Requeue

the
PORT

with

port

Cross

Page

Boundary

Checking

status.

<05> =-CLR EB PS - This bit is
asserted
(low)}
if
the
field
specifies the Clear EBox Port Status function to
the EBox Port status latches.

uMCF
reset

<04> E DISP I - This signal is asserted
if
specifies
the EBox Dispatch IBox function.

the
uMCF
field
This function is
microcode to test the IBox.
The IBox will
dispatch its microcode based on the contents of the
EBox uMCF
in the microinstruction tollowing the
microinstruction
that
has a uMCF equal to E DISP I.
by

diagnostic

<03> -MEM
encodings
are

REQ
of

the

This
uMCF

expected

from

<02> MEM WRT - If
for
those
uMCF

-MEM

<01>

-OP WRT

specifies
16.

the

that

- This

commands.

15,

into

uMCF

the uMCF field
Reference function.

bit

behalf

asserted

bit

- Another

Buffer

Reference
OP

This

Trapped

(on

for

Port

reset

RESP

14.

<06> -CLR OP PS
field specifies

used

13.

loaded

asserted

Instruction

Operand
to

Port

Reference

status

10.

will

bit

specifies

-REQUEUE TRAP REF

TRAP

REQUEUE

<07>

This

must

uMCF

field.

<11>

UMCF

REQ,
It
uMCF field

<00>

field

the

This

OP WRT

Operand

Port

STL

the

Write

the

is
asserted
(low)
for
which both EBox PA ACK and

MBox.

REQ is asserted,
encodings
that
are

bit

Operand

specifies

bit
for

Port

asserted
Write

This signal
Operand Port

Stall

(low)

bit will be
set
PORT memory write

the

uMCF

Function.
is

Write

function.

11-20

this
OP

those
EB MD

asserted

function

the

field

uMCF
Enable

EBOX

EBOX MICROTRAP VECTOR ASSIGNMENTS

11.4

EBOX MICROTRAP VECTOR ASSIGNMENTS

The EBox Microtrap Vector assignments areée listed in Table 11-6.
Table

11-6

Vector

Microtrap Condition

FBox Problem

EBox Microtrap Vectors

Action

The

FBox

service

determines
if
an
error occurred and

routine

FBox
if so,

request

for

FBox

EHM.STS,

then

it passes

hardware
sets the

service

control

EHM.

MBox Error Register

The MBox
it

interrupts

latches

the

MBox

EBox

error

when

address

register and wants it saved.
EHM
reads
the
register and places it
in
scratchpad
MEAR.SAV,
calls
interrupt
code, then
rolls back

pending instructions
at PC interrupted.

Interrupt

and

restarts

Interrupt requests are filtered by
EBox hardware and the request with
in
1latched
1is
priority
highest
to
microtrap
a
and
CSLINT
interrupt microcode is
generated.
If the IPL is 1D then the MBox has
latched

microcode

Interrupt

error.

notices

fact and

this

sets
EHM.STS
<07>,
service
request
and

the
MBox
branches to

EHM.

EBox Hardware Error

When the EBox detects
a
hardware
error,
it
latches
the reason in
EDPE
and
EBCS
and
generates
microtrap at vector 8.

MBox TB Error

When the MBox

MBox Fatal

Errors which

Error

detects

problem

with
the
TB
during
EBox port
requests it reports the event with
a
Port
Status
Code
=
8
and
destination code = 2.
The
error
is serviced by EHM.

cause

unpredictable

results
in
the MBox for any type
of request
are
reported
to
the
EBox
the
same as EBox errors are
reported.

IBox Hardware Error

IBox hardware error is

latched

in
the
1IBE
and the IBox stalls.
ORed
1IBox
errors
form
an
IBox
microtrap
request,
if
E
ENA 1is
set.
Ebox hardware
services
the
request
when
it finishes current
execution
and
attempts
to
get
operands from the IBox (fork).

11-21

EBOX

EBOX MICROTRAP VECTOR ASSIGNMENTS
11 - 17 MBox TB Error

If the MBox
returns
an
OP
PORT
status
code
of
other
than
no
problem
for
a
memory
request
issued
by
the
OP
PORT,
the
microtrap vector will
be
in
the
range
of
11 - 17, with the least
significant bits being supplied by
the
least significant bits of the
OP PORT status latches.

when IBF PE, DRAM PE, or R-MODE PE
is
detected,
the IBox stalls the

IBox Hardware Error

IBUF PORT,
and
sends
the
error
flags
to
the EBox where they are
latched
in
1IBE.
If
a
flush
command
is
executed
before
the
EBox forks
for
an
operand,
the
error will be cleared.
Otherwise,
it will be reported
through
this
vector.

19 - 1F MBox TB Error

If the MBox returns an
IBUF
PORT
status
code
of
other
than no
problem

for

memory

request

the
PORT,
IBUF
the
by
issued
microtrap vector will
be
in
the
range
of
19
-~
1F.
The
least

significant
bits
of
the
vector
will
be
provided
by
the
least
PORT
IBUF
the
significant bits of
status latches.

IBox Sync

After the EBox flushes and
starts
the IBUFF, it stalls until the CPC
is
wvalid.
CPC
VALID
indicates

that
a
new
macro instruction is
being processed.
If an IBox error

occurs
which
inhibits loading of
CPC, a microtrap will be generated
through this vector.

11.5

Unwind Rlog

EHM

FATAL

ERROR

If an IBox error occurs during the

RLog
Unwind
command
reported through this

it
will be
vector.

LOOPS

When EHM detects a condition which

it can't handle or

report

another part of microcode, it branches to a sunset loop and waits
for the console to detect a Keep Alive Ceased condition.
Console
software

checks

for

the micro PC'’s

in Table

11-7 and

found,

reports a corresponding message to describe the KAF.
Table
EBox

uPC

11-7

EHM Fatal

Error Loops

Reason

RAM A and RAM B parity error in the same cycle

Multiple EBox errors
entry vector 8)

(two

11-22

errors

detected

EHM

EBOX

CONSOLE SUPPORT MICROCODE

11.6

CONSOLE SUPPORT MICROCODE

(CSM)

CSM utilizes a 32 location section of EBox

microcode

(addresses

1080
109F)
for
the
execution
of
console
commands.
When
required, the console will load the apropriate routine
into
the
the
ECS/CSM
overlay region, then pass control to CSM to execute
the

routine.

CSM.MIC
contains
the
(non-resident)
area.
KA8650.MCR,

resident
CSM
source
code
and
overlay
CSM.MIC
<can
be
found
in KA8600.MCR or

and contains:

DC022 read and write subroutines

Packet read and write subroutines

Command and response read and write subroutines

Certain resident entry points

Command fetch, checksum calculation microcode

Console wait

loop

Table 11-8 lists the special CSM microaddresses, and
lists

the

11-8

Contents

1080
1081

The start of the non-resident section
The restart address of
the
Find 64
Kb
procedures
'

0E30
1005

1000

1001

The jump-dots used to tell
the
console
(e.g.,
finished
have
commands
special
power-on part

and

Find_RPB

that
the

certain
or
end

#1)

The start of the Compatibility Mode microcode
The microaddress to send a l-packet response
The microaddress to send a

The microaddress to
loaded

start

CSM.STATUS

2-packet response

housekeeping

1A7C

The entry into REI microcode,

04D0

The start address of EHM.MREG.RW,

04C2
0041

after

needed for

The start address of PR.INVALIDATE.TB
The start address of MTRP.CACHE.SWEEP
The start address of READ.FBOX.REG

The start address of FBOX.RESET.O
The start address of REQUEST.SOFTWARE.INTRPT
The start

The
The
The
The

start
start
start
start

address of GET.PTE.SUBROUTINE

address
address
address
address

of
of
of
of

GTE.PTE.2
MTPR.TODR.SUB
MTPR.CSL.WRITE
MTPR.CSL.WRITE.1l

0047
0048
0265
0279
09C2
09C4
09cCse

11-23

having

used by the IRD command

The start address of CSM.CNSL_READ
The start address of CSM.CNSL_WRITE
commands

0040
0042
0044

11-9

Special CSM Microaddresses

Address

1087

Table

CSM overlays.

Table

(CSM)

some

CSM

EBOX

CONSOLE SUPPORT MICROCODE

CsM001

Read

CcsM002
CSM003

IRD

IPR

(CSM)

Table

11-9

Group

CSM

Overlays

[KSP,ESP,ssp,UsP, ISP,POBR,POLR,PCBB,P1BR,P1LR,

SCBB,SBR,SLR]
Continue_ Microflow
Examine Ebox _Scratchpad _Register

CSM004
CsSMOO05

Examine Ebox
_Misc. Reglster

[SPADR,

Examine Ibox
_Misc. Register
[EMD,
CPC, I1ISA, ESA, VPCBITS]
Deposit_ Ebox_ Scratchpad Register

CSM006
CsSM007

Deposit “Ebox

csM008

Misc. Reglster

Examine Phy51calCPU_Memory

CSM009
CsSM010
CsMO011
CSM012
CcsMO013
CsM014
CSMO15

STATE,

IBGPR]

VA.SAV,

VIBA.SAV,

[SPADR,STATE]

Flush_Ibox_and_Loop

Deposit Phy51calCPU_Memory
Translate

Test

Find 64kb

Vlrtual _Read

Read Internal Mbox_Register
Read Internal Ebcx _Register
EBCS, EDMS]

[CSLINT,

Write_ Internal Mbox_Register

CSMO16

Write_
“Internal Ebox _Register

CsSM017
CsmMO018

PSL,

[CSLINT,

EDPSR,

PSL,

EDMC,

TODR,-.SISR,

ICR,

IBE,

EBCS]

Clear Internal Mbcx _Register

Translate

CsM019
CsM020
CsM021
CcsM022
CsM023
CsM024
CsM025

Test Vlrtual _Write

Examlne“PAMM_Locatlcn
(and do not

Flush_ IBOX

loop)

Access_IOA

Find RPB

Examine
Read

IPR

ICCS,

Group

[IPL,

PAMLOC, SID,

Read_IPR_Group_2
Read IPRGrnup 3

CsM026

csM027
CsM028

ASTLVL,

CSWP]

[RXCS, MAPEN, PMR, TXCS, RXDB]
[STXCS, PAMACC, ACCS, ESPD, STXDB]

erte IPRGreup 0 [KSpP, ESP, SSP,
PCBB, P1BR,

EHSR,

PI1ILR,

SCBB,

SBR,

UsSP,

ISP, POBR,

SLR]

POLR,

erte IPR_Group 1 [IPL, ASTLVL, SIRR, SISR, NICR, ICCS]
Write IPRGrcup 2
[RXCS,
DFI,
EHSR,
PAMLOC,
TXCS,
PAMACC, TXDB, PMR, ACCS]
Write
IPR Group 3
[MAPEN,
TBIA,
TBIS,
TBCHK,
CSWP,
CRBT]
erte IPR_Group__ 4 [STXCS, STXDB, ESPA, ESPD]
ReadIPRGroup4 [MDECC, MENA, MDCTL, MCCTL, MERG]

CsM029
CSM030
CsM031

CsSM032
CsSM033
CsM034
CsMO035
CSM036
CSM037
CSM038
CSMO039
CsM040
CSM041
CsM042
CsSM043

erte IPRGreup 5

Write IPR
Grcup 6
Clear Maln_memory

[MDECC,
[TODR,

MENA, MDCTL,

TXCS]

RESERVED

FOR

FUTURE

GROWTH

RESERVED

FOR

FUTURE

GROWTH

RESERVED FOR FUTURE GROWTH
PART
1
CSM.ENTRY.PO PART
2
CSM.ENTRY.MICRO
(formerly CSMY21l) Flush_Ibox

MCCTL,

MERG]

CSM.ENTRY.PO

and

IRD without NOPs

NOTE

To determine which CSM overlay was

use
l.

the

Determine

the

Tll memory

address

overlay
number
is
stored
VERSION console command.

last

loaded,

following procedure:

Examine
console

the

TIll

address

command.

11-24

using

where

the

SHOW

the

EXAM

CONSOLE

Example

Convert
the
determine the

11-1

EBOX
SUPPORT MICROCODE

octal
value
to
decimal
CSM overlay loaded.

Determining which

CSM

(CSM)

overlay was

loaded

SPECIFY

>2>>>SHOW VERSION

CSMOVN:013251

>>>>E/U/B
$013251
U 013251 000017

17 (octal)
loaded was

:USE

= 15
decimal,
CSM015.BPN

therefore

11.7

EBOX MICROCODE

LOCATIONS/REGIONS

Table

11-10

contains

Table

11-10

list

EBox

Microcode

EBox

the

microcode

last

CSM

OCTAL

overlay

locations/regions.

Locations/Regions

Address

Contents

0001
0007
000A
000B
000C
000E
000F
0012
0014
0015

Integer overflow trap after IRD
Trace trap entry point
EBox TB miss routine
Memory management faults (Access
violation
or
translation not valid)
M-Bit not set for EBox references
EBox page boundary crossing
Unaligned reference traps
OP PORT TB miss routine
M-Bit not set for OP PORT references
Retry OP
PORT
write
and
OP
PORT
I/0
read

0016

Page boundary

(combined)

001Aa
001D

IBUF

0040

Invalidate

0265
1800~18FF
1AQ00-1AFF
1B00-1BFF
1C00-1FFF

crossing

in OP PORT

IBUF TB miss routine
read

from

I/0

space

TB routine
Routine to fetch PTE from Page
Native mode C and D Forks
Native mode B Fork
Native mode A Fork
User microcode (WCS)

11-25

Tables

EBOX

EBOX UPC TESTPOINTS

11.8

EBOX UPC TESTPOINTS

Table 11-11, a list of the EBox UPC backplane pins, may be used
for scoping or used with a logic analyzer. For triggering, use
"CLOCK5 141 D H" and enable with "LD ENA L".
Table 11-11

EBox Micro PC Testpoints

Channel

Signal Name

Section/Slot/Pin

0
1
2
3
4
5
6
7
8
9
A
B
C
CcQ
CLK

EUPC 00 H
EUPC 01 H
EUPC 02 H
EUPC 03 H
EUPC 04 H
EUPC 05 H
EUPC 06 H
EUPC 07 H
EUPC 08 H
EUPC 09 H
EUPC 10 H
EUPC 11 H
EUPC 12 H
LD ENA L
CLOCK5 141D H

CSB
CSB
CSB
CSB
CSB
CSB
CSB
CSB
CsB
CSB
CSB
CSB
CSB
CSB
CSB

A03.68
C03.06
C03.42
B03.03
B03.48
B03.10
B03.56
B03.06
B03.53
B03.08
B03.54
B03.04
B03.49
A03.94
B03.44

MARK

EBOX MARK H

CSA

11-26

C03.63 or Bl1l.45

:"V"
.

CHAPTER 12
FBOX

OP BUS D<31:00>

WBUS D <31:00>, OPAR B <3.0 >
SYSTEM CLOCKS

[

lm21'

;

CONTROL/STATUS

r“'—]

[ GPR/
/]
SPAD

[]

-—

CONTROL
FROM IBOX

o — CONTROL
\
FROM EBOX

- (] |, sratus
FBBUS D<31:00> > ' l CONTROL
RRC
STATUS
'

TO IBOX

STORE

FBM|

.
3

LAcL |

sos

—* 10 EBOX

Lsorf

|status
TO MBOX

Max]

| roram |

[Wcs

— : FA <31:00>
—

(mce| [msa]

BUS
D

<«

’

s08B

CONTROL

FROM IBOX
CONTROL

" FROM EBOX

L
Figure

12-~1

SDR
FBox

Basic

TO/FROM
CONSOLE

MR-14812

Block

Diagram

FBOX

WBUS

FRACTION

r——'—
ACC

)

]

B-SIDE

ALIGN
NORM

MPIER

]

’Sggggg
PApey
L

peesecy

A-SIDE

unpack|
ALIGN

go—

W——

B-SIDE

| unpack
ALIGN

CONTROL
FBM

sopA | sops | sopc

FBA

CONTROL
STORE

STORE

FDRAM

OPERAND
MULTIPLEXER

‘

[

ADDER

A-SIDE
ALIGN

MULTIPLY

EXPONENT

ADDER
A
I

EXPONENT
RESULT

FBOX
REG'S

FRACTION
RESULT

DIAG

OPBUS
MR-12741

Figure 12-2

FBox Block Diagram

12-2

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Hed

XogdsovJIojUI

Wed
Hed

JHY J4y

B‘WIeWd

40wa8d5

oY Ovd Qv Hed UsW uad

12-3

D'HS8Wd

20 ued HEd

Had

WS NUddYHLPO>HAY<O
wad

dx9
dX9

Wad
wad

B"WOeWd B‘OaW4 wad Ngd

4 20w wed wed

Jud

WadWa4 BOW82N
'WEd‘w ea BNG0N

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'vEd DS

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FBOX

BELEL-UW

wad

a0v w4

4"0D8y

FBOX

FBOX MICROCODE
FBOX MICROCODE

12.1

FBox Adder (FBA) Microcode

12.1.1

ABORESS (HED)

RN | |
BMICROWORD BITS <47.00>

{ULD FORMAT

FEGX ADDER (FBA} MICROWORD

EXAMINE FROM CONSOLE: >>>»E/FBACS ADDRESS
42
43
44
45
46
47
UORTY <1:0>
USEL RA <20>
UWRT

SPAD

]

UHMX<20>

12-4

Figure

12
3

UDRTY <10>

USEL RA <20>

WRT

ggifla

l UK HMX !

1,0

hil

0z
R

]

UJUMP {NEXT ADDRESS) <8.0>
5

UROTK <20>

]

1
05

J
)

MICROWORD BITS <47:32>
FA 18-23
32
33

FBox Adder Microcode Worksheet

(ULD FORMAT)
FEOX ABDER [FEA} MICROWGRD
EXAMINE FROM CONSOLE: >>>E/FBACS ADDRESS
42
43
44
45
48
47
!

UBEN <30>

1,0

{

}

‘

1.0

UAUXK <103 l

UFADSIC

UFADK <1:0> l UBSIDE <1:0> l USHFTX l USOPK <1:0> l UFARAK <10> l UNSIGNIF]
10

]

{

UFADROTK <20>

UEALU <4:0>

UPAR

FA18-23
32

k¥

41
UPAR

UFADROTK <2:0>

UEALU €405

PHYSICAL BIT NUMBERS

UFADSIG

13
LLRETEEY

Figure 12-5

FBA Microword <47:32>

UWRT SPAD<O0>

This bit specifies reading or writing the scratchpad, and has the
0

]

following encoding:

read scratchpad
write scratchpad

FBOX

FBox

Adder

(FBA)

Microcode

USEL RA<K2:0>
This field selects the
following encoding:

scratchpad

or GPR

address,

and

has

= base

address

(30)

for

scratchpad

locations

address

(20)

for

scratchpad

locations

= base address

(10)

for

scratchpad

locations

= base

(00)

for

GPRs

base

address

= GPR/SP

= GPR address

= GPR address = previous address
+1
if
OPBus
otherwise GPR address = previous GPR address

GPR/SP
from

GPR/SP

address

00 -

the

locations

hold

address

the

address
IBox

for

optimized

instruction
1is

wvalid,

UDRTY<1:0>

This
SOPC

field controls DATA READY, DATA
REQUEST,
and
latch.
The field has the following encoding:

holding

the

NO OP

= At

= At T3 predict DATA RDY for F-format, else,
if
1in
range
assert DATA RDY.
At T1, clock the conditions in the FBR

= At T3

assert

DATA RDY.

hold

SOPC

DATA REQUEST

UPARKO>

This bit reflects
encoding:

0
1

the microword parity,

and

has

the

following

= microword has odd parity, parity bit is reset
= microword has even parity, parity bit is set

UEALU<4:0>

COMP.SIGN

SPARE

GXP

DIFF

SUBG

XOPA

02
03
04
05
06
07
08
09
OA
0B
0C
OD
OE
OF

=
=
=
=
=
=
=
=
=
=
=
=
=
=

SPARE 3
FXP DIFF
LOAD EXP
WBUX -> XOPA
WBUS + 1
CLR EXP
LD BYT NORM
CLR XOPB
CLR XOPA
HOLD EXPS
WBUS => XOPB
LOAD 32
LD BIT NORM
LD 80 -> XOPB

12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F

=
=
=
=
=
=
=
=
=
=
=
=
=
=

ALIGN ADD GXP
SPARE 2
CLOCK SELF TEST ERROR
SET DIVIDE BY O
SUM AND LOAD BIAS
SUB AND LOAD BIAS
DIVIDE ADJ EXPONENTS
MUL.ADJ EXPONENTS
ADJ ADD FXP
SPARE 1
SAVE EXPS
SUBF XOPA - XOPB
CLK EXCEPTS
NORM EXPS

12-

This field controls the FXP, GXP, and FBR.
The
following
encoding specifies the related macro definitions:

XOPB

field

FROX

FBox Adder (FBA) Microcode
UFADROTK<2:0>

that controls the bit
This field specifies loading of the latch
encoding:
The field has the following

rotator.

DIVIDE, set up for a rotate 1

1 = HOLD, do not change the content of the BIT ROT latches
2 = UNDEFINED, not used

3 = UNDEFINED, not used
4 = NO ROTATE, do not rotate

5 = NORM, load bit normalize count

6 = ALIGN, load bit alignment count

(G-tormat)

7 = DIVIDE UNPACK, load 7 (F or D - format) or
for divide unpack

UFADSIG<0>

operand

the

This field defines

addition or

significance

for

fraction

adder

1is

low

fraction adder

high

The field has the following encoding:

substraction.

processed

0 = data

being

1 = data

being processed by

significance

(LD FORMAT)
(FBA) MICROWDRD
FBOX ADBER
EXAMINE FROM CONSOLE >>>E/FBACS ADDRESS
i
27
28
29
30
31

UFADK <1.0>

UBSIDE <1:0>

]

USHFTX

25
USOPK <10>

3
74
UFARAK <1.0>

22
UALNSIG

20
21
UAUXK <1 0>

19
2

MICROWORD BITS <3116>
FA 18-23
1%
17
18
UK HMX
UROTK <20>
2.

PHYSICAL BIT NUMBERS

Figure 12-6

FBA Microword <31:16>

UFADK<1:0>

This field controls the fraction adder,

and has

the

following

encoding:

0 = ADD,

add A + B

1 = OPCODE, add or subtract A+B depending on op code

and

2 = DIV, add or subtract A+B depending on previous

guotient

code sign

bit

3 = SUBT, subtract A - B

12-6

FBox

Adder

FBOX

(FBA)

Microcode

UBSIDE<1:0>

This

field
0

controls

load

FAD,

load

BYT

the AUGL,

and

has

the

following encoding:

clear EXT
ROT,

ROT

and

BSMX potentially

normalized

ZERO,

HOLD

unpacked,

aligned,

clear

USHFTX<0>

This
the

field

controls

SHFTX MUX,

0
1

=
=

and

loading
has

the

FARA and

following

FMRB

macro

and

the

definition

input

encoding:

READ.FMRB
LOAD.ADDL

USOPK<1:0>

This field selects the inputs to the source
the following macro defintion encoding:

0
1

= FARA.OPBUS
= WBUS.FARA

= GPRBUS.OPBUS

operand muxs,

and

has

OPBUS.OPBUS

UFARAK<1:0>

This
macro

field controls loading
definition encoding:
=

LOAD.H.G,
FARA

load

the

<31:00>,

the

packed

CROVER

LOAD.H.DF,
FARA

load

the

<31:00>.

packed

GROVER

has

bits

rotate

LOAD.L.G, if the previous FARA was 0,
bits
of
G-format, load FARA<31:00>.
the FARA output left 4 bits.
LOAD.L.DF,

low

bits

rotate

FARA

LOAD.NOROT,

<31:08>.

and

= HOLD,

hold

the

FARA was

F/D-format,

output

left

the

GROVER will

FARA.

the

following

bits
of
G-format:
rotate
FARA oulput

high

will

bits.
2

high
will

bits.
1

FARA,

load

load
4

left

F/D-format:
FARA

output

1load
left

load the packed low
GROVER will rotate

load

FARA<31:08>

the

packed

GROVER will

bits.

previocous

rotate

FARA
was
2,
FARA output left

load

bits.

FARA

FBOX
FRox Adder

(FBA)

Microcode

UALNSIG<K00>

This field determines the significance of operands
and has the following encoding:
0
1

for alignment,

= process low-order bits
= process high-order bits

UAUXK<1:0>

This field CONTROLS THE
AUXA
and
AUXD
following macro definition encoding:
0

= HOLD

1
2
3

= LOAD.AUXA
= LOAD.AUXD
= LOAD.AUXA.AUXD

latches,

and

has

the

UROTK<2:0>

This field
controls
rotator, and has the
0

1
2
3
4
5
6
7

=
=
=
=
=
=
=
=

the
AMX/BMX
inputs
and
following macro definition

the
BSIDE
encoding:

byte

INPUT.A.B

INPUT.B.A
ALN.LD.CNT
ALN HOLD.CNT
DATA.A.B
DATA.B.A
DATA.A.B.NRM
NORM

UKHMX<0>

This

bit

generates

the

input

the AHMX,

and

has

the

following

macro definition encoding:
0
1

= K.ZERO,

generate

zero

K.RND.DT,

generate

data

for AHMX.K

type

for AHMX.K
rounding

12-8

constant

dependent

the

FBOX

FBox
FBOX ADDER (FBA} MICROWORD
EXAMINE FROM CONSOLE. >>>E/FBACS ADDRESS

1
11

3
42

Microcode
MICROWORD BITS <15:00>
18-23

UBEN 1305

(FBA)

{ULD FORMAT)

UHMX2205

2
a7

Adder

(i}

UJUMP (NCXT ADDRLSS) <0:0>

;

6
34

PHYSICAL BIT NUMBERS

Figure

12-7

FBA Microword

<15:00>

UHMX<2:0>

K.AUXD
BERT.O

N
W

T
|I

~3 O

AUXA.BERT

BERT.WRTLT

| B

K.BERT

DO b

This field enables the hidden-bit MUXs,
macro definition encoding:

and

has

the

following

AUXA.AUXD

AUXA.O
AUXA.WRTLT

UBEN<3:0>

e
I ON Ul L) B

Y U D WD 00
I DT

Womow

wowmnonoun

This field
enables
modifying
the
following macro definition encoding:

IRD and

DATA

UJUMP

field,

and

has

1IN

PREDICT.NORM.RESP
ED.INFO

not

used

FAD.ZERO
MUL.SYNC

DATA

SYNC

DATA.IN

EXP.ZERO

OPVAL

and

not used
EXP.DIFF

EXP.DIFF
<64

OPC.SS
RETURN

CALL
NOP

UJUMP<8:0>

This field generally defines the
modified by the UBEN field which

next micro address,
is ORed into it.

12-9

but

may

the

FBOX

FBox

Multiplier

12.1.2

(FBM)

Microcode

FBox Multiplier

(FBM)

Microcode

ADDRESS [HEX

DATA (HEX)

FROX MULTIPLIER (FEM) SICROWORD
EXAMINE FROM CONSOLE >>=>E/FBMCS ADDRESS

(ULD FORMAT)

MICROWORD BITS <39:00>
FM 14-18

PARITY

SPARE <105

]
31

i
30

MAMX SEL <2 0>
1

]

MHOLD SEL 3 0%
2

i
27

EXAC LD <102

)

l
0

i
26

LDACC <1.0>

BEN 30
3

0BMUX

| COUNTER

SEL

MuL

LOFMRA

SYNC

MSMX CTL <10>

| mamx el

MPLR SEL<20>

CLEAR

{
1

<20

CARRY CTL <202
2

MHOLD

MCAND | spi<an>

MPLRENAB L cFip
0

NEXT ADDRESS (J) <8.0>
6

5o,

I
.

MHIEITE

Figure

12-8

FBox

Multiplier

Microcode

12-10

Worksheet

FBOX

FBox Multiplier
FROX MULTIPLIER (FBM) MICROWORD

EXAMINE FROM CONSOLE: >>>E/FBMCS ADDRESS

(FBM)

(ULD FORMAT)

Microcode
MICROWORD BITS <39:32>
FM 14-18

UL
SYNL

LOFMAA

SPARE

<1.0>

MSMX CTL <1:0>

MBMX SEL
<Z0>

&
04

PHYSICAL BIT NUMBERS

Figure

12-9

FBM Microword

<39:32>

PARITY<0>
This

bit

reflects

the

microword

parity,

and

has

the

following

encoding:

0
1

= ODD, uword has odd parity and parity bit is reset
= EVEN, uword has even parity and parity bit must be

set

SPARE<1:0>
This

spare

field

and

all

encoding

and

decoded

NOP.

MUL SYNC<O0>

This bit informs the FBA that
has the following encoding:
0
1

= NOP
= SYNC,

send

SYNC

the

FBM has

result data

ready,

and

FBA

LDFMRALKO>

0
1

This bit enables
1loading
following encoding:
HOLD

FMRA

LOAD

FMRA

the

FMRA

latches,

and

has

the

mixer,

and

has

the

MSMX CTL<1:0>

field selects the input to
the
following macro definition encoding:
0

EXACC

EXACC and

EXACC

BYPASS

FMRA

ouou

This

and

BYPASS

12-11

MSMX

FBOX

FBox Multiplier

(FBM)

FBOX MULTIPLIER (FBM) MICROWORD

EXAMINE FROM CONSOLE: >>>E/FBMCS ADDRESS
31

MAMX SEL <203

(ULD FORMAT)

MICROWDRD BITS <31:16>
FM 14-18

EXAC LD <1.0>

CARRY CTL <20>

to,0

Microcode

0
14

LDACC <1:0>
L

QBMUX | COUNTER

SEL

CLEAR

MPLR s&mz;i‘:;t §ENAB

MHOLD

MCAND
SEL

SEL<3 0>

3
03

PHYSICAL BIT NUMBERS
MR 161%

Figure

12-10

FBM Microword

<31:16>

MRMX SEL<2:0>

This field selects the
following encoding:
0

input

= PROD.F

the

MRMX

mixer,

and

has

MRMX enabled

for

MRMX enabled

for FMRA unshifted

FRMX enabled

for

FMRA

for

EXACC

unshifted

the

FMRA unshifted

DIVISOR.LOW

= PROD.D.HIGH
QUOT.D.HIGH

= PROD.G.HIGH
QUOT.D.HIGH

3
4

= not used
= QUOT.F

MRMX enabled

ACC.LEFT24

shifted

= PROD.D.LOW

EXAC

= PROD.G.LOW

MRMX enabled

for

EXACC

unshifted

MRMX enabled

for

EXACC

shifted

QuUOT.D. LOW

left

bit

QUOT.G.LOW

bit

ZERO

MRMX disabled

and

ocutput

left

LD<1:0>

0
1
2

BHunn

This field enables loading of the
EXACC
following macro definition encoding:

latches,

and

has

the

LD.Q
MSMX.TO.EXACC

Q.TO.EXACC
NOP

CARRY CTL<2:0>

This field controls
encoding:

the

Carry Save

logic,

and

has

the

following

= add ACC
product

CLACOUT A

and

ACC

CLACOUT

the

partial

CLACOUT B

and

ACC

CLACOUT

the

partial

CLACOUT C

and

ACC

CLACOUT

the

partial

add ACC
product

= add ACC CLACOUT D to

the

partial product

12-12

FBox Multiplier

- FBOX
Microcode

CRY A

load

CRY B

load

CRY C

not

(FBM)

used

LDACCK1:0>

This

field controls the loading of the ACC,

and has the

following

O
e

hold

accumulator

shift ACC

clear

W B

uou

encoding:

right 8

bits

shift ACC left 24 bits
accumulator

OBMUX SEL<0>

This bit selects
or quotient),
0

the

and

has

input
the

to the MDQOX multiplexer
following

SEL.MCAND, select MDOX for MCAND
SEL.QUOT, select MDQX for quotient

(multiplicand

encoding:

bits

COUNTER CLEARKO>

This bit enables

and clears

the Quotient Bit Counter,

and has

the

following encoding:

0
1

= INC,
= CLR,

enable quotient bit counter to incréement
initialize quotient bit counter to 0001

MLPR SEL<K2:0>

[
IB
| IO T IO

N U
~

) B

This bit
selects
the
active
8=bit
following macro definition encoding:
MHLDC.BO,

select

MHLDC

MHLDD.BO,

select

MHLDD byte

MHLDC.B1l,
MHLDD.B1l,
MHLDC.B2,

select
select
select

MHLDD byte
MHLDC byte

MHLDD.B2,

select

MHLDD byte

MHLDC.B3,
MHLDD.B3,

select
select

MHLDC byte
MHLDD byte

MHLDC

multiplier,

and

has

the

multiplicand,

and

has

the

byte

MCAND SEL<O0>

This bit selects the active

32-bit

following encoding:
0
1

= SEL.MHLDA,
= SEL.MHLDB,

select MCAND MUX for MHLDA
select MCAND MUX for MHLDB
12-13

FBOX

FBox

Multiplier

(FBM)

FBOX MULTIPLIER (FEM] MICROWORD

Microcode

(ULD FORMAT

MICROWORD BITS <1500

EXAMINE FROM CONSOLE == =E/FBRMCS ADDRESS
15

MHLD SEL <30

BEN «<30>

NEXT ADDRESS () <890>

f o,

PHYSICAL BIT NUMBERS

Figure

12-11

FBM Microword

<15:00>

MHLD SEL<3:0>

(O
RO

LOAD.A.D.H

latches,

and

SPARE

DATA.LOAD.AB.D.L

T I TVI

hold

LOAD.A.G.H

LOAD.AB.G.L

the multiply
encoding:

LOAD.A

LOAD.A.F

LOAD.B
LOAD.C.F
LOAD.C.D.H
LOAD.C.G.H

LOAD.C
TVO

MO
W0
B W
e O

This field controls the loading of
has the following macro definition

HOLD

LOAD.CD.D.L

LOAD.CD.G.L
LOAD.D

BEN<3:0>
The

Branch

ADDRESS

Enable

(UJUMP)

field

allows

field,

and

the
has

modification
the

following

of
macro

the

defintion

W R

on
€4

nonmonou

and

IRD

used

DATA.SYNC
EXPONENT.ZERO

not

used

not

used

not

used

not

used

OPBUS.VALID
onow

MO WD W00 I

OPBUS.VAL

not

e O

encoding:

not

used

not

used

not

used

not

used

RETURN

CALL
NOP

NEXT ADDRESS<8:0>

The

be
it.

UJUMP field specifies the
modified
by
the content

next microaddress.
The
field
of the BEN field which is ORed

12-14

may
into

FBOX

FBox

12.1.3

FBox

Dispatch RAM

Dispatch

RAM

(FDRAM)

(FDRAM)
DATA {HEX)

ADDRESS (HEN

FBOX DISPATCH RAM [FDRAM] MICROWORD

EXAMINE FROM CONSOLE >>>E/FDRAM ADDRESS

{ULD/PHYSICAL FORMAT

MICROWORD BITS <7.0>

FM11

e
Figure

12-12

FBox

Dispatch

Ram

EleEN

FORMAT

FORAM
PARITY

(FDRAM)

]

FORK ADDRESS <4:0>
3,

Microword

NOTE

The ULD and physical
identical.

FDRAM

This

bit

number

assignments

are

PARITY<O0>

bit

represents

the

odd

FDRAM parity.

FORMAT<0>

This field is enabled only when an OP Code
field
1is
routed
to
the
FBR
where
it
G-format, F-format, and I-format (integer)

is being decoded.
The
1is decoded to provide
data formats.

FORK ADDRESS<4:0>

This field is routed to the FBA and FBM MSQs as the micro PC ‘fcr
fork

and

12.1.4
If

the

trap

conditions.

FBox Substitution Modules
FBox

FBox

removed

for

troubleshooting,

substitution modules

must

any

installed.

other

The

reason,

FBox Jumper

Module (FJM), an L0218, will replace the FBM (L0213) in slot AC7.
The FBox Terminator Module (FTM), and L0223, will replace the FBA
(L0212) in slot AC8.
The FBox terminates the WBus and OPBus.

12-15

FBOX

Turning the FBox ON and OFF
12.1.5
The

FBox

Turning the
can

FBox ON and OFF

turned

and

off

via

the

Accelerator

Control

and

Status
register
(ACCS
1IPR number 28).
This register may be
written or read
via
any
Macro
program
or
alternatively
via
console
commands.
When
the FBox is turned off, EBox microcode
will handle those floating point instructions
normally
executed
by the FBox.
The default mode of operation is for the console
to
enable
the
FBox
(if present) upon booting.
VMS, in turn, will also attempt
to turn on the FBox at system startup time.
Note that
in
order
to
disable
the
FBox while running VMS, you must write the ACCS
register AFTER VMS has been booted.

12.1.5.1

Disable

the

FBox

- After

the

running a Macro program

(such as VMS):

“P

;

enter CIO mode

>>>HALT

;

halt

the

processor

;

turn

the

FBox

;

then

continue

>>>DEPOSIT ACCS

>>>CONTINUE

12.1.5.2
To Enable the FBox - After
Macro program (such as VMS):

system

and

off

the

system

up and

running

“p
>>>HALT

>>>DEPOSIT ACCS

8000

>>>CONTINUE

12.1.5.3

;

enter

;

halt

;

turn on the

;

then

Determine

the

CIO mode
the

processor

FBox

continue

Status

is up and running a Macro program

the

FBox

- After

“P

;

enter

>>>HALT

;

halt

the

>>>EXAMINE ACCS

;

read

the ACCS

;

ACCS contents printed on console,

28 0000X001

b T

>>>CONTINUE

the

CIO mode
processor

where

X=0 if FBox is disabled
X=8 if FBox is enabled
that the 'l' digit refers

Note
to the
accelerator type and is set by microcode
Refer to the register description for ACCS
then continue
NOTE

There
be

is a console

set

FBOX OFF

system

(such as VMS):

flag called

cleared

commands.

wvia
In

the

'FBOX'

which

SET FBOX ON and

addition,

the

status

may
SET
of

this
flag
will be displayed with the SHOW FLAGS
console command.

12-16

FBOX

Turning the FBox ON and OFF

This

command

enabling

DOES

directly

NOT

disabling of the FBox.

is to control the

action

the

control

the

1Its purpose

INIT

console

of
command regarding the enabling or disablingwill
the FBox. If set ON, the FBox (if present)
be enabled by the INIT, INIT/CPU, or INIT/PAMM
.
commands

Accessing the ACCS register is the only way ¢to
determine the actual status of the FBox and to
control enabling and disabling it.

12-17

CHAPTER
IBOX

13-1

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13-3

a|gWX9I3ONId|4

IBOX

IBOX MICROCODE

13.2

1IBOX MICROCODE

ADDRESS (HEX

BATA [HEX)

MICROWORD BITS <50 00>
iCA 2-6

(ULD FORMAT)
180X CONTROL STORE MICROWORD
EXAMINE FROM CONSOLE >3 > E/ICS ADDRESS

UMISC? <20>

OPAR

DIAG

180X

502

i
3

H
0

i
79

UNPACK | OPVALIDCTL <10>

IS
i

{

i
1%

to,

Figure

WBUS

i
13-3

i
25

|
11

)

;

{FORK CTL <203
2

i
Q7

UNPACK

1L 10>

|
a5

l
4

AMUX SEL<20>

1
01

BMUX SEL <Z0>

]
08

i
a2

i
0

l
00

NEXT ADDRESS (NA} <7.0>

7o,

CTXLTL €20

MCF <30>

l UBEN CTL <10> }
0

UMISC<3 0>

GPRSEL <205

AEQ

UCoDE

REG

MOOE

<Z20>

CYCLEID <102

[Aag%x s&l UTRAP CTL<1 0>

43
UNSTALL

SHIFT)

;?Nfi%i?

i
TauF
| {NHI
onstace

MARK

l
£

IBox Microword Worksheet

PHYSICAL BIT NUMBERS

Figure

13-4

IBox Microword

<50:48>

ICS OPARKO>

The MICRO PARITY field

contains

odd

uword.

13-4

parity

generated

the

IBOX

IBOX MICROCODE
180X CONTROL STORE MICROWORD
(ULD FORMAT)
EXAMINE FROM CONSOLE >>>E/CS ADDRESS
47
45
45
44
43
1B HOLD

HMISR?

180X

NIAG

<20>

MARK

UNSTALL

‘

IBUF

GYGLE D <1 0%

SHIFT)

UMISO <305

1,
0

UNHIRIT | yNSTALL |

MICROWORD BITS <47.32>
iCA2-6
33
32

1L < UE”
UNPACK

MOF <3:0>

" PHYSICAL BIT UMBERS

Figure

13-5

IBox Microword

<47:32>

UMISC2<2:0>

The

MICRO

for

control.

functions

MISCELLANEOUS

field

provides

those

miscellaneous

which do not require the assignment of an entire field

NOP

MO e

Wou

e L
~J O

INDEX.IMM

ENA.OPBUS.PARITY
UNUSED

FORCE.SET.SB.VALID
INHIBIT.SET.SB.VALID

FORCE.SET.SB.ENA.OPBUS.PARITY
UTRAP.CIP

IBOX MARK<O0>

The IBOX MARK field

1is

used

‘microcode or hardware debugging.

= Normal:
1

mark

microinstruction

for

no microbreak

Microbreak

DIAG UNSTALLKO>

The DIAGNOSTIC UNSTALL field is used only in diagnostic mode, and
0

will override all IBox stall conditions.

IB HOLD

NOP

Override any IBox stall condition

(INHIBIT IBUF SHIFT)<0>

This field inhibits the IBUF from shifting, and is used

only

diagnostic mode.
0

Nohold

Hold

|UNSTALL

(DIAGNOSTIC UNSTALL)<0>

This field is used in some IBox microtrap
all

ISTALL terms:

DRAM

SUSP.

0
1

NORMAL

Override

routines

override

ISTALL due to an EBox STOP command, or due to

STALL
13-5

IBOX

IBOX MICROCODE

CYCLE

ID<1:0>

The CYCLE
following
0
1

ID field
types:

classifies

the

=
=

NORMAL:
NON-IFORK CYCLE
INDEX IFORK ENTRY [RX]

BASE

TFORK

OPERAND ADDRESS
ENTRY

AND

current

(BOA)

cycle

into one

the

ENTRY

- (BOA+[RX])

UMISC<3:0>
MICRO
functions.

MISCELLANEOUS

field

handles

miscellaneous

IBox

NOP

Stall

until

FBRox

OP.WRITE

command

IB.FLUSH.LD.CPC

IB.FLUSH

CON.BRANCH
IB.FLUSH.COND
READ. IMD

INH.SB.CHECK

Reserved

Addressing

Mode

(RAF)

DIAG.DONE
DIAG.RESET
BMUX.CHK.CTX

POP

Stack

Clear
W

MO
I O 00 IO U e G0 R

om0

The

CPC

VALID:;

for

Flush

and

Branch

COND.FA.OP.MEM.REQ
FA.OP.MEM.REQ

MCF<3:0>
The

MICRO

MEMORY

CONTROL

FUNCTION

field

defines

the

PORT

MCF

DRAM

field.
READ.RCHK

DRAM MEM

modify

OP-PORT

MEMORY

WRITE.V.NOPAGE
O
B
N

UNUSED

UNUSED
UNUSED

READ.V.RCHK.
2ND

| N

READ.V.NOPAGE

READ.V.RCHK

READ.V.NOPAGE.
2ND

REQUEST

READ. V.WCHK

1B.FILL.OP

equals

WRITE.V.NOPAGE.2ND
WRITE.V.WCHK

AL 0D

equals

O U

MEM
ke

e L B

IB.FILL.IBF

13-6

read

and

READ.WCHK

IBOX

IBOX MICROCODE
MICROWODRD BITS<31:16>

{ULD FORMAT)
180X CONTROL STORE MICROWORD
EXAMINE FROM GONSOLE: >>>E/CS ADDRESS
UNPACK
cTL

0P VALID CTL <10>

1o,

iCA 2-6

WBUS

AMUX SEL<20>

BMUX SEL €2:0>

CTX CTL <20

GPR SEL <2.0>

LCODE

REG

1ID

data

and

type

PHYSICAL BIT NUMBERS

Figure

13-6

IBox Microword

<31:16>

UNPACK CTL<1:0>

The UNPACKER CONTROL field determines how the

should be unpacked before being driven onto the OP Bus.
0
1

= NOP
= SIGN EXTEND

fields.
= Unused

IF -~ASRC

2 = Unpack as short literal according to DRAM

CTX

OP VALID CTL<1:0>

The OPERAND VALID CONTROL field controls the setting
VALID

0
1

flag for the

ID and

NOP

Set OPVALID if ((READ + MODIFY + VSRC)* RMODE) + ~-(ASRC *

)
RMODE
2
3

the

IMD operand buffers.

Set OPVALID if ASRC + ((READ + MODIFY)

* ALIGNED)

Set OPVALID unconditionally

REG MODE<O0>

mode
register
of
beginning
the
The REGISTER MODE field marks
the validity of an entry
determines
It
processing.
specifier
scoreboard
when
cases
These are the only
into the scoreboard.
entries are validated.

0
1

= Not an RN specifier
= RN specifier

UCODE WBUS REQ<0>

The UCODE WBUS REQUEST bit partially controls updating
and requesting an

the

RLOG

IBox WBus cycle.

0 = RLOG entry is pushed if this is the first IFORK for
this
if doing an
requested
c¢onditionally
is
WBus
OPCODE.
UNWIND

(GPR SEL =

entry.

WBus

1 = RLOG entry

is pushed with valid GPR
is

requested.

13-7

number

and

context

IBOX

IBOX MICROCODE
GPR SEL<2:0>

The GPR SELECT field

determines

the

source

the

GPR

read

nou
oW

W) B
Lo

b O

address.

GPR address

from IBUF

1is

Index register

<Bl>

being

addressed

saved

Iindex

address

<1:0>

contexts

(data

GPR address
RLOG unwind

plus 1
previous GPR address

GPR address <3:2»> from CTX CTL<1:0>»;

GPR

from UNPACK.CTL<1:0>

UNUSED

CTX CTL<2:0>

The CONTEXT CONTROL field controls

the

various

for Lhe adder, memory references, and RLOG entries during

types)

a microcycle.

CONTEXTS
ADDER

1
2
3

(IN BYTES)

CTX

MEM
CTX

RLOG
CTX

DRAM
CTX
4
X
+ RLOG

DRAM
CTX
4
2
X

DRAM
CTX
4
X
X

DRAM
CTX
4

~DRAM
CTX
X

CTX

-DRAM
CTX
-4

4
5
X

UNDEFINED

BMUX SEL<2:0>

I
T

UNUSED
DMX. IBF

CPC, used for string continued flushes

~J O

s L

Adder CTX as defined by CTX CTL

nunu

ZERO

The BMUX SELECT field controls the input to the BMUX.

DMX.IMD

Hold VA, inhibit VA clocking.

Not a BMUX SEL function

IBOX

IBOX MICROCODE
180X CONTROL STORE MICROWORD

EXAMINE FROM CONSOLE >>>E/ICS ADDRESS
15

UTRAP CTL<10>

AMUX SEL
20>
0

(ULD FORMAT)

MICROWORD BITS <1500>
ICAZ-6

FORK CTL <20

UBEN CTL <1:0>

2
17

NEXT ADDRESS (NA) <7:0>

10
36

| PHYSICAL BIT NUMBERS

Figure

AMUX

AMUX SELECT

Microword

<15:00>

AMUX

controls

the

input

the

AMUX.

W) N

-4
T
I
U

GPR, if WBus match
GPR (Left Shift 1)
GPR (Left Shift 2)

then

replace

GPR data

with

WBus

data

the

WBUS

Enable

ISTALL

scoreboard

ENABLE

ISTALL

WBus

hit

match

CTL<1:0>

MICROTRAP

Enext

field

ZERO

D1
wJ O U
i
O COh

UTRAP

The

IBox

SEL<2:0>

The

13-7

cycle

CONTROL
the

Inhibit

Micro-trap
Micro-trap

field

current

enables

a microtrap

PORT memory

Micro=trap

due to
next cycle for
for unaligned

request

occur

unaligned.

unalignment

unaligned
(RN)
or

indirect fetch
any
other
wunaligned

operand

IFORK CTL<1:0>
CONTROL

field

word,

Do not IFORK
IFORK if ASRC

e
W
b
YA
~J

Hon

not.

byte,

IFORK

entry

nwwunun

The

The
L

determines

field

has

the

following

cycle

encoding

+
+

(READ* (BWL))
WRITE + ((READ

READ
QUAD

(BWL)

EBOX

UMCF

IFORK

VSRC

IFORK
IFORK

if
if

IFORK

Unconditional

equals

IFORK

unused

13-9

+ MODIFY)

IFORK

(where

longword):

(BWL))

IBOX

MICROCODE

UBEN<1:0>
The BRANCH ENABLE field enables a multi-way (up to
in microcode in the absence of IFORK or microtrap.
UBEN

MUX

QUAD

DRAM

MEM

OCTA

RLOG

DRAM

FIRST

CTX

branch

BITS

l6-way)

MEM

CTX

DRAM

CTX

DRAM

NA<7:0>
The

NEXT ADDRESS

absence
of a
are ORed with

13.3

field

addresses

the

microinstruction

branch, IFORK, or microtrap.
the branch conditions.

1IBOX DISPATCH

RAM

For

branch,

the

NA<3:0>

(IDRAM)

ADDRESS {HED

BATA (HED

MICROWORD BITS< :;55813}&

(ULD/PHYSICAL FORMAT)

JGRAM MICROWORD

EXAMINE FROM CONSOLE: >>>E/IDRAM ADDRESS

.
iS

... ... . .
14

REF <1.0>
]

SUSFENE} BDEST

CONTROL 10>

LASY

OPAR

FPA

]

ADDRESS <0500>

!
[SERE-3 -]

Figure

13-8

IDRAM MICROWORD WORKSHEET

13-10

IBOX
IDRAM

13.3.1

1IDRAM Address

Address

Generation

The IDRAM
.execution

address is a 12-bit address which is generated from the
point
counter (EPC), the OPCODE, and a bit controlled
/by
whether
or
not
the
instruction
is
extended
(an
FD
“instruction).
The initial FDRAM address for any instruction, has
the least significant three bits equal to zero because the EPC is
initially zero, being incremented for each specifier.
Table

13-1 shows how to generate
Example 13-1 gives examples.

the

initial

FDRAM

address,

and

NOTE

Example

ADRS

13-1

KA86*.MCR.

IDRAM Address

Generating

Generation

<10:03>

OPCODE

<07:00>

<02:00>

EPC

<02:00>

IDRAM Addresses

CVTLD instruction, OPCODE = 6E

IDRAM ADRS

"o
|
+-

found

a'nm ke e

IDRAM

e
e
e

Table

ot
— +

code may

e
e

IDRAM

ADRS

CVTLH

instruction,

IDRAM

ADRS

01101110

o000

FD |OPCODE <07:00>=6E | EPC <02:00> |
+

001101110000

OPCODE

IDRAM

370

6EFD

01101110

070

{

|OPCODE <07:005=6 | EPC <02:00> |

101101110000

B70

13-11

IBOX

IDRAM Microword

1IDRAM Microword

13.3.2

MILHOWURD BITS219 165
1808, C

{ULD/PHYSICAL FORMAT)
|DRAM MICROWORD
EXAMINE FROM CONSOLE >>>E/IDRAM ADDRESS

NOTE: ULD AND PHYSICAL BIT NUMBER ASSIGNMENTS ARE IDENTICAL

Figure

13-9

IDRAM Microword

<19:16>

CONTEXT<2:0>
The CONTEXT

e
B

wnounn

-7

field

specifies

the

data

context

based

the

encoding:

BYTE

following

WORD

(2 bytes)

LONG
QUAD

bytes)

OCTA

(16 bytes)

UNPREDICTABLE

TYPE<1:0>

The TYPE field specifies the data types based

the

., 04,

following

encoding:
0

INTEGER,

FLOATING,

2
3

= G=-FLOAT
= VSOURCE

ASOURCE
F,

EXAMINE FROM CONSOLE: > >E/IDRAM ADDRESS
14

TYPE

10>

REF <10>

MICROWCRD BITS <1500

{ULD/PHYSICAL FORMAT)

{BRAM MICROWGRD
15

1808.¢

CONTROL <10> | syspenn|

moest | Last

OPAR

ADDRESS <0500

03,

)

o1,
00

NOTE ULD AND PHYSICAL BIT NUMBER ASSIGNMENTS ARE IDENTICAL

Figure

13-10

IDRAM Microword <15:00>

REF<1:0>

The MEMORY REFERENCE field specifies the memory reference and the
checking applied.

ACCESS

READ

CHECK

WRITE

—
-————

0
0

= ASOURCE
= VSOURCE

~---===-

READ

= WRITE
= MODIFY

- e e
READ

WRITE
WRITE

13-12

IBOX

IDRAM

Microword

CONTROL<1:0>

The CONTROL (CTL)
field
determines
the
content
of
address.
See Figure 13-11, Fork Address Generation.
0

EXECUTE

SINGLE

OPT-TWO

the

FORK

EXECUTE

CTL

FORK

4=t

ADDRESSES

DRAMKFPA>

EXECUTE

FEN OR

DRAM ADRS

<05:00>

-DRAM<KFPA>
4=t

==+

——tm———

DRAM<KFPA>
& FEN OR

o o

+-——+

SINGLE

DRAM ADRS

~-DRAM<FPA>

OPT-TWO

RMODE

FEN

tom——+t

07
OPT-TWO

RMODE
|

RMODE +

DRAM ADRS

FORK ADRS

bit

(FA<00>»)

turn

off

If FORK ADRS bit

(FA<05>)

turn

off

scoreboard

Figure

13-11

Fork

Addressess

<04:00>

REGMODE

NOTE

+-——t-————————— - +-

<00>

RMODE

—-

<05>

00
DRAM ADRS

DRAM ADRS

FEN

;

|DRAMKFPA>
&

CTX<2:0>

-t

<05:01>
-4

07
&

TYPE<1:0>

DRAM ADRS

02
DRAM

FEN

fm——f————

NOT

DRAM

<04:00>

fomm

EXEC

B1=REGMODE

|DRAMKFPA>

DRAM ADRS

o
o e e e

00
-

FEN

OPT-TWO

= v

|DRAM ADRS<05>

————

EXEC

= REGMODE

<05>

|DRAM<FPA>

NOT RMODE

OPT~-TWO

ADRS

-————

DRAM

<00>

-BDEST

DRAM ADRS
& RMODE &
+

+—-

|DRAMKFPA>

<05:01>

05
'

-———

et R
s ikt
L e

+———+

e e

Generation
13-13

IBOX

IDRAM

Microword

SUSPEND<KO>

If
set
(1),
the
Calculation
Unit
specifier

that

had

SUSPEND
(SUSP)
field
to
suspend
operation
SUSPEND bit set.

the

causes
the
Address
after
processing
the

BDEST<0>

The

BRANCH

DISPLACEMENT

set

bit
the

is not set for
Opcode
is

NEXT field
displacement.
This
first
item
following
displacement.

preceding
which
the

0
1

the

= Next

byte
after
this
specifier
1is
a
specifier or new OPCODE.
= Next byte after this specifier is a branch

DRAM

entry

Opcodes in
a
branch

mode-register
displacement.

LAST<0>

The
one

LAST bit indicates that
for this instruction.
optimized.

the
This

current
bit is

DRAM entry
is
the
last
implied if an instruction

OPAR<O>

The
The

ODD PARITY bit is used to check the integrity of
console attempts to correct DRAM parity errors.

DRAM

data.

FPA<O>

The
for

FPA OVERRIDE bit specifies that the FPA may override
the specifier that the IBox is currently processing.

the

ERox

ADDRESS<5:0>

The

EXECUTION ADDRESS
will
be
sent

that

modified

before

field

supplies

the

EBox

becoming

the

EBox

FA.

13-14

the
no

basic
error

FORK
is

address

detected.

(FA)
It

IBOX

IBUFFER AND OPCODE

TESTPOINTS

13.4

IBUFFER AND OPCODE TESTPOINTS

Table

13-2 lists oscilloscope/logic analyzer test points

IBUFFER

(bytes

and

Table

13-3

for

lists

the

oscilloscope/logic analyzer testpoints for the OPCODE bits
(sent
from
the
ICA to FBM) which are available on the backplane.
The
tables include channel number suggested
for
use
with
a
1logic
analyzer, signal name, print page on which the signal originates,
and the CPU backplane pin location.

Table 13-2
Channel
$0

IBUFFER Testpoints

Signal Name

IBD IBUF DATA Bl

7 H

IBD3

IBD IBUF
IBD IBUF

DATA Bl
DATA Bl

5 H
4 H

IBD2
IBD2

#4
#5
6

IBD IBUF DATA Bl
IBD IBUF DATA Bl
IBD IBUF DATA Bl
IBD IBUF

DATA Bl

3 H
2 H
1 H

#8
#9
#A
#B

IBD
IBD
IBD
IBD

IBUF
IBUF
IBUF
IBUF

DATA
DATA
DATA
DATA

BO
BO
BO
BO

7
6
5
4

#C
#D
$E
#F

IBD
IBD
IBD
IBD

IBUF
IBUF
IBUF
IBUF

DATA
DATA
DATA
DATA

IBD IBUF DATA Bl

$2
$#3

Table

6 H

Section/Slot/Pin
Cl5_08

IBD3

C15;24

Cl5_44
CIS;SU

IBD2
IBD1
IBD1

IBD1

Cl5_68
Cc15_71

H
H
H
H

IBD3
IBD3
IBD2
IBD2

C15_02
BIS;SZ
B15_56
B15_53

BO 3 H
BO 2 H
BO 1 H
BO O H

IBD2
IBD1
IBD1
IBD1

Al5 89
B15 30
315”18
B15 46

13-3

Cl5_12
ClS_lS

OP CODE Testpoints

Channel

Signal Name

Section/Slot/Pin

#0
#1
#2
#3
#4
#5
#6
#7

ICA OPTIMIZED A H
ICA EXT OPC A H
ICA OPC BIT 7 A H

ICAE
ICAE
ICAE
ICAE
ICAE
ICAE
ICAE
ICAE

BO7_83
B07_85
B07_81
BO7_82
B07_86
BO7_77
BO7_87
B07_80

#8
#9

ICA OPC BIT 6 A H
ICA OPC BIT 5 A H

ICA OPC BIT 4 A H
ICA OPC BIT 3 A H
ICA OPC BIT 2 A H
ICA OPC BIT 1
ICA OPC BIT 0

A H
A H

13-15

ICAE
ICAE

BO7_76
B07_84

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14.2

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MICROCODE

ADDRESS (HEX

DATA §HEX}

MBOX CONTROL STORE (MCS} MICROWBRE
PXAMINE FROM CONSOLE

> > >

ApuHEys S
papity CORECTION]

(ULD FORMAD)

S
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REQUEST

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§1

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60
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CLEAR
8D
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ABUS?
ABUSZ

ENABLE
BYTE
MERGE

8
ffbeer

COUNT | COUNT

ABUS

ARRAY

mark

52
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CACHE

WAL

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R
COUNT

| MO wsc| ADDRess | ~ermor | ConThoL <io>

ENABLE | EnaBie

ABUS

ABUS ADDRESS

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TRAP

PAR

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cear | cAeus
3

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53
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54 |

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WORD -} WORD

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.
_
REG LOAD<1 0>

STACK <10>

‘
.
[
—ENABLE
DRIVE
| ARRAY
ENAHLE | BUS

MICROWORD BITS <79:00>

E/MCS ADDRESS

ENABLE

i
MR 18783

14-6

MBox

Control

Store

Microword

Figure

14-7

Worksheet

MBOX

MBOX MICROCODE
MBOX CONTROL STORE (MCS) MICROWORD

EXAMINE FROM CONSOLE: >>>E/MCS ADDRES.

(ULB FORMAT)

CORECTION so,: sa;s.c*r <:;0>

]

MCCD-H

?TAcf <1:99> //%} 3 a:sax ;YCLE,W?E:&Q}: .

ADBRESS AES

MICROWORD BITS <7964>

LATCH // ) %fi ATA
38

BIT NUMBERS
PHYSICAL

Figure

14-7

ADDRESS

MBox Microword

<79:64>

PARITY<O0>

The address parity bit reflects odd parity of the
the microword

is stored in the control

store.

address

where

RES CORR REQ<0>

When set,
correction

IOA SEL

the

RESET

cycle

CORRECTION

REQUEST

bit

resets

1
2
3

data

<1:0>

The I/O ADAPTER
SELECT
field
provides
commands
interface MCA to select the specified I/0 adapter.
the following encoding:
0

the

request.

to
the
ABus
The field has

DMA DONE not sent to ABus
= LATCH B sends DMA DONE to ABus
= LATCH A sends DMA DOME to ABus
= CPA sends DMA DONE to ABus

STACK<1:0>

O
Wk

Wnouwou

This field provides stack control.

The field encoding is:

NOP

= push current micro address on the stack
= pop a micro address from the stack
when asserted, either does a return from top of stack,

return

arbitration.

MFORK.

UNUSED FIELDS

Two 2-bit fields are unused

ARB SEL must be specified to disable

in the ULD:

14-8

<K73:72> and <66:65>.

MBOX
MBOX MICROCODE

MBOX CYCLE

TYPE<3:0>

Indicates

the cycle type the MBox controller will perform.
no type
read register cycle
write register cycle
writeback cycle
ABus array write cycle
data correction cycle
probe cycle
ABus cycle
CP refill cycle
invalidate TB cycle
TB cycle
CP array write cycle
CP write cycle
CP read cycle
reftill cycle

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

00
01
02
03
04
05
07
08
09
0OA
0B
0C
0D
OE
OF

-REFILL LATCH

When reset
ADDRESS

-ABUS

LOAD<O0>

(asserted

REFILL

DATA

1low),

this

bit

enables

1loading

low,

parity onto the

the ABUS DATA EN bit

asserts data and

MICROWORD BITS <6348
MCCD-H

ENABLE | ~CACHE | SELECT
WRITE

ENABLE

COUNY

COUNT

875

CLEAR

e | 28

BRANCH

—ENABLE|

cB
ORIVE | ARRAY
;
ENABLE | BUS

longword

ABus

{ULD FORMAT)
MEBOX CONTROL STORE (MCS) MICROWORD
EXAMINE FROM CONSOLE: >>>>E/MCS ADDRESS
82

the

ENABLE<O>

When asserted

LATCH.

LRU

WORD

LOAD

PHYSICAL BIT NUMBERS

Figure

14-8

CB DRIVE

MBox Microword

<63:48>

ENABLE<0>

When asserted, CB DRIVE EN gates check bits, read from
the
data
cache, and stored in the DATA CB MUX LATCH OUT, to the Array Bus.

When there is a cache data parity
error,
the
cache
correction
cycle
requires
that the check bits be read from the cache.
The

0
1

Hon

bit has

the

following encoding:

do not gate CB MUX LATCH OUT to check bit bus
gate CB MUX LATCH OUT to check

bit

bus

-ENABLE ARRAY BUS<0>

When asserted
CACHE

WRITE

low,

this bit enables gating 32 data bits from

DATA MUX

LATCH

the

14-9

Array

Bus.

the

MBOX

MBOX MICROCODE

REG

LOAD<K1:0>

ABUS

W B

=t O

The REGISTER LOAD field provides
to load the I/O adapter latches,
not

load

IOA

latches

load LATCH A with IOA REQ
load LATCH B from LATCH A
lovad CPA latch from PAMM

IOA

SELECT

DISABLE<O0>

When set, the ABUS IOA SEL
PROGRESS is not true.

CLEAR

The

CLR

inputs to the ABus interface MCA
and has the following encoding:

DIS

bit

inhibits

IOA

SELECT

BD SEL bit

]

hold

ENABLE

BYTE

The

BYT

during

SOURCE

the

data

SOURCE

not
A2

used

for

array

DMA writes, this
The bit has the
hold
DAT

select

refills.

Two

for current and
of Lhe
current

A2 DAT
REG

bit causes data to
following encoding:

held

REG

MERGE<0>

MERGE

DATA

bit

byte

MUX

and

the

enables

the

DATA

write.

When

the

BYT

MERGE

DATA

LAT

OUT

enabled,

with

MUX

select

DO MUX selection

the

data

hardware

coming

hardware

for

will

from

the

merge

the

DATA

MUX.

-ARB

SELECT<0>

This

bit

selects

address.
SEL

the

However,
bit

and

arbiter address
<VECTOR

disables

.and.

instead of
NOT

arbitration.

STACK
The

bit

the

EMPTY>
has

select

micro address

from arbiter

select

micro address

from NEXT ADDRESS

MARK<0>

bit

trace

bit

used

for

debugging.

14-10

micro

override

the

following

encoding:

This

HOLD<O>

When set during
the A2 DAT REG.

ARB

XFER

SELECT<O0>

latches
retain
the
array
select
information
pending refills.
If set, this bit allows loading
latch from the pending latch.

ABUSZ

field

MBOX

MBOX MICROCODE

-ABUS

REFILL BRANCH<O0>

When asserted
logic.

low,

this bit enables

the optimized

refill

branch

CLEAR CACHE W/V BITS<0>

When asserted with the CACHE WRITE
ENABLE
bit,
this
cause the written and valid (W/V) bits to be set to 0.

ENABLE

This

will

LRU WRITE<O>

bit enables

—-CACHE

When

bit

WRITE

this

LRU to be written,

switching cache

selection.:

ENABLEKO>

bit

asserted

low,

enables

writing

the

cache

data

tag.

and

SELECT WORD COUNT<O0>

When

a refill, writeback,
or
ABus
multi-word
array
reference
takes place, the word counter keeps track of the current longword
being read or written.
If SELECT WORD
COUNT
1is
set
the
word

counter

1is

physical

address

selected
is

for

addressing

the cache.

1If reset,

the

used.

LOAD WORD COUNT<O0>

When

asserted,

from

LATCH

the

MBO0X CONTROL STORE {MCS) MICROWORD

EXAMINE FROM CONSOLE: >>>E/MCS ADDRES

COUNT | COUNT |
73

load

the

1longword

counter

MICROWORD BITS <47:32>

MCCD-H

PA MUX LATCH SEL <20> | cLup | HOLDON | g

ECC

DATE JauMUX

—ABUS

cean | Nc

will

(ULG FORMAT)

b
k-4

X4
m

LD WD CNT bit

<03:02>.

BUSY

HOLD | CHECK |

ABUS

I MDwse] ADDRESS

|EnasiE I DRVE ) TRap
82

PHYSICAL BT NUMBERS

Figure

14-9

ABUS ADDRESS

Eusts | GoNTRoL <1.0>

52
wEIEE

MBox Microword

<47:32>

CLEAR WORD COUNT<O0>
When
in

asserted,

the

WVP MCA on

CLR WD CNT
thc

address

bit

will

clear

the

longword

module.

INC WORD COUNT<O>

The

INC WD CNT bit

increments

the

14-11

longword counter.

counter

O
e
B
L

onwunnuw

U b

VA MUX

Refill
ABus

|
|

This field controls the PA MUX on the Address
Path
module,
and
determines
the input to the PA MUX LATCH.
The [ield encoding is
as follows:

wd O

PA MUX LATCH SEL<2:0>

CO0 TAG Store
Cl TAG Store

Error

Latch
Latch

Latch

PTE

Store

TAG

Store

-ABUS CLUP<KO0>
The ABUS

CLEAN UP bit

conditions

array

step.

also

informs

the
ABus interface logic to start looking for a word count match
for ABus Transfer.
The bit has the following encoding:
0
1

Array
U

MBOX
MBOX MICROCODE

and

array
hit.)

Step

Enable

NOT ABUS

step

causes

REFILL

only

array

CYCLE

NOT

step

TYPE.

refill

(Array

Step

causes

in progress AND NOT block

HOLD ON ARRAY BUSY<0>

The combination of this bit set and ARRAY BUSY true, will prevent
the
micro
address from changing until ARRAY BUSY is false.
The
bit has the following encoding:
0

= do not hold here and wait for ARRAY BUSY to drop
= hold here until ARRAY BUSY is false

HOLD<O>

When HOLD is set,
the Al DATA LATCH

the Al DATA LATCH will
is held.

1loaded.

reset,

ECC CHECK<0>
The ECC CHECK field controls whether the ECC MCA on the data path
module
1is checking data read from memory for errors (refill), or
generating
check
bits
on
data
being
written
to
memory
(writeback).
The bit will be reset for a writeback and set for a
refill.
The bit has the following encoding:
0
1

= generate check bits
= check read data for

errors

14-12

MBOX
MBOX MICROCODE

DATA OUT MUX<1:0>

The DO MUX field determines the DATA OUT MUX selections.
byte
write
or
an ABus masked write, the UCODE selects
SOURCE

MUX and

the

the
operation
DATA LATCH for

hardware

selects

the

bytes

nonunn

1
2
3

select

DATA SOURCE

select

ARRAY

indicates

ABus.

This

send

DRIVE

the ABUS
module,

-ENABLE

valid

bytes

to be

MUX

DATA

LATCH

is asserted, it
current
cycle

when

ADDRESS

If set,
address

the CP
masked

ENABLE<O>

MD RES EN
that
the

ABUS

written.

select A2 DATA REGISTER
select CP DATA LATCH

MD RESPONSE

When
MCA

a CP
DATA

1is
a
CP byte write, the hardware selects
valid bytes to be
written.
On
an
ABus

write,
the hardware selects the A2 DAT REG for
written.
The field has the following encoding:
0

On
the

status

CP port
This

interface
also

bit

code.

ENABLE<O0>

ADR DR EN bit enables the ABus
drivers
on
allowing an address from the PA MUX LATCH to

function

ERROR

the

indicates to the
has
completed.

used

for

initiated

the
the

requests.

TRAP<0>

When asserted low, the ENABLE ERROR TRAP bit is a signal
to
the
micro
address
control
to go to micro address FF if there is an
ABus address parity error.
It forces a POP of the
stack
if
an
error trap is taken.

ABUS

ADDRESS

CONTROLKL1:0>

Honnou

This bit is a signal to the ABus interface MCA to
allow
control
of
the
1I/0
adapter register file.
The field has the following
encoding:
hold

current

address

I/0

increment if write
increment current address
load

current

address

adapter

file

1/0 adapter register
register file

1/0 adapter

NOTE

MCC ABUS ADDRS
ABus

same

that

the

CTRL

control

<01:00>,
the

the

MBox microcode

14-13

bits.

signals
file,

are

the

not

the

file

MBOX

MICROCODE

—t

ARRAY | TARRAY | ABUS
INHIBIT
START
ENABLE | INCREMNT

ARRAY 2 | TABUS | pean
ATA
HOLD
ENABLE

ABUS

MICROWORD BITS <31:16>
-~ MCCD-H

DS MUX SEL <1:0>

DSM
VALID
35

i rivd

’

’ f?

LAST

CACHE

ASSERT

- SEL

——

MEGX CONTROL STORE (MCS) MICROWORD
{ULD FORMAT)
EXAMINE FROM CONSOLE: >> >E/MCS ADDRESS
18

—pA
LATCH
LOAD | TRANSFER

PHYSICAL BIT NUMBERS

Figure

14-10

MBox Microword

<31l:16>

ABUS MBOX OUT<O0>

When asserted,

indicate

that

file.

this bit

is a signal

to the ABus

interface MCA

the MBox is ready to send data to the I/0 adapter

ARRAY 2 HOLDKO>
If ARRAY 2 HOLD is reset, the ARY 2 DATA LAT will be loaded.
If
the
ARY2
HLD
bit
1is
set
the
ARY
2 DATA LAT will hold data
presented to the CACH WRIT DAT MUX LAT, thus preventing the
CACH
WRIT DAT MUX LAT

-ABUS

LATCH

from changing.

LOADKO0>

When asserted low,

this bit causes

the ADR A LAT to be

loaded

T7A
(second
T3A).
The bit is also used to clear ABUS
and used as an enable into the GO REFILL logic.

XFER EN,

ARRAY READ DATA ENABLE<KO>

When asserted the ARRAY RD DATA EN
bit
will
enable
the
array
board drivers of the selected board.
Data from the DC109 will be
asserted

the

Array Bus.

ARRAY START<KO>

When this
bit
1is
asserted
to
the
array
interface
MCA,
it
indicates
that
the microsequencer wants the array to initiate a
write or read operation.
The array interface MCA will issue
the
start signal
available.

to the

array at

the

first T2 after

Lhe array becomes

=ARRAY STEP ENABLEXO>

When asserted
1low,
this
bit
1is
used
on
array
cycles,
and
conditions
the
array interface MCA to issue ARRAY DATA SHIFT to
the array.
Note that this is an
enable
function
and
not
the
actual
step.
Hardware
issues
the
array
step
at
T2 in the
subsequent

ABUS

cycle.

INHIBIT INCREMENT<O0O>

This bit
inhibits
an
address
increment
function
from being
the ABus device if ABUS TRANSFER IN PROGRESS is
to
transmitted
not

true.

14-14

MBOX

MBOX MICROCODE

DATA SOURCE MUX<2:0>
DSM VALID<KO>

) DS MUX SEL<1:0>
DATA
The DATA SOURCE MUX field consists of three subfields:
SOURCE MUX, DSM VALID, and DS MUX SEL. The overall field selects
the data source to have byte parity generated or checked and
clocked into the CP DATA LATCH, DATA ERROR LATCH, or A2 DAT REG,
and sent to the DATA OUT MUX. When explicitly set it also tells
the MBox that the DATA SOURCE MUX is valid, that is, that parity
The field encodings are as follows:

counts.

uoH
Ho#

~3 AT
P

DATA SOURCE MUX<K24:22>:

select
select
select
select

MDBus and valid
MDMUX and valid
A2 DATA LAT and valid
Al DATA REG and valid

DS MUX SEL<23:22>
0

= MDBus

2
3

= ARRAY BUS
= ABUS DATA

MDMUX

DSM VALID<K24:24>

0 = No valid data at DATA SOURCE MUX output
1 = valid data at DATA SOURCE MUX output

MIC PAR<O>

The MIC PAR bit reflects the odd microword parity.

MIC PAR

will

DMA

write

be calculated after the address parity bit is calculated.

ASSERT LAST WD<O0>

ASSERT LAST WD is used to force last word

for

valid

optimization.

-SEL CACHE<O0>

The NOT SELECT CACHE bit specifies whether the MD
select

the

cache,

either

based on the encoding of the DSM VALID and

The -SEL CACHE bit has the following encoding:
.

MUX

LAT

will

the DATA OUT MUX or DATA ERR LAT

= select cache

1 = select DATA ERR LAT or DATA OUT MUX

14-15

MUX

SEL

fields.

MBOX

MBOX MICROCODE
-PA

LATCH

LOADKO0>

When

asserted

will

low,

the

FORCE

ABUS

TRANSFER<0>

Used

during

DMA writes

MBOX GONTROL STORE {MC3) MICROWORD

EXAMINE FROM CONSOLE >>>E/MCS ADDRESS
15

]

BEN

14-11

transfer

CLEAR

FLAGS

NEXT ADDRESS <7:0>

MFORK

ENABLE

MBox Microword

)

<15:00>

SEL<2:0>

the

through

BEN

progress.

| —ABUS

The BRANCH ENABLE SELECT field enables
one of
multiplexers.
The outputs are ORed with the
of

otherwise

MOCD-H _

PHYBICAL BIT NUMBERS

Figure

ABus

loaded,

MICROWORD BITS <15:00>
10

BEN MASK <3:0>

force

[ULD FUHMAD

BEN SEL <2:0>
1

PA MUX LATCH will

held.

NEXT ADDRESS

the

BEN MASK

field.

1Individual

field.

See

eight

four

multiplexers

Table

inputs to 8:1
low-order bits
are

14-1.

disabled

MASK<3:0>

Each bit in this field enables one of the
8:1
branch
condition
multiplexers.
Bit
zero
enables
multiplexer
0, bit 1 enables
multiplexer 1,
and
so
forth.
Table
14-1
1lists
the
branch
conditions that are ORed with next address
<03:00>.

Table
MUX SEL

MUX

NOT.INT.
MEM

14-1
MUX

MBox Branch
2

MUX

CP.BW.HIT

Conditions
1

ABUS.REFL.
REQ

MUX

W.EQ.1/NO.BK.HT
OR

(NO.CACHE.HIT

* LAT.RD.CYC
* W.EQ.1)
1

ARRAY.BUSY

IO.WRT

REFL.PROG

CACHE.HIT

PAMM.SEL.

W.EQ.1.

ABUS

CACHE.ON

REFL.PROG

TAG.PERR

I0.MASK

BLK.HIT

IO.WRT

CACH.DAT.

ABUS.XFR.

PA3

PERR

{

TAG. PERR

LAST.WD

CQOFF

BYT.WRT

NEXT.ABUS

ADR.ERR.

DATA.ERR, LAT

LAT

ARRAY.BUSY

CP.WRT

REFL.PROG

14-16

BLK.HIT

MBOX

MBOX MICROCODE

CLEAR FLAGS<0>

When set, this bit clears the ABUS REFILL REQUEST and
REQUEST flags used in MFORK address arbitration.

REFILL

for

-ABUS MFORK ENABLE<O0>

This bit is asserted to

cause

return

request, and has the following encoding:
enable

MFORK

DMA

ABus

do not enable ABus

NEXT ADDRESS<7:0>

This field designates the next micro address, which may be ORed
with the branch conditions, or modified by the arbitration logic
or stack

14.3

logic.

MBOX MFORK ENTRIES

Table 14-2 is a list of the MBox micro address entries for
conditions.

Table 14-2

02:
06:

M.DIAG.READ.IOA
M.BUFF.DONE

OB:
0C:
0D:
OE:
OF:
10:
12:

M.PROBE.READ
M.READ.MBOX.REG
M.READ.PTE.TAG
M.READ.PTE
M.SWEEP.CACHE
M.WRITE.EMD
M.DIAG.WRITE.IOA

07:

14:

MBox Entries on MFORK

M.ABUS.DMA.REQ

M.CACHE.READ.PAR.ERROR

16:
17:
18:
19:
1A:
1B:
1C:
1D:
l1E:
1F:

14-17

M.CP.REFILL
M.ABUS.REFILL
M.IDLE

M.CP.CACHE.READ
M.CP.CACHE.WRITE
M.PROBE.WRITE
M.WRITE.MBOX.REG
M.CLEAR.TB.ENTRY
M.WRITE.PTE
M.CLEAR.CACHE

MFORK

MBOX

CYCLE

14.4

CONDITION

MBOX CYCLE

CODE

MICROWORD

CONDITION

CODE MICROWORD

ABDRESS [HEX)

BATA (HEX

MBOX CYCLE CONDITION CODE (CYCLE) MICROWORD

(uwD FORMAT

EXAMINE FROM CONSOLE >>>E/CYCLE ADDRESS
a1

MICAOWORD BITS <31 00>
Meee

THERE ARE NO PHYSICAL BITS PRESENT)

)

Fggg&sa

PROBE

0SS
Check

Figure

14-12

MBOX CYCLE CONDITION CODE (CYCLE] MICROWORD
0

Cycle

!
0%

Code

14-13

This

—

reflects

Cycle

the

£5

Microword

RESERVED (NO PHYSICAL BITS)

Condition

party

Code

calculated

ROT

ENABLE

DEST

CACHE

READ

ENABLE

ALIGN

CHECK

PROBE

ADDRESS

WRITE

| CACHE

FROM

Worksheet

MICROWORD BITS <3116>

MBox

-I0 ACC

?,fizt

L gAfi {

Microword

~DEST

g{iig

<10

—SECOND

<31:16>

<00>

bit
-NO

Figure

1
| —secnip

—nO
MOoIFY | CHECK | WRITE | ROT

PHYSICAL BIT NUMBERS

PAR

~DESTCP <1 0>

T
DEST CP<1 0

ENNBLE

Condition

i
;‘gg

oask | Rean

NEXT ADDRESS FIELD (USED ONLY BY UCODE ASSEMBLER
i

MCCC
27

THERE ARE NG PHYSICAL BITS PRESENT

)

!
SMABLE | cacke

(ULD FORMAT)

EXAMINE FROM CONSOLE >>>E/CYCLE ADDRESS
31

l PR I

MBox

RESERVED INO PHYSICAL BITS)

TENPAGE
BOUNDARY

fock | TioN
CHECK
.

ACCESS
VIOLA.

[

NEXT ADDRESS FIELD (USED ONLY BY UCODE ASSEMBLER,

L[|

IVA

LOCK

14-18

the

following

fields:

MBOX

MBOX CYCLE

CONDITION

CODE

MICROWORD

-DEST CP<1:0>

This bit

specifies

current request.

the destination of

the

RESPONSE

the

The field has the following encoding:

0
1

= IBF
= OP FETCH

EBOX

IBF FROM OP

-SECOND REFERENCE<00>

This bit
second

reset to

reference

MBOX CYCLE CONDITION CODE (CYCLE} MICROWORD

ocK | TION

CHECK
80

ACCESS | _
viotA- | meap

ADDRESS | ¢p

PAR | proge | FROM

to the MBox logic that

this

MICROWORD BITS <15:00>

(ULD FORMAT)

EXAMINE FROM CONSOLE: »> > E/GYGLE ADDRESS

indicate

request.

check
73

MCCC

[CROSS

EN PAGE
|BounpARy| ENABLE | cacye | Z10
CHECK
L

READ | Enapie
57

T
DEST CP<1:0>
Lo,

WRITE | CACHE | —NO

MODIFY | CHECK | WRTE | ROT
53

PHYSICAL BIT NUMBERS

Figure

14-14

MBox Cycle Condition Code Microword <15:00>

CP PAR A<O00>

This bit reflects the parity calculated on the following fields:
WRITE

CHECK

DEST CP

BOUNDARY CROSS

PAGE

CHECK

READ CHECK
ACCESS

VIOLATION

SECTION

CACHE

CHECK

REFERENCE

WRITE

CP MODIFY

-DEST CP 0
-DEST

PROBE<00>

This bit specifies a TB PROBE request.

14-19

MBOX
MBOX

CYCLE

ADDRESS

CONDITION

FROM

This bit

CODE

MICROWORD

IVAK00>

specifies

that

this

an ADR FROM

that

this

IBOX VA cycle.

CP LOCK<00>

This

bit

ACCESS

This
WRITE

specifies

CP LOCK request.

VIOLATION CHECK<00>

bit

enables

the

access

violation RAM when a

READ

CHECK

specifies
that
a
read
access
violation
and is asserted with ACCESS VIOLATION CHECK.

check

CHECK

required.

READ CHECK<00>

This

bit
required,

PAGE

This

bit

BOUNDARY CROSS

enables

the

CHECK<O00>

Crossing

Page

Boundary

trap.

ENABLE ALIGN CHECK<00>

This
bit
enables
Longword Alignment

CACHE

longword

alignment

references

trap.

cause

READ<00>

This bit
from the

is asserted whenever
cache.

the

EBox or

14-20

IBox

requests

read

MBOX

MBOX CYCLE CONDITION CODE MICROWORD
-I0 ACC

ENABLE<K00>

When

this

IBUFF

bit
OP

port

reset
read

(asserted
requests

low)

will

enable

trap

the

check

space.

DEST CP<1:0>

This

bit

current

specifies
request.

0
1
2

IBF

EBOX

IBF

the destination of
The

field

has

the

following

RESPONSE

encoding:

FETCH
FROM

CP MODIFY<00>

This

bit

specifies

CP MODIFY request.

WRITE CHECK<00>
This

bit

specifies

that

write

access

violation

required.
The
bit is asserted with ACCESS VIOLATION CHECK.
It
is also used whenever an M Bit check is required, and is asserted
with CACHE WRITE.

CACHE WRITE<O00>

This bit is asserted whenever
to the cache.

the

EBox

IBox

requests

write

alignment

checks

-NO ROT<K00>

When

for

reset (asserted
EBox requests on

low) this
the first

bit

inhibits
reference.

14-21

MBox

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14.5
MBOX

Q9v3i4y

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dOW

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MBOX

MBOX
REGISTERS

REGISTERS

5A3NI4

HH3

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LAVIN

_EL OL

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14-22

05f

MBOX

MBOX REGISTERS
|

ADR

NAME

ADDR

|
||

FORCE

CONTROL

)

FORCE

CACH
MISS

)

cvL

| CACHE1

| CACHEO

:
ADDR

ADRRAM |

EVNTB

| GENTB

DIAG

TAG PAR

CONTROL

| GENEVN

VALERR

GENEVN
PAPAR
HEG
MCA

MAPP

ADDR

| _

~CACHEO |

-CACHE

RO gratus | TTBMIT | BLKHIT | UGMAT | HIT

STATUS

34 AW ERREN

pres

PAMM

RW PAMM

PTE A

TB TAG

TEBVALERR | pARERR | PARERR | - PARERR

CONFA

PAMM

CONF8

PAMM

CONF4

PAMM

CONF2

PAMM

CONF1

|ram
|waAP9

ERROR
ERRO

ADA.B
MCA
.
mca

w
,
PHYSICAL ADDRESS IN PA LATCH WHEN ERROR DETECTED

1-2

MR-13148

Figure

ADR

14-16

NAME

MAP Module MBox

mcc

Registers

RW CONTROL
1

MCC
RO STATUS
1

ARY

MEM

)

|LAT DEST|LATDEST|
CP1
CPO

STATUS

mce

cp
BYTE

WRITE

AB
BAD

DATA
ERROR

ucyc
TYP 3

| ucvc
TYP 2

| ucyc
TYP 1

LABUS | LABUS |

CPR

LABUS | LABUS

cMD | INH ARY | 10A
BAD | CORR
DIAG
PAR

| REP

. ABUS | .ABUS | = ABUS

perre | perra | OAT

| MSKO

BERR

LCNTL

ADR'

PERR

IN PROG |

MEM
MAN EN

ABUS

CMD

SEL

cno

&
»

;

LABUS |

mccJ

REQ

MCC

| WDCNT | WD CNT
3
2

LABUS |

INH
DMA

CRA
MCA

| uCYC
TYPO

| STAT1 | STATO | MSK3 | MSK2 . | MSK1

RO STATUS

VSO

mMcc
18 RW CONTROL

INH

ACCESS | OVRLP

e RW B

REP

MCCJ

Mee

;

)

RW ERROR

MULTIPLE
ERROR

TAG

ENAB

MCC

fSTATU S

CHE

)

TAG
W
PERR

W BRCH

CP
NXM | LATBUF
ERR
ERR -

PERR

ABUS

MEMORY
LOCK

MA-13158

Figure

14-17

MCC Module MBox

Registers

14-23

MBOX
MBOX REGISTERS

ADR

NAME

DATA
CONTROL

CACHE

PERR3

RwW

INH BAD
DATA
FLAG

RATA
CONTROL
2

| CACHE

| CACHE | CACHE
| PERR2 | PERR1
PERR O

INV

DISAECC|

EN CACH
| BYTE
PERR

UFO
MCA

RwW

DATA

STATUS

CACH | cache1 | any
DAT
PERR

DAT
'

|CACH DAT Mmcou

REFILL |BYT WR
PERR

DATA
ERROR

DATA

DATA INVERT

CHECK
INVERT

DATA
SYNDROME

DATA
RO

ECC
ERROR

DATA

ca4

ECC

SYNDROME

MCA

MCDM

DATA

BAD

ERROR

MULTIPLE|

DATA

pATA

4
DATA

ooe | ADR PAR
ERR

31
78

DATA
ERROR

DATA
LWP
INVERT

INVERT
32

ENABLE

00
MDP

DATA WORD USED DURING READ

MCA

MCD1-3

MMI1015Y

Figure

14-18

MCD Module MBox Registers

14-24

MBOX
MBOX

MSTATI

MSTAT2

T1b

Zb”

T16

16 ¥5
Mcc

CRA

CRB

2¢C

REGy |

MAP

MERG

CSHUCTL

T17

T18

Tig

00
MCD

UFO

mcc

REG

CRA

CRB

MCD

MDECC

J
MAP

REGISTERS

MCD

ECC

mcc

MAP

CRB

REG

MAP

REG
04

MEAR

T1A

MAP

ADA/ADB
7C

MEDR

T1B

MCD

MDP
78

MCC

MCCTL

MCC
MENA

MCC

CRA

ocC

MCD

MDCTL

CRA

MCD

UFO

MAP

MCD

CRB

REG

UFO

MR-13180

Figure

14-19

EBox

Microcode

14-25

Assembly

MBox

Registers

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MBOX

REGISTERS

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MBOX

ABUS

INTERFACE
ADDRESS/DATA

DATA LENGTH/

ADDRESS/DATA

STATUS

PARITY

CONTROL l COMMAND/MASK
D D (l | l l l [J fDOQO l LONGWORD ADDRESS l
3

PARITY

28 27

COMMAND

——

((0001 ) READ
{ 0010) ) READ LOCK
(0100) READ MODIFY
{ 1101) ) WRITE MASK

— (1110) ) WRITE MASK UNLOCK

DATA LENGTH

|
—

(01) EVEN WORD
(10) ODD WORD

(11) LONG WORD
#MR-15855

Figure 14-22

ADDRESS/DATA

PARITY

ABus CPU Command/Address Cycle Format

DATA LENGTH/

STATUS

CONTROL l
PARITY

COMMAND/MASK
3

l l

ADDRESS/DATA

28 27

rGG{}Q 1 LONGWORD ADDRESS i

COMMAND

| (0001) READ
| (0010) READ LOCK
L (1000) WRITE

__ (1101) WRITE MASK
[ (1110) WRITE MASK UNLOCK

DATA LENGTH

(00) LONGWORD

—
L

(01) QUADWORD
(10) OCTAWORD
#R-15856

Figure 14-23

ADDRESS/DATA

PARITY

ABus DMA Command/Address Cycle Format

DATA LENGTH/

STATUS

CONTROL 1
PARITY

[:Ij

CGMMAND/MASK
0

[ll ]

ADDRESS/DATA

2423

1615

0807

lBYTESlBYTEZ[BYTE1lBYTEG]
LONGWORD ALIGNED DATA
MR-14978

Figure

14-24

ABus Read/Write Cycle Format

14-28

MBOX

ABUS

Table

14-3

A
|

Signal

Name

ABus

Signal

ABus

Backplane

STM

SBA

‘

3/5

Location
CPU

Backplane

MCD

MAP

Conn

MCC
18

NT 2

ABUS

ADR

DATA

C39

C80

J1803

J1804

ABUS

CMD

MSK

B15

C42

J1621

J1622

C1l0

ABUS

CMD

MSK

Bl18

C47

J1625

J1626

Cl2

PTY

C35

A37

ABUS

CMD MSK

B17

C40

J1é6l5

J1616

ABUS

CMD

cos8

B20

C51

J1631

J1632

Cl4

MSK

ABUS

CPU

BUF

DONE

ABUS

CPU

BUF

ERROR

ABUS

CTRL

ABUS

PTY

C90

cC31

J1531

J1532

C87

C46

J1623

Jl624

c09

C83

(63

J1715

J1716

C37

B36

DATA ADDRS

B32

C07

Jl433

J1434

AO05

ABUS

A0S

DATA

ADDRS

B29

CO08

J1435

J1436

AO07

ABUS

A07

DATA ADDRS

c28

CO09

J1437

J1438

A09

ABUS

A09

DATA ADDRS

C30

C10

J1439

J1440

Al2

All

ABUS

DATA

ADDRS

c32

Cl11

J1441

Jl442

A20

Al9

ABUS

DATA

ADDRS

C34

cC18

J1443

J1444

A2]1

ABUS

A2l

DATA

ADDRS

B24

C10

J1511

J1512

A57

ABUS

DATA

AS7

ADDRS

B26

C20

J1513

J1514

A60

AS59

B25

C21

J1515

J1516

A64

A63

ADDRS

B28

C22

J1517

J1518

A65

ADDRS

A69

ABUS

DATA

ADDRS

ABUS

DATA

ADDRS

ABUS

DATA

ADDRS

ABUS

DATA ADDRS

B27

C25

J1519

J1520

A70

B30

C26

J1521

J1522

B09

BO9

B19

cC27

J1523

J1524

B15

BI1S5

B22

(C28

J1525

J1526

B1l7

B17

C29
C30

J1527
J1529

J1528
J1530

B19
B87

B19
B87
B57

ABUS

DATA ADDRS

ABUS
. DATA ADDRS

ABUS

DATA

ADDRS

ABUS

DATA

ADDRS

ABUS

DATA

ADDRS

ABUS

DATA ADDRS

ABUS

DATA

ADDRS

ABUS

DATA

ADDRS

ABUS

DATA ADDRS

ABUS

DATA ADDRS

ABUS

DATA ADDRS

b vfile

ADDRS

B34

C32

J1543

J1444

B57

B35
B36
B37

C35
C36
C37

J1601
J1603
J1605

Jl1602
J1604
Jl1606

B59

BS59

B63
C71

B63
C37

B38

(C38

J1607

J1608

B73

C31

B39

(C39

J1613

J1614

CO08

B40
B41

C41
C49

J1619
Jlez27

J1620
J1628

C10
Cl1

CO07
CO09
C91

B42

(53

J1639

J1640

C21

B44
B45
B48

C54
C66
C67

Jl641
J1721
J1723

J1642
J1722
J1723

C24

C77

C54

(C53

C56

C55
B28

fo s 3w s e o e o}

DATA ADDRS
DATA

b wfin s R« sl o

ABUS
ABUS

B21
B31

s
o lia s I

ADDRS

DATA
DATA

bust o

DATA

ABUS
ABUS

ARIS

— qomnil

INTERFACE

(85

ABUS

DATA ADDRS

BSO

€68

J1725

J1726

ABUS

C57

DATA

ADDRS

B52

C71

J1731

J1732

ABUS

DATA ADDRS

C63

B8l

C42

C73

J1733

J7434

C65

ABUS

DATA ADDRS

B41

C74

J1735

J1736

C69

A77

A0331 J1509

J1510

'}ABUS DEADO L

/ ABUS DEADI

A0531 J1501

J1502

A0252

A0240

ABUS

DMA

DONE

C0364

J1717

J1718

ABUS

C39

DMA

DONE

DMA

DONE

H
H

C0564

ABUS

J1705
31703

J1706
J1704

c29
c27

ABUS

DMA

DONE

J1707

J1708

C32

14-29

MBOX
ABUS

INTERFACE

Table
ABUS

IPR RETURN

0 H

1
2
3
4

H
H
H
H

ABUS
ABUS
ABUS
ABUS

IPR SELECT
IPR SELECT
IPR SELECT
IPR SELECT

0
1
2
3

I
H
H
H

ABUS
ABUS
ABUS
ABUS

IPR RETURN
IPR RETURN
IPR RETURN
IPR RETURN

ABus Signal Pin Location (Cont.)

14-3

C38

cge
c37
C35
C36

J1739

J1740

C0575

C0390 J1807
C0590 J1801
J1809
J1541

J1808
J1802
J1810
J1542

co584
c0581
C0586
c05438

C76

C75
C717
C78
(88

C0573
C0576
c0578
Cc0583

J1738
J1742
J1744
J1806

J1737
J1741
J1743
J1805

C62
C60
B85
co02
co4

ABUS LEN STAT O I
ABUS LEN STAT 1 H
ABUS MEMORY LOCK H
ABUS MSKED CMD H
ABUS WR CMD H

C40
c84
c89
A48
A49

C40
C69
CO05
CO4
CO06

J1729
J1727
J1429
J1427
J1431

J1730
J1728
J1430
J1428
J1432

MCC ABUS CPU BUF SEL H
MCC ABUS DMA ERROR H

c85
B49

C55
C60

J1643
J1711

Jl644
J1712

C24
C36

Cc0357 J1701
C0557 J1609
J1617
J1l611

J1702
J1l610
J1l618
J1l612

C25
Cc03
co7
CO05

J1719
J1713
J1709

J1720
J1714
J1710

C25
C35
co3

C0352 J1635
C0552 J1629
J1633
J1637

J1636
J1630
J1634
Jl638

c20
Cl1
c1l7
Cl9

MCC ABUS
MCC ABUS
MCC ABUS
MCC ABUS

IOA SELECT 0 H
IOA SELECT 1 H
IOA SELECT 2 H
IOA SELECT 3 H
Cc88
C31
c29

MCC ABUS MBOX OUT H
MCC ADDRS CTRL 0 L
MCC ADDRS CTRL 1 L
SB ABUS
SB ABUS
SB ABUS
SB ABUS

IOA REQUEST
IOA REQUEST
IOQA REQUEST
IOA REQUEST

0
1
2
3

H
H
H
H

C65
cCe2
C59

NOTE

"SBA
The pin number under the column titled
refers to the signal pin for both slots
3/5"
in which
3 and 5 unless it is 5 characters,
the SBA module in one
it designates
case
particular slot.

Under the column titled "MCC 18", if the pin
is 5 characters, then the signal
designation
but
to the MCC module,
connected
is not
in the slot
module
another
to
rather
identified by the pin number.

under the
slot
the

The numbers
to
refer

particular modules,

module

(ABus

MCD module

module designations
the
for
number(s)

as slot

for

the

STM

backplane) and slot 16 for the

(CPU backplane).

14-30

MBOX

ABUS

14.7

ABUS

INTERFACE

following sections
their meanings.

During

provide

read
the

or write

data

between

ABus

cycles,

the

DATA/ADDRESS

PARITY--0dd

data/address

field.

interface

MBox

parity

these

and

signals

and

bi-directional

SBIA

according

Table

Command/Mask
<03:00>

Table

14-4

computed

over

the

cycle,

ABus

Read

0010

CPU/DMA

Read

0100

Read modify

1000
1101

Write

mask

Write

mask

wused

set,

the

During

DATA

cycles

specify

data

CPU/DMA

CPU

byte

bits

are

the

byte(s)

are

written.

cycles,

cycles

14-=5

Length/Status

10
11

not

bits

indicate

the

data

for

CPU

Command/Address

Function

Even Word
0dd Word
Longword

14-31

and

bit

are

CPU

<01:00>

MASK bits

Cycle

Length/Status

bits,
If

the

according

14-6.

Table

MASK

written.

<1:0>--These

Command/Address

CPU/DMA
CPU/DMA

unlock

these

which

return

LENGTH/STATUS

the

DMA

corresponding

read

during

Table

lock.

Write

are

these

Commands

0001

data

bit

14-4,

Command
Application

1110

command

Command

During write

bits

SBIA.

COUMMAND/MASK <03:00>--During a Command/Address
bi-directional
four
bits
indicate
the ABus

MBox

the

DATA/ADDRESS <31:00>--During
Command/Address
cycles,
these
bi-directional
bits
will
carry
a
28-bit physical address
between the MBox and SBIA.
The most significant 4 bits
will
be 0.

carry

SIGNALS

The

INTERFACE

Table

used.

length

14-5

Command/Address

and

MBOX
ABUS

INTERFACE

SIGNALS

Table 14-6

Length/Status

for

DMA

Command/Address

Cycle
DMA

Length/Status

Command/Address

<01:00>-

Function

00
01
10

Longword
Quadword
Octaword

(4 bytes)
(8 bytes)
(16 bytes)

NOTE

The SBIA only supports Longword and

Quadword

transfers.

the
of
status
the
During Data cycles, these bits indicate
bits only have meaning during a CPU read
Status
The
data.
Normally zero, they will be "11" to indicate bad
data cycle.
data, if the SBIA received Read Data Substitute (RDS), during
the SBI read data cycle (SBI data cycle mask bits = 0010).
CONTROL PARITY--Odd parity computed
and Command/Mask

over

the

Length/Status

bits.

ADus
the
MSKED CMD--This bit, when set, tells the MBox that
command
is
for
a
masked
operation.
It
allows the MBox
the
microcode to branch before decoding the command field in
command/address.

ABUS WR CMD--~Like the MSKED CMD, ABUS WR CMD allows the

MBox

to branch before decoding the command field in the
microcode
command/address.
This bit indicates that the ABus command is
for a write

operation.

CLK SBA[N] CLOCKS5 141 B[D]--Each I/0 adapter
receives
clock
signals from the KA86 system clock module to control the ABus
interface

logic.

CLK SBA[N] RESET--A reset signal to each of the I/O
adapters
used
to
initialize
the
<clock
generation and distribution
logic.

IOA REQUEST <03:00>--One line from each I/0 adapter
request the MBox to service a DMA.

used

DMA DONE <03:00>--A signal to each of
the
1I/0
adapters
to
signify
that
the MBox has completed the DMA transfer.
Only
the 1/0 adapter that had a DMA being
serviced
will
receive
the
DMA DONE.
1In case of a DMA err?r, DMA DONE will be sent .
with DMA ERROR.
‘
.
i

indicate
to
DMA ERROR--A signal to each of the I/O adapters
‘that the MBox has detected an error while processing the DMA.
DMA ERROR is sent at the same time as DMA DONE.

14-32

ABUS

ADDRS

CTRL

<01:00>--These

two

signals

MBOX

ABUS

INTERFACE
are

SIGNALS

used

1in

the

selected
1I/0
adapter
to
control
the loading, holding, or
incrementing of the DC022 register file address, according to
Table 14-7.
These bits are asserted low, and in the table, a
logic 1 indicates an asserted signal.

Table
ADDRS

14-7

Address

CTRL

Control

the

Function

0
0
1
1

Hold address
Increment address
Not used
Load address

0
1
0

OUT-—-MBox

file,

for

be read
control

OUT

the

controls

whether

the

I/0

adapter

selected

ABUS

I/0

or written.
It
the
two least

by the MBox
data
will

adapter.

sending data

the

ABUS

CPU

SEL--This

OUT,

the

BUF

control

selected

Table

14-8

not

the

I/O

signal

adapter

DC022

used

along

file

(see

adapter

address

with

14-8).

File

Address

ABUS MBOX

ouT

ECL

**00

OUT
I/0
be

Address

the

MBOX
MBox

Control

Comments

Prepare

the
0

will

ABUS

loaded

Table

BUF

IOA SELECT,

MBox.

the

1/0

adapter

(see Table 14-8).
If ABUS MBOX
be
driven
by
the MBox to the

asserted,

ABUS CPU
SEL

File

is also used with ABUS CPU BUF SEL to
significant bits of the DC022 address

being loaded
is
asscrted

DC022

<01:00>

MBOX

DC022

**00

read

DMA C/A

Prepare

write

CPU C/A or an
ABus diagnostic
cycle
1

0011

Prepare

the
data

0010

The upper two bits are determined
buffer that requested service.

14-33

the

DMA

to read
read

return

Prepare

the
* %

CPU

word

write

CPU C/A
transaction

MBOX

ABUS

INTERFACE

SIGNALS

CPU BUF DONE--Asserted by the I/0 adapter to inform the
MBox
that
a
CPU
read
or
write transaction is complete.
A CPU
write
1s
complete
when
the
NEXUS
has
acknowledged
the
command/address
and write data.
A read is complete when the
read
will

data is placed
be asserted if

in the DC022 register file.
CPU BUF ERROR is asserted.

CPU BUF

DONE

CPU BUF
adapter

ERROR--CPU BUF ERROR is asserted by the selected
TI/0
to
indicate
to the MBox that an error was detected
during a CPU initiated I/0 transaction.
It
indicates
that
the I1/0 adapter aborted the command.

MEMORY LOCK--A bi-directional

adapters

signal

that

line between
an
interlock

the

MBox
and
operation
1is

1I/0

progress.

ABUS

IPR RETURN <04:00>--The encoded
value
of
the
highest
priority
1interrupt the I/0 adapter has pending, when the I/O
adapter is polled by the EBox with the assertion of ABUS
1IPR
SELECTI[N].

ABUS

IPR SELECT([N]--ABUS

poll

each

EBox

polls

the

ABUS

ENABLE--This

MCSR1<01>.

the

I/0

bit

When

IPR SELECT
adapters

adapters

1is

this

for

modulo

used

controlled

bit

pending

the

EBox

interrupts.

to
The

order.

asserted,

the
the

console

I/0

with

adapters

are

enabled.

ABUS DEAD[N]--This
assertion
of
SBI

bit
1is
FAIL and

asserted
as
a
used to forward

from another processor on the CI to the
the console of an SBI power failure.

LO--A

signal

indicate
adapter

LO=--DC

force

14.8

that

the

EMM

power

assert

BUS

SBI

FAIL

the

EMM

from

initialize

within

the

failures.
on

used

the

I/0

result
reboot

console,

I/0
It

the

SBI.

assert

adapters
is

used

BUS

SBI

of
the
request

inform

wused

the

I/O

DEAD

and

adapters.

MBOX TESTPOINTS

14.8 .1
Tabl e

from

impending
to

MBox

14-9
may

cont rol

is
be

MicroPC

list
used

and ABus

Control

Testpoints

of MBox microPC and ABus control
testpoints
when troubleshooting MBox microcode and ABus

problems.

14-34

,
MBox MicroPC

Table

Channel

}

E
D
C
B
A
9
8
7
or
6
or
5
4
3
2
1

MBox MicroPC and ABus

MUPC O H

MCCD-H

(LSB)

1 H
2 H
3 H
4 H
5 H
6 H
7 H
(MSB)
IOA REQ O H
IOA REQ 1 H
IOA SEL O H
IOA SEL 1 H
ADR CTL 1 H
ADR CTL 0 H
MBOX OUT H
WR CMD H

e o e

Ss31
MCCK

MBOX
Testpoints

Section/Slot/Pin

MCCD-H
MCCD-H
MCCD-H
MCCD=H
MCCD-H
MCCD-H
MCCD-H
SBAS
SBAS
SBAS
SBAS
SBAS
SBAS
SBAS
SBAS

SS31 FAULT OR ERROR H
CLOCK

Control

Control Testpoints

Signal Name

MUPC
MUPC
MUPC
MUPC
MUPC
MUPC
MUPC
ABUS
ABUS
ABUS
ABUS
ABUS
ABUS
ABUS
ABUS

0
CLK

14-9

and ABus

Exx.13

Exx.14
Exx.15
Exx.16
Exx.17
Exx.09
Exx.10
Exx.11
C03.52
C05.52
C03.56
C05.56
C03.59
C03.62
C03.65
C03.06
e

(ECL)

(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)

B02.49
E51.12

(TTL)
(ECL)

for

MBox

NOTE

"Exx"

indicates

any

RAM

chip

microcode.

.
b

14.8.2

To display the MBox uPC in HEX,
MSB and MUPC 0 is the LSB.

MUPC 7 is the

ABus/SBIA Testpoints

Table 14-~10 contains a list of ABus signals and SBI FAULT,
can be used when troubleshooting SBI FAULT/ABus problems.

Table

Channel

14-10

which

ABus/SBIA Testpoints

Signal Name

Section/Slot/Pin

0
1
2
3
4
5
6
7
8
9
A

SS831
ABUS
ABUS
ABUS
ABUS
ABUS
ABUS
ABUS
ABUS
ABUS
ABUS

FAULT OR ERROR H
IOA REQ H
IOA SELECT H
ADR CTL 1 L
ADR CTL O L
MBOX OUT H
WR CMD H
MASKED CMD H
DATA/ADR 00 H
DATA/ADR 01 H
DATA/ADR 02 H

SBS
SBA
SBA
SBA
SBA
SBA
SBA
SBA
SBA
SBA
SBA

B02.49
C03,.52
C03.56
C03.59
c03.62
C03.65
C03.06
C03.04
C03.07
C03.08
C03.09

(TTL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)
(ECL)

ARUS

DATA/ADR

SRA

c03.10

(ECL)

SBA

C03.46

(ECL)

C
D

ABUS BUF

ERROR H

14-35

MBOX

CP Port

Testpoints

14.8.3

CP Port Testpoints

Table

14-11

contains a

Table

Channel

list of CP port

14-11

testpoints.

CP Port Testpoints

Signal

Name

Section/Slot/Pin

MCC OP

PA ACK A H

MCCé

1
2
3

MCC EBOX PA ACK A H
MCC IBF PA ACK H
MCC MD RESP C H

B18,39
B18.41
B18.37
cl18.75

4
5
6
7

MCC
MCC

PORT
PORT
MCC PORT
MCC PORT

STAT
STAT
STAT
STAT

CODE
CODE
CODE
CODE

MCCé
MCC6
MCC5

3 H
2 H
1 H
0 H

MCC7
MCC7
MCC7
MCC7

14-36

B18.20
B18.25
B18.,11
B18.18

CHAPTER

SBIA

15.1°

SBIA GENERAL

INFORMATION

The

SBIA is configured/cleared during CPU initialization
by
the
INIT/PAMM console command.
This command is required to reset the
SBIA.
The SBIA must be configured prior to attempting any access
to the SBI for an UNJAM or depositing/examining nexus control and
status
registers.
Therefore,
to
reset
the
1I/0
world, . the

following

sequence

>>>INIT/PAMM

>>>UNJAM

>>>INIT

For

example

SBIA SBI

15.2

SILO

console

SBI

SILO

commands must

interpretation,

executed.

refer

Chapter

20,

description.

SBIA JUMPER SETTINGS

The
is

SBIA has two DC10l1 chips used for SBI arbitration.
One DC101
used
to gain control of the SBI for CPU deposits/examines of

SBI

nexus

control

to
gain
control
applicable nexus.
the SBIA DC1l0ls.

and

status

of the
Table

Table

registers.

The

SBI to transfer
15-1 shows the

15-1

SBIA DC10l1l

other

the DMA
jumper

DC101

used

read word to
information

TR Jumpers

Transmit
,

TR SEL

Jumper

from XMIT

TR L,

C83* to
BUS SBI

TR ___on

Pin___

DEVICE
TR

Jumper
Needed

LLLL

——

LLLH

Yes

LLHL

Cc81

Yes

14
13

c77
C73

LHH

LHLL

Yes

C75

LHLH

Yes

C71

LHHL
L

HHH

HLLL

Yes

Cc69

Yes

ce67

Yes

Cé65

HLLH

Yes

HLHL

Yes

‘

15-1

Cé63

C59

the
for

SBIA

SBIA JUMPER SETTINGS

SBIA DC101 TR Jumpers

Table 15-1

Transmit
TR

Jumper

C83* to
BUS SBI TR __ on Pin____

TR SEL
8 4 21

DEVICE
TR

Jumper
Needed

HLHH
HHLL
HHLH

05
04
03
02
01=%

Yes
Yes
Yes

HHHL
HHHH

(Cont)

from XMIT TR L,

Cc57
C55
C51
C53
C47

05
04
03
02
01

Yes
Yes

*Jumper connections made on SBS backplane slots
Normal configuration for CPU DC101
Normal configuration for DMA DC101

15.3

SBIA BLOCK

DIAGRAM

e—

;

INTERRUFT
LOGIC

g?g{is’
MACHINE

SBAD

SBA O

READ/WRITE

CONTROL

——

SBAK. SBAL

|
§

S-DATA
ASSEMBLY

—»

SS41-47

O e

REGISTERS

SS 40

!
o

SBA 1-4

ABUS

INTERFACE

;

—

$501-5S05

16 X 40

SBI
INTERFACE

ASSEMBLY
,

ECL ADDRESS,

|
)

SB1

CONTROL

ARBITRATION

READ/WRITE

SBA 7

CHIPS

A8
'

$513-17

PROTOCOL

$509, 10,12

A-DATA

SBI

SS 19-32

—

58 07

DMA BUFFER

SBI

;

CONTROL AND

|
|

)
«—fREQUEST
SYNCHRONIZATION

‘Q\,Q’

CLOCK

SBAF-SBAI

GENERATION

SBAC

SBA

‘;\;;?

SBS
MR- 145

Figure 15-1

SBIA Block Diagram

15-2

SBIA
VAX 86XX PHYSICAL MEMORY ADDRESS ALLOCATION

15.4

VAX 86XX PHYSICAL MEMORY ADDRESS

ALLOCATION

HEX BYTE ADDRESS
SYSTEM

MAIN MEMORY
1FFF FFFF

2000 0000

I0AQ
21FF FFFF
2200 0000

I0A 1
23FF FFFF

| CHE| WY | VR

0000 0000
UPTO 512 MEGABYTES
IN 1 MEGABYTE
INCREMENTS

32 MEGABYTES

2400 0000

NOT

ASSIGNED

448

MEGABYTES

3FFF FFFF
MFA-14938

Figure

15-2

VAX 86XX Physical Memory Address
Allocation
’

|
|

15-3

SBIA

VAX 86XX PHYSICAL MEMORY ADDRESS ALLOCATION

HEX BYTE ADD

2x00
0000 [ TROO 8 KBYTES
1
2X00 1FFF

2X00
2000
2X00 3FFF | TRO1 8 KBYTES

4000
2X00
X0 sprr | TRO2 B KBYTES

2X00 6000

KBYTES

2X00 8000}

tRO4 8 KBYTES

2x00 7FFF | TRO3 81

2X00 9FFF

,
AQOO
2X00
S%00 BEFF | TROS 8 KBYTES
2X00
CO00
,
2%00 OFFr | TRO6 8 KBYTES
2X00 EO00

2%00 FFFF | THO7 8 KBYTES

2X01 0000

2X01 1FFF

TROS 8 KBYTES

| NEXUS REGISTERS
128 KBYTES

2X01 2000
2X01 4000

2x01 5FFF | TR108 KBYTES

2X01 6000

2X01 8000
2X01 SFFF

:
TR12 8 KBYTES

2X01 ADOO
o%01 arpr | TR13 8 KBYTES

2X01
CO00 | TR148 KBYTES
oxo1 oper
2X01 E0OO

%01 FreF | TR15 8 KBYTES

2X02 0000
2X07 FFFF
2X08 0000

UNASSIGNED

384 KBYTES

SBIA REGISTERS

512 KBYTES

UNIBUS O

256 KBYTES

UNIBUS 1
.

256 KBYTES

UNIBUS 2

256 KBYTES

UNIBUS 3

756 KBYTES

UNASSIGNED

30 MBYTES

2XOF FFFF

2X10 0000

2X13 FFFF
2X14 0000
2X17 FFFF

2%18 0000
2X1B FFFF

2%1C 0000
2X1F FFFF

2X20 0000
21FF FFFF

23FF FFFF

X=0FORSBIAO
X=2 FORSBIA1
MR-14335

Figure

15-3

I/0 Adapter Physical Address
Allocation

SBIA

" SBIA Register Addresses
15.4.1

SBIA Register Addresses

Table

15=2

SBIA Register Addresses

Hex Byte

Address

Configuration Register
Control Status Register
Error Summary Register
Diagnostic Control Register
DMAI Command/Address Register
DMAI ID Register
DMAA Command/Address Register
DMAA ID Register
DMAB Command/Address Register
DMAB ID Register
DMAC Command/Address Register
DMAC ID Register
SBI Silo
SBI Error Register
SBI Timeout Address Register
SBI Fault/Status Register
SBI Silo Comparator
SBI Maintenance Register
SBI Unjam Register
SBI Quadclear Register
Vector Registers

2X080000
2X080004
2X080008
2X08000C
2X080010
2X080014
2X080018
2X08001C
2X080020
2X080024
2X080028
2X08002C
2X080030
2X080034
2X080038
2X08003C
2X080040
2X080044
2X080048
2X08004C
2X080080

Vector Registers

2X0800B8

NOTE

For SBIA 0,

X = 0 and for SBIA 1,

15-5

X = 2

SBIA

SBI

PROTOCOL

15.5

SBI

P <1:0> (PARITY)

TAG <2.0> (TAG)

AV VAR

TR <15:00>

INFORMATION TRANSFER

1D <4:0> (IDENTIFIER)

M <3.0> (MASK)
B <31:00> (INFORMATION)

NN/

ARBITRATION

PROTOCOL

RECEIVE

NEXUS

FAULT

CNF <1:0> (CONFIRMATION)

N2+

TRANSMIT/

RESPONSE

CONTROL

TRANSMIT/
RECEIVE
NEXUS

UNJAM
FAIL
DEAD

VAVANS
ANV e I

INTLK (INTERLOCK)

CLOCK (6 LINES)

INTERRUPT REQUEST

MP1-2
SPARE (2 LINES)

AVAVA

ALERT

MR-14968

Figure

15-4

SBI

Signal

15-6

Names

SBIA
SBI

Table

15-3

PROTOCOL

SBI Signal Names and Description

Arbitration Group

Arbitration Field
[TR<15:00>] -- Establishes
a
fixed
priority
among nexus for access to and control of the information transfer
path.

’

Information Transfer Group

Information
Field
[B<31:00>]
transfer data, command/address,

-- Bidirectional
lines
that
and interrupt information between

nexus.

Mask Field
[M<03:00>] -- Encoded to indicate that
a
particular
byte
within
the
data field is to be read or written.
With the
read data, the mask bits indicate if the data is
correct
or
in
error.

Identifier Field
[ID<02:00>] -- Indicates the logical
destination of information contained in B<31:00>.

source

Tag Field
[TAG>02:00>] -- Determines if the SBI cycle
command/address, read data, write data, or ISR,

Response

Group

Confirmation Field
its

for

response

|[CNF<01:00>]

to an SBI

no response

acknowledge

busy

4.,

error

Function Field
function
field

-~ The receiving nexus specifies

cycle:

[F<03:00>]
1is
bits

-~ Specifies the
command
code.
The
<31:28> of the command/address (Figure

15"6) »

Parity Field
[P<01:00>] ~-- Indicates even parity
over
the
SBI
information.
P0
is
computed
over the information in B<31:00>
while Pl is computed over
M<03:00>,
1ID<04:00>,
and
TAG<02:00>

(Figure 15-5).

Interrupt

Request

Request Field

Group

[REQ<07:04>] -- Each signal represents a‘level

[ALERT] -- A

priority whereby a nexus requests

Alert

Field

interrupt due

to a power

signal

loss.

15-7

interrupt service.

that

allows

SBI memory

SBIA

SBI PROTOCOL

SBI Signal Names and Description (Cont)

Table 15-3

Control Group

Clock Field

[CLOCK] -- Six control lines that provide the

clock

Fail Field

|[FAIL]

-- The assertion

within

nexus

Dead Field

[DEAD]

-- The assertion

within

nexus

signals necessary to synchronize SBI activity.
causes the assertion of SBI FAIL.

causes the assertion of SBI DEAD.

Unjam Field

[UNJAM]

Interlock Field

-- A reset signal to all SBI nexus.

[INTLK]

-- A signal that indicates that a shared

location is being modified by a nexus.

Unused Signals

Multiprocessor
Spare

[MP<02,01>]

-- Two unused lines

[SPARE<01:00> -- Two additional unused lines

B <31:00>
S

l TAG ’l l
TAG <2:0>

l l MASK l

ID <4:0>

M <3:.0>

!‘

;

FUNCTION

ADDRESS

F <3:0>

A <27:00>

TAG <2:0> = 011 = COMMAND/ADDRESS FORMAT
ID <4:0> = LOGICAL COMMAND SOURCE
M <3:0> = COMMAND DEPENDENT
F <3:0> = COMMAND CODE

A <27:00> = READ/WRITE, ADDRESS OF INTENDED NEXUS
BAR-18970

Figure 15=5

SBI Command/Address Format

15-8

]
]

F <3:.0>

A <27:00>

MASK

FUNCTION

UskE

CODE

DEFINITION

IGNORED

Q000

RESERVED

USED

0001

READ MASKED

USED

0010

WRITE MASKED

IGNORED

o011

RESERVED

USED

0100

IGNORED

0101

RESERVED

IGNORED

0110

RESERVED

USED

0111

INTERLOCK WRITE MASKED

IGNORED

1000

EXTENDED READ

IGNORED

1001

RESERVED

INTERLOCK READ MASKED

1010

RESERVED

USED

1011

EXTENDED WRITE MASKFD

IGNORED
IGNORED

1100

RESERVED

1101

RESERVED

IGNORED

1110

RESERVED

IGNORED

1111

RESERVED
MA 14871

Figure

SBI

15-6

Command Codes

TAG

IDENTI -

MASK

P <1:0>

TAG <2:0>

ID <4:0>

M <3:0>

A 9

| }

INFORMATION FIELD

FIELD l l

l FIELD l l FIELD ] L:;sa F:Eml
PAHHY

B <31:00>
o

COMMAND FORMAT

FUNCTION
FIELD

ADDRESS
FIELD
|

F <3:.0>

———

——

A <27:00>
MAR-14369

Figure 15-7

SBI Parity Field Configuration

ERROR-FREE, DATA

LOGICAL
[ 000 H{}ESTW
AT!GN”' GODOJ l

TAG <2:0>

ID <4:0>

TAG <2:0>

000
TAG <2:0>

ID <4:0>

,
DATA
CORRECTED

0010

LOGICAL

ID <4:0>

B <31.00>

M <3.0>

DESTINATION

B<31:00>

M <3:0>

GICAL
A'nca:g“ 0001 J l
DESTIN
l 000 l ILG

Ho,

]

M <3:0>

IGNORED

PROTOCOL

l FUNCTION ] ADDRESSJ

MASK

fn,

;

SBIA

SBI

UNCORRECTED DATA OR OTHER

MEANINGFUL INFORMATION
B <31:00>

M <3:.0>

MAR-14872

Figure

15-8

SBI

Read

Data

Formats

15-9

SBIA

SBI

I/O BACKPLANE

101

’I

INTERCONNECTIONS

LOGICAL
LSEURCEI
l MASK l L

WRITE DATA

1D <4.0>

8 <31:00>

TAG €2:0>

M <30>

‘]
MR.14873

Figure

15~9

SBI

Write

Data

Format

FIRST EXCHANGE:

08 07

INTERUPT SUMMARY

CDMMAND

READ

HREQUEST{*ZE RO-l
LEVEL

TAG<2:0>

1D<4:0>

M<3 G>

REQ<7:4>

SECOND EXCHANGE:

nesvonse

INTERUPT SUMMARY

B 31

[ oo | (BRI] [0] |
[

TAG<2:0>

STCAL

ID<4:0>

M<3:0>
—

17 16 15

0100

]

[

BIT PAIRS

(BIT PAIRS=B17 AND B0O1-B31 AND B15)
MR-14974

Figure

15.6

15-10

SBI

=--

SBI

Interrupt

I/0 BACKPLANE

Summary

Formats

INTERCONNECTIONS

Table 15-4 lists the cable connectors
associated
with
the
cables
from
the
ABus
backplane
to
the I/0 backplane and

expansion

the

SBIs

from

the

I/0

backplane.

See

also

SBI
for

Figure

15-11
for
locations
of the cable connectors.
Table 15-5 lists
the SBI signals along with their backplane pin for the cable from
the
ABus
backplane
to
the
1I/0O
backplane
and
from
the I/0
backplane to an SBI expansion cabinet.
Table

15-4

(SBI Expansion)

Cable

Interconnections

ABus Backplane to I/O Backplane

I/0 Backplane

ABus
SBIO

SBI1l

Backplane

SBI1

SBIO

SBI1l

ouT

SBIO

ouT

J47

J41

J19

J25

J19

348

J42

320

J26

J20

J49

J43

J21

J27

J21

Row

SBI

J50

Jé4

J22

J28

J22

J51

J45

J23

J29

J23

J52

J46

J24

J30

J24

i—aSBIB—-+

SBI1

15-10

SBIA

1lP8I6L-0L|_SBIBL-OL1

SBI -- I/0 BACKPLANE INTERCONNECTIONS

)OISANVN/IBNOI)YVE

- 1Oed

& 3 85
,

“

o]1jy

15-11

=i®t

SBIA

SBI --

I/0 BACKPLANE

INTERCONNECTIONS

Table 15-5

Signal

ABus

I1/0

I/0

Name

Out

Qut

Note

SBI Signal and Backplane Pins

Note

BOO
BO1
B02
B03

J25 B
J25 D
J25 J
J25 R

B04

J25

B0O5

J25 FF

BO6
BO7

J25 NN
J25 DD

B0OS8
BO9

J25 LL
J25 RR

B10
Bll

Note

Nexus

Note

J25 A
J25 C
J25 H
J25 D

J41
J41
J41
J41

B
D
J
R

ABl
ACl
AD1
AE1l

J25 AA

J41

AM1

J25

J41

J25
J25

MM
CC

J41
J41

NN
DD

AN1
APl
AP2

KK
PP

J25 TT
J25 Vv

J25
J25
J25
J25

SS
UU

J41 LL
J41 RR
J41l TT
J4l Vv

AS2
AT2
AUl
AU2

Bl2
B13
Bl4

J26
J26
J26

L
T
N

J26
J26
J26

K
S
M

J42
J42
J42

L
T
N

BF2
BH2
BJ1

B15

J26

J26 W

J42

BJ
2

Blé6

J26 JJ

J26 HH

J42 JJ

BS2

B17

J26

J42

B18
B19

J26 TT
J26 VvV

J26
J26

SS
UU

J42 TT
J42 vV

BT2
BU1
BU2

B20

J27

J43

CB1

B21
B22

J27
J27

J
N

J27
J27

H
M

J43
J43

J
N

CCl
BU1

B23

J27

J43

CD2

B24

J27
J27
J27
J27

J27 AA
J27 EE
J27 KK
J27 CC

J43

CM1

J43
J43
J43

FF
LL
DD

CN1
CPl
CP2

B25
B26
B27

FF
LL
DD

B28

J27

J43

cs2

B29

J27

J43

CT2

B30
B31

J27 RR
J27 Vv

J27
J27

PP
UU

J43
J43

RR
v

Cul
Ccu2

FAIL
DEAD

J27
J28

TT
D

J27
J28

SS
C

J43
J44

TT
D

cva
DAl

IDO
ID1
ID2
ID3
ID4

J28
J28
J28
J28
J28

DD
LL
RR
TT

CC
KK
PP
8§
UU

J44
J44
J44
Jd4
J44

DD
LL
RR
TT
VvV

DP2
DS2
DT2
DU1

J28
J28
J28
J28
J28

MO
M1

J28
J28

B
F

J28
J28

A
E

J44
J44

B
F

DB1
DC1

J28

J44

J28

J44

L
J

DD1

J28

L
J

J28

15-12

DU2

DD2

SBIA

SBI

Table 15-5

~--

I/0

BACKPLANE

INTERCONNECTIONS

SBI Signal and Backplane Pins

(Cont)

PO
Pl
SPARE O
SPARE 1

J28 N
J28 T
J28 R
J28 2

J28 M
J28 S
J28 P
J28 Y

J44 N
J44 T
J44 R
J44 Z

DV2
DH2

TAGO
TAG1
TAG2
ALERT

J28
J28
J28
J29

AA
EE
MM
KK

J44 B
J44 FF
J44 NN
J45 LL

DM1
DN1
DP1
EP2

CNFO
CNF1
FAULT

J29 RR
J29 VvV
J29 TT

J29 PP
J29 UU
J29 SS

J45 RR
J45 VvV
J45 TT

ES2
ET2
EU1

PCLK H
PCLK L
PDCLK H
PDCLK L

J29 R
J29 2
J29 X
J29 BB

J29 P
J29 Y
J29 W
J29 AA

J45 R
J45 2
J45 X
J45 BB

EH2
EJ1
EJ2
EK2

REQ
REQ
REQ
REQ

J29 B
J29 F
J29 N
J29 D

J29 A
J29 E
J29 M
J29 C

J45 B
J45 F
J45 N
J45 D

EB1
EC1
ED1
ED2

TP H
TP L
UNJAM

J29 T
J29 J
J29 NN

J29 S
J29 H
J29 MM

J45 T
J4as J
J45 NN

EF1l
EF2
EP1

INTLK
TROO
TRO1
TRO2

J30
J30
J30
J30

B
D
F
J

J30
J30
J30
J30

A
C
E
H

J46
J46
J4é
J4e

B
D
F
J

FAl
FB1
FC1l
FD1

TRO3
TRO4
TROS5
TRO6

J30
J30
J30
J30

L
N

T
V

J30 K
J30 M

J30 S
J30 U

J46
J46
J4e
Jde

L
N

T
V

FE1
‘FF2

TRO7
TROS8
TROO
TR10

J30
J30
J30
J30

X
2
DD
FF

J30
J30
J30
J30

W
Y
CC
EE

J46
J4e
J46
J46

X
2
DD
FF

FJ2
FM1
FN1
FP1

TR11
TR12
TR13
TR14
TR15

J30 JJ
J30 RR
J30 LL
J30 TT
J30 vv

J30 HH
J30 MM
J30 KK
J30 Sss
J30 UU

J4e
J46
Jd6
J4e
J4e6

JJ
NN
LL
TT
VvV

FP2
FS82
FT2
FU1
FU2

MP1
MP2

J29
J29

4
5
6
7

BB
FF
NN
LL

FF
DD

J29
J29

EE
CC

J45
J45

FF
DD

EM1
EN1

FH2
BFJ1

NOTES

Signal names are prefixed by

J numbers shown are for SBI 0.
subtract

"BUS SBI".

J numbers shown are for SBI 0.
add

15-13

For

SBI

For

SBI

SBIA

SBl

I/O BACKPLANE
4.

Standard signal pins for slot
including I/0 backplane slots

All

signals

All
TP,

signals are TTL except
which are ECL.,

Nexus power and ground pins are:
+5

Gnd

15.7

SBI

Table

15-6

FAULT

the

Parity Error -- An
not

nexus

agree

when

with

are

asserted

and

C2,

H1l,

N2,

faults

15-6

SBI

not

Read

receive

and

received

parity.

and

Data

command

When

for

nexus

Sequence

generated

over

the

receives

extended

Interlock

Fault

definitions.

Definitions

received

one
data

or
does

nexus,
which
received
a
write
or interlock write masked command
receive the
write
data
in
the

read masked on the previous
When

nexus

Multiple Transmitter Fault -- When a
an ID different from the transmitted

read

read,

data,

read

receives

has

not

transmitting
ID.

CONFIRMATION AND FAULT DECISION

but

did

masked,

cycle.

write
masked
command
and
interlock
interlock read masked command.

SBI

true.

PDCLK,

error

calculated

interlock

15.8

PCLK,

their

Fault

parity

cycle.

Unexpected

low when

and

information path

the

SBI

Write Sequence Fault -- When a
masked,
extended write masked,
on the previous cycle, does not
current

1 of any nexus,
6, 11, and 16.

DEFINITIONS

lists

Table

INTERCONNECTIONS

been

nexus

interlock

set

by an

receives

FLOW

Figure 15-12 is a flow chart that indicates how SBI
nexus
check
for
SBI
faults
and
the
decisions
involved
with sending SBI
confirmation, SBI CNF<01:00>.

15-14

SBIA

CONFIRMATION

AND FAULT DECISION FLOW

BELUYS

QHOM Ol

aw>zH./uNm§m

SBI

)
¢

AHVININNS

FAILOY

Yivad

Lved

Alidvd

Invd

NIAD

3NIAD

ovi

15-15

Ovad Yiva

ALlHYd
1nvd

HILLIWX
Lnvd

FdUIN

LdNHILMI

ALIHYd
L4

Nvd

ttt S

CHAPTER

SBI

16.1
This

SBI

NEXUS ADDRESS

chapter contains information on SBI
nexus
DR780, DW780, and RH780.
There will be a

C1780,

the module utilization,

each

INFORMATION

16.1.1

block diagrams,

the

devices.

SBI

Nexus Addressing

addressing,

the

section covering

and jumper selection

for

Table

16-1 contains a list of
SBI
nexus
base
addresses
as
function
of the TR number.
The address is listed for each SBIA.
If the address for Unibus address space is
desired,
see
Figure

Table

16-1

SBI

Nexus Base Address

SBIA O

SBIA 1

Byte

Longword

Byte

Longword

TR#

Address

1
2
3
4
5
6

20002000
20004000
20006000
20008000
2000A000
2000C000

8000800
8001000
8001800
8002000

DW4
DW5

8002800
8003000

DW6
DW7

2000E000

8003800

DWO
DW1

DW2
DW3

g*
g*
10*
11*

RHO
RH1
RH2
RH3

20010000
20012000
20014000
20016000

12
13
14
15

20018000
2001A000
2001C000
2001E000

*RH780
16.1.2

8004000
8004800
8005000
8005800

8800800
8801000

22006000
22008000

8801800
8802000

2200A000
2200C000

8802800
8803000
8803800

2200E000

22010000
22012000
22014000
22016000

8804000
8804800
8805000
8805800

22018000
2201A000
2201c000
2201E000

8806000
8806800
8807000
8807800

SBI Nexus Address Generation

Figure

16~1

address
and

the

Fill in bits <26:25> of Figure

number.

Fill

Ecalculated using

RH4
RH5
RHG6
RH7

8006000
8006800
8007000
8007800

. An SBI nexus physical byte

22002000
22004000

in bits

(the

CPU

address)

may

the

adapter

following steps.

16-1

with

1I/0

<16:13>

of Figure 16-1 with the TR number of the

nexus.

l6~-1

SBI

Nexus Address Generation

Add

030

offset

(see
the
register
description
1in
the register offset) to the bit combination
first two steps.
\

20
for
from the
26

l o & l 3 l a O NUMBER
i

Figure

16-2

Nexus

SBI

]

Address

Description

<26:25>

1I/0 Adapter

068

Number

3
<16:13>

TR Number

<12:02>

The

address

level

The

)

O 0

Generation

I/0

Nexus Address Generation Bit

Bit
Number

SBI

NUMBER

16-1

Table

MBZ

i0A

onow

the
Chapter
derived

SBIAO
SBIAl

currently unused
currently unused

the

space.

Descriptions

These

addressed

offset

bits

NEXUS

within

refer to the

the

nexus

registers

position in SBI address
space.
Wwhen
calculating
the
physical
byte address, do not place the register uvffset
into these bits, they are to be added.
Example

16-1

Nexus

Address

Generate

the

physical

byte

Calculation

address
of
the
USAR
(UBA
Status
Register,
which
has
a
register offset of 8) for DWO (TR 3) on
SBIA 0.
Filling in bits <26:25> with 00 (I/0 adapter number) and
<16:13>
with
0011
(TR3)
provides
a base address of 20006000.
Adding the register offset of 8 to the base address
gives
us
a
physical byte address of 20006008.

16.1.3
119

SBI
08

Nexus
06

0 | numser | 1 l LEVEL
10A

Bit
Number

<10:09>

<07:06>

BR/REG

Figure

Interrupt Vector Generation
03

NUMBER

R’

16-2

SBI

Table

16-3

l 5 0i
i

Interrupt Vector Generation
SBI Vector Generation Bit Description

_
- Description

1I/0 Adapter Number

0
1
2
3

SBIAO

=
=

SBIAl
currently

unused

currently

unused

BR/REQ LEVEL - The interrupt
00 = BR 4
01 = BR 5
10 = BR 6
11 = BR 7
16-2

request

level

or BR level.

SBI

.SBI
Table

16-3

SBI

Vector

Nexus

Interrupt Vector Generation

Generation

Bit

Description

(Cont)

Bit

Number

Description

<05:02>

TR Number

Example

16-2

The

Interrupt Vector

interrupt from a BR4

generate

16.2

TR number

interrupt

Unibus

vector

the

gencration

device

NEXUS

DWO

(TR

10C.

CI780

23 222120191817
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1/0 BACKPANEL BP4
ME-15862

Figure 16-3

CI1780 I/0 Backplane Module Utilization
16-3

will

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SBI

C1780

16.2.1

CI1780

Table

16-4

names,

and

Backplane Jumper

contains
a

Table

16-4

Jumper Settings

Settings

list

description

Backplane

the

CI780

jumpers

with

jumper

jumpers.

C1780

Backplane Jumpers

CI780 Jumpers
J17
or

Signal

J31

Name

LT Jumper

TR Jumper

W3
w4

TR Jumper C
TR Jumper A
PRI Jumper 0
PRI Jumper 1
TR Jumper B

Description
In

Out

W5
Wé
w7
w8

Panic

Mode Jumper

Boot Jumper
Boot Jumper
Reserved

3
4

H
H

0
2

H
H

Wl4

Boot Jumper
Boot Jumper
Disable Arb

W15

Extend

W10
wll
W12

W13

W16

Alter

:
HDR/TRLR

Delay

Extend

SBI

cycles

before

CXTMO

512

SBI

cycles

before

CXTMO

In = Panic mode disabled
Out = Panic mode enabled

Time

Out

ACK

Timeout

arbitration on CI before
transmission
= Normal CI arbitration

Extends

header/trailer

Out = Normal

header/trailer

Out
W17

2048

Long

=
=

Out
NOTE

delta

Short
Long

time

delta

time

timeout

Short

timeout

For the SBI expansion cabinet, use J17,
and
the VAX 8600/8650 I/0 backplane, use J31.

Interrupt/Priority
Level

W5
0

BR
Level

0
1

1
0
1

5
6
7
out
in

1
0

Jumper

for

SBI

CI780 Backplane Jumper Settings
Table

16-4

C1780

Backplane Jumpers

Boot Timer

Wl3

w10

wl2

Time
(Seconds)

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0000
0100
0200
0300
0400
0500
0600
0700
0800
0900
1000
1100
1200
1300
1400
1500

= Jumper out

Jumper

TR Level

0
0
0
0
0
0
0
0
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1

)
0
1
1
0
0
1
1
0
0
1
1
0

0
1
0
1
0
1
0
1
0
1
0
1
0

1
1
1

0
1
1

1
0
1

1 = Jumper in

Level

1
2
3
4

5
6
7
8
9
10
11
12
13
14
15
16

Jumper out

16-8

(Cont.)

CI780

Table

SBI

16-4

C1780

Backplane

Backplane Jumpers

Jumper

{(Cont.)

TR Arbitration

Wirewrap from
CXX-53 (BUS TR L)
For

TR1

CXX-57
CXX-63

TR2
TR3

CXX-62

TR4

CXX~-65

TR5

CXX-69

- TR6

CXX-71
CXX-73
CXX-75

TR7
TRS8
TR9
TR10
TR11
TR12
TR13
TR14
TR15

CXX-77

CXX-81
CXX-83
CXX-85
CXX-86
CXX-87
CXX-88

For SBI expansion cab,
For I1/0 backplane, X =

X =
C24

C01

NOTES

The standard configuration
other jumpers out.

TR4

with

all

Other wirewrap needed:
a.

Expansion cab:

Jumper B05-05

to B05-06

1I/0 backplane:

Jumper B24-05

to B24-06

The jumper selection for TR level must
the wirewrap for TR arbitration.
TRO

reserved

for holding

16-9

the SBI.

match

SBI
Settings

SBI

DR780
16.3

DR780

B
o

o«

W
w

cla
%{3

o«

SQ
© iy

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lofole

g:um

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SEHHEEHNE
@ic@egfl?a
2jlm|z2|2|2|=2

NOTES:
1.

VIEW FROM MODULE SIDE.

2. SBI EXPANSION CAB USE.
3.

M8046 PADDLE CARD MOUNTS ON PIN
SIDE OF BACKPLANE.
MR-16153

Figure

16-6

DR780

16-10

Module

Utilization

SBI

DR780

DR780 SBI CONTROL (DSC)

18296

PARITY CHK GEN:

—

| MASK CHK,
GEN;

S8l

eol XCVR

XMIT

FUNCTION

DECODE;

8646

DSCB

ID COMP,

REC

_=+_1

DSCC. H.

H.L,

ADRS

CMND

bC102

745194

MISC

DCR WRITE

DECODE

DCR

745138

"1 DSCH

745112

DSC.

DATA
RATE
REG

DAR
DI
¢
COUNT f—(

DSCS

745194
DSCS

|93s16

XCVR XMIT

8645

DSCA

OUTMUX

225163

REC

16
A
TR JMPR—e<—|

DSCL
741.5259

32
i

OUT OF

DSCC

%
132

SEQ
S

— oseanw |748373
y
DSCE

—4 OSEQT LW |

igfi?\S/ER

OSEQ

SBUS REC

DRIVER

DSCT

SBUS

745241
0SCD

745241
DSCE

745573
4

132
-

S BUS
MR 16787

)

Figure 16-7

DR780 Block Diagram (Sheet 1 of 4)

16-11

SBI

DR780

DR780 CONTROL (DCB) M8297

132
) -

132

[SBI ADRS

BYTE COUNT

LOOK AHEAD

REG

CONTROL

7418377

7415377

DCBC

DCBA

RAM
-

85568

DCBB

SBI ADRS

SBI BYTE

DDI BYTE

COUNTER

7418377

136

7415169 |
DCBC

DCBD

32},

(27

32,

DCBE

;jé‘fgfg
X3,

7415283 (

745157

S BUS MUX
)

745153

DCBF, H

S BUS

S BUS DRIVERS

REC.

MASK DRIVER

745241

DCBF, H

$ 745373

DCBA

(a)

32
S BUS

(o)
MR-16788

Figure

16-7

DR780

Block

16-12

Diagram

(Sheet

2 of

SBI

DR780
DR780 MICROPROCESSOR (DUP) M8298

{

CONTROL INTERCONNECT

CONTROL

FLAGO,1

745231
DUP

INTERCONNECT
CTRL/DATA

STATE REG
DUPU

745153
Ts

B-2301A

LITERAL <15:00>

BUS D<29:02> +2

8.93422

71 LS<31:00>

3‘%’3

D BUS

STORE

LS ADR

CNT/REG
DuUPU

1t
UWORD REG
WCS PARITY

WRT

[PUPM

|DUPL

BUS WCS D<30:00> | 1K X 40

LATCH

DUPE

|je——}

uSEQ

DUPN

bDuPC

745373

l——i‘—SBi FUNCTION
IS
S BUS RCVRS
745374

DUPA

745241
purB

S BUS

fup

;fi’fg 1

DRIVERS

ADRS

‘

DATA

132

@:)

5BUS

(f)
MA-16788

Figure

16-7

DR780 block

Diagram

16-13

(Sheet

3 of

SBI

DR780

DR780 SILO MODULE (DSM) M8299
q

)

DATA INTERCONNECT

{8
3

132

DI CONTROL

DSMP,R,S, T

2_§;3?

XMIT REG

| RCVR LATCH
|

DsmH

l_.

[12]

7415161

DSMC

—1

OAR

1s |

—l

DEMD

I OwW

DSME | DSMF

I .@

172

HIGH

BANK | BANK
85568 | 85568

|rs

745158

|REQ1

—

ssC

REQ2

STALL

— DDI REO

DSMM.N.P

SILO CTRL

DSML,M,N

BYTE ROTATORS

DSMK

/.,

4}'32
745241

DSMA

S BUS
DRIVERS

745241
DSMN
S

L—

_/ BYIE
ROTATORS

]

S BUS
MASK

25510 DSMB
‘{,32
S BUS RCVRS
745374
DSMA

DRIVER

132

S BUS

/
MR-16730

Figure

16-7

DR780

block

Diagram

16-14

(Sheet

SBI
DR780

Lol

[ ]

=z=z

Ll
el

=z=z

..99".0"!‘.“9’.3‘

®©

J14

J8
=i

)

J10
B

J11

J12

J15 J14 J13
131 (3]

iazgh!igi
3

GND

+5V
MR.I4680

Figure

16-8

DR780

Backplane

16-15

Jumper

Location

SBI

DR780

Table

16-5

DR780

Backplane Jumper Settings

and

Wirewrap

Selection
TR

SELD

SELC

SELB

SELA

FO2L2

No.

Wirewrap
To

F02C1

F02D1

-—

—~—

FO2E1l

I
-

I
—

FO2F2
FO2H2
F02J1

8
9

I
I

F02J2
FO2M1

-—

FO2N1
FO2P1

11
12

I
I

—
-

I
I

F0282

FO2P2

F02T2

FO02U1

FO02U2

NOTES

An
is

The
W3

first DR780
installed.

and

has

The

first

"I" in the
installed.

W4,

table

W3,

DR780

indicates

at TR 13,

The

W5,

W6:

For

DR780

has

jumper

from F02L2
a wirewrap

and

W7,

MSEL Jumper Select:
If the DR780 is
going
to
perform DDI arbitration, or be
then W7

installed.

is to be the master device,
installed.
W8,

master,

to
from

out.

and

at TR 14

installed.

a wirewrap

F02T2.
The second
FO2L2 to FO2Ul

and has

second DR780

and W1

has

that

Clock

Jumper

the

Interconnect
installed.

the

Interconnect

clock

Select:

clock

(DI),
If the

source

the

source

the

jumper

the

for

(DDI),

its

DR780

the

then
jumper
W8
customers device

not

Data

is
not
is to be

the

DR780

Device

then

jumper

installed.
7.

W9 - W1l2:
These jumpers are not
DR780,
but
may
contain
spare
installation in W8 or W7.

used by
jumpers

the
for

Disable Wirewrap
Selection:
If
the
DR780
interface
1is
device
A,
wirewrap
EO3Rl to
E03T2
and
EO3R2
to
EO3F2.
Otherwise,
wirewrap
EO3R1
to EO3F2 and EO3R2 to EO0O3T2.
When connecting two DR780
interfaces
(DR780
to DR780), only one can be device A.
16-16

SBI
DW780

DW780

24 23 222120191817
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NOTES:.
1.
DWO AND DW1 HAVE EXTERNAL UNIBUS.

2.
3.

——r—
UNIBUS

SLOTS

DW2 HAS INTERNAL UNIBUS, LE., DOES
NOT LEAVE CABINET.
UNIBUS OUT CABLES AND M2044 MODULES

MOUNT ON PIN SIDE OF BACKPLANE.

Figure

16-9

DW780

I/0 Backplane Module

16-17

MA-15864

Utilization

SBI
DW780

A
k.

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3|2

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wlwiolw

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NOTES:
1. VIEW FROM MODULE SIDE

2. SBI EXPANSION CAB USE
3. M3042 AND M9044 MODULES MOUNT

ON PIN SIDE OF BACKPLANE.
MA-18151

Figure

16-10

DW780 Expander Cabinet
Module Utilization

16-18

HALNOD

5534GAY

‘

185

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16-19

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16-20

B SHES

DW780

SBI

DW780

16.4.1

Jumper

SBI
Settings

DW780 Jumper Settings

The DW780

jumpers are

installed

in the

I/0

backplane,

J35,

J39, and J40 for DWO, DW1l, and DW2 respectively.
If the DW780 is
installed in the SBI expansion cabinet, the jumpers are installed
in J24 of the UBA backplane.

The DW780 jumpers in the I/0 backplane are not the
same
as
the
DW780
jumpers
in
an
SBI
expansion
cabinet.
Although Unibus
adapter (UBA) interrupt level
selection
1is
the
same,
UBA
TR
arbitration
selection
differs
by slot numbers, and the jumpers
for UBA Unibus address space selection are reversed.
Table
16-6
lists the DW780 Unibus adapter jumpers.
Table

16-6

DW780 Jumper Settings

UBA TR Arbitration Level Selection

UsIC

USIC

TR
SEL

From
DX%R$

No.

—

7
8
9
10
11
12
13
14
15

-I
-I
I
I
-

I
I
-I
I
-I

I
I
-I
I
I

-I
I
I
I
I
I
I

-t

Wirewrap
>

NOTES

The
"I®"
indicates
that
installed to provide a low

the
(true)

jumper
signal.

The XX indicates the slot number as follows.
1I/0 backplane DWO
- I(G.backplanewfiiggfigfi

1I/0 backplane DWl1 - I/0 backplane slot 11

I/0 backplane DW2 -

SBI expansion
Slot 01

I/0 backplane slot 6

cabinet

UBA

The first
UBA
(DW0O)
is
jumpered
Subsequent UBAs are jumpered as TR4,
TR6.

16-21

backplane

as
TR3.
TR5, and

SBI
DW780

Jumper

Settings
Table

16-6

DW780

Jumper

UBA Unibus Address

SBI

Expansion

Settings

Space

Cabinet

(Cont)

Selection

I/0 Backplane

USID

Adapter

Adapter
1L

Number

Adapter
0L
W2

0
1
2
3

—
-

I
I

e
I

Adapter
Number

0
1
2
3

USID

Adapter
1L
W2

Adapter
0L
W1

——
I
I

I
I

WARNING

The use of Wl and W2 in the expansion cabinet has
the opposite use as in the I/0 cabinet.

NOTE

The "I"TM
provide

UBA

Interrupt

indicates that the jumper
a low (true) signal.

Level

UAIF
PRI

installed

the

jumper

(true)

signal.

Selection

SBI

UAIF

JMP

PRI

Request

Level

1L
w8

SBI
JMP

NOTES

The

"I"

installed
2.

The

UBAs

indicates

that

to provide a
are

installed

low
as

16-22

BR4

devices.

SRBRIT

UDA

16.4.2

Module

Utilization

UDA 50 Module Utilization

PB4 12 17 1Y 10 9

&8 &4 3

74 I3

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elgiz

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VIEW FROM MODULE SIDE

Figure

16-13

UDA 50 Module Utilization

16-23

UDASBO

18863

SBI

Unibus Signals
16.4.3

Unibus

Signals

<::_

A0O-17 (ADDRESS)

i:)

DO0-15 (DATA)

C0-C1 (CONTROL)

MSYN (MASTER SYNC)
SSYN (SLAVE SYNC)
-PA-PB (PARITY)
DEVICE

BR4-7 (BUS REQUEST)

___UBA

usT

BG4-7 (BUS GRANT)

NPR (NONPROCESSOR REQUEST)

NPG (NONPROCESSOR GRANT)

SACK (SELECTION ACKNOWLEDGE)
—

—

INTR (INTERRUPT)

BBSY (BUS BUSY)
INIT (INITIALIZE)
AC LO (AC LINE LOW)
DC LO (DC LINE LOW)

MR-15891

Figure

16-14

Table

Unibus

16-7

Signal

Data

Unibus Signal Descriptions
Description

Transfer Group

Address

Lines

These

lines are used by the master
device
to select the slave (a
unique
memory
or
device
register
address).
SA<17:01>
specifies a unique
16-bit
word.
SA<00>
specifies a byte within the word.

SA<17:00>

Data

Signals

Lines

Control

[D<15:00>]

[Cl,

CO]

These

lines
transfer
16
information between master and

Dbits
slave.

These signals

the

device

are

coded

master

to control the slave in one of four
possible
data
transfer
operations
as
specified
below.
The transfer direction
is always designated with respect
to
the
master device.

16-24

SBI

Unibus

Table 16-7

Unibus Signal Descriptions

Signals

(Cont.)

Description

Signal

Data In (DATI):
A
data
byte
is
transferred
master from the slave.

Data In Pause (DATIP):
Similar to
DATI
except
that
it
1is
always
followed by a DATO(B) to the
same

word
into
‘

or
the

location.

Data Out

(DATO):

transferred
the slave,

A data

out

the

word

1is

master

Data Out Byte (DATOB):
Identical
to
the
DATO
except
a
byte
|is
transferred
instead
of .a
full
word.

Parity

[PA, PB]

These

signals

information.
not asserted.

transfer

PA
PB,

Unibus

parity

1is currently unused and
when true
indicates
a

device parity error.

Master
Synchronization
(MSYN)

Slave

Synchronization
(SSYN)

MSYN is asserted by the master to indicate
to
the
slave
that
wvalid
address
and
control information (and data for
a
DATO

or DATOB)
SSYN

is present on the bus.

is asserted by the

slave.

On a

DATO

it indicates
that the slave
has
1latched
the write data.
On a DATI(P) it indicates
that
the
slave has asserted read data on
the Unibus.

Interrupt

(INTR)

This signal

is asserted by an interrupting

device
after
1t
becomes
bus
master to
inform the UBA that an interrupt is to
be
performed,
and
that the interrupt vector

is
present
on
the
D
lines.
INTR
is
negated
upon
receipt of the assertion of
SSYN
by
the
UBA
at
the
end
of
the
transaction.
INTR may be asserted only by
a
device
that
obtained
bus
mastership
under the authority of a BG signal.

Priority Arbitration Group

Bus Request

(BR7-BR4)

These

devices

Bus Grant (BG7-BG4)

signals
to

are

request

used

control

peripheral

the

bus

for

interrupt operation.

These

signals

response

form
bus

the

CPU

request.

and

UBA

Only one of

the four will be asserted at any one time.

16-25

SBI

Unibus

Signals
Table

16-7

Signal

Unibus Signal

Descriptions

(Cont.)

Description

Ncfiprecesssr

Request

(NPR)

This

transfer

Nonprocessor

Grant

This

bus

request
from a device for a
requiring
CPU
intervention

not

the grant

response

an NPR.

(NPG)
Selection

Acknowledge

(SACK)

SACK
1is
asserted
device after having
control
passes
to
current

bus

by
a
bus-requesting
received a grant.
Bus
this
device when the

master

completes

its

operation.,

Bus

Busy

(BBSY)

BBSY
bus

indicates that
1in
use,

are

Unibus

the data

lines

the

asserted by

the

master.

Initialization Group

Initialize

(INIT)

Asserted

when

the

terminator

asserted

asserted
tor
following the negation

stays

Line

Low

(AC

LO)

This
of

is
an

Line

Low

(DC

LO)

anticipatory

impending

initiates
may
also

terminate

loss.

This

signal

all

voltages

If
DC

le-26

that

warns

failure.

available

supply

limits.

milliseconds
LO.

signal

power

operations

power

occurs,

(UBT)

Unibus.

AC LO
power fail trap sequence and
issued in peripheral devices

the
be

power

board

the

and

an
1is

from each

remains

are

preparation

within

clear

the

out-of-voltage
asserted.

for

system
long

specified

condition

SBI

Unibus

Table

16-8

Standard
Signal

AAl

INIT

AA2
AB1

+5 V
INTR

Unibus

Pin Assignments -

Modified
Signal

INIT

+5 V
INTR

Standard and Modified

Standard
Signal

Modified
Signal

BAl

BG6

SPARE

BA2
BB1

+5 V
BGS H

+5 V
SPARE

AD1
AD?2

L
GROUND
DOO L
GROUND
D02 L
DO1 L

TEST
DOO L
GROUND
D02 L
DO1 L

BB2
BC1
BC2
BD1
BD2

GROUND
BR5 L
GROUND
GROUND
BR4 L

TEST POINT
BR5 L
GROUND
BAT BACKUP +5
BR4 L

AE1
AE2

D04
DO3

L
L

D04
DO3

L
L

BE1
BE2

GROUND
BG4 H

INT SSYN*
PAR:DFT*

AF1

D06

BF1

AF2

D05

DO5

BF2

AH1
AH2
AJl
AJ2
AK1

D08
D07
D10
D09
D12

L
L
L
L
L

D08
DO7
D10
D09
D12

L
L
L
L
L

BH1
BH2
BJ1
BJ2
BK1

A0l
A00
AO03
AQ02
AQ05

L
L
L
L
L

AO1
A00
A03
A02
AO5

L
L
L
L
L

ALl
AL2
AM1

D14 L
D13 L
PA L

BL1
BL2
BM1

AQ7
A06
A09

L
L
L

AQ7
A06
aA09

L
L
L

BBSY L
GROUND

BBSY L
BAT BACKUP

BN2
BP1
BP2
BRIl

AlQ0
Al3
AlZ2
Al5

L
L

Al0
Al3
Al2
AlS5

L
L

SACK L

BR2

Ald L

Ald4

AB2
AC1
AC2

AK?2

aAM2
AN1
ANZ2
AP1
AP2
AR1

AR2
AS1

D11

D15 L
GROUND
PB L
GROUND

GROUND

AS2

NPR

ATI1
AT2
AUl
AU2
avl
AV 2

GROUND
BR7 L
NPG H
BR6 L
BG7 H
GROUND

D11

L
POINT

Signals

BK2

D15 L
P1*
PB L
PO*

BAT

BACKUP

NPR

GROUND
BR7 L
+20 V
BR6 L
+20 V
+20 V

BM2
BN1

+15

BSl

aA04 L

A08
All

L
L
L
L

Al7

BS2

Alé

BT1
BT2
BU1
BUZ
BV1
BV 2

GROUND
Cl L
SSYN L
CO0 L
MSYN L
GROUND

*pins used by parity control module.

16-27

A04

A08
All

L
L
L
L

Al7

Al6é

GROUND
Cl L
SSYN L
CO L
MSYN L
-5 vV

SBI
Unibus

Address

to VAX

Physical

Address

16.4.4

Unibus

Address

to VAX

Physical

example

will

used

address

(Octal)

760270

Example

16-3

show

Conversion

how

the

Conversion

Address

VAX

Conversion

convert

physical

from Unibus

from

Unibus

address

(Hex).

address

First

111
2.

change

110

000

Prepare

010

1110

Add

the

HEX

the

0000

111

the

octal

1011

example

HEX

number

binary

physical

digits.

000
binary
binary

number

into

Hexadecimal

4-digit

segments.

1000

appropriate

number

the

octal

convert

re-ordering

the

VAX

byte

DW780

the

Unibus

preceding

will

use DWO,
representation

Adapter
step

20100000.
of

Address,

the

Base

(Figure

The
VAX

Address
15-3).

resultant
Physical

the

For

this

number

is
Unibus

Byte

20100000

Unibus

HEX

Adapter Base Address (Adapter
representation of Unibus address

HEX

representation

3EOBS8

2013E0B8

converted

VAX

the

Unibus

Physical

Byte

address

address
Unibus

NOTE

For

word

access,

always

boundary.

16.4.5

VAX

Physical

Address

(Hex)

Conversion
An

example

will

address

space

2013E008

will

To make

to
be

this

assigned
to
Figure
15-3

Change

the

Unibus

word

Address

(Octal)

used.

conversion,

the

physical

byte
address
must
be
for the DW780 adapter.
Use
the
address
with
the
range
of
Determine which UBA corresponds to

the

space

the HEX digits to the binary
least significant bits (bits
2

0010

0000

0001

o ————

used to show the conversion from VAX
physical
Unibus address space.
The physical address of

Unibus
to
compare
addresses
for
each UBA.
this address.
2.

examine

equivalent

and

17-0).

0011

1110

0000

1000

17
11

0
1110

16-28

0000

1000

extract

VAX
3.

Physical

Reformat

the

DW780

Table 16-9
devices,

Unibus

Table

(Hex)

binary

the Unibus byte
111

16.4.6

SB1

Address

to Unibus

bits

into

Address

3-bit

address

in octal.

110

000

Device

1list

16-9

000

001

000

(Octal)

sections.

Conversion

The

result

for

Unibus

760010

Addresses

VAX

physical

DW780 Unibus

addresses

Device Addresses

Unibus
Device

Equivalent

Address

760010

2013E008

2013E010
2013E018

26172508

2017E010
2017E018

201BE0OS

760040

2013E020

2017E020

201BE020

201FE020

760050

2013D028

2017E028

201BEOQO28

201FE028

760060

2013E030

2017E030

201BE030

201FEQ030

760070
760100

2013E038
2013E040

2017E038
2017E040

201BE038
201BE040

201FE038
201FE040

760110
760120

2013E048
2013E050

2017E048
2017E050

201BE048
201BEO050

201FE048
201FEOS50

2017E058
2017E060
2017E068
2017E070
2017E078

201BE0SS8
201BE060
201BE068
201BE070
201BE0O78

201FEOQO58
201FE060
201FEQO68
201FEQ70
201FEO078

760020
760030

760130

2013E058

760140
760150

2013E060
2013E068

760160
760170

2013E070
2013E078

DW780

Adapter

"BYTE"

201BEO10
201BEO18

Address

(SBIA

201FE008

201FEO10
201FEO18

760200

2013E080

2017E080

201BE080O

201FE080

760210
760220
760230
760240

2013E088
2013E090
2013E098
2013E0A0

2017E088
2017E090
2017E098
2017E0Q0AQ

201BEO8S8
201BE090
201BE098
201BEOAO

201FE088
201FE0Q90
201FE098
201FEOAQ

760250
760260
760270
760300
760310

2013E0A8
2013E0BO
2013E0BS8
2013E0CO
2013E0C8

2017E0AS8
2017E0BO
2017E0BS
2017E0CO
2017E0CS8

201BEOAS
201BEOBO
201BEOB8
201BEOCO
201BEOCS

201FEOAS8
201FEOBO
201FEOBS
201FEOCO
201FEOCS8

2017E0DO
2017E0D8

201BEODO
201BEODS8

201FEODO
201FEOD8

760320

2013E0DO

760330
760340

2013E0DS8
2013E0QEQ

760350
760360

2013E0OES8
2013EOFO0

2017EQEQ
2017EQES
2017EOFO

201BEQOEQ
201BEOES

201FEQEQ
201FEOES8

760370

2013EOF8

2017EOF8

201BEOF8

201FEOF8

760400

2013E100

2017E100

201BE100

201FE100

760410

2013E108

2017E108

201BE108

201FElO08

760420
760430

2013E110
2013E118

2017E110
2017E118

201BE110
201BE118

201FE110
201FE118

16-29

201BEOFO

201FEOQOFO

SBI

DW780

Unibus

Table

Device

Addresses

16-9

DW780 Unibus

Device Address

(Cont.)

Unibus
Device

Equivalent

Address

$#0

760440

2013E120

2017E120

201BE120

201FE120

760450

2013E128

2107E128

201BE128

201FE128

764004
764014

2013E804
2013E80C

2017E804
2017E80C

201BE804
201BE8SOQC

201FE804
201FE80C

DW780

Adapter

"BYTE"

Address

(SBIA 0)

764024

2013E814

2017E814

201BE814

201FE814

770460

2013r130

2017F130

201BF130

201FF130

772410

2013F508

2017F508

201BF508

201FF508

774400

2013F900

2017F900

201BF900

201FF900

777160

2013FE70

2017FE70

201BFE70

201FFE70

777440

2013FF20

2017FF20

201BFF20

201FFF20

777514

2013FF4C

2017FF4C

201BFF4C

201FFF4C

NOTE

For
DW780
addresses
on
SBIA
1,
simply
add
02000000
to
the
address.
For example, Unibus
address 760010 on DWO, SBIA 1 will be 2213E008.

16-30

SBI

RH780

16.5

RH780

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NOTES:
1.

VIEW FROM MODULE SIDE.
THE M9041
MASSRUS PADDLE

CARD
MOUNTS ON THE PIN SIDE OF THE BACK-

PLANE. SLOT 6 IS EMPTY ON THE

MODULE

SIDE.
3. THE M8277 MDP MODULE IS STANDARD,

AND CONTA
A 32 X INS
8 BIT SILO.
4. THE M8274 MDP MODULE HAS AN EXTENDED SILO {256 X 8) AND IS USED FOR
HI-SPEED RPO7 DISKS.
MR-16152

Figure

16-15

16-31

RH780

Module

Utilization

9.28W10152_

HOLV1

1 wyiano |

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VAN

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MAP

16.5.1

MAP Register Address

The following
address,

2%
‘

steps may

Address

SBI
Calculation

Calculation
used

calculate

MAP

Determine the desired MAP Register location or offset.

must

1in

the

Registers

Enter

MAP

the

range

00-FF

(Hex)

there

are

256

MAP

MBA.

offset

Calculation
diagram
(Figure
will
be
shifted
two
bits

into

the

MAP

Address

16-18).
The register offset
1left,
creating
a
longword

boundary.
3.

Add

the

MBA

address.

MAP

base
The

address

result

(Table

the

16-10)

CPU

HEX

the

address

calculated
the

desired

MAP REGISTER ADDRESS CALCULATION
11

MAP REGISTER OFFSET
i

MR-18147

Figure

16-18

16.5.2
The

Map

MASSBUS

following

Calculation

steps may

used

calculate

MASSBUS

address.
The
example
will
be
used
to calculate the MASSBUS
register address for the control and status register (register 0)
for drive 7, SBI 1, RH780 # 0.
1.

Use

the MASSBUS Register Offset
determine the correct offset for

Add

this

offset

the

MBA base

table

the

(Table
16-11)
desired register.

address

from

Table

and

16-10.

The
result
is the CPU HEX address of the desired external
register.
Do not let the bit configuration of Figure 16-19
confuse
vyou.
Bits
01
and
00 will always be zero, bits
<06:02> indicates which register
1is
being
selected,
and
bits <09:07> indicates which drive is selected.

Example

16-4

Calculating

physical

Calculate the physical byte address
7, SBI 1, RH780 # 0 (TR8).
1.

MBA

MASSBUS

Adding
of

base

address

from Table

the

two

byte

CS1

16-10

from Table

together provides

22010380.

16-35

address

(register 0)

for drive

22010000
16-11

380

the physical

byte

address

SBI

MASSBUS

Calculation

MASSBUS REGISTER ADDRESS CALCULATION
11

DRIVE

iSELE,C?; |

]

MR-16143

Figure

16-19

MASSBUS

Table

16-10

Calculation

MBA Base Addresses

~
TR Level

SBIA

Base

Address

Base

Address

20010000

20012000

22012000

20014000

22014000

22010000

20016000

22016000
NOTE

Always

examine MASSBUS

boundary.

Table

REG NO.

16-11

registers

MASSBUS

longword

MASSBUS DEVICE TYPE

DRIVE NUMBER

DISK

TAPE

0
1
2
3
4
5
6
7

c¢s1
DS
ERI
MR
AS
DA
DT
LA

0
4
8
C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44

80
84
88
8C
90
94
98
9C
A0
A4
A8
AC
BO
B4
B8
BC
<CO
CA

180
184
188

200

280

300

380

204

284

304

384

208

288

308

10C
110
114

18C
190
194

20C
210
214

28C
290
294

10
11
12
13
1%
15
16
17
20
21

CASO0
CASOl
CAS02
CAS03
CAS04
CAS05
CAS06
CAS07
CAS08
CAS09
CAS10
CAS11
CAS12
CAS13
CAS14
CAS15
CAS16
CAS17

100
104
108

8
9
A
B
C
D
E
F
10
11

CS1
DS
ER
MR
AS
FC
DT
CX
SN
TC

17C

1FC

27C

2FC

37C

3FC

RMCS1
RMDS
RMERl
RMMR1
RMAS
RMDA
RMDT
RMLA
SN
RMSN
OFF
RMOFP
DCA
RMOC
cca
RMNR
EBER2
RMMR2
ER3
RMER2
ECCPOS RMEC1
ECCPAT RMEC2

TM78

L¥S)
o

tx)

OCT

RP
HEX

16-36

388
30C 38C
310 390
314 394
118 198 218 298 318 398
11C 19C 21C 29C 31C 39C
120 1A0 220 2a0 320 3A0
124 1A4 224 2a4 324 3A4
128 1A8 228 2A8 328 3AS8
12C 1AC 22C 2AC 32C gt
130 1BO 230 2B0 330 380
134 1B4 234 2B4 334 3B4
138 1B8 238 2BS8 338 3BS
13C 1BC 23C 2BC 33C 3BC
140 1CO 240 2CO0 340 3CO
144 1C4 244 2C4 344 3C4

CHAPTER
REVISION

17.1
The

CONTROL

VAX 8600/8650 REVISION INFORMATION
following

They
do
reference

tables

are

not
replace
the
only.
They are a

check

list

for

the

KA86

RM
document
and
history of changes

unit

revision.

are to be
that have

used for
occurred
to the KA86 from revision H4 to K3.
For prior history, see early
revisions of the
RM
document.
The
following
information
is
subject to change.

Table 17-1 shows revision information for the VAX
17-2 shows revision information for the VAX 8650.
Table 17-4 contains the diagnostic media revision
VAX 8600 and VAX 8650 respectively.
For file

revision

information,

read

the

file

8600 and
Table
Table 17-3 and
information for

RL2REV.MEM.

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REVISION CONTROL

REVISION
INFORMATION

SBINPOR

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VAX

17-3

8600/8650
REVISION CONTROL
REVISION INFORMATION

‘31SD84et0MUL

(DBU1XOIl~L0UVSa-B9W0LIeADO8B14)]UYT)

NOom

REVISION CONTROL

VAX 8600/8650 REVISION INFORMATION

|sdyaoeuyeg
17-4

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VAX

17-5

8600/8650
REVISION

REVISION

INFORMATION

CONTROL

REVISION CONTROL

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NEORISEINAEZLY.

INFORMATION
VAX 8600/8650 REVISION

{

CHAPTER
REMOVAL

18.1

AND

REPLACEMENT

PROCEDURES

GENERAL

This chapter describes how to remove and replace assemblies in
kernel
system.
Only the major field replaceable units (FRUs)
the system are covered.

the
for

This chapter covers the two major system components included
in
a
kernel
system, the front end and CPU cabinets, and is divided into
four major parts, one part
for
each
o©of
these
components,
this
introduction, and a section on module paddle connector cleaning.
The

procedures

completion

order

you

work

into problems

performing

this

work

Use

all

put

them
not

each

specific
of

each

the

Unless

otherwise

removal

Perform

the

signal

cables

pay

stated,

with

because

ones.

component,

some

sure

you

may

procedures.

and bolts when you
their correct places.

bundle

order

preceding
system

screws

the

component,

the

As you
rules.
®

listed

run

are

depend

attention

reassemble

power

replace

the

following

component

and

cables.

FRU,

test

for

reverse

the

order

procedures.

appropriate

diagnostic

replace.

18-1

each

FRU

that

vyou

REMOVAL

18.2

AND

FRU

REPLACEMENT

PROCEDURES

PART NUMBERS

Digital
A.

FRUs

FOR

POWER

CPU

SUPPLY

ASSEMBLY

AC Input Assembly

(2)
(2)

Modular Power Supply
Modular Power Supply

Modular Power
EMM

Assembly

Modules
H7231
876

Supply
(with

V/240

120

CENTRIFUGAL

in CARD CAGE

FOR

120

70-19219-00

70-20340-00

V @

200

H7170-A

H7180-A

1500

CFM

H7188-A

Aa)

H7187-A
H7186-A
PNs

V/208

876-A

12-19197-00

12-19197-01
12-23034-02

LED)

12-22805-01

Sensor

FRONT

END

12-19526-01

CABINET

ASSEMBLY

70-19218-00

70-19218-01

CVT

30-23959-00

RLO2

DISK

DRIVE

BAll-A

UNIT

Modules

H7140
FAN

SUPPLY

ASSEMBLY

Filters

(four,

and

two

BAll-AL

BAll-A

POWER

PANEL

RLO2-FK

ASSEMBLY

two

back

PNs
in

BAll-A

(50

Hz)

front

FRONT

available

H7140
70-19886~00

door

door)

12-11255-08

Filter in Back Door Assembly

18.3

available

H7231-A

SUPPORT ASSEMBLY

(with

12-11255-02

END CABINET ASSEMBLY

This

paragraph describes how to electrically disconnec
t
End
cabinet from the CPU cabinet and how to remove
and
field replaceable units in the front end cabinet.

the
Front
replace the

NOTE
Some

the

different
Hz

70-19219-~01

(+2.5 v @ 100
(+5 v @ 85 A)

SUPPLY

Flow Sensor

FRUs

(+5

POWER

Temperature

PROM)

ASSEMBLY

Filter

Kw)

CARD CAGE

POWER CONTROLLER

Air

(2.8

BLOWER,

ASSEMBLY

(2)

CABINET

system

modules

from

those

differences

in
are

the

noted.

18-2

system

system.

All

are

REMOVAL

18.3.1

AND

REPLACEMENT

PROCEDURES

Preliminary Steps

C——

This procedure describes steps that you must take before you
work
1.

the

panel

Open

front

end

the

the
switch
18-3).

Contact
breaker

Open

lower

the

Remote

CPU

cabinet,

control

and

rear

left panel at
main
circuit

front

power

Remote

switch

doors

the customer and
is switched off.

the

876-A

front

doors

the

front

the

rear of
breaker to

ensure

the

controller,

turn

CPU

switch

Restart

that

the

Restart

Enable

Active

Alert

T_Q--

RED

RESTART CONTROL

Boot

system

OFF position

end

control

(Figure

cabinet.

the customer

cabinet.
CB1l

keyed

the front
end
cabinet,
the OFF position (Figure

State

—

begin

cabinet.

the

terminal

VAX

front

f-Halt

the

OFF

power

front

position

Local

circuit

the

(Figure

Lm{

Remote

Disable
—
N\ 7 /7 Disable

Qfi.... —

GREEN

LEDs

LED

TERMINAL CONTROL

SWITCH

MR-13562

Figure

18=1

System Control

Panel

MR-18332

876 POWER
CONTROLLER

Figure

18=2

876=A Power

Controller

18-3

Front View

AND

REPLACEMENT

PROCEDURES

J2
11
TEMPERATURE/GROUND = |

A N\
P

CONNECTOR

cB2

REMOVAL

NN
AN
A\

BREAKER

[y Sl %

MAIN CIRCUIT

Q BUS

J32,J33J434

47,48
1

)%
1]

oVT

p—

——

”

UNIBUS 0

F/E CABINET (RIGHT SIDE VIEW)

—

& l\

f o

1
Ty

|50 HZ
ONLY

CPL] BEAR VIFW

UNIBUS 1

F/E REAR ViEwW

J36.,437.J38
DRANEZ CONNECTOR

Figure

18-3

Front

End

Cabinet

Cable

18-4

Connections

Mu-14858

Rear

View

REMOVAL

18.3.2

AND

REPLACEMENT

PROCEDURES

Front End Cabinet Disconnection

This procedure describes how to electrically disconnect
the
front
end cabinet from the CPU cabinet.
Before you begin this procedure,
make

sure you

complete

the

preliminary steps

that the customer has

18.3.1.

Ensure

Disconnect the front end cabinet main ac power cable
wall receptacle at the customer site.

from

the

Disconnect triple ribbon cable connectors P4, P5, and

from

cable
connectors J32, J33,
CPU cabinet (Figure 18-3).

turned off

in Paragraph

power to the system.

and J34 on the

I/0 backplane of

the

NOTE

When
reconnecting
indicates pin 1 and
4.

Disconnect double

connectors
(Figure

ribbon
the red

ribbon cable

and

<cables,
the
notch
stripe points up.

connectors

and

J8 on the CPU backplane of

from

cable

the CPU cabinet

18-3).

Disconnect the right angle end of
the
large
ac
power
cable
connector
P18
from cable connector J18 at rear of 876-A power
controller in the CPU cabinet (Figure 18-3).
NOTE

When reconnecting the power cable,
be
careful
not to pull out any cable connectors in the CPU
cabinet.

Disconnect the RL02 disk drive ac

the

rear

(Figure 18-3).

line cord

from receptacle

of the 876-A power controller in the CPU cabinet

Disconnect the BAll-A unit ac power cord from receptacle L2
at
the
rear
of 876-A power controller in the CPU cabinet (Figure
18-3).

18.3.3

Constant Voltage Transformer

(CVT)

Assembly Removal

This procedure describes how to remove the CVT
assembly
from
the
front end cabinet.
Before performing this procedure, make sure you
complete the preliminary steps in Paragraph 18.3.1.
Remove the CVT
module

follows.

(to

supplied)

18-5

REMOVAL

AND

18.3.4

RLO2

This

REPLACEMENT

Disk

PROCEDURES

Drive

Removal

procedure

describes

from

the

front

end

sure

you

complete

Disk

Disconnect
drive unit

the I/0
(Figure

Disconnect
controller

the ac
in the

Disconnect

end

Move

the

RLO2

all

remove

Drive

Removal

"CABLE
18-4).

IN"

Remove

RL02

the

ties

that

bind

the

front

end

disk

this

the

RL02

from

rear of

the

front

wunit

out

from

the

front

18-5).

drive

make

18.3.1.

‘

disk

drive

unit

the

rear

disk

the

line

876-A

cord

power

cabinet

carefully

end

until

and
cabinet

unit

procedure,

Paragraph

connector

line cord from
CPU cabinet.

cable

the

performing

steps

frame.

the

(Figure

Installation

Before

preliminary

18.3.4.1
RLO2
as follows.

front

how

cabinet.
the

and

the

slide
catches

WARNING

The

RL02

disk

equipment.
procedure is
each side.
5.

Remove

unit

the

Remove

the

drive

unit

Lift

each

two

(Figure

the

rear

The
best

slide

unit is a
heavy
piece
of
next
three
steps
of
this
handled by two people, one on

screws,

one

each

side

18-6).

two

front

(Figure

two

side

drive

slide

the

the drive.

one

each

the

side

drive

18-6).

locking

screws,

latches

drive

on the
slide
mounting
rails
on
unit (Figure 18-6).
Carefully remove

1/0 CABLE

{“CABLE IN")

fify/fxz//

TERMINATOR

NORMALLOW /

LINE VOLTAGE
RS
TERMINAL BLOCK 57
KX

COVER

CABLE "OUT”

;'"z

110/220 VOLTS

TERMINAL
BLOCK COVER

7
AC LINECORD
CIRCUIT BREAKER
ME 154HEY

Figure

18-4

RL0O2

Disk

the

Drive

= Rear View
18-6

REMOVAL

AND REPLACEMENT PROCEDURES

F.E. ACCESS COVER

COVER RELEASE
BUTTON

CARTRIDGE OR CUSTOMER
ACCESS COVER

SLIDE MOUNTING

HAND GRIP

RAIL

OPERATORS CONTROL PANEL
ME.IB168

Figure

18-5

RL02

Disk

Drive Mounted

in Slides

LOCKING TAB

RIVETS

SLIDE MOUNTING RAIL

REAR SLIDE SCREWS
ACCESS SLOT FOR

REAR SCREWS

LOCKING

LATCH GROOQVE

FRONT SLIDE SCREWS

SLIDE EXTENSION
RELEASE CATCH

SLIDE
BUMPER

Figure

18-6

MR-16154

Slide Mounting Rail and Slide

18-7

REMOVAL AND REPLACEMENT

PROCEDURES

18.3.4.2
RLO2 Disk Drive Installation - This
procedure
describes
how to install the RL0O2 disk drive unit into the front end cabinet.
Figure 18-5 shows a cabinet-mounted RL0O2 unit.
Tnstall the unit ag
follows.

Open the front and rear doors of the front end cabinet.

Remove
unit.

the

slides from the carton
containing
(Retain the hardware for reassembly.)

Install
Be

the slides

sure

the

the cabinet using

slides

are

the

the enclosed

correct

Extend

Place the
hardware.
a.

the

Figure

slides

lock

drive

unit

18-5

shows

drive

hardware.

height

installation of dress panels when
vyou
finish
unit.
Also
make
sure
that
the
slides
do
hardware used to mount the slide.
4.

disk

permit

installing
the
not bind on any

position.

the

slides

and

relationship

reinstall

between

the

mounting

drive,

slide

mounting rails, and the slides.
Notice the position of the
slide mounting rails.
These rails are riveted to the sides
of the drive.

The cabinet slides fit
under
the
edge
of
the
mounting
rails.
The
forward edge of the mounting rails are curved
to grip the curled edge of the
slides
(Figures
18-5
and
18-6).

At the rear of each slide
top rear edge of the rail

Carefully

place

front

rear

Ensure
into a

1Insert

slide
g.

and

is a locking tab
(Figure 18-6).

the drive on top
of each slide.

the

that

slides,

that the locking latch on each mounting
groove on each slide (Figure 18-6).
the

front

slide

the drive

screws

(Figure

secure

the

grips

the

hooking

the

rail

front

drops

each

18-6).

Using the slide extension release catch, adjust the
1length
of
the
slide
and insert the rear slide screws.
The rear
slide screws secure the rear of the slides to the drive.

Make sure that
there
1is
no
room to insert

the disk drive moves easily on the slides,
that
binding in the cabinet, and that there is enough

Open the drive

access

fasteners

the

holding

dress

panels.

cover

the cover.

the drive.
You can rest
the drive (Figure 18-7).

loosening

the

four

captive

the

rear

1lip

Lift the drive access cover off

the access

cover

REMOVAL

AND REPLACEMENT PROCEDURES

DRIVE LOGIC
MODULE

RED

STRIPE
RED

RED

STRIPE

RAfo’/f

MODULE

D.C.SERVO MODULE
AND TEMPLATE
MR- 15880

Figure

18-7

RLO2 Disk Drive with Exposed Drive Logic Module

18-9

REMOVAL AND REPLACEMENT PROCEDURES

Loosen the head restraining bracket screw
on
the
positioner.
Turn
the
bracket
90
degrees and retighten the screw (Figure

On the bottom of
secure

10'

Make

the

sure

the drive,

remove

spindle/blower motor.

that

the

terminal

the

block

correctly for the input power available

two shipping screws

covers

are

configured

(Figure 18-4).

POSITIONER
FRONT VIEW:

POSITIONER

RESTRAINING
BRACKET

LATCH

SOLENOID
ACCESS COVER

MA- 15987

Figure

18-8

RL0O2 with Covers Removed

18-10

that

REMOVAL

AND

REPLACEMENT

PROCEDURES

11.

If there is only one drive in the system, or
if
this
last
drive
of
the daisy chain, install a terminator
part number 70-12293) on the "CABLE OUT" receptacle at
of the drive.

12,

If this is a multidrive
system,
connect
an
I/0
cable
from
"CABLE
IN"
of
this
drive to the "CABLE OUT" of the previous
drive.
Repeat for each drive.

1is
the
(Digital
the rear

NOTE

The total length of
the last drive must

13.

Install

the proper unit

14.

Connect

the

line

from
controller
to
not exceed 30 m (100 ft).

select plug

cord

876-A power controller

cable

LOAD SWITCH ~

the

receptacle

the CPU

'‘

AND INDICATOR

UNIT SELECT PLUG

front

the

rear

cabinet.

|
[

AND READY INDICATOR

FAULT

INDICATOR

WRITE PROTECT SWITCH
AND INDICATOR

MR-15988

Figure

18-9

RL02 Disk

Drive - Front View

18-11

drive

the

REMOVAL

AND

REPLACEMENT PROCEDURES

18.3.5

BAll-A Unit Assembly Removal

and

Installation

This procedure describeées how to remove and install the BAll-A
unit
assembly
from
the
front
end
cabinet.
Before
performing this
procedure, make sure you complete the steps in Paragraph 18.3.1 and
1803§20

18.3.5.1
1.

1In

BAll-A Unit

the

from

CPU

Assembly Removal

cabinet,

receptacle

disconnect

Release all fasteners
to the frame.

the

rear

bars
that
is held by
4.

1Insert

the

small

external

inch

nuts

screwdriver

front

bezel.

sliding

the

or clamps

the

1/4

the

rear

BAll-A

the

used

BAll-A mounting

secure

two

the

Release

screwdriver

into

the

power

secure

box,

cables

(Figure

876-A power

the

plug

the

power

cable

unit.

cord

clamp

Each

clamp

18-10).

the

slot

latch

that

holds

the

remove

cord

controller.

left

the

(Figure

right

the mounting

top

box

18-11).

Pull the front of the mounting box until it is
fully
and the slide hold levers are engaged (Figure 18-12).

extended

Remove

the

cover

and
to

Remove

retain

the

the mounting

the

UNIBUS

four
box

cable

6-32
and

screws

remove

connector

that

the

from

top

the

secure

backplane,

cables
attached
to
the consocle interface module
all other cable connectors in the modules.
Route

the

cables

away

from

the

mounting

the

(M7090),

1I/0

and

box.

LRI

AL
R ]

CABLE CLAMP

t)wm

Jowaeseeccooccoos @®le
(s

FRONT VIEW

couvoocooogl

®
&

—

20 (®

SLUSeAMeRR
O D00 00

top

cover.

Figure

18-10

Cable

MR.16077

Clamps

18-12

REMOVAL

]

AND

REPLACEMENT

THIS TYPE OF BOX LATCH

= —

NS>

PROCEDURES

RELEASE

DIRECTION

—

MECHANISM IS ALSO USED
FOR THE RACK MOUNTED
VERSION.

adadey

Release

Latch

MB-16003

Figure

18-11

CABINET RAIL N

/— BA11-AA, —AB UNIT

HOLD /

SINGLE—/

SLIDE

CHANNEL

LEVER
*

SLIDE

/— BA11-AA —AB UNIT

CABINET RAIL

PAWL RETRACTOR

,
\

hjwfii*f

SLIDE HoLD/
LEVER

’

[

DOUBLE CHANNELJ

]

SLIDE

Figure

18-12

BAll-A

Installed

18-13

Slide

Mount

8002

REMOVAL AND REPLACEMENT PROCEDURES

Remove

and

and right

retain

the

three

index plates

that

secure

to the slide assembly

8-32

screws

(Figure

the

left

18-13).

WARNING

The BAll-A mounting box is
a
heavy
piece
of
equipment.
Removal
of
the
mounting
box
requires two people, one on each
side
of
the
unit.

10.

Remove the mounting box from the
until
the alignment tabs on the

slides
by
1lifting
the
box
index plates are free from the

slide mounting bracket.

8-32 SCREWS

(3 PLACES)

INDEX

PLATE

SLIDE

ALIGNMENT

TAB

MOUNTING —A—
BRACKET
|

AR 18000

Figure

18-13

Slide

Index

18-14

Plate Mounting

REMOVAL

18.3.5.2

BAll-A

describes
cabinet.

how

3 1.
2.

AND

REPLACEMENT

PROCEDURES

Unit

Assembly
Replacement -~ This
procedure
replace a BAll-A unit assembly in the front end

Open the front and rear doors of the front end cabinet.
Extend the left
position at the

and
right
slide
channel
front of the cabinet.

their

maximum

WARNING

The BAll-A mounting box is
a
heavy
piece
of
equipment.
Installation
of
the mounting box
requires two people, one on each
side
of
the
unit.

Carefully lift
set

the

index

the mounting box

side of the box
alignment
tabs
bracket.

plates

over

the

(Figures 18-12
will
engage

above

the extended

slide

mounting

and
the

18-13).
sides of

slides

brackets

and
each

The
index
plate
the slide mounting

NOTE

When the slides are
fully
extended,
you
may
have
to force the ends of the slides in toward
the
sides
of
the
mounting
box
during
installation.

Insert the three 8-32 screws through the left index
plate
tab
and into the threaded holes of the
slide
mounting bracket.
Tighten the screws (Figure 18-13).
Repeat the process for
the
right index plate.
Perform steps 1 through 7 of Paragraph 18.3.5.1,
order, to complete the replacement process.

18.3.6

H7140

in the

reverse

Power Supply Removal

This procedure describes how to remove the H7140 power
supply
from
the
BAll-A
unit
assembly
in
the
front
end
cabinet.
Before
performing this procedure, make sure you complete
the
preliminary
steps

Paragraph

the CPU cabinet,

receptacle

3.
\

the

Release

all

fasteners

cord

the

cabinet

the

rear of

the

secure

the

two 1/4

inch nuts

Remove and
cover

18.3.1

Remove

the

side

the

power

retain

bus

remove

the

rear

the

Clamps

BAll-A box,
cables

(Figure

the

mounting

I/0

18.3.2.

BAll-A

used

remove

the

cables

the

box.

and

from

screws

remove

the

cable

the power supply and route

supply.

18-15

the

power

the

cable
Each

that
top

cord

controller.

secure

18-10).

four 6-32
box,

876-A power

frame.

external

the

and

power

clamp bars
clamp

secure

that

held

the

cover.

trough

from

the

the cables over the

top

1left

top of

REMOVAL AND REPLACEMENT PROCEDURES

of the
Remove and retain the two 8-32 screws located in each
two chassis angles at the rear of the mounting box (Figure

box and tilt:
Release the pawl retractors on each side of the (Figure
18-15).
the box 90 degrees to the maintenance position
bottom
Remove and retain the four 6-32 screws that secure thecover.
cover to the mounting box (Figure 18-15). Remove the
secure

Remove and retain the four 6-32 screws that

the

bottom

Remove the cover.

1
,

(8-32)

- / 2 PLACES

O COOGOOO DD OGN

Yoo

e eeR o000 000

SCREW

the

MR-15989

Figure 18-14

Power Supply Unit, Rear Mounting Screws

18-16

cover

supply assembly (Figure

power

the

Glooee
ee |

18-15).

BeREO 000000 MBI

plate

REMOVAL AND REPLACEMENT PROCEDURES

BA11-A
MOUNTING BOX *

FRONT

CABINET

H7140 AA—-AB

POWER SUPPLY

)

SCREW (6-32)

4 PLACES

LT
o

]

(=R

‘}

BOTTOM COVER

SCREWS (6-32)
4 PLACES

200

RAIL

{sgz&)ws

P ks
(EACH SIDE)

* NOTE:

SLIDE MOUNTED VERSION OF THE
BA11-A BOX IS SHOWN. THE
PDP-11/X44 SYSTEM CABINET
VERSION IS SIMILAR.
MA-18004

Figure 18-15

Power Supply Unit Removal

18-17

REMOVAL

10.

AND

Remove

to
11.

REPLACEMENT

PROCEDURES

and

the

retain

the ground bus

Loosen
cable

the
to

screw

18-16).

3/8

inch

nuts

ground

bus

bar.

two

the

10-32

(Figure

that

the

Loosen the two 3/8 inch nuts on the
Flexprint cable to the +5 V bus bar.

13.

Slide

the

14.

Remove

the

connector

15.

power
Jll

bend

clamp

V cables

away
backplane.

Flexprint

and

the

clamp holding

12.

the ground and
cables up toward

secures

from

ground

the Flexprint

holding

the

connector

from

connector

toward

the

clamps

the
the

lead

and

power

V.-

bend

supply

backplane.

1If one or more additional backplanes are mounted
in
the
box,
disconnect
the
connectors
attached
to J2, J3, and J4 of the
power distribution board.
Disconnect the backplane
connectors
from

P2,

P3,

and

the

power

distribution harness.

BEZEL PC BOARD

<=/

FAN ASSY

‘ /PC}WER FLEXPRINT CABLE

POWER

. /'GRGUND FLEXPRINT CABLE

CABLE

(J2ANDJ3

NOT SHOWN)

/fi-—flPSV FLEXPRINT CABLE

‘\\

\\
et

——5

—

]

[

74
J4
J3

~— SCREW

[

§odl

LEAD

[

548

————GROUND

{10-32)

L
GND
BUS

CABLE -

NUT

9.5 MM (3/8 IN)
2 PLACES

CONNECTOR

AVARR
HA-180084

Figure

18-16

Mounting Box,

Power Cable Connection

18-18

REMOVAL

16.

Remove

and

retain

screws

located

each

PROCEDURES

side

the

Slide the power supply
assembly
forward
about
5.0
cm
inches)
and
disconnect
the
fan
assembly
power
cable

(2.0
from

connectors

18.

6-32

REPLACEMENT

mounting box,
17,

the

AND

Slide
from

toward the

and

rear

the

(Figure

power

18-15).

supply

board.

the power supply assembly from the mounting box and

the

cabinet.

away

NOTE

When replacing the power supply, make sure
you
set
the
mounting
box
in
the
maintenance
position.
Then perform the reverse of steps 18
through 1 above.

18.3.7

Fan Panel

Assembly Removal

(50

system)

This procedure describes how to remove the fan panel assembly

from

the
front
end
cabinet and how to remove each fan from the panel.
Before performing
this
procedure,
make
sure
you
complete
the
preliminary steps in Paragraph 18.3.1 and 18.3.2.
NOTE

This procedure

not

Remove

system does

the

ten

for 50 Hz

screws

the power

power

supply

Remove

each

fan.

cable

(Figure
fan

systems only.

Fan

surrounding

pull
out
the
entire
cable (Figure 18-3).
Pull

have

panel

Panel

the

until

connector away

fan

panel

the

from

four

then

catches on

the

18-17).

removing

The

Assembly.

screws

carefully

the

fan power

plug

the

surrounding

the

Fen Power Cabls

Washer

Screw

Figure

18-17

Fan Panel Assembly

18-19

REMOVAL AND REPLACEMENT PROCEDURES

18.3.8

Front Door Filter Removal

This procedure describes how to remove the
front
door
of
the
front
end
cabinet.
procedure,
make
sure
you
complete
the
Paragraph

The

two

from

the

Before performing
preliminary
steps

filters

this
in

18.3.1.

filters are on the

inside of

the door.

Remove eéch

peeling
it
away from the velcro strip holding
are:
18-18).
The part number for the filters
and bottom, 12-11255-14.

it in
top,

filter

FILTERS

F/E CABINET FRONT VIEW

MRIBIET

Figure

18-18

Front End Cabinet - Front Door Filters

18-20

place (Figure
12-11255-08;

REMOVAL AND

18.3.9

REPLACEMENT

PROCEDURES

Rear Door Filter Removal

This procedure describes how to remove the three filters
rear
door
of
the
front
procedure,
make
sure
you
Paragraph 18.3.1.

end
cabinet,
complete
the

from

the

Before
performing
preliminary
steps

this
in

The filters are on the inside of the door.
Remove each
filter
by
peeling
it
away
from
the velcro strip holding it in place.
The
part numbers for the filters are:
top, 12-11255-02; and middle and
bottom, 12-11255-08.
(Figure 18-19).

FILTER

FILTERS

F/E CABINET REAR VIEW
MR. 16144

Figure

18-19

Front

End Cabinet = Rear

18-21

Door Filters

REMOVAL AND REPLACEMENT PROCEDURES

CPU CABINET ASSEMBLY

18.4

the

This section describes how to remove and replace
replaceable units in the CPU cabinet assembly.

major

field

Preliminary Steps

18.4.1

any

Complete the following steps before you do

work

CPU

the

cabinet.
1.

on the front of the CPU cabinet, turn the keyed system control
the OFF position (Figure
to
switch
control
terminal
panel
18-20).

State

Open the front
cabinets.

Enable

and

Algit

Active

GREEN

LEDs

doors

the

CPU

and

front

end

Restart

Sna——-‘lll'--wm

:
4

rear

Off = <1E> = Remots

RED

LED

RESTART CONTROL

SWITCH

TERMINAL CONTROL

SWITCH

MA-13582

Figure

18-20

System Control Panel

18-22

REMOVAL

18.4.2

Centrifugal

1500

AND

REPLACEMENT

PROCEDURES

CFM Blower Removal

This procedure describes how to remove
the
Centrifugal
1500
CFM
Blower
from
the
CPU
cabinet.
Before performing this procedure,

make

sure

you

complete

the

preliminary

steps

Paragraph

18.4.1.

On the lower left panel at the rear of the front
end
turn the main circuit breaker to the OFF position.

cabinet,

On the
switch

cabinet,

Remove the two screws from the
cabinet (Figure 18-21).

Lift off

front of the 876-A power controller in
CB1 to the OFF position (Figure 18-2).

the

rear of

the

CPU

top cover of

the

top cover.

TOP COVER

10-32 HEXS SEMS SCREW

Figure

18-21

CPU Cabinet

- Top Cover Removal
18-23

MR- 15158

CPU

REMOVAL AND REPLACEMENT PROCEDURES

At the rear of the CPU cabinet,
disconnect
from terminal block 1 (Figure 18-22).

the

blower

leads

release

the

blower

cable

Loosen the blower cable clamp
(Figure

and

18-22).

screws
On top of the CPU cabinet, remove the 26
blower to the CPU cabinet frame (Figure 18-23).

securing

WARNING

The centrifugal blower
equipment.
done

Removal

1is

the

heavy

piece

blower should be

two people.

CPU CABINET — REAR VIEW
NOTES:

1. TERMINAL BLOCK
2. SCREWS (10 - 32)

3. BLOWLR CABLE

4. CABLE CLAMP

Figure

18-22

MR- 16140

CPU Blower Cable Removal

18-24

the

REMOVAL

Using the
away from

handles
the CPU

AND

on top of the blower,
cabinet frame.

REPLACEMENT

lift

the

PROCEDURES

blower

and

NOTE

Upon power
up
after
installation
of
a
new
blower
assembly,
ensure
that the blower fans
rotate in the
downward
direction
(as
viewed
from
the rear of the cabinet, looking into the
blower

exhaust

port).

rotation
is
reversed,
connection on the terminal
for reversed leads.

BLOWER
HANDLE

the

direction

check
the
harness
block (Figure 18-22)

SCREWS

BLOWER

T e

iiiii
Ty

IR e

]
]
MR.15159

Figure

18-23

CPU

Blower

Removal

18-25

Rear

View

REMOVAL AND REPLACEMENT PROCEDURES

18.4.3

Modular Power Supply Removal

remove

This procedure describes how to

power

modular

individual

supplies from the power supply assembly in the CFU cabinet. Before
performing this procedure, make sure you complete the preliminary
steps

in Paragraph

18.4.1.

the

On the front of the 876-A power controller, switch CBl1

from the
to remove
Select the modular power supply you want
Loosen the thumbscrew at the bottom of
power supply assembly.

OFF position (Figure 18-2).

the module.

Using the handle at the middle of the module, slide the
out of the Power Supply Assembly (Figure 18-24).
NOTE

You

can

sugplies

remove

from

all

the

power

modular

the Power Supply Assembly using

e wn | wn Y |
LN

A\N

\ ‘Lm;x._uu\

the above procedure.

THUMB SCREW

MR IBIGY

Figure 18-24

Modular Power Supply Removal

18-26

module

REMOVAL

replace
above
in

AND

REPLACEMENT

PROCEDURES

the modular power supply, simply repeat steps
1
the
reverse
order.
Exercise
caution
when
being
"mated"
to
the
backplane
and
bus

regulator

L———

is
assemblies,

18.4.4

This

CPU

procedure

cage

the

procedure

how

Before

to remove module

boards

performing

module

Connect

the

around

the

the grounding cord, on the
side
of
to the plug on the module case (Figure

the

from the

card

this procedure, make sure you
steps in Paragraph 18.4.1.
The
cleaning
paddle fingers is found in Section 18.5.

the

Strap

velcro

your

wrist

strap,

connected

wrist.

Break the recessed
open the case,

Place the module case
the upper half of the

seal

the

case

left

floor

side

so that

TOY

ON/OFF

H7231

battery

CPU
18-25).

the

cabinet

the

cabinet

module

frame,

case

and

foam padding

exposed.

MODULE
ACCESS

—~ GATE

MODULE

CASE -

2
I
Figure

bar

preliminary

1If replacing the L0201 console
module,
turn
switch to the OFF position.
It is located on
back-up unit (Figure 18-2).

frame,
3.

for

3
the

Replacement

describes

assembly.

complete

Module

18-25

Module

Case

Ground

18-27

L
Connection

REMOVAT. AND

REPLACEMENT

PROCEDURES

Choose the module board you want to replace.

Turn the wing nut

at
the
top
of the hinged gate covering that module board and
open the gate (Figure 18=26).

Grasp the bad module board
work

out.

inside the card cage

and

carefully

Place the bad board on the foam padding on the
upper
half
of
the
module case.
Take the good module board out of the module
case

and place

into the empty slot.

Close the hinged gate and latch the wing nut at the top of
the
gate, and, if the TOY powcr was turned of at the H7231, turn it
on.

10.

Secure

11.

Disconncct the grounding cord from the module case,
the

12.

the bad board

strap

in the module

case.

then remove

from your wrist.

On the Reason for Return label on the lower right side

module
module,

the

case, make sure you indicate what is wrong with the bad
your namc,; and badge number in the spaces provided.

WING NUT

MODULE ACCFEFSS

Figure

18-26

GATE

CPU Module

Access

18-28

Gate

REMOVAL

18.4.5
The

AND

REPLACEMENT

PROCEDURES

Array Modules
Mb,

described
module is
have
to

16 Mb, or 4 Mb array modules are removed
as
previously
for
CPU
modules.
However,
1if a 64 Mb or 16 Mb array
to be replaced, the SMUs
(standard
memory
units)
will
be
removed
and reinstalled on the new array module.
To

remove

SMU

from

the

array,

use

the

following

procedure:

Remove

the

two

mounting

disengage

the

Carefully

work

Reverse

previous
that
the

18.4.6

screws

from

the

from

the

four

standoff

SMU

from

its

connector

the

insuring
memory

SMU

two steps
standoffs

faulty

SMU,

crowns.
on

to install
are locked,

the

mother

beard.

a
replacement
SMU,
and then install the

module.

Air

Filter

This

procedure

card

cage

Removal

describes

support

how

remove

the

air

filter

make

sure

under

the

assembly.
WARNING

Before

performing

this

procedure,

have

vyou

completed
the preliminary steps in Paragraph
18.4.1.
The CPU must be powered down.
If not, the
CPU
will
power
down
automatically if you try to
remove

the

without

Turn

the

air

filter.

an air

filter

black

catches

two

support

assembly

(Figure

18-27).

Slide

the

air

filter

You

that

out

cannot

power

the

bottom

they

the

are

CPU

parallel

cabinet.

AIR FILTER CATCHES

AIR FILTER

Figure

18=27

CPU

Card

the

CPU

the proper position.

Caye

Air

18-29

Filter

Removal

the
to

card
the

cage

support

REMOVAL AND REPLACEMENT PROCEDURES

18.4.7

Air Flow Sensor Removal and Installation

This procedure describes how to remove the air
flow
sensors
from
the
card
cage
assembly.
Before performing this procedure, make
sure you complete the preliminary steps in Paragraph 18.4.1.
Air Flow Sensor Removal -

18:4.7:1

There are two
air
flow
sensors
on
the
card
cage
support
Disconnect the cable connector from
18-28).
(Figure
assembly

Remove the screw from the middle of the

the air flow sensor

remove

18.4.7.2

the

air

(Pl

or P3).

flow sensor.

air

flow

sensor

Air Flow Sensor Installation -

Installation

Test the new sensor after
power-up
by
giving
a
SHOW
command.
The sensor is good if no fault is reported.

18.4.8

and

is the reverse of

the removal procedure.
POWER

Air Temperature Sensor Replacement

This procedure describes how to remove the temperature sensors from
the
CPU
cabinet.
Before performing this procedure, make sure you
complete the preliminary steps

18.4.8.1

in Paragraph 18.4.1.

Temperature Sensor Removal -

There are four temperature sensors;
three
on
the
card
cage
assembly,
and
one
on
the
card
cage
support
assembly.
Disconnect
the
EMM
harness
cable
spade
lugs
from
the
temperature sensor you are removing

(Figure 18-28).

Remove the screw from the right side of
remove

the

temperature

the

heat

sensor

and

sensor.
NOTE

For

troubleshooting

emergency

situations

only,
the
system
may be operated with one or
more
temperature
sensors
removed
or
disconnected.
Once
a sensor is disconnected,
the console (if in PIO mode)
will
report
the
condition via a message as follows:
?EMM DETECTED TEMPERATURE INPUT TN IS
OPEN
OR
VERY
COLD.
THIS
IS
A
WARNING AND WILL NOT
INITIATE A POWER DOWN SEQUENCE.

18.4.8.2
Temperature Sensor Installation - The temperature
sensor
installation procedure is the reverse of the removal procedure.

18-30

REMOVAL

AND

REPLACEMENT

PROCEDURES

T4
”"xggsflfe;s,erv‘gg

TEMPERATURE

TEMPERATURE
SENSOR

TEMPERATURE

SENSOR

fear

1] F
i

€

P1% AIR

[

*..w%g@fl%g}f*fiwfi%é;:g

ig-

TEMPERATURE

pgéSMR

SENSOR

—

[]

@ 7
MR-18180

Figure

18-28

Temperature and Air Sensor

18-31

Locations

REMOVAL AND REPLACEMENT PROCEDURES

18.4.9

876-A Power Controller Removal

This procedure describes how to remove the 876-A
power
controller
from
the CPU cabinct.
Before performing this procedure, make sure
you complete the preliminary steps in Paragraph 18.4.1.
1.

Disconnect the ac distribution cable
the 876-A (power to the 876-A).

from J18

Oon the lower left panel at the rear of the front
end
cabinet,
switch
the
main
circuit
breaker
to the off position.
This
action cuts off power to the power controller.
Disconnect MPS cable connectors from ocutlets Jl1
rear of the power controller (Figure 18-29).
Disconnect the blower assembly cable
at the rear of the power controller.
Disconnect SCP
the

rear of

Disconnect BBU
the

rear

"DEC

the

Pwr Bus"

power

cable connector from

outlet

from J17

the

rear

the

rear

controller.

Disconnect MPS
at

from outlet J6

J13

controller.

Disconnect MPS "Total Qff"
of the power controller.

J10

and J12 at the

connector from outlet

cable connector

Disconnect BBU power connector
power

rear

controller.

"Delay Out"

the

connector

from outlet J8

"Alarm" black/white cable connector from

rear of

outlet

the power controller.

POWER CONTROLLER

=
Ja

O
J5

0
J7J8

112

X0 &
J9
J1o

13 (fi)€f>iiiiii

¢ ..@
L1

GROUND

Figure 18-29

MR-16154

Power Controller and BBU - Rear View

18-32

REMOVAL AND REPLACEMENT PROCEDURES

10.

Disconnect the RL02 disk drive and BAll-A unit assembly power
from outlets L1 and L2 (respectively) at the rear of the
cords

power

controller.

Move around to the front of the CPU cabinet and remove the six
three on the left and three on the right side of the
screws,
power controller

(Figure 18-30).

WARNING

The 876-A power controller is a heavy piece of
Be careful when sliding out the old
equipment.
The
the new.
power controller and inserting
removal and insertion is best handled
task of
by

slide the power controller out from the CPU cabinet.

;

12.

two people.

N)g
>4
POWER CONTROLLER

SCREWS
MR-16157

Figure 18-30

Power Controller Removal

18-33

REMOVAL AND REPLACEMENT PROCEDURES

H7231 BBU Power Supply Removal

18.4.10

This procedure describes how to remove the

H7231

battery

back-up

Before performing this
supply from the CPU cabinet.
power
in
procedure, make sure you complete the preliminary steps
Paragraph

18.4.1.

to off
On the front of the 876-A power controller, switch CBl1
Then turn the TOY ON/OFF switch
to remove power to the BBU .
on the front of the BBU to the off position (Figure 18-2).

Disconnect cable connector P18 from the rear of the

Disconnect bus bar ground connector and bus bar cable connector

Disconnect BBU main power cord connector from outlet L3 at

the

Disconnect black/white cable connector P6 from the rear of

the

supply

(Figure

from the rear of

rear of

BBU

power

18-31).

the BBU power supply.

the 876-A power controller.

BBU power supply.

POWER CONTROLLER

Ji4
J12

J13

J16

J1é

J17

GROUND

REAR VIEW

BBU MAIN POWER CDRD7

—BUS BAR CABLE

MR-18188

Figure

18-31

BBU Cabling

18-34

REMOVAL

AND REPLACEMENT

PROCEDURES

Move around to the front of the CPU cabinet and remove the
two
securing nuts, on the sides of the power supply (Figure 18~32).
7.

Slide the power supply forward out from the CPU cabinet.

Remove

side,

the four screws, two on the
from the power supply shell.

left and two

the

right

Slide the power supply shell out from the CPU cabinet.
10.

A new H7231 power supply comes with shell sleeves.

Reverse the

above procedure to install the new power supply.
NOTE

the
on
switch
select
voltage
front
of the power supply is set correctly for
your environment (120 V).
Also, make sure that

Make sure

the

the TOY ON/OFF switch is set to the on position

when the system

is powered-up.

NUT

SCREW / BBU SHELL

)
000
0000,

0202

SCREW

00000
ooo

SCREW

BBU

SCREW

4
SCREW

TOP VIEW

Figure

18-32

BBU Removal

18-35

MR-18161

REMOVAL AND REPLACEMENT PROCEDURES

18.5

MODULE

18.5.1

PADDLE

CONNECTOR CLEANING

PROCEDURE

Introduction

This procedure describes the cleaning method
module paddle connector fingers.

for

the

gold

plated

NOTE

This

procedure

method
each

which

time

replaces

the

traditional

removes up to 10 microinches
eraser is used for cleaning.

The continuous gold

removal

base
metals
(copper
which in
turn
causes

causes

eraser
of

gold

corrosion of

and

the

nickel) under the gold,
contact
intermittents
and

opens.

For

additional
l.

detail

Standard

Board

Gold

(PWB)

DOCUMENT

to:
EL-FS$266-00,

Contact

IDENTIFIER:

Cleaning

Required

Protective

gloves,

37-175-X

(where

18.5.3

Cleansing

SDLVEX gloves

size).

There

Edmont,
is

time.

Pads,

vendor

Digital

D igital

part

number

Precautions

DO NOT

USE

assembly
tapes,

gold
such

wipeés to clean any
part
of
disk heads and packs, tape

disk
or
tape
and ma gnetic

heads

etc.

2.,

NO SMOKING - Highly toxic phosgene
coming into contact with a burning

Do not expose Gold Wipe pads to sources of extreme
soldering iron) as toxic gases can be generated.

Use

Avoid prolonged

Wear the specified gloves.
Do not use
gloves
=~ they will dissolve and leave
on

Wiring

Materials

Cleaning material:
TX809 GOLD WIPES
number:
49-01603-01.

this

Printed

Field
Service
Miscell aneous
4,
1984, Title:
Gold Finger

part

Title:
Process

A-SP-ELFS266-00

Miscellaneous Fiche
(Green)
Tech
Tip
Number
1,
April
Cleaning Using Gold Wipes

18.5.2

refer

Engineering

with

the

adeguate

contact

gas can develop
¢igarette tip.

from

heat

fumes

(e.g.,

ventilation.

contact with

skin

surfaces.

18-36

and

eyes.
Latex
harmful

or
polyet hylene
plasticize d film

REMOVAL

Wear

safety glasses with

Contact

lenses

should

not

After

using Gold Wipes,

water

before

not

most

18.5.4

side

handling

yourself

the

rubber,

polystyrene,

properly

using

grounding

one

Gold Wipe

a TX809

cleansing

Open

Firmly grasp

the module

unpopulated

area

and

damage.

physical
the

packet,

and

¢f

pre-folded

Place the module
and apply finger

and

aluminum,

and

should

pad

clean,

for

each module.

remove

the

cleansing

cleaned

module

the

minimizing

partially

the

fingers

length

conductive,

pad.

handle,

the

risk

reversing

static

the

pad
the

opened

pad

away
from
the
cleansing action

fingers.

the

fold

the

pad

‘

the pad
located

and
in

packet
in
a
an
adequately

R——

After cleaning each module, discard
disposal
receptacle
which
is
ventilated area.

Figure

open.

paddle fingers into the partially
pressure against the pad.

parallel

Wipe all paddle
required.

strap.

pad

to be

the

Maintain finger pressure while pulling the
paddle fingers.
As shown in Figure 18-33,

11.

soap

PRECAUTIONS.

Place the module on a static mat,
and grounded table surface.

10.

with

Cleaning Procedure

Ground

Hold

thoroughly

drink.

plastics.

Use

PROCEDURES

shields.

wash hands

REPLACEMENT

be worn.

food

use Gold Wipes

AND

18-33

Paddle Finger Cleaning Action

18-37

CHAPTER 19
TECHNOLOGY AND TOOLS

19.1

MCA DESCRIPTIONS,

Table 19-1
mnemonics,

LOCATIONS,

AND PRINT SET CROSS

REFERENCE

contains an alphabetical
1list
of
MCAs,
with
name descriptions, and print set locations.
Table

19-1

MCA/Print

Description

ABS
ADA

ABus interface
Address translate

ADB
ADD

Address translate
GPRA/GPRB address,
EBox WBus address

ALU

EVA,

ARB
ACB
ACC
ACL
ALN

Arbitor
Adder Control B
Adder Control C
Adder

Carry

Reference

Print
Location
(Quantity)

MCA

ARbus,

Set Cross

their

MCC4
MAP1(3)
MAP2(2)
MAP2
WBus match A/B,
EDPC

BROT

EDP1(2)
EDP2(2)
EDP3(2)
EDP4(2)
MCCé6
FAl3
FAl3
FAlOQ
FA04(2)
FAO05(2)

Look-ahead

Alignment

BEN

UPC,

CAM
CKP

Match
Check bit

micro stack address

MAP3(2)
MCDW

CLA
CRA
CRB

Carry Look-ahead
Control Register A
Control Register B

EDPF
MCCJ
MCCJ

DBS

Double Buffer Slice

DPC

Data

DPP

control, parity control
Data Path Parity and carry

ECC

MCDM

ERR

Error

MCCM

Patch

Control

counter

CSBP(3)

IBD6(2)
IBD7(2)
= ALU control,

WBus match

look-ahead

EDPD
IDP6(2)

TECHNOLOGY

MCA

AND

TOOLS

DESCRIPTIONS,

Table

LOCATIONS,

19-1

AND

SET

CROSS

MCA/Print Set Cross Reference

REFERENCE

(Cont.)
Print
Location
(Quantity)

MCA

Description

FBR
FAD

FBox Registers
Fraction Adder

FAOQ1l
FAOB(2)
FA07(2)

FXP

Exponent

Processor

GXP

Exponent

Processor

IAD

IBox

IBF

FAO8(2)
FAQ9(2)
FAQ1
FAQ1l

Adder

IDP1(4)

Instruction

IDP2(4)

Buffer

IBD1(3)

IBD2(3)
|

IFG

Decode

Flags,

I0P

data

IST

IBox

IVA

Bus

IBD3(3)

buffer

control

IBDA

path

Stall
IBox Virtual

IBD4(2)
IBD5(2)
ICAG

Address

IDP3(4)
IDP4(4)

MAI

MBox

MAX
MCF
MCB

Multiplier Accumulator Extension
Microcontrol Field Decode
Multiply Control B

Array

Interface

MCL

Multiply

MDP

Memory

MIC

UPC,

CSDR

MMD

MBox

Microcode

MMS

MBox Microsequencer

Carry

Data

MCC8

FM11
MCC6
FM09(2)
FM10(2)
FMO08

Look-ahead

Paths

MCD1(2)

MCD2(2)
MCD3(2)

MPR

Multiplier

MPY

Multiplier

MPZ

Multiplier

load

sync.,

Data

clear

flag

sync.

Registers

Unpacker

CSBQ(2)

MCCA(2)

MCCB(2)
MCC1
FM01(2)
FM02(2)

FM03(2)
FM04(2)
FM0O5(2)
FMO6(2)
Extension

FMO7(1)
FMO7

MSQ

Micro Sequencer

(FBox adder)

FAll

MSQ

Micro

(FBox multiplier)

FM12

PDP

Data

Sequencer
path

WBus,
OPBus

parity checker - GPRA/B, ALU,
ALU shift bits, VMQ shift bits
long word, WReg longword

REG

Address

RES

Response

RRC

RAM

Control

EDPH
MAPP
MCC5

FAl2

TECHNOLOGY AND TOOLS

MCA DESCRIPTIONS, LOCATIONS, AND PRINT SET CROSS REFERENCE

MCA/Print Set Cross Reference

Table 19-1

(Cont.)
Print

Location

(Quantity)

MCA

Description

SCE

Shift Count Element - shift count information

and control, ALU control, data path control,
"
ARBUS receivers

EDPE

ICAS8

IBox micro sequencer
Shifter - Post ALU shifting, data formatting,
0 - 63 data rotation, WBus receive

SEQ
SHF

EDPA(2)

EDPB(2)

FAO02(2)

Source Operand

SOP

SPA
SPD
STA

Scratch Pad Addressing
Specifier Decode
Port Status

IDP7
IBD9
MCC7

UFO
UPC
UPK

Data Register
IBox Micro PC
Unpacker

MCDU
ICAS8
IDP6

VAL

IBuf valid Bits

IBD8

WVP

Write Valid

MAPL

Table 19-2 contains a list of MCAs by module, with
print

set

Table 19-2

MCA

Module

Qty

MCA Descriptions and Locations

Location

Description

Name

Name
EBox

corresponding

locations.

MCAs

L0209

(EDP)

EBox Data Path

ADD

ALU

CCD
CLA
DPC
PDP
SCE
SHF

L0216

(CSB)

Address

1
1
1
1
1
4

F
F
D
H
E
A-B

Condition Codes
Carry Look Ahead
Data Path Control
Parity Data Path
Shift Counter
Shifter

Arithmetic Logic Unit

1-4

Control Store B

3
2

Branch Enable
Microseqguencer

P
Q

BEN
MIC

19-3

TECHNOLOGY

MCA

AND

TOOLS

DESCRIPTIONS,

Table

19-2

Module

MCA

Name

FBOX

L0212

L0213

LOCATIONS,

MCA

Qty

AND

Descriptions

Location

SET

and

CROSS

REFERENCE

Locations

(Cont.)

Description

MCAs

(FBA,

FA)

FBox

Adder

ACB

Adder

Control

ACC

Adder

Control

ACL

Add

ALN

4=5

Alignment

FAD

Adder

Carry

Look

6-9

FBR

FXP

Exponent

GXP

MSQ

Microsequencer

Exponent

RRC

RAM

SOP

2-3

Source

(FBM,

FM)

Ahead

Control

Operand

FBox Multiply

MAX

9-10

Multiply

ACC

MCB

Multiply

Control

MCL

Multiply

Carry

MPR

1-2

Multiply

Unpacker

MPY

3-7

Multiply

MPZ

Multiply

MSQ

Microsequencer

Extension

Look

Extension

IBOX MCAs

L0208

(IBD)

IBox

DBS
IBF

L0207

L0206

Buffer

Decode

4
9

6
1

Double Buffer Slice
Instruction Buffer

IFG

IBox

FFlag

I0P

IBox

SPD

Specifier

Decode

VAL

valid

Logic

(ICA)

IBox

Control

Logic

Bit

IST

Istall

SEQ

Sequencer

UPC

Micro-PC

(IDP)

IBox

Data

Control

Bus

Path

DPP

IAD

IBox

Address

IVA

IBox

Virtual

SPA

Scratch

UPK

Unpacker

Data

19-4

Path

Parity

Pad

Address

Ahead

TECHNOLOGY

MCA

DESCRIPTIONS,

Table

19-2

Module

MCA

Name

MBOX

LOCATIONS,

MCA Descriptions

Oty

Location

AND PRINT

and

SET

Locations

CROSS

Description’

(MAP)

MBox

Address

ADA
ADB
CAM
REG

5
1
2
2
1

WVP

L0220+

L0204

(MCC)

Path

1
2
6
5

Address Path A
Address Path B
Match
Register

Written-Valid-Parity

ABus Control
Arbitrator
Control Register A
Control Register B

Control

ABS
ARB
CRA
CRB

1
1
1
1

4
6
J
J

ERR

Error

MAI
MCF
MMD
MMS
RES
STA

1
1
4
1
1
1

8
6
A
1
5
7

Memory Array Interface
Micro Control Function
Memory Data Register
MBox Microsequencer
Response
Status

1
1

W
M
1
U

Check Parity
Error Correction Code
MBox Data Path
Data Registers

Clock

(MCD)

Data

Path

CKP
ECC
MDP
UFO

1
1

CLOCK MCA

L0217%

(CLK)

Clock

CLC

L0230

for VvAX

8650

L0231

for VAX

8650

Control

NOTE

"Location” refers to
a
specific
module
print.
e.g., the Clock Control MCA is found on CLK3.

TOOLS

REFERENCE

(Cont.)

MCAs

L0205

AND

TECHNOLOGY AND TOOLS

MCA DESCRIPTIONS,
19.2

LOCATIONS, AND PRINT SET CROSS REFERENCE

ECL TROUBLESHOOTING INFORMATION

The VAX 8600 processor logic is

implemented with Emitter

Coupled

Logic
(ECL) technology.
There are numerous Technical Data books
logic,
of
family
this
of
available which describe the theory
including the advantages and disadvantages of its use,

From a troubleshooting aspect, there are
a
number
of
concerns
that must be considered when investigating ECL circuits.

19.2.1

Test Equipment

As ECL logic is relatively fast, comparable test
equipment
must
be
used.
For
scoping,
a
200
MHz
or faster oscilliscope is
required, along with equal length probes and
short
(6
inch
or
less)
ground
clips.
Beware that 'kinks' in the probe leads may
distort

the waveforms.

19.2.2

Termination

One of the most critical components in
an
ECL
circuit
is
termination.
It can be the source of many circuit problems.

the
The

text that follows describes the basic ECL circuit and termination

techniques
used
in
the
VAX
8600/8650,
troubleshooting flowchart and related waveforms.

followed

Every ECL signal run requires termination.
The VAX 8600/8650 CPU
employs
parallel termination techniques on both single-ended and
double-ended

buses.,

19.2.2.1
Single-ended ECL Signal Run - This type of
termination
is used to terminate a signal at or near the end of the run.
The
termination consists of a 56 ohm resistor
tied
to
-2
V.
See
Figure

19-1.

19.2.2.2
Bi-directional
ECL
Signal
Run - This
type
of
termination
(Figure
19-2)
is
wused
in
bus applications where
multiple
bus
drivers
are
employed,
and
the
signal
run
|is
terminated
at
both
ends
of the run with 56 ohms to -2 V.
For
this application, 25 ohm bus drivers are
used
(as
the
circuit
impedance
will
be 28 ohms).
Note that these special 25 ohm bus
drivers have a very high output impedance.
When all drivers
are
disabled,
the
signal
will
be
at
a -2 V level (rather than a
typical

-1.8 V level).

-2V

DRIVING OR

SOURCE GATE

RECEIVING OR

562 2 LOAD GATE

84H.15823

Figure

19-1

Single-ended ECL Signal Run

19-6

TECHNOLOGY

AND

TOOLS

Termination
-2V

-2V

;; 56 (1

:’! 56 1

<k
ENABLEL —Of

(

O—— ENABLE
L

25 02

250

BUS DRIVER

BUS DRIVER
MR-16088

Figure

19=2

Bi=directional

ECL Signal

Run

19.2.2.3
Termination
Components - Following
is
a
list
termination components used in the VAX 8600/8650 system.
1.

56 ohm
discrete
component
resistor
(13-02602-00).
For
instance, ABUS termination on STM/L0224 module (print STM1)

10-pin STERM SIP

modules

where

18-pin VTERM SIP (20-21347-01) used on
CPU
modules
the signal leaves the module or requires visibility.

where

the

signal

does

(19-17493-00)
not

leave

used on

UCPU

the module.

Refer to the STERM SIP and VTERM SIP data sheefs
on

these

for more details

components.

19.2.2.4
How to Locate the Termination Point of a Given Signal There
are
several
methods
used by the engineering CAD tool to
indicate the termination of an
ECL
signal
1in
the
engineering
drawings.
Although there are no hard and fast rules to determine
where a signal is terminated, there are some
dgeneral
guidelines
that
are
used.
Beware that these guidelines are sometimes not
followed.

1If the signal does not leave the module
on
which
it
generated,
it
will
be
terminated
on
that module.
schematic
representation
will
depend
upon
whether
termination is on an STERM or a VTERM.

was
The
the

If terminated by an STERM, a resistor will be drawn at
the
output
of
the
signal
source
gate.
If terminated by a
VTERM, the signal is terminated within the VTERM
which
is
shown on the visibility terminator print pages near the end
of the module schematic set. See Figures
19-3
and
19-4.
Figure
19-3 is taken from print set sheet MCDT, and Figure
19-4

taken

from print

set

19-7

sheet MCDV,

TECHNOLOGY AND TOOLS
Termination

110

MCDT CLK6
PHASE TIB L

— MCDT CLK3 TIBA L

_10

10H210

.
MCDTCLK3TIBB L

— MCDTCLK3TIBCL

MR-16148

Figure

19-3

STERM

Termination

VTERM

Z105

—MCDT CLK3 TICB

B2 MCDV VIS BUS DATA 02 H

——{D0

"W\

—MCDT CLR3 11D B H —2 D1
MCDI LAT DSM SEL1 A H —24 D2

ANV
MA-

MCDI LAT DSM SELO A H —H] D3
—~MCDT CLK3 TIA B H~i3-04

MWv

MAPQ CACHE DAT PA 05 H—lé-Ds
~MCDT CLK3 T1B B H —
D6
MCCM HLD ERR DAT REG H — D7

A
AN
MMW\

MCDV VIS MUX S2 H —-H 4
MCDV VIS MUX S§1 H — 2 SEL
MCDV VIS MUX SO H 1 1
MCDV VIS MUX ENA 1 L -1;0 EN
MR-16147

Figure

Notice

CLK3

19-4

VTERM Termination

two of

the output signals shown on print MCDT,

MCDT

T1B A L and MCDT CLK3 T1B C L, are terminated on this

module and do not have visibility
the
gate
output).
The
signal
terminated
at
illustrated.

the

VTERM

(termination is shown
at
MCDT
CLK3
TIB
B
L is

set

sheet

MCDV

VTERM termination of a signal will identify the termination
component
location
wusing
the 'Znn’' identifier within the
SUDS

drawing.

The

physical

type

and

1location

the

termination
component
for
STERM and discrete termination
can be found only by using the module NAME-SORT wirelist.
2.

1If

the

the signal
signal

leaves

will

the module on which
terminated

determine where the signal

is terminated,

the

BL or

the

console

SHOW NAME

’'signal

the

'signal

name

SDB

it was

another

generated,

module.

use:

NAMESORT wirelist.

sort'

name'

command.

table.

Once you determine which module the

signal

terminated

on,
refer
to
the
'SDB
VISIBILITY'
pages
(which
are
generally near the end of the module schematic set).
This
will
give
you
the
pin
and
component
number
of
the
termination package (either a VTERM SIP or a
10164V
DIP).
See the example that follows.
19-8

TECHNOLOGY AND TOOLS
Termination

Example 19-1
The signal
print

CSAS

Off Module Termination

'CSA UMCF 4 A L'
and

(Figure

terminated

19-5)

originates

ICAK

at VTERM

Z29

(Figure 19-6).
Note that on
print
ICAK,
the
signal
is
titled '-CSA UMCF 4 A H' and there is no designator to show
_
that the signal is on backplane pin Al3-42.
This is due to
a
deficiency
1in the CAD tools.
Note that the wirelist BL
sort

entry gives

the pin

number of

the

backplane,

well

as
some
print pages where the signal goes to (See Example
19-2).
Since there is no
designator
for
the
signal
on
print
ICAK,
the print page number is excluded from the BL
list.
However, once you determine which module the
signal
feeds, you need only check the VTERM print page to find the
signal.

CSA7 UMCF 4 H ——

_
CSAUMCF4
AL
-

CSA UMCF
4 A H
MA-16148

Figure

19-5

UMCF

L Signal

Generation

VTERM

—~CSAUMCF4AH

229

——po

ICA6 UTRAP CTL1 H —d b1
ICA6 IFORK CTL2 H —24po
ICAB LD ORSAVO H —2p3

AAAAAAA

ICAS INH IBF SHIET H —2dpa

—ICAG SET OPVILATH —2d o5

ig
’
,
18
[V ICAK
DIAG BYTE
2 H,

M-

AAA-

14
et G

A5 D7

ICAK VIS MUX SEL2 C H — 4
ICAK VIS MUX SEL1 ¢ H —2d 2 sEL
ICAK VIS MUX SELO C H —24 1
1

ICAI VIS MUX ENAO L —O) EN
MR-16148

Figure

Example

19-6

Extract

19-2

UMCF

from

4 A L Signal Termination

CPU

Backplane

Wirelist

BL-sort

(70-19198)
-CSA UMCF

AC3

AC3
AC13
AC1l3

A47

A47
A42
A42

A H

0.00

-10.00

0.00

EIPZ

3.42

17.09

0.00

-200.00

EOIPZ

3.42

17.09

-10.00

-200.00

19-9

CSAQ

CSAS
ICAO
ICAB

Cc8

Cc4
B7
D8

CSAS

TECHNOLOGY

AND

TOOLS

Troubleshooting

ECL Signals

19.2.3

Troubleshooting

Figures

19-7

ECL

circuit

through
failures

ECL Signals

19-20

illustrate some of

that may

the

common

be experienced.
Although many of
these problems were
more
symptomatic
of
older
wire-wrapped
backplanes,
you
may
experience
similar
faults
caused
by
electrical/mechanical failures due to current processes such as
dirty
finger
pins,
bad
ground cubes, nicked backplane wires

(from an ECQ), or cold solder
a typical ECL waveform.

joints.,

Figure

19-7

illustrates

TYPICAL ECL WAVEFORM

-1V

LN
4

-2V

TMTM
I

EFNEINTEE ii[ i3 3 : .;;::“:ii i3 i i
o N /
s
F

5§ 884878

BBRI

I!Ei’.llli

L ibdd 32 34

LR E REREEEREEAI

’:

‘

-3

HOR = 10 NS/DIV

5602

SCOPE HERE

MR-158

Figure

19-7

Typical

ECL Waveform

19-10

O|N3I~L8nOoYlHS
1AwL

S3A MOS

butjoyseTqnoay
FJMHLIOSWd

3O£IJ|LW6NINHDILNG IDHONVSIOLVSISNIY 4ONo]YD

0LWE-

19-11

ONNOYD

TDA3SLHHNNVAdDILHINTNEIOLNWOIJIT3SGLTHNIODAHTS
N3O LOdNE HLIM

TYWHON

592

ONELDLNIOD g1(3w~n
‘HIHLIDOL

LS 6

N3O INdNI Q3L 01

gTYNOL D3YIg- 2NO~IALVHNOINNOYYIHLL

SHL1NIOEM8 sSyaslga a3gvsio TYNOIS

NS3OHLNOYON3HI4NDIEIYHLIQ0LINYLW)SYI{NHDITWHYNHOIS

TYNDIS

TYNDHS

53HNDI4§ONYL dOHdWIb3

4OITOSMVNNYM3DLNILHDDTISNINSOOTSIYNLHGTNYAOILDTYYLIONDJSHNI3IOS3YNGH8MEDA12STIYLOVI4LH0I1HNOL34(NWHL01FSZS58IN-OITON4F'ALIVHL1LAIL32YIHSH8U1NOILV3IdNIONNIDHYTOON3LI0YSOLSDOAHL
T"OVNINSDISN9H631I5M802d)4{10ALQ~NY
1T|Y0NDIS3

MWNDIS

Troubleshooting

TECHNOLOGY

O3unolid

WHOAIAVM

ECL Signals

AND

OTLWONFLDHIOHS

TYNDHS

TOOLS

6ILNOI HOLSIS3Y

TECHNOLOGY

AND

TOOLS

Troubleshooting

ECL

Signals

e .

[

-y

i L. 1

]

TMTM

-1V

IMPROPER TERMINATION: TOO LOW

ebedododed.
TF
e 0

HOR = 50 NS/DIV

SCOPE HERE

MR-15831

Figure

19-9

Improper

Termination:

Too

low

SIGNAL SHORTED TO~2 Vv

-1V

—

~+
LEiil s adal
LB 2

]

so 350414y

3§ ¥

NENENEY

]

WEFENENE
3

T
-3V

HOR = 50 NS/DIV

2V
f’

{

—2v

\\ ’p[

560

]

SCOPE HERE

560
-3\

Figure

19-10

Output

Shorted
19-12

MR-15878

-2

TECHNOLOGY AND TOQLS
Troubleshooting ECL Signals
UNTERMINATED WAVEFORM: 562 RESISTOR MISSING

1113 ii 3
8

¥ 3

$ 3 £ 3 3 3§ 3 Ei!l::lil! § 1 & 1 1§21 i 313 $ i § 3

[RE D D]

Elil_—ii'l

-2V

353

813

¥ 5

T
-3V

HOR = 50 NS/DIV

-2V

560

-2V

fgt‘\
[
2

560

/\‘: vl

MISSING RESISTOR

S€

SCOPE HERE

-2V
#B-18827

Figure

19-11

Unterminated

Waveform,

Ohm Resistor

Missing

SIGNAL SHORTED TO =2 V

5
8

§§ %% i 3 % i & § 2 fili::l!ll £ 3 5 3 i 3 § 3 § 5 3 f 33 21

lliili!!!iiii!ll_‘_iill

I RB BRI

-2V m‘p

—

-3 v

i§id

INERIREE R

I‘h‘

—

HOR = 50 NS/DIV

-2V
,

SHORTTO -2V

SEOPEHEREE\\kflk

~I~

—

)

-2V

Figure

19-12

Inverted

Output

19-13

Shorted

MR- 15828

to -

TECHNOLOGY AND TOOLS

Troubleshooting ECL Signals

—

id.t.L

LRI]

IMPROPER TERMINATION: TOO HIGH

111t nnutaf;nun"‘ni
5 8

)

llll‘bf!
L

NUNIREERIENENIN]

33 7

¥ F

-3

e il
d

HOR = 50 NS/DIV

—+

-3V

560

SCOPE HERE

=2V
MR-15830

Figure

19-13

Improper Termination:

Too High

CAPACITOR IN SIGNAL RUN

TERY

'WPRESIREROA

HOR = 50 NS/DIV

LILILEE]

T17

.14

FF
¥ T FR N 8

ENW]

-2V

560

SCOPE HERE
——
SIGNAL COUPLED TO

GROUND
MR-15832

Figure

19-14

Capacitor

in Signal Run

19-14

TECHNOLOGY AND

Troubleshooting

ECL

OPEN ETCH: NO CONNECTION TO -2 V

~-2V

IR Lilil b i i 3 0 4 ¢ %3 Iiil::ll!! INEEEESENEEENEENENE!
LALALILE

RRLALALE

-4

AL NLL

LA I

-5V

’

HOR = 50 NS/DIV

-2V

560

2V
562 &

-2V

SCOPE HERE

’/

]

560

OPEN ETCH

-2
MR-15834

Figure

19-15

Open

Etch,

Connection

CHANNEL
1

H4 ::::T’“;,.“_m.

w’

IMPEDANCE MISMATCH

*I{

\—44 CHANNEL 2
VERT = .5 V/DIV

HOR = 50 NS/DIV

AREAS OF VARYING
IMPEDANCE
CHANNEL 1
PROBE

CHANNEL 2
PROBE
MR.T5824

Figure

19-16

Impedance

Mismatch

19-15

TOOLS

Signals

TECHNOLOGY

AND

TOOLS

Troubleshooting

ECL Signals

)

TM~

moss

1. 1.4

i411

e84

=TM~

=TM

bbbi ls

111

REEEEEE]

SIGNAL SHORTED TO GROUND

HOR = 50 NS/DIV

|
|

SCOPE HERE

TWISTED PAIR BACKPLANE WIRING

Figure

19-17

Signal

Shorted

to Ground

OPEN INPUT ETCH

-1V

§ i1 §.1 .01 1 B i1 i i1l ll!i;;illl i i1 IS ENENERE 1114
§

]

$ 3 3

-2V

&1 8 %

III!_—"I’

8§ %

$ 3 % 3

T
i P

LRI

]

T 0§

8 ¢

HOR = 50 NS/DIV

-3V

-2V

5641
560

T
|

‘\\—f
56

SCOPE HERE
OPEN ETCH

—2
BF-15B35

Figure

19-18

Open

Input

Etch

19-16

TECHNOLOGY AND TOOLS

Troubleshooting ECL Signals
TWO SHORTED SIGNALS

L =

[ 2

(

SIGNAL B. ::\' R

l
SIGNAL A ——L
'\\J
~J

A AND B
SIGNAL

SHORTED TOGETHER . “

“ HOR = 20 N5/DIV

W\/

VER = .5 V/DIV

,
MR-15837

Figure

19-19

Two Shorted Signals

COMPLEMENTARY OUTPUTS SHORTED TOGETHER

-1V

T
n

= =

\f#*;zr,\iuxfe-

U U IR ST P

W\i

SV SIS DT FOE L

-2V

-3V

-2V

SHORT HERE

5642

-2V

-2V
L1l

560

SCOPE HERE
-2V

Figure 19-20

Complementary Outputs Shorted Together

19-17

CHAPTER 20

VAX 8600/8650 REGISTER DESCRIPTION

Chapter 20 has been reorganized.
There are
no
longer multiple
copies
of
any register.
Unfavorable feedback from the field, the
increase in page
count
due
to
size
reduction,
and
additional
material
for some registers, necessitated the removal of duplicate
registers.

The

registers

are

listed

alphabetically,

except

the

C1780

registers, DR780 registers, DW780 registers, and SBIA registers are
listed alphabetically within the individual groups,
registers are listed under CI780.

ie.,

all

CI780

In the index, The Internal Privileged Registers
(IPRs),
Internal
(IRs), Miscellaneous Registers (Misc), and Machine Check
Registers
Stack Frame (MHCK
Stack
Frame)
are
1listed
both by
individual
Frame
Stack
The
groups.
alphabetically within
and
registers
registers are listed in two sub-groups, Machine Check Stack
Frame,
and Stack

Frame.

Error
wunless
not valid
is
Frame
the Stack
Keep in mind that
Handling Microcode has loaded the EBox scratch pad locations.

VAX 8600/8650

ACCS

20-7

EBCS

20-48

ASTLVL

20-7

EBXWD1
EBXWD2

20-51
20-51

BTOYO
3

20-8

CBUS

REGISTERS

20-52

EDPSR

20-53

EHMSTS

20-55

EHSR

20-60

20-20

EMD
ERRSIUM

20-63
20-148

RBUFO_3

20-113

ESASAV

RBUFC

20-114
20-129
20-130
20-176
20-177
20-180
20-182
20-184

20-63

BTOYO

CMISC

20-8

RXCS
RXDB

STXCS
STXDB
TURN

TXCS
TXDB

UTOYO_3
XBUFO0_3
XBUFC

C1780 CNFGR
CI1780

MADR

C1780
C1780
CI780
CI780

MDATR

PMCSR

PORT CONTROL
PORT ERR STATUS

CI780 PORT FAILING ADR
CI780 PORT PARAMETER
CI1I780 PORT QUE BLK BASE
CI780 PORT STATUS.

ESP

20-63

ESPA
ESPD

20-64
20-64

EVMQSAV

20-65

FBXERR

20-66

IBESR

20-68
20-70

20-187

IBGPR

20-189
20-189

ICCsS

20-71

ICR

20-72

IPL

20-72

20-8
20-10

INTERNAL

20-10

ACCS

20-13
20-14
20-16
20-17
20-18
20-18
20-19

20-7

ASTLVL

20-7

CRBT

20-21

CSWP
DFI
EHSR

ESP

PRIVELEGED

REGISTERS

20-27
20-28

20-60
20-63

ESPA

20-64

ESPD

20-64

CMISC

20-20

ICCS

20-71

CPC
CRBT
CSES

20-20
20-21
20~-22
20-23

ICR

20-72

CSHCTL
CSLINT

EDMC

IPL

20-72

ISP

20-73

KSP

20-73

MAPEN

20-80

MCCTL

20-80

CSWP

20-24
20~26
20-27

DFI

20-28

MENA

DIAGCS
DMAICA

20-144
20-144
20-145

MERG

20-91

NICR

20-98

POBR

POLR
P1BR

20-98
20-98
20-99

P1LR

20-99

CSM STATUS

DMAIID

DR780

CR READ

20-29

DR780

CR WRITE

MDCTL

20-86

MDECC

20-87

20~-90

DR780

DCRAR

DR780

UTL

20-30
20-31
20-32

DW780 BRRVR4_7

PCBB

20-102

20-33

PMR

DW780 BRSVRO
3

20-104

20-34
20-35
20-37
20-38
20-40

PTE

20-107

RXCS

20~129

DW780 CNFGR
DW780

DCR

DW780

DPRO_15

DW780

FMER

DW780

FAILED

DW780

ADDRESS
MRO_495

DW780
DW780

UACR

USAR

UNIBUS

20-40
20-41
20-42
20-45

20=-2

PAMACC

20-100

PAMLOC

20-101

RXDB

20-130

SBR

20-166

SCBB

20-166

SID

SIRR

20-171
20-173
"

SISR

20-173

VAX 8600/8650

IVASAV
MDECC =~

20-73
20-87

INTERNAL PRIVELEGED REGISTERS
(continued)

SLR

20-174

MEAR

STXCS

20-176

MER

SSP

20-175

STXDB
TBIA

20-177

T"WMSTAT2 =

]

20-178
20-179

———psT
“SFBCNT

2D=30
20-170

20-20
20-22
20-23
20-24

MAINT
MAPEN
MCCTL
MCSRO
MCSR1

20-154
20-80
20-80
20-81
20-82

20~-52

MCSR3 READ

20-178

TBIS
TODR
TXCS

20-182

TXDB

20-184

INTERNAL REGISTERS
CPC
CSES
CSHCTL
CSLINT

_EBCS
:

EDPSR

20-48

20-53

EMD

ISASAV

20-188

ISASAV

20-72

IVASAV

20-73

KSP

20-73

LRHR
LRSR

20-74
20-74

LTHR
20-75
LWCR
20-76
LWMR_HI_ORDER
20-78
LWMR_LO_ORDER
20-77
'
MACHINE CHECK STACK FRAME

CPC

20-20

EBCS =
EBXWD1

20-48 20-51

FBXERR "=

JBESR =~
ISASAV

20-22
20-23
20-24 .

20-51

20283 7
35
K
20-65

20-83

20-84

MENA
MERG

20-96
20-188

EDPSR»
EHMSTS ==
ESASAV
EVMQSAV

MCSR2

20-73
20-89

MSTAT2
VIBASAV
VPCBITS

EBXWD2

20-188

20~-87
20-89

20-93

CSES
CSHCTL
CSLINT.~

VIBASAV

MDECC
"MEAR

20-89

ISP

20-96

.20-101

20-63
20-68

MEDR

MSTAT]1

~20-93

20-85

420-72 "

IVASAV
MEAR

'"H§T§§1*~

20-89

20~

MCSR3 WRITE

20~-63

ESASAV
IBESR

20-89

)

20-177

TBCHK

MEDR

—20=B686

20-6820-72

MDCTL

20-86

MEDR

20-89

20-90
20-91
:

MISCELLANEOUS REGISTERS
EVMQSAV
IBGPR

PSL

SPADR

STATE

MSTAT1

20-65
20-70
20-105
20-174
20-175

20-93

MSTAT2

20-96

NICR

20-98

PCI

REGISTERS

ERCR
ERHR
ERMR
ERSR
ETHR
EWCR

20-76
20-74
20=77
20-74
20-75
20-76

LRCR
LRHR
LRMR

20=76
20~-74
20-77

EWMR

20-77

LRSR
LTHR

20-74
20-75

LWCR

20~76

LWMR_HI_ORDER
LWMR_LO_ORDER
RBSR
B
RRCR

20-78
20-77
20-113
20-76

RRHR

RRMR
RRSR

20=74

20-77
20-74

VAX 8600/8650 REGISTER DESCRIPTION
PCI

REGISTERS

(continued)

20-75
20-76
20-77

RTHR

RWCR
RWMR

POBR

POLR
P1BR
P1LR
PAMACC

PAMLOC

PC
PCBB

PECAS
PERAS
PMR
PSL

20-103

20-104
20-105
20-107

PTE

DMA CA
DMA 1D
ERROR SUMMARY
SBI ERROR

SBI

FAULT STATUS

SBI

MAINT

SBI
SBI

QUADCLR
SILO
SILO COMPARE
TIMEOUT ADR
UNJAM
VECTOR

SBIA SBI

SBIA SBI
SBIA SBI
SBIA SBI
SBIERR
SBISTS
SBR
SCBB

SDCS
SDDDB

SDMS

QADRO
QADRI1

QCSRO
QCSR1

QCSR2
QCSR3

QDATAO
QDATAl

- QUADCLR

RBSR

RBUFO_3
RBUFC
RH780
RH780
RH780
RH780
RH780
RH780
RH780
RH780

20-98
20-98
20-99
20-99
20-100
20-101
20-101
20-102
20-103

SBIA
SBIA
SBIA
SBIA
SBIA
SBIA
SBIA
SBIA

BCR
CAR

CR
CSR
DR
SMR
SR
VAR

RLBA

RLCSR

RLDA GET STATUS
RLDA READ WRITE
RLDA SEEK
RLMPR GET STATUS
RLMPR READ
RLMPR WRITE
RXCS

RXDB

SBIA CR

20-108
20-108
20-109
20-110
20-111
20-112
20-112
20-112
20=159

SFBCNT

20-113
20-113
20-114

STACK FRAME
CPC
CSES
CSHCTL

20-114
20-115
20-115
20-116
20-117
20-118
20-118
20-121

CSLINT

20-121
20-122
20-124
20-125
20-126
20-126
20-128
20-128
20-129
20-130

SID

SILO
SILOCOMF
SIRR

SISR

SLR
SPADR
SSP

EBCS

EBXWD1
EBXWD2
EDPSR

EHMSTS
ESASAV
EVMQSAV
FBXERR

IBESR

ISASAV
IVASAV
MDECC
MEAR
MEDR
MERG
MSTAT1

MSTAT2
PC
PSL

SBIA CSR

20-142
20-143

SBIA REGISTERS
SBIA CONFIG REG
SBIA CONTROL STATUS
SBIA DIAG CONTROL

20-142
20-143
20-144

SFBCNT
VIBASAV
STATE

STXCS

STXDB

20-146

20-147
20-148
20-152
20-154
20-156
20-158
20-159
20-162
20-164
20-164
20-165
20-152
20-154
20-166
20-166
20-167
20-168
20-169
20-170
20-171
20-159
20-162
20-173
20-173
20-174
20-174
20-175

20-20
20-22
20-23
20-24
20~-48
20-51
20-51
20-53
20-55
20-63
20-65
20-66
20-68
20-72
20-73
20-87
20-89
20-89

20-91
20-93
20-96
20-101
20-105
20-170
20-188
20-175
20-176

20-177

VAX 8600/8650 REGISTER DESCRIPTION

TBCHK
TBIA

TBIS
TOADR
TODR

TOY REGISTERS
TRDR
TRSR
TWCR
TWDR

20-177

20-178
20-178
20-164
20-179

20-179
20-180
20-181
20-179

TXDB

20-179
20-180
20-180
20-181
20-179
20-182
20-184

UNJAM

20-164

TRDR
TRSR
TURN

TWCR
TWDR
TXCS

USART REGISTERS
ERCR
ERHR

ERMR
ERSR
ETHR
EWCR
EWMR
LRCR

LRHR

LRMR
LRSR

LTHR
LWCR

LWMR_HI_ORDER
LWMR_LO_ORDER
RBSR
RRCR

RRHR
RRMR
RRSR
RTHR
RWCR
RWMR
USP

20-76
20-74
20-77
20-74
20-75
20-76
20-77
20-76

20-74
20-77
20-74
20-75
20-76
20-78
20-77
20-113
20-76
20-74
20-77
20-74
20-75
20-76
20-77

- 20-187

UTOYO_3

20-187

VECTOR
VIBASAV

20-165
20-188
20-188

VPCBITS

XBUFO0_3
XBUFC

20-189
20-189

VAX 8600/8650

ACLS

ACCELERATOR STATUS REBISTER

PR 28

FBOX REVASION
§
11

[

]

FROX TYPE
l

Note:

The

ACCS

accelarator

type,

the

<31:24>

<23:16>

read/write

revision

status,

and

that

contains

the enable

the

bit.

RESERVED

FBOX REVISION
Number

for

boards

the VAX

that

86xx

replace

FBox,

the

FBox

for

the

‘#hen

there

FTM

and.

FJM

no FBox

present.

<15>

FBOX

ENABLE

Enables

the
FBox

the

execution

FBox.
Writing
and enables it

<14:08>

RESERVED

<07:00>

FBOX TYPE

Specifies

the

type

instructions

a one to this position initializes
to execute VAX instructions.

the

FBox,
this
field
location:
DC).
If
equals 0.

Floating

the

Point

accelerator.

1is
set
to
a
no accelerator

1
is

For

ASTLUL

<31:03>

86xx

ee s

.. ...

AST
LEVEL

3B
- 13847

MBZ

Must

zero.

ASYNCHRONOUS

SYSTEM TRAP

Contains access mode

LEVEL

number

(established by

software)

the
most privileged access mode for which an Asynchronous
System Trap (AST) is pending.
Controls the triggering
of
the AST delivery interrupt during REI instructions.

)t
b O

ASTLVL

<02:00>

VAX

ASYNCHAONOUS SYSTEM TRAP LEVEL REGISTER

IPR: 13 (ESCRATCH LOCATION: EE)

by
ECODE (Escratch
present, this
field

MEANING

AST pending for access
AST pending for access
AST pending for access
AST pending for access
No pending AST
Reserved for Digital

mode
mode
mode
mode

0
1
2
3

(KERNEL)
(EXECUTIVE)
(SUPERVISOR)
(USER)

VAX 8600/8650

BTOY

CI1780 CNFGR

T-11)

(CBUS)

174036

4
35
38

BT0YS

174037

BTOYR
BTOYI
gTovz

174034
174035

BUFFERED TIME OF THE YEAR REGISTERS

CL17.18

BUFFERED TOY DATA

’

MR- 14208

The BTOY registers
<07:00>

consist of

BUFFERED TOY

The

console

DATA
software

counter once every
is

read

loads

the

BTOY

The

<23-16>
<15-08>
<07-00>

=
=
=
=

BTOY

BTOY
BTOY
BTOY

2
1
0

NOTE:

Refer

byte

Description

the

VAX

from the TOY

This maintained value

executing

alignment

Manual,

locations.

registers

10 milliseconds.

EBox microcode when

instruction.
<31-24>

four CBus RAM byte

MFPR

#TODR

is:

8600/8650

Console

EK-KA86C~-TD,

for

Technical

detailed

information on TOY CLOCK operation.

CNFeR

{CI780) CONFIGURATION REGISTER

XXXXX000

PARITY

WRITE

READ

ERROR SEQUENCE DATA

<31:26>

;

MULTIPLE

1§

ATIMEOUT | TIMEOUT | ERROR

FAIL

DEAD

07
0

sUB
READ
| DATA
sTiTure

RANSMI

f% TRANSMIT | TRANSMIT
12

SBI FAULT BITS
These bits are set when the port
detects
the
respective
fault
condition
as
described below.
The fault bits are
read only.

<31>

PARITY

Set
<30>

FAULT

when

WRITE

the

port

SEQUENCE

detects

SBI

Parity

error.

FAULT

Set when the port receives a write mask
command
that
not immediately followed by the expected write data.
<29>

UNEXPECTED

Set when
read
<28>

READ

DATA

the port

FAULT

receives

command.

RESERVED

20-8

read data but did

not

issue

VAX 8600/8650 REGISTER DESCRIPTION

<27>

CI1780

CNFGR

Set when the ID bits transmitted by the port do not

match

MULTIPLE TRANSMIT FAULT

the ID bits received back from the SBI.

<26>

TRANSMIT FAULT

Set if the CI780 was the SBI nexus

that

SBI

the

caused

FAULT line to assert.

<25:24>
<23>

RESERVED
POWER DOWN

PDN is set by the
Set if the port is powering down.
ACLO if the port is in the
SUPPLY
of
assertion
by the microcode
set
uninitialized state, otherwise it is
Cleared: by writing a 1 to it or by
via the PDN bit.
setting the PUP bit.

22>

POWER UP

Cleared by writing

Set by the negation of SUPPLY ACLO.
1 to it or by setting the PDN bit.

21>

RESERVED

<20>

COMMAND TRANSMIT TIMEOUT

ACK

backplane

jumpers.

microseconds.
<19>

does

not

selectable

Set when the port initiates an SBI transfer and

receive

The

error

timeout

confirmation
is

period

<17>

102

within

READ DATE TIMEOUT

Set when the port initiates an SBI read transfer and
data is not returned within 102 microseconds.

<18>

read

)

COMMAND TRANSMIT ERROR

Set when the port receives an error confirmation
response to a port initiated SBI command transmission.

1in

READ DATA SUBSTITUTE

(uncorrectable read
Set when the port receives an RDS
data) confirmation in response to a port initiated SBI
read command.

<16>

CORRECTED READ DATA

Set when the port receives a CRD confirmation in

response

to a port initiated SBI read command.

<15:11>
<10>

RESERVED

TRANSMIT

FAIL

~Set by the microcode
field

when

PFV

through

the

miscellaneous

control

through

the

miscellaneous

control

(power

fail

wvalid) and ASSERT FAIL are

true.

<09>

TRANSMIT DEAD

Set by the microcode

field when PFV and ASSERT DEAD are true.

<08>

POWER FAIL DISABLE

Set when the SBI FAIL and SBI DEAD drivers to the SBI
disabled.

<07:00>

ADAPTOR CODE

These bits contain the CI780 SBI adaptor code, 38(16).

20-9

are

VAX 8600/8650
CI780 MADR
CI780 MDATR

MaGR

{CI780) MAINTENANCE ADDRESS

XXAHA014

]

MAINTENANCE CONTROL STORE CONTROL STORE ADDRESS
¢

]

[

]

]
|

<31:13>

RESERVED

<12:00>

MADR

Contains

the

accessed.

address

read

state,

the

control

written

store

only

location
the

uninitialized

"“5 "
HXXXAD1

{CIT80) MAINTENANCE DATA REGISTER

313929232??5252%2322212@

BIT FIELD

3913??!61514?312!?3{2990

l
3

8!}7%1353@6382@19&

MAINTENANCE CONTROL STORE DATA

‘

]

MR 13555

The CI780 MDATR (maintenance data register
) does
not
exist
as
a
physical register.
A read or write of MDATR will read or
write the
microword in the control store locatio
n specified by the address in
the
MADR
(maintenance address register).
When MADR 12 = 0, MDATR

(31:00)
(15:00)

0's).
<47>

contains microword bits (31:00).
When MADR 12 =
1,
MDATR
contains
microword
bits
(47:32)
(MDATR (31:16) are all

MDATR

read

or written only

the

uninitialized

state.

SYNC
A programmable

bit

that

bit

bits

(45:00)

the

2901

ALU on

the

(data

for the

2901

used

during

port

debugging

indicate
the execution of a specific microword.
The SYNC
bit is not included in the parity check
of the
microword.
The SYNC bit can be written in both
the RAM and PROM areas
of the CS (control store).
The bit is
available
on
the

port

<46>

<45:43>

backplane.

PARITY
The

odd

ALU

FUNCTION

Function
<42:40>

ALU

parity

code

SOURCE

Operand

microword.

<2:0>

for

CODE

source

paths).

<2:0>

code

<39:37>

ALU

<36:33>

ALU A/B ADDRESS LINES <3:0>
The A and B address lines for

DESTINATION CODE
Destination code for

ALU on

the

DP.

<2:0>

the

2901

DP.

20-10

ALU on

the

2901

DP.

scratch pads

the

VAX

<32>

DESCRIPTION
CI1I780 MDATR

TYPE

Selects
<31:24>

8600/8650

the definition of

LITERAL <7:0>
Valid when TYPE

bits

Used

<31:24>

the

shown

number

below.

address.
<31:24>

LINK AND PB (PACKET BUFFER) CONTROL BITS
Valid when TYPE = 1.
The bit fields are defined

<31>

RESERVED

<30>

SELECT
Indicated

<29:28>

PMUX

that

LINK

CONTROL

lines

(<27:24>)

the

packet

buffer

input

registers

the

LINK CONTROL <3:0>
valid when
IB

valid.

SOURCE

Selects

and

output

DP.

Specifies operations on the

*¥<23:21>

are

<1:0>

Selects a byte

<29:24>

the

below.

SELECT

link and PB.

This

field

|is

1in

the

<£2:0>

the

source of BUS

(internal

bus)

data

DP!

*<20:17>

<16:12>

IB DESTINATION <3:0>
Selects the destination

*These

bits bypass

DP.

the

SEQUENCE CONTROL

for

BUS

the microword

<11:00>

selects

the

DP.

directly

<4:0>

Specifies
the
operation
of
selects the branch conditions
and

IB data

definition

the
2911
micro-sequencer,
that alter the microaddress,
bit <11:00>.

MICROADDRESS

This field is the base address that
1is
modified
by
branch bits to form the address of the next microword.

the
It

allows

CS.

the

microcode

jump

any

address

This
field is valid
is not all 1's.

long

the

Sequence

MISCELLANEQOUS

1in

the

Control

field

CONTROL

This field (MISCELLANEOUS CONTROL) allows the microcode to
control
miscellaneous
flags
and
functions in the port.
The field is valid when the Sequence Control field is
all
l1's.
The Miscellaneous Control bits are described below.
<11>

MCLR

This

bit (MAINTENANCE
uninitialized state.

<10>

INTERRUPT
Sets

the

interrupt
<09>

CLEAR)

causes

the

port

enter

the

initiates

REQUEST
INTERRUPT

sequence

REQUEST

the

flag

that

host CPU.

INITIALIZE

Generates

INITIALIZE

signal

20-11

the

link.

VAX

8600/8650

C1780

MDATR

MOATH

{C1780] MAINTENANCE DATA REGISTER BIT FiELD

XAXXXO18

Q0B

MAINTENANCE CONTROL STORE DATA
i

<08>

]

<06>

POWER

the

<04>

When

FAIL VALID (PFV)
the POWER-FAIL VALID

ASRT

FAIL

ASRT

DEAD

bits

Facilitates
<05>

£l

]

CLEAR REGISTER WRITE
Clears

07>

are

flag

bit

the

DP.

set,

the

ASRT

DEAD

and

valid,

processor

initialization

and

booting.

processor

initialization

and

booting.

the

host

ASRT

FAIL
Facilitates

SET A GO

Starts

external

bus

transfer

bus

transfer

with

using

the

parameters.

<03>

SET

B GO

Starts

external

with

host

using

parameters,

02>

POWER

Allows

DOWN

the

microcode

configuration
<01>

INHIBIT

set

the

Power

Down

bit

the

port

RBPE

Set during a DP read of
the
first
byte
from
a
packet
buffer.
The
first
byte
read is always undefined data.
INH RBPE (receive buffer parity error) prevents
a
parity
error from asserting on the undefined data.
<00>

RESERVED

20-12

VAX

8600/8650

PMCSR

{C1780) POAT MAINTEMAMCE CONTROL AND STATUS

XXXXX004 OR XXXXX010
31

CONTRAOL

STORE

LOCAL

STORE
PE

RECHVE

BUEEER

F“??Efifififi

DAT,

ANSMIT

TRANSH

.pg

INPUT

ouTRT eu§Fsa
PE

L PE

ONIN
.

TIALIZD

STATE

OGRAM 7

onG

wAmTENANEE

WRONG

g?fi%fina

| ApDRESS

PARITY | INTRRUPT INTRRUPT iNTBfl

FLAG

ENABLE

SABLE . INTIALIZ

ME.14583

<15>

PARITY

ERROR
bit is set when any of bits <14:08> are set.
cleared when PMCSR (14:08) bits are all cleared,

This

<14>

CONTROL STORE

This

bit

Control
only be
<13>

LOCAL

This

PARITY

set

ERROR

when

a parity error
is
detected
Store in the Packet Buffer (PB).
Note:
set when the microcode is running.

STORE

bit

PARITY

set

the

CSPE

can

ERROR

when

a
parity
error
1is
detected
while
the
Local
Store
(LS)
or
the
Virtual Circuit
Descriptor Table (VCDT).
Note:
A
Local
Store
Parity
Error can only be set by a microcode read of the LS or the
reading

VCDT.

<12>

RECEIVE

not

BUFFER

This bit
reading
<11>

will

set

PARITY

is set when a
a packet

TRANSMIT

DATA

during

unsolicited

INPUT

PARITY

This bit
transfer
<09>

OUTPUT

request.

ERROR

parity

error

detected

while

buffer.

PARITY

ERROR

This bit is set when a parity error
link transmit channel.
<10>

SBI

1is

detected

the

detected on

data

ERROR

is set when a parity error
from the SBI module to the

PARITY

is
DP.

ERROR

This bit is set when a parity error is detected on a
data
transfer from the output buffer to the transceivers within
the SBI module.

<08>

TRANSMIT BUFFER PARITY ERROR

This bit is set
PB is unloading
07>

when a parity error
a transmit buffer.

detected while

the

UNINITIALIZED

This

bit

STATE
set when

state.

Note:

will

respond

not

DEAD,
by

The

writing

(PICR)

microcode

into

a boot

port

microcode

to data
(maintenance

MIN

error).

the

The

is
is

in
not

the
running

uninitialized
and

the

port

packet

the

traffic.
UNINIT is set by
initialize)
or MTE {(maintenance

started

Port

time-out.

when

UNINIT

Initialize

cleared

Control

<06>

PROGRAMMABLE STARTING ADDRESS
When set, the microcode will start at the address
in
the
MADR (maintenance address register), when a "1" is written
into the PICR or a boot time-out occurs.
When
reset
the
microcode starts at location 000.

<05>

RESERVED

20-13

VAX 8600/8650 REGISTER DESCRIPTION
C1780 PMCSR

CI780 PORT CONTROL REGISTERS
[CIT80] PORT MAINTENANCE CONTROL AND STATUS

PMECSR

KOOXH004 OR X000010

//////%/
2

LOCALL RECENE
CONTROL
)
DATA
BUFFER TRANSMI
STORE
STORE

PE | PE

L PE

GE
Mflfi INTRAUPT
WRONG
i!éTRRG?T
PARITY
INTIALIZ
ENABLE DISABLE=
LAG INTRRUPT

;gngam
UNINi St
TRANSMIT
[TALIZD
BUFFER i . STATE
QUTPUT PE
i‘é?,‘%fgs?

WPUT

, PE

WRONG PARITY

<04>

This bit is set when the DP
generator/checker will generate
instead of odd.

This

Note:

bit

parity
path)
(data
and check even parity
1is

parity errors for maintenance purposes.
MAINTENANCE INTERRUPT FLAG

<03>

This bit is set when an

wused

interrupt-~causing

generate

condition

has

timers

are

occurred.

<02>

MAINTENANCE

INTERRUPT

ENABLE

This bit is set by PS DC LO from
Note:
writing MIE with a "1".

the

SBI

module

When set, interrupts are

enabled.

<01>

MAINTENANCE TIMER DISABLE

This bit is set when the boot and maintenance

disabled

cannot cause an interrupt.

and

When reset, the

timers are enabled.

<00>

MAINTENANCE

INITIALIZE

This bit is set when an
that clears all port
uninitialized

{C1780] ONE BIT REGISTERS

initialize signal 1s generated
errors and leaves the port in the

state.

_ s

////////////////////////////:

samm

The port control registers are 32-bit write only registers, and are
written by the port driver. Each port control register controls
one function, and this function is invoked when a "1" is written to
The register offset, name and function, and
register.
the

description follows.

XXXXX908 PORT COMMAND QUEUE 0 CONTROL REGISTER (PCQOCR)
When the port driver inserts an entry in an empty CMDQO,
the port driver writes PCQOCR to initiate port execution
of the command queue. PCQOCR can be written only when the
port is in the enabled or enabled/maintenance state.

XXXXX90C PORT COMMAND QUEUE 1 CONTROL REGISTER (PCQICR)
Same as PCQUCR except refers to CMDQl.

20-14

VAX

8600/8650

CI780
XXXXX910

XXXXX918

DESCRIPTION

PORT COMMAND QUEUE 2 CONTROL REGISTER (PCQ2CR)

Same

XXXXX914

PORT CONTROL REGISTERS

PCQOCR

except

refers

PORT COMMAND QUEUE 3 CONTROL
Same as PCQOCR except refers

PORT

STATUS

RELEASE

CMDQ2.

(PCQ3CR)

CMDQ3.

CONTROL

(PECR)

(PSRCR)

After the port driver has received an interrupt
and
read
the PSR, it returns the PSR to the port by writing PSRCR.
XXXXX91C

PORT

ENABLE

CONTROL

The port driver enables the port by writing PECR.
PECR is
ignored
if
the
port
is
in
the
uninitialized,
uninitialized/maintenance, enabled, or enabled/maintenance
state.

XXXXX920

PORT

The
the

DISABLE

CONTROL

port driver disables
port
is
disabled,

the

(PDCR)

port

by writing
PDCR.
When
port requests an interrupt.
is
in
the
wuninitialized,
disabled,
or

the
ignored if
the
port
uninitialized/maintenance,
PDCR

disabled/maintenance

XXXXX924

PORT

The
When

state.

INITIALIZE CONTROL REGISTER (PICR)
port driver initializes
the
port
by
writing
PICR.
the
1initialization is complete the port requests an

interrupt.
As part of
timer is set to expire
XXXXX928

PORT

DATAGRAM

When

the

FREE

the initialization,
in 100 seconds.

QUEUE

CONTROL

port driver inserts
latter
was
previously

PDFQCR

XXXXX92C

Lo indicate the
availability
of
can
be written only if the port
enabled/maintenance state.

XXXXX930

PORT

MESSAGE

Same

PORT

MAINTENANCE

FREE

QUEUE

PDFQCR except

CONTROL

refers

TIMER

(PDFQCR)

an entry on
the
DFREEQ
and
empty, the port driver writes

PDFQCR

the maintenance

DFREEQ
is

entries.

the

enabled

(PMFQCR)

to MFREEQ.

CONTROL

(PMTCR)

The port driver forces the maintenance timer to reset
expiration time by writing the PMTCR.
If the PMTCR is
written again before the expiration time,
the
port
enter

the

XXXXX934

wuninitialized/maintenance

state
timer expiration interrupt (Port
ignored if the maintenance timer is

maintenance

PMTCR

PORT

MAINTENANCE

(PMTECR)

The

port

driver

interrupt
by
written
only

TIMER

forces

states

and

only

disabled,

while

20-15

the

and

will
request a
status <06>).
not running.

and

CONTROL

maintenance

writing
the
PMTECR.
when
the
port
is

enabled/maintenance,

disabled.

EXPIRATION

timer

This
in

its
not

expiration

disabled/maintenance

maintenance

timer

1is

not

VAX 8600/8650 REGISTER DESCRIPTION
C1780 PORT ERROR STATUS
(Ci780] PORT EARCA STATUS

10 09 08 07 06 05 04 03 02 O 0O

3y 80 29 28 27 %R 25 24 23 22 g 18 18 17 & 15 14 13 12 1

XXXXX93

}

ERROR CODE

" S|

error

The Port Error Status
read only by the
which resulted in a DSE interrupt. The PESRThe1s codes
and a brief
port driver and valid after a DSE interrupt.
description follow.
CODE

DESCRIPTION

1Illegal system virtual address format.

the

virtual

address

Failing Address Register

(PFAR)

<31:30>

Bits

are not equal 10.

contains

The Port

virtual

address.

Non-existent system virtual address.

<29:09>

Bits <31,26,22>

not

equal

1xx,

Bits <31,26,22>

not

equal

1xx,

SPT_LEN.

PFAR contains a virtual address.

Invalid system PTE.

000,

or 00l1.

PFAR contains the virtual address being

mapped.

4.
5.

1Invalid buffer PTE.

000, or 001.

PFAR contains the PTE virtual address.

Non-existent system global virtual address.

GPTX

Non-existent buffer global virtual address.

GPTX

GPT LEN.

GPT_LEN.

PFAR contains the virtual address.

PFAR contains the PTE virtual address.

Invalid system global PTE.

PTE <31,26,22>

not

equal

1Invalid buffer global PTE.

PTE <31,26,22>

not

equal

Invalid system global PTE mapping. The system virtual
address of system global PTE is itself globally

1xx or 000.

mapped.

10.

PFAR contains the PTE virtual address.

PFAR contains the virtual address.

1Invalid buffer global PTE mapping.

address

mapped.

11.

PFAR contains the virtual address.

buffer

global

PTE

1is

The system virtual
itself

PFAR contains PTE virtual address.

globally

Queue interlock rctry failure. Interlock was tested
specific
implementation
an
locked
found
and
consecutive number of times.
head virtual address.

20-16

PFAR contains the

queue

VAX

8600/8650

CI780
CI780

CODE

PORT

DESCRIPTION

PORT ERROR STATUS

FAILING

ADDRESS

(PFAR)

DESCRIPTION

12.

TIllegal
<2:1>

queue
1is

offset

not

alignment.
PFAR contains

address.

13.

TIllegal
be
for

14.

POB

format.
A field of
was found to be other
fields is optional
so

zero
zero

return

this

the

PQB

error.)

the

(The

check
ports

value or under

for protocol
will

byte

specified

this

zero.

(The

check

not

all

ports

will

the

field

offset

was

written

the wrong conditions.

violations

return

offset

PQOB

than

contains

violation.

wrong

all

PFAR

the

bytcs.

with

FLINK <2:1> or
BLINK
the queue head virtual

is optional so
error.) PFAR contains

from device

base

not
the

address.

{CI780) PORT FAILING ADDRESS
XAXXX938
31

FAILING ADDRESS
;n:n;;ll___pxc

a|;1L__Lali;[§

L__1:llgll

After

MSE

DSE

memory

system

(PFAR)

contains

The

address

same

page

interrupt

error

status,

the memory

may

the

and

the

after

the

address
exact

failing

Port

response
Failing

with

Address

buffer
Register

which the
failure
occurred.
failing address, an address in the

address,

or,

the

case

DSE

interrupts, an address in some part of the data structure.
For DSE
interrupts PFAR contains a virtual address or offset, while for
MSE
interrupts
and
buffer
memory
system
errors the PFAR contains a
physical adddress.
Since
after

the port continues command execution
and
packet
processing
buffer
memory
system
errors,
the
PFAR is overwritten if
subsequent errors occur.
For DSE and MSE interrupts
the
PFAR
is
effectively
fixed
since
the
port
enters
the
disabled
or
disabled/maintenance state.
PFASR
MSE

read

interrupt

status.

only
or

the

after

port
a

driver

response

20-17

and

with

readable after a
DSE
or
buffer memory system error
~
‘

VAX 8600/8650 REGISTER DESCRIPTION
CI780 PORT PARAMETER REGISTER (PRR)

C1780 PORT QUEUE BLOCK BASE (PQBBR)
{CiT80] PORT PARAMETER

0o
31

CLUSER

implementaion
contains port
(PPR)
The Port Paramater Register
The value of the PPR is set by the
parameters and the port number.
PPR is
port during initialization and valid after a PIC interrupt.
read only by the port driver.
<31>

CLUSTER SIZE

Cluster size = 0
the

<28:16>

indicates a maximum of

ports

the

Cluster size = 1 indicates a maximum of 224 ports on

CI.

INTERNAL BUFFER LENGTH

internal

The internal buffer length indicates the size of

buffers
availabale
for
message and data transfers.
The
maximum data packet
is
IBUF_LEN
16
bytes.
Max imum
message
or datagram length = IBUF_LEN.
The minimum value
is

<07:00>

592.

PORT NUMBER

{CIT88) PORT QUEUE BLOCK BASE
XHOHKHT04

3 30

09 08 07

1413

PORT QUEUE BLOCK BASE
§

]

)

This register contains the physical address of the base of the Port
The PQBB register is read/wrlte by the port driver
Queue Block.
and

writable

only

when

the

port

disabled/maintenance state.
<31:30>

MBZ

<29:09>

Port Queue Block Base address

<08:00>

MBRZ

20-18

the

disabled

VAX

8600/8650

DESCRIPTION

CI780

PORT

STATUS

{CI780) PORT STATUS
XXXXX800

/////////////,,,
Py
[+

MAINT
//;/ fi TIMER

MEMORY

EYSIEM

/ EXPIRATN

i 4

§&ABLE

ZATION

éasaa

ERROR

eusvg

COMPLETE COMPLETE| £y

This

14558

returns status to the port driver after
an interrupt.
When
an
interrupt is requested by the port, the value
of the Port
Status Register (PSR) is fixed and
is not changed
wuntil
the
port
driver
releases
the
register
by writing the Port Status Release

Control

<31>

(PSRCR).

MAINTENANCE

ERROR
This bit, if set, indicates that the port
implementation
specific
error
(or
condition).
The
source
of
the
error
accurately

determined

maintenance

from

the

registers.

RESERVED

<06>

MAINTENANCE TIMER EXPIRATION
this bit is set, it indicates
timer
has
expired.
The
uninitialized/maintenance state.
When

MEMORY SYSTEM ERROR
When Memory System Error
an

uncorrectable

data

referencing

memory.
disabled/maintenance
Register for further

<04>

DATA STRUCTURE
When
a

this

port

bit

data

information.
queues

<03>

port

set,

the

Port

The

PORT

INITIALIZATION

When

Port

the

encountered

memory

error

while

the

port

(i. €.,

encountered

error

entry,

BDT

POB,

the
Port

See

Falilng

errors

has

queue

is
state.

Address

the queue

page

disabled
or
Error
Status

for

structure

further

leave

the

COMPLETE

Initialization

Complete is
initialization.

internal

set,

the

port

has

The

port

the

state.

PORT

DISABLE COMPLETE
Port Disable Complete is set,
the
disabled or disabled/maintenance state.

port

1is

the

MESSAGE
When

FREE QUEUE EMPTY
set, Message Free Queue

attempted

and
SO

found
the

port

<00>

has

information.

When

<01>

maintenance

ERROR

disabled or disabled/maintenance
<02>

the

non-existent

locked.,

completed

the

specific

port
is
in
the
disabled
or
state.
See the Port Failing Address

structure

and

set,

that

port

The

table).
The
port
disabled/maintenance
Register

is
or

detected
an
hardware
status
may
be
more

implementation

<30:07>

<05>

has

remove

empty.

message

driver

free

gets

Port

has

inserted

processing

queue may

entry

20-19

indicates

from

not

control.

RESPONSE QUEUE AVAILABLE
When set, Reasponse Queue

port

Empty

entry

message

commands

empty

Available
on

that

the

empty

the

free

port
queue

continues

the

time

indicates

that

response

queue.

the

VAX 8600/8650 REGISTER DESCRIPTION
CMISC
CPC

CMIsE

CBUS MISCELLANEOUS CONTROL REGISTER

cLi3

174043 (T-14

{CBUS)

T-11
RESTART

NOTE BIT <7> READ ammn CBUS BT <6> a&aa ONLY BY m

CBus

This register is implemented by two flip-flops outside of the
RAM.

contains

Restart

(TSTR).

<07>

TOY

UPDATE

CS15

TSEL

two

bits:

TOY Update Pending

(UPND)

and T-11

PENDING
H

is
it
while
software
console
the
by
This bit is set
This
register from the TOY register.
BTOY
the
updating
operation
1is
performed
every
10
ms
by
the
consovle
software.

06>

T-11

RESTART

CL15

TSTRT H

Lo
interrupl
(T-11)
c¢onsole
a
Setting this bit forces
This bit
which reboots the console from PROM.
24
vector

may be set by

the MACRO program running

in the CPU.

Under

done by writing the Console Reboot (CRBT)
1is
bit
this
select
also
program may
console
writing MCSR3 <07:05> with a function code
by
of 7 which will also force a T-11 reboot via PROM.

this
VMS,
The
IPR.
indirectly

<05:00>

cre

RESERVED

{ESCRATCH LOC: 24 -

CUARENT PROGRAM COUNTER

T14)

08 07

222 019

PC OF THE INSTRUCTION THE IBUFFER IS CURRENTLY PROCESSING

<31:00>

CURRENT

PROGRAM

process

next.

COUNTER

This register contains
the
that
instruction

)

]

[

the
of
PC)
(Macro
address
the
IBox Address Calculation Unit will

20-20

VAX

8600/8650

REBOOY CODE

REBOOT ADDRESS
i

i
LLLERE

This wr ite
process or

when

sec.

<15:08>

software to reboot the
console
the whole system.
To determine
examines
the
TOY
every
90
been
updated by the console
If TOY hasn'’t changed, the console needs to be rebooted.
Code/Address is supplied by microcode not VMS.
the
1if

REBOQOT

<07:00>

only register is used by
without having to reboot

reboot
to
see

software.
The Reboot

x5+

conscle, macrocode
the
content
has

CODE

hex

REBOOT ADDRESS

CBus
to

to console

address

(33

occur.

20-21

hex)

used

force

the

reboot

vAX 8600/8650 REGISTER DESCRIPTION
CSES

CONSOLE CONTROL STORE ERRORE STATUS WORD

CSES

{ESCRATCH LOCG: 2D - T1D}

‘ CONBOLE

£CC CORR

FAILED
15

128

10, 03

SYNDROME USED Y0 CORRECT CS OR DRAM BIT

o7,

OFCSCS OR DRDRAM PARITY E ERROR
ADDRESS OF

The contents of this register are generated by the console during
sends
Control Store and Dispatch RAM ECC correction. The conscle
process.
this register to the CPU as part of the ECC correction
<31>

CORRECTION FAILURE

indicates that the console was unable to correct the
Control Store or Dispatch RAM identified in the CS/DRAM ID
field

<02:00>.

<30:29>

RESERVED

<28:16>

Address the console used when correcting the Control Store

CONTROL STORE ADDRESS
or DRAM Parity Error.

<15:08>

CONTROL STORE SYNDROME

This is the syndrome the console used to correct

the

bit

in error.

<07:03>

RESERVED

<02:00>

CONTROL STORE/DRAM IDENTIFICATION CODE
This is the code passed to the conscole from the EBox
determine what Control Store to apply correction to.

) O U

b L

DD e

CODE

MEANING
No

Error

EBox Control Store Parity Error
IBox Control Store Parity Error
IBox DRAM Parity Error
FBox DRAM Parity Error

FBox Adder Module Control Store Parity Error
FBox Multiplier Module Control Store Parity Error
MBox Control Store Errors (Data, Address, or
Micro-stack)

20-22

VAX

8600/8650

LSHCTL

CACHE CONTROL

(ESCRATCH
LOC: 29 = T19)
30

] FORCE

CACHE

HIT

ENABLE | ENABLE
CACHE 1 | CACHEQ

This

is made

<31:08>
<07:00>

RESERVED
SOURCE:
MAPP

<07:04>

RESERVED

<03>

FORCE

MBOX

(REG)

REG

MBOX

(byte

(ADDR CONTROL

CACHE MISS

REG4

FORCE

CACHE

When

set,

forces

MISS

(MAPP)

a cache miss (overrides
CACHE
1
and CACHE 0 ENABLE).
This bit is used for forcing
refill during diagnostics.

FORCE

REG4
This

CACHE

ENABLE
CO

—

ot et L3 (T et et

00 (0
et e
Pt o

The

three

following

Cache

bits

Code

000

CACHE

WONG

0 determines Hit or Miss
Cache 1 determines Hit or Miss
Both Caches detcrmine Hit or Miss
Cache Miss
Force Hit in Cache 0
Force Hit in Cache 1
Illegal, gives tag parity error
with Written Bit = 1

<02:00>

Cache

reflect

and

Disabled

the

following:

Disabled

001

Cache

010

Cache

Code

011

Normal

Code
Code

100
101

- Cache 0 and 1 Disabled
- Used to force a sweep of Cache 0
Bit
is
set,
Also
used
for

Code

110

Disabled

Running

Used

Bit

a
set.

‘§Ol>

ENABLE CACHE

REG4
When

CACH
set,

ENABLE
When

set
written).

hit

force

given

Also

Cache 1
wused
for

hit

given

Written
diagnostic
cache.

1 ON (MAPP)
enables Cache

CACHE

CACH

sweep

This is an illegal code that covers the
case
of
a hit in both caches.
A tag parity error
with W=1 is also
forced
if,
during
normal
operation,
both caches give indications of a
hit.
This is considered an MBOX FATAL ERROR.

written).
REG4

Code.

force

purposes

and

Miss

Code

111

ENABLE

table:

Cache

purposes

<00>

the

Code

cache

Function
T

et O et O

with

shown

C(C1

Hit

(MAPP)
in conjunction
as

et 0%

Force

ENABLE
a

HIT

FORCE CYC
bit works

Pk 70

<02>

13824

0).

(allows

Cache

read

and

read

and

0 ON (MAPP)
enables Cache

(allows

20-23

Cache

VAX 8600/8650
CSLINT

CONSOLE AND INTERAUPT STATUS WORD

CSLNY
{ESCRATCH LOC 1€ - T00)
el

CONSOLE

cpu

KABG0O INTERRUPTS

MBOX

INTERVAL

CONSOLE

| PENDING | FAILURE | ERROR |TIMER _ RLO>
15

10A WITH HIGHEST

£BUS DATA

{NTERUFT REQUEST

SOURCE
0=EXT

1= INT

10=RDCS
{I=RDLSL
1=WRCSLE

A4,

RECEIVE TRANSMIT
CBUS
grock

CBUS RIW

EBOX IPRSTATUS

A3,

A1,

CBUS ADDRESS

;

CSLINT (Console and Interrupt Register)

System

reflect the
Bits <31:16>
register.
This is a two part
Interrupt Status and bits <15:00> reflect the CBus Status.
<31:30>

RESERVED

<29:23>

CPII

INTERRUPT

Setting

bit

this

field

will

result

CPU

interrupt.

<29>

CONSOLE HALT PENDING
EBE3

CSL

1Indicates that the console wants
Posted by the console.
to interrupt the EBox and force it to execute a Console
The Ebox micro code will be forced to the CSM wait
Halt.
loop.

<28>

CPU POWER FAIL

EBC2 CPU PF INTR LVL3

Posted

notified

the

console.

Indicates

about

console

the

that

EMM

has

an impending power failure

VMS has approximately 300 ms to shut down

orderly

manner.

27>

ERROR

MBOX

EBC2 MBOX INTR LVL3

Indicates that the MBox detected an
Posted by the MBox.
error of any type (excluding TB parity errors). The
(Same as
interrupt is handled by the EBox at IRD time.
<14>).

EBCS

<26>

INTERVAL TIMER

EBE9 TIME INTR LVL3

Posted by the EBox.

Indicates

<25>

CONSOLE RLO2
EBC2 RL INTR LVL3

Posted by the console.

interrupt

the

that

the

1Indicates that the

Interval

Count

console

wants

EBox to transfer a byte to or from the

RLO2.

assembles
During an RLO2 read (SNAP files, etc.), the Tll
512 bytes and then transfers them to the EBox a byte at a
time via this

interrupt mechanism.

During an RLO2 write, the T1l1l interrupts the EBox for
It the
byte of data until it has assembled 512 bytes.
transfers the data to the RLO2.

20-24

VAX

8600/8650

DESCRIPTION

CSLINT

<24>

CONSOLE

RECEIVE

EBC2 TRX INTR LVL3
Posted by the console.
acknowledged

<23>

CONSOLE

- EBC2
to
<22:21>

last

1Indicates
CPU

the

console

has

INTR LVL3

the

transfer

IOA WITH

console.

byte

HIGHEST

1Indicates

INTERRUPT

INTERRUPT SOURCE
INT INTR
Set by hardware.

that

the

information
to the

EBC1 EXT INTR SRC 1:0
This field indicates the
highest IPR.
<20>

that

transmission.

TRANSMIT

TTX

Posted

the

console

CPU

via

the

wants
CBus.

REQUEST

I/0 Adapter

(SBIA)

that

has

the

source

(0=EXT/1=INT)

EBC3

<19:16>

the

pending

that

the

EBOX

IPR STATUS

EBC3
This

ACTIVE

When

interrupt

source

the

set,
is

indicates

internal.

pending

that
When

interrupt

the
clear,

indicates

external.

<03:00>

IPR 3:0
field represents the least significant four
bits
of
the
highest
active
hardware
(internal
or
external)
interrupt request during the previous machine cycle.
When
this field is zero, there was no hardware interrupt.

<15:08>

CBUS

DATA

EBE2

CBUS

Although

<D7:D0>

from
the
to the CPU
07>

REG

this

CBUS

CLOCK

EBEZ2

CBUS

D7:D0

console,
are

all

latched

used primarily to
receive
data
data transfers between the console

this

CLOCK

This bit represents the state of the CBus Clock Line.
The
CBus
Clock
must be asserted by writing a one to this bit
and negated (in a subsequent microinstruction) by
writing
a
zero
to
this
bit in order to complete a CBus read or
write operation.
<06>

CBUS R/W (0=RD CSL/1=WR CSL)
EBE2 CBUS WRITE
This bit determines whether a CPU read or write
is
to be performed over the CBus.
The EBox is
drive

the

CBus

data

lines

console
1is enabled
bit is reset.
<05:00>

CBUS

EBE2
The

ADDRESS

to drive

the

this

bit

CBus

data

operation
enabled to
The
lines when this
1is

set.

<A5:A0>

CBUS A5:A0
of the

address

loaded

when

into

this

console

location

20-25

read

written

VAX 8600/8650 REGISTER DESCRIPTION
CSM.STATUS

ESCRATCH LOC.000

CSM STATUS WORD

CSM.STATUS

DOUBLE ERROR STATUS

This is the
<31:16>

NON-0 = VAX ISP RUNNING

word

status

(CSM).

used

located

CSM ENTRY CODE
i

control

the

has

in ESC CO.

occurred.

EXECUTION STATUS

If this field is equal to zero it indicates
is executing

microcode

CSM

that

in the EBox.

ENTRY CODE

was

started.

Code

Reason

CSM

why

not executing.

Interrupt Stack not Valid (Software Error).
A non-EBox double error was detected.
in Kernel Mode.
Halt Instruction was decoded
3 (Software Error).
SCB Vector Code <1:0>
2 (no WCS Microcode).
SCB Vector Code <1:0>

0A
OB
10

CHMx Instruction decoded and Interrupt Stack = 1.
CHMx Instruction decoded and Vector <1:0> # 0.

Console

wou

04
05
06
07
08

If this field is not equal to zero
ISP
VAX
the
that
indicates
it

This field contains a code that indicates reason

Pending Error on Halt.

Micro-break

was encounterd

which

caused

console to start CSM at CSM.ENTRY.MICRO:.

Halt Pending

was set

the

which caused

CSM to

start running on AFork at A.CSM.ENTRY.MICRO:.
and the Console started
The CPU was powered up
at

CSM

CSM.ENTRY.PO:.

by
code is used
up sequence this
During the power
interface
FIND RPB procedures to
the FIND 64KB and

with CSM.ERROR:

see this code.

wrong

the

routine. The

Console should

If it does then there something

CPU.

20-26

]

Support

Console

00 ¢

Iis
field
this
If
This field is normally equal to zero.
indicates that a non=EBox double error
it
then
non-zero

executing in the EBox.
then
(i.e., non-zero)

<07:00>

DOUBLE ERROR STATUS

condition

<15:08>

(CSM Status Register)

CSM.STATUS

Microcode

CSM EXECUTION STATUS

0 = CSM RUNNING
i

{IF NON-TERQ = INDICATES THAT A NON-[DBOX DOUBLE CAROR WAG DETECTED)

never

very

)

VAX

8600/8650

DESCRIPTION

CSWP
Lswp

PR 42
31

CACHE SWEEP

:
13

i
12

// 7

i 7 Z ’2' i

// ,f’fx%%%%%

]

o11

CACHE CONTROL

7 gfiufigfi VALIDATE CACHE1 CACHF0 l

CACHE

MEMORY = ENABLE , ENABLE
MR

<31:04>

RESERVED

<03:00>

CACHE

<03>

CONTROL

INVALIDATE

When

set,

clears

written

and

update

memory.
Both
caches
regardless of whether they were

cache

access

halves

valid

bits

and

Cache

after

CACHE

does

always
invalidated,
previously
enabled.
The

both

ENABLE

Both

Cache

are off
active Cache

off

active

Cache

off

and

VALIDATE MEMORY
When
set,
copies
according
is

ENA

and

cache

operation:

mode

not

are

mode is then set to select one
expressed by CO ENA and Cl1 ENA.

State

ENABLE

<02>

33933

then

Cl1

neither

CSWP
will
<01:00>.

the
set

ENA

Caches

are

cache

written

enable

select

the

table

cache

Cache

active

1locations
bits.,

halves

<01>

CACHE

ENABLE

CACHE

ENABLE

20-27

to
cache

memory,
access

expressed

above.

INV or VAL are set, the only
be
to
enable
the
cache

<00>

The
as

effect of
according

an
MTPR
to bits

VAX

8600/8650

DFI
DIAGNOSTIC FAULT INSERTIGH REGISTER

f/fi?f
/’

13 -

<31>

ks 1

/
?

1716

EVENT COUNTER
i

]

2{;

ARMED

Wwhen set, fault insertion is armed and controlled
EVENT SELECT CODE <02:00>

These bits form the
increment enable.

count

modes

When enabled,

for

the

hardware associated with this register.

<30:28>

EVEN

the

COUNTER

the counter increments at

CLK TiC.

The following Count Modes exist:
ACTION
o

0
1
2
3
4

NEVER COUNT
ALWAYS COUNT
-ESTALL
-ISTALL
EBOX UMARK #

5
6

IBOX UMARK

EBOX UMARK * -ESTALL + IBOX UMARK * -ISTALL
IRD * -STALL

27>

OVERRIDE MICRO CODE MARK

<26:16>

RESERVED

<15>

When set, causes PTE in Rl to be loaded into TB location
corresponding to virtual address in RO, All other bits

the
of
when set, overrides microcode mark as one
conditions needed to insert the fault. In other words,
fault insertion occurs when the EVENT COUNTER overflows.

TP LOAD PTE

are ignored.

recognized

|is
It
MTPR DFI microcode (branch condition), and

This bit does not exist in hardware.

may be used by macrocode to generate TB parity errors.
<14:11>
<10:00>

RESERVED

EVENT COUNTER

The event counter is capable of counting 1 to 2047 cycles,

EBox and IBox microcode mark bits with and without stalls,

unstalled IRD cycles, unstalled IBox or EBox cycles, or an
external event until EVENT COUNTER OVERFLOW occurs.

20-28

VAX 8600/8650 REGISTER DESCRIPTION
DR780 CONTROL REGISTER (READ)

gg?sigfifggé

OR780 CONTROL REGISTER (READ)

s w2

<31>

PARITY

FAULT

<30>

WRITE

SEQUENCE

<29>

UNEXPECTED

o w

<28>

RESERVED
MULTIPLE

<26>

TRANSMITTER

<25>

RESERVED

<24>

EXTERNAL ABORT

<23>

POWER

DOWN

22>

POWER

DATA

TRANSMITTER
DURING

| <21>

RESERVED

| 20>

INTERRUPT ENABLE

FAULT

READ

27>

FAULT

<19>

PACKET

<18>

ABORT

INTERRUPT

17>

HALT

<16>

CORRECTED READ DATA

<15>

READ DATA SUBSTITUTE

<14>

COMMAND/ADDRESS TIME OUT IDI1

<13>

READ DATA EXPECTED TIME OUT ID1

12>

RECEIVED ERROR CONFIRMATION

11>

DATA

<10>

COMMAND/ADDRESS TIME OUT ID2

<09>

READ DATA EXPECTED TIME OUT

ID2

<08>

RECEIVED ERROR CONFIRMATION

ID2

' <07:00>

INTERCONNECT

ID1

STALL

ADAPTER TYPE CODE

Adapter type code = 30(16)

20~-29

o«

VAX 8600/8650 REGISTER DESCRIPTION
DR780 CONTROL REGISTER (WRITE)
BCR (WRITE)

DA780 CONTROL REGISTER (WRITE]

OFFSET. 000

RESERVED

CONTROL FIELD B

ot ok pod et 3

12
D

D b

D LD KD

No operation
Clear corrected read data (DCR read
Set external abort (DCR read <24>)

Clear packet

Set out of sequence test
Clear out of sequence test
No operation

RESERVED

<19:08}

CONTROL

FIELD A

D bt e €D

OO
O

bt
b D

el o I o 3 o B o |
|l ol

interrupt

(DCR read

No operation
Clecar power up (DCR read <22>)
Clear power down (DCR read <23>)
No operation
Clear abort interrupt and read data
substitute’ (DCR read <18, 16>)
Clear interrupt enable
Set interrupt enable
Clear halt

RESERVED

20-30

<16>)

<19>)

Reset

<11>

<07:00>

09
CONTROL FIELD A

D e

- <14:12>

<31:15>

Pt K

iie

D et et D LD

CONTROL FIELD B

ot o £

%
Z

VAX

8600/8650
DR780

ADDRESS

BCRAR

ADDRESS
SPACE FORDR780

(DCRAR)

BR780 SB1 ADDRESS REGISTER

OFFSET: 014

DESCRIPTION

0 = $BI0

1=SBt

’

TRANSFER
REQUEST

|NUMBEH
00

<31:30>
<29:17>

RESERVED
DR780

ADDRESS

These

bits

SPACE

are used as the ADDRESS SPACE available to
the
The addresses for the DR780 fall into the adapter
space as do all hardware addresses.
Bit 29 is set
a
1 and <28:26> and <24:17> are all 0's.
Bit 25 is 0
SBIA 0 and 1 for SBIA 1.

DR780.
address
to
for

<16:13>

TRANSFER REQUEST IDENTIFIER
number for the transfer

The

DR780
any

<12:11>

<10:09>

1is

from

The

request

number

through

bits

used

set

this

when

field

the

can

15.

MBZ

Must

PAGE

SELECT

These

bits

zero.

accessed.,
selection

<08:00>

installed.

numbers

inform

This

the

DSC

which

bits,

20-31

page

contains

the

DR780

table

to be

page

VAX 8600/8650
DR780 UTL

DESCRIPTION

]

DR780 UTILITY REGISTER

OFFSET: 004

GENERAL

PARITY ERRORS

ENABLE

C%NTRGL
iC

0i PE

ABORT

FORCE

GENERAL

PARITY

]

é2%%%%%%%%é%%§%%§§§%%%%fi%%iii%gifiz{éi%
A

DATA RATE

[

<30>

DEVICE

PARITY

INTERCONNECT

Indicates
error
<28>

that
the

WRITABLE

\>
[

on
the

the
SBI

Module.

INTERCONNECT

CONTROL

ERROR

Indicates that the DSM detected a parity error
This bit is generated on the Silo Module.
<29>

;

PRI

Indicates that a parity error was detected either
CI,
the DI, or the WCS.
This bit is generated on
Interface

i
<31>

the

PARITY

This

CONTROL

STORE

bit

the

DI.

ERROR

Microprocessor

CI.

Module

detected

generated

PARITY

the

parity

DUP.

ERROR

Indicates that the DUP detected a Writable
Control
Store
RAM
Parity
Error.
This
bit
1s
generated
on
the
Microprocessor Module.
<27>

ENABLE DEVICE INTERCONNECT PARITY ERROR ABORT
When this bit is set and a DI parity error is detected
it
will cause the DR780 to abort the data transfer and notify
the

<26>

processor.

FORCE

This

DEVICE

error

FORCE

COMPUTER

WRITABLE
set
in

When

to
set

test

the
DI
bit will

this

parity
force a

DI.

INTERCONNECT

PARITY

fedture used

the
DUP.
on the CI.

When

ERROR

‘

to test

set

CONTROL STORE VALID
this
bit
allows
the

operate.,

<07:00>

DSM.

the

ERROR

used

the

this

bit

CI
will

parity
force

RESERVED

When

<10:08>

PARITY

feature

is a diagnostic

circuits
on
parity error

<11>

the

parity

This

<24:12>

INTERCONNECT

diagnostic

circuits

<25>

When cleared

the

DR780

microprocessor

DR780

aborts

the data

transfer

progress.

RESERVED
DATA

RATE

Specifies

the

2's

complement

megabytes/second.

The

data

the

data

transfer

rate

is calculated using the following formula:
Where 256 is the value of the data rate in

DR
=
bytes.

40/256.

NOTE
The maximum data
rate

less

loaded

and

than

the

rate

five

prevents

field

value.

20-32

will

rate

(in MB/sec.)

;j
(eight MB/sec).
this

field

retain

1its

from

Any
being

VAX

8600/8650 REGISTER DESCRIPTION
DW780 BRRVR 4 - 7

SRRVE 4-7

OW780 BR RECEIVE VECTOR REGISTERS 4-7

OFFSET. 030-03C

UMDT U

UNIBUS DEVICE INTERRUPT VECTOR
i

BR RECEIVE VECTOR REGISTERS

Note:

The UBA contains

BRRVR 4.

]

1
§

4-7

four BRRVR’s:

BRRVR 7,

BRRVR 6,

Each BRRVR corresponds to a Unibus

BRRVR 5,

interrupt bus

request level:
7, 6, 5, or 4.
Each BRRVR is a read
only
register
and
will
<contain
the
interrupt vector of the
Unibus device interrupting at the corresponding BR
level.
Each
BRRVR
1is
read by the software as a part of the UBA
interrupt service routine.
Note that
the
UBA
interrupt

service

CPU will
UBA
or

routine

is the routine to which the VAX 8600/8650

transfer control once it has determined that
the
the Unibus has issued an interrupt request to the

SBI.

<31>

ADAPTOR INTERRUPT REQUEST INDICATOR
0 = No UBA interrupt pending
1 = UBA interrupt pending

<30:16>

RESERVED

<15:00>

DEVICE

INTERRUPT

VECTOR

FIELD

These bits contain the device interrupt vector
the UBA during the Unibus

interrupt transaction.

20-33

loaded

VAX 8600/8650 REGISTER DESCRIPTION
DW780 BRSVR 0-3
BASYR 03

DWT80 BUFFER SELECTION VERIFICATION REGISTERS 0-3

OFFSET: 020-02C

UMDY, U

TEST DATA
3

<15:00>

‘g

FAILED UNIBUS ADDRESS BITS <17:02>
BUFFER SELECTION VERIFICATION REGISTERS 0-3
Note:
These
four
read/write
do-nothing

provided

accessing and

Four

give

the
diagnostic
testing the integrity

1locations

registers
are
software
a
means of
of the data path
RAM.

in the data path RAM have been assigned

these registers.
Writing
effect on the behavior of

and reading
the UBA.

20-34

the BRSVR's

has

to
no

VAX 8600/8650 REGISTER DESCRIPTION
DW780

CNFGR

OW780 CONFIGURATION BEGISTER

CHraR

USJF

OFFSET. 000
31

SBiPE

UNEXPCTD
WRITE
RD DATA
SEQUENCE,

S8l FAULTS

<31:27>

SBI

INTERLK

SEQ

XMITTER

MULTIPLE DURING

UNIBUS

POWER

INIT

DOWN

XMITTER | FAULT _ F

(

FAULTS

These bits are set when the

conditions

the

SBI.

UBA

Note:

detects

specific

fault

These bits cannot be set

once FAULT has been asserted.
The negation of
FAULT and
the
clearing of the fault conditions clear the bits.
The
setting of any bits <31:27> will cause the UBA
to
assert
the
FAULT
signal
for
one
c¢ycle
on the SBI during the
confirmation time for the assocaited transfer.
<31>

PARITY

FAULT

This bit
<30>

WRITE

set when

SEQUENCE

the UBA detects

an SBI

parity error.

FAULT

This bit is set when the UBA receives a
write
interlock
write
masked
command and does not
expected

<29>

write

UNEXPECTED

data

READ DATA

INTERLOCK

SEQUENCE

following

or
the

cycle.

FAULT

This bit is set when
read command was not
<28>

the

masked
receive

the UBA
issued.

receives

read

FAULT

data

when

This bit is set when an interlock write masked command
to
the
Unibus address space is received by the UBA without a
previous interlock read mask command.
<27>

MULTIPLE

TRANSMITTER

FAULT

This bit is set when the UBA is transmitting
on
the
SBI
and the ID bits received do not match the ID transmitted.
<26>

TRANSMIT

FAULT

This bit is set if

the

UBA

was

transmitting

during

detected
fault
condition.
Note:
When
the
software
subsequently reads the configuration and status
registers
of
each
of the nexus on the SBI in order to identify the
source of the fault, the UBA will be
identified
as
that
source

bit

set.

<25:24>

RESERVED

<23>

ADAPTOR POWER DOWN
Set when the UBA power supply asserts AC LO.
writing a 1 to this bit or when Adaptor Power

<22>

ADAPTOR POWER

Set

negation

LO.

Cleared

bit or when Adaptor Power Down
<21:19>

Cleared
by
Up is set.

RESERVED

20-35

by writing

set.

this

VAX 8600/8650
DW780

CNFGR

CHFER

BW7B0 CONFIGURATION REBISTER

OFFSET: 000

USJF

SBIFAULTS
8BiPE

WRITE

UNEXPCTD

,SEQUENCE ,RDDATA

26
£

INTERLK

, SEDQ

MITTI

MULTIPLE DURING
EMITTER | FAULY

_u
i;/y;“f/?/ :

{éfg’ég/%

UNIBUS

ADAPTOR POWER
NIT
DOWN

ASSERTED ,

gfig gg;ma&
DOWN

UNIBUS ADAPTOR CODE

<18>

UNIBUS

This

INITIALIZATION ASSERTED

bit

cleared

(UBIC)
<17>

set

the

setting

the

Unibus

(UBINIT)

assertion of

or by writing a

Unibus

1Init.

Initialization

1is

Complete

Bit

to this bit.

UNIBUS
Set

POWER DOWN (UBPDN)
when Unibus AC LO is asserted.

Note:
This
indicates
that
the Unibus has initiated a power down sequence.
The
setting of the UBIC bit or writing a 1 to
this
bit
will
clear UBPDN.

<16>

UNIBUS

INITIALIZATION

COMPLETE

(UBIC)

This bit is set by a successful completion of a
power
up
sequence
on
the
Unibus.
Note:
It is the last of the
status bits that can be set during
a
UBA
initialization
sequence,

and

the

and

Unibus

are

or Unibus Init,
clears UBIC.
<07:00>

can

interpreted

ready.
The
the writing

to mean

that

ADAPTOR CODE

These

bits

define

the

ADAPTOR

Bit Number
Value

7
0

6
0

code

assigned

the UBA.

CODE

BIT

ASSIGNMENT

UBA Number

20-36

the

UBA

assertion of Unibus
AC
LO
of a 1 to this bit location

VAX 8600/8650 REGISTER DESCRIPTION
DW780

BeR
OFFSET: 00C

DCR

OW780 DIAGHOSTIC CONTROL REBISTER
USIF

28
ccap

| DEFEAT
x

POWER

T ADAPTOR

JMICRO

PARITY

INTERUPT

spane | DiSABLE | VEFEAT | para

INIT

:4,

UNIBUS

POWER x
05

ERTED

POWER

INIT

DGW&

COMPLETE

UNIBUS ADAPTOR CODE
o

<31>

]

SPARE

This read/write bit has no effect on
Note:
the
<30>

SBI

DEAD,

UBA will

DISABLE

Adaptor

clear

this

INIT,

and

any

UBA

operation.

a power up sequence on

bit.

INTERRUPT

When set, this bit will prevent the UBA
from
recognizing
interrupts
on
the
Unibus.
It is useful in testing the
response of the
UBA
to
the
passive
release
condition
during
a Unibus interrupt transaction.
SBI DEAD, Adaptor
INIT, and the power up sequence on the UBA will clear this
bit.

<29>

£28>

DEFEAT MAP

PARITY

When set, this read/write bit will inhibit the parity bits
of the map registers from entering the map register parity
checkers.
Note:
The
map
register
parity
generator/checkers
dgenerate and check parity on eight bit
quantities.
Each parity field (eight data
bits
and
one
parity

hit)

field

the

implemented

that

the

total

number

1's

odd.

DEFEAT DATA PATH

PARITY

When set, the DDPP bit will inhibit the parity bits of the
data
path
RAM
from entering the parity checkers.
Note:
The DDPP bit functions in the same manner as the DMP
Dbit.
The data path parity generator/checkers generate and check
parity on eight bit data units.
Each parity field
(eight
data
bits
and one parity bit) is implemented so that the
total number of
1's
in
the
field
is
odd.
When
the
integrity of the parity generator/checkers is to be tested
through use of the DDPP bit, the total number of 1's in at
least
one
of
the
bytes of data must be even.
With the
parity bit disabled by the DDPP bit, a
data
path
parity
failure
will result during a Unibus to BDP read, a BDP to
SBI write, or a purge.
SBI DEAD, Adaptor
INIT,
and
tLhe
power up sequence on the UBA will clear the DDPP bit.
27>

MICROSEQUENCER OK

The MIC OK bit is a read only bit which indicates that the
UBA
microsequencer
is
in
the
idle
state.
The
microsequencer will enter the
completed
the
initialization
completed a UBA function.

idle
state
after
sequence
or
once

The MIC OK bit can be used by the diagnostic to

it
has
it has

determine

whether
or
not
the
microsequencer
has
completed
a
successful power up sequence
and whether
or
not
it
is
caught
up
1in
any
loops.
Note that SBI DEAD, UBA power
supply DC LO, and Adaptor INIT
force
the
microsequencer
into
the
initialization
routine.
Once the routine has

been completed and
state, MIC OK will

the microsequencer has entered
be true (1).

<26:24>

RESERVED

<23:00>

These bits are the same
configuration

20-37

bits

<23:00>

the

idle

DW780

VAX 8600/8650 REGISTER DESCRIPTION
DW780

DPR

DW780 DATA PATH REBISTERS 0-15

PR O-16

UMor

OFFSET 040-07C

EMPTY

BUFFER

DATA

TRANSFER ATH
ERROR
FUNCTION

BUFFER STATE BITS

BUFFER

BUFFERED UNIBUS ADDRESS

BUFFER NOT

1
0

EMPTY

Note:
Each DPR contains
buffer not empty.
o

a data

path

status

bit

called

Buffer

not empty
Buffer empty

The BNE bit reflects the state of the associated BDP.
If
this
bit is
set
(1),
the BDP contains valid data.
If
clear, then the BDP does not contain valid data.
The
UBA
uses
the
bit
to
determine
the
proper
action for DMA
transfers via the BDP.
If
bit
31
1is
set
as
a
DATI
transfer
begins,
the data in the BDP will be asserted on
the Unibus.
1If bit 31 is clear on a DATI,
the
UBA
will
initiate a read transfer to SBI memory, gate the addressed
data to the Unibus, and then load the read data
into
the
BDP, thereby setting bit 31.
For

bit

DMA write transfer via the associated BDP,
1is
set each time Unibus data is loaded into

The bit

then cleared when the contents of

transferred

the

BNE
BDP.

BDP

are

SBI memory.

The software will write a 1 to the BNE bit to
initiate
a
‘purge
operation at the completion of a DMA transfer using
the corresponding buffered data path.
The
UBA
executes
purge operations as follows:
1.
WRITE TRANSFERS TO MEMORY
This bit is set
if
any
bytes
of
data
remain
in
the
corresponding
BDP.
The bit is cleared if no data remains
to be transferred.
Note:
The UBA will transfer this data
to

the

SBI

location

initialize

the BDP and

operation

will

do-nothing

function).

addressed.

clear

treated

the
as

The

BNE
a

UBA

bit.

no-op

(it

will

then

The

purge

2.
READ TRANSFERS TO MEMORY
Note:
If any bytes of data remain in
the
BDP;
will initialize the BDP by clearing the BNE bit.

In addition,
purge

the

following

considerations

apply

legal

the

UBA

the

operation:

For purge operations in which data
is
transferred
to
memory,
the
SBI
transfer
takes about 2 us.
The UBA
will not respond to data path register
read
transfers
during
this
period
(busy
confirmation),
thereby
preventing a race condition when testing for BNE bit.

A purge operation to data path register 0
path) is treated
by the UBA as a no-op.

20-38

(direct

data

VAX 8600/8650

<30>

BUFFER

TRANSFER

DPR

ERROR

This is a
read-write-one-to-clear
bit.
The
UBA
the
BTE bit if a failure occurs during a BDP to SBI
or a purge, or for a buffer parity failure during
a
Unibus
to
BDP
read
access.
If
bit
30
1is
set, any
additional DMA transfers via the BDP will be aborted until
the bit is cleared by the software.
Note that if a parity

eM@"”

Note:
sets
write

error on the Unibus
signal
PB
will be
opportunity

does

not

transfer

abort
on

the

clear
the
writing a 1
<29>

DATA

PATH

Note:

The

bit

transfer.

the

purge

software

the

device

UBA will

abort

the

operation

does

not

clears

this

bit

location.

DMA write

a
DMA

read

only bit.
transter using

This bit
this data

indicates
path.

the

read

BUFFER

STATE
Note:
These eight read only bits indicate
the
state
of
each
of
the
eight
byte
buffers
of the associated BDP
during a DMA write transfer.
They
are
included
in
the
data
path register for diagnostic purposes only.
The UBA
generates the SBI mask bits from the BS bits during a
BDP
to
SBI
write
transfer or purge operation.
The bits are
set as each byte is written from the Unibus.
The bits are
cleared during the SBI write operation.

0
1

<15:00>

DMA

<23:16>

the

DPF

DMA

transfer,

access.

bit.

the

own

FUNCTION

The

function

its

BTE

occurs during a DMA read,
the
Unibus
asserted, giving the Unibus device the

abort

EmplLy

Full

BUFFERED UNIBUS

Note:

This

the

ADDRESS

portion

Unibus

each

DPR

<15:00>

Note:

This

address

will

Upper

the

bits

Unibus

mapped

contains

upper

asserted

<17:00>

address

during

20-39

<K17:02>,

the

bits

a
Unibus to BDP write transfer using the associated BDP.
If
the
transfer
through
the
associated BDP is in the byte
offset mode, and the last Unibus transfer has spilled over
into the next quadword, then these bits contain UA <17:02>
t+ 1.
Equation:
BUBA

address,

purge

from

Byte

which

operation.

during

Offset

the

SBI

VA¥

8600/8650

DW780

FMER

DW780

FAILED UNIBUS ADDRESS

UMDL

MMMMMM

<31:09>

RESERVED

<08:00>

MAP

the
of
These bits contain the binary value of the number
1in use at the time of a failure.
was
that
register
map
Bits <08:00> correspond to
bits
<17:08>
of
the
Unibus
address.

The Failed Map
Entry
Register
contains
the
map
register number used for either a DMA transfer or a
purge operation that has resulted in the setting of

Note:

one
of
the
following status register error bits:
IVMR, MRPF, DPPE, CXTMO, CXTER,
RDS,
RDTO.
This
is locked and unlocked with the Unibus to
register
status
the
of
field
error
transfer
SBI data
register.
The
FMER
is
a read
only
register.

Attempts to write to the FMER will result in an SBI
- error
confirmation.
When the FMER is not locked,
its

contents

are

<31:16>

RESERVED

<15:00>

FAILED UNIBUS ADDRESS
Note:

invalid.

BITS

<17:02>

The FAILED UNIBUS
ADDRESS
REGISTER
contains
the
upper 16 bits of the unibus address translated from
an SBI address during a previous software initiated
data
transfer.
The
occurrence
of either of two
errors indicated in the status register
will
lock
the
FAILED UNIBUS ADDRESS REGISTER:
Unibus Select
Time Out (UBSTO) and Unibus
Slave
Sync
Time
Out
(UBSSYNTO).
When
the
error
1is
cleared,
the

The

FAILED UNIBUS ADDRESS

read

only

register.
Attempting to write to the register will
result in an error
confirmation.
No
signals
or
conditions
will
<clear the register.
The contents
of the FAILED UNIBUS ADDRESS
REGISTER
are
listed
below.

20-40

;

VAX 8600/8650 REGISTER DESCRIPTION
|

DW780

MAP

IWT780 MAP REGISTERS 0485

AR 0-495
QFFSET: 800-FBC

UMDT, U

LWAE

MAP REGISTER RESERVED BITS (5/8 0)

BYTE

]

$BI PAGE ADDRESS (PFN)

indicate

922

DATA PATH DESIGNATOR

GEFSET

MAP REGISTER VALID

The MRV bit

{

(MRV)

set

software

that

the

contents of this map register is valid.
The MRV is tested
each time a map register is accessed.
If the bit is
set,
the transfer continues.
If the bit is not set, the Unibus
transfer is aborted (NXM) and the invalid map register bit
(IVMR)
1is
set
in the UBA status register, provided that

the map register has not been disabled by the map reglster

disable

(MRD)

bits

the

control register.

<30:27>

RESERVED

<26>

LONGWORD ACCESS ENABLE (LWAE)
If set, and the map register selects a buffered data

path

(BDP), then the longword aligned 32-bit random access moQde
is enable for the BDP.
This bit
has
no
effect
if
the
direct
data
path
1is selected by the map register.
This
bit

<25>

BYTE

cleared on

OFFSET

initialization.

BIT

This read/write bit is set if "this Unibus page" is
using
and the transfer is to an SBI memory
BDP's,
the
of
one
address.

This bit

is cleared

initialization.

Note:

Then
the
UBA will perform a byte offset operation on the
current Unibus data transfer.
The software can
interpret
this
operation
as
increasing
the
physical
SBI memory
address, mapped from the
Unibus
address,
by
one
byte.
This allows word-aligned Unibus devices to transfer to odd
byte memory

addresses.

Unibus transfers via the DDP or to SBI I/0 addresses

DATA PATH

Note:

will

DESIGNATOR BITS

0000
0001
1111

<24:21>

the byte offset bit.

Direct Data Path

ignore

Buffered Data Path
Buffered Data Path

(DDP)
1
15

The data path designator bits are read/write bits that are
set and cleared by the software to designate the data path
that

"this Unibus page"

will be using.

The software can assign more than one Unibus

the

DDP.

active Unibus

) <20:00>

SBI

PAGE

transfer

The software must ensure that not more than one
transfer

is assigned to any BDP.

ADDRESS

The "Unibus page" will be mapped.
These bits perform
the
Unibus
to
SBI
page
address
translation.
When an SBI
transfer

initiated the

concatenated
the

bit

SBI

with

contents

SPA

<27:07>

are

Unibus address bits UA <08:02> to form

address.

20-41

VAX 8600/8650 REGISTER DESCRIPTION
DW780 UACR

uAc

DW780 CONTROL REGISTER

OFFSET. 804

UAIL, M

ZS ‘

MAP REGISTER DISABLE BITS

UBA INTERRUPT ENABLE
UNIBUS

31>

RESERVED

<30:26>

MAP REGISTER DISABLE

SBITO

TOSBI , UNIBUS

(MRD)

This read/write field disables Map Registers in groups
of
sixteen
according
to
the
binary value contained in the
field.
The MRD bits prevent the UBA from responding to a
Unibus
address
that
points
to a disabled Map Register.
The software will load
equal to the number of
the Unibus as follows:
MAP

MRD

this
field
with
a
binary
value
4K word units of memory attached to

DISABLE

BITS

| AMOUNT OF UNIBUS | MAP REGISTERS

<4:0>

00000
00001
00010
00011

MEMORY

(WORDS)

DISABLED

0K
4K
8K
12K

11110
11111

NONE
0 - 15
0 - 31
0 - 47

120K
124K

(10)
(10)

(10)

480

(10)

0 -

495

(10)

(ALL)

<25:07>

RESERVED

<06>

INTERRUPT FIELD SWITCH (IFS)
This bit determines whether interrupts from
a
Unibus-Out
side
of
the
UBA
will
be fielded by the VAX86xx CPU or
passed

set and

the

Unibus-In

if bit

<05>

be passed to the CPU.
1nterru§t
and it is
<05>

side

(BRIE)

1If

the

set,

this bit

UBA.

then

the

this

bit

1is

set,

(BRIE)

the

UBA

‘

1is

interrupt will

cleared,

then

will be passed to the Unlbusfiin side of
not seen by the SBI.

BUS REQUEST INTERRUPT ENABLE

When this

allowed

the

the UBA

pass

interrupts
from the Unibus to the CPU, providing that bit
<06> (IFS) is set.
It is cleared by the Adaptor INIT, SBI
UNJAM, and SBI DEAD signals.
Note:
The power up state of
the BRIE bit is 0.

20~-42

VAX 8600/8650

<04>

UNIBUS

SBI

ERROR

This

bit enables

any

the

DMA

<10>

RDTO

<09>
<08>

<06>

INTERRUPT

interrupt

following

during

<07>

FIELD

DW780

ENABLE

request
Status

CXTMO

DPPE

(Command

(Data

Transmit

Time

Parity

Error)

Path

<05>

IVMR

(Invalid

MRPF

(Map

TO UNIBUS

this bit

requests

Status

the

UBSTO

UBSSYNTO

UNJAM,

this

bit

request

SBI

UNJAM

and

ENABLE

will

either

generate
Lhe

interrupt

following

DW780

set.

when
and

Time Out)
Slave Sync Time

the

Adaptor

Out)

power

INIT

will

state.

clear

the

SBI
SUEFIE

set,

the

CPU

Status

ENABLE

UBA

will

initiate

whenever

bits

any

the

set.

AD PDN

(Adaptor

Power

<22>

Down)

(Adaptor

Power

Up)

PUP

INIT

<17>

PDN

<16>

UBIC

This bit

UNIBUS

POWER

interrupt

the

following

(Unibus

Init Asserted)
Power Down)
Initialization Complete)

(Unibus

is set when

cleared

Configuration

<23>

<18>

<01>

Select

INTERRUPT

Environmental
are

Out)

CONFIGURATION

are

(Unibus

DEAD

UBA

when

(Unibus

cleared

.SBI

INTERRUPT

the

CPU

bits

<00>

bit.
<02>

set,

bit

set

Map Register)
Register Parity Failure)

ERROR FIELD

<01>

This

are

(Read Data Time Out)
(Read Data Substitute)
CXTER (Command Transmit Error)

<04>

SBI

whenever

bits

RDS

The power up state of the USEFIE bit
Adaptor INIT will clear USEFIE.

<03>

(USEFIE)

to the CPU
Register

transfer.

UACR

Adaptor

the power up state

INIT,

SBI

UNJAM

and

is
SBI

set.

DEAD.

FAIL

This bit is set when a power fail sequence on
the
Unibus,
asserting
AC
LO,
DC
LO
and
INIT are in their correct
sequence.

Unibus.,

The

UPF

when

set.
the

Unibus power

software

Unibus
It

uses

will

this

bit

initialize

the

remain powered down as long as

cleared when a Unibus power up sequence

Unibus

power

is OK.

20-43

down

sequence

has

finished

and

VAX 8600/8650 REGISTER DESCRIPTION
DW780

UACR

DW780 CONTROL REGISTER

UACH

UAIL. M

OFFSET: 004

MAP REGISTER DISABLE BITS

INTERUPT

FIELD

SWITCH

<00>

ADAPTOR

UBA INTERRUPT ENABLE
UNIBUS
10 881

BUS

REQUE

UNIBUS

SBITO
UNIBL

POWER
FAIL

INIT

When this bit is set it will completely initialize the UBA
the Data Path
The Map Registers,
the Unibus.
and
Reyisters, Lhe Status Register and the Control Register
initialization
the
start
The UBA will
will be cleared.
routine in the microsequencer,

Unibus

1initialization

sequence on the Unibus.

sequence

The UBA

and

will

generate

a Unibus power fail

initialization

sequence

takes only 500 us to complete, while the Unibus power fail

sequence

requires

approximately

25 ms.

Oonly the Configuration Register and the Diagnostic Control
Register can be read during the adaptor initialization
sequence. Only the Configuration Register, the Diagnostic
Control

the

Control

and the Status

initialization

sequence.

UBA registers
all
once the sequence has been completed,
However, the Unibus cannot be accessed
can be accessed.
been
has
sequence
initialization
the Unibus
until

The software can test for this
completed as well.
condition by reading bit <16> (UBIC) of the Configuration
or by setting bit <02> (CNFIE) of the Control
Register,
Register and looking for the interrupt generated by the
that the
Note, however,
of the UBIC bit.
setting
assertion of either Unibus INIT or Unibus power down will
also initiate an interrupt (UBINIT). The Adaptor INIT bit
|is
it
location;
to the bit
can be set by writing a 1
self-clearing.

20-44

VAX 8600/8650 REGISTER DESCRIPTION
DW780

USAR

DW780 STATYUS REGISTER

USAR

AL M

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STITUTE

| TRANSMIT |TRANSMIT]

DATA

ERROR

TIMEOUT

RESERVED

<27:24>

BR RECEIVE VECTOR REGISTER FULL
These bits indicate
the
state

loaded

Each
into

bit

the

Each bit

the

ERR
BT

S8SBI

addressable

interrupt vector

BRRVR

providing that
interrupts.

Lost

set when the

corresponding

interrupt transaction,
fielding Unibus device

data

PATH | MA
PE
| REGISTER

————

<31:28>

BRRVR's.

oata | wwvaup | wap

during

the SBI

processor

1s cleared by the successful completion of

transmission

following

software will see these bits set
failure
has occurred during the
command and the Unibus interrupt
the UBA.
These bits are cleared
to the corresponding BRRVR or by

read

BRRVR

Unibus

a read

command.

The

only after
a
read
data
execution of a read BRRVR
vector has been saved
by
only by a subsequent read
an adaptor initialization

sequence.

Bit 27 = BRRVR
7
Bit 26 = BRRVR b6
Bit 25 = BRRVR 5
Bit 24 = BRRVR 4

Full
Full
Full
Full

<23:11>

RESERVED

<10>

READ DATA TIME OUT (RDTO)
The UBA sets the RDTO bit when
the
following
conditions
are
all
true.
A Unibus device has initiated a DMA read
transfer.
The UBA has
successfully
transmitted
a
read
command
on
the
BSBI.
The
SB1
memory
or SBIA has not
returned the requested data within 100 us, and the Unibus

device

time out

will

has

set

not

us,

timed

out.

Note that the normal Unibus

and that after 10 us,

its non-existent memory bit.

the Unibus device

Thus,

the RDTO bit

will be set on the UBA status register only if the
Unibus
device timeout function is inoperative, or takes more than
100 us.
This bit is not set for a BDP
to
SBI
prefetch.
Also see Note 1.

<09>

READ DATA SUBSTITUTE (RDS)
This bit is set if a read data substitute is
received
in
response
to
a
Unibus
to
SBI
read
command
(DMA read
transfer).

when

the

non-existent
<08>

No data will

device
memory

sent

timeout
bit

read

SBI

transfer.

20-45

the Unibus

device.

CORRECTED READ DATA (CRD)
The UBA sets this bit when
response

occurs

the

it
Also

device,

will

set

see

Note

receives corrected
command during

and

the
1.

read data
a

DMA read

VAX 8600/8650 REGISTER DESCRIPTION
DW780 USAR

BWT80 STATUS REGISTER

isal
OFFSET. 008

UAIL M

BR RECEIVE VECTOR REGISTER FULL

BRRVA7
PULL

[
BRAVAA4
BAAVAS
BRAVRG
FULL
, FULL
| FULL

COMMAND ICOMMAND]

TRANSMIT |TRANSMIT|
ERRDR
TIMEOUT

DATA

PATH
PE

INVALID | MAP

LOST

uNiBys

MAP
REGISTER|
REGISTER | PE

ERROR | SELECT
By
TRIEQUT
3
PLRE:-

<07>

COMMAND TRANSMIT

ERROR

(CXTER)

This

bit
is
set
when
the
UBA
receives
an
error
confirmation
in
response
to an SBI command transmission
during a Unibus to SBI access, a BDP to SBI read, a BDP to
SBI
write, or a purge operation.
This bit is not set for
a

<06>

BDP

SBI

prefetch.

command

transfer

within

operations:

see

100 us

A BDP

A BDP purge

Note

A BDP to SBI
read
operation
device has timed out

DATA

PATH

complete

for any of

the

SBI

following

to SBI write

This bit is not
prefetch.
Also
<05>

Also

COMMAND TRANSMIT TIMEOUT (CXTMO)
This bit is set when the UBA
fails

PARITY

operation

set
see

for

Note

ERROR

for

timeout

which

for

the

BDP

Unibus

SBI

(DPPE)

This bit is set when a parity error
in
a
buffered data
path occurs during either a Unibus to BDP read, BDP to SBI
write, or a BDP purge operation.
Also see Note 1.

<04>

INVALID MAP REGISTER (IVMR)
The UBA sets this bit during
a
Unibus
DMA
transfer
or
purge
operation
when
the Unibus address points to a map
register that has not been validated by the
software
and
has not been disabled by the MRD bits.
Also see Note 1.

<03>

MAP REGISTER PARITY FAILURE (MRPF)
This bit is set with the
occurrence
of
a
map
register
parity error during one of the following operations:

A Unibus access in which the Unibus address points
to
a map register that has a parity error in the upper 16
bits, providing that the map
register
has
not
been
disabled by the MRD bits.

Mapping a Unibus address to an SBI
address
during
a
direct data path to SBI operation or a BDP to SBI read
operation (but not during a prefetch).

Mapping an address
address
during
a
write.

Also

see

from a buffered data path to an SBI
purge
operation
or
a BDP to SBI

Note

20-46

VAX 8600/8650

<02>

LOST
The

ERROR BIT
UBA

and

sets

this

another

error bit
Note 1.
<01>

USAR

bit

error

does

not

the

within

locking
this

initiate

error

field

occurs.

interrupt

UNIBUS SELECT TIME OUT (UBSTO)
The UBA sets this bit if it
cannot
gain
Unibus
within
50
wus
in
the
execution

locked

The

lost

request.

access

See

the

of
a software
initiated transfer (SBI to Unibus transfer).
Note:
When
UBSTO
is
set it indicates that the UBA has issued NPR on
the Unibus but has not become bus master.
This
condition
indicates
the
presence
of
a
hardware
problem
on the
Unibus.
The Unibus may be inoperative, or one device
may
be
holding
it
for
extended
periods.
Note that if the
Unibus does become inoperative,
it
may
be
possible
to
clear

the problem with the
the setting and clearing of
(control
register
bit
1)
(control register bit 0).
<00>

UNTBUS

SLAVE

SYNC

TIME

OQUT

the

SBI,

the
Unibus
Power
Fail
or the setting of Adaptor

assertion

UNJAM

bit
INIT

(UBSSYNTO)

This bit is set when an SBI to Unibus
transfer
(software
initiated
transfer)
times
out
during the data transfer
cycle on the Unibus.
The timeout occurs
after
12.8
us.
This
bit
indicates
a
transfer
failure resulted when a
Non-Existent

Memory

The
above
two
Unibus transfer
occurrence

either bit will

device

the

UNIBUS

addressed.

bits,
UBSTO and UBSSYNTO, form an SBI to
error locking field.
They are set by
the
the

conditions

cause

the

mentioned.

UBA to make an

The

setting

interrupt

request

on the SBI if the SBT to Unibus error interrupt enable bit
<03> (SUEFIE) in the control register is set.
The setting
of
either
UBSTO
or UBSSYNTO will lock the Failed Unibus
Address

UNIBUS

address

thus

storing

identified

the

with

high
the

‘Unibus Address Register will remain
and UBSSYNTO bits are cleared.
NOTE:

the

above

bits

CXTMO,

Seven

DPPE,

1IVMR

and

locking

field.

1If

any

bits

failure.

locked

(RDTO,

The

until

the

RDS,

the

Failed

URBRSTO

CXTER,

MRPF)

form

these

bits

error

set,
the
field
1is
1locked,
thereby preventing the
setting of other bits within this field,
until
the
bit
indicating the error is cleared.
The
failed map entry register (FMER) is also locked

and

unlocked

with

this

field.

The

setting

these bits will cause the UBA
to
initiate
an
interrupt
request
if the interrupt enable bit
for the Unibus to SBI data transfer error field
(USEFIE) in the control register is set.

20-47

VAX 8600/8650 REGISTER DESCRIPTION
EBCS
EBES

EBOX CONTROL ANB STATUS WORD

(ESCRATCH LOC: 1A - T0A)

CONSOLE ECC CORRECTION RE&EST

1B0%
180
FBM , €5FBA , FBOX
CS
DRAM , DRAM ,
¢S
15

MBOX
FATAL

MBOX
INTERUPT

ERROR

PENDING

13
IRNY

ERROR

MACHINE

MODIFIED

iyA

)

09
oA

U-8TACK
PE

FRAME

EBOX

EBOX | EBOX

£BOX

ALK
.

775

MCF RAM | CS

;

MEMORY
On GrR
WRITE

READ

2
4
MR

This register is made up from the EBCS register (see EBD2,
EBE5) and other EBox status bits (see EBEB and EBEC).
<31:27>

CONSOLE

916

EBD3 and

ECC CORRECTION REQUESTS

The bits in this field are set by
the
EHM
in
order
to
interrupt
the
Console
for Control Store or Dispatch RAM
correction.

When set, these
bits will
cause
an
immediate
Console
interrupt.
The
EHM will loop waiting for the Console to
set "DONE" in RBUFC.
When correction is complete, control

is
returned
to the EBox by setting "DONE".
The EHM will
then clear the correction request EBCS
<31:27>
and
thus
release the Console interrupt.

<31>

FBM CONTROL STORE CORRECTION
EBES5 FBOX FBM CS PE

The Console will

the parity

error

and

The Console will attempt to correct the parity

error

and

then

return

<07>
<30>

FBA CS
EBE5

<29>

"DONE" bit

RBUFC.

FBA CS

return

<07>

to correct

control to the EHM by setting the

CORRECTION

FBOX

then

attempt

REQUEST

RBUFC.

REQUEST
PE

control to the EHM by setting the "DONE" bit

FBOX DRAM CORRECTION REQUEST
EBE5 FBOX DRAM PE

The Console will reload the FBox
Dispatch
return
control
to the EHM by setting the

RAM
and
then
"DONE" bit <07>
;

in RBUFC.
<28>

IBOX
EBES5

DRAM CORRECTION REQUEST
IBOX DRAM PE

The Console will attempt to correct the parity
error
and
then
return
control to the EHM by setting the "DONE" bit

<07> in RBUFC.

27>

IBOX CS CORRECTION REQUEST
EBE5 IBOX CS PE
=

error

The Console will attempt to correct the parity

then

return

<07>

RBUFC.

<26:24>

RESERVED

<23:21>

STACK

FRAME

control
to the EHM by setting the

REVISION

The stack frame revision is written by the error

microcode

been revised.
and

the

current

indicate

how many times

The previous stack
stack

frame

20-48

frame

revision

the

stack

was

and

"DONE" bit

handling

frame

has

revision

VAX 8600/8650

<20>

<19:16>

PERFORM MONITOR

PERFORMANCE

This

is an architecturally defined bit which
It is
allows

monitored externally.
information.

See

PROCESS

ABORT

EHMSTS

the

controlled

wired to a CPU backplane
system
performance
to

the

PMR description

for

CODE

PROCESS

faulted

ABORT,

set,

instruction

EBCS

cannot

<19:16>

0101

CPR parity error that
fatal error
RLog parity error
FATAL

ERR6

MBOX FATAL

ERR1

ERROR
Port Status Line
of the following

ERRZ

WR DAT
TAG PE
DMA PE

MCCJ

CPR

MBOX

not

the

result

MBox

0.
Indicates that the
Fatal Error conditions:

MBox

ERROR

Set via EBox
detected one

ERR2

did

retried.

Unrecoverable GPR parity error
EBox WBus parity error
All IBox PC’'s are invalid
EBox failed to detect OPBus byte parity error

MBOX

pin
be

further

0001
0010
0011
0100

0110

REASON

<17>,

reason why

<14>

MONITOR ENABLE

by
System
software.
(Slot 09 Pin A07) and

<15>

ENABLE

EBE5

PE & WRITE
& WBIT

FTL

INTERUPT

REG

ERR2 CP IO PE
ERR6 CP BUFF ERR
ERR6 CFP NXM ERR

ERR

PENDING

EBC2 MBOX INTR LVL3
Mbox generates an interrupt request when it detects an
error
of any kind (excluding TB parity errors).
This bit
is set by the EBox on the third occurrence of T3 after
it
receives
MBox
Interrupt
and
is
usually handled at IRD
Time.

The

<13>

IBOX

ERROR

EBEA

IBOX

ERR

LTH

Set by the EBox when
error conditions.

<12>

ICBC
EBD7

IDRAM PE
RSV MODE

ICB6

RLOG

the

IDP6
IDP6

IBox

reports

one

IBMUX

ICA7

ICS

IAMUX

ICBC

IBUF

the

following

PE
PE

EBOX MEMORY

CONTROL

FIELD

RAM

PARITY

ERROR

EBD2

EMCR PE FLAG
Set when the EBox detected a parity error
Control Field (MCF) RAM.
<11>

EBOX

CONTROL

STORE

PARITY

for

ECC

correcting the
(Vector 8).
<10>

EBOX

Correction.

error

MICRO-STACK

PARITY

the

Memory

ERROR

EBD2 ECS PE FLAG
Set when the EBox detected a
Setting
this
bit
results
Console

will

Control Store
Parity
Error.
in
a
immediate
trap to the
When
the
Console
finishes
force the EBox to trap to EHM

ERROR

EBD2 USTK PE FLAG
Set when the Ebox detected a parity
the last entry off the micro-stack.

20-49

error when

popped

VAX 8600/8650 REGISTER DESCRIPTION
EBCS
Eacs

EBOX CONTROL AND STATUS WORD

{ESCRATCH LOC: 1A~ TOA)

FBM
€S
15

CONSOLE ECC CORRECTION REQUEST
,

STACK

FBA
FBOX IBOX
CS , DRAM , DRAM
14

PERFORM

REviSioN .
.

EBOX

<09>

MONITOR
ENABLE
04

W, o

,
03

| 6 |l e [P0 TM [P | B |
EBOX

||
|B

EBOX DATA PATH PARITY ERROR
EBD2 EDP PE FLAG
Set when the EBox detected either

an Operand

parity

error

or a Result parity error.
<08>

EBOX WBUS PARITY ERROR
EBD2 WBUS PE FLAG

Set when the EBox detected a WBus Parity
was driving

the

Error

while

bits

<15>,

bus.
NOTE

Writing,

1
<12:09> and

to
this
<4>.

This bit has

bit

different

clears

use

1in

diagnostic

mode.
<04:01>

VMS ABORT FLAGS.
VMS uses these flags,

the error
<04>

EBOX ABORT

part,

MACHINE

EBD3

<01>

<00>

whether
or

not

an MCF RAM Parity
Error
or
cases are non-recoverable.

STATE MODIFIED

STA MOD FLAG

Set by Microcode via the UMISC

<02>

determine

EBD3 EB ABORT FLAG
Set when the EBox detected
Result Parity Error.
Both
<03>

recoverable.

Field.

1Indicates

that

the

state
of
an error

the machine
occur
while

has been modified such that, should
this
bit
1is
set
the
operation

currently

executing

the

EBox

MEMORY OR GPR WRITE
EBD3 MEM WRT FLAG
Set when
a Memory or GPR write
when the error occurred.

IO READ
EBD3 IO RD FLAG
Set when the error

some

I/0

the

contents

involved

registers
of

the

cannot

retried.

operation was

1/0

1in

progress

read.

automatically clear after being
I/0

RESERVED

20-50

have

been

lost.

Since

read

VAX

8600/8650

EBXWDI

EROX WORD |

(EGGRATCH LOC 1L ~ TOE)
!i

O7T

LAST WORD THAT THE EB0X SENT TO MEMORY TO BE WRITTEN (TOP OF STACK POINTER)
i

]

<31:00>

S—

]

[

EBox

the

FQ).

copy of

the

last

word

that

EBXWEZ
73

EBDX WORD 2

SECOND TO LAST WORD THAT THE EBOX SENT TO MEMORY TO BE WRITTEN
{TOP OF SCRATCH PAD MINUS 1)
h

the

wrote to the MBox.
This word is obtained by popping
last word off the Scratch Pad Stack (EScratch
Location

(ESCRATCH LOC: 1F — T0R)
30

| —

| N—

[]

]

SECOND TO

This
that

LAST

popping

EBox

the

MR -13908

EBOX WORD WRITTEN

the

AER

<31:00>

LAST EBOX WORD WRITTEN

This

[

wrote

second

a copy of

the

MBox.

last word

(EScratch Location F1).

20-51

the second
This

off

the

word

to
is

Scratch

last

word

obtained

Pad

by
Stack

VAX 8600/8650 REGISTER DESCRIPTION
EDMC
EOME

EBOX DIAGNOSTIC/MAINTENANCE COMTROL BEGISTER
£EBD4

DIAG

UADRE |

180X

MBOX

AG 1 piag

Reser | GHEAR

FLAGS

INHIBIT

ESTALLS

The EBox Diagnostic/Maintenance Control Register (EDMC) is a write
only register which shares the same WBus register address as the
EDMC
EBox Data Path Error Register (EDPE), a read only register.
implements up to 8 bits which can be used by EBox microdiagnostics
to control hardware

in the CPU.

A Master Reset or Diagnostic Reset causes EDMC to be written with
all zeros, thus clearing INH STALL, CLR FLAG, RST IBOX, and MB UADR
<07:06>.

<07:05>

RESERVED

<04>

DIAGNOSTIC MBOX MICRO ADDRESS 07

EBD DIAG MBOX UADR 7 H <Pin A06-69> V$Al1l02
wused by
This bit is
Diagnostic MBox Microaddress Bit 7.
bit 7 of the MBox Microsequencer
to control
diagnostics
Address.

<03>

DIAGNOSTIC MBOX MICRO ADDRESS 06

EBD DIAG MBOX UADR 6 H <Pin A06-71> V$Al0l
This bit is wused by
Diagnostic MBox Microaddress Bit 6.
to control bit 6 of the MBox Microsequencer
diagnostics

Address.
<02>

DIAGNOSTIC

RESET

IBOX

<01>

DIAGNOSTIC CLEAR CYCLE IN PROGRESS FLAGS
EBD4 DIAG CLR FLAGS H VS$C198

EBD DIAG RST IBOX H <Pin A06-87> V$D1l16
This bit initiates an IBox reset.
Diagnostic Reset IBox.

The assertion
Diagnostic Clear Cycle in Progress Flags.
of this bit clears the Cycle in Progress Flags in the EBox
Control Logic when they

are

<clocked

the

end

machine cycle.

<00>

DIAGNOSTIC

INHIBIT ESTALLS

EBD4 DIAG INH STALLS H V$C177

The assertion of this bit
Diagnostic Inhibit EBox Stalls.
prevents the EBoOX Mlcrcsequencer and EBox Data Path from
not
The bit does
asserted.
stalling when EBox Stall is
inhibit the assertion of copies of EBox Stall used by the
FBox, IBox, MBox, or EBox Control Logic or the copy which
serves as a branch condition to the EBox Microsequencer.

20-52

VAX

8600/8650

EOPSR

EBGX DATA PATH STATUS WoRD

{ESCRATCH LOC: 1B - T0B)

BMUX BYTE (N ERROR

~
BY

AMUX BYTE IN ERROR

ot o7

ERROR ADDRESS

VMOBYTE IN ERROR
.,

BMUX | BMUX
l weus
| oesus REsuLT W

esox | Amux | esox
SEERAND cRa
| WeUs | GeRB
:

This

is made

from the

nibble

registers

13977

the PDP MCA.

<31:28>

BMUX BYTE IN ERROR
PDP4 BMX ERR BYTE <3:0> (EDPH)
|
This field is only valid when either bit <07> or bit
<00>
is
set.
This
field
indicates
the
byte(s)
that were
associated with the BMux Parity Error.

<27:24>

AMUX

BYTE

ERROR

PDP3 AMX ERR BYTE <3:0> (EDPH)
This field is only valid when either bit <01> is
set,
or
when
bit
<02>
1is
set, or when bit <03> is set and bits
<00:02> and <06:07> are reset.
This field
indicates
the

<23:16>

byte(s)

that were

EBOX GPR

PARITY

EHMSTS

set,

<15:12>

<26>

these

bits

associated with

the AMUX Parity

Error.

ERROR ADDRESS

(EBox GPR B PE) or <25> (EBox GPR A PE)
indicate the failing GPR address.

VMQ

BYTE IN ERROR
PDP5 VMQ ERR BYTE

<3:0> (EDPH)
This field is only valid when bit <05> is set and bit <08>
is
reset,
It indicates the byte(s) that were associated
with the Result parity error.

<11>

WREGISTER PARITY

ERROR
PDP6 WREG ERR (EDPH)
Indicates that the parity
not

match

the

The

inputs

parity

the WReg Mux

The

AMux

and

The

BMux

for WReg

The ALU

BMux

the

generated

for

input
at

the

output

WReg Mux did
of the WReg.

are:

WReg

Format

Shift

Operations.

for post ALU Wreg

Shift

Operations.

NOTE

This error will

also cause

a RESULT PE.

<10:09>

RESERVED

<08>

EDP MISCELLANEOUS PARITY ERROR
PDP8 EDP MISC (EDPH)
Indicates that the ALU was the input
to the VMOMUX when
a
parity error was detected at the VMOMUX output.
When this

bit is set the contents of
This error will also cause

20-53

bits

<12:15>
a RESULT PE.

are

not

valid.

vAX 8600/8650 REGISTER DESCRIPTION
STATE EDPSR

EBOX DATA PATH STATUS wWORD

1340
{ESCRATCH LOC: 1B - T08)

BMUX BYTEIN ERROR
i

AMUX BYTE IN ERROR

VMG BYTE IN ERROR

MISC | WBUS

l WREG

BMUX

£pe

06
BMUX
oPBUS
PE

RESULY

]

EBOX

AMUX

GPRA

WBUS

EBOX

GPR B

uuuuuuu

<07>

BMUX WBUS PARITY ERROR
PDP8 B WBUS (EDPH)

a
when
Indicates that the WBus was the input to the BMux
parity
error
was
detected
at
the
BMux
output.
Bits
<28:31>

<06>

indicate

BMUX OPBUS

the byte(s)
in error.

PARITY ERROR

PDP8 B OPBUS (EDPH)
Indicates that the OPBus
parity) was the input to
was detected at the BMux
contents of bits <28:31>
<05>

longword
by
(which is protected
the BMux when a BMux parity error

output.
When this bit is set the
are not valid.

RESULT PARITY ERROR

PDP8 RSLT CHK

(EDPH)

If neither WREG PE <11> nor EDP MISC <08>
are
set,
this
bit
indicates
that
the VMQSAV Register was the input to
the VMOMUX when
a VMOMUX
parity
error
was
detected.
Otherwise,
this
bit
is
the
"or" of all three of those
conditions.

<04>

RESERVED

<03>

OPERAND PARITY ERROR

PDP8 OPER CHK

(EDPH)

this bit
then
reset,
are
<07:06>
If bits <02:00> and
indicates
that
the
VMQSAV Register was the input to the
AMux when an AMux Parity error was detected.
Otherwise,
this

indicates that one of the following errors were

bit

detected:

BMux GPR B PE
PE
BMux WBus
BMux OPBus PE

<02>

AMux GPR A PE
PE
AMux WBus

EBOX GENERAL PURPOSE REGISTER A PARITY ERROR
PDP8 A RAM (EDPH)

Indicates that Scratch Pad-A was the

input

the

when a parity error was detected at the AMux output.
<01>

AMUX WBUS PARITY ERROR

PDP8 A WBUS

(EDPH)

Indicates that the WBus was the input to the AMux

parity error was detected at the AMux output.
<00>

AMux

EBOX GENERAL PURPOSE REGISTER B PARITY ERROR
PDP8 B RAM (EDPH)

Indicates that Scratch Pad-B was the

when

parity

error

was

BMux.

20~-54

input

when

the

BMul

detected at the output of the

VAX

8600/8650

DESCRIPTION
EHMSTS

EHMETS
{ESCRATCH LOC: 18 - T08)
31

EARDA HANDLIRG MICROCODE STATUS WORD
29

Service
| Enm
SomicE
‘ | ENTERED | YMS
aequest
:
ENTERED

REQUEST

FBOX
apg

EBD)

GPRB

EBOX

GPRA

180X
on

£BA

FBM

;

DRAM

Vfiufi

1B
1Be

180X

DRAM

1SBIA

BNt | SOMMARY

]

FBOX
8

MBOX

MICRO-TRAP VECTOR ADDRESS
i

EHM HAS STARTED PARITY ERROR CORRECTION PROCESS

0¥

EAR | PROCE3S {7
| ABORT
vSAVED

TURNED I

SBIA

‘

{SUPPLIED BY VM$)CODE
PRIMARY
ERROR
s

RESOURCE

FULL RPT
FOLLOWS | OFF

Vfiug

80X

'
5

9—
MR

This

status

Status

word

contains
(EHSR)

a modified

which

copy

stored

addition,

two

status

Routine

uses

Problem

other

the

EHM

bit

Handling

Microcode
Routine.

report

Routine

The

MBox

uses

EHM copies
18 just before
then calls the
frame onto the

<31>

the

Scratch

Routines

use

error

Error
Pad

keep

the

EHSR

report

contents of EHSR into EBox
it sets VMS ENTERED and clears
Interrupt Exception
Microcode

Scratch

interrupt

stack

and

call

the

ODA.

status

pass

Microcode

and

the

Handling

interrupts;

Handling

location

track

Interrupt

bit

errors.

The

The Error Handling Microcode uses EHSR
during the error handling process.

1390

the

FBox

FBRox

hardware

Pad
1location
ENTERED.
The EHM
to
push
the
stack
Machine Check Handler.
EHM

MBOX SERVICE REQUEST
If the Interrupt Handling

Microcode determines that it was
an MBox Error Interrupt it will set this
EHM.
The EHM will test this
flag
and,
will process the MBox Error.

called
to handle
flag and call the

<30>

set,

the

EHM

EHM ENTERED

This flag is
condition.
occurs

the

first

the

by
is,

EHM to detect
those cases when

the

EHM

Routine

before

This flag
EHM

used
That

the

error and pass

control

able

a double
a second
to

finish

flag

Routine

clear

will

set

(which

this

trap
trap

processing

to VMS.

is checked each time the EHM routine

error
error

is entered.

the

expected

case)

flag

and

process

the

will

happen:

then

the

error

the
normal
manner.
If
the
flag
is
set,
however,
indicating that the EHM Routine
was
in
the
process
of
handling
an
error
when it was called to handle a second

error,

then

the

Keep

one

two

things

second error was detected by either the EBox
or
the MBox Fatal Error detection circuitry,
then the EHM
Routine will loop at UPC 21.
This in turn will
cause

the

Alive

Fail

condition

following message

system.

"Attempting
DOUBLE

and

to save machine

ERROR"

20-55

and

Snap

the

Shot

state

Console

will

the

state

due

to"

the

"MACHINE

VAX 8600/8650 REGISTER DESCRIPTION
EHMSTS

ERAGA HANBLING MICROCODE STATUS WORD

HMSTS

{ESCRATCH LOC: 18~ T0B)

SERVICE
REQUEST

[

15
Ed

MICRO-TRAP VECTOR ADDRESS
3

PROLESS
MEAR || ABOS
SAVED
Rl

EHM HAS STARTED PARITY ERROR CORRECTION PROCESS

180X GS180
FBOX
DRAM DRAM

MBOX

VALID

JSBIA

lon

TRY

VALID

l;’fifflfiuw SUMMARY | FULL RPT |TURNED

1HUR , oM
:
SEmice
CS, CSFBA
GPRA , GPR
GPRB , 80X
Gen. . £BOY
| EBOX
REQUEST

YME
EHM
ENTERED | ENTERED

AESGURCE

{SUPPLIED BY VMS) 3

PRIMARY ERROR CODE

FOLLOWS | OFF

If the second error was detected by the IBox then the
EHM will put a code of 5 in CSM.STATUS (Scratch Pad
location:

C€O0)

and

call

the

Routine.

CSM.ENTRY.DE

This will result in a Keep Alive Fail Condition and
the Console will print the following message and Snap
|
Sshot the state of the system.
"Attempting to save machinc state due to"

"CPU

ERROR

HALT"

NOTE

Because the state of EHSR is saved in EScratch 18
before the EHM Routine clears EHM ENTERED, this
flag will always be set in the copy of the Stack
Frame saved by the VMS MCHK Handler.

<29>

VMS ENTERED

This flag is similar to the EHM ENTERED flag.

It is

use

detect the case where the VMS Machine Check Handler i

in the process of handling an error when a second error is 7

detected.

The EHM Routine sets this flag just before

<calls

the

The Machine Check Handler
Handler.
Check
Machine
processes the errors and clears this flag just before it
executes

REI to continue the operation (or a BUGCHECK

to halt the operation).

If a second error trap occurs while the Machine Check
is still processing the first error, then the EHM
Handler

Routine will process the error in the normal manner. That
is, build a Stack Frame, clear the error condition, roll
back the PCs and determine if it should call VMS.

However, since the VMS ENTERED
that

VMS

flag

set

(indicating

was processing an error when a second error was

Instead it will put
detected), the EHM will not call VMS.
a code of 5 in CSM.STATUS (EBox Scratch Pad Location: CO)
This in turn will
and call the CSM.ENTRY.DE Routine.
result in a Keep Alive Fail Condition and the Console will

print the following message and Snap Shot the state of the
system.

"Attempting to save machine state due to" "CPU ERROR HALT" .

20-56

VAX

8600/8650

DESCRIPTION
EHMSTS

<28>

FBOX SERVICE REQUEST
The micro-routine that

flag

FBox

handles FBox Problems will set this
determines that the problem was caused by an

hardware

error.

The

Routine
to
process
flag, to determine if
error.

27>

FIX

FBOX GENERAL

Set

the

EHM

PURPOSE

when

routine

starts

FIX

EBOX GENERAL

Set

the

EHM

PURPOSE

when

parity error.

<25>

FIX EBOX GENERAL
Set

the

parity

<24>

<23>

EHM

FIX

FBM

CONTROL

FIX FBA CONTROL
Set

the

ERROR
an

correct

EBox

STORE

PARITY

STORE

when

PARITY

GPR

ERROR
an

EBox

IBox

GPR

ERROR

starts

GPR

correct

FBM

Control

FBA

Control

ERROR

starts

correct

FBox

Dispatch

FIX IBOX DRAM PARITY ERROR
Set by the EHM when it starts
RAM parity error.,

to correct

IBoOx

Dispatch

FIX

IBOX

Set

PARITY

ERROR

starts

to correct

FBOX

error.

DRAM

the

PARITY

EHM when

ERROR

starts

error.

CONTROL

the

STORE

EHM when

parity

error.

1IBox

Control

MEAR SAVED

Indicates
saved

the

MBox

Error Address

EScratch

Location:

Error

Full

DB)

(MEAR)

result

the

was
last

trap.

ABORT

EBox microcode

retry

the

that

(in

PROCESS

The

<l16>

PARITY

correct

FBox

FIX

Set

MBox

<17>

correct

Store
<18>

EHM

parity

RAM parity

<19>

EHM

Store

<20>

the

test this
an
FBox

ERROR

FIX IBOX GENERAL PURPOSE REGISTER PARITY ERROR
Set by the EHM when it
starts
to
correct
an
parity error.

by the EHM when
Store parity error.

21>

call

correct

starts

error.

Set

<22>

starts

PURPOSE

when

then

PARITY

parity error.
<26>

will

the
error.
The EHM will
it was
called
to
handle

reason

the

code.

detected

faulted

condition which

instruction.

RESERVED

20-57

See

EBCS

prevents
<19:16>

a
for

VAX 8600/8650 REGISTER DESCRIPTION
EHMSTS
T3t

ERRGE HANDLING MICROCODE STATUS wonn

(ESCRATCH LOC: 18 - TO8)

MBOX

£HM

vMS

FBOX

<15:08>

;
| PROCESSN¥
MEAR
c§FBM , CSFBA | £BOX
DRAM 180X
DRAM CS180X SAVED |l ABORT .
|

E£BOX _ GPR180X
SERVICE ENTERED l ENTERED SERVICE
lms*r
SEDfiESTl G | £B0X
GPAR | GPRA
15

EHM HAS STARTED PARITY ERROR CORRECTION PROCESS

MICRO-TRAP VECTOR ADDRESS

AESOURCE
J;fifi”“ 23?;}“"]%5Ao | TURNE

MBOX

[seiA

MICRO TRAP VECTOR ADDRESS

SBIA

BNED
OFF

through

Contains the vector address

PRIMARY ERROR CODE
BY VMS)
(SUPPLIED

the

which

EHM

was

entered.

VECTOR

FBox Error (Called by FBox Interrupt Handler)

EHM Detected a Process Abort condition during

by MBox Interrupt Handler)
MBox Error (Called

a MBox Error Register Full Micro-trap.

EBox

Error

MBox

Fatal

Error.

TB PE Error (EBox Port Regquest only)
IBox Op-Port-Write and IBox Error
IBox Op-Port-Write and TB Parity Error

10
10
10

EBox

IMD Read and

18
18
18
18

EBox
EBox
EBox
EBox

Fork and IBox Error
Fork and TB Parity Error
ID Read and IBox Error
String Read and IBox Error

IBox Sync Failure

IBox

Error

EBox IMD Read and TB Parity Error

EBox String Read and TB Parity Error

Rlog Unwind Failure

1F
<07:00>

REASON

CODE

This field

is supplied by the VMS Machine

Check

Handler,

Therefore, this field will be valid only after the Machine
Check has been processed by VMS.
This field will
not
be
Frames extracted directly from the EBox
Stack
for
valid
for
See <03:00>
Scratch Pad RAMs or the Interrupt Stack.
the actual Reason Codse.

£07>

MBOX INTERRUPT ENTRY VALID

Indicates that the Stack Frame was generated as

an MBOX

result

interrupt.

<06>

‘SBI

SUMMARY ENTRY VALID

<05>

SBIA FULL REPORT FOLLOWS

Indicates that a copy of the SBIA Error
Summary
has been appended to the end of the stack frame.

Indicates that a full SBIA Error Log

entry

entry in the System Event File (ERRLOG.SYS).

20-58

follows

this

VAX

8600/8650

DESCRIPTION
EHMSTS

<04>

<03:00>

RESOURCE

TURNED OFF
Indicates that VMS disabled
Caches.
PRIMARY ERROR CODE
This field indicates which

Code
o

001

Box

Detecting

mwn*—

—m--—

Error

———;u

-—g‘—

—

FBox

010
011

EBox

100

MBox

IBox

(Fatal

Error)

20-59

either

Box

the

detected

FBox

the

one

error.

the

vAX 8600/8650 REGISTER DESCRIPTION
EHSR
ERROA HANDLING STATUS REGISTER

EHSR

1PR; 4A (ESC:DA)

BOX
Cs

;‘5&&

Agggsss

TRAP
104

29
EHM FIXING

FBM

80X
£BOX
DRA M . DRAM .

MBOX

MICRO-TRAP VECTOR ADDRESS

Vi3
EHM
ENTERED | ENTERED

<26>

EHM

£80X

SERVICE |

REQUEST

]

[

<31:27>

EHM FIXING

rBOX

ka0

EBOX

GPRB

EBOX

GPRA

FIXING

The EHM sets the appropriate bit in this field just before
it sets the corresponding bit in EBCS <31:27>. Setting a
bit in EBCS <31:27> causes the EBox to interrupt the
Console for Control Store or Dispatch RAM correction.
)

MEAR SAVED

When the EHM is called to handle an MBox Error Register
DB and sets
(ERF) micro trap, it saves MEAR in ESC:
Full
this bit. Later, when the EHM 1is servicing the MBox
interrupt associated with the ERF micro trap, it checks
the

this bit to determine whether it should get MEAR from

MBox or
<25>

1BOX

ESC:

DB.

PROCESS ABORT

An MBox
1)
The EHM sets this bit if it determines that:
CPR Parity Error failed to result in an MBox Fatal Error,

or 2) The EBox failed to detect bad data on the OPBus. If
this bit is set, VMS will either Bugcheck the user or the
system.

<24>

MBOX TRAP TO 4

This bit indicates the occurrence of an MBox trap to 4.
When running with the the IPL above 1D this may be the
only sign of an SBE. It is used by VMB to check for
single bit errors.

<23:16>

MICRO-TRAP VECTOR ADDRESS

The EHM saves the entry level trap vector address in
field.

VECTOR

2
4

REASON

FBox error (Called by FBox interrupt handler)
EHM detected a process abort condition during

a MBox ERF micro-trap

MBox error (Called by MBox interrupt handler)

MBox fatal error

VECTOR

EBox

error

TB parity error (Ebox port request only)
EBox Op-Port-Write and IBOx error

IBox Op-Port-Write and TB parity error

EBox IMD read and IBoX error

EBox IMD read and TB parity error

REASON

(Cont)

EBox fork and IBox error

18
18

EBox ID read and IBoX error
EBox string read and IBoXx error

1F
<15:08>

this

The vector addresses are:

EBox fork and TB parity error

EBox string read and TB parity error
EBox sync failure

RLog unwind parity error

RESERVED
20-60

VAX 8600/8650 REGISTER DESCRIPTION
,

<07>

MBOX

SERVICE

the

called

EHSR

REQUEST

interrupt

handling microcode

handle

MBox

error

determines

interrupt,

flag and call the EHM.
The EHM will
if set will process the MBox error.
<06>

EHM

test

occurs

that

will

this

ENTERED

it was

set

this

flag

and,

This flag is
condition.
the

used by the EHM to detect a double error
That is, those cases when a second error

before

the

first error

EHM

routine

and pass

able

control

finish

trap.
trap

processing

to VMS.

This flag is checked each time EHM
is
entered.
If
the
flag
1is clear (which is the expected case), then EHM will
set this flag and process the error in the normal
manner.
If
the
flag
1is set, however, indicating that EHM was in
the process of handling an error when
it
was
called
to
handle

the

the
will

second

error,

second

MBox
loop

then one

two

error was detected

fatal
at UPC

things

will

either

happen:

the

error
detection circuitry,
21.
This in turn will cause

EBox

then EHM
a
Keep

Alive
Fail
condition
and the Console will print the
following message and capture (Snap Shot) the state of
the

system:

Attempting

to save machine

"MACHINE
2.,

the

second

error

was

DOUBLE
detected

state

due

to"

IBox

then

ERROR"
by

the

EHM

will put a code of 5 in CSM.STATUS (ESC:
CO0) and call
the CSM.ENTRY.DE routine.
This will result in a
Keep
Alive
.Fail
Condition
and the Console will print the
following message and
Snap
Shot
the
state
of
the
system:

Attempting

to save machine state due
"CPU ERROR HALT"

to"

NOTE

When EHM
will set
and call

<05>

finishes
processing
the
error,
it
the VMS ENTERED flag, clear this flag
the VMS Machine Check Handler.

VMS ENTERED
This flag is similar to the
to

detect

flag

operation).

just before

VMS Machine

calls

Check

used

Handler.
The
and clears this
continue
the

the

this

case where

Handler

EHM sets

the

EHM ENTERED flag.

in the process of handling an error when a second error
detected.
the Machine

Check

Machine Check Handler processes the errors
flag just before it
executes
an
REI
to
operation
(or
a
BUGCHECK
to
halt
the

20-61

VAX 8600/8650 REGISTER DESCRIPTION
EHSR
EHSH

PR 4A (ESCDA)

£}

ERROR HANBLING STATHS REGISTER

MEAR

PROCESS

EMM FIING
'
l €SFBM | £BACS , FBOX
DRAM _ 180X
DRAM CS180X, | SAVED | ABORT | /7
-

i
07

i
06

MICRO-TRAP VEGTOR ADDRESS

EnM

EHM FIXING

semcs
aeeuss&* ENTEnen | ENTeneo | SERVCE, | Foox b

Gk G)
MR-} IRIG

If a second error trap
occurs
while
the
Machine
Check
1is still processing the first error, then the EHM
Handler
routine will process the error in the normal manner.

is,

back the PC’'s and determine

However, since the VMS ENTERED
that

VMS

That

a Stack Frame, clear the error condition, roll

build

it should call VMS.

flag

(indicating

set

was processing an error when a second error was

a
Instead, it will put
detected), EHM will not call VMS.
code
of
5
in
CSM.STATUS
(ESC:
C0)
and
call
the

This in turn will result in a Keep
CSM.ENTRY.DE routine.
print the
will
Console
the
and
condition
Fail
Alive
following message and capture (Snap Shot) the state of the
system:

" Attempting to save machine state due to"
"CPU ERROR HALT"

<04>

FBOX SERVICE

REQUEST

The micro-routine that handles FBox problems will set this

determines that the problem was caused by an
it
if
flag
EHM
the
The routine will then call
FBox hadrware error.
routine to process the error.
The EHM will test this flag
to determine if

<03>

it was called to handle an FBox error.

FIX FBOX GPR PE

Set by the EHM when
parity error.

<02>

it attempts

correct

FBox

FIX EBOX GPRB PE

Set by the EHM when it attempts to correct an EBox

GPR

parity error.
<01>

FIX EBOX GPRA PE

Set by the EHM when it attempts to correct an EBox

parity error.
<00>

FIX IBOX GPR PE

Set by the EHM when it attempts to
parity error.

20~-62

correct

IBox

GPR

VAX

8600/8650

EMD

ERGX MEMORY DATA RERISTER

{ADDRESSED BY NAME FROM CONSOLE)

PRINT LOCATION: 1BD1-3 (IBF1)
313829282725?52&?32231301'9181716151413121115@859?05059493&20139

CONTENTS OF THE IBOX EBOX MEMORY DATA (EMD) REGISTER
i

]

}

]

NOTE: BITS <31:80°> ARE READ ONLY

<31:00>

1IBOX EBOX MEMORY DATA REGISTER
The contents are displayed in bit

Additional

<31:00>.

Notes:

(1)

CSM

Overlay

"Examine_IBox_Miscellaneous_Register",

read

the

contents

the

EMD

the
UOPSEL
field
selects
the OPBUS
which
in
turn
location.

(2)

The

EMD register

nor

the

SDB

not

the

ESC

on any backplane

ESASAV
3

to drive

pins

path.

EBOX STARTING ADBRESS SAVE REGISTER

{ESCRATCH LOG 22— T12)
N3

used

Basically,

EMD register
loaded
into

visible

visibility

"EIMR",

27T

o088

VIRTUAL ADDRESS OF INSTRUCTION CURRENTLY BEING PROCESSED BY EBOX
i

<31:00>

CURRENT PC FOR EXECUTION UNIT (EBOX)
This register contains
the
address

instruction that

(Macro

PC)

the

EBox or FBox

is currently processing.

ESP

the

EXECUTIVE STACK PRINTER

IPR: 01 (ESCRATCH LOCATION: E1}
31

VIRTUAL ADDRESS OF TOP OF STACK (EXECUTIVE MODE)
]

]

<31:00>

EXECUTIVE
Contains

access

STACK
the

mode

]

POINTER

stack

field

pointer

the

PSL

20-63

used

when
(Executive

the

Mode).

current

VAX 8600/8650 REGISTER DESCRIPTION
ESPA/ESPD

ESPA/ESPD

These registers allow VMS to access
the
EBox GPR/SP
RAMS
using
For example, during machine checks
macro instructions (MTPR/MFPR).
for array

single bit errors,

the VMS machine

check

handler

would

in RAM locations 25 thru 28 (HEX).
the MBox state saved
access
Executing macro instructions between the MTPR and MFPR will yield
address

with the RAM

loaded

must

ESPA

The

results.

unpredictable

followed immediately by reading the data from ESPD.

The reason for the above scenario is
errors,

the

Stack

Frame

1is

not

that

for

array

single

access

the

bit

pushed on the Interrupt Stack.

Therefore, the VMS machine check handler

must

explicitly.

GPR/SP

EBOX SCHATCH PAD ADDRESS REGISTER

ESPA

IPR: 4E

08 07

912

27 2

31 30

EBOX SCRATCH PAD ADDRESS
3

]

i
MR- 13933

scratchpad

location

to be

EBox

address

the

This write only register is loaded with
accessed.

EBOX SCRATCH PAD DATA REGISTER

ESPD

PR 4F

EBOX SCRATCH PAD DATA
2

]

This read only register contains the data requested by the MTPR to
data,
the
accessing
to
prior
loaded
not
is
ESPA
If
ESPA.
unpredictable

results will occur.

20-64

VAX 8600/8650

EVESAY

EBGX VIRTUAL ADDRESS MULTIPLIER

{ESCRATCH L0C: 19 — T09)

QUOTIENT SAVE REGISTER

EBOX VIRTUAL ADDRESS (EVA) FOR EBOX PORT REQUESTS
£

[

EVMQSAV

(EBox
Register).

During

EBox

Virtual

port

Memory

requests

[

]

Address/Multiplier

this

contains

results.

May

contain

calculated

an
EBox

EBox
result

Virtual

Address

depending

EBoX.

20-65

the

Quotient

address
that was acknowledged by the MBox (PA ACK).
operation, this register is used to temporarily store

<31:00>

Save

the

virtual

During

normal

partial

operation

EBox

partial
of

the

VAX 8600/8650 REGISTER DESCRIPTION
FBXERR
FBOX ERBOR REGISTER

T!G}
{E&fii&‘mfi Lt 20~

FBM

FBA

Fg%

SELF

ERROR

GPR
PE

Pads

reading

The EHM builds this register in the EBox Scratch
three FBox registers:

03,

02,

and 01.

18
}

FBOX | aggeaven
AX
OPERAND

<31:26>

RESERVED

<25:24>

EXPONENT EXTENSION <01:00>
FBRD EXT <1:0> (FA01)
This field, which is an extension of the
exponent field,
indicates overflow and underflow conditions as follows:

€23:22>
<21>

FIELD

CONDITION

00
01
10
11

Normal
Overflow
Underflow
Underflow

RESERVED
FBM CONTROL

STORE

PARITY

MPZ5 CS PAR ERR (FM07)
Set when the FBM module

Parity

Error.

When set,

ERROR

detected

FBM

Control

Store

the CS Address is latched in the

FBM MSQ MCA.

<20>

FBA CONTROL STORE PARITY ERROR

ACC4 RAM PERR (FAl3)

Store
FBA Control
an
detected
Set when the FBA module
the Control Store Address is
When set,
Error.
Parity
latched

19>

in the FBA MSQ MCA.

FBOX DRAM PARITY ERROR

MCB3 FDRAM PAR ERR (FM1ll)

Set when the FBM module detected
a
Dispatch
RAM
Parity
Error.
Neither
the
DRAM
address nor the DRAM data are
latched.

<18>

SELF TEST ERROR

FBR3 SELF TEST ERROR (FAOQ01l)

Set when the FBox detected an error while running the Self
error was
the
whether
indicate
will
<02>
Bit
Test.
associated with the

17>

FBA or FBM Mcdule.

FBOX GENERAL PURPOSE REGISTER PARITY ERROR
FBR4 GPR ERROR (FAO01l)

Set when the FBA Module detected a GPR Parity Error.
specific byte in error cannot be identified.

20-66

The

VAX 8600/8650

<16>

RESERVED OPERAND

FBR6 RESERVED OP

This

bit

(FAO01l)

generally

indicates

software

problem

and

has

significance
1in
the
«context
of
a
hardware error.
It
indicates that one of the operands received
by
the
FBox
had a negative sign and an exponent of zero.
<15:14>

INSTRUCTION FORMAT CODE <01:00>
FBR9 FORM <01:00> (FA01)
This field indicates the format of
the
instruction
that
the
FBox
was executing when the FBox status was saved in
this register.
CODE

FORMAT

F
G
D
I or

01
10
11

<13:12>

<06:05>

FXP6
This

<5:6> (FA01)
has no significance

<08>

FPX RESULT

FXRES
field

represents

DENORM

FBR1

exponent

result

the

bits

context

error.

<13:12>.

RESULT

DENORM (FA01)
bit has no significance

This
indicates
out”.

that

in the context of errors.
It
rounding operation resulted in a "carry

<07:03>

RESERVED

<02>

IF SELF TEST ERROR (0=FA/FM=1)
FBR4 WBUS D00 (FA01)
This bit has a double meaning.
During
normal
operation
this bit indicates that the divisor was equal to zero.
If
SELF TEST ERROR is set, however, this bit indicates
which
FBox module detected the Self Test error (0=FA/FM=1).

<01>

RESERVED

<00>

FBOX

PROBLEM

FBR1 FBOX PROBLEM (FAOQ1l)
Set
when
the
FBox
detected
conditions:
Exponent

Extension

Problem

one

.......

GPR Parity Error ....ceeeeseseeses
FBM Control Store Parity Error ...
FBA Control Store Parity Error ...
FDRAM Parity Error ..ceeeeeessss0.
Self

Test

ErXror

the

Bits

<25:24>

Bit
Bit
Bit
Bit

(17>
<21>
<20>
<19>

..cescecssasncaaana

BRit

<18>

Divide Dy Z€r0O .ieeescasscssssasss
Denormalize Result ..cessseessess0¢

Bit
Bit

<02>
<08>

Reserved Operand

Bit

<K16>

...ccsceeeeeeessss

20-67

following

VAX 8600/8650

IBESR

1BESR
(ESCRATCH LOC: 1D - T0D)
31

1BOX EAROR STATUS WORD
29

IAMUX BYTE IN
LRARGA GODL
1

1AMUX
30URCL
0= GFR
11=WBUS

RESERAVED]|

MODE

1BOX

INST

RLOG

BMUX

23
180X

AMUX
PE

80X

180X

DRAM

¢S

This register is a combination of the IBox Error
the EBox Diagnostic Maintenance register (EDMS).

<31>
<30:29>

(IBE)

and

with

the

RESERVED
IBOX AMUX BYTE IN ERROR CODE
IAMUX EC <1:0> LTH
Indicates the most significant
IBox AMux parity error.

EBEA

Code

Byte

00
01
10

0
1

IAMUX
EBEA

SOURCE
IWBUS

(0=GPR/1=WBUS)

DATA

Indicates

,J’

associated

2
3

11
28>

byte

that

LTH

the WBus

was

the

input

the

1IBox

AMux

when an error was detected at the output of the IBox AMux.
<27>

RESERVED MODE

DETECTED

EBEA

LTH

RSV MODE

Indicates that an operand specifier attempted
addressing
mode
that
1is not allowed in the
which it occurred.
<26>

IBOX BMUX
EBEA

PARITY

IBMUX

Indicates
of

the

IBuffer

<25>

ERROR

LTH

that
1IBox

a parity error was detected at
BMux.

the

The

IMD

Latch.

INST

BUFFER PARITY

ERROR

EBEA

IBUF

to
wuse
an
situation in

input

the

BMux

the

was

output

either

the

LTH

Indicates that a parity error was detected on
either
the
OPCode
bytes (Byte 0 or Byte 1 in the IBuffer), or on the
byte
selected
by
the
RMode
Finder
(IBGPR)
during
optimization,
<24>

RLOG PARITY ERROR
EBEA RLOG

Indicates

that

the

23>

LTH

a parity error was

detected while

unwinding

RLog.

AIBOX AMUX PARITY

ERROR

EBEA IAMUX PE LTH
Indicates that a parity error was detected at
the
output
of
the
1IBox
AMux.
The input to the AMux was either the
WBus

<22>

GPR.

See:

IBESR

<30:29>

and

<28>.

IBOX DRAM PARITY ERROR
EBEA 1DRAM PE LTH

Indicates that a parity error was
data.

20-68

detected

the

DRAM

VAX 8600/8650 REGISTER DESCRIPTION
IBESR

<21>

IBOX CS PARITY ERROR
ICS PE LTH

EBEA

Indicates that a parity error was

Control
<20:16>
<15:08>

<14>

detected

the

IBox

RESERVED

EDMS REGISTER BITS <D15:D08>
See

<15>

Store data.

EBEA

RESERVED

ENABLE EBOX MICRO TRAP LOGIC
EBD3

ETRAP

Enables the EBox microtrap mechanism.

This in turn allows

CPU error reporting.
<13:11>

MICRO TRAP PRIORITY
EBDE UTRP <2:0>

LEVEL

the

This field indicates the priority of
'

request.

Pricority

last

microtrap

Microtrap Type

EBox Read/Write Microtrap
OP Write Microtrap
IBox Error Microtrap
Misc Microtrap
Fork Microtrap

IMD Read Microtrap
ID Read Microtrap
STRING Read Microtrap

<10>

OPBUS SOURCE
EBD5 SRC

(0=ID/1=IMD)

IMD LVL3

When set,
This bit is only valid when IBESR <09:08> = 3.
this bit indicates that the OPBus came from IMD register.
When cleared,

indicates that the OPbus data

came

from

ID register.
<09:08>

UOPSEL <1:0>
EBD5 UOPSEL <1:0>
This field indicates
<1:0>
0

3
<07:03>

<02>

Data

the OPBus data

source.

Source

IBox Register Select
Operand Source is EMD

Operand Source

is IBUFFER

Operand Source is IMD or ID Registers
(See Bit

10 above)

RESERVED

ESA VALID

This bit is set by the EHM if the IBox ESA

VALID

bit

VALID

bit

valid

bit

set.

<01>

ISA VALID

This bit is set by the EHM if the IBox ISA
set.

<00>

CPC VALID

This bit is set by the EHM if the IBox CPC
set.

20-69

VAX 8600/8650 REGISTER DESCRIPTION
IBGPR

IBGPR

(ADDRESSED BY NAME FROM CONSOLE ONLY)

{BOX &PR ADDHESS

)

PRINT LOCATION: iCB8

iBOX GPR ADDRESS

NOTE: BITS <3:0> ARE READ ONLY
MB-1537%

<03:00>

1IBOX GPR ADDRESS
Lines are generated
by
the
IBOX
(Print:ICBB)
distributed
to
the
EBOX
(Print:EDPC)
and
(Print:FAl2) when OPTIMIZATION is
done.
Note

IBGPR
within

and
are
the
FBOX
that
the
lines
are
also latched and distributed internally
the IBOX to perform a variety of functions.
NOTE

The
the

IBGPR register
following

>>>EXAM

The
the

(read only)

console

IBGPR address lines are
SDB
visibility
bus
on

ICBB

and

are

FBA module).

BIT

accessed

via

also available
(all
signals

are

IBGPR<cIr>

generated

IBGPR

command:

SIGNAL

NAME

SDB

terminated

SYMBO

B/P

ICB

IBGPR

2
1
0

ICB

IBGPR 2
IBGPR 1
IBGPR 0

Vv$0108

ICB

ACl12A54

V$0118

AC12A71

V$0119

AC12A60

ICB

20-70

on
the

PIN(ICB)

V$0187

AC12A60

VAX

8600/8650

DESCRIPTION

ICCs

INTERVAL CLOCK CONTROL AMD STATUS REQISTER
22

ilNTERHUPT
<31>

INTERRUPT
ENABLE

set

via

MTPR

clears

then
An

ERR

attempt

ERR.

zero.

hardware

then

this
tick

bit

every

time ICR overflows.
If
IE
1is
set
1is also generated.
An attempt to set
clears INT, thereby reenabling the clock

interrupt

via MPTR
interrupt (if

set).

INTERRUPT ENABLE
When set, an interrupt request at IPL 18(16) is
generated
every
time
ICR
overflows
(INT is set).
When clear, no
interrupt is requested.
Similarly, if INT is already
set
and the software sets IE, an interrupt is generated [i.e.,
an interrupt is generated whenever the
function
(IE
and
INT)
changes from 0 to 1].
At bootstrap time this bit is
cleared.
SIGNAL

A write

set,
<04>

bit

INTERRUPT

Set

<05>

this

MBZ

Must

<06>

ERROR

<07>

SIGNAL l TflAHSFEfll

Whenever ICR overflows, if INT is already set,
set.
Thus, ERR indicates a missed clock tick.

<30:08>

ICR

only bit.
If RUN is clear,
is incremented by one.

TRANSFER
A write only

NICR
<03:01>

MBZ

<00>

RUN

Must

bit.
Each time
transferred to ICR.

zero.

each

time

written

this

bit

this

bit,

When set, ICR increments each
microsecond.
When
clear,
ICR
does not increment automatically.
At bootstrap time,
RUN is cleared.

20-71

VAX

8600/8650

ICR

IPL
ISASAV

INTERYAL COUNT REGISTER
34

227

<31:00>

08B

INTERVAL COUNT
The interval register is a read only register
incremented
once
every
microsecond.
It is automatically loaded from
NICR upon a carry out from bit 31
(overflow)
which
also
interrupts at IPR 18(16) if the interrupt is enabled.

1PL

INTERRUFT PRIGRITY LEVEL

PR 12

330

11 10

INTERRUPT

PRIORITY LEVEL

sAR
- TIDET

<31:05>

MB2Z
Must

<04:00>

INTERRUPT

zero.

Writing

PRIORITY

the

LEVEL

IPL with

the MTPR

instruction will

load

the

processor
priority
field
in the Program Status Longword
(PSL), that is, PSL <20:16> is loaded
from
IPL
<04:00>.
Reading
from
IPL with Lhe MFPR instruction will read the
processor priority field from the PSL.
On
writing
IPL,
bits
<31:05> are ignored, on reading IPL bits <31:05> are
returned

zero.

ISASAY

180X STARTING ADBRESS SAVE REGISTER

{ESUHAIUH LUG: 23 — 113

PC OF THE INSTRUCTION THE 1BOX ADDRESS CALCULATION UNIT IS CURRENTLY PROCESSING
3

<31:00>

CURRENT PC

This

]

FOR ADDRESS

instruction

currently

that

the

]

CALCULATION

the

1IBox

processing.

20-72

]

UNIT

address

Address

(Macro

PC)

Calculation

Unit

the
is

VAX 8600/8650 REGISTER DESCRIPTION
ISP
IVASAV

KSP

INTERRUPT STACK POINTER

o, I8P
N

IPR 04

VIRTUAL ADDRESS OF TOP OF STACK (AT INTERRUPT LEVEL)

VIRTUAL ADDRESS OF TOP OF STACK

<31:00>

Unlike

This is the stack pointer for the interrupt stack.

for process context stacks, which are

pointer

stack

the

]

[

04 03 02 O1 OO

O6 05

10 09 08 07

13 12

7 & 5

2 21

2B 2% 24 23

a0 29

stored in the hardware PCB, the interrupt stack pointer is

Refer to PSL to determine
stored in an internal register.
The ISP is in use if we
which SP is currently being used.
<26>, Interrupt Stack, is
PSL
in Kernel mode and if
are
set.

VIRTUAL ADDRESS SAVE REGISTER

VASAY

{ESCRATCH LOC: 20 — T10)

2 25

1BOX VIRTUAL ADDRESS FOR: OPERAND (0P PORT) FETCH AND RESULT STGRAGE

FI |

]

(08 07

MR- 13807

' IVASAV (IBox Virtual Address Save) - This register contains the
last virtual address that was calculated by the Address Calculation

IVASAV
Therefore,
Unit and acknowledged by the MBox with PA ACK.
will contain the Virtual Address associated with either the current
operand fetch cycle, or the current result store cycle.
Operand Fetch or Result Store.

either

for

1IBox

the

used

Last Virtual Address

<31:00>

KERNEL STACK POINTER

KSP
PR 00 (ESCRATCH LOCATION: E0)

313fl29282??5252423222‘!2%31938‘!755153413121%%GBSGSQTG%@SN@G?G?W
VIRTUAL ADDRESS OF TOP OF STACK (KERNEL MODE)

[

]

§
MB-I0955

<31:00>

KERNEL STACK POINTER

Contains the stack pointer to be

access

Mode)
.

mode

field

the

20-73

PSL

used

when

the

current

1is 0 and IS = 0 (Kernel

VAX 8600/8650 REGISTER DESCRIPTION

USART RECIEVE HOLDING REGISTER
USART STATUS REGISTERS

USART RECEIVED HOLDING REGISTER
175400

LRHR

LOCAL RECEIVED HOLDING REGISTER

175410 RRMR

175420

REMOTE RECEIVED HOLDING REGISTER

ERHR

EMM RECEIVED HOLDING REGISTER

CL1o

RECEIVED CHARAGTER
]

]

ALL BITS READ ONLY

<07:00>

RECEIVED CHARACTER

When

complete

serial

line,

character

has

been

received

the

USART

it is moved from the USART shift register to

the USART Receive Holding Register.

USART STATUS REGISTER
175402

175412
175422

LRSR

RRSR
ERSR

LOCAL READ STATUS REGISTER (USART)

REMOTE READ STATUS REGISTER (USART)
EMM READ STATUS REGISTER {USART}

_ 07

CLig 1y

FRAMING | overuN | PaRTY | DEVICE | mecewe [ransmir

ERROR

| ERAOR

ALL BITS READ ONLY

|READY

<07:06>

RESERVED

<05>

FRAMING

<04>

ERROR | STATUS | eapy

MA-

ERROR

Indicates that
by the correct

the character just received was
number of stop bits.

OVERRUN ERROR
Indicates that

a data

program

before

the

the Receive Holding

character was not read
next one was assembled
Register.

<03>

PARITY ERROR
Indicates that bad parity was

received.

<02>

DEVICE STATUS CHANGE
The transmitter has completed

serialization

Transmit

state.

<01>

<00>

Holding

not

framed

by
and

the
7T-11
loaded in

character

or DSR or DCD have changed

RECEIVED READY
RXRDY indicates to the T-11 program that
USART holding register to take the data.

it may

read

the

TRANSMIT READY
TXRDY is set by the USART, signifying that
the
USART
is
ready
to
accept
the
character.
This generates a T-11
interrupt request.

20-74

VAX

8600/8650 REGISTER DESCRIPTION
USART TRANSMIT HOLDING REGISTERS

USART TRANSHIT HOLDING REGISTER

175401
175411
175421

LTHR
RTHR
ETHR

LOCAL TRANSMIT HOLDING REGISTER
REMOTE TRANSMIT HOLDING REGISTER
EMM TRANSMIT HOLDING REGISTER

CL10,11

CHARACTER T0 BE TRANSMITTED
3

NOTE:
ALL BITS WRITE ONLY
MR-34I8T

The T-11 program loads the character in the USART
Transmit
Holding
Register.
TXRDY is negated.
When the character previously loaded
(if any) has
been
transmitted,
the
character
is
moved
to
an
internal
shift
register and transmitted on the serial line.
When
the character is moved
to
the
shift
register,
TXRDY
1is
again

asserted,

and

ready

indicating

that

another

the

transmit

character.

20-75

holding

empty

VAX 8600/8650 REGISTER DESCRIPTION
USART COMMAND REGISTERS

USART COMMAND REGISTER
175407 LWCR
175417 AWCR
175427 EWCR
175406 LRCR
175418

RACR

175426 ERCR

LOCAL WRITE COMMAND REGISTER
REMOTE WRITE COMMAND REGISTER
EMM WRITE COMMAND REGISTER
LOCAL READ COMMAND REGISTER
REMOTE READ COMMAND REGISTER

l SUBMODE
i

NOTE:

address
<07:06>

lm ssunl RESET |Lm
CHARACREQUEST

SEND
BREAK

ERROR

One address
to

read

the

RECEIVE
ENABLE

DATA
TERMINAL

TRANSMIT
ENABLE

READY

MR.18192

is used to write a command register and
same

another

SUBMODE
00

= Normal
= Auto Echo
= Local Loopback
= Remote Loopback

01
10
11
<05>

cLign

EMM READ COMMAND REGISTER

REQUEST TO SEND
For the
remote

(RTS)
1line

only,
Request
To
Send
(RTS)
asserted
1in
the
USART Command Register.
This signal
set by the T-11 program when
it
is
ready
to
place
answer

<04>

call

the

ERROR RESET (ER)
The setting of this

remote

bit

is
or

line.

clears

the

Parity

Error,

Overrun

Error
and
Framing
Error bits (Read Status Register bits
<05:03>).
Error Reset
must
be
performed
when
Receive
Enable

<03>

<02>

set.

SEND BREAK CHARACTER (SBRK)
This is a programmable bit and when set, the output
USART
transmitter, TX DATA, goes to a logical zero
This condition will generate a continuous
spacing
to
be
asserted.
wWwhen
this
flag
1is
cleared,
operation is exercised.

RECEIVE ENABLE
0
1

<01>

of the
state.
signal
normal

(RXEN)

= Disable
= Enable

DATA TERMINAL READY

(DTR)

For the remote line Data Terminal Ready (DTR)
in the USART Command Register.
The T-11 sets

is
asserted
DTR when the
remote line is enabled by the switch on the system control
panel.
DTR
enables
the
modem
to
receive
a call and
indicates that the USART is ready to accept data.

<00>

TRANSMIT ENABLE
0

Disable

Enable

(TXEN)

20-76

VAX 8600/8650
USART
USART MODE REGISTER
i
175405
175415
175425
175404
175414

LWMR
RWMR
EWMR
|RMR
RRMR

175424

ERMR

LOW-ORDER MODDE REBISTER BITS

L0 CAL WRITE MODE REGISTER
REMOTE WRITE MODE REGISTER
EMM WRITE MODE REGISTER
LOCAL READ MODE REGISTER
REMOTE READ MODE REGISTER

{FIBST ACCERS)

CL10.11

EMM READ MODE REGISTER

NUMBER OF

l PARITY
EVEN | ENABLE
PARITY

STGPVBITS

<07:06>

GHARACTER
LENGTH

MODE
AND
BR FACTOR

]

STOP BITS

Invalid

*01 =

Stop Bit

Stop

Bits

<05>

EVEN

<04>

ENABLE

<03:02>

CHARACTER LENGTH

<01:00>

PARITY

00
01

Bits

*11

Bits

= 8 Bits

MODE

BR FACTOR

Sync.1lX

*01 = Async.1lX
11

NOTE:

Async.64X

= NORMALLY USED VALUE

20-77

MODE

LOW ORDER

vAX 8600/8650 REGISTER DESCRIPTION

USART MODE REGISTERS, HIGH ORDER

HIGH-OROER MODE REGISTER BITS

USART MODE REGISTER
175415 RWMR

MODE REGISTER
LOCAL WRITE
WRITE MODE REGISTER

175414 RRMB
175424 ERMR

REMOTE READ MODE REGISTER
EMM READ MODE REGISTER

LWMAR
175405
,

175425 EWMB
175404 LBMR

{SECOMR ACCESS) £L10, 11

REMOTE

EMM WRITE MODE REGISTER
LOCAL READ MODE REGISTER

LOCK

TRANSMIT

CLOCK l
RECEIVE

INTERNAL BAUD RATE
BAH- 18154

NOTE:

ALL BITS ARE READ/WRITE

<07:06>

RESERVED

<05>

TRANSMIT CLOCK

Selects the source clock for the transmit frequency where:
1
0

Internal
External

clock
clock

If set to 0, External clock, the External USART clock is
used as transmit frequency. The baud rate is selected via

The External baud rate must be the same for
bits <03:00>.
If set to 1, Internal clock, the
transmit and receive.
The standard
clock source is Internal (pin 9 of USART).
1Internal clock for CTY and E-ETERM, External
1is
setting
clock

<04>

for RTY.

RECEIVE CLOCK

Selects the source clock for the receive frequency where:
1 = Internal clock
0 = External clock

If set to 0, External clock, the External USART clock 1is
used as receive frequency. The baud rate is selected via
bits <03:00>. The External baud rate must be the same for
If set to 1, Internal clock, the
transmit and receive.
The standard
clock source is Internal (pin 9 of USART).
setting 1is Internal clock for CTY E-ETERM, External clock
for RTY.

20-78

VAX

B8600/8650

USART

<03:00>

INTERNAL

BAUD

MODE

HIGH

ORDER

RATE

If Internal baud rate is selected via bits
bits <03:00> determine the frequency (baud

BITS
<03:00>

<05>
or
rate).

<04>,

BAUD RATE

0000

50
75
110
134.5

0001
0010
0011

0100
0101

150
300
600

0110
0111

1200
1800
2000
2400
3600
4800
7200
9600
19.2K

1000
1001
1010
1011
1100
1101
1110
1111

The default

setting

CTY:

3E(X)

ETERM:

3E(X)

RTY:

07(X)

for

these bits

are

follows:

NOTE

Each

the

USARTS

the
console
module
has
a
mode
register,
one for each port:
local
(CTY), remote port (RTY)
and
the
EMM
port

16-bit

port

(ETERM) .

addressing
access

Access
an

addresses

the second
<15:08>.

to this

8-bit

access

addresses

20-79

twice.

low-order

the

bits

The

first

<07:00>

high-order

and

bits

VAX 8600/8650 REGISTER DESCRIPTION
MAPEN

MCCTL

MAPEN

MEMORY MANAGEMENT ENABLE

iPR: 38

068

0283

MR —13956

Memory Management Control - The action

translating

virtual

address
to
a
physical
address is governed by the setting of the
MEMORY MAPPING ENABLE (MME) bit in
the
MAPEN
Internal
Processor
Register.
<31:01>

RESERVED

<00>

MME

When MME, the MEMORY MAPPING
ENABLE
BIT
1is
memory
management
is
enabled.
When
MME
memory

management

initialization time,

disabled.

MAPEN

processor

initialized to 0.

MELTL
31

set
to
1,
1is set to 0,

MBOX MCC CONTROL REGISTER
30

28 -

,,,,

DIAG WRITE COMMAND/MASK
2

<31:14>

On a write to the MBox (MTPR)

<13:12>

DIAGNOSTIC WRITE LENGTH/STATUS <1:0> H
When the MBox is using the ABUS in
diagnostic
mode,
the
bits
stored
in
these
1locations are substituted for the

on a read

(MFPR)

these bits must be zero, but

they will be undefined.

normal data length/status bits when
writing
to
the
1I/0
adapter
register
file.
They
are
used for diagnostics
only.

<11:08>

DIAGNOSTIC WRITE COMMAND/MASK <3:0> H
When the MBox is using the ABUS in
diagnostic
mode,
the
locations are substituted for the
these
in
stored
bits
normal command/mask bits when writing to the
I/0
adapter
register file.
They are used for diagnostics only.

<07:02>

RESERVED

01>

SLOW ARRAY ACCESS MODE

when set, memory access time from the array is
repeatable
(and
slow).
This is for diagnostic reasons.
The access
time is greater than
the
normal
access
time
plus
the
refresh

<00>

time.

INHIBIT MEMORY OVERLAP

When set, memory overlap is inhibited [i.e., not
starting
another array read unless the data from the previous array
read has been
extracted
from
the
array
register
file
(DC109)].
This
is
needed if the clock is to be stopped
and continued.
This is also used to do single step on DMA
transfers by affecting DMA done.

20~-80

VAX

8600/8650

REGTSTER DESCRIPTION
MCSRO

MCSRO

MISCELLAKEOUS CONTROL/STATUS REGISTER D
CLOS (W), CLOB (R)

176040

o7
HOLD
STATE
RESET

NOTE: READ/WRITE

<07>

pusLe
INTERUPT

PROM 1

MAP

HOLD STATE

NABLE

INTERUPT

RESET

CL09 HOLD STATE RESET H
Initialize the VAX CPU
information.
<06>

CL04

CLK

but

not

clear

error

status

CLO4 CLK PE H
Qutput of
parity
error
F/F.
Clocks
PECAS
and
PERAS
registers
during
normal
operation.
When
1in
the test
bench, the T-11 may set CL09 DIAG TRIGGER,
which
may
be
used

<05>

<04>

scope

trigger by

FORCE PARITY ERROR
CL09 FORCE PE H
Write bad parity in
ENABLE

ENABLE

<02>

RAM.

PROM.

MAP

CL09 ENA MAP H
Enable virtual
RAM

the T-11

diagnostics.

PROM S1

CL0O9 ENA PROM S1
Select upper 4KB of
<03>

console

address

to physical

address

translation of

by paging

(mapping)

RAM.

FLAGS ENABLE
CL0O9 ENA CPU FLAGS H
Enable console (T-11)

interrupt

requests

VAX

CPU.

Enable

VAX

CPU

interrupt

ENABLE

TOY

<00>

T-11

Clock

every

ENABLE

T-11

CL09

interrupt

the

;

requests

generated

requests

1 ms.

Time

INTERRUPT

ENA TOY INTR
H
T-11 interrupt

Enable

generated

INTERRUPT

CL09 ENA TOY INTR H
Enable

T-11

generated

requests

the console.
<01>

the

20-81

the

T-11

program.

Year

VAX 8600/8650 REGISTER DESCRIPTION
MCSR1
.

MLsAl

MISCELLANEOUS CONTROL/STATUS REBISTER 1

176041

TeRGPT

CLO9 (W), CLOB (R}

08
RTERM

ENABLE | DSRS

csM

cPu_

QMAINT

ERABLE l RESET lEaAaLE N1 l o

SIMULATE

REQUEST

CPU

ERROR

ENABLE l
l ABUS
| MEM BUS | ADAPTOR
iiiiiii

<07>

RTERM INTERRUPT ENABLE
CL09 TERM IE H

Enable T-11 interrupt request

generated

remote

receiver ready condition or change in modem status.

<06>

RTERM DSRS
CLUY9 RTERM DSRS H

Enable some remote line modems
(split)

<05>

operate

transmit and receive baud rates.

1line

different

SIMULATE CPU ERROR
CL0O9 SIM CPU ERROR H

Force T-11

interrupt request normally generated by VAX CPU

control store parity error.
<04>

CSM REQUEST ENABLE
CL0O9 CSM REQ ENA H

Request that the VAX CPU microprogram in

the

EBox

enter

console support microcode.

<03>

CPU

RESET

CL09

CPU RESET

Initialize VAX CPU (master reset).

<02>

MEMORY BUS ENABLE
CL09 MEM BUS ENABLE H

Enable main memory array to respond to read/write requests

<01>

the MBox.

ABUS ABORT INITIALIZE
CL09 ABUS ADAPT INIT H

Initialize SBIA and ABus devices.

<00>

ENABLE QMAINTENANCE CLOCK
CL09 ENA QMAINT CLK H

Enable alternate clock source (SDB clock) for

QBus RPLY timeout counter.

20-82

testing

VAX

8600/8650

DESCRIPTION
MCSR2

MCSR2

176042

MISCELLAKEDUS CONTROL/STATUS !58]8?53{%

RIW

~ABUS REQUEST <3:0> H

RIW

07>

<06>

SYSTEM AC FAULT
CL09 SYS AC FAULT H
Latched AC LO indication from EMM.
simulate AC LO for test purposes.

VAX

CPU ALIVE
CPU

IRD.

written

executing

Bit

determine

1is

another

«cleared

that VAX

CPU

instruction.

and

Set

rechecked

program

EBox

periodically

running.

REPLY TIMEOUT

CL30

RPLY

RPLY TIMEOUT H

was

not
received
on
operation.
T-11 program is

<04:01>

Bit may

CPU ALIVE

CL09

<05>

oo
ABUS

QBus

during

OQBus

read/write

interrupted,

-ABUS REQUEST <3:0> H
ABUS REQ H <03:00>

-CL09
VAX

CPU

restart

adapters.
connected)

requests

restart

processor.

from

state.

- <00>

system's

request
Bits

are

four possible
ABus
originates from another (CI
asserted

when

the

=zero

ABUS

DEAD INTERRUPT
CLO9 ABUS DEAD INTERRUPT H
Latched VAX CPU restart request
system's

bits

four

possible

ABus

from one
adapters

<04:01>).
The
console
T-11
interrupted.
Bits
may
be written
for test purposes.

20-83

(such

of
the

the
OR of

<01>
program
is
to simulate ABUS DEAD

VAX 8600/8650 REGISTER QESCRIPTION
MCSR3
MC3R3

MISCELLANEGUS CONTROL/STATES REGISTER 3 (BE&JBA

176043

o7
~CPU
ACLO

‘

(READ)

— ERROR H

CONSOLE IDENTITY
2

—CPU
CONTROL

STORE PE

NOTE: READ
MET4EIT

<07>

-CPU AC LO H
-EMM3 CPU AC LO H

Indicates that AC
AC LO is unlatched from the the EMM.
power has dropped, but not enough to cause loss of DC
power. DC LO, QCSR3, indicates that software operation is
unpredictable.

<06:04>

CONSOLE IDENTITY <0:2>
CL09

ID <0:2> H

Console identity bits programmed at backplane to establish
These bits
access privileges on EMM multi-drop bus.
drawing
originate from backplane jumpers (see CL12 and and
read
BD-L0201-0-BPC). Currently these bits are unused
as 0's (jumpers out).

<03:01>

-ERROR <2:0> H
-CL09 ERROR <2:0> H

Complement of error code from EBOX specifying type of
control store error condition in the VAX CPU. These
the
signals originate on EBE3 and are transmitted to VAX
console module (print CL09). Used by the console for
CPU CS error correction and reporting:
R

==
. o

2-FBOX ADDER CS PE

3-FBOX DRAM PE
4-1BOX DRAM PE
5-IBOX CS PE

.
%

<00>

3£}

6-EBOX CS PE
7=NO ERROR

0-MBOX CS PE
1-FBOX MULTIPLIER CS PE

-CPU CONTROL STORE PARITY ERROR H

CL0% CPU CS PE L

This bit indicates that a CPU control store parity exists
and will interrupt the console program at vector 110.
This signal is asserted if any of the control store parity
errors specified by bits <03:01> exist, or if SIMULATE CPU
for
The latter is
ERROR, MCSR1 bit <05> is set.
diagnostic purposes only.

20-84

VAX

MC3RI

DESCRIPTION
MCSR3 (WRITE)

MISCELLANEOUS CONYROL/STATUS REGISTER 3 WRITE

176043

! §§T

TSTAT

8600/8650

CLEAR

TIMEOUT |

02_

CLEAR

TSTART

NOTE: WRITE

A write to MCSR3 enables
diagnostic functions.

<07:05>

decode

DAL<07:05>

provide

FUNCTION
The

following

bits
0.

functions/operations are performed when
the
in this field equal an octal 7, 6, 5, 4, 3,
2, 1, or
Note:
Only one function can be performed at a time,

SET TSTRT

Set

(CMISC<6>),

TSTRT

VAX CPU.

SET

PARITY

Sets

the

bad

parity

simulates

Generates

ERROR

parity

T-11

the

console

interrupt

CLEAR TIMEOUT

the

indicator

T-11

RAM.

simulate

Generates

(MCSR2<5>)

CLEAR TSTRT L
Clears
TSTRT
(CMISC<6>)
interrupt request.
SET

TIMEOUT

the

STOP

Timeout

CLOCK

(MCSR2

the

SDB

CLEAR TOY

INTERRUPT

Clear

T-11

and

the

corresponding

the

corresponding

T-11

<5>).

QBus.

Simulates

Generates

a T-11

interrupt

clocks.

L
interrupt

Year Clock.
CLEAR PARITY

of
interrupt

generation of

the

detection

T-11

and

request,

SET

Timeout condition on

Stop

request

Clears the Reply Timeout
T-11 interrupt request.

Set

reboot

request.

L
error

request.

request

generated by

the

Time

the T-11

RAM

ERROR L

Clear the T-11
parity error.
<04:00>

interrupt

request generated by

RESERVED

20-85

VAX 8600/8650 REGISTER DESCRIPTION
MDCTL
HICTL

#00X BATA CORTROL

PR 45

BAD DATA

<31:15>
<14>

<13>

11>

EMBLE

NVERT

REGiSTEE

CACHE
BYTE

On a write to the MBox (MTPR) these bits must be zero, but
on a read (MFPR)

they will be undefined.

INHIBIT DATA PARITY ERROR CHECK

PARITY
DATA
CACHE
When Set, MD BUS WRITE PARITY ERR and
ERR errors will not be detected or reported by the MBox.
DIAGNOSTIC CHECK RAM READ

Cache

When set, check bits will be read from the selected

RAMs.

<12>

ECE 08

DATA

This function will only be used by diagnostics.

RESERVED

INHIBIT BAD DATA FLAG

When set, will inhibit the bad data code check bits being
for a description of the BAD DATA
MDECC
See
generated.
CODE.

<10>

DISABLE ECC ON DATA

When set, ensures that no correction takes

the

CHECK

BIT

place

data. Error information will still be logged and reported
in register
unless INHIBIT ERROR REPORTING bits are set
MERG.

<09>

ENABLE INVERT REGISTER

when set, allows the data stored in

the

DATA

INVERT REGISTER to complement the check bits generateé on
The check bit invert bits are in register
any write data.
Also allows bad ABus parity to be generated for
MDECC.
DMA array reads if MDECC <0> had been written.

<08>

ENABLE CACHE BYTE PARITY ERROR

Cache

When set, allows bad byte parity to be written into

as determined by CACHE PERR <03:00>
from a CP request
invert
the MBox will
Once this bit is enabled,
bits.
After the first request the
parity for one MBox request.
take
bit will stay set but no more parlty inversions will
place.
To enable a second parity inversion the ENA CACHE
BYTE PE bit must be reset, then set.

To invert byte parity in Cache,

BYTE

PERR

the incoming data.

This

the ENA

CACHE

bit must be set along with ENA CACHE PERR <03:00> and INH
If the INH DAT PERR CHK is not set the MBox
DAT PERR CHK.

will

detect

parity

errors

function can be used to produce WRITE DATA PARITY

ERRORS,

<03:00>

RESERVED

ENABLE CACHE BYTE PARITY ERROR

When set in conjunction with ENABLE CACHE
generate

even

parity

BYTE

PE,

will

on byte <03:00> belng written into

the Cache during CPU longword writes. This is also used
to generate single longword failures for CPU ABus write.
20-86

VAX

8600/8650

DESCRTIPTTON

MDECC
MOECC

MBOX DATA ECC REGISTER

(ESC 27-T17) IPR43

{BAD OATA | SINGLE | DOUBLE | yppess

DETECTED | ERROR | Fmmom | PE
15

NVERT

ECC DATA CORRECTION SYNDROME

BUS
L ONGWORD

ARITY

MDECC

(MBox

Data

ECC

three

MBox

DIAGNOSTIC ECC CHECK BIT INVERT

§§§§gus

ONGWORD

¢1

ARITY
MR

Status

registers;

(byte

2),

<31:24>

Reserved

<23:16>

Source:

MCDM

Held

(ECC)

ECC4

ERR HLD and

23>

<22>

at:

MBox

This

(byte

Reg

and

(DATA

ECC

into

the

T2D

made

(byte

0).

ERROR)

Reserved

BAD

DATA SYNDROME

ECC4
The

DETECTED

BD ERR (MCDM)
bad
data
bit

generation

either

whenever

XORed

"known"

the

bad

data

ECC
is

check

bit

written

into

cache or the array.
A read
to
that
1location
will
vresult in the detection of a Bad Data code
and cause
this bit to be set.
Note that to
read
check
bits
from

<21>

<20>

cache

invoke

the

check

SINGLE

BIT

ERROR

ECC4

The

data

bit

(ECC

The
bit

<18:16>

byte

bit

parity

error must

read.

have

been

found

ERR

(MCDM)
word read

from cache
correctable) error.

or main memory

had

single

BIT ERROR
DB ERR (MCDM)
data word read from cache or main memory had
error or a detectable multiple bit error.

double

ADDRESS

PE
ECC4 AP ERR (MCDM)
The word fetched from memory was either
written
or
read
from
the wrong location.
The ECC code indicates that the
parity of the
address
written
and
the
parity
of
the
address
read
from
are different.
ECC is generated over
the data bits and a parity bit computed over
the
physical
address bits <29:04>.

110
ECC2 DATA <33:32> (MCDM)
These
bits
should
always
return
as
a
binary
Therefore,
this
field
position
can be used as a
confirm the location of MDECC in a Stack
Frame.

<15:08>

115>

DOUBLE

ECC4

<19>

cache

Source:

MCDM

Held

ECC4

at:

INVERT ABUS

ECC3
When

(ECC) MBox
ERR HLD

LONGWORD

Reg

longword parity.

set

SYNDROME)

PARITY

LWP INVERT REG (MCDM)
this bit is set, and bit

Control

(DATA

110.
Key to

the

20-87

ECC

<01>

MCA will

generate

10
bad

(Data
ABus

13335

VAX 8600/8650 REGISTER DESCRIPTION

MDECC

56 2

(ESC 27-T17) IPRA3

/’

15
TNVERT
ABUS

i ONGWORD
PARITY

<14:09>

28 _

ng
,égf
% ?’:

10
11
12
13
ECC DATA CORRECTION SYNDROME

02, Oi

o, e

%
%

o7
)

SINGLE | DOUBLE

83
04
05
DIAGNOSTIC ECC CHECK BIT INVERT

MBOX BATA ECC REBISTER
17

o
NVERT
\RRY BUS

ERROR | ERROR

LONGWORD
ARETY

ECC DATA CORRECTION SYNDROME
ECC3 SYN REG <32:1> (MCDM)

ECC3 SYN REG <32:1> (MCDM) = This field corresponds to the
syndrome generated by the ECC chip and indicates the
failing

number.

(MSB)
(LSB)

70
07

0421000 66666655555444443333322222111111
0000421 65432132654654326543265432654321

DATA BIT

(MSB)

CCCCCCC 33222222222211111111110000000000

<08>

Reserved

<07:00>

Source:

<07:01>

bit

SYNDROME
IN OCTAL

(LSB)

0654321 10987654321098765432109876543210

MCDM (ECC) MBox Reg 50 (DATA CHECK INVERT)

DIAGNOSTIC CHECK BIT INVERT <CP:Cl>

ECC3 <CP:Cl> INVERT REG

When

set

the

(MCDM)

corresponding

ECC

check

bits

will

inverted.

<00>

INVERT ARRY BUS LONGWORD PARITY
ECC3 LWP INVERT REG (MCDM)

When this bit is set, and bit <01> in Register 10 (Data
is set, then the longword parity generated on
Control 2)
ARRAY BUS data will be inverted when the ECC MCA is the
This bit is write only and is read via bit
check mode.
<15> in MDECC (MBox Register 60).

20-88

VAX

8600/8650

DESCRIPTION
MEAR

MEDR
MEAR

MEMORY ERROR ABDRESS REGISTER

{ESCRATCH LOG: ZA-TIA)
31

3§

PHYSICAL ADDRESS <29:02> IN PA LATCH WHEN MBOX ERROR WAS DETECTED

]

[

///

| AP

This is a copy of MAP1/3 (ADA/ADB) MBOX REG 7C
(ERROR
ADDR).
It
contains
the
physical address present at the output of the PA Mux
when the MBox detected an error.
Interpreting this address depends
on
the
MBox
Data
Destination Code
Cycle Type (MSTAT1 <29:26>).

CP initiated
(Non
1/0)
contain
the
address
of
the error unless:
CP

REFILL or WRITEBACK

Cache
;

Retill

<25:24>

the

address

error.

contains
€rror.

MSTAT

Cycle,

(Longword

the

(The

the

<A3:A2>)

1longword

<25:24>

address

Otherwise,

<25:24>

you

determine

Initiated

I/0 Read/Write

initiated

I/0 Cycles.

Initiated

<A3:A2>)
that was
MEAR

the
octaword).

must

that

was

then

the

MEAR

to be

MSTAT1

MEAR

caused

to
determine
associated with the
<03:02>

then

associated
MEAR

MEAR

with

<03:02>

not

valid

the
with

for

any

MEAR
will
contain
the
processed (i.e., longword,

<25:24>

contains

the
If

(Longword
Count
address of the longword
MSTAT1
<25:24>
equal

the

address

the

longword

Otherwise, you must substitute MEAR
to determine the address.

MEER
29

either

Then MSTAT1

MEMORY ERROR BATA REGISTER

{ESCRATCH LOC: 28 — T18)

MBox

address.

Cycles
data

associated with the error.
<03:02> with MSTAT <25:24>

the

used

MEAR

substitute

must be used to determine
associated with the error.

<03:02>

and

Cycle).

longword

Cycles

Read/Write

address

quadword,

the

must

starting

request

equal

ABus

a Cache Writeback

Count

of
MSTAT1

<31:30>)

Read/Write
Operations
MEAR
will
the longword that was associated with

(MSTAT1

DATA WORD BEING PROCESSED BY MBOX WHEN THE MBOX ERROR WAS DETECTED
i

]

]
MR- 13913

This is a copy of MCD1/3 (MDP) MBOX REG 78
(DATA
ERROR).
only valid (held) for ABus Parity Errors (DMA Data PEs and

PEs

only),

data word

ABus

BDC

latched

Errors,

the

and

CPU

Write

MCD MCAs when

20-89

the

It
is
CPU Read

PEs.
It
contains
error occurred.

the

VAX 8600/8650 REGISTER DESCRIPTION
MENA
MBOX ERROR ENABLE

MENA

IPR: 44

- %

%
13

MBOX 18 ERROR REPORT ENABLE

MBOX STATUS REPORT ENABLE

ABUSADR
s
B CTL s
Olikwe ABUS
Ncennne conare, ABUS

MBOX DATA ERROR REPORT ENABLE

WRBYTE
WRBYTE WRBYTE
WRBYTE CACHE
./
DATAPE
OPE
1PE
2PE
TAGPE | 3PE
VALIDPE PTEBPE PTIEAPE

CACH BYT
WRITE PE
(LN

from
bits
status
the
these bits are reset, they only prevent
they do not prevent the error from being reported,
1latched,

being

the trap still occurs.

what

appears

corresponding
<31:24>

error

If these bits are reset, software will

spurious

traps

interrupts

1if

see

the

detected.

On a write to the MBox (MTPR) these bits must be zero,
on a read (MFPR) they will be undefined.

<23:16>

MBOX STATUS REPORT ENABLE
Enable value = F8 HEX.

<23>

CPR B

PARITY

ERROR

22>

CPR A PARITY

ERROR

<21>

ABUS

DATA

<20>

ABUS

CONTROL

PARITY

ERROR

PARITY

ERROR

PARITY

ERROR

<19>

ABUS ADRRESS

<15:12>

RESERVED

<11:08>

MBOX TB ERROR REPORT ENABLE

<11>

VALID PARITY ERROR

<10>

PTE B PARITY ERROR

<09>

PTE A PARITY

<08>

TAG PARITY

<07:00>

MBOX DATA ERROR REPORT ENABLE

<07>

WR BYTE

PARITY

ERROR

<06>

WR BYTE

PARITY

ERROUR

<05>

WR BYTE

PARITY

ERROR

<04>

WR BYTE 0

<03>

CACHE

<02:01>

RESERVED

<00>

CACHE BYTE WRITE PARITY ERROR

ERROR

PARITY ERROR

DATA PARITY

ERROR

20-90

but

VAX

8600/8650

MERG

MBOX ERBOR RENERATION WORD

(ESCRATCH LOC: 28 — T18) iPR: 47
31

328

IREPOF:?S l N PROG

MEMORY
MGMT
ENABLE

ARRY SBE

02
ot
GENERATE EVEN PARITY

ADDRESS
M
VA DIAG

CACHE

00
o

CACHE

TBTAG . TBVALID . _WBIT

PHISICAL

TAG _, ADDRESS
@R -13623

MERG
MBox

(MBox

Error Generation Register) registers 18 (byte 1) and 14 (byte

<31:16>

<15:08>

<12>

<11>

Source:

MCCJ

(CRB)

MBox

Note:

This

field

DMA

REQUESTS

Reg

set

(MCC

the

Control

Reserved
INHIBIT
MCCJ

INH

When

set,

DMA

REQ

the Mbox will

not

honor

any DMA requests.

GENERATE BAD ABUS CMD/MASK PARITY
CMD

BAD

PAR

set, ABus Command/Length
transferred with even parity.

and ABus

Mask/Status

will

INHIBIT ARRY

SBE REPORTS
INH ARY CORR REP
set, this bit prevents the
correctable errors.
The errors

MCCJ
When

usual.

IOA DIAG

MCCJ

IOA

DIAG

When

set,

lines are
08>

CONTROL

CRB4.

MCCJ

<09>

is made

0).

When

<10>

Reserved

<15:13>

This

MBox

from

will

still

reporting
be

corrected

ECC
as

PROG

IN PROG
the Abus command/mask
field
and
length/status
driven from MCC CONTROL REGISTER 1C <03:00>.

MEMORY MGMT
MCCJ

MEM MAN

When

set,

ENABLE
EN

memory

management
is
enabled.
All
wvirtual
are
then translated by the TB.
When this bit
all references will be treated as physical and
TB parity error checking will be disabled.

references
is cleared,

all

<07:00>

sSource:

MAPP

(REG)

MBox

Reg

<07:06>

Reserved

<05>

ADDRESS TB RAM VIA DIAG
MAPP ADR RAM DIAG
The effect of this bit depends

(ADDR CONTROL

the

.
cycle

type:

Write TB - Causes the TB RAMs containing physical
address
bits
<12:09>
and selected by the IVA lines to be written
instead of those selected by
the
EVA
lines.
Used
for
diagnostic testing of TB RAMs.
Read TB - Causes the contents of the
TB
RAMs
containing
physical
address
bits <12:09> and selected by the IVA to
be read instead of those selected by the EVA lines.
Used
for diagnostic testing of TB RAMs.

20-91

VAX 8600/8650 REGISTER DESCRIPTION
MERG

#80X ERROR GENERATION WoRD

MERS

(ESCRATCH LOC: 28 — T18) PR 47

=
15

g2;

TAG , ADDRESS

VIADIAG | TBTAG _ TBVALD, WBIT

ENABLE

/| REQUESTS DARIY Y| REPORTS

MR.-I382F

Diagnostic Read Cache Tag Address - Causes the written
bit, written parity valid bits and cache tag parity to be
Used for
read in place of the cache tag address bits,
diagnostic testing of the cache tag RAMs.

<04:00>

GENERATE EVEN PARITY

the

When set, the bits in this field will cause

MBox

tag

generate even (bad) parity for the corresponding function.

<04>

GENERATE EVEN PARITY TB TAG
MCCJ EVN TB TAG PAR

When set, a write to the TB will

beiny

written

with even

result

parity.

the

read

location will result in a TB TAG parity error.

<03>

this TB

GENERATE EVEN PARITY TB VALID
MAPP GEN TB VAL ERR

When set, a write to the TB will result in
bit field being written with even parity.

the TB Valid
A read to this

TB location will result in a TB Valid parity error.

<02>

GENERATE EVEN PARITY CACHE WBIT
MAPP GEN EVN WBIT PAR

Wwhen set, parity for the cache written bit will be
complemented before being written in the cache. A read to
this Cache location will result in a Cache WBit parity
error.

<01>

GENERATE EVEN PARITY CACHE TAG
MAPP GEN EVN TAG PAR

Wwhen set, the cache data address tag is stored
A read to
parity during a cache write.

with even
this Cache

location will result in a Cache Tag parity error.

<00>

GENERATE EVEN PARITY PHYSICAL ADDRESS
GEN EVN PA PAR

The effect of this bit depends on the
the MBox is performing.

type

operation

Cache or Array Writes - When set, the address parity bit
as part of the ECC character generation will be
generated
this
array
the
to
the write was
If
complemented.
be detected when that array location is
condition will
If the write was to the Cache a Cache Byte
next read.

parity error will have to be forced by some other means in
order to detect this condition.

DMA - The MBox will detect an ABus Address Parity Error.

CP to I/0 Transfers - The ABus

Adapter

will

address parity and set CP 1/0 Buffer Error.

TB Writes — Bad parity will be forced in both
PTE

20-92

detect

bad

and

PTE

VAX 8600/8650

METATI

MBOX STATUS WoRD |

{ESCRATCH LOC: 25 - T15)

31
MBOX DATA

DESTINATION CODE
iy

;

28
27
MBOX CYCLE TYPE

25
24
LONGWORD COUNT.

BLOCK
HIT

CACHE [
TAG MISS

CACHE

MiSS

TBVALID
PE

TBPIEB
PE

ggfifl

gg“

18
ABUS

CYCLE

DATA

)

17
16
I0A SELECT

| DA MASK | ADDRESS | LMI/AUH

21
20
19
aBus | ABus cwo | ABus

15
®

MISS -

l pE

up of

the

TBRIEA | TBTAG

{BYTE IN ERROR)
CPL WRITE PE

ggm

CACHE 1

CACHE

SELECT

DATA PE
DURING

g BYTE WRT
MA
- 13320

This
3),

<31:24>

<31:30>

(byte

is made
2),

(byte

MBOX REGISTER

SOURCE:

MCCJ

(CRA)

ACCESS:

Read

Only

HELD AT:

MCCJ

TOT

and

(byte

(MCC STATUS

CYC

ERR

00
01
10
11

(byte

0).

(MCC STATUS

associated with

the

error.

Destination
IBUF
IMD
EMD
IBUF

MBOX CYCLE
MCCD U

MBOX REG

MBOX DESTINATION CODE <1:0>
MCCC LAST DEST CP <1:0>
Indicates the destination code

Code

<29:26>

following MBOX REGISTERS:

CYC

Indicates

(IBox - Don't Load Tail Pointer)
(IBox - FETCH/STORE Operand)
(EBox - FETCH/STORE)
(IBox - FETCH - Load Tail Pointer)
TYPE
TYP

<3:0>

the microword cycle

type

associated

with

the

when

the

error.

CODE

CYCLE

0000 NOP
0001 READ REG
0010 WRITE REG
0011 WRITEBACK
0100 ABUS ARRAY WRT
0101 DATA CORRECTION
0110 CLEAR CACHE
0111 TB PROBE
<25:24>

<23:16>

Indicates

the

error

detected.

ABUS
CP REFILL
INVAL TB
TB C¥C
CP ARRAY WRT
CP WRITE
CP READ
ABUS REFILL

was

longword that was being processed

MBOX REGISTER 28 (MCC STATUS 3)
SOURCE:
MBox Register 28 (MCA:

CYCLE
MCCC

PARAMETER RAM B
CPR

Indicates
detected.
22>

CYCLE

1000
1001
1010
1011
1100
1101
1110
1111

LONGWORD COUNT
MCCJ WD CNT <03:02>

28 (MCC STATUS 3)
.
ACCESS:
Read Write
HELD AT: MCCM CYC ERR SUM
<23>

CODE

CRB)

(CRB)

MBOX REG

+ TO

PARITY

ERROR

PERR B

that a Cycle Parameter RAM B
parity
The MBox response is unpredictable.

CYCLE PARAMETER RAM A PARITY ERROR
MCCC CPR PERR A

Indicates
detected.

MCCJ

that a Cycle Parameter RAM A
parity
The MBox response is unpredictable.
20-93

error

was

error

Wwas

VAX 8600/8650 REGISTER DESCRIPTION
MSTAT1
HETATY

MBO0X STATUS WORD 1

{ESCRATCH LOC: 25 - T15)

;]

1,0

ggg}éi&éxgm cooe

<21>

"55

]

3‘zi:.a]A3,AzEPEPEPfPEC"CK;‘GI
MBOX CYCLE TYPE

ABUS

LONGWORD COUNT. l

DATA PARITY

MCD3 ABUS
Tndicates

ABus

Cycle.

<20>

gpas

ABUS

,gg?g,

‘éfiuéAc;;g iggiisslgg%?ma

DA SELECT

parity

error

was

detected
on

the

Field during either a CP I/0 READ or DMA WRITE

ABUS COMMAND OR MASK PARITY
MCC4

cPRA

ERROR

DAT PERR
that a longword

Data

CNTL

ERROR

PERR

If bit <18> is set, this bit indicates that a parity error
was
detected
on
the command/length field during an ABUS
Command Address cycle.
If bit <18> is reset then this bit
indicates
that
a
parity
error
was
detected
on
the
Mask/Status Field during an ABus Data Cycle.
<19>

ABUS

ADDRESS

PARITY

ERROR

MAP2 ABUS ADR PERR
‘
Indicates that a parity error was detected on the
Address
Field associated with an ABus Command Address Cycle.

<18>

ABUS COMMAND/ADDRESS CYCLE
MCCJ ABUS

LD CMD

Indicates that
the
MBox
was
executing
Address cycle when an error was detected.

<17:16>

<15:08>

IOA SELECT <01:00>
MCC4 ABUS SEL <01:00>
Indicates the ABus Adapter
error was detected.

was

DMA

selected

Read Only
Self holding

the

at T3

HIT

Indicates that the TB TAG (indexed by VA <16:09>)
match
VA
<30:17> or the valid bit was not set.
will

send

a Port Status of

"A"TM

(TB Miss)

back

did
not
The MBox
the

EBox.

BLOCK HIT

MAPL BUF BLOCK
Indicates that

Cache
set,
<13>

when

TB MISS
MAP3

<14>

Command

MBOX REGISTER 24 (ADDRESS STATUS)
SOURCE:
MAPP (REG) MBOX REG 24 (ADDR STATUS)
ACCESS:
HELD AT:

<15>

that

HIT
either

the Tag for Cache 0 or the
Tag
for
<28:13>, at least one valid bit was
adapter was not selected.

matched

and

I/0

CACHE

TAG MISS

MAP3

TAG MAT

Indicates

that Tag

in Cache 0

20-94

did not match PA <28:13>.

VAX

8600/8650

<12>

CACHE MISS
MAPL

BUF CACHE
Indicates that

HIT

either PA

<28:13>

failed

to match

both

the

Cache
0
Tag and the Cache 1 Tag or, if a match did occur
then the valid bit for the target word(s) was not
set.
<11>

TB VALID PARITY

MAPP TB VAL

Indicates

bit

<10>

that a parity error was detected

when

the

Status

"8"

PARITY

PTE

ERROR

ERR

(TB

was

read.

Error)

back

the

09>

RAM

containing

Status

MAP4

that

containing

(TB

was

Error)

detected when the TB PTE
The MBox will send a

read.
back

the

EBox.

a parity error was detected when
PA

<29:25>,

The MBox will
to the EBox.

PROTECTION

send

<D:A>,

the TB PTE
and

a Port Status

MODIFY

TB TAG PARITY ERROR
MAP3 TB TAG PAR ERR
Indicates that a parity

RAMs
were
(TB Error)

<03>

<24:09>

"8"

Bits were read.
(TB Error) back

<07:04>

Port

EBox.

PTE A PAR ERR

Indicates

'<07:00>

valid

TB PTE A PARITY ERROR

RAM

<08>

the
send a

ERROR

MAP3 PTE B PAR ERR
Indicates that a parity error was
Port

The MBox will

MCDU

error was detected when the TB
The MBox will send a Port Status of
the EBox.

read.

back

"8"

TAG
"§"

SOURCE:

MCDU

REG

ACCESS:

Read

Only

HELD AT:

MCCJ

TOT

(DATA STATUS)

CYC

ERR

CPU WRITE (BYTE IN ERROR)
UFO5 WR BYT <3:0> PERR (MCDU)
This field indicates that a parity error was
detected
on
the
data
received
from
the
CPU
during
a
CPU write.
Furthermore, this field indicates which
byte(s)
had
the
parity error.
CACHE

DATA PARITY

ERROR

UFO5

CACHE BYT PERR (MCDU)
Indicates that a byte parity error was

detected
on
data
from
cache
during any Cache operation other than a
Byte
Write
Hit.
Includes:
CPU
Read,
DMA
Read,
Writeback, and DMA Masked Write.
read

CPU

<02>

CACHE

SELECT

MAPL CACHE 1 DAT
This bit indicates

<01>

Brror

was

ARRAY

READ

the Cache

detected.

MCCJ ANY REFILL
Indicates that a Cache
error

<00>

was

Refill

detected.

that was

was

selected

progress

CACHE DATA PARITY ERROR DURING BYTE WRITE
UFO5 CACHE BWRT PERR (MCDU)
Indicates that a Cache
Data
Parity
Error
during a CP Byte-write Operation.

20-95

was

when

the

detected

VAX 8600/8650 REGISTER DESCRIPTION
MSTATZ

MBOX STATUS WORD 2

MSTAT2

(ESCRATCH LOC: 26 - T16)

‘C’;AB{?%%E

CACHE
WEIT
SET

PAMM CONFIGURATION CODE

‘

MuLT;:Lg i

CMD/MASK FIELD

DENSTAT FieLo

CACHE

Dasfiasrc ABUS

AGNOSTIC — ABUS

ARAAY TYPE LUDE

WRiTE

03
CRi0

CPNXM | BUFFER
ERROR

gsaafiv

LOCK /
M

following

This register is made up from the
(byte 2),

(byte 1), and 58

(byte 0).

Registers:

MBox

<31:24>

VMS SUPPLIED

<31:28>

RESERVED

27>

ARRAY TYPE CODE VALID

This field is supplied by VMS and describes the array type
selected at the time that the error occurred.

Indicates that the Array Type

Code

bits

<26:24>

vaild.

<26:24>

ARRAY TYPE CODE

Indicates the Array type that was selected when the

error

occurred.

CODE

ARRAY TYPE

CODE

ARRAY TYPE

000
001
010
011

Reserved
16 Mb Array
04 Mb Array
64 Mb Array

100
101
110
111

Reserved
Reserved
Reserved
Reserved

<23:21>

RESERVED

<20:16>

MBOX REGISTER 54

<20:16>

SOURCE:

MAP9

(RAM) MBOX REG 54 (PAMM)

PAMM CONFIGURATION CODE <A:1>

MAP9 PAMM CONF <A:1>

The Error Handling Microcode uses MEAR <29:20> to

address

the PAMM and then loads the five-bit PAMM code into this
field. Normally this field will indicate the Array Module
If,
or 1/0 Adapter selected when the error was detected.
then
however, the error involved a CP to I/0 transfer,
this field will not be valid.
SELECTS

CODE

SELECTS

00
01

Array Slot
Array Slot

18
19

1/0 Adapter 0
I/0 Adapter 1

04
05

Array Slot
Array Slot

Array Slot

MBOX REGISTER 5C

<15>

BYTE WRITE
MCC7 CP BYTE WRITE

Indicates

jer

1C
1D
1E

I1/0 Adapter 2 (Not used)
I/0 Adapter 3 (Not used)

Reserved
Reserved
Reserved

Non-Existent Address

Reserved

<15:08>

SOURCE:

1A
-

o
VA

%
R

Array Slot

- WV

Array Slot
Array Slot

02
03

CODE

MCCJ (CRA) MBOX REG 5C (MCC STATUS 2)

that

the

MBox

request.

20-96

was

servicing

byte

write

VAX 8600/8650

<14>

ABUS BAD DATA CODE
MCC4 AB BAD DAT ERR
Indicates that the CP

T0O

read

data

received

from

the

ABus

Adapter was marked as bad data via the ABus Status Field.
<13:12>

DIAGNOSTIC ABUS LENGTH/STATUS FIELD
MCC4 LABUS STAT <1:0>
Indicates the state of

during
<11:08>

the ABus

Length

and

Status

lines

Mask

lines

I/0 diagnostic operation.

DIAGNOSTIC ABUS COMMAND/MASK FIELD
MCC4

LABUS

MSK

<3:0>

Indicates

the

during

I/0 diagnostic

state of

<07:00>

MBOX REGISTER 58

SOURCE:

MCCJ

<07>

MULTIPLE

ERROR

(CRB)

CRB5 MULT ERR

the ABus

Command

and

operation.

MBOX REG 58

(MCC STATUS 4)

(MCCJ)

Indicates that a second MBox error was detected before the
EBox could read and clear the first error.
Most or all of
the

information associated with

the

second error

will

lost.

<06>

<05>

CACHE TAG PARITY ERROR
CRB5 CACHE TAG PERR (MCCJ)
Indicates that a parity error was detected
and valid bit portion of the Cache tag.
CACHE

WRITTEN

BIT

PARITY

CACHE

WRITTEN

NON

EXISTENT

in
the

the
Cache
request as

BIT SET

CRB5 WRITTEN (MCCJ)
Indicates that the cache
was detected.
<03>

address

ERROR

CRB5 TAG WRT PERR (MCCJ)
Indicates that a parity error was detected
tag
Written
Bit
Field.
The MBox handles
though the written bit was a one.
<04>

the

written bit was set when an error

MEMORY

CRB5 NXM (MCCJ)
|
Indicates
that
either
the
memory
request
was
to
Non-Existent Memory or an 1/0 adapter attempted to address
another 1/0 adapter.
An MBox Fatal Error status
code
|is
sent

the

EBox

for CP

initiated

requests,

and

ERROR
1line
1is
asserted
to
the
1I/0
Adapter
initiated requests.
All writes are cancelled.
<02>

CP I/0 BUFFER ERROR
CRB5 CP IO BUF ERR (MCCJ)
Indicates

that

the

selected ABus Adapter detected

while processing a CPU request.
<01>

ABUS

MEMORY

driven on the ABus.

<00>

DMA

1I/0

an error

LOCK

CRB5 LOCK LINE (MCCJ)
When set, indicates that the Memory Lock
MBox

the

for

an ABus

Line

was

being

This line may be driven by either the

Adapter.

RESERVED

20-97

VAX 8600/8650

NICR
POBR

POLR
Nich

MEXT INTERVAL COUNT REQISTER

PR18
31

NEXT INTERVAL COUNT
)

<31:00>

]

The

INTERVAL

reload

]

COUNT

is a write only
register
that
holds
the
value
to
be loaded into ICR when it overflows.
The
value is retained when ICR is loaded.
NICR is capable
of
being
loaded
regardless of the current values of ICR and
ICCS.

]

PO BASE BEBISTER

PR 08 (ESCRATCH LOGATION: EB)
31

)
F

[

SYSTEM VIRTUAL LONGWORD ADDRESS

33
3

°A

)é

4R -13958

<31:02>

PO BASE REGISTER
Contains the system virtual

<01:00>

Process

MBZ
Must be

Page

Table

longword

address

the

zero.

FOLR

PO LERGTY BEBISTER

IPR: 08 (ESGRATGH LOGATION: £3)

330

IGNORE

]

MBZ
Must

<26:24>

RESERVED

<23:22>

MBZ

Must
<21:00>

LENGTH OF POPT IN LONGWORDS
3

<31:27>

start

(POPT).

zero.

PROCESS 0 LENGTH REGISTER
Contains the size (in longwords)

.
(POPT)

20-98

Process

Page

Table

VAX 8600/8650

PI8A

P1 BASE REGISTER

iPR: 0A

VIRTUAL LONGWORD ADDRESS
3

]

<31:02>

]

PIlBR

(PROCESS 1 BASE REGISTER)
Base register for page table
describing
addresses from 2**31-1.

<01:00>

MB2Z
Must

process

virtual

zero.

PiiR
PR 0B
31

MBZ2

F1 LENGTH REGISTER
30

MBZ
2

<31:22>

2°21 - LENGTH OF PIPT IN LONGWORDS
3

]

[

]

[

]

MBZ
Must

<21:00>

zero.

PI1LR PROCESS 1 LENGTH REGISTER
Length register for page table located
effective length of page table.

20-99

P1BR.

Describes

VAX 8600/8650

PAMACC
PHYSICAL ADDRESS MEMORY MAP ACCESS

FAMACL
PR 40

PAMM ADDRESS
3

—

CONFIGURATION CODE
A

1
ME-1338

NOTE

PAMACC and PAMLOC are used to write/read the
PAMM.
When writing the PAMM, the PAMM address and data is
written to PAMACC with a
MTPR.
EBox
micro
code
will

carry

out

the write

the

PAMM with

an MBox

When
reading,
PAMLOC
will
be
PAMLOC, with the PAMM address to
data will be gated from the PAMM
MFPR PAMACC which will cause the

read

the

PAMM

with

MBox

read.

<31:30>

RESERVED

<29:20>

PAMM ADDRESS

The PAMM address specifies the PAMM address to be read
or
written.
It
can specify one of 1024 possible entries in
the PAMM.

Each PAMM address,

when mapped corresponds

to a

1-MByte
window
of
physical
address
space.
The
bit
alignment in the PAMM address field corresponds to the bit
alignment of

the physical address.

<19:05>

RESERVED

<04:00>

CONFIGURATION CODE

CONF A,8,4,2,1 - CONF
CODE
<8:1>
defines
Memory Array
CONFIG CODE "A" set to one
or NXM.
Code,
Adapter
Card,
specifies on one mega-byte boundaries to
inhibit
writing

data to Cache (used to inhibit writing I/0 data to cache).

CONFIG

CODE

SELECTS

Internal Array Slot 0

01
02
03
04
05
06

Internal
Internal
Internal
Internal
Internal
Internal

08-17

Unused

18
19
1A
1B
1C-1E
1F

I/0 Adapter O
1/0 Adapter 1
I/0 Adapter 2
I/0 Adapter 3
Unused Codes
Non Existent Address

Array
Array
Array
Array
Array
Array

Slot
Slot
Slot
Slot
Slot
Slot

1
2
3
4
5
6

Internal Array Slot 7
Codes

20-100

(Array Card 0)

(Array Card 7)

VAX 8600/8650

PHYSICAL AGDRESS MEMORY MAP LOCATION

&\a

PANLIC

PAMM ADDRESS

NOTE
See

PAMACC.

boundaries,
bit 20.

The

PAMM

which

why

<31:30>

RESERVED

<29:20>

PAMM ADDRESS

<19:00>

RESERVED

addressed

the

Mega-byte

PAMM address

starts

PROGRAM COUNTER

{ESCRATCH LOC: 2E — TIE)
31

RETURN PC FOR REI {CALCULATED BY EHM)
;]

This

that
an
REI
determined by

instruction
this

]

)

contains
1is
the

the PC

to be

possible.
The
Error
Handling

the

pipeline

reflect

the

]

used by VMS

this register are
Depending
on
the

the

20-101

contents
of
Microcode.

that was
CPC,

determines

associated with the error,
ISA,

the

ESA.

VAX 8600/8650 REGISTER DESCRIPTION
PCBB

PROCESS CONTROL BLOCK BASE REGISTER
;ggga
4033263@
8878505&
22110698
61513!31
31913171
23222!2‘
3!38?92827?625?4
1
PR

MBZ
"

<31:30>

<29:02>

MBZ

Must be

PHYSICAL LONGWORD ADDRESS OF PCB
b

]

_§

]

F S— |

MBZ
i

zero.

PHYSICAL LONGWORD ADDRESS OF PCB

The Process Control Block Base (PCBB) Register points to
the process control block for the currently executing
process. The PCBB Register 1is an internal privilegeotd
register, which contains the physical longword address
the Process Control Block (PCB). The PCB itself contains
all of the switchable process context collected into a
compact form for ease of movement to and from the
privileged internal registers.

<01:00>

F N

MBZ

Must be

zero.

20-102

VAX 8600/8650

PECAS

PARITY ERROR ADDRESS REGISTER {CAJ)

176061

cigs

HIGH-ORDER ERROR ADDRESS BYTE {SAL<15:08>)
i

ALL BITS READ ONLY
MR- 34312

NOTE:

See

description

PERAS

PECAS

PARITY ERROR ADDRESS REGISTER (BAY)
CLos

’

LOW-ORDER ERROR ADDRESS BYTE (RAS<07.00>)
3

NOTE:
ALL BITS READ oNLY
MR 4TI

When a parity error is detected, the failing RAM address is
stored
in
two
8-bit
registers that may be read by the T-11.
The Parity
Error CAS (PECAS) register stores the high=order address byte.
The
Parity
Error
RAS
(PERAS)
register
stores the low-order address
byte.
In

pass

stored

map

mode,

the

failing

these
the

T-1l1

address

(SAL<15:08>

registers.

failing

virtual

address

is
stored.
physical page

(SAL<15:08>

and

RAS<7:00>)

therefore
which RAM

The
physical
address
depends
on the corresponding
number in the mapping RAM.
The
T-11
program
must
calculate
the
physical
address
in order to determine
location is bad.

case

either

rebooting
is done by

the

Console

either by

the

PROM

the

prints
an
operator or by

code.

20-103

error
message
and
awaits
the operating system.
This

VAX 8600/8650 REGISTER DESCRIPTION
PMR
PERFORMANCE MONITOR ENABLE
PR30

<31:01>

<00>

RESERVED

PERFORMANCE MONITOR ENABLE

Performance Monitor Enable controls a signal visible to an

This bit is set to
external hardware performance monitor.
1is desired
identify those processes for which monitoring
their behavior to be observed without
and to permit
interference from other system activity.

Writing a 1 to bit
provide

CPU backplane

ECL'

<00>

via

MTPR

instruction

will

logic "high" output on pin AC9A07 of the

(EBES).

20-104

VAX

8600/8650

PsL

PROCESSOR
STATUS LONGWORD

(ESCRATCH
LOC: 2F - T1F)

COMPAT

ABILITY
MOBE

TRACE
PENDING

GURRENT

INTERUFT

oo,

20
o

INTERRUPT PRIORITY LEVEL

ACCESS MODE

STACK

~ TRAP ENABLES
DECIMAL

FLOATING

CONDITION CODES

INTEGER

OVERFL OW :lmBRF! OW OVERFLOW ~ TRACE

NEGATIVE

]

ZERO

OVERFLOW

CARRY

hf . 13827

<31>

COMPATIBILITY MODE
When set,
indicates

compatibility
processor

<30>

TRACE PENDING
This bit works

that

When

native

(VAX)

thus

cause
Trace

trap

the

Handler

processor

c¢lear,

1in

indicates

PDP-11

that

the

mode.

conjunction

If
Enable Trace is set
then the processor will

The

the

mode.,

with

Enable

Trace

at the beginning of
automatically
set

Trace

Routine

Handler
will

<04>,

Routine.

gather

information about the state of the
the Enable Trace and Trace Pending

bit

an instruction
this
bit
and

the

desired

system and REI (leaving
bit alone).
This
will

allow
the
next instruction to be traced.
When the Trace
Handler Routine wants to discontinue tracing it will clear
both bits (Enable Trace and Trace Pending).
<29:28>
<27>

RESERVED
FIRST

PART

DONE

This
bit
1is
set
by
1long
instructions
that
can
be
interrupted during execution (e.g., Move String).
The REI
following the
interrupt
will
continue
the
interrupted
instruction.
<26>

INTERRUPT

STACK

When set, the processor
stack.
Any
mechanism
current

mode

attempts
mode

<25:24>

zero

field

reserved

IS=1

and

non-zero
is

MODE

indicates
process,

SUPERVISOR,

operand fault

current
When

CURRENT ACCESS

PSL with

stack
set.

the

access

follows:

mode
0

KERNEL,

the
1

currently
EXECUTIVE,

USER

PREVIOUS ACCESS

MODE
This field is loaded
from
the
Current
Access
Mode
exceptions
and
CHMx
instructions.
It
1is
cleared
interrupts, and restored by REI's.

21>

RESERVED

€20:16>

INTERRUPT

IPL,

this bit is clear, the processor is executing on the
specified by current mode.
At bootstrap time, IS is

executing

raises

restore

taken.

This

<23:22>

and

1is
executing
on
the
interrupt
that
sets
this
bit also clears
the
IPL
above
0.
If
an
REI

PRIORITY

by
by

LEVEL

Indicates the current processor priority, in the
range
0
to 1F (Hex).
The processor will accept interrupts only on

<15:08>

levels

greater

IPL is

initialized to 1F

than

the

current

(Hex).

RESERVED

20-105

level.

bootstrap

time,

VAX 8600/8650

PSL
5L

PROCESSOR STATUS LONGWORD

{ESCRATCH LOC: 2F - T1F)

{ COMPAT
'

PART l

{HACE

ABILITY
MODE

PEMDING

CURRENT
ACCESS MODE

INTERUPT
STACK

NTERRUPT PRIORITY LEVEL

PREVIOUS
AUCESS MUDE

TRACE

NEGATIVE
N

TRAP ENABLES

CONDITION CODES

DECIMAL
FLOATING INTEGER
OVERFLOW UNDRFLOW OVERFLOW ~

ZERO
7

QVERFLOW
vy

CARRY
¢
MR- 1FRIT

<07>

DECIMAL OVERFLOW TRAP ENABLE

When this bit is set,
after
execution
of
error,

produced

it forces a
decimal
overflow
trap
an instruction that had a conversion
result

with

a decimal

overflow

(e.g.,

numeric
string,
or
packed
decimal).
When this bit
clear, no trap will occur, however, the condition
code
bit will still set.
<06>

is
V

FLOATING UNDERFLOW EXCEPTION ENABLE
When this bit is
set,
it
forces
a
floating
underflow
exception after execution of the instruction that produced
a result with an underflow (e.g., a result exponent, after
normalization
and
rounding,
1less
than
the
smallest
representable exponent for the data type).
When this
bit
is clear, no exception occurs.

<05>

INTEGER OVERFLOW TRAP
When this bit is sct;

ENABLE
it forces

integer

overflow

trap

after execution of an instruction that produced an integer
result that overflowed or had a
conversion
error.
When
this
bit
1is
<clear, no integer overflow trap will occur,
however, the condition code V bit will still set.
<04>

TRACE

ENABLE

When this bit is set at the beginning of
an
instruction,
it
will
cause
Trace
Pending
<30>
to set.
When Trace
Pending is set at the end of an instruction, a trace fault
is
taken
before
the
execution of the next instruction.
When TP is clear, no trace exception occurs.
<03:00>

CONDITION

CODES:

BIT - When

indicates
produced

set,

that
a

the

last

negative

(negative)

condition

<c¢ode

instruction that affected

result.

this

bit

1is

bit

this bit

clear,

the

result was positive or zero.

Z BIT - When set, the Z (zerco)
condition
c¢ode
indicates
that the last instruction which affected this bit produced
a result which was zero.
When
this
bit
1is
c¢lear,
the
result was non-zero.
V BIT - When set, the
V
(overflow)
condition
code
bit
indicates
that
the
last instruction which affected this
bit either had a conversion error
or
produced
a
result
whose

magnitude

was

too

large

be properly

in the operand which received the result.
is

clear,

there was

conversion

error

When

represented

this

or overflow.

bit

C BIT Wwhen
set,
the
C
(carry)
condition
code
bit
indicates
that
the
last instruction which affected this
bit either had a carry out of the most significant bit
of

the
result
or
When this bit is

a
borrow
into the most significant bit.
clear, there was no carry or borrow.

20-106

VAX

8600/8650

PTE

PAGE TABLE ENTRY
28

PROTECTION

<31>

l MODIFIED ZERD

OWNER

SOFTWARE

PAGE FAME NUMBER
PFN

]

VALID BIT

Governs the
valid;
V=0
are

<30:27>

reserved

validity of the M bit and PFN field.
V=1
for
for not valid.
When V=0, the M and PFN fields
for

DIGITAL

software,

PROTECTION

FIELD

This

field

always valid and

used by the CPU hardware

even when Vv=0.
<26>

MODIFY

BIT

When

the valid
hardware,
and
devices.
When

bit

is
<clear,
M
is
not
used
by
CPU
is
reserved
for DIGITAL software and I1/0
the Valid bit is set, M shows
whether
the
page
has
been modified.
If M is clear, the page has not
been modified.
If M
1is
set,
the
page
may
have
been
modified.

M is
cleared
only
by
Microcode
(firmware).
probe-write

instruction

software.
It
is
set
by
EBox
In addition, it may be set by the

probe-write.
M
instruction which

(PROBEW)
or
by
an
implied
is
not
set
if
a
fault
occurs in an
would otherwise have modified the page.

For

write

example,

where

reference

crosses

page

boundary

the first page is not accessible and the second page
is accessible, the reference will fault.
M
is
unchanged
in
the
PTE
mapping the first page.
It is UNPREDICTABLE
whether M is set in the PTE mapping the second page.
It is UNPREDICTABLE whether the modification of a
process
PTE<M> bit causes modification of the system PTE that maps
that process page table.
Note that the update
of
the
M
bit is not interlocked in a multiprocessor system.
<25>

ZERO BIT

Bit 25 is reserved to
DIGITAL
and
must
be
zero.
The
hardware
does
not necessarily test that this bit is zero
because the PTE is established by privileged software.
<24:23>

OWNER BITS

Reserved for DIGITAL software use as the
access
mode
of
the owner of the page, (that is, the mode allowed to alter
the page protection or to delete the page);
not
examined
or altered by any hardware.
<22:21>

' <20:00>

SOFTWARE BITS
Bits 22 and 21

are

reserved

for DIGITAL software.

PAGE FRAME NUMBER
The upper 21 bits of the physical address of
the page.
Used by CPU hardware only if V=1.

20-107

the

base

VAX 8600/8650 REGTSTER DESCRIPTION
QADRO /QADR1

{BUS ADAPTER ADORESS REGISTER

gADRD

176406

c127

{ OW-ORDER OBUS ADDRESS

3. ..

NOTE:

ALL BITS WRITE ONLY

MR 14217

See QADR]l for register description.

Note:

gADR1
176407

QBUS ADAPTER ADDRESS REGISTER
ciz7

1.,

HIGH-ORDER OBUS ADDRESS

14,

13,

12,

NOTE:

ALL BITS WRITE ONLY

The program loads the address in the address registers.
loads

first

the

data

the low-order byte in QADR <00> and then the high-order byte

When

in QADRl.

the

data

read

1is

stored

registers, QDATAO and QDATAl and CONSOLE MASTER PENDING is cleared.
that the
This signifies that the read operation is completed and
data may

retrieved

from QDATAO

and QDATAIL.

20-108

VAX 8600/8650

QCSRO
GCSR0

QB4 CONTROL AND STATUS RESifléiiizg

176400

MAINT
MODE

0BUS DMA

ENABLE

QA
QBU3
INTERUPT | READ BY

ENABLE | CONSOLE

g8u3

QONSOLE

CONGOLE
REQUEST
MASTER

WRITE BY | MASTER

CONSOLE | PEND

NOTE:

BIT 01 READ ONLY, ALL OTHER 8ITS READ/WRITE

07>

MA-74208

MAINT MODE

CL29 MAINT MODE H
Set maintenance mode
<06>

QBA AND QBUS
CL.29

QBA

to allow

simulation of QBus device.

INIT

Initialize QBA and QBus devices.
<05>

ENABLE

QBUS

DMA

CL29 ENA QBUS DMA H
Enable QBus DMA transfer

<04>

requests.

QBA INTERRUPT ENABLE
CL29 QBA IE H
Enable

QBA

acknowledge

QBus

device

interrupt request.

<03>

QBUS READ BY CONSOLE
CL29 QBA READ H
Request QBus read operation by Console.

<02>

QBUS

WRITE

CONSOLE

CL29 QBA WRITE H
Request QBus write
<01>

<00>

CONSOLE

MASTER

operation by Console.

PEND

CL31

CSL MASTER PEND H

Qbus

read/write operation by Console

CONSOLE

in progress.

REQUEST MASTER

CL31 CSL REQ MASTER H
Request QOBus for read/write

20-109

operation by Console.

VAX 8600/8650 REGISTER DESCRIPTION
QCSR1
{BA CONTHOL AND STATUS REGISTER |

gesni

gL28

176401

APLY l ouT l N l 91ec54]

SIMULATED NRUS SIGNALS DURING MAINTENANCE MODE

REQUEST REGUESTl

INTERUPT | DMA

DATA

DATA | SYNC

MR- 14318

ALl BITS ARE READ/WRITE

<07>

UNUSED

Bits

<06: 00>

are used during maintenance only and simulate

MAINT MODE,
<07>,
QCSRO
If
corresponding
the
will
assert
<06:00>
signal on the QBus.

signals.
QBUS
setting of QCSR1

<06>

SIMULATE SLAVE ACK

(QBUS SIGNAL:BSACKL)

CL29 SIM SACK H
<05>

SIMULATE INTERRUPT REQUEST
CL29 SIM IRQ H

<04>

SIMULATE DMA REQUEST
CL29 SIM DMR H

<03>

SIMULATE

<02>

SIMULATE

(QBUS SIGNAL:BRIQ L)

(QBUS SIGNAL:BDMR L)

REPLY (QBUS SIGNAL:BRPLY L)
CL29 SIM RPLY H

DATA OUT (QBUS SIGNAL:BDOUT L)

CL29 SIM DOUT H
<01>

SIMULATE

DATA IN (QBUS SIGNAL:BDIN L)

CL29 SIM DIN H
<00>

SIMULATE SYNC CLOCK
CL29 SIM SYNCH H

(QBUS SIGNAL:BSYNC L)

20-110

VAX

8600/8650

Qcsaz

{(BA CONTROL AND STATUS REGISTER 2
£izg

176402

SLAVE

1 ac

RECEIVED

-0

BYTE COUNT

NOTE:
ALL BITS READ ONLY

<07>

STATE COUNTER

SLAVE

RECEIVED SLAVE ACK

CL32 SREC SACK
BSACK received

H
on

QBus

indicating

QBus

device

1is

bus

master.

06>

-AC POWER OK (QBUS)
=CL32 RPOK H
When asserted, indicates

"-BRPOK

H",

which

the

indicates

reception

1loss

QBus

signal

of AC

power

QBus

signal

the

QBus.
<05>

-DC

POWER OK (QBUS)
-CL32 RDOK H
When asserted, indicates

"-BRDOK

H",

which

the

indicates

reception

1loss of

DC power on

the

QOBus.

<04:03>

BYTE COUNT
CL33 <B1:BO0> H
At the initiation of
a
QBus
DMA
sequence,
this
field
counts
the
byte
transfers
required to translate a QBus
word operation to a byte orientated data path
to
memory.
Cleared by Console initialization.

<02:00>

STATE

COUNTER

CL30 <CNT
Output of

2:0>
time

H
state generator

20-111

in QBus

control.

VAX 8600/8650

QCSR3

ODATAO/QDATAl
ALK

(B4 COMTROL AND STATUS REGISTER 3

174400

CL20

EMM

CPU

TIMEQUT

0BUS TIMEQUT COUNT

DCLO | TiMEOUT | 0BUS
L

NOTE:
ALL BITS READ ONLY

<07>

NOT

<06>

EMM CPU

USED

-CLO9

LO L
LOW H

This signal reflects the status of the DC Lo
signal
from
the EMM.
When asserted (= 0), a DC LO condition exists.
<05>

RPLY TIMEOUT

CL30 RPLY TIMEOUT H
RPLY not received on QBus during QBus read/write operation
(8 usec).
Interrupts Console (T-11) program.
<04>

TIMEOUT

CL30

TIMEOUT H

QBus RPLY
usec)
.
<03:00>

timeout

counter

QBUS TIMEOUT COUNT
CL30 TIME <3:0> H
Qutput of QBus RPLY

QUATAD

timeout

control

counter

has

in QBus

timed

out

control.

QBUS ADAPTER DATA REGISTER

176404

cLz7

85,

LOW-ORDER QBUS DATA

in QBus

3 ..,

0
MR- 184 ¥

Note:

See QDATAl

for register description.

goaTAl
176405

QBUS ADAFTER DATA REBISTER
cLz7

16,

HIGH-ORDER 0BUS DATA

%5,

8
R, 12220

The

data

registers,

console

program

loads

first

the

QDATA0

then

and

loads

the

low-order byte

QDATAl,
address

in QADRO

are
in

loaded
the

and

first.

address

The

registers.

then the
high-order
the address register
QBus
operation
if
the
CONSOLE MASTER PENDING bit is set.
The hardware automatically
clears CONSOLE MASTER PENDING at the end of the QBus
write.
This
indicates to the console program that the operation has ended.
byte in QADR1.
Loading the high-order byte in
causes the hardware to automatically begin the

20-112

VAX 8600/8650

CBUS
fEs8

RBUF

RBSR

REMOTE BAUD SELECT REGISTER

175431

cLign

REMOTE TRANSMIT
i

REMOTE RECEIVE

BAUD RATE SELECT

BAUD RATE SELECT
i

g(};’& BITS WRITE ONLY

The T-11 program specifies the baud rate by loading the Remote Baud
Select
Register
(RBSR).
The
<c¢lock rates are set by loading two
4-bit codes (one for the transmit
<c¢lock
and
the
other
for
the
receive

clock).
REMOTE

BAUD

BITS<7:4>

BAUD

BITS<3:0>

RATE

SELECT

BITS<7:4>

BAUD

BITS<3:0>

RATE

{=11)

RBUFD

174026

REUF2

174030

BBYFI

EBUF

1000
1001
1010

2000
2400

0011
0100
0101
0110
0111

134.5
150
300
600
1200

1011
1100
1101
1110
1111

3600
4800
7200
9600
19.2K

174031

1800

BECEIVED DATA BUFFER REGISTER

50
75
110

{CBUS)

174027

>
-

0000
0001
0010

CL17, 18

RECEIVED DATA
i

NOTE:

T-11 BITS WRITE

CBUS BITS READ

B 14198

The RBUF0-3 registers
are
used
1in
conjunction
with
register for transferring data packets from the console

the
RBUFC
to the EBox
microcode.
This communication occurs only
in
Console
I/0
(CIO)
mode
and will take place between CSM and MCP (if in MACRO context)
or DSM and DCP (if in DIAGNOSTIC context).
Refer to
CSM
and
DSM
specifications
for
operation
of
these registers, as well
"KA86 Console Technical Description” manual, EK-KA86C-TD.

20-113

the

VAX 8600/8650
CBUS

RBUFC

RH780

BCR

ABUFC
174032
32

RECEIVE BUFFER COMMAND REGISTER
(111

(CBUS)

DONE
PACKET
RIGHT OF ] CONTROL
l it

DATA
MR- 18198

The
RBUFC
registers

microcode.
This communication occurs
mode
and will take place between CSM
or DSM and DCP
specifications

"KA86

Console

<07>

RBUF0-3
and EBox

only
in
Conscle
I/0
(CIO)
and MCP (if in MACRO context)

(if in DIAGNOSTIC context).
Refer to
for
operation
of
these registers,

Technical

Description®TM

manual,

CSM
and
as well as
EK-KA86C-TD.

DSM
the

DONE

RIGHT-OF-ACCESS BIT
DONE is set, the EBox microcode
register.
When
DONE
1s
cleared,
write the RBUF register.
When

<06>

may
the

read
the
RBUF
T-11 program may

PACKET CONTROL

When

this bit is set, another packet will be sent
by
the
EBoX microcode.
When it is not set, the current packet is
the last one for this transaction.

<05:00>

DATA

Applications
dependent;
specifications.

refer

DSM

and

aca

CSM

RH780 BYTE COUNT REBISTER

OFFSET. 010

MASSBUS BYTE COUNTER

SBI BYTE COUNTER
1

E___

]

£
M 14311

The program loads (writes) the 2's
complement
of
the
number
of
bytes
to
transfer
into
bits
<15:00>
of
this
register.
Upon
initiation of the transfer, the MBA hardware
will
1load
these
16
bits
into
<31:16>
and into <15:00>.
The Byte Count Register may
not be modified during a data transfer.
Any attempt to do so
will
be
ignored
and
<19>, PGE, of the

<31:16>

<15:00>

will

result

RH780

Status

programming

error,

setting

bit

MASSBUS

BYTE COUNTER
The 2's complement byte count
transferred on the MASSBUS.

SBI

BYTE COUNTER

The

2's

complement

transferred

the

byte
SBI.

count

20-114

the

number of

bytes

to be

the

number

bytes

VAX

RH780

8600/8650

COMMAND/ADDRESS

DESCRIPTION

(CAR)

RH780

caR

BH780 COMMAND/ADDRESS REGISTER

OFFSET: 01C

FUNCT

SBi ADDRESS

§81 ADDRESS
F

]

MA-14314

READ

ONLY

This register is read only and valid only when DT BUSY is set.
contains
the
wvalue
of
bits
31 through 00 of the SBI during
command/address part of the MBA's next data transfer.

4 ]

It
the

RHT80 CONTROL REGISTER

OFFSET. 604

ABORT
-

R/W

L
W ONLY»
%P1 4308

<31:04>

RESERVED

<03>

MAINTENANCE MODE

Set when the MBA is in the maintenance
mode,
which
will
allow
the
diagnostic
programmer to exercise and examine
the Massbus operations without
a
Massbus
device.
When
set,
the
MBA will block RUN, DEM, and assert FAIL to the
Massbus so that all the devices on the Massbus will detach
.

from
the
Massbus.,
This
bit
transfer is not in progress.
<02>

INTERRUPT

«can only be

set

a data

ENABLE

Set by writing a 1 or at power up.
Cleared by writing a 0
or INIT.
Setting this bit allows the MBA to interrupt the
CPU when certain conditions occur.
<01>

ABORT

Set

DATA TRANSFER

by writing

a
Setting

UNJAM.
abort

sequences

addresses,

and

and
this

cleared

by writing

bit will

initiate

that

will

stop

the

byte

stop

a
the

sending

counter.

0,
data

INIT

or
transfer

commands

will

also

and

negate

RUN, assert EXC to the Massbus,
wait
for
EBL,
and
set
ABORT
to
a
1
at
trailing
edge
of
EBL.
The CPU is
interrupted if the Interrput Enable bit is 1.

1<00>

INITIALIZATION

This bit is
bit
clears

self-clearing (always reads 0).
Setting
this
status bits in the MBA configuration register,

clears ABORT and IE bits
in
the
MBA
the MBA status register, clears

clears

bits of diagnostic
commands

pending

transfer
command.

command

registers.

will

also

cancel

all

except the read data pending abort
well as
asserting
the
Massbus

data
Init

20-115

control
control

VAX 8600/8650
RH780 CSR

£sh

RUTE0 CONFIGURATION/STATUS REGISTER

OFFSET: 000

MIRR ST U

SBI FAULTS

UNEXPCTD
sg1 . WRITE
SEQUENCE RDDATA ,

HIl

Y
%%W
-ng -

. .

" ADAPTER
i}?? .
' //f?|- -~
POWER POWER :///
/é‘/fj’;f 7;

MULTIPLE éggz&%g %@%/Qf/fi
XMITTER | FAULT M,@@gféfi/fg DOWN |, UP
%2%&?;}“”

gg'

]

ADAFTCR CODL

e
MR- 14307

NOTE

When bits 31,
on
asserted

30, 29, or 27 are set, FAULT will be
In addition,
the SBI for one cycle.

they will be reset by a power

deassertion
<31>

<30>

SBI PARITY ERROR (FAULT A)
This bit is set when an SBI
WRITE DATA SEQUENCE
This

bit

set

when

a write operation,
<29>

<27>

(no

read

upon

the

(FAULT B)
a

received

but

is not

command

is detected.

address

indicates

followed by write data.

address

received but

is not

transmitted).

RESERVED

MULTIPLE TRANSMITTER FAULT
When

the

1ID

received

transmitted on the SBI,
<26>

parity error

UNEXPECTED READ DATA (FAULT C)
This bit will be set when read data
expected

<28>

fail

FAULT.

TRANSMITTER DURING

(FAULT D)

does

not

agree

with

the

this bit will be set.

FAULT

This bit is set when the SBI fault is detected on the
2nd
cycle
after the MBA transmits information on the SBI.
It
is cleared by a power fail or the deassertion of FAULT
on.
the SBI.

<25:24>

RESERVED

<23>

ADAPTER POWER DOWN

This bit will be set when the MBA receives
the
assertion
of
AC
LO.
It will be reset when power comes up, by the
assertion of INIT, UNJAM, DC LO, or the writing of
a
"1"
to
this
bit.
The
setting of this bit will generate an
interrupt if interrupt enable is set.

<22>

ADAPTER POWER UP

This bit will be set when the MBA receives the deassertion
of
AC
LO.
It will be cleared upon power down, or by the
assertion of INIT, UNJAM, DC LO, or the writing of
a
"1"
to
this
bit.
The
setting
of
this
bit
will set the
interrupt enable bit and

<21>

interrupt

the CPU.

OVER TEMPERATURE

Always 0
<20:08>

RESERVED

<07:00>

ADAPTER CODE

The MBA adapter code is:

<07:00> = 00100000

20-116

VAX

8600/8650

RHTE0 DIAGMOSTIC REGISTER

"”‘WM

QFFSET: (14

MIRL R 8

INVERT

PARITY

BLOCK

T0 88i

BLOCK

MIRJ

“MCP

MASSBUS DRIVE SELECT
]

CLOCK

SIMULATE (ON MASSBUS)

g??f BUS géérs%é g%: Eggggga SYNC
13

[

FAIL

DATA PARITY GENERATOR

CONTROL PARITY GENERATOR

<29>

INVERT MAP PARITY

<28>

BLOCK

Maintenance

simulate

the

SIMULATE

EBL

Mode

assertion of

the MM

bit

1is

(MM)

set,

this

set,

this

bit will

set,

this

bit will

’;’

—

bit

will

set,

this

bit

7
will

bit

will

simulate

the

simulate

the

assertion

SIMULATE ATTN
is

MAINTENANCE

When

this

simulate

assertion

the

MDIB

DATA INPUT BUFFER SELECT
set, the upper eight bits
(B<15:08>)
sent out from bits 07 through 00 of

the

When

the

MASSBUS

bit

diagnostic

will

MDIB

will

diagnostic

read.

<20>

ATTN.

<22:21>

SCLK.

OCC,.

When MM bit

<23>

IEXCEPTON!

EBL.

SIMULATE OCC
When MM bit is
of

<24>

GLOCK

SCLK

<03>,

assertion

WRITE

SENDING COMMAND TO THE SBI
During a data transfer,
the
sctting
of
this
eventually cause a DLT bit set and a DT ABORT.

When

<25>

RUN
03

INVERT MASSBUS

WOPE

INVERT MASSBUS

SIMULATE

MAINTENANCE MASSBUS DATA

E;é

<30>

<26>

<31>

<27>

[T —

MASSBUS

ouLy

MASSBUS REGISTER SELECT

Secr

, OCCUPIED | ATENTION
09

}

the diagnostic

cleared,

1is

read.

the lower eight bits (B<07:00>)
out from bits 07
through
00
of
register,
if
the diagnostic register is

sent

MAINTENANCE

USE ONLY
Read/write with no effect.
of these bits.

MASSBUS

Fail

Used

FAIL

(Read Only)
asserted when MM

<19>

MASSBUS

<18>

MASSBUS WCLK

17>

MASSBUS

EXC

<16>

MASSBUS

METOD

<15:13>

MASSBUS

DEVICE

<12:08>

MASSBUS

<07:00>

MAINTENANCE

RUN

set.

(Read Only)
(Read Only)
(Read

Only)

(Read

Only)

SELECT

(Read

Only)

(Read Only)

UPPER/LOWER MDIB
20-117

test

the

writability

VAX 8600/8650
‘RH780
RH780

SMR
SR

RH780 SELECTED MAP BEBISTER

b4 1

OFFSET: 018

7
-

l
3

]

PHYSICAL PAGE FRAME NUMBER

There are 256 MAP registers, and the Selected

MAP

(SMR)

contains
the
contents
of
the
MAP
register
pointed
to by VAR
<16:09>,
The SMR is a read only register and is valid only when DT
BUSY is set (SR <31>, data transfer command has been received).

The MAP registers can
only
be
written
when
there
1is
no
data
transfer
operation in progress.
A write to a MAP register while a
data transfer is in progress will be ignored and cause the
setting
of PGE (SR <19>)
IE is set.
<31>

and

interrupt

VALID BIT
Bits <20:00>

<30:21>

MBZ

<20:00>

PHYSICAL PAGE

the CPU at

a valid physical

FRAME

the end of

page

frame

transfer

number.

NUMBER

RHT80 STATUS REGISTER

OFFSET: 008

MIRR 5, T.U

28
o
T

DATA
O
TRANSFER
|RESPONSE
|CORECTED
READ ;ff’«’f‘/f’fé";
f}éffii{ff{@
15

)

;’;f%f

DATA TRANSFER

COMPLETE

ABORT _

.
.
18

18
,

02
.22

08:

wyaup | ERROR | DETY

CHEck | CAkck [MSSED uasseus |MAsssus

LATE

£RROR

17
MASSEUS

A HON
Ll BARTY [NAEwHON

{;’"

-1

W18
7

ERAOR

STTUTE

liNTREACE | READ
|V

NOTE: WRITE | TO CLEAR BITS EXCEPT BIT 31 WHICH IS READ ONLY.

wnre300
NOTE

When set,
CPU

the tollowing bits

1IE

1is

set:

will

<19:17>,

interrupt

<16>,

<13:12>

the
and

<08>.
The following bits, when
set,
will
cause
the transfer to be aborted:
<11:09> and <07:00>.

<31>

{30>

DATA TRANSFER BUSY

This bit is set when a data transfer command is
received.
Read only.
It is cleared when a data transfer is aborted.
NO RESPONSE

This bit

CONFIRMATION

set

when the

MBA

received

no-response

confirmation
for
a read or write command.
It is cleared
by writing a 1 to this bit or INIT.
Setting of
this
bit

will

cause

retry of

the

command.

20-118

’

VAX

8600/8650

DESCRIPTION

RH780
<29>

(CRD)
Set when read data has a MASK field of 0001
indicates that the data has been corrected.
by writing a 1 to this bit or INIT.

<28:20>

RESERVED

<195

PROGRAM

This

is set when
transfer when a

Load MAP,

progress;

transfer

VAR,

Set

NON-EXISTING

the program

tries to:
1) Initiate
a
transfer is already in progress;

data

while

MBA

operation;

command.

data

maintenance

Initiate

cleared

transfer

mode

writing

This

bit

CONTROL PARITY
is
set
when

occurs.

<16>

ATTENTION

This

bit

cleared

FROM

MASSBUS

set

when

this

13>

Massbus

writing

transfer

bit.

parity

this

line on

error

bit.

the Massbus

RESERVED

DATA TRANSFER COMPLETED

bit is set when data transfer is
cleared by writing a 1 to this bit.

DATA TRANSFER ABORTED
This bit is set with the trailing
data
transfer has been aborted.

a l

<11>

in
data

assert
TRANSFER
It is cleared by

control
a

This

<12>

ERROR

the ATTENTION

asserted.

<15:14>

data

bit is set when the drive fails
to
within 1.5 us after assertion of DEMAND.
writing a 1 to this bit,
MASSBUS

during

illegal

DRIVE

This

<17>

(CRD),
which
It is cleared

ERROR

bit

data

<18>

CORRECTED READ DATA

to this bit or INIT.

DATA TRANSFER

completed.

edge

EBL
cleared

1is

when
the
by writing

LATE

This bit is set 1) for either a write data transfer
or
a
write
check
data
transfer
providing the data buffer is
empty when WCLK is sent to the Massbus, 2)
for a read data
transfer

received

<10>

WRITE

providing

from

CHECK

This bit

upper

byte
operation.

the

WRITE

This

CHECK

bit

lower
byte
operation.
INIT.

data

buffer

full

when

SCLK

UPPER ERROR

set when a
while

INIT.

<09>

the

Massbus.

compare error

detected

the
MBA
1is
performing
cleare
by
d writing a 1 to

write

this

the
check

bit

LOWER ERROR
set when a compare error is
detected
in
the
while
the
MBA
is
performing a write check

cleared

writing

this

bit

MISSED TRANSFER ERROR

This
us

bit

after

writing

set
data

when

no OCC

transfer

this

bit

20-119

SCLK

busy

INIT.

received

set.

within
cleared

50
by

VAX 8600/8650 REGISTER DESCRIPTION
RH780

BHTSO STATUS REGISTER
MIRA, 5T U

sk
OFFSET: 008
28

CORECTED
NO
DATA
;%2%5?58 RESPONSE | READ

CONFIRM JOATA

/;fé««z,f

DATA TRANSFER

COMFLETE ~ ABORT

LATL

PEAD
gRaoR | 2613
MASSBUS wappe | INVALID § corip-|
|Msseo MASSELS, | para
e | ynansren|
DATA
CHECK
CHECK || She
B
oA | g
PE
ERRORA
MATION | enure flflisfi}"kk TIMEOUT
o
ERROR

ERROR

1S READ ONLY.
NOTE: WRITE 1 TO CLEAR BITS EXCEPT BIT 31 WHICH

<07>

AR 14308

MASSBUS EXCEPTION

This bit is sect when EXC is received from Massbus.
cleared by writing a 1 to this bit or INIT.

<06>

MASSBUS DATA PARITY ERROR

This bit is set when a Massbus data parity error |is
detected during a read data transfer operation. It is
cleared by writing a 1 to this bit or INIT.

<05>

MAP PARITY ERROR

This bit is set when a parity error

read

data

from

the

map

detected

during a data transfer.

cleared by writing a 1 to this bit or INIT.
<04>

the

It is

INVALID MAP

This bit is set while reading a map register if the wvalid
bit of the next page frame number is zero and the byte
counter is not zero. It is cleared by writing a 1 to this
bit

<03>

INIT.

ERROR CONFIRMATION

This bit is set when the MBA receives error confirmation
for a read or write command on the SBI. It is cleared by
writing a 1 to this bit or INIT.

<02>

’

READ DATA SUBSTITUTE

This bit is set when the TAG of the read data received
from memory on the SBI is READ DATA SUBSTITUTE. It is
cleared by writing a 1 to this bit or INIT.

<01>

INTERFACE SEQUENCE TIMEOUT

This bit will be set for the following conditions: 1) SBI
arbitration is received and no ACK for the command
address, and write data (for a write operation) within
102.4 usec; or 2) ERR confirmation is received for a
command address. It is cleared by writing a 1 to this bit
or

<00>

INIT.

READ DATA TIMEOUT

This bit will be set if, starting from the acknowledge for
the read command address, read data is not received within
102.4 usec. It is cleared by writing a 1 to this bit or
.

INIT.

20-120

VAX 8600/8650

VAR
RLBA

VAR

RHT80 VIRTUAL ABDRESS REGISTER

OFFSET 00C

MAP POINTER
i

Note:

The

data

<19>
will

Address

in the RH780 Status
not be modified and

<31:17>

RESERVED

<16:09>

MAP POINTER
Select one of

attempt

the

data

256

should

to do

not

so will

PHYSICAL PAGE BYTE ADDRESS

transfer.

<08:00>

’

Virtual

The

set

virtual

transfer will

'
MAP

written

PROGRAM

during

ERROR

(bit
register

address
continue.

registers.

PHYSICAL PAGE BYTE ADDRESS
This field specifies the
byte

offset
into
the
current
(data)
page.
The
contents of the selected MAP register
and the value
of
this
field
are
used
to
assemble
a
physical SBI address to be sent to memory.

ALBA
174402

RLV1Z BUS ADDRESS REGISTER

]

BUS ADDRESS <15:01>
5

O
HAR-IBBT

The

Bus

Address

bit,

word—-addressable

with
a
standard
address
of
174402
for
the 16 bit QBus.
Bits
<15:00> can be read or written; bit <00> is usually written
as
0.
The
Bus Address Register indicates the memory location for the DMA
transfer during a read or write operation.
The register’'s contents
are
automatically
incremented
by
2
as each word is transferred
between the system memory and the controller.
Although

unused

expanded

for

(as

Bus

Address

<17:16>)

The

RLBA

on
an

the
18

to a

Extension)

VAX

bit

8600

LSI-11

bit

cleared

consocle,
Bus

using

LSI-11
bits

Bus

the

Address

<05:04>

by using

the

can
the

RLBAE

the

Bus

RLCSR

(RLV12

<05:00>.

initializing

20-121

Bus

bits

(BINIT L).

vAX 8600/8650 REGISTER DESCRIPTION
RLCSR
BLESR

RL¥1Z GONTROL STATUS REBISTER

174400

[ERRG% ERROR i
'

<15>

<14>

, E2

£1

DRIVE SELECT

CoN-

EXTENDED ADDRESS

FUNCTION CODE

INTEAUPT | BiTS

i l READY l
DRIVE

COMPOSITE ERROR

When set, this bit indicates that one or more of the error
bits
(bits <14:10>) are set.
Cleared by initializing the
bus by starting a new command, with the
exception
of
DE
and ERR if they were caused by a drive error.
Note:
When
an error occurs, the current operation terminates
and
an
interrupt
routine
is started if the interrupt enable bit
(bit 06 of the CSR) is set.
DRIVE ERROR
When set, it

an error.

indicates

bit

(bit

07)

buffered

the

Note:

selected drive

has

flagged

DE will

not set

ERR

(bit

15)

wuntil the usual occurrence of CRDY.

from the drive

CONTROLLER STATUS

Set by

that

The source can be determined by executing a get

status command.

CRDY
<13:10>

£0 DSQ D51 ;225%§R IEHABLE BA17 , BAIG l 2, f

ERROR CODE

COMPOSIT | DRIVE

error

interface

line.

This

ERRORS

the controller to

indicate

one

the

following

errors:

ERROR CODE

EO0O

1
0
0

1
0
1

0
0

0
1

1
1

0
0

0
0
0

0
1
1

BITS

OCTAL

ERROR

1
0

OPERATION INCOMPLETE
DATA CRC (DCRC)

0
1

NONEXISTENT MEMORY
PARITY ERROR ABORT

CODE

(OPI)

1
2
3
4
5
10
11

HEADER CRC (HCRC)
DATA LATE (DLT)
HEADER NOT FQUND (HNF)

(NXM)
(PAR ERR)

Operation incomplete indicates that
the
current
command
was not completed within the OPI timeout period of 550 ms.

A data CRC error indicates that
field

from the disk

A header CRC

error

an error was

indicates

while

found,

that while

from
the
disk
an
error
was
found.
performed on the first and second header
the

second header word

always

reading
reading

the

data

the header

The CRC check is
words,
although

Data late indicates that the FIFO RAM was more
than
full
and
the
controller
was
not able to read the
sequential sector.
This error may
occur
during
a
without header check command.

half
next
read

Header not found indicates that an
OPI
timeout
occurred
while
the controller was searching for the correct sector
to read or write.
A header compare did not occur.
A non-existent memory error indicates that
during
a
DMA
transfer
the
memory
location
addressed did not respond
with RPLY within

us.

A memory parity error abort indicates that a parity
error
was
detected
while
reading the system's optional memory
that has parity error checking.
If an error was detected,

the current command to the RLV12

20-122

is aborted.

VAX

8600/8650

DESCRIPTION

RLCSR

<09:08>

DRIVE SELECT
set,
these

When

bits
communicate
with
the
Cleared by initializing

<07>

CONTROLLER

Set

determine

which

<controller

the

via

the

drive
drive

will
bus,

bus.

READY

the controller at the completion of a
command,
at
detection
of
an
error, or by initializing the bus,
Cleared by software.
This bit indicates that the
command
in
bits
01-03 is to be executed.
Note:
Software cannot
set this bit because registers are
not
accessible
while
CRDY is 0.

the

<06>

INTERRUPT

Set

when

ENABLE

CRDY

interrupt
Note:

is asserted, bit 06
processor.
Cleared

the

This

interrupt

occurs

allows

the controller to
initializing the bus.

the

termination

command.,
Once
an
interrupt
request
1is
placed on the
LSI-11 bus, it is not removed until
acknowledged
by
the
LSI-11

<05:04>

processor

even

EXTENDED ADDRESS

BITS

These
18~-bit
and

05
17
of
writes
<03:01>

two bits
buses.

06)

indicate

the

command

FUNCTION
F2
F1
F1

COMMAND

0
0

0
1

MAINTENANCE MODE
WRITE CHECK

GET

0
1
1

1
0
0

1
0
1

SEEK
READ HEADER
WRITE DATA

READ

DATA

READ

DATA WITHOUT

executed.

0
1

2
3
4
5

CHECK

initializing the
starts when CRDY
software.

ready

CODE

STATUS

Cleared by

DRIVE

OCTAL

execution

When

cleared.

the upper-order bus
address
bits
for
These bits are read and written as bits 04
of the CSR.
They function as address bits
16
and
the
BAR.
Writing bits 04 and 05 of the CSR also
bits 0 and 1 of the BAE.
’

FUNCTION CODE
Set by software

are

HEADER

<00>

(bit

bus

(BINIT L).

Note:

(bit

Command

07)

CSR

cleared

the

READY

set
to

this

bit

receive

Cleared when
and set when

indicates
a

that

command

the
or

seek or head select
the seek operation is

20-123

selected
drive
is
valid read data.
operation
1is
started
completed.
supply

VAX 8600/8650 REGISTER DESCRIPTION
RLDA (GET STATUS)
RLOA

]

174404

RLVI2 DISK ADDRESS REGISTER (DURING A BET STATUS COMMAND)

> ®BOT U3ED DURING & GLT STATUS &

MUST BE A ZERD

1 RESET

géJST

aET

MAKER
BIY
1
A1 4842

The Disk Address Register is a 16 bit Read/Write
register
with
a
standard
address
of
174404,
Its
contents
have
one
of three
meanings, depending on the command being performed.
The
RLDA
is
cleared by

initializing the bus

(BINIT L).

RLDA during a GET STATUS command:

Both

the

RLCSR

and

the

RLDA

registers must be programmed to execute the GET STATUS command.
<15:08>

RESERVED

<07:04>

MBZ
Must

<03>

zcros

RESET

When this bit
register
of
the
<02>

MBZ

Must
<01>

is set, the
disk
drive
clears
its
error
soft
errors before sending a status word to

controller.

GET

zero.

STATUS

Must be a 1, indicating to the drive to
send
1its
status
word.
At
the
completion of the get status command, the
drive status word is read into the controller multipurpose
register
(RLMPR).
With
this
bit
set,
bits 08-15 are
ignored

<00>

the

drive.,

MARKER

Must

20-124

VAX 8600/8650

AL0A

ALViZ DISK ADDRESS REGISTER (DURING READ, WRITE OR WRITE CHECK COMMAND)

174404

CYLINDER ADDRESS DIFFERENCE <08:00>

RLO2

CAS

LA4

UA3

l HEAD

LAl

SELECT

SAl

SECTOR ADDRESS <05.00>
SAS

SA3

$A2

WR-14843

'The Disk Address Register is a 16 bit Read/Write
standard

address

meanings,

depending

174404.

the

Its

commands,

and

the

sector

<15:07>

READ,
the

address

WRITE

RLDA

the

cylinders

CHECK

loaded

sector

one

The

RLDA

commands:

with

head

For

select

three

these

information

transferred.

the RLDA sector address

one

lower,

increments by 1.

each

the

head

256

cylinders

(Octal

range

(disk

surface)

for

RLOl1

512

777.)

to be

selected:

track.

(Octal

upper.

SECTOR ADDRESS
Address of one
is

for RL02.

HEAD SELECT
Indicates which
=

<05:00>

WRITE
is

first

(BINIT L).

with

CYLINDER ADDRESS

Address

<06>

transferred,

have

command being performed.

cleared by initializing the bus
RLDA during

contents

the

sectors

to 47.)

20-125

range

VAX 8600/8650 REGISTER DESCRIPTION
RLDA (SEEK)

RLMPR (AFTER A GET STATUS)

BLY1Z DISK ADBRESS REGISTER (DURING A SEEK COMMARD)

RiBA

174404

RLUZ

ONLY

CYUINUER AUDRESS DIFFERENCE DF 08:00

OF6 ,

OF8 OF7

DFS DOF4 DF3

DF1 ,

DF2_

DFO

403

weao | must
SELECT | BEA

DIRECTON]

ZERD

BEA

MUST BE

MusT | MARKER

ZERG | ONE

AR 24840

The Disk Address Register is a 16 bit Read/Write register with a
Tts contents have one of three
174404.
standard address of
The RLDA is
meanings, depending on the command being performed.
cleared by initializing the bus (BINIT L).

will

program

The

command:

RLDA during a SEEK

execute

SEEK

command by loading the RLDA with the head select, direction to move
information.

and cylinder difference
<15:07>

CYLINDER ADDRESS

DIFFERENCE

Indicates the number of cylinders the heads are to move on

seek.

<06:05>

RESERVED

<04>

HEAD

SELECT

Indicates which head (disk surface)

=
03>

lower,

MB?Z
Must

02>

is to be selected:

upper

zero.

DIRECTION

to
is
This bit indicates the direction in which the seek
distance moved depends on the
actual
The
place.
take
cylinder address difference

(bits 07-15).

This bit is set when the heads move toward the spindle (to

It is cleared when the heads
a higher cylinder address).
move away from the spindle (to a lower cylinder address).
<01>

MBZ

Indicates to the drive that a seek

Must be zero.
is

hold
<00>

the

seek

applications.

MARKER

Must

BLY1Z MULTIPURPOSE REGISTER (AFTER A GET STATUS COMMAND)

aLMea
ERROR | ERROR | M€ | wur | FRRO
7

ERROR l CHECK

FRROR

06
S———

————

command

and that the other bits in the register

issued

being

STC_ .

STB . STA

Following the GET STATUS command, a status word is

stored

R 14845

the

RLMPR.
The
status
word
from
the
selected disk drive includes
an:
including
the drive,
information on the functional statc of

drive
<15>

errors.

WRITE

DATA ERROR

Indicates write gate was
asserted,
detected on the write data line.

20-126

but

pulses

were

VAX

8600/8650

:
<14>

HEAD CURRENT ERROR
Indicates that write

when write
<13>

WRITE

gate

was

current was
not asserted.

SEEK

detected

TIME

selected

SPIN

ERROR

Indicates
a
<10>

WRITE

heads

not

VOLUME

track within

spindle did not reach

that

turning

full

too

speed within

fast.

ERROR

that

ready,

was write

drive:

the

time,

GATE

Indicates

<09>

that

specific

was

the

OUT

Indicates that the heads did not come onto
specific time during a seek command.
<11>

DESCRIPTION

(AFTER A GET STATUS)

LOCK

Indicates write
1lock
status
unlocked; 1 = protected.

<12>

RLMPR

the write gate was
the

sector

pulse

asserted when

was

asserted,

the

drive

the

locked.

drive

CHECK

VC is set every time the drive goes into load heads state.
This
asserts
a drive error at the controller, but not on
the front panel.
VC is an
indication
that
the
program
does

not know which disk is present until it
serial number and bad sector file.
(The disk
been changed while the heads were unloaded.)

<08>

DRIVE

SELECT

<06>

DRIVE

HEAD

the

selection

detected.
u

type of disk drive:

= RLO1l,

the

head

when

the

cover

Asserted when

the

heads

are

BRUSH HOME
Asserted when

the

brushes

selected:

lower,

open

the

in place.

upper.

STATE

LOAD STATE

BRUSH

D et ©

it O bt

STA,

ek et D OO O

CODE

dust

cover

0OUT

MAJOR STATE

ok b

<02:00>

HEADS

bt bt €

<03>

= RLO2.

COVER OPEN
Asserted

<04>

SELECT

Indicates
05>

drive

TYPE

Indicates

read the
might
have

ERROR

Indicates multiple

<07>

has

SPIN

are

STB,

not

the

STC

UP
CYCLE

HEADS

SEEK

TRACK

COUNTING

SEEK LINEAR MODE
UNLOAD HEADS

(LOCK ON)

DOWN

20-127

disk.

over

DRIVE

LOAD

SPIN

over

the

disk.

1is

not

VAX 8600/8650 REGISTER DESCRIPTION
RLMPR (READ)
RLMPR (WRITE)
L]

RLVIZ MULTIPURPOSE REGISTER (READING THE MPA AFTER READ HEADER COMMAND)

174408

151 WORD

[

]

;

]

CYLINDER ADDRESS
CAB

CA7

CA6

CAS

CAd

SELECT
CA3

;

CAZ

;

cat

]

SAD

SECTOR ADDRESS

HEAD

CAD

SA5

SAd

SA3

SAZ

SA1

[

2N0 WORD

[ g l 0 l g I 0 l g l 0 l 0 l e l 1] l g l [ l g l 4] { |4

] } 0 l
IR0 WORD

]

l CRCS . CRCH4 . CRL13 . CrCiz CRCH1 , CRcie CRCS CRCB CRCY A CRCE . CRCS \ CRCE CRC3 . CRC2Z CRCY CACO
After a READ
HEADER
command
is
executed,
three
words
can
be
sequentially
read
from RLMPR.
The first word includes the sector
address, the head selected, and the cylinder address.
The
second
word

is all zeros.

The third word

is CRC computed over the header.

RLYIZ MULTIPURPOSE REGISTER (WRITING THE MPR TO SET THE WORD COUNT)

RLMPR

174406

ltlslsiwmzlwcn,wcm,wcas1wcea WCO7 | WCOB | WCOS | WCD4 | WCO3 | WC02 |, WCO1 | WCO
WORD COUNT

R 4804

RLMPR loaded with a word count:

Before starting a DMA transfer,

the RLMPR is loaded with

the

word

The program must load the RLMPR with the 2's complement of

count.

thé number of words to be
transferred.
The
bits
are described
below.
As
each word
1is transferred, the RLMPR is automatically
incremented by 1.
The READ or WRITE operation
continues
until
a
word
count
overflow
occurs,
indicating that all words have been
transferred.

The word count can range from 1 to 5120 data

count

1limited

words.

The

maximum

by the maximum number of sectors available (40)

and the maximum words per sector

(128).

Once written, the word count cannot
be
read
back.
Reading
the
RLMPR does not change the word count.
The word count is cleared by
initializing the Qbus

<15:13>

<12:00>

(BINIT L).

MUST BE ALL ONES
For word count 1n correct

range.

WORD COUNT

This is the 2'S complement of the total number of words to
be transferred.
The maximun count is 5120.

20-128

VAX

8600/8650

AXCS3

CONSOLE

o,
13

REMOTE

LOCAL

AXCS2 — DATA TERM READY
DATA

RXCS1

EMM

TERMINAL TERMINAL

RXCSO

INTERUPT .,

7 oo

ewmslE

777 7

7000

/5
MR -1 FREG

<31:24>

RXCS3

RESERVED

<23:20>

RXCS2

DATA TERM READY

Reserved

<19:16>

RXCS2

for

Other

DATA TERM

any

set,

the

any

the

above

bits

data

from

the

are

18>

EMM

Corresponds

set,

"Logical"

EMM Data

TERMINAL
Corresponds to the

are

device.

the CPU wants

Console

CPU.

CPU

ready

the

above

to disconnect

Subsystem

from

Data.

Line.

remote

services port

the

console.

LOCAL TERMINAL

<15:08>

RXCS1

<07:00>

RXCSO

to console

terminal.

RESERVED

DONE
Read

only

the CPU.
1Initialized to zero by
to
a
one,
this
bit
indicates
from the console, and that the data

When
set
available

of
the
RXDB.

source

INTERRUPT

ENABLE

by
When

is equal

Control

Block

RXCSO0

RESERVED

the

data

are

both

the console.
that data is

and
available in

the
the

1ID
IPR

Read/Write
console.

IE"

<05:00>

not

(19-16)
modem

Only

REMOTE

Corresponds

<06>

READY

CONSOLE DATA
Corresponds To

<07>

Interfaces.

Write

<19>

<16>

Resident

Logical Data Terminal Ready (DTR).
Initialized to zero by the console.

bits (19-16)
the modem.

17>

Console

the
the

CPU.
Initialized
to
=zero
by
the
logical AND of "RXCS DONE" and "RXCS

a CPU

(SCB)

interrupt

vector

20-129

"F8".

is generated via

System

VAX 8600/8650

RXDB

CONSOLE RECEIVE DATA BUFFER
29

AXDA3

<23:20>

RXDB3

Must

CONSOLE
GATA
_

EMM

REMOTE
LOCAL
TERMINAL TERMINAL
gt

RXDBO — DATA
2

l
.

MBZ
zero.

RESERVED

Must

<19:16>

///

RXDBT — DATA ID CODE

<31:24>

RXDB2 — LOGICAL CARBIER
/.

RXDB2

zero.

CARRIER DESTINATION

Read only by the CPU.
Initialized by the console based on
the
state
of the corresponding DTR Field <19:16> in RXCS
?gd the state of any modem connection associated with that
ine.

<19>

LOGICAL

CONSOLE

DATA

Because

this

bit will always
<18>

<16>

<15:12>

<11:08>

line

(no modem

involved)

this

lineé

(no modem

involved)

this

Remote

Line

involved)

this

set.

EMM

Because this is
bit will always
<17>

hard-wired

a hard-wired
be set.

REMOTE TERMINAL (RTY)
|
Indicate that the modem associated with
(RTY) is active.
LOCAL TERMINAL (CTY)
Because this is a hard-wired
bit will always be set.
RXDB1 Must be

line

the

(no modem

RESERVED

zero.

RXDB1 DATA ID CODE
Read only by the CPU.
Initialized to
Identifies
the
destination
of
the

zerov by

data

the console.
byte
in bits

<07:00>.

<07:00>

DESTINATION

00
01
02
03
04

Console Terminal
Remote Services Port
EMM Data
Logical Console Data
Reserved to DEC

Reserved

"Carrier"TM

DEC
Byte Has

RXDB0O - DATA
Read only
by
the
meanings
depending
DATA

ID CODE

CPU.
of

Changed

The
Data
Byte
has
different
the
destination specified by the

<11:08>,

20-130

VAX 8600/8650

RXDB

Data

Byte

Definitions:

Data

Source

RXDB
DATA

Console Terminal of
data
received

RXDB

Remote

byte

Services

data

<07:00>

from

(CTY).
Port

the

RXDB

received

contains a
byte
Console
Terminal

<07:00>

from the

contains

Remote

Services

Port.

Environmental
case
type

the

EMM

The format
follows:
7

Monitoring

RXDB

data

for an EMM

|TYPE | ASD |
Fmm———t

<07>

RXDB.

Byte

1is

EMM OPCODE ID
+

S
—

the
type
of
EMM
Opcode
in
bits <04:00>.
There are

types:

<07>
-

the

Data

Identifies

(RXDB)

contained

a—

that

two

Module (EMM) - In
this
is used to identify the

byte

bytes

OPCODE

TYPE

EMM

EXCEPTION

EMM

RESPONSE

EMM

EXCEPTION

OPCODES

indicate

that

the

EMM
1is reporting a status change.
All
Exception Reports consist of
a
single
data byte which
EMM

RESPONSE

EMM

1is

sending

oOr

that

the

running

power

cause

for

the

ASD (Automatic
EMM

and

sent

Shutdown)

type,

via RXDBO.
-

Indicates

Automatic

Shutdown

Timer

that

total

system

(RED ZONE Temperature

20-131

the

response

additional

shutdown
1is
pending.
of the condition is not

RESERVED

that

Response Opcode

bytes

RXDBO.

information.

If
the
rectified

Fault or AIR FLOW

Fault) the EMM will shutdown
when the timer times out.
<05>

via

indicate

information

information will
<06>

also

request

Depending
one

OPCODES

the

system

VAX 8600/8650

RXDB

COHBOLE RECEIVE DATR BUFFER
31

By by 1t

RXDBZ — LOGICAL CARRIER
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;

ittt byttt rsnser s

REMOTE
LOCAL
TERMINAL TERMINAL

DONSOLE

DATA

EMM

4
,,

tivuiivadi

dtiuiudissdioviomin

RXDBY — DATAID CODE
3

RXDBO — DATA
2

13841

RXDB
DATA
-

Data

—
-

Source

(Continued)
<04:00>

EMM OPCODE ID
Used
in. conjunction
with
bit
<07> to identify the type of
EMM data that follows in the next RXDBO
byte transfer.
If set, <07> bit
1indicates
that
this
field
contains an EMM Exception Opcode
and

single

byte

data

follows

describes the exception.
the EMM Exception Opcodes
the associated data byte.
If

clear

field

<07>

DATA

BYTE

the

associated

bytes.

this
case
RXDBO
identifies the type of
follows via additional

DESCRIPTION

<07:00>

Returned_Warm_Flag

<06:01>

RESERVED
0

= Warm_Flag

Warm Flag

Clear

Set

<07:00>

Returned_Cold_Flag

<06:01>

RESERVED
0 = Cold_Flag

clear

set

<00>

data

BITS

<00>

= Cold_Flag

00
01
02

<07:00>

Returned
UCODE Version

<07:00>

Version

00
01

<07:00> Returned_Array_ Config
<07:00> Array slots (n+l) in use

this

bytes of
data
follows
the exception.
Table 2
Response
Opcodes
and

transmissions.

HDR

that

and one or more
that
describes
lists
the
EMM

Logical
Console
Data.
contains a Header ID that
Logical Console data that
RXDBO

indicates

an EMM Response Opcode

describes

bit

that

Table 1 lists
and describes

contains

<07:00> Version Lower 8 Bits
Upper

bits

<01:00>

Array

type

slot

<03:02>

Array

type

slot

3
4

<05:04>

Array

type

slot

<07:06>

Array

type

slot

20~132

VAX 8600/8650

RXDB
ID

Data

Source

(Continued)
HDR

DATA

BYTE

BITS

DESCRIPTION

<01:00> Array
<03:02> Array
<05:04> Array
<07:06>

Array

type
type
type
type

ARRAY

TYPE

in slot 5
in slot 6
in slot 7
in slot 8

ARRAY

CODES

0
1

Slot empty
16 Megabyte

04 Meagbyte
Reserved

array
array

<07:00>

Console Command String Complete
The
Conscle
has
successfully
completed executing the CCS

00
01

<07:00>
<07:00>

Returned_ Last_VAX PC
VAX PC <07:00>

<07:00>

02
03

<07:00>

VAX PC
VAX PC
VAX PC

<07:00>

Returnei_Last_CS&fiStatus

<07:00>

CSM

02
03
04

<07:00>

Snapfile_Status_Returned
The
data
byte
indicates
validity of the snapshot files

<07:02>
<00>

RESERVED

Status

<07:00>

<15:08>
<23:16>
<31:24>

<01>

<15:08>
<23:16>
<31:24>

CSM Status
<07:00> CSM Status
<07:00> CSM Status

<07:00>

0
1

Wow

DATA

SNAP1.DAT
SNAP1.DAT
SNAP2.DAT
SNAP2.DAT

Invalid
Valid
Invalid
Valid

Console_Reboot_Successful

Response

successful

VMS

after

console

reboot

initiated by a MTPR CRBT.
82

<07:00>

Console Command_String Error
Indicates that:
e

the

Console

encountered

error
while
trying
to
execute an Console
Command
String (CCS) or,
e

the
CCs
was
rejected
because
the
CCS
exceeded
the 512 byte console buffer
space

the

or,

console

locked

via

the terminal control switch
20-133

VAX 8600/8650

RXDB
Rxpe

CONSOLE RECEIVE DATA BUFFER
3

" R%DE3
7

747

RXDB1 — DATA 1D CODE

;

CONSOLE

457

EMM

REMOTE

LOCAL

MXDDE - LOGICAL GARRILA

—

DATA

RXDBO — DATA

TERMINAL TERMINAL

TABLE

EMM

EXCEPTION

5243

REPORTS

Use

this table to interpert the
meaning
of
the
Opcode
1in
bits
<04:00>
if
bit
<07> is set.
1In addition to listing the Opcodes,
this table also describes the meaning of the contents of
the
data
byte associated with each Opcode.

OPCODE

EXCEPTION

TYPE

Status Change in Regulator A +5v
The contents of the Data
Byte
associated
Opcodes

in the

through A

indicates

that

the

with
this
and
status has changed

following manner:

DATA
BYTE

BITS

<07:01>

MEANING

<00>

Status

Change

Byte

Regulator C

definition:

See

00.

+5v

OPCODE

00,

Status Change in Regulator D -2v
Data Byte definition:
See OPCODE

00.

Status Change
Data

Normal
out of

Status Change in Regulator B +5v
Data Byte definition:
See OPCODE

Data

RESERVED
0 = Voltage
1 = Voltage

Byte

Regulator

definition:

=-2v

See OPCODE

00.

Status Change in Regulator F -5.2v
Data Byte definition:
See OPCODE 00.
Status Change in Requlator H -5.2v
Byte definition:
See OPCODE 00.

Data

Status
Data

Change

Byte

Regulator

definition:

L +12v
OPCODE

00.

Status Change in Regulator L -12v
Data Byte definition:
See OPCODE 00.
Status

Change

in Regulator K

Data Byte definition:
0A

See

Status
Data

Change

Byte

+15v

See OPCODE

00.

Regulator K -15v
See OPCODE

00.

definition:

20-134

Spec.

VAX

8600/8650

TABLE
OPCODFE

EMM EXCEPTION

EXCEPTION

Status

REPORTS

(continued)

TYPE

Change

The Data Byte
indicates the

Temperature

associated with the OPCODE
following status change:

ID's

through

DATA
BYTE

MEANING
-

<07:02>

RESERVED

<01:00>

Temperature

ocC

Status
Data

Status

Change

Byte

meaning:

Normal

Temperature in Yellow Zone
Temperature in Red Zone.
This
will
result
in
an
automatic shutdown if
not corrected.
Temperature Below Nominal Range

Temperature

See

meaning:

Status Change in T3
Data Byte meaning:

Data

Change

Byte

Woun

ID 0OB.

Tcmperature

See

OB.

Temperature

See

ID 0B.

Status of Delta T2-T1 has Changed
The Data Byte associated with the OPCODE
indicates the following status change:

ID's

through

DATA

BYTE

BITS

S W SO T

MEANING

i
v

<07:02>

RESERVED
O
Difference

<01:00>

1
2

Status

Data

Delta

T3-T1

Byte meaning:

Status

Delta

T4-Tl1

Normal
in Yellow Zone
in Red
Zone.
an
automatic

Difference
Difference
result
in
not

corrected.

has

Changed

See

Data Byte meaning:

Huh

ID OF.

has

See

This
will
shutdown if

Changed

OF.

Status of AIR FLOW SENSOR 1 has Changed
The Data Byte associated with the OPCODE
indicates the following status change:

ID's

and

DATA
BYTE

BITS

<07:01>

<00>

MEANING
RESERVED
O

= Air Flow Normal
= Air Flow
out
of
result
in
an
not corrected.

Status of AIR FLOW SENSOR 2 has
Data Byte meaning:
See ID 12.

20-135

spec.

automatic

Changed

This

will

shutdown

VAX 8600/8650 REGISTER DESCRIPTION
RXDB

CONSOLE RECEIVE DATA BUFFER
24

REMOTE

LODCAL

RXDB2 — LOGICAL CARRIER

RXDB1 — DATA 1D CODE
3

TABLE
OPCODE

1 -

‘

CONSOLE

EMM
a2

DATA

TERMINAL TERMINAL

RXDBO ~— DATA

Dslnz‘m‘ml

EMM EXCEPTION REPORTS

(continued)

EXCEPTION TYPE

Status of
with this

BBU Availability has Changed.
ID has the following meaning:

DATA

BYTE

BITS

A
MEANING

<07:01>

RESERVED

<00>

’

= BBU

available

= BBU

not

Byte

available

EMM STATUS CHANGED - Except for the case where the
EMM
dead,
the
EMM
1is rebooted by the console when any of
following

errors

<07:04>
<03:00>

is
the

occur.

RESERVED
O = EMM Dead

(failed

EMM encountered

EMM

3
4
5

6
7
8

restart)

RAM parity

encountered

error

illegal
instruction
= EMM encountered an unknown trap to 0
= EMM encountered an unexpected trap
= EMM
encountered
an
unexpected
6.5
interrupt
= Excessive collisions on EMM bus
= No transport acknowledge from EMM

9 =
A =

response

from EMM

Negative response from EMM
EMM has no buffers available

B = CSL to EMM message transmit
16

associated

timeout

TX_RDY TIMEOUT - The TXCS RDY bit has not been set
by
console for 2 seconds.
Operation in progress aborted.

the

DATA
BYTE

BITS

MEANING

<07:01>
<01:00>

RESERVED

1
2
3

Local terminal operation aborted
= Remote
services
port
operation
aborted
= EMM operation aborted
= Logical console operation aborted

20-136

VAX 8600/8650 REGISTER DESCRIPTION

RXDB

TABLE 2 - EMM RESPONSE REPORTS

in bits
Use this table to interpret the meaning of the Opcode
Opcodes,
<04:00> if bit <07> is clear. In addition to listing the the
data
the meaning of the contents of
this table also describes
bytes associated with each Opcode.

NOTE

The first data byte following the RXDB is always
byte

count.

INDICATION

RESPONSE TO "EMM STATUS - This operation returns the status
of the EMM status registers and PROM revision number. This
response consists of the following 8 Data Bytes.

BYTE

0
1

BITS

MEANING

<07:00>

Packet size = 8 bytes (10)
+5V BBU *
+5V SBIA *
-2V ECL *
-2V ECL *

<05>

<07>

BBU disable

<00>

MARGIN ENABLE REGISTER
Regulator A +5V CSL *

<05>

Regulator F

<04>

<06>

<01>
<02>
<03>
<04>

<06>

<07>

<00>
<01>
<02>
<03>
<04>
<05>
<06>

<07>

POWER CONTROL REGISTER

Regulator B
Regulator C
Regulator D
Regulator E
Regulator F
Regulator H

<00>
<01>
<02>
<03>

<00>
<01>
<02>
<03>
<04>
<05>
<06>

<07>

Regulator J

+5.2 ECL *

(unused)

Regulator B
Regulator C
Regulator D
Regulator E

+5V BBU *
+5V SBIA *
-2V ECL *
-2V ECL *

Regulator H

+5.2 ECL *

‘Regulator J

(0 = regulator off

1 = Margin Enabled

1 = MOD OK

** 0 = enabled

+5.2 ECL *

(unused)

MARGIN SELECT REGISTER

Regulator A +5V CSL *
Regulator B +5V BBU *
Regulator C +5V SBIA *
Regulator D -2V ECL *
Regulator E -2V ECL *
Regulator F +5.2 ECL *
Regulator H +5.2 ECL *

Regulator J

(unused)

MODOK REGISTER

Regulator A
Regulator B
Regulator C
Regulator D
Regulator E
Regulator F
Regulator H

Regulator J

+5V CSL *
+5V BBU *
+5V SBIA *
=-2V ECL *
=2V ECL *
+5.2 ECL *
+5.2 ECL *

(unused)

20-137

VAX 8600/8650

RXDB

RiDB

GONSOLE RECEIVE BATA BUFFER

PR 21

BXDB3

1§

Z
14

;

Z ; 7 /jff/

CONSOLE

DATA

RXDBY — DAYA 1D CODE

sicdias

TABLE
ID
s cowe w— —

EMM

REMOTE

LOCAL

EMM TERMINAL TERMNAL
02

RXDB0 — DATA

RESPONSE

REPORTS

(continued)

INDICATION
DT

N T

(Continued)
BYTE

BITS

MEANING

MODOK REGISTER
Regulator K OK

<01>

Regulator

<02>

Module

<03>

Module

<00>

K AC
L AC

LO
LO

<04:06>

EMM

unit

<07>

Key

OVERRIDE

*
**

1 = MOD OK
0 = KA86xx

number

Air

Flow

BBU

unit

<02>

Minus

2V
Flow

circuit

MISCELLANEQUS

<00>
<01>

status

HARDWARE

Sensor

STATUS

Status

= failure)
CROBAR fault (1

<03>

Air

<04>

Latched

<05>

LO)

Latched

<06>

LO)

Parity

Bit

Parity

Error

<07>
7

Sensor

Status

MISCELLANEOUS
<00>

External

<01>

Default

<02>

Process

<03>

<04:07>

SOFTWARE
Output Signal

fault)

= crobar)
(1 = fault)

STATUS REGISTER
(1 = asserted)

Mode

Enable (1 = enabled)
Abort (1 = active)
Interrupt Disable (1 = disabled)

Reserved

EMM

<07:00>
01

RXDB2
— LOGICAL CARRIER
;

Response

PROM VERSION NUMBER
Integer value of the EMM PROM

version

System
Environment
Information
Request.
This
operation
returns
32
bytes
which
reflect
all
measured
environmental information, which includes the voltage outputs

all

regulators

and

temperature

Sensors.

20-138

measurements

all

VAX

8600/8650

DESCRIPTION
RXDB

TABLE 2 - EMM RESPONSE REPORTS (continued)
ID

INDICATION

)

(Continued)
NOTE

values returned are in their digitized format

the formulas
using
converted
must
be
interpreted.
below before being displayed or
each entry
for
parentheses
in
number
The
to
wused
be
must
equation
indicates which
and

perform the conversion.

BYTE

.0276 * MAGNITUDE

Volts =

Milliamps = 70 + (2.8 * MAGNITUDE)

Volts = .0762 * MAGNITUDE

Volts =

Degrees Celsius = 16 + (.3333 * MAGNITUDE)

All numbers in equations are decimal.

.0691 * MAGNITUDE

BITS

MEANING

<07:00>

Packet size = 32 bytes (10)

<07:00>

REGULATOR A (+5V TTL) Magnitude
See

<07>

note

REGULATOR A (+5V TTL)

0 = Positive Polarity
1 = Negative Polarity

Polarity

<06:00>

Reserved

<07:00>

REGULATOR B (+5V BBU) Magnitude

<07>

REGULATOR B (+5V BBU) Polarity

See Note

<06:00>

See Byte 2
Reserved

<07:00>

REGULATOR C (+5V SBIA) Magnitude

<07>

See Note

REGULATOR C (+5V SBIA)
See

Byte

Polarity

<06:00>

Reserved

<07:00>

REGULATOR D (-2V ECL) Magnitude

<07>

See Note

REGULATOR D (~-2V ECL)

<06:00>

See Byte 2
Reserved

<07:00>

REGULATOR E
See

Note

20-139

(-2V ECL)

Polarity

Magnitude

VAX 8600/8650

RXDB

CONSOLE RECEIVE DATA BUFFER
28

RRUBZ — LUGIAL GARRIER

CONSOLE
DATA

Efi%fi%%%%%%%%%%% 3

EMM

RADBO — DATA

RXDB1 — DATA 1D CODE

TABLE

RESPONSE

REPORTS

(continued)

INDICATION

(Continued)
BYTE

BITS

<07>

MEANING

REGULATOR E
See

Reserved

<07:00>

REGULATOR F

<07>

Reserved

<07:00>

REGULATOR H

<07>

(-5.2V ECL)

Polarity

(-5.2V ECL)

Magnitude

(-5.2V ECL)

Polarity

REGULATOR H
See Byte
Reserved

<07:00>

GROUND CURRENT Magnitude

<07>

Note

GROUND CURRENT Polarity
0 = Positive Polarity
1 = Negative Polarity

<06:00>

Reserved

<07:00>

REGULATOR L
See Note 3.

<07>
<06:00>

<07:00>

<07>

(+12V TTL)

Magnitude

REGULATOR L (+12V TTL)
Always Positive (i.e.,

Polarity
0)

REGULATOR L
See Note 4.

Magnitude

Reserved

(=12V TTL)

Polarity
1)

<06:00>

REGULATOR L (=12V TTL)
Always Negative (i.e.,
Reserved

<07:00>

REGULATOR K

Magnitude

See

Magnitude

<06:00>

See

Note

(-5.2V ECL)

<06:00>

See

Byte

Polarity

REGULATOR F
See

Note

(=2V ECL)

<06:00>

See

Byte

<07>
<06:00>

Note

(+15V TTL)

REGULATOR K (+15V TTL)
Always Positive (i.e.,
Reserved

20-140

Polarity
0)

REMOTE

LOCAL

TERMINAL TERMINAL

VAX 8600/8650

TABLE
ID

EMM

RESPONSE

REPORTS

(continued)

INDICATION
-

——

(Continued)

BYTE

BITS

MEANING

<07:00>

REGULATOR K

See

07>

Note

(-15V

TTL)

REGULATOR K (-15V TTL)
Positive (i.e.,

Always

<06:00>

Reserved

<07:00>

THERMISTOR
See

<07>

Polarity

<06:00>
<07:00>

THERMISTOR

(T2)

Magnitude

(T2)
Negative

Polarity
(i.e., 1)

<07>

Note

<06:00>

Reserved

<07:00>

THERMISTOR

<07>
<06:00>

Reserved

<07:00>

THERMISTOR

<07>
<06:00>

(T3)

Magnitude

THERMISTOR (T3)
Always Negative

Polarity

(i.e.,

(T4)

Magnitude

THERMISTOR (T4)
Always Negative

Polarity
(i.e., 1)

See

Note

(i.e.,

THERMISTOR

See

Magnitude

(T1)
Always Negative
Reserved

Always

(T1)

Polarity
1)

THERMISTOR

See

Note

Magnitude

Note

Reserved

20-141

—

VAX 8600/8650 REGISTER DESCRIPTION
SBIA CONFIGURATION

CONFIGURATION REGISTER
2008 000, 2208 0000

]

)

Fid

FL]

Fii)

[ 4]

MEMORY SEPARATOR
i

;

]

<29:20>

MEMORY

REVISION

ABUS ADAPTER TYPE SBIA
o

MBZ

<31:30>

[+]

(SS28)

zero.

Must be

SEPARATOR

S5S28 MSR <27:18>

This field defines the memory address boundry and is equal
to the number of megabytes of memory addressable over the
of
MBytes
512
are
there
If bit 29 is asserted,
ABus.
memory and bits <28:20> are disregarded when the hardware
in
checks the DMA address. These bits are bits <29:20>

the Memory Separator register, but within the SBIA they
are shifted right by two bits to match the physical
address.

<19:08>

MBZ

(SS36)

<07:04>

ABUS ADAPTER TYPE

Must be

zero.

BUS REG D<07:04>

(SsS28)

These bits identify the type of ABus adapter, 0001 for the
SBIA.

<03:00>

ABUS ADAPTER REVISION

BUS REG D<03:00>

(SS28)

These bits identify the

these bits are hardwired.

revision

20-142

the

ABus

adapter;

VAX

8600/8650
SBIA

CONTROL

STATUS

CONTROL AND STATUS REGISTER
2008 0004, 2208 0004

31
.

- 30
EMABLE

§:§§§Zw ?}i%ffis

I3l

;EELES

- ‘Zisfo'“':LE”E:"’ o

ENABLE

CPU TR SELECT

a/w

RAW

[£74

[&]

<31>

<30>

MASTER

INTERRUPT ENABLE
SS29 MSTR INTR ENA
When
set,
this
bit
will
prioritize
the
interrupts
interrupt priority level for
ENA SBI

CYCLES

access

SBI

access

NEXUS

error

condition,

SBI

will be set.
<29>

ENA SBI

CYCLES

SS29

ENA SBI

bit must

not

and

00,

all

set,

and

with

ERROR SUMMARY

DMA

will

not

ZERO (Ss33)
This read only

<27:24>

CPU

TR SELECT

CPU

TR SEL

set

activity

SBIA

respond
response).

bit

will

for

through

not

contents

SBI

select
this

ZERO (Ss36)
These bits are

fill

normal
the

<20>

to
an

and

<19>

operation.

SBIA.

commands

always

this

bit

SBI

function

(SBI

confirmation

codes

zero.

(SS07)

visibility

the

SBI

field

the

read

level,
<23:00>

the

attempts

reset,

<08:04>

It enables

the CPU
bit

recognize

These bits provide backplane
to

If
this

also

<28>

used

operation.

registers.

the

will

for normal

NEXUS

See description of ERROR SUMMARY register.

This

enables

the
SBA
module
to
and
generate the appropriate
CPU polling.

oOUT

SS29 ENA SBI OUT
This bit must be set
CPU

enable

always

logic.

20-143

for
two's

CPU

the

jumpers

transactions.

complement

zero provided

the

The
TR

=zero

VAX 8600/8650 REGISTER DESCRIPTION
SBIA DIAGNOSTIC CONTROL REGISTER
DIAGNOSTIC CONTROL REGISTER
2008 000C, 2208 000C

]

<31:20>

MBZ

20
4]

DMAC

DMAB

OMAA

DMAL

FOHLE !;&!A ?RANS;iTSDN &JFéER 8UsY

ADDRESS | MENT
WO

FORCE |

FORCE

TIMEOUT

DATA

MODE

ERROR

TIMEOUT

A/w

B/w

zero.

FORCE DMA TRANSACTION BUFFER BUSY

SS29 FORCE DMAC (DMAB, DMAA, DMAI) BUSY
into specific
These bits are used to direct DMA traffic
forcing other buffers to be
by
DMA transaction buffers

MBZ

effect

DMA

(SS32)

Must
<08>

DISABLE | pyap

The state of these bits has
busy.
transaction already in progress.

<15:09>

(SS36)

Must be

<19:16>

}

o |SB" | She. | e | o 1SS | WoRo | sack | eammy ?&323’

0 } 0

zero.

CLEAR SILO ADDRESS

SS19 CLR SILO ADR

When
setting.
This bit will clear the silo address upon
always be zero
bit will
this
read,
1is
register
this
(hardwired).
07>

DISABLE SILO INCREMENT
S529 DISABLE SILO INC

Wwhen set, this bit will prevent the silo address from
This bit will be reset during normal
incrementing.
This
operations to allow the silo address to increment.
is also read as

bit

<06>

zero.

DIAGNOSTIC DEAD
S$S29 DIAG DEAD

DEAD,
ABUS
simulate
it will
When this bit sets,
ABUS DEAD
the console and causing a reboot.
interrupting
read
also
This bit is
is normally asserted by SBI FAIL.
as

<05>

zero.

MBZ
Must

<04>

(SS30)
be

zero.

DISABLE SBI TIMEOUT
SS29 DISABLE SBI TMO

When set for diagnostics, this bit will prevent a timeout
for the SBIA to gain control of
condition while waiting
NEXUS

the SBI, while waiting an acknowledgment from a

while waiting for CPU read data.
<03>

FORCE QUADWORD DATA
§S529 FORCE QUAD DATA

(Loop
This bit is used by microdiagnostics with bit <02>
to provide a way to use a quadclear to loop
Back Mode),
then the
FORCE QUAD DATA is set,
data back on the SBI.
CPU will execute a quadclear, but for microdiagnostics,
the address will be a memory address
address

(bit 27

is clear).

20-144

instead

SBI

VAX

8600/8650

SBIA

The ABus command/address
write
to
the quadclear
the

same

memory

except

for

(cache)

DIAGNOSTIC

CONTROL

is the same; it specifies
a
CPU
register.
The ABus write data is

the

address,

address.

When

which

will
be
for
command/address

the

a
is

transmitted on the SBI it will be received by the SBIA,
as
it
always
1is, but in this case, the address will be less
than the configuration register.
To
the
SBIA
it
looks
like
a
DMA
extended write mask to memory and it will be
handled as such.
For

normal

zeros.

quadclear,

A-Data

this

Assembly

the

case,

write

FORCE

Multiplexers

data
QUAD

data

longword

transceivers,

<02>

bits

will

allow

LOOP

BACK MODE

the

is
27

all

the

Data,

1011

SBI.

When

the

will

data

the

contents

toggled

bits

all

enable

Write

transferred

and

setting

forced
will

transfer

the
Write
Data
Latch (the ABus
Quadword Boundary Address) to the

write

is
DATA

the

second

the

SBI

(set).

the

and

This

SBI.

5529
This

LOOP BACK MODE
bit is used by microdiagnostics to allow a
CPU
read
or
write
to be looped back in the SBIA.
The PAMM has to
be configured such that a memory (cache) address is
mapped

to
an
bits 27

I/0
adapter,
and the same PAMM address, but with
and 28 inverted, is mapped to a memory address.

In the SBTA, LOOP BACK MODE will invert
address
bits
and
26, if bit 27 is reset, which will be the case if
CPU write is to a memory address.
When

the

I/0

adapter,

write

CPU

data

carry

writes

a memory

out

the

command/address

inverted.

that

file.

normal

CPU

from

the

is mapped

the MBox will write the command/address and

longword

latch
to
the
address bit 27

location

25
the

into the

command

SBI,
is

transferred

because

reset,

LOOP

address

write.

When

the

command/address

BACK

bits

The SBIA will

MODE
and

set

and

will

The command/address, followed by the write
data
will be
transmitted
on
the
SBI.
When
the SBIA clocks the SBI
receivers and looks at the received data, the
address
is
less
than
register),

data

the

the memory
separator
(in
the configuration
it will transfer the command/address and
write
register

file

and

request

MBox

service.

The MBox will write
the
data
into
memory
because
the
address,
with
bits 27 and 28 inverted (bits 25 and 26 in
the SBIA), addresses
a
different
PAMM
location.
This
location is mapped to memory.

This diagnostic bit can also be used with a CPU read
$imilar manner

<01>

FORCE

STATE

PARITY

further

check

out

the

SBIA

ENABLE

SHORT

error

ENA SHORT TIMEOUT
set, this bit will enable an SBI
timeout
cycles instead of the normal 512 cycles.
This
a

will

TIMEOUT

SS29
When
as

ERROR

SS29 FORCE STATE PTY
If this bit is set, a state machine parity
forced during the CPU ARB WAIT state.
<00>

logic.

zero.

20-145

SBI

bit

read

VAX 8600/8650 REGISTER DESCRIPTION
SBIA DMA COMMAND/ADDRESS REGISTER
DA COMMAND/ADDRESS REGISTER
DMAI

2008 0010
22080010

20080018

DMAC

2008 0020

22080018

2008 0028

22080020

2208 0028

RECEIVED S8! COMMAND/ADDRESS

RECEIVED $BI COMMAND/ADDRESS

nyd

MR- 14853

DMAICA)
These four registers (DMAACA, DMABCA, DMACCA, and
are used to save information about transactions in the DMA
Each time a command/address is loaded into a DMA
buffers.
copy of the command/address and SBI ID of the
a
buffer,
to
corresponding
commander is saved in the two reglsters
If an error is dectected by the MBox or
DMA buffer.
the
two
the
confirmed,
1is
transaction
the
the SBIA after
registers

<31:00>

are

locked.

RECEIVED SBI COMMAND/ADDRESS
BUS REG <31:00> (SS32, SS33)

Each

time

command/address

1loaded

into

DMA

transaction buffer in the DC022, that command/address is
also loaded into the corresponding DMA Command/Address
These error registers are actually TTL
register.
error
register files that are addressed by the upper two bits of

SBI B <31:00> are written in
address.
DC022 write
the
command
these registers, with bits <31:28> being the SBI
These error
and bits <27:00> the longword address.
codes
DMA
a
detects
registers are locked if the SBIA or MBox
error.

20-146

VAX

8600/8650

DESCRIPTION
SBIA

DMA

DMA ID REGISTER
DMAL

2008 0014

2208 6014

DMAA

2008 001C

DMAB

DMAC

2208 0024

2208 002C

2008 0024

2208 001 C

2008 NI

]

[¢]

[}

These
are

four

used

registers

buffers.

save

(DMAAID,

information

BECEIVED 5BIID

DMABID,
about

Each

DMACID,

and

transactions

time a command/address is
copy
of the command/address

loaded

DMAIID)

the

DMA

into

a DMA
and SBI ID of the
in the two registers
corresponding
to
1If an error is dectected by the MBox or
the SBIA after
the
transaction
is
confirmed,
the
two
registers are locked.
buffer,
a
commander
is saved
the
DMA
buffer.

<31:08>

MBZ

(58536)

Must

' <07:00>
i

zero.

RECEIVED SBI IDENTIFICATION
REG <07:00> <S823)
Each
time
a
command/address

BUS

transaction

buffer

the

1is

DC022,

1loaded

the

into

SBI

same

way,

also

DMA
loaded

into the corresponding DMA ID error register, an extension
of
the
DMA command/address error registers.
These error
registers are TTL register files like the
command/address

error

registers,

two

bits

the

inputs

zero.

the

at
Bits

and

DC022

addressed

write

<04:00>

are

the

address.

ground potential

loaded

Bits

they will
with

REC

the

upper

<07:05>

have

always
SBI

Like
the
DMA
command/address
error
registers,
registers are locked if the SBIA or
MBox
detects

error.,

20-147

read

<04:00>.

these
a
DMA

VAX 8600/8650 REGISTER DESCRIPTION
SBIA ERROR SUMMARY
ERROR SUMMARY REGISTER
2008 0008, 2208 0008

COMMAND

o2z

LENGTH/STATUS

o1,

DMAC TRANSACTION BUFFER
OX
s8
SBIA
o
DETECTED |DETECTLD | DETEGTED
A/DPE _ |CNTRL PE |ERROR

CPU

ERROR | ERROR

LOCK

RIW

DMAB TRANSACTION BUFFER
MBOX
8IA
5BlA
DETECTED | DETECTED | DETECTED
A/DPE | CNTAL PE ERROR

MULTIPLE

|ceu
ERROR

RAW

287 14953

the
of
most
contains
The error summary register
information about errors which have been detected by the
SBIA on transactions involving the SBIA.

<31:28>

COMMAND <03:00>
BUS REG D<31:28> (SS26)

These bits represcnt the ABus command bits for a CPU
They are loaded each time
register read/write.
command/address latch is loaded, and are latched by
ERROR LOCK,

<27:26>

1/0
the
CPU

bit <23>.

LENGTH/STATUS <01:00>

’

BUS REG <27:26> (SS26)

1/0
These bits represent the ABus data length for a CPU the
They are also loaded each time
register read/write.
command/address latch is loaded, and are latched by CPU
ERROR LOCK,

bit <23>.

<25:24>

MB2Z
Must be

<23>

CPU BUFFER ERROR LOCK

zero.

§S37 CPU ERROR LOCK

This bit will be asserted for any of the following

errors

on a CPU 1/0 read/write.

22>

A/D Parity Error (bit <22>)

Control Parity Error (bit <21>)

Address Error (bit <20>)

CPU read/write timeout on SBI (SBI Error Register

SBI Error (SBI Error Register <08>)

bit

<12>)

If this bit is set, Error Summary Register <31:26> and the
Timeout Address Register are latched. If clear, these
Writing
bits will represent the most recent transaction.
this bit will clear Error Summary Register <22:19,16>.

CPU A/D PARITY ERROR
SBAN A/D PTY BAD

This bit is set if a parity error is detected on the
address/data bits of the command/address or write data for
a CPU I/O read/write. If the error is detected on the

is
command/address, bit <19> will also be set. Parity bit
checked on the output of the file data latch. If this CPU
sets,

bit

writes bit

<23> is set.

<23>.

This bit is cleared when the

20-148

VAX

8600/8650

<21>

CPU

CONTROL

SBAN

PARITY

DESCRIPTION

ERROR

SUMMARY

ERROR

CNTRL PTY BAD

This bit

set

parity

error

detected

the

control
field
of the command/address or write data for a
CPU 1I/0 read/write.
If
the
error
1is
detected
on
the
command/address
cycle, bit <19> will also be set.
Parity

is checked on the output of the file data latch.
If
this
sets, bit <23> is also set.
This bit is also cleared

bit

when

<20>

the

CPU

writes

bit

<23>.

CPU ADDRESS ERROR
SS38 LOCAL ADR ERR

This bit is set if the CPU
accesses
a
nonexistent
SBIA
register
or
when
an SBI NEXUS register is accessed when
Control/ Status Register <30> is clear (CPU access
to
the
SBI is disabled).
When it sets, it will set bit <23>, and
it is cleared when the CPU writes bit
<23>.
This
error
will
be
detected
when
the
command/address
word
is
available, so bit <19> should also be set.

<19>

ERROR
SBAN

DETECTED ON
ERR ON

COMMAND/ADDRESS

This read only bit
is
parity,
or
address
command/address

bit

<23>.

one

<18>

cycle.

This

bit

The

<23>.

address/data,
control
is
detected
on
the
setting of this bit
will
set

reset when the CPU writes

STATE MACHINE PARITY ERROR
SBAO FORCE PARITY TRAP
This error bit will be set if the state machine
microword
does
not
contain
even
parity.
The occurrence of this
error will cause a CPU transaction to be
aborted,
if
one

progress,

progress

MBZ

and

will

generate

can occur
not

set

bit

interrupt.

CPU

A state

transaction

<23>.

(SS33)

Must
<16>

set
if
error

bit will

machine parity error

<17>

CYCLE

C/A

zero.

MULTIPLE CPU

ERROR

SBAN MULT CPU

ERR

This bit can only be set if bit <23> is already set and
a
CPU
addressing
error
is detected on the command/address

cycle or there is'an address/data or control parity
error
on
the
command/address or write data.
This bit will not
be set for a write data parity error for
the
transaction

that
<16>

<15>

<14>

MBZ

sets bit
is reset

<23>, but for a subsequent transaction.
when the CPU writes bit <23>,

Bit

(SS32)

Must

zero.

DMAC

TRANSACTION

BUFFER SBIA

SS30 DMAC A/D ERROR
This bit will be set
data

being

DETECTED A/D PARITY

for a data parity error when

transferred

from

transaction

buffer

ERROR

the
C

read

the
DMA read.
This bit cannot
be
set
if
bits
<13>
or
<12>
have
been
previously
set.,
This bit is
cleared by the CPU writing it.
The
DMAC
Command/Address
Register
and
DMAC ID Register will be locked if this bit

SBI

during

sets.

The

setting

this

interrupt.

20-149

bit

will

generate

local

VvAX 8600/8650 REGISTER DESCRIPTION
SBIA ERROR SUMMARY
ERROR SUMMARY REGISTER
2008 0008, 2208 0008

g3,

COMMAND

LENGTH/HTAIUS

15
o

14
13
DMAC TRANSACTION BUFFER
SBIA

lsam

11
o

A/DPE |CNTRL PE 1 ERROR

LPU

ERROR

MBOX

DETECTED | BETECTED | DETECTED

18
MULTIPLE

10
08
08
DMAB TRANSACTION BUFFER
l sEiA

I SBIA

MBOX

A/DPE__|CNTALPE |ERROR

DETECTED | DETECTED | DETECTED

06
05
04
DMAA TRANSACTION BUFFER
SBIA

l SBIA

MBOX

A/DPE | CNTRL PE| ERROR

03
INTER-

DETECTED | DETECTED| DETECTED | LOCK

0z
o
00
DMA] TRANSACTION BUFFER
sBiA

A/D PE

|smia

MBOX

| ERROR_

DETECTED DETECTED {DETECTED

<13>

14853

DMAC TRANSACTION BUFFER SBIA DETECTED CONTROL PARITY ERROR
SS30

DMAC CONTROL ERROR

This bit will be set for a control parity error
when
the
read
data
is being transferred from transaction buffer C
to the SBI during a DMA read.
This bit cannot be
set
if

bits
<14>
or <12> have been previously set.
This bit is
cleared by the CPU writing it.
The
DMAC
Command/Address
DMAC ID Register will be locked if this bit
and
Register
sets.
The setting of
this
bit
will
generate
a
local
interrupt.

12>

DMAC TRANSACTION BUFFER MBOX DETECTED ERROR
§530

DMAC MBOX ERR

This bit will be set if the MBox detects a parity error or
from the DMAC
command/address
of
transfer
the
on
NXM
<14>
bits
This bit cannot be set if
transaction buffer.
This bit is cleared by
<13> have been previously set.
or
the CPU writing

DMAC

setting of

<11>

<10>

MBZ
Must

it.

The DMAC Command/Address Register and

will

be locked if this bit sets.

this bit will generate a local

The

interrupt.

zero.

DMAB TRANSACTION BUFFER SBIA DETECTED A/D PARITY ERROR

SS30 DMAB A/D ERROR

This bit will be set for a data parity error when the read
data is being transferred from transaction buffer B to the
SBI during a DMA read.
This bit cannot
be
set
1if
bits
This bit 1is
set.
been previously
have
<08>
or
<09>
cleared by the CPU writing it.
The
DMAB
Command/Address
Register and
DMAB ID Register will be locked if this bit
sets.
The setting of
this
bit
will
generate
a
local
interrupt.

<09>

DMAB TRANSACTION BUFFER SBIA DETECTED CONTROL PARITY ERROR
SS30

DMAB CONTROL ERROR

read
the
This bit is set for a control parity error when
data is being transferred from transaction buffer B to the

SBI during a DMA read.
<10>

<08>

have

This bit cannot

been

previously

set.

set

bits

This bit is

cleared by the CPU writing it.
The
DMAB Command/Address
DMAB ID Register will be locked if this bit
Register and
sets.
The setting of
this
bit
will
generate
a
loca.
interrupt.

20-150

VAX 8600/8650

<08>

DMAB

this

will

bit

will

locked

generate

this

local

bit

sets.

The

interrupt.

MBZ

Must

<06>

SUMMARY

DMAB TRANSACTION BUFFER MBOX DETECTED ERROR
5530 DMAB MBOX ERR
This bit is set if the MBox detects a parity error or NXM
on
the
transfer
of
command/address
from
the
DMAB
transaction buffer.
This bit cannot be set if
bits
<10>
or
<09> have been previously set.
This bit is cleared by
the CPU writing it.
The DMAB Command/Address Register and

setting
<07>

ERROR

zero.

DMAA TRANSACTION

BUFFER

SBIA DETECTED A/D PARITY

ERROR

SS30 DMAA A/D ERROR
This bit is set for a data parity error when the read data
is
being transferred from transaction buffer A to the SBI
during a DMA read.
This bit cannot be set if bits <05> or
<04> have been previously set.
This bit is cleared by the
CPU writing it.
The
DMAA
Command/Address
Register
and
DMAA
ID
Register
will
be locked if this bit sets.
The
setting

<05>

this

bit

will

generate

local

DMAA TRANSACTION BUFFER SBIA DETECTED CONTROL PARITY ERROR
SS30 DMAA CCNTRL ERR
This bit is set for a control parity error when
the
read
data is being transferred from transaction buffer A to the
SBI during a DMA read.
This bit cannot
be
set
if
bits

<06>

<04>

have

been

previously

cleared by the CPU writing it.
The
Register
and
DMAA ID Register will
sets.

The

setting

this

bit

interrupt.
<04>

interrupt.

DMAA TRANSACTION

BUFFER MBOX

will

the

transfer

This

bit

generate

1local

DETECTED ERROR

SS30 DMAA MBOX ERR
This bit is set if the MBox detects
on

set.

DMAA
Command/Address
be locked if this bit

a parity

command/address

transaction buffer.
This bit
<05> have been previously

error

from

cannot be set if
set.
This bit is

the

NXM
DMAA

bits
<06>
cleared by

the CPU writing it.
The DMAA Command/Address Register and
DMAA
ID
Register
will
be locked if this bit sets.
The
setting of this bit will generate a local interrupt.
<03>

DMAI

TRANSACTION

BUFFER

INTERLOCK

TIMEOUT

SS30 DMAI TIMEOUT
This bit is set if an
interlock
write
masked
does
not
occur
within 512 SBI cycles (102.4 microseconds) after an
interlock read masked.
This bit cannot
be
set
if
bits
<02>,

<01>,

this

cleared
and DMAI
<02>

DMAI

bit

<00>

will

have

been

generate

TRANSACTION

BUFFER

set.

The

setting

interrupt.
This bit
is
it.
The DMAI Command/Address
locked if this bit sets.

by
the CPU writing
ID Register will be
SBIA

SS30
This

previously

local

DETECTED A/D PARITY

ERROR

DMAI A/D ERROR
bit is set for a data parity error when the read data
is
being transferred from transaction buffer I to the SBI
during a DMA interlock read,
This bit cannot
be
set
if
bits
<03>,
<01>, or <00> have been previously set.
This
bit
is
cleared
by
the
CPU
writing
it.
The
DMAI

Command/Address

and

this bit sets.
The
local interrupt.

DMAI

setting

20~151

this

bit

will

locked

generate

VAX 8600/8650 REGISTER DESCRIPTION
SBIA ERROR SUMMARY
SBIA SBI ERROR REGISTER
ERROR SUMMARY REGISTER
2008 0008, 2208 0008

k.Y

Fal

COMMAND
a3

;

i3
SBiA

S8iA

BBOX

<01>

SBIA

saiA

DETECTED | DETECTED

A/DPE

ERROR

R/w

a7
o

|DETECTED

CPU

ERROR

STATE

ERROR

PARITY

ROR

CONTROL | ADDRESS

PARITY | PARITY

LOCK

MBOX

CPU

A/D

ERROR

DMAB TRANSACTION BUFFER

DETECTED | DETECTED | DETECTED
A/D PE
CNTRL PE |ERRDR

22
CRU

BUFFER

DMAC TRANSACTION BUFFER
1]

23
CcPU

LENGTH/STATUS

SBIA

DETECTED|

| CNTRL PE | ERROR

A/DPE

s81A

DETECTED|

MBOX

INTER-

DMAA TRANSACTION BUFFER

ETIRLE
g

DETECTED | MACHINE

| ERAOR

ERROR

RIW

DMAS TRANSACTION BUFFER
$BiA

DETECTED | LOCK

| CNTRL PE | ERROR

|smiA

MEOX

A/D PE

RROR

DMAI TRANSACTION BUFFER SBIA DETECTED CONTROL PARITY ERROR
SS30

DMAI

CNTRL ERROR

This bit is set for a control parity error when
the
read
data is being transferred from transaction buffer I to the
set
be
This bit cannot
SBI during a DMA interlock read.

bit

bits
is

<03:02>

<cleared

This

or <00> have been previously set.

DMAI

The

it.

writing

CPU

the

ID Register will be
Command/Address Register and DMAI
will
bit
this
of
The setting
locked if this bit sets.

generate a local
<00>

interrupt.

DMAI TRANSACTION BUFFER MBOX DETECTED ERROR
SS30 DMAI MBOX ERR

NXM
This bit is set if the MBox detects a parity error or
on
the
transfer
of
command/address
from
the
DMAI
transaction buffer.
This bit cannot be set if bits
<03>,
<02>,
or
<01>
have
been previously
set.
This bit is

cleared by the CPU writing it.

and

The

DMAI

Command/Address

DMAI ID Register will be locked if this bit

The setting of

this

bit

will

generate

local

interrupt.

SBi ERADR REGISTER

2008

-11

TIMEOUT

TIMEOUT STATUS

<01>

{

18,

EAROR

)

—

MR- TARER

The
SBI
error
register
stores
information
about
CPU
SBI due to timeout or
the
on
failed
trnsactions which
error confirmation.
<31:16>

ZERO

(SS36)

These bits are read as zeros provided

the

zero

fill

logic.

<15:13>

ZERO

(SS32)

These read only bits are forced to zero by hardware ground
potential.

20~-152

VAX 8600/8650 REGISTER DESCRIPTION
SBIA SBI ERROR REGISTER
<12>

TIMEOUT

BUS

REG

D<12>

(SS32)

This

bit will be set when there is
reterence for one of the following

an SBI timeout
reasons:

SBIA does

Unsuccessful
an

access:

acknowledge

When

the

confirmation

for

CPU

not

SBIA

b.
c.
d.

the

SBI

wunable

arbitration
Target NEXUS
The
address
address
Combinations

SBIA does

cycles

win

'
is always
1is
for
the

not

the

receive

command/address

or
write
data
within
512
SBI
cycles
microseconds)
from
the
time the SBIA first
the SBI.
Unsuccessful access can
be
caused
following:
a.

on a CPU

SBI

(102.4
requests
by
the

through

bus

busy when accessed
a
non-existent
device

first

receive

two

the

acknowledge

read data within

for

a read data timeout.

the

512

command/address,

When this bit sets, Error Summary Register
<23>
will
be
set,
locking Error Summary Register <31:26> (type
of reference), SBI Error Register <11:10, 08>, and the
Timeout
Address
Register (referenced address).
This
bit is reset when the CPU writes it to
a
one.
This
will also reset <11:10, 08>.

<11:10>

CP TIMEOUT STATUS
BUS REG D <11:10>

The

timeout

<01:00>

(SS32)

status

bits

are made

follows:

Bit <01>:

Bit

these

SBI

confirmation equals

two

signals

indicate

timeout.

00:

01l:

10:

11:

Cannot

These bits

<09>

ZERO

These

reset

are
when

01,

the

SBI NEXUS did not respond
Device was busy (Busy)
wWaiting for read data

and

two

signals

State machine is in the read pending state.

<00>:

Together

busy.

type

SBI

(No Response)

happen

locked by Error Summary Register

<23>,

the

<12>.

(SSs32)
read only bits

CPU

are

writes

forced

SBI

Error

zero by

hardware

ground

potential.
<08>

CPU

SBI

ERROR CONFIRMATION

BUS

REG

<08>

(s8S832)

This bit is set when the
SBI
state
machine
enters
the
error
abort
state if the SBI NEXUS has returned an error
confirmation on a CPU
read/write
command/address
cycle.
If
this
bit
1is set, Error Summary Register <23> will be
set, locking the Timeout Address Register,
Error
Summary
Register <31:26>, and bits <12:10> of this register.
This
bit is reset when the CPU writes bit <12>.
<07:00>

ZERO (8s532)
These read only bits
potential.

are

forced

20-153

zero by

hardware ground

VAX 8600/8650 REGISTER DESCRIPTION
SB1A SBl

2008 003C, 2208 003¢C

FAULT STATUS REGISTER

SBI FAULT/STATUS REGISTER

;
%
|

UNEXF

MULTIPLE | sai

TRANG: | XWITTER
LOCK
SEQUENCE] MITTER | DURING
FAULT
FAULT
FAULT

|READ
WRITE
s8I
PARITY. | SEGUENCE|DATA
FAULT
FAULT | FAULT

581

PO
ri
PARITY | PARITY
ERROR
ERROR

§BI5TS
16

R/W

_/W

)

information on SBI
The SBI fault/status register saves
in which the SBIA may or may not
faults on transactions
All SBI devices monitor the SBI every
have been involved.

|
|

and check for errors.

cycle

If an error is detected, the

and a fault/status
Fault wire is asserted

the

SBI

PARITY FAULT

for

configuration

(part

non-CPU devices) is

locked.

<31>

SS11 FAULT REG B <31>

This bit will set if the SBIA detects an SBI parity

error

parity

error.

received

SBI information.

Bits <23:22> will indicate

whether it was an address/data or

|
|

<30>

control

The register is written every SBI cycle, and locked when
SBI FAULT is asserted. This bit will be cleared when SBI

FAULT

is set.

This bit is only valid if bit <19

deasserted.

WRITE SEQUENCE FAULT

SS11 FAULT REG B <30>

This bit is set if the SBIA is expecting write data, and
information, with no parity error, but the
receives SBI
tag does not indicate write data (101). This bit is- also
locked when SBI FAULT is asserted, and clears when SBI
FAULT clears. This bit is only valid if bit <19> is set.
<29>

UNEXPECTED READ DATA
§S11 FAULT REG B <29>

This bit sets if the SBIA receives information with the
(10000) with a read data tag (000), but the SBIA
SBIA ID
is not expecting read data (no read pending). This bit is
is asserted, and clears when SBI
locked when SBI FAULT
FAULT clears.

|
|

<28>

INTERLOCK SEQUENCE FAULT
SS11 FAULT REG B <28>

This

This bit is only valid if bit <19> is set.

bit

1is

set

the

SBIA

receives

valid

interlock write masked but the
for an
command/address
interlock flip-flop is not set (an interlock read has not

This bit is also locked when SBI FAULT is
occurred) .
asserted, and clears when SBI FAULT clears. This bit is
only valid

<27>

if bit <19>

is set.

MULTIPLE TRANSMITTER FAULT
S§S11 FAULT REG B <K27>

that 1is not
the same as the ID it transmitted on the SBI. This bit is
also locked when SBI FAULT is asserted, and clears when
SBI FAULT clears. This bit is only valid if bit <19> is

This bit will set if the SBIA detects an ID

set.

20-154

VAX8600/8650 REGISTER DESCRIPTION
SBIA

<26>

FAULT

STATUS

SBI TRANSMITTER DURING FAULT
SS11 FAULT REG B <26>
This bit sets when the SBIA was the nexus transmitting
on
the
SBT.
This bit is locked when SBI FAULT is asserted,
and

if
<25:24>

SBI

clears

bit

MBZ

when

SBI

set.

<19>

FAULT

clears.

This

bit

only

wvalid

(SS33)

Must

zero,

<23>

SBI P1 PARITY ERROR
SS11 FAULT REG B <23>
This bit indicates that an SBI parity error was over SBI B
<31:00>.
It
is
only
wvalid
if bit <19> is set.
It is
locked when SBI FAULT is asserted, and will clear when SBI
FAULT clears.

<22>

SBI

PARITY

ERROR

SS11 FAULT REG B 22>
This bit indicates that an SBI parity error was
over
SBI
TAG
<02:00>,
SBI
ID
<04:00>,
and SBI MASK <03:00>.
It
too, is only valid if bit <19> is set, and is locked
when
SBI FAULT is set.
It will clear when SBI FAULT clears.
<21:20>

MBZ

(SS33)

Must
<19>

FAULT

BUS

zero.

LATCH

REG

<19>

(s8s33)

If an SBI nexus, including the SBIA, detects an SBI fault,
the nexus will assert SBI FAULT.
The SBIA, upon reception
of SBI FAULT will set the fault latch, which will keep SBI
FAULT

asserted.

clears

the

fault

FAULT
will
conditions:
1.
2.
3.
4.
5.

latch

will

remain

by writing

asserted

for

the

FAULT

§S21

until

to bit

following

the

<19>.
SBI

SRT
error

INTERRUPT

<31:26>

SBI

ENABLE

INTR ENA
CPU will set this

an
be

FAULT WIRE

SS33 BUS

This bit
<l6>

and

FAULT

The
bit by writing bit <17> to enable
SBI fault to generate an interrupt.
The interrupt will
asserted if the fault latch, bit <19>, is set.
<17>

CPU

1Interlock sequence fault
Unexpected read fault
Write sequence fault
Multiple transmitter fault
Parity fault

When this bit
sets,
Fault/Status
<23:22> will be locked.
<18>

asserted

a one

FAULT

REG
D <17>

indicates the state of

SILO

the SBI FAULT signal.

LOCK

SS33 BUS REG D 16>
This bit will be set when the silo locks
due
to
an
SBI
fault.
It
will
be
reset when the CPU resets the fault
latch,
<15:00>

MBZ
Must

bit

<19>.

(SS36)
be

zero.

20-155

VAX 8600/8650 REGISTER DESCRIPTION
SBIA SBI

MAINT REG

SB! MASNTENANCE REG!STER
008 0044, 2

FORCE

O 381

FARULT

FAULT

REVERSAL SEAUENCE ggfiépcm Mummg

FORCE

MAINTENANCE 1D <04:00>

?EVERSAL
N 58!

R/W

R L

11
FOR€€

<01

“<gd= e i

S04s

fonce

gi?is

TIMEQUT

II A

FORCE

EQRCE

?&;mce
gggcg ?fi:& fSORaCE
ifi‘saw
DATA
REQUEST | SEQUENCE] TR-

and maintenance
a diagnostic
This register is used as
Operational software does not use this register.
tool.
<31>

FORCE PO REVERSAL
S524

FRC

REV ON

SBI

When set, this bit will cause the SBIA to transmit bad PO
parity on the SBI for all SBIA to SBI transactions. This
includes CPU read/write and DMA read data.

<30>

FORCE WRITE SEQUENCE
S824 FORCE WSQ FAULT

When
When
will
This

FAULT

1.
1logic
set, this bit will force SBI TAG <01> to a
used with a CPU write to an SBI nexus register, it
force the write data tag to 111, the diagnostic tag.
will cause a write sequence fault because SBI devices

are looking for a tag of 101, write data.
FORCE UNEXPECTED READ FAULT
SS24

FORCE

read

data.

UNEXP

READ

bits <27:23>,
When this bit is set, the maintenance 1ID,
with a TAG of zero, will be repeatedly transmitted on the
SBI (the data is undefined). When the nexus, as selected
by the maintenance 1D, receives read data (TAG = 0), it
should assert BUS SBIT FAULT because of the unexpected
<28>

FORCE MULTIPLE TRANSMITTER FAULT
§524

FORCE

MULTI

Setting this bit forces a multiple

transmitter

fault

The CPU will load the maintenance ID
any selected nexus.
nexus
that
with the ID of the selected nexus, then read
after the
cycle
the
On
register.
configuration
command/address is transmitted on the SBI, the SBIA will
enable the SBI to continually transmit a TAG = 111 with
the maintenance ID (data is undefined).

When the nexus transmits the read data, the ID transmitted
It will be ORed with the
by the nexus is the SBIA's ID.
maintenance ID, and as long as the bits are not masked,
will cause the nexus to detect a multiple transmitter
fault.

<27:23>

MAINTENANCE ID <04:00>
SS24 MAINT ID <04:00>

These bits are used to generate the maintenance ID in
following

1.
2.
3.

4.,

instances:

Generation of unexpected read fault
Generation of multiple transmitter fault
Used by the silo as the compare ID

Used to check ID logic
20-156

the

<29>

VAX

8600/8650

<22:12>

MBZ

(SS33,

Must
<11>

SS36,

MAINT

REG

SS832)

zero.

FORCE
P1 REVERSAL ON
SS24
When

SBI

FRC Pl REV ON
set, this bit

SBI

will cause the SBIA to transmit bad
Pl
parity
on the SBI for all SBIA to SBI transactions.
This
includes CPU read/write and DMA read data.

<10:09>

<08>

MBZ (Ss832)
Must be zero.
FORCE

READ

SS524

FORCE

DATA

TIMEOUT

This bit will preset the state machine
all ones when the state machine enters
state.

The

timer

generating

will

timeocut

expire

condition

the

while

MBZ (SS32)
Must be zero.

<04>

FORCE SBI INTERRUPT REQUEST
SS24 MAINT REQ ENA

When
set,
this
Register
<07:04>
ALERT

<03>

the

will
enable
<03) to force

count,

CPU

read

SBI
Silo
Comparator
interrupt requests and

SBI.

FORCE TR SEQ
bit will enable

assert

<15:00>

is transmitted.
back
read
to
logic.
FORCE

SBI
on

:
<15:00>

Silo Comparator Register
the

SBI

when

CPU

Command/Address

It is used in
conjunction
with
a
loop
test
the
SBIA
and SBI nexus arbitration

MAINTENANCE

SS24 FORCE MAINT TR
This bit will unconditionally assert the TR
to SBI Silo Comparator Register <15:00>.
<01>

for

FORCE TR SEQUENCE

SS24
This

<02>

bit
and

first

waiting

data.
<07:05>

timeout counter
to
the read wait start

FORCE INTERRUPT SUMMARY
5524 FORCE ISR DATA

READ

corresponding

DATA

This bit is used to enable
the
SBIA
to
respond
to
an
interrupt
summary
read
to
check out the circuitry that
prioritizes the ISR data and generates the vectors.
During

the

SBIA
transmitted

response

cycle of an
interrupt
summary
will
enable
the
write
data
latch
on the SBI along with a TAG, MASK, and

read,
to
ID

be
of

Zero.

<00>

USE

SS24
This

MAINTENANCE

1ID

USE MAINT ID
bit will enable

<27:23>

for

the use of

diagnostic

purposes.

20-157

the maintenance

1ID,

bits

VAX 8600/8650 REGISTER DESCRIPTION
SBIA SBI

QUADCLR REGISTER

S8! QUADCLEAR REGISTER
2008 004C, 2208 004C

VUAUWUHRU AUIGNED PHYSILAL ADDRESS

S8 FUNCTION CODE

ADR <26> ADR <26> iADR 424>J ADR <23> SAQR <22}2 ADR <212> y ADR <20> ADR <§9}§AGR <i1g> ‘ADH <1 7>iéf38 <18>

QUADWORD ALIGNED PHYSICAL ADDRESS

ADR <T5> ;ADR <14> iADfi <13> lfi{.‘)R <12> ADR <11> ADR <10> ADR <08> JADR <Q8>! ADR <07> iAfiR <(}6>! ADR <05> !N}R <04 ‘ADE <03>, ADR <02>, ADR <€)i>’ADfi <00
samaggyq

The purpose of the quadclear register is to clear ECC errors in SBI

memory .

The

quadclear

does

not

exist

as a physical

When the CPU writes the SBI Quadclear Register, the

CPU

The
operation.
command/address.

SBI
the
generate
to
is used
write data
Two longwords of all zero data is supplied by the

SBIA.

<31:28>

SBI FUNCTION CODE

27>

MBZ

the SBI
become
Bits <31:28> must be 1011, as they will
If this register is
function code, extended write masked.,
will be
data
read
the
and
read, the quadclear is not done,
all zeros supplied by the zero fill logic.

Must be zero.
address must

the
zero because
This bit is written as
be a memory address, not an I/0 address.

This bit is also read as a zero provided by the zero
‘

logic.

<26:00>

fill

QUADWORD ALIGNED PHYSICAL ADDRESS - ADR <26:00>
the
in
address
the quadword
become
These bits will
This bit is alsc read as a zero provided
command/address.
by the zero fill

lsglc.

20-158

VAX

8600/8650

SBI

SILO

S8I SiLO REGISTER
2008 0030, 2208 0030

)

RECEIVED

AFTER

S8t

FAULT

| iNTER-

LOCK

ID<04> | ID<03>

TRC15>

TRL<14>

{

1D<01> f

20
T

OR 581

ID<00> | TAG02> | TAG<01> | TAG<00> |Be31>

08
i

RECEWED TR <15:00>

18
T

RECEIVED S8i MASK OR FUNCTION
B<30>

05
i

OR SBI

B<25>

04
1

SBI

8<28>

CONE <01.00>

|CONF

RECEn}ED a8

MASK<0I>, MASK<D2>, MASK<O1
>, MASK<OO>

OR SBI

]

TR<11> § TR<I0>

RECEIVED SBI TAG <02:00>

]

TR<13> [ TR<12>

L 1D<02> i

RECEIVED 581 1D <04:00>

|conF<oo

[

TR<09> I TR<O8> i TR<D7> | TR<O6> 1 TR<GE> i TR<04> 1 TR<03> l TR<02> I TR<01> I TR<OO>
RO

M T8TET

The

SBI

storage

The

silo

is a read
various SBI

assertion

FAULT

SILO

data

available

locked
silo

<31>

the

FAULT by

through

wusing

Description,
of

SBI

LOCK

only

SBI

nexus

SBI

FAULT/STATUS

the

SILO

SBI

COMPARE

locks
The

interpretation
AFTER

silo

See

the

1is

1loaded

DB86

silo,

sets

and

makes

may

also

the

be
SBIA Technical

the SILO.

An example

description.

FAULT

REG

SBI

follows

the

EK-DB86X~TD for a description of

BUS

D<31>

silo

(85820)

bit

<31>

indication

that

AFTER

FAULT

the

only

written
into
clears.
It may be
fault conditions.
<30>

any

the

provides
temporary
SBI cycles.

SBI

fault

asserted

for

with

AFTER
FAULT,
an
condition
has cleared.

one

SBI

cycle,

and

will

the first silo location after the fault
used to recognize frequently
occurring

RECEIVED SBI INTERLOCK
REG D<30> (8S20)
Silo bit <30> is loaded

BUS

with REC SBI

INTLK

,
from

the

SBI

Silo bits <29:25> are loaded with REC SBI ID
<04:00>,
indication
of
which nexus is in control of the SBI.

an
See

transceivers.
<29:25>

RECEIVED SBI
BUS

REG

the table
ID

CODE

——

16—
3
4

<04:00>

D<29:25>

that

follows.

DEVICE

SBIA
SBIA

(Ss20)

DW780
DW780
DW780

(DMA)

1**

(CPU)

2%
* %

3
4
5

DW780

7
8

6
7

RH780

RH780
RH780

10
11
12

CI780
DR780

13
14

12
13
14

VAX 8600/8650 REGISTER DESCRIPTION
SBIA

SBI

SILO

$8f $i1LO REGISTER
2008 0030, 2208 0030

RECEIVED
AFTER is“;sTa;jE

15
TRLIE>

14
TR<CI14>

0<04> { 1D<03> iD<02> 1 0> l 10<00> TAG‘(G?}iTAG(Qi} TAGLO0> (B<31> 18<3{3

B<29>

B<28>

13
TR<C13>

|
!
S8 1D <04.00>
RECEIVED

TR<12>

TR<11> i TRCIO>

RECEIVED TR <15:00>

TR<O9> l TR<08>j TRO7>

TROE> i THIOE>

TR<04>

Notes:

-A TR 0
-A TR 1

i
CE VED SBI MASX
o8 Fii?iéigag“cwi
THOM
ggfii“!jg g
MAs%> 1Mask<on
|MASK<03>
RECEIVED| S8 TAG <02.00>

TR<O3>

TR<O2>

ONF<O1> CONF<OD>

TREO1> | TESOO>

is used to hold the SBI for the next SBI cycle.
the
is used by the SBIA for DMA reads to transfer

The ID will be the ID
return word to the SBI.
data
read
of the device that originated the DMA read transaction.
-A TR 2 is used by the SBIA for
CPU
read/writes
of
SBI
nexus

<24:22>

<21:18>

registers.

RECEIVED SBI TAG <02:00>
BUS REG D<24:22> (SS20)
Silo bits <24:22> are loaded with REC SBI TAG <02 00>,
indication of the type of SBI cycle as follows:
1.

000:

Read Data

011:

Command/Address

101:

Write Data

110:

Interrupt Summary Read

111:

Diagnostic Tag

RECEIVED SBI MASK OR FUNCTION

BUS REG D <21:18>

(SS20)

The contents of silo bits <21:18> depend upon the SBI tag.

I1f the tag is 011, command/address, the silo is loaded
the
Otherwise,
with the SBI function from bits <31:28>.
silo is loaded with the mask bits.

decoded

as:

0001:

Read Masked

0010:

Write Masked

0100:

1Interlock Read Masked

0111:

1Interlock Write Masked

1000:

Extended Read

1011:

Extended Write Masked

20-160

The function codes are

VAX 8600/8656

The mask

bit meanings

for

are:

Mask <03> = 1:

Read or write to_byte 3

Mask <02> = l:

Read or write to byte 2

Mask

Read or write

Mask <00>
= 1:

<01>

bit meanings

for

valid

0001:

Corrected

0010:

Uncorrectable

RECEIVED SBI
REG

read

<17:16>

which

read

have

<01:00>

(SS20)

are

the

loaded

with

following

No response
Acknowledge

10:

Busy

1l:

Error on command/address

Silo

SBI

bits

requests

Example of

TRANSFER

SBI

confirmation

<15:00>

(8S19)

<15:00>

that

REQUEST

the

meanings:

01:

D<15:00>

are:

error

00:

REG

1 «

read data

BUS

to byte

data

RECEIVED

data

CONFIRMATION

D<17:16>

Silo bits
bits

write

Read or write to byte‘

0000:

BUS

<15:00>

command/address

The mask

<17:16>

may

are

loaded

with

any

SBI

transfer

asserted.

interpreting a deposit byte to DW780

#0 at TR3.

D/B 2X006000 AA
The

SILO may be
REPEAT

read

EXAMINE

follows:
2X080030

‘The following information would appear in the silo if it
was locked after 16 SBI cycles (or less) by SBI FAULT or
by using the SILO COMPARE register.
Note that the first
silo location read would be the first location loaded.

Only silo 4
SILO

locations

CONTENTS

20C80001

are

shown.

BREAKDOWN

ID =

16,

FUNCTION
TR

21440000

ID =

00010000

CONF

CPU;

MASK

= 3,
WRITE

TAG
0001,

01,

ACK

"CONF = 01,

ACK

20-161

TAG

0010,

C/A;
MASKED;

HOLD

16,

DATA,

CPU;

WRITE

BYTE

VAX 8600/8650 REGISTER DESCRIPTION
SBIA SBI

SILO COMPARE

SBi 51LO COMPARE REGISTER
2008 0040, 2208 0040

30
3
“compan- | sno
LOCK

LOCK

ENABLE

TIONAL

SiLo

INTERUPT | UNCONDI-

)

LULR COUE

CMD/MASK CMD/MASK CMD/MASK CMD/MASK

)

20
21
COMPARATOR TAG

[TAG 02> f TAG <Q1>’ TAG <O0>

<0O0>

02> \ <01 >J

<03>

<00

<01

23
24
25
26
COMPARATOR COMMAND/MASK

27
28
CONDITIONAL

ATOR

i7
18
COUNT FIELD

<03>

<02> A <0t>

<00>

<01>

<G0>

1. fi’
15
<16> f

14> N <13> 4 13> .

)

MAINTENANCE TR <15:00>

A =08>

<10>

=3i>

<08>

! <07>

MAINTENANCE $BI REG <07:04>

§ <08> A <08

f <4

l MAINT

ALERT

<0?t>

WO/READ AS ZERDS

<31>

COMPARATOR SILO LOCK
§S21 CMP SILO LOCK

The Comparator Silo Lock bit is set if the count in the
silo counter has reached F. When this bit sets, the CPU
This bit is
1is set.
will be interrupted if bit <30>
cleared when the CPU loads the silo count field with a
count

<30>

other

than F.

SILO LOCK INTERRUPT ENABLE
SS25 SILO LOCK

INTR EN

The CPU sets this bit to
CMP

<31>,

<29>

SILO LOCK,

enable

when

interrupt

Dbit

sets.

LOCK UNCONDITIONAL
S825

LOCK UNCOND

When this bit is set, the silo counter will count on each
It will cause a silo lock within 16 SBI.
SBI cycle.

cycles, depending upon the count that had been
loaded into the silo c¢count field.

<28:27>

previously

CONDITIONAL LOCK CODE <01:00>
S$S25 COND LOCK CODE <01:00>

These two bits determine the comparisons that will enable
If the
counting the silo counter to achieve a silo lock.
SBI data matches the silo comparator bits, for the enabled
comparison, the counter is incremented. The conditions

<26:23>

follows:

are

00:

No compare (no comparison is made)

2.,

01:

SBI

10:

SBI

ID and SBI TAG

11:

SBI ID and SBI TAG and SBI COMMAND/MASK

COMPARATOR COMMAND/MASK
$S25 COMP CMD/MSK <03:00>

These bits provide the base for the silo comparison, when
If the SBI tag
it is enabled to compare the command/mask.

is 011, command/address, then this field is compared with
If the SBI tag is other
SBI B <31:28>, the SBI function.
than 011, this field is compared to the SBI mask bits.

20-162

VAX

8600/8650

<22:20>

DESCRIPTION
SILO

COMPARE

COMPARATOR TAG
SS25 COMP TAG <02:00>

These bits provide the base for the
it
1is enabled to compare the tag.
with SBI TAG <02:00>.
<19:16>

SBI

COUNT

SS19
The

silo comparison,
when
This field is compared

FIELD

COUNT
CPU

FIELD

loads

the silo counter with the
two's
complement
of
the
number
of
SBI cycles to be loaded into the silo
after a comparison is made.
When the count reaches F, the
silo
is
1locked.
The counter is also enabled by the Lock
Unconditional bit <29>.

<15:00>

MAINTENANCE

SS25

MAINT

These

bits

requests,

TRANSFER REQUEST <15:00>
TR <15:00>
provide the
means
to
simulate
SBI

interrupt

requests,

and

SBI
SBI

transfer
alert

for

cause

the

diagnosing
the
interrupt
logic
and
SBI
priority
arbitration
logic.
They also provide a means of testing
the lower 16 bits of the silo.
They are controlled by SBI
Maintenance Register bits <04:02> as
follows:
1.

The

asserted MAINT

corresponding

SBI

Maintenance

SBI

TR
REQ

If MAINT TR <03> and SBI
both set, SBI ALERT will
If

SBI

MAINT

<07:04>
<04>,

Maintenance

<15:00>

MAINT

REQ

asserted

ENA,

<03>

cause

<03>,

the

CPU
SBI

set,

the

<04>

SBI

command/address

FORCE MAINT TR,

20-163

set.

MAINT TR <15:00> will cause the corresponding
SBI
<15:00> to be asserted if SBI Maintenance Register

<02>,

are

asserted

corresponding

Maintenance

set.

asserted.

to be asserted when a
transmitted
on the SBI.
See

bit

will

bit

Maintenance
be

<15:00>

bit

<07:04>

TR
bit

VAX 8600/8650 REGISTER DESCRIPTION

SBIA SBI TIMEOUT ADDRESS

SBIA SBI UNJAM
S

as]

SBI LONGWORD PHYSICAL ADDRESS

:
, <18> . <17> , <187
<27F . <26> , <28> , <2L <23> . <22 | <21> : <LZ0> ) <i18>

<15>

<14

<13 | <iz> . <i1>

<10 . <08> , q}gj‘_, <Q7> ' <08> 1 <05>

<04>

<03>

<02> , <0i> , <00

SBI LONGWORD PHYSICAL ADDRESS

address for all
The SBI timeout address register holds antheerror
occurs on a
CPU transactions in the SBIA. When
CPU transaction, the timeout address register is locked.
MBZ (SS36)

<31:28>

These bits are forced to zero by the zero fill logic.

ADDRESS - BUS REG D <27:00> (S55827) l ‘
<27:00> SBI LONGWORD PHYSICALRegiste
r is loaded with the physica
The Timeout Address
time a command/address
address, for the CPU command, each data
latch to the
is transferred from the file
locked if Error Summary
It will be

command/address latch.

%%%

SBI UNJAM REGISTER

2008 0048, 22

15
o

[¢]

4
o

<31:00>

]

[

o ‘ a

F-4

08
o

08
Q

04
¢}

03
o

a2
o]

01
o

oo
Fi]

¢]

]

WO—

13
o

12
0

11
o

10
o

08
o

a8
o

o7
o

SBAQ
as a hardware
The SBI Unjam Register does not theexist
address of the Unjam
When the SBIA decodes
register.
seguence will Dbe
register, for a CPU write, the Unjam
s will
If this register is read, the content
initiated.
show all zeros, provided by the zero fill logic on SS36.

For a read, the Unjam sequence will not be done.

20-164

VAX 8600/8650

SBI

VECTOR

S8i VECTOR REGISTER

TO 2008 009C

2008

2208 009G TO 2208 00SC

o i ‘0

0 ! 0 I o

)

@ I| o

{ o I 0

} 0 l 1

] o { 0 ] 0

LEVEL

REGUEST

TR LEVEL

{ 0 ’ o

o
i

14585

THE REGISTER FORMAT SHOWN IS FOR PR
LEVELS 14,15, 16, AND 17 VECTORS FOR IPR
LEVELS 15,18, 1C, AND 1 E ARE READ FROM
A

PROM. THESE VECTORS AND THE ADDRESSES
ARE AS FOLLOWS.
INTERRUPT

PRIDRITY

ADDRESS

INTERRUPT

2008 O0A4, 2208 00A4
2008 DOAC, 2208 ODAC

COMPARE INTERRUPT 50
SB1 ALERT
58

2008 OOBO, 2208 0OBO SB8I FAULT

2008 OOBO, 2208 00BO

SEIA ERROR

5¢C

(IPR 19)
(PR 18}
{IPR 1C)

2008 0088, 2208 DOBB

581 FAIL

The

CPU

will

VECTOR

LEVEL

{1PR 1C)

read

{1PR 1E)

the

appropriate

vector

response

the
arbitrated
interrupt
priority requests,
which it will use,
along with the I/0 adapter number to build the vector register.
1If
the
interrupt
being serviced originated on the SBI, the vector is
made up
If
the

of the interrupt priority request level and the
interrupt being serviced originated on the SBIA,

from

read

TR
the

level.
veclLor

PROM.

<31:12>

MBZ (Ss36)
Must be zero.

<11:09>

MBZ

(SS36

Must

SS31)

zero.

1If

the

interrupt

being

serviced

originated

on the SBI, these zeros are forced by ground potentials in
the hardware on SS31.
If the interrupt is
a
local
SBIA
interrupt,
these
zeros
are
provided by
the zero fill

logic.

<08>

LOGIC ONE

(SS31)

SS31 BUS REG

This

bit

always
<07:06>

read

<08>

tied

to +3

volts

logic

zero

for an SBI interrupt
from the PROM.

REQUEST LEVEL
SS831 BUS REG <07:06>
These

fieclds

arc

supplied

the

two

address
bits,
which correspond to the
an SBI interrupt.
They are provided by
local SBIA interrupt.
<05:02>

and

TR LEVEL

least

significant

request level, for
the
PROM
for
a

(SS531)

BUS REG <05:02>
The TR
1level
1is
interrupt
1s
an
local
<01:00>

SBIA

g
represented
by
bits
<05:02>
if
the
SBI
interrupt.
If the interrupt is a
interrupt, these bits are provided by the PROM.

ZERO

SS31
This
for

SBI

BUS REG <01:00>
field is read as zeros.
1local
SBIA
interrupts,
interrupt.

20-165

inverting

supplied by
+3

the

volts

PROM
for

VAX

8600/8650

SBR

SCBB

s8a

SYSTEM BASE REGISTER

PR OC
31392‘323272525232322212019

3817?515313!211fl}flSO&éTG&

MBZ

%GQN@E!Gfi

PHYSICAL LONGWORD ADDRESS
]

]

MBZ

]

MR-13984

<31:30>

MBZ
Must

<29:02>

zero.

PHYSICAL

LONGWORD ADDRESS
address points to the first PTE in the SPT.
1In
turn,
this
PTE
maps
the
first page of System Space, that is,
virtual byte address 80000000 (hex).

The

<01:00>

MBZ

Must

zero.

SCE8

SYSTEM CONTROL BLOCK BASE REGISTER

333&2@28?2525242322212&%

3181?1’5153;131211:aesas

MBZ
¥

<31:30>

MBZ
|

]

zero.

PHYSICAL PAGE ADDRESS OF SYSTEM CONTROL BLOCK
The SCBB is a privileged register containing the
address
of
the
System
Control
Block,
which
page—aligned.

<08:00>

MB2
Must

<29:09>

masesmaaazmm

PHYSICAL PAGE ADDRESS OF SCB

MBZ

Must

zero.

20-166

physical
must

VAX 8600/8650 REGISTER DESCRIPTION
SDCS
§ics

174403
o7

508 CONTROL/STATUS SES?S{}T&%
06

sror | swer | o

Evae cnaBE | siNGLe
i

CHANNEL

FLAG

MR 14833

<07>

<06>

STOP CLOCK
When set, it
clocks
have
complete,

SHIFT VALUE START
The T-11 program asserts

SDB

<05>

clock

<03>

the

console

Shift

needed

Start

to generate

SDB

the

console

test

station.

from the VAX CPU.

READY
interrupts from the VAX CPU.

SINGLE EVENT FLAG
this bit is negated,
it

asserted,

one

eight

SDB

READ
The direction of the data

SDB

clocks

are

generated.

clock

generated.

transfer

specified by

CHANNEL WRITE,
either

the

CHANNEL WRITE

CHANNEL

8DCS

CONTROL

BIT

SETTINGS

READ OR

WRITE

A VISIBILITY

SINGLE

CHANNEL

EVENT

WRITE

READ

OPERATION

Shift

eight

bits

to visibility
VIS
SDB

SHIFT =
clocks.

Shift

SHIFT =
clocks.
1

Shift

1).

from

CHANNEL

SDB

eight bits

setting

READ bits.

Specify the
operations
used
to
transfer
data
selected visibility channel.
See Table below.

the

operation.

ENABLE TRAMSMIT

When

<02:00>

value

to perform an

When

<01:00>

program
that
all
SDB
that
the operation is

the input to DAL <5> via the SDB to
It is used to inform the software

module

ENABLE STORE READY
Enable STX interrupts

Enable TX
<02>

clocks

-TEST READY
This is an unused pin,
the
DAL
multiplexer.
that

<04>

indicates to the T-11
been
generated
and

out

(if SDMS

Generates

eight

from visibility

into SDB (if SDMS VIS
1).
Generates eight SDB
:

one

bit

in SDB

out

visibility register (if VIS SHIFT
= 1).
Generates one SDB clock.
1

Shift

one

bit

from

visibility

1).

Load

from

visibility

diagnostic

SHIFT =

20-167

0).

terminators

Generates

(if VIS

one

SDB clock.

VAX 8600/8650 REGISTER DESCRIPTION
SDDB

15?338131

$08 DATA BUFFER BEGISTER
CL18, 20

)

SERIAL DIAGNOSTIC BUS (SDB) DATA BUFFER
£

R 14831

It is parallel loaded by the
The SDDB is an 8-bit shift register.
T-11 program with the data to be shifted ocut to a visibility or
control

channel.

and enable
terminator select
1is either diagnostic
This data
information 1loaded prior to shifting data back to the console, or
control data when the channel

is used for control purposes.

The serial data shifted back to the console is loaded in the SDDB
The direction of the
it may be read by the T-11 Program.
where
shift paths

is as

follows:

DATA FROM
VISIBILITY
CHANNELS

S00B

—
i

DATA T0
VISIBILITY/CONTROL
CHANNELS

MA-15378

For additional information, refer to the SDB section of this
the VAX 8600/8650 Console Technical
and
Guide
Maintenance
Description,

EK-KA86C-TD.

20-168

VAX 8600/8650

18?4'432

SOB MODULE/CHANNEL SELECT “g{?g%

WAUNE U

VISt

MODY F/CHANNFL BERLFCT

CONTROL CHANNEL

BILITY

SHIFT

The SDMS register is used by the console program to
control/set-up
the SDB prior to initiating the SDB seguence via the SDCS register,
For

additional

information

pertaining

SDB

operation

and

the

register,
refer to the SDB section of the Maintenance Guide and
the KA86 Technical Description Manual (EK-KA86C-TD).
<07:03>

MODULE/CHANNEL SELECT
The module/channel select

field determines
which
to perform the SDB operation on and is encoded as
the following table.

NOTES:

<02>

Module

Control

Module

Channel

(NOTE

Select

Module

00
01
02
03
04
05
06

FBA
FBM
MCD
IBD
IDP
ICA
ICB

07
10

channel
shown in

Control
Channel

Module

{NOTE

CSB
CSA
IocA
IOA
IOA
IoA
MTM

Yes
No
Note
Note
Note
Note
No

Yes
Yes
No
Yes
No
Yes
No

16
17
20
21
22
23
24

CLK
EDP

Yes
Yes

25
26

Spare
Spare

EBE

Yes

Spare

MCC

Yes

SDD

MAP

Loopback

Test

EBD

SCP

Yes

EBC

Yes

has

and

(3)

manufacturing only (via special test ABus
IOA2 and IOA3 are currently nonexistant

and

visibility
control

2
2

3
3

——
N/A

IOAQ0

visibility

Module

IOAl

control

2
3

(2)

VISIBILITY

both

O
1

(1)

and

channels.

available

backplane)

SHIFT

This
signal
1is
distributed
(daisy
chained)
to
each
visibility
channel
and
used
to control the loading and
shifting
of
shift
register
logic
in
the
selected
visibility channel.
When asserted, the visibility channel
shift register will shift data one bit position
for
each
SDB
<¢lock.
When
<c¢leared,
the visibility channel shift
register will perform a parallel load operation.
<01:00>

CONTROL

These

CHANNEL

two

controel
channel

cahnnel

each

distributed (daisy chained) to
each
channel
and
are
implemented within the control
to
perform
specific
functions.
The

imnplementation
is

S2,

signals

are

dependent

channel).

these bits within the control channel
(may be

Refer

description manual for
description of SDB, S2

implemented

the

differently

appropriate

20-169

1in

technical

the module (box) in gquestion
and S1 operation.

for

VAX 8600/8650 REGISTER DESCRIPTION
SFBCNT

STACK FRAME BYTE COUNT

SFRCNT

{ESCRATCH LGC: 17 — T07)

313&2928272825242322212@19133??515?61312“135’9953?85656493325!@
NUMBER OF BYTES {HEX) IN STACK FRAME — CURRENTLY 58 (DETERMINED BY EHM)

]

[

]

[

3
AR
-] 3803

It
(EHM).
This longword is built by the Error Handling Microcode
contains the number of bytes (in HEX) that the EHM will assemble in
the EBox Scratch Pad RAMS (location 18 through 1D). When the EHM
is finished building the Machine Check Stack Frame, it calls the
Interrupt Exception Microcode. The microcode pushes the contents
of the Scratch Pad RAMS onto the Interrupt Stack and calls the VMS
The MCHK Handler will wuse the
Machine Check (MCHK) Handler.
contents of this longword to process the stack but the SFBCNT will
not appear in the Stack Frame Record written to ERRLOG.SYS.
<31:08>

RESERVED

<07:00>

BYTE COUNT

HEX-88
currently 58
Indicates the number of bytes,
Decimal, that the EHM has pushed onto the Interrupt Stack.

20-170

VAX 8600/8650 REGISTER DESCRIPTION
SID
sig

SYSTEM {DENTIFICATION REBISTER

1PR 3E

[

CPU SYSTEM TYPE
i

[

PLANT CODE
i

0888888688800880LETE
b0 0000080000808

& oobobob bbb

NOT USED
o

fg; ZL50o

CPU REVISION

System

Identification

(SID)

register contains information unique to
the system:
the CPU serial number, the
processor type, the manufacturing plant
name and the CPU revision.
The
source
of
this
register is the Console, with
bits <31:24> being generated by Console
software
and
bits
<23:00>
jumper

PLANT CODE

<31:24>

—

CPU TYPE
This field identifies
type
and
Pprocessor
as
bits
<31:24>

<23>

\ USE THESE PINS TO STORE
UNUSED JUMPERS

the

CPU

specifies
the
04(X).
These
are generated by

the console software when
register
1is
read
(i.e.,
not
set
in
Jjumpers
on
backplane like the rest of
bits in this register).

» CPU BERIAL NUMBER

<22:16>
-

VAX

CPU

TYPE

VAX

8600,

kernal

= VAX 8650

specifies
revision
of

CPU.

Only

revision levels are
here.
To calculate
revision,
simply

NEVER INSTALLA
JUMPER HERE

one~to=one

number

01(X) = A,
etc.

ALL EVEN NUMBERED PINS (RIGHT HAND SIDE}
ARE GROUND.

the
are
the
the

CPU REVISION
This
field
hardware

using the console registers as shown in
the
BITMAP
above:
SID2 <23:16>, SIDI1
<15:08> and SIDO <07:00>.

selectable on the CPU
backplane,
J09.
The
contents
of this register (except
the software
generated
bits
<31:24>)
are
also addressable from the console,

18 w0 VAX CPU TYPE

The

sio

CPU SERIAL NUMBER

ECO LEVEL

[

the
the

MAJOR

ECO

considered
the letter
use
a

conversion

from

alphabet

thus:

02(X)

03(X)

MA-ISE03

<15:12>

MANUFACTURING

PLANT CODE

This
field
contains
a
code
which
represents
the
Manufacturing plant where
the
CPU
are

was built.
follows:

PLANT

20-171

codes

CODE

'MANUFACTURING

PLANT

(HEX)
1,

Current

GALWAY
FRANKLIN, MA
BURLINGTON, VT

MARLBORO,

VAX 8600/8650 REGISTER DESCRIPTION

SYSTEM IDENTIFICATION BEGISTER
29

CPU SYSTEM TYPE
&

ECO LEVEL
£

PLANT CODE

CPU SERIAL NUMBER
$

<11:00>

CPU

l
§

SERIAL NUMBER

This
the

field contains the CPU serial number (also
shown
on
silver label attached to the CPU cab:
top left rear)

converted to hexidecimal.
For example, if the CPU
serial
number
displayed
on
the serial number tag were MR00617,
the conversion would be 269(X).
Additional

(1)

(2)

Notes:

Refer to the diagram at
1left
which
illustrates
the
relative
bit
positions of the SID jumper, located on
the CPU backplane.
The SID register is read by VMS (via the Console)
and
will
be
1logged into each entry of the error log.
To
read manually, you can use the MFPR
instruction
(IPR
number 3E) or from the Console thus:
>>>E

SID

04045269

In addition,
display
the
the contents
176403.

(3)

the Console command 'SHOW
VERSION'
will
Hardware Revision Level in hex, which is
of SID <23:16> or console register SID2 /

vAX 8650 System SID Jumper Settings
SID

JUMPER

JP PINS

BIT

(IN/OUT)

VALUE

FUNCTION

17 19 21 23 25 27 29 31 -

23
22
21
20
19
18
17
16

ouT
IN
IN
IN
IN
IN
IN
ouT

1
0
0
0
0
0
0
1

8650

REV A

18
20
22
24
26
28
30
32

To verify the correct

SID

perform

EXAMINE

SID

shown

the

following

>>>EXAMINE

0481F095

example:

SID

(sample

system

20-172

ID)

the

jumper
MHC

prompt

settings,
(>>>)

VAX 8600/8650

!Splélfl

SOFTWARE INTERRUPT REQUEST REGISTER

31362‘928?

i!?’JB!S!S3321?1365&867051}5940302016{}
INTERRUPT
LEVEL
i
4§

i
A-13888

<31:04>

MB2Z
Must

<03:00>

zero.

INTERRUPT REQUEST LEVEL
The
software
interrupt

request

(SIRR)

write-only
four
bit
privileged register used for making
software interrupt
requests.
Valid
software
interrupt
levels
are OF:01 (interrupt levels 1F-10 are reserved for
hardware).

Executing MTPR SIRR requests an
interrupt
at
the
level
specified
by
bits
<03:00>.
Once
a software interrupt
request is made, it will be cleared by the
hardware
when
the
interrupt
is
taken.
If SRC <03:00> is greater than
the current IPL, the interrupt occurs before execution
of
the following instruction.
If SRC <03:00> is less than or
equal to the current IPL, the interrupt will
be
deferred
until
the IPL is lowered to less than SRC <03:00> with no
higher interrupt level pending.
This lowering of
IPL
is
by
either REI or by MTPR x, IPL.
If SRC <03:00> is 0; no
interrupt will occur.

§ig8

SOFTWARE INTERRUPT SHMMARY RERISTER

1PR: 15 (ESCRATCH LOCATION: 3?}

<31:16>

MBZ

Must

<15:01>

zero.

PENDING SOFTWARE INTERRUPTS - Levels 01-0F (HEX)
The processor provides 15 priority
interrupt
levels
for
use by software.
Pending software interrupts are recorded
in the Software Interrupt Summary
Register
(SISR).
The

SISR
contains
1's
in the bit positions corresponding to
levels on which software interrupts are pending.
All such
levels,

IPL, or the
interrupt.

¢ourseée,

must

processor

lower

would

than

have

the

taken

current

the

process

requested

SISR is a read/write privileged register
accessible
only
to
privileged
software.
At bootstrap time, the contents
of SISR is cleared.
The SISR is accessed using
MTPR
and
MFPR instructions.
<00>

RESERVED

20-173

VAX 8600/8650

SLR
SPADR

SLR

SYSTEM LENGTH REGISTER

PR 0D

27T

<31:22>

LENGTH OF SPT IN LONGWORDS

MBZ
§

12z

[

]

MBZ

Must be
<21:00>

zero.

LENGTH OF

SPT

LONGWORDS

The System Virtual Address space

is defined by the

System

Page
Table
(SPT),
which
1is
a collection of Page Table
Entries (PTE's).
The SPT is always
located
in
physical
address
space.
The
base
address
of the SPT is also a
physical address and
1is
contained
1in
the
System
Base
Register
(SBR).
The
size of the SPT in longwords (that
is, the number of PTE’'s) is contained in the System Length
Register (SLR).

SPADR

]

EBOX SCRATCH PAD ADDRESS

2‘5

PRINT LOCATION: EDPC (ADD MCA)

{ADDRESSED BY NAME FROM CONSOLE ONLY:

E‘G

i‘&

‘l"

***

<07:00>

CURRENT CONTENTS OF SPADR
3

WH-IE3TE

CURRENT CONTENTS OF

SPADR

When accessed by the Console, this register
will
contain
the
current
contents
of
the
Scratch Pad address lines
<07:00>,
Note that a CSM Overlay is
required
to
access
these
contents,
which may not reflect the actual address
prior to loading the CSM Overlay.
To examine the contents
of
SPADR
before CSM is started, the Console must examine
CSM.SPADRSC (which is ESC location C2).
NOTE

The SPADR register
via

the

following

»>>>EXAM

SPADR<cr>

>>>DEPOSIT

SPADR

(read/write)
console

1is

accessed

commands:

data<cr>

The SPADR lines are generated on
1logic
print
EDPC
by
the
ADD MCA and are distributed and
used

the

available

EDP

module

the

visibility.

20-174

only

backplane

and

are

not

wvia

SDB

VAX 8600/8650 REGISTER DESCRIPTION

SSP
EDP STATE

SUPERVISOR STACK POINTER

{PR: 02 (ESCRATCH LOCATION: £2)

of OF

VIRTUAL ADDRESS OF TOP OF STACK (SUPERVISOR MODE)
i

]

SUPERVISOR STACK POINTER

<31:00>

Contains the stack pointer to be
used
when
the
current
access mode field in the PSL is 2 (Supervisor Mode).

EBOX STATE REGISTER

STATE

PRINT LOCATION: EDPE

(ADDRESSED BY NAME FROM CONSOLE ONLY)
31

3(%

2::

27 2% 25

17 15:5

iQGQfiEG?GGQfiN

CONTENTS OF STATE REGISTER
]

BiTS <7:8> ARE READ/WRITE
MP-1537Y

<07:00>

CONTENTS OF

STATE

The STATE register is utilized
by
EBox
Microcode
as
a
miscellaneous
register
to control the microprogram flow.
A microinstruction is used to load the STATE register from

the
ARBUS
(refer
to DEF.MIC and any EDP block diagram).
The BEN field of the EBox microword
is
wused
to
control
microprogram
flow
and
may be used to select the various
bits of the STATE register to
control
selection
of
UPC
bits

<02:00>.

NOTE

The STATE register
via

the

following

>>>EXAM

STATE<LcCr>

(read/write)
console

accessed

commands:

>>>DEPOSIT STATE data<cr>

This register is also
available
on
the
SDB
visibility
bus
(all signals are generated on
CSB
the
on
terminated
are
and
Print:EDPE
module).

STATE BIT
7
6
5
4
3
2
1
0

SIGNAL NAME
EEP
EDP
EDP
EDP
EDP
EDP
EDP
EDP

STATE
STATE
STATE
STATE
STATE
STATE
STATE
STATE

20-175

7
6
5
4
3
2
1
0

H
H
H
H
H
H
H
H

SDB SYMBOL

B/P PIN

VSE138
VS$SE109
VSE177
VS$SE120
VS$SE184
VS$E136
VSE1l1l0
VSEL178

ACl10B84
AC10B86
AC10BBO
AC10B76
ACl10B74
AC10A07
AC1l0Al12
AC10Al17

VAX

8600/8650

STXCS
CONSOLE BLOCK TRANSFER CONTROL AND STATUS
29

5THCS3 — STATUS CODE
i
13

[}

§TX(82 — HIGH ORDER DISK ADDRESS

STXCS1 — LOW ORDER DISK ADDRESS
3

READY

I
03

i
0z

i
01

DiSK FUNCTION CODE

INTERUPT y

| ENABLE

<31:24>

STXCSO0

STATUS

Status

Initialized
CODE

CODE

current

transfer.

to ONE by

the

Only

CPU.

Transactlen_Complete
Continue Transaction

Transaction Aborted

Return_

Device_ Status

Handshake Errar _During_Transaction

Hardware

Errcr_During

STXCS2 HIGH ORDER DISK
Write only
by
CPU.
transfer.
The console
replacement

the

<15:08>

STXCS1

<07:00>

STXCSO

<07>

READY
Read only

by CPU.

INTERRUPT

ENABLE

<06>

Read

console.

STATUS

01
02

<23:16>

139483

LOW ORDER

Transactlon

ADDRESS
Logical

block

software

will

NOT

to ONE

number
of
current
perform bad block

RLO02.

DISK ADDRESS

1Initialized

the

console.

Write only by CPU.
<05:04>

RESERVED

<03:00>

DISK

FUNCTION

CODE

Disk
functions
to
perform.
Write
Initialized to ZERO by the console.
CODE

FUNCTION

o>
-

NoOperatlen
Continue Transaction

AbortCurrent_Transfer
Read Dev1ce Status
Write BlockData
Read_Block Data

20-176

only

CPU.

VAX

8600/8650

DESCRIPTION
STXDB
TBCHK

§TX0B

GCONSOLE BLOCK TRAMSFER DATA BUFFER

PR 4D

STXDB3

]

5TXDBY — HIGH ORDER DISK DATA
5

]

STXDB3

Must

<23:16>

STXDB2

<15:08>

STXDBl

<07:00>

STXDBO

Low

zero

Must

zero

High

order

Data

disk

should

STXCS

STXDB?

STXDBO — LOW ORDER DISK DATA

<31:16>

[»

data

data
be

RDY,

read

STXCS

from

<07>,

the

STXDB

only

when

set,

and

valid

only

the

STXCS
status
field
is
transaction)
or 4 (Return Device
function

field

(Reset

and

1
(Continue
Status), or the
Return

Device

Status).
Data

only

when

Transaction)

Block

written

the

this

STXCS

status

the

function

and

field
field

by
is

field

the

Data).

TROHK

CPU

(Continue

(Write

TRANSLATION BUFFER GHEGK

The

TBCHK

anticipated

use

DIGITAL.

the

TBCHK

the

MTPR

protection

1is

included

VAX/VMS.

1Its

1in

architecture
specification and use is

VAX-11/730,
the
if

field

the

virtual

the

PTE

the

condition

address

specifies

20-177

code

maps

bit

134T0

due

to
reserved
cleared

into

I/0

space

access

for

all

modes.

VAX

8600/8650

TBIA
TBIS

18IA

TRANSLATION BUFFER INVALIDATE ALL

IPR. 39

When the software changes a System Page Table Entry which maps
any
part of the current process page table, all process pages so mapped
must be
invalidated
1in
the
translation
buffer.
They
may
be
invalidated
by
moving
an
address within each such page into the
TBIS register.
They may also be invalidated by clearing the entire
translation
buffer.
This
1is done by moving 0 to the Translation
Buffer Invalidate All (TBIA) register with the MTPR instructions.
The translation buffer must not store
the
software
1is
not
required
to
entries when making changes for PTE'’'s

When the
the

invalid
PTE's.
Therefore,
invalidate translation buffer
that are already invalid.

location or size of the system map

entire

translation

buffer must

is changed

(SBR,

SLR)

cleared.

Whenever Memory Managegment Enable (MME) is a 0,
the
contents
of
the
translation
buffer
are
UNPREDICTABLE.
Therefore,
before
enabling memory management at processor initialization time, or any
other time, the entire translation buffer must be cleared.

TRANSLATION BUFFER INVALIDATE SINGLE

T8I

VIRTUAL ADDRESS

]

i
WR

When

the

software

changes

any

part

system or a current process

address

within

the

Invalidate Single

corresponding

(TBIS)

a valid Page

region,
page

Table

Entry

it must also move a virtual
to

the

Translation

20-178

138732

for

Buffer

VAX

8600/8650

DESCRIPTION
TODR

TRDR/TWDR

TOBR

PR 18
31

TIME OF YEAR REGISTER

,
30

i¢

©B

TIME OF YEAR SINCE SETTING
2

[

]

#MB.-

The

Time

Year

(TOY)

clock

elapsed

time

indicator

for

13873

VMS

and
the
means
by which VMS knows whether the console is running.
Power for the TOY clock (+5V B) is supplied by the
Battery
Backup
Unit (BBU) as long as the batteries can retain enough charge and if
the TOY ON/OFF switch on the BBU is in the
ON
position.
If
the
batteries
are
fully
charged, the BBU can supply power to the TOY
clock
The

for
TOY

100

hours.

<clock

incremented at
timing control

1is

implemented

a rate of
chip that

10 ms

per

count.

32-bit

is controlled by
TOY
clock
wvia

counter

uses

that

an Am9513

the
T-11
TODR, the

system

program.
VAX Time of

VMS
communicates
with
the
Day
Register.
The KA86 implements this register as a software register
in
the CBus RAM.
VMS loads and reads the TOY clock with MTPR/MFPR
#TODR.
The assembler translates "TODR" to address "1B" (hex).
The
EBox

the

microcode

TOY

clock

the

correct

The

timing of

used
the

by
BBU

turn

interprets

becomes

"1B"

invalid,

VMS

CBus

asks

the

RAM

location.

operator

load

also

time.

the Am9513

the
+5V

count

console

lost,

controlled

operating

system
communications

EMM

crystal which

for EMM
as well

communications.
If
as
TOY
operations

cease.

TROR

TOY READ DATA REGISTER

175000

gLz

REGESTER READ DATA

See

TWDR

]

Description.

TWOR

TOY WRITE DATA REBISTER

175002

CL22

£
AR 1A7E3

All

TOY

Chip

(Am9513)

can

read

registers (except the Command
written one byte at a time from the

Registers via the TOY Data Port.
The Data Port is
C/-D input to the Am9513 (CL03 RAS ADR 2) is true.
The

Write Register)
Read/Write Data

enabled when

the

registers that can be accessed in the CSL module are:
the Data
Pointer
and Master Mode Registers; and for each counter group, the
Hold, Load and Counter Mode Registers.
The Data
Pointer
Register
determines which register is accessed.

20-179

vax 8600/8650
TRSR

TURN

TASH

TOY READ STATUS REGISTER

175004

(L2

00R1

COUNTER

ER QUTPUTS {

QUTPUTS

(QUT <05.01>

l POINTER
BYTE

1
2,

NOTE: READ ONLY
MR- 14727

The Read Status Register (read-only) allows the
(BP)
and
the
state
of
the
counter outputs

byte
pointer
bit
(OUT <05:01>) to be
The Read Status Register may also be read via
the
Data

examined.
Port.

TURK

174013

(T-113

(CBUS)

l ;%IECT l

TOY UPDATE REQUEST NUMBER REGISTER

CL17.18

UPDATE REQUEST NUMBER

MR- 14207

The TURN register 1is implemented in the CBus
RAM.
Refer
to
the
KA86
Console
Technical
Description
manual
(EK-KA86C-TD), for a
detailed description of
<07>

TOY

This

TOY clock

operation,

SELECT

bit

has

two

uses:

It is set
before
(and
cleared
after)
the
console
updates
the
BTOY Register.
This will cause the EBox
microcode to read the UTOY reyister
(instead
of
the
BTOY
Register) if it executes an MFPR
TODR while the
console
is
in
the
process
of
updating
the
BTOY
Register.

It is set by the EBox microcode when
it
updates
the
TURN
Register
(via
an MTPR #TODR).
This will cause
the Console to update the BTOY Register in the Console
and
the
TOY
Counter
in
the
9513 (TOY) Chip.
The
Console will perform the
wupdate
request
during
its
next

<06:00>

UPDATE

interrupt

REQUEST

cycle.

NUMBER

This field contains a count of the number
of
times
that
the
UTOY
register
has
been written (updated via a MTPR
#TODR

instruction)

the

EBox microcode.

20-180

VAX

8600/8650

TWCR

TOY WRITE COMMAND REGISTER

175006

cL22

[C?,cs,cs,cach.czgm,m
The

9513

(TOY

Chip)

Status

Registers

Control

Port

ADR

1is

enabled

false.

COMMAND

Control
which

The

Registers

1is

include

accessed

when

the

following

via

the
the

C/-D

input

table

lists

the

8-bit

Command

and

Control

Port.

The

(CL03

RAS

the

9513

TOY

Chip

CODE

FUNCTION

Load

5S4

Data Pclnter Reglster
with
contents
and G fields.
(000<G<110 or G=111)
counting for all selected counters
Load contents of specified source into all

Arm

S84

Disarm

5S4

save

sS4

Ss3

Disarm

Set

Clear

101).
Step counter

Disable

selected
Load and

counters (NOTE 1).
arm all selected
counters

1).

(NOTE

and

save

all

selected

1).
all

selected

output

counters

(NOTE
Gate

1
1
11

1
1
1

1.
1
1

1
1
1

0
0
1

o
1
1

(N=001

for

counter

bit

for

counter

(N=001

data

pointer

FOUT,

set

2).
16-bit
data

mode,

MM<12>

set

pointer

Source

1is

Counter

Mode

Sets or
Register

MM<13>
seq..

2).
(NOTE

clear

2).
on

2).
MM<14>

FOUT, clear MM<12> (NOTE 2).
8-bit mode, clear MM<13> (NOTE 2).
Enable Prefetch for Write Operations
Disable Prefetch for Write Operations
Master reset,

for

(MM).

MM<14>

(NOTE

Enter

determined

clears

1).

101).
seq.,

NOTE

Hold

Enter

(NOTE

bit

Ena.
Gate

counters

(NOTE

output

off

(NOTE

(NOTE 1).
selected counters

101).

1
1
1

Commands.

appropriate

20-181

each

bit

counter

Master

its

Mode

VAX 8600/8650 REGISTER DESCRIPTION
TXCS
TXES

CONSGLE TRANSMIT CONTRGL AND STATUS BEGISTER

PR 22

TTM@CS3
i

7
13

RITE

MASK NOW
7/

7.
09

1D CODE

20
18
18
TXCS2 ~ TRANSMIT ENABLE MASK

TXCS1
.

)

720
07

TXCS

1.0

READY

LOBICAL

G, CONSOLE
06

TM*es

INTERUPT

ENABLE 7/

TXCS0

EMM

17
REMOTE

TERMINAL TERMINAL

16
LOCAL

%
MR RS

<31:24>

TXCS3
Must be

zero

<23:16>

TXCS2

<19:16>

TRANSMIT

ENABLE

This

field

Line

Enabled).

Console.

MASK

Read/Write

1is

by the

CPU and Read only

initialized to 01 by the Console

the

(Local

‘

A bit set in this field indicates that the
CPU
wants
to
activate interrupts for that line.
When the line is ready
the console will generate an interrupt via the TXCS.
<19>

ENABLE

LOGICAL TERMINAL

Corresponds
Conscole
<18>

ENABLE

"LOGICAL"

interface

EMM data

REMOTE PORT
to Console

Corresponds

<16>

ENABLE

Console

Subsystem

(i.e.,

the

path).

EMM

Corresponds
<17>

to the

to CPU

CONSOLE

Corresponds

line.

Remote

Services

Port.

TERMINAL

to Console

Terminal.

<15:08>

TXCS1

<15>

Write Mask Now
Read/Write by CPU and Console.

1Initialized to zero by the

Console.

This bit is set by the CPU to allow the MTPR microcode
to
write
to the Transmit Enable Mask Field.
The bit is used
by the Console to determine
which
operation
caused
the
Console interrupt; a Mask Field Write or a TXDB Write.
<14:12>

MB?Z

Must

zero.

20-182

vAX 8600/8650 REGISTER DESCRIPTION
TXCS
<11:08>

ID Field
Read only by CPU.

1Initialized

zero by

the

Console.

When the CPU receives a "RDY" interrupt, this
identify
the
1line that caused the interrupt,
line is now ready to transmit data.
ID = 0
Console Terminal
=

Remnote

ID =
ID =
ID =

2
3
F

Environmental Monitoring Module
Logical Console Data
No Lines Currently Enabled

<07:00>

TXCSO0

<07>

TXCS Ready
Read only by CPU.
When
set
to
a
specified in
the Transmit

<06>

Port

(EMM)

Data

1Initialized
to
one
by
the
Console.
one,
this
bit
indicates that the line
ID Field is ready to transmit, provided
that
Enable Mask Field is not zero.

TXCS Interrupt Enable
Read/Write by CPU.
1Initialized to zero
by
the
When
the
1logical
AND
of "TXCS RDY" and "TXCS

ENABLE"
Control
<05:00>

Services

field
will
i.e., which

is 1, a CPU
Block (SCB)

interrupt
1is
vector "FC".

MBZ

Must

zero.

20-183

generated

Console.
INTERRUPT

via

System

VAX 8600/8650 REGISTER DESCRIPTION
TXDB
THOB

CONSOLE TRANSMIT DATA BUFFER

TXDB3

- TXDB2

12 — 11

) G)

) 94

X081

nr,fi‘,;§§§§5§;§§§§§§3§;§2§§§§??
<31:08>

<07:00>

TXDBO — TRAMSMIT DATA

,ff,,,,'—zrtuf:»

MBZ

Must

Data

Byte

Write

The

zero.

only

code

destination

TXCS ID
0

1Initialized

TXCS

this

<11:08>

data

zero by

(ID

Code)

the

Console.

determines

byte.

Console

Terminal.

Console

Terminal

Output
Line

the

Data

Byte

the

Byte

(CTY).

Remote

Services Port.
Output the
Remote Terminal Line (RTY).

Data

Environmental

Monitoring
Module
(EMM).
Output
the Data Byte to the EMM.
The TXDB data byte may
contain any one of four HEX
values.
All
other
value will be ignored by the Console.

= CPU Request
The

EMM

for

data

EMM

Status

response

Information.

returned

via

RX registers.
01

= CPU
Request
Information.
returned

= CPU
If:

via

Command

the

System
data

Environment
response is

EMM

registers.

Control

Regulator

Margins.

1
1

=
=

0
1

---

Set
Set

all
all

margins

NORMAL

margins

LOW

Byte

Set

all

margins

HIGH

to cancel

current

and

Queued

requests.

Logical

Console.

Logical
byte may

Console
contain

_values.

for
The

the

Byte
Byte

= CPU Command
EMM

the

TXDB DATA BYTE DESTINATION AND DEFINITION

the
2

CPU.

All

Send

the

Data

Byte

the

for
processing.
any one
of
the

The TXDB data
following
HEX

other value will be

ignored by the

Console.
NOTE

The

following

data

Request

Request
of

the

codes

(2,

and

return

CPU.

Console

initiate

Console

clear

Warm_Start_Flag.

20-184

the

system.
Console

copy

VAX

8600/8650

DESCRIPTION
TXDB

TXCS

TXDB

DATA

BYTE

Request
of

the

DESTINATION

AND

DEFINITION

Console

to clear
Cold_start_Flag.

the

Console

copy

NOTE

The

following

return

data

the

(10,
CPU

11,

via

Request
the

codes

the value of
Warm_Start_Flag.

Request

the

value

12,

the

13,

and

20)

registers.

the

Console's

copy of

the

Console's

copy

Cold_Start_Flag.

Request the
microcode

16-bit
value
of
the
version
currently

Request
3
bytes
configuration data.

Used

system
being

executed.

condensed

array

by
diagnostics
and
error
handler
verification
tools.
Commands the Console
to
begin
accepting
a
Console
Command
String
(CCs).
Any
previous
CCS
1in
progress is aborted,
NOTE

The

CCS

bytes
e

may

consist

including

the

Null

ASCII

Bit <7> must be set in each ASCII
byte
that
1is
part of the CCS.
The Console
uses Bit <7> to identify
the
data
as
part of the CCS.

Individual commands in a

separated

with

CCS

pair.
®

512

Terminator.

The Console stores
buffer
until
it
The

the

ASCII

detects

must ‘be
character

bytes

Null

Byte.

Null

Byte terminates CCS
mode
and
causes
the Console to begin processing
the CSS.
The Console
stops
the
CPU,

exits

PIO

the

entered

were

Console

Mode,
halted

Mode,

processes

then

enters

CIO

Mode,

(just

though

command

exits

via

"CONTINUES"TM
the
PC, and re-enters

The Console will

the

CIO mode,

remain

CTY).

The

enters

PIO

CPU
from
CCS Mode.

CSS

its

Mode

until
it
receives
a
CSS
terminator
character set (<cr><lf><null>).

20-185

VAX 8600/8650 REGISTER DESCRIPTION

TXDB

COMSOLE TRANSMIT DATA BUFFER
22

1§

ix]

a?!nslas{m

%
09

DATA BYTE

TXDBO —TRANSMIT
DATA

DESTINATION AND DEFINITION

CSS ERRORS - The Console will
reject
the
CCS
and
return
an error code via the RX
registers
1.

The

if:

CCS

EXCEEDS

the

512

byte

BUFFER

SPACE

The
the

front panel switch indicates
that
CONSOLE is LOCKED.
The check for

the

locked Console
NULL character

the

not

made
received.

until

Because of the possibility of an RX
abort
message
occurring
at any time during the

issuing of
a
CCS,
required
to
poll
the

the
CPU
program
is
the RX register during

transfer.

Request the
the time of

32-bit

Request the
at the time

32-bit value of the
of its last entry.

Request

the

its

value of
last halt.

the

request

the

to
the

the
console
to
SNAP2.DAT
File.

Files.

the

to have

CSM Status

status

console

the VAX PC

return

two machine SNAPSHOT

console

have

invalidate
the
SNAP1.DAT
File.
The CPU
should
make
this
request
after
successfully
processing
the
SNAP2.DAT
File.

A
request
invalidate
should

make

successfully
File.
70

this

request

processing

the

Cancel

all

Console

Requests.

20-186

current

and

Queued

have
it
The CPU
after

SNAP2.DAT

Logical

VAX

8600/8650

DESCRIPTION
UsSP
UTOY

use

0-3

USER STACK POINTER

IPR: 07 (ESCRATCH LOCATION: £3)

313529282?3252#232223?{31’9

181?1515133312111@{?938&7&6

653‘&3326399

VIRTUAL ADDRESS OF TOP OF STACK {USER MODE)
K1

<31:00>

]

UTove

174014

)

mode

field

the

]

PSL

be
is

used

when

(User

Mode).

]

the

current

(cBuS)

174015

1§

uTeY2
s

74018
a0t

16
a7

UPDATE TIME OF YEAR BUFFER REGISTER
CL17. 18

[

TOY UPDATE DATA
i

USER STACK POINTER
Contains the stack pointer
access

uan

]

| S

I
F1

]

load

RAM byte

the

UTOY

MTPR

locations.

registers

#TODR

follows:

with

the

instruction.

The

08
UToY

00
UToY

+—+

alignment

will

specified

byte

data

CBus

bit

four

A e
e

TOY UPDATE DATA
The EBox microcode

‘kmlb

consists

<07:00>

UTOY

S
C

The

When the EBox executes a . MFPR #TODR
instruction, the
EBox
microcode
will
read
the data from the UTOY registers if
the BTOY registers are being updated
(see
BTOY
register
description).

NOTE

Refer
manual

the

KA86

Console

(EK-KA86C-TD),

Technical
for

information on TOY clock operation.

20-187

Description
detailed

VAX 8600/8650 REGISTER DESCRIPTION
VIBASAV

VPCBITS
YiBASAY

YIRTUAL IBUFFER ADDRESS SAVE REGISTER

{ESCRATCH LOC: 21 — T11)

@8 gf

<31:00>

‘

1BOX IBUF PORT VIRTUAL ADDRESS

virtual
IBuffer
This register contains the last
that was acknowledged by the MBox (PA ACK).

address

YALID PC BITS

¥PC BITS

PRINT LOCATION: ICB6, 7

(ADDRESSED BY NAME FROM CONSOLE ONLY)
3

TS SO TS SN YN WA NN SN NN SN VU WU SO S

TN T

IBUFFER VIRTUAL ADDRESS FOR INSTRUCTION BUFFER (IBUF PORT) FETCHES

Zf}

77"

GPC I1SA | ESA

An WVALIDVALY

NOTE: BITS <2:0> ABE READ OHLY

<31:03>

RESERVED

<02:00>

VALID PC BITS

These bits represent the validity

Counters:

CPC,

ESA.

and

1IsA

three

the

Program

1If the valid bit is set,

When
then the corresponding register contains valid data.
the CSM overlay is called to read this register, it simply

reads the status of

the following

and

signals

corresponding bits:
VPC

BIT
2
1
0

sets

‘

SIGNAL NAME

SDB SYMBOL

ICB B/P PIN

ICB CPC VALID H
ICB ISA VALID H
ICB ESA VALID H

VS$SEl44
VSEle6l
VSE129

ACl2C24
AC12B56
aACl2Cl4

NOTE

These signals are generated on the ICB module
(prints ICB6, ICB7) and are each terminated on

The VPCBITS register (read only)

the CSB module.

via the following console command:
>>>EXAM

VPCBITS

20-188

1is

accessed

the

VAX 8600/8650

0-3
XBUFC

{T-11)

XBUFD

174006

XBUF1
XBUF2
IBUF3

174007
174010
174011

(CBUS)

TRANSMIT DATA BUFFER REBISTER

07
1B

117 18
‘

TRANSMIT DATA
i

]

ROTE:
T-11 BITS READ
CBUS BITS WRITE

These
XBUFC

LUt

four registers (XBUF0-3) are used
1in
conjunction
register
for
transferring
data
packets
from

microcode

the

console.

This

communication

with
the

the
EBox
only
in

occurs

Console
I/0 (CIO) mode and will take place between CSM and MCP (if
in MACRO context) or DSM and DCP (if in DIAGNOSTIC context).
Refer
to
CSM
and
DSM
specifications,
and the "KA86 Console Technical
Description”

manual,

XBUFC

EK-KA86C-TD

for

operation

these

registers.

TRANSMIT BUFFER COMMAND REGISTER

174012

(T-11)

{Caus)

€L17,18

READY
PACKET
lACCESS
[ fiGNTRGLl
HiGHI UF

UATA

MR- 14300

The

XBUFC

1is

wused

conjunction

with

the

XBUFO0-3

registers
for
communication between the console software and EBRox
microcode.
This communication occurs only
in
Console
I/0
(CIO)
mode
and will take place between CSM and MCP (if in MACRO context)

DSM and DCP

(if

in DIAGNOSTIC context).

Refer

CSM

and

DSM

specifications,
"KA86 Console Technical Description", EK-KA86C-TD,
and "VAX 8600/8650 System Diagnostic User's Guide", EK-KA86D-UG.
<07>

READY RIGHT-OF-ACCESS BIT
When set indicates that the

into

the

Console
<06>

<05:00>

XBUF

software

read

PACKET CONTROL
When set indicates that
clear
indicates
that
for this transaction.

EBox

When
the

microcode

cleared

XBUF

may

load

indicates

that

data

the

another packet will follow.
When
the current packet is the last one
~

DATA

Application

dependent;

refer

specifications.

20-189

both

the

DSM

and

CSM