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Document:	VAXstation II Technical Manual BA123 Enclosure
Order Number:	AZ-GMZAB-MN
Revision:	0
Pages:	202
Original Filename:	gmzabmn.pdf

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AZ-GMZAB-MN

VAXstation Il
Technical Manual,

BA123 Enclosure

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AZ-GMZAB-MN

VAXstation |l
Technical Manual,
BA123 Enclosure

Prepared by Educational Services
of Digital Equipment Corporation

1st Edition, Januar

1 % 86

quipment Corporation 1986.

All Rights Reserved.
The material in this manual is for informational purposes only and is subject to
change without notice.
A

nt Corporation assumes no responsibility for any errors that may

appear in this manual.

FCC Notice This equipment generates, uses, and may emit radio frequency energy.
L]

s, which are

designed to provide reasonable protection against S uch dC
commercial
i

environment.

Operation of this equipment in a residential area may cause interferenc e 1in which
&l

case, the user, at hi s own expense, may be required to take measures to correct the
rference.

Printed in U.S.
"he manuscript for this book w [#as created on [a VAX-11/780 system and, vi:
#

Publishing System. The book was produced by E ducational Services Development
i

B2=

MicroVMS
VAX

Dt (
.

it
"

VAXstation

ork Processor

Contents

Preface

INTRODUCTION ... . X1
CONVENTIONS USED IN THIS DOCUMENT ............. Xil
Chapter 1
1.1

System Introduction
INTRODUCTION ... e
e e 1-1

1.2

SYSTEM COMPONENTS

1.3

SYSTEM ENCLOSURE

1.3.1

1.3.1.1

1.3.1.2
1.3.2

1.3.2.1
1.3.3

1.3.3.1

... ...

1-1

. ... ... . . . 1-4

BA123-AFrame .......... ... 1-5

Air Circulation . ........ .. i 1-6

Temperature Sensor Printed Circuit Board ............ 1-6
Control Panel ......... ... . .. .. 1-6

CPUConsole Board .................
... ... ... ...... 1-8
............c.c.iiiiiiiii
. 1-10

Mass Storage Area

Signal Distribution Board ........................... 1-11

1.34

Backplane Assembly ....... ... . . . 1-12

1.3.5

Power Supply ... 1-15

1.3.5.1

Electrical Distribution ...............
... ... ... ..... 1-18

1.3.6

I/O Distribution Panel

.............
... ... ... ........ 1-19

GRAPHICS SUBSYSTEM

... . 1-22

14.1

VR260 Monitor . ...t 1-22

14.2

LK201 Keyboard ............
... .. .
1-23

14.3

VSIOX Mouse . . ..o 1-23

Contents

System Description

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Chapter 2

Contents

Configuration
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Chapter 6

FRU Removal and Replacement
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Left Side Panel Removal
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' Main Printed Circuit Board Removal

6.4.2

RD53 Disk Drive F lectronics Board Removal .................¢
%

Contents

FAN
»fii& E REMOVAI
AN VLI AW
f”«srr

LB IR R I RN NO O O I B N O N A A A
516
e i Q}Wfl‘.w}
Mass Storage Fan Removal ................................6-16

(Mw fzi M%W Fan Removal ............ e P

&
5

iQR

o = I

e eeueraeaeee.....6-18

Precautions ........................ e 6-18
Removal . ...

..
.....6-18
"}@fifiw INT %‘;RMMR %WIfM% M* MMM% NI ¢ 24 .
T

| ?WWHJM ;%HW’LW m MKWMM e e .. 6-22

BACKPLANE ........ e e P
» PR

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Replacement ..... e e mm

TOR %m@
Cover and Rear Bezel . ... ... e, 626
Removal .............. e R
o 7 o1
Replacement ......... .. ... ... .
.. .. 6-26
6.12.2.1

Deflection Board ............. .. ... .
... ...627
Removal ............ ef WM?

Replacement .
S
,
A
CRT Assembly ........... ... ....U Cereraee.... 628
6.12.3.2

Removal ................ e e..., 628
Replace
.......ment
... ...
i, 6-28
Power LED ..... . ... ... ... .. ... . . ... e ceeee... 629
Removal ....... ... ... . . .
Replacement ..................

ce.... 629
... i
... 629

Monitor Alignment ........................ P

Appendix A

Console Commands

Appendix B

Console Error Messages and Explanations

Appendix C

VCBO1 Video Controller Module

Index

=% 1

Contents

Figures

1-1
1-2
114
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-18

VAXstation II System Components ...................... R
BA123 Enclosure ................. e . e 1-4
BA123 Removable Panels md Dmm eP
S
5
Airflow ......... e e AU eP
6
Temperature bwmmw wwwwwwwwwwww e
1T
BA123Front Control Panel Cutouts ........... e AP S17
CPU Console Board . ........ .ot...
198
Mass Storage Shelves ......... e
.1410
Signal Distribution Board .............. e RS
B3 8 |
Signal Distribution Board Cabling ........ e URTCU
1-13
Backplane Grant Circuitry ......................S
S 1-13
Backplane Connectors ........ e
e
114
Power Supply . ... e
115
Circuit Breaker, Voltage "y@*lect Swuch, (J(mnmmm (Rmr Vl%fi:‘W) .
1-17
Electrical Distribution . ... ceveo.... 1-18
Rear
Door . ... ...
a2
1-19
Rear 1/0 I)Mrlbmmn Bmm“d ee cee.. 1220
[/O Insert Panels and Adapter Plate ......... ... ... ... ... .. ... R 524|

1-19
1-20
1-21
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
3-2
3-3
3-4
35
3-6
4-1
4-2
4-3
4-4

VR260 Monitor ............ ee... 1222
LK201 Keyboard .
.......... U
AU UPUPEE A 1&4
VS10X Mouse Device ............ e e R
. 1-2
KA630-ACPUModule
.. ...t RRN ?223
CPU Patch Panel Insert ....... .. ... . ... ciiiiiit.. S D¢
VCBO1 Video Controller Module ........eA
2-9
RQDX3 Controller Module .................... .. 2-13
RD52 Fixed Disk Drive ... ...... 216
RX50 Diskette Drive . ... .
ie
217
TK50 Tape Drive Subsystem ................ e ceenenea... 2-18
M7546 Controller Module
.......... e erareieansS A 2-19
DEQNA Ethernet Controller Modul@ AAP 3-3
DEQNA Module Internal Cabling ...................... PR
=
DZQI1I Module . ...
e 3-6
DZQ11 Module Internal (/z»mflmg P ... 38
GraphicsTablet Components .. ... PP T
Graphics Tablet Connector Pins .. ...........OO
JConfiguration Worksheet . ... ... e e e 4-3
Base System .. ... £
Completed Configuration Worksheet . ...............A
8!
Advanced System . ............... e
B
S 0

Contents

Completed Configuration Worksheet (Advanced System) ........... ... 4-13
CPUModule LEDs ............... e e 5-1
DEQNA Module LEDs . ...........A

RQDX3Module LEDs .................... ee ... 58
TQKS50 Module LEDs .................... e e e 59
MicroVAX Maintenance System Mmm Tree ........ e e .. 5-10

Boot Failure Troubleshooting Flowchart . ............e
DS
Device-Specific Failure Troubleshooting Flowchart ...................515
BAI123-AFRUs ................. e e 6-2
Unhooking the Right Side Panel

............S R
Right Side Panel Removal. . . . ... P
¢
Unhooking the Left Side Panel ...................... e e ... 66
Left Side Panel Removal .....
... ... .. ...
....
. . . . . . . . . ... ... ... 6-7

ON/OFF Switch Removal ........... ... ... .. ......... R
=
CPU Console Board Removal ............ e ....69

Slide Plate Removal ........ ... ... ... .. .. ... ... .......N e 8
Removing the 2-pin Connector gmfl &aamw&, e 6-11
Front Bezel Removal...................... eS
12
Removingthe Phillips Screws from thwnl{ e e 6-13
MPCB Removal ...... ... .. ... ... . .. . . . ... ceen....6-13
RD53 Device Electronics B«(md Hmmval ... e

6-15
Mass Storage Fan Removal ............... .. ee 6-16

Card Cage Fan Removal .........
.. e I =
Module Removal . ....................... e 6-19

6-19

Temperature Sensor/Door Inter mck bw*xtah ””””””” eR 6-21
Power Supply Removal . .. .. e
e 6-23
Backplane Removal ................. ...e ... 624

6-21

Deflection Board and Chassis Door Location .................... ...L. 627
Power LED Removal/Replacement ... ... .. e 6-29

6-23

VR260 Monitor Adjustments, H CE NT, W]WE“H and LIN ... .. c...6-31

6-20

6-24
6-25

C-1

Monitor Alignment Patterns ........ ... . .

6-30

VR260 Monitor Adjustments (Top) ................. e . 6-32

VRZ260 Monitor Adjustments, Focus and G2 ....... e e cee 6-33
VCBO1 Module, Simplified Block Diagram ...........................C2

VCBO1 Module, Functional Block Diagram

C-4

C-5

......................... . C-3
VCBO1 Module, Simplified Timing Generator ........... e C-4
VCBO01 Q22-Bus Interface . .........
.. . e Cienees e C-6
VCBO1 CSR Read/Write Paths .. ... ...e e e C-8

Video Memory Access Cycle .......... e P
O=¢
CRTC Horizontal Timing ...... i ie i
e R .. C-10
CRTC Vertical Timing ................... eSN C-11

Cont

ents

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Video Memory Read (RAM Refresh)

Video Memory Read (Video Refresh) .. ... e AURPPENRE

Mouse Construction .. ..., ... 23

Sed

Video Memory Write (Update) ............SS

Mouse Interface ....... ... ... .. ... .. ...... T

VR260 Monitor Display Mapping ........ e s .. C-13

...............................C19

Keyboard Interface ............... A

Scan Line Map Write (Update) ............. e e C-21
Cursor

RAM Read/Write .. ...

..S C-22
S

C-26

MicroVAX Physical Address "apm,,u ***** e e... G227
VAXstation Il Physical Address Space ............. e ... 28
VCBO1 256-Kbyte Address Space . ...

... C28

C-21

VCBO1 CSR Format ................ e

... C-30

C-22

VCBO1Cursor X-Position Format . ... e e R R

C-23

Mouse Position Register Format ................ eB ... CG31

C-24

CRTC Address Register Pointer Format ...................... oo

C-25

CRTC Data Register Format.............. Ceeeeehan AR
A ... C33
... .. .

.. R

O3|

G133

C-26

ICDR Register Format .. ...

C-27

ICSR Format ...... e P ... G35

C-28

Mode Registers 1A and M Mrmat

C-29

Status/Clock Select Register A Pwmmt e

C-30

Command Register A Format ..........e U

C-31

Transmit/Receive Buffer A Format ........... e AP C-43

Interrupt Status/Mask Register Format ........................ el C-43

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39
G40

SR .. C42

Regulator A and B Current and Power ..........................1-17

1-2

LLK201-AA Keyboard Physical and Electrical Specifications ........1-24
VS10X Mouse Physical and Electrical Specifications ..............1-25

NI SN

Cutout, InsertPanel Size . ... . .
... . .. ... . . ... .. R 1-21
VR260 Monitor Physical and Electrical %pmxmmxmm wwwwwwwwwwww oL, 1-23

;‘

VAXstation II Configuration .................. A S e

Tables

UM‘MW Program Boot Sequence .......... s A cev..2-D
CPU Patch Panel Insert Switches . .......
... .. ... .. ........ e . 2-7
MS630 Memory Modules . ........ ... 278
RQDX3 Controller Module ... ... e 2-10

CSR Base Address Select . .............. e e 2-10
1
VR260 Monitor Display Density ‘wimmm e e e 2-11

RQDX3 Controller Module CSR Address . .......................2-14

(O @

Contents

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Example of Vector Bits <08:03>

.. ................. e 3-2

DT O o

DEQNA CSR Address Settings ............... e
34
DEQNA Interrupt Vectors ... ...... ... 3-4

DEQNA Interrupt Vectors ................. e P.34

DZQ11 Module CSR Address.

G S
DZQ11 Module Interrupt Vecuw wwwwwwwwwwwww e R R 3-7

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.‘M%::wi»b Leci»:ntm:fim Mfiz,,.w;ium K‘h‘“fit .Nmmbw ::;awfi::}m e
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Example of a 22-bit CSR Address . .............................32

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32}.
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RQDX3 Controller Module LUN Jumpers . ...................... 2-15
M'?%fi Cmm wflm Mmdmfiw (,%R Addm% 02220

Graphics Tablet Physical and E@thml ‘%pm 1fmm«mm e 3-8
Graphics Tablet Pin Assignments ....................S 3-10
Power Requirements, Bus Loads, I/O Inserts ....................4-5
Address/Vector Worksheet

.......... ...
... ...... e.....4-8
Floating CSR Addresses .. .............. e e 4-9

Diagnostic LED Status and Error Messages ... ...e ... 52
DEQNA Module LEDs

5-3

TQKS50 Module LEDs . ...

i
1

5-5

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CRTC Internal Registers ................e
G32
CRTC Address Register Pointer Bits ..................... e C-33

ICSR Bits
......e C
AP
O 13
ICSR Commands ....................... T C-36
Interrupt Controller Mode| «Mu%m Bits ...
...
. C-38
Mode Registers 1Aand 2A Bits . ...............................C-40

Status/Clock Select Register
Command Register

Transmit/Receive Buffer

,‘

CRTC Data Register Bits . .........e P
O
ICDRBi
... ... .. . ts .. e e C-34

syl

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VCBO1 Registers . ...................... e e
i‘;‘:

Smenmns

"»/(,H(M QQI{ Bm e e e C-30

éffi;fi{‘:

) VSN W

OGO

0. . ...
.. .. 5-16

é\ffifi(flfllmmH“MHMWMH wwwwwww e ce... C4

..... e 5-9

BA123-A FRUs . ...
. e ....6-3
Console Error Messages . .. ..ottt ....B-1

... ... ...

VR260 Monitor Failure [ Indications ... ..........
.. e 5-16

g i E {% &

............. e R

VR260 Monitor Failure Indications .. ......... ...

£3

5-1
5-2

ABits

ABits ...
.. ... . .. .. . ..., .. C-41
.................. .. C42

ABits . ........... .. . .
... C-43
Interrupt Status/Mask Register Bits ............................C44

Preface
INTRODUCTION

The VAXstation II is a single-user workstation based on the MicroVAX II
processor. It contains the VCBO1 single-plane bit-mapped video subsystem, an
RQDX3 mass storage subsystem, and the MicroVMS operating system. A technical/graphics workstation is formed with the addition of the VR260 monitor, an
LK201-AA keyboard, and a VS10X-EA mouse. The workstation can be used as a

stand-alone system, or, using the DEQNA Ethernet controller, in a clustered
environment of print servers, disk servers, and other workstations.

This manual describes the VAXstation II base system, its service procedures, and
configuration of options. The manual is meant as a reference tool for Digital’s Field
Service engineers trained to maintain the VAXstation II system.

e Chapter 1, System Introduction — Describes and lists the general and physical
characteristics of the base system.

e Chapter 2, System Description — Describes the major functional components of
the base system, and includes information about addresses, switches, and
indicators.

e Chapter 3, Options — Describes the optional modules that can be installed to
extend the base system’s capabilities, and includes information about the
addresses, switches, and indicators of the options.
e Chapter 4, Configuration — Describes configuration rules, and switch and jumper
settings.

e Chapter 5, Diagnostics — Describes the MicroVAX Maintenance System (MMS)
and error reporting, and includes basic troubleshooting guidelines.

e Chapter 6, FRU Removal and Replacement — Describes FRU removal and
replacement procedures.

e Appendix A, Console Commands - Describes the command line processor, and
lists and describes the available commands, giving their proper syntax.

Preface

Appendix B, Console Error
U,

Messages and %Wmm%mm ~ Lists and describes the

error messages generated by the command line Iprocessor.

Appendix C, VCB01 Video Controller Module

— Describes the module’s architec

ture and provides register and www%mmmgg :imn%%:«z&‘m:f“m;mt;fi{:‘:m%

Contains information to prevent damage to equipment.
Contains information to prevent personal injury.
Read as

“mm throughnn.” This use of angle brackets and
the colon indicates a bit field or a set of lines or signals. For
example, A<17:00> is the mnemonic for Unibus address

lines “AW through A00.”
<RETURN>

A label enclosed by angle brackets represents a control or

special character key on the keyboard (in this case, the
Return key).

<CTRL>C

Control sequence. Press the special function key <CTRL>
and the standard key C at the same time.

System Introduction
This chapter describes the general and physical characteristics of the VAXstation

II. The major physical units are:

1. System Enclosure
2. Graphics Subsystem I/O Devices
1.1

INTRODUCTION

The VAXstation II is a single-user workstation based on the MicroVAX II
processor. It is mounted in the BA123 enclosure frame, a floorstanding unit for
microcomputer systems. The enclosure is air cooled and is designed to operate in
an open-office environment. It supports a variety of hardware options. Table 1-1

lists a typical VAXstation II configuration.
1.2

SYSTEM COMPONENTS

Several major components make up the VAXstation II. (Figure 1-1) These are the

BA123 enclosure, which houses either an RD52 fixed disk drive and RX50 diskette
drive, or an RD53 fixed disk drive and the TK50 tape drive, depending upon the
particular system configuration. Also included within the BA123 enclosure are the
system controls and indicators, backplane, mass storage area, power supply, and

I/0 distribution panel.
The VAXstation II graphics subsystem consists of a VR260 monochrome monitor,
LK201 keyboard, VCBO01 video controller, and the VS10X mouse. An optional
graphics tablet that uses either a hand-held puck or stylus may be used in place of
the mouse.

The VCBO1 video controller is a quad-height module (part number M7602-YA)
that provides a mouse interface, keyboard interface, and cursor controls for
creating displays on the VR260 monitor.

1-1

Table 1-1

VAXstation II

Function

Component

onfigurat

&
e

Des cript

rval

Tt E]

%£ gt

]

818-Kbyte dual diskette drive

= m«

s= fi

TMSCP (tape mass storage control protocol).

System Introduction

WITH THE PUCK OR

L2001 KEYBOAHD

RHBD
——

TKBO
"

| veBo1 VIDEO CONTROLLER
4]

FOR RDn SERIES FIXED DISK
DRIVES

Figure 1-1

VAXstation Il System Components

System Introduction

1.3

SYSTEM ENCLOSURE

The BA123 enclosure (Figure 1-2) contains the MicroVAX II CPU, the VCBO01
video controller, mass storage devices, and options. The air-cooled enclosure
operates in an open-office environment and includes the following major sub-

assemblies.
e Frame
e (Control panel

e Mass storage area
Backplane assembly

o Power supply

I/0 (input/output) distribution panel

Figure 1-2

BA123 Enclosure

System Introduction

1.3.1

BA123-A Frame

The BA123-A frame houses the power supply and the backplane assembly, and

includes space for five 13.3 cm (5.25 in.) mass storage devices. Mounted on four
shockproof castors, the BA123-A frame has the following dimensions.

e Height: 62.2 cm (24.5 in)
o Width: 33.0 cm (13.0 in)

e Depth: 70.0 cm (27.5 1n)
Removable panels cover the front, right, and left sides of the enclosure frame
(Figure 1-3).

There are three doors: a control panel door on the front, an I/O panel door at the
rear, and a card cage door inside the right side panel.
NOTE
For panel removal procedures, see section 6.1.

CONTROLY

L.,

PANEL
DOOR

(| FRONT PANEL

" RIGHT
SIDE PANEL

L
Figure 1-3

BA123 Removable Panels and Doors

System Introduction

1.3.1.1

Air Circulation - Three fans in the BA123-A frame draw air from th:

bottom of the enclosure. (Figure 1-4) Air is drawn from below the module card

cage, behind the control panel, and from inside the power supply.
1.3.1.2 Temperature Sensor Printed Circuit Board - A printed circuit (P
board above the card cage contains two temperature sensors. (Figure 1-5) One

sensor regulates the speed of the card cage fan at the minimum level required {
maintain a constant temperature within the card cage. The other sensor, the ov.
temperature sensor, shuts down the system at high temperature. The card cage

door encloses the area surrounding the modules. If this door is removed, an

interlock switch is triggered, and the speed of the card cage fan is increased to
maximum. If the proper temperature within the card cage cannot be maintainec
even at maximum fan speed, the over-temperature sensor will cause the systen

shut down. The system also shuts down if the card cage fan fails.
1.3.2

Control Panel

The control panel has six cutouts to provide space for control circuits. One cuto
is used for a CPU console board. The other five cutouts provide space for mass

storage control boards. Unused cutouts are covered with removable plates. Figu

1-6 shows the relation between the cutouts and the mass storage shelves.

MASS STORAGE
FAN

Figure 1-4

Airflow

System Introduction

”’“‘M.M,‘,M

MWMM

Figure 1-5

Figure 1-6

Temperature Sensors

BA123 Front Control Panel Cutouts

System Introduction

1.3.2.1

CPU Console Board - The CPU console board (Figure 1-7) is attached

to the back of the control panel. It contains a DC OK indicator light and two
buttons that let the user halt or restart the system. A ribbon cable connects the

CPU console board to the backplane. This cable provides the connection between
the CPU and the CPU console board.

RESTART/RUN

]

DC OK

HALT

(REGULATOR A}

(REGULATOR B)

Figure 1-7

CPU Console Board

System Introduction

The buttons and DC OK light provide the following functions.
¢ When the HALT button is pressed, the red LED in the

HALT button lights up.

If halts are enabled by the switch on the CPU distribution panel at the rear of
the system, the system enters “Console I/O Mode” when the HALT button is
pressed.

NOTE
If halts are disabled at the rear of the system, the LED in the

HALT button will still light up when the button is pressed, but
the system will not be halted.

e When the DC OK light is on, the system is receiving stable dc voltage from the
power supply.
e When the RESTART button is pressed, the system boots.

There are two LEDs on the CPU console board. These can be seen by removing
the left side panel of the enclosure. If the DC OK light on the control panel is not

lit, the two LEDs on the CPU console board indicate which regulator supply to the

backplane has failed.

= Regulator A

Right LED

= Regulator B

LED is ON

= +5 Vdc to the backplane is OK

LED is OFF

= regulator or connection to regulator has failed.

Left LED

NOTE
There should be at least one module in both an odd and even
numbered backplane slot to draw enough current to start each
regulator.

There is a DIP switch pack to the left of the LEDs that contains two switches. Both
switches are normally OFF and are not used in VAXStation II systems.

1-9

System Introduction

1.3.3

Mass Storage Area

The front panel covers five shelves used for mounting 13.3 cm (5.25 in) mass

storage devices is four. These should be installed with two in shelves 1 and 2 and
two in shelves 3, 4, or 5. Removable plates in front of shelves 3, 4, and 5 allow
access to removable media devices.
Devices normally occupy the shelves as follows.

Figure 1-8

Mass Storage Shelves
o,

System Introduction

1.3.3.1 Signal Distribution Board — The Signal |Jistribution Board (M9058,
Figure 1-9) is mounted in the bottom two (C and D) 1-ows of backplane slot 13.

c@)l

EW{WL-:LH

[ii?:]!j

RD3

[:{TTZ#J

RD?2

Figure

1-9

Signal

Distribu

tion

Board

System Introduction

Uw to fmIr nmi {li%’k drivw or an RW&(‘) d’i%%‘%tm dr‘iw MM mm to ”W(} fi%m‘i Clifl‘;k

n be connected to the signal distribution board cabling. (Fig

wwm} mt im@rwtm ‘tmmd1S umm«;u d to an WZM)H mass wm age mmtmflw
module (M7555)in the card cage by a 50-conductorribbon cable. The signal
distribution boardis also connected tothe RD mmmm boards behind thecontrol

panel by a 40-conductor ribbon cable.
1.3.4

Backplane Assembly

The BA123 has a four row by thirteen slot backplane that measures 27.9 X 19.9 em

(11 in X 7.85 in). The backplane implements the extended LSI-11 bus (or Q22Bus), which uses 22-bit addressing.

The first twelveslots of the backplane provide space for dual or quad-height
modules that are compatible with the Q22-Bus.

A dual-height module has connectors that fit into two rows of a backplane slot.
Two dual-height modules can occupy one backplane slot.

A quad-height module has connectors that fit into all four rows of a backplaneslot.

One quad-height module occupies one backplane slot.
NOTE

Dual-height modules in slots 5 through 11 and rows C and D of
slot 12 require another dual-height module or an M9047 grant
card in the other two rows of the siot.

Figure 1-11 shows the Q22-Bus interrupt and direct memory access (DMA) grant
lines. The C and D rows of slots 1 through 4 implement a separate MicroVAX 11

local memory interconnect used to interface the system CPU and memory

modules.

Four 120 ohm resistor packs between backplaneslots twelve and thirteen are used

to terminate the Q22-Bus.

The thirteenthslot of the backplane provides space for two dual-height modules
(rows AB and CD). The Q22-Busis notimplementedin this slot. The CD rows are

used for the signal distribution board. The AB rows can be used for a second
signal distribution board. The thirteenth slot provides +5 Vdc, +12 Vdc, ground,

and a signal (BDCOK) that indicates the dc voltage from the power supply is

stable.

NOTE
This backplane is a “bounded” system. That is, an additional
backplane cannot be connected to the system.

System Introduction

17-00867-01

CPU COMSOLE BOARD
TO BACKPLANE

17-00860-01 — N _/ |
o

M7855

17-00861-01

7-00282-01

Figure 1-10

SLOTS
7

REAR OF

SYSTEM

FRONT OF

SYSTEM

Signal Distribution Board Cabling

Figure 1-11

Backplane Grant Circuitry

System Introduction

The backplane supports a maximum of 38 ac loads and 20 dc loads. The backplane
balances the load on each of the power supply’s two regulators. Figure 1-12 shows
three J connectors on the backplane. J1 and J2 are 18-pin connectors that receive

dc power and signals from two independent regulators in the power supply. J3
provides the connection between the CPU installed in the backplane and the CPU
console board.

J1 1s connected to regulator A, which supplies power to the odd-numbered slots
and the resistor packs.

J2 is connected to regulator B, which supplies power to the even-numbered slots.

J3 is a 10-pin connector for a cable to the CPU console board.

Figure 1-12

Backplane Connectors

System Introductio

The backplane has an eight layer PC board, which is arranged as follows.

Signal
Ground

Ground
+12 Vdc from power supply regulator

OO0 =3

Vdc from power supply regulator

0 Do

Signal

Signal
Signal

Chapter 4 explains the backplane configuration rules.
1.3.5

Power Supply

The power supply (Figure 1-13)is a 460-watt unit consisting of two regulators.
Each regulator supplies power to one-half of the slotsin the backplane and to the
mass-storage devices inside the system.

2
Figure 1-13

Power Supply

System Introduction

The power supply provides protection against excess voltage and current, and
protection against temporary fluctuations in the ac power supply. Table 1-2 lists

the minimum and maximum currents supplied by each regulator.

NOTE
Total power used from each regulator must not exceed 230 W.
This means that maximum current at +5 Vdc and +12 Vdc

cannot be drawn at the same time. See the configuration work-

sheet in Chapter 4 for further information.
The power supplyalso has two separate +12 Vdc outputs that are independent of
the main 460 W «zmtpm
t. These are used to drive the two fans that are external to
the power supply, and to provide power to the temperature sensor above the card
Cdge.

The power supply contains a connector at the back for remote control of the power.
The input power cableis protected by a circuit breaker. (Figure 1-14) There is an
International Electrical Commission (IEC) ac input connector for compatibility
with international power cables.

Two voltage ranges can be selected:
120V
=

8-128 Vac

240V = 176- 256

V ac

NOTE
In order to compensate for line cord voltage drop when the
system is operating at maximum load, a minimum of 90 volts ac
(88 - 128 V setting) should be present at the outlet for low-line

operation.

System Introduction

Table 1-2

Regulator A and B Current and Power
Power

Current at +5 Vdc

Current at 12 Vdc

Regulator

Maximum

Minimum

Maximum

Minimum

230 W

45 A

36.0 A

0.0 A

CIRCUIT

BREAKER TM,

REMOTE
CONTROL

CONNECTO
=
R
VOLTAGE

SELECT

SWITCH
S

’

Wy
—

ACPOWER

CONNECTOR
.

Figure 1-14

7
s

Circuit Breaker, Voltage Select Switch,
Connectors (Rear View)

= -

Maximum

7.0 A

System Introductio n

1.3.5.1

Electrical Distribution - Figure 1-15 shows the electrical power distri-

bution of the enclosure.

POWER

The part numbers of the power cables are also shown.

SUPPLY

J
REGULATOR

switcH

|
JBA

J9A

17-00911-01

[
%1 MASS STORAGE DEVICES |
bl [N SHELVES 3, 4, AND 5

17-00865-01

e BACKPLANE J1

(ODD NUMBERED SLOTS)
REGULATOR

188

jpe—l00870-01

JOB

el 0086

o4 MASS STORAGE DEVICES

L
& INSHELVES 1 AND 2

17-00865-01

»d BACKPLANE J2

(EVEN-NUMBERED SLOTS)

17-00863-01

CARD
- CAGE FAN
J10

TEMPERATURE SENSOR | (SEE NOTE 2)
PC BOARD

| INTERLOCK
SWITCH

17-00864-01

MASS STORAGE FAN

AC POWER CORD
1.

(INCLUDES THE ON/OFF SWITCH) 17-00859-01

(INCLUDES INTERLOCK SWITCH)

Figure 1-15

17-00942-01

Electrical Distribution
.

System Introduction

1.3.6

1/0 Distribution Panel

The 1/0 distribution panel 1s used for connecting the system to external devices.
The rear door provides access to the I/O distribution panel. (Figure 1-16)

Each module that connects to an external device requires an internal cable, a filter
connector, and an insert panel. Together, these three items are referred to as a
cabinet kit.

Filter connectors are mounted in the insert panels. The insert panels install in
cutouts in the I/O distribution panel. The CPU I/0 distribution panel insert 1s
typically mounted in cutout A. Unused cutouts are covered by removable plates.

Figure 1-16

Rear Door

System Introduction

The rear I/O panel has ten cutouts. (Figure 1-17) Table 1-3 lists the cutout and
corresponding panel sizes.

In addition, a removable bracket between the bottom two type B cutouts allows
three more type A insert panels to be installed with an adapter plate. Figure 1-18

shows typical type A and type B insert panels, and the adapter plate.

TYPE

B —~—J
o

TYPE

A —_

/ L]

[ & ) ,

\e/\e/\&/

Figure 1-17

1-20

Rear 1/0 Distribution Panel

System Introduction

Table 1-3

Cutout, Insert Panel Size
Ed

mim

Type A (4)

Cutout
25 X 102

Insert Panel

Type B (6)

Cutout
Insert Panel

ADAPTER

PLATE

~aae.

REMOVABLE

BRACKET

POST

Figure 1-18

I/0O Insert Panels and Adapter Plate

System Introduction

1.4

GRAPHICS SUBSYSTEM

The major physical units of the graphics subsystem are:

e Monitor
e Keyboard

e Mouse.
1.4.1

VR260 Monitor

The VR260 is a 48 cm (19 in) diagonal, non-interlaced, 60 MHz, input bandwidth,

monochrome monitor. (Figure 1-19) It can display graphics and text with a
resolution of 1024 X 864 pixels (horizontal X vertical). It has a horizontal scan rate

of 54 KHz and a 60 Hz refresh rate. Table 1-4 lists the monitor’s physical and
electrical specifications.

Figure 1-19

VRZ260 Monitor

System Introduction

Table 1-4

VR260 Monitor Physical and Electrical Specifications

Height

38.10 cm (15.00 in)

Width

45.72 cm (18.00 in)

Depth

40.64 cm (16.00 1n)

Weight

20.50 kg (45.00 1b)

Viewable

1024 X 864 pixels

Area

AC Power
Requirement

1.4.2

120 Vac at 1.0 A
240 Vac at 0.6 A

LK201 Keyboard

The VAXstation II keyboard, LK201-AA, (Figure 1-20) is connected to the VCBO1
video controller subsystem through the I/O panel insert and a coiled, 4.78 m
(19 ft), cable (BC18P-10). The keyboard’s physical and electrical specifications are
listed in Table 1-5.
1.4.3

VS10X Mouse

The mouse (Figure 1-21) is a hand-held device that moves a pointer displayed on
the monitor screen. It is attached to and receives power from the VCBO1 subsystem through the I/0 panel insert and a 3.7 m (12 ft) cable. The mouse generates
relative-position data (quadrature-encoded, X and Y axis), and includes three
buttons for event signaling. The mouse’s physical and electrical specifications are
listed in Table 1-6.

System Introduction

Figure 1-20

Table 1-5

LK201 Keyboard

LK201-AA Keyboard Physical and Electrical

Specifications
Height

5.10 cm (2.00 in)

Width

53.30 cm (21.00 in)

Depth

17.20 cm (6.75 1n)

Weight

DC Power

Requirement

+12.0 Vdc at 350 mA

Table 1-6
Height
Width

VS10X Mouse Device

VS10X Mouse Physical and Electrical Specifications

Length

3.30 cm (1.30 in)
7.00 cm (2.75 in)
9.50 cm (3.75 in)

Weight

0.50 kg (1.10 1b)

DC Power

+5.0 Vdc £+ 10% at <150 mA

Requirement

Accuracy

7.87 pulses/mm (200 pulses/in)

Rate of

25.4 cm/s (10 in/s) or less

Movement

Figure 1-21

em Introduction

System Description 2
This chapter describes the major functional components of the VAXstation II
subsystems:

1. MicroVAX II processor
2. Graphics subsystem

3. Mass storage subsystem.

MicroVAX Il PROCESSOR

2.1

In the base system, the MicroVAX II processor comprises the KA630 CPU module

and an MS630 memory expansion module.
2.1.1

KA630-A CPU

The KA630-A CPU includes:
e

MicroVAX processor chip, which provides a subset of the VAX instruction set

and data types, as well as full VAX memory management.
VAX data types:

Byte, word, longword, quadword
Character string

Variable-length bit field.

— The remaining VAX data types are supported through software emulation.
VAX instruction set:

— Integer and variable
— Address

— Variable-length bit field

2-1

System Des ription
i,

L
o

ontrol and procedure

all

- Queue
- MOVC 3 IMOVCS.
i,

ing floating point for the KA630-AB
version, are supported through software emulation.
.

dlhe

modules.

e
@

Support for up to 4 ( bytes (27°) of virtual memory.
on
e SLU with extern
selec ible b wud rate. The console SLU is a {~cessed
using our VAX IPRs (internal processor registers).
L

Interval timer, with 10 ms interrupts. Interrupts are enabl e C1 via an IPR.

64-Kbyte boot/diagnostic ROM, which provides:

— A subset of the VAX
-

Power-up diagnostics

- Boot program
e

onsole program

for standard devices.

Q22-Bus map/interface, provides DMA ( =lirect memor
ory.

access) for all local mem-

30-A processes Q2 ) -Bus interrupt request levels BR7 through

Connects to the configuration and display connector cable from the ( PU patch
e,

panel insert.

> SLU connector internal cable from the CPU patch
panel ins ert.

System Description

CAUTION - CPU Slot Position

A KA630-A CPU module must be installed only in backplane slot
1, 2, or 3 (all three contain the MicroVAX local memory interconnect). It must not be installed in slots 4 through 8.

ROM

BYTE

ROM
HIGH

BYTE
MicroVAX 32780
MICROPROCESSOR

Q FLOATING POINT
UNIT

ROW D

[ l

ROW C

Figure 2-1

2.1.1.1

ROW B

i I

ROW A

I-

KA630-A CPU Module

Console Program - The console program, resident in two ROM chips

on the module, receives control whenever the processor halts. For the KA630-A
CPU, a halt means only that processor control has passed to the console program,
not that instruction execution stops. The processor halts as a result of:

System power-up or Restart button pushed

An external halt signal

Halt instruction execution

A system error.

2-3

System Description

At power-up, the system enters one of three power-up modes. The mode is
selected with a switch on the CPU patch panel insert (Paragraph 2.1.2). The con-

sole program then determines console device type and console language.

If the console device supports the MCS (multinational character set), the console
program can be directed to output the console program in any one of 11 languages.

The user language is recorded in battery backed-up RAM (Paragraph 2.1.2), which
retains the language selection when the system is turned off.

If the console device does not support the MCS, there is no language prompt, and
the console program defaults to English. The message “Performing normal system
tests” 1s displayed. A diagnostic test countdown is displayed on the console termi-

nal, in the CPU patch panel insert segmented-LED display, and in LEDs on the
CPU module. These diagnostics test the CPU, memory system, and Q22-Bus interface. The diagrostic test codes and messages are described in Chapter 5.

If a halt has been caused by a condition other than power-up, the console program
will branch directly to service the halt. Depending on the type of halt, the console
program may branch to diagnostics, a restart sequence, a primary bootstrap rou-

tine, or console 1/O mode.

If halts are enabled by the switch on the CPU patch panel insert (Paragraph 2.1.2),
the console program will enter console I/O mode in response to any halt condition,
including system power-up. Console I/O mode allows the user to control the system
through the console terminal by use of a console command language (described in

Appendix A). The console I/O mode prompt is >>>.
2.1.1.2

Primary Bootstrap Program (VMB) - If halts are disabled by the CPU
patch panel switch, and the diagnostic tests are completed successfully, the console

program will try to bootstrap (load and start) an operating system. The console

program first searches for a 64-Kbyte error-free segment of system memory.
Next, it copies VMB (the primary bootstrap program) from the console program

ROM into the segment at base address +512. The console program then branches
to VMB. VMB attempts to bootstrap an operating system from one of the devices
listed in Table 2-1, starting at the top.

System Description

Table 2-1

Console Program Boot Sequence

Priority

Controller

Type — Designation

Q22-Bus CSR Address

RQDX
RC25

MSCP (Disk) - DUAn
- DAAn

17772150 (first)
Floating (additional)

-~ DJAn

KDA

TK50

MSCP (Tape) - MUAn

MRV11

PROM - PRAn

17774500 (first)
Floating (additional)

Program searches for a

valid signature block at 4K
boundaries within the Q22Bus address range.

DEQNA

ETHERNET - XQAn

17774440 (first)
17774460 (additional)

When VMB determines that a controller is present, it searches in order of increasing unit number for a bootable unit with a removable volume. If it finds none, it

will repeat the search for a nonremovable volume.

The system can also be directed to enter VMB through console I/O mode by use
of the boot command, followed by the unit designation and number; for example,
B DUAO.

When the operating system is booted, the processor no longer executes instructions
from the console program ROM. The processor is then in program I/O mode, and
terminal interaction is controlled by the operating system.
2.1.2

CPU Patch Panel Insert

The CPU patch panel insert (Figure 2-2), mounted in the rear I/O distribution

3 switches

1 segmented-LED display

1 external connector

panel, contains:

2 internal connectors

1 BBU (battery backup unit).

Table 2-2 describes the CPU patch panel insert’s switches.

System Description

HALTS ENABLED

/', HALTS DISABLED

HEX

/uxwww

NORMAL OPERATION

- LANGUAGE INQUIRY MODE

__LOOPBACK TEST MODE
CONNECTOR
TERMINAL

OUTSIDE

TO CPU

UNIT

MODULE J? \
® @

P ® @

TO CPU,

Figure 2-2

2.6

CPU Patch Panel Insert

System Description
%

Table 2-2

CPU Patch Panel Insert Switches

Switch

Position

Function

Halt
Enable

Dot

Factory setting; halts are disabled. On power-up or
restart, the system will enter VMB at the completion
of start-up diagnostics.

Circled dot

Halts are enabled. On power-up or restart, the system
will enter console I/O mode at the completion of startup diagnostics.

Power-Up
Mode

Baud
Rate

Arrow

“

Factory setting; Run. If the console terminal supports
MCS, the user will be prompted for language only if
the BBU has failed. Full start-up diagnostics are run.

Face

Language Inquiry. If the console terminal supports

Circled T

Test. ROM programs run wrap-around SLU tests.

MCS, the user will be prompted for language on every
power-up and restart. Full start-up diagnostics are run.

1 through 8 Factory-set to 4800 baud. Sets the baud rate of the
console terminal serial line. The baud rate selection
must match the console terminal’s baud rate.

The segmented-LED displays the number of the currently executing power-up test
or bootstrap procedure. If a failure occurs, the number displayed represents the

FRU that is the most probable cause of the failure. Test numbers are defined in
Chapter 5. The 9-pin external and internal SLU connectors connect the console
terminal cable to the cable from connector J3 on the KA630-A CPU module.

The 20-pin internal configuration and display connector connects the three switches
and the segmented-LED display to the cable from connector J2 on the KA630-A
CPU module.

When system power is off, the BBU (battery backup unit) provides power to the
TOY (time-of-year) clock chip on the KA630-A CPU module. The code for the
user’s language is stored in RAM on the TOY chip, and is lost if the BBU fails.
For more information, refer to the KA630-AA CPU Module User’s Guide

System Description

2.1.3

MS630 Memory Module

The MS630 memory module provides memory expansion for the KA630-A CPU

module. It is available in three versions (Table 2-3), all populated with 256 K

RAM:s.

Table 2-3

MS630 Memory Modules
Part

Ve:mimn

Number

MS630-AA

M7607-AA

1 Mbyte

MS630-BA

Dual

M7608-AA

2 Mbyte

MS630-BB

Quad

M7608-BA

4 Mbyte

Quad

Capacity

Height

One or two MS630 modules can be used in the VAXstation II. The MS630 modules
interface W}‘ifih the KA630-A CPU through the MicroVAX local memory interconBewnt

iect and an “over-the-top” cable. The MicroVAX local memory interconnect is
implementein
d the CD rows of backplane slots 1, 2, and 3. The over-the--top cable

is connected
to J1 on the KA630-A CPU and the corresponding 50-pin connector(s)

on the MS630 module(s). There are no hardware settings on the MS630 module.

CAUTION - MS630 Memory Module Slot Position
An MS630-B module must be installed only in backplane slot 2

or 3. It must not be installed in slots 4 through 8. The MS630-AA
can be installed only in the CD rows of slots 2 and 3.

For an overview of module configuration, see Chapter 3, Paragraph 3.1.2.

2.2
2.2.1

GRAPHICS SUBSYSTEM
VCBO01 Video Controller Module

The VCBO1 controller kit includes the M7602-YA controller module, an I/O distribution panel insert, and a module-to-insert cable.
The VCBO1 is a quad-height, Q22-Bus bit-mapped video option module (Figure 2-3)
that provides workstation capability for Q22-Bus systems.

An on-board, 256-Kbyte, MOS RAM bit-map memory (also called video memory)
residesin the Q22-Bus address space. In the VAXstation II, a subset of the bit-

mapped video memory is displayed on the 48 ¢cm (19 in) VR260 monochrome
monitor. This subset is sometimes called screen memory. The VCBO01 relies on the

CPU to generate all images stored in video memory.

System Description

,wzmg

Juuuy UL

E48

]
Figure 2-3

]

VCBO01 Video Controller Module

The VCBO1 also provides several basic 1/O functions, including:
e C(Cursor controls

e Mouse interface
e Keyboard interface

e Primitives for VT100-style split-screen scrolling.

The VCBO1 contains switches to select:
e

MSA (memory starting address)

e CSR (control and status register) base address
e

Display density.

2-9

System Description

2.2.1.1

Memory Starting Address (MSA) - Switches 1 through 4 of switch-

pack E14 select the starting address for the 256-Kbyte block of MicroVAX

memory where the VCB0O1 module resides. To take advantage
of certain

MicroVAX architectural features when programming bit-map operations,

memory always resides in the topmost 256 Kbytes of the [/O physical

physical

the video

address

space. Therefore, all the MSA switches are set to OFF; that is, address

bits

<21:18> select the 256-Kbyte block starting
at 3C0000 (hexadecimal). (Note that

VCBO1 MSA Selection

Address Bit:

A21

A20

Switch E14:

Switch Setting:*

MSA Address:

A19

[

Table 2-4

this is equivalent to address 3FFC0000 in the [/O physical address space.
See
Paragraph C.2.1.) Refer to Table 2-4.

000 0007

* 0 = off: 1 = on

2.2.1.2 CSR Base Address - In the system I/O page, 32 locations
are allocated
to the VCBO1 module. These locations allow the CPU and VCBO1
to exchange
control and status information through hardware registers on the
VCBO1. As a
group, these registers are called CSRs, but the first register is
specifically named
the CSR. Switches 1 through 7 of switch-pack E48 correspond
to address bits
<12:06> and select the base address for these registers. (Table
2-5) In the VAXstation II system, E48 switches S1:S7 are set to 1E80 (hexadeci
mal). (See Appen-

dix C, Figure C-19.)

Table 2-5

CSR Base Address Select

Address Bit:

Al2

All

A10

A09

Switch E48:

Switch Setting:*

CSR Address:
* 0 =off: 1 = on

1777

A08

AOQ7

A06

/
2

007t

System Description

2.2.1.3 Display Density — The VCB01 module can drive either full-page or halfpage monitors, as selected by switch E68 and switch S8, respectively, of switchpack E48. The VR260 monitor used in the VAXstation II system is a full-page
monitor, and is selected as shown in Table 2-6. Half-page monitors are not
supported.

Table 2-6

VR260 Monitor Display Density Selection

For more detailed information on the VCB01 video controller module see
Appendix C.

2.2.2

VR260 Monitor

The VR260 monitor has three external controls (on/off, contrast, and brightness)
and one indicator (power-on LED). Internal alignment controls and adjustments are
described in Chapter 6.

The monitor has a self-contained power supply and its own ac power cord. It is
connected to the system via the VCBO01 I/O panel insert by the BC18P-10 cable.
The keyboard and data pad are connected at the monitor end of this cable.
2.2.3

LK201 Keyboard

The LK201 keyboard is driven by a microprocessor and contains a set of
microdiagnostics. Communication between the keyboard and the VCB01 module 1s
full-duplex, serial/asynchronous at 4800 baud, and conforms to EIA standard
RS423. The keyboard lead is terminated in a 4-pin modular connector that plugs
into the monitor end of the BC18P-10 video cable.
2.2.4

VS10X Mouse

The hand-held VS10X mouse controls the pointer image (icon) on the monitor

screen. It provides relative pointer position to the VCBO1 in the form of X-coordinate and Y-coordinate pulse outputs. Three push buttons on the mouse perform
software-defined functions. The mouse is connected to the VCBO1 I/O panel insert
with a 3.7 m (12 ft) 10-conductor cable.

System Description

2.3

MASS STORAGE SUBSYSTEM

The base system’s mass storage subsystem can be configured differently from that
shown in Table 1-1. For an overview of ordering information and module configura-

tion see Chapter 3.
2.3.1

RQDX3 Disk Controller

Order: RQDX3-BA

Controller kit includes:
e

RQDX3

M7555 controller module

17-00861-1

50-pin signal cable

For more information, refer to the RQDX3 Controller Module User's Guide

(EK-RQDX3-UG).

The dual-height RQDX3 controller module provides the interface between the

Q22-Bus and the fixed disk and diskette drives. It is an intelligent controller with

on-board microprocessors. Data is transferred using DMA; control and status

munication between the host and controler uses MSCP (mass storage control

com-

protocol).

The RQDX3 can control up to four drives. Each fixed drive counts as one drive:

each RX50 dual diskette drive counts as two.

Figure 2-4 shows the jumper and LED locations for the RQDX3 controller module.

2-12

System Description
W

(COMPONENT SIDE}
J1

RQDX3 CONTROLLER

{M7555)

o1 W03b
Woz
W04 | oo
oo

Wo6e

WOhH

oo | WO

w10

Figure 2-4

(©

W11

RQDX3 Controller Module

2.3.1.1 CSR Address and Interrupt Vector - The CSR address of the first
RQDX3 module is fixed at 17772150 (factory-set). If a second RQDX3 is installed,
its CSR address is floating, and set with jumpers A12:A2. (Table 2-7).
NOTE - MSCP Device CSR Address

The RQDX3 controller module is an MSCP device. The first
MSCP device in a system is assigned a CSR address of
17772150. If more than one MSCP device is installed, the CSR
address of the second device must be set within the floating
range 17760010 through

17763776.

2-13

System Description
3

s
es
dr
Ad
R
CS
le
du
Mo
er
ll
ro
nt
Co
3
DX
RQ
Table 2-7

Jumper:

A12 A1l A10 A09 A08 A07 A06 A05 A04 A03 A02

Jumper Position:*

P«

Cas

o
gl

ule

1776

CSR Address:

Jumper Position:

1776

CSR Address:

Jumper Position:

1776

iy,

CSR Address:

[
&%i‘(‘

Jumper Position:

Pl =

1777

CSR Address:

—_

(factory-set)

* 0 = removed; 1 = installed

The RQDX3 interrupt vector is set under program control. The first RQDX3 interrupt vector is fixed at 154. If a second RQDX3 is installed, its interrupt vector is

floating.

2.3.1.2
Logical Unit Number
- In addition to the CSR address and interrupt
vector, the RQDX3 LUN (logical unit number) jumpers LUNO through LUN7 must

be configured. The jumpers represent a binary-weighted value and can be configured to assign any four LUNs to an RQDX3, starting with any LUN. The RQDX3

module is shipped with no LUN jumpers installed. No LUN jumpers installed

assigns LUNs 0 through 3 to the module, and is the correct configuration for the

first RQDX3 in a system. (Table 2-8) If a second RQDXS3 is installed, jumper LUN2
would normally be installed, assigning LUNs4 through 7 to the second RQDX3;
and so on.

System Description

Table 2-8

RQDX3 Controller Module LUN Jumpers

LUN7 LUN6 LUN5 LUN4 LUN3 LUN2 LUN1 LUNO LUNSs

Jumper:

Value:

2.3.2

RD52 and RD53 Fixed Disk Drives

Order:

RD5nA-AA
Disk kit (n = 2 or 3) includes:

RD5n-A

Disk drive

17-00282-00

20-wire signal distribution cable

17-00286-00

34-wire signal distribution cable

e B e Ji e Y

3:0
8:11

16:19
24:27
28:31

ek O

Position:*

e Y o 8 o B8 e

Jumper

For more information, refer to the RD52-D, -R Fixed Disk Drive Subsystem

Owner’s Manual and the 113-UC/11C23-UE RD52 Upgrade Installation Guide.

The RD52 and RD53 are fixed disk drives with formatted storage capacities of 31
and 71 Mbytes, respectively.

In addition to the cables listed above, a cable from the power supply must be
connected to each RD drive in the system. If an RD5n drive is added to the
system, it must be formatted. The formatting utility is included in the maintenance
section of the MicroVAX II Diagnostics Kit.

2.3.2.1 RD52 Configuration — The RD52 read/write PC board has five pairs of
pins (Figure 2-5) that are used to select the drive. To configure an RD52 as drive
DUO, place a jumper on pin-pair DS3.

2-15

System Description

-l

FRONT OF DRIVE

Ds1 |

DS2

]

bps3

DS4

REAR
OF DRIVE

Figure 2-5

RD52 Fixed Disk Drive

2.3.2.2 RDS53 Configuration - The RD53 read/write PC board has four switches
at its rear edge. With the rear of the drive at the left, the switches are numbered:

To configure an RD53 as drive DUOQ, press switch 3.

2.3.3

RX50 Diskette Drive

Order:

RX50A-AA
Diskette drive kit includes:

RX50-AA

Diskette drive

17-00867-00

34-wire signal distribution cable

System Description

The RX50 drive (Figure 2-6) is a random-access, dual diskette storage device that
uses two single-sided 13.3 cm (5.25 in) diskettes. It has a total formatted capacity
of 818 Kbytes (409 Kbytes per diskette). The diskettes are inserted into slots
behind the drive’s two access doors. A light next to each slot indicates when the
system is reading or writing the diskette in that slot.

One RQDX3 controller supports only one RX50 diskette drive.

Figure 2-6

2.3.4

RX50 Diskette Drive

TK50 Tape Drive Subsystem

Integral TK50 tape drive subsystem:
Order:

TK50-AA
Tape drive and tape cartridge
TQK50-AA

M7546 controller module and internal cable

Stand-alone TK50 tape drive subsystem:

Order: TK50-DA, -DB (DA = 120 V, DB = 240 V line cord)
Tape drive and tape cartridge

M7546 controller module, internal cable, and filter connector

System Description

The TK50 is a streaming tape drive subsystem (Figure 2-7) that uses
magnetic tape cartridges for backup data storage.

Figure 2-7

95-Mbyte

TK50 Tape Drive Subsystem

The M7546 controller module (Figure 2-8) provides the interface between
the
TK50-AA tape drive and the Q22-Bus.

System Description

< |LEDS

UNIT

NUMBER

ADDRESS

JUMPEM%”MW

W OB

VOW**W#%*W%*

Figure 2-8

M7546 Controller Module

2.3.4.1 M7546 Controller Module CSR Address and Interrupt Vector - The
M7546 controller module is a TMSCP (tape mass storage control protocol) device.
The CSR address of the first M7546 module is fixed at 17774500 (factory-set).
If a second TK50 subsystem is installed, the CSR address of the second M7546
module is floating in the range 17760010 through 17763776, and set with jumpers
A12:A2. (Table 2-9)

2-19

System Description

Table 2-9

M7546 Controller Module CSR Address

Address Bit/

Jumper:

A12

Jumper Position:T

(factory-set)
CSR Address:

1777

Jumper Position:

A10

A09

A08

A07

A06

A05

A04

A03

A02*

1776

Jumper Position:

\
0

1776

4
0

CSR Address:

,
CSR Address:

A1l

5
0

0
0

\
0

4
0

I\
4

0
0

[\
0

I\
4

4
1

/
4

* Jumper A2 is closest to the module’s edge.

T 0 = removed; 1 = installed

The interrupt vector is fixed at 260 and is set under program control.
2.3.4.2 M7546 Controller Module Revision Level and Unit Number - Two
sets of DIP switches on the M7546 controller module (Figure 2-8) configure the

hardware revision level and the unit number. The switches in both DIPs have
binary-weighted values.

The hardware revision level DIP switch is factory-set to match the module revision
level stamped on the back of the module. (Table 2-10)

Table 2-10

M7546 Controller Module Revision Level Switches

Revision

Switch*

Level

1 (A)

2 (B)

3 ()

Switch 8 is closest to the module’s edge.

T 0 = open; 1 = closed

System Description

The unit number can be specified with the unit number DIP switches. (Table 2-1 1)
If the MicroVMS operating system is installed, these switches can remain at the
factory setting.

Unit
Number

Switch*
7
8
fi

1
m

M7546 Controller Module Unit Number Switches

cocoo

Table 2-11

* Switch 8 is closest to the module’s edge.
T Factory setting
t 0 = open; 1 = closed

2-21

Options

3.1

GENERAL

This chapter describes the options currently supported by the VAXstation II system. Each option’s section includes configuration set-ups and a description of the
cabinet kit required to install the module. Device reference documentation is also

listed. Option bus loading is listed in Chapter 4.

3.1.1

Ordering Options

Usually, to get all the parts needed to install an option, both a module and a
cabinet kit must be ordered. For example:
e

DEQNA-M M7504 module

CK-DEQNA-KB cabinet kit

3.1.2

Module Configuration

When a device is installed, both its device address, commonly called a CSR (control
and status register) address, and its interrupt vector must be set. The CSR address
and interrupt vector are either fixed or floating.

A fixed address or vector indicates the device has a system memory address
reserved for its CSR address or vector. Devices having fixed CSR addresses and
vectors are usually shipped with their addresses set to the reserved memory

address. If two devices of the same type are installed, the factory set addresses of

the second device must be changed.

A floating CSR address or vector is assigned a memory location within an octal
range. The exact address or vector within the range depends on which devices are

in the system. The ranges are:
e

Floating CSR address: 17760010-17763776

Floating interrupt vector: 00000300-00000777.

3-1

Options

Guidelines in Chapter 4 describe how to determine floating CSR address and interrupt vector settings.

Table 3-1 shows the 22-bit binary equivalent

Table 3-1

for the CSR address W?m40

Emmmwm of a 22-bit CSR Ad

21 20 19 1 8 17
1

|\
As Table 3-1 shows, floating CSR addresses in the range 17760010-17763776 can
-y

beset in bits<11:01>; bits <21:12> are not affected. Fixed CSR addresses above
17763776can be set in bits<12:01>; bits<21:13> are notaffected. Because each

device typically uses a block of addresses, bits <02:00> areusually not changed.
Therefore, WW
al switch settings affect only bits <12:03> to cover the range of

both floating and fixed CSR addresses. (Table 3-2)

Example of Address Bits <12:03>
All

A10

A09

A08

A07

A06

A05

A04

AO03

Switch Setting:*

)ctal Address:t

* 0 =off: 1 = on
T if }%M wmtm = "i 22-bit address = 17771540.

In a similar way, interrupt vectors are typically configured in bits <08:03>.

(Table 3-3)

Example of Vector Bits <08:03>

Octal Address:

0 =Wff& } = Y

T <V02:V00> = 0

3-2

V07

V06

V05

V04

V03

/
ks

Switch Setting:*

Vo8

Vector Bit:

Table 3-3

AlZ

)

Address Bit:

Table 3-2

Options

3.2

DEQNA ETHERNET CONTROLLER

Order:

DEQNA-M
M7504 module

Cabinet kit (type A filter connector and internal cable)
The dual-height DEQNA module connects a Q-Bus system to an Ethernet network.

The Ethernet is an LAN (local-area network) that supports data exchange between
processors through coaxial cable at a data rate of 1.2 Mbytes/s, over a moderate
distance of up to 2.8 km (1.74 mi).
W

The module is configured using three jumpers, W1 through W3. (Figure 3-1)
Jumpers W2 and W3 are factory-set and do not need to be changed.

TW?2

Qmwmmmmw

Figure 3-1
2.1
w

DEQNA Ethernet Controller Module

CSR Address and interrupt Vector

Jumper W1 determines the CSR address assignment. The DEQNA CSR addresses
i

are fixed as follows. (Table 3-4)

3-3

Options

Table 3-4

DEQNA CSR Address Settings

DEQNA

CSR Address

17774440

If two DEQNA modules are to be installed, move jumper W1 of the second DEQNA
ontothe left and center pins. (Figure 3-1)
P

Software writes the interrupt vector into a read/write register. No hardware con-

figurationis required. The interrupt vectors are listed in Table 3-5. Figure 3-2
shows the internal cabling for the

Table 3-5
DEQNA
)

3-4

) DEQNA.
]

DEQNA Interrupt Vectors
Interrupt Vector

Floating

Options

Figure 3-2

DEQNA Module Internal Cabling

Options

3.3

DZQ11 ASYNCHRONOUS MULTIPLEXER

Order:

DZQ11-M
M3106 module

Cabinet kit (type B filter connector and internal cable)
The dual-height DZQ11 module (Figure 3-3) connects the Q22-Bus to as many as
four asynchronous, serial lines. It conforms to the RS-232-C and RS423-A interface
standards. The DZQ11 supports dial-up (auto-answer) operation with full-duplex

modems.

3.3.1

CSR Address and Interrupt Vector

The floating CSR address and floating interrupt vector are set with two DIP switch
sets, E28 and E13. (Figure 3-3) Tables 3-6 and 3-7 show the factory and common

settings. E13 switch 7 is not used. For normal operation, E13 switch 8 must be
ON, and switches 9 and 10 must be OFF. Figure 3-4 shows the module’s internal

cabling.

VECTOR

SWITCH PACK

]

E13

ADDRESS

"lE28

Figure 3-3

DZQ11 Module

Options

Table 3-6

DZQ11 Module CSR Address

Address Bit:

Switch E28:
Switch Setting:*

(factory-set)
CSR Address:

1776

Switch Setting:

CSR Address:

1776

* (0 = open; 1 = closed
T <A02:A00> = 0

Table 3-7

DZQ11 Module Interrupt Vector

Vector Bit:

Vo8

V07

V06

V05

Vo4

VO3

Switch E13:

Switch Setting:*
(factory-set)

0
\

Switch Setting:

Vector Address:

Vector Address:
* () = open; 1 = closed
T <V02:V00> = 0

3.7

Options

Figure 3-4

3.4

DZQ11 Module Internal Cabling

GRAPHICS TABLET

The graphics tablet (Figure 3-5) consists of a digitizing tablet, 4-button puck or 2-

button stylus, and a 5-foot power/signal cable. The puck and stylus

are interchange-

able. The tablet may be used instead of the mouse as the pointing device for

menu selection, graphics entry, and cursor control.

Options

RUBBER
g” !:‘ E,"w‘

Figure 3-5

%M\A

)
Mok

b — ,w

Graphics Tablet Components

The digitizing tablet is an input device that sends X-Y coordinates to the
VAXstation II system to accurately indicate the position of the stylus or cursor on
the tablet’s surface. The tablet has a resolution of 0.005 inches (200 counts per
inch). The tablet has an active area of 279 mm X 279 mm (11 in X 11 in). The
tablet’s physical specifications are given in Table 3-8.

Table 3-8

Graphics Tablet Physical and Electrical Specifications

Height
Width
Length
Weight

20 mm (0.80 in)
412 mm (16.20 in)
406 mm (16.0 1)
3.2 kg (7.0 1bs)

DC power

300 mA at +12 V +0.5% regulation

Active area

279 mm X 279 mm (11 in X 11 in)

Proximity
(nominal)
3.4.1

12.7 mm (0.5 in) puck
6.3 mm (0.25 in) stylus

Baud Rate Selection

Tablet communications with the host are via an asynchronous, full-duplex, serial
interface at 4800 baud (+2%) and 9600 baud (+2%).

Options

The default baud rate of the tablet is 4800 bits/s. The baud rate is changed to

9600 bits/s by sending the ASCII character “B” (42 hexadecimal) to the tablet.

The tablet is switched back to the default baud rate by sending a “BREAK”’ (minimum of two character times), or by requesting a self-test of the tablet.

Baud rate selection is controlled by software, with the appropriate commands being
issued by the software driver. Baud rate is not user-selectable. A modification to
the software driver is necessary.

- 3.4.2

Graphics Tablet Connector Pin Assignments

The tablet uses a 7-pin micro-DIN-type connector. The pins are shown in Figure

3-6. Note that the top of the connector is three pins wide and the bottom is two

pins wide. The numbers and names of these pins are listed in Table 3-9.

Figure 3-6

Graphics Tablet Pin Assignments

Name (Function)

=3
U1 o
WD e

Table 3-9

Graphics Tablet Connector Pins

GND (Signal ground and return for power)

hell

3-10

TXD (Serial out from tablet)
RXD (Serial in to tablet)
Not used

Not used

+12 'V
Device present — connected to pin 1

Protective ground

Configuration
4.1

CONFIGURATION RULES

You must consider the following when configuring a VAXstation II system.

Bus loading

Backplane and I/0 distribution panel expansion space

Physical priority

Power requirements

CSR addresses and interrupt vectors

4.1.1

Physical Priority

System performance is affected by the backplane slot positions of the system
modules. Observe the following rules when installing modules.
e KA630-An CPU is installed in slot 1.

e MS630-AA memory modules are installed in the CD position of slots 2 and 3.
M9047 grant continuity cards are required in unoccupied AB positions of slots 2
and 3.

If any other dual-height modules are installed in slots 2 or 3, they must occupy
the AB (that 1s, Q22-Bus) half of the slot. M9047 grant continuity cards are not
required.
e MS630-Bn memory modules are installed in slots 2 and 3.
NOTE

Reserve Slots 2 and 3
When slots 2 and 3 are not occupied, M9047 grant continuity

cards must be installed in the AB position, and the slots
reserved for future memory expansion.

4-1

Configuration

¢ Dual-height modules can be installedin either the AB or CD position of slots 4
through 8. If only one dual-height moduleis installedin any of these slots, the

configuration may require an M19047 grant cardin the empty half of the slot.

Modules should be installedin the following sequence, with no intervening empty

@%mm W“‘m relative priority of the modulesis based on their preferred interrupt and

%usé

DMA priority.

KA630-An CPU
Memory expansion modules (two maximum):

Q22-Bus memory modules:

JPV11 (M8020) synchronous communication module - no silos

DRV11]J (M8049) general purpose I/0 ports
LPV11 (M8027) line printer interface
DLVJ1 (M8043A) asynchronous communication module - no silos

Asynchronous communication modules - with silos:

DZV11 (M7957)
9. Synchronous communication modules - DMA:
DMV11-N (M8064)

DEQNA (M7504) Ethernet communications module
. DHV11 (M3104) asynchronous communications module - with silos/DMA

VCBO01 (M7602) bit map video controller
13. TQK50 (M7546) streaming tape controller (Smart DMA)
14. Mass Storage Controller (Smart DMA):

4-2

Configuration

4.1.2

Expansion Space

All twelve backplane slots accept Q22-Bus modules. Figures 4-2 and 4-4 show the
occupied and available slots in typical configurations.
ADD THESE COLUMNS
%

REGULATOR A

SLOT

CURRENT

MODULE | 45 vDC

(AMPS)

REGULATOR B

POWER

| +12 vDC | (WATTS)

CURRENT

1 AB

(AMPS)

)

(2% 3) (1 X4)

| POWER

+12 VDC | (WATTS)

cD
2

co|

4 AB
CD
|

5 AB
cD

6 AB
CcD
7

8 AB
cD

9 AB

e
e

10 AB
11

CD
RS

13 AB | SIGNAL

cD | DIST.

MASS STORAGE

SHELF | DEVICE

2.66

7 A

230 W

TOTAL THESE

COLUMNS:
MUST NOT

EXCEED:

36 A

Figure 4-1

36 A

230 W

Configuration Worksheet
4-3

Configuration

BACKPLANE

SLOT

ROW

A
1

KAG30-AB (QUAD) CPU

MSB047 GRANT CARD

MS630-AA MEMORY

M93047 GRANT CARD

EMPTY

DEONA NET (DUAL)

EMPTY

VCBO1 (QUAD) BITMAP VIDEO CONTROLLER

RODX3 CONTROLLER |

TQK50 CONTROLLER

Figure 4-2

Base System

Four type A (1 X 4) and six type B (2 X 3) cutouts are available on the back panel
for mounting I/O panel inserts. The bottom two type B cutouts can be converted to
provide three additional type A cutouts. Table 4-1 lists the type of inserts used for

each module. The configuration worksheet (Figure 4-1) is used to determine the
"

number of inserts that can be installed.

4-4

Configuration

Table 4-1

Power Requirements, Bus Loads, I/0 Inserts

Option

Module

Current

(amps)

+5V +12V

Power

Bus Loads

1/0 Inserts
A=1X4

(watts)

B=2X3

2.7

M7606

5.9

M7607

0.14

2.7

0.0

25.00

0.0

1.8

0.0

DPV11-DP
M8049

LPV11-XP

0.8

0.25

DZV11-DP

M7957

1.2
1.5

DZQ11

DMV11-BP

M8053-MA

0.4
0.4

2.0

21.56

M8053-MA

1.0

21.8
2.0
2.9

0.10

RLV12-AP
M7546

26.2

2.7
2.0

0.0

M7740
2.0

0.1

25.9

RX50-AA
1.0

1.0

RD52-A

2.5

TK50-AA

Configuration

4.1.3

Power Requirements

System module and mass storage device current and power requirements must
not exceed the following.

® Current:

+ 5Vdc=36A
+12 Vdec=

e Power:

230 W

CAUTION - Maximum Current
Maximum +5 Vdc and +12 Vdc current cannot be drawn at the
same time. The 230 W power limit will be exceeded.

Table 4-1 lists the module current requirements. The configuration worksheet
(Figure 4-1) is used to determine the current and power used.
4.1.4

Bus Loads

The number of backplane bus loads available are:
e 38 ac
e 20 dc

These limits will not be exceeded using standard Q22-Bus options. If a nonstandard module is installed, Table 4-1 includes bus loads for each option. In such
a case, the total loads of installed modules should be checked to be sure the total
does not exceed these limits.

Table 4-1 lists the ac and dc bus loads for each module. The configuration worksheet (Figure 4-D) 1s used to determine the number of bus loads used.

4-6

Configuration

4.1.5

CSR Addresses and Interrupt Vectors

Modules must be set to the correct CSR address and interrupt vector (Table 4-2).
Observe the following rules when using Table 4-2.
ot

Check off all the devices that will be installed in the system.

. An F in the vector column means the device has a floating vector. Assign a
vector to each option installed, starting at octal 300 and continuing as follows:
DLV]J1
DRV11

(increment of 40 to next device)
(increments of 10 for subsequent devices)

DPV11

2nd MSCP
2nd TQKS50
DHV11

ond DEQNA

(first 1s fixed at 154)
(first 1s fixed at 260)

(first is fixed at 120)

For example, from the list of devices above, systems containing the following

modules would be assigned as shown:

Example 2

Example 1

DZV11

340

2nd MSCP

310

2nd MSCP

360

2nd DEQNA

330

The floating vector of a 2nd MSCP or TQKS50 is program set, not configured using
jumpers or switches. If there is a second MSCP or TQKS50 in your system, you
must still determine what the vector is, because it will determine the vector of
devices after it.

3. An F in the CSR address column means the device has a floating CSR address.
Use Table 4-3 to determine the correct addresses for these devices.
4. If a module’s vector and CSR address are both floating, an additional module of
the same type will also have a floating vector and floating CSR address.

Configuration

Table 4-2

Address/Vector Worksheet

Option

Module

No.

System

Vector

CSR Address(N=177)

M760x
DPV11

F
N64140

LPV11

N77514
N76510

M7957
DZQ11

DHVI11

M7504

120

N74440

DMV11
DMV11-CP
N74500
154

N72150

The DLV]1 vector can be configured only at 300, 340, 400, 440 etc. If the first
avatlable floating vector 1s 310, 320, or 330, the DLV]J1 should be set to 340 and the
next device set to 400.

4-8

Table 4-3

Floating CSR Addresses

Go down through the columns in the table to find the column that matches your
confi

Any device added to or removed from the list will not affect the addresses of
devices above it.

Substitute the numbers below for the ;nnn in 17760nn

Device

DZQ/V 3

DPV11

*120

*270

DMV11

120

*270

*310

3
*330

320

2nd MSCP

334

*354

2nd TKS0

*404

*444

Y444

DHVI1 1

440

500

340

360

374

*414

*504

504

540

340

*444
500

* = Device may or may not be installed

Example 1:

Example 2:
1 DHV11 only: 17760440
(derived from the first column)

DZQ11:

17760100

DPV11:
17760310
DHV11:
17760500
(derived from the fifth column)

4-9

Configuration

4.2

FLOATING CSR ADDRESSES

Table 4-3 lists the floating CSR addresses for common combinations of devices
that will require configuration. These settings are valid only for the devices listed
and may change if other devices with floating CSR addresses are installed.
4.3

CONFIGURATION EXAMPLES

Many BA123-A enclosure configurations are possible. Figures 4-2 and 4-4 show
possible module utilizations for MicroVAX II systems.

NOTE
Before configuring a system, refer to Figure 1-11 to review the
bus grant continuity.
4.3.1

Module Utilizations

Figure 4-2 shows the backplane setup for a base system, which can be expanded at
a later time.

Figure 4-3 shows a completed configuration worksheet for the base system
configuration.

Figure 4-4 shows the expandability of a MicroVAX Il system in the BA123-A

o 9 Mbytes of main memory

e 2 RD-53 fixed-disk drives, providing 142 Mbytes of mass-storage
e a DEQNA module to connect to Ethernet

e a2 DPV11 module to connect to a modem
e an LPV11 module for an LP25 printer

e a TK50-AA tape drive for system loading and backup.
Figure 4-5 shows a completed configuration worksheet for the expanded system.

Configuration

ADD THESE COLUMNS
iP5,

REGULATOR B

REGULATOR A

SLOT

CURRENT
+5VvDC
|

MODULE}

AB | KA630

(AMPS)
+12VDC

(2 X 3)(1X4)

M9047

CD |MSB30AA
3 AB|

M9047
|

co|

4 AB Wfi@fiwm':"

5 AB

6 AB | RQDX3
CD | TOKS50

8 AB

CcD
9 AB
CD
10 AB
cD
1

12 AB

co|

3 AB | SIGNAL
cp | pisT.

S HELF | DEVICE
5*

RX50
TK50

3
1

RDB3

TOTAL THESE

COLUMNS:

13.92

4.34

119.856

10.78

3.06

90.7

36 A

7 A

230 W

36 A

230W

MUST NOT
EXCEED:

*RECOMMENDED FOUR DRIVES MAXIMUM — TWO IN SHELVES 1T AND 2, TWO IN 3, 4, OR 5.
**IF MORE THAN FOUR 1 X 4 1/O PANELS ARE REQUIRED, AN ADAPTER TEMPLATE MAY BE USED.

Figure 4-3

/O INSERTS

6.2

co|

{

Completed Configuration Worksheet

Configuration

BACKPLANE | BACKPLANE
SLOT

ROW

KAB30-AA (QUAD) CPU, 1 MBYTE MEM. + FPP

MS630-BB (QUAD) 4 MBYTE MEMORY

MS630-BB (QUAD 4 MBYTE MEMORY

DPV11 COM (DUAL)

EMPTY

LPV11 PRT (DUAL)

DEQNA NET (DUAL)

VCBO1 (QUAD) BITMAP VIDEO CONTROLLER

M9047 GRANT CARD

EMPTY

TQK50 CONT. (DUAL)
RQDX3 CONTROLLER

9
10

Figure 4-4

4-12

Advanced System

onfiguration

ADD THESE COLUMNS
i,
-\

REGULATORB

REGULATOR A
CURRENT

CURRENT

(AMPS)

/0 INSERTS

(AMPS)

| POWER

POWER

|(2X3) (1X4)

174

1.8

195.75

11.38

2.86

913

1.3

36 A

230 W

36 A

230 W

2 AB | MS630
cD | BB
3 AB | MSB30
4 AB | ...,

cD WiliWWH

5 AB | LPV11
CD 1 DEQNA
6 AB |

Lrpn.

7 AB | MB047T
CD | TOK50
8 AB

cD | RQDX3 |

9 AB

10 AB
11

13 AB | SIGNAL
CcD | DIST.
MASS STORAGE

TK50

SHELF | DEVICE

TOTAL THESE

COLUMNS:

MUST NOT

EXCEED:

4**

*RECOMMENDED FOUR DRIVES MAXIMUM — TWO IN SHELVES 1 AND 2, TWO IN 3, 4, OR 5.
“*IF MORE THAN FOUR 1 X 4 1/O PANELS ARE REQUIRED, AN ADAPTER TEMPLATE MAY BE USED.

Figure 4-5

Completed Configuration Worksheet

(Advanced System)

4-13

Diagnostics

This chapter presents an overview of MicroVAX II diagnostic and maintenance

tools, and also provides fault isolation guidelines.
KA630 SELF-TESTS

5.1

The MicroVAX II boot and diagnostic ROM tests the basic functions of the KA630
CPU module. Testing can occur in either power-up mode or console I/O mode.
5.1.1

Power-up Mode

In power-up mode, the ROM-based diagnostics and boot programs test the KA630
CPU module’s ability to load and run an operating system, the MicroVAX Maintenance System, or other diagnostic software.

Table 5-1 describes each test in the ROM-based diagnostic and lists its hexadecimal
code. While each test is being run, the hex (hexadecimal) value is displayed:
e In the segmented LED on the CPU patch panel insert

e In four red LEDs (in binary form) on the KA630-An CPU module
(Figure 5-1), and

e For values less than 9, on the console terminal.
GREEN

DC OK LED

RED LEDS

VALUE ON

VALUE OFF

Figure 5-1

CPU Module LEDs

5-1

Diagnostics

h“éfia

The green DC OK LED indicates the same conditions as the front control panel DC

OK indicator (Table 1-3).

The sum of lighted red LEDsis a hexadecimal value that

indicates the same condition as a value mm in Table
5-1.

If a test fails, the test sequence halts, and the code of the failed test re
displayed. Table 5-1 also lists the field replaceable unit(s), or FRU(s), that most
likely caused the test to fail.

Table 5-1

Diagnostic LED Status and Error Messages

Hex

TM%T NAME

Value

MostLikely Failed @“WWW

- CONSOLE TERMINAIL MESS

KA630-An module (does not recognize DC OK assertion)
Power supply (negating DC OK on bus)

Q22-Bus device (negating DC OK on bus)

Backplane (DC OK shorted to another signal)

KA630-An module (does not recognize P OK assertion)

Power supply (negating P OK on bus)

Q22-Bus device (negating P OK on bus)

Backplane (P OK shorted to another signal)

KA630-An module

MS630 module(s)

KA630-An/MS630 interconnect cable (short- or open-circuited)

READ KA630-An IPCR REGISTER (accesses Q22-Bus)
1.

KA630-An module

Q22-Bus device (preventing the CPU from acquiring the bus)

Backplane (preventing the CPU from acquiring the bus)

Diagnostics
#

Table 5-1

Diagnostic LED Status and Error Messages

(Cont.)

Hex
Value

Most Likely Failed FRU(s)

TESTING VCBO1 VIDEO CONSOLE DISPLAY (if present)
1.

Keyboard for VCBO1 (defective or not connected)

Video display for VCBO1 (defective or not connected)
NOTE: A failed monitor is indicated by no video display. The system

does not detect a failed monitor. If the keyboard is connected through

the BC18P cable, the system will boot.

VCBO1 module
KA630-An module (cannot read or write Q22-Bus; may be shorting
Q22-Bus)

Q22-Bus device (preventing the CPU from acquiring the bus)

6.
7.

Backplane (preventing the CPU from acquiring the bus)
VCBO1 I/O distribution panel insert

KA630-An module (If console does not respond within six seconds,

CPU will proceed to 7.)
LANGUAGE INQUIRY OR CPU HALTED
When the LED is stopped at 8, the system is either:
a)

preparing to ask the user to select the language to be used,

b)
¢)

actually indicating a failure.

informing the user that the CPU is halted, or

If the system is not indicating a halt, but waiting for a language to be
entered, within 2 to 6 minutes (depending on console terminal’s baud rate)
a time-out occurs and testing continues.

Before the console terminal displays the message for test 8, it should

display a header message reporting the CPU version number and other
system information. If the LED on the CPU patch panel displays 8 (or a
lower test number) and the console terminal does not display a header
message, suspect:

KA630-An module (probably the console interface)

2.
3.

Console cables (defective or not connected)
Console baud rate (mismatched)

5-3

Diagnostics

Table 5-1

Diagnostic LED Status and Error Messages

(Cont.)

Hex

Value

Most Likely Failed FRU(s)
NOTE: There is no baud rate setting when the graphics subsystem is
used as the console terminal. This test applies to base-MicroVAX II
systems, or to printers connected to the CPU SLU port.

Console terminal (defective or power off)

Console I/O distribution panel insert

KA630-An module (RAM memory failure)

MS630 module

Backplane (CD interconnect short- or open-circuited)

KA630-An/MS630 interconnect cable (short- or open-circuited)

MS630 module

Backplane (CD interconnect short- or open-circuited)

KA630-An/MS630 interconnect cable (short- or open-circuited)

251

KA630-An module

Q22-Bus device (preventing the CPU from acquiring the bus)

Backplane (preventing the CPU from acquiring the bus)

C
1

KA630-An module

Q22-Bus device (incorrectly requesting interrupt)

Backplane (Q22-Bus BR line short-circuited)

NOTE: Before continuing here, try the procedures in the Troubleshooting
section of the VA Xstation II Owner’s Manual, BA23 Enclosure.

Before assuming drives or controllers are defective, check their signal and
power cables. After checking the cables, check the devices’ power-up

LEDs. (See Paragraph 5.2.)

5-4

Table 5-1

Hex
Value

Diagnostic LED Status and Error Messages (Cont.)

TEST NAME — CONSOLE TERMINAL MESSAGE/
Most Likely Failed FRU(s)

1.
2.

RQDX controller module, RD5n fixed disk drive, RX50 diskette drive,
or interconnect cable (defective or not properly connected)
TQK50 controller module, TK50 tape drive, or interconnect cable
(defective or not properly connected)
DEQNA module

KA630-An module

1.
2.
3.
4.

5.1.2

Q22-Bus bootstrap device
Signal cable to bootstrap device (defective or not connected)
Power cable to bootstrap device (defective or not connected)
KA630-An module

Console Mode

In console I/O mode, the TEST command is used to select any of the ROM tests;
the EXAMINE command displays the contents of registers and memory; and the
BOOT command, with an appropriate qualifier, selects the boot device. Console
commands are described in more detail in Appendix A.

5.1.2.1 Console Terminal Error Messages — The following is an example of the
console terminal error message format.
KAB30.XX
Performing normal system tests.

? <subtest> <pl1> <p2> <p3>
Failure.

Normal operation not possible.

5-5

Diagnostics

Where:
KAB30.XX

Identifies the processor and the console program ROM version number.
Performing normal system tests.

The system is performing the tests programmed in the ROM.

The countdown sequence, showing the system is progressing through its tests. The
numbers displayed indicate the same conditions as the numbers displayed in the
segmented LED on the CPU patch panel insert. (Table 5-1)

A diagnostic message including the question mark, a subtest code number, and up
to three parameters: indicates the countdown sequence has been interrupted.
Parameters are described in Appendix B.

Failure,

Normal operation not possible.

The test failed and the console program is not executing.

5.2

DEVICE SELF-TESTS

Several VAXstation II devices and options also have the on-board capability to
perform power-up self-tests, and report the results in on-board LEDs. Figures 5-2
through 5-4 show these LEDs, and Tables 5-2 through 5-4 describe what they

indicate.

5-6

Diagnostics
¥

]

5.2.1

DEQNA Ethernet Controller Module
3

Figure 5-2

Table 5-2

DEQNA Module LEDs

LED

Description/

Most Likely Failed FRU(s)

Performing DEQNA station address PROM test.
1.

OFF

KA630 module

Q22-Bus device

Backplane

Performing DEQNA internal loopback test.

1.
ON

OFF

DEQNA module

Performing DEQNA external loopback test.

DEQNA module

Cabling (short- or open-circuited, or not connected)

Fuse in I/O distribution panel insert

DEQNA passed all power-up tests.

Diagnostics

5.2.2

RQDX3 Mass Storage Controller Module

RODX3 CONTROLLER

(M75565)

2;“'““* W23
d
LED

'
S

w02

Wo4

W01

W03

W06

w12
w13
[0 o] [o o]
e

wo8s
Wi

o
W17 1o

Figure 5-3

ol W14
o

Ol
o

Wib

W10

(O]

S B
o0

wao7

o0
L

W11

RQDX3 Module LED Location

The RQDX3 also tests itself when it i1s powered up and initialized by the host
system. There is a single LED on the RQDX3 module. (Figure 5-3) At the
beginning of testing the LED is lit. When testing is completed (after about 7 to 10
seconds) the LED is extinguished. If the test detects an error, the LED will remain
lit after this initialization period.

Diagnostics

5.2.3

TQK50 Tape Controller Module
2

A N
Figure 5-4

Table 5-3

TQK50 Module LEDs

TQK50 Module LEDs
Description/

LED

Most Likely Failed FRU(s)

OFF

Module/drive interaction test fails.

then

OFF

TQK50 module

TK50 drive

Interconnect cable

Module failed power-up test.
1.

OFF

TQK50 module

Module power-up test and module/drive interaction test
both failed.

TQK50 module

TK50 drive

Interconnect cable

Module and drive working correctly.

then

OFF

5.3

MicroVAX MAINTENANCE SYSTEM (MMS)

The MicroVAX Maintenance System (MMS) is a combination diagnostic/
maintenance operating system. The system is available in: 1) the verification version, provided with each MicroVAX II system, and 2) the maintenance version,
shipped with the MicroVAX Il Maintenance kit. The verification version is
described here. (The maintenance version is described in the MicroVAX II System
Maintenance Guide.) The verification version provides configuration verification
and system-level testing.

5.9

Diagnostics

MMS is menu-driven, and can be loaded from tape or diskette into any MicroVAX
[T system. Figure 5-5 shows the menu tree of MMS functions.
MAIN MENU
1.

TEST THE SYSTEM

DISPLAY UTILITIES MENU

EXIT MICROVAX MAINTENANCE SYSTEM

PERFORMS SYSTEM-

IS FOUND

SHOWS SYSTEM

GIVES MESSAGE:

TO USE THIS FUNCTION, YOU MUST PURCHASE THE MICROVAX

MAINTENANCE KIT WHICH INCLUDES THE APPROPRIATE LICENSE

GIVES MESSAGE:

TO USE THIS FUNCTION, YOU MUST PURCHASE THE MICROVAX

MAINTENANCE KIT WHICH INCLUDES THE APPROPRIATE LICENSE

EXITS MICROVAX

MAINTENANCE SYSTEM

Figure 5-5

5.3.1

MicroVAX Maintenance System Menu Tree

Configuration Verification

MMS verifies the system installation by determining which devices are installed,
and then displaying the system configuration it recognizes. An installation problem
appears when the terminal display does not include a device known to be installed.

5.3.2

System Tests

MMS runs system-level functional and exerciser tests. Any user can run systemlevel tests on all recognized devices, at any time, without loss of data.

Diagnostics

5.4

TROUBLESHOOTING
NOTE
Before going on, read the Problem/Solution section of the

VAXstation Il Owner’s Manual, BA123 Enclosure.
The primary VAXstation Il troubleshooting tools are:
e Front panel indicators

e Power-up self-tests

VAXstation II Technical Manual, BA123 Enclosure

o VAXstation II Owner’'s Manual, BA123 Enclosure

VAXstation Maintenance Guide
MicroVAX Maintenance System

Most VAXstation II system problems will be:

e Unknown system-level problems (system fails to boot)
e Suspected device-level problems (system can boot; problem may be intermittent). Problems in the:

- Memory

~ Graphics subsystem
Mass storage devices

— Communications devices.

The following are suggested troubleshooting methods for each type of problem.
5.4.1

Unknown System-Level Problems

Follow these steps to diagnose unknown system-level problems:
1. Read the message on the console terminal.

— If the test number is 7, 6, 5, 4, or 3, use Table 5-1 to isolate the failed FRU.
— If the test number is 2, 1, or 0, use Table 5-1 and the module LEDs to
isolate the failed FRU.

5-11

Diagnostics

2. If the terminal screen is blank, check the segmented LED on the CPU patch
panel insert.

— The LED has run through power-up tests. The panel insert could be in loopback mode, bypassing the console terminal.
— The LED value is not F. The console terminal cable or the console-to-patchpanel cable is faulty or disconnected.

- The LED value is F. The CPU, the patch panel insert, or the
CPU-to-patch-panel-insert cable is faulty or disconnected.
3. If the segmented LED is blank, check the front panel indications, and continue
.

as shown in Figure 5-6.
Figure 5-6 shows the general procedure for troubleshooting the system when
either the operating system or the MMS fails to boot.

Diagnostics

TRY TO RESOLVE

PROBLEM USING

i
DISPLAY

15 TN

DISPLAY

~
"

ARE
KAB30-A

3 OR

MODULE LEDs OR

CPU
DISTRIBUTION
«

[INSERT

CHECK LED
INDICAmm
b ON AALL
022-BUS StDEVICES

OF THIS MANUAL

REFER TOTABLE
5
OF THIS M%Mhfi%

REFER TO TABLES

5-1

}
ISOLATE FRU AND

THROUGH 5-4

AND APPENDIX B

OF THIS MANUAL

CHAPTER 6

REPLACE USING
INSTRUCTIONS IN

ISOLATE FRU AND

REPLACE USING

NSTRUCTIONS
HAPTER 6
5

" SYSTEM DC OK
LED UIT

MODULE TO

DISTRIBUTION PANEL|

;
REPLACE USING

| SUSPECT POWER
| SUPPLY AND/OR

!
REPLACE USING
INSTRUCTIONS IN

CHAPTER 6

Figure 5-6

CHAPTER 6

Boot Failure Troubleshooting Flowchart

Diagnostics

5.4.2

Device-Specific Problems
;i

Follow these steps to diagnose a device-specific problem:
i

1. Boot the MicroVAX Maintenance System.

2. Select the configuration procedure from the Main Menu. The screen display
should list all the devices known to be installed. If an installed device does not
appear in the display:

ifi e M

- informatio

po|

~ The device is faulty or disconnected. See Chapter 6 for removal and replacen.

The device address is wrong. See Chapter 6 for removal and replacement

information, and Chapter 4 for configuration information.

3. Select the system-level tests from the Main Menu. Within 6 minutes the test
results should be displayed. When testing has started, one of the following
should occur.

— The test locates a failed FRU. See Chapter 6 for removal and replacement
procedures.

-~ The test fails, but a failed FRU is not identified. See the VA Xstation Maintenance Guade.

— The test passes, but a system problem exists. Check the device LEDs.

Figure 5-7 shows the general troubleshooting procedure for device-specific
problems.

Diagnostics

TROUBLESHOOTING

LOAD MICROVAX

CONFIGURATION
UTiumy

MMS

DEVICE 1S BROKEN,
NOT PROPERLY

START SYSTEM

TESTING
ISOLATE AN
FRU

;
MICROVAX SYSTEM

MICROVAX SYSTEM

Figure 5-7
5.4.3

Device-Specific Failure Troubleshooting Flowchart

VR260 Monitor Troubleshooting Procedures

Table 5-5 lists some symptoms of common problems with the VR260 monitor.
When troubleshooting, follow the suggested corrective actions in the order listed.

Diagnostics

Table 5-4

VR260 Monitor Failure Indications

Symptom

Corrective Action

No LED or screen display

Check that the power switch is on.
Check the power cord connection.

Check the 120/240 Vac setting.
Remove the rear bulkhead assembly and check
the connection to the ac transformer assembly.

Check the deflection board connections.
Replace the deflection board.
Flashing LED

Check the deflection board connections,
including the chassis ground.
Make sure the high voltage anode lead has a
good connection with the CRT.

Replace the deflection board.

Compressed raster or no video
display

Check the VAXstation II diagnostic display.
If other than a pass indication (.), fix the
VAXstation II before proceeding with
adjustment/repair of the VR260 monitor.

Ensure proper VAXstation-to-VR260 monitor
cabling.

Remove the rear bulkhead assembly and check
the cable connections to the video amplification

board.

Remove the video amplification board and
check the CRT pin connections.

Replace the video amplification board.
Raster present but no video
display

Check for a pass indication (.) on the
VAXSstation,

Ensure good CRT connections.

Replace the video amplification board.

Symptom

VR260 Monitor Failure Indications (Cont.)
Corrective Action

LED off but video display 1s

present

Remove the LED bezel assembly and check for
good connection.

Replace the LED.

Ensure proper cable connections from the
deflection board to the LED bezel assembly.

Table 5-4

FRU Removal and Replacement 6
This chapter describes the removal and replacement procedures for VAXstation II
FRUs. Only qualified personnel should perform these procedures. Table 6-1 lists
the FRUs and their part numbers. Figure 6-1 shows an exploded view of the

BA123 FRUs.
NOTE

Unless otherwise specified, replace FRUs by reversing the order
of the removal procedures.

6-1

FRU Removal and Replacement

‘m{: x&fi
e

& 1

Fe?

gure

ap?
g

e s

owm owe

i
sl

£%

6-2

FRU Removal and Replacement

Table 6-1

BA123-A FRUs

Part Number

Description

17-00859-01

switch, ac power to power supply, and cable from switch to

17-00860-01

cable, backplane to CPU console board

54-16596-01

CPU console board

17-00862-01

cable, signal dist. board to 4 RD consoles

17-00282-01

cable, 20 conductor, RD drive

power supply

cable, 40 conductor, RD drive
54-16244-02

RD52 console

17-00861-01

cable, 50 conductor, RQDX to signal dist. board

17-00867-01

cable, signal dist. board to RX50

70-22300-01

cable,

54-16674-01

signal distribution board (M9058)

TK50-A/TQK50 interconnect

12-23395-01

12-22271-01

fan, 4.5 in (11.4 cm) (mass storage)

17-00942-01

switch, door interlock, and cable from switch to temperature

54-16665-01

temperature sensor board

17-00863-01

cable, power supply to card cage fan and temperature sensor

17-00864-01

cable, power supply to mass storage fan

17-00865-01

cable, regulator “A” to backplane

17-00865-01

cable, regulator “B” to backplane

17-00870-01

cable, regulator “A” to 2 drives via 2 plugs

17-00911-01

cable, regulator “B” to 3 drives via 3 plugs

30-23616-01

power supply

54-17507-01

Q22-Bus backplane, 13 slot, quad height

sensor board

FRU Removal and Replacement

6.1

EXTERIOR PANEL REMOVAL

You must remove the exterior panels before beginning most removal

and replace-

ment procedures. Refer to the following two sequences in the procedure

s that

follow.

6.1.1

Right Side Panei Removal

1. Turn the system off and unplug the ac power cord from the wall socket.

2. Open the rear door.

3. Loosen the captive screw that connects the right side panel to the rear
of
enclosure frame. (Figure 6-2)

Figure 6-2

Unhooking the Right Side Panel

the

FRU Removal and Replacement

4. The panel is attached to the bottom of the enclosure frame by two snap

fasteners. Pull the bottom of the panel out until the panel detaches from the
bottom of the enclosure.

5. Lift the panel slightly to release it from the lip at the top of the frame and
remove the panel. (Figure 6-3)

Figure 6-3

Right Side Panel Removal

FRU Removal and Replacement

6.1.2

Left Side Panel Removal

1. Turn the system off and unplug the ac power cord from the wall socket.

2. Open the front control panel door.
3. Loosen the screw that connects the left side panel to the front of the enclo S

frame. (Figure 6-4)

Figure 6-4

6-6

Unhooking the Left Side Panel

FRU Removal and Replacement

4. The panel is attached to the bottom of the enclosure frame by two snap
fasteners. Pull the bottom of the panel out until the panel detaches from the
bottom of the enclosure.

5. Lift the panel slightly to release it from the lip at the top of the frame and
remove the panel. (Figure 6-5)

Figure 6-5

Left Side Panel Removal

FRU Removal and Replacement

6.2

ON/OFF SWITCH REMOVAL

Remove the left side panel. (See Paragraph 6.1.2.)

Unplug the ON/OFF switch cable from the power supply.
Remove the nut that holds the cable’s ground lead to the enclosure frame.
Disconnect the ground lead.
Press the top and bottom of the ON/OFF switch and push the switch and its
cable out from the inside of the front panel. (Figure 6-6)

Figure 6-6

ON/OFF Switch Removal

FRU Removal and Replacement

6.3

CPU CONSOLE BOARD REMOVAL

1. Remove the left side panel. (See Paragraph 6.1.2.)

2. Disconnect the ribbon cable from the CPU console board. (Figure 6-7)
3. Remove the two screws that hold the CPU console board assembly to the
control panel.

4. Remove the board from the plastic brackets.

Figure 6-7

CPU Console Board Removal

FRU Removal and Replacement

b the enclosure by foursnap fasteners. Remove the
the frame
until the snap fasteners detach.
> power cables from the device.
m

nd
b

device out fif;‘“)@f ffi:h ¢ fif@h fiszl

6.4.1

RD52 Main Printed Circuit Board Removal

NOTE
Replace the main printed circuit board (MPCB) only on RD52
disk drives with part number 30-21721-02.

Screws located on the slide plate and MPCB are different sizes.
Make sure you reinstall the screws in their proper location.

1. Remove the four phillips screws retaining the slide plate and ground clip. Set
the slide plate aside. (Figure 6-8)

2. Unplug the 2-pin connector. (Figure 6-9)
3. Remove the two phillips screws that attach the front bezel to the drive.

6-10

FRU Removal and Replacement

Figure 6-9

Removing the 2-pin Connector and Screws

FRU Removal and Replacement

4. Remove the front bezel by pulling it away from the drive. The bezel is held in
1]

place with pop fasteners. (Figure 6-10)

5. Remove the three phillips screws from the heatsink, grounding strip, and the
corner opposite the heatsink. (Figure 6-11)

6. Lift the MPCB straight up until it clears the chassis. This disconnects P4, a 12-

pin fixed plug. (Figure 6-12)
e

. Disconnect P5, a 10-pin connector.

Figure 6-10

6-12

Front Bezel Removal

FRU Removal and Replacement

Figure 6-11

Removing the Phillips Screws from Heatsink
[

Figure 6-12

MPCB Removal

6-13

FRU Removal and Replacement

6.4.2

RD53 Disk Drive Electronics Board Removal

The RD53 read write boardis the only replacable part of an RD53 drive. Always

try to replace the device electronics board before you replace an entire RD53

drive.

1. Remove the four phillips screws retaining the slide plate and ground clip. Set

the plate aside.(Figure 6-13)

2. Loosen the two captive screws which hold the device electronics board in place.
3. Rotate the board upward (the board pivots in hinge slots at thefront of the

drive). Being careful not to strain any of theconnectors or cables, tilt the board

over center until it comes to rest against the outer frame.

ible circuit-material is fragile and requires careful hand ling

S
(==

—

?ai

o
o

e
-

S
£

o
S

soed

[
PO

feme

Fae

to avoid damage.

ig%é

[

o 2
oD

e o

Lo
s’

]

connector J9 from the read/write board. The connecmm mwfi WMM are %mmhm

mpers and switches for the newboard to

”&m same positions as the old one.

FRU Removal and Replacement

Figure 6-13

RD53 Device Electronics Board Removal

FRU Removal and Replacement

6.5

FAN REMOVAL

The following two sections list the procedures for removing the card cage fan and the

mass storage fan. The fan in the power supply is not an FRU.

6.5.1

Mass Storage Fan Removal

Remove the left side panel. (See Paragraph 6.1.2.)
jis

Note that the dc power cable plug is contoured to fit along the side of the fan.

Disconnect the cable from the fan. When replacing the fan be sure to align the cable

he same way.

Remove the three screws that connect the fan’s metal base plate to the enclosure

frame. (Figure 6-14)

NOTE

Observe the alignment of the fan before removing it. Be sure to
align the replacement fan in the same direction.

Figure 6-14

6-16

Mass Storage Fan Removal

FRU Removal and Replacement

4. Remove the four screws that connect the fan to the metal base plate.
6.5.2

Card Cage Fan Removal

1. Remove the right side panel. (See Paragraph 6.1.1.)

2. Remove the card cage door by releasing the two clasps at the front end of the
door and swinging the door open.

. Slide the tray below the card cage partially out. (Figure 6-15)

4. Note that the cable’s dc power plug is contoured to fit along the side of the fan.
Disconnect the cable from the fan. When replacing the fan be sure to align the
o

cable the same way.

Remove the four screws that connect the fan to the tray.

Figure 6-15

Card Cage Fan Removal

617

FRU Removal and Replacement

6.6

6.6.1

MODULES

Precautions

® Static electricity can damage modules. Always use a grounded wrist-strap (part
number 29-11762-00) and grounded work surface when working with or around
modules.

¢ Remove and install modules carefully to prevent damage to module components
&

and other modules and to prevent cha
1anging the switch settings.
L3

#°

® Replacement modules are shipped in special antistatic packaging material. A
silica gel packet is also included to prevent damage from moisture. Use this

antistatic packaging material and silica gel packet to protect any modules you
store, transport, or return.

e Be sure that the jumper and switch configurations on the replacement module

are the same as those on the module removed.
(re

removing a module from the backplane, be sure to note the position of
nodules and the alignment of any cables that you disconnect.

» When removing modules from the card cage, carefully but firmly pull the levers
which hold the module in place. When installing modules, make sure the levers
latch properly as you are trying to seat the module in the backplane.

e If you install a dual-height module in slots 1-4 of the backplane, you must install
it in the AB rows. MS360-AA memory modules must be installed in the CD
rows of slot 2 or 3. If you install dual-height modules in slots 5 through 12, you

the other two rows of the slot.

6.6.2

Removal

1. Remove the right side panel. (See Paragraph 6.1.1.)
2. Remove the card cage door by releasing the two clasps at the front end of the

door and swinging the door open.

Slide the module partially out of the backplane. (Figure 6-16)

4. Note the alignment of any cables attached to the module. Disconnect the cables.

Remove the module from the enclosure.

FRU Removal and Replacement

Figure 6-16

Module Removal

FRU Removal and Replacement

door

@:fi 0or md SW inging the door wwn

3. ThereisMdMfi; connecting the interlock switch to the temperature sensor.

Disconnect this cab «1
e from the temperature tensor. (Figure 6-17)

4. Remove
thetwo screws that connect the switch to the side of the card cage and
remove thw switch andthecable.

6.8

TEMPERATURE SENSOR REMOVAL

1. Remove the right side panel. (SeeParagraph 6.1.1.)
2. Remove the card cage door by releasing the two clasps at the front end of the

door and swinging the door open.

There is a cable connecting the interlock switch to the temperature sensor.
Disconnect this cable from the temperature sensor. (Figure 6-17)

4. There is a cable connecting the temperature sensor to the power supply.
Disconnect the cable from the temperature sensor.

5. Remove the temperature sensor from the four plastic brackets connecting it to
the enclosure frame.

6-20

FRU Removal and Replacement

TEMPERATUR
SENSOR

ooor InTERLOCK | N

SWITCH

HPR

Figure 6-17

Temperature Sensor/Door Interlock Switch

FRU Removal and Replacement

6.9

POWER SUPPLY REMOVAL

1. Remove the left side panel. (See Paragraph 6.1.2.)
2. Note the location and alignment of all cables attached to the power supply.

Disconnect all cables, including the ac power cord at the rear of the system.

Remove the four 1/4 turn fasteners holding the power supply to the enclosure
frame and remove the power supply. (Figure 6-18)

CAUTION
Before installing a new power supply, verify that the voltage
select switch at the rear of the power supply is set for the
correct ac voitage. Damage to the system could result if the

switch is not properly set.

6-22

FRU Removal and Replacement

Figure 6-18

Power Supply Removal

6-23

FRU Removal and Replacement

6.10

BACKPLANE

6.10.1

Removal

1. Remove both side panels. (See Paragraphs 6.1.1 and 6.1.2.)
zfi

. Slide all modules, including the signal distribution board, partially out of the
backplane.

. Remove the power supply. (See Paragraph 6.9.)

4. There i1s a metal plate between the backplane and the power supply. Remove
o

the six screws that hold the plate to the enclosure frame.

Lift the metal plate and the backplane out of the back of the card cage. (Figure

6-19)

6. Remove the screws that hold the metal plate to the backplane.

Figure 6-19

6-24

Backplane Removal

FRU Removal and Replacement

6.10.2

Replacement

Replace the backplane as follows.
N

_ Insert the screws that hold the metal plate to the backplane.

. Place the backplane and the metal plate at the back of the card cage.

_ Insert a module in the first and the last card guide of the card cage.
. Align the backplane so that the two modules can be fully inserted into the
backplane. Insert the modules.

_ Insert the six screws that hold the metal plate to the enclosure frame.
. Check the alignment of the backplane by inserting all of the system modules in
their original slots.

Replace the power supply by reversing the procedure described in Paragraph
6.11

FILTER CONNECTOR REMOVAL

Turn the system off. Unplug the ac power cord from the wall socket.
. Open the rear door.

Disconnect any cables attached to the filter connector. Note where the cables

were attached.

. Remove the right side panel. (See Paragraph 6.1.1.)

_ Remove the card cage door by releasing the two clasps at the front end of the
door and swinging the door open.
NOTE

Some of the internal cables that connect to the back of filter
connectors may not be keyed. Observe the alignment of the

internal cables and be sure to reconnect them the same way.

. Disconnect any cables that connect the filter connector insert to modules inside

j<§

the enclosure.

Remove the screws that hold the filter connector to the rear I/O panel.
Remove the filter connector.

6-25

FRU Removal and Replacement

6.12

MONITOR

The VR260 monitor comprises five assemblies
@

Cover and rear bezel

Chassis

Deflection board

Power LED.

In the following procedures, the left and right sides of the monitor are at your left

and right as you face the screen.

Turn off the monitor’s power.

2. Remove the power cord from the monitor’s rear bulkhead.

3. Remove the BC18P-10 video cable from the monitor’s rear bulkhead.
6.12.1

6.12.1.1

Cover and Rear Bezel

Removal -

1. Carefully place the monitor on its face.
2. Unscrew the four rubber feet from the bottom.

Remove the tilt swivel base.

Remove the four screws from the enclosure’s rear corners.
&

5. Lift off the cover.

6. Lift off the rear bezel.
6.12.1.2

Replacement- To replace the cover and rear bezel, reverse the

removal procedure.

6-26

FRU Removal and Replacement

6.12.2

Deflection Board

The deflection board and left-side chassis door are remove d as a unit.
i

6.12.2.1

Removal -

ig‘ai

Remove the monitor cover and rear bezel. (See Paragraph 6.12.1.1.)
Place the monitor on its bottom.

Loosen the two 1/4-turn fasteners at the front corners of the left-side chassis
door, and open the door.

J1 - 3-pin/2-wire power transformer connection
J2 - 12-pin/10-wire CRT socket board connection
J3 - 6-pin/4-wire CRT yoke connection

J5 - 3-pin/2-wire CRT socket board connection.
VIDEO

BOARD

TUBE/YOKE/BEZEL

ASSEMBLY

REAR

BULKHEAD

8 %\5{5;

4. On the deflection board, disconnect:

DEFLECTION

BOARD

Figure 6-20

TRANSFORMER

ASSEMBLY

‘

LED

ASSEMBLY

Deflection Board and Chassis Door Location

FRU Removal and Replacement

5. To remove the board/door assembly, lift the door up and pull it out.
#

sert a grounded screwdriver under the anode cap and make

anode clip to discharge the anode.

contact with the

7. Dis C onnect the anode lead (remove the 4inode cap from tt1e C
#

8. Remove the deflec tion circuit board from the six pl

door.

the deflection board assembly, reverse the

peef

Replacement - To repl

-emoval procedure.

e CRT assembly (Figure 6-20) is replaced as a unit and comprises
i

the following.

® Yoke
ocket board

e Monitor enclosure front/bezel

1. Remove the monitor cover and rear bezel. (See Paragraph 6.1:

lower left corner.

the upper
Bk

slip-on terminal.

ocket board ground

On the top front of the chassis, at its center, remove the screw that

fastens t he

chassis from the

oly, reverse the removal

6-28

FRU Removal and Replacement

6.12.4

Power LED

On the front of the monitor enclosure, the green LED that indicates “power on” is
held in place with double-sided, transparent, adhesive tape. (Figure 6-21)
6.12.4.1

Removal -

1. Using a knife tip or similar tool, carefully pry the LED/bezel assembly free of
the enclosure.

2. Disconnect the LED wires.
6.12.4.2

Replacement-

1. Connect the LED wires. The black wire is connected to the notched connector
leg.

9. Remove the protective paper backing from the double-sided tape on the LED/
bezel assembly.

3. Press the LED/bezel assembly in place.

Figure 6-21

Power LED Removal/Replacement

6-29

FRU Removal and Replacement

6.12.5

Monitor Alignment
The only special tools required for monitor alignment are a metric measuring

the diagnostic test patterns. (Figure 6-22)

tape and

Alignment should be checked and needed adjustments made after replacing
the deflection board or the CRT assembly.

All internal adjustments are accessible through appropriately labeled holes

top and left side of the chassis.

either

in the

FOCUS and G2 do not interact with any other internal adjustments.
The remaining
adjustments should be performed in the order listed to minimize the
effects of
interaction.
1. Turn the monitor’s and system’s power on.

32 SQUARES

26 SQUARES

Figure 6-22

6-30

Monitor Alignment Patterns

FRU Removal and Replacement

9 Set the monitor's BRIGHTNESS and CONTRAST controls to their maximum
positions.

3. After 30 seconds, adjust BRIGHTNESS until the raster disappears.
4. Adjust CONTRAST for the best picture.

. Run the display adjustment diagnostic and select the circle cross-hatch pattern.
Set BRIGHTNESS to a viewing level.
h. Set CONTRAST to extinguish the raster.

c. On the left side of the chassis (Figure 6-23), adjust LIN (horizontal linearity)
for horizontally uniform squares across the display. Note that the display size

Ygfi

B
it& gl
ek ffifi
e o
ik
3

should be near or at maximum, and positioned toward the left of the screen.

Figure 6-23

VR260 Monitor Adjustments,
H CENT, WIDTH, and LIN

FRU Removal and Replacement

d. On the top of the chassis (Figure 6-24), adjust VL (vertical linearity) for
vertically uniform squares.

J ]
s

&
HV

VE
|

w l

)

/TM

Figure 6-24

6-32

VR260 Monitor Adjustments (Top)

FRU Removal and Replacement

e. On the top of the chassis (Figure 6-25), adjust

FOCUS for the best vertical/

horizontal line convergence. Use cross-hatch pattern intersections approximately three squares toward the center from any screen corner.

FOCUS O

O G2 ADJ

—

Figure 6-25
&

VR260 Monitor Adjustments, Focus and G2

6-33

FRU Removal and Replacement

6. Select an all white screen.
Adjust CONTRAST and BRIGHTNESS for normal viewing with a visible
raster.

On the left side of the chassis, adjust

H CENT (horizontal centering) for a

centered raster.

On the top of the chassis, adjust HP (horizontal phase) to center the video in
the raster.

)

. Adjust BRIGHTNESS to extinguish the raster.

Set CONTRAST to a normal viewing level.

On the left side of the chassis, adjust WIDTH for a display width of 334 mm.
On the top of the chassis, adjust VH (vertical height) and VC (vertical
centering) so that the display touches both the top and bottom edges of the
screen.

h. Set VH for a display height of 282 mm.

7. Select the circle cross-hatch pattern.
d.

Check the vertical and horizontal linearity of the squares. Readjust if needed.

b. Check the vertical and horizontal centering, height, and width of the squares.

Readjust if needed.
C.

Check G2:

(1) Set CONTRAST to minimum and BRIGHTNESS to maximum. A raster
should be faintly visible.

(2) If no raster 1s visible, adjust G2 until a raster is faintly visible.

6-34

Appendix A
Console Commands
A.1

CONSOLE COMMAND SYNTAX

The console terminal accepts commands up to 80 characters long. Longer com-

mands result in error messages. The character count does not include rub-outs,
rubbed-out characters, or the terminating <RETURN>.

You can abbreviate a command by dropping characters from the end of its
keyword. However, it is necessary to supply enough letters of the keyword for the
system to distinguish one command from another.

The console treats multiple, adjacent spaces and tabs as a single space. Leading
and trailing spaces and tabs are ignored. Command qualifiers can appear after the
command keyword, or after any symbol or number in the command.
All numbers (addresses, data, counts) are hexadecimal; but, symbolic register
names include decimal digits. The hexadecimal digits are:
0123456789ABCDEF

The console accepts both upper- and lowercase letters in hexadecimal numbers
(A through F) and commands.

A.2

REFERENCES TO PROCESSOR REGISTERS AND MEMORY

The KA630-A console mode is implemented in macrocode executed from ROM.
For this reason, the actual processor registers cannot be modified by the command
interpreter. When console I/O mode is entered, the console saves the processor
registers in a scratch page, and all command references to them are directed to
the corresponding scratch page locations, not to the registers themselves. When

the console returns to program mode, the saved registers are restored. It is only
then that changes take effect. References to processor memory are handled normally, except where noted below.

Console Commands

°h page is a free page on the interrupt stack, so the
dify the machine state. If a free page on the interrupt stack cannot be

hysical mem-

<address> <count> <RE

addre 55,
[

ole 1s to read data from memor

and send it.
number (positive) of bytes to lo ad or unload.
B

command checksum is correct, the console respon

mode where the console is accepting keyboard characters as data, vA
€scape sequence.

yecified number of data byte S
an additional byte of received data checksum. The data is verified by
o an 8-bit regist%fl:«“ r initiz lly
set to zero. If the final register content is not zero, the dat LR1 or checksum 1 in
N

error, and the console responds with an error message.

A-2

Console Commands

is set), the console responds with

For a BINARY UNLOAL

the transmission, the 2's complement of the low byte of the register is sent.

Echo is suppressed during the data string and checksum reception.
¥

<( ¢ g ME«WWW%@

AN T

must be received. If dny of these timing requirem
aborts the transmission by issuir

single burst of characters at the console’s specified character rate. The console 18
i

able to receive at least 4 Kbytes of data in a single X command.
A.3.2

BOOT

T [<qualifier list:

The device specification format is “‘ddcu”, where “dd” is a 2-letter device mnei

)

¥ %

The Corn sol e initializes the proc € ssor and starts VMB running.
oy

VMB boots the

operating system from the specified or default device.
Qualifier:

e /R5:<data> - After initializing the processor and before starting VMB, R5 1
loaded with the specified data. This allows a console user to pass a parameter to
VMB. (To remain compatible with previous processors, /<data> will also be
.

recognized to have the same result.)

A-3

onsole C ommands

A.3.3

COMMENT

‘comment>

i,g

e
W

fi;«
M

omment command (exclamation point) is ignored. It is used to annotate con-

sole I/O command sequences.

ONTINUE

The processor begins instruction e xecution at the addre
ol

> <data>

Deposits the data into the specified addres:i If no address space or data size
qualifiers are specified, the defaults are the last address space and d.
g

in a DE POSIT or F
%

O mmand.

After proce sor initi 1lization, the default
-]

> 1s long, and the default

d data is too large to fit in the data size to be deposited, the con sole

(Processor st
| . fiw fi«i"‘”‘% fifiq 2”‘5@ amined, the
L 4o

Yoo

alh

Mot

[

iit

BB Ji.

B W %i

Hial

)

Mis?

Wit e

e W 5

Mgl

For example:

34 1s equivale

o012

D R10 6FF00 is equivalent to D/C|
L}

[

space 1s /G.

Console Commands

e -+ — (plus sign) The location immediately following the last location referenced
in an EXAMINE or DEPOSIT. For references to physical or virtual memory
spaces, the location referenced is the last address, plus the size of the last
reference (1 for byte, 2 for word, 4 for long). For other address spaces, the
address is the last address referenced, plus one.

e — —(minus sign) The location immediately preceding the last location referenced
in an EXAMINE or DEPOSIT. For references to physical or virtualmemory
spaces, the location referenced is the last address minusthe size ofthis refernce (1 for byte, 2 for word, 4 for long). For other address spaces, the address
is the last address referenced, minus one,

e * —(asterisk) The location last referenced in an

EXAMINE or DEPOSIT.

» (@- (at sign) The location addressed by the last location referenced in an
EXAMINE or DEPOSIT.
Qualifiers:
e

/B - The data size is byte.

/W - The data size is word.

/L — The data size is longword.

e /V — The address space is virtual memory. All access and |
occurs. If the access would not be allowed to a program running with

rent PSL, the console issues an error message. Virtual spa
the PT }M %m: to be set. If memory mapping is

)

ysical addresses.

re equal

e /P - The address space is physical memory.

o /I - The address space is internal processor registers. These are the registers
addressed by the MTPR and MFPR instructions.

e /G - The address space is the general register set, RO through PC (R15).

e /U-Access to console program memory is allowed. This qualifier also disables
‘&f

ss—é»

—

%#sé

f“"

- The address isthe first ofa range. The console depos s to the
fi mt mm2SS, Mwm to the specified number of succeeding addresses. [ven if the
‘““~"", the succeeding addresses are at larger
address is the symbolic address
addresses. The symbolic address specifies only the starting address
direction of succession. For repeated references to preceding K?M:M:m , use
%

virtual address protection checks.

“REPEAT DEPOSIT — <data>"".

Console Commands

NOTE

Only memory can be accessed as bytes or words. Registers, the

PSL, and the IPRs must be accessed using the longword reference. This means that the /B and /W qualifiers cannot be used

with the /Il and /G qualifiers.

For example:

D/P/B/N:1FF 0 0
D/V/L/N:3 1234 5

Clears the first 512 bytes of physical memory.
Deposits 5 into four longwords starting at virtual
address 1234.

D/N:8 RO FFFFFFFF

Loads general registers RO through R8 with —1s.

D/N:200 — 0

Starting at previous address, clear 513 bytes.

If conflicting address space or data sizes are specified, the console ignores the

command and issues an error response.

A.3.6

EXAMINE

EXAMINE [<qualifier list>] [<address>]

Examines the contents of the specified address. If no address is specified, “+" is

assumed. The address may also be one of the symbolic addresses described under

Qualifiers:
e

EXAMINE can use the same qualifiers as DEPOSIT

RESPONSE: <tab> <address space identifier> <address> <tab> <data>

The address space identifier can be:
e

P - Physical memory. Note that when virtual memory is examined, the address

space and address in the response are the translated physical address.

G - General register.

| - Internal processor register.

M - Machine-dependent (used only for display of the PSL).

A-6

Console Commands

A.3.7

FIND

FIND [<qualifier list>]

The console searches main memory starting at address zero for a page-aligned 64Kbyte segment of good memory, or an RPB (restart parameter block). If the segment or block is found, its address plus 512 is left in SP. If the segment or block is
not found, an error message is issued, and the contents of SP are unpredictable. If
no qualifier is specified, /RPB is assumed.

Qualifiers:

e /MEMORY - Search memory for a page-aligned 64-Kbyte segment of good
memory. The search includes a read/write test of memory and leaves the contents of memory unpredictable.

e /RPB - Search memory for a restart parameter block. The search leaves the
contents of memory unchanged.
A.3.8

INITIALIZE

A processor initialization is performed. The following registers are set (all values
are hexadecimal).

PSL

041F0000

All other registers are unpredictable.

The previous console reference defaults (the defaults used to fill in unsupplied
qualifiers for DEPOSIT and EXAMINE commands) are set to physical address,
longword size, and address 0.

A-7

Console Commands

A.3.9

HALT

The HALT command has no effect; the processor is already halted when in console

[/O mode.
A.3.10

REPEAT

REPEAT <command:=

The console repeatedly displays and executes the specified command. The repeating 1s stopped when the operator types <CTRL>C. Any valid console command

may be specified for the command, with the exception of the REPEAT command.

A.3.11

START

START [<address>]
The console starts instruction execution at the specified address. If no address is

given, the current PC is used. If no qualifier is present, macroinstruction execution
is started. If memory mapping is enabled, macroinstructions are executed from

virtual memory. The START command is equivalent to a DEPOSIT to PC, followed

by a CONTINUE. No INITIALIZE is performed.

A3.12

TEST

TEST [<test number>]

The console invokes a diagnostic test program denoted by <test number>. Valid

hexadecimal test numbers are 3 through 7, and B. If a test number is not supplied,

no test is performed.

A.3.13

UNJAM

UNJAM
An I/O bus reset is performed.

Appendix B

Console Error Messages and Explanations

Table B-1

Console Error Messages

Hex

Value

Message

EXT HLT

Explanation

<BREAK> was typed at the console; QBINIT or
QHALT was asserted.

ISP ERR

Caused by attempt to push interrupt or exception
state onto the interrrupt stack; when the interrupt
stack is mapped NO ACCESS or NOT VALID.

DBL ERR

A second machine check occurred while the
processor was attempting to report a machine check
to the operating system.

HLT INST

The processor executed a HALT instruction in
kernel mode.

SCB ERR3

Vector bits <1:0> = 3.

SCB ERR2

Vector bits <1:0> = 2.

CHM FR ISTK

A change mode instruction was executed when
PSL<IS> was set.

CHM TO ISTK

Exception vector bit <0> was set for a change
mode.

SCB RD ERR

A hard memory error occurred during a processor
read of an exception or interrupt vector.

MCHK AV

An access violation or invalid translation occurred
during machine check exception processing.

KSP AV

An access violation or invalid translation occurred
during invalid kernel stack pointer exception
processing.

B-1

Console Error Messages and Explanations

Table B-1

Console Error Messages

(Cont.)

Hex

Value
15

lessage
CORRPTN

Lxplanation
The console data base was corrupted. The console

simulates a power-up sequence andrebuilds its data

base.
16

ILL REF

The requested reference would violate virtual
memory protection, addressis not mapped, is invalid

in the specified address space, or valueis invalidin

the specified destination.

['he command S string cannot be parsed.
A number has an invalid digit.

LTL

The command was too large for the console to
buffer. The message
is issued only after the

gz;

ILL ADR

The specified address is not in the address space.

VAL TOO LRG

The specified value does not fit in the destination.

SW CONF

For example, an EXAMINE command specifies two
different data sizes.

UNK SW

<RETURN> terminating the commandis
received.

UNK SYM

he switc h m not recognized.

TheEXAMINEor DEPOSIT symbolic address is not

reco %mmmi*

CHKSM

An X command’s command or data checksum is

incorrect. If the data checksum is incorrect, this

message Is issued, and is not abbreviated to “Illegal

HLTED

The operator entered a HALT command.

FND ERR

A FIND command failed to find either the RPB or
64 Kbytes of good memory.

TMOUT

Data failed to arrive in the expected time during an

X command.
23

MEM ERR

Parity error detected.

UNXINT

An unexpected interrupt or exception occurred,

NOSUCHDEV

No bootable devices found.

DEVASSIGN

Device is not present.

Console Error Messages and Explanations

Table B-1

Console Error Messages (Cont.)

Hex
Value

Message

Program image not found.

42
43

FILESTRUCT

Invalid boot device file structure.

Bad checksum on header file.

44
45

Explanation

BADFILEHDR

Bad file header.

Bad directory file.

FILNOTCNTG

Invalid program image file.
Premature end-of-file encountered.
Bad file name given.

BUFFEROVF

Program image does not fit in available memory.
Boot device I/O error.

Failed to initialize boot device.
Device 1s off-line.
Memory initialization error.

SCBINT

Unexpected SCB exception or machine check.

Unexpected exception after starting program image.
NOROM

No valid ROM image found.
No response from load server.

Invalid memory configuration.
No devices bootable, retrying.

B-3

Appendix C
VCBO01 Video Controller Module
This appendix has two major sections. Section C.1 is a functional description of the

VCBO01 video controller module’s hardware. Section C.2, which contains programming information, describes the programmable functions of the VCBO01; that is, the

functions that can be specified and/or examined by software.
C.1

HARDWARE

C.1.1

Overview

Figure C-1 is a simplified block diagram of the VCB01 module, showing its major
functional areas, excluding its connections with the power supply and timing gener-

ator. Figure C-2 is a functional block diagram of the VCBO01, showing its major
address and data paths. The following sections describe the functional operation of

each major area.

C-1

VCBO01 Video Controller Module

INPUT/OQUTPUT

CONTROL AND STATUS
REGISTER

{CSR)
INTERRUPT

CONTROLLER
MOUSE

XCVRS

COUNTER

DUART

MOUSE

KEYBOARD

MEMORY

CURSOR
RAM

RAM
i3

VIDEO
L

MONITOR

Figure C-1

C-2

VCBO1 Module, Simplified Block Diagram

VCBO1 Video Controller Module

RCVR/

xcvRs | fCU8

MOUSE

Reg

[*1

DUART

MOUSE

LoGic

INTERRUPTS
{7)

CRTC

ADDR

ol MUX

LATCH

SCAN

MAP

i ADDR

¢ MOUSE

® INTERRUPT

CONTROL

KEYBOARD

o] CONTROLLER

_..l :x:c::vm!

rONTR

LATCH bt

LINE

MAP

MEM

BUFF

TM RFSH |,

MEMORY REFRESH

ADDR |

258 kB

MUX

RAM

- ADDR

MUX

»{

pATA
L ADDRESS

. wl PROM

|—e 1/0 SELECT

- OCKS ] TIMING
TIMING

CLOCKS

f—

%% ;2?1 |

DOUT 4 pata

LATCH

ol WE

)
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Figure C-2

VCBO01 Module, Functional Block Diagram

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VCBO1 Video Controller Module

C.1.2

Timing

Refer to Figure C-3. Basic timing for the VCBO1 is provided by an on-board

69.1968 MHz oscillator, providing a 14.45 ns clock. (An alternate on-board 32
MHz oscillatoris not used.) This frequency is divided through a pair of flip-flops

and a counter to generate the clocks listed in Table C-1. A timing PAL (programmable logic array) uses these clocks to generate the CRTC (CRT controller) clock

input as well as timing for other functions. (For more on CRTC timing, see Paragraph C.1.4.1.)

MHZ

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Table C-1

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VCBO1 Module, Simplified Timing Generator

VCBO1 Clocks
Period (ns)

Name

Actual

Nominal

D10DOTCLK/2

28.90

D12DOTCLK/4

30.0

57.80

D1260NS

60.0

57.80

D11120NS

60.0

115.60

115.5

D11240NS

231.20

231.0

D11480NS

462.40

462.5

D11960NS

924.80

925.0

Another on-board oscillator provides a 3.7 MHz clock to the keyboard/auxili1ary
DUART (dual universal asynchronous receiver/transmitter).

NOTE - Nominal Values
In most cases, the following descriptions and explanations rely
on the nominal values listed in Table C-1.

C-4

VCBO1 Video Controller Module

C.1.3

Q22-Bus/CPU Interface

The VCBO1 interface to the Q22-Bus uses standard DC0O05 transceivers and a
DC004 protocol chip, and a 9519A interrupt controller. (Figure C-4) The interface
supports the following.
Write word

DATO

Read word

DATI

Read/modify/write word

DATIO

Write byte

DATOB

Write block
L

Read block

Read interrupt vector

The VCBO1 can perform a block data transfer of up to two words. The block must
be longword-aligned (BDAL<01:00> = 0).

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C.1.3.1 Interrupt Controller - The 9519A interrupt controller handles eight
interrupt requests on priority levels 0 (highest) to 7 (lowest):
0 - DUART
1 - Vertical sync
2 — Mouse
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3 — Cursor start
4 — Mouse button A

5 — Mouse button B

6 — Mouse button C
7 — (Spare)

A set of internal registers control specific features of interrupt controller operation. The registers are described in section C.2.

Figure C-4 shows the control and data paths for the interrupt controller. Each
interrupt level has its own vector, stored in the controller’s internal 8 X 32
response memory. When an interrupt is requested on any level, the group interrupt
troller selects the highest priority request, asserts RIP (response in process), and
outputs the vector on BDAL<07:00>.

C.1.3.2 Registers ~ Control and status information is exchanged between the
VCBO1 and the CPU through hardware registers and 32 16-bit locations in the I/O
Page. These 32 locations are described in Section C.2. (See Table C-3.)

CSR - Figure C-5 shows the read and write paths for the CSR. Note that the CSR
comprises separate input and output registers. (See Table C-4 for bit descriptions.)
The input register data comes from BDAL<06:02>. The CSR output register
returns CSR bit status on BDAL<10:06,04:02>.

VCBO1 Video Controller Module

CSR
(OUT)

{

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DCOO3

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NORM

DALO3

DALO4

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DALO4

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DALO6

RINIT

DRVRS

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CLR

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Figure C-5

C.1.4

LOGIC

VCBO1 CSR Read/Write Paths

CRTC

The CRT controller generates CRT (cathode-ray tube) timing, video refresh
addresses, and controls cursor position. The CRTC is programmable, and accessed

through the CRTC address pointer and the CRTC data register. (See Paragraph

C.1.4.1

CRTC Timing - The horizontal frequency (approximately 54 kHz) and

vertical frequency (60 Hz) of the VR260 monitor, along with the 925 ns clock

(nominal; see Table C-1), determine the timing sequence for transferring an image
from video memory to the CRT screen.

VCBO01 Video Controller Module

The dual-ported video memory is accessed in both halves of a 925 ns access cycle,
as shown in Figure C-6. During the first half-cycle, the memory is addressed and
updated from the Q22-Bus. During the second half-cycle, the memory is addressed
by the video refresh address from the CRTC, and read to refresh the CRT screen.
(The update and refresh cycles are described in more detail in Paragraph C.1.5.)

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Figure C-6

|Q22-BUS| VIDEO

|REFRESH |UPDATE | REFRESH

Video Memory Access Cycle

In CRTC terminology, the 462.5 ns video refresh half-cycle is equivalent to a
character time. The number and duration of the character times determine the
period of HSYNC (horizontal sync); that is, the time for each horizontal scan line.

Using the VR260 monitor with a horizontal frequency of 54 kHz, the HSYNC
period is 18.5 us, or 40 character times. (Figure C-7) Note that time and frequency values are nominal. The horizontal retrace period (horizontal blanking) 1s
the difference between the total time for one horizontal scan line and the displayed
(unblanked) part of the scan line. For the VR260, this is 40 — 32 = 8 character
times, or 3.7 us horizontal blanking.

In a similar way, the CRTC controls vertical timing. (Figure C-8) In a 60 Hz
VR260 monitor, the VSYNC period is 16.667 ms. Of this, approximately 0.7 ms is
vertical retrace (vertical blanking) time and the screen is unblanked for 15.9 ms.
With a horizontal scan line time (HSYNC period) of 18.5 us, a total of 901 horizontal scan lines can be generated during the VSYNC period (16.6 ms), with 864 scan
lines displayed during the 15.9 ms vertical unblanking time.
*

In CRTC terminology, vertical timing is programmed in terms of character row (or
character line) times. A character row comprises 16 horizontal scan lines. For the
displayed portion of the vertical scan, the CRTC vertical displayed parameter is 54
(for 54 character rows, or 864 scan lines). For the total vertical scan, the vertical
total parameter of the CRTC is 55 (for 56 minus 1 character rows). This equates
to 896 horizontal scan lines, where 901 need to be generated. Therefore, the
CRTC vertical adjust parameter (must be less than 16) is 5, providing the required
number of scan line times for the VR260 to complete the 16.6 ms vertical scan.

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CRTC Vertical Timing

During the time the display is blanked, the 462.5 ns video refresh cycles are used
to refresh the video memory RAMs. The dynamic RAM refresh address is gener-

ated by a 4-bit refresh counter.

Other timing values programmed in the CRTC include sync pulse width, start of
sync, and start of display enable.

VCBO1 Video Controller Module

The CRTC also contains a video refresh register and cursor start and end address
registers. The refresh register contains the address of the first video memory
address to be read at the end of vertical blanking. The cursor start address regis-

ter contains the scan line where the cursor starts, and control bits to enable the
cursor, cause it to blink, and set the rate at which it blinks.

C.1.5

Video Memory

The video memory is a 256-Kbyte dual-ported MOS RAM array. It is a single-

plane (or 1-plane) bit-mapped memory; that is, the value (on or off) of each pixel
on the screen corresponds to the value (1 or 0) of only one bit in memory. Each

pixel is defined by its X,Y position in the memory, where Y represents a scan line

1 pixel (bit) high and 1024 pixels (bits) long (X). There are 2048 scan lines in

video memory. (Figure C-9)

NOTE - Coordinate System
The top, left corner of the screen is (X,Y) coordinate (0,0).

The bottom, right corner of the screen is (X,Y) coordinate

(1023,863).

Video memory is dual-ported, giving access to the Q22-Bus to update video memory, and to the scan line map to refresh the monitor screen (video refresh).

The 32 64 K X 1 dynamic RAMs (refresh is required) that make up the array are
arranged in 32-bit words. The byte, word, or longword operand is specified by

Q22-Bus BDAL<17:00>. BDAL<17:07> specify one of the 2048 scan lines, and

BDAL<06:00> specify one of the 128 bytes within the scan line. Individual bits are

controlled by CPU bit operations.

For video refresh, video memory is addressed through the scan line map as an X-Y
address space. The scan line map selects any 864 scan line segment of video

memory, each line having 1024 pixels.

C-12

VCBO0O1 Video Controller Module

1023

CURSOR

RAM

2047

Figure C-9

VR260 Monitor Display Mapping

C.1.5.1 Scan Line Map - The scan line map comprises two 2 K X 8 static
RAMs (refresh is not required). It is configured as a 1 K X 11 RAM; that is, the
MSB (most significant bit) of the address is disabled, and the five MSBs of the
output are not used. It translates the 10 MSBs of the CRTC start address output

(video refresh address) into an 11-m video memory physical address, mapping any

864 of the 2048 video memory scan lines to the VR260monitor (Figure C-9). If
the VCBO1 is usedin half-page mcf}dfi‘: the scan line map maps only the lowest 800
pixels of any 480 scan lines to a half-page monitor.

The scan line map is addressed as the upper 2 Kbytes of VCBO1 address space

(see Figure C-18), making these video memory addresses unavailable for storing
and refreshing video images. (Note that read and write operations to these
addresses access both the scan line map and video memory.) Therefore, the 11
LSBs (least significant bits) of location MSA + 254 K (MSA + 260096) are the 11
bits output from the scan line map. They point to the video memory address of the
first video scan line; MSA + 254 K + 2 points to the next scan line, and so on.

C-13

VCBO1 Video Controller Module

C.1.5. fl

Video Memory (Update Memory) - As Figure C-10 shows, video

memory is fiddwwwd by eight lines fmm the memory address mux {mmtiplexer).

‘Tmm MEW% are multiplexed, 8-bit, row and column addresses. The row and column

addresses are latched in memory at the appropriate time by RAS and fi AS (row

address strobe and column address strobe) inputs, providing a 16-bit memory

address.

The memory addressmux output, D4AMA07:00, is one of the following, selected by
the combinations of D11UPDATE and—D11COL (read as “not D11COL”).

0 - Video refresh column address
1 - Video refresh row address
o

Jpdate memory column address

— Update memory row address

Video memory is updated from the Q22-Bus every 925 ns. To update the image in
video memory, the row address on BDAL<14:07> is selected by:

The column address on BDAL<17:15,06:02>

is selected by:

—D11COL = Low

The addresses are latched by D11RASO and D D11CASO from the timin g PAL.
The input data (two 16-bit words) on BDAL<15:00> is written into each of the
four bytes of the ‘”W bit memory by four write-enable signals, D12WE03:00, from a
32 X 8 write PROM.

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C.1.5.3

Video Memory (Video Refresh) - Figure C-11 shows the read-access

paths to video memory. To refresh the monitor screen, the row address on

D5CRO7:00 is selected through memory address mux input 1 — DA by:

D11UPDATE = Low

The column address on D5LMAP10:08 and D5LCADRO04:00 is selected through

input 0 — DA by:

D11UPDATE = Low

~D11COL = Low
The row address is selected through refresh mux input 0 — DA (this mux is
described in more detail below), and is supplied by the scan line map on

D5MAPDATO07:00. The scan line map also supplies the three MSBs of the column
address on D5LMAP10:08. The five LSBs of the column address, DSLCADRO04:00,

are supplied by the CRTC. This 16-bit (8 row, 8 column) video memory read
address is interpreted as shown in Table C-2, and described below.

Table C-2

Video Refresh Address Derivation

Address: | Row

Source:

Column

Memory Address MA_

Memory Address MA__

07 06 0504 03 02 01 00|

07 06 05 04 03 02 01 00

| Scan Line Map
MAPDAT _

CRTC
- LMAP_. | LCADR_

07 06 05 04 03 02 01 00 | 10 09 08| 04 03 02 01 00
11 bits address 2048 lines
5 bits address
(32 words per line)
(32 words)

For video refresh, video memory represents 2048 scan lines with 1024 pixels per
line. Therefore, each line of the video image requires 32 32-bit words. Because
each memory address reads one 32-bit word, 32 addresses are required to read

one scan line. To read a specific line for display, the 11-bit scan line map outputs,

D5MAPDATO07:00 and D5LMAP10:08, provide the 11 MSBs of the memory

address. Each of the 32 32-bit words in that line are read by incrementing the

5 LSBs of the memory address, supplied by the CRTC as DSLCADR04:00. In the
VAXstation II system using the VR260 monitor, only 864 of the 2048 lines are

C-16

VCBO1 Video Controller Module

displayed, and all 1024 bits (32 32-bit words) of any scan line are displayed.
The 32 words correspond to the 32 character times that the screen is unblanked.
(Figure C-7)

The scan line map is addressed by the 10 MSBs of the CRTC address output,
D5RA03:00 and D5CADR13:08, through map address mux input 0. (This mux is
described in more detail below.) The CRTC start address register contains the
value of the first address output by the CRTC; the address is then updated at the
CRTC clock rate (determined by the timing PAL). Timing i1s such that 864 scan

line map locations will be addressed during vertical display time, and 37 addressed
during vertical retrace time. (Figure C-8) The CRTC output address will then be
reset to the value of the start address register, and the process repeated. Continuing the address update during vertical retrace provides the addresses needed for
dynamic RAM refresh (described below).

The contents of each scan line map location is the 11 MSBs of a video memory
address.

C.1.5.4 Video Memory (RAM Refresh) - Figure C-11 shows that the only difference between the video memory read path and the dynamic RAM refresh path
(Figure C-12) is that the row address, D5CR07:00, is supplied by the refresh
counter through input 1 — DA of the refresh mux.

The RAM refresh row address, D4REF07:00, is selected through the refresh mux
when D5DE (display enable) from the CRTC is not asserted. D5DE is de-asserted
during horizontal retrace time and vertical retrace time.

The refresh counter is updated during every video memory update cycle (every
925 ns; see Figure C-6) when D5DE is not asserted. Therefore, every video
refresh cycle during horizontal and vertical retrace times is a RAM refresh cycle,
and updated row and column addresses are generated each cycle.

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C.1.5.5.

Scan Line Map (Update) - The 864 video memory addresses to be

read for video refresh are stored in the scan line map. (Figure C-13)

When D11UPDATE is asserted, the scan line map is addressed from the Q22-Bus
through input 1 of the map address mux. If the bit-map memory (video memory) is

being addressed (D3BMSEL asserted) and the upper 2 Kbytes are being addressed

(BDAL<17:11> asserted), the buffer is enabled, and write data is gated through to

the scan line map RAM 1/O pins. The write is enabled to each of the RAMs by
D12WRSCANHB:LB from the 32 x 8 write PROM.

C.1.5.6

Cursor - The cursor is a 16 X 16 pixel image stored in the cursor RAM
(static RAM). The output of the cursor RAM is logically combined with the output

of video memory, by either ANDing or ORing the two outputs.

The cursor image is stored by writing to the upper 16 locations of the VCBO1
address space (MSA + 256 K — 16).
The cursor can be positioned at any point on the screen, within the limits of the
coordinate system. The cursor origin is its top, left corner: its minimum (X,Y)
position is (0,0) and its maximum (X,Y) position is (1007,847). The cursor Y-

position is determined by the contents of the CRTC cursor start, end, and address
registers; its X-position is stored in the cursor X-position register.

C.1.5.7

Cursor RAM (Write) - Refer to Figure C-14. When the top 16 locations
(BDAL<17:05> asserted) of bit-map memory are addressed (D3BMSEL asserted)

during an update cycle (D11UPDATE asserted), the 16 cursor RAM locations are
addressed by BDAL<04:01> through input 0 of the cursor address mux.
The data (cursor image) on BDAL<15:00> is written into the RAM when
D12WRCURSHB:LB are asserted by the 32 x 8 write PROM.

C.1.5.8

Cursor RAM (Read) - To read the cursor RAM and display the cursor

image, the RAM is addressed by a 4-bit address counter through input 1 of the

cursor address mux. The counter is enabled (through combinational logic) by the
CURS and HSYNC outputs of the CRTC.

C-20

VCBO1 Video Controller Module

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C.1.6

Mouse

The mouse position logic comprises flip-flops driven by commutator brushes
(Figure C-15) and push buttons. The flip-flops provide signal settling (de-bouncing)
and pulse shaping, and generate square-wave outputs. The square-wave leading

edges are counted, giving an effective resolution of 100 counts per 2.54 cm (1 in).
COMMUTATOR

B WGOMMUTATOfi

BRUSHES

Figure C-15

Mouse Construction

The X and Y commutators each provide a distance signal (D15CLK1B and
D15CLK1A) and a direction signal (D15CLK2B and D15CLKZ2A), which control the
clock and count direction of X and Y counters. (Figure C-16) The mouse push
buttons are input to the interrupt controller and CSR.

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Mouse direction is determined by the direction of the count; that is, up or down.
The direction of count is determined by the phase relationship between the distance and direction outputs. When the mouse is moved in one direction, the distance output leads the direction output; mouse travel in the opposite direction
reverses the phase relationship. This phase relationship is a result of commutator
construction.

Another characteristic of mouse construction is that the period, and therefore, the
number, of square-wave edges-per-inch varies with direction of travel. For example, if the mouse is moved in an exact vertical direction, the Y-axis would output
the maximum number of edges-per-inch, indicating the maximum rate-of-change;
the X-axis output would be flat, indicating no rate-of-change. If the mouse is moved
in a direction that is halfway between vertical and horizontal, both the X-axis and
Y-axis will output the same number of edges-per-inch.
Each time the mouse is moved an interrupt request is generated

(D15MOUSECTINT). The accumulated X and Y count is transferred to
BDAL<15:00> through the X and Y registers as a result of a bus DATI function
(D3INWD). Normally, this occurs during vertical sync time; that is, every 16.6 ms.
The distance the mouse traveled in that time is proportional to the change in the
accumulated count.

C.1.7

Keyboard

The keyboard is driven by an 8051 microprocessor, and contains a set of
microdiagnostics. The keyboard logic detects and encodes keystrokes, and transmits the information to the DUART. (Figure C-17) The programmable DUART
serializes/deserializes parallel bus data (BDAL<07:00>), implements the EIA
RS423 interface, and generates an interrupt request (D14COMINT) to the interrupt controller. An on-board 3.6864 MHz oscillator supplies the baud rate clock
input to the DUART.

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VCBO1 Video Controller Module

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VCBO1 Video Controller Module

C.2

PROGRAMMING INFORMATION

This section describes the programmable functions of the VCBO1 video controller
module; that is, the functions that can be specified and/or examined by software.

C.2.1

Address Space

The MicroVAX architecture specifies a 1-Gbyte (gigabyte) physical address space,

divided into a memory space and I/O space. (Figure C-18)

3FFFFFFF

I/O SPACE

20000000
1FFFFFFF

MEMORY SPACE

00000000

Figure C-18

MicroVAX Physical Address Space

In the MicroVAX, address bit <29> selects either the memory space or I/O space,

bit <28> is a no-cache indicator, bits <27:22> are ignored, and bits <21:00>
select a location within memory space or I/O space.

In the VAXstation II, the VCB01 video memory resides in the I/O physical address
space, in the highest 256 Kbytes addressable by BDAL<21:00>. Figure C-19
shows the location on the VCB0O1 video memory in the VAXstation II physical

address space. The MSA (memory starting address) of the 256-Kbyte VCBO1 block
1s switch-selectable.

The 256-Kbyte VCBO1 address space comprises the three segments, shown in
Figure C-20. The scan line map RAM overlays the upper 2 Kbytes of the

256-Kbyte bit-mapped RAM; the cursor RAM overlays the upper 32 bytes of the
scan line map RAM. As described in Section C.1, these are all separate RAMs, not
part of the same RAM.

C-27

VCBO1 Video Controller Module

3FFF FFFF

VCBO1 VIDEO MEMORY

256 KBYTE
FFC 000

2000 1FFF

2000 1E80

VCBO1 CSR BASE ADDRESS
Q22-BUS 1I/O SPACE

8 KBYTE
2000 0000

MEMORY SPACE BEYOND

INSTALLED MEMORY SPACE
008F FFFF —

—

=9 MBYTE:

—

O01F FFFF -

—

2 MBYTE

~—
—

INSTALLED MEMORY SPACE

2TO 9 MBYTE

0000 0000

Figure C-19

VAXstation II Physical Address Space

} 32 BYTES

CURSOR RAM
MSA +262112

2 KB LESS

SCAN LINE MAP RAM

32 BYTES
“

ingoni

, 256 KB LESS
2 KB

MSA + 000000
Figure

C-28

C-20

VCBO1

256-Kbyte

Address

Space

VCBO1 Video Controller Module

C.2.2

VCBO1 Registers

Control and status information is exchanged between the VCBO0O1 and the CPU
through 32 16-bit locations in the I/O page. These locations are listed in Table C-3
and described below.
NOTE - Bit Descriptions

Many of the bit descriptions in the following tables include a
value in parenthesis; for example: (1 = chip armed). This usually
indicates the initialized value of the bit.
Table C-3

VCBO1 Registers

Address*

Name

BASE
BASE+4

CSR - Control and status register
Cursor X-position
Mouse position register

BASE+6

(Spare)

BASE+8

CRTC address pointer register
CRTC data register
ICDR - Interrupt controller data register
ICSR - Interrupt controller command/status register

BASE+2

BASE+10
BASE+12
BASE+14

BASE+16 through BASE+31 (Spares)
UART mode registers 1A and 2A
BASE+32
UART status/clock select register A
BASE+34

BASE+42

UART command register A
UART transmit/receive buffer A
(Spare)
UART interrupt status/mask register

BASE+44

(Spare)

BASE+46

(Spare)

BASE+36
BASE+38

BASE+40

UART mode registers 1B and 2B
UART status/clock select register B
UART command register B
BASE+52
UART transmit/receive buffer B
BASE+54
BASE+56 through BASE+62 (Spares)
BASE+48

BASE+50

* BASE = CSR base address

VCBO01 Video Controller Module

C.2.2.1
Control and Status Register - The CSR bits are shown and described
in Figure C-21 and Table C-4. Note that following a Q22-Bus BINIT, bits <06:02>
are cleared (= 0).

ADDRESS = CSR BASE

Figure C-21
Table C-4

Bits

VCBO01 CSR Format

VCBO1 CSR Bits

Access

Description

<14:11>

READ

Memory bank switch 0:3 (MSA switch E14 S1:54)

<10:09>

READ

Mouse switch C:A (0 = closed)

<07>

READ

Cursor active (1 = cursor on)

<06>

RD/WR

Interrupt enable (1 = enabled)

Test bit (used with loopback connector)

<15>

(Spare - not used)

<05>

RD/WR

<04>

RD/WR

Enable video read-back (1 = enabled)

<03>

RD/WR

Cursor function (1 = OR, 0 = AND)

<(02>

RD/WR

<01>
<00>

C-30

Enable video output (1 = enabled)
(Spare - not used)

READ

19 in/15 in mode (1 = 19 in)

VCBO1 Video Controller Module

C.2.2.2 Cursor X-Position - This register (Figure C-22 and Table C-5) contains
the horizontal position location of the top left corner of the 16 X 16 (pixel) cursor
image. The value is in pixels and must not allow the cursor to be positioned beyond
the maximum X pixel. That is, the maximum value is 1007 (1023 — 16) for a
VR260 monitor, and 783 (799 — 16) for a 38 cm (15 in) monitor.

*Wxfififlfifm 7
)

;;”/ »;;,;%ff /»*;f
L

Figure C-22

CURSOR X POSITION

VCBO1 Cursor X-Position Format

VCBO1 Cursor X-Position Bits

Table C-5

Description

Access

Bits

<15:10>

(Not used)

Cursor X-position in pixels.

WRITE

<09:00>

C.2.2.3 Mouse Position Register — This register (Figure C-23 and Table C-6)
contains mouse X- and Y-position values. The values are counted up or down, in
proportion to the direction and amount of mouse movement.
15

Figure C-23

Table C-6

]

Mouse Position Register Format

Mouse Position Register Bits

Bits

Access

Description

<15:08>
<07:00=>

READ
READ

Mouse Y-position count
Mouse X-position count

C-31

VCBO01 Video Controller Module

C.2.2.4

CRTC Registers —

CRTC Address Register Pointer — This register points to the 1 of 17 internal
CRTC registers (Table C-7) that is to receive the data contained in the CRTC data

Table C-8)

Table C-7

CRTC Internal Registers

Reg

Name

Horizontal Total

Description
The total number of character times in a line,
minus 1.

Horizontal Displayed

The total number of displayed characters in a
line.

HSYNC Position

Defines the number of character times until
HSYNC (horizontal sync).

HSYNC/VSYNC Widths

Four bits each are used to define the HSYNC
pulse width and the VSYNC (vertical sync)

pulse width.
04

Vertical Total

Total number of character rows on the screen,
minus 1.

Vertical Total Adjust

The number of scan lines to complete the
screen.

Vertical Displayed

The number of character rows displayed.

VSYNC Position

The number of character rows until VSYNC.

Mode

Controls addressing, interlace, and cursor.

Maximum Scan Line

The number of scan lines in a character row,
minus 1.

Cursor Scan Start

Defines the scan line at which the cursor
starts.

Cursor Scan End

Defines where the cursor ends.

Start Address High

Defines the RAM location where video refresh

Start Address Low

C-32

begins.

VCBO1 Video Controller Module

Table C-7

CRTC Internal Registers (Cont.)

Reg

Name

Description

Cursor Address High

Defines the cursor position in RAM.

Cursor Address Low

Light Pen Position High

Light Pen Position Low

Contains the position of the light pen.

00
T

LPF | VBL

ADDRESS = CSR BASE+S

Figure C-24

Table C-8
Bits

CRTC Address Register Pointer Format

CRTC Address Register Pointer Bits
Access

<15:08>

Description
(Not used)

<Q7>

READ

Update strobe (not used)

<06>

READ

Light pen r@gi&mr fmll (1 = full)

<(05>
<04:00>

READ
WRITE

Vertical blank (
Vblank time)
CRTC internal mgz,&ter address (Table C-7)

CRTC Data Register - This register (Figure C-25 and Table C-9) contains the
eight bits of data to be loaded into the internal CRTC register addressed by bits
<04:00> of the CRTC address pointer register.

///fMm
U /1//,.»
M’"

o’

ADDRESS= CSR BASE+10

Figure C-25
Table C-9
Bits

CRTC Data Register Bits
Access

<15:08>

<07:08>

CRTC Data Register Format

Description
(Not used)

RD/WR

CRTC internal register data

C-33

VCBO1 Video Controller Module

C.2.2.5

Interrupt Controlier Registers - Using a set of internal registers, the

interrupt controller handles eight interrupt requests on priority levels 0 (highest) to

7 (lowest):

1 - Vertical sync

2 - Mouse

3 — Cursor start
4 — Mouse button A

5 — Mouse button B
6 — Mouse button C

7 - (Spare)
A vector for each request level is stored in an internal 8 X 32 response memory.

The response memory cannot be read and is unaffected by a RESET command.
The internal registers are accessed through the ICSR (interrupt controller command/status register) and ICDR (interrupt controller data register). The registers

are described in the following paragraphs.

ICDR - The interrupt controller data register (Figure C-26 and Table C-10) contains the data for/from the internal interrupt controller register addressed by the
last PRESELECT command.

“f"“H’“«“74

00
i

DATA

]

ADDRESS
= CSR BASE+12

Figure C-26

Table C-10

Bits

ICDR Bits

Access

<15:08>

<07:08>

C-34

ICDR Register Format

Description
(Not used)

RD/WR

Interrupt controller internal register data

VCBO01 Video Controlier Module

ICSR - The internal interrupt controller registers are accessed through the ICDR
and the ICSR (interrupt controller command/status register). The ICSR is a command register on write operations and a status register on read operations. (Figure
C-27 and Table C-11)
READ:

Figure C-27
Table C-11
Bits

]

ICSR Format

ICSR Bits
Access

Description
(Not used)

Group interrupt (1 = interrupt pending). Vector is in
bits <02:00>.

READ

Enable (1 = chip enabled).

Priority mode (1 = rotating, 0 = fixed).

<(5>

Interrupt mode (1 = polled, 0 = interrupt).
Master mask (1 = chip armed).
<(02:00>

READ

Binary vector of the highest unmasked bit in the IRR
(interrupt controller interrupt response register). Valid
only when bit <07> 1s set.

Command. (See Table C-12.)

C-35

VCBO1 Video Controller Module

Table C-12

ICSR Commands

ICSR*

<07:00>

Command

00000000

Description
Sets the IMR (interrupt mask
register) to all ones. Clears to zeros

the: IRR (interrupt response
register), ISR (interrupt service

memory and byte count registers are

not affected.
00010xxx

Clears all bits in the IRR and IMR.
Clears both the IRR bit and the IMR
IMR BIT

bit specified in <02:00>.

00110xxx

Sets all IMR bits to ones.

00111BBB

Sets the IMR bit specified in

01000xxx

CLEAR IRR

Clears all IRR bits to zeros.
Clears the IRR bit specified in
<02:00>.

0110xxxx

Clears the highest priority bit set in
the ISR.

01110xxx

CLEAR ISR

CLEAR ONE ISR BIT

Clears all ISR bits to zeros.

Clears the ISR bit specified in
<02:00=>.

Sets the five low-order bits of the
M4:MO

mode register to the value in
<04:00>.

VCBO1 Video Controller Module

Table C-12

ICSR Commands (Cont.)

ICSR*

Command

Description

1010MMNN

CONTROL MODE BITS

Sets mode register bits 6 and 5 to

M7:M5

the value in <06:05>. Mode register
bit 7 1s set according to <01:00>, as
follows.

Bit7

Unchanged

0
1
0

1
0
0

Set
Cleared
(llegal)

1071 1xxxx

PRESELECT IMR FOR
WRITING

All future write operations to the
ICDR load the data into the IMR.

1100xxxx

PRESELECT ACR FOR
WRITING

All future write operations to the
ICDR load the data into the ACR.

11100LLL

PRESELECT RESPONSE
MEMORY FOR WRITING

All future write operations to the
ICDR load the data into the response
memory at the interrupt request
level location specified in <02:00>.

* x = 1 or 0 (does not matter)

IRR — The 8-bit interrupt request register stores pending interrupt requests. An
IRR bit is set when the corresponding interrupt request line is asserted, and is
automatically cleared when the request is acknowledged. The IRR bits can be read,
set, and cleared through the ICSR and ICDR. RESET clears the IRR.
IMR - The 8-bit interrupt mask register is used to enable (bit cleared) or disable
(bit set) the corresponding interrupt request lines. A set IMR bit does not disable
the IRR bit, and the request will remain pending until the IMR bit is cleared. Only
unmasked interrupts generate the group interrupt output. All IMR bits are set by

ISR -~ The 8-bit interrupt service register stores the acknowledge status of interrupt requests. When an interrupt is acknowledged, the controller selects the high-

est priority request pending, clears its IRR bit, and sets its ISR bit. ISR bits can be
automatically cleared at the end of the acknowledge cycle or on specific command.
The ISR can be read through the ICSR and ICDR. RESET clears the IRR.

VCBO1 Video Controller Module

ACR ~ The 8-bit auto clear register specifies the clearing mode for the ISR. A set
ACR bit specifying the corresponding ISR bit will be automatically cleared at the

end of the acknowledge cycle; a cleared ACR bit means the corresponding ISR bit
must be cleared by the CPU through the ICSR and ICDR. The ACR can be read
through the ICSR and ICDR. RESET clears the ACR.

Mode -~ The 8-bit interrupt controller mode register controls many controller
options. The mode register is loaded through the ICSR and ICDR. It cannot be

read. Bits 00, 02, and 07 are available to the ICSR on read operations. RESET
clears the mode register. The bits are described in Table C-13.

Table C-13
Bits
<07>

Interrupt Controller Mode Register Bits
Description
MM - Master mask. Enables (set) and disables (cleared) group
interrupts to the CPU.

<06:05>

RP1:RP0O - Register preselect. Select the internal register to be read

RP1

<04>

RPO

O
e O

when the CPU reads the ICDR:

ISR
IMR

ACR

REQP - Interrupt request polarity. Determines interrupt request
transition direction for setting IRR bits. Set = low to high, cleared =

high to low. (Should always be cleared.)
<03>

GIP - Group interrupt (GINT) polarity. When set, GINT is asserted

high; when cleared, GINT is asserted low. (Should always be
cleared.)
<02>

IM - Interrupt mode. When set, polled mode is selected, and group

interrupt disabled. The controller will not interrupt the CPU. To
determine if there are any pending interrupts, the CPU must read

the ICSR. When cleared, interrupt mode is selected, and group
interrupt functions normally.
<01>

VS - Vector selection. When cleared, each interrupt will generate its
own vector (contained in response memory). When set, all interrupts
generate the same vector (request level 0 vector).

C-38

VCBO1 Video Controller Module

Table C-13

Interrupt Controller Mode Register Bits (Cont.)
Description

PM
-Priority mode. When cleared (fixed priority), level 0 interrupt
requests are the highest priority, level
7 the lowest. When set
(rotating priority), the last interrupt level serviced becomes the
lowest priority level.

C.2.2.6 UART Registers - The registers shown and described in Figures C-28
through C-32 and Tables C-13 through C-18 are all used to communicate with and
control the keyboard/auxiliary DUART.
Note that mode registers 1A and 2A are accessed by two successive references to
the same [/O address. The same is true for the channel B mode registers. Also
note that the following registers serve different functions on reads and writes.

Read

Write

Status/clock select
Transmit/receive buffer
Interrupt status/mask

UART status
Receive data
Interrupt status

Tx/Rx clock select
Transmit data
Interrupt mask

Mode Registers 1A and 2A - These UART registers are accessed by two successive references to the same I/O address.

RC | RIS | ERM | PARMOD | PAT

TRC | CET

B/CHAR

00
STOP BIT LENGTH

Figure C-28

03
i

Q00
i

Mode Registers 1A and 2A Format

C-39

VCBO01 Video Controller Module

Table C-14
Bits

Mode Registers 1A and 2A Bits
Access

Description
(Not used)

<07>

RD/WR

<06>

RD/WR

<04 03>
<02>

Rx (receive) RTS (request-to-send) control (1 = no)
Rx interrupt select (1 = FIFO full)

RD/WR

Error mode (1 = block)

RD/WR

Parity mode (10 = no parity)

RD/WR

Parity type (1 = odd)
Bits per character (11 = 8)

RD/WR

Channel mode (00=normal)

RD/WR

Tx (mmwmm RTS control (1=no)

RD/WR

CTS (clear-to-send) enable Tx ( 1 =no)

RD/WR

Stop bitMmgth (0111=1 bit)

Mode Registers 1B and 2B - (ADDRESS
= CSR BASE + 48) See mode regis-

ters 1A and 2A.

Status/Clock Select Register A - This register returns UART status information on a read, and selects the transmit and receive baud rates on a write.

WRITE:

]

Status/Clock Select Register A Format

C-40

VCBO1 Video Controller Module

Table C-15
Bits

Status/Clock Select Register A Bits
Access

<15:08>

Description
(Not used)

<07>

READ

Received break (1 = yes)

<06>
<05>
<04>
<03>

READ
READ
READ
READ

Framing error (1 = yes)
Parity error (1 = yes)
Overrun error (1 = yes)
Transmitter empty (1 = yes)

<()2>

READ

Transmitter ready (1 = yes)

<01>

READ

FIFO full (1 = ves)

<00>
<07:04>

READ
WRITE

Receiver ready (1 = yes)
Receiver clock select (1001 = 4800 baud)
Transmitter clock select (1001 = 4800 baud)

<03:00>

WRITE

Status/Clock Select Register B -~ (ADDRESS = CSR BASE + 50) See status/

clock select register A.

VCBO1 Video Controller Module

Command Register A - All the bits in this UART register are access-only.
06

04
§

Figure C-30

Table C-16
Bits

MIS COMMAND
1

| DTX | eTx | DRX | ERX

Command Register A Format

Command Register A Bits
Access

<15:08>

Description
(Not used)

<07>

WRITE

(Spare — must be zero)

<06:04>

WRITE

Miscellaneous commands:
000

NOP (no operation)

001

Reset mode register pointer (Causes the mode
register pointer to point to register 1.)

010
011

Reset receiver
Reset transmitter

100

Reset error status (Clears error status bits

101

Reset channel A break-change interrupt (Clears

<(07:04> in status/clock select register.)

interrupt status/mask register bit <02>.)

110

111

Start break
Stop break

<(3>

WRITE

Disable transmitter (1 = yes)

<02>

WRITE

Enable transmitter (1 = yes)

<01>

WRITE

Disable receiver (1 = yes)

<00>

WRITE

Enable receiver (1 = yes)

Command Register B -~ (ADDRESS = C5R BASE + 52) See command register A.

C-42

VCBO1 Video Controller Module

Transmit/Receive Buffer A -

Figure C-31

Table C-17

Transmit/Receive Buffer A Format

Transmit/Receive Buffer A Bits

Bits

Access

Description

<15:08>

(Not used)

Receive data
Transmit data

READ
WRITE

<07:00>
<07:00>

Transmit/Receive Buffer B — (ADDRESS = CSR BASE + 54) See transmit/
receive buffer A.

Interrupt Status/Mask Register — This register transfers interrupt status on a
read. On a write, set bits enable the UART interrupt request associated with the

Figure C-32

IPC

| CBB

| RBI

| TBI

| CRI

| CBA

Interrupt Status/Mask Register Format

)

00
4

corresponding status bit.

VCBO1 Video Controller Module

Table C-18
Bits

Interrupt Status/Mask Register Bits
Access

Description

<15:08>

(Not used)

<07>

READ

Input port change (1 = yes)

<06

READ

Change in break B (1 = yes)

<05>

READ

Receiver ready/FIFO full B (1 = yes)

<04>

READ

Transmitter ready B (1 = yes)

<03>

READ

Counter ready (1 = ves)

<02>

READ

Change in break A (1 = yes)

<01>

READ

Receiver ready/FIFO full A (1 = yes)

<00>

READ

Transmitter ready A (1 = yes)

<07:00=>

WRITE

Bit-for-bit mask to enable interrupt request associated

with the above status bits (00000010 = enable receiver
ready interrupt on channel A)

C.2.3

C.2.3.1

Programming

Cursor ~ The cursor image is stored in the cursor RAM and occupies

the upper 16 locations (32 bytes) of the VCBO1 address space (Figure C-20).

The cursor position is determined by the cursor X-position register (Paragraph
C.2.2.2) and the CRTC internal registers: cursor scan start, cursor scan end, and

cursor address high (Table C-7). These registers are loaded as follows.

1. The four Y-position LSBs determine where the cursor starts within a character
row, and are loaded into the CRTC cursor start register and cursor end register. Note that the cursor start register includes the cursor enable bit and the
cursor blink rate bit.

he next six Y-position bits determine in which character row the cursor starts.
hese bits are loaded into the CRTC cursor address high register.

After these registers have been loaded, the CRTC generates a cursor signal,
which starts a 16 scan line counter. This counter addresses the cursor RAM.
3. The cursor X-position is loaded into the cursor X-position register.
i

C-44

VCBO1 Video Controller Module

The minimum X- and Y-positions are zero. The maximum X-position is the last
pixel minus 16. The maximum Y-position is last scan minus 16. For best display
presentation, all cursor operations, such as loading position or changing the image,
should be performed when the cursor is off or during vertical retrace time.

Index
AC load,

1-14

INITIALIZE,

ACR (interrupt controller auto clear
register),

C-36

TEST,

fixed,

3-1

floating,

2-3
CRT (cathode-ray tube),

BBU (battery backup unit),

2-5, 2-7

1-12

CRTC,

1-9

1-17

line,

C-9

row,

C-9

time,

C-9

Blink rate,

C-44

CRT controller,

BPOK H,

1-17

horizontal
blanking,

CAS (column address strobe),

1-12

CD interconnect,
Character

C-14

C-9

retrace,

sync,

C-9

Hsync,

C-9

row,

C-9

vertical

time,

C-9

Console commands
BINARY LOAD and

UNLOAD,
BOOT,

A-2

A-3

COMMENT,

CONTINUE, A-4
DEPOSIT, A-4
EXAMINE,

FIND,

A-7

HALT,

A-8

blanking,

C-9

retrace,

C-9

sync,

C-9

Vsyne,

C-9

CSR (control and status
register),

A-6

C-9

1-1

C-4

character time,

line,

Components,

C-8

character

BEVENT
Enable,

A-8

UNJAM, A-8
CPU slot position,

3-1

BDCOK,

A-7

A-8

START,

Address

REPEAT,

CTS (clear-to-send),
Cursor
blink rate,
enable,

DC load,

2-9, 3-1

C-40

C-44

1-14

Index-1

Index

DIP (dual in-line package),
1-9
DMA (direct memory access), 2-2

DU (disk unit),

1-14

DUART (dual universal asynchronous
receiver/transmitter),

Dynamic RAM,

C-4

C-12

sync,

C-9, C-32

ICDR (interrupt controller data

FIFO (first-in-first-out stack,

6-34

Hsync (horizontal sync),

Icon,

silo),

C-9

HP (horizontal phase),

C-29, C-34

2-11

ICSR (interrupt controller

C-40

command/status

Fixed

address,

C-29, C-34
IMR (interrupt controller interrupt

3-1

disk drive

mask register),

Initialized bit values,

shipping carton part

number,
vector,

Interrupt controller

6-8

registers

3-1

Flexible circuit material,

6-14

Floating
address,

3-1

FRU (field replaceable unit)
part numbers,

6-3

Gbyte (gigabyte), C-27
GINT (groupinterrupt),
Grant continuity,
Graphics
subsystem,

C-29, C-34

C-29, C-35

IRR,

C-35, C-36

response memory,

interrupt,

C-38

polled,

1-12, 4-1

fixed,

C-39
[PR (internal processor

Halt Enable,

5-1

Horizontal

C-9

centering,

6-47

character time,
linearity,

6-31

phase,

6-34

retrace,

C-9

scan line,

C-9

C-39

rotating,

3-8

blanking,

C-38

priority mode

1-20

1-9
Hex (hexadecimal),

(-34

mode

H CENT (horizontal centering),

Index-2

ICDR,

ICSR,
3-1

vector,

tablet,

C-36

C-29

6-47

2-2

IRR (interrupt controller interrupt
response register),

C-35,

C-36
ISR (interrupt controller interrupt
service register),

C-9

C-36

Keyboard 1-23

LAN (local area network),

3-3

LIN (horizontal linearity),

6-44

LSB (least significant bit),

C-13

index

LTC (line-time clock),

Maximum current,

FRUs, 6-3

1-9

LUN (logical unit number),

table,

2-14

4-3

MCS (multinational character
set),

6-3

video cable,

2-11

wrist-strap,

6-18

PC (printed circuit),

1-9

PC (program counter),

2-4

Memory

A-4

Priority mode

fixed,

MSA (memory starting

address),

response memory,

C-39

PSL (processor status longword),

C-34

MMS (MicroVAX Maintenance
System),

C-39

rotating,

C-27

Puck,

A-4

3-8

5-9
Q22-Bus,

Mode

1-15

interrupt

fixed priority,

interrupt,
polled,

C-39

C-38

rotating priority,
Monitor (VR260),

Mouse,

dynamic, C-12
static, C-13, C-20
RAS (row address strobe),
C-14
Registers. See interrupt controller

C-38
C-39

1-22

1-23

Restart Enable,

board),

6-10

MS630 slot position,

2-8

MSA (memory starting address),

Mux (multiplexer),

(C-40

Stylus,

C-42

Test point

C-29

coordinate system,
nominal values,

6-18

3-8

+5 Vde,
bit descriptions,

A-7

2-13

C-14

NOP (no operation),

Rx (receive, receiver),

Static
electricity,

1-2, 2-13

device CSR address,

C-40

SLU (serial line unit),
1-2
SP (stack pointer), A-4

C-13

MSCP (mass storage control
protocol),

RTS (request-to-send),
2-9,

C-27

MSB (most significant bit),

1-9

RPB (restart parameter block),

MPCB (main printed circuit

C-12

C-4

PAL (programmable logic array),

1-12

+12 Vde,
1-12
TMSCP (tape mass storage control
protocol),

C-4

1-2

TOY (time-of-year) clock,

2-7

Tx (transmit, transmitter),

C-40

Part number
fixed-disk drive shipping
carton,

UART (universal asynchronous

receiver/transmitter),

C-4

Index-3

Index

VC (vertical centering),

C-34

VCBO1 video controller module,

Vector
fixed,

3-1

floating,

3-1

Vertical
blanking,

C-9

centering,

height,

6-48

6-34

linearity,

6-44

retrace,

C-9

sync,

C-9

VH (vertical height),
Video

6-34

cable part number,

2-11

controller module,

2-8

refresh,

C-12

VL (vertical linearity),

6-32

VMB (primary bootstrap
program), 2-4
VOLT SEL (voltage select)
switch,

1-17

Vsync (vertical sync),
Wrist-strap
part number,

Index-4

6-18

C-9, C-32

1.7, MR-14187; 1-8, MR-14031;
T, ML0-486-85; 1,1-1 MR-16836: 1-2, MR-14027: 1-3, MR-14028; 1-4, MR-14029; 1-5 Mf:z 14030; 1-6, MR-15792;
. MR-14 166
%H MR-14068; 1-12, MR-14034; 1-13, MR-] 4035 ; 1-14, MR-14036; 1-15, MR-142
1-9. MR-14032: 1-10. MR-1.
mm«&

I- 17, MR-14037; 3 18, MR-14038: 1-19, MR-16335; 1-20, MR-16448; 1-21, W‘m16254: 9.1, MR-14502; 2.2, MR 13827/14504; 2-3, %W

2.4, MR-16713: 2-5, MR-14714; 2-6, MR-15289; 2-7, MR-14044; 2-8, MR-14083; 3-1, MR-14072; 3-2, MW%”" ;iwi’i« MR-15244; 3
3-5, MR-16837; M‘;; MR-16357; 4-1, MR-15028: 4.2, MR-16838; 4-3, MR-16839; 4-4, MR-16840; Yn5-1, MR-15684
(‘E’
;
4, M MR-15688;5-5, MR-15689; 5-6, MR-15690; 5-7»,MR 15691; 6-1, MR-17006; 6-2, MK-14

5-12, MR-15224: 6-13, MR-15
h% MR-165671; m7 MR-14047/14048; 6-8, MR-14719; 6-9, MR-14713; 6-10, ME-15217; 6-11, %M W‘ fi?fi20,
6-21,
6-14, MR-14050; «é‘» M MR-14049; 6-16, MR-14051; 6-17, MR-14052; 6-18, MR-14053; 6-19, MR- MQ}‘M C-3, MR-16341:
:
MR-14635; (-4,
MR-14634;
(-2,
MR-14633;
2, MR-1635(; 6-23, MR-16340; %M MR-16344; 6-25, MR-16351; C-1,
m?
MR-14648; C-11, MR-14632; (-12, “‘«‘W MMZ‘:
C.5 MR-14641: (-6, MR-14640: C-7. MR-14360; C-8, MR-14638; C-9, MR-14352; (-10,
MR-14627;
-M
&M 13. MR- MM? C-14, MR-14564; C- M MR-09709; C-16, MR-14618; C- 17, MR-14617; C-18, MR-14628; MW MR-14240;
C-21, MR-14575; C-22, MR-14576; C-23, MR-14577; C-24, MR-14578; C-25, MR-14587; (-26, MR-14588; C-27. MR-14589; (-28, MR-14590;
-29, MR-1 m; C-30, MR-14592; C-31, MR-14593; C-32, MR-145%4.