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EK-CI780-TD-001

1983

206 pages

Original

16MB

Document:	CI780 Hardware Technical Description
Order Number:	EK-CI780-TD
Revision:	001
Pages:	206
Original Filename:	EK-CI780-TD-001_CI780_Hardware_Technical_Description_1983.pdf

OCR Text

El<-Cl780·TD-00l

Cl780 Hardware
Technical De~cription

PfeporA<'.I by EducoliOnal Servi<';'''''t;
of
DiQilOI [quiprnent Corpoi1Jtion

The informatinn in thi' document ;, sul'!CCt to dian!(c withnut n<1ticc
and shllllld not be .:on,trncd as a C<lmmitmcnt by Digital l'quipmcnt
(°<irr~iration. ();gital l'quip111cnt <"irpornti1rn ""umc' 1111 rc'P•':hibilil)
for an) errors that m;1y appcm m thb (h>cumcnt.

Primed in l.'.S.A

The m111uscrip1 for lhi~ book was created on a DIGITAi. Word
Proccssinjl System and, ~ia a translation pro2ram. ""s aulomaticall)
type~et on DIGITAl.'s DEC'sel lnlcgratcd Publishing Syslcm. Rook
production "·as done by Educational St•nkcs llt.»clop•llt'nt and
P11nlishin11 In Soulh Lawrence, MA.

The fnllowin11 arc tr:i(kmarb of l)ignal h1uipmu11 Corp.iration

~amaama

rn:c1ap.

DATATRff.\'I'

DICliS
DH.'wntcr
DIBOI
\1,\SSBliS

DH
rn·.Cmatc
lll·Cnct
:ih'.:
Ill'(\) 'tcm-10
l,lH 'SYSTI' ~1-cO

PDP

R~1inbtrn

RSTS

RS\

l '\llll s
\\\

P/OS

\\IS
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Pr~lfi.::-.~ii m.~ I

\\,'or~ J>nh:l'""l°'lilf

CONTENTS

<llAPTER I

INTRODl l(TION

l. l

1.4.4
1.4.5

MANUAL SCOPE............................................................................
.. .. 1-1
THE COMPUTER INTERCONNECT(CI)................ .....................
.... 1-1
RELATED IXX.'UMENTS..............................................................
... 1-3
THE Cl780 INTERFACE .............................................................................. 1-4
Link Module ............................................................................................. 1-6
Packet Buffer Module (PBl ......................................................................... 1-6
D<lla Path Module (DP) .............................................................................. I };
The Syncht'Jnous Backplane lntcrconn<'Ct Module (SBI)..................
.. 1-X
Cl780 Power .. .. .. .... .. ..... .. .. ... .. .... ..... .. .. .. .. .. .. .... .. .. ... .. .. .. .... ... . .. . ... .. .. . .. .... 1.-9

CHAPTER:?

UNKMODCLE

2.1
2.J I

PACKET FORMATS ....................................................................................... :!·!
Information Packet .................................................................................... 2-1
Bit Synchroni1.ation ............................................................................. 2-1
Character Synchroni141tion ... .. .. . .... .. .. .. ... .. . ... . ... ... .. . ... . ... . .. . ...... ... ... .... . 2· I
Pa1;kct Type/Length (High) ................................................................. ·.-2
Pa•k>!t Length (I.ow) ........................................................................... 2-2
Destinations (True and Complement) ................................................... 2-3
Sourcc ............................................................................................... 2-3
Body ................................................................................................ 2-3
Cyclici1l Redundancy Check (CRC) Bytes ............................................. 2-3
Trailer ............................................................................................... 2-3
Acknowledge/Negative Acknowledge (ACK/NACK) P•1ckc1 ........................ 2-3
LINK OVERVIEW ........................................................................................... 2-4
Information Packet Reception ..................................................................... 2-4
ACK/NACK Packet Transmission .............................................................. 2-6
Information Packet Tm nsmission ................................................................. 2-7
ACK/NACK Packet Reception ................................................................. 2-8
LINK OPERATING ST ATES ......................................................................... 2-8
I' :~·:·i0 JVE CHANNEL ..................................................................................... 2-8
CJ Carrier Detection and Pu th Selection ....................................................... 2-8
Carrier Detect Logic ........................................................................ 2-10
Receive Path Select. Mux - ECL Logic ................................................. 2-10
Manchester Dccodcr .................................................................................... 2-11
Phase Encoding .................................................................................. 2-11
cx.~coder Logic .. ...... ... ..... ....... .... .. .......... .. .. . ........................................ 2-11
Sync Character Detect Enable PAL .......................................................... 2-13
Byte Frnmcr............................................................................................ 2-13
RCVR CLK Generator .............................................................................. 2-16
CRC Check .............................................................................................. 2-1 7
Dc~t~n~lion Co_rnparc ., ............................................................................... 2-19
ACK Source Comparison...................
.. ........................................ 2-19
Rcci•ivc Data Parity and Ch<umcl Output............ .. .............. .. ................... 7-19
TRANSMIT CHANNEL..................................
......................... 2-19
Transmit Data Input...................................
.. ........... 2-19
Bit Sync, Sync Character, and Trailer Byte».
.. ........ :........ 2-21

I.~

lJ
1.4

1.4.1
1.4.2
l.4.3

2.1 I. I

2. i.1.2
2.1.1.3
2.1.1.4
2.1.1.5

2.1.1.6
2.1. J.7
2.1.1.8
2.1.1.9
2.1 2
2.1
2.2.I
2.~.'.!

2.2.3
2.2.4
~ .4
2.4.1
2.4.1. I
2.4.U
2.4.2
2.4.2.1
2.4.2.2
~.4.3

2.4.4

2.4.5
2.4.6

:!.4.7
~.4.8

2.4.9
2.~

25.1
~,:\.~

iii

2.5 ..U

ACK Packet lthcil> .... .
l'ac·kc1 Tvpc Byte ... .
Soun:c Byte .......
[lc,ti11:1tion Hvlcs ..

2.5.t

Dc~stination .\ddn~» Rcgi.>tcr.

~ >~-'.'
~.~.b

rrammit Data Pctrit\ Chcd ..
C!{C Gcncr,Hi<ln ... ·
XMll CLK CkncTat•Jr .......... ..
Parallel to &:rial Data Conversion
Manc-hcslcr hiKudcr ..
XMIT ECI. DriV<~rs .

_?.jJ

2.'- .< I
2.5 ..'i,2

~.5. 7

25.l)
2.:i.\I

2.5.10
2.6
~.h. I
2.6.2

2.7.1
~

2.9

2 Ill
2.10. l
:.lO.l.1

2.lO.U
2.JlU
2.I0.2.1

2.10.2.2

CRCGENERATOR AN!HflECKER .....
CRC G<:ncrator

CRC Checker .
ARBI TRAT IO"!
General .............. .
:\rbitrntion Logic
UJ\K FUNCTIONS.
LINK 1-JTERFACI' SIGNALS.
OPERATING STATl-'S ..
Message Tr::1Nnit ..
Tr:insmit O.int.ro! L,1gic.
Trans11·it StJtus .......... .
ACK Rc1;circ ......
ACK Rccdvc PAL Stak' .....
Svnc Character Dctcc; Fn:1blc PAI

~.HU

Message Rccc:vc ............. .

2.10.4

ACK Transmit..

CHAPTER :l

PACKET BUFFER MODI :u.

J. I
.1. l.I
J.1.2

DATA FLOW;GENFRAL DISCL•SSIOJ\
TBUF Load .

. U.3
l.l.4

3.1.'i
3.L6
~. l .7

:u.x

3.2
J.2.1

J ..: ..:.
3 2.J
.U
.UI

.u:
LU
:LU
.1.4

Tr:111s111it. .... .
TBLF Read .. ..
Valid RCVR [·ta .....
RBUr MLO:\i.1 (\fai111cr:ancc t.uadl ...
RBUF RL\lL ......

PB Read Mux

. 2.::
. ~~, .~

., :?.- 2

' ~--,
)'
......... "·-·
. "2-·~'.0
>

::..:()

">J.i/
' 2-:~9

.. 7 1 !
.. 2- \.'.
. '' ., ... ,,. ,., ...... 2-:111
'~~_,Jtj

. ~-.+)
2-4.l
. . 2.....~

.. - - .....~
!

..2-4'1
. . 2-4~1

. ~-:\!
..2.S:l
2-Sf)

... 3,, ~

-,. '-~ -3

. . :1- ,\
.. J-.\

.J 3

Control Logic........
. , ....... .
TBUF DAl A FLOW OPER.\flOi'<S ..

TBUF L<HD .. ..
TRANSMIT .. .

TBl 'F RFAD1Lm•rback1.
RBUF DATA FLO\\ Of'ERr\TIO'-'S .
V ,\l ID RCVR DXL\
R Bt;F MLO:\D I Maintcn:mc'~ Lr:.;;d) ...
RBLF Rc,1d,.

PB Rc,1d Mux
CLOCKS .

,.,

3.:i
."5.1

3.5.:
3.:d

3.5.4
J.5.5
.1.5.6

FUNCTION DECODER AND BUFFER SELECT I .OGIC ..
SEL LOAD BUF ................... .
SEL READ BUF ..................... .
LOAD BUF ....... .
LOAD LAST DATA BYTE .......... .
READBUF......
. ............ ..
TRANSMIT....
. ................ .

3.5.7

RSETTBUf

.l.5.X
3.5.9
.l.5.10
.l..5.11
3.5.12
3.6

RELEASE RBUF ... .
READ NODE ADR ..... .
READ XMIT STATUS .. ..
READ RCVR STATUS ....................... ..

................... .

Link Enable and Link Disable ................... ..
PB LOAD..................................
.. ...

3.7. I
3.7.2

SEQl :ENCJNG LCX.JIC ..................... .
TBUFLOAD........
..................... ..
TRAN MIT ................ .

.l.7.3

TBUF READ (Loopb:Kkl ............... .

3.7.S

VALID RCVR DATA.
RBUFMLOAD ................................ ..

J. !

3.7.6

38
.l.8.1
3.!U
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7

RBUF READ ................... ..
R CVR STATUS........................... .. ........... ..
CRC ERR ................ ..
RBUf /\ FULL, RBliF B FLLL. ....
RBUF B FIRST ........... .
RBUF A BUS ................... .

RBUF BBUS.
RCVR A ENABLE.
RCVR B ENABLE ........................... .

. ........... 3-10
.. ..........<-l ()
. ......HO
.... 3-l 0

...3-13
.. .... 3-13
... 3·!.1

.. 3-lJ
..... 3~ l 3

..3-U
.... .1·13
. .......... 3-14
... 1 -14
.. ... 3-14

.. ......... 3-! 5
.... 3-' s
1-i ~
.. J-17

3-1 7
.... 3-19

• ••.••.••••..••.••.. '"'0

.......... 3-19
.... 3-20
.. .... 3-20

l-20
......................... .l-22
""<•-•• . . .

.J-22
........ 3~22

.. ., ...... 3-12
3-22

CHAPTF:R4

CONTROL STORE

4.1

SIMPLIFIED BLOCK DIAGRA~f ..
MICROWORD PARITY......
.. ....

. .. 4-1
.. . .4·3

CSMICROWORD ..
Microword fields ........... ..
Mkroword Register.. ............. .

.... .4-6
..... 4-6

4.2
4.3

4.3 I
4.3.2
4.4
4.5
4.5. l

4.5.2
4.6
4.6. I
4.6.2
4.6.2. I
4.6.2.2
4.6.2.3
4.7
4.~

MAINTENANCE MUX ........... .
CONTROL STORE SPACE AND LOGIC

Contrnl Store Space ................ .

Control Store Logic ............................ ..
CO,"\TROL STORE ADDRESS SOURCE .... .

Maintenance Address Register ...
Mkroscqucnccr Logic.
291 I Micrnseq uencer.. ......... ..
Mirni>equenccr Control Logic ...
Branch Logic ......... .
MICROCODE START-UP ...
CLOCKS ............ ..

. .......... .4-6
. ......... 4-9

.... 4-9
.... .4~·9
..-HI
""'"'.4-13
. .. 4~; -~

.... 4-l 3
..4-) 3
.......... 4· !3

('HAPTER 5

DATA PATH MODULE

). I

5.8. I
5.X.2
5.8.3

OVERVIEW .........
DP BUSES AND PB IJ\TERFACE. . ..... . .
DP-to-PB Interface ...................... .
PB-to-DP Interface ..................... ..
L.ITERAL/PMCSR Mux .. ..
LS/VCDT ................................................ .
LS/VCDT Address Selection ......... ..
Write Control Logic ............................. ..
UNSOLICITED SB! REQUESTS ........... .
Unsolicited Write Sequence ....... ..
Unsolicited Read Sequence .................... .
CONTROL LOGIC ................................ .
BUS TB Dcstinatio'.' ..................................... ..
BUS IBSourcc ................................. ..
Control Signals ...................................... ..
DP PARITY GENER1'. TOR/CHECKER .... .
PB PAR ...................... .
Input Parity Error (!PE) ..
Local Store Parity Error (LSPE) ................. ..
XBOUT PAR HI andXBOLT PAR LO .... .
Receiver Buffer Parity Error (RBPE) ..
Parity Error (PE) .........
BOOT TIMER A ND MAINTENA"iCI~ TIMER. ... . .
290iA MICROPROCESSOR .......
Data Path ..................... .
Data Manipulation .......................... .
Carry Look-Ahead Logic .

CHAPTER6

SBJ MODULE

6.1

SB! OVERVIEW .....
Write Transfers ................. .
Read Transfers ..................... ..
PORT-INITIATEDTRANSFERS .................. .
.C:BI Extended Write Transfer ... .
SBI Extended Read Tran>fer.... .
UNSOLICITED SB! REQUESTS ... .
Unsolicited SB! Wriks .......... ..
Writing a DP Register.
.......... ..
Writing the Confilrnration Regiscn .
Unsolicited SB! Reads Reading•! DP Register ....
Reading the Configuration Register ...
INTERRUPT SU\fMARY REQUEST dSRi
INITIALIZATION AND RESTART L<..1GIC..
Start-Up Seque.ncc ......... ..
Power-Fail Sequence
Maintenance Mode ..

S.~

5.2.1
5.2.2
5.2 ..l

5.3.1

5.3.2
5.4
5.4.l
5.4.2

5.5

5.5. I
5.5.2
5.5.3
5.6
5.6. I
5.6.2
5.6.3
5.6.4
5.6.5
5.6.o
5.7
5.8

6.1.1
6. 1.2

6.2
6.2.l

6.2.2
/I.~

6.3.J
6. Jl.I
ld.1.2
(i.3.2
6.3.2.1

6..1.1.2
6 ..f

6.5
6.5. l
(i.5.~

6.5 . .1

.. S-l
.. ~-3
... 5-3
. ..... 5··.S

...... 5~ 7

..S-9
·'·! l
... 5-l 3

. .

... .

..5· l3
.. .... 5-Jt;
... 5-18
,, 5-1 ~

,, 5.. 20
.... )-23
., ... S-23
... S-23
.. 5-24
... 5-24

. ..... 5-24
.......... 5~25
...... _. ........ 5-25
.... 5-15
.. . . ......

5-30
... 5-31

.. ..... 6-1
......... 6-2
,,, .. 6-3
. ....... 6-4

.. '" ....... 6-4

...6·:
.... 6-l j
..... '6- l ~
....... 6-J 2
.6-14
.6-14
..... 6-J 6

.... 6· 16
..... 6·!['
,6-19
..... h-19

. 6-21
"' ........ 6··2.+

APPENDIX A

Cl780 MNEMONIC GLOSSARY ............................................................ A·I

APPENDIX B

FLOW DIAGRAM SYMBOLS ............................................................... B·I

APPE'\iDIX C

HARDWARE RFGISTERS ........................................................................ C·I

C.1

C'
C.3
C.4

MADR - Maintenance, \ddress Register ............................................................... C-1
MDATR - Maintenance Data Register ............................................................... C-2
PMCSR - Port Maintenance Contro;/Status Register ............................................ C-3
CNFGR - Configuration Register ......................................................................... C-4

FIGURES
1-1
1-2
1-3
1-4
1-5

Four-Node Cl Cluster .............................................................................................. 1-2
Cl780 Conncction .................................................................................................... 1-4
Cl780 Modules ..................................................................................... :.................. 1-5
Cl780 Block Diagram ............................................................................................ 1-7
Cl780 Power ......................................................................................................... 1-10

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2·28
2-29
2-30
2-31

Pocket Formats .................................................................................................... 2-2
Link Simplified Block Diagram .............................................................................. 2-5
Receive Channel Block Diagram ............................................................................ 2-9
Receive Path Select Mux-ECL Logic ................................................................... 2-10
PE (Phase Encoded) Data ...................................................................................... 2-1 I
Manchester Decoder Timing Diagram ..................................................................... 2-12
Byte Framer Block Diagram ................................................................................... 2-14
Enabling the RCVR Serial Shift Register ................................................................ 2-14
~ytc Framer Timing Diagram .............................................................................. 2-15
RCVR C :.K Generator .......................................................................................... 2-16
RCVR CLK Synchronizat;on. ... .. .. .... ... .. .............................................................. 2-18
Transmit Channel Block Diagram .......................................................................... 2-20
Sync/Trailer PROM Space .................................................................................... 2-22
XMIT CLK Generator Block Diagram ................................................................. 2-24
XMIT CLK Generator Timing Diagram ................................................................. 2-'.!S
Manchester Encoder Timing Diagram ..................................................................... 2-27
XMIT ECL Drivers ............................................................................................... 2-28
CRC Generator/Checker ....................................................................................... 2-30
Arbitration Flow Diagram .................................................................................... 2-32
Arbitration Block Diagram ..................................................................................... 2-33
Link Functions ...................................................................................................... '.!-37
Link Interface Signals ............................................................................................ 2-40
Interface Flow Diagram -Transmit Operation ......................................................... 2-41
Interface Flow Diagram - Receive Operation ........................................................ 2-42
Message Transmit State Logic ............................................................................... 2-44
Transmit Control Logic .......................................................................................... 2-46
Transmit Status ..................................................................................................... 2·48
AC" Receive State Logic ...................................................................................... 2-50
Sync Character Detect Enable PAL ..................................................................... 2-52
Message Receive State Logic .................................................................................. 2-54
ACK Transmit State Logic ..................................................................................... 2-57

vii

Packet Buffer Data Fiow ..
TBUF Operations.
RBUF Operations ......
Packet Buffer Clocks
Function Decoder and Buffer Select Logic
PH l.oad L•)gic. .......... .
TBUF Scyuencing Logic ... .
RHUF Sequencing Ll>gic ..... .
RCVR Status Logic .................................. ..
4-1
4-2

·H
4-4
4-6
4·- 7
4-X
4-9
4-10

•!-1 I
4-12
4 .. 13

5-1
:"<~

'
5.. 4
).

5-5
5-6
5-7
5-8

5-9
5-10
5-1 i
)-12

5-13
5-14
5-15
fl· I
h~· 2

li-3
() ... ~

(>-)

6-6

6-7
()-~

(1-9

11-10
6-l 1
h-1.'

6-U

Control Store Simplified Block Diagram .......... .
Control Store Block Diagram .. ..
Microword Parity Checker ............ .
Microword Fields ....................... ..
Control Store Space .......... ..
Control St(lrc Logic .............................. .
Control Store 1\ddrcss Multiplexing ... .
29 J I Micm•cqm.. ncer ......
Microseyucnn'r Control Logic ..
Branch Logic ....................... ..
Microcode Start-Up Flow Diagram ......
Microcode Start-Up Logic ....... .
\1icronxlc Start-Up Timing Diagram ........... .
Data Path Block Diagram .............................. ..
DP Buses and PB lntcrfacc.o......
.. ........... ..
LS/VCDT Block Diagram ....
LS/VCDT Address Scleciion Simplified Block Diagram ... ..
: S/VCDT Address Selection Blo<'k Diagram ...................... .
\Vrit.e RAM Timing Diagram ......... .
Un;,olkit~d SBl Write Request Flow lh1gram
Un>olicitcd SBI Read Request Flow D;c;gram.
Unsolicited SHI Request Logic ....... .
C..ini rol Logic .......

l\1rity Generator /Cncckl'r Logic ..
&xH Timer and Maintenance Tim.:r.
290 l A Micrnproccs:,or Simplified Bind. Diagram

2901 A Microprocessor Block Diagram ..
Carry l.. ook-Ahc:td Logic .....
SB! Module Block Diagnim
·wrik Transfer BL~ Diaernn;

Lxi.c·ndcd Write Flow Diagram.
Read Transfer Bloc:k Diagram ...
fa tended Read Fiow Diagram ..
Lnsolicitcd SBI Rcy11•"t Biock Gidgram .. ..
Umoli..:itcd SB! Write how Diagram ... .
Fns,ilicitcd SB! R~ad Flow Diagram ............ ..
!SR Block Diagr;\:lJ... .. "..
ISR Flow DiJgr:un ........ .
lnitiaiiut1on and Rc:.tart Logic.."
Start-Up Se4ucncc
l\1\1cr Fail Stquencc

,, . ., ....... 3-2
. . .... 3-4
.. .... 3-7
................ 3-9
.... 311
...... }-14
3·16
.. .. 3-18

.. ... 3<~ I
. .. 4-2
.4-4

.4-5
.. . .4-6
.. ........... 4-!0
...4-12
.. 4-14

.. .... 4-15
. ""'""'.4-16
............... 4-20
..4-23
.. 4-24

...... 4-25
•0•·••·5-2

..... 5-4
... 5-8
.. ...... 5-9
....... 5-10
... 5-12
"5-14
........ 5-15
. :i-16
5-17
S-22
.... 5-26
...... 5-27
..... 5-28
...S-J i
.6~2

........... 6-5
.. ,{\~6

. (•-8

..6·9
.... ,(J-i2
h- j -~
.. 'f.'1·· ! )
..... 6- '

• • • • • • • • ". '>

........ 6· 8
....... 6- 0
.. 6... {i~

B-1

Flo'' Diagram Symbols .......................................................................................... B-1

C-1

Maintenance Address Register (MADR) Bit Fields ............................ ., .................... C-1
Maintenance Data Register (MDATR) Bit Field ....................................................... C-2
Port Maintenance Control/Status Register (PMCSR) Bit Fields ............................... C-3
Configuration Register (CNFGR) Bit Fields ............................................................. C-4

('.)

C-3
C-4

TABLES

1-l

Cl780 Related Documents ...................................................................................... 1-3

2-1
2-2
2-3

Link State Diagrams ............................................................................................... 2-8
Link Clocks ........................................................................................................... 2-17
N Load Mux Selection ........................................................................................... 2-34

3-1
3-2

3.3

Link Control Codes Vs PB Function Commands ...................................................... 3-12
Load Buffer Select Code ........................................................................................ 3-12
R2ad Buffer Select Code ...................................................................................... 3-13

4-1
4-2
4-3
4-4

Microword Fields ................................................................................................... .4-7
Maintenance Mux Selection 1 ·ode ............................................................................ .4-9
Microsequcnccr Control Functions .......................................................................... 4-18
Branch Conditions ...................... ., ......................................................................... 4-21

5-1

5-2
5.3
5.4
5-5
5-6

PMCSR Bits ......................................................................... ., ................................ 5-6
LSA Mux Selection Code ....................................................................................... 5-11
IB DST Codes ..................................................................................................... 5-19
IB SRC Codes .................................................................................................... 5-20
ALU Source Code ................................................................................................. 5-29
ALU Function Code .............................................................................................. 5-30

C-1

CNFGR Bits .......................................................................................................... C-5

CHAPTER I
INTRODlJC1'10N

1.1

MANUAL SCOPE

'P1is document provides a technical description of the Cl780 computer imcrconnect hardware. It Jvc> not
treat the Cl780 port architecture or other software applications such as the Cl780 l"'rt dri,·er, command
queues, or the VAX/VMS opcrati11g system.
A basic description of the Cl780 rnmputcr intcn.onnect is given in this chapter. Chapti:rs 2, 3. 5 and 6
provide a detailed description of cacb of the four Cl780 moduies. Chapter 4 dcscrilxs the mi•:nicode control store and associated control logic. By describing the control store. its addressing logic. and its branching
logic in a separate chapter we can trcai it as a single cohesive function although the hardw· l'e is distributc'd
over two rnoduks (packet buffer and data path).
Three appendixes supplement the information contained in this manual. Appendix A define' the mncmon
ics found within this document. Appendix B explains the sym·oology used in the flow diagrams. Appendix ( ·
is ;; des.;ription of hardware registers used for maintenance purposes.

1.2 THE COMPUTER IN'fERCONNECT (Cl)
The computer interconnect (Cl) (Figure 1-1) is a high-speed, serial data bus tb»:t is used to link computer
subsystems (nodes) to form a Cl cluster. Typically, the dust.er is confined to a computer room environ·
mcnt. Nodes may consist of CPUs and memory. Nodes may also include intclli.gci;t mass storage, c:omrnunication, or d»1ta acquisition subsystems.
Features of the CJ include:
•
"'

•
•
•
•
•
•

Du·d signal paths c;ipable of simultaneous operation
70-mcgabit-per-sccond bandwidth and transfer rate
32-bit CRC generation and checking

Low error rate
Packet-oriented data transfers
lmmediatl'. acknowlcdgemc1't of' the reception of a packet
Contention arbitration at light loading ,ind round-robin arbitra1.ion at hcav1 loading
Internal and external d11:a looping for diagnostic purposes

F;1ch ;1odc within :.t duster connects to the computer interconnect via a C:J780 interface that pnvides two
scp;trat•' signal paths. D.1al paths provide a high degree of data a,·ailability between nodes. One pair c,f
nodes can c<1mmunica1e over one path (pillh A) while another pair of nodes commur,ic:-ites over the ;econd
path (path Bl.

Fadi path contains a central star rnuplcr tSC008) that r~ceivc' the d:11a trarJSmittcd
a n:)t'c :rnd distrib-·
ulcs it to lhe other node$ with;n the cluster. A single Cl p:Hh consist' of a pair
cabic' lnne for
lr,msmil, one for receive). These cable> provide 1he conn.:uion between a ·1ode and ci1c ,;;gnat d:s:.riburion
coupler (star c;:mpkn for that path.

l . 1}=
;.=1
1

I I
1

111 VAX
11

I !.
I ~~ I Ii
c1

n,.~, ii 780

I
VAX
11/780

i_rll

ST Mi

cou, ,rn A

t:-_----~:,
---i I II
R

,- - .I :: Jl I
J· i : ~._;_;..._:----'
ci

I . . - !- - · · - :

!_
.,..
_ _ _ _ _ __ , ,

"AR

i
COUPLER B
II R..._--'-~-'--:_~~~~~-'~_,_,
T
IT
__....___
~R
I
:
I Cl
I
! Cl

I 780

I v11x

1er 1 - L 7Wl

I I

1µ

780

'----..:.i_..J:r_ _J
figure 1-l

.___ __....,R

F1Jur-No<k Cl Cllm;:r

!-.?

VAX
! 11780

1.3 RELATED OOClJMENTS
fable 1-1 is a list of documents pro\'iding additional information related tu the Cl/80.
Table 1-1
flem

Cl780 Related Documents

Title

Documt•nt
Number

C/780 User's lluide

EK-·Cl780-UG

Contains instructiom for unpacking. i1 . stailing, and ,H.:cq1tan..:t: test·
ing the Cl780. A phv,;i<:ai dcscrip·
:ion of the Cl780 is also provided.
Information is :Jlso prov idc<l on tht·
Cl780 backplane jumpers.

SC008 Star Coupl.·r
User's Guide

EK-.SC008-LG

Contains a description of the SC008
Star Coupler. Also provides instrtic·
lions for unpacking and installing
the various Star Coupler
configurations.

VAX-I l /780 Power

EK-PS780-TD

Contains a 11.'.chnical des..:nption
(physical and functional) Df the
ti'.' !00 option power supply and the
H710L --5.2 Y regulator.

VAX Architecture
Hand hook

EB-!9580-20

Contains a description of the V A.X
family architecture. including data
representations. instructions. registers. and operational modes.

VAX llardwarl' Handbook

EB-21710-20

Provides a hardware 01·(~fVil!'w of
the YAX family. Hard1,.uc dl!'smptions include the l J /no, the
I l/750. ;md l l/730.

,\ystem Technical
Description
4

Contents

!.4 THE Cl780 INTERFACE
The Cl780 is the interface used to connect a VAX-11/780 system to the Cl cluster. It connects between
the synchronous backplane interconnect (SBI) cf the host system and the Cl cluster. Figure 1-2 illustrates
the Cl780 connection.
The Cl780 is an intelligent interface that performs the function of a buffered communications port. It
utilizes the queue structure provided under the VAX/VMS operating system to transfer messages and
blocks of data between the host's memory system and other nodes within thl~ Cl cluster. By providing data
buffering, address translation. and serial encoding and decoding, the CJ780 reduces the amount of over:iead software processing required to complete high-level intercomputer communications.
The Cl780 may be installed in any four-inch option slot in either the 1-19602-H SBI expansion cabinet or
the standard CPU cabinet of the host system. The Cl780 contains the following four modules functionally
connected as shown in Figure 1-3:
l.

2.
3.

Link Interface Module (ILi) LOIOO
Packet Buffer Module (IPB) LOIOI
Data Path Module (IDP) L0102
SB! Interface Module (ISi) LOI04

VAX

11/780

MEMORY
ADAPTER

al
{/)

UNIBUS
ADAPTER

MASSBUS
ADAPTER

h TX/RX A

Cl780

~µ

[TX/RX B

11
·-

STAR
COUPLER A
STAR
COUPLER B

T
TK..S15'1

Figure 1-2 Cl780 Connection
1-4

SBI

DATA
PA Hi
MODULE

f PACKET

INTERFACE
MODULE

L0104

L0102

L0101

BUFFER
MODULE

1----rx PATH A

LINK
INTERFACE---- RX f'ATH A
MODULE
- T X PATH B
LOlOO
RX PATH H

n<>a 1 so

Figure. Ll Cl780 Modules

Figun.~ 1-4 is a hJ,ick diagram of the Cl780. It should be used with the folklwing discu,sion of the Cl780
modules.

1.4.1 Link Module
The link module provides the interface to the Cl bus and has the c.ipability <lf scrvidng both Cl paths. Tlic
module is functionally divided into a transmit path and a receive path with a Cydit Redundancy ChccK
(CRC) function shared between the two dannels. The link .:an transmit or receive mw only one Cl path at
:i time due to the common CRC logic being used by both channels.

Data padcts arc received from th.: packet buffer (PBl module over the XMIT DATA HUS, and :ire
appended with hc:1dcr information and a trailer The header functions to identify the source and dc,tination
of the packet. Node address switches provide the node with an addrc's on the Cl cluster. The packet header
contains this address ;is a source idcntih;;ation. The traikr serves to keep the node receiver locked up ~hik
the last d;tla bytes in the packet are being processed.
The CRC logic uses the pac.ket data bytes to generate four CRC check bytes !hat arc appended to the data
packet. The CRC bytes arc unique for the specific data bytes in the packet. The bytes arc used for crrnr
checking at th.: packet <lcstination.
The link lransmittt:r converts the data packet from a byte format o a 70-megabit-pcr-s.:cond ;crial forrnat
and then applies it to a Manchester encoder.
The !\faw;hestcr encoder combines the serial data with the bit rate ckick to produce a modulated (phase
encoded) carrier for the Cl bus.
The path selection logic selects the Cl path (A or B) for the transmission. The path selection is under
rnicnx:odc control.

Carrier detection logic monitors <he two Cl paths and connects the: receiver channel to whichever path 1'
active.
The serial data frnm the Cl is applied to a Manchester decoder which sq,arntcs the signal into its cltx:k and
data comroncnts. The clock and data signal C(lmponcnts arc aprlicd 10 the link rc..:civ..:r.
The link receiver converts the packet data from a 70 megabit-pcr-serund serial f,,rniat w a byte forniat.

The link receiver then supplies the packet data to the CRC logic. The CRC logic validates the packet by
chcd.ing lhc packet data against the packet CRC bytes. If a C'RC error is detected. no response {ACK or
NACK) is returned to the transmitting node.

1r1hcrc isnoCRCcrror, lhc packet is sent to the PBmodulco\crthc RCVR DATA bus. If the PB module
..:an accept the packet, the link returns a positive acknowledgement (ACK) to the transmilting noc~. If the
buffers''° the PB module are full and cannot Jc..:cpt the padct. lhc link returns a NACK 10 the transmit·
ting node which will then retransmit the pttckct.
1.4.2 Packet Buffer Module (PB)
'(he PB module provides buffering for the data packet" tran;,fcrring thrnugh the Cl7XO. Two transmit and
lwo rccdve buffers (A and B) are provided. Each buffer has a l'.ap;1city of I K. When data packets are being
transmitted. tr;rnsmit buffer A is filled from the d<ito path (DP) rmKluk 1ncr the PORT DATA bus. The
ri<·xl data padct is loaded into buffer B while the link is unloading the data frnm buffer /\_

I ikcwis·~. received data rackets ilfl' loaded into receive buffer ,\ from the link module 1wcr the KCVR
I.MT'\ bus. The following data packet is loaded into rcccin: buffer B while the DP i•. unloading the data
from f<'.ccivc buffer A.

BUST
)(MIT
FILE

XMIT
BUFFERS

Rf'AD
CONTROL

PB OUT
REG
I

I
I

XMIT DATA BUS

B ill<)

Ell/CODER

'PORT DATA

PATH
SELECT

·1~··.

B (lK)

l1
Cl780 CONTROL
MICROWORD

BUS MD

I 1"v"
I
·

DATA

CARRIER
DETECT

~.
1B1N.1
\!:../
. .. I
DATA PATH

Siii

Figure IA

Cl780 Block f>i:1gram

].)

PACKET BUFFER

I r-<J-

,1~

A (11<1

FILE

--L>-}Cl·A

HEADER/
TRAILER

RCVR
BUFFERS
RECEIVE

MANCH.

LINK

I
i

I
I

The Cl780 microcode resides in <1 :lK RAM/PROM control store located on the PB module. The control
store RAM/PROM outputs a 47-bit mkroword that controls and rcguJatcs operations throughout the
Cl780. Stepping of the microcode is controlled by a microscqurnccr which samples the next address field
of the microword The micnx,odc i' also subject to branching conditions via branching !ogle located in the
DP module. The branching logic tests various conditions throughout the Cl780. The test results arc ORcd
with the miffOSt'qucnccr output to provide branching <lf the microcode sequences.
The Cl780 control microw<)rd can be read by the host system via the BUS MD in the DP module.
Under certain 1.xmditions (system initialization or detection of an error) the host system can force a routine
by inputting the starting addrc~s via the DP IB IN bus and the maintenance address register.
1.4.3 Data Path Module (DP)
Convcrsicm 1>f data packet~ from longword w byte format and from byte tu longword format is accom·
plishcd on the DP module. Dal<! to be transmitted is input into a 32-bit PB OUT register from the IB IN
btts (internal bus). in longword format. The PB OUT register is unloaded onto the PORT DA TA bus a byte
nt a time.

Likewise, received data bytes from the PR module arc input into a 32-bit PB IN register from the PORT
DATA bus. When four bytes have been loaded into the register, the register outputs the 32-bit longword
onto the MD (mi:;ccllancous data) bus.
The DP module contains LS (local store) and VC[)T (virtual drcuit descriptor table) storage areas. The LS
is a 256 >< 32 RAM area used to store software status blocks and software registers associated with the
CJ780 port architecture. The VCDT is a 256 >< 16 RAM area used to store Cl node parameters.
Al~,, contained •)O the DP module is a 290 I A ALU used to pcrfo;·m general purpose arithmetic and logical
OJ1Crati(lrlS.

The d;lla interface between lhc DP and the SBI m<ldulc is the BUS IB bus. Data input to the DP on the
BUS lfl. h;is scvcnll possible destinations. It may be applied to the LS or the VCDT for storage, to the
ALU f1ir prnccst-ing, or to the PB OUT rcgist.cr for transfer to the PB module.
Out.rut d.na frnm the DP on the BUS IB. may be obtainc(! from several sources. 11 may tx' data read from
th<' l. S or th<; VCPT ;m:a. it may be data obtained frnm the ALU after processing, or il may be data
obtained frc\111 the HUS MD. Data from the BUS MD may be fro;n th1'. PB IN register or it may be the
Cl780 control rmcrnword read from the '"J11trol store in ihc PB module.
lfa: dtstination and sourCL~ or the BUS IB d~la 1s seh:cwd by the Cl780 mic'.rocode.
1.4.4 Thi: Synchronous Backplane lnterconneca Module (SBI)
The basic function of the SBI module b to interface with the SBI. All SBI protocoi and timing must b:;
ob'<,rvcd while tr:msfcrring dnta to and from the SB!. A transmit and a receive file act as isolation buffers.
fhc SBI sid<: of the files arc loaded and unbaded under SRI timing and control while the DP siJe of the
files arc loaded and unloaded under Cl780 microcode control.

!.>at.a rcc:cived fnm1 the DP over the BUS IB is loaded into the transmit file by the microcode. Up tu two
extended writ<' transfers of data can be stored in the l'ilc. The micrtxodc informs the read control th:u data
i> available 111 the fik~. The: read control arbitrat.es for the SBJ, receives and supplies information fields as
requirc1t by SB: protocol, and unlo.id.'> (reads) the dala in the transmit fik out to the SB! over the Bl;S T
bus.

I-~

Data rcc·civcd from i.hc SRI is loaded into the receive file by the write control. Up to two extended read
1ran:.;fcr;; 11f da1:1 can be ston:d 111 the file. Th•: write control receives and supplies the information fields
required by SBI ilrotocol and then loads (writes) the SBI data into the file over the RB bus. The write
control informs !he CJ780 rnicrowde that data is available in the file. The microcode unloads the data
Jn ·n the recciv~ fik 1into the BUS IB for transfer to the DP module.
The SRI module provides for CPU :.iccess of Cl780 registers via unsolicited SBi requests. Both reads ,ind
11Titcs of the registers can be performed.

The SBI module also requests interrupts of the CPU when servic~ routines arc run on the Cl780.
1.45 · !780 1'11111·er
Power 's supplied w the Cf 780 frnm an H71 (l0 option power supply with an H7I01, -·5.2 V regulator. The
supply receives 120 V, 60 Hz from a switched outlet on the 869 power c<.mtroller located in the cabinet.
The supply provides +5.0 V to the four Cl780 modultcs, and -5.2 V to the link and Sl31 modules. The
supply abo provides ACLO and tX:LO to the SBI module.
Power signals and voltages pass frnm the power supply to the Cl780 modules via the Cl780 backplane.
Figure I ·5 illustrates the routing of tht~ power signals and voltages

1-9

SBI

MODULE

,..--f-0 SUPPLY ACLO

y--i-<> SUPPLY DCLO

I
I

-5.2 v

RET +5.0 v

G~~""
,,, r

f
''

I +

_, !J Q \I

RET

L~Nr'.

?B
MODUU:

~.~c::'.

+•J.~

Q
i

~ ~

.::·E-:

·:::·I

Q
1

'. ~·~·--+-,-·--~

--+-+--a~::-B'T---+-------

FROM SWITCHED
~
( OUTLET IN CABINET
.
l20 V. 60 Hz
1
,AC POWER CONTROLLER ,
.I

i H7100 POWER SUPPLY

I(WITH H7101 -5.~ v REGULATOR)
Figure 1-5

Cl780 Power

CHAPTER2
LINKMODUtE

NOTE
The functional block diagrams in Chap Ier 2 use logical AND 1md OR symbols. It does not. necessarily
follow that a corresponding gate exists on the link
logic prints. The assertion of input~ A and B causing
the assertion of output (' may be reprcsl'nted on a
block diagram by a single AND gate, )'el the engineering drawing may show that several circuit stages
are involved in the ANDing operation.
The functional block diagrams in this chaptt>r are
keyed to the link engineering drcuit schematics (CS
prints) by letter designations in parentheses. Thi' let·
ters specify the li11k CS sheet that cont11ins the
d('tailed logk associated with the functional blocks
in the diagram.
The signal names used in !he functional block diagrams are the 11amcs used on the engineering CS
prints. Where ofoer ~ignal names or notes are used,
they are enclosed in parentheses.

2.J PACKET FORMATS
Formats of the two types of pad;cts, information and ACK/NACK (;1cknowlcdgc/ncgatwc acknowkdgc),

.ire 1Jc,cribcd below
2. I.I

Information Packet

Figure 2· I A illustn1tcs the format of an information packet The information packet is used to transmit
bo:h messages ;ind data across the CL Parts •Jf the packet arc generated hy the link and inscrtl'd into the
packet as it pa'"'' through the link to be transmitted.
2.1.1, I Bit Synchronization - The first five bytes of the packet ;:re for bit synchromzation within the
link. The hytcs arc 5~ hexadecimal whi<'h is an ah~,,rnatin!,! pattern r•f I's and O's used to turn on the carrier

detect circuits and lo synchronize the f\1anrhc:;;lt:- decoder pr:or h> the receipt of us~fuJ dabt. The link
inserts the hit ~ync bytes into the packet.
2.1.L2 Chat1H'ler Synchronizarion - The character synchroni1ation b;·ti: (% hexadecimal) is u>cd w
indicate the .>l.lrt of u~cful dat;1 in the pa,;kcL \Vhcn the ~ync charact('r is r<.0<:<Jgnizcd during packd rccepti<JJ1. it s1,.• rts the framing or the S<'rial d.na into eight-bit bytes. Thl· link insert<, the S\'!K charact1~r into the
pack rt

OR USED
BY L!NK

SEE NEXT FHAME

TAAi LER 100 HE Xi

[

TRAILER (00 HEXI

FOR LARGER ART

TRAlllR (00 HEX)
· - - - - l
TRAILER 100 HEX)

TRAILER 100 HEXJ

ACK/NACK PACKET

A. INFIJRMATION PACKET

Figure 1-1

Packet Ftmnats

2.1.U Packet Type/Length (High)-The packet type and length (high) byte specifics the type of pa·~kct
(information or acknowledge) and contains the upper four bits of a 12-bit packet length word. Bits (7:4) arc
the packet type bits. For an information packet bit 7 is a 0 (I for an ACK/NACK packet) and bits (6:4)
arc O'•;.

Bits (3:0) are the upper four bits of the !2-bit word that specifies the packet length. Information packets
,m: ')f variable length in one-byte increment.•. :1p lo I K bytes* with the minimum packet length being seven
byte,. The packet length specified by the 12-1-iit p:1ckct kngth word includes all data from the packet type
and length (high) byte up to and including the lasi byte of the body.
The port processor supplies the packet type and length I high) byte as ran of the pa-:kct.
2.1.J .4 Packet Lenj!th (to"'') - This byte contains the low eight bitsof the 12-bit packet length word. The
port pro<:cssor stipplics this byte as part of the packet.

2--2

0
FIRST BYTE
TRANSMITTED

BIT SYNC (55 HEX)
GENERATED)
( OR USED
BY LINK .

{

LOADED OR
)
( READ BY PORT
PROCESSOR

BIT SYNC (55 HEX)

CHAR SYNC (96 HEX)

PACKET TYPE/LENGTH (HIGH)

PACKET LENGTH (LOW)

DESTINATION (TRUE)

DESTINATION (COMPLEMENT)

SOURCE

>"!

GENERATED)
( OR USED
<
BY LINK

FIRST BYTE
TRANSMITTED

BIT SYNC (55 HEX)

BODY

CRC·O

CRC·l

CRC-1

CRC-2

CRC·2

CRC·3

CRC-3

TRAILER (00 HEX)

TrlAILER (00 HEX)

TRAILER (00 HEX)

TRAILER (00 HEi<)

TRAILER (00 HEX)

\,.

B. ACK/NACK PACKET
A. INFORMATION PACKET
Ti<.·8599

figure 2-1

Packet formats

2·2

2.1.1.5 Destination (True and Complement) - The destination is the eight-bit address of the Cl node lo
which the packet is transmitted. There are two destin,ttion bytes: the first being the true node address value
and the second being the complement of the true value. The port processor supplies the destination bytes as
part of th~ packel.
Redundant destination addresses are used h> preclude a single logic failure bringing down both paths on the
Cl bus. With a single address decode circuit, a failure which caused a node to decode another node's
address might result in both node• transmitting an acknowledge packet at the same time. This would result
in a collision on the Cl bus and would be seen as a "no response'' by the trans mi Hing node.

2.1.l.6 Source - The source is the eight-bit ,~ddress of the sending node and is provided by the port processor as part of the packi;L
2.1.1.7 Body -The body contains the data and port-processed protocol information. The body is supplied
by the port as part of the packet.
2.1.t.8 Cyclical Redundancy Check (CRC) Bytes- Foilowing the body are four CRC bytes generated by
the CRC k1gic in the link. During a packet transmission. the packet [starting with the pac;kct type and
length (high) byte], is input into the CRC logic which generates the coefficients of a CRC polynomial. The
coefficients arc expressed as a 32-bit longword that is a function of the packet data. Each CRC word is
unique for the specific packet that generated it.
During packet reception, the CRC longword is regenerated and compared to the four CRC bytes generated
during the transmission. An error-free packet results in a ma.tch between the two longwords.
2.1.1.9 Trailer - The trailer consists of six bvtes of al.I O's. It is u~ed to insure that all bits of a rct·eivcd
packet have been shifted through the link froni end before 1hc carrier detl~Ct logic senses the end of packet
reception. The link inserL~ the trailer into the packcl.
2.1.2 Acknowledge/Negative Acknowledge (ACK/NACK) Packet
Figure 2-1 B illustrates the format of ACK and NACK packets. ACK and NACK packets arc sent by the
receiving node to inform the transmitting node that the packet arrived without data loss or bus collision
(CRC checked OK).
If the receiving node successfully accepted the packet into the buffers on the PB. an ACK packet is
returned indicating a successful bus transaction and storage in the PR If the receiver buffers in the PB
were full and. therefore. unable to accept the packet, a negative: acknowledge (NACK) packet is sent to
inform the transmitting node that the packet was smxccssfully received but could not be accepted. The
transmiuing node must then retransmit the packet.
The cmirc ACK (or NACKl packet is generated and transmitted by the link.

An ACK/NACK packet differs from an information packet in the following three ways:
A.

It has no body. An ACK/NACK packet only acknowledges reception of an information packet.
It docs not transfer messages or data as such.

It has no packet length word. Al! ACK and NACK packets are the same length. Consequently
bits (3:0) of the packet type and length (high) byte arc O's and there is no packet length (low)
byte.

The packet type bits (bits (7:4)) of the packet type and length \high) byte s~·cifi...; the type of
packet as follows:
Bit 7 ~· 1 indicating an ACK/NACK packet (0 for an information packet)
Bit 6 = I for an ACK packet
0 for an NACK packet.

2.2 UNI(. OVERVIEW
The link (Figure 2-2) is functionally divided into a receive channel and a transmit channel with a CRC
fun..:tion shared between the two. The overview bricny describes the following four link operations with the
transmit and receive channels functioning as they would for the specific type of packet being processed.
The operations are described as they would occur with B following A and D following C.

A.
B.
C.
D.

The reception of an information packet
The transmis.'iion of an ACK/NACK packet
The tran~mis.-;ion of an information packet
The reception of an ACK/NACK packet

Link control logic receives commands from the port to select and start link operations, and senses signal
conditions to control the transfer of d<1ta packets through the link. A receive clock (RCVR CLK) and a
transmit clock (XMIT CLK) arc generated on the link to time operations in their respective channels.
2.2.1 Information Packet Reception
Data packets on the Cl bus arc in serial format at a serial bit rat.e of 70 MHz. The data is Manchester
encoded (phase encoded) wherein the clock is incorpor:ited into the modulated signal.

CJ paths i\ and B arc input to a RCVR sc:lcct multiplexer (mux) in the link front end. Carrier detect logic
monitors both CI paths. When the logic Sl.">scs the initial presence of a carrier on om~ of the paths and if
that path has been enabled by the port, it switches the mux to the active path, selecting CIA RCVR or CIB
RCVR for the Manchester decoder. The port may also select the internal loop path wherein the mux sclecl<;
the output from the transmit channel and loops it back into the port. This feature is used for maintenance
operations.
The mux out.put is applied to a Manchester decoder where the signal dock is extracted from the modulated
signal. The Manchester decoder outputs the data (RCVR SERIAL DATA) and the dock (MDECODER
Cl...<X:K) to the byte framer. The byte framer contains the sync character detector.

2·4

SYNC/
TRAILER
PROM

XMIT
(FROM PB)

XMIT DATA <7:0>_

~N~~~

XMIT DATA BUS <7:0>

•

LATCH

ACK
RCVR BUFFERS FULL
{FROM PB) _...:.;..;;...:..;..;....;:,..;.___;...:_
_ _"' TYPE
LOGIC

__.

ACK
SOURCE
LOGIC

ACK
DESTINATION
LOGIC

XMITSERIAL
DATA
XMIT
SERIAL
MANCHESTER ME DATA
SHIFT
ENCODER
XMITC~
FEG

g~~ERATORl-

- --- - ---- - ---to- - ~t----1- r'° g~~CKER
- -+--- - ---L...,

{TO PBl

XMIT
DATA
REG

BUS
TDATA
<7:0>

CRC STATUS""""

r-·----<

XMIT
PATH
SELECT
LOGIC

-}(~?'",)

CIA XMIT
CIB XMIT

TRANSMIT CHANNEL
(FIG. 2-12)

(TO MESSAGE-~\
RECEIVE STATE)
LOGIC AND PB

- -+-- - ---RECEIVE CHANNEL
{FIG. 2·3)

ACK
SOURCE
COMPARE

t-+ DESTINATION

NODE

~~l~~;i~~ 1--_,__ _...--~lcOMPARE

ME
/1-----DATA
- - - - - . RCVR SERIAL DATA------.
RCVR
RCVR DATA <7:0> RCVR
ROAT <7:0>
MANCHESTER~ PATH
{TO P B ) - - - - - - - - - - - - 1 OUTPUT S.1-t-....,__ _ _ _ _ __...-t BYTE
FRAMER
MDECODER CLOCK DECODER
SEL
REG.
MUX
lSYNC

'""RCVR CLK

RCVR
CLK
GEN.

CIA RCVR }
CIB RCVR

~CARRIER
PET~T/
L

(FROM )
Cl BUS

MUXSELECT
LOGIC

TK-8620

Figure 2·2 Link Simplified Block Diagram

2-5

The byte framer performs serial to parallel convcrsi<m of the signal data. The framer is enabled by the 'ync
character detector which activates the framer when it recognizes the sync character. When enabled. the
byte framer ouputs a data byte (RDAT (7:0)) for every eight M;rial bits received from the Manchester
decoder. /\ RCVR CLK generator develops RCVR CLK which times the transfer of data through the link
receive channel. SYNC from the byte framer synchronizes RCVR CLK with the data bytes so as to occur
approximately centered on the asserted time period of ROAT (7:0).
The RD/\ T (7:0) data bytes arc coupled to the RCVR output register and then to the PB as RC:VR DAT/\

c '.") .

The link verifies that the packet is meant for this node by comp;•ring the packet destination bytes to the
node address set into the node address switches. The compari~ion is made in the destination compare logic.
If a match i~ not obtained, the receiver is cleared and reception is terminated.
The packet source byte is extracted from the incoming packet and placed into the /\CK destination rcgio,tcr. When the link transmi.ts an ACK packet in response to the information packet now being received. it
will use the addre:;s ia the register (the source of the information packet) as the ACK destination.
The packet bytes extending from the packcl type and length (high) byte up to and including the last byte of
the body, ~re applied t<J the CRC checker. The bytes ;ire acted on by the CRC algorithm which generates
the 32-bit CRC longword. The four CRC bytes in the. packet arc compared lo the generated longword and
if the packet is free of error, CRC STATUS is asserted to message receive logic.
After the packet trailer has passed through the link front encl. thl· carrier detect 1,1gic senses the end of the
packet and informs the ACK transmit logic. The ACK transmit logic then initiates the transmission of an
ACK packet.

2.2.2 ACK/NACK Packet Tninsmission
An ACK/NACK packet is generated and transmitted entirely by the link. No packet data is received from
the PB as XMIT DAT A (7:0).
The link ACK traosmit logic initiates the transmit operation by enabling the sync/trailer PROM which
1lutputs fil'c bit-sync by!cs and a sync character byte onto the XMIT DATA bus (XMIT DATA BUS
(7:0)).

The ACK type logic is then enabled and outputs the packet type byte onto the XMIT DA TA bus. The
logic sampled the state of PB signal RCVR BUFFERS FULL at the start of the information packet recep·
tion. If RCVR BUFFERS FULL was true. the PB was not able to accept the information pa.:kct just
rccciv•:d. In this case, the ACK type logi<; outputs the code for a NACK packet. If RCVR BUFFERS
FULL was false, the logic outputs the code for an ACK type p<1ckct.
The link control logic then cnabb the output or the ACK destination register which outputs the two destination bvtc;; onto the XMIT DAT A bus. The destination value used is the source address taken from the
information packet just received.
The ACK source logk is then enabled and transfers the node address from the node address switches to the
XMIT DATA bus as the source byte.

2-(•

The ACK/NACK packet is transferred to the BUS TDA T/\ bus via the XMIT data register. The packet.
starting with the packet type byte. ha,; also been input into the CRC generator where a .U-bit CRC longword is generated. After the source byte has been input to the CRC generator. the link contrnl gates the
CRC longword onto the BUS TDA TA bus a byte at a time. The four CRC bytes arc thus inserted into the
ACK/NACK packet.
Finally. the ACK transmit logic re-~nablcs the ~ync/trailcr PROM which outputs six trailer byte' onto the
XMIT DATA bus to complete the ACK/NACK packet.
The ACK/NACK packet on the BUS TDATA bus is applied to the XMIT serial shift register which
performs parallel to serial conversion of the signal data. Data bytes are input to the register and then shifted
out serially to the Manchester encoder as XMIT SERIAL DAT A. The bit rate of the serial data is 70
MHz. The register logic also generates XMIT CLK which times the transfer of data throug:-, lhl' link transmit channel. XMJT CLK is synchronized with the serial data within the shift register.
The XMIT SERIAL DATA is applied to the Manchester encoder where the bit rate dock is combined
witli the serial data to produce a phase-encoded carrier. The Manchester t'ncoder outputs the modulated
carrier (ME DATA) to the Cl bus. The ACK transmit logic selects the same Cl path used by the information packet just received. The ME DA TA can also follow an internal loop path into the receive channel if
the link is in internal loop mode an-i the receiver inputs from the Cl bu~ are disabled. This feature is used
for maintenance testing.
2.2.3 Information Packet Transmission
An information packet is mostly generated by the port and input to the link transmit channel from the PB.
The information packet bytes that are inserted by the link arc:
/\.
B.
C
D.

The five-bit sync bytes
The character sync byte
The four CRC bytes
The six trailer bytes.

Transfer of an information packet utilize> only some of the functions de>cribcd in Paragraph 2.2.2. The
functions that arc used operate a;; previously described.
The port initiates the 1ransmit operation via the message transmit illgic. When the transmit operation is
initwtcd, the link enables the sync/trailer PROM which outputs five bit sync bytes and a sync character
byte ontu the XMIT DATA bus.

The packet type and length (high) byte and the pa.::kct length (low) byte are provided hy the port.
The destination bytes arc also provided by the rort When the destination bytes arc on the XMIT DATA
bus the link enters the de;tination addre:-s into the ACK sourc<: conip~!rc lngic. When the ACK/NACK
response packet is received from the target node. the packet sourc'<: byk is compared with the contents of
the compare logic. If the corrr.ct node rc>pondcd, a mat,:h "iii b, obwincd.
The source byte is im.ertcd by the PB, not by the link. Tht' addn>s;; source is the link node switches which
output the node address to th1: PB. The source byte. then, is <tn inpllt to th~ XMIT D/\ TA bus from the PB.
The CRC generator functions to produce th~ four CRC bytes just as for an 1\CK/ NACK transmission.
HowcvcL the information packet has a body which is also input to the CRC generator and contributes to
the generation of the CRC longword
Finally. the link message tran;111it logic re-enables the sym:/trailcr PROM which outpub the six trailer
bytes onto the XM!T [),\TA bus lO l'Omplctc the informatinn packet.

~-7

2.2.4 ACK/NACK Packet Reception
Transfer of an ACK/NACK through the receive channel utilizes most of the functions described in
Paragraph 2.2. 1, Information Packet Reception. The functions also operate as previously described.
With regard to the link receive channel, the basic difference between the reception of an ACK/NACK
packet and an information packet is in the handling of the packet source byte. The source byte is not
entered into the ACK destination register but is applied to the ACK/NACK source compare logic. The
source compare logic presently contains the destination address of the information packet just transmitted.
The source byte is compared to the destination address. The address will match if the correct nodes arc
involved in the data transfer.
2.3 LINK OPERATING STATES
Paragraphs 2.4 and 2.5 provide a detailed description of the operation of the receive channel and transmit
channel hardware. Control of the hardware is a function of commands from the port, the type of operation
being executed, and conditions sensed by the logic (e.g. "rrors) during the operation. Hardware control is
implemented via programmable array logic (PALs) which define various hardware states during each
operation. The states are represented in four diagrams contained in the engineering drawing set. The operations described by the diagrams are shown in Table 2-1 and described in Paragraph 2.10.
Table 2-1 Link State Diagrams
Operation

Number of States

Information Packet Reception

ACK Packet Transmission

Information Packet Transmission

ACK Packet Reception

2.4 RECEIVE CHANNEL
Figure 2-3 is a block diagram of the recei 1e channel and ,,hould be referred to throughout Section 2.4.
The receive channel hardware contains be th transistor-transistor (TTL) logic and open collector emitter
C"Upled logic (ECL). The carrier detection/path selection logic, Manchester decoder, byte framer. and
sync character detector all use ECL logic. ECL has an active high and nor.-active low state on common
lines resulting in a different interpretation of circuit logic than with TTL. A description of the receive path
select mux is given Paragraph 2.4.1.2 as an example for those unfamiliar with ECL logic.
2.4.1 Cl Carrier Detection and Path Selection
The carrier detect and path select logic monitors activity on the Cl bus and, when activity is detected,
selects the active path as an input to the link receive channel. The port uses port and link control PALs to
specify which receive channel(s) are allowed to receive signal inputs from the CI bus. The PALs enable the
receive channel(s) by asserting RCVR A ENABLE or RCVR B ENABLE.

2-8

(FIG. 2,12)

,---"'---,

\FIG.220)

..,

ACK SOURCE CMP

l---------~--------------- ~(FIG 2 27)

1J
1-l-----...I-.,. (FIG. 2301

r---1
CRC
CHECKER

COMPLHMoNT
NODE ADR SW

CRCSTATUS

L~12:.2~_J

(K)

1~---------------__,~
I

MDECODER

CLOCK

RCVR
SERIAL
DATA
ROAT

<7:0>

BYTE
FRAMER
(FIG 2 7)

RCVR
DATA
PARITY

c
'RCVR D;
DATA
PARITY
FF

IF)

RCVR CLK

Ci EN

IF!

!SYNC

~~~R~(FIG228;2'.i01
GENERATOR
iFIG210)

RCVR
DATA
PARITY

hgurc 2·3

ENA SYNC

!FIG. 33)

VALID RCVR PARITY 1· F..IG. ')

Receive Channd Block Diagram la)

2 21

EXTSYNC
IFIC 225)

NOH:
LETTER DESIGNATIONS IN PARENTHESES
RHrn TO ENGINEERING DPAWl!llGS
CONTAINING CORRESPONDEIN(i LOGIC.

(flG. 2 28:230.!
[, ;-------------_:D:::S::_:T:._C::::M:.::_PL_ _ __

MR STATED

Dt-~~---+-------DECODER
FF

~--A_R_S_T_'A_T_E_·F_ _iF-·l_G_.2 :-lO)

I
I

;FIG.2281

l-!-1-1_c:M_;;.E;...:DATA
2 ·1.2)
- - - , d ( J. .

(S)

CIA
RCVR

~.
}/FROM.\
RC /R
,c1 BUS I

10.7 NS

RCVR PATH SEL 8
RCVR PATH SELA

r-:.Ase;

ir-

FND + H10

ENA SYNC..------.
SYNC CHAR
~T
DETECT

CARRIER
DETECT
A
(Sl

ENABLE
PAL

CARRIER
DETECT
B
(Si

(FIG.229)
- - - - lCCS Pt-\ TH

SET

8 CDET
Cl!------.,!

()

CAR
DET 8
FF

(J}

c!~T D
DET

A
FF
ISi

RCVR
CLK
C ..,..._ _ __...._

RCVR A ENABLE

11CVR B ENABLE

~==_E~~-;,\-~-~OP~==--Figure 2·3

Rc<.:civc Chunncl Block Diagr;im (h)

·--------~

~--"_1c_v_R_·_B_E_:~;_'A_B_L.:_.E.:_._ ..
MX '.]TA.TE A

-=} /(~.
"F

:•.;' 1!

t-----_::_-·--- ..~- 'F JG 2 '.?C1~

2.4.1.l Carrier Dt'tect Loi:ic - IJcnticd and parallel logic llh'niturs paths .\ and B. If a c1rrk•r is present
on Cl p;1th A. the carrier dctccl A logic: ,e:;, the ,:;1rricr dc11:.:t A flip-f' ;p. tr the port has enabled ch.1nnd :\
<RCVR 1\ ENABLE trucl. ICCS f',\Tll A CDET <l"crts and cause,; Ci\RRIER DFT A t11 be asserted b\
a flip-llop on 1hc next RCVR CL!\. The !lip-flop outputs CARRIER D1T A t'' the cmicr select stat~'
P,\I .. It. 1hc existing ,,tatc of the port is sud1 that a receive channel 11'.ay be opcm:d. the carrier state sckct
PAL 1mtputs an ;1>scrtcd ICCS PATH SELECTED and a ncg,llcd ICCS PA Tl! B RCVR PA TH SELA
assert;; w the receive path select inux to select Cl path ;\ for the rnuK input.

N1itc that the receiver carrier detect flip-tli>p is dockt'd by RCVR CL!\ which rcscls the flip-tlop as soo!l
as the carrier ..:ctcct A output ncgaw;, Thu-;, th.: Cl input path to the rccciw channd is dosed once the
carrier presence is n" longer sensed.
Had activity been sensed <Ill Cl rath B, similar k'gi~ would have sdc.'li.'d Cl path B for the mux input.

FORCE PATii A and FORCE PATii B from the link c 'nlrol logic force a corresponding path selection
from the carrier select state PAI... Whc.n the 1x•rt ..:omman<J.' a rnc.,sagc transmission, the path selected fnr
the transmission is reserved in the receive channel in prcpara1ion to receive the ACK response.
The port and link cont"ol PALs can also select the internal mainlcnancc hnp (INT MLOOP) whcrdn ME
DATA from the transmit channel is scb:tcd for the mux inpu1. The true st,itc of INT MLOOP inhibits
both RCVR PATH;\ and RCVR f',\TH H \\hich ,\tuscs the mux lo select the MF. DAT/\ input signal.
2.4.1.2 Receil'l' Path Sdect Mux - ECL Logic - The rcc'civc p;11b :'.elect mux is on sheet S of the engineering drawing set. The detailed opcr-.tion (1f circuit klgic i:- not usually described in a functional description manual, howc\cr, the operation of the mux is dcs.:;ribcd here as an example of th(· ECL lo11ic referred
to Ill Parngrnph 2.4.
Refer to hgurc 2-4. If RCVR PATii SEL •\is true. the otHp1:t of OR gcile A can follow !he CIA RCVR
sign:d input. The signal RCVR PATH His false which l11)ids the output of OR gate Blow, In ECL logic, a
signal lo" is till' non-active state and a high is 1h<: active state. Any gate connected to a common line can
pull the line up to the active state. Thus, OR gak Bis held inac1ivc (low) while OR gate· A transfers the
CIA RCVR signal to the Manchester decoder. The true state of RCVR PATii SELA also h,iJds the
LOOP OR g;H~ in the inactive st.ah:.

r,
(;';') 1

Cl.ll. RCVR

~R_c_v_R_r_A_T_H~Sf_:L~A.....-~

ME DATA
RCVH PATH SEL B

NOH-S
:·HE LOGIC IN THIS FtGUH[ IS COCHAi,,ED
ON SHEETS OF THE FNGINLEHiNG DRAWING:-;

FRCVR f'\Tl!SFLB"cr:tn;ciRC\'R P.\THS!'.. \'
~~- hdd :;n:l,:tii'c· ~tnd l)R g.~:x· H --'·:>u::1\i ft_;_ri-.;.t.i1 fr; t<' ! ~ ·.~;~1~: ..·:-

UR~"''-'.'\ .,r\'\i ;! ,, LO<Jf'OR p1c.: ,1 1tdd
RC\R w \hr \LrnLht:<:rr (!e,:1~kr.

If !.he ,niernal rn.,ti11tcn.1nce :,;.,p i:. ><~lc,:t••d. t.~.•i.h RCVR P \Tl l SEL >ign;tls .ire .Lds.:: luiding OR gait:' '\
·:r;d R in the inaL:ti . ,· sutr H.1wc>c:". :IK l(l()P OR ~:<le: i> n•. rn dd1v~ and 1r:;r1;;"•·r· \1E DA IA
t}w
\1.Hh~'fh!-:-i:i..'r \iC~\.Xkr

2.4.2.1

Phast> En<.'odin!;

Pt::t"<' Ull><Xhn!,'. 1Tigurc: •:\I ,

:•1;1<.ltil;;t10n te.:hntQUc'. i.n whit'r,

'-tn;d rh:l>C

:-n..;:~~l1 \X'.i..'.lJrS fo~ {.:,h·h bi: 1Jf inforrnatjiJn, A" i. !<.; ddinc·.d :1~ ~1 p:·)~nirt: k\d fulk~.,,~·t:d Py :J -nrg_;ui1·{
~:r.~_n:-;iti._:\rl, w·hdc J '··tr' i~ Jcfin~·d JS (J neg~i.t;\c .kn: 1 ~u1r<~•..q.~.d h:1r .~l po-;:itivl'. lran~i:i(lrL Ph;:'( n-:q·;·:"-ab ;"Jr(~~;
~ht.~ d'"H·il rate ._tr lH 1 wice !ht: dau1 r~nc. CiJn:~,~utiV(.' l ''5 t'r ~.,_-.ry~i.·uni\~c il~ wiU t'.~tUSt~ phu'-c n'."\'t:.'.r~.i'l:-; tt'· <:'Cb"
'H t"·io,~ the drna Litt \hgurc 2··'.'A} \!tc-"ndt~ t··_,_ and;)'_~ ~a:U~t nt.J·. r1,;:vcr.:·,.1i"' ti• C•(.... 'UJ
the tt1.ta r'\Ht"
<.FigUr<' :.~fj)
.

2.4.2.2 Dt-coder Logic --lho: \far:ch:s::: de-:c>dc.r dee •ks 1'1:: ,';i(,•.kd >ign:ll d<tlJ by ."<'p.lrciung otlt <he:
-;: MHz bit m1c ck"><:l ('.l.10ECODER CU). Kl k:;1\.·1~•: t'w ,ui1 d:t1;1 iRCVR SFRlAL D.\L\1. The

or ;t fliJ"'"llop w.ith the
input :s derived fr..:.n·r

J°;;"'..::i:.ldcr c,r~si;-;~.-:.
;.,·j'(K~

d;~i~t f:;:ir:.·t"thc ri::·~'Ci\ ,, {X1th ~lc~·t rnux. a:' the [) inpuL Thl:
!he cc;~~yt.:".d ;•0.:.pu~ ·:::tf th1; r~i,:;~:v(: palh s.c.k(!_ mux {dt:~·~tyL""d

r·h"'

:. ~1. F. t.:: >6 dJu~t:dtC!\ ;he ~t\:·ti~)r· z" 1f 01::: d~code.r lo~ic>
tfat·: fr(·ff: lh~: n.-~·c1 .. ·-.: p,lth ~c.kd ,1~wx i,·
~·rt) t.r,:in,.;i1i.on~ 4t !he- ..:·er.~::'."
t:·a~::1 hi~ -.;e;J
,~ 7t) ;\·iH.1 bit r.Jtc,_ 1h1..· ~·li..h~
the bit cdi~
6 \;;t~~ n~. Th~ "Ymput .Jf the dcL:ty tint"·:,~ ~~t•."11 a.~ ihc $fgru.1 Ua~~~ tk~;ayt..·d 10, - n" . .X()Rinf the drl.Jyt;"'.J d·.i.r,:
>1i:.c' ;he li:r-fl,;t 1.1~tru1 \.RC\R SERIAL !I,\, \l gcncr.:1e, :h.:: MDECODER CLOC!\ '>'.:1ef.Jrr• '-•'k
: (-,;,: :~ !he .;jse nitcrni1ting ·, .wd
the' w:Jtll oi it.; \1 DEC ODER CLOCK
lfa~ >e1 :inc •e><:';
~;~·~'::e"ii ·uftht.~ Lit:c<:.:icr t~ir-11·op Jr,. :hc-c~~;~(
c:.;.~r.x·cutih· ·s
(_,·,, d·1c·clock i'i
t:-:. t'h~· inYer~the
dd~::yc.d d.Jtu
~~1-.:~~_.-n wi!h

·r11·; MDFCODER CLOC!\ i>

7C \Hi:'."''"'

'-l

> ~' rxcn1,;. Th:: XOR '"'i.ior- '"''''''

!.'.::_'.)\.:·:(·--. r-is'.r;g i;dgi" ::,~ i~td ¢~tL:h ~i.: . C('.-n. T~~ :., ~ . c~;,~~~, tht ri.•j;,:.g ,':~:e:~ ;.r; tht" };dll; ~~rr.-hc.:
(ij·; l.:i::L

g~r,,c,:;:: the

:-<··r~:: h.:J\!'

(h(,~

'-'

·~:

Ln__n__ru-i_ J-1
, (.,.(,!W

,,,-- BIT CF i l.

14 2q "IS

l.---··'----.../
D

0
OUTPUT FROM RECEIVER
PATH SELECT MUX

DELAYLINEOU1PUT

MDECODEH CLOCK.

RCVR SERIAL DATA

_____j_,rti

1---•

f-·L-1

0 DELAY" 10."1 NS
0 DECODER FLOP SET TIME .
FL!?

•

OECODLR FUP FLOP RESET TIME

0 VAdO STROBE .•\REA
Figure 2·6

Manchester [)ec,xl<-'r riming Diagram

2.43 Sm~ Chi1rach'r lklt'CI l"~Rllble PA l
The purpose ,,f thr syn.; char.:i.:tcr dcteci cn.1hlc PAL is 1,1 a,.scrt L NA SYNC ULT ltl the• byk frama
when a pack.:! is c.\JX'ctcd. T'hc P,\L monitor> CARRIER DET ,\and CARRILR DFI B :ind m.,crh
FNA SY'\iC DFT wr"n it <>enses ltidt a signoil carrit•r i;, b<:ing received. T~w PAL nc11atc' ENA SYNC
DET during node transmi-;sions (FORCF PATH A, !ORCE PA Tll B) so the link will not rcsJXlnd lo it;,
11wn transmissions. The [>,\I. a:.scrts f:NI\ SY:\C DET immcdi,1tdy after inf11rmat1on packet transrnis~
oions in anticip;Hion 1Jf the• ."\CK \or !\iACK) rcsrxm,c:.

fhc byte framer ..:ontains a \\nc detector whkh i, en<1blctl b~ ENA SYNC DFI, Tfa· sync dt~tcctor ltxiks
for the p<ickct sync .;h,1ra1:tcr a> a mc;ms of rccogni1.ing th,it :1 p:1dct is b.:ing rccdv.:d, When the dctec'.tor
rccognin-s the syn .., character, it enables the byte framer to mirt prncc,sing the packet byte,, By keeping
the dctc.:tor disabled C)l.Cept when a packet is c.xpcctcd. the sync .:h:m1ctcr detect PAL prevents !he dct<'c'.·
tor from erroneously n:cogrnzi1ig noise as a sync charadcL
The sync charn.:tcr detect enable P,I\ L is discus<;cd in more d<:ta1l in l'aragrnph 2, I0. '.'..2.
2,4.4 Bytf' Framer
The byte framer is enabled when it receives the sync charncter byte, Once the frarnt:r rcc1lg111zcs the ,;ync·
chara<:tcr, it then functions to convert the serial signal data from the \ianchester decoder into eight-bit
data bytes for the RDAT bus.

As shown in Figure 2-7, RCVR SERIAL DATA b input to the RCVR serial >hift register. The rcgisrcr i'
held in the load state by the negated 'tatc of E i 97-R2 (Figure 2-8). thus n,l data 1> shifted into In(" register.
When a carrier presence is sensed al the f:-ont end of the receive channd, the >ync character detect enable
PAL also senses the carrier presence, If the PAL deem;; th;t1 this is a \'alid time to receive a packet.it asserts
ENA SYi'.;C DET to the SYNC ENA flip-flop. On the next RCVR CLK, the flip-flop outputs SYNC
ENA t<1 another flip-flop which asserts Fi 97·R2 to the RCV R serial shift rcgbter. The true state (1f EI 97R2 cn:1blc;. the register by changing it> state from load to shifL RCVR SERI AL DA TA i·· now shifted into
the register ;it the 70 MHz bit rate by \1DECODER CLOCK Figure 2-8 illustrates the timing of the
cnabJin!! of the RC\'R serial shif! rcjol"istcr.
The RCVR >crial \hift register outputs eight-bit bytes onto a data bus, The data bytes are then applied to
:he RCVR input rcgJ,tcr. The .\,1.nc dclC<'tor monitors the data lln the bus looking for r.hc sync· .::h ..ira.:tcr
byte, When the detector rc.cogniLcs tbc >ync char•1cter, il as~.rts E 198-3 to the sync tlip-nop. The next
.\1DECODER CLCX:K set~ the fl1p-n,lp and a,;,crt' SYNC to the external data framer.
"lotc that only seven of the cigh! bits on the data bus arc fed into the sync detcct»L Thc eighth bit i;. t;ikcn
from the RC\'R SERIAL DATA b<:ing fed int(> the RC\'R serial shift rcgi,tcr Thus. the syn.: detector
m,"<l!!ni1cs the syn.: character b<:fore the last character bit is shifted into the >hift register, The nc\t
\1DECODER CLOCK that docks the last bit into the register. alstl sets the sym,, flip-nor. ilcm:e, SYNC
:is:-crn. when the sync .::hara«tcr is in the shift register and n<.1t one dock pulse. later d"ig,urc 2-9).
When SYNC Jsscrts. the external frJmcr shil1 rcg,istcr fun..:trons to -;witch the RCVR input rcgi>ln from
the hold state to the load state (for one clod pulsci e"cry eight MDECODER C'L(l('I\, pul'c'. RCVR
SERIAL Dr\ TA continues 1<1 Ix· shifted mto the RCVR scri.11,hifl register hNy eight clock pulsi:.; a d.1ta
byte is present in the shift register "nd on the d.Hil bus. At thi' time the external fr,1mcor 'hif1 rcgi-;tcr
sv.itt;he>, the RCVR input regbtcr frnm hold tc> lo.id. The nc't MDECODFR CLOCK pulse then hiatls the
dat,1 byte into the rcgi>tcr,
The ()7 input to the external framer shift rcgisrcr is tied high Before the :isscni,111 of SY 'C. th<: fr<imcr

rcJli>tcr is in the ioad state. hence the R~ uutput is trut•. The tru~ stntc <)I the R7 out rut keep> 1hc RCVR
mput register m thc lo;1d state. When SY'(" as<;<"rtS. the framer shift r<'gister starts to 1-hilL ·r he i .it R ~ i'
shifted in dnd through the fr.imcr ~hirt rc~i>trr

·'"i'

SYNC

(FIG. 2·3)

(FIG. 2·3) _E_N_A_ __
SYNC DET

ROAT

-+-----------tiot D

7 .;..:0_>.;..)_ _ _ _ _ _ _ _
LOAD/SHIFT._.(D,...A_T_A_<_

<7:0>

RCVR
SERIAL
SHIFT
RCVR CLK

REG

____

(DATA<7:1>)

(Pl

RCVR
INPUT
REG

_ _ _ _ _ _ _..;.......;.......;....._..;..........;;.....-. . CLK
{

(FIG. 2-3)

RCVR SERIAL DATA

SHIFT IN

(P}

SYNC

._.,....__ _M LOAD/SH I FT .,_,R,...7--4M HOLD/LOAD

+V
NOTE:
LETTER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.

D7
EXTERNAL
FRAMER
SHIFT REG

CLK

(P)
~--"CLK

SHIFT IN

MDECODER CLOCK
TK,·8623

Figure 2·7

Byte Framer Block Diagram

RCVR CLK
(8.75 MHZ)
ENA SYNC DET

SYNC ENA

______

_,,,

E197-R2
STATE OF RCVR
SERIAL SHIFT REG.

LOAD

I~.

SHIFT

MDECODER CLOCK
(70MHZI
•

RCVR SERIAL SHIFT REGISTER STARTS TO SHIFT.
TK·860B

Figure 2-8

Enabling the RCVR Serial Shift Register

2-14

!1Jlf1Jl

fl.J1JUlJ1JUlJ

MDECODER
CLOCK 701\i!HZ
E1963

I
I

0
I

SYNC

0:
STATE OF
EXTERNAL FRAMER

E 199-R7
STATE OF RCVR
INPUT REGISTER

LOAD

J I

O--i.4°

I
I

SHIFT

0--1

I
I ,
!
I I
~~-1.__~~~__.n~~~~__,n~~~~---J_n

LOAD

._____________H_o_L_D_,f1.:~_L_O_A_D__________

O--l

fl..__
I

__,r-1.____________~__~ri_____,_~
I

o--i

0-1

- - - - - - - - - - - - - - - - - - ' F P A C K E T LE!l,GTHITYPE BVTE+·--··PACKET LENGTH BYTE·:=+=~-TRUE DEST. BYTE---~

ROAT <.7:0>

•

SYNC CHARACTER BYTE IN SYNC DETECTOR.

0 LAST BIT OF SYNC CHARACTER BYTE CLOCKED INTO RCVR SEWAl SHIFT REG:STER .
•

SYNC CHARACTER BYTE IN RCVR SERIAL SHIFT REGISTER.

0 FIRST SIT OF PACKET LENGTH/TYPE BYTE CLOCKED INTO RCVR SERIA.L SHIFT REG!SfER .
•

LAST BIT OF PACKET LENGTH/TYPE BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.

0 PACKET LENGTH/TYPE BYTE IN RCVR SERIAL SHIFT REGISTER .
•

EXTERNAL FRAMER SHIFT REGISTER STARTS TO SHIFT.

0 \DATA <7
Figure 2-9

0.>) CLOCKED INTO RCVR INPL:T REGISTER.

Byte Framer Timing Diagram

Every eight MDECODER CLOCK pulses. the I is shifted through to the R7 output. switching the RCVR
input register to the load st.ate for one clock pulse. As seen in Figure 2-9, the timing is such that a data byte
is on the data bus when the RCVR input register is loaded. The timing for the first three bytes of a packet
is shown in Figure 2-9.

2.4.5 RCVR CLK Generator
Figure 2-10 is a block diagram of th~ RCVR CLK generator. The RCVR CLK is derived from a crystal·
controlled 70 MHz oscillator. The RCVR CLK pulses function to time and control the operation of the
receive channel logic. When a :;ignal packet is received, the RCVR CLK is synchmnizcd to the pack.ct
bytes by SYNC received from the byte framer.
The output from the 70 MHz crystal-controlled oscillator is doubled to 140 MHz by a frequency doubler.
(The 140 MHz is used in the Manchester encoder in the transmit channel.) The 140 MHz is divided down
Lo 35 MHz and then applied to a shift register consisting of four llip-nops. The shift register divides the 35
MHz by four, outputing RCVR CLK at a frequency or 8. 75 MHz (period = 114.28 ns).

(RESET COND.i
35 MHZ

FF
IN)

FF
{N)

ACVR CLK

FF
IN)

A -------------<>ICLK

FROM BYTE)
( FRAMER

F1G.2-7

SYNC
-------oo1

E151 3

140MHZ
~

70MHZ
XTAL OSC

ITI

FREQ

140MHZ

DOUBLER

7l')M112'

ITl

fr)

NOTE
LETTER DESIGNATIONS IN P.•RENl'HESES REFER TO

ENGINEERING DHAWJNGS CONTAINING CORRESPOND1NG

LOGIC.

Figure 2- l 0

RCVR CLK Gcntnh1r

SEE NEXT FRAME
FOR !.AR:>ER ART

2-16

( TO MANCHE:TE R ENCODER )
FIG.212

-')
!Tl

(RESET COND.)
FF

(Nl
35MHZ
A r---------------CLK

(N)

RCVR CLK

[RESET) (SET ) (SET ) (SET
\
ICOND.
COND.
cmm.
COND. I

( ~=~~::TE) _ _ _ _s_Y_N_c_ _ _ D SYNC E153·9
FIG. 2-7

D SYNC!---.---:---..,

____
E151-3

(N)

(Nl

CLK

EXT SYNC}
(FIG. 2-3~
r-----.CHAR
PW
FF

D FF

'-----INCLK

SYNC

(A)

(N)

RCVR CLK

( TO MANCHESTER ENCODER\
FIG. 2·12
/
70MHZ
XTAL OSC

70MHZ

FREQ.
DOUBLER

140 MHZ

!Tl

(T)

NOTE:
LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
LOGIC.

Figure 2-10 RCVR CLK Generator

2-lli

,,__3_S_M_H_z_,... A

Table 2·2 list the frequency and period of the link c.locks. The XMIT CLK (di,cu~scd in Paragraph 2.5.7)
is included in the t~blc.
The register functi,ms to shift a logic low through the f1ip-!1np chain. When the 1<.!w is in the rightmost
flip-flop, the other three tlip-llops are set. Outputs from the three set ilip-llops arc :\ 1\Dcd iogcther to
condition the first flip-flop to reset on the next dock pulse thus n:-inscrting the low into the tlip-flop chain.
The cycle is then repeated.
Table 2-2
frequenc~ (MHz)

Link Clocks

Period (ns)

Clock

14 . 28

MDECODER CLOCK

28.57

8.75

114.28

RCVRCLK

8.75

l 14.28

XMITCLK

The left and right portions of Figure 2-11 illustrate the operation cyck of the shift register. (The center
portion ill, Mates the synchroni1.ation function.) Waveforms I, 2. 3, and 4 relate t<l the corresponding
points in Figure 2-10. Also shown is the MDECODER CLOCK and SYNC from the b~ tc framer, and the
time periods that :he ROAT (7:0) by1es are in the RCVR input register These three signals are rime
relJted to each other and are shown as they appear in the byte framer timing diagram (Figt:re 2-9). The 3~
\Uiz clock and the shift n:gister waveforms are time related to each other but are independent of the byte
framer timing. The SY~C signal is used to synchronize the action of the shift rcgi>lcr with the data bytes
fr0··1 th·· byte framer.
As shown in Figure 2-10, when SY:\C asserts. two sync llip-t1ops are set by •he 35 \1Hz dock which in
turn assert E ! 51-3. The next 35 MHz clock sets a pulse width '"'Vl flip-flop which negates E 15 I <3. thus
forming an E 151·3 pulse to the shift register. The E 151-3 pul~ synchronizes the register by forcing a re,,ct
condition on the first flip-flop anci a set condition 0n the other three flip-flop:;. The next 35 1\fHz dock
pulse places th~ register into the conditioned state which is to introd•Jce a logic low into the i'irst 11.ip-llop,
Thus, regardless of where the register wa.\ in its cycle. it is rcsrnrted at the beginning of the cycle,

The assertion of SYNC followed bv the assertion of E i Sl ·3 is seen in Fic.ur<c 2- l l. Note that the col'ditions
forced onto ,he shift register by th.e El 51-.1 pulse are docked in by the "nc:xt 35 \IHz ckJ<;k pulse (the first
11io-tlop is reset and the other three are sell. As seen m Figure 2·: '..the logic klw had reached the second
f1ip-11op when the register cycle was interrupted and reset bck to it> ;,tarting point. The register cycics
from this point on are in synchwniwtitm with the byte frame, Th.IS results in the generation of RCVR CLK
pulses approximately centered in the time period when the pa,kcl bytes (RD\ 1 1,7:0}1 drc in the RCVR
input register.
2.4.6 CRC Check
The packet bytes on the RDA Thus, up to and including the four CRC bytes. a·e input ln the CH( d1cck·
er. If no errors are detected by the ch·~d..ec the checker <i>scw• CRC S L'<TUS lo the message receive state
logic, indicating the receptic'n L'f a valid, error-free packet.

2-17

018

MDECODER
CLOCK (70 MHZi

35MHZ

~ t-----:----

SYNC

E1539

EXT SYNC

E151 3

0
0
0
0-1

L_J

L.J

L_j

L...J

~cit:~~ ---i~~~~~~~--'r---1~~~~~~~~~~~~--Jr---l~~~~~~~--'_.r--l~~~~1 ?DA~·<I0>•

j-·--i'.,FOR
i'" RCVR INPUT REG J-····+-··-i IN RCVR iNPJT REG.t, .• _ ,
THIS PERiO[i
\FOR TH;S PERIOD. }

0 LAST BIT OF SYNC CHARACTER BYTE CLOCKED INTO RCVR SER'.t\l. SHIFT REGISTER.
0 SVNC CHARACTER BY TE IN RCVR SERIAL SHIFT REGISTER .
•

FIRST BIT OF PACKET LE"iGTH/TYPE BYTE CLOCKED !NTO RCVR SEH/,L SHIFT REG'Sff P

0 LAST BIT OF PA~KET LENGTH/TYPE BYTE CLOCKEC. l'l;TO RCVR SERiAL SHIFT RHi'STE'i.
0 PACKET LENGTH/TYPE BYTE IN F:C' ;, ;)~RIAL SHIFT REGISTER
0 FIRST BIT OF PACKET LENGTH
•.UCKEu INTO RCVR SERI Ac. SHiFT 'l2CiiSTER .
•

LAST BIT OF PACKET LENGTH 3rTE c:..OCKEC INTO RCVR SE81AL. SH:"i ".E·:.i6TEP.

0 PACKET LENGTH BYTE IN RCVR SERIAL StiiFT REG!S.ffR.
0 FIRST BIT OF TRUE DESTINATION BYTE CLOCKED INTO RCVR ::.<:,\:.AL .3'-'i" T HEGISTER.
figure 2-1'

RCVR Ci.K Synchronization

(RDAT

()

'·

Pi\ChJ:T TYf.1 f /L.!:~-~GTH BYTE
PACKE: LP<.)TH BYTE

2.4.7

Destination Compare

The node address and the complement nf the node address are set into two sets of cight-contdct node
addrt's~ switches. The eight-bit output c>f the complement node addrc\s switch is applied to the lruc dcstm:.ition compare logic as CNODE ADDRESS (7:0). The eight-bit output of the tn.c node address switch is
applied to the complement destination compare logic as NOOE ADDRESS (7:0).
The true dc1>tination byte and complement destination byte arc applied from the RDA T bus to both dcstina1ion compare logic circuits. The state PALs enable the compare logic outputs ;;ud1 that when the true
destination byte is on the RDAT bus. the output of the true destination compare logic is cn:ibk<L Ir the true
dc,tin~tion byte matches CNODE ADDRESS (7:0) from the complement node addre5s switch. TDST
CMP asserts indirnting that a true address match was obtained. Likewise. when the complement dcs<.ination byte is on the RDAT bu.,, the output of the complement destination compare logic is enabled. Jr the
complement destination byte matches NODE ADDRESS (7:0) from the true node address switch. CDST
CMI' asscm indi..:ating that a complementary address match was obtained.

True and complement dc,ti.nation matches assert DST CMP to the message receive and ACK receive otatc
Joi:.ic.
A pobrity rcvcr~al in the compare lork results in the output of the true 1wde address"' itch being applied
IO the complement destination comp~~c logic and !he output of the complement node add, ·:ss switch being
;1pplicd to the true destination .:omparc logic.
The output of th'' node address switches is coupled to the compare logic via XOR gates. This allows the
true address and the comp!cmcnt address to be swapped for m.aintcnance testing.
2.4.8 ACK Source Comparison
The ACK source compare logic is used only during !he reception of an ACK p~det. The ACK packet was
transmitted from its s<Jurcc lo acknowledge an inf<lrrna!ion packet that was transmit.t.cd from this n-.>dc.
When 1:·" information packet wa> in the transmit channel, t.hc destination address was saved and applied
into the Al 'K source compare logic.

The ACK source compare logic receives inpu:s from the transmit channel and from th~ RDAi' bus. When
the source byte of the ACK packet is on the RDAT bus. the output of the compare logic is sampled. If a
match is obtained, ACK SOURCE CMP is nsscrtcd indicating that !he source address of the ACK pack.ct
makhcs the dl'Stination :tddrcsS of the preceding infornMlioO pack.ct.
Receive l.>'dla Parity And Channel Output
Data bvtcs arc trnm.fcrrcd f'rom the RD.l\T bus tc1 the PB via the receiver output data rcgist•:r. The bytt:s
arc output from the register as RCVR DATA {7:0).
2.4.9

The d:Ha byt.:s arc also applied f;om the RDAT bus into a receiver data parity generator where 1.idd parity
is gcn~rated cm each byte . A ninth input to the parity gcm:rntor (VALID RCVR PARITY) rrovidcs a
rncan:; or introdunng parity errors for nmintcnam;c testing. The: output from the parity generator is applied
!.ti .i pcirity flip·l1op which outputs RCVR DATA PARITY to the PB.

l.5 TRANS!\HT CHANNEL
Figure 2·· ! 2 is a block cti.1grnm of the tran~mit channel and should be rdcncd to throughout Sct:tion 2.5.

2.5.1 Transmit !>al.a Input
Transmit data. from the PB IXMIT DATA (7:0)) is input 11110 the transl1\il channel via the XMIT datil
input latch :111d then transfrrrcd to thi: XMIT da1a bus as XMIT DATA BUS (7:0). The input la1ch is
tr:rnsp:m,nt in that the data on th<: XMlT data bus will follow the XMIT [),\l A (H)) input. so l11ng as the
iatd: j, t:nablcd by ENA XMIT DATA LATCI I from the transmit ,:ontwl lugk ;rnd by the high state of
XMIT CLK. When XMIT CLK is low. the latch is dis:1hled (closed)

)_ i 9

ENA SYNC/TR

(FIG. 3_21 XMIT DATA PARITY

TDATA

SEL TRAILER (AO)
SYNC/
TRAILER
PROM

BINARY

(BINARY 1010)

..-------..io COUNTER
(E)

ENA SYNC/TR
CNT
-----'----.iEN

XMITCLK

(A4·A1) (A4·AO)

(E)

(B)

1-'---'-_,_~~~ADDR

_X-'M"-1T'--"-C--.LK--..._ CLK

SYNC/TR
GONE

(A2)

XMIT CLK
LAST
SYNC

-----

L-NA XMIT DATA LATCH
(FIG. J-Z)

XMIT DATA <7:0>

<7:0>

XMIT
DATA
INPUT
LATCH

XMIT
CLK

(El
XMITCLK
---'---'""HOLD

XMIT
DATA
REG
(E)

70
(FIG.) MHZ
\ 2-10

XMIT
SERIAL
SHIFT
REG
D (A)
SHIFT/LOAD

C NODE ADDRESS <7:0>

(FIG. 2-lOl

GENERATOR

[A DRIVER ENA
(FIG. 2 · 26 \

l"G'2'1~

{

70MHZ

140 MHZ

L~G:..:1~ _J

ENA ACK SRC
(FIG. 2-31) { ENA ACK TYPE
ENA ACK COST
RCVR
BUFFERS PAL
STATE
(FIG. 3-9) FULL
LOGIC
(L)

BUSY

RCVR CLK

..--......_._......,CIA
XMIT
XMIT
ECL
DRIVERS CIB
(FIG. 2-17) XMIT

' - - - - - - - - - - - - ( F I G . 2-3)

COMPLEMENT
ACK
DESTINATION
REG
(0)

CLK ACK DST REG

MANCHESTER
ENCODER
FF

'----....ic

(E)

(FIG. 2_31 RDATA REG <7:0.>

(FIG. 2.3Q) MR STATE E

XMIT
RO
CLK
GEN
(FIG. 2_141 XMITCLK

ACK
TYPE
LOGIC

(FIG. 2-27)

B DRIVER ENA

t:LK

rcRc-- -,
(FIG. Z·J)

D
SERIAL
DATA
FF
(T)

CLK

( FIG. 2-25 )
FIG. 2-27

(El

CLK

XMIT
SERIAL
DATA

TDATA
PARITY
ERROR

XMIT
DATA
PARITY
CHKR

LATCH
FF

(32X8)

LOAD

(FIG. 2 26)

(FIG. 2_261 ENA XMIT DATA PARITY
- - -.. TDATA . . . - - - - - .
PARITY

DESTINATION
ADR REG
(D)

{FIG. 2 3)

CLK

(FIG. 2 _ 31 )---------------+--+---E_N_A_A_C_K_T_DS_T_~

CLK DST
ADR REG

TRUE ACK
DESTINATION
REG
(D)

'---1--D

NOTE:
LETTER DESIGNATIONS IN PARENTHEZES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
LOGIC.

TK 8628

figure 2· 12 Transmit Channel Block Diagram

2.S.2 Bit Sync, Sync Charncter, and Trailer Bytes
Tht" bit synchronir.ation bytes, the sync character byte, and the trailer bytes reside in a 32 X 8 PROM. The
PROM output is enabled by ENA SYNC/TR from the transmit control logic. A five-bit address input to
the PROM ((A4:AO)) selects the output bytes which are placed onto the XMIT data bus.
Figure 2-13 illustrates\ .i: 32 eight-bit locations in the sync/trailer PROM. The five bit-sync bytes and the
sync character byte are located in the tpper area of PROM space. They are spaced at every other b .on
starting at address I 0 IO I. The six trailer bytes are located in between the sync bytes starting at addr11ss
10100. The lo11•er area of the PROM is reserved for possible extension of the header to 16 bytes (15 by.
of bit synchronization and one byte for the sync character).
PROM address bits (A4:AI) are obtained from a binary counter which is enabled by ENA SYNC/TR
CNT from the transmit control logic. When ENA SYNC/TR CNT is false, the counter is loaded with
starting adcress 1010. When ENA SYNC/TR CNT asserts, the counter counts up from 1010 addressing
every othe:
.,M location. The PROM's least significant address bit (AO) is SEL TRAILER from the
·ransmit conn :>I lugic. When SET TRAILER is false, the pr '1M sync bytes are addressed. When SEL
TRAILER is true. the PROM .lier bytes are addressed.
Address bits <A4:A2) are monitored and cause LAST SYNC to be asserted to t.;e transmit control logic
when all three bits are true. As is shown in Figure 2-13, this occurs when the last sync byte ,sync byte 5) is
being addressed.
When the binary counter has counted up past the last trailer byte (or past the sync character byte) it overflows and asserts SYNC/'"'l GONE to the PAL state logic.

2.S.3 ACK P•cket in!.<!1
The packet type, source, and destination bytes are in&erted into ACK packets by the link. When information packets are being transmitted, these bytes are inserted by the port and do not involve the link
hardware.
2.5.3.1 racket Type Byte - The packet type byte is obtained from the ACK type logic. The logic outputs
a I in bit position 7 signifying an ACK (or NACK) packet. Bit positivn 6 is a function of BUSY which is
derived from RCVR BUFFERS FULL from the PB. If the receive buffers in the PB are full, the information packet just received could not be accepted by the node causing BUSY to assert. This causes a l in bit
position 6 signifying that a ]',JACK packcl is being transmitted. If BUSY is false, bit position 6 is 0 indicating that an ACK packet is being transmitted.
Bits (5:0) from the ACK type loi-tic are always 0.

2.S.3.2 Source Byte - The ACK source byte is
complement node address (CNODE ADDRESS
(7:0)) obtained from the complement node address switch. The source byte is gated onto the XMIT data
bi.s by ENA ACK SRC from !he PAL state logic.
2.S.3.3 Destination Bytes - The ACK destination bytes arc derived from the source byte of the associated information packet. The source byte is taken from the RDA T bus in the receive channel and clocked
i:1to the destination address registers by CLK ACK DST REG. ROAT REG (7:0) is entered directly into
the true ACK destination register while the inverse (complement) is entered into the complement ACK
destination register. The true destination byte and the complement destination b} le are gated to the XMIT
data bus ry ENA ACK TDST and ENA A'-:'.K COST, respectively. The gating signals are asserted by the
PAL state logic to insert the bytes intf' ;he ACK packet at the appropriate insertion times.

2-21

(HEX)

O
0

TRA'LER

(551
:001

J_ .

BIT SYNC BYTE 4

i55)

O .Q..

. Q..

START HE RE
J.
FOR '1EADER- 1

100)
BIT SYfl.C B~ ~55)

2..

()

2..

ST./:\RT HERE FOR TRAILER

_2_ ~BIT_~:::Nc BYT_E b

(96)
(OQ)

0
1

SYNC CHARACTFR

f- TRAILER

TRAILER

BiT SYNC BYTE 2

i5~j

TRAILER

(00)

BIT SYNC BYTE 1

(551

TRAILER

{OOi

BIT SYNC BYTE

(55)

TRAILER

mo:

BIT SYNC BYTE

(55}

'
0

..Q.

() .Q.. I

TRAILER

(OQI

..Q. 1
..Q.

BIT SYNC BYTE

{5!))

0 I

TRAILER

...LI

BIT SYNC BYTE

(55)

TRAILER

(()())

1
-;-

()

L
I

-1 I

_Q_

0
J_ . .L .Q..
1 -; :

I ________

..Q.

0 )

TRAILER

-; ;

BIT

srnc BYTE

(00)
(55)

1 ..Q. ..Q. ..Q. ~~A_l}~ ______
w_o_i___.
BIT SYNC BYTE
..Q... ...L 1

...L

TRAILER

(00}

BIT SYNC BYTE

(5~)

\001

2..

TRA1LER

Bl T SYNC BYTE

Ji... 0
_g_ _Q.

J_
..Q.

()

TRl\ILEl;;_ _______,_.o_o_)- i
BITSYNCt\"\TE

(55!

_1_._RA_IL_E_R_ _ _ _.,_w_o.;_)-'

ITI Tl-=AO
L_:~

T
!I'

BIT SYNC._B_Y_T_E_ _ _l.;_55;...:i_
- ,_____
___,

.Q..

(001

A3
~------A4

Figun. 2--l .< Sync/Traikr PROM SruL·~

2.S.4 Des~ination Address Register
The destination address register saves the destination address of an information packet that is being transmitted. CLK DST ADR REG asserts at the ..:orrect time to clock the true destination byte into the register.
The destination byte is used when the associated ACK packet is received. It is compared to the source of
the ACK packet in the receive channel where a match will be obtained if the correct node responded to the
message transmission.
·
2.S.S Transmit Data Parity Check
Data on the XMIT data bus is transferred to the BUS TOA TA bus via the XMIT data register. The register output is gated to the BUS TDATA bus by ENA XMIT DATA REG from the PAL state logic.

Data from the BUS TDATA bus is applied to the XMIT data parity chee,ker where a parity check is made
on the packet bytes. The parity bits (XMJT DATA PARITY) are received from the PB and applied to a
latch flip-flop as TDATA PARITY LATCH. An OR feedback network holds TDATA PARITY LATCH
true for both alternations of XMIT CLK to allow the latch flip-flop to set (if parity is a I). The latch
flip-flop outputs the parity bit (TDATA PARJTY) to the parity checker. Parity is ch:::cked when ENA
XMIT DATA PARITY asser::S and enables the parity checker output. If a parity error occurred, TDATA
PARITY ERROR is asserted to the message state logic.
2.5.6 CRC Generation
The packet bytes on the XMIT data bus, starting with the packet type byte and ending with the last byte of
the body, are input int~ the CRC generator. The generator functions to produce a 32-bit CRC longword
unique to the packet beint transmitted. The longword is inserted into the packet, a byte at a time, after the
packet body.
2.S. 7 XMIT CLK Generator
Figure 2-14 is a block diagram of the XMIT CLK generator. The transmit clock (XMIT CLK) is derived
from a 70 MHz input received from a crystal oscillator network in the RCVR CLK generator. The transmit clock generator functions to produce XMIT CLK pulses at 8.75 MHz (period= 114.28 ns). The generator also outputs an RO pulse to load the XMIT ~erial shift register from the TDAT A bus.

The XMTR framer shift register is clocked at 70 MHz and has an eight-bit parallel output ((R7:RO)). The
inverse of bit~ (R6:RO) are ANDed such that when all seven bits arc false, a I is input to the framer shift
register. The I is clocked l'P to the R7 output at which time another I is generated for the shift register
input. This action is illustrated in Figure 2-15.
R6 and R7 from the framer shift register are applied to the D input of the XMIT CLK flip-flop causing the
flip-flop to set for two 70 MHz clocks. The output of the flip-flop is XMIT CLK. Figure 2-15 illustrates the
time relationship of XMIT CLK relative to the outputs of the framer shift register.
For maintenance testing, the output of the XMIT CLK flip-flop can be disabled and an XMIT TEST CLK
substituted.
2.5.8 Parallel to Serial Data Conversion
Eight-bit data bytes from the TOA TA bus are input to the XMIT serial shift register. RO from the XMIT
CLK generator asserts every eighth 70 MHz clock to load the shift register with a data byte from the
TOA TA bus. After being loaded, the register returns to the shift state and shifts out the data byte a bit at a
time as XMff SERIAL DATA. As the last bit is shifted out, RO asserts again to load the next packet byte
into the serial shift register. Figure 2-15 illus!J".ites the load and ~hi ft time periods of the serial shift register.

The XMIT SERIAL DATA is applied to a serial data flip-flop clocked by 70 MHz. The flip-flop output
(E 183-11 ) is then applied to the Manchester encoder.

2-23

RO
,-+IFIG.23)

O XMITTESTC_l_K~~~~~·~~~~~~
~TCLKD~

II I
'
III
I
I, ·Ii

(FIG. 2-10) ?OMHZ

XMIT

I ~~K

1 iFIG. 2.1oi-7"""
0 ....
M--H_z_.,..cLK

XMIT
FRAMER
SHIFT
<R7:RO>
REG

XMITCLK

.._~__.

<R6:RO>

CLK
NOTE:
1. THE LOGIC IN THIS FIGURE IS CONTAINED
ON SHEET R OF THE ENGINEERING DRAWINGS.

SHIFT IN

TK--8603

Figure 2-14

XMIT CLK Generator Block Diagram

2-24

MHZ

_fROL

I _1R1l

__JFi1"1__
I

_JR2l_

XMIT
FRAMER
SHIFT
REGISTER

_IROL
__JR2

_JR2l_

JFi4L

___lFi5L

___f!i6L

0 IN SHIFT
(E1861)
DO

IE17J.3) - - - - - - - - - - · - - - - - - - "

· - - - " - - - - - - - - 1 1 4. 28 N S - · - - - - - - - - - - - - - f

XMIT CLK

...----1_____

XMITSEAIAL
SHIFT
REG.

--------------------.-'"LoAD1
. . .______1HIFT
__________,~LOAD
SHIFT
!
L
I
1
......- - -

Figure 2· 15

XMIT CLK Generator Timing Diagram

LUAU

2-2.5

L.U"U

2.$.9 11,bnchester Encoder
The Manchester encoder modulates the serial data with the data bit rate clock l<> produce the signal format
that is placed onto the Cl bus.
The encoder iogic consists of XORing the E183-l J output of the serial data flip·flop with the 70 \fHz
clock. The output. of the XOR gate is inverted and applied to the Manchester encoder ilip-llnp. The encoder flip-flop is clocked at 140 MHz (twice the data rate) t1s required for phase encoded (PE) data (sec
Paragraph 2.4.2. l )_The output of the Manchester encoder t1ip-llop (ME DA TA) is the pa\·kct data ready
to be t.ransmittcd onto the Cl bus.
The action of the Manchester decoder can be seen from the timing diagram of Figure 2·16. The EPU·l l
output of the serial data llip-llop is shown for the given data bits. The result of XORing E 183-11 with the
70 MHz is seen. Using the inverse of the XOR output for the encoder llip-11op ()input, and th•· 140 MHz
for the clock, the resultant ME DAT A waveform is derived. The ME DAT A signal format is identical to
the format of the serial data received from the Cl bus as shown in Figure 2·6.
2.S.10 XMIT ECL Driters
The ME DATA from the Manchester encoder is transferred to the Cl bus via XMIT ECL drivers(Figurc
2· 17). The XMIT drivers arc divided into two channels feeding the A and B paths on the Cl bus. Path
selection is made by the port via the transmit control logic which enables the driver in the selcct.cd channel.
The ME DA TA is routed to drivers in both channels and then through coupling transformers to the Cl bus
as CIA XMIT and CIB XMIT. The XMIT drivers are enabled by redundant XOR gates. When the trans·
mit control logic seleds channel A, A DRIVER ENA asserts (B ()RIVER ENA false) and in turn asserts
El 5 I ·I from the channel A AND gate. The assertion of El 51·1 causes outputs from both channel A XOR
gates which in turn cnabl•~s the channel A driver.
Likewise, the assertion of B DRIVER ENA from the transm!t control logic causes the assertion of the
E 151-2 output of the channel BAND gate and thus enables the channel R driver.
Redundancy exists in the driver ('nabling logic to prevent the possibility of a single component failure cau~
ing the A and B channels to be enabled simultanc.ously. If through a logic component failure, the outputs of
both the channel A and channel BAND gates were asserted (E 151· I and 2 both true). one of the channel
A XOR gates and nnc of the channel B XOR gates would be mhibitcd. This would hold the enabling inputs
to the channel drivers high to inhibit the drivers and 1s11late the node fnlm the Cl bu.\,•
The port can also select. internal maintenance loop operation where the ME Di\ Ti\ from the transmit
channel is looped back into the receive channel. To do this, the port control logic ;1sscrt> INT MLOOP
which inhibits both El:51 AND gates, shutting off both output drivers. In addition. the signal lines into
both the A and B channel drivers arc held high by INT l\HJX)p to inhibit any signal data variations into
the drivers.

DATA BITS

()

70MHZ

E H:!3-11
XOR

140 MHZ

ME CATA

n_n_rLn
I

I
1..

I
1

.. 1

""BIT CELL" 14.28 NS

Figure 1-16

Manchester Encoder Timrng Diagram

~CIA XMIT ..

"'G ,.

,Jl_

Figure 2·17

tFIG. 2 12)

_J_-+--IN_T_M-LO_O_P--+---+----1
ME DATA

eta XM!T

XMIT ECL Drivers

2-2li

2.6 CRC GE 1\!ER \TOR A!\D OUCKF:R
Figure :C-1 ~ j, .1 blod d1.tgrcm1 o! lhL' CR(' gcm2r.11<'r .md dic-:k<:r.
2.6.I CRC Generator
P11dc1 byh·, frum th"' XMIT dat;t bu:' i11 the tr.1mmit .:bnnd ar(: in rue u• •he C RC ir1rut n·w, ,,., X\111
DAT•\ BU'l :~.o:. The trnnrn1it c,1mwl :ll~ic 2s-en, X\fiT (RC F'A 111 the mt;\ 10 .;dcd :h,: by\,:• fhrn1
the tran~mit chJnncL The mux outpu~ '' arrlkd w rhe CRC input rcgi,;1.:' "hich ::utpu:s thl· b~ tl'-' .is
NEW DATA -:::o).
~EW DAT.\· ~:O; is applied to 3 CRC lookup tabk 1·ia ;in XOR g•HC. The i"''~'"' ;.1bk !ngic g1 naak> the
CRC longwwd for the ix1.;:ket bt:ing tntn>m,ncd. CR(' T'\BLE (JI :\)(r twm the i<il\•kup t:1bli:: log1~ 1s
applied <o a CRC r<·g1,tcr which outputs CRC (.1 l :00 . • CRC ,·j l :00> i,; k••DCC l:>,1d into ihe f,,u~up tu bk
logic in tvon parts. The first three bvte' tCRC i~J:O(l ,'1 .m: ctpplicd dirndl\· inc• the tc;bk k•gi' w!tile th<c
uppcrb~te (CRC /}1·24)1 is XORt>d with th, Oc\\ input b)t<' frnrn thl.'('RC rnput n:g:.t<.:L Thus, the new
dalJ bytes are ,-omiruously 1ntcgra!cd m1<1 the cornr1Jatio:: of the pre' 1<ll1' d;1t;1 bite·, 'uch that the CRC·
generated longword is alwaY> a furn:•i'm of the p:1d.:c.1 bytes r<'ee.il'cd fr,y,n th>: lr.1m,mi.t ch.mnc:

The CRC long'h'rd !'mm the. CRC n:gi>tcr 1.s als.:1 coupled tc the Bl:S TD.-\ T .\bu;; in the tram,mit ..:h,::rn~'
1·1a fou~ dnvers. When cnJbied. each dr11er nb~e' ;1 bvt.: ontc the Bl 'STD\ T -\ bu;; l(I in,;en a CRC

intc1 the packet being tran~rnit<ed.

h! ·.,t

The drivers are enabled frnm d CRC byte ;;ouni.cr The c. 1;.;.'.ltt:r rtcwc> "SHIFT fl\' input tE29.<) \\Oen
the last bvte .:1f the pa.;ket l:xldy is <m 1he BLS Tl>A T .\ t-u.'. The rnput I> 'hifted through the .;,iunter h~
CRC Cl.CKK a.sserting RO through R:l in sexic~ncc. RO thrc•ugh R.1 ;lre a,.iplll·d tc four ·\ \D !'ales" hich
arc enabled at the appr,;pd;1te time frnm the PAL >ti11C k>gic.
In additior:, ENA XMiT O;\TA t<.EG must be faise bcl~7r( 1hc RJ A \D iJJ«' ;, e.:iobk'd t(1 place the first

CRC bytc{CRC ,7:1f;\onl0 :r.c TDATA b·J.,. Thi.; in,ur~~ tha~ th~ TD.\TA bu,,, '-;.:,iate!'! inm the X\1lT
data rcg[ster before th~ CRC Jog1\: 1> i::cinne.:ted tl' th1.· bu» i,e(· figur,: ::'.· \2i L1kcwi.;c, rn"h AND gate
mu.st be disabled in sequence before tbc nnt \l\;j) gale can ti;; cr.abled Thi' i11'UH.'' th.11 0nly c1n~ wtm:c i;
driving the TD-\ T \ bu.< .It :iny one t'mc.

The CRC gencrat.1r l0gic i> clocked b~ (RC CU.XX ".hici'\ ,.; .-\.·1.·~: t<.> bc \:'.,HT Cl. 1-: during the tr;i:1,mi!.
state~.

2.6.2 CRC Checker
Packet byt~ from the RDA T regi:iter bus in the rcc.::ivc chJnne: arc
t. :n,.c CRC mr1". mux a' RD.\'I
REG OJI), The trm.<rnit control logic ncg.ucs the X\llT CRC L'-.,\
·;h1.: mu.x >de.:;1ing !h" b.1 t<.><
from the m;:1ve ~.h;mnel. The mux ma put is appfa·d hl :h~ CR(' '.nr<>' rqp,lc .,foch outnuts the bite> as
EW ;)A TA (i:Oi.

°"

The CRC k1gic fo11\:dons 10 generJte tht' CRC '.ongw,,,.,; (CRC (.1: :00: 'i !rn:;; 1N· !',lCket h~tc' .1' d<:., .. ·:t><;:;J
in Paragra('i ] I:<, L Th.: i::.s1 four bi res inpu' 1" th~ CRC k·gic 1s tht CRC j,!ngw,1rd gcncrakd for t t•t:
rxtcket. V.,.hcn the: CRC k'ngword is ~.r.tt·rcd inlil the CRC l;.,!:ur t'.i\>k J~, '''u'.pt:l <•l DEBR ::'.~F1 •he,\,«
dccimali wi!i be <>bt .. ined if the packet trnnofer '-'JS em>r ir~.t·.
The longwcm! is applied !o a CRC c:t•rnparit<'f whi.:h chc.:>.:, the,,,,,.;,·
ST.\ Tl.S if th.;- pr,ipcr >;!tuc "a, ,>tnained

CRC
CMP

_ _ _ _ _c_R_C_S_T_A_T_u_s_.,..( FIG. 2 3; 3 91

(V)

----.cRC TABLE

<31:00>

CRC <23:00>

XMITiJATA
(FIG. 2-121 ~._<_.7_:0_>_ _ --!

CRC <31:24>
CRC
INPU'~

MUX
!FIG. 2 31

RDATR~

(FIG. 2 261

XMIT CRC 'ENA

CRC

!DCR.C
INt'UT
REG

I l
ru
I
r~)G

(f')

ENA CRC TABLi'

CL~

1
1

)--'----~(C~R_C~C"-'-LK~)-------1---~IC_R_c_c_·K_l~~

RCVR CLKL{:::::o

LOOP

E295 !START

IFIG_ 2251 MXSTATE
AX STATE C
(FIG. 2' 31 {

AX STATE G

(FIG. 2 _251 MX STATE K'

----......,c

FF
IUI

( FIG.) CRC BYTES OUTI
,226

!(FIG 2301

-~B-'U-'S_T_D_A_T_A_<_7_:o_··_.. \

( FIG.)1
2 12

l .•

l
I

CRC<15:08> V

·.

-i

CRC <07:00>
I

2-261_[~

~NACRCI

CRC
!RO
BYTE
COUNTER Rl
CLK
R2l
ICI
SH If·; IN

___

I
.._,,_.

0 OUT

(Cl

__,,

~..,---~

ENA CRC 1 OUT

CLR

I(FIG.' MR

L___

VALID RCVR
8STATUS
IC)
(FIG. 3-91

i ..

I ,2.30) STATE H

(FIG.)
2-30

~-----------r--,1----~~-~._,_1~i-----~ (Cl

r_J

<-'31:24>~

~- 1 '

~";;TEH~ f'......... I I
il(FIG.228)~
IUSTATEG

r-----,K

CRC

ENA XMIT

(FIG

Y i

1'\
I.

!FIG 2211

CRC

,. OOKL'P
TABLE

LNEWDATA<7·0>

l C R C <31:00>

,___IF1G. 2-26)
ENACRC30UT

..0

MR CRC 3

·-------------M_A_X_C_R_C_3
_

(FIG. 2·301
(FIG. 2-25; 2-28)

FF
(U)

I ARSTATED
(FIG. 2 781) ·

l.~A~R"-"-ST~A~T-'E~H-------~

CLR

IFIG. 23 0) MRSTATEH
0MR CRC3
ICCS PATH SELECTED
(FIG 2 3 1 - - - - - - - - - - - - - - - ----~

NOTE:
LETTER Dc:SIGNATIONS IN PARENTHESES REFER TO
ENGINF.ERING DRAWINGS CONTAINING CORRESPONDING
LOGIC.
Tl< Rf.:10

Figure 2·18

CRC Generator/Checker

2-30

2.7 ARB.ITRATION
2.7.1 General
To prevent collisions on the bus, only one node should be transmitting at a time. When the port commands
a node to transmit an information packet, the link goes through an arbitration process in order to "gain
control" of the bus.• For a node to "gain control" of the bus means that it is the node's turn to have the bus
within the arbitration process that is being executed by all the nodes competing for the bus. There is no
hardware or software control by which a node may sei:ze the bus and exclude other nodes.
The arbitration process consists of counting down a specific number of "quiet slots'" on the bus. A quiet slot
is a time period of approximately 800 ns during which there is no activity on the bus. Eight hundred ns is
sufficient time for a one-way trip on the bus and to detect a carrier presence. Thus, a quiet slot is a time
period allocated for an arbitrating node to detect. another node's transmission.
If a node completes its quiet slot countdown (reaches 0), the node wins the bus and may transmit. If the
node detects activily on the bus (another node is transmitting) before the countdow" is complete, the arbitration process is interrupted a,..: •tarted O\'er once the bus is quiet again. If several nodes are compt~tingfor
the bus, all but the winner will ha\:'. their arbitrati0n countdowns interrupted. When the bus i;oos quiet
again, the losing nodes will restart their countdowns simultaneously. thus, placing them ;n sync with each
other. This synchronism occurs only on a busy bus where the competing nodes will sense a "loss of carrier"
to synchronize their countdowns.
The arbitration countdown is a round robin dual countdown algorithm such th~\, if more than one node i>
trying to transmit, the lower numbered node will be given the bus Lfst. The other nodes, hl1wever, can each
gain the bus before the lower node can gain the bus again. This is implemenled by the number of quiet slots
c:;ch node must count.
The number of quiet slots tc be counte-0 down is determined by the number of the node attempting to
transmit and the numller of thr node that last had the bus. A node may count N + I + I slots or I -1 I slots
where:
N = 16 (the maximum number of allowable nodes)
I= the nod.e number
When a node starts to arbitrate, it counts N + r + I slots. If the countdown is interrupted, the node determines the number of the winning node. If the winning node was a lower number, the node restarts an I + I
countdown. If the winning node was a higher number, !he nude restarts an N + I + I countdown. Thus,
when several nodes are competing for the bus, the lowest number node wins the bus first but must count
down the N +I+ I slots to gain the bus again. The higher nodes will restart their arbitration with the I+ I
countdown and all will win the bus before the first winner can gain the bus again. As each node wins the
bus, the N term is added to its countdown value and the next higher numbered node wins the bus. Thus,
each competing node will have a turn at the bus, starting with the lowest numbered node and working up to
the highest.
The arbitration algorithm is illustrated in Figure 2-19. Note that whenever a node complete' its count.down
(reaches 0), it checks that the receiver is free (ALT PATH BUSY false) before trammitting. Transmission
should not occur from a node unless the node receiver is free to accept the ACK response. Although the
node may have completed its countdown and gained one path of the bus, the nod~ receiver could be busy
receiving a packet on the other path. When this happens, the transmission is delayed by loading 16 into the
node's counter and continuing the countdown.
The I term is included in the two countdown expressions because the lowest node number is 0. When node
0 is executing an I + I countdown, then it will be looking for J slot - not 0 siots.
•

There :s nc urbitration pr()ccss when t'ransmittlng an ACK pa1..ket itS it is assumed the bus has alreadj been acquired for the

information and ACK packet transfers.

2-31

YES

lOADCOUNTEA

LOAD COUNTER

WITHI+ i

WlTHN+l~l

LOAD 16 lNlO

COUNTER

Figure 2-19 Arbitration Flow Diagram
2.7.2 Arbitration Logic
Figure 2-20 is a block diagram of the arbitration logic. Prior to receiving a transmit command from the
JXlrt, the link is in the idle state (MX state A). In MX state A, the true state of LOAD ARB COUNT loads
the arbitrator in preparation for the quiet slot countdown. The basic slot counter is loaded with l 00 I (binary) and the down count.er is loaded with 1' + i + I.

SEE NEXT FRAME
FOR LARGER ART

START

LOAD N + I+ 1 INTO
COL?H:)OWN
COUNTEfl

YES

NO
LOAD COUNTER
WITH I+ 1

YES
LOAD Cl'l•NTER
WITH N + t t 1

I
I___

~!.Q _ __

!
I

i
LOAD 16 INTC
COUNTFR
TAKE OVER
RECEIVER CHM 1 NEL

Figure 2-19

Arbitration Fh1w Diagram

'---__J

('. FiG.'.) CARRIER DET 8

.2-3 -

(

FIG.\fSEL TPATH 8
221ll_2£L TPATH

!FIG

(FIG. 2 3)--------~-NODE ADDRESS ·2:0 .
(FIG. 2 251-i
1 0 0 1

V--'--::_::~..,.JI N

:--0

BASIC

SLOT

COUNTER
CLK

i Ki

1--+..::..:=~C!__.l

r""iFiG. 227)
I

CRY
;:

'
I; I

L\Jll.D~IK.~l~NTEH
f'OWN

BA.SIC

(FIG. 2-301 RCVR ACTIVE

Arbitration Block Diagram (a)

2-33

-~T c ~~i3
~u---'K
CLK

:'<)

iJ
Sj~-·---AL-TP-f:\_T_H..Ji ·----'1-

MX STATE 8
~
i
V

Figure 2-20

.
(FIG. 2-30)

CLR

---w.l,CU<

I'---{

~::_Q__j
i I1

BUSY

i
~ r:\
__ _L-{>o--~

iFIG.2-21).f.5.J.~CEARB

,,J~~~I

iFI('
.,
. ···•··"LMXSTATEB

"-::/

G)i-------

_ ___

0~---fc\,____...;;So.;;E"'L'-'-P~ATHC.ARRIER
V

__,

\Kl

I
~ M • ST A TE B
I I
(FIG. 225) L~.:.:.l·X~ST,:..:A~T'"'E-'-A-'---------·--H
(

SET
N
LOAD

I l

!Kl

-------~

XMIT CLK

LATCH
FF

!Kl

·-

I I

~t--t-----i')

,11'

"LI
i I -~~'i,N

f\j

YBI

,_QAD
MUX

IK)
SEL

L-----. . .8

!
'

NOTE:
LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINitJG CORRESPONDIN(i
LOGIC.

8,_____
ARB OK (FIG.)'

0--0---Figure 2·20

Arbitration Block Diagram <b)

:?-30

1 K-8941

The down counter is in two sections: the lower four bits and the fif1h bit. The four-bit section is loaded with
the node add.ress (NODE ADDRESS (3:0}). The fifth-bit section is loaded from an N load mux that sup-plies the N term in the arbitration countdown expression. The mux select inputs are shown in Table 2-3.
While the link is idling in MX STA TE A. the mux sclc..:ts the+ V input to lo~d a l into the fifth bit section
of the down counter. The I represents the N tc.rm in the N + I + 1 countdown expression.
Table 2-3 N load Mux Selection
Select Code
MXSTATEA

Input Selected
SELPATHCARRIER

True

False

True (load arb.)

N Load FF

False

Latch FF

X " don't care

When the link shifts to MX STATE B, LOAD ARB COUNT negates and the arbitrator starts its countdown. The slot counter is docked from 1001 by XMIT CLK and outputs BASIC SLOT after seven clock
pulses. BASIC SLOT is looped back to reload the counter with 100! and the cycle is repeated The time
period of XMIT CLK is 114.28 ns; hence. BASIC SLOT asserts every 800 n;, (7 X l 14.28).
Each time BASIC SLOT asserts it enables the four-bit section of the down counter which is decremented
by XMIT CLK. When this section of the down counter reaches 0, the next assertion of BASIC SLOT
a~:serte the carry (CRY) output which enables the fifth bit section to decremenl. If the fifth bit section
contains a I (N +I + I count), the I becomes a 0, !he four-bit section becomes all l's, and the countdown
continues. If the fifth bit section contains a 0 (I + I count). the CRY output goes true asserting A RBC = 0
(3rbitration counter= 0) which conditions the ARB nip-flop to ;,ct on the next XMIT CLK. If the alternate
bus path is not busy \ALT PATH BVSY false) ARB and ARB OK assert signifying a successful countdown and causing the link to shift to MX state C.
Note that after the counter has reached 0 count, one more assertion of BASIC SLOT is required to assert
the CRY output and cause ARB to go true. The additional assertion of BASIC SLOT n~prescnts the I term
in the two cour.tdown expressions.

If a carrier from another node is dctccled during the arbitration countdown, the arritrator is reloaded and
the countdown starts over. The node address comparator determines whether the 111terrupting (winning)
node is alx>vc or below this node in order to determine the new countdown value. (See Paragraph 2. 7. I for a
general discussion ()f the arbitrator.) The comparator compares the node address with ARB CMP ADD
(3:0) from the four-bit section of the down counter and asserts, LT (I PLUS I)* if this node number is less
than the winning node number. For example, assume this to be node 5 and the winner to be node 2. ARll
CMP ADD (3:0) is down counted to 3, the comparator A input is greater than the B input; therefore, LT {I
PLl.'S I) is false. This node is not less than the winning node. If the winner were node 7, ARB CMP ADD
(3:0} wouJd be 14 (the fifth bit h11ving been decremented), the comparator A input is less than the B input;
therefore. LT (I PLUS I) is true. This node is less than the winning node. The LT (I PLUS I) signal is used
to determine which count down value is to be reloaded into the down counter for the next countdown.
When a carrier is detected {interrupting the countdown), CARRIER DET A or CARRIER DET B asserts.
If the carrier is detected on the SEL TPATH selected by the link control PAL SEL PATH CARRIER is
asserted. The assertion of SEL PATH CARRIER causes LOAD ARB COUNT to assert and reload the
basic slot counter and both sections of the down counter. The fifth bit section of the down counter is again
loaded from the N load mux; however, now the mux is selecting its input from the N load nip-flop (see
Table 2-3).
During the countdown, the false state of SE,~ PATH CARRIER holds the N load nip-flop reset. When
SEL PATl-1 CARRIER asserts, it allows the .I input to the Oip-nop to look at LT (I PLUS I) from the
node comparator. If l T (I PLUS I) is true (this node is less than the winning node), the nip-flop is set and a
I is loaded into the fifth bit section. If LT (I PLUS I) is false (this node is higher than the winning node),
the flip-nop remains reset and a 0 is loaded into the fifth bit section.
The output from the N load mux is latched up in a latch Oip-llop. When SEL PATH CARRIER negates,
the N load mux selects the output of the latch nip-flop thus maintaining the fifth bit selection after SEL
PA TH CARRIER negates.
As described in Paragraph 2. 7. I, a round robin arbitration algorithm is used in which the lowest-numbered
node wins the bus first, then the next higher, and so forth in a continuous loop. For the loop to be contin11·
ous, node 0 must follow node 15 in the same way that any node follows the node preceding it. When node X
is beaten by the preceding node (X-1 ), it restarts its countdown as I + l. Node X is not less than the winner,
therefore, LT (I PLUS I) is false and the fifth bit section of the counter is loaded with a 0. Likewise, when
node 0 is beaten by node 15 it must appear that it was beaten by a lower node and restart its countdown as I
+ I; however. in this case, LT (I PLUS 1} is true. Logic has been added to the input of the N load llip-nop
to force a() into the fifth bit section of the counter when node 0 is beaten by node 15. Thus, when this is
node 0 (CNODE ADDRESS (3:0)"' all I's) and .it has just been beaten by node 15 (ARB CMP ADD (3:0)
"" all l's), the AND gate transferring LT (I + I) into the N load llip-nop is inhibited and the flip-nop
remains reset. Hence, a 0 is reloaded into the fifth bit sect.ion of the down counter and node 0 docs an I + I
countdown.
If the link receive channel is busy on the alternate bus path, RCVR ACTIVE will be true, causing ALT
PATH BUSY to also be true. This condition inhibits the assertion of ARB and loads 16 into the down
counter. ALT PATH BtJSY loads only the fifth bit section of the down counter. The four-bit section
remains enabled in count mode. ALT PATH BUSY generates the I Ci by disabling the N load mux causing
it to output a 0 into the fifth bit section. The four-bit section is at all O's (countdown successfully completed), hence, as the fifth bit section is loaded with a 0, the four-bit section is decremented to all I's. Thus,
when the entire counter is enabled again, it contains a count of 16.

•

LT" less th11n

2-.15

The true state or RCVR ACTIVE inhibits a successful arbitration by reasserting ALT PATH BUSY.
RCVR ACTIVE ncgal~s after the message on the alt.;rnatc path has been received. The transmission that
is arbitrating for the bus, however. still cannot be allowed because the transmit channel must be used to
transmit an ACK response. This point in the message receive slate sequence is state I. Hence, MR STATE
I is used to keep ALT PATH BUSY true to inhibit the assertion of ARB.
The false state of DLYD HDR TO also asserts ALT PATH BUSY and inhibits a successful arbitration.
DLYD HOR TO is false if a transmission is occurring from this node (A DRIVER ENA or B DRIVER
ENA true) as shown in Figure 2-30. The transmission in this case would be the transmission of an ACK
packet on the alternate path.
·
2.8 UNK FUNCTIONS
Link functions (Figure 2·21) are commanded from the port vi<! four link control lines (LINK CONTROL
(3:0)) and eight port data lines (PORT DA TA (7:0}). The port asserts SELECT when a valid ,·unction
exists on the link control lines.
A function decoder decodes the link control lines and outputs the specific function commanded by the port.
The function commands are de•;cribed below:
A.

XMITFCN

This function initiates arbitration and transmission on one of the Cl paths. The Cl path
used is selected by port data bit 7 (0 =path A:
I ~, path 8).

RESET XMIT ST ATUS

This function resets transmission status bits at
the end of a transmission operation.

ABORT XMIT FCN

This function aborts a currently activ~ transmit operation.

The link mode conlroi, PAL receives the link control lines and the port data lines from the port. The port
data lines carry control information relating to the commanded function, and specify various maintenance
functions for the link.

2-36

rntfa){; I
FORCE CARRIER

!.FIG. 32 )

SWAPTRUE~OMPADR

RCVR A ENABLE

1----------'---t--O>

(FIG 4 21 { UNK CONTROL 3
LSELECT

I--'--'--"-------+--+- IF I G. 2 20)

PORT DATA<J:O>
(LINK CONTROL <2:0>
LINK

~R_c_v_R_B_E_N_A_B_L_E

MODE

_____
}AUD RCVR PARITY

CONTROL
PAL

EXT MLOOP

(FIG. 2·31

( f'IG.)

(Ml

2 18

INT MLOOP

2-25
:l-26

FORCE ARB
~X_M~l_T_P_A_T_H_B_S_E_L_ _ _ _ _ _ _ _ _-t>tD

XMIT CLK

SEL TPATH El

~----------+}

FUNCTION
(M)

XMIT
1------'-----.....,..-+
iFIG. 2·25!
XMIT FCN
RESET

STATUS

}

SEL TPATH AJ

Link Functions

FORCE PATY A

(FIG. 220i ARB OK

ABORT

L_}
Figure 2-21

<'ORCE PATH B

(M:1

XMIT fCN

DECODER

iFIG 2 20: 2 2fi\

ic!G. 227i

NOTE:
LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CO'HAINING CORRESPOlliDING
LOGIC

The control informatilm and maintenance functions are dcs<:ribed behJ\I:
A.

X\11TPATHBSEL

f'hi:, signal sde,':s the Cl path associated with
the XM.IT FCN command.

RCVR A EN ·\BLE

This signJI enables path A in t.he link rcccil'cr
making the nod.: a,·cessibk on Cl r;!th A.

RCVR B ENABLE

Thi' signal enables path Bin the link receiver
making the node accessible on Cl path B.

EXT MLOOP

This is a maintenance functi•m that allows the
link to receil'c its own tran,;mission by k><Jping.
on the >clcclcd Cl path.

INT MLOOP

This is a maintenance function th2.t allows the
link Ill receive its ,Jwn tr•insnmsion by looping
inside the transmi~. dri1cr' and inrut receiver
detectors . This opcr.1tion will !l(J\ mtcrferc with
th<: Cl opcrati,m ol' oth,~r nodes.

FORCE CARRIE.R

This b a maintenance funnion that cau;•cs the
link to see a dctcct<:d ;;arrier.

FORCEARB

This is a m'iintcnancc functifln that caus;:s t.hc
link 10 force a >uccessful arbitration.

VALID RCVR PARITY

This is a main1..-:nancc functi<)O that is used to
generate parity crrc·~s in the receive channel.

S\VAP TRlJE/COMP ADR

This i> a maintenance functi,Jn that causes the
true a:1d comrlemcnt:1r\ addres;; sources w be.
sw,:ppcd resulting in an addrc's mbmatch.

The tram;mission path select signal (SEL PA TH A ur SEL PA TH Bl ;mens a ,·nm> ponding FORCE
PA TH signal afkT the node has successfully arbitr,ucd f,:ir thl' bus ! ARB OK true) The FORCE PA Tll
signal cnablt's the corresponding path in the receive chunnei in preparation to re.cc1vc the AC'!\ rcsron.;c.

2-38

2.9 LINt. INTERFACE SIGNAi~<;;
Figure 2-22 illustrntes the link interface sign;1ls. 'lost of the link interfacing" with the· PB Figures 2·23
and 2-24 arc 11ow diagrams of a typical transmit and receive operation. The How diagrarm. h11?-hlight the
interface signal> to illustrate their basic functions. Some other maJ<lr signals. internal 1,1 the link. Jrc included for wmpleteness. The two 11ow diagrams utilize mo;,t of the interface sign,ils and explain their basic
functions. Interface signals not included i'1 the flow diagrams arc the three clocks 1PORT CLK. X\11T
CLK, RCVR CLK). the node address (NODE ADDRESS \7 0)), and INITIALIZE.
PORT CLK is n:cci\ed from the PB while XMIT CLK and RC\'R CLK arc g~n.etJt.:d within the link. Al.I
three clocks are used in both the PB and the link.
NODE ADDRESS (7:0) is sent to the port (via the PB.I ;ind inserted into the transmitted packet as the
source byte.
INITIALIZE i• i.:sed for system initialization.
The flow diagrams illustrate a typical crrnr-frec sequence of a transmit and a rccei•c oper.<1tion. They c.1;1
be used in conjunction with the receive channel block diagram \Figure 2-3) and tbc transmit channd lilock
diagram (Figure 2-1 ~). or with the more det:uled state diagrams di~'u:•sed in Paragrnph 2..I0.

INITIALIZE

PACKET
BUFFER

; _ -L _,,.. XMIT FCN

i'ORTDATA<7:Qo

~-i---XMITPATHBSEL

XMIT DATA ENABLE ._-i
NODE ADDRESS <7:0>

(PB}

SELECT
LINK CONTRf)l. <3:0.>

r _,,..RESET XMIT STATUS!

1- _ -• RCVR A ENABLE
I

1
XMIT DATA <7:0>
.J 1
i1--~~~:.:...:...::.:..:..:.:.'-'-'-'--~~-•":j
XMiT DATA PARITY
! l - - ""RCVR B ENABLE
I
I

XMIT BUFFER EMPTY
XMIT ATTENTION

XMIT STATUS<7:0>

-r 4

l"'----'R:.:;C::,.V::.:R~A'-.!E:;..N:,:.A.:.:;B:..::L:.;.;E_ _

RCVR B ENABLE

r..

RCVR DATA PARITY

~VALlu RCVR DATA
l

LINK

PACKET LENGTH
RCVR PACKET END

r--

'',.....

VALID RCVR STATUS
CRC STATUS
ICCSPATH B

PORT CLK

r--

-·-

XMIT CLK
RCVR CLK

,__

Tl( 8615

figure 2-22

Link Interface Signal'

2-40

!
1

1
j

Start
C AC bytes are
inserted into the
packet.

•SELECT
A valid function exists on
. LINK CONTROL lines. .

Trailer bytes are
inserted into th~
packet.

•uNK CONTROL <3:0)
XMIT FCN
I Port commands

~ a transmit function via

SYNC/TA GONE
Packet ha; been
transmitted.

LINK CONTROL lines.
PORT DATA <7:0>
XMIT PATH B SEL
Port sP.lects transmit pat
via PORT DAT A lines.

WACK
Wait for ACK response.

L;nk arbitrates for
the selected bus.

ACK RCVD
ACK response has been
successfuily received.

Link transmits header (bit
sync bytes and sync

character byte).

'),11/!IT ATTENT,ON
An ACK response has
been detected.

*XMIT DATA ENABLE
Link is ready to receive
data from the PB.

*XMIT STATUS <'.7:0>

Transmit status
available to the
*XMIT DATA <7:0>
•xMIT DATAPAAITY

port.

Packet bytes (with

parity) are transferred
from the PB to the link.

'XMIT BUFFER EMPTY
Ali ;lacket bytes have
been received from the_

•LINK CONTROL <3:0>
RESET XMIT STATUS
Command {via LINK
CONTROL lines) t0
reset 11'0St of XMIT
STATUS bits.

=-.J

PB.

Done
"'lnterfoce signal

Figure 2-23

lmcrfac(' Fi<m Diagram -· Trar1>rni< Orx·ration

Start

• RCVf; PACKET
Lasr byte ot pdcke

*PORT DATA <:70>
'RCVR A ENABLE
,
*RCVR B ENABLE
P_ort selects receiver path
via PORT DATA l;nes.

body has been
transterred to PB.

~\/AL~D RCVR STATUS.

\/.a!id r.eceiver status
int·;'ln·:;3tic,n k avaiiabi£'

:o tne port.

ICCS PATH SELECTED
Carner is detBcted on bus.

'CRC STATUS

I ;r- .iicates CRC status ori
J .receivPd packet.

CHAR SYNC
Carri!~r is a vatid packet.

'iCCS PATH B
indicates over which Ct

Path the pack e1 was
*VALID RCVR DATA
Valid packet data

~ece;ve(1.

tn l)e transffrrt3rl
to PB.

-;..cK

"".'·:-ctr1sJn!t an ACK
'RCVR BUFFERS FULL,
True if PB receive
l
bdfers are full.

*RCVR DATA <7:0>
'RCVR DATA PARITY l
Packet Lvtes \with
.

parity-) are transferre-li
from link to PB.

;

f:); NACK) ;nicket.

ACK DONE
ACK !Ot NACK) paGke:
has be-en ~1ans.rnittfld.

C_______..
Dont'

)

'PACKET LENGTH
Data being transferred
to PB specifies length
of received pacl<:et

""Interface signai

Figure 2·24

Interface Flow Diagram -- Receive Opcr:ifrm

2.10 OPERATING STATES
Tile foJllowing description of the four lmk operations utili1cs the ,;1:1tc di;1grnms ,.onlaincd in 1hc engineer·
;ng drawing sci. The varioui; swtcs arc ,h<•wn in the diagrams ;15 circks. A path loopin11. back into a .:irclc
holds the link in that state so long as the :;ign3! condition sh(iwn in the loopb;tck path is true. -; he link goes
wit;; next ,late if the :;ignal"s conditi(m ,;hown in the C1)nncctmg path to the next stare is true. Where no
k~1pback paths are shown. the link stays in that >!ate for one dock pul-;c to perform th<: indicated task(sl
and then advances to tk next stuti.: .
.\l><' included m the draw· g set is a X~llT/RCVR MSG State Flow Diagram. The diagram shnws the
numrnl "tatc flow;; for a message transrrnssion and ACK reception operm1on and for a mcs<.agc rcccpti,m
and ACK transmission 1>peration. The 1.!i.1gram i!lm.tratcs whrn PA Ls arc used and how rbc scqucm.:c shifts
from one PAL to another as the oper::1.ion is cxccut.ed. The diagram illusiratcs a basic point in link operation:;; that an ACK receive scqucn-.:c i:, a part of the mcs>agc transmit sequence in that the message trans··
mit scqucnct is nm complete until tile ACK receive sequence is done. Likcwis~. the ACK transmit
sc4acncc is pan of the mc.ssagc nxcivc sequence and that the message rc,ceive. ~cquencc is not complete
until the ACK transmit. sequcni:e is done.

2. IO. t

Mess11gt> Tr1111smit

figure 1-25 illustrates the mcss~ge transmit stale logic and j, used in conjunction with the MESSA.GE
XMIT STA TE diagram in the cnginc~ring drnwing set Two PA Ls are used for the message XMIT sl;1te
sequence.
INITL\UZE from the JXlrt asserts TINIT which initializes the hr.k a.orl asserts MX STATE A from PAL
no. ! . \1X State A i,; the tnmsmil idl~ state. When the port C(•mmand> a transmit function, XMIT FC:\
asserts from the link control PAL causing TXMIT to assert and tr;msfcr the link to st.ate B.
The link arbitrate-> for the hus in :-tate B. When the Mbitra!ic•n is successful. ARB as>crts and the link
transfer~ l(' >late C.
In st;1t~ C th<~ link transmits the bit syn('hronizatmn bvtes '1.nd the ,;vnc ~haractcr bvtc. After the sync
chuactcr byte I.as 0..·en transmitted. S\'NC/TR GONE assens :.ind sends the link to.slate D
"
In state D the CRC gcncrntor i;, enabled (except for maintcnanc:c loop operntions). the second MSG XMIT
Stale PAL 1;; cm1blcd, and the link goes to st~tc E
PAL O•'. l ,;tays in state E for the rest of 1lic transmission
occurs, PE asserts and transfers the link to ,tak F.

long ;is 1hen: is no parity error. If a parity crr0r

II the iink is plac·cd in state F. PAL no. 2 i> reset and XMIT ATTENTION is assc,rtc'd to the port which
will lhi:n abort the transmission. The link then rcrnrns to state A.

PAL r·•. 2 moved from its idle >late (State G) w ~talc H when PAL no. I asserted MX STATE: D.
From ·ilak H the link gncs to state I "here the destination byte is clocked into the destination address
re ·~:st er.
The iink then transfers Ill >tatc J where it waits for the body of the packet to be uansmitt.ed When the last
byte ,if the body is transmitted. XMIT BUFFER EMPTY ii r~ccivcd from thl' PB and transfers the iink to
><ate I< (if thi;; is not a mc1intcnancc operatmn: if :~is is 3 maintenance operation (LOOP true). the link goes
directly h:- >late L].
In state >< the CRC bv1c:; arc trclnsrnitlcd. \1-'\X CRC 3 m;sen.s when the last CRC bvic is tr:rnsmi1kd.
MAX CRC 3 c:1u,;es the link to trnn1for Vo slat"' L.
Ir: state L the p;1'·ket trailer byie.,; are transmitted. Aft,~r t!ic tt·aikr bytes arc tram;rniHcd. Sr NC/TR
liONE asscns anc transfers iht link tel .statr M.

MXSTATE F

B
{FIG 2·28) {

ARSTATED

..--

AR STATE H

J B/

J
RCVR CLK

FF
G (B)

ACKR~

ch-

r K CLR
(FIG. 2-30) MR ;TATE

(FIG. 2·12)

.G:(FIG. 2-20l

SET
PORT CLK J XMIT
C FF
(FIG. 2_211 XMIT FCN K {B)
CLR
(FIG. 4-2)

INITIALIZE

H>:

~XSTATE M

(FIG. 2 20)

T FLAG

FF
iFIG. 2·21)

(B)
XMITCLK

MX STATE A

ARB

MX STATE B

TXMIT

MX STATE C

LOOP

MX. STATE 0

TABORT
TINIT

c
c

(FIG. 2_121 TDATAPARITY ERROR~

j (A)

(FIG. 2_261 XMIT DATA ENABLE

XMITCLK

FF
!B)

MX STATE F
~

(FIG. 2-121

MAX CRC3
SYNC/TR GONE

LOOP
( IG. 2-2 1) XMIT BUFFER EMPTY
(FIG. 3-2)
XMITCLK

TINIT
FF
(8)

XMITCLK_ C

C( "G 226)
FIG. 2·27

{
(FIG. 2-30)

MR STATE F

HEADER TIME OUT

J (B~ J FF
c

RM L K
NOTE:
LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEE RING DRAWINGS CONTAINING CORRESPONDING
LOGIC.

Figure 2·25

Message Transmit Staie Logic

2-44

MXSTATE F

041

CLK

ACK RCVO
(FIG. 2-18)

INITIALIZE

MX STATE E

. ABORT RCVR

MX STATE G

'-MX STATED

TABORT

.....

)

{FIG. 2·30)

XMIT STATUS 4

ACK RCVD

....

MX STATE M

~
-

(FIG. 4-2)

MSG
XMIT
STATE
PAL
(A-Fl
(B)

(FIG. 2·27)

bYNC/TR
GONE

MX STATE H
MX STATE I

MSG
XMIT
STATE
PAL
G-M

MX STATE L

(6)

MX STATE M

MX STATE J
~

MX STATE K

CLK

ABORT
RCVR

c (B)

~
A

ACK RCVD

~ ( 2-28
2-30

FIG.)

FF
(8)

XMITCLK

I'K

.....

c
CLR

Jn state M the link has completed its transrnis;.;011 and is waiting for the ACK rccci1'c ,;cqucnce to com·
pletc. The end or the ACK rcc·civc sequence is indicated by the assertion of AR STA TE Dor AR STATE
H from the ACK receive state logic. Either of these signals assats ACK RCVD to both PAL> causing
them to return w their idle :;tales. ACK RCVD also negates TXMIT Ill complete the nm,sagi: XMIT
sequence.
When the link enters state M, WACK (wait for ACK) is asserted to the ACK receive state k)gic enabling
the ACK RCVR PAL to start the ACK receive sequence. When the ACK response is received. ACK
RCVD asserts and negates WACK.
The port can abort the transmission by assi;rting ABORT XMIT FCN via the Ll1'.K CO'.'JTROL lines.
ABORT XMIT FCN asserts XMIT STATUS 4 and then T ABORT via two flip-Oops. TABORT is applied
to both messag..: XMIT PALs resetting them to their idle states.
The MSG XMIT sequence i> also reset by HEADER TIME OUT which asserts ·\HORT RCVR to PAL
no. I. HEADER TIME: OUT i> asserted by the MSG RCVR stak logic when a carrier is detected but syn''
character recognition does not occur.
2.10.1. l Transmit Contr.~' Logic - Figure 2-26 illustrates the logic that controls th<: llow of data through
the transmit channel shown in Figure 2-12. The control signals arc regulated by the 'talc signals generated
by the XMIT state PAb. The assertion <tnd negation of the control signals can be related to the task(>)
performed in the various ~tates a> shown in the XMIT state diagrams.
ENA SYNC/TR CNT is asserted by the appropriate STATE signals and enables the sync/trailer counter
to stan counting.
ENA SYNC/TR gates the bit sync bytes and the tr:iiler bytes onto the XMIT DATA bus. ENA SYNC/
TR is negated by ENA XMIT DAT A LATCH which gates the padet bytes from the PB onto the XMIT
DATA bus. ENA XMIT DATA LATCH also asserts ENA XMIT DATA PARITY.
ENA XMIT DATA REG isolates the BUS TDATA bu;; from the X\flT DATA bus while the CRC bytes
arc being placed onto the TDATA bus. TINIT initially assert~ ENA XMIT DATA REG which passes. the
packet bytes onto the BUS TDATA bus until XMIT BUFFER E\.iPTY is received from the PB. XMIT
BUFFER EMPTY negates ENA XMIT DATA REG which remains negated until all tl>c CRC bytes ari;
placed onto the BUS TDATA t •s. When this occurs. MX STATE L asserts thereby re-asserting ENA
XMIT DATA REG for the trai.er bytes. MX ST ATE L alc;o as.~rts SEL TRAILER to gate the trailer
bytes out or the sync/trailer PROM onto the XMIT DA TA bus.
A DRIVER ENA and B DRIVER ENA enable the driver;, that output the transmitted packet onto the
selected Cl path. During a message XMIT operation. the selected DRIVER ENA signal is asserted by the
SEL TPATH signal selected by the port via the LINK CONTROL line>. and by MX STATE C. The
DRIVER ENA signal is negated during MX state L when SYNC/TR GONE asserts. During an ACK
XMIT operntion. the selected DRIVER ENA signal is asserted by AX ST ATE B :rnd LAST RCVR ~· B.
LAST RCVR =Bis true if the last message was received on Cl path B (ICCS PATH B true). In this case,
B DRIVER ENA asserts to transmit the ACK over the same path ,Jn which the message wa' received.
Conversely, ir the message was received on Cl path A. A DRIVER EN/\ would assert, transmitting the
ACK over Cl path A. ThC' DRIVER ENA signal is negated during AX state H when SYNC/TR GONE
a:;serts

Tf ;G .' 18

fiG. 3 2:

---;~E~.•l\~A?.C~R~C~3~0~~;T~;-;---·----X'Vl•T BUFFER FMPn

(

AX STATE f
If

S>::c iRA:d.P

2"3' J----------:A~X-;-S::T;::A::T:-::E.:.B_ _ _ _
MX STATE C
E"iA ACK SRC·-----'r--"L

I...._

.....:_:::1

XMi.T
DATA

ENABLE

~UFFE?R EMPTY

<F!G. 3-?'

,F,,G c2'.

LOOP

\FiG;>2s:,

MXSTATEC
AX STATE B

'flG. 2-.3l { _- AX STATE H
iF!G 2-25'

MX STATE L

'.FIG.~JI

!CCSPATHB
{

DR1\i( ~~
[r~_A,

Xo,llTCLi<

le{:..,~

E>-LJ

MR STA~!: y

----i
l

rl
l

;B: J'
.,,,

~ER

'F ·G. 2 2s: _ _ _ _ _ _ _ _ _ __:M;..::x:...:.s.:_T.:-_A::_T:_E~c:__J

Figure 2-?6· T ran~m.1
. . ; Cc1ntrol Logic

2.IO.L2

frahft'lit Sf,etus - Ligh: .t:,m>rnit ,u:u> t>:~, \X\flT ~·L\Tt''.

'talus ()J ~~ tr~1n~rni 1, 1.1pcrJtinn. t.~l°'. F:1~.urc "7·17

l.~._.'.d
indit:.-,~{.,\ 1he
;;i•·: ;,L:•'li' v.i1h X\lll

I'b,' ~·::.'.' :1r-c- H\:iiL:1bh:

A TIE'\TIO"-.
X\UT ·\Tll'\TIOS i;, ,J'<,t:ncd when ii. r<':i['<Jfl'i<' i> r.:<'<';1,_,J fr··"n th~ J,·.,1imwi;•:: :···:,fr •\CK \11 \i \CK 1,
re\..·Civ(>:\i fn)m lhc -dl'»,.tinati1Jn f'l1.xk {_.>\CK f\::_~·kd 'lin1,·ou<: ~ ~:!J~--" i wh\'n .tr:111..;rrn t

"h~n nn rc~f".Jn~·- i.~

rarity error .xxur>. .:•r when ;in :tbort 1ra1N11i~si 'n .:cimmw:d ., is>ucd (.\BORT XMlr f'C' .;; ;i:<,crl~dl

\:\tlT ST.\ TtS ~

This bit is -~t if ~l p..1ri't\ (".r.r,n 4~ dt"t1..~.\:l('d -.'-'t·. -:_he dri-;_;1 ·.'.•n the Bl ··s
TDAT•\ bus in :he tr.rnxn·,i c:h:1nnci d>JfHHl ••:,rhff'l>'i<'fi. ·\ f':>T:!\

error will c.m:><: .')<'\lJT \TTl \iTJO'

. "'-' ''"'"'ncJ t;· th<: [';<n

*hich "'ill then :1b;or1 1hr tr.msmi<».ion.

\MIT STATl86

X\HT Sl'.\HS 5

.X\HT STA Tt S 4

Thi .; blt i.\ M::. l' h~~n .;i tr.Jn~rn·i,~1;,m i~ ~tt)t>-r·:r:.d b~ dit' ab-:x·t fu.n . . ·tkm:
;ABORT X\flT n St ,,,mni<indcd h,~ ~nc f'l.1r:. >i:1 :.ht LINK
CO!'\TROL lint'>

X\HT STATUS 3

Thtl bi1 is'<': when an :i:·b:tr:ili•:•n ;:ountdu,..·~ f13> n:.1.::h<.'d 0. It dclC';.
not. nc"'c.':S))J.ri\ rnc~:r th;f J n--.Htstnts.sion w;H K<:ur .fx·.~~. P1nj~rar'h
:.~ i.

XMIT STA.TL'S Z

This bit i;; »et when u NA(!\.'' ret:i:ivcct :c.1m the dc,,1in:J1iC1n n•.>dc.
\ '\;·\CK rcspon<i<:. .::ID'<'' X\1!T .\PT NT f(l~, w as-.cn hi th<'

pc)rL

XMIT ST:\Tl;S l

Thi' bi1 b sc: wbc.r, Jr \( ·11.. '' rc:cc1vt'<T
lh·(' J.<:,lln:!li1111 m><.k
.\n ACK rcsp.~r;s.: c;tux-.. X \UT ATlL '<TH)'\
:i.''"':
th~
rxirt,

\MIT STATUSll

Thi:\ blt i5 ...ct "-hc-r. a H<L'1~-:-'."\~· <·:per.-tti1)n '""
Xl'-11T ATTL'>iT!ON v, ;'""';td

p;•1~i;rc,~ or 'IA'h\.'"\<-'Vt'~

(FIG. 2_121 TDATA PARITY ERROR
NOTE:
LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
LOGIC.

"'G- 2·31

XMITSTATUS7

FF
(L)

XMITCLK
----..iCLK
CLA

{FIG. 5·2; 5-11)

CARRIER OET B

XMITSTATUS6

CARRIER DET A

XMIT STATUS 5

J-----------------------+--~CLK
l
CLK

{
22

(FIG. - l)

ABORT XMIT FCN __________..__..J FF
-------------:..:.:.::..:.;.;...;.;_;,_;,;:._

XMITSTATUS4
iFIG. 2-25)

RESET XMIT STATUS

I-

______.;.;T.;_;IN.;_;1.;_;T______~{ L) ..__CLEAR
_ _ _XMITSTATUS
_ _ _ _ _........_____.......,,..__~

(FIG. 2-25)

ARBO= 0

{FIG. 2-20)

XMIT STATUS 3

XMIT STATUS 2 (NACK)

(FIG. 2 _28 ) _ _ _ _ __;,A.;.A.;.S;;..T;..A.;..T;..E;..;B;;.._-r-......

(FIG. 3-3)

XMlTSTATUS 1 IACK)

RCVR DATA6
ACVA CLK

(FIG. 2-31

{----~
{

(FIG. 2_251 MX STATE A

XMIT
STATUS 0

ACK RESPONSE

AR STATE H

XMiT
i...;..;A.;..TT.;..E:.;N.;..'T;..l..:;O;..N_,,. !FIG. 4 101

AA STATE 0
{
FIG. 2 -28 1 AA STA.TE H
ACVACLK
RCVA CLK

PORTCLK

------"'C CLA

TK BS:i'S.

Figure 2-27

Transmit Status
2-48

2.10.2 ACK Rl'ceile
Figurc :2<28 illusmucs 1hc 1\CK re<:ci\c state logic and i; tbcd in ,-..rnjunclinn ,,:J: the the ACJ..: RC\'R
STATE diagram in the engineering drawing set. Two PALs arc used for the ACK RCVR 'late 'cywnc:c.
2.10.2.1 ACK R~eiw PAL States - INITIALIZE frnrn the pun initialize,. tl1c r«c<:i': <.:h:rnnt'I nnd
:i>scrts RIMT to both ·\CK RC\'R PA Ls rlacing them into their idk states (sbtc \ for PAL thi. l; stale E
for PAL no. 2). The linL ts transft.'rrcd to AR stat<' B when PAL no. I sense, 1h:11 a \'cllid packet i< bcmg
received (CHAR SY:\C true). that the receiver is waiting for an ACK rcspi.msc I WACK trud. and that
the packet is an ACK tRDAT REG 7 ·~ l l r.ither than .:i message packet.
in swtc B the packet true destination bvtc is checked. II a mai..:h is •.1btained (DST< \f P uud. the link
t.ransfcrs to state C
Jn :-iatc C ACK RCVR ,t,nc PAL no. 2 i> enabled (AR STATE E asserts) and the compkl1lcnt destination byte is checked. If a destination m.it.:h i,; obtained (DST C\tP true) PAL no. 2 1L<>1·e, tu state F. P·\t
r10. I remain> in stale C until the ACK RCVR state sequence is rnmpictcd
Stale D or PAL no. 1 is a "rccci\·er clear" state which i,; cntcrcJ if ,in improper re:-ponsi;· is obtained in
st<ttcs A. B, or C State Dis entered from state:'\. if CHAR SY'\iC ,10-j W \Cl< are true but RDAf REG"
0 ~ 0 (thi,; is a mc~sagc packet. not an ACK rcsoom•cl. State Di-; entered from \(Jte 8 1! :1 true dc,linatii.m
mismatch occurred. State Dis entered from siatt: C 11' ;1 complcmcntarv dcstin~:ion mi>match 1>..:currcd
After clearing the various receiver function,;, PAL no. I returns to the idle swtc t\t:ttc A:.

In 'late F the packet sourc,, byte is checked. The link then passc' tu sl;itc G pruvided this 1' ilill :i maintenance operation (11'\T MLOOP falsc). lfthi;; is a main'.cnance iJpcr,ttion (INT ~11.CXW true). t.hc link goc.;
tu state H.
In state G the CRC bytes are input tu the CRC chcci<.cr \\hi;;h checks fnr any (RC error. When !\1:\X
CRC 3 asserts (last CRC byte into the CRC chcd.er) the link move' to stale H.
State Hi;, the la>l wite i!l the ACK RCVR sequence. In thi;; st.1tc :.hl' ..,rious rcceivt· functicms are clc.1rcd
and then both PA Ls .m: returned to their idle states.
The LI>.! state in a MESSAGf; XMIT stat.: sequence is stat:: M. When MX ST.\ TE \1 .i«;er1'. ,rn \CK
timeout counter is enabled and st.trts c,lunting. If. .irtcr ~.60 µ:i. the ACK RCVR sqJ.:n..:c i,; not .:,Jmrlcte<l. the counter asserts ACK TO which terminates the sequence and return' both .\CK RCVR PALs tc.1
their idle states. The fl<lrt then reads status bit:> to determine the mrnblc.

(FIG. 2·25)

IFIG. 2·3)

{--

(FIG. 2·21)

WACK

AR STATE A

CHAR SYNC

AR STATE B

ICCS PATH SELECTED

AR STATE C

ROAT REG 7
ACK
RCVR
STATE
PAL
(A·D)

EXT MLOOP

{

INTMLOOP
RINIT

IFIG. 2·30)

AR STATED

DSTCMP

(FIG. 2·3)

ACK TO

!Bl

ACK
TIMEOUT
COUNTER
RCVR CLK

MX STATE M

RCVRCL~

CLK

ENA
CLR
CLK

G
.....
.....

(B)

MAX CRC3

(FIG. 2·18 l
NOTE:
LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
LOGIC.

Figure 2-28

ACK
RCVR
STATE
PAL
(E·H)

ACK Receive State Logic

2-50

RCVR CLK

-.. CLK

...

AR STATE E
AR STATE F

AR STATE G
AR STATE H

2.I0.2.2 S~·nc Charllcter Detect Enable PAI.. - The purpose of th.: :;ync char;Ktcr d~te,·t cn.1bk PAL
(Figure 2-3) is to cnabk the ;;ync character detector when a packc: is c.x1J<:<::tc·d and to inhibit the dc:wct1:1r
when trcins111itting from this node. The sync .::haractcr detector :-.hould be enabled during the fnllowing
times:
A.

During an internal maintenmwe loop operation

,\ftcr a t.ransmission when an ACK packet is expected

To receive a message packet from another node taking care not to respond 1<1 transn1ission•; frGm
this node (transmi&sion of an ACK packet).

Figure 2-29 functionally illustrates t.he sync character detect e<lable PAL. ENA SYNC DET is asserted by
any of five signals applied 10 an output OR gate.
When in maintenance loop operation, I NT \1.LOOP is true and enables the syn(: detector.
The next two signals enable the sync detector when an ACK packet i' received. One is generated b'
ANDing CARRIER DET A with the negated state of ICCS PATH B while the 1Jthcr is generated by
ANDing CARRIER DET B ,ind the asserted state of JC:CS PATH B Thus, the two gates look for a
carrier presence in both Cl paths. Enabling of the two gates is restricted to ACK packets by ACK ENA
which asserts while waiting for a.n ACK packet (WACK true) and after a loss of carrier has been sensed.
The carrier lost would be the message transmit <:arrier from thi<. node. ICC'S PATH B (true or false)
enables one of the AND gates in the ACK ENA logic. When that gate senses a loss ,\t· c;micr (CARRIER
DET negates), ACK ENA asserts and is latched. The next time a carrier is sensed (the ACK respon,,~). the
output AND gate is enabled and assen:; ENA SYNC DET via the output OR .!!<Ile.
The last two signals enable the >ync detector when a message p:ick.:1 is rncei•ed. The signals arc generated
by Al\D gates which arc enabled when the node is not transmitting a message packet (both FORCE
PATH signals false), and a carrier is dete~ted on one ,if the Cl paths. The gate> arc inhibited by trailer
delay (TR Dl Yl which is true at the end of an ACK transiu·sion when the packet trailer is being
transmitted.

WACK
C\RRIEROETA

,.--------+--------~

I',;:cs

('FIG.·.)

2·3

(FIG 2 31

PATH

'CARRlE R DET B

ENA
SYNC

DET
MR STATE I

,,--\-__.:~::: :::: :,} ~o"
L-o<J
NOTES:
L THE LOGIC IN THIS FIGUR!:: IS CONTAINED
ON SHEET J OF THE ENGINEERING DRAWINGS.
2 SIGNALS GENERATED INTERNALLY.

Figure 2-29

Sync Character Detect Enable PAL

1-52

G,_________

FORGE PATH A

}

F_O_R_G_E_P_A_T_H_B________

<FIG. 2 31

2.10.3 Message Receive
Figure 2-JO illustrates the message receive state logic. It is used in conjunction with the MSG RCVR
STATE diagram in the engineering drawing set. Two PALs arc used fnr the message RVCR state
sequence.

INITIALIZE from the purl asserts ABORT+ !NIT FCN which in turn asserts RINIT. RINIT initializes
the logic in the receive channel and places the two MSG RCVR state PALs into their idk states (state A
for PAL no. I: state M for PAL no. 2). When the receiver is not disabled due to transmission from the
transmit channel tRXMIT false), a valid packet is in !.he receive channel (CllAR SYNC true), and 1hc
packet is recognized as a message (RDAT REG 7 """ 0) and not an ACK: PAL no . I transfer' to MR state

B.
In MR state B. V,\LID RCVR Di\ TA is asserted to the PB indicating that a valid packet is being received.
and PACKET LENGTH is ,1sscrtc;d to the PB indicating that the byte. being transfccrcd co: '.ains p,ickct
length information. Als<J, the CRC checker is enabled and starts rccei\ing the packet bytes. The link moves
to MR slate Con the next clock pulse.
In MR state C the true destination byte is checked. If a mat•:h is obtained (DST CMP trud. the link moves
to state D. PACKET LENGTH remains asserted in state C as th<: byte being tram.t'errcd to the PB contains packet length infc'rma'.ion.
In MR state D the complement destination byte is checked. If a match is obtained (DST CMP true). the
link moves to MR state E.
In MR state Ethe packet source byte is docked into the true and compkmcnt ACK destin:ition registers to
serve as the destination for the ACK response. The next RCVR CLK pulse moves the link to MR state G.
PAL no. l remains in MR state G for the rest of the MSG RCVR state sequence\ The assertion of i\,1R
STATE Ci enables PAL no. 2 in that it allows it to move from its idle state (state M) lo state H when its
cond;ti1m signal (RCVR PACKET ENDJ is asserted.
If anv of the three condition tests made bv PAL no. I fails. the link is tr:rnsfcrrcd to MR :,talc F. Failing
any l)f the Lhrcc tests would be:
·
J.

While in state A with RX!\1JT false, CHAR SYNC aS>erts but RDAT REG c~ I (this is an
ACK packet)

A true destination mi,'lnatch occurred in state C
A complement destination rnisrna1ch occurred in state D

In MR -.;tat<: F the receive logi..: is cleared, and PAL no. I returns to the idle state (state ,\) 0:1 the next.
RCVR CLK pulse.
PAL no. 2 remains in its idle stntc (state M) while the packet body is being tr.msfcrrcd to the PR Al'ter the
l<tst byte of the bod} h;1s been sent 10 the PB, the PB asserts RCVR PACKET END c1nd PAL no. 2 goes t(I
MR state H.
In state H the packet Cl~C byte,; ,:re input to· J1c CRC checker. When the hist h; tc is in the checker, !\JR
CRC J asserts. If there is 110 CRC error, CRC OK is true when \llR CRC 3 ;Jsscns. In this case. the link
nwn:s to state I. lf there is a CRC error, CRC OK is false and the link goc~s to st,nc L
In st.ate L the MSG RCVR slate scqucnt·c is aborted. The ;cc·civc channel is dcarcd. PAL no.
io its idle state htatc ;\),and PAL no. 2 moves to its idle sute (stall: Mi.

is moved

ICCS PATH SELECTED

'\-__P_A_T_H_S_E_L_T_(_)_ _..,.(';')

MR STATE E
i FIG 2 30) ---'-'-"-'------,

FC
IJI

ICCS PATH SELECTED

CLR

ARB OK

!FIG. 2 201

\FIG. 3 '3)

RESET RCVR

HI------'

:'vlSG

(FIG.2251{

RDAT REG 7
iFIG. 2 121 - - - - . RCVR ACTIVE
B 1--C-H_A_R_S_r_'N-'c-4"1

_;X~M~1~1T~S~T~A~T~U~S~4-----~

RCVR
STATE
PAL
(AG)

LOOP

_ _;,;_.IN~l~T_IA~.L~.l~Z~E------~

!FIG.

(Ai

23){~CMP

ICCS

MR STATE F

r-t11o \FlG. 2·3l

MSG
E"ID I INTO

MR STATE L

LOAD
ENA

MR STATE G
CLK

MR STATE K

!JI

r----AR STATED

iFIG. 2-28) {

AR STATE H
I

L-

(FIG. 2"25i

RCVR CLK

(;:-..

iFIG. 2 31

(J}

ABORT
~ INIT FCN

{F !G. 3.'.3)

i FIG. 2-21 I { _ _ _ _._... " - " - - -

:NA

MSG

AX STATE H
HDH
,.__DLYD
___
_TO
_ _ !FIG. 2 20}

ENA

PORT CLK

MR STATE J

.
~

RCVR

INT MLOOP

STATE
PAL

1-M_R_ST_A_T_E_·_K...._
.......

(HMI

MR STATE L

IA)

(FIC 7 · 1 BI
CRC STATUS
IF!G 2 - 3 ) - - - · - - - ACK DONE

RCVR CLK

{FIG. 231)

/ 26~ DRIVER

RCVR ACTIVE

"'.>---.---.. (FIG. 220)

R<:VR PACKET END

MR CRC 3

'IGJ

MR STATE I
R!NlT

0_)----+--1

FIG. /'I { _ _ _L_o_o_r_ _ _
2 21
1

A
DRIVER

PA.TH

- - - - - M..__
R STATE H

RCVR
CLK
CHAR ~YNC

~J____

RXMIT FLAG
FF

RXMIT

RCVR CL K
MX STATE C

i-;.D_A_T_A_.,. IF IG. 3 Si

!Ai

(FIG.

HEADERS TIME OUT

Fr
MR STATE F

(FIG. 2 251

HE.ADER
TIME
OUT
COUNHR

VALID
RCVH

RCVR CLK

NOTE:
LETTER DESIGNATIONS IN PARENTHESES REFER TO

ENGINEERING DRAWINGS CONTAIN!NG CORRESPOr~DiM3
LOGIC.

CLK
(FIG 2·31)
!FIG. 2 211

AX STATE A
------1
EXT M:.:.·.:..LO.:..JO.:..P
_ _ _~-~·.
ABORT+ INIT FCN

RESET liCV+i

The message receive state sequence remains in state I while the link transmits the ACK response. The
assertion of MR STATE I asserts TACK (transmit ACK) to the ACK transmit slate PAL initiating the
ACK transmit sequence. When the ACK transmission is done AX STATE H negates to assert ACK
OONE to MSG RCVR PAL no. 2. The assert.ion of ACK OONE moves the link to MR state K.
In MR state K the receive channel is cleared and PAL no. I is returned to its idle state (MR state Al. The
next RCVR CLK pulse return PAL no. 2 to its idle state (sta.tc 1\.0.
The message receive state logic contains a header timeout counter to prevent receive channel hangups. The
counter is turn~>d on by ICCS PATH SELECTED (removes the coulllcr LOAD signal) and cleared by
CHAR SYNC. It thus st.arts ..:ounting when a c:mier is detected and is cleared when the carrier is recognize<l as being a valid packet. If SYNC CHAR fails to assert. the counter times out (in 3.66 µs) and
outputs HEADER TIME OUT. The assertion of HEADER TIME OUT causes MSG END+ HTO to
assert. thereby asserting CLEAR RCVR to reset the receive logic.
The header timeout counter is enabled and disabled al the RCVR CLK rate via a flip-flop. Thus, the
four-bit counter is extended to five bits. producing the 3.66 µs timeout period (32 X 114.28 ns = 3.66 µs).
Note that the counter is disabled by WACK. WACK asserts in MX state M when the transmit channel is
transmitting a message packet. Thus. W.\CK prevents the detection of the trnns111ittcd carrier from start·
ing the header timeout period.
Other signals besides MSG END+ HTO assert CLEAR RCVR. One of these is RCAR DROP (receive
carrier dropped) which <1sscrts ff a carrier is lost during a message reception. ICCS PA TH 'iELECTED
asserts before CHAR SYNC asscr•·; and negates after CHAR SYNC negates. If a receive carrier is prema·
turcly lost, ICCS PATH SELEC". ED will negate while CHAR SYNC is still true, causing RCAR DROP
to assert. Note that CHAR SYNC is not applied to the ANDing operation until MR ST ATE E sets a
nip-flop which gates CHAR SYNC to the RCAR DROP AND gate. Delaying CHAR SYNC until MR
state E allows the header portion of the packet to pass before the node looks for c;;rrier drop-out.

2-55

2.10.4 ACK Transmit
Figure 2-J l illustr,1tcs the ACK transmit state logic and is used in conJunction with the 1\CK XMIT
STA TF diagr:11n in the engineering drawing 'ct.
1'\llTli\LIZE frnm the P<irl asserts 'i'INIT which initializes the link and a~scrts AX Sl \'TF •\ from the
ACK X)'v!IT PAI. AX state A is the ACK trans.nit idle state. When TACK I transmit ACK) is n:cciYcd
from the MS<i RCVR state PAL. the link goes into AX ~tatc B.
In state B the sync/traikr PR0'.\1 logi.; is enabled and output' the bit synchrnni~ati,111 byte' and the syn,·
character byte on!\> the Xl\11T DATA BUS. The selected transmit drivl'r is also cnabkd. When SYl"C/
TR GONE asserts. the link transfers to state C.
The link is in AX state C for one dock pube. While in state C. the ACK tvpc byte is placed onto the XMIT
DATA BUS and the CRC generator is enabled. The next XMIT CLK pulse moves the link to AX state fl

In AX state D the ACK true destination byte is pla\:cd onto the XMIT DATA BliS. The link then
advances to AX state F.
In AX state Ethe ACK complement destination byte is placed onto the XMIT DATA BUS. The link then
advanc~-s to AX :;talc L

In AX state F the ACK source byte is pbccd 0111\1 the XMIT DATA BUS. The link then moves to state G.

In AX state G the CRC bytes generated by the CRC generator arc output 11nto tl11: BljS TDATA bus.
When the last CRC byte has been piaccd onto the bw.. MAX CRC 3 asscrh and moves the link to AX
state H.
In AX state H the sync/trailer PROM is enabled again and the packet t1ailcr bytes arc output from the
PROM onto the XMIT DATA BUS After the trailer bytes have been phKed ,into the bus, SYNC/TR
GONE asserts and returns the ACK XMIT PAL to its idle st,1tc (state Al.

Note in Figure 2-31 that the assertion of each gate rnupling a b~ tc to the XMIT DA TA BUS depends on
the negation of the. 11atc that coupled :he preceding byte 111 the bus. This insures that only one source is
driving the XMIT DA TA BUS <ll any t~t!e time.

J. .. )(j

(FIG 2-30)(FIG. 2·21)

TACK

AX STATE A.

INT MLOOP

AX STATE B

TABORT

\FIG.

225)

!FIG. 2-12)

{F1G. 2-18)

AX STATE C
ACK
XMIT
STATE
PAL
IAH)
(Al

TINIT

MX STATE M

AX STATED

AXSTATEE

SYNC,'TR GONE

AX STATE F

MAX CRC 3

AX STATE G

XMITCLK

{FIG

CLK

--0

AX STATE H

El\JA ACK TYPE

ENA ACK TDST

~ iFIG. 2-12)

ENA ACK COST

~~
~,
-

(;::\

AXSTATEF

~r-----------------------NOTE:
LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPO~;DING
LOGIC.

Figure 2-31

ACK Transmit State Logic

ENA ACK SRC
io

LT;<;, 2·26)

n-..st.:>19

(TL\PfFR 3
P.H l\ET BUHTR '.\tODULF

NOlE
'rtu.· fumtiooal blud: diMgr:tnt~ in ( h11.p1n J ll"it' logi"
,•a\ AND and OR nmbol;;. II ~ "''' oo.·es,11rih
follo1<1 th>tl a «orr~mlini; gatt• ni.s1;. 011 tht· pad<f:t
buffer Jo2k prints. The il~St>rtion of input~ '\ and 8
Ult!iin11: the asS<'rtion of outpul C lllll) bl· repr~nt.t"d
on a block diagram b~ a .single AND g111e, ~el !ht•
enginttring dr1111ing may ;;h-0111 thi111 >t•Htral. drtuil
stages U(' inmht"d in the A'ff>inj! operation

The functional l>lock diaj!ram!> in rhis du11mr an·
ke~·t>d 10 th<' packet buffer moduk tPB) rngirn.'t •• 02
dn:uit sdlt'INHks KS prints) b~ letter designati llS
in parent~. The lt'tteo "Jlf'('if, tlw PB CS .,ht>el

that cootaift!i I.he cktailt"d loi!k a;,..ociart"d ,.;,h th;full(tional blod:s in tlw diagram.

The ~igMI name.. ~ in the foll( 1iom1I block dia·
grams are the namer. used on the eni:ineering CS
prints. Wht>re other \ij!nal narnt'\ or noh~ are used,
the' .are ('llC.losed in parenth~.

IUTA FLOW; GENERAL DISCt'SSION
>,, ~ i_, :1 bkx.:k di~~gcm1 of d:1L:t !')(\i,
the p:-ickc·-~ b-u:·::c:i:« lnt«Jn~L'.llDn in thL'
~-;,;'
~md d~:il.l. !l.JWS t'hr.:mgh the: P-~1(~'k't bU:ff('·!"
;'PB) ;n pa~~~et;;.
\':tric 1 u~ silL:. n~~:;l g:i.1ing w the CJ
tlzr-....·~ Lom the d:::\l.~t path rnrkiwk (DP'~ tc t.he dnk "'·hilc <la~,;~. "C:<,('.)vc·d from the Cl bu:-: Hr_;w~ fr,;1~) the link
J.J

Fi.~,ur,

l.c Ih~ DP.

A u~~nsmit buffer tTBUFi 1_:.;. in the d;11J f\:tfi 1hc Cl bu$ ;~-re:: r·i.:,·<._.'.se b1Jfc:- !RBl. Fl~~ :he: dnL: p,J.tb
fr:. ~n) -~ht.: (.:f bus. ·rhc huffcrs ar('. k1~1d.:.C ~~rj rcaJ t:.ndc: (\_·1:-,:;n;
:l(e port 1n,;(roc,)tk:. S·r~
11rc
u~.:d ir: ~rnns.ferring dJtj .in and ou~ ~i rhc !::n.iJfc;-s, F1)U'.' <:re u~.::(i
'.ki-rnwJ tr:rn..;;kr
C'.~L:
,,'_:c- ;..,st..'d frir mairH.¢n;1n\:e and ~il~di:-tf~~~t~ <:Ci;~;n;~Hh.i~ rhi.: s.i:i: '''1per:i 1.ions arc 11~1cd lie), _ ,-·'-·
TBU LO"\D
TRA!'\S\fJT

TBtT RE'\D
\Al.ID RCVR D.\T:\

RBUr MLOAD
RBLT RE.\D

TBUF DATA

TBUF
IN
REG1SfEFl

·~7:0>

TBUF

TBUf

OUT

X'M'T'

1---·--'-'--·:..;.::..;.,., no

!S!":·t

REGISTUl

L.OOf>
BACK
REGISTER

no DATA PATH/

PORT DATA <.7:0>

(R8UF OAT A"
RBUF DATA <h:J>

=-i
-----1
I

RBUF
OUT

\V>.
RSUF

RBUF
!N
REGISTER

I '~·___N_O...;D_E.,;.A,,;,:D;..;D:.:R:..:.E:.::.S:.::S:..;<::,::7...:0:;c::_ __
.___ _ __: Xc: Ml-'!T.!. . 2S. !.T~AJ.T.':!U~S_: •.,:17·: 10J.: .
} ff ROM LINK!
RBUF

I RECEIVER ST1HUSJ

RECEIVER
STATUS

FUNCTION

DECODER
TBUF

SEOUENClNG
LOGIC

Packet Buffer f}ata Flow

o-ir:.....+--s-F-ILECTIONI
/

SEQUENCING "
LOG•C

LOGIC

' COMMOI\ i 'C

'COMMANDS:
& BUFFER I

!TO LINK)

Figure 3-1

RBUf IMt,X
DATA <'.7:0"

BUffER
SELECT

3.1.1 TBlff LOAD
Data from the DP is kmded into the TBlJF via the TBlf in rcgiskr. The TBLT LOAD •lperation is con·
trolled from the PB.
3.1.2 TRANSMIT
Data is read out of the TBl.iF into th<.' link via the TBlF (>Ut r.:gbtcr. The TRA !'\S\llT <.\f1\:rnt1on is con·
trolled by the link.
3.1.3 TBl.1F READ
Data is read out of the TBUF back into the DP via the loorback register. fhe k\\1pback dc1ta 1> muxcd with
the received data on the RBUF DATA (7:0) data lines and returned to the port hus vi,11he PB read mux
This operation is controlled by the PB and is used for mainten,inc-c .md self-directed (Ornnrnnds.
U.4 VAIJD RCVR DATA
Received data (RCVR DATA (7:0)) from the link is loaded into the RBUF \ia the RBUF in mux and the
RBUF in register. The VALID RCVR DATA operation is controlkd from the link.
3. t.5 RBlJF MLOAD (Maintenance Load)
Data from the DP (PORT DATA (7:0)) is loaded into the RBl•F via the RBl!f' in mux and the RBUF in
register. Th..: RBUF MLOAD operntion is contrnllcd by the PB and is tbcd for maintenance purpnscs.

:U.6 RBlJf' READ
Dat;t is read out of the RBUF tu the DP via the RBLF out register and the t'B read mux. The dat;t from
the RBUF out rcgi>tcr i,; mu:-.cd with the loopback data .:in the RBUF D.·\ TA (7:0} data lines. The RB! IF
R FAD operation is controlled by the PB.
3.1. 7 PB Read Mux
Oth<:r data is provided to the DP over the PORT DAT:\ (7:0) bus via the PB read ;',w' This data is
NODF ADDRESS (7:0) and XMIT STA n;s (7:0) from the lmk. ,rnd rccci1c 'tatm ir:im the rccci1c
·Hatus logic in the PB.
3.1.8 Conlrol Logic
The PB operations arc controlled by dcrnding and sequencing lugic. A function de•t)dcr issue.,; commands
that :;pccify the operation to be cxecut"d ~t;fccr select logic selects the buffer for the 11pcra11on spccifit~d
by the function decoder. If" TE 1 I ; . .;elected {there arc rnol. the TBl.'F 'e4ucncing logic gcncrn\cs the
C1ln -.;i signals for 11 ~operation, Corresponding sc4ucncing logic cxisb f(•r the R BUfs "'hi.:h generate th<'
control >ignals for an RBUF operation.

The• function decoder and buffer select logic arc conirollcd by the p<lrt micn.•co1.k.
3.2 TBl F DATA Fl.OW OPERATIONS
The TBUF (f·igurc 3-2) i' divided int•l two pans (TBUF A and TBUf '~)with each TBLF h;iving a scpa·
r;1tc. P•!ralld data path. fhus,
is incrc:ised in that TBUF A c.in be loaded fr,Jm the DP while
TBUI B is being transmitted t,.
Each TBL F ha> I K of storage. The foliowing d1>cussion ll'ill
describe TBlT :\and its dat,l Pc.t 1>. TBl'F Band i1s data path arc idcntic;rl to TBL'F :\

PORT DATA <.7:0>
-+WG.221)
PORT DATA <7, 6, 1>
- - - - - - - - - • ' . F I G . 3 5i

TBUF · OVFL

--1

iT:UFA "
(FIG. 3-7.i \OUT ENA}

PORT CLK

(FIG 351 _

111

l XMIT CLK
I

(E)

I
I

LASTTBUF

LAST
, . . - - - - - . XMIT
BYTE
LAST
BYTE IN
REGISTER.

POAT CLK

BUS
TBUF PAR

IBUS

(F)

LOAD LAST
DATA BYTE

---

PORT CLK

XMITDATA<7:0>

TBUF
XJAIT DATA
PARITY
PARITY
i
OUT
REGISTER
II

I
(FIG. 5· 11) _P_B_PA_R+------<1~

II . - - - - · - · - · - }

XMIT CLK

(A}

LAST
BYTE OUT
REGISTER
(El

----~
PARITY
CHECKER
(H)

(FIG.2·12)

. .

(FIG. 5 2: 5-11!

'------'
I XMIT CLK

XMIT

~~{FIG.225\

, FiG. 226)

II
I

TBUF PAR 8

,___ _ _....... TBUFB
IN
PORTCLK
REGISTER

( TBUF B '1
\OUT ENA/
· (FIG. 3-7)

(C)

TBUF B
ADDA <9:0>

TBUF B
I Fi G. 3 7i ---'-A,_.E""G'-'E"'-111"-A'--+---'
PORT DATA <7:0>

FIG

1. 3 7

~~~~ I

XMIT CU<

CLK
-"T.:B.:U.:..F..:B;..:cA.,,,D::.:D::.:A.;...iTBUF
B
TBUF B OVFL _ _ _ _ _ _ _ _ _ _ _ _ _ _ __J
CLR
ADDRESS
t----!!--t-t--f---'..:::...:..:....::-:::..:.:_:;__

TBUF B AOOR

l II

~E~UNTER

r--_,_L_o_o_P_BA_C_K_R_EG_A_E_N_A_l_

_._UL. -,
I i !

{FIG 5 2 ) - - - - !

LOOPBACK
I
REGISTER.,.__ ___,
1------lA

BUS RBUF DATA <J:O>

'
'

TBUF A READ ENA

RBUF PAR

(KIE)

i
I

I ~F
~

B READ ENA

i.o-----J

I
l

.___ _ _ __

CLK TBUF A ADDA

LOOP BACK
~
REGISTER i . o - - - 1-----<B
IKIEJ t---------'C:.::L:.:..K:_T::.;:B::.;:U:.:'f_.:B:._:..:A.:::D.:::D.:.:R_
(LOOP BACK REG BENA'

·--------====----T-B_U_f_P:..:A=R=IT=Y....::.:...:.:.;:...:.:..::..::..::..:::.:.::..~-L--tl--ilr.----------- ___________.:P:.:..O:..:R:..:.T:.:...D:::A:.:T:..:A..:_:<c:.,7:.::;::0:~} !F iG. 3.31
I

{FIG. 331

Figure 3-2

TBCF Oper3tions

NOTES:
1. COMMON I /0.
2
LETTER DESIGNATIONS IN PARENTHESES REFERS TO
ENGINEERING DRAWINGS CON7'AINING CORRF.SPONDiNG
LOGIC.

3.2.1 TBl.iF UM.D
SEL TBUI- A enables TBlff A, ,electing i1 f1lr ;1 TBUF A <Jpcration. \\ R TBLF ,\ <:11,1blc:; the Tl:llT. l\
input and disables the output thcreb' >citing up TBUf A for a write. (TBlT A has a common 1/0.) A
data byte (PORT DATA (7 0)) is dcx:ked inw the TBUF A in rcgi;tcr by PORT CLK. PORT CLK al-.o
clocks a parity bit (PB PAR) from the DP rnto the TBUF parity in rcgi,;tcr. TBL'F A REG EN.\ then
a~scns to enabk the data byte (TBUF A DA TA (7:0)) and the· parity bit (TBt:I' PAR :\)to he 11 ritt.:n in10
TBt:F A.
The TBUF .'\ addres> (TBUF A ADDR (9:0}) is obtained from the TBlJF A addre>s counter. The· niuntcr
is cleared by CLR TBUF A ADDR prior tel.loading a data packet into TBUF A. \>each byte is written.
the counter is incremented by CLK TBUf A ADDR to the next locatic111 in thc buffer.

When the last byte of the data packet is on the port data bus, a LOAD LAST Dl\TA HYlE !lag is:1:.;scrt··
ed and clocked into a "last byte in" register by PORT CLOCK, The !lag is written mt() TBUF ,\ along
with the last data byte and its parity bit. The flag is u>ed to indi('ate the end of the di1ta p;ickct tc) the link
during a TRANSMIT operation.
U.2 TRANSMIT
SEL TBllF A enables TBUF A, selecting it for a TBUF A operation. WR TBCF A i, false to inhibi1 the
TBUF A input and enable the output for a read. The TBUF A address l.'.ounter is dcarcd by CLR TBt F A
i\DDR t') address location 0 in TBUF 1\.

The first data bvte is read out of TBUF A from address 0. The byte (TBUF A DA TA 17:01) i> dockd into
the TBUF A o~tput register by XMIT CLK from the link. "TBUF A OUT ENA .. i<; true and gat~s the
da!a byte out of the register as XMIT DATA {7:0). The parity bit from TBUF A <TBUF PAR A I is g:11cd
to the TBl!F parity out register where it is clocked in by XMIT CUC The data byte is clock.:d inhJ the
THUF A out register at the same time the parity bit ts clocked into the TBL F parity out register.
The data byte is now availblc to the link as XMIT DA TA {7:0) and hi n parity checker. The parity bit

(XMIT DATA PARITY) from the TBUF parity out register j,; also applied w the parity chcd;cr, tr a
parity error i;. detected, XBUF PE is a~scrtcd to the DP where it sets an error bit in the porl maintenance
control ;md status register (PMCSR).
X\11T DATA Pl\RITY is also applied to the link as the parity bit for the .XMIT D-'\TA ( 1 :0) data b.vtc.
CLK TBL:f A ADDR increments the TBL!f A address counter to the next loca1iun in the liufftr. The
address counter is a I K counter capable of addressing the ! K location~ or TBU' A. In pmctKc, a packet
-.•ill be less than 1K bytes of data; thus, the address counter should nel'er rt:ach i\ fuil C<lUnt If the coun1cr i.s
not cleared prior to a TRANSMIT operation, a full count may be rc:u:hed. In ihi' c1cnt. TBUF A 0\ FL
comes true and asserts XMIT BUFFER EMPTY to the iink.
\\'hen the las1 data bvte is read from TBUF A. the BUS LAST TBUF bit i> alsP read uut :rnd docked into
the "iasr byte out" register by X\:.r CLK. This in turn asserts XMIT BUFFFR E\ll'TY t<1 tht' .link as an
indication that it has rece.ivcd the entire data packet

3.2.3 TBlJF READ (Loopback)
SEL TBUF A enables TBUF A, selecting it for a TBUF A operation. WR TBUF A is false 10 inhibit the
TBUF A input and enable the TBUF A output for a read. The TBUF A addres.~ counter is cleared by CLR
TBUF A ADDR to address location 0 in TBUF A.
The first data byte at address 0 (TBUF A DATA (7:0}) and its parity bit (TBUF PAR A) is clock<'d into
loopback register A by CLK TBUF A ADDR. Signals "LOOPBACK REG A ENA" and TBUF A READ
ENA arc true and respectively couple the data byte (RBUF DATA (7:0)) to the PB read mux and the
p:irity bit (RBUF PAR) to the DP.
CLK TBUF A ADDR increments the TBUF A address counter to the next location in the buffer.
3.3 RBlJF DATA FLOW OPERATIONS
The RBUF (figure 3-3) is divided into two parts (RBUF A and RBUF Bl with each RBUF having a separate. parallel data path. RBUF A can be loaded from the link whiie RBUF Bis be.ing read by the DP, thus
allowing greater throughput. Each RBUF has I K of storage. The following discussion will describe RBUF
A and its data path. RBUF B and its data path is identical to RBUF A.
3.3.1 VALID RCVR DATA
A VALID RCVR DATA operation is an RBUF load of received data from the link. The operation is
initiated and controlled from the link.
SEL RBUF A enables RBUF A, selecting it for an RBUF A operation. WR RBUF A enables the RBUF A
input and disables the output, setting up RBUF A for a write. (RBUF A has a common 1/0.)
The data byte and parity bit from the link are input to the PB through an RBUF in mux. The mux uses two
select signals; one for the data byte and one for t'1e parity bit. When mux select signal RBUF INPUT
MUX SEL is false, the data byte from the link (RCVR DATA {i:O}) is applied to the RBUF A in register
as RBUF IMUX DATA (7:0). The byte is clocked into the register by RBUF REG CLK and then gated to
RBUF A by the true state of RBUF A REG ENA.

RBUF REG CLK also clocks the parity bit (RCVR DATA PARITY) into the RCVR parity in register.
When mux select signal RBUF MLOAD is false. the parity bit from the register is applied to RBUF A as R
PARITY.
The RBUF A addr~-ss (RBUF A ADDR (9:0)) is obtained from the RBUF A address counter. The counter
is cleared by "CLR RBUF A ADDR" prior to loading in a data packet. As each byte is written, the counter is incremented by CLK RBUF A ADDR to the next location in the buffer. The address counter is a I K
counter capable of addressing the I K locations of RBUF A. In practice, a packet will be less than I K bytes
of data: thus. the address counter should never reach a full count. If the counter is not cleared prior to a
VALID RCVR DAT A operation. a full count may be reached. In this event. RBUF A OVFL asserts and
terminates the VALID RCVR DATA operation.
The link uses a RCVR byte counter to indicate when the data p:i.cket has been loaded into RBUF A. Th~
first two bytes of a data packet specify how many data bytes are in the packet (packet length). PACKET
LENGTH from the link asserts and loads the first two packet length bytes into the RCVR byte counter.
The counter is a down counter which is decremented by RCVR CLK each time a byte is loaded into RBUF
A. RCVR PACKET END asserts when the packet is completely loaded.
3.3.2 RBlJF MLOAD (Maintenance Load)
Sci RBUF A enables RBUF A. selecting it for an RBUF A operation. WR RBUF A enables the RBUF A
input and disables the output, setting up RBUF A for a write.

3-6

(FIG. 3·21

~1111~

~-P_O_R_T_D_A_T_A_<_.7_:_0~_'·~-

RBUF A
ADDA <9:0>

EN RB A

(RBUF A
DATA<7:0>)
..--~--.{RBUFA
_ _ _ _ _ _ _ ___, RSUF A
DATA <7:0>)
RBUF A
OUT
RBUF A PAR
(NOTE l)
REGISTER
CLK RBUF A ADDA
(F)
(F/E)

"'G ' '" • "'"' '" J I

SEL RBUF A
WR RBUFA

1 BUS

RBUF
DATA<7:0>
NOOE
ADDRESS <7:0> (FIG. 2_31 i
PB
1
READ XMIT
1
STATUS C'.7:0>
MUX
{FIG. 2·2711
(Kl
{RCVR STATUS
I
.-·-~l_:O_::O_'l_ _ _ IFIG. 3-9) i

PB MUX
ENA

--.._...,r-,"'°""

PARITY iFIG. 2-31
RCVR
PARITY IN
RBUF
REGISTER
REG CLK

3-8)~

(F)

WR RBUF B u
READ RBUF 8

SEL RBUF B J

RBUF 8 PAR
RSUF B
_ ___, RBUF B
OUT
(RBUF B DATA <7:0~REGISTER 14----------; !NOTE l)
(X/E)
CLK RBUF BA.DOR
(X)

(RBUF B
DATA <7:0>)

RBUf B
ADDA <9:0>

(FIG. 3-8) {
READ BUFI
PB MUX
SEL <1:0>

_J ~~~~~SS
RBUF B OVFL

NOTES:

1. COMMON 1/0.
2. LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
LOGIC.

RBUF Operations

RBUF
REG CLK
PACKET LENGTH }(FIG. 2_301

I RBUF B REG ENA
CLK RBUF B ADDA} !FIG. 3·Bl

COUNTEA14------(~C_L_R_R_B_U_F_BADDR)

IJI

Figure 3-3

~---)
(FIG.

RCVR
DATA

..----.RCVR
PACKET END
RCVR
BYTE
COUNTER
RCVR CLK
(L)

The duta pa.:ht i.s obtained from the DP via the port data bus and input to the PB through the RBUF in
mux. When mux select >ignal RBUF INPUT Ml:X SEL is true. data bytes from the port bus (PORT
DATA (7:0)) arc applied to the RBUF A in register as R BUF 1'-1UX DATA (7:0). The· bytes are clocked
into the register by RBUf REG CLK and then gated to RBUF i\ by the true state ,,f RBUF A REG
ENA.
The parity bit from the port bus (PB PAR) is docked into the TBl,F parity in register tFigurc 3-2) and
then applied to the RBUF in mux as TBUF PARITY. With mux select signal RBl.:F Ml.OAD true, TBUF
PARITY i,; coupled to RBUF A as R PARITY.
The RBUF A address (RBUF A ADDR (9:0)) is obtained from the RBl 1F i\ address counter. The counter
is cleared by "CLR RBUF A ADDR" before loading in a data P<lCkct. As each byt<.: is written, the counter
is incremented by CLK RBUF A ADDR to the next location in the buffer.
3.3.3 RBt:r R~ad
SEL. RBUF A enables RBUF A. selecting it for ari RBUF A opcra1ion. WR RBl.iF A is false to inhibit the
RBUF A input and enable the output for a read. The RBUF A address counter is cleared by "CLR RBLIF
A ADDR" to address location 0 in RBUF A
A data byte ("RBUF A DATA (7:0}'') and parity bit (RBUF A PAR) read out of RBUF A arc clocked
into the RBUF A out register by CLK RBUF A ADDR. EN RB A is true, gating out the data byte and
parity bit as RBUF DATA (7:0} and RBUF PAR. respectively. (READ RBUF Bin the RBUF B data path
corresponds to EN RB A.) RBUF PAR is applied to the DP while RBUF DATA (7:0) is placed on the port

data bus via the PB read mux.
When reading RBUF A out to the DP, EN RB A a··q:ns and rnuples the data in th.; RBUF A out register
tc> the BUS RBUF DAT!\ (7:0) bus before CLK RBLF A ADDR asserts. The data 111 the RBUF A out
register is undetermined until CLK RBUF A ADDR asserts and clocks the first data byte from RBlJF A
into the register. Thus, when reading RBUF A. the DP discards the first byte as invalid data.
The reading of a data packet from RBUF A doc>' not hal'c to be done in consecutive cycles. The fMckct can
be partially read and the remainder of the packet read al a later time. If a read operation i;, interrupted, the
first data byte read when the read operation is continued. is valid data.
3.J.4 PB Read Mux
The PB read mux muxes four signal groups of eight bits each onto the port d<1ta bu' as PORT DATA <7:0}.
\\'hen READ BUF is asserted. the RBUF DATA {7:0) lines arc selected. i<.t:AD NODE ADR. READ
XMIT STATUS. and READ RCVR STATUS rcsp.:ctivcly select '\iODE ADDRESS \7:0/. X\tlT
STATUS (7:0), and "RCVR status". NODE ADDRESS (7:fJ) and XMIT STA fUS (7:0) come directly
frnm the link ;ind do not pertain to the PB. "RCVR status'' is .::omprised of eight status signals rdating to
rc.::civ~d data from the link (Paragraph 3.lS).
The PB read mux is cnablcd by PB MUX ENA \\hencvc-r any of the four select signals is ;hs~rtcd.
3.4 CLOCKS
Three docks arc used within the PB and these arc obtained from the DP and the link (Figure 3-.+). The
three clock- u;,cd arc:
I.

1.
_,
"'

PORTCLK*
XMIT CLK
RC:VR CLK

POR"f ('l.K T~ :Ii:-.•) .:tppc;H"i. l)n tiK PH logi.c pripts but i:-. 1d.:ntic,d rn PORT CLf\. The n,.1._~ ,;/f'.n~1h. r.rn out frllm J~ffcr.::n
dri1.tD·. hi.:nc.: the d1fkrL'nl mni:n11.mi ••:..~.

3-H

(FIG. 4 _12 ) PORT OLK

TBUF
LOAD
OPERATION

TRANSMIT

XMIT CLK

OPERATION-.~=-..;;.;o.'-'---(FIG. 2-14)

TBUF
,___ _ ___,.., READ
OPERATION
PORT CLK

r---1

RBUF
READ
OPERATION

RBUF
MLOAD
c 0 ERATION

RBUF
REG CLK

VALID
RCVR DATA
OPERATION
NOT!=:
LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
LOGIC.

figure 3-4

Packet Buffer Clocks

RBUF CLK MUX

RBUF MLOAD (FIG. 3 8)

I ~-----~'-RC_V_R_C_L_K

_ _ (F IG 2 10)

PORT CLK i' obtained frolll the DP an•:: synchrnnin" all \ipcr;;ti,rns that involl'c data flow to "r fr•.Hll the
DP. PORT Cl .K has ,; 200 n' period.
XMIT CLK is obtained from the link and s\nchrnni1l·, the TRANSMIT opcratinn in whi..:11 data Hows
from th.: PB to the link. XMIT CLK has a 114 ns pcrivd.
RCVR CU; is obtained from t'ie link and synchroni7c> the VALID RCVR DATA C'J'lCrntion in '~hid1 data
floll's frum th.: link to the PB. RCVR CLK !ms a 114 ns period.

Figure J-4 illustrates the six PB operati1,ns and the docks that :;ynchroni1.c them. Note that the two <lpcrations that k'ad the RBUF, (RBUF MLOAD and VALID RCVR D,.\TAl arc svnchroni1cd bv RBlif·
REG CLK. RBLIF REG CLK is PORT CLK when the RBUF is being loaded from the DJi (RBLT
MLOAD opcra1'on). and is RCVR CLK when the RBUF is being loaded from the link !VALID RCVR
DA TA operationr
The TBUF and RBl;F address counters arc docked by whichever dock is synchroni1ing the partic·ular
operation.

3.S FlJN(TI01'i DECODER AND BlJFFER SELE<,. LOGIC
The SELECT bit from the microword asserts for one rnicrocvcle and enables the function (krndcr and the
buffer select logic (sec Figure 3-5). Four link control bits from the microword (I.INK CONTROL 0:0})
carry the PB function command to the function decoder which outputs one of thirteen possibic commands
for one microcyde. The function commands and their as"1Ciatcd link control codes arc sh011,n in Table 3-1
The f,lllowinµ par;;graphs de,cribc each of the function command,.

3.S. I SH LOAD BtTI··
Prior 10 issuing a load buffer command (LOAD HUF or LOAD LAST 0.\ T.<\ BYTE.I. or a RESET THl~F
command. the microcode selects the buffer with th<;' SEL LOAD BUF command. The sckcti<lll is rnadc bv
the buffer select logic during the microcydc, in which the micrnword SELECT bit is mu:. The .-;ekctc!i
output is latched and remain, true until SELECT asserts again and
,, her buffer i~ st·ic<.ted
SEL LOAD BU F enable> the "load" ;,cction of the buffer select
luad enable" signals according to port data bit; PORT DAT,\

,; h1ch ,1utpub unc ,,r four '"buffer
: Table :i.2)

3.S.2 SEL READ BUF
Before issuing a rr"d buffer comniand (READ BUF) or ,1 RELEASE RBL'F cmnm;111d, the miu1.x'<J<k
sclc<.:t!. the buffer with !he SFL READ BUF command. The selection is made by the huffor sdcct lugic
during lhc mirnx:ydc in whid1 the microword SFl.ECT bit i-; true. The selected vulput i1> latched and
rcmaim; true until SELECT <h->~rts again and another buffer i.s sdcctcd.
SEL READ BUF enables the "read" section of the buffer sckct logic which llUtputs one nf i'uur "'btil"fcr
read enable" signals a,cwding to pon data bits PORT DAT.-\ \7:'1) (Table 3-.n

3.S.3 LOAD Bl;F
Tht LOAD BUF cumrnand loath pon data into the buffer sdcctcd by tl1.: SFL L(>t\D BCI- ,::umm:mcL
The htd npcr;1tions arc TBUF 10,\D and RBUF \1LOAD. The \'ALID RCVR DA"L\ <Jpcration 1io:1ding of the RBUF from the linkl i' not a function of the PH rnicrowc.>rd.
A d:lla rackt't d1ics not ha\'c w be loaded in consecutive cydcs. A pa(k~t can be partial!: io.idc:d and 1h~
remainder of the r,1ckct kMdcd al ;l later time.
When lmding a ·y BLF. the !:tst by1,: or da1a mu!>t be loaded with,, LO-\D LAST J),\fi\ BYTE urmnund

(FIG. 3-2}

TBUF A LOAD ENA

PORT DA~A <7:6>

{

TBUF B LOAD ENA

BUFFER
SELECT
LOGIC

PORT DATA 1

:}FIG 37)

RBUF A MLOAD ENA
RBUF B MLOAD ENA

~}(FIG. 3·8; 3-9)

TBUF A READ ENA

SELECT

(FIG. 3·71

TBUF B Rl::AO E:NA
PORTCLK_.

RBUF A READ ENA

lf<ITIALIZE

~}FIG. 3-8; 3·9)

RBUF B READ ENA

:}FIG. 36)

SELECT

ENABLE

SEL LOAD BUF

~(FIG.3-8)

SEL READ BUF

{FIG. 3-2)

LOAD BUF

LINK CONTROL <3:0>

LOAD LAST DATA BYTE

FUNCTION
DECODER

Y-

TRANSMIT

{FIG. 3-6; 3-7)

}FIG. 3·6; 3·7)

TBUF B XMIT ENA_..

D
TBUF
XMIT
SELECT

}

TBUF 8
SEQUENCING
LOGIC

~BUF A XMlT ENA {FIG. 3-71
~

FF
PORT CLK
RESETTBUF
{FIG. 3·3; 3-7; 3-8)

READ BUF

RELEASE RBUF
READ NODE ADA
READ XMIT STATUS
READ RCVR STATUS

CLK
(FIG. 37)
(FIG. 3-8; 3·9)

}FIG. 3·31

(LINK ENABLE)
(LINK DISABLE}

Figure 3-5

Function Decoder and Buffer Select Logic

3-11

_.}FIG. 3-6)

NOTES:
1. THE LOGIC IN THIS FIGURE IS CO NT Al NED
ON SHEET A OF THE ENGINEER! NG DRAWINGS.

Ta.bk 3-1

Link Control Codes Vs PB Function Commands

UNI\ CONTROt
3 2 l
0

Function Command

READ '-iODE ADR

()

LOAD LAST D:\ TA B'lTE
0
TRANSMIT

()

"Enable link"
"Disable link"

0
()

()

READ RCVR STA TL'S

()

READ XMIT STATUS
()

READ HUF
I OAD BUT

0
()

RELEASE RBUF
RESFTTBUF

()

SELREAD BUF

SEL LOADBUF

Tahlt> 3-2

PORT DATA

()

Load Buffer Select Code
Buffer Selecled

TBUF A LOAD ENA
TBUF B LOAD ENA

()

RBLIF A M!.OAD !:NA
RBLF B \1LOAD ENA

PORT DH.\
6
i}

tUllT ,\ RE.\fl I:'\;\

RBUf B RE \DEV\

TBt.'.F .'\ RL\ ,·i F "- .\

IRlF A READE"\

~l5A

LOU> LAST IHT.\ BYTE

The 10\D L.\ST D1\T\ HYTF ~·1r11nwll~ ,, •he
•!W
;h;:
,., ,,.
of the THUFs !t r:x·rfdrl.H:-< thi.~ !>-~d1~f..· fr;.ndfiH~ ,b :l LC> . ·\D Bt F fi; n::nLi.tW :_l;·,n
l;yte" bi1 int•• tb(: TRl..T :tldfiJ.! ,,il.h tlK' dnL' b) :.:
1

l5.I\ RL\D BU
lhc RL\D BLF c:1:nnand ~c:1d-> d;1L·r frnn; t\1(: ·t!u 1 :c:: :;c:,·.-t.,il h :•k ~11 HI \!) IH ! cr•m:n:•;1d The
..b.~:1 ~' read o'~i, L> ~.h(• rx· r', d.au bu.:-1 Y1.'.~ the PB ::-c~:d :r>.,.\. T'hl' ·---~'.,JJ
THUF Rf.\U
RRLI RE\D The TRA;-...S\lfl >•p..:r.u1on (rcadinf' ,/
lfllT le the
1

Wdrd but 1.~

~~p:tr:1k~ n)n1rn~ird

th~ link tJintnAs ~bi;,: .'.\'.:1d ...:•p..:rJtk~n.
b) k" !li~ :;. rcrid dul.

'J h'· :.i'l'k ,,,:or::J.; 1:~1-:- r,.:JC1-'":.ll:

Durini:. \ 11c micr.:..;y(h: that TR.'\ "-S\11T 1s Im~ .nc
<kkrril,rt<: 11 h;d: l'BU will be 1nn,rniHcd i\ TH\. f \\t!T

r<·r1 dat;.; b~t i,; '.·,d.'<: ... ~d TBt.+ R '\\HT[\.\

. . -.::-, . .>:•.·:

l!H. I

ht;' ['CIR r D:\T.\
i;, :,.,"iJ"cc'C
,~.-·'THI f .\\:,\!JI[\;,\ i!

On\\ •-'!le 1 R\\SM.IT dX:r::ti:i,n c::rn he ;.\c:::li~<: «''
:ink.) A TBUF mu>: N' ;;.impk1d' rc,1d.
anmhci TR:\~S\tf'f .::.1.··mm~rid c..tn be i.:-1~L~;..'lL

.15.7 RESH rRu
Th: RESET TBl..I ,.,, ·:,n::rnd r~sd; <hi: addr'"'

3.5,8 Rf.LEASE RBl <F
fht:: RFLFi\SE RBUF r.:ui:1nur1J reset.:-; ~h~. addrc~s ;.:< 1 u:~:t.:'. :·:~ ... ,-..... ;:.:_:~'-~
ck;trS the '•fu:l ..' !l:i: (:1.\.Y:HC>- RBtf FLU .. rig•m· .3·'i\ r· t'.l<O ,,,:k~r,·d
\in~ fur :1 VALID RCVR D,\T,\ •.•!X'ra1i1•n
3.5.\1 READ NODE \DR
Tfi(; READ N<)DL ·\.DH
.~.!UO

!n~:Jn~l s~';'"._:·~~s ·1~-~c nc~J::· ;--~~.;dr ~'.~,·

RF\U '\\HT ~l.\TtS

\t_f; rt: \ t');)~>LS.~'.-

\\\'.

-~...

3.5.11

REA n R('VR sr \H. s

The RL\D RC\ R SL\ TLS cDn.nwrhi sckc:., rh'
dat~i bus by the PB rt;:i'.~.d mu\. Th~: ''p.::·cd.vc .~u:~:~

···r~-(\:i\-: ~:;1h>·" bib Li he nHi.\..:-·d

·;:c: disci.1~sl:·d

the f\l.lf t

P:·':a~:J:_i1·:h .1)\

.t5. I 2 I.ink [nable and Linlo. Disable
The "link en~Lbk·"· and "link di>~abtt:"·• l:'.\Jn1m,1n<l~ ~·:'"<~ 1t..;ed ~n the link nirl<jl.~-;~'. '.J':d r"<:d'c~nn ~10 fur,ctidn .)n
ttlc PB other th.!n 1n a,;;;crt PB LOAD. PB LO:\D mm.: be' !Im: lo crablc :lw r.nh to :lie iink ()r the
rnnrnrnnds. r,Scc PB LO\D: Paragr:lph .lA)

J.6 PB LOAD
();Jta placed ''n the port data bus from the DP i> obt,1incd fr,irn ;1 L)·bit PB OLT rq:,\,tcr. Tht: rq,:isH.:1
output is cn;1bkd by PB LOAD froil\ !he PB. PB LO.·\D ;, ;isscrtcd for ;,li ,,,m•:Hrnds :ha: ''''l\;irc da1a to
be transferred fron: the PB OUT rcgis1er to th~ i"m d:.t;: bus \&;c Fi~nrc .;-6 •

:\n eight-bit en,1bk ;md ar eight-bit Jisablc comm,md fun(tion for thr iink i> tr:11,kncd i.:: !lie i:nk from
the DP via the pllrl data bus 1Figur.: 3-1 ·l. Although these c.··mmand' de· nut p.::n.,,11 \(1 the PB !: r,:1p1irtctl
that PB LOAD be true in order to trnnsf~r the .:ommands frnrn i.he PB OLT rc:girn:r to :h.: po1: d:Hil btiS.
Referring to Figun: 3-6:

SH. LOAD Bl!F .md SEL READ HLF <'1>m1tund,; require por: t.i:<la bite; PORT DATA .(7:6,1 t•l
sck.:t l'hi..:h buffer to bad or re.id.

LOAD BUF and LO·\D LAST DATA BYTE "''nrnMnd, "'!>tais :h" "''tc tc lx> J,;aJcd from the
port data bus.

The TRAl\SMIT command requires PORT DATA l tc
link .

.i:.

'"Link enable·· and "link disable'' comm;mds reyuirc '' path fr.:11n the PB Ol: f register on the·

DP lO the port data bus.

i SEL LOAD SUF
ll SEL READ BUF
LOAD BUF
(FIG. 35) {

LOAD LAST DATA BYTE

5-2.i

I TRANSMIT

!LINK ENABLE)
(LINK DISABLE)
NOTES:
i. THE LOGIC IN THIS FIGURE !S CONTAINED
ON SHEET A OF THE ENGINEERING DRAWl!ltGS

J-14

3.7 SEQl.'E1'ctr-.;G IJ)Glf
The PB functi;m decoder and buffer s.:lect l<>gi<. gc'ncratc' the ncccss;iry 'ign.tb tc.' <"!1,tbk the TBUF and
RBUF load/rcud operations. The signals pertinent to each of the six •Jpcr;1tic•ns ::re dis<'•i\o>c:d in Par.igraph,,
.l.7.1through3.7.6. The A buffer is used in :Iii the discussi,ms. (\Jrrc,pcinding higic C\ISI> r. 1r the B buffer.
Figure 3-7 illusm1:cs the sequencing 1,1gic ;tSS•JC',1tcd "ith the thrc.; TBUF clp\;r:11.ic)l1S. hgurc ·'·X illustr;ucs
the sequencing logii.: ass.x'i:itcd \\ith the three RBtf operations.
3.7.1 TBUF LOAD
The TBUF LO.-\D sequencing Jc;gic is illustrated in figure J-7 Before a Tflt:F LOAD .1pcr;1tion is initiated, :i RESET TBUF command is issued lo clear the ·":lectcd TBUF address counter. The RFSET Till+
command is Al\;Ded with TBl'F :\LOAD E'\A to assert (l,R TBUF A ADDR The next PORT CLK
pulse asserts CLK TBUF A .-\DDR which clears the counter. (The addrc,s counter i;; an as)nehn)nous
counter which requires a clock pulse while the clear input is true in 'lrder tt• reset.)

Tile TBUF LOAD operation is initiated by the LOAD BUF command. The LOAD Pt;F co1nmand (or
LOAD LAST DATA BYTE if this is the last bl'tcl is A '\Ded with TBUF 1\ LO:\D ENA tor TBUF B
LOAD ENA) to enable the pulse width flip-flop w be -.et by th,;; next PCRT CU< pulse The llip-llop
output is ANDcd with TBUF A LOAD ENA to assert WR TBL'F A and ScL TRcT A. SEL TBl-'F A
enables TBUF A and WR TBL'F A enables it for a load
The output of the pulse width 11ip-tlop is delayed 80 ns .•ind then used to cle,ir the l11p-1l,1p. Thus, SEL
TBUF A and WR TBL"F A become 80 ns pulses.
Another output of the puh,e width tlip-fiop is delayed ~O ns and ANDcd with TBliF <\LOAD F"A I•)
assert TRUF A REG ENA and CLK TBLF A ADDR. These two signals arc al;;o 80 ns wid~ and arc
delayed 20 ns with respect 10 SEL TBUF A and \\'R TBUF •\.
TBUF A REG ENA gates the output of the TBUF A in register t1J TBUF A Dcbiying TBCF A REG
ENA allows time for the tri-statc output ofTBL'F A to be dis;iblcd by WR TBl:F :\before the \\Titedata
is gated into TBUF A from the TBUF A in register.

The TBUF A addr(..'SS C<lU!ll\:r j, incremented on the trnilmg edge of Cl.K TBLF A ADDR. Delaying CLK
TBUF A ADDR assures that TBUF 1\ i' dis<iblcd (SEL TBUF A is ncgat~dl befi:1rc the address is incre·
mcntcd 10 the next lo.:ation .

.l7.2 TRA:\SMIT
The TRANSMIT sc:qucncing logk is illustrated in figure.'-/.·\ TRANS\llT opcr.nion requires both a
TRA'.\iSMIT command from the function dccnder and :he X\HT DATA E"A signal frnm the link
X\,flT DATA E!\iA is true \\hen the link is r-::tdy to recciYe mrnsmilled datt from 1h,~ PR
Before a ~RA NSMIT opcraLicin can be executed. the sclc.:ted TBUF addre>> wuntcr niust be cleared. [n a
TRANSMIT ()peration the counter is cleared by the as;;cr1ion •lf TRA~SMIT instead of by a RESET
TBLJF command. TR.-\NSMIT is ANDcd \\ith TBUr A X\llT ENA to assen CLR TBUF A ,\DDR.
The nc\I PORT CU.. pulse a;.scrts CU( TBliF A ADDR. Clocking the rnuntcr with the clear input
as;,crtcd rc;;cts it to zero.
XMIT Di\ TA E1'A is ANDcd with TB".'F A XMIT ENA to a,;sert "'TBUl- A OUT ENA" and SH.
TBUF A. SEL TBCF A cm1bb TBUF A. 'TBUF A OUT El\\" g,11cs the data oytc .mt of the TBUl A
register to the lin~.
CLK TBl.F A ADDR i~.:rcrncnts the• TBUF A addrc;.s cuuntc'f <.luring tk TRA'Sl\.!IT opc:·ati<,n. The
chx~ is asserted by the \"IDing •.If XMIT DATA E .... A. TBU \ EN:\. and XMIT CLK Thus, the Jin~
syn.:hMni··cs thl~ Jddrcs, Cclunce' with XMlT CLK

3-15

XMIT DATA ENA

TBUF A REG ENA

----

TBUF A LOAD ENA

IFIG. 3·5)

(F:G. 2. 141

XMIT CLK

(FIG. 2_26}

XMIT DATA ENA
TBLiF A XMIT ENA

~
~
I•.·

IF IG. 3 S} {-T_B_U_F_A_A_E_A_D_E_NA
_ _ _ _ _ __,
READ BUF

r RESET TBUF
TBUF A LOAD ENA
TRANSMIT

(FIG. 3. 21

POAT CLK

!FIG. 35)

L,J

CLK TBUF A ADDA

CLA TBUF A ADDR

-~--------!~"""'

TBUF A XMIT E:NA

NOTE:
THE LOGIC IN THIS FIGURE IS CONTAINED
ON SHEET D OF THE ENGINEERING DRAWINGS.

Figure 3-7 TBUF Sequencing Logic

.\-16

3.7.3 TBlJF READ (Loopback)

The TBUF READ Ooopback) sequencing logic is shown in Figure 3-7. The TBUF A address countct must
be reset to zero before the TBUF REi\D operation can be executed. The microcode resets the address
counter by selecting TBUF A with a SEL LOAD Bl.IF command (asserting TBUF A LOAD ENA from
the buffer select logic) and then asserting the RESET TBUF command. The AN Ding of RESET TBUF
and THUF A LOAD ENA asserts CLR TBUF A ADDR. The next PORT CU~ pulse asserts CLK TBUF
, \ ADDR thcrebv resetting the counter.
With the address counter reset to zero. READ BUF and TBUF A READ ENA arc ANDt;d to assert
"LOOPBACK REG A ENA" and SEL TBUF A. SEL TBUF A enables TBlJF A. "LOOPBACK REG A
ENA" gates the data from loopback register A onto the RBUF data lines.
The ANDing of READ BUF, TBUF A READ ENA. ;tnd PORT CLK asserts CLK TBUF A ADDR.
Thus. the address counter is synchronized by PORT CLK from the DP.
3.7.4 VALID RCVR DATA

The VALID RCVR DATA logic is illustrated in Figure .1-8. The RBUF address counter is cleared at the
end of all RBUF operations. Thus, the VALID RCVR DATA operation will start with the ;1ddress counter
already set to zero.
The VALID RCVR DATA operation is initiated and executed entirely under link contrnL Consequently,
the >election of the receive buffer (RBUF A or RBUF B) is not made by the buffer select logic but by the
''RBUF load selection" logic shown in Figure 3-8.
When both RBUFs are empty, RBUF A is selected to receive the datit p<ickct as described below. The
RBUF A LOAD ENA and the RBUF B LOAD ENA tlip-llops arc initially in the reset state. Signals
RBUF A FULL ENA and RBUF B FULL ENA are false (both RBUFs arc empty). When VALID RCVR
DATA asserts. the VRD and the RBUF A LOAD ENA t1ip-flops arc enabled and become set by the next
RCVR CLK pulse. The corresponding: RBUF B LOAD ENA flip-tlop does not set due to the negated state
of RBUF A FULL ENA. VALID RCVR DATA stays true while the entire data packet is being loaded,
holding "VRD" true and keeping the RBUF A LOAD ENA flip-flop sci via a feedback gate.
After the packet is loaded into RBUF A, RBUF ." FULL FNA is asserted by the receive status logic.
When VALID RCVR DATA asserts to load another I" .. .;kct, the true state of RBUF A FULL ENA inhibits the setting of the RBUF A LOAD ENA llip-flc1p but allows the RBUF B LOAD ENA flip-flop 10 be
set. Thus, RBUF Bis selected to receive the next data packet.
Selection will continue to alternate to the empty RBUF, If both RBUFs are full, neither RBUF A LOAD
ENA nor RBUF B LOAD ENA will assert and the klad operation will not b:: executed. This condition
causes the receive status logic to raise a flag to both the link and t.he DP (see Paragraph 3.8).
fhc toad operation is inir.iated by the assen ion of VALID RCVR DA TA. If neither address counter has
overflowed (both RBUF A OVFL and RBIJF B OVFI. arc false), "VALDA T" asserts aP.d is ANDcd with
RBUF A LOAD ENA I<> assert RBUF A REG ENA. RBUF A REG ENA gates the output of the RBUF
A in rc,gistcr to RBUF A.

"VALDA T" is synchronized by RCVR CLK and sets the pubc-width llip-Oop. The flip-flop output is
ANDcd with RBUF A LOAD ENA to assert WR RBUF A and SEL RBUF' A. SEL RBUF A enables
RBUF A. WR RBUF A enables RBUF A for a load operation. The output of the pulse width llip-f1op is
delayed 50 ns and then fed back to reset the. flip-flop, converting the SEL RBUF A and the WR RBUF A
signals into 50 ns pulses.
Another output frorn the pulse-width flip-!1op is delayed 20 ns and AN Dcd with RBU FA LOAD ENA to
assert CLK RBUF A ADDR. The setting of the pulse-width tlip-llop is synchronized by RCVR CLK,
hence the incrc111cnrn1ion of the RBt'F A address counter is al;.o synchninizcd by HCYR CIK.

LOAD SUF
{
(FIG. 3·5)

(MLOADI

_R...
s_uF
__
B_M..;L;:.;O;.;.A..;D;_E
...N
...A~.--.......
MLOAD

RtlUF A MLOAD ENA

SF.L RBUF A

FF
SET
PORTCLK

CLK

{ RBIJF A READ ENA
(flG. 3-3)

ClR

\FrG. 3 _51

PULSE
WIDTH
FF

READ BUF
RSUF B READ EN.A

READ R,...B_U_F_B_ _..

RSUF A MLOAD ENA

r-;;--------,------,
I
I

RBUF LOAD SELECT ION LOGIC

IY)

s T
RBUFA
LOAD
ENA

0
(FIG. 2 .JO) VALID RCVR DATA

30NS

RBGF A LOAD ENA

(VRO}

iFIG.

VAD

READ BUF
RBUF A READ ENA

CLK
RBVF
AADORl

_R_s_u_F_s_~_l_LO_A_o

(,..F'_G_.-3--5-)

,...R~C-V~R-C~L~K-+--+----+-4CLK

3-51{

__E_N_A_ _ _......_ _} (FIG. 3·9)

SE.T

ABUF B
(TO RBUF B )
RBUF B 1---'-+=l"'O,_.A;:;;D...:E:.:..N;.;..A--- SEOUE NCI NG
D

RBUF A FULL ENA

(FIG. 3·9) { ABUF B FULL ENA

L..

LOAD
ENA
FF

I
_..__. ______ ......._._.,_____
CL~LR

(FIG. 3-5) ~F "\ MLOAD ENA

NOTE;
LETTER DESIGNATIONS IN PARENTHESES REFER TO ENGINEERING DRAWINGS CONTAINING CORRESPONDING
LOGIC. THE RBUF LOAD SELECTION LOGIC IS ON SHEET Y. LOGIC NOT DESIGNATED IS ON SHEET H.

Figure 3-8

LOGIC

RBUF Sequencing Logic
3-!8

VALID RCVR DATA

ICU'! f!SIJF

(FIG. 3-9) ABUF A FULL ENA

[RELEASE
R UF
\...
{FIG. 3·5) 1 RBUF A READ ENA

AADDRl

The RBUF .\ addrc.;s counter is in(rc·1Jl(:,Hd <m :he ir:1iiing edge ,,f CLK RBL! ·\ ,\DDR. By >hifk1g
CLK RBlT \ ,\DDR 20 n,;, it is as,urcd 1h:1t RBUF Ai.; tfaabkd 1SU RBLf ,\negated) before· the
:iddrc" is changed w the next lcx·;Hinn.
,\f1cr the datJ pJcket ha,; bt:en loaded inw RBUI· A. the' RBLT ,\ dddre.,;; ((>Unll'r i~rn,1 be re'''t to 1er•)
,\1 the end 1Jf the load opcrali(m, VALID RCVR D.\TA ncf:Hes. One cycle later RliUF A f'ULI l'NA
as->erts mdic:uing th:it RBUF Ai<; full .rnd n:.1dy to be re.id out 1,1 the pen. During thi, c:clr. ltlc ...~gated

state of !x1th ol the-;e <ignals assen:. CLR RBLF ,.\ ADDR :ind, ,,r, the ne.1: RC\ R CU,: ruise. '1>'Crt~
CLK RBL'F :\ ADDR. This de,m. the RBUF A :iddres, c.:,unter, preparing it 1,: .;lock r1'.'t RBL F \ I< F.\D
operation .

.l B RBlJF .MLOAD
Refer h> the RBlF lo~d sdc.:tion logic in Figure 3-~. The ;J.;,;crticm of RBLT A \1LO,\D FSA direct!\
:,~t> the RBUF A LO,\D f.,l\A 11lp-tlop and directly 1csct-; 1hc RBUF BL().\[) E:\.\ :1;r-tl•)p. Thu'.
RBUF A LOAD E"\A is true during the RBUF MLOAD 1ipcration.

The RBUr MLOAD opi;ratiun is initiated b) the. J'scrtiim ,Jf LUAD RUF The LOAD BtF command i,;
\ '1Ded with RBUF MLOAD (as,encd by either RBLF .\ \1LOAD EN\ 0r RBlf B \110 \0 El\A) tu
assert RBUF J>.,;PLT MFX SEL RBUF MLO;\D and RBl'.F IS PUT \fLX SEL switch the RBUF m
mu' to "'lc.:t the p.irit) bit and the data byte from the DP. RBl:F l:"-IPt:T ML.\ SE L "i"' enable~ the
\1LO/\D f1ip-tl<.'P to be set by the ne.\t PORT CLK pulse. The !lip-ilop (1utput 1."MI OAIY') is .\'.\DED
Y.ith RBUF t\ MLO,\D E'\A to as:-.crt Rill TA RE Ci Ei\A. RBlF AR EG I'\.\ gate; the output of the
RBLF A in register to RBl!F A.
"ML1JAD" also ,;cts the pulse widtli Oip-tlop. The !lip-tlc1p Cllltput i' AN!A:d \\'iih RBl.'F .\LOAD F~.\
to a"'cr1 WR RBUF A and SEL RBUF A. SEL RBU' A cnabk' RBlfF \ :md WR RBl.. F A cnahb it
for'' load. The 1>u1put c>f the pulse 1<idth flip-llop is delay<xi 50 n' and then fed b.1ck w reset the flip-!lop.
(On»:rting SEL RBLF A and the WR RBl Jf A sign;tls mt\• "I' ns pulses.
An1)thc · c>utput 1rom the rulsc width 11ip-f1op 1> delayed .20 r.; aqd :\'\[)i:d v.1th RBl.iF '\LOAD l'N.·\ 10
assert CU: RBL'I' A ,\DDR The setting of the pulse-width llip-flop is >:;r..:hronizcd by PORT CLK iv1.i
the M.LOAD flip-11op). hcncc the inuemenlauon. of t.hc RBl.T A addrcs<; (:ounter i> "1~11 synchr.:inizcd bj

PORTCLK.
The RBL F A address (<)Untcr is incremented un the trailing edge .,i CU:: RBl.T ,.\ .·\DDR B.\ :;hifting
CLK RBlT .•\ ·\DDR 20 ns. it 1> a''urcd that RBLF A 1.s di;.:ibicd (SEl RBLF A r·<!l,;c\ hcforc 1hc,1ddrcss
i,; changed to the ne:>.t !ocJtion .
. \ftcr th~ M'... C.·\D opcr.atlun i> completed. the RBCF \ :1d11r~.s, cc1unttr mLi>t be r~;.ct to zero. The mk:ro·
rndc accomplishes the re,..:1 by selecting RBlT A "ith Ih.: SEL READ Bl F ~:nnm:ind (:Merling RBUI
A READ EN,\ fr,Jrn :he buffer select logic) J · :J then '''~r-ur.g : he- R FLE.\SE R RUF <.:Qrnmand. The
AN Ding (if RELEASE RBUF :md RBlT ·\ Rb\D E'•A .1ssem CLR RBL'F ·\ ADDR. The nt.\I RCVR
CLK puls.:- as,;crts CU.: RBt:F A :\DOR. thereby rc:>ctting the: counter.

J.7.6 RBl'F READ
The RBL:F READ klgic 1s illu>tra1ed in Figure:~-~ The RBUF RL\D "JX'rntic·• i<u:ncd b' the N;cr·
tion 11! READ Bl IF. The Rf'. AD BU c.m1m:rnd i-; ·\ "'l:kd "ith RBLF ,\ RE'D t::'\ ,\ ii) ,1,,cn E'.'. RB
·\and SEL RBUF .\. SEL RBUF A ,.nabk:' RBUF ,\ ,md EN RB.\ 11"1<:·' UK d::u irnm 1h,, RBLT ,\out
rcgisti:r nntu the RBliF data line,. (Th.: signJl in the RB'.. f B 11'.::1 ·p.:lh ,,;orri:>p.:.nding tu EN RB A is
READ RBUF B)
The A'.\Din.o ~f READ RUF RBl.F A READE''"'· ard PORT CLK fl."cr-:- l c K RBl FA \Df>R.
Thu>. the RBl.'F \ addn.•,; t.Juntcr h ·'~ nchroniz.ed by PORT CL!\ :rn•r ch< DP.

After the READ RRUI Ofl<'rJtion i' rnmrbc·d. UK RIH T .·\ :1ddrc,> C:·ci\ifll.:r· cr11h\ be: rcsci tic z,·r•r T'h<
micrncode d,...:s thi; b' sckc1in11. R BL F ,, with the SEL RF ·\D BLF ;:;om1:::•nc:
RBLr .\RF\ D
E:'\A from the trnffe~ .sck1.•t k;11.k) Jnd then a,;scnin~. the RELL\SE RBtT
Th<' ,\Nfling •Jf
RELEASE RBlT .rnd RBLF .\READ ENA :N•cn.s CLR RRUF A ,\DDR. The nn1 PORT CL!I. ;misc
as,cns CLK RBtF A ADDR thereby re,ctting th(' n•urlll'r

3.8 RCVR ~IA TVS
''RCVR stJtucC is placed cm the port data bu;; fr.rm the PB read mu.x when tk RL\D RCVR STAT~,'S

command is asserted. "RCVR statu;," consist> of eight >ign:ds. The. signal;;, dc~.ribcd in Paragraph, JX I
through 3.~5.1. arc listed belo.,.:
CRC ERR
2.

3.
4.
5.

RBl'F A FULL
RBLT B Fl.U.

RBLT B FIRST
RBlif A !1CS
RBliF B BUS
RCVR A E"'iABLE
RCVR B El\iABLE

Figure 3-9 illustrates the RCVR stams logic.
3.8.1 ('RC ERR
The link d<>e> a CRC check on recehed data packets. The re-:eivc MatusCRC ERR bit l:l as..-;ertcd if a CRC
error is detected. The CRC ERR bit h used on!~ 1n maintenance loop m,lde,. 1.t is not u>ed in normal
operation.

The CRC ERR bit asserts after the 3''>SOCiatcd data packet has been ki;1dcd in1D the RBUF Thus, if;; CRC
error is flagged, the packet containing the error is in the RBLf
\'Al.ID RC\'R STA TliS asserts after a data packet has been kl<lded into the RBUF with a VALID RCVR
DATA operation. If no CRC error occurred, CRC STATLS 1> true when VALID RCVR ST..\Tl.$ j,
asserted. Thi> causes CRC OK hl assert. CRC OK enable\ 1he CR.C OK llip-flop to ;;et (Jn the. next RCVR
CLK pulse. The as...;erted output from the ilip-flop results in a negakd CRC ERR blr for RCVR ST.\ Tl.S.
3.8... RBlif A nu,, RBl'F B FULL
If RBUF A had just been loaded wnh .; data packet ha•'i,,g no CRC error. CRC OK is a:\serted and
ANDed with RBUF A .lOAD E~A to enable theRBl. f A FULL E"\A flip-flop tn ;;et RCVR CLK set;;
the flip-flop asserting RBl.<F A FULL E~A The fl.ip-fl.•)P is he:, ··"'.
::_feedback gate holding RBlT .\.
I-TU. ENA true. The 11ext PORT CU( pulse as;.em RBtT A Ft LL via the RBt.I' A fll.L flip-flor.
When RBLF A FCLL is <rue it asserts REC:\ TTN w the DP.

RBLF A is emptied 1.read c1ut tci the DP) by ;1 READ RBlF {•petai.ior.. After a READ RBCF operJtion, a
RELEASE RBLF comma.nd is E>sued to re>et the RBUF A addres, c:oumcr anu t(• release RBUF A ba•k
to the link. The RELEASE RBl'F command releases RBt'T A tr. the link by ao>>ening CLR RBLT ..\ vi:1
two flip-flop:» RELEASE RBUF is ANDed with the negated >tate ;!! RBLF BREAD ENA to en;i.bk the
first CLR RBUF :\ fl.lp-t1<)P t.o be set by PORT CLK. (RBCF :\ha~ ju't been read .:>ut: therefor<:. RBUf B
READ ENA will be false I The output from the first !1ip-fa1p en.1ble-s the se,.;;rnd CTR RBUF A t1ip-ilor
"'hich is set by RCVR CLK. Thus. CLR RBU' A ts >yn.::hr.-:1r.md by RCVR Cl K
CLR RBUF A breaks the feedback lat~h holding the RBLF ,,, FtLL F'\1\ 1Tip-fbp se\ Thi., ncgai.e,, both
RBliF A FULL ENA Jnd RBCF A FULL indicating lh.H RBUT -\ is
:-,,r :in"nher io;1d fro1:1 ihc'
lin~.

,,-ad'

RBUF A MLOAD ENA
(FIG. 35) - - - - - - - - - - - - - - - - - .

SET

A .._C'-'L'-.R_R--'B-·U_F_A_....

(FIG.

3-8){

D
RBUFA
FULL
FF

FF {Y)

REC ATTN

CLK
CLR

').....-------------+--+(FIG. 4-10)

RBUF B FULL

FULL ENA
1--..----......,,__,.-.i
D

RBUF 8
FULL
FF

RBUF B
FULL
ENA
FF {Y)

(Y)

~----tcLK

!FIG. 3·5i

{STATUS

RBUF B
FIRST
FF

RBUF B
FIRST

{Y)

CLK
'-..;C;.:;Lp.;R;......,

RBUF FULL
1-------'---t D
FF

{YJ

CLK

RCVR BUFFERS FULL

!FIG. 2-12)

RCVR CL.K
-------.........;cLK

ClR RBUF A

CLR
R.BUF A
FF

CLR
RBUF A

!Yi

(Yl

CLK

RBUF 8
READ ENA

RELEASE RBUF

PORT
CLK

CLK

CRC ERR ( RCVR STATUS\
, FIG. 3-3
)

CRC
OK
RCVR CLK

(Y)

CRCOK

.___...._....,o

CLK

RBUF A MLOAD ENA

VALID
RCVR

( RCVR STATUS)
. FIG. 3.3

RBUF B

SET

FIG.

}

(Y)

PORT CLK

CLK
CLR

CRCOK

RBUF A FULL

RBUF A FULL ENA

RBUF A
FULL
ENA

(FIG. J·Bl~A LOAD ENA

RBUF A BUS

CLK

VALID RCVR STATUS

CLK

}CcvR
STATUS )
FIG. 3·3

J RBUF
ABUS

(FIG 23)

ICCS PATH 8

FF
K (A)
CLR

RBUF A
READ ENA

CLR RBUF B

CLR
RBUF 8
Ff

CLR
RBUF B

IYl

(Y)

PORTCLK

------'-~-'-.....jCLK

RBUF B BUS

8
{FIG. 3 Si RBUF B LOAD ENA

CLK

RCVR CLK

J RBUF

B BUS
CLK

FF
+V K {A)
CLR

RCVR CLK

Figure: 3-9 RCVR Statu.~ logi.:

J-2l

NOTE:
LETTER DESIGNATIONS lN PARENTHESES
REFER TO ENGINEERING DRA'¥1.NGS
CONTAIUING COHRESPONDING LOGIC.

Identical "RBUF FULL" logic exists for RBlJF B. If the data packet had been loaded into RBUF B
instead of RBUF A, an identical sequence would have occurred in the corresponding RBUF B logic causing
"RCVR status" bit RBUF B FULL to assert.
Should both RBUF A FULL and RBUF B FULL be true, RCVR BUFFERS FULL is asserted to the link
preventing it from initiating another VALID RCVR DATA operation.
3.8.3 RBUF B FIRST
If both RBUFs arc full (RBUF FULL true), the RBUF B FIRST status bit indicates which RBUF was

filled first. The RBUF B FIRST status bit is invalid (not sampled) until both RBUFs are filled.
RBUF B FULL ENA is ANDed with CRC OK and the negated state of RBUF FULL to enable the first
RBUF B FIRST flip-flop to be set by RCVR CLK. The flip-flop is set if RBUF Bis full but not R8UF A.
The second R8UF B FIRST flip-flop is set by PORT CLK asserting RBUF B FIRST.
If RBUF A is loaded while RBUF B is still full, RBUF FULL asserts holding the first RBUF B FIRST
flip-flop set via a feedback gate. With both RBUFs full, the RBUF B FIRST bit is sampled and found to be
true.
3.8.4 RBUF A BUS

This bit indicates which Cl bus r;;ceived the last data packet loaded into RBUF A. If the bit is negated, the
pack was received on CI bus A. If the bit is asserted, the pack was received on CI bus B.
While RBUF A is being loaded, RBUF A LOAD ENA is true. RBUF A LOAD ENA is ANDed with
VALID RCVR STATUS and ICCS PATH 8. Thus, when VALID RCVR STATUS asserts. the ICCS
PATH 8 signal is sampled. If the signal is true, the data packet just loaded into RBUF A was received on
Cl bus 8. In thi~ case, the RBUF A BUS flip-flop is enabled and sets on the next RCVR CLK. When the
flip-flop sets. the RBUF A BUS bit is asserted as part of "RCVR status."
3.8.5 RBUF B BUS

This bit indicates which CI bus received the last data packet loaded into RBUF B. If the bit is negated, the
pack was received on Cl bus A. If the bit is asserted, the pack was received on CI bus B.
The RBUF B BUS logic is identical to the RBUF A BUS logic with RBUF B replacing RBUF A.
3.8.6 RCVR A ENABLE
This bit is set if the RCVR A ENB bit (bit(OO)) of a "link enable" command byte is set. The RCVR A
ENB bit must be set for the link to respond to traffic on CI bus A.
3.8.7 RCVR B ENABLE

This bit is set if the RCVR B ENB bit (bit (07)) of a "link enable" command byte is set. The RCVR B
EN8 bit must be set for the link to respond to traffic on Cl bus B.

3-22

CHAPTER4
COJ'\TROL STORE

NOTE
The funclional block diagrams in Chaph•r 4 use logical AND and OR symbols. II does not necessarily
follow that a corre!>ponding gate exists on the t'ngineering logic prints. The assertion of input~ A and B
causing ihe a~sertion or output C may be rt'presentt>d
on a block diagram by a single AND gate, ye1 the
engineering drawing may show that sen•ral drcuit
stages are imohed in the ANDing operarion.
The block diagrams are keyed to the engineering circuit schematics (CS prints) by letter designations in
parentheses. Tbe letters spedfy the CS sheet that
contains the logic a~sociated l\ ith the functional
blocks in the diagram. The logic for the CS function
discussed in this chapter, is dhided he1-.een the DP
and the PB modules. A note on each block diagram
specifies whkh module contains the logic used in N1e
diagram.
The signal names w.ed in the fu~ction11I block di11grams are the names used on the engineering CS
prints. Where other signal names or nott's H(' used,
they are l'nclosed in parentheses.

4.1 Sll\IPLffIF:D BLOCK DIAGRA!\I
The control store (Figure 4·1) consists of :iK bytes of storage used w ,:tore the port micrvco<k The microcode uses 48-bit microwords. Each micr.iword consists <Jf 47 Ctrn:rol bits (BUS U(46:00)) and J sync bit
used for maintenance purposes. The <K of Sl<l':l!!<~ consists ()12K of RAM and l K of PRO\L
rhc RAl\1 area <lf the CS is writwn during the uniniti,dizcd stak'. lB JN (i J :00) frc;m il1c DP io- pbc.::d on
the CS 1/0 bu;. (BUS U{46:00)) :rnd then writkn into the CS. The kiw.;r 32 bits :ire 11ritll"n first :ind then
the upper bits.

Bit 46 1s the p;iri1y bit for the microword (cxduding tht: sync hi! .L '\ parity check b J'<:'.·fomid on cad1
mkroword read out of the CS during the initialized state wh~n th~ rniccnxodc is running. If'" parit:- error is
detected. CSP!~ is asserted io the DP ~s an emir flag.
:-.fust of th<: micrnword read from th~ CS is l.atchcd inw the· microword f(~gio>ter. Tile r-:gist~:· 011:p1.ts '''ntrnl sign,1ls to ,ill of lh<.t rort modules.

~-I

MICROWORD
REGISTER
(TO DP) .....__ _ _ _c.....s_P_E_ _ _-f

PARITY
CHECKER

...,_ _ _.,........_ _ _ _ _-...I

BUS U <46:00>

BUS U <45:17>; BUS U <11:00>
BUS U <11:00>

SEQ CNTL <4:0>

BUS U <16:12>
IB IN <31:00>
(FROM D P ) - - - - - - - - - - - - - - - - t

BUS U <46:00>

c>-.co...;.;;..,.;____-1

fMo9o~1

BUS U <46:00>
BUS MO <31 :00>
(TO D P ) . _ - - - - - - - - - - - 1

_ ___.,__.

CONTROL
STORE

MAOR <12:00>

BRANCH
LOGIC

L ___ .....,

(3K)

BR <3:0>

MADR <11:00>

IB IN <31:00>
tFROM DP)------..;.;;;........,...-'-......,...-------1"'1

MAINT.
ADDRESS
REGISTER

MICRO·
SEQUENCER

loP -;;o~I
EN MADR
f MICROCODE ~-'-E""N_se_o__.
' " - - - - ' - - - - - - 1 1 - - t STARTUP

NOTE:
THE LOGIC SHOWN IN THIS
DIAGRAM IS LOCATED ON THE
PB MODULE EXCEPT AS NOTED.

L __ _,
TK·B7.:i;O

Figure 4-1

Control Store Simplified Block Diagram

4-2

The CS is addressed via 12 address bits (CSA (11:00)) obtained from c:ithcr the microscqucnccr or the
maintcnan;;c addrc's register_ In the uninitialized state (q;. during power up) the maintenance address
register provides the address (M/\DR (l J :00}). The register input is IB IN (l 2:00) from the DP. The minocodc start-up l<)gic enables the maintenance address register by asscning EN MADR.
In the initiali1cd state (while the microcode is runn;ng) the address is provided by the microsequcnccr. The
microscqucnccr is enabled IJy EN SEQ from th~ 111icrocodc start-up logic. The micrnscqucnccr uses bits
BUS U( I l :00) from the microword as the base <tddress. Branching logic is used to specify the lower four
•tddress bits. The branching conditions arc selected by sequential control bits SEQ CNTL (4:0) which are
actually bits l3US U(l6:12) of the microword. The microsequenccr contain> a memory stack and a PC
counter for address control.
The CS micmword and the contents nf the maintenance address register can be read by the DP via the
maintenance mux. The mux scJccu, the lower 32 bits of the microword. the upper bits of th.:: microwurd, or
the 13 bits from the maintenance register for the MD (miscellaneous data) bus to the DP (BUS
Ml)\31 :00)).

Figure 4-2 is a detailed block diagrnm ofthe control store area and should be referred to throughout the
rest or this chapter.
4.2 MICROWORD PARITY
A parity ch.:ck is made <lll each microword as it is read out of CS. BUS U(46:00) is input lo a microword
p:1rity checker which outputs CSPE to the DP if a parity error is detected. Bi1 46 is the purit) bit Pencr;iy
ing odd parity for each microword. Als(). note that a CS parity cr~or resets the microword register containing the microword with the error.
·1 .1c SYNC bit (U47) is not included in the parity check as it b a programmable bit that can be used with

any or the CS microwords. even the mi..:roword·; in the PROM area whose parity bits cannot be changed.

Figure 4-3 is a block diagram of the parity checker. Each byte of the microword is checked for odd parity
in parity generators. Those bytes with an odd number of bits ;isscrtcd will :•s1-.crt the output of th~ir 1espcctivc generator. The generator out.puts arc themselves input int.u a summation parity generator where again
;In a5scrtcd output means an odd number of as;,ertcd inputs. This is a ''no crrnr" state which would condition the parity error nip-lfop tn reset.

If the number of asserted input> to 1hc summation parity generator i> even. the generator output is false
and the parity error 11ip-tlop set& ()11 tht: next SEQ CLK T3 pulse. When the tlip·flop si;ts. CSPE is
asserted

4-.\

EN CS DATA IN

IB IN <31:00>
CSWE

CONTROL
STORE
(NOTE 31
(FIG. 4-6)

MICROWORD
BUS U <46:00>
PARITY
1,.-=.-=--~-- (FtG. 5-2; 5-111
~--=--=----'----4"1 CHECKER

BUS U <46:00>

(FIG. 4-3\

U4?

BUS LI <45:00>

'--lc::B....:l....:N_<__;:1.:;2_:00_>-9'\ C

CSA <11:00>
MADR <12:10>

BUS U <31 :00>
BUS U <46:32>
BUS MD <31:00>

L____----8

U47

EN MAINT

MADR <12:00>

(FIG 5-9) ~

XBUS LSA 00

MUX
SELECT

MADR12

(U)

MADA <'.11:00>

2911

MICROSEOUENCER
FE
(FIG. 4,8)
,..._P_U_P_ __,
,__ _ ___, MICROWORD'
REGISTER

EN MADA

~-- - - ,

IB IN <12:00>

I ?.P

MAINT.
ADDRESS
REGISTER

I
I
I

MODULE

(P)

1. THE LOGIC SHOWN IN
THIS DIAGRAM IS LOCATED
ON THE PB MODULE EXCEPT
AS NOTED.
LETTER DESIGNATIONS IN
PARENTHESES REF ER TO
ENGINEERING DA.l'.WINGS
CONTAINING CORRESPONDING
LOGIC.

COMMON 110.

EN SEQ

CONTROL

MICROCODE l - - 1 ' - - - - - - - '
STA.ATUP
(F!G.4-121
(FIG.4-121 SEOCLKT3

UN!N!T~

'.16:12>
DPUP

(V)

I .__.;;.,;;.;..;..._. .

i.-----1,>-1 ~~~~,'"

c__ :...J

12) ~)

'"'"'" co,orno"r

sea

'"-'c'.~

L_3USU<11:00>

Control Store Block Diagram (a)

!FIG. 4· 10l

I
Figure 4-2

(FIG 4-9)

F'1G · r~~,____.

BUS U

DFE

~__,.._..,.cLK CLR

FORCE ZERO

BR <3:0>

B
2.

i--1-_;;_;..;:..;:..:::;..._J

NOTES:

~~~<~.S_1:~SO_> ~~-~1~

·-------0

BUS
BUS
BUS
BUS
u <16:12> u <11:00> u <32:24> u <45:33>

BUS
u <23:17>

IB SAC 2

BUS U 23

BUS U <22:21>
BUS U <20: 17>

IB SAC <1:0>

}

,.__ _ _ _ _ _.._
IB DST <3:0>

(FIG. 5-5)

4_7 _ _ _ _--1..r~~~~.,_s_v_N_C.___ _ _...... (BACKPLANEFL~G)
b 1---1-------;1-------;1-------;1--u_
r-B_u_s_u_<_4_5_:4,...3_>_ _.,.. MICROWORD ALU FCN <2:0>
BUS U <42:'40>
BUS U <39:37>

l'-------..i

c 1----1--.

BUS U <36:33>
- - - - - - - - 1..
BUS U ·<31 :24>

,.._B_U_S_U-----------;~

ALU SAC <2:0>
ALU DST <2:0>

....

(FIG. 5-13)

ALU A/B <3:0>
LITERAL <7:0>
- ( F I G . 5·2; 5-5)

BUS U 30

1--S_E..;..L_EC_T_ _.,(FIG. 3-5; 2-211

BUS U <27:24:>
BUS U06

EXECUTE (FIG. 5.9 )
PMUX<l:O>
1-------•(FIG. 5-2)
LINK CONTROL <3:0>
(FIG. 3·5; 2-21)
ASRT DEAD
}FIG.6·11)
ASRT FAIL

BUSIJ11
BUS U 10

MIN
(FIG. 5-2)

---,FORCE

~M-C_L_R----•
>-----;~C~L_E_A_R_--1~(FG
i------------;t---L._M__,,
I . 6-11)

BUS U09

(FIG. 5-11)
INTR

BUS U 08

fDP ~~E__J

BUS U 07
BUS U 04

BUS U 03
BUS U 02
BUS U01
(NOT USED)

BUS U 00

MISC CNTL

e-------'
TK·8729

Figure 4-2 Control Store Block Diagram (b)

4-4

( FIG ..) BUS U <46:00>

BUS U <07:00>

~BUS U <15:08>

BUS U <23:16>

BUS U <31 :24>

PARITY ---~
GEN.

PARITY
GEN.

CSPE
SUMMATION
PARITY
GEN.

PARITY
ERROR

PARITY·

GEN.

BUS U <39:32>

PARITY
GEN.

BUS U <46:40>

PARITY .,.___ __.

CLK
CLR

GEN.
!FIG. 4 . 12) SEO CLK T3
NOTE:
THE LOGIC IN THIS FIGURE IS CONTAINED ON
SH.EET S OF THE PB ENGINEERING DRAWINGS.

Figure 4-3

Microword Parity Checker

(FIG. 6 l l) REG CLR A

4.3

CS MICROWORD

4.3.1 Micro11rnrd Fields
The 48 bits ,,f the CS mkroword arc shown in Figure . 4, grouped by fit-Ids . Table + l dc"ribes each of
the fields shown .in the figure'..
4.3.2 Microl'iord Register
When a microword is read out of CS, most of the bits arc latched inhl th.: micrnword rcgis11:r by SEQ CLK
T3. The remaining bit fields arc the next address field and the SEQ CNTL field us<.·d IO select the next
microaddrcss, and the IB SRC and IB DST fields. The IB SRC and IB DST fields rnu-;t be present in th~
DP at the stan of the microcyclc, hence, they cannot wait for SEQ CLK TJ to chick the microword
register.
The register is rc:;ct in the uninitialized state and whenever the current mkroword produce-; a parit)' error.

4 7 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
ALU FCN ALU SRC ALU DST

ALU A/B

LITERAL
LINK AND
BUFFER CONTi10L

SYNC

TYPE

! PMUX

NOT USED

SELECT

23 22 21 20 19 18 17 16 15 14 13 12

I1~ s~c I :1a :osf I ~E1 c~T~ I
11 10 09 08 07 06 05 04 03 02 01 00
NEXT MICRO ADDRESS

MISCELLANEOUS
CLR ASRT SET UP
I INTR REG
DEAD A
PON

MCLR

GO
PF ASRT SET
INITIALIZE VLD FAIL B GO

NOT USED

WAT

INH RBPE

Figure 4.4

Microword field~

LINK
CONTROL

Table 4-1

Microword Fields

Bit

Name

Desc.ription

SYNC

A programmable bit that is used during port
debugging to indicate the execution of a specific
microword. The SYNC bit is not included in the
parity check of the microword. The SYNC bit
can be written in both the RAM and PROM areas
of the CS. The bit is available on the port
backplane.

PAR

The odd parity bit on bits (45:00} of the CS
microword.

(45:43)

ALU FCN (2:0)

Function code for the 2901 ALU <:>n the DP.

(42:40)

ALU SRC (2:0)

Operand source code for the 2901 ALU on the
DP.

(39:37)

ALU DST (2:0)

Destination code for the 2901 ALU on the DP.

(36:33)

ALU A/B (3:0)

The A and B address lines for the 2901 scratch
pads on the DP.

TYPE

Selects the definition of bits (31 :24) as shown
below.

(31 :24)

LITERAL (7:0)

Valid when TYPE= 0. Used in the DP as a number or as an address.

(31 :24)

Link and PB control bits. Valid when TYPE= I.
The bit fields are defined below.

Not used.

SELECT

Indicates that the LINK CONTROL lines
((27:24)) are valid.

(29:28)

PMUX(l:O)

Selects a byte in the packet buffer input and out·
put registers on the DP.

(27:24)

LINK CONTROL (3:0)

Specifies operations on the link and PB. This field
is valid when SELECT = l .

(23:21}*

IB SRC (2:0)
Selects the source of BUS IB data in the DP.

(20:17)*

IB DST (3:0)
Selects the destination for BUS lB data in the DP.

•

These bits bypass the microword register and go directly to the DP.

4-7

T 11ble 4-1

Descripiion

Bit
(Io: 12i

!\1icro,.ord Fields (Cont)

SEQ C STL (4:0)

Specifics the np<:r;it1cm uf lhc 29 l I mic:w>1.,yuc~nc
er. selects t.he br11.nch condition~ that .titer th..:
minoaddrc>;,, .md sck•·ts the definition uf b11'
(1100),

( 11 00)

Next microaddrcss

This field is the b;1se addrc~s that i' modified bv
the branch bits lO form the ad.Jrc,;s of the next
m1ctoW\)rd. It allows ·.he mic1\x:odc. to jump to
any address in the CS. This field is valid ."<• long
as the SEQ CNTL ficitl • not all is.

(I I :CXl)

MISCCNTL

This field (rn1s.:dlancou' 1.·(1mrol1 alhJW'\ the mi~r·
c.:odc to control mi"cllane.ous !lags and funcuons
•n the port. The field is valid when the SEQ
CNTL rtdd 1.; all h. The MISC CNTL bits :ire
dc~''ribed below.

MCl.R

This bit tm.aintcnuncc dc<H) cau>es the port lo
enter the u11ini1i,1;i1cd st.,11e.

INTR

Sets the intcrrup1 rcquc't Hag that in1ti,1tc' an

interrupt sequc'\cc to the host CPU.

INITIALIZE

Generate' ;in init•alizc signal to the link.

CIR REGWRT

Clears the REG WRT flag in the DP.

PFH.D

When the pi.>wcr-fail vahd bit is set. the ·\SRT
DEl\D and ASRT FAIL bits arc valid.

l\SRTDEAD

facilihHcs proccs.sor mitialrr.ation <1nd booung,

ASRTFAIL

hicilit;it~s proce;,sor inittalitation and b<X>liniz

SETA GO

Start" 3n external bu;.: trnnsfcr with the host using
the A p;1ramctcrs

SETBGO

Start" un external bu> trarhfcr with the host using
the B par<rmcrer,.

UP PD!\

Ali<Jw., the mirf,><:odc w set lhc PDN (p<>w~r
down I bit •n the port C'<mfigur:irion register,

lNH RBPE

This bit is set during <.I DP n;:;1d of the first b;t(

frnrn :1 p.1~k.:t bulfer. The first byte n·ad i> :dw:1y,
undc~fint:d dm8 1;.,;H H BPE prc\;.nt, a parir··
error fr1Jn1 asserting on lht.: unat.~fincC daLt.

4.4 :\Ul'\TENA:\CE :\ltX
During the unini<iJ.lilcd slat.: the CS can he rc"d l'I the DP fm 11'aintcn:1n1:c purpo'''s. 'The CS m1(Tdw,ml
i> input rn the DP 1·ia a maintenance mu\ a.nd ,, .1'.:·hit rnis.:e.liJn<.:<:1u., J·"t" bu' ! BLS M Dd I :l)(f:J ·1 he
microword i;; :1 pplil:d w the maintcn•llll'C mux 1<•hcrc lht mu~ firs1 '"kct> 1bi: hJ11,·r JJ b;r, 1BUS U() l ()1))'
for thl' MD bus. and then the upper lb bits (BUS L{4h:J2\: L4 °)
The DP can alsc' rc,1.d the 13 bits from th.: maintcn,:Jll'c ;id dress rcgis:cr ('I.I.\ DR (. '. 2:oo: \ 1 i" 1he 11nin1c··
nan.:c mux.

Mu.\ :.;ek..:tion j, a1xompli-;hcd using one d the k..:·ci! :;tore address bi!' fr·•m the DP i,XBCS LSA Cl11i and
\IADR 12 from the maintcncn<.:c address r.cgisu:r XBl'S LS.\ 00 sdc.:ts citht:r the mkn··wc1rd ,,r tlw
maintenance address. \!!\DR 12 ic; use-0 here ~nd lhf1)ugbout th~ CS logic w select the upper or IDwcr
portion ,)f 1hc mic-roword. MADR 12 fol.;e ;ekct' the~ luwcr !'m.i.m d:H.:S U\3i :00)). M '\DR l '.:' lfll('
sckcb the upper porti,,n 1RLS U<4td2): U4'.'l Ti<blc 4·:' hst> the '''m i.~k~1i,1n ,·ode

Table 4-2 Maintt'llllnce \fux SeleciHm C<Hk>
XBl'SlBAOO

MADR 12

BUS \1Di31:00/

()

RLS L iJ LOO)

\1ADR;12.u<J)

llC~.lll'1

:lS."'t'rtt,,'Ci

dc>r.'t '""'

4.5 CO\'TROL STORE SPACE: AND I.OGie
4.5.1 Control Store Space
The ~ontrc~~ ~ti.Jrc :SPJ~c (Figur\!· ..i..)t h•:l:S a tn:i~:re!f.nr~ "rL·:: ·T :nea ~1nd ~!
sh•r('. are:_t. Th~: mi'-:ro\v:rrd j~~)!'{':
an:~1 "'mist'
l K ' 41 ,,f PR0\1 ::md 1K ,,, 4 i
R ,\ \t The .:re"
,;ddn:.,•«cd b1 ! 2 ;;ontrfl'. \h•r\
addrc~s bits CS/\ J l :(MJ) . The two rnost s-~gn.if!\,·;;•.:'1t -~idJr·e·;-..s bib {CS,\ ~.:" 11):-t dirid,· ihc '.'.tC~r1.: ..;.:'c1: ::--L··
three: ban~s .~t:1d ;J;-;::;' used ~i~ t.h~ bdnk ~k"X-t hlt'i, Bi·;_, CSA ,Jl9:00)' ~1ddrc7' ..; 1'w H\:.4 ( ! ~:1 w~~,~a !0<::1:_1\_ ,r,;;,
within eJch ba~k
1

T~~ fl:.ifStnr~ ~·r~~t l~ .~K ·x: 1 ofR!\\1 u~".:~ to :'it•:?r1..' the:
JtJdr~~~~ ~h-c J~ 1Jl !1_~1g st-uragc thu~ g1\~:~n~ ::_, .

SY'\"C hit {l. . '-+'7!. CSA 1: LC;(i·',.·.;\:
ht: 1"L1t: ~l<ifl·, '"l\, t.it i.. t...' ~., -~·...-i
kx:a.twn t.h~- ru-.:;o\.\ord st1}re d.rca. Th(·~\'~(' tn~ c:·:.:-i oc wr;_:h~-r; ;:r;ywhc:--e acn>S~ dw ;1ddrc.-.;" sr('.(.:\
thu~. ~·er. t!;c- ';1':.i·c,=~\\..:1rds in thC" PR()\1 J.rea (tx1~.k
.:~-.:-u:;·c_ h::.\·(: 2: SY~C ~ii: \\.r]!.tt.:·i in
l!H ~!
~

M:·GR C>i.\::>R ~-.
s.TCR E
llAM
RAN•:~

''.·.,...,

- - - - - - - - - - - · - - - - - - - - - :-S.A ')S

. l . ._~ ' •. ,,

4.5.2 Control Store Loi:k
Figure 4-6 i,; a block diagram of the control sLOrc l1>gic. Bank 0 is comprised of six l K :;<Ii PROMs. Each
PROM ,iutputs eight bits onto the rnicroword 1/0 bus (BLS U\46:00)), The high-order PROM outpub
only seven bi1' (BUS U\46:40)). Banks i :ind 2 arc each made up or twelve l K :-; 4 RAMs. E:ich RAM h:ts
a four-bit 1/0 to the microword bm. The high-order RAM in each b:ink uses only three 1Jf its four 1/0 lines
(BUS U\46 44)).

Bits MADR (I 1:10) (identical to CSA (I !:IO) shown in Figure 4-5) arc the bank sciccl bits. They arc
applied to bank select logic where they arc dcc.>dcd to output one or three SEL BANK c:nabling signab.
When true. each SEL BANK signal enables all the R \Ms (or PROMs) in iis respective bank. Address bib
CSA (09:00) arc applied to all the RAMs and PROMs; however, only the RAM> (or PROMs) in the
enabled b,mk will respond t.J the address. The ;1ddrcss bits select a location in each Ill° the RA Ms (<Jr
PROMs) of the selected bank.
;\II 47 bits from the <tddrcsscd location in the selected bank arc available on the microword bus for reading
except during a CS write op.::ration. All 47 bits arc read siniultancuusly,
The two writable CS banks arc divided int\J three p.1rts of four RAMs each. The parts arc 16 bits each and
:uc designated as LO (Bl.iS U( 15:00)), MID (BUS \A3 I: l 6,1). and HI (BUS U(46 .12)). Each p:1rt receives
a separate write enable: signal.

To Mile the CS RAMs. the signal CS WE is acscrtcd from the DP ard then A NDed with MADR 12.
MADR fabc asserts WR CS LO and WR CS ~·ID thw, enabling the LO and MID parts for a write.
MADR 12 true a;,scns WR CS HI. enabling the HI part for a write.
Write data (IB IN(3 I :00)) and a data in enabling signal (EN CS DATA ;N) is received from the DP.
MADR 12 is ANDcd with EN CS DATA IN to again selc.:t th.: high or low portion of the micr(lword
When MADR 12 is false, IB JN(3 I :00) is coupled to BUS U(~ I :00) and written into the LO and 'vllD
parts of the selected RAM bank. When MADR 12 is true. IB JN( I HJO) is coupled to BUS U(46J2} and
written into the HI part of the selected RAM bank.
The flag store R:\M is addressed by CSA(i 1:00) to sclcci bit 47 of the microword being addressed in the
microword s1orc area. The !lag store output (li47) is available on the microword btb for reading ex.cert
during a CS write Clpcration. Bit U47 is read out along with its :1ssociatcd microword.
The flag store is written as bit 47 of the input microword. The input to the flag store RA'-.1 is IB IN I 5. The
flag swrc is enabled by WR CS HI. Thus, the nag is written when IB 1N \ 14:00) is being coupled to BUS U
(46:00) and the upper portion of the 111icrowc1rd is Jcing written.

4-l 1

EN CS DATA IN

MADA 1;>
A ;-~~~~--'-~

(

1-----------------1

aus u<31 oo>

......0<3_1_:00.._>_ _ _ _ _ _ _ _ _ _ _.,.
88,;,IN

BUS U<.45:32>
IB IN 15

!FIG

I
IJ

.,,1

MADfl<11:10>

l=-,
i

...

0~~6 44>

.. 1_s=1.,..:

ADDR

SELECT
LOGIC
{R)

l RAM

SEL BANK 2
SEL BANK 1

I RAM
EN (1 K x 41! 11 K x 4) (1 K x 41

SEL BANK 0 - - i

WR EN
(N)

RAM

RAM
(1 K 41

(NI

(N)

...:_D,_t:_IW-I
BUS

BUS

U<39:36''
CSA <09:'JO> -~-_,...........__..,...._...___,_ _..__,

BANK

U47

-------------~~-=~ =~ =~-c~-A:=R~_"_c=· =:~_,_.-=·'~:="'!: ---------i---------------.,...--""'11""'"'•1(:!~;')

CSA<11:00>

IN)

BUS U<.46:00>

BUS

U<31:28> U<27.24> U<23:20>

ADDA
, RAM
EN(1KX41

I
RAM
(1KX4)

RAM
11i-;X4)

{NI

(M)

(Ml

WREN
{N)

BUS

U<07:04> U<03:00>

ADDA

RAM
(1KX4)

BUS

U<15:12>

RAM • RAM
RAM
EN(1KX4• (1KX4! ll1KX4)
WREN

(Ml

IMI

RAM
(1KX4)'

l (M)

(M!

11 .

BUS

U<46:44>

U<11"08> U<.07:04> U<03.00>

ADDR
RAM
RAM
EN{1K X 4) l1KX41

RAM
(1KX4)

ADOR

RAM
(1KX4)

WR EN
(N)

(N)

BUS
U<46:40'>

(N)

ADDA

BUS

RAM
IRAM
RAM
RAM
EN(1KX4! llK X4) • 11K X4) \!K X 4)

RAM
. RAM
. , RAM
EN 11 K X 4) (1KX4) il1KX4)

WREN

IN)

INi

(M)

IM)

(~)

IMI

BUS

RAM
11 K X 41

(Ml

IMl

BUS

SUS

U<39:32·-.

U<31 :24>

U<23 16>

U<15:08>

U<Ol:OO>

ADDA

NOH

LE'TTER DESIGNATIONS IN PARENTHESES REFER
TO THE PB ENGINEERING DRAWINGS CONTAINING
THE eDARESPONDING LOGIC.

Figure 4·6 Control Store Logic

PROM
11K XS)

PROM
l1K X 81

PROM

(11< X8i

l1K X Bl

(IK X 81

PROM
!1K X Bi

iNI

IN)

(Ni

\Mi

(Ml

PROM
EN

b:~,~~-~c~_·\

. 1 :~0(1--,,·f~ih~:i:'~~.::.nv:j

h.~~-~r,,_·~~,

l'~\:' '-('kl'tion l".-l 1r,J.dc t:\ (~;L ::,;.-.;;.:,,~·-.:~fr :::t;~rt<•;; ·vf""-: -·,,H . . :·,· :::.i-....~:;·t,. f
~ 11,<. n1d inh:11:1nc~ ~tdJ r\:"S'." :-e ~;:<c~. d!' 1-: :\ :--;LO

·Ud

~:tnblc 1>..:· : ::.~ '.

.,. ~-:·r-~

\.1 \OR

··t···~l i"t':-i.'~ ta:.~rh.~: ·

\faiatt'Rllnct- Addr....,.s R.-gi~rer

f"~-t :n:~-i-ii:::;;.:1:~1:1.:.:l• ~tddr"~',;;,

i(~~_iy:,i:r '.,'l:LJ!~u.-.b ~t.\DR :~. ~

h~1s L~ tin.s ;1r;d !";.)cc:v~,, l-H l\· ~- ~-:,,\)t~). ~·:-:.'-1~· . the DP \\.'!-·,~-~~ (~1·1itbk~ th~
-\ll i 3 b'.:l~ ~H('
'..hi:'. irn.u~-~~';'1_~rn\."'.~- ''PU\\ ;r ;";.::-i:1.i b;h~:~
th,~- f)P

"1\·::r tr:.: '.\fb bu~. :\L\.DR J: t~ u.;cd in t-hc· rnt.:.\
\·i.~'.(· to .~tee ;_~1t..' hi;~di
w.:i:j I< ·.'J.c \;ID bus .\i \DR I: is JL"· u~<l ... '.. h·: e's i.•gl'
,;eke! the
;~:;·;~r::1 \A\ ~d t,:o lx~ writltT: fr-._;rt: tht· IB b~~-

\·1i\.DR

4.6.Z 'fk""'"fueoctr l<>gic
lhe mit:·rd·\~.~ue11.\.".cr ht~!c (fin~i.'.B ,,f th~ 24\. l
~~-f~'.-.Jt~~ :iii.~ (\)ntri:.~h ~he ri.ui\)US n1icrosequ~n1..::,::;.e:

~·J"i ~Y~r(,_ ..-~'~-~( r~1irr,··
•)r V•'o\ p._or~''" •Ji ihc

i.-.: ~-~<.'.d :r. ch'-" CS

:-er LS b.:~r:k -;;c_kctH:in

ih(- ~i<),:·;(·-,-K..-x:;-uc.n(~C-r cortr-:"; '.:;:,~1i..: \A·-hi\'.h

i.rild fh('. br:mt-'b ;"·it!i.:·,

4.6.2.1 Z91 I \ficr~-cr -The .2911 mia(>S<.'.yucn<:c.r 1.1utput' :1 ! 2-bi! o.ddre•,; ,•n:;; '.:·r::;n,·.-, ;,ddn.'''
'incs \IADR l. oo: where 11 b nrnxcd with the . 2-bi: .Jutput fo1m the msin1<,nan;;c ;;dJrc.;> '«gi,kr.
F1~tJr-c 4- ~ illu,'"l.r~th..~ the m.ltxlng funt~ti~;n, A.'f~t.:i n(~H:· :h.J.1 the rnicrt'r:t,-quen(.c.r cr1rnpri.~·s lhr('r..'. 2q ' 1.'hips
c;tc.h r>utputi.ing four bits <mto the '.1>\DR lines Thc upp.:r dght bits 1.1n th.: \!ADR 1.inc.s '\t\DR : .04;:
l:x'\:('Jne: :1dctre:,.;; bib CSA \.!I :04). re,p.:cmcl). The l,•1<c.r fllU.r bits (\t\DR \.0:1.CW.l.) ,,~;: ORcd "ith
br.ifll:h !<t> BR ;;OJ:l)ll:' frnm the br:tn<:h wgic in th<: DP I<' pr •.>ducc :1ddre" bits CS\ .U.l:f.•.·;
The lower l:. l:>i.t'i uf the CS micrnword (BUS U:, i l :(~·~;I .:m u,..;d h} tht niin\i;.cqu<'n'cr k• f,<rr:;..IJtc. the
nrx1 Jddres.'. Each chip receives the four bi»: frnm th m1erowurd that (I•rre~pond t<1 i:s lour .1u:puts onl'l'
ihc M.. \DR lin~"'··

Flgu_rc 4-S. i~ a fun~tionaJ block diag,.r.~lm of a 29 ~ l :r~1i('f\.1St.>:qucn ...'.('.T ch;p llic s•. Ur\.·c
th..:'. ;·..-~u~· . b-i! 1.:hip
,iutput .could be .m addre>s registt'.r 1which w1,uld lx the Liu; next :Jddre'» bits from :h.: ·nicrcw•!·d··. ".J ><
..i rncrnon ~tack, or a PC ~\)U.nkr/!.ncr-cn1e·ntt1:L A. ni·tf'( ~k·.~L) the ~·idJn.:s':I ~uuru: ~h.:c:on.f.'.lll
se~e~:r. <x)()c
1,S: ·$()• f~om the micw~equ~ncer. '')ntrol logic
'·
1

The ~n~_mory ~.tack i.~ en.abkd by file enaNe -(Ff'>! tTCe.~1c:d. :·r<irn lh1~ c·-s ~r'Li.:r1__-i\v-C;~-d \;;:_ ~h:. ·;-..:,'" J\HW-C
n:gi~tc-r. The. 5lacl: push/~'f1 control {PUP'l 15 r.~'-'1J- -~~btxlni..·d fr•.:in1 the ml.::.r-.1v.-;:1rd y;_~t the ,. . ~c ...:!w 1:•:d
regl'l~-r.

FORCE ZERO ft\"lm the m·f(·.r::~~thl.1·; s~art-up logic ·negatt:':-: ~:h~ m~cro:-.t:"4U(:nc(·: ;.~u-tp':l! i.::.:t·tL"'~:".',g ~hl'
OC ~:1ll z.cr\)S.

uq: 1 ~~

dw :1;h::~·)'.'1-(1 -q~i:0-,,;..:_:· ;,:--.-_:rt.:r<:;

4.6.2.2 :\Ucrowqumcer Control Logic - Figu.~c .+-G i.> :: block
k~;"'~· BLS C ~ !:6~Ln is the ~'11irro~."Quenccr ~(:rntro.l fic:d r. :_~;r CS
n1.::% t CS ~tddrcs~ 'i~ Ln mul21-,.:d~

Th~ f~c:.id ;,:pt·--'"":Lcs h'>"" :h.::

H SE~~ l '\-TL 4. SEQ C 'TL 3, or SEQ CNTL ~- i5 fa;~:, 1.>)ntroi bits SEQ C7"TL
~.he mu:' ~h:('t Jcg:ic and the :'L!..::~ <.'tL bk fr,_gj(:

.:n.~ ~nh:b_;:~~-j {:·y·,:-;;

I.:i th~~ ;::1~· t:he ~1:ux s.ck·ct '...:_)g;l. outru~ dcl;iu!t~ r.J- S ~ Lil:-;c'.
\\'I c>nd SO true\ l l. and dcc;:.;:kd file enabk t.DFE! :·rcri1 :.he s:,ick cn;ihk !cg>,· is
Tr: ;ou:;t·
~~~~(·k '~>: 1 r1tr(;~ l.Jgic ~cspond~ t<', SEQ (_''.\:TL l :0): hciwcv-~"·- dt<_C,:.x:h:d fH;-~h/pt~_·p DPt
"'
1fic· <rnd: :·•k rnctbie si~n:-.: iDFE! is false
1.'.

IHG

EN MADR

••1

llB IN <12:00>

(FIG. 5.9 ) CLK MADR.

MAINT.
ADDRESS
REGISTER
(Pl

MAOR <07:04>
MADA <11 :08>

CLK

MADA 12

MAOR <07:04>
MAOR<t1:08>
2911

<Sl:SO> 2911

<Sl:SO>

<Sl:SO> 2911

M~RG

FE
M~RG
FE
M~RG
SEQUENCER
PUP
SEQUENCER
PUP
SEQUENCER
(P)
.._...;;,...:..__,(Pl
.._..;...;:;.;._~(P)
BUSU<i1:08>

BUS U<07:04>

(FROM MICROSEOUENCER)
CONTROL

FE
PUP

MICROWORD)
-----1"t(FROM
REGISTER

BUS U<03 :00>

BUSL. <11 :00> (FROM
)
MICROWORD
._IM_A_D_R_<_t_2_:00_>
_ _ _ _ _ _ _ _ _ _ _ _ __,.,., TO MAINTENANCE MUX AND)
\CONTROL STORE

r·

NOTE:
LETTER DESIGNATIONS IN PARENTHESES A'EFER TO THE PB
ENGINEERING DRAWINGS CONTAINING THE CORRESPONDING
LOGIC.
TK-8722

Figure 4-7 Control Store Address Multiplexing

4-14

FIG.
4·2

MADA 11
MADA 10
MADA 09

EN SEQ

(29i1-

I
I
(FIG.

MADA 08

I
PC COUl'I TE R/

i-----t---...,. INCREMENTER

I
4- 2 {- -'-F.;:;.O~RC.,_E: :. ; ZE;:.;R'-"O=- '- t X..,_..__t-_..-+--'-+---'
BUS U<11 :OB>

I
I

NOTE:
THE LOGIC IN THIS FIGURE IS CONTAINED ON
SHEET P OF THF. PB ENGINEERING DRAWINGS.

Figure 4·8

2911 Microsequencer

4·15

CLK

(PC+ 1)

I
I
I
I

i...------1 (V}
t,------t.
J

MISC CNTL ('TO MICROWORD)
REGISTER
FIG. 4-2

....-... {.·TO BRANCH LOGIC 'J
'
\FIG. 4-2
.

BUS
(FIG. 4-21 U<l6: 12 >

SEO CNTL <4:0>

SEO CNTL 4
SEOCNTL 3L-r-SEQ CNTL 2 r--1

MUX

SEO CNTL 1

SELECT
LOGIC

("7"0 MICROSEOdE1'.CER)

<Sl:SO>

FIG. 42

(W)

SEOCNTL 0
STACK
ENABLE
LOGIC

)

IW1

l~- - - 'sr'- :c"'":.: .c" r-:-'-r=-L_<;.;.1"':0; . .>

~~!~·;oP

_______ CONTROL
LOGIC
(WJ

NOTE:
LETIE::: CE.SIG NATIONS IN PARENTHESES REFER TO THE PB ENGINEER IN,:: ::'?AW!NGS CONTAINING THE CORRESPONDING LOGIC.

Figure

•::::;;(isequencer Control l-0gic

4-lo

OFE

Ml.CROWOR;:::)
Iho
REGISTER

\FIG. 4·2

Table 4-3 lists the five SEQ CNTL bits in binJry scqucnc~ and shows how the bit> contrnl the rnri•ms
sequencing function'>. All 32 bit counts (or bit states) arc listed.
The first 28 counts (bit stares) operate the branch h1gic. During the first f<.'ur bit srntc,, branches 3, 2. ! .
and the A portion of branch 0 arc enabled. During the next four bit state'. ,ml~· brunch l ,rnd the/\ portion
of branch 0 arc enabled. For the next dght states. the B porti<JO of bram:h 0 is enabled. The next eight
states find the C portion of branch 0 enabled. The last four bit states of branch logic operation has select
condition code tSEL CC) as.o;erted. SEL CC is actually the D portion of branch 0. The branch logic is
described in Paragraph 4.6.2.3.
Note that during the 28 bit states of branch logic operation. either SEQ CNTL 4. SEQ CNTL 3. or SEQ
CNTL 2 is false, hence the SI and SO control bits from the mux select logic are in the default stale (SI = O;
SO= I) and the DFE signal from the stack enable logic is false. With the control bits in the default state,
the microsequencer mux selects the address register and the microsequencer serves only to couple the micro·
word next address field (BlJS C (I 1:00)) to the MADR (I I :00) common addn..-ss lines as the base addres.~
for branching operations. The stack is disabled by the negated state of DFE during branching operations,
hence. the state of DPUP is meaningless.
During the last four bit states, the SEQ CNTL (4:2) bits arc true» disabling the branch k1gic and causing
the microscquencer to be used as the addressing control. As shown in Figure 4-9. SEQ C"Tl. (I :0) arc n1iw
input to the mux select logic and the stack enable logic. Table 4-3 shows the state of the St.SO control bits
and the stack enabling signal (DFE) for the last four bit states.
The first of the four bit states i;; a (jump to subroutine) JSR function, In this ,1atc SEQ CNTI. (I :0) arc
both 0 hence SI and SO rcm<1in in their default 'late and the addrcs,; register is s1ill selected; however. now
the stack is enabled and DPUP is asserted. DPUP true causes the ''utput of. the PC c,>untcr /incrementer
(PC -t I) tor: pushed onto the stack. The microcode jumf" Ill th.: address of a wbroutinc but saves the
next address (PC + I) to return to the main How aft~r the subrciutine is finished.
The sc.;ond state is a return from subroutine (RTSJ function. In this state the mux >elects the stack for the
next add res.~. The stack is enabled and DPU Pis false which pops the stored address from the stack to the
mu.\. The microcode, returning from a subroutine, uses the address stored on the stack to return to the
main flow.
The third state is a "pop the stack" hou>cdcaning function. In this state the mux select:> the PC counter/
incrcmcntcr for the next address. hence the microcod-: simply advances to the next address in the main
!low. The stack is enabled and DPU P is false which pops the stack •"lf an unwanted .i.ddress. Clca~ing the
st:Kk in this manner is necessary when the microcudc jumps to a subroutin<' and continue!' on from th~
subroutine without re-turning to the main tfow 1·ia an RTS
The fourth state is the MISC CNTL function. Jn this state the mux agJin sl'iects th~ PC c01"1' er 1
im:remcntcr for the next address and the mkrocode advances tc• the next address in the main flow, ~-he
stack is disabled by the negated state of DFE. Th.: MISC CNTL function is the utilization of the nc:..t
address field of the rmcwword fBL:S lJ <11 ·.00)) for one rnicri'lcydc for mi;:,:ellaneous flags and control
functions. In this state. the sequential control bits (SEQ C:l\lTL <·i:O>J ctrc all ls. hence BUS U ( 16: 12) arc
all Is and MISC C"'JTL is Jsscrted (Figure 4-9). \1lSC CNTL gaics 1hc microword next addrc~-. rield (n.iw
carrying the miscclbncou5 fiag.; and controls) into the minoword rcgi:;ter I Paragraph 4.3).*

•

Hit:-;:' and{\ of tt·, n;.-::\t at1dri;;-:-.-, fidd {ASRT h\IL ,mJ ASRT DE,\D~ ,,;i.,; 'Vi'. t.<lti:d Gl:..:dh ~~ \fl SC C\Tf
an.· indirt.'.ct!y ~ated by \1.ISC C!\.Tl X(',1U~ th~: ~\re suh~cqucnily e-~·h·d by }lF \ LD.
- -

4-! 7

f hmc-vc;, the~

Table 4-3 Microsequencer Control Functions

Bit SEQCNTL
State43210

EN
BR

2/3

OA/1

SEL

Microseouencer

~ux

Actaress

Select

Source

Stack
Enable
(Dl"E)

Pop
(DPUP)

Push/

Code
<St:SO)
I
2
3
4

00000
00001
00010
0 0 0 I I

00100
0 0 I 0 I
0 0 I I 0
0 0 I I I

I
~

--1-----1-----1
6
7
8

;-~~~~-;;10
II
12
13
14
15
16
17
18
19
20
21
22
23
24

0
0
0
0
0
0
0

I 0 0 I
I 0 I 0
l 0 I I
I I 0 0
I I 0 I
I I I 0
I I I I

__ .,

·r·
Address

•

---~-r

t----t--- t---1- +-,-I
I 0 0 0 0
I 0 0 0 I
I 0 0 I 0
I 0 0 l l
I 0 l 0 0
I 0 I 0 I
l 0 I I 0
I 0 I I :

2;-7-;-;;-;o_, __ r---+---1-- f--126
27
28

l I 0 0 I
I I 0 I 0
I I 0 I I

---1-----1----1---i---I
29
I I I 0 0

Address
Register

r - - - 1 - - - - - - - - 1 - - - ..,. __
0 I
Address
I
I
Register

I I I 0 I

I l l I 0

Stack

PC CounterI I

Incrcmcnter

I I I i i

I =Asserted
0 =Negated

X = Don't care

4-l 8

PC Counter/ 0
lncrcmenter

Jn describing the 32 Mates of sequential control bits SEQ CNTL \4:0/. four sixcial mkrosc4ucnccr srat..:s
and 28 branch states were discussed. It may have been noticed that thl.'rc appeared lo 'x: no qatc that us1;d
the next address field of the microword unchanged. As will be seen in the section on branc·hing. (Paragraph
4.o.2.3), one of the branching states is a null wherein nc) conditions arc checked. This allows the next
e1ddrcss field to pass h> the CS unchanged.
4.6 ..2.3 Branch togic- Figure 4-10 is a block diagram of the branch logic. Four brcinch bits (BR (3:0))
are generated by the branch logic to nwdify the bm.e address from the 2911 micro,cquencer. Brnnch bits
BR {3:1) each have a niux for selecting the various conditions affe.::ting that branch. Branch bit AR 0 has
four muxcs to select its bran<'h conditions.

The branch mux~'5 arc controlled by sequential control bits SEQ C'-/TL (4:0}. The muxcs funeti0n during
28 of the 32 bit slatl!s of SEQ CNTL (4:0) as shown in Table 4-3: however. not al! the mu.xc<. arc enabled
during all or these states. When a branch mux is not enabled. the ::isso.:iated <iddrc;.sing bit is dctcrmin~d by
the corresponding bit from the microsequcnccr.
Control bits SEQ CNTL (4:3) arc applied to the branch 0 mux sckct logic. The control bll> ~ire decoded tn
assert one of four outputs to enable one of the branch 0 muxcs. The control bits divide the .l2 bit stat.es into
groups of eight. Table 4-3 illustrates this and alsc1 shows the state of the four outputs from the bram·h 0
mux select logic for the eight-bit groul'S.

E' 1\ BR OA/ I enables the branch l mux and the A mux of branch (l It is asserted for the eight bit state~
that SEQ CNTL (4:3) are false.
EN BR OA/ I is ANDed with the negated state of SEQ CNTL .2 to assert EN BR 2/3. EN BR 2/l
enables the branch 2 mux and the branch 3 mu.x. Maling EN BR 2/3 a funnicm of SEQ CNTL 2 limits
the enabled state of the branch l mu:-. and the branch 3 mux to ,,nly four bit stairs.

El\ BR OB enables the B mux of branch 0 for the eight bit states that SEQ CNTl <4:3:) arc 0 and 1,
respectively.
EN BR OC enables the C mux of branch 0 for the eight bit swes that SEQ C\TL {4:3} arc I and O.
respectively.
The fourth output from 1.he branch 0 mux scle.:t logic is a>scrted by the I: l state of SEQ C'\TL (4:3). It is
ANDed with the negated state of SEQ CNTL 2 to produce SEL CC. SH. CC selects the bran,:h conditions Ill" the branch 0 "o·· mux. ~faking SEL CC a function of SEQ C'iTl_ 2 limits the asserted stat<~ of
SEL CC to only four bit states.
Table -<-4 list:; the branching conditions for the 32 bit state,; of SEQ C\TL \4:0). Refer to it durir.g 1hc
following discus:;ion of the branch muxcs. When a condition is s::impled b\ the branch logic. the corresponding bit from the microsequem::cr is always 0.
The branch 3 mux. io; enabled for the first four bit states. The rnux :;ekct.s IB JN I9 when SEQ CNTL (I :0}
.1rc in the l: I state. The mux sc.kcts 0 {ground) for the other 1.hm: >1atcs of SEQ C'\ TL / l :O!. The mux
output routes to the branch output register and then to ;he BR 3 output !inc.
Th<~ branch 2 mux is also enabled for the fiN four bit states. The mux selects one of four condition rnrut>
as determined by SEQ CNTL i I :0). The BUS ERR c1mdition (ncg:it.:dt" selected l•.Jr b<Jlh the 0:0 and the
O:l states of SEQ C!'<TL (I :0). The mux output is placco on the BR 2 output lint'. 1i:t th« bratKh output
reg1~ter.

The branch J rnux is enabled for Lhc first eight bit states. The n1u' ~k\..'ts i:-mt: c,f t.;iv:h;. ,:r_~.ndition .input~ a,;;
d~knnincd by SEQ CNTL (2:0). The mux ~1urput is placed on the BR l ompur l:n·:~·
riic branch ou!plll
rcgl:i!CL

IB IN 19

(

. FIG.)SEO CNTL <4:0>
4-2

BUS ERR

(FIG. 6·2)

{FIG. 6 _11 ) ---+-A_C_L_O_FA_l_L_ _ _ ,
IB IN lB

SEO CNTL <1 :O>
SEQ CNTL <2:0>

IFIG. 6·2)

SEQCNTL 2

~--.......~~f--+---------w

EN BR 2/3

SEQ CNTL <4:3>

(FIG. 5·12)

EN BR OA/1
BRANCH

EN BR OB

EN BR OC

MUX
SELECT

SELCC

AON
BON
TICK<l>
IB IN 17
IB IN 26
IB IN 14
IB IN 10
IB IN 26

(BRANCH 3)
BRANCH
OUTPUT
REGISTER

(BRANCH 2)
!BRANCH 1)
{BRANCH 0)

BR 3

}(~)

BR 2
BR 1
BRO

LOAD
SEO CNTL <1 :O>

CLK
CLR

'CJ I
{FIG. 5-2)

__j

IB IN 25
IB IN 13
IB IN09
IB IN 22

UNINIT
T40
EXECUTE

IB IN 31
IB IN 15
IB IN 12
IB IN 24

SEOCNTL 2
SEOCNTL.3

>-(;....E_N_B_R_O_D..;..)__....,. D

~IB;;-,..,IN~00::;..,;..------1---_..aRANCH

IB IN 20
RSVOJMPR
RSVD

SEO CNT...::;L;..;4'----'

{FIG. 5-9)

REG WRT

BACKPLANE---------+---0-l~SA-...-.BL_E-.;...;A~R-"-IB
{FIG. 5-12)
{FIG. 3-9)
(FIG. 2·27)

BTO
REC ATTN
XMIT ATTENTION
18 IN 21
IB INOB

OB MUX

:~~~
{
( ~-I~)

WALU
ALUC

fflG. 5-12)
{FIG. 5-5)
(FIG. 5-9)

BRANCH
OOMUX

SEL

NOTE:
THE LOGIC IN THIS FIGURE IS CONTAINED ON
SHEET J OF THE DP ENGINEERING DRAWINGS.

Tl< 8731

Figure 4-10 Branch Logic

4-20

Table 4-4 Branch Conditions

SEQCNTL
Bit
State (4:0)

Function

Branch 3

Branch 2

Branch

0
0
0
IB IN 19
0
0
0
0
0
0

ADN
BUS ERR
BUS ERR
BDN
ACLO FAIL TICK \l}
IB ll'i 18
IB IN 26
IBIS 17
0
IB JN 14
0
0
IB IN 10
0
IB IN 26
0
0
0
0

()
()

()

0
0
0
0
0
0
0
0

0
0

0
0
0
0
0
0

2
3
4
5
6

7
8

9
lO
JI

12
B
14
15
16
17
18

19
20
21
22
23
24
25
26
27

28
29
30
31

00000
00001
00010
00011
00100

00101
00110
00111
01000
01001
01010

01011
01100
01101
Oll 10
0111 l
10000
100)1
10010

!0011
10100
JOIOI
10110
10111
11000
11001

()

I 10!0
I IOI I

11100
I 1101
11110
11111

JSR
RTS

0
0
0
0
0
0
0
0
()

POP STACK 0
MISCCNTL 0

Branch I

Branch 0

0
0
0
0

(l
(l

ALUC
\LUC
\HD
lB IN 16
lB IN 25
IB IN 13
iBIN 09
lB IN 22
IBJN 31
.IB!Nl5
!BIN 12
!BIN 24
lB IN 00
IBIN 20
RSVDJMPR
RSVD
REGWRT
DISABLE ARB
BTO
REC AITN
XMIT ATTENTION
IB IN 21
IB IN 08

()

0
0
0
0

0
0

.!\LU N
ALUC

{)

ALli V

0
0

0
()

0
0
0
0

0
0
0

()
()
()

ALUZ
()
(}

fhc A, B. and C mux of branch 0 have their outputs connected to a common output. line. Mux A is enabkd
for the first group of eight bit stat<:.» mux. B for the second group. and mux C for the third group. The
cnc1bled mux seie.::ts one of eight condit.ion inputs as determined by SFQ CNTL {2:0/. Thus, the rnmmon
mux output fine recei\es a branch condition for the first 24 bit states.

Note that one of the branch condition inputs of rnux C is 0 (ground). When this condition is selected (bit
state 14 )~ there are no branch conditions and the next addrcs...' fn._)m t.he ~911 inicros.:qu~ncer is applied hJ
th.: CS unrhanged.

The branch condition on the common output. line.: is appli~J lo the four k.>w order inputs of the bran<'h 0
'"D" mux. The three select. bits for the D rnux Jrc SH. CC a.ad SEQ \l:O;> \\ith SEL CC being the most
significant biL SEL CC is false for the first 24 bit slates nabk 4-J) hence che mux selects only from the
four low order inputs. Thus. for the first 24 bit states, the D mux simply couples the selected branch condition from the common line to the BR 0 output line via the branch output register. SEL CC is true for the
next four bit states (stale> 25 through 28). causing SEQ Cl\iTL (I :0> to select from thi: four high order
inputs (ALU fun.:tions)
Branch 0 is active for all 28 bit :·tatcs of bran,\ llperat.ion,. AIS<' it can be >een that the branch D mux is
enabled for all 28 states. It is disabled during s• ..::s 29 through 32 (SEQ C"ITL \4:2) all ls) when the
microscquencer special functions arc enabled.
4.7 MICROCODE START-t'P
The twll CS address sources (the maintenance address register and the microscqucncer) are enabled from
the mi.;rocodc start-up logic, EN MADR enables the maintenance address register during the uninitialized
state. When the initiali7.ation process is tomplcte, EN MADR negates and EN SEQ asserts. EN SEQ
enables the microsequen.:er which supplies the CS address during the initialited state.

Figure 4-1 I is a flow diagram of the microcode start-up proces.'>. The following discussion follows the
sequence illustrated in the diagram. Figure 4-12 is a block diagram of the logic involved in the start-up
proces.,.
Upon system start-up., UN!NIT asserts on the DP and places the port into the uninitialized state. When
UNJNIT a>Serb, E:\ MADR as.o;crl' to the maintenance addrcs.'> register and EN SEQ is negated. Also
FORCE ZERO is asserted tll the m1crosequenccr in prcparatilln for when the microscquenccr will take
over the addressing function. In addition. UNINIT asserts SUSPEND CLK. inhibiting the microsequcncer
clock (SEQ CLK TJJ.
When initiali1.ation is completed, the DP negates UNlNIT and the port goes frum the uninitialized to the
initialized state. The negation llf UNI NIT negates SUSPEND CLK thereby enabling SEQ CLK T3 io the
FORCE ZERO flip-flop and to the micrOS<'\juencer.
The CS address source for the fir;t microcycle llf the initialiwi state may not be the microi.equencer
depending on the state of the programmable starting address\ PSA) bit in the p(lrt maintcnante control/
status register (PMCSRl. During a normal start-up, PSA = 0 In this case, the negation of liNI NIT directly negates EN MADR which in turn directly a::serts EN SEQ. The enabled microscquencer then responds
to the true state of FORCE ZERO and outputs a starting address of 0 to the CS. The next SEQ CLK T3
pulse resets the FORCE ZERO flip-flop allowing the microsequenccr to re;pond to the microcode in the
CS.

If. while in the uninitialized state, it is determined that a d1agm)5tic routine should be run, the PSA bit is set
to l. With PSA = I, the negation of UNINIT docs not c:rusc E~ MADR to negate (and thus EN SEQ to
as..o;crt) until the next DP CLK T3 r,.ilsc rescts the enable tlip- !lop. Thus, for the first microcycle of the
initialized state, the maintenance address register still provides the CS address. The addm,s provided would
be the starting address of the desired diagnostic routine.
When the DP CLK T3 pulse ('ICcurs. EN ~1ADR negates. EN SEQ asserts and the CS addn:ss source
shifts from the maintcn:incc addr:ss register to the microscquenccr. Th.: sJme DP CLK T3 pulse resets the
FORCE ZERO tlip.llop to allow the microsequcncer to respond t1:. the next <lddress field of the fiN micro·
word of the diagnostic routine.

Start

t UNINl1
Port enters the
uc:nitialized state.

t EN MADR
Maintenance address
register enal1led.
Register provides
addresse!> to control

• EN MADR
Disable maintenancu
address register.

store.
SUSPEND CLK
SEO CLK T3 is
inhibited.

t .:N SEO
which outputs zero as

Fi"t address in the
initial11ed state ob·
tained from the main-

first address ln the
initialized state.

Enable m1crosequencer

tenance ar1dress

t FORCE ZERO
M icrosequencer yene·
rates zero address,
however, outpu1: is
not enabled.

DP CLK T3
SEO CLK T3

t FORCE ZERO
Microsequencer gene··
rates addn~s:ses under
control of microseq·
uencer control logic.
T

!
YES

DP CLK T3
SEOCLK T3

l EN MADH
Disable rnaintenancr
dddress reqister.

t EN SEO
Enaole microsequcocer.

t FORCE ZERO
Microsequencer 9ene·

rates addr-esses under
control of rnlcrosc·
quencer control logic .

• UNINIT
Port enters the
initiali7i~d state.

SUSPEND CLK
SEO CLK T3 i;
enabled.

TK~i ;~·,

F!gurc 4- l I

Micrncodc Start-Uio F1ow Diagram

I FROM '
I PMCSR
\FIG. 52

PSA

IFiG. 5-121---1

EN MADR

EN SEQ

UNINIT

l( ~'~-)
I .·

lJNINIT

FORCE ZERO

SUSPEND CLK

-=
SEQCLK T3

DP CLK T3 A

\ f3
(.FROM
SBI MODULE,--""'--!
'

POAT CLK T3

NOTES:

'1.

LETTER DESIGNATIONS IN PARENTHESES REFER TO THE DP
ENGINEERING DRAWINGS CONTAINING THE CORRESPONDING
LOGIC.

LOCATED ON SHEET W OF PB ENGINEERING DRAl'1 1NGS.

Microcode Start-Up Logic

"NOTE
2
CLK

(FIG_ 48; 43i

DP CLK T3

figure 4· l 2

l
J

Figure 4· ! 3 is a timing diagram of lhc micrc..:ock start·up. Figure 4· I 3A illuslrnt.:.s lb(~ start·up timing
when t.he PSA bit = 0. Figure 4-1.JB illustrates the start-up timing whc11 th<: PSA bit " l. Note that the
difference between the two t.iming sequences is the point at which EN MAl>R negat1,'"$ I.and EN SEQ
asserts) and what causes it to negate.
4.8 CLOCKS

Figure 4-12 illustrates the generati.on of the DP clocks. The DP clock~ I DP ( LK T3. DP CLK "f.l,\, irnd
PORT CLK T3) are all derived from T3 as shown in the figure. The time period for 1.be clock~ is 200 ns

(see Figure 4·13).
SEQ CLK T3 is also derived from T3; however. it is subject to the negatt-rl state of SUSPEND CUC

OP CLK i3
PSA

::::DCLK-·~·------f';
FORCE ZERO

__.__I

•

EN MA.OR

SE0CLKT3

EN SEO

A. f'SA ~ 0

OPClK T3
PSA
UNINIT
SUSPENDCLK

FORCE ZERO

EN MADA
EN SEO

;

SEOCLK T,l
8, PSA

• SET DURING UNH~!T!ALl:ZEO STATE

Figure 4-13 Microcode Start-Up Ti;i1ing. Diagram

SEE NEXT FRll.ME

FOR LARGER ART

4-25

i----- ·.:·:)'~ ~·;~ _ ____,

--lsoNof-PSA

_ _ _; ]-'_\......--~~
1

(t==:J

i)P CU( T3

PSA

~-----------------------------------(

SVSPE"D CcK
FORCE ZEP.C

. , . t ..~

rt+·
I

: ~....___'_l?f_~
r \
l

U'<l'ilT

~L_

;

)

CHAPTERS
DATA PATH MODULE

1'/0T[
fhe functional block diagrams in Chapter 5 use logical AND and OR symbols. It does not necessaril}
follow that a correspunding gate exists on the DP
logic prints. The assertion of inputs A and B causing
the assertion of oulput C may be represen1eJ on a
block diagram by a single AND gate, yet the enginttring drawing may show that several circuit sta11es
are involved in the ANDing operation.
The functional block diagrams in this cba1>1er are
keyed to the DP engineering circuit schematics (C'S
prints) by letter designations in parentheses. The kt·
ters specify the DP CS s&:eet that i:ootains the
detailed logic associated with the functional blocks
in the diagram.

1 he signal names used in the f11114:tional block diagrams are the names ~ oo the engine..!ring CS
prints. Where other signal names or notes ar~ used,
they are enclosed in parentheses.

5.t OVERVIEW
figure 5·l is a block diagram of the data path module,, Operation or the DP is under microword control
except during an unsolicitc" 3BI request operation. The microword fields control the flow of data through
the DP, selecting the M>Urce of data for the BUS IB when outputting from the DP into the SBI module, and
selecting the destination for the BUS JB data when receiving data from the SBI module. Possible sources
for the BUS IB data are the local store (LS) RAMs, the virtual circuit descriptor table (VCDT) RAMs, the
::!90lA microprocessor. or the miscelianeous data (BUS MD), Possible sources for the BUS MD data arc
the PB IN register, the microword fr;)m the control stori: (CS), the port maintenance control/status register (PMCSR). or the mkroword literal field,
An unsolicited SBl request is a read o; a write of a DP location, IMt is not con1r.11led by the microword.
The request sequence is initia11•d from the host via the SB! module and controlled via the R 8(09:00) inptH
lines from the SB! module.
The microword IB DST field and IB SRC field selcci 1hc BUS IB destination and source. rcsJ¥.:<.:tivdy.

When the IB DST field and the IB SRC field sck<.'t the PB OUT regi;.tcr and the PB IN register as •ht•
BUS IB destination and BUS lB 1-0urec, respectively, the DP is fun1.ctwning to transfer data packet,;
between the PB a11d the SBI module. The data undergoes form;it conversion within the DP. Longwords
received from the SB! module arc applied to the BUS IB bm. and then to the IB IN bu' l'ia a hitch. From
the IB IN bus the l<>ngword is lo;1c:d in1o a PB OUT register which then unloads a byte at a tirnl' onto th~
PORT DATA bus.

{

IB SRC

ADDRESS

PARITY
GEN/

SELECTION
LOGIC

CHECKER

.----------(TO CS)

t---.i.......,..-...--.;.;....&..4~

..--....i...--. ALU DST
2901A

ALU~ } FROM\
1

µPROCESSOR ALU FCN

PORT
<15:00>

,CS

"---.----'

PB
OUT
REG

DATA
PMCSR

LITERAL <-7:0>

<7:0>

(~~/FROM)

(FROM CS)

(FROM CS)
BUS MD <31:00>

.FROM
(

~~DULE

')f

RB <Og:OO>

UNSOLICITED

µP WOIP
SBI
....:.:.µP_;,;.R.;:..D;.;.IP_ __.,. ,REQUEST

LOGIC

Figure 5. I

Data Path Block Diagram

CONTROL

EN PB IN

LOGIC

1:,·tm PB l" '.'~g1,1u. When f•,wr
Byte' r•~•:<:i1cd lrom the PB 1m the PORT DXL\ bu,s .u.: appli,i:J
byt~ are l<><ld<,J into the register. the register ,1ut.put i> co;iblt'>d Wll•' 1'.<· B\ ''." \11) bu:' b; IN PB IN i'nmi
the DP c011trnl logic. The d.ita longw,)rd ;,, tr"n,fcm:·d fwm th~ IH. 1S \~D btis tc• the l!l.'S lB bu,!:>~· E:-..

MD 1.0/HI (al"<' from the control logic) and then sent I\) the SBI moduk
Tile DPc,mtainsa ZS6 >< .12 LS RAM area and a :~6 ><. 16 VCDT RAM .;1~c;1. The IS.:<1 n1;1in~:.<1ltwaT\'
status bl,Jds and many &oft ware registers ;1S>OCmted with the p<lrt architc:•·tun: Th< \'CDT i> used tci store
Cl node parameters. The LS or VCDT can be selected i1s a BUS IB s.:•urce fre~1d the RA'\h) ,,r a BCS lB
destination (write the RAMs via the IB 1;-.; bus) Th< U'i and VCDT ;Uc addressed in paralkl fr,nn the
add, ~·ss se1'ecuoa logic. The add res~ source may be the 18 ' ' bus data .. the lB J:-.. bu; daw 1ran\lated. or the
m1m11»ord literal field. If the l.S/VCDT is the Bt1S IB source, the microword lll SRC field xk<:ts thC'
LSiVCDT addrtss. If the LS/VCDT is the BUS 18 destlaaikin. the microword IB DST field sdech the
l.S/VCDT address.

In an unMJhcited SBI request sequence. the microc(ld¢. is ,uspcndcd and the host "rites or rc;ids a sclcctl'<:l
DP locJtion as specified by the R 8{09:00) inpul~. H the LS or \'CDT R -\\hare ~lec1cd. the R 8{09:00l
control lines supply the LS/VCDT addres.~ io the L,SiVCDT ~1ddr~"' .election l1>gk
The DP con.trol logic receives both the source and the destination c<mtr,11 fields from the microword. It
dec«1des the control fields to detc~mine if a BUS lB S<mrcc: or Bl'S IB desl.tn.ilt"n ''being >pe1.·ified, and
what source (or destiaatio11) ha~ been .selected. The logic then generate> th.: required enabling signab for
th\.' selected area, and the required gating signals h\ connect that .irea to the Bl!S IB.
A parity generator /chec.ker is connected to the lB I ;'lo: bus and doe,, all the parity generaiing and check.ing
for the DP. The BUS IS bus l$ eonnecte4 to the IB IN bus through a latch v.h1ch makes the BLS IB daH
available to the parity logic. Byte parily is generated and checked on data for the PB intcrf,1ce. wclrd punt~
is generated and checked on data in the Ui and the\ CDT. and longword p;1ri1y is generated and checked
on data at the SBI modul.e interface.
·
The DP contains a 2901 t\ mic•opro~. .essor which perform~ general purpose arithmetic and logical '1per·
atioos under control of the microword ALU control field; The 290 IA can be a BLS IB source or a BUS IB
destination. The functio11 performed by the 2901 A is specified by 1he ALl FC'< field from the
microword

5.2 DP Bl SES A~D PB INTERFACE
Figure 5-2 is a block diagram of the DP buses and the PB tniaface Data t.ramferring between the: SHI
module and the PB is in two different formats. Data at the DP/SBI modul.e int.eda.:e i~ in 32·bit longword
format. Data at the DP/PB interface 1s in eight-bit byte formal. L,1ngword·to·b~ le J.nd byte·tn-longword
conversion ocqurs at the DP/PB interface.

5.2.1 OP·to-PB J11terf11ce
Data from the SB! module inputs a..~ BUS IB (31.00) in.fl) a transparent latch. The latch output foll""'' the
latch input so long as the: latch HOLD input (LATCH IB) i·, true. The latch output OB 11' 01.00)J j,; then
applied in eight-bit byte; to four sections of the PB OUT rcgi~ter . The J~·bit longword is docked into the
register by CLK PB OLT which is a&'ierted by the LO PB Ol'T C<lmmand frnm the DP controi logk. LD
PB OUT is asscrt.~d when the PB OUT register is seleeied a.' the BUS lB dc\'ination.
The PB OCT register ii; un.loaded b5 the PB. .\ PB LOAD Cl)mmand .i.nd '' P'\fl.' \ (l.O} code from 1hc PB
control the data !low from the PB OUT register to the PORT D.\ TA bu:-. The PB LO;\ D comm.i.nd
enable> the PB out byte select kigic while !he P\fUX ~ i \!' <:<Ide .is.sern one or 1he fr•ur E i'- PB BYTE
output sitznals. The PMUX. (LO) .:ode a."-ert,; the four E~ PB BYTE \3:0.' signal,; in :'l'XJ.U.Onn: to unh.>ad
lhc PB OUT register or.to the PORT DAT'\ bus a byll.' ~t '"lime . .\f\cr the Ll't byte ha: hecn u.nload\.'d.
I .D PB OLT is again asserted by the DP contrnl logic w l1>ad the nc:xt lon~w~1rd intn the t·'1J QI r rcf!ister.

~---•"'(FIG. 5·11)

(FIG. 4 - 2 ) - - - - - - .
(FIG. 4·12)-----,
(F!G. 4-10)----.
PMUX <1:0>
(FIG. 4·2)-----'---'-'"""

UNINIT (FtG. 5-12)
MIE

(FIG. 3 _ 6 )....;P.;.;B;...L;...O;...A.;.;O~-.....
MLDPB
(FIG. 5·10)1----r--C....-""'

SET 0
FF

PSA

IB IN <13:00>

IB IN
<23:16>

IB IN
IB IN 00
<15:08>
(FIG. 5-9)-.----------.i,_,;...;.;..._ _t...-i
IB IN <02:00',.>
IB IN <06:04>

IB IN 02

(M)

l\i!IN

PS DC LO (FIG.6-11)

_.M_iF--(FIG. 6-9)-.---.

(FIG. 5-11)

IBIN
<06:04>
BUS MD
<07:00>

LITERAL <07:00>

CSPE

r(FIG. 4-2)

OPE

XMIT STATUS 7

(FIG. 6-2:/1.------~
6·6l , ,.......
B_us_1s••<_3_1_:00_>.....,,_....

XBUF PE
( FIG.)

3·2

BUS MO
<15:08>

IB IN
<01:00>
Cl.K
__,_P_M_c_sR_ _ (FIG. 5-9)

' - - - - - - ( F I G . 6-11)
MTO
(FIG. 5·12)

SET

(Fl
CLR

(FLOW
THRU)
BUS MO

,,.....,._e_x_E_c_u_T_E_ _ 1F1G. 5_9)

....._....l.__u_N_IN_l_T_ _ _ (FIG. 5·12)
BUS MD
<30:16>

<15:00>

BUS MD 31

ENMO LO
(FIG. 5·K'

{

!!f MO HI

...._ ___ _..-.,L-..;.X.;.;B.;.;U..;.S..;.R""O_R_E_C_ _} (FIG. 5- 9 )

BUS MD
<31:00>
PBIN
BYTE

BUS IB <31: 16>

BUS MD

.---"'M..:.TE;;;...._ _ _ (FIG. 5-11)
PSR

----...-.J

,,,--,.-+-1 SELECT
l'H

BUS MD

L---------E_N_M_1_sc
_ _ (FIG. 5-10)

<31:16>

...___E_N_P_B_IN--(FIG. 5-101

NOTE:
LETTER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
TK·88S8

Figure 5-2 DP Buses and PB Interface

5-4

5.2.2 PB-to-DP Interface
Input data bytes rrom the PB (PORT DA TA (7:0)) arc applied to a transparent latch. The latch tiu•put
follows the latch input so long as the latch HOLD input (LATCH IB) is true. The latch output byte is then
applied to four sections of the 32-bil PB IN register.
The PB IN register is loaded by the PB. A PB MUX ENA command and a PMUX (I :0) code from the PB
control the data flow from the PORT DATA bus to the PB IN register (via the transparent latch). The PB
MUX ENA command enables the PB in byte select logic while the PMUX ( l :0) code asserts one of the
four CLK PB IN output signals to clock a data byte into the PB IN register. The PMUX (I :0) code asserts
the four CLK PB IN signals in sequer.ce to load the PB IN register fom, the PORT DA TA bus a byte at a
time. After the last byte has been loaded. EN PBJN is asserted by t!'.e DP control logic to gate the 32-bit
register output onto the BUS MD as BUS MD (31 :00}. EN PB IN i~, asserted when the PB IN register is
selected as the BUS IB source. EN PB IN then negates while PB MUX ENA asserts to start loading new
data bytes into the PB IN register.

The BUS MD bus is gated to the BUS IB in two sections. The lower 16 bits arc gated by EN MD LO while
the upper 16 bits are gated by EN MD HI. The BUS MD bus also receives a 32-bit input from the CS in
the PB.
5.:L.3 LITERAL/PMCSR Mux
A third source for the BUS MD is the LITERAL/PMCSR mux. When the port is in the uninitialized &late
(UNINIT true) or executing an unsolicited SBl request (EXECUTE true), the mux selects the 16-bit
PMCSR register. An unsolicited SB! write request of the PMCSR will assert CLK PMCSR which writes
six PMCSR bits (MIE. MIN,PSA, MTD, WP, RSVD). The PMCSR register bits. are described in Table
5·1

When not in the uninitialized staie and not executing an unsolicited SBI request (EXECUTE and UNINIT
false), the LITERAL/PMCSR mux selects LITERAL (7:0) for the lower eight bits of the BUS MD bus.
The next e,ght bits (BUS MD (15:08)) are grounded.
BUS MD 31 receives the maintenance error (MTE) bit during an unsolicited SBJ read request of the port
status register (PSR). XBUS RD REC asserts during an unsolicited SBI read request and is ANDed with
PSR and MTE to generate bit 31 for the BUS MD.
The UTERALJPMCSR mux output is gated 10 the BUS MD bus by EN MISC from the DP control
logic. EN MISC assert.~ when the DP control logic selects the LITERAL as the BliS lB data source, and
during an unsolicited SB! request when the i'MCSR is to be read.

5-5

Table 5-J

PMCSR Bits

Bit

Mnemonic

Dt-ocription

Parity Error: PE is the OR of PMCSR bits (14:08). It
is cleared when PMCSR (14:08} are ail cleared.

CSPE

Control Store Parity Error: CSPE sets when a parity
error is detected in the CS in the PB. CSPE can only
be set when the microcode is running.

LSPE

Local Store Parity Error: LSPE sets when a parity
error is detected while reading the LS or the VCDT.
LSPE can only be set by a microcode read of LS or the
VCDT. It will not set during an unsolicited SB!
request.

RBPE

Receive Buffer Parity Error: Set when a parity error is
detected while reading a packet buffer.

XMITSTATUS 7

Transmit Data Parity Error: Set when a parity error is
detected in •he link transmit channel.

!PE

Input Par:ty Error: Set when a parity error is detected
on a data transfer from the SBI module to the DP.

OPE

Output Parity Error: Set when a parity error is detected on a data transfer from the output buffer to the
transceivers within the SBI module.

XBUFPE

Transmit Buffer Parity Error: Set when a parity error
is de:ected while the PB is unloading a transmit buffer.

UNINIT

Uninitialized State: When set the port is in the uninitialized state. The microcode is not running and the
port will not respond to data packet traffic. lJNINIT is
set by DEAD, MIN, or MTE. The microcode is started when UNINIT is cleared by writing a I into the
PICR, or bj a boot timeout.

PSA

Programmable Startirg Address: When set the microt:od.e will start at the addres.' in the MADR register in
the PB when a "l" is written into the PICR or a boot
time-out occurs. When reset the microcode start' at
location 000.

RSVO

Not used.

Wrong Parity: When set the DP parity generator/
checker will generate and check even parity instead of
odd. Used to g1!neratc. parity errors for maintenance
purposes.

5-6

Table 5-1 PMCSR Bits (Cool)
Bit

MDelllOllic

Description

Mlf

Maintenance lnte;rupt Flag: Wht~n set. this bit indicates that an interrupt-causing condition has occurred.

MIE

Maintenance Interrupt Enable: When set interrupts
are enabled. This bit is set by PS DC LO from the SBI
module. or by writing MIE with a"!".

MTD

Maintenance Timer Disable: When set, the boot and
maintenance timers are disabled and cannot cause an '
interrupt. When reset the timers arc enabled.

MIN

Maintenance Initialize: When set, an initialize sigual is
generated that clears all port errors and leaves the port
in the uninitialized state.

5.3 lS/VCDT
LS (local store) consists of eight 250 X 4 RAMs addressed in. parallel to form a 32-bit output. The total LS
space (256 X 32) is enabled in two 16-bit segments forming a 256 X 16 LS HI section and a 256 X 16 LS
LO section.
The virtual circuit descriptor table (VCDT) consists of four 256 X 4 RAMs addressed in parallel to form a
16-bit output. One signal enables the total VCDT space.

Figure 5-3 illustrates the LS and VCDT space and the addressing and enabling signals associated with each.
All three areas (LS HI, l.S LO, VCDT) are addressed in parallel by LSA (07:00) from the LSA mux. Thus,
a~ is to the same location in each area.
Data placed into the LS and VCDT is from the IB JN bus. lB IN i"3 I :16) is input i.nto the LS Hl area. IB
IN (15:00) is input into the LS LO area and the VCDT.
Data out of the LS a.nd VCDT is placed onto the BUS 18. The LS HI section outputs onto BUS 18 (3 l :.16).
The LS LO section and the VCDT output onto BUS lB (! 5:00}.
Sections LS LO. LS HI, and the VCDT are enabled by E!'f LS LO, EN LS HL and EN VCDT, respectively. The enabling signal for any area must be true before data can be written into <)r read out of that area. l.n
addition, to write data into an enabled area, WR RAM must be true. To read data out of an enabledll!ea,

EN lS/VCDT must be true and WR RAM must be faL-e (asllertion of the WR RAM write strobe inhibits
the RAM output).

5-7

BUS 18 <31:00>

BUS IB <15:00>

BUSIB<31:16>

LS - HI
(256 16)
(0)

LS - LO
(256 16)
{C)

LSA <07:tl0>

(FIG. 5-5)-----+---+---11"1 ADR - - - t - - - - - - - + - - - A D R (

VCOT
(256 16)

(Cl

--+-------+--..._ ADR

'F•G.) EN LS LO

5-10

IB IN

<31:16>
(FIG.

5-2)---------------------------------------'
IB IN <15:00>

IB IN <31:00>

NOTE:
LEITER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
TK-8860

Figure 5-3

LS/VCDT Block Diagr.im

5-8

5.3.1

l..S/VCDT Address Selection

Figure 5-4 is a simplified block diagram of the lS/VCOT address selection fum.:ti<ln. The LS 'ind \/CDT
addr~"SS (lSA (07:00)) is obtained from an LSA mux which functions to select the addrcs,; from four possible .,;ourccs. Addrcs.\ source decode J,,gic monitors the IB DST and IB SRC fields from the microword to
determine if the LS/VCDT is to be a BUS lB destination or a possible BL:s IB source. Accordingly. the
address source decode logic decodes the IB DST field or the IB SRC field to effect mu;; selection of the
LS/VCDT addrcso source. When the logic senses that the LS/VCDT has been selected as the bus IB destination. it ;;s.\Crts EN RAM WR to the write strobe logic. The write ~trobe lvgic generates the write ;.trobe
(WR RAM) for the L'>/VCDT RAMs.

LITERAL <07:00>

r ..-_1B_IN_~_,o_s_:OO_~_·,__.."

:__
1

LDINDEX

LSA <07:00>

INDEX
REG
LSA

(FIG 5-51 ~
I

I
!

MUX

IB IN <13:09>
LD XLATE

TRANSLATE
REG

1~~~~~~~~~-111o1._~~~__,

XBUS LSA <07:00>

i~~~-IB~D.s_T~·~_·3_:o_>~~"iPf

!bSRC<1:0>

L
~}(FIG.
!

ADDRESS
SOURCE
DECODE
LOGIC

SELECT

WRITE
WR RAM
- - - - STROBE i - - - - - '
El'. RAM WR
LOGIC

Figure 5-4 LS/VCDT Addr.:ss Selection Simplified Block Diagram

5-9

5-5)

Figure 5-5 is <1 detailed block diagram of the LS/VCDT <iddrcss selection function. A two-bit input to the
two mux SEL pins (SEL 2, SEL 1) select the address sour.:c. Table 5-2 lists the address source selected by
the mux for the four states of SEL 2 and SEL I.
The SEL 2 and SEL 1 inputs .ire obtained from two flip-flops. Both flip-flops are directly set by UNJNIT
when tfie port goes into the uninitialized state, thereby forcing SEL 2 and SEL I true. With SEL 2 and
SEL ' both true, the mux selects XBUS LSA (07:00) as the LS/VCDT address. The assertion of
SUSt'END during an unsolicited SBI request also forces the LSA mux to select XBUS LSA (07:00).
Thus. during the uninitialized state and during an unsolicited SBI request when microcode control of the
LSA address mux is suspended, the LS/VCDT address is supplied from the host via the SB! module and
the XBUS LSA address lines.

{FIG. 4-~i

18 !N <08:00>

(FIG. 5·2)

ILSA FSA
<07·00> /.'.!G_\
tf>)
\ 53 l

(FIG. 5· 10)

\f-IG_ 4-21

I MUX

~:: ~: -~~'.:

.._i~SE_:L_<_.i-<><SEL 2

tB DST 3

lB OST 2

!Pl

.._.1s_t_L_>'-1-..istl 1

or cu"'

NOTL
LETTfR Dts;GNAT!ON'S !N PARENiHE.."iES
RfFEA TO f:NGi!\IH_R!NG DR,AWJNGS
CQNlAINiNG CORRESPQNOINC LOGiC.

Figure 5-:i LS/VCDT Address Selection 13101.J, Diagram

)- l()

F'()R lARGER. ART

LITERAL <07:00>
(FIG 42)

LITERAL 00

(<03:00>i
18 IN <08:00>

~----------...itNDEX

REG

LDINDEX

\P)

DP CLK

LO XLATE

(FIG. 4-2)

DPCLK

{----------'

18 DST<l:O>
{

18 SAC <1:0>

INDEX 08

!FIG. 5· 10)
LITERAL 00

(FIG. 5-21
(FIG 5·10)

1--...------~-----~~

(<05:01>)

TRANSLATE
rlEG

(<07:06>)

(P)

fFIG. 5 9)
UNINIT
!FIG.5-121 - - - - - - - (FIG. 5-9) __s_u_s_P_E_N_D~

-:::-

18 DST 3

r--r.._ __,

!Pl

iFIG. 5·101

(SEL 1)

FF
DP CLK

: 5.9

(.FIG. )' UNINIT
512

NOTE:
LETTER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.

Figure 5-5

I
I

L-

LS/VCDT Address Selection Bloclo. Di,1gram
'-iO

SEL 2

(Pl

(, FIG.)" SUSPEND

<07:00>

DECODE
LOGIC

LSA

X&US LSA <07:00>

(SEL 21
-~---SELECT

l.SA

MUX
(P)

{Pl

SEL 1

.FIG.)
:

"53

Ti1ble 5-2

L"iA Mux Selection Codt'

SEl.2

SEL 1

Address Source

()

0
I
I

Literal
I ndcx Register
Translate Rc.gistcr
XBUS LSA Register

0
I

When not in the uninitialized state (UNINIT false) and when not executing an unsolicited SBI request
(SUSPEND false), the select decode logk controls the two SEL bits by i.:onditioning the two SEL flip-llops
to set or reset. The decode logic rnuses both the flip-flops lo reset. or one or the other to be set, thereby
causing the LSA mux lo select the LITERA~., the index register, or the translate register as the LSA
address source. The decode logic will not cause both flip-flops to set and hence will never select the XB!JS
I .SA input as the LSA address source.

The decode logic operates from a two-bit source/destination input (S/D (I :0)) obtained from !he S/D mux.
The mux selects destination bits lB DST< I O) or source: bits IB SRC (I :Oi for the S/D (I :0) output. The
mux selection is made by ANDing lB DST bits J and 2. If both bit.s arc true, the LS/VCDT i:; being
selected as the BUS IB destination and the mux scl\:cts IB DST (I :0) for the S/D {I :0) bits. If either (or
both) bits are false, another destination is being selected for the BUS IB (Table 5-3). In this case the mux
select<> IB SRC (l:O) for the S/D (1:0) bits in the event the LS/VCDT is selected as the BUS IB source.
When the LSA mux SEL bit> (2: 1) arc 0:0, the literal input (LITERAL (07:00)) from the microword in
the PB is selected for the LSA (07:00) address lines
When the LSA mux SEL bits (2: I) arc 0: 1, the output of i.hc index register is sckcted for the LSA (07 :00)
address lines. The index register is loaded with IB IN (08:00) when LD INDEX asserts from the DP control
logic. 18 IN (07:00) provides the eight-bit address input to the mux. IB IN 08 provides INDEX 08 which is
used in the DP control logic to select the LS or the VCDT (INDEX 08 negated '"' LS: IN DEX 08 asserted
= VCDT). Also note that the four least significant bits from the index register arc ORed with the four least
signifi1:ant bits of the LITERAL input This allows the literal bits to perform four-bit wide indexing into
th(' LS or VCDT tables.
When the LSA mux SEL bits (2: I) are I :0, the output of the 1.ranslate register is selected for the LSA
(07:00) address lines. The transllltc rcgi>tcr is loaded with five bits f'rom the IB IN bus (IB IN (l 3:09))
when LD XI.ATE asserts frorn the DP control logic. These five bits output from the register as address
lines (05:0 I). Address lines (07:06) are grounded. The least o;ignifkant. address line (00) is LITERAL 00
which allow one-bit indexing of the translate LS or VCDT entries,

5.3.2 Write Strobe Logic
As previously mentioned, when the LS/VCDT is sdcned as the BUS iB destination, lB DST (3:2) arc both
true. If this is not an unsolicited SBI request (SUSPEND false) and the port is not in the uninitialized state
(IJNINIT J'abc), then EN RAM \\iR is asserted to generate an LS/VCDT write strobe·. l'N RAM WR is
applied 111 a flip-flop whose output is CRcd with XHUS WR LS/VCDT from th.:: unsc1licited Sill request
logic. Th,;. OR gate output is applied to some delay logic where th<~ LS/VCDT write strobe (WR RAM)
and the parity write strobe (WR PAR) arc generated. Delays arc iucorporatcd into the write ;,trobc logk
nrnking tl11: WR RAM strobe 40 ns wide and the WR PAR strobe' .JO ns wide. The WR P.i\R strobe begins
011 the tr:tiling edge of the WR RAM strobe <b shown in Figmc S·6.
The ckluv ing;c consist> of two flip-flops. The first flip-llop i, cnabkd by 1h1: OR gaw output and is set by
DP CLK. 'foe nip-fi'1p oi;tput i.s applied to '.lll AND gale which th~n ;h:,crts WR RAM. The dod puls•.:

tkll set th.; rJip.-flop is :1pplicd hl a dday line wlKl'l': it is delayed 40 rb to bcwnH: T40 T40 i:; invcrn:d und
:1ppkd tn tl1<: WR RAM AND gat<: causin;J, WI< RAM io negate.

DP C.LK
E113·5

WR RAM ____J:::::::40NS~~......
~LI~~~~~~~~~~~~~~~~~~~~
T40
E113-9

WR PAA
T70

Figure 5-6

Write RAM Timing Diagram

5-12

The assertion of T40 clocks the ;;ccond flip-flop. The se,·unJ flip-flop output i> applied to the WR PAR
A~D gate whi.:h then as.,erts WR PAR T40 i;de.laycd 30 m, imcrted, and th<'n applied to the WR PAR
AND gate causing WR PAR to negate

5-4 UNSOUCITF.D SRI RE:Ql ESfS
An unsolicited SBI request b a read or " write or a DP lo..:.ition. that was initiated by the host and not by
the pNt microcode. The request is a two-state sequence involving a susprnd cycle and an execute qdc:.
During the su,pcnd state the. microscquenccr ck>ek b stopped for one cycle. the microcode branch flags :•re
saved. and the BUS IB sour~es :rnd destinations are disabled thus freeing up the BUS IB for the external
access. During the execute state, the re:;d or write of the DP location c~curs and the data j, transferred
between the BUS IB and the SB! module. After the '!xccu:e c;cle. normal microcode execution is resumed
at the address that was frozen during the suspend c·yde.
An 1.rnsolidled SBI request SC'..JUence is i'litiated by either a write-in progress (UP WDIP) or a read-in progress (UP RDIP) flag from the SBI module. ln addition, the SB! module foods control information (R
B(09:00)) associated with the requested operation. into the XBUS L$ address register with LD LS ADRS
REG. XBUS LSA (07:00) from the register is applied to the LSA mux "here it may be selected to address
LS or the VCDT. XBUS LSA (09:00), also from the register. addresses a location in a I K x 8 PROM
\\hich outputs the control information for the requested operation,
Figure' 5-7 and 5-8 are flow diagram~ of unwlicited SB! write and read ><.>quences. respectively, Figure 5-9
illustrates the logic associated with the sequences.
5.~ I tlnsolidted Writl' Sequence
An unsolicited write sequence (Figure 5- 7) ts initiated by UP WDIP from the SB! module which causes
XBUS RD/WRT m assert. The next DP CLK pulse sets the suspend flip-flop placing the port into the
suspend state and causing SUSPEND to assert. SUSPEND in turn a'serts SUSPEND CLK to the c-introl
store logic in thi; PB where it inhibits the CS microseqJencer clock thereby susp-::nding microsequencer
operation. The next DP CLK negates SUSPEND and asserts EXECUTE The as_.;ertion of EXEClTE
causes EN RCV WD to assert. The next DP CU< pulse negates EXECLTE to complete the unsolicited
SB! write request sequence.

XBLS LSA (09:00) addresses a l K x 8 PROM which outputs control. information regarding the write
operation.

If PROM output 0 I (MDA TR) is true during the s;cspcnd cycle !SUSPEND true), and the port is in the
uninitialized state (lJNINIT truei, maintenance data is written into the CS in the PB. EN CS DATA IN
gates the maintenance data into the CS while CS W"f' a<.scrts ::1e CS wri;e strobe.
If PR0.\4 output 03 (LS/VCDTJ is true during the execute cydc (EXECL.TE 1rue.1. XBUS WR LS;
VCDT i; a.serted to the LS and VCDT write logic !Figure S-5) to 1.1-rite the data from the BUS IB into the

location addressed by XBUS LSA (0700) . Also XBCS E~ LS/VCDT HI and XBUS EN lS/VCDT LO
assert to the DP control logic 10 enable the RA\ls to be written. XBUS LSA OR :.pec1fics either the LS
RAMs or the VCDT RAMs. XBL.:S LSA 08 i, applied to the DP control logic which then enables the
selected RAMs (Figure 5-10),
If IB ll\ 00 is true during the execute cycle, PROM output> 05, 06. wd 07 arc sampled. If ,mtput 05 is
true. PICR WRT asserts which in tum negates UNINIT and take;. the port out of the uninilialil(~d ,t,1te
!Figure 5-1 ~).If output 06 is true, REG WRT a:..<;erts as a branch condition to the CS branching logic-.
REG WRT is a flag to the micro< ode that :l regi,ter h~> been written. The microcode .:an then chc~k th<~
registers for new data. If output er ;, true, PMTCR CLR is ;1ssencd to th~ boot timer logic to rc,c1 the
BTO rimer and extenc the boot time pe;iod ;Figur~ 5-12).

Start
t SUSPEND CLK
Disable microsequencer

clock.

I µPWDIP

t WDIP

DPCLK

PORT Tl

DPCLK

I CSWE

t EN CS DATA IN

l SUSPEND CLK
Enable m icrosequencer

clock.

t EN ACVWD

t XBUSWAT LO

POAT Tl

t XBUS EN LS/VCDT HI

t XBUS WR LS/VCDT

I XBUS ENLS/VCD7LO

! µP WAT CMPL T
To SBI module.

l EXECUTE

DPCLK

t PICA WAT

t CLK PMCSR

DPCLK

REG WAT
To CS
branching

t PMTCR CLR
To BTO timer.

UNINIT

Done

t CLK MADA
TK-8856

Figure 5-7

Unsolicited SBI Write Request Flow Diagram

5-14

Start

t µP RDIP

DPCLK

t SUSPEND

DP CLK

t SUSPEND CLK

RD PENDING

Disoble microsequencer
clock.

t EXECUTE

i SUSPEND

LO RTN RD

SUSPEND CLK
Enable microsequencer
clock.

t XBUS RD REC

t EN MAINT

DP CLK
I

t XBUS EN LS/VCDT HI
t XBUS EN LS/VCDT LO

EXECUTE

Done

Bit 31 of BUS t.<D.
Figure 5-2
TK-8861

Figure 5-8

Unsolicited SBI Read Request Flow Diagram

5-15

_x...;B;...U;...S...._LS'-A-'-00__._ _ _ (FIG. 4 _2 )
i.--x_s_u_S_L_S_A_OB
_ _ _ _ (FIG. 5 10)
,_x_s_u_·s_L_S_A_<_O_?_OO_>_,.. (FIG. 5-5)
(R 8<09:00>

.I
FIG.It
I'6·6
I LD LS
.

ADRS nEG

LSA
REG

(FIG. 5 10)

CLK

,__c_L_K_P_M_c_s_R...,.( FIG.:
5-L

XBUS LSA <09:00>
ADDR OM ,___P_M_c_s_R_ _ _ __,

MADR

-...,__.;-

CLK
MADR

2M1--..-------------~

IU.
F ·)
42
( 4-10
5-13

{ µP
i
XBUS
F.G.• _R.:.D.:.IP-+.......~-..... RD/ltlRT
ij 6
I
"p
WDIP .,-.__,,..
•FIG 4 7)

}
r-*

( FIG. 1
I,

4-2

DP CLK

----"'C
EN CS
DATA IN

LD RTI• RD

-"-·s_u_s_A_D_R_E_c_ _ (FIG. 5-21

PROM
(1K XS)

DP CLK

'.'>

XBUS WRT LO

F:G. 5- 101
XBUS EN
LSNCDT
HI
XBUS EN}· FIG.
LS/VCDT , 5 10
LO

' - - - - - - • } (FIG. 66!
1<P WRTCMPLT

FF
PORT T1
------<"'IC

4Mt----(FIGS. 5-10, 5-2)

5M 1 - - - - - - - - - - l r -

PICR WRT

(FIG 5-12l

6M 1----+----

REG WRT

1-----"' iFIG. 410!
DP CLK

C FF

CLR REG WRT
\FIG. 4-21 ------~K

Figure 5-9

Unsolicited SB! Ret;ue"t L)gic

NOTE
THE LOGIC IN THIS FIGURE 1$ CONTAINED
ON SHEET L OF THE ENGINEFRING
DRAWlNGS EXCEPT WHERE NOTED IN
PARENTHESES.

t - - - - - - - - { F I G . 5-11)

PMCSR
RD PENDING

r:;

PSR
(FIG. 5-9)

(FIG. 5-31

EN LS/VCDT

RD LS/VCDT
XBUS EN LS/VCDT LO
XBUS LSAOB
EXECUTE

EN VCDT
r-"'---.--<i. (Fl G. 5·) 1)

, ,. ,., l
f

XBUS EN LS/VSDT LO
XBUS LSA08
XBUS EN LS/VCDT HI
PSR
EXECUTE
EN LSHI

,,,. '"{

SID 0
S/D 1
INDEX OB

'"·· .,, {

18SRC01
IBSRCOO

TK SS!>6

Figure 5-tO

Control I ogic

5.17

5.4.2 l'nsolicited Read Seq~nce
An unsolicited read sequence (Figure 5-8) is initiated by UP RDIP from the SBI moduk which -::auses
XBUS RD/WRT to assert The next DP CLK pulse sets the suspend flip-!1,)p placing the po;l into the
SU5pend state and causing SUSPEND to assert. SCSPEND in turn asserts SUSPE.!\D CLK to the control
store logic in the PB where it inhibits the CS microsequcocer clock, suspendmg microsequenccr operation
The next DP CLK negates SUSPEND and asserts EXECUTE The next DP CLK negates EXECUTE to
complete the unsolicited SBI read request sequence.
XBUS LSA (09:00) addresses a I K X 8 PROM which outputs •:ontrol information ~~garding the read
operation.
The assertion of SUSPEND causes RD PENDING to assert. If PROM output Oi (MDATR) or PROM
output 02 (MADR) is true while RD PENDING is true, EN MAJNT is asserted to the PB to enable
maintenance data into the DP over the BUS MD bus. EN MAJNT is also applied to the DP control logic
where it asserts EN MD LO and EN MD HI to gate the BUS MD data to the BUS IB bus.
If PROM output 03 (LS/VCDT) is true while RD PENDING is true. RD LS/VCDT is asserted 10 the DP
control logic to assert EN MD HI and enable the high word from the BUS MD to the BUS IB. When
EXECUTE asserts, XBUS EN LS/VCDT HI and XBUS EN LS/VCDT LO assen to the DP control
logic to enable the RAMs to be read. XBL'S LSA 08 specifies either the LS RAMs or the VCDT ~AMs.
XBUS LSA 08 is applied to the DP control logic which then enables the selected RAMs.
The assertion of EXECUTE causes LD RTN RD and XBUS RD REC w assen. If a maintenance error
exists (MTE true). PROM output 04 (PSR) is sampled. If PSR is true. this ope.ration is a read of !1,c port
status register and bit 31 is asserted onto the BUS MD bus when miscellaneous dat'I is read !Figure 5-2).

5.5 CONTROL LOGIC
The DP control logic (Figure 5-10) generates the commands and enabling signais controlling the data llow
within the DP. Operation of the DP is controlled by the microword from the PB e'cept during unso!ici'.ed
SB! requests when the microcode is SU5pended and control shifts to the host via the SBI module.

5.5.1 Bl'S rB lle!.tia..tion
The IB DST (03:00) F:.J from the microword selects the destination for the data on the BUS IB. Table 5-3
lists the IB DST code' rnd the destinatiQns they select
A destination decoder Clecodes the !B DST field and output" the selected destination. The decoder 1s
enabled when IB DST 03 ~· 0 (first eight codes in Table 5-J). The remaining three bits (iB DST (O::!:OO))are
decoded to select the destination shown in the table. Note that if the port is in the uninit.ializcd state
(UNINIT true), or an unso;icited SBJ request is in progress IEXECLTE true), the d~C•)der is dii;a.bled and
the BUS JB destination is selected by the host via the SBI module and the XBLIS LSA address lines
(Paragraph 5.4).
The LD INDEX or LD XLA TE outputs are asserted during the fim cycle of a twc• .:yde access when the
LS or the VCl)T is the destination. LD INDEX (or LD XLATEi functions to load the index register (or
the translate register) with the LS or VCDT address (Figure 5-5). The selection bernecn the LS or i.he
VCDT is made during the second cycle when IB DST 03 = I.
Th·~ next three outputs from the dest.ination decoder (LD WRT FILE. LD BM. LD C/A! arc a,;.~encd

when the SB! module is selected as the BUS 18 destination. All three signals arc sent rn the SBI moduk.
Dt:codt:r output. LD PB OCT is as.-.erted when the PB OUT regi:;tcr is selected as the BUS IB oestina1ion.
LD PB OUT ioads the PB OUT register from the IB IN bus for output onw the PORT DAT A bus (Figure
5-2).

Table 5-3 18 DST Codes
IBDST
03
02
0
0
0
0
0
0
0
0

0
0
0
0
l
I
I
I

Destination
01

0
0
I
I
0

I
0
I
0
I

I
I

0
0

I
I

0
0
0
0

I
I
l
I

l
I
l
I

0
0

I
I

I
I
I
I

0
I

0
l

Address Source

S/D
01

I
0
I
0

No operation
LO INDEX
LDXLATE
LDWRTFILE
LDBM
LDC/A
LDPBOUT
MLDPB
Not used
LS
LSorVCDT*
LS
VCDT

0
0

LITERAL
Index Register
Translate Register
LITERAL

• Depending on INDEX 08; INDEX 08 = O. LS select.:<!
INDEX 08 = l, VCDT selected

Decoder output MLD PB is a maintenan.ce function. When asserted it enables the output of the PB OUT
register onto the port data bus and allows the data to loop back into the DP by enabling the PB in register.
When 18 DST (03:02} = I: I, source/destination (S/D) codes are generated in the LS/VCDT address select
logic which control LS/VCDT address selection by the LSA mux (Paragraph 5.3.1 ). The S/D codes are
listed in Table 5·3 along with the aMress sources that they select.

5-19

5.5.2 BliS IB Source
The lB SRC (02:00) field from the microword selects the >ourcc for the BUS IB data. foblc 5-4 li,ts the IB
SRC ..:,ides and the ~oun;cs they select
A source decoder decodes the IB SRC field and <mt puts the -ckctcd source. Not<' that if :i1c port is in the
uninitialized state (Ul'iINIT true). or an unsolicited SBI request is in progress (SlJSPEND true), the
decoder is diii<1blcd and the BUS IB source is selected by the hos! via the SBI module and th<~ XBUS LSA
address lines 1 Paragraph 5.4).
·

The first four codes listed in Table 5-4 as..,crt LS/VCDT SRC thereby selecting the LS or the VCDT as the
BUS 18 source. Accordingly. the S/D codes generated in the LS/VCDT addrc's sck<'I logic control the
LS/VCDT addrcs..., selection just as they did in the BUS IB d~llnation decode process. The S./D codes arc
listed in Table 5-4 along with the address sources that they select.
LS/VCDT SRC asserts EN UWE to the DP pari.ty logic to cnabl.c the logk to check parity on the data
read out of LS.
l~'>/VCDT SRC also asserts EN LS/VCDT to enable the output of the LS/YCDT RAMs.

The lruc state of EN LS/VCDT caus..'S EN MD HI to as.o;crt if the VCDT has been selected (EN VCl.H
true). Thus, the high word from the BUS MD bus is placed onto the BUS lB bus along with the low word
from the VCDT.
Decoder output EN PB IN is as.sened when the PB IN register is selected as the BUS lB source. As shnwn
in Figure 5-2, EN PB JN gate,~ the output from the rcgish:r onto the BUS MD bus. The data is then
transferred to the BUS IB bus. :-iote in Figure S-10 that EN PB IN also asserts EN MD LO and EN MD
HI in order to transfer the BUS MD data to the BUS lB bus. In addition, EN MISC is ncg;•kd to isolate
the UTERAL/PMCSR rnux output from the BUS MD bus while the PB IN register data is being
transfcrrcv..
Table S-4 IB SRC Codes
02

IBSRC
01

L'i
LSorVCDT*
LS
VCDT
EN PBIN
LITERAL

()
()

()

I
I

()

l
I

0
0

()

l
I

()

EN ALU

EN XBL'S IN

()

•

S/D

IBSooree
00
I
I
I

Ix rending on INOl' X 08; 0 .•. LS, I

Address Source

00
l
()

(l
()

l
()

LITERAi
Index RcgistL'r
Translate Register
LITERAL

\'CDT

The next decoder output is asserted when the LITERAL field of the micr•.lword is ,,+:ctcd ct.' lhc BUS rn
source. The decoder output asserts EN MD LO and EN MD HI tu transfer BLS MD dat.1 to th.: BCS Ill
bus. EN M!SC is true to gatl' thl' LITER1\L data frnrn the LITERi\L'PMCSR mu.x ont•.> the BCS MD
bmc.

Decoder output EN ALL is asserted when the ALU is selected a> the BUS IB sourcc. F\.i ALU enables the
ALU logic.
Decoder output EN XBUS IN is asserted when the SBI module is selcncd as the BUS IB darn source. EN
XBUS IN is sent to the SBI module to enable the data transfer into the DP. EN XBUS I~ is also applied
to the DP p:trity logic to enable the logic to check parity on it"~ <i:lla from the SBI module.

5.5.3 Control Signals
EN MISC is used in the interface logic (Figure 5-2) to gate the output of the LITERAL/P\ICSR mux
onto the BUS MD bus. EN MISC is always <1ssertcd c.xccpt "hen the Bt'S MD bus is being used to transfer
data out or the PB IN register (EN PB IN true), or BUS MD data is being input frorn the PB (EN MAINT
true).
EN MAINT is applied to the PB to gate data from the PB into the DP on the BUS MD bus. EN MAl:";T
is asserted from the unwlicited SBI request logic in order to rc;1d the maintenance data register or the
maintenance address register in the PB.
EN 1\f 'LO and EN MD m gate the BUS MD low word and the BUS MD high wnrd rcspectivdy. onto
the Bl.JS IB bus. Both signals arc as.serted by EN PB IN, thus gating th.: assembled longword from the PR
IN register to the BUS IB. Both signals arc also asserted when EN MAI NT is true, thus gating lhe maintenance data from the PB onto the BUS 18. &1th si.gnals are again asserted b~' the LITERAL output of the
source decoder.

When executing an unsolicited SB! read request !RD PENDING true). and if the P\1CSR is being read
(PMCSR true), both EN MD LO and EN MD HI are agam asserted., If the uns•)li<.itcd SBI request is to
read the PSR (PSR true), only EN MD Hl as.~erK
EN MD HI is also as.;;erted by the AN Ding of EN 1~5/VCDT and EN VCDT. EN LS/VCDT is a~~crtcd
by an unsolicited SBI read request of the LS or the VCDT (R () LS/VC DT true). or by the LS/VCDT SRC
output from the source decoder as described in Paragraph 5.5.2 above.
Control signals EN VCDT. EN LS LO, and EN LS HI enable:.. the VCDT, the low wllrd sccti,in of LS. and
the high word section of LS, respectively. Each of the three cn,1bling signab arc e1sscrted from an OR gate.
Ea1:h OR gate is fed from three :\'SI) gates. any of which can a>scrt the p.1rticular enabling signal via the
OR gJte,
During an unsolicited SBI request, EXECUTE asserts and d1s;ibks two ol' the three A~ D gates in each
signal area. The third :\ND gate is used during the unsolidtc.d SBI rc'"qucst. XBl.'S EN LS/VCDT LO
from the unsoliciteo SBI request logicc is applied to the unsolicited SB! request AND gates in the EN
VCDT and the EN LS LO signal areas ,iJong with XBUS LSA 08. XBLX LSA 08 sclec't$ between the LS
and the VCDT. If XBUS EN LS!VCDT LO is true and XBl 'S LS,\ 01< is true. the VCDT i::. enabled (EN
VCDT a:;.<;ertsl. If XBUS !..SA 08 is false, the lt1w section oC LS is enabled CE1' LS LO asserts).
XBUS EN l~5/VCDT HI from the unsolicited S!31 request logic is applied to the unsolicited SBI m.1ucst
AND gate in lhe EN LS HI signal area along with XBUS LS\ 08. I! XBUS EN LS/\CDT HI 1s true and
XBUS LSA 08 is false, the high section of LS is enabled (EN LS HI a:<scrh).
\\hen the port is under microcode conlrnl (EX!TLTE false'!, enabling d the VCDT . the low section of
LS. and the high section ,,f LS is done via the (>thcr two AND gates in the EN \CDT. E.N LS LO, crnd EN
l..S HI signal areas. The tw(l-bit Si[) code generated in the LS/\( DT addre,s sekc(i,1n ingic 1s appiicd to
the si.x :\ND gates to select th•' LS and the VCDT. INDEX OS i> u,;cd 10 scb.~1 between lhc L'i and the
\ COT when ncccs,;arv.

The logic in Figure :i-10 foilows the S/D code in Tables 5-3 and ) . . J to enable Ihle appropriate RAM area.
VALID PAR i:; asscncd to the SBl nwdulc as a nag that data being trJnsft.rcd from the DP to the SBI.
module has been checked for parity. VALID PAR i> ncgJtcd by the IB SRC co<k v.hen the Bt:s IB source
j,; a LITERAL or the ALU (Table 5-4)." Neither the LITERAL field or the ALL' output is (cheeked for
parity and the negation of VALID PAR flag~ the SHI m(X:ulc of this
5.6 DP PARITY GENERATOR/CHECKER
A multipurpose parity generator/checker (Figure 5-1 l) perforrm. most ol' the DP parity i.asks. The parity
gcncrntor/checkcr is connected to the IB IN bus.

E ~ X.l:H.!S I'.\ al:;t\ nrl!:1t.c~ \',.\LI n P ,\ R.
~.he da1:t trn.r.sfcr is ft·;:11r :he SBf :r1"1'.11.i:i~' 1, .,_

!h;:~ ·~~ ;.i ''lkr, "( c·..:~ '' c·tJndi: id< ..,:..... ; }1('· SB! rnf~:Lh.: ;-, ~ n~· Rl ·S Hh,·;l~i..,_::.: ;PK'.

f N LSPE

LD PB

IF!G

510,·I.:@
,{WP
FiG. )

OtJT

PARITY

( _:s PAR

FIG. J'

5·2

5-2'.1 ~

IN LATCH

?V:.:x<.1:0>

I PB MUX EN

1..-

( IF1G. 6-2)

(RI

SEL
,,
E_:..,

,_PB
_ PAR
_ _ _ :F1G. 3-21

/~~I
~----~.-LJ

I'""'
LW PAR

·-

XB OUT
cAR HI

GEN

iE'
1;F1G.6-4}

ir\PAROUD

iF iG. 5-10' _ _ _ _ _ _
E_N_x_·B_'u_·s_1N_'_ _ _ _ _ _ _ _ _ _ _ _ _ ____J
IPE

~
~-------- -- iF!G.69:

LSPE
RBPE

XBUF PE
--------1

,FIG. 3·2'
i F!G_ 421 _ _ _c_s_P_E:_ _ __,.

!F, G_2_2 71 __
x_M_,T_s_T_A_T_u..:·s_7_.J
OPE

F IC
f' 1

{---SE_T_~"_;T_E_

!<DTE:

1---'--w

LETIER OESIGNAT!O'iS
JN PARENTHE~ES REFER
TO ENGINEERING
~iHAWJ~~GS CONT A!N li\itJ
CORRESPONDING LCl(dC

i.__________

5- . . ,

_____

I
I

__J

5.6.I PB PAR
PB PAR arc parity bits generated on data bytes output from the PB OLT register to the PORT DATA
bus. PB PAR is sent to the PB along w... ..i the its associated data byte.
Data packets on the IB IN bus are in 32-bit longword format. The longword is input to the parity
generator/checker logic where it is divided into bytes and input into four parity generators. Each generator
outputs an odd parity bit (BYTE (3:0) PAR) generated on the associated input byte. The four parity bits
arc applied to a PB parity mux. The mux select input (PMUX ( 1:0)) selects the parity bit for the mux
output which is placed on the PB PAR line to the PB. PMUX (I :0) is the coe~ that selects which byte of
the longword is to be output from the PB OUT register onto the PORT DA TA bus (Figure 5-2). Hence,
the parity bit on th.: PB PAR line is for the data byte on the PORT DATA (7:0) bus.
A WP (wrong parity) bit can be input to each of the byk parity generators as a maintenance check of the
parity logic. LD PB OUT is trm: during a data tram;fe; from the PB Ot:T register to the PORT DA TA
bus; hence, the WP maintenance bit is applied to each c•i the byte parity generators.

5.6.2 Input P11rity Error (IPE)
Parity is generated on the longword input from the SB! module and compared with the associated parity bit
supplied by the SB! module. If the two do not compare, there is an input parity error and !PE asserts.
The four parity bits generated on the lc;ngword byte~ (BYTE (3:0) PAR) are applied to a longword parity
generator which generates a single parity bit for the enti:e longword. The longword parity bit (IB LW
PAR) i;. XORed with the longword parity bit (IN PAR ODD) input from the SB! module If the two XOR
inputs do not compare and EN XBUS IN from the DP control logic is true, IPE asserts as a PMCSR bit
and as an input to the PE OR gate.
The WP\ wrong pari•y) bit is again used to genente a parity error as a maintenance check. With LD PB
OLIT false. only one WP bit is used for the input longword.

5.6.3 Local Store Parity Error (LSPE)
A parity bit is generated on each word written into I.Sand into the VCDT. The parity bits are stored in two
RAMs. When the LS or the VCDT is read, parity is regenerated on the data read out and compared to the
parity bits stored in the RAMs. If a match is not obtained, there is a IO'~al store parity error and LSPE
asserts.
The BYTE 0 PAR and BYTE I Pl',R parity bits from the first two-byte parity generators are XORed to
produce a single parity bit (LOWD PARITY) for the IB IN low word. Likewise, a single parity bit (HI
WD PARITY) is produced 'or the 18 IN high word. LOWD PARITY and HI WD PARITY are written
into a low word parity RAM and a high word parity RAM, respectively. The two RAMs arc addressed by
LSA (7:0) from the LS/VCDT address selection logic to write the parity bits at the same address as the
data b<'ing. written imo L'i. EN VCDT is applied to the RAMs as the most significant address bit. While
the VCDT is being written, EN VCDT is true thereby writing the VCDT parity bits in a separate location
within the RAM. The RAM write strobe (WR PAR) is obtained from the write ;.trobe logic in the LS1
VCDT adJress select logic (figure 5-5).
When Lhe LS or the VCDT is read. the data read out appears on the IB IN 1.incs for a parity check. The rn
H\ data generates a LOWD PARITY bit and a HI \VD PARITY bit as described in the preceding para·
graph. LSA (7:0) associated with the read, addresses the low-word parity RAM and the high-w1.ird parity
RAM to access ihe parity bits stored when the LS/VCDT data (now being read) was written. Write strobe
WR PAR is false thereby enabling the parity RA.M outputs L'i/VCDT LO PAR acd LS/VCDT HI PAR.

LOWD PARITY and HI WD PARITY generated from the read data is XORed rcspecti\cly "'ith LS/
VCDT LO PAR and LS/VCDT HI PAR from the parity RAMs. If the compared bits d•• nci match, and
EN LSPE is as.~erted from the DP control logil:, LSPE is as,;erted as a bit in the PMCSR Jnd as an inpm to
the PE OR gate.
5.6.4 XB OUT PAR HI and XB OUT PAR LO
Parity is generated for the data being output from tht: DP to the SBI module. The data source may be thcLS. t!ie VCDT. or the PB IN register. The lB SRC code specifies the data source and, therefore, the 'ourcc
of the parity bits to be supplied with the data.

IB SRC 02 specifies the data source as shown in Table 5-4. When false, the data source is the LS or the
VCDT. In this case, the LS/VCDT LO PAR and LS/VCDT HI PAR parity bits are read out of the lo"'
word parity RAM and the high word parity RAM. respectively. The bits are then gated out tel the SB!
module as XB OUT PAR LO and XB OUT PAR Hi.
When lB SRC 2 is true. the data source is the PB IN register. In this case, PB MUX ENA is true and
PMUX (I :O> selects the input byte for the PB IN regish.:r (Figure 5-2). PB MUX ENA al-.:J enables a
parity latch which receives RB PAR from the PB JN parity generator. The PMUX (1 :O> code places four
RB PAR parity bits into the parity latch as the four data bytes are loaded into the PB !'\' register. The
parity uits associated with the first two by!cs are output from the parity latch and XORcd to form the XB
OUT PAR LO parity bit. The parity bits associated with the last two byte> arc XORed to form XB OUT
PAR HI.
5.6.S Recei•er Buffer Parity Error (RBI ·E)
Data from the PB ;:;t.o the Pb IN register is checked for parity errors. A parity bit (RBUF PAR) is
received from the PB along with the packet bytes. An RB PAR parity bit is generated for each byte loaded
intc the PB I?'-! register. RB PAR is compared with RBUF PAR and if a match is not obtained, RBPE is
asserted. RBPE is a bit in thc PMCSR register and is also input to the PE OR gate logic. During valid data
transfers E'°ll RBPE from the PB is true to gate RBPE to its destinations.
S.6.6 Parit) Error (PE)
PE is an OR functLm of seven port parity error bits. Included in the OR function are the three parity error
bits gcnera1ed in the parit» generator/checker logic OPE, LSPE. RBPE). Additional inputs are parity error
bits from the PB transmit channel (XBljf PE) and contr,;il store RAMs (CSPE). Output parity error
(OPE) from the SBI 1.1odule and XMJT STATUS 7 (TDATA PARITY ERROR) from the link are also
'inputs to the PE OR gate.

PE is at.it in the PMCSR register. PE causes the assertion of MTE (maimenanc: error) MTE is applied to
t~~ boot timer logic (Figure 5-12) where it resets the boot timer and places the port · to the uninitialized
state. MTE can also be asserted by SET MTE fn>m the SBJ module.
If the nrnintenance interrupt nag (Mlf) from the SB! module is false. the true state of \!TE i.vil; caus1·
PORT INTR to assert to the SB! module cau<ing an interrupt on the SBL A feedba.:k loop negates PORT
INTR after two DP CLK pulses. MTE remains true until REG Cl.R is asscr,cd from the SB! nwdulc.

S.7 BOOT TIMER AND MAINTENANCE TIMER
The boot timer (Figure 5-12) is used to delay starting the CS microcode by holding the pott in the uninitialized state. Boot jumpers selec: the delay which can be up to 1500 seconds in JOO-second increments. The
delay is used to allows time for the cluster to boot and to load the microcode.
Upon system power up, LOGIC CLR ass-erts from the SBI module causing CLR to a~rl. CLR directly
sets the uninitializ.e flip-flop causing UN. c :IT to assert, placing the port into the uninitialized state.
Feedback from the output of the uninitialize flip-flop to the flip-flop input, holds the flip-flop in the reset
state until CLR asserts. In the reset state, UNINIT is false, resulting in feedback that conditions the flipflop to reset.
A boot timer one•sccond oscillator outputs into a decade counter at a one-<:ycle-per·S¢COnd rate. The de·
cade counter divides by 100 and outputs into a binary counter once every 100 seconds. A comparator
compares the binary counter output with the count set into four boot jumpers. When the output from the
binary counter matches the count set into the boot jumpers, the BTO (boot timeout) fiip-flop sets and
asserts BTO to the uninitialize flip-flop. BTO causes the uninitialize flip-flop to reset and negate UNINJT.
The negation of UNINIT takes the INTI out of the uninitialized slate and starts the microcode running:
The assertion of PICR WRT by an unsolicited SBI request from the host, also take the port out of the
uninitialized state. Thus, the host can start up the microcode before the boot timeout period has expired.
The assertion of the maintenance error flag (MTE) from the parity generator/checker logic, also sets the
uninitialize flip-flop and places the port into the uninitialized state. In addition, MTE clears the 8TO de·
cade counter and holds the BTO flip-flop reset so that the uninitialized state is maintained until MTE is
cleared from the SDI module (Paragraph 5.6.6).
Other signals that clear the BTO flip-flop and decade counter are maintenance timer disable (MTD) from
the PMCSR register, and PMTCR CLR from the SBI module. The BTO timeout period can be extended
by clearing tht boot timer with PMTCR CLR via an unsolicited SBI request.
A maintenance timer 400-microsecond oscillator outputs a TICK signal to the CS branching loi;ic every
400 microseconds. TICK forms a time base used by the port microcode.
5.8 290lA MICROPROCESSOR
The DP contains eight 2901A microprocessor chips which constitutes the DP 2~:::iA mk•oprocessor. See
Figures 5-13 and 5-14. The microproc;;ssor functions are controlld by the microword fam the CS. The
following paragraphs discuss the 2901A microprocessor and its operations.

5.8.1 ~ta Path
Eight 2901As l'te used in parallel to formulate a 32-bit longword input/output for the microprocessor. The
2901A contains two 16 X 32 RAMs, an arithmetic logic unit (ALU). a Q register, and control circuitry.
The RAMs are used as a scratch pad where the results of arithmetic and logical operations are stored
temporarily for future use. The contents of the RAM are gated into the ALU by the source cor.trol signals
supplieci from the CS microword.
The two 16 X 32 RAMs are designated as RAM A and RAM B. The RAM A and RAM B address lines
are tied together and are addressed by ALU A/B {3:0) from the CS microword. Hence. both RAMs
address the same locatio,; simultaneously.
The 2901A operates such that when RAM Bis written, RAM A is also written. When writing RAM B, the
RAM B select lines select both the RAM Band RAM A internal address. Data presented at the data input
is writ.ten at a location dependent on the ALU destination code from the microword.

5-25

l3>>-----..---_..,.,If:\

L LOGIC CLR

__
M_.T_E_ _~ (M)
(FIG.b11) -

BOOT
JUMPERS

CLR

PICA WRT
!FIG. 5-9)---~
JMPR <3•0>

BOOT
TIMER

osc

DECADE
COUNTER
(c100)

CLI".

e:.,,,;.y
CC· t"r:ER

!1 SEC)

A
COMP.AR·
ATOR

B
CLR

CLR

(FIG. 5· 1 li _ _...;M:.:.T.:..;E:;.__ _...--..,.
(FIG. 5-2) _______
M_T_D_ _-jc_.,;

I ~

UNINIT

CFF

IL...

(FIG. 410)

(FIG. 59 ) __P_M_T_C_R_C_L_R_-.f
CLR

MAINT.
TIMER

osc

(400 µSEC)

1-------ID

TICK
- - - (FIG. 4 101
NOTE:
THE LOGIC IN THIS FIGURE IS CONTAINED
ON SHEET N OF THE ENGINEERING
DRAWINGS EXCEPT WHERE NOTED IN
PARENTHESES.

DPCLK

(FIG. 6· 111 __
L_O_G_IC_C_L_R_ _-40\ B

Figure 5-12

Boot Timer and Maintenance Timer

:.-26

(FIG. !J-9) EXECUTE ..-A-L_U_G ALU DST
DST
<2:0>
rALU DST

<2:0'>

~?'

BUS 18 <31 :OD>

::i::n-------:-:_______. ,. . ._

(:·nj

ALU FCN <2:0>

ALU SRC <2:Q'>

t:ffi

t:TIM
I

ALU AiB <3:0>

..-,--l-1"1

3~--'--+-+-+--+--9'1

RAM
(2-PORT)
16 X 32 BITS

2-~--.......1-'t-l-....

1 - - - -......-+-1-+I

a-----·-'--+-.,.

NOTE
THE LOGIC IN THIS FIGURE IS CONTAINED
ON SHEET A/B OF THE ENGINEERING
DRAWINGS EXCEf'TWHERE NOTED IN
PARfNTdESF.S.
TK8St).8

F1Hure 5· 13

2901 A Microprocessor Simplified Block Diagram
5-27

2901A
DATA PATH
,---~~~-----------

I
(0)

SHIFTER

--+--------l

I
G AL;J I
OST ·-'-l<_L_U...,I
!DEST)

<2:0>

ALU
OEST
DECODE

LATCH

RAM
(REG

t-'.,--------L,--------iSTACKI

L_
(RAM)

B
(. ~l?:i) 1 _A_Af_~u-~_'.3_:_0~_~r-------~~~.!...::!~~c._
___________.J

LATCH

PORT SELECT

I CCO"

Oe<C<

MX DATA BUS

ALUINPUTSEL
ALU INPUT
:-'-..;:.c..;:.c~-+_;;;.:;.;::..:.:.;;..:::..:...:::.~---...1 OPERAND
SELECT

(ALU FCN) ! ALU FUNC SE_L_ _ ,.

ALU SRC <2:0>

---------el OEST
ALU OUTPUT
~-----~
OE CODER

ALU FCN <2:0.

..:o;;::U:..:T.:..P:::.UT.:....::E.:.:N:;:.A~BL_E_ _ _ _ _ _ _ _ - - - - - ·

(f IG. 5-101 __E_N_A_Lu_+-'-IE;..cN;..cD
__A_.cT_:.A..c_:.PA-'-T-'-H--')+-l

ICARRYl

Figure 5-14

2901A Microprocessor Biock Diagram

5-28

The high-speed ALU can perform three binary arithmetic and five logk operations on the two input words,
R and S. The R input field is dnven from a two-input mux, while the S input field is driven from a thrceinput mux. Both muxes have an inhibit capability: that is, no data is passed. This is equivalent to a zero
source operand.
The ALU R-input mux has the RAM A port and the BUS IB bus connected as inputs. The ALU S-input
mux has the RAM A port, the RAM B port, and the Q register as inputs.
The mux can select various combinatiJns of input pairs among the A, B, D, Q, and zero inputs as source
operands to the ALU. The microinstruction inputs used to select the A.LU source operands arc ALU SRC
(2:0}, The ALU source bits are defined in Table 5-5.
Table 5-5 ALU Source Code

Mnemonic

ALliSRC
I 0

Octal
Code

AUJ Source
R

0
0
0
0
I

0
l
0
I
0

0
I

A
A
0
0

5
6
7

D
D
D

Q
0

2
AQ

AB
ZQ
ZB

ZA
DA
DQ

l
l
I

0
0
l
I

0
0
I
I

0
I

0
B
A

The D and Q source operands are described as follows. The D input is the direct data input from the BUS
IB bus. This port is used to insert all data into the working registers inside the 290!A data path. The Q
input from the Q register is a separate file used as an accumulator or holding register.
The ALU destination is ;;elected by the ALU DST code from the microword. During an •Jnsolicited SBI
request function (EXECUTE true), the ALU DST field is altered to force a null de~tination code. Thi' is
done to prevent any erroneous data from being '.vritten internally within the microprocessor.

5-29

The ALU functions are selected by ALU FCN (2:0) from the micro\\\Jrd. The ALU function bits arc
defined in Table 5-6.
The ALU has four status outputs: carry out (ALU C). sign bit F3 (ALU N), zero bit F-·~O (ALL' Z). a:•J
overnow (ALU V). ALU C is used as the carry nag. ALU N is the most significant digit of the ALU and is
used to determine positive or negative results without enabling the tri-slatc outputs. ALU Z is used for zero
detection. ALU Z is asserted when all the F outputs are low. ALU Y is used to !lag arithmetic operations
that exceed the available 2's complement number range. The four status outputs arc applied to the branching logic in the CS.
The Q register is a file loaded from the ALU and used as a temporary storage register. The Q register
output can be loaded back into itself and shifted right or left as during fraction, muhiplication. and division
operations.
Table 5-6 ALU Function Code
Mnemonic.

ALl' FCN
2 I 0

ADD
SUBR
SUBS
OR
ANO
NOTRS
EXOR
EX NOR

0
0
0
()

J
l
I
I

Octal
Code

ALll hnction

Symbol

R plusS
Sminus R
R minusS
RORS
RANDS
Not RANOS
REXORS
REXNORS

R+S
S-R
R-S
RVS
RAS
R ;\ S
RVS
RVS

()

I
0
0
I
I

2
3

l
0
I

5
6
7

5.8.2 Data M11niJrulation
After data is loaded into the microprocessor, both the Q register and any RAM address can be rotated or
shifted left or right. During a rotate, the bit transferred out one end is transferred in on the other end.
During a shift operation, the bit shifted out is lost and a new bit is generated and shifted in at the far cr,d.
To acrnmplish these shifts and rotations, the most significant bit (MSB) of each four-bit 2901 A is connect·
ed to the least. significant bit (LliB) of the adjacent 290 I A via a bic:!in:ctional transfer line. To complete the
wraparound required to rotate data. the MSB of the entire 32-bit longword is connected to the LSB via a
bidircction~ I transfer line.

5-.lO

5.8.3 Carry' l..ook-Ahelld I.-0gic
Circuitry a"~ociated with the 290 I As contains full carry fc)(lk-ahead logic thai ~pceds the e\ecut1on of arith·
rnetic instructiom and allows the data path to function with full 32-bit carry look-ahead gencratio1L Figure
5-15 illustrates this logic. Each of the 290! \chips generates bc'th a curr) gcncrdtc output (GEN) and''
carry propagate c)Utput \PROP). The f<'"r jX!irs of GEN and PROP signals for bit,; ( 15:00) are combined in
a curry ·kipper along with a C IN signal derived from A.LU function codes ALL FCN (I :0). The sum of
the outputs of the carry skipper (ALU CJ 6) go to another c,my :c.kipper and are combined with the GE~
and PROP signal> fc.~m the bit \31:16> 290!As. The output of the second carry .,kipper is combined to
output carry status bit (ALU C) to the CS branching logic.

ALU FC!'< 0

ALU FCN 1

\Ai

G <03.:00>
p <03·00>

-·-

G -<.07:04>

(

FROM\

29()1 A
l(AJ
'

<0704>
rro2901A \Bli

)1 G < 11'08>
?

C'.6__.__,A
,__b..LiJ
__

< 11 00>

i g <\15 12>

p < 15:12':

.,,__

ALU C16

,.__A_L_u_,_1s_:_OO_>_c_;- - - - - - - - - 1'::AARY
ALC <15.00> f'
SKIPPER

_____

( G <19 16>

(

FROM \

P <2J 20>

ALUC

ALU C20

>------nOC:Sf

ALU C24

p <•9:16>
G <:13:20>

1----------·----.i 'SJ

ALU C28

CARRY
SKJPPER

:a:

2901A i 11· P
G <27:24--,:27..:24'...• ·
\\B)
)<()TE
:...ETTER DfSlGNAT!JNS •N PARE:'JTHESES
PEfER TO E~G1f'<EEA!N'3 i)RAWiNGS
'.;(JNTA.lMNG CORRESPONDING L.OG!C

G ~3;:28>
p ·-'.'."3'!·28>

\ALU<31:0C ·P

Figure. 5-l 5 Carry Look A.head Logic

FOR

5-31

Ll\R:3ER i'.R';'

ALU FCN 0
ALU FCN 1

ALU CO

G ,03 Off··

p <07 04"

,fROM»
( ?9?1A
iAr

P <03·oa::

ALUC4

1--A-l_l.i_'C-8-•

G .07.04>
CARRY

ALU C12

------..i SKIPPER i - - - - - -

)1 GP ·•.11:08>
<.11:08:>

'T"

l <15:12>

ALU <15:00> P

P <27:24>

figure 5-15

ALIJ C 16

SK!PPEl'1

ALU C20

ALU C

)

i - - - - - - - i T O CS)

i -ALUC.24
- - - - 1· !.(TO
2901A

P <lg:l6>

'IBI

i-------...,(T02901A (B))

!---------------~ 18!

ALU C16
A ) - -8-<-:-1-6 ->-..i C IN
19

p <23:20>
G <27:24>

Cit-.

1-A_L_U_'_<_1_5._:00_>_G_ _ _ _ _ _ _ _ _~ CARRY

G <15:12>

, 2F.90R
. 01MA ,,.
(

T
j

(A)

G <23:20:>

)

( ;O. 1A.·
;Al

CARRY

ALU C28

\ IB)

SKIPPER

(8)

G <31:28>

!!LC-.:: 1:00> GI

p <31:28>

cA;_~;

Carry Look-Ahead Logic

<J;:'.lQ> Pi

NOTE
LETTfQ JES!GNATIONS •N PA.RENTHESFS

:·o

REFER
E''.:;•NEERiCiG DR A.WINGS
CONTA''.•'NG CORRESPON01NG LOGIC

CHAPTER6
SBJMODULE

NOTE
Tiie functional block diagrams in Chapt

6 use logi-

c11; AND and OR syml>ols. It elves not necessarily
follow that a corm.ponding gate exists oa t.he SBI
mocluie logic prints. Ille assert'on of inputs A alld B
causbg the assertion of out?'l~i C -y be represested
on a block diagram by 11 >iagle AND gate, yet the
englaeering drawing -y show that senn1l circuit
stqes are inv.ll•~ in the ANDing operation.
The fanctiooal block diqrun ill this chapter are
key~ to the SBI mo41de ~ circuit scltematia (CS prints) by letter desipatiou 1111 pal'Plldie-ses. Tiie letten sped{~ the 5lleet of the CS prints
tht eot:taias the detailed 1Qcic associated with the
f1111etional blocks In the diagna.

Tiie slpal !Wiies llSed ill die f llBctioaal blv.k diagr&Bi are the nmes used Oil die eapieering CS
prints. Where other slpa.l iwnes or notes are used.
they arie t'llclosed ia parendleses.
6.1 SBJ OVERVIEW
Figure 6-1 IS a simplified block diagram of the SBI module. Note that the SBI module interfaces witb the
SBI bus via SBI trnnsceivers. Signals shown in the block diagrams in this chapter \a11d on the engineering
logic ;:>rints) will be prefixed with a T if they are being transmitted to the SBI, or with an R if they are being
received 'rom the SBI.
Data transfers within the SBI module are port initiated or unsolicited SB! requ~ts.
Port-initiated transfers are controlled by the microcode. The microcode CTlmmands a tran.~mission c-'· .:fat;;
from the DP to the SBI. or a read of data from the SB! to the DP. The data is transmitted lo or read from a
device on the SB!.

Unsolicited SBI requests are initiated by the host CPU to read or >Vrile a DP register. The host controls the
transfer sequence.
An xn.it file and a receive file, each capable of holding four longwords of darn. ~re used for port-initiated
data transfers. The files are divided into A and B se1.·tions with each se,'(wn ~.:iPJbk of :c1;:.g a quadword
of data (two iongwords). The files have '>Cpi!nitc read and "'fHC :1ddres< pointer>. Th~ xmi\ fi,c i.; used when
data is being written to the SBI from th<c DP Th(' rcc:(·iv,: !!le j, used whc" ,fau is bcmg read frM1 !he SB!
to f\11~ DP.

,.,
TR.\NS

CE1VERS l
SET A GO

~---'SE"-T'""Sc:G,_O----~-}
; ON

, •11..ire 6-1

fFROM

CS~

}

SBI Module Block Diagram

6.t.l Write Trusfen
For a port-initiated write transfer, LO C/A (command/address) is asoerted by the microcode and loads a
C/A register with the write command and the SBI address that. is to be written. The command/address is
obtained from the DP over the BUS IB.

The microcode then asserts LO WR T FILE to load the xmit file with a longword of data from the BUS IB.
The xmit file is write addressed by DP FILE ADD {I :0) from a two-bit file address counter. LO C/A from
the microword resets the file address counter to zero when the C/A register is loaded. Thus, when the first
data longword is loaded into the xmit file, it is plac.:d in the fim !:x:ation (A 'ND!).
LD WRT FILE increments the file address counttr to point to location A WD2. Thus, as each :ongword is
loaded, the file pointer is incremented to the next location. After all four locations are filled, the microcode
wiU not attempt to load any more data until the A section of the file has been read out lo the SBI and there
is room in the file for new data.
The byte mask associated with the data longword is loaded into the byte mask register by LO BM asserted
by the microword. The byte mask (BUS 18 (7:0)) is brought into the byte mask register from the DP over
the BUS 18.

SEE NEXT FRAME
FOR LARGER ART

6-2

T MASK <3:0>

; BYTE

LD1~-LD_B_I\_!_ _ _ _ _ _ _ _ _ _ _ _ _ __

114----------------------1 MASK

EUSIB <7 0-'
j

RE_c__

......--~...-.---··

XMiT
FILE

BUST <31:00>

'----'---"'"-

B WD2
8

WD1.

WD2

GUS IB <31 :00;·
v - - - - - - - - - - - - - - - . - - L - D - C -....JA

~ , HWM DVi

A WD1
(TO OPI

PARITY

WR EN ....- - - - - - DP FILE ADD <1:D>

CIA TSE

CHECKER

TX FILE TSE
TX FilE
RD ADRS 0

WA ADRS

RCV!XMiT
FILE'
iNCR
ADRS
CNTR

RD EN

SBI
TRANS-

I
_J

ClR._.-~

CEIVERS

B BSY
XJVl!T
_ _ _ _ _ _s_E_T_A_G_o_ ------~·
CONTROL

i.FHOM CS)

,________s_E_T_B_G_o_ _ _ _ _ _ _

i..----

TTAG <2:0>

ADr>

RCV RD 2

BON
1--- - - -}

R CNF <1:0>

i.10 (;.$.'

SET RDXPi

RDTO

CONFIGURATION
REGISTtR

------~---------------~· ~B~~P~D.\2'E-r-----------~
R 8 <3;:.JC>

PARITY

CHECKER

c .__SET
____
RDXPT _..,

RCV RD\

RD2

RD1

___

... WR ADRS

1------.--~

cb L=
·

LOGIC

..__

6-2

RD1

t - - - - - - - - " ' 4 WF: P<

RECEIVE
READ
DATA

R 10<4:0>

SHI Module Block Diagram

BUS !8 <31:00>

Ru EXPT

POK
R TAG <2:0>

Figure 6-1

RCV RD2
_,i-----1"'
D

H< x~uc; ii,

RD fNle-------------·------··---··-·

R~ :~:S!<t--__D_P_F_1L_E_. A_f_:><-i_·----····---

•:HH·/, :JP.

After loading the C/A register, the A section of the .xmit fiic, and the byte mask register, the mkn.,.;<'dc
asserts SET A GO to the xmit control to start the .xmit file unlciad sequence . A GO is asserted 10 the
transmit logic where the write operation is controlled. The xmit controi asserts A BSY tndicating that the A
section of the file is busy being unloaded. While the A section is being unloaded (read). the B section is free
to be loaded (written) with more data longwords from the DP
The transmit logic initiates arbitration for the SBI bus by asserting El" TR to the arbitration logic \\"hen
the Cl780 has won the SB! bus, the arbitration logic returns ARB OK l'l d1e transmit logic
The transmit logic asserts C/A TSE (transfer enable} to transfer the command/addre&> From the C/A
register to the SBI bus. The transmit logic then proceeds to read the xmit file by asserting TX FILE TSE
which enables the file output to the SBI bus.
The xmit file read address is a two-bit pointer in which TX FILE RD ADRS 0 from the transmit logic is
the least significant bit, and B BSY from the xmit control is the most significant bit. The addreo;.~ pointer
initially points to location A WDL
After the first longword is read out, TX FJLE RD ADRS 0 asserts to addr~ the next location in the fik
(A WD2).

The tag and ID associated with the longword is also sent out to the SBl.
After the data has been placed on the SBI. the transmit logic looks for an acknowledge (ACK) confirmation from the receiving device. When the ACK confirmation (R CNF {l :O}) is recc.1ved, the transmit logic
resets the GO bit by asserting CLR GO to the xmit control.
When the GO bits resets. A DN is sent to the CS branchi:ig logic to in~cate that. the transfer is complete.

If the transmit logic does not receive an ACK confirmation, it re-tries the opero1tion. If, after 102 microseconds of re-trying, the ACK confirmation has not been. received, the transmit logic aborl~ the transfer
and sets a timeout error bit (CXTMO) in the: configuration register (se.: Appendi~. C; Paragraph C.4)

6.1.2 Read Transfers
for a port-initiated read transfer, LO C/ A is asserted by the microcode and loads the C/ A register with the
read command and the SB! address that is to be read. The command/address is obtained from the DP over
the BUS IB.
After loading the C/A rcgistet, the microcode asserts SET A GO to the xmit ~-ontrol t0 start the ;eq"ence
that will load the A section of the receive file with the read data from the addrC!>Sed device. A GO ;,s.-em to
the transmit logic where the read operation is controlled . The xmit control asserts A BSY to indicate that
the A section of the file is busy being loaded. While the A section is being loaded !written). the B secuon is
free to be unlooded (read) by the microcode.
The transmit logic initiates arbitration for the SBI bus by asserting EN TR to the arbitration logic. When
the CI780 has won the SBl bus, the arbitration logic asserts ARB OK to the transmit logic which then
asserts C/ A TSE to transfer the command/address from the C/A register to the SB! bus. The transmit
logic then looks for :m ACK confinnation (R CNF (l:O}J from the SB!. When the ACK confirmation is
received, the transmit. logic shifts control of the read sequence to the receive read data logic whkh looks for
the read data to appear on the SBL When the read data appears. the receive read data contrnl logic che(b
the ID field (that the data is for the Cf780), ch~cks the tag field (that it i> read dal3). and the ;wit;. If
everything checks good, the logic asserts RD EXPT to w•.ite the data kng,h1rd inw the receive fik.
If the read data dOt:S not appear within 102 micwsec('nd&, :he 'cc~i1c read <lotll lugk asserts:. read d:H:;
timeout (RDTO) signal which set5 a bit in the configuration register.

The rcx""Cive file is write addressed by a t.vo-bit. pointer with RCV RDI bciLf. the lc;ist >ignifit·ant bit and B
BSY being the most significant bit. The pointer initially points to location A RD I.
After the first longword is written, the receive read dcta logic asserts RCV RDl which increments t~e
address pointer to the next file location (A RD2 ).
If this is a simple read (of one longword). rtCV RDI nega1~ A GO in the xmit control. If ihis is an
extended read (of a quadword), RCV RD2 asserts when th,: second longword is recei~·ed. In this case, RCV
RD2 is used to negate A GO.
When A GO negates, A DN is sent to the CS brwching logic to indicate that the transfer is complete

6.2 PORT·INmATED TRANSFERS
6.2.J SBJ Exteaded Write Trusfer
An extended write transfer is the transfer of a quadword of data from the DP ir the SBI bus. Figure 6·2 is a
block diagram of the logic involved in a wrik transfer. Figure 6-3 is a llow diagram illustraung the
sequence of events in an extended write transfer.
The microcode initiates the transfer by asserting LDC/A. LDC/ A loads a C/ A register and counter with
the command and address (R 18 {31 :00)) from the BUS IB in the DP. The register and counter are ioaded
via an IB receive register which latches the BUS IlJ data for 200 ns. Bits RIB (31 :28) specify the command
to be executed (in this case an extended write): bits R IB (27:00) specify the address on Lhe SB! bus where
the quadword is to be written. Bits R IB (8: I) of the address field are loaded into the C/ A counter which is
incrementd by INC ADRS from the transmit logic after each transfer. Thus, the C/A register does not
have to be reloaded for each transfer when doing multiple transfers. The microc~"lC!e reloads the C/A regis·
ter with a new page address whenever a page boundry is crossed.
LDC/A clears the file address counter so the xmit file write address bits \DP fl LE ADD< l :O)) point to
location A WDI ir. ;he xmit file.
A data quadword is then loaded into the xmit file by LD WRT FILE from the DP. LD WRT FILE asserts
TX FILE WT EN which loads the first longword into locatwn WDL LD WRT FfLE llso increments the
file address counter to !!ddress A WD2. LD WRT FILE then reasserts to place the ~nd longword intc A
WD2 and to increment the file address counter to address the first longword location in the B sectiun. ..,,- the
file.
After the data quadword is in the xmit file, LD BM (load byte mask) from the DP asserts and loads the
byte mask (R IB (7:0)) into the byte mask register. RIB (7:0/ contains two four-bit byte masks, one for
each longword in the xmit file.

NOTE
If all the quadword bytes are to be used, the byte
mask register need not be loaded as the l~k ~m
automatically assuroe a masli Jf all I',;.
The microcode assert-; SET A G<) to start th~ transfer sequence . SET :\ GO sets a Jl;p-11op (;au>ing :\ GO
and A BSY to ai;sert. A GO is applied to the transmit k'gic wh1.::h .:.-.Jntrois inc data transfer. !\ BSY indic3tcs thal tlle A section of the xmit file is busy.

CLR .,._l_N_C_A.-.O_R.._S_

LOAD.,._L_D_B_M
_ _ _ _ _ _ _ _ _ {FIG. 5· 10)

T MASK <3:0>

BYTE
MASK REG

OMMK

R IB <7:4>
R IB <3:0>

(J)

{

IB
,_.-----. R IB<31:09>,00
RECEIVE
BUS IB
- - - - - -......-t REC
....-.-<"'3.,.-1:"'"00""':-,-(FIG. 5-2)
CIA REG
(Tl

BUS TB <31:00>
(TO SBI) ------------------0.....--<
4

lMI

OPE
PARITY
XBUS OUT P;.1 R LO
(FIG. 5-2; 5-11) 4 - - - - - - - t C H E C K E R - - - - - - - - - . . - + (A)
XBUS OUT PAR HI

C/ACNTR

..__V_A_L_ID_P_A_R_ _ __.(FIG. 5-IO)
T ID <4:0>

TOI
FROM
SBI

{

R 10 <4:0>

ID
LOGIC

,___ __.

LOAD

(6FIG.){
4
:"""!

RIB <08:01>

(M)

CURIO
t----(FIG. 6-4)

LOAD

(0)

INC ADRS

!NCR

...-----·

OUT

TR
TR SEL <D,
C, B,
,1:.JMFERS t--..--.._____
..........-..
..........A>
_.,(FIG. 6-6)
(HI
ARBITRAEN TR . . - - - BUS SBI
TION
t---LOGIC
ARB OK SBI
CIA TSE
( FROM) TR <15:00>
SBI
.
(H)
t - - -..... TRANSMIT MASK
TTAG <2:0!-->_ _ __,
~~GIC
SEL
TTAG 1

;

WR ADR
RO EN
XMIT
FILE
(Sl

IN~.t - - - - - - - - - - + - - R - " I B____...
OP FILE
ADD <1:0> FILE
ADDRESS
( FIG.)
· 6-4

<31:00>

LOCIA

CNTR
(P)
CLR

EN XBUS IN
}
·---'-.• lflG. 5·101
....._~_,._......,.LD--'W_R..._T_F~IL~E'--~·

!NCR

WR EN .,..__ _T_X_F_l_L_E..._WT..._..._E_N___<

1----'

------,
{
SET B GO
(FIG. 4-2) _____
s_ET_A_G_o_ _ _....,.

RCV RD 1

IF !G. 6-4)

GO
CLR

RD XPT L

{

c (J)

I' ON

}

X>------e_o_N_'- - - - -

ri~--------1 TIMEOUT
COUNTER
(102.4 µs)
(LI
EN

------11----------------------------t

L-Figure 6-2

Write Transfer Block Diagram
6-5

(FIG. 4·101

TTA.G 1

I
A

__________
Ro_e_x_n_,F1G. 6·41

----------------

NOTE:
LETTER DESIGNATIONS iN
PARENTHESES REFER TO
ENGINEERING DRAWING',
CONTAlNING CORRESPIJNDING

LOGIC.

Start

f SET A GO

t LD CIA
Load command/address
~ ,r:~gister from 18 bus with

~rom microword. ~

BSYINE

In. itiates transfer to SB!
from sccticn A cf >i:r:'lt
file.

I extended write command
and address to be written.
Clear file address counte•

..-----L--f--- --,-(7)

in DP file control so address pointer DP FILE

AD'.) <1:0> points to
A WD1 in xmit file.

EN rn

I __.

i CLR GO
Clears GO bit in xmit
controi

Perform arb1trat100
for SBI bu~

t LD WRT FILE
Load xmit file with
data IMgword from

IB BUS. lncremer i
file address counter.

'.A DN

Tei is mkrocode that
the tran$fer is do~

a 0-d .!'le\111 do ta car. be
ioaded into sect;op A
of wrlte file,

i C/A TSE
Transfer write C/A
and associated ID a~d

i TX FILE TSE
Transfer longword in

File addres> counter
points to B section of

A WD1 to SBI. Transler

xmit file (6 WD 1) for
next write command
from microcode.

byte mask fron, byte

Ma.I< regi.ster to SBI.
Transfer T TAG <2:0.>
for d2ta to SBI

t
!Ticrerne,..l C/A cnu~;ter.
Pedorrr, ar~itration and

1 TX FILE RD ADRS 0
locrement xmit file read
pointer to A WD2.
Mask-~ all

l LD BM
<7:0>1.

Figure 6-3

l's

_ _ _J

Extended Write Fiow Diagram
6-(·

trans1e-r data fro.,-, B
section e:~ ~~:te file to
SHI.

NO
~~:t MS

r: {'fnt"MOfY

f!"i'Stem (>rron [Jct Jr"\

?SR .. , ?tt'frjFTi: .fi'.'."rn-

nx FILE TSE

Load byte mask register
with byte mask (R I B

Aboct transfe.-. ~l
CXTER error h·t ;c
con1 iq, ,ration register.

YES

tag to SBI.

Fil;, address counter
points to A WD2_

Mmrt transfer.
S..t CXTMO ierro• b•t. ir<
configorati·ot; regine<-

To CS branch Ing togic.

Transfer longword in A
W02 to SB L Trans<er
byte mask. from bne
register to SB I.

f{'• ,; ~ :, nt<

When rhe transmit logic receives A GO from the xmit control, it ass.:rts EN TR to enable the arbitration
logic. Four TR jumpers generate TR SEL (D,C,B,A) to establish the prioritv level of the Cl780 port The
arbitration logic looks at the SBI arbitration field (BUS SBI TR (15:00)) from the SBI and compares the
level of any pending TR requests with the level established by the TR jumpers. If there arc no TR request<
pending at a higher level then that established by the TR jumpers, the port wins the SBJ bus and the
arbitration logic asserts ARB OK to the transmit logic.

The transmit logic responds by asserting C/ A TSE (transfer enable.) to transfer the command/address
from the C/A register out to the SBI bus. The transmit logic outputs the tag identifying the SBI data as a
command/add:-ess. Also the TR SEL priority code is output to the SBI (via the ID logic) as the ID field (1
ID (4:0)).

The transmit logic then asserts TX FILE TSE which reads the longword in A WDI out of the xmit file a.•
BUST B (31 :00) and then to the SBr bus. The transmit logic outputs the tag identifying the longword a>
write data. In addition, the transmit logic outputs MASK SEL to select the four-bit byte m~sk associated
with the longword. The trammit logic then asserts 0 MASK to gate the ma.~k (T MASK (3:0)) to the SBl
bus.
'
The transmit logic next asserts TX FILE RD ADRS 0 to increment the xmit file pointer to address location
A WD2. TX FILE TSE then asserts again to transfer the second longword to the SB! bus. The transmit
logic then selects the other rour-bit byte mask from the byte mask register and places it on the Sbl bus.
After transmitting the C/ A, the data, and the associated information fields onto the SBi bus, the transmit
logic checks the confirmation response (R CNF (I :0)) from the receiving device. If a no response or a busy
confirm:ttion is received, the transmit logic retires the extended write transfer on the SBI If, after I 02
microseconds of re-trying, an error or ACK coniirrnation response still has not been received, the transmit
logic aborts the write operation and assert~ SET CXTMO to the configuration register. SET CXTMO sets
a command/address timeout error bit (CXTMO) in the configuration register

If an error confirr.1ation is received, the operat.on is immediately aborted and the CXTER e.rror bit set in
the configuration register.

If a positive confirmation (ACK) is received, the transmit logic assert' CLR GO to the xrr.il control logk to
clear the GO bit.
A timeout counter establishes the "no response" and busy time• ut periods. The counter L' enabled by T
TAG I when the C/A tag is asserted to the SB!. When the timeout period has expired ( 102 4 ;i;s) the
counter output is asserted causing CA TO to go true.
CLR GO from the transmit logic is applied to the x.mit control where it a:sert. GO CLR to the A GO
flip-nop. GO CLR resets the fli~nop negating A GO to the transmit logic and asserting A DN to the
microcode branching logic in the CS. When the microcode senses the presence of A Dl'i . it kn,w•s that
:.cction A of the .xmit file is ready to receive more data.
Abo, A BSY negates, therebr allowing B BSY to ctimc true when the B GO bit set,;.
After the extended write transfer is complete, the BUS ERR bit in the configumtion register;, ;;hcckcd b)
the microcode branching logic. If Bl'S ERR is true, an error occurred during th..: extended v.ritc trnrs1c:
just completed.
6.2.2 SBI Extended Read Transfer
An extended read transfer is the transfer of a quadword of data frnm '"m1c dc-.·icc <Ii' the SBI
the DP'
Figures 6-2 and 6-4 arc block diagrams of the logic involved in a read tran,fcr. F;g;,:rc ()·~ i; c ;fo" diagr:.::"
illustrating the sc,quence of event> i~ an extended read transfer

R PAR
r---------------i

(FROM 5811 {

(A)

( FIG.)
6-2

PARITY
GEN/CHECK

Ip OK

R 8<31 :00>

~-·----------..._·--+--~·

smomcl ~" rmcl
I i :
.
I

(

OUT

BL,S iB <3 ~ ·o··
·---~"

1~ii:J_ 6<.2)

•

l,___IN_._PA_R_O_D_D_., , ",,3 . b •

RDE~.._E_'N_'_X_0_us_.N_·_1

ROADR...,._V_P__F_IL_E_•_ _

ADD -·:-~1:0~

RECEIVE
Fi LE
(Al

--11-----.-.._,i.1 WR ADA

·11

SET RDXPTO

RD XPT 0

IL_I_
K

R JAG ·•2:0>
(FROM SBI 1 - · - - - - - - - - . . i

;: ~ !'.,:, , \

'," ..
- · - i,
(

TAG
DECODE
(C)

Figure 6-4

Read Transfer Block Diagrnm

RD TAG

NOTE:
LETTER DESIGNATiONS !~, f ~;;.u;">lESES
REFER TO ENGINEERING J":.t,'.~:·;ss

CONTA1t'lNG CORR.t-SPVr~::·--"~ L(<LC.

Start

t LO CIA
Load command/address
register from IB BUS
with extended read
command and address
of data source. Clear
file address ~ounter in
OP file control so
address pointer DP FI LE
ADD <1 :O> points to
A RD 1 in receive file.

Abort transfer. Set
RDTO error bit in
configuration register.

t SET A GO
Frcm microword.
Initiates read data
sequence.

t A BSY
A section of receive
file is busy.

t OUR ID
Received ID matches
our ID. The received
data is for Cl780.
I RD TAG
Data on SB I is read data.
! POK
Parity is go<rl on received
data.

t ENTR
Perform arbitration
for SBI bus.

t A DN

·ro CS ~ranching logic.

Tells microcode that
requested read data i~
available in the receive
file.

YES

t RD EXPT
Write longword into
receive 'file.

Se! MSE \memor~

sv:stem errort oit in

PSR *. Perform e~ror
rout~ne.

Transfer read command/
address, tag, and ID to
SBI bus.

t RCV RD1
Increment receive file
write address to location
A RD2.

t RCV RD2
Second longword is
transferred to A RD2
in receive file.

ACK

l RCV RD1
Negates ADRS 0 to
address RD1 word in
receive file.

t SET RDXPT u
Receive read data logic
monitors SB I bus
looking for the returned
read data from the
addressed device.

YES

Abort transfer. Set
CXTER error bit in
configuration register.

Abort transfer.
Set CXTMO error bit in
configuration register.

Extended Read Flow Diagram
6-9

Perform arbitration and
transfer data from SB I
10 B section of receive
file.

l AGO
GO bit cieared in
transmit control logic.

Figure 6-5

1 B BSY
Addresses section 8 of
receive file.

! EN XBUS IN
Read receive file out 10
IB BUS. increment f•le
address counter.

The microword initiates the transfer by asserting LDC/A.LDC/A loads the C/i'I register anr.! count<~r
with the command and address (R I~ (31 :00)) from the BUS IB in the DP. The register and counter are
loaded via an IB receive register which latches the BUS IB data for 200 ns. Bits R 18 (31 :28} specify the
comm:ird to be executed (in this case an extended read); bits R IB (27:00) spe.cify the SBl bus address of
the device to be read. Bits R IB (8: I) of the address field are loaded into the C/ A counter which is incre·
mcnted by INC ADRS aft.:r e~d1 transfer. Thus, the C/ A register docs not have to oc reloaded for each
transfer when doing multiple transfers. The microcode reloads the C/ A register with a .. cw kdg<' address
whenever a rage boundry is crossed.

;,DC/A also clears the file address counter so the receive file read address bits (DP FILE A;)D {l:O)l
point to location A ROI in the receive file.
The microcode ass.:rts SET A GO to start the transfer sequence. SET A GO sets a Oip-nop causing A GO
and A BSY to <l!;Sert. A GO is applied to 1he transmit logic to initiate the arbitration process for the SBI
bus. A BSY indicates that the A section of the receive file is busy.
The transmit logic asserts EN TR to cna1'lc the arbitration logic. Arhitration for the SBl bus proceeds as in
the case of an extended write transfer. When the port has won the SBI bus. the arbitn•tion logic returns
ARB OK to the transmit logic.
The transmit logic responds by asserting C;' A TSE to transfer the command/address from ihe C/A regis·
tcr out to the SB! bus. The transmit logic outputs the tag identifying the SBI data as a command/address.
Also the TR SEL pri<>rity code i> output to the SBI (via the ID logic) as the ID field (T JD (4:00)).
After transferring the C/ A and the associated tag and l D fields onto the SB! bus, the transmit logic checks
the confirmation response (R CNF (I :0)) from the add1.:ssed SB! device. If a no resJX>nse or a busy confir·
mation is received. the transmit logic re-tries the extended read transfer on the SB! :r, after 102 microseconds of re-trying, an error or ACK confirmation response still has not been rcceiv d, the transmit k'gic
aborts the read operation and as..serts SET CXTMO to the configuration register. ,.,ET CXTMO sets a
command/aJdress timeout error bit (CXTMO) in the configuration register.

If an error confirmalion is received, the operation is immediately aborted and the CXTFR ernir IJit set in
the configuration register.

If a rositivc confirmation (ACK) is received, the transmit logic asserts SET RDXPT L (read data c\pcCt
longword) to the receive read data logic. SET R DX PT transfers cont. ol of the read sequence to the receive
rc,td data k•gic.
A~ sli0wn 111 Figure 6-4, SET RDXPT L from 1hc transni:t logic sets a tlip-nop asserting RD XPT L which

in '11~n asserts ilD EXPT. RD EcXPT enables the receive file to write the received dat:; 1..ingword into
location A ROI
When the data appear,., the associat::d ID field is compared with the TR SEL code from the arbitration TR
jumpers. If a match is obtained, OUR ID asserts lo the receive read data logic indicating th~.t thr· rcJd da:a
is f,ir the Cl780.

The tag field is ~ccodi>d by a lag decode circuit. lf the tag indicates that the'. dat.1 is read d,ila. RD TAG
nsscrh to the rccciv(: read data logic.
The incoming data ;, checked for parity in a parity checker. lf there arc no parity emir,. POK is J.'>Sertcd
!<.> the receive read data logic.

6-lO

Ir the ID. the lag. and t.hc parity arc all good, the receive read data logic as:;crts RCV RDI. RCV RDI is
the lcasl significant bit of the receive file write address pointer. Asserting RCV RDI increments the write
pointer to kication !\ RD2. RCV RDI is then m:gatcd via feedback to the RD XPT L llip-llop causing it t.o
reset

For an extended read sequence (Figure 6-5), the transmit control logic asserts SET RDXPT Q (read data
"~pcctrd quadword) which sets a flip-flop asserting RD XPT Q. RD XPT Q keeps RD RXPT asserted to
write the second longword of the read tran~fer into location A RD2 of the receive file.

The ID. tag, and parity associated with the second longword arc checked. If they arc all good. the rcceil'c
read data logic asr;erts RCV RD2. RCY RD2 is rct:irncd to the xmil ''ontrol and resets the A GO bit.
When A GO negates, A PN asserts to the microcod~ signifying that the trnnsfer is complete.
If the requested data did not appear on the SBi after I02 microseconds, the operation is aborted and the
t imcout C·)Untcr asserts RDTO to the configuration register setting a timeout error bit.

6.3 UNSOLICITED SBI REQtJE~'TS
Unsolicited SBI RCAiuests arc reads and writes of a CI781J location that have been requested by a device on
the SBL The transfer sequence is not under control of the port microcode,
6.3. l l.lnsolkited SBI Writes
Figure 6-6 is a block diagrarn of the logic involved in an unsolicited SBI write sequence. Figure 6-7 is a flow
diagram illustrating the sequence of events in the write sequence.
The unM>licite<l SBI write command/01ddres.~ is placed on the SBI bus (along with the associated tag and
mask) by the soliciting device. R TAG (2:0) is decoded in !he tag decode logic and outputs C/A TAG
identifying the information on t.he SBI as a command/address.

Pamy is checked on the command/address field. POK asserts if there is no parity error.
'f h" Jddrcss dewdc logic receives R ll (2.7: IO) from lhc SBI and asserts OUR ADD it' the unsolicited
rt'.yucst ;, addressed the Cl780 porL
l'h~: address/function Mc<K!c logic dtcodes R B (:l I :28) to determine what the function is and if it is a valid
functiun. FUNC VU) asserts if the function is valid.

The SBI trl·civc state logic rtl<1nitors and co11trols the unsolicit.ed write sequence. It senses if the corrc.::t tag
w:rn reo~ivcd, if parity was g<.~id. and if the function is valid. If these were all go<J'.l, the rc<:civc state logic
'""~:m, WD LXPT to thr T confim; logic. The T Cimfirm logic transmits an ACK confirmation back to lhc
,~(~hr;ting dcvic,:(;,

1 'I' /\f U·~SS ;i,,,<·rh ii the write is to a DP register. If UP ACCESS docs not assen, the write is t.o tk
:.. 1nhp11,,;i,.:li r<'.~:i,ln. R H (O"i:OO> stJ)'plic;; the addrcs> of' t.hc port rcgisler to rttci\'t' the write data.

PARITY

fi PAh

!FROM SSIJ --

POK

CH€C~EA

<Al

TR SEL

( flG

<.D.C.B,A>
[

R TAG <2:0>

I
( FRCIM)J R MASK <JO>

ser

)

··

l ~-23022>,
R8

<2(U6>

L.D PT~ RD

59'
BUS 18
-lFIG.':i2J

-------~---fFiG

IS
flLCEIVE
RE ti

<31•00',

iTI
l\IOTf.·

U:TrfH m:srGN.ATIONS IN !>ARENTHf.Sf;S
RHL:A TO ENGINfERING Di:tAWlNG:~
CONTA.11\,llP''llG COAAE-SPO"fDING tOGIC

Figure 6-6

Unsolicited SBI Request Block Diagram

6.3.J.J Writing a DP Register - If the function is a write of a DP register (UP ACCESS true), LD LS
ADRS REG is asserted to the DP to load the address of the register to be written into an XBUS address
register in the DP. The address of the register to be writt"n (RB (09:00) is supplied from the SBI module to
the DP.
When the write data appears on the SBJ, the a.•sociated tag is decoded by the tag decode logic. The ti.lg
dec(lf!e logic asserts WO TAG identifying the SBI data as write data.
Parity is checked on the write data. POK assells if there is nc> parity error.

SEE NEXT FRAME

FOR LARGER /\HT

6-12

R 8 <09:00>
___
EN_R_c_v__w_o_ _ _ _ } (

(FROM 581)

RB <31:00>
---------------...-.i
RECEIVE WRITE
DATA REG.

BUS IB <31:00>
- - - - - - - - - ( F I G . 5.:?)

µPWD EXPT

CLK

~!~ )

(NJ

PARITY
CHECKER
(Al

(FROM SB!) _ _ _ _ _ _ _R_P_A_R_ __

---(TOOP)

)
( 6FtG
2

TR SEL
-<-:o-.c-.-B.-A->_ _,...

f
( ::,OM

___

.._

(FIG 69)

µPWRTCMPLf
- - ·• (FIG. 5.91
CIA TAG

R TAG <2:0>

~ "MASK

CLR SBI REO
POK

TAG
DECODE

(Cl

WO TAG

WSQ FLT

CNFG RDIP

C!ffG STB

WO EXPT

<3 O>
FUNC VLD
OUR ADD

R B <23:22>, <20: 16>

T
CONFIRM
(C)

T CNF <1:0>

BUST <11:0~>
!TOSBI) ---...-~
'----~"'-"''---(FIG. SBl-2)
1---"'"'--~---(FIG. SBl-9)

SBI
TnANSMIT

t.OGIC
(Kf

LO ATN RD

------~------------•(FIG.

NOTE:
LETTER DESIGNATIONS IN P!\RHHHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.

Figure 6·6

Unsolicited SBI f(i:qucst Block Diagram

5-9)

r<-c>:•01

Start

CIA received from SBI.

NO
t C/A TAG
Data is a command/
adaress.
tPOK
No parity errors.
t OUR ADD
Cl7BC is being addressed.
t FUNC VLD
Command is a valid
function.

1 WO EXPT
Write data is expected.

t T CNF
ACK confirmation
transmitted to SBI.

Error confirmation
returned to SBI.

IT CNF
ACK confirmction
transmitted to SBL

t µPWO EXPT
Write data loaded into
receive write data register

Configuration register
is to be written.
t LO LS ADAS REG
load address to be
written into DP.

tµPWDIP
DP notified that write
data is available.

t EN RCV WO

or takes write data.
DP writes data into
addressed location.

t µP WAT CMPL T
DP notifies SBI module
that write data is loaded
into selected register and
transfer is complete.

t WDTAG
Data on SBI is write data.

uone

Figure 5-7

Un$0licit.ed SB! W:ite flow Diagram

6-13

t CNFG STB
Write data loaded into
configuration register.

The mask 2ss.,-ciated with the write data is checked for all l's. Any other mask code for an unsolicited SBI
write request operation results in an error confirmation being returned to the requesting device.
The T confirm logic chec for the presence of WD TAG, and that the mask is all l's. The T confirm logic
then transmits an ACK wnfirmation to the requesting device on the SBI.
The SBI receive state logic also generates UP WD EXPT which ioads the write data from the SBI into the
receiv<' write data register.
The SB! receive state logic then asserts UP WDIP (write data in progress) to inform the DP that the write
data is available. The DP responds with EN RCV WD which gates the write data out of the receive write
data register into the DP.
A sequence is now executed in the DP to write the data into the selected location.
After the DP has deposited the write data in the selected in the location, it asserts UP WRT CMPLT to the
SBI receive state logic indicating that the transfer is complete. The receive state logic then retumc- to the
"not busy" state.
6.3.1.2 Writing the Coatfipratioa Register - If the function command decoded by the address/function
decode logic is not UP ACCESS, then the write data is for the configuration register.
When ihe configuration register is to be written, LD LS ADRS REG does not assert to the DP as there is
no DP register ajdres£ to be loaded into the DP XBUS register.
The SBI receive state logic monitors and controls the writing of the configuration register. As in the ease
for writing a DP register, if FUNC VLD, OUR ADD and POK all check good, then WD EXPT is true. If
a write data tag is received (WO TAG true) and the write data mask i~ all I's, an ACK confirmation
response is sent to the requesting device. The rec<:ive state logic then asserts CNFG STB which loads the
write data into the configuration register.
The receive state logic then returns to the "not busy'' state.
6.3.2 Unsolicited SBI Reads
Figure 6-6 is a block diagram of the logic involved in an unsolicited s·m read sequcnc.; Figure 6·8 is a flow
diagram illustrating the sequerce of events in the read sequence.
The u11S-Olicited SB! read command/address is placed on the SBI bus (along with the associated tag and
mask) by the soliciting device. R TAG (2:0) is decoded in the tag decode logic and outputs C/A TAG
idcniifying the information on the SBI as a command/address.
Parity is checked on the command/address field. P OK asserts if there is no parity error.
The address decode logic receives R B (27:10) from the SB! and as.-;erts OUR ADD if the unsolicited
request is addressed to the Cl780 port.
The address/function decode logic decodes RB (31 :28) to determine what the function i~ and if il is a valid
function. FUNC VLD as.5erts if the function is valid. UP ACCES.5 as.5erts if the read 'sofa DP register. If
UP ACCESS does n"t assert, the read is of the configuration register. R B (09:00} supplies the addr::ss or
the port register that is to be read.
When the T confirmation logic senses that POK, OUR ADD, and FUNC VLD are all true, it transmits an
ACK confirmation response (T CNF) to the requesting device on the SBL

6-!4

Stan

C/A received from SBI.

ress.
t POK
No parity erron.
t OUR ADD
Cl780 is being addressed.
t FUNC VLD
Commalld is a valid
function.

tTCNF
ACK confirmation
transmitted to SBI.

Configuration register
is to be read.
t LO LS ADAS REG
Load address to be
read into OP.

t µP RDIP
OP notified that read
data is expected.
OP gets requested
data from audressed
location.

t CNFG ROIP
Configuration read data
expected. Transmit
logic notified to transfer
configuration register
dalll toSBI.

t EN TR
Perform arbitration
forSBI bus.

t LO A N 0
OP loads return read
data Into return read
data register. Informs
transmit logic that dalll
is ready for transmission
toSBI.
~ µP ROIP

t ENTR
Perform arbitration
for SBI bus.

t RTN RO TSE
Return rea<I data
transferred to SB I bus.

Done

Figure 6-8

Unsolicited SB! Read Flow Diagram
6-15

t CNFG ISR TSE
Configuration register
data transferred to SB I.

6.3.2.t Reading 11 DP Register - If the function is to read a DP register (UP ACCESS true), LD LS
ADRS REG i.~ ~rted to the DP to load the address of the register to be read into an XBUS address
register in the DP. The address of the register to be read (R <• \09:00)) is supplied from the SBI mOdule to
the DP.
The SBI receive state logic monitors and controls the unsolicited read sequence. It senses that the operation
is an access of a DP register (UP ACCESS true), that the operation is a valid function (FUNC VLD true),
and that the request was for the CJ780 (OUR ADD true). The receive state logic also checks the parity (P
OK) of the SBI information field.
When the logic senses that all of the above signals are true, it asserts UP RDIP (read data in progress) to
the DP notifying it that read data is expected.
UP RDIP initiates a sequence in the DP that gets the requested data from the selected location and places
it on the BUS IB.

The DP then asserts LD RTN RD to load the return read data into the rc::um read data register. LD RTN
RD also informs the SBI transmit logic that the requested data is ready to be transmitted to the SBI. At
this point the receive state logic negates UP RDll'.
The transmit logic asserts EN TR to the arbitration logic enabling it to arbitrate for the SBI bus. When the
arbitration is successful and the SBI bus is obtained. the arbitration logic r~turns ARB OK to the transmit
logic.
The transmit logic then asserts RTN RD TSE to transfer the return read data out of the return read data
register and onto the SBI bus.
6.3.2.2 Reacling die Configuration Register - If the function command decod..,d by the address; function
decode logic is n<>t UP ACCESS, then the register to be read is the configuration register.
The SBJ receive state logic senses the false state of UP ACCESS and ru>serts CNFG RDIP (configuration
read data in progress) indicating that configuration read data is ex.pected.
CNFG RDIP is sent to the transmit logic which then mvst arbitrate for the SB! bus. When the arbitration
is successful the transmit logic asserts CNFG ISR TSE.
CNFG ISR TSE g::t.!S the output from the configuration/JSR mux onto the SBI. The configuration/ISR
mux selects the output from the configuration register due to the false state of ISR.
With the data in the configuration register transferred to the SB! bus, the SB! receiver state logic returns to
the "not busy" state.

6.4 INTERRUPT SUMMARY REQUEST (JSR)
The Cl780 port can request a CPU interrup1 for the purpose •>f having (he CPU run Cl780 service routines. Figure 6-9 is a block diagram of the logic involved in requesting the interrupt. Figure 6-10 is a flow
diagram of the ISR interrupt sequence.
A CPU interrupt SC(!uence is requested by INTR from the microcode, or by the assertion of the maintenance error flag (MTE). In either case, the DP asserts PORT l 'ffR to the SBI module to initiate the !SR
sequence.
?ORT INTR sets a t1ip-flop a~serting MIF (maintenance interrupt !lag). If the maintenance interrupt
function is enabled (MIE bit in the DP PMCSR ~cgister set), the !SR decode logic becomes ..:nabkd.

6~16

(FIG. 5-2)-- ··

·-I

!
!NIT&
SET PUP
RESTART
LOGIC
1-------.
(FIG. 611)

PORTINTR
(FIG. 5-11)-----lol

PRiORITY
• JUMPERS

PR! JMPR <1:0.>

(H)

""~

T REO <7:4>

!SR
1 - r - - - · - - - - - - - · · - ITO $81)
DECODE
(H)

L(FIG.5-2;5-11)

CLR SBI Rhl

RB <7:4>

1rno•ssn[_

(FiG. 6-C.I

R "IAG
NOTE:
LETTER DESIGNATIONS 11\ "~' ENTHESES
REFER TO ENGINEERING D:>AWINGS
CONTAINING CORRESP0NDING :..0GiC.

Figure 6·9

JSR Block Diagram

TAG
DECODE
(C)

JSR TAG

POK
--------1

(FIG. 6-61

Start

I
l,

Selects TR SE L code
tor configuration/ISR

mu.>c Signals transmit

logic to transmit TR
SEL code to SBI.

! CNFG ISA TSE
Gates YR SE L code
from confiqurationilSR

mux to SBJ. Host CPU
enters interrupt service
routine and asserts
PSRCR ACCESS.
Interrupt request
placed on SBI.

Data received from SBI.
1 ISR TAG
Data is an interrupt
summary read command.

Figure 6- l 0

JSk Flow Diagram

l CLA SBI REG

i MIF
Clears Cl780 interrupt
request st•tus.

Done

The ISR decode logic asserts one of four T REQ output lines to the SBI bus. The T REQ level asserted
depends on two priority jumpers that input PR! JMPR (1:0} into the decode logic.
T REQ (7:4} from the decode logic is placed on the SBI bus to request ~ervice from the CPU. The request
is at the priority level established by the priority jumpers. The CPU responds by placing an interrupt sum·
mary read command on the SBI. The associated tag is decoded to assert ISR TAG identifying the bus data
as an interrupt summary read command.
Parity is cheeked on the <:ornmand and P OK asserted if there are no parity errors.
Bits R B (7:4) of the interrupt summary read command is the request level now being serviced by the CPU.
The interrupt service request level is compared with the port request level (T REQ (7:4)). If ti1ey mat<:h,
ISR is asserted to the configuration/ISR mux and to the transmit logic (Figure 6-6 ).
ISR causes the configuration/JSR mux to select the TR SEL code generated by the TR jun:;iers.

ISR also notifies the transmit logic to transmit the TR SEL code to the SB!. The transmit logic responds by
asserting CNFG ISR TSE which gates the TR SEL (D,C,B,A) code from the configuration/ISR mux to
the SBI bus.
The CPU now generates a vector used to invoke the Cl780 service routine.
To clear the port of the interrupt state, the CPU asserts a. PSRCR ACCESS (port status release control
register) function. The address/function decoder outputs PSRCR ACCESS to the receive state iogic
(Figure 6-6). This causes the receive state logic to assert CLR SBI REQ which resets the MIF nip-flop.
Resetting the flii>-flop negates MIF and takes the port out of the interrupt request state.
6.5 INTITIAUZATION AND RESTART LOGIC
The initialization and restart logic (Figure 6-11) initiali1.es the port on system power-up and shuts down the
port when a power failute occurs within the Cl780 or the host system.
VAX·l 1/780 protocol requires that a power failure cause the assertion of SUPPLY ACLO followed by the
:\SSertion of SUPPLY OCLO (Figure 1-5). During power-up the reve.rse is true, that is SUPPLY OCLO
negates and then SUPPLY ACLO negates.
6.5.1 Start-Up Sequence
Figure 6-12 is a flow diagram of the start-up sequence. When power is applied to the port, both SUPPLY
ACLO and SUPPLY DCLO come true. SUPPLY OCLO asserts PS OC LO which clears the PUP and
PDN bits in the configuration register and sets the MIE bit in the PMCSR. PS DC LO also causes REG
CLR and LOGIC CLR to assert and reset the port hardware registers and logic circuits respectively,
LOGIC CLR also asserts UNINIT and places the port into the uninitialized state (Figure 5-12).
As power comes up SUPPLY OCLO negates followed by the negati< n of SUPPLY ACLO. ·rhe nev·:·m
of SUPPLY ACLO causes SET PUP to come true and set the PUP bit in the configuration register.
SET PUP also asserts Mlf (Figu1" 6·9) and, with maiatenance interrupts enabled (MIE bit in PMSCR
true), an interrupt sequene<; is initiated to the host CPU.
When the boot timer start-up delay has timed out (BTO) or the ho;t a~serts PICR WRT l'ia an unsolicited
SBI write operation /Figure 5-12), the port enters the initialized state and UN !NIT negdtes.

6-';9

_ _ _ ASSERT FAIL

T FAIL

.......;...--.~---~D

FAIL

:)Ji166
r:_1G.
(C)
'(

FORCE CLEAR

(FIG. 4-2)-----~

flUSSBIFA.~J

Jno;rnoM

:·~ 1j

(FROM r• <), _ ___;;,R...:U::..N:.:J.;..;A:...:M:.._....,..._ _ _ (flG 521

sen
LOGIC Cl.R
> - - - - ( F I G . 4-2;5121

PS DC LO

BUS SBI DEAD

_ _;A:...:S:::S:.:E:.:..R:...:T:...:D:..::E::..A:..::D::......_1--4"1 D

T DEAD

DEAD

DIS A DEAD

'\...:.R:.:E:.::G:..:C::.:L::.:R.:....s._ _ _ _...., (~ IG. 4 3; 5·2; 5-11)

SET
FF
(UI

_r-'-o---<MC

(,::'\ ______BUSSBI FAIL~
~

DLYD T DEAD

ACLO FAIL

~-----+(FIG. 69)

~-:..:::..;:;;:_.:..:..:;.:.::.__ _ _ (FIG. 4101

SUPPLY ACLO

SET PUP

CNfGA

~E~G

PUP

i--PD_N_..,...._ -

(FIG. 6 6)

(FIG. 1-51

--,...;..S.;;.ET_M_T_E_{FIG. 5-111

SUPPLY DCLO

--0

I [>o

UNINIT _ _ _ _ _ __._
(FIG. 5-12)--_::;....;__;_

'"°"

SET PON

~'o"' ©

(FIG. 4 · 2 1---=---=~------------'

"°''°

PF DISABLE OB

LETTER DESIGNATIONS 1~; PARENTHESES REFER TO

ENGINEERING DRAWINGS CONTAINING CORflESPONDllKi LOGIC.

Figure 6-l l

lnitializ.ation and Restart Logic

Start

Power on

l SUPPLY ACLO
t SUPPLY DCLO

I PSDC LO

PON

I MIE

PUP

t LOGIC CLR

i SUPPLY ACLO

1 SET PUP

I Pt;P

Initiates interrupt
sequence to host CPU.
rK-99!.4

Figure 6-12 Start-lip Sequence

6-21

6.5.2 Power-Fail Seque11<;e
Figure 6-13 is a flow diagram of the power-fail scqu..:nce. When a power failure occurs within the Cl780.
SUPPLY ACLO comes true and asserts ACLO FAIL to the CS bran.::hing logic. ACLO FAIL is also
Jssertcd by a power failure within the host CPU which causes BUS SBI FAIL to as~ert on the SBI.
If the port is initialized (UNINIT false), ACLO FAIL causes t11c microcode to branch to a power-fail
routine. The power-fail routine causes the port to save current information so that operation may be
resumed when power returns.

The microcode power-fail routine asserts UP PDN. With the port in the initialized state (UNINIT false).
UP PDN asserts SET PDN to the configura•.ion register which reset~ the PUP bit and sets the PON bit in
the register. PDN asserts SET MTE which then asserts MTE in the DP module. MTE places the port in
the uninitialized state (figure 5-12), thereby stopping the microcode. MTE also asserts PORT INTR which
initiates an interrupt sequence to the host CPU (Figure 6-9).
If a genuine power interruption is occurring, SUPPLY ACLO wilt still be true and if this is a port power
failure, SUPPLY DCLO will assert. When SUPPLY DCLO comes true it asserts PS ex: LO. PS DC LO
asserts REG CLR and LOGIC CLR thereby clearing all the port hardware registers and logic circuits.
If the power failure occurred in the host CPU, BUS SBI DEAD will be asserted on the SB!. BUS SBI
DEAD asserts REG CLR and LOGIC CLR to reset the port registers and logic circuits,
If only a transient AC power dip occurred. SUPPLY ACLO may negate before SUPPLY DCLO asserlS,
hence the port registers and logic circuits are not cleared. In this case, the negation of SUPPLY ACLO
causes SET PUP to come true which sets the "UP bit and resets the PDN bit in the configuration register.
Resetting the PDN bit negates SET MTE and MTE which allows the port to enter the initialized state
when the boot timer has timed out (BTO) or the host asserts PICR WRT via an unsolicited SBI write
operation (Figure 5-12).
If the port is not initiali1_ed (l.'NINIT true) when SUPPLY ACLO fir.;t asserts, the same basic sequence is
executed except that the hardware - not the microcode - powers down the port. As shown in F:gures 6-1 I
and 6-13, the assertion of ACLO FAIL negates SET PUP. With UNINlT true, the negation of SET PUP
causes SET PON to assert to the configuration register. SET PDN sets the PDN bit and reset~ the PUP bit
in the register.

PDN asserts SET MTE which then asserts MTE in the DP module. MTE asserts PORT INTR which
initiates an interrupt sequence to the host CPU.
The power-fail sequence then completes as shown in Figure 6-13.
As illustrated in,Figurc 6-11. FORCE CLEAR (asserted by MCLR from the microword or by MIN from
the PMCSR) also resets the CI780 by asserting REG CLR and LOGIC CLR.
R UNJAM from the SB! clears the port logic while leaving 1.he register wntents intact for diagnostic
examination.

Powe.'· failure in

Powe.r fa\rure
in port

host CPU.

YES

l
NO

I SET PUP
M icroc~e branches to
POV-~~:- fail :outine.

Power tail routine saves
current in formation.

~?UP

BUSSBi DEAD

i REG CLR

BTO
or
P!CR WRT

t PON

l PUP

• LOGICCLR

Do-nt
~ UNINIT
Port enter$ uninitialized
st.ate, Microcode stops
running .

T PORT INTR
Initiates interrupt
seQuence to host CPU.

.figure 6-13

Power Fail Sequence

1>·23

6.S.3 Mlhlteauce Mode
In the maintenance mode, the Cl780 port can be reset from another node by means of a reset packet. The
remote node sends the reset packet to the Cl780 causing the port microcode to assert ASSERT f AIL and
PF VLD (power-fail valid) (Figure 6-11). A~ERT FAIL conditions a fail flip-flop to set while PF VLD
enables the Tl clock to set the nip-flop. Setting the fail flip-flop asserts T FAIL which in tum asserts BUS
SBI FAIL onto the SBI (Pf DISABLE 08 false). BUS SDI FAIL functions to initiate a power-down
sequence within the host.system.
The microcode then asserts ASSERT DEAD and PF VLD which similarly resuits in the assertion of T
DEAD and then BUS SDI DEAD on the SDI. BUS SDI DEAD completes the power-down sequence within
the host system.
Note that T DEAD also asserts DIS R DEAD (disable receive dead). DIS R DEAD inhibits BUS SBI
DEAD from clearing the port registers and logic. Thus the port is still able to function while the host
system is powered down.
When T DEAD negates, DIS R DEAD is held true by DLYD T DEAD for one clock pulse after T DEAD
negates. This insures that BUS SDI DEAD has negated before DIS R DEAD goes false, and prevents BUS
SBl DE AD from possibly clearing the port registers and logic circuits.

Tl)C microcode then asserts PF VLD with ASSERT DEAD negated resulting in the resetting of the dead
fli('-flop and the negation of T DEAD and BUS SDI DEAD. With BUS SDI DEAD false, the host system
attains a partial powered-up state.
The host system remains in the partial powered-up state until the remote port sends a start packet. The
start packet causes tile port microcode to assert PF VLD with ASSERT FAIL negated, thereby resetting
the fail flip-flop and negating T FAIL and BUS SBI FAIL The host system will now complete its powerup.
When the PF DISABLE 08 bit in the configuration register is true, maintenance diagnostics can test the
microword ASSERT FAIL and ASSERT DEAD bits without affecting the SBI.

6-24

APPENDIX A
Cl780 MNEMONIC GLOSSARY

ACK
ALU
AR
ARB
ARBC

AX
BM

Byte m<lik
Branch
Busv
timeout

BSY

Boot

BTO
I<\

'O
,

Acknowledge
Arithmetic logic unit
ACK receive (state)
Arbitrate
'.rbitration counter
r.CK transmit (state)

.. ~,.

CNFGSTB
CRC
CRD

':'SA

LSPE
CXTER
CXTMO

Command/address
Command address timeout
C-Omputer interconnect (formerly JCCS and IPA)
'::onfirm
Configu, -llOn strobe
Cyclic redundancy check
Corrected read data
Control store
Control store address
Control store parity error
Command transmit ~rror
Cr nand transmit timeout

DSTCMP

Dis..ole receive duid
Decoded file enable
Done
Data path (module)
Decoded push/pop
l::>cstination compare

'aECL

Emitter coupled logic

FCN
FE

Function
File enable
Fault

D.ISR DEAD

DFE
DN
DP

DPUP

FLT

IB
IBDST
IBSRC

JCCS

Internal bus
IB destination
IB source
lntercomputcr rnmmurncation,o W'itch (sec Cl)

JNTR
IPA
IPE
!SR

Intern; pt
Interprocessor adapter (sec ('I)
Input parity error
lr.t::rrupt summary request

JSR

Jump to subroutine

LS
LSB

Local store
Least significant bit
Local store parity error
Less than

LSPE
LT
MADR
MCLR
MD
MDATR
ME
MIE
MIF
MIN
MJSCCNTL
MLOAD
MLOOl:MR
MSB
MSE
MTD
MTE
MXT

l\fointenance address register
Maintenance dear
Miscellaneous data
Maintenance data register
Manchcsterencoaed
Maintenance interrupt enable
Maintenance interrupt flag
Maintenance initialize
Miscellaneous control
Maintenance load
Maintena.:<:e loop
Message receive (state)
Most significant bit
Memory system erro;
Maintenance timer di!>:!ble
Maintenance error
Message transmit (state)
Multiple transmit

NACK

Negative acknowledge

OPE

Output parity error

PAL
PB
PC

Program~ble array logic

PDN
PE
PFVLD

PIC'R
PMCSR
PMTCR
PROM
PROP
PS/\

PSR

PSRCR
PUP
PUP

Packet buffer (mooule)
Program counter
Power-down
Parity error
Power fail valid
Port mitialize control register
Port maintenance control/status register
Port maintenance timer control register
Programmable read-only memory
Propagate
P., igrammable starting addre;s
Port status register
Port status release control register
Push/pop
Power-up

RAM
RBPE
RBLiF
RCAR

RD
RDS

RDTO
RDIP

RDXPTL
RDXPTQ
RSVD
RTS
SBI

S/D
SELCC

SEQ
TACK
TBLiF

TSE
HL

UNINIT

Random access mcmorv
Receiv'° buffer parity ciror
Receive buffer
Receive carrier
Read data
Read data substitute
Read data timeout
Read data in progress
Read data expected longword
R_.:id data expected quadword
Reserved
Return from subroutine
Synchronous backplane interconnect
Source/destination
Select condition code
Sequencer
Transmit ACK
Transmit buffer
Transfer request
Transfer enable
Transistor-transistor logic

URD

Uninitialized
Unexpected read data

VCDT
VRD

Virtual circuit descriptor table
Valid receive data

WACK

'.'.'.:lt for ACK
v:.:ie data
Write data in progres.~
Wrong parity
Write
Write sequence
External bus

WD
WDIP
WP

WRT
WSQ

XBUS

APPENDIXB
FLOW ·11AGRAM SYMBOLS

The flow diagram symbols used in this manual are defined i.n Figure B- l. Signal mncmunics ;ire shc1wn in
upper case. All other flow diagram text is in lower case.

X ·~ OESCHIPTION OF AN EVENT OR ACTION IU1WER CASE).

IF COND:T10N OR SIGNAL IS TRL!E FLOW
FOLLOllE> YE.S BRANCH, OTHERWISE FLOW
FOLLOWS NO BRANCH.

6
CJ
(..______,.)

ON PAGE CO'INECTOR.

OFF PAGE CONNECTOR.

BEGINNING OR ENDING POiNT OF A FLOW
DIAGRAM.

Figure B-1

flc•w Diagram Symbol>

SEi NEXT FRl;,,"18

FOR LARGER ART

B-i

X ~DESCRIPTION OF AN EVENT OR ACTION (LOWER CASE).

'"'

5'GNAI ' ' " " '5 ASSCR'rn 1ue.rn " " '

+_PW-~

..__ _

...
R-F_L_ __,, THE SIGNAL PWRFL IS NEGATED.

_L_
~

FLOW DELAYED
UNTIL CLK ASSERTS.

IF CONDITION OR SIGNAL IS TRUE FLOW
FOLL0"'5 YES BRANCH. OTHERWISE FLOW
FOLLOWS NO BRANCH.

ON PAGE CONNECTOR.

(

)

OFF PAGE CONNECTOR.

BEGINNING OR ENDING POINT OF A FLOW
DIAGRAM.
TK .6(n l

Figure B-i

..low Dia~::.'"am Symbols

APPENDIXC
HARDWARE REGISTERS

A.ppendix C is a description of four hardware registers that can be accessed by the port software for maintenance purpo6CS. The registers described are:
I.
2.
3.

MADR - Maintenan<'(; Address Register
MDA TR - Maintenance l ta Register
PMCSR - Port Maintenance Control/Status Register
CNFGR - Configuration Register

C.1 MADR - Mahrteunce Address Register
figure C-1 mil.Strates the function of the MADR bits. The register address = XXXXXO 14 (hex). MADR
contains the address of the control store location to be accessed. It is read or written only in the uninitial-

ized stat·.:.
Refer to ."igure 4c1 and Paragraphs 4.1, 4.6.l, and 4.7 for a discussion of MADR operation.

31
-

Figure C-l

1\00 )H

PRG'41

1400if~

;;<A.Ml

~OOB'·F

RA.YI

1; ! I i I I I

Maintenance Address Register (MADR) Bit Fields

SEE NEXT FRAME
FOR LARGER AR'r

C-!

I i

SELECTS THE MICROWORD
SEGMENT TO BE READ
FROM OR WRITTEN •NTO CS.

0 "<31:0<r>
1 ~ <.47 32··

SELECTS ll( BAN~: CF CS

Figure C-1

Al'

A 10

0
0
I

rQ00.3FF

,·400..1~F RA!.'}
i800 BFF RA.Mi

Maintenance Address Register {MADR) Bit Fields

--·

I'.

8Ai'OK SE:..ECTED
PHOM\

SELECTS MICROWORO
w1n:1N IK BANK.

C2 MOATR - Mai11teun~e Data Register

Figure C-2 illustrates the MD/\ TR bits. The register address= XXXXXO! S (hex). MDA TR does not exist
as a physical register. A read or write of MDA TR will read or write the microv.ord in the control ~tore
location specified by the address in the MADR. Wher. MADR 12 = 0, MDA TR (31 :00) contains microword bits (3 l :OO>. When MADR 12 = I, MDA TR {15:00) contains microword bits {4 7:32) (MD ATR
(3J:lti) are all Os). MDATR is read or wriu~n only in the uninitialized state.
Figure 4-4 and Table 4-1 def:ne the microword bits. Refer to Figure 4·2 and Paragraph 4.4 for a disrnssion
of reading and writing the control store.

Figure C-2

Maintenance Data Register (MDATR l Bit field

SEE NEXT FRAM:':
FOR LAR.GER AR':'

DATA BITS <3Hlff·'
TK-9911

Figure C-2

Maintenance Data Register (MDATR) Bit Field

C-2

C.3 PMCSR - Port Maintenance Control/Status Rt>gister
hgurc C-1 illustrates the function of the PMCSR bits.
f'he register address = XXXXX004 or XXXXXO i 0. PM CSR contains !XJrl hardware error flags, hlerrupt bits, and initialii.ation control bits.
A description of the PMCSR bits is given in Paragraph 5.2.3 and Table 5-J.

!',

f,IE:

{)';'.,

f.:2

0('

L..~~::::_-::::::::_-::_-_._-·::::::::_-_-_-_-~-----=-·---~~~~~-'~1..-~.._,.~....~........_,...__,...,...,..._,,_._.,....~.._,~,...~......~
!>.11,~!'...... _J
E>i~C•R

GO"IHWL S1QRf
fkFOR

P~.>i:r;·,,

ii,

1
1

__J

'""A•. 5'0A[
PAR\"")' 01.ROP.

Ij I
r

R~cuvE e~:ntR __J

f>AAIT"' (RROR

'}>tANSi.llr D.ATA
i'A~IT'!" ERROR

I
_j

!NPU~ PARITY _J
ERR~;"!

l)UTf>;!T f'AP.1!-'I

ERR.OH
1FIAN$.liilli BU!'!'(!':

f'A!Onv ERP.OR
1..lr-.:>">ITIAU.?"fi)
ST.l\H

__!

PHOG'<AMMAB:.,£- __;
STAr--'fi'.;G Ai•.X.lR
Fit:SE RVED

W~Ofli\3

PA~IT\

Y.A!i'('l'E'-ANCF.
__j
1~, 1, i";h1PT i:NiA.6~.F.

Y-1\INHNASCf _j
! !MfR o:sA~Lf
MAINH,,.ANCl
1~._1n•Ai._l;7f

Figure C·.3

SEE NEXT FR.l\.'lf;
F'Of".

LA!H~ ER

ART

Pi>rt Maint"nancc Control/Status Rcgi,:tcr ( PMCSR'1
Bit Fields

PARITY
ERROR
CONTROL STORE
PARITY ERROR

·j

LOCAL STORE
PARITY ERROR

RECEIVE BUFFER
PARITY ERROR

TRANSMIT DATA
PARITY ERROR

~~~ci:ARITY
OUTPUT PARITY
ERROR
TRANSMIT BUFFER
PARITY ERROR
UNINITIALIZED _
STATE
PROGRAMMABLE
STARTING ADDA.
RESERVF.O
WRONG
PARITY
MAINTENANCE
INTERRUPT FLAG
MAINTENANCE
_J
INTERRUPT ENABLE
MAINTENANCE
TIMER DISABLE
MAINTENANCE
INITIALIZE

Figure C-3

Port Maintenance Control/Status Register (PMCSR)
Bit Fields

C-3

C.4 C'NFGR - Configuration Register

Figure C-4 illustrates the function of the CNFGR bits.
The register addn:ss = XXXXXOOO. CNFGR contains SBI fault bits. and statu;, and error bit-; for an SBI
transfeL It also contains the C1'!80 adaptor code. Refer to Paragraph 6J for a discussion of reading and
writing ti1c CNFGR.
Table C-1 describes the CNFGR bit functions.

l
(;Qt.IJ.!A~D TP~!"f·J~!T
1!¥f{)'..•~

L_ !fiA"liSll.~!T
tAfl

l'fiA"'!i';,7
t',-lJ

"Ult:•';; ;-U,"l'.)1.1;1
i ..-\L,.1

'..'•\i(•.r(C'.G ",f4'.)
,)J,. TA f ..,,i_,~ 1

-... c:;r~ ~-£ --w. '1(f
•0

".!.!lT

Figure C-4 Configuration Register (C"IFGR) Bit hdds

SEE NEXT FRAME
(

..... '

oI o

o :o

()

' ,I L
'

LL
i

L
I

IL
.L
1

PO\HRU"

POWER DOWN

TRANSMIT
FAULT

MULTIPLE TRANSMIT
FAULT

\.JNO'."ECTED READ

LL
!

DAI"'. FAULT

WRITE

FAUL f

sea~n:NcE

PARITY
FAULT

Figure C-4

Configuratior. Register (CNFGR) Bit Fields

C-4

C ?80 :!'1 ADAPTER CODE

. I

READ DATA
SUBSTITUTE

READ DATA
TIMEOUT

i L

COMMAND TRANSMIT
ERROR

COMMAND TRANSMIT
TIMEOUT

IL'

CORRECTED
Rf,\;) OAH,

POWER FAIL
DISABLE

L_ TRANSMIT

LTRA::~,:
FAIL

()

Table C-1
Bit

Mnemonic

CNFGR Bit~

Description
Bits (31 :26) .ire the SBI fault bits. They arc set
when the p•<'t detc..:ts the rcspcuivc fault con<li·
tion as described below. The fault bits an· read

31 :26

t)!lJ}'.

.JI

PAR FLT

Parity fault: Set when the port deiccts an SBI par·
ity error.

WSQFLT

Write sequcnc' fJu!t: Set when the port rccci1es a
write mask command that is nat immcdi,\tcl1 fol·
lav.ed by the expected write data.
·

URD FLT

L'ncxpected read dat.J fault: Set when the port
receives re.id data t.ut did not issue a read
command.

I'his bit is reser\'ed und reJd as 0.

MXTFLT

Multiple transmit fa uh: Set "hen the ID bits
tr~nsmitted by the port do ll<ll match the ID bits

received back from the SBI
26

XMT FLT

Transmit fault: Set if the Cl780 was the SB!
nexus that caused the SBI FAULT line to assert

2~;_,:4

Reser\'ed. Read as Os

pl):-.;

Power down. Set if the pori i~ powering down
PON i; set b' the as.1ertwn or Sl!PPL.Y ACLO ii'
the port is in ·the unini1ia!ic.ed ~late, otherwise it i>
set by the microcode vie: the PDN bit. The PDN
bit is. ,Jeared by writing a I ti.> it or t .' selling the
PLP bit.

PtP

Pswer up: Set by th1.'. negation of SUPPLY

~-·

ACLO. The PUP bit 1, ..:It-med by writing ii l tu it
or ~> >('ling the PDN bi!.
21

()

Reserved. Rc:1d iJ> ti

C\TMO

Cumm;rnd tran~mi1 ~imcout: Set when t~t: t'lol.:rt
initia:cs :;n SB! tra11sfcr and docs not rc<.:ci•c rn

ACK ar ,,;.,or C00ilfl'1:Jtion within l O? micrc»
\.C1.'0'!ds T 'K t;;m·>:·td t:ll·riod is ~elect a bk h\ back·
plane jurn(X'.''·
·
·
J9

---·--...

Re.id d:nn :i:nt: t l. S.:1. "her; the port initiate; ,;n
SB! read tr:n:>f,:r :1:1d re.id d.1ta is nl'l return~d
'"': 1
~----

hin 102 i-:·;'.<.'i»~~Pnd~

l able C~I C"IFGR Bits (f on1i
l)t>scription

Bit
IX

CXTER

c,-,mmand tran,m1t crru·: S<-1 when the P"rt
rt:\.:Ci\'C''- an 1.".rflH' ~Vnfirmillion

;I\

r<.':~f'".Jll~C lO ;cl

port initiated SBI command tran>mt,,inn
17

RDS

Rc,1d data sub-tirntc:· Set "hen the f''r1 re'«~,,_.,
an RDS (uncorrectable rc;id d&ta) confirmation in
respon><· w a port in111atcd SB! read comm.ir.d

CRD

(«)rrectcd re.id Jata: Set when the port receive,; ·'
CR[) ~·onfirmmior. i:c 'C'i"''nsc to a port initincd
SBI r~'1d rnrnrn;md

Rei.erved. Rc..id a; Ci:-.

15: 1 I
IO

TF.\IL

Tramrni1 fail: Se.t b) th~ rnKr.:..:1xk through the
misc'elluneous contrul field when PFV and
l\SSERT FAIL are true.
Transmit dead: Set by the minncodc through the
mi:-<:cliJneous ·:ontrc'l field "·hen PF\' Jnd
/\SSFRT DEAD are true

PF DISl\BLE

Power fail dis;;bk: When >cl. th<'. SB! !':\IL and
SBl DEAD drivcN to the SB! are disabled.

·\d;ii'(or ,·,xJe: These b;:s rnntain the Cl"'ilfl SBI
a.dapte>r ,;ode.