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EK-640EA-HR-001

July 1989

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Document:	VAX 6000-400 Mini-Reference
Order Number:	EK-640EA-HR
Revision:	001
Pages:	102
Original Filename:	EK-640EA-HR-001_VAX_6000-400_Mini-Reference_Jul89.pdf

OCR Text

VAX 6000—400

Mini-Reference

Order Number: EK-640EA-HR-001

VAX 6000—400 Mini-Reference

Order Number EK—640EA—HR—001

This manual supplies easy-to-access key information
on VAX 6000—400 systems.

digital equipment corporation
maynard, massachusetts

First Printing, July 1989
The information in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation.
Digital Equipment Corporation assumes no responsibility for any errors that may appear in
this document.
The software, if any, described in this document is furnished under a license and may be used
or copied only in accordance with the terms of such license. No responsibility is assumed
for the use or reliability of software or equipment that is not supplied by Digital Equipment
Corporation or its affiliated companies.
Copyright ©1989 by Digital Equipment Corporation.
All Rights Reserved.
Printed in U.S.A.
The following are trademarks of Digital Equipment Corporation:
DEBNA
DEBNI
DEC

PDP
ULTRIX
UNIBUS

DECnet

VAX

DECUS

VAXBI

VAXcluster
VAXELN
VMS
XMI

RASAAL

FCC NOTICE: The equipment described in this manual generates, uses, and may emit
radio frequency energy. The equipment has been type tested and found to comply with the
limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which
are designed to provide reasonable protection against such radio frequency interference when
operated in a commercial environment. Operation of this equipment in a residential] area
may cause interference, in which case the user at his own expense may be required to take
measures to correct the interference.

Contents
Preface

Chapter 1

Console Operation

Chapter 2.

Self-Test

Chapter 3

Address Space

3.1
3.2

How to Find a Register in XMI Address Space ...........
How to Find a Register in VAXBI Address Space..........

Chapter 4
4.1
4.2
4.3
4.4
4.5

KA64A CPU Module Registers

KA64A Internal Processor Registers .............000005
KA64A Registers in XMI Private Space.................
KA64A XMI Registers .............. cc ee eee eee eens
Machine Checks.............. cc cece eee e eee eee tees
Parse Trees .......... ccc ce eee eee eee eee eee

Chapter 5

MS62A Memory Registers

Chapter 6

DWMBAAdapter Registers

Index

3—5
3-6

4—2
4—14
4—23
4—27
4-30

Examples
2-1. Sample Self-Test Results .............. cece eee eee

2-1

Figures
1-1 International and English Control Panels ...............
1-2 BOOT Command Syntax ...... 2... 0. cece ees
2-1 KA64A LEDs After Self-Test ........ 0.0... 0. cee
3-1 VAX 6000—400 Slot Numbers ............... 2... ce eee
3-2 XMI Memory and I/O Address Space................208.
3-3 XMI I/O Space Address Allocation ................0000.
4—1
Machine Check Error Summary Register (MCESR).......
4-2
Accelerator Control and Status Register (ACCS) .........
4—3
Console Saved Program Counter Register (SAVPC) .......
4—4
Console Saved Processor Status Longword (SAVPSL)......
4-5
Translation Buffer Tag Register (TBTAG)...............
4-6
I/O Reset Register (IORESET) ............... 00000 0ee
4-7
Translation Buffer Data Register (TBDATA).............
4-8 System Identification Register (SID) .................5.
4-9
Backup Cache Backup Tag Store Register (BCBTS).......
4-10 Backup Cache Primary 1 Tag Store Register (BCP1TS) ....
4-11 Backup Cache Primary 2 Tag Store Register (BCP2TS)....
4-12 Backup Cache Refresh Register (BCRFR)...............
4—13 Backup Cache Index Register (BCIDX).................
4-14 Backup Cache Status Register (BCSTS)................
4—15 Backup Cache Control Register (BCCTL)...............
4-16 Backup Cache Error Address Register (BCERR)..........
4—17 Backup Cache Flush Backup Tag Store Register (BCFBTS).
4—18 Backup Cache Flush Primary Tag Store Register (BCFPTS)
4-19 Primary Cache Tag Array Register (PCTAG) ............
4—20 Primary Cache Index Register (PCIDX) ................
4—21 Primary Cache Error Address Register (PCERR).........
4-22 Primary Cache Status Register (PCSTS) ...............
4-23 Control Register Write Enable Register (CREGWE).......
4-24 RSSC Base Address Register (SSCBAR)................
4-25 RSSC Configuration Register (SSCCNR) ...............

1-2
1-8
2-4.
3-1
3-2
3-3
4—5
4—5
4—§
4-6
4—6
4—7
4—7
4—7
4-8
48
4-8
4—9
4-9
4—10
4—10
4—10
4~-11
4-11
4—11
4—12
4—12
4—13
4—15
4—15
4—16

RSSC Bus Timeout Control Register (SSCBTR) ..........
RSSC Output Port Register (OPORT)..................
Control Register 0 (CREGO) .......... 0. ce eee eee
Control Register 1 (CREGI1) ............ 2. eee eee wees
RSSC Input Port Register (IPORT)................006.
Control Register Base Address Register (CRBADR) .......
Control Register Address Decode Mask Register (CRADMR)
EEPROM Base Address Register (EEBADR) ............
EEPROM Address Decode Mask Register (EEADMR) .....
Timer Control Register 0 (TCRO) ...........Lee ee eae
Timer Interval Register 0 (TIRO) ...............00008:
Timer Next Interval Register 0 (TNIRO)................
Timer Interrupt Vector Register 0 (TIVRO)..............
Timer Control Register 1(TCR1) .................200..
Timer Interval Register 1 (TIR1) .............. 202 aee
Timer Next Interval Register 1 (TNIR1)................
Timer Interrupt Vector Register 1 (TIVR1)..............
Interval Counter Register (SSCICR)...............200.8:
Device Register (XDEV)............... eee ee eee
Bus Error Register (XBER) ............. 2.0 eee eee eeee
Failing Address Register (XFADR)..............002 ee:
XMI General Purpose Register (XGPR) ...............4..
KA64A Control and Status Register (RCSR) .............
The Stack in Response to a Machine Check..............
Machine Check Parse Tree.......... 0.00 cece cece ees
Hard Error Interrupt Parse Tree ..............200eeeee
Soft Error Interrupt Parse Tree ...... Lecce eee eueueeees
Device Register (XDEV).......... 0. cece eee eee ees
Bus Error Register (XBER) ............. cece eee eeaee
Starting and Ending Address Register (SEADR)..........
Memory Control Register 1 (MCTLI1)................055
Memory ECC Error Register (MECER) .................
Memory ECC Error Address Register (MECEA) ..........
Memory Control Register 2 (MCTL2)...............200%
TCY Tester Register (TCY).... 2.0.0... 0... cee ec ee eee
Interlock Flag Status Registers (IFLGn) ................

4—16
4—17
4—17
4-18
4—18
4—19
4-19
4—19
4—19
4—20
420
4—20
4—21
4—21
4—21
4—22
4—22
4—22
4—23
4—24
4—25
4—26
4—26
4—27
4-30
4-33
4—35
5-2
5—2
5-3
5-3
5-4
5—4
5—5
5—5
5-6

6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16

Device Register (XDEV)........... 0. ccc cece cee eee
Bus Error Register (XBER) ........ 0.0... cc cece eens
Failing Address Register (XFADR)..............0 00000
Responder Error Address Register (AREAR) .............
DWMBASA Error Summary Register (AESR).............
Interrupt Mask Register (AIMR) .................0000.
Implied Vector Interrupt Destination/Diagnostic Register
(AIVINTR) .. 0... ccc cc cc ee eee nett eens
Diag 1 Register (ADG1) ........ 0... ccc eee ee ees
Control and Status Register (BCSR) ...................
DWMBA/SE Error Summary Register (BESR).............
Interrupt Destination Register (BIDR)..................
Timeout Address Register (BTIM) .................000%
Vector Offset Register (BVOR) ........... 0.00 cee ee eens
Vector Register (BVR) ........... ccc cee ee eee eee
Diagnostic Control Register 1(BDCR1).................
VAXBI Device Register (DTYPE) ................ 00 cues

6-3
6-3
6—4
6-4
6—5
6-6
6-6
6—7
6-7
6-8
6-8
6-8
6-9
6-9
6-9
6-10

Tables
1-1
1-2
1-3
1—4
1—5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
2-1
2-2
3-1
3-2
3-3

Upper Key Switch .............. eee eee eee eee
Lower Key Switch ............ cece ee ee eens
Restart Button... .... ee ee ee
Control Panel Status Indicator Lights ..................
Console Commands and Qualifiers.................000%
Console Control Characters ............ 00. e eee eee
Sample BOOT Commands ................. 0c eeeeeee
BOOT Command Qualifiers ................. 000 cee eee
R5 Bit Functions for VMS .......... 0... eee eee eee
R5 Bit Functions for ULTRIX ............ 0... 0. cee eee
Console Error Messages Indicating Halt ................
Standard Console Error Messages ............. 0.00000:
System Configuration for Sample Self-Test ..............
TK70 Light Summary ................ cece ee ees
XMI Addressing ............ 0. ccc eee eee ee eee
VAXBI Nodespace and Window Space Address Assignments.
VAXBI Registers ............. ccc eee eee ete eeeee

1-3
1-3
1-3
1—4
1—4
1-7
1-9
1-9
1-10
1-10
1-11
1-12
2-3
2-5
3-4
3-7
3-8

4—1
4-2
4-3

4-5
5-1
6-1

Types of Registers and Bits ............ 0. cc eee ee eee
4—1
KA64A Internal Processor Registers ............0200005
4—2
KA64A Registers in XMI Private Space................. 4—14
XMIRegisters for the KA64A CPU Module.............. 4—23
Machine Check Parameters ...........000 cee eeeeecees 4—28
MS62A Control and Status Registers...............2020.
5—1
DWMBARegisters ........... 0. cee cece ee cette eens
6-2

vil

Preface
Intended Audience
This manual is intended for the system manager and programmer.

Document Structure
This manual hassix chapters:
Chapter 1—Console Operation
Chapter 2—Self-Test
Chapter 3—Address Space
Chapter 4—KA64A CPU Module Registers
Chapter 5—MS62A Memory Registers
Chapter 6—DWMBAAdapter Registers

VAX 6000—400 Documents
Documents in the VAX 6000—400 documentation set include:
Title

Order Number

VAX 6000-400 Installation Guide

EK-640EA-IN

VAX 6000-400 Owner’s Manual

EK-640EA—OM

VAX 6000-400 Mini-Reference

EK-640EA—HR

VAX 6000-400 System Technical User’s Guide

EK-640EA—-TM

VAX 6000-400 Options and Maintenance

EK-640EA—MG

VAX 6000 Series Upgrade Manual

EK-600EA—UP

Associated Documents
Other documents that you mayfind useful include:
Title

Order Number

CIBCA User Guide

EK-—CIBCA-—UG

DEBNIInstallation Guide

EK-—DEBNI-IN

Guide to Maintaining a VMS System

AA-LA34A-TE

Guide to Setting Up a VMS System

AA-LA25A-TE

HSCInstallation Manual

EK—HSCMN-IN

H4000 DIGITAL Ethernet Transceiver Installation
Manual

EK-—H4000-IN

H7231 Battery Backup Unit User’s Guide

EK-H7231—UG

Installing and Using the VT320 Video Terminal

EK-VT3820—UG

Introduction to VMS System Management

AA-LA24A-TE

KDB50 Disk Controller User’s Guide

EK—KDB50-UG

RA90 Disk Drive User Guide

EK-—ORA90—-UG

RV20 Optical Disk Owner’s Manual

EK-—ORV20—-OM

SC008 Star Coupler User’s Guide

EK-SC008-UG

TK70 Streaming Tape Drive Owner’s Manual

EK-—OTK70—-OM

TU81/TA81 and TU81 PLUS Subsystem User’s Guide

EK-TUA81—UG

ULTRIX-32 Guide to System Exercisers

AA-—KS95B-TE

VAX Architecture Reference Manual

EY-3459E—DP

VAX Systems Hardware Handbook — VAXBI Systems

EB-31692—46

VAXBI Expander Cabinet Installation Guide

EK-VBIEA-IN

VAXBI Options Handbook

EB-32255—46

VMSInstallation and Operations: VAX 6000 Series

AA-LB36B-TE

VMS Networking Manual

AA-—LA48A-TE

VMS System Manager’s Manual

AA-LAO0A-TE

VMS VAXcluster Manual

AA-—LA27A-TE

Chapter 1

Console Operation
This chapter provides reference information for working at the console
terminal.
Terminal setup characteristics:
e

The maximum recommendedbaudrate is 1200.
If the console is not responding, you may needto press the Break key
to increment the baudrate.

Terminal characteristics should be set to the following: eight bits, no
parity, one stopbit.

Console Operation

1-1

Figure 1—1:

International and English Control Panels

FRONT
EEPROM

Standby

[___]

Run

Enable

[_]

Battery

Secure

[.__]

Faut

Update
Halt

Auto Start [——] Restart

msb-0037-89

1—2

VAX 6000-400 Mini-Reference

Table 1—1:

Upper Key Switch

Position

Effect

O (Off)

Removesall power, except to the battery backup unit.

Nolight

Standby

Supplies power only to memory and blowers.

Red

Enable

Supplies power to whole system; console terminal is enabled. Used for console mode or restart, and to start
self-test.

Yellow

Secure
(Normal Position)

Prevents entry to console mode; position used while machine is executing programs. Disables Restart button and causes the lower key switch to have the effect of Auto Start, regardless of its setting.

Green

Table 1-2:

Light Color

Lower Key Switch

Position

Effect

Update

Enables writing to the EEPROM on the boot processor. Halts boot processor in console mode on powerup or when Restart button is pressed. Used for updating parameters (such as the terminal] characteristics and boot specifications) that are stored in each processor’s EEPROM(upper key switch must be set to Enable). Prevents an auto restart.

Red

Halt

Prevents an auto restart if a failure or transient power outage occurs.

Yellow

Auto Start
(Normal Position)

Allows restart or reboot.
tion of the system.

Green

Table 1-3:

Light Color

Used for normal opera-

Restart Button

Upper Key Switch

Lower Key Switch

Restart Button Function

Enable

Update or Halt

Runs self-test, then halts.

Enable

Auto Start

Runs self-test, and attempts a restart.
If the restart fails, then it reboots the operating system. If the reboot fails, contro] returns to the console.

Standby

Any position

Does not function.

or Secure

Console Operation

1-3

Table 1—4: Control Panel Status Indicator Lights
Light

Color

State

Meaning

Run

Green

System is executing operating
tions on at least one processor.

Off

System is in console mode, is set to Standby, or is
turnedoff.

Battery backup unit is fully charged; normal operation.

Flashing
1 x/sec

Battery backup unit is charging.

Flashing
10 x/sec

Battery backup unit is supplying power to the
system.

Off

Either system does not have a battery backup unit or
the battery backup unit is turnedoff.

Self-test is in progress. If light does not turn off, system has a hardware fault. See Chapter 6 for selftest information.

Off

Self-test has completed, or the system is turned off.

Battery

Green

Fault

Red

Table 1—5:

system instruc-

Console Commands and Qualifiers

Command and
Qualifiers
BOOT
/R3:n /R5d:n
[XMI:n /BI:m
/NODE:n
CLEAR EXCEPTION

Function
Initializes the system,
gins the boot program.

Cleans

ters.

error

causing a self-test,

state in XBER and

and be-

RCSR regis-

CONTINUE

Begins processing at the address where processing wasinterrupted by a CTRL/P console command.

DEPOSIT
BIG A A
IN (PP N /W

Stores data in a specified address.

EXAMINE
BIG A A
IN (PP N /W

Displays the contents of a specified address.

1—4

VAX 6000—400 Mini-Reference

Table 1-5 (Cont.): Console Commandsand Qualifiers
Command and
Qualifiers

Function

FIND
/MEMORY
/RPB

Searches main memory for a page-aligned 256-Kbyte block
of good memory or for a restart parameter block.

HALT

Null command; no action is taken since the
cessor has already halted in order to enter
sole mode.

HELP

Prints explanation of console commands.

INITIALIZE[n]
/BI:n

Performs a system reset, includingself-test.

REPEAT

Executes the command passed as its argument.

RESTORE EEPROM

Copies the TK tapes EEPROM contents to the EEPROM ofthe processor executing the command.

SAVE EEPROM

Copies to the TK tape the contents of the EEPROMof the processor executing the command.

SET BOOT

Stores a boot commandby a nickname.

SET CPU [n]
/ENABLED
/ALL
/NOENABLED
/NEXT_PRIMARY
/PRIMARY
/ALL
/NOPRIMARY

Specifies eligibility of processors to become the boot processor.

SET LANGUAGE
ENGLISH
INTERNATIONAL

Changes the output of the console error messages between
numeric codeonly (international mode) and codeplusexplanation (English mode).

SET MEMORY
/CONSOLE_LIMIT:n
/INTERLEAVE:(n+n...)
/JINTERLEAVE:DEFAULT
ANTERLEAVE:NONE

Designates the method of interleaving the memory modules; supersedes the console program’s default interleaving.

SET TERMINAL
/BREAK
/NOBREAK
/HARDCOPY
/NOHARDCOPY
[SCOPE
/NOSCOPE
/SPEED:n

Sets console terminal characteristics.

Console Operation

procon-

1-5

Table 1-5 (Cont.): Console Commands and Qualifiers
Command and

Qualifiers

Function

SHOW ALL

Displays the current value of parametersset.

SHOW BOOT

Displays all boot commands and nicknamesthat have been
saved using SET BOOT.

SHOW CONFIGURATION

Displays the hardware device type and revision level for

SHOW CPU

Identifies the primary processor and the statusof other processors.

SHOW ETHERNET

Locates all Ethernet adapters on the system and displays their addresses.

SHOW LANGUAGE

Displays the mode currently set for console error messages, international or English.

SHOW MEMORY

Displays the memory lines from the system self-test, show-

SHOW TERMINAL

Displays the baud rate and terminal characteristics func-

START

Begins execution of an instruction at the address specified in the commandstring.

STOP
/BI:n

Halts the specified node.

TEST
/RBD

Passes contro] to the self-test diagnostics.

UPDATE

Copies contents of the EEPROM on the processor executing the command to the EEPROM of the processor specified in the commandstring.

Logically connects the console terminal to another processor on the XMI bus or te a VAXBI node.

/BI:n

each XMI and VAXBI node and indicates self-test status.

ing interleave and memory size.
tioning on the console terminal.

Introduces a comment.

1—6

VAX 6000—400 Mini-Reference

Console Control Characters

Character

Function

Causes the console to abort processing of a command.

&
ale

a
4)
ml
QO
4
0
fo
{4
iz

Causesconsole to discard output to the console terminal until the next[CTRUO]

is entered.

In console mode, acts like

Resumesconsole output that was suspended with

In program mode,causes the boot proces-

sor to halt and begin running the console program.

Redisplays the currentline.

Discards al] characters on the current line.
Deletes the previously typed character.

c
2

m
m

HG E

Suspends console output on the console terminal until

al
4)
yl

aak

Increments the console baud rate if enabled.

BREAK

2
i
ix

Table 1-6:

is typed.

Suppresses any special meaning associated with a given character.
Carriage return; ends a commandline.

Console Operation

1-7

Figure 1-2:

BOOT Command Syntax
BOOT /XMIi:m /BI:n /R5:v /R3:w /NODE: xxyy DDzz

Console command

invoking BOOT program

Selects VAXBI channel
Selects boot device's

VAXBI adapter (KDB50,
CIBCA, DEBNI)

unit numberinformation

Selects HSC controller

Selects boot
device type
Selects hexadecimal
unit numberof boot device
msb-0165-89

1-8

VAX 6000—400 Mini-Reference

Table 1-7: Sample BOOT Commands
Boot Procedure

BOOT command

Boot from TK tape drive

BOOT CSA1

Bootfrom local disk

BOOT /XMI:m /BI:n DUzz

Boot from HSC disk

BOOT /XMI:m /BI:n /R5:v /NODE:xxyy DUzz

Boot VAX/DS from TK

BOOT/R5:10 CSA1

Boot VAX/DS from disk

BOOT/XMI:m /BI:n /R5:10 DUzz

Conversational] boot

BOOT /XMI:m /BI:n /R5:1 DDzz

Boot from VMSshadowset

BOOT /XMI:m /BI:n /R3:w /NODE:xxyy DDzz

Boot over the Ethernet

BOOT /XMI:m /BI:n ETO

Table 1-8:

BOOT Command Qualifiers

Qualifier

Function

/X[MT):number

Specifies the XMI node numberof the node that connects the boot device.

/B[T):number

Specifies the VAXBI node that connects the boot device. The /XMI
qualifier must have selected a node containing a DWMBA/A.

/R5:number

Specifies the hexadecimal] value to be loaded into register R5 immediately before the virtual memory boot (VMB) program receives control. Use as a bit mask to select VMB options and to set the system root directory.

/R3:number

Specifies the hexadecimal valueto be loaded into register R3 immediately before the virtual memory boot (VMB) program receives control. This qualifier is used when multiple unit numbers must be specified: for example, when booting from VMSshadowsets.If /R3 is specified, the unit number portion of the device name is ignored.

/N([ODE):number

Specifies the remote node(s) that provide access to the boot device. The /XMI (and optionally /BI) qualifiers must have identified a controller that supports "nodes" such as a VAXcluster adapter. The /NODE qualifier would then specify the VAXcluster node number(s) of the HSC controlling the boot device.

Console Operation

1-9

Table 1-9:

R5 Bit Functions for VMS

Bit

Function

Conversational boot. The secondary bootstrap program, SYSBOOT, prompts you
for system parameters at the console terminal.

Debug. If this flag bit is set, the operating system maps the code for the
XDELTA debugger into the system page tables of the running operating system.

Initial breakpoint. If this flag bit is set, VMS executes a breakpoint (BPT) instruction early in the bootstrapping process.

Secondary boot from boot block.
The secondary boot is a single 512byte block whose logical block number is specified in General Purpose Register R4.

Boots the VAX Diagnostic Supervisor. The secondary loader is an image called DIAGBOOT.EXE.

Boot breakpoint. This stops the primary and secondary loaders with a break-

Image header.
The transfer address of the secondary loader image comes from the image header for that file. If this flag is not set, control shifts to the first byte of the secondary loader.

File name. VMB prompts for the nameof a secondary loader.

Halt before transfer. VMB executes a HALTinstruction before transferring contro] to the secondary loader.

No effect, since console program tests memory.

Reserved for VAX Diagnostic Supervisor.

Do not discard CRD pages.

31:28

Specifies the top-level] directory numberfor system disks.

point (BPT) instruction before testing memory.

Table 1-10:

R5 Bit Functions for ULTRIX

Bit

Function

Forces ULTRIXBOOTto promptthe user for an image name(the default is VMUNIX).

Boots the ULTRIX kernel] imagein single-user mode.

Mustbe set, and R4 must be zero.

Mustbe set.

1-10

VAX 6000-400 Mini-Reference

Table 1-11: Console Error MessagesIndicating Halt
Error Message
702 External halt (CTRL/P, break, or exter-

nal halt).

Meaning
or STOP command.

703 Power-up halt.

System has powered up, had a system reset, or an XMI nodereset.

704 Interrupt stack not valid during exception processing.

Interrupt stack pointer contained an invalid address.

705 Machine check occurred during exception processing.

A machine check occurred while handling another error condition.

206 Halt instruction executed in kernel mode.

The CPU
tion.

207 SCB vector bits <1:0> = 11.

An interrupt or exception vector in the
System Control Block contained an invalid address.

7208 SCB vector bits <1:0> = 10.

An interrupt or exception vector in the
System Control Block contained an invalid address.

270A CHMxexecuted while on interruptstack.

A change-mode instruction was issued
while executing on the interrupt stack.

710 ACV/TNV occurred during machine check
processing.

An access violation or translation-not-

711 ACV/TNV occurred during kerne]-stack-notvalid processing.

An access violation or translation-not-

712 Machine check occurred during machine
check processing.

A machine check occurred while processing a machinecheck.

713 Machine check occurred during kernel-stacknot-valid processing.

A machine check occurred while handling another error condition.

719 PSL <26:24>= 101 during interrupt
or exception.

An exception or interrupt occurred while
on the interrupt stack but not in kernel mode.

71A PSL <26:24>= 110 during interrupt
or exception.

An exception or interrupt occurred while
on the interrupt stack but not in kernel mode.

71B PSL <26:24>= 111 during interrupt
or exception.

An exception or interrupt occurred while
on the interrupt stack but not in kernel mode.

executed

Halt

instruc-

valid error occurred while handling another error condition.

Console Operation

1-11

Table 1-11 (Cont.): Console Error MessagesIndicating Halt
Error Message

Meaning

71D PSL <26:24> = 101 during REI.

An REI instruction attempted to re-

store a
bination

PSL with an invalid comof access mode and inter-

rupt stack bits.

71E PSL <26:24> = 110 during REI.

An REI instruction attempted to restore a PSL with an invalid com-

bination

access

rupt stack bits.

?1F PSL <26:24> = 111 during REI.

mode

and

inter-

An REI instruction attempted to restore a PSL with an invalid combination of access mode and inter-

rupt stack bits.

Table 1-12: Standard Console Error Messages
Error Message

Meaning

720 Illegal memory reference.

An attempt was made to reference a virtual

address

(/V)

that is

either un-

mapped oris protected against access under the current PSL.

721 Tegal command.

The command was not recognized, contained the wrong number of parameters, or contained unrecognized or inappropriate qualifiers.

722 Illegal address.

The specified address was recognized as
being invalid, for example, a general purpose register numbergreater than 15.

723 Value is too large.

A parameter or qualifier value contained too manydigits.

724 Conflicting qualifiers.

A command specified recognized qualifiers that are illegal in combination.

725 Checksum did not match.

The checksum calculated for a block of X
command data did not match the checksum received.

226 Halted.

The processor is currently halted.

227 Item was not found.

The item requested in a FIND command could not be found.

1-12

VAX 6000-400 Mini-Reference

Table 1-12 (Cont.): Standard Console Error Messages
Error Message

Meaning

728 Timeout while waiting for characters.

The X commandfailed to receive a full
block of data within the timeout period.

229 Machine check accessing memory.

Either the specified address is not implemented by any hardware in the system, or an attempt was made to write
a read-only address, for example, the address of the 33rd Mbyte of memory on a 32-Mbyte system.

?72A Unexpected machine check or
interrupt.

A valid operation within the console
caused a machinecheck or interrupt.

?72B Commandis not implemented.

The commandis not implemented by this
console.

?72C Unexpected exception.

An attempt was made to examine either a nonexistent IPR or an unimplemented register in RSSC address range
(20140000—20140800).

22D For Secondary Processor n.

This message is a preface to second message describing some error related to a secondary processor. This message indicates which secondary processor is involved.

72E Specified node is not an I/O adapter.

The referenced node is incapable of performing I/O or did not pass its selftest.

730 Write to Z commandtarget has timed out.

The target node of the Z commandis not
responding.

731 Z connection terminated by “P.

A CTRL/P was typed on the
board to terminate a Z command.

732 Your node is already part of a Z
connection.

You cannot issue a Z command while exe-

2733 Z connection successfully started.

You have requested a Z connection to a
valid node.

734 Specified target already has a Z
connection.

The target node was the target of a previous Z connection that was improperly terminated. Reset the system to clear this
condition.

736 Commandtoo long.

key-

cuting a Z command.

The command length exceeds 80 charac-

ters.

Console Operation

1-13

Table 1-12 (Cont.): Standard Console Error Messages
Error Message

Meaning

237 Explicit interleave list is bad.
Configuring all arrays uninterleaved.

The list of memory arrays for explicit interleave includes no nodes that
are actually memory arrays.
All arrays found in the system are configured.

2739 Console patches are not usable.

The console patch area in EEPROM
is corrupted or contains a patch revision that is incompatible with the console ROM.

73B Error encountered during I/O
operation.

An J/O adapter returned an error status
while the console boot primitive was performing I/O.

?3C Secondary processor not in console mode.

The primary processor console needed to
communicate with a secondary processor, but the secondary processor was not
in console mode. STOP the node or reset the system to clear this condition.

73D Errorinitializing I/O device.

A console boot primitive needed to perform I/O, but could notinitialize the I/O
adapter.

?3E Timeout while sending message to
secondary processor.

A secondary processor failed to respond to a message sent from theprimary.
The primary sends such messages to perform console functions on secondary processors.

?3F Microcode power-upself-test failed
in REX520.

CPU chip failed its microcoded self-

test.

240 Key switch must be at "Update" to
update EEPROM.

A SET command was issued, but the
key switch was not set to allow updates to the EEPROM.

741 Specified node is not a bus adapter.

A commandto access a VAXBI node specified an XMI node that was not a bus
adapter.

2742 Invalid terminal speed.

The SET TERMINAL command specified an unsupported baudrate.

743 Unable to initialize node.

The INITIALIZE command failed to re-

1-14

VAX 6000-400 Mini-Reference

set the specified node.

Table 1-12 (Cont.): Standard Console Error Messages
Error Message

Meaning

744 Processor is not enabled to BOOT or START.

As a result of a SET CPU/NOENABLE
command, the processor is disabled from
leaving console mode.

2745 Unableto stop node.

The STOP commandfailed to halt the

246 Memory interleaveset is
inconsistent: nn...

The listed nodes do not form a valid memory interleave set.
One or more
of the nodes might not be a memory array or might be of a different size, or the set could contain an invalid number of members. Each listed array that is a valid memory will be configured uninterleaved.

247 Insufficient working memory for normal operation.

Less than 256 Kbytes per processor of
working memory were found. There is insufficient memory for the console to function normally or for the operating system to boot.

2748 Uncorrectable memory errors—long memory test must be performed.

A memory array contains an unrecoverable error.
The console must perform a slow test to locate all the failing lo-

specified node.

cations.

749 Memory cannotbeinitialized.

The specified operation was attempted
and prevented.

274A Memories not interleaved due to
uncorrectable errors:

The listed arrays would normally have
been interleaved (by default or explicit request). Because one or more of them contained unrecoverable errors, this interleave set will not be constructed.

?4B Internal logic error in console.

The

24C Invalid node for Z command.

The target of a Z command must be a CPU
or an I/O adapter and must not be the primary processor.

24D Invalid node for new primary.

The SET CPU commandfailed when attempting to make the specified node the
primary processor.

74E Specified node is not a processor.

Thespecified node is not a processor, as required by the command.

console

encountered

cally impossible condition.

theoreti-

Console Operation

1-15

Table 1-12 (Cont.): Standard Console Error Messages
Error Message

Meaning

2?4F System serial number has not been
initialized.

No CPUin the system contains a valid
system serial number.

250 System seria] numbernotinitialized on
primary processor.

The primary processor has an uninitialized system serial number. All other processors in the system contain a valid serial number.

251 Secondary processor returned bad
response message.

A secondary processor returned an unintelligible response to a request made
by the console on the primary processor.

252 ROM revision mismatch. Secondary
processor has revision x.xx.

The revision of console ROM of a secondary processor does not match that of
the primary.

253 EEPROM header is corrupted.

The EEPROM header has been corrupted.
The EEPROM must be restored from the TK tapedrive.

754 EEPROMrevision mismatch.
Secondary processor has revision x.xx/y.y.

A secondary processor has a different revision of EEPROM or has a different set of EEPROM patches installed.

755 Failed to locate EEPROM area.

The EEPROM did not contain a set of
data required by the console. The EEPROM maybe corrupted.

256 Console parameters on secondary processor do not match primary.

The console parameters are not the same
for all processors .

757 EEPROM area checksum error.

A portion of the EEPROM is corrupted.
It may be necessary to reload the EEPROMfrom the TK tape drive.

2758 Saved boot specifications on secondary processor do not match primary.

The saved boot specifications are not the
samefor all processors.

259 Invalid unit number.

A BOOT or SET BOOT command specified a unit number thatis not a valid hexadecimal number between 0 and FF.

25A System serial number mismatch.
Secondary processor has xxxxxxxx.

The indicated serial number of a secondary processor does not match that of
the primary.

1-16

VAX 6000—400 Mini-Reference

Table 1-12 (Cont.): Standard Console Error Messages
Error Message

Meaning

?5B Unknown typeof boot device.

The console program does not have a boot
primitive to support the specified type
of device or the device could not be accessed to determine its type.

?5C No HELPis available.

The HELP command is not supported
when the console language is set to International.

75D No such boot spec found.

The specified boot specification was not
found in the EEPROM.

?25E Saved boot spec table full.

The maximum number of saved boot specifications has already been stored.

?75F EEPROM headerversion mismatch.

Processors have different versions of EEPROMs.

261 EEPROM header or area has bad

All or part of the EEPROM contains inconsistent data and is probably corrupted. Reload the EEPROM from the TK

format.

tape.

762 Illegal node number.

The specified node numberis invalid.

2763 Unable to locate console tape device.

The console could not locate the I/O

764 Operation only applies to secondary
processors.

The command can only be directed at a
secondary processor.

765 Operation not allowed from secondary
processor.

A secondary processor cannot perform this

266 Validation of EEPROM tape imagefailed.

The image on tape is corrupted or
is not the result of a SAVE EEPROM command. The image cannotbe restored.

767 Read of EEPROM imagefrom tape failed.

The EEPROM image was not successfully read from tape.

768 Validation of local EEPROM failed.

For a PATCH EEPROM operation, the
EEPROM must first contain a valid image before it can be patched. For a RESTORE EEPROM operation, the image was written back to EEPROM
but could not be read back successfully.

769 EEPROM not changed.

The EEPROM contents were not changed.

adapter that controls the TK tape.

operation.

Console Operation

1-17

Table 1-12 (Cont.): Standard Console Error Messages
Error Message
?6A EEPROMchanged successfully.
?6B Error changing EEPROM.

?76C EEPROMsaved to tape successfully.
26D EEPROM not saved to tape.

Meaning
The EEPROM contents were success-

fully patchedor restored.

An error occurred in writing to the EEPROM. The EEPROMcontents maybe corrupted.
The EEPROM contents were success-

fully written to the TK tape.

The EEPROM contents were not com-

pletely written to the TK tape.

?76E EEPROM Revision = x.xx/y.yy.

The EEPROM contents are at revision x.xx with revision y.yy patches.

?6F Major revision mismatch between tape
image and EEPROM.

The major revision of tape and EEPROM donot match. The requested operation cannot be performed.

770 Tape image Revision = x.xx /y.y.

The EEPROM image on the TK tapeis
at revision x.xx with revision y.yy patches.

773 System seria] number updated.

The EEPROM has been updated with the
correct system serial number.

?74 System serial number not updated.

The EEPROM has not been changed.

775 /CONSOLE_LIMIT value too small for
proper operation. Value ignored.

No change has been made.

276 Error writing to tape. Tape may be
write-locked.

Tape has not been written. Check to see
if tape is write-locked.

777 CCA not accessible or corrupted.

Attempt to find the console communications area (CCA) failed.
The console then builds a local CCA, which does
not allow for interprocessor communication.

778 CONTINUE command is disabled, be-

Systems with pass 1 and pass 2 DC520
chips do not implement the CONTINUE
console command.

783 Loading system software.!

The console is attempting to load the operating system in response to a BOOT command, power-up, or restart failure.

cause DC520 revision is less than 3.

1No numberedprefix appears with these messages in English language mode. These numbers are used for these messages in International mode.

1-18

VAX 6000-400 Mini-Reference

Table 1-12 (Cont.): Standard Console Error Messages
Error Message

Meaning

784 Failure.

An operation did not complete successfully. Should be issued with another messageto clarify failure.

285 Restarting system software.!

The console is attempting to restart the inmemory copy of the operating system following a power-up or serious error.

?A0 Initializing system.!

The console is resetting the system in response to a BOOT command.

?7A6 Console halting after unexpected ma-

The console executed a Halt instruction to reset the console state after processing an unexpected machine check.

2?A7 RCSR <WD>is set.
built.

When the <WD> bit is set, writes
to memory are disabled.
The processor must then build a CCA in local memory,
Main memory cannot be written to or accessed with interlocked instruc-

chine check or exception.!

Local CCA must be

tions.

2A8 Bootstrap failed due to previous error.!

The previous attempt to bootstrap the system failed.

2?A9 Restart failed due to previouserror.!

The previous attempt to restart the system failed.

Node: n ?xx

Error message ?xx was generated on secondary processor n and was passed
to the primary processor to be displayed.

1No numberedprefix appears with these messages in English language mode. These numbers are used for these messages in International mode.

Console Operation

1—19

Chapter 2

Self-Test
Example 2—1 is a sampleself-test display, which deliberately includes some
failuresto illustrate the type of information reported. Each lineis described
below. Table 2—1 describes the configuration and assumptionsused for this
sample.
Example 2—1:

Sample Self-Test Results

#123456789 0123456789 0123456789 012345678@

¢C

A
o

A.
oo.

_
-

M
+

M
+
,

M
+

ROMO = V1.00

A2
32

P
+
E
+
B

P
+
B
E

PP
+
E
D
=
+
E
D

,
+

Al.

ROM1 = v1.00@) EEPROM = 1.00/1.01@

+12

wope#*@
TYP
STF
BPD
ETF
BPD

.
.

xBIv -O
=XBIE +
ILV

128Mb

sw = sco1234567®

>>>

@ The progress trace. This line appears when slot 1 holds a KA64A
module.

@ Identifies the node number (NODE#).
Lines 3 through 7 refer to XMI node numbers; the XBI lines refer to
VAXBI node numbers.
© Identifies the module type (TYP).
P = processor

M = memory

A = adapter

Self-Test

2-1

Gives self-test failure results (STF).

+ = passed

— = failed

o = not tested as part of the initial power-up test

Showsboot processor designation (BPD).
E = eligible to be boot processor
D = ineligible to be boot processor
B = designated as boot processor
Gives extended CPU/memory tests failure results (ETF). Same
interpretation as STF.
Shows the second boot processor designation, which may be different
from that on thefirst BPD line.

Shows DWMBAtest results, node number, andself-test results of the

VAXBI nodes (XBI). The + or — at the right means that the DWMBA

Displays the memory array membershipin interleave sets (ILV). Each
letter denotes a different interleaveset.

Gives each memory array size and the total working memory size (Mb).

passed or failed when tested by the boot processor. If the DWMBA
passed, a + or — corresponding to each VAXBI nodeindicates whether
that node passed or failed its ownself-test.

Gives the version number andrevision numberof the boot processor’s
EEPROM.Thefirst numberis the base revision of the EEPROM, which
rarely changes. The second numberis the revision of console and
diagnostic patches applied to the EEPROM. This number increments
with every patch operation. For example, revision 1.01 means that
there has been one patch for base revision 1.00.

Shows the version number of the boot processor’s ROMs (ROMO and
ROM1).

Lists the serial number of the system (SN).

2-2

VAX 6000-400 Mini-Reference

Table 2—1: System Configuration for Sample Self-Test
Module

XMI Node
Number
Module Type

KA64A

Processor; disabled from being boot processor.

KA64A

Processor; fails self-test.

KA64A

Processor; boot processor after self-test, fails extended test.

KA64A

Processor; becomes boot processor.

MS62A

Memory (32 Mbytes); interleaved with memory at node 8.

MS62A

Memory (32 Mbytes); interleaved with memory at node 7.

MS62A

Memory (32 Mbytes); interleaved with memory at node A.

MS62A

Memory (32 Mbytes); interleaved with memory at node 9.

DWMBA/A

I/O adapterthat failed self-test.

DWMBA/A

I/O adapter leading to a VAXBI bus that has passing modules at nodes 1, 4, 5, and 6; node 2 on the VAXBIbusfailed selftest.

Self-Test

2-3

Figure 2-1:

KA64A LEDsAfter Self-Test

[/—~

SELF-TEST PASSED

SELF-TEST FAILED
pt

YELLOW
RED

RED
BOOT CPU

OFF
OFF

‘7

OFF
ON

SECONDARY CPU

OFF

MOST
SIGNIFICANT
|

FAILING

TEST NUMBER
f (BINARY-CODED
DECIMAL)
msb-0176-69

NOTE: Interpretation of small red LEDs: ON is a zero, and OFF is a one.

2-4

VAX 6000-400 Mini-Reference

Table 2-2: TK70 Light Summary
Light

State

Condition

Green
(Operate Handle)

On
Off
Blinking

OK to operate handle.
Do not operate handle.
Defective cartridge. Pull the handle to the open position and remove cartridge.
Try another cartridge.

Yellow
(Tape in Use)

Steady
Blinking

Drive ready.
Drive in use.

Orange !

Tape write protected.

All three lights

Blinking

Drive fault. Attempt to reset the fault by pressing the unload button.

(Write Protected)

Off

Tape write enabled.

1The orange light is on when anyof the following conditions exist:
eCartridge write protect switch is in the protected position.
eCartridge is software write protected.
eAttempt was made to mountorinitialize a cartridge previously written in a TK50drive.

Self-Test

2—5

Chapter 3

Address Space
The design of the hardware for the system bus (the XMI) and for the
VAXBI bus affects addressing. The VAXBI card cage was designed so that
node addressing did not depend upon a particular slot; a node’s address
was derived from a node ID plug in the backplane, a number from 0 to
15. VAXBI address space was divided up to provide for 16 nodes. The
system bus card cage, on the other hand, has its 14 slots permanently
assigned to specific address locations. Furthermore, because of the XMI
architecture and the XMI cage design, no modules that require I/O cables
can beinstalled in the middle six slots (slots 5 through A).

Figure 3-1:

VAX 6000-400 Slot Numbers

VAXBI
CAGE1

VAXBI
CAGE 2

6 643 2 1

_XMI CARD CAGE

th
TE 2. eT

all
E DCBA® 876543 2 4

meab-0040-89

Address Space 3-1

The system bus address space is equally divided between memory and
I/O space (see Figure 3-2). Figure 3—3 shows how the XMI I/O address
space is allocated. Each node on the XMIhas its own nodespace of 512
Kbytes. Sixteen 512-Kbyte blocks are in XMI nodespace, but the system
bus implements only 14 nodes, leaving the first and last blocks reserved.
The 192 reserved Mbytes shownin thecenterof the figure correspondto the
slots that cannot be used for I/O. Eight blocks are assigned to I/O adapters.

Figure 3-2:

XMIi Memory and I/O Address Space

Byte Address
0000 0000
1FFF

FFFF

2000 0000
3FFF FFFF

Physical Memory Space
(512 Mbytes)

I/O Space

(512

Mbytes)

msb-p001-89

Register addresses for a particular device in a system are found by adding
an offset to the base address for that device. To distinguish between
addresses in XMI address space and addresses in VAXBI address space,
we use the following convention:
lowercase bb + offset indicates an address in VAXBI address space
uppercase BB + offset indicates an address in XMI address space

3-2

VAX 6000—400 Mini-Reference

Figure 3-3:

XMI I/O Space AddressAllocation

Byte Address

2000 0000
2180 0000
2200 0000

2400 0000
2600 0000
2800 0000
2A00 0000
3600 0000
3800 0000
3A00 0000
3c00 0000
3E00 0000
3FFF FFFF

Size
XMI Private Space
XMI Nodespace

24 Mbytes
16 x 512 Kbytes

I/O Adapter 1 Address Space

32 Mbytes

I/O Adapter 2 Address Space

32 Mbytes

I/O Adapter 3 Address Space

32 Mbytes

I/O Adapter 4 Address Space

32 Mbytes

Reserved

192 Mbytes

I/O Adapter B Address Space

32 Mbytes

I/O Adapter C Address Space

32 Mbytes

I/O Adapter D Address Space

32 Mbytes

I/O Adapter E Address Space

32 Mbytes

Reserved

32 Mbytes
msb-p002-89

Address Space

3-3

Table 3-1: XMI Addressing
Slot

Node

Permissible

Nodespace Base I/O Window Space

Modules!

Address (BB)

Prefix

CPU, VO

2188 0000

22xx XXxx

CPU, Mem, /O

2190 0000

24xx xxxx

CPU, Mem, I/O

2198 0000

26xx Xxxx

CPU, Mem, I/O

21A0 0000

28xx xxxx

CPU, Mem

21A8 0000

N/A

CPU, Mem

21B0 0000

N/A

CPU, Mem

21B8 0000

N/A

CPU, Mem

21C0 0000

N/A

CPU, Mem

21C8 0000

N/A

CPU, Mem

21D0 0000

N/A

CPU, Mem, I/O

21D8 0000

36xx Xxxx

CPU, Mem, I/O

21E0 0000

38xx xxx

CPU, Mem, I/O

21E8 0000

3AXX XXxXXx

CPU, I/O

21F0 0000

3Cxx xxxx

1Key to permissible modules:
CPU = KA64A CPU module
Mem = MS62A memory module
YO = DWMBAAA adapter module

3~4

VAX 6000—400 Mini-Reference

3.1 How to Find a Register in XMI Address Space
Because XMI addresses correspondto slot and node numbers, you wantto
determine the slot of the XMI card cage in which the module resides. The
slot number can be determined in two ways:
e

By looking at the XMI card cage (numbering of slots is shown in
Figure 3-1)

By entering at the console a SHOW CONFIGURATION command

A typical response is shown below.
>>> SHOW CONFIGURATION
1+
2+
9+
A+
D+
E+

Type
KA64A
KA64A
MS62A
MS62A
DWMBA/A
DWMBA/A

(8082)
(8082)
{4001)
(4001)
(2001)
(2001)

Rev
0006
0006
0002
0002
0002
0002

XBI
1+
5+
6+

D
DWMBA/B
DMB32
DEBNI

(2107)
(0109)
(0118)

0007
210B
0100

XBI
1+
4+
6+

E
DWMBA/B
KDB50
TBK70

(2107)
(O1LOE)
(410B)

0007
OFIC
0307

Assume that you want to examine the Bus Error Register (XBER) of the
DWMBA/A module in the leftmost slot (14), which is XMI node E. From

Table 3—1 you can see that the nodespace base address for the XMI module
at node E is 21F0 0000. From Table 6—1 you can see that the XBERoffset
is BB + 04, so you add 04 to the base address to get the address for that
module’s XBER register. You could examine the XBERregister with the
command:
>>>

E/L/P 21F00004

Address Space

3-5

3.2 How to Find a Register in VAXBI Address Space
Thefirst part of a VAXBI adapter’s physical XMI address depends on which
XMI slot the DWMBA/A module occupies. The second part of the address
dependson the adapter’s VAXBI node number, which is shown in the SHOW
CONFIGURATIONdisplay.
NOTE: VAXBIslot and node numbers are not identical. The placement of
the VAXBI node ID plug on the backplane determines the node ID, so seeing
that a particular option is in a certain slot does not guarantee that the slot
and node numberare identical. Use the VAXBI node identification from the
SHOW CONFIGURATION command.
The XMI slot number can be determined in two ways:
e

By looking at the XMI card cage (numbering of slots is shown in
Figure 3—1)

By entering at the console a SHOW CONFIGURATION command

A typical response is shown below.
>>> SHOW CONFIGURATION
Type

Rev

1+
2+
9+
A+
D+
E+

KA64A
KA64A
MS62A
MS62A
DWMBA/A
DWMBA/A

(8082)
(8082)
(4001)
(4001)
(2001)
(2001)

0006
0006
0002
0002
0002
0002

XBI
1+
S+
6+

D
DWMBA/B
DMB32
DEBNI

(2107)
(0109)
(0118)

0007
2108
0100

XBI
1+
4+
6+

E
DWMBA/B
KDB50
TBK70

(2107)
(O10E)
(410B)

0007
OF1C
0307

Assume that you want to examine the Device Register (DTYPE) for the
DEBNI, which is node 6 in the first VAXBI channel shown above (XBI D).
Figure 3—1 also shows which VAXBIcageis linked to which XMIslot.
To get the address for the DEBNI Device Register (DTYPE), do the
following:
1.

3-6

From Table 3-1 find XMI node D andtake the 2-digit prefix for that
node’s window space (3A).

VAX 6000—400 Mini-Reference

From Table 3-2 find VAXBI node 6 and in column 2 you can see that
the starting address for VAXBI node 6 is xx00 C000.

Combine this second numberwith the 2-digit prefix. You now have the
adapter’s base address (3A00 C000) in VAXBI address space, indicated
by lowercase bb.

From Table 3-3, VAXBI Registers, you can see that the VAXBI Device
Register (DTYPE)is at bb + 00, which is 3A00 C000.

The Device Register for the DEBNI would be examinedby:
>>>

E/L/P 3A00C000

Table 3-2: VAXBI Nodespace and Window Space Address Assignments
Node

Nodespace Addresses

Window Space Addresses

Number

Starting

Ending

Starting

Ending

xx00 0000

xx00 1FFF

xx40 0000

xx43 FFFF

xx00 2000

xx00 3FFF

xx44 0000

xx47 FFFF

xx00 4000

xx00 5FFF

xx48 0000

xx4B FFFF

xx00 6000

xx00 7FFF

xx4C 0000

xx4F FFFF

xx00 8000

xx00 9FFF

xx50 0000

xx53 FFFF

xx00 A000

xx00 BFFF

xx54 0000

xx57 FFFF

xx00 C000

xx00 DFFF

xx58 0000

xx5B FFFF

xx00 E000

xx00 FFFF

xx5C 0000

xx5F FFFF

xx01 0000

xx01 1FFF

xx60 0000

xx63 FFFF

xx01 2000

xx01 3FFF

xx64 0000

xx67 FFFF

xx01 4000

xx01 5FFF

xx68 0000

xx6B FFFF

xx01 6000

xx01 7FFF

xx6C 0000

xx6F FFFF

xx01 8000

xx01 9FFF

xx70 0000

xx73 FFFF

xx01 A000

xx01 BFFF

xx74 0000

xx77 FFFF

xx01 C000

xx01 DFFF

xx78 0000

xx7B FFFF

xx01 E000

xx0]1 FFFF

xx7C 0000

xx7F FFFF

Address Space

3-7

Table 3-3: VAXBI Registers
Name

Mnemonic

Address!

Device Register

DTYPE

bb+00

VAXBI Control and Status Register

VAXBICSR

bb+04

BusError Register

BER

bb+08

Error Interrupt Control] Register

EINTRSCR

bb+0C

Interrupt Destination Register

INTRDES

bb+10

IPINTR Mask Register

IPINTRMSK

bb+14

Force-Bit IPINTR/STOP Destination Register

FIPSDES

bb+18

IPINTR Source Register

IPINTRSRC

bb+1C

Starting Address Register

SADR

bb+20

Ending Address Register

EADR

bb+24

BCI Control and Status Register

BCICSR

bb+28

Write Status Register

WSTAT

bb+2C

Force-Bit IPINTR/STOP CommandRegister

FIPSCMD

bb+30

User Interface Interrupt Control Register

UINTRCSR

bb+40

General Purpose Register 0

GPRO

bb+F0

General Purpose Register 1

GPR1

bb+F4

General Purpose Register 2

GPR2

bb+F8

General Purpose Register 3

GPR3

bb+FC

Slave-Only Status Register

SOSR

bb+100

Receive Console Data Register

RXCD

bb+200

1The abbreviation "bb" refers to the base address of a VAXBI node (the address of the first lo-

cation of the nodespace).

3-8

VAX 6000-400 Mini-Reference

Chapter 4

KA64A CPU Module Registers
The KA64A registers consist of the following:
e

Internal processor registers (IPRs) (see Table 4—2)

Registers in XMI private space (see Table 4—3)

XMIregisters (see Table 4—4)

Machine-check parameters are listed in Section 4.4 and parse trees in
Section 4.5.

Table 4—1: Types of Registers and Bits
Type

Description

Read only

R/W

Read/write

R/W1C

Read/cleared by writing a one

Write only

KA64A CPU Module Registers

4—1

4.1 KA64A Internal Processor Registers
Table 4-2:

KA64A internal Processor Registers

Mnemonic

Address
decimal (hex)

Type

Class

Kernel Stack Pointer

KSP

0 (0)

R/W

Executive Stack Pointer

ESP

1 (1)

R/W

Supervisor Stack Pointer

SSP

2 (2)

R/W

User Stack Pointer

USP

3 (8)

R/W

Interrupt Stack Pointer

ISP

4 (4)

R/W

Reserved

5—7 (5-7)

PO Base

POBR

8 (8)

R/W

PO Length

POLR

9 (9)

R/W

P1 Base

P1BR

10 (A)

R/W

Pi Length

P1LR

11 (B)

R/W

System Base

SBR

12 (C)

R/W

System Length

SLR

13 (D)

R/W

Reserved

14-15 (E-F)

Process Control Block Base

PCBB

16 (10)

R/W

System Control Block Base

SCBB

17 (11)

R/W

Key to Types:
R—-Read
W-_-Write
R/W-Read/write
Key to Classes:
1—Implemented by the KA64A (as specified in the VAX Architecture Reference Manual).
2—Implemented uniquely by the KA64A.
3—Not implemented. Read as zero; NOP on write.
4—Access not allowed; accesses result in a reserved operandfault.
5—Accessible, but not fully implemented; accesses yield UNPREDICTABLE results.
J-The register is initialized on KA64A reset (power-up, system reset, and node reset).

4-2

VAX 6000-400 Mini-Reference

Table 4—2 (Cont.):

KA64A Internal Processor Registers

Mnemonic

Address
decimal (hex)

Type

Class

Interrupt Priority Level

IPL

18 (12)

R/W

AST Level

ASTLVL

19 (13)

R/W

Software Interrupt Request

SIRR

20 (14)

Software Interrupt Summary

SISR

21 (15)

R/W

Reserved
Interval Counter Control and
Status

22-23 (16-17)
ICCS

Reserved

24 (18)

3
R/W

25-26 (19-—1A)

21
3

Time-of-Year Clock

TODR

27 (1B)

R/W

Console Storage Receiver Status

CSRS

28 (1C)

R/W

Console Storage Receiver Data

CSRD

29 (1D)

Ponaole Storage Transmitter Sta8

CSTS

30 (1E)

R/W

Console Storage Transmitter Data

CSTD

31 (1F)

Console Receiver Control/Status

RXCS

32 (20)

R/W

Console Receiver Data Buffer

RXDB

33 (21)

Console Transmitter Control/Status

TXCS

34 (22)

R/W

Console Transmitter Data Buffer

TXDB

35 (23)

WwW

Reserved
Machine Check Error Summary

36—37 (24—25)
MCESR

Reserved
Accelerator Control and Status

38 (26)

3
Ww

39 (27)
ACCS

Reserved

40 (28)

2
3

R/W

41 (29)

21
3

Console Saved PC

SAVPC

42 (2A)

Console Saved PSL

SAVPSL

43 (2B)

Reserved
Translation Buffer Tag
Reserved

44-46 (2C—2E)
TBTAG

47 (2F)

3
WwW

48-54 (30-36)

KA64A CPU Module Registers

2
3

4-3

Table 4—2 (Cont.):

KA64A Internal Processor Registers

Mnemonic

I/O Reset

Address

decimal (hex)

Type

Class

IORESET

55 (37)

Memory Management Enable

MAPEN

56 (38)

R/W

Translation Buffer Invalidate

TBIA

57 (39)

WwW

Translation Buffer Invalidate
Single

TBIS

58 (3A)

Translation Buffer Data

TBDATA

59 (3B)

WwW

All

Reserved

60-61 (3C-3D)

System Identification -

SID

62 (3E)

Translation Buffer Check

TBCHK

63 (3F)

Reserved

64-111 (40-6F)

Backup Cache Reserved

BC112

112 (70)

R/W

Backup Cache Backup Tag Store

BCBTS

113 (71)

R/W

Backup Cache P1 Tag Store

BCP1TS

114 (72)

R/W

Backup Cache P2 Tag Store

BCP2TS

115 (73)

R/W

Backup Cache Refresh

BCRFR

116 (74)

R/W

Backup Cache Index

BCIDX

117 (75)

R/W

Backup Cache Status

BCSTS

118 (76)

R/W

Backup Cache Control

BCCTL

119 (77)

R/W

Backup Cache Error

BCERR

120 (78)

Backup Cache Flush Backup Tag
Store

BCFBTS

121 (79)

Backup Cache Flush Primary Tag
Store

BCFPTS

122 (7A)

WwW

Reserved

123 (7B)

Primary Cache Tag Array

PCTAG

124 (7C)

R/W

Primary Cache Index

PCIDX

125 (7D)

R/W

Primary Cache Error Address

PCERR

126 (7E)

R/W

Primary Cache Status

PCSTS

127 (7F)

R/W

VAX 6000-400 Mini-Reference

Table 4—2 (Cont.):

KA64A Internal Processor Registers

Mnemonic

Address
decimal (hex)

Type

Class

Reserved

128-143 (80-8F)

Reserved

144—147 (90-93)

Reserved

148-156 (94—9C)

Reserved

157-159 (9D-9F)

Reserved

160-255 (A0-FF)

Reserved

256 (100) and up

Figure 4—1:

Machine Check Error Summary Register (MCESR)

IPR38 (26 hex)

3
1

0
Machine

Check Error

Summary

(MCESR)

msb-p023-89
Figure 4—-2:

Accelerator Control and Status Register (ACCS)
IPR40 (28 hex)

3 3
1 0

210

|
L

MUST BE ZERO
Write Even Parity

WoO

| Jo]
F-Chip Present r/w—
msb-p024-89

KA64A CPU Module Registers 4-5

Figure 4-3:

Console Saved Program Counter Register (SAVPC)

IPR42 (2A hex)

0
Console Saved Program Counter

(SAVPC)

|
msb-p025-89

Figure 4—4:

Console Saved Processor Status Longword (SAVPSL)
IPR43 (2B hex)

3
1

11iil1i
6 5 4 3

}

Processor

Status Longword<31:16>
(PSL<31:16>)
RO
Memory Management Enable

(MAPEN<0>)

Valid Bit
RO
Halt Code
RO
Processor Status Longword<7:0>

(PSL<7:0>)

RO
msb-p026-89

Figure 4-5:

Translation Buffer Tag Register (TBTAG)
IPR47 (2F hex)

9 8
Virtual

Page

Number

(VPN)

0
MUST BE

ZERO

msb-p027-89

4-6

VAX 6000-400 Mini-Reference

I/O Reset Register (IORESET)
IPR55 (37 hex)

MH WwW

Figure 4-6:

IORESET

R/W
msb-p028=-89

Figure 4-7:
3 3
1 0

Translation Buffer Data Register (TBDATA)
IPR59 (3B hex)

222
765

22
1 0

(TIT = |
;

Page Table Entry Page
Frame

Number

(PTE.PFN)

wo——

Page Table Entry Modify (PTE.M)
WO
Page Table Entry Protection (PTE.PROT)
Page Table Entry Valid (PTE.V)
WO

WO
msb-p029-89

Figure 4-8:

System Identification Register (SID)

IPR62 (3E hex)

3
1

MUST

ZERO |

cre "yet erocode Options

Microcode Revision

wot
RO

msb-p077-89

KA64A CPU Module Registers 4~-7

Figure 4—-9:

Backup Cache Backup Tag Store Register (BCBTS)

IPR113 (71 hex)

3322
109 8

11
7 6

mez. |

6 5
MUST BE

ZERO

|
Parity Bit

210

Valid Bits<4:1>
Cache Entry Tag
R/W
R/W

| maz,|

R/w—

msb-p030-89

Figure 4-10:

Backup Cache Primary 1 Tag Store Register (BCP1TS)

IPR114 (72 hex)

11
1 0

[ee] |

Twez

Parity Bit R/W

Valid Bit

Cache Entry Tag

R/W

321

| [mma]

n/w—

msb-p068-89

Figure 4-11:

Backup Cache Primary 2 Tag Store Register (BCP2TS)

IPR115 (73 hex)

3 22
09 8

11
1 0

-——

con

Tez

|
Parity Bit R/W

Valid Bit
Cache Entry Tag
R/W

321

| [una]

rR/w—

msb-p0 68-89

4-8

VAX 6000—400 Mini-Reference

Figure 4-12:

Backup Cache Refresh Register (BCRFR)
IPR116 (74 hex)

3
1

iil
7 6
MUST BE

ZERO

9 8

Backup Tag Store Refresh Address

r/w—

Primary Tag Store Refresh Address

R/W

0
MBZ

msb-p031-89

Figure 4-13:

Backup Cache Index Register (BCIDX)

IPR117 (75 hex)

When used for backup tag store indexing:
3
1
|

11
7 6
MUST BE

ZERO

6 5

Backup Tag Store Row Index
(BTS

9 8

ROW INDEX)

Backup Tag Store Column Index
(BTS COL INDEX)

R/W

0
MBZ

R/W

When used for primary tag store indexing:
1 1
1 0 9 8

3
1
|

MUST BE ZERO

Primary Tag Store Column Index
(PTS COL INDEX)
Primary Tag Store Row Index (PTS ROW INDEX)

4 3

| mez |

a
msb-p032-89

KA64A CPU Module Registers

4-9

Figure 4-14:

3
1

| mez

Backup Cache Status Register (BCSTS)

IPR118 (76 hex)

22 22
7 6 5 4

22i1i3a1ai1i1
109 8 7 6

| |

LL LL

PEEDnoJ

543210

must Be zero

|_| | | |

pusERRRo|

I-BUS
CYCLE
RO
DAL CMD<3:0>
RO
P2TS HIT
RO
P1TS HIT
RO
BTS HIT
RO
BTS COMPARE
RO

P1TS PERR

BTS PERR
RO
STATUS LOCK R/W1C

msb-p033-89

Figure 4-15:

Backup Cache Control Register (BCCTL)
IPR119 (77 hex)

54321
MUST

ZERO

| |

Two-Cycle RAMs
R/w———_—— |
Enable Refresh
R/W
Enable Primary Tag Store
R/W
Enable Backup Tag Store
R/W
Force Backup Tag Store Hit
R/W
msb-p034-89

Figure 4-16:

Backup Cache Error Address Register (BCERR)
IPR120 (78 hex)

33 2
10 9
| o

3
Backup

Cache

Error Address Register

(BCERR)

2
|

0
MBZ |

msb-p035-89

4-10

VAX 6000—400 Mini-Reference

Figure 4-17:

Backup Cache Flush Backup Tag Store Register (BCFBTS)

IPR121 (79 hex)

3
1

0
Backup Cache Flush Backup Tag Store Register

(BCFBTS)

msb-p036-89

Figure 4-18:

Backup Cache Flush Primary Tag Store Register (BCFPTS)
IPR122 (7A hex)

3
1
|

0
Backup Cache Flush Primary Tag Store Register

(BCFPTS)

msb-p037-89

Figure 4-19:

ee
or

2
8

wo bO

Primary Cache Tag Array Register (PCTAG)

IPR124 (7C hex)

Tag

L Parity
Valid

R/W

MUST BE ZERO

R/W

msb-p038-89

KA64A CPU Module Registers 4-11

Figure 4—20:

Primary Cache Index Register (PCIDX)
IPR125 (7D hex)

1
|

MUST BE ZERO

11
1 0

3 2

Tag Array Index

0
MBz |

r/w—
msb-p039-89

Figure 4-21:

Primary Cache Error Address Register (PCERR)
IPR126 (7E hex)

When Trapl is set:
3 3 2
109
| mez |

Primary

Cache

Error Address

(PCERR)

When Trapl is not set:
3

1
|

MUST

9 8

ZERO

Refresh

6 5

Timer

Refresh Counter

R/w—

R/W

3 2

0
MBZ

msb-p040-89

4-12

VAX 6000-400 Mini-Reference

Primary Cache Status Register (PCSTS)
IPR127 (7F hex)
11iii
3210987654321 «0

Figure 4-22:

MUST BE ZERO

LEEEELEELELELELLE

BackupCacheHit,(BCACHE EIT) _xo—J]

Primary Data Parity Error
(P DATA PARITY ERROR)
RO
DAL Bus Data Parity Error
(DAL DATA PARITY ERROR)
Ro
Tag Parity Error
RO
Trapl

R/WI1C

Trap2
R/W1C
Interrupt
R/W1C
Primary Cache Hit
(P

Enable Refresh

Flush Cache

CACHE HIT)

R/W

R/W1C

Enable Primary Tag Store

(ENABLE

Force

Hit

RO-—

PTS)

R/W-—

R/W

msb-p0 41-89

KA64A CPU Module Registers 4—13

4.2 KA64A Registers in XMI Private Space
Table 4-3:

KA64A Registers in XMI Private Space

Mnemonic

Address

Control Register Write Enable

CREGWE

2000 0000

Console ROM (halt protected)

2004 0000 to 2007 FFFF

Console EEPROM (halt protected)

2008 0000 to 2008 7FFF

Console ROM (not halt protected)

200C 0000 to 200F FFFF

Console EEPROM (not halt
protected)

2010 0000 to 2010 7FFF

RSSC Base Address

SSCBAR

2014 0000

RSSC Configuration

SSCCNR

2014 0010

RSSC Bus Timeout Control

SSCBTR

2014 0020

RSSC Output Port

OPORT

2014 0030

Control Register 0

CREGO

Control Register 1

CREG1

RSSC Input Port

IPORT

2014 0040

Control Register Base Address

CRBADR

2014 0130

Control Register Address Decode Mask

CRADMR

2014 0134

EEPROM Base Address

EEBADR

2014 0140

EEPROM Address Decode Maak

EEADMR

2014 0144

Timer 0 Control

TCRO

2014 0160

Timer 0 Interval

TIRO

2014 0164

Timer 0 Next Interval

TNIRO

2014 0168

Timer 0 Interrupt Vector

TIVRO

2014 016C

Timer 1 Control

TCR1

2014 0170

Timer 1 Interval

TIR1

2014 0174

Timer 1 Next Interval

TNIR1

2014 0178

Timer 1 Interrupt Vector

TIVR1

2014 017C

RSSC Interval Counter

SSCICR

2014 01F8

4-14

VAX 6000—400 Mini-Reference

Table 4—3 (Cont.):

KA64A Registers in XMI Private Space

Mnemonic

Address

RSSC Internal RAM

2014 0400 to 2014 O7FF

IP IVINTR Generation

IPINTR

2101 0000 to 2101 FFFF

WEIVINTR Generation

WEINTR

2102 0000 to 2102 FFFF

Figure 4-23:

Control Register Write Enable Register (CREGWE)

2000 0000

0
Control

Enable

(CREGWE)

msab-p008=-89

Figure 4-24:

RSSC Base Address Register (SSCBAR)
2014 0000

3.322
1098
|mez} 1

11
10
RSSC Base Address (SSCBAR)

R/W |

0
MUST BE ZERO

msb-p009-89

KA64A CPU Module Registers 4—15

3 3

2 2
8 7

Figure 4-25:

RSSC Configuration Register (SSCCNR)
2014 0010

2 2 22
5 4 3 2

2i1i1
0 9 8

111
65 4

1
2

Coe DLT
L

CREG Address

Enable

(CREG ADS
EEPROM Enable
(EEPROM ADS ENA)

Console Terminal Baud Rate Select
(TERM BAUD SEL)
R/W
CTRL/P Enable (CTRL/P

ENA)

R/W

ROM Halt Protect Address Space Size
(HALT PROT)

R/W

ROM Address Space Sizer Select (ROM SIZE)
R/W
Interrupt Priority Level Select (IPL SEL)
R/W
Interrupt Vector Disable (IV Disable)
R/W
Battery

Low

(BLO)

R/W1C

msb-p010r=-89

Figure 4-26:
3 3 2
10 9

RSSC Bus Timeout Control Register (SSCBTR)
2014 0020
22
4 3

To]
|

L read Write Timeout (RWT)
Bus Timeout (BTO) R/W1C

:
R/W1C

Bus

Timeout

Interval

R/W

msb-p011-89

4-16

VAX 6000—400 Mini-Reference

Figure 4-27:

RSSC Output Port Register (OPORT)
2014 0030

3
1

1
0 9
MUST BE ZERO

| | |

Control Register Data (CREG DATA)
R/w—
Control Register 1 Select (CREG1 SEL)
R/W
Control Register 0 Select (CREGO SEL)
R/W
msb-p012-89

Figure 4-28:

Control Register 0 (CREGO)
6543210

MUST BE ZERO
Force Pl

ry) /})

Parity Error

Force PO Parity Error
Force P2 Parity Error
Console

Terminal

Enable

wo ——_____

WO
wo

(TERM ENA)

Console Terminal Mode Select

(TERM SEL)

msb-p0 66-89

KA64A CPU Module Registers 4-17

Figure 4-29:

Control Register 1 (CREG1)

87654321
MUST BE

ZERO

Self-Test

Self-Test
Self-Test
Self-Test
Self-Test
Self-Test

LED

LED
LED
LED
LED
LED

POG b& UO

Self-Test Passed LED (STP LED)
Self-Test Valid LED (STV LED)
(ST LED6)

(ST
(ST
(ST
(ST
(ST

LED5)
LED4)
LED3)
LED2)
LED1)

wo—
WO

0
| |

WO
Wo
WO
WO
WO

msb~-p067=-89

Figure 4-30:

RSSC Input Port Register (IPORT)

2014 0040

3 3
1 0

| |

98765

MUST BE ZERO
Console Enable
Scan Test

RO
Disable

4 3

TPtd dd

Self-Test Loop Disable

(STL DISABLE)
RO
XMI AC LO State (XACLO)
RO
Front Control Panel EEPROM Enable
(FP EEPROM ENABLE)
RO
Front Control Panel Boot Disable
(FP BOOT DISABLE)
RO==

XMI Node Identification

(NODE ID)

msb-p013-89

4-18

VAX 6000-400 Mini-Reference

Figure 4-31:

Control Register Base Address Register (CRBADR)

2014 0130

3 3 2
10 9
| mez}

210
Control

(CRBADR)

R/W

|upz|

msb-p014=-89

Figure 4-32:

Control

(CRADMR)2014 0134

Address

Decode

Mask

332
10 9
MBz |

21
Control Register Address Decode Mask

(CRADMR)

R/W

| mez |

msb-p015-89

Figure 4-33:

EEPROM Base Address Register (EEBADR)
2014 0140

3 3 2
1 0 9
|mez. |

210
EEPROM Base Address

(EEBADR)

R/W

|mBz.|
msb-p016-89

Figure 4-34:

EEPROM Address Decode Mask Register (EEADMR)
2014 0144

3 3 2
i 0 9
|

21
EEPROM Address

Decode Mask

(EEADMR)

R/W

[mez

msb-p017-89

KA64A CPU Module Registers 4-19 .

Figure 4—35:

Timer Control Register 0 (TCRO)

2014 0160

3 3
1 0

r]
L

8765 4

MUST BE ZERO
Error

(ERR)

R/W1C

TTT] Il Jol

Interrupt (INT)
R/W1C
Interrupt Enable (IE)
R/W
Single (SGL)
R/W
Transfer (XFR)
R/W

Stop

Run

(STP)

(RUN)

R/W

msb-p018-89

Figure 4—36:

TimerInterval Register 0 (TIRO)

2014 0164

Timer Interval Register

|
msb-p019-89

Figure 4-37:

Timer Next interval Register 0 (TNIRO)

2014 0168

1
|

0
Timer Next Interval Register

R/W

|
msb-p020-89

4-20

VAX 6000—400 Mini-Reference

Figure 4-38:

Timer Interrupt Vector Register 0 (TIVRO)
2014 016C

1
|

10 9

210

| 52 |

MUST -BE ZERO

SCB Vector Offset

R/w—!
msb-p021-89

Figure 4—39:

Timer Control Register 1 (TCR1)
2014 0170

3 3
1 0

8765 4

MUST

Error

(ERR)

ZERO

R/W1C
Interrupt
Interrupt

(INT)

Enable

| |

2
}o|

0
| o|

J
R/WI1C Rw
(IE)

Single (SGL)
R/W
Transfer (XFR)
R/W
Stop (STP)
R/W
R/W
Run (RUN)

msb-p018-89

Figure 4-40:

Timerinterval Register 1 (TIR1)
2014 0174

0
Timer Interval Register

|
msb-p019-89

KA64A CPU Module Registers 4-21

Figure 4—41:

Timer Next Interval Register 1 (TNIR1)
2014 0178

Timer Next Interval Register

]

msb-p020-89

Figure 4—42:

Timer interrupt Vector Register 1 (TIVR1)
2014 017C

3
1

10 9
MUST

ZERO

21 0

SCB Vector Offset

| mez. |

R/w—
msb-p021=-89

Figure 4—43:

Interval Counter Register (SSCICR)
2014 01F8

3
1

11
3 2
MUST BE ZERO

0
Current Count

R/W

msb-p022-89

4-22

VAX 6000—400 Mini-Reference

4.3 KA64A XMI Registers
Table 4—4: XMI Registers for the KA64A CPU Module
Name

Mnemonic

Address

XMI Device Register

XDEV

BB!+ 00

XMI Bus Error Register

XBER

BB + 04

XMI Failing Address Register

XFADR

BB + 08

XMI General Purpose Register

XGPR

BB + 0C

KA64A Control and Status Register

RCSR

BB + 10

1BB = base address of an XMInode, which is the address ofthe first location in nodespace.

Figure 4—44:

Device Register (XDEV)
BB + 00
0

Device Revision

R/W

Device Type

(8082)

R/W

msb-p003-89

KA64A CPU Module Registers 4—23

Figure 4-45:

Bus Error Register (XBER)
BB + 04

LEP EET EET EE EEE EE rez
=

rex
L railing Command

(NSES)

Commander Errors
—====

ttIClv—=es

——_—«««emmeme

Transaction Timeout (TTO)
R/W1C
Reserved; must be zero
Command NO ACK (CNAK)
R/wic

Read Error Response

(RER)

——eee
oe

Read/IDENT Data NO ACK

(RIDNAK)

R/W1c

Write Sequence Error (WSE)
R/WI1C
§6Parity Error (PE)
R/WI1C
Inconsistent Parity Error (IPE)
R/WI1C

Miscellaneous
wees Write Error Interrupt (WEI)
ee =8XMI Fault (XFAULT)
R/W1C
“nme§€8COrrected Confirmation (CC)
es §=8XMI Bad (XBAD)
R/W
———— Node Halt (NHALT)
R/W
ns «=8NOode Reset (NRST)
R/W

Error Summary

(ES)

R/wic
R/wic

msb—-p004r—89

4-24

R/W1C

Read Sequence Error (RSE)
R/W1C
No Read Response (NRR)
R/WI1C
Corrected Read Data (CRD)
R/WI1C
Write Data NO ACK (WDNAK)
R/W1C

Responder Errors
__

VAX 6000-400 Mini-Reference

Failing Commander
Identification RO
Self-Test Fail (STF)
R/W1Cc
Extended Test Fail (ETF)
R/wi1c
Node-Specific Error Summary

Figure 4—46:

Falling Address Register (XFADR)
BB + 08

When XBER <3:0> =

1001

3
1
MUST BE

ZERO

(IDENT transaction):

21
0 9

11
6 5

Interrupt Priority Lever |
(IPL)
RO
Interrupt Source
When XBER <3:0>

1111

(IVINTR transaction):

3
1

l1iiil
8 7 65

MUST BE ZERO

| |

Write Error Interrupt
Implied Vector Interrupt

RO
Request (WEI IVINTR)
Interprocessor Implied
Vector Interrupt
(IP IVINTR)
RO
Interrupt Destination
RO

When XBER <3:0>
transaction:

neither

IDENT

transaction nor

332
109
|

|
L_ painting Length

IVINTR

0
Failing Address
(FLN)

RO
msb-p005-89

KA64A CPU Module Registers 4-25

Figure 4—47:

XMIi General Purpose Register (XGPR)
BB + 0C

3
1

XMI General Purpose Register

(XGPR)

R/W

|
msb-p006-89

Figure 4—48:

KA64A Control and Status Register (RCSR)
BB +10

332222222 22
10987654321

PYida’iaid’iaiiaidaiili
98765432109

5 43

LEE tT Ty tI CT wee |

LUxca Revision (XCA REV)
Second Error (SE) R/WI1C

Control/Status

——ee

——'
==

Write Buffer Disable (WBD) R/W
Auto Retry Disable (ARD) R/W
Enable Self-Invalidates (ESI) R/W
Interprocessor Interrupt Disable (IPID) R/W
Timeout Select (TOS) R/W

RAM Speed (RAM SPD) R/W
Corrected Read Data Interrupt Disable (CRDID)
Corrected Confirmation Interrupt Disable
(CCID) R/W

Warm Start (WS) RO
Boot Processor Disable (BPD) R/W
Boot Processor (BP) R/W
Commander NO ACK Received (CNAKR)
Unlock Write Pending (UWP) R/WI1C
Lockout

<1:0>

R/W

Lockout

Time

Select

(LTS)

R/W1C

R/W

RSSC Interrupt Priority Level <1:0>
Write Disable

(WD)

R/W

(RSSC

IPL<1:0>)

Errors

meme
——e=e

Cache Fill Error (CFE) R/WI1C
«6Write Data Parity Error (WDPE) R/W1C
XDPO Parity Error (XDPOPE) R/W1C
XDP1 Parity Error (XDP1PE) R/W1C
XCA Parity Error (XCAPE) R/W1C
msb—p007r=-89

4—26

VAX 6000—400 Mini-Reference

R/W

4.4 Machine Checks
Figure 4—49 showsthe parameters that are pushed on the stack in response
to a machine check. Table 4—5 lists these parameters. Note that machine
checks are taken regardless of the current IPL. If the machine check
exception vector bits (<1:0>) are not both one, the operation of the processor
is undefined. The exception is taken on the interrupt stack and the IPL is
raised to 1F (hex).

Figure 4-49:

The Stack In Response to a Machine Check
BYTE COUNT

MACHINE CHECK CODE

SP+4

VIRTUAL ADDRESS

SP+8

VIRTUAL INSTRUCTION BUFFER ADDRESS

SP+C

INTERRUPT STATE

SP+10

INTERNAL STATE

SP+14

INTERNAL REGISTER

SP+18

PROGRAM COUNTER

SP+1C

PROCESSOR STATUS LONGWORD

SP+20
meb-0180-89

KA64A CPU Module Registers 4—27

Table 4—5:

Machine Check Parameters

Parameter

Value (hex)
or Bit
Description

Byte Count
(SP)

Size of stack frame in bytes, not including PSL, PC, or byte count longword

Machine check code
(SP+4)

Floating-point operand or result transfer error

Floating-point reserved instruction

Floating-point operand parity error

Floating-point unknown status error

Floating-point returned result parity error

Translation buffer miss in ACV/TNV microflow

Translation buffer
croflow

Undefined INT.ID value

Undefined MOVCxstate

Undefined instruction trap code

Undefined control store address

Cache read tag/data parity error

DAL busor data parity read error

DAL buserror on write or clear write buffer

Undefined bus error microtrap

Virtua] address

<31:0>

Current contents of VAP register

Virtual instruction buffer
address

<31:0>

Current virtual instruction buffer address

Interrupt state
(SP+10)

<22>

ICCSbit <6>

<15:1>

SISR bits <15:1>

<31:24>

Difference between current PC and PC of op-

<20:18>

Addressof last memory reference

(SP+8)

hit

in ACV/TNV mi-

(SP+C)

Internal state
(SP+14)

4—-28

VAX 6000—400 Mini-Reference

code

Table 4—5 (Cont.): Machine Check Parameters
Parameter

Value (hex)

or Bit

Description

<17:16>

Data length of last memory reference

<15:8>

Opcode

<3:0>

Reserved

Internal register

<31:0>

Program counter

<31:0>

PC at the start of the current instruc-

Processor status longword
(SP+20)

<31:0>

Current contents of PSL

(SP+18)

(SP+1C)

tion

KA64A CPU Module Registers

4—29

4.5 Parse Trees
Figure 4-50:
=

(select

Machine Check Parse Tree
one)

MCHK_FP_ PROTOCOLERROR

(01 hex)
ym

MCHK_FPILLEGAL_OPCODE (02 hex)

MCHKFP _OPERAND_ PARITY

(03

hex)

MCHK_FP_UNKNOWNSTATUS (04 hex)

™

hex)

F-chip operand parity error
F-chip unknown result

status

F-chip result parity error

MCHK_TBM_ACV_TNV (08 hex)

(05

F-chip illegal opcode

MCHKTBHACV_TNV (09 hex)

TB miss status during ACV/TNV
processing

MCHKFP_RESULTS PARITY

F-chip protocol error

MCHK_INTIDVALUE (0A hex)
MCHKMOVCSTATUS (0B hex)
MCHK_UNKNOWNIBOX_TRAP

(0C

TB hit

status

processing

during ACV/TNV

Undefined interrupt ID value

MOVCx status encoding error

hex)

Unknown I-box trap

MCHK_BUSERR_READ_PCACHE

(select

all)

PCSTS<TAGPARITY_ERROR>

(PCSTS<8>)

PCSTS<P_ DATA_PARITYERROR>

neither

P-cache tag parity error on

m™

P-cache data parity error on

~™

Inconsistent status (one
both bits must be set)

D-stream read hit
(PCSTS<10>)

D-stream read hit

msb-p069-89

Figure 4—50 Cont’d. on next page

4—30

VAX 6000—400 Mini-Reference

Figure 4-50 (Cont.): Machine Check Parse Tree
MCHK_BUSERR_READ_DAL

6(select

(11 hex)

one)

PCSTS<DAL_DATA_PARITY_ERROR>

€6(select

one)

PCSTS<B_CACHE_HIT>

(PCSTS<12>)

“=

Backup cache data parity error
on D-stream read

B-

REXMI data parity error on
D-stream read

otherwise

PCSTS<BUS ERROR>

pees

(Select one)

SSCBTR<RWT>

(PCSTS<9>)

(PCSTS<11>)

(SSCBTR<30>)

RSSC bus

timeout

D=-stream read

(XBER<FCMD> = read) AND (XFADR = PCERR) (select one)
((XBER<3:1> = 1 hex) AND (XFADR = IPR126) )
XBER<RSE>

(XBER<17>)

XBER<RER>

(XBER<16>)

XMI read sequence error on first
quadword of D-stream read

XMI read error response on first
quadword of D-stream read

XBER<TTO> (XBER<13>)
ea(select one)
XBER<CNAK>

XBER<NRR>

(XBER<15>)

e—-

(XBER<18>)

otherwise

otherwise
/

NXM on first quadword of D-stream
read

XMI no read response for first
gquadword of D-stream read

No XMI grant to D-stream read

Inconsistent status

error bits

set)

(no XBER

™

Inconsistent status (machine
check during error interrupt)

™

Inconsistent status
error bits set)

(no PCSTS

msb-p070-89

Figure 4—50 Cont'd. on next page

KA64A CPU Module Registers

4-31

Figure 4—50 (Cont.):

Machine Check Parse Tree

MCHK_BUSERR_WRITE_DAL

(Select

one)

(SSCBTR<30>)

SSCBTR<RWT>

(12 hex)

otherwise

2”

MCHK_UNKNOWN_BUSERR_TRAP

RSSC bus timeout on write
clear write buffer
‘Inconsistent

bits set)

status

(no

error

(13 hex)
2 Unknown bus error trap
,

MCHK_UNKNOWN_CS_ADDR (0D hex)
otherwise

2”

Unexpected control

Inconsistent status
machine check code)

store address
(unknown

NOTES:
(select

one)

exactly one
than one is

(select

all)

than

case must
true, the

one

case may

be true.
status is
be

If zero or more
inconsistent.

true.

otherwise

- fall-through case for
options are true.

(select one)

if no other

neither

- fall-through case for
options are true.

(select all)

if none of the

The parse tree assumes that retry is enabled

(RCSR<ARD> = 0).
msb-p071-89

4—32

VAX 6000—400 Mini-Reference

Figure 4-51:

all)

XBER<KXFAULT>

XMI XFAULT signal asserted

(XBER<25>)

XBER<WEI>

(XBER<26>)

(select

ACKed parity error

—

Hard Error interrupt Parse Tree

IVINTR

received

Inconsistent
set)

XBER<IPE> (XBER<24>)
=m
(select one)

XBER<PE>

(XBER<23>)

otherwise

RCSR<WDPE>

(RCSR<4>)

XBER<FCMD>
-———»
(select

(PE

not

DAL write data parity error

RCSR<SE>

(RCSR<28>)

status

Second error

(XBER<3: 0>)
one)

write

———m

(select one)

XBER<KTTO> (XBER<13>)
=m
(select one)

XBER<CNAK> (XBER<15>)
—

XBER<WDNAK>

(XBER<20>)
-

Data NO ACK on write
No XMI grant on write

otherwise

NXM on write

Inconsistent status
error bits set)

otherwise
(no XBER

msb-p072-89

Figure 4-51 Cont’d. on next page

KA64A CPU Module Registers

4-33

Figure 4—51 (Cont.):
Y
§€=8(select

one)

XBER<RSE>

(XBER<17>)

XBER<RER>

(XBER<16>)

IDENT

XMI read sequence error on
return of interrupt vector

XMI read error response on
return of interrupt vector

B—-

No adapter ACK to IDENT

Hard Error interrupt Parse Tree

XMI no read response to
IDENT

No XMI grant on IDENT

XBER<TTO> (XBER<13>)
em
€6( select one)
XBER<CNAK>

XBER<NRR>

(XBER<15>)

(XBER<18>)

otherwise

™

Inconsistent status

(no XBER

=”

Inconsistent

(machine

Inconsistent status (no
or RCSR error bits set)

otherwise

neither

error

bits

set)

status

check during error interrupt)
XBER

NOTES:

(select one)

- only one case must be true.

(select

all)

neither

otherwise

than

one

than

true,

one

case

the

may

status
be

If none or more

inconsistent.

true.

fall-through

case

for

(select

all)

if none

fall-through

case

for

(select

one)

if no

the options are true.
options are true.

The parse tree assumes that retry is enabled

other

(RCSR<ARD> = 0).
msb-p073-89

4—34

VAX 6000—400 Mini-Reference

Figure 4-52:
—

(select

Soft Error interrupt Parse Tree

all)

PCSTS<INTERRUPT>

(PCSTS<5>)

(select all)

PCSTS<P_TAG_PARITY_ERROR>

(PCSTS<8>)
m P-cache tag parity error on
read,

write,

or invalidate

PCSTS<P_DATA_PARITY_ERROR> (PCSTS<10>)
= P-cache data parity error on
I-stream read hit
PCSTS<DAL_DATA_PARITY_ERROR> (PCSTS<9>)

(select one)

PCSTS<B_CACHEHIT>

otherwise

(PCSTS<12>)
™ Backup cache data parity
error on I-stream read or
nonrequested longword of
D-stream read

PCSTS<BUSERROR>

————

(select one)

SSCBTR<RWT>

(PCSTS<11>)

(SSCBTIR<30>)
™

XBER<FCMD> = read
—
(select one)

XBER<RSE>

XBER<RER>

RSSC bus
read
(XBER<3:0>)

(XBER<17>)

XBER<NRR>

read sequence

I-stream

XMI

XMI read error response on
first quadword of I-stream
read

(XBER<16>)

XBER<CNAK>

timeout on

™

XBER<TTO> (XBER<13>)
m———m
(select one)

error on

first quadword of I-stream
read

(XBER<15>)
m>- NXM on first quadword of
I-stream read
(XBER<18>)
™ XMI no read response for
first quadword of I-stream

otherwise

REXMI data parity error on
I-stream read or nonrequest-—
ed longword of D-stream read

otherwise

Figure 4—52 Cont'd. on next page

read

No XMI grant to I-stream

Inconsistent status
error bits set)

(no XBER

2»

Inconsistent status
error bits set)

(no PCSTS

read

msb-p074r—-89

KA64A CPU Module Registers

4—35

Figure 4—52 (Cont.):

RCSR<CFE>
(select

Soft Error Interrupt Parse Tree

(RCSR<27>)
one)

XBER<RSE>

(XBER<17>)

XBER<RER>

(XBER<16>)

XBER<TTO>

(XBER<13>)
one)

(select

XBER<NRR>

XMI read sequence error on
second gquadword of read
XMI read error response on
second quadword of read

(XBER<18>)

XMI no read response for
second quadword of read

XBER<CC>

Y
XBER<PE> (XBER<23>)

Inconsistent status
timeout reason)

otherwise

(no

NO ACKed parity error

(XBER<27>)
Corrected confirmation ~

(XBER<19>)

XBER<CRD>

LOCK>

(BCSTS<0>)

BCSTS<BTS_PERR>

(BCSTS<1>)

BCSTS<STATUS

—

(select all)

S,..
al

BCSTS<P1TS_PERR>

(BCSTS<2> )

BCSTS<P2TS_ PERR>

(BCSTS<3>)

l,.
~~

read data

(BCSTS<4>)

Backup tag store parity
error
Primary tag store parity
error

BCSTS<BUS_ERR>

Corrected

memory read

(lst

half)

Primary tag store parity
error

(2nd half)

DAL Protocol

Error

NOTES:
(select one)

- exactly one case must be true.

(select

- more

all)

otherwise

The

parse

than

tree

one

than

true,

one

the

case may

status
be

If none or more
inconsistent.

true.

fall-through

case

for

(select

one)

assumes

retry

enabled

(RCSR<ARD>

options are true.
that

if no

other

0).

msb-p075-89

4-36

VAX 6000—400 Mini-Reference

Chapter 5

MS62A Memory Registers
Table 5—1: MS62A Control and Status Registers
Name

Mnemonic

Address

Device Register

XDEV

BB!+ 00

Bus Error Register

XBER

BB + 04

Starting and Ending Address Register

SEADR

BB + 10

Memory Control Register 1

MCTL1

BB + 14

Memory ECC Error Register

MECER

BB + 18

Memory ECC Error Address Register

MECEA

BB + 1C

Memory Control Register 2

MCTL2

BB + 30

TCY Tester Register

TCY

BB + 34

Interlock Flag Status Register

IFLGn

BB+ n?

1"BB" refers to the base address of the XMI node, which is the address of the first loca-

tion in nodespace (see Table 3—1.)

2"»," depends on the Interlock Flag Status Register number (0-15)

MS62A Memory Registers

5-1

Figure 5-1:

Device Register (XDEV)
BB + 00

2i1
09
MUST

1 i
6 5

ZERO

0
Device

Device

Type

Revision

(4001)

(DREV)

msb-p042-89

Figure 5—-2:

Bus Error Register (XBER)
BB + 04

3 3222 2
1 098 7 6
| }ofo|

22222
4321 0
MBZ

l11idail
3210 9
MUST BE ZERO

| o|

MUST BE ZERO

Self-Test Fail

(STF)

R/w1c

(NSES)

Node-Specific
Error Summary
Read Data

NO ACK

(RDNAK)

R/W1C

Write Sequence Error (WSE)
Parity Error (PE)
R/WI1C
Corrected Confirmation (CC)

Node Reset (NRST)
Error Summary (ES)

WO
RO

R/W1iCc
R/W1C

msb-p043-89

5-2

VAX 6000—400 Mini-Reference

Figure 5-3:

Starting and Ending Address Register (SEADR)
BB + 10

332
10 9

22
1 0

[woz|

11
6 5

| vez |

Ending Address
(ENADR)

765

210

Li | | vz | | |

R/W

Starting Address (STRADR)
R/W
Interleave Address 2 (INAD2)
R/W
Interleave Address

(INADR1)

R/W

Interleave Address 0 (INADRO) R/W
Interleave Mode 1 (INTMl)
R/W
Interleave Mode 0 (INTMO)
R/W

msb-p044-89

Figure 5—4:

Memory Control Register 1 (MCTL1)
BB +14
Tidadlaizidaziididl
8765432109876«5

4321@«+0

|
Cc

a O—

PET yy eet EEE
|

7 6 5
1 0
3
Diagnostic Check

(DIAGCK)
R/W
MW Write Error

(MWRER)

R/W1C

Unlock Sequence Error
(UNSEQ)

R/W1C

— Lock Queue Error (LQERR)
— Enable Protection Mode
———e
——eeees

——eee

Memory

ECC Disable (ECCDIS)
R/W
ECC Diagnostic (ECCDIAG)
R/W
«Error

Summary

(ERRSUM)

(EPM)
R/W
Memory Valid (MEMVAL)
RO
6Inhibit CRD Status (ICRD)

RAM Type

Size

(RAMTYP)

(MEMSIZ)

R/W1C

R/W

msb-p045-89

MS62A Memory Registers

5-3

Figure 5-5:

Memory ECC Error Register (MECER)
BB + 18

33222222
1098765 4

1 |} fol fy |

MUST BE ZERO

Error Syndrome
Column Parity Error

Row Parity Error
Byte Write Error
CRD Error

(CRDER)

(ERSYN)

(CPER)

(RPER)
(BWERR)

R/W1C

RO
RO

ro—

High Error Rate (HIERR)
R/W1C
RER Error (RERER)
R/W1C
msb-p046-89

Memory ECC Error Address Register (MECEA)
BB +1C

io ft
aan

=
w
N

MH WwW

Figure 5-6:

3 2
ERROR

ADDRESS

(ERRAD)

| Bz |
msb-p047-89

VAX 6000—400 Mini-Reference

Figure 5—7:

Memory Control Register 2 (MCTL2)
BB + 30

3
1

111
7 6 5
MUST BE

Refresh Error
Disable

Hold

ZERO

(RERR)

(DISH)

6543210
MUST BE

ZERO

R/wic—

R/W

Refresh Rate<2> (RRB1)
Refresh Rate<1l> (RRB2)
Refresh Rate<0> (RRBO)
Arbitration Suppression
Arbitration Suppression

R/W
R/W
R/W
Control<1l>
Control<0>

(ARBSC1)
(ARBSCO)

R/W
R/W
msb-p0 48-89

3
1

TCY Tester Register (TCY)
BB + 34

oO WwW

Figure 5-8:

MUST BE

ZERO

ECC Test

TCY Mode

(TCYM)

TCY Refresh Request

(ECCT)

(TRR)

—

msb-p049-89

MS62A Memory Registers 5-5

Figure 5-9:

Interlock Flag Status Registers (IFLGn)
BB + relative address

3322
109 8
|

Jo|

Interlock Address
Lower
Interlock

Interlock

Bit

Interlock Flag n

where n

(0-15)

<5>

(IADR)

ID Bits

<4:0>

|
(LIID)

0
|

ro—

RO
R/wic

(IIDB)

(IFLG)

is the number of the Interlock Flag Register:
Register

Relative Address

IFLGO

BB + 20

IFLG1

BB + 24

IFLG2

BB + 28

IFLG3

BB + 2C

IFLG4

+ 40

IFLG5

BB + 44

IFLG6

+ 48

IFLG7

+ 4C

IFLG8

+ 80

IFLG9

+ 84

IFLG10

BB + 88

IFLG11

BB + 8C

IFLG12

+ 100

IFLG13

+ 104

IFLG14

BB + 108

IFLG15

+ 10C
msb-p050-89

5-6

VAX 6000-400 Mini-Reference

Chapter 6

DWMBA Adapter Registers
The DWMBAadapter consists of two modules: an XMI module in the XMI
card cage and a VAXBI module in the VAXBI card cage. Table 6—1 lists
the DWMBAregisters: some of which are XMI required registers, some
DWMBA/A registers, some DWMBA/B registers, and the VAXBI Device
Register for the DWMBA/B module.
Register addresses for a particular device in a system are found by adding
an offset to the base address for that device. To distinguish between
addresses in VAXBI address space and addresses in XMI address space,
we use the following convention:
lowercase bb + offset indicates an address in VAXBI address space
uppercase BB + offset indicates an address in XMI address space

DWMBAAdapter Registers

6—1

Table 6—1:

DWMBA Registers

Name

Mnemonic!

Address”

Device Register

XDEV

BB + 00

Bus Error Register

XBER

BB + 04

Failing Address Register

XFADR

BB + 08

Responder Error Address Register

AREAR

BB + 0C

DWMBA/A Error Summary Register

AESR

BB + 10

Interrupt Mask Register

AIMR

BB + 14

Implied Vector Interrupt Destination/Diagnostic

AIVINTR

BB + 18

Diag 1 Register

ADG1

BB + 1C

Control and Status Register

BCSR

BB + 40

DWMBA/SB Error Summary Register

BESR

BB + 44

Interrupt Destination Register

BIDR

BB + 48

Timeout Address Register

BTIM

BB + 4C

Vector Offset Register

BVOR

BB + 50

Vector Register

BVR

BB + 54

Diagnostic Control Register 1

BDCR1

BB + 58

Reserved Register

BB + 5C

Device Register®

DTYPE

bb + 00

1The first letter of the mnemonic indicates the following:
X=XMI register, resides on the DWMBA/A module
A=Resides on the DWMBA/A module
=Resides on the DWMBA/B module;accessible from the XMI bus

2The abbreviation "BB"refers to the base address of an XMI node(the addressofthe first loca-

tion of the nodespace). The abbreviation “bb” refers to the base address in VAXBI nodespace.
8This is a VAXBI register. For information on other VAXBI registers, see the VAXBI Options Handbook.

6-2

VAX 6000—400 Mini-Reference

Figure 6-1:

Device Register (XDEV)
BB + 00

3
1

11
6 5
Device Revision

0
Device Type

(2001)

msb-p051-89

Figure 6-2:

Bus Error Register (XBER)
BB + 04

332222222222i112313a34a3a3atatziziizu
171098687654321098765 43210 9

4 3

)

LETT EE Erez] rex |
|

LUpailing Command
Failing Commander

Identification
RO
Self-Test Fail (STF)
R/wic
Extended Test Fail (ETF)
R/W1c

Node-Specific Error Summary
(NSES)

Commander Errors
—e
——=ee

———os

—=—=0Na=—=u=s=»>

Transaction Timeout (TTO)
R/Wwic
Reserved; must be zero
Command NO ACK (CNAK)
R/W1c
Read Error Response (RER)
R/wic
€=8Read Sequence Error (RSE)
R/WI1C

NO Read Response

(NRR)

R/WI1C

Corrected Read Data (CRD)
Write Data NO ACK (WDNAK)

R/W1C
R/W1Cc

Responder Errors
mer

——e—e~ee
aEEeEEeeD

§=Read/IDENT Data NO ACK

(RIDNAK)

R/wW1c

Write Sequence Error (WSE)
R/W1C
Parity Error (PE)
R/W1C
Inconsistent Parity Error (IPE)
R/WI1C

Miscellaneous

ee Write Error Interrupt

ae
ene
—eEme
—~Tees

(WEI)

6XMI Fault (XFAULT)
R/wic
§€6COrrected Confirmation (CC)
«68XMI Bad (XBAD)
R/W
Node Halt (NHALT)
R/W
Node Reset (NRST)
R/W
Error Summary (ES)
RO

R/W1C
R/W1C

msb—p004r-89

DWMBAAdapter Registers

6-3

Figure 6-3:

Falling Address Register (XFADR)
BB + 08

3 3 2
1 0 9
|

Failing Address
Failing Length

(FLN)

RO
msb-p052-89

Figure 6—4:

Responder Error Address Register (AREAR)
BB + 0C

3 3 2
10 9
|
L

Responder Failing Address

Responder Failing Length

(RFLN)

RO
msb-p053-89

6-4

VAX 6000-400 Mini-Reference

Figure 6-5:

BB + 10

L {ez |
L

XBI CABLE OK
RO

11
6 5

22
6 5

3 3
1 0

DWMBA/A Error Summary Register (AESR)

87654321 0

Failing Command
(ECMD)

Failing Commander ID
(EID)
RO

XBIA INTERNAL ERROR
R/W1C
I/O WRITE FAILURE
R/W1C
BCI AC LO
R/W1C
IBUS DMA-A DATA PE
R/W1C
IBUS DMA-A C/A
PE
R/W1C
IBUS DMA-B DATA PE
R/WiC
IBUS DMA-B C/A
PE
R/W1C
IBUS
CPU DATA
PE
R/W1C
msb-p054-89

DWMBAAdapter Registers

6-5

Figure 6-6:

3 3
1 0

222
8 7 6

Interrupt Mask Register (AIMR)
BB +14
22222ia141iqaqctrTiti1rtliiaiii
43210987645 432

54321

Lt| ee TTT TTT EY fof | ms se zero | | | | | |
L piagnostic
Read or Write
RO
Diagnostic Read
or Write
RO
INTR on IBUS
DMA-A C/A
PE
R/W
Diagnostic Read
or Write
RO
INTR on IBUS
DMA-B C/A PE
R/W
INTR

IBUS

CPU DATA PER

—-

INTR

on
on
on
on
on
on

Command NO ACK/NXM
R/W
R/W
Read Error Response

Read Sequence Error

R/W

No Read Response
R/W
Corrected Read Data
R/W
Write Data NO ACK R/W

Read/IDENT

data NO ACK

R/W

Write Sequence Error
R/W
Parity Error
R/W
R/W
INTR on Corrected Confirmation
Enable IVINTR Transactions
R/W
msb-p055-89

Figure 6-7:

Implied Vector Interrupt Destination/Diagnostic Register
(AIVINTR) BB + 18

3
1
|

11
6 5
MUST BE ZERO

0
IVINTR Destination

R/W

msb-p056-89

6-6

VAX 6000—400 Mini-Reference

Figure 6-8:

Diag 1 Register (ADG1)
BB +1C

3 3
1 0
|

76543210

|
L

MUST BE ZERO

Auto Retry Disable

(ARD)

(MBZ)

| |

| | mez

R/W

FORCE OCTAWORD XFER

R/W

FORCE DMA-A BUSY
R/W
FORCE DMA-B BUSY
R/W
GEN BAD IBUS RCV PAR
R/W
GEN BAD IBUS XMIT PAR R/W
msb-p057=-89

Control and Status Register (BCSR)
BB + 40

Figure 6-9:

54321

| |

MUST BE ZERO

| fol | | |
BI

BAD

Ro —

BI Interlock Read Failed Mask
BI Self-test LED
IBUS Parity Error Interrupt Mask
Enable XBI

Interrupts

(to XMI

processor(s))

R/W
R/W
R/W

R/W

msb-p058-89

DWMBAAdapter Registers

6-7

Figure 6-10:

DWMBA/B Error Summary Register (BESR)
BB + 44

11
7 6

1
1

MUST BE ZERO

87654321 0

EERREREE

Interrupt Sent Status
ro——!
_|
XBI Interrupt~-Pending Status
RO
BI Interrupt-Pending Status
RO
Multiple CPU Errors
R/W1C

Command/Address Fetch Failed

Slave Sequencer Transaction Failed RO
Master Sequencer Transaction Failed RO
Illegal CPU Command RO
BI Interlock Read Failed
R/W1C
IDENT Error
R/W1C
XBIB-Detected IBUS Parity Error R/W1C
msb-p059-89

Figure 6-11:

Interrupt Destination Register (BIDR)
BB + 48

3
1

iil
6 5

Diagnostic Read/Write

R/W

Interrupt Destination

R/W

msb-p060-89

Figure 6-12:

Timeout Address Register (BTIM)
BB +4C

33 2
10 9
|

Length

DMA Address-

RO
msab-p061-89

6-8

VAX 6000—400 Mini-Reference

Figure 6-13:

Vector Offset Register (BVOR)
BB + 50

11
6 5

9 8

MUST BE ZERO
Vector Offset Register

(VOR)

0
MUST BE ZERO

r/w—
msb-p062=-89

Figure 6-14:

Vector Register (BVR)
BB + 54

MUST BE ZERO

XBI Vector

R/W

| mp2

msb-p0 63-89

Figure 6-15:

Diagnostic Control Register 1 (BDCR1)
BB + 58

765432i1
MUST BE ZERO

Flip FADDR Bit 1

Flip Bit 29

R/W

R/w—!

£40

mp2

BIIC Loopback Mode
R/W
Force BCI Bad Parity
R/W
msb-p0 64-89

DWMBAAdapter Registers

6—9

Figure 6-16:

VAXBI Device Register (DTYPE)
bb + 00

1 i
6 5
Device Revision

R/W

0
Device Type

(2107)

R/W

msb-p065=-89

6-10

VAX 6000—400 Mini-Reference

Index
A
Accelerator Control] and Status

Backup Cache Backup Tag Store
Register, 4-8
Backup Cache Control Register,
4—10
Backup Cache Error Address
Register, 4-10
Backup Cache Flush Backup Tag
Store Register, 4-11
Backup Cache Flush Primary Tag
Store Register, 4—11
Backup Cache Index Register, 4-9
Backup Cache Primary 1 Tag Store,
4—8
Backup Cache Primary 2 Tag Store,
4-8
Backup Cache Refresh Register,
4—9
Backup Cache Status Register,
4—10
BCBTS, 4-8
BCCTL, 4-10
BCERR, 4—10
BCFBTS, 4—11
BCFPTS, 4-11
BCIDX, 4-9
BCPITS, 4-8

BCP2TS, 4-8
BCRFR, 4-9
BCSR, 6—7
BCSTS, 4-10
BDCRI1, 6-9
BESR, 6-8
BIDR, 6-8
BOOT command, 1-8
qualifiers, 1-9
sample, 1-9
BTIM, 6-8
Bus Error Register, 4-24, 5-2, 6-3
BVOR, 6-9
BVR, 6-9

C
Console commandsand qualifiers,
1-4 to 1-6
Console control characters,

1—7

Console error messages, 1-11 to
1-19
Console Saved Processor Status
Longword, 4—6
Console Saved Program Counter
Register, 4-6
Control and Status Register, 6-7
Control panel, 1-2
Control panel status indicator lights,
1—4
Control Register 0, 4-17
Control Register 1, 4-18
Control Register Address Decode
Mask Register, 4-19
Control Register Base Address
Register, 4—19
Control Register Write Enable
Register, 4—15

index—1

CRADMR, 4-19
CRBADR, 4-19
CREGO, 4-17
CREGI, 4-18
CREGWE, 4-15

Interval Counter Register, 4-22
IORESET, 4-7
IPORT, 4-18

KA64A Control and Status Register,
4—26
KA64A internal processor registers,
4-2 to 4-5
KA64A LEDsafter self-test, 2—4
KA64A registers in XMI private
space, 4-14 to 4-15
KA64A XMI registers, 4—23
Key switch
lower, 1-3
upper, 1-3

Device Register, 4—23, 5-2, 6-3
Diag 1 Register, 6—7
Diagnostic Control Register 1, 6—9
DTYPE, 6-10
DWMBAS/A Error Summary Register,
6—5
DWMBA/JB Error Summary Register,
6-8
DWMBAregisters, 6-2

E
EEADMR, 4-19
EEBADR, 4-19
EEPROM Address Decode Mask
Register, 4—19
EEPROM Base Address Register,
4-19
Error messages, 1-11 to 1-19
F
Failing Address Register, 4—25, 64

H
Hard error interrupt parse tree,
4-33 to 4-34

I/O Reset Register, 4—7
IFLGn, 5-6
Implied Vector Interrupt
Destination/Diagnostic
Register, 6-6
Interlock Flag Status Registers, 5-6
Interrupt Destination Register, 6—8
Interrupt Mask Register, 6-6

index—2

Machine Check Error Summary
Register, 4-5
Machine check parameters, 4—28 to
4-29
Machine check parse tree, 4-30 to
4—32
Machine checks, 4-27 to 4-29
MCESR, 4-5
MCTLI1, 5-3
MCTL2, 5-5
MECEA, 5-4
MECER, 5—4
Memory Control Register 1, 5-3
Memory Control Register 2, 5—5
Memory ECC Error Address
Register, 5-4
Memory ECC Error Register, 5—4
MS62A control and status registers,

5-1

O
OPORT, 4-17
p
Parse trees, 4-30 to 4-36

PCERR, 4-12
PCIDX, 4-12
PCSTS, 4-13
PCTAG, 4-11
Primary Cache Error Address
Register, 4—12
Primary Cache Index Register,
4—12
Primary Cache Status Register,
4-13
Primary Cache Tag Array Register,
4—11

R
R5 bit functions
ULTRIX, 1-10
VMS, 1-10
RCSR, 4-26
Register bit types, 4—1
Registers
DWMBA, 6-2
finding in VAXBI address space,
3-6 to 3-7
finding in XMI address space,

9.5

KA64A internal processor, 4—2
to 4-5
KA64A in XMI private space,
4-14 to 4-15
KA64A XMI, 4-23
MS62A control and status, 5-1
VAXBI, 3-8
Responder Error Address Register,
6-4
Restart button,

1-3

RSSC Base Address Register, 4—15
RSSC Bus Timeout Control Register,
4—16
RSSC Configuration Register, 4—16
RSSC Input Port Register, 4-18

RSSC Output Port Register, 4—17

SAVPSL, 4-6
SEADR, 5-3
Self-test results, 2-1
SID, 4-7
Soft error interrupt parse tree, 4—35
to 4-36
SSCBAR, 4-15
SSCBTR, 4-16
SSCCNR, 4-16
SSCICR, 4-22
Starting and Ending Address
Register, 5-3
System Identification Register, 4—7

TBDATA, 4-7
TBTAG, 4-6
TCRO, 4—20
TCR1, 4-21
TCY, 5—5
TCY Tester Register, 5—5
Timeout Address Register, 6—8
Timer Control Register 0, 4-20
Timer Control Register 1, 4-21
Timer Interrupt Vector Register 0,
4-21
Timer Interrupt Vector Register 1,
4-22
TimerInterval Register 0, 4-20
Timer Interval Register 1, 4-21
Timer Next Interval Register 0,
4-20
Timer Next Interval Register 1,
4-22
TIRO, 4-20
TIR1, 4-21
TIVRO, 4-21
TIVR1, 4-22
TK70 lights, 2-5
TNIRO, 4-20
TNIR1, 4-22
Translation Buffer Data Register,
4—7

SAVPC, 4-6

index—3

Translation Buffer Tag Register,
4-6

XBER, 4-24, 5-2, 6-3
XDEV, 4-23, 5-2, 6-3
XFADR, 4-25, 64
XGPR, 4—26
XMI addressing, 3—4
XMI address space, 3-5
XMI General Purpose Register,
4-26
XMI V/O space addressallocation,
3-3
XMI memory and I/O address space,
3-2

VAX 6000-400 slot numbers, 3-1
VAXBI address space, 3-6 to 3-7
VAXBI Device Register, 6-10
VAXBI nodespace and window space
address assignments, 3—7
VAXBIregisters, 3-8
Vector Offset Register, 6-9
Vector Register, 6—9

index—4