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Document:	VAXstation 2000 and MicroVAX 2000 Technical Manual Addendum: DHT32 Asynchronous Serial Line Option
Order Number:	EK-ASYNC-IM
Revision:	1
Pages:	30
Original Filename:

OCR Text

VAXstation 2000 and MicroVAX 2000
Technical Manual Addendum:
DHT32 Asynchronous Serial Line Option

Order Number EK-ASYNC-IM-001

digital equipment corporation
maynard, massachusetts

October 1987

The infortnation in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation.

Digital Equipment Corporation assumes no responsibility for any errors that may appear in

this document.
The Software, if any, described in this document is furnished under a license and may be used
or copied only in accordance with the terms of such license. No responsibility is assumed for
the use or reliability of Software or equipment that is not supplied by Digital Equipment
Corporation or its affiliated companies.
Copyright ©1987 by Digital Equipment Corporation.

The following are trademarks of Dig
DEC
DEC/CMS

D1BOL

UNIBUS

EduSystem

VAX

DEC/MMS

IAS

VAXcluster

DECnet

MASSBUS

VMS

DECsystem-10

PDP

DECSYSTEM-20

PDT

DECUS

RSTS

DECwriter

RSX

FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio
frequency energy. The equipment has been type tested and found to comply wlth the limits
for a Class A Computing device pursuant to Subpart J of Part 15 of FCC Rules, whlch are

designed to provide reasonable protection against such radio frequency interference when
operated in a commercial envlronment.

Operation of this equipment in a residential area

may cause interference, in which case the user at his own expense may be required to take
measures to correct the interference.

Introduction

Physical Description

2.1

DHT32 Controller Module

2.2

DHT32 Driver/Receiver Module

2.3

Electrical Characteristics

2.4

Environmental Specifications

Controller Module Input/Output Connectors

Functional Description

4.1

Overview of the Controller Module

4.2

Interrupts

4.3

Registers

4.4

Control And Status Register

4.5

Receive Buffer Register

4.6

Receive Timer Register

4.7

Line Parameter Register

4.8

Transmit FIFO Data Register

4.9

Transmit FIFO Size Register

4.10

Line Status Register

4.11

Line Control Register

4.12

Transmit Enable Register

5
5.1
5.1.1

Internal Diagnostics
Self-Test
Self-Test Codes

24
24
25

5.2

Background Test

5.3

Reset State

5.4

ROM Option

iii

Figures
1

DHT32 Controller Module Layout

DHT32 Option Block Diagram

Control And Status Register

Receive Buffer Register

Receive Timer Register

Line Parameter Register

Transmit FIFO Data Register

Transmit FIFO Size Register

Line Status Register

Line Control Register

Transmit Enable Register

/Ä^^
»

Tables
1

Storage Conditions

Operating Conditions

Nonoperating Conditions

Controller Module Connectors J3 and J4

Controller Module Connector Jl

Interrupts

Registers

Binary Codes Used to Select Baud Rates

Self-Test Error Codes

^ssw?!s^
1

1 Introduction
The DHT32 serial line Option adds eight serial lines to the MicroVAX 2000
System. The serial lines are implemented with a DHU style interface and
support data lead (no modern control) type serial lines.

The DHT32 Option consists of a Controller module, a driver/receiver module
and cables.

2 Physical Description
This section describes the DHT32 option and teil how it interfaces with the
MicroVAX 2000 System unit.

2.1 DHT32 Controller Module
The DHT32 Controller module is a two-layer printed circuit board measuring
26.42 centimeters (10.4 inches) by 19.31 centimeters (7.6 inches), and
weighing 297.67 grams (10.5 ounces). It connects to the MicroVAX 2000
System module by way of two 40-pin connectors (J3 and J4, on the DHT32
Controller module connect to J8 and Jll, respectively, on the System
module). All power, ground, and data/address lines come through these
connectors. In addition, there is a 34-pin connectors (Jl) which connect to
the driver/receiver module. The driver/receiver module receives its power
and data lines through this connector, so the System module is actually
supplying the power for the entire DHT32 option.

2.2 DHT32 Driver/Receiver Module
The DHT32 driver/receiver module is a four-layer printed circuit board
measuring 8.13 centimeters (3.20 inches) by 13.21 centimeters (5.20 inches),
and weighing 99.23 grams (3.5 ounces). It is mounted in the expansion
adapter with a 34-pin ribbon cable that connects connector J2 (on the
driver/receiver module) to the Controller module's connector Jl. Connector
Jl on the driver/receiver module is used with an eight line cable concentrator
to connect to terminals or other peripherals.

DHT32 Asynchronous Serial Line Option

2.3 Electrical Characteristics
The power for the DHT32 Controller module and the driver/receiver module
is supplied by the MicroVAX 2000 System module through connectors J3 and
J4 on the Controller module. The Controller module's power requirements
are listed as follows.
«

+12 volts at 700 mA maximum

—12 volts at 120 mA maximum

•

H-5 volts at 1.5 A maximum

2.4 Environmental Specifications
The DHT32 asynchronous serial line Option environmental specifications
are listed in Table 1, Table 2, and Table 3. Refer to Table 1 for storage
conditions, Table 2 for operating conditions, and Table 3 for nonoperating
conditions.

Table 1:

Storage Conditions

Parameter

Range

Temperature ränge

5 °G (41 °F) to 50 °C (122 °F)

Relative humidity

10% to 95% (noncondensing)

Maximum wet bulb
temperature

32 °C (90 °F)

Maximum dew point

2 °C (36 °F)

Altitude

2400 m (8000 feet) at 36 °C (96 °F)

DHT32 Asynchronous Serial Line Option

Table 2:

Operating Conditions

Parameter

Range

Temperature ränge

10 °C (50 °F) to 40 °C (104 °F)

Temperature
change rate

11 °C (20 °F) degree/hour maximum

Relative humidity

10% to 90% (noncondensing, no diskette)

20% to 80% (diskette in use)
Maximum wet bulb

28 °C (82 °F)

temperature

Minimum dew point

2 °C (36 °F)

Altitude

2400 m (8000 feet) at 36 °C (96 °F)

Heat dissipation

17.4 watts maximum

Table 3:

Nonoperating Conditions

Parameter

Range

Temperature ränge

-40 ?C (-40 °F) to 66 °C (151 °F)

Relative humidity

95% at 66 °C (151 °F) (may condense)

Maximum wet bulb
temperature

28 °C (82 °F)

Minimum dew point

2 °C (36 °F)

Altitude

4900 m (16000 feet)

]

/0?®\

DHT32 Asynchronous Serial Line Option

3 Controller Module Bnput/Output Connectors
Connectors J3 and J4 on the Controller module share data/address lines,
control lines, and several power and ground lines with connectors J8 and
Jll, respectively, on the System module. The Signals on connectors J3 and
J4 are listed in Table 4.

Table 4:

Controller Module Connectors J3 and J4

Signal

J3-1

+ 5 volts

J4-1

GND

J3-2

+5 volts

J4-2

GND

J3-3

+ 12 volts

J4-3

BDAL31 H

J3-4

-12 volts

J4-4

BDAL30 H

J3-5

GND

J4-5

BDAL29 H

J3-6

BCLKO H

J4-6

BDAL28 H

J3-7

BRESET L

J4-7

BDAL27 H

J3-8

BVAS L

J4-8

BDAL26 H

J3-9

VDS L

J4-9

BDAL25 H

J3-10

BWRITE L

J4-10

BDAL24 H

J3-11

N/C

J4-11

BDAL23 H

J3-12

N/C

J4-12

BDAL22 H

J3-13

GND

J4-13

GND

J3-14

GND

J4-14

GND

J3-15

CAS3L

J4-15

BDAL21 H

J3-16

CAS2L

J4-16

BDAL20 H

J3-17

CAS1 L

J4-17

BDAL19 H

J3-18

CASO L

J4-18

BDAL18 H

J3-19

N/C

J4-19

BDAL17 H

J3-20

N/C

J4-20

BDAL16 H

J3-21

N/C

J4-21

BDAL15 H

J3-22

N/C

J4-22

BDAL14 H

J3-23

OPTROMENA L

14-23

BDAL13 H

DHT32 Asynchronous Serial Line Option

Table 4 (Cont.):

Controller Module Connectors J3 and J4

Signal

13-24

OPTV1DENA L

J4-24

BDAL12 H

J3-25

OPTIRQ L

J4-25

BDAL11 H

J3-26

OPTEOF L

J4-26

BDAL10 H

J3-27

GND

J4-27

GND

J3-28

GND

J4-28

GND

J3-29

INTENA L

J4-29

BDAL09 H

13-30

SCYC/1AD2 H

J4-3Ü

BDAL08 H

J3-31

DCYC/IAD1 H

J4-31

BDAL07 H

J3-32

STFH/IADO H

J4-32

BDALÜ6 H

J3-33

N/C

J4-33

BDAL05 H

J3-34

GND

J4-34

BDAL04 H

J3-35

N/C

J4-35

BDAL03 H

J3-36

GND

J4-36

BDAL02 H

J3-37

N/C

J4-37

BDAL01 H

J3-38

GND

J4-38

BDAL00 H

J3-39

OPT.PRESENT L

J4-39

GND

J3-40

+5 volts

14-40

GND

DHT32 Asynchronous Serlal Line Option

Connector Jl on the Controller module connects the Controller module,
Channel numbers 0 through 7, to the driver/receiver module. Connector
J2 is not used on this module. The Signals on connector Jl are listed in
Table 5.

Table 5:

Controller Module Connector J1

Signal

Jl-1

BSDO 7 H

Jl-18

-12 volts

Jl-2

+5 volts

Jl-19

N/C

H-3

BSDO 6 H

Jl-20

BSDI 7 H

Jl-4

GND

Jl-21

GND

)\-5

BSDO 5 H

Jl-22

BSDI 6 H

Jl-6

GND

Jl-23

GND

Jl-7

BSDO 4 H

Jl-24

BSDI 5 H

Jl-8

GND

Jl-25

GND

Jl-9

BSDO 3 H

Jl-26

BSDI 4 H

Jl-10

GND

Jl-27

GND

Jl-11

BSDO 2 H

Jl-28

BSDI 3 H

Jl-12

GND

Jl-29

GND

Jl-13

BSDO 1 H

Jl-30

BSDI 2 H

Jl-14

GND

Jl-31

GND

Jl-15

BSDO 0 H

Jl-32

BSDI 1 H

Jl-16

+ 12 volts

Jl-33

GND

Jl-17

N/C

Jl-34

BSDI 0 H

•"^^V

DHT32 Asynchronous Serial Line Option

4 FunctäonaO Description
^jp^

The functional description of the DHT32 Option and its registers is described
in the following sections.

4.1 Overview of the Controller Module
The DHT32 Controller module implements a DHU compatible device on the
MicroVAX 2000 System unit. The major features of the module are listed as

follows.
•

Eight data lead only serial lines at independent baud rates up to 38400
bits per second.

Two hundred and fifty six
programmable hold-off timer.

character

input

Sixty four character per line Output FIFO buffer.

FIFO

buffer

The major differences between the DHT32 Controller module
implemetation) and the other DHU-like products are listed below.

/^^

with

(DHU

•

The module has eight versus sixteen serial lines.

The module has no output direct memory access (DMA) support.

The module has no modern control.

These lines connect to terminals or other peripherals by way of a
driver/receiver module mounted in the MicroVAX 2000 expansion adapter.
The driver/receiver module converts TTL levels from the main Controller to
DEC423 levels for transmission outside of the enclosure. Passive devices
for added electrostatic discharge (ESD) and electrical overstress (EOS)
protection are also resident on this board.

DHT32 Asynchronous Serial Line Option

The Controller module layout is shown in Figure 1.

Figure 1:

DHT32 Controller Module Layout

0 Q
CD

D
cd

□

D
DD

■\

DHT32 Asynchronous Serial Line Option

A block diagram of the DHT32 Option is shown in Figure 2.
Figure 2:

DHT32 Option Block Diagram

CONNECTOR

z\
646 XCVRS

LATCH

V-l

\7
INTERRUPT
GENERATION

FPLS

QBUS SIGNALS

CONTROLLER
DC7045

OCTART
DC7O44

\z
0

RAM

DHIVER/RECEIVER
BOARD

/^y

DHT32 Asynchronous Serial Line Option

4.2 Interrupts
The receiver Interrupt is enabled by setting bit 0 in the video select register
(VDCSEL). This bit selects the interrupt source for vector 244h as the DHT32
Controller module. The other bits in this register should always be written
to 0.
Two interrupts are used for program control of the DHT32 Controller
module. Refer to Table 6 below.

Table 6:

Interrupts

Interrupt

Vector

Source Mask Bit

244h

Receive FIFO not empty

248h

Transmit FIFO empty

NOTE: The video select register address is 2008.000E (hexadecimal).
The receiver interrupt is qualified on the module by any value that was
programmed into the hold-off timer for receive interrupts. This concept is
explained in Section 4.4.

4.3 Registers
All registers on the Controller module are word addressable. They should
not be addressed as longwords. Table 7 briefly describes the registers.

Table 7:

Registers

CSR Address
(hexadecimal)

Type

Control and Status (SLU.CSR)

3800.0000

r/w*

Receive buffer (SLU.RBUF)

3800.0002

ro*

Receive timer (SLU_RTIM) + §

3800.0002

wo*

Line parameter (SLUJLPR) $

3800.0004

r/w

Transmit FIFO data (SLU.DATA) t

3800.0006

*Read/write => r/w; write only = wo; read only =» ro
§Able to be read/written as a Single byte only or as part of the word it is in.

tAvailable only when SLU.CSR |0:3j equal 0.

JA separate register is available for each line based on the value of SLU.CSR (0:3].

DHT32 Asynchronous Serial Line Option

/^
1

Table 7 (Cont.):

Registers
CSR Address
(hexadecimal)

Type

3800.0006

Line Status (SLU.STAT) X %

3800.0007

Line control (SLU.CNTL) X

3800.0008

r/w

Not used X ®

3800.OOOA

r/w

Transmit enable X

3800.000C

r/iv

Not used X ®

3800.000E

r/w

Transmit FIFO size (SLU.DATA) jf

®Not used on this module. These registers are normalty used to implement DMA output transfers and are listed here only because they appear in the address Space.
§Able to be read/vvritten as a Single byte only or as part of the word it is in.
JA separate register is available for each line based on the value of SLU.CSR |0:3).

Registers are accessed by instructions which use the register address as a
source or destination. However, before multiple registers are accessed, the
Channel number should be written to the CSR address (3800.0000). For
example the following I/O comimands would be executed to read the line
Status register of Channel number 3.
MOVB

#CHAN,@#CSR

;WRITE CHANNEL NUMBER TO CSR

MOV

@#CSR+6,R0

;READ THE LINE STATUS REGISTER

Example:
CHAN

OerOOOll(b)

where

e = the R.IE bit

r = the RESET bit
0011(b)

= Channel

number

CSR + 6 addresses a block of 16 line Status registers, only eight of which are
used. The DHT32 hardware indexes this address by three, thereby selecting
line Status register of Channel number 3.

DHT32 Asynchronous Serial Line Option

4.4 Control And Status Register
Figure 3 shows the bits in the control and Status register (SLU_CSR).

Figure 3:
Address
15

Control And Status Register
:

3800.0000
13

Data Bit

Definition

<15> (RO)

Tranmitter ready (T.RDY). Set this
comes empty.
This bit is cleared

bit when a tranmit FIFO beby reading the register or set-

ting the RESET bit.

<14> (RW)

Transmit

Interrupt

enable

(T.IE).

When

this

bit

set,

terrupt is generated to the System at vector address 248h
ever the T.RDY bit becomes set.
Clear by writing to 0.
ting the RESET bit has no effect on this bit.

<13> (RO)

Diagnostic failure (D.FAJL). When this bit is
bit is clear, a failure has been detected by
agnostics.
The bit is set if the RESET
ter internal diagnostics have run successfully.

<12> (RO)

Not used.

bit

set and
internal
set

and

in-

whenSet-

the RESET
module dicleared

af-

This bit is not used on the serial Option card and should be ig-

nored by System Software.

<11:8> (RO)

Transmit
ber that

line number (T.LINE). These bits hold the line numcaused the T.RDY bit to set.
The bits are only valid
while T.RDY is set. Clear by setting the RESET bit.

<7> (RO)

Receiver done (R.DON). This bit is set when receive FIFO data is available.
This bit is set by setting the RESET bit since diagnostic information is left in the receive FIFO. This bit is only cleared
when the FIFO is empty.

<6> (RW)

Receiver Interrupt enable (R.IE). Setting this bit enables a receive interrupt to the System
at vector address 244h.
An Interrupt oc-

curs under the following conditions:
• R.IE is set and a character is placed into an empty FIFO.
o R.IE is changed from a 0 to a 1 while the FIFO is not empty.

DHT32 Asynchronous Serial Line Option

/•""^V

/0\

Both of the above conditions are subject to the delay specified in the hoJd-off
timer in register SLU_RT1M. The enable is cleared by writing to 0. Setting
the RESET bit does not affect this bit.
Data Bit

Definition

<5> (RW)

Reset (RESET). Setting this bit causes the moduleto reset itself and run the internal diagnostics.
The bit stays set while the diagnostics are running.
This bit should not be vvritten to a 1 when it is already set. Clear by completion of diagnostics. (See Section 5.3 for the status of all bits after a successful reset.)

<4> (RW)

Diagnostic skip (D.SKP). When this bit is set at the same time as the RE
SET bit,
the reset and diagnostic time is shortened.
This allows fast reseting of the module.

<3:0> (RW)

Line selecl number (L.SEL). This field is used to select which line the SLU
LPR, SLU.DATA, SLU.SIZE, SLU.STAT, and SLU_CNTL registers represent.
Additionally,
when these bits are all zero,
the SLU_
RTIM value may be set.
Only lines zero through seven are
valid on the serial Option card.
Any data vvritten to registers outside that ränge cause unpredictable results.

NOTES: To enable receive Interrupts from the serial Option card, bit 0 of the video
select register (VDCSEL) should be set to 1.

Since the State of the transmit ready bit is cleared on any read of the register, the
Software must itse only word or byte write instructions and not read-modify-xorite
instructions when accessing the register.

4.5 Receive Buffer Register
Figure 4 shows the bits in the receive buffer register (SLU_RBUF).
Figure 4:
Address
15

Receive Buffer Register
:

3800.0002
13

DHT32 Asynchronous Serial Line Option

Data Bit

Definition

<15> (RO)

Data valid (D.
ia not empty.

VAL). This bit is
The bit is set

formation is left in the FIFO.
<14> (RO)

set
by

whenever the receive FIFO
RESET since diagnostic in-

/*■%

)

Over-run error (O.ERR). This bit is set if a character is received on the indicated line (R.LINE) and the FIFO for that line if füll or an er
ror occured while receiving a character.
If this bit is set along
with F.ERR and P.ERR then the R.DATA field contains diagnos
tic information.

<13> (RO)

Framing error (F.ERR). This bit is set
if there was a framing
error (no stop) on
receiving the character.
If this bit is set
along with O.ERR and P.ERR then the R.DATA field contains diag
nostic information.
A break detected on the indicated line appears as a framing error with a null (all zero) data field.

< 12 > (RO)

Parity error (P.ERR). This bit is set if parity is enabled for the line and the par
ity of the character received is incorrect.
If this bit is set along
with O.ERR and
tic information.

<11:8> (RO)

F.ERR

then

the

R.DATA

field

contains

diagnos

Receive line (R.LINE). These bits form the binary value of the line number for which the data in the word is valid.
(Even though there
is room for
16 Hnes,
only lines zero through
seven are con-

sidered valid.)
<7:0> (RO)

Received data (R.DATA). These bits contain the data received for the indi
cated line.
If the error bits (O.ERR, P.ERR and F.ERR) are all
clear, then the data is valid. If any one of the bits are set, then the data is in
valid due to the condition specified by that bit
(with
the exception of F.ERR; see that bit's documentation).
If all the er
ror bits are set,
then the word contains diagnostic information
in the R.DATA field.
(See Section 5 for a description of the di
agnostic codes.)

DHT32 Asynchronous Serial Line Option

■^*s%v

4.6 Receive Timer Register
Figure 5 shows the bits in the receive timer register (SLU_RTIM).
/0\

Figure 5:

Address

Receive Timer Register

3800.0002

R. TIME

Data Bit

Definition

<7:0> (WO)

Receiver

time

delay

(R.TIME).

When

the

L.SEL

bits

SLU.CSR

are all 0, a byte written to thls address sets the value of an in

terrupt holdoff timer for receive character Interrupts.
The following table shows the various programmed values and the response of the Option card.

The value is set to 1 by setting the RESET bit.
Value

Interrupt Requested

The receive FIFO becomes three quarters
could take an infinite amount of time.

(48

characters

füll).

This

Immediate interrupt. The interrupt is requested as soon as the FIFO is not empty.
2to

255

An interrupt is requested after the first character is received and the number of milliseconds equal to the value written have passed.

DHT32 Asynchronous Serial Line Option

4.7 Line Parameter Register
The line parameter register (SLUJJPR) is used to program the characteristics
for each of the eight lines of the DHT32 option. The line parameter register

for the appropriate line can be selected by setting the line value in the L.SEL
field of the control and Status register. Figure 6 shows the bits in the line
parameter register.
Figure 6:
Address
15

/Ü^

Line Parameter Register
:

3800.0004
13

< 15:12> (RW) Transmit

speed

(T.SPEED).

These

bits

are

used

set

the

trans-

mit speed of the selected line. See Table 8 for the baud rates that correspond to the values for the field. The field is set to 1101 (9600 baud) by set
ting the RESET bit.

<11:8> (RW)

Receive speed (R.SPEED). These bits are used toset the receive speed of the selected line.
See Table 8 for the baud rates that correspond to the values for the field.
The field is set to 1101 (9600 baud) by set

>**%.
)

ting the RESET bit.

<7> (RW)

Stop code (S.CODE). This bit defines the length of the transmitted stop bit.
If S.CODE is set to 0, then one stop bit is always sent. If S.CODE is set to 1, the two stop bits are sent for 6, 7, and 8bit characters and one and one-half stop bits for 5-bit characters. Setting the RESET bit sets S.CODE to 0.

<6> (RW)

Even
acter

<5> (RW)

Parity

enable

mission

parity
parity

select (E.PAR). This bit
(if enabled by P.ENA).
ity is expected.
If set to 0, then
ting the RESET bit sets E.PAR to 0.

(P.ENA).

character

This

bit

parity.

abled for the line.
If set to 0,
ting the RESET bit clears this bit.

<4:3> (RW)

selects the sense of the charIf set to 1,
then even par
odd parity is expected.
Set

enables

the

set

parity

to
is

detection
then

disabled

for

and

parity
the

line.

transis

en
Set

Character length (C.LEN). These bits define the number of bits
that make up each character.
The bits do not include the start,
stop or parity bits.
The following Information shows the character length for each of the field settings.

/•*=*%.
1

DHT32 Asynchronous Serial Line Option

Value

Bits Per Character

Setting the RESET bit causes this field to be set to 11 (8 bits per character).
Data Bit

<2:1>(RW)

Definition

Diagnostic

control

(DIAG).

These

bits

control

the

state

the

in-

ternal diagnostics on the option. If both bits are set to 0, then the background diagnostics only reports the Status when an error is detected.
If the bits are set to 01,
then the background pro
gram runs and reports the Status whether or not an error is de-

tected.
Once these bits are set to 01,
no other bits should
be changed in this register until that code is cleared to 0.
See Section 5 for more Information.

<0> (RW)

Disable XON and XOFF reporting (D.XRPT). This bit is used to con
trol whether or not XON and XOFF characters are saved in the re
ceive F1FO. If this bit is 0,
then XON and XOFF characters
are saved.
If this bit is 1 and the transmit auto flow con
trol (T.AUTO) bit in the line control register (SLU.CNTL) is set,
then XON and XOFF characters are not saved in the FIFO. Set
ting the RESET bit clears this bit.

Table 8 defines the binary codes used to select the transmit and receive data
rates for the Controller module.

Table 8:

Binary Codes Used to Select Baud Rates

Value

Baud Rate

0000

0001

0010

110

0011

134.5

0100

150

0101

300

0110

600

DHT32 Asynchronous Serial Line Option

Table 8 (Cont.):

Binary Codes Used to Select Baud Rates

Value

Baud Rate

Olli

1200

1000

1800

1001

2000

1010

2400

1011

4800

1100

7200

1101

9600

1110

19200

1111

38400

4.8 Transmit FIFO Data Register
The Transmit FIFO data register (SLU_DATA) sends characters out the
desired line. The Transmit FIFO data register for the appropriate line can
be selected by setting the line value in the L.SEL field of the control and
Status register. Figure 7 shows the bits in the transmit FIFO data register.
Figure 7:
Address

Transmit FIFO Data Register
:

3800.0006

Data Bit

Definition

<15:0> (WO) Transmit data (T.DATA). The transmit data field programs the data to be sent
out

the

selected

line.

byte

write

performed

the

reg

ister, only the data in the low byte is placed in the transmit FIFO.
If a word wrlte is performed to the register,
then two char
acters are placed in the FIFO. First the low byte is placed in the FIFO,
then the high byte.
Setting the RESET bit clears this regis
ter.

DHT32 Asynchronous Serial Line Option

4.9 Transmit FIFO Size Register
/!

The transmit FIFO size register (SLU_SIZE) is used to determine the amount
of available space in the transmit FIFO for the selected line. The transmit

FIFO size register for the appropriate line can be selected by setting the line

value in the L.SEL field of the control and Status register. Figure 8 shows
the bits in the transmit FIFO size register.

Figure 8:

Address

Transmit FIFO Size Register

3800.0006

F. SIZE

Data Bit

Definition

<7:0> (RO)

FIFO space available (F.SIZE). This field is used to indicate the number of en-

tries
able

left in the transmit FIFO for the selected line.
size ranges from 0 to 64 characters.
Setting
bit sets this field to 40h (64 entries are available).

The avail
the RESET

DHT32 Asynchronous Serial Line Option

4.10 Line Status Register
The line Status register (SLU_STAT) is used to read the Status of the modern
control Signals on the module. While modern control is not used, the Status
bits are set to indicate to DHU compatible Software that no modern control
exists. This register must be read (as a word) along with the FIFO size
register. It is documented here at its byte position.
The line Status register for the appropriate line can be selected by setting

the line value in the L.SEL field of the control and Status register. Figure 9
shows the bits in the line Status register.
Figure 9:

Address

Line Status Register

3800.0007

DSR

DCD

CTS

M .STA

Data Bit

Definition

<7> (RO)

Data set ready (DSR) bit. Not implemented. Always read as 0.

<6> (RO)

Not implemented. Always read as 0.

<5> (R0)

Ring indicator (RI) bit. Not implemented. Always read as 0.

<4> (RO)

Data carrier detect (DCD) bit. Not implemented. Always read as 0.

<3> (RO)

Clear to send (CTS) bit. Not implemented. Always read as 0.

<2> (R0)

Not implemented. Always read as 0.

<1> (R0)

Modem Status (M.STAT) bit.
This bit is used to indicate if mo
dern support is available for the selected line.
No modern support is available at all on the Option so this bit will always read as 1.

<0> (R0)

Not implemented. Always read as 1.

DHT32 Asynchronous Serial Line Option

4.11
.gp^

[

Line Control Register

The line control register (SLU_CNTL) is used to control miscellaneous line
interface functions. The line control register for the appropriate line can be
selected by setting the line value in the L.SEL field of the control and Status
register. Figure 10 shows the bits in the line control register.

Figure 10:
Address
lb

Line Control Register
3800.0008
13

Data Bit

Definition

<15> (RO)

Not implemented. Ahvays read as 0.

<14> (RO)

Not implemented. Always read as 0.

<13> (RO)

Not implemented. Always read as 0.

<12> (RW)

Request to send (RTS) bit.
ing this bit has no effect.

<n> (RO)

Not implemented. Always read as 0.

<10> (RO)

Not implemented. Always read as 0.

<9> (RW)

Data terminal ready (DTR) bit.
ting or Clearing this bit has no effect.

<8> (RW)

Link

type

(L.TYPE).

This

Not used on

bit

used

module.

Setting or Clear

Not

used

module.

inform

the

Controller

Set-

mod

ule of a modern attached to the selected line.
Since modern con
trol is not supported on the DHT32 option,
this bit should al
ways be left cleared.
Setting the bit should have no effect on the Con
troller function.
<7:6> (RW)

Maintainance mode (MA1NT). These bits are used

to control the main-

tainance features incorporated into the module.
A 2-bit value
is used to place the module in one of four operating states.
The values and the corresponding states are as follows.

DHT32 Asynchronous Serial Line Option

Value

Operating State

Normal operating State.

Automatic echo

mode.

The data

received on the selected

line is

)

sent back out the corresponding transmit line (even if T.ENA is cleared).

The normal
internal receive/transmit path is used and the characters are saved in the receive FIFO. The receive line musl be enabled and no data placed into the FiFO by the user is transmitted.
The baud rate selected for the receiver is used for both trans
mit and receive.
10

Local ioopback. The data seilt out the transmit Channel is looped back to the re
ceive Channel even if the receiver enable is clear.
The transmitter en-

able muat be set (T.ENA),
any data
received at this time is ignored, and the Output line is held in the mark condition.
The baud
rate selected for the transmitter is used for both transmit and re
ceive.
11

Remote Ioopback.
The data received is retransmitted at the receiving baud rate.
The data is not saved in the FIFO and the trans
mit enable is ignored. The receive enable must be set.

Setting the RESET bit causes these bits to be set to 00 (normal operating

mode).
Data Bit
<5> (RW)

/^^!v
Definition
Force transmit XOFF (F.XOFF).

This bit is used to send an XOFF be-

fore any other character in the FIFO. If this bit stays set, an XOFF is sent after every other character received on that line.
When the bit
is cleared (after being set), an XON character is sent unless the re
ceiver auto flow control (R.AUTO) is enabled and the FIFO Is threequarters füll.

<4> (RW)

Tranmitter auto flow control (T.AUTO). This bit is used to con
trol the Controller module's response to valid flow control characters received on a line. When the bit is set, a received XOFF charac
ter causes the transmisson to stop until an XON character is re
ceived. The T.ENA bit is actually cleared and set by this action so host Soft
ware can
nel both

override thia action.
To completely disable a
this bit and the T.ENA bit
must be cleared.
ting the RESET bit causes this bit to ciear.

<3> (RW)

Transmit break (BREAK). This bit is used to assert a break con
dition on the selected Channel.
The condition is held until the

bit is cleared. Setting the RESET bit causes this bit to clear.

Chan
Set

DHT32 Asynchronous Serlal Line Option

/"^^N
T

Data Bit

Definition

<2> (RW)

Receive line enable (R.ENA). This bit is used to enable and di.sable the receiving of data on the selected line.
This bit is set to en
able a line. Setting the RESET bit clears this bit.

< 1 > (RW)

Receiver auto floiv control (R.AUTO).
This bit
is used to con
trol the flovv of characters into the receive FIFO. An XOFF character is sent to any line that has this bit set when the re
ceive FIFO become three-quarters füll.
An XON character is then sent
when the
FIFO
becomes
SET bit clears this bit.

<()> (RW)

less

than

half

füll.

Setting

the

Transmit abort (T.ABT). This bit is used to flush all characters from the trans
mit FIFO for a line.
A few characters may be sent after the bit is set.

When the FIFO is cleared,
the T.RDY bit is set and,
if
abled, an interrupt is requested. Setting the RESET bit clears this bit.

en-

4.12 Transmit Enable Register
The transmit enable register (SLU_TXA) is used to enable data transmission
on the selected line. Extreme care must be taken when setting the enable
bit in this register. While the other bits in the register are not used, setting
certain bits could hang up the Controller module. Only the most significant
bit of this register should ever be changed.
The transmit enable register for the appropriate line can be selected by
setting the line value in the L.SEL field of the control and Status register.
Figure 11 shows the bits in the transmit enable register.
Flgure 11:
AddresB

Transmit Enable Register
3800.000C

DHT32 Asynchronous Serial Line Option

Data Bit

Definition

<15> (RW)

Transmitter enable (T.ENA). This bit is used to enable and disable the transmission of characters on the selected line.
When this
bit is set,
the Controller module transmits all characters placed
in the FIFO. When cleared, the Controller module only transmits
flow control characters that are generated by the Controller mod
ule (if enabled by the user).
To completely stop character tranmission

line,

both

the

T.AUTO

bit

and

should be cleared. Setting the RESET bit sets this bit.

the

T.ENA

<14:8> (RO)

Not implemented. Always read as 0.

<7> (RW)

Do not set.
Setting this bit hangs up the Controller module.
ting the RESET bit clears the bit.

<6> (RO)

Not implemented. Always read as 0.

<5:0> (RO)

Not used. Always set to 0.

)

bit

Set

5 Intemal Diagnostics
The DHT32 option has two levels of internal diaenostics:

self-test and

background test.

5.1 Self-Test
The DHT32 option self-test runs when the System powers-up and each time

the RESET bit is set without the D.SKP bit being set. The diagnostic leaves
8 bytes of data in the receive FIFO. When the reset bit is cleared by the
option and the T.RDY bit is set, the D.FAIL bit indicates whether any of the
data bytes in the FIFO contain error information. After setting the RESET
bit, the user waits for the bit to clear before doing anything eise with the
option.

The self-test can take up to two seconds to run.
manipulate the option in any way during this time.

DHT32 Asynchronous Serial Line Option

The user should not

5.1.1 Self-Test Codes
The 8 data bytes that we referred to in Section 5.1 are placed in the FIFO.

The line number field (R.LINE) is used to determine the sequence of the
byte. Sequence numbers 0 through 7 are returned in the FIFO along with
the following possible error codes in the data field (R.DATA). The self-test
error codes are referenced in Table 9.

Table 9:

Self-Test Error Codes

Octal Code

Hex Code

Definition

201

Self-test null (filier byte)

203

Self-test skipped

211

Low octart error

213

High octart error

225

RAM error

When the test is complete, 6 data bytes and 2 bytes of ROM version code are
left in the FIFO. Null codes are used whenever there is no error to report.
An error-free test returns six null codes and two version bytes. If the test is
skipped, six test skipped codes are returned instead of the null codes.

5.2 Background Test
A background test program continuously runs in the DHT32 Option. If an
error is detected, the octal code 307 is placed in the FIFO along with the
setting of all the error bits (O.ERR, F.ERR, and P.ERR) and the Clearing of the
line number field (R.LINE). If all the error bits are set the Software Signals
that a problem exists with the module.

The user can cause the background test to explicitly place a code into the
receive FIFO by setting the diagnostic bit (DIAG). When the test is complete,
the DIAG bit is cleared and either the octal code 307 is placed in the FIFO
to indicate an error or the octal code 305 is placed in the FIFO to indicate
normal Operation.

(
DHT32 Asynchronous Serial Line Option

5.3 Reset State
This section summarizes the reset Information that is available individually
for each of the sections above. After System power-up or setting the RESET

bit (and waiting for it to clear), a successful (no errors detected) reset leaves
the Controller module in the following State.

•

Eight bytes of diagnostic data are in the FIFO.

•

The diagnostic failure bit is clear.

•

The transmit baud rate for each line is set to 9600 and is enabled.

•

The receive baud rate for each line is set to 9600 and is disabled.

•

Each line is set for 8 data bits, one stop bit, and odd parity but with
parity disabled.

•

Transmit and receive auto flow control are disabled for all lines.

•

Normal operational mode is set in the maintainance bits.

•

No space (break) condition is asserted on any line.

/!!W^

5.4 ROM Option
The ROM Option for the DHT32 Controller module resides in address ränge
2014.0000 to 2015.FFFC (hexadecimal).

1
26

DHT32 Asynchronous Serial Line Option