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Document:	DEC 7000 AXP, VAX 7000 Technical Bulletin Number 3
Order Number:	EK-70TBA-T3
Revision:	A01
Pages:	27
Original Filename:

OCR Text

DEC 7000 AXP
VAX 7000
Technical Bulletin Number 3
Order Number EK–70TBA–T3. A01

This document accompanies the release of the KA7AB CPU module used in
VAX 7000/10000 systems and the KN7AB CPU module used in DEC
7000/10000 systems.

digital equipment corporation
maynard, massachusetts

First Printing, June 1994
The information in this document is subject to change without notice and should
not be construed as a commitment by Digital Equipment Corporation.
Digital Equipment Corporation assumes no responsibility for any errors that may
appear in this document.
The software, if any, described in this document is furnished under a license and
may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software or equipment that is
not supplied by Digital Equipment Corporation or its affiliated companies.
Copyright © 1994 by Digital Equipment Corporation.
All Rights Reserved.
Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation:
Alpha AXP
AXP
DEC
DECchip
DEC LANcontroller
DECnet

DECUS
DWMVA
OpenVMS
ULTRIX
UNIBUS
VAX

VAXBI
VAXELN
VMScluster
XMI
The AXP logo

OSF/1 is a registered trademark of the Open Software Foundation, Inc.
FCC NOTICE: The equipment described in this manual generates, uses, and may
emit radio frequency energy. The equipment has been type tested and found to
comply with the limits for a Class A computing device pursuant to Subpart J of
Part 15 of FCC Rules, which are designed to provide reasonable protection against
such radio frequency interference when operated in a commercial environment.
Operation of this equipment in a residential area may cause interference, in which
case the user at his own expense may be required to take measures to correct the
interference.

Contents
Preface ....................................................................................................... v
Section 1
1.1
1.2

Changes .................................................................................. 1-2
System Upgrades ................................................................... 1-4

Section 2
2.1
2.1.1
2.2

User Information

Console Commands ................................................................ 2-2
Set System_Variant ......................................................... 2-2
Registers ................................................................................. 2-3
KA7AB BIU Control Register (BIU_CTL) ..................... 2-3
KN7AB Cache Status Register (C_STAT) ..................... 2-5
KN7AB Abox Control Register (ABOX_CTL) ................ 2-6
KN7AB BIU Control Register (BIU_CTL) ..................... 2-8

Section 3
3.1
3.2
3.3

Installation

Service Information

KFMSB Adapter ..................................................................... 3-2
MS7AA-FA Memory Module ................................................. 3-4
Power Requirements for Options .......................................... 3-6

Examples
2-1

Set System_Variant Command ............................................. 2-2

Figures
3-1

KFMSB Module ...................................................................... 3-2

iii

3-2

MS7AA-FA 2-Gbyte Memory Showing J Connectors for
SIMMs .................................................................................... 3-4

Tables
2-1
2-2
2-3
2-4
3-1
3-2

KA7AB BIU_CTL Register Bit Definitions, Revised ........... 2-4
KN7AB C_STAT IPR Bit Definitions, Revised ..................... 2-5
KN7AB ABOX_CTL IPR Bit Definitions, Revised ............... 2-7
KN7AB BIU_CTL IPR Bit Definitions, Revised .................. 2-9
KFMSB Kit Contents ............................................................. 3-3
Power Requirements for Options .......................................... 3-6

Preface
Intended Audience
This document is written for system managers and service engineers.

Document Purpose
This technical bulletin provides information to update the DEC
7000/10000 and VAX 7000/10000 documentation set. Since the original
documentation set was published, we have issued two other Technical Bulletins, which are a part of the documentation set:
•

DEC 7000/10000 AXP Technical Bulletin Number 1—EK–70TBA–T1

•

DEC 7000/10000 AXP Technical Bulletin Number 2—EK–70TBA–T2

This document accompanies the release of two new modules for this platform. They are:
•

KA7AB CPU module for VAX 7000/10000 systems

•

KN7AB CPU module for DEC 7000/10000 systems

The following options are also described in this document:
•

KFMSB adapter module—Supports DSSI buses on DEC 7000/10000
systems

•

MS7AA-FA memory module—A 2-gigabyte memory module; supported
on both VAX and DEC 7000/10000 systems.

Chapter 3 also provides the power requirements for newly supported options, used to determine when a second power regulator is needed.

If you have an Internet account, you may mail us your comments on VAX
7000/DEC 7000 hardware documentation. Please mail your comments,
suggestions, and corrections to msbdoc@lando.enet.dec.com. We will
reply to all comments. Digital values your input.

Section 1
Installation
The KA7AB and KN7AB processor modules can be used to upgrade VAX
7000/10000 and DEC 7000/10000 systems. The KA7AB module is used to
upgrade VAX systems with KA7AA modules, and the KN7AB module is
used to upgrade DEC systems with KN7AA modules.
Sections include:
•

Changes

•

System Upgrades

Installation 1-1

1.1 Changes
Alpha AXP systems are supported by OpenVMS AXP Version 6.1
and DEC OSF/1 Version 3.0. VAX systems are supported by OpenVMS VAX Version 6.1.

DEC Systems
The DECchip 21064A CPU chip on the KN7AB module provides improved
performance over the DECchip 21064 chip. The chip speed is 275 MHz.
Other features of the CPU chip, which differ from DECchip 21064, are the
following:
•

Instruction cache increased from 8 Kbytes to 16 Kbytes

•

Data cache increased from 8 Kbytes to 16 Kbytes

•

Parity protected internal caches

•

Improved branch prediction logic

•

Improved floating-point divide pipeline

•

Some bit changes in internal processor registers

With the release of the KFMSB module, DEC systems now support DSSI
subsystems.
VAX Systems
The NV5 CPU chip on the KA7AB module provides improved performance
over the NVAX and NVAX+ chips. The CPU chip is implemented in
CMOS-5 technology. The NV5 chip speed is 137.5 MHz compared with 91
MHz for the NVAX+ chip.
One internal processor register has changed: the BIU Control Register.
Both DEC and VAX systems now support the 2-Gbyte memory module.

1-2 Installation

Console Revision Requirements
KA7AB —V1.0 console release is required initially, until Version 3.5 is
available, which provides support for both KA7AA and KA7AB modules.
KN7AB —V3.3 console release or later
KFMSB —V3.2 or later for DEC 7000 systems with KN7AA modules
V3.3 or later for DEC 7000 systems with KN7AB modules
MS7AA-FA —V3.2 or later for DEC 7000 systems with KN7AA modules
V3.3 or later for DEC 7000 systems with KN7AB modules
V3.2 or later for VAX 7000 systems with KA7AA modules
V1.0 or later for VAX 7000 systems with KA7AB modules
Correction to LFU Booting on DEC 7000
The Loadable Firmware Update (LFU) Utility is on the Alpha AXP Systems Firmware Update CD-ROM. To boot LFU from the InfoServer, enter
the following command at the console prompt, supplying the version number for nn:
P00>>> boot exa0 -file AXP7000_Vnn
LFU starts, displays a summary of its commands, and issues its prompt
(Function?).

Installation 1-3

1.2 System Upgrades
Upgrades can be of various types. Modules must be returned when
the upgrade replaces the current CPU modules.

Upgrades can be of the following types:
•

Upgrading from KA7AA modules to KA7AB modules

•

Adding a KA7AB to an existing VAX system with KA7AB modules

•

Upgrading from KN7AA modules to KN7AB modules

•

Adding a KN7AB to an existing DEC system with KN7AB modules

•

Upgrading from a VAX 7000 or 10000 system to a DEC 7000 or 10000
system.

Complete installation instructions are packaged with each CPU module.
NOTE: The numbering scheme for the OpenVMS AXP operating system
has changed to match the OpenVMS VAX numbering scheme. The
revision level required to support these CPU modules is Version 6.1
for both VAX and DEC systems.

1-4 Installation

Section 2
User Information
Changes to console commands:
•

Set System_Variant

Changes to registers:
•

KA7AB BIU Control Register

•

KN7AB Cache Status Register

•

KN7AB Abox Control Register

•

KN7AB BIU Control Register

User Information 2-1

2.1 Console Commands
2.1.1 Set System_Variant
The default value for the system_variant environment variable is
0. After issuing a build EEPROM command on a DEC or VAX 10000
system, you must set the system_variant environment variable to a
value of 1.

Example 2-1

Set System_Variant Command

P00>>> set system_variant 1

# Set system variant
# to 1 for DEC 10000.

P00>>>
The set system_variant command syntax is:
set[t] system_variant<value>
where value is one of the following:
•

0 for DEC 7000 and VAX 7000 systems (default)

•

1 for DEC 10000 and VAX 10000 systems

2-2 User Information

2.2 Registers
The following register information updates that given in the
KA7AA and KN7AA CPU Technical Manuals. The registers described are on-chip registers.

KA7AB BIU Control Register (BIU_CTL)
Address
Access

00A0
R/W

The BIU_CTL register controls certain operations
and parameters related to the P-cache, B-cache,
and I/O mapping. This register reads the complement of its contents.

31 30

28 27

24 23

20 19 18 17 16 15 14 13 12 11 10 9 8

XXXXXXX 00

X X

3 2

BC_SIZE
WS_IO
BACKMAP_EN: Backmapping Enable
PROBE_CIM: B-Cache Probe Cycles = 3
WRITE_CIM: B-Cache Write Cycles = 3
IO_MAP
PV: PV System Mode
QW_IO_RD: Quadword I/O Read
PCACHE_MODE: P-Cache Mode
BC_SPD: B-Cache Speed
BC_FHIT: B-Cache Force Hit
OE: Output Enable
ECC: Error Correction and Control
BC_ENB: B-Cache Enable
NOTE: X bits read values from DIAG_CTL.
This register reads inverted.

BXB-0213A-93

User Information 2-3

Table 2-1 KA7AB BIU_CTL Register Bit Definitions, Revised
Name

Bit(s)

Type

Function

BACKMAP_EN

<18>

R/W, 0

Backmap Enable. Controls
whether internal IRead aborts,
which have been backmapped,
generate invalidates to the Pcache. The console program sets
this bit to 1.

PROBE_CIM

<17>

R/W, 0

Probe Cache Cycle Injection
Mode. Controls the number of
CPU cycles for all B-cache probes
when set. The console program
sets this bit to 1, which allows all
B-cache probe cycles to increase
from 2 to 3 CPU cycles.

WRITE_CIM

<16>

R/W, 0

Write Cache Cycle Injection
Mode. Controls the number of
CPU cycles for all B-cache writes
when set. The console program
sets this bit to 1, which increases
the assertion duration on the
dataWE_h<3:0> and tagCtWE_h
pins from 2 to 3 CPU cycles.

2-4 User Information

KN7AB Cache Status Register (C_STAT)
Address Abox 12
Access R

This register was named D-Cache Status Register in
the DECchip 21064 (EV4 chip).

6
3

1 1
5 4

RAZ

0 0 0 0 0
6 5 4 3 2

0
0

0's
IC_ERR: I-Cache Parity Error
DC_ERR: D-Cache Parity Error
DC_HIT: D-Cache Hit
CHIP_ID: EV45 = 011
BXB-0607A-93

Table 2-2 KN7AB C_STAT IPR Bit Definitions, Revised
Name

Bit(s)

Type

Function

IC_ERR

<5>

Instruction Cache Parity Error. Set by
I-cache parity error. Cleared by read of this
register.

DC_ERR

<4>

Data Cache Parity Error. Set by D-cache
parity error. Cleared by read of this register.

CHIP_ID

<2:0>

Chip Identification. This field has a
value of 011 (bin).

User Information 2-5

KN7AB Abox Control Register (ABOX_CTL)
Index
Access

Abox 14
W
The ABOX_CTL IPR controls the Abox functions.
PALcode writes to this register at initialization and
keeps an image of the register which appears in error
log entries and is readable by the user. The console
initializes the D-cache to 16 Kbytes.

6
3

1 1 1 1 1 1 0
5 4 3 2 1 0 9

MBZ

0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0

MBZ

DOUBLE_INVAL: Invalidate Both D-Cache Blocks
NOCHK_PAR: Disable Checking P-Cache Parity
F_TAG_ERR: Fill P-Cache Tag with Bad Parity
DC_16K: Select 16 KB D-Cache
DC_FHIT: D-Cache Force Hit
DC_EN: D-Cache Enable
EMD_EN: Endian Mode Enable
SPE_2: Superpage Enable 2
SPE_1: Superpage Enable 1
IC_SBUF_EN: I-Cache Stream Buffer Enable
CRD_EN: Correctable Read Interrupt Enable
MCHK_EN: Machine Check Enable
WB_DIS: Write Buffer Unload Disable
BXB-0604A-93

2-6 User Information

Table 2-3 KN7AB ABOX_CTL IPR Bit Definitions, Revised
Name

Bit(s)

Type

Function

DOUBLE_INVAL

<15>

W, 0

Invalidate Both D-Cache
Blocks. When set, dInvReq_h<0>
assertions invalidate both D-cache
blocks addressed by iAdr_h<12:5>.
Cleared by reset.

NOCHK_PAR

<14>

W, 0

Disable Checking P-Cache Parity. Set to disable checking of primary cache parity. Cleared by reset.

F_TAG_ERR

<13>

W, 0

Fill P-Cache Tag with Bad Parity. Set to generate bad primary
cache tag parity on fills. Cleared by
reset.

DC_16K

<12>

W,0

Select 16-Kbyte D-Cache. Set to
select 16-Kbyte D-cache. Clear to
select 8-Kbyte D-cache. Cleared by
reset.

User Information 2-7

KN7AB BIU Control Register (BIU_CTL)
Address
Access

Abox 18
W
The BIU_CTL IPR is a write-only register that controls
the operating parameters of the BIU interface and the
B-cache. PALcode writes to this register at initialization and keeps an image of the register which appears
in error log entries and is readable by the user.

6
3

444 4 3 33 3
543 0 9 87 6

MBZ

3 3 3
2 1 0

2 2
8 7

1 1 1
3 2 1

0 0
8 7

0 0 0 0 0
4 3 2 1 0

BC_WE_CTL<15:1>

FAST_LOCK: Fast Lock Mode
B-Cache Write
IMAP_EN: I-Stream Cache Read Enable
Enable Control
BYTE_PARITY: External Byte Parity
BAD_DP: Bad Data Parity
BC_PA_DIS: B-Cache Phys Addr Disable
BAD_TCP: Bad Tag Control Parity
MBZ
BC_SIZE: B-Cache Size
BC_WR_SPD: B-Cache Write Speed
BC_RD_SPD:B-Cache Read Speed
BC_FHIT: B-Cache Force Hit
OE: Output Enable
ECC: Error Checking and Correction
BC_EN: B-Cache Enable
BXB-0606A-93

2-8 User Information

Table 2-4 KN7AB BIU_CTL IPR Bit Definitions, Revised
Name

Bit(s)

Type

Function

FAST_LOCK

<44>

W, 0

Fast Lock Mode. When set,
FAST_LOCK mode operation is selected. This mode can only be used
when BIU_CTL<2> is also set, indicating that OE-mode B-cache RAMS
are used. Cleared by reset.

IMAP_EN

<39>

W, 0

I-Stream Cache Read Enable. Set
to allow dMapWe_h<1:0> to assert
for I-stream backup cache reads.
Cleared by reset.

BYTE_PARITY

<37>

W, 0

External Byte Parity. If set when
BIU_CTL<ECC> is clear, external
byte parity is selected. When
BIU_CTL<ECC> is set, this bit is ignored. Cleared by reset.

User Information 2-9

Section 3
Service Information
Information covered includes:
•

KFMSB Adapter

•

MS7AA-FA Memory Module

•

Power Requirements for Options

Service Information 3-1

3.1 KFMSB Adapter
DEC 7000/10000 systems now support the KFMSB adapter, which
provides the XMI interface to DSSI buses. Each KFMSB supports
two DSSI buses. The KFMSB has a diagnostic LED and reports
status to the system self-test display.

Figure 3-1

KFMSB Module

Yellow
Self-Test LED

BXB-0686-94

3-2 Service Information

With the KFMSB adapter it is now possible to upgrade a VAX 7000/10000
system with a DSSI subsystem to a DEC 7000/10000 system with a DSSI
subsystem.

Table 3-1 KFMSB Kit Contents
Option Number

Description

KFMSB-AA

Includes the KFMSB XMI module that supports
DSSI systems in DEC 7000 and 10000 (AXP) systems and an installation guide (EK-KFMSB-IN).

KFMSB-UA

The upgrade kit includes the KFMSB XMI module,
the installation guide, and the KFMSB cabinet kit
(CK-KFMSB-LB).

LFU now allows you to change the DSSI node number of a KFMSB
adapter, using the modify command.

Service Information 3-3

3.2 MS7AA-FA Memory Module
Restrictions on use of the 2-gigabyte memory module depend on
the operating system.

Figure 3-2

MS7AA-FA 2-Gbyte Memory Showing J Connectors
for SIMMs

J37
J36
J34
J32
J30
J28

J35
J33
J31
J29
J27

J26

J25
J24
J22
J20
J18
J16
J14

J23
J21
J19
J17
J15

J13
J12
J10
J8
J6
J4

J11
J9
J7
J5
J3

BXB-0687-94

3-4 Service Information

The MS7AA-FA memory module is the 2-gigabyte memory module for
VAX 7000/10000 and DEC 7000/10000 systems. It is populated with 36
64-Mbyte single in-line memory modules (SIMMs).
Restrictions on its use depend on the operating system.
The following versions of console firmware are required to support the
MS7AA-FA module:
•

For VAX 7000 systems
Version 3.2 with KA7AA modules
Version 1.0 with KA7AB modules

•

For DEC 7000 systems
Version 3.2 with KN7AA modules
Version 3.3 with KN7AB modules

For more information: Repair instructions can be
found on TIMA. See:
MS7AA-FA Memory Module Service Guide
(EK-MS7AA-SV).

Service Information 3-5

3.3 Power Requirements for Options
Various options have been released since the introduction of the
VAX 7000/10000 and DEC 7000/10000 systems.
Table 3-2 lists the power requirements for each option, needed in calculating the need for a second power regulator. Power requirements are measured in equivalent power units (EPUs). This information updates the information found in Table B-1 of the Advanced Troubleshooting manuals.

Table 3-2 Power Requirements for Options
Option

EPUs

DEFAA Futurebus+ to FDDI adapter

DWLVA VME adapter

KFMSB XMI SCSI controller

KZASA Futurebus+ FWD SCSI controller

KZMSA XMI SCSI controller

MS7AA-FA 2-Gbyte memory module

MS7BB 16-Mbyte battery backup memory module

3-6 Service Information

Index
D
DEFAA
power requirements, 3-6
DSSI adapter for DEC 7000
systems, 3-2
DWLVA
power requirements, 3-6

MS7AA-FA memory module, 3-4
MS7BB
power requirements, 3-6

P
Power requirements for options,
3-6

EPUs, 3-6

SIMM locations on MS7AA-FA
module, 3-4

K
KA7AB
BIU_CTL register, 2-3
console revision required, 1-3
KFMSB
console revision required, 1-3
kit contents, 3-3
module, 3-2
power requirements, 3-6
KN7AB
console revision required, 1-3
KN7AB registers
ABOX_CTL, 2-6
BIU_CTL, 2-8
C_STAT, 2-5
KZASA
power requirements, 3-6
KZMSA
power requirements, 3-6

M
MS7AA-FA
console revision required, 1-3
power requirements, 3-6

Index-1