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DEC-11-H40SA-A-D

2000

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Document:	PDP-11/40 System manual
Order Number:	DEC-11-H40SA-A-D
Revision:	0
Pages:	358
Original Filename:	DEC-11-H40SA-A-D_PDP-11_40_System_manual.pdf

OCR Text

PDP-11/40 system manual

DEC-11-H40SA-A-D

P‘DP-HMO system mavnual

digital equipment corporation - maynard. massachusetts

TABLE

COMTEMTS

Page

INTRODUCTIONM

Scope

System Components
Functional

Description

Unibus
KD11=2A

Processor

FY11=D

Programmer®s

MF11=-1L

Core

Optional

DL11
Power

!Memorv

Memory

DECwriter

Svsterms

Asynchronous

Line

Interface

Systcm

Documentation

Engineering

1=18

Svstenm

Arplicahle

CHAPTER

Console

Drawings

INSTALLATION

Scone

Site

Preparation

Physical

Dimensions

Fire

Safety

and

Dnvironnental

Precauticns

Requirements

iii

TABLE

COMNTENTS

{Cont)

Paace

Humidity

N
(N

Darmpineg

Static

~ustical

Special

Flectrical

Installation

Younting

Elcctricity

Conditions

Reouirenents
Procedures

Unpacking

Inspection

Tritial

Power

Initial

Operaticn

[@»]

(]

Installation

Pemote

Customa

Varification
Turn=0n

and

Accerptance

Pre~syrarminT

[EW]

8
[

Interconnection

3]
~J

Connections

Perirheral

Power

)

Renote

Connections

Unibus

Connections

)

Intercakinet

Power

Installation

Cabinret

Temperature

Conditionina

1\W]

by
>

Air

and

TABLE OF

CONTENTS (Cont)

Page

CHAPTER

SYSTEM

OPERATION

Scope

KY11=D Programmergs Conscle
DECwriter

TeletYpe
Basic

Operaticn

Power

Basic

Conscle

Mapual

Control

Automatic

Running Profirams
Basic

CHAPTER

Programming

PROCESSOR

INSTRUCTIONS

AMD

OPTIONS

Scope

Instruction
Address

Basic

Modes

Instruction

Extended
Processor

KE11=E

(ETIS)

Set

Instructicn

Set

Ontions

Extended

Instruction

Oontion

\Y4

Set

TABLE

COMITENTS

(Cont)

Page

4,3.2

KE11=F
(FIS)

Floatirg

Instructicon

Option

4=30

4.,3.3

KJ11=-A Stack Limit

4.,3.4

KT11=-D Memory

4.3.5

EW11=L

4.3.6

KM11=A Maintenance

4.3.7

Small

4,4

Set

Lire

Management

Frecuency

Peripheral

4=34

Ontion

Cloclk

Yodule

Option

4=37

Ontion

Opticn

Controller

=i
,

4=473

Slot

A=44

Mermory Ontions

A=An

4.4.1

MM11=1,

Core

Memorv

A=lr

4.4.2

MF11=L

Core

Menorvy

L=49

4.4.3

ME11=L

Core

Memory

4=50

4.4.4

MMT11=-S

Core

Homory

4etD

UNIRUS

2MD

CHAPTER

5.1

Sconpe

5.2

linibus

5.3

SYSTEM

OPTIONS

‘

Unibus

5=1

S5e2
Ontions

5=8

5.3.1

PC11

Nivh=Speed

Paner=Tane Rrader/Punch

5=0

5.3.2

LP11

High=Srneead

Linc

5=1n

5.3.3

CP11

Card

5e11

TH11/7TU10

DECmactape

(9%

5.3.5

DECtave

Reader

TC11/TUSG

Printer

System

Svstenm

5=13

5«15

TABLE

RC11/RS64

DECdisk

RF11/RS11

Disk

RK11=C

DECpack

CONTENTS

(Cont)

Menorv

System
Disk

Cartridae

Svstem

VT01

Storage

VR0O1

Oscilloscope

VR14

Point

VT05

Alphanumeric

5.3.13

RT01

DEClink

5.3.14

Communications

5,3.15

AFC11

5,3.16

AD01=D Anélog-to~Diqital Conversion Subsvystem

5.3.17

AR11=D

CHAPTER

Displav

Plot

Display

Displav

5=24

Display

Terminal

Options

Low=Level

Analég

Input

Digital-to=Analog

EQUIPMENT

5=25

MOUNTING

AND

Conversion

POWEPR

Scope4
System

Mounting

Processor

Memory

Module

MModule

Programmer
®*s

Box
Allocations

Allocations
Conrscle

Mounting

Cabinet and Svstem Mountinq N
System

Cabinet

System Configuration

vii

Subsvstem

Subsvsten

TABLE

CONTEHNTS

(Cont)

Paoe

Power

Control

Svyvstem

860

Power

860

Physical

860

Functional

860

Circuit

841

Power

PCP11/40
H742

Bulk

+15V

and

Control

Unit

Description
Description

Desc

rintion

Control‘Unit

Rasic

Power

Supnly

Power
of

the

H742

Sunnlvy

Clock

Outvrut of

the

11742

Sunnlv

and

Circuits

48V

Sunnlvy

744

45V

Reculator

11744

Reulater

Circuit

+5vV Overcurrent

Sensins

Civcuit

+57 Overvecltage

Crowbar

Circuit of

the

the 11744

(1745 =15V Regulator'
=15V

Requlator

Circuit

the

1745

Circuit

the

H7/

=15V

Crowhar

Circuit

the

H745

Overvoltage

Power

Distribution

Maintenance

Power

Svsten

Senrnsirg

=15V Overcurrent

TABLE

CIIADPTER

GENERAL

OF COMTENTS

(Cont)

MAINTENANCE

Scope

Overall Maintenance

Technicues

Knowledge

Hardware

Detection

and

Means

Digital

Proper

Isolation

Repairing

Field

the

Equirment

Preventive

Maintenance

860
AC

ASR33

Checks

Regulator

Power
Power

Condition

Required

and

Adjustments

Checks

Control
Connector

Receptacles

Teletvpe

7.4.3.1

Preventive

70403.2

Lubrication
LA30

Error

Condition

Checks

Electrical
Voltage

Error

Service

Maintenance

Physical

Operation

Maintenance

Checks

DECwriter

Preventive

Maintenance

Schedule

Cleaning Procedures
PC05
7.4.5.1

High=Speed Paper=Tape Reader/Punch

Mechanical

Checks

(option)

TABLE

Electrical
Use

COMTEHTS

(Cont)

Checks

Module

PDP=-11/40

Extenders

Power

System

Maintenance

Circuit Tracing
Voltage

REgulator

Tests

Voltage

Reqgulator

Test

(Off-Line

(After

Repnair)

REpair)

ILLUSTRATIONS

PDP=-11/40

D.C.

Cakble

Connector

2-162

Harness

2=45n

PDP=11/40

Programmer?®s

DECwriter

Controls

Teletvpe

Controls

Flowchart
Doukle

Console

and

Procedure

Single

for

Operand

Running
Address

Proagrams
Modes

Instruction Formats

PDP=11/40

Svstem Cabinet

PDP=11/40

Mounting Rox

(R211=-FC)

Module

Allocation = XD11«A Processor,

Basic

(*)

Module

Allocation —

Rasic

(*)

and

Options

MF11=1 Memory,

Optional

"TM11=Ls

ILLUSTRATIONS

(Cont)

Page

Typical

Power

Multiple

Control

PDP=11/40

Cabinet System

Cinficuration

Interconnection

Power

System Block

Diagram

PDP=11/40 Powei Supprly
Simplified Diagfam‘of Precision Voltage

Regulator E1
DC Power
Voltage

Distribution
Requlator

Tvpical Voltage

Test Bench

Regulator

x1i

Source

and

Loads

Outnut Waveforms

CHAPTER

INTRODUCTION

1.1

SCOPE

This

manual,

the

introduction

PDP11/40

the

System Manual,

PDP11/40

svstem

and

provides

includes

general

sections

installation, operation, the instruction set, options, mounting
and

power,

and

references

maintenance.
other

This

manuals

overview

the

PDP11/40

supplerented
series

for

with

detailed

explanations.

The

PDP11/40

necessary

manuals

provide

understand,

the

user

operate,

with

and

the

theorv

maintain

the

operation

PDP11/40

Svstem,

These manuals reference associated engineerina drawinas, bhoth
are

listed

are

separate

number

The

(not

level

1-2.

volumes

and

the

basic

presents

enables

necessary

manual

discussion

familiar with

nhilosophy
and

Table

the

user

corrective

Please

documented

number).

each

digital

information
to

note

Both

volumes

Fach

associated
Drawina

are

assumes

computer
about

the

their

manual

recognize

action.

that

theory.

normal

trouhle

drawinas

Directorv

necessary.

that

The

syster

svmptoms

individual

manual

the

reader

maintenance
oneration
and

nerform

contairs

theorv

of operation, diaqrams, maintenance technimues. Tocic drawines for
the specific

component

covered

are

contaired
in

scrarate

volures.

This chapter describes
and

provides

and

each

the

chapter

drawings

a
its

the basic

functional
major

covers

(paragrarh

description

components

applicable
1.5),

system components

and

the

(paraaraph

documents

overall
1.3).

(paragraph

termirologv

(paraaraph

The

PDP-11/40
remainder

1.4),

(paracranh

1.2)
system
of

engineerina

1.6).

1.2

SYSTEM

The

PDP-11/40

programmer
’s

control,

this

are

System

and

covered

system

are

memory,

and

mounting

listed

peripherals

added

manuals

separate

are

with

individual

included

six

core

sunply,

Manuals

consists

console,

power

basic

Options

COMPONENTS

only

system.

for

hasic

DECwriter

bhex.

1-1.

the

basic

delivered

with

Possible

Tahle

those

comnonents:

associated

variaticn

PDP-11/40
with

options

the

nrocessor,

Svstem

svstem.

specificallyv

ordered

Table

Possible

Major

1-1

PDP-11/40 Variations

Compoeonent

*KD11-A

*KY11-D

Processor

Programmer’s

Possibhle

variations

the

included:

followinag

hasic

Variaticns

processor.

internal

Howsver,

processor

ontions

EE11-%

Exterded

Instructionr

Set

(7I%)

KE11-T

Floatinag

Instruction

Set

(FT1S8)

KT11-2

Stack

TM11-2

Maintenance

KT11-D

Memory

KW11-1L.

Line

T.init

anv
can

(conscle)

Manarmerent

Freauency

TInterrupt

Clock

None

Console

Table

Possible

Major

Core

1-1

PDP-11/40

Component

Memory

(Cont)

Variations

Possihle Variations

MM11-L

*MF11-L

core

merory,

350

internal

MM11-L

space

memory

exists

901

access

plus

for

cycle

time,

time

backnlane,

two

additional

MM11-Ls

ME11-L

MM11-L memory

plus

mounting box,

and power supply

(complete

MM11-S

memory

backplane,

system)

MM11-L memory,

interleaved,

backplane

(may

expansion

of memory

used

plus

for

above

24K)

Table

Possible

Major

Core

1-1

(Cont)

PDP-11/40

Variations

Possihle Variatinns

Compnonent

Memory

(Cont)

MNOTER

Memorv

svsters

PDP=-11/2N

mav

PDP-11/40.,

comnatible
also

These

used

memories

bit

MM11-F

bit

MM11-FP

bit,

1K bv

1€

bit

MM11-J

bit

memories

powered

PDP11/4N

the

narity

MM1T1-H

These

the

ares

MM11-E

with

cannot he mounted within

within

nountinag

the
hox.

bhasic

Table

Possible

Major

1- 1

(Cont)

PDP=11/4N

Variations

Component

DECwriter

Possible

**TLA30

Standard.97-character kevhoard.
Optional

128-character

available.

(LA30-S

DECwriter

a DL11

and

Input

Terminal

Control

*%33

ASR

Each

unit

KSR

120V

ASR

KSR

DL11-A

Teletyne,

DL.11-B

EIA

DL11-C

Teletype,

DL11-D

EIA

DL11-E

Dataset

kevhoard

serial

controlled

LA30-P is a

DECwriter

controlled

Unit

control;

parallel

Teletype

Variations

and

LC11

is
control.)

awvailable

240V models.

disvnlav,

terminal

LA30-S

control

LA30-S

control

displav,

terminal

control

Table

Possible

Major

1-1

(Cont)

PDP-11/40

Variations

Component

Possible Variations

KL11-B

Similar

KL11-A.

X1.11-C

prirmarily

in bhaud

rates

KL11-E

described

manual.

KL11

Differ

KL11-F

LC11

Power

Svstem

*H742
120V

*H744

ILA30-P

Power
or

Suprply

240V,

45V

DECwriter

(mayv

50/60

bhe

jumvnered

25A

supplied

with

svstem;

unit may

basic

included

(two

normallv
additional

handle

102

(two)

options)

=15V

regulator,

1-8

for

Hz)

reculator,

*H745

control

svstem

either

Table

Possible

Major

Component

1-1

PDP-11/40 Variations

‘

*860

Possible Variations

Power

cabinet.

Mounting

Box

indicates

Control

mounted

Two versions

requires

120V

input

860B

requires

240V

input

that

top

available:

860A

*BA11-FC

asterisk

(Cont)

Mounting Box

this

the

normal

configuration

shippéd with the basic machine, unless otherwise specified
by

the

Either
the

customer.

the LA30

basic

DECwriter

PDP-11/40

System

the Teletype Unit may be

input/output device.

used

1.3

FUNCTIONAL DESCRIPTION

The

PDP-11/40

16-bit,

~m§

general-purpose,

microprogrammed computer using 1-

and

system

complement

instruction
core memory.

arithmetic.

length processor,
All

all

single

peripherals

can be

are

all

instructions

and

peripherals

bus,

the

rate

in the basic
are
are

I/0

and

addresses

all

peripherals)
is performed
Because

2,500,000

All

the Unibus

the

bus

concept,

transfers

words-per-second.

space;

system components

and

power

connectors.

functional description

A functional description

of all processor options

presented

All

therefore,

Subsequent paragraphs present a brief
basic PDP-11/40 System components.

;

components

system address

a variable

and device-to-device

instructions.

linked

instructions

contains

system

the Unibus.

are compatible,

accomplished

peripherals

among

core memory,

high-speed

2-address

which directly

communication

(including processor,
on a

The

parallel-logic,

in Chapter

4 of

this manual.

1.3.1

‘Unibus

‘The Unibus is a single high-speed bus that provides communication

between system éfimponentsa The Unibus, with bidirectional data,
address,

and

units

the bus

‘these

transfers.

enough

for

control

eases

with

speed

interfaces.
design

lines,

DATI,

DATIP,

INTR,

PTR

data

control
of the

transfers

bus

an
bus

The

fixed

repertoire

and

design

economy,

yet

The

and

allows

asynchronous

operation.

DATO,

(BR,

The

DATOB

NPR)

nature

data

control

important

these
of

all

factor

operations

provides

repertoire

between

is flexible

fixed

specification

operations

bus

operations

also
is:

operations

Full 16-bit words or 8-bit bytes of informatién can be transferred
on the bus between the master and slave. The DATI, DATIP operations

transfer data into the master; the DATO, DATOB operations transfer
data

out

master

and

the

master.

requests

two purposes:

force

the

interrupt

or
to

processor

service

device

the

bus,

capable

generally

becoming

bus

for one of

to make a direct memory access (DMA) transfer‘of

‘data directly to,
intervention;

use

When

from,

another device without processor

interrupt

(INTR)

branch

routine

Bus

control

obtained

for

the direct memory

under

access

program execution and

specific

address

where

located.

non-processor

(DMA)

or under

request

bus

(NPR)

reguest

(BR)

for

interrupt

acquiring bus
lower

(INTR).

control

A device

by
a BR:

can

bus

perform

control

DMA

after

acquisition

priority.

Requests

for

(BR)

and

non-processor

from

one

device

arbitration

having

the

directly

the

bus

logic

can

made

request

another

after

during WAIT

Unibus

TRAP

data

any

(MNPR)
made

which grants

highest priority.

lines.

the

control

The NPP’s

cycles,

sequences.

The

time

bus

Transfer

processor

the

are

bus

are

request

bus

control

priority

serviced

addition

BR’s

the

device

before

and

specific

serviced

times

the

end

of the instruction if the requesting priority exceeds that of the
ProCcessor.,

The
it

processor
performs

master.
has

has

the

The

special

priority

processor

role

in bus

arbitration

assumes

bus

control
select

control

when

operations

the

bus

other

dev

ice

control.

The Unibus

originates

the

processor with

the

Internal Unibus

and Terminator modulé (M981) that carries the Unibus from the
processor

grounds

Flexprint
mounting

the

are

system

carried

cable may be
hoxes

mounting

box.

unit.

this

used

connect

All

one module.
connect

Unibus

In addition,

system

peripheral

signals

units

device

and

120-conductor

in different

removed

from

complete

description

presented

Handbook.

the

PDP-11

the

Unibus,

Peripherals

including

and

specifications,

Interfacing

1.3.2

KD11-A Processor

The KD11=A Processor decodes instructions, modifies data, makes

decisions, and controls allocation of the Unibus among external
devices. The processor contains eight hardware programming
registers which are used ‘as arithmetic accunmulators, index

register, autoincrement and autodecrement registers, and stack
pointer registers. Two registers are specifically used for

the processor:s program counter (PC) and stack pointer (SP).

Because of the flexibility of hardware registers, address modes,
instruction set, and direct memory access, PDP-11/40 programs are

written in directly relocatable codes. The processor also includes
a full complement of instructions that manipulate byte operands,
including provisions for byte swapping. Either words or bytes may
be displaved on the programmer’s console.

Any of the eight internal registers can be used to build last-in,
first-out stacks. One register serves as a processor (or machine)
stack pointer for automatic stacking. This stack handling
capability permits save and restore of the program counter and
status‘word in conjunction with subroutine calls and interrupts.

This feature allows true reentrant codes and automatic nesting of
subroutines. Addition of the KJ11 Stack Limit Register Option

permits alteration of the stack overflow limit and provides both

warning (vellow) and fatal (red) stack error indications.

The

Unibus

therefore,

device
the

used

there

becomes

bus

must

bus

make

bus

request

cycles

(NPR)

and

without processor

peripheral
to

generally

requests

device

interrupt
to

all

structure

branch

and

priority

nonprocessor

processor

end

nonprocessor

processor

master.

from memory,
to

the

transfer

program

interrupt
is

allows

data

execution
service

granted

bus

directly

and

request

which

use

force

the

processor

device-to-device

intervention.

determine

routine.

the

devices;

the

data

transfers

(BR)

granted

by the processor at the end'of an instruction and allows the
device

interrupt

instruction

The

processor

each

major

attached

closest
same

set

the

priority

processor

then available

four

contains

each

programmable

current

recognizes

level

the

major

processor
level.

within

given

The
the

levels

with

hardware

Many

the

entire

level

over
of

levels;

bus

devices

device

priority

The

for manipulating device

sublevels.

level

task.

that

the

requests;

can
is

other

registers.

be
electrically

devices

processor

therefore,

the

itself

running

program"can select the priority level of permissible interrupts.

Additional
through

the

speed
use

With vectored
unique
the

power

the

service

This

of device

are

added

PDP-11/40

interrunts,

interrupt

processor.

nesting

and

the

service

fully

device

routine

eliminates

interrupt

vectored

identifies

volling,

The

device

structure

interrunt

itself,

automatically

device

routines.

the

and

selected
permits

interrupt

scheme.

a
hy

priority
dynamic

and

service

adjustment

routine

priority

are

system

behavior

in response

independent
to

allow

real-time

conditions.

The
most

address

mapping

significant

bits

the
of

system

the

bhits

dependent
in

the

KD11-A

three

processor

address for the basic processor. If these bits are all 1s, the
two most
1s;

significant bits

otherwise,

Unibus

address

Option coverts
phvsical

Unibus

A detailed
KD11

the

two

are

forced

these

most

the Unibus

address

significant bhits

0s.

The

16-bit addresses

are

forced

the

18-hit

Manual,

the

KT11-D Memory Management

into

full

18-bit

addresses.

description of

Processcr

processor

DEC-11-HKDAA=-A-D.

presented

the

1.3.3

The

KY11-D

direct
stop,

The

Programmer’s

system
load,

displays

Programmer®s

Console

interface.

modify,

indicate

controlling

the

programmer’s

console

continue

and

bus;

address

thus,

console

provides

The

step,

data

Console

the

allows

programmer with

the

user

program.

well

operations

interacts with

can

the

start,

Console

which device

be monitored.

processor,

with

microprogram control for the processor operation located in
the

processor.

The

emitting diodes),
circuits

for

the

certain Unibus
and

DATI

responds

for
to

console

switches,

and

the

control

switches.

operations

through

EXAM.
a

contains

For

console

request

indicators

contact
Console

the

single=-step
bus

only

bounce

filtering

operation does

processor:

operation,
(CBR).

(light

The

DATO

the

require

for

DEP

processor

CBR priority

supersedes all other BR priorities. Note that use of the KM11
Maintenance
states

The

and

Console
allows

programmer’s

option provides

single microstate

console

BA11-FC mounting
box
of

two

and

further displav

of machine

stepping.

mounted

connected

the

front

the

panel

the

processor

means

cables.

Console operation,
indicators,
descriptions

is
of

including descriptions

presented
console

Processor Manual,

in Chapter
logic

circuits

DEC-11-HKDAA=-A-D.

1=-17

of
this

are

all

controls

manual.

covered

and

Detailed
the

KD11

1.3.4

MF11-L

Core

The ME?1¢L Core

access,
with

350 ns.

Memory

coincident
cycle

Memory

time

used

current,
of

The memory

900

consists

the

PDP-11/40

magnetic
and

core,

random

read/write memory

internal

ferrite

Svstem

access

cores

tire

wired

a planar

3-D, 3~wire configuratiofi that uses a shared sense/inhihit line.
The basic memory unit
modules
for

capable

storing

additional memory

equivalent
modules

providing

processor

bus master.

and

into

memory

can

true

device;

recuest

through

(NPR).

the processor,

(8K)

backplane

devices;

9-slot,

each
can

for

data

always

addressed

every

the

locatior

the

Provision
unit

three

and

from

1is

never

added.

transfers

core memory

slave

information transferred
Because

three

2-system

consisting

however,

and

16-bit words.

this

words,

Unibus

device,

out of

core

the

structure,

processor

can

the

any

functicn

hecause

accunulator.

not enter

never bus master.

the

(8K)

the memorv

be directly

The memory does

the memory

other

indicates

arithmetic

8192

made

the

the memory.

other master

Two MM11-Ls,

8192

Because

DATO or DATOB
master

backplane.

The core memory uses
the

consists

the priority

The master device,
either

Because

bus

any master device

with memory without processor

however,

request

the memory

structure

(BP)

can
or

completely

request use of
non-nrocessor

independent of

can perform direct data transfers

intervention.

detailed

Core

description

Memory

basically

manual,

the memory

DEC-11-HMELA-A-D.

an MF11-1 with

the

addition

presented

Note

that

mounting

the

MRE11-L

ME11-L

box

and

power

supply.

Note

that

applies

the

only

employ

memory

housed

instruction

for

special
in

the
MSYN
the

timing

MF11-L
signal
same

and

specified

MM11-S

between

mounting

the

memories.

the

box.

for

PDP-11/40

System

These memories

processor

and

the

1.3.5

There

Optional Memory

are

two

types

Systems

optional

memory

used with the PDP-11/40 System:
MM11-1,
PDP-11

and

core memories

systems

core memories

that may

similar to the

used with other members

the

family.

There are four memory systems
difference

is packaging.

MM11-L

to the MM11-L.

The prime

These four memories are:

8K by

16 bit,

modules

MF11-L

similar

and

900 ns

stack

cycle time,

only.

MM11-1L memory plus backplane

accomodating three MM11-L memories
in a double

ME11-1L

system unit.

Complete memory svstem consisting of

MM11-L memory, backplane, mounting box,
and

MM11=S

power

supply.

MM11-1 memory singularly in a single
system

unit.

There are five core memories desiqned for use with the PDP=11/20
System that may be used,

if desired,

with the PDP-11/40 System

provided they are powered by H720 type power supplies. These

are:

-y

memories

}

(

MM11-E

4K by 16 bit, 1.2 us access time

MM11-F

MM11-FP

an MM11-F

MM11-H

MM11-J

2K by 16 5it, 950 ns access time

Both

the

MM11-E

and

increments.

bit,

950

with

bit,

access

parity

950

MM11-F memories

Each

may

segment may

option

access

time

included

time

expanded

interleaved.

28K

1.3.6

DECwriter System

The LC11 DECwriter System is a high-speed teletypewriter system:

designed to interface wit@ the PDP-11 family of processors to
provide both input (keyboard)} and output (printer) functions

for the system. It can be used as the console input/output device.
The system can receive characters from the keybaord or can print
at speeds up to 30 characters per second in standard ASCII formats.
The ILC11 System consists of two distinct components:

an LA30

DECwriter and a DEC PDP-11 interface unit, which is referred to
as

the LC11

Controller.

The LA30 DECwriter is a dot matrix impact printer and keyboard

for use as a full-scale hard copy I/0 terminal teletypewriter.

The keyboard is either 97 or 128 characters. The print set is
64 ASCTII characters, 80 characters per line, 10 characters
per

inch.

The LC11 Controller is the interface between the DECwriter and
the PDP-11 Unibus. It controls data transfers between the

DECwriter and other devices in the system. It also monitors
print status, indicates when the kevboard buffer is full,
and enables the interrupt logic.

The LC11 controller consists of a single quad module that can be
mounted in the processor small peripheral controller slot. The

LA30 DECwriter is covered in detail in the LA30 DECwriter manual,

DEC-00~-LA30-DA

and

System manual,

DEC-11-HLCB=D.

Note

that

the

parallel

word

it is

used,

LC11

the

LC11

Controller

DECwriter.

controlled

covered

onlyv

LA30-S

the

DL11

used

the

LC11

with

serial

the

word

interface.

DECwriter

LA30-P

DECwriter

1.3.7

DL11

The DL11

Asynchronous

Serial

assembled
to,

Interface

Asynchronous Line Interface provides an interface between

a communications

Unibus.

Line

device,

such as

the

the Unibus so

and

information read or written by

or disassembled

from,

a Telet'pe,

Unibus.

that it is

the

The

control

for

also

the PDP-11/40

the

device

parallel

formats

the

1is

transfer
data

from

in the format required by the device.

The interface provides the flags that initiate thesé data
transfers and cause a priority interrupt to
of

the device.

The DL11

used when

a Teletype

system input/output device.

It is

communications devices

as datasets.

The

interface

such

indicate the availability
is

used as

also used,with other types of

transfers data via processor

cycles. Although a DATO can be used,

DATI and DATOB bus

normal operation consists

of a DATOB transfer because the device and the interface handle

by te, ratherAthan word, data. The interface can acguire bué control
by a bus request

(BR)

and is normally set at the BR4 priority

level. Because the interface operates by a means of an interrupt,
no non-processor request

(NPR)

There are five available DL11
DL11-E)

can he made.

interface options

(DL11-A through

in order to provide the flexibility needed to handle a

variety of terminals. For example,

the user can select an option

for interfacing a Teletype or display keyboard, for handling
EIA data, or for handling dataset devices.

In addition, depending

the

option used,

character

size,

the

user

stop-code

has

length,

choice

and

line

speeds,

parity.

The DL11 interface consists of a singie quad module. This
module

contains

incoming bus

address

address,

selection

interrupt

logic

for

control

interrupt,

and receiver/transmitter logic

conversion

and

formatting

functions.

The

decoding

the

for generating

that performs
interface

the

can

be mounted in a standard processor small peripheral controller
slot.

A detailed

the DL11

description

Asynchronous

the

DL11

Line manual,

interface

presented

DEC-11-HDLAA-A-D.

1.3.8

Power

System

The PDP=-11/40 Power
and

for

System provides power

expansion units

{e.g.,

for

extra memory

the basic

device

system

interfacesg)

mounted

within

the box

the

basic

BA11-FC mounting box.

limited by space

The basic

power

two H745

=15V regulators,

additional

system

space

and

consists

in the

and

on the requirments

availabh le power.

two

a base

H744

H742

system

(either H744

the particular

power supply,

{5V reqgulators.

H742 base power

additional power regulator unit

Expansicn within

for

or H745)

There

depending

system.

All regulated outputs are protected with current limiting

circuits.

In addition,

a crowbar overvoltage circuit protects

the +5V output and the

=15V output. An unrequlated,

partially

filtered 45V output is

supplied for the indicators on the

r console.
programme*s

Tn addition to voltage,

system:

other ocutputs are provided by the power

a line frequency signal,

a DC LO logic sianal, and an

AC LO logic signal. The line frequency signal, which is a sine
wave clipped at both ground and +5V,
interrupt clock option

(KW11-L)

is used by the line frequency

within the processor. The DC LO

signal indicates that the dc voltage outputs are not at the proper

value:

the AC LO signal indicates insufficient ac voltage.

The

basic

power

control

system

unit.

This

controlled
power

control

cabinet-mounted

unit

provides

860

thermal

and

over load protection for the base power supply. Overloads in the
switched

switch
fire.

line

removes
The

are

input

power

and

power

control,

LOCK "switch on the
supply

handled

the

which

console,
cabinet

circuit

event of

pwwer

and

excessive

controlled

applies
power

breaker

the

connectors.

the

thermal

heat

OFF/PWR/PANEL

base H742

power

1.4

APPLICABLE

PDP-11

Table

documents

1-2

two

System manuals.

specifically

DOCUMENTATION

main

System manuals

logic

Also

covered

programs

mdoules,

must be

Unibus

general
for

used

together

have

the

list

DEC

addressing

of other

the

modes,

information.

covering

running,

program

PDP=-11/40

overall

interfacing

loading,

and

manuals

covers

set,

listed

associated

documentation

A current

for

hardware

and

description,

are

handbooks

documentation

developing,

series

the

instruction

from

System

general

cover

software

obtained

PDP-11/40

General

applications.

programs may

the

necessary

diagnostic

Both

the

system descriptions,

basic

the

categories:

engineering drawings.
PDP-11

bhasic

and

available

library.

of manuals

and

general

a complete

understanding of

handbooks
PDP-11/40

systems. The prime subject of this series is the processor
and related

internal

options

Other handbooks discuss
to peripherals,
information.
provided

the

its

hardware

associated

the

PDP-11/40

system.

to connect the processor

themselves,

and

description of

programming
each

peripheral

hardware maintenance manual

peripheral.

with

peripherals

A detailed

the Unibus used

the

unique

supplied

Table

Applicable

1-2

Documents

Associated

Title

Drawing Set

PDP=-11/40 Processor
Handbook

J N/A

DEC, 1972

Description

A general PDP-11/40
System handbook covering

system architecture,
addressing modes,

the

instruction set, programming
merory

techniques,

management,

internal processor

bptions, console

operation, and systefi
specifications.

PDP-11
and

Peripherals

N/A

Interfacing

general peripheral

interface

Handbook

DEC, 1972

The

handbook.

first part

devoted tQ a discussion
of

the

various

used with
Systems.

peripherals

PDP~-11
The

second

pért provides detailed
theory,

flow,

(continued

and

logic

page)

Table 1-2 (Cont)
Applicable

)

Documents

Asspociated

Title

Drawing

Set

Description

descriptions
the

Unibus

external

and

device

logic;

methods of interface
construction;
examples

and

typical

interfaces.

Logic Handb ook
DEC,

1972

N/A

Presents
and
of

specifications
the

M~series

modules

used

types

logic

accessories

inter-

(includes

DEC

with

and

in PDP-11

facing

functions

logic

but

not

other

produced
used

the PDP-=11.

Table

1-2

Applicable

(Cont)

Documents

Associated

Title

Drawinc

Paper-Tape Software

Set

N/A

NDescrintion

Programmina

Handbhook

Detailed discussion
0f

DEC-11-GGPR=-D

the

PDP-11

ware

svstem

used

load,;,

dumn,

edit,

assemhle,

PDP-11

and

PDP=-11/40

System

PPDP-11/40

Svystens

Manual

DEC=-11-H405A

’

pro-

and

floatine

noint

qeneral

basic

irtro-

the

including

sections

stallation,

set.

and

PDP-11/40

system

and

the

naclkacaoe.

duction

debuda

aramminT:

math

nroarams;

input/outrut

soft-

the

operation,

instruction

Also

detailed

in-

nrovides

information,

includino maintenance,

(fi

of the svstem power
sunnlv.,

Table

1-2

Applicable

(Cont)

Documents

Associated

Title

KD11

Drawina

Processor

Set

PDP-11/40

Svstens

Descrintion

Block

diaaram

Manual

cussion,

DEC=-11-HEDAA=-A=-D

discussion,
of

flow

nrocrammer?®s

M”11

Svstem

XKJ11

stack

recister

-clocv

PDP-11/40

the

KY11-D

KV711-I,

Merory

for

processor,

lirit

Core

and

KN11-~

console,

ME11-L

diacram

theorwvw

omeration,

naintenance

dis-

line

ortion,

frecuencv

ontion,

and

mairtenance

console

ontion.

General

descrintion,
i

Manual

detailed

DEC-11~IIMELA-A=D

and maintenance of
the

MM11~-L

(Tote
the

descriontion,

that

riemorv

M11-1,

the

(contirued

core

memorv.

MR11-L

svster;
hasic

naage)

Table

1-2

Applicable

(Cont)

Documents

Associated

Title

Drawing

Set

Description

core

memory.

MF11-L uses

backplane

The

the

and

core memorf of the
ME11-L without

the

box and power supply.

DL11

Asynchronous

Line

Interface

PDP-11/40

System

Installation,

con-

figuration, programming,

Manual

and theory of opéra-

DEC-11-HDLAA~-A-D

tion

the

interface.

DL11
Covers

DL11-A

through DL11-E.
The

DL11=A

normally uéed as a
control

for

Teletype

DECwriter
DL11

can

variety

the

LA30-S

but
be

munications

the

used

for

com-

devices.

Table

1-2

(Cont)

Applicabie Documents

Asseciated
Title

KE11

Instruction

Drawing

KE11-E

Description

Set

Extended

data

programming,

theory

Set Options

Instruction

Manual

(EIS)

DEC-11-HKEFA=-A=-D

KE11-F Floating

maintenance

Instruction

KE11-E Extended

(FIS)

Set

Algorithms,

Option

and

Set

Option

operation,

for

Instruction

option

and

Set

the

(EIS)

the

KE11-F Floatihg
Instruction Set

(FIS)

otpion.

KT11-D Memory

Operation,

Management

and

detailed

Option Manual

operation

DEC=-11-HKTDA-A-D

KT11-D Memory

Management

programming,
theory
for

the

option.

(

Table 1-2 (Cont)
Applicable

Documents

Associated

Title

LA30

DECwriter

Drawing

Manual

Set

DEC-00-LA30-DA

Description

Presents
a detailed

discussion
DECwriter

the

including

installation,
tion,

opera-

principles

operation,

maintenance,

troubleshooting,
Y

engineerinag

- LC11

DECwriter

System

Manual

DEC-11-HLCB-D

and

drawings.

Provides

general

detailed

descriptions,

programming,
operation

LC11

the

DECwriter

LA30-P

when

(parallel)

system

device.

The

used

DFCwriter
a

and

for

interface.

LC11

and

used

input/output

Taklie

1-2

{(Cont)

Applicable Documents

Associated

Title
KL11

Teletype

Drawing Set

Description

DEC=~11=-HR4C-D

Provides general and

Control Manual

detailed descriptions,
programming,

justments,
tenance

for

Teletype

ad-

and mainthe

KL11

Control

may be used

that

instead

the DL11 Control.

Automatic Send-

Bulletin 2738,

Describes operation

Receive Sets,

two volumes,

and maintenance of

Manual

Teletype Corp.

the Model 33 ASR
Teletype unit that
can be

used

input/output device
with

the PDP-11/40

System.

Comparable

manuals

available

for

other Teletype models.

Table

1-2

Applicable

(Cont)

Documents

Associated

Title

Model

Printer
Parts

Drawing

Page

Set,

Set

Description

Bulletin

1184B,

Contaihs an illustrated

Teletype

Corp.

parts
as

breakdown
guide

for

serve

dis-

assembly,

reassembly,

and

ordering

parts

the Model

Teletype

Unit.

ASR

Comparable manuéls
available

for

other

Teletype models.

for

1.5

ENGINEERING

A complete
is

DRAWINGS

set of

provided with

noted in Table
reference or

engineering drawings and module circuit schematics
each PDP-11/40

1-2

System.

paragraph

1-4

second volume

These

either

prints

under

sets were

a Drawing

Directory

the Maintenance Manual.

The
i

engineering drawings
manual discussion.
list of prints

title,

and

PRINT SET

The

1972

are necessary and

The DDI

included

(Drawing Directory

in the

revision numbers.
indicates

DEC Logic

on DEC drawings.
conventions

interrelate with

set

each drawing

and

includes

the

that

Handbook contains

Index)

column

provides

number,

labled

CUSTOMER

logic

for

the

in the KD11

customer.

symbols used

A more detailed discussion of drawing

contained

drawing

provided

general

the

set

Processor Manual,

DEC-11-HKDAA-A-D with this convention directly applicable

the

processor and processor optiohs of the PDP=-11/40.

An overall corporate convention is useful
and

noted

in identifyinag prints

below:

D=-CS=M7233=-0-1
%

Original drawing

Series

size

Manufacturing variation
Drawing

Module

type

type,

type,
or a
DEC

part

equipment

7-digit

number.

CS:

Circuit

BS:

Block

schematic

BD:

Block

diagram

FD:

Flow

DD:

Drawing directory

MU:

Module

AD:

"'Assembly

schematic

diagram

utilization

drawing

UA:

Unit Assembly

WL:

Wire

PL.:

Parts

AL:

Accessory

list

In addition to the basic drawing number,

a second type of number

is used with logic drawings. It consistof
s a 3-digit number

located in the title block. For example:

KT11-D

Option

drawing

set

Sheet

this

specific

drawing

The processor drawing set uses a number designation for each
module.

Thus,

K2-4

indicates

sheet

indicates

the

U WORD drawing

designations

are

listed

the

set.

the

drawing

set.

Processor

drawing

set

XKD11-A Drocessor

Manual

with a descrlptlon éf the flow chart and logic diagram
conventions.

along

set

CHAPTER

2.1

INSTALLATION

SCOPE

Thisvchapter provides installation information and recommendations
to

ensure

proper

PDP=11/40

Only

installation,

subsequent

operation

the

System,

installation

options

and

included

the
in

basic

this

PDP=-11/40

chapter.

System

section

and
on

processor

installation

of periphefals is not provided because of the modular'and Unibus
concepts of the system. To install a peripheral, for example,
it

is usually only necessary to insert the interface module(s) into

the basic systém mounting box and connect appropriate cabling
between

the

interface

and

the peripheral

itself

that

and

recommended

preparation

specific

system

peripherals

are

with

the

peripheral.

normally covered

sufficient

particular

configuration

part of

the

Installation

time

given

site

attention

given

the

maintenance

in associated manuals.

especially

and

large

planning
user?’s

number

system.

There are two DEC documents that aid in proper site planninag:
the PDP=11
Worksheet.

Configuration Worksheet

and

the

PDP=11

Site

Preparation

The

configuration worksheet permits

system prior

ordering

that

the

user

lay out

aware

drawer

the

layout,

cabinet layout, and Unibus interconfiectiono This ensures that
the

proper

Unibus

number

length

drawérs

sufficient

and

for

cabinets

the

Site PREPARATION Worksheet permits

the

power

arrangement

operating

his

environmental

system.

environment,

requirements,

and

peripherals.

available

physical

the

and

user

that

determine

preparations,

The worksheet

power

used

system.

The

requirements,

are

provides

requirements,

specifications

data

service
for

and

the

phvsical
on

and

access

basic

svstem

A final lavyout plan should be approved jointlv by the user and
DEC

prior

to delivery of

modifications

shipment and

the

installation

installation of

DEC Sales Engineers
consultation and

installation

and Field

planning and

DEC representative
the

equipment.

either

process.

the

It is

site be

recommended
effected

that

prior

anv

system,

Service Engineers
it is

install

receommended

the

system,

are

available

that

for

a gqualified

or be present during

2,2

SITE

Adequate

PREPARATION

site

planning

and

preparation

can

greatly

simplify

the

installation process, resulting in more efficient and reliable
PDP=11/40

installation.

DEC

Sales

Engineers

are

for

consultation

customer

and

representatives

progress

paragraph

available

the

regarding

installation.

provided

primarily

Engineers

and

course

information

permit

Service

planning with

objectives,

The

Field

review

in
of

action,

this
the

site

planning.

é}

Physical Dimensions

2.2.1

The overall dimensions
PDP=11/40

and

System as well

total weight
of the

dimensions,

particular

weights,

and

cable

lengths of anv optional cabinets and free=standing perinherals
should bhe

known prior

The route

the

area

the

of doors,

eqguipment

be submitted

installation

passageways,

delivery of

to-shipment of

equipment.

site

etc.

the

travel

equipment.

from

should be

the

studied

taken

All measurements

customer receiving

and

and measurements
facilitate

floor plans

should

to the DEC Sales Engineer and DEC Field Service to

ensure that the

equipment is packed

suit the

installation site

facilities. Any restrictions (such as bends or obstructions in
ahllways,

etc.)

an elevator

should be

reported

to be used

for

DEC.

transferring

the PDP=11/40

and its related equipment to the installation site, DEC
should be notified of
so

the size and gross weight limitations

that the equipment can be shipped accordingly.

Installation site space requirements
specific

are determined by the

system configuration to be installed and,

applicable,

provision for future expansion.

when

To determine

the exact area required for a specific configuration, a
machine=room floor plan layout can be helpful. When applicable,

space should be provided in the machine room for storage of

| »}

tape

reels,

printer

the work

forms,

area with

the work

flow

installations

large

recommends

adjacent

storage

requirements

that

card

the

the machine

area

between

where

test

files,

test

equipment

etc.

can

The

integration

considered

relation

areas.

equipment

storage

area

maintained,
be

within

DEC
or

room,

Operational requirements determine the specific location of
the

various

options

and

free-standing

Dimensions,

weights

and

cable lengths of freéastandinq peripheral

equipment must be
during
‘must

site

not

connecting
should

known

located

distances

from

maximum

limits.

cables

exceed

considered when

Ease

of visual

Adequate

Space

planning

The

the

observation

area

console,

availability

expansion.,

planning.

for

system,
-

peripherals

basic

system where

the

The

following

PDP=11/40

input/output

installing

points

layout:

tapes,

etc.

for

the

system

operating personnel.

work

installation; preferably

and

access

Ce.

preparation

devices

prior

peripherals

contemplated future

Proximity

the

Proximity

cabinets

humidity

cabinets

and

controlling or

peripherals.

peripherals

air

any

conditioning

equipment.

The final layout should be reviewed by the DEC Sales Engineer,
DEC Field

that cable

Service,

and

limitations

in=house

have

engineering

not been

clearances have been maintained.

personnel

exceeded

and

ensure

that proper

2.2,2

Fire

and

The

following

aid

fire

providing

safequards

Safety

for

safety

precautions

installation

personnel
and

‘¢dry
of

and

Precautions

overhead

pipe®®

that

system

sprinkler

system

system,_upon

are

presented

affords

adequate

system

used,

detection

power

the

room

master

valve

f£ill

the

of
and

fire,

then

room®s

This

type

removes

opens

overhead

sprinklers.

If the fire detection system is the tyne that
shuts

off

the

power

battery-operated

provided.

automatic

system

release

used,

the

emergency

installation,

light

carbon=dioxide

an
CO

alarm
to

fire

should

warn

source

should

protection

sound

personnel

prior

within

the

installation.

power

connections

raised=floor

electrical
be

used.

are

made

bheneath

installation,

receptacles

the

floor

waterproof

and connections

operational

components,

recommended.

source

should

An adequate earth ground connection should be provided
for

the

protection

operating

personnel.

2=8

2.2.3

Environmental

ideal

computer

system which

room air
areas

room

provides

pressure

to prevent

Requirements

type
cool,

should
dust

environment

has

well-filtered,

kept

higher

infiltration.

air

distribution

humidified

than

that

air.

The

adjacent

2.2.3.1
are

Humidity and Temperature = The PDP~11/40 electronics

designed

operate

temperature

range

from

}

(?OQC) to 122°F (SOOC) at a relative humidity of 20 to 95%
without condensation.
that use

I/0 devices

However,
such

typical

magnetic

system

confiqurations

tape units,

card

readers,

etc., require an operational temperature range of from 60 F
(15°C) to 80°F (27°C) with 40 to 60% relative humidity.
Nominal

operating

conditions

for

typical

system

confiquration

are a tenperature of 70" F (ZOQC) and a relative hunmidity of 45%.

2=10

“

2.2.3.2

Air Conflitioning — When used,

equipment

should

the

conform

Installation of

Air

(non-residential)®®,
of

the

Number

°‘Standard
75,

for

the

requirements

Conditioning

N.F.P.A Number
Electronic

computer room aireconditioning
of

the

nad Ventilating
90A;

Computer

well

Systems®®,

¢¢Standard for
Systems
the

requirements

N.F.P.A.

2:.2.3.3

Acoustical Damping =~ Some perinheral devices

line

installations

that

acoustically

damped

comfort

printers

and

and magnetic

efficiency

use

tape

group

transports)
of

high

ceiling reduces
is

a major

the

concern

noise

are

here.

quite

level

noise.

(such
noisy.

devices,

Operator

;}f

2.2.3.4
are

part

Lighting
of

peripherals
conveniently

the

system,

should

observe

cathode=ray
the

tube

illumination

reduced

the display.

enable

(CRT)

peripheral

surrounding

the

operator

these

devices

2.2.3.5

Special Mounting Conditions = If

to be subjected
mounting

to rolling,

surface

securely anchored
Since

such

cabinets,

(e.g.,

the

pitching,

aboard

the

cabinets

that necessary modifications

the
should

bhe

floor by mounting bolts.,.

installations require modifications
DEC must be notified

PDP=11/40

or vibration of

ship),

installation

the

upon placement of

can be made.

the

system

the order

2.2.3.6

Static

annoyance

operational

Electricity

personnel

and

characteristics

Static

can,

the

electricity

extreme

cases,

PDP=11/40

can

affect

System

and

the

peripherals. If carpeting
is installed on the installation room
floor,
of

static

flooring

should

electricity.

with metal

type designed

Flooring

edges,

to minimize

consisting

should

of metal

adequately

the

effects

panels,

grounded.

2.2.4

Electrical

Reguirements

The PDP=11/40 can be operated from a nominal 115V,
or

230V,

50/60

voltages

should

Line voltage
the

nominal

vary

power

maintained

tolerance
value

source.

and

should
the

The

within

primary

the

defined

50/60 Hz
operational

tolerances,

be maintained within

50/60

line

}

frequency

10%

should

not
28

Primary

from

than

power

Hz.

the

lighting,

operation

The

PDP=11/40

the

building

point.

Direct

system

should

aire-conditioning,

not

affected

cabinet

power

any

grounding

questions
to

the

point

ground

regarding
DEC

provided

etc.,,

by voltage

transformer

installation wiring

Sales

that

surges

line

computer

fluctuations.

should
be

connected

building

power

the

requirements

Engineer

separate

or Field

ground

and

Service

Engineer.

Primary

power

compatible

The

with

PDP=11/40

Figure

2-1

outlets
the

basic

shows

the

PDP=11/40

system

installation
primary

requires

site must

power

only

one

input

connectors.

receptacle.
I

plug.

2=16

115V, OR 230V, 60Hz,SINGLE-PHASE,30A

(PIN VIEW OF MALE PLUG)
FRAME GROUND

(GREEN)

NOTE:
Hubbell
Nema

2610

L5-30P (plug)

L5-30R (receptacle)

NEUTRAL
OR
RETURN

(WHITE)

PHASE
(BLACK)

11-1134

Figure 2-1

PDP-11/40 Connector
2-16A

2.3

The

INSTALLATION

procedures

provided
of

the

PROCEDURES

presented

assist

PDP-11/40

the

following

in unpacking,

System

and

paragraphs

inspection,

associated

and

processor

installation
options.

CAUTION
Do

not

attempt

until

DEC

Field

Service

has

been

install

the

notified

Representative

system

and
is

are

a DEC
present.

2.3.1

Unpacking

Before unpacking

packing
has

list

the

equipment,

provided.

been delivered

and

Check
that

check

that
each

the

shipment

correct

package

against

number

contains

all

the

packages

the

items

listed on the accompanying packing slip. Also, check that all
k2

items

have

been

described

the

accessories

included
in

the

list

the

shipment.

Customer Acceptance
Unpack

following procedure.

the

cabinets

Procedures
as

Step

Remove

outer

Procedure

shipping

container.

NOTE

The

container

corrugated

either

straps

case

first

container

wood

around

the

polyethylene

Remove

the

tape

from

Unbolt

the

is
the

the

plastic

cabinet(s)

bolts,

located

facilitated

rear

from

securina
If

and

the

opening

perimeter.

the

cabinets.

»nins,

applicable,

door (s) .

shippinag

the

applicable,

shipping

lower

anv

supports

from

access

the

metal

remove

cabinet

cover

heavy

plvwood,

all

skid.

framing

Rerove

then

cleats

either

remnove

and

from

bhe

cardhoard

fasteners

remove

mav

skid.

Access

supporting

access

siderails,

door(s).

Remove

bolts.

Raise

the

level

leveling
the

feet

rollearound

that

thev

casters,

are

above

the

Use wood

skid

blocks

the

floor.

Roll

the

and

floor

system

planks

and

form

carefully roll

the

proner

ramp

the

location

from

the

cabinet onto

for

installation,
i

applicable,

repeat

Steps

through

for

the

expansion

cabinets.,

When

the

cabinets

are

oriented prorerly

procedure of Paragraphs
cabinet{s).

2.3.2

and

2.3.3

the

install

the

2.3.2

INSPECTION

After removing the equipment packing material, inspect the
equipment,

and

Inspect

follows:

report

any damage

Step

the

local

DEC

slaes

office.

Procedure

Inspect

external

surfaces

equipments

for

Remove

shipping

the

surface,

the

bezel,

bolts

from

the rear door of the cabinet,

cabinets

switch,

the

and

rear

light damage,

door,

then

etc.

open

and internally inspect

the cabinet for console, processor, and interconnedting
cable

damage;

modules,

hlower

screws,

etc.

Inspect

the

and

the

power

the

external

suponlv

connections.

rails,

damage,

side

loose

power

mounting

fan

wiring

broken wires,

Inspect

loose

for

anv

loose

logic

hroken

nuts,

panels

components

prorer

and

seating

for

bolts,

bent

foreign

fuses

pins,
material.

Step

Procedure

Inspect

all

peripheral

external

damage.

magnetic

tape

papere-tape

and

This

eguipment
includes

DECtape

sprockets,

for

internal

inspection

transport

heads,

motors,

etc.

CAUTION

not operate

which

any

peripheral

employs motors,

sprockets,

etc.,

damaged

tape

thev

shipment.

device

heads,

appear

and

,,_vc;-\\)

2.3.3

Cabinet

Installation

'The

PDP=11/40

and

adjustable

leveling

the

cabinet

the

cabinets

are

feet.

mounting

otherwise

(e.g.,

shipboard

procedures

are

follows:

provided

with

floor

not

rolle-around

necessarv

unless

conditions

installation).

Cabinet

casters

bolt

indicate

installation

NOTE

multiple

cabinet

installation,

receiving restrictions

shipping cabinets

pairs.

connected

such
at

Step

necessitate

individually

cases

the

may

the

cabinets

installation

in
are

site.

Procedure

With

the

cabinets

positioned

11952-GA

filler

strips

(filler

strips

are

cabinet

the front and

rear

between

shipped

group).

the

cabinet

attached

Remove

room,

bolts

filler strins.,

groups

the

each

Butt

install

from

the

cabinet groups together while holding the
filler

strips

both cabinets
Drawing
hbolts

in place

and

through

the filler strips

C~UA=H952=G=0)
., Do

securely

rebolt

this

not

time,

(see

tighten

end

the

Lower

the

leveling

are

not

are

supported

Use

that

resting

spirit
all

feet

the

level

leveling

that

the

rollearound

leveling

cabinet(s)

casters

but

feet.

level

all

cabinets

feet

are

firm

against

and
the

ensure
floor.
3

Tighten

the

together
Acain

bholts

that

secure

and

then

recheck

ensure

that

all

the

cabinet groups

cabinet

leveling

feet

firmly

Remove

the

shipping bracket

that

extendable

BA11=FC Mounting

Box

leveling.

are

planted

floor

secures
in

the

cabinet.

2.3.4

Power

Connections

A 3ewire cable is used to connect the
power

control

in the

top of

site source power to the

the H960=C cabinet

(see Fiqure

2=1

for connector type). The cable is connected at the factory for

either’230V, 50 Hz or 115V, 60 Hz operation. Most cabinets
in
a

PDP=11/40

svstem

include

power

control

and

single
ac

power cab le; power is distributed within the cabinet from the
power

control.

Power

cables

systen

that

ground

system.

are

intended

provides
One

power

the

connected

twco

site

single=phase,

wires

power

2=wire

should maintain

plus

constant

(neutral) voltage, while the supply voltage‘is developed on
the

other

The

cabinets

ground

(phase)

should

straps

In addition,

wire.

grounded

connecting
the

all

the

frame ground

earth

cahinets

wire

ground,

each

power

with

other.
cable

connects the cabinet ground system to the site power system
ground.,

Thekpower controls in all the cabinets are connected together
to

nrovide

These

connections

supplied

the voltage
same

central

systen.

each

control

reguire
power

supplicd

that

control

to all

power

the
be

turn=-cn

phase
the

same

other power

and

the
as

voltage

the

controls

turn=-off.

phase

the

Before connecting any power cables to the site source power,
check

all

customer wiringa

appropriate

types

the receptacles
positions
or

crossing

have

are

Ensure

been

provided

positioned

allow connecting
the

that power

close
the

for

each

enocugh

cables

cables.
In. particular,

receptacles
cabinet,

the

without

check

that

and

fi}
the

that

cahinet

stretching
the

phase

and neutral wires have bheen connected to the same pins in

each

receptacle,

the

same voltage

that

all

cabinet power

controls

receive

phase,

2:3.5

When

Intercabinet

multi-cabinet

connections

must

for mechanical

C.'

system

made

connections

last

system

unit

Remote

power

are

connected

for

system

Ground

assembled,

the

BC11=A

turn-on

distributed

cable

cabinet

all

Paragraph

electrical

2.3.3

are:

must

the

cabinet

control

and

turn-off,

the

frame

connections

types

connect

first

cabinet.

3-wire

through

(see

connections

connections
to

three

cabinets

These

unit

strapping

electrical

between

connections).

Unibus

the

Connections

the

bus

that

controls

provides

and

ground

cabinets

between

power

the

system

by direct
cabinet

frames.,

2.3.5.1

Unibus

H960=C cabinet

Connections

and

= To

connect

H960-D Expansion

BC11=A cable

the

rear

mounting box

the

H960-C

system unit

Cabinet.

the

Unibus

Cabinetp

slot

The

insert

the

cable

between

the

BA11=FC

then

runs

through

a cablé clamp in the upper left corner at the rear of the BA11=FC
mounting

box,

into

next cabinet.

the

through

slot of

the

and

similar

first

noted

above

the

last

box.

passed

cable

under

the

H960-D

clamp,

and

system unit of
an

the

example,

the

power

supply mounting

cabinet,

the

inserted

mounting box.

other mounting

cable
the

The

rails

passes

appropriate

BA11=FC

boxes might

bhe

2.3.5.2
has

Remote Power Connections - Each cabinet in the syséem

one

860

3-wire

emergency

power

bus

control.

that

turn=off

All

carries

signal,

and

the

power

remote
a

controls

turn=on

control

are

connected

signal,

ground;

there

are

three Mate=N-Lok connectors on each power control for the
3=wire

bus.

the

power

each

860

power

cable

control
power

that

control

controls

supplied

cabinet

must

the

with

each
the

capable

preceding

and

cabinet
next

connect

cabinet.

connecting

following

Because
the

cabinets,

two Mate=N=Lok connectors ére reserved for the intercabinet

cables. A third connector is provided for connection’to the

on/off switch, the thermal switch, or othef emergency shuteoff
devices

within

the

cabinet.

2.3.5.3

Ground Strapping -~ Electrical safety is provided by

connecting

all

site power

system.

power
is

ground

load

path.

ground,

This

cable between the

not a

that

the cabinet

while

improve

frame

the white wire

the

load

level

the

ground

done by connecting

green wire

the

connections,

carrying wire,
The

carries

frames

and
and

the power
is

a wire

of
in

the
each

system ground;

intended only

in each power

level

cable

the neutral,

the

this

emergencv
frame

or return wire,

current.

safety provided by

all cabinet frames

are

4 AWG

solid wire with crimp-on

to copper

studs

that are welded

the

frame

ground

connected by braided copper

straps of

lugs,

the frames

which

are fastened

(this

also prevents

the generation of ground loops between cahinets that are connected
by

signal-carrying cables).

side rails of

the

cabinet

The

studs

frame,

left side of the cabinet 1s

are welded

facing

inward;

the bottom

the

stud on the

slightly forward of center while the

stud on the right side is slightly to the rear.

one stud,

strap supplied with each cabinet is

passed over the

side rail of the adjacent cabinet,

the

and
are

studs.

]

studs

supplied

The copper

[A®]

in that cabinet.

fastened

side rail of that cahinet and the

The ground

}

fastened to the stud
threaded,

and

nuts

are

2,3.6

Remote

Peripheral

Interconnection

Installation instructions for remote peripheralsy
printers,

card

readers,

and magnetic

tape

units,

such as line
are

covered

the appropriate peripheral maintenance manual. Normally, the
peripheral itself
controller

and

mounted

connected

a basic

PDP=11/40

controller mounting

system

one

the

system

interconnected

power

System,
slot

input/output device

The

the

peripheral

small

peripheral

controller

must

source,

there

that

and

drawers.

houses

(LA30

a
the

controller

DECwriter

for

the

Teletype Unit).

This device is characteristic of remote peripherals installation.

When

installing

the

system

described

and

the
the

system,

input/output

the

following

Step

peripheral must be

also

is a free=standing unit and the péripheral

necessary

device

interconnect

(Teletype

or DECwriter)

steps:

Procedure

Place

the

desired

freestanding

position

DECwriter

the

Teletype

system

cabinet,

the

Step

Procedure

Run

the

control

unit through

cable

the

back

from

the

DECwriter

system

Teletype

cabinet and

through

the cable clamp at the rear of the mounting box. the
that,

because

size of

the

control

clamp must

first be

removed

connector

1is

into

box.

the

can

clamp

Connect

the

brought
be

control

the

small

cable

(DL11,

peripheral

that the

the

cable

before

Once

this

connector,

the

is done,

replaced.

controller

small

Verify
into

the

the cable

on the

connector

KL11,

controller

LC11)

slot of

controller meodule
controller

the

receptacle

mounted
the

plugged

processor,

securely

slot.

Connect the power cable from the DECwriter or Teletype
unit into

one of

the

cabinet power

receptacles.

2.3.7

Prior

Installation Verification

turning

power

internal

options

and memory

and

processor

gy R
s,

installation

options

should

on,

are

proper

installation

should

he verified.

installed

verified

the

all

processor

Although memory

system

the

factorv,

site,

Installation Verification procedures for the available processor
options

are

memory,

are

given

shown

given
well

Table

in Figure

in Table

2=1.

procedures

2-2.

2=2.

Verification

for

diagram

installing

the

nrocedures

for

additional

memnory,

memory

svstem

unit

core

Table

Option

2-=1

Installation Verification

Option

Procedure

KE11-E Extended

Instruction

Verify

that KE11=-E module

M7238
3

Set

(EIS)

Option

is installed in slot 2
A=-F)

processor

(sections

bhackplane

assemblv,

Ensure
K3=8

M7233
A=F)

that

jumper W1

has

been

that

the

cables

have

been

the

40=-pin Berg

the

M7238

KE11=-E

processor

section A=D).
required

hbetween
KF11=E

the

slot

sections

removed.

Ensure

the

KD11=A processor module

(located

M7232

three

connected

connectors

module

These
logic

and

the

(slot

cables

provide

interconnection

processor

ontion.,

overe-the=hack

module

and

the

Table 2-1
Option

Installation Verification

Option

KE11=F

Set

Procedure

Floating

(FIS)

Instruction

Option

Verify

been

that

installed.

prerequisite

Verify

that

KE11-E

The

for

the

KE11=F

module

processor

backplane

the

that

KE11-E

removed.

allow

execute

three

M7238

These

the

slot

the

KE11=F

M7239

(section A=D)
assembly.

jumpers

module

must

has

KE11-=F,

installed

Ensure

option

KE11=-E

is
0t

the

have

heen

removed

ontion

floating=pcint

to
instructions,

Jumper

Module

KE=2

M7238

KE=5

M7238

KE=9

M7238

Table 2=1
Option

{Cont)

Installation Verification

Option

Procedure

KT11=-D Memory

Option

Management

irequires

the

KJ11=2A installation
procedure

Verify

that

KT11=D module

installed

slot

processor

system

M7236

(section

A=F)

unit,

also)
2,

Verify

that

changes

below

processor

have

(these

detailed
section

in
of

been

made

changes
the

the

jumper
as

indicated

are

installation
KT11-D

ontion

manual)
¢

Verify
have

that

been

Jumper

the

following

jumpers

reroved:

Module
o

W10

K1=6

M7231

K1=-8

M7231

W6
W5

Table

Option

2=1

(Cont)

Installation Verification

Option

Procedure

Jumper

Module

K1=7

M7231

Ki=9

M7231

W2
w3
W4

W7
W8

Verify

been

jumper

that

the

M7234

following

have

added:

C106

C107

following

Kd=4

Verify
been

the

moved:

[on)

has

that

K4=4

M7234

Table

Option

2=-1

(Cont)

Installation

Verification

Option

KJ11=A Stack Limit Register

Procedure

Verify
is

that KJ11=A module M7237

installed

processor

2.,

Verify

slot E03

the

backplane,

that

processor

the

following

Jjumpers

have

been

changed:

Jumper

Module

W2k

K1=8

M7231

K4=4

M7234

K5=4

M7235

Jumpers
to

are moved

instructions

*Note

that

the

according
prints.
KT11=-D

present

Jumper

removed

completely.

option

of M7231

Table

2-1

(Cont)

Option'Installation Verification

Option

KW11-L Line

Procedure

Frequency

Clock

Verify

that KW11-L module

installed

backplane,

Verify

slot F03

that

M787

the

processor

backpanel

wire between pin FO3R2 and F03V2

KM11=-A Maintenance

Console

for

BG6
H has

This

option

length

been

removed.,

consists

module

(W130/W131)

doublethat

plugged into slot FO01 whenbused to
monitor
E01

when

KE11=E,

Note

KD11=A operation,
used
or

that

the

to monitor

KE11=F

this

and

slot

KT11=D,

operation.

option

not

system during normal

installed

use.

Table 2=2

}

Memory Verification or Installation

Procedure

Memory

{(basic to PDP11/40)

1. Verify proper address selection on jumpers

on CONTROL & DATA LOOPS(G110) module.

)
gy

MF11=-L Core Memory

2. Verify that modules are installed properly:

Slot

Module

MEMORY STACK(H214)

1,8ections C thru F

MEMORY DRIVERS (G231)

2,Sections A thru F

CONTROL & DATA LOOPS(C110)

3,Sections A thru F

3. Verify Unibus interconnection to the KD11-A
processor

(M980)

and interconnection or

termination to rest of system (M920 or M930).

4, Verify that system unit power cable

(D=TA=7009103=0-0) is connected from the
system unit to MATE=-N=LOK receptacles of

the power distribution panel lécated on the

BA11=FC mounting box. Connector P1 goes
to 3: connector P2 goes to 4.

Table
Memory

2=2

(Cont)

Verification

Memory

Installation

Procedure

5. Verify the interconnection of K4-4 MSYNA L
signal

from

the

(pin AN781)

MM11-L

Core

Memories

KD11-A processor
MF11-L memory

(pin C01U1).

Use

grounding

nearest

Select
on

proper

CONTROL

twisted

address
DATA

system

pair

ground

system

unit

wire with

pin.

selection

LOOPS

(G110)

either

set

jumpers

module.

{(additional
memories'added
to

Insert modules

locations:

MF11=L

memories)

Module

MEMORY

DRIVERS (G231)

CONTROL
MEMORY

Slot

DATA

LOOPS(G110)

STACK(H214)

Module

MEMORY

DRIVERS (G231)

CONTRO
& DATA
L
MEMORY

thru

5,Sections

thru

6,Sections

thru

Slot

LOOPS(G110)

STACK(H214)

4,Sections

7,Sections

thru

8,Sections

thru

9,Sections

thru

Table

2=2

(Cont)

Memory Verification

Installation

Procedure

Memory

Verify

the

interconnection

wire

wrap

of
%

pins

MF11=L

Core

CO03U1

Insert

the

C04U1

MF11=L

Memory

BA11=FC mounting

(expansion units

provided.

added

PDP11/40)

and

CNEUT

system

unit

bhox

using

CO7U1.

into

thumb

the

screws

basic
Rearrange

Unibus

using

M920

the

If memory

use

and

last

BC11=A cable

proper

CONTROIL,

Core

unit

for

termination

resnectivelv,
the

mountinag

interconnection

address
DATA

Insert modules

for

M930,

and

box

bhox.

Verify
on

connections

MF11=1L

LOOPS(CG119)

accordinag

Core

Memories

selections

Merorv

jumners

modules.

locations

(basic)

(additional).

and

noted

MM11eL

(

Table 2-2 (Cont)
Memory Verification

Memory

system

Installation

Procedure

unit

power

cable

(D=IA=7009174=0-0)

is used to connect the backpanel of.the

additional MFi11-L to the power diétribution
panel®s

MATE=N=LOK

receptacles.

paragraph 6.5.4 for power

6.,

Connect

the

K4-4

MSYNA I

See

loading restrictionéo

signal

from the

previous MF11=L system unit (pin CO9U1) té |
this

additional

MF11-L

system unit

(Co01U1) .

Twisted pair wire with grounding at nearest
pins

should

be used,

2.3.8

Before

Initial Power

turning power

described

the

Turn-0On

on,

check

following

the

PDP=-11/40

Procedure

Ensure

that all

(paragraph

installation verification procedures

2.3.7)

Before plugging

have

the

been

supply wiring harness

Note

that plugs P8

Turn off

the

regulator.

system ac

all

860

power

(see Figure

circuit breaker on

cables,

in the basic
2-3):

through P15 remain

(If more

performed.

the following Mate=N=Lok plugs

steps:

Step

system

the

disconnect

H742 power

through P7.

connected.

860 power

than one cabinet exists,

turn off

regulators.)

Plug in the ac power cable,
and check the dc voltages

turn on the circuit breaker,

generated
bv the

regulators.

ot
Cién

These voltages can be checked at pins of plugs P1
through P6.
numbers,

See drawing D=IC=11/40-0-2 for specific pin

Check fan ac power on plug P7.

Procedure

Step

Turn off

the circuit breaker

connectors

Turn on

through

the

console

the operation of

mounting

box.

all

P7).

the circuit breaker

operation

Check

(P1

and re=-connect

and verify correct

OFF/POWER/PANEL

all

fans

switch,

in the top of

the

‘.“

POWER DISTRIBUTION BOARD
MOUNTING BRACKET

FAN AC POWER

DISTRIBUTION

BOARD

11- 1388

Figure

2-3

D.C.
2=45A

CABLE HARNESS

2.4

INITIAL

Once the

OPERATION AND

PROGRAMMING

system has been installed and

operating and programming procedures

power

applied,

should be

preliminary

followed prior

to using the éystem@ Console operation, as well as the basic
operating procedures
first.,

the user

then the basic

already

immediately.

but independent from,
paragraph

After

the

should be performed

familiar with

console

operation,

in paragraph 3.6

These procedures

are

necessary

customer acceptance procedure

noted

2.5.

initial operation,

system,

in Chapter

operating procedures given

may be performed
to,

noted

peripheral,

These programs,

both procedures use

a common set of

and individual instruction diagnostics.

listed in Table 2=3,

define initial acceptance

and operation. They also provide for a continuing check on proper
operation as well as permit analysis of system failures.

2-46

Table
PDP-11/40

2-3

Diagnostic

Programs

Number

Tests

PROCESSOR

(INSTRUCTION

SET)

TESTS

MAINDEC=11=DOAA

Unconditional

MAINDEC=11=DOBA

Conditional

MAINDEC=11=DOCA

Single

operand

MAINDEC=11=DODA

Single

& double

MAINDEC=11-DOEA

Rotate/Shift

instructions

MAINDEC=11=DOFA

Compare

with

equal

MAINDEC=11=DOGA

Compare

with

not

MATHNDEC=11=DOHA

Move

MAINDEC=11=DOIA

Bit manipulation

MAINDEC=11=DOJA

Add

MAINDEC=11=DOKA

Subtract

MAINDEC=11=DOLA

Jump

instruction

MAINDEC=11<DOMA

RTS,

RTI,

MAINDEC=11<DCKBA=A

Sign

extend

MAINDEC=11=DCKBB

Subtract one and branch instruction

MAINDEC=11=DCKBC

Exclusive

MAINDEC=11=DCKBD

Mark

instruction

MAINDEC=11=DCKBE
*

Trap

and

_ MAINDEC=-11=DBKDM

Trap

instructions

MAINDEC=11=-D0OQB

T15

branch
-

branch

instructions
operand

instructions

results

equal

results

instructions

(BIT,BIC,BIS)

instruction
instruction

JSPR

instructions

instruction

interrupt

combined

return

error

instruction

traps

test

Table
PDP-11/40

2=3

(Cont)

Diagnostic

Number

Programs

Tests

MEMORY

TESTS

MAINDEC=11=-DZMMA

Address

test up

MAINDEC-11-DZMMB

Address

test down

MAINDEC=11=-DZMMK

Up/Down address

MAINDEC=11-DZMMD

Basié memory patterns test

MAINDEC=11-DZMME

Moving

MAINDEC=11=-DZMMF

MAINDEC=11=-DZMMG

Worst=case

noise

MAINDEC=11-DZMMI

Random data

test

MAINDEC=11=-DZQMBA

Memory exerciser

MAINDEC=11-DZQMBA

and

test for ACT=11

O0Os

susceptibility test
test

Extended memory exerciser

KE11=-E

(EIS)

OPTION

MAINDEC=11=-DCKBL

Divide

MAINDEC=11=DCKBK

Multiply instruction

MAINDEC=11-DCKBJ

instruction

Arithmetic shift combined instruction

MAINDEC=11=-DCKBI

Arithmetic shift instruction

MAINDEC=-11=-DCQKA

MUL/DIV Exerciser

Table 2-3

(Cont)

'PDP611/40 Diagnostic Programs

Number

Tests

KE11=F

(FIS)

MAINDEC=11-DBKEA

Basic,instruction tests

MAINDEC=11-DBKEB

Exerciser

MAINDEC=11=-DBKEO

GTP

overlay

KT11=D MEMORY

MANAGEMENT

MAINDEC=11=-DBKTA

Basic

logic

test

MAINDEC=11=DBKTB

Access

keys

test

MAINDEC=11=DBKTC

MFPI/MTPI

MAINDEC =11-DBKTD

States

MAINDEC=11=DBKTG

Memory managemen£ exerciser

MAINDEC=11=DBKTF

Abort

tests

test

KJ??»A STACK

MAINDEC=11=DCKBF

Stack

limit

KWi1-L LINE

LIMIT

test

FREQUENCY

CLOCK

/fi“‘@,

OPTION

MAINDEC=11=DZKWA

Line

frequency

clock

test

2.5

CUSTOMER

Verify correct
Acceptance

document
the
,

tools,

operation.

ACCEPTANCE

system operation by performing

Procedures.

The

shipped

with

programs,

and

Customer

the

Acceptance

PDP=-11/40

tests

required

System
to

the Customer
Procedures

and

certify

lists

all

system

3.1

SYSTEM

OPERATION

SCOPE

This

chapter provides

and program the

terminal

the

PDP-11/L,0

information necessary to

System and associated input/output

(Model 33 ASR Teletype or LA30 DECwriter).

descriptio
is
n divided into
console,

’

basic

The

operate

DECwriter,

five major parts:

Teletype,

basic

system

The

programmer!'s

operation,

and

system programming.

description of

consoles

type

function

and

Operating

controls

tabular

controls

form

each

and indicators
and

provides

operating

for peripheral

of the basic machine

are

for

the

user

switch and

devices

contained in the

the

that

with

the

indicator.

are

not part

appropriate

peripheral manual,

Basic

step-by-step procedures

operation

are

given

for both manual

in paragraph

3.5.

Basic

and program

system programming

covered in paragraph 3.6.

3-1

3.2

K¥1l-D PROGRAMMER'S

The KY1ll-D Programmer's

PDP-11/49H System with

interface.

CONSOLE

Console

a necessarv

Manual operation of

switches mounted on

(Figure

this

3-1)

the

system is

console which

displays

operation and

address

the

controlled by

the

Visual

contents

the

and useful programmer's

of the basic mounting box.

the

provides

front panel

indicate processor

and data

registers.

All register disfilays and switches, whether marked on the
console panel or not, are numbered from right to left. The
numbers

correspond

to the

powers

two,

i.e.;,

2
.cc..27,

Zlg 20, Therefore, the most significant bit (MSB) is at the

left of each specific re§ister or display, the least
significant bit

(LSB)

at the

right.

Whenever an

indicator

is on, it denotes the presence of a binarv 1 in the particular
bit position.
identifies

The

alternate color coding on the console

the different

number in octal

functions

or segments of the binary

format.

3-2

In addition

contains

the

alternate

color»coding,

an index mark that divides

(bits 0-7)

from the high-order byte

order byte

marks.

divided

No marks

into

octal

are required

the

DATA register

low-order bvte

(bits 8-15). The high-

format bv

for the

two more

index

low-order bvte because

octal coding for this byte is identical to the alternate
color

Figure

coding.

3-1

shows

the

location of all PDP-11/40

controls

and

function

listed

in Table

3-1.

function

listed

in Table

3=2.

indicators.

Each

indicator

Each

and

console

associated

control

and related

3-3

3-4

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DECWRITER

3.3

The

LA30

DECwriter unit

that can be u§ed with the
entered
the

into

processor

Controls

and

the

one

via

printed

indicators

the

input/output

PDP-11/l10 System.

processor

can be

for

the

out
the

keyboard

by
LA30

devices

Data can be
or

data from

the DECwriter.
DECwriter

are

shown

in Figure 3-2 and listed ih Table 3-3. Further detailed
operating information is

manual

(DEC-00-LA30-DA)

manual

(DEC-11-HLCB-D)}.

contained in the LA30

DECwriter

and in the LC1ll DECwriter System

3-138

cB2

CcB1

11-06TH

Figure 3-2

DECwriter Controls

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3-290

3.4

TELETYPE

The model 33 ASR Teletype unit is one of the input/output

devices that can be used with the PDP-11/40 System. Data
can be

entered into

the

processor via

the

keyboard

| thrbughya paper-tape reader. The Teletype can also be

operated off-line toi?unch fiaper'tapes; Controls for the
Model 33 ASR Téletype are shofin in Figure 3-3 and listed

in Table 3#&» Further detailed operating information is
contained ih the Teletype Corporation manuals listed in
Tabl
1-2 e
of this manual.

F igure

3 3

Teletype Controls

3-22

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3-26

3.5

BASIC OPERATION

Many methods

exist

for

storing,

modifying,

and retrieving

information from the PDP-11/140 Systefi. These methods
depend
on the form of the information, time limitétion
s, and the

péripheral equipment connected to the processor.
The

foliowing procedures are basic to the use of the PDP-11/10
System. Although they may be used less frequent
lj as the

prbgrammifig and use of the system become more sophisticated,
they are valuable in,pfeparing the initial programs
and in

learning the

function of

For an understanding of
-and

indicators,

programming

refer

techniques

Operating procedures

system input

the

are

output

various operational

paragraphs

are

and

given

3.2

the

Power

paragraph 3.5.1

Basic console
control

paragraph 3.5.,2

¢.

Manual

paragraph 3.5,3

program

Automatic program

paragraph 3.5.4

Running programs

paragraph 3.5.5

3.6.

following

categories:

controls

through 3.l;.

paragraph

separated into

transfers.

Basic

3.5.1

When
OFF

Power On

the
to

console

POWER,

OFF/POWER/PANEL

the

time delay allows
units

The

system is

(especially memory elements)

power-up

determined

the

power

initialized

initialization

the

turned

(or

zeroed).

setting

on,

the

microprogram

sequence

determined by

jumpers

logic

switch is

the

to logic

sets

set

executes

power-up

Status

the

controlled

the ENABLE/HALT

with the
on

directly

processor

to stabilize.

sequence

console ENABLE/HALT
is

turned from

sufficient time for voltages

microprogram control

switch is

switch.

ENABLE
a

when

power-up

vector

module

events

address

(M7285)

the KDl1-A processor. A new processor status (PS) word
and program counter

(PC)

address,

address

.and

vector

Program operation begins

portion
the

first

module
This

are unstacked from the
plus

with

the microflow with
instruction.

jumpers

location

are
can

Note

initally
be

changed

two,

that

set
to

respectively.

entrance

the

new
the

vector

the

FETCH

used

obtain

processor

octal

Status

location

accommodate

system

requirements.

3-28

If the console ENABLE/HALT
switch is
pover

set

turned

the

activation

The

on,

console

the processor microflow

microloop.

console

control

The

control

third position of the

which provides

set to HALT when

machine

switeh.

directly

awaits

the

OFF/POWER/PANEL

switch is

PANEL

for program operation
with the console

switches

disabled.

However,

the

console

switch

accessed.

3-29

3.5.2

Basic Console Control

Two major
the

areas

ENABLE/HALT

console

control

switch,

control;

and

exist:

which

control

sequences

used

3.5.2.1

ENABLE/HALT Switch

When

the

either
run.,

and

last

CONT

the

obtains
can be
to

begins

step

the

causes

operation

program

switches

the

processor.

in ENABLE),
program

system with a

specific

address

control,

and

clear

determined

(usually LOAD ADRS).

console

and

into

(ENABLE/HALT

initializes
at

influenced by

either

manually

switch

operation

console

control

CONT

switch

selects

data

switch merely releases

program

When

START

signal

the

processor has

the

The

for

control

The

the

continues.

ENABLE/HALT
control.

used.

The

through

The

set

LOAD ADRS,

CONT
the

switch is

switch

program

can
a

to HALT,

EXAM,
now

single

the

and DEP
cause

the

console

switches
processor

instruction

time.

3-30

3.5.2.2

Loading Data Manually

Whenever data is menually loaded into
desirable

upon

each

address

have

the

deposit.

and

locations

Thus,

continue

providing

programmer's

immediately

address

the

data

examine

logic

the

also

data

with automatic

incrementation.

address

increment
or

immediately

DEP,

This

does

the

deposit
having

ADDRESS

does

These
of

EXAM or

the

DEP

after EXAM

if EXAM is

increment

an EXAM

the

used

a word

changed

load

address

look

and
each

then

The

continue

are
EXAM

switches,

does

a HALT

used
DEP

used

and

and R(TEMPC),

and

DEP

after

isg

immediately

the

after

console

a location,

re-examine

not

used

immediately

increment

user can
data,

memofy

user

sequences

DEP

the

necessary,

functioning

starting

deposited without

increment

Thus,

the

sequential

permits

not

increment

oriented.

the

the first time

LOAD ADRS.

DEP.

re-deposit

automatically

set

it is

for each location.

Just

re-addressing,

The

can

only new data

console

associated with

increment

user

store

a computer,

after

EXAM.

word

change

it,

them without

time.

3-31

Incrementation

address

registers,

For

even boundaries

specifically designated
which

example,

following

steps

are

incremented

alter

are

several

for

all

addresses

the processor

except

internal

one.

successive

locations,

the

performed:

Step

Procedure

LLOAD ADRS

EXAM

DEP

for

(no
(no

(starting

increment
increment

location)

looks
loads

starting

location)

| EXAM (no increment ~ checks previous deposit)

EXAM

(increment

DEP

EXAM

(no

EXAM

(increment

(no

increment
increment
-~

looks

at next

loads
-

second

checks

looks

location)

previous
third

deposit)

location)

etc.

the

user desires

incrementation

take

advantage

for examining or

automatic

loading data,

the

address

following

steps can be used to load data into sequential locations:
Step

Procedure

LOAD ADRS

2
3

(starting

location)

| DEP (no increment - loads starting location)
:

DEP

(increment

DEP

(increment - loads

third location)

DEP

(increment

fourth

loads

second

location)

etc.

The

same procedure

sequential memory

can be

used

for examining data

locations.

3-33

gt
=

3.5.3

Manual Loading

A primary manual use
store
and

the

data

bootstrap
can

of the programmer's console is.to.
loader

stored

the

or modified

core

by manual

programmer's

console.)

instruction program that

a minimal

load programs
in

special

after being
tape

into

stored,

can

computer.
used

bootstrap

loader

can

for

format.
in
(An

DEC

turn

One

load

these

programs

use

the

(DEC-11-L3PA-LA)

tape

punched

programs,

any binary

explanation

(Programs

automatically

core memory from a paper

bootstrap

the

designations

into

The

memory.

format

the

number

given

Table

3-5.)

3-34

Tabie 3-5
Program

Identification

COMPUTER

PRODUCT,

Codes

IDENTIFICATION

;msmmmo*x
P

DEC-11-L1PA-LA

Format:

4
1

Notes:

Product Code

4 M4

3456

MAINDEC = maintenance library products
DEC = programming library products

Computer Series

i1 = PDP-11 Computer Systems

Major Category

L= Loader

Minor Category

I = first in a series of programs

(sequential numbers)

2 = second in series, etc.

Option Category

P = paper tape system

{(hardware required

H = high-speed reader and/or punch

to use software)

K = Teletype keyboard only

M = magtape

Revision Category
(sequential letters)

A = basic program

B = first revision
C = second revision, etc.

Distribution Method

L = listing
P = paper tape

Distribution Mode

= ASCII

B = binary (absolute)
O = other (bootstrap binary)

Example:

DEC-11-L2PB-PO

indicates a PDP-11

programming library pro-

duct, second in a series of loaders, requiring a
paper tape system to use, the first revision to the

program, supplied as a paper tape in bootstrap

binary format.
References:

’

DEC Classifying and Documenting Standard, DEC-00-BZZB-D.

A list of all identification codes is in the PDP-11 Convention Manual.

3-35

The

sequence

with programs

of loading
noted

Bootstrap

the

shown

Figure

3-l

follows:

loader

(DEC-11-L1PA-LA)

Absolute

computer is

loader

manually
switches:
automatic

loaded by
provides
loading

punched

special

console
for
of programs

special

format.

format;

loaded by bootstrap loader:
provides for automatic loading
of programs punched in binary
format.

¢c.

Selected program

punched
loaded

in binary format;
automatically by

absolute

loader.

3-36

PROGRAM
LOAD

USE ABSOLUTE
& LOADER TO
LOAD PROGRAM

USE
MAINTENANCE

“1LOADER TO
LOAD

USE BOOTSTRAP

TO LOAD

ABSOLUTE OR
MAINTENANCE

YES

-~ DO

YOU

HAVE

\\A BOOTSTRAP
“\_

ROM

LOAD BOOT
L.OADER

PROGRAM

PROGRAM
RUN

LOAD ADDRESS
AND START

PROGRAM

i1-1023

Figure 3-4

Flowchart of Procedure for Loading
and Running Programs

3-37

In order to eliminate the necessity of more than one bootstrap
loader,

the bootstrap loader instructions contain two

variables
memory

(x and y)

to provide compatibility with various

configurations

and reading

devices.

These

variables

are listed in Table 3-6. A complete explanatiofiwof the

bobtstrap loader program is given in Chapter 5 of the
Paper Tape

Software

Programming Handbook

further information may be

found

(DEC-11-GGPB-D);

the program listing,

DEC~11-~L1PA-LA.

The

following procedure

is used

for manually loading

the

BOOT loader program (DEC-11-L1PA-LA):

Step

Procedure

Set ENABLE/HALT switch to HALT to
to the console when powering up.

Turn

OFF/POWER/PANEL

energizes

the

give

bus

control

switch to POWER position.

programmer's

This

console.

Enter starting address of bootstrap loader (Table 3-6)
into switch register. Make certain that the correct

xx value is used (03774l for 8K memory, O7774L for
16K memory, 1377y for 2LK memory, etc.).

Depress LOAD ADRS

switch.

switch register is

shown

The address
on

the

set in

ADDRESS

the

display.

Enter starting address contents (016701) into

Lift DEP switch. The contents just entered in the

Enter

switch register.

switch register
contents

displayed in

address

the

into

DATA

display.

switch register.

NOTE
It

not

starting
address
time

DEP

necessary

address
is
is

has

load

been

addresses

after

loaded because

automatically incremented by
used

sequentially.

the

the
two

each

Procedure

Lift DEP

Repeat

switch.

steps

7. and 8

of the bootstrap
contents
the

address

xx7766,

value

locations

programs

make

certain

xx7744

the

used.
is

now loaded

through xx7766

automatically

load other

into memory.

Correct program entry can be verified by
examining the

addresses between xx7744

xx7766.

This

starting

address

the

starting

display.

setting the

into

the

Each time

are

the

address

and the

corresponding

This

last

been loaded into

the

memory

that

operation

programs.
step

may be

program has

system.

displayed.

sufficient
already

The program is

last portion of available
it tends

and is

available

survive program
for reloading

If the program is not intact,

according to

with

the DATA

again depressed,

contents

(verification)
loader

the

automatically incremented by

1f the bootstrap

and

The contents
shown

the EXAM is

two

stored

switch

switch.

addresses

step

and

accomplished by

depressing the EXAM

that

address,

loader program

can be used to

certain

correct y value

in memory

make

the

When

that

The bootstrap

last

location

used.

the

each

When

contents

and

correct

above for

loader.

the

above procedure,

load

beginning

3-39

Table

3-6

Bootstran I.oader

(DEC-11-L1PA-LA)

Bootstrap loader should be toggled into highest core memory bank.
Address

Instruction

xx7744

016701

xx7746

000026

xx7750

012702

xx7752

000352

xx7754

005211

xx7756

105711

xx7760

100376

xx7762

116162

xx7764

000002

xx7766

xx7400

xx7770

005267

xx7772~

177756

xx7774

000765

xx7776

VYYVVY

xx represents highest available memory bank. First location of the loader is one of the following, dependi
on memory size; xx in all subsequent locations is the same as the first.

Address

Memory Bank

Memory Size

077744

16K

137744

24K

037744

157744

“

28K

ape reader to

Contents of address xx7776 (yyyyyy) should contain device status register address of paper-t
be used when loading the bootstrap formatted tape. Addresses are:
Teletype Paper-Tape Reader

177560

High-Speed Paper-Tape Reader

177550

3.5.4

Automatic Loading

Information can be stored or modified invthe'computer
"automatically only if a program capable of performing these
functions has previously been stored in the core memory.

For

example, having -the bootstrap‘loader stored in fhe computer
enables the user to operate

any program that has been punched

in the special tape format required by the bootstrap loader.

Typical programs of this tYpe include the absolute loader,
the absolute dump,

and the teleprinter dump.

The bootstrap loader is
format;

limited because of the

another loader is used to

tape intc the computer.
11-1.2PB-P0O),

which

This

special tape

load any binary format

is the absolute loader

loaded into

the

(DEC-

computer by the boot-

strap loader. Once the absélute loader is in memory, any
binary tape program

(such as PAL III

editor,

service routines,

input/output

ematical routines,

assembler,

symbolic

diagnostics,

math-

etc.)‘may be automatically loaded.

The following paragraphs give procedures

for loading the

absolute loader,

and for using the

other programs.

A complete description of the absolute

loader program is give in Chapter

ware Programming Handbook
program listing,

absolute loader to

store

5 of the Paper Tape Soft-

(DEC-11-GGPB-D);

refer also the the

DEC-11-L2PB-LA.

2-41

3.5.h.1

Loading Absolute Loader

The follow‘ng procedure is used for automatically loading the
ABSolute Loader Program (DEC-11-L2PB-PO):
Procedure

Step

switch to HALT.

Set ENABLE/HALT

Make certain that the bootstrap loader has been

stored in core memory (refer to Paragraph 3.6.3,
step 11).

Enter starting address of bootstrap loader into
switch register. The starting address is xx7744

(037744 for 8K memory, 07774y for 16K memory,
13774 for 24K memory, etc.).

Depress LOAD ADRS switch.

The address set in the

switch register is displayed in ADDRESS REGISTER

indicators.

Set Teletype LINE/OFF/LOCAL switch to LINE.

connacts the Teletype to the computer.

This

NOTE

If some other reading device {such as
the high speed paper tape reader) is
used, make sure that the y value in
bootstrap loader address xx7776
corresponds to the device as described
in Table 3-6.

Place the absolute loader tape in the Teletype
reader. Make certain that the special leader
(a sequence of 351 punches) is under the reader
station.

Blank leader does not work.

Set ENABLE/HALT to ENABLE.

Depress START switch.

The tape is now read into

the computer which halts when the entire program
is loaded.

Upon completion of loading this tape, the DATA display lights may be in any configuration. The main

Z-42

reason for this is that no checksum
exists

capability

the bootstrap loader.

Any PDP-1l program punched
.in binary

format may Be loaded

automatically by using the absolute loader. The absoclute
loader

can be

code.

set

relocatable

specify that the

select~either
code

absolute or relocatable

selected,

relocatable code

start

the user may

a specific

address

or that the code start laading at the point the previous
1oad-st0ppede

The absolute loader also provides a checksum

test to ensure accurate loading.

Although the computer

normally stops when the’binary tape is loaded, instructions

on the tape itself may cause the computer to begin éxecution
of the program immediately after loading is finishedo

This

action is beyond the contrdl of the user because._it is akpart
of

the program on

The

certain

following procedure

binary

tapes

into

the

used

Make certain that
stored

automatic

using

Set ENABLE/HALT

Enter

starting

the

absolute

switch

absolute

of
loaders:

The

loader program is

to paragraph 3.5.4.1).

to HALT.

address

the

Procedure

core memory (refer

switch

tapes.

for

computer by

Step

binary

absolute

starting

loader

address

into

isyx7500

(037500 for. 8K memory, 077500 for 16K memory,
137500 for 24K memory, etc.).
.
e

Steg

Procedure

Depress LOAD ADRS

switch.

The starting address of

the absolute loader is now displayed in ADDRESS
REGISTER indicators.

Select the type of load desired by setting switch
register as

specified in Table 3-7,

Table

‘

3-7

Binary Tape Load

Selection

{(using ABSolute Loader)

Switch
Tyvpe of Load

Normal

(absolute)

Relocatable

Bits

Bit

Not applicable

(continue

where left off)
Relocatable

15-01

(load at

specified address)

Offset

from

tape origin

Make certain that input/output device (Teletype unit
of LA30 DECwriter) is on-line.

NOTE
The

reading device may be

time by the user without
absolute

loader.

changed,

simply

replace

address

status

xx7776 with

address

Load desired binary
leader under

the

reader

the

(y value
tape

reader

changed

into

reloading

the

any

the

to be

contents

appropriate

of
device

in Table 3-6).
reader by placing

station.

3-44

Procedure

Set ENABLE /HALT switch to ENABLE.

Depress START switch. This bégins the binary tape
load.

If the binary

instruction,

tape

the

the program as

contains

soon

The computer stops when
or

there

a transfer

computer begins

checksum

complete

address

execution of
complete.

either loading is complete
error.

the

low-order

byte displayed

(right hand)

in the DATA indicators is zero.
Additional binary tapes may be loaded by repeating steps 5 through 7 above and depres
sing
the CONT switch.

Checksum error-

in the DATA

the

low-order byte displayed
is not zero, thereby

indicators

indicating

a checksum error has occurred ipthe
previous block of data. 1In this case, reposi
tion
the tape in front of the error-producing block
and depress

the

CONT

switch.

3-435

3.5.4.3

Loading Maintenance Loader

The maintenance Loader program,
an

alternate method

can be used

MainDEC-11-D9EA,

loading diagnostic programs

the Absolute Loader

because

used

load diagnostic programg

a hardware

provides

failure.

fails

This

loader

that

function
should

only be

the Absolute Loader

malfunctions.

Use the

following vprocedure to automatically

maintenance

load

the

loader:

Steg

Procedure

Set ENABLE/HALT switch to HALT and depress
START

Make

clear

the

certain that

system.

the bootstrap

been stored in memory,

loader has

starting at address

037744,

NOTE

The maintenance loader operates in the
lowest 8K of memory. If some other memory

area must be used,

several

must be changed as

listed in Table 3-8

after

the maintenance program is

Set switch register to 037744

Set Teletype LINE/OFF/LOCAL
Place

program locations

the

maintenance

loader

loaded.

and depress

LOAD ADRS.

switch to LINE.
tape

in paper-tape

reader.

Set ENABLE/HALT switch to ENABLE and depress START,
The tape is read into memorv and the processor halts
when

the

entire program has

been

loaded.

NOTE

the

maintenance

loader was

not

loaded

into the lowest 8K of memorv, make location
changes at this time (see Table 3-8).

3-46

Table 3-8
Maintenance

Change

Loader Location Changes

Contents

For Different Memories

of:

To:

xx7502
xx7510

xx7566

XxTUT70
xx 77l
xx7h 75
xx7h75

XXT767L

xXTLTY

xXX75).2

xx762l

Where xx equals:

xxT7776

03 for 8K memory
07 for 16K memory

for 24K memory

3-47

3.5.5 Running Programs
When

running

any program,

into the core memory

the program must

loading programs

loader).

Once the program is

any time by

(refer to

loading the

(bootstrap loader or absolute
in

storage,

it can be run

starting address of the program

appropriate program documentation}

depressing the LOAD ADRS

pressing the

START

loaded

either manually or by using one of the

automatic

first be

switch.

switch,

The user

that the ENABLE/HALT

switch

appropriate external

devices

into

the

switch

and then de-

also must make certain

in ENABLE

are on-line

and that the
(connected to

the

computer).

The program can be manually

stopped at

the ENABLE/HALT switch to HALT.

any time by

can be restarted

setting

from

that point by returning the ENABLE/HALT switch to ENABLE
and depressing the CONT

switch.

It can be

started anew by

reloading the starting address and depressing the START switch.

A program can be

introduced,
register has
in its

altered during operation,

through the switch register.
a bus

instruction

address

or new data

This console

that the processor can reference

sequence.

The

information transferred

may be treated as data or used to alter program flow.

Because of the

speed of the computer,

console indicators are

3-48

of limited value while thé computer is running. Major
use
of

the

indicator

panel

single

instruction

mode.

During manual

reflect

the

made

operation,
operation,

console operations

During maintenance

operations,

during manual

or during
the

the maintenance

console

indicators

of LOAD ADRS,

the

operation,

EXAM,

and DEP.

console indicators

displéy various éata functions‘of the processor as the
maintenance

module

used

step

through

the

program

a microword at a time. Use of the maintenance
modulé is
described

the

KD11

Processor Manual,

DEC-11-HKDAA-A-D.

3-49

3.6

BASIC PROGRAMMING

order

and
user

to produce

flexibility
to

first

techniques

of the

the

become

that

are

subroutine

and recursive

PDP-11/140
detailed

that

PDP-11/Li0,

fully utilize
it

part

the

These

linkage,

programming,

basic

techniques

etc.)

are

In addition

the

(such as use

nesting,

covered

general

instruction

familiarize himself with console

and with the basic

instruction sets

reentrant

the

set.

programming information given

PDP-11/lj0 Processor Handbook,

paragraph 3.2)

the

philosophy

Processor Handbook which also provides
discussion

power

programming

design

interrupt

the

necessary for

familiar with various

PDP-11/10 System.

stacks,

in the

programs

the user should

operation

(described

and extended PDP-11/140

(Chapter l).

3-50

In the event the user is already familiar with progfamming
the

PDP-11/20

comparing

two

systems.

Basically,
These

System,
the

prime

These

the

programming

PDP-11/l40 has

Memory Management

(FIS)

PDP-11/10

differences

capabilities

Floating

the

are

can quickly be
differences
listed in

Option

between

Table

added capabilities

increased even more

and the KE1ll Extended

Instruction Set

Options

are

learned
the

3-9.

and speed.

the KT11-D
(EIS)

and

included
in the

system,

Note

that

- four more

are:

the basic

PDP-11/L0 System

instructions

than

eXclusive
OR (XOR},

the

(without

PDP-11/20.

Subtract One

options)

These

and Branch

has

instructions

(SOB),

ReTurn from inTerrupt (RTT), and Sign eXTend (SXT).

3-51

Table

PDP-11

3-9

Programming

Comparison

PDP-11/20

JMP/JSR (R)+ uses

PDP-11/L0

(REG)+2 as address

JMP/JSR

(R)+ uses

{(REG)

before

auto-increment as address. All
auto-increments are now post
auto-increments.

A1l REG 6

(SP)

autodecrement

Address

references can cause overflow,
Address modes I} and 5, JSR and
traps are tested.
No red

zone

stack

and

modes

traps

nonaltering
stack

overflow.

Red

data

zone

1,2,lt,

are

and

(DATIs)
are

always

trap occurs

PC+2

locations

SWAB instruction
affect

does

not

ogan

SWAB

Program HALT displays PC of
instruction in ADDRESS

HALT

display.
Byte

and

instruction

that

allowed.

stack is

on new

This

trap

stack

O.
clears

Program HALT

displays PC+2 of
instruction in ADDRESS
display.

HALT

Byte cperafiions to the odd byte

operations to the odd
byte of the PS cause odd
address traps.

bits

No RTT

If RTT

instruction.

and

JSR

references

16 words below boundary.
saves

tested except

the

PS do not
may exist.

trap.

Not

all

sets

the T bit, the T bit
occurs after the instruction
following RTT,.
trap

If RTI

sets

T bit,

bit

trap

If RTI

sets

bit, T bit
immediately

trap

acknowledged after instruction
following RTT,

acknowledged

Explicit

Only implicit references (RTI,
RTT, traps, and interrupts) can
load T bit. Console cannot load
T bit but initialize can clear it.

reference to PS can
load T bit. Console can load
T bit, initialize can clear it.

following RTI.

Table 3-9

(continued)
PDP-11/20

PDP-11/L10

0dd address or non-existent
references using the SP cause
a HALT. This is a case of double

bus

error with a

occurring

the

second error

in the trap
first error.

octal 00 with violations
serviced

by an

OVFL

trap.

fatal

trap. On bus error in
service, a new stack is
created at locations 0 and
2.

trap

service

Stack limit boundary fixed at

0dd address or non-existent
references using the SP cause

‘

Optional variable stack limit
boundary (KJ11-A Option). Use
of red and yellow zones on
either basic (octal [j00) or
optionally variable

First

instruction in an
interrupt service routine
is guaranteed to be executed.

The first instruction in an
Interrupt routine is not executed
if another interrupt occurs at
a
higher priority level than was
assumed

Power up
power

vector at

2l when

returns.

Power up
;

can

the

interrupt.

initially at

jumpers

other

The formerly unnamed instruction
for IR

code

now

called BPT.

trap instruction to vector
location 1l exists for the
IR code 3. No name is given
this instruction.
‘

first

vector is
alter

addresses.
A

boundary.

3-53

Table

3-9

(continued)
PDP-11/20

PDP-11/110

NOTE
The following is the sequence of service
for internal processor traps, external
interrupts, and HALT and WAIT.

BUS ERROR

TRAP

data time

out.

odd

address,

X
e

BUS

ERROR TRAP - odd address, fatal
stack overflow (red); if KT11-D option
is used, memory management violations

to 250.

HALT

instruction

for

consocle

Same.
(Refer to KT11-D,
for other changes.)

operation.
TRAP

instructions

illegal

regserved
10T,

instructions,
EMT, TRAP.

TRACE TRAP

T bit

processor

status

OVFL

trep

PWR FAIL
CONSOLE

stack

trap
BUS

operation

TRAP

instructions - Illegal
reserved instructions, BPT,
EMT, TRAP,

TRT,

‘

OVFL

power down

Same

REQUEST

console

installed,

or
I0T,

S ame

overflow

after HALT

UNIBUS BUS
request,

warning

(yellow)

stack

overflow

Same

switch
peripheral

S ame

compared with processor

priority,

usually an

interrupt

occurs.

WAIT

LOOP

instruction

loop

the

an interrupt allows
CONSOLE BUS REQUEST
to

this

loop

a WAIT

Same

IR until
exit.

“

returns

after being

honored.

3-5%

li.1

PROCESSOR INSTRUCTIONS AND OPTIONS

SCOPE

The purpose
of

the

PDP-11

available

for

Paragraph l{.2

this

chapter is

instruction
the

set

PDP-11/40

discusses

to present
and

the

a brief introduction

processor options

System.

the basic

PDP-11

instruction

set

and also covers the expanded inst
ructiong that are
available

KTi1-D)

are

certain processor

installed in

Paragraph li.3
mounted in

the

appropriate

the

describes

specific

basic

each of

the

containing

These

(KE1l1l-E,

options
snd

detailed

options

KE1l-F,

and

system,

KDl11-A processor

documents

option.

the

options

are:

that

can be

references
information

KEll=E,

KEll=F,

" KJ11-A, KT11-D, KW1l-L, and KM1l-A with an addit
ional
Small

Peripheral

in Tables =12

Controller,

units

memories,

are

contained

through lL-16,

Information on memory units
These

Specifications

include

the

MM1l-L,

presented
MPll-L,

in paragraph l.l,

ME;lmLy

and MM1l=S

INSTRUCTION SET

This

section summarizes

the

PDP-11/L0

address

modes

and

instruction set. Its purpose is to define the KD11-A and
provide

tabular,

description

PDP-11/li0

Wwith additional

PDP-11/Li0

The

quick-reference

details

the

processor

Table

used

chapter.

this

notation

Handbook.

flow

defines
A more

diagram description

the

basic

(

)

paragraphs

instruction

instruction
KDl1ll=A

and

complete

instructions,

provided

the

set

ued

Processor

ISP

the

Processor

and

the

and

extended

used

are:

an expression indicates

indicates

logical

indicates

logical

negation

plus

indicates

addition

minus

indicates

subtraction

around

ISP

(paragraph h.2.,1}),

conventions

>or [ ]

)

implementation.

is usfor
ed
<
(

and

block diagram

(paragraph 4.2.2),
The

symbology

PDP-11/l10

address modes

(paragraph L.2.3).,

used

description

address mode

the modified

instruction

cover

set

each

detailed

notation

for

Appendix A

Similar notation

following

(ISP)

operations

-1

provided

The

the

examples,

Processor

instruction.
in

and

modes

Processor Handbook.

Instruction Set

define

address

information.

[

logical

Table

4-1

ISP Symbology

Symbol
{)

Definition
Defines the limits of an expression, such as word length (15:0).

Defines the limits of a memory declaration: Mw [SP] specifies the address

stack pointer in memory.
-

of the
|

The expression to the left of this symbol is replaced by the

of this symbol,

expression to the right

)

Z < | indicates the Z bit is set,
" PC « PC + 2 indicates the program counter register (PC) is increment

ed by 2.

cat

Indicates concatenation; registers to the left and right of this

ered to be &ae reguster

equiv

Designates that expressions to the left and right are equivalent.

Logical AND

Logical inclusive-OR

Negate

XOR

’

expression
are consid-

Logical exclusive-OR -

Indicates that a reference to the expression with which this symbol is used may

cause side effects, e.g., registers may be changed as a result of the

;

operation.

Used as a delimiter
A sequential delimiter, the operation to the left must occur before the

the right.

ignates an address mode; address mode 1 is indicated by m= 1.

General register 7 (program counter)

Auto-increment; by 2 for word instructions, and by 1 for byte instructions.

operation to

Indicates a result; used many times with limit symbols as an

intcmedia&e regig@gg

{5:00).

Addition; expression to the left is added to expression

Subtraction; expression to the right is subtracted from expression

Multiply; expression to the left is multiplied by expression to the
right.

Divide; expression to the left is divided by the expression to the right.

sign-extend

’

T
to the right.

to the left.

The sign bit of a byte, bit 7, is extended through bits 8 to 15.

Memory word declaration; the address in brackets points to the memory location.

nw’

Indicates next word, as pointed to by the PC with side effects (’).
The word is at
the next sequential PC address, or the word pointed to by the next word
(deferred
addressing).

R [dr]

Indicates that a register (R) address as a memory declaration is that of a device

Destination

Byte destination

Source

' Sb

Byte source

h.2.1

The

Address Modes

instruction

interacts

with

address modes.,
including
These

the

address

designation,

set

the

general=purpose

Table -2 lists
program counter
modes,

determine

format

all
(PC)

along with
the

(source and/or destination)
instruction

PDP-11/)0

(Figure

the

System

registers
of the

flexibply

through ths

address modes,

address modes.

general-purpose

instructions!

operands

and form part of the 16-bit
l-1).

Tahle

4-3Q,

Address Modes

Mode |- Designation | Symbolic' |

ISP

Description

General Purpose Register-Addressing

@R or (R) | if (m=1) then M[Rr];

deferred
2

if (m=0) then Rr({w1:0);

;

auto-increment | (R)+

The register (R, Rr) is the operand.
Defer to operand through register

(R, Rr) as address.

’

if (m=2) and (rg#7) then

Defer to operand through register

(M[Rr]; next

(R, Rr) as address, then increment,.

Rr + Rr + ai);

auto—inérefient

@(R)+

deferred

auto-decrement —(R)A

if (m=3) and (rg#7) then

[Rr] as address, then increment

Rr+Rr+ 2;

if (m=4) then (Rr + Rr - ai); | Decrement register (R, Rr), then defer
-next M[Rr];

to operand through register (R, Rr) as

address.

auto-decrement | @-(R)

if (m=5) then (Rr « Rr - ai; | Defer to operand through (R), Mw

deferred

next M[Mw[Rrl]);

indexed

+X(R)

Rr after decrement of register (R, Rr).

if (m=6) and (rg#7) then
M{nw’ + Rr];

Defer to operand through (R), Mw

(M[Mw[Rr]];next

Index via register = (R, Rr) by the
| amount specified in next PC word (X).

indexed

@+ X(R) or|

if (m=7) and (rg#7) then

Defer to operand through index of

deferred

@(R)

M{Mw[nw’ +Rr]l;

‘

PC Register Addressing
2

immediate

if (m=2) and (rg=7) the’n'

Defer to operand through PC value

nw’ (wi:0

(next word); next word is immediate

. ~operand.

absolute

@#A

if (m=3) and (rg=7) then
M{nw’]

relative

| relative

deferred

Defer via next word (PC address) as
address to operand; absolute address-

‘£

ing.

if {(m=6) and (rg=7) then

Relative to PC; uses next word as de-

Minw’ +PC];

ferred address of operand.

if (m=7) and (rg=7) then

Defer relative to PC; uses next word as

M{Mw{nw’ +PC]];

address of deferred address of the operand.

NOTE: The following symbols are used in thivs table:
R

’

= Register

X, n, A = next program counter (PC) word (constant)

SINGLE OPERAND
|
"

%%
|

}

I\,

OP CODE
%= SPECIFIES DIRECT OR

MODE
4

' @
N

|
v

"
Ty

]

0
J

)

DESTINATION

ADDRESS FIELD
INDIRECT ADDRESS.

%%= SPECIFIES HOW REGISTER WILL BE USED.

##% = SPECIFIES ONE OF EIGHT GENERAL PURPOSE REGISTERS.

DOUBLE OPERAND

%% %

OP CODE

MODE

| @

12\11 10.9

MODE L @

6415

SOJRCE

ADDRESS

R#E

FIELD

4'3

DESTH‘;ATION

ADDRESS FIELD

#=DIRECT/DEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS.

w#=SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED.
wux=SPECIFIES A GENERAL

Figure 4-1

Double and Single Operand
Addressing

L-6

i.2.2

The

Basic Instruction Set

KD11-A basic

instruction

of instructions.

Figure Ij-2.

The

format

The

six groups

Double

Operand -

(such as

add,
is

called

the

the
source

different

divided

of each group

)

‘

six groups

shown in

are:

Operations which imply two
that

called

the

move,

and compare)

specify two

addresses.

operands

are handled
The

first

source

operand; the second is
destination operand. Bit assignments in
and destination address fields may specify

address modes

and

Double-operand instructions

{

into

of instructions

subtract,

by instructions
operand

set

different registers.

are

listed in Table l-3.

Single Operand - Operations which require only one

operand (such as clear, increment, test) are handled
by instructions that specify only a destination

address
and

(operand).

destination

The operation code,

address

are

address mode,

specified by

the

instruction.

Single-operand instructions are listed in Table -l .
c.

use

or Destination
of

the

general

Instructions

processor

in this

registers

simple accumulators and the resulted is stored in the
selected register. Information can be used as either
a source or destination operand. For example,
exclusive OR of the selected register and the

operand

can be
source

stored in
or

the

destination address.

destination

listed in Table l-5.

the

destination

instructions

are

Program Control

(Branch) -~
These instructions permit
program by branching to new locations
in the program dependent on conditions tested by the
program. The instructions cause the program to branch
to a location specified by the sum of an offset value
control

the

(multiplied by 2)

provided

the

conditional

the

and the current contents

branch

and

the

PS word.

either

Program control

instructions

Miscellaneous

These

and RESET

are

listed in Table L-6.

instructions

well

instructions

interrupt

and

such

RTI,

EMT,

Miscellansous

RTT,

instructions

Condition Code Operators set or clear individual

processor status
these

bits

Condition

may be

code

of the PC

unconditionals or is
conditions are met after testing

(PS)
set

word.
or

operators

are

include

HALT,

and TRAP,.

listed

in Table L-7.,

These instructions
condition codes in

are

together.

listed in

used

the

Selected combinations

cleared

WAIT,

trap handling

Table -8,

DOUBLE OPERAND

OP CODE

|
12

Src

]

dst

]

SINGLE

]

‘

REG
i

]

Src/dst
|
]

OPERAND

OP CODE

]

dst

;

MISCELLANEOQUS

[

]

REG

]

BRANCH (PROGRAM CONTROL)

]

OP CODE

]

)

OFFSET

‘

]

CONDITION

CODE OPERATORS

]

]
11-1069

Instruction Formats

TM,

Figure 4-2

4-9

Table

4-3

Double Operand Instructions
Mnemonic

Description

ISP Notation

Instruction
and Op Code

MOV
Move
(SrctoDst) |

Move source to intermediate register, r.

< 8’ next
N+« (19
if (1(15:0)=0) then (Z < lelse Z + 0),

Set N if negative.
Set Zif 0.

Clear V.

—

01SSDD

V<0
Der

Transmit resuit to destination.

MOVB

r < Sb’; next

Move source to intermediate register, 1.

Move Byte
(Stc to Dst)
11SSDD

N« (D;
if (r (7:0) = 0) then (Z < 1 else Z « 0);
V+0;
Db’ «r

Set N if negative.
Set Zif 0.
Clear V.
Transmit result to destination.

CMP

r{16:0) < S - D’; next

Source and destination operands are compared, but unaffected.

{(Src to Dst)
02SSDD

N« {195,
if (r (15:0)=0) then (Z « 1 else Z « 0);

Compare

Set N if r is negative.
SetZifris0.

if (S5 =~D(U)&(S(15) XOR1(15) then | Set Vif operands have opposite signs and the sign of the source

(V< 1lelse
C+rll&

is the same as the result, 1.
bit is carry.
Set C if 17th

V<0)

CMPB

1 {8:0) « Sb’ - Db’; next

Compare Byte|

N« (7,

12SSDD

Only condition codes are affected, as follows:

Same as CMP, except operands are bytes.

if (£ (7:0) = 0) then (Z < 1 else Z < 0);
if (Sb (7 = ~ Db () & (Sb (7 XOR r (7) then
(V+lelseV<0);
C«r1(®

Logical AND of source and destination operands.

BIT

1< D" &S’ next

03SSDD

if (£ (15:0) = 0) then (Z « 1 else Z < 0);

Bit Test

N <7 (15);

Set N if negative.
Set Zif

‘

V<0

No overflow.

BITB

r < Db’ & Sb’; mext

Same as BIT, except byte

Bit Test,

N < (M,

;

Byte

if (7 ¢7:0) = 0) then (Z + 1 else Z+ 0};

138SDD

V<0

BIE

1+ D &~8;next

AND destination operand with complemented source operand.

V<0

in
V and put result
Clear

N+«r{15;
if (r (15:0)=0) then (Z « 1 else Z + 0);

Set N if negative.
Set Zif G.

Dey

destination address.

BICB

r < Db’ & ~ Sb’; next

Same as BIC, except byte.

Bit Clear,

N+ (7

Bit Clear
04SSDD

Byte

if (r (7:0) = 0) then (Z « 1 else Z <+ 0);

14SSDD

V «0;

Db<«r

'
(continued on next page

=10

Table 4-%
(continued)

ISP Notation
i

BIS

r+D’OR S’; next

Bit Set

Inclusive OR of source operand and destination operand.

N<+r(19;

05SSDD

if (z (15:0) = 0) then (Z < ] else Z + 0);

Set N if negative.

Set
Z if Q.

V<0

Clear V.

Der

Put result in destination.

r < Db’ OR Sb’; next

Same as BIS, except byte.

BISB
Bit Set, Byte

15SSDD

| N« (?;

if (r (7:00 = 0) then (Z < 1 else Z « 0);
V0

Db +r

ADD

r{16:0) « 8 + D’; next

Add

Add source and destination to provide 17-bit sum.

N<+«7(19);

Set N if negative result.

if (r {15:00 = Q) then (Z + 1 else Z « Q);

Set
Z if 0.

06SSDD

if (S (15) equivD (1) & (S (15) XOR r (15)

SUB

Subtract

16SSDD

Set V if both operands were same sign and the result is of

then (V + 1 else V « 0);

opposite sign.

C+r

&),

Set C if carry.

D+

(15:00

Put result in destination.

1{16:0) « D"~ §"; next

Subtract source operand from destination operand.

N<«r{(1%;

if (r (15:0) = 0) then (Z + 1 else Z + 0);

Set N if negative results.

Set Z if 0.

if (D (15 XOR §(15) & (D (15) XOR ¢ (15))

Set V if operands had different signs and result is opposite

then (V « 1 else V < 0);

sign from destination.

C+r (16

Set C if a carry.

D+ z{15:0

Put result in destination.

=11

Table

-l

Single Operand Instructions
Mnemonic

Description .

ISP Notation

Instruction
and Op Code

Clear destination, N, V,and C; set Z.

D+ 0;

CLR
Clear dst

N<«Q;

0050DD

Z+1;
V<0

C<0

Clear destination byte.

Db’ < 0;

CLRB

Clear Byte dst | N+ 0;

Z<+1;

1050DD

VY «0;
C«0

Complement destination.
Set N if negative.
Set Zif 0.
Clear V.

r <~ D’; next
COM
Complement | N «r({15);
if (r(15:00=0) then Z < 1 else Z «< Q);
dst
V<0
0051DD

Set C.
Put result in destination.

C<l;
Der

COMB

Complemeni

1+~ Db’; next

N« (D;

Same as COM, except byte.

if (1 7:00= Q) then (Z « 1 else Z < 0);

Byte dst

\AtH

1051DD

C«1;

Db<r

g+ D+ 1;next
INC
Increment dst | N+ r{15);
if (r {15:0) = 0) then (Z « 1 else Z < 0);
0052DD

Result is sum of D plus 1.
Set N if negative.
Set Z if 0.

if (r {15:0) = 100000, then (V <+ lelse V<0); | Set Vif result equals 100000, (dst was 077777g)Dex

Put result in destination.

INCB

r < Db’ + 1; next

Same as INC, except byte.

Increment

N« (7

if (r (7:0) = Q) then (Z + 1 else Z + 0);

Byte dst

if (r (7:0)= 200g) then (V < 1 else V «0);

1052DD

Set V if result equals 200 (dst byte was 177g)-

Dber

DEC

r < D’-1; next

dst

if (7 {15:0) = 0) then (Z < 1 else Z + 0);

N+« (IS,

Decrement

if (£ (15:00=777775) then (V < 1 else V

0053DD
DECB
Decrement
Byte dst

1053DD

Result is destination operand minus 1. -

Set N if negative.

Set Z if 0.

0); | Set V if result equals 77777 (dst was 100000

D<r

Put resuit in destination.

r <+ Db’ -1;next

Same as DEC, except byte.

N« (D;
if (1 (7:00=0) then (Z « J else Z+ Q);

if (1 (7:00=1775) then (V< I else ¥ « 0);

’

Set V if result is 1775 (dst byte was 000g).

Db<r

(continued on next page)

=12

Table

L=l

{(continued)

Beseription

r «-D’; next

Negate D by 2’s complement.

Negate dst

Ne«r(15);

Set N if negative result.

0054DD

if (r (15:00=0) then (Z + 1 else Z < 0);

Set Zif Q.

if (r (15:0) = 100000;) then (V < 1 else V « 0); | Set V if destination operand was 100000;.

NEGB

if (1 (15:00 =0) then (C+Oelse C « 1);

Clear C if result is 0, otherwise set C.

De+r

Put result in destination.

r +-Db’; next

Negate Byte

Same as NEG, except byte.

| N« r(7);

1054DD

if (r {7:0) = Q) then (Z « 1 else Z « Q);
if (¢ (7:00 = 2005) then (V « 1 else V < 0);
f (@ (7:0=0)
then (C + Oelse C+ 1);
Dbe+r

ADC

r+<D’+C;next

AddCarry

00SSDD

)

Add the C bit to the destination.

N«r(19);

Set N if negative.

if (r (15:0)=0) then (Z « 1 else Z+ 0);

Set Zif 0.

if (r(15:0)= 100000g) & (C = 1) then (V+ 1

Set V if destination was 077777 and C was 1.

else V <« 0); next

if(5:0=0)&(C=1) then (C « | else

Set C if destination was 177777 and C was 1.

C«0);
De+y

ADCB

1< Db’ +C; next

Add Carry

N«

Same as ADC, except byte.

(D;

Byte

if (r (7:0) = 0) then (Z « 1 else Z <+ Q);

1055DD

if (1 ¢7:0)=200g)
& (C = 1) then (V « ] else

VY + 0); next

if (t (7:00=0)
& (C = 1) then (C+1 else C+0);
Dber

SBC

<D’ -C; next

Subtract C bit from contents of destination

Subtract

N+« (15;

Set N if negative.

Carry

if (r {15:0)=0) then (Z « 1 else
Z < 0);

Set
Z if 0.

00546DD

if (r (15:0) = 100000,
) then (V « 1 else V< 0); | Set V if result is 100000,
f@5:00 =0)&(C=1)then (C <«

Qelse

Clear Cif resultisOand C=1. "

C«1)

SBCB

Der.

Put result in destination.

1< Db’ -C;next

Same as SBC, except byte.

Subtract

N« (D

Carry Byte

if (£ (7:0) = 0) then (Z « 1 else Z < Q);

1056DD

if (£ ¢7:0) = 200,) then (V « 1 else V < 0);

if (1 ¢7:0)=
0) & (C = 1) then (C « O else C « 1);.
Dber

(continued on next page)

le13

Table L-l

{(continued)
Single Operand Instructions
Mnemonic

TST

Description
'

ISP Notation

Instruction
and Op Code

Sets N and Z condition codes according to contents of

r < D’-0; next

destination address.

Test
00sS7DD

N<«r{15);
if (r (15:0) = Q) then (Z < 1 else Z < 0);

V<0

’

C+«0

Same as TST, except byte.

TSTB

r < Db’ -0; next

Test Byte

N«

1057DD

if (1 (7:0)=0) then (Z «+ 1 else Z « 0);

(D;

V<0

C<«0

ROR

Rotate Right
0060DD

r{16:0) « D’ () cat C cat D" {15:1); next
N« (15);

CcatD(15:0) < r (16:0); next

Put 17-bit result into C bit and destination.

if (r(15:0)=0) then(Z < 1 else Z < Q);

if (NXORC) then(V <« lelse V< 0)
RORE

17-bit intermediate result is C and contents of destination

rotated right one place.
Set N if high order bit is set.

1 {8:0) « Db’ (O cat C cat Db’ {(7:1); next

Rotate Right | N« (7);

Set Z if result is 0.

Load V with exclusive-OR of N and C (after rotation is

complete).

Same as ROR, except byte.

Byte

if (r (7:0) = 0) then (Z « 1 else Z « 0);

1060DD

C cat Db « r (8:0); next

(V « | else V< §)
if (N XOR C) then

ROL
Rotate Left
0061DD

17-bit result is C and contents of destination rotated left one
bit.

r (16:0) « D’ {15:0) cat C; next
N« (13);
Z < 0);
then (Z+ 1 else
if (r 15:0Y=0)
C cat D «r {16:0); next

Set N if result is negative.
is 0.
| Set Z if result
Put result into C and D. Bit 15 into C bit and previous C bit
‘

into bit 0.

|
ROLB

if (N XOR C) then (V « 1 else V « 0)

Load V with exclusive-OR of N and C after rotation is
complete.

1 (8:0) < Db’ (7:0) cat C; next

Same as ROL, except byte.

Rotate Left

N+ (P;

Byte

= 0) then (Z« 1 else Z < 0);
| if (1 ¢7:0)

1661DD

C cat Db <1 (8:0); next

ASR

1 < D’/2; next

Contents of destination shifted right one place (+ 2).

N+r(15;
if (r (15:0) = 0 then (Z « 1 else Z +0); next

Set N if result negative.
Set Z if result 0.
Load V with exclusive-OR of N and C after shift is complete.

Put result into destination.

Arithmetic

Shift Right
0062DD

if (N XOR C) then (V « 1 else V < 0)

Least-significant bit loaded into C.

C<D(®;

V + 0);
(V « 1 else
if (N XOR C) then

{continued on next page)

Table L=l
(continued)
nd Instructions

ISP Notation

Description
&

ASRB
Arithmetic

r < Db’/2; next

Same as ASR except byte.

| C < Db (O,

Shift Right

N«

Byte
1062DD

if (r (7:0) = 0) then (Z « 1 else Z « 0); next
if (N XOR C) then(V
+ lelse V<+0Q);

Db+r

ASL

r <D’ (15) cat D’ {13:0) cat 0; next

Shifts contents of destination left one place, but sign bit

Arithmetic

remains in most significant place.

Shift Left

C « D(14); next

Bit 14 loaded into C.

0063DD

MN+r{l®);

Set N if result negative.

if (z (15:0)
= 0) then (Z « 1 else Z + Q0); next

Set Z if result 0.

if (N XOR C) then (V « 1 else V+Q);

Load V with exclusive-OR of N and C after shift completed.

Der

Put result in destination.

ASLB

r + Db’ (7) cat Db’ {(5:0) cat 0; next

Arithmetic

C + Db (6); next

Shift Left

N«

Byte

if (£ (7:0) = 0) then (Z « 1 else Z « 0); next

1063DD

Same as ASL, except byte.-

if (N XOR C) then (V« 1else V<0);

SP « SP + (2 X df (5:0)); next

Mark

0064nn

(D)

Db <1
MARK

Adjusts stack pointer by. the number of words indicated in the
low 6 bits of the instruction {2 X nn locations).

PC « R[5];next

Puts old PC (RS) into PC.

R[5] <« Mw [SP];

Contents of old RS poppe into RS.

SP-SP+2

SXT

Sign Extend

(N=1)then (r {(15:00« -1 else r (15:0)
< 0); | If the N bit is set, then - 1 is placed in the destinstion ¢
Otherwise, O is placed in the destination operand.

destination

if (£{15:0)=0) then (Z « 1 else Z < Q);

Set Z if result is 0.

C067DD

D ey

Table ;-5
Register

Ins@uction

Source

XOR

074RDD

Instructions

ISP Notation

and Op Code

Exclusive-OR

Destination

Description
4

r < Risr] XOR D’; next

The exclusive-OR of the register and the destination operand

if (r = 0) then (Z « 1 else Z + 0);

Set Z if result is 0.

N+« 115,

Set N if result is negative.

V<0,

Clear V; no overflow possible.

is stored in the destination address.

Risr] «r

SOB

r < Rfsr] -1; next

Subtract

Rist] < 1;

One and

if (r # 0) then (PC < PC-2 X 4f (5:0))

Decrement register by 1. If result is not equal to 0, branch.
Subtract 2 X 6-bit offset from PC to get new PC-

Branch
077R offset

u-lé‘

Table li-6
s

Control Instructions

ISP Notation
PC « PC + sign-extend (instr {7:0) X 2)

BR
Branch

Description

Always branch.
-1 PC changed as follows:

Eight least-significant bits of instruction are multiplied times 2

Unconditional |

and added to PC with sign extended.

0004 loc

if (Z = 0) then (PC-+ PC + sign-extend

BNE

Branch if Z is 0.

(instr (7:0) X 2))

Branch

Not Equal
0010 loc

BEQ

if (Z = 1) then (PC « PC + sign-extend

Branch on

(instr {7:0) X 2))

Branch if Z is 1.

Equal

0014 loc

BGE

Branchif

if (N equiv V) then (PC « PC + sign-extend

Branch if N is equivalent to V.

if (N XOR V) then (PC « PC + sign-extend

Branch if exclusive-OR of N and V equal 1.

(instr (7:0) X 2))

" Greater than

or Equal (zero)
0020 loc

BLT

Branch on
Less Than

(instr (7:0) X 2))
~

0024 loc

BGT
Branch on

if (~Z & (N equiv V)) then (PC « PC + sign-

Branch if Z not 0 and N equals V.

if (Z OR (N XOR V)) then (PC « PC + sign-

Branch if Z equals 1 or if exclusive-OR of N and V equals 1.

extend (instr (7:0) X 2))

“Greater Than

0030 loc

BLE

Branch on

Less Than

extend (instr (7:0) X 2))

or Equal (zero)
0034 loc

BPL
Branch on

if (N = 0) then (PC « PC + sign-éxtend

Branch if Nis 0.

if (N = 1) then (PC « PC + sign-extend

Branch if Nis 1.

(imstr ¢7:0) X 2))

Plus

1600 loc

~ BMi
Branch on

(instr ¢7:0) X 2))

1004 loc

BHI
Branch on

if ~(C OR Z) then (PC « PC + sign-extend

Branch if C and Z are 0.

(instr (7:0) X 2))

Higher
10101loc

(continued on next page)

=17

Table li-6
(continued)
Program Control Instructions
Mnemonic

Description

ISP Notation

Instruction
and Op Code

BLOS

if (C OR Z) then (PC « PC + sign-extend

Branch on
Lower or

(instr (7:0) X 2))
o

Branchif

CorZis 1.
S

Same
1014 loc

BVC

if (V = 0) then (PC « PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if V is 0.

Overflow
Clear

BVS

if (V = 1) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if V is 1.

Overflow Set
1024 loc

BHIS

if (C = 0) then (PC « PC + sign-extend

Branch on

(instr (7:00 X 2))

Branch if C is O.

Higher or

Same

1030 Ioc

BLO

if (C = 1) then (PC « PC + sign-extend

Branch on

(instr 7:0) X 2})

Branch if Cis 1.

Lower

1034 loc

JSR

SP « SP~2; next

Jump to

Mw [SP] « Rlsr];

Push contents of R onto stack.
,

Risr] < PC

Store curréent PC in R.

004RDD

PC « D address

Load subroutine address into PC.

RTS

PC < R[dr];

Load contents of R into PC.

Subroutine

SP<«SP+2

Subroutine

Return from | R{dr] « Mw [SP];

Pop stack pointer into R.

00020R

]

Table -7
Miscellaneous
Mnemonic
Instruction

Instructions
:

ISP Notation

and Op Code
HALT

Off < true

Processor halts with console in control. No activities or

Halt

instructions can be executed until a console actions restarts

000000

WAIT

the processor.

Wait + true

Wait

Description

Processor relinquishes bus and waits for an external interrupt.

000001
I0T

SP « SP~-2; next

I/O Trap

Mw [SP] < PS;

000004

Push PS onto Stack.

SP < SP -2; next

Push PC onto stack.

Mw [SP] « PC;

PC « Mw [20];

Get new PC from location 20.

PS « Mw [22]

Get new PS from location 22.

RESET

Init < I;

Reset

Send INIT on Unibus for 20 ms.

Delay (20 milliseconds); next

External Bus | Init <0
000005

SPL

PS{(7:5) < df Q:0

- Set Priority

Load three least significant bits, N, into PS.

‘

Level
00023N
RTI

PC < Mw [SP];

Return from

SP + SP + 2; next

Interrupt

PS < Mw [SP};

000002

SP+SP+2

~ (RTI permits trace trap.)

PC « Mw [SP];

Pop PC off stack.

RIT

Pop PC off stack.

Pop PS off stack.

Return from

| SP < SP + 2; next )

Interrupt

PS < Mw [SP];

Pop PS off stack.

000006

SP«SP+2

(RTT inhibits trace trap.)

EMT

SP « SP -2; next

Push PS onto stack.

Emulator Trap|

Mw [SP] « PS;

104 Code
(104000 —

104377)

- Push PC onto stack.

Mw [SP] « PC;

PC «~ Mw [30];
- PS + Mw [32}

. TRAP

Trap

SP < SP -2; next

SP
« SP -2; next

Mw [SP] < PS

104 Code

SP + SP -2; next

(104400 —

Mw [SP] « PC;

104777)

PC < Mw [34];

PS « Mw [36]

Get new PC and PS from locations 30 and 32.
‘
Push PS onto stack.

Push PC onto stack.

- Get new PC and PS from locations 34 and 36.

=19

Table -8
Condition Code Operators
Mnemonic

Instruction

ISP Notation

Description

ang Op Code

CLC

if (instr (4)=0 & instr{0) = 1) then C <0

Clear C

CLV

When bit 4 of the instruction is 0 bits 3, 2, 1, and O clear
corresponding bits in PS.

if (instr @ =0& instr (1) = 1) thenV « 0

Clear V

000242

CLZ

if (instr

)=0& instr (¥ =1) thenZ <0

if (instr

=0& instr 3 =1) thenN+Q

Clear Z
000244

CLN
Clear N

000250

CCC

if (instr (4) = 0 & instr (4:0) = 17) then

Clear all

(C<0;

Condition

V «0;

Codes

Z«0;

000257

N<«Q)

SEC

if (instr ) =1 & instr O = 1) then C « 1

Set C

When bit 4 of the instruction is 1, bits 3, 2, 1, and O set corresponding bits in PS.

000261

SEV

if (instr @ =1& instr{1) = 1) then V « |

SetV
000262

SEZ

if Ginstr @)= 1& instr D =1)thenZ <« 1

Set Z
000264

SEN

if (instr@)=1&instr 3¥=1)then N« 1

Set N

000270

SCC

- if (instr 4:0) = 37) then

Set all

(C«1;

Condition

Ve«l;

Codes

Z<«1;

000277

N<+1)

1 =20

1.2.3

Extended

Additional
options

are

Instruction

instructions
added

are

the

Set

available

basic

system.

certain processor

These

instructions

are.

KE11-E

Extended

Instruction

Set (EIS)
These
same format as double-operand
instructions and provide an increased arithmetic
capability to the basic instruction set. These
instruction
are:
s multiply (MUL), divide (DIV),

instructions

have

arithmetic shift
combined (ASHC).

the

(ASH),

and arithmetic

shift

The EIS instructiocns are listed in Table L-9,
KE1l1-F Floating

Instruction Set (FIS)
- These
instructions permit arithmetic operations in
floating-point notation. The instructions are:
FADD, FSUB, FMUL, and FDIV (floating point addition,

subtraotlon, multlplloatlon, and division).
Deseriptions of each of these instructions are

given

the

PDP-11/L0

Processor Handbook.

KT11-D Memory Management
-

The

MFPI

instruction

provided to allow inter-address space communication
when the PDP-11/110 is using the memory management
option. The MTPI instruction determines the address
of the

destination operand in the

current

address

space.

Note

that

in the

table,

instruction (MFPI)
instruction (MTPI)

the move from prev1ous

and the move to previous
are listed as MFPI/D and MTPI/D

This is because in the PDP-11/L,0, MFPI and MFPD
are executed in an identical manner as are MIPI
and MTPD.

The KT11-D instructions are listed in Table Lh-10.

=21

Table -9
Extended

Instruction

Set

(FIS)

Mnemonic

Instruction

ISP Notation

Description

and Op Code

MUL

r{31:00 < D’ X R{sr}; next

Multiply
070RSS

Multiply contents of source register and destination to form

32-bit product.

if (r (31:0) = 0) then (Z « 1 else Z + 0);

Set Z if product is 0.

N<+<r3D;

Set N if product is negative.

if (r 31:0<-28) OR (r (31:0) > 2%) then
(C+ lelse
V<0

No overflow possible; clear V.

R st} €15:0) < r 31:16); next

Store the high-order result in R.

Rsr OR 1] (15:0) < r (15:0);

Store the low-order result in succeeding register if R is even

DIV

number. Otherwise, store in R.

r1 (31:0) « R|sr] cat R[sr OR 1]}/D’; next

Divide

071RSS

Set C if product is more than 16-bit result.

C+0j;

The 32-bit dividend, R, R OR 1, is divided by source operand
D. R must be even number.

r2(15:0) «< R]sr} cat R[sr OR 1] -(r1 X D);

Determine the remainder.

next N <l {15);

Set N if quotient is negative. .

if (r1 (31:0) = 0) then (Z < 1 else Z «+ Q);

Set Z if quotient is 0.

if (D =0) then(C+« 1 else C « 0);

Set C if divide by 0 attempted.

ifri{d5=0)& (1 31:16)70)
OR

Set V if divisor is O, or if the result is too large to be stored
as a 16-bit number.

fFE1a=1)& 1 31:16#-1)
OR

(D=0)then(V<« 1 else V<« 0);

Risr} < r1415:0)

Store quotient in R.

R[srOR 1] + 12

Store remainder in R OR 1.

ASH

1 {79:0) < sign-extend (R{sr] (15:00X 21

Contents of R are shifted NN places right or left, where NN

Arithmetic

(D’ (5:0) + 32) mod 64); next

equals the six low-order bits of DD.

Shuft
072RDD

R[sr] (15:0) « r (47:32); next

NN =-32 to +31.
Store result in R.

if (R[sr] =0) then(Z « 1 else Z « 0);

Set Z if result is 0.

if (R[sr] {(15)=0) & (r(79:48)%0) OR

Set V if sign of register changed during shift.

(Rfsr] (15)=1) & (1 (79:48) #-1)) then
(V< lelse V<0,

N<R[st] 15

Set N if result is negative.

if (D{5=1)thenC <131

Load C from last bit shifted out of register.

if (D (5)=0) & (D (5:0) # 0) then
C+«rds;

if(DG:0=0)thenC+«0

ASHC

1 (95:0) « sign-extend (R{sr] cat R[sr OR 1] X | Contents of R, and R ORed with 1, form a 32-bit word (R =

Arithmetic

2 1 (D’ (5:0) + 32) mod 64); next

Shift

31:16, ROR 1 = 15:0) that is shifted right or left NN places,
specified by six low-order bits of destination operand, DD.

Combined

Rsr] < r{63:48); next

073RDD

Rsr OR 1] < r{47:32); next
if (Rfsr] cat R{st OR 1] =0) then (Z + 1 else

Store results in

Rand R OR 1.

Set Z if result is 0.

Z +0);
N+ R[sr] (15);

Set N if result is negative.

if (r 63)=0) & (1 (95:64)# 0) OR

Set V if sign bit changes during the shift.

if (r (63)# 0) & (r (95:64) #-1) then
(V< lelse V<«0)

if(D{5)=1) thenC « r (31);

Load C with high order if left shift.

if (DG)=0)&(D(5:0)# 0) then

Load C with low order if right shift.

C «r {64);
if (DG:00=0)thenC <« 0

Otherwise, clear C.

ly-22

Table

l-10

Memory Management

Instruction Set

Mnemonic

Instruction

ISP Notation

Description

and Op Code

MFPI/D

r < D’; next

Move From

SP+~§8P-2;

N« r(15;

Set N if negative.

Instruction

if (r {15:0)=0) then (Z + 1 else Z < 0);

Set Zif 0.

Space
0065DD

V<0

Get destination operand from previous [

‘

Clear V.

- Mw [SP] «r

Put operand into current address space.

-MTPI/D Move To

space.

Push stack.

Get data from current stack.

SP « SP + 2; next

N« (15

Instruction

if (r (15:0)= 0) then (Z « 1 else Z + 0);

Space

V<0,

0066DD

D «r

Pop stack.
Set N if negative.
|

SetZif
0.

Clear V.

- Move to previous | space destination.

L-23

PROCESSOR OPTIONS

The basic KD11-A processor of the
space

for

there

installing

small

six

processor

peripheral

used for a programmerfs

or Teletype interface)

PDP-11/110 System contains
options.

controller

console

device

addition,

slot

that

(such

the

usually

DECwriter

but that also can be used for a

variety of options dependent on the user's individual
requirements.

each option

The

processor

specific

listed

options

slot,

Table L4~-11

that

are

slots,

and

allocated

shown

availsble

KEl11-E Extended

Instruction

Set

(EIS)

KE11-F Floating

Instruction

Set

(FIS)

KJ11-A

KT1l-D Memory Management

KWll-L

Line

Frequency Interrupt

Clock

KML1-A

Maintenance

Small

above

Stack Limit

peripheral

options

can be

for

Figure

are:

The

Console

controller

used

in any

slot

(variable

combination

function independently with two exceptions.

The

option)

they

KE11-F(FIS)

option phsically requires the KEll-E(EIS)optiofigand software
for

the

option

include

KT11l-D
is

option

discussed

a general

reference

to more

requires

the

separately in

description,
detailed

KJ11-A option.

Each

subsequent paragraphs

specifications,

documents.

and

which

Table li-11

Location of Processor Optiéns

Option

KE11-E Extended

Section(s)

Instruction

Set

(EIS)

KEll—F Floating Instruction Set (FIS)
KJl1-A StackvLimithegisterv

KT11~D‘Memory Management

KW11~L'Line Frequency‘Clock ‘

KMllQA Maintenance Console

For maintenance of the basic
processor

For maintenance of the KT11-D
and /or EIS and FIS options

Small Peripheral Controller Slot

Slot

A-F

A-D

03
- 08
03

L-25

.3.1

KE11-E Extended Instruction Set (EIS) Option

The KE11l-E Extended Instruction Set Option is a processor
option

that

include:
and

expands

multiply

arithmetic

multiplication

the

(MUL),

shift

basic

PDP-11/L40

divide

combined

and division

(DIV),

(ASHC).

instruction

arithmetic
The

set

shift

(ASH),

option permits

signed 16-bit

numbers

and

arithmetic shifting of signed 16-bit or 32-bit numbers.
Condition

The

codes

are

set

KE11-E (EIS)option is

(M7238)

the

result

single hex

that plugs directly into slot

system unit.

of each instruction.

(six section)

AO02-F02 of the processor

The option functions as an extension of the

basic KD11-A data paths, microbranch control,
The basic

module

processor

timing

not

and control ROM.

degraded when

this

option

is used. The NPR latencj is not affected when the instructions
are

being

executed.

each instruction

There

are

All

operands

the

general

operation

Interrupts
the

are

serviced

registers
in the

are

from either

fetched

stored

the

end

standard manner.

addressable

processor

registers

the

and

general

KE11-E

core memory
the

result

option.

from

each

registers.

=26

The MUL

instruction uses

the contents
of

the

effective

address

specified by the destination register and the source registef
as 2's complement integers which are mult:’fplied° The result is

stored in the,sofirce register and; if even, the low-order
result

the

succeeding

the

source

address 1s odd, gnly the low-order product is stored. The MUL
instruction multiplies

full

16-bit numbers

for

a 32-bit product.

The DIV instruction permitsva’32—bit dividend to be divided

by a 16-bit divisor to provide a 16-bit qfiotient and a
16-bit remainder.

The

sign of the

remainder is

always

the

same as the sign of the dividend unless the femainder is zero.
Overflow is
express

the

the quotient.

overflow

status

indicated

(EPS)

if more

than

case,

the

instruction is

set,

the

expansion processor

this

condition code

word is

16 bits

are

required

loaded into the processor PS

to
aborted,

and

the program branches to a service routine. If the source
register

zero,

indicating

divide

by O,

an overflow

indicated,'

L-27

When

the

ASH
is

instruction
shifted

right

specified by a count.
complement

the

contents

left

the

number

This

number which

used,

shift

the

count

least

the

selected

places

6-bit,

significant

2's
bits

the destination operand. If the count is positive, the number

shifted left;

if it

negative,

the

number

shifted

right. This allows for shifts from 31 positions left to 32
positions

right

change

the

(+31

to -32).

A count

’

of zero casuses no

number.

When the ASHC instruction is used, the contents of a register

(address R) and ‘the contents of another register (address of the
first register ORed with one, R+l) are treated as a single 32-bit
word, Register R+l represents bits 0-15, register R represents

bits 16-31. This 32=-bit word is shifted right or left the

number of places specified by a count, This shift count is the
same as that described for the.ASH instruction and permits shifts

(R) is an odd number,
from +31 to =32, If the selected register
then R and R+1 are the same., In this case, a shift becomes a

rotate and the 16-bit word is rotated the number of counts
specified by the shift count (up to 16 shifts}).

Speéifications for the KE11-E option are listed in Table L -12
at the end of
option is

this paragraph. A detailed description of this

given in

the

KEl1l

Instruction

Set

Options Manual,

DEC-11-HKEFA-A-D,

=28

Table ) -12

KE11-E (EIS) Specifications

Instructions

Multiply

Divide

(MUL)

(DIV)

Arithmetic Shift
Arithmetic
Operations

(approximate)

shifting

signed

or 32-bit numbers

None

option.

Operands

core

fetched from

general

processor

registers.

MUL

9.5 us

DIV

10.5 us

ASH

3.l us plus address calculation
time plus 300 ns times absolute

value

ASHC

Size

(ASHC)

and division
signed 16-bit numbers.

16-bit

Timing

Combined

Multiplication

Arithmetic

Registers

(ASH)

Shift

Single

of shift

count

3.8 us

plus address calculation
time plus 300 ns times absolute
value of shift count

hex module

(M7238)

=29

1 .3.2
The

KE11-F Floating Instruction Set (FIS) Option

KE11-F Floating

option

that

arithmetic

prime

Instruction

enables

Option

the KD11-A processor

operations

advantage

Set

using

this

processor

to perform

floating-point

option is

increased

arithmetic.

The

speed without

the necessity of writing complex floating—point software
routines.

The

KE11-F performs

single-precision

operations.

The KE11-F option cannot be used unless the KE11-E (EIS)
option has been installed in the system.
The

KE11-F (FIS)option

plugs directly into

single

quad module

slot AOl1-DO1 of

the

(M7239)

processor

that

system unit,

If a BR request is issued before thé instruction is within
approximately 8 us
instruction
points

the

instruction

aborted.
aborted

the

The NPR latency

are

being

next
is

executed.

instruction

of completion,

the

this

the

event,

floating-point

instruction

not

affected

Interrupts

flcating-point

are

program

instruction,

to be
when

the

performed

making

floating-point

serviced

counter

the

(PC)

the

program.

instructions

end

each

standard manner.

L4-30

The

FIS

point

option

addition

fleating-point

division

mantissa.

multiplicaticn

representation

binary point

are

special

instructions:

floating-point

The mantissa is

significant

(FADD),

four

(FMUL),

subtraction
and

floating-~

(FSUB),

floating-point

(FDIV).

Floating-point

the

provides

bit.

eliminated

a binary number

a fraction inymagnitude

positioned between

the

normalized,

the mantissa

from

consists

the

binary

sign bit

format with
and

all

representation;

the

most

leading

the most

significant bit is thus a 1. Leading Os are removed by
shifting the mantissa left; however,
mantissa must be
To maintain
represents

obtain

For

FADD

the
the

the

followed by a decrement of the
true

value

power

value

or FSUB

to be

number.
the

The

exponent

mantissa

value

multiplied

aligned

the mantissa with the

smaller

used.

operations,

If they are not,

exponent

shifted

right

the

by which

(or equal).
is

each left shift of the

the

until

exponents

they

are.

must

Each

right

shift

is accompanied by incrementation of the exponent value,VOnce
the

exponents

subtracted.
the

binary

are

The
peoint

aligned

exponent
is

toc

(equal),

value
moved

the

mantissa

indicates
in

order

the
tc

number
obtain

added

of places
the

actual

representation of ‘the number.

L-31

For FMUL

instructions,

exponents

are

added.

divided

The

KE11l-F Floating-Point

are

the

mantissas

are

multiplied

For FDIV instructions,

are

excess

and

the

exponents

2008 notation.

are

the

the mantissas

subtracted.

option

stores

the

Therefore,

values

from -128

represented by the

and

binary equivalent

exponent

of 0

to +127

to 255

(octal 0-377). Mantissas are

represented in sign magnitude form.

The

the

floating-point

operations

always

increasing

absolute

binery radix

the

exponent

regardless
generates

the

end

option is

of the
a

clean

Specifications
at

point

equal

given

sign bit
O

for the
this

value

this

result

the

away

from

zero,

number.

number

assumed

value.

The

hardware

instance.

KE1l-F

KE1ll

the

The

rounded

or fraction

paragraph.

the

left.

option are

listed

description

detailed

Instruction Set

in Table }j-13

Options

this

Manual,

DEC-11-HEKEFA~A-D,

L-32

Table L-13

KE11-F (FIS)Specifications

Prerequisite

Instructions

KE11-E Extended

Multiply

" Divide

Instruction

Set

Option

(MUL)

(DIV)

Arithmetic

Shift

(ASH)
Arithmetic Shift Combined (ASHC)
Floating-point Addition (FADD)
Floating-point Subtraction (FSUB)

Floating-point Mulitply (FMUL)
Floating-point Divide (FDIV)
Operations

Multiplication

and

division

signed 16-bit numbers.
Arithmetic

shifting
or 32-bit numbers.

Single-precision
subtraction,

signed 16-bit

floating-point

multiplication,

of 16-bit numbers.
Registers
-

and

addition,
division

None

option.

Operands

fetched from

core

general

processor

registers

(stack ordered)
Size

Single

quad

module

(M7239)

L-33

1.3.3

The

KJ11-A Stack Limit Register Option

KD11-A processor

operations.

Because

capable

the

number

of
of

performing
locations

hardware

occupied

stack

stack is unpredictable, some form of protéction must be
provided

prevent

conftaining

other

protection

Limit

the

from expanding

information.

provided

stack

Option

the

fixed

provides

basic

into

locations

machine,

boundary.

The

s programmable

this

KJ11-A

Stack

boundary.

The KJ11-A consists of a single addressable reéister,
accessible

change

used

both

the

console

stack limit

(yellow zone violation)
indication'O
s

the

8-bit register

processor.

a high-order byte

(777775)

During

the

signifying
occcur

the

below

pointer related
the

address

the

lower

the

stack limit

1limit

processor,

is
the

provide

(red zone
stack

that can be

this

bus

Ihe

the

and

and error

(high byte)

operation,

and

liwmit

full

word

stack

(stack

operations

(DATO,

DATOB,

less

error

than

address

violations

subsequent

(77777L).

loaded with

addressed either as

During

operation

warning

violation)

1limit).

bus

that

stack

and DATIP),
the

condition

contents

exists.

L=3l

If the difference is less than or equalkto 16 words, a yellow
zone violation occurs. The operations that céused the yellow
zone

vioclation

are

completed

and

then

bus

error

trap

occurs.

This error trap, which itself uses the stack, executes without
causing

the

space

stack

additional

and

between
greater

the

violation.

the
than

operation

repositioned

bus

address

16 words,

and

then

the
a

red

causing

the

error

a bus

error

trap

and

stack

limit

zone

violation

aborted.

occurs;

The

that

is,

the old PS and PC are pushed into locations 2 and 0 and the
new PC and PS are taken from locations i, and 6. A red zone
violation
are

odd

stack

error

fatal
or

stack

error.

non-existent

conditions

exist

Other

stack.

the

fatal

stack

Note

that

basic

KD1l-

errors

these

two

processor;

however; in this case the stack limit is fixed at memory
location

LOOg.

The

option utilizes

this uOOBboundary also,

The KJ11-A Stack LimitVRegister Option is a single-height
module

that

plugs

Specifications
at

the

opticn

end
1s

into

for
this

presented

the

slot

EO03

KJ11-A

paragrsph.
in

the

the processor.

option
A

are

detailed

XKDl11-A

listed

Table

description

Processor Manual,

L -1l
tnis

DEC-11-HKDAA-A-D,

L-35

Table L-1l
KJ11-A

Specifications

8-bit stack limit register (bits 15-08)
addressable

consocle

processor,but

not by

any bus

device

777774
777775

(word addressing)
(byte addressing)

Stack Limit

programmable; if register is all Os,

;

’

then:

000

310

Yellow Zone
Violation

Zone

Violation

red

zone

yellow zone

occurs if the stack operation's address
less than the stack limit address by

16 words

Red

337

- 377

or less.

completed

and

occurs

the

less

than

The

then

stack

the

operation is
TRAP

igs

executed.

operation's

stack limit

than 16 words.

The

address

operation is

aborted (fatal stack error), a stack
vector exists
at address lj, and a bus

error TRAP

occurs.

are

pushed

into

new

I and

PDP-11/40

The

Stack Limit

limit
to

Size

one

and

The

old

locations

are

taken

and

0O;

the

from locations

PDP-11/L,0 System has
the

377.

Therefore,

initialized

state

a fixed stack
it

equivalent

the

KJ11l-A,

single-height module

L-36

l.3.4,

The

KT1l-D Memory Management

KT11-D Memory Management

option

that

provides

the

Option

capability

expand

PDP~-11/110

the

processor

32K-word

addressing of the KD11-A processor to 128K words and to
enhance

the use

time-sharing
operating

with

The

of multi-user,

environment

modes:

or without

made

option

Expands

These

modes

and protection.

basic

32-K word

four

two

can

Mode

expanded KD11-A processor

basically performs

the

systems,

created by providing

and user.

relocation

by using

KT11-D

kernel

multi-program

operate

selection

status

word.

functions:

address

capability

to 128K words.

Provides

address

space

with memory

and protection for multi-user

relocation

timesharing

systems.,

Implements
kernel

the

separate

and user modes

Provides

address

in multi-user,

for

the

operation.

memory management

of memory

spaces

information

multi-program

for use

systems.

L=-37

The

standard 16-bit word length of the

the memory

address

capability

upper LK of address
register

and

space

external

the 16-bit virtual

memory address

Because

the

KT1l-D

addition,

the

reserved for internal

addresses.

The

KT11-D

converts

generated by the processor to an

address,

option

space.

loaded

re-linked;

thereby increasing the usable

capability from 28K to 12K words.

address

program is
be

device

relocates

KD11-A processor may be

virtual

32K words.

is always

address

18-bit physical bus

KD11-A processor limits

This

all

addresses

automatically,

considered

to be

means

no matter where

into

physical

always

appears

that

memory,
to

operating

does

the

not

sasme

have

virtual

location in memory.

a multi-programmed,

prevented

from modifying

The KT11-D option

upon which the
sets

of eight

timeshared

implements

timeshared
32-bit

actually a pair

destroying

the

user

programs

the

operating

kernel/user modes

system is

Active

16-bit

system,

Page

based.

The

Registers

registers:

system,

operation

option uses

(APR).

Page

must

Address

APR

two

(PAR), and a Page Descriptor Register (PDR). These registers
are

always

needed

One

used

describe

PAR/PDR set

pair

and

locate

provided

contain

the

for

all

the

currently

each mode

and user). Logic within the KT11-D analyzes

information

active

memory pages.

operation

(kernel

every memory

L-38

reference

mode

enable

program,

assigned

for

the

correct

example,

kernel

PAR/PDR

cannot

set.

operate

Thus,

the

a user

space

programs.

In a multi-program, multi-user enviromment, memory spéce

mustvbe used in the most efficient method possible in order
to

accomodate

The

KT11-D

associated
memory

many users

option maintains
page

has

management

bits

ever been

system

possible

can

that

written

with minimum

indicate
into.

interrogate

whether

The

each

delay.

the

software

PDR

determine

how that page had been used. Thisvinformation enables the
software
memory

never

system

space.

been

For

evaluate
example,

altered,

the

necessary,

overlay

that

user.

current

the
if

overall

active

use

memory

memory management
page

active

with

page

new

has

rage

has

system might,

program

been

available

requested

written

into,

the

memory management operating system needs to be informed so
that

the

storage

modified

program

before

the

page

Specifications

for

the

listed

Table

description

Management

L-15
this

Option

can

rewritten

into

overlaid.

KT11-D Memory Management
the

option

Manual,

secondary

end
is

this

given

Option

paragraph.
the

are

detailed

KT11-D Memory

DEC-11-HKTDA-A-D.

L-39

Table

j-15

KT11-D Specifications

Memory Expansion

Interface

Expands

PDP-11/40 memory address
capability up to 12K words.

Address
with

Timing

line outputs
PDP-11 Unibus

Timing

Delay

Adds
when

derived

Available

Provides

Length

ns to every memory reference
installed.

Kernel

Page

from KD11-A processor

150

Operating Mepdes
Pages

compatible

and user
8 LjK-word pages

for

each mode

A page can vary in length from one
32-word block up to 128 32-word blocks.

Maximum page
Program Capacity

Eight

Size

Single

length is

[j096-word pages
32K-word programs.

hex-size module

11096 words.
accomodate

(M7236)

L =L0

4L.3.5

KW1l1-L Line Frequency Clock

The KW11-L Line Frequency Clock is a PDP-11/40 Drocessof
option

This

that

provides

option

generates

processor.

The

frequency,

either

period,

rate

referencing

interrupt

derived

a repetitive

therefore,

freouency

a method

Hz.

dependent

The

real

request
from

accuracy

the

intervals.

the

accuracy

the

line

the

clock

this

source.

The KW1ll-L Line Freqguency Clock can be Opefated in either
an

interrupt

npn—interrupt

mode.

When

the

interrupt

mdde, the clock option interrupts the processor each time
it

receives

pulse

from the

non-interrupt

mode,

the

line

clock

freaguency

option

source,

functions

the

program

switch that the processor cén examine or ignore. Mode
selection

made

the

progran.

Specifications’for the KWll-L Lihe Frequency Clock Option
are
listed

Table

description

this

the

option

end
is

this

given

paragraph.
the

KWll-L

A detailed
Line

Time

DEC-11-HKWB-D,

,,Q

Clock Manual,

L -16

Tahle
KW1ll-1,

4-16

Specifications

2-bit

status

bit
hit

06
N7

reagister
interrunt enable
interrupt monitor

777546

Address

100

Vector

Address
Mode

Control

hit
bit

set clear

interrunt mode
- non-interrupt mode

bit 07 can be used to serve as a partial

Monitor

check on

Function

Interrupt

Rate

same

Priority

Level

RR6

Size

06
06

the

origin of

the

line

freaguencv:

Single-height module (M787)
in ¥D1ll1-A processor slot F3

interrunt vector

that mounts

L=L.2

L.3.6 KM11-A Maintenace Console Option
The

KM11=A

Maintenance

maintenance

indicator
control

The

module)

lights

functions

processor

overlays

tested.

The

when

testing

solt

EO1

module

Use

the

overlays,

the

during

the

testing

DEC=11=HKDAA=A=D

a detalled

description

the

Processor

KD11-A

module,

the

containing

monitor

depend
in.,

and

Different

processor

and

on which

function

being

slot

FO1

installed

or KE1l=-E,F options,

including
KD11l-A

option

description

Processor Manual,

appropriate

the

tests,

the

KT11-D

the

installed

processor

used

option

indicste

the

given

and

the

installed

maintenance

set

switches

KD11=-A

referred

maintenance

module

(Also

2-module

four

provided

when

monitored

slot

are

and

functions

Console

option manuals,

presented

Also,

Msnual,

L-L3

4.3.7

Small Peripheral Controller Slot

Processor

small
used

slot

09,

peripheral
to

install

sections

controller
the

The

standard

device,

controller,

controllers

DL1l

LCl1l

KL11

Teletype

paragraphs
Detailed

the

1.3.6

and

descriptions

either

Teletype

any

normally

PDP-11/10

System

used for any small

devices

the

LA30-S

are:

standard
DECwriter

unit.

a
as

controller
the

used

system

an earlier

which is

I/0

version

only with

when

the

device.

the

unit.

the

LC11

1.3.7,
of

used

Control

A brief description

slot

Interface

Control

Teletype

the

but may be

Line

for

DECwriter

Teletype
ASR

ASR

DECwriter

LA30-P

the

This

desired.

Asynchronous

for

installation

for system I/0

controller used

permit

option.

controller

input/output console
peripheral

C-F,

respectively,

all

related meintenance

and DL11

three

manual

are

given

this

controllers

listed

are

Table

manual.

included

1-2.

L-Lly

L.l

MEMORY

Memecries
and

OPTIONS

with

different

electrical

ranges

characteristics

speeds

can

and

various

freely mixed

physical

and

interchanged in a single PDP-11/L0 System. The basic system
mounting box
processor

and

The

processor

added by using

box may be

that

separate

expanded up

noted

may

also

can

that
be

used

different

used

core

and

56K of memory in

boxes

2LK

with

the

memory

and power

supplies.

fqur

compatible

PDP-11/L0

units

the
may

Each

increments.

PDP-11/l,0

addition

Additiocnal

describe

memories

with

box

options.

following paragraphs

types

can house

the

System.

with

provided

an H720

core memory

the

should

PDP-11/20

they

power

are

mounted

supply.

L=U5

..l

The

MM11-L Core Memory

MM11-L

current,

and

core

memory

magnetic

core

type

access

time

3-wire

planar

configuration.

that

are

both word

The

memory is

two

8-bit bytes.

(bits 00-07)

of ;00

and

The

memory

The

with

memory

provides

16-bit

always

numbered

has

are

addressed

addressed,

the

its

are

own

and

cycle

time

(8K)

coincident

organized

8192

words,

900

3D,

16-bit words

address

high

bytes

even-numbered

high byte

each word

identified as

and the high-order byte
and

access,

addressable.

into

bytes

addressable
even

random

ns.

byte

organized

read/write,

(bits

the

low-order byte

8-15).

Each byte is

location.
are

odd

locations

containing

Low

bytes

numbered.

Full

words

full

word

included.

For

only.

automatically

are

When

example,

the 8K memory has 8,192 words or 16,38l bytes; therefore, 16,38)
locations
address

byte,

The

are

assigned.

000001

000003

MM11-L

the

consists

Address

first

second

000000

high

byte,

three

modules:
logic;

containing

the

memory

control

containing

the

memory

driver

containing

the

memory

core

logic:

the

000002

Ffipst
is

low

the

byte,

second

low

etec.

G110

G231

and

hex~-type
hex-type

H21l

module
module

quad-type

module

stack.

L-L6

The

memory

device,

control

logic

acknowledges

determines

which

DATIP,

DATO,

timing

and

DATOB)

operations

(DATI,

to be

performed,

and

appropriate

read

or write

operation.

also

contains

the

amplifiers

well

includes

been

a 16-bit

the master

four basic

circuits

has

the

contrcl

memory bank

the request

device

perform
inhibit

desired

drivers

selector logic

addressed

fliov-flop

the

from

the

sets

and

determine

Unibus.

that

sense

The

stores

control

the

the
logic

contents

of a word after it is read out from destructive memory. This

same word

can then be

written back

into memory

(restored)

when

in the.DATI mode. The register is also used during DATO and
DATOB

cycles

Unibus

lines

The memory
decodes

the

addressed:;

accomodate

into

the

core

driver logic
incoming

the

incoming

data

from

the

memory.

includes:

address

switches

and

address

determine

drivers

that

selection
the

core

direct

logic

that

specifically

current

flow

through the magnetic cores to ensure the proper polarity for
the

desired

provide
magnetic

the

function;

and

the

necessary

current

X
to

and Y

current

change

the

generators

state

that

the

cores.

L-L7

The

ferrite

core memory stack

arranged

ferrite

cores

represents
core

can

either

planar

assume

a binary 1

from the

ccnfiguration.

arranged
single

core,

consists

bit

stable

128

position

appropriate

control

Information

for

core

retains

16 memory mats

Each mat

contains

6l matrix.

magnetic

or binary 0.

the

word.

state

Even

Each mat

Each

ferrite

corresponding

power

8192

removed

changed

its

state

until

the

MM1ll-I

signals.

installation

the

BAll=FC

box of the PDP=11/l10 is noted in Table 2-2,

L-L8

L.h.2

MF11-L Core Memory

The MF11-L core memory iswbasically a standard MM11-L, 8K

core memory with the éddition of a backplane. The backplane
provides

the interconnections

modules.

The

PDP-11/0

MF11-L

the

between

normal

the

core memory

memory supplied with

the

System.

Information for

installation of

the MFlle-L in

the

BAll=FC

box of the PDP-11/L0 is noted in Table 2-2.

L-l9

4.y.3

ME1l-L Core Memory

The MEl1l-L

MM11-L

a complete memory

core memory

and associated backplane

in its‘own mounting box which
supply.
up

This

system consisting

power

contains

(MF11-L)

an integral

supply and mounting box can

three MM11l-L

core memories.

effect,

housed

power

accomodate

the

MEll-L

can

be expanded up to 24K in 8K increments.

The

system mounting

inches

deep

box is

and is

19-inch cabinet.

inches

high,

inches

designed for mounting in a

Rack-mountable

slides

are

wide,

and

standard

included but

the

‘boX can be used as a stand-alone unit, if desired. In addition
to holding

the

box contains

core memory,

all

for interfacing
connection
clamps,

a line

memory modules

cables

the

and

necessary for

units

Unibus.

cord

backplane,

of
The

for input
power

and power

providing power

the ME1l-L.
rear of
power,

supply,

and

supply,

the

and

also provides

box contains

cooling

power

fan for

control

for

cable
the

circuit

breaker.

150

Thé system power supply converts single-phase 115V or 230V acline

voltage

memory

system:

the
+5V

two
for

regulated
dc
the

logic

Both

outputs

are

overvoltage

power

supply

also

provides

cooling

fan

and

sent

the

Unibus

The

power

the

supply

BUS

the

consists

and

line

required by

-15V

the

for

overcurrent
power

and

event

and

voltages

the

BUS

power

a power

core

mernory.

protected.
mounting

signals

the

The

box

which

are

failure.

control,

a power

chassis

assembly, and a dc regulator along with aséociated ac and dc
cables.

The

power

which protects

a button on

control

against

the

opens

the

supply if

automatically

input

overload

thermal

and

rear of the mounting box.

regulator

power

contains

one

reset

side

the
when

the

primary

temperature
the

reset

breaker

depressing

A thermostat in the

circuit

rises

temperature

circuit

and

deenergizes

above

100°

reaches

630

L-51

MM11l=S Core Memory

The MM11=S

core memory is

an MM1l-L memory with backplane

and is capable of being interleaved in 16K segments. This
permits

the memory to be expanded above

the

24K 1limit of

the MF1ll=L. The prime physical difference between the MM11-S
and the MF1I=L 1s

while

that

the MFl1ll-L is

If the MM11l=-S
operation.,

the MM1l-8

single

system unit

double system unit,

is interleaved,

When interleaved,

it permits faster memory
two

adjacent contiguously

addressed 8K memory banks are used and successive memory

cycles are performed within alternate 8K memory blocks.

L-52

UNIBUS AND SYSTEM. OPTIONS
.

5.1

SCOPE

The purpose’of this chapter is to provide a general
description

the

Unibus

that

used

interconnect

all major components_of the PDP~11/MO SyStem, In addition,
it provides brief descriptions

of some

of the Unibus

options

(peripherals)

that can be used with the

Because

of the Unibus

concept,

PDP-11/110.

these pefipherals

can be

used, without'modificatiQn, with any member of the PDP-11
family of computers.

Detailed information

the

Unibus

and peripheral

interfacing

is provided in the PDP-11 Peripherals‘and Interfacing Handbo
ok,

UNIBUS

5.2

The

Unibus

memory,

and

single,

all

information

peripherals.

transmitted

form of communication
Unibus.

The

same

communicate
devices

All

memory,

equally well

this

device

memory by

feature,

the

same

other

processor.

considering

the

and

lines

the

used by

processor,

control

of the bus.

for every device
the

the

processor

devices.

The

Peripheral

when communicating with the
peripheral

data

devices.

in memory

in peripheral

registers

connects

data,

and peripheral

applied
data

along

format

that

Address,

format

with memory

instructions

peripheral

signal

also use

processor,

common path

device

can be

registers

may be manipulated
This

special

applied

and

flexibly

especially powerful

capability of

PDP-11/L0O

instructions to process dats in any memory location as
though it were

Most

Unibus

lines

can also be

a peripheral
by

the

lines

same

are

can be
can

bidirectional;

driven

device

processor

data

accumulator.

output

lines.

used
be

for

used

therefore,

This

either

read

peripheral

devices,

transfer

operations.

for

both

input

and

the

input

mesans

that

and

changed
the

Thus,

output

same

the

functions.

5-2

Communication between

slave

relationship.

has

control

the

bus

called

when

the

two

devices

During

the bus.

any bus

This

typical

the

bus

operation,

device,

communicating with

slave.

the bus

another

example

one

master-

device

master,

device

this

controls

the

bus,

relationship

is the procéssor, as méster, fetching an instruction from
memory

disk,

(which

always

master,

slave).

Another

transferring data

to memory,

Master-slave félationships are dynamic.
example,

then

The

passes

bus

communicates

Unibus

thus,

control

with

used by

a priority

slave

the

disk.

the

slave.

The processor, for
The

disk,

master,

memory bank.

processor

structure

control of the bus.

example

and

determines

»Consequently,

all

which

I/0 devices:;
device

obtains

every device on the

Unibus capable of beComing bus master has an assign
ed priority.

When two devices, which are capéble of becoming bus master,
have

identical

use

the

bus,

the

processor

Communication

Each

priority values

control

transfer.

receives

the

signal

acknowledged by

device

Unibus

that

Therefore,

simultaneously
electrically

request

closest

control.

issued by

response

and

interlocked

the

from

master

the

communication

slave
is

between

device
to

devices.

must be

complete

independent

the
the

5-3

physical
slave

bus

length

devices.

The

optimum device

and

the

maximum

design,

response

time

transfer

one

rate

16-bit

of
on

word

the
the

master
Unibus

every LOO

and

with

ns,

2.5 million 16-bit words per second.

Registers

in peripheral

similar to memory;

devices

thus

all

are

PDP-11/Li0

address memory locations

can become

registers

take

and logic

power

differently
assigned

within

devices

the

tape

computer

can

command
is

instructions

I/0

to make

then

the

all

the

PDP-11/l40

Control

the

control

provided by

systems.

and

cause

The

controls

(the

in the controllregister of the device.

such

and BIS

MOV

conditions

this

are

registers

and

that

flexibility in

The
to
the

same
the

bit

same

device,

used

also handled by

instructions.

may be

the

addition,
device

the

bit

similar

the

there

may have,

design

locations
or

status

for

and

purpose.

assignmment

limit

providing

peripheral
For

represents

Status

within

BIT,

the

and

number

are

equipment.

assigned

example,

regardless

flag.

ERROR

CMP

unlimited

peripheral

registers

read

Instructions

of bits

occur.

reader

checked with TST,

control

operation.

15 usually

this

are

bits

reader

enable bit)
as

devices

functions

operations

a bit

Dsata

arithmetic

individual

paper-tape

setting

that

instructions.

advantage

processor.

address,

For example,
of

the

than most

that

a frame

can

assigned addresses

5-4

A device

(other than

the

processor)

bus master generally requests

use

that

is capable

of the bus

of becoming

for one

of two

purposes:
<

To make

non-processor

from memory by means

transfer of data directly to or
a non-processor request (NPR).

interrupt program execution and force
branch to a specific address where an
service routine is located by means of a

the processor
interrupt
bus request (BR).

The

request

with data

Thus,

and granting of bus mastership

transfers

while

one

being checked

Because

using

for priority

time

different master

performed in parallel

a completely independent

device

this

and

the
the

parallelism,

devices

can

bus,
next

the

occur

user is

successive
the

set

request

being

data

full

of bus

lines.

assigned,

transfers

Unibus

speed.

When
a device capable of becoming bus master requests use
of
bus,

the handling

that

device

must

the

determine

processor's

one

processor's

one

has
by

levels

status

inhibits

from external

priority

and

lines.

request

bus

request:

under program control
bits 7,6, and 5 in the
These

three

granting

bits

of bus

set

requests

can be made on any
Non-processor request (NPR)
and its request 1is granted

highest priority,
processor between bus
Bus

of the

devices

the

request

following factors

or lower levels.

five

execution.

The

the location

set

using

the

priority

that

on the same

Requests

depends

the

priority

eight

priority level

(BRs)

request

priority structure.

considered

The

that

the

cycles

(BR7)

request i

(BRlL)

the

an
next

the

instruction
highest

lowest.

5-5

The

four lower level priority requests (BR7 to BRl)
the processor between instructions. When

are

granted by
processor

priority

requests

that

example,

the

set

to a specific level, all bus
and below are ignored. For
processor priority is 6, requests on

level

BR6 or any other lower level

When a
it

other than

the bus

Direct memory
between

any

are called
-made

During NPR

or device

NPR

level

the

data

memory

transfers,

the

access

peripherals

granted.

The

thereby

allowing

bus

directly access
access

structure

control

or interrupt

the

transfers

can be

without

processor

supervision.

a mass

not

between

allows

Normally,

storage

device,

necessary for
the memory

capability permits

disks)

operations

directly refreshing a CRT display.

accomplished
These

transfers

are

such as

disk.

the

device-to-device

(such as

bus,

the processor

and

customer~de$igned peripheral

other devices

NPR

mass

storage

transfers,

controllers

on the

This

bus.

such

An NPR device

allowed

disk

extremely fast access to the bus and can transfer data at high
rates

once

gains

control.

The

processor

state

transfer.

data

transfers.

and

information

device.

direct

not

the processor gains

to perform either a data

two

between

transfer

are

When more than one device is connected to the same
bus request line, the device electrically nearer the
processor has a higher priority than the device further
away. Any number of devices can be connected to a
specific BR or NPR line.

device

uses

the

not

affected

)

by this

type of transfer:

therefore,kthe processor can relinquish

bus

control while an instruction is

the

bus

normally occurs:at

the

in progress.

beginning

or end

This

release
of

of bus

cycles;

however; the bus is never released between cycles of a readmodify~-write

sequence.

Devices

gain bus

(BR7,

that

BR6,

BR5,

BRl)

control

with

one

the

bus

request

lines

can take full advantage of the power and

flexibility of the processor by requésting an interrupt. The
entire

instruction

and status

set

then

registers. When

available

a device

for manipulating data

servicing program is

to be

run, the task being performed by the précessor is interrupted,
and

the

device

service

routine

initiated.

After

the

device

re@uest has been satisfied, the processor returns to its
former
bus

task.

control

Note
has

that

been

interrupt

gained

requests

can be

made

only if

through a BR priority level.

NPR level request can never be used for an interrupt request.

5-7

5.3

UNIBUS

OPTIONS

A large number of Unibus

the PDP-11/40
options is

System.

options

available

for use with

A brief description of some of these

included in the

detailed information,

are

following paragraphs.

For more

refer to the associated hardware

maintenance manual.

5-8

5.3.1

The

PCll

High-Speed

Reader

Paper-Tape

and Punch

unoiled perforated paper

tape

Reader/Punch

capable
of

reading

300 characters

per

8-hole

second,

and punching tape at 50 characters per second. The system
consists

a High-Speed Paper-Tape

Reader/Punch

and

the

PC1ll Control. A uni£ containing a reader only (PR11l) is
also

available.

In reading

tape,

set

of phototransistors

translate

the

presence or absence of holes in the tape to logic levels
representing

1ls

and

the

presence

absence

of holes

in the tape. Any information read or punched is paralleltransferred
on

the

through

Unibus,

the

control.

control

When

decodes

the

address

and

placed
determines

if the reader or punch has been’s‘electedo If one of the four
device

determines

addresses

whether

have been

input

selected,

output

the

control

operation

should be

performea° An input operation from the reader is initiated when
the processor transmitsia command to the paper-tape reader status
register.

transfers

output
byte

operation

initiated when

the varer-tape

punch

buffer

the

processor

The control enables the PDP-11 System to controi the reading or
punching of paber tarne in a flexihle ménner. The reader can be
uncer

direct

surervision

procram

throuch

control

the

use

can

operate without

interrunts

direct

*to maintain

continuous

operation.

5-9

5.3.2

The

LP1]l High=Sreed Line Printer

LP11 High-Speed Line Printer

models,

ranging

(LP11-TA)

Iither

20-column,

132-column,

sets.

available

can be

model

several

(LP11-ITR),

ordered with

The printer

revolving character drum

f4-character model

96-character

column-width printer

96-character
a

from

64-

impact

and one hammer per

tvpe

column.

using
Forms

up to six parts may be used for multiple copies. Fanfold
paper

from

adjustment

inches
to

for pin-feed

7/8

inches

tractors.

wide may be

The

used with

print rate

dependent

upon the data and the number 6f columns to be printed.
Characters
~and

1100

are printed
(or

lines

per

less

in parallel

memorv via

memoryv becomes

a time

are used,

(24

the

the rate

representing a character

line printer then

printer

132-column model)

can be

high

minute.

8-bit value,

transferred

The

24)

full

from the

loads

the
(20

line

the

character

characters)

This

have been printed
or a

special

prints

the

continues

characters

(LPB).

characters

until

character

line printer.

seriallv

printer buffer

automatically printed.

132-column model

Unibus

to be printed,
.is

the

into

When the
are

full

recognized.

time.

the

columns
The

5.3.3

CR11l

Model

CR11l

data

cards

column

Card

Peader

Reader

300

reads

cards

The

punched

per

EIA

standard

per minute;

mark-sense cards,

200

Card

which

80-column

model

can have

CM1l

punched

reads

40-

punched holes,

minute.

card

reader

conjunction with

nificant,

card

extremely

tolerant

separates

the

uses

riffle

air

jam virtually
of

cards

the

that

cards.

input

which works

card wear

impossible

damaged

vacuum picker

and

The

hopper

the

reader

riffling

insig-

prevent

action

sticking.

The picker uses a strong vacuum to grasp thevbottom card and
deliver

the

read

station

demand.

The

picker

and

associated throat block prevent the unit frofi multiple
picking

the

allowed

enter

the

extent

stops

with

pick

check

cards

and

enter

them

reading.

The

card

tolerance,

provide

Cards

in motion

card

into

track
at

read by

taped or
track.

alarm.

gentle

virtually

are

that

The

the

time.

stapled

1In

such

column,

cases

are

the

not

reader

operator

can

separate

input hopper

for

normal

that

only

very
The

short,

combination

card handling,

jam-proof

cards

and

short

the

one

damaged
card

track

operation.

beginning with

Column

select

5-11

instruction starts the card moving past the read station.
Once a card is in motion, all 80 columns are read.

Column

information is read in one of two program-selected modes:

card image or compressed code.

In the card image mode 12

information bits in one column are loaded into the data

buffer and are available to the program at CRBl address.

In the compressed code mode, the card image is encoded into
8-bit bytes and is available to the program at CRB2 address.

A punched hole is interpreted as binary 1, and the absence
of a hole as binary O.

5-12

5.3.4
The

TC1l1l/TU56

TCll/TU56

transport

for

bidirectional

auxiliary

data

reliability

designed

capstans

Svsten

dual-unit,

and high

simply
no

system

maintenance
a.

DECtape

storage.

are

pinch

tape

floats

guides

air

redundant

Manchester

over

the

and

low

tape

guiding
while

(the

tape

in motion)

recording

recording techniques

transport has

recording

cost,

which haveno

(virtually

drop-outs)

Each

tape

rollers.

hydrodynamically lubricated
on

ILow

assured by:

transport mechanisms

and

magnetic

read/write head

playback

five

for

channels

eliminate

information
of

tape.

The

system

stores information at fixed positions on magfietic{tape as in
magnetic

disk

known

variable

tape

systems.

data

tape

drum

positions

This

storage

feature

random

devices,

information on

and

timing

information

determine

ation

the

exact

to be written.

and

timing

‘back

from

information

the

from

used

disturbing

other

In particular, during the

Similarly,
is

of blocks

system reads

tape

position

un-

replacement

the

magnetic

fashion without

tape,

than

conventional

allows

'previously recorded information.
writing
of

rather

format

and

uses

this

which

record

reading,

locate

data

the
to

(mark)

information
the

inform-

same mark
be

played

tape.

5-13

The DECtape

TCll Control
up to

system consists of the TU56

(which will buffer

four dual

transports)

dual

and control

and DECtape(3/4

transport,

the

information

for

inch magnetic

tape on 3.9inch reels),

The

system utilizes

the

first

and three

five

tracks

and

are

system reliability.
on

include

data tracks.

counterparts

bit

a lO-track

non-adjacent

read/write head.
a

timing track,

The other

used

for

tracks

redundant

The redundant
tracks

five

a mark
are

recording

The

reduces bit

a tape

’

track,

identical
to

recording of each

materially

and minimizes the effect of skew.

increase

character

dropout

use of Manchester

phase recording, rather than amplitude sensing techniques,
virtually eliminates dropouts.

5-14

5.3.5

TTM11/TULY

The

TM11/TUl0

tape

system

large

DRCmactare

a high-performance,

ideally

volumes

Svstem

suited

data

for

low-cost magnetic

writing,

and programs

reading,

serial

and

storing

manner.

Because

the

format,

information can be transferred between a
PDP-11 ané

other

system

computers.

collect

data

For

and

tape

stored

upon which

on high

The

TM11/TUll

employs

that

proper

assume

Tape

motion

data

read

writien

detected,

magnetic

the

head

and

might be

processing

used
on

to
large

million bits

tape

density

after
on

the

over

7-track

write

data

can\

million

tépe,

error

checking

tape.

Should

action

can

taken

check

tape

data.

controlled

only

later

appropriate

controlied single capstan.
because

industry-compatible

PDP-11

9-track

stored on high

loss

for

over

density

can be

Tfie 10 1/2 inch tape reels contain up to 2400

bits

dropout

and writes

example,

record

computer.
feet

reads

vacuum

and

servo-

Long tape life is possible

contact with
at

columns

rolling

the

oxide

contact

surface
on

one

the

low-friction,

low-inertia bearing.

5-15

5.3.6
The

RC11/RS64 DECdisk Memory

RCl11/RS64

storage

a fast,

system.

bit words

One

RC11/RS64

storage.

controlled by

one

low-cost,

RC1ll

random access,

combination

four

RS64

Controller

for

provides

disks
a

bulk
65,536,

1l6-

can be

totalof

262,144

words éf storage. Disk functions include: look ahead,
read,

write,

and write

The

RS64

Cyclic

disk

check,

indicates

stores

current

data

Redundancy Check

(CRC)

well

"look

ahead"

disk position.

16-bit word block

error detection

format.

performed

automatically by the controller on a block basis, the blocks
being

randomly

addressable.

clock

recovery

system

reliability.

This

of high

used

technique

restart

shock

after

self-synchronizing,
to

ensure

facilitates

a power

phaselock

exceptional

data

failure

data

recovery

during periods

or vibration.

Fast t}ack switching time permits spiral read and write.
may be
words.

used,

read
When

the

written

the

RCl1l

last

32-~word blocks

address

Controller will

track

from one
or

automatically

65,536

surface has

advance

Data

been

the

next frack orto the first track of a new disk surface.

5-16

Each

RS64

the

disk.

disk

unit has

The Write

Lock

set

switches

ENABLE/DISABLE

whether protgétion is desired or not.
in ENABLE position,

writing

switches is not allowed.

data on

for Write

switch

protecting

determines

If this sWitCh is

tracks

selected by five

The setting of fivé switches

below the ENABLE/DISABLE switch forms a binary number that
corresponds

effect,

the

all

number

tracks

track;

numbered

when

write

from zero

number (both inclusive) are write protected.
to

write

a write

indication by

the

protected

area will

result

protection

the

selected

Any attempt
in

error

controller.

5-17

5.3.7

RF11/RS11 Disk Svstem

The RF11l Controller and RS1ll Disk combine as a fast,

low-cost

random-access bulk-storage package for the PDP-11.

One

RS1l and the RF1l provide 262,144 17-bit words (16 data
bits and 1 parity bit) of storage.

Up to eight

RS11 disks can be controlled by one RF1ll for a tbtal of
2,047,152 words of storage.

The F11/RS11 is unique!in fixed head disks because each
word is addressable.

Data transfers may be as small as one

word or as large as 65,536 words.

Individual words ox

groups of Qords may be read or rewritten without any limits
of fixed blocks or sectors, providing optimum use of both
disk storage and ma'n memory in the PDP-1l system.

The RS11 contains a nickel-cobalt-plated disk driven by a

hysterisis synchronous motor.

Data is recorded on a single

disk surface by 128 fixed read/write heads.

Fast track switching time permits spiral read or write.

Data

may be written in blocks from 1 to 65,536 words. The RF1l control
automatically continues on the next track, or on the next
disk surface, when the last address on a track or sur face
has been used.

The

disk

steres

guard bits and

data words

sync bit

of the RS11 Disk logic.
the

data

data.

strobinto
g

The

RS1l1

has

22-bit

operate

the

The sync bit

ensure

proper

a redundant

set

format which

self-clocking

logic

adjusts the timing of

recovery

includes

timing

each word

tracks,

* %’m

recorded exactly in phase with the primary timing tracks.

5-19

5.3.8

RK11-C DECpack Disk Cartridge Svstem

The DECpack

cartridge

storage

system,

volume,

radom-access

modular mass

tridges

and

The DECpack
over

offering

600,000

1.2

million words

The

DECpack

data

are

1is

When used with

storage.

two

drive;

storage

system

and

per

the

The

own

RKO03

large volume

software

program and data

4.8 million words

for

large

includes

disk

car-

drive

with

(RKO2)

with
over

drive.

for

such

one

the

each member of a group of users

private

complete mass

RKO02

programs

Disk

System or RSTS-11 System, DECpack offers the
permitting

removable

models:

and maintained

PDP-11

solution

The

utilizing

ideal where

developed

control

easy-to-program control.

available
per

and

economical

device

complete

words

drive

data

storage

disk

files.

and

users.

Operating

flexibility of

to maintain his
expandable

up to

or 9.6 million words (RKO3 or RKO5) per

controller.

The

removable

virtually
of
-

disk

cartridge

unlimited off-line

files between on~line

tions.

but with

utilizes

12 sectors.

and

offers

the

flexibility

capacity with

rapid

off-line without

cartridge

similar

the

transfers

copying
IBM

opera-

2315,

Average

total

access

expanded

systems,

one

drive

read

drives

may

time

each

operations

are seeking

write

new head

drive

are

while

milliseconds.

overlapped

one

positions

for

efficiency;

additional

the hext

ransfer.

All data transers utilize thezfinL—Processor Request facility
during

transfers.

Each

disk

that

automatically

While

permanently mounted

on-line,

efficient

The

opens when

dust

continuous

a write

"absolute"

accurate
check

ication by hardware,
maintenance
a major

of wear

There
and

air

data

function,

hardware

features.

source

inserted

contamination

DECpack provides

by means

inside

the

filtration

storage
correct

and

case

drive.

a highly-

system.

transfers

cylinder

verif-

and hardware

no mechanical

critical

disk

prevented by

checksum,
are

a protective

adjustment

detents,
is

thus

eliminated.

5-21

5.3.9
The

with
300
20)s

can

VT01l Storage Displav

VTOlA

Tektronix Model

a resolution of 400
stored
,

with

display

line
a

pairs

full

30,000

stored

611

direct-view

line pairs

horizontally.

screen

erase

discrete

time

storagg

vertically

tube

and

Dot writing

time

The

VTOl

resolvable

500

ms.

points.

The VTO01lA is interfaced to the Unibus and controlled via the
AA11-A and AAll-D

conversion

subsystem.

5-22

5.3.10
The

VROl Oscilloscope Displav

VR0O1lA,

provides

a modified

Tektronix

accurate measurements

tvre

Rm504

DC-to-450

oscilloscore,

KHz

applications.

It is a low-frequencv, high-sensitivitv displav and can be |
used

for

accurate

curve

vlotting

the

X~-Y

mode

operation.

The

VROl

means

is
the

Subsystem.

interfaced
AAl1-R

and

the

AA1l-D

Unibus

and

controlled by

Digital-to-Analog

Conversion

5.3.11

VR14 Point Plot Display

The VR14 is a completelyv self-contained CRT displav with a
6.75 by 9-inch viewina area in a compact 19-inch package.
The VR14 reauires only analog X and Y position information

with an intensitv pulse to generate sharp, bright point
plot displays. Except for the CRT itself,

the unit uses all

solid-state circuits with high-speed magnetic deflection to
enhance brightness and resolution. The intensity pulse may
be time multiplexed or gated by a separate input to allow

the screen to be timeshared between two inputs.

The display

unit is available in rack-mountable or stand-alone models.

The VR14 is interfaced to the Unibus and controlled through

the AAl11-C and AAll-D Dicgital-to-Analoqg Conversion subsvstem,
A two-color display
with the AAl1l1-E
subsvstems,

(VR20)

is also available.

It is used

and AAl11-D Digital-to-Analog Conversion

5.3.12

The

VT0R Alphanumeric Display

VT05

terminal

with

eqguipment

lines
300

flexible,

hgh

performance

ray

tube

cathode

capable

and data

sets

display

transmitting

at half or

alphanumeric

data

full

and

over

duplex

display

communications
standard

rates

phbne

up to

Baud.

contolled by

Teletype

the DL11l,

terminals,

equivalent

the

same

controller used wit

may be

used

over

Bell

103A

modem.

5-25

5.3.13

RTfli DIIClink Terminal

DEC-link

low-cost,

self

contained

which is remotely locatable.
serial

line

keyboard

either
up

compatibility.

characters

numeric
12

data

digits

which

well

status

Data

entered

via

data

displayed

numeric

indicators

device

DEC-link

offers

a monitoring

(plus

unique

computer

functions.

data

decimal

may

can

use

for

display

point)

indicators.

are

entry

It features Teietype and BIA

control

decimal

data

used

integral

l6-character keyboard;

locally.

indicate

non-numeric

The

status

information

such as 'repeat transmission', "cbmputer ready", etc. Four
programmable
The

DL11l.

status

Control

indicators

may be

are

used with

‘or it may be used over a Bell

standard
the

RT01l

on
for

DEC-link.
direct

connection

1032 or equivalent modem.

5.3.14

Communications

DIGITAL has

extended

communications

Ontions

the

PDP-1l's

applications

with

adaptability

variety

various

interfaces.

These devices enable the PDP-11 to be connected both locally
and

remotely

lines.

The

serial asynchronous

interfaces

allow both

and

full

serial

synchronous

and half

duplex

operations with connections to communications terminals via
the

standard EIA

are

summarized bebow:

DEVICE

DC1l1

RS232-C

INTERFACES

and CCITT

PDP-11

interface.

WITH:

Serial Asynchronous Line

The

TYPICAL

devices

USES

Connects PDP-11 to
various

asynchronous

terminals,
another
a

computer

common

carrier

communications

DP11

Serial

Synchronous

Line

program

controlled

Baud

rates,

character

lengths,

and

Connects

PDP-11

remote

terminals

serial

DM11

Autocalling Unit

l6-serial

Asynchronous

Lines

8-bit

Line

local
and

speed

terminal.

remote

computer

Terminal-oriented
timesharing,

remote

Serial

computers

dial

for

codes.

via high

forward,

~Asynchronous

stop

line.

switching,

DL11

facility.

Has

DN11

via

store

data

systems
message

and

collection,

concentrators.

Connects

PDP-11

teletype

connections

and
mode

local

8-bit

local

current

devices.

5-27

DL11

Serial

8-bit

Asynchronous

Connects
Line

remote

PDP-11

8-bit

asynchronous

CRTs,

readers,

to local

terminals

plotters,
and

EIA-compatible

line

such

card
printers.

5-28

5.3.15

AFCll

The AFCll
input

Low-Level Analog

flexible,

subsystem

for

Input Subsystem

high performance,

IDACS-11l

differential

industrial

data

up to

differential

analog

acquisition

conttol

systems.

The AFCll

system multiplexes

analog signals,
to-digital

selects gain,

conversion

1024

input

and performs a 13-bit analog-

200

channel

per

second rate

under

program control. Three signal conditioning modules and eight
program-selectable

gains

allow

the

system

intermix

accept a wide range of signals: low level

(1l0mv f.s.),

level

(100%0v

Designed

for

industrial

f.s.),

and

accurate

current

and

environments,

inputs

reliable

the AFCll

operation

50ma

and

high

f.s.).

demanding

achieves high

isolation

and common mode noise rejection‘through relay switched
capacitor multiplexing.
wiring,
to

requiring only

The

subsystem

simple

twisted

also

pairs

simplifies
which

input

connect

screw terminals.

Modularly constructed in eight-channel standard hardware

,.e’/“ A

units,

the

AFCll

and

simple

The

analog

input

easy

configure

user applications,

expand.

subsystem

particularly

suited

for

data

5-29

acquisition in the high noise environments

encountered in

process

testing

monitoring

applications.

noise,cabling
operation

and
such

production

environments

common

and grounding problems
such

transducers

analytical bridges,
These

control,

problems

can

the measuring

typical

and

can

and normal

greatly

thermocouples,

.industrial milliamp,

also

affect

the

accuracy

and

laboratory
mode

affect
strain

current

the
gages,

transmitters.

and performande

system.

applications,

use of ungrounded

sensors

could

cause

common mode voltages of up to 150 volts peak-to-peak (at powér
line

frequency)

measuring

system.

appear on
For

the

example,

ungrounded during operation,

input
if

large

signal

leads

the

termocouples become
common mode

voltages

can

appear in coincidience with the signal. The design features
of the AFCll

allow either floating

grounded

signal

thus insuring reliable, trouble - free operatiogl°
the
mode

flying

capacitor

design,

voltages

excess

multiplexers,

contrast,

mode

over

voltages

the

200

system

volts.

can be

tolerates
FET

seriously

sources

Due to
common

solid-state

damaged with

common

volts.

5-30

5.3.16

AD(01-D Analog-to-Digital Conversion Subéystem

The ADOl-D is a flexible, low-cost multichannel analog
data

acquisition

computers.

control,

When

the

option which
it

ADOl-D

under

interfaces
computer

rpovides

10-bit

directly

external

clock

digitizatinn

PDP-11

unipolar

high-level analog sighals having a nominal full-scale range
of

bit

to _1.25,

addition

input

range

+2.5,

allows

sampling

unipolar

signals

optional

aperture

Available

the

14 bits

sample-and-hold

100

volts.

operation.

the ADOl—D's

the

optional

equivalent

for bipolar

amplifier

sign-

Programmable

dynamic
of

range

bits

for

signals.

reduces

the

conversion

nanoseconds.

factory or

standard ADOl-D

+10.0

extends

rates

ll-bit bipolar

selectionn

moderate

+5.0

consists

fEld-installed
of

PDP-11

expandable

option,

the

solid-state

input multiplexer, programmable input

range selector, A/D

converter,

control,

rackmountable

assembly plus

The multiplexer
up

provide

and bus

can be

channels.

a manimum

interface

separate

expanded by
expansion

configuration

single

logic

adding

power

4-channel

multiplexer

may be

1/4

inch

supply.

modules
added

channels.

5-31

The

subsystem

is well

monitoring, logging,
in both

laboratoy

choice with

first

economic

and

acquisition

suited

and

a variety of

analytical

and manufacturing

OEM's

efficient

systems.

and

system

tasks-testing,

instrument

data

environments.

system contractors
component

for

reduction

also

sophisticated

data

5.3.17

AAll1-D Digital-to-Analog Conversion Subsy
siem

The AAll-D

digital

analog

Interfacing
up

four

low cost,

conversion

directly
single

converters.

Each

high performance multichannel

the

buffered,
BA614

subsystem

PDP-11
12

for

Unibus,

the

bit bipolar

converter,

which

PDP=ll

computers.

AAll-D

digital

includes

controls
analog

output

amplifier and reference voltage.source, ié contained on a
plug-in module

volts.

Full

+1lv to +10v

Storage

are

and provides

scale

two

scope,

available

output voltage

current output

timpot

at ilQ

adjustable

from

ranges.

display

for

10 ma

scope,

the AAll-D.

and

light

These

pen

control

options

provide

axis

bianking for intensity control and require two D/A converters
to

control

Available
fully

and Y

trace

factory

implemented with

scope

rack mountable

control

option,
power

coordinates.

field

installed option,

four

digital

contained

supply

to
in

analog
a

the AAll-D

converters

single

and

System Unit.

separate.

5-33

EQUIPMENT

6.1

SCOPE

The

purpose

MOUNTING

this

PDP=11/40 mounting

The

POWER

chapter

and

BA11=FC mounting

is discussed

AND

power

box

in paragraph

provide

detailed

information

the

system.

basic

6.2.

the

PDP=11/40

mounting

System unit allocations

system

as well

and

processor and basic memory slot allocations are noted for the basic
box.

This mounting

system mounting

(paragraph

System

6.4)

consists

space within

provided

basic

power

H742

in paragraphs

shooting

6.5.1

power
of

the

bulk

presented

same

cabinet

This

power

supply

and

power

through

distribution
power

supply.

and H745 (=15V) regulatofs.

Basic

context with

and

the

adjacent

cabinets

6.3).

power

and

information

system

power

control

supply
its

unit

(paragraph

individual

H744

6.5)
(+5V)

These three items are covered separately
6.5.3.

is
is

covered

described

paraagraph
in

6.5.4

paragraph

and

6.5.5.

trouble-

6.2

SYS5TEM MOUNTING

BOX

The major components of
the power

system and

BA11=FC mounting

interfaces

console

box.

also

the PDP=11/40 System,

Space

I/0
for

device,

the exception of

are mounted

additional

provided within

with

memory

and/or

single
peripheral

this mounting box.

The BA11=-FC mounting box is mounted‘in a standard DEC H960=-C cabinet
as

shown

that

in Figure

6-1,

it can be pulled

modules;
fans

the

power

are mounted

The

box

is mounted

out for maintenance

supply,
top

however,
the

box

logic elements within the box.,
located on the front of

this

Chassis

and/or

remains
to

installation of

within

provide

slides

the

proper

cabinet.

cooling

The KY11-D Programmer®s

Console

logic
Cooling
the

box.

The mounting box is capable of holding nine system units or
equivalents. Each system unit casting contains four slots for
mounting logic modules.

An alternate double system unit contains nine

sloté as it has no center casting,
for

the KD11=A processor

and

This double system unit is used

MF11-L memory.

Allocation of logic within the box is shown in Figure 6»2° A double
system unit
options.

(with nine

Another

double

slots)

used

system unit

for

the processor

used

for

and

the MFil1-L

processor
core memory

which includes\threelmodfiles to provide a basic 8K memory. This leaves
space

for

five

additional

system units

(or

equivalents)
for additional

memory and/or peripheral interfaces. Note that core memory should always

placed

box

asclose

provides

(expansion)

Module
are

mounting

allocations

Whenever
be

the

processor

space,

power,

possible.

and

cooling

The

basic

mounting

for

these

additional

units.

covered

must

for

the

paragraphs

expansion

considered

processor,
6.2.1

item

such

through

added

the

memory,

number

and

6.2.3,

the
of

programmer®s

console

respectively.

basic

system

box,

certain

units

required

factors
by

the device, power cable connections, Unibus connectiofis, and jumpers.
Power

cable

connections

are discussed

(such

often

necessary

existing

the

KT11=D,

device

included

the

KT11-D,

included

are

KJ11-A,

cut

(such

KE11=E,

the

etc.)

installed

both

are
on

the

processor).

covering

this

paragraph

6.3.2.

KE11-F,

paragraph

jumpers

the manual

Chapter

covered

and

manual.

When

Pertinent

Unibus

the

bhox,

and

jurmper

However,

processor

inter-

certain devices

new device

the device.
KJ11=-A

6.5,

it is
an

information

options

also

FAN

CABINET
HOUSING
860

POWER

CONTROL
1

860A:
11, Vac
860B:230
Vac

[

HS60 C CABINET
CA :1i5Vac
CB: 230 Voc

(HIDDEN)
AC POWER
RECEPTACLES

CABLE SUPPORT STRAP
AND CABLE HARNESS

H742
POWER SUPPLY
WITH REGULATORS

——BA11-FC
MOUNTING

.\.\Q.O\

BOX

UPPER LOGIC FANS
Q Q Z 2 o - ut

Y
/=

MODULES INSTALLED IN CPU
BACKPLANE ASSEMBLY

11~1386

Figure

6-=1

PDP=11/40

6=3A

System

Cabinet

MF11-L

CORE MEMORY

DOUBLE SYSTEM
UNIT, 9 SLOTS
—A—

T
|

SECTIONS

;

[

¥
I

;

[

]

—

]

KY{11-D
PROGRAMMER'S

s CONSOLE

]

o
~

SPACE FOR
ADDITIONAL MEMORY
OR PERIPHERAL
INTERFACES

_“—-——-——J

KD11—A PROCESSOR
DOUBLE SYSTEM
UNITS,
9 SLOTS

S5 SINGLE SYSTEM
UNITS OR EQUIVALENT

LEFT SIDE VIEW

(MODULE VIEW)
11-4570

Figure

6-=2

Mounting

Box

(BA11-FC)

6,2.1

Figure

Processor Module Allocations

6=3

unit for

shows

the

the module

basic

KD11=A processor

noted with an asterisk

be present.

allocation for

are

Other modules

the

the M7237 module

Maintenance Console

processor options.

standard basic modules

are optional with

designation noted on the figure.
requires

and

the KD11-A double

The modules

and must always

specific option

The KT11-D Memory Management option

addition to

option may be

the

system

the M7236

plugged

into

module.

either

The KM11=A

slot F1

or EI

depending on whether the user is monitoring the basic KD11-A procéssor
or one

Ixtended

three processor

Instruction Set,

options

(KT11=-D,

or KE11=F,

Memoryv Management,

Floating

KE11<E,

Instruction Set}.

'r"\j,/\/__\\/\_/_\—/_- w
@

(@]
—-‘

SMALL

PERIPHERAL CONTROLLER

(USUALLY DL1{)

KT11-D

TIMING

STATUS M7235

DECODE M7233

PATH

U WORD

(M787) | (M7237)

TOP —&

Figure

6=3

EIS OPTION

KMI1-A | KM11-A
(FOR
KDIN|(FOR K1 KE)

Module

Allocation

LEFT

—

M7232

M7238

]
KE11-F
FIS OPTION M7239

SIDE VIEW

KD11=-A

6=4A

M7231

KWIT-L | KdJil <A
OPTION | OPTION

KEi11-E

DATA

| o

M7234

REAR

UNIBUS (M981)

MEMORY MANAGE
OPTION
MEN
(M7236)
T

Processor,

11-1381

Basic

(*)

and

Options

»6,2,2

Memory Module Allocations

Figure

6-4

unit.

This

for

the

also

shows

the module

memory unit

basic

PDP=11/40;

mounted

within

allocation

provided
two

the

with

additional

same

system

for
a
8K

the MF11-L double
single

8K memory

segments

unit.

sys tem

segment

(MM11=-Ls)

Additional

MF11-L

can
and

MM11=L memories can be installed in the free system unit space Within

the

BA11-FC mounting

box

(Figure

6«2).

6.2.3

Programmer
’s Console Mounting

The K¥11=D Programmer’s Console

is mounted on the front of

mounting box as

6-1. Mounting is

shown in Figure

the BA11=FC

integral with the be:zel

‘and panel mounting. The console is cabled directly to the processor
modules and provides both switch and display signals. Power to the console
is applied

through

these

same

cables.

SECTION
1

v
1

)

sl
|

H214 MEMORY STACK
G231

MEMORY

oAl
1

UNIBUS

DRIVER

SLOT

09
08

G110 CONTROL AND DATA LOOPS

G231 MEMORY DRIVER

H214 MEMORY STACK

[

*G110 CONTROL AND DATA LOOPS

%G231 MEMORY DRIVER

REAR L% H214 MEMORY
R
STACK

]

UNIBUS

TOP —&
11-1571

Figure

6-4

Module

Allocation

- MF11-I, Memory,
6=-6A

Basic

(*)

and Optional MM11-Ls

6.3

CABINET AND

Because

the

modularity

peripherals may be
and

number

system

SYSTEM MOUNTING

added

peripherals

cabinet may

the

PDP=-11/40

the basic

selected,

sufficient,

System,

system.

the

variety

Depending on

remaining

space

additional cabinets

the

in the

may

type
basic

have

be added to the system. The basic system cabinet is discussed in

paragraph 6.3.1 and multiple=cabinet systems ére discussed in
paragraph

6.3.2.

631

System

Cabinet

The cabinet housing £he basic PDP=11/40 is divided into six levels.
The

bottom

level

entry.

Levels

houses

the basic

(level

four

and

six)
five

system.

reserved

contain

Levels

one

the

for

power

BA11=-FC

through

supplies

mounting

three

provide

box

and

cable

which

space

for

.mountingAup to three peripherals, each having a front panel height
of

10%

inches.

system,

box.

There

cabinets.
system

always

are

high=-speed

installed

paper-tape
directly

certain restrictions

These

cabinet

peripheral

are
is

(system

discussed

concerned,

in
it

I/O device,

reader

above

should

card

the

mounting

paragraph
be

reader,

BA11=-FC

the

basic

mounting

peripherals

6.3.2.
noted

added

far

that

any

free=standing

etc.)

can

the

basic

further

from the cabinet than the maximum length of the interconnecting
cable

between

the

interface

the

cabinet

and

the

device

itself,

6.3.2

System Configuration

In many cases,

the number and types of peripherals added to a basic system

necessitate additional mounting cabinets; The standard cabinet
layout

for

PDPm11.$ystems

starts

the

right

and

evolves

the

left.

Another standard practicelis to define the equipment in the processor

cabinet first, then move to the next cabinet not defined for a specific
device.
It is
chain

always

keep Unibus

interaction are all

necessary

to keep

length

a minimum.

toc

in mind

the

overall Unibus

Cooling,

cabling

and

logic

system considerations which must be accomodated.

Configuring multiple cabinet systems therefore requires, as a general
rule,
at

the

This

full-depth

top

device,

position

restriction

(level

combination

bottom

position

necessary

ensure

unrestricted

the unused

bottom.

Devices

can

device

provided

the

installation

that device.

specific

any

disk

Disk

the

placed

cabinets

system

cabinet,

and

top

rigidly

fixed

equipment.

rigidly

fixed

equipment

cabinet may

used

for

mounting box which

the discretion of

the

information

for

of devices,

its

does

cabinet

used

only

cable

placed

cabinet,

entry

space

with

the

another
operation

for mounting

that

options.

Levels

(level

interfere

are normally

position

not

should

(level
2

through

slide-mounted

should
5

user.

Figure

a multiple

cabinet

house

6=5

may be

equipment.

peripheral device

then used

used
The

only

for

device

illustrates

for

either

level

for mounting an

various

system.

used

any

extension

interfaces

typical mounting

The major
is

logic

latency.

Latency

left unserviced
only

optimum

interaction consideration

before

extremely
system

defined

large

loses

systems

performance.

in multiple cabinet

the

longest

time

data.

Latency

but

should

A recommended

still

device

usually
be

priority

can be

a problem

considered
has

systems

for

been established

to determine which peripherals should be mofinted closer to the

‘processor to compensate for timing characteristics of NPR devices and
latency
Tables

requirements
6=1

and

Figure

system configuration

the

BR devices.

respectively.

and

6=2,

for

accomodates

PDP=11/40

these

The

These

typical

priorities.,

contained

priorities
mounting

Additional

in PDP=11

are

listed

information

Confiquration Worksheet

Site Preparation Worksheet,

6-104A

g2aIn31¢-9Jeo1dLIo1dI3Ini1outqe)WISAGUOT1eINSTIUO)
v6Y31INlYd
HO 96
HYHO

Hid 3NN

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%,

d3Llgm

2L51-1

Table

Timing

Characteristics

NPR

Worst

Priority

*The

RP11

6-1

Case

PDP-11

NPR Devices

Time

Between

Device

Latency

RK11/RKO03

8.5

11.1

RP11

*¥14,8

RC11

RF11

RK11/RK02

22.2

TM11

TC11

200

DM11

100

}119

CD11

800

DR11=B

Dependent

customer

use

transfers

two

words

{usec)

each

Available

14.8

(at

800

Data

(usec)

bpi)

1200

baud)

microseconds

Table

6<2

BR7

BR6

BR5

*ADO1

KW1i=L

DP11

- DT11=-B

TC11

DC11

CR11

DP11

CM11

DC11 @ 1200 baud

KWi1=-P

DP11

2400

+UDC11

DC11

600

DP11

2000

DC11

300

DM11

‘

9600

baud

higher

KL11

1800

baud

+UDC11

4800

baud

AFC11

“

baud
baud
baud
baud

**DR11=2A

DR11=B

*For ADO1

slow

sampling

input

high

rates.

Can

assigned

applications.

**Priority positions

BR4

(D]

Priority

wezh

Priority of Devices Affected by BR Latency

depend

UDC immediate = BR6;

customer

application.

UDC deferred = BR4,

lower

level

for

6.4

POWER CONTROL

Both

the

power

control

permits
and

basic

system

down

power

computers

that

the

system

functionally

the

following:

power

control

consists

a master

power
of

the

switch

system.

The

860

power

and

861

power

include

components,

the

single master

event

the

system

fire

same

for

switch,

any

all

cabinet,.

PDP=11

unit

(OFF/POWER/PANEL

switch

programmer’®s

PDP=-11/40)

cabinete=mounted

PDP=11/40

system from a

control
and

specific

power

system

cabinet=mounted

the

entire

the

entire

Cc.

controls

the

console

expanded versions

operation of

shuts

This

and

SYSTEM

thermal

system may
control

control

unit

switch

use

unit
is

either
is

described

referenced

6-13

860

861

power

paragraph

control

6.4.1

6.4.2.

6.4.1

860

Power

The 860

power

Control

control

Unit

unit

operated

from

the

console

panel

switch

and is capable of switching up to 302 of 115 Vac (860A) or up to
15A of

230 Vac

voltage

two

(8B60B).

The

power

output

strips

control

located within

provides switched

(or controlled)

plugged

into

strip

second

strip

continual

strips

this

provides

application

permit all

under

power,

basic

PDP11/40

the front)

In multiple

ac
such

system devices

thereby necessitating only one
cabinet

the

ac power;
control

unswitched
of

unit distributes

for

the

cabinet.

that is,

right

cord

disk

strip

you

face

(as

the switched or controlled

cabinet configurations,

the

cabinet.
the

The

that require

drives.

within

from

strip

switch.

operating devices

to be connected

power

One

any component

the master

as magnetic

These

cabinet,

the

cabinet

from

ac power strip.

operation

the

entire

system

can

be controlled by the console OFF/POWER/PANEL switch provided there is
at

least one

power

control

unit.

However,

than one

processor

require

a master

processor

console

any

switch

systems

that

containing

separate

from

more
the

switch.

The cabinetemounted thermostat removes power from the switched ac
power

strip

A power

system,

bus

in the

control

bus

event of

cable

Devices may be

in parallel

at any

added

fire

in any cabinet.

used

“

the

interconnect

system

convenient point.

all devices

connecting

terminators

them

the

are required

the bus and ¢°T*®® connections may be used without any restrictions. The

poWer control bus cable is a 3-wire cable joining two 3-wire male
Mate=N-Lok connectors.

Detailed instructions for

are given in paragraph 6.4.1.1.

interconnecting devices

860 Physical Description

6.4.1.1

The 860 powér control unit consists of an input circuit breaker, line
filter,

pilot light,

detector.

relay,

output filter,

control board,

and

thermal

These components are housed in an enclosure which is mounted

in the top of the system cabinet next to the cabinet air intake fan.

The bottofi of the enclosure contains three 3-pin Mate=N-Lok connectors,
a REMOTE/OFF/LOCAL switch,

and the detection element of the thermal switch.
”

The three connectors are wired in parallel to accept connection from the

standard 3e-wire control system. These connectors permit interconnection
of power control units from one system cabinet to another.
REMOTE/OFF/LOCAL switch permits all

system power

one power control unit. When set to LOCAL,

The

to be controlled by

it allows the specific power

control unit to be removed from the overall power system so that it can
be run independently.

control,

In a system containing more than one power

interconnecting cables would be

installed between the connectors

of adjacent power control units in a daisy chain manner to provide
system power control

(Figure 6-6).

In this instance,

the switch

would be set to REMOTE to allow routing of power control fromone
‘cabinet to another.,

6-16

860

POWER CONTROL

860
POWER CONTROL

(PROCESSOR CABINET)

(ADDITIONAL CABINET)

(1 23) (12 T}

(12‘7)(1273

(12 T) (12 3)

POWER

860
CONTROL

7009053
" CABLE

7008288

CABLE

PDP-11/40

CONSOLE

(KY11-D)
11-1573

Figure

6-=6

Power

6-16A

Control

Interconnection

6@4®132

860 Functional Description

The 860 power control unit has two main functions:

to route ac power

from its line cord to an unswitched ac power strip and to switch

,thekincoming'ac on another power strip when the console switch is
closed

turn on

the

system.

The

~ 860A or 860B power control unit.
models

The

power

lines

If
a

are

listed

in Table

6=3,

control

operates

system may use

either an

The differences between these two

3=wire

parallel

control.

The

three

are:

Line

power

Line

emergency

Line

ground

neither Line
power

When

PDP-11/40

off

lines

Line

off

connected

Line

the

system

state.

and

3 are

connected

through

the

console

switch,

operation

of the switch causes activation of the power relay within the 860

power control and provides input powér to fhe switched or controlled
ac power strip.

Connecting Lines

2 and 3 causes an override of any

other state of the power control and removes the switched»ac power
by

opening

the

860

power

control

internal

relay,

Line 2 is utilized by the thermal detector to provide protection in
case

fire

excessive heat.

Table

Model

Ttem

Input

line voltage

Circuit breaker CB1

Transformer T1

Input power

primary

line cord

6=3.

Differences

Model

860A

860B

115 Vac

230 Vac

30A

15A

115 Vac

230

Vac

115

230

Vac

VvVac

15A

30A

25
P/N

feet
1203485

P/N

feet

1204687

6.4.1.3

860

Circuit

The

860

power

basic

light on

cord

the

line

plugged

Description

control

side

into

circuit{is

the

circuit

the wall

and

shown

in Figure

breaker

lights

power

applied

6=7.

when

the

A pilot

the

unit.

line

The

voltage from the secondary of transformer T1 is half-wave rectified
to

provide

and

Q2,

424V which

and

energize

the

event

the

power

control

this

fuse

power

K1.

The

control

transformer

and

output

present

the

checked.

Note

that

power

strip

this

case

because

but

does

not pass

When

the

power

control

relay Ki1.

used

switched

power

set

REMOTE.

When

set

S1
is

POWER,

power

applied

off

control,

the

completes

strip,

the

tapped

the

fused.

switched
ac

available

through

switch
switch

transistors

sicondary

properly

and

OFF/POWER/PANEL

to provide

connected

line

REMOTE/OFF/LOCAL

used
relay

system

should
be

unswitched

the

console
a

ground

circuit that causes Q1 to cut off. When 01 cuts off, Q2 conducts
and

causes

relay

circuit.

Other

switches

the

energize,

connectors

perform

the

circuit between pins

used,

for

example,

are

which

provided

same

function

3).

and

systems

closes

to
as

the

allow
the

A remote

switched

remote

console

power

containing more

than

power

switch

output

control
(close

switch would
one

processor,

Thermal switch S2 provides protection against fire or excessive heat.
It

normally

open but

closes

the

cabinet

ambient

temperature

exceeds 130°F (540C), When it closes, Q2 cuts off, relay K1 deenergizes,

and

the

switch

switching

off

connects

the

ac output.

additional

thermal

box)

connected

the

same

Line

function.

switches

(emergency

Pin
(in

The

switch

on connectors

the

in parallel

off)

cabinet

with

opens

and

thermal

ground,

J1,

and

permits

extension mounting

switch

restore

J2,

thereby

power

once

perform
the

temperature

falls below 85 F.

When

the

power

control

REMOTE /OFF/LOCAL
always

cut off,

switch
Q2

is deenergized,

strip,

only

used

an unswitched

always

conducts,

thereby

removing

there

condition occurs.

set
and

to
K1

power

input power

power

LOCAL.
remains

from

failure

the
or

control,

Thus,

energized.

switched
if

)
Relay

power

overtemperature

6.4.2

specific

than

861

Power

Control

PDP-11/40

860.

The

861

Unit

system may
power

use

control

an
is

861
a

power

later

control

version

and

unit

rather

available

three different models:

861A

115

Vac,

50/60

Hz,

2-phase

861B

230

Vac,

50/60

Hz,

single

861C - 115 Vac,

A detailed
Type

861-A,

description
861-B,

861=-C

phase

50/60 Hz, single phase

the

861

power

control

unit

Power Controller Maintenance

is given
Manual.

the

6.5

PDP11/40 Basic Power Supply

The basic PDP11/40 power system consists of

the ac power distribution strips,
basic box fans,

the power control unit,

power distribution for

the cabinet and

and a modular power supply for regulated dc voltages.

A block diagram of the basic power system is shown in Figure 6.8. The
power control unit
been discussed.,

(860 or

861)

and the ac power strips have already

The distribution for cabinet fan power is

ac power strip with

the unswitch

the basic box fans receiving power through the

H742 bulk power supply.

The PDP11/40 Modular Power Supply

consists of this H742 bulk power

two H745 =15V regulators.

supply,

two H744

(Figure

6.9}

{5V regulators and

These elements of the modular power supply

are discussed in detail in paragraphs 6.5.1

through 6.5.3,

respectively.

Please note that these details are for theory of operation and off=line

repair., Maintenance should éonsist of replacement per paragraph 6.5.5.
DC power distribution and cabling are covered in paragraph 6.5.4 with
information on expansion provided. Power supply maintenance is
covered

in paragraph 6.5.5.

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Figure

6-9

PDP-11/40

Power

6=22B

Supply

6.5.1

H742 Bulk Power Supply

The H742 power supply is functionally divided into two major pafts:

Bulk

57,

Power

Supply

(drawing

D=CS=H742-0-1)

used

provide

the various ac input voltages required by the fans, regulators,
and

power

Power

control

board.

Control Board

(drawing C=CS=5409730-0~1)

provide +15 and +8 voltages,

line‘clockp

— used

and AC LO and

DC LO signals for system use.

The PDP=11/40 power systefi operates with 115 Vac or 230 Vac primary

SOfirce power inputs, Although different 860 (or 861) power control

’units are provided for each input voltage, the same H742 power
supply can be used with both versions. Jumpers are connected fo
terminal

T1,

strip

that

TB1,

which

the

it can operate with

primary

the

power

selected

supply

transformer

input voltage.

If 115 Vac 0peration is required, jumpers are placed between pins
1 and 2, and between pins 3 and 4 of TB1.
required,

Line power

jumper

applied

T1.

The

the

regulators

for

the

from TB1

transformer

power
and

and

power

not

between

through TB1

secondaries

control
does

connected

control

board.
come

from

board

the

pins

and

the primary of

provide

Power

If 230 Vac operation is

20-30
as

well

cooling

transformer

Vac

input

power

15=24

Vac

fans

transformer.

tapped

for

power
directly

The power

control

output used
the

These

and

outputs

board

drive
DC

portion

the

power

supply

(drawing

the KW11-L Line Frequency Clock
control

are discussed

signals

used

paragraphs

for

power

6.5.1.1

option,

fail

and

sequences,

through

6.5.1.3.

6.5.1.1

+15V and

The

control

power

+8V of

board

the

H742

Supply

H742

supply

contains

+15V/+8v

»dc supply and is described on print C=CS=5409730=0=1, This dc
supply

This
dc

The

receives

15=24

Vac

from

the

input

fullewave

applied

Darlington power

bias

on Q1

secondary

rectified

controlled

voltage

increases,

starts

to provide

+8 Vdc at output pin
conducts

+15V and

bridge

increase,

+15 Vdc

5, and 6
the

transformer

D1.

The

through

fuse

output

T1,

resultant
F1.

pins

(ground). If the Of

bias

the

base

and 02 conducts slightly more current to maintain a

constant output voltage.

by diode

amplifier 01,

and 3 with respect to output pins.4,
collector

hard

1.
cut

48V outputs,

Zener diode D7 provides approximately
When DC LO is
off

grounded at output pin

completely;

thus

removing

both

9,
the

6.5,1.2

Cilock Output of

the H742

The CLOCK output is derived off one

Supply

leg of

full-wave rectifier

bridge D1 by voltage divider R10 and R11, and Zener diodé D2, The
CLOCK output is a 0 to 5V square wave at the

line frequency of the

inpuf power source (47 to 63 Hz). The CLOCK output is used to drive

£he KW11=L Line Frequency Clock option, which mounts in slot ¥3 of the
processor backplane or

the KW11=-P option, which can be mounted in

the Small Peripheral Controller slot.

Operation of the RKWi1i1-=L

option is described in the KD11-=A Processor Manual;
the KW11=<P is described

in its manual.

operation of

6.5.1.3

The

LO and

and

Circuits

control

signals

are

used

warn

the

processor

that a power failure is imminent so that the processor has time‘to
perform

power=fail

(line power

bulk

followed

LO.

allow

storage

sequence.

supply

failure),
AC LO

asserted

Sufficient

volatile

there

time

data

and

exists
the

power

between

failure

these

conditioning

the bus

signals

peripherals.

The 20=30 Vac input from the secondéry of transformer T1 is applied to
the AC LO and DC LO sensing circuits on the power control board. The
ac inputlis rectified and filtered by diodes D8 through D11, and
capacitor
R18

and

manner.

and

C3.

zener

diode

Each

contains

associated

common

the

reference

D12.
a

circuits.

Both

voltage

sensing

differential

The

major

derived

circuits

circuit differential

resistor

operate

amplifier,

difference

amplifier

similar

transistor

that

the

switch,

base

slightly

lower value than that of Q9 in the DC LO differential amplifier.
The

operation

capacitor

When AC

both

sensing

circuits

depends

upon

the

voltage

across

C3.

being

sensed,

the

20=30

Vac

input

rectified

and

stored in capacitor C3 which charges and discharges at a known
rate

whenever

that

through
example,

the

applied
R17

when

to
a

power

the

rising

power

switched

emitters
or

fails,

off.

of differential

falling
or

waveform

shut

down,

Thus,

the

amplifier

known

the

Q6/Q7

value.

voltage

For
decays

at a known rate as determined by the RC time constant. If the voltage
decreases to approximately 20V,

the base of Q6 becomes negative with

respect to the base of Q7. The increased forward bias on Q6 causes
it to conduct more and the resultant decrease in Q7 causes it to cut
off.

This removal of voltage across R16 causes Q5 and Q4

to conduct,

grounding the AC LO line‘at pin 8. The AC LO signal is applied
through the cable harness and processor backplane to the processor

power fail initialize logic

so that the power fail sequence can be

started.

The DC LO sensing circuit operates in a similar manner to the AC LO

sensing circuit. The prime difference between these two circuits is
the voltage level at which they ¢®trip.°®® For example, if the ac input
starts to decrease,

as a result of a power failure or shutdown,

the

AC LO lines are grounded before the DC LO lineéo As power is restored,
the ground is removed from the DC 1O lines before it is removed from

the AC LO lines. The DC LO signal is also applied to the power fail
initialize logic.

A description of how the AC LO and DC LO control signals are used

in the KD11-A processor is provided in the KD11=A Processor Manual.

6.5.2

H744

+5V Regulator

Two H744 15V regulators are used

in the basic PDP=11/40 Power System,

The H744 circuit schematic is shown in drawing D=CS=H744-0=1, The
’following paragraphs describe the requlator circuit, overcurrent

sensing

circuit,

and

overvoltage

crowbar

circuit.

6.5.2.1

The

H744

20=30 Vac

provide

Regulator Circuit

input

is a full wave which is rectified by bridge D1

voltage

(24

40V,

depending on

line voltage)

across

filter capacitor C1 and bleeder resistor Ri. Opefation centers on
- precision voltage regulafor E1 which is configured as a positive
swifching regulator. A simplified schematic of E1 is shown in Figqure 6=10.
Regulator

ET1

a monolithic

precision voltage

reference

regulator.

amplifier,

integrated
It

consists

error amplifier,

circuit
of

that

used

temperature=-compensated

series-pass

power

transistor,

and the output circuit requifed to drive the external transistors.
In

addition to E1,

the regulator

circuit includes

pass

transistor

.sz premdrivers 03 and Q4, and level shifter Q5. Zener diode D2 is
used with Q5 and R2
shifter?®?®;
of Q5.

This

most of
is

to provide
the

input voltage

necessary

that required for E1

+15V for E1.

since

operation.

the

absorbed

used
across

raw input voltage

This

+415V input is

¢¢level

the collector-emitter

is well

above

supplied while still

retaining the ability to switch pass transistor Q2 on or off by drawing
current down through the emitter of

The output circuit is

standard

Q5.

for most switching requlators

and

consists of ¢¢free=wheeling®® diode D5, choke coil L1, and output

capacitors C8 and C9. These components make up the regulator output
filter. Free wheeiing diode D5 is used to clamp the emitter of Q2 to
grouhd when Q2 shuts off, thus providing a discharge path for L1,

In operation,

Q2 is

turned on and off generating a square wave of

FREQUENCY
V+

COMPENSATION

INVERTING
INPUT
VREF o-

SERIES PASS
TRANSISTOR

ERR

—

oV ouT

NONINVERTING o
INPUT

V__

CURRENT

LIMIT

SENSE
11-1331

Figure

6-10

Simplified

Diagraof
m Precision Voltage
6=-30A

Regulator

voltage which is applied.across D5 at the input of
(11,

device,
at

the

and

C9).

regulation.

on and

increases.

off

one

may

fixed

Defined

averaging

upper

cycle

on and

L1.

the

varied

sensed

and

the

lower

conduction

controlled,

and

fed

reference voltage.
output
limits

thus

back

turns

voltage
for

the

Q2,

the

supplying

where

pass

level

transistor
decreases

output

are

+4.95V,

operation

the

high voltage

output

requlator

operates

(approximately

already

+5V

+30V)

level,

follows:

applied

constant

then

+25V would be present acrdés L1. This constant dc voltage causes a
linear

ramp

output

capacitors

causing

the

output,

which

shuts

off

current
C8

output
is

and

bukld
C9

level

off,

through

absorb

(+5V

this

and

can

are used
be

turned

Conversely,

decrease,
reached

once

this

reaches

and

the

increase

the

and

off

turned

a predetermined

causing E1

turn

emitter

and

on which

the

same

current

time,

and

increase.

approximately

voltage,

When

the

+5.05V,

clamped

ground.

and the load. Pre=drivers Q3
gain

relatively

off

value

point)

effective
a

L1.

changing

monitored

turning

L1 discharges into capacitors C8, C9,

basically only

the period

to whether

+5.05V and

full

voltage

according

turned

across
st

voltage

compared with

approximately

circuit

By varying

The output

terminal.

(average)

During

type

and the square wave of voltage appears as an average voltage
output

~output

This

the LC filter

Q2 to

short

period

ensure
of

veoltage begins

apprroximatelv

+4.95V will be

turn

causes

that

time,

output

the

conduct,

beginning another

cycle

of operation.

Thus, a ripple voltage is superimposed on the output and is detected
as predetermined maximum (+5305V) and minimum (+4.95V) values by E1.
When +5.05V is

turns

Q2 on,

®*ripple

reached,

This

turns

type of

regulator.®®

circuit

off

and

action

when

+4.95V

reached,

also referred

to as

6.5.2.2

+5V Overcurrent Sensing Circuit of the H744

The overcurrent sensing circuit consists of:

Q1} R3 through R6, R25,

R26, Q7, and C4. Transistor Q1 ié normally not conducting; however,
if the output exceeds 30A,

the forward Voltage across R4 is sufficient

to turn Q1 on, causing C4 té begin charging. When C4 reaches a value
equal

biased

the

off,

voltage

turning

the

pass

anode

gate

transistor

Q7,

off.

turns

Thus,

the

and

output voltage

is decreased as required to ensure that the butput current is maintained
below

The

35A

(approximately)

regbulator

condition

continues

removed.

and

the

regulator

oscillate

this

¢‘short

new mode

circuit®®

protected.

until

overload

the

6.5.2.3

+5V Overvoltage Crowbar Cirdfiit of the H744

The‘overvoltége crowbar circuit consists of the following components:
Zener diode D1, silicon-controlled rectifier (SCR) D7, D8, R22, R23,
C7,

and

Q6.

Under normal conditions,
ground

because

the voltage across

it to conduct.
As the

and

the trigger input to the SCR

the voltage drop

+5V line

across

Zener

dicde

approaches

resistor R23

6V,

Zener

draws

gate

(D7)

too

is at

small

diode D3

cause

conducts

current and

triggers

the SCR. The SCR shorts the +5V line to ground through resistor R21,
which

capacitors

current-limiting resistor.
discharge.

The SCR remains

on until

the

6.5.3

Two

H745

=15V Regulator

-15V reqgulators

are

includéd

the PDP-11/40

Power

System.

Operation of the H745 is basically the éame as that of the +5V
regulator. The H745 schematic is shown in drawing C-CS-H745-0-1. Input
power
and

(20 to 30'Vac)

applied

the

a variable

resistor R1.
overcurrent

ST,

is taken from the secondary of transformer T1

full-wave

Vdc

bridge

rectifier

(d1).

and

applied

across

The

output

capacitor

and

The following paragraphs discuss the regulator\circuit,
sensing

circuit,

and

the

overvoltage

crowbar

circuit.

6.5.3.1

=15V Regulator

Circuit of

the H745

Reqfilator operation is almost identical to that of the 45V regulator;

however, the +15V input that is‘required for operation of E1 is
derived

externally and

applied across

inverting and non-inverting

the polarities
05,

inputs

to E1

the various components

which is used as a

level

shifter,

capacitor
are

to E1

reversed.

are reversed.

and

the

In addition,

For

example,

an NPN transistor on

the 45V

re@ulator but a PNP is required on the -15V regulator to allow the
requlator

to operate below ground

(at

Under normal operating conditions,
linear regulator E1
E1.

regulator operation centers around

transistor Q2,

which is

controlled by

Predetermined output voltage limits are

=-14.85V

(minimum)

-15.15V

(maximum). When the output reaches

turning Q2 off,

reaches

and pass

-15V).

-14.85V,

and L1

discharges

conducts,

into C8

causing Q2

[0)

output voltage.

=-15.15V,
and C9%.

and

shuts off,

When the output

to turn on,

increasing the

6.5.3.2

=15V Overcurrent

The

=15V

regulator

the

same

components

the

Sensing

overcurrent
as

=15V regulator.

the

45V

Circuit

sensing

the

circuit

requlator

Transistor

H745

except

basically made

normally

not

NPN

transistor

conducting;

however, once the output exéeeds 15A, Q1 turns on and C3 charges. When
C3

reaches

the

same

value

the

anode

gate

Q7,

biased

off,

which turns Q2 off,

thereby stopping‘current flow and turning the

-15V

Thus,

regulator

off.

the

requlator

short-circuit

protected.

6.5.3.3

=15V

Overvoltage

Crowbar

Circuit

the

H745

When SCR D5 is fired, the =15V output is pulled up to ground and latched
at ground

slope

until

the

sequencing,

input

+15V
if

power,

line

desired.

can be

the

used

415V

input

trip

the

removed.

crowbar

for

negative

power-down

6.5.4

DC Power

Distribution

of dc

power

from

the basic

PDP11/4O

power

supply

Shown on the cabling diagram (Sheet 3) of the BASIC ASS°YV (11/40)
print
the

(D-VA-11/40-0-0).

various

with

H744

further

and

panel

defined

and

HARNESS,

the

power

H745

cabling

(E-IA-70008754-00)

regulator

is effected
to

power

cabling

distribution

the individual

svstem units.

from

the requlators

POWER

Distribution

the

prints:

(WIRE

LIST),

distribution

panel

the

power

POWER HARNESS

the

system

distribution

The

units

panel

The cable

(11/40),

K-WL-7008784-0-1.

from

are

D-IC-IV40-0-2

cables

from

diverse,

and

relate to the power interconnection technique on the system units.
Detailed

information

backpanel

and

The

types

for

MF11-L

for

the

coprnections

backpanel,

both

Sheet

the

basic

the

provided

cable

print
the

noted

D-VA-11/40-0-0

respective

units

are

cable

requiring

the

with

G772

cable.

The

distribution panel

details

drawings.

D-IA-7009177-0~-0

distribution

results

connection

from

BASIC

on connection

Connection

module

power

the

ASS°Y

DD11

provided

PDP11/40.

(11/40),

Sheet
type

KD11-A

and

system

the

regulatqrs

certain

requlators

driving

the

power

certain

connectors. Limitations, therefore, exist on the amount of power on
a

connector

and

the

number

a representation of

connectors

available.

Fiqure

the distribution panel with usage

6-11

(KD11-A,

and source (H744°s and H745°’s per slot assignment in the H742 bulk
power

supply).

MF11-L)

Power is supplied to three groups of connectors on J1, J2 and J3,
J4 and J5, J6, respectively. Each of these input connectors have

output connectors: J1, J2 ahve 1, 2 and 3; J3, J4 have 4, 5 and 6;
and J5,

J6 have 7,

8 and 9.

Connectors J1, J2 receive powér from the +5V regulator of SLOT A

and the‘=15v regulator of SLOT E. All of this power is committed
to the KD11-A processor and the MF11-6 memory. Note that this

happens with only two of the three distribution conneétors being
used, 1 and 3. The cable from 3 is a joint cable, this portion from
3 suuplying the MF11-6 with =15V power.

Connectors J3, J4 receive power from the 45V regulator of SLOT B and
the -15V regulator of SLOT D. Note that only two distribution

connectors, 5 and 6, are available for expansion use; connector 4 is

already used to provide'+5v power (A) to the basic MF11-6. The

+5V power left for connectors 5 and 6 is reduced by that amount;

the -15V power must be shared with any further expansion logic from
connector

Connectors J5, J6 receive power from the optional +5V regulator of
SLOT C and the already mentioned -15V requlator of SLOT D. Three

distribution connectors 7, 8 and 9 are available but care must be

used to avoid overloading the =15V requlator also used for the J3, J4
connectors. Note that expansion bevond two additional single system

units réquire the option +5V regulator of SLOT C due to distribution
connection limitation. The first two svstem units use up connectors

and

the

J5,

additional
J6

units

connector

require

group.

The

connector

optional
+5

(and

regulator

is provided with logics origianally»ordered with
separately

ordered

for

add

)

must

therefore

situations.

power)

SILOT

the PDP11/40;

from

-{15V@I0A,SLOT D
AL

SUPPLY

+5V @254,

+5V@25A,SLOTC

-15V@ 10A,SLOT E

(REGULATOR)

+5V @ 25A,SLOT A

SLOT B

(OPTIONAL)

(

POWER

DISTRIBUTION

KD11-A

+5V @ 25A

-15V@
1A

-5V @ 9A

M
MFi1-L

J3 |

Js | | ue

+5V

’

+15V
@ .3A
11-1574

Figure

6=11

6=41A

6.5.5

For

Maintenance

the most part,

consists of

Power

System

maintenance of

the power

replacing defective modules,

details on regulator operation presented
6.5.3 are

units

for

theory of

operation

(see paragraph 7.5).

replacement,

system at

such as

the

field

the regulators.

in paragraphs

and off-line repair

6.5.1
of

level

The

through

failed

With Maintenance consisting of module

the major maintenance

effort consists
of failure

isolation.

Table 6-4 lists a procedure that can be followed as a guideline to
assist in

locating

defective

components.

CAUTION

Because

there

regulators

are

two

+5V

and

the PDP-11/40

two

-15V

System,

common troubleshootihg technique would
be to swap an operéting requlator with
a

faulty regulator.

first check

regulator

prevent damage

the

the event the fault

supply.

this

is done,

input voltages
second

lies

regulator

the power

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GENERAL

MAINTENANCE

7.1

SCOPE

This

chapter

System

and

system

power

provides

general

includes:

Maintenance

maintenance

preventive

checks,

and

information

power

information

maintenance

supply

the

for

the

mechanical

PDP=-11/40

assemblies,

maintenance.

processor

and

memory

components of the bhasic PDP-11/40 Systém is presented in the
associated

requires

maintenance

not

only

the

manuals.

Maintenance

Unibus

associated maintenance manual,

peripherals

but

also

" understanding of Unibus operation.

addition

processor,

the

memory,

maintenance
and

information

peripherals

significant maintenance

information

programs

The

detecting
should

documentation.

and

include

isolating
their

diagnostic

machine

regular

manuals

faults

use.

contained
of

the

PDP=-11/40,

available

programs

are

and

the diagnostic
a

Preventive

major

tool

maintenance

for

7.2

OVERALL MAINTENANCE

Maintenance

knowledge

ability
means

This

the PDP-11/40

proper

to repair

all but

assemblies

procedures.

This

maintenance

starting point

the

and

error

an error

condition,

the preventive maintenance
for

and

condition.

the relatively

section outlines

to have

operation,

isolate

the PDP-11/40.

System requires:

hardware

to detect and

true for

mechanical

TECHNIQUES

techniques

Note,

however,

knowledgeab

and

simple
for

procedures
power

for

check-out

performing

that

the

essential

able

service personnel.

7.2.1

Knowledge

Proper

Training

courses

and

machine

hardware

operation

and

individual

The

training

device

courses

Hardware

PDP-11/40

Options

Other
System

courses

are

Software,

these

and

available

for

information

programming,

PDP-11/40

Familiarization

svstems,

(10

System

include:

days)

Maintenance
(5 days)

days)

available

Paper

and

provide

the

PDP=-11

other

Digital Account

documentation

available

the

Operation

levels.

PDP-11/40

Interfacing

and

Hardware

Resource

PDP-11

Tape

Software,

Timesharing

courses

Representative

System

available

from

the

Disk

Operating

Software.

from

Digital

Information

either

the

Education Centers.

Documentation pertinent to the PDP-11/40 System includes documents
produced

specifically

on programming
are

listed

and

for

Unibus

in Table

1-2

the

PDP-11/40,

interfacing.
this

and

common

All of

PDP-11

documents

the relevent documents

manual.

A special effort has been expénded in production of documents
relating

(KE11=-E,

KET11-F,

formats,

tables

notations.

the

These

PDP-11/40
and
and
are

processor

KT11-D).
notes

provided

(KD11-A)

Innovations
the
to

prints,

and

processor

include:
and

facilitate

wire

print
list

initial

options
set

learning

but,

more importantly,

to provide instant reminders of specific details

during maintenance.

Information describing the print sets appears

in the processor and options maintenance manuals.

7.2.2

Detection

Malfunctioning
or

programs.

with

by MainDEC

Isolation

hardware

peripheral

software

and

the

periodic

failure

programs

Isolation of

the

maintenance

repair

This

can

Condition

occur

operation

occurs

with

either

with

various

system

software

customer’®s

MainDEC

software,

failure

svstem

diagnostic

verification

suggested.

specific
and

Error

normally indicated

malfunctions.

the

failure

reason

for

the

most difficult

trained

service

aspect

personnel.

Operatioh of MainDEC diagnostic programs can isolate the failure to
a

specific

device

operation

but

knowledge

program

operation

and documentatioh is necessary. The modular nature of the Unibus, with
its

separate

peripherals,

knowledge of Unibus
essential.
of

Often,

proper machine

manuals

device

may

also

specifications

however,

help

and

isolate

failures,

but

peripheral overation is

error

detection

reduced

operation with

detection

discrepancies.

operation

clear,

with

annotated

knowledge

prints,

Detailed

provide

information on operatibn, Detection of discrepancies requires
experience

The

level

regulator

and

expertise.

fault

units

isolation

such

the

H744

important.

H745

are

the

power

replaced
if

supply,

their

output voltages are in error;

the circuit board of the H742 unit

is replaced if the AC LO or DC 1.0 control signals are in error.

Repair procedures for the replaced units are given in paragraph
7.5.2. Replacement of KD11-A processor modules is suggested for

situations requiring minimum down time. Experienced service
personnel,

however, may find integrated circuit

(IC)

replacement a

practical alternative to the cost or transportation of modules.

7.2.3

Means

The method
the

level

of
of

Repairing

repairing
fault

the

Error

error

isolation

Condition

condition

mentioned

directly

the

paragranvh.

I1f, for example, fault isolation;afid repair is to be at the IC
level,
be

then

the

available.

parts

Suitable

identified
repair

and

the

machine

rework

documentation must

techniques

must

followed to avoid equipment damage. If modulé or sub assembly level
of

fault

available.

for

processor

isolation

and

Spare
and

repair

used,

part

kits

are

available

SP11-PD

for

the

power

these

units must

for

the

PDP-11/40

supply)

and

the

(SP11-KP

various

Unibus devices. Repair is normally at this level when down time is
critical

Verification

when

repair

f'@:@"’% n

MainDEC diagnostic

large

number

any

programs.

level

machines

made

involved.

running

the

aporopriate

7.2.4

Digital Field

Service

The present state-of-the-art

in complex computer

qualified

Installation and

service

service personnel.

are provided by

such personnel

systems requires

90-day warranty

from Digital Field

Service.

These people are trained both in basié PDP-11/40 components (processor,

console,

‘

and memory)

and

in the peripherals

that may be placed on

the Unibué, Material support exists both at the IC level (directly
equivalent parts)

and at the module and subassembly level.

Digital Field Service support may be continued beyond the warranty

period with a Digital Service Agreement.
programs are available.

Total equipment maintenance

Details of this service may be obtained

from the Digital Account Representative at the local Field Service
Office.

7.3

MAINTENANCE

EQUIPMENT

Maintenance procedures

(or equivalent)

REQUIRED

for the PDP-11/40 require

listed in Table 7-1.

the standard equipment

Especially important in analyzing

operation of the processor, or processor options, is the KMI11 option
consisting of W130 and W131 modules and associated overlays.
the KM11 maintenance displays

and switches

Use of

is covered in the processor

and processor options maintenance manuals. The module extender board
(W900)

is also an important diagnostic tool and is discussed in

paragraph

7.4.

Table

7-1

Maintenance Equipment Required

Egquipment

or Tool

Manufacturer

Oscilloscope

Tektronix

Model,

Type,

or Part No.

29-13510

Gardner-Denver 505 244-475 | 29-18387

(Cat.

Hand Wrap Tool

4453

Volt/Ohmmeter (VOM) Triplett

Unwrapping Tool

DEC Part No.

H812A)

Gardner -Denver A-20557-29
(Cat.

29-18301

H811A)

29-13460

Diagonal Cutters

Utica

47 =4

Diagonal Cutters

Utica

466-4 (modified) 29-19551

Miniature Needle

Utica

23-4-1/2

29-13462

Wire Strippers

Millers

101S

29-13467

Solder Extractor

. Solder Pullit

Standard

29-13467

Nose Pliers

Table

7-1

(Cont)

Maintenance Equipment Required

Model,

Equipment
or

Tool

Soldering

Iron

Manufacturer

Paragon

615

Type,

Part

DEC

Iron Tip

Paragon

Part

No.

29-13452

(IC

(30 watts)

Soldering

No.

type head)

605

29-19333

16=-pin IC Clip

Inc.

AP923700

29=-10246

24-pin IC Clip

Inc.

AP923714

29-19556

KM11=-A

**W130,W131

KM11

Option

DEC

Maintenance Modules

Maintenance Card

Overlay

559081-0=-12

DEC

5509081-0-13

DEC

W00

(KD11-2)

Maintenance Card

Overlay

DEC

(KE11-E,F,

KT11-D)

Module Extender
Board

7-11

Table

7-1

(Cont)

Maintenance Equipment Required

Model, Type,

Equipment

or Tool

Manufacturer

or Part No.

DEC Part No.
£

Regulator Extender

DEC

70-08850=-0-1

Cable

Tektronix Type 453 Oscilloscope is adequate for most test

procedures; Type 454 (or equivalent) may be reguired for
some measurements.

% %

w133 is a dual version of W130. It provides the drivers for

two W?B?‘maintenance cards. The 130 may still be used;

however, two units would be required for simultaneous

monitoring of the basic‘processor and options. Two W131s
are required for simultaneous monitoring in any case.

7-12

7.4

PREVENTIVE

Preventive

MAINTENANCE

maintenance

consists

specific

tasks

performed

periodically; its major purpose is to prevent future failures caused
by minor

damage

progressive

preventive maintenance

log

entries made

over

possible

according

extended

period

component

projected module

book

time,

tasks

can be

due

aging.

established

schedule.

resulting

component

Preventive maintenance

should

regular

failures

deterioration

very

and

This

data,

useful

in module

A
necessary

compiled

anticipating

replacement

on a

reliability basis.

consist

of mechanical

and

electrical

checks. All maintenance schedules shbuld be established according
to

conditions

environmental

the

particular

conditions,

installation

usage,

etc.

site

that

Mechanical

are dependent

checks

should

performed as often as re§uired to allow the fans and air filters to
function efficiently. All other pfeventive maintenance tasks should
be

performed

requirements.
or

every

regular

schedule

determined

A recommended schedule

three months,

whichever

comes

everv
first.

reliability

1000

operation

hours

7.4.1

Physical Checks

The following procedure contains
the necessary steps required for

mechanical checks and physical care of the PDP-11/40¢

Step

Procedure

Clean the exterior
vacuum cleaner

flammable,

Check

all

clean

fans

ensure

that

clean

the

lower

fan housings,

located

Remove

the

Inspect all wiring
deterioration,
Repair

replace

Inspect the

top of

fans,

they

air

are

vents

upper
the

and

not

obstructed

the upper

and

lower regqulator

filters

strain,

for cuts,

the

breaks,

and mechanical

any defective

following

non-

cabinet

the cabinet.

and cables

wiring

for mechanical

lamp assemblies, jacks,
regulators,

and

and wash

kinks,

with

solvent.

Vacuum

logic

the cabinet with a

cloth moistened

in any way.

fan,

interior of

non-corrosive

fan housings.

and

fraying,

security.

cable

security:

covering.

LED or

connectors, switches, power supply

capacitors,

required.

7-14

etc.

Tighten

or replace

Inspect

module

all

module

securely

mounting

seated

locking-releasing mechanism

Inspect

power

discoloration

Inspect module

supply

its

capacitors

and replace

guides

panels

for

ensure

connector

that

and

each

the

functioning properly,

for

leaks,

bulges,

required.

wear,

damage,

and

secure

fastening.

7.4.2

Electrical Checks

The following

checks

and Adjustments

should

installed and whenever

be made when

a new component

system

(such as

module,

interface module,

an additional regulator,
etc.).

‘

the

system

first

installed

the

processor

option
5

7.4.2.1

Voltage Regulator Checks — Perform the power

checks
under

listed
normal

peak-to-peak

has

Table

load

ripple

lamp.

tolerance,

adjusted

to meet

Use

content

a VOM

Use

the
as

regulator

required

adjustment

all

potentiometer

adjust

non~conducting

7-2.

conditions.

adjustment

indicator

Output

the

outputs.

just

output voltages
to measure

Each

below

voltage

the

not within

the

obtain

acceptable

output

remove

voltage
and

reculator

replace

the

Checks

Ripple
REgulator

H744

+5V

Voltage

Peak-to-Peak

Regulator

+5.0 volts

0.15

volts

Regqulator

+5.0 volts

0.15

volts

Regulator,

+5.0 volts

0.15

volts

-15.0

0.45

volts

(slot
A)

H744

{15V

(slot B)

H744

45V

optionsl

(slot C)

H745

=15V

Regulator

{slot

volts

7=-17

regulator

specified
(use

cannot

reculator.

7-2

Voltage

the

output

outout

Table

check

oscilloscope

located

tool).

specifications,

system

Table

7-2

(Cont)

DC Output Voltage

Checks

Ripple
Regulator

Voltage

Peak-to-Peak

H745

=15.0 volts

0.45

+8.0

0.24 volts

- 15V Regqulator

wvolts

(slot E)

H742

Power

Supply

(6.8

9.2)

7-18

7.4.2.2
on

the

860
860

Power

Control

Operate

to make

sure

the’REMOTE/OFF/LOCAL
power

turned
on

switch

the

LOCAL position and disconnected in the OFF position. Return S1 to
the

LOCAL

(single
other

position

box)

after

PDP11/40

connections.

performing

present.

this

See

test

section

only

6.4

basic

this manual

for

7.3.2.3

Power

Connector

REceptacles

— Test the

output voltage

at each plug to be sure 115- or 230-volt ac power is available.

7.4.3

7.4.3.1

ASR33

Teletype

Preventive Maintenance

items during

system preventive

Checks

— Check

the

following ASR33

maintenance:

Check distributor plates for deposits.

Check

platen

Check wires

and

typewheel

for

deposits.

around distributor area

for

secure

mechanical and electrical connections.

Check the print hammer and replace if worn.

Rotate
is

the mainshaft manually

free,

If movement

and check

restricted,

that movement

check

clutch

assemblies,.

Check typewheel

pinion racks,

and gears

for dirt.

7.4.3.2

Lubrication — Use a 50-50 mixture of 20 weight, non-detergent

o0il and STP oil additive for viscosity improvement to perform the
following lubrication, except where otherwise noted:

0il all clutchwassembliesg

0il all felts until saturated.

Lightly oil all pivot points.

0il drive motor at both lubrication points provided.

0il print carriage bearings.

0il main shaft‘bearinqs°

0il bearing on funétion shaft.

0il the eye en@s of all springs.
A

0il the typewheel pinion and gear.

0il repeat mechanism in keyboard assembly.

Clean the dashpot assembly and lubricate it with
graphite dust.

NOTE
Do

Grease

not

the

put

teeth

o0il

the

dashpot.

spacing

ratchet.

7.4.4

LLA30 DECwriter

7.4.4.1

Preventive

included

the

WW}

Maintenance

sytem,

Schedule

supplied

- When

with

the

LA30

a maintenance

that contains detailed preventive maintenance procedures.
to

cleaned,

listed

Printing

the

inspected,

following

Interval

and

replaced

DECwriter

reqular

manual

The

schedule

items
are

chart:

Clean

Inspect

Replace

(Hours)

300-500

Ribbon

Idlers

(Para.

5.2)

Ribbon

Tension

Head

Assy

(Para.5.4.2)

2000

Ribbon

Motors

(Para.

5.2)

Carriage

Ribbon

Tension

(Para.

5.4.6)

Assy

Round Shaft
(Para.
3.

5.2)

Ventilating
Blades,

essary

{(Para.

5.2)

Fan
nec-

Printing Interval Clean

Inspect

Replace

(Hours)

Linkage

Pins,

Ratchet

and

Pawl

Mechanism

(Para.

5.2)

NOTE

Paragraphs

to
the

referenced

applicable
LA30

paragraphs

DECwriter

this

chart

in Chapter

Maintenance

refer

Manual.

7.4.4.2

Cleaning Procedures - Aiways use a clean, lint-free cloth

to wipe off

outside

dust or

from inside

the unit.

{(The

ink

commercial

furniture or

automotive

wax

to protect

the cover.

Dust the

paper

ink

surfaces

cover

and

lightly-oiled

and wipe

cloth

to remove

oil-base).

the keyboard

any

Use

the outside

clean whenever

replenished.

Do not attempt

to clean

the print

head

it after 300-500 hours

of operation.

described

5.4.2 of

in Paragraph

assembly;

rather,

replace

The replacement procedure

1is

the LA30 DECwriter maintenance

Manual. At the time it is replaced, wipe the ribbon idlers clean
with an oiled

After

2000

cloth.

hours of operation,

remove

each ribbon motor,

described in Paragraph 5.4.5 of the LA30 manual. Apply a light
0il

to the lower bearing felt.

At this

time,

lubricate the carriage

assembly round shaft, DEC part number 74-8656-1/2. Spray a light
coating of Molykote

557

along the entire

shaft and

with a dry cloth to leave a thin coating of

sipe lightly

lubricant on the shaft.

NOTE

S
Do

not attempt

clean

&£ vacuum=-clean

the control box assembly.
better

If necessary,

after

It will

function

left alone.

2000 hours

of operation remove

wipe the blades clean with an oiled cloth.

The

the fan and

fan motor does

(wf

not

require

the

paper

and

scheduled

2000-hour
advance

freedom

However,

environment,

lubrication.

interval

mechanism

movement.

the

terminal

preventive

linkage

Normally,

and

maintenance,
pivot

pins

no maintenance

extreme

ambient

these pins will require lubrication.

check

for

the

grease

required.

temperature

If so, disassemble

the linkagesvand apply Molykote B2KR grease to all bearing surfaces.

NOTE

The

two

remain

dark

free

green

the mechanism

0il
to

nvlon

rollers

grease

function

must

allow

properly.

7.4.5

PCO05 High-Speed Paper=Tape Reader/Punch (optioq}

The PC05 High-Speed Paper-Tape Reader/Punch includes a ROYTRON

500 Series Reader /Punch mechanism. Complete lubrication and
preventive maintenance instructions for this mechanism are contained

in the Preventive Maintenance Section of the Roytron Maintenance

Manual, which is supplied with the PC05.

In addition to the preventive

maintenance procedures listed in that manual,

perform the following

mechanical and electrical checks as part of the system preventive
maintenance procedure.

7.4.5.1

Mechanical

Checks

Inspect

Step

the

PC05

follows:

condition

the

Procedure

Visually

inspect

the

PC05,

inside

general

tape

reader.

Clean
or

the
clean

cloth

that

non-flammable

solvent.

Lubricate

chassis

the

oil.

Inspect

all

Wipe off

has

out,
been

using

a vacuum cleaner

moistened

with

slide mechanism with a
excess

light

oil.

machine

and

wiring

defective

Check

that

LINE

switch

depressor

replace

any defective wiring

cables.

the

READER FEED

switch,

light condensor,

arm,

hold-down

circuit modules,
resistor

and

assembly

tape

READER

ON/OFF

phototransistor

bracket,

feed motor,

are mechanically

all

assembly,

connectors

front

cover,

secure.

and

7.4.5.2
tests

Electrical Checks - Perform power supply output

listed in the following chart:

Output

Pin Number

Tolerance

Ripple
(peak~-to=-peak V)

+5 volts

A1A2

f 0.25 volts

0.1 volts

-15 volts

A1B2"

7 1.0 volts

0.1 volts

-18 volts

B8V2

+ 2.0 volts

1.0 volts

-36 volts

A8V2

+4.0 volts

1.0 volts

Use a VOM to measure output voltage and an oscilloscope to check
ripple voltage. The +5- and -15-volt outputs are adjustable;

)

the -18~ and -36-volt outputs are not adjustable.

7.5

The

USE

W900

board

MODULE

module

that

EXTENDERS

extender

provides

is
a

double-height,

one-to-one

connections

multi-layer

etch

between module

connectors and corresponding processor backplane connector slots.
Thus,

three

W900

module

extenders

can

used

extend

PDP=-11/40

hex-size module from thé processor backplane to provide access
and

operating

discrete

components

for

test

purposes

than

under active

conditions.

CAUTION
Do

not

module
Note

attempt

that

time

the

adjusted

the modules

extend

while

performing

processor

clock

allow

one

tests.

may

have

operation

with

extended.

]

ICs

7.6

PDP-11/40

POWER SYSTEM MAINTENANCE

Syétem maintenance of the PDP11/40 power system consists of
replacement of the modular elements. Offline repair is then
necessary for the replaced element,
‘sectione

and is presented in this

Detailed circuit operation is presented in paragraph 6.5

and is necessary for background to the troubleshooting procedures
of

this

section.

7.6.1

should

contained
in

schematic
user

power
to

the

Chapter

and

should

first

the

this

interconnecting
able

distribution
dc

read

inputs

trace

circuits
each

description
By

diagrams

the

through

from

logic

manual.

the

prirmary

module.

user

The

Circuit Tracing

the

power

system

referring

power

the

set,kthe

control

and

input connectors

7.6.2

Voltage

Figure

7-1

shows

fabricated

from

loads used

load

other

Requlator

than

test the

those

The voltage

a recommended
standard

conditions.

(0Off-Line

bench

parts.

test

also

Repair)

source

shows

that

the

can

bench

test

voltage

regulator outputs

under various

additional

test equipment or

tools

listed

regulator

to be removed

Tests

in Table

extender

from its

required

7-1.

cable

assigned

are

allows

slot on

a voltage

the H742

regulator

power supply

provide access for test purposes. This cable only supplies.ac
input power

the voltage regulator.

An additional voltage

regulator befichvtest source and load fixture can be fabricated
from standard

tests under
schematic

DEC parts

the various

load conditions required.

and part numbers required

fixture are

shown in Figure

Whenever a

power

regulator,

examine

means

to perform troubleshooting and performance

internal

that the main pass

drivers

(03,

Q4)

this

optional

test

7-1.

system fault has
the

to build

The circuit

been

isolated

fuse F1.

transistor Q2,

short circuited.

using the following procedure:

7-34

A blown

to a voltage
fuse

and/or one of

This

can be

usually

its

checked by

Step

Procedure

Check
and

for

damage

scorching

and

Q4.

the

pass

fault may

the

first driver

short

base-emitter

the

etched

transistor

the

and

bleeder

board

drivers

caused

(Q4).

Check

the

are

continuous

level

resistors
area

not
base

shifter

faulty,
drive

for

circuit.

Check the resistance to éround at the input to the
precision voltage

regulator

integrated

(pins

determine

circuit

and

holding

resistance

the

ground

regulator

in Table

7-3.

Use

for

VOM

terminals

and

mounting

TO-3

located
a

regulator

check

ground.

short

for

each

circuit

Possible

external

conduction.

listed

components

circuit EfT

the

connecting

the

VOM

mounting

screw

short

The

approximate

voltage

between

fuse

short

circuits

involving

heat

sink may

leads
the

between

end

the

TO-€
heat

cases
sink.

and

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Table 7-3
Regulator Resistance to Ground

Regulator

Type

H744

H745

Inverting

(-)

Non-Inverting (%)

Input at Pin 4

Input at Pin 5

20K

1.5K

A voltage regulator that provides no output, or a low output,

without causing fuse F1 to blow, probably has a short circuit
in the output. This can be checked by the following procedure:

NOTE

An activated crowbard, or a short-circuited
output,

in an otherwise properly operating

voltage regulator does not cause F1

Step

to blow.

Procedure

If fuse F1 is not blown, and the area of etched
circuit around the ac input to the bridge circuit
is not damaged, it is safe to apply an ac input to

the voltage regulator to determine if the regulator

is overloaded by a short circuit across the output.

Step

Procedure

Connect
source

the
and

audible

the

advance

tone

output

adjustment

the

short

voltage

fully

regulator

component

the

variac

indicates

circuits

regulator

near

CCW

and

failure

the

about

overload

volts,

the

output
crowbar

test
volts.

the voltage

test.

overloaded,

the
the

bench

conditions.

turn

repeat

appears

across

and

check

for

circuit.

NOTE

H744

revision G modules

contain

additional

SCR in the crowbar circuit to pull down the
+15V control

voltage

off

power

until

ssoverload

failure

faulty

symptoms,

whistle’’®

conditions

voltage

and

regulator
then

Step

not

some

does

perform

the

removed.
may

hold

the

not

Therefore,

IC drivers

heard

these

exhibit

following

the

under

modules.

any of

the

steps:

Procedure

Apply 115 Vac to the bench test source

(25 Vac at the

voltage regulator input) with no load on the
regulator

output.

Step

Procedure

Check for

30 Vdc across

Check for

415 Vdc at pin

regulator E1.

No voltage

that Zener diode D2

12 of precision voltage
at

this

(in the H744)

point could mean

has

failed.

Check for 6.8 to 7.5 Vdc at pin 7 of E1 with respect
to ground

filter capacitor Ct.

(pin

6).

If all output measurements
correct,

and

there

in the above steps

no output voltage,

are

then

pin 5 of E1

should be positive with respect to pin 4.

Pin 2 of E1

should be +0.6V with respect to pin 3.

If it is not, connect emitter and base of Q5
together.

If a 0.6V indication is

precision voltage regulator E1

then obtained,
not faulty and

the fault is probably caused by 05 or 04.

7.6.3

Voltage

Regulator

Test

After

a voltage

regulator

has

tested

with

the

bench

the

system.

Use

the

following

Repair)

been repaired,

source

recommended

before

bench

should

installing

test

loads

into

when

performing

the

appropriate

steps:

Step

test

(After

Connect

Procedure

the

repaired

voltage

regulator

source connector.

Set

voltage

adjustment

input

output

circuit

voltage

input). No

audible

full

CCW and

set

load

breaker

and

advance

indicated

(at

approximately

noise

should

variac

heard

zero.

until
60-80

under

Vac

no-load

conditions.

Advance

Make

certain

the

regulator.

Apply

variac

30%

remain

nearly

buzz

instability.

50%

130

Vac

return

connected

and

load.

output

constant.

harsh

and

The

115

soldered

before

voltage

clean

whistle may

hissing

sound

indicates

Check waveforms

shown

Vac.

should

heard.

possible

in Figure

7-2.

Procedure

Step

Apply

100%

load and set voltage adjustment for

output as

nominal

follows:

H744

+5.10 vdc

H745

-15.10 vdc

Apply 200%
frequency

load and check for a decrease
and

the

output voltage.

CAUTION

the output voltage does

noticeably

in the

not decrease

volt on H744;

on H745), do not attempt the
short-circuit

5 volts

following

test.

Short circuit the output. The regulator should continue
to operate at a low frequency, with a clean,

smooth

whistle and stable waveforms.

Increase the voltage adjustment and observe the output

voltage when the crowbar circuit fires. A sudden decrease

in frequency and output voltage should be observed.

H744

6.00

6.65V

H745

16.8

20.5V

The output voltage should be within the following ranges:

40V

3ov

Vout

50-200us

FULL LOAD

7
Vout —»
NOTE 2

P
NOTE

30 volt

level

doubles

in H746

shifts

with AC input voltage. This vaiue

(i.e.

60V).

Small

{20Hz

jitter

normal

NOTE 2:

Output ripple aond noise as follows:
H744

H745%

H746

RIPPLE (P to P) | 3% max.| 3% max. | 3% max}

NOISE (PEAK)
Measure

o |

2%typ. | 2%1typ.

|2%typ |OUTPUTS

|1%

noise with a short

1%
100§

terminated piece of foil

coax. Normal 10.1 scope probe will not give an accurate
noise

measurement.
14-1075

Figure

7-2

Typical

Voltage

Regulator

7=40A

Output

Waveforms

5
a

el Redis =il

DIGITAL EQUIPMENT C

MAYNARD, MASSACHU

£ 4

DIGITAL EQUIPMENT CORPORATION

MAYNARD, MASSACHUSETTS 01754