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XX-BD9E8-C3

2000

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Document:	MF11-LP Parity Control - M7259
Order Number:	XX-BD9E8-C3
Revision:
Pages:	3
Original Filename:	MF11-LP%20Parity%20Control%20-%20M7259.tif

OCR Text

;

ery of Digis Equipment Corperation and shan nor o
the basis for themanufacofture
sale-of s amout

NOTES:
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REF DESIGNATION

DESCRIPTION

FIRST USED ON OPTION MODEL

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PART NO.

PARTS LIST

ENRRNR
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oll &

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GND AND
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7 AND 14

DEC NO.

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NONE

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CORPORATION

TITLE

PARITY

CONTROL

M F || — L_ P

f25

SIZE|CODE
NUMBER
DICSIM7259 — @ —
\

TREV,
E

“THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE
PROPERTY OF DIGITAL EQUIPMENT CORPORATION AND

" DIGHAL EQUIPMENT CORPORATION"

BUS DIS L

PC2 CSRIS (1) H —={8881 \ I3
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NOTES:
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THE

ADDRESS

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OF THE CSR REGISTER IS LOCATED

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BUS A6 L

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PCl ER AIT H

IN PART A6 THE BASIS FOR ThIe MANORACTORE
R 2oLt

D | cg M7253=7—

—qE

BETWEEN 772|100 AND 772136, IT 1S SELECTED
WITH JUMPERS WI THRU W4, REMOVING A JUMPER
SELECTS A 'ONE" FOR THAT BIT POSITION,

—
-

PC2 +3V
:

¥ % THE R INPUTS ARE SELECTED WHEN THE SEL
INPUT GOES LOW.

4.7K

4.TK

47K

* W4

* W3

* W2

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GND
|

AD4

A@B?

REVISIONS

CHK |

CHANGENO.

AD2

AQ I f

| Rev.

‘

PARITY CONTROL-MFII-LP (PCI)|D [C3|M7259-0~|

w8
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SCALE

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NONE

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3

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[

]

[

]

;

;‘;g:)SER?rB{AW!NG AND SPECIFICATIONS, HEREIN, ARE THE
OF DIGITAL EQUIPMENT CORPORATION AND
SHALL NOT BE REPRODUCED OR COPIED OR USED IN WHOLE
OR IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE

.,{.. SV

PC2 B GEN
H OR ER Lo
o

PCl DI5 W ——pp

P8 INT BUS L

PA INT BUS L

PCI

Pcl DIzH —3p3

PCI DP9 H ————
D6
PCI Dpe H —'2{p7
PC2 B BIT GEN H——21D8

PC2 +3V

RI3

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7&_‘5,%

04} 5 =

PC2 PARLTY ERROR H

EI5 |

3|1
PCl

DP7 H——LIop

PCl DP6 H ——21D)

PCI D5 H ——2{D2
.

oDD

el D4
PCI DP3 H

1P >
D4
cvEnl2

PCi D¢2 H

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PCI MSYN H

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PC2 A GEN H ORER L

Pc2 A BIT GEN H ——21Dg

pRea MYt RULSEL

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@ =

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9|E25 K
8881

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Pe2 ERRORCLRINH L

pcz csri5(@) H

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PCI

INIT

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ERROR

PCl DP2 H

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ENABLE

]

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PC2 CSRY(

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(1)

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25K

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PC2 +3V

+5V

ENAB SEL
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s BT GEN N

DIP H N
" 05

0() L

PARITY ERROR

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e rp
2

o102

PC2

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H——%Ip4

DIt

Pdaz

PC2 CSR2 (B)H

| 1y

F3 (—=— PC2 BBIT GEN H

DI4 H——=DI

PCI DI3 H — 3102
'

15 |5 B2e6
I

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PClCl H

+_ SV

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Fe— pc2 csrR® @) H

L 32

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= 5%

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PC2 READ SEL H

Zud

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7T4HOLN

PC2 SSYN H

oe1Cl H

BUI

74p8\6
5 9‘

PC2 CLK CSR H

I
=

’

o
0

SSYN INT BUS L

PCI

) “T:-:fizéoi
113

o—H

RI6

Ml23

PC2 CLK

is| *9Pd—

Pc2 SSYNDLY@H

CSR

—

553

20K

56K

=
=

;___5

(

PCI INIT L

PC2 PARITY ERROR
(1) H
o

%
1]

- 4\'7‘/‘2

C38—‘L

22¢eF |
5%

PCI €l H—21

1 =3

PC2 PARITY ERROR () L -

#5 74060 .6

5
——E8 Iplz

428 e

774123

D@¢N§

T
ory

PC2 PARITY ER DLY @H

PCI INIT H

74_(’)2_

12 E31

—> 7492

_PC2 DATIP CLR PAUSE H

PC2 DATIP L —( E31 /4

REVISIONS

cHANGE NO.

I35 NS

FOR

MFI1-UP

BETWEEN

B@oUl

GOING

} VOLT OF THE RISE AND FALL..

% % THE 'B' INPUTS ARE SELECTED WHEN
THE

SEL INPUT

GOES

LOW,

Pc2 DATO L

cHK |

LOW TO PIN ADLS2 GOING HtGH»MEASURE AT

(avl]

51, DNTIP CLR PAUSE
|L e

EZ—% 4

ADRS H

THIS MUST BE SET FOR I125NS FOR MF[1-LP OR

,DATIP CLR PAUSE L —

CLK

NOTES::

PC2

AU
-

[ Rev.

[

TITLE

SIZE|CODE

NUMBER

PARITY CONTROL-MFII-LP (PC2)|p |CSIM7252-F
[scale

- .

N ONE

[SHEET

st |

]

[

|
T

REV.
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