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DEC-15-H2EB-D

2000

322 pages

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Document:	PDP-15 Module Manual
Order Number:	DEC-15-H2EB-D
Revision:
Pages:	322
Original Filename:	DEC-15-H2EB-D%20PDP-15%20Module%20Manual.pdf

OCR Text

Digital Equipment Corporation
Maynard, Massachusetts

PDP-15 Systems

Module Manual

DEC-lS-H2EB-D

PDP-15
MODULE MANUAL

DIGITAL

EQUIPMENT

CORPORATION • MAYNARD, MASSACHUSETTS

1st Edition July 1970
2nd Printing November 1970
3rd Printing {Rev} November 1972

The material in this manual is for informational purposes and is subject to change without
notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

PDP
FOCAL
COMPUTER LAB

PDP-15 FAMILY OF MANUALS

SOFTWARE

HARDWARE

INSTALLATION
MANUAL

ACCEPTANCE
TEST
PROCEDURES

OPERATORS
GUIDE

INTERFACE
MANUAL

UTILITY
PROGRAMS
MANUAL

...-.

MAN UFACTURERS
EQUIPMENT
MANUALS

MACRO -15

FORTRAN Ill:

FOCAL-15

8/15
TRANSLATOR

NOTE:
New manuals will be added
as they are developed.

15-0040

SYSTEMS REFERENCE MANUAL - Provides overview of PDP-IS hardware and software systems and
options, instruction repertoire, expansion features,
and descriptions of system peripherals.
(DEC-IS-BRZD)
USER'S HANDBOOK VOLUME 1, PROCESSORPrincipal guide to system hardware includes system
and subsystem features, functional descriptions,
machine-language programming considerations,
instruction repertoire, and system expansion data.
(DEC-IS-H2DC-D)

PDP-IS/40 DlSK-ORIENTED BACKGROUND/
FOREGROUND MONITOR SOFTWARE SYSTEM
- Describes Background/Foreground Monitor in
disk-oriented environment; programs include language, utility, and application types.
(DEC-IS-MR4A-D)
MAINTENANCE MANUAL VOLUME 1, PROCESSOR - Provides block diagram and functional theory
of operation of the processor logic; lists preventive
and corrective maintenance data. (DEC-IS-H2BB-D)
VOLUME 2, ENGINEERING DRAWINGS -Provides engineering drawings and signal glossary for
the basic processor and options. (DEC-IS-H2BB-D)

VOLUME 2, PERIPHERALS - Features functional
descriptions and programming considerations of
peripheral devices. (DEC-IS-H2DC-D)
OPERATOR'S GUIDE - Lists procedural data, including operator maintenance, for using the operator's console and the peripheral devices associated
with PDP-IS Systems. (DEC-IS-H2CB-D)

INST ALLA TION MANUAL - Provides power specifications, environmental considerations, cabling, and
other information pertinent to installing PDP-IS
Systems. (DEC-IS-H2AB-D)

PDP-IS/IO SYSTEM USER'S GUIDE - Features
COMPACT and Basic 1/0 Monitor operating procedures. (DEC-IS-GGIA-D)

ACCEPTANCE TEST PROCEDURES - Lists stepby-step procedures designed to insure optimum
PDP-IS Systems operation.

PDP-IS/20 SYSTEM USER'S GUIDE - Lists Advanced Monitor System operating procedures.
(DEC-IS-MG2B-D)

PDP-IS MODULE MANUAL - Provides characteristics, specifications, timing and functional descriptions
of modules used in PDP-IS Systems.
(DEC-IS-H2EB-D)

BACKGROUND/FOREGROUND MONITOR
SYSTEM USER'S GUIDE - Lists operating procedures for the DEC tape and disk-oriented Background/Foreground monitors. (DEC-lS-MG3A-D)

INTERFACE MANUAL - Provides information for
interfacing devices to a PDP-IS System.
(DEC-IS-HOAC-D)

PDP-IS/IO SOFTWARE SYSTEM - Describes COMPACT software system and Basic 1/0 Monitor
System. (DEC-IS-GR lA-D)

UTILITY PROGRAMS MANUAL - Provides utility
programs common to PDP-IS Monitor Systems.
(DEC-IS-YWZA-D)

PDP-IS/20/30/40 ADVANCED MONITOR SOFTWARE SYSTEM - Describes Advanced Monitor
System; programs include system monitor language,
utility, and application types; operation, core organization, and input/output operations within the
monitor environment are discussed.
(DEC-IS-MR2B-D)

MACRO-IS - Provides MACRO assembly language
for the PDP-IS. (DEC-IS-AMZA-D)
FORTRAN IV - Describes PDP-IS version of the
FORTRAN IV compiler language. (DEC-IS-KFZB-D)

PDP-IS/30 BACKGROUND/FOREGROUND
MONITOR SOFTWARE SYSTEM - Describes Background/Foreground Software System including the
associated language, utility, and applications program.
(DEC-IS-MR3A-D)

FOCAL-IS - Describes an algebraic interactive compiler level language developed by Digital Equipment
Corporation. (DEC-lS-KJZB-D)

List of Modules
Al24
A222
A40S
A607
A708
A877
G08S
GIOO
G222
G223
G28S
G286
G290
G613
G614
G681
G711
G77S
G821
G822
G823
G82S
G827
G829
G8S8
K303
MOO2
MIOI
MI03
MI04
Mill
MI12
MI13
MilS
MI17
MI19
MI21
MI27
MI29
MI33
MI3S
MI39
MI49
MIS9
MI61
MI62
MI64
MI82
MI91

Analog Multiplexer
Selectable Gain Amplifier
Sample and Hold Amplifier
lO-Bit D/A Converter, Single Buffered
Dual Voltage Regulator
Analog-to-Digital Converter
Disk Read Amplifier
Sense Amplifier and Inhibit Driver
Memory Selector
Read/Write Driver
Series Switch
Center Tap Selector
Writer Flip-Flop
X Diode Matrix
Y Diode Matrix
Track Matrix
Terminator Board
Indicator Panel
+SV Regulator
-6V Regulator
-24V Regulator
-24V Pass Element
Power Sequence Detector and Delays
Power Connector
Teletype@ Connector
Timer
Logic I Source
Bus Data Interface
Device Selector
I/O Bus Multiplexer
Inverters
NOR Gates
NAND Gates
NAND Gates
NAND Gates
NAND Gates
AND/NOR Gates
AND/NOR Gates
AND/NOR Gates
NAND Gates
NAND Gates
NAND Gates
NAND-Wired OR Matrix
4-Bit Arithmetic Logic Unit
Binary-to-Octal/Decimal Decoder
Parity Circuit
6-Bit Parallel Adder
Parity Circuit
Carry Look-Ahead Generator

~eletype is a registered trademark of Teletype Corporation.

List of Modules (Cont)
M205
M206
M207
M2ll
M2l2
M2l4
M216
M2l8
M2l9
M223
M226
M227
M238
M240
M242
M248
M302
M3ll
M3l2
M40l
M402
M420
M452
M500
M5l0
M5l5
M602
M606
M6ll
M6l7
M62l
M622
M627
M628
M632
M706
M707
M7l7
M770
M77l
M772
M773
M775
M776
M90l
M902
M904
M909
M910

D Flip-Flops
D Flip-Flops
Flip-Flop
Binary Up/Down Counter
6-Bit Left/Right Shift Register
Data Storage Register (6-Bit)
D Flip-Flops
MQ Register (9-Bit)
Step Counter and Control
MA and MB Register (4-Bit)
Register (7-Bit)
AC Shifter (9-Bit)
Synchronous Up/Down Counter
R-S Flip-Flops
J-K Flip-Flops
Right Shift Parallel Load Register
Dual Delay Multivibrator
Tapped Delay Lines
Delay Lines
Variable Clock
Photo Mod Clock
Phase-Lock Clock
Variable Clock
Converter-I/O Bus Receiver
I/O Bus Receiver
Real Time Clock
Pulse Amplifiers
Pulse Generators
High-Speed Power Inverters
Power NAND Gates
Data Bus Drivers
I/O Bus Drivers
NAND Power Amplifiers
Block-Bank Address Card
Converter-I/O Bus Driver
Teletype Receiver
Teletype Transmitter
Display Control VP 15
EAE Control
Internal lOT Decoder
Console Control No.1
Console Control No.2
Time State Generator
Reader Register
Flexprint@ Cable Connector
Terminator Card
Coaxial Cable Connector
Terminator Card
CP Terminator Card

List of Modules (Cont)
M911
M912
M91S
M1701
M1713
WOlD
W028
W076
W714
W8S0

Memory Bus CP Terminator Card
I/O Bus Connector
Console Cable Connector
Data Selector
16-to-l Data Selector
Clamped Loads
Cable Connector for Levels and Pulses
Teletype Connector
Switches
I/O Connector

vii

General Description

This manual provides descriptions of modules used in the PDP-IS System and its associated peripherals. A
schematic diagram is included with each module description. Parts location diagrams are supplied for those modules that have numerous discrete components.
DEC builds three series of compatible below-ground logic (the B-, R- and S-series), two series of compatible aboveground logic (K- and M-series), an extensive line of modules to interface different types of logic (W-series), a line
of special-purpose modules (G-series), and a line of support hardware for its module line (H-series).
With few exceptions, the DEC below-ground logic operates with logic levels of ground to -O.3V (upper level) and
-3.2V to -3.9V (lower level), using diode gates that draw input current at ground and supply output current at
ground. Figure I shows the voltage spectrum of negative logic systems.

ov
UPPER LEVEL { -O.3V

-------

,
{ - 1.3V
INDETER MINANT _ 2.2V
LOWER LEVEL{ - 3.2V
- 3.9V

~---

15-0070

Figure I Voltage Spectrum of Negative Logic Systems

The compatible above-ground logic generally operates with levels of ground to +O.4V (lower level) and +2.4 to
+3.6V (upper level), using TTL or TTL-compatible circuits with inputs that supply current at ground and outputs that sink current at ground. Figure 2 shows the TTL logic voltage spectrum.

UPPER LEVE L {

+3.6V
+2.4V

INDETERMINANT {

+ 2.0V

+O.BV
LOWER LEVEL {+O.4V
OV

~----~

~b
15-0070

Figure 2 Voltage Spectrum of TTL Logic

A set of special modules designed to operate on the PDP- 15 I/O bus is also available. Figure 3 indicates the
voltage spectrum in which these special modules operate.
The use of DEC's Digital Logic Handbook is recommended for readers of this manual who are not familiar with
the basic principles of digital logic and the type of circuits used in DEC logic modules.

UPPE R LEVEL

2 8V
.
+2.0V

r--r--------

INDETE RMINANT t,·6V
+1.3V
LOWE R LEVEL

to.

----- - ---

BV
+O.4V

, 5- 0070

Figure 3 Voltage Spectrum for Positive PDP-I 5 I/O Bus Logic

MEASUREMENT DEFINITIONS
Timing is measured with the input driven by a gate or pulse amplifier of the series under test and with the output
loaded with gates of the same series (unless otherwise specified). Percentages are assigned with a percent indicating the initial steady-state level and 100 percent indicating the final steady-state level, regardless of the direction of change.
Input/output delay is the time difference between input change and output change, measured from 50 percent
input change to 50 percent output change. Rise and fall delays for the same module are usually specified separately.
Risetime and falltime are measured from 10 percent to 90 percent of waveform change, either rising or falling.
WADING
Input loading and output driving are specified in "units", with one unit equivalent to 1.6 rnA. The inputs to
low-speed gates usually draw I unit of load. High-speed gates draw 1.25 units, or 2 rnA.
PARTS LOCATION
A parts location diagram is provided for those modules that contain numerous discrete components and integrated circuits. The location of parts on integrated circuit modules can be determined by visual inspection and
circuit schematic reference.
"E" designators are assigned to integrated circuits according to the following convention: looking at the component side of the module, "E" numbers are assigned from right-to-Ieft within each horizontal row, starting with
the top row. Figure 4 illustrates this convention and typical symbols used in the parts location diagrams.

8
8

CRLJ

@=rl

8-.

lliIJi
lliIl NOTE
NOTE 2

MXXX
NOTES

c::::::IJ Indicates diode palarity -{>I-.
2.

E 9 is an integrated circuit operational amplifier.
15-0173

Figure 4 Sample Parts Location Diagram

A124
Analog Multiplexer

The A 124 Analog Multiplexer consists of four MOSFET switches and four driver gates used for selection of
single-ended analog inputs in the range of ± 10V. This module is also used for gain selection with the A222
Selectable Gain Amplifier in the ADI5 Analog Subsystem.
Isolated grounds are used in the module to help prevent program noise from causing analog signal acquisition
errors. Analog and logic grounds may differ by as much as 9V without malfunction.
Each drive consists of 2-bit input decoding and a common enable input. All inputs are de~activated when power
is removed.
INPUTS:

Digital: Pin H (enable) presents I unit load; pins J, K, L, M, Nand P present
1/2-unit load each.
Analog: Pins R, S, T, and U - ±lOV normal, ±20V maximum.

OUTPUTS:

Analog: Pin V series resistance < 2200 ohms, 3 rnA max. load.
Response time to logic input change < 1.2 Jl,sec.

POWER:

+15V at pin D, 25 rnA
-20V at pin E, 30 rnA
+5V at pin A, 8 rnA

A124-1

•

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

-20V,E,

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A222
Selectable Gain Amplifier

The A222 is a non-inverting operational amplifier with high input impedance. A precision voltage divider is connected between output and ground with taps at ratios of 1.0, 0.5, 0.25, and 0.125. This module is used with an
A124 Analog Multiplexer in the ADlS Analog Subsystem to provide computer-controlled gain selection in the
AD 15. An lOT instruction causes two AC bits to be transferred to an AD 15 buffer register. These bits are decoded by the A 124 to select one of four available gains: 1, 2, 4, or 8.
INPUTS:

Inverting input (pin S) - Connect to the desired feedback tap through a series
resistance of 3000 ohms or less (A 124 Analog Multiplexer).
Non-inverting input (pin P) - Gain of 1, 2, 4, or 8 ±.02% with .02% linearity error
over a ± 10V output range. Input impedance greater than 1000 megohms in parallel
with 10 pF. Protected against overload up to ±20V.

OUTPUTS:

POWER:

Analog Input Range

Selected Gain

Output Selected

±1.2SV
±2.SV
±S.OV
±lO.OV

8
4
2

Pin V
Pin U
Pin T
Pin R

+lSV, ±l%, 20 rnA, max. (Pin D)
-lSV, ±l%, 20 rnA, max. (Pin E)

A222-l

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A405
Sample and Hold Amplifier

The A405 Sample and Hold Amplifier is used in the ADl5 Analog Subsystem to sample the rapidly varying analog
input (25 kHz, minimum) and store the signal level at a particular time to allow an A/D converter to convert the
signal to a digital word. The amplifier provides acquisition of a lOY step input to within I mV in less than 2 MS.
Two digital Track Control inputs are provided to control the sample/hold function: pin BF for positive logic and
pin BH for negative logic. In positive logic applications, the amplifier will sample (track) when the level at pin BF
is high and hold when the level at pin BF is low. For pulsed RS flip-flop control, jumper WI is removed and
jumper W2 is connected. Then, a positive pulse at pin BF sets the flip-flop for tracking and a positive pulse at pin
BH resets the flip-flop to hold the signal.
A voltage offset circuit is provided at the input to allow the output signal to be shifted more positive. To use this
offset, pin AU isjumpered to pin Bl and pin BM isjumpered to pin AE. (-15V). This circuit is not used on the
AD 15 Analog Subsystem application.
INPUTS:

Analog input: ±IOV range, 2000 ± 1% ohms
Digital inputs: Positive logic Track Control at pin BF presents 1 unit load.
Pulse input to set hold at pin BH presents I unit load.

OUTPUTS:

Analog output: ± 1OV at lOrnA, 0.1 ohm maximum output impedance at pin AV.

POWER:

+15V at 35 rnA at pin AD
-15V at 40 rnA at pin AE (plus additional 11 rnA if offset circuit is connected)
+5Vat 15 rnA at pin AA

A405-1

A405-2

A607
10-Bit Of A Converter, Single Buffered

The A607 module contains a 10-bit D/ A converter that consists of a 10-bit buffer register, a binary weighting
network, and a current summing amplifier. The reference voltage used in the binary weighting network is externally supplied for greater efficiency and optimum scale factor matching in multi-channel applications. Data
on register input lines must be settled 20 ns before the leading edge (positive-going voltage of the CLOCK pulse
passes the threshold voltage and should remain stable 5 ms afterward. The duration of the positive CLOCK pulse
should be at least 50 ns, and the duration of the negative CLEAR pulse should be at least 30 ns. Data present at
the input of the register is transferred to the output when the leading edge of the CLOCK pulse passes the threshold. The analog output voltage is unipolar and varies from OV to 2.0V (in two millivolt increments) in accordance with the binary input data.
The following are the input, output, and power characteristics of the A607 module.
INPUTS:

Each DATA input presents one TTL unit load. The CLOCK input presents 2 unit loads,
and the CLEAR input presents 3 unit loads.

OUTPUTS:

The analog output voltage is capable of driving a lOrnA load (maximum).

POWER:

Power dissipation of the A607 is SV at 200 rnA (maximum) and -I SV at 100 rnA (maximum).

DATA INPUT
AE2 AF2 AM2 AN2 AS2 AT2 BD2 BE2 BH2 BJ2

15-0118

A607 Simplified Diagram

A607-1

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A708
Dual Voltage Regulator

The A 708 Dual Voltage Regulator is used in the AD IS Analog Subsystem to provide regulated -15V and +5V output voltages.
In the -15V regulator circuit, Q3 and Q4 control the forward bias on series regulator Q5 to maintain the -15V
output within ± I %. In the +5V regulator, any change in the +5V output is sensed at the base of Q2, which controls forward bias on QI to maintain the +5V output with ±5%.
INPUTS:

Less than 20 mV ripple.
-20V, ±I%, 0.25A max. Pin N2
+15V, ±I%, 1.25A max. Pin E2, V2

OUTPUTS:

-15V, ±0.5%, 0.2A max. Pin S2
+5V, ±I%, 1.2A max. Pin A2

A 708-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1970 BY DIGITAL EQUIPMENT CORPORATION

DEC2219
-2OV,AN

•

AS,-15

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•

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GND,AC

• • •

DUAL VOLTAGE
REGULATOR
A 708

A877
Analog-to-Digital Converter

The A877 Analog-to-Digital Converter is used in the AD 15 Analog Subsystem to convert the A405 Sample and
Hold Amplifier output to a l3-bit digital word (12 bits plus a sign bit). A comparator amplifier compares the
analog input voltage with a programmed sequence of internally-generated reference voltages to determine the
polarity and amplitude of the input signal. The result is stored in a 13-bit data register. An AID DONE signal is
provided when the conversion is complete.
MAINTENANCE NOTE
The A877 uses special matched components to achieve specified
measurement accuracy. If a fault is isolated to the A877, do not
attempt to replace components in the field. Substitute a spare
module and return the faulty module to DEC for service.
ANALOG INPUT SIGNAL:

Full scale range: ± 10V
Connections: Single-ended
Impedance: 28K ohms
Overvoltage limit: ± I 5V, maximum
Settling time: I JIS

ENCODING PROCESS:

Digitalizing resolution: I part in 8,190 (2.5 mY)
Encoding word time: 36 JIS, typical
Encoding word rate: 28,000s, typical
Code: Parallel, binary 2's complement

MEASUREMENT ACCURACY:

Full range: 0.015%
Temperature coefficient: ±0.0020%tC (over full operating
temperature range)

CONTROL SIGNALS:

Input: Command to Convert (CTC) initiates encoding process
on a logic I-to-O transition
Output: End of Conversion (EOC) pulse is 100 ns logic I pulse

DATA OUTPUTS:

13 bits, held in storage until next CTC input.

POWER REQUIREMENTS:

+ 15V, ±5%, 100 rnA, typical, pin AD
-15V, ±5%, 50 rnA, typical, pin AE
+5V, ±IO%, 400 rnA, typical, pin BA

A877-1

CONNECTOR PIN ASSIGNMENTS
Pin

Function

ADI/2
AEI/2
AFI/2
AJ2
AK2
AUl
BA2
BC2
BE2
BF2
BJ2
BK2

+15V
-15V
.±.l5V Common
Analog Input
Analog Return
Command to Convert (CTC)
+5V
Logic Ground
Sign Bit, Complemented
Sign Bit
Data Bit 2
Data Bit 3

BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2
BJl
BFI

Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11
Data Bit 12
Data Bit 13 (LSB)
End of Conversion (EOC)

ADJUSTMENT AND CALmRATION
NOTE
Do not attempt to adjust any potentiometers other
than the reference, gain, and zero adjust potentiometers at the rear of the module (see illustration).
Adjust the A877 while it is installed in slot Cil of the AD 15. Remove the A405 module and allow 15 minutes
warmup.
~RED TEST POINT (+IOV)

Reference Voltage Adjustment
Use Fluke 585A voltmeter (or equivalent voltmeter with
0.005% accuracy) to measure voltage between + 1OV test
point (red) and ground (black). Adjust reference potentiometer (top) to obtain 1O.000V, ±I mY.

c:::::J
REFERENCE

c:::::J

Gain Adjustment

GAIN

Connect EDC voltage standard (or equivalent voltage
standard with 0.005% accuracy) between pins CIIJ2 and
CIIF2 (See drawing D-AD-7007029-0-0 in ADI5 manual).

ZERO ADJUST

c:::::J

Run MAINDEC-I5-D6GA-D(D), with any channel and gain
setting. Adjust the EDC to find the most positive switchb B L A C K TEST POINT (GND)
ing point (007776-007777). Record the voltage. Reverse
the polarity of the EDC connections to find the most negative switching point. Record the voltage. The difference between the voltages should be 19.9995V, ±2 mY. Adjust the gain potentiometer and repeat these measurements until the difference is within the specified tolerance.
\1-0423

Zero Adjust
Short-circuit pins CIIJ2 and CIIF2 and note the conversion value. If the reading is outside the range 77776000002, adjust the zero adjust potentiometer (bottom) to bring it within range. This adjustment interacts with
the gain adjustment and several passes may be required to bring both adjustments within their specified tolerances.

A877-2

G08S
Disk Read Amplifier

The G08S Disk Read Amplifier is a double-height module consisting of an ac-coupled amplifier with a bandwidth
(-3 dB) from 20 kHz to approximately I MHz, followed by a slicer. The G08S module is used to detect and
amplify timing tracks and data signals for the RS09 DECdisk. The maximum voltage gain (under potentiometer
control) is approximately 60 dB (1000). Common mode rejection ratio is approximately 40 dB. The amplifier
is insensitive to any power supply ripple voltage less than 5 percent. Pin AM increases the gain by approximately
20 percent when its input is low. The nonrectified slice output is gateable, and the slice point can be varied by
logic inputs. A potentiometer is provided to adjust the slice. Pins at AT and AV are provided as amplifier test
points. Proper grounding is critical in this module. G08S ground pins should not be bussed. Pins AS and AC
should be connected to analog ground, and BF and BC should be connected to logical ground. All amplifier connections must be isolated from fast rise-time signals.
INPUTS:

OUTPUTS:

Voltage levels are 0 and -3V, except at the input to pins AE and AF.
Pin

Function

Load or Input Voltage

AE,AF
AM
BU,BV
BS,BT
BP,BR

Read Head Input
Read Gain Control
Read Slice Control
Read Slice Control
Enable Output

approx. IS mV peak-to-peak
2mA
2mA
2mA
2mA

Voltage levels are 0 and -3V except at AV, which provides +20V for the
timing track center taps.
Pin

Function

Drive

BE,BD

Signal Output

10 rnA

INPUT/OUTPUT DELAY: 120 ns
POWER DISSIPATION:

2W at +20V
I.5Wat-ISV
BP

AE
AV

BE
SLI CE
BS

BT
09-0357

G08S Disk Read Amplifier and Slice, Block Schematic
G08S-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSlS. THE
CIRCUITS ARE PROPtUETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION

! !!
R2
22K

R8
15K

904

R4
10K

RIO
4.64K
1/8W
1%
R9
100
II8W
1%

903

059

0864

RI7
4.64K
I/SW
1%

,...

CoL

i:7~L4

>R15
215K

R20

fR23
IK
IISW
1%

908
0672

R6
3.48K
1/8W

AE~

09
0664

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~
R5
3.48K
It 8W

..,

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Q6
OEC65348

010
0644
~

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R21
IK

EblQI

-,,+

RI
7.5K

R7
IK
1/8W
1%

06
05

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+1 CIO
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Q7
OEC6534B

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All 0

... 1

07
0672

r r:::

R28
IK
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1%

•

R3
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RI2
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R27
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•
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03S
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:~W

I~W

BV~

7.l5K

UNLESS OTHERWISE INolCATEO
CAPACITORS ARE 35V
RESISTORS ARE I~W,5%
OIOoES ARE 0662
TRANSISTORS ARE oEC3009B
R21,R32 ARE POTS 76 PR I K HELITRIII
IIBW, 1% RESISTORS ARE 100llF

R33
1.47K
118W
1%

R34
1.96K
1/8W

037

100

j ~I
~R39

R51
68K

R41
IK

019
0664

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R57
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QS
2_58

020
0664

025
0664

R43
10K

RS6
IK

R36
6SK

-15V

I~)~~
R37
1.96K
II.8W
1%

R40
1.96K

liIIW
1%

R45
1.5K

034

BE
OUT PUT

-3V
R49
100
:!1..C14
_.,...,IIFO

033

.p~0664
R46
BD
1.5K OUT PUT
BR

032
0664

R52
7.5K

R48
1.5K

RS3
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G100
Sense Amplifier and Inhibit Driver

The G I 00 module contains four sense amplifiers and four inhibit drivers. Five of these modules are used in the
PDP-IS for each 4K memory stack. (Refer to Engineering Drawings D-BS-MM 15-0-1 0 through D-BS-MM 15-0-15).
Each inhibit driver consists of a two-input NAND gate and a high-speed current switch. One driver is used for
each bit plane of the memory array. An inhibit signal is received by all inhibit drivers only during a write operation.

CORE

AD2 AC 1
STROBE

AKI

AH1

AVl (TEST POINT)

365m A

G I 00 Simplified Diagram

Each driver also receives a signal indicating the state of the corresponding bit in the MB. Inhibit drivers that receive a signal indicating a 0 state in the MB bit are gated on and cause inhibit current to be applied to the associated
bit plane of the memory array. Each inhibit driver employs a discharge network to speed up inhibit current cutoff. The output of the inhibit driver is connected to the middle of one core sensing string, which represents one
bit plane of the memory array. The balun network at the front end of the sense amplifier ensures equal current at
all times through both sides of the core string. In addition to the balun network, the sense amplifier consists of a
differential amplifier and output driver. One sense amplifier is used for each bit plane of the memory array. During a read operation only the signal induced on the sense winding of a core plane by a core-changing state is received by the differential amplifier. The differential amplifier has a nominal threshold of 17 mY. Output pulses
of standard amplitude and duration are supplied by the output driver when the sense amplifier reads a logic I from
the associated core, which in turn is strobed by a standard positive going pulse at ACI. Propagation delay from
the input to the sense amplifier to the buffered output is 25 ns (maximum) and from strobe input to buffered
output is 15 ns (maximum). These output pulses are used to direct set the MB register.

GIOO-l

The following are the input, output, and power characteristics of the G I 00 module.
INPUTS:

Inhibit driver DATA inputs present 1.25 TTL unit loads and INHIBIT inputs present 5 unit
loads. Sense amplifier inputs are 0-9 mV for a logic 0 and 31-35 mV for a logic I.

OUTPUTS:
POWER:

Inhibit driver inhibit current is 730 rnA.
Power dissipation of the G I 00 module is +5V at 130 rnA (maximum), -6V at 60 rnA
(maximum), and -24V at 800 rnA (maximum).

GlOO-2

This page intentionally left blank.

GIOO-3

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1:1'0:;0

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75
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-1
R2
3K
ANI

2
~
3

UNLESS OTHERWISE INDICATED:
DIODES ARE 0672
CAPACITORS ARE .01 MFD,IOCV, 20%
RESISTORS ARE 1/4W,5%
TRANSISTORS ARE DEC3639B
EI IS DEC74HOON

8KI
BLI

750

AJI

CI2
22 MFD
35V

Cll

680pf,5%

1-,

r--11-

13
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ADI

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R22

.D15

E2,E3, E4,E5, ARE DECI540G

~',~ ; ~~ ~UU~~~5 Tg V,~t~~ (G:,!i~ AC2 (GND)

DI9
14

LJ· I ~

~'I%~'40~~~'IE;+E5;;E5: +5V
TRANSFORMERS ARE 1609478
HOUSING IS DEC.,209482
INDUCTORS LI- L4 ARE 10MH

L-...

"",""
(GND)

BRI,BKI (-24V)
BPI,BLI

75
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G 100-5

G222
Memory Selector

The C222 module contains four memory selectors. Eight of these modules are used in the PDP-IS for each 4K
memory stack. (Refer to Engineering Drawings D-BS-MMIS-O-6 and D-BS-MMIS-0-7.) The modules are used to
decode the memory address to obtain the X- and Y-axis select signals for accessing the core memory. Each memory selector consists of a 3-input NAND gate and a bidirectional current switch network for both read and write
current. An 8 x 8 matrix (see G613 and G614) is used for each of the X and Y selection paths. Thus, two switches
must be energized to establish the path in the X plane, and another two switches must be energized to establish
the path in the Y plane. In a 4K system a total of four G222 modules are used to decode the fIrst six bits of the
memory address. This provides one out of 64 states for the Y plane. Similarly, four G222 modules are used to decode the remaining six bits of the memory address in order to establish the selection path in the X plane.

4-- -

MATRIX DRIVE
r-'--.....--"'-~;.;......:.;.;.;.....;..
MI

+---

02
EI

- - - . -V
+V

T 2 (CONNECTED TO
G223 OUTPUT)

+
, ,

'MATRIX DRIVE M2
READ CURRENT ~
WRITE CURRENT ----.

US-OI20

G222 SimplifIed Diagram

The following are the input and output characteristics of the G222 modules.
INPUTS:

Each NAND gate input presents 2.S TTL unit loads.

OUTPUTS:

Each matrix selector switch handles 400 rnA (typical).

G222-1

+
THIS SCHEMATIC IS FURNISHED ONLY fOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

GND
H2

118
9
•

..--J
rlM""\04

7"0

R25
470

010

~!t • 10._ _

i3~

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MMF

C 10

R24

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7"0

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330

M2
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NI
RI3

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MMF

Fl.

-----;0

2
:5 0

~,~< I I :l:
-l

R28
RII
PI

MMF

1-.-

RIO

II~O

C8
P2

470

II~

~z,

Gil

~'1°F

+5V
A2

UNLESS OTHERWISE INDICATED:

11
CI

01 r

0662 06620662

~i~

01
MFD 1'01
MFD
20%
20%

03
T2

R6
2.2K

R5
470

GND
C2,TI

U2
-24V

t'~,-:

~·t;6oAt'w....
IE~~..I'

;~:'{'f1

-r~"

D"'~E

,fl(jt,..l1.--... ~
,

DEC FORM NO.
DRe 102

• • •

61~~~~ISX~~SD~~~ DEC6534C

RESISTORS
RESISTORS ARE
ARE 1.5K
1/4W,5'%
CAPACITORS ARE47PF,IOOV,5%
I C'S ARE DEC74HION
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V

-1'

ATE

TRANSISTOR & DIODE CONVERSION CHART
DEC

DEC6534C
0662
0172

EIA

DEC

EIA

mamaoma
••

•

TITLE

MEMORY SELECTOR G222

I14PS6534
IN645

'0"03

E QUI P MEN T
CORPORATION

SIZE

..... "N.... D ........... CHU •• TT.

PRINTED CIRCUIT REV

£lIsT.

CODE

CS IG222

3..2..'1) 4-3!f 1+-33'2.-

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G222-3

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G223
Read/Write Driver

The G223 module contains two read/write drivers. Two of these modules are used in the PDP-IS for each 4K
memory stack; one provides the drive for the X plane and the other provides the drive for the Y plane. (Refer to
Engineering Drawings D-BS-MMIS-O-6 and D-BS-MMI S-O-7.) The G223 and G222 modules work together (see
illustration) in that the current path selection through the core memory is established by the G222 modules, and

READ CURRENT
WRITE CURRENT - - - - - - - -

--I
+V

SOURCE

1/2 G223

\..1
{ 1

SINK

r - - ---- -+Yl

II
I
II

:
SOUR!E

I•

-)t 1 1

1/2 G2 2 3

__ -.I I

READ------~r---l~---------------- 1
--'!l~_________

\.1,'

----=-----j~--+------+--+----f------*---

SINK

tEAD

WRITE ____________

•

-v I

---~

MA
15-0133

G223 Simplified Diagram

G223-1

the drive current for reading and writing is supplied by the G223 module. Reading and writing currents travel in
opposite directions. Each read/write driver consists of two input control NAND gates and two current switches
connected in series with a common output. The read and write commands and the page select command are applied to the input control NAND gates, turning on the corresponding current switches and establishing a current
path from ground to -24V. The balun network at the output of the driver ensures equality of input and output
current through the stacks at all times.
The following are the input and output characteristics of the G223 module.
INPUTS:

The READ and WRITE inputs (pins E I and F I) each present 1.25 unit loads. The pageselect input (pin D I) presents 2.5 unit loads.

OUTPUTS:

The measured read/write voltage waveform and its current waveform for the worst
case pattern take the form shown below for an 800 ns memory cycle time.

lOOns

-I V

-12V

VOLTAGE WAVEFORM

CURRENT WAVEFORM
15 - 0121

G223 Current and Voltage Waveforms

The current-rise time to get to 400 rnA for both reading and writing is approximately 100 ns, while the fall time
is 40 ns. The stagger time (Ts) between read and write currents is approximately 130 ns.

G223-2

This page intentionally left blank.

G223-3

•

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE ANO SHOULD BE TREATEO ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CDR.f>ORATION

GND (-24VI
. UI

C2,T!
GND

GND (-24VI
U2

, , ~

+~~

<U7. ~ <U7• •

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DI
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R5
82

T5
T2

R7
17
5W
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IK

01
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4

5 I

13
T4

\04

II~"

I200
MMF

I+~ RIO
IK

+lc6
50
-TMFD
50V

T2
VI
-24V

V2
-24V

UNLESS OTHERWISE INDICATED,
TRANSISTORS ARE DEC 1008
TI-T4 ARE SPRAGUE 5574,17Z1 OR 5387 16-09479
DIODES ARE 0664
CAPACITORS ARE 120MMF,IOOV,5%
RESISTORS ARE 1/4W 5%
T5 IS SPRAGUE 5386,OR 17Z5 16-09478
PIN 14 ON EACH Ie = +5V
PIN 7 ON EACH IC = GNO
E21S SN74HOON
E I, E3 ARE SN74H40N

READ WRITE DRIVER G223
EQUIPMENT

COR PM'?~A~?"u~~~ II--'-:...JIL..-c.--,-::-,,---=-:--

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2:J

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G223-5

£:J

L:J

G285

Series Switch

The G28S Series Switch is a single-height module consisting of two 4-inch AND gates, each driving the base of
two driver transistors. This series switch is used together with the G290, the G286, and the G08S to form the
Read/Write head matrix in the RS09 DECdisk. When a gate is enabled, it in turn switches its corresponding
transistors that form part of the select and read/write matrix of the disk or memory.
INPUTS:

Voltage levels to the gates are 0 and -3V. In levels to the signal inputs
Land Mare 0 and -ISV.
Function

Load

D,E,F,H,S
T,V,M

Gate Enabling Inputs

1 rnA shared among
inputs at ground

L,M

Signal Inputs

OUTPUTS:

Voltage levels are 0 and -ISV (Le., the input signal gated through the
transistor). Each switch pole can drive up to 150 rnA. Reverse voltage
transients up to 100V do not destroy the switch circuits. Output pins J,
K, R, and P must be returned through the load to + lOY. The common
pins (L and M) to both sets of switches must be returned to -ISV. The
switches will pass I MHz current. The voltage drop for 100 rnA is approximately IV.

INPUT/OUTPUT DELAY: 1 IlS
POWER DISSIPATION:

l.SW

D
E
F
H

S
T
U
V

09-0356

G28S-I

~:o,ooo ~ ;~300
112W

5 ...

...

'
R7 "
3,300

100,000

j.R14

100,000

~ 3,300

I,ZW

f:IOV FOR

. ..

RI2

...

1/2W

RI7
100,000

RI.
3.300

1'2_

~'(IOVFOR

010
liPS
6551

011
0870

•

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00

011

+J..~:
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1,.00

10%

10'"

1/2_
10'"

All

US,DOO

10.000
10 ...

10.000

+
R4
15,000
10%
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4. i 5~
TRANSISTORS ARE DECISS48
DIODE8 ARE D81.
PARTS LIST IS A-PL-G285-0-0

01.
08.2

R13

:~~OO

0'1
0 ••2

020
0 •• 1

io4

OC IND

.011llFO

L----------------------r--------~--~~------~--------------~O.-I.V

1::::::::::::::::::1

r-------_

10
CD
N
(!)

G285-3

G286
Center Tap Selector

The G286 Center Tap Selector is a single-height module consisting of four AND gates, each of which drives a
power output stage that applies a +20V level to its output pin when enabled by the gate. This module supplies
the +20V read/write level to the coil of each head it drives in the RS09 DECdisk Read/Write matrix.
INPUTS:

OUTPUTS:

Voltage levels are 0 and -3V.
Pin

Function

D,E,K,L,N,P,
S,T,F,H

Gate inputs
Gate inputs

I rnA shared among
inputs at ground in
each circuit

Each output is +20V when the AND gate is enabled and OV when the gate
is not enabled. Each output drives 150 rnA at +20V.

INPUT/OUTPUT DELAY: 500 ns
POWER DISSIPATION:

Load

I.4W

----<:r---'-. . .

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THIS S(HlMA,TIC IS fUflNISHED
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101/ FOR DF32
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G290
Writer Flip-Flop

The G290 Writer Flip-Flop is a single-height board containing one JR flip-flop driving two AND gates and two
power drivers. This module, used in the RS09 DECdisk supplies the -15V write voltage to the G285 Series
Switch. There are several gates to the input of the flip-flop.
Voltage levels are a and -3V.

INPUTS:

Function

Load

N,M,T,U,

Inputs to flip-flop
Input to flip-flop
Direct Clear
Enable input to output driver gate

Each gate is a I rnA
load shared among
its grounded inputs

S
K,J
OUTPUTS:

The E and F outputs are -15V or an open collector. The P and R outputs
are a and -3V.

Function

E,F
P,R

Drive

Output to G285 Series Switch
Test output of flip-flop

INPUT/OUTPUT DELAY: 90 ns
POWER DISSIPATION:

L ----<~-....

¥=====r-<
u ---L.--'

s
09 - 0354

G290 Writer Flip-Flop, Block Schematic

G290-1

150mA
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09-0~90

G613
X Diode Matrix

The G613 module contains 256 diodes connected to form an 8 x 8 two-way crosspoint switching matrix that provides 64 pairs of interconnecting points. (Refer to Engineering Drawings D-BS-MM 15-0-6 and D-BS-MM 15-0-7.)
Sixty-four cores from each of the 18 memory planes are connected between each pair of interconnecting points,
thereby creating the current paths of the X-axis in the core memory stack. A thermistor is also included in the
G613 module to control the read and write currents in response to temperature changes.

G613-1

+
THIS SCHEMATIC IS fURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCOROlNGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

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TITLE

EQUIPMENT
CORPORATION

S~E_rc~J

.......H .... D .......... C ...... TT.

PltIHTED CIRCUIT REY.

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X DIODE MATRIX G613
HUM'EIt

G613 0 I
ABC

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056

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061

062

063

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066

067

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072

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075

076

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078

079

080

081

082

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084

085

086

087

088

089

090

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092

093

094

095

096

097

098

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0100

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0102

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0182

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0'84

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0186

0187

0188

0189

0190

0191

0192

0193

0194

0195

0196

0199

0200

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0198

0201

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0210

0211

02'2

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0216

02'7

0218

0219

0220

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0225

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0228

0229

0230

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0232

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0234

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G613
-----

15-0152

C')
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G614
Y Diode Matrix

The G614 module contains 256 diodes connected to form an 8 x 8 two-way crosspoint switching matrix
providing 64 pairs of interconnecting points. (Refer to Engineering Drawings D-BS-MM 15-0-6 and
D-BS-MMI5-0-7.) Sixty-four cores from each of the 18 memory planes are connected between each pair of
interconnecting points, thereby creating the current paths of the Y axis in the core memory stack.

G614-1

•

THIS SCHEMATIC IS FURNISHED ONLY fOR nST AND MAINTENANCE PiJRPOSES THE
CIRCUITS ARE PROPRln.r.AY IN NATURE AND SHOULD BE lAUTEO ACCORDINGLY

BY DIGITAL EQUIPMENT CORPORATION

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0672

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mamaama

TITLE

EQUIPMENT
CORPORATION

S~E 1~~El

............ D . . . . . . . . C .. U . .'T . . .

F'RINTEDCIRCUITR[II

Y DIODE MATRIX G614
NUMBER

G614 -I) - I

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(--p I 9!)

032

0224

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0160

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D196

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D194

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G681,G711,G775

OECdisk Modules

1. G681 8 TRACK MATRIX

The G681 Track Matrix is a single-height board containing the resistors and diodes for eight DECdisk read/write
heads.
2. G711 RF08 TERMINATOR BOARD
The G711 RF08 Terminator Board is a single-height board containing IS terminating resistors that present lOOn
to ground at each input pin. This board must connect to the output cable slot of the last RS09 on each DECdisk
cable bus.

INPUTS:

lOon to ground

OUTPUTS:

None

POWER DISSIPATION:

Approximately 90 mW per terminator

3. G77S INDICATOR PANEL
The G77S Indicator Panel is a connector card that provides isolation for logic levels and allows these levels to
directly drive indicator bulbs without using light drivers. The connector is designed to be used with the indicator
panel, which supplies the necessary bias voltage.

INPUTS:

All inputs are 0 and -3V with 3 units of load each.

OUTPUTS:

The output connects a Flexprint cable to the indicator board.

POWER DISSIPATION:

ISOmW

G681, G711, G77S-1

M.'N1E"'ANrf PUAP(J"t~ IH[
llHAll(" ,o,lCORDINGLY

THIS SCHEMATIC IS fUR",$HfD
CIRCUITS AfH PflOPIIIEUfl¥ IN
COPYRIGHT 1969 BY DIGITAL

R38

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R58

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(4)

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DI~

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R24

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_--,

R23

(6)

(7)

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(9)

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EQUIPMENT!WII(C,:,'I

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C(,)\J~~ECT,GR Ci~RD

7 ('J -0- I

1"1.

G821
+5V Regulator

The G821 module contains a voltage regulator with over-voltage, under-voltage, and over-current protection
circuits. This module supplies the regulated +5V in the memory of the PDP-IS. Combinational logic circuits are
also included in the module to provide lamp driver and memory power OK signals when the memory voltages are
within set levels. The input power connections to the module are made with an 8-pin mate-in-Iock connector at
the back of the module.
The following are the input and output characteristics of the G821 module.

INPUTS:

The inputs to the G821 module are +8V, +I IV, -15V, and ground. These voltages are supplied
by the 715 power supply. The module also receives positive level power OK signals from the
G822 and G823 modules.

OUTPUTS:

The outputs of the G821 module are variable 4.5V to 5.5V at 7A (maximum)* (when set at
5V, regulation is ±2% with a ripple voltage of 25 mV peak-to-peak); + II V at 1.0 amp (maximum) with the same regulation as the input voltage; and -15V at 3.0 amps (maximum) with
the same regulation as the input voltage.

----..,
CONNECTOR

+5V

CURRENT SENSING
t-----<p-'VIIIr<~--------__...------------__...-----

(BB1,BC I,BD 1
SEE·SCHEMiI-TI-C)

20---.---'
30-.-~~--------,

4 0--.-----'

5 0-.----------,
6

OVER
VOLTAGE
DETECTION
AND
SENSE(+)
CROWBAR

UNDER
VOLTAGE
DETECTION

SENSE (-)

'-15V

____ .J

M6N~~~ {BNl
GB23 IF USED
AND G822

BP 1

>------- BRI (MEM PWR OK)

>------- BM 1
~--+--------------------~---------=---------- GND (AC2, AHL ___ _

SEE SCHEMAT IC)
'------~----------------------------------------- BMI (+ 11 V)

' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AB2, AE 2, AF2 (-15 V)

G821 Simplified Diagram
*The 7A rating is valid only when adequate fan cooling is used. Without additional coding, the output rating is 2A (maximum). The +5V
potentiometer must be rotated clockwise to obtain a higher output voltage.

G821-1

Additional outputs include an open collector lamp driver (output pin BMl) that is turned
on when the SV power is within set limits (by rotating the voltage detection potentiometer
CCW, the low voltage limit decreases) and an open collector driver (output pin BRI) that is
turned on only when the SV power is not within set limits. Voltage limits are usually set at
4.7SV by the voltage detection potentiometer, while the upper voltage detection level is set
at S.SV.

G821-2

- f=-cHG89 [ 53

. A3M

M38V'/nN

[81I

3000 3ZIS

THIS SCHEMAT~C IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY

+5V

BY DIGITAL EQUIPMENT CORPORATION

• • • • • • •

•
R4
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47

<>,.""

(,c..c."

CIO

·· .. -<>'K

Ir\(")\/

GND

+1 C9
AB2
AE2
AF2

>
Z

W ...

III

Q zoo
~<.!lOO

> rOo

u 0 0
O::~!"(,

LLJ

iL'Y t

DEC FORM NO
ORB 102

-15V

10MFD
20V
10%

UNLESS OTHERWISE INDICATED
PIN 7 ON EI=GND
PIN 14 ON EI=f-5V
EI IS DEC740lN
E2 IS LM300
CAPACITORS ARE IMFD ,35V, 10%
DIODES ARE D664
RESISTORS ARE 1/4W 5%
R3,R17 ARE POTS #76PR
TRANSISTORS ARE DEC3009B

CONVERSIO~ ~~~~T
II"

DEC
TRANSISTOR EIA
& DIODE
0664
0672
I N74BA
DEC3009B
OEC6534B

IN3606
IN36~3

SAME
2N3009B
MPS6534

]

DEC

2N2904
2N3055

'w,,"

,....

RI7
IK

G ND

Ef:p'.'

R27
330

'VV'v

(/) rr

BBI,BCI
BDI,BEI
AA2,BA2
ABI,ACI
ADI,AEI
AFI,AHI
AJI,AKI

AC2,AH2
AK2,AL2
AT I,BC2
BD2,BH2
BK2,BL2
BTl

momoomo I~;~ RE~ULATOR CClJTROL ~821

QUI P

MEN

=~~~M'?S~A~~~~~I
-,--

NUMt:H~.K

'. f':'>lrVK

G822
-6V Regulator

The G822 module contains a voltage regulator with an over-voltage protection circuit. This module supplies the
regulated -6V in the memory of the PDP-IS. A sensing circuit is also included on the module to provide a memory
power OK signal when the output is more negative than -6.5V.
The following are the input and output characteristics of the G822 module.
INPUTS:

The G822 module operates on II V input power from the 715 power supply.

OUTPUTS:

The outputs of the G822 module are:

INPUT
TABS

variable -5.0 to -7.0V at I.SA. (When set at -6V, regulation is ±2% with a ripple
voltage of 50 mV peak-to-peak. The potentiometer must be rotated clockwise
to obtain a more negative voltage setting);

variable 0 to -6.0V used as the threshold voltage for the G I 00 module. (This
voltage is nominally set at -3.8V. The potentiometer must be turned clockwise
to obtain a more negative voltage setting);

BN I, which is a TTL output that drops to ground when the -6V output voltage is
more negative than -6.5V.

@ 1.5A MAX
>-__.......________..-__......._______ -6V
BBl. BB2,BC1,BOl

REFERENCE
VOLTAGE
>-___
BNl
CROWBAR
CIRCUITRY

'--_-1,-

OETECTOR

...._ _ _ _ _ _ _ _ _ _ BV2 (TO G100)

'---________<10---------_---------- AC2,AB2, BTl
GNO
15-0130

G822 Simplified Diagram

G822-1

tI 1 A3~3

I - 0 - Z2 8

~38~nN

91 3ao~
S3 , 8
3ZIS

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY

~ RI7

~~R18 +5'
AA2
3
~IK
?II\ B N I
_ 2~1
I E I p-----*-----

TAB-

lei

RI
820
1/2W

+-r

10%

f f R21~ f~~
R22
820
1/2W
10%

68
IW

R6
270
'V' -

5.IV

Ai!l

--.J-.. C5
--.+

R10
100

4.7K

5 T
·2

TAB +
•

•

04
IN753A

':.7

~.Ol
--.J-..C6

+
•

•

011

RI3
330

R9
?7.5 K

R4
5.6 K
•

BV2

-r--

•

C4
...L.OI
MFD
100V
20%

BBI, BB2,
-6V
BCI,
BDI

010

01
DEC
3790
R8

•

*09

i----~----~---------------T----~~--,-----~----------t---~-----1--------

R2
2K

114M

35V
20%

-CP

02
DEC
2904

C2
68
M'FD

00
N

.03
~D672

f.--______---.-~

-..,- 'DB

RI4
330

,<",,1/05

MFD
100V
20%

'--"

••

~D6

-rD5
.0664

.0664

•

RI5
330

GND
AC2, BTl

UNLESS OTHERWISE INDICATED;
DIODES ARE 0662
RES I STORS ARE 1/4W, 5%
CAPACITORS ARE 20MFD,50V,-IOt75%
TRANSISTORS ARE DEC6534B
EI IS DEC740 I
PIN 7 ON EI = GND
PIN 14 ON EI = +5V

DRN
(f) or U
Zo -

N
,.,
Q z 00
0

(f)",
00
00
1:
WU 0 0 0

'>
Cl:

~ ~I~

DEC FORM
DRB 102

NO.

~Jn.~

DATE

l'd'-0

~~L...2
!tN~O ~",- 12O:lsE!
fo 6'1
DATE

;0--'"

PROD

DATE

,,,.

TRANSISTOR & DIODE CONVERSION CHART
DEC

EIA

0662
IN645
0664
IN3606
114M 5.IV Ai!l NONE
IN753A
SAME
2N4441
NONE

DEC
OEC65:3411
OEC2904
OEC3790
IN4733A

EIA
MPS6534
2N2904
2N 3790
SAME

TITLE

REGULATOR G822
~DmDDmD -6V
I I

EQUIPMENT
CORPORATION

SIZE

CODE

NUMBER

G822-0- I

""' ... YN ..... O. M ........ CHU.~TT.

PRINTED CIRCUIT REV.

VI5i, 3;) ,/, I{ 3'-1.Jt35

1R~V

IFI I I I ILl
Pm//<.....

N
N
CD

l!l

i--

,.....-

G0008 ~

GGGG0~ G
o

G
0

'<t

G GG

[TIT]

7~,"

Q:a::a:::a

00::00

G G
a:

-w

If)

~O
'"a:

0)8

ffiBG
a:::

a::

lr-t.J

G822-3

G823
-24V Regulator Control

The G823 module contains a temperature-compensated voltage regulator control with an over-voltage protection
circuit. This module is used in conjunction with the -24V pass element (G82S) to supply a regulated -24V for the
memory of the PDP-IS (see illustration). A thermistor mounted on the G613 module is connected to the -24V
regulator control module to provide a negative temperature coefficient for controlling the regulated -24V. For a
typical setting of -24V at 2S o C and with an average output current of 4A, the output voltage changes to -22.4V at
SO°C and to -2SV at O°C. The over-voltage protection circuit will disconnect the output above -26V.
The following are the input and output characteristics of the G823 module.
INPUTS:

The G823 module receives -30V from the 71 S power supply.

OUTPUTS:

The outputs of the G823 module are:
a.

A variable -18V to -28V at S.5A. When the module is set for -24V regulation,
the output is ±l % with a ripple voltage of less than SO mV peak-to-peak at full
load. Rotating the potentiometer CCW provides a more negative voltage setting.

An open collector driver (output pin Nl) that supplies a memory power OK signal
when the regulator control is operating properly.

>
~
')'

>
v

~
(\J
t,!)
N
t,!)
I
I
I
I
~~~~,...-........,....-.....,,----......--.

. - - - + - - - - - - - - , <muo~~i:;;:Ji~~~;;i

mmmmmmmmmmmmmmmm

THERMISTOR
AI

(BASE) AJ2

MI
T1

C2 _
G823 AVI TO GIOO AVI } SENSE
G823 AUI TO G 100 AUI

G823 Simplified Diagram

G823-1

15-0129

THIS SCHEMATIC IS fURl\lSHED ONl.Y FOR lEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE f'ROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL lQUIPMENT CORPORATION

--------<> L I
-30V
R5
825
1/8W
1%
NI

R6
7.2K
1/8W
.1%

R9
330
1/2W

00
IV

RI
1.5K

(-SEN)
VI

RI5
1.5K

05
",,,,999

RI6
4.7K

07
",,,,999

RI4
5K

02
IN758A
03
IN750A

81
RIO
.300

A2
R2
330

RI3
330
1/2W

04
DEC3790

1%
R8
909
1/8W
R3
180

RI2
330
1/2W

05
0671

R7
IK
1/8W

C'}

C4
(-24V)
RI

RI7
7.5K

C3
I",FD
35V

CI
6.8",FD

UI
(+SEN)

- 35V
+
UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 ",FD
RESISTORS ARE 114W,5%
EI IS MCI709CG

04
0662

C5
IMFD
35V

C2,TI,MI,GNO
02
DEC3009
02 (BUS)

TRANSISTOR & DIODE CONVERSION CHART
DEC

0662
0664
0611
I 75
rN750A

£lA

IN645

IN3606
IN36!53
SAME
SAME

DEC

MM999
DEC3790
DEC6534C
DEC3009

£lA

SAME

2N 3790
MPS6534
2N3009

mamaama

EQUIPMENT
CORPORATION
...... YN .... O ...... s .... C .... U.ETT.

TlTLr-24V REGULATOR
CONTROL G823

000 0°0 00 0

8
0
80
80
.

•

G823-3

G825
-24V Pass Element

The G82S module contains the power stage of the -24V regulator, which is controlled by the -24V regulator
control module G823 to supply the regulated -24V for the memory of the PDP-IS. Refer to the description
of the G823 module.

G82S-I

THIS SCHEMATIC 15 FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCDROINGL Y
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

TAB
-30V

+
-"

." :::50MFD
50V
10%

AJ 2
BASE

AV2
T.P

ABI
T.P
R3
1.5K

C')
00

~ALI

R2
.1

RI
.1

- 24V

"" AV ',AR', BAI, BBI,BEI
SF ',BKI,BLI,BPI,BRI

~~~D

.r. AM I, AUI, BCI,BD\BHI
BJI, BM',BN',BSI,BUI

UNL.ESS OTHERWISE INDICATED:
RESISTORS ARE 5W, 5%
TRANSISTORS ARE DEC 3790-1

DRN

<n"
Z

<a~
> u"
w
Q:

l--

5t - -

DATE

""i'a.- r-.2J"'"
~~~aI~ 1~:?~
~}".c....n. '/."lil"i
PROD

DATE

TRANSISTOR & DIODE CONVERSION CHART
DEC

DEC3790

EI.

2N3790

DEC

EI.

TITLE

mamaoma I

-24V PASS ELEMENT G825

EQUIPMENT SIZE
B
CORPORATION

....... " .... ~O. "'''SSACHV SETTS

CODE,

NUMBER

G825-0-1

PRINTED CIRCUIT REV

REV

JEtiJJJJJJ

G827
Power Sequence Detector and Delays

The G827 module contains a level detector, three RC networks, and an open-collector driver. This module is used
in the I/O processor of the PDP-IS. (Refer to Engineering Drawing D-BS-KPIS-O-S7.) The level detector is used
to detect a power-low condition in the 11 V supply and sequence the memory power off. The RC networks are
connected to the K303 timers to establish the timer delays, and the open-collector driver is used to energize the
memory power relay in response to the memory OK signal.
Power dissipation of the G827 module is SV at 144 rnA (maximum).

G827-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

4 IIV

_~•. -_ __

v
A

2~U
30-----,

AMP. SOCKET
1-480459
DECI209340

RI
IK
il8W
1%

•

L3.

•

~
6

N
-...I

6~L

IIBW

•

+5V

.---

Q2
DEC6534C

....LC3
'1'2.2
MFD
20V
10%

....l...C4
'I'.47MFD
35V
10%

8~'~OO'r±~~, f j f j f j",,,
R9
lOOK

R4
220

) 13

.---

:""'C2
.:T'IOMFD
20V
10%

3L-14

R2
1.21K

• R5
IK

g:64~

R3
330

C)
00

• R6
330

D664~1:

RS
180K
10%

R7
12K

8"" MEM. RELAY

UNLESS OTHERWISE INDICATED
CAPACITORS ARE 100V,20%
RESISTORS ARE 1/4 WI 5%
PIN70NEI·GND
PIN 140N EI'+5V
EllS DEC 740lN
E2 IS MC 1709CG

DRN
q~

DATE

"'C"

l5""? ~,p. IZ'Z),H

I'1.T tz.-- ~~/6~
PROD

DATE

TRANSISTOR & DIODE CONVERSION CHART
DEC

EI'

0664

IN3606

DEC3009C
DEC6534

I:!N3009

MPS6534

DEC

EI'

momoomo

EQUIPMENT
CORPORATION

....... "."' ..... 0

...... S!l ... CHUSItTTS

POWER SEQUENCE DELAYS
AND DECODER G8 27

I v~ I

88
00~G~0GG0

8
L

J
G827-3

G829
Power Connector

The G829 module is a power connector with over-voltage, under-voltage, and over-current protection circuits.
This module connects the +SV to the peripherals of the PDP-IS. Combinational logic circuits are also included
in the module to provide lamp driver and power OK signals when the peripheral voltages are within set levels.
Rotating the voltage detection potentiometer CCW lowers the low voltage limit. The potentiometer is normally
set to detect voltage below 4.7SV. The input power connections to the module are made with an 8-pin matein-lock connector at the back of the module.
The following are the input, output, and power characteristics of the G829 module.
INPUTS:

The inputs to the G829 module are +SV, +IOV, -ISV, and ground. These voltages are supplied by the 721 power supply. The module also receives positive power OK signals from
associated power supplies.

OUTPUTS:

The outputs of the G829 module are:
a.

+SVat lOA (maximum) with the same regulation as the input, +lOY at 2.SA (maximum) with the same regulation as the input, and -ISV at 3.SA (maximum) with the
same regulation as the input;

CONNECTOR

---l

<5V

I O---:-I-'---=--'---iL.._FU_S_E~I------1'--------'----- ~~~!~~_'!!'_~~_
SEE SCHEMATICS

OVER
VOLTAGE
DETECTION

30---'-1-'

UNDER
VOLTAGE
DETECTION

CROWBAR

4 0------'-+

GND
5 o--:---,~'-'-=-------------4o----t--_----- AC2.AH2.AK2

sEE-scHEMATics
BNI

I
I
I

> - - - - B R I (MEM PWR OK)
BPI

> - - - - BMI (LAMP DRIVER)

67:~I~~1+~lo~v

___________________________

BM2.BJ2.BKI

I
00-----:----'-::....:...--------------------___
J
8

-15V

AB2. AE2. AF2

15-0131

G829 Simplified Diagram

G829-1

•

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ,lCCORDINGLY.
COPYRIGHT 1970 BY DIGITAL EQUIPMENT CORPORATION

AMP. CONN.
1-480459

.---I
~

b6- I--

R3
.I
5W

CI3 ;

;,
~
7

_; i'C4
~ ~ ~;bu/ ~;gU/ i'C3
ISOut
ISV
20%

ISV
20%

RS
100

R6
IK

15V
20%

R9
100

AJ', AK1 ,ALI
ASI,+5V

RIO
I.SK

• 02
R4

47QI
OEC65348

C5
S6pt
'~V,5%

1 " 1 fP

+IOV
Va
-ISV
6

BNI

L----

,I. 01

GNO

~~\:2g~e9.k
~~::t'I,~~11

I~MP

+SV

N
\0

4
s J EI

BPI

RII
IK

DEC6,5348

BRI

~Q2

...

RI2
47

~
12

RI3

R20
IK

OS
i\N4441
RI7
IK
~

RIS
47

-J
_--'I~~~k _
I+f:%__L

-ISV,AB2,AE2,AF2

~uf

g6uf

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 33O,1I4W,5%
CAPACITORS ARE .alut,100V,20%
DIODES ARE 0664
TRANSISTORS ARE OEC30098
EI IS DEC 7401
PIN 7 ON EI =GNO
PIN 14 ON EI = +SV

,'Se::c:::- Fe
,~

C9
~k: 50ut

CII
I uf
3SV
10%

CI2

;i'~~
10"1.

1 ~Q7

R21
IK
1/2W

Rl9
I.SK

R22
IK

~~~

,-I)

RI8
2.2K

20%

:E~~28~~2
A02:BH~,BK2

BL2, BTl, AN2
GNO

CIO

i-M~
_T
+}·S.D _______

____

.-.

(JQB

RI6

8MI

RI4

a ... ~

Ell ....

..L.,.."

This page intentionally left blank.

G829-3

.
AMP. CONN.
1-480459

.---

+5V

BBI,eCI,BDI

IDAMP

BEI,AA2,BA2

ABI,6.CI,AO!

AEI,AFI,A.HI

6- t -

+
CI3

CI
150uf
15V
20%

~ t5

+
C2

ISOuf

ISV
20°/0

C3
150uf
15V
20%

7
~

N
\0

R'
C5
!56pf

BNI-

~
,

.j,..

~
12

RI3

A'
j\N4441

-151/, AB2,AE2,AI'"2.

f~~%

UNLESS OTHERWISE

INDICATED"

RESISTORS ARE

330,lI4W,5%

C9
50uf

}o; C6
+

+~~~/o

BMI
06

g6ut
+'.fs%

Lr)

RI'

R20
IK

RI5
'7

2!>V

DEC65,34B

RI.

f? a'
1 \!:::,

RII
I.

RI2
47

+F~~f

RID
1.5K

IOQV,5"fo

BPI-

R9
100

t : f :EI} 1 0

-15V

~02

~OlOEC65348

L-

'-------.,

tlOV

BRI

R.
I.

If 02

GNO

R5
100

AJI,AKI,ALI
A51,+511

+lCII

r~~

10%

r ~I~~

!O%

IN748A

~T(~

RI6
2.2K

RI9
1.5K

R21
I.

1/2W
20%

R22
I.

• <X>

~~~~2e~~2

:E~;:~~::~

CIO

GNO

~
8M2, BJI, BKI,+IQV

CAPACITORS ARE .Olut, 1001/,20%
DIODES ARE 0664
TRANSISTORS ARE DEC30098
EI IS DEC7401
PIN 7 ON El ='GND
PIN 14 ON £1 = +5V

momoamo

';;OWER CONNECTOR G829

EQUIPMENT SIZE
CORPORATION I

CODE

c I Cs I

GS29-?-1
IA

.... ~ ....... CI .......... " ......... TT.II'Allil(O CllI.CUll 11.["

DtC fORM HO
ORC 102

i'15{'c::- Fe

;~
~N
'"

.l..

DIS"'T, 3""Y,4~"f14~S

1 1
CONNECTOR

FUSE

1 1

I
I

G
03
RI7

I
I

RI9

RIB
R20
R22

88
I

CI2

RIO
R9

RII

CII

0I
RI5

RI2
RI4
RI3
RI6

o01

8
EB
RI

C'l

00
N

'P
Vl

G829

G858
Teletype Connector

The G858 module contains a level converter, an open-collector driver, and interconnecting wiring. The module is
used as a Teletype connector for the PDP-IS, serving as the interface between the Teletype receiver/transmitter
(M706 and M707) and the Teletype. The converter changes the OV and +30V levels received from the Teletype
to OV and +3V levels for the receiver/transmitter, and the driver provides the reader run drive current for the
Teletype.
The following are the input, output, and power characteristics of the G858 module.
INPUT:

Input pin M2 (the reader run in) presents 4 unit loads.

OUTPUT:

Output pin E2 (the Teletype keyboard in) is capable of driving 30 unit loads.

POWER:

Power dissipated in the G8S8 module is SV at 12 rnA and 30V at 30 rnA.

G8S8-1

~
'A3"

r ---

~----u
1-0- 898!>
S3 J~~
8

"3B~nN

3000 3ZIS

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THEJ
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

RI
220,10%

5 (7) (H)

~~------------------------------------------o H

•

0 A +5V

;>
R3
•
6

('l
00

0 M

(+RELAY) (M)

0 V +30V

• •

TO AMP.
CONNECTOR
# 1-480459-0

<' RII

R6
470
IW
10·'
,.

(4)(N)

R8
470
IW 10%

(- RELAY )(K)

2Rlo
01
~

03
DEC6531

RIO
4.7K

(6)(F)

; ' ' ,'

D6
D670

f I ~t~i
t

I~'" 1!

<R5

D4
D5

o C GND

UNLESS OTHERWISE INDICATED:
DIODES ARE D664
RESISTORS ARE IK, 114W,5%
AMP. CONN. PINS ARE 1161320-\
* REMOVE AT 300 BAUD
**REMOVE a INSTALL JUMPER FOR LA30

DRN.

_.-."

,DU/Z.E

IDATE

.,y:4Y6~ L

TRANSISTOR & DIODE CONVERSION CHART
DEC

EIA

IN3606
IN3653

~~~~534
DEC FORM NO
DRB 102

no,

co.

'_"."".11
~

TITLE

•

11I:.I1Il;J1l1iI~1I
E a U I
MEN T

PDP-15 TELETYPE
CONNECTOR G858

:.~~;'M:>'~A-;"~"~~ I--L--L----'----,-,---,.---,.--.---r--'r---r

DI '3T.

1'1, 'IJlI,ll $ ';.3

,JINI<...

K303
Timer

The K303 module contains three timers that are triggered by a level change from HIGH to LOW.
K303 timers provide time delays from 10 JlS to 30 sec and can be interconnected to form clocks with periods
covering the same intervals. Fixed or adjustable delays and frequencies are obtainable. Calibrated controls are
available (K371 through K378) for mounting directly on the K303. Remote controls can also be added, if desired.
When a K303 input gate steps to zero, the uninverted output falls after a controlled interval, while the inverted
output rises (see simplified illustration). The interval can be as little as 10 JlS or as long as 30 sec, depending on
the size of the Rand C connected to pin J, P, or V. Recovery begins when the input gate rises to logic 1. A
recovery time of at least 0.3 percent of the maximum delay obtainable from the capacitor is required in order to
guarantee 95 percent repeat accuracy in the delay.
A positive step at the input gate resets the K303 timer outputs. If the step occurs before a timeout is complete,
the timeout is terminated and no change appears at the outputs. This property is sometimes convenient for
establishing a pulse repetition-rate threshold (frequency setpoint).
A built-in 2.2 nF timing capacitor assures adequate noise rejection when external capacitors are mounted several
inches from the timer. Time threshold for resetting is always several percent of rated recovery time. Thus, noise
rejection time increases in proportion to the size of the timing capacitor. If remote rheostats and timing
capacitors are used, noise rejection is degraded. If several timing capacitors are to be switch selected, the smallest
capacitor is wired near the module; and the other capacitors are switched in parallel with it.
For additional information, refer to DEC's Digital Logic Handbook, 1970 edition.

RECOVERY TIME....j

I--

r - - - - - l,,
I

~
NOTE
K374, K376,K378 PROVIDE
TIMING COMPONENTS FOR
THIS CIRCUIT.

15-0128

K303 Simplified Diagram

K303-1

fHIS SCHEMATIC IS FURNISHED ONLY FOR nSf AND MAINTENANCl PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1967 BY DIGITAL EQUiPMENT CORPORATION

A + 5V
R2
750
5%

~RIO

R5
1,800

1,800

RII
1,800

RI3
~R15
1,800
750
5%

RIG
100

RI8
1,800

R23
11 800

-<> J

R8
4,700

RI
750
5%

R39
1,800

014

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DEC
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R21
4,700

R34
4,700

C3
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MFO
GMV

015

Oil

CIO

C5
0.0022
MFO
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DISC

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0.0022
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R37
1,800

1,800

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05

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R31
1,800

R28
750
5%

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DEC
2219A

R26
1,800

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DEC
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7150
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R27
750
5%

RI7
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10,000 ? 10pOC

10,000
10,000
(3
0
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UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DECI
DIODES ARE D600
RESISTORS ARE 1/4W, lOok
CAPACITORS ARE 680 MMFD t 10%
ERIE 309 OR EQUIV.

... v

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SIDE

PARTS LIST IS A-PL- K303-0-0
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.-18-67

CHK'9

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15-0148

M002
Logic 1 Source

The M002 provides IS outputs at +3V (logic 1) on pins D2 through V2 to hold unused M-series TTL gate inputs
HIGH. Up to 10 unused M-series gate inputs can be connected to anyone output. If a M002 circuit is driven by
a gate, the M002 circuit appears as two TTL unit loads, or 3.2 rnA at ground.
Power dissipation of the M002 module is +5V at 16 rnA (maximum).

M002-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST ANO MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY

"I, BY DIGITAL EQUIPMENT CORPORATrON

A
RI6

RI7

Rig

Ria

R20

R21

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R25

R26

R27

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R29

R30

~F ~E ~D
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RI4

+5V

C GND

RI5

N
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R16- R30
RI - RIS
CI

1------------------1
... ..... .. .......
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mamaDma

TITLE

".. ... VN .... P. M". . . .CHU.II:TT.

PRINTED CIRCUIT REV.

EQUIPMENT
CORPORATION

1301428
1300439
1001610
A-PL-MOQ2-0-o
PART NO.

15 LOADS MOO2
SIZE, CODE

NUMBER

MOO2-0-1

REV.

IAI I I I I I I

M101
Bus Data Interface

The M 10 1 contains fifteen, two-input NAND gates. One input of each gate is tied to a common line so that all
data signals on the second input of each gate can be enabled simultaneously. The M 10 1 can also be used as inverters or a data multiplexer. All data inputs are protected from a negative or more than -O.8V.

INPUTS:

Each data signal input presents one TTL unit load. The common line input
presents fifteen unit loads.

OUTPUTS:

Each output can drive ten unit loads.

POWER:

+5V at 82 rnA (max.)

MlOl-l

..,

I - 0 - IOH'l

M3~"'QN _. _

'A3M

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION

kS~
8 j
3000 31IS

A2 +5V
ICI
C2,TI GND

CI
AI

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F2

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S2
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C 1- C4

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.........

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REFERENCE DESIGNATION
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SIZE

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PARTS LIST
DESCRIPTION
PARTS LIST

EQUIPMENT
CORPORATION

> r 0
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INTEGRATED CKT. DEC7400N
010 DE 0664

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1905575
1100114
1001610
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PART NO.

M103
Device Selector

The M I 03 module is used to decode the six device bits transmitted in complement pairs on a positive bus in a
digital system. Selection codes are obtained by selective wiring of the bus signals to the code select inputs; D2, E2,
F2, H2, 12, and K2. The M I 03 module also includes pulse buffering gates for the lOP signals found on the positive bus in digital systems. Two 2-input NAND gates are also provided for any additional buffering that is required.
The following are the input, output, and power characteristics of the M I 03 mod ule.
INPUTS:

All inputs that receive positive bus signals are protected from negative voltage undershoot
of more than -0.8V. The following inputs each present one TTL unit load: D2; E2; F2; H2; 12;
K2; HI; 11; Ll; and MI. Inputs P2, R2, and S2 present 2.5 TTL unit loads. Inputs U2, L2,
and N2 each present 1.25 unit loads. These inputs do not need to be tied to a source of
logic I when they are not in use.

OUTPUTS:

Gate outputs K I and N I can each drive ten TTL unit loads. Pulse buffering outputs A I, B I,
CI, DI, EI, and FI can each drive 37 TTL unit loads. The Option Select output can drive
16 TTL unit loads.

POWER:

The power dissipation of the M 103 module is +5V at 110 rnA (maximum).

M103-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION

'+I' I :>

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E2

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---- ---------------I
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REFERENCE DESIGNATION
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DEC
DEC3009B
0664

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IN 3606

DATE

DEC

EIA

ITRANSISTOR DEC3009B- S
INTEGRATED CKT. DEC7400N
INTEGRATED CKT. DEC74H40N
I INTEGRATED CKT. DEC7430N
RES. 330
1/4W 5% CC
RES. 750
114W 5% CC
RES. 8.2K 114W 5% CC
IDIODE D664

1503100
1905575
1905586
1905578
1300295
1301401
1303179
1100114

I CAP• . 0IMFD 100V 20% DISC
PARTS
LIST
DESCRIPTION
PARTS LIST

1001610
IA-PL-MI03-0-0
PART NO.

mamaama

TITLE

DEVICE SELECTOR M 103

EQUIPMENT
CORPORATION

SIZEICODEl

""'''VNAIltD, ""'''' • • ''CHU8ETT.

PRINTED CIRCUIT REV.

NUMBER

M 103-0-1

~ST. £.1.'11'13'1 }13;--'

lei I I I I I I
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M104
1/0 Bus Multiplexer

The M 104 module has been designed specifically for controllers of PDP-IS peripherals. It is used in all controllers
that make use of the API or data channel facilities in the I/O processor. It accepts a request from the controller
logic at its FLAG (1) H input and synchronizes this request to the I/O SYNC H pulses issued from the I/O processor. These pulses are fed into SYNC of the MI04 and immediately set the REQ flip-flop. The REQ flip-flop can
be monitored through pins J2 and U2. The I/O processor responds to a request with a GRANT, and ENA is set.
This flip-flop is generally used to gate any address information onto the bus; e.g., the API trap address or the word
count address of the multicycle data break. The next SYNC pulse sets ENB.
The REQ flag can be reset through pin F2 (CLR RQ) by the controller logic. Pin N 1 should be tied to power
clear or its equivalent.
The Enabling level ENABLE IN holds REQ off if ENABLE IN arrives as a negative level. When REQ is set (if
ENABLE IN is positive), ENABLE OUT goes negative; and the next peripheral on the bus receives this level as a
negative ENABLE IN. In this way, the M 104 establishes priorities among devices on the same API level or among
devices that use the data channel. See the timing diagram for additional information.
The following are the input, output, and power characteristics of the M104 module.
INPUTS:

OUTPUTS:

The inputs are standard TTL voltages and have the following input pins and loads:
Input Pin

Load (Units)

H2
S2
HI
E2
Nl
F2
K2
S2

2.S
1
6
3
1
1-1/4
68il Termination
1

The output gates can drive as follows:
Output Pin
U2

12
PI
Sl

El
Fl
M2
11

POWER:

Number of Loads Pin Can Drive

S
8
9
10
10
10
PDP-IS I/O Bus
Compatible (30 units)
7

The power dissipation of the MI04 module is lW at SV.
MI04-1

1
110 SYNC

REQ EN

REQ

1
0

GRANT H

•

CLR REQ

0 ----4-..1

1 -----~~~-_+-----~-~-----

1
ENA

0 - - - - -....

ENB

0 - - - - - - - - -.....

AJI is ASSUMED TO BE WiRED TO F2
15 -0017

M 104 Timing Diagram

MI04-2

This page intentionally left blank.

Ml04-3

I -O-vOI ~

M3B~nN.

'A3M

1S:J 18 J
lOO~

l.zIS

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

C3
~L

H2 -

tE~N~:.:.:IN:....:H~_ _ 'T

~C2

*CI

+5V
A2

F2 CLR FLAG L

HI I 0 SYNC H

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S2 FLAG H

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R. GUTIERREZ

DATE
3-13-69

CHK'D
A.YAUGA
ENG.
J. GODBOUT

DATE
3-17-69
OATE
4-7-69

PROD

DATE

~
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SIZE

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CAPACITORS ARE .01 M FD, 100V, 20%
RESISTORS ARE 1/4W,5%
EI,E4 ARE DEC7474
E2 IS DEC7400
E3 IS DEC74H40
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V

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NUMBER

MI04-0-1

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THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULO BE TREATED ACCORDINGLY.
COPYRIGHT I'" BY DIGITAL EQUIPMENT CORPORATION

BI
,

A2 +5V

F2
R2
C3:::;:::C4
RI

==
.....

•

C2, TI

GND

NOTE~:

PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC
1-5V

gE4
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1905575
1301401
1001610
A-PL-M',,-O-O
PART NO.

"O-DD'.O'TITLE
W iI
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INVERTER Mil I
a U I P MEN T f-.:SI;;ZE'T.C:;;O"O' '---;:;N;7,UM;;;O' 'O.----',.iC,v;-1

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MII'-Q-'

M112
NOR Gates

The M112 module contains ten 2-input NOR gates, each performing the function NOT (A + B). Pins U I and V I
provide +3V, and each are capable of holding HIGH (logic 1) up to 40 unused M-series inputs. Propagation delay
is 22 ns (maximum).
The following are the input, output, and power characteristics of the M 112 module.
INPUT:

Each input presents one unit load.

OUTPUT:

Each output can drive up to ten unit loads.

POWER:

The power dissipated in the M 112 module is +5V at 50 rnA 6:naximum).

MI12-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE

CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION

AI~
II
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CI
BI
01

~
4

LI
FI

D2~
8
EI
F2
;s::

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JI

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A2
+5V

1 1
11

......

T2~
2
E3
I
V2

H2~
2
E2
I
K2
J2
E2

P2
NI

L2~
E3
N2
8

~UI

~VI

C2,TI
GND

CI,C2 , C3
E I E2 E3
R2,R4
RI, R3

NOTES:
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V

REFERENCE DESIGNATION
--->
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;,,;;,~

DATE
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RES. 330 1/4W 5% CC
RES. 750 1/4W 5% CC
PARTS LIST
----DESCRIPTION
PARTS LIST

1001610
1909004
1300295
1301401
A-PL-MI12 0-0
PART NO.

TITLE

~DmDDmD I NORGATEMI12
I
IR~V

EQUIPMENT
CORPORATION
...... y ...... "D, ........... C ... U.I[TT.

SIZE

CODE

NUMBER

MI12-0-1

PRINTED CIRCUIT REV

IDI I I I I I I

M113, M115, M117, M119
NAND Gates

The M113, MIlS, M117, and MI19 modules provide general purpose gating for the M-series. They are most
commonly used for decoding, comparison, and control. Each module performs the NAN D function NOT
(A' B - - - - - - - - N), depending upon the number of inputs.
The modules and their descriptions are as follows:
Ml13 - Ten 2-input NAND gates that also can be used as inverters;
MIlS - Eight 3-input NAN D gates;
Ml17 - Six 4-input NAN Dgates;
Mll9 - Three 8-input NAN Dgates.
Unused inputs on any gate must be returned to a source of logic I for maximum noise immunity. In the M113,
M117, Ml19, M121, M617, and M627 modules, two pins (VI and VI) are provided as a source of +3V for noise
immunity. Each pin can supply up to 40 unit loads. Modules M103, MIll, and M002 provide additional sources
of logic I level. Typical propagation delay of these gates is 15 ns, and maximum propagation delay is 22 ns.
The following are the input, output, and power characteristics of these modules.
INPUTS:

Each input presents one unit load.

OUTPUTS:

Each output is capable of supplying 10 unit loads.

POWER:

Power dissipation for the respective modules is:
MIl3:
71 rnA }
MIlS: 41 rnA
41
rnA
+maximum current at SV
MII7:
M119: 9mA

MIl3,MlIS,MI17,M119-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIHARY IN NATURE AND SHOULD BE TREATED ACCORDINGL Y
COPYRIGHT
BY DIGITAL EQUIPMENT CORPORATION

I"r

+5V

- - - - A2

NOT USED -15V - - - - 8 2
GND - - - - C 2 . TI
CI

.....

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NI

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+5V

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VI
BV

C2
GND

-.l

:l
0..

~
LI

'-0

NOTES:
PIN 7 ON EACH IC GND
PIN 14 ON EACH IC = +5V

L2 M2

P2 R2

E I THRU E3
RI AND R3
R2 AND R4
ClAND C2
REFERENCE DESIGNATION
TRANSISTOR & DIODE CONVERSION CHART

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PARTS LIST

1905575
1301401
1300293
1001610
IA~PL-M"3~0-0

PART NO.

THIS SCHEMATIC IS FURr.ISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY

'1,7

BY DIGITAL lQUIPMENT CORPORATION

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REFERENCE DESIGNATION

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mamaO!O

EQUIPMENT
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...
...... ss ... C ... USETTS
",.."'''~o,

TITLE

SIZE

1905576
1001610
A-PL-MII5-0-0
PART NO.

8-3 INPUT
NAND GATES MI15

CODE

NUMBER

MI15-0-1

PRINTED CIRCUIT REV

IR~V

101 1 1 1 I I I

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULO BE TREATED ACCORDINGLY
COPYRIGHT 1117 BY DIGITAL EQUIPMENT CORPORATION

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REFERENCE DESIGNATION
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RES. 750 1/4W 5% CC
RES. 330 1/4W 10% CC
CAP•• 01 MFD 100V 20% DISC
PARTS LIST
OEseR I PTION
PARTS LIST
TITLf

1905577
1301401
1300293
1001610
A-PL-M 117-0-0
PART NO.

6-4 INPUT

GATES MI17
~lmDDmD I NAND
II
I

EQUIPMENT
CORPORATION
..... .,N ... "C) . . . . . . . . . C ... U.I:TTS

Silt

CODE

NUMBER

MI17 0-1

PRINTED CIRCUIT REV

R~V

lEI I I I I I I

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST ANO MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1961 BY DIGITAL EQUIPMENT CORPORATION

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PIN 14 ON EACH IC • •• V

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PARTS LIST

JNPUT NAND-GATES
MI19

mamaamD lCOOfl
TI"'3-8

EQUIPMENT
CORPORATION

SIZE

.............. "'D .......... CHV • • TT.

PRINTED CIRCUIT REV.

1905578
1300293
1301401
1001610
A-PL- M1I9-o-0
PART NO.

NUMBER

MI19-0-1

IRaY

lei I I I I I I

M121
AND/NOR Gates

The M 121 module contains six ANDjNOR gates that perform the function NOT (AB + DC). The exclusive OR,
coincidence, and NOR functions can be performed by proper connection of signals to the AND inputs. Maximum propagation delay of an M 121 gate is 22 ns.
The following are the input, output, and power characteristics of the M 121 module.
INPUTS:

Each input presents one unit load to the driving module.

OUTPUTS:

Each output is capable of driving up to 10 unit loads.

POWER:

Power dissipation of the M 121 module is +5V at 50 rnA (maximum).

M121-1

THIS SCHEMATIC IS FURNISHED ONLY fOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT I'll BY DIGITAL EQUIPMENT CORPORATION

~J_UI

a::

F
4

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+5V

-1.c21

1C4
C2,TI

GND

NOTES:
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V
EI THRU E3
R28 R4
RI 8 R3
CI THRU C5
REFERENCE DESIGNATION

DATE

~~=C'---f.~:,;;:'~:-_4--j'

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D'C

DEC

INTEGRATED CKT. DEC7450N
RES. 330 1/4W 10% CC
RES. 750 1/4W 5% CC
CAP•. 01 MFD
IOOV
20% DISC
PARTS LIST
_ ~_D~CRIPTION
PARTS LIST

JIIO-OO-O

I:J

1905580
1300293
1301401
I 1001610
/A-PL-MI21-D-0
PART NO.

AND-NOR GATE MI21

Tf.ccSl~ZE~C"'O"'DEo-_.----::N"'UMCC."'Ecc' - - - -

E QUI PM E N
CORPORATION

...... " .... AO ...... ss ... C .... U,."TTS

MI21-0-1

M127
AND/NOR Gates

The M 127 module contains three general purpose AND/NOR gates that perform functions similar to the M 121
module. By connecting signals to the AND inputs, these gates can be used to select and to place on a single output any of several input signals. Propagation delay of an M 127 gate is II ns (maximum).
The following are the input, output, and power characteristics of the M127 module.

INPUTS:

Each input presents 1.25 unit loads.

OUTPUTS:

Each output is capable of driving 12.5 unit loads.

POWER:

Power dissipation of the M 127 module is 5V at 100 rnA (maximum).

MI27-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

loll

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H2

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UNLESS OTHERWISE INDICATED
CAPACITORS ARE .0IMFD
RESISTORS ARE 1/4 W 5"1.
IC'S ARE DEC 74H53
PIN7 ON EACH IC =GND
PIN 14 ON EACH IC, GND

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TlTLEZ-Z-Z-3 AND / NOR GATE
MIZ7
SIZE

CODE

NUMBER

101127-0-1

M129
AND/NOR Gates

The M129 module contains four general purpose AND/NOR gates that perform functions similar to the M121
module. By connecting signals to the AND inputs, these gates can be used to select and to place on a single output any of several input signals. Propagation delay of an M 129 gate is II ns (maximum).
The following are the input, output, and power characteristics of the M129 module.
INPUTS:

Inputs H2, L2, NI, and V2 present 2.5 unit loads, and the remaining inputs present
1.25 unit loads.

OUTPUTS:

Each output is capable of driving 12.5 unit loads.

POWER:

Power dissipation of the M 129 module is 5V at 50 rnA (maximum).

M129-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT . .I . BY DIGITAL EQUIPMENT CORPORATION

DI=m
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12
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UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFD
IC'S ARE DEC 74 H55N
PIN 7 ON EACH IC:GND
PIN 14 ON EACH IC: +~V

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1II0-00-D
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TITLE

ANO/O R I NVERT GATE
M12 9
COOf

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B
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M 129 - 0 - I
I:~~~~'~ I~_: • 'I 1====r====1I====1===~ =~~,;_c:.~.~;:,~~~ ~~L.=:~~=-'--l.nIITTI1

M133
NAND Gates

The M 133 module contains ten 2-input NAND gates, each performing the function NOT (A' B). The module is
used for general purpose high-speed gating. Maximum output propagation delay to a logic I or 0 is IOns. The
high-speed characteristic of these gates frequently solves tight timing problems in complex systems. Unused inputs on any gate must be returned to a source of logic I for maximum speed and noise immunity.
The following are the input, output, and power characteristics of the M 133 module.
INPUTS:

Each input presents 1.25 unit loads.

OUTPUTS:

Each output is capable of driving 12.5 unit loads.

POWER:

Power dissipated in the M 133 module is +5V at 130 rnA (maximum).

M133-1

THIS SCH~MATIC IS ~URr-.ISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION

•

R4
330
114W
10%

R2
330
1/4W
10%

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C5
6.BMFD
10V

IC3

IC4

10%

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+3V

~
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R3
750
1/4W

5%.
I

•

•••••

C2, TI GND

UNLESS OTHERWISE INDICATED:
E I - E3 ARE DEC74HQON
PIN 7 ON EACH Ie = GND
PI N 14 ON EACH Ie = +5V
CAPACITORS ARE .01 MFD, fOOV, 20%

M. HALLER

~~~E.681

CHK'O

DATE

W. MULLEN

8 -9-68

ENG

0.0 'CONNOR

I~A.~E~_6E

PROD

DATE

DRN

"
0
0
0

TRANSISTOR & DIODE CONVERSION CHART
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CIA

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......... N ... ~O ........... CHU.IETT.

TITLE

SIZE

10-2 INPUT
NAND GATES MI33

M135
NAND Gates

The M135 module contains eight high-speed 3-input NAND gates that perform the function NOT (A' B·C). These
gates are most commonly used for decoding, comparison, and control. Unused inputs on any gate must be returned to a source of logic 1 for maximum speed and immunity. Propagation delay of an M135 gate is IOns
(maximum).
The following are the input, output, and power characteristics of the Ml35 module.
INPUTS:

Each input presents 1.25 unit loads.

OUTPUTS:

Each output is capable of driving 12.5 unit loads.

POWER:

Power dissipated in the M135 module is 5V at 90 rnA (maximum).

M135-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1919 BY DIGITAL EQUIPMENT CORPORATION

1 I II II IIC~

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L2

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NI

10
9

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10
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52

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R2

UNLESS OTHERWISE INDICATED
IC'S ARE DEC74H 10
PIN 7 ON EACH IC, GND
PIN 14 ON EACH IC' +5V
CAPACITORS ARE 01 MFO 50V

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TRANSISTOR & DIODE CONVERSION CHART
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DEC

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"'D.DD~D
~

3 INPUT NAND GATE

M 13 5

~~""'-="'-"~~Cf1~====t====1I-----+-----I~g~~;R~;I~~ S~E C~~E MI35:uO~E~
PRINTED CIRCUIT REV

TATfTTlTI

M139
NAND Gates

The MI39 module contains three high-speed 8-input NAND gates that perform the NAND function NOT
(A· B ... N), depending on the number of inputs. These gates are most commonly used for decoding, comparison, and control. Unused inputs on any gate must be returned to a source of logic I for maximum speed
and noise immunity. Propagation delay of an Ml39 gate is 10 ns (maximum).
The following are the input, output, and power characteristics of the MI39 module.
INPUTS:

Each input presents 1.25 unit loads.

OUTPUTS:

Each output is capable of driving 12.5 unit loads.

POWER:

Power dissipated in the M139 module is 5V at 40 rnA (maximum).

M139-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. T. HECIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

~ l a

1- 0 - 6£ 1W [ s:J

M38~nN

. ·A3M

300~

I8 I
3ZIS

...

A2
r-----~·.------4·.-----~·.------·.------·.------e·------+ev

UNLESS OTHERWISE INDICATED:
IC'S ARE DECI074H30
PIN 7 ON EACH IC =GND
PIN 14 ON EACH IC =+5V
CAPACITORS ARE .01 MFD, 100V,20%
RESISTORS ARE 1/4W,5'Yo

>R I

~ 330
*CI

--'l'C2

+
l'C3

l'C4

--'-C5

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10V, 10%

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Lj----~~--~~---*----~----~--~.--- C2,TI,
GND

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0 00
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DEC FORM NO.
ORB 102

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DATE

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~K'D

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DATE ~1

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TITLE

mamaoma I 1

3-8 INPUT NAND GATE
MI39

EQUIPMENT
CORPORATION

-7-

DATE

MAVNAIIID. M" • • ,.,CHuaETTa

SIZE

CODE

PRINTED CIRCUIT REV.

Pt57.

NUM8ER

M 139 - 0 - 1

161 I

324, ~ 34, IiJ,>:L

REV

'-1 III
PINK

M149
NAND Wired OR Matrix

The M 149 module contains two sets of nine open-collector NAND gates. The NAND gates are OR wired
together onto nine output pins having the standard TTL output levels. Each set of NAND gates is connected to
operate in conjunction with a separate enable gate. The M149 module is used to gate desired signals onto an
open-collector bus. (Refer to Engineering Drawings D-BS-KPlS-O-38 through D-BS-KPlS-O-43, and
D-BS-KP1S-0-60 through D-BS-KP1S-0-62).
The following are the input, output, and power characteristics of the M149 module.
INPUTS:

Each input presents 1 unit load.

OUTPUTS:

Gate outputs are all open-collector and can sink 16 rnA (maximum). The pulse amplifier
output is capable of driving 10 unit loads.

POWER:

Power dissipation of the M149 module is SV at 130 rnA (maximum).

M149-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

•

•
E2

•

a::

......

V2
UI

--1-----------21\
VI

P2
E3

•

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UNLESS OTHERWISE INDICATED
PIN 7 ON EACH IC ~ GND
PIN 14 ON EACH IC ~l-5V

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E3 IS DEC7400N
RESISTORS ARE 1/4W 10%
CAPACITORS ARE .OIMFD,IOOV,20%

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9X'2 NAND WIRED
OR MATRIX
MI49
SIZ'

CODE

NUMBER

REV

MI49-0-1

1---=--'--:c-:-L:::-:=----'-::TIlirl"n1

M159
4-Bit Arithmetic Logic Unit

The M159 4-Bit Arithmetic Logic Unit (ALU) module contains a single DEC? 4181 integrated circuit. Nine of
these ALU modules are used in the FP 15 Floating-Point Processor to perform 36-bit arithmetic and logic operations, as shown on D-BS-FP 15-0-19 through -28 of the FPl 5 drawings.
The integrated circuit is capable of performing 16 4-bit arithmetic operations when the MODE control and CN
inputs are low and 16 logic functions when the MODE control input is high. The functions are selected by applying combinations of function select inputs SO through S3. For FPlS applications, the function select and
MODE control inputs are generated by the adder control logic shown on D-BS-FPlS-0-33 of the FPlS drawings.
Only two arithmetic operations, A plus B and A minus B minus 1, are selected. Five logic functions, A, -A, B,
-B, and logical 0, are performed. The combined ALU truth table for FPlS arithmetic operations and logic functions is listed as follows:
MODE
Control

Function Select Inputs
SO
S2
S3
SI

Output Function

A plus B (arithmetic
operation)

A minus B minus 1
(arithmetic operation)

A (logic function)

-A (logic function)

B (logic function)

-B (logic function)

Logical 0 (logic function)

In addition, a comparator output, A=B, is provided when the four A inputs are equal to the four B inputs. A full
carry look ahead capability is provided for fast, simultaneous carry generation.
INPUTS:

Each input presents 1 unit load.

OUTPUTS:

All outputs are capable of driving 10 unit loads.

POWER:

MlS9-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1970 BY DIGITAL EQUIPMENT CORPORATION

~ ----T-

I-O-691~IS5T8l
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.........................
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4
5
6

.:li0
S3
S2

16
19
20
21

CN+-4
EI

7
6

A-6

+5V,A2
81

OTHERWISE INDICATED:

CAPACITORS ARE .01 UF, 100V, 20".
IC IS A DEC74161

+lci
AI

l2
o.Wtlo1L

CH~~:~.(a.,

DATE
~.2B·'70

DATE
//-'3·70

TRANSISTOR & DIODE CONVERSION CHART
DEC

EIA

'[],OA,Q.. D~l;'/].
$. (

DEC

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'f:S:~FT

mamaamD

EQUIPMENT
CORPORATION

PROD.

C2,TI

IC2

DATE

MAYNA.,.O, MASS ... CHUSE:TTS

2- -

r
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TITLE

SIZE

4-BIT ARITHMETIC
LOGIC UNIT MI59

I CS I

MI59-0-1

PRINTED CIRCUIT REV.

. . 3,.
DI"'l1.
'1/ 1/3 ~ 'Ii!> .
~

NUMBER

CODE

REV.

IAI I I I I I I

P//V~

M161
Binary to Octal/Decimal Decoder

The Ml61 is a functional decoding module that can be used as a binary-to-octal or binary-coded decimal-(8421 or
2421 codes)-to-decimal decoder. In the binary-to-octal configuration, up to eight M161 s can be linked together
to provide decoding of up to six bits. Three ENABLE inputs are provided for selective enabling of modules in decoders of more than one digit. In the octal mode, the bit 2* input is connected to ground, which automatically
inhibits the 8 and 9 outputs. Connections for a 5-bit binary/octal decoder (4 modules) are shown in DEC's
Digital Logic Handbook, 1970 edition. The figure assumes that the inputs to the decoder are the outputs of flipflops such as FF2° (1), 1 output side; and FF2° (0), 0 output side.

ENABLE 1
ENABLE 2
ENABLE 3

2"
22
21
20

U1
V2
U2
V1

2*
22
21
20

115-0169

Ml61

Simplified Diagram

The propagation delay through the decoder is typically 55 ns in the binary-to-octal mode and 75 ns in the BCDto-decimal mode. The maximum delay in the BCD-to-decimal mode is 120 ns, thereby frequency-limiting this
module to 8 MHz when used in this fashion. The ENABLE inputs can be used to strobe output data, if inputs
20 - 2* have settled at least 50 ns prior to the input pulse.

*The 2-bit input may be of decimal value 2,4,6, or 8 if illegal combinations are inhibited before connections to the inputs, and the 4-2-1 part of the
code is in binary.

M161-1

The following are the input, output, and power characteristics of the M161 module.

INPUTS:

The inputs to the M16l are: 2° through 2*,1 unit load each; ENABLE 1 through
ENABLE 3, 2 unit loads each.

OUTPUTS:

Each positive output is capable of driving 10 unit loads, and each negative output is
capable of driving 9 unit loads.

POWER:

Power dissipation of the M 161 module is 5V at 120 rnA (maximum).

*The 2-bit input may be of decimal value 2,4,6, or 8 if illegal combinations are inhibited before connections to the inputs, and the 4-2-1 part of the
code is in binary.

M16l-2

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATEO ACCOROINGLY.
COPYRIGHT 19B7 BY DIGITAL EQUIPMENT CORPORATION

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CI

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01

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PIN 7 ON EACH Ie .: GND
PIN 14 ON EACH IC .: t 5V

lEI, E5,E9,EIO,EII
E2,E3,E4,E6,E7, E8
02
01
CI THRU CI2
REFERENCE DESIGNATION

ilit-:
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PARTS LIST
DESCRIPTION
PARTS LIST

110-00-0
W
~

190557&
1905577
1300293
1301401
1001610
A-PL-MI61-0-0
PART NO.

'BINARY TO OCTAL/DECIMAL
DECODER MI61

E QUI P MEN T

SIZE

NUMBER

RIV

CORPORATION

MI61-~

M162
Parity Circuit

The M162 module is a parity detector and contains two parity circuits. Each circuit indicates whether the binary
data presented to it contains an odd or even number of Is. The requirements of the data and its complement are
shown in the illustration.
Indication of odd parity is given by a HIGH level at pins Kl and U2. Pins Ll and V2, when HIGH, indicate even
parity or no input.
The following are the input, output, and power characteristics of the M162 module.
INPUTS:

Each input presents four unit loads.

OUTPUTS:

Pins Ll and V2 can each supply up to ten unit loads. Pin Kl and U2 can each supply up to
six unit loads.

POWER:

Power dissipation of the M162 module is +5V at 102 rnA (maximum).

DATA IN

KI PARITY 000

1/2 MIS2
L1 PARITY 000
AI

......~"..----'

~--

DATA IN
US-OI62

Ml62 Simplified Diagram

M162-1

THIS SCHEMATIC IS fURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 11.7 BY DIGITAL EQUIPMENT CORPORATION

6.8
_ MFD
CI4
35V • 6 8
2D%
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2D%

C2 C4 C6 • CI2
6.8

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UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFO
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V
EI, E2, E4, E5, E6,E7, Ee, EIO 8
E II ARE OEC7420 N
E3 a E9 ARE OEC7430N

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... "yN ..... C, .... AsS ... C .. USETTS

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TITLE

PARITY CIRCUIT MI62

M164
6-Bit Parallel Adder

The Ml64 module contains a 6-bit conditional sum adder. Three of these modules are connected in tandem to
form the IS-bit adder used in the central processor of the PDP-IS. (Refer to Engineering Drawings
D-BS-KPIS-O-I through D-BS-KPIS-O-IS.) The adder can generate an IS-bit sum in S2 ns. This high speed is
available because there is no carry propagated from one adder module to the next. Instead of having the carry
propagated from module to module, which takes 48 ns per module, each 6-bit sum is performed twice simultaneously (see illustration). One sum, CA (carry anticipated), is formed without a carry inserted, while the other
sum, NCA (no carry anticipated), is formed without a carry inserted. Combinational logic in each adder module

L 1 c""A'--_ _~-.r-....
M2S~C~A~_~+-~~

>-__________________~------------------~S~C~A

SNCA

roo

P2 NCA
N2 SNCA

02 A BUS
El B BUS

NCA·
roo
E2

CA INSERT
+5V

CA
roo
El

V2
U2

NOTE: BITS 01 THRU 04
ARE NOT SHOWN

A BUS
B BUS

NCA
r05
El0

-L
Ell

r05

CA
r05
E9

0.....-00

E2
NCA

01
15-0111

M164 Simplified Diagram

M164-1

provides the control inputs SCA (select carry anticipated) or SNCA (select no carry anticipated) to the module
handling the next six most significant bits. The sum from the first adder module during normal addition is always
a sum without a carry inserted because the combinational logic is strapped to select the adder that has no carry
inserted.
The following are the input, output, and power characteristics of the M164 module.
INPUTS:

OUTPUTS:

The MI64 adder module is unbuffered; and all inputs must, therefore, remain stable for the
entire add cycle. The following list shows all input connections and the TTL unit loading
they present:
Name

True I

AO
BO
Al
BI
A2
B2
A3
B3
A4
B4
A5
B5
CA
SCA
SNCA
NCA

2.0
2.0
8.0
8.0
2.0
2.0
8.0
8.0
2.0
2.0
8.0
8.0
2.5
2.5
2.5
2.5

+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0

F2
H2

12
K2
L2
R2
S2
T2
U2
V2
L1
M2
N2
P2

The M164 adder module generates a 6-bit sum in 78 ns and a carry in 42 ns. All output connections and TTL driving capabilities are shown below.
Name

Drive

True I

BI
Al
SI
CI
VI
Ul

12.5
12.5
12.5
12.5
12.5
12.5
5.0
5.0
5.0
5.0

0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
0.4
0.4

I
~ 2
~ 3
~4
~

5
SNCA
SCA
CA
NCA
POWER:

MI
E2
DI

Power dissipated in the M164 module is 5V at 118 rnA (maximum).

M164-2

THIS SCHEMATIC IS FlJ.
.oJ ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.

P2 N2

_-_ ...... _..A

( M5B
AO

EI
2

.!! 12

L.!.!... 10

~12

...

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A,

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141'314

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EIO

114

13 12

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CONTROL OUTPUTS
UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFD
RESISTORS ARE 1/4W; 5%
PIN 7 ON EACH IC (EXCEPT DEC7482N'S)= 6ND
PIN 14 ON EACH IC (EXCEPT DEC7482N'S)= +5V
E I, E2, E5, E6, E9, EIO ARE DEC7482N
E3,E4, E7,EII ARE DEC74H50N
E8 IS DEC74H52N

,;
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C2. \

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2
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OUTPUT DRIVE (UNIT LOADS)

-2, 12.5

LSB

I NPUT LOADS (UNIT)

A"A!,.,:I

B.,B5 ,8, :8
Ao ,A 2 ,A4 :2
80,82,84 :2

CARRY SELECT; 5.0

: 5.0

OUTPUT SELECT: 2.5

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C He ,CCA

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52 T2

14 1314 2 3
A I I,
Ao Bo

A4 84

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5

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)000 1l1:

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1970 BY DIGITAL EQUIPMENT CORPORATION

~
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TRANSISTOR & DIODE CONVERSION CHART

DEC

CI4
6.8

I/lv

PARITY CIRCUIT MI82

..... V...... "'D .......... C ....... TT.

.£

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C2.TIGND

TITLE

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CORPORATION

ORB 102

5
4
2
I
9
121
13

8
E4

EIO

UNLESS OTHERWISE INDICATED'
CAPACITORS ARE .01 ).If, IOOV, 20 %
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC=+5V
E1,E2, E4, E5, E6,E7,E8,EIO,8EII,AR-E DEC74H20N
E3. E9 ARE DEC74H30N
USE MIS2 ETCH BOARD

10
121

I
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9

P
S2

9
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2

E4 ) - - - - -

10
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D/ST. 3'-'/.~:S'f,~3S!l

THIS SCHEMATIC IS fLJ
" ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT IS89 BY DIGITAL EQUIPMENT CORPORATION

P2 N2

.. - -

_.. . .. - .A

( MSB

4
E4

~12

~IO

[

Az 82,

C,,+z

A2 82

A, B,
F2 H2

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....

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3
RI
330

A, 8,
E9

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1'4J'3

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CONTROL OUTPUTS
UNLESS OTHERWISE INDICATED:
CAPAC ITORS ARE .01 MFD
RESISTORS ARE 1/4W; 5"10
PIN 7 ON EACH IC (EXCEPT DEC7482N'S) = GND
PIN 14 ON EACH IC (EXCEPT DEC74B2N'S)= +5V
EI,E2,E5,E6,E9,EI0 ARE DEC7482N
E3,E4, E7, Ell ARE DEC74HSON
E8 IS DEC74HS2N

BI AI
\. ::10 ""

SI CI

"'. ::I,

::10 ::I.)

MSB

ADDER OUTPUTS

OUTPUT DRIVE (UNIT LOADS)
12.5
CARRY SELECT: S.O
C He ,CCA
: 5.0
::IEOI~I." -25!

LSB

INPUT LOADS (UNIT)

A1,A,.A,:S
81,83,B5: B
AOtAz,A. :2
80,8z 1 8. : 2
OUTPUT SELECT: 2.S

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~Pu~P~!q r'T",o~M~~T
A~.~_:_R MI64
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DEC FORM NO.
DRC 102

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M191
Carry Look-Ahead Generator

The M 191 Carry Look-Ahead Generator, consisting of two DEC 74182 integrated circuits, is a high-speed
generator capable of anticipating a carry through a group of ALUs. A 13-ns delay occurs for each look-ahead
level.
Input Voltage:

5.5 volts (with respect to network grand terminal).

Supply Voltage:

4.75 - 5.25 (5 v. nominal)

Normalized Fan Out
from Each Output:

High logic level 20
Low logic level 10

Each carry look-ahead circuit in the M 191 is associated with four ALUs (16 bits). The M 191, when used in conjunction with the M 159 ALU, provides carry, generate-carry, and propagate-carry functions for 36-bit words.
Each circuit generates the anticipated carry through its respective group of ALUs, as well as providing a Generate
(G) and Propagate (P) input to a third carry look-ahead circuit associated with the last ALU; hence, the term fullcarry look-ahead in three levels (36 bits).
Depending on the selected function of the ALUs, the carry look-ahead circuitry determines whether a carry will
be propagated through the particular ALU, or whether the selected function will generate a carry. If a carry is
produced, it is directed into the next ALU in line. This sequence is continued for each of the four ALUs in the
section. The carry look-ahead circuitry then "looks" at the G and P signals of all four ALUs and determines
whether a carry should be inserted into the next four ALUs and into the third level of carry look-ahead. This
process is continued for the second section of ALUs (next 16 bits). Finally, the third level of carry look-ahead
determines whether a carry should be inserted into the final ALU by examining the resulting G and P inputs of
the other two look-ahead circuits.
The truth table for the first-stage carry is as follows:
True Carry Insert = L
POO

GOO

CNOO

CN +X

L
L
H
L

L
L
H
H

L
H
H
L

H
H
L
L

M191-1

True Carry Insert = Low
POO

GOO

CNOO

CN+X

L
H
L
H
L
H
L
H

L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H

H
H
L
L
H
H
H
L

The following are the logic equations for a carry look-ahead stage:
CNOI = CNOO * GO + GO * Po
CN02 = G I *P I + Po*G o *G I + G I *GO*C N
CN03 = P 2 *G 2 + G I *G 2 *P I +GO+G I *G 2 *PO+GO*G I *G 2 *C N
GGOO = P3 *G 3 + P 2 *G 3 *G 2 +P I *G3*G2*GI+G3*G2*GI *Go
PPOO

= P3+P 2 + PI+PO

where
CNXX = True L
GXX

=TrueH

PXX

=TrueH

GGXX =TrueH
PPXX =TrueH
FPI5-0-28
FP24 P03 L H2
FP24 003 L

FP25 P02

FP25 G02
HI
FP 26 P01 L LI
FP26 GOI L KI
FP27 POO L
FP27 000 L

K2
L2

FP33 CNOO L Fl

P3
G3
P2

M191
E13

P F2
G E2

FP28 PPOO L

02
01

FP28 CN03 H
FP28 CN02 H

Pi
G1
PO
GO

CN+Z
CN+Y
CN+X

FP28 GGOO L

FP28 CNOI H

CN
15-0576

Ml91 Carry Look-Ahead Generator

M191-2

M159-ALU'S

15-0577

36-Bit ALU, Full-Carry Look-Ahead in Three Levels

o 161rl

1:t]8~nN

THIS SCHEMATIC IS FURNISHED ONLY fOR TEST AND MAINTENANCE PURPOSES. THE

CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1170 BY DIGITAL EQUIPMENT CORPORATION

H2--.:..! P3

P iL---F2

R2~ P3

J2~ G3

G~E2

S2~G3

JI~ ;;2

CN+Z ~D2

SI~P2

CN+Z r!--M2

HI~ G2

CN+Y r!-!---DI

RI~G2

CN+Y f!--MI

LI~PI

CN+X 1L-EI

VI ----.£ PI

P iL--- P2
G

f1L- N2

CN+X r!-L-NI
E2

---.! 61

KI-GI

K2~ Po

U2~ PO

[2----2 Go

V2----2 GO

FI~ CN

PI~ CN

+5V, A2

lC2 IC3

Lf,!LESS OTHERWISE INDICATED:

!LC4

I~~uF

EI, E2 ARE DEC74182

~~: ~

GND ,c2 ,TI

ON EI,E2
CAPACITORS ARE .0IUF, 100II, 20%

~;N'Y Ifcd~ ~/J~ ITo
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DEC FORM NO.
ORB 102

D~70

IT~J-,

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ElA

O-'T£

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M191-3

DEC

ElA

"D-DU-O
W W

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SIZE

LOOK AHEAD LOGIC

FOR 74181

I I
CODE

NUMBER

MI91

REV

M205
D Flip-Flops

The M205 module contains five separate D-type flip-flops. Each flip-flop has independent DATA, CLOCK, SET,
and CLEAR inputs. Information must be present on the DATA input 20 ns (maximum) before the CLOCK pulse,
and the information should remain at the input at least 5 ns (maximum) after the CLOCK pulse has passed the
threshold voltage. Data transferred into the flip-flop by the previous CLOCK pulse will be present on the I output of the flip-flop. Typical time duration of the CLOCK pulse preset and reset pulses is 30 ns each. Maximum
delay through the flip-flop is 50 ns. Refer to the M206 description for additional details.
The following are the input, output, and power characteristics of the M205 module.
INPUTS:

D inputs present I unit load each.
C inputs present 2 unit loads each.
SET inputs present 2 unit loads each.
CLEAR inputs present 3 unit loads each.

OUTPUTS:

Each output (0 and I) is capable of driving 10 unit loads. Two +3V supplies (Ul and V I),
capable of 25 unit loads, are available.

POWER:

Power dissipation of the M205 module is +5V at 55 rnA (average), 100 rnA (maximum).

M205-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

~ r8

F2~ o S I~J2

N2~ o S I~R2

SI~ o S I~U2

E2~ C R 0 ~K2

M 2 2 C R 0 ~S2

RI~ C R 0 ~V2

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~ 0 S

-----

: RI

• R2

E.3
R 0

A2 +5V

,.....--

UI~
+3V

•

;~CI

VI~

+3V

~ R3

-~C2

-~C3

•

~ R4
C2, TI GND

NOTES:
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V

EI, E2, E3
R3,R4
RI,R2
CI,C2,C3

INTEGRATED CKT. DEC7474N
RES. 750
1/4W 5% CC
RES. 330
114W 5% CC
CAP. .0IMFD 100V 20% DISC
PARTS LIST
DESCRIPTION
PARTS LIST

REFERENCE DESIGNATION

~ al
~~ -

0_ 0Z '-0=
00",
:;; l:

0
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DEC FORM NO.
DRB 102

DRN.

'1h.~

DATE

2-17-('f'

IW'~~~J 3 1~'1.1

TRANSISTOR & DIODE CONVERSION CHART
DEC

EIA

D,TE

Ef.f~ 4}'~?

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EIA

TITLE

~DmDDmD 5 "0" IFLIP FLOPS M205
I

EQUIPMENT
CORPORATION

DATE

MAVNA"D, MA • • ACHU • • TT.

1905547
1301401
1300295
1001610
A-PL-M205-0-0
PART NO.

.r;

SIZE

CODE

PRINTED CIRCUIT REV.

Drs,--

R~V

NUMBER

M205-0-1

-~ A ",t! ",'1, ", -,

lAlllllll
OS

\ ',i,,,,

M206
D Flip-Flops

The M206 contains six separate D-Type flip-flops. Each flip-flop has independently gated DATA, CLOCK, and
dc SET inputs.
Provision is made on the printed circuit board for changing the configuration of the two CLEAR lines to the flipflops. All M206 modules are supplied with the 3-3 configuration, but the grouping can be changed as follows:
Delete Jumper

Add Jumper

FF2, 3, 4, & 5

Al to FF2

K2 to FF2

FFI,2,3,4,&5

Al to FF2
Al to FFI

K2 to FF2
K2 to FFI

Configuration

CLEAR I (AI)

CLEAR 2 (K2)

3-3

FFO, I, & 2

FF3, 4, & 5

4-2

FFO& I

5-1

FFO

Information must be present on the D input 20 ns (maximum) prior to a standard CLOCK pulse and should remain at the input at least 5 ns (maximum) after the CLOCK pulse leading edge has passed the threshold voltage.
Data transferred into the flip-flop is stable at the output within 50 ns (maximum). Typical width requirement
for the CLOCK, dc RESET, and dc SET pulses is 30 ns each.
Information present on the D input is transferred to the output when the threshold is reached on the leading
(positive-going voltage) edge of the CLOCK pulse.
The following are the input, output, and power characteristics of the M206 module.
INPUTS:

D inputs present I unit load each. C inputs present 2 unit loads each. CLEAR lines present
3 unit loads per connected flip-flop. S inputs present 2 unit loads each.

OUTPUTS:

Each output is capable of driving 10 unit loads.

POWER:

Power dissipation of the M206 module is +5V at 87 rnA (maximum).

A common clear for all six flip-flops can be obtained by externally wiring pins Al and K2 together.
CAUTION
The loading of each CLEAR line is calculated on the basis of 3
unit loads per flip-flop. For example, the 4-2 configuration results in 12 unit loads at input K2 and 6 unit loads at input AI.

M206-1

THIS SCHEMATIC IS FURr.ISHED ONLY FOR TEST AND MAINTENANCt PURPUSES THE
CIRCUITS ARE PROPRIETARY IN NATUPE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1917 BY DIGITAL EQUIPMENT CORPORATION

+5V - - - - A2
NOT USED -IS\' - -_ _ B2

DIRECT
CLEAR
AI

a FFO

1'5
I
4
D

DIRECT
SET
DI

02
JUMPER

TAB
AI

Cl\

)'2
M2

GND - - - - C2, TI

1111

J2
E2

+sv

f I J 2 J 3 } 4GND

------TAB
FFI

LI~

r 4 ' O FF2 I 4
R
E2
5
C
0

JUMPER

TAB
FF2
UI

13J a FF3 I 10
lR
E2
5
C
D

n 0 FFI
I 10
R
EI
5
C
0

------TAB
K2

MI~

r4 l l

r 4 ' O FF4 I
4
R
E3
5
C
D

a FF5
E3

I 10
5

NOTES:
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +SV

EI THRU E3
CI THRU C4
REFERENCE DESIGNATION

on "

O'N

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DATE
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0
- 0

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DATE

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TRANSISTOR & DIODE CONVERSION CHART
DEC

ElA

[)fC

INTEGRATED CKT. DEC7474N
1905547
CAP. .01 MFD 100V
1001610
20% DISC
A-PL-M206-0-0
PARTS LIST
DESCRIPTION
PART NO.
PARTS LIST

TITLE

FLOPS M206
~DmDD~D SIXI FLlPI

EQUIPMENT
CORPORATION
..... " ........ D

....... ss"'e'. "JSIOTH.

SIZE

CODE

NUMBER

M206-0-1

PRINTED CIRCUIT REV

R~V

TDI I 1 I II I

M207
Flip-Flop

The M207 Flip-Flop module contains six J-K type flip-flops that can be used as buffers, control flops, shift
registers, and counters. A truth table for clocked set and reset conditions is shown below:

INPUT

OUTPUT
Initial State

Resultant State
1
0

H~L

L
L
H
H

L
H
L
H

L
L
H
H

H
H
L
L

L
L
H
H

L
H
L
H

H
L
H
L

L
H
L
H

Note that when both inputs are high, the flip-flop complements on each clock pulse.
Application of a low level to an R input for at least 30 ns unconditionally resets the flip-flop. Two CLEAR inputs are provided with jumper terminals for optional clearing in groups of 3 and 3 (standard), 4 and 2, 5 and 1,
or 6 and O.
J and K inputs must be stable during the leading-edge threshold of the standard clock input, and must remain
stable during the positive state of the clock. Data transferred into the flop will be stable at the output within
30 ns (typical) of the clock pulse trailing-edge threshold (negative-going voltage).
Provision is made on the printed circuit board for changing the configuration of the two CLEAR lines to the
flip-flops. All M207 modules are supplied with the standard 3-3 configuration but the grouping can be changed
as follows:
Clear
Grouping

Clear 1 (Al)

Clear 2 (K2)

Delete
Jumper

Add
Jumper

3-3

FFO,FF I ,FF2

FF3,FF4,FF5

4-2

FFO,FFI

FF2,FF3,FF4,
FF5

FFI-FF2

K2-FF2

5-1

FFO

FF I ,FF2,FF3,
FF4 and FF5

AI-FFI

K2-FFI

M207-1

INPUTS:

Input characteristics are as follows:
J and K inputs present one unit load
C inputs present two unit loads.
CLEAR inputs present two unit loads per connected flip-flop.

OUTPUTS:

Each output is capable of driving 10 unit loads.

POWER:

+5V, 96 rnA (max.)

M207-2

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 11117 BY DIGITAL EQUIPMENT CORPORATION

-6 -

~A-;;-

- -- --TAB

FFO

'1 K

EI
C

TAB
K2

L4~

J
1 -"4
DI

~
-.J

JiB

L2
I

3-1

-113

I'"

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FF4
E3
C

3 '(I

HI:
FFI

113

1,2
E2
C

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1'4

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......
-

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''''

FF5
E3
C

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1
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TRANSISTOR & DIODE CONVERSION CHART
DEC

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DATE

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DATE

DEC

I ...

A2
A2

CI J[C2J[C3J[C4 +5V

1I I I
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CI THRU

DATE
-V-~('61

FF3

VI:

REFERENCE DESIGNATION
w

NOTES:
PIN 4 ON EACH IC =+5V
PIN II ON EACH IC = GND
----INDiCATES JUMPER
JUMPER CAN BE INSTALLED BY
CUSTOMER BETWEEN FF2 a K2,
AND BETWEEN FFI a K2

(()

PI:

J'O
T2 S2

R:
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FF2

Fil
CLEAR

"i\3M

FFI

EIA

C2,TI
GND

INTEGRATED C KT. DEC7473N
CAP. ,01 MFD 100V 20% DISC
PARTS LIST
DESCRIPTION
PARTS LIST

1905587
1001610
A-PL-M207-0-0
PART NO,

TITLE

-FLOP M207
~amDDmD IFLIP
I
IT

EQUIPMENT
CORPORATION

SIZE

CODE

NUMBER

M207-0-\

"" ...... "" ... "'0. MASSACHUSETTS

PRINTED CIRCUIT REV

r, N I<\.

IE1 I I ITT I

lD\ sr-. 3)..'11'1,"'1"3 , __J

M211

Binary Up-Down Counter

The M2ll is a 6-bit binary UP/DOWN counter. It can switch counting mode (UP or DOWN) without disturbing
the contents of the counter. Maximum count rate is 10 MHz. SET/RESET inputs are available for each bit.
Maximum carry propagation time is 80 ns per bit.
The Enable input must be negated 100 nsec prior to an UP/DOWN
level command.

ENABLE LINE:

The Enable input must not be negated earlier than 500 nsec after the
leading edge (positive going voltage) of the clock pulse.
The Enable input must be asserted at least 60 nsec prior to the first count.
UP/DOWN Control Line:

A logical 1 on this line will yield an up count. A logical 0 on this line will
yield a down count.

CARRY OUT:

The Carry Out will yield a positive level change whenever a carry or borrow
occurs.

INPUTS:

Count In - positive transition or pulse with less than 400 nsec risetime.
Count In presents 2 unit loads. Reset - Each reset input presents 3 unit
loads. Set - Each set input presents 2 units loads. All other inputs
present 1 unit load.

OUTPUTS:

Each flip-flop output (1 or 0) can drive 8 unit loads. Carry Out can drive 10
unit loads. Each inverter output can drive 30 unit loads.

POWER:

+S.OV, 217 rnA (max.)

COU'lT IN 02

ENABLE At

FFO

FFl

FF2

FF3

UP/DOWN B1

POWER

+ 5 V - ' 2 ___
GRD -

C2. T1--eo

M2ll-l

FF4

FF5

H1 CARRY

OUT

•

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANC~ PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1967 BY DIGITAL EQUIPMENT CORPORATION

02
COUNT
IN

-N --.
IV

r-------~~~~~~~~~~~_.--_.--~--~--~----A2

F+---;N~~LE

+5V

R2
NI

+3.0V

~~~OWN

o
I

52
K2~

•

e2 , T1

GND

''""
U

NOTES:
PIN 7 ON EACH Ie.: GND
PIN 14 ON EACH Ie = +5V
DEC7451N MAY BE USED IN PLACE OF DEC7450N

E8
E3
E2.£4, E5, E7, fIO.E II
EI,E6, E9
R2
RI
C 1 THR'lICrr

INTEGRATED CKT. DEC7440N
INTEGRATED CKT. DEC74QON
INTEGRATED CKT. DEC74~ON
INTEGRATED CKT. DEC7474N
RES. 3.3K
1/4W 5% CC
RES. 7.5K
1/4W ~% CC
CAP.
.01 MFD 100V 20% DISC
PARTS LIST

1905579
1905575
1905580
1905547
1300439
1301422
I
1001610
IA-PL-M211-0-0

DESCRIPTION

PART NO.

REFERENCE DESIGNATION

PARTS

DRN

'"oz

?n_Jt'~

_IN

00
00
00
00

~
ENG

"R"I ......

,':91

DEC FORM NO
oRC 102

DATE

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"DATE

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~~;;J~

TRANSISTOR & DIODE CONVERSION CHART

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LIST

IIIIO"DDII!IID
1:1
W

OITLE

E QUI P MEN T

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BINARY UPI DOWN
COUNTER M211
("nn~

-~ 1 ... _ ..

3..1't,4i'1Ji./S0

I_I

I I, -I

6-Bit Left/Right Shift

M212
Register

The M212 module is an internally-connected left/right shift register/buffer that consists of six edge-triggered
D-type flip-flops. The M212 features parallel selection and loading of either of two independent 6-bit sources,
or serial loading and shifting of data in either the left or right direction.
All operations of this register, with the exception of clear, are effected by the leading edge of a positive pulse
applied at pin C I. Four function enable inputs define the module operation. The enable inputs are: ENABLE
RIGHT SHIFT, ENABLE LEFT SHIFT, ENABLE INPUT A, and ENABLE INPUT B.
INPUTS:

Input characteristics are as follows:
Data inputs present one unit load, logic I is +2.8V, or greater, logic 0 is +0.8V,
or less.
Enable inputs present six unit loads, logic I is +2.8V, or greater, logic 0 is +0.8V
or less.
Data and enable inputs must be stable at the gate inputs 50 ns before the clock
threshold is attained.
Assertion of the clock input is a transition from 0 to +3.0V. The clock input
presents 12 unit loads.
A direct clear input at pin BI resets all flip-flops. A +3.0 to OV transition at least
30 ns duration is required. The direct clear input presents 12 unit loads.

OUTPUTS:

Both the 0 and I output of each flip-flop are brought to output pins. Data transferred into each flip-flop will be stable at the output within 50 ns of the leading
edge of the clock pulse.
Each 0 output will drive 10 unit loads. Each I output will drive 8 unit loads.

POWER:

+5V, 145 rnA (max.)

M212-1

SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCl PURPOSES THE
ARE PROPRI,TARY IN NATURE AND SHOULD BE TRlATfD ACCORDINGLY
1967 BY DIGITAL EQUIPMENT CORPORATION

1 p..-

El'

E 31
Ff(ll
C
D

rO
C

~: CLEAR REG

,,~~

L2
SHifT RIGHT INAB(II)
INSERT

H~
H~
~~

,,8
~~,

~~
H~

'45

RI
INSI(G)

"'2
INAI «(II)

Hf--

P2
INBe(G)

F-

4"" 5

EN ABLE RIGHT SHIfT
LI
ENABLE INPUT A
NI
ENABLE INPUT B
U2
ENABLE LEFT SHIFT
PI

yl2

[ 1 0 ff2
E6 I
C
D

fD
fl Ip:D

HI2

4J 0

EI2

IN~: (G)

r;- 10

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INS2Ie)

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1 C ff3
D

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2

+5V

,,~ls0.

~~,
9

'"
'"2i

'9 10

INTEGRATED CKT, DEC7474N
INTEGRATED CKT. DEC7453N

£3,£6,£9

NOTES:
PIN 7 ON EACH IC. GND
PIN 14 ON EACH IC' +5v

R2
INA3(fII)

UI
IN83(8)

INA4(8)

IN841(11)

T2
INS5(G)

V2
INA5(111)

S2
SHifT
LEFT
INSERT

~~5_!~~~~
R2
RI

C 1- CIO
REFERENCE

gg
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cr:1

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D<N

ORe 102

",'--6

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[nc ~ORM NO

Dm.

DATE

DESI~ATION

TRANSISTOR & DIODE CONVERSION CHART

DEC

1905.547
1905582
1300432
RES.---3~~ I/~,!¥~?% c'~~=-1300391
RES,_1.5K
1/4W
5% CC
_.
----[001610
c~. . 01 MFD~'{~,?_o~~~~__
PARTS LIST
A-~J:.- M212-0 -0
PART NO
_L ___ .Ut.:;CIiII-' JJ.l,L~_
PARTS LIST

~------

"DIIIDDlllg
"'''6 BIT L-R SHIFT
i:.I ~ ~
REGISTER M212
E QUI P MEN T

""7~

=~:;.:-'M';',~.~,:r:,I,:,,~1

PINK

("",no-

,,'

I '"~, ~

\lll~T, 3:C"l

"H'~I>

I, ",

'-~ 57'

M214
Data Storage Register

The M214 module contains a 6-bit adder and a 6-bit storage register with input gating logic. Three of these
modules are connected in tandem to form the IS-bit data storage register (DSR) used in the I/O processor of
the PDP-IS. (Refer to Engineering Drawings D-BS-KD IS-O-1 through D-BS-KD IS-0-3.) The register is used for
exchanging data between memory and I/O devices. Input gating logic is included in the module for strobing
the memory data lines (MDL), I/O buffer (lOB), and the I/O address (lOA) into the register.
The following are the input, output, and power characteristics of the M214 module.
INPUTS:

The following list shows all input connections and the TTL unit loading they present:
Name

CARRY-IN

lOA to DSR

lOB to DSR

MDL to DSR

DSR to DSR

lOA

B2, Cl, K2,
11, P2, PI

1 each

lOB

H2, F2, L2,
Ll, S2, T2

1 each

MDL

AI, D2, 12,
Fl, N2, Nl

I each

STROBE

OUTPUTS:

Each DSR output (pins E2, El, Kl, Ml, U2, and VI) is capable of driving 9 unit loads,
and the CARRY OUTPUT (pin Dl) is capable of driving S unit loads. The STROBE pulse
should occur at least 100 ns after the CARRY-IN and the input data have stabilized. DSR
outputs should occur SO ns (maximum) after the module is strobed.

POWER:

Power dissipation of the M214 module is SV at 2S0 rnA (maximum).

M214-1

•

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE I"URPOSES_ THE
CIRCUITS ARE PflOPRI[TARY IN NATURE AND SHOULD BE TREATED .... CCORDINGlY.
COPYRIGHT INt ay DIGITAL EQUIPMENT CORPORATION

DSAI2(1)
E2

SI RESET

•

OSR 13(1)
EI

OSR 14(1)

r. I

DSR 1&(1)

r, I

OSRI7(1)

OSRI6( I)
U2

V I

r, I

V2 STROBE

RI
330
!/4W

~UI

01-

s:::
N

...

R I I/O eus- DSR

M2 OSR-OSR

I~m

"io
I

:~ ~~~ .U:::" -U'H

• I 1I

• I i I

IIOAI2(1)

CI
IIOAI3{t)

I10AI4(1)

MOLl2(i)

.2
02
MDLI30)

• I 1I

• I i I

J I
I/OAIS(I)

I10AI6(1)

MOL 14(1)

'2
FI
MDlIS(l)

N2
MOLI6( I)

II I
• I
l/OAI7(1)

NI
MOLI7(1)

C2,TI
aND

UNLES OTHERWISE INDICATED'
PIN 70N EACH IC (EXCEPTE3,E7,EII)=GNO
PIN 14 ON EACH IC {EXCEPT E3,E7,EII)=+~W
PIN 4 ON E3, E7, EII:+!5Y
PIN liON E3, E7, EII=G NO
E4, E8,EI2 ARE DEC7474
E3, E7,EII AFlEOEC7482
E I,E2, E5, ES,E9,E 10 ARE DEC 7450
CAPACITOAS ARE. 01 jJf, IOOY, 20%

J-IT-.'
DATE

!JJi'

$"-.;.,-·',"1

g~g ~~~M NO

•

TRANSISTOR & DIODE CONVERSION CHART

momoomD
EQUIPMENT

CORPORATIONi

"DATA
SIZE

STOR~~T4REGISTER

CODE

c I CS I "'214-0-1

............ D........... c .. u •• n.1 PRINTED CIHo.;U"

("J 1 'f!-

'!t_y

':;:''-1, ~"" Ii:::<'"

1'11\ K

M216
D Flip-Flops

The M216 module contains six separate D-type flip-flops with independent DATA-SET and CLOCK inputs. The
CLEAR inputs to these flip-flops are connected to two clear input lines (three flip-flops to each line).
Data must be present on the D input 20 ns (maximum) before the CLOCK pulse and should remain at the input
at least 5 ns (maximum) after the CLOCK pulse leading edge has passed the threshold voltage. Data transferred
into the flip-flop is stable at the output within 50 ns (maximum). Typical width requirements for the CLOCK and
dc RESET pulses are 30 ns each.
Data present on the D input is transferred to the output when the threshold is reached on the leading (positivegoing voltage) edge of the CLOCK pulse.
The following are the input, output, and power characteristics of the M216 module.
INPUTS:

D inputs present I unit load each.
C inputs present 2 unit loads each.
CLEAR inputs present 3 unit loads per connected flip-flop.
SET inputs present 2 unit loads each.

OUTPUTS:

Each output is capable of driving 10 unit loads.

POWER:

Power dissipation of the M216 module is SV at 87 rnA (maximum).

A common clear line for all six flip-flops can be obtained by externally wiring pins Al and K2 together.
CAUTION
The loading of each CLEAR line is calculated on the basis of 3
unit loads per flip-flop.

M2l6-l

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY"
COPYRIGHT 1987 BY DIGITAL EQUIPMENT CORPORATION

+5V - - - - A2
NOT USED -15V - - - - B2
FI

DIRECT
CLEAR
AI

U
~
T12

DIRECT
SET
01

n
BI

[Cff.J
16

ICI lc2 1 c:

T I IOND

a::

GNO - - - - C2 • TI

0I'1

NOTES:
PIN 7 ON EACH IC =GND
PIN 14 ON EACH IC =+5V

EI THRU E3
CI THRU C3

INTEGRATED CKT. DEC7474N
20% DISC
LIST
DESCRIPTION
PARTS LIST

I CAP•. 01 MFD IDOV
PARTS

REFERENCE DESIGNATION

~"'ID

DRN

if>

"',y...a-

4'~/~~

CHK"D"

DATE

~')~"I).

DATE
"
DATE

(;
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iii 0
;;

.. 0
.. 0

PROD

DATE

TRANSISTOR & DIODE CONVERSION CHART
DEC

CIA

DEC

EIA

TITLE

1905547
I
1001610
IA- PL-M216-0-0
PART NO.

~DmDamD SIX FLlP- FLOPS M216

EQUIPMENT
CORPORATION
............... O

..... SS ... C .. USETTS

M218
MQ Register

The M218 module contains a 9-bit storage register with input gating and shifting logic. Two M218 modules are
used in the PDP-IS central processor equipped with the EAE option to form the 18-bit MQ register. (Refer to
Engineering Drawings D-BS-KE 15-0-1 and D-BS-KE 15-0-2.) This register extends the AC shifter (M227), facilitating high-speed arithmetic operations (shifting, normalizing, division, and multiplication) and double-precision
results.
The following are the input, output, and power characteristics of the M218 module.
INPUTS:

All inputs but the CLOCK input present 1.25 TTL unit loads. The CLOCK input presents
18 unit loads.

OUTPUTS:

Each output is capable of driving 10 TTL unit loads.

POWER:

Power dissipation of the M218 module is 5V at 310 rnA (maximum).

M218-1

.MIS

_t .'"

"".. ' . ,," _ _ '1_,
.,.,."'"""N ........ _ _"O . . . . . .IOOCC_.

lC~'''.''C's 1".~,S"'C

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CO ... ,..... ' ' '. . . . D... '' . . .

QU·_..

'Co-_.. _

KE"IMQ04QIII)H

"t... , 11lii0i ..... VIlli'"

A81

KEGI
MQ(l2
01 (IIH
---------"

KEG' MQ.(I 01 (I)H

ACI

KEltlMQGl2DI(I)H

AM'
ANZ

KEI3IMQCJ4D1UlH

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9FI

KEtI\ MQe601(IlH BM2

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8.12

KEIlI Me (l701lt11lH

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K~ARI

KEGI MQIMiDi II) H

BEl

P\c,,",.w-LJII"""aN ...

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8A2 +3V

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12

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K
EA[ SHIFT RT H

"
,', " 1",..
, EI?

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:~:KEIf4 DIV H
EAE SHIFT RT H

:~: K 19

IV SHI T H

A>,

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KPqI I SUM BUS Ie Fl H

s::

KEIII MQ GIGI 0I(8)H

IV
.-

.~
,,~

KP83 SUM BUS I l Fl H

80'
BClKE"IMlHJlOl(llf) H

~~
12

...

1 8

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M219
Step Counter and Control

The M219 module contains a 7-bit synchronous step counter with input gating and EAE control logic. One of
these modules is used in the PDP-IS central processor equipped with the EAE option. (Refer to Engineering
Drawing D-BS-KE 15-0-3.)
The following are the input, output, and power characteristics of the M219 module.
INPUTS AND OUTPUTS: Both inputs and outputs are standard TTL levels.
POWER:

Power dissipated in the M219 module is 5V at 540 rnA (maximum).

M219-1

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M223
MA and MB Registers

The M223 module contains two 4-bit registers with input gating logic. Five of these modules are used to form
the 18-bit memory buffer (MB) register and the 13-bit memory address (MA) register that are used in each
memory bank of the PDP-IS. (Refer to Engineering Drawings D-BS-MMIS-O-3 through D-BS-MMIS-O-S.) The
MA register receives the memory cell address from the central processor or the I/O processor and selects a specific
core location. The data or instruction word to be read from or written into the specified core location travels
through the MB register to or from the central processor and the I/O processor.
The following are the input, output, and power characteristics of the M223 module.
INPUTS:

All input connections and the TTL unit loading they present are shown below.
Name

MDL
MBLOAD
MBCLEAR
MALOAD
MAROLD
SA (MB D SET)

D2, E2, F2, R2
11
12
PI
P2
K2, L2, M2, N2

I each
8
12
4
4
2 each

OUTPUTS:

Each MB output (pins K I, L I, M I , and N I) is capable of driving 9 unit loads. Each MA output
(pins RI, R2, SI, S2, Ul, U2, VI, and V2) is capable of driving 10 unit loads.

POWER:

Power dissipation of the M223 module is SV at 17S rnA (maximum).

M223-1

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COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

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M226
Register

The M226 module contains seven storage flip-flops providing I bit of storage for each of the following registers:
1.
2.
3.
4.

5.
6.
7.

Data Switch (OS)
Index (XR)
Memory Address (MA)
Limit (LR)
Program Counter (PC)
Output Buffer to Memory (MO)
Memory Input (MI)

Eighteen M226 modules are used to form the registers in the central processor of the PDP-IS. The registers require an IS-bit capacity. (Refer to Engineering Drawings D-BS-KPIS-O-I through D-BS-KPIS-O-IS.) Mixertype logic for A bus, B bus, C bus, and I bus gating is also included on the M226 module.
The following are the input, output, and power characteristics of the M226 module.
INPUTS AND OUTPUTS: Inputs and outputs are standard TTL levels except for pin BM I, which is an
open-collector output capable of sinking 16 rnA (maximum).
POWER:

Power dissipation of the M226 module is SV at 260 rnA (maximum).

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M227
AC Shifter

The M227 module contains 9 bits of the accumulator with input gating and shifting logic. Two of these modules
are used in the central processor of the PDP-IS to form the 18-bit accumulator (AC) shift register. (Refer to
Engineering Drawings D-BS-KP IS-O-I through D-BS-KPIS-0-18.) The register is used for manipulating data and
temporarily storing results of arithmetic/logical operations.
The following are the input, output, and power characteristics of the M227 module.

INPUTS:

All inputs but the CLOCK input present 1.2S TTL unit loads. The CLOCK input
presents 18 unit loads.

OUTPUTS:

Each output is capable of driving 10 TTL unit loads.

POWER:

Power dissipation of the M227 module is SV at 420 rnA (maximum).

M227-1

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M238
Synchronous Up/Down Counter

The M238 Synchronous Up/Down Counter consists of two DEC74193 4-bit synchronous up/down counter
integrated circuits. The M238 is used in the EPA, DIR, and DAR registers of the FPI 5 Floating-Point Processor,
where the counters are connected to provide eight bit counting capability.
Synchronous operations is provided by clocking all flip-flops in the counter simultaneously so that the outputs
change in coincidence with each other. The flip-flops are master-slave flip-flops and the outputs are triggered
by a positive-going transition of either of two clock inputs. One clock input is designated U (up count) and the
other is designated D (down count). The direction of counting is determined by pulsing one clock input while
the opposite clock input is kept high.
The outputs of the flip-flops may be preset to any state by entering the data at the data inputs while the load
input (L) is low. The output will change to reflect the input, regardless of the clock pulses. The clear input is
provided to clear all flip-flops, independent of the clock and load inputs.
Both the borrow and carry outputs are available for cascading the up-counting and down-counting operations.
When counter underflow occurs, the borrow output produces the same width pulse as the down-count input.
When counter overflow occurs, the carry output produces the same width pulse as the up-count input. Cascading
is accomplished by applying the borrow and carry inputs to the down-count and up-count inputs of the next
counter.
In the example of the DIR register, the UPCOUNT input is inhibited by +3V, indicating that the DIR can only
be decremented.
M238
H24

02
DATA INPUTS {

::::
MD 16
MD 17

LOAD
CLEAR

- LD IR H
GND

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DIR 15 (1) H

DIR 16 (1) H

DATA OUTPUTS

DIR 17 (1) H

CLR

UP COUNT

+3V H 19 Ul - - - - - '

DOWN COUNT

DlR OWN PI - - - - - '

M238-1

15-0565

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1970 BY DIGITAL EQUIf':.lENT CORPORATION

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M240
R-S Flip-Flops

The M240 module contains six R-S-type flip-flops. Each flip-flop consists of two NAND gates with crosscoupled outputs. Two inputs are provided for setting the flip-flops, and one input is provided for resetting the
flip-flops. The following truth table defines the operation of the flip-flops. When the SET output (F 1) is HIGH,
both of the SET inputs (Cl and Bl) are HIGH. When the SET output is LOW, either one or both SET inputs are
LOW.
Previous State
1
0
L
H
L
H
H
L
L
H

H
L
H
L
L
H
H
L

Input Condition
SET RESET
L
H
H
H
L
H
L
L

H
L
H
H
H
L
L
L

Result
0
1
H
L
H
L
No Change
No Change
No Change
No Change
H*
H
H*
H

'Ambiguous state: In practice, the input that stays low longest assumes control.

Propagation delay time from SET or RESET to logical 1 (HIGH) level output is 10 ns (maximum). Propagation
delay time from SET or RESET to logical 0 (LOW) level output is 20 ns (maximum).
The following are the input, output, and power characteristics of the M240 module.
INPUTS:

Each input presents 1.25 TTL unit loads.

OUTPUTS:

Each output is capable of driving 34 TTL unit loads.

POWER:

Power dissipated in the M240 module is 5V at 185 rnA.

M240-1

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THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

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M242
J-K FI ip-Flops

The M242 module contains three J-K flip-flops augmented by multiple-input AND gates for general use as gated
control flip-flops or buffers. A truth table for the clocked set and reset conditions appears below. The J or K
inputs are HIGH when the three inputs to their corresponding AND gate are HIGH; otherwise, they are LOW.
Note that when the J and K inputs are both HIGH, the flip-flop complements on each CLOCK pulse.

Starting Condition
(Output)

Input Condition

Result at End of
Standard CLOCK Pulse
(Output)

L
L
H
H

L
H
L
H

No Change
No Change
H
L
H
L

L
L
H
H

L
H
L
H

No Change
L
H
No Change
H
L

The J and K inputs must be stable during the leading edge threshold of a standard CLOCK input and must remain
stable during the positive state of the CLOCK. The J and K inputs do not have to remain stable after the CLOCK
pulse reaches its trailing edge threshold (negative-going voltage). The minimum width of the CLOCK pulse should
be 12 ns.
Application of a LOW level to the R input for at least 16 ns resets the flip-flop unconditionally. Application of a
LOW level to the 5 input for at least 16 ns sets the flip-flop unconditionally. Propagation delay time to logical 1
level (HIGH) from trailing edge of the CLOCK pulse to output is 21 ns (maximum). Propagation delay time to
logical level (LOW) from trailing edge of the CLOCK pulse to output is 27 ns (maximum).
Propagation delay time to logical 1 level (HIGH) from Sand R input to output is 12 ns (maximum). Propagation
delay time to logical 0 level (LOW) from Sand R input to output is 24 ns. Maximum clock frequency is 24 MHz.
The following are the input, output, and power characteristics of the M242 module.
INPUTS:

All inputs but the Sand R input present 1.25 TTL unit loads. The Sand R input
presents 2.5 unit loads.

OUTPUTS:

Each output is capable of driving 12 unit loads.

POWER:

Power dissipation of the M242 module is 5V at 90 rnA (maximum).

M242-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

81
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C2, TI,GND

CAPACITORS ARE .OIMFO, IOOV
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PIN 14 ON EACH IC=+SV

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M248
Right Shift Parallel Load Register

The M248 Right Shift Parallel Load Register consists of two DEC7495 Right Shift, Parallel Load Register
integrated circuits. The M248 is used in the EPB, FMA, FMB, and FMQ registers in the FP 15 Floating-Point
Processor. The modules are connected to allow right-shifting between four-bit sections so that each module
is capable of handling eight bits. A sample FP 15 Floating-Point Processor application is shown in the illustration.
When a logic a input is applied to the mode control (MC) input, the output of each flip-flop is applied to the
succeeding flip-flop. The right shift operation is performed by clocking at the RS input. During this time, the
left-shift (LS) input is inhibited.
When a logic I input is applied to the mode control input, the flip-flops are decoupled to prevent right shift and
parallel inputs are loaded when the LS input is clocked. The register can be configured for left-shift operations
by connecting the output of each flip-flop to the parallel input of the preceding flip-flop.

23 H

ADD 22 H

DATA INPUTS

ADD 21 H
ADD 20 H

EPB 01

(1)

M248
E07

S2
U2

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EPB

1 P1

EPB 04 (1) H

2 R1

EPB 03 (1) H

3 S1

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U1

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DATA OUTPUTS

LS
-EB Me H
EB RS H
EPB LD H

R2
P2
N2
15-0564

M248-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. T. HE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD 8E TREATED ACCORDINGLY
COPYRIGHT 1970 BY DIGITAL EQUlr'..1ENT CORPORATION

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PROD
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TITLE

4 -BIT RT SH IFT PARALLEL:
LD REG (DUAL) M248

SIZE

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M302
Dual Delay Multivibrator

The M302 contains two delays (one-shot multivibrators, see Figure A) that are triggered by a level change from
HIGH to LOW, or by a pulse to LOW whose duration is equal to or greater than 50 ns. When the input is triggered, the output changes from LOW to HIGH for a predetermined length of time and then returns to LOW. The
basic delay range is determined by an internal capacitor. The delay range can be increased by selection of additional capacitance, which is available by connecting various module pins or by the addition of external capacitance.
An internal potentiometer can be connected for fine delay adjustments within each range, or an external resistance
can be used. If an external resistance is used, the combined resistance of the internal potentiometer and the external resistance should be limited to 10,000il.

DELAY 1

112 M302

OUTPUT

F2 OUTPUT

~-----"v,---_J

SEE TABLE

A
M302 Simplified Diagram

The fall-time of the input trigger should be less than 400 ns.
The delay time is adjustable from 50 ns to 7.5 ms using the internal capacitors and can be extended by adding an
external capacitor.
Care should be exercised in the selection of external capacitors to assure low leakage because leakage affects the
time delay.
Recovery time is determined by the size of the capacitance used. The minimum recovery time of the M302 module is 30 ns when no additional capacitance is used. Recovery time with additional capacitance can be calculated
by using the following formula:
Where T r is in seconds and C is in farads
Recovery time is defined for this module as follows: Recovery time (Tr ) is the minimum time interval that must
exist before each trigger, with all inputs HIGH and the output LOW. The table below illustrates these conditions.

M302-1

Delay Range

Capacitor Value

Interconnections Required
Delay 1
Delay 2

50 ns - 750 ns

100 pf (internal)

None

500 ns - 7.5 J.ls

1000 pf (internal)

DI - L2

NI - S2

5 J.ls - 75 J.ls

0.01 uf (internal)

HI - L2

SI - S2

50 J.ls - 750l1s

0.10 uf (internal)

11 -L2

Ul - S2

500l1s - 7.5 ms

1.0

EI - L2

PI - S2

Above 7.5 ms

uf (internal)

Add external
capacitors between
specified pins

For adjustable delays (D2 - E2 and V2 - R2), connect the pins to the internal adjustment potentiometer. Without
a potentiometer, the delay will not recover. An external potentiometer of less than 10 Krl can be used by connecting the potentiometer between E2 or R2 and ground pin C2. Use of an external adjustment resistor causes
some increase in jitter. It is recommended that the leads to an external potentiometer be twisted pairs and be made
as short as possible.
The following are the input, output, and power characteristics of the M302 module.
INPUTS:

Each input presents 2.5 unit loads.

OUTPUTS:

Each output is capable of driving 25 unit loads.

POWER:

Power dissipation of the M302 module is +5V at 166 rnA (maximum).

M302-2

This page intentionally left blank.

M302-3

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THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY,
COPYRIGHT 1967 BY DIGITAL EQUIPMENT CORPORATION

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M302-5

M311
Tapped Delay Lines

The M311 module contains two tapped delay lines. Each delay line has ten taps providing delays in 25 ns
intervals from 25 ns through 250 ns (see simplified diagram). Pin 11 supplies the minimum delay of 25 ns and
pin VI supplies the maximum delay of 250 ns. The input NAND gate of the delay line provides an additional
delay of IOns (maximum). Delay line tolerance is ±5%.
The following are the input, output, and power characteristics of the M311 module.

INPUTS:

Each input presents 1.25 TTL unit loads.

OUTPUTS:

Each output is capable of driving 1.25 unit loads. Maximum driving capability of the
delay line is 6 unit loads, with a maximum line length of 8 ns.

POWER:

Power dissipation of the M311 module is 5V at 170 rnA (maximum).

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M311

Simplified Diagram

M311-1

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THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

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PIN 7 ON IC = GND

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M312
Delay Lines

The M312 module contains six delay lines. Five of these delay lines have fixed delays with ±5% tolerance, and
one is variable. Delays and output pins are as follows:
Output Pins

Delay (ns)
30
50
30
50
50
0-40

No. I

No.2

Fl
F2
L1
L2
Rl
R2

HI
H2
Ml
M2
Sl
S2

The input NAND gates of the delay lines provide an additional delay of IOns.

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L
_______

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' - - - - - - - - R2 (OUTPUT-I)

FI (OUTPUT 1)

VARIABLE DELAY LINE

FIXED DELAY LINE

15-0114

M312 Simplified Diagram

The following are the input, output, and power characteristics of the M312 module.
INPUTS:

Each input presents 1.25 TTL unit loads.

OUTPUTS:

30 ns delay lines - Each output of the 30 ns delay line is capable of driving 6 unit loads.
However, the total number of unit loads on both outputs of the delay line should not
exceed six.
50 ns lines - Output No.1 of each 50 ns delay line is capable of driving 6 unit loads, and
output No.2 is limited to 4 unit loads. The total unit load capability of each delay line
should not exceed 6 unit loads.

M312-1

Variable delay line - Output No. I of the variable delay line is capable of driving 5
unit loads, and output No.2 is limited to I unit load. The total unit load capability
of this delay line should not exceed 5 unit loads.

POWER:

Power dissipation of the M312 module is 5V at 275 rnA (maximum).

M312-2

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THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

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DELAY MODULE M312
CODE

NUMBER

M312-0-1

PRINTED CIRCUIT REV.

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M401
Variable Clock

The M401 Variable Clock is a stable RC-coupled multivibrator that produces standard timing pulses at adjustable
repetition rates.
The module is intended for use as the primary source of timing signals in a digital system. Repetition rate is adjustable from 175 Hz to 10 MHz in five ranges. Internal capacitors, selected by jumper pin connections, provide
coarse frequency control. An internal potentiometer provides continuously variable adjustment within each range.

E2}
02

OUTPUTS

SEE TABLE
15·01 ...

M401 Simplified Diagram

A 2-input OR gate input is provided for start-stop control of the pulse train. A level change from HIGH to LOW
with fall time less than 400 ns is required to enable the clock.
Delay between enabling inputs and output pin E2 is 50 ns.

Frequency Range
1.5 MHz to 10 MHz
175 kHz to 1.75 MHz
17.5 kHz to 175 kHz
1. 75kHz to I 7.5 kHz
175 Hz to 1.75 kHz

Interconnections Required
(100 pF)
(1000 pF)
(.01 MF)
(0.1 MF)
(1.0 MF)

None
N2
N2
N2
N2

R2
S2
T2
P2

Fine frequency adjustment is controlled by an internal potentiometer. No provision is made for any external
connections.
External capacitance can be added by a connection between pin N2 and ground.

M40I-l

The M401 can also be voltage controlled by applying a control voltage to pin M. This feature is available only
in M401 modules using printed circuit board revision "E" or a later revision. The voltage applied to pin M
should be limited to the range of OV to + I OV. This voltage swing allows the frequency to be shifted by approximately 30 percent in the frequency range, using the internal capacitors of 1.0,0.1, 0.0 I and 0.00 I J1fd. If the
voltage applied to pin M is dc or low frequency (below I KHz), pin M appears as a + I V source with a Thevenin
resistance of 800n. Modulating the M401 with a 10V peak-to-peak signal about a center frequency, as derived
by the application of a mean voltage of +5V to pin M, yields a typical frequency excursion of -0 in excess of
±15% about the center frequency. Typical frequency excursions that may be obtained are shown below.

Voltage (V)
applied to
PinM

1.0 Mfd

0.1 Mfd

0.01 Mfd

.001 Mfd

1.000

10.00

100.0

1000

1.054

10.49

104.6

1036

1.1 01

10.94

109.2

1071

1.147

11.39

113.6

1108

1.193

11.83

118.0

1142

1.238

12.26

122.2

1181

1.282

12.69

126.4

1271

1.325

13.10

130.4

1295

1.368

13.50

134.2

1312

1.408

13.87

137.7

1322

+10

1.443

14.20

140.9

1323

CAPACITOR

Output frequency in kHz

The following are the input, output, and power characteristics of the M401 module.
INPUTS:

Each ENABLE input represents I unit load. For pin M, refer to above text.

OUTPUTS:

The positive output can drive 10 unit loads; the negative output, 9 unit loads.

POWER:

Power dissipation of the M401 module is +5V at 80 rnA (maximum).

M401-2

This page intentionally left blank.

M401-3

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THIS SCHEMATIC IS FURNISHED ONLY FOR TEST ANO MAINTENANCE PURPOSES. THE
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COPYRIGHT 1967 BY OIGITAL EQUIPMENT CORPORATION

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PIN 7 ON IC • GND
PIN 14 ON IC • +5V
TRANSISTORS ARE DEC4258
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TITLE

VARIABLE
CLOCK M401

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M401-5

M402
Photo Mod Clock

The 402 module contains a stable RC-coupled multivibrator that produces standard I OO-ns timing pulses at
adjustable repetition rates.
The module is intended for use as a source of timing signals in a digital system. Repetition rate is adjustable from
I Hz to 500 kHz in two ranges. An internal capacitance, selected by a jumper wire, facilitates coarse frequency
control; and an internal light source provides continuously variable adjustment within the selected range.

ENABLI NG
INPUTS

lJr

21
D2J

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2
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OUTPUTS

P2
15-0115

M402 Simplified Diagram

Coarse Frequency Range
Frequency Range

Cap

Interconnections Required

250 Hz to 500 kHz

0.0 I IlF

None

I Hz to 6 kHz

2.001lF

N2 - P2

A 2-input OR gate input is provided for start-stop control of the pulse train. A level change from HIGH to LOW
with fall time less than 400 ns is required to enable the clock.
Fine frequency adjustment is obtained by applying a control voltage to pins L2 and M2. This voltage changes the
intensity of a lamp inside the module, which in turn adjusts the recovery time of the multivibrator. The voltage
applied between pins Land M should be limited to the range of OV to 5V.
The following are the input, output, and power characteristics of the M402 module.
INPUTS:

Each ENABLE input presents I unit load. For input characteristics of pins Land M,
refer to text above.

OUTPUTS:

Output pin D supplies positive 100 ns pulses capable of driving 10 unit loads. Output pin E
supplies pulses that are the reverse of pin D. This output is capable of driving 9 unit loads.

POWER:

Power dissipation of the M402 module is 5V at 100 rnA (maximum).

M402-1

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M402-3

M420
Phase-Lock Clock

The M420 Phase-Lock Clock is used in the data separator control of the RP IS Disk Pack Control. Inputs include
a reference signal at pin BE2 and a controlled input at pin BH2. The controlled input is the output frequency of
the M420 at pin BK2 divided by 1,2, or 4. This 5 MHz output has a 50 percent duty cycle.
The M420 contains a phase error detector and a voltage controlled oscillator (VCO). The phase error detector
output is connected to the VCO input by a jumper between pins AV2 and AU2.
INPUTS:

Inputs at pins BE2 and BH2 present two unit loads.

OUTPUTS:

The output at pin BK2 can drive eight unit loads.

POWER:

13 rnA at -15V (MAX)
10 rnA at +IOV (MAX)
108 rnA at +5V (MAX)

M420-1

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33p'

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-15V,AH

AlJ
UNLESS OTHERWISE INDICATED.
RESISTORS ARE 10K, I!8W. 1%, MF
CA~CITORS

ARE .Oluf, 100'1, 20%

DIODES ARE 0664

TRANSISTORS ARE

2N42~

R25 IS A CUSTOMER OPTION
£1 IS DEC74HQO
E2 IS OEC74H1II-

E4-£6 ARE LM30lA

::~ ~4'::N5~ 00 fl, E2, E3
E3 IS OEC7'4H50

4/;.

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DIS ..

:1.2.'1. jJ3'f,~35-3 ~

_~_

l-r

M452
Variable Clock

The M452 is a free-running clock that generates the necessary timing signals for the Teletype control in a digital
system. Frequency adjustment of this module is limited to less than 5 percent, and the overall clock stability
with respect to supply voltage and temperature variations is approximately 1 percent. The available output frequencies are 880 Hz and 220 Hz. A pulse amplifier is provided for the generation of nominal 150 ns pulses.
The following are the input, output, and power characteristics of the M452 module.
INPUTS:

The pulse amplifier input presents 1 unit load.

OUTPUTS:

Pin 12 drives 30 unit loads at 880 Hz. Pins N2 and M2 drive 9 unit loads at 330 Hz. Pin
L2 drives 9 unit loads at 220 Hz. Pin K2 drives 30 unit loads at 220 Hz. Pin R2 drives
10 unit loads with a nominal 150 ns positive output pulse. Under normal operating conditions, pins L2, M2, and N2 are used as test points.

POWER:

Power dissipation of the M452 module is +5V at 77 rnA (maximum).

L2 M2 N2

15-0167

M452 Simplified Diagram

M452-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTEJIIANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1981 BY DIGITAL EQUIPMENT CORPORATION

220
BAUD
K

RI
220

R3
2,000
TRIMPOT
04
03

s::

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NI
N

750

~:~O

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N

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RI5
470

r-ID

~_"!':~6534B
Q-"

RIO

,r;-';A. MFO

DEC

*g~~

R9
470

+3V

UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114W, 5%
CAPAC ITORS ARE .01 MFD
C5 IS 35V, 10%. TANT.
DIODES ARE 0662
EI IS DEC7440N
E2 IS OEC7474N
E3 IS DEC7400N
PIN 7 ON EACH IC =OND
PIN 14 ON EACH IC =+5V
R3 IS A .275P

R4
1,500

~RB
680

~R"
1,500

I~-~---------------I
.............. a . . . . . .

.......

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M452-3

M500
Converter-I/O Bus Receiver

The M500 Converter - I/O Bus Receiver module is an M-series single-height module containing eight converter I/O bus receivers that can accept negative logic levels and convert them to positive levels. Each converter - bus
receiver has a negative input clamped to OV and -3V. The threshold switching level is -1.5V with an input current of 100 JlA. Inverted and noninverted outputs are supplied by each receiver.

+3V

OUTPUT NO.1
(INVERTING)
L -_ _ _ _.:....:....

OUTPUT NO.2
(NON-INVERTING)

-1.5 V --"VV'v-H

3KA
-15V
15 - 0074

M500 Simplified Diagram

The following are the input, output, and power characteristics of the M500 module.

INPUTS:

Input characteristics are as follows:
Minimum input impedance at OV - 30 kil
Maximum current load to bus - 100 JlA
Inputs are standard negative logic levels of OV and -3V.

OUTPUTS:

Outputs are standard TTL positive logic levels with the following driving capability:
Output No. 1 - 12 unit loads
Output No.2 - 11 unit loads

DELAYS:

Input/Output No. 1 delay - 50 ns
Input/Output No.2 delay - 40 ns

POWER:

Power dissipation in the M500 module is 750 mW (maximum) from -I5V and 800 mW
(maximum) from +5V.

M500 -1

The MSOO module was designed to receive PDP-9 I/O bus signals for devices using positive logic. It provides a
high input impedance. This module is pin compatible with the MSI 0 module.

MSOQ-2

This page intentionally left blank.

MSOO-3

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AN~ MAINTENANCE PURPOSES. THE

CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COP'l'RIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

~Cl

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1.51t

1.5IC.

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+5V

1.51t
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0662
02.
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0662
02.
0662
-GND

014

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.,.020

C2,F2.
J2,L2,

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N2,TI

is::
o

-1.5V

••

OK
5%

3'
5%

'9
3.

RI5

R2I
3'
5%

3'
5%

-3V

RI.

E2
-U5V

R2'

OK
5%

''Y.

-3V

'2.
1.51<.

.2
-15

UNLESS OTHERWISE INDICATED,

TRANSISTORS ARE OEC3Q09B
DIODES ARE 0664
RESISTORS ARE r/4W,IO%
IC'S ARE DEC74HQON
PIN 70N EACH IC=GND
PIN 14 ON EACH Ie = +5V
CAPACITORS ARE .01 MFa
RESISTORS ARE 470

OA~tlT';.e - ~/1/t;--;

~.K~~ r-;E_t..
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M500
09·04'0

M510
1/0 Bus Receiver

The MSI a module is an M-series single-height module containing eight PDP-IS I/O bus receivers. The receiver
circuit consists of a two-stage emitter follower with two TTL output buffer gates to supply both inverted and
noninverted outputs.
The following are the input, output, and power characteristics of the MSI a module.
INPUTS:

Input characteristics are:
Minimum input impedance - 22.S kn
Maximum current load to bus - 100 JIA
Inputs are standard PDP-IS I/O Positive Bus levels.

OUTPUTS:

Outputs are standard TTL positive logic levels with the following driving capability:
Output No.1 - 10 units
Output No.2 - 12 units

DELAYS:

Input/Output No.1 delay - SO ns (maximum)
Input/Output No.2 delay - 60 ns (maximum)

POWER:

The power dissipation of the MSI a module is 900 mW (maximum).

The MSI a module was designed to receive PDP-IS I/O bus signals for devices using positive logic. It provides a
high input impedance that yields a switching threshold between the HIGH and LOW levels of the propagated
signals. This feature reduces loading and noise problems. The MSl a module is pin compatible with the MSOO
module.
r------_---O + 5V
r----..!!N..!,I-<> OUT PUT
NO.1
( INVERTING)

100 ..
I NPUT P2 <>--,'\IVI...---i-(

30098
1.8K ..
1.8K ..

+3V
15-0076

MSlO Simplified Diagram

MSlO-l

THISSCH['-IATIC IS FURNISHED ONLY fOfl TEST "NO '-I"INTEN"NCE PUflPOSES THE
CIRCUITS "RE PROPRIETARY IN NATURE AND SHOULD BE TR(AT[O "CCOROINGlY
COPYRIGHT III., BY DIGITAL [QUIP'-IENT COflPOR"TION

+OV

02~ ~:.
R9
100

~ ".
1

RIO
18.

RI'
R4
100
l O O K2 ---'V\I\

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RI7

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UNLESS OTHERWISE INDICATED
IC'S ARE OEC74HOO
PIN 7 ON ECH IC "OND
PIN 14 ON EACH IC"+!5V
DIODES ARE 0 664
RESISTORS ARE 1/4W 10%
TRANSISTORS ARE DEC 500M

TRANSISTOR & DIODE CONVERStON CHART

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MSIO-3

M515
Real Time Clock

The M5lS module contains a real time clock that converts conventional sinusoidal power waveforms into timing
gates. Complementary timing gates are available at the output pins of the module (see illustration).
The following are the input, output, and power characteristics of the MSIS module.

INPUTS:

The input is 12 Vac.

OUTPUTS:

The output at pin D2 is capable of driving 36 unit loads, and the output at pin E2 is
capable of driving 31 unit loads.

POWER:

Power dissipation of the MSIS module is SV at 55 rnA and 10V at 30 rnA.

+10V 12Vac

E2
M515

D2
15-0116

MSlS Simplified Diagram

MS1S-1

~ [ -<ff

1s:rfa-]

I-O-~I~~

~3a~nN

. A3M

3ao~

3ZlS

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THEJ
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

1c2

C>-1

'1"

.l
C3
~

CI...J....+
6.81lf '1"_
35V

.04

a:::

~0664

,...!.J 02

'.IN748

>R6
210K

C;R2
SIK

,...!...I 03
'.IN748

01
0664

....

+12 VAC

JII"1

RI
220

R8
220

5?IKR3

'..
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IN75'-'1

Lr
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+EI

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3~4

VV\

r.:;:)

R7
IK

S
S
'-E

GNO{

5
UNLESS OTHERWISE INDICATED:

,-C

().

GND

RESISTORS ARE 1/4W.5%
L-.E2 IS MCI709CG
AMP. CONN.
EI IS OEC74H40
CAPACITORS ARE .Oluf. 100V.20%
EIPIN7=GNO
EI PIN 14=+5V
CONNECTOR IS OECtl209340
P INS ARE DEC 111209456
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DEC

EIA
EIA

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IN3606

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COR P 0 RAT ION ~B=--L.:C..:S-L----J:::-r"'''''r'inr1

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CODE

........ v ...... "'o. ,....".S ... CHUSf!TT!I

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M602
Pulse Amplifiers

The M602 contains two pulse amplifiers that provide power amplification, standardize pulse amplitude and
width, and transform level changes into a standard pulse. A negative pulse output is produced when the input is
triggered by a transition from HIGH to LOW. Propagation time between input and output thresholds is 30 ns
(maximum). An internal capacitor is brought out to pin connections to permit the standard SO ns output pulse
to be increased to lIOns (nominal). Recovery time is equal to that of the output pulse width. The input must
have a fall time (10 percent to 90 percent pOints) of less than 400 ns and must remain below 0.8V for at least
30 ns. Maximum PRF is 10 MHz.
The following are the input, output, and power characteristics of the M602 module.
INPUTS:

Each input presents 2.5 unit loads.

OUTPUTS:

Each output is capable of driving 30 unit loads.

POWER:

Power dissipation of the M602 module is 5V at 213 rnA (maximum).
PA 1

OUTPUT

I D2

INTERNAL CAPACITQR*

*JUMPER E2-D2 OR R2-S2 FOR
110n. PULSE WIDTH. STANDARD
PULSE WIDTH IS 50n ••
15 - 017 2

M602 Simplified Diagram

M602-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD 8E TREATED ACCORDINGLY.

RI
150

PULSE
INPUTS

~~",~6 1 1 M~rO

~R4

~R7

150

100
112W
10%

~ RS

150

~IIY'\ ~2

PULSE
INPUTS

a::::

o
N
N

R3
330

CIO

D7
D662

DI4
D662

F
PULSE
OUT

L
PULSE
OUT

::::::::C5

D5
D662

~R5
330

+:V

1/2W
10%

P
N
M

D6
D662

hl8 hl~ r r

~~~6

!4() !

::::::C6

RII
330

~ RI3

330

DI3
D662
DI2
D662

,
C
"ND

UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DEC36398
DIODES ARE D664
RESISTORS ARE 1/4W, 5%
CAPACITORS ARE .01 MFD
PIN 7 ON IC; GND
PIN 14 ON IC; +5V
IC IS DEC74H40N

I--------~---------I
....

v.,

DRN

DATE

<J)

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6-/-67

CHK'O

DATE

:;:

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DATE

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....

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TRANSISTOR & DIODE CONVERSION CHART
DEC

ElA

2N3009
DEC30098
DEC36398
2N3639
0662
IN64'5
0664
..lIN3606

DEC

ElA

~DmDDmDITI~~LSE GENERATOR M602
EQUIPMENT
CORPORATIONi
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M602-3

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M606
Pulse Generators

The M606 module contains six separate pulse generators. Each generator produces a pulse to ground in response
to an input level shift from HIGH to LOW (see illustration). Duration of the pulse must be at least 30 ns, and the
pulse can be no wider than 100 ns. Each pulse generator is also equipped with an inhibit gate that blocks the output if grounded. A logic I level should be applied to the inhibit gate if a continuous output is required. Each
pulse generator can be used for setting or clearing flip-flops by connecting the output to the DIRECT CLEAR or
SET inputs of up to IS flip-flops.
The following are the input, output, and power characteristics of the M606 module.
INPUTS:

The TRIGGER input presents two TTL unit loads, and the INHIBIT input presents
one unit load.

OUTPUTS:

All pulse generator outputs present 30 unit loads. Output pin VI is a source of a logic 1
level that is capable of driving 10 unit loads.

POWER:

Power dissipation of the M606 module is SV at 188 rnA (maximum).

TRIG IN
01

INHIBIT
E2-------"
15-0117

M606 Simplified Diagram

M606-1

•

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

_A2

< R5

~ R7

+5V

470
VI

+3.4 V
~.DI

.... .....
04

~ ~~MMF

~~ D2
8
EI

F 1----<

I
E2

(

F-~JMMF

s:::

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V-,3

...

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~
....

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P
8

10
9

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J2
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0662

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1 .0IMFD

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H·2

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68MMF
f3
5%

E3~

6
EI

~ ...
~
....

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r-Cl~-h .0IMFD
CI2

--.

RI2

RII

2
I
3

.... ...
DI3

DI4

f?
~

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RI3

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6
E3

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DI6

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-

UNLESS OTHERWISE INDICATED

CAPACITORS ARE IOOV,20%
DIODES ARE D 664
RESISTORS ARE 1.5K, 1/4W, 5%
TRANSISTORS ARE DEC3009B
PIN 7 ON EACH IC =G ND
PIN 14 ON EACH IC=+5V

EI,E3,E5 ARE ()EC7440N
E2,E4, E6 ARE DEC740lN

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TRANSISTOR & DIODE CONVERSION CHART
DEC

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DEC FORM NO.
ORe 102

EIA

DEC

EIA

mamaDma

TITLE

• • •

PULSE GENERATOR
M606

1N645
IN3606

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M606-3

M611
High-Speed Power Inverters

The M611 module contains 14 high-speed power inverters. Each inverter has a maximum propagation delay of
12 ns.
The following are the input, output, and power characteristics of the M611 module.
INPUTS:

Each inverter input presents 1.25 TTL unit loads.

OUTPUTS:

Each inverter output is capable of driving up to 36 unit loads.

POWER:

Power dissipation of the M611 module is 5V at 240 rnA (maximum).

M611-1

~ I

~·---··I-O-':119-~TI:)J

IA3~

~381'jnN

-13ao:) 3ZIS1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.

•

DI~

•

81
AI~

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S2

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C9
6.8MFD ::=:::: C 8
35V

::=::::C7

::=::::C6

::=::::C5

*C4

::=::::C3

1..-

1
T

CI
C2,CI,M2
N2,T I
GND

UNLESS OTHERWISE INDICATED
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V
IC'S ARE DEC74H40
CAPACITORS ARE .0IMFD 100V
RESISTORS ARE 220 1/4W 10%

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M617
Power NAND Gates

The M617 contains six 4-input NAND gates, each capable of driving up to 30 unit loads. Gate propagation delay
is 25 ns (maximum). Physical configuration and logical operation are identical to the Mil 7.
The following are the input, output, and power characteristics of the M617 module.

INPUTS:

Each input presents I unit load.

OUTPUTS:

Each output is capable of driving 30 unit loads.

POWER:

Power dissipation of the M6l7 module is 5V at 97 rnA (maximum).

M617-1

IH<5 SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE 'UR'OSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1917 BY OIGITAL EQUIPMENT CORPORATION

+5V

NOT USED -15V • - - - - 82

C2, TI

GND

AI~
8I
CI
01

12
10

D2~
E2
i EI 6
J2
F2
s:::
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K2~
L2
~
E2
6
P2
~~

MI~
NI

R2~
S2

-.J
1

+SV

R3
lCI

NOTES:
PIN 7 ON EACH IC= GND
PIN 14 ON EACH IC=+5V

~UI

~YI

+3V

~r-C3

GND
EI THRU E3
R2 a R3
RI a R4
C I a C2 eo C 3
REFERENCE DESIGNATION

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DEC

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INTEGRATED CKT, DEC7440N
RES 330 1/4W 10% CC
RES. 750 1/4W 5% CC
CAP.. 01 MFD 100Y
20% DISC
PARTS LIST
DESCRIPTION
PARTS LIST

1905579
1300293
1301401
1001610
A-PL-M617-0-0
PART NO,

6-4 INPUT

~DmDDmD INOR BUFFERS M617
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PRINTED C)RCUIT REV

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IAI I I I I I I

M621
Data Bus Drivers

The M621 module contains six open-collector AND-NOR gate drivers. Two separate data inputs can be strobed
through each driver. The strobe inputs are common to all six drivers. Propagation delay with a 68n resistive
load is 55 ns (maximum) for outputs going HIGH and 35 ns (maximum) for outputs going LOW.
The following are the input, output, and power characteristics of the M621 module.
INPUTS:

Data inputs present 1.25 unit loads. Strobe inputs present 8 unit loads.

OUTPUTS:

Each driver output can sink 100 rnA to ground.

POWER:

Power dissipation of the M621 module is 5V at 200 rnA.

M621-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

K 2

CI
.0IMFD

RI
470

R4
470

R6
470

C2
.0IMFD
R7

220

C3
.0IMFD

C4
.01 MFD

C5
.0IMFD

C6
6.8MFD
35V

- .. +

UNLESS OTHERWISE INDICATED
PIN 7 ON EACH IC , GND
PIN 14 ON EACH IC'+5V
EI,E3,E5 ARE DEC 74H50N
E2,E4 ARE DEC 74HOON
CA~CrTORS ARE 100V, 20%
RESISTORS ARE 1/4W 10%
TRANSISTORS ARE DEC3009B-S

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M621-3

M622
1/0 Bus Drivers

The M622 I/O Bus Driver is an M-series single-height module containing eight I/O bus drivers. Each driver consists
of an AND/OR integrated circuit gate and a discrete component open-collector driver.
The following are the input, output, and power characteristics of the M622 module.
INPUTS:

Inputs are standard TTL positive logic levels.
The input load is 1.2S units.

OUTPUTS:

Outputs are standard PDP-IS positive I/O bus signals. Output characteristics are:
Risetime - IS ns at the input to the cable
Current sink - 100 rnA (maximum) at Vcesat = O.4V (maximum)
Falltime - IOns at the input to the cable
Input-Output Delay - 4S ns (maximum)

POWER:

The power dissipation of the M622 module is 1.0SW (maximum) at +SV.

The M622 module was designed specifically to drive PDP-IS I/O bus signals for devices that use positive logic
modules. The M622 module is pin compatible with the M632 module.

+5V
470 ..

Bl
+3V
Cl

3009B
220 ..

+3V

-=
, 5-0078

M622 Simplified Diagram

M622-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY

R3
470
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UNLESS OTHERWISE INDICATED:
CAPACITORS ARE 100MMF
RESISTORS ARE 220; 114W;fO%
TRANSISTORS ARE DEC3009B
IC'S ARE DEC74H50
PIN 7 ON EACH IC ~ GND
PIN 14 ON EACH IC ~ +5V
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M622-3

M627
NAND Power Amplifiers

The M627 combines power amplification with high-speed gating for high fan-out of clock or shift pulses that are
to be expanded counters and shift registers. Propagation time between input and output transitions is 12 ns
(maximum). To utilize the timing accuracy of this module, wire runs of minimum length are recommended.
The M627 module can also be used as a 4-input NAND gate. In the pulse amplifier application, unused inputs
should be connected to the +3V pins provided.
The following are the input, output and power characteristics of the M627 module.

INPUTS:

Each input presents 2.5 unit loads.

OUTPUTS:

Each output is capable of driving 40 unit loads.

POWER:

Power dissipation of the M627 module is +5V at 136 rnA (maximum).

M627-1

1H<5 SChtMAl'C " 'U,"'H£O ONLY fO' lE51 " 0 MA<NlENANCE 'U,fOSES THE
CIRCUITS ARE PROPRIETARY IN N .... TURE AND SHOULD BE TREATED ACCO;>DINGLY
COPYRIGHT IIITB" OIGITAL EQUIPMENT CORPORATION

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NOTES:
PIN 7 ON EACH IC: OND
PIN 14 ON EACH IC: t5V

REFERENCE DESIGNATION
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190558S
1300293
1301401
1001610
A~PL- M627-0-0
PART NO.

INTEGRATED CKT. DEC74H40
RES. 330 1/4W 10% CC
RES. 750 1/4W 5% CC
CAP•. 01 MFD IQQV 20% DISC
PARTS LIST
DESCRIPTION
PARTS LIST

.......... CHV.IlTT.

TITIf

SIZE

POWER AMPLIFIER
MODULE M627
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IIM627-0-\

PRINTED CIRCUIT REV

NUMBER

IR~V

IAI I I I I I I

M628
Block-Bank Address Card

The M628 module contains two 2-position switches, a 2-bit adder, and output gating logic. A maximum of three
M628 modules are used in one MX 15A memory multiplexer. Address bits 03 and 04 are modified by the module
to select the desired memory bank in the PDP-15 system. The module also contains a set of input-output connections that can be jumpered to select a specific memory block.
The following are the input, output, and power characteristics of the M628 module.
INPUTS:

DI presents 5.25 unit loads and CI presents 2.25 unit loads.

OUTPUTS:

L I and K I are capable of driving 12 unit loads each, while L2 and K2 can drive only
9 unit loads.
E2 and H2 are open-collector outputs capable of sinking up to 100 rnA (maximum).
Total propagation delay through the adder and one driver is 100 ns (maximum).

POWER:

Power dissipation of the M628 module is SV at ISO rnA (maximum).

M628-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES TH
CIRCUITS APE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1970 BY DIGITAL EQUIPMENT CORPORATION

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TRANSISTORS ARE OEC30098
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CAPACITORS ARE .Oluf, IOOV, 20%
INDICATES SPLIT LUGS

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M628-3

M632
Converter-I/O Bus Driver

The M632 is an M-series single-height module containing eight converter-I/O bus driver circuits. It accepts
positive logic signals and converts them to negative logic levels. Each driver consists of a TTL input gate and
a negative open-collector output driver clamped to ground and -3V.
The following are the input, output, and power characteristics of the M632 module.
INPUTS:

The inputs to the M632 are standard TTL positive logic levels. The input current
load at OV is 1.25 units.

OUTPUTS:

Outputs are standard negative logic levels. Output characteristics are:
Risetime - 15 ns
Falltime - 15 ns with 1.5 kS1 to -ISVat output
Input-Output Delay - 50 ns (maximum)

POWER:

Power dissipation in the M632 module is 600 mW from -ISV (maximum) and
900 mW from +SV (maximum).

This driver is used to convert positive logic signals to negative logic levels that drive the PDP-9 negative I/O bus.
The M632 module is pin-compatible with the M622 module.

A2(+5V)
47011
10%

1/4W

664

BI>I----1,

+3V
CI>I-----LJ

NKII

-3V

1/4W

-.6V

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02
15-0078

M632 Simplified Diagram

M632-1

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UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W,5%
DIODES ARE 0664
TRANSISTORS ARE DEC36398
I C'S ARE OEC74H50
PIN 7 ON EACH Ie = GND
PIN 14 ON EACH Ie = +5V
CAPACITORS ARE .01 MFO

TRANSISTOR & DIODE CONVERSION CHART

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M632-3

M706
Teletype Receiver

The M706 Teletype Receiver is a serial-to-parallel Teletype code converter self-contained on a double-height
module. This module includes all of the serial-to-parallel conversion, buffering, gating, and timing (excluding only
an external clock) necessary to transfer information in an asynchronous manner between a serial data line or Teletype device and a parallel binary device. Either a S-bit serial character consisting of 7.0, 7.5, or 8.0 units; or an
8-bit serial character of 10.0, 10.5, or 11.0 units can be assembled into parallel form by the M706 through the use
of different pin connections on the module. In the PDP-IS, the Teletype receiver is connected to assemble 8-bit

AD2

AF,-

~~
~
~

CODE

DEVICE

~~ SELECTOR
CODE

ENABLE OS API
READER ON

r-- ~AU2

AV2
READER
CONTROL

BL2

READER
RUN

READER (I)

FLAG STROBE BD2 ~
CLEAR FLAG I BJ2
CLEAR FLAG 2 BDI

r-FLAG

BH2

STROBED FLAG

AF2

FLAG

BE2
AE2

,CLOCK"

~~l!Q,
ENABLE

BRI

I/O
CLEAR

BF2

ANI

BN2

ACTIVE (0)

CONTROL

PIN CONNECTIONS FOR 5 OR 8
BIT CODE
5 BIT - AM2 TO AJ2
AR I TO GROUND
8 BIT - AM2 TO ARI
AJ2 TO AKI
PIN CONNECTIONS FOR STOP TIME
1.0 UNITS - BP2 TO BT2
BR2 TO BU2
1.5 UNITS - BP2 TO BSI
BR2 TO BU2
BUI
2.0 UNITS - BP2 TO BT2
BR2 TO BV2
SERIAL INPUT
BM2

SHIFT
REGISTER

READ BUFFER

AN2

BIT I

AT2

BIT 2

AP2

BIT 3

AMI

BIT 4

ALI

BIT 5

AS2

BIT 6

AR2

BIT 7

AK2

BIT 8

AL2

M706 Simplified Diagram

M706-1

characters consisting of 11 units. When conversion is complete, the start and stop bits accompanying the serial
character are removed. The serial character is expected to be received with the start bit first, followed by bits 1
through 8 in order, and completed by the stop bits. Coincident with reception of the center of bit 8, the FLAG
output goes LOW, indicating that a new character is ready for transmission into the parallel device. The parallel
data is available at the BIT I through BIT 8 outputs until the beginning of the start bit of a new serial character
is received on the SERIAL input (see the timing diagram for additional information).

+3V
SERIAL
INPUT

STOP
0

CLOCK

ACTIVE

STOP

+3: I I I I I I I I I I I I :I I I I I ~I I I
+3]

111111:111111111111

(0)

CLEAR
FLAG

+3:1

(I)

FLAG

+3:11

READER

lS-016!

M706 Timing Diagram

In addition to the above listed features, the M706 includes the necessary logic to provide rejection of spurious
start bits less than 1/2-unit long, and to also provide half-duplex system operation in conjunction with the M707.
Device selector gating is also provided; thus, this module can be used on the positive 1/0 bus of a digital system.
The following are the input, output, and power characteristics of the M706 Teletype Receiver.
INPUTS:

All inputs present one TTL unit load (except where noted). When input pulses are required,
they must have a width of 50 ns or greater.
CLOCK:

The clock frequency must be eight times the serial input bit rate
(baud rate). This input can be either pulses or a square wave. Input loading on the CLOCK line is three unit loads.

ENABLE:

The ENABLE input, when brought to ground, inhibits reception of
new characters. It can be grounded any time during character reception, but returned HIGH only between the time the FLAG output
goes to ground and a new character start bit is received at the serial
input. When not used, the ENABLE input should be tied to a source
of+3V.

M706-2

I/O CLEAR:

A HIGH level or positive pulse at this input clears the flag and
initializes the state of the control. When not used, or during reception, the I/O CLEAR input is grounded.

CODE SELECT Inputs: When a positive AND condition occurs at the CODE SELECT inputs, the following signals can assume their normal control functions: FLAG STROBE; READ BUFFER; and CLEAR FLAG I.
These inputs are frequently used to multiplex receiver modules
when a signal such as READ BUFFER is common to many modules. The inputs are also used for device selector inputs when the
M706 is used on the positive I/O bus of a digital system. The
CODE SELECT inputs must be present at least 50 ns prior to any
of the three signals that they enable. If it is desired to bypass the
CODE SELECT inputs, they can be left open and the ENABLE D. S.
line tied to ground.
CLEAR FLAG 1:

A HIGH level or positive pulse at the CLEAR FLAG I input while
the CODE SELECT inputs are all HIGH clears the flag. When not
used, this line should be grounded. Propagation delay from input
rise until the flag is cleared is a maximum of 100 ns. The flag cannot be set if this input is held HIGH.

CLEAR FLAG 2:

A HIGH level or positive pulse at the CLEAR FLAG 2 input, independent of the state of the CODE SELECT inputs, clears the flag.
All other characteristics are identical to those of CLEAR FLAG 1.

FLAG STROBE:

If the flag is set and the CODE SELECT inputs are all HIGH, a
positive pulse at the FLAG STROBE input generates a negativegoing pulse at the STROBED FLAG output. Propagation delay from
the strobe to output is a maximum of 30 ns.

READ BUFFER:

A HIGH level or positive pulse at the READ BUFFER input while
the CODE SELECT inputs are all HIGH transfers the state of the
shift register to outputs BIT 1 through BIT 8. Final parallel character data can be read by this input as soon as the FLAG output
goes to ground. Output data is available a maximum of 100 ns after
the rising edge of this input. See the timing diagram for additional
information.

READER ON:

A LOW level or ground at the READER ON input turns on the internal reader flip-flop. This element is turned off at the beginning
of a received character start bit. The READER ON input can also
be pulsed by tying it to one of the signals derived at output pins
AE2 or BE2.

SERIAL Input:

Serial data received on the SERIAL input has a logical 0 (space)
equal to +3V and a logical I (mark) of ground. The input receiver
on the M706 is a Schmitt trigger with hysterisis thresholds of nominal 1.0V and 1.7V. This allows the SERIAL input data to be
fIltered up to 10 percent of bit width on each transition to remove
noise. The SERIAL input is diode-protected from voltage overshoot
above +5.9V and from voltage undershoot below -0.9V. Input
loading is four unit loads.

M706-3

OUTPUTS:

All outputs can drive ten unit loads (unless otherwise specified).
BITS 1 through 8:

A READ BUFFER input signal transfers the shift register contents
to those outputs with a received logical 1 appearing as a ground
output. If the READ BUFFER input is not present, all outputs are
at logical I. When the M706 is used for reception of 5-bit character
codes, the output data appears on output lines BIT 1 through 5;
and BITS 6, 7, 8 receive logical zeros.

ACTIVE (0):

The ACTIVE (0) output goes LOW at the beginning of the start bit
of each received character and returns HIGH at the completion of
reception of bit 8 for an 8-bit character, or bit 5 for a 5-bit character. Because this signal uses from OV to +3V (at 1/2-bit time after
the FLAG output goes to ground) it can be used to clear the flag
through the CLEAR FLAG 2 input while the FLAG output, after
being inverted, can strobe parallel data out when connected to
READ BUFFER.
If an M706 and M707 are to be used in half-duplex mode, this output should be tied to the WAIT input of the M707 to inhibit M707
transmission during M706 reception. Output drive is eight unit
loads.

POWER:

FLAG:

The FLAG output falls from +3V to ground when the serial character data has been fully converted to parallel form. Relative to
serial bit positions, this occurs during the center of either bit 8 or
bit 5, depending on the respective character length. If the M706 is
receiving at a maximum character rate (i.e., one character immediately following another), the parallel output data is available for
transfer from the time the FLAG output falls to ground until the
beginning of a new start bit. This is stop-bit time plus 1/2-bit
time.

STROBED FLAG:

The STROBED FLAG output is the NAND realization of the inverted FLAG output and FLAG STROBE.

READER (1):

Whenever the internal reader flip-flop is set by the READER ON
input, the READER output rises to +3V. The flip-flop is cleared
whenever a start bit of a new character is received on the SERIAL
input.

READER RUN:

The READER RUN output is used with DEC modified 33 ASR
and 35 ASR Teletypes that have relay-controlled paper tape
readers. The READER RUN output can drive a load of 20 rnA at
+0.7V. The common end of the load can be returned to any
negative voltage not exceeding -20V.

PIN AE2:

The PIN AE2 output is the logical realization of NOT (CLEAR
FLAG 1 or CLEAR FLAG 2 or I/O CLEAR) and is a +3V-toground output level or pulse, depending on the input. The signal
is used to pulse READER ON for control of READER RUN in the
system.

PIN BE2:

The PIN BE2 output is brought from +3V to ground by an enabled
CLEAR FLAG I input. It can be connected to READER ON for a
different form of control of READER RUN.

+3 VOLTS

Pin ADI can drive ten unit loads at a +3V level.

Power dissipation of the M706 is 5V at 400 rnA (maximum).
M706-4

This page intentionally left blank.

M706-S

9-90LW

1 11

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330
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CAPACITORS ARE .Oluf,IODV,20%
RESISTORS ARE 1/4W; SOk
DIODES ARE 0664
PIN 7 ON EACH Ie;:; GND
PIN 14 ON EACH IC=+SV
£1 IS OEC7430N
E2, E5,£6, ES, EIO,EI3, E14,
[17 a EI9 ARE DEC7474N

E2I

:;
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E20

E3., E4, E7, E12, EI6 a E21 ARE DEC7400N
E9 a Ell ARE ofC741ON
[15,E20 ARE DEC7440N
EIB IS DEC7460N

PARTS

LIST A- PL- M70S-0-0

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M706-7

M707
Teletype Transmitter

The M707 Teletype Transmitter is a parallel-to-serial Teletype code converter self-contained on a double-height
module. This module includes all of the parallel-to-serial conversion, buffering, gating, and timing (excluding
only an external clock) necessary to transfer information in an asynchronous manner between a parallel binary
device and a serial data line or Teletype device. Either a S-bit or an 8-bit parallel character can be assembled into
a 7.0,7.5, or 8.0 unit serial character (or a 10.0, 10.5, or 11.0 unit serial character) by the M707 through the use
of different pin connections on the module. When conversion is complete, the necessary start bit and selected
stop bits (1.0, 1.5, or 2.0 units) have been added to the original parallel character and transmitted over the serial
line. In the PDP-IS, the Teletype transmitter is connected to assemble 8-bit characters consisting of II units.

AFI

AE1

iE2
CODE ~I::::::'\
CODE
SELECT Ati2
INPUTS

DEVICE
SELECTOR

ENABLE DS ANI

FLAG STROBE

BH2

CLE AR FLAG I

BD2

CLEA R FLAG 2

BF2

BJ2

STROBED FL AG

BK2

FLAG

~'VER
AV2

rCLOCKD~
L2~B~D
BP2

AD2

~ACTIVE(1)

WAIT BS2

10 CLEAR BE2

•

FLAG

SERIAL
OUTPUT

LINE

CONTROL
PIN CONNECTIONS FOR
5 OR 8 BIT CODE

BIT I
BIT 2
BIT 3
BIT4
BIT 5
BITS
BIT 7
BIT 8
ENABLE

5 BIT - AKI TO AJ
8 BIT - AKI TO AK 2

AUI
AT2
AS2
AU2

PIN CONNECTIONS FOR
STOP TIME

AM2
AL2
AR2
AP2

SHIFT
REGISTER

1.0 UNITS - BN2 TO BR2
1.5 UNITS - BN2 TO BPI
2.0 UNITS - BN2 TO BNI

AN2

~
ALI

LOA D BUFFER

AS'
15-0165

M707 Simplified Diagram

M707-I

LOAD
BUFFER

+ 3V

CLOCK

ACTIVE

+:vh h h h h h h h h h h h
+:vt~__~__~__~~__~__~__~____~__~__~____ ~
L -__

LINE

+3V

BIT

FLAG

BIT

BIT
4

____

STOP: STOP

IL---~-,-----,-----,--------,-~~I~I_
+:vtL-__~&
'~I__'__~.t

+:V
CLEAR
FLAG 2

__________________________________________

BEGINNING OF I
CHARACTER

END OF
CHARACTER
15-0171

M707 Timing Diagram

The serial character is transmitted with the start bit first, followed by bits I through 8 in order, and completed
by the stop bits. Coincident with the stop bit being put on the serial line, the FLAG output goes LOW indicating that the previous character has been transmitted and a new parallel character can be loaded into the M707.
Transmission of this new character does not occur until the stop bits from the previous character are completed.
See the timing diagram for additional information.
In addition to the above listed features, the M707 includes the necessary gating so that it can be used in a halfduplex system with the M706. Device selector gating is also provided to allow this module to be used on the
positive bus of a digital system.
The following are the input, output, and power characteristics of the M707 Teletype Transmitter.
INPUTS:

All inputs present one TTL unit load with the exception of the CLOCK input, which presents
ten unit loads. Where the use of input pulses is required, the pulse width must be 50 ns or
greater.
CLOCK:

The clock frequency must be twice the serial output bit rate. The
CLOCK input can be either pulses or a square wave.

BITS 1 through 8:

A HIGH level at the BITS I through 8 inputs is reflected as a logic I
or mark in the serial output. When a 5-bit code is used, BIT inputs
I through 5 should contain the parallel data; BIT 6 should be considered as an enable; and BITS 7, 8, and ENABLE should be
grounded.

ENABLE:

The ENABLE input provides the control flexibility necessary for
transmitter multiplexing. When grounded during a LOAD BUFFER
pulse, the ENABLE input prevents transmission of a character. The
ENABLE input can be driven from the output of an MI61 for scanning purposes or, in the case of a single transmitter, tied to +3V.

M707-2

WAIT:

If the WAIT input is grounded prior to the stop bits of a
transmitted character, the input then holds transmission of a succeeding character until the input is brought to a HIGH level. A
ground on this line does not prevent a new character from being
loaded into the shift register. This line is normally connected to
ACTIVE (0) on a M706 in half-duplex two wire systems. When
not used, the line should be tied to +3V.

CODE SELECT Inputs: When a positive AND condition occurs at the CODES SELECT inputs, the following signals assume their normal control functions:
FLAG STROBE; LOAD BUFFER; and CLEAR FLAG I. These
inputs are frequently used to multiplex transmitter modules when
signals such as LOAD BUFFER are common to numerous modules.
The CODE SELECT inputs can also be used for device selector inputs when the M707 is used on the positive bus of a digital system.
The CODE SELECT inputs must be present at least 50 ns prior to
any of the three signals that they enable. If it is desired to bypass
the CODE SELECT inputs, they can be left open and the ENABLE
D.S. line tied to ground.
CLEAR FLAG 1:

A HIGH level or positive pulse at the CLEAR FLAG I input while
the CODE SELECT inputs are all HIGH clears the flag. When not
used, this line should be grounded. Propagation delay from input
rise until the flag is cleared at the FLAG output is a maximum of
100 ns. The flag cannot be set if the CLEAR FLAG I input is held
at logic 1.

CLEAR FLAG 2:

A LOW level or negative pulse at the CLEAR FLAG 2 input clears
the flag. When not used, the CLEAR FLAG 2 input should be tied
to +3V. The flag remains cleared if this input is grounded. Propagation from input fall to flag output rise is a maximum of 80 ns.
If it is desired to clear the flag on a LOAD BUFFER pulse, CLEAR
FLAG 2 can be tied to pin AR 1 of the module.

FLAG STROBE:

If the flag is set and the CODE SELECT inputs are all HIGH, a
positive pulse at the FLAG STROBE generates a negative-going
pulse at the STROBED FLAG output. Propagation delay from the
strobe to output is a maximum of 30 ns.

I/O CLEAR:

A HIGH level or positive pulse at the I/O CLEAR input clears the
flag, clears the shift register, and initializes the state of the control.
This signal is not necessary if the first serial character transmitted
after power turn-on is not required to be correct. When not used,
or during transmission, the I/O CLEAR input should be at ground.

WAD BUFFER:

A HIGH level or positive pulse at the LOAD BUFFER input while
the CODE SELECT inputs are all HIGH loads the shift register buffer with the character to be transmitted. If the ENABLE input is
HIGH when the LOAD BUFFER input occurs, transmission begins
as soon as the stop bits from the previous character are counted out.
If a level is used, it must be returned to ground within one bit time
(twice the period of the clock).

M707-3

OUTPUTS:

POWER:

All outputs present normal TTL logic levels except the serial output driver, which is an open
collector PNP transistor with emitter returned to +5V.
SERIAL Output:

This open collector PNP transistor output can drive 20 rnA into
any load returned to a voltage between +4V and -15V. A logical
output or mark is +5V, and a logical 0 or space is an open circuit.
If inductive loads are driven by this output, diode protection must
be provided by connecting the cathode of a high-speed silicon diode
to the output and the diode anode to the coil supply voltage.

LINE:

The LINE output can drive ten TTL unit loads and presents the
SERIAL output signal with a logical I as +3V and a logical 0 as
ground.

FLAG:

The FLAG output falls from +3V to ground at the beginning of the
stop bits driving a character transmission. The M707 can then be
reloaded and the flag cleared (set to +3V). The FLAG output can
drive ten TTL unit loads.

STROBED FLAG:

The STROBED FLAG output is the NAND realization of the
INVERTED FLAG output and FLAG STROBE. Output drive
is ten TTL unit loads.

+3V:

Pin B11 can drive ten TTL unit loads at a +3V level.

The power dissipation of the M707 is +5V at 375 rnA (maximum).

M707-4

This page intentionally left blank.

M707-S

9-LOLW

AA2, BA2 +5V

1[ii'llIOOOOI
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~A02

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BK2 ~I. REO.

EI3
CLEAR FLAG 2
8F2------CLEAR FLAG •
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UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFO

RESISTORS ARE 1/4 W, 5%
DIODES ARE 0662
PIN 7 ON EACH Ie = GND
PIN 14 ON EACH Ie = +5V
E I 8 E9 ARE DEC7430N
E2, £6, E8, EII,EI4,EI5, EI6 II; EI7 ARE OEC7474N

E3, E4, £5 • £7 ,E12 •
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M707-7

M717
Display Control VP15

The M717 module contains the timing and control circuits req uired by the VP 15 point-plotting display. Since
anyone of three scopes can be used in the VP 15 display, the M717 module incorporates the necessary control
circuits for all three scopes. The scopes that can be used are the Tektronix RMS03, the DEC VRI2, and the
Tektronix 611 storage tube in both the store and nonstore modes. A simple patching arrangement selects the
required control circuits for a specific scope. The timing circuits on the module provide the necessary deflection
settling time delays and intensification pulses for all scopes. Light pen circuitry is provided for use with the
RMS03 and the VR 12. A display-done flag circuit and an erase control circuit are included for the 611. In addition, a two-bit brightness register is provided for controlling brightness on the RMS03 and the VRI2.
The power dissipation characteristics of the M717 module are:
IOVat 10 rnA
ISVat 10 rnA
SVat 130 rnA
30Vat 20 rnA

M717-1

•

THIS SCf-'EMATIC IS FURNISHED ONLY rOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATuRE AND SHOULD BE TRlATED ACCORDI"JGLY
COPYRIGHT 1969 BY DIGIlAl EQUIPMENT CORPORATION

INTANAAI

+5V

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PIN 7 = GND
PIN 14::+5V ON EI,E3,E4,E7, E8
83,E 9,EIO,EII,EI2
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INTEGRATED CKT. AM2602
INTEGRATED CKT, OEC7440
INTEGRATED CKT. OEC7474
INTEGRATlD CKT. D[C7410
INTEGRATED CKT, DEC7400
TRANSISTOR DEC6534C
TRANSISTOR DEC3009B
RES.
10K
1!4W 5% CC
RES.
47K
1/4W 10% CC

R25

RES,
RES.
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4.7K
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PIN 8= GND
PIN 16=+5V ON E2,E5,E6

~EFERENCE DESIGNATION

JUMPER NORMALLY OUT

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TRANSISTOR'" DIODE CONVERSION CHART
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15-0157

-.J
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M770
EAE Control

The M770 module contains a 6-bit timing generator and EAE control logic. One of these modules is used in the
PDP-IS central processor equipped with the EAE option (refer to Engineering Drawing D-BS-KE 15-0-4).
The following are the input, output, and power characteristics of the M770.
INPUTS AND OUTPUTS: M770 EAE control module inputs and outputs are standard TTL levels.

POWER:

The power dissipation of the M770 module is 5V at 500 rnA (maximum).

M770-1

il
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M770-2

•

~
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M771
Internal lOT Decoder

The M771 module contains combinational logic circuits to decode bits 6 through 13 of the Input/Output
Transfer (lOT) instructions of the PDP-IS.
The following are the input, output, and power characteristics of the M771 module.
INPUTS:

The table below lists all input connections and the TTL unit loading they present.
Name

NOT INT DSOO
INT DS01
INT DS02
INT DS03
INT DS04
INT DSOS
INT SDOO
INT SD01
INT IOPl
INT IOP2
INT IOP4
INT IOPI
MEM

Al
P2
D2
V2
U2
VI
M2
N1
S2
Sl
M1
D1
FI

S
4
4
6
S
S
S
4
4
4
4
1
I

OUTPUTS:

Each decoder output (except lOT 03XX pin PI) is capable of driving 10 unit loads. Pin PI
is capable of driving 7 unit loads.

POWER:

The power dissipation of the M771 module is SV at 74 rnA.

M771-1

T'<15 5C><E \!ATIC 15 " ~', ~"f D O",L Y FOf! lEST ANt' MAINH NANCE PURPOSES THE
e'R(UIT5 ARE ,~( f f,. ! r.h\ ,,< .,ATUfH ANl SHOU.C Bf TRLAlf 0 AC~ORDINGlY
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50',

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CLOF N2

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CLON J2

UNLESS OTHERWISE INDICATED:
PIN 7 ON EACH IC: GND
PIN 14 ON EACH IC = +5V
EI,E5 ARE DEC7400N
E2,E6,E7,E9,EI0 ARE DEC7402N
E3,E4,E8,EII,EI2 ARE OEC7430N
CAPACITORS ARE .OIMFD,IODV,20%

TRANSISTOR & DIODE CONVERSION CHART

mamaoma 'TNTERNA~7~~T
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DECODER

EQUIPMENT SIZE CODE
CORPORATION
c Cs M77I-0 - r
"''''~''''.O.'''''' ••''''HU •• TT. PRINTED CIRCUIT REV
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I I I

M772
Console Control No. 1

The M772 module contains 12 storage flip-flops and output gating circuits for generating 24 register strobes in
response to a 12-position rotary switch and a slide switch. The module is used in the console of the PDP-IS to
provide the strobes required for displaying selected data (refer to Engineering Drawing D-BS-KPIS-0-44).
The following are the input, output, and power characteristics of the M772 module.
INPUTS AND OUTPUTS: M772 inputs and outputs are standard TTL levels.
POWER:

Power dissipated in the M772 module is SV at 440 rnA (maximum).

M772-1

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M773
Console Control No. 2

The M773 module decodes the console switch and key signals. A 6-count register generates timing pulses that
strobe the address, data switches, and key functions such as STOP, START, CONTINUE, EXAMINE, and
DEPOSIT) to the I/O processor. The M773 module also contains logic circuits for controlling the repeat speed
functions (refer to Engineering Drawing D-BS-KPIS-0-4S).
The following are the input, output, and power characteristics of the M773 module.
INPUTS AND OUTPUTS: M773 inputs and outputs are standard TTL levels.
POWER:

The power dissipated in the M773 module is SV at 500 rnA (maximum).

M773-1

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M775
Time State Generator

The M775 module contains a 5-18 MHz variable clock and a four-stage ring counter. This module is used in the
central processor of the PDP-IS to divide each of the three time states of each cycle into four phases. The clock
frequency is adjusted to obtain a period equivalent to one time phase.
The following are the input, output, and power characteristics of the M775 module.
INPUTS:

OUTPUTS:

The table below lists all input connections and the TTL loading they present.
Name

REPEATTS2
SING TIME LOOP
TS2
ADD*TS2*E
ADD*TS2*E
CLOCK
CLEAR
STOP CLOCK

FI
EI
CI
Al
P2
R2
T2
PI

1.25
3.75
1.25
1.25
1.25
10
10
1.25

The table below lists all output connections and their unit load-driving capabilities.

Name
TIME STATE I
TIME STATE I
TIME STATE I
TIME STATE 2
TIME STATE 2
TIME STATE 2
TIME STATE 2A
TIME STATE 2A
TIME STATE 3
TIME STATE 3
TIME STATE 3
HS CLOCK
HSCLOCK

POWER:

Drive

Jl
K2
11
H2
12
L2
DI
M2
V2
D2
N2
E2
F2

9
36
36
9
36
36
8
36
9
36
36
II
36

Power dissipated in the M775 module is 5V at 325 rnA (maximum).

M775-1

THIS SCHEMATIC IS FURNISHED ONLY fOR TEST AND "''''INTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE 1R£ ... TEO ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

KE04 EAE RPT

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5~'

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6
4

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10

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V2
KP21 TIME STATE 3(O)H

+5V

1 1 1 I I I I I Om

01
KP21 TIME STATE 2A (0) H

KP21 TIME STATE 2 {oj H

I GNO

8
E7

il3r--v5

HI
KP21 TIME STATE I (0) H

[i2

1 1 1 1 I r r r I j ~i(FD
C3

Clo

C'3

_____

UNLESS OTHERWISE INDICATED:

E2
CAPACITORS ARE QIMFD,IOOV
RESISTORS ARE 1/4W,5%
PIN 7 ON EACH Ie = GND
PIN 14 ON EACH Ie = +5',1

EI IS DEC7400N
E3 IS DEC74HOON
E2,E4,E5-E7 ARE DEC74H40N
E8,E9,EI0,EI', ARE DEC74H72N

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M776
Reader Register

The M776 module contains two 6-bit buffer registers, output gates, and control logic. The module is used in
Reader Control PClS to serve as the interface between Paper Tape Reader PCOS and the PDP-IS, transferring
S-bit or IS-bit data words. For the IS-bit data transfers, three characters from the reader are automatically
assembled by the module.
The following are the input, output, and power characteristics of the M776 module.
INPUTS AND OUTPUTS: M776 Reader Register inputs and outputs are standard TTL levels.

POWER:

Power dissipated in the M776 module is SV at 470 rnA.

M776-1

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M776-2

00
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M901
Flexprint Cable Connector

The M90 I module allows 36 lines to be used as signals and/or grounds. The lOOn resistors connected in series
with the module pins A2, B2, U I, and V I are provided to afford some measure of protection if these pins are
inadvertently connected to a source of supply voltage.
The recommended current per line is 100 rnA (maximum).

M901-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIET.... RY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT
BY DIGITAL EQUIPMENT CORPORATION

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PARTS LIST
DESCRIPT ION
PARTS LIST

1300170
A-PL-M901-0-0
PART NO.

FLEXPRINT
CABLE CONNECTOR M901

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.............. 'u' ....... s ... C... U.II:TT.

SIZE

CODE

NUMBER

M901-0-1

PRINTED CIRCUIT REV

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M902
Terminator Card

The M902 module contains 18 terminating resistors connected to ground. Each resistor value is lOOn, 1/4W at
S%. This single-height board replaces the output cable of the last memory used on the PDP-IS memory bus.
Two of these boards are req uired for each PDP-IS system.
Ground pins are:
C2; F2; 12; L2; N2; R2; U2;
A I; C I; F I ; K I ; N I; R I ; and Tl.
The following are the input, output, and power characteristics of the M902 module.
INPUTS:

There are 18 inputs, one to each resistor.

OUTPUTS:

There are no outputs.

POWER:

The power dissipation of the M902 is 1.12SW (maximum).

M902-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULO BE TREATED ACCORDINGLY.
COPYRIGHT 191111 BY DIGITAL EQUIPMENT CORPORATION

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DEC

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IRES. 100 1/4W 5% CC
IPARTS LIST
DESCRIPTION
I
PARTS LIST

RES ISTOR
TERMINATOR M902

mamaDma I I
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1300229
IA-PL-M902-Q-O
I PART NO.

EQUIPMENT
CORPORATION

SIZE

CODE

NUMBER

M902-0-1

MAYNA"'O, MA ..... CHU . . . TT.

PRINTED CIRCUIT REV.

R~V.

IAI I I I I I 1

M904
Coaxial Cable Connector

The M904 connector is a single-size, double-sided board.
This connector provides high-density cable connections using coaxial cable. Provisions are made for connection
of two 9-conductor coaxial cables to the M904 connector. Eighteen signal leads and grounds are used.
The signal leads are:
B I; D I; E I; HI; J I; Ll; M I; PI ; S I
D2; E2; H2; K2; M2; P2; S2; T2; and V2.
The common (ground) leads are:
AI; CI; FI; KI; NI; RI; Tl;
C2; F2; 12; L2; N2; R2; and U2

M904-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION

GND

GND C2

fl2

>- COAXIAL

o
f"

\0
N

COAXIAL

M2 0

0.../

PARTS LIST IS A-P L-M904-0-0
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TITLE

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PRINTED CIRCUIT REV

EQUIPMENT
CORPORATION

SIZE

CONNECTOR
(COAXIAL) M904
CODE

NUMBER

M904-0-1

IR~V

lsi I I I I I I

M909
Terminator Card

This is a standard single-height M-series board with 18 terminating resistors connected to ground. All the resistors
are 68n, 1/4W at 5%.

GND Pins are: C2; F2; J2; L2; N2; R2; U2; AI; CI; FI; KI; NI; RI; and Tl.
The following are the input, output, and power characteristics of the M909 module.

INPUTS:

There are IS inputs; one to each resistor.

OUTPUTS:

There are no outputs.

POWER:

The power dissipation of the M909 is I.SW (maximum).

These boards replace the output cable of the last peripheral on the positive PDP-IS I/O bus.

M909-1

SCHEMATIC IS FURNISH£D ONLY FOR HST AND MAINTENANCE PURPOSES THE i
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREAHD ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

r'" THIS

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R 17

R 18

GND

s=
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b l b b l b b b l b l

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(>R9

UNLESS OTHERWISE INDICATED
RESISTORS ARE 68 1/4W 5%

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M909

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M910
CP Terminator Card

The M91 0 module contains eighteen 68il terminating resistors. Each resistor is connected to a common +5V
source. The resistors are used as load resistors to terminate the I/O bus lines in the PDP-IS.
Power dissipation is 1.8W (minimum) and 7.2W (maximum) .

M910-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
BY DIGITAL EQUIPMENT CORPORATION
COPYRIGHT

t5V
C3
A2
.OIMfD

GND
C2

(

V2
(

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C2

~fL

CI
HfD
C6

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C5
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RIO

RI2

RII

\0
.-

RI4

RI3

RI5

RI6

R 17

-It

RIB

(

(
JI

(

(
NI

L=jt±-

UNLESS OTHERWISE INDICATED:
CAPACITORS ARE 6.B MFD
RESISTORS ARE 6 B IIZW, 5%

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DEC

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momoomo

EQUIPMENT
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...... v ...... "O, .......... CHU.ETTS

TlTLEC

P TERMINATOR CARD
M910

M911
Memory Bus CP Terminator Card

The M911 module contains eighteen lOOn terminating resistors. Each resistor is connected to a common +5V
source. The resistors are used as load resistors to terminate all the memory bus lines at the CP end in the PDP-15.
Power dissipation is 1.25W (minimum) and 5.0W (maximum).

M9ll-l

THIS SCHEMATIC 15 FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY

+~V

GND
C2

(

;r~
C2

~.~
CI

(

Ar
s:::
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RIO

....

RI2

RII

RI3

RI4

RI5

RI7

RI6

RIB

~f±-

(
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(

(
JI

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PI

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UNLESS OTHERWISE INDICATED
CAPACITORS ARE 6.BMFD
RESISTORS ARE 100 1/2W ~%

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momoomo

EQUIPMENT
CORPORATION
...... VN ..... O

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TITLE

MEMORY BUS CPTERMINATOR
M911
NUMBER

SIZE JCOOE

M 911-0-1

PRINTED CIRCUIT REV

REV

IAI I I I I I I

M912
I/O Bus Connector

The M912 module is a double-height and double-sided FLIP CHIP connector card used in fabricating I/O bus
interconnect cables for peripheral devices.
Four of these cards are required to fabricate a BC09B cable, and two cards are needed to fabricate a BC09C cable.

M912-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD 8E TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

AAI
ABla

BAI
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ACI

BBI a

GND
AC2

ADla

a AD2

BDI a

<2>

a BD2

AEI a

a AE2

BEla

<2>

a BE2

a BH2

a BK2

a BM2

AF2

AFI

BFI

BF2

a AH2

BHla

no.

AJ2

BJI a

I])

a AK2

BKI

AL2

BLI a

(J)

aAM2

BMla

(J)

AN2

BNI

AHla

AJI a

AKI
~

s=\0

GND
BC2

BCI

ALI a

AMla

III

BJ2

0-----'
I])

ANI ~

B L2

BN2

API a

I])

a AP2

BPI a

AR2

BRI

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a AS2

BSI a

I])

a AT2

BTl

ARI
ASI a
AT!

(J)

a BP2

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a BS2

a BT2

AU2

BU2

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a AV2

BR2

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1·11-11
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DATE

TRANSISTOR & DIODE CONVERSION CHART

DEC

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BUS CONNECTOR CARD

M912

EQUIPMENT
CORPORATION

SIZE

CODE

................ O ............ CHU • • TT.

PRINTED CIRCUIT REV

NUMBER

M912 - 0

REV

JAJ J J J LI J

M915
Console Cable Connector

The M915 module is used in conjunction with the M901 module and a Flexprint cable to fabricate the I bus
interconnect cable. The M915 module contains twenty-four 750n terminating resistors and twenty-four 0.01 JlF
bypass capacitors. Each resistor is connected to a common +5V source. The resistors are used as load resistors
to terminate the I bus lines in the PDP-I 5 console, and the capacitors bypass the I bus lines to ground.
Power dissipation of the M915 module is 5V at 330 rnA.

M915-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY

----<

JI
~

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'-----<

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TI

RI7

RI9

R20

R21

R22

R23

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FLEXPR INT
+~V

rs::
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C2

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6.8~f

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l l t t l: t t:

35V
20%
(

(

)

V
FLEX PR INT

UNLESS OTHERWISE INDICATED
RES ISTORS ARE 390, 1/4 W, 5%

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CONSOLE CABLE CONNECTOR
CARD M915

M1701

Data Selector

The M 170 1 Data Selector contains two DEC74153 Dual 4-Line-to-l-Line Data Selector/Multiplexer integrated
circuits. These modules are used as input multiplexers in the ALU section of the FP 15 Floating-Point Processor.
Complete block schematics of these input multiplexers are shown on FP 15 drawings D-BS-FP 15-0-19 through
-28.
For each section of each IC, one of four data inputs is selected by combinations of address input signals A and B.
The selected data input is strobed to the output when the S (strobe) input goes low. Refer to the following truth
table.
Data Inputs
1
2
3

Strobe
S

Output

0
1

x
x

0
0

x
x

0
1

x
x

0
0

0
1

0
0

1
1

x
x

0
0

I
I

1
1

x
x

0
1

0
0

0
1

Address Inputs
B
A

0
0

1
I

x indicates irrevelancy. Address inputs A and B are common to
both sections of each IC.
INPUTS:

Each input represents 1 unit load.

ADD 02 H
ADD 03 (1) H

OUTPUTS:
POWER:

Each output is capable of driving
10 unit loads.

ADD 03 H
ADD 01 H

01
E1
F1

OUTPUT

Typical power dissipation is
170 mW for each IC on the
module.

ADD 03 H
ADD 04

(1) H

ADD 04 H
ADD 02 H

M1701
608
0

J2
K2
L2

OUTPUT

MXA
MX6

M1701-1

H
15-0566

'HIS SCHEM"IC IS IU~"SHED ON" FOR " " AND MAI","ANCE PUReOSES 'HE
elRCUllS ARE PROPRIETARY IN NATURE AND SHOULD 8E TREATED ACCORDINGLY

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INPUTS

ADDRESS

DATA
INPUTS

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STROBE 2

I
6
7

INPUTS

{I'
RI

DATA

2
ADDRESS

15,

MI
NI

STROBE 2 SI

DATA
INPUTS

""'"'~:;

+5V
A2
+:LCI
UNLESS OTHERWISE INDICATED:

GND
C2,TI

CAPACITORS ARE ,OIUF. IOOV,20%
IC'S ARE DEC74153

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TRANSISTOR & DIODE CONVERSION CHART

DEC

~""'~ -/9-71
DATE

PROD

DATE

DEC

~DmDDmD

TITLE

DATA SELECTOR MI701

IMI701-0-1

EQUIPMENT
CORPORATION

SIZE! CODE

... "'y ........ o, ........... CHuSI;TT5

PRINTED CIRCUIT REV
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NUMBER

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M1713
16-to-1 Data Selector

The M1713 16-To-1 Data Selector contains a single DEC74150 integrated circuit. It is used in the output
multiplexer section of the FPI5 Floating-Point Processor where up to 16 major register outputs are selected for
transfer to the common MPO bus. The block schematic of the output multiplexer is shown on D-BS-FP 15-0-03
of the FP15 drawings.
Data inputs are selected by combinations of data select signals MXA, MXB, MXC, and MXD, which are generated
by the multiplexer control logic shown on D-BS-FPI5-0-05. The strobe inputs are wired to ground so that each
IC is always enabled. A typical truth table for the 16-To-I Data Selector is shown in the following table.
Data Select Inputs
MXD

MXC

MXB

MXA

Data Input*
Selected

0
0
0
0
0
0
0
0
I
1
1
1
1
1
1
I

0
0
0
0
I
1
I
I
0
0
0
0
1
1
1
I

0
0
I
I
0
0
I
I
0
0
I
1
0
0
1
1

0
I
0
I
0
0
0
I
0
1
0
I
0
1
0
I

DIR12
JEAI2
ADD30
ADDI2
FMQ30
FMQI2
FMB30
FMBI2
EPBl2
FMA30
FMA12
EPAl2
IRI2
BMB30
BMBI2
MPI12

.=r
MPI 12 H
E2
BMB 12(1) H ~~

~~~2~~)(~)HM2 :~

EPA 12(1)H~;
13
FMA 12(1)H HI
12
FMA 30 (1)H F ' "
16-TO-l
EPB 12(1)H L1
10
OATA
FMB 12 (1) H 51
07 SELECTOR
FMB 30(1)H RI
g~ M1713
FMQ 12 (1)H P1
04
D18
FMQ 30 (1) H Nl

~gg ~20 ~

DIR 12 (1) H

01
00

Ml
JEA 12(1)H;~

ABC
MXA L
MXB L
MXC L
MXD L

'Signal mnemonics vary as shown on D-BS-FPlS-O-03.
Note that the output is the complement of the selected
input.

INPUTS:

Each input represents 1 unit load.

OUTPUTS:

The output is capable of driving up to 10 unit loads.

POWER:

Typical power dissipation is 200 mw.

M17l3-1

MPO

12 L

15-0563

ns,

'HIS SCHEMA'" IS FU",ISHED
FOP
AND MAINOFNANCE PU",OSES 'H
C1Rcuns ARE PROPRIUAR'I IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 19TO BY DIGITAL EQtJW,1fNT CORPORATION

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MI
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F2
H2
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CAPACITORS

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ARE .01 UF, IOOV, 20%

IC IS A DEC74150

N2
R2

•
3
2
EI

RI
SI

22
21
20

19
18
17
16
15
I.

13
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W010
Clamped Loads

The WO I 0 module contains fifteen identical 10 rnA clamped loads, each consisting of a resistor and a diode.
Each load resistor is connected to a common -15V source. The clamping diodes are connected to a -3V source,
which is obtained by a resistor-diode voltage divider.
Power dissipation of the WO I 0 module is 15V at 250 rnA.

WOlO-I

THIS SCHEMATIC IS FURNISHED ON" FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 19 •• BY DIGiTAL EQUIPMENT CORPORATION

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mamDoma

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TITLE

CLAMPED LOADS WOIO
SIZEj CO

DElWOIO-O-I

NUMBER

"""'''''''''''0, "''''SS"CHUSETTS PRINTED CIRCUIT REV

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W028
Cable Connector for Levels and Pulses

The W028 module provides cable connections to the FLIP CHIP mounting panel. The cable is a 19-conductor
ribbon with 9 signal leads and 10 shields. The signal leads are connected to pins D, E, H, K, M, P, S, T, and V.
The shields are internally connected together and to pins C, F, J, L, N, R, and U.

W028-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1968 iilY DIGITAL EQUIPMENT CORPORATION

00000
1

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DEC

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SIZE

CODE

NUMBER

W028-0-1

PRINTED CIRCUIT REV

W076
Teletype Connector

The W076 module is a universal interface module used in controlling a Teletype from logic using positive
voltages of +5V or + 1OV. The module is soldered to a cable that connects the Teletype to a computer.
Networks contained on the module set the current through the keyboard contacts and selector drive magnet.
Either -15V or -30V can be used across the commutator.
Power dissipation of the W076 is +5V at 25 rnA or + I OV at 25 rnA; -15V at 4 rnA or -30V at 51 rnA.

W076-1

THIS SCHEMATIC IS fURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1967 IiiY DIGITAL EQUIPMENT CORPORATION

TYPICAL PIN ASSIGNMENTS
A

r
F

~r 06
7

t
f

r- C7

r- C6

SPUT
LUGS

RELAY

_r-

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00
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00

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DEC FORM NO
ORB 102

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00 0
000
00 0

M. HALLER

... J

....

+SY

GND

GNO

GND

LOGIC INPUT

READER ENABLE READER ENABLE READER ENABU

LOGIC OUTPUT

M
D

LOGIC OUTPUT

LOGIC OUTPUT
-ISY

-30V OPTIONAL -30Y OPTIONAL -30Y OPTIONAL

DATE
~-18-67

EI.

5-23-67

_eSS40

IIPSIIM

DATE

0671

IN3653

R. SOGGE

!5-ze-&?
DATE

",C2
V
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R8
R6
R7
R3 R4
R2
RI
RS
DI-D8
C2-C7
CI

TRANSISTOR & DIODE CONVERSION CHART
DEC

DATE

N. PERRYMAN

PROD.

E
C5

REFERENCE DESIGNATION

CHK'O

ENG.

-ISY

. . . . . . . . . ,.,.

DRN.

-ISV

1-.:----------------1
~

+SV

c . . . . _ .. a ' ..

DC08

tSY

+
~~CI

-30V

8:1:,8L

+IOV

RS
RELAY

DEC

ElA

TRANSISTOR DEC65340
RES. 1.5K 1/4W S% CC
RES. I.IIK 1/2W 10% CC
RES. 10k 1/4W 10% CC
RES. 750 1/2W 5% CC
RES. 750 2W 5%
CC
RES. IK
IW
10% CC
RES. 120 1/2W 5% CC
DIODE 0671
CAP••0IMFD 100V 20% DISC
CAP. IMFD 150V 10% FOIL
PARTS LIST
DESCRIPTION
PARTS LIST
TITLE

mamlOla S'ZEjCODEl
EQUIPMENT
CORPORATION

MAVNARD, M .......C ... U • • TT.

1503409
1300391
1300400
1300481
1300354
I
1301984
1301499
1300243
1103309
1001610
1000063
A-PL-W076-0-0
PART NO.

TELETYPE
CONNECTOR W076

NUMBER

W076-0-1

PRINTED CIRCUIT REV

IROV

101 1 1 1 1 1 1

W714
Switches

The W714 module contains two switches accessible at the back of the module. These switches are used as bank
selection switches for the MM 15 memory extension and the MX 15A multiplexer.

W714-1

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST ANO MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

3000 3ZIS

-..l

)(
l"

I-O-t>ILMISOI 81

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ARE SPLIT LUGS
SWITCHES ARE MICRO-SWITCH 6AT56-T2

[DRN

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~HK'D
r
~,M

L .f

DATE

J-Z-7.1

D~TE I

TRANSISTOR & DIODE CONVERSION CHART
DEC

EIA

DEC FORM NO.
ORB 102

EIA

mamaDma
••

TITLE

SWITCH MODULE W714

•

Jlnl?"

E QUI P MEN T ~=-r=~r--~~;;;;-----TREv~

DATE

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I~ fa. "'" $AE?A~
PROD.

DEC

CORPORATIONI---L_-'--:--_ _

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W850
I/O Connector

The W850 module is a double-height FLIP CHIP connector card used in fabricating I/O bus interconnect cables
for peripheral devices.
Two of these modules are used to terminate each side of a cable having 36 twisted pairs, thus forming the BL09A
cable assembly. One wire of every twisted pair is connected to ground, while the signals carried by each of the
36 signal wires are clamped to -O.6V and -3.0V by diodes.
Power dissipation of the W850 module is 15V at 250 rnA (maximum).

W850-1

THIS "CHEMA III IS I UR'
'. I ?~L" ~(1R Tf ST ANll MA;NH "A"Ct .>:~';-:,~E,S, T HE
fIRCU,TSARlPR'"
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CAPACITORS ARE .01 MFO,IOOV,20%

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11-4-•• 0&62
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TRANSISTOR & DIODE CONVERSION CHART

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AC
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TITLE

momoamo I I

I. O. CONNECTOR

W850

EQUIPMENT
CORPORATION

S~E C~~E W8!jO~~~·r

..... yH .... D, .......... CHV ...

PRINTED CIRCUIT REV

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Digital Equipment Corporation
Maynard, Massachusetts

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