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XX-60467-DD

September 1995

328 pages

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Document:	MIPS IV Instruction Set
Order Number:	XX-60467-DD
Revision:
Pages:	328
Original Filename:	mips-isa.pdf

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MIPS IV Instruction Set
Revision 3.2
September, 1995

Charles Price

 MIPS Technologies, Inc. All Right Reserved
RESTRICTED RIGHTS LEGEND
Use, duplication, or disclosure of the technical data contained in this document by
the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the
Rights in Technical Data and Computer Software clause at DFARS 52.227-7013
and / or in similar or successor clauses in the FAR, or in the DOD or NASA FAR
Supplement. Unpublished rights reserved under the Copyright Laws of the
United States. Contractor / manufacturer is MIPS Technologies, Inc., 2011 N.
Shoreline Blvd., Mountain View, CA 94039-7311.

R2000, R3000, R6000, R4000, R4400, R4200, R8000, R4300 and R10000 are
trademarks of MIPS Technologies, Inc. MIPS and R3000 are registered trademarks
of MIPS Technologies, Inc.

The information in this document is preliminary and subject to change without
notice. MIPS Technologies, Inc. (MTI) reserves the right to change any portion of
the product described herein to improve function or design. MTI does not assume
liability arising out of the application or use of any product or circuit described
herein.

Information on MIPS products is available electronically:
(a) Through the World Wide Web. Point your WWW client to:
http://www.mips.com
(b) Through ftp from the internet site “sgigate.sgi.com”. Login as “ftp” or
“anonymous” and then cd to the directory “pub/doc”.
(c) Through an automated FAX service:
Inside the USA toll free: (800) 446-6477 (800-IGO-MIPS)
Outside the USA:

(415) 688-4321 (call from a FAX machine)

MIPS Technologies, Inc.
2011 N. Shoreline Blvd.
Mountain View, CA 94039-7311
Phone: USA toll free:

(800) 998-6477

Outside USA: (415) 933-6477

MIPS IV Instruction Set. Rev 3.2

MIPS IV Instruction Set
CPU Instruction Set
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Functional Instruction Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Load and Store Instructions . . . . .
Delayed Loads . . . . . . . . .
CPU Loads and Stores . . . . . .
Atomic Update Loads and Stores .
Coprocessor Loads and Stores . .
Computational Instructions . . . . .
ALU. . . . . . . . . . . . . .
Shifts . . . . . . . . . . . . .
Multiply and Divide. . . . . . .
Jump and Branch Instructions . . . .
Miscellaneous Instructions . . . . . .
Exception Instructions . . . . . .
Serialization Instructions . . . . .
Conditional Move Instructions . .
Prefetch . . . . . . . . . . . .
Coprocessor Instructions . . . . . .
Coprocessor Load and Store . . .
Coprocessor Operations . . . . .

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. . A-2
. . A-3
. . A-4
. . A-5
. . A-5
. . A-6
. . A-6
. . A-7
. . A-8
. . A-8
. . A-9
. . A-9
. A-10
. A-10
. A-10
. A-11
. A-12
. A-12

Memory Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
Uncached . . . . . . . . . . . . . . .
Cached Noncoherent . . . . . . . . . .
Cached Coherent . . . . . . . . . . . .
Cached . . . . . . . . . . . . . . . .
Mixing References with Different Access Types.
Cache Coherence Algorithms and Access Types
Implementation-Specific Access Types . . . .

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. A-12
. A-12
. A-13
. A-13
. A-13
. A-14
. A-14

Description of an Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
Instruction mnemonic and name . . . . . .
Instruction encoding picture . . . . . . . .
Format . . . . . . . . . . . . . . . . .
Purpose . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . .
Restrictions . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . .
Exceptions . . . . . . . . . . . . . . . .
Programming Notes, Implementation Notes .

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. A-15
. A-16
. A-16
. A-16
. A-16
. A-17
. A-17
. A-17
. A-18

Operation Section Notation and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18
Pseudocode Language . . . . . . . . . . . . .
Pseudocode Symbols . . . . . . . . . . . . . .
Pseudocode Functions. . . . . . . . . . . . . .
Coprocessor General Register Access Functions .
Load and Store Memory Functions . . . . . .
CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

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. A-18
. A-18
. A-20
. A-20
. A-21

Access Functions for Floating-Point Registers . . . . . . . . . . . . A-24
Miscellaneous Functions . . . . . . . . . . . . . . . . . . . . . A-26

Individual CPU Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
CPU Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-174
CPU Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-175
Instruction Decode . . . . . . . . . . . . . . . . . . . . .
SPECIAL Instruction Class. . . . . . . . . . . . . . . .
REGIMM Instruction Class . . . . . . . . . . . . . . .
Instruction Subsets of MIPS III and MIPS IV Processors. . . . . .
Non-CPU Instructions in the Tables . . . . . . . . . . . . . .
Coprocessor 0 - COP0 . . . . . . . . . . . . . . . . . .
Coprocessor 1 - COP1, COP1X, MOVCI, and CP1 load/store. .
Coprocessor 2 - COP2 and CP2 load/store. . . . . . . . . .
Coprocessor 3 - COP3 and CP3 load/store. . . . . . . . . .

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. A-175
. A-175
. A-175
. A-175
. A-176
. A-176
. A-176
. A-176
. A-176

FPU Instruction Set
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
FPU Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Floating-point formats. . . . . . . . . . . . . .
Normalized and Denormalized Numbers . . .
Reserved Operand Values — Infinity and NaN .
Fixed-point formats . . . . . . . . . . . . . .

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. B-3
. B-4
. B-4
. B-6

Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
Organization . . . . . . . . . . . . . .
Binary Data Transfers . . . . . . . . . .
Formatted Operand Layout . . . . . . .
Implementation and Revision Register . .
FPU Control and Status Register — FCSR .

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. B-7
. B-7
. B-9
B-10
B-10

Values in FP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13
FPU Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14
Precise Exception Mode . . . . . . . . .
Imprecise Exception Mode . . . . . . . .
Exception Condition Definitions . . . . .
Invalid Operation exception . . . . .
Division By Zero exception . . . . . .
Overflow exception . . . . . . . . .
Underflow exception . . . . . . . .
Inexact exception . . . . . . . . . .
Unimplemented Operation exception .

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B-15
B-16
B-16
B-17
B-18
B-18
B-18
B-19
B-19

Functional Instruction Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19
Data Transfer Instructions . . . . . . . . .
Arithmetic Instructions . . . . . . . . . .
Conversion Instructions . . . . . . . . . .
Formatted Operand Value Move Instructions.
Conditional Branch Instructions . . . . . .

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MIPS IV Instruction Set. Rev 3.2

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B-19
B-21
B-22
B-23
B-23

CPU Instruction Set

Miscellaneous Instructions . . . . . . . . . . . . . . . . . . . . . B-24
CPU Conditional Move . . . . . . . . . . . . . . . . . . . . . B-24

Valid Operands for FP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24
Description of an Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-26
Operation Notation Conventions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . B-26
Individual FPU Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-27
FPU Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-95
FPU (CP1) Instruction Opcode Bit Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-98
Instruction Decode . . . . . . . . . . . . . . . . .
COP1 Instruction Class . . . . . . . . . . . . .
COP1X Instruction Class . . . . . . . . . . . . .
SPECIAL Instruction Class . . . . . . . . . . . .
Instruction Subsets of MIPS III and MIPS IV Processors. .

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

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B-98
B-98
B-99
B-99
B-99

List of Figures
Figure A-1.
Figure A-2.
Figure A-3.
Figure A-4.
Figure A-5.
Figure A-6.
Figure A-7.
Figure A-8.
Figure A-9.
Figure A-10.
Figure B-1.
Figure B-2.
Figure B-3.
Figure B-4.
Figure B-5.
Figure B-6.
Figure B-7.
Figure B-8.
Figure B-9.
Figure B-10.
Figure B-11.
Figure B-12.
Figure B-13.
Figure B-14.
Figure B-15.
Figure B-16.

Example Instruction Description . . . . . . . . . . . . . . . . .
Unaligned Doubleword Load using LDL and LDR. . . . . . . . .
Unaligned Doubleword Load using LDR and LDL. . . . . . . . .
Unaligned Word Load using LWL and LWR. . . . . . . . . . . .
Unaligned Word Load using LWR and LWL. . . . . . . . . . . .
Unaligned Doubleword Store with SDL and SDR . . . . . . . . .
Unaligned Doubleword Store with SDR and SDL . . . . . . . . .
Unaligned Word Store using SWL and SWR. . . . . . . . . . . .
Unaligned Word Store using SWR and SWL. . . . . . . . . . . .
CPU Instruction Formats . . . . . . . . . . . . . . . . . . . .
Single-Precision Floating-Point Format (S) . . . . . . . . . . . .
Double-Precision Floating-Point Format (D) . . . . . . . . . . . .
Word Fixed-Point Format (W) . . . . . . . . . . . . . . . . . .
Longword Fixed-Point Format (L) . . . . . . . . . . . . . . . .
Coprocessor 1 General Registers (FGRs) . . . . . . . . . . . . .
Effect of FPU Word Load or Move-to Operations . . . . . . . . .
Effect of FPU Doubleword Load or Move-to Operations . . . . . .
Floating-point Operand Register (FPR) Organization . . . . . . . .
Single Floating Point (S) or Word Fixed (W) Operand in an FPR . . .
Double Floating Point (D) or Long Fixed (L) Operand In an FPR . . .
FPU Implementation and Revision Register . . . . . . . . . . . .
MIPS I - FPU Control and Status Register (FCSR) . . . . . . . . .
MIPS III - FPU Control and Status Register (FCSR) . . . . . . . . .
MIPS IV - FPU Control and Status Register (FCSR) . . . . . . . . .
The Effect of FPU Operations on the Format of Values Held in FPRs. .
FPU Instruction Formats . . . . . . . . . . . . . . . . . . . .

MIPS IV Instruction Set. Rev 3.2

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. A-15
. A-83
. A-85
. A-97
. A-100
. A-129
. A-131
. A-149
. A-152
. A-174
. . B-3
. . B-4
. . B-6
. . B-6
. . B-7
. . B-8
. . B-8
. . B-9
. . B-9
. B-10
. B-10
. B-11
. B-11
. B-11
. B-14
. B-95

CPU Instruction Set

List of Tables
Table A-1.
Table A-2.
Table A-3.
Table A-4.
Table A-5.
Table A-6.
Table A-7.
Table A-8.
Table A-9.
Table A-10.
Table A-11.
Table A-12.
Table A-13.
Table A-14.
Table A-15.
Table A-16.
Table A-17.
Table A-18.
Table A-19.
Table A-20.
Table A-21.
Table A-22.
Table A-23.
Table A-24.
Table A-25.
Table A-26.
Table A-27.
Table A-28.
Table A-29.
Table A-30.
Table A-31.
Table A-32.
Table A-33.
Table A-34.
Table A-35.
Table A-36.
Table A-37.
Table A-38.
Table A-39.

Load/Store Operations Using Register + Offset Addressing Mode. . .
Load/Store Operations Using Register + Register Addressing Mode. .
Normal CPU Load/Store Instructions . . . . . . . . . . . . . .
Unaligned CPU Load/Store Instructions . . . . . . . . . . . . .
Atomic Update CPU Load/Store Instructions . . . . . . . . . . .
Coprocessor Load/Store Instructions . . . . . . . . . . . . . .
FPU Load/Store Instructions Using Register + Register Addressing .
ALU Instructions With an Immediate Operand . . . . . . . . . .
3-Operand ALU Instructions . . . . . . . . . . . . . . . . . .
Shift Instructions . . . . . . . . . . . . . . . . . . . . . . .
Multiply/Divide Instructions . . . . . . . . . . . . . . . . . .
Jump Instructions Jumping Within a 256 Megabyte Region . . . . .
Jump Instructions to Absolute Address
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PC-Relative Conditional Branch Instructions Comparing 2 Registers .
PC-Relative Conditional Branch Instructions Comparing Against Zero
System Call and Breakpoint Instructions . . . . . . . . . . . . .
Trap-on-Condition Instructions Comparing Two Registers . . . . .
Trap-on-Condition Instructions Comparing an Immediate . . . . .
Serialization Instructions . . . . . . . . . . . . . . . . . . . .
CPU Conditional Move Instructions . . . . . . . . . . . . . . .
Prefetch Using Register + Offset Address Mode . . . . . . . . . .
Prefetch Using Register + Register Address Mode . . . . . . . . .
Coprocessor Definition and Use in the MIPS Architecture . . . . . .
Coprocessor Operation Instructions . . . . . . . . . . . . . . .
Symbols in Instruction Operation Statements . . . . . . . . . . .
Coprocessor General Register Access Functions . . . . . . . . . .
AccessLength Specifications for Loads/Stores . . . . . . . . . . .
Bytes Loaded by LDL Instruction . . . . . . . . . . . . . . . .
Bytes Loaded by LDR Instruction . . . . . . . . . . . . . . . .
Bytes Loaded by LWL Instruction . . . . . . . . . . . . . . . .
Bytes Loaded by LWR Instruction . . . . . . . . . . . . . . . .
Values of Hint Field for Prefetch Instruction . . . . . . . . . . . .
Bytes Stored by SDL Instruction . . . . . . . . . . . . . . . . .
Bytes Stored by SDR Instruction . . . . . . . . . . . . . . . . .
Bytes Stored by SWL Instruction . . . . . . . . . . . . . . . . .
Bytes Stored by SWR Instruction . . . . . . . . . . . . . . . . .
CPU Instruction Encoding - MIPS I Architecture . . . . . . . . . .
CPU Instruction Encoding - MIPS II Architecture . . . . . . . . .
CPU Instruction Encoding - MIPS III Architecture . . . . . . . . .

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

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. A-3
. A-3
. A-4
. A-4
. A-5
. A-5
. A-5
. A-6
. A-7
. A-7
. A-8
. A-9
. A-9
. A-9
. A-9
. A-9
. A-10
. A-10
. A-10
. A-10
. A-11
. A-11
. A-11
. A-12
. A-19
. A-21
. A-24
. A-84
. A-86
. A-98
A-101
A-117
A-130
A-132
A-150
A-153
A-177
A-178
A-179

Table A-40.
Table A-41.
Table A-42.
Table A-43.
Table A-44.
Table B-1.
Table B-2.
Table B-3.
Table B-4.
Table B-5.
Table B-6.
Table B-7.
Table B-8.
Table B-9.
Table B-10.
Table B-11.
Table B-12.
Table B-13.
Table B-14.
Table B-15.
Table B-16.
Table B-17.
Table B-18.
Table B-19.
Table B-20.
Table B-21.
Table B-22.
Table B-23.
Table B-24.
Table B-25.
Table B-26.
Table B-27.
Table B-28.
Table B-29.
Table B-30.

CPU Instruction Encoding - MIPS IV Architecture . . . . . . . . . .
Architecture Level in Which CPU Instructions are Defined or Extended.
CPU Instruction Encoding Changes - MIPS II Revision. . . . . . . .
CPU Instruction Encoding Changes - MIPS III Revision. . . . . . . .
CPU Instruction Encoding Changes - MIPS IV Revision. . . . . . . .
Parameters of Floating-Point Formats . . . . . . . . . . . . . . .
Value of Single or Double Floating-Point Format Encoding . . . . . .
Value Supplied when a new Quiet NaN is Created . . . . . . . . . .
Default Result for IEEE Exceptions Not Trapped Precisely . . . . . .
FPU Loads and Stores Using Register + Offset Address Mode
. . . .
FPU Loads and Using Register + Register Address Mode
. . . . . .
FPU Move To/From Instructions . . . . . . . . . . . . . . . . .
FPU IEEE Arithmetic Operations . . . . . . . . . . . . . . . . .
FPU Approximate Arithmetic Operations . . . . . . . . . . . . .
FPU Multiply-Accumulate Arithmetic Operations . . . . . . . . . .
FPU Conversion Operations Using the FCSR Rounding Mode . . . .
FPU Conversion Operations Using a Directed Rounding Mode . . . .
FPU Formatted Operand Move Instructions . . . . . . . . . . . . .
FPU Conditional Move on True/False Instructions . . . . . . . . .
FPU Conditional Move on Zero/Nonzero Instructions
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FPU Conditional Branch Instructions . . . . . . . . . . . . . . .
CPU Conditional Move on FPU True/False Instructions . . . . . . .
FPU Operand Format Field (fmt, fmt3) Decoding . . . . . . . . . .
Valid Formats for FPU Operations . . . . . . . . . . . . . . . .
FPU Comparisons Without Special Operand Exceptions . . . . . . .
FPU Comparisons With Special Operand Exceptions for QNaNs . . .
Values of Hint Field for Prefetch Instruction . . . . . . . . . . . .
FPU (CP1) Instruction Encoding - MIPS I Architecture . . . . . . . .
FPU (CP1) Instruction Encoding - MIPS II Architecture . . . . . . .
FPU (CP1) Instruction Encoding - MIPS III Architecture . . . . . . .
FPU (CP1) Instruction Encoding - MIPS IV Architecture . . . . . . .
Architecture Level In Which FPU Instructions are Defined or Extended.
FPU Instruction Encoding Changes - MIPS II Architecture Revision. . .
FPU Instruction Encoding Changes - MIPS III Revision. . . . . . . .
FPU Instruction Encoding Changes - MIPS IV Revision.
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MIPS IV Instruction Set. Rev 3.2

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. A-180
. A-181
. A-182
. A-183
. A-184
. . B-3
. . B-4
. . B-6
. B-17
. B-20
. B-20
. B-20
. B-21
. B-21
. B-21
. B-22
. B-22
. B-23
. B-23
. B-23
. B-24
. B-24
. B-25
. B-25
. B-39
. B-40
. B-79
. B-100
. B-102
. B-104
. B-106
. B-109
. B-112
. B-114
. B-116

CPU Instruction Set

Revision History
2.0 (Jan 94): First General Release
This version contained incorrect definitions for MSUB and NMSUB. It did not
contain the RECIP and RSQRT instructions. It contained incomplete or erroneous
information for LL, LLD, SC, SCD, SYNC, PREF, and PREFX.
All copies of this version of the document should be destroyed

2.2 (Jul 94): Mandatory Replacement of Rev 2.0
This version should probably have been 3.0 since it is a major content change.
This version is issued with no known errors. It includes the late changes to the
MIPS IV definition including the reintroduction of RECIP and RSQRT and the
definition of the multiply-accumulate instructions as unfused (rounded)
operations.

3.0 (Oct 94):
Add itemized instruction lists in the discussion of instruction functional groups.
Add a more complete description of FPU operation
Correct problems discovered with Revision 2.2.

3.1 (Jan 95):
Correct minor problems discovered with Revision 3.0.

3.2 (Sep 95):
Revise the opcode encoding tables significantly.
Correct minor problems discovered with Revision 3.1.

Changes from previous revision:
Changes are generally marked by change bars in the outer margin of the page -just like the bar to the side of this line. Minor corrections to punctuation and
spelling are neither marked with change bars nor noted in this list. Some changes
in figures are not marked by change bars due to limitations of the publishing tools.

CVT.D.fmt Instruction
Change the architecture level for the CVT.D.L version of the instruction
from:
to:
MIPS III

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

CVT.S.fmt Instruction
Change the architecture level for the CVT.S.L version of the instruction
from:
to:
MIPS III

LWL Instruction
In the example in Fig. A-4 the sign extension “After executing LWL $24,2($0)”
should be changed
from:
no cng or sign ext
to:
sign bit (31) extend.
The information in the tables later in the instruction description is correct.

MOVF Instruction
Change the name of the constant value in the function field
from:
MOVC
to:
MOVCI
There is a corresponding change in the FPU opcode encoding table in section B.12
with opcode=SPECIAL and function=MOVC, changing the value to MOVCI.

MOVF.fmt Instruction
Change the name of the constant value in the function field
from:
MOVC
to:
MOVCF
There is a corresponding change in the FPU opcode encoding table in section B.12
with opcode=COP1, fmt = S or D, and function=MOVC, changing the value to
MOVCI.

MOVT.fmt Instruction
Change the name of the constant value in the function field
from:
MOVC
to:
MOVCF
There is a corresponding change in the FPU opcode encoding table in section B.12
with opcode=COP1, fmt = S or D, and function=MOVC, changing the value to
MOVCI.

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

CPU Instruction Encoding tables
Revise the presentation of the opcode encoding in section A 8 for greater clarity
when considering different architecture levels or operating a MIPS III or MIPS IV
processor in the MIPS II or MIPS III instruction subset modes.
There is a separate encoding table for each architecture level. There is a table of the
MIPS IV encodings showing the architecture level at which each opcode was first
defined and subsequently modified or extended. There is a separate table for each
architecture revision Ι→II, II→III, and III→IV showing the changes made in that
revision.

FPU Instruction Encoding tables
Revise the presentation of the opcode encoding in section B.12 for greater clarity
when considering different architecture levels or operating a MIPS III or MIPS IV
processor in the MIPS II or MIPS III instruction subset modes.
There is a separate encoding table for each architecture level. There is a table of the
MIPS IV encodings showing the architecture level at which each opcode was first
defined and subsequently modified or extended. There is a separate table for each
architecture revision Ι→II, II→III, and III→IV showing the changes made in that
revision.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Introduction
This appendix describes the instruction set architecture (ISA) for the central
processing unit (CPU) in the MIPS IV architecture. The CPU architecture defines
the non-privileged instructions that execute in user mode. It does not define
privileged instructions providing processor control executed by the
implementation-specific System Control Processor. Instructions for the floatingpoint unit are described in Appendix B.
The original MIPS I CPU ISA has been
extended in a backward-compatible
fashion three times. The ISA extensions
are inclusive as the diagram illustrates;
each new architecture level (or version)
includes the former levels. The
description of an architectural feature
includes the architecture level in which
the feature is (first) defined or
extended. The feature is also available
in all later (higher) levels of the
architecture.

MIPS I
MIPS II
MIPS III
MIPS IV

MIPS Architecture Extensions
The practical result is that a processor implementing MIPS IV is also able to run
MIPS I, MIPS II, or MIPS III binary programs without change.
CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-1

The CPU instruction set is first summarized by functional group then each
instruction is described separately in alphabetical order. The appendix describes
the organization of the individual instruction descriptions and the notation used
in them (including FPU instructions). It concludes with the CPU instruction
formats and opcode encoding tables.

Functional Instruction Groups
CPU instructions are divided into the following functional groups:
•

Load and Store

•

ALU

•

Jump and

•

Miscellaneous

•

Co processor

Branch

A 2.1 Load and Store Instructions
Load and store instructions transfer data between the memory system and the
general register sets in the CPU and the coprocessors. There are separate
instructions for different purposes: transferring various sized fields, treating
loaded data as signed or unsigned integers, accessing unaligned fields, selecting
the addressing mode, and providing atomic memory update (read-modify-write).
Regardless of byte ordering (big- or little-endian), the address of a halfword, word,
or doubleword is the smallest byte address among the bytes forming the object.
For big-endian ordering this is the most-significant byte; for a little-endian
ordering this is the least-significant byte.
Except for the few specialized instructions listed in Table A-4, loads and stores
must access naturally aligned objects. An attempt to load or store an object at an
address that is not an even multiple of the size of the object will cause an Address
Error exception.
Load and store operations have been added in each revision of the architecture:
MIPS II
•

64-bit coprocessor transfers

•

atomic update

MIPS III
•

64-bit CPU transfers

•

unsigned word load for CPU

MIPS IV
•

A-2

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Tables A-1 and A-2 tabulate the supported load and store operations and indicate
the MIPS architecture level at which each operation was first supported. The
instructions themselves are listed in the following sections.
Table A-1

Load/Store Operations Using Register + Offset Addressing Mode.
CPU

Data Size

coprocessor (except 0)

Load
Signed

Load
Unsigned

Store

Load

Store

byte

halfword

word

III

doubleword

III

unaligned word

unaligned doubleword

III

linked word
(atomic modify)

linked doubleword
(atomic modify)

III

Table A-2

Load/Store Operations Using Register + Register Addressing Mode.
floating-point coprocessor only

Data Size

A 2.1.1

Load

Store

word

doubleword

Delayed Loads
The MIPS I architecture defines delayed loads; an instruction scheduling
restriction requires that an instruction immediately following a load into register
Rn cannot use Rn as a source register. The time between the load instruction and
the time the data is available is the “load delay slot”. If no useful instruction can
be put into the load delay slot, then a null operation (assembler mnemonic NOP)
must be inserted.
In MIPS II, this instruction scheduling restriction is removed. Programs will
execute correctly when the loaded data is used by the instruction following the
load, but this may require extra real cycles. Most processors cannot actually load
data quickly enough for immediate use and the processor will be forced to wait
until the data is available. Scheduling load delay slots is desirable for performance
reasons even when it is not necessary for correctness.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-3

A 2.1.2 CPU Loads and Stores
There are instructions to transfer different amounts of data: bytes, halfwords,
words, and doublewords. Signed and unsigned integers of different sizes are
supported by loads that either sign-extend or zero-extend the data loaded into the
register.
Table A-3

Normal CPU Load/Store Instructions

Mnemonic

Description

LB
LBU
SB

Load Byte
Load Byte Unsigned
Store Byte

LH
LHU
SH

Load Halfword
Load Halfword Unsigned
Store Halfword

I
I
I

LW
LWU
SW

Load Word
Load Word Unsigned
Store Word

I
III
I

LD
SD

Load Doubleword
Store Doubleword

III
III

Defined in

MIPS I
I
I

Unaligned words and doublewords can be loaded or stored in only two
instructions by using a pair of special instructions. The load instructions read the
left-side or right-side bytes (left or right side of register) from an aligned word and
merge them into the correct bytes of the destination register. MIPS I, though it
prohibits other use of loaded data in the load delay slot, permits LWL and LWR
instructions targeting the same destination register to be executed sequentially.
Store instructions select the correct bytes from a source register and update only
those bytes in an aligned memory word (or doubleword).

A-4

Table A-4

Unaligned CPU Load/Store Instructions

Mnemonic

Description

LWL
LWR
SWL
SWR

Load Word Left
Load Word Right
Store Word Left
Store Word Right

LDL
LDR
SDL
SDR

Load Doubleword Left
Load Doubleword Right
Store Doubleword Left
Store Doubleword Right

Defined in

MIPS I
I
I
I
III
III
III
III

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

A 2.1.3 Atomic Update Loads and Stores
There are paired instructions, Load Linked and Store Conditional, that can be used
to perform atomic read-modify-write of word and doubleword cached memory
locations. These instructions are used in carefully coded sequences to provide one
of several synchronization primitives, including test-and-set, bit-level locks,
semaphores, and sequencers/event counts. The individual instruction
descriptions describe how to use them.
Table A-5

Atomic Update CPU Load/Store Instructions

Mnemonic

Description

LL
SC

Load Linked Word
Store Conditional Word

LLD
SCD

Load Linked Doubleword
Store Conditional Doubleword

Defined in

MIPS II
II
III
III

A 2.1.4 Coprocessor Loads and Stores
These loads and stores are coprocessor instructions, however it seems more useful
to summarize all load and store instructions in one place instead of listing them in
the coprocessor instructions functional group.
If a particular coprocessor is not enabled, loads and stores to that processor cannot
execute and will cause a Coprocessor Unusable exception. Enabling a coprocessor
is a privileged operation provided by the System Control Coprocessor.
Table A-6

Coprocessor Load/Store Instructions

Mnemonic

Description

LWCz
SWCz

Load Word to Coprocessor-z
Store Word from Coprocessor-z

LDCz
SDCz

Load Doubleword to Coprocessor-z
Store Doubleword from Coprocessor-z

Table A-7

FPU Load/Store Instructions Using Register + Register Addressing

Mnemonic

Description

Defined in

LWXC1
SWXC1

Load Word Indexed to Floating Point
Store Word Indexed from Floating Point

MIPS IV
IV

LDXC1
SDXC1

Load Doubleword Indexed to Floating Point
Store Doubleword Indexed from Floating Point

CPU Instruction Set

Defined in

MIPS IV Instruction Set. Rev 3.2

MIPS I
I
II
II

IV
IV

A-5

A 2.2 Computational Instructions
Two’s complement arithmetic is performed on integers represented in two’s
complement notation. There are signed versions of add, subtract, multiply, and
divide. There are add and subtract operations, called “unsigned”, that are actually
modulo arithmetic without overflow detection. There are unsigned versions of
multiply and divide. There is a full complement of shift and logical operations.
MIPS I provides 32-bit integers and 32-bit arithmetic. MIPS III adds 64-bit integers
and provides separate arithmetic and shift instructions for 64-bit operands.
Logical operations are not sensitive to the width of the register.
A 2.2.5 ALU
Some arithmetic and logical instructions operate on one operand from a register
and the other from a 16-bit immediate value in the instruction word. The
immediate operand is treated as signed for the arithmetic and compare
instructions, and treated as logical (zero-extended to register length) for the logical
instructions.

A-6

Table A-8

ALU Instructions With an Immediate Operand

Mnemonic

Description

ADDI
ADDIU
SLTI
SLTIU
ANDI
ORI
XORI
LUI

Add Immediate Word
Add Immediate Unsigned Word
Set on Less Than Immediate
Set on Less Than Immediate Unsigned
And Immediate
Or Immediate
Exclusive Or Immediate
Load Upper Immediate

MIPS I
I
I
I
I
I
I
I

DADDI
DADDIU

Doubleword Add Immediate
Doubleword Add Immediate Unsigned

III
III

Defined in

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Table A-9

3-Operand ALU Instructions

Mnemonic

Description

ADD
ADDU
SUB
SUBU

Add Word
Add Unsigned Word
Subtract Word
Subtract Unsigned Word

DADD
DADDU
DSUB
DSUBU

Doubleword Add
Doubleword Add Unsigned
Doubleword Subtract
Doubleword Subtract
Unsigned

III
III
III
III

SLT
SLTU
AND
OR

Set on Less Than
Set on Less Than Unsigned
And
Or

XOR

Exclusive Or

NOR

Nor

I
I
I
I
I
I

Defined in

MIPS I
I
I
I

A 2.2.6 Shifts
There are shift instructions that take the shift amount from a 5-bit field in the
instruction word and shift instructions that take a shift amount from the low-order
bits of a general register. The instructions with a fixed shift amount are limited to
a 5-bit shift count, so there are separate instructions for doubleword shifts of 0-31
bits and 32-63 bits.
Table A-10

Shift Instructions

Mnemonic

Description

SLL
SRL
SRA
SLLV
SRLV
SRAV

Shift Word Left Logical
Shift Word Right Logical
Shift Word Right Arithmetic
Shift Word Left Logical Variable
Shift Word Right Logical Variable
Shift Word Right Arithmetic Variable

Defined in

DSLL
DSRL
DSRA
DSLL32
DSRL32
DSRA32
DSLLV
DSRLV
DSRAV

Doubleword Shift Left Logical
Doubleword Shift Right Logical
Doubleword Shift Right Arithmetic
Doubleword Shift Left Logical + 32
Doubleword Shift Right Logical + 32
Doubleword Shift Right Arithmetic + 32
Doubleword Shift Left Logical Variable
Doubleword Shift Right Logical Variable
Doubleword Shift Right Arithmetic Variable

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

MIPS I
I
I
I
I
I
III
III
III
III
III
III
III
III
III

A-7

A 2.2.7 Multiply and Divide
The multiply and divide instructions produce twice as many result bits as is typical
with other processors and they deliver their results into the HI and LO special
registers. Multiply produces a full-width product twice the width of the input
operands; the low half is put in LO and the high half is put in HI. Divide produces
both a quotient in LO and a remainder in HI. The results are accessed by
instructions that transfer data between HI/LO and the general registers.
Table A-11

Multiply/Divide Instructions

Mnemonic

Description

MULT
MULTU
DIV
DIVU

Multiply Word
Multiply Unsigned Word
Divide Word
Divide Unsigned Word

DMULT
DMULTU
DDIV
DDIVU

Doubleword Multiply
Doubleword Multiply Unsigned
Doubleword Divide
Doubleword Divide Unsigned

III
III
III
III

MFHI
MTHI
MFLO
MTLO

Move From HI
Move To HI
Move From LO
Move To LO

I
I
I
I

Defined in

MIPS I
I
I
I

A 2.3 Jump and Branch Instructions
The architecture defines PC-relative conditional branches, a PC-region
unconditional jump, an absolute (register) unconditional jump, and a similar set of
procedure calls that record a return link address in a general register. For
convenience this discussion refers to them all as branches.
All branches have an architectural delay of one instruction. When a branch is
taken, the instruction immediately following the branch instruction, in the branch
delay slot, is executed before the branch to the target instruction takes place.
Conditional branches come in two versions that treat the instruction in the delay
slot differently when the branch is not taken and execution falls through. The
“branch” instructions execute the instruction in the delay slot, but the “branch
likely” instructions do not (they are said to nullify it).
By convention, if an exception or interrupt prevents the completion of an
instruction occupying a branch delay slot, the instruction stream is continued by
re-executing the branch instruction. To permit this, branches must be restartable;
procedure calls may not use the register in which the return link is stored (usually
register 31) to determine the branch target address.

A-8

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Table A-12

Jump Instructions Jumping Within a 256 Megabyte Region

Mnemonic

Description

J
JAL

Jump
Jump and Link

Table A-13

Jump Instructions to Absolute Address

Mnemonic

Description

JR
JALR

Jump Register
Jump and Link Register

Table A-14

PC-Relative Conditional Branch Instructions Comparing 2 Registers

Mnemonic

Description

BEQ
BNE
BLEZ
BGTZ
BEQL
BNEL
BLEZL
BGTZL

Branch on Equal
Branch on Not Equal
Branch on Less Than or Equal to Zero
Branch on Greater Than Zero
Branch on Equal Likely
Branch on Not Equal Likely
Branch on Less Than or Equal to Zero Likely
Branch on Greater Than Zero Likely

Table A-15

PC-Relative Conditional Branch Instructions Comparing Against Zero

Mnemonic

Description

BLTZ
BGEZ
BLTZAL
BGEZAL
BLTZL
BGEZL
BLTZALL
BGEZALL

Branch on Less Than Zero
Branch on Greater Than or Equal to Zero
Branch on Less Than Zero and Link
Branch on Greater Than or Equal to Zero and Link
Branch on Less Than Zero Likely
Branch on Greater Than or Equal to Zero Likely
Branch on Less Than Zero and Link Likely
Branch on Greater Than or Equal to Zero and Link Likely

Defined in

MIPS I
I

Defined in

MIPS I
I

Defined in

MIPS I
I
I
I
II
II
II
II

Defined in

MIPS I
I
I
I
II
II
II
II

A 2.4 Miscellaneous Instructions
A 2.4.1 Exception Instructions
Exception instructions have as their sole purpose causing an exception that will
transfer control to a software exception handler in the kernel. System call and
breakpoint instructions cause exceptions unconditionally. The trap instructions
cause exceptions conditionally based upon the result of a comparison.
Table A-16

System Call and Breakpoint Instructions

Mnemonic

Description

Defined in

SYSCALL
BREAK

System Call
Breakpoint

MIPS I
I

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-9

Table A-17

Trap-on-Condition Instructions Comparing Two Registers

Mnemonic

Description

TGE
TGEU
TLT
TLTU
TEQ
TNE

Trap if Greater Than or Equal
Trap if Greater Than or Equal Unsigned
Trap if Less Than
Trap if Less Than Unsigned
Trap if Equal
Trap if Not Equal

Table A-18

Trap-on-Condition Instructions Comparing an Immediate

Defined in

MIPS II
II
II
II
II
II

Mnemonic

Description

TGEI
TGEIU
TLTI
TLTIU
TEQI
TNEI

Trap if Greater Than or Equal Immediate
Trap if Greater Than or Equal Unsigned Immediate
Trap if Less Than Immediate
Trap if Less Than Unsigned Immediate
Trap if Equal Immediate
Trap if Not Equal Immediate

Defined in

MIPS II
II
II
II
II
II

A 2.4.2 Serialization Instructions
The order in which memory accesses from load and store instruction appear
outside the processor executing them, in a multiprocessor system for example, is
not specified by the architecture. The SYNC instruction creates a point in the
executing instruction stream at which the relative order of some loads and stores
is known. Loads and stores executed before the SYNC are completed before loads
and stores after the SYNC can start.
Table A-19

Serialization Instructions

Mnemonic

Description

SYNC

Synchronize Shared Memory

Defined in

MIPS II

A 2.4.3 Conditional Move Instructions
Instructions were added in MIPS IV to conditionally move one CPU general
register to another based on the value in a third general register.
Table A-20

CPU Conditional Move Instructions

Mnemonic

Description

Defined in

MOVN
MOVZ

Move Conditional on Not Zero
Move Conditional on Zero

MIPS IV
IV

A 2.4.4 Prefetch
There are two prefetch advisory instructions; one with register+offset addressing
and the other with register+register addressing. These instructions advise that
memory is likely to be used in a particular way in the near future and should be
A-10

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

prefetched into the cache. The PREFX instruction using register+register
addressing mode is coded in the FPU opcode space along with the other
operations using register+register addressing.
Table A-21

Prefetch Using Register + Offset Address Mode

Mnemonic

Description

Defined in

PREF

Prefetch Indexed

MIPS IV

Table A-22

Prefetch Using Register + Register Address Mode

Mnemonic

Description

Defined in

PREFX

Prefetch Indexed

MIPS IV

A 2.5 Coprocessor Instructions
Coprocessors are alternate execution units, with register files separate from the
CPU. The MIPS architecture provides an abstraction for up to 4 coprocessor units,
numbered 0 to 3. Each architecture level defines some of these coprocessors as
shown in Table A-23. Coprocessor 0 is always used for system control and
coprocessor 1 is used for the floating-point unit. Other coprocessors are
architecturally valid, but do not have a reserved use. Some coprocessors are not
defined and their opcodes are either reserved or used for other purposes.
Table A-23

Coprocessor Definition and Use in the MIPS Architecture
MIPS architecture level

coprocessor

III

Sys Control

FPU

unused

not defined

FPU (COP 1X)

The coprocessors may have two register sets, coprocessor general registers and
coprocessor control registers, each set containing up to thirty two registers.
Coprocessor computational instructions may alter registers in either set.
System control for all MIPS processors is implemented as coprocessor 0 (CP0), the
System Control Coprocessor. It provides the processor control, memory
management, and exception handling functions. The CP0 instructions are specific
to each CPU and are documented with the CPU-specific information.
If a system includes a floating-point unit, it is implemented as coprocessor 1 (CP1).
In MIPS IV, the FPU also uses the computation opcode space for coprocessor unit
3, renamed COP1X. The FPU instructions are documented in Appendix B.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-11

The coprocessor instructions are divided into two main groups:
•

Load and store instructions that are reserved in the main opcode space.

•

Coprocessor-specific operations that are defined entirely by the
coprocessor.

A 2.5.1 Coprocessor Load and Store
Load and store instructions are not defined for CP0; the move to/from coprocessor
instructions are the only way to write and read the CP0 registers.
The loads and stores for coprocessors are summarized in Load and Store
Instructions on page A-2.
A 2.5.2 Coprocessor Operations
There are up to four coprocessors and the instructions are shown generically for
coprocessor-z. Within the operation main opcode, the coprocessor has further
coprocessor-specific instructions encoded.

Table A-24

Coprocessor Operation Instructions

Mnemonic

Description

COPz

Coprocessor-z Operation

Defined in

MIPS I

Memory Access Types
MIPS systems provide a few memory access types that are characteristic ways to use
physical memory and caches to perform a memory access. The memory access
type is specified as a cache coherence algorithm (CCA) in the TLB entry for a
mapped virtual page. The access type used for a location is associated with the
virtual address, not the physical address or the instruction making the reference.
Implementations without multiprocessor (MP) support provide uncached and
cached accesses. Implementations with MP support provide uncached, cached
noncoherent and cached coherent accesses. The memory access types use the
memory hierarchy as follows:

Uncached
Physical memory is used to resolve the access. Each reference causes a read or
write to physical memory. Caches are neither examined nor modified.
Cached Noncoherent
Physical memory and the caches of the processor performing the access are used
to resolve the access. Other caches are neither examined nor modified.

A-12

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Cached Coherent
Physical memory and all caches in the system containing a coherent copy of the
physical location are used to resolve the access. A copy of a location is coherent
(noncoherent) if the copy was placed in the cache by a cached coherent (cached
noncoherent) access. Caches containing a coherent copy of the location are
examined and/or modified to keep the contents of the location coherent. It is
unpredictable whether caches holding a noncoherent copy of the location are
examined and/or modified during a cached coherent access.

Cached
For early 32-bit processors without MP support, cached is equivalent to cached
noncoherent. If an instruction description mentions the cached noncoherent
access type, the comment applies equally to the cached access type in a processor
that has the cached access type.
For processors with MP support, cached is a collective term, e.g. “cached memory”
or “cached access”, that includes both cached noncoherent and cached coherent.
Such a collective use does not imply that cached is an access type, it means that the
statement applies equally to cached noncoherent and cached coherent access
types.

A 3.1 Mixing References with Different Access Types
It is possible to have more than one virtual location simultaneously mapped to the
same physical location. The memory access type used for the virtual mappings
may be different, but it is not generally possible to use mappings with different
access types at the same time.
A processor executing load and store instructions must observe the effect of the
load and store instructions to a physical location in the order that they occur in the
instruction stream (i.e. program order) for all accesses to virtual locations with the
same memory access type.
If a processor executes a load or store using one access type to a physical location,
the behavior of a subsequent load or store to the same location using a different
memory access type is undefined unless a privileged instruction sequence is
executed between the two accesses. Each implementation has a privileged
implementation-specific mechanism that must be used to change the access type
being used to access a location.
The memory access type of a location affects the behavior of I-fetch, load, store,
and prefetch operations to the location. In addition, memory access types affect
some instruction descriptions. Load linked (LL, LLD) and store conditional (SC,
SCD) have defined operation only for locations with cached memory access type.
SYNC affects only load and stores made to locations with uncached or cached
coherent memory access types.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-13

A 3.2 Cache Coherence Algorithms and Access Types
The memory access types are specified by implementation-specific cache
coherence algorithms (CCAs) in TLB entries. Slightly different cache coherence
algorithms such as “cached coherent, update on write” and “cached coherent,
exclusive on write” can map to the same memory access type, in this case they both
map to cached coherent. In order to map to the same access type the fundamental
mechanism of both CCAs must be the same. When it affects the operation of the
instruction, the instructions are described in terms of the memory access types.
The load and store operations in a processor proceeds according to the specific
CCA of the reference, however, and the pseudocode for load and store common
functions in the section Load and Store Memory Functions
on page A-21 use the
CCA value rather than the corresponding memory access type.

A 3.3 Implementation-Specific Access Types
An implementation may provide memory access types other than uncached,
cached noncoherent, or cached coherent. Implementation-specific documentation
will define the properties of the new access types and their effect on all memoryrelated operations.

A-14

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Description of an Instruction
The CPU instructions are described in alphabetic order. Each description contains
several sections that contain specific information about the instruction. The
content of the section is described in detail below. An example description is
shown in Figure A-1.

Instruction mnemonic
and descriptive name •
Instruction encoding
constant and variable •
field names and values
Architecture level at
which instruction was
defined/redefined and •
assembler format(s)
for each definition
Short description

•

Symbolic description •
Full description of •
instruction operation
Restrictions on
instruction and
operands

•

High-level language
•
description of
instruction operation

Exceptions that
instruction can cause •

Notes for programmers •

Notes for implementors •

Figure A-1

Example Instruction Description

A 4.1 Instruction mnemonic and name
The instruction mnemonic and name are printed as page headings for each page
in the instruction description.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-15

A 4.2 Instruction encoding picture
The instruction word encoding is shown in pictorial form at the top of the
instruction description. This picture shows the values of all constant fields and the
opcode names for opcode fields in upper-case. It labels all variable fields with
lower-case names that are used in the instruction description. Fields that contain
zeroes but are not named are unused fields that are required to be zero. A
summary of the instruction formats and a definition of the terms used to describe
the contents can be found in CPU Instruction Formats
on page A-174.

A 4.3 Format
The assembler formats for the instruction and the architecture level at which the
instruction was originally defined are shown. If the instruction definition was
later extended, the architecture levels at which it was extended and the assembler
formats for the extended definition are shown in order of extension. The MIPS
architecture levels are inclusive; higher architecture levels include all instructions
in previous levels. Extensions to instructions are backwards compatible. The
original assembler formats are valid for the extended architecture.
The assembler format is shown with literal parts of the assembler instruction in
upper-case characters. The variable parts, the operands, are shown as the lowercase names of the appropriate fields in the instruction encoding picture. The
architecture level at which the instruction was first defined, e.g. “MIPS I”, is
shown at the right side of the page.
There can be more than one assembler format per architecture level. This is
sometimes an alternate form of the instruction. Floating-point operations on
formatted data show an assembly format with the actual assembler mnemonic for
each valid value of the “fmt” field. For example the ADD.fmt instruction shows
ADD.S and ADD.D.
The assembler format lines sometimes have comments to the right in parentheses
to help explain variations in the formats. The comments are not a part of the
assembler format.

A 4.4 Purpose
This is a very short statement of the purpose of the instruction.

A 4.5 Description
If a one-line symbolic description of the instruction is feasible, it will appear
immediately to the right of the Description heading. The main purpose is to show
how fields in the instruction are used in the arithmetic or logical operation.
The body of the section is a description of the operation of the instruction in text,
tables, and figures. This description complements the high-level language
description in the Operation section.

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This section uses acronyms for register descriptions. “GPR rt” is CPU General
Purpose Register specified by the instruction field rt. “FPR fs” is the Floating Point
Operand Register specified by the instruction field fs. “CP1 register fd” is the
coprocessor 1 General Register specified by the instruction field fd. “FCSR” is the
floating-point control and status register.

A 4.6 Restrictions
This section documents the restrictions on the instruction. Most restrictions fall
into one of six categories:
•

The valid values for instruction fields (see floating-point ADD.fmt).

•

The alignment requirements for memory addresses (see LW).

•

The valid values of operands (see DADD).

•

The valid operand formats (see floating-point ADD.fmt).

•

The order of instructions necessary to guarantee correct execution. These
ordering constraints avoid pipeline hazards for which some processors do
not have hardware interlocks (see MUL).

•

The valid memory access types (see LL/SC).

A 4.7 Operation
This section describes the operation of the instruction as pseudocode in a highlevel language notation resembling Pascal. The purpose of this section is to
describe the operation of the instruction clearly in a form with less ambiguity than
prose. This formal description complements the Description section; it is not
complete in itself because many of the restrictions are either difficult to include in
the pseudocode or omitted for readability.
There will be separate Operation sections for 32-bit and 64-bit processors if the
operation is different. This is usually necessary because the path to memory is a
different size on these processors.
See Operation Section Notation and Functions
information on the formal notation.

on page A-18 for more

A 4.8 Exceptions
This section lists the exceptions that can be caused by operation of the instruction.
It omits exceptions that can be caused by instruction fetch, e.g. TLB Refill. It omits
exceptions that can be caused by asynchronous external events, e.g. Interrupt.
Although the Bus Error exception may be caused by the operation of a load or store
instruction this section does not list Bus Error for load and store instructions
because the relationship between load and store instructions and external error
indications, like Bus Error, are implementation dependent.

CPU Instruction Set

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A-17

Reserved Instruction is listed for every instruction not in MIPS I because the
instruction will cause this exception on a MIPS I processor. To execute a MIPS II,
MIPS III, or MIPS IV instruction, the processor must both support the architecture
level and have it enabled. The mechanism to do this is implementation specific.
The mechanism used to signal a floating-point unit (FPU) exception is
implementation specific. Some implementations use the exception named
“Floating Point”. Others use external interrupts (the Interrupt exception). This
section lists Floating Point to represent all such mechanisms. The specific FPU
traps possible are listed, indented, under the Floating Point entry.
The usual floating-point exception model for MIPS architecture processors is
precise exceptions. However, the R8000 processor, the first implementation of the
MIPS IV architecture, normally operates with imprecise floating-point exceptions.
It also has a mode in which it operates with degraded floating-point performance
but provides precise exceptions compatible with other MIPS processors. This is
mentioned in the description of some floating-point instructions. A general
description of this exception model is not included in this document. See the
“MIPS R8000 Microprocessor Chip Set Users Manual” for more information.
An instruction may cause implementation-dependent exceptions that are not
present in the Exceptions section.

A 4.9 Programming Notes, Implementation Notes
These sections contain material that is useful for programmers and implementors
respectively but that is not necessary to describe the instruction and does not
belong in the description sections.

Operation Section Notation and Functions
In an instruction description, the Operation section describes the operation
performed by each instruction using a high-level language notation. The contents
of the Operation section are described here. The special symbols and functions
used are documented here.

A 5.1 Pseudocode Language
Each of the high-level language statements is executed in sequential order (as
modified by conditional and loop constructs).

A 5.2 Pseudocode Symbols
Special symbols used in the notation are described in Table A-25.

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Table A-25

Symbols in Instruction Operation Statements

Symbol

Meaning

←

Assignment.

=, ≠

Tests for equality and inequality.

Bit string concatenation.

A y-bit string formed by y copies of the single-bit value x.

xy..z

Selection of bits y through z of bit string x. Little-endian bit notation (rightmost bit
is 0) is used. If y is less than z, this expression is an empty (zero length) bit string.

+, -

2’s complement or floating-point arithmetic: addition, subtraction.

*, ×

2’s complement or floating-point multiplication (both used for either).

div

2’s complement integer division.

mod

2’s complement modulo.

Floating-point division.

2’s complement less than comparison.

nor

Bit-wise logical NOR.

xor

Bit-wise logical XOR.

and

Bit-wise logical AND.

Bit-wise logical OR.

GPRLEN

The length in bits (32 or 64), of the CPU General Purpose Registers.

GPR[x]

CPU General Purpose Register x. The content of GPR[0] is always zero.

FPR[x]

Floating-Point operand register x.

FCC[cc]

Floating-Point condition code cc. FCC[0] has the same value as COC[1].

FGR[x]

Floating-Point (Coprocessor unit1), general register x.

CPR[z,x]

Coprocessor unit z, general register x.

CCR[z,x]

Coprocessor unit z, control register x.

COC[z]

Coprocessor unit z condition signal.

BigEndianMem

Endian mode as configured at chip reset (0 →Little, 1 → Big). Specifies the
endianness of the memory interface (see LoadMemory and StoreMemory), and the
endianness of Kernel and Supervisor mode execution.

ReverseEndian

Signal to reverse the endianness of load and store instructions. This feature is
available in User mode only, and is effected by setting the RE bit of the Status
register. Thus, ReverseEndian may be computed as (SRRE and User mode).

BigEndianCPU

The endianness for load and store instructions (0 → Little, 1 → Big). In User mode,
this endianness may be switched by setting the RE bit in the Status Register. Thus,
BigEndianCPU may be computed as (BigEndianMem XOR ReverseEndian).

LLbit

Bit of virtual
state used to specify operation for instructions that provide atomic
read-modify-write. It is set when a linked load occurs. It is tested and cleared by
the conditional store. It is cleared, during other CPU operation, when a store to the
location would no longer be atomic. In particular, it is cleared by exception return
instructions.

CPU Instruction Set

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A-19

Symbol

I :,
I +n :,
I -n :

Meaning
This occurs as a prefix to operation description lines and functions as a label. It
indicates the instruction time during which the effects of the pseudocode lines
appears to occur (i.e. when the pseudocode is “executed”). Unless otherwise
indicated, all effects of the current instruction appear to occur during the instruction
time of the current instruction. No label is equivalent to a time label of “I :”.
Sometimes effects of an instruction appear to occur either earlier or later – during
the instruction time of another instruction. When that happens, the instruction
operation is written in sections labelled with the instruction time, relative to the
current instruction I, in which the effect of that pseudocode appears to occur. For
example, an instruction may have a result that is not available until after the next
instruction. Such an instruction will have the portion of the instruction operation
description that writes the result register in a section labelled “I +1:”.
The effect of pseudocode statements for the current instruction labelled
“I +1:”appears to occur “at the same time” as the effect of pseudocode statements
labelled “I :” for the following instruction. Within one pseudocode sequence the
effects of the statements takes place in order. However, between sequences of
statements for different instructions that occur “at the same time”, there is no order
defined. Programs must not depend on a particular order of evaluation between
such sections.

PSIZE

The Program Counter value. During the instruction time of an instruction this is the
address of the instruction word. The address of the instruction that occurs during
the next instruction time is determined by assigning a value to PC during an
instruction time. If no value is assigned to PC during an instruction time by any
pseudocode statement, it is automatically incremented by 4 before the next
instruction time. A taken branch assigns the target address to PC during the
instruction time of the instruction in the branch delay slot.
The SIZE, number of bits, of Physical address in an implementation.

A 5.3 Pseudocode Functions
There are several functions used in the pseudocode descriptions. These are used
either to make the pseudocode more readable, to abstract implementation specific
behavior, or both. The functions are defined in this section.
A 5.3.1 Coprocessor General Register Access Functions
Defined coprocessors, except for CP0, have instructions to exchange words and
doublewords between coprocessor general registers and the rest of the system.
What a coprocessor does with a word or doubleword supplied to it and how a
coprocessor supplies a word or doubleword is defined by the coprocessor itself.
This behavior is abstracted into functions:

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Table A-26

Coprocessor General Register Access Functions

COP_LW (z, rt, memword)
z:
The coprocessor unit number.
rt:
Coprocessor general register specifier.
memword:
A 32-bit word value supplied to the coprocessor.
This is the action taken by coprocessor z when supplied with a word from
memory during a load word operation. The action is coprocessor specific. The
typical action would be to store the contents of memword in coprocessor general
register rt.
COP_LD (z, rt, memdouble)
z:
The coprocessor unit number.
rt:
Coprocessor general register specifier.
memdouble: 64-bit doubleword value supplied to the coprocessor.
This is the action taken by coprocessor z when supplied with a doubleword from
memory during a load doubleword operation. The action is coprocessor specific.
The typical action would be to store the contents of memdouble in coprocessor
general register rt.
dataword ← COP_SW (z, rt)
z:
The coprocessor unit number.
rt:
Coprocessor general register specifier.
dataword:
32-bit word value.
This defines the action taken by coprocessor z to supply a word of data during a
store word operation. The action is coprocessor specific. The typical action
would be to supply the contents of the low-order word in coprocessor general
register rt.
datadouble ← COP_SD (z, rt)
z:
The coprocessor unit number.
rt:
Coprocessor general register specifier.
datadouble: 64-bit doubleword value.
This defines the action taken by coprocessor z to supply a doubleword of data
during a store doubleword operation. The action is coprocessor specific. The
typical action would be to supply the contents of the doubleword in coprocessor
general register rt.
A 5.3.2 Load and Store Memory Functions
Regardless of byte ordering (big- or little-endian), the address of a halfword, word,
or doubleword is the smallest byte address among the bytes forming the object.
For big-endian ordering this is the most-significant byte; for a little-endian
ordering this is the least-significant byte.
In the operation description pseudocode for load and store operations, the
functions shown below are used to summarize the handling of virtual addresses
and accessing physical memory. The size of the data item to be loaded or stored is
passed in the AccessLength field. The valid constant names and values are shown
in Table A-27. The bytes within the addressed unit of memory (word for 32-bit
processors or doubleword for 64-bit processors) which are used can be determined
directly from the AccessLength and the two or three low-order bits of the address.
CPU Instruction Set

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A-21

(pAddr, CCA) ←AddressTranslation (vAddr, IorD, LorS)
pAddr:
Physical Address.
CCA:
Cache Coherence Algorithm: the method used to access
caches and memory and resolve the reference.
vAddr:
Virtual Address.
IorD:
Indicates whether access is for INSTRUCTION or DATA.
LorS:
Indicates whether access is for LOAD or STORE.
Translate a virtual address to a physical address and a cache coherence
algorithm describing the mechanism used to resolve the memory reference.
Given the virtual address vAddr, and whether the reference is to Instructions or
Data (IorD), find the corresponding physical address (pAddr) and the cache
coherence algorithm (CCA) used to resolve the reference. If the virtual address
is in one of the unmapped address spaces the physical address and CCA are
determined directly by the virtual address. If the virtual address is in one of the
mapped address spaces then the TLB is used to determine the physical address
and access type; if the required translation is not present in the TLB or the
desired access is not permitted the function fails and an exception is taken.

MemElem ← LoadMemory (CCA, AccessLength, pAddr, vAddr, IorD)
MemElem:
Data is returned in a fixed width with a natural
alignment. The width is the same size as the CPU general
purpose register, 32 or 64 bits, aligned on a 32 or 64-bit
boundary respectively.
CCA:
Cache Coherence Algorithm: the method used to access
caches and memory and resolve the reference.
AccessLength: Length, in bytes, of access.
pAddr:
Physical Address.
vAddr:
Virtual Address.
IorD:
Indicates whether access is for Instructions or Data.
Load a value from memory.
Uses the cache and main memory as specified in the Cache Coherence Algorithm
(CCA) and the sort of access (IorD) to find the contents of AccessLength memory
bytes starting at physical location pAddr. The data is returned in the fixed width
naturally-aligned memory element (MemElem). The low-order two (or three)
bits of the address and the AccessLength indicate which of the bytes within
MemElem needs to be given to the processor. If the memory access type of the
reference is uncached then only the referenced bytes are read from memory and
valid within the memory element. If the access type is cached, and the data is not
present in cache, an implementation specific size and alignment block of
memory is read and loaded into the cache to satisfy a load reference. At a
minimum, the block is the entire memory element.

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StoreMemory (CCA, AccessLength, MemElem, pAddr, vAddr)
CCA:
Cache Coherence Algorithm: the method used to access
caches and memory and resolve the reference.
AccessLength: Length, in bytes, of access.
MemElem:
Data in the width and alignment of a memory element.
The width is the same size as the CPU general purpose
register, 4 or 8 bytes, aligned on a 4 or 8-byte boundary.
For a partial-memory-element store, only the bytes that
will be stored must be valid.
pAddr:
Physical Address.
vAddr:
Virtual Address.
Store a value to memory.
The specified data is stored into the physical location pAddr using the memory
hierarchy (data caches and main memory) as specified by the Cache Coherence
Algorithm (CCA). The MemElem contains the data for an aligned, fixed-width
memory element (word for 32-bit processors, doubleword for 64-bit processors),
though only the bytes that will actually be stored to memory need to be valid.
The low-order two (or three) bits of pAddr and the AccessLength field indicates
which of the bytes within the MemElem data should actually be stored; only these
bytes in memory will be changed.

Prefetch (CCA, pAddr, vAddr, DATA, hint)
CCA:
Cache Coherence Algorithm: the method used to access
caches and memory and resolve the reference.
pAddr:
physical Address.
vAddr:
Virtual Address.
DATA:
Indicates that access is for DATA.
hint:
hint that indicates the possible use of the data.
Prefetch data from memory.
Prefetch is an advisory instruction for which an implementation specific action
is taken. The action taken may increase performance but must not change the
meaning of the program or alter architecturally-visible state.

CPU Instruction Set

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A-23

Table A-27

AccessLength Specifications for Loads/Stores

AccessLength Name

Value

Meaning

DOUBLEWORD

8 bytes (64 bits)

SEPTIBYTE

7 bytes (56 bits)

SEXTIBYTE

6 bytes (48 bits)

QUINTIBYTE

5 bytes (40 bits)

WORD

4 bytes (32 bits)

TRIPLEBYTE

3 bytes (24 bits)

HALFWORD

2 bytes (16 bits)

BYTE

1 byte (8 bits)

A 5.3.3 Access Functions for Floating-Point Registers
The details of the relationship between CP1 general registers and floating-point
operand registers is encapsulated in the functions included in this section. See
Valid Operands for FP Instructions
on page B-24 for more information.
This function returns the current logical width, in bits, of the CP1 general registers.
All 32-bit processors will return “32”. 64-bit processors will return “32” when in
32-bit-CP1-register emulation mode and “64” when in native 64-bit mode.
The following pseudocode referring to the StatusFR bit is valid for all existing
MIPS 64-bit processors at the time of this writing, however this is a privileged
processor-specific mechanism and it may be different in some future
processor.
SizeFGR() -- current size, in bits, of the CP1 general registers
size ←SizeFGR()
if 32_bit_processor then
size ← 32
else
/* 64-bit processor */
if StatusFR = 1 then
size ← 64
else
size ← 32
endif
endif

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MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

This pseudocode specifies how the unformatted contents loaded or moved-to CP1
registers are interpreted to form a formatted value. If an FPR contains a value in
some format, rather than unformatted contents from a load (uninterpreted), it is
valid to interpret the value in that format, but not to interpret it in a different
format.
ValueFPR() -- Get a formatted value from an FPR.
value ←ValueFPR (fpr, fmt)
/* get a formatted value from an FPR */
if SizeFGR() = 64 then
case fmt of
S, W:
value ← FGR[fpr]31..0
D, L:
value ← FGR[fpr]
endcase
elseif fpr0 = 0 then
/* fpr is valid (even), 32-bit wide FGRs */
case fmt of
S, W:
value ← FGR[fpr]
D, L:
value ← FGR[fpr+1] || FGR[fpr]
endcase
else
/* undefined for odd 32-bit FGRs */
UndefinedResult
endif

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-25

This pseudocode specifies the way that a binary encoding representing a
formatted value is stored into CP1 registers by a computational or move operation.
This binary representation is visible to store or move-from instructions. Once an
FPR contains a value via StoreFPR(), it is not valid to interpret the value with
ValueFPR() in a different format.
StoreFPR() -- store a formatted value into an FPR.
StoreFPR(fpr, fmt, value):
/* place a formatted value into an FPR */
if SizeFGR() = 64 then /* 64-bit wide FGRs */
case fmt of
S, W:
FGR[fpr] ← undefined32 || value
D, L:
FGR[fpr] ← value
endcase
elseif fpr0 = 0 then
/* fpr is valid (even), 32-bit wide FGRs */
case fmt of
S, W:
FGR[fpr+1] ← undefined32
FGR[fpr] ← value
D, L:
FGR[fpr+1] ← value63..32
FGR[fpr] ← value31..0
endcase
else
/* undefined for odd 32-bit FGRs */
UndefinedResult
endif

A 5.3.4 Miscellaneous Functions

SyncOperation(stype)
stype:
Type of load/store ordering to perform.
order loads and stores to synchronize shared memory.
Perform the action necessary to make the effects of groups synchronizable loads
and stores indicated by stype occur in the same order for all processors.
SignalException(Exception)
Exception
The exception condition that exists.
Signal an exception condition.
This will result in an exception that aborts the instruction. The instruction
operation pseudocode will never see a return from this function call.
UndefinedResult()
This function indicates that the result of the operation is undefined.

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MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

NullifyCurrentInstruction()
Nullify the current instruction.
This occurs during the instruction time for some instruction and that instruction
is not executed further. This appears for branch-likely instructions during the
execution of the instruction in the delay slot and it kills the instruction in the
delay slot.
CoprocessorOperation (z, cop_fun)
z
Coprocessor unit number
cop_fun
Coprocessor function from function field of instruction
Perform the specified Coprocessor operation.

Individual CPU Instruction Descriptions
The user-mode CPU instructions are described in alphabetic order. See
Description of an Instruction
on page A-15 for a description of the information
in each instruction description.

CPU Instruction Set

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A-27

ADD
31

Add Word
26 25

SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

ADD rd, rs, rt

Description:

rd ← rs + rt

0
00000
5

0
ADD
100000
6

MIPS I

To add 32-bit integers. If overflow occurs, then trap.

The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a
32-bit result. If the addition results in 32-bit 2’s complement arithmetic overflow then
the destination register is not modified and an Integer Overflow exception occurs. If it
does not overflow, the 32-bit result is placed into GPR rd.

Restrictions:
On 64-bit processors, if either GPR rt or GPR rs do not contain sign-extended 32-bit
values (bits 63..31 equal), then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
temp ←GPR[rs] + GPR[rt]
if (32_bit_arithmetic_overflow) then
SignalException(IntegerOverflow)
else
GPR[rd] ←sign_extend(temp31..0)
endif

Exceptions:
Integer Overflow

Programming Notes:
ADDU performs the same arithmetic operation but, does not trap on overflow.

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CPU Instruction Set

Add Immediate Word
31

26 25
ADDI
001000
6

ADDI
21 20

16 15

immediate

Format:
Purpose:

ADDI rt, rs, immediate

Description:

rt ← rs + immediate

MIPS I

To add a constant to a 32-bit integer. If overflow occurs, then trap.

The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit
result. If the addition results in 32-bit 2’s complement arithmetic overflow then the
destination register is not modified and an Integer Overflow exception occurs. If it
does not overflow, the 32-bit result is placed into GPR rt.

Restrictions:
On 64-bit processors, if GPR rs does not contain a sign-extended 32-bit value
(bits 63..31 equal), then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rs])) then UndefinedResult() endif
temp ←GPR[rs] + sign_extend(immediate)
if (32_bit_arithmetic_overflow) then
SignalException(IntegerOverflow)
else
GPR[rt] ←sign_extend(temp31..0)
endif

Exceptions:
Integer Overflow

Programming Notes:
ADDIU performs the same arithmetic operation but, does not trap on overflow.

CPU Instruction Set

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A-29

ADDIU
31

Add Immediate Unsigned Word

26 25
ADDIU
001001
6

21 20

16 15

immediate

Format:
Purpose:

ADDIU rt, rs, immediate

Description:

rt ← rs + immediate

MIPS I

To add a constant to a 32-bit integer.

The 16-bit signed immediate is added to the 32-bit value in GPR rs and the 32-bit
arithmetic result is placed into GPR rt.
No Integer Overflow exception occurs under any circumstances.

Restrictions:
On 64-bit processors, if GPR rs does not contain a sign-extended 32-bit value
(bits 63..31 equal), then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rs])) then UndefinedResult() endif
temp ←GPR[rs] + sign_extend(immediate)
GPR[rt] ← sign_extend(temp31..0)

Exceptions:
None

Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit
modulo arithmetic that does not trap on overflow. It is appropriate for arithmetic
which is not signed, such as address arithmetic, or integer arithmetic environments
that ignore overflow, such as “C” language arithmetic.

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ADDU

Add Unsigned Word
31

26 25
SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

ADDU rd, rs, rt

Description:

rd ← rs + rt

0
00000
5

0
ADDU
100001
6

MIPS I

To add 32-bit integers.

The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit
arithmetic result is placed into GPR rd.
No Integer Overflow exception occurs under any circumstances.

Restrictions:
On 64-bit processors, if either GPR rt or GPR rs do not contain sign-extended 32-bit
values (bits 63..31 equal), then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
temp ←GPR[rs] + GPR[rt]
GPR[rd]← sign_extend(temp31..0)

Exceptions:
None

CPU Instruction Set

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A-31

AND
31

And
26 25

SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

AND rd, rs, rt

Description:

rd ← rs AND rt

0
00000
5

0
AND
100100
6

MIPS I

To do a bitwise logical AND.

The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical
AND operation. The result is placed into GPR rd.

Restrictions:
None

Operation:
GPR[rd] ← GPR[rs] and GPR[rt]

Exceptions:
None

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ANDI

And Immediate
31

26 25
ANDI
001100
6

21 20

16 15

immediate

Format:
Purpose:

ANDI rt, rs, immediate

Description:

rt ← rs AND immediate

MIPS I

To do a bitwise logical AND with a constant.

The 16-bit immediate is zero-extended to the left and combined with the contents of
GPR rs in a bitwise logical AND operation. The result is placed into GPR rt.

Restrictions:
None

Operation:
GPR[rt] ← zero_extend(immediate) and GPR[rs]

Exceptions:
None

CPU Instruction Set

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A-33

BEQ
31

Branch on Equal
26 25

BEQ
000100
6

21 20

16 15

offset

Format:
Purpose:

BEQ rs, rt, offset

Description:

if (rs = rt) then branch

MIPS I

To compare GPRs then do a PC-relative conditional branch.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← (GPR[rs] = GPR[rt])
I + 1 :if condition then
PC ← PC + tgt_offset
endif
I:

Exceptions:
None

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

A-34

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

BEQL

Branch on Equal Likely
31

26 25
BEQL
010100
6

21 20

16 15

offset

Format:
Purpose:

BEQL rs, rt, offset

Description:

if (rs = rt) then branch_likely

MIPS II

To compare GPRs then do a PC-relative conditional branch; execute the
delay slot only if the branch is taken.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← (GPR[rs] = GPR[rt])
I + 1 :if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction()
endif
I:

Exceptions:
Reserved Instruction

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-35

BGEZ
31

Branch on Greater Than or Equal to Zero
26 25

REGIMM
000001
6

21 20
rs
5

16 15

BGEZ
00001
5

Format:
Purpose:

BGEZ rs, offset

Description:

if (rs ≥ 0) then branch

0
offset
16

MIPS I

To test a GPR then do a PC-relative conditional branch.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] ≥ 0GPRLEN
I + 1 :if condition then
PC ← PC + tgt_offset
endif
I:

Exceptions:
None

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

A-36

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

BGEZAL

Branch on Greater Than or Equal to Zero and Link
31

26 25
REGIMM
000001
6

21 20
rs
5

16 15

BGEZAL
10001
5

Format:
Purpose:

BGEZAL rs, offset

Description:

if (rs ≥ 0) then procedure_call

0
offset
16

MIPS I

To test a GPR then do a PC-relative conditional procedure call.

Place the return address link in GPR 31. The return link is the address of the second
instruction following the branch, where execution would continue after a procedure
call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch (not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the
effective target address after the instruction in the delay slot is executed.

Restrictions:
GPR 31 must not be used for the source register rs, because such an instruction does
not have the same effect when re-executed. The result of executing such an instruction
is undefined. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] ≥ 0GPRLEN
GPR[31] ← PC + 8
I + 1 :if condition then
PC ← PC + tgt_offset
endif
I:

Exceptions:
None

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump and link (JAL) or jump and link register (JALR) instructions for procedure
calls to more distant addresses.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-37

BGEZALL Branch on Greater Than or Equal to Zero and Link Likely
31

26 25
REGIMM
000001
6

21 20
rs
5

16 15

BGEZALL
10011
5

Format:
Purpose:

BGEZALL rs, offset

Description:

if (rs ≥ 0) then procedure_call_likely

0
offset
16

MIPS II

To test a GPR then do a PC-relative conditional procedure call; execute the
delay slot only if the branch is taken.

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] ≥ 0GPRLEN
GPR[31] ← PC + 8
I + 1 :if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction()
endif
I:

Exceptions:
Reserved Instruction

A-38

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

BGEZL

Branch on Greater Than or Equal to Zero Likely
31

26 25

REGIMM
000001
6

21 20
rs
5

16 15

BGEZL
00011
5

Format:
Purpose:

BGEZL rs, offset

Description:

if (rs ≥ 0) then branch_likely

0
offset
16

MIPS II

To test a GPR then do a PC-relative conditional branch; execute the delay
slot only if the branch is taken.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] ≥ 0GPRLEN
I + 1 :if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction()
endif
I:

Exceptions:
Reserved Instruction

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-39

BGTZ
31

Branch on Greater Than Zero
26 25

BGTZ
000111
6

21 20
rs
5

16 15

0
00000
5

Format:
Purpose:

BGTZ rs, offset

Description:

if (rs > 0) then branch

0
offset
16

MIPS I

To test a GPR then do a PC-relative conditional branch.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch (not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch
to the effective target address after the instruction in the delay slot is executed.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] > 0GPRLEN
I + 1 : if condition then
PC ← PC + tgt_offset
endif
I:

Exceptions:
None

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

A-40

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

BGTZL

Branch on Greater Than Zero Likely
31

26 25
BGTZL
010111
6

21 20
rs
5

16 15

0
00000
5

Format:
Purpose:

BGTZL rs, offset

Description:

if (rs > 0) then branch_likely

0
offset
16

MIPS II

To test a GPR then do a PC-relative conditional branch; execute the delay
slot only if the branch is taken.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch (not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch
to the effective target address after the instruction in the delay slot is executed. If the
branch is not taken, the instruction in the delay slot is not executed.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] > 0GPRLEN
I + 1 :if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction()
endif
I:

Exceptions:
Reserved Instruction

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-41

BLEZ
31

Branch on Less Than or Equal to Zero
26 25

BLEZ
000110
6

21 20
rs
5

16 15

0
00000
5

Format:
Purpose:

BLEZ rs, offset

Description:

if (rs ≤ 0) then branch

0
offset
16

MIPS I

To test a GPR then do a PC-relative conditional branch.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch (not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero),
branch to the effective target address after the instruction in the delay slot is executed.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] ≤ 0GPRLEN
I + 1 :if condition then
PC ← PC + tgt_offset
I:

endif

Exceptions:
None

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

A-42

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

BLEZL

Branch on Less Than or Equal to Zero Likely
31

26 25
BLEZL
010110
6

21 20
rs
5

16 15

0
00000
5

Format:
Purpose:

BLEZL rs, offset

Description:

if (rs ≤ 0) then branch_likely

0
offset
16

MIPS II

To test a GPR then do a PC-relative conditional branch; execute the delay
slot only if the branch is taken.

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch (not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero),
branch to the effective target address after the instruction in the delay slot is executed.
If the branch is not taken, the instruction in the delay slot is not executed.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] ≤ 0GPRLEN
I + 1 :if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction()
endif
I:

Exceptions:
Reserved Instruction

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-43

BLTZ
31

Branch on Less Than Zero
26 25

REGIMM
000001
6

21 20
rs
5

16 15

BLTZ
00000
5

Format:
Purpose:

BLTZ rs, offset

Description:

if (rs < 0) then branch

0
offset
16

MIPS I

To test a GPR then do a PC-relative conditional branch.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] < 0GPRLEN
I + 1 :if condition then
PC ← PC + tgt_offset
endif
I:

Exceptions:
None

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

A-44

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

BLTZAL

Branch on Less Than Zero And Link
31

26 25
REGIMM
000001
6

21 20
rs
5

16 15

BLTZAL
10000
5

Format:
Purpose:

BLTZAL rs, offset

Description:

if (rs < 0) then procedure_call

0
offset
16

MIPS I

To test a GPR then do a PC-relative conditional procedure call.

Place the return address link in GPR 31. The return link is the address of the second
instruction following the branch (not the branch itself), where execution would
continue after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch, in the branch delay slot, to form a PC-relative
effective target address.
If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target
address after the instruction in the delay slot is executed.

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] < 0GPRLEN
GPR[31] ← PC + 8
I + 1 :if condition then
PC ← PC + tgt_offset
endif
I:

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-45

BLTZALL
31

Branch on Less Than Zero And Link Likely

26 25

REGIMM
000001
6

21 20
rs
5

16 15

BLTZALL
10010
5

Format:
Purpose:

BLTZALL rs, offset

Description:

if (rs < 0) then procedure_call_likely

0
offset
16

MIPS II

To test a GPR then do a PC-relative conditional procedure call; execute the
delay slot only if the branch is taken.

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] < 0GPRLEN
GPR[31] ← PC + 8
I + 1 :if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction()
endif
I:

Exceptions:
Reserved Instruction

A-46

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

BLTZL

Branch on Less Than Zero Likely
31

26 25
REGIMM
000001
6

21 20
rs
5

16 15

BLTZL
00010
5

Format:
Purpose:

BLTZ rs, offset

Description:

if (rs < 0) then branch_likely

0
offset
16

MIPS II

To test a GPR then do a PC-relative conditional branch; execute the delay
slot only if the branch is taken.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] < 0GPRLEN
I + 1 :if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction()
endif
I:

Exceptions:
Reserved Instruction

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-47

BNE
31

Branch on Not Equal
26 25

BNE
000101
6

21 20

16 15

offset

Format:
Purpose:

BNE rs, rt, offset

Description:

if (rs ≠ rt) then branch

MIPS I

To compare GPRs then do a PC-relative conditional branch.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← (GPR[rs] ≠ GPR[rt])
I + 1 :if condition then
PC ← PC + tgt_offset
endif
I:

Exceptions:
None

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

A-48

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

BNEL

Branch on Not Equal Likely
31

26 25
BNEL
010101
6

21 20

16 15

offset

Format:
Purpose:

BNEL rs, rt, offset

Description:

if (rs ≠ rt) then branch_likely

MIPS II

To compare GPRs then do a PC-relative conditional branch; execute the
delay slot only if the branch is taken.

Restrictions:
None

Operation:
tgt_offset ← sign_extend(offset || 02)
condition ← (GPR[rs] ≠ GPR[rt])
I + 1 :if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction()
endif
I:

Exceptions:
Reserved Instruction

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-49

BREAK

Breakpoint

65
code

SPECIAL
000000
6

Format:
Purpose:

0
BREAK
001101
6

MIPS I

BREAK
To cause a Breakpoint exception.

Description:
A breakpoint exception occurs, immediately and unconditionally transferring control
to the exception handler.
The code field is available for use as software parameters, but is retrieved by the
exception handler only by loading the contents of the memory word containing the
instruction.

Restrictions:
None

Operation:
SignalException(Breakpoint)

Exceptions:
Breakpoint

A-50

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

COPz

Coprocessor Operation
31

26 25

COPz
0100zz
6

cop_fun
26

Format:

COP0
COP1
COP2
COP3

Purpose:

To execute a coprocessor instruction.

cop_fun
cop_fun
cop_fun
cop_fun

MIPS I

Description:
The coprocessor operation specified by cop_fun is performed by coprocessor unit zz.
Details of coprocessor operations must be found in the specification for each
coprocessor.
Each MIPS architecture level defines up to 4 coprocessor units, numbered 0 to 3 (see
Coprocessor Instructions
on page A-11). The opcodes corresponding to coprocessors
that are not defined by an architecture level may be used for other instructions.

Operation:
CoprocessorOperation (z, cop_fun)

Exceptions:
Reserved Instruction
Coprocessor Unusable
Coprocessor interrupt or Floating-Point Exception (CP1 only for some processors)

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-51

DADD
31

Doubleword Add

26 25
SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

DADD rd, rs, rt

Description:

rd ← rs + rt

0
00000
5

0
DADD
101100
6

MIPS III

To add 64-bit integers. If overflow occurs, then trap.

The 64-bit doubleword value in GPR rt is added to the 64-bit value in GPR rs to
produce a 64-bit result. If the addition results in 64-bit 2’s complement arithmetic
overflow then the destination register is not modified and an Integer Overflow
exception occurs. If it does not overflow, the 64-bit result is placed into GPR rd.

Restrictions:
None

Operation:

64- bit processors

temp ← GPR[rs] + GPR[rt]
if (64_bit_arithmetic_overflow) then
SignalException(IntegerOverflow)
else
GPR[rd] ← temp
endif

Exceptions:
Integer Overflow
Reserved Instruction

Programming Notes:
DADDU performs the same arithmetic operation but, does not trap on overflow.

A-52

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

DADDI

Doubleword Add Immediate
31

26 25
DADDI
011000
6

21 20

16 15

immediate

Format:
Purpose:

DADDI rt, rs, immediate

Description:

rt ← rs + immediate

MIPS III

To add a constant to a 64-bit integer. If overflow occurs, then trap.

The 16-bit signed immediate is added to the 64-bit value in GPR rs to produce a 64-bit
result. If the addition results in 64-bit 2’s complement arithmetic overflow then the
destination register is not modified and an Integer Overflow exception occurs. If it
does not overflow, the 64-bit result is placed into GPR rt.

Restrictions:
None

Operation:

64- bit processors

temp ← GPR[rs] + sign_extend(immediate)
if (64_bit_arithmetic_overflow) then
SignalException(IntegerOverflow)
else
GPR[rt] ← temp
endif

Exceptions:
Integer Overflow
Reserved Instruction

Programming Notes:
DADDIU performs the same arithmetic operation but, does not trap on overflow.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-53

DADDIU
31

Doubleword Add Immediate Unsigned

26 25
DADDIU
011001
6

21 20

16 15

immediate

Format:
Purpose:

DADDIU rt, rs, immediate

Description:

rt ← rs + immediate

MIPS III

To add a constant to a 64-bit integer.

The 16-bit signed immediate is added to the 64-bit value in GPR rs and the 64-bit
arithmetic result is placed into GPR rt.
No Integer Overflow exception occurs under any circumstances.

Restrictions:
None

Operation:

64- bit processors

GPR[rt] ← GPR[rs] + sign_extend(immediate)

Exceptions:
Reserved Instruction

Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 64-bit
modulo arithmetic that does not trap on overflow. It is appropriate for arithmetic
which is not signed, such as address arithmetic, or integer arithmetic environments
that ignore overflow, such as “C” language arithmetic.

A-54

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

DADDU

Doubleword Add Unsigned
31

26 25
SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

DADDU rd, rs, rt

Description:

rd ← rs + rt

0
00000
5

0
DADDU
101101
6

MIPS III

To add 64-bit integers.

The 64-bit doubleword value in GPR rt is added to the 64-bit value in GPR rs and the
64-bit arithmetic result is placed into GPR rd.
No Integer Overflow exception occurs under any circumstances.

Restrictions:
None

Operation:

64- bit processors

GPR[rd] ←GPR[rs] + GPR[rt]

Exceptions:
Reserved Instruction

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-55

DDIV
31

Doubleword Divide
26 25

SPECIAL
000000
6

21 20

16 15

0
00 0000 0000
10

0
DDIV
011110
6

MIPS III

Format:
Purpose:

DDIV rs, rt

Description:

(LO, HI) ← rs / rt

To divide 64-bit signed integers.

The 64-bit doubleword in GPR rs is divided by the 64-bit doubleword in GPR rt,
treating both operands as signed values. The 64-bit quotient is placed into special
register LO and the 64-bit remainder is placed into special register HI.
No arithmetic exception occurs under any circumstances.

Restrictions:
If either of the two preceding instructions is MFHI or MFLO, the result of the MFHI or
MFLO is undefined. Reads of the HI or LO special registers must be separated from
subsequent instructions that write to them by two or more other instructions.
If the divisor in GPR rt is zero, the arithmetic result value is undefined.

Operation:
I - 2 :, I - 1 :
I:

64- bit processors
LO, HI ← undefined
LO
← GPR[rs] div GPR[rt]
HI
← GPR[rs] mod GPR[rt]

Exceptions:
Reserved Instruction

Programming Notes:
See the Programming Notes for the DIV instruction.

A-56

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

DDIVU

Doubleword Divide Unsigned
31

26 25
SPECIAL
000000
6

21 20

16 15

6
0
000000 0000
10

0
DDIVU
011111
6

MIPS III

Format:
Purpose:

DDIVU rs, rt

Description:

(LO, HI) ← rs / rt

To divide 64-bit unsigned integers.

The 64-bit doubleword in GPR rs is divided by the 64-bit doubleword in GPR rt,
treating both operands as unsigned values. The 64-bit quotient is placed into special
register LO and the 64-bit remainder is placed into special register HI.
No arithmetic exception occurs under any circumstances.

Operation:
I - 2 :, I - 1 :
I:

64- bit processors
LO, HI ← undefined
LO
← (0 || GPR[rs]) div (0 || GPR[rt])
HI
← (0 || GPR[rs]) mod (0 || GPR[rt])

Exceptions:
Reserved instruction

Programming Notes:
See the Programming Notes for the DIV instruction.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-57

DIV
31

Divide Word
26 25

SPECIAL
000000
6

21 20

16 15

0
00 0000 0000
10

0
DIV
011010
6

MIPS I

Format:
Purpose:

DIV rs, rt

Description:

(LO, HI) ← rs / rt

To divide 32-bit signed integers.

The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both
operands as signed values. The 32-bit quotient is placed into special register LO and
the 32-bit remainder is placed into special register HI.
No arithmetic exception occurs under any circumstances.

Restrictions:
On 64-bit processors, if either GPR rt or GPR rs do not contain sign-extended 32-bit
values (bits 63..31 equal), then the result of the operation is undefined.
If either of the two preceding instructions is MFHI or MFLO, the result of the MFHI or
MFLO is undefined. Reads of the HI or LO special registers must be separated from
subsequent instructions that write to them by two or more other instructions.
If the divisor in GPR rt is zero, the arithmetic result value is undefined.

Operation:
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
I - 2 :, I - 1 :
LO, HI ← undefined
I:
q
← GPR[rs]31..0 div GPR[rt]31..0
LO
← sign_extend(q31..0)
r
← GPR[rs]31..0 mod GPR[rt]31..0
HI
← sign_extend(r31..0)

Exceptions:
None

Programming Notes:
In some processors the integer divide operation may proceed asynchronously and
allow other CPU instructions to execute before it is complete. An attempt to read LO
or HI before the results are written will wait (interlock) until the results are ready.
Asynchronous execution does not affect the program result, but offers an opportunity
for performance improvement by scheduling the divide so that other instructions can
execute in parallel.

A-58

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

DIV

Divide Word

No arithmetic exception occurs under any circumstances. If divide-by-zero or
overflow conditions should be detected and some action taken, then the divide
instruction is typically followed by additional instructions to check for a zero divisor
and/or for overflow. If the divide is asynchronous then the zero-divisor check can
execute in parallel with the divide. The action taken on either divide-by-zero or
overflow is either a convention within the program itself or more typically, the system
software; one possibility is to take a BREAK exception with a code field value to signal
the problem to the system software.
As an example, the C programming language in a UNIX environment expects division
by zero to either terminate the program or execute a program-specified signal handler.
C does not expect overflow to cause any exceptional condition. If the C compiler uses
a divide instruction, it also emits code to test for a zero divisor and execute a BREAK
instruction to inform the operating system if one is detected.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-59

DIVU
31

Divide Unsigned Word
26 25

SPECIAL
000000
6

21 20

16 15

6
0
000000 0000
10

0
DIVU
011011
6

MIPS I

Format:
Purpose:

DIVU rs, rt

Description:

(LO, HI) ← rs / rt

To divide 32-bit unsigned integers.

The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both
operands as unsigned values. The 32-bit quotient is placed into special register LO and
the 32-bit remainder is placed into special register HI.
No arithmetic exception occurs under any circumstances.

Restrictions:
On 64-bit processors, if either GPR rt or GPR rs do not contain sign-extended 32-bit
values (bits 63..31 equal), then the result of the operation is undefined.
If either of the two preceding instructions is MFHI or MFLO, the result of the MFHI or
MFLO is undefined. Reads of the HI or LO special registers must be separated from
subsequent instructions that write to them, like this one, by two or more other
instructions.
If the divisor in GPR rt is zero, the arithmetic result is undefined.

Operation:
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
I - 2 :, I - 1 :
LO, HI ← undefined
I:
q
← (0 || GPR[rs]31..0) div (0 || GPR[rt]31..0)
LO
← sign_extend(q31..0)
r
← (0 || GPR[rs]31..0) mod (0 || GPR[rt]31..0)
HI
← sign_extend(r31..0)

Exceptions:
None

Programming Notes:
See the Programming Notes for the DIV instruction.

A-60

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

DMULT

Doubleword Multiply
31

26 25

21 20

SPECIAL
000000
6

16 15

0
00 0000 0000
10

DMULT
011100
6

MIPS III

Format:
Purpose:

DMULT rs, rt

Description:

(LO, HI) ← rs × rt

To multiply 64-bit signed integers.

The 64-bit doubleword value in GPR rt is multiplied by the 64-bit value in GPR rs,
treating both operands as signed values, to produce a 128-bit result. The low-order 64bit doubleword of the result is placed into special register LO, and the high-order 64bit doubleword is placed into special register HI.
No arithmetic exception occurs under any circumstances.

Operation:

64- bit processors

I - 2 :, I - 1 :LO, HI ← undefined
I:
prod
← GPR[rs] * GPR[rt]

LO
HI

← prod63..0
← prod127..64

Exceptions:
Reserved Instruction

Programming Notes:
In some processors the integer multiply operation may proceed asynchronously and
allow other CPU instructions to execute before it is complete. An attempt to read LO
or HI before the results are written will wait (interlock) until the results are ready.
Asynchronous execution does not affect the program result, but offers an opportunity
for performance improvement by scheduling the multiply so that other instructions
can execute in parallel.
Programs that require overflow detection must check for it explicitly.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-61

DMULTU
31

Doubleword Multiply Unsigned

26 25
SPECIAL
000000
6

21 20

16 15

Format:
Purpose:

DMULTU rs, rt

Description:

(LO, HI) ← rs × rt

0
00 0000 0000
10

DMULTU
011101
6

MIPS III

To multiply 64-bit unsigned integers.

The 64-bit doubleword value in GPR rt is multiplied by the 64-bit value in GPR rs,
treating both operands as unsigned values, to produce a 128-bit result. The low-order
64-bit doubleword of the result is placed into special register LO, and the high-order
64-bit doubleword is placed into special register HI.
No arithmetic exception occurs under any circumstances.

Operation:

64- bit processors

I - 2 :, I - 1 :LO, HI ← undefined
I:
prod
← (0 || GPR[rs]) * (0 || GPR[rt])

LO
HI

← prod63..0
← prod127..64

Exceptions:
Reserved Instruction

A-62

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

DSLL

Doubleword Shift Left Logical
31

26 25
SPECIAL
000000
6

21 20

0
00000
5

Format:
Purpose:

DSLL rd, rt, sa

Description:

rd ← rt << sa

16 15

11 10

DSLL
111000
6

MIPS III

To left shift a doubleword by a fixed amount  0 to 31 bits.

The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the
emptied bits; the result is placed in GPR rd. The bit shift count in the range 0 to 31 is
specified by sa.

Restrictions:
None

Operation:

64- bit processors

s
← 0 || sa
GPR[rd]← GPR[rt](63–s)..0 || 0s

Exceptions:
Reserved Instruction

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-63

DSLL32
31

Doubleword Shift Left Logical Plus 32

26 25
SPECIAL
000000
6

21 20

0
00000
5

Format:
Purpose:

DSLL32 rd, rt, sa

Description:

rd ← rt << (sa+32)

16 15

11 10

0
DSLL32
111100
6

MIPS III

To left shift a doubleword by a fixed amount  32 to 63 bits.

The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the
emptied bits; the result is placed in GPR rd. The bit shift count in the range 32 to 63 is
specified by sa+32.

Restrictions:
None

Operation:

64- bit processors

s
← 1 || sa
/* 32+sa */
GPR[rd]← GPR[rt](63–s)..0 || 0s

Exceptions:
Reserved Instruction

A-64

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Doubleword Shift Left Logical Variable
31

26 25
SPECIAL
000000
6

21 20

DSLLV

16 15

11 10

Format:
Purpose:

DSLLV rd, rt, rs

Description:

rd ← rt << rs

0
00000
5

0
DSLLV
010100
6

MIPS III

To left shift a doubleword by a variable number of bits.

The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the
emptied bits; the result is placed in GPR rd. The bit shift count in the range 0 to 63 is
specified by the low-order six bits in GPR rs.

Restrictions:
None

Operation:

64- bit processors

s
← 0 || GPR[rs]5..0
GPR[rd]← GPR[rt](63–s)..0 || 0s

Exceptions:
Reserved Instruction

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-65

DSRA
31

Doubleword Shift Right Arithmetic

26 25
SPECIAL
000000
6

21 20

0
00000
5

Format:
Purpose:

DSRA rd, rt, sa

Description:

rd ← rt >> sa

16 15

11 10

DSRA
111011
6

MIPS III

To arithmetic right shift a doubleword by a fixed amount  0 to 31 bits.
(arithmetic)

The 64-bit doubleword contents of GPR rt are shifted right, duplicating the sign bit (63)
into the emptied bits; the result is placed in GPR rd. The bit shift count in the range 0
to 31 is specified by sa.

Restrictions:
None

Operation:

64- bit processors

s
← 0 || sa
GPR[rd]← (GPR[rt]63)s || GPR[rt] 63..s

Exceptions:
Reserved Instruction

A-66

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

DSRA32

Doubleword Shift Right Arithmetic Plus 32
31

26 25
SPECIAL
000000
6

21 20

0
00000
5

Format:
Purpose:

DSRA32 rd, rt, sa

Description:

rd ← rt >> (sa+32)

16 15

11 10

DSRA32
111111
6

MIPS III

To arithmetic right shift a doubleword by a fixed amount  32-63 bits.
(arithmetic)

The doubleword contents of GPR rt are shifted right, duplicating the sign bit (63) into
the emptied bits; the result is placed in GPR rd. The bit shift count in the range 32 to 63
is specified by sa+32.

Restrictions:
None

Operation:

64- bit processors

s
← 1 || sa
/* 32+sa */
GPR[rd]← (GPR[rt]63)s || GPR[rt] 63..s

Exceptions:
Reserved Instruction

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-67

DSRAV
31

Doubleword Shift Right Arithmetic Variable

26 25
SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

DSRAV rd, rt, rs

Description:

rd ← rt >> rs

0
00000
5

DSRAV
010111
6

MIPS III

To arithmetic right shift a doubleword by a variable number of bits.
(arithmetic)

The doubleword contents of GPR rt are shifted right, duplicating the sign bit (63) into
the emptied bits; the result is placed in GPR rd. The bit shift count in the range 0 to 63
is specified by the low-order six bits in GPR rs.

Restrictions:
None

Operation:

64- bit processors

s
← GPR[rs]5..0
GPR[rd]← (GPR[rt]63)s || GPR[rt]63..s

Exceptions:
Reserved Instruction

A-68

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

DSRL

Doubleword Shift Right Logical
31

26 25

21 20

0
00000
5

SPECIAL
000000
6

Format:
Purpose:

DSRL rd, rt, sa

Description:

rd ← rt >> sa

16 15

11 10

DSRL
111010
6

MIPS III

To logical right shift a doubleword by a fixed amount  0 to 31 bits.
(logical)

The doubleword contents of GPR rt are shifted right, inserting zeros into the emptied
bits; the result is placed in GPR rd. The bit shift count in the range 0 to 31 is specified
by sa.

Restrictions:
None

Operation:

64- bit processors

s
← 0 || sa
GPR[rd]← 0s || GPR[rt]63..s

Exceptions:
Reserved Instruction

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-69

DSRL32
31

Doubleword Shift Right Logical Plus 32

26 25
SPECIAL
000000
6

21 20

0
00000
5

Format:
Purpose:

DSRL32 rd, rt, sa

Description:

rd ← rt >> (sa+32)

16 15

11 10

DSRL32
111110
6

MIPS III

To logical right shift a doubleword by a fixed amount  32 to 63 bits.
(logical)

The 64-bit doubleword contents of GPR rt are shifted right, inserting zeros into the
emptied bits; the result is placed in GPR rd. The bit shift count in the range 32 to 63 is
specified by sa+32.

Restrictions:
None

Operation:

64- bit processors

s
← 1 || sa
/* 32+sa */
GPR[rd]← 0s || GPR[rt]63..s

Exceptions:
Reserved Instruction

A-70

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Doubleword Shift Right Logical Variable
31

26 25
SPECIAL
000000
6

21 20

DSRLV

16 15

11 10

Format:
Purpose:

DSRLV rd, rt, rs

Description:

rd ← rt >> rs

0
00000
5

DSRLV
010110
6

MIPS III

To logical right shift a doubleword by a variable number of bits.
(logical)

The 64-bit doubleword contents of GPR rt are shifted right, inserting zeros into the
emptied bits; the result is placed in GPR rd. The bit shift count in the range 0 to 63 is
specified by the low-order six bits in GPR rs.

Restrictions:
None

Operation:

64- bit processors

s
← GPR[rs]5..0
GPR[rd]← 0s || GPR[rt]63..s

Exceptions:
Reserved Instruction

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-71

DSUB
31

Doubleword Subtract

26 25
SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

DSUB rd, rs, rt

Description:

rd ← rs - rt

0
00000
5

DSUB
101110
6

MIPS III

To subtract 64-bit integers; trap if overflow.

The 64-bit doubleword value in GPR rt is subtracted from the 64-bit value in GPR rs to
produce a 64-bit result. If the subtraction results in 64-bit 2’s complement arithmetic
overflow then the destination register is not modified and an Integer Overflow
exception occurs. If it does not overflow, the 64-bit result is placed into GPR rd.

Restrictions:
None

Operation:

64- bit processors

temp ← GPR[rs] – GPR[rt]
if (64_bit_arithmetic_overflow) then
SignalException(IntegerOverflow)
else
GPR[rd] ← temp
endif

Exceptions:
Integer Overflow
Reserved Instruction

Programming Notes:
DSUBU performs the same arithmetic operation but, does not trap on overflow.

A-72

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

DSUBU

Doubleword Subtract Unsigned
31

26 25
SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

DSUBU rd, rs, rt

Description:

rd ← rs - rt

0
00000
5

0
DSUBU
101111
6

MIPS III

To subtract 64-bit integers.

The 64-bit doubleword value in GPR rt is subtracted from the 64-bit value in GPR rs
and the 64-bit arithmetic result is placed into GPR rd.
No Integer Overflow exception occurs under any circumstances.

Restrictions:
None

Operation:

64- bit processors

GPR[rd] ← GPR[rs] – GPR[rt]

Exceptions:
Reserved Instruction

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-73

Jump

26 25
J
000010
6

Format:
Purpose:

0
instr_index
26

MIPS I

J target
To branch within the current 256 MB aligned region.

Description:
This is a PC-region branch (not PC-relative); the effective target address is in the
“current” 256 MB aligned region. The low 28 bits of the target address is the instr_index
field shifted left 2 bits. The remaining upper bits are the corresponding bits of the
address of the instruction in the delay slot (not the branch itself).
Jump to the effective target address. Execute the instruction following the jump, in the
branch delay slot, before jumping.

Restrictions:
None

Operation:
I:
I + 1 :PC ← PCGPRLEN..28 || instr_index || 02

Exceptions:
None

Programming Notes:
Forming the branch target address by catenating PC and index bits rather than adding
a signed offset to the PC is an advantage if all program code addresses fit into a 256 MB
region aligned on a 256 MB boundary. It allows a branch to anywhere in the region
from anywhere in the region which a signed relative offset would not allow.
This definition creates the boundary case where the branch instruction is in the last
word of a 256 MB region and can therefore only branch to the following 256 MB region
containing the branch delay slot.

A-74

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

JAL

Jump And Link
31

26 25

JAL
000011
6

Format:
Purpose:

instr_index
26

JAL

MIPS I

target

To procedure call within the current 256 MB aligned region.

Description:
Place the return address link in GPR 31. The return link is the address of the second
instruction following the branch, where execution would continue after a procedure
call.
This is a PC-region branch (not PC-relative); the effective target address is in the
“current” 256 MB aligned region. The low 28 bits of the target address is the instr_index
field shifted left 2 bits. The remaining upper bits are the corresponding bits of the
address of the instruction in the delay slot (not the branch itself).
Jump to the effective target address. Execute the instruction following the jump, in the
branch delay slot, before jumping.

Restrictions:
None

Operation:
I : GPR[31] ← PC + 8
I + 1 :PC ← PCGPRLEN..28 || instr_index || 02

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-75

JALR
31

Jump And Link Register
26 25

SPECIAL
000000
6

21 20

16 15

rs
5

11 10

rd
00000
5

00000
5

Format:

JALR rs
JALR rd, rs

Purpose:

To procedure call to an instruction address in a register.

Description:

rd ← return_addr, PC ← rs

(rd = 31 implied)

0
JALR
001001
6

MIPS I

Place the return address link in GPR rd. The return link is the address of the second
instruction following the branch, where execution would continue after a procedure
call.
Jump to the effective target address in GPR rs. Execute the instruction following the
jump, in the branch delay slot, before jumping.

Restrictions:
Register specifiers rs and rd must not be equal, because such an instruction does not
have the same effect when re-executed. The result of executing such an instruction is
undefined. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
The effective target address in GPR rs must be naturally aligned. If either of the two
least-significant bits are not -zero, then an Address Error exception occurs, not for the
jump instruction, but when the branch target is subsequently fetched as an instruction.

Operation:
temp ← GPR[rs]
GPR[rd] ← PC + 8
I + 1 :PC ← temp
I:

Exceptions:
None

Programming Notes:
This is the only branch-and-link instruction that can select a register for the return link;
all other link instructions use GPR 31 The default register for GPR rd, if omitted in the
assembly language instruction, is GPR 31.

A-76

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Jump Register
31

SPECIAL
000000
6

21 20
rs
5

Format:
Purpose:

JR rs

Description:

PC ← rs

000 0000 0000 0000
15

0
JR
001000
6

MIPS I

To branch to an instruction address in a register.

Jump to the effective target address in GPR rs. Execute the instruction following the
jump, in the branch delay slot, before jumping.

Restrictions:
The effective target address in GPR rs must be naturally aligned. If either of the two
least-significant bits are not -zero, then an Address Error exception occurs, not for the
jump instruction, but when the branch target is subsequently fetched as an instruction.

Operation:
I : temp ← GPR[rs]
I + 1 :PC ← temp

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-77

LB
31

Load Byte
26 25

LB
100000
6

21 20

16 15

base

offset

Format:
Purpose:

LB rt, offset(base)

Description:

rt ← memory[base+offset]

MIPS I

To load a byte from memory as a signed value.

The contents of the 8-bit byte at the memory location specified by the effective address
are fetched, sign-extended, and placed in GPR rt. The 16-bit signed offset is added to
the contents of GPR base to form the effective address.

Restrictions:
None

Operation:

32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1).. 2 || (pAddr1..0 xor ReverseEndian2)
memword ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr1..0 xor BigEndianCPU2
GPR[rt] ← sign_extend(memword7+8*byte..8*byte)

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddrPSIZE–1..3 || (pAddr2..0 xor ReverseEndian3)
memdouble ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr2..0 xor BigEndianCPU3
GPR[rt] ← sign_extend(memdouble7+8*byte..8*byte)

Exceptions:
TLB Refill, TLB Invalid
Address Error

A-78

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LBU

Load Byte Unsigned
31

26 25

LBU
100100
6

21 20

16 15

base

offset

Format:
Purpose:

LBU rt, offset(base)

Description:

rt ← memory[base+offset]

MIPS I

To load a byte from memory as an unsigned value.

The contents of the 8-bit byte at the memory location specified by the effective address
are fetched, zero-extended, and placed in GPR rt. The 16-bit signed offset is added to
the contents of GPR base to form the effective address.

Restrictions:
None

Operation:

32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddrPSIZE – 1 .. 2 || (pAddr1..0 xor ReverseEndian2)
memword ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr1..0 xor BigEndianCPU2
GPR[rt] ← zero_extend(memword7+8* byte..8* byte)

Operation:

64- bit processors

Exceptions:
TLB Refill, TLB Invalid
Address Error

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-79

LD
31

Load Doubleword
26 25

LD
110111
6

21 20

16 15

base

offset

Format:
Purpose:

LD rt, offset(base)

Description:

rt ← memory[base+offset]

MIPS III

To load a doubleword from memory.

The contents of the 64-bit doubleword at the memory location specified by the aligned
effective address are fetched and placed in GPR rt. The 16-bit signed offset is added to
the contents of GPR base to form the effective address.

Restrictions:
The effective address must be naturally aligned. If any of the three least-significant bits
of the address are non-zero, an Address Error exception occurs.
MIPS IV: The low-order 3 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr2..0) ≠ 03 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
memdouble ← LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA)
GPR[rt] ← memdouble

Exceptions:
TLB Refill, TLB Invalid
Bus Error
Address Error
Reserved Instruction

A-80

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LDCz

Load Doubleword to Coprocessor
31

26 25
LDCz
1101zz
6

21 20

16 15

base

offset

MIPS II

Format:

LDC1 rt, offset(base)
LDC2 rt, offset(base)

Purpose:

To load a doubleword from memory to a coprocessor general register.

Description:

rt ← memory[base+offset]

The contents of the 64-bit doubleword at the memory location specified by the aligned
effective address are fetched and made available to coprocessor unit zz. The 16-bit
signed offset is added to the contents of GPR base to form the effective address.
The manner in which each coprocessor uses the data is defined by the individual
coprocessor specifications. The usual operation would place the data into coprocessor
general register rt.
Each MIPS architecture level defines up to 4 coprocessor units, numbered 0 to 3 (see
Coprocessor Instructions
on page A-11). The opcodes corresponding to coprocessors
that are not defined by an architecture level may be used for other instructions.

Restrictions:
Access to the coprocessors is controlled by system software. Each coprocessor has a
“coprocessor usable” bit in the System Control coprocessor. The usable bit must be set
for a user program to execute a coprocessor instruction. If the usable bit is not set, an
attempt to execute the instruction will result in a Coprocessor Unusable exception. An
unimplemented coprocessor must never be enabled. The result of executing this
instruction for an unimplemented coprocessor when the usable bit is set, is undefined.
This instruction is not available for coprocessor 0, the System Control coprocessor, and
the opcode may be used for other instructions.
The effective address must be naturally aligned. If any of the three least-significant bits
of the effective address are non-zero, an Address Error exception occurs.
MIPS IV: The low-order 3 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:

32- bit processors

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-81

LDCz
Operation:

Load Doubleword to Coprocessor
64- bit processors

Exceptions:
TLB Refill, TLB Invalid
Bus Error
Address Error
Reserved Instruction
Coprocessor Unusable

A-82

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LDL

Load Doubleword Left
31

26 25

LDL
011010
6

Format:
Purpose:

21 20

16 15

base

offset

MIPS III

LDL rt, offset(base)

To load the most-significant part of a doubleword from an unaligned
memory address.
rt ← rt MERGE memory[base+offset]

Description:

The 16-bit signed offset is added to the contents of GPR base to form an effective address
(EffAddr). EffAddr is the address of the most-significant of eight consecutive bytes
forming a doubleword in memory (DW) starting at an arbitrary byte boundary. A part
of DW, the most-significant one to eight bytes, is in the aligned doubleword containing
EffAddr. This part of DW is loaded appropriately into the most-significant (left) part of
GPR rt leaving the remainder of GPR rt unchanged.
The figure below illustrates this operation for big-endian byte ordering. The eight
consecutive bytes in 2..9 form an unaligned doubleword starting at location 2. A part
of DW, six bytes, is contained in the aligned doubleword containing the mostsignificant byte at 2. First, LDL loads these six bytes into the left part of the destination
register and leaves the remainder of the destination unchanged. Next, the
complementary LDR loads the remainder of the unaligned doubleword.
Doubleword at byte 2 in memory, big-endian byte order, - each mem byte contains its address

most

— significance —

least

9 10 11 12 13 14 15

Memory

GPR 24: Initial contents

After executing LDL $24,2($0)
Then after LDR $24,9($0)

Figure A-2

Unaligned Doubleword Load using LDL and LDR.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-83

LDL

Load Doubleword Left

The bytes loaded from memory to the destination register depend on both the offset of
the effective address within an aligned doubleword, i.e. the low three bits of the
address (vAddr2..0), and the current byte ordering mode of the processor (big- or littleendian). The table below shows the bytes loaded for every combination of offset and
byte ordering.
Table A-28

Bytes Loaded by LDL Instruction

Memory contents and byte offsets (vAddr2..0)

Initial contents of
Destination Register

most

— significance —

7 ← big-

most

M N

0 ← little-endian offset

least

— significance —
b

least
g

Destination register contents after instruction (shaded is unchanged)
Big-endian byte ordering
I

M N

Little-endian byte ordering

vAddr2..0

M N

Restrictions:
None

Operation:

64- bit processors

Exceptions:
TLB Refill, TLB Invalid
Bus Error
Address Error
Reserved Instruction

A-84

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LDR

Load Doubleword Right
31

26 25
LDR
011011
6

21 20

16 15

base

offset

MIPS III

Format:
Purpose:

LDR rt, offset(base)

Description:

rt ← rt MERGE memory[base+offset]

To load the least-significant part of a doubleword from an unaligned
memory address.

The 16-bit signed offset is added to the contents of GPR base to form an effective address
(EffAddr). EffAddr is the address of the least-significant of eight consecutive bytes
forming a doubleword in memory (DW) starting at an arbitrary byte boundary. A part
of DW, the least-significant one to eight bytes, is in the aligned doubleword containing
EffAddr. This part of DW is loaded appropriately into the least-significant (right) part
of GPR rt leaving the remainder of GPR rt unchanged.
The figure below illustrates this operation for big-endian byte ordering. The eight
consecutive bytes in 2..9 form an unaligned doubleword starting at location 2. A part
of DW, two bytes, is contained in the aligned doubleword containing the leastsignificant byte at 9. First, LDR loads these two bytes into the right part of the
destination register and leaves the remainder of the destination unchanged. Next, the
complementary LDL loads the remainder of the unaligned doubleword.
Doubleword at byte 2 in memory, big-endian byte order, - each mem byte contains its address

most

— significance —

least

9 10 11 12 13 14 15

GPR 24: Initial contents

After executing LDR $24,9($0)

Memory

Then after LDL $24,2($0)

Figure A-3

Unaligned Doubleword Load using LDR and LDL.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-85

LDR

Load Doubleword Right

Bytes Loaded by LDR Instruction

Memory contents and byte offsets (vAddr2..0)

Initial contents of
Destination Register

most

— significance —

7 ← big-

most

M N

0 ← little-endian offset

least

— significance —
b

least
g

Destination register contents after instruction (shaded is unchanged)
Big-endian byte ordering

Little-endian byte ordering

vAddr2..0

M N

Restrictions:
None

Operation:

64- bit processors

Exceptions:
TLB Refill, TLB Invalid
Bus Error
Address Error
Reserved Instruction

A-86

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Load Halfword
31

26 25
LH
100001
6

21 20

16 15

base

offset

Format:
Purpose:

LH rt, offset(base)

Description:

rt ← memory[base+offset]

MIPS I

To load a halfword from memory as a signed value.

The contents of the 16-bit halfword at the memory location specified by the aligned
effective address are fetched, sign-extended, and placed in GPR rt. The 16-bit signed
offset is added to the contents of GPR base to form the effective address.

Restrictions:
The effective address must be naturally aligned. If the least-significant bit of the
address is non-zero, an Address Error exception occurs.
MIPS IV: The low-order bit of the offset field must be zero. If it is not, the result of the
instruction is undefined.

Operation:

32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr0) ≠ 0 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddrPSIZE – 1..2 || (pAddr1..0 xor (ReverseEndian || 0))
memword ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr1..0 xor (BigEndianCPU || 0)
GPR[rt] ← sign_extend(memword15+8*byte..8* byte)

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr0) ≠ 0 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddrPSIZE – 1..3 || (pAddr2..0 xor (ReverseEndian || 0))
memdouble ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr2..0 xor (BigEndianCPU2 || 0)
GPR[rt] ← sign_extend(memdouble15+8*byte..8* byte)

Exceptions:
TLB Refill , TLB Invalid
Bus Error
Address Error

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-87

LHU
31

Load Halfword Unsigned
26 25

LHU
100101
6

21 20

16 15

base

offset

Format:
Purpose:

LHU rt, offset(base)

Description:

rt ← memory[base+offset]

MIPS I

To load a halfword from memory as an unsigned value.

The contents of the 16-bit halfword at the memory location specified by the aligned
effective address are fetched, zero-extended, and placed in GPR rt. The 16-bit signed
offset is added to the contents of GPR base to form the effective address.

Operation:

32- bit processors

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr0) ≠ 0 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddrPSIZE – 1..3 || (pAddr2..0 xor (ReverseEndian2 || 0))
memdouble ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr2..0 xor (BigEndianCPU2 || 0)
GPR[rt] ← zero_extend(memdouble15+8*byte..8*byte)

Exceptions:
TLB Refill, TLB Invalid
Address Error

A-88

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Load Linked Word
31

26 25
LL
110000
6

21 20

16 15

base

offset

Format:
Purpose:

LL rt, offset(base)

Description:

rt ← memory[base+offset]

MIPS II

To load a word from memory for an atomic read-modify-write.

The LL and SC instructions provide primitives to implement atomic Read-ModifyWrite (RMW) operations for cached memory locations.
The 16-bit signed offset is added to the contents of GPR base to form an effective
address.
The contents of the 32-bit word at the memory location specified by the aligned
effective address are fetched, sign-extended to the GPR register length if necessary, and
written into GPR rt. This begins a RMW sequence on the current processor.
There is one active RMW sequence per processor. When an LL is executed it starts the
active RMW sequence replacing any other sequence that was active.
The RMW sequence is completed by a subsequent SC instruction that either completes
the RMW sequence atomically and succeeds, or does not and fails. See the description
of SC for a list of events and conditions that cause the SC to fail and an example
instruction sequence using LL and SC.
Executing LL on one processor does not cause an action that, by itself, would cause an
SC for the same block to fail on another processor.
An execution of LL does not have to be followed by execution of SC; a program is free
to abandon the RMW sequence without attempting a write.

Restrictions:
The addressed location must be cached; if it is not, the result is undefined (see Memory
Access Types on page A-12).
The effective address must be naturally aligned. If either of the two least-significant
bits of the effective address are non-zero an Address Error exception occurs.
MIPS IV: The low-order 2 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-89

LL
Operation:

Load Linked Word
32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr1..0) ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
memword ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
GPR[rt] ← memword
LLbit ← 1

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr1..0) ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
memdouble ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte ← vAddr2..0 xor (BigEndianCPU || 02)
GPR[rt] ← sign_extend(memdouble31+8*byte..8*byte)
LLbit ← 1

Exceptions:
TLB Refill, TLB Invalid
Address Error
Reserved Instruction

Programming Notes:
There is no Load Linked Word Unsigned operation corresponding to Load Word
Unsigned.

Implementation Notes:
An LL on one processor must not take action that, by itself, would cause an SC for the
same block on another processor to fail. If an implementation depends on retaining the
data in cache during the RMW sequence, cache misses caused by LL must not fetch
data in the exclusive state, thus removing it from the cache, if it is present in another
cache.

A-90

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LLD

Load Linked Doubleword
31

26 25
LLD
110100
6

21 20

16 15

base

offset

Format:
Purpose:

LLD rt, offset(base)

Description:

rt ← memory[base+offset]

MIPS III

To load a doubleword from memory for an atomic read-modify-write.

The LLD and SCD instructions provide primitives to implement atomic Read-ModifyWrite (RMW) operations for cached memory locations.
The 16-bit signed offset is added to the contents of GPR base to form an effective
address.
The contents of the 64-bit doubleword at the memory location specified by the aligned
effective address are fetched and written into GPR rt. This begins a RMW sequence on
the current processor.
There is one active RMW sequence per processor. When an LLD is executed it starts
the active RMW sequence replacing any other sequence that was active.
The RMW sequence is completed by a subsequent SCD instruction that either
completes the RMW sequence atomically and succeeds, or does not and fails. See the
description of SCD for a list of events and conditions that cause the SCD to fail and an
example instruction sequence using LLD and SCD.
Executing LLD on one processor does not cause an action that, by itself, would cause
an SCD for the same block to fail on another processor.
An execution of LLD does not have to be followed by execution of SCD; a program is
free to abandon the RMW sequence without attempting a write.

Restrictions:
The addressed location must be cached; if it is not, the result is undefined (see Memory
Access Types on page A-12).
The effective address must be naturally aligned. If either of the three least-significant
bits of the effective address are non-zero an Address Error exception occurs.
MIPS IV: The low-order 3 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-91

LLD
Operation:

Load Linked Doubleword
64- bit processors

Exceptions:
TLB Refill, TLB Invalid
Address Error
Reserved Instruction

Programming Notes:
Implementation Notes:
An LLD on one processor must not take action that, by itself, would cause an SCD for
the same block on another processor to fail. If an implementation depends on retaining
the data in cache during the RMW sequence, cache misses caused by LLD must not
fetch data in the exclusive state, thus removing it from the cache, if it is present in
another cache.

A-92

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LUI

Load Upper Immediate
31

26 25
LUI
001111
6

21 20

0
00000
5

16 15

immediate

Format:
Purpose:

LUI rt, immediate

Description:

rt ← immediate || 016

MIPS I

To load a constant into the upper half of a word.

The 16-bit immediate is shifted left 16 bits and concatenated with 16 bits of low-order
zeros. The 32-bit result is sign-extended and placed into GPR rt.

Restrictions:
None

Operation:
GPR[rt] ← sign_extend(immediate || 016)

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-93

LW
31

Load Word
26 25

LW
100011
6

21 20

16 15

base

offset

Format:
Purpose:

LW rt, offset(base)

Description:

rt ← memory[base+offset]

MIPS I

To load a word from memory as a signed value.

The contents of the 32-bit word at the memory location specified by the aligned
effective address are fetched, sign-extended to the GPR register length if necessary, and
placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form
the effective address.

Restrictions:
The effective address must be naturally aligned. If either of the two least-significant
bits of the address are non-zero, an Address Error exception occurs.
MIPS IV: The low-order 2 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:

32- bit processors

Operation:

64- bit processors

Exceptions:
TLB Refill, TLB Invalid
Bus Error
Address Error

A-94

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LWCz

Load Word To Coprocessor
31

26 25
LWCz
1100zz
6

21 20

16 15

base

offset

MIPS I

Format:

LWC1 rt, offset(base)
LWC2 rt, offset(base)
LWC3 rt, offset(base)

Purpose:

To load a word from memory to a coprocessor general register.

Description:

rt ← memory[base+offset]

The contents of the 32-bit word at the memory location specified by the aligned
effective address are fetched and made available to coprocessor unit zz. The 16-bit
signed offset is added to the contents of GPR base to form the effective address.
The manner in which each coprocessor uses the data is defined by the individual
coprocessor specification. The usual operation would place the data into coprocessor
general register rt.
Each MIPS architecture level defines up to 4 coprocessor units, numbered 0 to 3 (see
Coprocessor Instructions
on page A-11). The opcodes corresponding to coprocessors
that are not defined by an architecture level may be used for other instructions.

Restrictions:
Access to the coprocessors is controlled by system software. Each coprocessor has a
“coprocessor usable” bit in the System Control coprocessor. The usable bit must be set
for a user program to execute a coprocessor instruction. If the usable bit is not set, an
attempt to execute the instruction will result in a Coprocessor Unusable exception. An
unimplemented coprocessor must never be enabled. The result of executing this
instruction for an unimplemented coprocessor when the usable bit is set, is undefined.
This instruction is not available for coprocessor 0, the System Control coprocessor, and
the opcode may be used for other instructions.
The effective address must be naturally aligned. If either of the two least-significant
bits of the address are non-zero, an Address Error exception occurs.
MIPS IV: The low-order 2 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:

32- bit processors

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-95

LWCz
Operation:

Load Word To Coprocessor
64- bit processors

vAddr ← sign_extend(offset) + GPR[base}
if (vAddr1..0) ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached)← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
memdouble ← LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA)
byte ← vAddr2..0 xor (BigEndianCPU || 02)
memword ← memdouble31+8*byte..8*byte
COP_LW (z, rt, memdouble)

Exceptions:
TLB Refill, TLB Invalid
Bus Error
Address Error
Coprocessor Unusable

A-96

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LWL

Load Word Left
31

26 25
LWL
100010
6

21 20

16 15

base

offset

MIPS I

Format:
Purpose:

LWL rt, offset(base)

Description:

rt ← rt MERGE memory[base+offset]

To load the most-significant part of a word as a signed value from an
unaligned memory address.

The 16-bit signed offset is added to the contents of GPR base to form an effective address
(EffAddr). EffAddr is the address of the most-significant of four consecutive bytes
forming a word in memory (W) starting at an arbitrary byte boundary. A part of W, the
most-significant one to four bytes, is in the aligned word containing EffAddr. This part
of W is loaded into the most-significant (left) part of the word in GPR rt. The remaining
least-significant part of the word in GPR rt is unchanged.
If GPR rt is a 64-bit register, the destination word is the low-order word of the register.
The loaded value is treated as a signed value; the word sign bit (bit 31) is always loaded
from memory and the new sign bit value is copied into bits 63..32.
Word at byte 2 in memory, big-endian byte order, - each mem byte contains its address
most

sign bit (31) extend

Figure A-4

- significance -

least

32-bit GPR 24: Initial contents

64-bit GPR 24

After executing LWL $24,2($0)

Memory initial contents

Then after LWR $24,5($0)

Unaligned Word Load using LWL and LWR.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-97

LWL

Load Word Left

The figure above illustrates this operation for big-endian byte ordering for 32-bit and
64-bit registers. The four consecutive bytes in 2..5 form an unaligned word starting at
location 2. A part of W, two bytes, is in the aligned word containing the mostsignificant byte at 2. First, LWL loads these two bytes into the left part of the
destination register word and leaves the right part of the destination word unchanged.
Next, the complementary LWR loads the remainder of the unaligned word.
The bytes loaded from memory to the destination register depend on both the offset of
the effective address within an aligned word, i.e. the low two bits of the address
(vAddr1..0), and the current byte ordering mode of the processor (big- or little-endian).
The table below shows the bytes loaded for every combination of offset and byte
ordering.
Table A-30

Bytes Loaded by LWL Instruction

Memory contents and byte offsets
0

3 ← big-endian

most

Initial contents of Dest Register
64-bit register

offset (vAddr1..0)

0 ← little-endian

most

least

— significance —

32-bit register

least
g

— significance —
Destination 64-bit register contents after instruction (shaded is unchanged)
Big-endian byte ordering

vAddr1..0

Little-endian byte ordering

sign bit (31) extended

The word sign (31) is always loaded and the value is copied into bits 63..32.
32-bit register

Big-endian

vAddr1..0

Little-endian

The unaligned loads, LWL and LWR, are exceptions to the load-delay scheduling
restriction in the MIPS I architecture. An unaligned load instruction to GPR rt that
immediately follows another load to GPR rt can “read” the loaded data. It will
correctly merge the 1 to 4 loaded bytes with the data loaded by the previous
instruction.

A-98

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LWL

Load Word Left
Restrictions:

MIPS I scheduling restriction: The loaded data is not available for use by the following
instruction. The instruction immediately following this one, unless it is an unaligned
load (LWL, LWR), may not use GPR rt as a source register. If this restriction is violated,
the result of the operation is undefined.

Operation:

32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..2 || (pAddr1..0 xor ReverseEndian2)
if BigEndianMem = 0 then
pAddr ← pAddr(PSIZE-1)..2 || 02
endif
byte ← vAddr1..0 xor BigEndianCPU2
memword ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
GPR[rt] ← memword7+8*byte..0 || GPR[rt]23–8*byte..0

Operation:

64- bit processors

Exceptions:
TLB Refill, TLB Invalid
Bus Error
Address Error

Programming Notes:
The architecture provides no direct support for treating unaligned words as unsigned
values, i.e. zeroing bits 63..32 of the destination register when bit 31 is loaded. See SLL
or SLLV for a single-instruction method of propagating the word sign bit in a register
into the upper half of a 64-bit register.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-99

LWR

Load Word Right

26 25
LWR
100110
6

21 20

16 15

base

offset

MIPS I

Format:
Purpose:

LWR rt, offset(base)

Description:

rt ← rt MERGE memory[base+offset]

To load the least-significant part of a word from an unaligned memory
address as a signed value.

The 16-bit signed offset is added to the contents of GPR base to form an effective address
(EffAddr). EffAddr is the address of the least-significant of four consecutive bytes
forming a word in memory (W) starting at an arbitrary byte boundary. A part of W, the
least-significant one to four bytes, is in the aligned word containing EffAddr. This part
of W is loaded into the least-significant (right) part of the word in GPR rt. The
remaining most-significant part of the word in GPR rt is unchanged.
If GPR rt is a 64-bit register, the destination word is the low-order word of the register.
The loaded value is treated as a signed value; if the word sign bit (bit 31) is loaded (i.e.
when all four bytes are loaded) then the new sign bit value is copied into bits 63..32. If
bit 31 is not loaded then the value of bits 63..32 is implementation dependent; the value
is either unchanged or a copy of the current value of bit 31. Executing both LWR and
LWL, in either order, delivers in a sign-extended word value in the destination register.
Word at byte 2 in memory, big-endian byte order, - each mem byte contains its address
most

no cng or sign ext

sign bit (31) extend

Figure A-5

A-100

- significance -

least

32-bit GPR 24: Initial contents

64-bit GPR 24

After executing LWR $24,5($0)

Memory initial contents

Then after LWL $24,2($0)

Unaligned Word Load using LWR and LWL.

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LWR

Load Word Right

The figure above illustrates this operation for big-endian byte ordering for 32-bit and
64-bit registers. The four consecutive bytes in 2..5 form an unaligned word starting at
location 2. A part of W, two bytes, is in the aligned word containing the leastsignificant byte at 5. First, LWR loads these two bytes into the right part of the
destination register. Next, the complementary LWL loads the remainder of the
unaligned word.
The bytes loaded from memory to the destination register depend on both the offset of
the effective address within an aligned word, i.e. the low two bits of the address
(vAddr1..0), and the current byte ordering mode of the processor (big- or little-endian).
The table below shows the bytes loaded for every combination of offset and byte
ordering.

Table A-31

Bytes Loaded by LWR Instruction

Memory contents and byte offsets
0

3 ← big-endian

0 ← little-endian

most

Initial contents of Dest Register
64-bit register

offset (vAddr1..0)

most

least

— significance —

32-bit register

least
g

— significance —
Destination 64-bit register contents after instruction (shaded is unchanged)
Big-endian byte ordering

vAddr1..0

Little-endian byte ordering

No cng or sign-extend

sign bit (31) extended

No cng or sign-extend

sign bit (31) extended

No cng or sign-extend

When the word sign bit (31) is loaded, its value is copied into bits 63..32. When it
is not loaded, the behavior is implementation specific. Bits 63..32 are either
unchanged or a the value of the unloaded bit 31 is copied into them.
32-bit register

big-endian

vAddr1..0

little-endian

The unaligned loads, LWL and LWR, are exceptions to the load-delay scheduling
restriction in the MIPS I architecture. An unaligned load to GPR rt that immediately
follows another load to GPR rt can “read” the loaded data. It will correctly merge the
1 to 4 loaded bytes with the data loaded by the previous instruction.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-101

LWR

Load Word Right

Restrictions:
MIPS I scheduling restriction: The loaded data is not available for use by the following
instruction. The instruction immediately following this one, unless it is an unaligned
load (LWL, LWR), may not use GPR rt as a source register. If this restriction is violated,
the result of the operation is undefined.

Restrictions:
None

Operation:

32- bit processors

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..3 || (pAddr2..0 xor ReverseEndian3)
if BigEndianMem = 1 then
pAddr ← pAddr(PSIZE-1)..3 || 03
endif
byte ← vAddr1..0 xor BigEndianCPU2
word ← vAddr2 xor BigEndianCPU
memdouble ← LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA)
temp ← GPR[rt]31..32-8*byte || memdouble31+32*word..32*word+8*byte
if byte = 4 then
/* loaded bit 31, must sign extend */
utemp ← (temp31)32
else
one of the following two behaviors:
utemp ← GPR[rt]63..32
/* leave what was there alone */
/* sign-extend bit 31 */
utemp ← (GPR[rt]31)32
endif
GPR[rt] ← utemp || temp

Exceptions:
TLB Refill, TLB Invalid
Bus Error
Address Error

A-102

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

LWR

Load Word Right

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-103

LWU
31

Load Word Unsigned
26 25

LWU
100111
6

21 20

16 15

base

offset

Format:
Purpose:

LWU rt, offset(base)

Description:

rt ← memory[base+offset]

MIPS III

To load a word from memory as an unsigned value.

The contents of the 32-bit word at the memory location specified by the aligned
effective address are fetched, zero-extended, and placed in GPR rt. The 16-bit signed
offset is added to the contents of GPR base to form the effective address.

Operation:

64- bit processors

Exceptions:
TLB Refill, TLB Invalid
Bus Error
Address Error
Reserved Instruction

A-104

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

MFHI

Move From HI Register
31

26 25
SPECIAL
000000
6

16 15

0
00 0000 0000
10

Format:
Purpose:

MFHI rd

Description:

rd ← HI

11 10
rd
5

6
0
00000
5

0
MFHI
010000
6

MIPS I

To copy the special purpose HI register to a GPR.

The contents of special register HI are loaded into GPR rd.

Restrictions:
The two instructions that follow an MFHI instruction must not be instructions that
modify the HI register: DDIV, DDIVU, DIV, DIVU, DMULT, DMULTU, MTHI, MULT,
MULTU. If this restriction is violated, the result of the MFHI is undefined.

Operation:
GPR[rd] ← HI

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-105

MFLO
31

Move From LO Register

26 25
SPECIAL
000000
6

16 15

0
00 0000 0000
10

Format:
Purpose:

MFLO rd

Description:

rd ← LO

11 10
rd
5

6
0
00000
5

0
MFLO
010010
6

MIPS I

To copy the special purpose LO register to a GPR.

The contents of special register LO are loaded into GPR rd.

Restrictions:
The two instructions that follow an MFLO instruction must not be instructions that
modify the LO register: DDIV, DDIVU, DIV, DIVU, DMULT, DMULTU, MTLO, MULT,
MULTU. If this restriction is violated, the result of the MFLO is undefined.

Operation:
GPR[rd] ← LO

Exceptions:
None

A-106

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

MOVN

Move Conditional on Not Zero
31

26 25

SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

MOVN

Description:

if (rt ≠ 0) then rd ← rs

6 5

0
00000
5

rd, rs, rt

0
MOVN
001011
6

MIPS IV

To conditionally move a GPR after testing a GPR value.

If the value in GPR rt is not equal to zero, then the contents of GPR rs are placed into
GPR rd.

Restrictions:
None

Operation:
if GPR[rt] ≠ 0 then
GPR[rd] ← GPR[rs]
endif

Exceptions:
Reserved Instruction

Programming Notes:
The nonzero value tested here is the “condition true” result from the SLT, SLTI, SLTU,
and SLTIU comparison instructions.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-107

MOVZ
31

Move Conditional on Zero

26 25

SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

MOVZ

Description:

if (rt = 0) then rd ← rs

6 5

0
00000
5

rd, rs, rt

0
MOVZ
001010
6

MIPS IV

To conditionally move a GPR after testing a GPR value.

If the value in GPR rt is equal to zero, then the contents of GPR rs are placed into
GPR rd.

Restrictions:
None

Operation:
if GPR[rt] = 0 then
GPR[rd] ← GPR[rs]
endif

Exceptions:
Reserved Instruction

Programming Notes:
The zero value tested here is the “condition false” result from the SLT, SLTI, SLTU, and
SLTIU comparison instructions.

A-108

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

MTHI

Move To HI Register
31

26 25
SPECIAL
000000
6

21 20
rs
5

Format:
Purpose:

MTHI rs

Description:

HI ← rs

0
0 0000 0000 0000 00
15

MTHI
010001
6

MIPS I

To copy a GPR to the special purpose HI register.

The contents of GPR rs are loaded into special register HI.

Restrictions:
If either of the two preceding instructions is MFHI, the result of that MFHI is
undefined. Reads of the HI or LO special registers must be separated from subsequent
instructions that write to them by two or more other instructions.
A computed result written to the HI/LO pair by DDIV, DDIVU, DIV, DIVU, DMULT,
DMULTU, MULT, or MULTU must be read by MFHI or MFLO before another result is
written into either HI or LO. If an MTHI instruction is executed following one of these
arithmetic instructions, but before a MFLO or MFHI instruction, the contents of LO are
undefined. The following example shows this illegal situation:
MUL r2,r4
...
MTHI r6
...
MFLO r3

# start operation that will eventually write to HI,LO
# code not containing mfhi or mflo
# code not containing mflo
# this mflo would get an undefined value

Operation:
I - 2 :, I - 1 :HI ← undefined
I:
HI ← GPR[rs]

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-109

MTLO
31

Move To LO Register

26 25
SPECIAL
000000
6

21 20
rs
5

Format:
Purpose:

MTLO rs

Description:

LO ← rs

0
0 0000 0000 0000 00
15

MTLO
010011
6

MIPS I

To copy a GPR to the special purpose LO register.

The contents of GPR rs are loaded into special register LO.

Restrictions:
If either of the two preceding instructions is MFLO, the result of that MFLO is
undefined. Reads of the HI or LO special registers must be separated from subsequent
instructions that write to them by two or more other instructions.
A computed result written to the HI/LO pair by DDIV, DDIVU, DIV, DIVU, DMULT,
DMULTU, MULT, or MULTU must be read by MFHI or MFLO before another result is
written into either HI or LO. If an MTLO instruction is executed following one of these
arithmetic instructions, but before a MFLO or MFHI instruction, the contents of HI are
undefined. The following example shows this illegal situation:
MUL r2,r4
...
MTLO r6
...
MFHI r3

# start operation that will eventually write to HI,LO
# code not containing mfhi or mflo
# code not containing mfhi
# this mfhi would get an undefined value

Operation:
I - 2 :, I - 1 :LO ← undefined
I:
LO ← GPR[rs]

Exceptions:
None

A-110

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

MULT

Multiply Word
31

26 25

SPECIAL
000000
6

21 20

16 15

0
00 0000 0000
10

MULT
011000
6

MIPS I

Format:
Purpose:

MULT rs, rt

Description:

(LO, HI) ← rs × rt

To multiply 32-bit signed integers.

The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating
both operands as signed values, to produce a 64-bit result. The low-order 32-bit word
of the result is placed into special register LO, and the high-order 32-bit word is placed
into special register HI.
No arithmetic exception occurs under any circumstances.

Operation:
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
I - 2 :, I - 1 :
LO, HI ← undefined
I:
prod
← GPR[rs]31..0 * GPR[rt]31..0
LO
← sign_extend(prod31..0)
HI
← sign_extend(prod63..32)

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-111

MULTU
31

Multiply Unsigned Word

26 25
SPECIAL
000000
6

21 20

16 15

Format:
Purpose:

MULTU rs, rt

Description:

(LO, HI) ← rs × rt

6
0
00 0000 0000
10

MULTU
011001
6

MIPS I

To multiply 32-bit unsigned integers.

The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating
both operands as unsigned values, to produce a 64-bit result. The low-order 32-bit
word of the result is placed into special register LO, and the high-order 32-bit word is
placed into special register HI.
No arithmetic exception occurs under any circumstances.

Operation:
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
I - 2 :, I - 1 :
LO, HI ← undefined
I:
prod
← (0 || GPR[rs]31..0) * (0 || GPR[rt]31..0)
LO
← sign_extend(prod31..0)
HI
← sign_extend(prod63..32)

Exceptions:
None

A-112

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

NOR

Not Or
31

26 25
SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

NOR rd, rs, rt

Description:

rd ← rs NOR rt

0
00000
5

NOR
100111
6

MIPS I

To do a bitwise logical NOT OR.

The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical
NOR operation. The result is placed into GPR rd.

Restrictions:
None

Operation:
GPR[rd] ← GPR[rs] nor GPR[rt]

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-113

OR
31

Or
26 25

SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

OR rd, rs, rt

Description:

rd ← rs OR rt

0
00000
5

OR
100101
6

MIPS I

To do a bitwise logical OR.

The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical
OR operation. The result is placed into GPR rd.

Restrictions:
None

Operation:
GPR[rd] ← GPR[rs] or GPR[rt]

Exceptions:
None

A-114

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

ORI

Or Immediate
31

26 25
ORI
001101
6

21 20

16 15

immediate

Format:
Purpose:

ORI rt, rs, immediate

Description:

rd ← rs OR immediate

MIPS I

To do a bitwise logical OR with a constant.

The 16-bit immediate is zero-extended to the left and combined with the contents of
GPR rs in a bitwise logical OR operation. The result is placed into GPR rt.

Restrictions:
None

Operation:
GPR[rt] ← zero_extend(immediate) or GPR[rs]

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-115

PREF
31

Prefetch
26 25

21 20

16 15

PREF
110011

base

hint

offset

Format:
Purpose:

PREF hint, offset(base)

Description:

prefetch_memory(base+offset)

MIPS IV

To prefetch data from memory.

PREF adds the 16-bit signed offset to the contents of GPR base to form an effective byte
address. It advises that data at the effective address may be used in the near future.
The hint field supplies information about the way that the data is expected to be used.
PREF is an advisory instruction. It may change the performance of the program. For
all hint values and all effective addresses, it neither changes architecturally-visible state
nor alters the meaning of the program. An implementation may do nothing when
executing a PREF instruction.
If MIPS IV instructions are supported and enabled, PREF does not cause addressingrelated exceptions. If it raises an exception condition, the exception condition is
ignored. If an addressing-related exception condition is raised and ignored, no data
will be prefetched, Even if no data is prefetched in such a case, some action that is not
architecturally-visible, such as writeback of a dirty cache line, might take place.
PREF will never generate a memory operation for a location with an uncached memory
access type (see Memory Access Types
on page A-12).
If PREF results in a memory operation, the memory access type used for the operation
is determined by the memory access type of the effective address, just as it would be if
the memory operation had been caused by a load or store to the effective address.
PREF enables the processor to take some action, typically prefetching the data into
cache, to improve program performance. The action taken for a specific PREF
instruction is both system and context dependent. Any action, including doing
nothing, is permitted that does not change architecturally-visible state or alter the
meaning of a program. It is expected that implementations will either do nothing or
take an action that will increase the performance of the program.
For a cached location, the expected, and useful, action is for the processor to prefetch a
block of data that includes the effective address. The size of the block, and the level of
the memory hierarchy it is fetched into are implementation specific.

A-116

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

PREF

Prefetch

The hint field supplies information about the way the data is expected to be used. No
hint value causes an action that modifies architecturally-visible state. A processor may
use a hint value to improve the effectiveness of the prefetch action. The defined hint
values and the recommended prefetch action are shown in the table below. The hint
table may be extended in future implementations.
Table A-32

Values of Hint Field for Prefetch Instruction

Value

Name

Data use and desired prefetch action

load

Data is expected to be loaded (not modified).
Fetch data as if for a load.

store

Data is expected to be stored or modified.
Fetch data as if for a store.

2-3

Not yet defined.

load_streamed

store_streamed Data is expected to be stored or modified but not
reused extensively; it will “stream” through cache.
Fetch data as if for a store and place it in the cache so
that it will not displace data prefetched as “retained”.

load_retained

Data is expected to be loaded (not modified) and
reused extensively; it should be “retained” in the cache.
Fetch data as if for a load and place it in the cache so
that it will not be displaced by data prefetched as
“streamed”.

store_retained

Data is expected to be stored or modified and reused
extensively; it should be “retained” in the cache.
Fetch data as if for a store and place it in the cache so
that will not be displaced by data prefetched as
“streamed”.

8-31

Data is expected to be loaded (not modified) but not
reused extensively; it will “stream” through cache.
Fetch data as if for a load and place it in the cache so
that it will not displace data prefetched as “retained”.

Not yet defined.

Restrictions:
None

Operation:
vAddr ← GPR[base] + sign_extend(offset)
(pAddr, uncached) ← AddressTranslation(vAddr, DATA, LOAD)
Prefetch(uncached, pAddr, vAddr, DATA, hint)

Exceptions:
Reserved Instruction

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-117

PREF

Prefetch

Programming Notes:
Prefetch can not prefetch data from a mapped location unless the translation for that
location is present in the TLB. Locations in memory pages that have not been accessed
recently may not have translations in the TLB, so prefetch may not be effective for such
locations.
Prefetch does not cause addressing exceptions. It will not cause an exception to
prefetch using an address pointer value before the validity of a pointer is determined.

Implementation Notes:
It is recommended that a reserved hint field value either cause a default prefetch action
that is expected to be useful for most cases of data use, such as the “load” hint, or cause
the instruction to be treated as a NOP.

A-118

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Store Byte
31

26 25
SB
101000
6

21 20

16 15

base

offset

Format:
Purpose:

SB rt, offset(base)

Description:

memory[base+offset] ← rt

MIPS I

To store a byte to memory.

The least-significant 8-bit byte of GPR rt is stored in memory at the location specified
by the effective address. The 16-bit signed offset is added to the contents of GPR base to
form the effective address.

Restrictions:
None

Operation:

32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddrPSIZE-1..2 || (pAddr1..0 xor ReverseEndian2)
byte ← vAddr1..0 xor BigEndianCPU2
dataword ← GPR[rt]31–8*byte..0 || 08*byte
StoreMemory (uncached, BYTE, dataword, pAddr, vAddr, DATA)

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor ReverseEndian3)
byte ← vAddr2..0 xor BigEndianCPU3
datadouble ← GPR[rt]63–8*byte..0 || 08*byte
StoreMemory (uncached, BYTE, datadouble, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Bus Error
Address Error

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-119

Store Conditional Word

26 25
SC
111000
6

21 20

16 15

base

offset

MIPS II

Format:
Purpose:

SC rt, offset(base)

Description:

if (atomic_update) then memory[base+offset] ← rt, rt ← 1 else rt ← 0

To store a word to memory to complete an atomic read-modify-write.

The LL and SC instructions provide primitives to implement atomic Read-ModifyWrite (RMW) operations for cached memory locations.
The 16-bit signed offset is added to the contents of GPR base to form an effective
address.
The SC completes the RMW sequence begun by the preceding LL instruction executed
on the processor. If it would complete the RMW sequence atomically, then the leastsignificant 32-bit word of GPR rt is stored into memory at the location specified by the
aligned effective address and a one, indicating success, is written into GPR rt.
Otherwise, memory is not modified and a zero, indicating failure, is written into
GPR rt.
If any of the following events occurs between the execution of LL and SC, the SC will
fail:
•

A coherent store is completed by another processor or coherent I/O module
into the block of physical memory containing the word. The size and
alignment of the block is implementation dependent. It is at least one word
and is at most the minimum page size.

•

An exception occurs on the processor executing the LL/SC.
An implementation may detect “an exception” in one of three ways:
1) Detect exceptions and fail when an exception occurs.
2) Fail after the return-from-interrupt instruction (RFE or ERET) is executed.
3) Do both 1 and 2.

If any of the following events occurs between the execution of LL and SC, the SC may
succeed or it may fail; the success or failure is unpredictable. Portable programs
should not cause one of these events.
•

A load, store, or prefetch is executed on the processor executing the LL/SC.

•

The instructions executed starting with the LL and ending with the SC do not
lie in a 2048-byte contiguous region of virtual memory. The region does not
have to be aligned, other than the alignment required for instruction words.

The following conditions must be true or the result of the SC will be undefined:
•

A-120

Execution of SC must have been preceded by execution of an LL instruction.

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Store Conditional Word
•

A RMW sequence executed without intervening exceptions must use the same
address in the LL and SC. The address is the same if the virtual address,
physical address, and cache-coherence algorithm are identical.

Atomic RMW is provided only for cached memory locations. The extent to which the
detection of atomicity operates correctly depends on the system implementation and
the memory access type used for the location. See Memory Access Types
on page
A-12.
MP atomicity : To provide atomic RMW among multiple processors, all accesses to
the location must be made with a memory access type of cached coherent.
Uniprocessor atomicity
: To provide atomic RMW on a single processor, all accesses
to the location must be made with memory access type of either cached noncoherent
or cached coherent. All accesses must be to one or the other access type, they may not
be mixed.
I/O System : To provide atomic RMW with a coherent I/O system, all accesses to the
location must be made with a memory access type of cached coherent. If the I/O
system does not use coherent memory operations, then atomic RMW cannot be
provided with respect to the I/O reads and writes.
The definition above applies to user-mode operation on all MIPS processors that
support the MIPS II architecture. There may be other implementation-specific events,
such as privileged CP0 instructions, that will cause an SC instruction to fail in some
cases. System programmers using LL/SC should consult implementation-specific
documentation.

Restrictions:
The addressed location must have a memory access type of cached noncoherent or
cached coherent; if it does not, the result is undefined (see Memory Access Types
on
page A-12).
The effective address must be naturally aligned. If either of the two least-significant
bits of the address are non-zero, an Address Error exception occurs.
MIPS IV: The low-order 2 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:

32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr1..0) ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
dataword ← GPR[rt]
if LLbit then
StoreMemory (uncached, WORD, dataword, pAddr, vAddr, DATA)
endif
GPR[rt] ← 031 || LLbit

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-121

SC
Operation:

Store Conditional Word
64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr1..0) ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
byte ← vAddr2..0 xor (BigEndianCPU || 02)
datadouble ← GPR[rt]63-8*byte..0 || 08*byte
if LLbit then
StoreMemory (uncached, WORD, datadouble, pAddr, vAddr, DATA)
endif
GPR[rt] ← 063 || LLbit

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Address Error
Reserved Instruction

Programming Notes:
LL and SC are used to atomically update memory locations as shown in the example
atomic increment operation below.
L1:
LL
ADDI
SC
BEQ
NOP

T1, (T0)
T2, T1, 1
T2, (T0)
T2, 0, L1

# load counter
# increment
# try to store, checking for atomicity
# if not atomic (0), try again
# branch-delay slot

Exceptions between the LL and SC cause SC to fail, so persistent exceptions must be
avoided. Some examples of these are arithmetic operations that trap, system calls,
floating-point operations that trap or require software emulation assistance.
LL and SC function on a single processor for cached noncoherent memory so that
parallel programs can be run on uniprocessor systems that do not support cached
coherent memory access types.

Implementation Notes:
The block of memory that is “locked” for LL/SC is typically the largest cache line in
use.

A-122

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SCD

Store Conditional Doubleword
31

26 25
SCD
111100
6

21 20

16 15

base

offset

MIPS III

Format:
Purpose:

SCD rt, offset(base)

Description:

if (atomic_update) then memory[base+offset] ← rt, rt ← 1 else rt ← 0

To store a doubleword to memory to complete an atomic read-modifywrite.

The 16-bit signed offset is added to the contents of GPR base to form an effective
address.
The SCD completes the RMW sequence begun by the preceding LLD instruction
executed on the processor. If it would complete the RMW sequence atomically, then
the 64-bit doubleword of GPR rt is stored into memory at the location specified by the
aligned effective address and a one, indicating success, is written into GPR rt.
Otherwise, memory is not modified and a zero, indicating failure, is written into
GPR rt.
If any of the following events occurs between the execution of LLD and SCD, the SCD
will fail:
•

•

An exception occurs on the processor executing the LLD/SCD.
An implementation may detect “an exception” in one of three ways:
1) Detect exceptions and fail when an exception occurs.
2) Fail after the return-from-interrupt instruction (RFE or ERET) is executed.
3) Do both 1 and 2.

If any of the following events occurs between the execution of LLD and SCD, the SCD
may succeed or it may fail; the success or failure is unpredictable. Portable programs
should not cause one of these events.
•

A memory access instruction (load, store, or prefetch) is executed on the
processor executing the LLD/SCD.

•

The instructions executed starting with the LLD and ending with the SCD do
not lie in a 2048-byte contiguous region of virtual memory. The region does
not have to be aligned, other than the alignment required for instruction
words.

The following conditions must be true or the result of the SCD will be undefined:
•

Execution of SCD must have been preceded by execution of an LLD
instruction.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-123

SCD
•

Store Conditional Doubleword

A RMW sequence executed without intervening exceptions must use the same
address in the LLD and SCD. The address is the same if the virtual address,
physical address, and cache-coherence algorithm are identical.

Atomic RMW is provided only for memory locations with cached noncoherent or
cached coherent memory access types. The extent to which the detection of atomicity
operates correctly depends on the system implementation and the memory access type
used for the location. See Memory Access Types
on page A-12.
MP atomicity : To provide atomic RMW among multiple processors, all accesses to
the location must be made with a memory access type of cached coherent.
Uniprocessor atomicity
: To provide atomic RMW on a single processor, all accesses
to the location must be made with memory access type of either cached noncoherent
or cached coherent. All accesses must be to one or the other access type, they may not
be mixed.
I/O System : To provide atomic RMW with a coherent I/O system, all accesses to the
location must be made with a memory access type of cached coherent. If the I/O
system does not use coherent memory operations, then atomic RMW cannot be
provided with respect to the I/O reads and writes.
The defemination above applies to user-mode operation on all MIPS processors that
support the MIPS III architecture. There may be other implementation-specific events,
such as privileged CP0 instructions, that will cause an SCD instruction to fail in some
cases. System programmers using LLD/SCD should consult implementation-specific
documentation.

Restrictions:
The addressed location must have a memory access type of cached noncoherent or
cached coherent; if it does not, the result is undefined (see Memory Access Types
on
page A-12The 64-bit doubleword of register rt is conditionally stored in memory at the
location specified by the aligned effective address. The 16-bit signed offset is added to
the contents of GPR base to form the effective address.
The effective address must be naturally aligned. If any of the three least-significant bits
of the address are non-zero, an Address Error exception occurs.
MIPS IV: The low-order 3 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr2..0) ≠ 03 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
datadouble ← GPR[rt]
if LLbit then
StoreMemory (uncached, DOUBLEWORD, datadouble, pAddr, vAddr, DATA)
endif
GPR[rt] ← 063 || LLbit
A-124

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SCD

Store Conditional Doubleword
Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Address Error
Reserved Instruction

Programming Notes:
LLD and SCD are used to atomically update memory locations as shown in the
example atomic increment operation below.
L1:
LLD
ADDI
SCD
BEQ
NOP

T1, (T0)
T2, T1, 1
T2, (T0)
T2, 0, L1

# load counter
# increment
# try to store, checking for atomicity
# if not atomic (0), try again
# branch-delay slot

Exceptions between the LLD and SCD cause SCD to fail, so persistent exceptions must
be avoided. Some examples of these are arithmetic operations that trap, system calls,
floating-point operations that trap or require software emulation assistance.
LLD and SCD function on a single processor for cached noncoherent memory so that
parallel programs can be run on uniprocessor systems that do not support cached
coherent memory access types.

Implementation Notes:
The block of memory that is “locked” for LLD/SCD is typically the largest cache line
in use.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-125

SD
31

Store Doubleword
26 25

SD
111111
6

21 20

16 15

base

offset

Format:
Purpose:

SD rt, offset(base)

Description:

memory[base+offset] ← rt

MIPS III

To store a doubleword to memory.

The 64-bit doubleword in GPR rt is stored in memory at the location specified by the
aligned effective address. The 16-bit signed offset is added to the contents of GPR base
to form the effective address.

Restrictions:
The effective address must be naturally aligned. If any of the three least-significant bits
of the effective address are non-zero, an Address Error exception occurs.
MIPS IV: The low-order 3 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr2..0) ≠ 03 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
datadouble ← GPR[rt]
StoreMemory (uncached, DOUBLEWORD, datadouble, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Address Error
Reserved Instruction

A-126

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SDCz

Store Doubleword From Coprocessor
31

26 25
SDCz
1111zz
6

21 20

16 15

base

offset

MIPS II

Format:

SDC1 rt, offset(base)
SDC2 rt, offset(base)

Purpose:

To store a doubleword from a coprocessor general register to memory.

Description:

memory[base+offset] ← rt

Coprocessor unit zz supplies a 64-bit doubleword which is stored at the memory
location specified by the aligned effective address. The 16-bit signed offset is added to
the contents of GPR base to form the effective address.
The data supplied by each coprocessor is defined by the individual coprocessor
specifications. The usual operation would read the data from coprocessor general
register rt.
Each MIPS architecture level defines up to 4 coprocessor units, numbered 0 to 3 (see
Coprocessor Instructions
on page A-11). The opcodes corresponding to coprocessors
that are not defined by an architecture level may be used for other instructions.

Restrictions:
Access to the coprocessors is controlled by system software. Each coprocessor has a
“coprocessor usable” bit in the System Control coprocessor. The usable bit must be set
for a user program to execute a coprocessor instruction. If the usable bit is not set, an
attempt to execute the instruction will result in a Coprocessor Unusable exception. An
unimplemented coprocessor must never be enabled. The result of executing this
instruction for an unimplemented coprocessor when the usable bit is set, is undefined.
This instruction is not defined for coprocessor 0, the System Control coprocessor, and
the opcode may be used for other instructions.
The effective address must be naturally aligned. If any of the three least-significant bits
of the effective address are non-zero, an Address Error exception occurs.
MIPS IV: The low-order 3 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:

32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr2..0) ≠ 03 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
datadouble ← COP_SD(z, rt)
StoreMemory (uncached, DOUBLEWORD, datadouble, pAddr, vAddr, DATA)

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-127

SDCz
Operation:

Store Doubleword From Coprocessor
64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr2..0) ≠ 03 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
datadouble ← COP_SD(z, rt)
StoreMemory (uncached, DOUBLEWORD, datadouble, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Address Error
Reserved Instruction
Coprocessor Unusable

A-128

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SDL

Store Doubleword Left
31

26 25
SDL
101100
6

21 20

16 15

base

offset

MIPS III

Format:
Purpose:

SDL rt, offset(base)

Description:

memory[base+offset] ← Some_Bytes_From rt

To store the most-significant part of a doubleword to an unaligned
memory address.

The 16-bit signed offset is added to the contents of GPR base to form an effective address
(EffAddr). EffAddr is the address of the most-significant of eight consecutive bytes
forming a doubleword in memory (DW) starting at an arbitrary byte boundary. A part
of DW, the most-significant one to eight bytes, is in the aligned doubleword containing
EffAddr. The same number of most-significant (left) bytes of GPR rt are stored into
these bytes of DW.
The figure below illustrates this operation for big-endian byte ordering. The eight
consecutive bytes in 2..9 form an unaligned doubleword starting at location 2. A part
of DW, six bytes, is contained in the aligned doubleword containing the mostsignificant byte at 2. First, SDL stores the six most-significant bytes of the source
register into these bytes in memory. Next, the complementary SDR instruction stores
the remainder of DW.
Doubleword at byte 2 in memory (big-endian) - each memory byte contains its address
most
0

— significance —
4

least
8

13 14 15

Memory

C D E F G H

...

GPR 24

After executing
0

SDL $24,2($0)
Then after

Figure A-6

...

SDR $24,9($0)

Unaligned Doubleword Store with SDL and SDR

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-129

SDL

Store Doubleword Left

The bytes stored from the source register to memory depend on both the offset of the
effective address within an aligned doubleword, i.e. the low three bits of the address
(vAddr2..0), and the current byte ordering mode of the processor (big- or little-endian).
The table below shows the bytes stored for every combination of offset and byte
ordering.
Table A-33

Bytes Stored by SDL Instruction

Initial Memory contents and byte offsets

Contents of
Source Register

most

— significance —

least

7 ← big-

most

A B C D E F G H

0 ← little-endian

— significance —

least

Memory contents after instruction (shaded is unchanged)
Little-endian byte ordering

Big-endian byte ordering

vAddr2..0

A B C D E F G H

A B C D E F G

A B

A B C D E F

A B C

A B C D E

A B C D

A B C D E

A B C

A B C D E F

A B

A B C D E F G

A B C D E F G H

Restrictions:
None

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..3 || (pAddr2..0 xor ReverseEndian3)
If BigEndianMem = 0 then
pAddr ← pAddr(PSIZE-1)..3 || 03
endif
byte ← vAddr2..0 xor BigEndianCPU3
datadouble ← 056–8*byte || GPR[rt]63..56–8*byte
StoreMemory (uncached, byte, datadouble, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Bus Error
Address Error
Reserved Instruction
A-130

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SDR

Store Doubleword Right
31

26 25
SDR
101101
6

21 20

16 15

base

offset

MIPS III

Format:
Purpose:

SDR rt, offset(base)

Description:

memory[base+offset] ← Some_Bytes_From rt

To store the least-significant part of a doubleword to an unaligned
memory address.

The 16-bit signed offset is added to the contents of GPR base to form an effective address
(EffAddr). EffAddr is the address of the least-significant of eight consecutive bytes
forming a doubleword in memory (DW) starting at an arbitrary byte boundary. A part
of DW, the least-significant one to eight bytes, is in the aligned doubleword containing
EffAddr. The same number of least-significant (right) bytes of GPR rt are stored into
these bytes of DW.
The figure below illustrates this operation for big-endian byte ordering. The eight
consecutive bytes in 2..9 form an unaligned doubleword starting at location 2. A part
of DW, two bytes, is contained in the aligned doubleword containing the leastsignificant byte at 9. First, SDR stores the two least-significant bytes of the source
register into these bytes in memory. Next, the complementary SDL stores the
remainder of DW.
Doubleword at byte 2 in memory, big-endian byte order, - each mem byte contains its address
most
0

— significance —
4

least
8

13 14 15

Memory

C D E F G H

...

GPR 24

After executing
0

SDR $24,9($0)
Then after

Figure A-7

...

SDL $24,2($0)

Unaligned Doubleword Store with SDR and SDL

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-131

SDR

Store Doubleword Right

Bytes Stored by SDR Instruction

Initial Memory contents and byte offsets

Contents of
Source Register

most

— significance —

least

7 ← big-

most

A B C D E F G H

0 ¨ little-endian

— significance —

least

Memory contents after instruction (shaded is unchanged)
Big-endian byte ordering

vAddr2..0

Little-endian byte ordering

A B C D E F G H

G H

B C D E F G H

F G H

C D E F G H

E F G H

D E F G H

E F G H

C D E F G H

F G H

B C D E F G H

G H

A B C D E F G H

Restrictions:
None

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..3 || (pAddr2..0 xor ReverseEndian3)
If BigEndianMem = 0 then
pAddr ← pAddr(PSIZE-1)..3 || 03
endif
byte ← vAddr1..0 xor BigEndianCPU3
datadouble ← GPR[rt]63–8*byte || 08*byte
StoreMemory (uncached, DOUBLEWORD-byte, datadouble, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Bus Error
Address Error
Reserved Instruction
A-132

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Store Halfword
31

26 25
SH
101001
6

21 20

16 15

base

offset

Format:
Purpose:

SH rt, offset(base)

Description:

memory[base+offset] ← rt

MIPS I

To store a halfword to memory.

The least-significant 16-bit halfword of register rt is stored in memory at the location
specified by the aligned effective address. The 16-bit signed offset is added to the
contents of GPR base to form the effective address.

Operation:

32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr0) ≠ 0 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddrPSIZE-1..2 || (pAddr1..0 xor (ReverseEndian || 0))
byte ← vAddr1..0 xor (BigEndianCPU || 0)
dataword ← GPR[rt]31–8*byte..0 || 08*byte
StoreMemory (uncached, HALFWORD, dataword, pAddr, vAddr, DATA)

Operation:

64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr0) ≠ 0 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian2 || 0))
byte ← vAddr2..0 xor (BigEndianCPU2 || 0)
datadouble ← GPR[rt]63–8*byte..0 || 08*byte
StoreMemory (uncached, HALFWORD, datadouble, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Address Error

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-133

SLL
31

Shift Word Left Logical
26 25

SPECIAL
000000
6

21 20

0
00000
5

Format:
Purpose:

SLL rd, rt, sa

Description:

rd ← rt << sa

16 15

11 10

SLL
000000
6

MIPS I

To left shift a word by a fixed number of bits.

The contents of the low-order 32-bit word of GPR rt are shifted left, inserting zeroes
into the emptied bits; the word result is placed in GPR rd. The bit shift count is
specified by sa. If rd is a 64-bit register, the result word is sign-extended.

Restrictions:
None

Operation:
s
← sa
temp ← GPR[rt](31-s)..0 || 0s
GPR[rd]← sign_extend(temp)

Exceptions:
None

Programming Notes:
Unlike nearly all other word operations the input operand does not have to be a
properly sign-extended word value to produce a valid sign-extended 32-bit result. The
result word is always sign extended into a 64-bit destination register; this instruction
with a zero shift amount truncates a 64-bit value to 32 bits and sign extends it.
Some assemblers, particularly 32-bit assemblers, treat this instruction with a shift
amount of zero as a NOP and either delete it or replace it with an actual NOP.

A-134

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Shift Word Left Logical Variable
31

26 25
SPECIAL
000000
6

SLLV

21 20

16 15

11 10

Format:
Purpose:

SLLV rd, rt, rs

Description:

rd ← rt << rs

0
00000
5

0
SLLV
000100
6

MIPS I

To left shift a word by a variable number of bits.

The contents of the low-order 32-bit word of GPR rt are shifted left, inserting zeroes
into the emptied bits; the result word is placed in GPR rd. The bit shift count is
specified by the low-order five bits of GPR rs. If rd is a 64-bit register, the result word
is sign-extended.

Restrictions:
None

Operation:
s
← GP[rs]4..0
temp ← GPR[rt](31-s)..0 || 0s
GPR[rd]← sign_extend(temp)

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-135

SLT
31

Set On Less Than
26 25

SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

SLT rd, rs, rt

Description:

rd ← (rs < rt)

0
00000
5

0
SLT
101010
6

MIPS I

To record the result of a less-than comparison.

Compare the contents of GPR rs and GPR rt as signed integers and record the Boolean
result of the comparison in GPR rd. If GPR rs is less than GPR rt the result is 1 (true),
otherwise 0 (false).
The arithmetic comparison does not cause an Integer Overflow exception.

Restrictions:
None

Operation:
if GPR[rs] < GPR[rt] then
GPR[rd] ← 0GPRLEN-1 || 1
else
GPR[rd] ← 0GPRLEN
endif

Exceptions:
None

A-136

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SLTI

Set on Less Than Immediate
31

26 25
SLTI
001010
6

21 20

16 15

immediate

Format:
Purpose:

SLTI rt, rs, immediate

Description:

rt ← (rs < immediate)

MIPS I

To record the result of a less-than comparison with a constant.

Compare the contents of GPR rs and the 16-bit signed immediate as signed integers and
record the Boolean result of the comparison in GPR rt. If GPR rs is less than immediate
the result is 1 (true), otherwise 0 (false).
The arithmetic comparison does not cause an Integer Overflow exception.

Restrictions:
None

Operation:
if GPR[rs] < sign_extend(immediate) then
GPR[rd] ← 0GPRLEN-1|| 1
else
GPR[rd] ← 0GPRLEN
endif

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-137

SLTIU
31

Set on Less Than Immediate Unsigned

26 25
SLTIU
001011
6

21 20

16 15

immediate

Format:
Purpose:

SLTIU rt, rs, immediate

Description:

rt ← (rs < immediate)

MIPS I

To record the result of an unsigned less-than comparison with a constant.

Compare the contents of GPR rs and the sign-extended 16-bit immediate as unsigned
integers and record the Boolean result of the comparison in GPR rt. If GPR rs is less
than immediate the result is 1 (true), otherwise 0 (false).
Because the 16-bit immediate is sign-extended before comparison, the instruction is able
to represent the smallest or largest unsigned numbers. The representable values are at
the minimum [0, 32767] or maximum [max_unsigned-32767, max_unsigned] end of
the unsigned range.
The arithmetic comparison does not cause an Integer Overflow exception.

Restrictions:
None

Operation:
if (0 || GPR[rs]) < (0 || sign_extend(immediate)) then
GPR[rd] ← 0GPRLEN-1 || 1
else
GPR[rd] ← 0GPRLEN
endif

Exceptions:
None

A-138

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SLTU

Set on Less Than Unsigned
31

26 25
SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

SLTU rd, rs, rt

Description:

rd ← (rs < rt)

0
00000
5

SLTU
101011
6

MIPS I

To record the result of an unsigned less-than comparison.

Compare the contents of GPR rs and GPR rt as unsigned integers and record the
Boolean result of the comparison in GPR rd. If GPR rs is less than GPR rt the result is
1 (true), otherwise 0 (false).
The arithmetic comparison does not cause an Integer Overflow exception.

Restrictions:
None

Operation:
if (0 || GPR[rs]) < (0 || GPR[rt]) then
GPR[rd] ← 0GPRLEN-1 || 1
else
GPR[rd] ← 0GPRLEN
endif

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-139

SRA
31

Shift Word Right Arithmetic
26 25

SPECIAL
000000
6

21 20

0
00000
5

Format:
Purpose:

SRA rd, rt, sa

Description:

rd ← rt >> sa

16 15

11 10

SRA
000011
6

MIPS I

To arithmetic right shift a word by a fixed number of bits.
(arithmetic)

The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the
sign-bit (bit 31) in the emptied bits; the word result is placed in GPR rd. The bit shift
count is specified by sa. If rd is a 64-bit register, the result word is sign-extended.

Restrictions:
On 64-bit processors, if GPR rt does not contain a sign-extended 32-bit value
(bits 63..31 equal) then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rt])) then UndefinedResult() endif
s
← sa
temp ← (GPR[rt]31)s || GPR[rt]31..s
GPR[rd]← sign_extend(temp)

Exceptions:
None

A-140

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Shift Word Right Arithmetic Variable
31

26 25
SPECIAL
000000
6

21 20

SRAV

16 15

11 10

Format:
Purpose:

SRAV rd, rt, rs

Description:

rd ← rt >> rs

0
00000
5

SRAV
000111
6

MIPS I

To arithmetic right shift a word by a variable number of bits.
(arithmetic)

The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the
sign-bit (bit 31) in the emptied bits; the word result is placed in GPR rd. The bit shift
count is specified by the low-order five bits of GPR rs. If rd is a 64-bit register, the result
word is sign-extended.

Restrictions:
On 64-bit processors, if GPR rt does not contain a sign-extended 32-bit value
(bits 63..31 equal) then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rt])) then UndefinedResult() endif
s
← GPR[rs]4..0
temp ← (GPR[rt]31)s || GPR[rt]31..s
GPR[rd]← sign_extend(temp)

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-141

SRL
31

Shift Word Right Logical
26 25

SPECIAL
000000
6

21 20

16 15

11 10

0
00000

Format:
Purpose:

SRL rd, rt, sa

Description:

rd ← rt >> sa

SRL
000010
6

MIPS I

To logical right shift a word by a fixed number of bits.
(logical)

The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros
into the emptied bits; the word result is placed in GPR rd. The bit shift count is
specified by sa. If rd is a 64-bit register, the result word is sign-extended.

Restrictions:
On 64-bit processors, if GPR rt does not contain a sign-extended 32-bit value
(bits 63..31 equal) then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rt])) then UndefinedResult() endif
s
← sa
temp ← 0s || GPR[rt]31..s
GPR[rd]← sign_extend(temp)

Exceptions:
None

A-142

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Shift Word Right Logical Variable

SRLV

16 15

26 25
SPECIAL
000000
6

21 20

11 10

Format:
Purpose:

SRLV rd, rt, rs

Description:

rd ← rt >> rs

0
00000
5

SRLV
000110
6

MIPS I

To logical right shift a word by a variable number of bits.
(logical)

The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros
into the emptied bits; the word result is placed in GPR rd. The bit shift count is
specified by the low-order five bits of GPR rs. If rd is a 64-bit register, the result word
is sign-extended.

Restrictions:
On 64-bit processors, if GPR rt does not contain a sign-extended 32-bit value
(bits 63..31 equal) then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rt])) then UndefinedResult() endif
s
← GPR[rs]4..0
temp ← 0s || GPR[rt]31..s
GPR[rd]← sign_extend(temp)

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-143

SUB
31

Subtract Word
26 25

SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

SUB rd, rs, rt

Description:

rd ← rs - rt

0
00000
5

SUB
100010
6

MIPS I

To subtract 32-bit integers. If overflow occurs, then trap.

The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs to
produce a 32-bit result. If the subtraction results in 32-bit 2’s complement arithmetic
overflow then the destination register is not modified and an Integer Overflow
exception occurs. If it does not overflow, the 32-bit result is placed into GPR rd.

Restrictions:
On 64-bit processors, if either GPR rt or GPR rs do not contain sign-extended 32-bit
values (bits 63..31 equal), then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
temp ← GPR[rs] - GPR[rt]
if (32_bit_arithmetic_overflow) then
SignalException(IntegerOverflow)
else
GPR[rd] ←temp
endif

Exceptions:
Integer Overflow

Programming Notes:
SUBU performs the same arithmetic operation but, does not trap on overflow.

A-144

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Subtract Unsigned Word
31

26 25
SPECIAL
000000
6

SUBU

21 20

16 15

11 10

Format:
Purpose:

SUBU rd, rs, rt

Description:

rd ← rs - rt

0
00000
5

0
SUBU
100011
6

MIPS I

To subtract 32-bit integers.

The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs and the
32-bit arithmetic result is placed into GPR rd.
No integer overflow exception occurs under any circumstances.

Restrictions:
On 64-bit processors, if either GPR rt or GPR rs do not contain sign-extended 32-bit
values (bits 63..31 equal), then the result of the operation is undefined.

Operation:
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
temp ←GPR[rs] - GPR[rt]
GPR[rd] ←temp

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-145

SW
31

Store Word
26 25

SW
101011
6

21 20

16 15

base

offset

Format:
Purpose:

SW rt, offset(base)

Description:

memory[base+offset] ← rt

MIPS I

To store a word to memory.

The least-significant 32-bit word of register rt is stored in memory at the location
specified by the aligned effective address. The 16-bit signed offset is added to the
contents of GPR base to form the effective address.

Operation:

32- bit Processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr1..0) ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
dataword ← GPR[rt]
StoreMemory (uncached, WORD, dataword, pAddr, vAddr, DATA)

Operation:

64- bit Processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr1..0) ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02)
byte ← vAddr2..0 xor (BigEndianCPU || 02)
datadouble ← GPR[rt]63-8*byte || 08*byte
StoreMemory (uncached, WORD, datadouble, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Address Error

A-146

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SWCz

Store Word From Coprocessor
31

26 25
SWCz
1110zz
6

21 20

16 15

base

offset

MIPS I

Format:

SWC1 rt, offset(base)
SWC2 rt, offset(base)
SWC3 rt, offset(base)

Purpose:

To store a word from a coprocessor general register to memory.

Description:

memory[base+offset] ← rt

Coprocessor unit zz supplies a 32-bit word which is stored at the memory location
specified by the aligned effective address. The 16-bit signed offset is added to the
contents of GPR base to form the effective address.
The data supplied by each coprocessor is defined by the individual coprocessor
specifications. The usual operation would read the data from coprocessor general
register rt.
Each MIPS architecture level defines up to 4 coprocessor units, numbered 0 to 3 (see
Coprocessor Instructions
on page A-11). The opcodes corresponding to coprocessors
that are not defined by an architecture level may be used for other instructions.

Restrictions:
Access to the coprocessors is controlled by system software. Each coprocessor has a
“coprocessor usable” bit in the System Control coprocessor. The usable bit must be set
for a user program to execute a coprocessor instruction. If the usable bit is not set, an
attempt to execute the instruction will result in a Coprocessor Unusable exception. An
unimplemented coprocessor must never be enabled. The result of executing this
instruction for an unimplemented coprocessor when the usable bit is set, is undefined.
This instruction is not available for coprocessor 0, the System Control coprocessor, and
the opcode may be used for other instructions.
The effective address must be naturally aligned. If either of the two least-significant
bits of the address are non-zero, an Address Error exception occurs.
MIPS IV: The low-order 2 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:

32- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr1..0) ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
dataword ← COP_SW (z, rt)
StoreMemory (uncached, WORD, dataword, pAddr, vAddr, DATA)

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-147

SWCz
Operation:

Store Word From Coprocessor
64- bit processors

vAddr ← sign_extend(offset) + GPR[base]
if (vAddr1..0) ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02)
byte ← vAddr2..0 xor (BigEndianCPU || 02)
dataword← COP_SW (z, rt)
datadouble ← 032-8*byte || dataword || 08*byte
StoreMemory (uncached, WORD, datadouble, pAddr, vAddr DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Address Error
Reserved Instruction
Coprocessor Unusable

A-148

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SWL

Store Word Left
31

26 25
SWL
101010
6

21 20

16 15

base

offset

MIPS I

Format:
Purpose:

SWL rt, offset(base)

Description:

memory[base+offset] ← rt

To store the most-significant part of a word to an unaligned memory
address.

The 16-bit signed offset is added to the contents of GPR base to form an effective address
(EffAddr). EffAddr is the address of the most-significant of four consecutive bytes
forming a word in memory (W) starting at an arbitrary byte boundary. A part of W, the
most-significant one to four bytes, is in the aligned word containing EffAddr. The same
number of the most-significant (left) bytes from the word in GPR rt are stored into
these bytes of W.
If GPR rt is a 64-bit register, the source word is the low word of the register.
Figures A-4 illustrates this operation for big-endian byte ordering for 32-bit and 64-bit
registers. The four consecutive bytes in 2..5 form an unaligned word starting at
location 2. A part of W, two bytes, is contained in the aligned word containing the
most-significant byte at 2. First, SWL stores the most-significant two bytes of the lowword from the source register into these two bytes in memory. Next, the
complementary SWR stores the remainder of the unaligned word.
Word at byte 2 in memory, big-endian byte order, - each mem byte contains its address
most

— significance —

least

64-bit GPR 24

...

32-bit GPR 24

Figure A-8

Memory

: Initial contents

F G H

...

After executing SWL $24,2($0)

...

Then after SWR $24,5($0)

Unaligned Word Store using SWL and SWR.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-149

SWL

Store Word Left

The bytes stored from the source register to memory depend on both the offset of the
effective address within an aligned word, i.e. the low two bits of the address
(vAddr1..0), and the current byte ordering mode of the processor (big- or little-endian).
The table below shows the bytes stored for every combination of offset and byte
ordering.
Table A-35

Bytes Stored by SWL Instruction

Memory contents and byte offsets
0

3 ← big-endian

0 ← little-endian

most

Initial contents of Dest Register
64-bit register

offset (vAddr1..0)

most

least

— significance —

32-bit register

H
least

— significance —
Memory contents after instruction (shaded is unchanged)
Big-endian
byte ordering

Operation:

Little-endian
byte ordering

vAddr1..0

32- bit Processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..2 || (pAddr1..0 xor ReverseEndian2)
If BigEndianMem = 0 then
pAddr ← pAddr(PSIZE-1)..2 || 02
endif
byte ← vAddr1..0 xor BigEndianCPU2
dataword ← 024–8*byte || GPR[rt]31..24–8*byte
StoreMemory (uncached, byte, dataword, pAddr, vAddr, DATA)

A-150

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SWL

Store Word Left
Operation:

64- bit Processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..3 || (pAddr2..0 xor ReverseEndian3)
If BigEndianMem = 0 then
pAddr ← pAddr(PSIZE-1)..2 || 02
endif
byte ← vAddr1..0 xor BigEndianCPU2
if (vAddr2 xor BigEndianCPU) = 0 then
datadouble ← 032 || 024-8*byte || GPR[rt]31..24-8*byte
else
datadouble ← 024-8*byte || GPR[rt]31..24-8*byte || 032
endif
StoreMemory(uncached, byte, datadouble, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Bus Error
Address Error

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-151

SWR
31

Store Word Right
26 25

SWR
101110
6

21 20

16 15

base

offset

MIPS I

Format:
Purpose:

SWR rt, offset(base)

Description:

memory[base+offset] ← rt

To store the least-significant part of a word to an unaligned memory
address.

The 16-bit signed offset is added to the contents of GPR base to form an effective address
(EffAddr). EffAddr is the address of the least-significant of four consecutive bytes
forming a word in memory (W) starting at an arbitrary byte boundary. A part of W, the
least-significant one to four bytes, is in the aligned word containing EffAddr. The same
number of the least-significant (right) bytes from the word in GPR rt are stored into
these bytes of W.
If GPR rt is a 64-bit register, the source word is the low word of the register.
Figures A-4 illustrates this operation for big-endian byte ordering for 32-bit and 64-bit
registers. The four consecutive bytes in 2..5 form an unaligned word starting at
location 2. A part of W, two bytes, is contained in the aligned word containing the leastsignificant byte at 5. First, SWR stores the least-significant two bytes of the low-word
from the source register into these two bytes in memory. Next, the complementary
SWL stores the remainder of the unaligned word.
Word at byte 2 in memory, big-endian byte order, - each mem byte contains its address
most

— significance —

least

64-bit GPR 24

...

32-bit GPR 24

Figure A-9

A-152

Memory

: Initial contents

F G H

...

After executing SWR $24,5($0)

...

Then after SWL $24,2($0)

Unaligned Word Store using SWR and SWL.

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SWR

Store Word Right

The bytes stored from the source register to memory depend on both the offset of the
effective address within an aligned word, i.e. the low two bits of the address
(vAddr1..0), and the current byte ordering mode of the processor (big- or little-endian).
The tabel below shows the bytes stored for every combination of offset and byte
ordering.
Table A-36

Bytes Stored by SWR Instruction

Memory contents and byte offsets
0

3 ← big-endian

0 ← little-endian

most

Initial contents of Dest Register
64-bit register

offset (vAddr1..0)

most

least

— significance —

32-bit register

H
least

— significance —
Memory contents after instruction (shaded is unchanged)
Big-endian
byte ordering

Little-endian
byte ordering

vAddr1..0

Restrictions:
None

Operation:

32- bit Processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..2 || (pAddr1..0 xor ReverseEndian2)
BigEndianMem = 0 then
pAddr ← pAddr(PSIZE-1)..2 || 02
endif
byte ← vAddr1..0 xor BigEndianCPU2
dataword ← GPR[rt]31–8*byte || 08*byte
StoreMemory (uncached, WORD-byte, dataword, pAddr, vAddr, DATA)

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-153

SWR
Operation:

Store Word Right
64- bit Processors

vAddr ← sign_extend(offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..3 || (pAddr2..0 xor ReverseEndian3)
If BigEndianMem = 0 then
pAddr ← pAddr(PSIZE-1)..2 || 02
endif
byte ← vAddr1..0 xor BigEndianCPU2
if (vAddr2 xor BigEndianCPU) = 0 then
datadouble ← 032 || GPR[rt]31-8*byte..0 || 08*byte
else
datadouble ← GPR[rt]31-8*byte..0 || 08*byte || 032
endif
StoreMemory(uncached, WORD-byte, datadouble, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Bus Error
Address Error

A-154

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SYNC

Synchronize Shared Memory
31

11 10

26 25
SPECIAL
000000
6

Format:
Purpose:

0
00 0000 0000 0000 0
15

SYNC

(stype = 0 implied)

6
stype
5

0
SYNC
001111
6

MIPS II

To order loads and stores to shared memory in a multiprocessor system.

Description:
To serve a broad audience, two descriptions are given. A simple description of SYNC
that appeals to intuition is followed by a precise and detailed description.
A Simple Description:
SYNC affects only uncached and cached coherent loads and stores. The loads and
stores that occur prior to the SYNC must be completed before the loads and stores after
the SYNC are allowed to start.
Loads are completed when the destination register is written. Stores are completed
when the stored value is visible to every other processor in the system.
A Precise Description:
If the stype field has a value of zero, every synchronizable load and store that occurs in
the instruction stream prior to the SYNC instruction must be globally performed before
any synchronizable load or store that occurs after the SYNC may be performed with
respect to any other processor or coherent I/O module.
Sync does not guarantee the order in which instruction fetches are performed.
The stype values 1-31 are reserved; they produce the same result as the value zero.
Synchronizable: A load or store instruction is synchronizable if the load or store occurs
to a physical location in shared memory using a virtual location with a memory access
type of either uncached or cached coherent. Shared memory is memory that can be
accessed by more than one processor or by a coherent I/O system module.
Memory Access Types

on page A-12 contains information on memory access types.

Performed load: A load instruction is performed when the value returned by the load
has been determined. The result of a load on processor A has been determined with
respect to processor or coherent I/O module B when a subsequent store to the location
by B cannot affect the value returned by the load. The store by B must use the same
memory access type as the load.
Performed store: A store instruction is performed when the store is observable. A store
on processor A is observable with respect to processor or coherent I/O module B when
a subsequent load of the location by B returns the value written by the store. The load
by B must use the same memory access type as the store.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-155

SYNC

Synchronize Shared Memory

Globally performed load: A load instruction is globally performed when it is performed
with respect to all processors and coherent I/O modules capable of storing to the
location.
Globally performed store: A store instruction is globally performed when it is globally
observable. It is globally observable when it observable by all processors and I/O
modules capable of loading from the location.
Coherent I/O module: A coherent I/O module is an Input/Output system component
that performs coherent Direct Memory Access (DMA). It reads and writes memory
independently as though it were a processor doing loads and stores to locations with
a memory access type of cached coherent.

Restrictions:
The effect of SYNC on the global order of the effects of loads and stores for memory
access types other than uncached and cached coherent is not defined.

Operation:
SyncOperation(stype)

Exceptions:
Reserved Instruction

Programming Notes:
A processor executing load and store instructions observes the effects of the loads and
stores that use the same memory access type in the order that they occur in the
instruction stream; this is known as program order. A parallel program has multiple
instruction streams that can execute at the same time on different processors. In
multiprocessor (MP) systems, the order in which the effects of loads and stores are
observed by other processors, the global order of the loads and stores, determines the
actions necessary to reliably share data in parallel programs.
When all processors observe the effects of loads and stores in program order, the
system is strongly ordered. On such systems, parallel programs can reliably share data
without explicit actions in the programs. For such a system, SYNC has the same effect
as a NOP. Executing SYNC on such a system is not necessary, but is also not an error.
If a multiprocessor system is not strongly ordered, the effects of load and store
instructions executed by one processor may be observed out of program order by other
processors. On such systems, parallel programs must take explicit actions in order to
reliably share data. At critical points in the program, the effects of loads and stores
from an instruction stream must occur in the same order for all processors. SYNC
separates the loads and stores executed on the processor into two groups and the
effects of these groups are seen in program order by all processors. The effect of all
loads and stores in one group is seen by all processors before the effect of any load or
store in the other group. In effect, SYNC causes the system to be strongly ordered for
the executing processor at the instant that the SYNC is executed.

A-156

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SYNC

Synchronize Shared Memory

Many MIPS-based multiprocessor systems are strongly ordered or have a mode in
which they operate as strongly ordered for at least one memory access type. The MIPS
architecture also permits MP systems that are not strongly ordered. SYNC enables the
reliable use of shared memory on such systems. A parallel program that does not use
SYNC will generally not operate on a system that is not strongly ordered, however a
program that does use SYNC will work on both types of systems. System-specific
documentation will describe the actions necessary to reliably share data in parallel
programs for that system.
The behavior of a load or store using one memory access type is undefined if a load or
store was previously made to the same physical location using a different memory
access type. The presence of a SYNC between the references does not alter this
behavior. See page A-13 for a more complete discussion.
SYNC affects the order in which the effects of load and store instructions appears to all
processors; it not generally affect the physical memory-system ordering or
synchronization issues that arise in system programming. The effect of SYNC on
implementation specific aspects of the cached memory system, such as writeback
buffers, is not defined. The effect of SYNC on reads or writes to memory caused by
privileged implementation-specific instructions, such as CACHE, is not defined.
Prefetch operations have no effects detectable by user-mode programs so ordering the
effects of prefetch operations is not meaningful.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-157

SYNC

Synchronize Shared Memory

EXAMPLE : These code fragments show how SYNC can be used to coordinate the
use of shared data between separate writer and reader instruction streams in a
multiprocessor environment. The FLAG location is used by the instruction streams to
determine whether the shared data item DATA is valid. The SYNC executed by
processor A forces the store of DATA to be performed globally before the store to FLAG
is performed. The SYNC executed by processor B ensures that DATA is not read until
after the FLAG value indicates that the shared data is valid.
Processor A (writer)
# Conditions at entry:
# The value 0 has been stored in FLAG and that value is observable by B.
SW

R1, DATA

R2, 1

SYNC
SW

# change shared DATA value
# perform DATA store before performing FLAG store

R2, FLAG

# say that the shared DATA value is valid
Processor B (reader)

R2, 1

R1, FLAG

# get FLAG

BNE

R2, R1, 1B

# if it says that DATA is not valid, poll again

NOP
SYNC
LW

# FLAG value checked before doing DATA reads
R1, DATA

# read (valid) shared DATA values

Implementation Notes:
There may be side effects of uncached loads and stores that affect cached coherent load
and store operations. To permit the reliable use of such side effects, buffered uncached
stores that occur before the SYNC must be written to memory before cached coherent
loads and stores after the SYNC may be performed.

A-158

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

SYSCALL

System Call
31

26 25

SPECIAL
000000
6

Format:
Purpose:

Code
20

0
SYSCALL
0 0 1 1 00
6

MIPS I

SYSCALL
To cause a System Call exception.

Description:
A system call exception occurs, immediately and unconditionally transferring control
to the exception handler.
The code field is available for use as software parameters, but is retrieved by the
exception handler only by loading the contents of the memory word containing the
instruction.

Restrictions:
None

Operation:
SignalException(SystemCall)

Exceptions:
System Call

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-159

TEQ
31

Trap if Equal
26 25

SPECIAL
000000
6

21 20

16 15

code

TEQ
110100
6

MIPS II

Format:
Purpose:

TEQ rs, rt

Description:

if (rs = rt) then Trap

To compare GPRs and do a conditional Trap.

Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is equal to
GPR rt then take a Trap exception.
The contents of the code field are ignored by hardware and may be used to encode
information for system software. To retrieve the information, system software must
load the instruction word from memory.

Restrictions:
None

Operation:
if GPR[rs] = GPR[rt] then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

A-160

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

TEQI

Trap if Equal Immediate
31

26 25
REGIMM
000001
6

21 20
rs
5

16 15

TEQI
01100
5

Format:
Purpose:

TEQI rs, immediate

Description:

if (rs = immediate) then Trap

0
immediate
16

MIPS II

To compare a GPR to a constant and do a conditional Trap.

Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if
GPR rs is equal to immediate then take a Trap exception.

Restrictions:
None

Operation:
if GPR[rs] = sign_extend(immediate) then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-161

TGE
31

Trap if Greater or Equal
26 25

SPECIAL
000000
6

21 20

16 15

code

TGE
110000
6

MIPS II

Format:
Purpose:

TGE rs, rt

Description:

if (rs ≥ rt) then Trap

To compare GPRs and do a conditional Trap.

Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is greater than
or equal to GPR rt then take a Trap exception.
The contents of the code field are ignored by hardware and may be used to encode
information for system software. To retrieve the information, system software must
load the instruction word from memory.

Restrictions:
None

Operation:
if GPR[rs] ≥ GPR[rt] then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

A-162

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

TGEI

Trap if Greater or Equal Immediate
31

26 25
REGIMM
000001
6

21 20
rs
5

16 15

TGEI
01000
5

Format:
Purpose:

TGEI rs, immediate

Description:

if (rs ≥ immediate) then Trap

0
immediate
16

MIPS II

To compare a GPR to a constant and do a conditional Trap.

Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if
GPR rs is greater than or equal to immediate then take a Trap exception.

Restrictions:
None

Operation:
if GPR[rs] ≥ sign_extend(immediate) then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-163

TGEIU
31

Trap If Greater Or Equal Immediate Unsigned

26 25
REGIMM
000001
6

21 20
rs
5

16 15

TGEIU
01001
5

Format:
Purpose:

TGEIU rs, immediate

Description:

if (rs ≥ immediate) then Trap

0
immediate
16

MIPS II

To compare a GPR to a constant and do a conditional Trap.

Compare the contents of GPR rs and the 16-bit sign-extended immediate as unsigned
integers; if GPR rs is greater than or equal to immediate then take a Trap exception.
Because the 16-bit immediate is sign-extended before comparison, the instruction is able
to represent the smallest or largest unsigned numbers. The representable values are at
the minimum [0, 32767] or maximum [max_unsigned-32767, max_unsigned] end of
the unsigned range.

Restrictions:
None

Operation:
if (0 || GPR[rs]) ≥ (0 || sign_extend(immediate)) then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

A-164

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

TGEU

Trap If Greater or Equal Unsigned
31

26 25
SPECIAL
000000
6

21 20

16 15

code

TGEU
110001
6

MIPS II

Format:
Purpose:

TGEU rs, rt

Description:

if (rs ≥ rt) then Trap

To compare GPRs and do a conditional Trap.

Compare the contents of GPR rs and GPR rt as unsigned integers; if GPR rs is greater
than or equal to GPR rt then take a Trap exception.
The contents of the code field are ignored by hardware and may be used to encode
information for system software. To retrieve the information, system software must
load the instruction word from memory.

Restrictions:
None

Operation:
if (0 || GPR[rs]) ≥ (0 || GPR[rt]) then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-165

TLT
31

Trap if Less Than
26 25

SPECIAL
000000
6

21 20

16 15

code

0
TLT
110010
6

MIPS II

Format:
Purpose:

TLT rs, rt

Description:

if (rs < rt) then Trap

To compare GPRs and do a conditional Trap.

Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is less than
GPR rt then take a Trap exception.
The contents of the code field are ignored by hardware and may be used to encode
information for system software. To retrieve the information, system software must
load the instruction word from memory.

Restrictions:
None

Operation:
if GPR[rs] < GPR[rt] then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

A-166

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

TLTI

Trap if Less Than Immediate
31

26 25

21 20

16 15

REGIMM
000001

TLTI
01010

immediate

Format:
Purpose:

TLTI rs, immediate

Description:

if (rs < immediate) then Trap

MIPS II

To compare a GPR to a constant and do a conditional Trap.

Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if
GPR rs is less than immediate then take a Trap exception.

Restrictions:
None

Operation:
if GPR[rs] < sign_extend(immediate) then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-167

TLTIU
31

Trap if Less Than Immediate Unsigned
26 25

REGIMM
000001
6

21 20
rs
5

16 15

TLTIU
01011
5

Format:
Purpose:

TLTIU rs, immediate

Description:

if (rs < immediate) then Trap

0
immediate
16

MIPS II

To compare a GPR to a constant and do a conditional Trap.

Compare the contents of GPR rs and the 16-bit sign-extended immediate as unsigned
integers; if GPR rs is less than immediate then take a Trap exception.
Because the 16-bit immediate is sign-extended before comparison, the instruction is able
to represent the smallest or largest unsigned numbers. The representable values are at
the minimum [0, 32767] or maximum [max_unsigned-32767, max_unsigned] end of
the unsigned range.

Restrictions:
None

Operation:
if (0 || GPR[rs]) < (0 || sign_extend(immediate)) then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

A-168

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

TLTU

Trap if Less Than Unsigned
31

26 25
SPECIAL
000000
6

21 20

16 15

code

0
TLTU
110011
6

MIPS II

Format:
Purpose:

TLTU rs, rt

Description:

if (rs < rt) then Trap

To compare GPRs and do a conditional Trap.

Compare the contents of GPR rs and GPR rt as unsigned integers; if GPR rs is less than
GPR rt then take a Trap exception.
The contents of the code field are ignored by hardware and may be used to encode
information for system software. To retrieve the information, system software must
load the instruction word from memory.

Restrictions:
None

Operation:
if (0 || GPR[rs]) < (0 || GPR[rt]) then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-169

TNE
31

Trap if Not Equal
26 25

SPECIAL
000000
6

21 20

16 15

code

0
TNE
110110
6

MIPS II

Format:
Purpose:

TNE rs, rt

Description:

if (rs ≠ rt) then Trap

To compare GPRs and do a conditional Trap.

Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is not equal
to GPR rt then take a Trap exception.
The contents of the code field are ignored by hardware and may be used to encode
information for system software. To retrieve the information, system software must
load the instruction word from memory.

Restrictions:
None

Operation:
if GPR[rs] ≠ GPR[rt] then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

A-170

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

TNEI

Trap if Not Equal Immediate
31

26 25
REGIMM
000001
6

21 20
rs
5

16 15

TNEI
01110
5

Format:
Purpose:

TNEI rs, immediate

Description:

if (rs ≠ immediate) then Trap

0
immediate
16

MIPS II

To compare a GPR to a constant and do a conditional Trap.

Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if
GPR rs is not equal to immediate then take a Trap exception.

Restrictions:
None

Operation:
if GPR[rs] ≠ sign_extend(immediate) then
SignalException(Trap)
endif

Exceptions:
Reserved Instruction
Trap

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-171

XOR
31

Exclusive OR
26 25

SPECIAL
000000
6

21 20

16 15

11 10

Format:
Purpose:

XOR rd, rs, rt

Description:

rd ← rs XOR rt

0
00000
5

0
XOR
100110
6

MIPS I

To do a bitwise logical EXCLUSIVE OR.

Combine the contents of GPR rs and GPR rt in a bitwise logical exclusive OR operation
and place the result into GPR rd.

Restrictions:
None

Operation:
GPR[rd] ← GPR[rs] xor GPR[rt]

Exceptions:
None

A-172

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

XORI

Exclusive OR Immediate
31

26 25
XORI
001110
6

21 20

16 15

immediate

Format:
Purpose:

XORI rt, rs, immediate

Description:

rt ← rs XOR immediate

MIPS I

To do a bitwise logical EXCLUSIVE OR with a constant.

Combine the contents of GPR rs and the 16-bit zero-extended immediate in a bitwise
logical exclusive OR operation and place the result into GPR rt.

Restrictions:
None

Operation:
GPR[rt] ← GPR[rs] xor zero_extend(immediate)

Exceptions:
None

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-173

A
A7

CPU Instruction Formats
A CPU instruction is a single 32-bit aligned word. The major instruction formats
are shown in Figure A-10.
I-Type (Immediate).
31

26 25

21 20

16 15

opcode

offset

J-Type (Jump).
31

26 25

opcode

instr_index

R-Type (Register).
31

26 25

21 20

16 15

opcode

function

opcode

6-bit primary operation code

5-bit destination register specifier

5-bit source register specifier

5-bit target (source/destination) register specifier or used to
specify functions within the primary opcode value REGIMM

immediate

16-bit signed immediate used for: logical operands, arithmetic
signed operands, load/store address byte offsets, PC-relative
branch signed instruction displacement

instr_index

26-bit index shifted left two bits to supply the low-order 28 bits of
the jump target address.

5-bit shift amount

function

6-bit function field used to specify functions within the primary
operation code value SPECIAL.
Figure A-10

A-174

11 10

CPU Instruction Formats

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

CPU Instruction Encoding

This section describes the encoding of user-level, i.e. non-privileged, CPU
instructions for the four levels of the MIPS architecture, MIPS I through MIPS IV. Each
architecture level includes the instructions in the previous level;† MIPS IV includes all
instructions in MIPS I, MIPS II, and MIPS III. This section presents eight different views of
the instruction encoding.
•

Separate encoding tables for each architecture level.

•

A MIPS IV encoding table showing the architecture level at which each
opcode was originally defined and subsequently modified (if modified).

•

Separate encoding tables for each architecture revision showing the
changes made during that revision.

A 8.1 Instruction Decode
Instruction field names are printed in bold in this section.
The primary opcode field is decoded first. Most opcode values completely
specify an instruction that has an immediate value or offset. Opcode values that do not
specify an instruction specify an instruction class. Instructions within a class are further
specified by values in other fields. The opcode values SPECIAL and REGIMM specify
instruction classes. The COP0, COP1, COP2, COP3, and COP1X instruction classes are not
CPU instructions; they are discussed in section A 8.3.
A 8.1.1

SPECIAL Instruction Class

The opcode =SPECIAL instruction class encodes 3-register computational
instructions, jump register, and some special purpose instructions. The class is further
decoded by examining the format field. The format values fully specify the CPU
instructions; the MOVCI instruction class is not a CPU instruction class.
A 8.1.2

REGIMM Instruction Class

The opcode =REGIMM instruction class encodes conditional branch and trap
immediate instructions. The class is further decode, and the instructions fully specified, by
examining the rt field.

A 8.2 Instruction Subsets of MIPS III and MIPS IV Processors.
MIPS III processors, such as the R4000, R4200, R4300, R4400, and R4600, have a
processor mode in which only the MIPS II instructions are valid. The MIPS II encoding
table describes the MIPS II-only mode except that the Coprocessor 3 instructions (COP3,
LWC3, SWC3, LDC3, SDC3) are not available and cause a Reserved Instruction exception.

† An exception to this rule is that the reserved, but never implemented, Coprocessor 3
instructions were removed or changed to another use starting in MIPS III.
CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-175

MIPS IV processors, such as the R8000 and R10000, have processor modes in which
only the MIPS II or MIPS III instructions are valid. The MIPS II encoding table describes
the MIPS II-only mode except that the Coprocessor 3 instructions (COP3, LWC3, SWC3,
LDC3, SDC3) are not available and cause a Reserved Instruction exception. The MIPS III
encoding table describes the MIPS III-only mode.

A 8.3 Non-CPU Instructions in the Tables
The encoding tables show all values for the field they describe and by doing this
they include some entries that are not user-level CPU instructions. The primary opcode
table includes coprocessor instruction classes (COP0, COP1, COP2, COP3/COP1X) and
coprocessor load/store instructions (LWCx, SWCx, LDCx, SDCx for x=1, 2, or 3). The
opcode =SPECIAL + function =MOVCI instruction class is an FPU instruction.
A 8.3.1 Coprocessor 0 -

COP0

COP0 encodes privileged instructions for Coprocessor 0, the System Control
Coprocessor. The definition of the System Control Coprocessor is processor-specific and
further information on these instructions are not included in this document.
A 8.3.2 Coprocessor 1 -

COP1, COP1X, MOVCI, and CP1 load/store.

Coprocessor 1 is the floating-point unit in the MIPS architecture. COP1, COP1X,
and the (opcode =SPECIAL + function =MOVCI) instruction classes encode floating-point
instructions. LWC1, SWC1, LDC1, and SDC1 are floating-point loads and stores. The FPU
instruction encoding is documented in section B.12.
A 8.3.3 Coprocessor 2 -

COP2 and CP2 load/store.

Coprocessor 2 is optional and implementation-specific. No standard processor
from MIPS has implemented coprocessor 2, but MIPS’ semiconductor licensees may have
implemented it in a product based on one of the standard MIPS processors. At this time
the standard processors are: R2000, R3000, R4000, R4200, R4300, R4400, R4600, R6000,
R8000, and R10000.
A 8.3.4 Coprocessor 3 -

COP3 and CP3 load/store.

Coprocessor 3 is optional and implementation-specific in the MIPS I and MIPS II
architecture levels. It was removed from MIPS III and later architecture levels. Note that
in MIPS IV the COP3 primary opcode was reused for the COP1X instruction class. No
standard processor from MIPS has implemented coprocessor 2, but MIPS’ semiconductor
licensees may have implemented it in a product based on one of the standard MIPS
processors. At this time the standard processors are: R2000, R3000, R4000, R4200, R4300,
R4400, R4600, R6000, R8000, and R10000.

A-176

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Table A-37

CPU Instruction Encoding - MIPS I Architecture
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

Instructions encoded by opcode

field.

bits 28..26
0
1
000
001
SPECIAL δ REGIMM δ
ADDI
ADDIU
COP0 δ,π COP1 δ,π
*
*
LB
LH
SB
SH
*
LWC1 π
*
SWC1 π

2
010
J
SLTI
COP2 δ,π
∗
LWL
SWL
LWC2 π

3
011
JAL
SLTIU
COP3 δ,π,κ
*
LW
SW
LWC3 π,κ

4
100
BEQ
ANDI
*
*
LBU
*
*

5
101
BNE
ORI
*
*
LHU
*
*

6
110
BLEZ
XORI
*
*
LWR
SWR
*

7
111
BGTZ
LUI
*
*
*
*
*

SWC2 π

SWC3 π,κ

opcode
= SPECIAL
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

1
001
*
JALR
MTHI
MULTU
ADDU
*
*
*

2
010
SRL
*
MFLO
DIV
SUB
SLT
*
*

opcode
= REGIMM
rt
bits
20..19
0
1
2
3

00
01
10
11

function

Instructions encoded by function
bits 2..0
0
000
SLL
JR
MFHI
MULT
ADD
*
*
*

bits 18..16
0
000
BLTZ
=
BLTZAL
=

CPU Instruction Set

1
001
BGEZ
=
BGEZAL
=

3
011
SRA
*
MTLO
DIVU
SUBU
SLTU
*
*

field when opcode field = SPECIAL.

4
100
SLLV
SYSCALL
*
*
AND
*
*
*

5
101
*
BREAK
*
*
OR
*
*
*

6
110
SRLV
*
*
*
XOR
*
*
*

7
111
SRAV
*
*
*
NOR
*
*
*

Instructions encoded by the rt field when opcode field = REGIMM.
2
3
4
5
6
7
010
011
100
101
110
111
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

MIPS IV Instruction Set. Rev 3.2

A-177

Table A-38

CPU Instruction Encoding - MIPS II Architecture
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6

000
001
010
011
100
101
110

111

Instructions encoded by opcode
bits 28..26
0
1
000
001
SPECIAL δ REGIMM δ
ADDI
ADDIU
COP0 δ,π COP1 δ,π
*
*
LB
LH
SB
SH
LL
LWC1 π
SC

field.

2
010
J
SLTI
COP2 δ,π
∗
LWL
SWL
LWC2 π

3
011
JAL
SLTIU
COP3 δ,π,κ
*
LW
SW
LWC3 π,κ

4
100
BEQ
ANDI
BEQL
*
LBU
*
*

5
101
BNE
ORI
BNEL
*
LHU
*
LDC1 π

6
110
BLEZ
XORI
BLEZL
*
LWR
SWR
LDC2 π

7
111
BGTZ
LUI
BGTZL
*
*
ρ
LDC3 π,κ

SWC1 π

SWC2 π

SWC3 π,κ

SDC1 π

SDC2 π

SDC3 π,κ

opcode
= SPECIAL
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

1
001
*
JALR
MTHI
MULTU
ADDU
*
TGEU
*

2
010
SRL
*
MFLO
DIV
SUB
SLT
TLT
*

opcode
= REGIMM
rt
bits
20..19
0
1
2
3

00
01
10
11

A-178

function

Instructions encoded by function
bits 2..0
0
000
SLL
JR
MFHI
MULT
ADD
*
TGE
*

bits 18..16
0
000
BLTZ
TGEI
BLTZAL
*

1
001
BGEZ
TGEIU
BGEZAL
*

3
011
SRA
*
MTLO
DIVU
SUBU
SLTU
TLTU
*

field when opcode field = SPECIAL.

4
100
SLLV
SYSCALL
*
*
AND
*
TEQ
*

5
101
*
BREAK
*
*
OR
*
*
*

6
110
SRLV
*
*
*
XOR
*
TNE
*

7
111
SRAV
SYNC
*
*
NOR
*
*
*

Instructions encoded by the rt field when opcode field = REGIMM.
2
3
4
5
6
7
010
011
100
101
110
111
BLTZL
BGEZL
*
*
*
*
TLTI
TLTIU
TEQI
*
TNEI
*
BLTZALL BGEZALL
*
*
*
*
*
*
*
*
*
*

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Table A-39

CPU Instruction Encoding - MIPS III Architecture
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

Instructions encoded by opcode

field.

bits 28..26
0
1
000
001
SPECIAL δ REGIMM δ
ADDI
ADDIU
COP0 δ,π COP1 δ,π
DADDI
DADDIU
LB
LH
SB
SH
LL
LWC1 π
SC
SWC1 π

2
010
J
SLTI
COP2 δ,π
LDL
LWL
SWL
LWC2 π

3
011
JAL
SLTIU
∗
LDR
LW
SW
∗

4
100
BEQ
ANDI
BEQL
*
LBU
SDL
LLD

5
101
BNE
ORI
BNEL
*
LHU
SDR
LDC1 π

6
110
BLEZ
XORI
BLEZL
*
LWR
SWR
LDC2 π

7
111
BGTZ
LUI
BGTZL
*
LWU
ρ
LD

SWC2 π

∗

SCD

SDC1 π

SDC2 π

opcode
= SPECIAL
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

1
001
*
JALR
MTHI
MULTU
ADDU
*
TGEU
*

2
010
SRL
*
MFLO
DIV
SUB
SLT
TLT
DSRL

opcode
= REGIMM
rt
bits
20..19
0
1
2
3

00
01
10
11

function

Instructions encoded by function
bits 2..0
0
000
SLL
JR
MFHI
MULT
ADD
*
TGE
DSLL

bits 18..16
0
000
BLTZ
TGEI
BLTZAL
*

CPU Instruction Set

1
001
BGEZ
TGEIU
BGEZAL
*

3
011
SRA
*
MTLO
DIVU
SUBU
SLTU
TLTU
DSRA

field when opcode field = SPECIAL.

4
100
SLLV
SYSCALL
DSLLV
DMULT
AND
DADD
TEQ
DSLL32

5
101
*
BREAK
*
DMULTU
OR
DADDU
*
*

6
110
SRLV
*
DSRLV
DDIV
XOR
DSUB
TNE
DSRL32

7
111
SRAV
SYNC
DSRAV
DDIVU
NOR
DSUBU
*
DSRA32

Instructions encoded by the rt field when opcode field = REGIMM.
2
3
4
5
6
7
010
011
100
101
110
111
BLTZL
BGEZL
*
*
*
*
TLTI
TLTIU
TEQI
*
TNEI
*
BLTZALL BGEZALL
*
*
*
*
*
*
*
*
*
*

MIPS IV Instruction Set. Rev 3.2

A-179

Table A-40

CPU Instruction Encoding - MIPS IV Architecture
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

Instructions encoded by opcode

field.

bits 28..26
0
1
000
001
SPECIAL δ REGIMM δ
ADDI
ADDIU
COP0 δ,π COP1 δ,π
DADDI
DADDIU
LB
LH
SB
SH
LL
LWC1 π
SC
SWC1 π

2
010
J
SLTI
COP2 δ,π
LDL
LWL
SWL
LWC2 π

3
011
JAL
SLTIU
COP1X δ,π
LDR
LW
SW
PREF

4
100
BEQ
ANDI
BEQL

SWC2 π

∗

LBU
SDL
LLD

5
101
BNE
ORI
BNEL
*
LHU
SDR
LDC1 π

6
110
BLEZ
XORI
BLEZL
*
LWR
SWR
LDC2 π

7
111
BGTZ
LUI
BGTZL
*
LWU
ρ
LD

SCD

SDC1 π

SDC2 π

opcode
= SPECIAL
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

1
001
MOVCI δ,µ
JALR
MTHI
MULTU
ADDU
*
TGEU
*

2
010
SRL
MOVZ
MFLO
DIV
SUB
SLT
TLT
DSRL

opcode
= REGIMM
rt
bits
20..19
0
1
2
3

00
01
10
11

A-180

function

Instructions encoded by function
bits 2..0
0
000
SLL
JR
MFHI
MULT
ADD
*
TGE
DSLL

bits 18..16
0
000
BLTZ
TGEI
BLTZAL
*

1
001
BGEZ
TGEIU
BGEZAL
*

3
011
SRA
MOVN
MTLO
DIVU
SUBU
SLTU
TLTU
DSRA

field when opcode field = SPECIAL.

4
100
SLLV
SYSCALL
DSLLV
DMULT
AND
DADD
TEQ
DSLL32

5
101
*
BREAK
*
DMULTU
OR
DADDU
*
*

6
110
SRLV
*
DSRLV
DDIV
XOR
DSUB
TNE
DSRL32

7
111
SRAV
SYNC
DSRAV
DDIVU
NOR
DSUBU
*
DSRA32

Instructions encoded by the rt field when opcode field = REGIMM.
2
3
4
5
6
7
010
011
100
101
110
111
BLTZL
BGEZL
*
*
*
*
TLTI
TLTIU
TEQI
*
TNEI
*
BLTZALL BGEZALL
*
*
*
*
*
*
*
*
*
*

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Table A-41

Architecture Level in Which CPU Instructions are Defined or Extended.

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-181

The architecture level in which each MIPS IVencoding was defined is indicated by a subscript 1, 2, 3,
or 4 (for architecture level I, II, III, or IV). If an instruction or instruction class was later extended, the
extending level is indicated after the defining level.
31

opcode
opcod
e
bits
31..29

Instructions encoded by opcode

field.

bits 28..26
0
1
000
001
000 SPECIAL 1-4 REGIMM

1
2
3

001
010
011

ADDI 1
COP0 1
DADDI 3

ADDIU 1
COP1 1,2,3,4
DADDIU 3

SLTI 1
COP2 1
LDL 3

SLTIU 1
COP1X 4
LDR 3

ANDI 1
BEQL 2
*1

ORI 1
BNEL 2
*1

XORI 1
BLEZL 2
*1

LUI 1
BGTZL 2

4
5
6
7

100
101
110
111

LB 1
SB 1
LL 2
SC 2

LH 1
SH 1
LWC1 1
SWC1 1

LWL 1
SWL 1
LWC2 1
SWC2 1

LW 1
SW 1
PREF 4
∗3

LBU 1
SDL 3
LLD 3
SCD 3

LHU 1
SDR 3
LDC1 2
SDC1 2

LWR 1
SWR 1
LDC2 2
SDC2 2

LWU 3
ρ2
LD 3
SD 3

2
010
J1

3
011
JAL 1

4
100
BEQ 1

5
101
BNE 1

6
110
BLEZ 1

7
111
BGTZ 1

1,2

opcode
= SPECIAL
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

1
001
MOVCI 4
JALR 1
MTHI 1
MULTU 1
ADDU 1
*1
TGEU 2
*1

2
010
SRL 1
MOVZ 4
MFLO 1
DIV 1
SUB 1
SLT 1
TLT 2
DSRL 3

opcode
= REGIMM
rt
bits
20..19
0
1
2
3

00
01
10
11

A-182

bits 18..16
0
000
BLTZ 1
TGEI 2
BLTZAL 1
*1

function

Instructions encoded by function
bits 2..0
0
000
SLL 1
JR 1
MFHI 1
MULT 1
ADD 1
*1
TGE 2
DSLL 3

3
011
SRA 1
MOVN 4
MTLO 1
DIVU 1
SUBU 1
SLTU 1
TLTU 2
DSRA 3

field when opcode field = SPECIAL.

4
5
100
101
SLLV 1
*1
SYSCALL 1 BREAK 1
DSLLV 3
*1
DMULT 3 DMULTU 3
AND 1
OR 1
DADD 3
DADDU 3
TEQ 2
*1
DSLL32 3
*1

6
110
SRLV 1
*1
DSRLV 3
DDIV 3
XOR 1
DSUB 3
TNE 2
DSRL32 3

7
111
SRAV 1
SYNC 2
DSRAV 3
DDIVU 3
NOR 1
DSUBU 3
*1
DSRA32 3

Instructions encoded by the rt field when opcode field = REGIMM.
1
2
3
4
5
6
7
001
010
011
100
101
110
111
BGEZ 1
BLTZL 2
BGEZL 2
*1
*1
*1
*1
TGEIU 2
TLTI 2
TLTIU 2
TEQI 2
*1
TNEI 2
*1
BGEZAL 1 BLTZALL 2 BGEZALL 2
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-183

Table A-42

CPU Instruction Encoding Changes - MIPS II Revision.
31

opcode
An instruction encoding is shown if the instruction is added in this revision.
opcod
e
bits
31..29

Instructions encoded by opcode
bits 28..26
0
000

1
001

2
010

3
011

field.

4
100

5
101

6
110

7
111

BEQL

BNEL

BLEZL

BGTZL

LDC2 π
SDC2 π

LDC3 π
SDC3 π

0
1
2
3
4
5
6

000
001
010
011
100
101
110

LDC1 π

111

SDC1 π

opcode
= SPECIAL
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

1
001

2
010

0
1
2
3

00
01
10
11

A-184

3
011

field when opcode field = SPECIAL.

4
100

5
101

6
110

7
111
SYNC

TGE

TGEU

TLT

opcode
= REGIMM
rt
bits
20..19

function

Instructions encoded by function
bits 2..0
0
000

bits 18..16
0
000

1
001

TGEI

TGEIU

TLTU

TEQ

TNE

Instructions encoded by the rt field when opcode field = REGIMM.
2
3
4
5
6
7
010
011
100
101
110
111
BLTZL
BGEZL
TLTI
TLTIU
TEQI
TNEI
BLTZALL BGEZALL

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-185

Table A-43

A-186

CPU Instruction Encoding Changes - MIPS III Revision.

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

opcode
An instruction encoding is shown if the instruction is added or modified in this revision.
opcod
e
bits
31..29
0
1
2

000
001
010

3
4
5
6

011
100
101
110

Instructions encoded by opcode
bits 28..26
0
000

DADDI

1
001

DADDIU

2
010

3
011

LDL

*
(was COP3)
LDR

field.

4
100

5
101

SDL
LLD

SDR

6
110

LWU
*
(was LWC3 )

111

*
(was SWC3)

LD
(was LDC3)

SCD

SD
(was SDC3)

opcode
= SPECIAL
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

7
111

function

Instructions encoded by function
bits 2..0
0
000

DSLL

CPU Instruction Set

1
001

2
010

DSRL

3
011

DSRA

field when opcode field = SPECIAL.

4
100

5
101

6
110

7
111

DSLLV
DMULT

DMULTU

DSRLV
DDIV

DSRAV
DDIVU

DADD

DADDU

DSUB

DSUBU

DSRL32

DSRA32

DSLL32

MIPS IV Instruction Set. Rev 3.2

A-187

opcode
= REGIMM
rt
bits
20..19
0
1
2
3

bits 18..16
0
000

1
001

Instructions encoded by the rt field when opcode field = REGIMM.
2
3
4
5
6
7
010
011
100
101
110
111

00
01
10
11

A-188

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

Table A-44

CPU Instruction Encoding Changes - MIPS IV Revision.
31

opcode
An instruction encoding is shown if the instruction is added or modified in this revision.
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

Instructions encoded by opcode
bits 28..26
0
000

1
001

2
010

000
001
010
011
100
101
110
111

3
011

field.

4
100

5
101

6
110

COP1X δ,π

PREF

opcode
= SPECIAL
functi
on
bits
5..3
0

000

1
2
3
4
5
6
7

001
010
011
100
101
110
111

1
001
MOVCI δ,µ

2
010

3
011

MOVZ

MOVN

opcode
= REGIMM

0
1
2
3

bits 18..16
0
000

1
001

function

Instructions encoded by function
bits 2..0
0
000

rt
bits
20..19

7
111

field when opcode field = SPECIAL.

4
100

5
101

6
110

7
111

Instructions encoded by the rt field when opcode field = REGIMM.
2
3
4
5
6
7
010
011
100
101
110
111

00
01
10
11

CPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

A-189

Key to notes in CPU instruction encoding tables:

This opcode is reserved for future use. An attempt to execute it causes a
Reserved Instruction exception.

= This opcode is reserved for future use. An attempt to execute it produces
an undefined result. The result may be a Reserved Instruction exception
but this is not guaranteed.

(also italic opcode name) This opcode indicates an instruction class. The
instruction word must be further decoded by examing additional tables
that show values for another instruction field.

π This opcode is a coprocessor operation, not a CPU operation. If the
processor state does not allow access to the specified coprocessor, the
instruction causes a Coprocessor Unusable exception. It is included in the
table because it uses a primary opcode in the instruction encoding map.

κ This opcode is removed in a later revision of the architecture. If a MIPS III
or MIPS IV processor is operated in MIPS II-only mode this opcode will
cause a Reserved Instruction exception.

µ This opcode indicates a class of coprocessor 1 instructions. If the processor
state does not allow access to coprocessor 1, the opcode causes a
Coprocessor Unusable exception. It is included in the table because the
encoding uses a location in what is otherwise a CPU instruction encoding
map. Further encoding information for this instruction class is in the FPU
Instruction Encoding tables.

ρ This opcode is reserved for Coprocessor 0 (System Control Coprocessor)
instructions that require base+offset addressing. If the instruction is used
for COP0 in an implementation, an attempt to execute it without
Coprocessor 0 access privilege will cause a Coprocessor Unusable
exception. If the instruction is not used in an implementation, it will cause
a Reserved Instruction exception.

A-190

MIPS IV Instruction Set. Rev 3.2

CPU Instruction Set

FPU Instruction Set

Introduction
This appendix describes the instruction set architecture (ISA) for the floating-point
unit (FPU) in the MIPS IV architecture. In the MIPS architecture, the FPU is
coprocessor 1, an optional processor implementing IEEE Standard 754† floatingpoint operations. The FPU also provides a few additional operations not defined
by the IEEE standard.
The original MIPS I FPU ISA has been
extended in a backward-compatible
fashion three times. The ISA extensions
are inclusive as the diagram illustrates;
each new architecture level (or version)
includes the former levels. The
description of an architectural feature
includes the architecture level in which
the feature is (first) defined or
extended. The feature is also available
in all later (higher) levels of the
architecture.

MIPS I
MIPS II
MIPS III
MIPS IV

MIPS Architecture Extensions

† IEEE Standard 754-1985, “IEEE Standard for Binary Floating-Point Arithmetic”
FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-1

In addition to an ISA, the architecture definition includes processing resources,
such as the coprocessor general register set. The 32-bit registers in MIPS I were
changed to 64-bit registers in MIPS III in a way that is not backwards compatible.
For changes such as this, processors implementing higher levels of the architecture
have a way to provide the processing resource model for earlier levels. For the
FPU there is a mode to select the 32-bit or 64-bit register model. The practical result
is that a processor implementing MIPS IV is also able to run MIPS I, MIPS II, or
MIPS III binary programs without change.
If coprocessor 1 is not enabled, an attempt to execute a floating-point instruction
will cause a Coprocessor Unusable exception. Enabling coprocessor 1 is a
privileged operation provided by the System Control Coprocessor. Every system
environment will either enable the FPU automatically or provide a means for an
application to request that it be enabled.
Before the instruction set is described, there is an overview of the FPU data types,
registers, and computational model. The FPU instruction set is summarized by
functional group then each operation is described separately in alphabetical order.
The description concludes with the FPU instruction formats and opcode encoding
tables. See the CPU instruction set section titled “Description of an Instruction” for
a description of the organization of the individual instruction descriptions and the
notation used in them.
The architecture of the floating-point coprocessor consists of:
•

Data types

•

Operations

•

A computational model

•

Processing resources (registers)

•

An instruction set

The IEEE standard defines the floating-point number data types, the basic
arithmetic, comparison, and conversion operations, and a computational model.
The IEEE standard defines neither specific processing resources nor an instruction
set. The MIPS architecture defines fixed-point (integer) data types, FPU register
sets, control and exception mechanisms, and an instruction set. The architecture
include non-IEEE FPU control operations, and arithmetic operations (multiplyadd, reciprocal, and reciprocal square root) that may not supply results that match
the IEEE precision rules.

FPU Data Types
The FPU provides both floating-point and fixed-point data types. The single and
double precision floating-point data types are those specified by the IEEE
standard. The fixed-point types are the signed integers provided by the CPU
architecture

B-2

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

B 2.1 Floating-point formats
There are two floating-point data types provided by the FPU.
•

32-bit Single precision floating-point (type S)

•

64-bit Double precision floating-point (type D)

The floating-point formats represents numeric values as well as other special
entities:
1.

Numbers of the form: (-1)s 2E b0 . b1 b2 ...bp-1
where (see Table B-1):
s = 0 or 1
E = any integer between E_min and E_max, inclusive
bi = 0 or 1 (the high bit, b0, is to the left of the binary point)
p is the precision

Two infinities, +∞ and -∞

Signaling non-numbers (SNaNs)

Quiet non-numbers (QNaNs)

Table B-1

Parameters of Floating-Point Formats

parameter

Single

Double

bits of mantissa precision, p

maximum exponent, E_max

+127

+1023

minimum exponent, E_min

-126

-1022

exponent bias

+127

+1023

bits in exponent field, e

representation of b0 integer bit

hidden

bits in fraction field, f

total format width in bits

The single and double floating-point formats are composed of three fields whose
size is listed in Table B-1. The layouts are pictured in the figures below.
•

A 1-bit sign, s.

•

A biased exponent, e = E + bias

•

A binary fraction, f = . b1 b2 ...bp-1

sign exponent
1

(the b0 bit is not recorded)

fraction
23

Figure B-1

Single-Precision Floating-Point Format (S)

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-3

sign

exponent

fraction

Figure B-2

Double-Precision Floating-Point Format (D)

Values are encoded in the formats using the unbiased exponent, fraction, and sign
values shown in Table B-2. The high-order bit of the fraction field, identified as b1,
is also important for NaNs.
Table B-2

Value of Single or Double Floating-Point Format Encoding

unbiased E

E_max + 1

≠0

E_max +1

E_max
to
E_min

B 2.1.1

E_min -1

≠0

E_min -1

value v

type of value

SNaN

Signaling NaN

QNaN

Quiet NaN

-∞

minus infinity

+∞

plus infinity

- (2E)(1. f)

negative normalized number

E)(1 f)

+ (2

positive normalized number

- (2E_min)(0 . f)

negative denormalized number

+ (2E_min)(0 . f)

positive denormalized number

-0

negative zero

positive zero

Normalized and Denormalized Numbers
For single and double formats, each representable nonzero numerical value has
just one encoding; numbers are kept in normalized form. The high-order bit of the
p-bit mantissa, which lies to the left of the binary point, is “hidden”, and not
recorded in the fraction field. The encoding rules permit the value of this bit to be
determined by looking at the value of the exponent. When the unbiased exponent
is in the range E_min to E_max, inclusive, the number is normalized and the hidden
bit must be 1. If the numeric value cannot be normalized because the exponent
would be less than E_min, then the representation is denormalized and the
encoded number has an exponent of E_min-1 and the hidden bit has the value 0.
Plus and minus zero are special cases that are not regarded as denormalized
values.

B 2.1.2

Reserved Operand Values — Infinity and NaN
A floating-point operation can signal IEEE exception conditions, such as those
caused by uninitialized variables, violations of mathematical rules, or results that
cannot be represented. If a program does not choose to trap IEEE exception

B-4

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

conditions, a computation that encounters these conditions proceeds without
trapping but generates a result indicating that an exceptional condition arose
during the computation. To permit this, each floating-point format defines
representations, shown in Table B-2, for +infinity (+∞), -infinity (-∞), quiet NaN
(QNan), and signaling NaN (SNaN).
Infinity represents a number with magnitude too large to be represented in the
format; in essence it exists to represent a magnitude overflow during a
computation. A correctly signed ∞ is generated as the default result in division by
zero and some cases of overflow; details are in the IEEE exception condition
descriptions and Table B-4 "Default Result for IEEE Exceptions Not Trapped
Precisely".
Once created as a default result, ∞ can become an operand in a subsequent
operation. The infinities are interpreted such that -∞ < (every finite number) < +∞.
Arithmetic with ∞ is the limiting case of real arithmetic with operands of
arbitrarily large magnitude, when such limits exist. In these cases, arithmetic on ∞
is regarded as exact and exception conditions do not arise. The out-of-range
indication represented by the ∞ is propagated through subsequent computations.
For some cases there is no meaningful limiting case in real arithmetic for operands
of ∞ and these cases raise the Invalid Operation exception condition. See the
description of the Invalid Operation exception for a list of these cases.
SNaN operands cause the Invalid Operation exception for arithmetic operations.
SNaNs are useful values to put uninitialized variables. SNaN is never produced
as a result value.
NOTE:

The IEEE 754 Standard states that “Whether copying a signaling NaN
without a change of format signals the invalid operation exception is the implementor’s
option”. The MIPS architecture has chosen to make the formatted operand move
instructions (MOV.fmt MOVT.fmt MOVF.fmt MOVN.fmt MOVZ.fmt) non-arithmetic
and they do not signal IEEE exceptions.

QNaNs are intended to afford retrospective diagnostic information inherited from
invalid or unavailable data and results. Propagation of the diagnostic information
requires that information contained in the QNaNs be preserved through
arithmetic operations and floating-point format conversions.
QNaN operands do not cause arithmetic operations to signal an exception. When
a floating-point result is to be delivered, a QNaN operand causes an arithmetic
operation to supply a QNaN result. The result QNaN is one of the operand QNaN
values when possible. QNaNs do have effects similar to SNaNs on operations that
do not deliver a floating-point result, specifically comparisons. See the detailed
description of the floating-point compare instruction (C.cond.fmt) for information.
When certain invalid operations not involving QNaN operands are performed but
do not cause a trap (because the trap is not enabled), a new QNaN value is created.
Table B-3 shows the QNaN value generated when no input operand QNaN value
can be copied. The values listed for the fixed-point formats are the values supplied
to satisfy the IEEE standard when a QNaN or infinite floating-point value is
converted to fixed point. There is no other feature of the architecture that detects
or makes use of these “integer QNaN” values.
FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-5

Table B-3

Value Supplied when a new Quiet NaN is Created

Format

New QNaN value

Single floating point

7fbf ffff

Double floating point

7ff7 ffff ffff ffff

Word fixed point

7fff ffff

Longword fixed point

B 2.2

7fff ffff ffff ffff

Fixed-point formats
There are two floating-point data types provided by the FPU.
•

32-bit Word fixed-point (type W)

•

64-bit Longword fixed-point (type L) (defined in MIPS III)

The fixed-point values are held in the two’s complement format used for signed
integers in the CPU. Unsigned fixed-point data types are not provided in the
architecture; application software may synthesize computations for unsigned
integers from the existing instructions and data types.

int

Figure B-3

Word Fixed-Point Format (W)

sign

int

Figure B-4

sign

Longword Fixed-Point Format (L)

Floating-Point Registers
This section describes the organization and use of the two separate coprocessor 1
(CP1) register sets. The coprocessor general registers, also called Floating General
Registers (FGRs) are used to transfer binary data between the FPU and the rest of
the system. The general register set is also used to hold formatted FPU operand
values. There are only two control registers and they are used to identify and
control the FPU.

B-6

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

There are separate 32-bit and 64-bit wide register models. MIPS I defines the 32-bit
wide register model. MIPS III defines the 64-bit model. To support programs for
earlier architecture definitions, processors providing the 64-bit MIPS III register
model also provide the 32-bit wide register model as a mode selection. Selecting
32 or 64-bit register model is an implementation-specific privileged operation.

B 3.1 Organization
The CP1 register organization for 32-bit and 64-bit register models is shown in
Figure B-5. The coprocessor general registers are the same width as the CPU
registers. The two defined control registers are 32-bits wide.

MIPS I
32-bit reg model
31

MIPS III
64-bit register model

reg # 0

..
.

FPU - Control Registers (FCRs)
31

Implementation and Revision #
0

FP Control and Status
31

Figure B-5

Coprocessor 1 General Registers (FGRs)

B 3.2 Binary Data Transfers
The data transfer instructions move words and doublewords between the CP1
general registers and the remainder of the system. The operation of the load and
move-to instructions is shown in Figure B-6 and Figure B-7. The store and movefrom instructions operate in reverse, reading data from the location that the
corresponding load or move-to instruction wrote it.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-7

MIPS I
32-bit reg model
31

MIPS III
64-bit register model

operation

empty

⇓

LWC1 f0,0(r0) / MTC1 f0,r0

data word 0

empty

⇓

data word 0

undefined/unused

empty

⇓

LWC1 f1,4(r0) / MTC1 f1,r4

data word 0

undefined/unused

data word 0

data word 4

undefined/unused

data word 4

Figure B-6

Effect of FPU Word Load or Move-to Operations

Doubleword transfers to/from 32-bit registers access an aligned pair of CP1
general registers with the least-significant word of the doubleword in the lowestnumbered register.

MIPS II
32-bit reg model
Loads/Stores
(see note below)
31

MIPS III
64-bit register model

operation

empty

⇓

LDC1 f0,0(r0) / DMTC1 f0,r0

lower word (0)

data doubleword 0

upper word (4)

empty

⇓
invalid to load
double to odd
register

LDC1 f1,8(r0) / DMTC1 f1,r8

⇓

data doubleword 0

data doubleword 8

NOTE: No 64-bit transfers are defined for the MIPS I 32-bit register model.
MIPS II defines the 64-bit loads/stores but not 64-bit moves.

Figure B-7
B-8

Effect of FPU Doubleword Load or Move-to Operations
MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

B 3.3 Formatted Operand Layout
FPU instructions that operate on formatted operand values specify the floatingpoint register (FPR) that holds a value. An FPR is not necessarily the same as a CP1
general register because an FPR is 64 bits wide; if this is wider than the CP1 general
registers, an aligned set of adjacent CP1 general registers is used as the FPR. The
32-bit register model provides 16 FPRs specified by the even CP1 general register
numbers. The 64-bit register model provides 32 FPRs, one per CP1 general
register. Operands that are only 32 bits wide (W and S formats), use only half the
space in an FPR. The FPR organization and the way that operand data is stored in
them is shown in the following figures. A summary of the data transfer
instructions can be found in section B 6.1 on page B-19.

MIPS I
32-bit reg model

MIPS III
64-bit register model
#0

1
2

..
.

31
16 x 64-bit
operand registers
(FPRs)

Figure B-8

32 x 64-bit
operand registers (FPRs)

Floating-point Operand Register (FPR) Organization

MIPS I
32-bit reg model
31

MIPS III
64-bit register model

data word
undefined/unused

Figure B-9

FPU Instruction Set

#0 undefined/unused
1

data word

empty — available to hold an operand

Single Floating Point (S) or Word Fixed (W) Operand in an FPR

MIPS IV Instruction Set. Rev 3.2

B-9

MIPS I
32-bit reg model
(see note below)
31

MIPS III
64-bit register model

lower word

data doubleword

upper word

empty — available to hold an operand

NOTE: MIPS I supports the Double floating-point (D) type; the fixed-point longword
(L) operand is available starting in MIPS III

Figure B-10

Double Floating Point (D) or Long Fixed (L) Operand In an FPR

B 3.4 Implementation and Revision Register
Coprocessor control register 0 contains values that identify the implementation
and revision of the FPU. Only the low-order two bytes of this register are defined
as shown in Figure B-11.

Figure B-11

Implementation

Revision

FPU Implementation and Revision Register

The implementation field identifies a particular FPU part, but the revision number
may not be relied on to reliably characterize the FPU functional version.

B 3.5 FPU Control and Status Register — FCSR
Coprocessor control register 31 Is the FPU Control and Status Register (FCSR).
Access to the register is not privileged; it can be read or written by any program
that can execute floating-point instructions. It controls some operations of the
coprocessor and shows status information:

B-10

•

Selects the default rounding mode for FPU arithmetic operations.

•

Selectively enables traps of FPU exception conditions.

•

Controls some denormalized number handling options.

•

Reports IEEE exceptions that arose in the most recently executed instruction.

•

Reports IEEE exceptions that arose, cumulatively, in completed instructions.

•

Indicates the condition code result of FP compare instructions.

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

The contents of this register are unpredictable and undefined after a processor
reset or a power-up event. Software should initialize this register.
Figure B-12

MIPS I - FPU Control and Status Register (FCSR)

23 22

18 17

12 11

7 6

2 1 0

cause

enables

flags

E V Z O U I V Z O U I V Z O U I
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

Figure B-13

MIPS III - FPU Control and Status Register (FCSR)

25 24

23 22

18 17

12 11

7 6

2 1 0

FS c

cause

enables

flags

E V Z O U I V Z O U I V Z O U I
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

Figure B-14

MIPS IV - FPU Control and Status Register (FCSR)

25 24

FCC
7

23 22

18 17

12 11

7 6

2 1 0

FS FCC

cause

enables

flags

7 6 5 4 3 2 1

E V Z O U I V Z O U I V Z O U I

31 30 29 28 27 26 25

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

All fields in the FCSR are readable and writable.
FCC

Floating-Point Condition Codes. These bits record the result of FP compares
and are tested for FP conditional branches; the FCC bit to use is specified in
the compare or branch instruction. The 0th FCC bit is the same as the c bit in
MIPS I.

Flush to Zero. When FS is set, denormalized results are flushed to zero
instead of causing an unimplemented operation exception. When a
denormalized operand value is encountered, zero may be used instead of the
denorm; this is implementation specific.

Condition Bit. This bit records the result of FP compares and is tested by FP
conditional branches. In MIPS IV this becomes the 0th FCC bit.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-11

cause

Cause bits.
These bits indicate the exception conditions that arise during the execution
of an FPU arithmetic instruction in precise exception mode. A bit is set to 1
if the corresponding exception condition arises during the execution of an
instruction and 0 otherwise. By reading the registers, the exception
conditions caused by the preceding FPU arithmetic instruction can be
determined. The meaning of the individual bits is:
E

Unimplemented Operation

Invalid Operation

Divide by Zero

Overflow

Underflow

Inexact Result

enables Enable bits (see cause field for bit names).
These bits control, for each of the five conditions individually, whether a trap
is taken when the IEEE exception condition occurs. The trap occurs when
both an enable bit and the corresponding cause bit are set during an FPU
arithmetic operation or by moving a value to the FCSR. The meaning of the
individual bits is the same as the cause bits. Note that the “E” cause bit has
no corresponding enable bit; the non-IEEE Unimplemented Operation
exception defined by MIPS is always enabled.

B-12

flags

Flag bits. (see cause field for bit names)
This field shows the exception conditions that have occurred for completed
instructions since it was last reset. For a completed FPU arithmetic operation
that raises an exception condition the corresponding bits in the flag field are
set and the others are unchanged. This field is never reset by hardware and
must be explicitly reset by user software.

Rounding Mode. The rounding mode used for most floating-point
operations (some FP instructions use a specific rounding mode). The
rounding modes are:
0

RN -- Round to Nearest
Round result to the nearest representable value. When two
representable values are equally near, round to the value that has a
least significant bit of zero (i.e. is even).

RZ -- Round toward Zero
Round result to the value closest to and not greater in magnitude
then the result.

RP -- Round toward Plus infinity
Round result to the value closest to and not less than the result.

RM -- Round toward Minus infinity
Round result to the value closest to and not greater than the result.

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Values in FP Registers
Unlike the CPU, the FPU does not interpret the binary encoding of source
operands or produce a binary encoding of results for every operation. The value
held in a floating-point operand register (FPR) has a format, or type and it may
only be used by instructions that operate on that format. The format of a value is
either uninterpreted, unknown, or one of the valid numeric formats: single and
double floating-point and word and long fixed-point. The way that the formatted
value in an FPR is set and changed is summarized in the state diagram in Figure
B-15 and is discussed below.
The value in an FPR is always set when a value is written to the register. When a
data transfer instruction writes binary data into an FPR (a load), the FPR gets a
binary value that is uninterpreted. A computational or FP register move instruction
that produces a result of type fmt puts a value of type fmt into the result register.
When an FPR with an uninterpreted value is used as a source operand by an
instruction that requires a value of format fmt, the binary contents are interpreted
as an encoded value in format fmt and the value in the FPR changes to a value of
format fmt. The binary contents cannot be reinterpreted in a different format.
If an FPR contains a value of format fmt, a computational instruction must not use
the FPR as a source operand of a different format. If this occurs, the value in the
register becomes unknown and the result of the instruction is also a value that is
unknown. Using an FPR containing an unknown value as a source operand
produces a result that has an unknown value.
The format of the value in the FPR is unchanged when it is read by a data transfer
instruction (a store). A data transfer instruction produces a binary encoding of the
value contained in the FPR. If the value in the FPR is unknown, the encoded binary
value produced by the operation is not defined.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-13

Load
Store

Rslt
unknown

Value
uninterpreted
(binary
encoding)

Rslt A

Rslt B
Src A
(interpret)

Src B
(interpret)
Load

Src A
Rslt A
Store

Value in
format
A

Rslt
unknown

Value in
format
B

Rslt A
Src B

Src A
Rslt B

Rslt A

Src A
Src B
Store

A, B:
Load:
Store:
Src fmt:
Rslt fmt:

Src B
Rslt B
Store

Rslt
unknown

Value
unknown
Load

Example formats
Destination of LWC1, LDC1, MTC1, or DMTC1 instructions.
Source operand of SWC1, SDC1, MFC1, or DMFC1 instructions.
Source operand of computational instruction expecting format “fmt”.
Result of computational instruction producing value of format “fmt”.

Figure B-15 The Effect of FPU Operations on the Format of Values Held in FPRs.

FPU Exceptions
The IEEE 754 standard specifies that:

B-14

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

There are five types of exceptions that shall be signaled when detected.
The signal entails setting a status flag, taking a trap, or possibly doing
both. With each exception should be associated a trap under user control,
...
This function is implemented in the MIPS FPU architecture with the cause, enable,
and flag fields of the control and status register. The flag bits implement IEEE
exception status flags, and the cause and enable bits control exception trapping.
Each field has a bit for each of the five IEEE exception conditions and the cause
field has an additional exception bit, Unimplemented Operation, used to trap for
software emulation assistance.
There may be two exception modes for the FPU, precise and imprecise, and the
operation of the FPU when exception conditions arise depends on the exception
mode that is currently selected. Every processor is able to operate the FPU in the
precise exception mode. Some processors also have an imprecise exception mode
in which floating-point performance is greater. Selecting the exception mode,
when there is a choice, is a privileged implementation-specific operation.

B 5.1 Precise Exception Mode
In precise exception mode, an exception (trap) caused by a floating-point
operation is precise. A precise trap occurs before the instruction that causes the
trap, or any following instruction, completes and writes results. If desired, the
software trap handler can resume execution of the interrupted instruction stream
after handling the exception.
The cause bit field reports per-instruction exception conditions. The cause bits are
written during each floating-point arithmetic operation to show the exception
conditions that arose during the operation. The bits are set to 1 if the
corresponding exception condition arises and 0 otherwise.
A floating-point trap is generated any time both a cause bit and the corresponding
enable bit are set. This occurs either during the execution of a floating-point
operation or by moving a value into the FCSR. There is no enable for
Unimplemented Operation; this exception condition always generates a trap.
In a trap handler, the exception conditions that arose during the floating-point
operation that trapped are reported in the cause field. Before returning from a
floating-point interrupt or exception, or setting cause bits with a move to the FCSR,
software must first clear the enabled cause bits by a move to the FCSR to prevent
the trap from being retaken. User-mode programs can never observe enabled
cause bits set. If this information is required in a user-mode handler, then it must
be passed somewhere other than the status register.
For a floating-point operation that sets only non-enabled cause bits, no trap occurs
and the default result defined by the IEEE standard is stored (see Table B-4). When
a floating-point operation does not trap, the program can see the exception
conditions that arose during the operation by reading the cause field.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-15

The flag bit field is a cumulative report of IEEE exception conditions that arise
during instructions that complete; instructions that trap do not update the flag bits.
The flag bits are set to 1 if the corresponding IEEE exception is raised and
unchanged otherwise. There is no flag bit for the MIPS Uniplemented Operation
exception condition. The flag bits are never cleared as a side effect of floating-point
operations, but may be set or cleared by moving a new value into the FCSR.

B 5.2 Imprecise Exception Mode
In imprecise exception mode, an exception (trap) caused by an IEEE floating-point
operation is imprecise (Unimplemented Operation exceptions must still be
signaled precisely). An imprecise trap occurs at some point after the exception
condition arises. In particular, it does not necessarily occur before the instruction
that causes the exception, or following instructions, have completed and written
results. The software trap handler can generally neither determine which
instruction caused the trap nor continue execution of the interrupted instruction
stream; it can record the trap that occurred and abort the program.
The meaning of the cause bit field when reading the FCSR is not defined. When a
cause bit is written in the FCSR by moving data to it, the corresponding flag bit is
also set.
All floating-point operations, whether they cause a trap or not, complete in the
sense that they write a result and record exception condition bits in the flag field.
When an IEEE exception condition arises during an operation, the default result
defined by the IEEE standard is stored (see Table B-4).
A floating-point trap is generated when an exception condition arises during a
floating-point operation and the corresponding enable bit is set. A trap will also
be generated when a value with corresponding cause and enable bits set is moved
into the FCSR. There is no enable for Unimplemented Operation; this exception
condition always generates a trap.
The flag bit field is a cumulative report of IEEE exception conditions that arise
during instructions that complete. Because all instructions complete in this mode,
unlike precise exception mode, the flag bits include exception conditions that
cause traps. The flag bits are set to 1 if the corresponding IEEE exception is raised
and unchanged otherwise. There is no flag bit for the MIPS Uniplemented
Operation exception condition. The flag bits are never cleared as a side effect of
floating-point operations, but may be set or cleared by moving a new value into
the FCSR.

B 5.3 Exception Condition Definitions
The five exception conditions defined by the IEEE standard are described in this
section. It also describes the MIPS-defined exception condition, Unimplemented
Operation, that is used to signal a need for software emulation assistance for an
instruction.

B-16

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Normally an IEEE arithmetic operation can cause only one exception condition;
the only case in which two exceptions can occur at the same time are inexact with
overflow and inexact with underflow.
At the program’s direction, an IEEE exception condition can either cause a trap or
not. The IEEE standard specifies the result to be delivered in case the exception is
not enabled and no trap is taken. The MIPS architecture supplies these results
whenever the exception condition does not result in a precise trap (i.e. no trap or
an imprecise trap). The default action taken depends on the type of exception
condition, and in the case of the Overflow, the current rounding mode. The
default result is mentioned in each description and summarized inTable B-4.
Table B-4

Default Result for IEEE Exceptions Not Trapped Precisely

Bit Description Default Action

Invalid
Supply a quiet NaN.
Operation

Divide by Supply a properly signed infinity.
zero

Underflow Supply a rounded result.

Inexact

Overflow Depends on the rounding mode as shown below

Supply a rounded result. If caused by an overflow without the
overflow trap enabled, supply the overflowed result.

0 (RN) Supply an infinity with the sign of the intermediate result.
1 (RZ) Supply the format’s largest finite number with the sign of the
intermediate result.
2 (RP) For positive overflow values, supply positive infinity. For negative
overflow values, supply the format’s most negative finite number.
3 (RM) for positive overflow values supply the format’s largest finite number.
For negative overflow values, supply minus infinity.

B 5.3.1

Invalid Operation exception
The invalid operation exception is signaled if one or both of the operands are
invalid for the operation to be performed. The result, when the exception
condition occurs without a precise trap, is a quiet NaN. The invalid operations are:
•

One or both operands is a signaling NaN (except for the non-arithmetic
MOV.fmt MOVT.fmt MOVF.fmt MOVN.fmt and MOVZ.fmt instructions)

•

Addition or subtraction: magnitude subtraction of infinities, such as:
(+∞) + (-∞) or (-∞) - (-∞)

•

Multiplication: 0 × ∞, with any signs

•

Division: 0 / 0 or ∞ / ∞, with any signs

•

Square root: An operand less than 0 (-0 is a valid operand value).

•

Conversion of a floating-point number to a fixed-point format when an
overflow, or operand value of infinity or NaN, precludes a faithful
representation in that format.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-17

•

B 5.3.2

Some comparison operations in which one or both of the operands is a
QNaN value. The definition of the compare operation (C.cond.fmt) has
tables showing the comparisons that do and do not signal the
exception.

Division By Zero exception
The division by zero exception is signaled on an implemented divide operation if
the divisor is zero and the dividend is a finite nonzero number. The result, when
no precise trap occurs, is a correctly signed infinity. The divisions (0/0) and (∞/0)
do not cause the division by zero exception. The result of (0/0) is an Invalid
Operation exception condition. The result of (∞/0) is a correctly signed infinity.

B 5.3.3

Overflow exception
The overflow exception is signaled when what would have been the magnitude of
the rounded floating-point result, were the exponent range unbounded, is larger
than the destination format’s largest finite number. The result, when no precise
trap occurs, is determined by the rounding mode and the sign of the intermediate
result as shown in Table B-4.

B 5.3.4

Underflow exception
Two related events contribute to underflow. One is the creation of a tiny non-zero
result between ±2E_min which, because it is tiny, may cause some other exception
later such as overflow on division. The other is extraordinary loss of accuracy
during the approximation of such tiny numbers by denormalized numbers. The
IEEE standard permits a choice in how these events are detected, but requires that
they must be detected the same way for all operations.
The IEEE standard specifies that “tininess” may be detected either: “after
rounding” (when a nonzero result computed as though the exponent range were
unbounded would lie strictly between ±2E_min), or “before rounding” (when a
nonzero result computed as though both the exponent range and the precision
were unbounded would lie strictly between ±2E_min). The MIPS architecture
specifies that tininess is detected after rounding.
The IEEE standard specifies that loss of accuracy may be detected as either
“denormalization loss” (when the delivered result differs from what would have
been computed if the exponent range were unbounded), or “inexact result” (when
the delivered result differs from what would have been computed if both the
exponent range and precision were unbounded). The MIPS architecture specifies
that loss of accuracy is detected as inexact result.
When an underflow trap is not enabled, underflow is signaled only when both
tininess and loss of accuracy have been detected. The delivered result might be
zero, denormalized, or ±2E_min. When an underflow trap is enabled (via the FCSR
enable field bit), underflow is signaled when tininess is detected regardless of loss
of accuracy.

B-18

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

B 5.3.5

Inexact exception
If the rounded result of an operation is not exact or if it overflows without an
overflow trap, then the inexact exception is signaled.

B 5.3.6

Unimplemented Operation exception
This MIPS defined (non-IEEE) exception is to provide software emulation support.
The architecture is designed to permit a combination of hardware and software to
fully implement the architecture. Operations that are not fully supported in
hardware cause an Unimplemented Operation exception so that software may
perform the operation. There is no enable bit for this condition; it always causes a
trap. After the appropriate emulation or other operation is done in a software
exception handler, the original instruction stream can be continued.

Functional Instruction Groups
The FPU instructions are divided into the following functional groups:
•

Data Transfer

•

Arithmetic

•

Conversion

•

Formatted Operand Value Move

•

Conditional Branch

•

Miscellaneous

B 6.1 Data Transfer Instructions
The FPU has two separate register sets: coprocessor general registers and
coprocessor control registers. The FPU has a load/store architecture; all
computations are done on data held in coprocessor general registers. The control
registers are used to control FPU operation. Data is transferred between registers
and the rest of the system with dedicated load, store, and move instructions. The
transferred data is treated as unformatted binary data; no format conversions are
performed and, therefore, no IEEE floating-point exceptions can occur.
The supported transfer operations are:
• FPU general reg ↔

memory

(word/doubleword load/store)

• FPU general reg ↔

CPU general reg

(word/doubleword move)

↔

CPU general reg

(word move)

• FPU control reg

All coprocessor loads and stores operate on naturally-aligned data items. An
attempt to load or store to an address that is not naturally aligned for the data item
will cause an Address Error exception. Regardless of byte-numbering order

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-19

(endianness), the address of a word or doubleword is the smallest byte address
among the bytes in the object. For a big-endian machine this is the most-significant
byte; for a little-endian machine this is the least-significant byte.
The FPU has loads and stores using the usual register+offset addressing. For the
FPU only, there are load and store instructions using register+register addressing.
MIPS I specifies that loads are delayed by one instruction and that proper
execution must be insured by observing an instruction scheduling restriction. The
instruction immediately following a load into an FPU register Fn must not use Fn
as a source register. The time between the load instruction and the time the data
is available is the “load delay slot”. If no useful instruction can be put into the load
delay slot, then a null operation (NOP) must be inserted.
In MIPS II, this instruction scheduling restriction is removed. Programs will
execute correctly when the loaded data is used by the instruction following the
load, but this may require extra real cycles. Most processors cannot actually load
data quickly enough for immediate use and the processor will be forced to wait
until the data is available. Scheduling load delay slots is desirable for performance
reasons even when it is not necessary for correctness.

B-20

Table B-5

FPU Loads and Stores Using Register + Offset Address Mode

Mnemonic

Description

LWC1
SWC1

Load Word to Floating-Point
Store Word to Floating-Point

LDC1
SDC1

Load Doubleword to Floating-Point
Store Doubleword to Floating-Point

Table B-6

FPU Loads and Using Register + Register Address Mode

Defined in

MIPS I
I
III
III

Mnemonic

Description

Defined in

LWXC1
SWXC1

Load Word Indexed to Floating-Point
Store Word Indexed to Floating-Point

MIPS IV
IV

LDXC1
SDXC1

Load Doubleword Indexed to Floating-Point
Store Doubleword Indexed to Floating-Point

Table B-7

FPU Move To/From Instructions

Mnemonic

Description

MTC1
MFC1

Move Word To Floating-Point
Move Word From Floating-Point

DMTC1
DMFC1

Doubleword Move To Floating-Point
Doubleword Move From Floating-Point

III
III

CTC1
CFC1

Move Control Word To Floating-Point
Move Control Word From Floating-Point

I
I

IV
IV

Defined in

MIPS IV Instruction Set. Rev 3.2

MIPS I
I

FPU Instruction Set

B 6.2 Arithmetic Instructions
The arithmetic instructions operate on formatted data values. The result of most
floating-point arithmetic operations meets the IEEE standard specification for
accuracy; a result which is identical to an infinite-precision result rounded to the
specified format, using the current rounding mode. The rounded result differs
from the exact result by less than one unit in the least-significant place (ulp).
Table B-8

FPU IEEE Arithmetic Operations

Mnemonic

Description

ADD.fmt
SUB.fmt
MUL.fmt
DIV.fmt
ABS.fmt
NEG.fmt
SQRT.fmt

Floating-Point Add
Floating-Point Subtract
Floating-Point Multiply
Floating-Point Divide
Floating-Point Absolute Value
Floating-Point Negate
Floating-Point Square Root

C.cond.fmt

Floating-Point Compare

Defined in

MIPS I
I
I
I
I
I
II
I

Two operations, Reciprocal Approximation (RECIP) and Reciprocal Square Root
Approximation (RSQRT), may be less accurate than the IEEE specification. The
result of RECIP differs from the exact reciprocal by no more than one ulp. The
result of RSQRT differs by no more than two ulp. Within these error limits, the
result of these instructions is implementation specific.
Table B-9

FPU Approximate Arithmetic Operations

Mnemonic

Description

Defined in

RECIP.fmt
RSQRT.fmt

Floating-Point Reciprocal Approximation
Floating-Point Reciprocal Square Root
Approximation

MIPS IV
IV

There are four compound-operation instructions that perform variations of
multiply-accumulate: multiply two operands and accumulate to a third operand
to produce a result. The accuracy of the result depends which of two alternative
arithmetic models is used for the computation. The unrounded model is more
accurate than a pair of IEEE operations and the rounded model meets the IEEE
specification.
Table B-10

FPU Multiply-Accumulate Arithmetic Operations

Mnemonic

Description

Defined in

MADD.fmt
MSUB.fmt
NMADD.fmt
NMSUB.fmt

Floating-Point Multiply Add
Floating-Point Multiply Subtract
Floating-Point Negative Multiply Add
Floating-Point Negative Multiply Subtract

MIPS IV
IV
IV
IV

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-21

The initial implementation of the MIPS IV architecture, the R8000 (and future
revisions of it), uses the unrounded arithmetic model which does not match the
IEEE accuracy specification. All other implementations will use the rounded
model which does meet the specification.
•

Rounded or non-fused: The product is rounded according to the
current rounding mode prior to the accumulation. This model meets
the IEEE accuracy specification; the result is numerically identical to
the equivalent computation using multiply, add, subtract, and negate
instructions.

•

Unrounded or fused (R8000 implementation): The product is not
rounded and all bits take part in the accumulation. This model does
not match the IEEE accuracy requirements; the result is more accurate
than the equivalent computation using IEEE multiply, add, subtract,
and negate instructions.

B 6.3 Conversion Instructions
There are instructions to perform conversions among the floating-point and fixedpoint data types. Each instruction converts values from a number of operand
formats to a particular result format. Some convert instructions use the rounding
mode specified in the Floating Control and Status Register (FCSR), others specify
the rounding mode directly.

B-22

Table B-11

FPU Conversion Operations Using the FCSR Rounding Mode

Mnemonic

Description

CVT.S.fmt
CVT.D.fmt
CVT.W.fmt

Floating-Point Convert to Single Floating-Point
Floating-Point Convert to Double Floating-Point
Floating-Point Convert to Word Fixed-Point

CVT.L.fmt

Floating-Point Convert to Long Fixed-Point

Table B-12

FPU Conversion Operations Using a Directed Rounding Mode

Defined in

MIPS I
I
I
I

Mnemonic

Description

ROUND.W.fmt
ROUND.L.fmt

Floating-Point Round to Word Fixed-Point
Floating-Point Round to Long Fixed-Point

II
III

TRUNC.W.fmt
TRUNC.L.fmt

Floating-Point Truncate to Word Fixed-Point
Floating-Point Truncate to Long Fixed-Point

II
III

CEIL.W.fmt
CEIL.L.fmt

Floating-Point Ceiling to Word Fixed-Point
Floating-Point Ceiling to Long Fixed-Point

II
III

FLOOR.W.fmt
FLOOR.L.fmt

Floating-Point Floor to Word Fixed-Point
Floating-Point Floor to Long Fixed-Point

II
III

MIPS IV Instruction Set. Rev 3.2

Defined in

FPU Instruction Set

B 6.4 Formatted Operand Value Move Instructions
These instructions all move formatted operand values among FPU general
registers. A particular operand type must be moved by the instruction that
handles that type. There are three kinds of move instructions:
•

Unconditional move

•

Conditional move that tests an FPU condition code

•

Conditional move that tests a CPU general register value against zero

The conditional move instructions operate in a way that may be unexpected. They
always force the value in the destination register to become a value of the format
specified in the instruction. If the destination register does not contain an operand
of the specified format before the conditional move is executed, the contents
become undefined. There is more information in Values in FP Registers
on page
B-13 and in the individual descriptions of the conditional move instructions
themselves.
Table B-13

FPU Formatted Operand Move Instructions

Mnemonic

Description

MOV.fmt

Floating-Point Move

Table B-14

FPU Conditional Move on True/False Instructions

Mnemonic

Description

Defined in

MOVT.fmt
MOVF.fmt

Floating-Point Move Conditional on FP True
Floating-Point Move Conditional on FP False

MIPS IV
IV

Table B-15

FPU Conditional Move on Zero/Nonzero Instructions

Defined in

MIPS I

Mnemonic

Description

Defined in

MOVZ.fmt
MOVN.fmt

Floating-Point Move Conditional on Zero
Floating-Point Move Conditional on Nonzero

MIPS IV
IV

B 6.5 Conditional Branch Instructions
The FPU has PC-relative conditional branch instructions that test condition codes
set by FPU compare instructions (C.cond.fmt).
All branches have an architectural delay of one instruction. When a branch is
taken, the instruction immediately following the branch instruction, in the branch
delay slot, is executed before the branch to the target instruction takes place.
Conditional branches come in two versions that treat the instruction in the delay
slot differently when the branch is not taken and execution falls through. The
“branch” instructions execute the instruction in the delay slot, but the “branch
likely” instructions do not (they are said to nullify it).

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-23

MIPS I defines a single condition code which is implicit in the compare and branch
instructions. MIPS IV defines seven additional condition codes and includes the
condition code number in the compare and branch instructions. The MIPS IV
extension keeps the original condition bit as condition code zero and the extended
encoding is compatible with the MIPS I encoding.
Table B-16

FPU Conditional Branch Instructions

Mnemonic

Description

BC1T
BC1F

Branch on FP True
Branch on FP False

BC1TL
BC1FL

Branch on FP True Likely
Branch on FP False Likely

Defined in

B 6.6

Miscellaneous Instructions

B 6.6.1

CPU Conditional Move

MIPS I
I
II
II

There are instructions to move conditionally move one CPU general register to
another based on an FPU condition code.
Table B-17

CPU Conditional Move on FPU True/False Instructions

Mnemonic

Description

Defined in

MOVZ
MOVN

Move Conditional on FP True
Move Conditional on FP False

MIPS IV
IV

Valid Operands for FP Instructions
The floating-point unit arithmetic, conversion, and operand move instructions
operate on formatted values with different precision and range limits and produce
formatted values for results. Each representable value in each format has a binary
encoding that is read from or stored to memory. The fmt or fmt3 field of the
instruction encodes the operand format required for the instruction. A conversion
instruction specifies the result type in the function field; the result of other
operations is the same format as the operands. The encoding of the fmt and fmt3
fields is shown in Table B-18.

B-24

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Table B-18

FPU Operand Format Field (fmt, fmt3) Decoding

fmt

fmt3

Instruction
Mnemonic

0-15

Reserved

Size

data type

name

bits

single

floating-point

double

floating-point

18-19

2-3

Reserved

word

fixed-point

long

fixed-point

22–31

6-7

Reserved

Each type of arithmetic or conversion instruction is valid for operands of selected
formats. A summary of the computational and operand move instructions and the
formats valid for each of them is listed in Table B-19. Implementations must
support combinations that are valid either directly in hardware or through
emulation in an exception handler.
The result of an instruction using operand formats marked “U ” is not currently
specified by this architecture and will cause an exception. They are available for
future extensions to the architecture. The exact exception mechanism used is
processor specific. Most implementations report this as an Unimplemented
Operation for a Floating Point exception. Other implementations report these
combinations as Reserved Instruction exceptions.
The result of an instruction using operand formats marked “i” are invalid and an
attempt to execute such an instruction has an undefined result.
Table B-19

Valid Formats for FPU Operations

Mnemonic
ABS
ADD
C.cond
CEIL.L,
(CEIL.W)
CVT.D
CVT.L
CVT.S
CVT.W
DIV
FLOOR.L,
(FLOOR.W)
MADD
MOV

FPU Instruction Set

Operation
Absolute value
Add
Floating-point compare
Convert to longword fixed-point,
round toward +∞
Convert to double floating-point
Convert to longword fixed-point
Convert to single floating-point
Convert to 32-bit fixed-point
Divide
Convert to longword fixed-point,
round toward -∞
Multiply-Add
Move Register

MIPS IV Instruction Set. Rev 3.2

operand fmt
float
fixed
S

•
•
•

COP1
function
W L value
U U
5
U U
0
U U 48–63

•

•
•
i
•
•

i
•
•
•
•

• •
i i
• •
i i
U U

•

•
•

U U
i i

COP1
X op4
value

10 (14)
33
37
32
36
3
11 (15)
4
6

B-25

Mnemonic

Operation

operand fmt
float
fixed
S

MOVC
MOVN
MOVZ
MSUB
MUL
NEG
NMADD
NMSUB
RECIP
ROUND.L,
(ROUND.W)
RSQRT
SQRT
SUB
TRUNC.L
(TRUNC.W)
Key:

D W

FP Move Conditional on condition
• • i
FP Move Conditional on GPR ≠ zero • • i
FP Move Conditional on GPR = zero
• • i
Multiply-Subtract
• • U
Multiply
• • U
Negate
• • U
Negative multiply-Add
• • U
Negative multiply-Subtract
• • U
Reciprocal approximation
• • U
Convert to longword fixed-point,
• • i
round to nearest/even
Reciprocal square root approximation • • U
Square root
• • U
Subtract
• • U
Convert to longword fixed-point,
• • i
round toward zero
• − Valid. U − Unimplemented or Reserved.

i
i
i
U
U
U
U
U
U

COP1
function
value
17
19
18

COP1
X op4
value

5
2
7
6
7
21

8 (12)

U
U
U

22
4
1

9 (13)
i − Invalid.

Description of an Instruction
For the FPU instruction detail documentation, all variable subfields in an
instruction format (such as fs, ft, immediate, and so on) are shown in lower-case.
The instruction name (such as ADD, SUB, and so on) is shown in upper-case.
For the sake of clarity, we sometimes use an alias for a variable subfield in the
formats of specific instructions. For example, we use rs = base in the format for load
and store instructions. Such an alias is always lower case, since it refers to a
variable subfield.
In some instructions, the instruction subfields op and function can have constant
6-bit values. When reference is made to these instructions, upper-case mnemonics
are used. For instance, in the floating-point ADD instruction we use op = COP1
and function = ADD. In other cases, a single field has both fixed and variable
subfields, so the name contains both upper and lower case characters. Bit
encodings for mnemonics are shown at the end of this section, and are also
included with each individual instruction.

Operation Notation Conventions and Functions
The instruction description includes an Operation section that describes the
operation of the instruction in a pseudocode. The pseudocode and terms used in
the description are described in Operation Section Notation and Functions
on
page A-18.

B-26

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

B 10 Individual FPU Instruction Descriptions
The FP instructions are described in alphabetic order. See Description of an
Instruction on page A-15 for a description of the information in each instruction
description.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-27

ABS.fmt

Floating-Point Absolute Value

26 25

31
COP1
010001
6

21 20
fmt
5

16 15

0
00000
5

11 10

6 5

0
ABS
000101
6

MIPS I

Format:

ABS.S fd, fs
ABS.D fd, fs

Purpose:

To compute the absolute value of an FP value.

Description:

fd ← absolute(fs)

The absolute value of the value in FPR fs is placed in FPR fd. The operand and result
are values in format fmt.
This operation is arithmetic; a NaN operand signals invalid operation.

Restrictions:
The fields fs and fd must specify FPRs valid for operands of type fmt; see FloatingPoint Registers on page B-6. If they are not valid, the result is undefined.
The operand must be a value in format fmt; see section B 7 on page B-24. If it is not, the
result is undefined and the value of the operand FPR becomes undefined.

Operation:
StoreFPR(fd, fmt, AbsoluteValue(ValueFPR(fs, fmt)))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation
Invalid Operation

B-28

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

ADD.fmt

Floating-Point Add
26 25

31
COP1
010001
6

21 20

16 15

11 10

6 5

fmt

Format:

ADD.S fd, fs, ft
ADD.D fd, fs, ft

Purpose:

To add FP values.

Description:

fd ← fs + ft

0
ADD
000000
6

MIPS I

The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite
precision, rounded according to the current rounding mode in FCSR, and placed into
FPR fd. The operands and result are values in format fmt.

Restrictions:
The fields fs, ft, and fd must specify FPRs valid for operands of type fmt; see FloatingPoint Registers on page B-6. If they are not valid, the result is undefined.
The operands must be values in format fmt; see section B 7 on page B-24. If they are
not, the result is undefined and the value of the operand FPRs becomes undefined.

Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) + ValueFPR(ft, fmt))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation
Invalid Operation
Inexact
Overflow
Underflow

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-29

BC1F
31

Branch on FP False
26 25

COP1
010001
6

21 20 18 17 16 15

BC
01000
5

cc
3

nd tf
0 0
1 1

0
offset
16

MIPS I
MIPS IV

Format:

BC1F offset
BC1F cc, offset

Purpose:

To test an FP condition code and do a PC-relative conditional branch.

Description:

if (cc = 0) then branch

(cc = 0 implied)

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch (not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
If the FP condition code bit cc is false (0), branch to the effective target address after the
instruction in the delay slot is executed
An FP condition code is set by the FP compare instruction, C.cond.fmt.
The MIPS I architecture defines a single floating-point condition code, implemented as
the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control and Status
register. MIPS I, II, and III architectures must have the cc field set to 0, which is implied
by the first format in the Format section.
The MIPS IV architecture adds seven more condition code bits to the original condition
code 0. FP compare and conditional branch instructions specify the condition code bit
to set or test. Both assembler formats are valid for MIPS IV.

Restrictions:
MIPS I, II, III: There must be at least one instruction between the compare
instruction that sets a condition code and the branch instruction that tests it. Hardware
does not detect a violation of this restriction.
MIPS IV:

B-30

None.

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

BC1F

Branch on FP False
Operation:

MIPS I, II, and III define a single condition code; MIPS IV adds 7 more condition
codes.This operation specification is for the general “Branch On Condition” operation
with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual
instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
MIPS I
I - 1: condition ← COC[1] = tf
I : target_offset← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then

PC ← PC + target
endif
MIPS II and MIPS III:
I - 1: condition ← COC[1] = tf
I : target_offset← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then
PC ← PC + target
else if nd then
NullifyCurrentInstruction()
endif
MIPS IV:
I : condition ← FCC[cc] = tf
target_offset← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then
PC ← PC + target
else if nd then
NullifyCurrentInstruction()
endif

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-31

BC1FL
31

Branch on FP False Likely

26 25
COP1
010001
6

21 20 18 17 16 15

BC
01000
5

cc
3

nd tf
1 0
1 1

0
offset
16

MIPS II
MIPS IV

Format:

BC1FL offset
BC1FL cc, offset

Purpose:

To test an FP condition code and do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.

Description:

if (cc = 0) then branch_likely

(cc = 0 implied)

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch (not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
If the FP condition code bit cc is false (0), branch to the effective target address after the
instruction in the delay slot is executed. If the branch is not taken, the instruction in
the delay slot is not executed.
An FP condition code is set by the FP compare instruction, C.cond.fmt.
The MIPS I architecture defines a single floating-point condition code, implemented as
the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control and Status
register. MIPS I, II, and III architectures must have the cc field set to 0, which is implied
by the first format in the Format section.
The MIPS IV architecture adds seven more condition code bits to the original condition
code 0. FP compare and conditional branch instructions specify the condition code bit
to set or test. Both assembler formats are valid for MIPS IV.

Restrictions:
MIPS II, III: There must be at least one instruction between the compare instruction
that sets a condition code and the branch instruction that tests it. Hardware does not
detect a violation of this restriction.
MIPS IV:

B-32

None.

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

BC1FL

Branch on FP False Likely
Operation:

MIPS II, and III define a single condition code; MIPS IV adds 7 more condition
codes.This operation specification is for the general “Branch On Condition” operation
with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual
instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
MIPS II and MIPS III:
I - 1: condition ← COC[1] = tf
I : target_offset← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then
PC ← PC + target
else if nd then
NullifyCurrentInstruction()
endif
MIPS IV:
I : condition ← FCC[cc] = tf
target_offset← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then
PC ← PC + target
else if nd then
NullifyCurrentInstruction()
endif

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-33

BC1T
31

Branch on FP True
26 25

COP1
010001
6

21 20 18 17 16 15

BC
01000
5

cc
3

nd tf
0 1
1 1

0
offset
16

MIPS I
MIPS IV

Format:

BC1T offset
BC1T cc, offset

Purpose:

To test an FP condition code and do a PC-relative conditional branch.

Description:

if (cc = 1) then branch

(cc = 0 implied)

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch (not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
If the FP condition code bit cc is true (1), branch to the effective target address after the
instruction in the delay slot is executed
An FP condition code is set by the FP compare instruction, C.cond.fmt.
The MIPS I architecture defines a single floating-point condition code, implemented as
the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control and Status
register. MIPS I, II, and III architectures must have the cc field set to 0, which is implied
by the first format in the Format section.
The MIPS IV architecture adds seven more condition code bits to the original condition
code 0. FP compare and conditional branch instructions specify the condition code bit
to set or test. Both assembler formats are valid for MIPS IV.

B-34

None

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Branch on FP True

BC1T

Operation:
MIPS I, II, and III define a single condition code; MIPS IV adds 7 more condition
codes.This operation specification is for the general “Branch On Condition” operation
with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual
instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
MIPS I
I - 1: condition ← COC[1] = tf
I : target ← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then

PC ← PC + target
endif
MIPS II and MIPS III:
I - 1: condition ← COC[1] = tf
I : target ← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then
PC ← PC + target
else if nd then
NullifyCurrentInstruction()
endif
MIPS IV:
I : condition ← FCC[cc] = tf
target ← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then
PC ← PC + target
else if nd then
NullifyCurrentInstruction()
endif

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-35

BC1TL
31

Branch on FP True Likely

26 25
COP1
010001
6

21 20 18 17 16 15

BC
01000
5

cc
3

nd tf
1 1
1 1

0
offset
16

MIPS II
MIPS IV

Format:

BC1TL offset
BC1TL cc, offset

Purpose:

To test an FP condition code and do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.

Description:

if (cc = 1) then branch_likely

(cc = 0 implied)

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address
of the instruction following the branch (not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
If the FP condition code bit cc is true (1), branch to the effective target address after the
instruction in the delay slot is executed. If the branch is not taken, the instruction in
the delay slot is not executed.
An FP condition code is set by the FP compare instruction, C.cond.fmt.
The MIPS I architecture defines a single floating-point condition code, implemented as
the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control and Status
register. MIPS I, II, and III architectures must have the cc field set to 0, which is implied
by the first format in the Format section.
The MIPS IV architecture adds seven more condition code bits to the original condition
code 0. FP compare and conditional branch instructions specify the condition code bit
to set or test. Both assembler formats are valid for MIPS IV.

B-36

None.

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

BC1TL

Branch on FP True Likely
Operation:

MIPS II and MIPS III:
I - 1: condition ← COC[1] = tf
I : target ← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then
PC ← PC + target
else if nd then
NullifyCurrentInstruction()
endif
MIPS IV:
I : condition ← FCC[cc] = tf
target ← (offset15)GPRLEN-(16+2) || offset || 02
I + 1 :if condition then
PC ← PC + target
else if nd then
NullifyCurrentInstruction()
endif

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation

Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes.
Use jump (J) or jump register (JR) instructions to branch to more distant addresses.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-37

C.cond.fmt
31

26 25
COP1
010001
6

Format:

Floating-Point Compare
21 20

fmt
5

C.cond.S
C.cond.D
C.cond.S
C.cond.D

16 15
ft
5

fs, ft
fs, ft
cc, fs, ft
cc, fs, ft

11 10
fs
5

8 7 6 5

4 3

cond

00
2

11
2

(cc = 0 implied)
(cc = 0 implied)

MIPS I
MIPS IV

Purpose:

To compare FP values and record the Boolean result in a condition code.

Description:

cc ← fs compare_cond ft

The value in FPR fs is compared to the value in FPR ft; the values are in format fmt. The
comparison is exact and neither overflows nor underflows. If the comparison specified
by cond2..1 is true for the operand values, then the result is true, otherwise it is false. If
no exception is taken, the result is written into condition code cc; true is 1 and false is 0.
If cond3 is set and at least one of the values is a NaN, an Invalid Operation condition is
raised; the result depends on the FP exception model currently active.
•

Precise exception model: The Invalid Operation flag is set in the FCSR. If the
Invalid Operation enable bit is set in the FCSR, no result is written and an
Invalid Operation exception is taken immediately. Otherwise, the Boolean
result is written into condition code cc.

•

Imprecise exception model (R8000 normal mode): The Boolean result is
written into condition code cc. No FCSR flag is set. If the Invalid Operation
enable bit is set in the FCSR, an Invalid Operation exception is taken,
imprecisely, at some future time.

There are four mutually exclusive ordering relations for comparing floating-point
values; one relation is always true and the others are false. The familiar relations are
greater than, less than, and equal. In addition, the IEEE floating-point standard defines
the relation unordered which is true when at least one operand value is NaN; NaN
compares unordered with everything, including itself. Comparisons ignore the sign of
zero, so +0 equals -0.
The comparison condition is a logical predicate, or equation, of the ordering relations
such as “less than or equal”, “equal”, “not less than”, or “unordered or equal”.
Compare distinguishes sixteen comparison predicates. The Boolean result of the
instruction is obtained by substituting the Boolean value of each ordering relation for
the two FP values into equation. If the equal relation is true, for example, then all four
example predicates above would yield a true result. If the unordered relation is true
then only the final predicate, “unordered or equal” would yield a true result.

B-38

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

C.cond.fmt

Floating-Point Compare

Logical negation of a compare result allows eight distinct comparisons to test for
sixteen predicates as shown in Table B-20. Each mnemonic tests for both a predicate
and its logical negation. For each mnemonic, compare tests the truth of the first
predicate. When the first predicate is true, the result is true as shown in the “if
predicate is true” column (note that the False predicate is never true and False/True do
not follow the normal pattern). When the first predicate is true, the second predicate
must be false, and vice versa. The truth of the second predicate is the logical negation
of the instruction result. After a compare instruction, test for the truth of the first
predicate with the Branch on FP True (BC1T) instruction and the truth of the second
with Branch on FP False (BC1F).
Table B-20

FPU Comparisons Without Special Operand Exceptions

Instr

name of predicate and
cond logically negated predicate (abbreviation)
Mnemonic
F
UN
EQ

ULT
OLE
ULE

Inv
If
Op
predexcp
icate
> < = ? is true if Q
NaN
relation
values

False

[this predicate is always False, F F F F

True (T)

it never has a True result]

T T T T

Instr
cond
field
3 2..0

Unordered

F F F T

Ordered (OR)

T T T F

Equal

F F T F

Not Equal (NEQ)

T T F T

F F T T

Ordered or Greater than or Less than (OGL) T T F F

Ordered or Less Than

F T F F

Unordered or Greater than or Equal (UGE)

T F T T

Unordered or Less Than

F T F T

Ordered or Greater than or Equal (OGE)

T F T F

Ordered or Less than or Equal

F T T F

Unordered or Greater Than (UGT)

T F F T

Unordered or Less than or Equal

F T T T

Ordered or Greater Than (OGT)

T F F F

UEQ Unordered or Equal
OLT

Comparison
CC Result

Comparison Predicate

0
1
2
3
No

0
4
5
6
7

key: “?” = unordered, “>” = greater than, “<“ = less than, “=” is equal,“T ” = True, “F” = False

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-39

C.cond.fmt

Floating-Point Compare

There is another set of eight compare operations, distinguished by a cond3 value of 1,
testing the same sixteen conditions. For these additional comparisons, if at least one of
the operands is a NaN, including Quiet NaN, then an Invalid Operation condition is
raised. If the Invalid Operation condition is enabled in the FCSR, then an Invalid
Operation exception occurs.
Table B-21

FPU Comparisons With Special Operand Exceptions for QNaNs

Instr

name of predicate and
cond logically negated predicate (abbreviation)
Mnemonic
SF

Comparison
CC Result

Comparison Predicate
relation
values

Inv
If
Op
predexcp
icate
> < = ? is true if Q
NaN

Signaling False [this predicate always False] F F F F
Signaling True (ST)

T T T T

NGLE Not Greater than or Less than or Equal

Greater than or Less than or Equal (GLE)

T T T F

Signaling Equal

F F T F

Signaling Not Equal (SNE)

T T F T

NGL Not Greater than or Less than

F F T T

Greater than or Less than (GL)

T T F F

Less than

F T F F

Not Less Than (NLT)

T F T T

NGE Not Greater than or Equal

F T F T

Greater than or Equal (GE)

T F T F

Less than or Equal

F T T F

Not Less than or Equal (NLE)

T F F T

F T T T

T F F F

NGT Not Greater than
Greater than (GT)

cond
field
3 2..0

F F F T

SEQ

Instr

0
1
2
3
Yes

1
4
5
6
7

key: “?” = unordered, “>” = greater than, “<“ = less than, “=” is equal,“T ” = True, “F” = False
The instruction encoding is an extension made in the MIPS IV architecture. In previous
architecture levels the cc field for this instruction must be 0.
The MIPS I architecture defines a single floating-point condition code, implemented as
the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control and Status
register. MIPS I, II, and III architectures must have the cc field set to 0, which is implied
by the first format in the Format section.

B-40

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

C.cond.fmt

Floating-Point Compare

The MIPS IV architecture adds seven more condition code bits to the original condition
code 0. FP compare and conditional branch instructions specify the condition code bit
to set or test. Both assembler formats are valid for MIPS IV.

Restrictions:
The fields fs and ft must specify FPRs valid for operands of type fmt; see FloatingPoint Registers on page B-6. If they are not valid, the result is undefined.
The operands must be values in format fmt; see section B 7 on page B-24. If they are
not, the result is undefined and the value of the operand FPRs becomes undefined.

MIPS I, II, III: There must be at least one instruction between the compare
instruction that sets a condition code and the branch instruction that tests it. Hardware
does not detect a violation of this restriction.

Operation:
if NaN(Value FPR(fs, fmt)) or NaN(ValueFPR(ft, fmt)) then
less ← false
equal ← false
unordered ← true
if t then
SignalException(InvalidOperation)
endif
else
less ← ValueFPR(fs, fmt) < ValueFPR(ft, fmt)
equal ← ValueFPR(fs, fmt) = ValueFPR(ft, fmt)
unordered ← false
endif
condition ← (cond2 and less) or (cond1 and equal) or (cond0 and unordered)
FCC[cc] ← condition
if cc = 0 then
COC[1] ← condition
endif

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation
Invalid Operation

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-41

C.cond.fmt

Floating-Point Compare

Programming Notes:
FP computational instructions, including compare, that receive an operand value of
Signaling NaN, will raise the Invalid Operation condition. The comparisons that raise
the Invalid Operation condition for Quiet NaNs in addition to SNaNs, permit a simpler
programming model if NaNs are errors. Using these compares, programs do not need
explicit code to check for QNaNs causing the unordered relation. Instead, they take an
exception and allow the exception handling system to deal with the error when it
occurs. For example, consider a comparison in which we want to know if two numbers
are equal, but for which unordered would be an error.
# comparisons using explicit tests for QNaN
c.eq.d $f2,$f4 # check for equal
nop
bc1t
L2
# it is equal
c.un.d $f2,$f4 # it is not equal, but might be unordered
bc1t
ERROR# unordered goes off to an error handler
# not-equal-case code here
...
# equal-case code here
L2:
# -------------------------------------------------------------# comparison using comparisons that signal QNaN
c.seq.d $f2,$f4 # check for equal
nop
bc1t
L2
# it is equal
nop
# it is not unordered here...
# not-equal-case code here
...
#equal-case code here
L2:

B-42

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

CEIL.L.fmt

Floating-Point Ceiling Convert to Long Fixed-Point
26 25

31
COP1
010001
6

21 20
fmt
5

16 15

0
00000
5

11 10

6 5

0
CEIL.L
001010
6

MIPS III

Format:

CEIL.L.S fd, fs
CEIL.L.D fd, fs

Purpose:

To convert an FP value to 64-bit fixed-point, rounding up.

Description:

fd ← convert_and_round(fs)

The value in FPR fs in format fmt, is converted to a value in 64-bit long fixed-point
format rounding toward +∞ (rounding mode 2). The result is placed in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-263 to 263-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active.
•

Precise exception model: The Invalid Operation flag is set in the FCSR. If the
Invalid Operation enable bit is set in the FCSR, no result is written to fd and an
Invalid Operation exception is taken immediately. Otherwise, the default
result, 263–1, is written to fd.

•

Imprecise exception model (R8000 normal mode): The default result, 263–1, is
written to fd. No FCSR flag is set. If the Invalid Operation enable bit is set in
the FCSR, an Invalid Operation exception is taken, imprecisely, at some future
time.

Restrictions:
The fields fs and fd must specify valid FPRs; fs for type fmt and fd for long fixed-point;
see Floating-Point Registers
on page B-6. If they are not valid, the result is
undefined.
The operand must be a value in format fmt; see section B 7 on page B-24. If it is not, the
result is undefined and the value of the operand FPR becomes undefined.

Operation:
StoreFPR(fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Invalid Operation
Inexact

FPU Instruction Set

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

B-43

CEIL.W.fmt
26 25

31
COP1
010001
6

Floating-Point Ceiling Convert to Word Fixed-Point
21 20

fmt
5

16 15

0
00000
5

11 10

6 5

0
CEIL.W
001110
6

MIPS II

Format:

CEIL.W.S fd, fs
CEIL.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point, rounding up.

Description:

fd ← convert_and_round(fs)

The value in FPR fs in format fmt, is converted to a value in 32-bit word fixed-point
format rounding toward +∞ (rounding mode 2). The result is placed in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-231 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active.
•

•

Imprecise exception model (R8000 normal mode): The default result, 231–1, is
written to fd. No FCSR flag is set. If the Invalid Operation enable bit is set in
the FCSR, an Invalid Operation exception is taken, imprecisely, at some future
time.

Restrictions:
The fields fs and fd must specify valid FPRs; fs for type fmt and fd for word fixed-point;
see Floating-Point Registers
on page B-6. If they are not valid, the result is
undefined.
The operand must be a value in format fmt; see section B 7 on page B-24. If it is not, the
result is undefined and the value of the operand FPR becomes undefined.

Operation:
StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Invalid Operation
Unimplemented Operation
Inexact
Overflow

B-44

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

CFC1

Move Control Word from Floating-Point
31

26 25
COP1
010001
6

21 20

CF
00010
5

16 15

11 10

0
0
000 0000 0000
11

MIPS I

Format:
Purpose:

CFC1 rt, fs

Description:

rt ← FP_Control[fs]

To copy a word from an FPU control register to a GPR.

Copy the 32-bit word from FP (coprocessor 1) control register fs into GPR rt, signextending it if the GPR is 64 bits.

Restrictions:
There are only a couple control registers defined for the floating-point unit. The result
is not defined if fs specifies a register that does not exist.
For MIPS I, MIPS II, and MIPS III, the contents of GPR rt are undefined for the
instruction immediately following CFC1.

Operation: MIPS I - III
I : temp
← FCR[fs]
I + 1 :GPR[rt] ← sign_extend(temp)

Operation: MIPS IV
temp ← FCR[fs]
GPR[rt]← sign_extend(temp)

Exceptions:
Coprocessor Unusable

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-45

CTC1
31

Move Control Word to Floating-Point
26 25

COP1
010001
6

21 20

CT
00110
5

16 15

11 10

0
0
000 0000 0000
11

MIPS I

Format:
Purpose:

CTC1 rt, fs

Description:

FP_Control[fs] ← rt

To copy a word from a GPR to an FPU control register.

Copy the low word from GPR rt into FP (coprocessor 1) control register fs.
Writing to control register 31, the Floating-Point Control and Status Register or FCSR,
causes the appropriate exception if any cause bit and its corresponding enable bit are
both set. The register will be written before the exception occurs.

Restrictions:
There are only a couple control registers defined for the floating-point unit. The result
is not defined if fs specifies a register that does not exist.
For MIPS I, MIPS II, and MIPS III, the contents of floating-point control register fs are
undefined for the instruction immediately following CTC1.

Operation: MIPS I - III
I : temp
← GPR[rt]31..0
I + 1 :FCR[fs] ← temp

COC[1] ← FCR[31]23

Operation: MIPS IV
temp ← GPR[rt]31..0
FCR[fs] ← temp
COC[1] ← FCR[31]23

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation
Invalid Operation
Division-by-zero
Inexact
Overflow
Underflow

B-46

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

CVT.D.fmt

Floating-Point Convert to Double Floating-Point
26 25

31
COP1
010001
6

Format:

21 20
fmt
5

CVT.D.S
CVT.D.W
CVT.D.L

16 15

0
00000
5

11 10

6 5

fd, fs
fd, fs
fd, fs

Purpose:

To convert an FP or fixed-point value to double FP.

Description:

fd ← convert_and_round(fs)

0
CVT.D
100001
6

MIPS I
MIPS III

The value in FPR fs in format fmt is converted to a value in double floating-point format
rounded according to the current rounding mode in FCSR. The result is placed in FPR
fd.
If fmt is S or W, then the operation is always exact.

Restrictions:
The fields fs and fd must specify valid FPRs; fs for type fmt and fd for double floatingpoint; see Floating-Point Registers
on page B-6. If they are not valid, the result is
undefined.
The operand must be a value in format fmt; see section B 7 on page B-24. If it is not, the
result is undefined and the value of the operand FPR becomes undefined.

Operation:
StoreFPR (fd, D, ConvertFmt(ValueFPR(fs, fmt), fmt, D))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Invalid Operation
Unimplemented Operation
Inexact
Overflow
Underflow

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-47

CVT.L.fmt
31

Floating-Point Convert to Long Fixed-Point

26 25

COP1
010001
6

21 20
fmt

16 15

0
00000
5

11 10

6 5

Format:

CVT.L.S fd, fs
CVT.L.D fd, fs

Purpose:

To convert an FP value to a 64-bit fixed-point.

Description:

fd ← convert_and_round(fs)

0
CVT.L
100101
6

MIPS III

Convert the value in format fmt in FPR fs to long fixed-point format, round according
to the current rounding mode in FCSR, and place the result in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-263 to 263-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active:
•

•

Operation:
StoreFPR (fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Invalid Operation
Unimplemented Operation
Inexact
Overflow

B-48

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

CVT.S.fmt

Floating-Point Convert to Single Floating-Point
31

26 25

COP1
010001
6

Format:

21 20
fmt
5

CVT.S.D
CVT.S.W
CVT.S.L

16 15

0
00000
5

11 10

6 5

fd, fs
fd, fs
fd, fs

Purpose:

To convert an FP or fixed-point value to single FP.

Description:

fd ← convert_and_round(fs)

0
CVT.S
100000
6

MIPS I
MIPS III

The value in FPR fs in format fmt is converted to a value in single floating-point format
rounded according to the current rounding mode in FCSR. The result is placed in FPR
fd.

Restrictions:
The fields fs and fd must specify valid FPRs; fs for type fmt and fd for single floatingpoint; see Floating-Point Registers
on page B-6. If they are not valid, the result is
undefined.
The operand must be a value in format fmt; see section B 7 on page B-24. If it is not, the
result is undefined and the value of the operand FPR becomes undefined.

Operation:
StoreFPR(fd, S, ConvertFmt(ValueFPR(fs, fmt), fmt, S))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Invalid Operation
Unimplemented Operation
Inexact
Overflow
Underflow

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-49

CVT.W.fmt
31

Floating-Point Convert to Word Fixed-Point

26 25

COP1
010001
6

21 20
fmt
5

16 15

0
00000
5

11 10

6 5

Format:

CVT.W.S fd, fs
CVT.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point.

Description:

fd ← convert_and_round(fs)

0
CVT.W
100100
6

MIPS I

The value in FPR fs in format fmt is converted to a value in 32-bit word fixed-point
format rounded according to the current rounding mode in FCSR. The result is placed
in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-231 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active.
•

•

Operation:
StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Invalid Operation
Unimplemented Operation
Inexact
Overflow

B-50

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

DIV.fmt

Floating-Point Divide
31

26 25

COP1
010001
6

21 20

16 15

11 10

6 5

fmt

Format:

DIV.S fd, fs, ft
DIV.D fd, fs, ft

Purpose:

To divide FP values.

Description:

fd ← fs / ft

0
DIV
000011
6

MIPS I

The value in FPR fs is divided by the value in FPR ft. The result is calculated to infinite
precision, rounded according to the current rounding mode in FCSR, and placed into
FPR fd. The operands and result are values in format fmt.

Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) / ValueFPR(ft, fmt))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Division-by-zero
Overflow

FPU Instruction Set

Unimplemented Operation
Invalid Operation
Underflow

MIPS IV Instruction Set. Rev 3.2

B-51

DMFC1
31

Doubleword Move From Floating-Point

26 25
COP1
010001
6

21 20

DMF
00001
5

Format:
Purpose:

DMFC1 rt, fs

Description:

rt ← fs

16 15

11 10

0
0 0 0 0 0 0 0 0 0 00
11

MIPS III

To copy a doubleword from an FPR to a GPR.

The doubleword contents of FPR fs are placed into GPR rt.
If the coprocessor 1 general registers are 32-bits wide (a native 32-bit processor or 32bit register emulation mode in a 64-bit processor), FPR fs is held in an even/odd
register pair. The low word is taken from the even register fs and the high word is from
fs+1.

Restrictions:
If fs does not specify an FPR that can contain a doubleword, the result is undefined; see
Floating-Point Registers
on page B-6.
For MIPS III, the contents of GPR rt are undefined for the instruction immediately
following DMFC1.

Operation: MIPS I - III
if SizeFGR() = 64 then
data ← FGR[fs]
elseif fs0 = 0 then
data ← FGR[fs+1] || FGR[fs]
else
UndefinedResult()
endif
I + 1 : GPR[rt] ← data
I:

/* 64-bit wide FGRs */
/* valid specifier, 32-bit wide FGRs */
/* undefined for odd 32-bit FGRs */

Operation: MIPS IV
if SizeFGR() = 64 then
data ← FGR[fs]
elseif fs0 = 0 then
data ← FGR[fs+1] || FGR[fs]
else
UndefinedResult()
endif
GPR[rt] ← data

/* 64-bit wide FGRs */
/* valid specifier, 32-bit wide FGRs */
/* undefined for odd 32-bit FGRs */

Exceptions:
Reserved Instruction
Coprocessor Unusable
B-52

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Doubleword Move To Floating-Point
31

26 25
COP1
010001
6

21 20

DMT
00101
5

Format:
Purpose:

DMTC1 rt, fs

Description:

fs ← rt

DMTC1

16 15

11 10

0
0 0 0 0 0 0 0 0 0 00
11

MIPS III

To copy a doubleword from a GPR to an FPR.

The doubleword contents of GPR rt are placed into FPR fs.
If coprocessor 1 general registers are 32-bits wide (a native 32-bit processor or 32-bit
register emulation mode in a 64-bit processor), FPR fs is held in an even/odd register
pair. The low word is placed in the even register fs and the high word is placed in fs+1.

Restrictions:
If fs does not specify an FPR that can contain a doubleword, the result is undefined; see
Floating-Point Registers
on page B-6.
For MIPS III, the contents of FPR fs are undefined for the instruction immediately
following DMTC1.

Operation: MIPS I - III
I : data ← GPR[rt]
I + 1 :if SizeFGR() = 64 then

FGR[fs] ← data
elseif fs0 = 0 then
FGR[fs+1] ← data63..32
FGR[fs] ← data31..0
else
UndefinedResult()
endif

/* 64-bit wide FGRs */
/* valid specifier, 32-bit wide FGRs */

/* undefined result for odd 32-bit FGRs */

Operation: MIPS IV
data ← GPR[rt]
if SizeFGR() = 64 then
FGR[fs] ← data
elseif fs0 = 0 then
FGR[fs+1] ← data63..32
FGR[fs] ← data31..0
else
UndefinedResult()
endif

FPU Instruction Set

/* 64-bit wide FGRs */
/* valid specifier, 32-bit wide FGRs */

/* undefined result for odd 32-bit FGRs */

MIPS IV Instruction Set. Rev 3.2

B-53

DMTC1

Doubleword Move To Floating-Point

Exceptions:
Reserved Instruction
Coprocessor Unusable

B-54

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

FLOOR.L.fmt

Floating-Point Floor Convert to Long Fixed-Point
31

26 25
COP1
010001
6

21 20
fmt
5

16 15

0
00000
5

11 10

6 5

0
FLOOR.L
001011
6

MIPS III

Format:

FLOOR.L.S fd, fs
FLOOR.L.D fd, fs

Purpose:

To convert an FP value to 64-bit fixed-point, rounding down.

Description:

fd ← convert_and_round(fs)

The value in FPR fs in format fmt, is converted to a value in 64-bit long fixed-point
format rounding toward -∞ (rounding mode 3). The result is placed in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-263 to 263-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active.
•

•

Operation:
StoreFPR(fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Invalid Operation
Inexact

FPU Instruction Set

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

B-55

FLOOR.W.fmt Floating-Point Floor Convert to Word Fixed-Point
31

26 25

COP1
010001
6

21 20
fmt
5

16 15

0
00000
5

11 10

6 5

0
FLOOR.W
001111
6

MIPS II

Format:

FLOOR.W.S fd, fs
FLOOR.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point, rounding down.

Description:

fd ← convert_and_round(fs)

The value in FPR fs in format fmt, is converted to a value in 32-bit word fixed-point
format rounding toward –∞ (rounding mode 3). The result is placed in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-231 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active.
•

•

Operation:
StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Invalid Operation
Inexact

B-56

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

LDC1

Load Doubleword to Floating-Point
31

26 25
LDC1
110101
6

21 20

16 15

base

offset

Format:
Purpose:

LDC1 ft, offset(base)

Description:

ft ← memory[base+offset]

MIPS II

To load a doubleword from memory to an FPR.

The contents of the 64-bit doubleword at the memory location specified by the aligned
effective address are fetched and placed in FPR ft. The 16-bit signed offset is added to
the contents of GPR base to form the effective address.
If coprocessor 1 general registers are 32-bits wide (a native 32-bit processor or 32-bit
register emulation mode in a 64-bit processor), FPR ft is held in an even/odd register
pair. The low word is placed in the even register ft and the high word is placed in ft+1.

Restrictions:
If ft does not specify an FPR that can contain a doubleword, the result is undefined; see
Floating-Point Registers
on page B-6.
An Address Error exception occurs if EffectiveAddress2..0 ≠ 0 (not doublewordaligned).
MIPS IV: The low-order 3 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:
vAddr ← sign_extend(offset) + GPR[base]
if vAddr2..0 ≠ 03 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
data ← LoadMemory(uncached, DOUBLEWORD, pAddr, vAddr, DATA)
if SizeFGR() = 64 then
/* 64-bit wide FGRs */
FGR[ft] ← data
elseif ft0 = 0 then
/* valid specifier, 32-bit wide FGRs */
FGR[ft+1] ← data63..32
FGR[ft] ← data31..0
else
/* undefined result for odd 32-bit FGRs */
UndefinedResult()
endif

Exceptions:
Coprocessor unusable
Reserved Instruction
TLB Refill, TLB Invalid
Address Error
FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-57

LDXC1
31

Load Doubleword Indexed to Floating-Point

26 25

21 20

16 15

11 10

COP1X
010011

base

index

LDXC1
000001

Format:
Purpose:

LDXC1 fd, index(base)

Description:

fd ← memory[base+index]

MIPS IV

To load a doubleword from memory to an FPR (GPR+GPR addressing).

The contents of the 64-bit doubleword at the memory location specified by the aligned
effective address are fetched and placed in FPR fd. The contents of GPR index and GPR
base are added to form the effective address.
If coprocessor 1 general registers are 32-bits wide (a native 32-bit processor or 32-bit
register emulation mode in a 64-bit processor), FPR fd is held in an even/odd register
pair. The low word is placed in the even register fd and the high word is placed in fd+1.

Restrictions:
If fd does not specify an FPR that can contain a doubleword, the result is undefined; see
Floating-Point Registers
on page B-6.
The Region bits of the effective address must be supplied by the contents of base. If
EffectiveAddress63..62 ≠ base63..62, the result is undefined.
An Address Error exception occurs if EffectiveAddress2..0 ≠ 0 (not doublewordaligned).
MIPS IV: The low-order 3 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:
vAddr ← GPR[base] + GPR[index]
if vAddr2..0 ≠ 03 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
mem ← LoadMemory(unchched, DOUBLEWORD, pAddr, vAddr, DATA)
if SizeFGR() = 64 then
/* 64-bit wide FGRs */
FGR[fd] ← data
elseif fd0 = 0 then
/* valid specifier, 32-bit wide FGRs */
FGR[fd+1] ← data63..32
FGR[fd] ← data31..0
else
/* undefined result for odd 32-bit FGRs */
UndefinedResult()
endif

B-58

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

LDXC1

Load Doubleword Indexed to Floating-Point
Exceptions:
TLB Refill, TLB Invalid
Address Error
Reserved Instruction
Coprocessor Unusable

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-59

LWC1
31

Load Word to Floating-Point
26 25

LWC1
110001
6

21 20

16 15

base

offset

Format:
Purpose:

LWC1 ft, offset(base)

Description:

ft ← memory[base+offset]

MIPS I

To load a word from memory to an FPR.

The contents of the 32-bit word at the memory location specified by the aligned
effective address are fetched and placed into the low word of coprocessor 1 general
register ft. The 16-bit signed offset is added to the contents of GPR base to form the
effective address.
If coprocessor 1 general registers are 64-bits wide, bits 63..32 of register ft become
undefined. See Floating-Point Registers
on page B-6.

Restrictions:
An Address Error exception occurs if EffectiveAddress1..0 ≠ 0 (not word-aligned).
MIPS IV: The low-order 2 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation: 32-bit Processors
/* “mem” is aligned 64-bits from memory. Pick out correct bytes. */
vAddr ← sign_extend(offset) + GPR[base]
if vAddr1..0 ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
mem ← LoadMemory(uncached, WORD, pAddr, vAddr, DATA)
I + 1 :FGR[ft] ← mem
I:

Operation: 64-bit Processors
/* “mem” is aligned 64-bits from memory. Pick out correct bytes. */
vAddr ← sign_extend(offset) + GPR[base]
if vAddr1..0 ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
mem ← LoadMemory(uncached, WORD, pAddr, vAddr, DATA)
bytesel ← vAddr2..0 xor (BigEndianCPU || 02)
if SizeFGR() = 64 then
/* 64-bit wide FGRs */
FGR[ft] ← undefined32 || mem31+8*bytesel..8*bytesel
else
/* 32-bit wide FGRs */
FGR[ft] ← mem31+8*bytesel..8*bytesel
endif

B-60

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

LWC1

Load Word to Floating-Point
Exceptions:
Coprocessor unusable
Reserved Instruction
TLB Refill, TLB Invalid
Address Error

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-61

LWXC1
31

Load Word Indexed to Floating-Point

26 25

21 20

16 15

11 10

COP1X
010011

base

index

LWXC1
000000

Format:
Purpose:

LWXC1 fd, index(base)

Description:

fd ← memory[base+index]

MIPS IV

To load a word from memory to an FPR (GPR+GPR addressing).

The contents of the 32-bit word at the memory location specified by the aligned
effective address are fetched and placed into the low word of coprocessor 1 general
register fd. The contents of GPR index and GPR base are added to form the effective
address.
If coprocessor 1 general registers are 64-bits wide, bits 63..32 of register fd become
undefined. See Floating-Point Registers
on page B-6.

Restrictions:
The Region bits of the effective address must be supplied by the contents of base. If
EffectiveAddress63..62 ≠ base63..62, the result is undefined.
An Address Error exception occurs if EffectiveAddress1..0 ≠ 0 (not word-aligned).
MIPS IV: The low-order 2 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:
vAddr ← GPR[base] + GPR[index]
if vAddr1..0 ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
/* “mem” is aligned 64-bits from memory. Pick out correct bytes. */
mem ← LoadMemory(uncached, WORD, pAddr, vAddr, DATA)
bytesel ← vAddr2..0 xor (BigEndianCPU || 02)
if SizeFGR() = 64 then
/* 64-bit wide FGRs */
FGR[fd] ← undefined32 || mem31+8*bytesel..8*bytesel
else
/* 32-bit wide FGRs */
FGR[fd] ← mem31+8*bytesel..8*bytesel
endif

Exceptions:
TLB Refill, TLB Invalid
Address Error
Reserved Instruction
Coprocessor Unusable

B-62

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

MADD.fmt

Floating-Point Multiply Add
31

26 25
COP1X
010011
6

21 20

11 10

16 15

6 5

3 2

MADD
100
3

fmt
3

MIPS IV

Format:

MADD.S fd, fr, fs, ft
MADD.D fd, fr, fs, ft

Purpose:

To perform a combined multiply-then-add of FP values.

Description:

fd ← (fs × ft) + fr

The value in FPR fs is multiplied by the value in FPR ft to produce a product. The value
in FPR fr is added to the product. The result sum is calculated to infinite precision,
rounded according to the current rounding mode in FCSR, and placed into FPR fd. The
operands and result are values in format fmt.
The accuracy of the result depends which of two alternative arithmetic models is used
by the implementation for the computation. The numeric models are explained in
Arithmetic Instructions
on page B-21.

Restrictions:
The fields fr, fs, ft, and fd must specify FPRs valid for operands of type fmt; see
Floating-Point Registers
on page B-6. If they are not valid, the result is undefined.
The operands must be values in format fmt; see section B 7 on page B-24. If they are
not, the result is undefined and the value of the operand FPRs becomes undefined.

Operation:
vfr ← ValueFPR(fr, fmt)
vfs ← ValueFPR(fs, fmt)
vft ← ValueFPR(ft, fmt)
StoreFPR(fd, fmt, vfr + vfs * vft)

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Invalid Operation
Underflow

FPU Instruction Set

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

B-63

MFC1
31

Move Word From Floating-Point
26 25

COP1
010001
6

21 20

MF
00000
5

Format:
Purpose:

MFC1 rt, fs

Description:

rt ← fs

16 15

11 10

0
0
000 0000 0000
11

MIPS I

To copy a word from an FPU (CP1) general register to a GPR.

The low word from FPR fs is placed into the low word of GPR rt. If GPR rt is 64 bits
wide, then the value is sign extended. See Floating-Point Registers
on page B-6.

Restrictions:
For MIPS I, MIPS II, and MIPS III the contents of GPR rt are undefined for the
instruction immediately following MFC1.

Operation: MIPS I - III
I : word
← FGR[fs]31..0
I + 1 :GPR[rt] ← sign_extend(word)

Operation: MIPS IV
word ← FGR[fs]31..0
GPR[rt]← sign_extend(word)

Exceptions:
Coprocessor Unusable

B-64

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

MOV.fmt

Floating-Point Move
31

26 25

COP1
010001
6

21 20
fmt
5

16 15

0
00000
5

11 10

6 5

0
MOV
000110
6

MIPS I

Format:

MOV.S fd, fs
MOV.D fd, fs

Purpose:

To move an FP value between FPRs.

Description:

fd ← fs

The value in FPR fs is placed into FPR fd. The source and destination are values in
format fmt.
The move is non-arithmetic; it causes no IEEE 754 exceptions.

Operation:
StoreFPR(fd, fmt, ValueFPR(fs, fmt))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-65

MOVF
31

Move Conditional on FP False

26 25

21 20 18 17 16 15

SPECIAL
000000

5
6

Format:
Purpose:

MOVF

rd, rs, cc

Description:

if (cc = 0) then rd ← rs

0 tf
0 0
1 1

11 10
rd
5

6 5
0

00000
5

0
MOVCI
000001
6

MIPS IV

To test an FP condition code then conditionally move a GPR.

If the floating-point condition code specified by cc is zero, then the contents of GPR rs
are placed into GPR rd.

Restrictions:
None

Operation:
active ← FCC[cc] = tf
if active then
GPR[rd] ← GPR[rs]
endif

Exceptions:
Reserved Instruction
Coprocessor Unusable

B-66

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

MOVF.fmt

Floating-Point Move Conditional on FP False
31

26 25

21 20 18 17 16 15

11 10

6 5

COP1
010001

fmt

5
6

Format:

MOVF.S
MOVF.D

fd, fs, cc
fd, fs, cc

Purpose:

To test an FP condition code then conditionally move an FP value.

Description:

if (cc = 0) then fd ← fs

0 tf
0 0
1 1

MOVCF
010001
6

MIPS IV

If the floating-point condition code specified by cc is zero, then the value in FPR fs is
placed into FPR fd. The source and destination are values in format fmt.
If the condition code is not zero, then FPR fs is not copied and FPR fd contains its
previous value in format fmt. If fd did not contain a value either in format fmt or
previously unused data from a load or move-to operation that could be interpreted in
format fmt, then the value of fd becomes undefined.
The move is non-arithmetic; it causes no IEEE 754 exceptions.

Operation:
if FCC[cc] = tf then
StoreFPR(fd, fmt, ValueFPR(fs, fmt))
else
StoreFPR(fd, fmt, ValueFPR(fd, fmt))
endif

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented operation

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-67

MOVN.fmt
31

26 25

COP1
010001
6

Floating-Point Move Conditional on Not Zero
16 15

21 20

11 10

6 5

fmt

Format:

MOVN.S
MOVN.D

Purpose:

To test a GPR then conditionally move an FP value.

Description:

if (rt ≠ 0) then fd ← fs

fd, fs, rt
fd, fs, rt

MOVN
010011
6

MIPS IV

If the value in GPR rt is not equal to zero then the value in FPR fs is placed in FPR fd.
The source and destination are values in format fmt.
If GPR rt contains zero, then FPR fs is not copied and FPR fd contains its previous value
in format fmt. If fd did not contain a value either in format fmt or previously unused
data from a load or move-to operation that could be interpreted in format fmt, then the
value of fd becomes undefined.
The move is non-arithmetic; it causes no IEEE 754 exceptions.

Operation:
if GPR[rt] ≠ 0 then
StoreFPR(fd, fmt, ValueFPR(fs, fmt))
else
StoreFPR(fd, fmt, ValueFPR(fd, fmt))
endif

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented operation

B-68

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Move Conditional on FP True
31

26 25

MOVT

21 20 18 17 16 15

SPECIAL
000000

Format:
Purpose:

MOVT

rd, rs, cc

Description:

if (cc = 1) then rd ← rs

0
0
1

tf
1
1

11 10
0

rd
5

6 5

00000
5

0
MOVCI
000001
6

MIPS IV

To test an FP condition code then conditionally move a GPR.

If the floating-point condition code specified by cc is one then the contents of GPR rs
are placed into GPR rd.

Restrictions:
None

Operation:
if FCC[cc] = tf then
GPR[rd] ← GPR[rs]
endif

Exceptions:
Reserved Instruction
Coprocessor Unusable

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-69

MOVT.fmt
31

26 25

Floating-Point Move Conditional on FP True
21 20 18 17 16 15

COP1
010001

fmt

0 tf
0 1
1 1

11 10

6 5

0
MOVCF
010001
6

MIPS IV

Format:

MOVT.S fd, fs, cc
MOVT.D fd, fs, cc

Purpose:

To test an FP condition code then conditionally move an FP value.

Description:

if (cc = 1) then fd ← fs

If the floating-point condition code specified by cc is one then the value in FPR fs is
placed into FPR fd. The source and destination are values in format fmt.
If the condition code is not one, then FPR fs is not copied and FPR fd contains its
previous value in format fmt. If fd did not contain a value either in format fmt or
previously unused data from a load or move-to operation that could be interpreted in
format fmt, then the value of fd becomes undefined.
The move is non-arithmetic; it causes no IEEE 754 exceptions.

Operation:
if FCC[cc] = tf then
StoreFPR(fd, fmt, ValueFPR(fs, fmt))
else
StoreFPR(fd, fmt, ValueFPR(fd, fmt))
endif

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented operation

B-70

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

MOVZ.fmt

Floating-Point Move Conditional on Zero
31

26 25

COP1
010001
6

16 15

21 20

11 10

6 5

fmt

Format:

MOVZ.S fd, fs, rt
MOVZ.D fd, fs, rt

Purpose:

To test a GPR then conditionally move an FP value.

Description:

if (rt = 0) then fd ← fs

MOVZ
010010
6

MIPS IV

If the value in GPR rt is equal to zero then the value in FPR fs is placed in FPR fd. The
source and destination are values in format fmt.
If GPR rt is not zero, then FPR fs is not copied and FPR fd contains its previous value in
format fmt. If fd did not contain a value either in format fmt or previously unused data
from a load or move-to operation that could be interpreted in format fmt, then the value
of fd becomes undefined.
The move is non-arithmetic; it causes no IEEE 754 exceptions.

Operation:
if GPR[rt] = 0 then
StoreFPR(fd, fmt, ValueFPR(fs, fmt))
else
StoreFPR(fd, fmt, ValueFPR(fd, fmt))
endif

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented operation

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-71

MSUB.fmt
31

Floating-Point Multiply Subtract

26 25
COP1X
010011
6

21 20

16 15

11 10

6 5

3 2

MSUB
101
3

fmt
3

MIPS IV

Format:

MSUB.S fd, fr, fs, ft
MSUB.D fd, fr, fs, ft

Purpose:

To perform a combined multiply-then-subtract of FP values.

Description:

fd ← (fs × ft) - fr

The value in FPR fs is multiplied by the value in FPR ft to produce an intermediate
product. The value in FPR fr is subtracted from the product. The subtraction result is
calculated to infinite precision, rounded according to the current rounding mode in
FCSR, and placed into FPR fd. The operands and result are values in format fmt.
The accuracy of the result depends which of two alternative arithmetic models is used
by the implementation for the computation. The numeric models are explained in
Arithmetic Instructions
on page B-21.

Operation:
vfr ← ValueFPR(fr, fmt)
vfs ← ValueFPR(fs, fmt)
vft ← ValueFPR(ft, fmt)
StoreFPR(fd, fmt, (vfs * vft) - vfr)

Exceptions:
Reserved Instruction
Coprocessor Unusable
Floating-Point
Inexact
Invalid Operation
Underflow

B-72

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

MTC1

Move Word to Floating-Point
31

26 25
COP1
010001
6

21 20

MT
00100
5

Format:
Purpose:

MTC1 rt, fs

Description:

fs ← rt

16 15

11 10

0
0
000 0000 0000
11

MIPS I

To copy a word from a GPR to an FPU (CP1) general register.

The low word in GPR rt is placed into the low word of floating-point (coprocessor 1)
general register fs. If coprocessor 1 general registers are 64-bits wide, bits 63..32 of
register fs become undefined. See Floating-Point Registers
on page B-6.

Restrictions:
For MIPS I, MIPS II, and MIPS III the value of FPR fs is undefined for the instruction
immediately following MTC1.

Operation: MIPS I - III
I : data ← GPR[rt]31..0
I + 1 :if SizeFGR() = 64 then

FGR[fs] ← undefined32 || data
else
FGR[fs] ← data
endif

/* 64-bit wide FGRs */
/* 32-bit wide FGRs */

Operation: MIPS IV
data ← GPR[rt]31..0
if SizeFGR() = 64 then
/* 64-bit wide FGRs */
FGR[fs] ← undefined32 || data
else
/* 32-bit wide FGRs */
FGR[fs] ← data
endif

Exceptions:
Coprocessor Unusable

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-73

MUL.fmt

Floating-Point Multiply

26 25

31
COP1
010001
6

21 20

16 15

11 10

6 5

fmt

Format:

MUL.S fd, fs, ft
MUL.D fd, fs, ft

Purpose:

To multiply FP values.

Description:

fd ← fs × ft

0
MUL
000010
6

MIPS I

The value in FPR fs is multiplied by the value in FPR ft. The result is calculated to
infinite precision, rounded according to the current rounding mode in FCSR, and
placed into FPR fd. The operands and result are values in format fmt.

Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) * ValueFPR(ft, fmt))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Invalid Operation
Underflow

B-74

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

NEG.fmt

Floating-Point Negate
31

26 25

COP1
010001
6

21 20
fmt
5

16 15

0
00000
5

11 10

6 5

0
NEG
000111
6

MIPS I

Format:

NEG.S fd, fs
NEG.D fd, fs

Purpose:

To negate an FP value.

Description:

fd ← - (fs)

The value in FPR fs is negated and placed into FPR fd. The value is negated by
changing the sign bit value. The operand and result are values in format fmt.
This operation is arithmetic; a NaN operand signals invalid operation.

Operation:
StoreFPR(fd, fmt, Negate(ValueFPR(fs, fmt)))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation
Invalid Operation

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-75

NMADD.fmt
31

26 25
COP1X
010011
6

Floating-Point Negative Multiply Add
21 20

11 10

16 15

6 5

3 2

NMADD
110
3

fmt
3

MIPS IV

Format:

NMADD.S fd, fr, fs, ft
NMADD.D fd, fr, fs, ft

Purpose:

To negate a combined multiply-then-add of FP values.

Description:

fd ← - ((fs × ft) + fr)

The value in FPR fs is multiplied by the value in FPR ft to produce an intermediate
product. The value in FPR fr is added to the product. The result sum is calculated to
infinite precision, rounded according to the current rounding mode in FCSR, negated
by changing the sign bit, and placed into FPR fd. The operands and result are values
in format fmt.
The accuracy of the result depends which of two alternative arithmetic models is used
by the implementation for the computation. The numeric models are explained in
Arithmetic Instructions
on page B-21.

Operation:
vfr ← ValueFPR(fr, fmt)
vfs ← ValueFPR(fs, fmt)
vft ← ValueFPR(ft, fmt)
StoreFPR(fd, fmt, -(vfr + vfs * vft))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Invalid Operation
Underflow

B-76

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

NMSUB.fmt

Floating-Point Negative Multiply Subtract
31

26 25
COP1X
010011
6

21 20

16 15

11 10

6 5

3 2

NMSUB
111
3

fmt
3

MIPS IV

Format:

NMSUB.S fd, fr, fs, ft
NMSUB.D fd, fr, fs, ft

Purpose:

To negate a combined multiply-then-subtract of FP values.

Description:

fd ← - ((fs × ft) - fr)

The value in FPR fs is multiplied by the value in FPR ft to produce an intermediate
product. The value in FPR fr is subtracted from the product. The result is calculated
to infinite precision, rounded according to the current rounding mode in FCSR,
negated by changing the sign bit, and placed into FPR fd. The operands and result are
values in format fmt.
The accuracy of the result depends which of two alternative arithmetic models is used
by the implementation for the computation. The numeric models are explained in
Arithmetic Instructions
on page B-21.

Operation:
vfr ← ValueFPR(fr, fmt)
vfs ← ValueFPR(fs, fmt)
vft ← ValueFPR(ft, fmt)
StoreFPR(fd, fmt, -((vfs * vft) - vfr))

Exceptions:
Reserved Instruction
Coprocessor Unusable
Floating-Point
Inexact
Invalid Operation
Underflow

FPU Instruction Set

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

B-77

PREFX
31

Prefetch Indexed

26 25

21 20

16 15

11 10

COP1X
010011

base

index

hint

0
00000

PREFX
001111

Format:
Purpose:

PREFX hint, index(base)

Description:

prefetch_memory[base+index]

MIPS IV

To prefetch locations from memory (GPR+GPR addressing).

PREFX adds the contents of GPR index to the contents of GPR base to form an effective
byte address. It advises that data at the effective address may be used in the near
future. The hint field supplies information about the way that the data is expected to
be used.
PREFX is an advisory instruction. It may change the performance of the program. For
all hint values, it neither changes architecturally-visible state nor alters the meaning of
the program. An implementation may do nothing when executing a PREFX
instruction.
If MIPS IV instructions are supported and enabled and Coprocessor 1 is enabled
(allowing access to CP1X), PREFX does not cause addressing-related exceptions. If it
raises an exception condition, the exception condition is ignored. If an addressingrelated exception condition is raised and ignored, no data will be prefetched. Even if
no data is prefetched in such a case, some action that is not architecturally-visible, such
as writeback of a dirty cache line, might take place.
PREFX will never generate a memory operation for a location with an uncached
memory access type (see Memory Access Types
on page A-12).
If PREFX results in a memory operation, the memory access type used for the
operation is determined by the memory access type of the effective address, just as it
would be if the memory operation had been caused by a load or store to the effective
address.
PREFX enables the processor to take some action, typically prefetching the data into
cache, to improve program performance. The action taken for a specific PREFX
instruction is both system and context dependent. Any action, including doing
nothing, is permitted that does not change architecturally-visible state or alter the
meaning of a program. It is expected that implementations will either do nothing or
take an action that will increase the performance of the program.
For a cached location, the expected, and useful, action is for the processor to prefetch a
block of data that includes the effective address. The size of the block, and the level of
the memory hierarchy it is fetched into are implementation specific.

B-78

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

PREFX

Prefetch Indexed

Values of Hint Field for Prefetch Instruction

Value

Name

Data use and desired prefetch action

load

Data is expected to be loaded (not modified).
Fetch data as if for a load.

store

Data is expected to be stored or modified.
Fetch data as if for a store.

2-3

Not yet defined.

load_streamed

store_streamed

Data is expected to be stored or modified but not
reused extensively; it will “stream” through cache.
Fetch data as if for a store and place it in the cache so
that it will not displace data prefetched as “retained”.

load_retained

store_retained

8-31

Not yet defined.

Restrictions:
The Region bits of the effective address must be supplied by the contents of base. If
EffectiveAddress63..62 ≠ base63..62, the result of the instruction is undefined.

Operation:
vAddr ← GPR[base] + GPR[index]
(pAddr, uncached) ← AddressTranslation(vAddr, DATA, LOAD)
Prefetch(uncached, pAddr, vAddr, DATA, hint)

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-79

PREFX

Prefetch Indexed

Exceptions:
Reserved Instruction
Coprocessor Unusable

B-80

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

RECIP.fmt

Reciprocal Approximation
31

26 25
COP1
010001
6

21 20
fmt
5

0
00000
5

16 15

11 10

0
RECIP
010101
6

MIPS IV

Format:

RECIP.S fd, fs
RECIP.D fd, fs

Purpose:

To approximate the reciprocal of an FP value (quickly).

Description:

fd ← 1.0 / fs

The reciprocal of the value in FPR fs is approximated and placed into FPR fd.
The operand and result are values in format fmt.
The numeric accuracy of this operation is implementation dependent; it does not meet
the accuracy specified by the IEEE 754 Floating-Point standard. The computed result
differs from the both the exact result and the IEEE-mandated representation of the
exact result by no more than one unit in the least-significant place (ulp).
It is implementation dependent whether the result is affected by the current rounding
mode in FCSR.

Operation:
StoreFPR(fd, fmt, 1.0 / valueFPR(fs, fmt))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Division-by-zero
Overflow

FPU Instruction Set

Unimplemented Operation
Invalid Operation
Underflow

MIPS IV Instruction Set. Rev 3.2

B-81

ROUND.L.fmt

Floating-Point Round to Long Fixed-Point

16 15

26 25

COP1
010001
6

21 20
fmt
5

0
00000
5

11 10

6 5

0
ROUND.L
001000
6

MIPS III

Format:

ROUND.L.S fd, fs
ROUND.L.D fd, fs

Purpose:

To convert an FP value to 64-bit fixed-point, rounding to nearest.

Description:

fd ← convert_and_round(fs)

The value in FPR fs in format fmt, is converted to a value in 64-bit long fixed-point
format rounding to nearest/even (rounding mode 0). The result is placed in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-263 to 263-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active.
•

•

Operation:
StoreFPR(fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Overflow

B-82

Unimplemented Operation
Invalid Operation

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Floating-Point Round to Word Fixed-Point
31

26 25

COP1
010001
6

21 20
fmt
5

ROUND.W.fmt

16 15

0
00000
5

11 10

6 5

0
ROUND.W
001100
6

MIPS II

Format:

ROUND.W.S fd, fs
ROUND.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point, rounding to nearest.

Description:

fd ← convert_and_round(fs)

The value in FPR fs in format fmt, is converted to a value in 32-bit word fixed-point
format rounding to nearest/even (rounding mode 0). The result is placed in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-231 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active.
•

•

Operation:
StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Invalid Operation

FPU Instruction Set

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

B-83

RSQRT.fmt
31

26 25
COP1
010001
6

Reciprocal Square Root Approximation
21 20

fmt
5

16 15

0
00000
5

11 10

0
RSQRT
010110
6

MIPS IV

Format:

RSQRT.S fd, fs
RSQRT.D fd, fs

Purpose:

To approximate the reciprocal of the square root of an FP value (quickly).

Description:

fd ← 1.0 / sqrt(fs)

The reciprocal of the positive square root of the value in FPR fs is approximated and
placed into FPR fd. The operand and result are values in format fmt.
The numeric accuracy of this operation is implementation dependent; it does not meet
the accuracy specified by the IEEE 754 Floating-Point standard. The computed result
differs from the both the exact result and the IEEE-mandated representation of the
exact result by no more than two units in the least-significant place (ulp).
It is implementation dependent whether the result is affected by the current rounding
mode in FCSR.

Operation:
StoreFPR(fd, fmt, 1.0 / SquareRoot(valueFPR(fs, fmt)))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Division-by-zero
Overflow

B-84

Unimplemented Operation
Invalid Operation
Underflow

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

SDC1

Store Doubleword from Floating-Point
31

26 25
SDC1
111101
6

21 20

16 15

base

offset

Format:
Purpose:

SDC1 ft, offset(base)

Description:

memory[base+offset] ← ft

MIPS II

To store a doubleword from an FPR to memory.

The 64-bit doubleword in FPR ft is stored in memory at the location specified by the
aligned effective address. The 16-bit signed offset is added to the contents of GPR base
to form the effective address.
If coprocessor 1 general registers are 32-bits wide (a native 32-bit processor or 32-bit
register emulation mode in a 64-bit processor), FPR ft is held in an even/odd register
pair. The low word is taken from the even register ft and the high word is from ft+1.

Operation:
vAddr ← sign_extend(offset) + GPR[base]
if vAddr2..0 ≠ 03 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation(vAddr, DATA, STORE)
if SizeFGR() = 64 then
/* 64-bit wide FGRs */
data ← FGR[ft]
elseif ft0 = 0 then
/* valid specifier, 32-bit wide FGRs */
data ← FGR[ft+1] || FGR[ft]
else
/* undefined for odd 32-bit FGRs */
UndefinedResult()
endif
StoreMemory(uncached, DOUBLEWORD, data, pAddr, vAddr, DATA)

Exceptions:
Coprocessor unusable
Reserved Instruction
TLB Refill, TLB Invalid
TLB Modified
Address Error

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-85

SDXC1
31

Store Doubleword Indexed from Floating-Point

26 25

21 20

16 15

11 10

COP1X
010011

base

index

SDXC1
001001

Format:
Purpose:

SDXC1 fs, index(base)

Description:

memory[base+index] ← fs

MIPS IV

To store a doubleword from an FPR to memory (GPR+GPR addressing).

The 64-bit doubleword in FPR fs is stored in memory at the location specified by the
aligned effective address. The contents of GPR index and GPR base are added to form
the effective address.
If coprocessor 1 general registers are 32-bits wide (a native 32-bit processor or 32-bit
register emulation mode in a 64-bit processor), FPR fs is held in an even/odd register
pair. The low word is taken from the even register fs and the high word is from fs+1.

Restrictions:
If fs does not specify an FPR that can contain a doubleword, the result is undefined; see
Floating-Point Registers
on page B-6.
The Region bits of the effective address must be supplied by the contents of base. If
EffectiveAddress63..62 ≠ base63..62, the result is undefined.
An Address Error exception occurs if EffectiveAddress2..0 ≠ 0 (not doublewordaligned).
MIPS IV: The low-order 3 bits of the offset field must be zero. If they are not, the result
of the instruction is undefined.

Operation:
vAddr ← GPR[base] + GPR[index]
if vAddr2..0 ≠ 03 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation(vAddr, DATA, STORE)
if SizeFGR() = 64 then
/* 64-bit wide FGRs */
data ← FGR[fs]
elseif fs0 = 0 then
/* valid specifier, 32-bit wide FGRs */
data ← FGR[fs+1] || FGR[fs]
else
/* undefined for odd 32-bit FGRs */
UndefinedResult()
endif
StoreMemory(uncached, DOUBLEWORD, data, pAddr, vAddr, DATA)

B-86

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

SDXC1

Store Doubleword Indexed from Floating-Point
Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Address Error
Reserved Instruction
Coprocessor Unusable

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-87

SQRT.fmt
31

Floating-Point Square Root

26 25

COP1
010001
6

21 20

16 15

0
00000
5

fmt
5

11 10

6 5

Format:

SQRT.S fd, fs
SQRT.D fd, fs

Purpose:

To compute the square root of an FP value.

Description:

fd ← SQRT(fs)

0
SQRT
000100
6

MIPS II

The square root of the value in FPR fs is calculated to infinite precision, rounded
according to the current rounding mode in FCSR, and placed into FPR fd. The operand
and result are values in format fmt.
If the value in FPR fs corresponds to –0, the result will be –0.

Restrictions:
If the value in FPR fs is less than 0, an Invalid Operation condition is raised.
The fields fs and fd must specify FPRs valid for operands of type fmt; see FloatingPoint Registers on page B-6. If they are not valid, the result is undefined.
The operand must be a value in format fmt; see section B 7 on page B-24. If it is not, the
result is undefined and the value of the operand FPR becomes undefined.

Operation:
StoreFPR(fd, fmt, SquareRoot(ValueFPR(fs, fmt)))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Unimplemented Operation
Invalid Operation
Inexact

B-88

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

SUB.fmt

Floating-Point Subtract
31

26 25

COP1
010001
6

21 20

16 15

11 10

6 5

fmt

Format:

SUB.S fd, fs, ft
SUB.D fd, fs, ft

Purpose:

To subtract FP values.

Description:

fd ← fs - ft

0
SUB
000001
6

MIPS I

The value in FPR ft is subtracted from the value in FPR fs. The result is calculated to
infinite precision, rounded according to the current rounding mode in FCSR, and
placed into FPR fd. The operands and result are values in format fmt.

Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) – ValueFPR(ft, fmt))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Invalid Operation
Underflow

FPU Instruction Set

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

B-89

SWC1
31

Store Word from Floating-Point

26 25
SWC1
111001
6

21 20

16 15

base

offset

Format:
Purpose:

SWC1 ft, offset(base)

Description:

memory[base+offset] ← ft

MIPS I

To store a word from an FPR to memory.

The low 32-bit word from FPR ft is stored in memory at the location specified by the
aligned effective address. The 16-bit signed offset is added to the contents of GPR base
to form the effective address.

Operation: 32-bit Processors
vAddr ← sign_extend(offset) + GPR[base]
if vAddr1..0 ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
data ← FGR[ft]
StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA)

Operation: 64-bit Processors
vAddr ← sign_extend(offset) + GPR[base]
if vAddr1..0 ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
bytesel ← vAddr2..0 xor (BigEndianCPU || 02)
/* the bytes of the word are moved into the correct byte lanes */
if SizeFGR() = 64 then
/* 64-bit wide FGRs */
32-8*bytesel
8*bytesel
data ← 0
|| FGR[ft]31..0 || 0
/* top or bottom wd of 64-bit data */
else
/* 32-bit wide FGRs */
data ← 032-8*bytesel || FGR[ft] || 08*bytesel
/* top or bottom wd of 64-bit data */
endif
StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA)

Exceptions:
Coprocessor unusable
Reserved Instruction
TLB Refill, TLB Invalid
TLB Modified
Address Error
B-90

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

SWXC1

Store Word Indexed from Floating-Point
31

26 25

21 20

16 15

11 10

COP1X
010011

base

index

SWXC1
001000

Format:
Purpose:

SWXC1 fs, index(base)

Description:

memory[base+index] ← fs

MIPS IV

To store a word from an FPR to memory (GPR+GPR addressing).

The low 32-bit word from FPR fs is stored in memory at the location specified by the
aligned effective address. The contents of GPR index and GPR base are added to form
the effective address.

Operation:
vAddr ← GPR[base] + GPR[index]
if vAddr1..0 ≠ 02 then SignalException(AddressError) endif
(pAddr, uncached) ← AddressTranslation(vAddr, DATA, STORE)
pAddr ← pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
bytesel ← vAddr2..0 xor (BigEndianCPU || 02)
/* the bytes of the word are moved into the correct byte lanes */
if SizeFGR() = 64 then
/* 64-bit wide FGRs */
data ← 032-8*bytesel || FGR[fs]31..0 || 08*bytesel /* top or bottom wd of 64-bit data */
else
/* 32-bit wide FGRs */
data ← 032-8*bytesel || FGR[fs] || 08*bytesel
/* top or bottom wd of 64-bit data */
endif
StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA)

Exceptions:
TLB Refill, TLB Invalid
TLB Modified
Address Error
Reserved Instruction
Coprocessor Unusable

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-91

TRUNC.L.fmt

Floating-Point Truncate to Long Fixed-Point

16 15

26 25

COP1
010001
6

21 20
fmt
5

0
00000
5

11 10

6 5

0
TRUNC.L
0 0 1 0 01
6

MIPS III

Format:

TRUNC.L.S fd, fs
TRUNC.L.D fd, fs

Purpose:

To convert an FP value to 64-bit fixed-point, rounding toward zero.

Description:

fd ← convert_and_round(fs)

The value in FPR fs in format fmt, is converted to a value in 64-bit long fixed-point
format rounding toward zero (rounding mode 1). The result is placed in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-263 to 263-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active.
•

•

Operation:
StoreFPR(fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Invalid Operation

B-92

Unimplemented Operation
Overflow

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Floating-Point Truncate to Word Fixed-Point

TRUNC.W.fmt

11 10

26 25

COP1
010001
6

21 20
fmt
5

16 15

0
00000
5

6 5

0
TRUNC.W
001101
6

MIPS II

Format:

TRUNC.W.S fd, fs
TRUNC.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point, rounding toward zero.

Description:

fd ← convert_and_round(fs)

The value in FPR fs in format fmt, is converted to a value in 32-bit word fixed-point
format using rounding toward zero (rounding mode 1)). The result is placed in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range
-231 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation
condition exists. The result depends on the FP exception model currently active.
•

•

Operation:
StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W))

Exceptions:
Coprocessor Unusable
Reserved Instruction
Floating-Point
Inexact
Overflow

FPU Instruction Set

Invalid Operation
Unimplemented Operation

MIPS IV Instruction Set. Rev 3.2

B-93

B.11 FPU Instruction Formats
An FPU instruction is a single 32-bit aligned word. The distinct FP instruction
layouts are shown in Figure B-16. Variable information is in lower-case labels,
such as “offset”. Upper-case labels and any numbers indicate constant data. A
table follows all the layouts that explains the fields used in them. Note that the
same field may have different names in different instruction layout pictures. The
field name is mnemonic to the function of that field in the instruction layout. The
opcode tables and the instruction decode discussion use the canonical field names:
opcode, fmt, nd, tf, and function. The other fields are not used for instruction
decode.
Figure B-16

FPU Instruction Formats

Immediate: load/store using register + offset addressing.
31

26 25

21 20

16 15

opcode

base

offset

26 25

21 20

16 15

11 10

COP1

fmt

function

26 25

21 20

16 15

11 10

COP1

sub

Condition code, Immediate: conditional branches on FPU cc using PC + offset.
31

21 20 18 17 16 15

26 25

COP1

nd tf

offset

1 1

26 25

21 20

16 15

11 10

8 7 6 5

COP1

fmt

function

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-95

Condition Code, Register FP: FPU register move-conditional on FP cc.
31

26 25

21 20 18 17 16 15

11 10

COP1

fmt

0 tf

MOVCF

1 1

26 25

21 20

16 15

11 10

3 2

COP1X

function
op4
fmt3

26 25

21 20

16 15

11 10

COP1X

base

index

function

26 25

21 20

16 15

11 10

COP1X

base

index

hint

PREFX

Condition Code, Register Integer: CPU register move-conditional on FP cc.
31

B-96

26 25

21 20 18 17 16 15

11 10

SPECIAL

0 tf

MOVCI

1 1

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Branch Conditional instruction subcode (op=COP1)

base

CPU register: base address for address calculations

COP1

Coprocessor 1 primary opcode value in op field.

COP1X

Coprocessor 1 eXtended primary opcode value in op field.

condition code specifier. For architecture levels prior to MIPS IV it must be
zero.

FPU register: destination (arithmetic, loads, move-to) or source (stores,
move-from)

fmt

destination and/or operand type (“format”) specifier

FPU register: source

FPU register: source (for stores, arithmetic) or destination (for loads)

function

function field specifying a function within a particular op operation code.

function:
op4 +
fmt3

op4 is a 3-bit function field specifying which 4-register arithmetic operation
for COP1X, fmt3 is a 3-bit field specifying the format of the operands and
destination. The combinations are shown as several distinct instructions in
the opcode tables.

hint

hint field made available to cache controller for prefetch operation

index

CPU register, holds index address component for address calculations

MOVC

Value in function field for conditional move. There is one value for the
instruction with op=COP1, another for the instruction with op=SPECIAL.

nullify delay. If set, branch is Likely and delay slot instruction is not
executed. This must be zero for MIPS I.

offset

signed offset field used in address calculations

primary operation code (COP1, COP1X, LWC1, SWC1, LDC1, SDC1,
SPECIAL)

PREFX

Value in function field for prefetch instruction for op=COP1X

CPU register: destination

CPU register: source

CPU register: source / destination

SPECIAL SPECIAL primary opcode value in op field.
sub

Operation subcode field for COP1 register immediate mode instructions.

true/false. The condition from FP compare is tested for equality with tf bit.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-97

B.12 FPU (CP1) Instruction Opcode Bit Encoding
This section describes the encoding of the Floating-Point Unit (FPU) instructions
for the four levels of the MIPS architecture, MIPS I through MIPS IV. Each architecture
level includes the instructions in the previous level;† MIPS IV includes all instructions in
MIPS I, MIPS II, and MIPS III. This section presents eight different views of the instruction
encoding.
•

Separate encoding tables for each architecture level.

•

A MIPS IV encoding table showing the architecture level at which each
opcode was originally defined and subsequently modified (if modified).

•

Separate encoding tables for each architecture revision showing the
changes made during that revision.

B 12.1 Instruction Decode
Instruction field names are printed in bold in this section.
The primary opcode field is decoded first. The opcode values LWC1, SWC1,
LDC1, and SDC1 fully specify FPU load and store instructions. The opcode values COP1,
COP1X, and SPECIAL specify instruction classes. Instructions within a class are further
specified by values in other fields.
B 12.1.1 COP1 Instruction Class
The opcode =COP1 instruction class encodes most of the FPU instructions. The
class is further decoded by examining the fmt field. The fmt values fully specify the
CPU ↔ FPU register move instructions and specify the S, D, W, L, and BC instruction
classes.
The opcode =COP1 + fmt =BC instruction class encodes the conditional branch
instructions. The class is further decoded, and the instructions fully specified, by
examining the nd and tf fields.
The opcode =COP1 + fmt =(S, D, W, or L) instruction classes encode instructions
that operate on formatted (typed) operands. Each of these instruction classes is further
decoded by examining the function field. With one exception the function values fully
specify instructions. The exception is the MOVCF instruction class.
The opcode =COP1 + fmt =(S or D) + function =MOVCF instruction class encodes
the MOVT.fmt and MOVF.fmt conditional move instructions (to move FP values based on
FP condition codes). The class is further decoded, and the instructions fully specified, by
examining the tf field.

† An exception to this rule is that the reserved, but never implemented, Coprocessor 3
instructions were removed or changed to another use starting in MIPS III.
B-98

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

B 12.1.2 COP1X Instruction Class
The opcode =COP1X instruction class encodes the indexed load/store
instructions, the indexed prefetch, and the multiply accumulate instructions. The class is
further decoded, and the instructions fully specified, by examining the function field.
B 12.1.3 SPECIAL Instruction Class
The opcode =SPECIAL instruction class is further decoded by examining the
function field. The only function value that applies to FPU instruction encoding is the
MOVCI instruction class. The remainder of the function values encode CPU instructions.
The opcode =SPECIAL + function =MOVCI instruction class encodes the MOVT
and MOVF conditional move instructions (to move CPU registers based on FP condition
codes). The class is further decoded, and the instructions fully specified, by examining the
tf field.

B 12.2 Instruction Subsets of MIPS III and MIPS IV Processors.
MIPS III processors, such as the R4000, R4200, R4300, R4400, and R4600, have a
processor mode in which only the MIPS II instructions are valid. The MIPS II encoding
table describes the MIPS II-only mode.
MIPS IV processors, such as the R8000 and R10000, have processor modes in which
only the MIPS II or MIPS III instructions are valid. The MIPS II encoding table describes
the MIPS II-only mode. The MIPS III encoding table describes the MIPS III-only mode.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-99

Table B-23

FPU (CP1) Instruction Encoding - MIPS I Architecture

Instructions encoded by the opcode field.
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

bits 28..26
0
000

000
001
010
011
100
101
110
111

1
001

2
010

3
011

4
100

5
101

6
110

7
111

COP1 δ
χ

LWC1
SWC1

Instructions encoded by the fmt field when opcode=COP1.
31

26 25

opcode
= COP1
fmt
bits
25..24
0
1
2
3

00
01
10
11

bits 23..21
0
000
MFC1
BC δ
S δ
*

1
001
*
*
D δ
*

fmt

2
010
CFC1
*
*
*

3
011
*
*
*
*

4
100
MTC1
*
W δ
*

5
101
*
*
*
*

6
110
CTC1
*
*
*

7
111
*
*
*
*

Instructions encoded by the tf field when opcode=COP1 and fmt=BC.
31

26 25

opcode
= COP1
t
f

B-100

bit 16
0
BC1F

fmt
= BC

t
f

1
BC1T

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Table B-23 (cont.)

FPU (CP1) Instruction Encoding - MIPS I Architecture

Instructions encoded by the function field when opcode=COP1 and fmt = S, D, or W
31

encoding when
fmt = S
functi
on
bits
5..3
0
1
2
3
4
5
6

000
001
010
011
100
101
110

bits 2..0
0
000
ADD
*
*
*
*
*
C.F α

111

C.SF α

encoding when
fmt = D
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

bits 2..0
0
000
ADD
*
*
*
CVT.S
*
C.F α
C.SF α

FPU Instruction Set

26 25

opcode
= COP1

fmt
=S

function

1
001
SUB
*
*
*
CVT.D
*

2
010
MUL
*
*
*
*
*

3
011
DIV
*
*
*
*
*

4
100
*
*
*
*
CVT.W
*

5
101
ABS
*
*
*
*
*

6
110
MOV
*
*
*
*
*

7
111
NEG
*
*
*
*
*

C.UN α
C.NGLE α

C.EQ α
C.SEQ α

C.UEQ α
C.NGL α

C.OLT α
C.LT α

C.ULT α
C.NGE α

C.OLE α
C.LE α

C.ULE α
C.NGT α

26 25

opcode
= COP1

1
001
SUB
*
*
*
*
*
C.UN α
C.NGLE α

2
010
MUL
*
*
*
*
*
C.EQ α
C.SEQ α

fmt
=D

3
011
DIV
*
*
*
*
*
C.UEQ α
C.NGL α

function

4
100
*
*
*
*
CVT.W
*
C.OLT α
C.LT α

MIPS IV Instruction Set. Rev 3.2

5
101
ABS
*
*
*
*
*
C.ULT α
C.NGE α

6
110
MOV
*
*
*
*
*
C.OLE α
C.LE α

7
111
NEG
*
*
*
*
*
C.ULE α
C.NGT α

B-101

encoding when
fmt = W
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

B-102

bits 2..0
0
000
*
*
*
*
CVT.S
*
*
*

26 25

opcode
= COP1

1
001
*
*
*
*
CVT.D
*
*
*

2
010
*
*
*
*
*
*
*
*

fmt
=W

3
011
*
*
*
*
*
*
*
*

function

4
100
*
*
*
*
*
*
*
*

MIPS IV Instruction Set. Rev 3.2

5
101
*
*
*
*
*
*
*
*

6
110
*
*
*
*
*
*
*
*

7
111
*
*
*
*
*
*
*
*

FPU Instruction Set

Table B-24

FPU (CP1) Instruction Encoding - MIPS II Architecture

Instructions encoded by the opcode field.
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

bits 28..26
0
000

000
001
010
011
100
101
110
111

1
001

2
010

3
011

4
100

5
101

6
110

7
111

COP1 δ
χ

LWC1
SWC1

LDC1
SDC1

Instructions encoded by the fmt field when opcode=COP1.
31

26 25

opcode
= COP1
fmt
bits
25..24
0
1
2
3

00
01
10
11

bits 23..21
0
000
MFC1
BC δ
S δ
*

1
001
*
*
D δ
*

fmt

2
010
CFC1
*
*
*

3
011
*
*
*
*

4
100
MTC1
*
W δ
*

5
101
*
*
*
*

6
110
CTC1
*
*
*

7
111
*
*
*
*

Instructions encoded by the nd and tf fields when opcode=COP1 and fmt=BC.
31

26 25

opcode
= COP1
t
f

bit 16

0
bit 17 1

0
BC1F
BC1FL

n
d

FPU Instruction Set

fmt
= BC

17 16

n t
d f

1
BC1T
BC1TL

MIPS IV Instruction Set. Rev 3.2

B-103

Table B-24 (cont.)

FPU (CP1) Instruction Encoding - MIPS II Architecture

Instructions encoded by the function field when opcode=COP1 and fmt = S, D, or W
31

encoding when
fmt = S
functi
on
bits
5..3
0
1
2
3
4
5
6

000
001
010
011
100
101
110

bits 2..0
0
000
ADD
*
*
*
*
*
C.F α

111

C.SF α

encoding when
fmt = D
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

B-104

bits 2..0
0
000
ADD
*
*
*
CVT.S
*
C.F α
C.SF α

26 25

opcode
= COP1

function

1
001
SUB
*
*
*
CVT.D
*

2
010
MUL
*
*
*
*
*

3
011
DIV
*
*
*
*
*

C.UN α
C.NGLE α

C.EQ α
C.SEQ α

C.UEQ α
C.NGL α

26 25

opcode
= COP1

1
001
SUB
*
*
*
*
*
C.UN α
C.NGLE α

2
010
MUL
*
*
*
*
*
C.EQ α
C.SEQ α

fmt
=S

4
5
100
101
SQRT
ABS
ROUND.W TRUNC.W
*
*
*
*
CVT.W
*
*
*

6
110
MOV
CEIL.W
*
*
*
*

7
111
NEG
FLOOR.W
*
*
*
*

C.OLT α
C.LT α

C.OLE α
C.LE α

C.ULE α
C.NGT α

C.ULT α
C.NGE α

fmt
=D

3
011
DIV
*
*
*
*
*
C.UEQ α
C.NGL α

function

4
5
100
101
SQRT
ABS
ROUND.W TRUNC.W
*
*
*
*
CVT.W
*
*
*
C.OLT α
C.ULT α
C.LT α
C.NGE α

MIPS IV Instruction Set. Rev 3.2

6
110
MOV
CEIL.W
*
*
*
*
C.OLE α
C.LE α

7
111
NEG
FLOOR.W
*
*
*
*
C.ULE α
C.NGT α

FPU Instruction Set

encoding when
fmt = W
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

bits 2..0
0
000
*
*
*
*
CVT.S
*
*
*

FPU Instruction Set

26 25

opcode
= COP1

1
001
*
*
*
*
CVT.D
*
*
*

2
010
*
*
*
*
*
*
*
*

fmt
=W

3
011
*
*
*
*
*
*
*
*

function

4
100
*
*
*
*
*
*
*
*

MIPS IV Instruction Set. Rev 3.2

5
101
*
*
*
*
*
*
*
*

6
110
*
*
*
*
*
*
*
*

7
111
*
*
*
*
*
*
*
*

B-105

Table B-25

FPU (CP1) Instruction Encoding - MIPS III Architecture

Instructions encoded by the opcode field.
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

bits 28..26
0
000

000
001
010
011
100
101
110
111

1
001

2
010

3
011

4
100

5
101

6
110

7
111

COP1 δ
χ

LWC1
SWC1

LDC1
SDC1

Instructions encoded by the fmt field when opcode=COP1.
31

26 25

opcode
= COP1
fmt
bits
25..24
0
1
2
3

00
01
10
11

bits 23..21
0
000
MFC1
BC δ
S δ
*

1
001
DMFC1
*
D δ
*

fmt

2
010
CFC1
*
*
*

3
011
*
*
*
*

4
100
MTC1
*
W δ
*

5
101
DMTC1
*
L δ
*

6
110
CTC1
*
*
*

7
111
*
*
*
*

Instructions encoded by the nd and tf fields when opcode=COP1 and fmt=BC.
31

26 25

opcode
= COP1
t
f

bit 16

0
bit 17 1

0
BC1F
BC1FL

n
d

B-106

fmt
= BC

17 16

n t
d f

1
BC1T
BC1TL

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Table B-25 (cont.)

FPU (CP1) Instruction Encoding - MIPS III Architecture

Instructions encoded by the function field when opcode=COP1 and fmt = S, D, W, or L
31

encoding when
fmt = S
functi
on
bits
5..3
0
1
2
3
4
5
6

000
001
010
011
100
101
110

bits 2..0
0
000
ADD
ROUND.L
*
*
*
*
C.F α

111

C.SF α

encoding when
fmt = D
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

26 25

opcode
= COP1

function

1
001
SUB
TRUNC.L
*
*
CVT.D
*

2
010
MUL
CEIL.L
*
*
*
*

3
4
5
011
100
101
DIV
SQRT
ABS
FLOOR.L ROUND.W TRUNC.W
*
*
*
*
*
*
*
CVT.W
CVT.L
*
*
*

6
110
MOV
CEIL.W
*
*
*
*

7
111
NEG
FLOOR.W

C.UN α
C.NGLE α

C.EQ α
C.SEQ α

C.UEQ α
C.NGL α

C.OLE α
C.LE α

C.ULE α
C.NGT α

26 25

opcode
= COP1

bits 2..0
0
1
000
001
ADD
SUB
ROUND.L TRUNC.L
*
*
*
*
CVT.S
*
*
*
C.F α
C.UN α
C.SF α
C.NGLE α

FPU Instruction Set

fmt
=S

2
010
MUL
CEIL.L
*
*
*
*
C.EQ α
C.SEQ α

C.OLT α
C.LT α

C.ULT α
C.NGE α

*
*
*

fmt
=D

3
4
5
011
100
101
DIV
SQRT
ABS
FLOOR.L ROUND.W TRUNC.W
*
*
*
*
*
*
*
CVT.W
CVT.L
*
*
*
C.UEQ α
C.OLT α
C.ULT α
C.NGL α
C.LT α
C.NGE α

MIPS IV Instruction Set. Rev 3.2

function

6
110
MOV
CEIL.W
*
*
*
*
C.OLE α
C.LE α

7
111
NEG
FLOOR.W
*
*
*
C.ULE α
C.NGT α

B-107

encoding when
fmt = W or L
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

B-108

bits 2..0
0
000
*
*
*
*
CVT.S
*
*
*

1
001
*
*
*
*
CVT.D
*
*
*

26 25

opcode
= COP1

fmt
= W, L

2
010
*
*
*
*
*
*
*
*

3
011
*
*
*
*
*
*
*
*

function

4
100
*
*
*
*
*
*
*
*

MIPS IV Instruction Set. Rev 3.2

5
101
*
*
*
*
*
*
*
*

6
110
*
*
*
*
*
*
*
*

7
111
*
*
*
*
*
*
*
*

FPU Instruction Set

Table B-26

FPU (CP1) Instruction Encoding - MIPS IV Architecture

Instructions encoded by the opcode field.
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

bits 28..26
0
000
000 SPECIAL δ, β
001
010
011
100
101
110
111

1
001

2
010

3
011

COP1 δ

4
100

COP1X δ,λ

5
101

6
110

7
111

LWC1
SWC1

LDC1
SDC1

Instructions encoded by the fmt field when opcode=COP1.
31

26 25

opcode
= COP1
fmt
bits
25..24
0
1
2
3

00
01
10
11

bits 23..21
0
000
MFC1
BC δ
S δ
*

1
001
DMFC1
*
D δ
*

fmt

2
010
CFC1
*
*
*

3
011
*
*
*
*

4
100
MTC1
*
W δ
*

5
101
DMTC1
*
L δ
*

6
110
CTC1
*
*
*

7
111
*
*
*
*

Instructions encoded by the nd and tf fields when opcode=COP1 and fmt=BC.
31

26 25

opcode
= COP1
t
f

bit 16

0
bit 17 1

0
BC1F
BC1FL

n
d

FPU Instruction Set

fmt
= BC

17 16

n t
d f

1
BC1T
BC1TL

MIPS IV Instruction Set. Rev 3.2

B-109

Table B-26 (cont.)

FPU (CP1) Instruction Encoding - MIPS IV Architecture

Instructions encoded by the function field when opcode=COP1 and fmt = S, D, W, or L
31

encoding when
fmt = S
functi
on
bits
5..3
0
1
2
3
4
5
6

000
001
010
011
100
101
110

bits 2..0
0
000
ADD
ROUND.L
*
*
*
*
C.F α

111

C.SF α

encoding when
fmt = D
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

B-110

26 25

opcode
= COP1

fmt
=S

function

1
001
SUB
TRUNC.L
MOVCF δ
*
CVT.D
*

2
010
MUL
CEIL.L
MOVZ
*
*
*

3
4
5
011
100
101
DIV
SQRT
ABS
FLOOR.L ROUND.W TRUNC.W
MOVN
*
RECIP
*
*
*
*
CVT.W
CVT.L
*
*
*

6
110
MOV
CEIL.W
RSQRT
*
*
*

7
111
NEG
FLOOR.W

C.UN α
C.NGLE α

C.EQ α
C.SEQ α

C.UEQ α
C.NGL α

C.OLE α
C.LE α

C.ULE α
C.NGT α

26 25

opcode
= COP1

bits 2..0
0
1
000
001
ADD
SUB
ROUND.L TRUNC.L
*
MOVCF δ
*
*
CVT.S
*
*
*
C.F α
C.UN α
C.SF α
C.NGLE α

2
010
MUL
CEIL.L
MOVZ
*
*
*
C.EQ α
C.SEQ α

C.OLT α
C.LT α

C.ULT α
C.NGE α

*
*
*

fmt
=D

3
4
5
011
100
101
DIV
SQRT
ABS
FLOOR.L ROUND.W TRUNC.W
MOVN
*
RECIP
*
*
*
*
CVT.W
CVT.L
*
*
*
C.UEQ α
C.OLT α
C.ULT α
C.NGL α
C.LT α
C.NGE α

MIPS IV Instruction Set. Rev 3.2

function

6
110
MOV
CEIL.W
RSQRT
*
*
*
C.OLE α
C.LE α

7
111
NEG
FLOOR.W
*
*
*
C.ULE α
C.NGT α

FPU Instruction Set

encoding when
fmt = W or L
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

bits 2..0
0
000
*
*
*
*
CVT.S
*
*
*

Table B-26 (cont.)

26 25

opcode
= COP1

fmt
= W, L

2
010
*
*
*
*
*
*
*
*

3
011
*
*
*
*
*
*
*
*

1
001
*
*
*
*
CVT.D
*
*
*

function

4
100
*
*
*
*
*
*
*
*

5
101
*
*
*
*
*
*
*
*

6
110
*
*
*
*
*
*
*
*

7
111
*
*
*
*
*
*
*
*

FPU (CP1) Instruction Encoding - MIPS IV Architecture

Instructions encoded by the function field when opcode=COP1X.
31

opcode
= COP1X
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

bits 2..0
0
1
000
001
LWXC1
LDXC1
SWXC1
SDXC1
*
*
*
*
MADD.S MADD.D
MSUB.S
MSUB.D
NMADD.S NMADD.D
NMSUB.S NMSUB.D

function

2
010
*
*
*
*
*
*
*
*

3
011
*
*
*
*
*
*
*
*

4
100
*
*
*
*
*
*
*
*

5
101
*
*
*
*
*
*
*
*

6
110
*
*
*
*
*
*
*
*

7
111
*
PREFX
*
*
*
*
*
*

Instructions encoded by the tf field when opcode=COP1, fmt = S or D, and
function=MOVCF.
31

26 25

opcode
= COP1
t
f

bit 16

0
1
MOVF (fmt) MOVT (fmt)

FPU Instruction Set

fmt
= S, D

t
f

function
= MOVCF

These are the MOVF.fmt and MOVT.fmt instructions. They
should not be confused with MOVF and MOVT.

MIPS IV Instruction Set. Rev 3.2

B-111

Instruction class encoded by the function field when opcode=SPECIAL.
31

opcode
= SPECIAL
functi
on
bits
5..3
0
7

bits 2..0
0
000

000
...
111

1
001
MOVCI δ

2
010

function

3
011

4
100

5
101

6
110

7
111

Instructions encoded by the tf field when opcode = SPECIAL and function=MOVCI.
31

t
f

bit 16

B-112

0
MOVF

opcode
= SPECIAL

t
f

function
= MOVCI

1
MOVT

These are the MOVF and MOVT instructions. They should
not be confused with MOVF.fmt and MOVT.fmt.

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Table B-27

Architecture Level In Which FPU Instructions are Defined or Extended.

Instructions encoded by the opcode field.
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

Architecture level is shown by a subscript 1, 2, III, or 4.
bits 28..26
0
000
SPECIAL β 4

1
001

2
010

3
011

COP1 1,2,3,4

4
100

COP1X 4

5
101

6
110

7
111

LWC1 1
SWC1 1

LDC1 2
SDC1 2

Instructions encoded by the fmt field when opcode=COP1.
31

26 25

opcode
= COP1
fmt
bits
25..24
0
1
2
3

00
01
10
11

bits 23..21
0
000
MFC1 1
BC 1,2,4
S 1,2,3,4
*1

fmt

Architecture level is shown by a subscript 1, 2, 3, or 4.
1
001
DMFC1 3
*1
D 1,2,3,4
*1

2
010
CFC1 1
*1
*1
*1

3
011
*1
*1
*1
*1

4
100
MTC1 1
*1
W 1,2,3,4
*1

5
101
DMTC1 3
*1
L 3,4
*1

6
110
CTC1 1
*1
*1
*1

7
111
*1
*1
*1
*1

Instructions encoded by the nd and tf fields when opcode=COP1 and fmt=BC.
31

26 25

opcode
= COP1
t
f
n
d

0
bit 17 1

fmt
= BC

17 16

n t
d f

Architecture level is shown by a subscript 1, 2, 3, or 4.
bit 16
0
BC1F 1, 4
BC1FL 2, 4

FPU Instruction Set

1
BC1T 1, 4
BC1TL 2, 4

MIPS IV Instruction Set. Rev 3.2

B-113

Table B-27 (cont.) Architecture Level (I-IV) In Which FPU Instructions are Defined or Extended
Instructions encoded by the function field when opcode=COP1 and fmt = S, D, W, or L
31

encoding when
fmt = S

26 25

opcode
= COP1

fmt
=S

function

Architecture level is shown by a subscript 1, 2, 3, or 4.

functi
on
bits
5..3
0
1

bits 2..0
0
1
000
001
000
ADD 1
SUB 1
001 ROUND.L 3 TRUNC.L 3

2
3
4
5
6
7

010
011
100
101
110
111

2
010
MUL 1
CEIL.L 3

3
4
5
6
011
100
101
110
DIV 1
SQRT 2
ABS 1
MOV 1
FLOOR.L 3 ROUND.W 2 TRUNC.W 2 CEIL.W 2

7
111
NEG 1
FLOOR.W

MOVN 4
*1
*1
*1
C.UEQ 1, 4
C.NGL 1, 4

*1
*1
*1
*1
C.ULE 1, 4
C.NGT 1, 4

*1
*1
*1
*1
C.F 1, 4
C.SF 1, 4

encoding when
fmt = D
functi
on
bits
5..3

MOVCF 4 MOVZ 4
*1
*1
CVT.D 1, 3
*1
*1
*1
C.UN 1, 4
C.EQ 1, 4
C.NGLE 1, 4 C.SEQ 1, 4
31

26 25

opcode
= COP1

*1
*1
CVT.W 1
*1
C.OLT 1, 4
C.LT 1, 4

RECIP 4
*1
CVT.L 3
*1
C.ULT 1, 4
C.NGE 1, 4

RSQRT 4
*1
*1
*1
C.OLE 1, 4
C.LE 1, 4

fmt
=D

function

Architecture level is shown by a subscript 1, 2, 3, or 4.

0
1

bits 2..0
0
1
000
001
000
ADD 1
SUB 1
001 ROUND.L 3 TRUNC.L 3

2
3
4
5
6
7

010
011
100
101
110
111

2
010
MUL 1
CEIL.L 3

3
4
5
6
011
100
101
110
DIV 1
SQRT 2
ABS 1
MOV 1
FLOOR.L 3 ROUND.W 2 TRUNC.W 2 CEIL.W 2

7
111
NEG 1
FLOOR.W

MOVN 4
*1
*1
*1
C.UEQ 1, 4
C.NGL 1, 4

*1
*1
*1
*1
C.ULE 1, 4
C.NGT 1, 4

B-114

*1
MOVCF 4 MOVZ 4
*1
*1
*1
CVT.S 1, 3
*1
*1
*1
*1
*1
C.F 1, 4
C.UN 1, 4
C.EQ 1, 4
C.SF 1, 4 C.NGLE 1, 4 C.SEQ 1, 4

*1
*1
CVT.W 1
*1
C.OLT 1, 4
C.LT 1, 4

MIPS IV Instruction Set. Rev 3.2

RECIP 4
*1
CVT.L 3
*1
C.ULT 1, 4
C.NGE 1, 4

RSQRT 4
*1
*1
*1
C.OLE 1, 4
C.LE 1, 4

FPU Instruction Set

encoding when
fmt = W or L
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

26 25

opcode
= COP1

fmt
= W, L

function

Architecture level is shown by a subscript 1, 2, 3, or 4.
bits 2..0
0
000
*1
*1
*1
*1
CVT.S 1, 3
*1
*1
*1

1
001
*1
*1
*1
*1
CVT.D 1, 3
*1
*1
*1

2
010
*1
*1
*1
*1
*1
*1
*1
*1

3
011
*1
*1
*1
*1
*1
*1
*1
*1

4
100
*1
*1
*1
*1
*1
*1
*1
*1

5
101
*1
*1
*1
*1
*1
*1
*1
*1

6
110
*1
*1
*1
*1
*1
*1
*1
*1

7
111
*1
*1
*1
*1
*1
*1
*1
*1

Table B-27 (cont.) Architecture Level (I-IV) In Which FPU Instructions are Defined or Extended
Instructions encoded by the function field when opcode=COP1X.
31

opcode
= COP1X
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

function

Architecture level is shown by a subscript 1, 2, 3, or 4.
bits 2..0
0
1
000
001
LWXC1 4
LDXC1 4
SWXC1 4
SDXC1 4
*4
*4
*4
*4
MADD.S 4 MADD.D 4
MSUB.S 4
MSUB.D 4
NMADD.S 4 NMADD.D 4
NMSUB.S 4 NMSUB.D 4

2
010
*4
*4
*4
*4
*4
*4
*4
*4

3
011
*4
*4
*4
*4
*4
*4
*4
*4

4
100
*4
*4
*4
*4
*4
*4
*4
*4

5
101
*4
*4
*4
*4
*4
*4
*4
*4

6
110
*4
*4
*4
*4
*4
*4
*4
*4

7
111
*4
PREFX 4
*4
*4
*4
*4
*4
*4

Instructions encoded by the tf field when opcode=COP1, fmt = S or D, and
function=MOVCF.
31

26 25

opcode
= COP1
t
f

bit 16

0
1
MOVF (fmt) 4 MOVT (fmt) 4

FPU Instruction Set

fmt
= S, D

t
f

function
= MOVCF

These are the MOVF.fmt and MOVT.fmt instructions.
They should not be confused with MOVF and MOVT.

MIPS IV Instruction Set. Rev 3.2

B-115

Instruction class encoded by the function field when opcode=SPECIAL.
31

opcode
= SPECIAL
functi
on
bits
5..3
0
7

function

Architecture level is shown by a subscript 1, 2, 3, or 4.
bits 2..0
0
000

000
...
111

1
001
MOVCI 4

2
010

3
011

4
100

5
101

6
110

7
111

Instructions encoded by the tf field when opcode = SPECIAL and function=MOVCI.
31

t
f

bit 16

B-116

0
MOVF 4

opcode
= SPECIAL

t
f

function
= MOVCI

1
MOVT 4

These are the MOVF and MOVT instructions. They should
not be confused with MOVF.fmt and MOVT.fmt.

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Table B-28

FPU Instruction Encoding Changes - MIPS II Architecture Revision.

An instruction encoding is shown if the instruction is added or extended in this
architecture revision. An instruction class, like COP1, is shown if the instruction class is
added in this architecture revision.
Instructions encoded by the opcode field.
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

bits 28..26
0
000

1
001

2
010

3
011

4
100

000
001
010
011
100
101
110
111

5
101

6
110

7
111

LDC1
SDC1

Instructions encoded by the fmt field when opcode=COP1.
31

26 25

opcode
= COP1
fmt
bits
25..24
0
1
2
3

bits 23..21
0
000

1
001

fmt

2
010

3
011

4
100

5
101

6
110

7
111

00
01
10
11

Instructions encoded by the nd and tf fields when opcode=COP1 and fmt=BC.
31

26 25

opcode
= COP1
t
f
n
d

0
bit 17 1

fmt
= BC

17 16

n t
d f

bit 16
0

BC1FL

BC1TL

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-117

Table B-28 (cont.)

FPU Instruction Encoding Changes - MIPS II Revision.

Instructions encoded by the function field when opcode=COP1 and fmt = S, D, or W
31

encoding when
fmt = S
functi
on
bits
5..3
0
1
2
3
4
5
6
7

bits 2..0
0
000

1
001

2
010

functi
on
bits
5..3
000
001
010
011
100
101
110
111

B-118

bits 2..0
0
000

function

3
011

26 25

opcode
= COP1

1
001

2
010

fmt
=S

000
001
010
011
100
101
110
111

encoding when
fmt = D

0
1
2
3
4
5
6
7

26 25

opcode
= COP1

4
5
100
101
SQRT
ROUND.W TRUNC.W

6
110

7
111

CEIL.W

FLOOR.W

fmt
=D

3
011

function

4
5
100
101
SQRT
ROUND.W TRUNC.W

MIPS IV Instruction Set. Rev 3.2

6
110

7
111

CEIL.W

FLOOR.W

FPU Instruction Set

encoding when
fmt = W
functi
on
bits
5..3
0
1
2
3
4
5
6
7

bits 2..0
0
000

26 25

opcode
= COP1

1
001

2
010

fmt
=W

3
011

function

4
100

5
101

6
110

7
111

000
001
010
011
100
101
110
111

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-119

Table B-29

FPU Instruction Encoding Changes - MIPS III Revision.

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

bits 28..26
0
000

1
001

2
010

3
011

4
100

5
101

6
110

7
111

000
001
010
011
100
101
110
111

Instructions encoded by the fmt field when opcode=COP1.
31

26 25

opcode
= COP1
fmt
bits
25..24
0
1
2
3

bits 23..21
0
000

00
01
10
11

1
001
DMFC1

fmt

2
010

3
011

4
100

5
101
DMTC1

6
110

7
111

L δ

Instructions encoded by the nd and tf fields when opcode=COP1 and fmt=BC.
31

26 25

opcode
= COP1
t
f
n
d

0
bit 17 1

B-120

fmt
= BC

17 16

n t
d f

bit 16
0

BC1FL

BC1TL

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Table B-29 (cont.)

FPU Instruction Encoding Changes - MIPS III Revision.

Instructions encoded by the function field when opcode=COP1 and fmt = S, D, or L.
31

encoding when
fmt = S
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

fmt
=S

function

bits 2..0
0
000

1
001

2
010

3
011

ROUND.L

TRUNC.L

CEIL.L

FLOOR.L

4
100

5
101

6
110

7
111

CVT.L

encoding when
fmt = D
functi
on
bits
5..3

26 25

opcode
= COP1

26 25

opcode
= COP1

bits 2..0
0
000

1
001

2
010

3
011

ROUND.L

TRUNC.L

CEIL.L

FLOOR.L

FPU Instruction Set

fmt
=D

function

4
100

5
101

6
110

7
111

CVT.L

MIPS IV Instruction Set. Rev 3.2

B-121

encoding when
fmt = L
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

B-122

bits 2..0
0
000
*
*
*
*
CVT.S
*
*
*

26 25

opcode
= COP1

1
001
*
*
*
*
CVT.D
*
*
*

2
010
*
*
*
*
*
*
*
*

fmt
=L

3
011
*
*
*
*
*
*
*
*

function

4
100
*
*
*
*
*
*
*
*

MIPS IV Instruction Set. Rev 3.2

5
101
*
*
*
*
*
*
*
*

6
110
*
*
*
*
*
*
*
*

7
111
*
*
*
*
*
*
*
*

FPU Instruction Set

Table B-30

FPU Instruction Encoding Changes - MIPS IV Revision.

An instruction encoding is shown if the instruction is added or extended in this
architecture revision. An instruction class, like COP1X, is shown if the instruction class is
added in this architecture revision.
Instructions encoded by the opcode field.
31

opcode
opcod
e
bits
31..29
0
1
2
3
4
5
6
7

bits 28..26
0
000

1
001

2
010

3
011

000
001
010
011
100
101
110
111

4
100

5
101

6
110

7
111

COP1X δ

Instructions encoded by the fmt field when opcode=COP1.
31

26 25

opcode
= COP1
fmt
bits
25..24
0
1
2
3

bits 23..21
0
000

1
001

fmt

2
010

3
011

4
100

5
101

6
110

7
111

00
01
10
11

Instructions encoded by the nd and tf fields when opcode=COP1 and fmt=BC.
31

26 25

opcode
= COP1
t
f

bit 16

0
bit 17 1

0
BC1F
BC1FL

n
d

FPU Instruction Set

fmt
= BC

17 16

n t
d f

1
BC1T
BC1TL

MIPS IV Instruction Set. Rev 3.2

B-123

Table B-30 (cont.)

FPU Instruction Encoding Changes - MIPS IV Revision.

Instructions encoded by the function field when opcode=COP1 and fmt = S, D, W, or L.
31

encoding when
fmt = S
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

bits 2..0
0
000

C.F
C.SF

encoding when
fmt = D
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

bits 2..0
0
000

C.F
C.SF

encoding when
fmt = W or L
functi
on
bits
5..3
0
1
2
3
4
5
6
7

bits 2..0
0
000

26 25

opcode
= COP1

function

1
001

2
010

3
011

MOVCF δ

MOVZ

MOVN

C.UN
C.NGLE

C.EQ
C.SEQ

C.UEQ
C.NGL

26 25

opcode
= COP1

C.OLT
C.LT

5
101

6
110

RECIP

RSQRT

C.ULT
C.NGE

C.OLE
C.LE

7
111

C.ULE
C.NGT

function

2
010

3
011

MOVCF δ

MOVZ

MOVN

C.UN
C.NGLE

C.EQ
C.SEQ

C.UEQ
C.NGL

1
001

4
100

fmt
=D

1
001

fmt
=S

26 25

4
100

C.OLT
C.LT

5
101

6
110

RECIP

RSQRT

C.ULT
C.NGE

C.OLE
C.LE

7
111

C.ULE
C.NGT

opcode
= COP1

fmt
= W, L

2
010

3
011

function

4
100

5
101

6
110

7
111

000
001
010
011
100
101
110
111

B-124

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Table B-30 (cont.)

FPU Instruction Encoding Changes - MIPS IV Revision.

Instructions encoded by the function field when opcode=COP1X.
31

opcode
= COP1X
functi
on
bits
5..3
0
1
2
3
4
5
6
7

000
001
010
011
100
101
110
111

bits 2..0
0
1
000
001
LWXC1
LDXC1
SWXC1
SDXC1
*
*
*
*
MADD.S MADD.D
MSUB.S
MSUB.D
NMADD.S NMADD.D
NMSUB.S NMSUB.D

function

2
010
*
*
*
*
*
*
*
*

3
011
*
*
*
*
*
*
*
*

4
100
*
*
*
*
*
*
*
*

5
101
*
*
*
*
*
*
*
*

6
110
*
*
*
*
*
*
*
*

7
111
*
PREFX
*
*
*
*
*
*

Instructions encoded by the tf field when opcode=COP1, fmt = S or D, and
function=MOVCF.
31

26 25

opcode
= COP1
t
f

bit 16

0
1
MOVF (fmt) MOVT (fmt)

t
f

function
= MOVCF

fmt
= S, D

These are the MOVF.fmt and MOVT.fmt instructions. They
should not be confused with MOVF and MOVT.

Instruction class encoded by the function field when opcode=SPECIAL.
31

opcode
= SPECIAL
functi
on
bits
5..3
0
7

bits 2..0
0
000

000
...
111

FPU Instruction Set

1
001
MOVCI δ

2
010

function

3
011

4
100

5
101

6
110

7
111

MIPS IV Instruction Set. Rev 3.2

B-125

Instructions encoded by the tf field when opcode = SPECIAL and function=MOVCI.
31

t
f

bit 16

B-126

0
MOVF

opcode
= SPECIAL

t
f

function
= MOVCI

1
MOVT

These are the MOVF and MOVT instructions. They should
not be confused with MOVF.fmt and MOVT.fmt.

MIPS IV Instruction Set. Rev 3.2

FPU Instruction Set

Key to all FPU (CP1) instruction encoding tables:

This opcode is reserved for future use. An attempt to execute it causes
either a Reserved Instruction exception or a Floating Point Unimplemented
Operation Exception. The choice of exception is implementation specific.

α The table shows 16 compare instructions with values named C.condition
where “condition” is a comparison condition such as “EQ”. These
encoding values are all documented in the instruction description titled
“C.cond.fmt”.

β The SPECIAL instruction class was defined in MIPS I for CPU instructions.
An FPU instruction was first added to the instruction class in MIPS IV.

(also italic opcode name) This opcode indicates an instruction class. The
instruction word must be further decoded by examing additional tables
that show values for another instruction field.

λ The COP1X opcode in MIPS IV was the COP3 opcode in MIPS I and II and
a reserved instruction in MIPS III.

χ These opcodes are not FPU operations. For further information on them,
look in the CPU Instruction Encoding information section A 8.

(fmt ) This opcode is a conditional move of formatted FP registers - either
MOVF.D, MOVF.S, MOVT.D, or MOVT.S. It should not be confused with
the similarly-named MOVF or MOVT instruction that moves CPU
registers.

FPU Instruction Set

MIPS IV Instruction Set. Rev 3.2

B-127