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EK-TMBEF-MM-2

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Document:	TMB11/TU10W DECmagtape System Maintenance Manual (TMB11-E/F System)
Order Number:	EK-TMBEF-MM
Revision:	2
Pages:	396
Original Filename:	EK-TMBEF-MM-002%20TMB11-TU10W%20DECmagtape%20System%20Maintenance%20Manual%20(TMB11-E-F%20System).pdf

OCR Text

TMB11/TU10W
OeCmagtape system
maintenance manual
(TMB 11-E/F system)

..,

(

EK-TMB EF-MM-002

TMB11/TU10W
OeCmagtape system
maintenance manual
(TMB 11-E/F system)

digital equipment corporation • maynard, massachusetts

1st Edition, January 1977
2nd Edition, June 1979

Copyright © 1977, 1979 by Digital Equipment Corporation
The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC

PDP
DECUS
UNIBUS

DECsystem-lO
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS

3/80-15

CONTENTS
Page
CHAPTER 1

GENERAL INFORMATION

1.1
1.2
1.2.1
1.2.2
1.3
1.4
1.5

INTRODUCTION . . . . .
GENERAL DESCRIPTION
System Configuration
Physical Description .
SYSTEM FUNCTIONAL DESCRIPTION
APPLICABLE DOCUMENTS
.......... .
SPECIFICATIONS

CHAPTER 2

UNPACKING, INSTALLATION, AND ACCEPTANCE TESTING

2.1
2.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.6
2.8

SITE PLANNING AND CONSIDERATIONS
Space Requirements . . . . .
Power Requirements
Environmental Requirements
UNPACKING . . . . . . . . . .
TU10W Cabinet Unpacking
TMB 11 Unpacking
INSPECTION . . . . . . . . . .
TUIOW CABINET INSTALLATION
TMBl1 INSTALLATION/CABLING
System Unit Installation
Module Installation . . . . . .
....... .
Unibus Cabling
Controller/Master Drive Cabling
Securing Cables . . . . . . . .
TUIOW CABLING FOR A ONE-DRIVE SYSTEM
TU10W CABLING FOR A MULTIDRIVE SYSTEM
ACCEPTANCE TESTING . . . . . . . . . . . . . .

CHAPTER 3

SYSTEM OPERATING INSTRUCTIONS

3.1

CONTROLS AND INDICATORS
OPERATING PROCEDURES ..
Application of Power
Loading and Threading Tape
Unloading Tape . . . . . .
Restart After Power Failure
Restart After Fail-Safe
OPERATOR TROUBLESHOOTING

2.7

3.2
3.2.1
3.2.2
3.2.3

3.2.4
3.2.5
3.3

iii

1-1
1-1

1-1
1-1
1-8
1-15
1-16

2-1
2-1
2-1
2-1
2-1
2-1
2-3
2-3
2-3
2-6
2-6
2-8
2-8
2-8
2-12
2-12
2-15
2-17

3-1
3-1
3-1
3-3

3-5
3-6
3-6
3-7

CONTENTS (CONT)
Page
CHAPTER 4

CUSTOMER CARE AND PREVENTIVE MAINTENANCE

4.1

4.3
4.3.1
4.3.2
4.3.3
4.3.4

CUSTOMER RESPONSIBILITIES
. . . . . . . . . . . . . . . . . . . . . . 4-1
CARE OF MAGNETIC TAPE . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
CUSTOMER PREVENTIVE MAINTENANCE OF TUIOW TAPE TRANSPORT 4-2
General
4-2
Preventive Maintenance . . . . . . . .
4-2
Magentic Tape Drive Cleaning Kit .. .
4-3
Cleaning the TUI OW DECmagtape Drive
4-3

CHAPTERS

SYSTEM MAINTENANCE

5.1
5.2
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
5.4.1.4
5.4.2
5.4.2.1
5.4.2.2
5.4.2.3
5.4.2.4
5.4.2.5
5.4.2.6
5.4.2.7
5.4.2.8
5.4.2.9
5.4.2.10
5.4.2.11
5.4.2.12
5.4.2.13
5.4.3
5.4.3.1
5.4.3.2
5.4.3.3
5.4.3.4
5.4.3.5
5.4.3.6
5.4.3.7

SCOPE
.................... .
TMBII/TUIOW MAINTENANCE PHILOSOPHY
TEST EQUIPMENT . . . . . .
Standard Test Equipment .
Special Test Equipment ..
PREVENTIVE MAINTENANCE
Monthly PM Schedule . . .
Tape Path Cleaning and Inspection
Reel Hub Inspection and Lubrication
Operator Panel Check
NRZ Diagnostic . . . . . . . . . . .
Quarterly PM Schedule . . . . . . . . . .
Reel Motor Brakes/Vacuum System Belt
Voltage Check Setup
+5 Vdc Check (Drive Logic)
+12 Vdc Check (Drive Logic)
- 6.4 V Check . . . . . . . .
+12 Vdc Check (NRZ)
Forward Tape Speed and DC Balance Check
Reverse Tape Speed Check
Forward Jitter Check
Reverse Jitter Check .
Forward Skew Check
Reverse Skew Check .
Test Function Generator (TFG) Relocation
Semiannual PM Schedule
Forward Ramp Check
Reverse Ramp Check
Tracking Check
Erase Head Check ..
Read Amplifier Check
Residual Amplitude Check
Reverse Amplitude Check

4.2

5-1
5-3
5-4
5-4
5-4
5-4
5-6
5-6
5-7
5-9
5-10
5-10
5-10

5-12
5-13
5-13
5-13
5-14
5-14
5-15

5-15
5-16
5-16

5-18
5-18
5-18

5-18
5-19
5-20
5-22
5-25

5-26
5-26

CONTENTS (CONT)
Page
5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
5.5.1.5
5.5.1.6
5.5.1.7
5.5.1.8
5.5.1.9
5.5.1.10
5.5.1.1l
5.5.1.12
5.5.2
5.5.2.1
5.5.2.2
5.5.2.3
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
5.7.8
5.7.9
5..7.10
5.7.11
5.7.12

ADJUSTMENTS AND ALIGNMENT PROCEDURES
Adjustment Procedure . . . . .
TUI0W Power Supply ..
Capstan Servo DC Balance
Capstan Speed . . . . . .
Capstan Acceleration and Deceleration Times
Brake Adjustment (Electrical)
Read Amplitude Adjustment
Write Skew Adjustment . . .
Read/Write Interlock Assembly
Vacuum Motor Belt Adjustment
Read Circuitry Adjustment
Write Circuitry Adjustment
TMB 11 Adjustment Procedure
Alignment Procedure . . . . . . .
Objectives . . . . . . . . . .
Tools Required for Tape Path Alignment
Proced ures . . . . . .
CORRECTIVE MAINTENANCE
TMB 11-TUI OW Diagnostics
Corrective Action Flow Diagram
Functional Block Diagram . . .
TMB 11 /TUI OW Troubleshooting Procedures
REMOVAL AND REPLACEMENT PROCEDURES
Operator Control Panel . . . . . .
Door Seal (Front Casting Perimeter)
EOT /BOT Assembly . . . . . . . .
Reel Motor Filter Elements
Reel Hub Compression Ring and Teflon Washer
Reel Hub Assembly
Reel Motor . . . . . . . . . . . . .
Reel Motor Brakes . . . . . . . . . .
Vacuum Switches and Rubber Sleeves
Vacuum Motor Assembly . . . . . .
TUIOW Power Supply Regulator Board
TUI0W Transformer-Capacitor Assembly (7009636)

CHAPTER 6

TMBll THEORY OF OPERATION

6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4

INTRODUCTION . . . .
GENERAL OPERATION
Read . . . . . . .
Write
System Monitoring
Interrupts

· 5-27
· 5-27
· 5-28
· 5-28
· 5-28
· 5-29
· 5-30
· 5-31
5-34
5-36
5-36
5-38
5-38
5-39
5-39
5-39
5-40
5-40
5-61
5-61
5-61
5-63
5-63
5-64
5-65
5-65
5-66
5-66
5-66
5-68
5-69
5-70
5-70
5-72

5-73
5-73

6-1
6-1
6-2
6-2
6-2
6-3

CONTENTS (CONT)
Page

6.2.4.1
6.2.4.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.5
6.5.1
6.5.2
6.5.3
6.5.3.1
6.5.3.2
6.5.3.3
6.5.3.4
6.5.3.5
6.5.3.6
6.6
6.6.1
6.6.1.1
6.6.1.2
6.6.1.3
6.6.2
6.6.2.1
6.6.2.2
6.6.2.3
6.6.2.4
6.6.2.5
6.6.3
6.6.3.1
6.6.3.2
6.6.3.3
6.6.4
6.6.4.1
6.6.4.2
6.6.4.3
6.6.4.4
6.6.4.5
6.6.5
6.6.5.1
6.6.5.2

NPR Requests . . . . . . . . . . . . . .
BR Requests . . . . . . . . . . . . . . .
FUNCTIONAL BLOCK DIAGRAM DESCRIPTION
TMB11 REGISTERS . . . . .
Status Register (MTS) . . . . .
Command Register (MTC) . . .
Byte/Record Counter (MTBRC)
Current Memory Address Register (MTCMA)
Data Buffer Register (MTD)
Read Lines Register (MTRD)
PROGRAMMING NOTES
Rewind Operation
New Drive Selection
Error Handling
Write Operation
Read Operations
Write End-of-File Operation
Spacing Operations
Write-with-Extended-IRG Operation
Rewind Operation . .
FUNCTIONAL DESCRIPTIONS . . . . . . .
Processor Data Transfer . . . . . . . . .
Processor Out (DATO) Transfer (TMB11 Register Write)
Command Decoder . . . . . . . . . . . . . . . . .
Processor In (DATI) Transfer (TMB11 Register Read)
Operation Start
Basic Sequence
Time Out
Restart
OPI/BTE
Initialize
NPR Bus Cycle
Basic Sequence
Bus Grant Late (BGL) and Nonexistent Memory (NXM)
BUS NPGOUT . . . . . .
NPR Read (DATO) . . . . . . . . . . . . .
Transport Strobe Processing . . . . . .
9-Track and 7-Track Normal Operation
Core Dump Operation . . .
..... .
Processor Read
Even Character Strobe Logic
...... .
NPR Write (DATI)
9-Track and 7-Track Normal Operation
Core Dump Operation . . . . . . . . .

6-3
6-3
6-3
6-3
6-8
6-12
6-15
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-21
6-21
6-22
6-22
6-22
6-22
6-23
6-23
6-23
6-25
6-26
6-32
6-32
6-32
6-32
6-32
6-32
6-37
6-37
6-38
6-38
6-41
6-41
6-41
6-42
6-42
6-43
6-49
6-49
6-49

CONTENTS (CONT)
Page
6.6.5.3
6.6.5.4
6.6.6
6.6.7
6.6.8
6.6.8.1
6.6.9

Processor Write
Write Data Ready
Done Logic
Error Logic . . . . .
Interrupt Bus Cycle
BUSBGXOUT
Timing Diagrams

6-50
6-50
6-54
6-57
6-61
6-61
6-65

M8926 THEORY OF OPERATION

CHAPTER 7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.4.1
7.4.1.1
7.4.1.2
7.4.2
7.4.3
7.4.3.1
7.4.3.2
7.4.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.4.1
7.5.4.2
7.5.4.3
7.6

GENERAL . . . . . . . . .
STATUS/COMMAND LOGIC
Command Logic
Status Logic . . .
DRIVE START-UP
Drive Start Signals
Start-Up Delay
WRITE SEQUENCE . .
Nine-Track Normal
Write Data ..
Write-End-of-Record
Seven-Track Normal .
Nine-Track File Mark
Write Data . . .
Writ e-End-o f-Re cord
Seven-Track File Mark
READ SEQUENCE
Read Data . . . . .
Error Detection
File Mark Detection
End-of-Record Detection
Nine-Track Normal
Zero CRC or LRC Characters
Seven-Track and File Mark
DRIVE STOP . . . . . . . . . . . . . .

CHAPTER 8

TUIOW HOST TRANSPORT THEORY OF OPERATION

8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3

INTRODUCTION . . . . . . . . . . . . . . .
TRANSPORT OPERATION
........... .
Logic and Write (LAW) Module (M8910)
Slave Clock and Motion Delay Module (M8911)
Read Head and Read Amplifiers
TU10W Power Board
WRITE DATA PATH . . . . . . . .

vii

7-1
7-5
7-5
7-5
7-11
7-11
7-11
7-15
7-15
7-15
7-15
7-17
7-17
7-17
7-18
7-18
7-22
7-22
7-22
7-22
7-27
7-27
7-28
7-29
7-34

8-1
8-4
8-4
8-6
8-6
8-6
8-7

CONTENTS (CONT)
Page

8.10.5
8.10.6

READ DATA PATH
..... .
TEST FUNCTION GENERATOR
Functional Modes
Theory of Operation
CLOCKS
.....
System Clocks
Write Clock
TAPE MOTION ..
TUI0W Power Board H606
Capstan Servo Control and Driver
Tape Reel Braking and Motor Control Circuits
Motion Control Logic ..
Manual Control Operation
Tape Unit Status Sensors
On-Line Operation
Transport Selection and Status Reporting
Tape Motion Initiation (On-Line) .
Tape Motion Termination (On-Line)
Read
Write
Space
Rewind
READ (NRZ)
Read Heads and Amplifiers
WRITE (NRZ) . . . . . . . .
NRZ Data Write . . . . . .
NRZ Data Write Timing ..
NRZ Tape Mark Generation
Tape Mark Write Timing
TUlOW POWER SUPPLY . . .
Generation of Raw ±DC .
+5 Vdc Regulator Circuit
+12 V de Regulator Circuit (Write Circuits)
+12 V de Regulator Circuit (Control Switch Circuits)
- 6.4 V dc Regulator Circuit
Specifications . . . . . . . . . . . . . . . . . . . .

APPENDIX A

MAGNETIC TAPE FUNDAMENTALS

APPENDIX B

SYSTEM DIAGNOSTICS

APPENDIX C

FLOW DIAGRAM GLOSSARY

APPENDIX D

M8926 INTERFACE SIGNALS

APPENDIX E

TMB11/TUI0W DATA SHEETS

8.4
8.5
8.5.1
8.5.2
8.6
8.6.1
8.6.2
8.7
8.7.1
8.7.1.1
8.7.1.2
8.7.2
8.7.3
8.7.4
8.7.5
8.7.5.1
8.7.6
8.7.7
8.7.7.1
8.7.7.2
8.7.7.3
8.7.7.4
8.8
8.8.1
8.9
8.9.1
8.9.2
8.9.3
8.904

8.10
8.10.1
8.10.2
8.10.3
8.1004

viii

8-7
8-7
8-7
8-12
8-15
8-15
8-15
8-16
8-16
8-17
8-19
8-25
8-27
8-28
8-30
8-30
8-31
8-33
8-35
8-35
8-35
8-35
8-35
8-35
8-39
8-39
8-39
8-39
8-39
8-39
8-42
8-42
8-42
8-45
8-46
8-46

FIGURES
Figure No.
1-1
1-2
1-3
1-4

1-5
1-6
2-1
2-2

2-3
2-4

2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
3-1

3-2
3-3
4-1

4-2
5-1
5-2

5-3
5-4

5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20

Title
TMB11/TU10W Tape Drive System Configuration
TMB 11 Controller . . . . . . . . . . . . . . . .
TU10W with Transport Extended and Side Panels Removed
TU10W Transport, Front and Rear Views .
..... .
TUlOW Transport, Side Views
TMB 11 /TU1 OW Functional Block Diagram
Space and Service Clearance, Top View .
....... .
Installation of Filler Strips
Transport Hold-Down Shipping Brackets
Expander Box Backplane (BA11F box shown)
Power Cabling of TMB 11 System Unit in BAll F Box
TMBII Module Location and Cabling in BAlIK Box
TMB11 Module Location and Cabling in BAIIF Box
Unibus Cabling . . . . . . . . . . . . . . . . . . .
TMB 11 Mounted in System Unit . . . . . . . . . .
M8926 with H851 Edge Connectors and H8800 Terminators
M8926 Cabling
...................... .
TUlOW System Unit Module Location, Viewed from Backplane
TMBII/TUIOW Master/TUIOW Slave Cabling Diagram
Operator Control Box
................. .
Tape Loading Path
Fail-Safe Limits . . . . . . . . . . . . . . . . . . . .
Location of Read/Write and Erase Heads and Tape Cleaner
Proper Ceramic Washer Positioning
TUIOW Tape Transport Assemblies . . . . . .
....... .
Transport Casting, Front View
Examples of Unacceptable Head Assembly Wear
Hub Composition . . . . .
Reel Motor Brake Assembly . . . . . .
Belt Tension Gauge . . . . . . . . . .
TUIOW Power Supply Regulator Board
Tape Speed Check .
Jitter Check . . . .
Good Capstan Motor
Bad Capstan Motor
PACKET Waveform
Adjusting Mechanical Skew
Forward Acceleration Ramp
Reverse Acceleration Ramp
Developing Magnetic Tape .
Developed Magnetic Tape .
Track No. 1 to Reference Edge Measurement
Acceptably Erased Signal . . . . . . . . . .
Sample Table for Read Amplifier Comparisons

Page
1-2
1-3
1-4

1-5
1-6
1-12
2-2
2-4
2-5
2-6
2-7
2-9
2-10
2-11
2-12
2-13
2-14

2-16
2-18
3-1
3-4

3-7
4-4
4-4

5-1

5-3
5-6
5-7
5-11
5-12
5-13
5-15
5-15
5-16
5-16
5-17
5-17
5-19
5-19
5-20
5-21
5-22

5-23
5-24

FIGURES (CONT)
Figure No.
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
5-52
5-53
5-54
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10

Title

Page

Read Amplifier Output
Negative Half of Read Amplifier Output
Capstan FWD and REV Speed Waveforms
Acceleration and Deceleration Times
Read Amplifier Output . . . . . . . . .
Negative Half of Read Amplifier Output
Measurement of Pulse Positions Relative to Packet
Read/Write Interlock Assembly
Vacuum Motor Belt Adjustment
.... .
Reel Hub Adjustment . . . . . . . . . .
Location of Upper and Lower Roller Guides
Roller Guide Adjustments . . . . . . . . .
Measurement of Head Plate Mounting Surface (HMS)
Location of Shims under Head Plate Assembly
Machined Reference Surfaces Used to Establish Tape Path Plane
Head Plate Assembly Mounted in the Plane of the Tape Path
Examples of Capstan Non-Perpendicularity
Location of Possible Capstan Burrs . . . . . . .
Measuring Depth of Left Vacuum Column (LVC)
Alignment Glass . . . . . . . . . .
Using Alignment Glass to Load Tape
Capstan Motor Shim Placement
Capstan Motor Shim . . . . . . . .
Gap (Y) from Tape to Floor of Left Column
Measurement of Tape Gap (Y) with Penlight and Shim
Upper Spring-Loaded Guide Location . . . .
Capstan Wobble Check
............ .
Summary, Capstan Alignment Flow Diagram
TMBll/TUlOW Corrective Action Flow Diagram
Reel Motors, Rear View
Hub Composition . . . . . . . . . . . . . . . .
Reel Hub
................... .
Reel Motor Brush Locations and Brake Assembly
Vacuum Switches . . . . . . . .
TMBll Flow Diagram . . . . . . . . .
TMB 11 Functional Block Diagram
Status Register (MTS) Bit Assignments
Command Register (MTC) Bit Assignments
Byte/Record Counter (MTBRC) Bit Assignments
Current Memory Address Register (MTCMA) Bit Assignments
Data Buffer Register (MTD) Bit Assignments . . . . . . . .
Relationship Between Tape Characters and Memory Byte Characters
Read Lines Register (MTRD) Bit Assignments
New Drive Selection Flowchart . . . . . . . . . . . . . . . . . . .

5-25
5-26
5-29
5-30
5-32
5-33
5-35
5-37
5-38
5-41
5-42
5-43
5-45
5-46
5-47
5-47
5-48
. 5-49
5-50
5-51
5-52
5-54
5-54
5-55
5-56
5-58
5-60
5-60
5-62
5-67
5-67
5-68
5-71
5-72
6-4
6-6
6-8
6-12
6-15
6-15
6-16
6-17
6-17
6-20

FIGURES (CONT)
Figure No.
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12

Title
Command Decoder Logic Diagram
..... .
Processor In/Out Flow Diagram (DATI/DATa)
Processor Out (DATa) Block Diagram
Processor In (DATI) Block Diagram
Operation Start Flow Diagram
Operation Start Block Diagram
NPR Bus Cycle Flow Diagram
NPR Bus Cycle Block Diagram
Strobe Processing . . . . . .
Even Character Strobe Logic Diagram
Even Character Strobe Timing Diagram
NPR Read (DATa) Flow Diagram
NPR Read (DATa) Block Diagram
Write Data Ready Logic Diagram
Write Data Ready Timing Diagram
NPR Write (DATI) Flow Diagram
NPR Write (DATI) Block Diagram
Operation Done Flow Diagram
Operation Done Block Diagram
Error Sequence Flow Diagram .
Error Sequence Block Diagram
Interrupt Bus Cycle Flow Diagram
Interrupt Bus Cycle Block Diagram
Start of Tape Operation . . . .
Spacing Forward Three Records . .
Spacing Reverse Three Records
Spacing Forward Three Records, Bad Tape Error
Appearing in First Record . . . . . . . . . . . .
Reading Record of Three Data Characters . . . .
Reading Record of Two Tape Characters in Core Dump Mode
Writing Record of Three Data Characters . . . . . . . . . .
Writing Record of Two Tape Characters in Core Dump Mode
M8926 Simplified Flow Diagram
M8926 Detailed Flow Diagram
M8926 Block Diagram . . . . .
RWS (SB) and CRWS Timing Diagram
Command Latch-Up Flow Diagram
Status/Command Block Diagram
M8926 Timing Diagram . . . . .
Drive Start-Up Flow Diagram
Start/Stop Control Block Diagram
Write Data Timing Diagram
Write Flow Diagram
Write Block Diagram

Page
6-25
6-27
6-29
6-31
6-33
6-35
6-39
6-40
6-41
6-43
6-44
6-45
6-47
6-50
6-51
6-52
6-53
6-55
6-56
6-59
6-60
6-63
6-64
6-65
6-65
6-66
6-66
6-67
6-68
6-69
6-70
7-2
7-3
7-4
7-5
7-7
7-9
7-12
7-13
7-14
7-16
7-19
7-21

FIGURES (CONT)
Figure No.

7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
8-1
8-2
8-3
8-4
8-5
8-6

8-7
8-8
8-9
8-10
8-11
8-12

8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
8-24
8-25
8-26
8-27
8-28
8-29
8-30
8-31
8-32
8-33

Title
. . . . . . .
Read Flow Diagram . . . .
Read Block Diagram . . . .
. . . . . . .
End-of-Record Timing, Non-Zero CRC and LRC
End-of-Record Timing, Zero CRC
End-of-Record Timing, Zero LRC
End-of-Record Timing, Seven-Track
File Mark Timing . . . . . .
End-of-Record Flow Diagram
End-of-Record Block Diagram
Drive Stop Flow Diagram
TU10W System Block Diagram
Slave Bus Interface Signals
TU10W Tape Transport Block Diagram
Read Amplifier Output
Write Data Path . . . . . . . . . .
Read Data Path
TFG Operating Procedure Sequence
TFG Switch Settings
..... .
Test Function Generator Module
SSRD Function . . . . . . .
SSWRT Function . . . . . . . .
WRT CLK Generation Timing ..
Tape Motion Control Block Diagram
Servo Feedback Loop . . . . . . .
Tape Transport Mechanism
Reel Motor Amplifier Equivalent Circuit
Brake Current Waveforms . . . . . . .
Rewind Sequence Timing . . . . . . .
Tape Markers, Recording Area, and Tape Wind
Tape Motion Timing . . . . . . . . .
Tape Motion Initiation Flowchart . . . . . . .
Tape Motion Termination Flowchart . . . . .
Equivalent Circuit of Read Circuitry for One Track
Read Amplifier Waveforms (NRZ)
Programmable Threshold . . . . . . . . . . . . .
TU10W Power Supply Regulator Board . . . . . .
TU10W Regulator Board (Cover Removed) and Fan
TU10W Power Supply Block Diagram
.'
+5.3 Vdc Regulator Circuit
Current Foldback Operation
+ 12 V Regulator Circuit
+ 12 V Regulator Circuit
- 6.4 V Regulator Circuit

xii

Page
7-24
7-25
7-27
7-28
7-29
7-30
7-30
7-31
7-33
7-35
8-1
8-2
8-5
8-6

8-8
8-9
8-10
8-11
8-11
8-13
8-14
8-16
8-17
8-18
8-20
8-21
8-24
8-26
8-29
8-31
8-32
8-34
8-36
8-37
8-38
8-40
8-41
8-43
8-44
8-44
8-45
8-46
8-47

TABLES
Table No.
1-1
1-2

1-3
1-4

3-1
3-2
5-1

5-2
5-3

5-4
5-5
5-6
5-7
6-1
6-2
6-3
6-4

6-5
6-6
8-1

8-2
8-3
8-4

8-5

Title
TVIOW Models
Controller Functions
Applicable Documents
TMB 11 ITDl OW Specifications
TU10W Control Box Switches
Status Indicators
..... .
Standard Test Equipment Required
Special Tools and Equipment and Their Use
TVIOW Power Supply Regulated Voltages
Read Amplitude Test Points
Write Deskew Parameters . . . . . . . .
Diagnostic Descriptions . . . . . . . . .
TVlOW DECmagtape Transport Troubleshooting Hints
Device Register Functions . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . .
Function Decoder Output vs Transport Commands
Decoder ORed Functions for TMB11 . . . . .
Data Multiplexing in 9-Track, 7-Track Normal,
and Core Dump Modes
........... .
Write Data Gating for 9-Track, 7-Track Normal
and Core Dump Modes
Slave Bus Interface Signals
Write Clock Frequencies .
Start and Stop Motion Delays
Power Supply Input Specifications
Power Supply Output Specifications

xiii

Page
1-8
1-9
1-15

1-16
3-2

3-3
5-4
5-5

5-28
5-33
5-35

5-61
5-63

6-7
6-24

6-25
6-26

6-42
6-49
8-3
8-15
8-33
8-47
8-48

PREFACE

Chapters 1 through 5 of the TMBll jTUlOW DECmagtape System Maintenance Manual cover the
description, installation, operation, and maintenance of the TMBl1/TVlOW as a system. Chapters 6,
7, and 8 describe the theory of operation of the TMBII Controller, M8926 Interface Module, and the
TV lOW Tape Transport. These chapters describe the respective units in detail, with only general
references to other areas of the system. They contain functional block diagrams and flow diagrams to
illustrate the operational sequences occurring within these units. A glossary of the symbology used in
the flow diagrams is contained in Appendix C.

TMBll/TU10W DECmagtape System

CHAPTER 1
GENERAL INFORMATION

1.1 INTRODUCTION
The TMBII-EX/FX* DECmagtape System (TMBll/TUlOWt) is a magnetic tape storage system
that interfaces with the PDP-ll family of processors and peripherals and provides storage for digital
information. The system reads and records digital data in a forward direction in an industry-compatible NRZI format at a maximum data transfer rate of 36,000 tape characters per second. Tape
density and tape character format are program selectable. Forward/reverse tape speed is 114 cm (45
inches) per second while rewind is performed at 381 cm (150 inches) per second. The TMBll/TUlOW
Tape Drive System has forward and reverse spacing capability.
1.2

GENERAL DESCRIPTION

1.2.1 System Configuration
The basic TMBll/TU10W DECmagtape System configuration is a TMBll Controller and a TUlOW
Master Tape Transport. From one to seven "slave" transports may be added to make a maximum
possible configuration of one TMBII Controller and eight tape transports. The master tape transport
is composed of a "host" transport and an M8926 Interface module. The M8926 interfaces the "host"
transport and the slave transports (if any) to the TMBll via the BellA master bus cable. All the tape
transports are "daisy chained" on the slave bus, making them essentially parallel with each other.
Figure 1-1 is an illustration of the TMBll/TUlOW system configuration.
1.2.2 Physical Description
The TMBII consists of the following six modules:
1.
2.
3.
4.
5.
6.

MIaS Address Selector Module
M795 Word Count and Bus Address Module
M796 Unibus Master Control
M7821 Interrupt Control Module
M7911 Tape Drive Interface
M7912 TMBll Unibus Registers

*The TMB11-EX is a 9-track system. The TMBII-FX is a 7-track system. "X" specifies the system voltage and
frequency requirements (Table 1-1).
tThe TMB11-EXjFX system is commonly referred to by its component subunits, the TMBll and TVlOW,
hence the manual title TMBlljTUJOW DECmagtape System Maintenance Manual. Within this manual, the
system is referred to as the TMB 11 JTV lOW.
1-1

BCllAMASTER
BUSCABLE

-TU 1OW
MASTE R
~

TAPE TRANSPORT

I
DECMAGTAPE
CONTROLLER
TMBll

I--t---+-'---t---I

v
WRITE STROBE

MB926
INTERFACE
MODULE

"HOST"
TAPE
TRANSPORT

I
I
I

-.J
TU10W
SLAVE TAPE
TRANSPORT
NO. n

WRITE DATA

In = 1 TO 71

TAPE
TRANSPORT

STATUS
READ STROBE

<'"'0

11-4783

Figure 1-1

TMBll/TUlOW Tape Drive System Configuration

The six modules are plugged into a TMBll system unit that is mounted in an expander box (Figure 12). Unibus input, Unibus output, and tape transport cabling also connect to the system unit. The
TMBII Controller interfaces the DECmagtape system to the PDP-I1 Unibus. It controls data transfers, issues control commands to the TU lOW master, and monitors system operation. Each TMBII
can control one master transport and up to seven slave transports.
The TUlOW Tape Transport is contained in a single 48.3-cm (19-inch) cabinet along with an 861
Power Controller (Figure 1-3). Figures 1-4 and 1-5 illustrate front, rear, and side views of the transport
and identify many of the TU lOW components and subassemblies.

1-2

TMB11
MODULES (6)

7941-6

Installed in BAliK Expander Box

TMB11
MODULES (6)

7997 -2

Installed in BA II F Expander Box
Figure 1-2

TMBII Controller
1-3

TAPE
TRANSPORT

VACUUM
MOTOR

861 POWER
CONTROLLER

8209-4

Figure 1-3

TV lOW with Transport Extended
and Side Panels Removed
1-4

TRANSPORT,________
SERVICE LOCK

1i~iiiiiiiiiiiiiii

CAPSTA N _ _'--"--",*"o.L

TAPE CLEANER
HEAD PLATE ASSEMBL
(COVER REMOVED)

EOT/BOT
ASSEMBL Y

CONTROL PANE
CE

7660-22·A058Q

a. Front View

CABINET FAN

LOGIC ASSEMBLY
FAN

POWER SUPPL Y
REGULATOR BOARD

SHIPPING
BRACKETS

VACUUM HOSE

TRANSFORMER/CAPACITOR
ASSEMBLY

8209-9

b. Rear View

Figure 1-4 TUlOW Transport, Front and Rear Views
1-5

BRAKE ASSEMBLY

AIR FILTER
SERVICE LOCK

ASSEMBLY

CAPSTAN MOTOR
H606 POWER BOARD

AKE -UP REEL MOTOR

LOGIC BACKPLANE
ASSEMBLY

VACUUM SWITCHES

POWER SUPPL Y
REGULATOR BOARD

FILE REEL MOTOR

VACUUM SWITCHES

TRANSFORMER-CAPACITOR ~~~--'------'
ASSEMBLY

VACUUM HOSE
(TO VACUUM MOTOR)

READ/WRITE

BRAKE ASSEMBLY

AIR FILTER

8209 -5

Left Side

Figure 1-5 TV lOW Transport, Side Views (Sheet 1 of 2)

1-6

H606
POWER BOARD

G056

M8910

M8926
(NOTE 2)

POWER
SUPPLY
REGULATOR
BOARD

M8911
M8912

(NOTE 1)

NOTES:

1. 9 track transports only. M8911.YA used for 7-track transports.
2. Master transport only. Slave transport contains cable cards M9001.
M8913 and M9001·YA in this slot.

b. Right Side
Figure 1-5

TV lOW Transport, Side Views (Sheet 2 of 2)

1-7

8110·1

The TUlOW master transport consists of an M8926 Interface module and a "host" transport. The
M8926 processes commands from the controller and issues motion and read/write commands to the
host and slave transports; the M8926 also monitors status lines from the host and slave transports.
Any status changes at the selected transport are reported immediately to the controller. In response to
inputs from the M8926 module, the host transport (if selected) controls tape motion and records and
reads data on magnetic tape.
The TUlOW slave transport consists of a tape transport only. In response to inputs from the M8926
module in the master transport, it controls tape motion and records and reads data on magnetic tape.
The slave transport contains three cable cards (M9001, M8913, and M9001-Y A) which replace the
M8926 module in the master transport.
The various models of the TUlOW Transport are identified by a 2-1etter dashed suffix. The first letter
of the suffix designates the number of tracks on the transport: E for a 9-track transport, F for a 7-track
transport. The second letter identifies the transport as a master or a slave (A, B, C, D = master; E, F,
H, J = slave) and specifies the voltage and frequency requirements. Table 1-1 summarizes the TUIOW
models and their identifying suffix.

Table 1-1 TUl OW Models
TUl OW-EX (9-track)

TUlOW-FX (7-track)

Master/Slave

Voltage/Frequency

Master

115 V/60 Hz
230 V/60 Hz
115 V/50 Hz
230 V/50 Hz
115 V/60 Hz
230 V/60 Hz
115V/50Hz
230 V/50 Hz

C
Slave

D
E

F
H
J

Master/Slave

Voltage/Frequency

Master

115 V/60 Hz
230 V/60 Hz
115 V/50 Hz
230 V/50 Hz
115 V/60 Hz
230 V/60 Hz
115 V/50 Hz
230 V/50 Hz

C
Slave

D
E

H
J

1.3 SYSTEM FUNCTiONAL DESCRIPTION
The basic functions performed by the controller are: off-line, read, write, write EOF, space forward,
space reverse, write-with-extended-IRG, and rewind. Each of these functions is briefly described in
Table 1-2.

1-8

Table 1-2

Controller Functions

Function

Description

Off-Line

The off-line function is used to return control to the tape transport so that tape can be rewound, reels changed, etc. without
using processor time.
The off-line function places the selected tape transport in the
off-line (local) mode and causes it to begin a rewind operation.
The controller cannot write on or read from the magnetic tape
when the off-line function is used. Manual intervention is
required to return the drive to on-line status, i.e., the ON-LINE
button must be pressed.

Read

This function permits reading from the magnetic tape. During
the read operation, the data portion of the record is loaded into
the controller data buffer for transfer to the memory. The LRC
and CRC characters are read but not transferred into memory.

Write

This function permits writing on the magnetic tape. During the
write operation, data from the bus is loaded into the controller
data buffer register. The controller then transfers the data to the
tape transport write heads. The necessary LRC and CRC characters are generated by the master transport and written on the
tape following the data. The write function advances the tape
one record.

Write EOF

This function writes an end-of-file (EOF) mark on the tape.
When selected, this function erases a 3-inch segment of tape
prior to writing the first character. The EOF mark and the associated LRC character are considered one record. The EOF
mark is an octal 23 character (9-track drive) or octal 17 character (7-track drive) followed by an octal 23 (or octal 17) LRC
character.

Space Forward

This function is used to skip over a number of records to find a,
specific record on the tape. When selected, the space forward
function causes the tape transport to advance a specified number of records. The program loads the byte record counter with
the two's complement of the number of records to be spaced
over. Detection of the end-of-file mark terminates a space
operation.
Space forward is used for tape positioning only and, therefore,
does not affect information stored on the tape or in memory.

Table 1-2

Controller Functions (Cont)

Function

Description

Space Reverse

This function is identical to the space forward function except
the tape moves in the reverse rather than in the forward
direction.

Write-with-Extended-IRG

This function is identical to the write function except that a
7.62-cm (3-inch) segment of tape is erased before writing the
first character.

Rewind

This function is used for rewinding the tape on the feed reel so
that the tape can either be unloaded from the transport or operation can start at the beginning of the tape. When this function
is used, the tape moves in the reverse direction, at a much higher
speed (3.81 meters/second, 150 inches/second) than for other
functions, until the beginning-of-tape (BOT) marker is detected.
When the BOT marker is detected, the tape slows down and
comes to a complete stop at a point beyond the BOT marker. It
then moves forward until the BOT marker is again detected,
which is when it comes to a final stop.
Rewind is used for tape positioning only and has no effect on
information stored on the tape or in the memory.

Figure 1-6 is a functional block diagram of the TMB 11 /TV lOW DECmagtape System. The processor
initiates a TMB 11 /TV lOW operation by addressing the TMBll registers via the address decoder and
loading the operation parameters into the registers. The BVS CO-Cl bits specify an out transfer (with
respect to the processor), causing SEL OUT to be asserted for the particular register addressed. As
each register is selected, the processor places the appropriate data on the V nibus data lines; the data is
then loaded into the register with the SEL OUT strobe. Thus, the command register receives the type
of operation to be performed; the byte record count register receives the number of bytes to be transferred; and the current memory address register receives the memory address of the first byte to be
transferred.
The command register selects which transport is to be involved in the transfer via the SEL O-SEL 2
lines, supplies the function command to the command decoder which generates the required commands for the tape transport, and asserts the GO bit to the start logic. When the start logic senses that
the tape transport has been selected (SELR) and is ready (TVR), it asserts SET to the M8926 Interface,
which then asserts SLAVE SET PLS to the transport to start the operation. If a read, write, or space
forward operation is commanded, the transport command logic asserts FOR to the tape drive system
which drives the capstan servo and moves the tape forward. When the tape is up to speed, the M8926
read channels are enabled by READING and start to transfer data from the read heads to the controller. The read data from the tape transport (RDO-RD7, RDP) is checked for eRe, LRC, and
vertical parity errors by the M8926 board.
If any such errors are detected, the TMBl1 error logic is notified (CReE, LRCE, VPE) for appropriate corrective action. The read data is supplied to the controller along with a read strobe (RDS), which
signifies the availability of read data from the transport. RDO-RD7 are routed through transport
receivers and become CHAN O-CHAN 7.

1-10

If a read operation is commanded by the command register, the CHAN O-CHAN 7 read data is gated
to the data buffer register where it is loaded into the register by RDS. RDS also requests an NPR
transfer from the NPR logic. When the request is granted, BUS BBSY is asserted by the logic along
with DATA - t BUS, which gates the output of the data buffer to the Unibus data bus (BUS DOO-D 15)
via the register select output multiplexer. DATA - t BUS accomplishes this by asserting either HI
DATA BYTE or LO DATA BYTE from the read byte select logic according to whether the CMA
register is addressing the low byte or the high byte in memory. Thus, the data byte from the data buffer
will output on either BUS DOO-D07 or BUS D08-DI5. The next character read will output on the
alternate half of the data bus. When the NPR logw receives BUS SSYN from memory, it asserts NPR
CLEAR BBSY, which increments the byte record counter and the CMA register to prepare for the
next trap.sfer.

When the M8926 read logic detects the end of a record, it asserts CRCS (9-track only) and LRCS to
the controller and RD CLR PLS to the motion control logic. The motion control logic asserts EMD
and STOP to the drive to stop the capstan servo motor.
If a write operation is commanded by the command register, the GO bit, in addition to enabling the
start operation logic, requests an NPR transfer from the NPR logic. When the request is granted, the
logic asserts BUS BBSY and BUS MSYN. The memory responds with SSYN to indicate that the first
data character is on the data bus (BUS DOO-DI5). The NPR logic asserts DATA STB 2, which loads
the data character into the data buffer, thus making it available to the transport as WDO-WD7. The
data character enters the data buffer via one of two gates. In the write mode CMA BIT 00 asserts either
SEL LO BYTE or SEL HI BYTE, according to whether the CMA register is addressing the low byte
or the high byte in memory, thereby enabling the gate corresponding to the location of the character
on the data bus.
Meanwhile, the start operation logic has asserted SET to the M8926 Interface, which sends SLAVE I
SET PLS to the transport, causing the transport command logic to assert FOR and start the capstan
servo system moving forward. When the tape is up to speed, the drive sends WRT CLK pulses to the
M8926 write channels and writing of the data characters begins. WDR (write data ready) from the
controller enables the write channels that transfer the write data from the controller to the write heads
in the tape drive. The write channel logic produces REC pulses which record the data characters on
tape via the write heads. A parity bit is generated for each character and is recorded on tape along with
the character. When all the data has been transferred to tape, WDR negates, enabling the end-ofrecord generator which functions to place the CRC character (9-track only) and the LRC character on
tape.
Each time a data character (not the CRC or LRC character) is written on tape, a WRS pulse is issued
to the controller, requesting the next character to be written. The WRS pulse makes an NPR request
from the NPR logic and the cycle is repeated. Note that in a write operation, the GO bit makes the first
NPR request and the WRS strobes make the second and subsequent requests. After the NPR logic
issues DATA STB 2, it asserts NPR CLEAR BBSY, which increments the byte record counter and the
CMA register to prepare for the next transfer. When the byte record counter senses that the desired
number of bytes have been transferred (written), it asserts CARRY OUT 2, which negates WDR to the
transport, thereby signaling the M8926 write logic to write the end-of-record check characters (CRC
and LRC).
The M8926 read logic is enabled during a write operation and reads each character approximately 3 ms
after it is written. The read heads are displaced from the write heads by 3.8 mm (0.15 inches). Thus,
depending on density, from 30 to 120 characters are written between the time a given character is
written and read back. When the read logic detects (reads) the end of the record, it issues a CRCS (9track only) and LRCS strobe to the controller.

1-11

C
GATE

GATE
M7912
COMMAND
DECODER
M7911
OPERATION PARAMETERS
BYTE/RECORD COUNT
16 STATUS BITS

BUS
INTERRUPT
LOGIC

DATA BFR
OUT BIT 11J-7

READ

CURRENT MEMORY ADDRESS

WRITE
M7821

WDR

WRITE
CARRY OUT 2

L lOUT
COMMAND
REGISTER
(REG 1)

DONE LOGIC

M7911
SEL 4 OUT

LRCS

DATA STB 2
(WRITE LOAD)

DATA BUFFER
(REG 4)

CARRY OUT 2
DATA BFR IN
BIT 11J-7
SEL 2 OUT
NPR
LOGIC

BYTE/RECORD
COUNT
REGISTER
(REG 2)

AD LOAD)

M795
M796/M7821
STATUS
REGISTER

RR (1)

M7911

CMA
REGISTER
(REG 3)
ADDRESS
DECODER
ECT TMBII
REGISTERS) j--.:::.~:::...!!':':":::""-'--

ERROR
LOGIC

-"-'-'-'-'--'=-----+\ WR I T E BYTE !-,S:..:E:..:L:..-=:LO::...::..:...:..:=----,
SELECT

SEL HI BYTE

M795
HI DATA BYTE
-BUS

LO DATA BYTE

Ml05/M7912

I
I

4------------------------------------------------------------------------------TMBII ----------------------------------------------------------------------------------------~·I

I
11-3988

Figure 1-6 TMB11/TUlOW
Functional Block Diagram
(Sheet 1 of 2)

1-12

r.~wRiTE LOGic
.-• -v:

C
lSEE NOTE

oa)
o

CWDO-CWD7
CWDR

TU10W HOST dR SLAVE TRANSPORT
RECORD
LOGIC & WRITE

CWRE
EPEVN

CDEN5

TAPE DRIVE SYSTEM
,

FOR
REV/REW

REWIND CAPSTAN

L --~

END OF
RECORD
GENERATOR

CD ENS
CSELO-CSEL2

WRITE DATA LINES

---- -----

POWER BOARD

LOWER REEL
& BRAKE DRIVE

,
J

VACUUM MOTOR ENABLE

CAPSTAN
SERVO

-- - 1
~

UPPER REEL & BRAKE DRIVE

(HS06)

)

€§9D
D8(j

VACUUM SWITCH SIGNALS

VACUUM
SYSTEM

I
I

L - I - - - - --- ----------- J

-- -- --

SLAVE SELECT

CSET

(

I----~-

FILE MARK
GENERATOR

II I
CPEVN

WDO(SB)-WD7(SB)

EWFMK
7TRK

PARITY
GENERATOR

r -

(1/2) (M8910)

WRITE
CHANNELS

CRWD

COMMAND

CFWD

LOGIC.

'W.,""}

FWD(SB)

COMMANDS:
FWD, REV, RWND & WRITE

REV(SB)

WRITE(SB)
SLAVE SET PULSE

CREV

";,.

CWRE

o "

STOP

L-

CWFMK

I
/

CWXG

EWFMK

SET

-'2.. SEE NOTE

RD CLR PLS

CWRS

READING

READ LOGIC

CRDO-CRD7,RDP
CRDS

CFMK

)

CCRCS

)

CLRCS

"
/

CVPE

OUTPUT
GATE

CCRCE
CLRCE

CEOT

READ
CHANNELS

L_--,
I

T
RD CLR PLS

1=
I

--r•
I

FILE MARK
DETECTOR

iERASE

READ AMPS
(G05S)

,WRITE

-- -- -- I-- - - -

,READ

L- _ _ ..J

OFF·LlNE
CONTROL

)

CWRL

LOGIC & WRITE

CSDWN

(2/2) (M8910)

CSELR

TRANSPORT

CTUR

STATUS

CRWS

LOGIC

G {~

G "-

STATUS

-I

7TRK

INDICATOR
SIGNALS

CON~ROLPANEL
swm;:HES

INDICATORS
I

SLAVE BUS

CBOT
C7CH

)

o {;

WRTCLK

ERROR
DETECTOR

READ DATA LINES

(RSDO) READ STROBE DELAY OVER

I
I

SLAVE CLOCK
& MOTION
MS911 = 9 TRACK
MS911·YA = 7 TRACK

RDO-RD7,RDP

......

END OF
RECORD
DETECTOR

ACCL

---r-l
.

ENABLE MOTION DELAY

START/STOP
MOTION
CONTROL

NOTE:
Lettering on connectors C and D are connecting

TU10W
POWER
SUPPLY

points to other half of this illustration.

They do not represent connector pin lettering.
I
I
I.~.-~---------------------------M892SINTERFACE-----------------------~.~I
••----------------------------TU10WTRANSPORT----____________________________~.I
11-4798

Figure 1-6 TMB 11 lTV lOW
Functional Block Diagram
(Sheet 2 of 2)
1-13

The LRCS strobe at the end of the record indicates to the controller that the data transfer is complete.
The LRCS strobe is applied to the done logic, which then asserts DONE DELAYED to the bus
interrupt logic. The interrupt logic requests a bus interrupt to notify the processor that the command
operation has been completed and the TMBII/TUIOW is ready for another command.
The TMBII error logic monitors transport status including parity, CRC, and LRC errors and asserts
ERR (1) to the done logic if an error condition exists. Some types of errors warrant terminating an
operation before it is complete while others wait until the end of the operation before asserting ERR
(1).

The processor can read the TMBII registers by addressing the registers and requesting an in-transfer
(with respect to the processor) via the BUS CO-Cl bits. The address decoder then asserts SEL IN for
the particular register selected; this gates the register bits out to the data bus via the register select
output multiplexer.
Detailed operation of the TMBII is given in Chapter 6 of this manual. Detailed operation of the
M8926 Interface board and the TUI0W Tape Transport are given in Chapters 7 and 8. Figure 1-6 can
be used along with the functional block diagrams and flow diagrams contained therein.

1-14

I
j

1.4 APPLICABLE DOCUMENTS
Table 1-3 lists documents that are applicable to the TMBll/TUlOW DECmagtape System.

Table 1-3 Applicable Documents
Title

Number

Description

861-A,B,C Power
Controller Maintenance Manual

EK-86lAB-MM-002

Contains theory of operation and maintenance
instructions for the 861 Power Controller.

PDP-II Processor
and Systems
Manual

A series of maintenance and theory manuals that
provide a detailed description of the basic
PDP-II system.

PDP-II Processor
Handbook

A general handbook that discusses system architecture, addressing modes, the instruction set,
programming techniques, and software.

PDP-II Peripherals
Handbook

112-00973-2908

A handbook devoted to a discussion of the
various peripherals used with PDP-II systems.
It also provides detailed theory, flow, and logic
descriptions of the Unibus and external device
logic; methods of interface construction; and
examples of typical interfaces.
Presents functions and specifications of the
M-series logic modules, accessories, and connectors used in the TMB 11 Controller and the
TUlOW DECmagtape Transport. Includes other
types of logic produced by DIGITAL but not
used with PDP-II devices.

DIGITAL Logic
Handbook,
1973-74 Edition

Paper-Tape Software Programming
Handbook

DEC-Il-GGPB-D

Provides a detailed discussion of the PDP-II
software system used to load, dump, edit,
assemble, and debug PDP-II programs; input/
output programming; and the floating-point
and math package.

*Applicable manuals are furnished with the system at the time of installation.
The document number depends on the specific PDP-II family processor.
tUse the processor handbook unique to the actual CPU.

1-15

1.5 SPECIFICATIONS
Table 1-4 contains operational, environmental, mechanical, and electrical specifications for the
TMBl1jTUlOW Tape Drive System.
Table 1-4 TMBll/TUlOW Specifications

Main
Specifications

Data
Organization

Tape Motion

Tape
Characteristics

Mechanical

Description

Number

Title

Storage medium

1.27-cm (1/2-inch) wide magnetic tape (industrycompatible)

Capacity /tape reel

23 million characters

Data transfer rate

36,000 char/second

Drives/control,
maximum

Number of tracks

7 or 9

Recording density

200, 556, 800 bits/inch; program-selectable

Interrecord gap

1.27 em (0.5 inch) minimum; 1.65 cm (0.65
inch) nominal

Recording method

NRZI: industry-compatible

Speed (forward and
reverse)

1.14 m/second (45 inches/second)

Rewind speed

3.8 m/second (150 inches/second)

Tape drive

Single capstan; vacuum columns

Start/stop distance

6.3 mm (0.25 inches)

Start/stop time

8 ms maximum

Width

1.27 cm (0.5 inches)

Length

731.6 m (2400 ft)

Type

Mylar base, iron-oxide coated

Thickness

0.038 mm (1.5 mils)

Tension

227 g (8.0 oz)

Reel diameter

26.7 cm (10.5 inches)

Reel hub

9.37 cm (3.69 inches) diameter (industry
standard)

TMB 11 Controller

Mounts in a single 41.9 X 5.7 cm (16-1/2 X
2-1/4 inch) system unit

Tape drive, mounting

Mounts on slides in a standard 48.3-cm (19-inch)
cabinet

1-16

Table 1-4 TMBll/TU10W Specifications (Cont)

Mechanical
(Cont)

TUlOW Transport
(without cabinet)
Depth

Power

Operating
Environment

Miscellaneous

0.64 m (25 inches)

Width

0.48 m (19 inches)

Height

0.66 m (26 inches)

Weight

70 kg (150 Ib)

861 Power Controller
Depth

Interchannel
Displacement

Description

Number

Title

0.20 m (8 inches)

Width

0.48 m (19 inches)

Height

0.13 m (5 inches)

Weight

4.54 kg (10 lb)

Write

1.9 Mm (75 Min) maximum

Read

1.9 Mm (75 Min) maximum

Erase head

Full width

Input current (TMB 11)

5Aat+5Vdc

Input current (TVl OW)

8 A at 115 V; 4 A at 230 V

Input Power (TVl OW)

920 VA

Voltage

115/230 Vac ± 10%

Frequency

47 to 63 Hz; single phase

Temperature

15° to 32° C*

Relative humidity

20 to 80%, with maximum wet bulb 25° C and
minimum dew point 2° C (no condensation)*

Altitude

2438 m (8000 ft) maximum

BOT, EaT detection

Photoelectric sensing of reflective strip,
industry-compatible

Broken tape detection

Vacuum fail-safe

Read/write head
displacement

3.8 mm (0.15 inch)

Electrical skew

Write deskew only. Read skew mechanically
aligned

*Magnetic tape operation is more reliable if the temperature is limited to 18° to 24° C (65° to 75° F) and the
relative humidity to 40 to 60%.

1-17

CHAPTER 2
UNPACKING, INSTALLATION,
AND ACCEPTANCE TESTING

2.1

SITE PLANNING AND CONSIDERATIONS

2.1.1 Space Requirements
Figure 2-1 illustrates the space and service clearances required for the TU1 OW cabinet. Adequate space
must be provided to slide the equipment out of the rack for servicing and to open the front door on the
TUlOW DECmagtape Transport. The TMBll is housed in the processor cabinet or in an expansion
cabinet.
2.1.2 Power Requirements
The TMBll/TUlOW DECmagtape System can be operated from a nomina1115 or 230 Vac, 50/60 Hz
power source. Line voltage should be maintained to within 10 percent of the nominal value and the
frequency should not vary more than 3 Hz.
2.1.3 Environmental Requirements
The TUIOW DECmagtape Transport should be located in an area free of excessive dust, dirt, corrosive fumes, and vapors. To ensure proper cooling, the bottom of the cabinet and the fan inlet at the top
of the cabinet must not be obstructed. The operating environment should have cool, well-filtered,
humidified air; a temperature range of 15° to 27° C; and relative humidity of 40 to 60 percent.
2.2 UNPACKING
The TMBll may be shipped in two different configurations: installed in an equipment rack or packaged separately. Unpacking and installation procedures vary depending on the system configuration.
For example, if the user has ordered a complete PDP-II system, the TMBl1 is shipped installed in its
appropriate rack. However, if only a part of the system is shipped because the user already has a basic
PDP-II system, then the TMBll is shipped separately with the appropriate cables.
2.2.1 TUIOW Cabinet Unpacking
To unpack the cabinet, proceed as follows:

Remove the outer shipping container.
NOTE
The container may be either heavy corrugated card=
board or plywood. In either case, remove all metal
straps first, then remove any fasteners and deats
securing the container to the skid. If applicable,
remove wood framing and supports from around the
cabinet perimeter.

Remove the polyethylene cover from the cabinet.

2-1

SWINGING DOOR
(RH) NOTE 1

18 }3~
(46.35cm)

REMOVABLE
END PANEL
REMOVABLE
END PANEL _ _ _ _

'--u---------,
I

I
I

487/

(122.47cm)

CABLE ACC ESS - -_ _ _ _ _--!-!-__

FAN
PORTS

/--\/-~-;

30"
(76.2cm)

I\~

LEVELER
4 PLACES

~ ...... - _ /

+
CASTER SWIVEL
RADIUS 2 1%~
(4) CASTERS

!
I.J.o.->------

2111/16

(54.87 em)

TU10W EXTENDED
FROM CABINET

25"
(63.5 em)

NOTES:
1. Door may be L.H. or R.H.
Allow space for either case.
717/1~ (182 .28cm) high
2. Cabinet
(floor line to cabinet tap).

L _______ -.J _ _ _ _

...L..

11-4800

Figure 2-1

Space and Service Clearance, Top View

2-2

Unbolt cabinet(s) from the shipping skid. The bolts are located on the lower supporting side
rails and are exposed by opening the access door(s). Remove the bolts.

Raise the leveling feet above the level of the roll-around casters.

Use wood blocks and planks to form a ramp from the skid to the floor and carefully roll the
cabinet onto the floor.

Roll the system to the proper location for installation.

2.2.2 TMBll Unpacking
Before unpacking the TMBll Controller, check the shipping list to ensure that the correct number of
packages has been received. Check the shipping list for the correct TMBll module types. Carefully
remove each device from its shipping carton.
2.3 INSPECTION
After removing the equipment from its container(s), inspect it and report any damage to the responsible shipper and the local DIGITAL Sales Office. Inspect as follows:
1.

Inspect all switches, indicators, and panels for damage.

Remove equipment covers where necessary and inspect for loose or broken modules, blower
or fan damage, and loose nuts, bolts, screws, etc.

Inspect the wiring side of logic panels for bent pins, broken wires, loose external components, and foreign material.

Check the TUlOW Transport(s) for any foreign material that may have lodged in the reel
hubs or other moving parts.

Check the TUIOW power supply for proper seating of fuses and power connectors.

Inspect each TMBll module for shipping damage.

2.4 TUIOW CABINET INSTALLATION
To install the TUlOW cabinet, proceed as follows:
1.

Lower the leveling feet so that the cabinet is resting on the floor, not on the roll-around
casters.

Use a spirit level to level the cabinet; ensure that all leveling feet are firmly on the floor.

Remove the shipping screws that secure the equipment to the cabinet.

If two or more cabinets are to be bolted together, install filler strips (P IN H952-G) between
the cabinets as shown in Figure 2-2. Tighten the bolts that secure the cabinet groups together
and then recheck that the cabinets are level.

2-3

71 7/16

FILLER STRIPS
NOTE:
ALL DIMENSIONS IN INCHES

Figure 2-2

Installation of Filler Strips

Remove the plastic shipping pin from the top of the cabinet rear access door.

Ensure that the TUlOW cabinet and the cabinet that contains the TMBII are tied to the
same ground or install a ground strap between the cabinets.

After the TUlOW has been positioned per the site plan, open the TUlOW front door and
unscrew the two service locks located in the upper left and lower right corners of the transport front panel (Figure 1-4a).

Loosen the two shipping brackets that secure the transport to the rear of the cabinet frame.
Slide the brackets toward the center of the cruciform as shown in Figure 2-3, and tighten.
NOTE
Do not remove the shipping brackets. If the TU! OW
is to be reshipped or installed in a new location, the
shipping brackets must be repositioned over the vertical members and tightened.

If necessary, clean all outer surfaces.

2-4

H950 CABINET
RTICAL MOUNTING
MEMBER

TRANSPORT
CRUCIFORM

SHIPPING BRACKETS (2)
(IN STORED POSITION)

CABLE STRAIN
RELIEF
8209-9A

Figure 2-3

Transport Hold-Down Shipping Brackets

2-5

2.5

TMBll INSTALLATION jCABLING

Ensure that power is removed from the PDP-I 1.

2.5.1

System Unit Installation
I.

Extend the expander box on its slides and remove the module access cover. (Extended
BA 11 K and BA 11 F boxes are shown in Figure 1-2.)

Install a TMBII system unit into the expander box using the two captive screws (Figure 24) .

0
AC
LO

DC
LO

TMB11BACKPLANE
POWER TERMINALS

+5V

0
GND

CAPTIVE
SCREW

OPTION POWER
HARNESS 70·09559

TMB11
SYSTEM UNIT

CAPTIVE
SCREW
8209-3

Figure 2-4

Expander Box Backplane (BAIIF box shown)

2-6

Install the option power harness by connecting the Faston connectors to the system unit
backplane and the harness plug(s) to the expander box (Figure 2-5).

Dress the option power harness along the top of the BAIIF expander box as shown in
Figure 2-5. If a BA 11 K box is used, dress the harness under the expander box.

OPTION
POWER HARNESS

OPTION POWER
HARNESS PLUGS

70·09559

8209·2

Figure 2-5

Power Cabling of TMBII System Unit in BAIIF Box

2-7

2.5.2

Module Installation
1.

Check the jumpers on the M7821 module for a bus interrupt address of 224.

Check the priority jumper on the M7912 module for the correct interrupt priority level
(usually DRS).

Check the jumpers on the M105 module for the correct address range for the TMB 11 registers (772520 to 772536).

Plug the six TMBII modules into the system unit according to Figures 2-6 and 2-7 and
engineering drawing BD-TMBI1-0-7.

2.5.3 Unibus Cabling
System units are connected to the Unibus in daisy-chain fashion as shown in Figure 2-8. Each unit has
a Unibus-in and a Unibus-out jack. A BCllA cable connects the Unibus into the first system unit.
M920 jumper modules connect the Unibus to the other system units in a given configuration. An M930
terminator module is installed in the Unibus-out jack of the last system unit in the chain. If the Unibus
is to be carried onto another expander box, a BClIA Unibus cable is used to connect the Unibus from
the Unibus-out connector of the last system unit in the first box to the Unibus-in connector of the first
system unit in the second box. The Unibus is terminated by an M930 module installed in the out jack
of the last system unit.
Install the Unibus-in cable, Unibus-out cable, M920 jumper, and/or M930 terminator according to
the particular configuration. The Unibus-in connections on the TMBll system unit are slots Al and
B 1. The Unibus-out connections are slots A4 and B4 (Figure 2-9 and engineering drawing BDTMBll-0-7). The configuration shown in Figure 2-6 utilizes a Unibus-out cable and an M920 to bring
the Unibus in from the preceding system unit. The configuration shown in Figure 2-7 uses an M920
jumper for the input and an M930 for the output to terminate the Unibus.
NOTE
BCnA cable connectors will plug into the system
units either way but will not fully seat if incorrectly
installed. Make sure the connectors are fully seated
and that the notches on the connector edges are up
against the system unit slots.
2.5.4 ControBler /Master Drive Cabling
Connect the BCllA master bus cable to slots E4 and F4 on the system unit (Figure 2-9). Install an
M930 terminator module into slots E3 and F3 to terminate the master bus cable (Figures 2-6 and 2-7
and engineering drawing BD-TMBI1-0-7).

2-8

!!!!!!!!!!!!!!!!!!!!!~_CABLE STRAIN
RELIEF

M7821

M920

M796

M105
M795

BC11A MASTER BUS
CABLE TO TAPE
TRANSPORT
M930 MASTER
BUS TERMINATOR
M7912
M7911

7941-5

Figure 2-6

TMBll Module Location and Cabling in BAliK Box

2-9

M7912
M7821

M795

M920

M796

M930 (UNIBUS TERMINATOR)

BC11A (MASTER BUS
TO TAPE TRANSPORT)

M791 1

M930 (MASTER BUS
TERMINATOR)

M105

Figure 2-7 TMBll Module Location and Cabling in BAllF Box

2-10

8209-6

M930
UNIBUS
TERMINATOR
MODULE

BCtt A
UNIBUS
CABLE

11-4121

Figure 2-8

Unibus Cabling

2-11

A4
UNIBUS (
OUT

A1 )

UNIBUS
IN

--..;~-

TAPE
TRANSPORT
I/O

{(:~T

SHOWN)

F4 ---=--:1

7941-1

Figure 2-9

TMBII Mounted in System Unit

2.5.5 Securing Cables
I f the installation is performed in a BA II F expander box, lift the cable trough cover and feed the
BC IIA cable(s) through the trough and the cable holding bracket.
If the installation is performed in a BAliK expander box, perform the following:

2.6

Remove one screw from the center strain relief and loosen the other (Figure 2-6).

Swing the strain relief out and place the BC II A cable(s) up against the edge of the chassis.

Swing the strain relief back into place.

Insert the removed screw and tighten both screws.

TUIOW CABLING FOR A ONE-DRIVE SYSTEM
I.

Slide the TU lOW Master Transport out of the cabinet.

Remove the M8926 Interface board from the transport system unit assembly.

Install H851 edge connectors on the J and K jacks of the M8926 board (Figure 2-10).

2-12

H8800
TERMINATOR (3)

H851 EDGE
CONNECTORS

)

t/@ ,

(I ,

Figure 2-10

PINA

8110-5

M8926 with H85l Edge Connectors and H8800 Terminators

Install three H8800 terminators into jacks 11, 12, and 13 as shown in Figure 2-10.

Feed the BCllA master bus cable from the TMBII through the slot between the logic
system unit and the sheet metal chassis (Figure 2-11).

Position the M8926 board in its approximate location as shown in Figure 2-11, and connect
the BC IIA master bus cable to the H85l edge connectors on the M8926.

Insert the M8926 board into the system unit.

Plug the 861 power cord into a power receptacle.

2-13

H851 EDGE
CONNECTORS

M8926 (PARTIALLY REMOVED)

COLORED
STRIPE

BC11A MASTER BUS
CABLE FROM
FORMATTER

COLORED STRIPE
CABLES TO
TAPE TRANSPORT
8209-10

Figure 2-11

M8926 Cabling

2- 14

2.7

Set the 861 circuit breaker to the ON position.

10.

Slide the TU lOW Transport back into the cabinet.

TUIOW CABLING FOR. A MULTIDRIVE SYSTEM
l.

Slide the TU lOW Master Transport out of the cabinet.

Remove the M8926 Interface board from the transport system unit assembly.

Install H851 edge connectors on the J and K jacks of the M8926 board (Figure 2-10).

Feed the BCllA master bus cable from the TMBII through the slot between the logic
system unit and the sheet metal chassis (Figure 2-11).

Route three BC06R slave bus cables through the same slot used in step 5 but from
underneath.

Position the M8926 board in its approximate location as shown in Figure 2-11, and connect
the BC IlA master bus cable to the H851 edge connectors on the M8926.

Connect the three BC06R slave cables to Jl, J2, and J3 on the M8926 board. Connect the 11
and J2 cables so that the rough side is down against the board and the colored stripe is up.
Connect the J3 cable so that the rough side is down against the board and the colored stripe
is out. Because the 11 and J2 cables are folded back, the rough sides are visible in Figure 211. The J3 cable is not folded back, and hence the smooth side is visible.
NOTE
It is important to observe the rough side/smooth side
and colored stripe orientation in step 7. The plugs on
the BC06R slave cables are not keyed and can be
incorrectly inserted.

Mark the BC06R slave cables.

Insert the M8926 board into the system unit.

10. Secure the slave cables with the cable strain relief located below the transformer/capacitor
assembly (Figure 2-3).

11. Slide the TU 10W slave transport out of the cabinet.
12.

Remove M9001, M8913, and M9001-YA from the slave transport system unit (Figure 2-12).

l3.

Route the three BC06R slave bus cables up through the slot between the logic system unit
and the sheet metal chassis.

2-15

2
M8926

G056

M8910

M9001

4
G056

- - - i- -

- i- - -

- i-

-- -

- ~ -- - ~ -- - i- -

- --

- i-

-- -

M8913

M8911
(M8911-YA
NOTE 11

- -- - i - - -I- - - - i - - - D

- - - f.-

-- - I- - - - I - -- -

- -r-

M9001-YA

M8912
(NOTE 21

I-

- - - I-

-- - I - -- - I- -

I-

- - I- -

- I-

-- - I - - - -

B. SLAVE DRIVE

A. MASTER DRIVE
NOTES:
1. M8911 ~ 9 track drives; M8911- YA ~ 7 track drive

2. M8912 must be in the ElF position for on·line operation.
In the off-line mode it can be used in position A/B as an
off-I ine exerciser.
11-4784

Figure 2-12

TUlOW System Unit Module Location,
Viewed from Backplane

2-16

14. Position the M9001-Y A module in its approximate location and connect the BC06R cable
from M8926-B to input jack 12 on M9001-Y A. Follow the rough side/smooth side and
colored stripe orientation of Figure 2-13.
15. If this is a 2-drive system, install an H8800 terminator in the M9001-Y A output jack (11). If
another drive is to be cabled up, connect a BC06R slave bus cable to output jack 11 in
accordance with Figure 2-13 and mark the cable.
16. Insert M9001-YA into the system unit.
17. Repeat steps 14, 15, and 16 to connect M8926-J2 to card M8913, and M8926-11 to card
M9001.
18. If the system contains more than two drives, install BC06R cables in daisy-chain fashion
from one drive to the other, observing the colored stripe and smooth side/rough side orientation shown in Figure 2-13. The smooth side/rough side orientation for the slave drive
cable cards is: smooth side against the board for input cable to J2 and rough side against the
board- for output cable from 11. Install H8800 terminators in the M9001, M8913, and
M9001-Y A output jacks of the last drive in the chain.
19. Plug the 861 power cords into a power receptacle.
20. Set the 861 circuit breakers to the ON position.
21. Slide the TV lOW Transports back into the cabinet.
2.8 ACCEPTANCE TESTING
Refer to Acceptance Procedure, Engineering Drawing No. A-SP-TVlOW-0-3, for the acceptance test
procedures for the TMBll/TVlOW Tape Drive System.

2-17

H8800
TERMINATORS

-----

LAST SLAVE DRIVE

H85l EDGE
CONNECTORS

~T7L;V~V-E- - ,

MASTER DRIVE
UNIBUS OUT.

IV
I

I
I
I
I
I
I
I
I
I
I

UNIBUS IN.
BCllA CABLE OR
M920 JUMPER

M8926
(SIDE 11

er-

MASTER

BUS
CABLE
BCllA

(j)i

STRIPE

SLAVE
CABLE
COLORED
STRIPE

BC06R

COLORED
STRIPE

SLAVE
CABLE

L ___

M930 TERMINATOR

BC06R

COLORED
STRIPE

SMOOTH SIDE UP

I
L

I
I
I
I
I

-.J
114797

Figure 2-13

TMB11/TUlOW Master/TUlOW Slave Cabling Diagram

CHAPTER 3
SYSTEM OPERATING INSTRUCTIONS

3.1 CONTROLS AND INDICATORS
The operator control box (Figure 3-1) is located at the left of the file reel. The functions of the control
box switches and indicators are listed in Tables 3-1 and 3-2.

START

o D
STOP
FWD

OFF-LINE
LOAD

~ REW
UNIT
SELECT
REV

BR REL

10-1267

Figure 3-1

Operator Control Box

3.2 OPERA TING PROCEDURES
3.2.1 Application of Power
If the 861 Power Controller REMOTE ON/OFF/LOCAL ON switch is in the REMOTE ON position, TUlOW power is controlled by the processor POWER key switch. This method is used in normal
operation.

3-1

Table 3-1
Switch
LOAD/BR REL
LOAD position

TUI0W Control Box Switches

Function
Enables vacuum motor and pulses reel motors which draw tape
into the buffer columns.

Center position

Disables vacuum motor; brakes are full on.

BR REL position

Releases brakes.

ON-LINE/OFF-LINE
ON-LINE position

Selects remote operation

OFF-LINE position

Selects local operation.

FWD /REW /REV
FWD position

Selects, but does not initiate, forward tape motion when transport is off-line.

REW position

Selects, but does not initiate, tape rewind when transport is offline.

REV position

Selects, but does not initiate, reverse tape motion when transport is off-line.

START/STOP
STAR T position
STOP position
UNIT SELECT
(plug activated)

Initiates tape motion selected by FWD /REW /REV switch
when transport is off-line.
Clears any motion commands when transport is off-line.
Selects the tape transport unit by number (0-7); this number is
used in the program to address the tape transport (slave
address).

3-2

Table 3-2

Status Indicators

Indicator

Function

PWR

Indicates power has been applied to the transport.

LOAD

Indicates the vacuum is on and the tape is loaded into the buffer columns.

RDY

Indicates that the tape transport is ready and on-line (vacuum on and settledown delay complete); no tape motion.

LD PT

Indicates that the tape is at load point (beginning-of-tape, BOT).

END PT

Indicates that the tape is at end point (end-of-tape, EOT).

FILE PROT

Indicates that write operations are inhibited because the write enable ring is
not mounted on the file reel.

OFF-LINE

Indicates local operation by the control box.

SEL

Indicates the tape transport is selected by the controller (program).

WRT

Indicates that a write operation is in progress.

FWD

Indicates that a forward command is in progress.

REV

Indicates that a reverse command is in progress.

REW

Indicates that a rewind command is in progress.

If the processor POWER key switch is not activated, TUlOW power may be turned on locally by
setting the 861 Power Controller REMOTE ON/OFF/LOCAL ON switch to LOCAL ON. This
method may be used during maintenance.
3.2.2 Loading and Threading Tape
Use the following procedure to mount and thread magnetic tape.
1.

Place the ON-LINE/OFF-LINE switch in OFF-LINE position. Apply power to the transport. Place the LOAD/BR REL switch to the center position.

Place a write enable ring in the tape reel groove if data is to be written on the tape. Ensure
that there is no ring in the groove if data on the tape is not to be erased or written over.

Mount the file reel onto the lower hub, with the groove facing the back (away from the
operator). Ensure that the reel is firmly seated against the flange of the hub and that the reel
hub is securely tightened by hand. To tighten the reel hub, turn it clockwise. Do not grip the
reel by the outer flanges. Ensure that brakes are on while tightening the hub.

3-3

Install the take-up reel (at the top) using the same procedure used in step 3.

Place the LOAD /BR REL switch in the BR REL position.

Manually unwind tape from the file reel and thread the tape by the tape guides and head
assembly as shown in Figure 3-2.

TAKE-UP REEL
(UPPER MOTOR)

TAPE GUIDES (2)

CAPSTAN

0
TAPE MOVES INTO BOTH
VACUUM COLUMNS
WHEN "LOAD" SWITCH
IS PRESSED

HEAD TAPE GUIDES (2)

.......

~'---

R/W ERASE
HEAD ASSEMBLY

I
I
I

, _....

I
I

I 0

I
0

I
I

TAPE PATH
WHEN LOADING

,_/ I
o
o

FILE REEL
(LOWER MOTOR)
to-t308

Figure 3-2 Tape Loading Path

3-4

Wind about four turns of tape onto the take-up reel. Ensure that the tape is in the guides.
CAUTION
Wind tape flat onto the take-up reel. Do not bend
tape back or place tape end outside of reel (out the
window). While winding tape on the take-up reel,
simultaneously unwind the file reel to relieve tension
on the tape. Rotate the reels gently. Do not jerk the
tape as this could cause the tape to stretch.

Place the LOADjBR REL switch in the LOAD position to draw tape into the vacuum
columns.

Select FWD and press START to advance the tape to the load point. When the BOT marker
is sensed, tape motion stops, the FWD indicator goes out, and the LD PT indicator comes
on.
NOTE
If tape motion continues for more than 10 seconds, it
is possible that originally too much tape was wound
by hand onto the take-up reel, passing the BOT
marker. If this happens, press STOP, select REV
(reverse), and press START. The tape should move
to the BOT marker (load point) and stop.

3.2.3 Unloading Tape
Different procedures are used to unload tapes, depending on whether or not the tape is at BOT.
Unloading Tape at BOT - To unload a tape which is at the BOT marker, perform the following
procedure:
1.

Place the LOAD jBR REL switch in the BR REL position to release the brakes.

Gently hand wind the file reel (lower) in a counterclockwise direction until all of the tape is
wound onto the reel.
CAUTION
While winding tape on the file reel, simultaneously
unwind the take-up reel to relieve tension on the tape.
Rotate the reels gently. Do not jerk the tape as this
could cause the tape to stretch.

Remove the file reel from the hub assembly. Turn the hub counterclockwise to loosen it.

3-5

Unloading Tape Not at BOT - To unload a tape which is not at the BOT marker, perform the following
procedure:
1.

Place the ON-LINE/OFF-LINE switch in the OFF-LINE position.

Press STOP; select REW.

Press START. The tape should rewind until the BOT marker is reached.

Place the LOAD /BR REL switch in the BR REL position to release the brakes.

Gently hand wind the file (lower) reel in a counterclockwise direction until all of the tape is
wound onto the reel.
CAUTION
While winding tape on the file reel, simultaneously
unwind the take-up reel to relieve tension on the tape.
Rotate the reels gently. Do not jerk the tape as this
could cause the tape to stretch.

Remove the file reel from the hub assembly. Turn the hub counterclockwise to loosen it.

3.2.4 Restart After Power Failure
In the event of a power failure, the TV lOW automatically shuts down and tape motion stops without
physical damage to the tape. However, if the TV lOW was on-line and was either reading or writing at
the time of the power failure, the last record was probably lost; refer to system recovery procedures
documentation if this happens. To restart the transport, proceed as follows.
NOTE
Return of power is indicated when the PWR
indicator lights.
1.

Set the ON-LINE/OFF-LINE switch to OFF-LINE.

Place the LOAD/BR REL switch in the BR REL position to release the brakes.

Manually wind the reels to take up any slack in the tape.

Set the LOAD /BR REL switch to the LOAD position to draw tape back into vacuum
columns.

Set the ON-LINE/OFF-LINE switch to the desired position.

3.2.5 Restart After Fail-Safe
If the tape loop in either buffer column exceeds the limit shown in Figure 3-3, the vacuum system
automatically shuts down and tape motion stops without damage to the tape. When this fail-safe
condition occurs, the TV lOW does not respond to either on-line or off-line commands. To restart the
transport, refer to Paragraph 3.2.4.

3-6

SHORT LOOP
(TRANSPORT
WILL SHUTDOWN l

VACUUM
SWITCHES

BUFFER
COLUMN

LONG LOOP
(TRANSPORT
WILL SHUTDOWN)

10-1268

Figure 3-3

Fail-Safe Limits

3.3 OPERATOR TROUBLESHOOTING
Before calling maintenance personnel to correct a problem, the operator can make several checks with
minimal effort. These steps may isolate an easily correctable error:
1.

Ensure that the vacuum door (Figure 1-4) is closed and sealed properly.

If the tape does not stop at BOT, be certain the tape has a BOT marker.

Ensure that the write enable ring is inserted in the tape reel if a write operation is to be
performed.

Clean the tape path according to the daily (8-hour) preventive maintenance procedures in
Chapter 4.

3-7

CHAPTER 4
CUSTOMER CARE
AND PREVENTIVE MAINTENANCE

4.1 CUSTOMER RESPONSIBILITIES
The customer is directly responsible for:
1.

Obtaining operating supplies, including disk cartriges, disk packs and filters, magnetic tape,
DECtape, paper tape, cassettes, printer paper, printer ribbons, plotter paper, etc.

Supplying accessories, including disk storage racks, DECtape storage racks, carrying cases
for disk cartridges and DECtape, cabinetry, tables, and chairs.
NOTE
Users of Digital Equipment Corporation equipment
may obtain the proper operating supplies and accessories by contacting:
Digital Equipment Corporation
DEC Supplies Order Processing
146 Main Street
Maynard, Massachusetts 01754
Phone: (617) 897-5111, Ext. 5218, 5907
Boston Area: (617) 890-0330
TWX: 710-347-0212
Cable: Digital Mayn
Telex: 94-8457

Maintaining the required logs and report files consistently and accurately.

Making the necessary documentation available in a location convenient to the system.

Keeping the exterior of the system and the surrounding area clean.

Turning off the teletypewriter and! or line printer when these devices are not in use.

Ensuring that ac plugs are securely plugged in each time equipment is used.

Performing the specific equipment care operations described in Paragraphs 4.2 and 4.3 at
the suggested frequencies or more often if usage and environment warrant.

4-1

4.2

4.3

CARE OF MAGNETIC TAPE
1.

Do not expose magnetic tape to excessive heat or dust. Most tape read errors are caused by
dust or dirt on the read head; it is imperative that the tape be kept clean.

Always store tape reels inside containers when not in use; keep the empty containers tightly
closed to keep out dust and dirt.

Never touch the portion of tape between the BOT and EOT markers; oil from fingers
attracts dust and dirt.

Never use a contaminated reel of tape; this will spread dirt to clean tape reels and could have
an adverse effect on tape transport reliability.

Always handle tape reels by the hub hole; squeezing the reel flanges could lead to tape edge
damage in winding or unwinding tapes.

Do not smoke near the tape transport or storage area; tobacco smoke and ashes are especially damaging to tapes.

Do not place magnetic tape near any line printer or other device that produces paper dust.

Do not place magnetic tape on top of the tape transport, or in any other location where it
might be affected by hot air.

Do not store magnetic tape in the vicinity of electric motors.

CUSTOMER PREVENTIVE MAINTENANCE OF TUI0W TAPE TRANSPORT

4.3.1 General
Digital Equipment Corporation tape transports are highly reliable precision instruments that will
provide years of trouble-free performance when properly maintained. A planned program of routine
inspection and maintenance is essential for optimum performance and reliability. The following information will assist the customer in caring for his equipment and ensure the highest level of performance
and reliability.
4.3.2 Preventive Maintenance
To ensure trouble-free operation, a preventive maintenance schedule should be kept. Preventive
maintenance consists of cleaning only a few items, but the cleanliness of these items is very important
to proper tape transport operation. The frequency of performance will vary somewhat with the environment and degree of use of the transport. Therefore, a rigid schedule applying to all machines is
difficult to define. Daily cleaning is recommended for units in constant operation in ordinary environments. This schedule should be modified if experience shows other periods are more suitable. Paragraph 4.3.4 contains the cleaning instructions.

Before performing any cleaning operation, remove the file reel and store it properly. All items in the
tape path should be cleaned on a daily basis. In cleaning, it is important to be thorough yet gentle and
to avoid certain dangerous practices. It should be remembered that some tape cleaners are strong
cleaning agents and should not come in contact with painted surfaces or plastic.
CAUTION
Do not use acetone or lacquer thinner, rubbing alcohol, or excessive deaner. Be extremely careful not to
aiiow the cleaner to penetrate ball bearings and
motors.
4-2

4.3.3 Magnetic Tape Drive Cleaning Kit
A magnetic tape drive cleaning kit has been carefully configured to provide cleaning materials that will
not harm tape equipment and will not leave any residue behind to interfere with data reliability. The
hints contained in the following few paragraphs will ensure that the very best results possible will be
obtained from the kit.
The Freon® TFl13 cleaning fluid in this kit is one of the safest and best degreasing agents available. It
will not adversely affect any part of DIGITAL's tape equipment. To prepare the can of fluid for
service, unscrew the top and punch a small hole in the metal seal covering the pour spout.
WARNING
TF113 is a non-restricted, non-hazardous substance.
However, when using TFl13, avoid excessive skin
contact, do not allow TFl13 to come in contact with
the eyes, and do not swallow it. Use TF113 only in a
well ventilated area.
When cleaning tape equipment, never dip a contaminated cleaning swab or wipe into the can. To
transfer fluid onto the swab, pour a little out into the screw cap and dip the swab into the cap. Discard
the remaining fluid in the cap when the cleaning operation is complete.
Always keep the can of fluid tightly closed when not in use, because Freon TFl13 evaporates rapidly
when exposed to air.
Use the cleaning materials contained in the kit to clean tape heads, tape guides, the tape cleaner, reel
hubs and any part of the drive where a dirty residue could ultimately come in contact with tape. To
clean other parts of the drive, such as the exterior surfaces of doors or the friction pads of brakes, use
any reasonable clean, lint-free material with or without cleaning fluid.
NOTE
If you encounter an unusually stubborn dirt deposit
that appears to resist TFl13, try a mild soap and
water solution to dislodge it. After using soap, be
sure to wash down the affected area thoroughly with
TF113 to remove soapy residues.
Cleaning the TU10W DECmagtape Drive

4.3.4
1.

Dismount the tape from the unit.

Clean the following components of the drive using a foam-tipped swab soaked in cleaning
fluid (Figure 4-1):
a.
b.
c.
d.
e.

Read/write head (Location A)
Erase head (Location B)
Tape cleaner (Location C)
Upper roller guide (Location D)
Lower roller guide (Location E)
NOTE
Be careful to keep cleaning fluid only on the tapebearing surface of roller guides to prevent degreasing
the roller guide bearings.

®Freon is a registered trademark of Dow Chemical Co.

4-3

o
E

..
...

F
11 - 3357

Figure 4-1

Location of Read/Write and Erase Heads and Tape Cleaner

When cleaning the head area, avoid the spring-loaded ceramic washers on the tape drive
assemblies. If it appears necessary to run the swab over the tape bearing surface of these
guides to remove oxide deposits, do so; however, when cleaning is complete, be sure that the
washer is pressed snugly up against the tape guide surface and not "hung up" on its shaft
(Figure 4-2).

Next, clean the vacuum pockets (F) and the inner surface of the vacuum door (G) using a
lint-free wipe and cleaning fluid. Pass another lint-free wipe over the head using a polishing
action to remove any remaining deposits.

CERAMIC
WASHER

HEAD
PLATE
NOT THIS

THIS

11- 4120

Figure 4-2

Proper Ceramic Washer Positioning
4-4

CHAPTER 5

SYSTEM MAINTENANCE

5. 1 SCOPE
This chapter provides a complete description of TM B 11 ITU lOW preventive and corrective maintenance procedures. The major TUI0W assemblies referenced throughout this chapter are shown in
Figure 5-1. Access to the interior components of the TUI0W is gained by rotating the service locks on
the upper left and lower right sides of the TU lOW to release the unit from the cabinet (Figure 5-2).

TRANSPORT
SERVICE - - _ - '
LOCK
CAPSTAN -~->----,*~.

TAPE CLEANER
HEAD PLATE ASSEMBL
(COVER REMOVEDI

EOT/ BOT
ASSEMBLY

TRANSPORT
SERVICE
LOCK

CONTROL PANEL-"-+''''---

766Q..22-A0580

a. Front View
Figure 5-1

TU lOW Tape Transport Assemblies (Sheet 1 of 2)

5-1

BRAKE ASSEMBLY

AIR FILTER

TACHOMETER

MOTOR
H606 POWER BOAR

LOGIC BACKPLANE
ASSEMBLY

TAKE-UP REEL MOTOR

VACUUM SWITCHES

POWER 5yPPLY
REGULATOR BOARD

FILE REEL MOTOR

VACUUM SWITCHES

TRANSFORMER -CAPACITO
ASSEMBLY

VACUUM HOSE
(TO VACUUM MOTOR)

READ/WRITE
INTERLOCK
BRAKE ASSEMBLY

AIR FILTER

8209-5

b _ Left Side View

Figure 5-1

TUIOW Tape Transport Assemblies (Sheet 2 of 2)

5-2

SERVICE

LOCK

DOOR_--i::-'
SEAL

SERVICE

LOCK

6999-11

Figure 5-2

Transport Casting, Front View

5.2 TMBlljTVlOW MAINTENANCE PHILOSOPHY
The TM B II JTV I OW DECmagtape System is a highly reliable system that will provide years of
trouble-free performance when it is properly maintained . A planned program of routine inspection
and maintenance is essential for optimum performance and reliability.
The preventive maintenance required on the TMB 11 differs from that required on the TU lOW Transport. The TMB II Controller and the M8926 Interface module are total solid-state units with no
moving parts; therefore, no preventive maintenance is required on these units. The TU lOW Transport,
however, requires daily customer care, consisting of head and tape path cleaning. (Refer to Paragraph
4.3.) Otherwise, the transport requires few adjustments, which should not be performed unless problems are encountered in transport operation . Refer to Paragraph 5.4 for the recommended preventive
maintenance procedures.
Corrective maintenance consists of troubleshooting at the system level (using system diagnostics and
visual methods) to localize the failure to a particular unit, whether it is the TMBII Controller, M8926
I nterface, or TU lOW Transport. Once a faulty unit is identified, unit level troubleshooting can be
performed using unit functional block diagrams, flow diagrams, timing diagrams, and engineering
logic diagrams to localize the failure to an electrical area (module) or a mechanical part. Then, when
the faulty module or mechanical part is located, it should be replaced.

5-3

5.3 TEST EQUIPMENT
Two categories of test equipment are required to maintain the TMBlljTUIOW: standard test equipment and special test equipment.
5.3.1 Standard Test Equipment
Maintenance procedures for the TMBl1jTUlOW require the standard test equipment and diagnostic
programs listed in Table 5-1, in addition to standard hand tools, cleaners, and test cables.
Table 5-1

Standard Test Equipment Required

Equipment

Manufacturer

Designation

M ultimeter

Triplett or Simpson

Model 630NA or 260

Oscilloscope

Tektronix

Type 453 or equivalent

XlO Probes (2)

Tektronix

P6008

Diagnostics (MAINDECS)**
(Use revision listed,
or a higher one.)

DIGITAL

Instruction Test
(MAINDEC-I1-DZTMA-*H)
Multidrive Data
Reliability Exerciser
(MAIND EC-l1-DZTM H-* E)
Drive Function Timer
(MAINDEC-I1-DZTME-*C)
Supplemental Instruction Test
(MAINDEC-I1-DZTMF-*D)
Utility Drive
(MAIND EC-l1-DZTM G-*C)

*Revision level
**Refer to Table 5-6 for a description of diagnostics.

5.3.2 Special Test Equipment
The special test equipment and tools required are listed in Table 5-2. Usage of the special tools and
equipment is also provided in the table.
5.4 PREVENTIVE MAINTENANCE
The TMBII Controller and M8926 Interface module are all electronic assemblies that require no
preventive maintenance. Care and preventive maintenance of the TU lOW to be performed by the user
are listed in Chapter 4. TU lOW preventive maintenance to be performed by the service technician is
provided in this section.
The recommended frequencies for performing the PM steps in this procedure are based on moderate
usage of the equipment. In cases where usage is heavy, certain steps should be performed more
frequently.
For example, in Paragraphs 5.4.2.1 and 5.4.2.7 through 5.4.2.13 of the quarterly procedure, assume
that tape motion will not exceed 150 hoursj quarter; if tape motion exceeds that figure, the steps should
be performed more often. (Tape motion = time spent actually moving tape; this time must be decreased by Ij2 if the software is not double-buffered, or if two drives exist on the same controller.)
5-4

The semiannual procedure assumes that tape motion will not exceed 300 hours during a 6-month
period; if tape motion exceeds that figure, these steps should be performed more frequently.

Table 5-2 Special Tools and Equipment and Their Use
Part No.

Item

2.
3.
4.
5.
6.
7.
8.
9.

10.
11.
12.
13.
14.
15.
16.

Skew Tape (800 bits/inch)
365.8 m (1200 ft)
182.9 m (600 ft)

29-19224
29-22020
29-18611
29-18607
29-20273
29-16871
29-10780
74-13969
29-22039

Reel Hub Tool
Roller Guide Tool
Microscope
Magna-See
Penlightt
Alignment Glass
Depth Micrometer
Shim Stock
0.001
0.002 (red)
0.003 (green)
0.004 (tan)
0.005 (blue)
0.0075 (transparent)
0.010 (brown)
TMBII/TUI0W Module Swap Kit
Feeler Gauge Set t
Allen Wrench Set
EOT/BOT Markers (Reflective Strips)

Usage *
2
1

X
X
X

X
X
X
X

48-50023-01
48-50023-03
48-50023-04
48-50023-05
48-50023-06
48-50023-07
48-50023-08

X
X
X
X
X
X
X

29-13515

90-09177

Deleted
Vacuum Belt Tension Gauge
Capstan Alignment Tool

29-22265
29-18609

*Usage Legend:
1. Routine Corrective Maintenance
2. Monthly PM
3. Quarterly PM
4. Semiannual PM
5. Major Tape Path Alignment
t Contained in standard tool kit.

5-5

X
X

5.4.1 Monthly PM Schedule
The items listed in this section are to be performed on a monthly basis:

S.4.Ll

Tape Path Cleaning and Inspection - Clean the tape path and inspect it for wear as follows:

Turn power off in the 861 power controller. Remove and clean the take-up reel, using a
Kimwipe dampened with water; inspect the take-up reel for cracks or loose center ring (hub
interface). Replace if defective.

Remove the supply reel (if installed). Using water-dampened Kimwipes, clean the deckplate
surfaces and front door.
CAUTION
Be careful not to saturate the fiberglass lining on the
vacuum column walls with fluid; this could cause
damage to the lining.

Remove the head cover and open the vacuum door.

U sing a penlight, inspect the read/write head and erase head for oxide accumulation. A
worn head will normally show oxide accumulation on the worn spot. If the read/write head
is unevenly worn or if the erase head shows any wear, replace the head plate assembly.
(Refer to Figure 5-3 shiny spots indicate uneven wear.)

WEAR SPOT ON
ONE SIDE

READ/WRITE
HEAD

r.......n;

I~I
EVEN

ERASE
HEAD
CP-1997

WEAR

CP - 199B

Figure 5-3

CP- 1999

Examples of Unacceptable Head Assembly Wear

5-6

U sing Freon TFl13 and cotton-tipped wooden swabs, clean any accumulated oxide from
the read/write head, erase head, tape cleaner, and fixed guides. (Pay particular attention to
removing oxide buildup from ceramic surfaces of the fixed guides.)
NOTE
Ensure that the inner (spring-loaded) guides move
freely after cleaning and that they are not jammed
under the fixed guides.

Clean vacuum columns and vacuum column doors with Freon TFl13 and Kimwipes. Clean
roller guides with cotton swabs and Freon TF113.

NOTE
Wear spots of any kind on the erase head are
unacceptable.
5.4.1.2
5-4).

Reel Hub Inspection and Lubrication - Lubricate and inspect the reel hubs as follows (Figure

PRESSURE PLATE

PLASTIC DISK

STOP PINS

KNOB
TEFLON

WASHER

COMPRESSION RING
10-1000

Figure 5-4

Hub Composition

5-7

Lubricate the upper and lower reel hub compression rings by applying silicon grease generously and rubbing it in. Wipe away excess with Kimwipe.

Place the take-up reel on the lower hub. Turn the hub lock until it hits the stop pin (PN 9006527). Hold the hub with one hand and attempt to turn the reel counterclockwise with the
other hand.

If the hub lock does not hit the stop when tightened, or if the reel turns while the hub is being
held stationary, readjust the hub pin and replace the compression ring according to the
following procedure.

Remove power from the TU lOW Tape Transport and remove the tape reel.

Carefully snap out the plastic disk (PN 12-09212-00) from the reel hub.

Mark the position of the center roll pin (PN 90-06526) in the hub guide.

Using a pair of heavy duty diagonal pliers, carefully remove the center roll pin.

Grasp the reel hub and unscrew the knob from the hub.

Remove (in order) the Teflon washer, pressure plate, and rubber compression ring.

Lightly lubricate the flat surfaces of a new compression ring with silicon grease. Wipe
all excess grease from the ring with a lint-free cloth.

Install (in order) the new compression ring, pressure plate, and Teflon washer.

Lightly tighten the knob on the hub until the compression ring is compressed and fully
seated.

Loosen the knob until it is free of the Teflon washer. Then gently screw it in until it just
touches the washer.

Reinstall the roll pin in the same hole from which it was removed (Step d).

Turn the knob counterclockwise until the roll pin makes contact with one of the two
hub stop pins.

Try to install a tape reel on the hub. If the tape reel does not easily slip on the hub,
move the stop pin back one hole at a time until the knob can be released far enough to
permit the tape reel to slip on the hub.

With a tape reel installed, tighten the knob (clockwise) until the roll pin contacts the
other hub stop pin. If the tape reel is not secure, move the stop pin ahead until the knob
can be tightened correctly.

Place the take-up reel on the upper hub. Repeat the above procedure from Step 2 for the
upper hub take-up.

5-8

5.4.1.3 Operator Panel Check - Check the operator panel switches and indicators as follows.
(Replace switches and/or indicators as required.)
1.

Apply power to the 861 power controller; ensure that the OFF-LINE and PWR indicators
on the control panel are ON.

Place a scratch tape (with write ring) on the lower hub and secure the hub lock. Set the
LOAD /BR REL switch to LOAD and then back to BR REL. Ensure that both reels turn
freely and that the FILE PROT light does not light as the supply reel is rotated.

Thread the scratch tape through the tape path and make two wraps around the take-up reel.
Set the LOAD /BR REL switch to LOAD; ensure that the LOAD indicator on the control
panel comes on.

Place the FWD /REW /REY switch to FWD; place the START/STOP switch to STOP and
then back to START. Ensure that the FWD indicator is lit while the drive is moving the tape
toward BOT, and that the LD PT indicator lights when the drive stops at BOT.

Run the tape forward for approximately 30 seconds; set the START/STOP switch to STOP.

Set the FWD /REW /REY switch to REV; press START. Allow the tape to run in reverse
for approximately 10 seconds and ensure that the REV indicator is on. Place the
START/STOP switch in the STOP position.

Set the FWD/REW /REV switch to REW; press START. Ensure that the REW indicator is
on.

Set the ON-LINE/OFF-LINE switch to ON-LINE. When the drive has completed the
rewind operation in Step 7 check that the RDY indicator comes on. Check that the SEL
indicator also comes on if the controller is currently selecting this TV lOW.

Set the ON-LINE/OFF-LINE switch to OFF-LINE and the LOAD/BR REL switch to BR
REL. Dismount the tape and remove the write enable ring. Mount the tape and ensure that
the FILE PROT indicator is on. Rotate the reel; ensure that the FILE PROT indicator
remams on.
NOTE
If a quarterly PM procedure is scheduled, proceed to
Paragraph 5.4.2; if not? continue with Paragraph
5.4.1.4.

5-9

5.4.1.4 NRZ Diagnostic - Position tape at BOT; place the unit ON-LINE. Run the Multi-Drive Data
Reliability Exerciser (DZTMH) for 10 minutes of NRZ (800 bits/inch). If any soft errors occur, run a
complete pass again to determine whether the frequency of soft errors is within specifications; no hard
read errors are allowed.
NOTE
The acceptable soft error rate for one 731.6 m (2400foot) reel of tape is:
1.
2.

Read: 2
Write: 5

Retries on the same spot do not increase the soft
error tally, i.e., a read error on block 1, record 1 that
required three retries to recover is recorded as one
soft read error.
5.4.2 Quarterly PM Schedule
The items listed in this section are to be performed on a quarterly basis.
5.4.2.1
1.

Reel Motor Brakes/Vacuum System Belt
Disassemble, clean, and reassemble the reel motor brakes according to the following
procedure:
a.

With power off, pull the transport out on its slides. (Access brakes from the left side of
the transport; operation is identical for both reel motors.)

Loosen the Allen screw located on the clamp (Figure 5-5).

Remove the spring and brake assembly. Push a cotton swab through each of the inserts
(locating holes) that hold the rotor disk and rotor to ensure that they are securely held
in the rotor and that they do not protrude in such a way as to interfere with operation
of the rotor disk. If inserts are loose, replace the brake assembly.

Using a clean, dry, lint-free cloth or wipe, clean the following:
(1)

The brake surface of the stator. (Stator is still on motor.)

(2)

Both sides of the rotor disk, including location pins.

(3)

The face of the rotor next to the rotor disk.
NOTE
Avoid skin contact with brake surfaces; body oils are
detrimental to brake function.

Install the rotor disk into the rotor; select the mating combination that allows for
smoothest insertion and retraction of rotor disk pins into the rotor locating holes. Try
each of the 120-degree intervals for best fit.

5-10

-----..,

14----.010" CLEARANCE

>+--+-- SPRING

REEL MOTOR

~"'M'

MOTOR SHAFT

~--3/16" SPACER

------'

ROTOR
ROTOR DISC

11-4672

Figure 5-5

Reel Motor Brake Assembly

Replace the brake, leaving a clearance of 0.025 cm (0.010 inch) between the rotor disk
and the stator and a 0.475-cm (3f16-inch) clearance between the rotor and the clamp.
In this position, the clamp should be clamping on the splits cut into the sleeve of the
rotor, ensuring that the rotor is fastened securely to the reel motor shaft. When clearances are correct, tighten the Allen screw.

With the 0.025-cm (O.01O-inch) feeler gauge inserted between the stator and the rotor,4
rotate the reel motor manually from the front of the unit to see that the brake is spaced
uniformly all around. If necessary, rotate the brake at 120-degree intervals to determine
the best position for uniform separation. (An excessively high or low spot is cause for
replacing the brake assembly.)

Remount the rotor spring between the rotor disk and the rotor.

When the above steps have been completed for both reels, rotate both reels, feeling for
free rotation and listening to ensure that there is no squealing from stator frotor disk
contact.

5-11

With the power off, check for correct vacuum system belt tension as follows:
a.

Position the belt tension gauge as shown in Figure 5-6.

BELT TENSION GAUGE

KNOB

DR IVE PULLEY 50 Hz

MOTOR PLATE
TAKE-UP SCREW

DRIVE PULLEY 60 Hz

BLOWER PULLEY

CP-2119

Figure 5-6

504.2.2

Belt Tension Gauge

Push against the knob at the end of the spring until the third tab on the gauge just
touches the belt.

Read the tension from the scale just under the spring. If the reading is not between 2.25
and 3.6 kg (5 and 8 lb), adjust the belt tension adjustment screw for 2.25 kg (5 Ib).

Voltage Check Setup - Set up as follows to check voltages:

Turn power off; remove M8912 [Test Function Generator (TFG)] from slot EF3 and place
it on the module extender in slot AB3.

Place the SSRO, SSWRT, and WRT switches down; turn power on.
NOTE
In all voltage checks, refer to Figure 5-7 for the location of the potentiometers that control adjustments.
If any voltages cannot be adjusted to meet specifications, repair or replace the regulator boards.

5-12

07
~

R26(+12)~

(NRZ)

$. e

R37(+12)-@)

R44(-6.4)"'"@

R57
(+5)
(N/A)

-® .-=-_-,

GND

5-lLe \

R59@(+5.3)

AC HI

AC LO

/ 0 0 [] 0 [J

b 6 115 230 115

NOTES:
1) 1-5 represent 5 Phillips head screws.
2) 6

represent Allen screw-must be secured very tightly,or
damage to the power supply may
result.
11-4683

Figure 5-7

5.4.2.3

TV lOW Power Supply Regulator Board

+5 Vdc Check. (Drive Logic) - Check the +5 Vdc drive logic voltage:

Reference Point
Nominal Value

DOlA2 (red wire)
+5.25 ± 0.05 V

If adjustment is necessary, adjust potentiometer R59.
5.4.2.4

+ 12 Vdc Check (Drive Logic) - Check the +12 V dc drive voltage.

Reference Point
Nominal Value

A04Vl (yellow wire)
+12.05 Vdc ± 0.05 V

If adjustment is necessary, adjust potentiometer R37.
5.4.2.5

-6.4 V Check - Check the -6.4 V dc drive voltage.

Reference Point
Nominal Value

C04N2 (green wire)
-6.35 V dc ± 0.05 V

If adjustment is necessary, adjust potentiometer R44.

5.4.2.6

+12 Vdc Check (NRZ) - With S5-9 (M8912) on, check the +12 Vdc (NRZ) drive voltage:

Reference Point
Nominal Value

C02J2 (orange wire)
+11.875 Vdc ± 0.125 Vdc

If adjustment is necessary, adjust potentiometer R26.

NOTE
The remaining steps in this PM procedure require a
well-calibrated oscilloscope. It is advisable to check
the voltage and frequency calibration at this time,
with the probes intended for use.
5.4.2.7

Forward Tape Speed and DC Balance Check - Check forward tape speed and dc balance:

Turn power off; disconnect the erase head cable (the 2-pin connector located just below the
read/write head) and the write head cable (located directly above the erase head connector).

Turn power on; load a master skew tape and position it at BOT.

Set the vertical gain of the oscilloscope to 50 mV /cm.

Slowly adjust R21 (BAL) on the H606 power board to obtain 0.0 V ± 0.04 V at test point 2.
NOTE
50 mV of ac ripple will be displayed; center the ac
ripple on ground to obtain a 0 Vdc level.

Set the oscilloscope as follows:
10 IIs/cm
Channell
Triggering

2 V/cm
Normal
Negative slope
Channell triggered

Channel 1 probe to C4-Ul.
6.

Initiate FWD tape motion; check that negative pulses are 55--57 liS apart (Figure 5-8). If
not, adjust FWD potentiometer R 13 on H606 for 56 liS.

5-14

l..'

Figure 5-8

5.4.2.8

Tape Speed Check

Reverse Tape Speed Check - Initiate REV tape motion; check that negative pulses are 55-57

MS apart. If not, adjust REV potentiometer R12 on H606 for 56 j.LS.

5.4.2.9
1.

Forward Jitter Check - Check forward jitter as follows:
Change sweep to 20 j.Ls/cm; initiate FWD tape motion. Check that four negative pulses
appear on the oscilloscope screen (Figure 5-9).

,1-+-+-+--t---t+=--t--+--t---t----j
I

00····

................... .

....

...

BU-0615

Figure 5-9

Jitter Check

5-15

Use the horizontal X 10 magnifier to increase the horizontal display. Using the horizontal
position knob, place the third pulse in the center of the screen. Check that the jitter is less
than 6 f.1S (3 cm on the scope, as indicated in Figure 5-10). If jitter exceeds 6 f.1S (as in Figure
5-11), replace the capstan motor.
NOTE
If it is necessary to replace the capstan motor, tape
path alignment must be performed at the same time.

10' . .

. . . . . . ..

....

..'

l--+--+-+-------t----+----1~f---l--------1

Figure 5-10

Figure 5-11

Good Capstan Motor

Bad Capstan Motor

5.4.2.10 Reverse Jitter Check - Initiate REV tape motion; repeat the procedure outlined in Paragraph
5.2.4.9 to check reverse jitter. Remove the XIO horizontal magnification on the oscilloscope.
5.4.2.11
1.

Forward Skew Check - Perform mechanical skew (head azimuth) adjustment as follows:
Set up oscilloscope as follows:
1 f.1s/cm
Channell
Triggering

2V/cm
Normal
Positive slope
Channell triggered
Channell probe to E4Kl (PACKET H).
2.

Initiate FWD motion; synchronize the scope. Adjust the Phillips head screw on the head
plate for minimum PACKET width (must be less that 2.5 f.1s). (See Figures 5-12 and 5-13.)

5-16

100---+--+--1---+--+----+--+----1---+---

. . . . . .. . . . . . . . . . ..

Figure 5-12

Figure 5-13

........... .

PACKET Waveform

Adjusting Mechanical Skew
5-17

If adjustment cannot be made, tape path alignment must be performed at this time.

NOTE
An occasional jump in PACKET width of 1 }LS is usually allowable in the procedures listed in Paragraphs
5.4.2.11 and 5.4.2.12 (usually due to tape defect);
however, this should not occur more than once per
second.
5.4.2.12 Reverse Skew Check - Initiate REV tape motion; ensure that width is less than 3.5 }LS. (No
adjustment is possible; if PACKET width exceeds maximum, tape path alignment must be performed.)
Allow skew tape to continue in REV mode to BOT. (Do not rewind.) Remove skew tape. Connect
write and erase heads.
NOTE
If a semiannual PM procedure is scheduled, proceed

to Paragraph 5.4.3; if not, continue with Paragraph
5.4.2.13.
5.4.2.13
1.
2.
3.

Test Function Generator (TFG) Relocation - Relocate the TFG as follows:
Turn power off.
Remove the TFG from slot AB03 and plug it into slot EF03.
Turn power on.
NOTE
Return to Paragraph 5.4.1.4 of the monthly PM
procedures.

5.4.3 Semiannual PM Schedule
The items listed in this section are to be performed on a semiannual basis.
5.4.3.1

Forward Ramp Check - Adjust forward acceleration ramp as follows:

Connect the oscilloscope.

Set the switches of the Test Function Generator (TFG) module (M8912) as follows:
SSRD, SSWRT, and WRT: Down
S4-9: OFF

Load a scratch tape (with write ring installed) and position it at BOT.
a.

Place the probe from the external trigger to A3Sl.

Connect the Channell probe to PI-7 of the H606 module.

Connect the Channell ground to the GND test point on H606 (adjacent to P3-4).

Set the scope to external sync, negative slope, 2 ms/cm, with Channell to 0.2 V /cm (20
mV /cm if XIO probe is used).

Set FWD/REW fREV switch to FWD. Place the SSRD switch on TFG (M8912) up.
Observe a negative slope of 7-8 ms (Figure 5-14.) Adjust -CUR potentiometer on H606, if
necessary.
5-18

11--~--~--4---+---+---+---~--r-~--~
I

90· • ••

.•..

.••.

•.•.

.•••

•...

...•

.•••

....

• .••

•.••

•••.

••••

.•.•

• •••

10' . •.

••.•

•.••

••••

l'--+--+--+----+--t-----I----t---t---------t---l

Figure 5-14

5.4.3.2

Forward Acceleration Ramp

Reverse Ramp Check - Adjust reverse acceleration ramp as follows:

Set FWD/REW /REV switch to REV. Observe positive slope of 7-8 ms (Figure 5-15.)

Adjust +CUR potentiometer on H606, if necessary.

1,-LLL~~~~
9~""

....

f----+-1fII'- . . .

10' . .•

•••.

.•••

.••.

. . . .-

....

.•••

••••

•••.

••.•

••..

• •••

l----+---+--+---+--+--+~-t----I

Figure 5-15

Reverse Acceleration Ramp

5-19

5.4.3.3 Tracking Check - Place SSRD switch on TFG (M8912) down. Rewind tape. Remove the float
from scope ground. Check the industry-compatible tape tracking as follows:
I.

Set up the TFG as follows :
SSWRT, SSRD, and WRT: Down
S5: 1-8 OFF
S5: 9 and 10 ON
S6: 1-10 OFF

Set the FWD/REW /REV switch to FWD. Place SSRD momentarily up, then down. (This
loads data into the TFG write buffer.)

Position tape at BOT.

Place the WR T switch of the TFG up; press FWD and START on the control panel.

Allow the tape to be written for 10 seconds; ensure that the WRT indicator on the control
panel is on as the tape is being written.

Place the WR T switch down; rewind tape.

Remove the tape from the drive, take it to a work area, and proceed as follows :
a.

Unwind tape until you reach the BOT marker; cut the tape with scissors.

Unwind 93 cm (3 feet) of tape beyond the BOT marker; cut the tape again.

Shake Magna-See solution vigorously.

Dip the 93-cm (3-foot) section of tape in Magna-See solution (Figure 5-16 .) Try to keep
a loop of tape at the bottom of the can.

766()"24

Figure 5-16

Developing Magnetic Tape
5-20

Work the tape back and forth until the entire 3-foot section (except for the ends being
held) has been dipped into the solution.

Allow the tape to dry. Data written on the tape should appear as the solution dries
(Figure 5-17.) If necessary, dip the tape again.

1\*

1\*
7660-27

TU45A/TM03

Figure 5-17

Developed Magnetic Tape

When the tape has been developed, proceed as follows:
a.

Place the developed tape flat on a white background (e.g., white sheet of paper).

Make sure that the tape is flat, then place a weight on each end.

Check four points along the reference edge (edge with BOT marker) 3.8 cm (1-1/2
inches) apart. (Refer again to Figure 5-17.)

Set up a microscope according to Figure 5-19; lay the penlight flat on the table, positioned so that it shines on the reflector.

Ensure a distance of 0.178 ± 0.076 mm (0.007 ± 0.003 inch) from the reference edge to
track I (inset in Figure 5-18) at each of the four points mentioned in Step c, above.

NOTE
If the tracking check described above fails, tape path
alignment must be performed at this time.
9.

Install a new BOT marker 4.58 m (15 feet) from the front of the tape on the non-oxide side,
against the reference edge. (The reference edge faces the operator when the tape is installed
on the transport.)

5-21

TRANSPARENT
CASE

Figure 5-\8

5.4.3.4

REFLECTOR

TAPE

PENLIGHT
7660-28

Track No. \ to Reference Edge Measurement

Erase Head Check - Check the erase head function as follows:
\.

Load the tape and position it at BOT.

2. Set up TFG as follows:
SSWRT, SSRD, and WRT: Down
S5: 1-8 OFF
S5: 9 and 10 ON
S6: 1-10 OFF
3.

Set the FWDjREW JREY switch to FWD. Place SSRD momentarily up, then down .

Place the WRT switch on the TFG up; press FWD and START on the control panel. Allow
tape to be written for 30 seconds.
NOTE
Steps I through 4, above, are recording an all-Is tape
at low density (full saturation). The steps below
check the ability of the TUIOW to erase a saturated
tape.

5-22

Press STOP on the control panel. Place the WRT switch down. Rewind tape.

Set up the TFG as follows:
S4: 1-8 ON
S4: 9 and 10 OFF
S5: 1-8 ON
S5: 9 and 10 OFF
S6: 1-10 ON
SSWRT, SSRD, and WRT: Down

Press FWD on the control panel and place SSWRT on the TFG up; allow tape to be written
for 1 minute.

Lower the SSWRT switch; rewind tape.

Set up the oscilloscope as follows:
1 ms/cm
Channell
50 mV /cm
Triggering
Auto, Channell triggered
Channell probe on A4-Ll
Channell probe ground on B4-C2.

10.

Press FWD and START on the control panel.

11.

Measure unerased signal level for maximum level. (Ensure good scope ground.) Maximum
level must be less than 300 mY. Failure of this check will require replacement of the head
plate assembly. (Tape path alignment must be performed at this time.) Figure 5-19 is an
example of acceptable erasure.

100-~---+---r--~--T---T-~r-~----T--~

I . ..
90·

.... ....

Figure 5-19

.... ...

. ..

.... ....

.... . ...

Acceptably Erased Signal

5-23

12.

Rewind tape. Place the Channell scope probe on C4-Ll. (Ensure good ground.) Initiate
forward motion. Check un erased signal level (max = 300 mY).

13.

Rewind tape. Place the Channell scope probe on F4-Rl. (Ensure good ground.) Initiate
forward motion. Check un erased signal level (max = 300 mY).
NOTE
The remaining tests require comparison of read
amplifier outputs under varied conditions. Photocopy
the table shown in Figure 5-20, or prepare a similar
table.

Track

Pin No.

A4-l1

Read Amplitude

Residual Amplitude

Reverse Amplitude

B4-B1

N/A

B4-M1

N/A

C4-K1

N/A

C4-L 1

D4-P1

N/A

D4-R1

N/A

F4-P1

N/A

F4-R1

Figure 5-20

Sample Table for Read Amplifier Comparisons

5-24

5.4.3.5

Read Amplifier Check - Check read amplifier outputs as follows:

Rewind the tape and remove from transport.

Clean the read/write head, erase head, and tape cleaner.

Load a good quality tape, positioned at BOT; set up the scope as follows:
Channell
Sweep speed
Trigger

2 V /cm
2 ms/cm
Normal, Channell triggered

Set the switches on the TFG as follows:
S4: 1-8 ON
S4: 9 and 10 OFF
S5: 1-8 OFF
S5: 9 and 10 ON
S6: 1-8 OFF
S6: 9 and 10 ON
SSWRT, SSRD, and WRT: Down

Place the SSWRT switch in the TFG up and place the Channell probe on A4-Ll. The scope
presentation should resemble Figure 5-21.

ll'--~--4---+---~~---+---r---r--~~
I
90· . .•

....

.•.•

.•..

•..•

•.••

10' . • • r-'--'1----+---+--+O-~

..•.

....

. ••.

.... .... .... .. ..

°i'-+--+---+---I-I------1--+--~

Figure 5-21

Read Amplifier Output

Increase vertical sensitivity to 1 V/cm and place interrecord gap 1 cm down from top.
Measure negative half of read amplifier output (using the interrecord gap as the baseline).
The peak amplitude of the negative-going signal should be from -4.45 to -4.75 V (Figure 522.) Record the results in the Read Amplitude column of the table (photostated from Figure
5-20 or prepared previously) beside Track 1.
5-25

,1-.- ' -' l.
9~."

............

,-I-,

10· . .•

••..

..•.

•••.

•.••

•.•.

••..

.•.•

••..

. •••

1---+---+-----+--+--+--t--+-------1!-----+------l

Figure 5-22

Negative Half of Read Amplifier Output

Repeat Step 6 for all nine tracks, recording the results in the same table. If any track is out of
the acceptable range (-4.45 to -4.75 V), adjust all nine channels to -4.6 V. Such adjustment
requires the following procedure:
a.

Turn power off.

Take the TFG off the extender.

Place G056 on the extenders.

Turn power on.

Adjust all read amplifiers to -4.6 V. (Potentiometers are arranged sequentially from
top to bottom, starting with Track 1.)
NOTE
If any channel cannot be adjusted within range, the
TUIOW input preamplifier resistors may have to be
changed.

Place the SSWRT switch on the TFG down; rewind the tape.

5.4.3.6 Residual Amplitude Check - Perform the residual amplitude check as follows. (Residual
amplitude is the amplitude left on the tape after several read operations. Some amount of erasure can
be expected during the first few read passes, due to residual magnetism in the write and erase heads.)
I.

Press FWD; raise SSWR T. Allow start/stop data to be recorded for at least 20 seconds, then
place SSWR T down and rewind tape.

Initiate FWD tape motion; allow the tape to run in the forward direction for 10 seconds.
Rewind tape. Repeat this operation ten times.

5-26

Leave scope setup as it was after the last step of Paragraph 5.3.4.5. Place the Channell
probe on A4-Ll. Initiate FWD motion. Record the negative read amplifier output in the
Residual Amplitude column of the table. Rewind tape.

Place the Channell probe on C4-Ll. Initiate FWD motion. Record the negative read amplifier output in the Residual Amplitude column of the table. Rewind tape.

Place the Channell probe on F4-Rl. Initiate FWD motion. Record the negative read amplifier output in the Residual Amplitude column of the table.
NOTE
It is assumed that tape did not run more than 10 seconds forward during Steps 3, 4, and 5, above. If there
is any doubt of this, rewind tape and recheck residual
amplitude.

5.4.3.7

Compare the entries in the Residual Amplitude column of the table with the entries in the
Read Amplitude column. If the Residual Amplitude entries show a decrease of greater than
20 percent on any of the three tracks, replace the head plate assembly.
Reverse Amplitude Check - Perform the reverse amplitude check as follows:

Rewind tape.

Place the Channell probe on A4-Ll; run tape FWD from BOT for 10 seconds. Initiate REV
tape motion; record the negative read amplifier output in the Reverse Amplitude column of
the table.

Place the Channel I probe on C4- L1; run tape FWD from BOT for 10 seconds. Initiate REV
tape motion; record the negative read amplifier output in the Reverse Amplitude column of
the table.

Place the Channell probe on F4-Rl; run tape FWD from BOT for 10 seconds. Initiate REV
tape motion; record the negative read amplifier output in the Reverse Amplitude column of
the table.

Compare entries in the Reverse Amplitude column of the table to the entries in the Residual
Amplitude column. If the Reverse Amplitude entries show a decrease of greater than 10
percent, the tape path alignment must be performed at this time.

NOTE
Perform Paragraph 5.4.2.13 at this time.

5.5

ADJUSTMENTS AND ALIGNMENT PROCEDURES
No adjustments exist for the M8926 Interface module. Adjustments and alignment procedures relative
to the TU lOW Host Drive and the TMBll Controller are provided in this section.

5.5.1

Adjustment Procedure
This section contains all the procedures required to adjust the TMBll/TUlOW DECmagtape System.
Paragraphs 5.5.1.1 through 5.5.1.11 relate to the TUlOW, while Paragraph 5.5.1.12 relates to the
TMBII.

5-27

5.5.1.1 TUIOW Power Supply - Four adjustments to the power supply adjust the four dc output
voltages: +5.3 V, +12 V, + 12 V, and -6.4 V. A small screwdriver is all that is required. Clockwise
adjustment of any of the potentiometers increases voltage. All potentiometers are located on top of the
TU lOW power supply board. Refer to Figure 5-7 for the respective locations and to Table 5-3 for
adjustment values. Do not make adjustments if voltages are within tolerances of Table 5-3.
Use a calibrated voltmeter, preferably a digital voltmeter. Voltages should be adjusted to the values
indicated in Table 5-3.

CAUTION
Do not adjust voltages beyond their 105 percent rating and adjust slowly to avoid overvoltage crowbar.

Table 5-3

J 5 Connector
Pin Number
1
4
5
8

TUI0W Power Supply Regulated Voltages

Adjustment
Potentiometer

Voltage (Under Load)
(Volts)

Wire Color
Code

R59
R44
R37
R26

5.2 to 5.3
-6.3 to -6.4
12.0 to 12.1
12.0 to 12.4 (NRZ)

RED
GRN
YEL
ORN

5.5.1.2 Capstan Servo DC Balance - To perform the capstan servo dc balance adjustment, proceed as
follows:
I.

Pull the TU lOW Tape Transport out on its slide mount.

Apply power to the TU lOW and place the unit off-line.

Place the control panel START/STOP switch on STOP.

Set up to measure the voltage at test point 2 of the TU lOW's H606 power board.

Slowly adjust R21 on the H606 power board to obtain 0.0 V ± 0.04 V at test point 2.

Check capstan speed (Paragraph 5.5.1.3).

5.5.1.3 Capstan Speed - Potentiometers are located on the H606 to adjust the FWD, REV, and REW
speeds. To check and adjust capstan speed, proceed as follows:
l.

Load a master skew tape (800 bits/inch).

Place an oscilloscope probe on pin CUI of the Read Amplifier (0056).

Initiate FWD tape motion and measure a 100- to 400-ns pulse with a period of 56.0 p,s as
shown in Figure 5-23.

5-28

11-4673

Figure 5-23

Capstan FWD and REV Speed Waveforms

4. If necessary, adjust the FWD potentiometer (R13).
5. Initiate REV tape motion; conditions should be identical to those observed in Step 3.
6. If necessary, adjust the REV potentiometer, R12.
7.

Remove the master skew tape and load a scratch tape.

8. With the TFG configured for 800 bits/inch, write an all Is pattern on the tape.
9. After ensuring that there is adequate tape on the take-up reel, run the TUI0W in REW.
Observe a wave pattern similar to that shown in Figure 5-23, except that the period between
pulses is approximately 16.6 }.LS.

10. If necessary, adjust the REW potentiometer (Rll).
11. Perform capstan acceleration and deceleration adjustment (Paragraph 5.5.1.4).
5.5.1.4 Capstan Acceleration and Deceleration Times - Capstan acceleration and deceleration times
are best measured while running the SSRD test with the Test Function Generator. To check the
capstan acceleration and deceleration times, proceed as follows:
1.

Connect oscilloscope channel A to the tachometer signal found on the H606 at PI pin 7.

Connect the oscilloscope EXT TRIG to pin A3S1 (FIRST ONE SHOT L) of the TUIOW
backplane.

Set the scope controls as follows:
Channel A
Time/Div
A TRIG

0.2 V/cm
2 ms/cm
EXT, negative slope

With the Test Function Generator (TFG) module, initiate an SSRD function in the FWD
direction, and adjust R89 on the H606 to obtain a negative slope of 7-8 ms duration on the
scope (Figure 5-24a).

5-29

With the TFG, initiate an SSRD function in the REV direction, and adjust R90 on the H606
to obtain a positive slope of 7-8 ms duration on the scope (Figure 5-24b).
NOTE
Deceleration times are not adjustable, and will be
somewhat shorter than the acceleration times.

8ms
MAX

(ACCEL):

1~7ms I
I MAX I

:(DECEU: T

-v

-v
a.FWD TAPE MOTION

b. REV TAPE MOTION
CP-OI24

Figure 5-24

Acceleration and Deceleration Times

5.5.1.5 Brake Adjustment (Electrical) - To ensure proper operation of the TUIOW, an adjustment to
the brake circuit may be necessary after normal wear or long periods of inactivity. In addition, brake
operation must be checked after cleaning the brake armature. The TU10W brake circuitry has two
adjustments that affect brake operation during rewind. Both adjustments affect only the upper brake
and upper vacuum column.
Proceed as follows to perform a visual check of the rewind operation:
1.

Place the TU10W in the off-line mode and move tape to EOT.

Initiate the rewind operation from EOT several times. Allow the operations to continue
approximately 10 seconds before returning to EOT.

5-30

Initiate the rewind operation and continue to the BOT marker. Check for an improperly
adjusted brake circuit by watching for any of the following symptoms during the rewind
operation:
a.

Any vacuum column failure.

More than two or three tape loop excursions exceeding approximately one-third of the
distance into the brake zone. During acceleration from EaT, two or three large excursions are normal.

Normal tape loop excursions during acceleration but a sluggish return of the tape loop
from the reel motor zone to the brake zone.

Erratic tape loop excursions during the con tin uous rewind operation exceeding 3.17 cm
(1-1/4 inches) above the upper vacuum column upper vacuum switch. Tape motion will
always be somewhat erratic, but the magnitude of the loop "jumps" should be less than
3.17 cm (1-1/4 inches).

In almost every case, a tape loop failure can be diagnosed as an extreme example of symptoms b, c, or
d.
Continuous large tape loop excursions (symptom b) are probably due to one of the following:
1.

High current rewind time is too short. The high current rewind time is measured as a negative pulse at test point 18 of the H606 power board during a rewind operation. Typical pulse
width is 20-25 ms. It is adjusted using the REW PULSE potentiometer (R61) on the H606
power board.

Low current rewind amplitude is too low. The amplitude is adjusted using the LOW CURRENT AD] potentiometer (R 79) on the H606 power board. Clockwise rotation of the
potentiometer increases the current to the brake. Adjustment should be made at intervals
not greater than two turns of the potentiometer.

Symptom c is an indication that the low current rewind amplitude is too high. Counterclockwise
adjustment of the LOW CURRENT AD] potentiometer (R 79) on the H606 power board will decrease
the amplitude. The effects of the potentiometer adjustment should be observed at intervals of two
turns of the potentiometer.
Symptom d is an indication that the high current rewind time is either above or below the ideal
operating range. The 20-25 ms range is a helpful guideline, but is not absolute, and will depend on the
operation of the brakes.
5.5.1.6

Read Amplitude Adjustment

Check capstan speed (Paragraph 5.5.1.3) and adjust if necessary.

Rewind the tape and remove it from the transport.

Clean the read/write head, erase head, and tape cleaner.

Load a good quality tape, positioned at BOT; set up the scope as follows:
Channell
Sweep Speed
Trigger

2V/cm
2 ms/cm
Normal, Channell triggered
5-31

Set the switches on the TFG as follows:
S4: 1-8 ON
S4: 9 and 10 OFF
S5: 1-8 OFF
S5: 9 and 10 ON
S6: 1-8 OFF
S6: 9 and 10 ON
SSWRT, SSRD, and WRT: Down

Place the SSWRT switch in the TFG up, and place the Channell probe on A4-Ll. The
scope presentation should resemble Figure 5-25.

,1---+----+---+----+---t---+----+----+-+-------1
I

90' . ..

•...

....

•..•

...•

'0' . . .

....

. ..•

. . ..

....

. ...

°r------+--+---+--t----t-----t------+-------lf---------+----

Figure 5-25

Read Amplifier Output

Increase vertical sensitivity to 1 V /cm and place the inter-record gap 1 cm down from the
top. Measure the negative half of the read amplifier output (using the inter-record gap as the
baseline). The peak amplitude of the negative-going signal should be from -4.45 to -4.75 V
(Figure 5-26).

Repeat Step 7 for all 9 tracks. See Table 5-4.

5-32

11_~

Al.

~ .... ~ ....... ~ ..

1-'

10' . ••

••••

• •.•

j.-+----+--+--+---+-----I--+--t---t---I
Figure 5-26

Negative Half of Read Amplifier Output

Table 5-4

Read Amplitude Test Points
Track

1
2
3
4
5
6

A4-Ll
B4-Bl
B4-Ml
C4-Kl
C4-Ll
D4-Pl
D4-Rl
F4-Pl
F4-Rl

7
8
9

If any track is out of the acceptable range (-4.45 to -4.75 V), adjust all nine channels to -4.6
V. Such adjustment requires the following procedure:

Turn power off.

Take the TFG off the extender.

Place G056 on extenders.

Turn power on.

5-33

Place the SSWR T switch on the TFG down; rewind the tape.

5.5.1.7 Write Skew Adjustment - The procedure should be performed only after completing the read
skew adjustment (Quarterly PM item in Paragraph 5.4.2). Write skew adjustment is only required
upon replacement of the head plate assembly, or when excessive wear in the head plate assembly is
suspected.
1.

Slide the TU lOW Tape Transport out of the cabinet.

With power removed from the transport, remove the Test Function Generator (TFG) module (M8912) from section EF of slot 3.

Set the TFG switches as follows:
S5: 1-8 OFF
S5: 9 ON
S5: 10 OFF
S6: 1-8 OFF

Insert TFG into section AB of slot 3.

Ensure that the SSRD, WRT, and SSWRT switches at the upper portion of the module are
in the lowered position.

Apply power to the TUIOW. The LED indicator on the TFG should light.

Load write-protected IBM skew tape (800 bits/inch) on the transport.

Initiate forward tape motion from the transport control panel.

Connect the channel A input of an oscilloscope to pin E4Kl (PACKET), using internal
sync, negative slope. PACKET is a composite signal, comprised of read amplifier outputs of
all nine tracks.

to.

Monitor the pulses which comprise PACKET on Channel B of the scope, using chopped
mode. Note and tabulate their positions, in microseconds, with respect to the leading edge of
PACKET (Figure 5-27). Table 5-5 lists the pins to be monitored for each track; it also
contains a column, left blank, for listing the position of the monitored pulses relative to
PACKET, and can therefore serve as a model to the user.

5-34

CHANNEL A
(PACKET)

II 1111I
I

I
I

~ PULSE POSITION
CHANNEL B

j
10-1338

Figure 5-27

Measurement of Pulse Positions Relative to Packet

Table 5-5

Write Deskew Parameters
Measured
Pulse Position

Track No.

A4J1
A4Hl

2
3
4
5
7
8

B4Nl
B4L1
C4Ul
C4S1
E4Hl
E4Fl

F4Ml

(J-ts)

11.

After tabulating the data for all nine tracks, terminate tape motion.

12.

Unload the skew tape and load a scratch tape on the transport.

13.

Raise and lower the TFG SSRD switch; this loads the preselected data pattern.

14.

Raise the TFG WRT switch. Now initiate forward tape motion from the transport control
panel. The TUIOW will perform a continuous write operation.

15.

Monitor the pins that were monitored in Step 10. Note the position of the displayed pulses
relative to the leading edge of PACKET. If the position measured now differs from the
position measured in Step 10 by more than 2 J-tS, alter the write deskew jumper configuration
on the TUIOW backplane. The jumpers connect the write deskew buffer (refer to drawing
M891O, sheets 3 and 4) to four record pulses (SK CLK A, SK CLK B, SK CLK C, and SK
CLK D) which are shift delayed in increments of 0.9 J-tS. These pulses are available at the
following pins:
SKCLKA
SKCLKB
SKCLKC
SKCLKD

A2R 1 and A2R2
A2Nl and A2N2
A2L1 and A2L2
A2B 1 and A2B2
5-35

The jumper configuration must be modified so that the position of the monitored pulse with
respect to the leading edge of PACKET does not vary by more than 2 }.LS from that obtained
in Step 10.
16.

After performing the write skew adjustment, remove power from the transport and replace
the TFG module in section EF of slot 3.

5.5.1.8 Read/Write Interlock Assembly - Proceed as follows to perform the read/write interlock
assembly adjustment (Figure 5-28):
1.

Loosen the two screws securing the switch to the bracket just enough to allow the switch to
be moved.

Loosen the locknut and adjusting screw several turns (see detail B, Figure 5-28).

Insert the small end of the setting gauge (29-18610) in front of the roll pin through the
bottom of the bracket body edge. Tighten the adjusting screw until the switch just actuates.

4. Tighten the two screws securing the switch to the bracket and lock the adjusting screw using
the locknut.
5.

Loosen the two solenoid mounting screws (detail A, Figure 5-28).

Insert the large end of the setting gauge in front of the roll pin as described in Step 3. Push
the solenoid body forward until the plunger bottoms out; then tighten the solenoid mounting screws, keeping the solenoid body parallel to the upper edge of the bracket.

Loosen the bottom screws securing the interlock assembly to the mounting bracket (detail
C, Figure 5-28).

Insert the ring gauge (29-18608) on the reel, lock it, and spin the reel to check for even
rotation.

Push the interlock assembly forward until the shaft bottoms in the solenoid and the small
spring is fully depressed.

10. Tighten the screws securing the assembly to the bracket, remove the ring gauge, and check
for free movement of the solenoid shaft in the casting.
5.5.1.9

Vacuum Motor Belt Adjustment - Proceed as follows to adjust the vacuum motor belt:

Tighten the four motor plate mounting nuts.

Using gauge 74-16187, set the pulley height to 1.32 cm or 2.08 cm (0.520 inch or 0.820 inch).
NOTE
The pulley is positioned either 1.32 cm or 2.08 cm
(0.520 inch or 0.820 inch) above the mounting assembiy to accommodate 60 or 50 Hz operation, respectively (selects one of two pulley diameters). For
further information, refer to the vacuum assembly
drawing E-AD-7009638-0-0.

5-36

SOLENOID

(ADJUSTABLE)----.~~

...-\.

SOLENOID MOUNTING BRACKET

SOLENOID SHAFT

" " - - - SWITCH (ADJUSTABLE)
........
\_,

VI
I

-..J

~~/

SWITCH
CONNECTING
PINS (3)

INTERLOCK ASSEMBLY
ADJUSTMENT
SCREWS
(UNDERSIDE OF
MOUNTING BRACKET)

I
I
I

SOLENOID
ADJUSTMENT
SCREWS (LEFT OF
INTERLOCK ASSEMBLY
AS VIEWED FROM
FRONT OF TU 16 )

Figure 5-28

SWITCH
ADJUSTMENT
SCREW

Read/Write Interlock Assembly

CP-0096

Place the belt tension gauge on the belt.

Pull the belt tension gauge knob until surface "A" touches the belt (Figure 5-29).

BELT TENSION
GAGE

KNOB

DRIVE PULLEY-50Hz

MOTOR PLATE
TAKE-UP SCREW

BLOWER PULLEY

SURFACE "A"

DR IV E
PULLEY-60Hz
10-2075

Figure 5-29

Vacuum Motor Belt Adjustment

Tension should read 2.25 to 3.6 kg (5 to 8 lb).

If tension is out of tolerance, loosen the four motor plate mounting nuts and adjust the
motor plate take up screw until a 2.25 kg (SIb) reading is obtained. Tighten the motor plate
mounting nuts.

If the belt adjustment was performed after installing a new belt, the new belt must be "run
in" for 30 minutes and then readjusted according to steps 3, 4, 5, and 6 above.

5.5.1.10 Read Circuitry Adjustment - The only adjustments directly affecting the proper operation of
the TMBlljTUI0W read circuitry are the read amplitude adjustment (Paragraph 5.5.1.6), the read
skew adjustments (Paragraphs 5.4.2.11 and 5.4.2.12) and the + 12 V NRZI threshold adjustment (R26)
on the regulator board (Paragraph 5.5.1.1).
5.5.1.11 Write Circuitry Adjustment - The only adjustment directly affecting the proper operation of
the TMBlljTUlOW write circuitry is the write skew adjustment (Paragraph 5.5.1.7). The adjustment
should only be performed after replacing the head plate assembly, or when excessive wear in the head
plate assembly is suspected. Note that before adjusting write skew, the read skew adjustment (Paragraphs 5.4.2.11 and 5.4.2.12) must be performed.

5-38

5.5.1.12 TMBll Adjustment Procedure- The TMBII Controller has two adjustments located on the
M7912 Unibus registers module. These are the drive function timer adjustment (Figure 6-13) and the
time-out adjustment (Figure 6-16).
I.

To adjust the drive function timer, apply power to the TMB II and scope E41 pin 9 [09
TIMER (1) H]. Adjust R7 (lower potentiometer) for a 50 f..lS positive pulse.

To adjust the time-out period, perform the following steps:
a.

Load the utility driver program (MAINDEC-II-DZTMG) into memory.

Load address 7008. Deposit 060400.

Install a 1 plug into the UNIT SELECT socket of an on-line TU lOW (master or slave).
Unit 0 must be off-line.

Load address 2008 and start the program.

With probe for trace 1, scope pin C02PI of the TM BI1.

Use an internal negative trigger. Set the horizontal sweep for 5 f..ls/cm.

Adjust R2 (upper potentiometer) for a 28 f..lS negative pulse.

5.5.2 Alignment Procedure
A TUIOW tape path alignment procedure should be performed when:
1.

A capstan, capstan motor, roller guide, or head plate is replaced.

Forward and/or reverse skew is found to exceed specifications. (Refer to Paragraphs
5.4.2.11 and 5.4.2.12.)

An amplitude difference of more than 10 percent is seen between forward and reverse read
amplifier output.

A visible change in the tape's path across the capstan is apparent when changing from
forward to reverse tape motion.

Measurement of reference edge to track I of a developed (with Magna-See solution) tape
shows a result different from 0.178 ± 0.076 mm (0.007 ± 0.003 inch). Refer to Paragraph
5.4.3.3.

After performing a tape speed adjustment (Paragraphs 5.4.2.7 and 5.4.2.8) and mechanical
skew adjustment (Paragraphs 5.4.2.11 and 5.4.2.12) under quarterly preventive maintenance, and performing capstan ramp adjustment (Paragraphs 5.4.3.1 and 5.4.3.2) and read
amplitude adjustment (Paragraph 5.4.3.5) under semiannual preventive maintenance, and
running all TUIOW diagnostics, you are still encountering incompatibility with other tape
transports.

5.5.2.1
1.

Objectives- The objectives of the tape path alignment procedure are listed below:
To establish a single plane for tape to travel from supply reel to take-up reel, independent of
the capstan and fixed guides (part of the head plate assembly). This is accomplished by
aligning reel hubs and roller guides.

5-39

To mount the head plate in the plane established in Step 1. This is accomplished by establishing the relationship between the reference surfaces used in Step 1 and the surface onto
which the head plate is to be mounted. If this relationship is nominal, the head plate is
simply mounted. If the relationship is not nominal, appropriate shims are placed under the,
head plate in order to bring the reference edges of the fixed guides into the proper plane.

To minimize the amount of distortion to the tape as it travels through the plane established
in Steps 1 and 2. This is accomplished by shimming the capstan motor so that the capstan
motor shaft becomes perpendicular to the tape path.
NOTE
The effect of accomplishing the above steps is to minimize static skew, dynamic skew, and tracking errors
in both forward and reverse directions. Skew is the
total amount of non-perpendicularity of characters
written on tape. Tracking is defined by ANSI standards as the measurement from the reference edge to
each track center line. Improper tracking takes two
forms:
Read - A tape transport that is tracking
incorrectly will not have its read head elements
centered over tracks correctly written by another
tape transport.
Write - A tape transport tracking incorrectly will
write tracks of data that are not correctly spaced
from the reference edge of the tape. Therefore, a
transport with proper tracking alignment would
not have its read head elements centered on the
incorrectly written tracks.

5.5.2.2 Tools Required for Tape Path Alignment - A list of tools specifically required for aligning the
tape path is provided below:
Tool Name

DEC Part No.

Tool Name

DEC Part No.

Skew Tape (800 bits/inch)
365.8 m (1200 ft)
182.9 m (600 ft)
Reel Hub Tool
Roller Guide Tool
Microscope
Magna-See
Penlight
Alignment Glass

Depth Micrometer
Shim Stock
0.001
0.002 (red)
0.003 (green)
0.004 (tan)
0.005 (blue)
0.0075 (transparent)
0.0010 (brown)

29-22039

29-19224
29-22020
29-18611
29-18607
29-20273
29-16871
29-10780
74-13969

5.5.2.3

48-50023-01
48-50023-03
48-50023-04
48-50023-05
48-50023-06
48-50023-07
48-50023-08

Procedures - Perform the following steps to establish a basic tape path plane:

Remove both the supply and take-up reels.

Use the reel hub alignment tool to check alignment of both reel hubs. You should feel a
small amount of friction when sliding the tool in and out between alignment boss and reel
hub. You should not be able to move tool back and forth between hub and alignment boss.
Loosen Allen screws and adjust the hub if necessary. Refer to Figure 5-30.

5-40

7660-3

Front View

REEL HUB ALIGNMENT
GAUGE #29-18611
(Should feel friction _ _ _ _~
in verticol (I) axis.
Gauge should not move

TOP
OF
TRANSPORT

in horizontal (-) ax.is.)

MACH INED
ALIGNMENT
BOSS
REEL HUB ALLEN _ _----..
LOCKING SCREWS (2)

TEFLON

WASHER--;r-~

3/16 INC H KEY

REEL MOTOR
DRIVE SHAFT

REEL HUB ASSEMBLY----.J

FRONT OF

TRANSPORT----~
CP-Ot04

b.
Figure 5-30

Side View
Reel Hub Adjustment
5-41

Rotate the hub, checking the fit of the alignment tool at several intervals. There will probably find some high and low spots but the tool should not bind hard or become loose when
moving tool toward and away from the casting. Replace hub and/or motor if either of these
conditions exists.

Remove the upper roller guide ramp (Figure 5-31).

Slide the roller guide alignment tool under the upper roller guide. You should feel a small
amount of friction as you slide the tool back and forth under the roller guide. Loosen the
clamp on back side of the casting and adjust the roller guide if necessary (Figure 5-32).

UPPER
ROLLER
GUIDE

LOWE-R

ROLLER
GUIDE

7660-12

Figure 5-31

Location of Upper and Lower Roller Guides

5-42

7660-1 .

7660-5 '

Upper Roller Guide Adjustment

Lower Roller Guide Adjustment

FRONT OF

~ TRANSPORT

ROLLER SHAFT
LOCK CL AMP

TAPE ROLLER
GUIDE ALIGNMENT
GAUGE # 29-18607

TAPE GU IDE ROLLER

# 6 X 32 X 1/2" ALLEN
CLAMP LOCK

SCREW ~

"" "'" 7--

[>-

EXERT PRESSURE
AT THIS PO INT
DURING ALIGNMENT

~-IIIW'

ROLLER SHAFT
CLAMP
MOUNTING
SCREW

CP-Ol05

Side View of Roller Guide Tool Insertion

Figure 5-32

Roller Guide Adjustments
5-43

Slide one side of the roller guide alignment tool under the lower roller guide. You should feel
slight amount of friction as you move the tool back and forth. Adjust if necessary (Figure 532).

Load a scratch tape. Run the tape forward for 5 seconds.
a.

Ensure that the tape is not touching either side of the supply or take-up reel while the
tape is moving.

Look for tape puckering against either the column floor or door glass at both the upper
and lower roller guides.

If either of these conditions exists, recheck the associated roller guide and reel hub
adjustments.

Dismount the tape. Reinstall the upper roller guide ramp.
CAUTION
When installing the ramp, you must push down on
the right side of the ramp while tightening the screw.
Otherwise, the ramp may touch the tape.

Perform the following steps to mount a head plate in the tape path plane:
1.

Remove the head plate cover.

Disconnect the write, read and erase head cables from the head.

Loosen the three shoulder screws and remove the head assembly.

Measure the depth from the outer surface of the left vacuum column to the surface onto
which the head plate was mounted. Nominal value is 2.84 cm (1.12 inches). Call this value
"HMS" (Figure 5-33).
NOTE
You may find this measurement difficult to make
because you can only seat one side of the micrometer
on the vacuum column surface. It is, therefore,
advised that you:
1.

Place the micrometer base at a 45-degree angle
with the vacuum column surface (gives greater
seating area).

Make the measurement with the micrometer
shaft as close as possible to the vacuum column
wall (gives more leverage to keep the micrometer base seated and has distance to project
error).

Repeat the measurement several times to verify
results.

5-44

DEPTH
MICROMETER

HEAD PLATE
MOUNTING
SURFACE

LEFT VACUUM
COLUMN

7660-18

Placement of Depth Micrometer

DEPTH
MICROMETER

LEFT
VACU UM
COLUMN

HMS

HEAD PLATE
MOUNTING
SURFACE
CP-1991

b.
Figure 5-33

Bottom View of HMS Measurement

Measurement of Head Plate Mounting Surface (HMS)
5-45

Subtract 1.120 from HMS.

If the result obtained in Step 5 is zero or negative, mount the head plate* without shims.
If the result obtained in Step 5 is positive, cut three horseshoe-shaped shims of the value
obtained in Step 5 and place one under each of the three shoulder screws when mounting the
head plate* (shims go between the head plate and mounting surface). See Paragraph 5.5.2.2
for shim color codes. Also cut a shim of the same value to surround the vacuum port which
goes to the tape cleaner (prevents air leakage). See Figure 5-34.

HOLES FOR MOUNTING
SCREWS (3)

VACUUM PORT

7660-20

Figure 5-34

Location of Shims under Head Plate Assembly

Thus far, this section has described how to set the reel hubs and roller guides in the same plane as
vacuum columns (Figure 5-35) and how to set the reference edge of the fixed guides into the plane of
the tape coming out of the vacuum columns. (Figure 5-36). The following paragraph will describe how
to set the shaft of the capstan motor perpendicular to the tape path so as to minimize distortion of the
plane already established.

*If a new head assembly is mounted, electrical wire deskew will have to be performed. This should be done after
the read mechanical skew adjustment (quarterly items 11 and 12 in preventive maintenance section).

5-46

SUPPLY
REEL

LEFT
VACU UM
COLUMN

LOWER
ROLLER
GUIDE

UPPER
ROLLER
GUIDE

TAKE-UP
REEL

MACHINED REFERENCE
SURFACES
CP-1993

Figure 5-35

Machined Reference Surfaces Used to
Establish Tape Path Plane

READ/WRITE
HEAD

FIXED GUIDE ON
REFERENCE EDGE

p
_____
__ ___':5,c;.O::---

T -_

l _____~-J

1.118*

~~---+--~--~~
t HEAD

LMOUNTING
SURFACE

DOTTED LINE
INDICATES
TAPE PATH

*Dimension from reference edge of fixed guide to
mounting surface set up by head plate jigging in
factory.

~f498

_ __

SPRING LOADED
GUIDE

**Nominal vacuum column depth is 0.502; nominal

tape width is 0.498; one edge of tape should be
0.002 from floor of vacuum column; other edge
should be 0.002 from glass.
CP-1983

Figure 5-36

Head Plate Assembly Mounted in the
Plane of the Tape Path

Steps 1 through 21 ensure that the capstan motor shaft is perpendicular to the tape path. Two conditions can cause non-perpendicularity of the motor shaft to the tape path. One is the capstan motor
shaft not being perpendicular to the mounting face of the motor. Figure 5-37a and 5-37c are examples
of this condition. [Specifications allow 0.127 mm (0.005 inch) of non-perpendicularity of the motor
shaft.] The other condition is non-parallelism between the motor mounting surface on the back of the
casting and the front surface of the casting. Figure 5-37b illustrates this situation. [Specifications allow
0.102 mm (0.004 inch) of non-parallelism between the machined surfaces on the front and back of the
casting.]

5-47

CP-1996
CP-1994
CP -1995

a. Side View Capstan Motor Shaft Pointing
Down due to Non-Perpendicularity of Shaft

Figure 5-37

b. Side ViewCapstan Motor Shaft Pointing
Up due to Non-Parallelism of
Machined Motor Mounting
Surfaces

c. Top ViewCapstan Tipped Toward Casting on Left Side and Away
from Casting on Right Side
due to Non-Perpendicularity
of Motor Shaft

Examples of Capstan Non-Perpendicularity

The effect of the capstan motor shaft not being perpendicular to the tape path depends on the direction
of the non-perpendicUlarity, i.e., whether the motor shaft is pointing up, down, toward the left, or
toward the right. When the shaft is pointing down (Figure 5-37a), the top of the capstan is away from
the casting, causing the tape to track away from the casting. Hard guiding occurs on the vacuum door
glass and the fixed guides in both forward and reverse directions. When the shaft is pointing up (Figure
5-37b), the bottom of the capstan is away from the casting, causing the tape to track toward the
casting. Hard guiding occurs on the vacuum column floor and the spring-loaded guides in both forward and reverse directions. When the shaft is pointing toward the left (Figure 5-37c), the tape tracks
away from the casting in the forward direction and toward the casting in the reverse direction. If the
shaft were pointing toward the right, the opposite would be true, Le., the tape would track toward the
casting in the forward direction and away from the casting in the reverse direction.
Figure 5-48 is a flowchart of capstan alignment, summarizing and complementing this alignment procedure. Refer to it while reading this section.
Perform the following steps to align the capstan motor shaft perpendicular to the tape path.
1.

Remove the capstan by loosening the capstan locking clamp with an Allen wrench and
remove the capstan and clamp.
NOTE
If the capstan is hard to remove, it may be bent and
should be replaced. The inside of the capstan should
be checked for burrs in the area of the slots. The end
of the capstan motor shaft should be checked for
burrs also. See Figure 5-38.

5-48

CP~ 1987

Figure 5-38

Location of Possible Capstan Burrs

2. Remove the capstan motor by unplugging PI from the H606 power board and removing the
four bolts holding the capstan motor on the casting.
CAUTION
Because the bolt heads are in front of the casting and
the motor is on the rear, caution should be used so
that the motor does not fall when the screws are
removed.
Do not attempt to remove the tachometer portion of
the motor; the two are replaced as an assembly.
3. Check the capstan motor and casting for the following:

The capstan motor specification template does not interfere with the motor mounting
on the casting. If there is interference, remove the template.

The motor does not have any burrs on the mounting surface that would prevent it from
mounting squarely on the casting.

Ensure that the mounting surface of both the motor and casting are free of dirt, gummy
substances and burrs pushed up by machining operations.

Lift up and remove the vacuum column door.

5. Measure the depth from the outer surface of the left vacuum column to the floor of the left
vacuum column. [Nominal depth = 1.275 cm (0.502 inch).] Call this value "LYC." See
Figure 5-39.
6. Subtract 0.500 from LYC; call the resulting value "X." Record. the value "X," as it will be
used in Step 16.
NOTE
X is the distance that the inside edge of the tape
should be from the floor of the left vacuum column
when the outside edge is 0.051 mm (0.002 inch) from
the outer surface of the left vacuum column. If the
capstan motor shaft is perpendicular to the tape
path, the adjustments described earlier in this section
were performed correctly; X is equal to this distance.

5-49

766()"11

Placement of Depth Micrometer

LEFT
VAC UUM
COLUMN

cp- 19 90

b.
Figure 5-39

Top View of LVe Measurement

Measuring Depth of Left Vacuum Column (L VC)
5-50

7. Remount the capstan motor on the casting (four bolts). Tighten the mounting bolts.
8. Clean the capstan with' a water-dampened Kimwipe or lint-free cloth. Do not use any
cleaner other than water on the capstan.
9. Reposition the capstan on the capstan motor shaft. Tighten the clamp.
10.

Load a good quality tape using the alignment glass (Figure 5-40). It will be necessary to hold
the glass doors with one hand while pressing "LOAD" with the other (Figure 5-41).

IFTHERE IS MASKING TAPE ON
ALIGNMENT GLASS,REMOVE IT
TAPE IS DETRIMENTAL TO
PROPER ALIGNMENT

r-- "-1

1- "-1

2 .7

,I"

>I'

"
'I

:'
::

I'
1/

:'"
"

1411

JI"

1:/,

MATERIAL IS
0.12" THICK
LEXAN

:: ~
"

,I"

I'
II

II
'I
II

'I
,

i.=~..:_-_-:..";..j

b. RIGHT COLUMN GLASS

o. LEFT COLUMN GLASS

CP-\989

Figure 5-40

Alignment Glass

5-51

LEFT COLUMN
GLASS

TAPE

RIGHT COLUMN
GLASS

7660-17

Figure 5-41

Using Alignment Glass to Load Tape

5-52

11.

Ensure that the tape rides in the center of the capstan. This can be done by running the tape
forward several feet and "eyeballing" the tape position on the capstan. The capstan can be
moved in or out to ensure that the tape is in the middle of the capstan. The capstan alignment tool (29-18609) can be used for coarse adjustment. Ensure that the capstan is clamped
securely to the capstan motor shaft.

12.

Align the capstan motor shaft (make it perpendicular to tape path) by placing shims between
the capstan motor mounting face and the casting surface onto which the capstan motor is
mounted. Shims are placed in the vertical axis to correct for capstan steering when both
forward and reverse tape motion produces the same steering characteristic, i.e., tape steers
toward the deck plate or toward the vacuum column glass in both directions. Shims are
placed in the horizontal axis if forward and reverse tape motion show opposite steering
characteristics. Figure 5-42 shows shim placements.
NOTE
A few tips will assist in performing the procedure in
the shortest possible time:
1.

The sequence of tightening the bolts on the capstan motor is important. Each time the bolts are
tightened in a particular procedure, they must
be tightened in the same order. This allows the
procedure to be repeated while keeping the
motor in the exact same position.

The use of sharp scissors on the plastic shim
stock is necessary to keep the edges from curling up. The plastic shim stock sizes are identifiable by the color coding as follows:
0.0254 mm (0.001 inch)
0.0508 mm (0.002 inch)
0.0762 mm (0.003 inch)
0.1016 mm (0.004 inch)
0.1270 mm (0.005 inch)
0.1905 mm (0.0075 inch)
0.254 mm (0.010 inch)

Amber
Red
Green
Tan
Blue
Transparent
Brown
3.

13.

The use of a good quality tape is necessary for
correct capstan alignment. A used or abused
tape does not nm true over the capstan, causing
false readings during the capstan alignment
procedure.

Cut one piece of each type of shim stock as indicated in Figure 5-43. Exact dimensions of
shim stock are not critical; the main idea is to have a manageable size to use as a feeler
gauge. The blunt point shown in Figure 5-43 also minimizes curling of the end that will be
used.

5-53

/
.,/

.--'"

CAP STAN

o. SIDE VIEW

b. FRONT VIEW
Shim placed in horizontal
Qxis when forward an-d
reverse steering are

opposi te.

-+ -t---+--------1f--'1--L-3

9~~+------#__

}
/'"

c. FRONT VIEW
Shims placed in verlical
Qxis when forward and

reverse steering are
similar.

6
cp- 2121

Figure 5-42

Capstan Motor Shim Placement

~I
-I-.

~~BLUNT
/1.1

=====-2-"::::~~~----"i-'

PO I NT

1:1-

CP-1988

Figure 5-43

Capstan Motor Shim

5-54

14.

Run tape forward from BOT for 5 seconds.

15.

U sing shim stock and a penlight, determine the spacing (Y) between the inside edge of the
tape and the floor of the left vacuum column (Figure 5-44). The method of measuring space
Y is shown in Figure 5-45 and is described in Steps a, b, and c below.
a.

Slide the shim stock under the inside edge of tape at the slot between the top of the left
column and capstan.

Shine the light onto the full width of tape while moving the shim stock back and forth;
look for puckering.

Measurement has been obtained when you select a piece of shim stock which causes a
small amount of friction when sliding back and forth, yet no visible pucker.
NOTE
Value "Y" (obtained in Step 15) must be equal to the
value "X" (obtained in Step 6). The tolerance for the
value "Y" is 0.0508 mm (±0.002 inch). In no case
shall "Y" be less than 0.0254 mm (0.001 inch). Continue with the procedure to determine corrective
action.

FLOOR OF LEFT
VACUUM COLUMN
CAPSTAN

"y"
MAGNETIC
TAPE
CP-1985

Figure 5-44

Gap (Y) from Tape to Floor of Left Column

5-55

~"
i I
I

•

7660-15

Figure 5-45

Measurement of Tape Gap (Y) with Penlight and Shim

5-56

16. Run the tape in reverse for 5 seconds. Measure the tape-to-column spacing to obtain value
"Y."

The value "Y" obtained in Step 15 must equal the value "Y" obtained in Step 6, ±0.0254
mm (±0.001 inch).
a.

Basically, the capstan motor must continually be shimmed, as described in Step 12,
until value "Y" is:
G

No less than "X" minus 0.0508 mm (0.002 inch) in forward or reverse [no less
than 0.0254 mm (0.001 inch) in any case.]
The difference between forward and reverse does not exceed 0.0254 mm (0.001
inch).

Shimming is accomplished as follows:
«I

III

No greater than "X" plus 0.0508 mm (0.002 inch) in forward or reverse.

If the tape is too close to the casting in forward and reverse, loosen the motor
mounting bolts, place a shim under the motor adjacent to the bolt at 6 o'clock,
tighten the bolts, and repeat Steps 14, 15, and 16.
If the tape is too far from the casting in both forward and reverse, loosen the
motor mounting bolts, place a shim under the motor adjacent to the bolt at 12
o'clock, tighten the bolts, and repeat Steps 14, 15, and 16.
If the tape is too close to the casting in forward and too far from the casting in
reverse, loosen the motor mounting bolts, place a shim under the motor adjacent
to the bolt at 3 o'clock, tighten the bolts, and repeat Steps 14, 15, and 16.
If the tape is too far from the casting in forward and too close to the casting in
reverse, loosen the motor mounting bolts, place a shim under the motor adjacent
to the bolt at 9 o'clock, tighten the bolts, and repeat Steps 14, 15, and 16.
If measurements meet the criteria stated in Step a, go to Step 17.

The following guidelines should be adhered to:
e

<II

A 0.127 mm (O.OOS-inch) shim is usually a good starting point, but almost any size
shim [up to 0.254 mm (0.010 inch)] may be necessary to accomplish the criteria
stated in Step a.
If a shim size greater than 0.254 mm (O.OIO-inch) is called for, it is advisable to
either rotate the motor mounting 90 degrees and try again or change the motor.

In no case should there be a shim at the two ends of the same axis, e.g., at 3 and 9
o'clock, or 6 and 12 o'clock. If the formula in Step b. calls for a shim to be placed
at 6 o'clock and there is already a shim at 12 o'clock, decrease the shim size at 12
o'clock.

5-57

17.

It is quite normal to have one shim in each of the two axes. In fact, it is desirable,
as this will make the procedure less subject to irregularities due to variations in
bolt tightening sequences (a shim in the vertical axis will allow the motor to rock
in the horizontal axis). For this reason, when you start a shimming session, place a
shim of half the value in the horizontal axis if a shim is placed in the vertical axis
due to the formula in Step a (or vice versa); this is only a time-saving starting
point, and both shims may need adjustment on reruns through Steps 15 and 16.
It is acceptable to use multiple shims under a given bolt to obtain the desired
value, e.g., placing O.127-mm (O.OOS-inch) and O.1016-mm (O.004-inch) shims
together to obtain a O.2286-mm (O.009-inch) shim.

If Steps 15 and 16 seem impossible to accomplish, or if measurements taken in
these steps are inconsistent, see Step 19 for an explanation of capstan and tape
phenomena.

It should be noted that, while a guiding surface exists on the right side of the
capstan (the head plate guides), none exists on the left side (left vacuum column).
This will tend to make forward capstan steering look less severe than reverse. You
will find, therefore, that small differences between forward and reverse are sometimes better corrected by shims in the vertical axis.

Mount a skew tape, and adjust mechanical skew per Paragraph 5.4.2.11.

18. With a skew tape mounted, scoping "PACKET" (E4-Kl), evaluate capstan alignment as
follows:
a.

Run the tape forward looking at the PACKET signal on the scope. PACKET width
must be less than 2.5 J.i,S.

While the tape is running forward, move the upper spring-loaded guide away from the
tape. PACKET width should not increase more than 2 J.i,S. (Take care not to touch
tape.) See Figure 5-46.

CAPSTAN

UPPER
SRING-LOADED
GUIDE

READ/W RITE
HEAD

/
CP-2131

Figure 5-46

Upper Spring-Loaded Guide Location
5-58

While the tape is running forward, look at the tape interface to the upper fixed guide
(use a penlight to reflect light off the tape surface); ensure that no puckering exists.

Run the tape in reverse, looking at the PACKET signal on the scope. PACKET width
must be less than 2.5 J.Ls.

While the tape is running in reverse, move the upper spring-loaded guide away from the
tape. PACKET width must not increase more than 2 J.LS.

While the tape is running in reverse, look at the tape interface to the upper fixed guide;
ensure that no puckering exists.

The following steps describe corrective action that may be taken when necessary:
a.

If the PACKET width increases by more than 2 J.LS in either forward or reverse when
the spring guide is depressed, it should be assumed the tape is running too close to the
casting in that direction of tape travel.

If the tape is puckering on the guide in either forward or reverse, or if the PACKET
width is excessive in forward or reverse, yet does not increase when the upper spring
guide is depressed, it should be assumed that the tape is running too far from the
casting in that direction of tape motion.

If neither a nor b exists, go to Step 19.

If a or b exists, make final shimming corrections according to the procedure in Step
16b.

NOTE
After all shimming is completed in this step, it will be
necessary to verify that the criteria in Step 16a (tapeto-column spacing) are still met.

19.

Run the tape forward. Look in the slot between the inside tape edge and the left vacuum
column floor while the tape is moving forward. If room light is not adequate, shine a penlight through from inside the vacuum column (Figure 5-47).
You should see a constant space (width of light) in this slot as the tape moves forward.
Periodic width change at a very low frequency (less than one per second) is probably due to
tape defects; do not worry about these unless they are very repetitive and cause wide excursions. Higher frequency width changes (5 to 10 times per second) are usually caused by a
bent capstan. If this occurs, it will be necessary to replace the capstan and recheck the tapeto-column spacing with shim stock feeler gauges.

20.

Run the tape in reverse. Check the slot width to the same criteria as in Step 19.

21.

Replace the vacuum column door. Run the skew tape forward and ensure that the PACKET
width does not exceed 2 J.LS. Run the tape in reverse and ensure that the PACKET width does
not exceed 2.5 J.LS. If either criterion fails, suspect roller guide adjustment problem.

22.

To return the tape transport to good working condition now that the tape path has been
aligned, it may be necessary to perform a number of electrical checks and adjustments
(depending on which parts have been replaced in this alignment procedure). Figure 5-48
indicates which checks should be made, and the order in which they should be
accomplished.
5-59

SHINE
LIGHT
HERE IF
NECESSARY

CAPSTAN

LOOK
THROUGH
SLOT HERE

SLOT
TAPE

RIGHT WALL OF
LEFT VACUUM
COLUMN
CP-1986

CP-1984

Front View
Figure 5-47

Right Side View

Capstan Wobble Check

ENTRY POINTS

AOJUST OC BALANCE
TAPE SPEEOQUARTERLY PM
SECTIONS 5.4.2.7
THROUGH 5.4.2.10

CAPSTAN MOTOR
REPLACEO

AOJUST CAPSTAN
RAMPS SEMIANNUAL
PM SECTIONS 5.4.3.1
AN05.4.3.2

HEAO PLATE
ASSEMBLY
REPLACEO

WRITE SKEW AOJUST.
SECTION 5.5.1.7

L
I

NEITHER CAPSTAN
MOTOR NOR HEAO
REPLACEO

PERFORM TRACKING
CHECK, ERASE HEAO
CHECK, REAO AMP
CHECK, RESIOUAL
AMPLlTUOE CHECK,
ON·L1NE ANO EVALUA·
TION NRZ. SEMIANNUAL
PM SECTIONS 5.4.3.3
THROUGH 5.4.3.7

Figure 5-48

Summary, Capstan Alignment Flow Diagram

5-60

5.6 CORRECTIVE MAINTENANCE
Corrective maintenance information is provided to guide and assist the field service engineer when he
is isolating and repairing faults. The information includes five troubleshooting aids:

1.
2.
3.
4.
5.

TMBlljTUlOW Diagnostics
Corrective Action Flow Diagram
Functional Block Diagram
TMBII Troubleshooting
TU lOW Troubleshooting

5.6.1 TMBlljTUlOW Diagnostics
Diagnostics, consisting of a paper tape and documentation, are provided with each system. The documentation includes instructions on loading, running, and interpreting diagnostic printouts. The diagnostics provided with the TMBlljTUlOW are listed and described in Table 5-6. Appendix B contains
the diagnostic documentation without the program listings.
5.6.2 Corrective Action Flow Diagram
Figure 5-49 provides sequential TMBlljTUlOW troubleshooting procedures.

Table 5-6 Diagnostic Descriptions
Number
(MAINDEC-ll-)

Title

Description

DZTMA-*H

TM,A,B-ll/TS03,TUI0,N,W
Instruction Test

A series of basic tests that checks TMB 11 registers for proper operation.

DZTMH-*E

TM,A,B-ll Multidrive Data
Reliability Exerciser

Tests all TMBII/TUIOW functions for evaluation and debugging.

DZTME-*C

TM,A,B-ll/TUIO,W,N
Drive Function Timer

Selected TMBII/TUIOW operations are executed,
timed, and the times are then printed.

DZTMF-*D

TM,A,B-Il/TUIO,N,W
Supplemental Instruction
Test

Four tests that check special data transfers of
the TMBII/TUIOW.

DZTMG-*C

TM,A,B-Il Utility Driver

Executes designated operation regardless of
errors or results.

*Revision level.

5-61

USING UTILITY
DRIVER PROGRAM
ATTEMPT FAILED
OPERATION

YES

RE~RUN

DIAGNOSTIC TO
DETECT FAULT

FAILURE AND
RETURN TO
CUSTOMER

TROUBLESHOOT

USING FLOW AND
TIMING DIAGRAMS
AND DETAIL LOGIC
TROUBLE SHOOT TO FAULTY
COMPONENT

REPLACE FAILED
MODULE OR
MECHANICAL
PART

REFER TO TRANS
PORT TROUBLE
SHOOTING PARA~
GRAPH 5.6.5 AND
DETERMINE FAILED,
MODULE OR PART

FAILED POWER

COMPONENT

SUPPLY

'f'

0\
N
VERI FY SYSTEM
OPERATION USING
DIAGNOSTICS ANO
ONLINE OPERA~

B
FUNCTIONAL
BLOCK DIAGRAM
(FIGURE 1~61
AND TROUBLE
SHOOT TO
FAILED PART

c
11 4671

Figure 5-49

TM B 11 /TU lOW Corrective Action Flow Diagram

5.6.3 Functional Block Diagram
Figure 1-6 functionally separates the circuitry comprising the three major units (TMBll, M8926,
TU lOW) into blocks, depicting signal flow among those blocks within each unit. It also depicts interfacing between each unit and between the TMBll and the Unibus. The functional block diagram
should be used with Figure 5-48 for both troubleshooting and maintenance.
5.6.4 TMBll/TUlOW Troubleshooting Procedures
The diagnostics listed in Table 5-6 test all TMB11 functions. Using the diagnostics while relating to the
functional block diagram (Figure 1-6) is the major aid to be used by the field service engineer in
isolating and repairing equipment faults.
Table 5-7 is a list of possible TUIOW related problems and some hints that may prove helpful when
troubleshooting.
Table 5-7

TUIOW DECmagtape Transport Troubleshooting Hints

Problem

Hints

General

Problems in the TUlOW Transport can usually be classified as either
mechanical or electrical; often, however, the classification may be confusing because a basically mechanical problem can cause what appears
to be an electronic malfunction and vice versa. In any case, the problem
should be thoroughly analyzed before any adjustments are made.
Electronic troubleshooting is greatly facilitated by the modular construction - a new card may be substituted and the effect observed. Most
difficult, of course, are subtle problems and those of an intermittent
nature.
Visualizing solution (Magna-See) is useful under certain conditions for
troubleshooting. At high densities, the data cannot be satisfactorily
resolved, but such problems as a dead track, improper gap length, etc.,
can be isolated rapidly by its use.
If a tape has had visualizing solution applied to it, do not reuse that
portion of the tape, as it will contaminate the head and the remainder of
the tape. Cut the visualized portion off, discard it, and apply a new
BOT marker.
To use visualizing solution, shake the can thoroughly, remove the top,
and pass the portion to be visualized through the solution. Snap the
tape vigorously to remove excess solution and let dry. Iron powder will
be left in magnetized areas. This can be picked off using transparent
tape and then applied to a sheet of paper for a permanent record.

5-63

Table 5-7 TUIOW DECmagtape Transport Troubleshooting Hints (Cont)
Problem

Hints

High Error Rate

Usually the more difficult problems involve a higher than permissible
error rate for which no obvious reason exists. If operating properly with
good tape, the transport should make very few errors in writing and, if
rewriting is included in the program, it should make no read errors.
Useful clues are:
1.

In what mode (read or write) are many errors occurring?

At what point in the block does the error occur?

What is the nature of the error: vertical parity, CRC, LRC?

Are the error patterns related?

Do errors occur only on certain sets of commands?

The first thing to be done is to inspect the head and other items in the
tape path for dirt accumulations. Be sure everything is clean. Check the
tape being used and try a new reel if tape is doubtful. Check the interface connections for broken wires or bad contacts.
Compatibility

The TU lOW Transport accepts and produces tapes conforming to
ANSI standards. Occasionally, compatibility problems can arise:
1.

Tapes written by and acceptable to the TUI0W Transport are not
acceptable to another transport.

Foreign tapes cannot be read by the TUlOW Transport but its
own tapes can be read satisfactorily.

Four items may be involved: skew, speed, ramp times, and tape path
alignment. These should be checked as described in the adjustment procedures (Paragraph 5.5.1).

5.7 REMOVAL AND REPLACEMENT PROCEDURES
This section outlines the removal and replacement procedures for the TMBll/TUlOW DECmagtape
System. The major TUlOW assemblies referenced throughout this section are shown in Figure 5-1.
Table 5-2 lists the tools and equipment required for performing these procedures.
NOTE
The capstan, capstan motor, roller guides, and head
plate directly affect the path of the tape as it moves
through the tape transport. If anyone of these items
requires replacement, an entire tape path alignment
is necessary. Refer to Paragraph 5.5.2.3 for tape
path alignment and for the conditions that require a
tape path alignment.
5-64

5.7.1 Operator Control Panel
To replace burnt-out bulbs in the operator control panel, proceed as follows:
1.

Remove power from the TUIOW Tape Transport.

Loosen the screw at the bottom-center of the control box and remove the panel.

Use a bulb extracting tool (DEC 12-09195-01) to remove and replace defective bulbs.

Mount the panel on the control box and tighten the screw.

The procedure for removing the control box is:
1.

Remove power from the TU lOW Tape Transport.
CAUTION
This procedure should be done carefully, since the
cable damp bracket and control box can both fall
and become damaged.

Disconnect the cable that runs from the rear of the control box to the M8910 module.

Remove the two cable clamp screws.

Loosen and remove the four nuts securing the control box to the casting.

Carefully remove the control box to ensure the connecting cable is not damaged.

Reverse Steps (in order) 5 through 2 to install the control box.

5.7.2 Door Seal (Front Casting Perimeter)
Proceed as follows to replace the door seal along the casting perimeter (Figure 5-2):
1.

Remove power from the TU lOW Tape Transport.

Remove any tape reels to avoid possible contamination of the tape.

Pull the old foam stripping from the front casting.

Remove all adhesive residue from the casting with Freon or another suitable solvent.

Cut the new foam stripping to the proper length before removing the protective backing.

Remove the protective backing from each stdp and carefully press each strip into place
around the casting perimeter.

Close the glass door to ensure correct latching and to ensure against binding the stripping.

5-65

5.7.3 EOT /BOT Assembly
To remove the EaT/BOT assembly, proceed as follows:
1.

Remove power from the TU 10W Tape Transport.

Open the glass vacuum column door.

Use a small screwdriver to loosen the EaT/BOT assembly mounting screw.

Disconnect the wires from the back panel.
Red
Orange
Yellow
Brown

C02A2
C02D!
C02C!
C02D2

Carefully remove the assembly.

Replace the faulty assembly and install by reversing steps 3 through 5.

Check for proper alignment by ensuring that the EaT and BOT markers are sensed; adjust
the assembly if necessary.

5.7.4 Reel Motor Filter Elements
The procedure for replacing the reel motor filter elements (Figure 5-50) is:
1.

Remove power from the TU10W Tape Transport.

Release the service locks and pull the transport out (forward) on the cabinet slides.

Reach in from the left side (as viewed from the front) of the transport and unscrew the filters
from the reel motors (one filter from each motor) ..

Wrap one turn of Teflon tape on the mounting threads of each new filter assembly and screw
them into the servo motors.
CAUTION
Hand tighten only! Do not use a wrench.

5.7.5 Reel Hub Compression Ring and Teflon Washer
Proceed as follows to replace the reel hub compression ring and Teflon washer (Figure 5-51):
1.

Remove power from the TU 10W Tape Transport and remove the tape reel.

Carefully snap out the plastic disk (PN 12-09212-00) from the reel hub.

Mark the position of the center roll pin (PN 90-06526) in the hub guide.

U sing a pair of heavy duty diagonal pliers, carefully remove the center roll pin.

Grasp the reel hub and unscrew the knob from the hub.

Remove (in order) the Teflon washer, pressure plate, and rubber compression ring.

5-66

MOTOR AIR FILTER
{DEC port number
12-09956)

REEL MOTOR

H606
POWER
BOARD

BRAKE
ASSEMBLY
TRANSPORT

o
FEED REEL

~MOTOR AIR FILTER
(DEC port number
12-09956)
10-1300

Figure 5-50

Reel Motors, Rear View

PRESSURE PLATE
ROLL PIN
PLASTIC DISK

STOP PINS

KNOB
TEFLON

WASHER

COMPRESSION RING
10-1303

Figure 5-51

Hub Composition

5-67

Lightly lubricate the flat surfaces of a new compression ring with silicon grease (DEC 9009299). Wipe all excess grease from the ring with a lint-free cloth.

Install (in order) the new compression ring, pressure plate, and a new Teflon washer.

Rotate the knob on the hub until the compression ring is compressed and fully seated.

10.

Loosen the knob until it is free of the Teflon washer. Then gently screw it in until it just
touches the washer.

II.

Reinstall the roll pin in the same hole from which it was removed (Step 4).

12. Turn the knob counterclockwise until the roll pin makes contact with one of the two hub
stop pins (PN 90-06527).
13. Try to install a tape reel on the hub. If the tape reel does not easily slip on the hub, move the
stop pin back one hole at a time until the knob can be released far enough to permit the tape
reel to slip on the hub.
14.

With a tape reel installed, tighten the knob (clockwise) until the roll pin contacts the other
hub stop pin. If the tape reel is not secure, the stop pin must be moved ahead until the knob
can be tightened correctly.

5.7.6 Reel Hub Assembly
Proceed as follows to replace the reel hub assembly (Figure 5-52):

REEL HUB ALI GNMENT
GAUGE #29-18611
(Should feel friction _ _ _-.
in vertical (I) ox is.
Gauge shou I d not move
in horizontal (-) axis.)

TOP
OF
TRANSPORT

MACHINED
ALIGNMENT
BOSS
REEL HUB ALLEN _ _"""'
LOCKING SCREWS (2)

TEFLON

WASHER --;r+--........

3/16 INCH KEY

REEL MOTOR
DRIVE SHAFT

REEL HUB ASSEMBLY

FRONT OF
TRANSPORT - - - - - - - - - '
CP-OI04

Figure 5-52
5-68

Reel Hub

Remove power from the TU lOW Tape Transport and remove the tape reel.

Loosen the two Allen locking screws that secure the reel hub to the reel motor drive shaft.
(Access holes for the locking screws are located on the side of the hub.)

Remove the reel hub assembly, along with the 0.475 cm (3jI6-inch) key (by pulling carefully) and carefully remove any burrs from the motor shaft.

Install a new reel hub assembly and the 0.475 cm (3jI6-inch) key on the motor shaft and,
using the reel hub alignment gauge, set the clearance between the back surface on the hub
assembly and the machined boss on the main casting.

Tighten the two Allen locking screws.

5.7.7 Reel Motor
Ptoceed as follows to remove and replace a reel motor (Figure 5-1):
NOTE
The reel motor brushes are not field replaceable.
1.

Remove power from the TU lOW Tape Transport.

Remove the reel hub assembly. Refer to Paragraph 5.7.6.

Unplug the P3 connector from the rear of the H606 power board.

Remove the pins from the P3 plug and observe that the motor and brake wires are now
disconnected from the connector.

Remove the four captive screws that secure the motor to the deck casting. Remove the
motor.
CAUTION
When removing these four screws, it is necessary to
support the motor from the rear. If support is not
supplied, the motor will fall when the screws are
removed.

Remove the air filter(s) from the motor(s).

Using the brake assembly removal procedure, remove the brake assembly.

Reinstall the brake assembly and air filter on the new reel motor.

Replace the reel motor and tighten the four captive screws to a torque value of 1.13 N -m (10
in-lb ).

10.

Reinstall the reel hub assembly and replace the pins in P3 plug. (Refer to Paragraph 5.7.6.)

5-69

5.7.8 Reel Motor Brakes
If the stator slot is worn away, proceed as follows to remove and replace the reel motor brakes:
I.

Remove power from the TU lOW Tape Transport.

Unplug the brake (P3) connector from the rear of the H606 power board.

Remove the pins (from P3) holding the wires for the particular brake being removed.
Observe that the wires for that particular brake are now disconnected from their respective
P3 pin locations.

Loosen the hub clamp with an Allen wrench and withdraw the clamp, spacer, rotor, rotor
disk, and spring (Figure 5-53).

Remove the four 10-32 screws securing the stator to the reel motor.

Replace the reel motor and secure the stator to the motor assembly using four 10-32 screws.
Ensure that the stator slot is at the 6 o'clock position.

7. Slide the rotor disk, rotor, spacer, and clamp onto the motor shaft. Insert a O.254-mm
(O.OIO-inch) feeler gauge between the stator and rotor disk face and rotate the disk face 360
degrees to obtain the required clearance at all points between the stator and rotor disk face.
8.

Tighten the hub clamp.

Replace the spring as shown in Figure 5-53

10.

Reinsert the brake wires into the brake connector (P3). Insert the connector back in its
correct location on the H606 power board.

NOTE
The armature is driven by three pins on the hub. It is
important that the armature does not bind on the
pins.
5.7.9 Vacuum Switches and Rubber Sleeves
Proceed as follows to replace the vacuum switches andlor rubber sleeves on the switches (Figure 5-54):

Remove power from the TU lOW Tape Transport.

Release the service locks and pull the transport out on the cabinet slides.

Carefully detach the pair of Faston connectors from each switch and note their respective
positions for reassembly purposes.

Remove the switch from the bracket by removing the two 2-56 screws and nuts.

Replace the rubber sleeve on each switch with a 2.22-cm (7/8-inch) length of tubing. Replace
the switch when necessary.

5-70

STATOR MUST
BE MOUNTED
WITH SLOT IN
DOWNWARD
POSITION

REAR VIEW

REEL MOTOR
BRUSH RETAINER

~---SPRING

~_ _ _ GAP

SUCH THAT CLAMP
IS OVER SLOTTED
SECTION OF ROTOR
SLEEVE.

REEL MOTOR

MOTOR SHAFT

P~CLAMP

~3!16" SPACER

"--

ROTOR

ROTOR DISC
STATOR SLOT
' - - - - STATOR
REEL MOTOR
BRUSH RETAINER

DRIVE

SIDE

VIEW
11-4801

Figure 5-53

Reel Motor Brush Locations and Brake Assembly

5-71

MOUNTING SCREW a NUT-~
(2 PER SWITCH)
'""_

LOW OUTLET

RUBBER SLEEVE
(HOSE) -

LOW OUTLET
CP-OI03

Figure 5-54

Vacuum Switches

Mount the switch to the bracket with two 2-56 screws and nuts.
CAUTION
Guide the switch assemblies so each switch sleeve fits
snugly into its respective hole in the casting without
any lateral strain. Never overtighten the screws
securing the vacuum switches to the bracket. Damage to the switch may result.

Reconnect the Faston connectors to all switches.

Operate the transport off-line to verify switch functions.

5.7.10 Vacuum Motor Assembly
Proceed as follows to remove and/or replace the vacuum motor assembly (70-09638-01, 2):
I.

Remove power from the TU10W by turning the circuit breaker on the 861 power control
off.

Slide the transport forward on its slides to facilitate access.

Unplug power connector P9 from J9 at the vacuum assembly from the rear of the cabinet.

Loosen the hose clamp at the vacuum pump and slide the hose off the shroud.

Disconnect the ground wire from the rear of the drive motor.

5-72

While supporting the vacuum assembly from underneath, remove the four screws holding it
to the cabinet. Remove the assembly.

To replace the assembly, reverse steps 3 through 6.

5.7.11 TUIOW Power Supply Regulator Board
To remove and/or replace the TU10W power supply regulator board (Figure 5-1), proceed as follows:

Ensure that power to the TU lOW is turned off; then unplug the TU lOW from its outlet.

Approach the TUIOW power supply from the rear of the TUIOWcabinet.

Remove all connectors (11-J5) from the TUIOW power supply board.

Remove the regulator board cover.

Unplug the three power connections (AC HI, AC LO, and GND) from the bottom left
corner of the regulator board.

Remove the five Phillips head mounting screws and the single Allen mounting screw (Figure
5-7).

Carefully lift the regulator board out of the cabinet.

To reinstall the regulator board, perform Steps 1-7 in reverse.
CAUTION
When replacing a TUI0W power supply regulator
board, apply a thin coat of Wakefield No. 128 compound or Dow silicon grease to the diode pack heat
sink, and ensure that the Allen screw is secured very
tightly. This provides adequate heat flow, and prevents the diode packs from overheating.

Next to the AC HI, AC LO, and GND connector tabs in the lower left corner of power supply
regulator board are three additional tab connectors and two wires. Two of the tabs are marked "lIS";
the other (central) tab is marked "230". If you are operating from a 115 V source, the two wires are
connected to the two outside tabs (marked 115); for 230 V operation, the wires are connected to the
two tabs on the central connector (marked 230).
5.7.12 TUIOW Transformer-Capacitor Assembly (7009636)
The procedure for removing and/or replacing the TUIOW transformer-capacitor assembly (Figure 51) is:
1.

Ensure that power to the TU lOW is turned off; then unplug the TU lOW from its outlet.

If possible, approach the TUlOW transformer-capacitor assembly from the rear of the
TU lOW cabinet. If this is not possible, pull the transport forward on its slides and work
from either side.

Remove connectors 12 and 13 from the TU lOW power supply board.

Remove the regulator board cover.

5-73

Remove the transformer-capacitor assembly cover.

Unplug the three power connections (AC HI, AC LO, and GND) from the bottom left
corner of the regulator board.

Remove the four Phillips head mounting screws that hold the transformer-capacitor
assembly.
NOTE
Do not remove the two Phillips head screws that hold
the transformer-capacitor assembly bracket.

Remove the Phillips head screw holding the ground strap in place.

Carefully lift the transformer-capacitor assembly out of the cabinet.

10. To reinstall the transformer-capacitor assembly, reverse Steps 1 through 8.

5-74

CHAPTER 6
TMBll THEORY OF OPERATION

6.1 INTRODUCTION
The TMBII Controller has three main functions: handling data transfers, issuing control commands,
and monitoring operation of the system.
During data transfer functions, the controller assembles the data word from the magnetic tape and
places it on the bus (read operation) or assembles it from the bus and loads it into the tape transport
read/write heads (write operation) for recording on magnetic tape. The commands necessary to perform the specified operation are generated by the controller under program control.
Normal data word transfers are performed by direct memory access transactions at the NPR level. If
the controller is ready to begin a new function or if an error condition exists, it issues an interrupt
request so that it can be serviced by the program.
In addition to the commands required for data transfers, the controller may issue other commands
governing tape unit selection, direction oftape travel, rewind, space forward, space reverse, write endof-file mark, etc. The controller also monitors various functions and provides an indication of error
conditions. The status of the monitored functions is stored in the status register.
6.2 GENERAL OPERATION
The prime function of the TM B 11 Controller is to control transfers of information so that digital data
can either be taken from the bus and recorded on magnetic tape (write operation) or read from the
magnetic tape and transferred to the bus for use by another device such as memory (read operation). In
addition, the controller performs tape transport selection, tape positioning, tape formatting, and system monitoring functions.
The controller contains a command register, which allows the program to specify desired operations
by loading control data (transport selection, packing density, function, etc.) into the register. System
status information (end-of-tape, errors, tape unit ready, etc.) is loaded into a status register, which can
be read from the bus.
Data transfers are controlled by a byte record counter (MTBRC) and a current memory address
register (MTCMA). The program loads the byte record counter with the 2's complement of the desired
number of data transfers. The counter is incremented before each transfer; therefore, the byte transfer
that causes the byte count overflow (MTBRC becomes zero) is the last transfer to take place. The byte
counter is also used to count the number of records during space forward and space reverse operations.
The current memory address register is also incremented before each transfer and, therefore, always
points to the next higher address than the one most recently accessed. Thus, when the entire record is
transferred, the register contains the address plus 1 of the last character in the record. For certain error
conditions, the register contains the address of the location in which the failure occurred.

6-1

6.2.1 Read
During read operations, the controller assembles bytes from successive characters read from the tape
channels. When reading a 7-channel tape, the 6 data bits are assembled in a data buffer register for
temporary storage. The parity bit is read but not loaded into memory. Because the PDP-II uses 8-bit
bytes, the remaining 2 bits in the buffer are forced to O. When the byte is assembled, it is placed on the
bus for transfer to memory. If an NPR transfer is used, bytes from the data buffer are alternately
stored into the low and high byte portions of memory.
When reading 9-channel tape, operation is identical except that 8 data bits are assembled. It is not
necessary to force any bits to 0, because the 8 data bits constitute a complete PDP-II byte. In the case
of both 7-channel and 9-channel tapes, the parity bit can be loaded into the data buffer but is not
loaded into memory.
!
I

When reading 9-channel tapes, either the CRC character or the LRC character at the end of a record is
stored in the data buffer, depending on the state of bit 14 in the MTRD. If this bit is 0, the CRC
character is loaded into the data buffer and can be used for error detection. If the bit is 1, then the data
buffer contains the LRC character at the end of the record. When reading a 7-channel tape, bit 14 in
the MTRD operates in a similar manner. If bit 14 is set, the LRC character is present, and when bit 14
is cleared, the last data character is present in the data buffer.
6.2.2 Write
During write operations, the controller disassembles 8-bit bytes from the bus and distributes the bits so
that they can be recorded on successive frames of the tape. The controller selects one of three recording
densities (200, 556, or 800 bpi) for 7-channel tapes. All 9-channel tapes are written at a density of 800
bpi. There are three possible write functions: write, write-with-extended-IRG, and write end-of-file
(EOF) mark.
When a write function is selected, the program loads the byte record counter with the 2's complement
of the n umber of bytes to be written in the record. Although the parity bit is generated by the master
tape transport, the polarity of the bit is determined by the controller so that either odd or even parity
can be selected. When the buffer is loaded, the controller transmits the byte to the master tape transport, which places the byte on the read/write heads of the selected slave transport so that data can be
written on the magnetic tape.
The write-with-extended-IRG function is identical to the write function except that a 3-in. gap, rather
than the normal gap is used between records. When this function is selected, a 3-in. segment of tape is
erased before writing begins.
The write end-of-file (EOF) function is used to indicate that a block ofrecords is complete. When this
function is selected, a special EOF character is written on the tape followed by an LRC character. In 7channel mode the EOF and LRC characters are octal 17. In 9-channel mode the EOF character (and
the LRC character) are octal 23. These two characters constitute a complete record. This command
causes a 3-in. gap to be placed before the EOF mark. The XIRG command must be absent to have this
gap written.
6.2.3 System Monitoring
System monitoring functions are performed by the controller status register. The 16 bits in this register
retain error and tape status information. Some status data is combined, such as lateral and longitudinal parity errors, or has a combined meaning, such as illegal command, for optimum use of the
available bits. The status register only monitors the tape transport selected by the command register;
therefore, other units that may be rewinding do not interrupt the system when ready for data.

6-2

6.2.4 Interrupts
The TMBII Controller uses NPR or BR interrupts to gain control of the bus in order to perform data
transfers or to cause a vectored interrupt, thereby causing a branch to a handling routine. The NPR
requests are used for direct memory access whenever it is desired to transfer data between memory and
the data buffer register without processor intervention. The BR requests are made when processor
servicing is required for completed operations or error conditions.
6.2.4.1 NPR Requests - The controller issues an NPR request whenever it is necessary to transfer
data between memory and the data buffer register. During a read operation, the direction of transfer is
from the data buffer to the core memory. The RDS pulse (read strobe, from master tape transport to
controller), which is used to strobe data from the tape transport into the data buffer register, generates
the NPR request. When the request is granted, the controller performs a DATOB bus cycle and
transfers information from the data buffer into memory.
During a write (or write-with-extended-IRG) operation, the NPR request is generated by the write
strobe (WRS) pulse from the transport. When the request is granted, the controller performs a DATI
bus cycle and transfers a byte from core memory into the data buffer register.
During both read and write operations, the address in memory that data is read from or loaded into is
determined by the value in the current memory address register (MTCMA).
6.2.4.2 BR Requests - A BR interrupt can occur only if the interrupt enable (INT ENB) bit in the
command register is set. With INT ENB set, setting the CU RDY bit in the command register, or
completing a rewind operation initiates an interrupt request.
When CU RDY is set, it indicates that the controller is ready to perform another command.
When ERR is set, it indicates that some type of error condition exists. In this case, an interrupt is used
to cause the program to branch to an error handling routine.

If a function command is issued with the GO bit cleared and INT ENB set, an interrupt is initiated.
If the selected tape unit (as indicated by the SEL bits in the command register) completes the rewind
operation before a new command to that unit is received and INT ENB is set, an interrupt is initiated.
If the interrupt is enabled (lNT ENB set) and selection of the tape unit is not changed (as indicated by
the SEL bits), then a rewind command causes two interrupts: an interrupt when the rewind function
begins and an interrupt when the tape unit completes the rewind function. If, however, the tape unit is
already at the BOT marker when rewind is issued, only one interrupt occurs.
6.3 FUNCTIONAL BLOCK DIAGRAM DESCRIPTION
The TMBII flow diagram (Figure 6-1) provides a brief functional description of the controller. This
diagram should be read in its entirety while referencing the controller functional block diagram, Figure
6-2.
6.4 TMBll REGISTERS
All software control of the magtape system is performed by means of six device registers within the
controller. These registers have been assigned bus addresses and can be read or loaded using any PDP11 instruction that refers to their address. The six device registers are listed in Table 6-1. The register
addresses are determined by jumpers on the MI05 address selector module. Any programs that refer to
these addresses must be modified accordingly if the jumpers are changed.

6-3

START

)

~
PROCESSOR ADDRESSES TMBl1 REGISTERS

•

PROCESSOR LOADS TMB11 REGISTERS:

1. LOADS BYTE/RECORD COUNT REGISTER WITH
NUMBER OF BYTES TO BE TRANSFERRED.
2. LOADS CURRENT MEMORY ADDRESS REGISTER
WITH FIRST MEMORY ADDRESS INVOLVED IN
TRANSFER.
3. CMA BIT OOSELECTS LOW DATA BYTE OF
SELECTED MEMORY LOCATION.
4. LOADS COMMAND REGISTER WITH DESIRED
FUNCTION, DESIRED TRANSPORT AND GO BIT.

COMMAND REGISTER ESTABLISHES OPERATION
PARAMETERS;
1. ASSERTS SELD-SEL2 TO SELECT DESIRED

TRANSPORT.
2. SENDS FUNCTION COMMAND TO COMMAND
DECODER WHICH ASSERTS COMMAND TO

TRANSPORT.
3. ASSERTS GO BIT TO ENABLE START
OPERATION LOGIC.

START OPERATION LOGIC INITIATES

OPERATION:
1. CHECKS THAT TRANSPORT IS SELECTED
AND ON LINE (SELR).
2. CHECKS THAT TRANSPORT IS STOPPED
AND READY TO START AN OPERATION
(TUR).
3. ASSERTS SET TO TRANSPORT TO START
THE OPERATION.

•

READ OPERATION

WRITE OPERATION

•

GO BIT REQUESTS AN NPR
TRANSFER FROM NPR LOGIC

TRANSPORT ASSERTS RDS WHEN DATA
(RDO-RD7, RDP) IS READY TO BE TAKEN

l
I l

TRANSPORT ASSERTS WRS
WHEN READY TO

RECEIVE DATA

WRS REQUESTS AN NPR
TRANSFER FROM NPR LOGIC

I
I

RDS:

NPR LOGIC:
1. ASSERTS NPR TO BUS.
2. RECEIVES NPG FROM BUS.
3. ASSERTS BBSY AND MSYN TO BUS.
4. RECEIVES SSYN FROM SLAVE INDICATING
DATA IS ON UNIBUS READY TO BE RECEIVED.
5. ASSERTSDATASTB2TOTAKEDATAFROM
BUS.

1. LOADS RDO-RD7 DATA FROM TRANSPORT
INTO DATA BUFFER VIA READ/WRITE MUX.
2. REQUESTS AN NPR TRANSFER FROM NPR
LOGIC.

!
NPR LOGIC:
1. ASSERTS NPR TO BUS.
2. RECEIVES NPG FROM BUS.
3. ASSERTS BBSY AND MSYN TO BUS.
4. ASSERTS DATA-BUS TO ENABLE EITHER
LO DATA BYTE OR HI DATA BYTE.

DATA STB 2 LOADS INPUT DATA BYTE INTO
DATA BUFFER VIA EITHER HI BYTE GATE OR
LO BYTE GATE, AND READ/WRITE MUX. DATA
NOW AVAILABLE TO TRANSPORT AS WDO-W07.

e)
1,-4144A

Figure 6-1

TMB 11 Flow Diagram (Sheet 1 of 2)

6-4

DATA BYTE IN DATA BUFFER TRANSFERRED TO
UNIBUS VIA EITHER HI BYTE GATE OR LO BYTE
GATE.

NPR LOGIC ASSERTS NPR CLEAR BBSY

NPR CLEAR BBSY:
1. INCREMENTS CMA REGISTER TO NEXT
MEMORY LOCATION FOR NEXT DATA
TRANSFER. CMA BIT 00 TOGGLES WRITE
BYTE SELECT LOGIC TO ASSERT ALTERNATE
BYTE SELECT SIGNAL.
2. INCREMENTS BYTE/RECORD COUNTER.

NPR LOGIC:
1. RECEIVES SSYN FROM SLAVE INDICATING
DATA HAS BEEN RECEIVED.
2. ASSERTS NPR CLEAR BBSY TO INDICATE NPR
TRANSFER IS COMPLETED.

NPR CLEAR BBSY:
1. INCREMENTS CMA REGISTER TO NEXT MEMORY
LOCATION FOR NEXT DATA TRANSFER. CMA
BIT 00 TOGGLES WRITE BYTE SELECT LOGIC TO
ASSERT ALTERNATE BYTE SELECT SIGNAL.
2. INCREMENTS BYTE/RECORD COUNTER.

YES

WRITE DATA READY LOGIC NEGATES WDR TO
TRANSPORT INDICATING END OF WRITE OPERATION.

YES

TRANSPORT WRITES LRC CHARACTER AND ISSUES
LRCS STROBE TO TMBll.

LRCS STROBE OR ABORTIVE ERROR ENABLES DONE
LOGIC ASSERTING DONE DELAYED TO BUS INTERRUPT
LOGIC.

BUS INTERRUPT LOGIC:
1. ASSERTS BUS BRX" TO UNIBUS.
2. RECEIVES 8US BGX· FROM UNIBUS.
3. ASSERTS BBSY AND BUS INTR TO UNIBUS.
4. ASSERTS VECTOR ADDRESS FOR PROCESSOR
INTERVENTION (NEW COMMAND, ETC.).

Figure 6-1

·X = 4, 5, 6 OR 7

TMBll Flow Diagram (Sheet 2 of 2)

6-5

COMMAND
DECODER
M7911
DATA BFR
OUT BIT {IJ-7

OPERATION PARAMETERS
BYTE/RECORD COUNT
16 STATUS BITS

BUS
INTERRUPT
LOGIC

READ

CURRENT MEMORY ADDRESS

WRITE
M7821

WDR

WRITE
CARRY OUT 2
SEL lOUT
COMMAND
REGISTER
(REG I)
~______~M~79~1~1r----t-t-t-t-------------------------------

DONE LOGIC

LRCS

DATA BUFFER
(REG 4)
CARRY OUT 2
DATA BFR IN
BIT {IJ-7
SEL 2 OUT

NPR
LOGIC

BYTE/RECORD
COUNT
REGISTER
(REG 2)

TO TAPE
TRANSPORT

RDS (READ LOAD)

M795
CHAN {IJ-CHAN 7,

M796/M7821
STATUS
REGISTER

ERR (1)

M7911

ERROR
LOGIC
M7911

FMK
\

CRCS
\

LRCS
\

BUS A{IJ{IJ-AI8
CMA
REGISTER
(REG 3)

WRITE BYTE
SELECT

SEL LO BYTE

VPE
\CRCE
\ LRCE

HI BYTE

M7912
M795
BYTE
BYTE
Ml05/M7912

EOT
\W,RL

M7912

'\SDWN

RWS

\iiQi
7 CH

08-1736

Figure 6-2

TMBII Functional Block Diagram
6-6 .

Table 6-1

Device Register Functions

Address

Mnemonic

Function

Status Register

772520

MTS

Provides detailed information on the status of the
controller. Such information includes error
indications and tape unit status indications.

Command
Register

772522

MTC

This is the main control register in the controller.
Specifies the operation to be performed on the tape
unit, selects the tape bit packing density, and
selects the tape unit to be used.
Indicates when the controller is ready, when an
error condition exists, and when the controller is
cleared.
Provides the two extended address bits for bus
addresses.

Byte Record
Counter

772524

MTBRC

Counts the number of bytes in any write operation,
the number of records in a space forward or space
reverse operation, and the number of bytes in a
read operation. Desired byte count is preset by the
program. When the register counts the number of
specified bytes, it prevents further transfers.

Current Memory
Address Register

772526

MTCMA

Specifies the bus or memory address to or from
which data is transferred during read and write
operations. After each transfer is completed, the
register is automatically incremented by I (next
byte location).
When BOL or NXM errors occur, the register contains the address of the location in which the failure occurred.
Note that this register is incremented by 1, and
therefore, accesses byte, rather than word,
locations.

Data Buffer
Register

772530

MTD

Contains the information read from or written on
the tape. Serves as a buffer between the tape unit
and the memory.

Tape Unit
Read Lines

772532

MTRD

Permits storage of data read from the tape transport. A parity bit indicates the occurrence of a parity error and the channel containing the error.
A character selector bit is used to select the last
character of a record that is to be loaded into the
data buffer register.
A timer bit is used for diagnostic purposes by
measuring the time duration of the tape
operations.
A BTE/OPI bit is used to set transfer done prematurely in order to provide a bad tape error
indication.

6-7

Figures 6-3 through 6-9 show the bit assignments within the six device registers. Except in the case of
the data buffer register, the "unused" and "load only" bits are always read as Os. Loading "unused" or
"read only" bits has no effect on the bit position.
The mnemonic INIT refers to the initialization signal issued by the processor. Initialization is caused
by one of the following: issuing a programmed RESET instruction; depressing the START switch on
the processor console; or occurrence of a power-up or power-down condition of either the processor
power supply or the controller power supply.
The INIT signal clears the entire system; however, the INIT signal produced by a RESET instruction
does not clear the processor. Clearing only the controller and the tape units can be accomplished by
loading a 1 into bit 12 (POWER CLEAR) of the command register (MTC).
NOTE
INIT and POWER CLEAR deselect the current
tape unit and select tape unit O. Also, a rewind operation in progress continues to the load point.
6.4.1 Status Register (MTS)
Address = 772520. All bits are read only.

11-0430

Figure 6-3

Status Register (MTS) Bit Assignments

Bit

Meaning and Operation

ILC - Illegal command bit. Indicates an illegal command. This bit is set whenever one
of the following illegal commands occur:
a.

Any DATa or DATOB transfer to the command register (MTC) during tape
operation (CU RDY bit clear). The register cannot accept a new command
while in the process of executing another command.

A write, write end-of-file, or write-with-extended-IRG (command register
functions 2, 3, and 6, respectively), when the WRL (write lock) bit is set.
Writing is inhibited with WRL set, and write commands are illegal.

Any command to a tape unit that has its SELR bit clear is illegal, because
SELR clear indicates that the unit is not on-line.

Any time the SELR bit becomes 0 during any operation except off-line, it
sets the ILC bit, because no command can be issued to a unit that is not online.

If any of the illegal commands listed in a through c above occur, the command is
loaded into the command register.
In all of the above cases, the ILC bit and the ERR bit (bit 15 in the command register)
are set simultaneously.
Cleared by INIT or by the GO pulse to the tape unit.
6-8

Bit

Meaning and Operation

EOF - End-of-file bit, used to indicate that the tape has reached the end of the file. An
end-of-file (EOF) character is detected during a read, space forward, or space reverse
operation. During the read or space forward operations, the EOF bit is set when the
EOF character is read. During a space reverse operation, the EOF bit is set when the
LRC character following the EOF character is read. The ERR bit (bit 15 in the command register) is set when the LRC character following the EOF character is detected.
It is also set during WRITE EOF command.
The EOF bit is set only by the tape unit logic; it is cleared by INIT or by the GO pulse
to the tape unit.
The EOF character is loaded into memory during read operations.

eRE - Cyclic redundancy error bit. A cyclic redundancy error can be detected during
either a read or write operation. This check compares the CRC character, written on a
9-channe1 tape during a write or a write-with-extended-IRG operation, with the CRC
character generated during a read operation.

If the two CRC characters are not the same, the CRCE from the tape unit becomes a 1,
forcing the CRE bit to a 1. The ERR bit in the command register, however, is not set
until the LRC character is detected.
Cleared by INIT or by the GO pulse to the tape unit.

PAE - Parity error bit. When set; this bit indicates that a parity error exists. The PAE
bit is the logical OR of both vertical and longitudinal parity errors.
A vertical parity error is indicated on any character in a record; a longitudinal parity
error occurs only after the LRC is detected.
A vertical parity error does not affect the transfer of data. In other words, the entire
record is transferred to the tape during a write operation or transferred into memory
during a read operation.
Both vertical and longitudinal parity errors are detected during read, write, and writewith-extended-IRG operations. The entire record is checked, including the CRC and
LRC characters.
Longitudinal parity occurs when an odd number of Is is detected on any channel in the
record. Vertical parity error occurs when an even number of 1s is detected on any
character, provided the PEVN bit (bit 11 in the command register) is clear, or if an odd
number of Is is detected when the PEVN bit is set.
When a parity error occurs, P AE is set, and the ERR bit (bit 15 in the command
register) is set after the LRC character has been detected.
Cleared by INIT or by the GO pulse to the tape unit.

6-9

Bit

Meaning and Operation

BGL - Bus grant late bit. If the controller issues a request for the bus and does not
receive a bus grant before it must issue another bus request for the following tape
character, a bus grant late error occurs.
This error condition is tested only for NPRs (non-processor requests). The BGL bit is
set if an NPR bus request is not honored before the controller receives a WRS pulse for
a write operation or an RDS pulse for a read operation.
The BGL bit and the ERR bit (bit 15 in the MTC) are set simultaneously, halting the
operation.
If the BGL error occurred during a write or write-with-extended-IRG operation, the
controller does not send the WDR signal to the master tape unit to allow the master
tape unit to write data characters on the tape.
Cleared by INIT or by the GO pulse to the tape unit.

EOT - End-of-tape bit. The EOT bit is set as soon as the EOT marker is detected, when
the tape is moving in the forward direction. It is cleared as soon as the EOT marker is
detected, when the tape is moving in the reverse direction.
The EOT is an error condition if the tape is moving forward. Therefore, when EOT is
set, ERR bit is also set when the LRC character is read.
Cleared by tape transport head passing over EOT marker when tape is moving in the
reverse direction.

RLE - Record length error bit. The record length error is tested only during read
operations. An error is indicated as soon as the byte record counter (MTBRC)
attempts to increment beyond O.
When a record length error occurs, the RLE bit is set, incrementation of the MTBRC
and the current memory address register (MTCMA) ceases, and the ERR bit is set
when the LRC character is read.
The CU RDY (bit 07 of the command register) remains cleared until the LRC character is read a t which time CU RDY is set.
Cleared by INIT or by the GO pulse to the tape unit.
If the exact record length is desired following the occurrence of a record length error, it
can be found by setting the MTBRC to a value so large as not to generate an RLE and
re-reading the record. Record length can be derived by subtracting the current value of
the MTBRC from its initial setting.

6-10

Hit

Meaning and Operation

BTEjOPI - Bad tape error operation incomplete bit. A bad tape error occurs when a
character is detected (RDS pulse) during the gap shutdown or settle down period for
any tape function except rewind.
During write, write EOF, or write-with-extended-IRG operations, a bad tape error sets
both the BTEjOPI and ERR bits immediately on detecting the error.
During both read and space forward or space reverse operations, the BTEjOPI bit is
set immediately on detection of bad tape.
During a read operation, the MTBRC increments continuously and words are read
into memory until the MTBRC overflows. During a space operation, the MTBRC
stops incrementing as soon as BTE occurs. When BTE is discovered, the tape unit
stops, regardless of the state of the MTBRC.
Because it is not possible to artificially generate bad tape, bad tape may be indicated by
setting the CU RDY bit prematurely, thereby producing the gap shutdown period
while the data is still being read. The CU RDY bit is set by loading a 1 into bit 13 ofthe
MTRD. If bit 13 of the MTRD is set during a record for either a read or write operation, a bad tape error indication occurs.
Any initiated tape operation other than a REWIND or OFF-LINE command that
does not detect an LRC character within seven seconds results in setting the BTEjOPI
bit. This 7-second time-out is called Operation Incomplete. Any legal size record with a
legal size gap results in detection of an LRC character within seven seconds. During a
spacing operation, the OPI timer is restarted at each interrecord gap. When the 7second time-out occurs, the tape unit in operation is RESET by CINIT. The BTEjOPI
bit is set and at TUR the CU RDY bit is set.
Cleared by INIT or GO.

NXM - Nonexistent memory bit. This error condition occurs when the controller is bus
master during NPR transfers and does not receive an SSYN response within 20 JlS after
asserting MSYN.
The NXM bit and the ERR bit are set simultaneously, halting the operation.
Cleared by INIT or by the GO pulse to the tape unit.

SELR - Select remote bit. The SELR bit is set when the tape unit has been properly
selected. The SELR bit is 0 if the tape unit that is addressed does not exist (UNIT
SELECT setting does not correspond to SEL bits), if the selected tape unit is off-line
(ON-LINEjOFF-LiNE switch set to OFF-LINE), or if the tape unit power is off:

BOT - Beginning-of-tape bit. The BOT bit is set as soon as the BOT marker is detected.
When BOT is set, it has no effect on the ERR bit. The BOT bit remains cleared whenever the BOT marker is not being read.
This bit is set and cleared only by the tape transport.

6-11

Bit

Meaning and Operation

7CH - 7-channel bit. This bit is cleared or set by the tape transport to indicate whether
a 7 -channel or 9-channel tape is being used.
When 7CH bit is set, it indicates a 7-channel tape; when it is clear, it indicates a 9channel tape.
The 7CH bit is also used in conjunction with the DEN 8 and DEN 5 bits in the command register to cause the core dump mode of operation. When the 7CH, DEN 8, and
DEN 5 bits are all set, the core dump mode of operation is used.

SDWN - Settle down bit. The settling down period is provided to allow the tape to
fully stop prior to starting a new operation. This settling down period sets the SDWN
bit. When the tape unit stops, SDWN is cleared, and the tape unit ready (TUR) bit is
set.
During a tape reverse operation (this does not include rewind operations), the gap
shutdown period begins immediately after the first gap encountered after spacing over
a record.

WRL - Write lock bit. The write lock bit is under control of the tape transport. When
set, it prevents the controller from writing information on the tape.

RWS - Rewind status bit. This bit is under control of the tape unit. It is set at the start
of a rewind operation and clears as soon as the rewind sequence is complete.

TUR - Tape unit ready bit. This bit is under control of the tape transport. Whenever
the selected tape unit is being used (such as rewind), this bit is cleared. When the tape
unit is stopped and ready to receive a new command, the tape transport sets the TUR
bit.

NOTE
Status register bits 00 - 05 are cleared or set by the
tape transport, not the controller.
6.4.2 Command Register (MTC)
Address = 772522. Bit 07 is read-only. All others are read/write.

Figure 6-4

Command Register (MTC) Bit Assignments

6-12

Bit

Meaning and Operation

ERR - I ndicates an error condition that is the inclusive OR of all error conditions (bits
15 - 07 in the Status Register, MTS). Causes an interrupt if enabled (see bit 06). The
ER R bit is not set for some errors until the longitudinal redundancy check (LRC)
character is read, in order to allow the current operation to be completed. Specific error
conditions are described in the status register bit assignments (Figure 6-3).
When ERR is set, it sets bit 07 (CU RDY) when the tape unit asserts TUR.
Cleared by INIT or by the next GO command (bit 00).

DEN 8 - This bit, in conjunction with bit 13, selects the bit packing density of the tape.
These combinations are shown below. Note that this bit, in conjunction with DEN 5
and 7CH in the MTS, can be used to select the core dump mode for 7-channel tape.
Bit 14
(DENS)

Bit 13
(DEN 5)

Density
(bpi)

200

556

1
1

800

}

7 -channel tape
9-channel tapej7-channel core dump

DEN 5 - This bit, in conjunction with bit 14, selects the bit packing density of the tape.
See bit 14 above for combinations.

PWR CLR - When a 1 is loaded into this bit position, it clears the controller logic and
all tape units. This bit becomes a 1 for 1 p.s during a processor DATO cycle, provided
the corresponding bit on the bus is a 1. Always read by processor as a O.

PEVN - This is the even parity bit. This bit is set whenever the selected tape unit is to
write or read even vertical parity on or from the tape. The bit is 0 whenever the selected
tape unit is to write or read odd vertical parity on or from the tape.
A search for parity error is made whenever the tape moves. The controller ignores
parity errors during space forward, space reverse, or rewind operations.
Cleared by INIT or by loading with a O.

10-08

SEL - These three unit select bits specify the number of the tape unit that is to function
as the unit under program control. These three bits (SEL 2, SEL 1, and SEL 0) are set
or cleared to represent an octal code that corresponds to the unit number of the tape
unit to be used. The tape unit number is selected by the UNIT SELECT plug on the
tape transport.
Cleared by INIT or by loading with a O.

6-13

Bit

Meaning and Operation

CU RDY - When set, indicates that the controller is ready to receive a new command.
This bit is set at the end of a tape operation (indicating that a new operation can be
started) and is cleared at the beginning of a tape operation (indicating that the controller is not ready for new commands).
This bit is also set (indicating CU RDY) whenever ILC (bit 15 of MTS) is set or
whenever INIT is generated.

INT ENB - Interrupt enable bit. This bit, when set, allows an interrupt to occur, provided either CU RDY (bit 07) or ILC (bit 15 of MTS) is set. With INT ENB set, a
REWIND command can cause two interrupts - one at initiation and one at
completion.
An interrupt also occurs whenever an instruction sets the INT ENB bit but does not set
the GO bit (bit 00). Interrupts are described in Paragraph 6.2.4.
Cleared by INIT or by loading with a O.

ADRS BIT 17 - Extended bus address bit 17. Used to specify address line 17 in direct
memory transfers. Increments with the current memory address register (MTCMA).
Cleared by INIT.

ADRS BIT 16 - Extended bus address bit 16. Function is the same as ADRS BIT 17
(bit 05 above).

03-01

FUNCTION - These bits specify a command to be performed by the selected tape unit.
These functions are:
Octal No.

Function Bits
03
02
01

1
2
3
4
5
6
7

0
0
1
1
1
1

0
0
I
I

0
1

0
1
1

1
1

Function
Off-line
Read
Write
Write end-of-file
Space forward
Space reverse
Write-with-extended IRG
Rewind

All function bits cleared by INIT.

GO - Loaded with a 1 from the bus to initiate the function selected. Clears CU RDY
bit.
Cleared when GO pulse is sent to tape transport. Normal time duration of bit is 1 J,LS,
but this time may extend to as long as several minutes in the case where the bit is loaded
for a tape unit that is in the process of rewinding.
Also cleared by INIT or cleared whenever ILC in the status register is set.
6-14

6.4.3 Byte/Record Counter (MTBRC)
Address = 772524. All bits are read/write.
15

00
2's

COMPLEMENT OF NUMBER OF BYTES (OR RECORDS) TO BE COUNTED
t 1-0432

Figure 6-5

Byte/Record Counter (MTBRC) Bit Assignments

Bit

Meaning and Operation

15-00

Contains the 2's complement of the number of bytes or records to be transferred. The
desired value is loaded by the program on a processor DATO. Cleared by INIT.
Increments by 1 after each memory access.
The byte record counter (MTBRC) is a 16-bit binary counter used to count bytes in a
read or write operation and used to count records in space forward or reverse
operations.
When used in a write or write-with-extended-IRG operation, this register is set by the
program to the 2's complement of the number of bytes to be written on the tape. After
the last byte of the record has been strobed from memory, the MTBRC becomes o.
Thus, when the next write strobe signal is received from the master tape transport, the
controller lowers the write data ready line to indicate to the master transport that there
are no more data characters in the record.
When used in a read operation, the MTBRC is set to a number equal to or greater than
the 2's complement of the number of words to be loaded into memory. A record length
error, which occurs for long records only, occurs whenever a read pulse is generated
after the MTBRC is at O. Neither the CRC or LRC character is loaded into memory
during a read operation, although both characters are checked for parity errors.
When used in a space forward or space reverse operation, the MTBRC is loaded with
the 2's complement of the number of records to be spaced. The counter is incremented
by 1 at LRC time, regardless of tape direction.

6.4.4 Current Memory Address Register (MTCMA)
Address = 772526. All bits are read/write.
00

15
BUS

ADDRESS
11-0433

Figure 6-6

Current Memory Address Register (MTCMA) Bit Assignments

6-15

Bit

Meaning and Operation

15-01

These bits specify the bus or memory address to or from which data is to be transferred
during write or read operations. Only bits 01-15 of the MTCMA are accessible by the
program, although bits 00-15 participate in NPR transfers. Bit 00 always starts in the
cleared or even byte state because all NPR transfers access even boundaries for a starting byte address. Therefore, MTCMA must be initially loaded with an even
address.The MTCMA contains 16 of the possible 18 memory address bits. The remaining two bits (16 and 17) are part of the command register.
Before issuing a command, the program loads the MTCMA with the memory address
that is to receive the first byte of data (read operation) or with the memory address
from which the first byte is to be taken (write operation). After each memory access
(read or write), the MTCMA is immediately incremented by 1 (the next byte boundary). Therefore, at any given time, the MTCMA points to the next memory byte
address that is to be accessed. On completion of the record transfer, the MTCMA
points to the address plus 1 of the last character in the record.

If a bus grant late (BGL) or nonexistent memory (NXM) error occurs, the MTCMA
contains the address of the location in which the failure occurred.
If an 18-bit memory address is required, the program loads the appropriate address
into bits 01-15 of the MTCMA and into extended address bits 16 and 17 of the command register. The extended address bits are a logical extension to the MTCMA register and participate in any required incrementation.
6.4.5 Data Buffer Register (MTD)
Address = 772530. All bits are read/write.
08

00
DATA
11-0434

Figure 6-7

Bit

Data Buffer Register (MTD) Bit Assignments

Meaning and Operation

15-09
(not shown)

Correspond to bits 07-01 respectively on a processor DATI cycle.
Example: Bit 15 = bit 7, bit 14 = bit 6, etc.

Correspond to the parity bit of the CRC and LRC characters. During a processor read
operation, this bit is stored in memory. During NPR operations, this bit is read by the
controller but not loaded into memory. If the CHAR SEL bit (bit 14) of the read lines
register is aI, bit 08 is the parity bit of the LRC character. If the CHAR SEL bit is 0,
bit 08 is the parity bit of the CRC character (9-track only).

6-16

9 TRACK TAPEFULL 8-81T BYTES ARE RECORDED ON TAPE.
15

I I

7 TRACK TAPEONLY 6 BITS OF EACH B-BIT BYTE ARE RECORDED
ON TAPE.BITS 6,7,14,AND 15 ARE NOT USED.

04
B

00
A

7 TRACK TAPE (CORE DUMP)FULL 8-BIT BYTES ARE RECORDED ON TAPE
BY USI NG TWO 4-BIT CHARACTERS

READ/WRITE
HEAD

11- 2061

Figure 6-8

Relationship Between Tape Characters and Memory Byte Characters

Bit

Meaning and Operation

07-00

During read operations, these bits are used for temporary storage of characters read
from tape prior to loading into memory. During write operations, these bits are used
for temporary storage of data from memory before writing on tape.
During read operations, the LRC character enters the data buffer when bit 14 of the
address location for the read lines register is a 1; the LRC character is prevented from
entering the data buffer when bit 14 is a O. Thus, after reading a 9-channel tape, the
data buffer contains an LRC character (if bit 14 is a 1) or a CRC character (if bit 14 is a
0). After reading a 7-channel tape, the data buffer contains either the LRC character (if
bit 14 is a 1) or the last data character (if bit 14 is a 0). After reading an EOF character,
the data buffer contains either all Os (bit 14 is a 1) or the EOF character (bit 14 is' a 0).
The data buffer can store only bytes; therefore, two bus cycles are required to transfer a
word. During NPR operation the data bits are written into or read from alternate low
and high byte positions. The relationship between tape characters and high and low
memory byte characters is shown in Figure 6-8.

6.4.6 Read Lines Register (MTRD)
Address = 772532. Read/write function contained in bit descriptions.
09

UNUSED

DATA
11-0435

Figure 6-9

Read Lines Register (MTRD) Bit Assignments
6-17

Bit

Meaning and Operation

'1'1 i\I ER - The timer bit is used for diagnostic purposes by measuring the time duration
of the tape operations. The timer signal is a 100 J.lS signal with a 50% duty cycle and is
generated by the controller. It is read as bit 15 in the memory location reserved for the
read data lines register. Read only bit.

CH A R S E L - This bit is used to select the last character of a record that is to be loaded
into the data buffer. Read/write bit. Selection is as follows:
7-channel

Set
Clear

9-channel

LRC character
Last data character

LRC character
eRC character

BTE GEN - Bad tape error generator bit. Actually, bad tape cannot be artifically
generated. When set, this bit sets the eu ROY bit. With CU ROY set, a premature gap
shutdown is generated, which produces a bad tape error indication when data is read
during this period. Write only bit.

GAP SHUTDOWN - Read only bit. When set, indicates a gap shutdown period.

11-09

Unused.

PARITY - Corresponds to the parity bit read from the tape by the master tape transport. Used in conjunction with bits 07-00 to indicate a longitudinal parity error. After
a read or write operation, bits 08-00 should all be o. If one or more of these bits
remains a 1 after the operation is complete, it indicates a longitudinal parity error. The
bit position containing the 1 indicates the tape channel containing the error. Read only
bit.

07-00

DATA - These bit positions contain information read from the magnetic tape transport. After these positions are read by the processor, all bit positions clear unless a
parity error exists.

Bits 07-00 in the read lines register correspond to tape channels 00-07, respectively.
Read only bits.
6.5 PROGRAMMING NOTES
In normal programming practice no attempt should be made to modify one record in the middle of a
file. This practice could result in overwriting the boundary of the record and destroying part of the
next record. Also, a read operation should never directly follow a write operation without at least one
intervening tape move operation. This prevents generating a BTE/OPI if the previous operation
involved the last record on the tape. If it is desired to read a record that was just written, a space
reverse command should be issued before the read command. New commands are issued only when
eu ROY is set, which is true after interrupts.

Attempting to write an all zero character with even parity on a 7-track or 9-track tape unit causes the
zero character to be converted to a tape character of 20. When reading this character from tape, a 20 is
read instead of zero.

6-18

ASCII standards provide for a 25-ft trailer following the end-of-tape marker. This allows approximately 10ft of writing space after passing EOT. Care should be taken when attempting to write past
the EOT marker if the operator is not familiar with the tape that he is working with, because after a
tape has been used, the reflctive markers are often changed, possibly decreasing the length of the
standard 25-ft trailer.
Because the physical displacement of the heads differ between 7-channel and 9-channel drives, records
written on one cannot be read by the other. However, a tape that is recorded on one can be fe-recorded
by the other, providing you begin at the load point.

I f two drives are sharing one controller, care should be taken not to allow both drives to have the same
unit number selected on the unit select plugs. If they are both set to the same number and a command
is issued, they will both attempt to respond and data transfers will become totally confused.
The industry-standard packing density for 9-channel drives is 800 bpi. However, 9-channel drives may
be recorded at 200, 556, or 800 bpi, providing the data is read back at the same rate.
A SPACE REVERSE or REWIND command issued while the tape is at the load point will cause an
im mediate interrupt.
6.5.1 Rewind Operation
Assume drive 0 is to be rewound. The command to rewind drive 0 is issued to the controller. At this
time the master tape unit asserts bit 1 (R WS) in the status register. If bit 6 (INT ENB) in the command
register was set at the start of the rewind operation, an interrupt occurs from the controller as soon as
bit 7 (CU ROY) of the command register has been set by RWS. This informs the program that the
controller is ready to accept a new command. By testing bit 1 (R WS) in the status register, the program
can determine if this interrupt was issued as a result of drive 0 completing its rewind operation or just
beginning it.

When the reflective marker, signifying BOT, is sensed, bit 5 (BOT) is asserted in the status register only
for the duration of time that the reflective marker is being read. Tape motion does not stop at this time.
Drive 0, still moving in the reverse direction, passes over the reflective marker, reverses its direction,
and proceeds in the forward direction back to the load point. Upon sensing the reflective marker while
proceeding in the forward direction, drive 0 halts tape motion, asserts bit 3 (SDWN) allowing the tape
to fully deskew, and then sets bit 0 (TUR) in the status register.
A n interrupt is issued coincident with bit 0 (TUR) being asserted in the status register, providing the
following conditions have been met.
1.

Bit 6 (INT ENS) in the command register is set,

The drive has not been deselected by changing the status of bits 10-8 in the command
register since issuing the REWIND command.

If multiple transports are used, it is not necessary to wait for a REWIND command to be completed
on one transport before switching to another. After a REWIND is issued, another transport can be
switched to as soon as R WS is set.

6-19

When operations on the second transport have been completed, a switch to the rewinding transport
can be made as soon as SOWN or TUR is true on the second transport (so the status bits will be from
the rewinding unit). Only the unit select bits in the command register have to be changed to the unit
that is rewinding to get its status. If the rewind is complete when the unit is selected, TUR is set in the
status register. If the R WS bit is still set, the software can either work on another transport or load the
next command to be executed in bits 1-3 of the command register where it is buffered until the rewind
is completed. If INT ENB is set at this time, the completion of the buffered command causes an
interrupt to occur. A REWIND command may take from 3 to 5 minutes to complete.
6.5.2

New Drive Selection

Figure 6-10 is a flowchart for new drive selection.

START NEW
OPERATION

YES

NO
ERROR

LOAO NEW
COMMAND
AND INT. ENB.

11-2673

Figure 6-10

New Drive Selection Flowchart

Other programming restrictions occur when using select remote along with tape unit ready. The select
remote lines for all tape units that are not addressed are at O. A tape operation may be performed only
on a selected tape unit and one whose SELR line is a 1. Thus, whenever a command is sent to a
different tape unit from the one presently indicated by the unit select bits, the SELR line becomes a
almost immediately (less than one instruction time later) and becomes a 1 from 1 to 28 microseconds
later.

6-20

6.5.3

Error Handling

6.5.3. B

Write Operations

ILC - Illegal Command
@

If SELR (bit 6 of MTS) is not set to a 1, or WRL (bit 2 of MTS) is set to a 1, then
operator intervention is required to ensure that the drive to be used is properly selected
and is not write locked.
If SELR (bit 6 of MTS) is set to a 1 and WRL (bit 2 of MTS) is not set to aI, then a
command has been issued while CU RDY (bit 7 of MTC) was cleared. Try the operation again, ensuring first that CU RDY is set before issuing a new command.
NjA

EOF - End-of-File

CRE - Cyclic Redundancy Error
Backspace and try operation again with extended IRG.

PAE - Parity Error
Backspace and try operation again with extended IRG.

BGL - Bus Grant Late
Backspace and try operation N times.

EOT - End-of-Tape
The reflective marker signifying the end-of-tape has been passed. Operations past
this point are not illegal; however, they are not recommended unless the programmer
is familiar with the tape being used and is knowledgeable about the length of tape
existing past the EOT marker. Conducting any write operations past the EOT marker leaves the programmer open to the possibility of running the tape off of the reel.

R LE - Record Length Error

BTEjOPI - Bad Tape Error jOperation Incomplete
Regain a known tape position and try the operation again with extended IRG.

NjA

NOTE
A known tape position refers to BOT, header
records, or EO F marks.

9.
6.5.3.2

NXM -Nonexistent Memory
Resolve the memory discrepancy and try the operation again.
Read Operations

ILC - Illegal Command
@

If SELR (bit 6 of MTS) is not set, then operator intervention is required to ensure that
the drive to be used is properly selected.
If SELR (bit 6 of MTS) is set, then a command has been issued while CU RDY (bit 7 of
MTC) was cleared. Try the operation again ensuring that CU RDY is set prior to
issuing the new command.

6-21

EOF - End-of-File
The characters signifying the end of a file have been read.

CRE - Cyclic Redundancy Error
Backspace and try the operation N times.

PAE - Parity Error
Backspace and try the operation N times.

BGL - Bus Grant Late
Backspace and try the operation N times.

EOT - End-of-Tape
The reflective marker signifying the end-of-tape has been passed. Continue only if it
is certain that an EOF mark exists after the EOT marker, or the tape will run off of
the reel.

RLE - Record Length Error
Reset the MTBRC to a value that is equal to or greater than the number of bytes in
the record, backspace, and try the operation again.

BTE/OPI - Bad Tape Error/Operation Incomplete
Regain a known tape position and try the operation again. If, after doing so,
the condition still persists, the data from the failing point to the next known
tape position is lost.

NXM -Nonexistent Memory
Resolve the memory location discrepancy and try the operation again.

6.5.3.3

Write End-of-File Operation

BTE/OPI - Bad Tape Error/Operation Incomplete.
Regain a known tape position and try the operation again.
6.5.3.4

Spacing Operations

ILC - Illegal Command
Same as read operation.

EOF - End-of-File
The characters signifying the end of a file have been read. Detection of the EOF
marks stops a spacing operation, even if the MTBRC is not equal to zero.

EOT - End-of-Tape
Same as read operation.

BTE/OPI - Bad Tape Error/Operation Incomplete
Regain a known tape position and try N times.

6.5.3.5

Write-with-Extended-IRG Operation - Same as write operation.

6.5.3.6 Rewind Operation - Once a rewind operation is started, it continues until complete, regardless
of errors or unit deselection.

6-22

6.6 FUNCTIONAL DESCRIPTIONS
The TM B 11 Controller may be divided into eight functional areas as follows:

Processor Data Transfer - The reading or writing of TMBll registers by the processor
(DATI/DATO).

Operation Start - The sequence from setting the GO bit to issuing SET to the transport to
start tape motion.

NPR Bus Cycle - Acquiring bus mastership for an NPR transfer.

NPR Read (DATO) - The transfer of characters from the tape transport to memory.

NPR Write (DATI) - The transfer of characters from memory to the tape transport.

Operation Done - The terminating sequence of a TMBII operation.

Error Sequence - The system errors detected by the controller and how they occur.

Interrupt B us Cycle - Acquiring bus mastership for a processor interrupt.

These eight functional areas are discussed in the following paragraphs. Block diagrams, flow diagrams,
and timing diagrams complement the discussions.
NOTE
The block diagrams that follow use logical AN D and
OR symbols. it does not necessarily follow that a
corresponding gate exists on the controller logic
prints. The assertion of inputs A and B causing the
assertion of output C may be represented on a block
diagram by a single AND gate yet the engineering
drawing may show that several circuit stages are
involved in the ANDing operation.
The signal names used on the functional block diagrams are the names used on the engineering circuit
schematics (CS prints). Where other signal names or
notes are used they are enclosed in parentheses.
Integrated circuit data sheets are contained in
Appendix E.
6.6.1

Processor Data Transfer

6.6.1.1 Processor Out (DATO) Transfer (TMBH Register Write) (Figures 6-12 and 6-13) - The
processor selects the TMB II for a data transfer by asserting the proper address on BUS A04-A17 to
the TM B 11 address decoder (address range = 772520 to 772536. *) When the decoder recognizes the
proper address it enables the address MSYN gate which asserts ADDR DEC MSYN when BUS
MSYN is received from the processor. ADDR DEC MSYN enables the select in/out logic which
looks at BUS AOI-A03 to select one of the six controller registers. The control select logic looks at
BUS CO-Cl and BUS AOO and asserts OUT HI, OUT LO, or neither according to whether a high byte
is to be written, a low byte is to be written, or a processor read operation is to occur. The control select
output enables the corresponding portion of the select in/out logic which outputs the loading strobe
for the selected register.

*Address locations 772534 and 772536 are not used.
6-23

When an "out" transfer is commanded, the SEL (1,4,5) OUT HI strobes will load their respective
registers, when selected.* The SEL 2 OUT HI, SEL 3 OUT HI, and SEL lOUT LO through SEL 4
OUT LO strobes are ANDed with SSYN INH to produce corresponding SLCT loading strobes.
SSYN INH is produced by inverting ADDR DEC MSYN on the MI05 module. A delay occurs with
the inversion, thus the loading of registers with SLCT strobes will be later (with respect to BUS
MSYN) than the loading of those with SEL strobes.
The information is strobed into the selected register a byte at a time; DOO - D07 = low byte, D08 - D 15
= high byte.
SSYN INH becomes BUS SSYN to notify the processor that the information on the data bus has been
strobed into the selected register.
The command register contains the type of operation to be performed and the operation parameters.
Dl3 and Dl4 are the density bits outputting DEN 5 and DEN 8. The processor sets these bits according to the desired mode of operation as shown in Table 6-2.
Table 6-2

Modes of Operation

Mode

DENS

200 bpi, 7-track
556 bpi, 7-track
800 bpi, 7-track
800 bpi, 9-track

0
0

1
0
1

1
1

The core dump mode is enabled when the program asserts both DEN 5 and DEN 8 while the 7-channel
(7CH) signal from the tape transport is true (indicating that a 7-channel tape transport is being used).
DEN 5 (1) and DEN 8 (1) are applied to an AND gate that is enabled by the 7CH signal from the
transport. The output from this AND gate is CORE DUMP which, when true, inhibits the DEN 5
AND gate thereby negating DEN 5. Thus, an 01 density code is sent to the tape transport indicating an
800 bpi data transfer.
The command register also specifies even or odd parity to the transport (PEVN), selects the desired
transport (SELO-SEL2), enables or inhibits BR cycles (INT ENB), and specifies the function that the
transport is to perform via a 3-bit function decoder. In addition, the command register carries 2
memory address bits to extend the current memory address register to 18 bits. Bit 00 of the command
register is the GO bit which initiates the commanded operation.
Other registers addressed during a processor out-operation are:
@

The current memory address register, which is loaded with the address of the first byte to be
transferred

" The byte record counter, which is loaded with the 2's complement of the number of bytes to be
transferred
o

The LRC ENB (l) bit of the read lines register which, when set, allows the LRC character to be
read into the data buffer.

*See Figure 6-27 for processor write of register 4.

6-24

6.6.1.2 Command Decoder (Figure 6-11) - The command decoder converts the eight functions generated by the command register function decoder into the six commands required by the tape transport.
Figure 6-11 illustrates the functions that make up each of the transport commands. Table 6-3 illustrates the conversion in tabular form.
READ + WRITE
WRITE ENS
FWD

READ
SPACE FWD

SPACE

SPACE REV

REV

REWIND
RWD
OFF LINE
WRE

WRITE
ENS

WRITE
WRT
DATA
ENS
WRITE XIRG

WXG

WRITE EOF

- - - - - - - - ' - - - 1 ( C l l l > O - - - - - - - - WFMK

NOTE:
Designolions in parenlhesis refer 10 engineering drawings
conloining corresponding logic.

Figure 6-11

11-4129

Command Decoder Logic Diagram

Table 6-3 Function Decoder Output vs Transport Commands
TRANSPORT
COMMANDS
COMMAND
DECODER
FUNCTIONS
OFF LINE
READ
WRITE
WRITEEOF
SPACE FWD
SPACE REV
WRITE XIRG
REWIND

>
~

~
X

X
X
X
X

~
~

c.!I

6-25

X
X

::lid

The conversion is mostly ORing and is straightforward except for the OFF LINE function. If the
processor orders an OFF LINE function, RWD (rewind) and WRE (write enable) are asserted to the
transport. Writing during a rewind is an impossible situation that the transport interprets as an OFF
LINE command. Four other signals are generated in the command decoder for use throughout the
TMBll. These signals are OR functions of decoder commands as shown in Table 6-4.
Table 6-4

Decoder ORed Functions for TMBll

TMBII Signal

ORed Function

WRITE DATA ENB

WRITE
WRITEXIRG

WRITEENB

WRITE
WRITEXIRG
WRITEEOF

READ + WRITE

WRITE
WRITEXIRG
WRITEEOF
READ

SPACE

SPACE FWD
SPACE REV

6.6.1.3 Processor In ( DATI) Transfer (TMBll register read) (Figures 6-12 and 6-14) - When an "in"
transfer is commanded by the processor, OUT HI and OUT LO from the control select logic are
negated thereby enabling the select in logic. BUS AOI-A03 selects one of the six controller registers
and outputs the corresponding SEL IN gating strobe to the output select multiplexer. Accordingly the
16 bits of the status register, register 1,2, 3,4, or the 12 bits of register 5 are gated out to the Unibus via
the Unibus drivers (see Figure 6-23 for processor read of register 4).

6-26

1. BUS A04·A17 SELECTS DEVICE
VIA ADDRESS DECODER.
BUS A01-A03 SELECTS ONE DF
6 TMB11 REGISTERS.
BUS CO-C1, AOO ASSERTS OUT HI,
OUT LO, OR NEITHER

PROCESSOR ASSERTS BUS MSYN
INDICATING DATA IS AVAILABLE
ON UNIBUS

ASSERTS SEL STATUS IN OR SEL(1:5)
IN AS SELECTED BY BUS A01·A03.

SELECTED REGISTER GATED
THROUGH OUTPUT MUX TO
UNIBUS VIA UNIBUS DRIVERS.

HI BYTE LOADED INTO
SELECTED REGISTER IF
REGISTER 1,4 OR 5
SELECTED.

DONE
NOTE:
During processor address of the TMB11
an I N transfer is a processor in transfer
or a read of the TMB11. An OUT
transfer is a processor out transfer or
a write into the TMB11.
11·4145

Figure 6-12 Processor In/Out Flow Diagram (DATI/DATa)

6-27

BUS SSYN

~------~~~~------------'~r----------------'

SSYN

INH

(ADDR DEC MSYN)

r---~~~L---~~~~~~~~~~~~------------------------~C

(FROM TAPE

TRANSPORT)~

BUS MSYN
BUS
A04-A17

ITOMMAND REGISTER

~ ~~~: ~(

ADDRESS
DECODER

MI05

SELECT
IN
(07)

OUTHII;J OUTLO_
@BUS AOI-A03

SEL STATUS IN

D13-D14

BUS
~ ~A..:..0=-1,--..;.A.:..:0:...:3'--__---+I b
~

SEL 3 IN

DI2

SEL 5 IN

BUS AOO

CONTROL
SELECT
Ml05

BUSCO-Cl

.OUT HI
OUT LO

)®

SELECT
OUT HI

®-OUT HI
®-BUS AOI-A03

(FIG 6-23)

SEL 5 OUT HI

SLCT 3 OUT HI'

I (D7) r-------------'---~ i

OUT H I

(011

SELECT
OUT LO
(D7)

SLCT 3
OUT HI

DOO-D07

I
I

CD
k

SlCT 3
OUT LO

ADDRESS
BITS OB-15

-t:J

M795
ADDRESS
BITS 00-07
M795

I
I

L ____ JI

(ADDRESS
BITS 00-07)

DOS-DI5
SLCT 2
h OUT HI

6-1S)

DOO-D07

SLCT 2
OUT LO

I
1
I

SEL 1
OUT LO

SLCT 4 OUT LO

(FIG 6- 23 and 6-27)

BITS
OS-15
M795

BI TS
00-07
M795

J (D7) .J SLCT30UTLO

DOB

I
DOO

9 OUT LO

(FIG 6-23)

--,

I
L ____ --I

TIMER L
(100,,"s) ITIMER(1) (FIG. 6-14)
(D9)
I(NOTE3)

P E VN
}

t2PE

T R A NS PORT

SELl

~
(FIG 6-33)

I
Ii

OFF LINE
\

READ
\

WRITE

EXTENDED
liADRS BIT16 (FIG \
WRITE EOF
ADDRESS:
6-1S) \
(DB)
:
\ADRSBIT17
SPACE FWD
SPACE REV

GO
FF
(C2)

!GO BIT (1)

I
L __ __ J'

(FIG
6-16)

\ WRITE XIRG
\

REWIND

O"'i: INES- -,

I
D14

LAST
CHARACTER
SELECT
(DS)

I I

(MTRD)

SEL5
OUT HI

DI3

FUNCTION
DECODER

(FIG 6-16)

fREA

I REGISTER

I
I
I

~--S-L-C-T--'-+--I--.)

(C4)

(C1J

D04- D05

(FIG 6-23)

~~~ 3LO

rBYTEI RECORD
I COUNTER
(MTBRC)

(ADDRESS
BITS OS-15)

INIT

(DS)
BUS INIT

I.INTENB (1)

L...--":"'~_.....J

I~~~RB~~PT

--:---

DOS- D15

D01- Da3

C SSVNIN8

I
I
I

-Ig

1(D7) } SLCT 2 OUT Lo.

SEL4
OUT LO

SEL2
OUT LO

fCURRENT MEMORY
I ADDRESS
REGISTER
I (MTCMA)

~
I

~ (FIG 6-33)

SEll lOUT LO /
h\-=-';"":;"::":'-=::'---''---lI((DD77))} SLCT lOUT LO

}TO
TAPE
TRANSPORT

r __I__..--sE_L__O_____

;rtl~~
SELECT
(CO

D06

r----------------L---~f

OUT LO
BUS AOI-A03

SELECT

I-D_O_S_~-~-~-O,---+---=I---+I

~/(FIG6-31)

PARI TY

1L...--_(C4_)----'

BUS DOO- D15

UNI BUS
RECEIVERS

(

-+__--I

C }-'::::":':':"'';':';';';'-I--j

DEN 5
I(CO

I
POWER
CLEAR
DS )
L...-------I

HI
L________J.::S:.=E~L~2....:0:..:U::..;T'-"H..:..I--1
-J (D7) j l - - -S-LCT- -2-OUT
-----+lh
SEL 3
OUT HI
SSYN INH

CORE DUMP

DEN5(1)

(CO

I-D_'_'______

(D7)

SEL 4 OUT HI

f---=----

r - - - - - . ( FIG 6 - 30

SEL lOUT HI

I
I

SEL41N
\ '---=.=.-..:...:~--------------------_(
FIG 6 - 231

(MTC)

(FIG6-23,6-24
and 6-27)

(CO jCORE DUMP

I
I
~L________~I---~D~E~N~B~--~------------------D-E-N-B---+

SEL 2 IN

7 CH

DENSITY
SELECT

SEL 1 IN

L...---=..:..::...._ _ _ _-'--......

BTE
GENERATaR
(C4)

LRC ENB (I)

r-________________________________~~FW~D-------+(t~PE
~

I (BTE CHECK)
I (NOTE 3)

L _ _ _ :.......J

_______________ { FIG 6-1Sand 6-24)

~::.....'--'--_________} (FIG 6-311
!-"-'-'-'=-.----------_{ FIG 6 -16,6 -IS and 6- 29 )

REV
\

TRANSPORT)

RWD
\

WRE
\

WXG

NaTES:
1. REGISTER 1 = COMMAND REGISTER (MTC)
REGISTER 2 = BYTE/RECORD COUNTER{MTBRC)
REGISTER 3 = CURRENT MEMORY ADDRESS REGISTER (MTCMA)
REG ISTER4 = DATA BUFFER REGISTER.! MTD),
REGISTER 5= READ LINES REGISTER (MTRD)
2. Designations In parenlhesis refer to engineering drawings
containing corresponding logic.
3. Maintenance use only.

11-4132

Figure 6-13 Processor Out (DATa)
Block Diagram

6-29

IOUTPUT-l
ISELECT
MUX

OBIT (/)(/)-15

16-BIT ......- f - - - - - - - - - - - - - - r - ILC (1)
GATE
EOF
SEL STATUS IN
(04-05)
CRE
PAE
(FIG.6-13)
BGL(1)

.0 BIT (/)(/)-15

OBIT (/)(/)-15
U
N
I
B
U
S

BUS 0(/)11l-015

16-BIT ......T - - - - - - - , - - E R R
DEN 8
GATE
SEL 1 IN
DEN5
(04-05)
(FIG. 6-13)
PWR CLR
PEVN
(COUNTER BITS
(6(/)-15 )
SEL2-SEL 121
16-BIT
CU READY (1)
GATE
INT ENB
SEL 2 IN
M795
ADRS BIT17-16
(FIG. 6-13)
FCTN BIT 2-121
(ADDRESS BITS
GO
(6(6 -15 )
16-BIT
GATE
M795

OBIT (/)(/)-15

o BIT011l-07

8-BIT
GATE
(04)

OBIT 9.12.14.15

5-BIT
GATE
(05)

NOTE:
1. Designation in parenthesis refer to engineering
drawings containing corresponding logic.

EOr
TUR
RLE
OPI/BTE
NXM
SELR
BOT
7CH
SOWN
WRL
RWS

14-7--1---------,- CHAN P (FIG. 6- 23)
SEL 5 IN
(FIG.6-13)

GSD (FIG. 6-31)
LRC ENB (1) (FIG.6-13)
TIMER (1) (FIG. 6-13)

2. See NPR read for processor read of data
buffer (register 4).
11-4124

Figure 6-14 Processor In (DATI) Block Diagram

6-31

6.6.2

Operation Start (Figure 6-15 and 6-16)

6.6.2.1 Basic Sequence - When the command register GO bit is set by the processor a command start
sequence is initiated. GO BIT (1) resets the CU ready bit in the command register indicating that the
TMB 11 is processing a command. If the tape transport is not rewinding and TUR is true, GO BIT (1)
triggers the GO strobe lone-shot. If the tape transport is rewinding (RWS true) GO BIT (1) will not
trigger the one-shot due to the "0" output from the transport rewinding flip-flop. When the rewind is
complete, TUR asserts resetting the rewinding flip-flop thereby triggering the GO strobe lone-shot.
The GO STROBE 1 output of the one-shot resets the request store flip-flop and if SELR is true, the
"0" output of the request store flip-flop triggers the GO strobe 2 one-shot. When GO STROBE 2 (1)
asserts, the following occurs:
1.

SET is asserted to the tape transport if there is no illegal command and if the function is not
REWIND or SPACE REV while the tape transport is at BOT (REV BOT false).

The GO flip-flop is reset and the request store flip-flop is set in preparation for another GO
command from the processor.

The trailing edge of GO STROBE 2 (1) resets the CUR delay flip-flop. CUR DEL (1) is
negated indicating to the error logic and the done logic that a transport operation is now in
progress.

6.6.2.2 Time Out - If the transport is not selected or is not on-line (SELR false), the output of the
request store flip-flop will not trigger the GO strobe 2 one-shot. In this case, GO BIT (1) initiates a 28
JlS delay after which TIME OUT (1) asserts and triggers the GO strobe 2 one-shot. The assertion of
GO STROBE 2 (1) while SELR is negated causes the assertion of SET ILC and ILC (Paragraph 6.6.7)
which respectively inhibit the assertion of SET to the transport and initiate a done sequence (Paragraph 6.6.6).
6.6.2.3 Restart - If the system is performing a spacing operation, either forward or reverse, the tape
will space through records without coming to a stop at each interrecord gap.
In this case the SET commands required by the transport are generated by RESTART which triggers
the GO STROBE lone-shot without the necessity of TUR being true. RESTART asserts in the
SPACE mode of operation each time SDWN is sensed and the following errors are false: BTE, BGL,
NXM, ILC (1), OVERFLOW (1), EOFF (1), and BOT.
6.6.2.4 OPIjBTE - When GO STROBE 2 (1) asserts, a 7-second delay is initiated. If the 7-second
time period elapses before an LRCS terminating strobe occurs, OPI is asserted indicating an operation
incomplete error. OPI asserts the OPIjBTE bit in the status register and also CINIT to the tape
transport resetting the transport logic circuits. The 7-second delay sequence is inhibited during a
rewind operation (RWD true) as rewinding the tape could exceed 7 seconds.
6.6.2.5 Initialize - GO STROBE 1 (or an INIT from the processor) asserts INIT + GO which causes
a general reset of the TMB 11 logic circuits. A general reset of the tape transport is caused by CINIT
which is asserted by any of the following conditions:
1.
2.
3.

The processor asserts INIT.
BOT is reached during a space reverse operation.
OPI is asserted.

6-32

ILC

YES

7 SEC

0'1
I

W
W

Anyone of the following:
BTE
BGl (1)
NXM
ILC (1)
OVERFLOW (1)
EOFF (1)

BOT

114139

Figure 6-15

Operation Start Flow Diagram

( FIG.

(FROM TAPE
TRANSPORTl

6 -13 ) _--,S,-,P...:.A.:.,:C:..:E:..:.:..:R;::;E..:.V-,

BOT

CINI T

BOT

O. S.
(Cn

(TO TAPE
TRANSPORTl

~=A:;l
REGISTER
I
I BIT 07

I
(FIG. 6-29) SET CUR

(FROM TAPE
TRANSPORT)

(RESETl

RWD

(C5)

(FIG. 6 -13)
(SET)

1N.:,:I..:.T-"-_-4
( FIG. 6 - 1 3 ) ___

INIT+GO (GENERAL
TMBll RESET)

CU
I READYt-...--R.:;cE
__
A=-DY.:....;,.(l;,,:,)... (FIG.6-14
,..:.(:..:.R=.E-=-S-=-E:..:.T:..:.)-lJ-.,J (~i~
AND 6-33)

GO STROBE 2 (1)

LRCS

F.F.
(C5)

(SETlI

!
GO
STROBE

O. S.

OPII

(RESET)

ROST
GO
STORE
STROBE 1 (RESET)
F.F.
(C2)0

GO
STROBE
.--~2

OPI/BTE (1)

(C5)

(FIG.
6-14)

(1)

r---~------L-------~
r-"--_/

TUR

BTE
F.F.

L __ -.I

(6-18,6-23
6-27,6-31
a 6-33)

(C 2)

SET

(TO TAPE

~~- TRANSPORT)

( FIG. 6 _ 31) _S:..:E:..:T--...:I:..::L:..::C~

RWS
FROM
TAPE
TRANSPORT

I ~~ATUS

1
(FIG.

r:: -~ l

1
DELAY
INHIBIT

(S ETl

TUR

TAPE
RWNDG.

(RESET)

SE LR

F.F.
(C2)
0

FROM {SELR
TAPE
TRANSPORT
SELR
B }---_-"G-"O~B~IT~(.!..lL)-I( 0 9)

(FIG.6-29)

REV BOT

28 }L S
DEL A Y I-'-T:..:.IM=E:..:.0:::U,,-T~(.!..1L)_---..1
( 09)

(FIG. 6 -24

SOWN

(FIG 6-13)

(FIG

,-'"

GO STROBE 2 (1)(RESET)

SPACE

[

SET CUR

( C2

BGL (1)

(FIGS. 6- 24
6-29
6-31 )

NXM
ILC (1)
OVERFLOW (1)
EOFF (1)

(FROM TAPE
TRANSPORT)

(FIG.6-29)

BTE

CUR 1
DELAY CUR DEL (1)
F. F.

BOT

(C2)
NOTE:
Designation in parenthesis refer to engineering drawings
containing corresponding logic.
11-4125

Figure 6-16 Operation Start
Block Diagram
6-35

N PR Bus Cycle (Figures 6-17 and 6-18)

6.6.3

6.6.3.1 Basic Sequence - An NPR bus cycle is initiated via the NPR request logic. The request logic
generates NPR ENB (1) if:

1.
2.
3.

No inhibiting condition exists.
The logic is enabled.
NPR SET is asserted.

The request logic is inhibited if OVERFLOW (1) is true (the desired number of data records have
already been transferred), BGL or NXM is true from the last NPR request, or CRCS or LRCS are
asserted (CRC and LRC characters are not transferred to memory). The request logic is enabled by
EVEN CHAR STB which is always high in normal7-track or 9-track modes but only high during even
character transfers in core dump mode. Thus in core dump, two characters are read from (or written
onto) tape for each NPR bus cycle.
The request logic is set by read strobes or write strobes (RDS + WRS) from the tape transport. If a
write operation is being executed (WRITE DATA ENB true) GO STROBE 2 (1) triggers the first NPR
bus cycle as the first write strobe is not generated until the first character is written on tape.
The request logic asserts NPR ENB (1) to the Unibus NPR acquisition logic which requests control of
the Unibus by asserting BUS NPR. When the processor responds with BUS NPG IN the acquisition
logic asserts BUS SACK and the processor responds by negating BUS NPG IN. The acquisition logic
checks for BUS BBSY true (by some other device) and if it finds the bus free asserts BUS BBSY
(indicating bus mastership) and NPR MASTER to enable the NPR master logic.
When the NPR master logic is enabled the following actions occur.
1.

ADRS --+ BUS becomes true and gates the address register and the two extended address bits
of the command register to the Unibus as BUS AOO - A 17.

BUS CO - Cl is gated to the Unibus. If a read operation is to occur, READ is true and BUS
CO - CI are high. If a write operation is commanded, READ is false and BUS CO - Cl are
low.

If the transfer is a read operation, DATA --+ BUS is asserted and gates the character in the
data buffer out to the Unibus.

Another output from the master logic undergoes a 150 ns delay (to allow for deskewing on
the Unibus address lines) and then sets the MSYN logic circuit.

The MSYN logic asserts BUS MSYN to the slave device which then returns BUS SSYN to the
TMB 11. BUS SSYN becomes SSYN and is applied to the read and write termination circuits. If a read
operation is being performed the read termination circuit asserts an input to the termination OR logic.
If a write operation is being performed (READ false) the write termination circuit asserts DATA STB
1 which undergoes a 150 ns delay (for input data deskewing) and then becomes DATA STB 2. DATA
STB 2 loads the data buffer with the input character that is to be written on tape. DATA STB 2 also
asserts an input to the terminator OR logic. The asserted output of the OR logic is delayed 75 ns (for
data deskewing into the data buffer) and then triggers the NPR clear logic.
The NPR clear logic asserts NPR CLR BBSY which resets the NPR request logic and increments the
bus address register and the byte/record counter for the next character transfer. If a spacing operation
is in progress the byte/record counter is incremented by LRCSD and no bus cycle is involved.

6-37

6.6.3.2 Bus Grant Late (BGL) and Nonexistent Memory (NXM) - When NPR ENB (1) is asserted the
bus grant flip-flop is conditioned to set. If another NPR SET is asserted to the NPR request logic
before the logic is reset, the bus grant late flip-flop will set asserting BOL (1) which in turn asserts BOL
+ NXM to the error logic.
If the MSYN logic is not reset within 20 J1.s after being set, NXM asserts and terminates the bus cycle
by asserting the termination OR logic output. NXM also asserts BOL + NXM to the error logic.

6.6.3.3 BUS NPG OUT - An NPO from the processor is passed from one system device to another in
daisy-chain fashion until it reaches the device that issued the BUS NPR. A BUS NPO IN received by
the TMBII is gated back to the Unibus as BUS NPO OUT under either of the following conditions:
I.

NPR MASTER is true (TMBll is presently bus master), or

NPR ENB is false (TMBll did not issue the BUS NPR that caused the BUS NPO IN).

6-38

READ OR
WRITE STROBE

20llS

150 ns

75 ns

* Anyone of the following:
OVERFLOW (1)
BGL (1)

NXM
CRCS
LRCS

I ADRS~ BUS
IDATA~BUS

I BUS CO-Cl

11-4140

Figure 6-17 NPR Bus Cycle
Flow Diagram
6-39

...

UNIBUS

~ NPRENs H

(FIGURES '-VM7B21
6-23
""'AND
6- 27)

BUS
NPR
( FIG.
6-33)

I----

BUS BUS BUS
NPG SACK BBSY

BUS
C(/l-Cl

p'"'

BUS
MSYN

NPRENB~

BUS
SSYN

BUS
A16-A17

~()
-V

H
)M7821
r----/

UNIBUS NPR
ACQUISITION
lOGIC
M7821

NPR ENB (1 )

BUS
NPG IN

SSYN

D
EXTENDED
ADDRESS BITS
A16-A17
(BITS (/l4-(/l5
OFMTC; FIG.
6-13)
(D8)

NPR MASTER
(FIG. 6-13) ~EAD
M796
_ _ ~BGl(1)

BUS
A00-A15

( ADDRESS
BITS 16-17)

BUS
ADDRESS
GATE

I--

(00)

GRANT
lATE
NPR SET
FF
E }-'-"--'-'--':':;;":"-+lC
(C5)

B CNTRl ClR (RESET)

NPR
MASTER
lOGIC

150 ns
DELAY
M796

(SET)
~

M796

MSYN
lOGIC
M796

r-~

20p.s
DELAY
M796

NXM

BGl + NXM

0-BGl (1) J (C5)

(FIG.6-24
~---------,- AND 6-31)

C~---------------,

( RESET)
A )--'--'---''-'---1

,...-_ _--, CARRY
OUT 3
(CLOCK)
BUS
I--,.... ADDRESS
REGISTER (ADDRESS BITS 00-15)
M796

BUS
ADDRESS
GATE
M795

B~---------~

A}+-----,

(FIG.6-13)~
(FIGURE 6-31)

OVERFLOW (1)

(NPR INHIBIT)

(FIGURE 6-19)
(FIGURE 6 - 27)
( FIGURE 6-19)
( FIGURE 6-16)
(FIGURE 6-13)

NPR
REQUEST
CRCS+LRCS
lOGIC
( D8)
E_V'--E.c.N_CH_A_R_S_TB_ _ _ _ _(;....N_P_R_E"'N--'A;....Bl....E;:..:)--+t
G BGl + NXM

1-kJ--t._.-..::..:..::...-.J
SSYN

( READ OR WRITE STROBE)
GO
~D8) NPR SET
STROBE 2 (1)

WRITE~A J

ENB

(D8)

'-<v

---NPR CLEAR BBSY (1)
(NPR RESET)
Cr----------------------~

READ
TERMINATION 1 - - - - - - - - - - - 1
M796
TERMINATION
OR lOGIC
M796

(FIG. 6-13)

-RE
AD
{
READ

WRITE
TERMINATION
M796

DATA STB1

150 ns
DELAY

75ns
DELAY
M796
L--____

CNTRl
ClR

NPR
CLEAR

NPR ClR BBSY ( 1)

lOGIC
M796

~
(D9)CLK2

DATA STB 2
(FIG.6-27)

(FIG. 6-19) lRCSD

(FIG.6-13) SPACE
DATA-BUS
M796 } - - - - - - - - - - - - - - - - - . (FIG. 6-23)

ADRS -

NOTE; Designations in parenthesis
refer to engineering drawings
containing corresponding logic.

(FIG.6-23)
BYTE/
RECORD
COUNTER
M795

( FIGS.
CARRY OUT 2 6-29AND
6-31)

L-_ _---I

(D9)

BUS

11-4126

Figure 6-18 NPR Bus Cycle
Block Diagram

6-40

6.6.4

NPR Read (DATO)

6.6.4.1 Transport Strobe Processing (Figure 6-19) - Various strobes from the tape transport are used
for a read function and in other functional areas of the TMB11. Many of the strobes are combined
and/ or modified before being used in the controller. This strobe processing is illustrated in a separate
figure due to its common application to the TMBII functions. Note the generation of READ STB. It
is asserted by RDS when READ is true, however, the RDS strobe associated with the LRC character
will not assert a READ STB pulse due to LRCS unless the LRC ENB bit is set in the read lines
register.

LRCS

LRCS
DELAY I--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
L R--,-C-,-,S0'----.
1",s
(C3)

FROM TAPE
TRANSPORT

CRCS + LRCS
CRCS---.

WRS---------~

(READ OR WRITE STROBE)

TO
TMB11
BLOCK
DIAGRAMS

(Fig. 6-13) R E A D - - - - - - - ,
READ STB
FROM TAPEl RDS
TRANSPORT _
LRCS-~-

LRC ENB (1)
(Fig. 6-13)-----<---NOTE:
Designations in parenthesis refer to engineering drawings
containing corresponding logic.
11-4128

Figure 6-19

Strobe Processing

6.6.4.2 9-Track and 7-Track.Normal Operation (Figures 6-22 and 6-23) - When a character is received
from the tape transport, READ STB asserts setting the select read flip-flop and causing SEL READ
DATA to become true. In 9-track operation SEL READ DATA enables gates A, B, and C which
respectively gate CHAN 0-3*, CHAN 4-S*, and CHAN 6-7* to become DATA BFR IN BIT 0-3,
D AT A BFR IN BIT 4-S, and DATA BFR IN BIT 6-7. The data buffer is divided into two halves with
each half of the buffer loaded by a separate strobe. DATA BFR STB 1 loads buffer bits 0-3 and
DATA BFR STB 2 loads buffer bits 4-7. The input READ STB asserts DATA BFR STB 1 (via the
even character strobe logic) and DATA BFR STB 2 which load both halves of the data buffer and
provide D AT A BFR OUT BIT 0-7 to the high and low data byte gates. Table 6-S summarizes the
gating action associated with the data buffer.
DATA -4 BUS is asserted during the NPR bus cycle and enables either the high data byte gate or the
low data byte gate according to the state of bit 00 in the current memory address register. When LO
DATA BYTE is true the data buffer output is gated to the Unibus drivers as D BIT 00-07 and thence
to the Unibus. On the next NPR bus cycle HI DATA BYTE becomes true and the buffer output is
gated to the Unibus as D BIT 08-1S.

*A channel reversal occurs in the input read amplifiers where R07 - ROO corresponds to CHAN 0 - CHAN 7
respectivel y.

6-41

The 7-track operation is identical to the 9-track operation except that the buffer input gate C is inhibited. (See Table 6-5.) Consequently CHAN 6-7 are not loaded into the data buffer and there is no data
on buffer output lines DATA BFR OUT BIT 6-7, or on Unibus driver input lines D BIT 06-07 (low
data byte) and D BIT 14-15 (high data byte).
Table 6-5
Mode of
Operation

Enabled
Gates

Channel Bits
From
Transport

DATABFROUT
BITS - From
Data Buffer

Number of
Output Bits
per Data Cycle

A
B
C

CHAN 0-3
CHAN 4-5
CHAN 6-7

0-3
4-5
6-7

A
B

CHAN 0-3
CHAN 4-5

0-3
4-5

First
Cycle

CHAN 0-3

0-3

Second
Cycle

CHAN 0-3

4-7

9-Channel

7-Channel
(Normal)
7-Channel
(Core
Dump)

Data Multiplexing in 9-Track, 7-Track Normal, and Core Dump Modes

6.6.4.3 Core Dump Operation (Figures 6-22 and 6-23) - Core dump operation can be implemented
only in the 7-track mode, thus both 7 CH and CORE DUMP are true throughout this discussion.

When the first character is received from the transport, READ STB sets the select read flip-flop, SEL
READ DATA becomes true, and gates A and D are enabled. CHAN 0-3 are passed through both
gates to become DATA BFR IN BIT 0-3 and DATA BFR IN BIT 4-7 into the data buffer. The input
READ STB asserts DATA BFR STB 1 (via the even character strobe logic) and DATA BFR STB 2
thereby loading both halves of the data buffer with the same character. The second character received
from the transport triggers the same sequence except no read strobe is issued from the even character
strobe logic and DATA BFR STB 1 is not asserted. DATA BFR STB 2 is asserted and loads bit 4-7 of
the data buffer with the second tape character. (See Table 6-5.) The read strobe associated with the
second character initiates an NPR bus cycle causing DATA ~ BUS to go true and gate the contents of
the data buffer out to the Unibus. Thus, NPR bus cycles are initiated after each even numbered
character is read from tape thereby allowing the two characters to be assembled into a byte in the data
buffer before being gated out to the Unibus.
6.6.4.4 Processor Read (Figure 6-23) - During a processor read of the data buffer SEL 4 IN asserts
both HI DATA BYTE and La DATA BYTE. The latter gates the 7 bits of the data buffer to the
Unibus while the former serves to gate D BIT 08 IN to D BIT 08 on the Unibus. During a processor
read (NPR ENB false) D BIT 08 IN reflects the state of the parity flip-flop as determined by the parity
bit of the LRC character.

6-42

6.6.4.5 Even Character Strobe Logic (Figure 6-20 and 6-21) - The even character strobe logic is
enabled in the core dump mode and function to:
1.

Suppress even numbered read strobes allowing read strobes no. 1,3,5, etc. as output; this is
used to ass semble two tape characters into a data byte

Toggles EVEN CHAR STB L to disassemble an input data byte into two 4-bit data characters (write operation)

Enables an NPR bus cycle only on even numbered read strobes (or write strobes).

GO STROBE 2 Land IN IT + GO L set the even character and strobe switch flip-flops. The first read
strobe passes to the output through enabled gate D2. The same read strobe toggles the even character
flip-flop to the reset state thereby conditioning the switch flip-flop to reset. The trailing edge of the first
read strobe clocks the switch flip-flop to the reset state which inhibits gate D2. The second read strobe
therefore does not appear in the output. It does toggle the even character flip-flop back to the set state
thus conditioning the switch flip-flop to set. The trailing edge of the second read strobe sets the switch
flip-flop thereby enabling gate D2 once again. The third read strobe will pass to the output through
gate D2 and the cycle is repeated. The read strobes (or write strobes) toggle the even character flip-flop
causing EVEN CHAR STB L to take on a square waveform. The timing diagram (Figure 6-21) illustrates the foregoing sequence.
When not in the core dump mode, EVEN CHAR STB L is held in a high state keeping the strobe
switch flip-flop set thereby allowing all read strobes to pass to the output.

GO STROBE

2 (1 ) L

, - - - - - . (HIGH WHEN NOT IN CORE DUMP MODE)

INIT. + GO L

(READ OR
WRITE STROBE) H

EVEN
FF
CHAR{O) H
EVEN CHAR
C{D6)o-t--'-----...--')O-ST_B_L----'---10

1 /-E_63_-_9_{1_)_H-r_-

STB
SWITCH
READ STB L
CORE DUMP H

C (2 )
READ STB H

NOTE:
Designations in parenthesis refer to engineering drawings
containing corresponding logic.

Figure 6-20

ODD NUMBERED )
READ STROBES:
1st.,3rd.,5th., .....

11-4136

Even Character Strobe Logic Diagram

6-43

--1 1 1'5 f~

GO STROBE 2 L
(O.S.)

EVEN CHAR (0) H

EVEN CHAR STB L

L-

EVEN CHAR STB H

RDS H

READ STB L

READ STB H

(READ OR WRITE STROBE) H

u
n
n

UIL
IL

INIT + GO

E63- 9 (1) H

NPR ENS (1) H

L
______________~rl~_____
11-4127

Figure 6-21

Even Character Strobe Timing Diagram

6-44

YES

Figure 6-22

NPR Read (DATO) Flow Diagram

6-45

'-;'::~I:D;:::;0;:::;8:::::::==::;;::;;~_ _ _ (FI G 6 -13)
CRCS + LRCS
PARBIT(ll

,--l-...::...:.c..::....:'
+ ---'.-=-"----}

NPR ENB (1)

CRCS

LRCS

(F I G 6-19)

~~CH~A~N~P------~ b
L-_:..:.:::c..:.::.--'S..cT.:;B_ _ _ _ _ _ _ _ _ (FI G 6-19)
SEL
4 OUT
L---_ _
__
_ _HI
_ _ _ _ _ _ _ (FIG 6- 13)
PR ENB (1)
N

l(FIG 6-18)

DATA BFR OUT BIT 0
(SET)

CMA BITOO(t)

HI DATA BYTE

BUS
DOO- D15

::> 1+-----1

r-+-_:...:N.:...P.:..:R--'C:..:L:..:E:.:.A.:...R----.:B:.cB"-S"-y_ _ _ _ _ _ _ _ _ _ ( FIG 6 -18)

SEL 3 OUT LO

DATA BFR OUT BIT 1-7

DATA- BUS
i - - - - - - ( F I G 6-18)

SEL 4 IN (FI G 6-13)

::>

I-+..:D:....:O:.:.O=---_ _ _ _ _r -_ _ _ _
(TOGGLE)

(FIG 6- 13

LO DATA BYTE
( RESET)

DATA BFR OUT BIT 0-7

(FIG 6-27)

(NOTE 2)

j4-'C:..:O:..:R.:.:E::......:D:..:U:..:M::.:P_ _ _ _ _ ( FIG 6-13)

o~D~A:...:T:.:.A.:....:;B.:...F.:..:R~S~T-=B~l-~

DATA BFR
OUT BIT 0-3

EVEN

DATA BFR
OUT BIT 4-7

SLCT 4 OUT LO (FIG 6-13)

INIT

+ GO

CHARACTER
GO STROBE 2 (1)
STROBE
~~~~~-=-"--=-LOGIC
(READ ORWRITESTRO
FIG 6-20

(FIG 6-16)

(D2,D6)
(FIG 6-19)

DATA BUFFER REGISTER (MTD)

DATA BFR STB 1 (LOAD)

BITO- BIT3
( D2)

DATA BFR IN
BIT 0-3

B IT4- BIT 7

(LOAD) DATA BFR STB 2
READ STB

(D3)
DATA BFR IN
BIT 4-7
DATA
BFR IN
DATABFRIN
BIT
BIT6,7
4,5

NOTE S;
t. Designations in parenthesis refer to engineer ing drawings
containing corresponding logic.
2. In 9-CHANNEL and 7-CHANNEL NORMAL MODES output is
every read strobe. In 7-CHANNEL CORE DUMP MODE
output is the odd numbered read strobes (1st, 3rd,5th, ---1.

(FIG 6-19)

READ

STB

(SET)
(SEL READ DATA)

D
SEL ECT
READ
FF
(FIG 6-18) NRP ENB (1)

(D2)

( FIG 6 -1 9) _L_R_C_S_D_('---R_E_S_E_T-'-)_-----'

( FIG 6- 27)

CORE
DUMP (FIG
6-13)
CHAN 6,7
CHAN4,5

READ
AMPS

(FROM
....-_R_D_7_-_R_D_0-,-,_R_D_P_ TAP E
TRANSPORT)

( D2)

11-4122

Figure 6-23 NPR Read (DATO)
Block Diagram

6-47

6.6.5

I
I

N PR Write ([) AT1) (Figures 6-26 and 6-27)

6.6.5.1 9-Track and 7-Track Normal Operation - An NPR request must be made (NPR ENB true)
before a write operation (READ false) can be initiated. With NPR ENB true and READ false either
SEL La BYTE WRITE DATA or SEL HI BYTE WRITE DATA asserts to gate respectively
OOO-D07 or 008-DIS from the Unibus to the input of the data buffer. The state of bit 00 in the
current memory address register determines whether the high byte or the low byte is gated to the
buffer. During the write NPR bus cycle DATA STB 2 is asserted (Paragraph 6.6.3.1) and asserts
OAT A BFR STB 1, 2 which loads the data buffer with the selected input byte. DATA BFR OUT BIT
0-7 is now available to gates A, B, C, and D. In 9-track operation gates B, C, and D are enabled gating
DATA BFR OUT BIT 0-7 to the tape transport as WD7-WDO. (Note the reversal in the bit/track
numbering sequence at the write gate outputs.) The 7-track normal write data sequence is identical to
the 9-track sequence except that write gate 0 is inhibited. Thus DATA BFR OUT BIT O-S are gated to
the transport as WD7-WD2. Table 6-6 summarizes the gating action for all modes of operation.
Table 6-6
Mode

9-Track

Enabled Write
Gates

B
C
0

7-Track
(Normal)
7-Track
(Core
Dump)

Write Data Gating for 9-Track, 7-Track Normal and Core Dump Modes
DATA BFR OUT
BITS - From
Data Buffer

Write Data
To Transport
Register

Number of
Input Bits
per Data Cycle

0-3

WD7-WD4
WD3-WD2
WDI-WDO

4-S
6-7

B
C

0-3

4-S

WD7-WD4
WD3-WD2

First
Cycle

0-3

WD7-WD4

Second
Cycle

4-7

WD7-WD4

6.6.5.2 Core Dump Operation - Core dump operation is identical to 9-track and 7-track normal
operation with regard to the input gating and loading of the data buffer. The difference is that only
write gates A and B are enabled and they are alternated by EVEN CHAR STB so when one gate is on
the other is off. With CORE DUMP true, the even character strobe logic is enabled and EVEN CHAR
STB is a sql,lare wave with its alternations switched by write strobes. (See Paragraph 6.6.4.S.)
A sequence is started by GO STROBE 2 (1) which sets EVEN CHAR STB to a high level and triggers
the first NPR write bus cycle. DATA STB 2 asserts during the bus cycle asserting DATA BFR STB 1,
2 which loads the data byte into the buffer register. DATA BFR OUT BIT 0-3 is gated through gate B
and passes into the tape transport as WD7-WD4. The first character is written on tape and the first
write strobe is generated. The first write strobe sets EVEN CHAR STB to the low state thereby
inhibiting gate B and enabling gate A which gates DATA BFR OUT BIT 4-7 to the transport as
WD7-W04 and the second character is written on tape. The low state of EVEN CHAR STB inhibits
another NPR bus cycle. The second write strobe will set EVEN CHAR STB high enabling gate B once
again and triggering the second NPR bus cycle. Thus, the even character strobe logic disassembles the
input data byte into two 4-bit characters for the tape transport while inhibiting an NPR bus cycle on
the odd numbered write strobes.

6-49

6.6.5.3 Processor Write - If a processor write is being executed, SEL READ DATA and NPR ENB
(I) are false, thereby asserting SEL LO BYTE WRITE DATA and gating the low data byte from the
Unibus to the buffer register. SLCT 4 OUT LO then asserts (Paragraph 6.6.1.1) in turn asserting
DA TA BFR STB 1, 2 which loads the buffer register with the input data.
6.6.5.4 Write Data Ready (Figures 6-24 and 6-25) - WDR to the tape transport must be true to enable
the write logic within the transport. The write data ready logic supplies WDR to the transport, under
the proper conditions, and assures a minimum record length of three characters in normal operation
and four characters in core dump. Also during core dump, when OVERFLOW (1) occurs, indicating
that the last character has been transferred to the controller, the logic holds WDR true for one more
write strobe to allow the second half of the last data byte to be written on the tape.
WDR is asserted true by the third stage output of a 3-stage counter or by the asserted output of a 5input A ND gate. When a write operation is initiated GO STROBE 2 (1) L is asserted and resets the
counter. The third stage output of the counter asserts WD R via the OR gate. OVERFLOW (1) H is
false, thereby conditioning the first stage of the counter to set. The first three write strobes set the
counter stages in order. The third write strobe sets the third stage causing its output to the OR gate to
assert high; however, the AND gate is now enabled and holds WDR true. Note that WDR is held true
for three write strobes regardless of the state of OVERFLOW (1) H.
When the desired number of characters have been transferred to tape, OVERFLOW (1) H goes true,
conditioning the first stage of the counter to reset. The next WRS strobe resets the first stage inhibiting
the AND gate causing WDR to go false. If CORE DUMP L is asserted the AND gate will not be
inhibited until the next WRS strobe when the second stage is reset. Thus, in core dump mode WDR is
held true for one more write strobe after OVERFLOW (1) H asserts.

BG L + NXM L
( FIG. 6- 18) - : . . . : . - : : - - - - - - - - - - - - - - - - ,
AC LO L
( FROM UNIBUS) - - - - - - - - - - - - - - - - ,
DEc.::L-'(_1l_H_ _ _ _-CII
(FIG. 6 -16) _C"--U_R___
WRT DATA ENB H
( FIG.6-13)
{

CORE DUMP L

------Q

WDR H
(TO TAPE
TRANSPORT)

OVERFLOW (1) H _~--'
(FIG. 6- 31 )

STAGE
(C3)

C
(FROM TAPE
TRANSPORT)
( FIG 6 -16)

11--+-~

, st

WRS H
GO STROBE 2(1) L

_-=-=-~-'-'--''--'--'-----'-

_ _ _ _- - . J_ _ _ _ _ _--'

NOTE:
Designations in parenthesis refer to engineering drawings
containing corresponding logic.

Figure 6-24

11- 4131

Write Data Ready Logic Diagram

6-50

GO STROBE 2

WRS H

(1st. STAGE OUT(1))

OVERFLOW

(1) H

( 2nd. STAGE OUT (1 ) )

(3rd. STAGE OUT (1 ) )

WDR H
(9 TRACK AND
7 TRACK NORMAL)
WDR
(CORE DUMP)

- - - - - r - 3 CHAR ACTERS -

........._ _ _---,'--_ _ _ _ _ _ _ __

_ _- - 1 4 - - - - 4 CHARACTERS - - " -_ _ _ _ _ _ _ _ __
11-4123

Figure 6-25

Write Data Ready Timing Diagram

Due to feedback from the second counter stage to the first, two write strobes must occur (to set the
second stage) before the first stage can be reset. Consider the case where OVERFLOW (1) H asserts
after the first or second write strobe (Figure 6-25). The first stage will reset on the third WRS which
also sets the third stage. If, in core dump mode, the AND gate holds WDR true until the fourth WRS
strobe which resets the second stage thereby negating WDR. Thus at least four write strobes are
assured in core dump operation.

6-51

11-4141

Figure 6-26 NPR Write (DA Tl) Flow Diagram

6-52

CH:::~TER

(FIG. 6-13)

CORE DUMP

(FIG. 6-16)

GO STROBE 2 (1)

(FIG.6-19)

(READ OR WRITE STROBE)

STROBE

~?~.'~:_ 20

EVEN CHAR STB

(HIGH WHEN NOT IN
CORE DUMP MODE)

WD7-WD4
DATA BFR OUT BIT 4-7

(02,06)

WD7-WD4

WDfJ-WD7

• (TO TAPE TRANSPORT)

DATA BFR OUT BIT 0-3

(FIGURE 6-13)

CORE DUMP

1WD3, WD2

DATA BFR OUT BIT 4,5

(FROM TAPE TRANSPORT)

7CH

I r.:AT~

WD1, WDI/I

DATA BFR OUT BIT 6,7

DATA BFR OUT
BIT'" -7

(FIG. 6-13)

0'1

(FIG. 6-18)

SLCT 4 OUT LO
(LOAD) DATA BFR STB 1,2
DATA STB 2

DATA BUFFER REGISTER
8 - BIT

(MTD)

(02 - 03)

VI
Vol

BUS DfJfJ - 015

UNIBUS
RECEIVERS

DfJfJ - DfJ7

READ

(SEL HI BYTE WRITE DATA)

CMA BIT

fJ!<l (fJ) (FIG.6-23)

D¢8-DI5

(Dll
(SEL LO BYTE WRITE DATA)

(SEL READ DATA)

(FIG.6-23)

NPR ENB (I)

(FIG.6-18)

NOTE
Designations In parenthesis refer to engineering drawings
containing corresponding logic.
11-4134

Figure 6-27

NPR Write (DATI) Block Diagram

6.6.6 Done Logic (Figures 6-28 and 6-29)
The done flip-flop senses the completion of an operation and functions to assert control unit ready (for
another command) and issue an interrupt request to the interrupt logic.

If a spacing operation was being executed CARRY OUT 2 signifies the completion of the operation by
asserting when the desired number of records has been spaced over. If a read or write operation was
being executed (SPACE false) the assertion of LRCSD signifies the operation is over.
In both cases the done flip-flop is set and DONE (1) is asserted. If ERR (1) asserts during the operation a done sequence will be triggered before the operation is completed. Certain errors will interrupt
an operation by asserting ERR (l) as soon as they are detected. Other errors will allow the operation to
terminate normally. (See Paragraph 6.6.7.)
When DONE (1) asserts and the tape transport comes to a stop (TUR true) DONE DELAYED (1)
asserts in turn asserting (GET NEW CMD) to the bus interrupt logic and SET CUR to the operation
start logic.
Some conditions that will assert DONE DELAYED (1) without waiting for TUR to come true are:
1.

2.
3.
4.
5.

An illegal command [ILC (1)]
Reaching BOT during a space reverse operation
Reaching BOT during a rewind operation that was commanded by the processor
Deselecting the drive
When the transport starts a rewind from a local command.

6-54

YES

0'\
I

Vl
Vl

11-4142

Figure 6-28

Operation Done Flow Diagram

REWIND
(FIG. 6 -13) {

SPACE REV

BOT

FROM
) {-=S=E=LR-=--_ _ _- - \
(
TAPE TRANSPORT
RWS

(FIG.6-18)

CARRY OUT 2
SPACE

(FIG.6-13)

{
SPACE

0\
I

(FIG.6-19)

DONE
(

FROM
)
TAPE TRANSPORT

r - - - - ' i DE1~rED
(SET)

(SET)

LRCSD

0\
(FIG.6-31) ....::;E.:..:R.:..:R.:..:(:..;.1:...)_ _ _ _ _ _ __
(FIG.6-16)

TUR

GO STROBE

(RESET) ~I

DONE
FF
(C3)

DONE
DELAYED
O.S.
(C3) 0

BTE CHECK
(FIG. 6-13)

(FIG
6-16)

(FIG.6-31)

o
(FIG.6-31)

I LC (1J

NOTE

Designations in parenthesis refer to engineering drawings
containing corresponding logic.
11~4t33

Figure 6-29

Operation Done Block Diagram

6.6.7

Error Logic (Figures 6-30 amI 6-31)

ERR (l) is asserted by any of the error conditions that could arise within the system. When ERR 0)
comes true it sets bit 15 in the command register and triggers a done sequence. The error conditions
that assert ERR (1) are in two classes: those that assert ERR (1) immediately and abort the current
operation, and those that allow the operation to terminate normally. In the latter case ERR (l) will
become true with the assertion of LRCSD.
Errors that abort an operation are:
NXM
BGL
ILC
BTE
Errors that allow an operation to terminate normally are:
RLE

eRE
PAE
EOFF
End of Tape Error
NXM and BGL are error conditions that arise from the execution of an NPR bus cycle.
ILC is asserted under the following circumstances:
II

II>

When the processor attempts to access the command register while the controller is busy executing a command (SEL lOUt asserted while CUR DEL 1 is false).
When an on-line transport is deselected while an operation is being executed (SELR negates
while OFF LINE and CUR DEL 1 are false).
The controller attempts to initiate an operation on a deselected transport (GO STROBE 2 (1)
asserts while SELR is false).
The controller attempts to initiate a write operation on a write protected transport (GO
STROBE 2 (1) asserts while WRITE ENB and WRL are true).

BTE is asserted when a read strobe occurs during the gap shutdown or settle down periods providecj. no
BGL, NXM, or ILC errors exist. (RDS asserts when either SDWN or GSD is true and the following
are false: BGL, NXM, ILC.) Gap shutdown is the period between the end of a record and the beginning of the settle down interval (from the assertion of LRCS to the assertion of SDWN).
RLE (1) is asserted when a read strobe occurs after an overflow condition has been sensed except if the
read strobe is a CRC or an LRC strobe (READ STB asserts when OVERFLOW (1) is true and CRCS
+ LRCS is false).
CRE (1) is asserted during a read or a write operation when a read strobe occurs and a CRC error
exists. (RDS asserts while CRCE and READ + WRITE are true.)
PAE (1) is asserted during a read or a write operation when a read strobe occurs and either a vertical
parity error or a longitudinal redundancy check error exists. (RDS asserts while either VPE or LRCE
is true and READ + WRITE is true.)

6-57

EOFF (1) is asserted when a file mark (FMK) is received from the tape transport.
An end-of-tape error is asserted when the end-of-tape marker is sensed during a transport operation
other than rewind or space reverse (EOT asserts when REWIND and SPACE REV are false).

6-58

SEllOUT LO

FMK

SEL lOUT HI

NO
EOFF 111

ILC 111

YES

11-4137

Figure 6-30 Error Sequence
Flow Diagram
6-59

CUR DEL (0

(FIG. 6-16)

''''- ,- '"

{

SEL lOUT LO
SEL lOUT
OFF LINE

r-..::.:...:.....;=----.! [j
SEL R

G
FROM
) { WRL
TAPE TRANSPORT
(FIG. 6-1:3)

_ _ _-!.:IL:,:C::...!.!(1!..)_ _ _ _ _1

_ _ _ _ _ _ _ _ _ _ _ _ _ _ (FIG. 6-29
AND 6-16)

ILLEGAL
COMMAND
FF

}---.!.._ (FIG. 6-16)

WRITE ENB

C (C4) 0

ILC (1)

:>O-':":":::'..!..!..!..--~A

GO STROBE 2 (1)

(FIG.6-16)

(F IG. 6 - 18) ~B=G=L=+=N~X::.:M=---_I
ILC (1)

(FIG. 6-29)

FROM
)
( TAPE TRANSPORT

DONE (1l.
CUR DEL (1)

(FIG.6-16)

{

CUR DEL (1)

(C5)

NXM
(FIG. 6-1:3) READ + WRITE

C (C5) 0

(

FROM
)
TAPE TRANSPORT

{~~D!:!:RS~C_E

CRE(O

(FIG. 6-18)

{

BGL

_ _ _S - i - - . . "

EOT
-="::~----.

CHG TU ENB

~~~~SPORT) {- ': .:~:. .: .:. :N"_

BTE

}-::....:...:=--;-+---~----------- (FIG. 6-16)

(FIG. 6-14)

GSD
ENABLE
FF

(TAPE

RDS
=:S~D~W~N====~--------r~~
___

GSD

(SET)

(FIG. 6-29)

{

SPACE REV
(FIG. 6-1:3)

{

REviiNi5
(FIG. 6-18 AND 6-24)

(FI G. 6 - 18) _C:..;.A.:.:.R;.:.R:..;.Y-'O::.cU::.cT:......=2c....!.:(S:..:Ec..:.T.!...)_~

I~O:...:V~E~R~F~L~O~W~(.!...l~)_-L_ _ _ _ _ _~

OVERFLOW
FF
(C5)

RLE (1)

READ STB
(FIG.6-19)

{

CRCS + LRCS

LRCE

(FIG. 6-19) LRCSD

(TAPE.~~~~SPORT) -..!~':':~:----J
{

(FIG. 6 -1:3) _..:.R;;:E:.;..A;;:D_+:.....:..:W.:..:Rc;..IT:...:E=--_ _ _ _---.J

PAE (1J
DpARITY 1
ERROR
FF

C (C4) 0

EOFF (0

ENDOF'r--~~~-----------~
FILE
FF
(C5) 0
NOTE
Designations in parenthesis refer to engineering drawings
containing corresponding logic.
11- 4135

Figure 6-31 Error Sequence
Block Diagram
6-60

6.6.8

Intermpt Bus Cycle (Figures 6-32 and 6-33)

An interrupt bus cycle is initiated if the interrupt enable bit (bit 06) in the command register is set and
anyone of the following occurs:

GET NEW CMD asserts from the done logic.

The tape comes to a stop (TUR asserts) after a rewind operation.

The processor requests an interrupt.

The setting of the BR interrupt flip-flop starts the interrupt sequence. The flip-flop is set via a gate
enabled by INT ENB (1) from the command register. The other gate input comes from the set interrupt one-shot or from the processor. The set interrupt one-shot is triggered by GET NEW CMD from
the done logic (if an interrupt bus cycle is not already in progress) or when the tape transport stops
(TUR asserts) after a rewind operation (BOT is reached when CU READY and RWS are true). The
processor initiated interrupt is accomplished by the processor asserting SLCT lOUT La and DOO
after it has set the interrupt enable bit in the command register.
NOTE
Processor initiation of an intermpt is done for special software purposes and is not a normal occur-

rence of tape system operation.
When the BR interrupt flip-flop is set, BR INT (1) asserts enabling the Unibus request logic. The
Unibus request logic asserts BR OUT which becomes BUS BRX to the Unibus. The value of X is
determined by the priority jumpers and may be 4, 5, 6, or 7 (usually 5). The processor responds to the
bus request with BUS BGX IN which becomes BG IN and enables the Unibus acquisition logic. The
Unibus acquisition logic asserts BUS SACK to the processor which responds by negating BUS BGX
IN. The acquisition logic checks for BUS BBSY (by some other device) and if it finds the bus free
asserts BUS BBSY to the Unibus (indicating bus mastership) and BR MASTER to the interrupt
circuits. BR MASTER becomes BUS INTR and is placed on the Unibus along with BUS D02-D08,
thereby commanding the processor to initiate an interrupt routine starting at the address specified by
BUS D02-D08 (address = 224). Processor acceptance of this data is indicated by its assertion of BUS
SSYN to the TMB 11. BUS SSYN becomes SSYN and triggers the interrupt done logic. The interrupt
done logic asserts INT DONE B which completes the interrupt bus cycle by resetting the interrupt flipflop and acquisition circuits.
606.801 BUS BGX OUT
A BUS BGX IN from the processor is passed from one system device to another in daisy-chain fashion
until it reaches the device that issued the BUS BRX. A BUS BGX IN received by the TMBII is gated
back to the Unibus as BUS BGX OUT if the controller is not making an NPR bus request (BUS NPR
false) (NPR requests take priority over all BR requests) and one of the following conditions exist:

BR MASTER is true (TMBII is presently bus master).

BR INT (1) is false (TMBll did not issue the BUS BRX that caused the BUS BGX IN).

6-61

t BOT

START

t (GET NEW CMO)

t SLCT 1 OUT LO
O .... BBSY FF
• BR MASTER

NO
• BUS BBSY
• BUS INTR
• BUS 0,82-011'8
SETBR

SET INT (1)

BUS BBSY
BR MASTER

BUSINTR
BUS 002-008

'X = 4, 5, 6 or 7

11-4138

Figure 6-32 Interrupt Bus Cycle
Flow Diagram
6-63

U N I

B U S

BUS
BR X*

INT ENB (1)

BUS
BG X*
IN

BUS
SACK

BUS
BBSY

BUS
INTR

BUS
BG X*
OUT

BUS

o 12l2- 0 1218

BUS
SSYN

SLCT lOUT LO
(FIG. 6 -13

(FIG. 6- 16)

){

( FROM TAPE
TRANSPORT

o I2lI2l
INTERRUPT
ENABLE
O.S.
(09)

INT ENB (0)

(INTERRUPT ENABLE PULSE)

(09)

RWS
TUR

UNIBUS
REQUEST
LOGIC

M7B21

(09)

INTERRUPT
VECTOR
JUMPERS
M7821

UNIBUS
ACQUISITION
LOGIC
M7821

BR INT (1)

•

GO STROBE 2 (I)
(RESET)

~ (C4).J

SETBS--

SET
INTERRUPT
O. s.
(09)

~(SET)
SET INT (1)

(09)

BR MASTER

BR
INTERRUPT
FF

...-BR INT (1)

(FIG. 6-18)

7821

-BUS NPR

17B21 \

BG OUT

(09)
(RESET)
INT DONE B

(GET NEW CMO)

(09)

r---

SET INT (1) (SET)

PRIORITY
JUMPERS

BG IN

CU READY
BOT

(C4)

(FIG. 6-2 9)

PRIORITY
JUMPERS

BR OUT

1
INTERRUPT
FF

(FIG. 6-1 6)

PRIORITY
JUMPERS

INTERRUPT
DONE
LOGIC
M7821

SSYN

(08)

NOTE
Designations in parenthesis refer to engineering drawings
contalnino corresponding logic.

X=4,5,6or7.

11-4130

Figure 6-33 Interrupt Bus Cycle
Block Diagram
6-64

6.6.9

Timing Diagrams

Timing diagrams of various tape operations are shown in Figures 6-34 through 6-41. These diagrams
portray specific tape operations such as reading a record of three data characters, reading a record of
two tape characters in the core dump mode, etc. The purpose of these diagrams is to illustrate overall
TM B II operation as described in previous paragraphs.

SEL 2 OUT La H

DOO H

GO BIT H

GO STROBE 1 H

GO STROBE 2 H -+______+-'

SET - t - - - - - - - - - - '

SELR L -\-------..:.'~----_+_r_----------r- -- - ---- - -------ILC

H __

__________

+_~

CU READY H
CUR DEL H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

_____________

11-0382

Figure 6-34

TUR H

Start of Tape Operation

~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

CU READY H

LRC H _ _ _ _--I

I\-----II--------..Jn....- - - - I I - - - - - - -..- _ _ _-+-_ _

--Jn. . ___

S DW N H _ _ _ _- - I f----++' ' - - - - I I -_ _ _ _

-II-_ _ _ _ _ _--'

GO~f----~~--I~__----~n~--~/,~,-----------MTBRC _____7_7_77_7~5___~_ _ _7_7~7_77_6_ _ _ _~_ _ _7_7_7_7_7_7______L -_ _ _ _O~O~O~O~O~O__
11- 0385

Figure 6-35

Spacing Forward Three Records

6-65

TURH

CU READY H

LRC H

: ~

SOWN H

GO H
MTBRC

"-0387

Figure 6-36

TUR H

CU READY H

Spacing Reverse Three Records

l'-_______________________

....J

____________________~

LRC H _ _ _--1/

SDWN H - - - - - I i ; - - - - - - - 1 , - - - ' '-_ _--1_-+-----.....1

GO H

BTE

~~------_+--~~----~~4_--------------------;

777775
MTBRC

ERR H

Figure 6-37

~ 777776
11-0386

Spacing Forward Three Records, Bad Tape Error Appearing in First Record

6-66

CU READY H ~~______________________________________________________________________

I-- 100",s--l
RDS H ________

~/~

Sl-----

~/~

~"------

NPR ENB H ---------t/

MASTER H _______

C L R B B S Y H _______

rLl-----'

~/,I-'

- - - - - - -......

MTBRC ____________7_7_7_1_2_3_~________~~------~-7-7-7-1-2-6--------------_____________

MTCMA ______________12_3_1_2_3__~________d __ _ _ _ _ _ _ _~_ _'2_3_'_2_6___________________________

CRCS _________________________________________- - J

CRCE _________________________________________

.--,
I
~

I ________________________
___L!

LRCS ______________________________________________________

r-'

r-,

VPE ______ ,f
~

r-,

,II'

....
I

r-"

I __ I___________
LRCE __________________________________________________________- L

r-,

I
I
I
I
I
!
//~--~----~;'~i-L!--~I------~/,~I-!~~!-----------11-0383

Figure 6-38

Reading Record of Three Data Characters

6-67

CU READY H ~~_____________________________________________________________
GO H ~~_________________________________________________________

EVErl CHAR H

RDS H --------f/ /

NPR INT H - - - - 1 / ,I-'- - - - - - - I I - - - - . J

CLR BBSY H - - - - - - - I f ,1-'____________-11-________..... L._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

MTBRC ______________7~7~7~12~3~____________~______~7~7~7~12~4________________

MTCMA ______________1~2~3~12~3_______________ L_ _ _ _ _ _ _ _l~2~3~12~4________________

CRC S ________________________________----1

LRCS __________________________________________----1

READ STB H ______________

~~~,I_,------------11-3992

Figure 6-39

Reading Record of Two Tape Characters in Core Dump Mode

6-68

CU READY H

WRS H

GO STROBE 2H

NPR INT H

MASTER H

CLR BBSY H

MTBRC 777775

1777777

1777776

OVERFLOW H

WDR

r--- 400,"5

400,"5----------1

nl....-..-

~~'I--'-IL/

RDS H

CRCS

-I-

____________________________~Il~_________
,r- ,
~,

CRC ERROR

LRCS

--------------------------------------------------~/~/----~

~~----.,

LRC ERROR

r-'

r-,

,--..,

' I
I
I
- - - - - - - - - i / , / - '_-_:..'-.1'--1;',1-'----l'---!..-f/,I-'-':"'--'---1/,1-'-----'--~/,I-'------:'-......:.'---I

VPC ERROR

'1-0384

Figure 6-40

Writing Record of Three Data Characters

6-69

CU READY H ~~_____________________________________________________________________________

GO STROBE 2 H

I-~

EVEN CHAR H

100 ~s ----.j

WRS H-+__+-____~

~--------------------------------------------

NPR INT H +-_~

CLR BBSY H+-______-J/I~____________~-------------------------------------------------------__
______+-________________________________________________________
MTBRC~

~~~~~~~

MTCMA-r__~~~~12~3~1~2~4________4-________________________________________________________

OVERFLOW H __~______~

WDR

f--- 100 ~s ---11------- 400 ~s

RDS H

"I-

400 ~s

----I

----.';'~r____1L..,_(-----T;'---1L-.,~

CRCS ______________________________________________________~~~_____________________

LRCS __________________________________________________________________

11-3993

Figure 6-41

Writing Record of Two Tape Characters in Core Dump Mode

6-70

CHAPTER 7
M8926 THEORY OF OPERATION

7.1 GENERAL (Figures 7-1,7-2, and 7-3)
Figure 7-1 is a simplified flow diagram of the M8926 Interface board. The CSET command from the
controller triggers a drive start-up sequence. The start-up sequence signals the drive to start the capstan motor and introduces a delay period for the capstan motor to get up to speed [1.14 m/ second (45
inches/second)] before enabling a read or write sequence.
All commands from the controller except rewind will cause a read sequence to occur. The read
sequence transfers data from the drive to the M8926 board. A write command (CWRE) must be
asserted by the controller to enable a write sequence. If a write command is asserted by the controller,
data is transferred from the controller to the drive to be written on tape (write sequence). The data
written on tape is then read back via the read sequence. This read-after-write feature allows the recorded data to be checked for errors by the M8926 board. The read-after-write data is made available to the
controller where it can be accessed by the processor for maintenance purposes. During normal operation, read data is not accepted by the controller unless a read command is asserted.
When the read circuits detect the end of the record, a drive stop sequence is triggered. The stop
sequence signals the drive to stop the capstan motor and initiates another delay period. The delay
allows the capstan motor to slow down to a stop before the command operation is terminated.
The M8926 detailed flow diagram (Figure 7-2) provides a more detailed functional description of the
M8926 Interface board. This diagram should be read in its entirety while referencing the functional
block diagram, Figure 7-3. Subsequent sections in this chapter treat the M8926 board according to the
functional divisions shown in Figures 7-1, 7-2, and 7-3:

1.
2.
3.
4.
5.

Status/Command Logic
Drive Start-Up
Write Sequence
Read Sequence
Drive Stop

7-1

It will be helpful to reference Figures 7-2 and 7-3 as an overview while reading through Chapter 7.

NOTE
The block diagrams that foHow use logical AND and
OR symbols. It does not necessarily follow that a
corresponding gate exists on the controller logic
prints. The assertion of inputs A and B that cause the
assertion of output C may be represented on a block
diagram by a single AND gate, yet the engnneering
drawing may show that several circuit stages are
involved in the ANDing operation.
The signal names used on the functional block diagrams are the names used on the engineering circuit
schematics (CS prints). Where other signal names or
notes are used, they are enclosed in parentheses.

START

READ
SEQUENCE

TAPE DRIVE
SLOW DOWN
TO STOP

DONE

114780

Figure 7-1

M8926 Simplified Flow Diagram
7-2

MOTION CONTROL LOGIC IDrive up to speed):
1. Negates STOPISB) and asserts EMDISB) and SLAVE SET PLSISB) to drive.
2. Loads start-up time from the read channels
(and CWXG or EWFMK if asserted)
into motion delay counter.
3. Allows CLOCK(SB) to clock motion delay counter.
4. When counter counts out delay period, counting stops and:
A. ACCUSBI negates gating WRT CLK(SB) from drive to M8926
B. READING asserts enabling read channels.

READ LOGIC:
1. Transfers data characters and read strobes
from tape transport to controller.
2. Checks for vertical parity errors.
3. Detects file mark if present.
4. Detects end of record.

WRITE LOGIC:
1. Transfers data characters from controller to tape transport.
2. Generates vertical parity bit for each character.
3. Generates CWAS pulses for controller.
4. Generates AEC(SB) pulses for tape transport.
5. Generates CRC character.
6. Generates file mark character if WFMK command asserted.

End of record logic:
1. Generates GRGS and LRCS for controller.
2. Checks for CRG and LRC errors.
3. Generates read strobes (CRDS) for CRG and LRC characters.
4. I nitiates end of record decision delay.
5. Asserts AD CLA PLS after decision delay to initiate
drive stop sequence.

YES

MOTION CONTROL LOGIC IDrive stop)
1. Asserts EMD(SB) to drive.
2. Negates READING thus inhibiting read channels.
3. Loads stopping time into motion delay counter
via read channels.
4. Allows CLOCK(SB) to clock motion delay counter.
5. When counter counts out delay period, counting stops and:
A. ACCUSB) asserts inhibiting WAT CLK(SB) from drive to M8926
B. MOVE negates.

Write end of record:
1. Transfers CAC character to tape transport.
2. Generates AEC(SB) pulses for CRC and LRC characters.
3. Generates LRC STRB(SB) for tape transport.

11-4777

Figure 7-2

M8926 Detailed Flow Diagram
7-3

r wRiTE LOGic -,

~--------------~~
r-_~_:_:_:_C_W_D7_ _ _ _ _ _ _ _ _ _ _ _ _ _ _.:-,V//

WDo(ssl-WD7(SBI - ;

WRITE

RECISBI
CHANNELS

CWRS

PARITY
GENERATOR

EWFMK

--l

WDP(SBI

FilE MARK
GENERATOR

lI I

WRTClK(SBI

EPEVN

7TRK

CWRE

ENDOF
RECORD
GENERATOR

lRC STRB(SBI

L ---- ~

CPEVN

)-~~~----------------------------------------------~~--------l~
CDENS

DEN 0 (SBI
DEN 1 (SBI

CDENS
CSElO-CSEl2

SSOISB)-SS2(SB)

CSET

(
(

CRWD

COMMAND

CFWD

LOGIC

RWNDISBI
FWOISB}

CREV

REVISB)

CWRE

WRITE(SBI

CWFMK

EWFMK

CINIT
SLAVE SET PLSISB)
CWXG

STOP(SB)

CONTROLLER

ROC~

r i ---- -- ---- -- 1
READING

READ LOGIC

•

(C~DO-CR07. CRopl

g~~~uT

'\[

READ

(

CHANNELS

CROS

CFMK

L-.

ACCl(SB}
ClOCK(SB)

~L--R-D-O(-SB-I-_-RD-5-(S-S-I'-R-D-P(-SS-I--'1
L..-_----I

________________________

---,
RD ClR PLS

I
•

CCRCE

I
I

END OF
RECORD
DETECTOR

ClRCS
CVPE

"'1_r----------------------------~

FilE MARK
DETECTOR

I L ________

ROO(SB)-R07(SBI. ROP(SB)

CCRCS

RSDO(SB)

7TRK
WRTClK

EPEVN

--C='L":R':C7E---------t-.~

CEOT

~AI~.

TAPE
TRANSPORT

EMOISBI

START/STOP
MOTION
CONTROL

ERROR
DETECTOR

I
EFOR
.....----'---=<!!

L..: ____ J

END PT(SBI

CWRl

WRL(SB}

CSDWN

SDWN(SB)

CSElR

TRANSPORT

MOL(SB)

CTUR

STATUS

TUR(SBI

CRWS

lOGIC

CBOT

RWS(SB)
BDT(SB)

C7CH

7CHISBI
7TRK
11-4799

Figure 7-3

M8926 Block Diagram

7-4

7.2 STATUS/COMMAND LOGIC (Figures 7-5 and 7-6)
7.2.1 Command Logic
Some operational commands are coupled from the controller to the drive via passive logic circuits.
Other commands that must stay asserted during the entire operation are latched up in flip-flops set by
CSET from the controller. Note the conversion of CDEN5 to DENO (SB) and CDEN8 to DENl (SB)
during the latch-up process.
CSELO-CSEL2 select a slave unit via a 3-bit code. The 3-bit code is latched up in the slave select latchup flip-flops which output SSO (SB) - SS2 (SB) to the drive. The input code from the controller is
compared to the output code in the slave select comparator. If the two codes do not match, the latchup flip-flops are clocked, forcing SSO (SB) - SS2 (SB) to agree with the select code from the controller.
An AND gate must be enabled by MOVE before clocking of the flip-flops can occur. MOVE is
asserted true during every command operation except rewind. Thus a new slave drive cannot be
selected during a read, write, or spacing operation. Note that a bit reversal takes place in the latch-up
flip-flops where the CSELO, 1, and 2 input bits become bits SS2 (SB), 1, and 0, respectively, in the
output.
Figure 7-6 shows four signal lines coupling fixed potentials to the host drive. These signal lines are not
used but the host drive requires that the lines be held at a fixed voltage level. Three of the lines [D R V
CLR PLS (SB), INIT PLS (SB), 1 RD (SB)] are tied to +3 V and the fourth (SLAVE BUS ENBL) is
tied to ground.
7.2.2 Status Logic
Some status signals are directly coupled from the drive to the controller while others such as RWS (SB)
and MOL (SB) undergo conditional gating. Rewind status, RWS (SB), from the drive negates at the
end of SDWN (SB) simultaneously with the assertion ofTUR (SB) (Figure 7-4). A timing requirement
within the controller demands that CRWS negate before CTUR asserts. This requirement is met by
ANDing RWS (SB) with SDWN DELAYED, thus producing the proper CRWS timing as shown in
Figure 7-4. SDWN is delayed approximately 100 ns, producing SDWN DELAYED, before being
ANDed with RWS (SB). This is done to eliminate the possibility of a spurious assertion of CRWS
should SDWN (SB) negate while RWS is still true.

RWS(SB)

1+-- 10ms--l
SDWN(SB)

(SDWN DELAYED)

TUR(SB)

CRWS

--l I--

-100 ns
11-4779

Figure 7-4

RWS (SB) and CRWS Timing Diagram

7-5

CSELR is negated for I IlS while a new drive is being selected by the slave select logic. This is accomplished by the gating of MOL (SB) with the 0 output of the slave select one-shot. The Ills delay allows
settling of the select code before CSELR is asserted for the new drive.
When a 7-track drive is being used, 7CH (SB) is asserted from the drive, causing the assertion ofC7CH
to the controller and R7CH to the 7TRK flip-flop. When SET asserts, 7TRK becomes true to indicate
the presence of a 7-track slave drive to the M8926 board. Note that the assertion of EDENS will also
cause 7TRK to become true at SET time. Compatibility between the TV 10 and TV lOW drives
requires that both EDENS and R 7CH cause the assertion of 7TRK at SET pulse time.

7-6

START

YES

(FILE MARK
CHARACTER)
(READ FLOW)

--.l
--.l

WRITE(SB)

DENO(SB)

7 TRK
(WRITE AND
READ FLOWS)

(FIG.7·B)
llA778

Figure 7-5

Command Latch-Up Flow Diagram

CEOT

•

~
~
~
~

CBOT

•

CWRL

CTUR

TO
CONTROLLER

BOT(SB) <
DRV CLR PLS(SB)
+3V
INIT PLS(SB)

SLAVE BUS ENBL

WRL(SB) <

SLAVE
SELECT
LATCH UP
FF
(2)

CSEL2-CSELO

SSO(SB)-SS2(SB)

(CLOCK) •
FROM
TAPE
DRIVE

SLAVE
SELECT
O.S.
(2)

SLAVE
SELECT
COMPARATOR
B
(2)

A
(SOWN DELAYED)
DELAY
(2)
> CREV

CSDWN

•

MOL(SB)

G=0

>CRWD

PCLR
(HOST DRIVE)
FROM
CONTROLLER

R7CH

C7CH

)CINIT

G?
G?
B

7TRK

COMMAND
LATCH UP
FFS
(1)

7TRK
FF
(4)

REV (SB)

RWND(SB)

•

•
TO
TAPE
DRIVE

WRITE(SB)

," CFWD

MASTER CLEAR • (GENERAL
)
DRIVE RESET

," CWRE
( FIGURES 7·12, 7.14)
AND 7·21

•

TUR(SB) <

CRWS

CSELR

TO
HOST
DRIVE

IRD(SB)
END PT(SB)<

EFOR

~
./

FWD(SB)

(FIG 7·14)

cl---------{

A. STATUS
11-4795

,CWFMK

,
,

EWFMK

,CPEVN

EPEVN

,CDEN 5

EDEN 5

(FIG 7·9 AND 7·12)
(FIG 7·12 AND 7·14)

DENO(SB)

,/
B
DEN1(SB)

,CDEN 8

CSET

~
V

DEN2(SB)
(CLO~K)

SET

NOTE

(FIGURES 7·9, 7·12 AND 7·14)

•

Designations in parenthesis refer to engineering drawings
containing corresponding logic.

B. COMMAND
11-4796

Figure 7-6 Status/Command Block Diagram
7-9

7.3 DRIVE START-UP (Figures 7-7, 7-8, and 7-9)
7.3.1 Drive Start Signals
The SET pulse starts the command operation in the drive by:

Setting the EMD flip-flop and asserting EMD (SB) to the drive

Asserting SLAVE SET PLS (SB) to the drive

Setting the MOVE flip-flop, thereby negating STOP (SB) to the drive.

MOVE remains asserted and holds STOP (SB) false during the entire command operation. During a
rewind operation, the MOVE flip-flop is not set. In this case, SLAVE SET PLS negates STOP (SB) at
SET time, which is sufficient for the drive to start the rewind sequence.
7.3.2 Start-Up Delay
The output of the EMD flip-flop loads the motion delay counter with delay data set onto read lines
RRDO-RRD6, RRDP by the drive. Bit 13 ofthe counter is preset to a 1 and gates in the clock pulses.
The clock pulses are obtained from a divide-by-four counter which receives CLOCK (SB) pulses from
the slave bus. An output from the divide-by-four counter is obtained after the first two CLOCK (SB)
pulses and every four CLOCK (SB) pulses thereafter. When the delay counter has been clocked
through the delay period, bit 13 of the delay counter is counted down to 0 and bit 14 is asserted. At this
time:

Input clock pulses to the delay counter are inhibited.

READING is asserted, enabling the read sequence.

ACCL (SB) is negated to the drive, thus gating WRT CLK (SB) pulses in from the drive for
the write sequence.

If the command is CWXG or CWFMK, an extended interrecord gap is generated prior to writing the

record. CWXG or EWFMK, if asserted, inputs into the delay counter, increasing the delay time and
allowing the tape to travel an extra distance before the read and write sequences are enabled. The delay
increase is from 8.99 to 95.00 ms for a 9-track drive, and from 15.26 to 101.3 ms for a 7-track drive.
The CWXG and EWFMK inputs to the delay counter are via a gate enabled by ACCL. Thus only the
start-up time or gap prior to the record is extended.

7-11

I-il~!----DRIVE START·UP

---""'IGI-

RECORD TRANSFER
OR SPACING
OPERATION

-~If<!OS~--- DRIVE STOP---.....>l1

CS±T
MOVE

~r----------------

EMD(SB)

;,...-_ _ _ __

_ 1 2 3456
CLOCK(SBH

1 1 1 1 1 1"'1 1 1 1 1 1 1 1

..1_11-1..1-'-'-'---'--'--'-'-

\-II--- STA RT UP DE LA Y-----<o>\
CLOCK TO
""-28I's"",,
I
COUNTER ~
A CCL(SB)
READING _ _ _ _ _ _ _ _ _ _ __

AEMD~
BIT 13

---.J

BIT 14 _ _ _ _ _ _ _ _ _ __

BIT 15 _ _ _ _ _ _ _ _ _ _ __

RDCLRPlS _____________________

11·4775

Figure 7-7

M8926 Timing Diagram

7-12

(FIG. 7·5)

1 - EMD FF

INHIBITS MOTION
DELAY COUNTER

YES

l-BIT14
CLEARSCRC
AND LRC
GENERATORS

(FIG.7·13)

(FIG.7·11)

114774

Figure 7-8

Drive Start-Up Flow Diagram
7-13

(FROM HOST DRIVE)

(FIG 7-6)

SLAVE SET PLS(SB)

_ _S_E.:..T_ _--.-_ _- '

___
~

}

STOP(SB)

(TO TAPE DRIVE)

CRWD

-=
ACC L

MOVE
FF

Ir~_O_V_E__r _ - - - L - - - - - - - -.. (FIGURES 7-9, 7-12, 7-14 AND 7-21)

(2)

FROM
CONTROLLER

(CLEAR)

(FIG 7-6)

EWFMK

(BIT 15)
16-BIT
MOTION
DELAY
COUNTER
.. (3)

CWXG

lr--

-.J
I

(FIG 7-14)

READING

RRDO-RRD6, RRDP

+>-

(BIT 14)

ACCL(SB)

~(COUNTER
,CLOCK
)
CLOCK(SB)
FROM
( TAPE DRIVE)

I
(CLEAR)

(FIG 7-21)

74
COUNTER
(3)

.. (FIG 7-14AND 7-21)

(TO
)
TAPE
DRIVE

)
(BIT 13)

RnrIRPI~

( FIG 7-12 AND)
7-14

NOTE:

Designations in parenthesis refer to engineering drawings
containing corresponding logic.

~ ~, .. -,--,

.. (TO TAPE)
DRIVE
114793

Figure 7-9

Start/Stop Control Block Diagram

7.4

WRITE SEQUENCE (Figures 7-10, 7-11, and 7-12)
Nine-Track Normal

7.4.1

Write Data - If a write command is asserted by the controller, CWRE will be true, allowing
the SET pulse to set the WRITING flip-flop. The assertion of WRITING loads the end-of-record
counter, which is preset to a count of 8. The 8-bit output from the counter gates R WRT CLK pulses
from the drive to produce WRITE STROBE pUlses. The assertion of each WRITE STROBE pulse
will:

7.4.1.1

Latch up write data from the controller, making it available to the drive via the output gates.

Assert CWRS to the controller to extract the next character from memory.

Assert REC (SB) to the drive and to the CRC generator.

Vertical parity is produced by a parity generator that monitors the eight write lines and outputs a true
or false parity bit according to the number of 1 bits and whether odd or even parity is specified
(EPEVN).
The write logic contains a circuit to detect a zero-character condition when even parity is specified.
Such a condition results in a blank space on the tape which cannot be sensed by the read logic. Should
an attempt be made to write a zero character with even parity, the zero character detector output
would assert WRX3, thereby generating a 1 bit on the third write channel. A single bit character
demands a 1 parity bit when EPEVN is true. The parity bit is also artificially generated via the zero
character detector output, which asserts WRXP to the parity write channel.
The CRC generator receives each data character from the write channels. REC (SB) pulses clock the
,generator which develops the CRC character during the body of the record.
Write-End-of-Record - When the data transfer has been completed, CWDR and WRITING
are negated, and REC and CWRS strobes are inhibited. The sequence is illustrated in the data transfer
timing diagram (Figure 7-10). It can be seen in Figure 7-12 that data characters are moved from
memory to tape in two steps: first from memory to the write data latch-up register, and then from the
register to the transport write logic. The last four characters of a record are shown in Figure 7-10.
CWRS 1 issued to the controller extracts data character 2 from memory, which moves through the
controller and over to the M8926 write data latch-up register. The next write clock pulse (R WRT
CLK 2) generates WRITE STROBE 2, REC 2, and CWRS 2. WRITE STROBE 2 latches up ,data
character 2 in the register, making it available to the transport write logic; REC 2 records data character 2 on tape; and CWRS 2 extracts data character 3 from memory. The next CWRS pulse (CWRS 3)
extracts the last character (data character 4) from memory. R WRT CLK 4 generates WRITE
STROBE 4 to latch up the last character, and REC 4 to record it on tape. CWRS 4 is issued to the
controller which, having sensed that the last character has been transferred, inhibits a data extraction
from memory (no NPR bus cycle) and negates CWDR. The negation ofCWDR conditions the WRITING flip-flop to reset. The trailing edge of R WRT CLK 4 clocks the flip-flop reset, thus negating
WRITING. When WRITING negates:
7.4.1.2

CWRS pulses to the controller are inhibited.

REC (SB) pulses to the drive are inhibited.

The end-of-record counter is enabled.

7-15

R WRTClK
WRITE
STROBE

REC(SBI

CWRS
DATA
CHARACTER ~+-...L-

DATA
CHARACTER 2

DATA CHARACTER 3

DATA CHARACTER 4

_______

From memory to

LU register

From memory to
latch~up register

From memory to

latch-up register

r,-----~~~------~
CONTROllER SENSES '\
THIS IS lAST DATA
CHARACTER

CWDR

WRITING

NOTE:
Each R WRT ClK pulse generates WR ITE STROBE which generates REC and CWRS. Arrows
shown only for R WRT ClK 1.
11-4776

Figure 7-10 Write Data Timing Diagram

7-16

WRITE STROBE pulses clock the end-of-record counter. When the counter reaches a count of 3,
CHK CHAR STRB asserts and:
1.

Switches the CRC character onto the write lines via the write data/CRC multiplexer

Enables the REC AND gate

The next WRITE STROBE pulse latches up the CRC character and generates a REC (SB) pulse for
the drive to record the CRC character. Three WRITE STROBEs later, the counter is at a count of 7
and again asserts CHK CHAR STRB which:
1.

Enables the REC AND gate

Asserts LRC STROBE via the enabled LRC STROBE AND gate

LRC STROBE asserts LRC STRB (SB) to the drive and resets the write data latch-up register, setting
all the write lines to zero. (The LRC character is generated in the drive.) The next WRITE STROBE
asserts REC (SB) to record the LRC character, and resets the end-of-record counter, thereby inhibiting
any further WRITE STROBE pulses.
7.4.2 Seven-Track Normal
Seven-track normal operation is identical to nine-track normal except for the write-end-of-record
sequence. In 7-track operation, both bits 4 and 8 of the end-of-record counter are preset to a 1. Thus
when the counter reaches a count of 3, the same conditions exist as a count of 7 in 9-track operation.
The 7 -track end-of-record sequence is:

7.4.3

The last data character

Three blank spaces

The LRC character

Reset end-of-record counter to terminate the write sequence
Nine-Track File Mark

7.4.3.1 Write Data - In file mark operation, EWFMK is true and forces the write data CRC multiplexer to output all Is into the write data latch-up register. After the Is are clocked into the register,
they are applied to the output gates. With EWFMK true and 7TRK false, an the output gates are
inhibited except 0, 1, and 4, thus outputting an octal 23 (9-track file mark) to the drive.
CWRE is true and CWDR is false for a CWFMK command. CWRE allows the SET pulse to set the
WRITING flip-flop. The first WR T CLK (SB) pulse asserts WRITE STROBE and then REC (SB)
but, due to CWDR being false, also resets the WRITING flip-flop. Thus one WRITE STROBE and
one REC pulse are issued for the file mark character.
No CWRS pulses are returned to the controller in file mark operation.

7-17

7.4.3.2 Write-End-of-Record - The write-end-of-record sequence for a 9-track file mark is identical to
the write-end-of-record sequence for 9-track normal except that the CRC character is skipped and only
the LRC character is written. The end-of-record counter must reach a count of 7 before a CHK CHR
STRB is asserted. At this point, the same conditions exist as in the 9-track normal mode; thus the LRC
character is recorded and the write sequence is terminated. The 9-track file mark end-of-record
sequence is:
1.
2.
3.
4.

The last data character (the file mark character)
Seven blank spaces
The LRC character
Reset end-of-record counter to terminate the write sequence

7.4.4 Seven-Track File Mark
The write data sequence for the 7-track file mark is identical to that for the 9-track file mark except
that 7TRK is asserted to the output gates via the enabled EWFMK gate. Output gates now enabled are
0, 1,2, and 3, thus outputting an octal 17 (7-track file mark) to the drive.
The end-of-record sequence for the 7-track file mark is identical to that for a 7-track normal sequence.

7-18

(Fig 7·8)

ALLOWS CLOCKING
OF END OF
RECORD COUNTER

RESETS WRITE
DATA LATCH

YES

1-+WDO(SB),1,2,3
(7·TRACK FI LE
MARK)

WDO(SB)-WD7(SB) ,
WDP(SB)
(DATA CHARACTER)

1-+WDO(SB), 1, 4
(S·TRACK FILE
MARK)

CLOCKS END OF
RECORD COUNTER
TO ZERO THEREBY
INHIBITING ANY
MORE WRITE

YES

(Fig 7·20)

11-4792

Figure 7-11

Write Flow Diagram
7-19

~.---.~....

7TRK
(FIG 7·6)

{
EWFMK

(WRITE DATA.)

> CWDO-CWD2. CWD4-CWD7

(~~~~ROLLER) >~_~C~W_D_3'-__rl________________-,

\ CRC OR 1',

{

~ .....w

ZERO

CHARACTER'~

I I ..I
I

EVEN PARITY

(FIG. 7·6)

EPEVN

DETECTOR
L_(..;5)_ _ _....

REC (SB) (CLOCK)

CRC
GENERATOR

IWCRO-WCR7.
WCRP

WRITE
DATAl
CRC

WD7(SB)-)

IWRITE

J WDO(SB).
WDP(SB)

(CLOCK)

(NOTE 2)

(TO TAPE
)
.. TRANSPORT

(RESET) IREGISTER
(5)

MUX
(5)

(5)

(SWITCH)
AEMD (RESET)
(FIG 7-9)
WRXP

PARITY
GENERATOR
(5)

-.l

TO
)
CWRS
( CONTROLLER ••.---------------------------------------------------------------------------~

(FIG 7-6)

......

CWRE
FROM
(CONTROLLER)

{

EWFMK

CWDR

(FIG 7-6)
WRITING

.. D

;

WRITING

FF
FROM
)
( TAPE
TRANSPORT

R WRTCLK

(1)

1'-C_ _--'
(FIG 7-14 AND 7-21)

(FIG 7-6) 7TRK (PRESETS 4 BIT)

-I

WRITING (LOADS COUNTER)

WRITE STROBE (CLOCK)

END
OF
RECORD

REC(SB)

TO TAPE
LRC

STRB(SB)..

( TRANSPORT)

COUNTER (2 BIT)

MOVE (ENABLES COUNTER)

}

(1)

NOTES:
1. Designations in parenthesis refer to engineering drawings

(1 BIT)

(FIG 7-9)

containing corresponding logic.

2. Note reversal of write data sequence with respect to
input from controller.
11-4794

Figure 7-12

Write Block Diagram

7.5

READ SEQUENCE

7.S.1 Read Data (Figures 7-13 and 7-14)
RSDO (SB) pulses from the drive assert COMP RD STRB which:
1.

Clocks the read data latch-up register

Triggers the read strobe one-shot, asserting CRDS to the controller.

Uses a second output from the read strobe one-shot (CHECK REG PLS) to dock the CRC
generator and the LRC generator (and the LRCS flip-flop in the end-of-record detection
sequence, Paragraph 7.5.4).

When the read data latch-up register is docked by COMP RD STRB, read data is made available to
the controller via the read data output multiplexer. (Note the order reversal of the read data in the
latch-up register.) When READING is true, the multiplexer selects the data character from the read
lines for the controller. When READING is false (for example, after a data transfer operation), the
LRC character is output to the controHer for maintenance purposes.
7.S.2 Error Detection (Figures 7-13 and 7-14)
Read data ERD7-ERDO, ERDP are checked for CRC, LRC, and vertical parity errors. Each data
character is clocked into the CRC and LRC generators by the CHECK REG PLS. At the end of the
record, the CRC character is compared with the contents of the CRC generator, causing the
CR 7-CRO, CRP output to be all zeros. The CRC error detector looks for an all zero output from the
comparison. If the CRC generator output is not an zeros when CRCS is true, CCRCE is asserted to
the controller, indicating a CRC error.
In a similar manner, the LRC character is compared with the contents of the LRC generator, causing
the LR 7-LRO, LRP output to be all zeros. The LRC error detector looks for an all zero output from
the comparison. If the LRC generator output is not all zeros when LRCS is true, CLRCE is asserted to
the controller, indicating an LRC error.
CRC and LRC error outputs are enabled only when the drive is executing a forward motion command. (This is due to the location of the CRC and LRC characters at the end of the record.) Accordingly, EFOR must be true for CCRCE or CLRCE to assert.
Each data character occurring during the body of a record is checked for vertical parity error by a
vertical parity error detector circuit. If a parity error is sensed by the detector, CVPE is asserted to the
controller. CVPE is inhibited during CRCS and LRCS times as the ERDP bit does not represent
vertical parity of the CRC and LRC characters.
7.5.3 File Mark Detection (Figures 7-13 ami 7-14)
The file mark detection logic monitors the read data and outputs CFMK to the controller if a file mark
is detected. Three conditions must be met before the record is identified as a file mark:
1.

There must be two characters and only two characters to the record.

Both characters must be file mark characters.

The second file mark character must be followed by at least eight blank spaces.

7-22

To meet condition 2, read data (ERD7-ERDO, ERDP) is examined by the file mark character detector
which outputs FMK CHR if a file mark character is sensed. A file mark character flip-flop is set by the
SET pulse at the start of the operation and then clocked by RRSDO pulses. The flip-flop is conditioned to set by FMK CHR, via an AND gate, so that if the flip-flop is clocked to the reset state it
cannot be set again during the current operation. Thus the first two characters read must be file mark
characters in order to keep the file mark character flip-flop set.
Conditions 1 and 3 are met by means of a file mark gap detector and a read strobe counter. When the
read strobe counter reaches a count of two, the file mark gap detector is enabled and starts counting R
WRT CLK pulses. When the strobe counter reaches a count of three, RSDO > 2 asserts and resets the
gap detector. If the gap detector reaches a count of eight, it outputs 8 BLANK SPACES and CFMK is
asserted to the controller via an enabled AND gate. If a third RSDO pulse occurs before the gap
detector reaches eight, the detector is cleared and the file mark character flip-flop is reset, indicating
that the record is not a file mark and a normal record transfer is in progress.
The end-of-record detection sequence is enabled from the read data channels via a record active OR
gate. If a normal record transfer is in progress (RSDO > 2 is true) or a file mark has been detected
(FMK true), RECORD ACTIVE is asserted and enables (but does not start) the end-of-record detection sequence.

7-23

(F'G. ].81

YES

-..l
N

.t:.
023
PAR==O

CRD7-CADO,
CROP (LRC

GENERATOR

YES

OUTPUT; FOR
MAINTENANCE
USE)

(FIG. 7,20)
11-4790

Figure 7-13

Read Flow Diagram

CRCS

(7)

CVPE

)(FIG 7-21)

LRCS

VERTICAL
PARITY ERROR
DETECTOR

(7)

EPEVN

(FIG 7-6)

(7)

CRCS
CCRCE

CLRCE

(FIG

7-21)

(7)

-----..

(7)

~(FIG

CRC
ERROR
DETECTOR
7-6)

CR7-CRO. CRP

(CLOCK)

(7)

T(RESET)

I (7)

LRC
ERROR
DETECTOR

(7)

LRCS

;--

(FIG

LR7-LRO. LRP

(7)

CRC
GENERATOR
CHECK REG PLS

AEMD (FIG
(CLOCK)

7-9)
CHECK REG PLS

LRC
GENERATOR
(6)

CHECK
REG PLS

(FIG 7-21)

READ
STROBE
O_S_

7-21)

CRDS

IRDO(SB)-RD7(SB).

(4)

CONTROLLER
(FIG
CRD7-CRDO. CROP

READ
DATA
OUTPUT
MUX
(6)

(3)

ERD7-ERDO.
(SWITCH)

READING

ERDP

(NOTE 2)
(FIG 7-9)

"'""'}

7-21)-

LRC7-LRCO. LRCP

RRDO-RRD7. RRDP

READ DATA
LATCH UP
REGISTER
(6)

RRSDO
(CLOCK)

00."'".. ~

RSDO(SB)

CFMK

(FILE MARK
CHARACTER)

~ (4)

[

---..

~(4)r
--...

FILE MARK
CHARACTER
FF
(4)

(FIG

D~FMK CHR

FILE MARK
CHARACTER
DETECTOR

(7)

7-21)

---8MRDO-MRD7. MRDP
(3)

--I

LGl
--

~ (FIG 7-61

(RESET)

(8 BLANK SPACES)

FILE MARK
GAP
DETECTOR
(4)

(ENABLE)
(CLEAR)

(RSDO

(CLOCK)

(CLOC K )

> 2) READ STROBE
COUNTER
(4)

lvl
-- "" '.'<8-

(RESET)

MOL
RSDO

I
FROM
HOST
TRANSPOR T

(RSDO =

(3)

(4)

(ARTI,FICIAL
READISTROBE)
SET
7-6)
F(FIG

ROM
LAVE
US

-MOVE

(FIG

7-91

RWRTCLK

(FIG

7-21)

(4)

(~ORDACTIVE~
(4)

---..

NOTES:
1- Designations in parenthesis refer to engineering drawings

containing corresponding logic.
2_ Note order reversal of read data in latch up register.
11-4823

Figure 7-14

Read Block Diagram
7-25

7.S.4

End-of-Record Detection (Figures 7-20 and 7-21)

7.5.4.1 Nine-Track Normal (Fi.gure 7-15) - The end of a record is detected by looking for the three
blank spaces that occur between the last data character and the CRC character (LRC character for 7track). The blank spaces are detected by an end-of-record counter that is clocked by R WRT CLK
pulses and effectively reset by COMP RD STRB pulses. (Actually the COMP RD STRB pulses load
the counter with a count of 8.) COMP RD STRB pulses are asserted by RRSDO pulses from the drive.
The R WRT CLK pulse and the RRSDO pulse are not necessarily in sync but they are of the same
frequency. Hence the end-of-record counter is continually being clocked and "reset" during the body
of a record. Two R WR T CLK pulses might squeeze in between two RRSDO pulses, thereby clocking
the counter to a count of two before it is reset, but it should never reach a count higher than two during
the body of a record. If the counter does reach a count of three (three R WRT CLK pulses with no
RRSDO pulse) 3 COUNT is asserted, signifying that this is 'the end ofthe record and the end-of-record
sequence is started.

COUNTER RESET

CRC CHARACTER STROBE

LRC CHARACTER STROBE

RRSDO
LOADS 0 INTO
DECISION DELAY
COUNTER

COMP RO
STRB
CRCS _ _ _ _ _ _ _ _--"

LRCS _ _ _ _ _ _ _ _ _ _ _- - '

END OF)- - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..::1
( RECORD
PLS
RD CLR ______________________________________________________~

11-4787

Figure 7-15

End-of-Record Timing, Non-Zero CRC and LRC

The assertion of 3 COUNT clocks the CRCS flip-flop set, outputting CCReS to the controller to
indicate that the next character will be the eRC character. The next RRSDO pulse will be the CRC
character strobe, which will:
1.
2.
3.
4.

Latch up the CRe character in the read data latch-up register
"Reset" the end-of-record counter
Assert CRDS to the controller
Assert CHECK REG PLS, which clocks the LRCS flip-flop to the asserted state

The asserted output of the LRCS flip-flop will reset the CRCS flip-flop and assert CLRCS to the
controller, indicating that the next character will be the LRC character. The next RRSDO will be the
LRC character strobe, which will:
1.

2.
3.
4.

Latch up the LRC character in the read data latch-up register
"Reset" the end-of-record counter
Assert CRDS to the controller
Assert CHECK REG PLS, which resets the LRCS flip-flop

7-27

The negation of LRCS sets the end-of-record flip-flop, asserting END OF RECORD which locks the
CRCS flip-flop in the reset state until the next operation.
When END OF RECORD asserts, a decision delay period begins. The decision delay period is a time
interval (normally eight R WR T CLK pulses long) between the assertion of END OF RECORD and
the assertion of RD CLR PLS. The delay period is a "last chance" look for more RRSDO pulses
before triggering the drive stop sequence. At the start of the decision delay, the end-of-record counter
is "reset" (preset to a count of 8) and starts counting R WRT CLK pulses. When the counter reaches a
count of 8, it overflows into the decision delay counter which then asserts RD CLR PLS to the drive
stop logic. Should RRSDO pulses re-occur any time during the decision delay period, the end-ofrecord counter will be "reset" and the read sequence will continue. When the actual end-of-record does
occur, the decision delay count will start again but the end-of-record sequence will not repeat.
The end-of-record sequence is inhibited if a write operation is in progress (WRITING true). During a
write operation, defective spots in the tape may simulate a gap and erroneously trigger the end of
record sequence. In this case, the end-of-record logic is functioning to stop the drive while the controller is still trying to write data. To prevent this, WRITING is gated with the R WRT CLK pulses
into the end-of-record counter, thereby allowing the counter to operate only if WRITING is false.
7.5.4.2 Zero CRC or LRC Characters - The CRC or the LRC character may be a zero character
resulting in no corresponding RRSDO pulse being received from the drive. In this case, a CaMP RD
STRB pulse is generated artifically so clocking of the end-of-record sequence can continue. If no
RRSDO pulse is received to "reset" the end-of-record counter, counting will continue up to six, at
which time CaMP RD STRB will be asserted via a gate enabled by CRCS or LRCS. Figures 7-16 and
7-17 illustrate the timing sequence for a zero CRC and a zero LRC character, respectively.

RRSDD
COMP
RD STRB
CRCS _ _ _ _ _ _ _-J
LRCS _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

( END OF )
RECDRD ' - - - - - - - - - - - - - - - - - - - - - '

RD CLR
PLS

11-4788

Figure 7-16

End-of-Record Timing, Zero CRC

7-28

f.-------DECISION DELAV---j

RRSDO
RESETS END OF RECORD COUNTER
COMP
RD STRB
CRCS _ _ _ _ _ _ _....;;.J

LRCS _ _ _ _ _ _ _ _ _----'
( END OF)
RECORD'----------------------~
RDCLR
PLS

------------------------------~S
11·4789

Figure 7-17

End-of-Record Timing, Zero LRC

The decision delay is normally eight R WRT CLK pulses long but is extended to 24 pulses ifno LRC
character is detected. Failure to detect an LRC character may be due to the character being zero, but it
could also be due to a bad area in the tape. Thus when no LRC character is detected, some doubt exists
on whether the end of the record has been reached. Extending the decision distance to 24 pulses
provides extra assurance that the end of the record has been reached. The decision delay counter is a
count-down counter that is loaded by each RRSDO pulse. The counter is loaded with zeros except for
the 1 bit, which is loaded with LRCS. If there is an LRC character, then LRCS is true during the last
RRSDO pulse (Figure 7-15) and the counter is loaded with all zeros. If there is no LRC character, then
LRCS is false during the last RRSDO pulse (Figure 7-17) and the delay counter is loaded with a 1. In
this case, the end-of-record counter must count an additional 16 pulses to count down the 1 and assert
RD CLR PLS.
7.5.4.3 Seven-Track and File Mark (Figures 7-18 and 7-19) - In 7-track or file mark operation, the
end-of-record sequence is modified to eliminate the CRC character from the sequence. With either
FMK or 7TRK true, the 3 COUNT output from the end-of-record counter directly sets the LRCS flipflop, which in turn holds the CRCS flip-flop reset. Also, when in file mark operation, the decision
delay is extended to 24 R WR T CLK pulses as there is no RRSDO pulse associated with the assertion
of LRCS.

7-29

...-----DECISIDN DELAY-----<~

LAST DATA
CHARACTER

LRC CHARACTER
INTO DECISION
DELAY COUNTER

RRSDD

COMP

S
LRCS

(END OF
RECORD)

RDCLR
PLS

S
11-4785

Figure 7-18 End-of-Record Timing, Seven-Track

R WRT CLK

RRSDO

A C T I V E - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -__~
LRCS _____________________________________________________________

END OF
RECORD------------------------------------------------------------------------~

RDCLRPLS ________________________________________________________________________________

11-4786

Figure 7-19

File Mark Timing

7-30

(FIGURES 7-11 and 7-13)
B

LRCS

YES

(FIG 7-22)

C
11-4791

Figure 7-20

End-of-Record Flow Diagram
7-31

"....iiillilllllf-

(FIG7_9)~.~R=D~C~L~R~P=LS=-______________________________________________~

(ARTIFICIAL
(FIG 7-14) •

READSTROBE)~
(4)

'--________....,

(4)

TO
CONTROLLER

.f=«1

~r---~--~------~----------------------_.

~r-

LRCS

DECISION
DELAY
COUNTER
(4)

END OF RECORD

(LOAD)

RRSDO

(FIG 7-14)

(ENABLE)
(CLOCK)

-.J
I

l;.)
l;.)

(RESET)

..I

-----,

END OF
RECORD
FF
(4)

(8 COUNT)

(6 COUNT)

(3 COUNT)

END OF
RECORD
COUNTER
(4)

I~ENABLE) I RECORD ACTIVE (FIG 7-14)
WRITING)
R WRT CLK

(FIG 7-12)

LRCS
READING

LRCS
(RESET)

o
LRCS
FF

MOVE (FIG 7-9)

COMP RD STRB (FIG 7-14)

(SET)

-----....
D

T'"--r
I

(FIG 7-9)

(FIG 7-6)

(4)

f(RESET)

(FIG 7-14)

CRCS

CHECK REG PLS

(FIG 7-14)

CRCS
FF
(4)

(RESET)j

NOTE:

Designations in parenthesis refer to
engineering drawings containing
corresponding logic.

114773

Figure 7-21

End-of-Record Block Diagram

7.6 DRIVE STOP (Figures 7-7, 7-9, and 7-22)
RD CLR PLS triggers the drive stop sequence by setting the EMD flip-flop and asserting EMD (SB)
to the drive. The output of the EMD flip-flop also loads the motion delay counter with data set onto
read lines RRDO-RRD6, RRDP by the drive. Bit 13 of the counter is preset to a 1. The bit 14 output,
which has been a 1 during the record transfer, is connected to the data input of bits 14 and 15. Thus
when EMD loads the counter, output bits 13, 14, and 15 become 1s. READING negates due to
exclusive a Ring of output bits 14 and 15, while bit 13 gates clock pulses into the counter from the
divide-by-four counter. The divide-by-four counter receives CLOCK (SB) pulses from the slave bus.
An output from the divide-by-four counter is obtained after the first two CLOCK (SB) pulses and
every four CLOCK (SB) pulses thereafter. After the delay period, the motion delay counter is clocked
reset and:
1.

Input clock pulses to the delay counter are inhibited (bit 13 = 0).

ACCL (SB) is asserted to the drive (bit 14 = 0) and inhibits WRT CLK (SB) pulses from the
drive to the write logic.

The assertion of ACCL resets the MOVE flip-flop, which negates MOVE and asserts STOP (SB) to the
drive, thereby terminating the command operation.

7-34

(FIG 7-20)

INCREMENT
MOTION DELAY
COUNTER

INHIBITS
MOTION DELAY
COUNTER

DONE

11-4782

Figure 7-22

Drive Stop Flow Diagram
7-35

CHAPTER 8
TUIOW HOST TRANSPORT THEORY OF OPERATION

8.1 INTRODUCTION
The TUlOW is the tape transport used in this magnetic tape storage system. A slave bus connects the
host TUlOW to the M8926 Interface board logic, and also to any slave TUI0W Transports used in the
system. Refer to Figure 8-1, the TUlOW system block diagram.

MAST-;;;U;;M8926
INTERFACE
LOGIC

TO
TAPE
CONTROLLER

HOST
TU10W

- - .J

SLAVE
TU10W

11-4669

Figure 8-1

TU lOW System Block Diagram

The slave bus consists of slave (TUlOW) select lines, write data lines, read data lines, transport control
lines, and additional transport status lines. Figure 8-2 and Table 8-1 show and list the slave bus
interface signals, respectively.

8-1

·".,t>
",.£>

WD (SS) L

SS 0-2 (SB) L

REC (SB) L
ACCL (SS) L
LRC STRS (SS) L
STOP (SS) L

EMD (SS) L
SLAVE SET PLS (SS) L

M8926
INTERFACE
LOGIC

FWD REV,
RWND, WRITE (SS) L

"'N~

DEN (0-1) (SS) H

H'·V

~D(SS)L

TU10W
TAPE
TRANSPORT

9 LINES

'II
CLOCK (SS) L
WRT CLK (SS) L
BOT (SB) L
END PT (SB) L
WRL (SB) L
RWS (SS) L
RSDO (SS) L

TUR (SS) L
SDWN (SS) L
7 CH (SB) L

MOL (SB) L

SLAVE BUS
11-4670

Figure 8-2

Slave Bus Interfac~ Signals

8-2

Table 8-1

Slave Bus Interface Signals

Slave Bus Signal

Function

Slave Select [SS(0:2) (SB)]

These lines select one of eight possible TU lOW Transports for
command execution.

Forward [FWD (SB)]
Reverse [REV (SB)]
Rewind [RWND (SB)]
Write Enable [WRITE (8B)]

These are the four command lines which determine TUIOW
operation.

Slave Set Pulse
[SLAVE SET PLS (SB)]

This signal initiates TV lOW response to the four command
lines.

Stop [STOP (SB)]

This signal causes the TUIOW to terminate motion. (Does not
apply to rewind, which terminates independently.)

Enable Motion Delay
[EMD (SB)]

This signal enables the TVIOW to gate out a coded motion
delay preset onto the read lines.

Accelerate [ACCL (SB)]

Asserted by the controller while the transport is getting up to
speed or not moving tape.

Write Data [WD (0:7, P) (SB)]

These nine lines transmit data to be written by the TUlOW.

Record [REC (SB)]

A pulse that causes data to be written on tape.

Density Select [DEN (0:1) (8B)]

These two lines control the density at which data is written on
tape. They must also represent the density of tape data during a
read operation.

Clock [CLOCK (8B)]

A 144-kHz clock, generated in the TV lOW, present at all times
when the unit is on-line.

Write Clock [WRT CLK (SB)]

This clock is transmitted to the controller by a powered, on-line
TUlOW loaded with tape when it is running at speed (ACCL
not asserted). The frequency of WR T CLK is a function of the
DEN lines, and controls the write timing frequency.

LRC 8trobe [LRC STRB (SB)]

Asserted by the interface logic prior to the REC pulse that
writes the LRC character.

Read Data [RD (0:7, P) (SB)]

These nine lines transmit read data from the TV 1OW to the
controller. (They also transmit the motion delay preset.)

Read Strobe Delay Over
[RSDO (8B)]

A read strobe pulse generated by the transport at the end of the
skew delay in NRZ mode.

Beginning of Tape [BOT (8B)]

Asserted when the TVlOW detects the beginning-of-tape
marker.

8-3

Table 8-1

Slave Bus Interface Signals (Coot)

Slave Bus Signal

Function

End of Tape [EaT (SB)]

Asserted when the TVlOW detects the end-of-tape marker.

Rewind Status [R WS (SB)]

Asserted while the selected TV lOW is performing a rewind
operation.

7-Channel [7CH (SB)]

Asserted when the selected drive is a 7-track transport.

Medium On-Line [MOL (SB)]

Asserted by a selected, powered TV lOW which is loaded with
tape.

Tape V nit Ready [TVR (SB)]

Asserted by a selected TV lOW to indicate that tape motion has
stopped.

Settle Down [SDWN (SB)]

Asserted while the transport is decelerating, until it has stopped.

Write Lock [WRL (SB)]

Asserted when the selected TVIOW detects that the write enable
ring has been removed from the tape reel.

8.2 TRANSPORT OPERATION
Figure 8-3 is a block diagram of the TVlOW, showing the major functional groups, control lines, and
data paths. The following paragraphs describe these functional groups.
8.2.1 Logic and Write (LAW) Module (M891O)
The LAW module (M89lO) interfaces the controller motion control signals and write data path to the
TVIOW.
Write Data Path - Input to the LAW circuitry of each track is the data line corresponding to that
track, plus a delayed REC pulse. (The delay is prewired and corrects for static write skew errors in the
write head itself.) NRZ write data is still in binary mode and is converted to NRZ mode (transition for
Is, no transition for Os) in the LAW module. The write data signals are then applied to the write heads.
ilTape Motion - The signals that control the power board (H606), which, in turn, controls capstan and
!tape reel motion, are generated on the LAW module. The LAW module contains Motion Control flipflops and additional sequencing circuits. The sequencing circuits provide smooth mechanical operation, which protects data and hardware. The flip-flops enable reel motion and vacuum operation,
determine the direction and speed of capstan rotation, and light control panel indicators. These flipflops are controlled by the controller via the slave bus when the TV lOW is on-line, and by the TU lOW
control panel when the transport is off-line. When the TV lOW is on-line and receives a motion/write
command from the controller, the flip-flop corresponding to that command will be set upon receipt of
SLAVE SET PLS (SB), at which time the motion will commence/the write amplifiers will be enabled.
Receipt of STOP L from the controller causes the Motion flip-flops to be reset and the motion
terminated.

8-4

TU10W MAGNETIC TAPE TRANSPORT
SLAVE SELECT

LOGIC S WRITE (M8910)
(LAW)

CONTROL
PANEL
SWITCHES

OFF-LINE
CONTROL

COMMANDSI
FWD. REV, RWND S WRITE

INDICATOR

1--

SLAVE SET PULSE
STOP

INDICATORS

SIGNALS

@) )

~TAPE DRIVE SYSTEM-------------~
CAPSTAN
FOR
POWER BOARD (H606)
f.o----- =E) ~ SERVO
'...

REV/REW~

",W"""

L_
-_ _---

WRITE DATA LINES
SLAVE
BUS

.......

(WRITE DATA PATH)

VACUUM
SYSTEM

VACUUM MOTOR ENABLE
ERASE

DOC)

I
___ .-l

''''''''''''' "'" ~
'"
6

DRIVE
VACUUM SWITCH SIGNALS

RECORD

UPPER REELS BRAKE DRIVE

MEDIUM ON
LINE

SLAVE CLOCKSMOTION
DELAY (M8911)

'"''
~

WRITE
HEAD

)

READ AMPS
(G056)
(READ DATA PATH)
READ DATA LINES
ENABLE MOTION DELAY

------

I--- ---- j..-

ACC L
WRT CLK
RSDO{READ STROBE DELAY OVER)

TU10W POWER
SUPPLY

11-4678

Figure 8-3 TV lOW Tape Transport Block Diagram

8.2.2 Slave Clock and Motion Delay Module (M8911)
The slave clock and motion delay module (M8911) generates clock signals (CLOCK and WRT CLK).
Signal CLOCK is a 144-kHz clock transmitted over the slave bus by a selected, on-line, and powered
TV lOW loaded with tape. The CLOCK signal is used in the interface module to generate other clock
signals, which perform various housekeeping functions. The frequency of WRT CLK depends on the
density. It is transmitted to the interface module by a selected, on-line TV lOW loaded with tape when
it is running at operating speed. Signal WRT CLK plays a crucial role in the interface module during
read and write operations. The slave clock and motion delay module also generates presets for the
motion delay counter in the interface logic. The presets are multiplexed onto the slave bus read data
lines whenever the TV lOW receives EMD (enable motion delay) from the interface logic.
8.2.3 Read Head and Read Amplifiers
The read head converts changes in magnetic flux on the tape into voltage signals, which are then
amplified by the read amplifiers (G056).
When reading in NRZ mode, the read amplifier of each track produces a high output level for each
change of magnetic flux on its tape track (Figure 8-4). These levels are strobed into the interface read
logic. Zero bits are recognized by no change in flux on a track (i.e., no high level) when at least one
other track has flux change. Because of parity conventions, each character on the tape will have at least
one flux change on one of the tape tracks.

DATA

...

BIT CELL •.------..------t.t--------j.~-----..------4I.f----

READ AMP OUT ----------~

'------'n'--___IL
\\- 4695

Figure 8-4

Read Amplifier Output

8.2.4 TVIOW Power Board
The TVIOW power board (H606) contains circuits that control and drive the capstan and tape reels.
The capstan motor is part of a servo loop, of which the inputs are motion signals (FOR, REV jREW,
and REWIND CAP) from the LA W module. These motion signals control the direction and speed of
the capstan motor, which controls the direction and speed of the tape relative to the heads. The tape
reel drives, do not control tape direction or speed. The tape reel drives function is to maintain the
proper amount of tape in the vacuum columns.

8-6

A TUlOW Tape Transport has two tape reel drive systems, each one operating independently of the
other, The upper tape reel drive operates with the upper vacuum column vacuum switches as inputs.
When the tape is too high in the column, the switches activate the tape reel motor to supply tape to the
column. When the tape is too low in the column, the tape reel motor is activated to take up tape. The
lower tape reel drive operates with the lower vacuum column switches in an identical manner.
8.3 WRITE DATA PATH
The write data path, shown in the TUlOW block diagram (Figure 8-3), is discussed in greater detail in
this section (Figure 8-5).
The slave bus write data line signals are received by slave bus receivers on the logic and write (LAW)
module (M8910), and then input to the LAW write data multiplex, through which they pass to the
LAW write deskew buffer.
Timing for the interface logic is derived from WRT CLK, which is generated in the TUlOW. Signal
WR T CLK is also gated in the interface logic to produce REC pulses, which are transmitted back to
the TUIOW. These REC pulses are input to a delay, which is tapped (hardwired at manufacture), and
connected to the clock inputs of the write deskew buffer. This arrangement provides write deskew; it
compensates for errors inherent in the manufacture oftape heads that prevent the heads for all the tape
tracks from ideally lining up.
The write deskew buffer circuitry also converts the binary NRZ data to its NRZ form, i.e., transition
for Is, no transition for Os. The write deskew buffer output is then driven to the write heads.
8.4 READ DATA PATH
The read data path, shown in the TUIOW block diagram (Figure 8-3), is discussed in greater detail in
this section (Figure 8-6).
As tape moves past the read heads, flux transitions on the tape cause the read heads to produce
positive and negative current pulse outputs. These current pulses are processed in the read amplifiers
(G056) to yield voltage levels. The voltage levels are then transmitted by line drivers in the TUIOW
through the slave bus and the interface board to the controller.
8.S TEST FUNCTION GENERA TOR
The test function generator (TFG) module (M8912) is used for off-line testing of the TUlOW Tape
Transport. During normal, on-line operation of the TUlOW, the module must be located in section EF
of slot 3 of the TU lOW backplane. For use as an off-line tester, the TFG module must be moved to
section A B of slot 3.

8.5.1 Functional Modes
An operating procedure for the TFG is presented in flowchart form in Figure 8-7. Figure 8-8 provides
additional information on TFG switch settings. The TFG module is illustrated in Figure 8-9.

8-7

TU lOW TAPE TRANSPORT

LOGIC ANDWRITE (M8910)

....,

WD 0
~

WD I

PIO SLAVE BUS ~

INTERFACE
LOGIC

I
f-

0
I-

WRITE DATA LINES
9 BITS

-I

WRITE
DESKEW
BUFFER

w
z
z

-V:

(/)

9 BITS

f--0-

SLAVE
BUS
RECEIVERS

WD 2

WRITE
DATA
MUX

I---0-

WD3

'-~

--l

RECORD PULSE

(/)

WD4

f~=;l

WRT CLK

TEST

DATA

I I

WD5

(M~2)

HEAD

WD6

TEST

~UNCTION:J
GENERATOR

--"-

I
'-"[3>
I
V

)

f--

f...r..

WD 7

I
!

SLAVE
I CLOCK AND
I
MOTION
I
DELAY
I
I1_ _(M8911)
_____

WD P

I
I
I

(

SKEW CLOCK . /

TAPPED

(
DELAY

11-4676

Figure 8-5

Write Data Path

TU10W TAPE TRANSPORT

r<G;-5~ -

I..

~
READ
HEAD

00
I

READ
AMPS

--= ___ I I

_
SLAVE CLOCK AND
MOTION DELAY (M8911l

MOTION
IDELAY - . , I
PRESETS----V

~-------- - - -

- --

v
-A

READ
DATA
"\ MULTIPLEX

---

I"
L

BBITS

I
I

_... _-

SLAVE
BUS
DRIVERS

'\
/

L ---- J

0::

L - -- J

I (IN TU10W SLAVE ONLY)

I
I
- "\
. / 1 -'"
A

RD(O-6,P) BBITS

roA~A~~(~) -

~ 1 - - - - - - 1 ' . . TO

RD(O-7,P)9BITS

"\ z
/

RD(O-7, P)9BITS

INTERFACE
LOGIC

ffi
~

-------

11-4677

Figure 8-6

Read Data Path

REMOVE POWER

I
REMOVE TFG
FROM SLOT EF3
EXTEND MODULE
IN SLOT AB3

PLACE WRT,
SS WRT, AND SS
RD SWITCHES
IN DOWN
POSITION

I
RESTORE POWER
AND LOAD TAPE

I
CONFIGURE S5-9
& S5-10 FOR
DENSITY

WRITE

READ

CONFIGURE DATA
PATTERN IN S5 &

S6
START
-STOP
READ

START-STOP WRITE
CO NTINUOUS
WR ITE

PLACE SS RD
SWITCH UP MOMENTARILY
THEN DOWN
(LOADS DATA
PATTERN)

PLACE WRT
SWITCH UP

LOAD FRAME
COUNT INTO
S41-8

CONTINUOUS
READ

INITIATE
FWD OR REV
TAPE MOTION
AT FRONT
PANEL

SET FRONT
PANEL FWDI
REW/REV
SWITCH
TO FWD

SELECT FWD OR
REV TAPE MOTION AT FRONT
PANEL

I
INITIATE FWD
TAPE MOTION
FROM FRONT
PANEL

PLACE SS RD
SWITCH UP

PLACE SS WRT
SWITCH UP

I
SET S4-9 TO ON IF
LONG DELAY BETWEEN STARTSTOP OPERATIONS
IS DESIRED.
ADJUST R23 AS
DESIRED
11-4675

Figure 8-7 TFG Operating Procedure Sequence

8-10

ON" LONG DELAY
START ISTOP OPERATIONS

NOT
USED

DETERMINE DATA
DENSITY AND MODE

,"- ,

____ ..1

----·'v/

ON"O

MODE
556

S5-9

S5 -10

/
238 bpi NRZ

800 bpi NRZ

OFF

DETERMINE TFG
TEST DATA OUTPUT
(SEE NOTE)
NOT USED

DETERMINE RECORD
LENGTH (2's COMPLEMENT)
FOR SS RD or SS WRT
OPERAT ION (BIT 1 " LS8)

S6
11-4674

Figure 8-8

TFG Switch Settings

WRT
55WRT--_

LED

* Adjusts start-stop time.
6999-5

Figure 8-9

Test Function Generator Module

8-11

As an off-line tester, the TFG module (Figure 8-9) controls tape motion, enables TVIOW read and
write circuitry, and generates test patterns to be written on tape. Three modes of operation are
possible:
I.

Start-Stop Read (SSRD) - When the SSRD switch (S3) is activated (raised), tape motion is
initiated; a record of predetermined length ,is read; tape motion is then terminated. This
cycle is repeated as long as the SSRD switch is up.

Start-Stop Write (SSWRT) - When the SSWR T switch (S2) is activated (raised), tape
motion is initiated; a record of predetermined length, consisting of preselected characters, is
written on tape; tape motion is then terminated. This cycle is repeated as long as the SSWRT
switch is up.

Continuous Write (WRT) - When the WRT switch (Sl) is activated (raised), power is supplied to the write drivers and they are continuously driven with a preselected pattern. Tape
motion is controlled from the TV lOW front panel.

When the tester card is located in the TV lOW, location AB, the pin labeled TESTER ENABLE L is at
ground potential (drawing M8912, sheet 3). This enables the TEST PE H and TEST DEN H switches.
With the LED on, the TEST PE H and TEST DEN H switches affect the recording density as controlled by the M8911 slave clock module. The TESTER ENABLE L level asserts LOCAL H, preventing the transport from going on-line.
An 8-bit counter, constructed from two 74197 up-counters, controls a preset record length. The preset
count is entered from the S4 switches [S4 (1-8)]. Both the SSRD and SSWRT functions use the counter
to control record length. The WR T function is continuous and does not use a preset panel.
A 16-bit shift register, constructed from two 74199 8-bit shift registers, allows various data test patterns to be generated. Switches on S5 and S6 select the data pattern to be loaded into the register.
When shifted out, the test data patterns (TEST DATA A Hand L and TEST DATA B Hand L) are
wired to the data multiplex on the LAW module (M891O) and written on tape.
The start-stop repetition rate during SSRD and SSWRT can be modified by adjusting R23. The range
of adjustment is determined by switch S4, segment 9.
8.5.2 Theory of Operation
The following paragraphs describe the theory of operation of the TFG module in its three functional
modes. The discussions reference the TFG schematic (TFG3).
SSRD Function - Figure 8-10 illustrates SSRD timing. When the SSRD switch (S3) is closed, El-pin 10
goes low and triggers the first one-shot delay. FIRST ONE SHOT L, input to the LAW module
(M891O), initiates tape motion; the direction of tape motion is determined by the direction switch on
the TV lOW control box. FIRST ONE SHOT also presets the 8~bit counter (E15 and E22) and loads
the 16-bit shift register (E13 and E23).

8-12

I
SS RD SWITCH HLII

'------/

H
1 ST

tOms
rl
}__;..;._---JI

ONE SHOT L
L

WRT CLK TEST ENS L
(RECORD PULSE)"

H_r-----,
READ

~OVERFLOW

H ----Jf------/
TSTR

FRAME CNT 2H

H
3RD ONE SHOT H

L -r------r

4 TH ONE SHOT H

INIT L

;:===:==:L...--.-J.-----I);:1----1: ~
CLOSE SS
RD SWITCH

COUNTER OVERFLOWS
AT END OF PRESET
COUNT

OPEN SS RD
SWITCH

"RECORD PULSE L PULSES
OCCUR DURING WRT CLK
TEST ENS L.
10-1298

Figure 8-10

SSRD Function

When FIRST ONE SHOT times out, flip-flop E8 is clocked set and asserts WRT CLK TEST ENB L.
This signal is used in the slave clock and motion delay module (M891l) to enable WRT CLK and
RECORD PULSE L pulses. The RECORD PULSE L pulses now clock the TFG 8-bit counter and
16-bit shift register. When the counter overflows, the third one-shot delay is triggered and negates
WRT CLK TEST ENB L, inhibiting further RECORD PULSE L pulses.
When THIRD ONE SHOT times out, FOURTH ONE SHOT H is generated, and causes tape motion
to terminate. When FOURTH ONE SHOT times out, the first one-shot is again triggered; the cycle
begins again. The start-read-stop cycle continues as long as the SSRD switch is depressed.
SSWRT Function - Figure 8-11 illustrates SSWRT timing. The start-stop write function operates in a
manner similar to the SSRD function, except that SET TEST WRE L is asserted along with WR T
CLK TEST ENE L. SET TEST WRE L causes the write and erase heads to be energized. When
RECORD PULSE L pulses clock the shift register (E13 and E23), the contents of the register are
rotated. The shift register outputs (TEST DATA A Hand L and TEST DATA B Hand L) can be
jumpered to the LAW data write multiplex and written on tape.

8-13

H
SS WRT SWITCH

\------1 /----------1/1-1

-------.-11---~

H
FIRST ONE SHOT L

-11..---,

r----+t~.---/I----

WRT CLK TEST ENB L

L
H
SET TEST WRE L
(WRITE CURRENT) L

L.----II------+--+----TI-------+-+--.-1---r-l
-1----.-1

---r/- -

-1---.-1

L.--I--.-1---~/- - -

TSTR FRAME CNT 2 H

H
3RD ONE SHOT H

H
4 TH ONE SHOT H

L - I - - - - - O...t - -.........

L...--...-....J~---I r

H -1..---.-11-+----,
INIT L

L
CLOSE SS
WRT SWITCH

COUNTER OVERFLOWS
AT END OF PRESET COUNT

SS WRT OPERATION
REPEATING

OPEN SS WRT
SWITCH
10-1297

Figure 8. . 11

SSWRT Function

Continuous Write Function - The continuous write function works differently than the SSWRT function in that in the continuous test mode, no starting and stopping occurs. One continuous write operation commences with the setting of the WR T switch and ends with the opening of the switch. Tape
motion (starting and stopping) is controlled at the TUlOW control panel.
As the WRT switch is closed, WRT CLK TEST ENB L and SET TEST WRE L are asserted. This
enables RECORD PULSE L pulses and passes write current to the heads. The 8-bit counters are not
used in the continuous write operation. Instead, the shift registers are clocked by inverted RECORD
PULSE L pulses and whatever data pattern was in the shift register switches is shifted out on the TEST
DA T A lines to be written and observed. The THIRD ONE SHOT delay is inhibited, which eliminates
the start-stop operations.
If the operator desires a test data pattern other than the pattern presently in the shift register switches,
he must first run an SSRD operation with the desired test data pattern. It is the only method for
loading new information from the switches into the shift register.
The continuous write operation continues until the WRT switch is opened; this clears the WRT flipflop and removes the write current and record pulses.

8-14

8.6 CLOCKS
System and write clocks are discussed in the following paragraphs.
8.6.1 System Clocks
All free-running system clock waveforms used in the TUIOW jcontroller are generated from a 2.3MHz, crystal-controlled clock located on the TU10W slave clock and motion delay module (M8911).
The 2.3- MHz clock is divided down to 144 kHz, and is transmitted to the interface logic over the slave
bus [CLOCK (SB)] by an on-line, selected transport loaded with tape.
8.6.2 Write Clock
A TUIOW jcontroller is capable of reading and writing data at several bit densities. To do this, a
separate clock signal, the frequency of which depends on the tape density data, must be developed;
WR T CLK is this signa1. WR T eLK is transmitted to the M8926 Interface module.

The WRT CLK signal is developed in the following manner. A number is preset into a 74161 (synchronously loaded) binary counter (SC 3), which is then upcounted at 575 kHz. When the counter overflows, WR T C LK H is asserted and causes the counter to be preset at the leading edge of the next 575kHz clock pulse. With the counter preset, WRT CLK is negated by the trailing edge of that same 575kHz clock pulse. The counter is clocked up as before, until overflow, and the cycle is repeated.
The presets of the 74161 counter are determined by various signals and conditions. These are listed in
Table 8-2, along with the resulting counter presets, WRT CLK frequency, and density.

On-Line

Off-Line

Table 8-2

Write Clock Frequencies

DEN

Test

DEN

r 0

1
1
1
1
1

1
1
1
1
1
1
1
1
0
1
0

0
1
1
-<
0
0
1
.... 1

0
1
0
1
0
1
x

x
x
x

1
1
0
0
1
1

WRTCLK
Counter Presets
LSB
MSB

Frequency
kHz (bpi)

10000011
01010111
10001111
10001111
10111111
00111111
10111111
10111111
01010011
10001111
00111111
10111111

9(200)
28(556)
36(800)
36(800)

NjA
NjA
NjA
NjA
10.7(238)
36(800)

NjA
NjA

Obviously, the frequency of the cycle will vary with the magnitude of the preset. Figure 8-12 shows
timing diagrams for presets of -1 (-n = 2'8 complement of n), -2, and -3. Note that for a preset of -n,
the frequency of WRT CLK, fWRT eLK = [575j(n+1) kHz.

8-15

575 KHz CLOCK

COUNT OUTPUT
(PRESET =-I)

LOAD

OFLO

LOAD

(J-<- - - - '

WRTCLK H L J

LOAD
COUNT OUTPUT

(PRESET = -3)

LOAD
----J

(

-I

OFLO

LOAD

1--1---II

(

LOAD

OFLO

LOAD

-I

OFLO

~--~I

(

OFLO

LOAD

----II

!-I

(

U''-------'U''-------'L

I~----~I

LOAD
-2
-I
OFLO
r :..--------------"

OFLO

/--1

(
U

H~~______~I

COUN T OUTPUT

WRT CLK

OFLO

LOAD

! - I- - - - I

--.J

(PRESET = -2)

WRTCLK

-I

OFLO

LOAD

-I

~----

____~rl------~______~I------~_______

LOAD

-2

(1------1

H~~__________~I~------~

-I

OFLO

LOAD

I
(!---l

-2

-I

1
(

OFLO

__________~~I------~__________---'r
10-1254

Figure 8-12

WRT CLK Generation Timing

8.7 TAPE MOTION
TU lOW tape motion can be controlled by the controller via the slave bus, or by the TUl OW control
panel switches (Figure 8-13), depending on whether the transport is on-line or off-line. The motion
control logic in the LAW module (M891O) provides proper sequencing and control during TU 10W
operations. It enables the vacuum motor and provides the signals that control the capstan drive
circuitry.
The H606 power board contains the capstan drive circuitry and the tape reel braking and motor
control circuits. The direction and velocity of capstan rotation are determined by three signals (FOR
H, REV /REW H, and REWIND CAP H) from the motion control logic. These signals, therefore,
determine the direction and speed of tape motion. The tape reel braking and motor control circuits
activated by the vacuum switches in the vacuum columns operate to maintain a reservoir oftape within
the columns. The vacuum system operates to supply tape to the capstan at constant tension.

8.7.1 TUIOW Power Board (H606)
The TUlOW power board (H606) is divided into two main areas: capstan servo control and driver
circuits and the tape reel braking and motor control circuits; the discussions reference the H606-0-1
schematics.

8-16

Ir - - - - - - - - - - - - - - - - ,I
TU lOW TAPE TRANSPORT

I
I ------LAW
{M8910l

FROM

ON-liNE

CONTROLLER ""'=""=-::-:-~/
CONTROL

I
I
I
I
I
I
I

TU10W
CONTROL

~Na

OFF -Li NE

SWITCHES

TAPE
MOTION
TU10W POWER BOARD
{H606l
CAPSTAN
SERVO
CONTROL
AND DRIVE
VACUUM

REEL BRAKE
AND MOTOR
CONTROL

SWITCHES

~
<J /\

QOD

REEL MOTORS
AND BRAKES

L ________________

11-4685

Figure 8-13

Tape Motion Control Block Diagram

8.7.1.1 Capstan Servo Control and Driver - The heart of the transport mechanism is the capstan
subsystem, which transports the tape across the read/write/erase head assembly at the desired speed.
The capstan is controlled by a velocity-feedback servo loop, shown in Figure 8-14. Refer also to sheet 3
of the H606-0-1 schematics. As a forward command enters the logic (FOR H), Q1 is biased correctly to
turn on. With Q 1 turned on, the voltage present at the base of Q7 is higher than the -8 V at the emitter,
resulting in Q7 being turned on. If either reverse or rewind is selected, signal REV /REW H becomes
true and turns Q2 on, while forward selects Q7. Notice that the collectors of both Q2 and Q7 are tied
together. That output line is the running speed line going to the "-" input of the operational amplifier.
Diodes 07 and 010 detect the more positive and more negative levels from Q2 and Q7, respectively,
when selected. Therefore, when Q2 is on (Q7 off), 07 conducts and when Q7 is on (Q2 off), 010
conducts. Resistors R12 and R13 are the reverse and forward speed adjustments. They are each
adjusted to move tape at 11.4 m (45 inches) per second).
Transistors Q8, Q9, and Q10 constitute a -8 V series regulator that biases the forward (Q7) logic.
Transistors Q4, Q5, and Q6 make up a +8 V series regulator, which supplies regulated +8 V to the
reverse (Q2) logic. Circuit schematic ORVR 3 (H606, sheet 3) lists test points available for checking
these supplies.
The tachometer feedback signal (TACH V) is filtered and applied to the "+" input of the operational
amplifier (comparator). The tachometer produces an output voltage (TACH V) proportional to the
velocity of the capstan. The capstan servo amplifier (72741 at Ell) compares the tachometer output
with a reference voltage that is proportional to the desired capstan velocity and generates an appropriate error voltage. The error voltage (SERVO SIGNAL) is further amplified by the capstan motor
driver, which drives the capstan motor. Thus, if the capstan is running slower than the desired speed,
the SERVO SIGNAL and, consequently, the voltage impressed on the capstan motor increase, speeding up the capstan. If the capstan is running too fast, the capstan velocity is similarly decreased.
8-17

CAPSTAN
MOTOR

TACHOMETER

CAPSTAN

TACHOMETER FEED BACK

FOR H

r---------------------,
II

FORWARD REFERENCE

VOLTAGE GENERATOR

REVERSE (1) H

REWIND CAP H

REVERSE REFERENCE

REWIND H _~~

VOLTAGE GENERATOR

RAMPED REWIND

REFERENCE GENERATOR

I
I

CAPSTAN SERVO AMPLIFIER

L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A~RIVE~ _ _ J
10-1299

Figure 8-14

Servo Feedback Loop

When the capstan is at rest and a forward command is issued, the difference between TACH V (0 V)
and the forward (Q7) circuitry is quite large. This causes the error voltage comparator to produce
SERVO SIGNAL, which goes on to the driver circuitry to allow the capstan velocity to approach 1.14
m (45 inches) per second forward velocity.
Resistor R21 is the balance adjustment resistor found in the comparator feedback loop. It is adjusted
for zero capstan creep with no input.
Due to the danger of "spooking" (slippage between adjacent layers of tape on the reels), which can
damage tape by stretching or buckling it, the tape reels cannot be accelerated as quickly as the capstan
for high-speed (rewind) operation. For normal [1.14 m (45 inches) per second forward and reverse]
operation, the vacuum columns buffer enough tape to allow time for the reels to catch up with the
rapid accelerations and decelerations of the capstan. However, the buffer columns cannot contain
enough tape to allow the capstan to accelerate and decelerate at its normal high rates to and from the
3.81 m (150 inches) per second rewind velocity. For this reason, the rewind command logic uses two
signals (REV jREW H and REWIND CAP H) to control the rewind velocity of the capstan.
When a rewind command is issued, signal REV jREW H is asserted, causing the capstan to accelerate
immediately to 1.14 m (45 inches) per second just as in a normal reverse operation. Then REWIND
CAP H is asserted; transistor Q3 is turned on, placing an increasing current on the running speed line.
This causes a ramped rewind reference voltage generator (RlOjC13 time constant) to gradually increase the rewind speed, exponentially approaching 3.81 m (150 inches) per second at a rate at which
the reels can be accelerated. Resistor Rll is used to fine-adjust the rewind speed.

8-18

Refer now to sheet 4 of schematic H606-0-1. This is the circuitry that drives the capstan motor. When
SERVO SIGNAL enters, it splits and goes to both the right and left sides of the drawing. Transistors
Q31 and Q32 sense the SERVO SIGNAL polarity for the forward (+) and reverse (-) directions,
respectively. The circuitry involving transistors Q33, Q34, and Q35 provides current amplification for
the forward direction, providing MOTOR with the current necessary to drive the motor. Transistors
Q36, Q37, and Q38 operate in a similar manner for the reverse direction.
The SERVO SIGNAL line also goes to the left of the drawing; diode D38 shunts a positive SERVO
SIGNAL for forward and diode D39 shunts negative levels for reverse. These two diodes are connected to the collectors of the two differential amplifiers (Q24 and Q26). The current (MOTOR)
through the motor and, consequently, its acceleration rate, would be functions of such loosely controlled parameters as power supply voltage, motor armature resistance (a function of temperature),
and the back emf of the motor if some precautions were not taken. By current-limiting the output of
the power current amplifier, the acceleration and deceleration rates of the capstan in normal (i.e.,
forward and reverse) operation become accurately controlled. The SERVO SIGNAL line is full of the
large variations mentioned previously. Resistor R85 (0.1 ohm, 1%) in the MOTOR RETURN line
senses current through the motor and supplies a feedback signal (through R94) to the bases of the Q24
and Q26 differential amplifiers. The selected amplifier (Q24 forward; Q26 reverse) limits the current to
the capstan motor and keeps the current between MOTOR and MOTOR RETURN constant.
Transistor Q24 is used in the forward line; Q26 operates in the reverse. Resistor R89 is the + current
adjustment used to fine-tune the forward running current, eliminating large changes in the MOTOR
RETURN line. Resistor R90 adjusts negative current for reverse direction, following a similar
philosophy.
8.7.1.2 Tape Reel Braking and Motor Control Circuits - Sheets 5 and 6 of schematic H606-0-1 illustrate the braking and motor control circuits. As explained in the previous paragraphs, it is necessary to
buffer a small amount of tape past the read/write/erase head assembly without "spooking" the tape
on the file and take-up reels. For this purpose, vacuum-buffer columns are used. The capstan does not
directly move tape from one reel to another; rather, it removes tape from one vacuum column and
deposits it in another. Each reel motion servo system endeavors to keep its associated vacuum-buffer
column half-filled with tape, ready either to supply or to take up tape, as might be required by a
sudden acceleration of the capstan.
Figure 8-15 shows the tape transport vacuum-buffer columns and the respective tape-positioningsensing vacuum switches; this figure is referred to again later in this section. A vacuum port at the
bottom of each vacuum-buffer column provides the vacuum that draws the tape loop into the column
with a constant tension, independent of the position or velocity of the tape loop. This ensures a good,
uniform wrap of the tape on the reel. In normal operation, the position of the tape loop in each
vacuum column is sensed by a vacuum switch located near the top of each column, i.e., the upper
motor upper vacuum switch (take-up reel column) and lower motor upper vacuum switch (the file reel
column). These vacuum switches close when subject to a vacuum exceeding 25.4 cm (10 inches) of
water and open when exposed to ambient air pressure. Thus, if the tape loop is above the upper
vacuum switch in the buffer column, the switch is exposed to vacuum; the switch is then closed and its
corresponding signal (UVS for the upper vacuum switches and LVS for the two additional lower
vacuum switches) is at ground. If, however, the tape loop is below a vacuum switch in either column,
the switch is exposed to ambient air pressure; it opens and the corresponding signal is high.
The reel servo systems endeavor to keep the respective tape loops in the brake zones (i.e., between the
UVS and LVS of each column). Thus, if the capstan stops, each reel comes to rest with the tape loop in
its brake zone.

8-19

TAKE-UP REEL
(UPPE R MOTOR)

TAPE GUIDE ~;::",,""_<;============I
I,
I

UPPER FAIL SAFE
TRANSPORT WI LL
AUTOMATICALLY SHUT-DOWN]}
(FAIL-SAFE CONDITION)

,- -

UPR MOTOR UVS
TAPE WILL BE SUPPLIED TO
COLUMN (TAKE-UP REEL
TURNED OFF)

R/W ERASE
HEAD ASSEMBLY

;::=:~':V-TAPE GUIDE

I'
I

"'ffl'
I

_~FAIL

'-~

UPR MOTOR LVS
TAPE WILL BE EXTRACTED
FROM COLUMNll\
(TAKE-UP REEL TURNED ON)
I

SAFE
TAPE SUPPLIED
TO COLUMN

'-;

"
:®

.\
LOWER FAIL SAFE
I'
_~/I
TRANSPORT WILL
\
AUTOMATICALLY SHUT DOWN~ /
(FAIL-SAFE CONDITION)
-~

VACUUM CHAMBER
PORT

~~__~~_TAPE

LEFT VACUUM
COLUMN

VACUUM CHAMBER
PORT

EXTRACTED
FROM COLUMN
FAIL SAFE

RIGHT VACUUM
COLUMN

FILE REEL
(LOWER MOTOR)
10-1293

Figure 8-15

Tape Transport Mechanism

8-20

If, then, the capstan begins to put tape into a buffer, the loop moves down until it passes over the

column LVS and enters the lower zone. At that point, braking is removed and a command is sent to
the reel motor amplifier to accelerate the reel in order to empty tape from the buffer.
The tape loop continues to move down into the lower zone until the reel is emptying tape out of the
buffer columns as fast as the capstan is putting it in. As the motor continues to accelerate the reel, the
tape loop begins to move up again until it passes the LVS and enters the braking zone. The motor is
then turned off and braking is again applied. The tape loop continues to move up into the brake zone
until the rate at which the reel motor is removing tape from the buffer column is again equal to the rate
at which the capstan is putting tape in and, as the reel continues to decelerate, the cycle repeats. Thus,
the tape loop oscillates about the position of the L VS. If the capstan instead removes tape from the
buffer, the tape loop similarly oscillates about the UVS as the motor and brake alternately accelerate
and decelerate the reel while supplying tape to the buffer column at the average rate at which the
capstan is removing it. Figure 8-15 also shows the additional fail-safe vacuum switches used. These
switches, located above and below the UVS and LVS in each column, are used to detect a failure in the
tape transport mechanism that threatens to damage the tape.
Figure 8-16 shows an equivalent circuit of the reel motor drive. Each reel motor is connected across a
transistor bridge, which can connect the motor between the -17 V and + 17 V INT power supplies in
either direction. Under normal operating conditions, REEL MTR ENABLE L is asserted and the reel
motor responds to control by the vacuum switch signals. When a UVS is low (closed), the reel motor is
connected across the power supplies in the direction that drives tape into the buffer column. When a
UVS is high (open) and an LVS is low, indicating that the tape is in the braking region, the reel motor
is shut off. When both a UVS and LVS are high, the reel motor is connected across the power supply in
the direction that removes tape from a buffer.

+17V

•

1
A

1----- c

-----,

I
I
I

EMPTY: A and B closed
C and 0 open
FULL: A and B open
C and 0 dosed
NEITHER: all open

-17V
10-1294

Figure 8-16

Reel Motor Amplifier Equivalent Circuit
8-21

Each reel motor amplifier has an additional input, REEL MTR PLS H, which is used during the
loading sequence to start tape into the vacuum column. The REEL MTR PLS signal is asserted during
the tape loading sequence to cause the reel motor to feed a few inches of slack tape into the buffer
column sealing the buffer column and allowing vacuum to build up in the column. The loading
sequence is explained in more detail later.
When tape is not loaded, or when a failure is detected by the fail-safe switches, REEL MTR ENABLE
L is negated, disabling the vacuum switch signals. The +17 V INT is interrupted, removing power
from the reel motors.
Tape Reel Motor Control Operation - The reel motor's circuit operation still references sheets 5 and 6
of schematic H606-0-1 and Figure 8-15. Because the upper motor circuitry (take-up reel) functions
identically to the lower motor circuitry (file reel), only the lower motor circuitry is detailed in this
section.
Referring to Figure 8-15, notice that the file reel is associated with the right vacuum column. The
column is numbered 1, 2, and 3 with respect to what happens when tape is in one of those numbered
areas. The three possibilities are described in the following paragraphs.
1.

Supplying Tape to the Vacuum Column - Refer to the H606-0-1 schematic, sheet 5. When
tape is in position 1, both the LWR MTR UVS and LWR MTR L VS are exposed to the
vacuum and are, therefore, low. This places low levels at the bases of both Qll and Q12,
keeping them turned off and resulting in high level outputs from both collectors. With both
LWR MTR UPR SW (LWR MTR UVS inverted) and El-pin 11 high, signal LWR MTR
UVSjLVS is low.
Refer to H606, sheet 6. Signal L WR MTR UVS jL VS low puts a low level at the input (base)
of Q28, keeping Q28 off. This indicates the column is empty. The L WR MTR UPR SW high
level and REEL MTR ENABLE low make REEL MTR PLS high at the base of Q45,
turning Q45 on. The base of transistor Q43 is clamped approximately three diode drops
below + 17 V. The base of Q43 is lower in potential than the emitter potential, so it turns on.
This results in a voltage divider network from +17 V INT down through R141, R143, and
R144 to -17 V, resulting in approximately + 15 Von the collector of Q43 and -15 Vat the
junction of R143 and R144. The + 15 V is also present on the base ofQ42, turning it on; -15
V on the base of Q41 turns it on. Transistor Q42 places + 17 V INT on the LWR MTR R T
line. Transistor Q41 places -17 V on the L WR MTR line, resulting in 34 V across L WR
MTR. The LWR MTR (file reel) turns in a clockwise direction, placing tape into the right
vacuum column.

No Action - As soon as the tape enters the area marked 2 on Figure 8-15, the UVS is no
longer exposed to vacuum pressure, but instead is exposed to open air. This makes the L WR
MTR UVS line high, turning on Qll and making LWR MTR UPR SW low. With LWR
MTR UPR SW low and TP8 still high, signal LWR MTR UVSjLVS remains low. Now
both the LWR MTR UVSjLVS and LWR MTR UPR SW lines are low.
The LWR MTR UVSjLVS low level keeps Q28 off. The LWR MTR UPR SW low level
keeps Q45 off. With both Q28 and Q45 off, no paths are connected to drive the L WR MTR,
so nothing happens (motor does not turn).

8-22

Remove Tape from the Vacuum Column - If tape continues to go into the right vacuum
column (the capstan may be putting it in), it passes point 3. Now both the UVS and LVS are
exposed to air pressure, putting ground levels at the bases ofQll and Q12, turning them on;
LWR MTR UVS/LVS becomes high and LWR MTR UPR SW becomes low. The high
level of L WR MTR UVS/L VS turns Q28 on and LWR MTR UPR SW low makes REEL
MTR PLS low, turning Q45 off. Transistor Q28 turned on creates a voltage divider from
+ 17 V INT, through R120 and R119 to ground. The base ofQ40 is clamped in the same way
Q43 was, placing about + 15 V at its base; this turns Q40 on. The approximate voltage of
+15 V at the base of Q39 turns Q39 on. The -15 V at the base of Q44 turns Q44 on.
Transistors Q39 and Q44 operate in a manner similar to the Q41-Q42 combination (when
the tape was in position 1). However, in this instance, the + 17 V INT is connected to the
LWR MTR line (through Q39) and the -17 V is connected to the LWR MTR RT line
(through Q44). This puts +34 V across the LWR MTR with polarity opposite that of the
supplying tape case, resulting in the reel motor turning in the opposite (counterclockwise)
direction and removing tape from the right vacuum column.

Tak.e-Up Reel Operation - The theory and logic operation for supplying and removing tape from the
left vacuum column (take-up reel) is almost identical to the file reel operation. The exception is that
when supplying tape to the column, the take-up reel turns counterclockwise (as opposed to clockwise
for the file reel), and, when removing tape, it turns clockwise.
Transistors Q47 and Q50 create the network to place + 17 V INT on the UPR MTR RT line and -17 V
on the UPR MTR lines, turning the UPR MTR counterclockwise to supply tape to the left vacuum
column. Transistors Q46 and Q51 reverse the polarity of the voltage across the UPR MTR and turn it
clockwise removing tape from the left vacuum column.

Brak.e Control Operation - The brake control logic is illustrated on schematic H606-1, sheet 5. The
brakes used on the TU lOW are electromagnetically opera ted friction brakes. In normal l.14 m (45
inches) per second operation, when UPR MTR UVS is high and UPR MTR L VS is low (i.e., when the
tape loop is in the braking zone), approximately 310 rnA of current is driven through the brake winding. With signal UPR MTR UVS high and signal UPR MTR LVS low, UPR MTR UVS/LVS becomes low. Tracing the AND of UPR MTR UVS/LVS and UPR MTR UPR SW through, note that
UPPER BRK ON H is true. This high level turns Q19 on; this turns Q18 on which, in turn, allows the
Q20 current driver to apply 3lO rnA of current to the brake winding (as UPPER BRK OUT). This
produces enough torque to rapidly stop the take-up reel.
When the tape loop moves out of the brake zone, the current is shut off. Because the braking current
tends to produce a significant residual magnetism in the brakes, a short (15 ms) pulse of about 150 rnA
current is applied in the reverse direction when the brakes are released to ensure complete demagnetization and release of braking. As the tape moves out of the brake zone, UPPER BRK ON goes away.
This low transition is ac coupled through C25 to Q21 and Q22 (as UPPER BRK ON), resulting in the
short pulse. Zener diode D25 and R71 (the collector resistor) cause the smaller (150 rnA) current.

8-23

During high-speed rewind, the operation of the brake circuitry must be modified somewhat to avoid
stopping the reel whenever the tape loop enters the braking zone. Without this modification, the reel
motor could not accelerate the reel to 38.1 m (150 inches) per second rapidly enough to prevent failure.
For this reason, when REWIND CAP H is asserted and the tape loop enters the brake zone, only a
short pulse of braking is applied to the reel to slow it down but not to bring it to a halt. In the case of
the take-up reel servo, if the tape loop remains in the braking zone longer than about 50 ms, a low
current of about 60 rnA is applied to the brake, further decelerating the reel. As REWIND CAP H
becomes asserted, signal LOW REWIND BRK L is asserted, placing a low level input to the base of
Q23. This turns Q23 on and allows Q20 to pass an additional low current out UPPER BRK OUT. In
the case of the lower (file) reel, this additional stop current is not necessary. The file reel brake control
logic otherwise operates identically to the take-up reel braking system. Signal LOWER BRK OUT is
the line to the file reel brake coil. The path for normal braking (when LOWER BRK ON high is
asserted) is through transistors Q15 and Q16 to drive 310 rnA out of the LOWER BRK OUT line. To
compensate for the residual magnetism in the brake coil, when LOWER BRK ON is negated, the
LOWER BRK ON low transition is ac coupled through Q53, allowing Q17 to apply the necessary
reverse current to LOWER BRK OUT.
The difference in braking of the two reel systems occurs because the upper reel is dumping tape into the
buffer during rewind and is, therefore, accelerated by torque resulting from the tape tension produced
by the vacuum column. The lower reel, however, is removing tape from its buffer and, therefore, the
tape tension tends to decelerate the lower reel, making low drag braking unnecessary.
Figure 8-17 shows the brake current waveforms of each reel system during both 11.4 m (45 inches) per
second and rewind operations. Whenever tape is not loaded or the fail-safe switches detect a failure,
and the LOAD/(OFF)/BR REL switch is not in the BR REL position, signal FORCE BRK ON low
is asserted. This signal causes high (310 rnA) braking to be applied to both reels, regardless of the
signals from the vacuum switches.

310mA
UPPER-REEL BRAKE
CURRENT WITH
REWIND CAP ASSERTED

HIGH BRAKE

a
-15-40ms

LOWER-REEL BRAKE
CURRENT WITH
REWIND CAP ASSERTED

EITHER BRAKE CURRENT
WITH REWIND CAP
NEGATED

BRAKE H a
NOTE:

15ms DEGAUSSING
CP-0215

Figure 8-17

Brake Current Waveforms

8-24

8.7.2 Motion Control Logic
The motion control logic, shown on the M8910 (LAW) drawings, provides the necessary sequencing
and control for loading tape rewinding, brake release, and shutting down the TUIOW if power or the
tape unit itself should fail. Its main sections are listed and explained below.
Power Clear - The power clear circuitry consists of a power transient detector and one-shot. When the
+ 5 V power supply is turned on, the circuit produces P CLR L, which produces LOCAL H; this
produces a I5-ms clear pulse (DELAYED LOCAL L) that resets all of the various status flip-flops of
the TU lOW to the idle, unloaded, off-line condition, keeps all motors turned off, and asserts braking
on the reels. Similarly, when the + 5 V power supply drops to approximately 4.4 V, a PWR CLR pulse
is produced that lasts for 20 ms, or until the power supply drops too low to operate the power clear
circuitry (approximately 3 V).
Servo System Failure Detection - As explained in previous text, two fail-safe switches, located in each
vacuum-buffer column, define the permissible limits of excursion of the tape into those columns. If the
tape loop in either buffer column goes below the lower fail-safe switch, the switch opens and LFS H is
asserted. If either tape loop is above its upper fail-safe switch, then UFS L is asserted. When VACUUM ON (0) L is asserted, indicating that tape is loaded, and either LFS H goes to 1 or UFS L goes to
0, then the FAIL flip- flop (LAW 5) is set. The effect of FAIL (l) is essentially the same as that of the
CLR PLS pulse, except that FAIL (1) is a level and remains asserted, preventing tape unit operation
until manually reset by moving the LOAD /(OFF)/BRK REL switch to its central OFF position.
Loading Sequence Logic - Initiation and shutting down of the reel motors, brakes, and function control logic is controlled by the loading sequence logic. The loading sequence logic consists of the
RELAY ENABLE flip-flop, the REEL MTR ENABLE L and VACUUM ON L one-shots, and their
associated gating. The RELAY ENABLE flip-flop is reset by either FAIL (1) or the
LOAD /(OFF)/BRK REL switch being in the OFF position. When RELAY ENABLE is reset, the
vacuum motor is turned off. Also, the power supply interrupts PWR COM INT and + 17 V INT,
which turns off power to the reel and capstan motors. The REEL MTR ENABLE L one-shot is held to
its 1 state, negating REEL MTR ENABLE L; the VACUUM ON L integrating one-shot is held to its
I state, negating VACUUM ON L. These prevent the function control logic from responding to any
command.
The RELAY ENABLE flip-flop is set by LOAD PULSE L, a pulse produced when the
LOAD/(OFF)/BRK REL switch is brought to the LOAD position. When the RELAY ENABLE flipflop is set, the vacuum motor is turned on; RELAY ENABLE L is asserted, clearing FORCE BRK
ON and generating REEL MTR PLS (H606, sheet 6). Both PWR COM INT and + 17 V INT are
restored. Signal REEL MTR PLS causes each reel motor to dump a small amount of tape into the top
of its buffer column, sealing it and allowing vacuum to build up in the column. When the lower failsafe switches in both vacuum columns sense vacuum, the REEL MTR ENABLE L and VACUUM
ON L delays are allowed to begin timing out. Approximately 100 ms is allowed for the vacuum to
build up and stabilize before the REEL MTR ENABLE L one-shot times out, asserting REEL MTR
ENABLE. When REEL MTR ENABLE is asserted, the reel servos can function normally, bringing
the tape loops to the middle of the buffer columns.
Approximately 3 seconds later, the VACUUM ON L one-shot times out, asserting VACUUM ON.
This allows the function control logic to accept commands and also enables failure detection. The tape
loading sequence is then complete, and the transport remains loaded until the RELAY ENABLE flipflop is reset.

8-25

Brake Release - When the FORCE BRK ON flip-flop is set, full braking is applied to both reels. It is
set whenever the RELAY ENABLE flip-flop is reset, and is cleared whenever RELAY ENABLE is
set. The FORCE BRK ON flip-flop can also be cleared by BRK REL SW L, the signal asserted when
the LOAD /(OFF)/BRK REL switch is in the BRK REL position, provided that LFS H is asserted.
Thus, the lower vacuum switches prevent brake release until the vacuum has drained out of the buffer
columns. Moving the LOAD/(OFF)/BRK REL switch from BRK REL to the center OFF position
causes RELAY ENABLE L to be asserted, again setting the FORCE BRK ON flip-flop.
Rewind Control- Due to the limited rate at which the reels can be accelerated and decelerated, a special
sequence of control signals must be generated to perform a high-speed rewind operation. The sequence
is shown in Figure 8-18. When the function control logic accepts a rewind command, it asserts (see
drawing LAW 7) signal SET RWD CMD L, which direct sets the RWS flip-flop.

RWS H
0

REWIND CAP DLY H
(E52 pin 13)

REV/REW H
0

REWIND CAP H
0

FWD H
0

BOT H
0
140 ms del H
(E52 pin 5)

FOR H
0
CAPSTAN
VELOCITY

+45 ips
0
-45 ips
10-1296

-150 ips

Figure 8-18

Rewind Sequence Timing

8-26

A high level is presented to the pin 12 input of the 7400 gate in location E41 (LAW 5). This asserts
signal REV /REW H, which accelerates the capstan servo to 11.4 m (45 inches) per second in the
reverse direction. At the same time, RWS H triggers a 300-ms delay, which allows the reels to stabilize
at 11.4 m (45 inches) per second. When the delay times out, it asserts signal REWIND CAP H. The
REWIND CAP H signal causes the capstan servo to gradually accelerate to 38.1 m (150 inches) per
second in the reverse direction.
Normally, rewinding continues until the function control logic detects the beginning-of-tape (BOT)
marker. When BOT is detected, the function control logic asserts FWD L (LAW 7) and removes
REWIND CAP H. The assertion of FWD L triggers the 140-ms delay (enabled by RWS H). Normal
braking is applied and the capstan servo gradually decelerates toward 11.4 m (45 inches) per second,
still traveling in the reverse direction past BOT.
When this delay times out, the forward command is passed on to the capstan servo as FOR H (LAW
5). The capstan accelerates from 11.4 m (45 inches) per second in the reverse direction to 11.4 m (45
inches) per second forward. The tape then moves forward until the BOT marker is again detected. At
this point, the function control logic clears FWD L, FOR H, and RWS H, and the capstan comes to a
stop, terminating the rewind.
The rewind control logic is designed so that if the rewind is terminated at any point in the sequence, the
operation stops without failure and without danger of "spooking" the tape.
Tape Unit Ready and Transport Settling Down - The RUNNING H and signals indicate whether the
transport is idle (ready to begin an operation) or settling down (coming to a halt after performing an
operation). When the tape transport is on-line and selected by its controller, it transmits the signals to
the controller to notify the controller when it is able to accept another command.
Whenever an operation is being performed, the function control logic asserts MOTION H. The OR of
MOTION H (operation in progress) and LOCAL H (unit off line) sets the RUNNING Hone-shot
delay (LAW 5), thereby asserting RUNNING H and also inhibiting the settle-down signal, SDWN
(SB) 1. When both MOTION H and LOCAL H are negated, the RUNNING H one-shot begins to
time out and SDWN (SB) L is asserted, indicating the transport is ready to accept a command to move
tape in the same direction as the previous command. After approximately 13 ms, when the capstan has
had time to come to a complete stop following any previous operation, the RUNNING Hone-shot
times out, negating SDWN (SB) L and, provided MOL H is asserted, asserting Tape Unit Ready
[TUR (SB) L], thereby indicating that the unit is ready to accept any command.
8.7.3 Manual Control Operation
Manual operation of the TU10W Tape Transport is effected by the operator control box switches. The
detailed operation of each of the switches is explained in this section.
LOAD I( OFF)/BR REL - This switch has three operations. In its center, or OFF position, signal OFF
L is asserted to clear the FAIL and RELAY ENABLE flip-flops. When the switch is brought to the
LOAD position, signal OFF L is negated and LOAD PULSE L is asserted for a few microseconds,
setting RELAY ENABLE H and initiating the tape loading sequence. When the switch is brought to
the BR REL position, OFF L is asserted again and the BRK REL SW signal is asserted low for
brakerelease. For a more detailed explanation of these operations, see the relevant sections of Paragraph 8.7.2.

8-27

ON-LINEjOFF-LINE - When this switch is quiescent in either position, no output occurs to change
the state of the transport. When it is moved from the ON-LINE to the OFF-LINE position, OFF
LINE SW is momentarily asserted low, setting LOCAL H (LAW 6). When the ON-LINE/OFF-LINE
switch is moved from its OFF-LINE to its ON-LINE position, ON LINE SW is asserted low momentarily, negating LOCAL H.
Unless a rewind operation is in progress, the assertion of either OFF LINE SW L or ON LINE SW L
causes the assertion of INIT L (LAW 8). The assertion of INIT L clears the FWD, R WS and REV flipflops and brings tape motion to a halt.
The LOCAL signal controls the operating mode of the TUlOW Tape Transport. When LOCAL L is
negated, the transport is on-line and all operations of the transport are directed by the controller via
the slave bus (SB). When LOCAL H is asserted, the transport is off-line and is, effectively, isolated
from the slave bus. In this mode, tape motion is controlled by the FWD/REW /REV and
STAR T /STOP switches, as discussed below.
FWD jREWJREV - This 3-position switch selects the direction of tape motion for off-line operations
(LA W 7). When it is in the FWD position, MANUAL FWD L is asserted; in the REW position,
MANUAL REW L is asserted; and in the REV position, MANUAL REV L is asserted. These signals
do not initiate tape motion, but are strobed by the START L pulse as explained below.
STARTjSTOP - When this switch is moved from its START position to the STOP position, signal
STOP L is asserted for a few microseconds. If the transport is off-line (LOCAL H asserted), this causes
a corresponding pulse at INIT L, clearing the FWD, REW, and REV flip-flops and bringing tape
motion to a halt. When the START/STOP switch is moved to the START position, START L is
asserted, directly setting a flip-flop (at coordinates D-7 of drawing LAW 7). The high-going transition
of this flip-flop is ANDed with LOCAL H (transport off-line) and MOTION L (no operation in
progress) to produce a pulse that strobes the MANUAL FWD, REV, and REW lines in an 8266
multiplexer. The assertion of one of these lines causes the FWD, REV, or RWS flip-flop to be set,
initiating tape motion in the indicated direction. Note, however, that if BOT H is asserted, the signal
that sets the RWS flip-flop is gated off because the tape is already at BOT. Note also that if END PT H
is asserted and FWD H is set, then INIT L is asserted to clear the FWD flip-flop and prevent running
off the end of the tape.
8.7.4 Tape Unit Status Sensors
The tape status (EOT /BOT) and write lock sensor features are discussed in this section.
EOT jBOT Sensor - To locate the beginning and end of the recording area on the tape, the load and
end points are marked by reflective strips mounted on the non oxide side of the tape. The dimensions
and placement of these strips are shown in Figure 8-19.
The strips are detected by the phototransistors of the EOT /BOT sensor assembly. The EOT /BOT
assembly is located in the wall of the lower vacuum column. It consists of an EOT sensor phototransistor, located to detect light reflected from the EOT strip; a BOT sensor phototransistor, located to
detect light reflected from the BOT strip; and two light-emitting diodes (LEDs), which illuminate the
EOT and BOT strips. The LEDs operate in the infrared region and, therefore, produce no visible light.
The outputs of the EOT /BOT assembly are amplified, filtered, and converted to logic levels, as shown
on drawing M8910 (LAW), sheet 6, producing signals BOT (SB) L, END PT H, and END PT (SB) L.

8-28

14~_ _ RECORDING

AREA _ _---<>I
SEE NOTE 2

PHOTO REFLECTIVE MARKERS
SEE NOTE 1

0.03-IN. MAX

HUB

REFERENCE
EDGE

-_-_t~~__

L-_ _ _ _

_,_J

FT~

25 FT. +5FT.
-OFT.

I BOT

0.49B

EDT

:!:0,002IN.

)r----.~ RIM END

I t

0.03:IN. MAX

r--15FT._1FT.----j

BACK SIDE~

MAGNETIC

::7

+ :!:

0.0019
0,0003 IN.

HUB END

MAGNETIC SIDE

FRONT VIEW
SCHEMATIC OF TAPE WINDING

NOTES:
{II Photo renective markers shall not protrude beyond
edge of tape and shall be free of wrinkles and excessive adhesive. Marker dimensions: length. 1.2 ± 0.2 inch: width.
0.19 ± 0.02 inch; thickness. 0,0005 ± 0.0001 inch.
(2) Minimum for test area: maximum for recording.
(3) Tape shall not be attached to the hub.

CP-0223

Figure 8-19

Tape Markers, Recording Area, and Tape Wind

The assertion of END PT H sets a flip-flop that remains set until either the tape is rewound or EOT is
negated while the tape is traveling in the reverse direction. Thus, if the tape is moved forward past the
EOT marker, the END PT flip-flop remains set even after the marker is passed and is cleared only by
rewinding or reversing the tape back past the EOT marker. Setting the END PT flip-flop has the
following effects:
1.

If the TUIOW is off-line (LOCAL H asserted), forward tape motion stops and the transport

does not accept manual forward commands until the tape is rewound or reversed off the
EOT marker.
2.

The End Point indicator lamp is lit.

If the TUIOW is on-line and selected by the controller, the TUIOW signal END PT (SB) Lis

asserted, indicating to the controller that it has passed the end point.
NOTE
Notice that if the TUlOW is on-line, it does not stop
automatically upon detecting EOT. It is permissible
to write data up to 3 m (10 ft) past the end point. It is
up to the program to ensure that the tape does not
run past this point.

8-29

The assertion of BOT H has the following effects:
1.

The TUIOW accepts no new rewind commands.

When the TUIOW rewinds into BOT (i.e., RWS H is asserted, FWD L is negated, and BOT
H becomes asserted), the FWD flip-flop is set (drawing LAW 7); refer also to the description
of rewind operation, Paragraph 8.7.2.

When the TUIOW moves forward into BOT, the FWD flip-flop is cleared. (If the RWS flipflop is set at this time, clearing FWD also clears RWS, terminating the rewind sequence.)

The LD PT indicator is lit.

If the TUIOW is on-line (i.e., LOCAL L negated) and selected by the controller, it asserts the
transport bus signal BOT (SB) L, indicating to the controller that it is at BOT.

Write Lock - To protect tapes from inadvertent erasure, tape reels are provided with a write enable
ring. If a reel of tape is mounted on the TUIOW Tape Transport with its write enable ring removed,
this condition is sensed and the transport refuses to honor any write commands. Further, if the transport is on-line and selected by its controller, it asserts WRL (SB) L to the controller, indicating to the
controller that it is write-locked.
The physical write-lock assembly consists of the write-lock solenoid and the write-lock switch. When
no write enable ring is inserted in the file reel, a feeler attached to the end of the solenoid shaft extends
into the write-lock slot on the back of the reel. This feeler puts the write-lock switch in its normally
closed position, asserting WR LOCK L (drawing LAW 8). When a write enable ring is inserted in the
file reel, the ring pushes back the solenoid shaft, actuating the write-lock switch and negating WR
LOCK L. If the write enable switch is actuated, + 17 V INT is turned on (i .e., when tape is loaded in
the buffer columns) and the write-lock solenoid is engaged and withdraws the write-lock feeler from
contact with the ring. This keeps the write-lock switch actuated until the tape is unloaded and reduces
wear of the write-lock assembly and write enable ring during tape unit operation.
8.7.5 On-Line Operation
When signal LOCAL L is negated, the TUIOW is on-line. In this state, all transport operations are
directed by the controller via the slave bus. The slave bus connects the controller to up to eight TU 1OW
Tape Transports.
8.7.5.1 Transport Selection and Status Reporting - All ofthe tape transports in a system communicate
with the same slave bus, but only one transport can be logically connected to the bus at one time, i.e.,
only one transport can transmit its status to the controller and respond to commands, and only one
transport can be reading or writing data at a given time.
To select the particular tape transport to converse with the tape controller, the controller transmits a
binary code on bus lines SEL 1 L, SEL 2 L, and SEL 4 L. As shown on drawing M8910 (LAW), sheet
6, each transport on the bus compares this code to the transport number determined by the unit select
plug (signals SWl, SW2, and SW4). If the selection code transmitted by the controller matches the
transport number, and the transport is on-line, the SELECT lamp lights and the transport logically
connects itself to the slave bus. All other transports remain logically disconnected and neither transmit
nor respond to bus signals.

8-30

When a particular transport is logically connected to the slave bus, it transmits status information to
the tape control as follows:
7CH (SB) L

Asserted when a 7-track tape drive has been selected.

BOT (SB) L

Asserted when the tape is positioned at load point (beginning of tape).

END PT (SB) L

Asserted when the End Point flip-flop is set.

WRL (SB) L

Asserted when the TUlOW Tape Transport is write-locked.

RWS (SB) L

Asserted when the Rewind Status (RWS) flip-flop is set.

SDWN (SB) L

Asserted when the transport is settling down following an operation, i.e.,
asserted for about 13.5 ms following the command to terminate an operation
while the capstan is coming to a halt.

TUR (SB) L

Asserted when the tape unit is ready to receive any command, i.e., when the
transport is neither performing an operation nor settling down following an
operation.

8.7.6 Tape Motion Initiation (On-Line)
Refer to Figures 8-20 and 8-21 while reading this section.

SELECT L

SLAVE SET PLS L

TUR (S8) L

EMD (S8) L

1 . .______________. . . .II.
~

LJ
-j

START MOTION
DELAY

ACCL L

-I STOP
MOTION rDELAY

WRT CLK H _ _ _ _ _ _ _ _ _----'ruur~~~-------n-----------------n~~JlJl'__

STOP L

r----------~~~I--------~
~(~)------~~

SOWN (S8) L

11-4688

Figure 8-20

Tape Motion Timing

8-31

CONTROLLER
CONTROL
REGISTER
LOADED
(GO BITSETI

TUlOW

SET PULSE

-1+- l

INTERFACE

SLAVE SET
PULSE

l
ENABLE
MOTION
DELAY

I
I
I
I

SET FWD FF

:",m:c I

IsET WR ENAB FF

*
PLACE TU10W
OFF-LINE

GENERATE FOR.
REV/REW&
REWIND CAP

I I

ENERGIZE WRITE
& ERASE HEADS

1
DRIVE CAPSTAN
SERVO

COUNT UP
UNTil BIT
14SETS

!
NEGATE ACCL L

SET REV FF

T
GATE OUT
MOTION DELAY
PRESETS

LOAD MOTION
DELAY COUNTER

WRITE
ASSERTED

YES

11
I

I
I

YES

ASSERT
READING l

I
I

11-4687

Figure 8-21

Tape Motion Initiation Flowchart

If a TUIOW is selected, on-line, and loaded with tape (MOL H asserted), it responds to DRV SET PLS
and the FWD, REV, and RWND command lines of the slave bus by setting the corresponding motion
control flip-flops [i.e., FWD, REV, and RWS (rewind status) flip-flops on LAW 7]. If the WRITE
command line is asserted, along with the RWND command line, SET OFFLINE L is generated,
setting the LOCAL flip-flop (LAW 6). If WRITE is asserted but RWND is not, SLAVE SET PLS
produces SET WRE (Set Write Enable), which sets the WR ENAB flip-flop (LAW 8).

The outputs of the Motion Control flip-flops produce FOR H, REV /REW H, and REWIND CAP H
(LAW 5) signals, which control the capstan servo and drive circuits as described in Paragraph 8.7.1.1.
At the same time, the WR ENAB flip-flop, if set, generates WRITE ENABLE H, which shunts
WRITE voltage to the write and erase heads, thereby energizing the heads. This causes tape to be
erased, generating IRG as the tape comes up to speed and the start motion delay times out. Simultaneous with motion initiation, EMD L gates the motion delay presets onto the read data lines of the slave
bus (SC 2) and loads them into a motion delay counter in the interface logic. When EMD L is negated,
the counter is upcounted until bit 14 sets, at which time ACCL H and READING L are asserted, and
further clocking is inhibited. The presets of the counter determine the time interval necessary to reach
the count, and hence the duration of the motion delay. When write extended IRG or write tape mark
operation is performed, the presets to the motion delay may be modified. Modification occurs only
when starting in the forward direction, not from BOT (E60 pins 3, 4, 5, and 6); this produces an
extended IRG on tape. The presets depend on the type of operation performed (read/write), the
direction of tape motion, and other parameters. Table 8-3 lists the motion delays generated under the
various conditions. READING L enables the read circuitry in the interface logic. ACCL L is transmitted to the TUIOW, where it enables generation of WRT CLOCK and other read and write
functions.
Table 8-3 Start and Stop Motion Delays
Start/Stop

Mode

Operation Times (ms)
9-Track
7-Track

Start Motion Delays

Write from BOT
Write
Read from BOT
READ/SPACE FWD/SPACE REV

184.60
8.99
150.60
2.72

200.70
15.26
86.94
0.924

Stop Motion Delays

WXG /WFMK/WRITE
READ/SPACE FWD/SPACE REV

2.72
1.82

Once forward or reverse tape motion is initiated, it continues (unless a TUlOW mechanical or power
failure is sensed) until the interface logic transmits STOP L asserted to the transport.
If a rewind operation is being performed, STOP L is asserted as soon as SLAVE SET PLS is negated.
However, since the Rewind Status flip-flop is already set, this does not produce an INIT L pulse (LAW
8) and does not terminate motion. Once the Rewind Status flip-flop is set, the TUlOW performs the
rewind operation independently, as described in Paragraph 8.7.2. The TUlOW notifies the controller
that it is performing a rewind by asserting R WS (SB) L on the slave bus. When the rewind control
sequence is over, motion terminates automatically.

8.7.7 Tape Motion Termination (On-Line)
The TUlOW terminates tape motion when an INIT L pulse (generated on LAW 8) clears the Motion
Control flip-flops (LAW 7). Several sequences cause this to happen, depending on the type of operation being performed (Figure 8-22). The various sequences are discussed in the following paragraphs.

8-33

CLEAR WR
ENAB F.F.
(IF SET)

11-4668

Figure 8-22 Tape Motion Termination Flowchart

8-34

8.7.7.1 Read - During a read operation, the motion termination sequence begins when the drive
receives a STOP pulse. An explanation of how the controller shutdown sequence functions is provided
in the interface logic theory section of this manual.
At the completion of the shutdown sequence, STOP L is asserted and transmitted to the TU lOW.
STOP L produces the INIT L pulse (LAW 8), which clears the FWD or REV Motion Control flip-flop
and thereby causes the capstan activating signal to be removed. As tape motion slows down, SDWN L
is asserted by the TU lOW and transmitted to the controller. When tape motion stops, RUNNING H
is negated, while TUR L is asserted and transmitted to the controller.
8.7.7.2 Write- Motion termination during a write is almost identical to that during a read. When
tape motion ceases, RUNNING L is negated and clocks the WR ENAB flip-flop clear, thereby deenergizing the write and erase heads.
8.7.7.3 Space - Termination during a space is similar to that of a read. Each time an LRCC is
detected, a stop motion delay is generated and STOP L is transmitted to the TU lOW, clearing the
Motion Control flip-flop. However, once the drive begins to slow down, a start motion delay is triggered. This causes the Motion Control flip-flop to be set once again. Thus, start motion delays and
stop motion delays are produced as each record is spaced.
8.7.7.4 Rewind -Once the RWS flip-flop in the TUIOW is set, the transport independently performs
the rewind operation. The transport rewinds past the BOT marker, then spaces forward until it encounters the BOT marker again. This causes INIT L to be generated (LA W 8), which clears the RWS
and FWD Motion Control flip-flops (LAW 7). When tape motion ceases, RWS (SB) L is negated on
the slave bus.
8.8 READ (NRZ)
This section discusses the operation of the TUlOW read circuitry when operating in NRZ mode.
8.8.1 Read Heads and Amplifiers
As tape moves past the read heads, flux transitions on the tape cause the read heads to produce voltage
pulses; the direction of flux transitions determine the polarity of the output pulses. The read preamplifier (Figure 8-23 and G056 schematic), consisting of two type 72733 differential amplifiers, then
inverts the read head signals. Each differential output of the read preamplifier is inverted and further
amplified by a group of three transistors; the final two transistors operate in push-pull mode. The
resulting amplified differential signals are then input to opposite sides of a delay line. A phase shift of
about 6 degrees (Figure 8-24) occurs across the delay line; this phase shift is utilized by the peak
detector. The peak detector is a comparator circuit whose output changes state when the relative
magnitude of its inputs change (i.e., when one input becomes greater or less than the other); this occurs
at the peaks of the read head signals.
Peak detector circuit output transitions are converted into pulses by the dual edge pulse amplifier;
these pulses strobe the dual threshold gate. The dual threshold gate compares its input (amplifier
output) to positive and negative threshold voltages (Figure 8-25). If the input is more positive than the
POS RD THRESHOLD at strobe time, a negative pulse is produced at the + output. If the input is
more negative than the NEG RD THRESHOLD, a negative pulse is produced at the - output.
Read threshold voltages are determined by the signal WRE H input to a 74156 data selector chip
(Figure 8-25). Depending on these inputs, one of two transistors is turned on. (Only two of four
transistors are used in this setup.) Because each transistor has a different collector resistor, a programmable current (+ Threshold V oltage) is obtained. The + Threshold Voltage is fed to a 72741 operational amplifier to produce an equal but opposite polarity - Threshold Voltage. These threshold
levels are used by the read amplifiers to establish the lowest acceptable signal level.

8-35

r;-;M~I;;- -

- l ~U~T;S~D-;;~

I
I
A\

READ
HE AD\::::::!)

I
L

_____

I I
I I
I I
I®
I
I
I I

r;E~D;;F~-~P-1

I
STRB

PACKET L

r--"'---I@

RDn(ll

7476

~--+--OC

75107

II
+
I I
®
I
I
I
.J _ _ _ _ _ _
L _ _ _ _ _ -.J

G~I~---"

INPUT

-1------;---'
NEG READ
THRESHOLD
POS READ
THRESHOLD

RDn(O)

CLEAR READ
BOARD L

r;~~C-;;---" ro~~E--l

II
II
©II

I I

PULSE AMP

I
I
I

II ~
L_____ J L______ J L___ ~J
11-4686

Figure 8-23

Equivalent Circuit of Read Circuitry for One Track

8-36

AMPLIFIER OUTPUT @

COMPARATOR INPUTS@

COMPARATOR

?~;:EU~)© 1111111111111111LJlIIIIIIIIIIIIIIIIIIIIIIII~111111111111111111111111111111111111111111111111111111u--L11111111111II

PULSE AMP OUTPUT@

1111111111111111~111111111111111111111111~1111111111IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~IIIIIIIIIIII

75107-0UT

CLEAR READ
BOARD L
(NOTE 2)

75107 + OUT@

®
®

RD n (l)@
--'
NOTES:
1. Oscillations occur at this output
when input is at zero.
2. Generated on M891t
10-1306

Figure 8-24

Read Amplifier Waveforms (NRZ)

8-37

f75107 DuALTHRESHoLDGATEI

+5V

+ THRESHOLD

I<EQUIVALENT CIRCUIT)

VOLTAGE

WRE H

INPUT
(FROM AMPLIFIER)

+3V

NRZ·WRE
NRZ·WRE

WRE
H B

STRB

11-4684

Figure 8-25

Programmable Threshold

Whenever the dual threshold gate produces an output pulse, PACKET L is asserted, and the Read
Data flip-flop is set. This signifies that a one-bit has been detected on the tape track. Because of parity
conventions, at least one of the TUI0W's read amplifiers will detect a flux transition (a one-bit) as a
tape character is read. When the first one-bit of a tape character is read, and the corresponding Read
Data flip-flop is set, START SKEW DELAY is asserted. This sets the Skew flip-flop and initiates a
read deskew timing sequence, at the end of which SDO H (Skew Delay Over) and RSDO (Read Strobe
Delay Over) are asserted.
SDO H generates CLEAR READ BOARD L, which clears the Read Data flip-flop in each read
amplifier. RSDO L is transmitted via the slave bus to the interface logic where it is used to generate
CRDS H (Read Strobe) for the controller.
The read deskew timing sequence during a read data operation differs from that of a write operation.
During a read data operation, the skew delay counter (two 74197s) loaded with a preset that depends
on the tape data density is up-clocked at 1.15 MHz when the Skew flip-flop is set. When the counter
reaches a count of 100, SDO H is asserted; this occurs approximately 50 percent into the data cell.
With SDO H asserted, the Skew flip-flop is reset on the next negative-going clock edge. This causes the
counter to be reloaded; SDO H is thereby negated. The deskew timing sequence will reoccur each time
a tape character is read.

8-38

During a write operation, the counter presets are greater and as a result, SDO H is generated 35
percent sooner. When SDO H is generated, the counter is reloaded and upcounted until NTZO H
(Non-Trespass Zone Over) is asserted. At this time, the Skew flip-flop is reset and the deskew timing
sequence is over. If the read amplifiers detect a data transition (PACKET L asserted) while SDO H is
asserted, SET VPE L is generated and transmitted to the controller.
The outputs of the G056 read amplifier are routed to the slave bus via a type 8266 multiplexer on the
slave clock and motion delay module (SC 2). The read data signals are then transmitted to the
controller.
8.9 WRITE (NRZ)
This section discusses operation of the TUIOW write circuitry when operating in NRZ mode.
8.9.1 NRZ Data Write
The slave bus write data (WD) lines are received in the TUI0W by receivers in the LAW (M8910)
module (refer to LAW 3 and 4). The data is then gated by the write data multiplex (E5, E13 and E19)
to the write deskew buffer and nine XOR gates. The XOR gates cause the write deskew buffer to be
complemented for each 1 that is written. The write deskew buffer is clocked by SK CLK (skew clock)
pulses (LAW 4). These pulses are actually delayed REC L pulses, jumpered to compensate for static
skew in the write head. The write deskew buffer outputs are then driven to the write head.
8.9.2 NRZ Data Write Timing
Once a write data function is decoded, WRITE and FWD commands are placed on the slave bus by
the interface logic. Also, a SLAVE SET PLS is sent to the TUI0W. This initiates tape motion and sets
the Write Enable flip-flop (LAW 8). WRITE ENABLE switches current to the write and erase heads
(LAW 3). Because no flux reversals can be effected until WRT CLK (SC3) pulses are produced, the
tape is dc erased as it accelerates.
When the transport is up to speed (ACCL H negated), the TUlOW begins to transmit WRT CLK
pulses to the interface logic. The logic returns REC L pulses to the TUlOW, which causes the tape
character presently in the interface logic to be transferred to tape.
8.9.3 NRZ Tape Mark Generation
The interface performs the write tape mark operation; the tape mark character forced on the WD lines
is 23 (9-channel NRZ format). Refer to the interface logic theory section of this manual for details.
8.9.4 Tape Mark Write Timing
When the SLAVE SET PLS is produced, the write and erase heads are energized, causing the tape to
be erased throughout the start motion delay. At the completion of the delay, an REC L pulse clocks
the TUlOW write deskew buffer and transfers the tape mark character to tape. Refer to the interface
logic theory section of this manual for details.
8.10 TUI0W POWER SUPPLY
The TUIOW power supply is a forced air-cooled unit that converts single-phase, 115 V or 230 V
nominal, 47-63 Hz line voltage to four regulated output dc voltages (+5.3 V, + 12 V, +12 V, and -6.4
V) and four unregulated voltages (± 16 V and ± 17 V). The power supply is controlled by an 861 power
control. Each of the regulated voltages has short circuit (current foldback) protection. Overvoltage
(CROWBAR) protection is incorporated in the +5.3 V, -6.4 V, and one of the + 12 V circuits.

8-39

The power supply is divided into two sections (Figure 1-5): the ac input circuitry, consisting of the
transformer and large filter capacitors (transformer-capacitor assembly); and a regulator board, which
contains the remaining circuitry. The power supply circuit description references schematic D-CS5412242-0-1. The regulator board (Figure 8-26 and 8-27) contains all the circuitry between the transformer secondary winding and the power supply output cables. A 4-pin Mate-N-Lok connector (11)
supplies voltage to the fans and vacuum motor. Connector 12 connects the transformer secondary
winding outputs to the regulator board, while J3 adds the large filter capacitors to the circuitry. Connector J4 connects the supply to the H606 power board servo circuitry and J5 supplies voltages to the
TV lOW backplane.

$. ·
.

07
~

e
.

$
06

010
~
o

R26(+12)~

(NRZ)

R37(+12)-@
R44(-6.4)~

R57
(+5)

-® ,..--_---,

(N/A)

R59@(+5.3)

GND
AC HI

.-r;:;-t,
~

G
G@

AC LO

.~ tJ b5/ 0115 230 IT]115

5- --'+' \

0 [] 0

NOTES:

1) 1-5 represenl 5 Phillips head screws.
2) 6

represent Allen screw-must be secured very lighlly,or
damage to the power supply may
result.
11-4683

Figure 8-26

TV lOW Power Supply Regulator Board

FAN

POWER
WIRING

LOGIC
ASSEMBLY
FAN

R59;
+5 V
ADJUSTMENT

8209-8

Figure 8-27

TUlOW Regulator Board (Cover Removed) and Fan

8-41

8.10.1 Generation of Raw ±DC
The ac power line cord, terminated with tab connectors, is brought to the lower left-hand area of the
regulator board (as viewed from the rear of the TUI0W cabinet) and connected to the input power
tabs (AC HI, GND, and AC LO). Two wires (in the same area) connect to either the 230 V tab or the
115 V tabs, and configure the power supply for 115 V or 230 V operation. The J2 Mate-N-Lok connector interconnects the regulator board and the main transformer.
A general block diagram of the TUIOW power supply is shown in Figure 8-28. The center-tapped
transformer voltage is fused, rectified, and filtered prior to being fed to the various voltage regulators
and J4. The fuses do not normally blow when an output is shorted because of an overcurrent (current
foldback) protection. Overvoltage protection (CROBAR) is also used on all regulated outputs except
the + 12 (NRZ) output, which does not require it.
The J4 Mate-N-Lok plug connects the TUIOW power supply's unregulated voltages to the TUIOW
power board (H606, plug P2). Once tape is loaded onto the transport, signal RELAY ENABLE L is
asserted. This places a low signal at the inputs of the 75451 gate (schematic D-CS-5412242-0-1, location A 7) that enables the K2 relay. This relay passes required voltages on to the H606 module when
tape is loaded.
8.10.2 +5 Vdc Regulator Circuit
The +5 Vdc regulator circuit is shown in Figure 8-29. Raw dc voltage is input to pins 11 and 12 of the
723 voltage regulator. The output voltage from pin 10 is fed to transistors Q6 and Q5, which are series
regulators used to increase the current output capabilities of the circuit. Resistors R62 through R66
(inclusive) sense the output current. R62 is used as a current limit monitor by the 723. As the current
increases, the voltage across R62 increases. When a reference voltage is exceeded, the 723 begins to
turn off Q6 and Q5, impeding current flow. The current does not stop, but instead decreases to a safer
level; this is called current foldback. It assures that the output current never goes over 10.0 A. Refer to
Figure 8-30, which shows how the current foldback procedure works. As the current surpasses the
limit of 10.0 A, the conduction of Q5 and Q6 slows down (toward being shut off) until no voltage is
produced (at the short circuit current rating). The output voltage may be regulated. Resistors R58,
R59, and R60 divide the actual output voltage. Pin 5 of the 723 accepts the output feedback voltage
through R59; the adjustment of R59 regulates the +5.3 V output.
In addition to the current foldback feature, a voltage CROBAR circuit is used, offering overvoltage
protection. If for some reason Q5 or Q6 become shorted, the overvoltage protection circuit protects
any load connected to the power supply. When Q5 or Q6 short circuits, the output voltage starts
increasing very rapidly. As the voltage across the D16 zener diode becomes greater than 6.8 V, it
breaks down and begins conducting; it does not conduct during normal operation. Current now begins
to flow through R22. When the voltage at the junction of D 16 and R22 becomes greater than approximately 0.7 V (at the gate of DI5), the SCR fires and begins conducting. This offers a path for current
from the output to ground, shunting any load, thus protecting it. The SCR continues conducting until
the power supply is turned off or the 15 A fuse (FI2) is blown.
8.10.3 +12 Vdc Regulator Circuit (Write Circuits)
The + 12 Vdc regulator circuit is shown in Figure 8-31. It operates in a manner similar, but not
identical, to the + 5 Vdc regulator circuit discussed previously. In the case of the + 12 Vdc regulator, a
type 723 regulator is again used.

8-42

REGULATED DC VOLTAGES
(TO TU10W BACKPLANE)

F12

~RECTIFIER

AND
+
FILTER _

15A

r--.

VOLTAGE
REGULATOR

OVERCURRENT
PROTECTION
( CURRENT
FOLDBACK)

JOVERVOLTAGE1

·1 CROWBAR

•

AND
+
FILTER -~

I REGULATOR 1

)F10

+12V
( WRITE CIRCUITS)

+12V
( CONTROL

.IOVERVOLTAGE
1 CROWBAR

SWITCH
CIRCUITS)

1
1

) Fa
'--

OVERCURRENT
PROTECTION
( CURRENT
FOLDBACK)

-6.4V (EOT/BOT
CIRCUITS)

.IOVERVOLTAGE1
CROWBAR

RELAY

1
1

UNREGU LATED DC
VOLTAG ES (TO H606 POWER
BOARD)
-16V

1 FILTER

(NRZ) +3

'-'"

(

J RECTIFIER
+
AND
I

OVERCURRENT
PROTECTION
( CURRENT
FOLDBACK)

VOLTAGE
REGULATOR

....,-...

VOLTAGE
REGULATOR

Fl1

J "'iJ1~'"
FILTER +

-I

OVERCURRENT
PROTECTION
( CURRENT
FOLDBACK)

+5.3V (TU10W LOGIC)

J VOLTAGE 1

~ RECTIFIER 1

AC
TAPPED FROM
TRANSFORMER t-SECONDARY

~
F7~

Y t-

20A

RELAY
DRIVER

+16 V

+17 V

-17 V

VACUUM 0 N L

"-4682

Figure 8-28

TV lOW Power Supply Block Diagram

8-43

lvA

+ C6
~47

R69
10
lOW

+10.S V
FROM
RECTIFIER

JS, PINS 1, 7
+S.3 V
8.0A OUTPUT

R66
.03
SW
R6S
.OS
SW

6
R10
390
2W

RS8
7S0
S

R64
.OS
SW

El
723
R68
680

R67
100

01S
C9
.22

016
IN469A
R21
27
C12
.31

R63
47

C8
47

R62
330

J5,
PIN 6

11·4666

Figure 8-29

+5.3 Vdc Regulator Circuit

v
5.0

-+-------_

I SHORT

10 A

CKT
11-4681

Figure 8-30 Current Foldback Operation

8-44

017
+17V FROM
RECTIFIER

R32

J5,pin B
+12V,
BOOmA

1.0
2W
Cll
10fLF
35V
6
R23
8.2K

723

R29
470

R2B
100

2
3
R25

R24
2.7K

3.91K
GI2
B20pF
R27

R30
30K
75451

R26
1K
R31
12K

2.71K

J5,pin2
+3

J5, pin 6
11 -4680

Figure 8-31

+12 V Regulator Circuit

The 723 is a precision voltage regulator. It is a 2-1evel regulator, in that it can output two selectable
voltages. Raw dc from the bridge rectifier network enters pins 12 and 11 of the 723. The TU 10W write
driver circuits require + 12 V for NRZ. A high level is presented through J5, pin 2, to the inputs of the
75451, which outputs a high level through R57 by R23 and R24 and lets the full reference voltage from
pin 6 of the 723 enter the noninverting input (pin 5). A + 15 V output is produced.
The output (from pin 10) of the 723 is applied to Q7, where higher current is produced for the output.
The current foldback and sense circuits operate in a manner similar to those of the +5 V regulator.
Output voltage is divided by R25, R26, and R27, and is adjusted by R26. Adjustment R57 is not used
in the TUlOW.
As output current increases, the voltage across R30 and R31 also increases. As the voltage reaches the
limit of the 723, it is sensed at pin 2. The output from the 723 starts reducing, starting to shut off Q7
and keeping the output current from reaching unsafe levels.
No overvoltage protection is provided in the + 12 V power supply section because it is not necessary.
The circuit that this supply feeds can stand voltage higher than this regulator can supply.
8.10.4 + 12 Vde Regulator Circuit (Control Switch Circuits)
The type 723 regulator used in this + 12 V supply operates in exactly the same way as the previous 723
regulator (Figure 8-32).

8-45

D21

+17V
FROM --~-----?---------;--f"

RECTIFIER

R41

J5, PIN 5

1,0

"lr-T---"----?--~W'v-~~------~__<+12V

800mA

C15

lOJ,.lf

R39
56

35V

W3
022

R54

10K

R42

D23
13V

R40
470

C1G

820pF

R37
lK

C18
R55

R38
3,3K

.47,uF
35V

C19
,01,uF

R43

680

' - - - - - + - - - - - + - - - - - - + - - - - + - - - - - - - - - - < > - - , - - < J 5 , PI N 6
10-1320

Figure 8-32

+ 12 V Regulator Circuit

In the + 12 V regulator circuit, resistor R37 is the fine adjustment for the output voltage. Resistors
R41, R39, R40, and R55 offer the sense for the current foldback network. The overvoltage network
acts in the same way as the network in the +5 V supply, except the zener diode (D23) does not conduct
until the voltage across it becomes greater than 15 V. Then the SCR fires and offers a path for output
current, if Q8 becomes shorted for some reason.

8.10.5 -6.4 Vdc Regulator Circuit
The TV 10W power supply also furnishes a regulated -6.4 V (Figure 8-33). The LM304 is intended for
systems requiring regulated negative voltages. Rectified negative voltage is presented to the LM304
from the negative output of the Dll diode bridge.
The LM304 output from pin 7 goes to the base of transistor Q 11. Transistor Q 11, connected with Q 10,
looks and acts like a normal PNP device; the combination supplies high current to the output.
Transistor Q12 is used in the current foldback network. Output current is sensed by R50, the Veb of
Ql1, R49, and R51. As the output increases (becomes more negative), the voltage at the base of Q12
also increases (becomes more negative). Transistor Q12 starts to turn on and, as it does, shunts LM304
output current away from Q l1-Q 12, limiting output current. Then, as the output decreases, Q 12 begins
to shut off and allows the output current to rise again.
The overvoltage protection works identically to the other networks. Zener diode D20 begins conduction at approximately -8.2 V, which fires the SCR (D26) and creates a path to ground if Q10
and/or Qll should short out. Again, the supply must be turned off to allow C22 to discharge before
D26 stops conducting. Diodes D24 and D25 protect the LM304 against any overvoltage surges.

8.10.6 Specifications
Tables 8-4 and 8-5 list the power supply specifications.

8-46

----~~---

~----

-------------

--------~

-14V FROM
RECTIFIER

025
J5, PIN 4
t--1r'VVIr-<p-----<l~_--< - 6.4 V
700MA
R46
27

R47
2.4 K

024
026
R52
27

4
C21
.001

LM304

C20
47p.F
35V

020
8.2V

7
07
.01p.F

8
R44
lK

R49
750
R51
10K

R45
2.74K

R53
680

C22
47p.F
35V
J5, PIN6

11- 4679

Figure 8-33

Table 8-4

-6.4 V Regulator Circuit

Power Supply Input Specifications

Parameter

Specification

Input Voltage
(1 phase, 2 wires, and ground)
Input Frequency
Input Current
Inrush

95-132/190-264 V

8-47

47-63 Hz
7 A nominal at 115 V, 60 Hz
85 A at 115 Vrms, 60 Hz

Table 8-5

Power Supply Output Specifications

Parameter

Specification

+5 V Regulator Circuit
Load Range
Overvoltage Crowbar
Current Foldback at 25° C
Backup Fuse
Adjustment
Regulation

8Amaximum
6.4 V, 10%
3 A nominal
SA
5% minimum
Less than 2%

+ 12 V Regulator Circuit
Load Range
Overvoltage Crowbar
Current Foldback at 25° C
Backup Fuse
Adjustment
Regulation

0.7SA
None
0.5A
lA
35% minimum
Less than 3%

+ 12 V Regulator Circuit
Load Range
Overvoltage Crowbar
Current Foldback at 2So C
Backup Fuse
Adjustment
Regulation

0.75A
15.5 V, 10%
0.75 A to 0.3 A
0.75A
10% minimum
Less than 3%

-6.4 V Regulator Circuit
Load Range
Overvoltage Crowbar
Current Foldback at 2So C
Backup Fuse
Adjustment
Regulation

O.75A
8V
0.75 A to 0.3 A
0.7SA
10% minim urn
Less than 3%

8-48

APPENDIX A
MAGNETIC TAPE FUNDAMENTALS

A.I

MAGNETIC' TAPE FUNDAMENTALS - DEFINITIONS

1. Reference Edge - The edge of the tape as defined by Figure A-I. For tape loaded on a tape
transport, the reference edge is toward the observer.
TAPE
LEADER

"hAi----- SUPPLY
REEL
10-1265

Figure A-I

Reference Edge of Tape

2. BOT (Beginning-of-Tape) Marker - A reflective strip placed on the nonoxide side of the
tape, against the reference edge, 15 ft, ± 1 ft (457 cm, ±30.5 cm) from the beginning of the
tape.
3. EaT (End-of-Tape) Marker - A reflective strip placed on the nonoxide side of the tape,
against the nonreference edge, 25 to 30 ft (762 to 914 cm) from the trailing edge of the tape.
4. 9-Channel Recording - Eight tracks of data plus one track of vertical parity. Figure A-2
shows the relationship between track and bit weight for a 9-channel transport. *

*When the track vs bit channel standard was adopted, the outer tracks were more susceptible to bit dropping
errors. Consequently, channels containing the least Is were assigned the outer locations on the tape.

A-I

BIT
WT

----

RD 0

CONTROLLER
INTERFACE
--CRD7

----

RD 1

--CRD6

TRACK

24 - 3 -

23 - 9 -

----------------------

RD 2

--CRD5

RD 3

--CRD4

RD 4

--CRD3

RD 5

--CRD2

RD 6

--CRDI

RD 7

--CRDQJ

RD P

--CROP

READ AMPS
READ HEAD
11-3091

Figure A-2

Track-Bit Weight Relationship for 9-Channel Transport

5. Tape Character - A bit recorded in each of the nine channels.
6.

Record - A series of consecutive tape characters.

File - An undefined number of records (minimum = zero, no maximum).

Interrecord Gap (IRG) - A length of erased tape used to separate records [0.5 in. (1.27 cm)
minimum for 9-track; maximum IRG is 25 ft (762 cm)].

Extended IRG - A length of erased tape [3 in. (7.62 cm) minimum] optionally used to
separate records.

10.

Tape Speed - The speed at which tape moves past the read/write heads; normally stated in
inches per second.

II. Tape Density - The density of sequential characters on the tape. It is normally specified in
bytes per inch (bpi), which is equivalent to characters per inch.

12. Write Enable Ring - A ring that must be inserted on the supply reel to allow the transport to
write on the particular tape. This safety feature helps prevent accidental destruction of previously recorded data.
13. Tape Mark (TM) - A record written on the tape to designate the end of a file; sometimes

referred to as a file mark (FMK).
A.2 RECORDING METHODS AND DECmagtape FORMATS
The DECmagtape system is an on-line mass storage system for programs or data. Data is recorded on
tape in vertical rows called characters. Each character consists of eight data bits and one vertical parity
bit. The vertical parity bit is program-selected as even or odd. The odd parity bit guarantees that each
character records at least one 1 bit.
The parity bit is generated according to the rule that the number of Is in a character (parity bit
included) is odd or even. For example, if odd parity is used and the character contains an even number
of 1 bits, the parity bit is generated as a 1 bit and an odd number of 1 bits are recorded; then, if an even
number of bits are read back from tape, a vertical parity error is generated to notify the program that
the data is in error.

A-2

The data characters are recorded in blocks of characters termed records (Figure A-3). Each record
contains a specified number of characters determined by the word count.

1-0>-------- FILE ---------+l~1

FILE MARK ~ 23 8

I
I

I
~"---1 'II I
t
Jc r I
I
r-

-APPROX 3 . 8 " I
LRC
I

III

~.~":r'
tH~2~gTER

LAST DATA
CHARACTER
OF PREVIOUS
FILE

0 .6 "-:

FI LE MARK
CHARACTEj
FIRST DATA
CHARACTER
OF NEXT
FILE

A. FILE MARK AND GAP FORMAT

* = 3 CHAR. SPACE

DATA PREVIOUS_
RECORD

i--lRG---ooj.- DATA NEXT
I
RECORD
I--O.6·~
I

1111~*+*1
J r t

LAST DATA
CHARACTER
OF PREVIOUS
RECORD

LRC
CHARACTER
CRC
CHARACTER

B. IRG

IIIII
LFIRST DATA
CHARACTER
OF NEXT
RECORD

FORMAT

* *= 7 CHAR.SPACE
11-3069

Figure A-3

Data Recording Scheme

Records are separated by interrecord gaps (IRGs). The IRG is 0.5 in. (1.27 em) minimum [approximately 0.6 in. (1.5 cm) in normal operation], but may be extended to 3 in. (7.62 cm) by performing an
extended gap operation. Tape IRGs (unrecorded areas) provide areas on the tape for the transport to
start or stop and also separate data records.
A.l.t NRZI Recording Method (non-return-to-zero inverted)
In the NRZI recording method, a 1 bit is represented by a reversal in the direction of tape magnetization on a track; a 0 bit is represented by no change in tape magnetization.

A-3

A.2.2 9-Channel Tape Format
The format (Figure A-4) is composed of from 18* to 2048 nine~bit characters spaced 1/800 in. (3 mm)
apart, followed by 3 character spaces, a CRC character, 3 more spaces and an LRC character. This
unit of data is called a record. At 800 characters per inch, the record is between 1/32 in. (79 mm)
minimum and 5 in. (12.7 cm) maximum. Between each record is a gap of at least 1/2 in.t The tape
structure consists of a number of records followed by a file mark (Figure A-3). Since data is recorded
and read at high speed, IRGs are used to provide space for starting and stopping a tape transport. A
transport accelerates from standstill to full speed in approximately 0.2 in. (0.5 cm) of tape and decelerates from full speed to standstill in 0.2 in. (0.5 cm) of tape; thus, the minimum IRG of 0.5 in. (1.27 cm)
provides adequate space for starting and stopping the tape transport.

/r
REFERENCE EDGE
(FRONT FLANGE
OF REEL)

LRC

0.005" ~ 10% (NOTE 3)

CRC 0.005" ~ 10%

_800 CPI
0.00125" ± 3%

GAP-~IL~---"!---~LOCK

INTERBLOCK
0.50 MIN
(NOTE
2)

WRITE TRACK

0.043" MIN

2048 MAX USASCII CH
18 MIN USASCII CH
LOAD POINT
BEGINING OF
TAPE REFLECTIVE
~~~~~~~~_~STRIP ON
NONOXIDE(SHINY)
SIDE OF TAPE

r---------END
OF
TAPE

~r--I--PARITY (ODD)

BEGINING
OF
TAPE

---------,

END POINT
END OF TAPE
REFLECTIVE
STRIP ON NONOXIDE
(SHINY) SIDE OF
TAPE

TAPE MOTION

1 . . - - - - -

8E - 0500

LEGEND:

NOTES:

BPI
BOT
LRC
CRC

1. Tape is shown with oxide side up. read/write head on same side as
oxide. Tape is shown representing 1 bits in all NRZI recording; 1
bit produced by reversal of flux polarity. tape fully saturated in
each direction.

Tape Bits per Inch
Beginning of Tape
Longitudinal Redundancy Check
Cyclic Redundancy Check

2. Tape to be fully saturated in the erased direction in the interrecord
gap and the initial gap.
3. An LRC bit is written in any track if the longitudinal count in that
track is odd .. Character parity is ignored in the LRC character.
4. CRC - Parity of CRC character is odd if an even number of data
characters are written. and even if a n odd number of characters
are written.

Figure A-4

Tape Recording Format

*USASCH program standards, not a hardware limit.
to.S in. 0.27 em) minimum; 0.6 in. (1.5 em) nominal.

A-4

The CRC character is generated during a write operation and written at the end of a record. The check
character performs the same function to a record as the parity bit does to a character.
The LRC character is the final character in the record and is generated so that for each track the sum
of 1 bits (CRC character included) is even. The LRC character is written on tape by clearing the write
buffer in the tape transport after the CRC character is written. The LRC strobe resets the write buffer,
causing a 1 to be written on each track containing an odd number of Is; a 0 is written on each track
containing an even number of Is.
A.2.3

7-Channel Tape Format

Each character frame in a 7-channel tape (Figure A -5) consists of six character bits (B, A, 8, 4, 2, 1) in
descending order of significance. The parity bit, or check bit (C), is the seventh bit and is set or cleared
by the transport write head. One byte of a data word corresponds to one tape character. However,
because one byte contains eight bits and a tape character contains only six data bits, two bits within
each byte are not used. During a read operation, the extra bits are forced to 0; during a write operation, the bits remain unchanged. During the core dump mode of operation, one byte corresponds to
two tape characters. Thus, all bits within the byte are used; however, the two most significant bits on
the tape are not used.

FORWARD

TAPE
~ MOTION

ONE BYTE DURING
CORE DUMP MODE
rTAPE CHANNELS

{PARITY)C

,....------,

IL.. BOT
TAB
____
_ _ .I

r---

BOT GAP

B
A

1
I

8
4

1
1

DATA
3-CHARACTER
MIN.

3
CHARACTER
PERIODS

~NTERRECOR1GAP
N~x~cgRA~A
(IRG)

o.7-CHANNEL DATA FORMAT

CHARACTER

.1.

LARSETCODRADTA --1-.1+.---- EXTENDED IRG
IN BLOCK

I
------to..........

b. EOF

RECORD

+- -+

EOF
RECORD
3 BLANK
CHARACTER
PERIODS

IRG

BEGINNING
OF NEW
DATA BLOCK

1 \-0391

Figure A-5

7-Channel Tape Format

A-5

The magnetic tape is divided into data records, each record separated by an interrecord gap (IRG). In
a block format, a number of records are written together with an IRG before the first record and after
the last record. In either case, the IRG is an unused portion oftape preceding and following the record
or the block.
The longitudinal redundancy check (LRC) character is written after the data and is separated from the
data by three character spaces. Each bit in the LRC is such that the total number of bits in any specific
channel is even.
The end of a block of records is indicated by an end-of-file mark character. The end-of-file (EOF)
mark is separated from the data by an extended IRG. The extended IRG is a 3-in. strip of blank tape
compared to the standard 3j4-in. IRG for 7-channel tape and the ij2-in. IRG for 9-channel tape. The
EOF mark and associated LRC character are considered to be one complete record.
The 9-channel tape format (Figure A-6) is similar to the 7-channel format; however, because each
character consists of eight data bits and one parity bit, a byte corresponds to a tape character. Therefore, there is no need for a core dump mode, because information can be transferred from the system
to the tape on a one-to-one ratio. In addition, the 9-channel format includes a cyclic redundancy check
(CRC) character. Data is followed by three blank character periods, the CRC character, three more
blank character periods, and the LRC character. The LRC character is followed by an IRG as before.

,..-------.",=r-.:.
rn
9
8
7

5
(PARITY)4

BOT GAP

ONE BYTE

1 I t1 11 l
1 I
1 t1
l
1 tit
1 1 1
til
1
1
1
1
1 1 lit
1 1
1 -,- 1 1 1 1 1
1
1
1 1 1 1
tIl
1 1 1 1
1 1 1 1 1 1 1

-+1

CRC CHARACTER

DATA
3 -CHARACTER
MIN.

-+ +
1

3
CHARACTER
PERIODS

3
t-INTERRECORD+ NEXT
CHARACTER
GAP
DATA
PERIODS
(IRG)
RECORD
11-0392

Figure A-6
A.3

9-Channel Tape Format

CYCLIC REDUNDANCY CHECK (CRC) CH.ARACTERS

The CRC character provides a method of error detection and correction on magtape transports. The
code has nine check bits that form a check character at the end of each record. To perform a com~c
tion, a record in which an error has been detected must be reread into memory with the LRC and CRC
character for program evaluation. Errors involving more than one track can be detected but not
corrected.
The CRe character is generated as follows:
1.

The CRe register is cleared at the beginning of each record. As each data bit is written on
tape, it is exclusively ORed with its corresponding bit in the CRC register.

The CRC register is shifted one position to the right after the exclusive OR operation has
taken place.

A-6

The bits entering CRC 2, CRC 3, CRC 4, and CRC 5 of the CRC register are inverted if the
bit entering CRCP is a 1. Data is shown in Table A-1; the resultant CRC character is shown
in Table A-2.

Table A-I

Five-Character Record
Characters

Data
Character 0

Data
Character 2

Data
Character 3

Data
Character 4

P
0

0
0

}

0
0

1
0
0
0
1
1
1
1
0

0
1
1
1
1
0
0
0
1

Bit

2
3
4
5
6
7

}

1
0
1
1
0
1

}

0
0
1
0
Table A-2

Data
Character 5
}

0
0
}

0
}
}
}

CRC Character in Register When Writing
CRC Register

CRC
Bits

Cleared

CRCP
CRCO
CRC}
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7

0
0
0
0
0
0
0
0
0

Character I Character 2 Character 3 Character 4
0
0
}

0
0
1
0
0
}

0
0
0
0
1
0
0
1
0

0
1
0
0
0
0
1
1
0

1
0
0
0
0
0
1
1
1

Final

CRC
Character
On Tape

1
0
0
1
0
1
0
0
0

0
1
1
1
1
1
1
1
1

Steps 1 - 3 are repeated for each data character of record.

At CRC time, all positions of the CRC register, except CRC2 and CRC4, are complemented
and the resultant CRC character is written on tape.

The CRC register is cleared for the next record.

A-7

A.4 LONGITUDINAL REDUNCANCY CHECK (LRC) CHARACTER
The LRC character is written three spaces after the CRC character. The vertical parity bit is always
written on the LRC character; the vertical parity of LRC is never checked. The LRC character makes
the longitudinal parity even for the entire record, including the CRe. The LRC character is generated
by the LRC register in the following manner:
I.

The LRC register is cleared at the beginning of a record.

As characters are written on tape, corresponding 1 bits complement the LRC register at the
time data is written on tape.

At LRC time, the LRC strobe clears the write buffer and Is are written on tape in only those
channels for which the write buffer is set prior to clearing.

Following this method, the LRC character forces an even number of bits to be recorded on
each track of the tape. The CRC character is included in determining the LRC character.

A.S DATA FILES
As previously stated, a record is a group of characters preceded by an IRG and terminated by three
spaces, a CRC character, three more spaces, and an LRC character. A file is a group of records
separated by IRGs and terminated by a 3 in. (7.62 cm) gap followed by a file mark. The file mark is a
record consisting of a single data character [the end-of-file (EOF) character] followed by seven blank
characters and an LRC character. The CRC character is not written on an EOF record. The LRC
character with a file mark is a duplicate of the EOF character (238).
A.6 TRACK ASSIGNMENTS
The track assignments for read, write, and parity bits are shown in Table A-3.
Table A-3
Transport
Track Number

1 furthest from
transport
2
3
4
5
6
7
8
9 closest to
transport

Track Assignments for Data and Parity
Write
Data Bits*

Read
Data Bits*

Binary
Weight

CWD5

CRD5

CWD7
CWD3
CWDP
CWD2
CWDl
CWDO
CWD6
CWD4

CRD7
CRD3
CRDP
CRD2
CRDl
CRDO
CRD6
CRD4

2°
24

*At controller interface.

A-8

25
26
27
21
23

APPENDIX B
SYSTEM DIAGNOSTICS

B-1

IDENTIFICATION
PRODUCT CODEI

MAINDEC-l1.DZTMA.H.O

PRODUCT TITLEI

TM,A,e-l1/TS01,TU10.N,W INSTRUCTION TEST

PROCR~M

~
I
W

DATEI

AUGUST 1976

MAINTAINERI

DIAGNOSTIC ENGINEERING

AUTHOR:

JOHN PODENHISER

REVISED:

JIM LACEY/JIM KApADIA/B. 8UPGESS/K. LIND/R, BARNES
SAM CARPENTER/R. SOLER
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT
NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIpMENT CORPORATION, DIGITAL EQUIpMENT CORPORATION ASSUMES
NO RESPONSIBILITY FOR ANy ERRORS THAT MAY APPEAR IN THIS DOCUMENT,
THE SOfTWARE PESCRleED IN THIS DOCUMENT IS fURNISHED UNDER A
LICENSE AND MAY ONLY 8E USED OR COPIED IN ACCORDANCE WITH THE
TERMS OF SUCH LICENSE,
DIGITAL EQUIpMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR
THE USE OR RELIABILITY OF ITS SOFTWARE ON EQijIPMENT THAT IS
NOT SUPPLIED BY DIGITAL,
COPYRIGHT

ee) 1971, 1972, 1973, 1975, 1976 BY DIGITAL EQUIPMEN CORPORATION

ABSTRACT
THE TM,A"S-ll INSTRUCTION TEST CONTAINS A SERIES OF BASIC TESTS
THAT CHECK REGISTERS fOR PPOPEP OPEPATION WHILE NOT INVOLVING
TAPE MOTION~ ALL TAPE MOTION FUNCTIONS, DATA TRANSFERS, EXTENDED
MEMORY, AND MANUAL INTERVENTION TESTS OF THE TU10 OR T503 TRANSPORTS m
***MANUAL INTERVENTION TESTS AFE SKIPPED IN C~AIN MODE***

REQUIREMENTS

2.1

EQUIPMENT
PDP-It WITH TM,A,e.l1 CONTROL UNIT AND t TS03,TUt0,N,W TAPE UNIT.

2s2

STORAGE

2,2.1

PROGRAM STORAGE
THE ROUTINE REQUIRES 4K OF MEMORY.

LOADING PROCEDURE

1.1

METHOD
Ai PROCEDURE FOR NORMAL BINARY TAPES SHOULD BE FOLLOWED.
8, PROGRAM IS LOADABLE AND

STARTING PROCEDURE

4,1

CONTROL SWITCH SETTINGS

CH~INA8LE

IN 8K or MEMORY.

STARTING AT LOC. 200 ALL SWITCHES SHOULD BE DOWN OR ZERO.
**.sOFtwARE SWITCH REGISTER Is LOCATED AT LOC. 176 IF NEEDED,***
4.2

STARTING ADDRESS
200

4.3

PROGRAM ANO/OR OPERATOR ACTION
10 LOAD PROGRAM INTO MEMORY,
PLAC~ ONE TAPE U~lT, ON-LINE, AT LOlD POINT (BOT), UNIT 0 SELECTED.
3. LOAD STARTING lDDRESS
4@ START PROGRAM
PROGRAM WILL T¥PE "SET SW0~1 IF 7 CHANNEL".!!F NOT CHAIN MODE)
CHAIN MODE DEFAULT IS DRIVE 0 9TRK ONLy.
IF APPROPRIATE SET SW0 AND THEN PRESS CONtINUE OR
***IF SOFTWARE SWITCH REGISTER IS USED TYPE CNTL G AND THEN CONTINUE
~THIS WILL ALLOW THE MODIFICATION OF THE SOFTWARE SWITCH REGISTER (REfER TO SECT, 5,1)
THE PROGRAM WILL BEGIN TESTING.
Z.

'JI

OPERATING PROCEDURE

5,1

OPERATIONAL SWITCH SETTINGS
IF THE DIAGNOSTIC IS RUN ON A CPU WITHOUT A SWITCH
REGISTER THEN A SOFTWARE SWITCH REGISTER IS USED WHICH ALLOWS
THE USER THE SAME SWITCH OPTIONS AS THE HARDWARE SWITCH REGISTER e
IF THE HARDWARE SWITCH REGISTER DOES NOT EXIST OR IF ONE DOES
AND IT CONTAINS ALL ONES (171177) THEN THE SOFTWARE SWITCH
REGISTER CLOC e 176) IS USED,
CONTROLI
THIS PROGRAM ALSO SUPPORTS THE DyNAMIC LOADING or THE SOFTWARE SWITCH
REGISTER (LOC; 116) FROM THE TTY. THIS CAN BE ACCOMPLISHED BY
DOING THE FOLLOWING:
1) TypE CONTROL G (oG>r THIS WILL ALLOw THE TTY TO ENTER DATA INTO
LOC. 176 AT SELECTED pOINTS WITHIN THE PROG~AM.
2)

TH~ ~ACHINE WILL THEW TYPE: SWR=XXXXXXNEW= (XXXXXX IS THE OCrAL CONTENTS
OF THE SOFTWARE SWITCH REGISTEF m,

~FTER THE '·NEW."
HAS BEEN TYPED THEN THE OPERATOR CAN DO ONE
OF tHE FOLLOWING AT THE TTYI

A) TYPE A NUMBER TO BE LOADED INTO LOC, 176 FOLLOWED BY A <CR>Q

[ONLY NUMBERS BETWEEN 0@7 WILL BE ACCEPTED AND ONLY 6 NUMBERS
WILL BE ALLOWED)

IF A (CR> IS THE FIRST KEY DEPR~SSED THE SOFTWARE SWITCH
REGISTER CONTENTS WILL NOT BE CHANGED,
B) IF A CONTROL U <-U> Is DEPRESSED THEN THE pROGRAM WILL SEND YOU
BACK TO STEP 2.

5@ie!

WITH ALL SWITCHES DOWN THE P~OGRAM WILL PRINT OUT ON ERRORS AND
CONTINUE IN TEST. (END OF PASS WILL PRINT ON EACH PASS)

5,1.2

SWITCH SETTINGS ARE:
SW15 ( UJliJ(00) ::: 1 OF! UP
swt4 (040000) !II 1 OR UP
SW13 (02I1JftH,IIJ) :lII 1 OR UP

UP
::i ~
OR UP
SW10 (002000) ill: 1 OR UP
SW9 ((lJ(H00"') z t OP UP
SW0
( 0011:HHH) :: 1 OR UP
SWO' C0U0011J)
SWtl (0(7l4~00)

5,1.3

HALT ON ERROR
SCOPE
LOOP
" • e
INHIBIT PRINTOUT.
, " INHIBIT SUBeTEST INTERATION.
8, 8
SINGLE PASS
S
INHIBIT MANUAL INTERVENTION TEST
"
FOR
TS~3 TAPE DRIVES
• ••
TEST
7 CHANNEL TAPE UNIT.
"
•

•

·.
..
•

MANUAL INTERVENTION TEST
THIS T~ST WILL REQUIRE THE OPERATOR TO PERFORM CERTAIN OPERATIONS
WITH THE TRANSpORT AS DIRECTED By MESSAGES PRINTED ON THE
TELETYPE.

txJ
o
0\

5.1

SUBROUTINE ABSTRACTS

5@2.1

SCOPE
THIS SUBROUTINE CALL IS PLACED BETWEEN EACH sue.TEST IN THE INSTRUCTION
SECTION. IT RECORDS THE STARTING ADDRESS OF EACH SUB~TEST AS IT IS
BEING ENTERED@ IF A SCOPE LOOP IS REQUESTED, IT WILL JUMp TO THE
START or THE SUB.TrST THAT THE SCOPE LOOp IS FEQUESTING~
*.*CNTL G WILL BE RECOGNIZED IN THIs ROUTINE (Rr-FER TO SECT 5 9 1)

5,2.2

HLT

THIS SUBROUTINE CALL PRINTS THE ADDRESS THAT TAGS THE FAILING
SUBTEST AND tHE CONTENTS OF ALL THE TM,A,Bol1 ~EGISTERSG
***THIS ~OUTINE RECOGNIZES CNTL G FUNCTION (REFER TO SECTa 5.i)

6,0

ERRORS

6,1

ERROR PRINTOUT FORMAT
WITH SW13=0 (OR DOWN) THE FOLLOWING PRINTOUT WILL APPEAR ON AN ERRORI
PC
XXXXXX

STATUS
XXXXXX

pC
•
STATUS
COMANO •
BYTE
•
CA
DATA 8
READ L
TEMp
•
CRC CAL •

•
•

••

~
I

COMANO BYTE
CA
XXXXXX XXXXXX XXXXXX

DATA 8
XXX XXX

READ L
XXXXXX

TEMp
CRC CAL
XXXIXX XXXXXX

ADDRESS OF TEST WHERE ERROR OCCURED
CONTENTS or STATUS REGISTER AT TIME OF ERROR
CONTENTS OF COMMAND REGISTER AT TIME or ERROR
CONTENTS OF BYTE COUNTER AT TIME OF ERROR
CONTENTS OF CURRENT MEMORY ADDRESS AT TIME or ERROR
CONTENTS OF DATA BUFFER AT TIME or ERROR
CONTENTS OF READ LINES AT TIME OF ERROR
CONTENTS or ADDRESS "TEMP" USED BY SOME TESTS
CRC CHARACTER CALCULATED (USEFUL ONLY FOR CRe TEST)

NOTE THAT NOT ALL OF THE INFORMATION PRINTED IS INTENDED TO BE
USEFUL rOR EVERY TypE or ERROR, THIS IS SIMPLY A STANDARD ERROR
REpORT rOR ALL ERRORS, THE OPERATOR MUST REFER TO THE PROGRAM
LISTING AT THE ADDRr.SS or THE ERROR FOR A DESCRIPTION OF THE
CAUSE OF THE ERROR, IT IS THEN uP TO HIM TO DETERMINE WHICH
or THE INFORMATION IS USEFUL.
6.2

ERROR RECOVERY
WITH SW1S=t OR UP THE PROGRAM WILL HALT ON AN [RROP,
CONTINUE SWITCH TO RESTART TEST,

DEPRESS

RESTRICTIONS

7.1

STARTING RESTRICTION
BEFOpE STARTING PROGRAM THE OPERATOR MUST MAKE CERTAIN THAT THE
TRANSPORT HAS DRIVE 0 SELECTED "ON.LINE".

7,2

OPERATIONAw RESTRICTIONS
MANUAL INTERVENTION TEST MUST BE PERFORMED ON EACH PASS THRU
THE PROGRAM UNLESS INHIBITED WITH swt0-1 (OR UP).
IF UNIT IS A TS0) SW9 MUST BE 1 (OR UP),

8,0

MlSCEw~ANEOUS

8,1

EXECUTION TIME

WITH MANUAL INTERVENTION TEST INHIBITED IT TAKES 1 MINUTE
FOR ONE pASS THRU PROGRAM. MANUAL INTERVENTION TEST IS
OPERATOR DEPENDENT BUT SHOULD TAKE APPROXIMATELY 2 MINUTES.
9.0

PROGRAM DESCRIPTION

10.0

LISTING

IDENTIFICATION
PRODUCT CODEi

MAINDEC-l1-DZTMH-g-O

PRODUCT TITLEI

TM,A,a-ll MULTIDRIVE DATA RELIABILITY EXERCISER

DATE CREATEP,

FEB 1977
DIAGNOSTIC GROUP

AUTHORI

R. R. BARNES/RON PLATUKIS/R. SOLER

T~f. INFOP~ATtON IN THIS DnCUMENT IS SUBJECT TO CHANGE WITHOUT
NDTICE AN~ SHOULD MOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION. ~IGITAL EQUIPMENT CORPORATION ASSUMES
NO RF.SPONSIBILITY FnR ANY EPRORS THAT MAY APPEAR IN THIS DOCUMENT
T~f snFTWARF DESCPIBED IN THIS DOCUMENT IS FURNISHED
tIC~NSE AND MAY ONLY BE USED OR COPIED IN ACCQRDANCE

UNDER A
WITH THE

TF.PMS OF SUCH LICENSE,
OTGITAL EQUIPMENT CORPORATION ASSUMES ND RESPONSIBILITY FOR
T~E USE OR RELIABILITY OF ITS SOFTWARE ON EQUIPMENT THAT IS
NOT ~UPPLIED BY DIGITAL.
COPYRIGHT ec) IQ75, 1977 BY DIGITAL EQUIPMENT CORPORATION

B-9

TA8LF. OF CONTENTS
PAR~GRAP'"

SUBJECT

~BSTRACT

REQUIREMENTS
LOADING PROCEDURF
STARTING PROCEnURE
DATA PATTERNS
RANDOMIZATION
nYNAMIC PARAMETEP
CO~SOLF. SWITCHr.S
FRROR PRINTOUT
~TATISTIC PRINTOUT
AUTO SEQUENCE
Tf.STING PROCEDURES
I·ISTING

4
5
6
7
p

9
10

11
12
13

B-lO

PAGF
1
1
1

2
7
8
9

10
14

22
24

(P~GE

~8S"RACT

THIS PROGRAM IS DESTGNED TO BE USED BY AN EXPERIENCED ENGINEER
ITrCHNICIAN FOR EVALUATION AND DEBUGGING OF MAG TAPE DRIVES.
THE PROGRAM IS CAPABLE OF EXERCISING ANY TAPE DRIVE THAT CAN
BE OPFR'T~D ON ~ UNIBUS PDP-11 SYSTEM THROUGH THE TM,A,B-l1 MAG
TAPE CONTROLLER. ANY TYPE OF TAPE ORIVE, 7 OR 9 TRACK MAY BE USED.
ANY NUMBER OF DRIVES, SINGLE OR MULTIDRYVE SYSTEMS, UP TO EIGHT
(B). MAY BE TESTED BY A SINGLE EXECUTION OF THE PROGRAM. THIS
FLF-XIBILITY IS P08STBLE 8ECAUSE THE PROGRAM HAS NO FIXED PARAMETERS
OR TESTIN~ SEQUENCE. THE ENTIRE TEST PLAN, INCLUDING PARAMETERS
A~D OPFRATING SEQUENCE, IS DETERMINED BY THE OPERATOR THRnUGH
RFSPDNSES T~ TFLETYPE REQUESTS AND SETTING OF CONSOLE SWITCHES.
THE PROGRAM PRovlnES FOR TESTING OF ALL TAPE DRlVE FUNCTIONS
SUCH AS wp.nniG, REFInING, REWINDING. TAPE POSITIONING, EDT - BOT
SENSING AND ASSUMES A GOOD CO~TROLLER.
HOWEVER, THE CQNTROLLER IS TESTEO SOMEWHAT INTRINSICALLY
DU?!NG TH~ TEST CYCLE IN ORDER TO PROVIDE FULL INFORMATION
A80UT ANY EPROp CONDITIONS DETECTED.
DIlRIr.rG A TEST cycr,!,;, CflECKS ARE MADE FOR STATUS ERRORS, DATA ERRORS,
POSITION ~RR(1RS,WORD COUNT AND CURRENT MEMORY ADDRESS ERRnRS
WH'RrV!~

RPQUIRE~E~TS

A.
B.
C.
O.
E.
3.

APPLICAB~E.

(HARDWARE)

A~Y PDP-tt PROCERSER
AK OF COPE
TELETYPE
TM,A,B-l1 TAPE CONTROL UNIT
1 TO 9 TS03 OR TH10,N,W Io4AG TAPE DRIVES

LOAnING PROCEDURE
---....••..... _A. liSE STANDARD PROCEDURE FOR LOADING BINARY TAPES
B. PROGRAM. IS LOADA~LE AND CHAINABLE IN 8K OF MEMORY.
DEFAULT CHAIN MODE IS A SINGLE PASS ON DRIVE 0
AT 9TRK.800 BPI,lOO RECORDS OF 200 CHARACTES EACH,
W1TH PATTERN ONE AND ALL SWITCHES D.

B-ll

(PAr.~

STlIR'J'lNr; PROCEDURE
THER~

APE rOUF (4)

2no(~),

204(8),

STl\RTI~G

210(~),

A~n

ADDRESSES THAT MAY BE USED,
240(8):

A. ?OO(R)I

THIS ADDRESS ~UST AE USED ON INITIAL START FROM
tOAD AS ALL PARAMETERS AR~ ENTERED FRnM HERE.
RI"QllE:STS ARE PRINTFD ON THE TrLF-TYPE FOR ENTRY OF'
cnNTROLLER REGISTFR STARTING ADDRESS, VECTOR ADDRESS,
UNIT NUMAER, DENSITY,PAPITY,RECORD COUNT,CHARACTER
cnUNT,PATTERN NUMBER, TAPE MARK (EOF) OPTION,AND STALL
F~g READ, WRITE, AND TURNaROUND.
ALL REPONSES SHOULD
BE MADE IN OCTAL AND WITHIN THE LIMITS OF THE PARAMETER.
A QUESTTON MARK (?l WILL AE TYPED IF ANY
CHARACTER ENTEREn IS NOT BETWEEN 0 TARU 7 (OCTAL).
THE CHARACTER M~Y BF RETYPED FOLLOWING THE QUESTION
MARK.
IF' THE RESPONSE IS NOT WITHIN ITS LIMITS. A
QUESTION MARK (?) IS TYPED AND THE ENTIRE RESPONSF
MAY AE RENTERED. SOME RFSPONSES REQUIRE MORE TH~N ONE
(1) C~AR~CTER, BUT NONE REQUIRES MORE THAN SIX (6).
RfS P OMSE5 NErD NOT ~AVE
L~AnING ZEROS AND SHOULD ~E TERMINATED BY A CARRIAGE
RETURN IF' L~SS THAN THE MAXIMUM NUM~EP Of CHARACT!RS
IS INPUT.

B. ?04(R):

THIS ADDRfSS SHOULD BE USED ANYTIME A RESTART
OF THf. PR0GRAw IS NECESSARY AND THE PAPAMETF.RS
[NT~RED ~T THE INITIAL START OF 200(8) NEEP NOT
BE CHANGED. ALSO NOTf THAT ANY DATA PATTERN WHICH
HAD BFF.N GENERATED BY SETTING THE RANDOM DATA
BAITeN (C0NSOLE SWITCH EIGHT) WILL NOT BE OVERWRITTEN
AND TMERFORF IS HELD IN CORE FOR USE UNTIL
cnNSOLE SWITCH EIGHT(8) IS AGAIN SET.

?tonn:

THIS ADDRESS IS THE SAwE AS USING 204(8) IN THAT THE
PRFVIOUSLY SET PARA~ETERS ARE USED: HOWEVER, THE DATA
PATTERN IS RETURNED TO THE FIXED PATTERN ORTGTNALLY
('ALLED FOR AT THE 200(8) ·START. ALSO ALL STATISTICS
PREVIOUSLY GATHFRED WTLL BE CLEARED,

D. 240CR):

THIS IS A SPECIAL ADDRESS WHICH WILL CAUSE THE
PROGRA~ TO EXECUTE A PRF.DETERMINED TEST PLAN ON
At.L AVULABLE UNITS. THE ONLY INPUT REQUIRED
RY THE OPER~TOP. IS A RESPONSE TO RFQUESTS FOR THE
CQNTROLLER AnnpESS, VECTOP ADDRESS, AND CDNTINU0US
OPFPATI0N OF THE SEQUFNCE.
S~F

TTgw 1"

(P4GB 72) FOR FULL DETAILS.

B-12

(PAGE 3)
THE FOLLOWING IS AN EXPLANATION OF THE INITIAL
START (2no OCTAL) REQUESTS AND RESPONSES a
PEGISTER START, THF. RESPO~SE REQUIRED FOR THIS REQUEST IS TO
INTER THE ADDRESS OF THE FIRST CONTROLLER REGISTER
(MTS) AS A SIX DIGIT UNIBUS AOORESS.
V~CTOR

ADDRESS I

(PitT NUMFlEfI:

DENSITY:

R~SPONSE FOR THIS REQUEST IS TO ENTER THE
I"TERRUPT VECTOR ADDR~SS USED BY THE CONTROLLER
AS A THREE (3) DIGIT ADDRESS.

T~E

THE UNIT NUMBER IS ENTERED AS ONE (1) OCTAL
CHARACTER AND MUST BE WITHIN THE LIMITS or 0
THROU~H 7.
WHEN THE UNIT NUMAER HAS BEEN ENTERED
AND IS LEGAL, THE PROGRAM TESTS FOR THE PRESENCE
OF A UNIT OF THAT NUMBER. IF THE UNIT IS
~vAILA5LE A PRINTOUT OF 7 CHANNEL OR 9 tHANNEL
WILL BE MADE TO ASSIST THE OPERATOR IN SETTING
DENSITY AND PARITY. IF THE UNIT IS NOT AVAILABLE,
A MESSAGE STATING SO WILL BE PRINTED AND A NEW
UNIT NUMBER REQUEST WILL FIE ISSUED. WHEN A
Gnon UNIT NUMBER HAS BEEN ENT~RED, REQUESTS FOR
OPERATING PENSITY AND PARITY ARE MADE fOR
THAT UNIT AND SHOUT,!,) BE RESPONDP:D Tn ACCORDING
TO THAT P~RTICULAR UNIT"S NEEDS. AS MANY AS
EIGHT (8) UNIT NUMBgR REQUESTS MAY BE USED,
~GWrVER, AT LEAST ONE MUST BE USED.
THr. UNIT
NUMFP;~ AND THEIR RESPECTIVE DENSITY AND PARITY
MAY BE ENTERED IN ANY ORDER. THE INFORMATION
rnR EACH UNIT ENTERE~ IS LOADED INTO A TABLE
FOR RErF.PENCE IN TESTtNG. IF LESS THAN ETGHT(8)
UNITS ARE REQUIRED, THEN RESPONDING TO THE
U~IT NUMAER REQUEST WITH A CARRIAGE RETURN WILL
TERMIN~TF. THF. UNIT ENTRIES AND COt-lTIN!JE
T~ THE NEXT PARAMETER.
IT SHOULD BE REMEMBERED
THAT ~T LEAST ONE UNIT NUMBER REQUEST MUST BE
ENTERED. IF THE FIRST REQUEST IS RESPONDF.D
TO BY A CARRIAGE RETURN, THEN THE REQUEST
WILL BE REPEATED.
THE DENSITY REQUEST IS RESPONDED TO BY ONE (1) OCTAL
AND MUST AE WITHIN THE LIMITS OF 0 THRU 3.
AS EACH UNIT NUMBER IS ENTERED, A REQUEST FOR THE
OPERATING DF.NStTY FOR THAT UNIT IS TYPED. THE
RESPONSE ME~NINGS ARE AS FOLLOWING a

C~APACTF.R

A. 0 = 200BPI,
A. 1 = 556BPI,
C. 2 = B008PI,
n.. 3 = ROOBPI,

B-13

7 CHANNEL NRZ1
7 CHANNEL NRZI
7 CHANNEL NPZI
9 CH~NNEL NRZI

(PAGE 4)
THE

Pll.lHTYr

PARITY PEQUEST IS RESPONDED TO BY ONE (1)
CHARACTER AND ~UST RE EITHER 0 OR 1.

OCT~L

A. 1 = EVEN PARITY
B. 0
ODD PARITY

RECORq COUN'T':

CHkpACTEP

COU~T:

THIS PEQUEST IS P~SPONDED TO BY A SIX (6) CHARACTER
OCTAL NUM8ER FROM 1 TO 177777. REMEMBER LEADING
ZEpns ARE NOT REQUIRED AND IF LESS THAN SIX
CHARACT~RS ARE ENTEREO, A CARPIAGF. RETURN
loJTT~T., TFRMINATE THE RESPONSE.
THE RECORD com/T
IS U5FD I~ CONJUCTIO~ ~ITH THE CHARACTER COUNT
TO ~STA8LrsH A 8LOC~TNG FACTOR FOR USE IN pEAD OR
WPITE CYCr,ES.
THIS RESPONSE IS ENTFRED AS rOUR (4) OCTAL
CHARACTEPS wITHIN THE LIMITS OF 4 THRU 4UOO. AGAIN
LEADING Z~Rns ARE NOT REQUIRED AND A CARRIAGE
RETUR~ TERMINATES A LESS THAN rOUR (4) CHARACTER
PfSPONSF.. THF: CHARA(;TEP COllNT IN CONJUNCTIrlN
WlTH THE RECORD COUNT IS USED TO ESTABLISH
THF. ALaCK SIZE (CHARACT~RS PER RECORD, AND
PfC8PDS P~R BLOCK) USED TN READ AND WRITE CYCLES
THE S~M~ BLOCKING IS USED ON ALL AVAILABLE UNITS.

PATTERN NUMBER: THIS RESPONSE IS A TWO (2) CHARACTER OCTAL
NUMA!P WITHIN THE LIMITS OF 0 THRU 20(8).
THE NUMRER ENTERED WILL CAUSE A SPECIFIC DATA
PA'!'TERM TO BE USED FOP ALT. READING AND WRITING. THIS
DATA PATTERN IS NOT CHANGED UNLESS RANDOM DhTA
IA R~QUESTrD BY SETTING CONSOLE SWITCH EIGHT (8)
Tn A ONE. RESETTING OF THE RANDOM DATA SwITCH
nOES NOT CAUSE REVERSION TO THE FIXED PATTEPN,
RUT WILL HOLD THE LAST GENERATED PATTERN UNTIL
A RfSTART IS DON~ FROM LOCATIO~ 210(8) OR 200(9).
T"E SFLECTlnN OF DATA PATTERN ZERO (0) HAS A
SPECIAL USE. PATTERN NU1>\P,EP ZERO (0) WILL
CAUSE TO BE PEAD IN AT THE HIGH SPEED PAPER
T~PF READER ANY DATA PATTERN DESIRED.
TH!': FXTERNAT, INPUT DAT" TH01lGH THE READER
IS nONE BY PREPARI~G A PAPER TAPE WITH A PROGRAM
CALl,E') 11TC. ("'ATNDEC-U-DZTUf) ANY CONFIGURATION
OF BITS AND CHARACTERS MAY BE USED AND A LIMIT
OF 377(8) CHARATERS IS IMPOSED.
wH~N EXTERNAL
l)AT~ IS J'JPtTT, THE ENTIPE WRITE !'UFFER IN
CnRF IS FTLLED WITH THF PATTERN SO THAT ANY
SIZE RECORD MAY BE USED. DATA PATTERN
ZFRn (0) ~XTERNAL PAP~R TAPE NEED ONLY
BE R~Ary ONCE AT INITIAL START OF 700(8), AND
N~EI" 1Il0T BE RE:AD AG"IN UNLESS OVEPwRITTEN !'y
R~NDnM nATA. ~E SURF TO LnAD THE READE~
AFFOPF PP~SSTNG START.
SEE ITEM 5, (PAGF 7) FOR A DESCRIPTION OF THf

n1\ T" P 1\ T n~ RillS.

B-14

(PAGE 5)
TAPF, MARK:

THE TAPE MARK RF,QUEST I~ USED TO DETERMINE IF
THE OPERATOR WISHES TO HAVE EACH DATA BLOCK
SEPARATED BY A TAPE MARK (OFTEN CALLED Eor rOR
END OF rILF,). IF RESPONDED .TO BY A ONECI) THE
TAPE MARK WILL BE WRITTEN AND WHEN READING WILL
BE ~XPECTED AT THE END OF EACH DATA BLOCK. A
ZER~(O) RfSPONSE WILL 01SALLOW TH~ TAPE MARK
OPTION. PLF.ASE NOTE THAT THE TAPE MARK RECORD
INCREASES THE BLOCK SIZE BY ONE(I) RECORD,
IN OTHER WORDS, A BLOCK or 100 RECORDS WILL
HAVE THE TAPE MARK AS RECORD 101.

SINGIJE PASS:

IF RESPONDED TO WITH A ONE, THE PROGRAM WILL HALT
AND PRINT AN END or PASS MESSAGE WHEN THE LAST
AVAILABLE UN1T RE~CHES F.ND OF TAPE AND IS REWOUND.

STALLS:

THE STALL RF.QUESTS ARE RESPONDED TO BY A SIX (6)
CHAFACTER OCTAL NUMBER" WITHIN THE LIMrTS OF 1
THRU 177777. LEADING ZEROS ARE NOT REQUIRED AND
AN ENTRY OF LESS THAN SIX (6) CHARACTERS SHOULD
BF. T~RMrNAT~D BY ~ CARRIAGE RETURN. EACH INCREMENT
OF THF. VALUE ADDS ABOUT 2.6 MICSEC TO THE DELAY.
READ:
THE TIME DELAY BETWEEN EACH RECORD READ
wRITE: THE TIME DELAY BETWEEN EACH RECORD WRITTEN
TURN AROUND: TIME DELAY BETWEEN CHANGES OF
TAPE DIRECTION (FORWARD,Tn REVERSE,ETC.>
AND BF.TWE~N BLOCKS.

FIXED

IT SHOULD BE NOTED T~AT ALL PARAMETERS EXCEPT
r"R THE UNIT DESCRIPTION VALUES (UNIT
NUMBER, OENSITY, AND PARITY) HAVE NOMINAL
V~tU~s ALREADY STORED IN THE PROGRAM.
AS ~ACH PARAMETFR REQUEST (PATTERN NUMBER, RECORD
COUNT, CHARACTER COUNT, ANO STALLS) IS TYPED.
rTS PRESENT STORED VALUE IS ALSO P~INTED.
IF THESF VALU~S NEED NOT BE CHANGED, SIMPLY
TYPE ~ CARRIAGE RETURN AS RESPONSE AND NO
CHANGE WILL BF MAOE. EACH START nr THE PROGRAM
AT 200(9) WILL SHOW THE CUPRENT VALUES OF THESE
P~R~M~TF.RS ~S PEP THE LAST ENTRY.
WHEN A
FRESH LOAD or THE PAPER TAPE IS DnNE. THE
PARAM~TERS WILL REFLECT THE FIXED VALUES STORED
IN THE PROGRAM.

PARAM~TERS:

A. PECORD COUNT E 100
CYAR~CTER COUNT = 200
C. PATTERN NUMBER E 1
D. READ STALt = 1
E. NRITE = 1
F. TlIRN APOUND = 1
B.

B-15

(PlIGF 6)
SAMPL~

START AT 2nO(8):
THE FOLLOWING JS A SA~PLE OF THE
PR PITEO RFQITF STS AND THFI R PESPOf-j SES.
RESPONSES ARE ENCLOSED IN PlIRENS FOR
CLARITY ONLY AND (CR) MEANS CARRIAGE RETURN

LOAD

AD~RESS

200(8), SET CONSOLF. SWITCHF.S, PRESS START SWITCH:

TM,A,S-11:TS03 OR TU10,N,W MULTIDRIVE DATA RELIABILTY EXERCISER
ENTER CONDITIONS IN OCTAL
RFGISTER START = 172520 (CR)
VECTOR ADDRESS = 224 (CR)
UNIT NU~BER=(5) 9 TR~
DF'NSITY=(J)
PAPITY=(O)
UNIT NUMBER=(2) 7 TRK
DF:NSTTY=(2)
PI\RTTY=(t)
UNIT NUMBER=CCR)
PFCORO COUNT=100 (5nO)(CR)
CHARACTER COUNT=201 (38)?(7)(CR)
PA rTERN NUMBER= 1 (22)
?

(")(CR)
TlIPE ~ARK = 0 (I)(CP)
SINGLE PASS = O(CR)
ENnp snf,LS

READ=l (CR)
WPITE=I. eCR)
TURN AROUND=1 (3nnp)CCR)

THE pROGRAM WILL NOW PERfORM THE TEST CYCLE SET IN
THE CONSOLE SWITCHES ON UNIT FIVE (5) THEN TWO (2),
ONE BLOCK ON FACH UNIT PEP CYCLE, USING DATA PATTERN
NUMR!R SIX (6) ~ITH A BLOCKING FACTOR OF 37 CHARACTERS
PER RECORD AND 500 RECORDS PER BLOCK. THE DELAYS ARE SET
FOP "1'(NIMIIM 0') PDf') r.~1D WRIT!';, AND Al>PROXJMlITELY .15
SFC:OI~r)S ON TITRN APOTlNl'l.

B-16

C PAGE 7)

DATA PATTERNS
THERE APE TWENTY DATA PATTERN G~NERATORS STORED IN CORE
AND ANY ONE OF THESE MAY BE SELECTED. THE ONE UNIQUE
C~SE IS PATTERN ZEpncn), SELECTION nr PATTERN ZEROeD)
REQUIRES THAT A PREVIOUSLY PREPARED PAPER TAPE BE
ENTERED AT THE HIGH SPEED READER. THIS TAPE CONTAINS
A DATA PATTERN OF NO MORE THAN 377 OCTAL
C~APACTERS.
THE FIRST CHARACTER READ IN IS THE
NUMBER or ACTUAL DATA CHARACTERS THAT ARE CONTAINED
ON THE TAPE, EACH DATA CHARACTER MAY BF ANY
COMBINATION OF BITS AND WILL BE LOADED INTO CORE
AS THEY APPEAR ON THE TAPE. NO MATTER HOW MANY
CHARACTERS ARE ON TAPE, THE ENTIRE wRITE BUFFER (2000 CHARACTERS)
WILL BE FILLED WITH THE PATTERN ENTERED SO THAT ANY
SIZE RECORD CAN BE USED.
THE FOLLOWING IS A LIST OF THE DATA PATTERNS
DATAO:
DATA I:
OATA2:
DATII3:
n,~T~4 :
OA'1'A51
DATA6:
DATA;:
OATAI0:
DA1'II1.1:
OATA12:
DATA13:
nAn14:
DAT.a,5:
DATI\161
DATAI;1
DATA20:

_VAILA~LEi

EXTERNAL INPUT THRU HIGH SPEED RFADER (SEE DTCI MAINOEC-l1-0ZTUr-A)
ALL ONE BITS IN ALL CHARACTERS
ALL ZERO 8ITS 1M ALL CHARACTERS
A O~E BIT WALKING FROM RIGHT TO LEFT IN A FIELD OF ZEROS
A Z!RO BIT WALKING FROM RIGHT TO LEFT IN A FIELD OF ONES.
ALT!RNATING ONE AND ZERO BITS IN EACH CHARACTER
ALTERNATING ZERO AND ONE BITS IN EACH CHARACTER
SAME AS DATAS BUT WITH EVERY OTHER CHARACTER COMPLEMENTED
SAME AS DATA6 BUT WITH EVERY OTHER CHARACTER COMPLEMENTED
rNCRE~ENTJNG CHARACTERS (000-3;7)
DrCRFMENTING CHARACTERS (377-000)
ALTERNATING CHARACTERS OF ALL ZERO AND ALL ONE BITS
ALTERNATING CHARACTERS Of ALL ONE AND ALL ZERO BITS
SPErlAL PATTERN OF A WALKING ZERO BIT REPEATED 4 TIMES
IBM COMPAT PATTERN 1: RIPPLE
IBM CO~PAT PATTERN 21 FIXED (ABeDEF)
IBM COMPAT PATTERN 3: FIXED (J)

B-17

(PAGE Bl

THERE ARE THREE (3) VALUES THAT MAY BE GENERATED RANDOMLY,
DATA, CHARACTER COUNT, AND RECORD COUNT, THESE ARE NORMALLY SET TO
SOM~ FIXED VALUE BUT MAY BE RANDOMIZED RY SETTING THE APPROPRIATE
CONSOLF SWITCHES.
A.

RANDOM

(CONSOLE SWITCH 81
AN ENTIRE BUFFER, CHARACTER BY
CHARACTER. OF RANDOM DATA WHEN SWITCH 8
IS SET TO ~ ONE. ONCE SET, THE RESETTING OF
SWITCH R CAUSES THE LAST GENERATED PATTERN
TO BE RETAINED IN CORE. A RESTART AT LOCATION
200(R) OR 210(R) WILL CAUSE REVERSION OF THE
DATA TO THE FIXED PATTERN REQUESTED INITIALLY.
A RESTART AT LOCATION 204(9) WILL HOLD
THE LAST GENERATED PATTER~ IN CORE UNTIL SWITCH
8 IS AGAIN SET.
ALTHOUGH THE DATA IS GENERATED AS RANDOM,
THE PROGRESSION OF RANDOM CHARACTERS IS ALWAYS
THE SAME FROM THE OUTSET OF RANDOMIZATION,
TKEPF-rORE IT IS POSSJALE TO GENERATE aNt TAPE REEL
O. RANDOM DATA ON ONE UNIT, RESTART T~E
PROGRAM TO RE-ESTABLISH THE OUTSET POINT, AND
READ THE RANDOM TAPE REEL ON ANOTHER UNIT FOR
COMPATABILITY TESTING, IN MULTIDRIVE SYSTEMS TME SAME
BLOCK 0F DATA. WHETHER RANDOM OR FIXED, IS
WRITTEN OR READ O~ EACH AVAILAALE UNIT IN THE
ORDFR T~AT THEY W~RE ENTFRED, BEFORE AEING CHANGED.
DAT~:

GF.N~R~TES

RANDOM CHAPACTER COUNTI (CONSOLE SWITCH 7)
GENERATES A DIFFERENT NUMBER OF CHARACTERS
PER REcnpD TO BE WRITTEN ON EACH BLOCK CYCLE.
TME S~ME NUMBER OF CHARACTERS PER RECORD IS
~!R!TTFN OR PEIID ON EACH AVA ILABT,P; UNIT BEFORE
8EIN~ CHANGE~.
RESETTING SWITCH 7 HOLDS THE
LAST VALUE GENERATED.

P.NDOM PECORD COUNT: (CONSOLt SWITCH 6)
A DIFFERF;NT Nl!MBER OF RECORDS
Fn~ EACH ALnCK OF D~TA WRITTEN OR READ ON
EACH BV1CK CYCLF:. THI': S;'ME NlT"'BER OF RECORDS
IS WRrTTE~1 OR READ ON EACH AVAI!.~RLE UNIT AEFORE
I3RCNG CHl\NG8D, RESET'rPI!; SWITCH 6 Bor,DS T,(\ST VALUE
G~Nl':PA'l'En •
GE~IERAn~S

(PJl.GE 9)
7.

DYN~MrC

PARJl.METERSI

THE THREE (3) STJl.LL VJl.LUES ARE CONSIDERED TO BE DYNAMIC
PARAMP:TERS AS T~EY MAY FIE CHANGED WHIL.E THE PROGRAM IS
RUNNING BY TYPING II CONTROL C CHARACTER AT THE TELETYPE.
AS SOON AS THE BUS IS RELEASED BY THE MAG TAPE OPERATION
IN PROGRESS, THE PROGRAM WILL RESPOND TO THE CONTROL C INPUT
8V TYPING II REQUEST rOR NEW STALL PAR~METERS.
THE LAST VALUES
THAT WERE ENTERED WILL BE PRINTED AS THE STORED VALUES AND MAY
FIE CH~NGED BY ENTERING ~EW VALUES OR LEFT UNCHANGED BY
TYPIN~ II CARRIAGE RETURN.

***********************************************************************************
8.

THIS PROGRAM HAS BEEN MODIFIED TO RUN ON A PROCESSI1R WITH OR WITHOUT
A HARDwARF SWITCH REGISTER. WHEN FIPST EXECUTED THE PROGRAM TESTS
THE EXISTENCE or A HARDWARE SWITCH Rf.GISTER, IF NOT FOUND A
sorTWARE SWITCH REGISTER LOCATION (SWREG=LOC. 176 ) IS DEFAULTED TO.
fr TRIS IS THE CASE. UPON EXECUTION THE CO~TENTS OF THE SWREG ARE
DI1MPED IN OCTAL ON THE CONSOLE TTY AND ANY CHANGES ARE REQUESTED
(IE)

POSSIBLE

PESPO~SFS

SWR=XXXXXX

N~W=

ARE:

1•

CCR>

(; DIGTTS 0-7

CLF'>

IF NO CHANGFS ARE TO BE MADE
TO REPRESENT TN OCTAL THE NEW SWITCH REGISTER
VALUE ,LAST DIGIT FOLLOWED BY CCR>.
TO ALLOW REF,NTERING VALUE IF ERROR IS COMMITTED
KEYING IN SWREG VALUE.
ONLY VALID FOR ACT-l1 SYSTEMS-DO NOT USE

BIIILT INTO THE PROGRAM IS THE ABILITY TO DYNAMICALLY CHANGE THE
CONTENTS OF SWREG DUPING PROGRAM EXECUTION, BY STRIKING -G
(CNTL G) ON CONSOLE TTY THE OPERATOR SETS A REQUEST FLAG TO CHANGE
T~E CONTENTS OF SWR~G. WHICH IS PROCESSED IN KEY AREAS OF THE PROGRAM
CODE (IE) ERROR POUTINES, AFTER HALTS END or PASS, AND OTHER
APPLICABLE AREAS.

B-19

(PAC:F: 10)
9.1

CONSOLE SWITCH SETTINGS
THE CONSOLE SWITCHES ARE USED TO SET UP THE TEST CYCLE
DESIRED, Tn GENERATE RANDn~ VALUES, AND TO CONTROL ERROR
RESPONSES. THE SWITCHES SHOULD BE SET TN THE DESIRED
MAN~gR BEfORE PRESSTNG THE START SWITCH BECAUSE THEY
ARE ALL DYNAMIC AND WILL RUN THE PROGRAM IN ANY
CONF'TGUPATtrJN. ALT, SWITCHES SFT TO ZEFH)(O) IS NORMAL.
t =5'1'01' ON ERR.OR
O=CONTINUE ON ERROR

SW14:

I=YOZZLE ON CURRENT BLOCK
~OT YOZZLE ON SLOCK

O=D~

SWDI

1=00 NOT C~ECK DATA ERRORS
O=CHECK DATA ERRORS

SW12:

,.nn NOT CHECK WRITE STATUS ERRORS
O=CHECK WP!TE STATUS ERRORS

SW11:

1=00 NOT CHECK READ STATUS ERRORS
O=C~ECK FEAO STATUS ERRQRS

gWiO:

l=DO ~OT PRINT ANY ERRORS
O=PRP'T AT,IJ ERRORS

SWQ:

l=REWTNn ALL AVAILABLE TAPES
O=DO ~"n REWI>.iD

SWRt

i=GENERATE PA~DOM DATA
O=USED FrXEn nATA

SW7:

l=GENERATE RANDOM CHARACTER COUNT
neUSE FIXED CHARACTER COUNT

5W6:

l=GEN[RATF ~ANDOM RECORD COUNT
FIXED RECORD COUNT

O=US~O

51015:

I=YOZZLE ON CURRENT RECORD
~OT YDZZL! ON RECORD

0=00

SW4:

1=PRI~T STATISTICS
~OT PRTNT RTATtSTJCS

0=00
5W31

1=00 NOT
O=READ

SW2:

NOT URED

5Wl1

PE~D

t=OISASLE WRITE AND READ RETRY OPTION
WRITE AND READ R!TRY OPTION

O=ENA~LE

SWOt

I=DO 'OT WRITE
O=wRIT~

B-20

(PAGE 1t)
SWITCH EXPLANATION AND EXAMPLES,
swo.SW],

THESE SWITCHES ARE USED TO CONTROL THE SEQUENCE
OF MAG TAPE OPERATIONS PREFORMED ON EACH AVAILABLE
UNIT. THE BLOCK OF DATA DESCRIBED THROUGH
THE RESPONSES TO TELETYPE REQUESTS AT INITIAL START
WILL BE EITHER WRITTEN OR READ FROM EACH AVAILABLE
UNIT IN THE ORDER THAT THEY WF.RE ENTERED. THE SEQUENCE
OF OPEPATIONS IS CALLED A CYCLE, AND WILL BE PERFORMED
CONTINUOUSLY UNTIL STOPPED BY THE OPERATOR. WHEN END
O' TAPE IS REACHED, THE UNIT WILL BE REWOUND AND
FLAGGED AS UNAVAILABLE FOR TEST UNTIL ALL UNITS HAVE
REACHED EDT, AT WHICH TIME TESTING IS RESUMED ON ALL
AVAILABLE UNITS.
EXA~PLESI

A.
B.
C.
SW1:

SWO+SW3
SWO~0,SW3=1

SWO=1,SW3=O
SWO~0,SW3z0

WRITE ONLY X RECORDS OF Y CHARACTERS
READ ONLY X RECORDS OF Y CHARACTERS
WRITE THEN BACKSPACE AND READ X RECORDS

SWITCH ONE(l), WHEN SET TO A ZERO (0), WILL
CAUSE ANY DATA RELATED WRITE ERROR TO BE RETRIED.
THE RETRY SCHEME CONSISTS OF REWRITING THE PECORD
IN THE SAME SPOT ON THE TAPE FOUR (4) TIMES.
IF
ALL FOUR (4) REPEATS ARE SUCCESSFUL, THE RECORD
IS CONSIDERED RECOVERED, AND A TAPE WRITE ERROR
IS LOGGED. IF ANY OF THE FOUR (4) REPEATS
IS UNSUCCESSFUL, A WRIT. WITH EXTENDED
INTFRFCORDGAP IS DONE, A SUSPECTED BAD TAPE
SPOT LOGGED AT THIS BLOCK .ND RECORD NUMBER,
AND A S~COND PETRY OF FOUR REPEATS IS DONE.
IF AFTER roup (4) R!TRI~S, THE RECORD CANNOT
BE RECQVERED A NOTIFICATION IS PRINTED, AND
TESTING IS RESUMED ON THE NEX1 RECORD.
IF 20(8) BAD TAPE SPOTS ARE FOUND, THE UNIT
WILL BE REWOUND AND REMOVED FROM TESTING WITH
AN APPROPRIATE MESSAGE PRINTED.
SWITCH ONE (1), WHEN SET TO A ZERO (0), WILL ALSO
CAUSE ANY DATA RELATED READ ERROR TO BE RETRIED.
T~E RETRY SCHEME CONSISTS nr REREADING THE RECORD
A MAXIMUM OF FOUR (4) TIMES. IF THE RECORD IS
SUCCESSFULLY RECOVERED ON ANY OF THE REREADS
IT TS CONSIDEREn FOR STATISTICS PURPOSES TO BE
A sorT READ ERROR AND TESTING CONTINUES IF THE
REREADS rAIL TO RECOVER THE RECORD, THE ERROR
IS LOGGED AS A HARD READ ERROR.

SW4:

SWITCH FOUR (4) WHEN SET WILL PRINT THE
STATISTICS GATHERED FOP. EACH UNIT. T~E NUMBER
WILL BE PRINTED AT THE END OF A BLOC~ CYCLE.
SEE ITEM 10, PAGE 20 rnR FULL DETAILS.

B-21

(PAGE 12)
SWITCH FrVE (5) WHEN SET DURING A READ
OPERATION wILL CAUS~ THE PROGRAM TO
CQNTINUOUSLY READ THE CURRENT RECORD BY
SPACING RrVERSE OVER THE RECORD AND
REREADING THAT RECORD. THIS TAPE MOVEMENT
15 CAtLED YGZZLING. THERE IS A SOFTWARE
DELAY EXECUTEn BETWEEN EACH SPACE/READ
OF THE RECORD AND IT MAY BE VARIED BY
TYPING CONTROL C ON THE TELETYPE DURING
THE EXECUTtrJ[IJ OF THE 10ZZ1,E AND RESPONDING
'Tn THE PIHNTED REQ1JEST WITH A SIX (6)
DIGIT VALUE, THE yQZZLE STALt IS PRESET
TO A VALUE OF 1000 IN THE PROGRAM TO
PREVENT EXCESSIVE TAPE WEAR, BUT MAY BE
SET TO ANY VALUE THROUGH THE TELETYPE.

SINS:

THESE THREE ()) SWITCHEs CONTROL THE RANDOMIZATION
DATA AND BLOCK SIZE AND MAY BE SET
AND RESET AT ANY TIM~. THE ACTUAL CHANGE
WTLL TAK! PLACE BETWEEN BLOCK CYCLES.

SW9!

SWiTCH NINE (9) WHEN SET WILL CAUSE ALL
AVAILaBLE TAPE UNITS TO BE REWOUND AT
THE END OF THE CURRENT RLOCK CYCLE, TESTING
WTLL SF RESUMED AT A BLOCK COUNT OF
ON! (1) W4EN ALL UNITS ~AVE REACHED BOT.

SW10-13:

THESE SWITCHES ARE USED TO CONTROL THE
ERROR HANDLING TO BE DONE ON THE TAPE
OPERATION DESCRIBED BY SWITCHES 0+3.
A.

SWITCH TEN (10) WHEN SET TO A ONE
\>JJ1.t. DISALLOW ANY ERROR PRINTOUTS MADE
ON THE OPERATION IN PROGRESS. rATASTROPHIC
FAILURES AND INFORMATION PRINTOUTS WILL
STILL nCCUR. IE! UNIT NOT AVAILABLE, ILLEGAL
AOT, DROP OR PICK OVERFLOW, AND EaT REWIND.

SWITCH FLEVPN (11) WHEN SFT TO A ONE
WILL DISALLOW THE CHECKING FOR STATUS
ERRORS ON READ OPERATTONS.

SWITCH TWELVE (12) WHFN SET TO A ONE
WILL DISALLOW THE CHBCKING FOR STATUS
ERRORS ON WRITE OPERATIONS.

SWITCH THIRTEEN (13) WHEN SET TO A ONE
WILL DISALLOW THE CHECKING OF REAn
DATA, THIS SWITCH HAS NO EffECT ON
STATIJS CHECKING.

B-22

(PAGE 13)
SW14:

SWITCH FOURTEEN (14) IS USED DURING A
Rr.AD ONLY OPERATION, WHF,N SET, THE
SLOCK OF DATA BEING READ WILL CONTINUOUSLY
BE READ AND SPACED OVER SO THAT TAPE wILL
RF.MAIN AT THE SAME BLOCK. WHEN RESET, THE
TAPE WILt BE ALLOWED TO MOVE FORWARD AND DATA
~LOCKS WILL BE READ PROGRESSIVELY.
THIS IS A BLOCK YOZZLE.

SW151

SWITCH FIFTEE~ (15) WHEN SET TO A ONE,
WILL CAUSE THE PROGRAM TO HALT ON ANY
ERROR DETECTED BY THE OPERATION IN PROGRESS.
IF BOTH SWITCH TEN (10) AND FIFTEEN (15)
ARE SET, THE ACTUAL ERROR DETECTED WILL
NOT SE PRINTED SUT WILL CAUSE A HALT.
IF SWITCH TEN (10) IS RESET BEFORE PRESSING
CO~TINUE, THE ERROR WHICH CAUSED THE HALT
Wt~L BE PRINTED BEFORE TESTING I~ RESUMED.

B~3

(PAGFO: 14)
9.

ERROR PRINTOUTS
THF.RE ARE THR~F TYPES or ERROP PRINTOUTS MADE BY
THE PROGRAM, OPEFATION ERRORS, DATA ERRORS, AND CONDITION
EPRORS. EACH ERRnp MP.SSAGE PRINTED IS PRECEDED BY A
HP.AOER WHICH cnNTAINS THE UNIT NUMBER, BLOC~ COUNT NUMBER,
B~!) Rfi:CORO NUMBfi:F PLTJS TOTAL NUMBER nF" RECORDS, SIZE OF
RECOPD, AND TYPE or OPFRATION WHICH CAUSED ERROR.
A.

OPERATION ERRORS:
THESE APE EPRnpS WHICH CAN OCCUR AS A DIRECT
RESIILT OF A TAPE OPERATION.

READ/WRITE STATUS ERRORS I

THESE ARE INDICATED BY THE ERROR BIT
(BIT 15) OF THE TAPE COMMAND REGISTER
BEI~G SET TO A ONE.

RECORD LENGTH ERRORS:

THESE ARE INDICATED BY A BYTE COUNT
OTHER THAN ZERO (0) OR AN INCORRECT
CURRENT MEMOFY ADDRESS OR AOTH

TAFF. POSITIONING ERRORS:

THESE APE INDICATED BY A SPACE
COUNT OTHER THAN ZERO (0), NO BOT FOUND
FROM A REWtND, OF NO TAPE UNIT
RrADY AT THE END OF PEWIND.

Dr.TA F.R~ORS:
DATA EPRORS WILL OCCUR WHEN TAPE IS
BrING READ AND THE DATA DOES NOT ~ATCH
THE EXPECTED DATA.
AECAU~E DATA PECO~DS CAN BE UP TO TWO THOUSAND
CHARACTERS LONG, AN ERROR CONDITION WHICH WILL CAUSE
THE ENTIRE RECORD TO READ INCORRECTLY COULD CAUSE A VERY
LrNGTHY PRINTOUT. THERErnRE, A cnUNTE~ OF SUCCESSIVE
BAD CHARACTERS IS EMPLOYED. IF TEN (10) CHARACTERS
IN SUCCESSION ARE 8AD, A NOTIFICATION IS PRINTED
(BAD RECORD) AND THE NEXT TWENTY (20) CHARACTEPS
A~E SKIPPED BFFORE CHECKING IS RESU~ED.
IF THE BAD
PEC~RD ~ONDITrON nCCURS THREE (3) TIMES IN ONF
RECnRD, THE RrST OF THE REcnPD IS SKIPPED, DOWN
TO THE LAST TEN (10) CHAPACTERS, WHICH WILL BE
CHECKED. THE SKIPPING AND RESUMPTION OF CHECKING WTLL
ONLY BE DONE nN RECORDS WHICH ARE LONG ENnUGH
Tn ALr,O'~ IT.

B-24

(PAGE 15)
C.

CONDITION ERRORS:

ERRORS REFLECT THE STATE or THE TAPE
SYSTEM BEFORE AND AFTER AN OPERATION.

~HESE

1. EOT: WHEN AN EOT (END OF TAPE) IS ENCOUNTERED DURING
EITHER A READ OR A WRITE, THAT UNIT IS FLAGGED AS
UNAVAlLABLE FOR TESTING AND IS REWOUND UNTIL ALL
AVAILABLE UNITS HAV~ REACHED EOT. AT WHICH TIME
TESTING IS RESUMED ON ALL AVAILABLE UNITS.
2. ILLEGAL ~OT: WHEN A UNIT ENCOUNTERS BEGINNING OF TAPE (BOT)
DUPING A REAP OPERATION THE ERROP IS
PRINTED AND THE UNIT DROPPED FROM TESTING
UNTIL ALL ARE RESTAPTED ON THE NEXT PASS.
3. DROP DRIVE:UNIT BECOMES UNAVAILABLE DUE TO LOSE OF SELECT REMOTE,
SOT DURING REWIND,OR NO TUR WHEN MAKING INITIAL SELECTION
UNIT IS DROPPED, STATISTICS PRINTED, TESTING WILL RESUME
AT BEGINNING OF NEXT PASS.
4.

NOT READY: BEFOPE ANY OPEPATION IS ATTEMPTED THE CONTROLLER
IS CHECKED FOR READY. IF IT IS NOT READY, AN
ERROR WILL BE PRINTED AND THE PROGRAM WILL STOP.

CO~TROLLFR

S. NO INTERPUPT PETURNED: EACH TAPE OPERATION SHOULD BE TERMINATED BY
SETTING AN INTERRUPT IN THE CPU. IF NO
TNTERRUPT IS RETURNED WITHIN THE APPROP1ATE
TJME, ~N ERPOR IS PPINTED.
6 •• 0 MOPE UNITS TO TEST: IF ALL UNITS HAVE BEEN DPOPPED
FOR CATASTPOP~IC ERROPS, THE PROGRAM WILL STOP.

BN = RLOCK NUMBER
RN
PECORD NUMBER (X) OF A TOTAL OF (Y)
RS = RECORD SIZE IN CHARACTERS PEP RECORD
WE = WRITE ERROR
FE = READ EPROP
SE = SPACr. ~PROR
F = FORWARD
CR
COMMAND REGISTER
CS = ~TATUS REGISTEP
WC = RYTE COUNTER
CA = CUP RENT MEMORY ADDRESS POINTEP AND EXPECTED VALUE
CN = C~ARACTER NUMBER
G = GOOD DATA (SHOWN IN BIT FORMAT AS IN CORE)
B = BAD DATA (SHOWN IN BIT FORMAT AS IN CORE)
ERR AMT = NUMBER LEFT Tn SP~CE
TM = TAPE MARK (OrtEN CALI,ED FOF FOR END OF FILE)
LPC = LONGITUDINAL PAPITY CHECK (PECEIVrD • EXPECTED)
PATTR~ = DATA PATTERN (R=RANOOM)

B-25

(PAGE 16)
EXAMPLE
EXAMPLE 11 IN THIS EXAMPLE A TAPE VERTICAL PARITY ERROR
WAS DETECTED DURING A WRITE OPERATIO~ OF THE
TWELVTH (12) RECORD OF THE BLOCK, THE WOPD
COUNT AND CURRFNT MEMORY ADDRESS ARE CORRECT,
THE RETRY OPTION WA~ DISABLED,
UNIT NO, 3 *DEN 1 *PAP 0 *PATTRN t
8N 406*RN 12-200*RS 2000*wE
COMD 1010001111000100
STAT 0001000001000001

we 0

CA \4436-14436
EXA~PLE

EXAMPLE 2: IN THIS EXAMPLE A RECORD LENGTH ERROR WAS
DETECTE~ WHILE READING THE FIRST
RECORD OF
THE BLOCK, THE RETRY OPTION WAS DISABLED, THE
wnpD COUNT SHOWS A COUNT OF 20 CHAPACTERS
LEFT TO BE TRANSFERREn, THE CURRf.NT MEMORY
AnDRESS REFLECTS THAT A SHORTAGE nF 20
C~ARACTFRS TRANSFERRED HAD OCCURRED,
IN
T"IS EXAMPLE THE STATUS AND COMMAND
REGISTERS Dn MOT SHOW ANY ERPOP, BUT
THE LPC IS SHOWN Tn BE INCORRECT,
UNIT NO, 7 *DEN 2 *PAR 0 *PATTRN
10*PH 1-100*PS 50*RE F***
COMO 0100011111000100
STAT 0000000001000001

we 20

CA 12466-12506
LPC 337 -\47
EXA~PL€

EXAMPLE 1: IN THTS EXAMPLE THE TAPE UNIT WAS TPYING
Tn SPACE OVER THE 15 RECORDS IN
THE BLOCK I~ nPDER TO ESTABLISH PROPER
POSITTON TO BFGIN READING,
THE OPERATInN WAS TERMINATED
REFORE THE FNTIRE 15 RECORDS WERE TRAVEPSfD
AND AN ERROR SHOWN RECAUSE THE TAPE IS
NOT TN PROPER POSITIDN TO AFGIN READING.
Nn, 0 *PATTPN R
2*RN 15·t5*PS 23 *SF

UN1~

ERK AMT 1

B-26

(PAGE 17)
EXAMPLE 4
EXAMPLE 41 IN THIS EX~MPLE UNIT NUMSER ONE (1) HAD BEEN
R~WOUND VIA CONSOLE SWITCH NINE (9) AND AT THE
cnMPL~TION OF THE OPERATION BOT WAS NOT S~T IN
THE STATUS REGISTER.
UNIT ~O. 1 *DEN 3 *PAR 0
3002*RN 6S-65*RS 10
NO ROT ON REWIND-HALT

*PATTRN R

EXAMPLg 51 TN THIS EXAMPLr. TWO BAD CHARACTERS WERE
RF.AD FROM TAPF. IN THE FORWARD DIRECTION.
THF FIRST (0) AND T~E THIRTEENTH (13) CHARACTERS
OF THE TOTAL NUMBER OF SIXTEEN (16) CHARACTERS
IN THE BLOCK ARE BAD. CHARACTER NUMBER
ZERO (~, HAS DROPPED BIT NUMBER FIVE (5) AND
CHARACTER NUMBER TWELVE (12) HAS PICKED UP
BIT NUM~EP SEVEN C71.
UNIT NO. 5 *DEN J *PAP 0 *PATTRN 5
BN 12*RN )-10*RS 15*OE-F**
CN 0
(;1 101.('11010
f!\,

10001010

CN t 2
G, IlI01011)1
1'\,

11(110101

B-27

(PAGE 1R)

EXAMPLE 6: IN THIS EXAMPLE UNIT NUMBER SIX (6) HAS
REa.CHEn END OF" TAPE (EDT) F"OR TKE 1ST TIME AND WILL SF: REWOUND,
TF"STING WILL RESTART ON UNIT NUMBER SIX (6)
\'!!-fEN IILI, UNITS !-fAVF" PEII(,HED EOT.
UNIT NO, 6 *DEN 3 *PAR n *PATTRN
8N 677 *RN 25~6nO*RS 1566
EDT NO. 1

UNIT WILL REWIND AND BE
RESTARTED ON BLOCK ONE
WI-1FN ALl, AVII.!I, UNITS REACH EDT

EXAMPLE 71 IN THIS EXAMPLE UNIT NUMBER TWO (2) HAS
E~COUNTF:RFD BEGINNING OF" TAPE (BOT). DRIVE WILL BE DROPPED
STATISTICS WILL BE PRINTED, TESTING RESUMED
AT BEGINNING OF NEXT PASS.
UNIT NO, 2 *DEN 2 *PAR 0
BN 56*RN 2-4*RS 1200
Tf.,LEGAL BOT

.PATTRN 2

EXA1',PLE 8
EXAMPI,F 8: IN THIS EXAMPl,F. THE SET"ECTFD UNIT (NUMBER 0)
HAS BECOME UNAVAILABL~.UNIT WILL PE DROPPED
STATI!>TICS WILL BE PRINTED, TESTING WILL RESUME AT
BEGINNING OF NEXT PASS.
UNIT NO, , *D~N 1 *PAR 0 *PATTRN 4
RN '.PN 0-200*RS ~6 NOT AVAIL
(DR LOST SEL!CT REMOTE, NO BOT ON REWIND)
F:XAMPLE 9
EXIIMPL~

9: IN THIS EXAMPLE THE WRITE OPERATION EXECUTED ON
lP'JIT N!J1>'BER SIX (6) WAS NOT COMPLETED AND NO
INTERRUPT WAS RETURNED.

UNIT NO, ~ *DEN 2 .PAR 0
AN 12*RN ]-4*R5 tnO-WE
NO INTERRUPT PETURNF:1'l

*PATTRN R

B-28

(PAGE 19)
EXAMPLE 10

.... _--- ..
EXAMPLE I to

THIS EXAMPLE SHOWS A RE~O ERROR WHICH
ON THE SECOND RETRY. THIS
ERROR WILL BE LOGGED AS A RDERR BUT WILL BE
CATEGORIZED AS A SOFT ERROR. THE REGISTERS
SHOW A PAPITY ERROR w~S THE CAUSE OF THE ERROR.
RECOVER~O

UNIT NO.1_DEN 3 *PAR 1 *PATTRN R
*BN 10 *RN 2-100 *RS 1117 *Rr. F***
COMO 1110100110000010
STAT 0011000001000001
WC 0
I, PC 3 37 -I 47
*-.ORIGINAL ERROR***
UNIT NO. 1 *Dr.N 3 *PAR 0 *PATTRN R
*RN 10 *RN 2-100 *RS 1117 *RE F**_
COMO 1110100110000010
STAT 0011000001000001
WC 0
LPC 337-147
READ FAILED--RETRYI 1
REREAD 5UCCESSFUL--RETRY: 2
EXAMPLE 11
EXAMPLE 111 THIS EXAMPLE SHOwS A WRITE ERROR WHICH
WAS NOT RECOVERED BY SUCCESSFbLLY REWRITTING
THE RECORD FOUR TIMES AT THAT LOCATION. TH!
RECORD WAS SUCCESSFULLY WRITTEN AFTER 3
INCHES OF TAPg WAS ERASED, THIS ERROR
WILL BF LOGGED AS A BAD TAPE SPOT,
UNIT NO. 0 .DEN 3 .PAR 0 *PATTRN R
*BN 2 *RN 370 -461 *RS 2407 *WE
COMO 1110000010000100
STAT 0011000001000001
WC 0
CA 25613 -25613
***ORIGINAL ERROR***
UNIT NO, 0 *DEN 3 .PAR 0 *PATTRN R
2 *RN 370 -46! *RS 2407 *WE
CO~D 11100.00010000100.
STAT ootl000001000001
WC 0
*~N

CA 25613 -25613

SUSPECT BAD
RETRY! 0
REPEAT: 0
RECClVF:RFD
RE'TRY: 1

TAP~

B-29

(PAGE 20)
10.

STATISTICS PRINTOUT
THE PROGRAM GAT~ERS A VARIETY OF STATISTICS DURING
COURSF. OF ITS T~STING. THg STATISTICS ARE KEPT
ON A UNIT BY UNIT BASTS AND ARE SUMMARIZEn IN A
STATISTICS PRINTOUT. STATISTIC PRINTOUTS CAN BE
PRINTFO AT THF. END OF EACH BLnCK CYCLF. BY SETTING
SWITCH FOUR (4) TO 1 • • ST~TISTIC PRINTOUT IS AUTOMATICALLY
PRINTED WHEN A UNIT REACHF.S EOT AND IS REWOUND.
T~E

HERE IS AN EXPLANATION OF THE STATISTIC SUMMARY.
DROPS:

T~E NUMBER OF 8JTS DROPPED ON A PER TRACK
BAStS. DROPS ARE cnLLECTED DURING THE DATA
CHECK ROUTINE.

PICKS:

THE NUMBER or AITS PICKED ON A PER TRACK
BASIS. DROPS APE COLLECTED DURING THE DATA
CHECK RnUTINE.

WTERR:

THE NUMBER OF RFCORDS IN WHICH A WRITE ERROR
OCCURRFD. IF WRITE RETRY WAS ENA8LED, WTFRR
WTLL CONTAIN nNLY THOSE RECORDS W~ICH WERE
NOT RECOVFRF.D AFTER ONE RETRY.

RTRYI

THE NUMBFR OF RETRlrs INITIATED UNDER THE
WRITE RF.TRY OPTION. (SEE ITE~ B., SWil)

RDERRI

THE TOTAL NUMBER OF RECORDS IN WHICH A
R~AD E~RnR OCCURRED.

SOFT:

THE NUMBEP OF READ ERRORS WHICH WERE
RECOVERED WITHIN A MAXIMUM OF FOUR
REREADS OF A RECORD UNDER THE RfAD RETRY
OPTION. (SEf ITEM 8 •• SW1:)
**NOTE: SOFT READ ERRnRS ARE ONLY CATEGORTZED
FOR THOSE READ [RRORS OCCURRING WHEN CONSOLE
SWITCH 1 IS SET TO ZERO.

~ARD:

OF PEAD ERRORS WHICH REMAINED
UNDER THE READ RETRY SCHEME,
(~E' ITEM R•• SW11)
**NOTE: HARD READ ERRORS ARE ONLY CATEGORIZED
F8R THOSE RF.AO ERRORS OCCURR1NG WHEN CONSOLE
SWITCH 1 IS SET Tn ZERO.
T~E

NU~BER

U~REcnVERED

DTERR:

THE NUMBER OF nATA ERRORS FOUND FOR THIS UNIT.
**NOTF.: DATA ERRORS ARE ONLY FOUND FOR THOSE
RECORDS W~ICH WERE READ WITH SWITCH 11 RESET TO
Z'PO.

(PAGE 21)
BAD TAPE SPOTS I A COUNT OF THE NUMBER OF TAPE SPOTS
WHERE A RECORD COULD ~OT BE REWRITTEN SUCCESSFULLY
UNDER THE WRITE RETRY OPTION (SEE ITEMB •• SWli)
FOLLOWING THE COUNT IS A LIST OF THE BAD TAPE
LOCATIONS IDENTIFIED BY THE BLOCK AND RECORD NUMBER
WHEN THE BAD TAPE SPOT WAS LOGGED.
EXAMPLE
DROPSI 0 0 0 0 7 0 0 0
PICKSI 0 0 0 2 0 0 0 0
WTERP: 3
RTRY: 4
RDEnRI 1\
SOrT: 1
HARDI 5
OTERRI 10
1 BAD TAPE SPOTS
o *AN 11; *R.N 41

B-31

(PAGE 22)
11.

AUTO SEQUENCE
THE AUTn SEQUENCE (START AT ADDRESS 240) WILL EXECUTE A
TEST PLAN ON ALL AVAILABLE UNITS. THE ONLY
OPERATOR RESPONSE REQUIRED IS Tn THE TYPED REQUESTS
FOR THE CONTROLLER ADDRESS AND VECTOR AND CONTINUOUS OR
~INGLE CYCLE~
ALL SWITCHES REMAIN ACTIVE AND MAY BE
USED NORMhLLY~ HOWEVER, THE INTENT IS TO LEAVE ALL SWITCHES
DOWN AND ALLOW FULL EXECUTION OF THp. TEST PLAN FOR
SYSTEM CHf1:CKOUT.
PREDETERMtN~D

SAMPLE START AT 240(8).
LOAD ADDRESS

240(~),

AUTO SEQUENCF.

SET SWITCHES TO ZERO, PRESS START.

TM,A,P~11 AUTO SEQUENCE TEST
ENTER RESPONSES IN OCTAL

RFGISTER START
172520 (CR)
VECTOR = 224 (CP)
AUTO CONTI 0 (I)
THIS EXA~PLE SHOWS AN AUTO SEQUENCE START WITH THE CONTROLLER
AT BUS ADDRESS 172520 AND A VECTOR OR 224. ALL AVAILABLE
UNITS WILL BE TESTED CONTINUOUSLY.
AS EACH PASS 1.5 crMPLETEO A DIVIDER LINE OF ASTERISKS
WILL BE PRINTED FOLLOWED BY AN END OF PASS MESSAGF.
'NDICATING HOW MANY PASSES HAVE BEEN COMPLETED SINCE
THE AUTO SEQUENCE WAS BEGUN. AT TH! START OF EACH
PA.SS TH~ tfNUS BEING TESTED APr.: PRINTE:O.
AUTO SEQUENCE TEST PLAN:
THE AUTO SEQUENCER WILL EXECUTE A PASS CONSISTING OF
THE WRITING, READING, AND CHECKING OF S~VEPAL
DIFFERENT DATA PATTERNS. EACH PASS WILL START AT BOT
AND PROCESS AN ENTIRE ~AG TAPE BEFORE REWINDING
THE UNITS WILL BE SET UP TO WRITE 800 BPI IN NINE
TRACK FnRMAT. 000 PARITY WILL BE USED AND NO
TIPF. MARKS WILL BE WRITTEN.
THE DATA

PATTF.R~S

WILL BE AS FOLLOWS I

THREE FIXED DATA PATTERNSr
EACH PATTERM wIJ,L BE USED FOR STX BLOCKS.
EliCH BLOCK CONS1STS OF (100) 4000 CJ.fARACTER RECORDS.
P.ATTEPI.J 3,

PATTERN 7:
P~TTFRN 111

WALKING ONE BIT
ALTERNATING ONE AND ZERO BITS
INCRE~ENTING CHARACTERS (000-377)

B-32

(PAGE 23)
RANDOM DATAl
rOLLOWING THE FIXED DATA PATTERNS, RANDOM
DATA WILL BE WRITTEN IN THE SAME BLOCK STRUCTURE
UNTIL EOT IS REACHED.
IT IS IMPORTANT THAT THE TAPE USED FOR THE TEST
BE OF SUFFICIENT LENGTH TO ACCOMODATE ALL OF
THE FIXED DATA PATTERNS AND AT LEAST OKE
RECORD OF RANDOM DATAl OTHERWISE, THE TAPE WILL
~E REWOUND UNTIL ALL nF THE DATA PATTERNS
H~VE BEEN TESTED.

B-33

(PAGE 24)
12.

TESTING

P~OCEDURES

.-------.~.------~

AS PREVIOUSLY STATED THIS PROGRAM CONTAINS NO
FIXED TESTS. THE ENTIRE TEST CYCLE TO BE EXECUTED
ts DESCRIBED BY THE OPERATOR THOUGH RESPONSES TO
TELETYP~ REQUESTS FOR PARAMETERS AND CONSOLE SWITCH
SETTINGS rOR ~PERATION. THE OPERATTON SELECTED WILL
BE EXECUTED WITH THE PARAMETERS ENTERED CONTINUOUSLY
ON EACH AVAILABLE UNIT, ONE BLOCK AT ~ TIME, UNTIL
STOPPED BY THE OPER~TOR. THE OPERATION MAY BE CHANGED
DYNAMICALLY BY CHANGTNG THE CON~DLE SWITCHES AT ANY
TIME. THE PROGRAM WILL ATTEMPT TO PERFORM ANY OPERATION
SET AND THEREFORE CAUTION SHOULD BE TAKEN TO ASSURE THAT
THE UNYT IS CAPABI,E OF PERFORMING AS REQUESTED. fOR
r.STANCE, ONE SHOUT,n NOT ATTEMPT TO PERrORM READ OPERATIONS
ON A TAPE WHICH HAS NOT BEEN ~RITTEN AS THE DAT~. IF ANY,
rs UNPREDICTAPLF. HOWEVER, IF A TAPF HAS BEEN WRITTEN WITH
THIS PROGRAM, IT CAN BE READ AS OFTEN AS DESIRED WITHOUT
BEING R~WRITTEN. THIS IS A GOOD PROCEDURE TO USE rOR
TESTING TAPE COMPATABILITY. SCOPING OF T~PE UNITS BECOMES
SIMPLE, BY SETTING THE DESIRED OPERATION AND ITS PARAMETER,
A UNIT M~Y BE cnNTIN 1lnUSLY EXERCISED IN ANY MANNER DESIRED.
BY USING THE VARIOUS ERROR CONTROl, SWITCHES AND ENTERING
THE NEEDED STALL, ANY FllNCTION CAN BE SCOPED RATHER
EASILY, RELIABILITY TESTING CAN BE PREFORMED BY USE
nr THE RANDOMIZATION CAPABILITY. PERHAPS A CYCLE OF
RANDOM TESTING MIGHT BE SET UP AND ALLOWED TO PUN
FOP SOME PERIOD nF TIME, THE STATISTICAL COLLECTION
OF DRnps AND PICKS IS THEN SIGNIFICANT. INTERHITTANT
PROBLEMS CAN BE fOUND BY SETTING THE nESIRFD OPERATION
IN MOTION AND DISALLOWING FRRnR PRINTOUTS WHILE ALLnWING
A HALT nN ERROR, THE ERROR THAT CAllSED THE HALT CAN
BE PRINTED BY RESETTING CONSOLE SWITCH TEN ANn PRESSING
CONTINUE. IF SOME PARTICULAR DATA PATTERN SHOULD BE
CAUSING DATA ~RAOA, USE OF THE YOZZLE SWITCH AND ITS
ASSOCTATEO STALL CAN R~ USED TO ALLOW SCOPING OF THIS
PAATTCULAA RECQRD.
AS YOU SEF, THERE ARE MYRIAD TESTING PROCEDURES WHICH
COULD AE pE~FORMED, THF PARAMETERS, TAPE OPERATIONS, ERROR
EXAMINATION AND REPORTING ARE ALL AT VOIIR DISCRETION.
TRY IT, YOU'LL LIKE IT,
13.

LISTING

B-34

IDENTIFICATION
PRODUCT CODEI
PRODUCT NAMEI

TM,A,B_tl/TU10,W,N DRIVE FUNCTION TIMER

DATE

AUGUST 1976

MAINTAINER I

DiAGNOSTIC ENGINEERING

AUTHORS

R. B. BARNES

eel 1976, 1974 DIGITAL EQUIPMENT CORPORATION
MAyNARD, MASS 01754
REVISED BYa

RON PLATUKIS/R. SOLER

THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT
NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQuIPMENT CORPORATION. DIGITAL EQuIPMENT CORPORATION ASSUMES
NO RESPONSIBILITY FOP ANY ERRORS THAT MMAY APpEAR IN THIS DOCUMENT
THE SOFTWARE DESCRIBED IN THIS DOCUMENT IS FURNISHED UNDER A
LICENSE AND MAY ONLY BE USED OR COpIED IN ACCORDANCE WITH THE
TERMS or SUCH LICENSE.
DIGITAL EQUIPMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR
THE USE OR RELIABILITY or ITS SOFTWARE ON EQUIPMENT THAT IS
NOT SUPPLIED BY DIGITAL.
COPYRIGHT (C) 1974, 1976 BY DIGITAL EQUIPMENT CORPORATION

B-35

TABLE OF CONTENTS
PARAGRAPH

SUBJECT

PAGE

ABSTRACT
3
REQUIREMENTS
3
LOADING PROCEDURE
3
STARTING PROCEDURE
4
OPERATING PROCEDURE
4
ERRORS AND LIMITS
5
RESTRICTIONS
1
MISCELLANEOUS
7
PROGRAM DESCRIPTION
B
REGISTER BIT ASSIGNMENTS 17

B-36

0S-AUG.76
1.

16.47

PAGE 61

ABST~ACT

THE DRIVE FUNCTION TI~ER ASSISTS IN THE TESTING OF THE TM_It
O~ TMA,S-11 CONT~OL UNIT AND TU10 OR TU10W OR TU10N TAPE UNITS.
OPERATIONS A~E EXECUTED, TIMED, AND THE TIMES ARE THEN
P~INTED (IN MILLISECONDS).
THERE IS NO LIMIT OR ERROR
TESTING fACILITIES IN THE PROGRAM, THE DECISION ON THE
VALIDITY OF TIMES MEASU~ED MUST BE MADE BY THE OPERATOR.
ANy CONFIGURATION or UP TO 8 TU10,W,N TAPE UNITS (7 AND 9
CHANNEL) MAY BE SELECTED.
2.

REQUIREMENTS

2.1

EQUIPMENT
PDP-l1.TM,A,B-ll TAPE CONTROL UNIT AND 1 TO B TApE DRIVES.
(TU10,N,w AND ANy CONFIGURATION OF 7 OR 9 CHANNEL DRIVES)
*NOTE. TU10W TAPE UNITS WILL GO IN COMBINATION W/TMA,B-l1
CONTROL UNITS ONLY.
STORAGE
PROGRAM STORAGE
THE PROGRA~ REQUI~ES 4K OF MEMORY.

LOADING PROCEDURE

3.1

METHOD
A.
B.

FOR NORMAL BINARY TAPES SHOULD BE FOLLOWED
IS LOADA'SLE AND CHAINASLE IN BK OF MEMORY.
DEFAULT IS DRIVE 0 9TRK ONLY.

PROCEDU~E
PROG~AM

B-37

0S .. l\UC;"76

16147

PAGE 62

PPOCEDURE

STA~TING

". i

BEFORE STARTINC PROGRAM SET LOC, 176 WITH DESIRED
CONTROL SETTINGS. (DEFAULT.200,DPIVE O,9 TRK)
BITS 1 S .. 0 ARE USED TO INDICATE THE TAPE UNIT CONFIGURATION.
Ulli
1481

U-l
12B1

HAVE UNIT e
1
"
2
"

"
"
"

U-l
1011 1

9Bl
8111

7=1

"
HAVE UNU

6B1
Sill
4=1
381

2=1
till

081

"
"
"

"5
6
'7

'1"

SELECTED,

7 TRACK

"
"
"
"
"
"
"
SELECTED,

"
"
"

4.2

STARTING ADDRESS

4.3

PROGRAM ANDIOR OPEPATOR ACTION

"
"
"

9 TRACK

"
"

is
6

LOAD PROGRAM INTO MEMORY.
SET DESIRED TAPE UNITS ON.LINE.
LOAD LOC. 176 WITH CONTROL SETTINGS (SEE 4,1)
LOAD STARTING ADDPESS.
PRESS START,
THt PROGRAM WILL BEGIN TIMING FUNCTIONS.
ON COMPLETION or ALL TESTS "END OF TIMING" WILL BE PRINTED AND
THE PROCESSOR WILL HALT.
TO REPEAT TESTI IF SAME CONTROL SETTINGS ~RE DESIRED SIMPLY PRESS CONTINUE.
IF DIFFERENT SETTINGS ARE NECESSARY RELOAD LOC.176 AND LOAD ADDRESS 200.START.
5.

OPERATING PROCEDURE

5.i

OPERATIONAL SWITCH SETTINGS
NONF:

B-38

THE PROGRAM HAS NO INTERNAL ERROR DETECTION fACILITI~S AND,
THEREFORE, NO ACTUAL ERROR TYPEOUTS. THE VALIDITY OF THE
TIMES MEASURED MUST BE DETERMINED BY THE OPERATOR,

6.1

TIME RELATIONSHIPS
A. "READ SHUTDOWN" MUST BE C "WRITE SHUTDOWN".
B. GAPS MUST. 8>1>6>5>4>3, 3-2-1 (1.5).
C. "WRITE EOr" SHOULD BE SLIGHTLY> "WRITE XJPG".
*NOTEI
1. TU10 TIMING INFO REFERENCE 6,2
2. TU10W (M8926) TIMING INFO REFERENCE 6.3
3. TU10N (M8921) TIMING INFO REfERENCE 6.4

B-39

*****************
TIME LIMITS AND PRINTOUT FORMAT *** TU10 ONLY ***
*****************

6,2

TIMES INDICATED UNDER "UNIT A" ARE STANDARD FOR A 9 CHANNEL UNIT
AND "UNIT Bft FOR A 7 CHANNEL UNIT, TIMES ARE IN MILLISECONDS.
TOLERANCES INDICATED WITHIN "e)" ARE PLUS OR MINUS,
UNIT A (9 CHANNEL)
FUNCTION
180.0
(15,0)
WRITE FPOM BOT DELAY
7,1
(1.0)
WRITE SHUTDOWN
8.9
(0.4)
WRITE START
SETTLE DOWN DELAY
12.0
(4.0)
11.0
(4.ft",
WRITE TO ERASE HEAD
BACKSPACE SHUTDOWN
2.2
e 0,3)
2,2
(0,3)
READ SHUTDOWN
GAPS SHOULD = 8>7>6>5>4>3, 3-2=1 (1,5).
13,4
SEE
GAP 1
0.4
NOTE
GAP 2
13.4
AeOVE
GAP 3
GAP 4
16.8
GAP 5
2IIJ • 2
23 ,4
GAP 6
;16.5
GAP 7
30,2
GAP 8
( 0,4)
8,9
WRITE START
(10.0)
95,0
WRI'l'E XIRG
(10,0 )
READ FROM BOT DELAY
9IIJ .0
( 10,0)
WRITE Eor
114.0
(10.0)
EOR TO EOF SP TIME
11!10 .0
( 0,3)
SPACE SHUTDOWN
2.2
( 1,0)
ONE INCH DATA TIME
22.3
*FUNCTIONS AT 556 BPI
WRITE FROM BOT
ONE INCH DATA TIME
WRITE SHUTDOWN
BACKSPACE SHUTDOWN
READ SHUTDOWN
*FUNCTIONS AT 200 BPI
WRITE FROM BOT
ONE INCH DATA TIME
WRITE SHUTDOWN
BACKSPACE SHUTDOWN
READ SHUTDOWN
END OF TIMING
*

NOTE,

UNIT B
SAME

10,4
12,6

1.0)
B.S)

SAME
SAME
6.5

SAME
20.1
20.1

20.1
26,7
33,3
39,9
46 ,5
53.1
12.6

SAME
SAME
! 18. 0
sAME
sAME
SAME
t 85.0

(15.0)

22. 0
10,4
6,7
2,3

( 1.'"
C B,5)

tl5,0
22.0
11!1,4

(15.0)
( 1.0)
( 1.0)

7.5
3.1

( 0,5)
( 0.3)

THESE TIMES ONLY PRINTED WHEN ONE OR MORE 7 CHANNEL
TAPE UNITS ARE SELECTED.

B-40

CHANNEL)

( 0,8)
( 0,3'

05-AUG-76

16,47

PAGE 65

******************
TIME LIMITS AND PRINTOUT FORMAT *** TU10N (1018926) ONLY ***
******************

6.3

TIMES INDICATED UNDER "UNIT A" ARE STANDARD FOR A 9 CHANNEL UNIT
AND "UNIT B" rOR A 7 CHANNEL UNIT. TIMES ARE IN MILLISECONDS.
TOLERANCES INDICATED WITHIN "C)" ARE PLUS OR MINUS.
FUNCTION
UNIT A (9 CHANNEL)
WRITE FROM BOT DELAY
184.6
C15.0)
WRITE SHUTDOWN
6.5
(0.6)
WRITE START
8,9
(0.8)
SETTLE DOWN DELAY
12.0
(4,0)
WRIT! TO ERASE HEAD
11.0
(5.0)
BACKSPACE SHUTDOWN
2.2
(0,2)
READ SHUTDOWN
2.2
(0,2)
GAPS SHOULD. 8>7>6>5>4>3, 3=2=1 (1,5)
GAP 1
13.2
SEE
GAP 2
13.2
NOTE
GAP 3
13.2
ABOVE
GAP 4
16~8
GAP 5
20,2
GAP 6
23.4
GAP 7
26.5
GAP 8
30.2
( 0.8)
WRITE START
8.9
( 9,0)
WRITE XIRG
95.0
(13.0)
READ FROM BOT DELAY
150.6
(15.0)
WRITE EOF
114.0
( 9,O)
EOR TO EOF SP TIME
100.9
( 0.• 2)
SPACE SHUTDOWN
2.2
( 1. 0)
ONE INCH DATA TIME
22.3
*FUNCTIONS AT 556 BPI
WRITE FROM BOT
ONE INCH DATA TIM~
WRITE SHUTDOWN
BACKSPACE SHUTDOWN
IlEAD SHUTDOWN
*FUNCTIONS AT 200 BPI
WRITE FROM BOT
ONE INCH DATA TIME
WRITE SHUTPOWN
BACKSPACE SHUTDOWN
READ SHUTDOWN
END OF TIMING
*

NOTEI

UNIT B
20e. 7

6.8
15 ,1

(15.0)
( O.6)
( 1.l)

SAME
SAME
6.6
SAME
(t.6)

19,1
19.1
19,1
26,7
33.3
H.9

46.5
53.1
15.1
98.6

90.e
117.2
104.4

( 1.l)
( 9.0)
( 9.0)
(15.0)
( 9.0)

SAME
SAME

200.7
22.3
7.2
6.9
2.3
200.7
22.3
9.4
7.9
3.3

THESE TIMES ONLY PRINTED WHEN ONE OR MORE 7 CHANNEL
TAPE UNITS ARE SELECTED.

B-41

CHANNEL)

(15,O)
( 1,0)
( 0.7)

( 0,6)

( 0.2)
(15.0)
( 1.0)
( 1.0)

( ".7)
( O.3)

05-AUG-76

16147

PAGE 66

••••••••••••••••••

TIME LIMITS AND PRINTOUT FORMAT •• * TU10N (M8927) ON~Y .**
*.********* •• *****

6.4

TIMES INDICATED UNDER "UNIT A" ARE STANDARD FOR A 9 CHANNEL UNIT
AND "UNIT B" FOR A 7 CHANNEL UNIT, TIMES ARE IN MILLISECONDS.
TOLERANCES INDICATED WITHIN "C)" ARE PLUS OR MINUS.
UNIT A (9 CHANNEL)
FUNCTION
180.0
(15,0)
WRITE FROM BOT DELAY
7.1
(1,0)
WRITE SHUTDOWN
8.9
(0,4)
WRITE START
12.0
(4,0)
SETTLE DOWN DELAY
11.0
(4.0)
WRITE TO ERASE HEAD
2.2
(0.3)
BACKSPACE SHUTDOWN
2.2
(0,3)
READ SHUTDOWN
GAPS SHOULD • 8>7>6>5>4>3, 3.2~1 (1,5),
13.4
SEE
GAP 1
13.4
NOTE
GAP 2
13.4
ABOVE
GAP 3
16.8
GAP 4
20.2
GAP 5
23,4
GAP 6
26.5
GAP 7
GAP 8
30.2
( 0.4)
WRITE START
8.9
(10.0)
95.0
WRITE XIRG
( 10.0)
90.0
READ FROM BOT DELAY
(10.0)
WRITE EOF
114 .0
( 10.0)
100.O
EOR TO EOF SP TIME
( 0,3)
SPACE SHUTDOWN
2.2
( 1.0)
ONE INCH DATA TIME
22.3
*FUNCTIONS AT 556 BPI
WRITE FROM SOT
ONE INCH DATA TIME
WRITE SHUTDOWN
BACKSPACE SHUTDOWN
READ SHUTDOWN
*FUNCTIONS AT 200 BPI
WRITE FROM BOT
ONE INCH DATA TIME
WRITE SHUrDOWN
BACKSPACE SHUTDOWN
READ SHUTDOWN
END OF TIMING
•

NOTEI

UNIT B
SAME
7,1
15,3
SAME
SA""E
6.5
SAME

1,0)
0,5)

20,1
20,1
20,1
26,7
33,3
39,9
46,5
53,1
15.3
SAME
SAME
118,0

SAMt:
SAME
SAME
185,0
22.0
7,1
6,7
2.3

(15,0)

185,0

(15.0)
( 1,0)

22.0
7.1
7,5
3.1

THESE TIMES ONLY PRINTED WHEN ONE OR MORE 7 CHANNEL
TAPE UNITS ARE SELECTED,

B-42

CHANNEl,)

( 0,8)
( 1,0)

( 0.5)
( £1,3)

( 1,0)

( 0,5)
( !!l,3)

RESTRICTIONS

7.1

STARTING RESTRICTIONS

AT LEAST ONE TU10 TAPE UNIT MUST BE "ON-LINE" AND S~LECT!D
BY SWITCHES PER 4.1. ALSO MAKE CERTAIN THAT EACH TM10
THAT IS "ON.LINE" HAS A UNIQUE UNIT NUMBER SELECTED,
1.2

OPERATING RESTRICTIONS
THE INSTRUCTION TEST MUST RUN WITHOUT ERRORS BEFORE ATTEMPTING
TO OPERATE THIS PROGRAM. (OZTMA)

MISCELLANEOUS

B,l

EXECUTION TIME

NOT APPLICABLE

B-43

05-AUG-76
9.0

PROGRAM DESCRIPTION

9.1

WRITE FROM BOT DELAY

16.47

PAG! 68

WRITE FROM BOT DELAY IS THE TIME NECESSARY TO MOVE THE BEGINNING
OF TAPE (BOT) MARKER APPROXIMATELY 6 INCHES PAST THE WRITE H!AD.
THE FIRST RECORD ON TAPE MUST BE WRITTEN AT LEAST 3 INCHES AWAY
FROM THE BOT MARKER.
PROCEDURE TO MEASURE TIME.
A.
8.
C.
D.
E,

9.2

IF TU10 IS NOT AT BOT IT IS REWOUND TO BOT,
INITIALIZE BYT! RECORD COUNTER AND CURRENT MEMORY ADDRESS
REGISTER.
ISSUE WRITE FUNCTION, 800 BPI, SET "GO",
MONITOR CURRENT MEMORY ADDRESS REGISTF.R TO DETERMINE WHEN
2ND BYTE IS OUTPUT.
THE TIME FROM "GO" UNTIL 2ND BYTE IS OUTPUT IS
APPROXIMATELY EQUAL TO "WRITE FROM BOT DEtAY",

WRITE SHUTDOWN
WRITE SHUTDOWN IS THE AMOUNT OF TIME NECESSARY TO CONTINUE
MOVING TAPE AFTER A RECORD IS WRITTEN SO THAT THE PROPER
INTERRECORD CAP WILL EXIST BETWEEN RECORDS.
PROCEDURE TO MEASURE TIME.
A.
B.
C.

THE PROGRAM USES THE SAME RECORD THAT WAS WRITTEN TO TIME
"WRITE FROM BOT DELAY",
AFTER THE LAST BYTE (BC~0), INDICATING THE END OF THE
RECORD, MONITOR "SETTLEDOWN" UNTIL IT BECOMES A 1,
THE TIME FROM "BC-0" UNTIL "SETTLEDOWN" IS "WRITE
SHUTDOWN".

B-44

9.3

WRITE STAPT
WRITE START IS THE TIME NECESSARY FOR TApE TO ACCELERATE TO
FULL SPEED AND GUARANTEE A 1/2 INCH INTERRECORD GAP.
pROCEDURE TO MEASURE TIMES
SAME AS "WRITE FROM BOT" EXCEPT NOW WE ARE NOr AT aOT.
A. INITIALIZE BYTE RECORD COUNTER AND CURRENT MEMORY ADDRESS
REGISTER.
B. ISSUE WRITE FUNCTION, 800 BPI, SET "GO".
C. MONITOR CURRENT MEMORY ADDRESS REGISTER TO DETERMINE WHEN
2ND BYTE IS OUTPUT.
D. THE TIME FROM "GO" UNTIL 2ND BYTE IS OUTPUT IS APPROXIMATELY
EQUAL TO "WRITE START".

9.4

SEtTLEDOWN DELAY
TAPE ODES NOT ACTUALLY COME TO A COMPLETE STOp UNTIL SOME
PERIOD OF TIME AFTER SHUTDOWN HAS ENDED. ALSO, AFTER TAPE HAS
rULLY STOPpED, AN ADDITIONAL PERIOD or TIME Is NECESSARY fOR THE
TAPE AND HARDWARE TO "SETTLEDOWN" AND BECOME STABLE. THE
"SETTLEDOWN DELAY" IS THE PERIOD OF TIME NECESSARY FOR THE TAPE
AND MECHANICAL CHARACTERISTICS or THE TU10 TO BECOME STABLE, so
THAT THE UNIT CANNOT BE OPERATED, STARTISTOP, AT A FREQUENCY WHERf,
IT IS Mf,CHANICALLY RESONANT.
PROCEDURE TO MEASURE TIME I
A.
B.
C.

9.5

THE PROGRAM USES THE SAME RECORD THAT WAS WRITTEN TO TIME
"WRITE START"
AFTER "SETTLEOOWN" BECOMES A 1, INDICATING THE START OF
SETTLEDOWN, MONITOR "TU READY" UNTIL IT BECOMES A 1.
THE TIME FROM "SETTLEDOWN~ UNTIL "TU RElDY" IS ·SETTLEDOWN".

WRITE TO EpASE HEAD

THE PURPOSE or THE ERASE HEAD IS TO INSURE THAT THE TAPE IS IN
THE SAME FtuX STATE AS THE WRITE HEADS. THIS IS NECESSARY FOR
sEVERAL REASONS.
1.
2.
3.

STAPT/STOP CHARACTERISTICs VARY AMONG TAPE UNITS AND IT
WOULD BE POSSIBLE TO LEAVE OLD DATA IN THE INTERRECORD GAPS
WHEN USING A TAPE ON MORE THAN ON! UNIT.
A TAPE PREVIOUSLY USED AT ONE RECORDING DENSITY COULD NOT BE
USED LATER AT ANOTHER DENSITY.
TRACK ALIGNMENT AND HEAD WIDTH VARY FROM TAPE UNIT TO
TAPE UNIT AND IT WOULD BE POSSIBLE rOR DATA TO BE LEfT ON
THE TRACK EDGES FROM OLO RECORDS.

B-45

0S-AUG-76

16147

PAGE 70

THE ·WPITE TO EPASE HEAD" TEST INSURES THAT THE TAPE IN FRONT or
THE WRITE HEAD IS ERASED DURING A WRITE OPERATION,
PROCEDURE TO MEASURE TIME.
A.
B,
C,
D,
E.
F.
G,
H.
I.

A LONG RECORD HAS BEEN WRITTEN FROM BOT. SAME RECORD THAT
WAS USED TO TIME "WRITE FROM BOT DELAY",
TAPE IS REWOUND TO BOT.
BYTE RECORD COUNTER IS INITIALIZED FOP A ] BYTE RECORD
AND CURRENT MEMORY ADDpESS REGISTER IS INITIALIZED,
ISSUE WRITE FUNCTION, 800 BPI, SET "GO",
MONITOR BYTE RECORD COUNTER UNTIL IT • A INDICATING THAT 2
BYTES ARE WRITTEN IMMEDIATELy ISSUE A POWr.R CLEAR WHICH
STOPS ALL DATA TRANSFERS AND CAUSES THE DRIVE TO SHUTDOWN,
TAPE IS REWOUND TO BOT
INITIALIZE BYTE RECORD COUNTER C] BYTES) AND CURRENT
MEMORY ADDRESS REGISTER,
ISSUE READ FUNCTION, 800 BPI, SET GO
MONITOR BYTE RECORD COUNTER UNTIL IT • -1 AND THEN TIME
UNIT IT • 0, THIS TIME WILL INDICATE THE DISTANCE BETWEEN THE
2ND BYTE AND THE 3RD BYTE wHICH Is ALSO THE AMOUNT OF TApE
THAT WAS ERASED BY THE ERASE HEAD DURING THE WRITE OPERATION
OR "WRITE TO ERASE HEAD".

B46

9,6

BACKSPACE SHUTDOWN
"8ACKSP~CE SHUTDOWN" IS THE LENGTH OF TIME NECESSARY TO GUARANTEE
THAT If A WRITE OPERATION FOLLOWS A BACKSPACE THE TAPE WILL BE
POSITIONED SUCH THAT ALL PREVIOUS DATA IS IN FRONT or THE WRITE
AND ERASE HEADS AND wILL BE ERASED, "BACKSPACE SHUTDOWN" MUST
BE LESS THAN "WRITE START" SO THAT INTERRECORO GAPS WILL I~CREASE
IF A BACKSPACE/REWRITE OPERATION IS INITIATED,

PROCEDURE TO MEASURE TIME.
A,
B,
C,
D,
E,

G,
9,7

INITIALIZE BYTE RECORD COUNTER AND CURRENT MEMORY ADDRESS
REGISTER,
ISSUE WRITE EOF FUNCTION, 800 BPI, SET "GO"
AfTER EOF RECORD IS WRITTEN WAIT FOR "TU READY",
SET BYTE RECORD COUNTER TO BACKSPACE 1 RECORD,
ISSUE BACKSPACE FUNCTION, SET "GO".
AFTER "EOF" BECOMES A 1, INDICATING THE RECOGNITION OF
THE "EOF" RECORD, MONITOR "SETTLEOOWN" UNTIL IT BECOMES A I,
THE TIME FROM "EOF" UNTIL "SETTLEDOWN" IS "BACKSPACE
SHUTDOWN",

READ SHUTDOWN
READ SHUTDOWN IS THE AMOUNT OF TIME NECESSARY TO CONTINUE MOVING
TAPE AFTER A RECORD IS READ sO THAT THERE IS ENOuGH GAP rOR TAPE
TO BE FULLY ACCELERATED IF A READ IS FOLLOWED BY A BACKSPACE,
"READ SHUTDOWN" MUST ALSO BE LESS THAN "WRITE SHUTDOWN" TO
GUARANTEE THAT THE WRITE AND ERASE HEADS WILL BE POSITIONED
SUCH THAT ALL PREVIOUS DATA IS IN FRONT OF THE HEADS AND
WILL BE ERASED IF A w~ITE FOLLOwS A READ. IN ADDITION, WHEN A
WRITE FOLLOWS A READ THE INTERRECORO GAP MUST STILL BE AT LEAST
1/2 OF AN INCH,
PROCEDURE TO MEASURE TIME.
A,
B,
C.
D.
E,

RECORD PREVIOUSLY USED IN "BACKSPACE SHUTDOWN" IS READ,
INITIALIZE BYTE RECORD COUNTER AND CURRENT MEMORY ADDRESS
REGISTER
ISSUE READ FUNCTION, 600 BPI, SET "GO".
AFTER "EOF" BECOMES A 1, INDICATING THE END or THE
RECORD, MONITOR "SETTLEDOWN" UNTIL IT BECOMES A 1,
THE TIME FROM -EOF" UNTIL "SETTLEDOWN" IS "READ
SHUTDOWN"

B-47

9,S

GAP CONSISTENCY
FOR PFOPER OPERATION, THE INTERRECORD GAPS ON TAPE MUST ALWAYS
BE AT LEAST 1/2 OF AN INCH. THIS WILL ALLOW DATA WRITTEN USING
ONE TApE UNIT TO BE READ ON ANOTHER TAPE UNIT WHEN THE START/STOP
CHARACTERISTICS or EACH UNIT ARE DIFFERENT. THE MINIMUM
GAP SIZE OF 1/2 INCH IS GENERATED wHEN A WRITE FOLLOwS A READ.
ALL OTHER GAPS SHOULD BE LARGER DEPENDING ON HOW THE¥ WERE
WRITTEN.
PROCEDURE TO MEASURE TIMEs
A.
B.
C.
D.
E.
F.
G.
H.

A TOTAL OF NINE RECORDS ARE WRITTEN ON TAPE (FROM BOT)
UTILIZING DIFFERENT SEQUENCES TO GENERATE THE INTERRECORD GAPS.
THE TAPE IS REWOUND TO eOT.
INITIALIZE BYTE RECORD COUNTER AND CURRENT MEMORY ADDRESS
REGISTER.
ISSUE READ FUNCTION, 800 BPI, SET "GO".
WAIT FOR "CU ~EADY" TO BECOME A 1, THEN REPEAT STEP C AND
RESET "GO" TO CONTINUE.
MONITOR CURRENT MEMORY ADDRESS TO DETERMINE WBEN 2ND BYTE IS
INPUT.
THE TIME FROM WHEN "GO- IS RESET UNTIL THE 2ND BYTE IS INPUT
WILL REFLECT THE SIZE OF THE GAP.
STEPS E, r ARE REPEATED UNTIL ALL 8 GAPS ARE MEASURED.

PROGRAM SEQUENCE FOR EACH GAPa
GAP 1

WRITE FOLLOWED BY A WRITE (START/STOP).

GAP 2

WRITE fOLLOWED BY A WRITE (START/STOP).

GAP :3

READ FOLLOWED BY A WRITE (STAPT/STOP).

GAP 4

WRITE.BACKSPACE fOLLOWED BY A WRITE (START/STOP).

GAP Ii

SAME AS GAP
TIMES.

GAP 6

SAME AS GAP 4 EXCEPT WIHTE ... 8ACKSPACE REPEATED 3
TIMES.

GAP '1

SAME AS GAP
TItolES.

GAP S

SAME AS GAP 4 EXCEPT WIUTE .. SACKSPACE REPEATED 5
TIMES.

" EXCEPT WRlTE ... BACKSPACE REPEATED
4

EXCEPT WRITE .. BACKSPACE REpEATED

GAP LENGTHS SHOULD REFLECT THE FOLLOwING RELATIONSHIP!
8>7>6>5>4>],

)g2111

(l.S).

B-48

0S-AUG-76

9.9

16147

PAGE 73

WRITE START
THIS IS A ~EPEAT OF THE "WRITE START" TEST PREVIOUSLY COMPLETED
(REFERENCE 9.]), IT'S PURPOSE IS TO DETERMINE IF TAPE WILL
DRIFT BACKWARDS TO BOT IF A "POWER CLEAR" IS ISSUED AS SOON
AS 80T DISAPPEARS WHEN MOVING FORWARD FROM 80T. TIME SHOULD
EQUAL 'WRITE START" AS MEASURED IN 9.3.

9.1A

WRITE XIRG
WRITE WITH AN EXTENDED INTERRECORD GAP IS A FUNCTION THAT CAUSES
THE GENERATION OF AN INTERRECORD GAP THAT IS AT LEAST 1 INCH LONG
AS COMPARED WITH THE NORMAL 3/5 INCH GAP. THE PURPOSE IS TO
ELIMINATE WRITE ERRORS THAT MAY BE CAUSED BY A DEFECTIVE AREA
ON TAPE. NORMALLY ONE REWRITE WITH XIRG WOULD 8E SUrFICIENT TO
MOVE PAST THE 8AO SPOT, HOWEVER IF IT ISN'T, THE PROCEDURE
WOULD BE TO REPEAT THE "BAC~SPACE-REWRITE WITH XIRG" SEQUENCE UNTIL
A RECORD IS WRITTEN WITHOUT ERRORS. EACH SUCCESSIVE REWRITE WOULD
ADD 3 INCHES TO THE INTERRECORO GAP UNTIL "GOOD" TAPE WAS REACHED,
PROCEDURE TO MEASURE TIMEI
A.
B.
C.
D.

E.
9.1t

TAPE IS NOT AT BOT
INITIALIZE BYTE RECORD COUNTER AND CURRENT MEMORY ADDRESS
REGISTER.
ISSUE WRITE WITH XIRG FUNCTION, 800 BPI, SET wGOw.
MONITOR CURRENT MEMORY ADDRESS REGISTER TO DETERMINE WHEN
2ND BYTE IS OUTPUT.
THE TIME FROM "GO" ·UNIT 2ND BYTE IS OUTPUT IS "WRITE WITH
XIRG".

READ rRO~ BOT
THE FIRST RECORD WRITTEN ON TAPE IS SUPPOSED TO BE AT LEAST 6
INCHES FROM THE BOT MARKER. IN THE EVENT THAT THIS CONDITION
WASNjT MET IT IS STILL DESIREABLE TO READ THE RECORD, READ FROM
80T IS THE TIME FROM WHEN A READ FUNCTION IS ISSUED UNTIL THE
2ND BYTE IS INPUT.
PROCEDURE TO MEASURE TIMEI
A.
B.
C.
D.
E.
F.

THE RECORD THAT WAS WRITTEN JUST orr BOT DURING "WRITE
START" (REFERENCE 9.10) IS USED.
TAPE IS REWOUND TO BOT
INITIALIZE BYTE RECORD COUNTER AND CURRENT MEMORy ADORESS
REGISTER.
ISSUE READ FUNCTION, 900 BPI, SET "GO".
MONITOR CURRENT ME~ORY ADDRESS REGISTER TO DETERMINE WHEN
2ND BYTE IS INPUT.
THE TIME FROM wGO" UNTIL 2ND BYTE IS INPUT IS "READ FROM
BOT".

B-49

05-AUG.76

9.12

16141

PAGE 74

WRITE [OF.
TO WRITE AN END OF FILE MARK IT IS NECESSARY FOR TAPE TO
MOVE 3 INCHES BEFORE WRITING. IN THAT RESPECT IT IS SIMILAR
TO WRITING A RECORD WITH EXTENDED INTERRECORD GAP, HOWEVER, AN
EOf MARK CORRESPONDS TO A 1 BYTE RECORD. THE TIME SHOULD BE
SLIGHTLY LARGER THAN "WRITE XIRG".
PROCEDURE TO MEASURE TIME,
A.
B.
C.
D.
E,
r.
G~

9.13

TAPE UNIT IS REWOUND TO 80T.
INITIALIZE BYTE RECORD COUNTER AND CURRENT MEMORY ADDRESS REGISTER.
ISSUE WRITE FUNCTION, 800 BPI, SET "GOR.
WAIT rOR "CU READY" AND THEN "TU READY· TO BECOME A 1,
ISSUE WRITE EOF FUNCTION, 800 BPI, SET "GO",
WAIT FOR "TU READY" TO BECOME A 1.
THE TIME FROM "GO" UNTIL "TU READY" IS "WRITE EOr",

EOR TO EOF SPACE TIME
EOR TO Eor SPACE TIME IS THE TIME NEEDED TO MOVE TAPE FROM THE
END OF A RECORD TO AN END OF FILE MARK WRITTEN AFTER IT. THE
PROCEDURE USED TURNS OUT TO BE A TEST or THE WRITE AND ERASE HEAD
POLARITIES. IF THE TIME PRINTED IS EQUAL TO ZERO IT IS AN INDICATION THAT THE EOF WAS NOT FOUND WHEN "TU READy" BECAME A 1.
THIS COULD INDICATE ONE OR MORE OF THE FOLLOWING PROBLEMS.
1.
2.
3.
4.
5.

ERASE HEAD POLARITY REVERSED.
ERASE HEAD TURRENT NOT SUFFICIENT TO rULLy SATURATE TAPE.
ONE OR MORE OF WpITE HEAD TRACKS POLARITY REVERSED.
ONE OR MORE SENSITIVE READ AMPLIFIERS.
WRITE Eor FUNCTION DIDN'T REALLY WRITE AN Eor MARK.
OTHERWISE "EOP TO EOF SPACE TIME" SHOULD BE SLIGHTLY LARGE~
THAN "WRITE EOF".

PROCEDURE TO MEASURE TIMEt
A.
B.

D,
E.
F.
G.

A PECORD AND EOF WAS PREVIOUSLY WRITTEN FROM BOT FOR "WRITE
EOF" (REFERENCE 9.14).
TAPE IS REWOUND TO BOT.
REWRITE RECORD OVER PREVIOUSLY WRITTEN RECORD.
BAC~SPACE OVER RECORD JUST WRITTEN,
SET BYTE RECORD COUNTER TO SPACE 2 RECORDS.
ISSUE SPACE FORWARD FUNCTION, SET RGO".
WAIT FOR BYTE RECORD COUNTEP TO INDICATE THAT 1ST RECORD
HAS SEEN SPACED OVER THEN MONITOR "TU READY" UNTIL IT 8ECOMES
A 1. AFTER "TU READY" CHECK TO S~E IF "EOr" IS A 1
IN STATUS REGISTER. IF "EOF" NOT SET THEN ZERO TIME COUNTER.
TIME FROM BYTE RECORD COUNTEp ~91 UNTIL "TU READY" IS "EOR
TO EOF SPACE TIME".

B-50

05-AUG-76

9,14

16t47

PAGE 75

SPACE SHUTDOWN
SPACE SHUTDOWN IS THE AMOUNT OF TIME NECESSARY TO
CONTINUE MOVING TAPE AFTER A RECORD IS SPACED OVER IN THE
FORWARD DIR~CTION FOR THE SAME REASONS AS "READ SHUTDOWN"
PROCEDURE TO MEASURE TIMEt
A,
B,
C,

SPACE FORWARD FUNCTION USED TO TIME "EOR TO EOr SPACE TIME"
IS USED,
ArTER "EOr" BECOMES A 1, INDICATING THE END or THE
RECORD (EOF), MONITOR "SETTLEDOWN" UNTIL IT BECOMES A 1,
THE TIME FROM "EOF" UNTIL "SETTLEDOWN" IS "SPACE
SHUTDOWN",

B-Sl

9.15

ONE INCH DATA TIME
ONE INCH OF DATA, 8~9 BYTES (ALSO 556 AND 290 IF 7 CHANNEL
UNIT), IS WRITTEN AND TIMED TO DETERMING IF TAPE IS MOVING AT
PROPER SPEED,
PROCEDURE TO MEASURE TIMEt

9.16

INITIALIZE BYTE RECORD COUNTER AND CURRENT MEMORY ADDRESS,

ISSUE WRITE FUNCTION, 800 BPI (OR 556, OR 200), SET "GO".

WAIT FOR CURRENT MEMORY ADDRESS REGISTER TO INDICATE 2ND
BYTE IS OUTPUT AND THEN MONITOR BYTE RECORD COUNTER UNTIL
EQUAL TO ZERO.

TIME FROM 2ND BYTE OUTPUT UNTIL BYTE RECORD COUNTER
IS "ONE INCH DATA TIME"

FUNCTIONS AT 556 BPI
ALL OF THE PREVIOUS TESTS USED THE DENSTIY OF 80~ BPI, IF A 7
CHANNEL DRIVE IS SELECTED IT IS USEFUL TO RUN SEVERAL OF THE TEST8
AGAIN UsING DENSITY OF 556 BPI. REFERENCE THE PROPER PARAGRAPHS
FOR A DESCRIPTION OF EACH TEST.

9.17

FUNCTIONS AT 200 BPI
SAME AS ABOVE. REFERENCE 9.17, "FUNCTIONS AT 556 BPI"

B-52

10.

STATUS A/IID COMMAND REGISTER BIT ASSIGNMENTS
COMMAND REGISTER

F:RROI<

14
13
12

DEN 8
nEN 5
POWER CLEAR

11
10
9

PARITY
I') III ODD
UNIT SEL. BIT 2
UNIT SEL. BIT 1

8
7
6

UNIT SEL. BIT 0
CONTROL UNIT READY
INTERRUPT [NABLE

5
4
3

ADDRESS BIT 17
ADDRESS SIT 16
FUNCTION SIT 2

2
1

FUNCTION BIT
FUNCTION BIT 0
GO

200 BPI 7 TRACK

= 556 BPI 7 TRACK

000

III

001

Ill:

lI:

OFF LINE
IIEAD
010 II! WRl'fE
011 II WRITE EOF

STATUS

ILLEGAL COMMAND CILe)

13
12

END OF FILE (EOF)
CYCLICAL REDUNDANCY ERROR (CRE]
PARITY ERROR (PAE)

it
10
9

BUS GRANT LATE (BGL)
END OF TAPE (EOT)
RECORD LENGTH ERROR (RLE)

8
7
6

BAD TAPE ERROR (BTE)
NON EXISTENT MEMORY (NXM)
SELECT REMOTE (SELR)

5
4

BEGINNING OF TAPE (BOT)
7 CHANNEL (7CH)
SETTLE DOWN (SOWN)

2
1
o

WRITE ~OCK (WRL)
REWIND STATUS (RWS)
TAPE UNIT READY (TUR)
.ENOR

B-53

= 800 BPI 7 TRACK

tl :: R00 BPI 9 TRACK

EVEN

100 :: SPACE rORwARD
101 :: SPACE REVERSE
110 = WRITE XlRG
111 :: RF.WIND

05.AUG.76

16.50

PAGE 59

IDENTIfICATION
PMDUCT CODE,
PRODUCT NAME.

TMA,B-1t/TUte,N,w SUPpLEMENTAL INST, TEST

PROGRAM DATE.

AUGUST 1976

MAINTAINER.

DIAGNOSTIC ENGINEERING

AUTHOR.

R. B. BARNES

REVISED BYa

RON PLATUKIS/R. SOLER

THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT
NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION. DIGITAL EQUIPMENT CORPORATION ASSUMES
NO RESPONSIBILITY FOR ANY ERRORS THAT MMAY APpEAR IN THIS DOCUMENT
THE SOFTWARE DESCRIBED IN THIS DOCUMENT IS FURNISHED UNDER A
LICENSE AND MAY ONLY BE USED OR COpIED IN ACCORDANCE WITH THE
TERMS or SUCH LICENSE.
DIGITAL EQUIpMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR
THE USE OR RELIABILITY OF ITS SOFTWARE ON EQUIPMENT THAT IS
NOT SUPPLIED BY OIGITAL.
COPYRIGHT eC) 1975, 1976 BY DIGITAL EQUIPMENT CORPORATION

B-55

0S.AUG.76

16150

PAGE 60

TABLE or CONTENTS
PA.RAGRAPH

SUBJECT

PAGE

1•

ABSTRACT
REQUIREMENTS
LOA.DING PROCEDURE
STARTING PROCEDURE
SWITCH SUTINGS
ERROR PRINTOUT
OPERATION
TEST DESCRIPTION
LISTING

3
3
1
3
4
5

2.
3.
4.

S.
6.
7.
8.

B-56

6
7

ABSTRACT
THIS PROGRAM IS INTENDED TO BE USED IN ADDITION TO
TNE TMA,B~lt INSTRUCTION TEST (MAINDEC.lt-DZTMA)
TO COMPLETE TESTING OF THE MAG TAPE eONTROLLER.
THE PROGRAM CONSISTS OF ONLY FOUR (4) TESTS WHICH
CHECK ONLY THE TMA,S-it FEATURES OF DATA TRANSFER AT 000
BYTE STARTING ADDRESS AND OPERATION INCOMPLETE TIME OUT.

A. ANY PDP.ii PROCESSOR
B. 4K OF CORE
C. CONSOLE TTY
D. TMA-it OR TMB-il TAPE CONTROLLER (ONLY)
E. t-o TAPE TRANSPOR~S (TU10,N.W)
3.

...-... .......-.

LOADING PROCEDURE
~

A. USE STANDARD PROCEDURE FOR LOADING BINARY pAPER TAPE
B. THIS PROGRAM IS LOADABLE AND CHAINA8LE pER XXDP, ACTtl,
AND SLIDE, IN OK OF MEMORY. (SEE 7.1)
4.

...-....-.....

STARTING PROCEDURE
.~

THERE ARE TWO (2) STARTING ADDRESSES THAT MAY BE USED,
200(8) AND 210(8).
STARTING AT THIS ADDRESS WILL CAUSE A PROGRAM
IDENTIFICATION HEADER TO BE PRINTED AND ALSO A
REQUEST FOR ENTRY OF THE UNIT NUMBER (TAP~ TRANspORT SELECT).
THE DEFAULT SELECTION or UNIT ZERO (0) IS DISPLAYED, AND
MAY BE CHANGED TO ANy NUMBER (0.7) OR UNCHANGED BY
TYPING THE DESIRED NUMBER OR A CARRIAGE RETURN.
IF THE SELECTED UNIT IS NOT AVAILABLE, A MESSAGE WILL
BE PRINTED SO STATING, AND THE UNIT SELECT REQUEST REPEATED.
STARTING AT THIS ADDRESS WILL NOT PRINT THE HEADER OR THE
UNIT SELECT REQUEST AND IS INTENDED AS A RESTART ADDRESS ONLY.

B-57

SWITCH SETTING
•..•..•..•.
--...... ..
CONSO~E

ALL SWITCHES EXCEPT 3-9 ARE USED AND THE NORMAL, OR DEFAULT, RUN
IS DONE WITH ALL SWITCHES SET TO ZERO (A).
ALL SWITCHES ARE DyNAMIC AND MAY aE CHANGED AT ANY TIME.
SWl51
SWl41
SW131
SWl21
SWlll
SW101
SW9.31
SW2-01
5,1

i-HALT ON E~RO~
hCONTINUE
i-LOOP ON ERROR (SCOPE)
e_CONTINUE
i_INHIBIT ERROR TYPE OUT
e-PRINT ALL E~~ORS
l_INHIBIT ITERATION**CFIRST PASS IS SINGLE ITERATION)**
0_ITERATE EACH TEST ITS ASSIGNED AMOUNT
l_CONTINUOus CYCLE
e-HALT AT END or PASS
t_HALT AT END or CURRENT TEST
0_CONTINUE
NOT USED
SELECT INDIVIDUAL TEST C1-4)** 00 • 00 ALL TESTS

THIS PROGRAM HAS BEEN MODIFIED TO RUN ON A PROCESSOR WITH OR wITHOUT
A HARDWARE SWITCH REGISTER. WHEN FIRST EXECUTED THE PROGRAM TESTS
THE EXISTENCE OF A HARDWARE SWITCH ~EGISTER. IF NOT FOUND A
sOFTWARE SWITCH REGISTER LOCATION (SWREG-LOC, 176 ) IS DEFAULTED TO,
IF THIS IS THE CASE, UPON EXECUTION THE CONTENTS OF THE SWREG ARE
DUMPED IN OCTAL ON THE CONSOLE TTY AKD ANY CHANGES ARE REQUESTED
(IE)

SWR~XXXXXX

NEW_

POSSIBLE RESPONSES A~EI
1.

eCR>
6 DIGITS 0.7

eLF>

IF NO CHANGES ARE TO BE MADE
TO REPRESENT IN OCTAL THE NEW SWITCH REGISTER
VALUE ,LAST DIGIT FOLLOWED BY eCR>.
TO ALLOW REENTERING VALUE Ir ERROR IS COMMITTED
KEYING IN SWREG VALUE,
ONLY VALID FOR ACT_II SYSTEMS_DO NOT USE

BUILT INTO THE PROGRAM IS THE ABILITY TO DyNAMICALLY CHANGE THE
CONTENTS OF SWREG DURING PROGRAM EXECUTION, By STRIKING ~G
(CNTL G) ON CONSOLE TTY THE OPERATOR SETS A REQUEST FLAG TO CHANGE
THE CONTENTS OF SWREG, WHICH IS PROCESSED IN KEY AREAS OF THE PROGRAM
CODE (IE) ERROR ROUTINES, AFTER HALTS END or pASS, AND OTHER
APPLICABLE AREAS.

B-58

THERE ARE THREE (3) TYPES or ERROR PRINTOUTS WHICH MAY
APPEARi STATUS ERROR, DATA ERROR, pOSITION ERROR.
ANy READ, WRITE, OR SpACE OPERATION WHICH
RESULTS IN SOME SAD STATUS CSIT 15 OF MTC),
OR UNEXPECTED 8US ADDRESS, OR INCORRECT
BYTE COUNT, WILL BE PRINTED,
ANy READ OpERATION WHICH RESULTS IN UNEXPECTED
DATA WILL BE PRINTED.
C. POSITION ERROR I

ANY SPACE OR REWIND OpERATION REsULTING IN
UNEXPECTED STATUS WILL BE PRINTED.

1. THE FOLLOWING EXAMPLE SHOWS A TYPICAL STATUS ERROR.
TEST18 WRITE FROM ODD BYTE
WRlTE Ej:lROj:l
THIS PRINT SHOws THAT WHILE EXECUTING
TEST 1 ON UNIT 2 AT 800 BPI, A WRITE
MTSI 11'101
PARITY ERROR OCCURED. THE BYTE COUNT
MTC I 161204
IS ZERO AS IT SHOULD BE AND THE CURRENT
"'TBe 8 0
MTCAI 6003 600]
ADDRESS IS AS EXPECTED.
2. THE FOLLOWING EXAMPLE SHOWS A TYPICAL DATA ERROR.

TEST 21 READ TO ODD BYTE
DATA ERROR
THIS PRINT SHOWS THAT A SINGLE BIT WAS
PICKED UP IN 80TH CHARACTER NUMBER ZERO
CN I 0
CiS 00000000
(0) AND CHARACTER NUMeER THREE (3).
51

0iI'J00000

CN a 3
Gr 000001'11 1
8. 0111100011

3. THE FOLLOWING EXAMPLE SHOWS AN

TEST4a opr TOO LONG
REWIND ERRORI NO BOT

B-59

E~ROR

DURING A REWIND OPERATION,

OPERATION
•.•.•.•..
THE PROCEDURES FOP OPERATING THIS PROGRA~ ARE QUITE
SIMPLE AND REQUIRE bNLY A FEW STEP.I
1. LOAD ADDRESS 200 OR 210
2. SET SWICHES FOR DESIRED TEST SEQUENCE
3. PRESS START
ALL CONSOLE SWITCHES ARE DyNAMIC AND MAY BE CHANGED
AT ANY TIME. THE NORMAL OPERATING SEQUENCE JS ALL SWITCHES
DOwN (0). THE PROGRAM WILL TAKE APPROXIMATELY 1.25 MINUTES
TO RUN, HOWEVER, IF ITERATIONS ARE INHIBITED (SW11=1), THE
PROGRAM WILL RUN IN ABOUT .75 MINUTES. THE END OF PASS
IS NOTED SY A PRINTOUT STATING END or PASS AND THE NUMBER OF
THAT PASS.
SINGLE TEST SELECTION I (SW0-SW)

7.1

WHEN SW0-3 ARE SET TO ZERO (0" THE SCHEDULAR WILL
EXECUTE ALL TESTS (1-4) IN SEQUENCE AS A SINGLE pASS.
IF SW0.3 ARE SET TO SOME NUMSER BETWEEN 1 AND 4,
THEN THAT PARTICULAR TEST WILL BE EXECUTED CONTINUOUSLY.
THE PROGRAM MAY BE STOPPED AT THE END OF THE CURRENT
TEST (EITHER IN SEQUENCE OR SINGLE TEST MODE) BY SETTING
SWITCH TEN (SW10) TO A ONE (1). yOU MAY SELECT TF.ST
NUMBERS IN ANY ORDER (UP OR DOWN) BECAUSE EACH TEST
IS SELF CONTAINED.
CHAIN MODE RUNS A SINGLE PASS ON DRIVE ~ WITH 7 OR 9 TRACK
AT THE STANDARD UNIBUS ADDRESS.

B-60

.... •.•.......

TEST DESCRIPTION
~

TE5T11 WRITE fROM

DO~

BYTE

THE PURPOSE Of THIS TEST IS TO ASSURE THAT DATA MAY BE
TRANSFERRED FROM MEMORY TO TAPE STARTING fROM AN ODD
8YTE ADDRESS. THF TEST WILL WRITE A SIX (6) BYTE RECORD
FROM AN ODD ADDRESS (WDATA+1) AND READ THAT RECORD
BACK INTO AN EVEN ADDRESS (RDATA). NO STATUS ERROR SHOULD
OCCUR, AND THE READ DATA SHOULD BE POSITIONED PROPERLY.
THE RECORD IS SIX BYES LONG, EACH BYTE IS ITS NUMBER (0,1,2,3,4,5)
TE5T21 READ TO ODD BYTE
THE PURPOSE OF THIS TEST IS TO ASSURE THAT DATA ~AY BE
TRANSFERRED FROM TAPE TO MEMORY STARTING AT AN ODD BYTE
ADDRESS. THE PROCEDURE IS THF. SAME AS IN TEST ONE (1),
EXCEPT THAT THE WRITE IS FROM AN EVEN ADDRESS (WOATA)
AND THE READ IS TO AN ODD ADDRESS (RDATA+l).
TEST3& oPt TOO LONG

(OPl

BJT 8 or MTS)

THE PURPOSE OF THIS TEST IS TO ASSURE THAT THE OPl TIMER
WILL SHUTDOWN TijE DRIVE BEFORE THIRTY rIVE FEET OF BLANK
T~PE IS PASSED.
THE PROCEDURE Is TO pERFORM A WRITE WITH
IRG, BACKSPACE, wRITE wITH IRG 105(10) TIMES IN ORDER
TO ERASE 35 FEET Of TAPE. AFTER REWIND, ISSUE A READ
COMMAND AND OpI SHOULD TIME OUT BEfORE THE FIRST RECORD
(15 FEET DOWN TAPE) IS rOUND. THE NOMINAL VALUE FOR OPI
IS SEvEN SECONDS ('SEC) OR ABOUT TWENTY-SIX FEET (26 FT)
OF TAPE. THIRTY.FIVE FEET or TAPE REFLECTS THE MAXIMUM
TOLERANCE FOR OPI.
T£5T41 OP! TOO SHORT

(OPl

BIT 8 or MTS)

THE PURPOSE or THIS TEST IS TO ASSURE THAT THE OPI TIMER
WILL NOT SHUTDOWN THE DRIVE BEFORE SIXTEEN FEET (10 FT)
or BLANK TAPE IS PASSED. THE PROCEDURE IS THE SAME
AS IN TEST THREE (3), HOWEVER OPl IS NOT EXPECTED BEFORE
THE FIRST RECORD IS rOUND (16 FEET DOWN TAPE), THE
SIXTEEN FEET or TAPE RELECTS THE MINIMUM TOLERANCE FOR OpI.
9.

LISTING

B-61

IDENTIFICATION
PRODUCT CODES
PRODUCT NAMES
PROGRAM DATES

AUGUST 1976

MAINTAINERI

DIAGNOSTIC ENGINEERING

AUTHORI

G. B. JOHNSON

REVISED BYa

RON PLATUKIS/R. SOLER

THE INfORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT
NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION, DIGITAL EQUIPMENT CORPORATION ASSUMES
NO RESPONSI8ILITY rOR ANY ERRORS THAT MMA! APpEAR IN THIS DOCUMENT
THE SOFTWARE DESCRIBED IN THIS DOCUMENT IS fURNISHED UNDER A
LICENSE AND MAY ONLY BE USED OR COPIED IN ACCORDANCE WITH THE
TERMS or SUCH LICENSE.
DIGITAL EQUIpMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR
THE USE OR RELIABILITY or ITS sOFTWARE ON EQUIPMENT THAT IS
NOT SUPPLIED By DIGITAL.
COPYRIGHT ee) 1974, 1976 BY DIGITAL EQUIpMENT CORPORATION

B-63

05-AUG.76

16151

I TABLE

PAGE 2

OF CONTENTS

PARAGRAPH

SUBJECT

PAGE

1.
2.
3.
4.

ABSTRACT
REQUIREMENTS
LOADING PROCEDURE
STARTING PROCEDURE
CONTROL SWITCHES
OPERATION
PROGRAM DESCRIPTION
LIsTING

5,
6.
7.
8.

B-64

]

3
3
1

4
6

.... ...
ABSTRACT
~

THIS PROGRAM IS INTENDED AS A BRUTE fORCE ROUTINE
TO EXECUTE AN OPERATION OR SERIES or OPERATIONS, CONTINUOUSLY
REGARDLESS or THE RESULTS or THE OPERATION.
THIS UTILITY DRIVER WILL ALLOW AN OPERATOR
TO EXECUTE ANYTHING DESIRED IN ANY ORDER. THERE ARE
NO ERROR CHECKS OR PRINTOUTS MADE, AND ANY VARIATION
fROM PRESET SEQUENCES AND VALUES ARE MADE BY
CHANGING THE APPROPIATE MEMORY LOCATIONS.
THIS PROGRAM IS NOT ELIGABLE fOR CHAIN MODE,
2.

REQUIREMENTS
••••••••••••

2.1

HARDWARE I
A. ANY POP-i1 PROCESSOR
B. TM,A,e-l1 TAPE CONTROLLER
C. AT LEAST ONE TU10,N,W MAG TAPE DRIVE

2.2

STORAGES
THIS PROGRAM REQUIRES AT LEAST 1K or CORE

LOADlNG PROCEDURE I
USE STANDARD BINARY LOADING PROCEDURE

STARTING PROCEDURE

.••.......•...•...

THE PROGRAM IS ALWAYS STARTED AT LOCATION 200 (8)
5.

... ... ......-..-...
CONT~OL
~.-

SWITCH SETTINGS (LOC. 176)
~

BIT 01 1=STOP ArTE~ EACH OPERATION
0aPROCEED
BIT 11 i.STOP AT THE END or THE OPERATION SEQUENCE
0aPROCEED

B-65

..-.. ..
OPERATION
~-

T~E PROGRAM OPERATION IS QUITE SIMPLE, BUT DOES
REQUIRE THE OPERATOR TO HAVE KNOWLEDGE or THE
MAG TAPE SYSTEM AS OPERATED ON THE TMA-l1 OR TM-ll
CONTROLLER. THE OPERATnR MUST BE ABLE TO D!CIDE
WHICH SEQUENCE or OPERATION IS REQUIRED, AND
WHAT VALUES TO ASSIGN TO THE VARIOUS PARAMETERS
REQUIRED TO EXECUTE THEM. THE OPERATION SEQUENCE
IS SET UP BY LOADING A TABLE WITH THE FUNCTION
CODES or THE DESIRED OPERATIONS AND SETTING THE
NUMBER OF OPERATIONS IN A COUNTER. THE PROGRAM IS
SET UP TO DO A WRITE OF TWENTY (20) rRAMES OF ALL
O~ES DATA TO TAPE UNIT ZERO (0)
WITH
A DENSITY or 800 BPI IN A NINE TRACK DRIVE.
THE DATA ADDRESS IS 3000 (8). THE OPERATION SE~UENCE
IS SET TO DO A SINGLE WRITE. lr LOADED AND STARTED
AT 200(9) WITH NO CHANGES MADE AND Loe, 116
SET TO A ZERO (0), THIS OPERATION wILL BE EXECUTED
CONTINUOUSLY.
THE FOLLOWING Is THE LIST OF PARAMETERS WHICH MAY
BE VARIED AND A DESCRIPTION or EACH ALONG wITH THEIR
CORE LOACATION8

pARAMETER

LOCATION

OESCRIPTION

CONTROL SETTINGS

176

PRESET FOR CONTINUOUS OPERATION

1 M,A,Sell ADDRESS

600

ADDREsS OF TM,A,Beil

UNIT DESCRIPTION

100

SET SELECTED SLAVE NUMBER (0.7) IN BITS 8.9,10
SELECT PARITY IN BIT 11 (0z0DD 1=EVEN)
SELECT DENSITy IN BITS 13,14

BYTE COUNT

102

SET NUMBER or BYTES

READ ADDRESS

704

SET DESIRED ADDRESS FOR START or READ BUFFER.

WRITE ADDRESS

706

SET DESIRED ADDRESS FOR START or WRITE BurFER.

SPACE COUNT

710

sET NUMBER OF RECORDS TO SPACE ON SPACE COMMAND
IN TWO'S COMPLEMENT.
NOTEI WHEN SPACING MuLTIPLE RECORDS INSURE THAT
SUFFICIENT TIME Is ALLOWED BY sETTING THE
READY MULTIPLIER TO THE NUMBER OF RECORDS SPACED.

(THE FIRST REGISTER ADDRESS I Mrs)

pER RECORD

IN TWOS' COMPLEMENT

B-66

READY DELAY

712

THIS DELAY VALUE IS USED By THE PROGRAM TO ESTABLISH
A MAXIMUM TIME TO AWAIT THE COMPLETION or AN OPERATION
BErORE PROCEEDING TO THE NEXT

READY MULTIPLIE~

714

IF THF. VALUE SET INTO 712 DOES NOT ALLOw ENOUGH TIME,
INCREASE THE SUE or THE MULTIPLIER, EACH INCREMENT or
THE MULTIPLIER WILL CAUSE THE 712 DELAY TO BE EXECUTED
THAT MANY MORE TIMES.

OPERATION DELI!

716

THIS DELIY IS USED TO ALLOW FOR SOME AMOUNT or
TiME 8ETW~EN THE EXECUTION or EACH OPERATION. IT IS
LOADED AND USED JUST AS IN THE READY DEtAY(712)

OPER MULTIPLIER

720

THIS IS USED JUST AS THE READY DELAY MULTIPLIER(714)

OPERATION NUMBER

722

THIS IS THE NUMBER or OPERATIONS TO BE PERFORMED
IN A SEQUENCE AND SHOuLD REfLECT THE NUMBERS
or OPERATIONS SET INTO THE OPERATION TABLE.

OPERATION TABLE

724~754

THIS TABLE (CONSISTING or 15 LOCATIONS) IS TO BE
LOADED WITH THE fUNCTION CODES rOR EACH OPERATION
TO BE PERFORMED IN SEQUENCE. THE NUMBER Of ENTIRfS
MAY BE fROM ONE (1) TO FIrTEEN (15). MAKE SURE THAT
THE NUMBER Of fUNCTION CODES SET IN THE TABLE IS
REfLECTED BY THE NUMBER IN LOCATION 722 (OPNUM)

Qj"OffLINE
illllREAD
21111WRITE
)IIIWRlTE Eor
-i.SPACE fORWARD
S.SPACE RFo:VERSE
&=WRITE WITH EXTENDED IRG
'.REWIND
O€NSITY (BITS 13,14 or UNIT DEsCRIPTION)
BPI
BPI
02 .. 800 BPI
011111l0Pl BPI
00111200
0111556

TIUCK
....
7 TRACK
....... 7 TRACK
9

TRACK

PARITY (BIT 11 Of UNIT DESCR! PTI ON)

l=EVEN PARITY
0.000 PARITY
6.4

UNIT SELECT (BITS

8,9~10

Of UNIT DESCRIPTIONS)

SET TO DESIRED UNIT NUMBER CQJm1)

B-67

PROGRAM DESCRIPTION
.•.•....••.........
IN ORDER TO MAINTAIN TNE CONTINUOUS EXECUTION OF
THE OPERATIONS DESCRIBED THE PROGRAM IS ORGANIZED AS
FOLLOWS.
START
INITIALIZE THE TH,A,S-1!
SET UP TAPE PARAMETERS (DENSITY, PARITY, BYTE COUNT, DATA ADDRESS)
SELECT DEVICE TO TEST (UNIT NUMBER)
EXECUTE OPERATION (SET FUNCTION fROM OP TABLE AND SET GO.!)
AWAIT END or OPERATION (TAPE UNIT READY)
STOP If LOC. 176 BIT 0,.1
DO OPERATION DELAY (OP DELAY)
STOP IF LAST OPERATION IN SEQUENCE AND LOC 176 BIT 1,-1
POINT TO NEXT FUNCTION CODE IN OP TABLE
JUMP BACK TO START
FLOW I

• ENOR

START I
HOUSEKEEPING
INITI
CLEAR TM,A,a e l1
SET UPI
SET UP REQUIRED REGISTERS
EXECUTE.
SET FUNCTION AND GO=l
AWAIT END,
LOOP ON TUR.0 AS LONG AS ALLOWED BY READY DELAY
STOPf
IF AIT 01-1 (LOe 176)
DELAY,
PER Op DELAY
E~D or SEQUENCE? IF NOT JUMP TO START
STOPI
If BIT 1.-1 (LOC 176)
JUMP TO START
RESTART SEQUENCE

LISTING
....
-- .

B-68

APPENDIX C
FLOW DIAGRAM GLOSSARY

C-l

FLOW DIAGRAM GLOSSARY

x = Description of an event or action (lower case).

The signal level WRITE is asserted.

The signal level WRITE is negated.

If condition or signal is true flow follows

YES branch, otherwise flow follows NO branch.

A flip-flop is set asserting WRITE.

A flip·flop is reset negating WRITE.

Delay. x = amount of delay or
delay range.

On page connector.

Off page connector.

C__)

Beginning or ending point of a flow

diagram
11·4781

C-2

APPENDIX D
M8926 INTERFACE SIGNALS

H8800

H851 EDGE

TERMINATOR (3)

CONNECTORS

PINA

Figure D-l

M8926 Input/Output Connectors

D-l

8110-5

Table D-l

M8926/TMBll Interface Signals

Connector

Signal

Connector

Signal

JBl
JCl
JDl
JEl
JFl
JHl
JJI
JJ2
JKl
JK2
JLl
JL2
JMl
JM2
JNl
JPl
JP2
JRl
JR2
JSl
JT2
JU2
JV2

CWFMK
CPEVN
CWDR
CSET
CINIT
CREV
CWD7
CWRE
CWD6
CRWD
CWD5
CFWD
CWD4
CWXG
CWD3
CWD2
CDEN5
CWDI
CDEN8
CWDO
CSEL2
CSELl
CSELO

KBI
KCl
KDl
KD2
KEI
KE2
KFI
KF2
KHI
KH2
KJ1
KJ2
KKI
KK2
KLI
KL2
KM2
KN2
KPI
KP2
KRI
KSI
KT2
KU2
KV2

CLRCS
CLRCE
CCRCE
CFMK
CEOT
CRDP
C7CH
CRD7
CSELR
CRD6
CVPE
CRD5
CWRL
CRD4
CBOT
CRD3
CRD2
CRDI
CRWS
CRDO
CCRCS
CWRS
CTUR
CSDWN
CRDS

D-2

Table D-2

M8926jSlave Bus Interface Signals

Connector

Signal

Connector

Signal

A
C
E
H
K
M
P
S
U
W

WDO(SB)
WDP(SB)
WDI (SB)
WD7 (SB)
WD2(SB)
WD6(SB)
REC(SB)
ACCL(SB)
SSl (SB)
LRC STRB (SB)
SS2 (SB)
WD5 (SB)
WD4(SB)
WD3 (SB)
SSO (SB)
SLAVE SET PLS (SB)
EMD (SB)
STOP (SB)

A
C
E
H
K
M
P
S
U
W

RDO (SB)
RDP(SB)
RDl (SB)
RD7 (SB)
RD2 (SB)
RD6 (SB)
RD3 (SB)
RD5 (SB)
RD4(SB)
RSDO(SB)
BOT (SB)
ENDPT (SB)
RWND (SB)
TUR(SB)
WRT CLK (SB)
FWD (SB)
CLOCK (SB)
WRITE (SB)
REV (SB)
MOL (SB)
7CH(SB)
RWS (SB)
WRL(SB)
DENO(SB)
SDWN (SB)
DEN 2 (SB)
DEN 1 (SB)

AA
CC
EE
HH
KK

MM
UU

AA
EE
KK
MM
PP
RR
SS
UU
A
C
y

CC
EE
KK
SS*
UU
*Tied to ground on M8926

D-3

Table D-3 M8926/Host TUIOW Interface Signals
Connector

Signal

Connector

Signal

D2
E2
F2
K2
H2
M2
P2
S2
U2*
V2

WDP(SB)
WD7(SB)
WD6(SB)
LRC STRB (SB)
ACCL(SB)
WD5(SB)
WD3(SB)
SLA VE SET PLS (SB)
INIT PLS (SB)
STOP (SB)

D2
EI
E2
M2
P2
R2
S2
U2
V2

WRITE (SB)
CLOCK (SB)
WRTCLK(SB)
BOT (SB)
MRD4
MRD3
MRD2
MRDI
MRDO

D2*
E2
Hit
H2
K2
M2
P2
R2
S2
U2
V2

DRV CLR PLS (SB)
EMD(SB)
SLAVE BUS ENBL
SSO(SB)
WD4(SB)
SS2 (SB)
SSI (SB)
REC(SB)
WD2(SB)
WDI (SB)
WDO(SB)

D2
P2
S2
U2*
V2

7CH (SB)
DEN 0 (SB)
SDWN(SB)
I RD(SB)
DEN I (SB)

D2t
K2
M2
V2

DEN 2 (SB)
WRL(SB)
RWS(SB)
MOL (SB)

D2
E2
F2
H2
K2
M2
P2
S2
U2
V2

MRDP
MRD7
MRD6
MRD5
RSDO
ENDPT(SB)
RWND(SB)
TUR (SB)
FWD (SB)
REV (SB)

*Tied to +3 V on M8926
tTied to ground on M8926

D-4

APPENDIX E
TMBll/TU10W DATA SHEETS

E-l

7475 4-BIT BISTABLE LATCH
The 7475 latches are used for temporary storage of binary information. Information present at a data
(D) input is transferred to the R output when the clock is high, and the R output will follow the data
input as long as the clock remains high. When the clock goes low, the information present at the data
input at the time of the transition is retained at the R output until the clock is permitted to go high.
Input ENBI is the clock input for data inputs DO and D1. ENB2 is the clock input for data inputs D2
and D3.

7475

R0(1)

RN (1)
OUTPUTS

ON
INPUTS

CLOCK
INPUTS

R0(0)
3

RI (1)
Rl (0)

R2 (1)
R2(0)

R3 (1)
R3(12))

0
1

RO
ENB1
R1

R2
ENB2
R3

vee PIN 5
GNO PIN 12

NOTE:

1. RN (0) Outputs = inverted RN ( 1) outputs.

2. ENBI and ENB2 clock on negative going edge.

IC-7475

E-2

7485 4-BIT COMPARATOR
The 7485 performs magnitude comparison of straight binary or straight BCD codes. Three fully
decoded decisions (A > B, A < B, A = B) about two 4-bit words (A,B) are made and externally
available at three outputs.

7485
01
15

14
13
11

12
09
10

B3
A3
05

A>B

A;B 06
07
A<B

A2
B1
Al
B0
Art;
IN>

IN;

IN<

104

103

102

vee; PIN 16
OND; PIN 08

TRUTH TABLE
COMPARING
INPUTS

CASCADING
INPUTS

OUTPUTS

A3, B3

A2, B2

A1, B1

AD, BO

IN>

IN <

IN =

A>B

A<B

A=B

A3>83
A3< 83
A3 = 83
A3 = 83
A3 = 83
A3 = 83
A3 = 83
A3 = 83
A3 = 83
A3 = 83
A3= 83

x
x

x
x
x

X
X

L
H
L

x
x
x

X
X
X
X
X
X
X
X
L
L

A2> 82
A2 < 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82

x
X
A1 > 81
A1 <81
A1 = B1
A1 = 81
A1 = 81
A1 = 81
A1 = 81

X
X
X

x
AO> 80
AO< 80
AO= 80
AO= 80
AO= 80

L
L

X
X
L

L
L

L
L
L
L
L
L
L
L
L
L

L
H

NOTE: H = high level, L = low level, X = irrelevant

IC·7485

E-3

8251 4 TO 10 DECODER
8751 TRUTH TABLE
INPUT

f OUTPUT

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0

1 = High

0= Low

01
BCD
INPUTS

DECIMAL
OUTPUT

02
8251

11
15

vec =PIN 16
GND=PIN08
IC-8251

E-4

8266 2-INPUT, 4-BIT DIGITAL MULTIPLEXER
The multiplxer is able to choose from two different input sources, each containing 4 bits: A = (AO, AI,
A2, A3), B = (BO, Bl, B2 B3). The selection is controlled by the input SO, while the seccond control
input, S 1, is held at zero.

8266
B3

10
05

A2
Bl

06
02

TRUTH TABLE
SELECT LINES

OUTPUTS

511'

Fn(O. 1. 2. 3)

VCC=PIN16
GND= PIN 0B

,-S0

(09)

(02)

(01)

(06)

A2
(05)

(10)

(11)

(15)

I
I
I

(14)

(1217)

I
I
L ____

---

(03)
F0

(04)
F1

I
_J

(12)
F2

F3
IC- 8266

E-5

8281 4-BIT BINARY COUNTER/STORAGE ELEMENT
The 8281 Binary Counter may be connected as a divide-by-two, eight, or sixteen counter. The counter
has a strobed parallel entry capability so that the counter may be set to any desired output state. A "1"
or "0" at a data input will be transferred to the associated output when the LD input is put at the "0"
level. It has a reset (CLR) input which is common to all four bits. A "0" on the CLR line produces "0"
at all four outputs. The counting operation is performed on the falling (negative-going) edge of the
input clock pulse.

Ri1J (1 )

R1 (1)

R2(1 )

(5)

(9)

(2)

R3(1 )
(12)

ClK 0 0 - - - - - - - 1 - - - 0 1
(8)

K
Sd

Q
Rd

K
Sd

C~1o_-----4----+---+~

(6)

lD(l)

ClR
(13)
(4)

(10)
D1

11
03

R3 (1 )

R 2(1 )

D2
D1

D(;l
CLR

C~l

TRUTH TABLE
COUNT
ICLKIil)

R 1(1)

R(IH 1)

0
1
2
3
4
5

ClK(;l

6
7
8
9

VCC = PIN 14
GND = PIN 07
13

(11)

8281
10

(3)

10
11
12
13
14
15

R011l R1(1) R2111 R3(11

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

00
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

01
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

02
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

03
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

NOTES:

Output Rill 1) connected to input
CLK1.

H = high; L = low

IC-8281

E-6

9301

1 OF 10 DECODER

The 9301 Decoder accepts four active HIGH BCD inputs and provides 10 mutally exclusive active
LOW outputs. The logic design of the 9301 ensures that all outputs are HIGH when binary codes
greater than nine are applied to the inputs. The most significant D3 input produces a useful inhibit
function when the 9301 is used as a 1 of 8 decoder.

o.ll 01 02 03
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

TRUTH TABLE
fll f1 f2 f3 f4
L H H H H
H L H H H
H H L H H
H H H L H
H H H H L
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H

H = HIGH Voltage Level
L = LOW Voltage Level

+ 5V PIN 16
f5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H

f6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H

f7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H

9301

GNO PIN 08

f8 f9
H H
H H
H H
H H
H H
H H
H H
H H
L H
H L
H H
H H
H H
H H
H H
H H

0(IJ

f(IJ

(03)
f5

(04)
f6

(05)
f7
Ie -9301

E-7

74157 QUAD 2 TO 1 MULTIPLEXER

STB
H
L
L
L
L

INPUTS
SO
A
X
X
L
L
L
H
H
X
H
X

B
X
X
X
L
H

OUTPUT
f
L
L
H
L
H

H = high level, L = low level, X = irrelevant.

13
14

f3 12

74157

03
02

A2
STB

fl 07

74157
BO

VCC=PIN 16
GND=PIN08

SO
01

01
IC'74157

E-8

74161

SYNCHRONOUS 4-BIT COUNTER
3

0"" {
INPUTS

5
6

RO(' )

R1( 1)

R2(1 )

R3(1 )

"}
'2

OUTPUTS

74161

CLEAR
lOAD

CLOCK
ENABLE P
ENABlET

ClK
CNT EN
CO 15

CARRY
OUTPUT

GND : PIN 8
+5V: PIN 16

typical clear,preset, count, and inhibit sequences for 74161
Illustrated below is the following sequence:
1. Clear outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine, zero, one, two, and three.
4. Inhibit

CLEAR
PINOI

I
LOIID

IASYNCHRONOUSI

1_=

DO
PIN03

DATA
INPUTS

[

03
1PIN06 _ _ _ _,.-,.-_ _...JI _ _

CLOCK
PIN02
INABLEP
I 1
PIN07 _ _ _ _---''-_....:...J.

ENA~LE

T
PINIO
ROil)
PINI4 _
RIII)PINI3 _

OUTPUTS
R21l) PINI2 _
R31l)
PINll -

=LJI
=LJI
-I

,_ _ _ _ _ _ _ _ _...J

,---------------------------

-II

CARRY
PIN15

____________ ____

+__~----~r--l~----------------__+-------------------------------117
is
B
0
1
3:
1----coUNT-----..I··----'NH'B'T-----

CLEAR PRESET

IC-74l6l

E-9

741()4 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
These 8-bit shift registers feature gated serial inputs and an asynchronous clear. The gated serial inputs
(A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits
entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level
input enables the other input which will then determine the state of the first flip-flop. Data at the
serial inputs may be changed while the clock is high, but only information meeting the setup
requirements will be entered. Clocking occurs on the low-to-high level transition of the clock input.

TRUTH TABLE
SERIAL INPUTS A AND B
INPUTS

OUTPUT

ATtn

ATtn+l

74164
R7(1)
R6(1)

13
12
11

Rlllli

+5V=PINI4

R5(1)
R4(1)

GND = PIN 07

R3(1)

R2(1)

1
2

( 3)
R0(1 )

(4)
R1( 1)

A B

ClK

ClR

(1) (2)

(8)

(9)

(5)
R2 (1)

(6)
R3(1 )

(10)
R4(1 )

(11)
R5(1 )

Rl (1)

DSf) Ri1l(I)
IN

ClR

elK

(12)
'1<6 (1 )

(13)
R7(1 )

DSflI IN
IC-74164

E-IO

74174 HEX D FLIP-FLOP REGISTER

~ RO( I)

DO (3)

G CLOCK
TRUTH TABLE
INPUT

OUTPUT

In "

R( 1)

H
L

CLEAR

\f
Dl

~ Rl (I)

(4)

In = Bil lime before

'" CLOCK

clock pulse.

CLEAR

In+1 =Bit time afler

-y

clock pulse.

f-ITlo R2( 1)

(6)

G CLOCK
CLEAR

9
14

R5(1 )

~ R3 (1)

D3 (11)
13

R4( 1)

R3(1)
74174

6
D2

R2 (1)

RI (1 )

RO(I)

12
.... CLOCK

CLEAR

~ R4(1 )

(13)

G CLOCK
CLEAR

~ R5 (1)

(14)
D5
CLOCK

CLEAR

~
(1)

'"'

". CLOCK
CLEAR

Pin (16)= VCC,Pin (8)= GND
1C·74174.

74180 9-BIT ODD/EVEN PARITY GENERATOR/CHECKER

TRUTH TABLE
74180

i: OF ,'s AT EVEN
o THRU 7

2 D7

DATA
INPUTS

1 D6
13
D5
12 D4
11

EVEN
}
6
OUTPUTS
ODD

10 D2

ODD

i:
EVEN

ODD

EVEN

OD D

EVEN

OUTPUTS

INPUTS

9 Dl

8 DO
EVEN ODD

X= IRRELEVANT

Vee = PI N 14
GND=PIN 7

i:EVEN
OUTPUT
DATA
IN PUTS

i: ODD
OUTPUT
6
7 ~"----./
ODD
INPUT ~--------------------------~

EVENO~----------------------------~

INPUT

IC-741BO

E-12

74193 4-BIT UP jDOWN COUNTER
The 74193 Binary Counter has an individual asynchronous preset to each flip-flop, a fully independent
clear input, internal cascading circuitry, and provides synchronous counting operations.

typical cleor,lood,ond count sequences for 74193

Illustrated below is the following sequence:
1. Clear outputs to zero.
2. Load (preset) to BCD thirteen.
3. Count up to fourteen, fifteen, carry, zero, one, and two.
4 Count down to one, zero, borrow, fifteen, fourteen, and thirteen.

SEE
NOTE
3

PIN 14

PIN 1 I

CRY

DATA
INPUTS

r:
01
15

SAW

PIN 15

R311)

D3
02

74193

R211)

::1
02

Rill)

ROI' )

PIN 01

CLEAR

I
LOAD

PIN 09

U
.-'---:---'--;: -- ______________________________
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -__
1

1
01

~--------------------------------

--'-...J: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

----;.-:_1'-'__

PIN 10

L)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

oo~

DATA

OUTPUTS

c================
c================

~~ , ,
I

P1N04 COUNl

DOWN

SEE SEE '-------'
NOTE NOTE SEE
NOTE
4
5
6
OUTPUTS

NOTES:

1. Clear overrides load, data, and count inputs.
2. When counting up, count down input must be high;
when counting down, count-up input must be high.

3. Produce pulses equal to width of count pulses
during: Underflow!BORROW)
Overflow (CARAY)
4. ClR input high forces all outputs low. ClR
overrides load, data and DN!UP inputs.
5. Preset to any state by applying input data with
load input low. Output changes to agree with inputs
independent of count pulses.
6. Select DN or UP clock while other is held high.

[:"::: ::::: =
PIN06

R2 (1)

PIN07

R3(1)

~i--'-,--'------~-------------c----------'
I

=~r7I-~--~
I

PIN 12 CAf1R~

PIN13 HORR()\\

In!

~-c-____---'

10 1

______

I "

r--

I
>"

0
CCUNTUP

~ r-1

COUNT DOWN ~

1C-14\93

E-13

74197 4-BIT COUNTER

DO
74197
TRUTH TABLE
COUNT
CLOCK 1 HlPUT
0
1
2
3

4
5
6
7
8
9
10
11
12
13
14
15

LOAD o-::0-'-I_---()\

OUTPUT
R3
(1)

(1)

RO
(1)

0
0
0
0
0
0
0
0
I
I
1
1
1
1
I
1

0
0
0
0
1
1
1
I
0
0
0
0
I
1
1
1

0
0

0
1
0

1
0
0
I
I
0
0
1
1
0
0
1
I

0
1
0
I
0
I
0
I
0
1
0
I

CLEAR 0-'-'3'-<1>-_ _-1

PRESET
05

RO(I)

CLOCKOo-::°~8-------~~-----~_-----aT

1
CLEAR

01 ~10~_ _ _ _ _ _-r-+~

PRESET
09

RO (1 ) connected to CLOCK 2 input.

CLOCK I

-r-+_____-+_____~T

RH 1)

o-::0~6~_ _ _ _ _ _

PRESET

DATA
INPUTS

03
03 02

f
10

R3 (1)
R2 (1)
74197

Rl (1)

RO(I)

R2(1 )

OUTPUTS

CLEAR

PRESET
12

R3(1 )

CLEAR

IC-74197

E-14

75107

SENSE AMPLIFIER (DUAL-IN-LINE)

G _ _ _----"5'--!
S _ _ _--=6~

TRUTH TABLE

DIFFERENTIAL
INPUTS
A-B

STROBES

V,D ~ 25 mV

Lor H Lor H

Lor H

INDETERMINATE

-25 mV < VID < 25-mV

y
S

V ID .. -25 mV

OUTPUT

Lor H

B
GND: 7

-vee: 13
tVee: 14
IC-7 5"1 07

E-15

Reader's Comments

TMB11/TU10W DECmagtape SYSTEM
MAINTENANCE MANUAL (TMB11-E/F SYSTEM)
EK-TMBEF-MM-002
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