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Document:	MM11-F Core Memory Engineering Drawings
Order Number:	DEC-11-HMFA-D
Revision:
Pages:	26
Original Filename:	DEC-11-HMFA-D_MM11-F_Manual.pdf

OCR Text

DEC-11-HMFA-D

MM11-F
core memory

manual

DIGITAL EQUIPMENT CORPORATION « MAYNARD, MASSACHUSETTS

1st Edition March 1971

The material in this manual is for information purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS

Page

CHAPTER 1 INTRODUCTION

CHAPTER 3 MAINTENANCE

1.1

Scope

3.1

Introduction

1.2

Introduction

Adjustments

3-1

MM11-F General Description

3.2.1

Equipment Required

3-1

1.3.1

Core Array

322

Initial Procedures

3-1

1.3.2

Memory Control

3.2.3

Voltage Reference (V REF) Adjustment

3-1

133

Address Selection

324

Voltage Slice (V SLICE) Adjustment

134

Inhibit Drivers

325

Strobe (STROBE DEL) Adjustment

32
32

1-2

3-1

1.35

Sense Amplifiers

Maintenance

1.3.6

Data Register

Programming Tests

13.7

Switches and Drivers

34.1

Address Test Up (MainDEC-11-DIAA)

1.3.8

Current Generator

342

Address Test Down (MainDEC-11-DIBA)

1.3.9

G103 Levels and Gates Module

343

No Dual Address Test (MainDEC-11-DICA)

1.4

Basic Memory Operations

344

Basic Memory Patterns Test (MainDEC-11-DIDA)

3-5

14.1

Data In (DATI) Cycle

34.5

Worst Case Noise Test (MainDEC-11-DIGA)

142

Data In, Pause (DATIP) Cycle

143

Data Out (DATO) Cycle

144

Data Out, Byte (DATOB) Cycle

APPENDIX A PARITY OPTION

APPENDIX B INTERLEAVING
CHAPTER 2 THEORY OF OPERATION
2.1

Introduction

2-1

2.2

Core Array

2-1

2.3

Memory Operation

2-1

2.4

X- and Y-Line Selection

2-2

ILLUSTRATIONS

2.5

Drivers and Switches

2.6

Current Generator

2-6

2.7

Control and Timing Logic

2.7.1

General

27.2

Device Selection

2-8

2-1

2.7.3

X-Y Address Latching

2-8

2-2a

274

Data In (DATI) Control Circuits

2.7.5

Data In, Pause (DATIP) Control Circuits

2-2b

Hysteresis Loop for Core

276

Data Out (DATO) Control Circuits

2-3

Core Orientation

277

Data Out, Byte (DATOB) Control Circuits

Sense Inhibit Windings

Figure No.

Art No.

Page

Three-Wire Memory Configuration

11-0079

2-1

Three-Wire 3D Memory, Four Mats Shown for a 16-

11-0088A

Title

Word — 4-Bit Memory
11-0088B

2-3
2-3

2.8

Read Operation

2-11

2-5

X-Y Windings

Write Operation

2-11

2-6

Word Size Variation

iii

ILLUSTRATIONS (cont.)

Title

Figure No.

Art No.

Page

X-Line Decoding

11-0086

2-8

Switch or Driver Base Drive Circuit

11-0084

2-5

X-Line Drivers and Switches

11-0078

2-6

2-10

Simplified Interconnection Diagram

11-0083

2-6

2-11

Current Generator, Simplified Schematic

110077

2-6

2-12

Current Generator Waveforms
M7290 One-Shot Delays

11-0082

2-13

11-0090

2-7

2-10

2-14

Sense Amplifier Detector Circuit

110089

2-15

Inhibit Driver

11-0080

2-11
32

Strobe Pulse Waveform

11-0081

MM1 |-F Sense/Inhibit Waveforms

11-0091

3-3

Drive Waveforms

11-0092

3-1

TABLES
Page

Table No.

MM11-F Core Memory Configurations

1-1

2-1

Address Functions

Read and Write Selection

2-6

2-3

Selection of Memory Operation

2-8

Core Memory Adjustments

MM I-F Troubleshooting Guide

1-1

—

CHAPTER 1
INTRODUCTION

Table 1-1

1.1 SCOPE

This manual provides the user with theory of operation and logic diagrams necessary to understand and maintain
the MM1 1-F Read/Write Core Memory. The level of discussion assumes that tne reader is familiar with basic digital
computer theory. Both general and detailed descriptions of the core memory are included.

Although memory control signals and data pass through the Unibus@, it is beyond the scope of this manual to describe the operation of the Unibus itself. A detailed description of the Unibus is presented in the PDP-11 Unibus

Interface Manual, DEC-11-HIAB-D.

MM11-F Core Memory Configurations

Designation

This manual is divided into three major sections:

Introduction

Theory of operation

¢.

Adjustment and maintenance procedures

Reference

MMI11-F

Standard core memory without parity or

(4K only)

interleaving capabilities.

MMI11-FP

Parity capability — an 18-bit core memory,

Memory covered in basic manual; par-

(4K only)

identical in all respects to the MM11-F (4K)

Basic MM 11-F manual

ity in Appendix A

except for bits 16 and 17.

A complete set of engineering logic drawings is shipped with each core memory. These drawings are bound in
a separate volume entitled MM11-F Core Memory, Engineering Drawings. The drawings reflect the latest print
revisions and correspond to the specific memory shipped to the user.

Description

Bit 16 is byte O parity.
Bit 17 is byte 1 parity.

MMI11-F

Interleaving capability — a basic MM11-F

Memory covered in basic manual; inter-

(8K or higher)

that has address bits 1 and 13 interchanged

leaving in Appendix B

to allow faster cycle times when alternate
adjacent memory banks within an 8K block

are addressed.
MMI11-FP

A memory unit combining both the inter-

(8K or higher)

leaving and parity capabilities.

Basic Manual, Appendices A and B

1.2 INTRODUCTION

1.3 MM11-F GENERAL DESCRIPTION

The MM11-F is a 16-bit, 4096-word (4K), read /write core memory designed for the PDP-11. The Unibus concept
is used by the PDP-11 System; thus, the central processor does not contain an integral memory. The memory used

The standard PDP-11 core memory, designated MM 11-F, is a random-access, coincident-current, magnetic read/

by the system is an external device and is connected to the processor through the bus interface. The core memory
functions as a true peripheral and is compatible with all PDP-11 Systems. It is normally used as the basic memory

a 3-D, 3-wire, planar configuration. The basic unit can store up to 4096 (4K) 16-bit words. The memory can be

unit in any system that requires a large core memory.

nal device is preselected by the user simply by moving appropriate jumpers on a logic card.

The MM11-F Core Memory may exist in any one of four-configurations, depending on whether parity and/or interleaving capabilities are included. These four configurations are listed in Table 1-1 along with a reference indicating

The Unibus concept of PDP-11 System requires that a master/slave relationship exist between the processor and an

bility is automatically added whenever an 8K or larger memory is used. The print set in this manual is applicable

eral. The core memory can never function as bus master.

to all configurations.

The basic functional components of the core memory are briefly described in the following paragraphs.

the section of the manual that contains a detailed description of the configuration. Note that the interleaving capa-

write core memory; cycle time is 980 ns and access time is 400 ns. The memory comprises ferrite cores wired in
expanded up to 28K words in 4K increments. The hard-wired address that selects the memory for use as an exter-

external device or between two different external devices. Although many devices can function as either master or

slave, the core memory always functions as a slave, whether the controlling unit is the processor or another periph-

1.3.1 Core Array

The ferrite core array consists of 16 core mats, each wired in a 64-by-64 matrix. This arrangement provides a total

@Unibus is a trademark of Digital Equipment Corporation.

of 4096 16-bit words of data and/or program storage. The cores are connected by three 'ires. An X and a Y line

are used for individual core selection. The third line is a shared sense/inhibit line. There is a separate sense/inhibit
line for each mat. This single line can function as either a read or write line due to the method of wiring and the
control logic circuits.

1.3.2 Memory Control

Memory control circuits acknowledge the requests of the master device, determine which of the four basic operations is to be performed, and set up the appropriate timing and logic sequences to perform the desired read or write
operations. The memory control logic also transfers data to or from the Unibus as required.

1.3.8 Current Generator

The current generator provides the current necessary to change the state of the magnetic cores. The linear rise

time and amplitude of the output-current waveform have been selected to provide optimum switching of the core

states and maximum signal-to-noise ratio for a wide range of temperatures.
1.3.9 G103 Levels and Gates Module

The G103 Levels and Gates Module performs address gating functions for X and Y selection; generates the -6V

and -5.2V threshold voltages which are derived from the -15V supply; and provides an ac termination for the X-Y

switching matrices.

1.3.3 Address Selection

The core memory receives an 18-bit address from the master device. The address is decoded to determine if the
memory is the selected device and to determine the core location specifically addressed. If the operation is a byte
operation, bus line AOO L indicates the byte to be used. The actual read or write operation is not selected by the
address but is selected by the settings of the bus C lines.

1.4 BASIC MEMORY OPERATIONS

The core memory has four basic modes of operation. The main function of the memory is simply to read or write
data, Additional modes are provided, however, to allow for byte operation and to eliminate the restore cycle
when it is not needed, thereby increasing overall system efficiency. The four basic memory operations are:

The X and Y portion of the address is decoded through selection switches and a diode matrix to enable passage of

Read/restore (DATI)

Read only (DATIP)

lects the specific 16-bit core memory location desired.

¢.

Write (DATO)

Write byte (DATOB).

read/write current through the selected X and Y drive lines of the memory. The coincidence of these currents se-

1.3.4 Inhibit Drivers

These four modes are discussed briefly in the following paragraphs.

The core memory is so designed that, unless inhibited, all bit locations of the selected memory cell are switched to
a logical 1 during the write portion of the memory cycle. To prevent this occurrence, each bit has inhibit drivers
that are used during write time to oppose the Y write current, thereby ensuring that, if logic O levels are stored in

NOTE

In the following discussions, all operations refer to the master
(controlling) device. For example, the term data out indicates
data flowing out of the master and into the memory.

the data register, they are written in the corresponding bit location of the addressed memory cell.

1.4.1 Data In(DATI) Cycle

1.3.5 Sense Amplifiers

During the rcad portion of a memory cycle, sense amplifiers detect analog signals induced in the sense/inhibit
windings of the core array. These signals are shaped, amplified, and then time sampled by means of a strobe signal to set corresponding bits of the data register.

1.3.6 Data Register

The data register is a 16-bit flip-flop register (18-bit register if the parity option is included) used to store the contents of a word after it is read out of the destructive memory; the same word can then be written back into memory (restored) when in the data in (DATI) mode. The register is also used to shift data from the Unibus lines to
accommodate the loading of incoming data into the core memory during the data out (DATO) or data out, byte
(DATOB) cycles.

1.3.7 Switches and Drivers

The switches and drivers direct the flow of current through the magnetic cores to ensure the proper polarity for
the desired function. This action is necessary because a single read/write line is used, and the current for a write
operation is opposite in polarity to the current required for a read operation. There are separate switches and
drivers for the read and write circuits in the selection matrix.

The DATI cycle is a read/restore memory cycle. During this operation, the memory reads the information from
the selected core location, transfers it to the Unibus, and then writes the information back into the memory loca-

tion. This last step is necessary because the core memory is a destructive readout device. During the first part of

the cycle, the memory loads the data into a register; at the same time, the memory applies the data to the Unibus.
Then, during the second part of the cycle, the memory takes the data from the register and writes it back into the
memory location.

1.4.2 Data In, Pause (DATIP) Cycle

Normally in reading memory, the information is destroyed in the particular location accessed, and the data must
be restored. However, sometimes it is not actually necessary to restore the information after reading, because the
location is to have new data writtgn into it. In this instance, eliminating the restore operation decreases the mem-

ory cycle time by approximately 50 percent. The DATIP operation is used for this purpose. The data is read from
memory and the restore cycle is inhibited. Because no restore cycle is used, a DATIP must always be followed by
a write cycle (either DATO or DATOB).
1.4.3 Data Out (DATO) Cycle

The DATO cycle is a write memory cycle used by the master device to transfer data into core memory. To ensure
that proper data are stored, the memory unit must first be cleared by reading the cores (thereby setting them all

)

to zero) before writing in the new data. During a normal DATO, the memory first performs the read operation to

clear the cores and then performs a write cycle to transfer data from the bus into the selected core location. Ifa
DATO follows a DATIP (rather than a DATI), the sequence is not the same. The DATIP clears core and generates
a pause flag; thus, the memory skips the read cycle and immediately begins the write cycle. This process reduces
DATO cycle time by approximately 50 percent.

1.4.4 Data Out, Byte (DATOB) Cycle

The DATOB cycle is similar in function to the DATO cycle, except that during DATOB data is transferred into
the core memory from the bus in byte form rather than as a full word. Actually, an entire word is loaded into the
selected memory location: the selected byte which is new data from the bus and the non-selected byte, which is

restored data from the word previously stored in that memory location. During the read cycle, the non-selected
byte is saved by storing it in the data register while the selected byte is cleared. During the write cycle, only the
selected byte portion of the word is loaded into the memory location from the bus. At the same time, the nonselected byte is restored from the data register into the memory location. In effect, the memory is first cleared

and then simultaneously performs a restore cycle for the non-selected byte and a write cycle for the selected byte.

CHAPTER 2

THEORY OF OPERATION

WRITE

)
\

The information in this chapter is supported by a complete set of engineering drawings which are contained in a

FERRITE
/\/ CORES

/‘

write operation, control and timing logic, read/write drivers and switches, and the current generator.

array and overall memory operation. Subsequent paragraphs describe X- and Y-line selection and decoding, read/

This chapter provides a detailed description of the MM11-F Core Memory. The first topic presented is the core

(]

2.1 INTRODUCTION

INHIBIT
CURRENT DRIVER

2.2 CORE ARRAY

separate volume. All calibration and adjustment information is included in Chapter 3.

64 array. Each mat represents a single bit position ofa word. The memory is referred to as a planar memory.

This planar configuration provides a total of 4096 16-bit word locations. Each ferrite core can assume a stable

The ferrite core memory consists of 16 memory mats; each mat contains 4096 ferrite cores arranged in a 64-by-

magnetic state corresponding to either a binary 1 or a binary 0. Even if power is removed from the core, the core
retains its state until changed by appropriate control signals. The ferrite cores themselves are 20-mil cores. The
outside diameter of each core is 22 mil; the inside diameter is approximately 16 mil. Each core is 5.5 mil thick.
Selection and switching of the cores is provided by only three wires traversing each core in a special selection technique. An X-axis read/write winding passes through all cores in each horizontal row for all 16 mats. A Y-axis

read/write winding passes through all cores in each vertical row for all 16 mats. Through the use of selection circuits which control the current applied to specific X-Y windings, any one of the 4096 word locations can be addressed for writing data into memory or reading data out of memory. A third line passes through each core on a

mat to provide the sense/inhibit functions. There is one sense/inhibit line per mat. This single sense/inhibit line,

Ims2

SELECTED
CORE

as well as the selection circuits, are discussed in subsequent paragraphs.

2.3 MEMORY OPERATION

4
-

Figure 2-1 illustrates a typical portion of the core memory. An X and Y winding pass through each core in the
mat. The current passing through any one winding is such that no single winding produces a magnetic field strong
enough to cause a core to change its magnetic state. Only the reinforcing magnetic field caused by the coincident
current of both an X and a Y winding can cause the core located at the point of intersection to change states. It

is this principle that allows the relatively simple winding arrangement to select one and only one memory core out

SENSE/INHIBIT

——
Y e

SE
8 AMPLIFIER
TO SEN

of the possible 4096 contained on each mat. The current passing through either an X or Y winding is referred to

TERMINATION

[m/Z

w0078

as the half-select current.
READ

A half-select current passing through the X3 winding (see Figure 2-1) from left to right produces a magnetic field
that tends to change all cores in that horizontal row from the 0 to 1 state. The flux produced by the current is,
however, insufficient to complete the state transition in any core. Simultaneously passing a half-select current

Figure 2-1

Three-Wire Memory Configuration

2-1

through the Y1 winding from top to bottom produces the same effect on all cores in that particular vertical row.
Note, however, that both currents pass through only one core which is located at the intersection of the X3 and
Y1 windings. This is the selected core and the combined current values are sufficient to change the state of the

ARROWS SHOW CURRENT
DURING WRITE TIME

core.

All X and Y windings are arranged in such a manner that whenever a half-select current is passed through each, the
resultant magnetic fields combine in the core at the point of intersection. This combined, full-select current en-

TOP VIEW OF C ORE MATS

sures that the selected core is left in the binary | state. The currents used to select the core are referred to as write
currents.

In the MM1 1-F Core Memory, the X3 windings in all 16 mats are connected in series as are the Y1 windings.
Therefore, whenever a full-select current flows through a selected core on one mat, it also flows through an identical core on the other 15 mats. The X3-Y1 cores on all mats switch to a binary 1, causing each of the 16 cores to

Xsw

become one bit of a 16-bit storage cell.

Because of the serial nature of the X-Y windings, a method must be employed to set certain cores to the 0 state;
otherwise, every 16-bit word selected would be all 1s. The method used in the MM11-F Core Memory is to first
clear all cores to the O state by reading and then, using an inhibit winding, inhibit cores on particular mats. The

inhibited cores remain Os even when identical cores on other mats are set to s,

W——

In many memories, the inhibit line serves only the inhibiting function; however, in the MM11-F, this line serves as
both an inhibit and sense line. As a result, only a three-wire memory is necessary, rather than a four-wire memory.

Wiy

———

—~==

INTERCHANGE
S FOR NOISE

CANCELLATION

Only the inhibit function is discussed at this point.

The half-select current for the inhibit lines is applied from an inhibit current driver, which is a switch and a resistor between the inhibit line and -15V. The current in the inhibit line flows in the opposite direction from the
write current in that line and cancels out the write current. There is a separate inhibit driver for each memory
mat, and each mat represents one bit position of a word; thus, selected bits can be inhibited to produce any combination of binary 1s and Os desired in the 16-bit word. It must be remembered that the inhibit function is active

the specific X and Y lines.

An 8-by-8 decoding matrix is used to select 1 of the 64 X-lincs. An identical matrix is used to select 1 out of the
64 Y-lines. For ease of presentation, only X-line decoding is discussed. Decoding of the Y lines is identical.
22

W R
W
YDR

SENSE~INH LINE

&
BONDING MEDIUM

{

except that it has 64 X-lines, 64 Y-lines, and 16 core mats. The core stringing is identical, and the sense windings
are strung through all 4096 cores with the interchange between X31 and X32 instead of between X1 and X2. The
actual configuration is shown in Figures 2-3 through 2-6. These figures show the core orientation, the sense inhibit

Previous paragraphs have explained the method for selecting a specific core by passing half-select current values
through specific X and Y windings. This paragraph is devoted to an explanation of the method used for selecting

CORE STRINGING

fier strobes the signal into the data register for eventual transfer to the Unibus.

2.4 X-and Y-LINE SELECTION

YSw

YSW

The sense/inhibit lines are also used to read out information in a selected 16-bit memory cell. The specific core is
selected at read time in the same manner as during the write cycle with one notable exception: the X and Y currents are in the opposite direction. These opposite half-select currents cause ail cores previously set to 1 to change
to 0; cores previously set to 0 are not affected. Whenever the core changes from 1 to 0, the flux change induces a
current in the sense winding of that mat. This current is detected and amplified by a sense amplifier. The ampli-

windings, the X-Y lines, and word size variations.

only during write time.

Figure 2-2 shows a 1 6-word by 4-bit planar memory. The MM1 1-F Core Memory functions in the same manner,

THERE 1S ) SENSE
WINDING PER MAT

INH

)

).—x LiINE

}

GROUND PLANE

BOARD

Figure 2-2a Three-Wire 3D Memory, Four Mats Shown for a 16-Word — 4-Bit Memory

11-00884

HYSTERESIS LOOP FOR CORE

FOLD LINE

FLUX STORED OR SWITCHED

INHIBIT OR

"UNDISTURBED

""DISTURBED

p~—

READ HALF SELECT

FULL

SELECT

FLUX

zzcucss{ :

DRIVE CURRENT

READ

I WRITE

CHANGE
FOR 1 AT
<
TIME

NOTES:
1.

DIMENSIONS

SHOWN ARE CORNER,
OR

CORE CENTER SPACING.

END,CORE

2 CORE CENTER TOCENTER SPACING ON 'viaxiS =005 oW,

3. CORE CENTER TO CENTE
B SPACING ONK'AXIS+. 085 Nom,
@ CORE PATTERN 70 BE DOUBLE HEREINGBONE "PATTERN.

e corES

READ

Gdr6d, 4096 CORE MULTIALE

SELECT

CONFIGURATION

0" DISTURBED - -

{

"0" UNDISTURBE

{

THE CINES ISIOE THE MAT AREAS SO THE QRIENTATION

THESE MATS OV Géi7

THESE MATS ON Gbl6

FULL

BIT MAT

Figure 2-3

{

HALF SELECT WRITE

OF THE PATTE PN, NOTE THE MAT INVERSION ALONG THE'YAXIS.
S EACH MAT TO BE &% Y& WITH
SENSE WINDING

IE0 SPCE TO ENABLE A

INTERCHANGE
.,

Core Orientation

_ _FLUX CHANGE AT READ

TIME FOR A"0"

SENSE

NOTE NO SWITCHING

TAKES PLACE.

CORE TIME CONSTANT AND IS

0" OUTPUT COMES DURING | RISE TIME
AND IS & FUNCTION OF IT AND CURRENT
AMPLITUDE.

“0" QUTPUT X A T‘IOR«%"II'

PRIMARILY DEPENDENT ON

CURRENT AMPLITUDE. 1T WILL

§84

SWITCH FASTER AND GROW AS
RISE TIME IS DECREASED,

G
13

Eole

5 [e]

DOTTED LINES SHOW HOW

OUTPUTS WOULD BEHAVE

Ija

I|a

‘

Hysteresis Loop for Core

[

[ )

)

as|lt

mallt

T la

Side

b fi

WITH DIFFERENT CURRENTS

11-00888

REF CORNER

sAjlr

as|ir

[

H—p

‘

alz

s
~

NOTES:
|

WINDINGE
TO 8 G0 INSUCATED MAGNET
8 AND § WIRES, ARE TO BE TWISTED TOGETHER,

& MINIMOM 10 TURNS, PER INCH,
BE TWEEN MATS
AND TERMINATIONS-

THE TWO WIRES MARKEL
T WILL BE TWINTED A

INNOTE 2.
4.

Figure 2-2b

WINDINGS

"1" QUTPUT SWITCHES AT THE

SENSE INHIRIT WERES WILL BE [MMORILIZEC
AT X7 INCH INTERVALS By BEASD OF
ADHESIVE OR SOME ERUIVALENT METHOD.
WINGINGS, SHOULD 8E UNIFORM WITH SMALL

TURN ARDUNG LOOSS

BUT NOT SO TIGHT AS

TS PULL THE CORES OUT OF ALLGRMENT.

Figure 2-4

Sense Inhibit Windings

The incoming address actually performs four separate functions; however, only X-line decoding is discussed at this

point. The four functions and corresponding bit assignments of the address are listed in Table 2-1.

Fess

none

‘4

REF CORNER

xS 8y

%57
Kl

FE——

|
|

=l
|

X6 § X7

xz
g X3

*1, 2 through 6

X584 X59

AGZ§ X3

7 through 12

X035

—@ied

777’

bits 10 through 12 = positive, negative switches O through 7

§ Xl

Device selection

X-line selection

bits 7 through 9 = positive, negative drivers O through 7

*13, 14 through 17

Y-line selection

XSG
¢ RST

’

Select byte only during DATOB

xagns

I~ g

Function

!
-

*When memory is interleaved, bits 1 and 13 are interchanged.

Eisid

X § v DRIVE L NES
EOA

L !

i"
i

voa@n
yegy

SF o
O HTARR

e
$e93s

HIGE 55A e

ARERALS

TF R

Figure 2-5

read switches are positive, write switches are negative.

X-Y Windings
= & TS SEC v

aos T [TERM% AT [ FEAM VAT

S508388]

Figure 2-7a is a representation of one pair of decoders used to select the X-line selection switch. As the method of
decoding is slightly unorthodox, consider the A and B decoders as a single 4-line to 16-line decoder with 16 output
pins. There are two pins for each switch: one for read operations and one for write operations. Figure 2-7b indicates the 16 possible outputs and the function of each. There are eight read switches and eight write switches:

saces0e]

T
i

Yo
e
¥a

In actuality, bit 12 of the incoming address effectively selects either the A or B decoder. If the bit is binary 0, the
A decoder is used; if the bit is binmy 1, the B decoder is used. The read signal selects one half of the selected decoder. If the read signal is present, the output comes from the upper half of the decoder, and one of the four read

(

outputs is used. If the read signal is absent, the lower half of the decoder provides one of the four write outputs.

The remaining two bits, bits 10 and 11, select one of the four outputs (0 through 3) from the decoder.

As an example, assume that all bits are set and a read signal is present. Bit 12 set selects the B decoder. The read
signal selects the upper half of the decoder. Bits 10 and 11 set represent a binary 3 so that output 7 from pin 3is

THE,

@lSE=e

e —

Address Functions

bits 1 through 3 = positive, negative drivers O through 7
bits 4 through 6 = positive, negative switches O through 7

x50

(

Address Bit Assignment

Table 2-1

the selected read switch.

Assume now that only bit 11 is set and the read signal is not present. Bit 12 being O causes the A decoder to be
used. The absence of a read signal effectively selects the lower (write) portion of the decoder. Bit 11 being set

with bit 10 being 0 represents a binary 2. The third number (binary 2) in the write portion of the decoder is represented by pin 6. Therefore, the output is write switch 2.

The read/write driver that corresponds to the other X octal digit is selected in the same fashion using TDRH and
bits 9, 8, and 7.

The portion of the address used to select the Y lines is represented by bits *1, 2, through 6. Therefore, bits *1
through 12 of the incoming address are used to select the X and Y lines that determine the specific core where a
bit is to be read or written. One core on each bit is selected (refer to Tables 2-1 and 2-2).
MODULE

AL
2

Figure 2-6

Word Size Variation

REGL RES | QUAL
ConECTGURAT
NS

MODULE

159

INGHES

SLOT FOR

*When memory is interleaved, bits 1 and 13 are interchanged.

KUTREEPN

IS1

—

BIT 10

A | Wy
8 | T2y

Y MEL N

READ

c | va)

4 RN 6y

{uz)

5 —(-Bg)—|

2 PN,

(NsTo-3
8251

—

A DECODER

|()

— a

(81T 12HeTssH) ——

8 | o2

Y MEL -

¢ | vy

> READ

NS 4-7

NOTE:

Numbers in parenthesis indicate system

b 6
o~

i3
»

Switch or Driver Base Drive Circuit

When the decoder is turned off by the timing input, its pull-up transistor now tries to drive current in the opposite
direction (i,). The capacitor performs two functions: it speeds up the turn-on current i, and allows the decoder to

verse breakdown of that junction during turnoff. Since this diode limits the transformer secondary voltage during
WRITE

turnoff, some of the circuits contain two diodes in series to allow faster transformer recovery. Note that the dc
level of the output transistor is irrelevant. This transistor is saturated when on.

7
2.5 DRIVERS AND SWITCHES

BITI

BIT 10

Drivers and switches direct the flow of current through the cores to ensure proper polarity for the desired read or

1
,

0
;

1
o

write function. A read driver and switch, as well as a write driver and switch, are provided for groups of eight X

BITI2

READ

o
S
0

[

)

[

o
)
iy

charge on the output transistor in the transformer secondary to turn it off. The base emitter diode prevents re-

location ond pin numbers.

(N1)

B3
b 5

Toxt

pump reverse current i, into the transformer primary. The reverse current is necessary to remove the base emitter

6 R4 [ ps a-7

—

Figure 2-8

(P1)

5 (B2

(FO2)

g s

11-0084

B DECODER

| ——

ps 03

2 LS

b | (v

——

[

AND
TIMING

avoress | — pecooer B 2

WRITE

s B5

(coz)

READ

BIT 11

(BIT 12HeTSSH)

+5V

[

READ

[

lines and groups of eight Y lines in the selection matrix, such that each axis has its 64 lines selected by an 8-by-8
matrix.

0-3

DECODER

WRITE 0-3

Figure 2-9 is a simplified diagram of the switches and drivers. The diagram represents one X line. Note that the
flow of read current is shown by a solid line; the write current path is shown by a broken line.

READ

4-7

DECODER

When a read operation is selected, the read driver and read switch are turned on, and the write driver and write
switch are turned off. The output current from the current generator flows through the read driver, through the

_
WRITE 4-7

cores on the associated X line, and through the read switch. When a write operation is selected, the write driver
and switch are turned on, and the read driver and switch are turned off. In this case, current from the current generator flows through the write switch, through the cores (in the opposite direction from that during read), and

1120086

Figure 2-7

X-Line Decoding

The X and Y selection logic is shown on drawing MM1 1-F-03, sheets 1 and 2. The decoder output numbers are
not shown on the drawings in the same manner as described in this section.

through the write driver. The signals that select the read and write operations are given in Table 2-2. Each line
has 64 x 16 (or 1024) cores on its as it threads through all 16 mats.

Resistors R1 and R2 are provided as terminations to prevent unwanted currents from affecting the drivers and
switches. The circuit that comprises transistor Q1 and resistor RS is used to make the write current equal the
read current and to assist the ferrite core stack in recovering. This method is much faster than allowing the stack

Figure 2-8 shows the switch or driver base drive circuit that is connected to the decoder. The timing and address

to recover by itself. The decoder output and write driver transformer base drive are shown. All base drives are

inputs cause the 8251 decoder output to go to ground and current i, flows from the +5V supply, through the re-

similar.

sistor, through the transformer primary, and into the decoder output. The value of the current is determined by
the resistor and the voltage reflected into the transformer primary (approximately 1.0V). An equal current (i,)

The drivers and switches in one line share a common line with drivers and switches in other lines. Figure 2-10 (re-

is induced into the base emitter circuit connected to the transformer secondary. This current turns on the trans-

presenting 16 lines on a 4-by-4 matrix) shows the interconnection of four drivers and four switches on 16 lines to

istor. Note that all base current is provided from this circuit and the current from circuit i, equals the collector

aid in understanding the interconnection of all 64 lines in the 8-by-8 matrix. Only one line is common between

current.

any driver and switch. Note how the diodes prevent sneak paths. Only a unipolar matrix is shown.

READ

X-LINE CIRCUITS

CURRENT |

READ DRIVER

GURRENT

)y
_——

_——

PD(0-7] POS

——

WRITE SWITCH

1024 CORES (64/MAT)

4 POSITIVE]

<
DRIVERS

|
:
@-@-@L

I
8 DIODES *
.

[

o —————

TO REGOVER
STACK

1-0083

Figure 2-10

NS(0-7) NEG

Simplified Interconnection Diagram

READ SWITCH

WRITE DRIVER

-15v

ND(0-7) NEG

AC TERMINATION
SWITCHES AND

<
MW—

}

+5V —AMN—8

[__4

DECODER QUTPUT

LOW ACTIVE

] l..

PS{0-7) POS

-15V —AM—4

SWITCHES

LINES

4 NEGATIVE

X-LINE CIRCUITS

GEN.

8 IDENTICAL

| .

WRITE

8 IDENTICAL

CURRENT
GENERATOR

YYY YYYY r ¥y 9 [

+5V

2.6 CURRENT GENERATOR

The current generator provides the current required to change states of the magnetic core. Generator design is

8 IDENTICAL
X LINE CIRCUITS

[

such that the linear rise time and amplitude of the output current waveform ensure optimum switching of core
states. Figure 2-11 is a simplified schematic of the current generator; Figure 2-12 illustrates the test point and

8 IDENTICAL

X-LINE CIRCUITS

output waveforms.

READ CURRENT
WRITE CURRENT

+8v

THE DRIVER AND SWITCH
EACH FEED 8 LINES,
HOWEVER, ANY ONE LINE
IS COMMON TO BOTH.

R2
f1-0078

Figure 2-9

X-Line Drivers and Switches

NS
Table 2-2

169

Read and Write Selection

Driver or Switch
Read Driver

Read Switch
Write Driver

Write Switch

Signals Required to Turn On

Vv REF

ADDRESS and TDR and READ H
ADDRESS and TSS and READ H

CIRCUIT

ADDRESS and TDR and WRITE H
ADDRESS and TSS and WRITE H

v REF

/;>

o
(0-2v)

TEST

POINT

D3
b2

Reon

WRITE
READ
CURRENT CURRENT

OUTPUT OUT PUT
-15v

NOTE

READ H and WRITE H are both outputs of the same control
flip-flop. When the READ flip-flop is set, the output is READ
H; when it is cleared, the output is WRITE H.

/T
1-0077

Figure 2-11

Current Generator, Simplified Schematic

AMPLITUDE

CURRENT

gsT\EF:iME’:ED

ouTPUT

:
«+— LINEAR PORTION

Perform the appropriate data transfer as requested by the master device by providing all internal
memory timing.

The following paragraphs discuss device selection, X-Y address latching, and control and timing circuits for each

of the four transfer operations (DATI, DATIP, DATO, and DATOB).
TEST

4TV

The control and timing circuits are shown on drawing MM11-F-05, Sheets 1 and 2. Sheet 2 contains the logic as-

LINEAR PORTIQN

POINT

OF RC CIRCUIT

sociated with the bus address and data lines, including the device selection logic. The remainder of the control

FORWARD

BIASED D1

(VRer -Vpo!

1o +50ba 0 +Von)- VRer
R3

and timing logic circuits are shown on Sheet 1. The timing diagram is shown on drawing MM11-F-08.
Details of the one-shot delays on the M7290 Module are shown on Figure 2-13. This figure provides circuit draw-

ings and waveforms for each of the three types of one-shots used on the M7290 Module.
19-0082

(1)

2601

When the current generator is in the quiescent state, transistor Q1 is saturated, thereby holding the voltage level at

the test point to 4.7V. Diode D1 blocks any voltage from the voltage reference (V REF) circuit, and transistor

equal to the voltage reference minus the voltage drop across diode D1. The voltage reference circuit contains a
trimpot to adjust the output between OV and 2V. The adjustment procedure is given in Chapter 3.

At the same time that transistor Q1 cuts off, capacitor C1 begins charging. The time constant of C1 and resistor

b—

When the logical transition satisfying sither (AL*CH#DH) osr (BLSCH®DH ) occurs, the outputs of

the 9601 change state for a time & 0.43 RC.

cuits. This signal is inverted by an AND gate and used to cut off transistor Q1. When Q1 cuts off, it allows the

N_
& (1§

$———— +3.75

(2) POSITIVE EDGE TRIGGERED {END H,RESET H}
B

voltage at the test point to start going negative until it reaches the forward bias level of diode D1. This level is

9601

t—

Q2 is cut off. Therefore, the only output at this time is the current through R4 and RS, which is negligible.
Operation of the current generator is triggered by the negative-going TSS L signal from the memory control cir-

'—T—*Nv—o#-\')V

Current Generator Waveforms

Figure 2-12

- e S DS

R6 determines the rise time as Q2 conducts to provide the read current. The write current is developed in the
same manner. There are actually two circuits (R3 and Q2) in parallel.
The value of the output current is:

+5V (-VbeQ2 * VbeD1) -Vref
R3

This value is approximately 250 mA per circuit, or approximately 500 mA for the two circuits. The amplitude of
the current output waveform is determined by the setting of the V REF trimpot. Resistors R4 and RS, and diodes
D2 and D3 in the output lines, are used to isolate the read switches from the write switches.

Although not shown on the schematic, a resistor and thermistor on the memory stack (see drawing MM11-F-03)
are connected to the voltage reference portion of the current generator. These components automatically track

the current amplitude with temperature to ensure that the amplitude remains within specified tolerances over the

temperature range of 0° C to 50° C.
2.7 CONTROL AND TIMING LOGIC
The memory control and timing logic circuits perform three basic functions:
a.

Decode the incoming address (bits *13 through 17) to determine if the memory has been selected
to engage in a data transfer

@——_L/

S~LIMITED B’

Latch the address bits controlling the X and Y lines (bits *A1 through A12) to ensure that the
proper core location is selected
11-0090

*When memory is interleaved, bits 1 and 13 are interchanged.

Figure 2-13

M7290 One-Shot Delays

2.7.1

2.7.3 X-Y Address Latching

General

All memory operations are started by the generation ofa memory select (MSEL) signal. This signal is initiated on

Bus address lines *1 through 12 are used to select the X and Y lines that select the desired core location (refer to

receipt of a MSYN (inaster sync) signal from the controlling device, a device select (D SEL) signal from the mem-

Paragraph 2.4). Bits *1 through 6 select Y lines, and bits 7 through 12 select the X lines.

ory address (*A13, Al4 through A17) decoding circuits, and a DC OK signal. These signals indicate, respectively,

When the bus master generates MSYN, the full 18-bit address appears at the memory control circuits. The five
most significant bits are used by the device selection circuits (refer to Paragraph 2.7.2). The next 12 bits are gated
into a flip-flop register. If the bit is low on the bus, it qualifies a gate that sets a corresponding flip-flop. If the

that a master device has control of the Unibus, that the master device has selected the core memory as a slave de-

vice, and that the dc power level to the memory circuits is within specified tolerances. The three signals set the
MSEL flip-flop to produce the memory select signal. This signal remains asserted until either the END WRITE or

bit is high on the bus, the gate is not qualified and the corresponding flip-flop remains cleared. The flip-flop is set

END PAUSE signal clears the flip-flop to indicate that the selected memory operation is complete. The MSEL

low rather than high because of the negative logic used by the Unibus. The original X-Y address from the master

flip-flop also acts as a memory busy signal by prohibiting a new cycle from starting until MSEL is cleared.

device is now stored in the flip-flop register to be used by the decoding circuits during the selected memory oper-

The bus master places appropriate levels on the two bus C lines to select the type of memory operation to be per-

formed. The data placed on these lines by the master to select a specific operation is shown in Table 2-3.
+

Table 2-3

ation. An asserted address bit is high (+3V) inside the memory.

Bus address line 0 is used for byte selection. The level on line O passes through a gate and is stored in a flip-flop
in the same manner as the X-Y address lines. The output of the flip-flop represents either byte 1 when set or byte
0 when not set and is applied to the memory control circuits described in Paragraph 2.7.7.

Selection of Memory Operation

C Line

Octal

Selected

State

Equivalent

Memory Operation

COH,CIH

2.7.4 Data In (DATI) Control Circuits

A DATI operation indicates that a selected location in memory is to be read and the information transferred
through the Unibus into the master device. Because the core memory is a destructive readout device, the data

DATI

COL,C1H

DATIP

must be restored to the selected location after the read operation. Therefore, a DATI is basically a read /restore

COH,CIL

DATO

(read/write) operation.

COL.,C1L,A0H

DATOB 0

COL,CIL,AOL

DATOB 1

In the following discussion, assume that all flip-flops are initially in the RESET state. When the M SEL flip-flop is
in the zero state, MSYN L is low, SSYN L is high, DSEL H is high, and the M SEL flip-flop qualifies an AND gate

2.7.2 Device Selection

Whenever a master dcvice addresses ai.other peripheral as a slave, the address is applied to all peripherals connected

to the Unibus. Therefore, it is necessary for each peripheral to have a method of recognizing its own address and
ignoring other addresses. The device selection circuits serve this purpose. The 18-bit address from the master device is used for both device selection and selection of the X-Y matrix. This paragraph covers the memory device
selection circuits and Paragraph 2.7.3 covers the X-Y selection.

Bus address lines *13, 14 through 17 are used for device selection. The selection logic is dependent upon jumpers

to produce a CLK 1 H pulse that latches the address and C lines from the bus. The CLK 1 H pulse is also gated
through an OR gate to set the DEL flip-flop 0 low, which starts a negative pulse through the delay line. When the
pulse comes out of the delay line, it resets the DEL flip-flop. In the interim, outputs from taps on the delay line
generate the read timing chain. The TSS H, TIG L, and TDR H signals are gated into the address decoders to enable the current paths through the X and Y switches and drivers. The CLK | H pulse also passes through a delay

line to set the M SEL flip-flop. The TIG L signal turns on the current driver; the TSS H and TDR H signals enable

the decoding matrix so that the selected core location receives the read currents. After the data register flip-flops
have been reset, the current flowing through the selected cores produces an output to the sense amplifier for every

connected to the input of a seven-input AND gate, 74H30. The device address is hard wired. If, for example, the

bit position having a logical 1 (refer to Paragraph 2.8).

desired bit is to be 0, a jumper is connected to the inverter output of the address buffer and ties this signal to the

When the strobe delay is completed, a STROBE H pulse is generated and applied to the sense amplifier. If, during

74H30 gate. When a 0 is placed on the associated bus line, that leg of the 74H30 gate is qualified. It produces an
output if all of the other four inputs to the gate are satisfied. If the bus line has a binary 1, that device selection
gate leg is not qualified and the 74H30 gate cannot be qualified. On the other hand, if a binary 1 is desired in the
address code, a jumper is connected directly from the SP 380 to the input of the 74H30 gate, bypassing the inverter gate for that line. This causes the 74H30 gate to be qualified whenever a 1 is present on the bus line. In this
manner, any combination of 1s and Os can be preselected as the device address. When the proper signals are pre-

strobe time, a sense amplifier has an input exceeding the threshold level, the amplifier direct sets the associated
flip-flop. The STROBE pulse is 50 +10 ns wide. This width is fixed and cannot be changed. The STROBE DEL
trimpot is factory adjusted so that the STROBE pulse occurs 220 ns after the read current is turned on (measured
from the 10 percent point of the current) to ensure that core transitions are compared to the threshold level of the

sense amplifiers at the proper time for best overall memory margins in the temperature range from 0° to 50° C.

sent on bus address lines *13, 14 through 17, the 74H30 gate is qualified and produces a low output which, when

The STROBE pulse is gated with C1 H and then gated through an OR gate to trigger a positive-edge circuit which

inverted, is the device select (D SEL) signal. This signal indicates that the master device has selected the core mem-

produces a negative pulse that direct sets the SSYN flip-flop. The output of the SSYN flip-flop is gated with C1 L

ory as the slave device.

through an inverter to produce the DATA OUT H signal. The SSYN output also gates a bus driver to produce the
BUS SSYN L signal. The DATA OUT H signal gates the outputs of the data register flip-flops onto the Unibus
through the open collector bus drivers.

*When memory is interleaved, bits | and 13 are interchanged.

2-8

*When memory is interleaved, bits 1 and 13 are interchanged.

In effect, the memory places data from the selected core location on the Unibus data lines and asserts SSYN to

the data register D lines. A LOAD H is then generated and applied to the data register C lines. When the LOAD H

inform the master device that it can now strobe in the data. After the master device strobes the data, it raises

pulse is generated, the data register flip-flops are set or remain cleared corresponding to the 1s or Os on the associ-

MSYN L which causes the memory control to produce a SSYN CLK signal, which resets the SSYN flip-flop. This

ated bus data lines. This action loads the data from the bus into the data register.

action completes the read portion of the memory cycle. The memory then immediately enters the restore portion
of the DATI cycle.

Between the end of the read cycle and the beginning of the restore cycle, all signals revert to their initial condi-

Just after the LOAD H signal is generated, the TSS and TDR signals are produced to enable the switches and driv-

ers in the X and Y selection matrices. The inhibit (INH) signals are produced as described previously. Write currents flow through the selected core locations. The current flowing through the selected core writes 1s into all

tions with the exception of the M SEL signal. Although MSYN is dropped, the M SEL flip-flop remains set be-

cores not inhibited. This causes the core memory location to contain the data stored in the data register. Thus,

cause it can only be cleared by an M SEL RESET signal which is not generated until the end of the write (restore)

data from the Unibus has been transferred into the selected core memory location.

cycle. The DEL flip-flop is reset by the DEL R signal at the end of the read cycle.

During a DATO or DATOB operation with the pause flag set, the SSYN signal is generated soon after the CLK 1

When the READ flip-flop is reset by ANDing the READ H and END H signals, a WRITE H level is generated. The

H signal is generated. The SSYN flip-flop is reset when the bus master device drops MSYN. The pause flag is re-

WRITE H level is combined with PAUSE L through an AND gate and then passes through an OR gate to set the

set when SSYN is generated. The M SEL flip-flop is cleared when the PS L, WR H, and RST pulses are ANDed

DEL flip-flop 0 low, which starts a pulse through the delay line to generate the'write timing chain.

together. This completes the write operation and all memory control circuits are in their original conditions.

The TSS H and TDR H signals are gated into the address decoder to enable the current paths through the X and
Y switches and drivers. The TIG L pulse turns on the current drivers. The INH H pulse functions in the manner

2.7.6 Data Out (DATO) Control Circuits

described in Paragraph 2.9. The current flowing through the X and Y switching circuits writes s into all cores
not inhibited and the contents of the memory locations are restored to their original states. After this occurs, the

RST H signal is ANDed with WRITE H and PS L to produce the RESET M SEL signal that ctears the M SEL flipfiop. While set, the M SEL flip-flop locks out the MSYN L signal so that a new cycle cannot be started until this
cycle is completed.

A DATO operation indicates that the master device is to transfer data through the bus into the core memory for
storage. In effect, the memory is to write data into the selected core location. It is necessary to clear the selected
cores before writing; thus, the memory first performs a read cycle and then writes new data into the location.
The read portion ofa DATO operation is similar to the read portion of a DATI operation except that no RESET

O L, RESET 1 L, STROBE 0O H, or STROBE | H pulses are generated. When the master device asserts MSYN, it

2.7.5 Data In, Pause (DATIP) Control Circuits

causes the M SEL, CLK 1 H, CLK 2 H, and READ signals to be produced. The LOAD 0 H and LOAD 1 H signals,

A DATIP operation indicates that a selected memory location is to be read out and the information transferred

together with the data on the bus D lines, are applied to the data register. The data register flip-flops are set or

through the Unibus to the master device. Although the memory is a destructive readout device, the restore cycle
is not entered because DATIP indicates that new data is to be stored in the memory location.

cleared in accordance with the data that is on the bus lines. The CLK 1 H pulse triggers the address flip-flops that
produce the enabling signals for the address matrix in order to establish the proper current return paths. After
this sequence is complete, the selected cores receive read current and perform the 1 to O transition, thereby clear-

The read portion of a DATIP is identical to that ofa DATI (refer to Paragraph 2.7.4) until the time the SSYN sig-

ing the cores. This transition does not enter the data register because no STROBE 0 H or STROBE 1 H

nal is produced. At this point, the output of the SSYN flip-flop and the output of the DATIP gate (from bus line

are produced to gate the transitions out of the sense amplifiers.

signals

C1) are applied to the PAUSE flip-flop, thereby setting it. This action produces PAUSE L which is the pause flag.
The END H pulse is ANDed with READ H to ctear the R/W flip-flop. The DP H and READ H levels are ANDed

with the RST pulse to clear the M SEL flip-flop; the memory control circuits revert to their original states with
the exception of the pause flag, which remains set. The restore (or write) portion of the memory cycle is inhibited.
Regardless of which operation is defined, the pause flag prevents the READ flip-flop from being set at the start of

This completes the read portion of the DATO cycle. All cores are in a O state and the data that had been on the
bus is now stored in the data register. When the READ signal drops (the pause flag is cleared), a write cycle is initiated. The X-and Y-matrix enabling levels are supplied along with the inhibit signals to gate data from the data
register into the selected core location during the write cycle as described previously.

the next cycle, thus forcing the next cycle to be either a DATO or DATOB. Therefore, the next time memory is
selected, it performs a write only operation.

During normal memory operation, it is always necessary to read the memory before writing into it. This read operation magnetically changes all cores to zero, thereby clearing all cores before new data is written into them. In
the case of a write operation (DATO or DATOB) following a DATIP, the normal read operation is not necessary

because the cores have already been zeroed by the previous DATIP read operation. Note, however, that the DATO
cycle following a DATIP is not identical to the DATO cycle that follows a DATL. In the former case, the pause
flag is set; in the latter case, the pause flag is cleared. A discussion of a DATO operation with the pause flag cleared
is covered in Paragraph 2.7.6.
The DATO operation associated with a DATIP begins when the master device asserts MSYN in order to start the

timing sequence as described previously. The CLK 1 H pulse is generated as before; however, because the pause

2.7.7 Data Out, Byte (DATOB) Control Circuits
A DATOB operation is the same as a DATO operation except a byte, rather than a full word, is transferred. In the

case ofa DATOB, a RESET O or 1 L and STROBE 0 or ! H signal are produced for the non-selected byte. This
process effectively strobes the byte into the data register for restoration during the write operation, because this
byte has not been selected to receive new data. A LOAD O or 1 H pulse is not provided for the non-selected byte;

therefore, any data on the bus has no effect on the non-selected byte.
The selected byte is controlled in just the opposite manner. Neither RESET O or 1 L nor STROBE 0 or 1 H is generated because it is not necessary to restore the byte. A LOAD 0 or 1 H pulse is provided, however, so that data

from the bus can be written into the selected byte location.

flag is set, no READ H signal is produced. The READ flip-flop remains cleared and produces a WRITE H output.

At the end of the DATOB operation, the selected byte has new information; the non-selected byte retains its pre-

Data from the bus master device is already applied through the input buffers to the D lines that are connected to

vious data.

DIODE

ITNEREEN

750

=C1

INHo—8

12opt

INSENENN]

RT
Loy

%5;(

TITTrTTT

+5v

AND

BALUN

__/\—’

R“Lo

J’

T STROBEH

SUTRUT

LOW ACTIVE

STROBEH
-5.2v

/ —»

DIOODE

-6.8V

AND

EFFECTIVE
THRESHOLD

BALUN

@2V

380

|- TO iNH GATE
SATER

BUS

7474
LOAD H—fc

7aHO1-)

RESETL

DATAOUT H—{ 8881

RESET
L
o
MC 1540
OUTPUT

] —l

I +5v
N
N

CExT
!

DIFF

AMP

-6.8V

GAIN IS =~

OTL GATE

OUTPUT

out
STROBE

7474 0,

ReCT [}

BIAS

-5.2 THRESH

DATAQUT H

BUS

/
11-00898

BLOCK DIAGRAM MC 1540
11-00894

Figure 2-14

2-10

Sense Amplifier Detector Circuit

2.8 READ OPERATION

2.9 WRITE OPERATION

This paragraph is devoted to an explanation of the read operation. The actual controf signals that govern the read

During a DATO operation, the word to be written into core memory is loaded into the data register flip-flops from

cycle are covered in Paragraph 2.7, This section covers read operation only from the standpoint of the core mem-

the data lines when a load pulse is applied to each of the flip-flops in the register. Whenever the input from the

ory itself.

data line is a 1, the load pulse (high) and the binary 1 set the flip-flop to the 1 state.

Whenever a word is to be read from memory, a read current passes through the address decoder and related X and

Y switches and drivers to the selected core. The read current is a half-select current in both the X and Y windings.

If the input from the data

line is 0, then the flip-flop remains cleared. The resultant states of the 16 flip-flops represent the word to be writ-

ten into memory. During a write/restore cycle, the contents of the data register (from reading) are written.

Since read current flows in the opposite direction of write current, all cores in the selected word previously set to

When the write cycle begins, an inhibit signal is applied to an inhibit driver (AND gate) for each line.

the | state are switched to the O state; cores previously set to O remain unchanged.

qualified (flip-flop set to 0), the gate enables an inhibit pulse. This inhibit pulse causes a current path through the

To make read current opposite

If the gate is

to write current, positive drivers and negative switches are used for reading, and negative drivers and positive

core opposing the Y write current to prevent a core from being set into a 1 state. If the flip-flop is set, represent-

switches are used for writing.

ing a 1, the gate is not qualified, no inhibit signal is generated, and the write currents set the selected core to the 1

A more detaifed explanation of the switches and drivers is given in Paragraph 2.5,

A sense/inhibit termination circuit (referred to as Circuit 1 on logic drawing MM 11-F-04) and sense amplifier are

state. Thus, the data word stored in the register is written into the appropriate core memory location.

provided for each of the 16 mats in the memory. The input to each amplifier comes from a sense/inhibit winding

Figure 2-15 is a schematic of the inhibit driver. When it is desired to write a O and the inhibit current (Link) goes

that passes through every core on the associated mat.

high, the 74H40 gate turns on and its output goes to ground. Current i, is determined by resistor R1 and the re-

I, during the rcad operation, the addressed core in a mat

makes the | to O transition, the flux change induces a current in the sense/inhibit winding of that mat. This cur-

flected base-emitter voltage (Vie) ofoutput transistor Q1. Current iy equals i, and turns on transistor Q1. When

rent develops a voltage pulse at the input to the amplifier circuit.

QI turus on, current flows from ground, through the Balun transtormer (which equalizes the two half-currents),

The input is amplified and (after strobed thresh-

old detection) used to set a flip-flop in the data register when the strobe pulse is applied to the amplifier.
The threshold tevel (voltage slice) is a factory-set level of -5.2V. Whenever a core makes the 1 to O transition, the

through the isolation diodes and the sense/inhibit winding, to the common inhibit terminal. Current then fiows
through resistor R2 and transistor Q1 to -15V.

resultant induced voltage is sufficient to exceed the preset threshold level during strobe time and causes the amTigh

inht

plifier to produce an output. Addressed cores that were already in the 0 state induce only a limited amount of

15V -Vee sat QVbe diodes

16.9 + mat§? (~2.0)

current into the sensc/inhibit windings when saturated by the full-select current. However, the voltage level pro-

duced by this noise is insufficient to reach the threshold level during strobe time and activate the amplifier. Therefore, the data flip-flop for that bit location remains cleared, indicating a logic 0 in that location.
After the sense amplifier outputs have been strobed into the data register, the data register flip-flops are set for
each bit position containing a 1. When the control logic generates a data out pulse, the high outputs (1s) from all

of the flip-flops that are set in the data register are gated through drivers onto the data bus for transfer to the processor or master device.
logic.

Note that the bus driver output is low for a Jogical | because the Unibus employs negative

150812 oo

16.9 + 2.0

Each winding sees nearly 345 mA. Capacitor C2 speeds up the rise time of the current. At turn-off time, the inductance of the stack winding would normally push the voltage at the switch (Q1) quite positive; however, the

diode at the collector of
Q1 clamps this voltage to ground. Capacitor C1 helps turn on Q1 faster and allows the
74H40 gate to provide reverse current to turn off Q1.

Any 0 output from the data register is not gated, and a logical 0 remains on the bus for those bit positions.
-

This type of readout destroys the contents of the addressed memory location (by switching all cores to 0); thus,
the data stored in the datu register must be put back into the cores to restore the memory location to its original
contents. This is accomplished by immediately following the read cycle with a write (restore) cycle.

" R2 16.90

Note, how-

cver, that this write cycle is delayed whenever a DATIP operation is performed, becausc it is not necessary to restore the contents of the memory.

In effect, the memory pauses and waits for new data to be written into the

Figure 2-14 is a circuit schematic of the sense amplifier detector circuit. At sense time, the effect of the inlibit

TINHH

drivers, isolation diodes, and Balun transformer can be ignored due to the high impedance of these components.

DATAOH

The voltage signal is developed on the sense line and propagates through a twisted pair of wires to the sense am-

core location. The restore cycle is the same as a normal write cycle as described in Puragraph 2.9,

—

74H40

2
—
i

Tinh

LH_J
ce

INH
WINDING

’

Hiah

‘2

Linh

finh

-15V

plifier module. The input to the MC 1540 Module is an impedance matching network used to terminate the sense

line. The MC 1540 amplifies the difference signal approximately 85 times and rectifies it. The signal is ac-coupled
through an external capacitor and superimposed upon a de bias which is controlled by the threshold input. During strobe time, if the dc bias plus the coupled core signal exceeds the DTL gate threshold, its output goes to
ground. This sets the 7474 flip-flop by means of a direct set gate. At the start ol each read cycle, the 7474 {lip11-0080

flop is reset by means of the direct reset gate. In a DATO operation, the data is shifted from the bus through the
SP 380 inverter to the D input of the 7474 flip-flop and clocked into the flip-flop by a LOAD H pulse.

Figure 2-15

Inhibit Driver

CHAPTER 3

MAINTENANCE

3.1

INTRODUCTION

3.2.2 Initial Procedures

This chapter contains maintenance and adjustment procedures for the MM11-F Core Memory. Adjustment proce-

Before attempting to check or adjust the core memory, perform the following steps:

dures are covered in Paragraph 3.2, and maintenance is covered in Paragraph 3.3.

NOTE

All tests and adjustments must be performed in an ambient

temperature range of 20° C to 30° C (68° F to 86° F).

3.2 ADJUSTMENTS
There are three adjustments that can be performed on the core memory: voltage reference (V REF), voltage slice

(V SLICE), and strobe delay (STROBE DEL). It is usually not necessary to make any of these adjustments unless
a module has been replaced. If, however, the memory is not functioning properly, check these adjustments before
attempting to troubleshoot the memory.

Step
1

Table 3-1

V REF

Location

Trimpot on current generator

B3U2

Verify that power buses are not shorted together.

Turn primary power on and make certain that both -15V and +5V (£5 percent) power is present.

Purpose

Trimpot on V levels Module

Start the system. Memory should now cycle without errors. If not, check
adjustments in Paragraphs 3.2.3, 3.2.4, and 3.2.5. If memory still does not
function properly, a malfunction is indicated.

Sets reference voltage for X-Y current.

Module G225

V SLICE

Visually check for broken wires, connectors, modules, or other obvious defects.

Core Memory Adjustments

Adjustment

Verify that all modules shown in the MUL print MM 11-F-06 are properly

installed in the backboard.

The purpose of each of the three adjustments is given in Table 3-1. Specific adjustment procedures are given in
subsequent paragraphs.

Procedure

3.2.3 Voltage Reference (V REF) Adjustment

D2F1

Sets threshold level of sense amplifier.

G103

The voltage reference (V REF) sets the amplitude of the X-Y current and is measured at pin B3U2 of the Current
Generator Module G225. This voltage should be in the range of +0.70V to +1.90V at an ambient temperature of

STROBE

STROBE DEL trimpot on con-

B3K1

Sets delay time of strobe pulse used dur-

30° C(86° F). The voltage fluctuates with temperature variations, going more positive as the temperature increases.

DELAY

trol and timing Module M729

E281

ing read cycle.

If the reference voltage must be reset, perform the following adjustment procedure:
Step

3.2.1 Equipment Required

The following test equipments are used when checking or adjusting the MM11-F Core Memory.

Tektronix 453 or 547 oscilloscope with dual trace plug in, voltage probes

Honeywell 333R Digital Voltmeter (or equivalent 0.5 percent DVM)

Procedure
Cycle the memory using a worst-case patterns program.
Use the V REF trimpot on the current generator module to vary the reference voltage to the points where memory fails (both high voltage and low

voltage). The system must have a margin of at least 0.80V, i.e., there must
be an interval 0.80V wide in which the system functions properly.

Set the V REF at a point midway between the worst-case limits of operation.

NOTE

If the margin is greater than 1.0V, set V REF at 0.5V below the failing high

Although the digital voltmeter is not mandatory, it can be help-

end point. (Examples of margins are 0.4V to 1.8V set at 1.3V, 1.3V equals

ful when performing the procedures in this section.

1.8V minus 0.5V.) To effect this condition, adjust the trimpot on the current

(continued on next page)

3-1

3.3 MAINTENANCE

Step

Procedure

generator for a reference voltage that is midway between the lowest voltage

The basic maintenance philosophy of PDP-11 manuals presents information on normal system operation. The user

(cont)

causing the memory to fail at the high end and the highest voltage causing

can utilize this information to analyze trouble symptoms and extrapolate necessary corrective action. This para-

the memory to fail at the low end.

graph provides additional maintenance information to aid the user in isolating and correcting malfunctions.

Figure 3-2 illustrates the sense/inhibit waveforms; Figure 3-3 illustrates drive waveforms. Both figures include
3.2.4 Voltage Slice (V SLICE) Adjustment

schematics to indicate the points in the circuit where the waveforms occur. In addition to the normal waveforms,

The voltage threshold (V SLICE) adjustment must be performed whenever a G103 Discharge Circuit Module is

dotted lines are used to indicate the waveform that appears if a component is faulty.
Table 3-2 is a troubleshooting chart that indicates possible malfunctions, probable causes, and corrective actions.

replaced. The adjustment procedure is as follows:

Step

Procedure

Paragraph 3.4 describes DEC program tests that serve as an aid to maintenance and troubleshooting.

Measure V SLICE at pin D2F1 of the sense amplifier with respect to ground.

Verify that the measured voltage is -5.2V (£0.2V).

If the voltage is not within the above tolerance, adjust V SLICE trimpot on

Table 3.2

;

able

MM11-F Troubleshooting Guide

the G103 Module until the voltage is within the specified tolerance.

Symptom
Picks up bits

Affects
All bits

Possible Cause(s)
X-Y current too high

Corrective Action
Check V REF and reset per
set-up procedure.

3.2.5 Strobe (STROBE DEL) Adjustment

Al bits

Strobe oceurs oo early

Module (current generator module) is replaced. 1f necessary, the strobe adjustment should be reset.

All bits

-15V input low

The STROBE DEL adjustment should be checked whenever an M729 Module (Control and Timing) or a G225

Reset STROBE DEL to 210

ns on M7290 Module.

Reset or repair H720 Power
Supply

NOTE
The adjustment of the STROBE DEL trimpot on the M729
Module is critical. The setting should only be changed when
absolutely necessary.

Figure 3-1 illustrates the proper setting of the strobe pulse. If required, adjust the STROBE DEL trimpot so that

Onene bitot

Inhibit
driver i
tive; i
h'j'bf i ‘;‘.’e’ Inoperative; in-

Repair
G102 Modul
Repaf’ Clo8 Vod“f'

All bits

Threshoid too low (less than

Reset V SLICE to -5.2V on

-5.2V)

G103 Module.

it winding open

isset set t to 210 ns +S
£3 ns ns.

odule.

Some bits in one byte | Sense amplifier reset; inoper-

Repair M7290 Module

8 or 16 bits

TINH H inoperative

Check M7290, G225 Module

All bits at high temp.

Stack thermistor or resistor

Check components and wir-

ative for that byte

T STROBE is

epair

ing to G225 Module.

+5v

T STROBE

T
'

I
3.5y

E1k1
CURRENT GENERATOR

TEST POINT

Drop bits

All bits
-

All bits

X-Y Current too low

Reset V REF or repair G225
Module.

Strobe too early or too late

Reset STROBE DEL on

M7290 Module.

:
i
|

All bits

Threshold too high

Reset V SLICE on G103

All bits, 64 locations

Open line in memory

Ring out stack (read or write)

All bits, 8 locations

Bad switch or driver

Troubleshoot and repair

Module

G226 Module.
One bit, all words

TsTROBEM ..

Bad sense line or sense chain

Troubleshoot and repair

(bus receiver, latch, sense

G102 Module.

amplifier, or bus driver}
GND
11-0081

Figure 3-1

Strobe Pulse Waveform

Some bits, one byte

STROBE inoperative, LOAD

Troubleshoot and repair

inoperative for that byte

M7290 Module.
(continued on page 3-5)

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11-00924

Figure 3-3

Drive Waveforms

—+5V INOP WNDR

----Dotted line show possibie

8251 DECODER

TORH

INOP RPDR

11-00928

Table 3-2 (Cont)

3.4.3 No Dual Address Test (MainDEC-11-DICA)

MM11-E Troubleshooting Guide

Symptom

Affects

Drop bits

All bits at low temp.

(cont)
No response to

The purpose of the No Dual Address Test program is to check the unique selection of each memory address tested.

Possible Cause(s)

Corrective Action

Stack themistor or resistor

No device select

MSYNL

Check components and wir-

first test location. This is followed by a read check from this location. The program then checks each field loca-

ing to G225 Module.

tion to ensure there are no variations from the 1s configuration. Upon completion of this

Check M1091 Module jum-

pointer is incremented. The next location is then write-read exercised with Os and the test field rechecked for any

All bits

forms a DATIP

test, the test location

change in content. When the selected test field has been tested in this mode, the program sets a flag and the sec-

pers and gates.

ond portion of the test is begun. The program fills the test field with Os and the field is then tested with a write-

MSEL not reset on previous

Check M7290 Module cir-

cycle

cuits.

read exercised with 1s.

SSYN not reset on previous

Check M7290 Module cir-

This program checks for faulty switches or wiring errors, checks the complete address selection scheme, and checks

cycle

cuits.

all 16 bits in the data field for 1s and Os operation.

SSYN not setting

Memory always per-

This test is divided into two parts. The first portion of the test fills the test field with 1s and writes Os into the

PROTECT L input to M7290 |

Check M7290 Module cir-

cuits.

3.4.4 Basic Memory Patterns Test (MainDEC-11-DIDA)

Check and repair.

The Basic Memory Patterns Test program has two main purposes:

Module grounded

3.4 PROGRAMMING TESTS

Verify that the selected memory test field is capable of writing and reading fixed data patterns.

Verify that the memory plane is properly strung.

This test program writes a specific pattern throughout a given memory zone, then reads the pattern back and com-

Certain DEC programs can be used to test various memory operations as an aid to troubleshooting. The purpose

pares it with the original for correctness. If the pattern read fails to compare correctly with the original, the pro-

of each of these memory-related test programs, as well as the program abstract, is given in the following paragraphs.

gram initiates a call to the error subroutine. After completely checking the pattern, the program continues on to
the next pattern test.

3.4.1 Address Test Up (MainDEC-11-DIAA)

3.4.5 Worst Case Noise Test (MainDEC-11-DIGA)

The purpose of the Address Test Up program is to demonstrate that the selected memory area is capable

of basic

read and write operations when address propagation is upward through memory.

The purpose of the Worst Case Noise Test program is to generate the maximum possible amount of plane noise
during execution of memory reference instructions to check system operation under worst case conditions.

This test program writes the address of each memory location (within the test limits) into itself and then increments through memory until the address corresponding to the high limit is reached. After this location
has been
written, the memory enters the read cycle. The read cycle starts with the high limit location and reads
and compares each word location, decrementing down to the low limit location. The program halts on an error.

This program checks that all addresses are selectable and can also be used to isolate bad switches, wiring errors,

This test program is designed to produce the greatest amount of plane noise possible during memory read and
write cycles, The noise parameters are effected by a number of factors; therefore, the test is designed to test all
conditions arising out of the four standard memory construction configurations. The noise generated is distrib-

uted across the core plane algebraically and adds to the normal dynamic noise present on the sense lines. This can
cause misreading of data (within the plane) that is in the low (1) or high (0) category. The sense windings of most
memories are such that worst case patterns can be caused by alternately writing -1 and O data configurations

or address selection errors.

throughout memory. Under these conditions, worst case noise is generated by performing a read, write, complement, read, write, complement, operation at each location. The test is repeated after complementing all of the

3.4.2 Address Test Down (MainDEC-11-DIBA)

pattern data stored in the memory test zone.

The purpose of the Address Test Down porgram is to demonstrate that the selected memory area is capable of
basic read and write operations when address propagation is downward through memory.

It is a companion test

to the Address Test Up program (Paragraph 3.4.1).

This test deviates from this form of testing only in the distribution of the -1 and 0 data patterns within the memory test zone. The constraint placed on this test requires writing the complement of the data pattern as described

by the exclusive OR of the second bit of the X and Y selection lines. These bits correspond to address bits 1 and

This test program writes the address of each location into itself, downward through memory. After writing down,

8. Therefore, the pattern, or its complement, is written into the memory test zone as determined by the exclusive

the program reads and checks back up through the memory test area. The program halts on an error.

OR between address bits 1 and 8.

The Address Test Down program resides in the high portion of core memory. It does not check memory below

The Worst Case Noise Test program is divided into two parts. Part 1 is run first and, during this part of the pro-

address 100, as these locations are reserved for trap and vector locations. The program verifies that all modules

gram, a -1 configuration is written into all locations having an address with an exclusive OR state between bits 1

can perform their basic functions, checks that all addresses are selectable, and can also be used to isolate faulty

and 8. All other locations are loaded with the O configuration. After the test zone has been loaded, the memory

switches, wiring errors, or address selection errots.

is rescanned. This time, each location is read, complemented, read, and complemented (RCRC). Any location

3-5

detected as being disturbed by a previous RCRC operation is flagged as an error. Upon conclusion of the read
scan loop, the program automatically switches to Part 2.

During Part 2 of the program, the data patterns stored in memory are complemented. In other words, O patterns

are stored in locations having addresses with an exclusive OR between bits 1 and 8. All other locations are loaded
with the -1 configuration.

The exclusive OR pattern distribution for Parts 1 and 2 is summarized for reference as follows:
Part 1

Exclusive OR (1 and 8) = -1 pattern
No Exclusive OR (1 and 8) = O pattern
Part 2

Exclusive OR {1 and 8) = 0 pattern
No Exclusive OR (1 and 8) = -1 pattern

After memory is loaded, it is scanned again with a read, complement, read, complement (RCRC) loop as described
previously. Any location detected as being disturbed by a previous RCRC operation is flagged as an error.
Before writing or reading any location (in either part of the program), the program issues a call to subroutine
XORCK (exclusive OR check) which tests bits | and 8 and sets the XORFLG if the exclusive OR condition is
present.

Subroutine ERRORA is called for any location disturbed from the -1 configuration; subroutine ERRORB is called
for any location disturbed from the 0 configuration.

The program prints out errors and repeats when complete without interruption. Upon completion, the program

tings the Teletype® bell and then halts if switch 12 is present. A continue from the halt initiates another pass.
If the program indicates an error, the failure may be due to a faulty memory stack, not enough twist in the SA-SB
twisted pairs, a faulty sense/inhibit card, incorrect strobe setting, incorrect threshold setting, incorrect current setting, or power inputs that are out of tolerance.
NOTE

In any interleaved memory, the bits that determine the worst
case pattern are bits 8 and 13 rather than bits 8 and 1.

®l"eletype is a registered trademark of Teletype Corporation.
3-6

APPENDIX A

PARITY OPTION

A parity option is available for use with the MM 11-F Core Memory. When this option is installed, the memory is

an 18-bit memory with bit 16 used for byte 0 parity and bit 17 used for byte 1 parity. Installation of this option
consists of replacing the H207 Memory Stack with the H210 Memory Stack and installing the G108 Sense/Inhibit
Module into location E1.

All MM11-F Core Memories come wired and documented as 18-bit systems. Therefore, only the H210 stack change
and the addition of the G108 are needed to convert the system to an 18-bit system with parity capabilities.
The H210, which is a 19-bit memory stack, is pin compatible with the H207 16-bit memory stack. Note that one
bit of the H210 is not used so that it functions as an 18-bit memory stack.

The two-bit sense/inhibit module enables the memory system to read and write parity data into and out of memory. The data bits on the bus are called BUS DPB0 and BUS DPB1. Stack bits 17 and 18 are used for this function. Note that one bit (DPB0) on this module has common strobe, reset, and load with byte 0. The other bit is

common to byte 1.

APPENDIX B

INTERLEAVING

When the address register is incremented by one (alternate states of BAO! L) on successive memory cycles, the
cycles are performed within a 4K memory bank and cannot be overlapped. If, however, address bit BUS AQ1 L
(inside the memory) is interchanged with BUS A13 L, it causes successive memory cycles to be performed within

alternate memory banks. This allows the cycles to be overlapped; that is, the second memory bank can start its
cycle before the first memory bank has completed its cycle, provided the bus is free. This effect is called memory
interleaving and causes the typical program to be executed faster.
Note that interleaving affects 8K blocks. For example, if a system has a 12K memory, only the first 8K is interleaved. If the system had 16K of memory, the first 8K would be interleaved and the second 8K would also be
interleaved.
Interleaving an 8K block in the MM11-F core memory is accomplished by changing the jumpers on the M1091

module on the Device Select Module, M1091, drawing B-CS-M1091-0-1.
It should be noted that any 8K block of memory delivered from DEC is automatically interleaved.