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EB-23144-18

1983

642 pages

Original

17MB

Document:	PDP-11 Microcomputer Interfaces Handbook
Order Number:	EB-23144-18
Revision:	0
Pages:	642
Original Filename:	EB-23144-18_QbusIntrfs_1983.pdf

OCR Text

Microcomputer Interfaces
Handbook
~DmDDmD

DIGITAL Facility, Hudson, Massachusetts

CORPORATE PROFILE
Digital Equipment Corporation designs, manufactures, sells and services
computers and associated peripheral equipment, and related software and
supplies. The Company's products are used world - wide in a wide variety
of applications and programs, including scientific research, computation,
communications, education, data analysis, industrial control, timesharing,
commercial data processing, word processing, health care, instrumentation,
engineering and simulation.

CO'ler- Flanked by two DIGITAL interface board modules- the
IBV11-A instrument bus interface and the DPV11-DA serial synchronous line interface- is DIGITAL 's first available serial line communications chip interface- the DC319-AA DLART. The DLART represents
DIGITAL's latest advancement and commitment to an even lower level
of integration than board-level components, while still providing proven PDP-11 architecture. System and hardware designers, as well as
other customers will find this new level of integration an attractive alternative for application designs based on chip-level microcomputerbased products, including implementation of DIGITAL's new family of
chip-level processors- the T-11, the F-11,and the J-11.

Microcomputer Interfaces
Handbook

Copyright© 1983 Digital Equipment Corporation.
All Rights Reserved.
Digital Equipment Corporation makes no representation that the interconnection of its products in the manner described herein will
not infringe on existing or future patent rights, nor do the descriptions contained herein imply the granting of license to make, use,
or sell equipment constructed in accordance with this description.
The information in this document is subject to change without notice
and should not be construed as a commitment by Digital Equipment
Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this manual.
DEC, DECnet, DECsystem-10, DECSYSTEM-20, DECtape
DECUS, DECwriter, DIBOL, Digital logo, lAS, MASSBUS, OMNIBUS
PDP, PDT, RSTS, RSX, SBI, UNIBUS, VAX, VMS, VT
are trademarks of
Digital Equipment Corporation
This handbook was designed, produced, and typeset
by DIGITAL:s New Products Marketing Group
using an in-house text-processing system.

CONTENTS
PART 1

INTRODUCTION

LSI-11 FAMI LY CHARACTERISTICS .
SPECIFICATIONS. . . . . . . . . .
DESCRIPTION OF OPTION CATEGORIES.
CONFIGURATION . . . . . . . . . . . .
PART 2

. 1

.4
.5
25

LSI-11 BUS INTERFACE DESCRIPTIONS

AAV11-A 4-ChanneI12-Bit D/A Converter.
AAV11-C 4-ChanneI12-Bit D/A Converter.
ADV11-A Analog-to-Digital Converter
ADV11-C Analog-to-Digital Converter
AXV11-C Analog Input/Output Board.
BA11-M Expansion Box. . . . . .
BA 11-N Mounting Box. . . . . . . .
BA11-S Mounting/Expander Box. . .
BA11-VA Expansion Mounting Box .
BDV11 Diagnostic, Bootstrap, Terminator.
DC319-AA DLART Asynchronous Receiver/Transmitter.
DCK11-AA,-AC Program Transfer Interface. . . .
DCK11-AB,-AD Direct Memory Access Interface .
DDV11-B Backplane. . . . . . . . . .
DLV11 Serial Line Unit . . . . . . . .
DLV11-E Asynchronous Line Interface. . .
DLV11-F Asynchronous Line Interface.
DLV11-J Four Asynchronous Serial Interfaces .
DMV11 Synchronous Line Controller. . . . .
DLV11-KA EIA to 20 rnA Converter. . . . . .
DPV11-DA Synchronous Serial Line Interface
DRV11 Parallel Line Unit . . . . . . . . .
DRV11-B Direct Memory Access Interface.
DRV11-J High-Density Parallel Interface .
DRV11-P LSI-11 Bus Foundation Module.
DUV11 Line Interface. . . . . . .
DZV11 Asynchronous Multiplexer . . . .
H780 Power Supply. . . . . . . . . . .
H909C General Purpose Logic Enclosure
H9270 Backplane. . . . . . . . . . . .

29
37
45
53
70
88
95
.104
.113
.116
.144
. 160
. 190
.205
.211
.217
.238
.258
.509*
.287
.520*
.293
.314
.338
.342
.347
. 352
. 357
.364
.366

* This interface product appears out of the alphanumeric sequence in
this handbook because it was included just prior to publication.
iii

H9273-A Backplane.
H9275-A Backplane.
H9276 Backplane . .
H9281 Backplane . .
I BV11-A I nstrument Bus Interface .
KPV11-A, -B, -C Power-FaiIlLine-Time Clock/Terminator
KWV11-A Programmable Realtime Clock. . . . . . . .
KWV11-C Programmable Realtime Clock . . . . . . .
LPV11 Printer Option . . . . . . . . . . . . . . . . .
REV11-A Terminator, REV11-C DMA Refresh, Bootstrap
RLV12 Disk Controller. . .
RXV11 Floppy Disk Option . .
RXV21 Floppy Disk Option . .
TU58 Cartridge Tape Drive . . .
VK170-CA Serial Video Module
W9500 Series High-Density Wire-Wrappable Modules

APPENDIX

.372
.376

.383
-.387
.393
.415

.420
.426
.449
.457
.556*
.459
.465
.487
.495
.504

A ASSIGNMENT OF
ADDRESSES AND VECTORS

. . 567

B ASYNCHRONOUS SERIAL LINE UNIT (SLU)
COMPARISONS. . . . . . . . . . . . ..

..585

C COMPARISON OF DATA TRANSMISSION
TECHNIQUES. . . . . . . . . . . .

.593

APPENDIX

D BUS RECEIVERS AND BUS DRIVERS

.596

APPENDIX

E CABLING SUMMARY . . .

.599

APPENDIX

F LSI-11 DOCUMENTATION.

.601

INDEX . . . . . . . . . . . . . . . . . .

.612

APPENDIX

* This interface product appears out of the alphanumeric sequence in
this handbook because it was included just prior to publication.

PREFACE
The 1983-84 Microcomputer Interfaces Handbook is the companion
publication to the 1982 Microcomputers and Memories Handbook.
Designed in the form of a catalog, the purpose of this handbook is to
provide DIGITAL customers with quick and handy reference material
"'"
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11 bus. Though user applications may vary widely, the detailed logic,
configuration, and installation information presented in this handbook should be sufficient to satisfy their needs. In most cases
throughout this handbook, the interfaces have a detailed introductory
section, a features section, specifications, configuration, and descriptive narrative- especially on the newer interface products. The major
product sections in the handbook include: Interface Options, Communications Options, Peripherals, Backplanes, Enclosures (boxes), Cabinets, Power Supplies, Cables and Connectors, Intergrated Circuits,
and miscellaneous options available for DIGITAL'S diverse family of
both board-level and systems-based microcomputers.
A major goal of this handbook is to present the most recently introduced interface products and still provide needed but basic information on the older interface products. Detailed passages on 11 new interface products are currently found in this handbook, including a new
family of analog I/O boards- the AAV11-C, the ADV11-C, and the
AXV11-C; the KWV11-C programmable realtime clock; the H9275-A
and H9276 backplanes; the BA11-S mounting/expander box; the
DPV11-DA synchronous serial line interface; the DMV11 synchronous
line controller; the RLV12 disk controller; and for the first time, we are
including a section on the new serial line communications chip interface- the DC319-AA DLART. Passag"es on the DPV11-DA, the DMV11,
and the RLV12 appear at the end of Part 2 of this handbook. These
three interface products are out of alphanumeric sequence because
they were included (immediately) prior to the time of publication.
Since this handbook was last published, many DIGITAL microcomputer interface products that were written about extensively then are
currently not necessarily the most technically advanced or newest
ones available. For example, in a case where a customer who still
uses the AAV11-A four-channel 12-bit D/A converter, a DIGITAL interface introduced a few years back, information pertaining to this interface was found in the first few pages of the 1981 Microcomputer interfaces Handbook. In this handbook, however, an abbreviated version
briefly introduces and describes its features and benefits, and lists its
specifications. Appendix F in the back of this handbook lists all the
documention and order numbers needed to supplement these older

products. For users requiring extensive information on some of these
microcomputer interfaces, this appendix lists all the necessary reference material, at several levels of technicality, including user documents, configuration guides, and data sheets.
A section devoted to mass storage peripherals will be covered in a future handbook. For users desiring information on DIGITAL's memory
offerings and detailed information on LSI-11 bus signals, please consult the 1982 Microcomputers and Memories Handbook. The order
code for the Microcomputer and Memories Handbook is EB-20912-20.

vii

viii

INTRODUCTION
This handbook is a reference guide for interface and peripheral hardware options that can be installed on the LSI-11 bus. It includes descriptions, specifications, configuration information, programming information as applicable to the options, and functional theory.
Because the hardware options described in this handbook are designed to interface with a processor via the LSI-11 bus, the user
should be familiar with the contents of the 1982 Microcomputer and
Memories Handbook.
The 1983-84 Microcomputer Interfaces Handbook is organized into
two parts. Part 1 contains general information about microcomputer
interfaces. Part 2 contains descriptions of the interface options in alphanumeric sequence.
Digital Equipment Corporation designs and manufacturers the options described in this handbook. Our general design criterion is to
provide maximum system throughput for options when they are installed on the LSI-11 bus. LSI-11 bus-compatible processors, interfaces, and peripherals are designed to work together to provide a
broad spectrum of system-compatible hardware options. Memory and
peripheral devices can be used with various LSI-11 bus configurations
and the system can later be expanded or modified to meet new system
requirements. This hardware flexibility, when coupled with DIGITAL
software and support, provides a single source for all present and future mLcrocomputer processing needs.

LSI·11 FAMILY CHARACTERISTICS
LSI-11 bus systems include various processors, memory and peripheral device options, and software. Some of the characteristics of the
LSI-11 bus systems are:
• Low-cost powerful components for integration into any small- or
medium-sized computer system.
• Direct addressing of all memory locations and peripheral device registers.
• Efficient processing of 8-bit bytes (characters) without the need to
rotate, swap, or mask.
• Asynchronous bus operation that allows system components to
run at their highest possible speed; replacement with faster devices
means faster operation without other hardware or software
changes .
• A module component design that provides ease and flexibility in
configuring systems.
1

INTRODUCTION
• Inherent direct memory access capabilities for high data rate devices.
• A bus structure that provides position-dependent priority for peripheral device interfaces connected to the 1/0 bus.
• Vectored interrupts that allow service routine entry without device
polling.
Processors
The processor is connected to the LSI-11 bus (backplane) as a subsystem that executes programs and arbitrates usage of the LSI-11 bus for
peripherals. It contains multiple, high-speed, general-purpose registers that can be used as accumulators, address pointers, index registers, and other specialized functions. The processor can perform data
transfers directly between peripheral input/output (110) devices and
memory without disturbing the processor registers. Data transfers include both 16-bit word and 8-bit byte data.
LSI-11 Bus
System components, including the processor, memory, and peripherals, are interconnected and communicate with each other via the LSI11 bus. The form of communication is the same for all devices on the
bus; instructions that communicate with memory can communicate
with peripheral devices. Each device, including memory locations and
peripheral device registers, is assigned an individual byte or word address on the LSI-11 bus.
The LSI-11 bus supports 16-, 18-, and 22-bit addresses. However, processors and peripherals having a 22-bit addressing capability are completely PDP-11 hardware- and software-compatible within the 18-bit or
16-bit limitation. Simarily, 18-bit addressing devices are downwardcompatible to 16-bit addressing. By PDP-11 convention, all peripheral
device addresses are located within the upper 4K address space in the
system, whether 16-bit or 18-bit addresses are used. This 4K'address
space is called the 110 page or "bank 7."
Whenever the 110 page is addressed, the processor must assert the
BBS7 L bus signal. All peripheral devices use this signal line during
addressing rather than decoding address bits < 15:13>or< 17:13>. An
active (asserted) BBS7 L signal will always indicate an address in the II
o page, enabling peripheral device addressing.
Peripheral device addresses within the I/O page are decoded by each
peripheral device. Each peripheral device will include one or more "device register(s)." These registers can be accessed under program con2

INTRODUCTION
trol in exactly the same manner as memory locations. Unique addresses within the 1/0 page are encoded on address bits < 15:00 >.
NOTE
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logical states present on LSI-11 bus signal lines
BDAL<17:00>L during the addressing portion of a
bus cycle.
Refer to the appropriate processor handbook for a complete description of bus transactions, including bus cycles, addressing, etc.
Device Registers

All peripheral devices are defined by one or more device registers that
are addressed as part of the main memory. These registers are generally designated control and status registers.
Control and status registers (CSRs) contain all the necessary information to establish communications with the device. Some devices will
require fewer than 16 status bits, while other devices could require
more than 16 bits and therefore will require additional registers. The
bits of the CSR have predetermined assigned functions. Typical bit
functions include interrupt enable, error, done or ready, and enabled.
Data buffer registers (DBRs) are for temporarily storing data to be
transferred into and out of the processor. The number and type of data
registers is a function of the individual peripheral device requirements.
Interrupts

Interrupts allow devices to obtain processor service when they are
"ready" for service, or "done" with a specific operation. The interrupt
structure allows the processor to execute other programs while one or
more peripherals are "busy." When a peripheral requires service it requests an interrupt. The processor completes execution of the present
instruction, saves PC and PS words on the stack, and acknowledges
the interrupt. The highest priority peripheral device currently requesting interrupt service responds by inputting its interrupt vector address
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to two memory locations containing the PC (starting address) and PS
for the peripheral device interrupt service routine. Program control is
transferred from the interrupted program to the routine associated
with the requesting peripheral device. Note that no device polling is
required, since the interrupt/vector is unique for that device. Once the

INTRODUCTION
device service routine execution has been completed, control is returned either to the previously interrupted program or to another peripheral device requesting interrupt service.

Memory Address
Memory addresses are generally limited to the address space other
than the I/O page. However, the I/O page can contain read-only memory (ROM) for disk bootstraps, paper tape loaders, diagnostics, etc. or
read/write memory for DMA buffers. The system designer must use
care in assigning memory addresses within the I/O page to avoid conflicts with peripheral device addresses used for actual system hardware, or addresses that system software may attempt to access for
peripheral devices not actually installed in the system. See Appendix
A for the standard assignments of the addresses in the I/O page.
SPECI FICATIONS
All the LSI-11 bus modules will operate under the following conditions:

Temperature
Humidity

to 60 0 C (41 0 to 1400 F)
10 to 95% (no condensation)

When operating at the maximum outlet temperature (60 0 Cor 1400 F),
adequate air flow must be maintained to control the inlet to outlet
temperature rise across the modules to 50 C (9 0 F) maximum. The air
flow should be directed to flow across the modules.
All the individual module specifications are included in the detailed
descriptions of the peripheral or option. A summary of the module
characteristics is provided in Table 2; these characteristics are defi ned as follows:
1. The option designation is the alphanumerical code assigned to
the option.
2. The module number is the number assigned to the interface modules that are connected to the LSI-11 bus. This number is printed
on the module handle and can be used as a quick reference to
determine what specific options are installed in any system. The
module numbers are listed numerically in Table 3 so that the user
can identify the options installed by using the module numbers.
3. The module description identifies the category of the option.
4. The power requirements specify the power by the option when
connected to the bus backplane. These requirements are used to
determine the total power supply loading within a Single system.
4

INTRODUCTION
5.
6.

The bus loads for ac and dc loading are provided so that the user
can calculate the total ac and dc loading for any system.
The interface modules are standarized as either a double or a
quad and all are extended length. The double size module is 13.2
cm (5.2 in.) high, 22.8 cm (8.9 in.) long, and 1.27 cm (0.5 in.) wide.
The quad size module is 26.5 cm (10.5 in.) high, 22.8 cm (8.9 in.)
long, and 1.27 cm (0.5 in.) wide (Figure 1).

DESCRIPTION OF OPTION CATEGORIES

The LSI-11 bus peripherals and options are classified into general categories that pertain to their performance and function. This listing indicates the wide span of equipment capability available to the user.
Interface Options

AAV11-A

The AAV11-A is a 4-channel, 12-bit digital-to-analog converter module that includes control and
interfacing circuits. It has four D/A converters, a
dc-dc converter that provides power to the analog circuits, and a precision voltage reference.
Each channel has its own holding register that
can be addressed separately and provides 12
bits of resolution. Bits 0, 1, 2, and 3 of the fourth
holding register are brought out to the 1/0 connector so that they can be used as a 4-bit digital
output register.

AAV11-C

The AAV11-C is a 4-channel, 12-bit digital-to-analog converter module that has four individually
addressable, separately controlled digital-to-analog converters (DACs), each with 12 bits of resolution. Each DAC can be written or read in either
word or byte format. One of the DACs also has
four digital output bits for creating control signals to an analog instrument. The D/A converters
accept data from a program controlled interface
in either a binary notation for unipolar output, or
offset binary for bipolar output.

ADV11-A

The ADV11-A is a 12-bit successive approximation analog-to-digital converter that samples analog data at specified rates and stores the
digital equivalent value for processing. The mul-

INTRODUCTION
tiplexer can accommodate up to 16 single-ended
or 8 quasi-differential inputs. The converter uses
a patented auto-zeroing design that measures
othe sampled data with respect to its own offset
and therefore cancels out its own offset error.
External event inputs can originate at the user's
equipment or from the Schmitt trigger output of
the KWV11-A clock. Three reference signals are
provided for self-testing any channel input.
These signals consist of two dc levels and one
bipolar triangular waveform. This output can be
used with DIGITAL diagnostic software to produce a data base for extremely precise analog
linearity testing.
ADV11-C

The ADV11-C is a dual-height LSI-11 bus module
that performs analog-to-digital conversions. It
may be configured to provide either 16 singleended, 16 pseudo-differential, or eight true-differential analog input channels with input full scale
ranges of either 0 to 10V or -10V to 10V. This
board is designed to interface analog instrumentation to the LSI-11 bus, and is suitable for use in
a wide variety of industrial and laboratory LSI-11
microcomputer applications such as data acquisition/display, process control, and signal analysis.
The ADV11's precision instrumentation amplifier, under software control, may be programmed
to amplify input signals by factors of 1, 2, 4, or 8
before being digitized by the AID converter. This
programmable gain feature provides effective input signal full scale ranges of 10V, 5V, 2.5V, and
1.25V, respectively, especially useful for maintaining maximum resolution of input signals that
fall below 50% of the 12-bit AID converter's 10V
range.

AXV11-C

The AXV11-C is a cost-effective analog I/O interface board that has 16 single-ended analog input
channels. The AXV11-C offers all the features of
the ADV11-C plus two analog output channels,

INTRODUCTION
each with 12-bit D/A converters. Each D/A converter generates an output signal with full 12-bit
accuracy and resolution. The D/A's accept data
in either binary, offset binary, or two's complement notation.
DRV11

The DRV11 is a parallel interface module that is
used to interconnect the LSI-11 bus with generalpurpose, parallel line TIL or DTL devices. It allows program-controlled data transfers at rates
up to 40K words per second and uses LSI-11 bus
interface and control logic to generate interrupts
and process vector handling. The data are handled by 16 diode-clamped input lines and 16
latched output lines. There are two 40-pin connectors on the module for user interface applications.

DRV11-8

The DRV11-8 is an interface module that uses direct memory access (DMA) to transfer data directly between the system memory and an I/O
device. The interface is programmed by the processor to move variable length blocks of 8- or 16bit data words to or from specified locations in
the system memory. Once programmed, there is
no processor intervention required. The module
can transfer up to 250K 16-bit words per second
in the single-cycle mode and up to 500K 16-bit
words per second in the burst mode. It also allows read-modify write operations.

DRV11-J

Sixty-four input/output data lines are now available on a double-height module for the LSI-11/2,
LSI-11/23, PDP-11103, and PDP-11/23. The DRV11J also includes an advanced interrupt structure
with bit interruptability up to 16 lines, programmable interrupt vectors, and program selection of
fixed or rotating interrupt priority within the
DRVll-j. The DRVll-j's bit interrupts for reaitime response make it especially useful for sensor I/O applications. It can also be used as a
general-purpose interface to custom devices,
and two DRV11-Js can be connected back-toback as a link between two LSI-11 buses.
7

INTRODUCTION
DRV11-P

The DRV11-P is a foundation wire-wrap interface
module with a 40-pin I/O connector. Approximately 25 percent of the module is occupied by
bus transceivers, interrupt vector generation logic, device comparator logic, protocol logic, and
interrupt logic. The remaining 75 percent is for
user applications; this portion has platedthrough holes for securing ICs and wire-wrap
pins for interconnecting the user's curcuits. The
plated-through holes can accept 6-, 8-,14-,18-,
20-,22-,24-, and 40-pin dual-in-line integrated circuits or discrete components.

IBV11-A

The IBV11-A is an interface module that interconnects the LSI-11 bus with the instrument bus
described in IEEE standard 4881975, "Digital Interface for Programmable Instrumentation." The
IBV11-A makes a processor-controlled programmable instrument system possible. The
module can accommodate up to 15IEEE-488 devices and is PDP-11 software-compatible.

KWV11-A

The KWV11-A is a programmable real-time clock!
counter that provides a means of determining
time intervals or counting events. It can be used
to generate interrupts to the processor at
predetermined intervals or establish timing between input and output events. It can also initialize the ADV11-A analog-to-digital converter by a
clock counter overflow or by firing a Schmitt trigger. The clock counter has a resolution of 16 bits
and can be driven by anyone of five crystal-controlled frequencies (100 Hz to 1 MHz), from a line
frequency input, or from a Schmitt trigger fired
by an external input. The module can operate in
any of four programmable modes: single interval,
repeated interval, external event timing, and external event timing from zero base.

KWV11-C

The KWV11-C, like the KWV11-A, is a programmable real-time clock!counter that provides a variety of means for determining time intervals or
counting events. It can generate interrupts to the

INTRODUCTION
processor at predetermined intervals or establish timing between input and output events. It is
used to start the ADV11-C analog-to-digital converter or the AXV11-C analog 1/0 module, either
by clock counter overflow or by the firing of a
Schmitt trigger. The KWV11-C's two Schmitt
triggers each have integral slope and level controls. The Schmitt triggers permit the user to
start the clock, initiate AID conversions, or generate program interrupts in response to external
events.

Communications Options
DLV11

The DLV11 is a serial line unit (SLU) that interfaces with asynchronous serial 1/0 devices. The
module has jumper-selectable baud rates (509600) and serial word format that includes the
number of stop bits, number of data bits, and
even, odd, or no parity bit. The DLV11 can support 20 rnA current loop interfaces or EIA "data
leads only" interfaces.

DLV11-E

The DLV11-E is an asynchronous line interface
module that interconnects the LSI-11 bus to
standard serial communications lines. The module receives serial data, converts it to parallel
data, and transfers it to the LSI-11 bus. Also, it
accepts parallel data from the LSI-11 bus, converts it to serial data, and transmits it to the peripheral device. The module has jumper-selectable or software-selectable baud rates (5019,200), and jumper-selectable data bit formats.
The DLV11-E offers full modem control for EIAI
CCID interfaces.

DLV11-F

The DLV11-F is an asynchronous line interface
module that interconnects the LSI-11 bus to several types of standard serial communications
lines. The module receives serial data, converts
it to parallel data, and transfers it to the LSI-11
"bus; it,also accepts·parallelc·data from the LSI-11
bus; converts it to serial data, and transmits it to

INTRODUCTION
the peripheral device. The module has jumper-selectable or software-selectable baud rates (5019,200) and jumper-selectable data bits. The
DLV11-F supports either 20 mA current loop or
EIA standard lines, but does not include modem
control.
DLV11-J

The DLV11-J contains four independent asynchronous serial line channels used to interface
peripheral devices to the LSI-11 bus. Each channel transmits and receives data from the peripheral device over EIA data leads (lines that do not
use a control line). The module can be used with
20 mA current loop devices if a DLV11-KA adapter is used. The DLV11-J has jumper-selectable
baud rates from 150 to 38.4 K baud.

DUV11

The DUV11 synchronous line interface module
establishes a data communication line between
the LSI-11 bus and a Bell 201 synchronous
modem or equivalent. The module is fully programmable with respect to sync characters,
character length (to to 8 bits), and parity selection. The receiver logic accepts serial data for
the LSI-11 bus. The transmitter logic converts
the parallel LSI-11 bus data into serial data for
the transmission line. The interface logic converts the TIL logic levels to the EIA voltage levels required by the Bell 201 modems and also
controls the modem for half-duplex or full-duplex
operation.

DZV11

The DZV11 is an asynchronous multipJexer interface module that interconnects the LSI-11 bus
with up to four asynchronous serial data communications channels. The module provides EIA interface voltage levels and data set control to permit dial-up (auto-answer) options with full-duplex
modems such as Bell models 103,113,212, or
equivalent. The DZV11 does not support half-duplex operations or the secondary transmit and
receive operations available in some modems
such as Bell 202. The DZV11 has applications in

INTRODUCTION
data concentration and collection systems
where front -end systems interface to a host computer and for use in a cluster controller for terminal applications.

Peripherals
LPV11

The LPV11 printer option consists of an interface
module, an interface cable, and either an LP05 or
LA180 line printer. The interface module provides
programmed control of data transfers and provides printer strobe signals appropriate for either
printer. The LA180 DECprinter is a high-speed
printer that prints 180 characters per second and
the LP05 printer can print 240 or 300 lines per
minute, depending on which model is selected.

RXV11

The RXV11 option consists of an interface module, cable assembly, and either a single or dual
drive RX01 floppy disk. This option is a random
access mass storage device that stores data in
fixed-length blocks on a preformattedflexible
diskette. Each diskette can store and retrieve up
to 256K, 8-bit bytes of data. The RXV11 system is
rack mountable in the standard 48.3 cm (19 in.)
cabinet.

RXV21

The RXV21 floppy disk option is a random access mass memory device that stores data in
fixed-length blocks on a preformatted, flexible
diskette. Each diskette can store and retrieve up
to 512K 8-bit bytes of data. The RXV21 system is
rack-mountable and consists of an interface
module, an interface cable, and either a single or
dual RX02 floppy disk drive. The interface module converts the RX02 1/0 bus to the LSI-11 bus
structure. it controis the RX02 interrupts to the
processor, decodes device addresses for register
selection, and handles the data interchange between the RX02 and the processor via DMA
transfers. Power for the interface module is supplied by the LSI-11 bus.
11

INTRODUCTION
TU58

VK170-CA

The TU58 is a low-cost intelligent mass memory
device that offers random access to block-formatted data on pocket-size cartridge media. It is
ideal as inexpensive archive mass storage or as
a software update distribution medium. A dual
drive TU58 offers 512 Kb of storage space, making it one of the lowest cost complete mass storage subsystems available. For mounting flexibility, the TU58 is offered both as a component level
subsystem and as a fully powered 5 Y2" rackmount subsystem.
The VK170 module forms an integral part of a terminal. The module accepts serial ASCII encoded
data to be stored in a refresh memory to generate a display for a video monitor. The VK170
also accepts parallel data from a keyboard (on
strobe demand) to generate serial ASCII output.
The VK170 is an extended-length, double-height
board. Mounting holes are provided for stand-off
mounting via handle rivets and two holes located near the module fingers.

Backplanes
The following backplane options are available for the LSI-11 bus:
H9270
A 4 x 4 (four rows of four slots each) backplane
with card guide assembly. LSI-11 bus in rows A8 and CoO. Accepts 8 double-height modules or 4
quad-height modules or combinations of both.
H9273-A

A 9 x 4 (nine rows of four slots each) backplane
with card guide assembly. LSI-11 bus in rows A8 only. Special interconnect bus in rows CoO. Accepts double-height or quad-height modules.

H9275-A

A 9 x 4 (nine rows of four slots each) backplane
with card guide assembly. LSI-11 bus in rows A8 and CoO. Accepts up to 18 dual-height modules
or nine quad-height modules or a mixture of
both. Supports 4 megabyte (22-bit) addressing
capability.

H9276

A 9 x 4 (nine rows of four slots each) backplane.
Extended LSI-11 bus in rows A-B. C-O rows are
12

INTRODUCTION
special interconnect bus rows. Accepts both
double- and quad-height LSI-11 modules for use
in a 22-bit addressing system. Can be used as a
mounting box or as an expander box.
H9281

A 2-slot backplane available in 4-, 8-, or 12-slot
options. Accepts double-height modules only.

DDV11-B

A 9 x 6 (nine rows of six slots each) backplane.
LSI-11 bus in rows A-B and C-D. Rows E-F are unbussed except for + 5V and ground. Accepts 18
double-height or 9 quad-height modules or combinations of both.

Enclosures
H909-C

A 13.3 cm (5.25 in) high, 48.3 cm (19 in) wide enclosure which can be mounted in a 48.3 cm (19
in) rack or as a stand-alone. Accommodates the
DDV11-B backplane or a 9 x 6 system mounting
unit or houses non-standard mounting arrangement. Includes cooling fan, cord guide, cable restraints, front bezel, and connector block.

BA11-M

A 8.9 cm (3.5 in) high, 48.3 cm (19 in) wide expansion box which can be mounted in 48.3 cm (19 in)
rack. Includes H9270 backplane, H780 power
supply, blank front panel or bezel, and cooling
fan.

BA11-N

A 13.2 cm (5.19 in) high, 48.3 cm (19 in) wide
mounting box which can be mounted in a 48.3
cm (19 in) rack. Includes H9273-A backplane,
H786 power supply, H403-A ac input panel, blank
front panel or bezel, and cooling fan.

BA11-S

A 13.2 cm (5.19 in) high, 48.3 cm (19 in) wide
mounting or expander box. It can be installed in
a standard 48.3 em (19 in) rack. Includes H9276
backplane, H7861 power supply, H403-B ac input
box, a blank front bezel or bezel assembly with
switches and indicators, and two cooling fans.

INTRODUCTION
BA11-VA

The BA11-VA is a small form-factor package providing mounting space and power for four LSI-111
2 or LSI-11/23 family modules. This package,
plus the high functionality of DIGITAL's microcomputer products, allows LSI-11 microcomputer applications to be implemented within a
space smaller than that required for many 8-bit
systems.

Power Supplies
H780

Provides + 5V ± 4%, 18 A (max) and + 12V ± 3%,
3.5 A (max) at 110 Vac and features line-time
clock, and power-fail/automatic restart. Available
primary power of 115 or 230 Vac and with or without master and slave console.

Cables and Connectors
Various preassembled cables in different
lengths are available for use with interface and
communications options. See Appendix E for
commonly used cables.

Wire-Wrappable Modules
W9500 Series: LSI·11 Bus·Compatible Wire·Wrappable Modules
(W9511, W9512, W9514 AND W9515) - The LSI-11 bus-compatible
wire-wrappable modules consist of quad-height and double-height
modules. Two LSI-11 bus-compatible modules are available without
01 P sockets.
Quad-height, extended-length, single-width
W9511
module with extractor handle. No DIP sockets included. One 40-pin male cable connector premounted on board and space for
additional 40-pin connector provided.
Power and ground connections are Vee BA2, CA2, DA2
GND -AT1, BT1, CT1, DT1, AC2, BC2, CC2,
DC2
W9514

Same as W9511 except with 58 pre-mounted 01 P sockets.

INTRODUCTION
Power and ground connections are the
same as W9511
W9512

Double-height, extended-length, single,.,irHh
l'T'\t"\nlllo
u,ith t=linJ'hin
h""nrlle 1'\11"\
VVI""""
111"' .... U v ... 11.11 I
"t",r"'llIl'-' I I Q I I U I • • 'V

DIP sockets included. One 40-pin male connector premounted on board.
Power and ground connections are
GND-AT1, BT1,AC2, BC2
W9515

Same as W9512 except with 25 pre-mounted DIP sockets.
Power and ground connections are the
same as W9512

Integrated Circuits
The DC319-AA DLART is a DL-compatible, asynDC319-AA
chronous receiver/transmitter designed for data
DLART
communications with Digital's microprocessor
family. Programmed by the CPU to operate either
in 8-bit or 16-bit mode with asynchronous baud
rates ranging from 300 to 38.4K, the DLART accepts data characters from the CPU in parallel
format and converts them into a continuous serial data stream for transmission. Simultaneously,
the DLART can receive serial data streams and
convert them into parallel data characters for the
CPU.
DCK11-AA, -AC

The DCK11-AA and -AC CHIPKITs provide the
logic necessary for a program transfer interface
to the LSI-11 bus. The DCK11-AA kit contains
one DC0031nterrupt Chip, one DC004 Protocol
Chip, and four DC005 Transceiver/Address Decoder/Vector Select Chips. The DCK11-AC kit
contains previous chips plus one W9512 doubleheight, extended length, high-density wire-wrappabie moduie and one BC07D-iO ten-foot, 40connector plug-in cable.

DCK11-AB, -AD

The DCK11-AB and -AD CHIPKITs provide the
logic necessary for a Direct Memory Access
(DMA) interface to the LSI-11 bus.
15

INTRODUCTION
The DCK11-AB kit contains one DC003 Interrupt Chip, one DCOO4 Protocol Chip, four DCOO5
Transceiver! Address DecoderlVector Select
Chips, two DCOO6 Word Count!Bus Address
Chips, and one DC010 DMA Control Chip. The
DCK11-AD kit contains the previous chips plus
one W9512 double-height, extended-length, highdensity wire-wrappable module and one BC07D10 ten-foot, 40-connector plug-in cable. DMA applications use the same chips as program
control interfaces, plus two DC006s for word or
byte address counters and a DC010 DMA bus
controllC.

Miscellaneous Options
BDV11
The BDV11 module has 2K words of read-only
memory (ROM) that contains diagnostic and
bootstrap programs. These programs are userselectable by setting dip switches. The diagnostic programs will test the processor, the memory,
and the user's console. The bootstrap programs
can boot most LSI-11 peripheral devices. The
module also has 120-0hm bus terminator circuits.
The user can add up to 16K of read-only memory
(ROM) and up to 2K words of erasable programmable ROM (EPROM) on the module. This 18K
words of additional memory can be used with no
increase in the amount of I/O address space.
KPV11-A, -B, -C

The KPV11-A module generates power-up and
power-down sequences, monitors for a powerfail condition, and generates the line-time clock
(LTC) function. The KPV11-B is the same as the
"A" except that it provides 120-ohm termination
circuits. The KPV11-C is the same as the "A" except that it provides 220-ohm termination circuits. The module can be installed on any backplane or remotely installed via an optional cable.

INTRODUCTION
REV11-A, -C

The REV11-C module has a bootstrap ROM and
direct memory access (DMA) refresh circuits.
The REV11-A is identical to the REV11-C except
it has additional 120-ohm termination circuits.

TEV11

The TEV11 is a bus terminator module that provides 120-ohm bus termination circuits.

DLV11

The DMV11 is a microprocessor- controlled communications interface that permits Direqt Memory Access (DMA) data transfers. The controller
converts parallel data from the LSI-11 bus to serial data for line transmission and serial data
from the the line to parallel data for the LSI-11
bus. The serial data is transferred synchronously
over private or leased telephone lines or through
shie1ded cables for local operation. The controller performs the detailed protocol operations, including character and message synchronization,
header and message formatting, error checking,
and transmission control.

DPV11-DA

The DPV11-DA is an single-line, program-controlled, double-buffered communication device
designed to interface the LSI-11 bus to highspeed serial synchronous lines for use in many
commercial, industrial, and scientific applications, such as remote batch, remote data collection, remote concentration and communication
networking. The self-contained DPV11-DA can
handle a wide variety of protocols.

RLV12

The RLV12 disk controller interfaces RL01 and
RL02 disk drives to any quad- or hex-size backplane that uses a 16-,18-, or 22-bit LSI-11 bus.
One RLV12 can control up to four RL01 and RL02
disk drives, in any combination. The RLV12 has
LSI-11 bus transceivers and decoders, programmable registers, controller timing and
sequence logic, and data formatting circuits to
read and write on the disk.

Table 1
Option
Desig.

Module
No(s).

Description

Module Specifications
Power Requirements

Bus Loads·

+5V
+5%

AC(Max)

Size

1.9

Quad

0.9

1.0

Double

3.25

Quad

AAV11-A

A6001

4-channel, 12-bit
0/ A converter

1.5 A

AAV11-C

A6006

4-channel, 12-bit
0/A converter

2.0A

ADV11-A

A012

16-channel, 12-bit

20.A

+12V
+3%
OAA

0045 A

AID converter
ADV11-C

A8000

16 single-ended or 8
1.5 A
differential AID channels,
12-bit

1.3

1.0

Double

AXV11-C

A0026

Analog I/O board
16 single-ended analog
input channels, 12-bits
2 0/A output, 12-bit
channels

1.5 A

1.3

1.0

Double

Bootstrap,
terminator,
diagnostic

1.6A

.....

BDV11

DDV11-B

M8012

6 X 9 backplane

-Z-I

0
C
c:

0.07 A

2.0

604

Quad

• These ac load figures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.

Table 1
Option
Deslg.

Module
No(s).

Power Requirements
+5V
+12V
+5%
+3%

Bus Loads·
AC(Max)

Size

DLV11

M7940

Asynchronous serial
line interface

1.0A

0.1BA

2.5

Double

DLV11-E

MB017

Asynchronous line
interface

1.0A

0.1BA

1.6

Double

DLV11-F

MB02B

Asynchronous line
interface

1.0A

0.1BA

2.2

Double

MB043

4 asynchronous
serial interfaces

1.0A

0.25A

Double

DPV11

MB020

Synchronous
serial line interface

1.2A

0.30A

1.0

Double

Synchronous
line controller

4.7 A

0.3BA

2.0

1.0

Quad

DMV11

-I

DLV11-J
~

Description

Module Specifications (cont.)

0
C
c:
0

-I

DRV11

M7941

Parallel line unit
interface

0.9A

1.4

Double

DRV11-8

M7950

DMA interface

1.9A

3.3

Quad

DRV11-J

MB049

64-line parallel 1/0

1.6A

2.0

Double

DRV11-P

M794B

Foundation
module

1.0A
+ user logic

2.1

Quad

1.BA

• These ac load fi~Jures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor is 9.35 pF/ac
load. These numbers are nominal values which wili tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.

Table 1
Option
Desig.

I\)

Module
No(s).

Description

Module Specifications (cont.)
Power Requirements

Bus Loads*

+5V
+5%

+12V
+3%

AC(Max)

Size

DUV11

M7951

Synchronous serial
line interface

0.86 A

0.32

1.00

Quad

DZV11

M7957

Asynchronous
line interface

1.15 A

0.39

3.95

Quad

H9270

4 X 4 backplane

5.1

H9273

4 X 9 backplane

2.6

H9275-A

4 X 9 backplane

10.0

H9276

4 X 9 backplane

2.6

H9281A

2 X 4 backplane

1.3

H9281B

2 X 8 backplane

2.4

H9281C

2 X 12 backplane

3.6

1.9

Double

2.4

Quad

IBV11-A

M7954

Instrument bus
interface

0.8A

KD11-F

M7264

LSI-11 CPU
4KRAM

1.8A

0.8A

Z
::rJ
-I

0
C
c:
0

-0-I
Z

* These ac load figures were measured using standardTDR (time domain reflectometry) techniques. The conversion factor is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.

Table 1
Option
Desig.

Module
No(s).

Description

Module Specifications (cont.)
Power Requirements

Bus Loads*

+5V
+5%

+12V
+3%

AC(Max)

Size

KD11-H

M7264-YA

LSI-11 CPU
without RAM

1.6A

0.25

2.4

Quad

KD11-HA

M7270

LSI-11/2 CPU

1.0A

0.22A

1.7

Double

KDF-11

M8186

LSI-11/23 CPU

2.0A

0.2 A

2.0

Double

KPV11-A

M8016

Power-faililinetime clock

0.56A

1.63

Double

KPV11-B

M8016-YB

Power-fail/linetime clockl120 Q
bus terminator

0.56

1.63

Double

I\)

.......

Z
-t

:lJ

KPV11-C

M8016-YC

Power-fail/linetime clockl220 Q
bus terminator

0.56A

1.63

KUV-11

M8018

WCS module

3.0A

KWV11-A

M7952

Programmable
real-time clock

1.75A

0.01 A

KWV11-C

A4002

Programmable
real-time clock

1.75A

0.1 A

Double

Quad

3.4

Quad

1.0

Double

* These ac load figures were measured using standard TDR (time domain reflectometry) techniques. The conversion factor is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.

-0-t
Z

Table 1
Option
Desig.

Module
No(s).

Description

Module Specifications (cont.)
Power Requirements

Bus Loads*

+5V
±5%

AC(Max)

Size

+12V
±3%

LPV11

M8027

LA180/LP05
printer interface

0.8A

1.4

Double

MRV11-AA

M7942

4K X 16 read-only
memory (less
PROM intergr'ated
circuits)

O.4M

1.8

Double

(with 32512 X 4
PROM integrated
circuits)
(MRV11-AC)

2.8A

UV PROMRAM (less PROM
integrated circuits

0.58A

0.34 A

(with81KX8
PROM integrated
circuits)
(MRV11-BC)

0.62 A

0.5A

N
N

MRV11-BA

M8021

-Z

-I

:a
0
C

-Z

-I

0
2.8

Double

* These ac load figures were measured using standard TDR (time domain reflectometry) techniques. The conversion factor is 9.35 pFlac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.

Table 1
Option
Desig.

Module
No(s).

Power Requirements
Description

+5V
±5%

+12V
+3%

Bus Loads·
AC(Max)

Size

2.0

Double

MRV11-C

MB04B

PROM/ROM module

O.B A

MSV11-8

M7944

4K X 16 read/write
MaS memory

0.6A

0.54 A

1.9

Double

MSV11-CD

M7955-YD

16K X 16 read/write
MaS memory

1.1 A

0.54 A

2.3

Quad

0.34 A

2.0

Double

-I
:rJ

MSV11-D

MB044

4K116K/32K
MaS memory

1.7 A

MSV11-E

MB045

4K116/32K
MaS memory

2.0A

0.41 A

2.0

Double

MXV11-A

MB047

Multifunction module

1.2 A

0.1 A

2.0

Double

REV11-A

M9400-YA

120 Q terminator,
DMA refresh,
bootstrap ROM

1.6 A

2.2

Double

REV11-C

M9400-YC

DMA refresh,
bootstrap

1.6A

2.2

Double

I\)

Module Specifications (cant.)

* These ac load figures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.

-0QZ

Table 1
Option
Desig.

Module
No(s).

Description

Module Specifications (cant.)
Power Requirements

Bus Loads·

+5V
±5%

+12V
+3%

AC(Max)

Size

0.1 A

3.0

1.0

Quad

RLV12

M8061

Disk controller

5.0A

RXV11

M7946

RX01 interface

1.5 A

1.8

Double

RXV21

N8029

Double density
floppy interface

1.1 A

2.0

Double

120 Q terminator

0.5A

Seriall cartridge
cassette

0.75
Appr.

1.2 A max

Serial video module

1.2 A

0.15

TEV11

M9400-YB

TU58
I\)

,.1:0.

VK170

CAM7142

Double

-I
::lJ

0
0

Double

-0~
Z

* These ac load figures were measured using standard TDR (time domain reflectometry) techniques. The conversion factor is 9.35 pFlac

load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.

INTRODUCTION
CONFIGURATION
The LSI-11 bus permits a unified addressing structure in which control/status and data registers for peripheral devices are directly addressed as memory locations. All operations on these registers, such
as transferring informaton to or from them or manipulating data within
them, are performed by normal memory address instructions. The use
of memory address instructions on peripheral device registers greatly
increases the flexibility of input/output communications.
Addresses
All the options except memories have at least one control and status
register and may have several data registers. Each register is assigned
an address through which the option can communicate with the processor. The upper 4K of memory address space is reserved for the
processor and external input/output (I/O) registers. The user can select any address (Appendix A) in the range of 160000 through 177776
and assign it to the option interface module. The modules are
configured to the desired address by selecting dip switches, connecting or disconnecting wire-wrap pins, or installing or removing wired
jumpers on the module.

AAV11-A
AAV11-A 4-CHANNEL 12-BIT D/A CONVERTER
INTRODUCTION
The AAV11-A is a four-channel, digital-to-analog converter module
that includes control and interfacing circuits. It has four D/A converters, a dc-to-dc converter that provides power to the analog circuits,
and a precision voltage reference. Each channel has its own holding
register that can be addressed separately and provides 12 bits of resolution. These registers can be written and read, using either word or
byte format. In addition, bits 0, 1,2, and 3 of the fourth holding register are brought out to the 1/0 connector, so they can be used as a fourbit digital output register.
FEATURES
• Four 12-bit digital input channels, binary encoded for either unipolar mode or bipolar mode.
• Jumper-selected output ranges and modes:
Bipolar mode ± 2.56 V, ± 5.12 V, ± 10.24 V
Unipolar mode 0 to +5.12 V, 0 to + 10.24 V
• One part in 4,096 resolution
• 5 V / f,lS slew rate
• ± 5 mA drive capability per converter
SPECI FICATIONS
Identification

A6001

Size

Quad

Power

+5.0Vdc ±5% at 1.5A
+12.0Vdc ±3% atO.4A

Bus loads
ac
dc

1.9
1.0

Resolution

12 bits (1 part in 4,096)

Number of D/A converters

Digital input

12 bits (binary-encoded for unipolar mode; offset-binary-encoded for bipolar mode)

Digital storage

Read/write, word or byte operable, single-buffered

AAV11-A
Output voltage range
(jumper selected)

±2.S6 V, ±S.12 V, ±10.24 V bipolar, 0 V to +S.12 V, 0 V to +10.24
V unipolar

Gain accuracy

Adjustable (factory set for bipolar
±S.12V)

Gain temperature coefficient

10 PPM per ee, max.

Offset temperature coefficient

20 PPM of full scale range per ee,
max.

Linearity

± % LSB max, nonlinearity

Differential linearity

± % LSB, monotonic

Output impedance

1 ohm max.

Drive capability

±6 mA max. per converter

Slewing speed

S VI J,LS

Rise and settling time (to 0.1 % of
final value)

4 J,Ls {8 J,Ls wth SOOO pF load in

parallel with 1 kO

CONFIGURATION

This section describes how the user can configure the module to
function within the system by setting dip switches (Figure 2) to obtain
the desired device address. The voltage range for each 01 A converter
(OAC O-OAC 3) can be configured independently by installing or removing the designated jumpers (Figure 2) associated with a specific
O/A converter. This section also describes how to connect external
devices to the module. The standard factory addresses for the registers are listed in Table 1.

AAV11-A
Table 1

Standard Addresses

Mnemonic

Address

Holding 0
Holding 1
Holding 2
Holding 3

DACO
DAC 1
DAC2
DAC3

170440
170442
170444
170446

DACIi'J

DAC1

DAC3

DAC2

DO
DO
DODD
/ \
/ \ / \:;:>

R4G
(OFFFET)

DAC 0

R35 R3G
R48
(GAINHGAIN) (OFFSET)

R34
R47
(GAIN) (OFFSET)

DAC 1

0!!2., ~o!!!....o~
_ _

0----<>

DAC 2

I
~~

WI3

DAC 3

0----<> 0----<>

R37 (GAIN)

R49 (OFFSET)

WI4

WI7

WIG

MODE I LEVEL STRAPS

BIT3

BITI1

Ir-----=-'---;I
(ADDRESS)

n·4319

Figure 1

AAV11-A Connectors, Switches, and Jumpers
31

AAV11-A

Device Registers
The device registers can be configured to respond to any address
within the range 170000 to 177777. Each register address does not
have to be individually set. The DAC 0 register address is selectable,
and the last digit will be zero. The remaining registers will use addresses 17XXX2, 17XXX4, and 17XXX6 for DAC 1, DAC 2, and DAC 3
registers, respectively. The factory-configured device address is
170440 as shown in Figure 2. The word formats for the DAC registers
are described in Table 2. Note that all device registers are always a
sequence of four consecutive even locations. There is no vector used
for this module.

D/A Converter Range and Mode
The range and mode (bipolar or unipolar) voltages can be selected by
the user inserting or removing jumpers as shown in Figure 1. Four
jumpers are associated with each D/A converter. The module is factory-configured for -5.12 to +5.12 V bipolar operation. The jumper
configuations for the bipolar mode ranges are shown in Table 3; the
unipolar ranges are shown in Table 4.

BDAL
BIT
POSITION

LOGICAL 1 = ON
LOGICAL a = OFF

MR-0855

Figure 2

Address Selection

AAV11-A
Table 2

DAC Word Formats

Bit

DACO, DAC1, DAC2

DAC3

15-12
11
10
9
8
7
6

Not used
Binary 11
Binary 10
Binary 9
Binary 8
Binary 7
Binary 6
Binary 5
Binary 4
Binary 3
Binary 2
Binary 1
Binary 0

Not used
Binary 11
Binary 10
Binary 9
Binary 8
Binary 7
Binary 5
Binary 5
Binary 4
Binary 3/Control 3
Binary 2/Control 2
Binary 1/Control1
Binary O/Control 0

5
4
3
2
1
0

Table 3

DAC1
W3
W4
W5
W6
DAC2
W7
W8
W9
W10

Jumper Configurations for Bipolar Operation

±2.S6 V

±S.12V

±10.24 V

OUT

OUT
OUT

OUT

OUT
OUT

OUT

IN
IN

AAV11-A
Table 3

Jumper Configurations for Bipolar Operation (Cont)

±2.S6 V

±S.12 V

±10.24 V

OUT

OUT
OUT

OUT

OUT
OUT

IN
OUT

DAC3
W11
W12
W13
W14

IN
IN

DAC4
W15
W16
W17
W18

Table 4

IN
IN

Jumper Configurations for Unipolar Operation

o V-+S.12 V

OV-+10.24V

DAC1
W3
W4
W5
W6

OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT
OUT

OUT

OUT
OUT
OUT

DAC2
W7
W8
W9
W10

DAC3
W11
W12
W13
W14

IN
OUT
34

AAV11-A
Table 4

DAC4
W15
W16
W17
W18

Jumper Configurations for Unipolar Operation (Cont)

OV-+5.12V

oV-+10.24 V

OUT

OUT
OUT
OUT

OUT

J 1 Output Connections
Analog output devices such as oscilloscopes may be either grounded
or floating. If the oscilloscope is grounded, either through its power
plug or through contact between its chassis and a grounded cabinet,
the oscilloscope ground should not be connected to any of the
AAV11-A ground pins. Doing so may result in a ground loop which will
adversely affect oscilloscope control results as well as ADV11-A operation (if used). If the oscilloscope is floating, its ground should be
connected to the AAV11-A logic ground, J1 pins L, N, R, or T. Note
that the foregoing assumes that the LSI-11 powersupply ground is
connected to powerline (earth) ground. If continuity checks reveal no
such connection, attach a length of 12-gauge wire between the
powersupply ground and a convenient point associated with earth
ground.

AAV11-A
J1
A

DAC 1 HQ GND
OAC 2 HQ GNO
DAC 3 HQ GND
- ISV TEST
+ISV TEST
DAe 0 HQ GND

0---

BIT 3 OUT

-BIT 2 OUT

BIT lOUT
BIT 0 OUT
DAC 3 OU T
DAe 2 OU T
DAe 1 OU T
DAe OOU T

BOARD SIDE
\1- 4314

Figure 3 Connection to Oscilloscope with Differential Input

AAV11·C
AAV11·C ANALOG OUPUT BOARD
INTRODUCTION
signed to interface analog instrumentation to the LSI-11 bus. It has
four individually addressable digital-to-analog converters (DACs),
each with 12 bits of input data resolution. Each DAC can be written or
read in either word or byte format. Jumpers permit selection of the
analog output voltage range for each register and its operating mode,
either unipolar or bipolar. One of the registers, DAC D, also has four
digital output bits for creating control signals to an analog device,
such as a CRT.

FEATURES
• 4 D/A converter circuits, separately controlled
• 12-bit digital resolution
• Read/write, word or byte addressable registers
• Unipolar or bipolar output
• Output voltage range selection of ± 10 V or 0 to 10 V
• 4-bit digital output for CRT control signals intensity, blank, unblank, erase

SPECI FICATIONS
Identification

A6006

Size

Dual-height: 13.16 cm x 21.6 cm
(5.18 in x 8.5 in)

Power

+5.0 V ±5% at 2.5 A

Bus loads
AC

0.9
1.0

D/A Resolution

12-bit

Number of D/A converters

Digital input

12-bits (binary encoded for unipolar output; offset binary for bipolar mode)

AAV11·C
Digital storage

Four separate Readlwrite DAC
registers for word or byte storage

Analog Output Voltage

±10V @ 10mA;
V to 10 V @ 10 rnA

Gain accuracy

Adjustable to (-) full-scale value

Gain drift

± 30 PPM per °C, max.

Offset drift

± 15 PPM per °C, max.

Offset error

Adjustable to zero

Linearity (0-10 V)

± % LSB; ± 1.2 mV at full-scale
range

Differential linearity

±%LSB

Output impedance

0.5 ohm

Output current

10mA @ 10V min.

Settling time

6/Ls to 0.1 % for a 20 V p-p output
change

I/O connector

20 pins; 3M no. 3421-7020

CONFIGURATION
The physical layout of the AAV11-C is shown in Figure 1. The AAV11C has switches and two jumpers to set up the device address. The
board also has jumpers to select the output voltage range for unipolar
and bipolar operation. The following paragraph describes in detail the
procedure for setting up the circuit board.
Device Select Addressing
The AAV11-C device address is the 1/0 address assigned to the first
of four DAC registers. The user selects the device address via a
switch pack for address bits DAL 3-10 and two jumpers for bits DAL
11 and DAL 12. The device address can range from 160000s to 177770a
in increments of 10a. The device address is usually set at 170440a. This
is shown in Figure 2. A switch in the ON position represents a 0; a
switch in the OFF position represents a 1. Jumper A 11 is installed to
place a 0 at address bit DAL 11. Jumper A 12 is removed to place a 1 at
address bit DAL 12.

AAV11·C
FS RANGE ADJ A

~
~

ZERO OFFSET ADJ A
FS RANGE ADJ B
ZERO OFFSET ADJ B
FS RANGE ADJ C
ZERO OFFSET ADJ C
ZERO OFFSET ADJ D
FS RANGE ADJ D

I
-

....-.

.--e

DACD

........

.--e

.........

DACC

DAC B

OFF

DACA

ADDRE:;D \~
\'
~

SELECT
SWITCHES

c:=-

DC-DC CONVERTER
JUMPERS

0 A12
_A11

Figure

AAV11-C Physical Layout

D/A RANGE
JUMPER
LOCATIONS

AAV11·C
15

BDAL
BIT

I...--L---'--L....,-....L.....r---l....~-,-...L....,-......L..........."'T'""......,..-'--r-I-"'T'""L...-....L---'----' POS IT ION
STANDARD ADDRESS
CONFIGURATION
(170440)

A12 All
OUT IN

ADDRESS SWITCH (S1)
LOGICAL 1 = OFF
LOGICAL 0 = ON

LOGICAL 1 = OUT
LOGICAL 0 = IN

Figure

Selecting AAV11-C Device Address

Output Voltage Range Selection
Each DAC on the AAV11-C has separate voltage range jumpers. These
jumpers are found above their corresponding D/A converter IC on the
printed circuit board (See Figure 1). When sent from the factory, the
AA V11-C has a voltage range selected for all four DACs of bipolar ± 10
V. Table 1 shows the jumpers to install to select the output voltage
range. The output of the board can be configured for either straight
binary notation for unipolar operation or offset binary notation for bipolar operation. The expected output values are shown in Table 1.

Table 1

AAV11·C Output Voltage Range Jumpers

Polarity

Output Voltage Install
Input Code Output
Range
Jumpers Notation (Octal)
Value

Unipolar

o to + 10 V

A to C

Bipolar

±10V

A to B:

Binary

Offset
binary

00000o

+ full scale

007777

00000o

+ full scale

004000
007777

0V
- full scale

AAV11·C
17XXXO

17XXX2

DATA

I
11

17XXUI

17XXX61

DAC A

DATA

DAC B

DATA

I
I I I
1

DAC C

DAC D

'----.,--/

TTL SIGNALS TO THE I/O CONNECTOR

Figure

I
I

AAV11-C DACs

PROGRAMMING

The AAV11-C has four addressable read/write registers. Each register
is used by one of four digital-to-analog converters and can be addressed as one word or two bytes, allowing complete use of the LSI11 instruction set. The AAV11-C device address is the base address of
the first register, usually 170440s. The other registers are addressed in
increments of 2s above the base address.
Interfacing to the AAV11·C

Figure 1 shows the location of the connectors on the AAV11-C. DAC
inputs and control signal inputs enter the board via the LSI-11 bus
connectors. Analog output voltages and digital control signals leave
the board via the top edge connector J1. Table 2 shows the signal
names on this connector. Each DAC has one output and a corresponding analog ground pin. The four least significant bits of DAC D
(DOO, D01, D02, and D03) are used for control signals to an analog device. These four bits are TIL-compatible.
41

AAV11·C
Figure 4 shows how the AAV11-C is connected to a device that uses
differential analog inputs and one control input. Both the AAV11-C
and the analog device must be set up for electrical compatibility. The
device manual should define which pins to attach to the AAV11-C
control bits. The software enables or disables the control bits.
Table 2

AAV11·C Connector J1 Pin Assignments

Signal

DOOH

DGND

001 H

DGND

oo2H

DGND

oo3H

DGND

AGND

DAC DOUT

AGND

DAC C OUT

AGND

DAC BOUT

AGND

DAC A OUT

AGND

AAV11-C

ANALOG INSTRUMENT
DAC A OUT (PIN 19)

XIN
X RETURN

Xo
DIFFERENTIAL
INPUTS

DAC B (PIN 17)

20-PIN
CONNECTOR

ANALOG GROUND (PIN 18)

,,><'

Y RETURN

--=z....:cl N-+-INTENSITY CONTRO L

Hf-=D.:...:.AC::...::....D.::..:DO::.::O..:...:H...!.:.(P...:..:.IN.:-1:..:....)_ _ _ _ _ _ _
DGND (PIN 2)

Figure

Z RETURN

Connecting AAV11-C to a Differential Input Device
42

rDACA -

-- -

'15

RANGE

GAIN "16

~1~WET I

'1-00

RDAL 11-00

OACA

-AJ?
:'B~~

RANGE
SELECT
JUMPERS

I
I
I
I
I

SEE
NOTE

CONTROL

RDAl02-oo

DIN H

L _____ _

SA 2 L

LOGIC

I
I
I
...J

SA 1 L

INWO l

'----~_tENB

f--<==-......---------+--.j ~~~~~Ol

II r - - - - - ,

LDOAC

LOGIC

BSYNC L. BOOUT l. BOIN L, tiWTBT L. BINIT L

LD OAe C L

DAC BAND C

LD DAf..!LL

L........:n---'

lSAME AS OAC AI

OAe A
OUT

_____ ..JL ____ ...l
L ________________ J

r ;,:;-C -;;- I
READ DAe 0

NOlI

RANGE Sf LlCT
RANGl
JUMPERS IN
0i"'6V
-A- C - 'IQV

B.O

- . 1BRAN:; . - GAIN

OAe 0

+150FFSET
A12

I
I

HOLDING
REGISTER

READ DAG I) l

I
L _____________ JI
BITS 3-0

Figure

5 AAV11-C Block Diagram

.....
.....
•

AAV11-C
DESCRIPTION

Illustrated in Figure 5 is the block diagram of the AAV11-C. It is addressable from the LSI-11 bus at its interface transceivers. An address switch pack determines the device address of the board. Setting the address switch pack is described in the Configuration
section of the discussion on this interface.
Binary data is written to these registers to be converted to an analog
voltage. BDALOO0-11 becomes RDAL00-11 within the AAV11-C. This
is the input to the holding register of the DAC selected. LD DAC A, B,
C, or D clocks the data into the DAC register.
DAC A, B, AND C

Digital-to-analog conversions are performed in each of three DACs by
identical circuits. A fourth DAC is slightly different. The first three
DACs have a holding register to store the digital input, a DAC IC that
generates a current to the input of the amplifier (the current is a function of the value in the holding register and the range select jumpers),
and an amplifier that changes its input current into a voltage proportional to its input. The fourth DAC performs a function similar to the
other three DACs, but can also supply TIL-compatible Signals for output to external logic.
Each DAC has an offset potentiometer to adjust the ampl ifier to negative full-scale range and a range gain potentiometer to adjust for positive and negative full-scale range.
DACD

The DAC D is identical to the DAC A, 8, and C except that bits 0-3 from
its holding register go to the I/O connector and to the DAC IC. These
bits can be used for external equipment that needs control Signals at
programmable times.
Control signals in these bits will affect any D/A conversions that occur
at the same time using DAC D.

ADV11-A
ADV11-A ANALOG TO DIGITAL CONVERTER
INTRODUCTION
The ADV11-A is a 12-bit successive approximation anaiog-to-digitai
converter that samples analog data at specified rates and stores the
digital equivalent value for processing. A multiplexer section can accommodate up to 16 single-ended or 8 quasi-differential inputs. The
converter section uses a patented auto-zeroing design that measures
the sample data with respect to its own circuitry offset and therefore
cancels out its own offset error.

AID conversions are initiated by program command, clock overflow,
or external events. The program control is determined by the control
and status register (CSR). The clock overflow command is supplied by
the KWV11-A option. External event inputs can originate at the user's
equipment or from the Schmitt trigger output on the KWV11-A ciock.
The digital data output is routed through a buffer register to the bus,
from which it can be transferred into memory. This buffer optimizes
the throughput rate of the converter.
Three reference signals are provided for selftesting on any channel
input: two dc levels and one bipolar triangular waveform. This output
can be used with DIGITAL diagnostic software to produCe a database
for extremely thorough and precise analog linearity testing.
FEATURES
• 16-channel multiplexer
• Sample-and-hold functions
• Autozeroing technique

• Buffered data output
• Selftesting features
SPECIFICATIONS

Identification

A012

Type

Quad

Power

+5 Vdc ±5% at 2.0 A
+12 Vdc ±3% at 450 mA

Bus Loads
ac
dc

3.25
1

ADV11-A
Inputs
Analog input protection

Fusible resistor guaranteed to
open at ±85 V within 6.25 seconds. Guaranteed not to open
from -25 V to +20 Vat the input.
Overload affects no components
other than the fusible resistor on
the overloaded channel; no other
channels are affected.

Logic input protection·

Fusible resistor guaranteed to
open at ±25 V within 6.25 seconds. Guaranteed not to open
from -4 V to +9 V at the input.

Analog input full scale range
(FSR)

10.24 V bipolar (-5.12 V to
+5.12V)

Analog input dynamic resistance
( Vin :5 5.12 V)

100 MQ minimum

Analog input bias current
( Vin :5 5.12 V)

50 nA, maximum

Logic input voltages

Low = 0.0 to +0.7 V
High = +2 V to +5 V

Logic input currents

Low = -6.8 rnA at 0 V
High = +1.3 rnA at +5 V

Logic input rise/fall time

400 ns maximum

Coding
A/D Converter
Resolution

12 bits, binary-weighted (2.5 mV
nominal)

Format

Parallel offset bina'ry, rightjustified
Input Voltage
+FS-1 LSB

o
-FS
Output Code
7777
4000

ADV11-A
(FS = 5.12 V;
1 LSB = 2.5 mV)
Vernier DIA
Reso!ution

8 bits, binary weighted

Format

Offset binary encoded
Input Code
377

200

Approximate
Offset Voltage
+2.5 AID LSB (+6.4 mV)

o
-2.5 AID LSB (-6.4 mV)

Performance
Gain error

Adjustable to zero

Offset error

Adjustable to zero

Differential linearity

No skipped states; no states wider than 2 LSB. 99% of state
widths ± 1h LSB

Integral linearity

± 1 LSB, maximum non-linearity
(referenced to end pOints)

Tem peratu re coefficients

Gain = 6 PPM per °C
Linearity = 2 PPM of full-scale
range per °C
Offset = 7.5 PPM of full-scale
range per °C

Noise

Module = 0.4 LSB rms; 2 LSB
peak
System = 0.5 LSB rms; 2 LSB
peak

Warm-up time

5 minutes, maximum

Timing
External start

Low level pulse, 50 ns minimum
to 10 /-Ls maximum; conversion
starts on leading edge
47

ADV11-A
Synchronization

Oto T

Conversion time

16 T (T = Clock period = 2 JLs)

Transition interval
(reacquisition interval between
end of conversion or channel
change and start of new conversion)
Test Signals
The ADV11-A provides three output voltages for test purposes:
1. Positive dc level, +4.4 V (±15%)
2. Negative dc level, -4.4 V (±15%)
3. Triangular wave, 15 Hz nominal (±15%)

CONFIGURATION
This section describes how the user can configure the module to
function within the system by setting dip switches S1 and S2 (Figure
1) to obtain the desired device address and interrupt vector as described in Table 1. When a jumper wire is inserted between the lugs,
the single-ended inputs (16 channels) are selected. When the wire is
removed, quasidifferential inputs are selected.

ADV11-A
SINGLE-ENDED
JUMPER LUGS

_________n

I~~

ADDRESS
SWITCHES
BI T 2 - - r - l
I l - - BIT 3

~IUU

OFFSET.J
ADJ

l...~
~

ill

" - GAiN
ADJ

S1
I

Q[}TAB C
(CLOCK
S C
OVERFLOW

LJ.- BITS TAB 5

VECTOR
SWITCHES

101)

(EXTER~)AL

START)

BlT 11

11- 4322

Figure 1

ADV11-A Connectors and Switches

Table 1

Description

Standard Assignments

Mnemonic

First
Module
Address

Second
Module
Address

CSR
DBR

170400
170402

170420
170422

400
404

410
414

Registers
Control and Status
Data Buffer

Interrupt Vectors
Conversion Complete
Error

ADV11-A
Registers
The control and status register (GSR) address can be selected in the
range of 170000 to 177774 by using the S2 dip switch as shown in
Figure 2. Switch S2 is factory-set at 170400, which is the recommended address as illustrated in Figure 2. The functions of the GSR bits are
shown in Figure 3 and detailed in Table 2.

CSR ADDRESS FORMAT
15

111111111010101110101010101010101

I I I I I I I I I I

STANDARD ADDRESS
CONFIGURATION
OFF OFF OFF ON OFF OFF OFF OFF OFF OFF

* * * ~ ! ~ ~ ! ! !1

( 1704001
CSR ADDRESS 1 10
SWITCH (S21

Figure 2

GSR Switch-Selectable Address

NOT USED

ERR

OS!:t4

DONE
INT ENA

MUX ADDRESS
READ/WRITE

ERR
IIliT EIliA

AD
DONE

EX
START
ENA

elK
START
ENA

AD
START

NOT USED

ENA
11-4.311

Figure 3

GSR Bit Format

ADV11-A
Table 2

DBR Bit Functions

Bit

Function

Read-Only
15-13

Not used. Should read as O.

ID-When 10 Enable (bit 3) of the CSR has been set,
DBR bit 12 will be set to 1 at the end of the conversion.

11-0

Converted Data-These bits contain the results of
the last AID conversion.

Write-Only
15-8

Not used.
Vernier 01 A-These bits provide a programmed offset to the converted value (scaled 1 01 A LSB = 1/50
AID LSB). The hardware initializes this value to 200 8
(midrange). Values greater than 200 8 make this input voltage appear more positive.

7-0

Vector Interrupt
The AID conversion complete interrupt vector is set by dip switch S1
(Figure 1). Any address in the range of 000 8 to 7778 can be selected by
the user. The switch is factory-configured for 400 8 , the recommended
vector, as shown in Figure 4. The error interrupt vector will be four
words higher than the AID conversion complete interrupt vector.

I0 I0 1 0 1 0 1 0 I0 1 0 I
I I I I I I

1
101010101010 1 0 1
1 0
STANDARD VECTOR

or or or or or or

CONFIGY4~~~I~:CTOR
S~~\~H I 8

I
:v1R

Figure 4

Interrupt Vector
51

08,,3

ADV11-A
Connections
Figure 5 illustrates the location of user connectors and switches on the
component side of the ADV11-A board.
Analog input signals are input to the ADV11-A through the 40-pin
connector. Pin assignments for the connector are shown in Figure 5.
The proper H856-to-H856 cable is the SC08R; The proper H856 to
prepared open-ended cable is the SC04Z.

LOGIC GND

51 NGLE END ED L

ANALOG GND

+4 .5V

ANALOG GND

- 15V TEST
+15VTEST

i AA

i CC

EXT START L

RAM P
-4. 5V
CH 1

-CH 07

CH X7

CH 16

-CH 06

CH X6

CH 15

-CH 05

CH X5

CH 14

-CH 04

CH X4

CH 07

+CH 07

CH 07

CH 06

+CH 06

CH 06

CH 05

+CH 05

CH 05

CH 04

+CH 04

CH 04

CH 1

-CH 03

CH X3

CH 1

- CH 02

CH X2

CH 1

- CH 01

CH XI

CH 1o

- CH 00

CH XO

CH 03

+CH 03

CH 03

CH 02

+CH 02

CH 02

CH 01

+CH 01

CH 01

CH 00

+CH 00

CH 00

SINGLE
ENDED

D I FFERENTI AL

H322
NOMENCLATURE

BOARD SIDE
n- oil I "0

Figure 5

ADV11-A 40-Pin Connector Pin Assignments

ADV11-C
ADV11·C ANALOG· TO· DIGITAL CONVERTER
INTRODUCTION
The ADV11·C is an LSI-11 analog input printed circuit board that performs analog-to-digital conversions. A dual-height module, it can accept up to 16 single-ended inputs, or up to eight differential inputs, either unipolar or bipolar. A unipolar input can range from 0 Vdc to 10
Vdc. A bipolar input can range from -10 Vdc to 10 Vdc. The ADV11-C
also has a programmable gain on these inputs of 1,2,4, or 8 times the
input voltage.
Analog-to-digital (AID) conversions are started by a program command, an external trigger, or a realtime clock input. When the program
command sets the AID START bit in the control/status register, the
ADV11-C will start the AID conversion on the selected input channel.
The ADV11-C changes the analog input into digital data. The digital
data goes to the AID data buffer register and waits for a programmed
data transfer to the LSI-11 processor or memory, or the ADV11-C puts
an interrupt request on the LSI-11 bus and waits for the interrupt request to be acknowledged.

FEATURES
• 16 single-ended analog input channels
• Eight differential analog input channels
• Software Programmable gain Amplifier with gains of 1,2,4, or 8
• 12-bit output data resolution
• Output data notation in binary, offset binary, or two's complement
format
• AID results can be received by a programmed 1/0 transfer or by
serviCing an interrupt request
• Interrupts can be enabled and automatically set by AID DONE and!
or ERROR flags
SPECI FICATIONS
Identification

A8oo0

Size

Dual-height: 13.16 cm x 21.6 cm
(S.18 in x 8.S in)

Power

+S.O V ±S% at 2.0 A

ADV11·C
Bus loads
AC
DC

1.3
1.0

110 Connector

26 pins 3M no. 3399-7026

Inputs
Number of analog inputs

Analog input range

Eight channels using differential
inputs, or 16 channels using single-ended inputs

oV to + 10 V
-10Vto +10V
± 10.5 V (signal + common

Maximum input signal

mode voltage)

Input impedance
Off channels

100 M ohm minimum in parallel
with 10 pF maximum

On channels

100 M ohm minimum in parallel
with 100 pF maximum

Power off

1 K ohm in series with a diode

Input protection

Inputs are current-limited and
protected to ± 30 V overvoltage
without damage

I nput bias current

20 nA at 25 0 C (76 0 F), maximum

AID Output
Data Buffer Register

16-bit read-only output register

Resolution

12-bit unipolar; 11-bit brpolar,
plus sign

Data Notation

Binary, offset binary, or 2's complement

Sample and Hold Amplifier
Aperture uncertainty

Less than 10 ns

Aperture delay

Less than 0.5Jls from start of
conversion to signal disconnect.
54

ADV11·C
Front end settling

Less thaFl 15ILs to ± 0.01 % of fu 11scale value for a 20 V pop input.

Input noise

Less than 0.2 mV rms

AID Converter Performance
Linearity

±1/2 LSB

Stability (temperature coefficient)

±30 ppm/°C

Stability, long-term

± 0.05% change per six months

System accuracy

Input voltage to digitized value±O.03%

Conversion time

25ILs from end of front end starting to setting the AID DONE bit

System throughput

25K channel samples per second

Environment
Temperature, operating

5°C to 60°C (41°F to 140°F)

Temperature, not operating

- 40°C to 66°C ( - 4Q°F to
150°F)

Relative humidity, operating

10% to 95% with max. wet bulb
of 32°C (90°F) and min. dew
point of 2°C (35°F)not condensing

DESCRIPTION
Figure 1 shows a block diagram of the ADV11-C. It is addressed via the
LSI-11 bus at its interface transceivers. The board has jumpers to select its device address. The ADV11-C has two programmable addressable registers: the Control/Status Register (CSR), which is a readl
write, byte-addressable register, and the Data Buffer Register (DBR), a
read-only, word-addressable register. The board also has jumpers to
select the base interrupt vector. The ADV11-C has two interrupt vectors. One is enabled when AID DONE is set in the CSR; the other may
be enabled for an ERROR set in the CSA. The ERROR vector automatically receives the base interrupt vector address + 4. See the address
and vector jumpers.
Once addressed, the transceivers send the bus data instruction to the
CSA. The instruction selects one of 16 channels, determines the gain

ADV11-C
selected (GSO, GS1), and determines how the board will start an analog conversion. An analog conversion can be started by a realtime
clock input, by an external event trigger, or under program control by
setting the AID START bit in the CSA.

i2t &

SAMPLE AND

SG OUT

16-CH
MUX

.--

~
GAIN
PI
~ SELECT

CH 0-16

(8CH
DIFFER
ENTIAl)

SEI~

~ P5

RTC IN l

RT~

f'.,.

fp2

""p

~~P

~SI

RTC ENA H

EXT ENA H

:::::::::

CONTROL
lOGIC
(CSR)
AND
CLOCK
SELECT

011:08
L-

lD CSR H
RD CSR l

~VN2..!:-

K
A

"
BDAl 15 00 )
-....
V
DEVIC:
~
ADDRESS IJUMPERS ~
A3--A12
I-

BUS
TRANSCEIVERS

(DBR)
ClK

------

GSO

",n

CONVERTER

MUX
ADDR
REGISTERI

.~1~rC>"

AID

~::

AMP l
Jl

PROG

r---

01500

~
RD BUF H

~ INTERRUPT
VECTOR
JUMPERS

v3-va

VECTOR'
~

""5 v

DC DC
CONVERTER

A GND
-15 V

A
A.D DATA DO-DI5

Figure

1 ADV11-C Block Diagram

One jumper (SEIDl) to the multiplexer determines whether the module
uses single-ended or differential inputs. Two jumpers (F2, F1) determine whether the external trigger comes from the 110 connector (J1) or
from the LSI-11 bus 50/60 Hz line input (BEVNT L).

ADV11·C
The output of the multiplexer goes to a differential amplifier then to a
programmable gain amplifier. Its gain is set by writing bits 2 and 3 in
the CSA. The gain selected (GSO and GS1) may be 1, 2,4, or8 times the
input voltage.
The output of the programmable gain amplifier goes to a sample and
hold amplifier, where the analog signal is continuously sampled until
one of the following inputs is received.

• AID START bit set in the eSR
• Realtime clock input at 1/0 connector or at pin RTe IN
• External event trigger input at 1/0 connector or at LSI-11 bus
BEVNTline.
When one of these inputs has been received, the sample and hold amplifier switches to "hold," and the 12-bit AID converter digitizes the
held analog voltage.
When the AID conversion is complete, the AID DONE bit is set in the
GSR, and the sample and hold amplifi-er returns to sampling. If the
DONE INT ENABLE bit is also set, an interrupt occurs to the LSI-11
bus. When the interrupt is acknowledged, the data is read by reading
the data buffer register (DBR).

PROGRAMMING THE ADV11-C REGISTERS
This section describes the mode of operation determined by setting
bits in the GSR and defines the bits in both registers.
Selecting ADV11·C Mode of Operation
The user determines the mode of operation of the ADV11-C, and selects how the AID conversions are to start and how the digital data is
transferred to the LSI·11 processor.
Starting an AID Conversion - An AID conversion can be started in
one of three ways.
1. Realtime clock input: Set bit 5 in eSR
2. External trigger enable: Set bit 4 in eSR
3. AID START bit: Set bit 0 in eSR
Transferring Data to LSI·11 - The digital data can be transferred to
the LSI-11 processor or memory by a programmed 1/0 transfer or by
servicing an interrupt request.
57

ADV11·C
Using LSI-11 instructions, a programmed I/O transfer can write the
GSR in the ADV11-C, read the GSR, and wait-for an AID DONE bit (bit
7), then read the DBR to get the AID data.
If interrupts are used, set interrupt enable bit (bit 6) of the GSA. When
the AID conversion is complete, the AID DONE bit (bit 7) sets, and an
interrupt occurs to the LSI-11 processor. The processor services the
interrupt request and gets the AID data. After receiving the data, the
software clears the AID DONE bit in the ADV11-C's CSA.
An interrupt may also be programmed to occur on an error condition
by setting bit 14 in the CSA.
ADV11·C Standard Device Address
The ADV11-C permits assigning a device address between 160000a and
1nnOs. The standard device address is 170400s. This is the address
for the control/status register. The data buffer register automatically
receives the base address + 2, or 1704021. Table 1 shows the standard
address and interrupt vector address aSSignments.
AD\.'11·C Standard Interrupt Vector Address
The interrupt vector can be aSSigned between 0 and 770s in increments
of 1Os. The standard base interrupt vector for the ADV11·C is 400s. This
vector is aSSigned to the AID DONE interrupt request. If the DONE INT
ENABLE bit (bit 6) is set in the CSR, the AID DONE bit (bit 7) enables
the interrupt request to the LSI-11 bus. When the interrupt request is
acknowledged by the LSI-11 processor, the interrupt service routi ne is
started at address 400a.
The ADV11-C can also interrupt on an error. The error interrupt request
is automatically assigned the base vector address + 4, or 404. If the
ERROR INT ENABLE bit (bit 14) is set by the program, an interrupt request will occur at the occurrence of any error (bit 15 set).
The standard interrupt vector addresses are shown in Table 1.

ADV11·C
Table 1

Mnemonic

First
Module
Address

Second
Module
Address

CSR

170400

170420

DBR

170402

170422

400
404

410
414

.~.

~scnp

..;on

Registers
Control
/Status
Data Buffer

Standard Octal Address Assignments

Interrupt Vectors
AID DONE
ERROR

Control/Status Register (CSR)
The control/status register is a read/write register, shown in Figure 2.
A control instruction is written into the GSR; the AID status is read
from the GSA. The bit definitions are described in Table 2.
Data Buffer Register (DBR)
The data buffer register is a read-only register that holds the digital
data after the AID conversion is complete. The DBR can be read after
the AID DONE flag is set in the CSR register. The format for the DBR is
shown in Figure 3. The bit definitions are described in Table 3. The AID
DONE flag is cleared after reading the register or on initializing the
LSI-11 bus.
CONFIGURATION
The ADV11-G, shown in Figure 4, has jumpers to set up the device address, the interrupt vector address, and the analog configuration. The
user may select the AID input range, polarity, and the output data notation.
AID CONTROL/STATUS REGISTER (READIWRITE)

170400
(BASE ADDRESS)

~~~7.===T~==~~~Jt~7T1I
MULTIPLEXER
ADDRESS

ERROR

ERROR
INT ENA

Figure

AID
DONE

RTC
ENABLE

DONE
INT ENA

GAIN
SELECT

EXT
TRIGGER
ENABLE

AID
START

NOT USED

ADV11-C Control/Status Register (ReadlWrite)
59

ADV11·C
Table 2

ADV11·C Control/Status Register Bit Assignments

Bit

Name

Description

AID START

Write Only - When set, this bit
starts an AID conversion. This
bit is cleared by internal logic
after starting conversion. It always reads back O.

Not used

2,3

GAIN SELECT

ReadlWrite - Set these bits to
select the gain for the analog
input as follows.
Gain

GS1
(bit 3)

GSO
(bit 2)

1
2
4
8

0
0

1
1

EXT TRIG
ENABLE

ReadlWrite - When set, this bit
allows an external trigger to
start an AID conversion.

RTC ENABLE

Read/Write - When set, this bit
allows a realtime clock input to
start an AID conversion.

DONE
INTERRUPT
ENABLE

ReadlWrite - When set, this bit
enables an interrupt on AID
DONE (bit 7). Both bits are
cleared by INIT.

AID DONE

Read Only - This bit is set at
the end of an AID conversion
and is reset by reading the AID
data buffer register.

8-11

MULTIPLEXER
ADDRESS

ReadlWrite - These bits select
one of 16 analog input channels.

ADV11·C
Bit

Name

12-13

Not used

ERROR

ReadlWrite - When set, this bit
enables an interrupt on an ERROR (bit 15). Both bits are
cleared by INIT.

ERROR
iNTERRUPT
ENABLE

Read/Write - When set, this bit
indicates that an error has occurred due to one of the following.

Description

• Trying an external start or
clock start during multiplexer
settling time .
• Trying a start while an AID
conversion is in process.
• Trying any start while the AID
DONE bit is set.
This bit can be cleared by writing the eSR or by an INIT.

AID DATA BUFFER REGISTER (READ ONLY)

~~~:2ADDRESS +2d
,

SI~N

I I I
J'MSB

AID

~ATA

I I
LS~

(USED FOR 2'5
COMPLEMENT
NOTATION ONL Yl

Figure

ADV11-C Data Buffer Register (Read Only)

There are two types of jumpers on the ADV11-C board. Some are pointto-point jumpers, in which each jumper pin has a unique number. A
jumper is installed from one numbered pin to another. The other jumpers are pairs of pins. With each jumper type, a jumper wire is installed
across a pair of pins.
This paragraph provides details on setting up the circuit board.

ADV11·C
Table 3 ADV11·C Data Buffer Register Bit Assignments
Bit

Name

Description

0-11

AID DATA

These bits hold the parallel
digital output after completion
of the AID conversion in one of
the following data notations.
• binary
• offset bi nary
• 2's complement
The user selects the data notation.

12·15

SIGN

These bits are the sign for the
bipolar inputs when using 2's
complement notation. These
bits are not used for binary or
offset binary notation.

FULL SCALE

PG ZERO

DC-DC CONVERTER

ZERO

AID CONVERTER MODULE

NOTE
THE JUMPERS SHOWN ARE THE
FACTORY·SHIPPED CONFIGURATION.
JUMPER

GROUPS
A ANDV

JUMPER

Figure

JUMPER

GROUPP

JUMPER
GROUP 0
INOT USED I

ADV11~C PhYSical Layout

GROUPF

ADV11·C
Selecting ADV11·C Device Address
The ADV11-C device address is the 1/0 address assigned to the AID
control/status register. The device address is selected by means of
jumpers A3 through A 12. (See jumper groups A and V in Figure 4). The
jumpers allow the user to set the device address within the range of
160000a to 177770a in increments of 10a. The device address is usually
set at 170400s, as shown in Figure 5. A jumper installed decodes a 1 in
the corresponding bit position; a jumper out decodes a O.

Al2 All AIO A9
A8 A7 A6 A5 A4 A3
IN
OUT OUT OUT IN OUT OUT OUT OUT OUT

LOGICAL 1 = IN
LOGICAL 0 = OUT

Figure

Selecting ADV11-C Device Address

Selecting ADV11·C Interrupt Vector Address
The ADV11-C is capable of generating two interrupt vectors to the LSI11 processor. These interrupts, if enabled, occur when the AID DONE
bit or the ERROR bit is set in the CSA. The base interrupt vector address is assigned to AID DONE. (The ERROR interrupt automatically is
assigned the base interrupt vector address + 4.)
The base interrupt vector address can be set within the range of 0 to
770a, in increments of 10a. It is usually set to 400a by jumpers V3
through VB, as shown in Figure 6. (See jumper groups A and V in Figure 4).
15

V8
IN

Figure

y r

V7
V6 V5 V4 V3
OUT OUT OUT OUT OUT

Selecting ADV11-C Interrupt Vector Address

ADV11·C
Selecting ADV11·C Analog Input Range, Type, and Polarity
The ADV11-C allows software control over the full-scale range selection. The effective ranges provided by the programmable gain are as
follows:
Gain

Unipolar

Bipolar

o V to + 10 V
oV to +5 V
oV to +2.5 V
oV to 1.25 V

±10V

2
4
8

±5V
±2.5V
± 1.25 V

Table 4 shows the jumpers that must be installed to set up the analog
input type. The board comes from the factory set for 16-channel single-ended, bipolar inputs. Refer to jumper group P in Figure 4.

Table 4

Selecting ADV11·C Analog Input Type

Input Type

Install Jumpers

Single-Ended Inputs·

P1 to P2; P8 to P9

Differential Inputs

P2 to P3; P4 to P5

* Factory configuration

NOTE
Jumpers P6 and P7 are factory installed for the pro·
grammable gain feature and should be left in.

Selecting ADV11·C AID Output Data Notation
The ADV11-C allows the user to select the data notation to be used for
the AID output, as either binary, offset binary, or 2's complement notation. Table 5 shows the jumpers that must be installed to select the
data notation. Refer to jumper groups D and E near the handle of the
board, shown in Figure 4.
64

ADV11·C
Table 5

Selecting AID Output Data Notation
Jumpers

AID Output
Data Notation

,'-'

"T'-'

hf"\
"'..,

an
v..,

"' .....

ht:

at:
v .....

Input Voltage

Output Code
(Octal)

Binary

OUT

+ full scale
OV

007777
000000

Offset binary*

OUT

+ full scale
OV

2's
Complement

OUT

- full scale
+ full scale

007777
004000
000000
003777

00000o

- full scale

174000

• Factory configuration

Selecting Source of External Trigger
The AID conversions within the ADV11-C can be started in one of the
following three ways:
1. Under program control, using the AID START bit in the CSR.
2. Bya realtime clock input at J1 pin 21 or at pin RTC IN.
3. By an external trigger, either at J1 pin 19 or at the BEVNT line on
the LSI-11 bus.
The user can select the source of the external trigger using two jumpers on the board. (See jumper group F in Figure 4.) Table 6 shows the
jumpers to install to select the source of the external trigger.
Table 6

Selecting ADV11·C External Trigger

External Trigger Source

Jumpers
F1

BEVNT line (LSI-11 bus)

OUT

EXT TRIG IN (J1 pin 19)

OUT

INTERFACING TO THE ADV11·C
Figure 4 shows the location of the 1/0 connector J1 on the ADV11-C.
Analog input signals enter the board through this connector. Up to 16
single-ended analog inputs can be connected to J1 (CH O-CH 15), or up
to 8 differential analog inputs can be connected to J1 using CH O-CH 7
65

ADV11·C
and RETURN 0-7. A realtime clock input and an external trigger can
also be connected to J1. Under program control, the clock or external
trigger can be enabled to start an AID conversion. The pin assignments for J1 are shown in Table 7.
The ADV11-C has two bus interface connectors that plug into the LSI11 bus. These connectors have signals defined by LSI-11 bus specifications.

Single·Ended Inputs (16 Channels)
Single-ended analog inputs have one side of the user's analog source
connected to the AID converter amplifier and the other side connected
to ground, as shown in Figure 7.
The benefit of single-ended inputs is that the user gets twice as many
channels as in a differential input system. The disadvantage is the
loss of the common mode rejection that is available with a differential
system. Therefore, the recommended analog inputs are as follows:
• Input level: High, more than 1 V
• Input cable lengths: Short, less than 4.5 m (15 ft)
The user's source may be positioned some distance from the computer, and a voltage difference may occur between the user's source
ground and the computer ground. This ground voltage difference (VN)
is included in the signal received by the AID converter. To decrease
this ground difference, plug the user's device into an ac receptacle as
close as possible to the one providing power to the computer.

Table 7

ADV111·C Connector J1 Pin Assignments

Signal Name

CH 0

CH 8 or RETURN 0

CH 1

CH 9 or RETURN 1

CH2

CH 10 or RETURN 2

CH 3

CH 11 or RETURN 3

CH4

CH 12 or RETURN 4

CH5

CH 13 or RETURN 5

CH6

CH 14 or RETURN 6

CH 7

CH 15 or RETURN 7

ADV11·C
Pin

Signal Name

AGND

AMPL

EXT TRIG IN L

DGND

RTCIN L

DGND

AID REF

r--- ..,I

,----,

GENERATING DEVICE

RECEIVING DEVICE

L _

L- _

,... .....

_.I

--------~~~--------,_/
VN
MR 5941

Figure

Single-Ended Analog Input

NOTE

Do not run a wire from the user's ground to the
ADV11·C analog ground, since this wire forms a path
for ground loop current that can affect the results on
all input channels.
Floating input lines can be created by connecting the common side of
the user's devices to the analog ground input on the ADV11-C (J1 pin
17). The ground point is shared among the channels. The signal return
path from the AID converter does not result in a current loopwith the
device ground.
Pseudo· Differential Inputs (16 Channels)
A pseudo-differential analog input system can be created by connecting all input sensors referenced to a common point, such as AMP L, as
67

ADV11·C
shown in Figure 8. This is possible because AMP L is an input at con·
nector J1 (pin 18) for user connection. The input amplifier rejects the
common mode noise. The recommended analog inputs are as follows:
• Input range: 100 mV to 10 V
• Input cable lengths: Less than 7.5 m (25 ft)

.-----,
ADV11-C

FLOATING SOURCE

I CHAN 0
I CHAN 1

SIGNAL 1' .....
RETURN ~.~

'''''

• CHAN 2

I CHAN 3
1.

I CHAN 15

SIGNAL

r .....

SIGNAL ;.:,

I
I
I

INSTRUMENT WITH
ISOLATION TRANSFORMER AND
FLOATING SECONDARY

111)It

SEE NOTE
PS

I--'

I
I

.... ./

P1 P3

.J; I P~ ; ; -

RETURN ...,..~

AMPL

BATTERY POWERED
SOURCE

....

AMPH

16-CHAN
INPUT
MUX

SIGNAL 1'"'\

RETURN IX,

.... ./

J1-1S

NOTE FOR SINGLE-ENDED INPUTS
(16 CHANNELS) CONNECT
P2 TO P1, AND PS TO P9

I AMP L

•
~ ANALOG GROUND

L- -

.. -

..J

COMPUTER
GROUND

FOR DIFFERENTIAL INPUTS·
(S CHANNELS) CONNECT
P2 TO P3, AND P4 TO P5

115 VAC

Figure

Pseudo-Differential Inputs

Differential Inputs (8 Channels)
Differential inputs have one side of the generating source connected
to the positive (+) input of the AID input amplifier and the other side of
the source connected to the negative (-) input of the amplifier, as
shown in Figure 9.

ADV11·C
GENERATING DEVICE

r- - - ..,

RECEIVING DEVICE
V,=VS+VN-V N

I--;V~

;---\.

r - - ' - . ....

r-- -

I
L-_

---,

I.
I Va

,----.

-------~~~--------'-/
7

Figure

Differentiallnputs

The benefit of differential inputs is that noise voltages appearing at
the same time on both sides of the source are rejected by the AID input amplifier. This is called common mode rejection, and provides a
system with low noise. The amount of noise rejection is a ratio, the
common mode rejection ratio (CMRR), given in decibels (dB). The
CMRR for the ADV11-C is 80 dB at full-scale range.
The disadvantage of differential inputs is that the number of available
input channels is lowered by half.
The recommended analog inputs are as follows:
• Input range: 10 mV to 10 V
• Input cable length: As needed by user
• Cable type: Twisted-pair, shielded lines with low impedance

AXV11-C

AXV11·C ANALOG INPUT/OUTPUT BOARD
INTRODUCTION
The AXV11·C is an LSI-11 analog input/output printed circuit board,
AOO26. The board accepts up to 16 single-ended inputs, or up to 8 differential inputs, either unipolar or bipolar. A unipolar input can range
from 0 V to + 10 V. A bipolar input can range from -10 V to + 10 V. The
AXV11-C has a programmable gai n on these inputs of 1, 2, 4, or 8 times
the input voltage.
AID conversions can be started by a program command, an external
trigger, or a realtime clock input. The AXV11-C changes the analog input into digital data at its output. The digital data waits for a programmed data transfer to the LSI-11 processor or memory, or the
AXV11-C puts an interrupt request on the LSI-11 bus and waits for the
request to be acknowledged.
The AXV11-C also has two separate digital-to-analog converters
(DACs). Each DAC has a write-only register that provides 12-bit input
data resolution. On receiving the data, the AXV11-C changes the data
to an analog output voltage.

FEATURES
• 16 single-ended analog input channels or 8 differential analog input channels; SEIDl jumper is field-selectable.
• Programmable gain of 1, 2, 4, or 8.
• 12-bit output data resolution.
• Output data notation in binary, offset binary, or 2's complement
format.
• AID conversions can be started by a program, an external trigger,
or a realtime clock.
• AID results can be received by a programmed I/O transfer or by
servicing an interrupt request.
• Common mode rejection ratio of 80 dB at maximum range.
• Two D/A converters (DACs).
• 12-bit digital input to each DAC.
• Each DAC has a unipolar or bipolar output.
• Output voltage range selection of ± 10 V or 0 V to 10 V.

AXV11-C
SPECIFICATIONS
Identification

A0026

Power Requirements

+5V(±5%)@ 2.0A

Bus Loads
1
1.3

DC bus loads
AC bus loads

110 Connector

26 pins; 3M no. 3399-7026

Analog Input
No. of analog inputs

8 channels using differential inputs, or 16 channels using single-ended inputs

Input range

OVto +10V;-10Vto +10V

Input gain (programmable)

Gain ( ± 0.05%) Range
1
2
4

10V
5V
2.5V
1.25 V

10.5 V (signal + common mode
voltage)

Maximum input signal
Input impedance
Off channels

100 M 0 in parallel with 10 pF
max
100 M 0 in parallel with 100 pF
max
1 k 0 in series with a diode

On channels
Power off
Input bias current

20 nA @ 25° C, max

Common mode rejection ratio

80 dB at 10 V full-scale range at
60 Hz

AID Output
Data buffer register

16-bit read-only output register

Resolution

12-bit unipolar; 11-bit bipolar
plus sign
71

AXV11-C
Binary, offset binary, or 2's complement

Data notation
Coding

Notation
Used

Output
Coding
Full·Scale
Code
Input Voltage (Octal)

Binary

+9.9976 V
0.0000 V

Offset
binary

+9.9951 V 007777
O.()()()()
004000
- 10.()()()() V 00000o

2's
+9.9951 V
complement 0.0000 V
-10.000V

007777
000000

003777
00000o
174000

Sample and Hold Amplifier
Aperture uncertainty

Less than 10 ns

Aperture delay

Less than 0.511S from start of
conversion to signal disconnect.

Front end settling

Less than 1511S to ± 0.01 % of
full-scale value
for a 20 V pop input

Input noise

Less than 0.2mV rms

AID Converter Performance
Linearity

±112 LSB

Stability (temperature coefficient)

±30 ppmJ°C

Stability, long-term

± 0.05% change per 6 months

Conversion time

2511S from end of front end starting to setting the AID DONE bit

System throughput

25K channel samples per second

System accuracy

Input voltage to digitized value±O.03%
72

AXV11-C
D/A Converter Specifications
No. of 01 A converters

Digitai input

12 bits (Binary code is used for
unipolar output; offset binary or
2's complement code is used for
biplar output)

Analog output

±10VorOVto +10V

Output current

±S rnA max

Output impedance

0.1 g

Differential linearity

± 1/2 LSB

Non-linearity

0.02% of full-scale value

Offset error

Adjustable to zero

Offset drift

± 30 ppm/°C max

Gain accuracy

Adjustable to full-scale value

Gain drift

± 30 ppm/oC max

Settling time

6SJLS to 0.1 % for a 20 V pap output change

Noise

0.1 % full-scale value

Capacitive load capability

O.SJLF

Environment
Temperature, operating

SOC to 60°C (41°F to 140°F)

Temperature, not operating

- 40°C to 66°C ( - 4Q°F to
150°F)

Relative humidity, operating

10% to 9S% with max. wet bulb
of 32°C (90°F) and min. dew
point of 2°C (3S°F)not condensing

DESCRIPTION
Figure 1 shows a block diagram of the AXV11-C. The board has jumpers to select its device address. It has four addressable registers: the
control/status register (CSR), the data buffer register (DBR), DAC A

AXV11-C
register, and DAG B register. The board also has jumpers to select the
base interrupt vector address. The AXV11-G has two interrupt vectors.
One is enabled when AID DONE is set in the GSR; the other may be
enabled for an ERROR set in the GSA.

AID Conversion
When the AXV11-G is addressed, the transceivers send the instruction
from the LSI-11 processor to the GSA. The instruction selects 1 of 16
channels, determines the gain selected, and determines how the
board will start the analog conversion. A jumper (SEIDl) to the input
multiplexer determines if singled-ended or differential inputs are to be
used.
An analog conversion can be started by a realtime clock, by an external trigger, or under program control by setting the AID START bit in
the GSA. GSR bit 5 enables the realtime clock input; GSR bit 4 enables
the external trigger input. Two jumpers (F2, F1) on the board determine
whether the external trigger comes from the I/O connector (J1) or from
the LSI-11 bus event line (BEVNT L).
The output of the multiplexer goes to a differential amplifier, then to a
programmable gain amplifier. The gain is set in the GSR with bits 2
and 3 (GSO and GS1). The gain may be selected as 1,2,4, or 8 times the
input voltage.
The output of the programmable gain amplifier goes to a sample and
hold amplifier. The amplifier continuously samples the analog signal
while waiting for the AID START bit in the GSR, for a realtime clock
input, or for an external trigger input. When one of these inputs has
been received, the sample and hold amplifier changes to "hold" and
the 12-bit AID converter digitizes the "held" analog voltage.
When the AID conversion is complete, the AID DONE bit is set in the
GSR and the sample and hold amplifier returns to sampling. If the
DONE INT ENABLE bit is also set, an interrupt occurs to the LSI-11
bus. The contents of the 12-bit AID converter is read by reading the AI
o data buffer register (DBR).

D/A Conversion
The DAG register input data is addressed on the LSI-11 bus as follows.
74

AXV11·C

RD BUF H

c;"'"
"*
SAMPLE AND

SG OUT

~
Pl
~

.,fP:

RT~IN

GAIN
SELECT

DIF
AMP

'---

MUX
ADDR
REGISTERI

EXT ENA H

ro~p
/

L
L

CONTROL
LOGIC
(CSR)
AND

CLOCK
SELECT

f--

011:08

DACAOUT

.---- LD CSR H

L-

RD CSR L

;::..

~VN~

,It If

DAC BOUT

I RTCENAH

~~~~

I .-----

K......

OFFSET

015:00

..."-

RD BUF H

TRANSCEIVERS

f - INTERRUPT
TO DAC B
f - VECTOR
fREGISTER
f - JUMPERS

~
DEVICE
~
ADDRESS ~
JUMPERS rrA3-A12
r-

V3-V8

VECTOR

DACA
REGISTER

CLK

'---

-ti

DAC
A
-V

(SEE NOTE 1)

LD DAC A L

--~ ~

-'"

5A~2A

CLR

'--INXL

1--+15V
DC-DC
CONVERTER

RANGE

~~~AIN +15

~BDAL15:~ BUS

CLK

~P9

AMP L
RTC IN L

I - ~Sl

PROG

(8-CH
DIFFER- ~
P2
ENTIAL)

SEt
P5

GSO

MUX

CH 0-16

CONVERTER
(DBR)

I 16-CH I
.-

AID

pA
BIPOLAR

-15V

AID DATA 00-015

NOTE 1 DAC B CIRCUIT (NOT SHOWN)
IS THE SAME AS DAC A CI RCUIT
NOTE 2 RANGE SELECT JUMPERS
DAC A JUMPERS
RANGE
± 10 V
3A-5A
0-10V
lA-2A

Figure

DAC B JUMPERS
lB-5B
2B-38

AXV11-C Functional Block Diagram

Signal Generated

Address

DACA
DACB

base address + 4 SEL 4 L
base address + 6 SEL 6 L

RANGE SELECT
JUMPERS
(SEE NOTE 2)

AGND

1/2 SCALE

AXV11·C
The signals SEL 4 Land SEL 6 L create LD DAC A and LD DAC B, respectively, to load either DAC A or DAG B. The digital data from the
LSI-11 bus goes to the bus transceivers, then into the selected DAC
register. Once the register is loaded, the digital-to-analog conversion
takes place. The DAC IG generates a current to the input of an amplifier. The current is a function of the value in the register. (A zero offset
adjustment is made at the input to this amplifier.)
The amplifier converts the current to a voltage proportional to its input, with its maximum range selected by jumpers. (A trim pot provides
adjustment to full-scale range.) The voltage is then amplified to become DAC A OUT or DAC B OUT at the I/O connector J 1.
PROGRAMMING THE AXV11·C
The AXV11-C has four programmable registers.
Register

Read or Write

Standard
Address

Control/status register
Data buffer register
DAC A register
DAC B register

Read/write
Read only
Write only
Write only

170400a
170402s
1704041
170406e

This paragraph describes setting the mode of operation, defines the
standard device address and vector address, and defines the bits in
each register.
Selecting AXV11·C Mode of Operation
The user determines the AXV11-G mode of operation. The user selects
how the AID conversions are to start and how the digital data is transferred to the LSI-11 processor.
Starting an AID Conversion - An AID conversion can be started in
one of the following three ways.
1. Realtime clock input: set bit 5 in GSA.
2. External trigger enable: set bit 4 in CSA.
3. AID START bit: set bit 0 in CSA.
Transferring AID Data to LSI·11 Processor - The digital data can be
transferred to he LSI-11 processor or memory by a programmed I/O
transfer or by servicing an interrupt request. Using LSI-11 instructions,
a programmed I/O transfer can write the GSR in the AXV11-C, read the
GSR and wait for an AID DONE bit (bit 7), then read the DBR to get the
AID data.

AXV11-C
If interrupts are used, set the DONE tNT ENABLE bit (bit 6) of the CSA.
When the AID conversion is complete, the AID DONE bit (bit 7) sets,
and an interrupt occurs to the LSI-11 processor. The processor services the interrupt request and gets the AiD data. After receiving the
data, the software clears the AID DONE bit in the AXV11-C's CSA.
An interrupt may also be programmed to occur on an error condition
by setting bit 14 in the CSA.
AXV11-C Standard Device Address
The AXV11-C permits assigning a device address between 160000aand
177770a. The standard device address is 1704OOa. This is the starting
address for the AXV11-C registers. The control/status register (CSR)
receives this first address; the AID data buffer register automatically
receives the starting address + 2, or 170402s. The DAC A register receives the starting address + 4, and the DAC B register receives the
starting address + 6. Table 1 shows the AXV11-C standard address
and vector address assignments. Please see section on selecting
AXV11-C device address.
Table 1

Description

AXV11-C Standard Address Assignments

Mnemonic

First
Module
Address

Second
Module
Address

170400
170402
170404
170406

170420
170422
170424
170426

400

410
414

Registers
Control/Status
Data Buffer
DACA
DACB

CSR
DBR

DAA
DAB

Interrupt Vectors
AID DONE
ERROR

404

AXV11-C Standard Interrupt Vector Address
The interrupt vector can be assigned between 0 and 770a in increments
of 10a. The standard base interrupt vector for the AXV11-C is 400a. This
vector is aSSigned to the AID DONE interrupt request. If the DONE INT
ENABLE bit (bit 6) is set in the CSR, the AID DONE bit (bit 7) generates
an interrupt request to the LSI-11 processor. When the request is ac77

AXV11-C
knowledged by the LSI-11 processor, it starts the interrupt service routine at address 400.
The AXV11-C can also interrupt on an error. The error interrupt request
is automatically assigned the base vector address + 4, or 404s. If the
ERROR INT ENABLE bit (bit 14) is set in the CSR by the program, an
interrupt request will occur at the occurrence of any error (bit 15 set).
The standard interrupt vector addresses are shown in Table 1. See selecting AXV11-C interrupt vector address section to change the base
interrupt vector address.
Control/Status Register (CSR)
The control/status register is a read/write register, shown in Figure 2.
A control instruction is written into the CSR; the AID status is read
from the CSA. Table 2 defines the bits of the CSA.

AID CONTROL/STATUS REGISTER (READIWRITE)

170400
(BASE ADDRESS)

~~~7c==~y==7T~~Tt~~~
ERROR

MULTIPLEXER
ADDRESS

ERROR
INT ENA

AID
DONE

RTC
ENABLE

DONE
INT ENA

GAIN
SELECT

EXT
TRIGGER
ENABLE

AID
START

NOT USED

Figure

AXV11-C Control/Status Register (ReadlWrite)

Table 2

AXV11·C Control/Status Register Bit Assignments

Bit

Name

Description

AID START

Write Only-When set this bit
starts an AID conversion. This
bit is cleared by internal logic
after starting conversion. It always reads back O.

Not used

2,3

GAIN SELECT

ReadlWrite-Set these bits to
select the gain for the analog
input as follows.

AXV11-C
Description

Name

Bit

Gain

GS1 (bit 3)

GSO (bit 2)

1
2
4
8

0
0
1
1

0
1
0
1

EXT TRIG
ENABLE

Read/Write-When set this bit
allows an external trigger to
start an AID conversion.

RTC ENABLE

Read/Write-When set this bit
allows a realtime clock input to
start an AID conversion.

DONE
INTERRUPT
ENABLE

Read/Write-When set this bit
enables an interrupt on AID
DON E (bit 7). Both bits are
cleared by INIT.

AID DONE

Read Only-This bit is set at
the end of an AID conversion
and is reset by reading the AID
data buffer register.

8-11

MULTIPLEXER
ADDRESS

ReadlWrite-These bits select
1 of 16 analog input channels.

12-13

Not used

ERROR
INTERRUPT
ENABLE

ReadlWrite-When set this bit
enables an interrupt on an ERROR (bit 15). Both bits are
cleared by INIT.

ERROR

ReadlWrite-When set this bit
indicates that an error has occurred due to one of the fo"owing .
• Trying an external start or
clock start during multiplexer
settl i ng time .
• Trying a start while an AID
conversion is in process.
79

AXV11-C
Name

Bit

Description
• Trying any start while the AID
DONE bit is set.
This bit can be cleared by writ
ing the CSR or by an INIT.

Data Buffer Register (DBR)
The data buffer register is a read-only register that holds the digital
data after the AID conversion is complete. The DBR can be read after
the AID DONE bit is set in the CSA. Figure 3 shows the format for the
DBR; Table 3 defi nes its bits.
The AID DONE flag is cleared after reading the register or on initializing the LSI-11 bus.

AID DATA BUFFER REGISTER (READ ONLY)

;~~2ADDRESS+2d\

I J,I I

SIGN
(USED FOR 2'$
COMPLEMENT
NOTATION ONLY)

MSB

AID DATA

Figure

Table 3

AXV11-C Data Buffer Register Bit Assignments

I I
I

LSB

AXV11-C Data Buffer Register (Read Only)

Bit

Name

Description

0-11

AID DATA

These bits hold the parallel
digital outputs after completion
of the AID conversion in one of
the following data notations.
• binary
• offset binary
• 2's complement
The user selects the data notation; see table 6.

AXV11-C
Bit

Name

Description

12-15

SIGN

These bits are the sign for the
bipolar inputs when using 2's
compiement notation. These
bits are not used for binary or
offset binary notation.

DAC A and DAC B Registers
DAC A register and DAC B register are 12-bit write-only registers. They
are loaded from the LSI-11 bus with digital data to be changed to an
analog voltage. Figure 4 shows the format for each register. Each DAC
responds immediately to the data word placed in its register. Each
register holds its last value until it is written again or power is turned
off.

DACA DATA REGISTER (WRITE DNLY)

15
170404
(BASE ADD R ESS +4)

~...I.-....L...----L..---1._L--...I.-...J......---L..---l.----J_..L...-......L.-.......L...----l.----J----J
~

_ _~y_ _ _ _k~~_ _ _ _ _ _ _ _ _ _~.~_ _ _ _ _ _ _ _ _ _ _ _~1

NOT USED

MSB

DAC INPUT

LSB

DAC B DATA REGISTER (WRITE ONLY)

170406
(BASE ADDRESS +6)

~-N-OT~~-S-ED--~~=SB~---------D-AC~TN-P-UT----------~L~S~

Figure

AXV11-C DAC A and DAC B Registers

Selecting AXV11·C Device Address
The AXV11-C device address is the 1/0 address assigned to the control/status register. The device address is selected by means of jumpers A3 through A12. (See jumper groups A and V in Figure 5.) The jumpers allow the user to set the device address within the range of 160000a
to 177770a. The device address is usually set at 170400s, as shown in
Figure 6. A jumper installed decodes a 1 in the corresponding bit position; a jumper out decodes a O.

AXV11-C
The user may select the format of the input data and output range and
polarity. However, both registers must use the same input data notation - binary, offset binary, or 2's complement format. The output ranges can be ± 10 V or 0 V to + 10 V. The two registers must use the same
polarity. Table 4 shows the expected output of the DAC for the selectedinput.

Table 4

AXV11-C DAC Input and Output Values

Polarity

Input Data
Notation

Input Code
(Octal)

Output
Voltage

Unipolar

Binary

007777

+ full scale

000000

Bipolar

Offset binary

2's
complement

007n7

+ full scale

004000
00000o

003777

+ full scale

00000o

004000

- full scale

CONFIGURATION
The AXV11-C, shown in Figure 5, has jumpers to set up the device address, the interrupt vector address, the analog configuration, and the
DAC configuration. The user may select the AID input range, polarity,
and the output data notation. The user may select the D/A input data
notation, output range, and polarity of each DAC.
There are two types of jumpers on the board. Some are point-to-point
jumpers, in which each jumper pin has a unique number. A jumper is
installed from one numbered pin to another. The other jumpers are
pairs of jumper pins. With each jumper type, a jumper wire is installed
across a pair of pins.
This paragraph provides details on setting up the circuit board.

JUMPER

RTC IN L

GROUPD~:::::::::::::::::::::::::::::::::::::::::____________--------------~L_____
~~

FULL SCALE

PG ZERO

DC-DC CONVERTER

ZERO

e 9i
... 6

Ig ~~

00 3
1002
1
02.1

JUMPER
GROUP E

AID CONVERTER MODULE

NOTE:
THE JUMPERS SHOWN ARE THE
FACTORY-SHIPPED CONFIGURATION.

A3
IO'Ili

c.u

110 6\.2

LO ~ I

FS RANGE ADJ A
ZERO OFFSET ADJ A
JUMPER
GROUPC
FS RANGE ADJ B
ZERO OFFSET ADJ B

e.9
A4

_l.. --- .a,

.1. ~

.Jol

435 L __ C!:.'l~ __ .J
89 6 7
4

II) l51 A5
00lA6
100 A7
100lV4
JUMPER
00 V3
1001 V7 ~-/GROUPS
00V6
AANDV

~ ~V5

2341 5

2 D

I(H)lV8

~1'2
Bro~~
11

~~ill

100lA9
100lAl0
00 All
t!"!t A 12

_A8

3 1

----~-----~·------------~7L-------~\------~~
JUMPER
GROUP B

JUMPER
GROUP A

Figure

JUMPER
GROUP P

JUMPER
GROUP D

AXV11-C Physical Layout

JUMPER
GROUP F

~..........

o•

AXV11·C

~ ~ ~

~ ~ ~ ~ ~

A12 All Al0 A9
AB A7 A6 A5 A4 A3
IN
OUT OUT OUT IN OUT OUT OUT OUT OUT
LOGICAL 1 = IN
LOGICAL 0 = OUT

Figure

Selecting AXV11-C Device Address

Selecting AXV11-C Interrupt Vector Address
The AXV11-C is capable of generating two interrupt vectors to the LSI11 processor. These interrupts, if enabled, occur when the AID DONE
bit or the ERROR bit is set in the CSA. The base interrupt vector address is assigned to AID DONE. (The ERROR interrupt automatically is
assigned the base interrupt vector address + 4.)

The base interrupt vector address can be set within the range of 0 to
770s, in increments of 10s. It is usually set to 400a by jumpers V3
through V8, as shown in Figure 7. (See jumper groups A and V in Figure 5.)

T T T T

VB V7 V6 V5 V4 V3
IN OUT OUT OUT OUT OUT

Figure

7 Selecting AXV11-C Interrupt Vector Address

Selecting AXV11·C Analog Input Range, Type, and Polarity
The AXV11-C allows software control over the full-scale range selection. The effective ranges provided by the programmable gain are as
follows.
84

AXV11-C
Gain

Effective Input Range
Unipolar
Bipolar

1
2
4
8

OVto +10V
oV to +5 V
o V to + 2.5 V
oV to ± 1.25 V

±10V
±S V
± 2.5 V
± 1.25 V

Table 5 shows the jumpers that must be installed to set up the analog
input type. The board comes from the factory set for 16-channel single-ended, bipolar inputs. Refer to jumper group P in Figure 5.

Table 5

Selecting AXV11·C Analog Input Type

Input Type

Install Jumpers

Single-Ended Inputs·

P1 to P2; P8 to P9

Differential Inputs

P2 to P3; P4 to P5

* Factory configuration

NOTE
Jumpers P6 to P7 are factory installed for the pro·
grammable gain feature and should be left in.
Selecting AXV11·C AID Output Data Notation
The AXV11-C allows the user to select the data notation to be used for
the AID output, as either binary, offset binary, or 2's complement notation. Table 6 shows the jumpers that must be installed to select the
data notation. Refer to jumper groups 0 and E near the handle of the
board, shown in Figure 5.
Selecting Source of External Trigger
The AID conversions within the AXV11-C can be started in one of the
following three ways.
1. Under program control using the AID START bit in the CSR.
2. Bya realtime clock input at J1 pin 21 or at pin RTC IN.
3. By an external trigger, either at J1 pin 19 or at the BEVNT line on
the LSI-11 bus.
The user can select the source of external trigger using two jumpers
on the board. (See jumper group F in Figure 5.) Table 7 shows the
jumpers to install to select the source of the external trigger.

AXV11-C
Selecting AID Output Data Notation

Table 6

Jumpers
AID Output
Data Notation

Input Voltage

Binary

OUT

+ full scale
OV

007777

+ full scale
OV
- full scale
+ full scale
OV
- full scale

007777

Offset binary*

2's
Complement

OUT

Output Code
(Octal)

00000o

004000
00000o

003777
00000o

174000

Factory configuration

Table 7

Selecting AXV11-C External Trigger
Jumpers

External Trigger
Source

BEVNT line (LSI-11
bus)

OUT

EXT TRIG IN (J1 pin
19)

OUT

Selecting AXV11-C 01A Configuration
The user can select the input data notation and the output voltage
range for the two D/A converters on the AXV11-C. DAC A and DAC B
can be configured for different polarities; however, the input data notation selected and the output polarity selected must be the same for
each DAC. Refer to Table 8 to set up DAC A; refer to Table 9 to set up
DAC B. Jumper groups A, B, and D for the DACs are found below the AI
D co,!ve~er module, shown in Figure 5.

AXV11-C
Table 8

Selecting DAC A Jumper Configuration

D/A Input Data Notation
Range and
Polarity

Binary

Offset Binary

2's Complement

±10V

N/A

3A to 5A*
D1 to D3

3A to 5A
Dto D2

oto + 10 V

1A to 2A
D1 to D3

N/A

* Factory configuration
Table 9

Selecting DAC B Jumper Configuration

D/A Input Data Notation
Range and
Polarity

Binary

Offset Binary

2's Complement

±10V

N/A

18 to 58*
D1 to D3

18 to 58
Dto D2

oto +10V

28 to 38
D1 to D3

N/A

* Factory configuration

INTERFACING TO THE AXV11-C
Figure 5 shows the location of the I/O connector J1 on the AXV11-C.
Analog input signals enter the board through this connector, and DAC
output signals leave through this connector. Up to 16 single-ended analog inputs can be connected to J1 (CH O-CH 15), or up to 8 differential
analog inputs can be connected to J 1 usi ng CH O-CH 7 and RETURN 07. A real-time clock input and an external trigger can also be connected to J1. Under program control, these two inputs can be enabled to
start an AID conversion.
RTC IN has a separate pin, found near the printed circuit board handle, for easy installation of a wire jumper from a clock board, such as
the KWV11-C ClK OVFl tab.

BA11-M
BA11-M EXPANSION BOX
INTRODUCTION

The BA11-M expansion box provides a convenient means for expanding LSI-11 bus systems. Each box includes an H9270 LSI-11 bus-structured backplane and an H780 powersupply system mounted in an enclosure with a blank front panel.
The BA11-M is shown in Figure 1. Mechanical and mounting details
are shown in Figures 2 and 3.
FEATURES
• Provides power and cool i ng for LSI-11 Bus options

• Accepts quad-or-double height modules
• Eight double-height (four quad) LSI-11 Bus slots available for options
• LSI-11 Bus power sequencing signals provided by the powersupply
• LSI-11 Bus line frequency clock signal provided by powersupply
• LSI-11 Bus backplane compatible with LSI-11, LSI-11/2, LSI-11/23,
and SBC-11/21 processors, memories, and interface modules
• Rack-mountable in standard RETMA 19 inch-wide-rack
• UL listed; GSA certified
SPECIFICATIONS
Dimensions (including bezel)
Width
Height
Depth
Without mounting brackets
With mounting brackets

48.3 cm (19 in)
8.9 cm (3.5 in)
34.3 cm (13.5 in)
38.1 cm (15.0 in)

" WeiQht
Shipping

18.1 kg (40 Ib)

Operati ng temperature *

5° to 60° G (41° to 140° F)

Operating humidity

10% to 95% with a maximum
wet-bulb temperature of 32° C
(90° F) and a minimum dew point
of 2° G (36° F)

The maximum allowable operating temperature is based on operation at sea
I~vel, i.e., at 760 mmHg (29.92 inHg); maximum allowable operating temperature will be reduced by a factor of 1.8 0 C/1000 m (1.0 0 F/1000 tt) for
operation at higher altitude sites.

BA11-M
AC input power

100-127 Vrms, 50 ±1 Hz or 60 ±1
Hz, 400 W maximum, or
200-254 Vrms, 50 ±1 Hz or 60 ±1
Hz, 400 W maximum

DC output power

+5 Vdc ±3%, 0-18 A load (static
and dynamic)
+ 12 Vdc ±3%, 0-3.5 A load (static and dynamic)
Maximum output power: 120 W
(total)

Recommended circuit breaker
rating

15 A and 115 Vac or at 230 Vac

CONFIGURATION

The BA11-M is a rack-mounted enclosure that provides power and
cooling for eight double (four quad) LSI-11 Bus module slots. It accepts either double-or-quad-size modules. Modules are accessible
from the front of the box. A cable area is provided for routing I/O
cables from the modules to the rear of the box where a cable clamp
allows cables to be strain-relieved before leaving the box. An ac ONI
OFF switch and linecord are located at the rear of the box. Two of the
eight slots for double-size modules are normally used for cabling and
termination, which leaves six bus slots available for options. Note
that multiboard options that require the special backplane interconnection on connections card 0 (Le., RLV11) are not accommodated by
this expansion box. The BA11-M is available in two line voltage variations: 115V and 230V. Each version accommodates either 60 Hz or 50
Hz line frequency.
When installing an expansion box to expand from a single to a dual
backplane system, the BCV1B bus expansion option and TEV11 bus
terminator option (or equivalent) must be used. Install the BCV1 B modules and cables as shown in Figure 4. The terminator must be installed in the option location in the last box. When installing the
BCV1 B cable set, disregard any "This side up" labels that may be on
the BC05L cables. Ensure that the red line on each cable is toward
the center of both modules and that J1 on each board is connected to
J1 on the second board, and similarly, J2 on both boards. Ensure that
the cables have no twists. Carefully fold excess cable as shown in
89

BA11-M
Figure 4. Figure 5 illustrales proper installation of the BCV1B and
TEV11 options.
When expanding from a second to a third backplane, the BCV1A bus
expansion option is required, in addition to the items required for
expansion to the second backplane.
NOTE
BCV1A and BCV1 B cables must differ in length by
121.92 cm (4 ft) (minimum).

The completed installation for a three-backplane system using the
BCV1A option is shown in Figure 5. In addition to this option, the
BCV1 B option is required to connect the first backplane to the second backplane; a 120 bus termination is required in the last optionslot
in the third backplane.

Figure 1

BA 11-M Expansion Box

BA11-M

1 4 - - - - - 4 4 . 8 em (17.625 inl _ _ _---1..
~1

8.9 em

~==============================::j.~'

l.8em~1

U.sinl

:..
1III_~_ _ _ _ _ _ _ 48.lcm _ _ _ _ _ _~..
~.
119inl

34.)cm
.......---------(1l.5inl--------~1~

POWER SUPPLY
AIR

AIR

t - - - - - - - - - - / t--T"""--...J
FRONT

PROCESSOR
MEMORY AND
DEVICES

,'·5207

Figure 2

SA 11-M Assembly Unit

BA11-M
FRONT VIEW

0.64 em
(0.25 in)

-T I

1.27 em (0.5 in)

---"

-t-

".45cm
(1.75 in)

1-- -

o
TOP OF A STANDARD
FRONT PANEL

1.59 em (0.625 in)

-+-

S.9em
(3.5 in)

1.27 em (0.5 in)

-t0 -t-

1.59 em (0.625 in)

1.59 em (0.625 inl

o
o
I

--- ---

-+-

1.27 em (0.5 in)

*
46.5 em
(1S.313 in)

I..

0.95 em
10.375 in)

f -r----fc::l
1

8.9 em 4,4S em
'15 I (1 75 I

.L4=L.c::l________________________CJ~ ~Ds:se:;;,
I~~~::i

FRONT OF BOX 1 PANEL REMOVED)

...~-----------119.0'n)----------~~

,;[IL..---_ _ _[}-,
~
..

_ _ _ 34.3em _ _
113.50 inl

~1
..

L3.sem
11.5 inl
" ·5206

Figure 3

SA 11-M Cabinet Mounting

Figure 4

BA 11-M Expansion Box Interconnections (two-backplane
system)

BA11-M

CPU
2

11/03

2·BOX
SYSTEM

IBCV1B·061
BAll·ME, MF
EXPANDER BOX
(TERMINATOR
REQUIRED
TEVll,
REVll·A, OR BDVll·AA)

6
8

CPU
2

11/03

5
IBCV1B-061
6
3·BOX
SYSTEM

BAll-ME, MF
EXPANDER BOXES
(TERMINATOR
REQUIRED
TEV11,
REVll·A, OR BDVll·AA)

11
IBCV1A.l01
12
14

NOTES
1.
INCLUDED IN BCV1B BUS EXPANSION OPTION. (CABLES ARE AVAILABLE IN 2,4,6, OR
12 FT LENGTHS.)
2.

INCLUDED IN BCV1A BUS EXPANSION OPTION. (CABLES ARE AVAILABLE IN 2,4,6, OR
12 FT LENGTHS.)

INCLUDED IN TEVll BUS TERMINATOR OPTION.

THE LSI·ll BUS IN RESTRICTED TO 15 OPTIONS, MAXIMUM. THESE OPTION SLOTS WOULD
ONL Y BE USED WHEN PREVIOUS OPTION(S) OCCUpy MORE THAN 1 OPTION LOCATION.

BCV1A AND BCV1B EXPANSION CABLES MUST DIFFER IN LENGTH BY 4 FT (MIN).
MA-2000

Figure 5

BCV1 A Installation

BA11-N
BA11-N MOUNTING BOX
INTRODUCTION
The BA11-N mounting box is designed to be used as a mounting box
or as an expander box for an LSI-11-bus-based system. Each mounting box (Figure 1) includes an H9273 backplane assembly, an H786
power supply, and an H403-A ac input panel mounted in an enclosure
with a blank front panel (BA11-NE, NF) or bezel assembly (PDP-11/03LC, LD).
FEATURES
• Nine slots for double-or-quad-size modules
• Powerful and reliable 240-watt switching powersupply, which is
both voltage- and frequency-independent
• Module cooling
• Designed to meet small-system applications
• Modular design for ease of servicing
• LSI-11 bus power-sequencing signals provided by power supply
• Line frequency signal provided by powersupply
• Unique backplane interconnection for custom multiboard options
• LSI-11 bus backplane-compatible with LSI-11, LSI-11/2 and LSI-111
23 processors, memories, and interface modules
• Rack-mountable in standard RETMA 19-inch-wide rack
• UL listed, CSA certified and complies with VDE and IEC requirements

SPECIFICATIONS
Tables 1 and 2 show BA11-NE and BA11-NF mounting box specifications, including the H786 powersupply.
Dimensions (including bezel)
Width
Height
Depth
Without mounting brackets
With mounting brackets

48.3 em (19 in)
13.2 em (5.19 in)
57.8 em (22.7 in)
67.96 em (26.75 in)

Weight (without modules)

20 kg (44Ib)

BA11-N
Operating temperature*

5° to 60° C (41° to 140° F)

Operating humidity

10% to 95%, with a maximum
wet-bulb temperature of 32° C
(90° F) and a minimum dew point
of 2° C (36° F)

Input voltage
SA11-NE
SA11-NF

115 Vac
230 Vac

Input current**
SA11-NE
SA11-NF

12 A max
6Amax

Circuit breaker rating

15 A at 115 Vac or 230 Vac

* The maximum allowable operating temperature is based on operation at sea

level, i.e., at 760 mmHg (29.92 inHg); maximum allowable operating temperature will be reduced by a factor of 1.8 0 C/1000 m (1.0 0 F/1000 ft) for
operation at higher altitude sites.
** Input current consists of that used by the SA 11-N, itself, plus whatever cur-

rent is supplied via the convenience ac outlet (J3) to an expander box; the
total current must be less than the maximum specified.

DESCRIPTION
The H9273 backplane assembly consists of a backplane, a card frame
assembly, and two cooling fans. The H9273 9-slot backplane
assembly will accept nine LSI-11 bus double-height or quad-height
modules (except for MMV11-A 4K X 16 core memory modules). The
PDP-11/03-LC and the SA 11-NE operate on 115 V and the PDP11/03-LD and the SA 11-NF operate on 230 V. Mechanical and mounting details are shown in Figure 2.

BA11-N

Figure 1

SA 11-N Major Assem blies

f---(~;
-r-""
.. -- __ _:2 ;i
132 em
c

=--7
L
578 ern -------.J
1 ---{C27,ni_
I

'5 19 on!

-l...

Figure 2

SA ll-NE and SA ll-NF Assembly Unit
97

BA11-N
The ac input box, powersupply, and H9273 logic assembly are attached to the logic-box base. The powersupply assembly is hinged to
the base and can be swung open to expose the internal components;
with little effort, the entire assembly can be removed from the base
and replaced. LSI-11 bus modules are inserted in the backplane from
the rear of the box through an access door that is equipped with
strain reliefs for LSI-11 bus and communications cables.
When the unit is to be mounted in an equipment rack, the logic-box
cover is attached to the rack with mounting hardware. The logic-box
base slides into the mounted cover and a spring-button assembly engages to prevent the base from being accidentally pulled out of the
cover.
Table 1

Item

Specification

Current rating

5.5 A at 115 Vrms
2.7 A at 230 Vrms

Inrush current

100 A peak, for % cycle at 128
Vrms or 256 Vrms

Apparent power

630 VA

Power factor

The ratio of input power to apparent power shall be greater than
0.6 at full load and low input voltage

Output power

+5 Vdc ±250 mV at 22 A
(A minimum of 2 A of 45 Vdc
power must be drawn to ensure
that the + 12 Vdc supply regulates properly)
+12 Vdc ±600 mV at 11 A

Power-u pI power-down characteristics
Static performance
Power-up
BDCOK H goes high; 75 Vac
BPOK H goes high; 90 Vac
Power-down

BPOK H goes low; 80 Vac
BDCOK H goes low; 75 Vac
98

BA11-N
Table 1

BA11-N Power Supply Specifications (Cont)

Item

Specification

Dynamic performance
Power-up

3 msec (min) from dc power within specification or to BOeOK H
asserted
70 msec (min) from BOeOK H asserted to BPOK H asserted

4 msec (min) from ac power off to
BPOK H negated
4 msec (min) from BPOK H negated to BOeOK H negated
5 tLsec (min) from BOCOK H negated to dc power as of specifications

Power-down

CONFIGURATION
The procedure for mounting the BA 11-N mounting box in an
equipment rack is presented below.
Installing the Logic Box Cover - The logic-box cover is mounted in
the equipment rack as shown in Figure 3.
1. When the unit is shipped, the logic-box cover is held to the base
by four screws (these are used only in non-rack-mounted applications) and a single shipping screw, which, for safety, must be in
place whenever the unit is moved or shipped. First, remove the
four screws that attach the cover to the base. Then open the rear
door and remove the shipping screw.
2. A safety locking device is found on the right side of the unit
(when looking at the front). This device, a spring-button assembly, is attached to the side of the ac input box. When the unit is
closed, the button on this assembly fits into the rear hole of two
holes in the right side of the cover. This mechanical interlock can
be overridden by pushing the button in from the outside of the
cover while, at the same time, pulling the logic-box base to get
the button past the hole. The base can then be pulled out of the
cover to its extended position; at this position, the button pops
into the front of the two holes, preventing the base from being
inadvertently pulled entirely out of the cover. Open the base to
the extended position and then release the button from the front

BA11-N

3.
4.
5.
6.

hole. Slowly pull the base entirely out of the cover and set the
base out of the way.
Attach the Tinnerman nuts to the cabinet uprights in eight places.
Mount the cover to the front cabinet uprights using four panhead screws (10-32 x 0.62 Ig) and four No.8 lockwashers.
Attach the two support brackets to the cover using four Phillips
pan-head screws (8.32 x 0.38 Ig) and four No.8 lockwashers.
Attach the support brackets to the rear cabinet uprights using four
Phillips pan head screws (10-32 x 0.62 Ig) and four No. 10 flat
washers.
Slide the unit into the cover. It will be held in place by the springbutton assembly. To slide the unit forward again it will be necessary to release this spring button.
If the system is to be moved or shipped, the shipping screw must
be replaced.
/1
CAB. UPIIIGHTS

/ !I

liEF

2910TY 81 liEF

635CM
12500 IN. I liEF'
12 IOTY 21

',-

'465 CM
118.31IN.IIIEF
11.471NI

13.1eCM
IS.19'N)

5.71 CM
(2.26IN.l

Figure 3

SA 11-NE and SA 11-NF Cover Mounting Dimensions
100

BA11-N
Installing the Logic-Box Base in the Cover - Set the rear of the logicbox base on the support flanges of the cover and slide the base in
until the spring-button assembly engages in the extended position.
Take care not to pinch the cables while sliding in the base. Release
the spring-button and push the base all the way in until it engages in
the closed position. Take the followi ng steps to complete the i nstallation.

NOTE
The base being- installed is either the main base,
i.e., the one containing the CPU, or an expander
base (two expander boxes can be added). Modify
the following instructions to suit the kind of base
you are installing, e.g., if there is a blank front panel,
skip the first half of step 1.

1.
2.

Put the AUX switch in the front panel in the OFF position; put
the ON/OFF switch on the ac input box in the OFF position.
When the AUX switch on the front panel is in the ON position,
the two wires of the powercontroller cable are common. Connect
the free end of the cable to the input circuiI of the powercontroller so that the AUX switch controls the application of primary
power to the controller. Keep the AUX switch in the OFF position.
Loosen the cable strain reliefs and open the rear door of the box
to install the LSI-11 bus expansion cable assemblies. Two cable
assemblies are used. Table 2 describes the assemblies and tells
where to insert the assembly modules. (Figure 4 illustrates module placement.) When inserting the modules, make sure the connectors are on top.
Close the rear door; bring the bus cables out under the left
strain relief and the communcations cables out under the right
strain relief. Adjust the strain reliefs so that the cables are held
firmly, but are not pinched or crushed. Secure the strain reliefs
and the rear door. Make sure the cables will not bind when the
base is pulled out to the extended position.

101

BA11-N
Table 2

LSI-11 Bus Expansion Cable Assemblies

Assembly

Assembly
Composition

BCV1B-XX

Two BCOSL-XX
cables

BCV1A-XX

Insert Modules In

One M9400-YE module

Slots A and B of the
first open row after all
other LSI-11 bus options have been
installed in the main
box.

One M9401 module

Slots A and B of row 1
of expander box 1

Two BCOSL-XX
cables
One M9400-YD
module

Slots A and B of the
first open row after all
other LSI-11 bus options have been installed in expander
box 1

One M9401 module

Slots A and B of row 1
of expander box 2

NOTE
"-X" in the cable assembly number denotes length,
which can be 60.96,121.92,182.88, or 304.80 cm (2,
4, 6, or 10 ft). (Each cable of an assembly is the
same length.) When both assemblies are used in a
system (boxes), the lengths must differ by 121.92
cm (4 ft). To facilitate servicing, the BCV1 B cables
should be 182.88 cm (6 ft) in length, while the
BCV1A cables should be 304.80 cm (10 ft) in length.

102

BA11-N

CPU
32KB MaS MEMORY
1
2
I-BOX
SYSTEM

IIIOJ

5
6
BDVll-AA

CPU
32KB MaS MEMORY
1
2
11/03

5
6
2-BOX
SYSTEM

BCV1B-06

8
9
BAll-NE. NF
EXPANDER BOX

10
11
12
13
BDVll-AA

MA-1999

Figure 4

Configuring Large Box

103

BA11-S
BA11·S EXPANSION BOX
INTRODUCTION
The BA11-S is both a mounting box and an expander box designed for
use with the PDp·11/23-PLUS computer system and LSI·11/23 modules. Each BA11-S box comes with an H9276 logic assembly, two
cooling fans (a 70 cfm fan to cool the logic boards and a 100 cfm fan
cools the power supply), and an H403-B AC input box. A layout of
these components in the BA11-S box is illustrated in Figure 1.
The BA11-S mounting box is available for both 120 V and 240 V systems, and a choice of two front panel models can be selected. Listed
below are the six models:
Model

Primary Power/Front Panel

BA11-SA

120 V/Control Panel

BA11-SB

240 V/Control Panel

BA11-SC

120 V/Blank Panel

BA11-SD

240 V/Blank Panel

BA11-SE

120 V/No Cable or Expansion Modules/Blank
Bezel

BA11-SF

240 V/No Cable or Expansion Modules/Blank
Bezel

FEATURES
• 9 slots for double-and quad-height LSI-11 modules
• Provides power and cooling for LSI-11 bus modules
• Modular design for easy servicing

SPECI FICATIONS
Dimensions (including bezel)
Width
Height
Depth
Without mounting brackets

48.3 cm (19 in)
13.2 cm (5.19 in)

Operating temperature*

5° to 60° C (41° to 140° F)

57.8 cm (22.75 in)

104

BA11-S
10% to 95%, with a maximum
wet bulb temperature of 32 0 C
(90 0 F) and a minimum dew pOint
of 2 0 C (36 0 F)

Operating humidity

I nput voltage
BA11-SA, SC, SE
BA11-SB, SD, SF

120 Vac
240 Vac

I nput current
BA 11-SA, SC, SE
BA11-SB, SD, SF

6Amax
3Amax

+ 5 V at 2 A to 36 A
+ 12 V at 0.0 A to 5 A

Output Voltage
*

The maximum allowable operating temperature is based on operation at
sea level, i.e., at 760 mmHg (29.92 inHg); maximum allowable operating tern·
perature will be reduced by a factor of 1.80 C/100 m (1.0 0 F/100 tt) for opera·
tion at higher altitude sites.

H403-B

BEZE L ASSEMBLY
PRINTED CIRCUIT BOARC,

(l00CFM)

CARD FRAME ASSEMBLY

H9276 BACKPLANE
MA-65S4

Figure

BA11-S Major Assemblies

105

BA11-S
When the equipment is being operated at the maximum allowable
temperature, air flow must maintain air temperature rise to a maximum of 7°e (12.6° F)
DESCRIPTION

Figure 2 illustrates the BA11-S with its logic box cover removed. The
ac input box, power supply, and the H9276-B logic assembly (which
includes the fans and the backplanes) are attached to the logic box
base. The bezel is attached to the power supply. The power supply
assembly is hinged to the base and can be swung open to expose the
internal components. The complete assembly can be easily removed

H9276B LOGIC ASSEMBLY
(INCLUDES CARD FRAME, BACKPLANE, AND FANS)

Figure

BA11-S Logic Box with Cover Removed
106

BA11-S
from the base and replaced. Extended LSI-11 bus modules are inserted in the backplane from the rear of the box through the rear access
door.
When the unit is mounted in an equipment rack, the logic box cover is
attached to the rack with mounting hardware. The logic box base
slides into the rack-mounted cover. A restraint cable is attached between the H403-8 ac input box and the rack frame to prevent the base
from being pulled completely out of the cover by mistake.

AC Input Box (H403-B)
Power is provided to the H403-8 box from the ac mains by either a 120
V line cord or a 240 V line cord. The box includes an ac input connector, a circuit breaker, a line filter, and a switch that makes the correct
connections to the fans and the power supply for both the 120 VAG
and 240 VAG line voltages. The output of the box is taken to the fans
and the power supply by an AG power harness. Connectors P1 and P4
(see Figure 3) of the harness are Mate-N-Lok connectors (12-pin and 9pin, respectively), while P2 and P3 are molded AG plugs that break out
of the harness to plug into terminals on the fans.
H7861 Power Supply
The H7861 power supply is attached to the logic assembly with two
screws and held to the logic base by two hinge assemblies. When the
two screws are removed from the logic assembly, the complete power
supply assembly can be tipped open on the hinges, allowing access
to the printed circuit boards mounted within. The assembly can be
easily removed by first removing the screws, unlatching the hinges,
and disconnecting a maximum of four cables (three, if a blank front
panel is used).
Three printed circuit boards contain all the power supply components. The control board and the power monitor board are inserted in
connectors that are mounted on the master board. The regulated dc
voltages generated on the master board are sent to the H9276 backplane by a dc harness that connects on both ends to screw terminals.
The signals generated on the control board are applied to the backplane and to the front panel by two different signal cable assemblies.

H9276 Backplane
The H9276 is a 9 x4 (nine slots of four rows each) backplane in which
both double and quad modules can be inserted. Rows A and 8 of
each slot supply the extended LSI-11 bus signals, and these signals,
in turn, are bused to each of the nine slots. The pins of the G and D
107

POWER SUPPLY, H7861

rMASi-ERBOARD{54.;4583) - - - ---,
I
I
I
I

r - ACiNPUT-=BOx.-H403-B ,

~~N----'

""
_n ~ :,- ~Bl

J
r-----L _______

AC HARNESS
(70140931

FLI

(70-17971-01
DC HARNESS
+5 VDC
+12 VDC

SWITCHING AND POWER TRANSFORMERS,
DC VOLTAGE REGULATORS

I
I

....I

....l-

....I
SIGNAL CABLE
(70-11411-0KI

SIGNAL CABLE (70114111

--,
II

TOPOWER-f]
CONTROLLER
J2

FRONT PANEL

L_7<l!..39~0!.l

Figure

BA 11-S Functional Block Diagram

BA11-S
rows are not bused; however, the pins of the adjacent slots are connected. This not only precludes the necessity of top connectors, but
also provides the means for designing buses whose lengths are
determined by the number of modules in a set. The C and 0 rows of
the backplane are referred to collectively as the CO bus. More information on the H9276 backplane is detailed in the H9276 section
which follows in this handbook.

BA11·S Expander Box
The BA11-S expander box for LSI-11 bus systems is physically identical to the BA11-S main box, with the exception of the front panel (usually only one box has a functional front panel). BA11-SE and BA11-SF
expander boxes are identical to the BA11-S main box, except for the
blank bezel. BA11-SE and BA11-SF boxes are identical to the BA11-SC
and the BA11-S0, except that they have 9404 and 9405 modules and
BC020 cables.
The BA11-S box with the H9276 backplane functionally differs only
slightly from the BA11-N box (with H9275 backplane). The BA11-S box
has four more address lines than the BA11-N box; these lines are
needed for 22-bit operation.

INSTALLATION
The procedure for mounting the BA11-S mounting box in an equipment rack is described below.
Installing the Logic Box Cover
The logic box cover is mounted in the equipment rack as depicted in
Figure 4. This illustration also shows the mounting dimensions and
the cover mounted to the four cabinet uprights.

2.
3.

When the unit is shipped, the logic box cover is held to the base
by four screws (these are used only in non-rack-mounted applications), and a single shipping screw, which, for safety, must be in
place whenever the unit is moved or shipped. First, remove the
four screws that attach the cover to the base; then open the rear
door and remove the restraining screw.
Attach the Tinnerman nuts to the cabinet uprights in eight places.
Mount the cover to the front cabinet uprights using four 10-32
screws and four No.1 0 flat washers.
109

BA11-S
CAB UPRIGHTS
REF

46.5 CM
(18.31 IN) REF

r - - - - 3.73 CM

(1.47 IN)

13.18 CM
(5.19 IN)

"NOTE:
ALL HARDWARE FURNISHED
WITH 11 123B/BA 11S
MOUNTING BOX.

Figure

4.
5.

5.71 CM
(2.25 IN)

BA11-S Cover Mounting Dimensions

Attach the two mounting brackets to the cover using four 8-32
Ph ill i ps screws.
Attach the support brackets to the rear cabinet uprights using
four Phillips 10-32 Phillips screws and four No. 10 flat washers.
Slide the unit into the cover. In the rear of the unit, attach a restraining cable to the stud on the H403-B ac input box with a No.
8 nut. Anchor the other end of the restraining cable the chassis or
patch panel.
If the system is to be moved or shipped, the shipping screw
must be replaced.
110

BA11-S
8.

A safety restraining cable is located on the right rear side of the
unit (when viewing from the front). This cable (DEC Part No. 1215700-06), when attached to the rear of the AC input box, keeps
the logic box base from being overextended. When the system
unit is in the closed position, the restraining cable loops around
at the rear of the unit inside the cover. When the base is pulled
out from the cover to its extended position, the 44 cm (17-1/2inch) restraining cable holds the box, preventing the base from
accidentally being pulled completely out of the cover.
To pull the base completely out of the cover, remove the nut on
the H403-8 ac input box stud, and then remove the restraining
cable. Slide the base forward and set the base out of the way.
Set the rear of the
logic box base on the support flanges of the cover and slide the
base in until it is in the closed position. Take care not to pinch
the cables while sliding the base in.
Installing the Logic Box Base in the Cover -

NOTE
A stud extending from the H403-8 acinput box is
used to anchor a restraining cable (DEC Part No. 1215700-06) to the patch panel, thereby preventing the
logic box base from accidentally being pulled completely away from the cover assembly.

Perform the following steps to complete the installation

NOTE
The box being installed is either the main box, i.e.,
the one holding the CPU, or an expander base. Modify the following instructions to satisfy the type of
box that is being installed; e.g., if there is a blank
front panel, skip the first half of step 1.

1.
2.

BA11-S

troller so that the AUX switch controls the application of primary
power to the controller. Keep the AUX switch in the OFF position.
To install the expanded LSI-11 bus expansion cable assemblies,
open and remove the rear access door by turning the two quarterturn screws in the lower corners of the door, then swing the door
out and up to unhook it. Then put it aside. The BC02D cable and
module configurations are listed in Table 1. When inserting the
modules, make sure the connectors are on top.
After installing the correct module and cable, let the cable extend out of the rear opening, and replace the access door in the
reverse of the way it was removed. Loosen the two Phillips
screws on the correct cable strain relief to allow enough space
for the cable to exit without binding when the box is extended.
After installing the cables, retighten the two screws.

Table 1

Extended LSI·11 Bus Expansion Cable Assemblies

Assembly

Assembly
Arrangement

BC02D

Two BC02D-03
cables

Insert Modules In

One M9404-00 module

Rows A and B of
the first open slot
after all other extended LSI-11 bus
options have been
installed in the
main box.

One M9405-YA module

Rows A and B of
slot 1 of expander
box 1

112

BA11-VA
BA11-VA MOUNTING CHASSIS/POWER SUPPLY
INTRODUCTION

The BA11-VA is a small form-factor package providing mounting
space and power for four LSI-11/2 or LSI-11/23 family modules. This
package, plus the high functionality of DIGITAL's microcomputer
products, allows LSI-11 microcomputer applications to be implemented within a space smaller than that required for many eight-bit systems.
FEATURES

• Four slots for double 5.2 in x 8.9 in-(13.2cm x 22.8cm) high modules.
• LSI-11 bus backplane compati ble with the LSI-11/2, LSI-11/23, and
SBC-11/21 processors, memories, and interface modules.
• Power and cooling for modules.
• ac power indicator.
• Mounting hardware for tabletop or fixed-position usage.
• Off/On switch located at the rear of the unit.
• External connection to let users add a remote restart switch.
• UL listed, CSA certified, and complies with VDE and IEC requirements.
SPECIFICATIONS

Mechanical
Capacity

4 dual LSI-11 bus modules

Size

11.7 in x 13.38 in x 3.62 in
(29.71cm x 33.98cm x 9.19cm)

Weight

10 Ib (4.5kg)

Mounting

4 rubber feet for table-top use
and 4 metal bracke1s for fixedposition mounting (installed by
user)

Environmental
Operating
Temperature
Relative
Humidity
Power
Output

10% to 95% (non-condensing)

5.6 amps at + 5V max
1.6 amps at + 12V max
113

BA11-VA
Input
Voltage

115Vac-50/60Hz or + 230V-501
60Hz (selectable by user)

Current

3.0 amps at 115V (maximum)
1.5 amps at 230V (maximum)

Power cord

6 ft 3 in (1.9m) for 115 Vac to be
used with a NEMA 5-15P wall
socket. User suppl ies cord for
other power requirements.

External Connectors
Optional
Poweroutlet

Plug type (user-supplied) for use
with the power outlet: 3-pin
AMP plug-Part #1-480700-0
AMP contact pins-Part
#350547-3

Remote
Restart

Plug type (user-supplied) for use
with the remote-restart outlet: 2pin AMP plug-Part #1-480698-0.
AMP contact pins-Part
#350547-3

Model
Number

BA11-VA-LSI-11 Bus mounting
chassis and powersupply

DESCRIPTION

The BA11-VA is designed as a low-cost mounting enclosure for a wide
range of mounting configurations. Two types of mounting hardware
let the BA 11-VA be used as a tabletop unit or be attached to a flat
surface in any plane.
The BA 11-VA does not generate a signal for use as a line-time clock in
the processor module. If this function is required, the MXV11 multifunction module, which includes a 60Hz clock, should be used. If
powerfail capability is needed, external hardware is required.
For applications where the mounting of the BA11-VA prevents easy
user access to the chassis, the capability is provided for adding an
external restart switch. A simple, single-pole/single-throw switch can
be located up to ten feet from the box and connected using a standard connector. Momentary closure of this switch causes the processor to go to the user-selected powerup mode for the system.
The powersupply has more capacity than normally used by the four
LSI-11 bus modules that can be mounted in the chassis. Therefore, a
114

BA11-VA
connector is supplied to let this power be used for other electronic
equipment located in the same area as the computer.
The SA 11-VA powersupply can be configured through selector
switches to operate throughout the world. The product is UL-listed,
CSA- certified, and complies with VDE and IEC requirements.

OPTIONAL POWER
OUTLET
RESTART OUTLET

~/ ~'RFLOW

FUSE

INTAKE
CABLE GND

• "DO 4." 112 CM. FOR

CABLf-S

RUBBER FEET

ACCESS

MODULE ACCl~S
DOOR

ADD 3'" .79 CM. rDR DEC
SUPPLlF.D FiXED MOUNTING

B'lACKET
REAR VI[W

115

BDV11
BDV11 DIAGNOSTIC, BOOTSTRAP, TERMINATOR
INTRODUCTION
The BDV11 module has 2K words of read-only memory (ROM) that
contains both diagnostic programs and bootstrap programs. These
programs are user-selectable by setting dip switches. The diagnostic
programs test the processor, the memory, and the user's console. The
bootstrap programs are used to boot a number of LSI-11-compatible
peripherals. The module also contains 120-ohm bus terminator circuits.
Space is available on the module to allow the user to add up to 2K
words of erasable programmable ROM (EPROM) and up to 16K words
of ROM.
A HALT/ENABLE switch allows the user to start and stop the processor and a RESTART switch enables the user to reboot the system. The
module also has four programmable light-emitting diodes (LEDs) that
indicate a failure in a program and monitor the tests in progress. All
the switches and indicators are edge-mounted on the module for easy
access.
NOTE
There are two versions of the BDV11 module: revisions 0 and A. The revision 0 module was produced
in limited quantities and does not incorporate all the
characteristics of revision A. The differences
between these modules are listed at the end of this
section.

FEATURES
• Programmed ROMs with bootstraps for RXV11, RXV21, RLV11 , and
RKV11 disk options

• DECnet bootstraps for DLV11-E, DLV11-F, and DUV11 serial line
units
• Capable of booting a system automatically with no operator intervention
• Can automatically load and start a 16K word program from
ROM/EPROM to RAM
• 12-bit readable configuration register
• 16-bit read/write maintenance register
116

BDV11
• Software-controllable line-time clock (LTC)
• Power OK monitor, green LED
• 4-bit LED programmable display
• RESTART and HALT switches
• 120-ohm bus terminator
SPECIFICATIONS
Identification

M8012

Type

Quad

Power

+5 Vdc ±5% at 1.6 A
+12 Vdc ±3% at 0.07 A

Bus Loads
AC
DC

2
1

DESCRIPTION
The functions of the BDV11 are shown in Figure 1. The transceiver and
control functions control the transfer of data between the bus and the
BDV11. The ROM address function decodes the address data from the
bus and uses the socket selection and ROM address functions to access the memory located on the BDV11. The ROM address function is
also used to transfer data into the data selection function. Then data
is placed on the LSI-11 bus by the control and transceiver functions.
The data for the read/write registers are also transferred in and out by
using the transceiver and control functions. The BDV11 uses powerup, BVENT, and display functions for monitoring program operations.
Transceiver
The transceiver logic monitors the LSI-11 bus BDAL lin~s for the address of a BDV11 register or the address of a ROM location. When a
register or a ROM has been addressed, the transceiver logic gates the
address onto the BDV11 DAL lines. If a register was addressed, the
transceiver logic generates the address match signal that activates the
control logic. If a ROM address was generated, then the DAL lines
transfer the address to the ROM address selection logic. The transceiver logic is also used to transfer data from the DAL lines to the LSI11 bus BDAL lines. When the transceiver receives XMIT H, the data
can be from either a register or ROM address.

117

BHALT L

BREPLY L

BRPLY L
RUN/HALT SW
RESTART SW

PDWER·UP
LOGIC

f---- DC NOK UH

BDCDK H

r----

BSYNC L

BWTBT L

----------------I,r----,

BDOUT L - - - - - - - - - - - - - - - - 1
BDIN L
SYNC L/H - - - - I

SYNC L/H

BRPLY L
XMIT UH

CONTROL
LOGIC

DAL <0,2> H - - - - I

INWD L
REG L/H
OUT LB/HB L

ADDRESSr----.l---------.J

SEL 012/4/6 L

MATCH
R<015>H

.....
.....

BDAL <0 15> L

BB57 L

DC005

[)AL <0 15> H

TRANSCEIVER~~~~~~~~r_--·--L----~-------~

ROM
ADDRESS
SELECTION
LOGIC

A<10,14>H

m
DATA
SELECTOR

<
.....

.....

SELO L
REG L
OUT LB/HB L

INWD L
XMIT H

SEL 4 L
REG L
INWD L

SEL2 L
REG UH
XMITH
OUTLS/HS L

DAL<O 3> H

SEL6 L
REG L
OUT LB L

SEL 4 L
REG L
OUT LB L

Figure 1

ROM
SOCKETS

5B<1.2> L
SE<1 2> L
ST< 1 2>
SP<1 8> L

SEVNT L _ -

DAL6 H

A<O 10> H

BDV11 Block Diagram

0<0,15> H

XMIT H

BDV11
Control
The control logic consists of a DC004 protocol chip and an 82523
PROM. The control logic is enabled by the address match signal from
the transceiver logic. The PROM monitors some of the DAL lines and
the address match signal and generates an enable signal for the
DC004 chip whenever any of the assigned bus addresses (173000 to
173777) is placed on the BDAL lines. The DC004 chip generates all the
protocol signals used with the LSI-11 bus to allow data transfers. The
control logic also generates the control Signals for the read/write register's ROM address selection and the ROM socket selection logic.
The bus control signals are defined in the appropriate processor handbook.
Read/Write Registers
The read/write register logic consists of two 8-bit universal shift registers. When the registers are being read, the control logic asserts XMIT
H and the information on the DAL lines is the data within the shift
registers. When the registers are to be written into, the XMIT signal is
negated and the registers are placed into a load condition. The registers are clocked and the information on the DAL lines is loaded into
the registers as data. The registers are cleared when power is turned
on or when the system is booted.
ROM Address Selection
The ROM address selection logic uses the contents of the peR register and the LSI-11 bus address to determine the address of the BDV11
ROM locations. Each ROM has 2048 10 addresses available. The logic
selects the high byte of the peR register if bit 8 of the LSI-11 bus is one
and selects the low byte if bit 8 is a zero. The selected byte is shifted to
the right one bit and used as the high byte of the BDV11 address. The
low byte of the LSI-11 bus address is shifted one bit to the right and
used as the low byte of the BDV11 address. The complete BDV11
ROM address is formatted by using a combination of the high and low
bytes generated. Table 10 is a listing of how the peR contents and the
LSI-11 bus addresses are used to generate ROM addresses.
Socket Selection
The socket (or ROM) selection logic (Figure 2) consists of two decoders (E30 and E35) that provide the outputs used to select the high byte
and low byte sockets. The user can program A10 Hand A14 H inputs
to these decoders by selecting jumper wires W1-W4 and W9-W12 to
determine the configuration designation described in Table 2. The

119

BDV11
SB1 Land SB2 L outputs are used to select the 4K of
diagnostic/bootstrap DIGITAL programs. The SE1 Land SE2 L outputs are used to select the 2K words of user PROM. The SP1 L to spa
L outputs are used to select the additional 16K words of user ROM.

+5V
A14 L
G1

SP8 L
SP7 L

A14 H

SPS L
SP5 L

74S138
E35

SP4 L
All H

A12 H

SP2 L

SPl L

A10 H

SP3 L

A13 H

W12
2B

2YO

2Y2

SEl L

2Y3

SE2 L

2Yl
74LS139
E30

lYO

SBl L

1Y1

SB2 L

1Y3

1Y2

W9
745138 TRUTH TABLE
Gl

OUT LOW

IL
L I L I H
L ! H I L

YO (SP8 L)

Y3 (SP5 L)

Y4 (SP4 L)

Y5 (SP3 L)

Y6 (SP2 L)

Y7 (SP1 L)

B
L

W10

74LS139 TRUTH TABLE (EACH HALF)
G

Yl (SP7 L)
Y2 (SP6 L)

OUT LOW

YO(5B1 U

Y1 (SB2 L)

Y2 (SE1 L)

Y3 (SE2 L)

M.A 1349

Figure 2

Socket Selection Logic
120

BDV11
ROM Address
The ROM address logic uses the socket select logic outputs and address lines AD to A1D to select the desired address. The diagnostic/bootstrap ROMs are enabled by SB1 Land SB2 L and are addressed by AD to A 1D. The user EPROMs are enabled by SE1 Land
SE2 L and are addressed by AD to A9. The user ROM sockets are
enabled by SP1 L to SP8 L and addressed by AD to A9. The output
data from the ROMs is sent to the data selector logic.
Data Selector
The data selector receives data from the ROMs and the registers of the
BOV11. This data is stored until the outputs are enabled by XMIT. The
data is then gated to the OALD-15 bus lines where it is transferred to
the LSI-11 bus by the transceiver and control logic.
Display
The display logic consists of four flip-flops and four LEOs. The
contents of the display register (address 177524) are gated into the
flip-flops and the outputs light the display LEO indicators. The pattern
of the display indicates to the user the type of program error when a
failure occurs.
Power-up
The power-up logic includes the ENABLE/HALT switch and the RESTART switch. In normal operation, the ENABLE/HALT switch is in the
ENABLE position. When the switch is placed in the HALT position, the
bus signal BHALT L is asserted. The processor enters the halt mode
and responds to the console OOT commands. To resume processor
operation, the user must set the switch to ENABLE and enter a "P"
command from the console.

The RESTART switch must be cycled to reboot the system. When the
switch is cycled, a capacitor is charged to disable the bus BOCOK H
signal and OCNOK L is asserted to initialize the BOV11 registers.
When the capacitor discharges, the BOCOK H signal is enabled, the
processor carries out a power-up sequence, and normal operation is
resumed.

BVENT
The BVENT logic uses a switch located in E21 that lets the user control
the LTC function. When the switch is open, the bus BVENT L signal
can be controlled by the LTC signal generated in the LSI-11 bus power
supply. When the switch is closed, the BVENT L signal can be controlled by the program.
121

BDV11
CONFIGURATION
The BDV11 is factory-configured in Table 2 by DIGITAL to let the user
expand the diagnostic and bootstrap programs by adding 2K words of
EPROM and 16K words of ROM/EPROM memory. The user can modify
the configuration for his own software requirements. Thirteen jumper
wires are located on the module as shown in Figure 3 and identified in
Table 1. Eight are used for selecting sockets, and five are used to accommodate various types of memory chips. The switches used to select programs are listed in the Programming section below.

Socket Selection
The socket selection logic is controlled by jumpers W1-W4 and W9W12, which can be configured in seven different ways, as shown in
Table 2. Group A assigns the PCR pages and socket selections.
Groups 8-G let the user choose where to begin program execution,
such as having the processor execute instructions directly from a system ROM or EPROM when power is turned ON, rather than from the
diagnostic/bootstrap ROM.
Table 1
Jumper
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13

Selectable Jumpers
Function
Socket selection
Socket selection
Socket selection
Socket selection
Chip selection
Chip selection
Chip selection
Chip selection
Socket selection
Socket selection
Socket selection
Socket selection
Chip selection

122

~
~

tlM

-c::::Y

.....
I'\)

c.u

:I;W

Figure 3

BDV11 Switch and Jumper Locations

c
<
.....
.....

Table 2
High Byte
Socket

Memory Configuration

Low Byte
Socket

Configuration
Designation

ROM
Address

PCR
Page

Selection
Signal

0-2K
4K-6K
16K-18K
20K-22K

0-17
40-57
200-217
240-257

SB1 L
SB1L
SB1 L
SB1 L

2K-4K
6K-8K
18K-20K
22K-24K

20-37
60-77
220-237
260-277

SB2 L
SB2 L
SB2 L
SB2 L

4K-5K
0-1K
20K-21 K
16K-17K

40-47
0-7
240-247
200-207

SE1 L
SE1 L
SE1 L
SE1 L

5K-6K
1K-2K
21 K-22K
17K-18K

50-57
10-17
250-257
210-217

SE2 L
SE2 L
SE2 L
SE2 L

------.---

4K Diagnostic/Bootstrap (DIGITAL)

-L

I\)

E53
(2)

E48
(1)

E58
(4)

E44

(3)

-'="

B
C
0

C
0

2K User EPROM
E57
(3)

E40
(1 )

C
0
E52
(4)

E36
(2)

..."----_..

B
C
0

----- ._--------------_._---_._--_. __._._-

m
C

<
.....
.....

Table 2
High Byte
Socket

Memory Configuration (Cont)

Low Byte
Socket

Configuration
Designation

ROM
Address

PCR
Page

Selection
Signal

E49
(1)

16K-18K
16K-17K
0-2K
0-1K

200-217
200-207
0-17
0-7

SP8 L
SP8 L
SP8 L
SP8 L

18K-20K
18K-19K
2K-4K
2K-3K

220-237
220-227
20-37
20-27

SP7 L
SP7 L
SP7 L
SP7 L

20K-22K
18K-19K
4K-6K
4K-5K

240-257
240-247
40-57
40-47

SP6 L
SP6 L
SP6 L
SP6 L

22K-24K
22K-23K
6K-8K
6K-7K

260-277
260-267
60-77
60-67

SP5 L
SP5 L
SP5 L
SP5 L

16K User ROM
E54
(2)

F
G

....
N

E59
(4)

E45
(3)

F
G
E60
(6)

E41
(5)

F
G
E55
(8)

E37
(7)

F
G

c
<
......

......

Table 2
High Byte
Socket

Memory Configuration

Low Byte
Socket

Configuration
Designation

ROM
Address

PCR
Page

Selection
Signal

E3B
(9)

A
E
F
G

24K-26K
17K-1BK
BK-10K
1K-2K

300-317
210-217
100-117
10-17

SP4L
SP4 L
SP4 L
SP4 L

16K User ROM {cont}
E51
(10)

- - - - . , , - - -.. ..-- --

-L

E47
(12)

(11 )

E43
(14)

E39
(16)

E42

A
E
F
G

26K-2BK
19K-20K
10K-12K
3K-4K

320-337
230-237
120-137
30-37

SP3 L
SP3 L
SP3 L
SP3 L

E46
(13)

A
E
F
G

2BK-30K
21 K-22K
12K-14K
5K-6K

340-357
250-257
140-157
50-57

SP2 L
SP2L
SP2 L
SP2 L

E50
(15)

A
E
F
G

30K-32K
23K-24K
14K-16K
7K-BK

360-377
270-277
160-177
70-77

SP1 L
SP1L
SP1 L
SP1L

....<
C

BDV11
NOTE
The parenthetical numbers in the socket columns indicate the order for installing each ROM.

Memory Configuration
The user can change the configuration of the BDV11 memory structure by using socket selection jumpers W1-W4 and W9-W12; the standard configuration is in Table 2. This table also indicates the installation order for the PROM/ROM chips. The B, C, D, E, F, and G
configurations show as alternate ways the user can map the ROM
memory. Details about selecting a configuration using the socket selection jumpers are shown below.
Configuration
Designation W1

Socket Selection Jumpers*
W2

I
X
X
X

R
X
X
X
R

A
B
C
D

R
X
X
X

R
R

W10

W11

R
R

R
R
X
X

W12
R

R
R
X
X
X

X
X
X

X
X

* I = Installed, R = Removed, X = Irrelevant

Chip Selection
The system ROM sockets can be occupied by either 2K ROMs or 1K
ROMs. The ROM socket logic uses jumpers W5-W8 and W13 to select
the type of ROM that can be used on the BDV11. Table 3 shows
jumper configurations and the type of ROM or PROM used with these
configurations.
Control Registers
The BDV11 module has five hardware registers that are softwareaddressable. These registers are assigned individual addresses that
cannot be changed or modified. The registers are described in the
following paragraphs; their designations and addresses are listed in
Table 4.

127

BDV11
Page Control Register (PCR) - This register is word- or byte-addressable and can be read or written. The PCR is a 16-bit register that
consists of two 8-bit bytes. The low byte consists of bits 0-7 and the
high byte consists of bits 8-15. When the low byte of the PCR is equal
to page 6, then bus addresses 173000-173777 accesses the 128 ROM
locations in the block 1400-1577. When a bus address falls in this
range, the logic considers only the low byte of the PCR. However, if the
bus address is in the range 173400-173777, only the high byte of the
PCR is used to select the ROM location.
Table 3

Chip Selection Jumpers

Jumpers Inserted 1
ROM Type

W13

2708 2
2716 3
8316E4
8316P

R
R
I
R

I
R
R
R

R
I
R

NOTES
1. I = Inserted; R = Removed.
2. CB2 and DB2 must be supplied with external -5 V power.
3. Use only +5 Vdc type components.
4. Chip select signals must be programmed as follows:
CS1
LOW
5.

CS2
LOW

CS3
LOW

Chip select signals must be programmed as follows:
CS1
LOW

CS2
LOW

CS3
HIGH

128

BDV11
Table 4

Standard Assignments

Read/
Write

Size

Address

Page Control
Read/Write
Configuration*
Display*
BEVNT*

R/W
R/W
R
W
W

16 bits
16 bits
12 bits
4 bits
1 bit

177520
177522
177524
177524
177546

* Dual-purpose register.

Table 5 relates the PCR contents to the PCR page for pages 0-17. If the
PCR is loaded with data 000400, the PCR low byte contains data 000,
while the high byte contains data 001. The PCR bytes can be loaded
separately. To select ROM locations 1600-1777, for instance, one need
only load the PCR high byte with page 7; thus, the high byte contains
007, while the low byte can contain anything. Table 6 lists the PCR
contents for the remaining PCR pages.
Read/Write Register - This register is used as a maintenance register for the diagnostic programs. The register is cleared when power is
turned on or when the RESTART switch is activated.
Configuration Register - This 12-bit read-only register is used to
select for execution diagnostics or bootstrap programs for maintenance and system configuration. Bits 0-11 of the register are set by
switches E15-1 through E15-8 and E21-1 through E21-4. These
switches are associated with BDAL(0:11)L, when an individual switch
is closed (on), the corresponding BDAL signal is low (1).
Display Register - This 4-bit register is used for program control of
the diagnostic LED display. When bits 0-3 of the register are set, then
the corresponding LEDs are off. The register is cleared by turning
power ON or by activating the RESTART switch.

129

BDV11
Table 5

PCR Contents/Page Relationship, Pages 0-17

PCR Page

PCR Contents

PCR High Byte
(Bits 15-8)

0
1

000400

001

000

2
3

001402

003

002

4
5

002404

005

004

6
7

003406

007

006

10
11

004410

011

010

12
13

005412

013

012

14
15

006414

015

014

16
17

007416

017

016

Table 6

PCR Low Byte
(Bits 7-0)

Pages 20-57, 200-377

Page

Contents

Page

Contents

20,21
22,23
24,25
26,27
30,31
32,33
34,35
36,37

010420
011422
012424
013426
014430
015432
016434
017436

260,261
262,263
264,265
266,267
270,271
272,273
274,275
276,277

130660
131662
132664
133666
134670
135672
136674
137676

40,41
42,43

020440
021442

300,301
302,303

140700
141702

130

BDV11
Table 6
Page

Pages 20-57, 200-377 (Cont)

Contents

Page

Contents

44,45
46,47
50,51
52,53
54,55
56,57

022444
023446
024450
025452
026454
027456

304,305
306,307
310,311
312,313
314,315
316,317

142704
143706
144710
145712
146714
147716

200,201
202,203
204,205
206,207
210,211
212,213
214,215
216,217

100600
101602
102604
103606
104610
105612
106614
107616

320,321
322,323
·324,325
326,327
330,331
332,333
334,335
336,337

150720
151722
152724
153726
154730
155732
156734
157736

220,221
222,223
224,225
226,227
230,231
232,233
234,235
236,237

110620
111622
112624
113626
114630
115632
116634
117636

340,341
342,343
344,345
346,347
350,351
352,353
354,355
356,357

160740
161742
162744
163746
164750
165752
166754
167756

240,241
242,243
244,245
246,247
250,251
252,253
254,255
256,257

120640
121642
122644
123646
124650
125652
126654
127656

360,361
362,363
364,365
366,367
370,371
372,373
374,375
376,377

170760
171762
172764
173766
174770
175772
176774
177776

SEVNT Register - Setting bit 6 (100 8 ) removes the clamp from
BEVNT, thus enabling the line-time clock. Under program control, the
user can clamp the BEVNT line low (thus stopping the line-time clock).
Opening the BEVNT switch disconnects this function; The register is
cleared (disabling the line-time clock) when the power is turned ON or
when the REST ART switch is activated.
131

BDV11
PROGRAMMING
The BOV11 contains dip switches that let the user select diagnostic
and bootstrap programs for execution. Four LEOs indicate when a
program fails. A green LED monitors the + 12 Vdc and +5 Vdc and is
lit when power is ON. A HALT/ENABLE switch and a RESTART switch
let the user start and stop the processor. The switches and LEOs are
shown in Figure 4.

HALT ~ ENABLE
J3 J2

DO 0

S2
RESTART
SWITCH

ENABLE
SWITCH

00000

D1 D2 D3 D6 D4

OFF

__ 1
_2
_3

_4
_5
__ 6

OFF

_2
_3

_4
_5

E2l
(DIAGNOSTIC/BOOTSTRAP
SWITCHES. BEVNT SWITCH)

(DIAGNOSTIC/BOOTSTRAP
SWITCHES)
MA·134Q

Figure 4

BOV11 Switches and Indicators

Diagnostic/Bootstrap Switches
Dip switch units E15 and E21 let the user select diagnostic programs
and/or a bootstrap program. Switches A1-A8 represent switches 1-8
132

BDV11
of E15, and switches 81-84 represent switches 1-4 of E21. The programs selected by these switches are listed below. These 12 switches
make up the configuration register that can be read at address
177524.
Switches A 1-A4 are defined as follows:
A1
A2
A3
A4
A4

ON
ON
ON
ON
OFF

Execute CPU test upon power-up or restart.
Execute memory test upon power-up or restart.
OECnet boot-A4, 5, 6, and 7 are arguments.
Console test and dialogue (A3 OFF).
Turnkey boot dispatched by switch setting (A3 OFF).

OECnet boot arguments are:
Boot*

DUV11
DLV11-E
DLV11-F

ON
OFF
OFF

OFF
ON
ON

OFF
OFF
OFF

OFF
OFF
ON

All boots other than the DEC net boots above are controlled by the bit
patterns in switches A5 throu~t, A8 and 81 (shown in Table 7) or, if the
console test is selected, by mm~monic and unit number. The console
test prompts with
xx
START?
where xx is the decimal multiple of 1024 words of RAM found in the
system when sized from 0 up in 1024-word increments. The first word
of each 1024-word segment is read and then written back into itself.
Allowed responses are a 2-character mnemonic with a 1-digit octal
unit number or one of two special Single-character mnemonics. The
response must be followed by a RETURN. The special single-character mnemonics are:
y
N

Use switch settings to determine boot device
Halt-enter microcode DDT

* DLV11-E CSR = 175610; DLV11-F CSR = 176500; DUV11 CSR = 160040 if

no devices from 160010to 160036.

133

BDV11
Table 7

Mnemonic

DKn; n<8
DLn; n<4

DXn; n<2

DYn; n<2

Diagnostic/Boostrap Switch Selection

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
·0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

On = 1
Off = 0
134

Program
Selected 1

Loop on test
RKV11 Boot
RLV11 Boot

RXV11 Boot

RXV21 Boot

ROM Booe

BDV11
1.
2.

All unused patterns or mnemonics will default to ROM boot if
switch 82, 83, or 84 is on.
The ROM boot uses switches 82, 83, and 84 to dispatch as folrows:

1
0
0

X
1
0

X
X
1

ROM
Extended diagnostic
2708
Program ROM

where X = Irrevelant
If an unrecognized mnemonic or switch setting (A5 through 81) is
encountered, 82, 83, and 84 are checked for the presence of additional ROM. If present, the ROM boot is invoked. The mnemonic's first
character is placed in the high byte location of 2. 80th characters are
converted to uppercase with bit 7 cleared. Location 0 is loaded with
the binary unit number. If an unrecognized switch setting is encountered instead, a copy of the switches is placed in location 2 with bit 15
set.
If no additional ROM exists, the switch-checking routine will halt or the
mnemonic routine will reprompt.
The above features let the user implement additional features or boots
in additional ROMs without changing to the base ROMs. If the
additional ROM encounters an unrecognized mnemonic, it should
load address 173000 into the PC, which will restart the 80V11 base
ROM and reprompt.
Diagnostic Lights
When a failure occurs in a diagnostic test or in a bootstrap program,
the diagnostic light display indicates the area of the failure as shown in
Table 8. A failure causes the error to be indicated by the display and
an error halt instruction is carried out by the processor. When entering
the halt mode, the processor outputs the PC address at the time of the
error on the console terminal. (The actual error address is one word
less than the terminal printout.) In the halt mode, the processor responds to console OOT commands and the operator can troubleshoot
the error. Table 9 lists the possible address and the cause of some
errors.

135

BDV11
BEVNT L Switch
Contact 5 of dip-socket switch E21 is the BEVNT L switch. When the
switch is off (open), the LSI-11 bus BEVNT L signal can be controlled
by the power supply-generated LTC signal. When the switch is on
(closed), the LTC function is program-controlled, i.e., a single-bit,
write-only register in the logic (address 177546, bit 6) clamps BEVNT L
low when the register is cleared. (The register is automatically cleared
when the power is turned on or when the RESTART switch is cycled.)
Power OK LED
This green LED is lit when the +12 Vdc supply voltage is greater than
+10 V and the +5 Vdc supply voltage is greater than +4 V for normal
operating conditions. The + 12 Vdc voltage and the +5 Vdc voltage
can be measured at the tip jacks as indicated below. (Both J2 and J3
have a 560-ohm resistor in series to prevent damage from a short
circuit; use at least a 20,000 ohm/V meter to measure the vOltage.)

Jack
J1
J2
J3

Color
Black
Red
Purple

Voltage
Ground
+5 Vdc
+ 12 Vdc

HALT/ENABLE Switch
When this switch is in the ENABLE position, the processor can operate
program control. If the switch is placed in the HALT position, the
processor enters the halt mode and responds to console OOT commands. While in the halt mode, the processor can execute single instructions for system maintenance. Program control is reestablished
by returning the switch to the ENABLE position and entering a "P"
command at the console terminal (providing the contents of register
R7 were not changed). Refer to the appropriate processor handbook
for a description of console OOT command usage.

136

BDV11
Table 8

Diagnostic LED Error Display (01-04)*

Bit3

Bit2

Bit 1

BitO

Off

Off
Off

Off
On

On
Off

Off
Off

On
On

Off
On

On
Off

Off

On
On

Off
Off

Off
On

On
Off

Comments*
(Type of Error)

System hung; halt switch on
or power-up mode wrong.
CPU, fault, or configuration
error.
Memory error; R1 points to bad
location.
Console SLU will not transmit.
Waiting for response from
operator.
Load device fault.
Secondary boot incorrect
(location 0 not a NOP).
DECnet waiting for response
from host.
DECnet; received done flag
set.
DECnet; message received.
ROM bootstrap error.

* The light pattern indicates the corresponding test is in progress or failed.

Some tests retry (DECnet) and others will halt the CPU (CPU, memory, nonDECnet boots).

Table 9

List of Error Halts

Address
of Error

Cause of Error

173022

Memory error 1. Write address into itself.

173040

SLU switch selection incorrect. Error in switches.

173046

SLU error. CSR address for selected device. Check
CSR for selected device in floating GSR address
area.
137

BDV11
Table 9

List of Error Halts (Cont)

Address
of Error

Cause of Error

173050

CPl error. RO contains address of error.

173052

Memory error 2. Data test failed.

173106

Memory error 3. Write and read bytes failed.

173202

ROM loader error. Checksum on data block.

173240

CP4 error. RO contains address of error.

173366

ROM loader error. Checksum on address block.

173402

ROM loader error. Jump address is odd.

173532

RL device error.

173634

CPU error 3. RO pOints to cause of error.

173642

In console terminal test, a "no" typed.

173656

RK device error.

173656

Switch mode halt. Match was not made with switches.

173670

Console terminal test. No done flag.

173706

CPU error 2. RO pOints to cause of error.

173712

RX device error.

RESTART Switch
When the RESTART switch is cycled, i.e., moved from one side to the
other and back, the CPU automatically carries out a power-up sequence. Thus, for maintenance purposes, the system can be rebooted
at any time.
Addressing ROM on the BDV11 module
A block of 256 LSJ-ll bus addresses is reserved to address the ROM
locations on the BDVll module. This block resides in the upper 4K
address bank (28K-32K), which is normally used for peripheral-device
addressing, and consists of byte addresses 173000-173776.
138

BDV11
All 2048 locations in a selected 2K ROM (or 1024 locations in a 1K
ROM) can be addressed by just these 256 bus addresses. The logic
includes a page control register (peR) at bus address 177520; the
contents of this read/write register determine which specific ROM
location is accessed when one of the 256 bus addresses is placed on
the BDAL lines. The peR is loaded with "page" information, i.e., the
peR contents point to 1 of 16 (or 1 of 8) 128-word pages in the selected ROM (16 pages X 128 words = 2048 words). For example, if the
peR contents represent pages 0 and 1, then bus addresses 173000173776 access ROM locations 0000-0377; if the peR contents represent pages 10 and 11, then bus addresses 173000-173776 access
ROM locations 2000-2377. Table 10 relates bus addresses, peR
pages, and ROM locations.
At the top of each column of peR pages in Table 10 appear two circuit
component designations; column 1, for example, is headed by
E53/E48. These designations represent the ROMs and EPROMs that
one might find on a BDV11 module. For instance, the BDV11 is supplied with 2K words of diagnostic ROM. The ROM inserted in socket
XE53 supplies the high byte (bits 8-15) of these 2K words, while the
ROM inserted in socket XE48 supplies the low byte (bits 0-7). To access the BDV11 diagnostic ROM locations, the user must load the peR
with the pages in column 1; thus, when 12 and 13, for example, are
loaded into the peR, diagnostic ROM locations 2400-2777 can be
addressed by the LSI-11 BDAL signals. Another variation of the
BDV11 could have 1K-word EPROMs inserted in sockets XE57 -XE40
(E57 supplies the high byte, while E40 supplies the low byte). To access these EPROM locations, the user would load the peR with pages
in column 3; thus, with 44 and 45 in the peR, EPROM locations 10001377 are accessible.

139

Table 10

BDV11 Bus Address/PCR Pages
PCR Pages

ROM
Location
Bus Address
Accessed

173000-173376
0000-0177
173400-173777
0200-0377

.....
~

173000-173376
0400-0577
173400-173777
0600-0777

E53/ E58/ E57/ E52/ E54/ E59/ E60/ E55/ E51/ E47/ E43/ E39/
E48

E44 E40 E36 E49 E45 E41

E37 E38

E42 E46

E50

200 220 240 260 300 320 340

360

201

341

361

202 222 242 262 302 322 342

362

221

241

261

301

321

203 223 243 263 303 323 343

363

173000-173376
1000-1177
173400-173777
1200-1377

204 224 244 264 304 324 344

364

205 225

245 265 305 325 345

365

173000-173376
1400-1577
173400-173777
1600-1777

206 226 246 266 306 326 346

366

207

267 307 327 347

367

227 247

OJ
C

Table 10

BDV11 Bus Address/PCR Pages (Cont)
PCR Pages

ROM
Location
Bus Address
Accessed

E49

E45

E46

E:50

210

230 250 270 310 330 350

:370

211

231

351

:371

173000-173376
2400-2577
173400-173777
2600-2777

212 232 252 272 312 332 352

:372

213 233 253 273 313 333 353

873

173000-173376
3000-3177
173400-173777
3200-3377

214 234 254 274 314 334 354

~374

215 235 255 275 315 335 355

~~75

216 236 256 276 316 336 356

~~76

217 237 257 277 317 337 357

~177

173000-173376
2000-2177
173400-173777
2200-2377

.....
~
.....

E53/ E58/ E57/ E52/ E54/ E59/ E60/ E55/ E51/ E47/ E43/ E:39/

173000-173376
3400-3577
173400-173777
3600-3777

E48

E44 E40

E36

E41

251

E37 E38

271

311

E42

331

c
....<

....

BDV11
As Table 10 implies, the PCR pages are assigned to specific module
ROM sockets. Furthermore, the sockets are assigned specific kinds of
ROMs, as Table 11 indicates, e.g., the diagnostic/bootstrap ROM can
occupy only sockets XE53 and XE48. Thus, a specific ROM can be
addressed only when the PCR contains the page or pages assigned to
the socket that the ROM occupies. For example, if 2K-word ROMs are
inserted in sockets E39 and E50, they can be addressed only when the
PCR contains pages 360-377. The page/socket assignments indicated
in Table 10 apply to the BDV11 module shipped by DIGITAL. There are
eight locations on the BDV11 printed circuit board in which jumpers
are inserted selectively to achieve these assignments. The user can
change the factory arrangement of these jumpers to cause the CPU to
execute instructions directly from a ROM or EPROM of the user's
choice when power is turned on, rather than from the diagnostic
ROMs.

Table 11

Functions of ROM Sockets

Sockets

ROM
Function

Sockets

ROM
Function

XE53/XE48

2K Diagnostic/Bootstrap

XE47/XE42

2K System
ROM

XE58/XE44

2K Diagnostic/
Bootstrap
(reserved for
DIGITAL)

XE51/XE38

2KSystem
ROM

XE57/XE40

1K EPROM

XE55/XE37

2KSystem
ROM

XE52/XE36

1K EPROM

XE60/XE41

2K System
ROM

XE39/XE50

2K System
ROM

XE59/XE45

2K System
ROM

XE43/XE46

2K System
ROM

XE54/XE49

2KSystem
ROM

142

BDV11
Loading ROM into RAM
A utility is provided in the BDV11 firmware which loads user programs
from ROM to RAM at specified (and possibly scattered) addresses and
transfers control to a specified address. This allows a programmer to
write a program (to be stored in ROM) without knowing the BDVll
mapping hardware or having to "ROMize" the program. This utility
loads the DIGITAL-reserved space, the 2K EPROM, or the 16K
ROM/EPROM areas. The utility uses the four highest words of RAM
( <30K) as scratch space.

The format is a modified version of absolute loader paper tape format.
The standard format consists of sequential blocks, organized by byte,
as follows:
1 BYTE
o BYTE
BCl
BCH
ADl
ADH
DATA
CKB

This indicates start of block.
Required.
low-order eight bits of byte count.
High-order eight bits of byte count.
low-order eight bits of load address.
High-order eight bits of load address.
Sequential bytes of data.
Checksum byte.

These frames are repeated as required until a starting address block
is encountered. This is indicated by a byte count of six, which is too
short to allow a data field. The load address of this block is used as the
starting address.
The format skips every 255th and 256th location in the ROM pattern.
These locations are filled with checking information which allows
DIGITAL diagnostics to determine whether the ROMs are good and
inserted in the correct socket.
The ROMs should be inserted as indicated by the ROM address chart.
The user program may be patched by changing only the~ast ROM of a
set and by adding a new data block(s) before the starting address
block. This block will overlay previously loaded data.
Executing ROMs in the 1/0 Page
ROMs may be executed in the 1/0 page provided their starting address is between 173016 and 173376.

143

DC319·AA DLART

DC319-AA DLART
INTRODUCTION
Digital's DC319-AA DLART is a DL-compatible, asynchronous receiver!
transmitter designed for data communications with Digital's microprocessor family. The DLART is used as a peripheral device. It is programmed by the CPU to operate either in 8-bit or 16-bit mode with
asynchronous baud rates varying from 300 to 38.4K. The DLART accepts data characters from the CPU in parallel format and converts
them into a continuous serial data stream for transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the CPU. The DLART will signal the CPU
whenever it can accept new characters for transmission or whenever it
has received a character from the CPU.
The DLART also has an internal baud rate control to reduce support
logic and provides four realtime interrupt outputs to support dynamic
memory refresh for realtime system applications. The CPU can read
the complete status of the DLART at any time. The status includes
data transmission errors and control signals such as BRK-IRQ and
RCV-IRQ. The DLART does not handle device address detection, vector generation, and interrupt arbitration. These must be handled outside the DLART. The DLART provides the DL-defined internal registers: RCSR, RBUF, XCSR, XBUF. Thus, standard Digital software will
work with the DLART. The chip is fabricated in N-channel MOS silicon
technology.

FEATURES
• Asynchronous operation
• Error detection-overrun, framing, and brake generation
• Compatible with both 8- and 16-bit modes of the micro T-11 microprocessor
• I nternal baud rate generation from 300 baud to 38.4K baud
• Four realtime clock interrupt outputs to support dynamic memory
refresh for realtime system applications
• One stop bit only
• Common baud rate for both transmitter and receiver
• 40-pin DIP package
• Single + 5 V supply
• Single TTL clock
144

DC319·AA DLART
0+5V
--:
GND

POWER

¢)D,"-r

BIDIRECTIONA
DATA BUS
DA115·DAlOO

BUS
BUFFER

RD
WlB

.--

BRK·IRQ
RECEIVER
CONTROL

~
RCV.IRQ

SHIFT REG.
{S-"}

SERIAL
DATA IN
MAl NTENANCE

~
V1

REG.
ACCESS
CONTROL

RCSR

J,,\
V
16·BIT

INTERNAL
DATA BUS

A2
A1
AO

l'.

INIT
TEST

RBUF

XCSR
TRANS·
MITTER
CONTROL

XMIT IRO

SHIFT REG.
{P_S}

SERIAL
DATA OUT

-V

XBUF

'"\.....
ClK
PBR I
BRS2
BRS 1
BRS0

REAL TIME
CLOCK IRO'S

BAUD
RATE
CONTROL

76.8KH Z
800 HZ

~~]Z

DLART Block Diagram

vce

TEST

WL~

BRS2

DALOO

BRSl

OALOl

RTClK60 160 H Zl

DAL02

RTCLKSO {SO HZI

DAL03

RTCLK77 176.B KHZI

DAL04

BRKIRO
eLK

DAL05
DAL06

DC319

BRSO
SO ISERIAL DATA OUTI

DAL07
DALOS

XMIT IRO

DALOO

PBRI

DAL10

SI {SERIAL DATA IN}

DALll

RCVIRO

DAL12

RTCLK800 {800H Z }

DAL 13

INIT

DALl4

DAL15

vss

DLART Pin Locations

145

DC319·AA DLART
PIN DESCRIPTIONS
Pin Functions

Pin No.

Name

Asserted
State

Low

Read
When asserted while CS
is asserted and WLB is
unasserted, this control
input causes the contents of the register selected by the A2, A 1 and
AO lines to drive the DAL
lines. This line has no effect if CS is unasserted
or if WLB is asserted.

Low

Chip Select
This input is asserted to
permit data transfers
through the DAL lines to
or from the internal registers under control of the
RD orWLB lines. When
this line goes from asserted to unasserted
while WLB is asserted
and AO is unasserted,
data on the low byte of
the DAL lines is written
into the writable bits of
the register selected by
the A2, A1lines.

WLB

Low

Write Low Byte
When this input goes
from asserted to unasserted while CS is asserted and AO is unasserted,
data on the low byte of
the DAL lines is written
into the writable bits of

146

Description

DC319·AA DLART
Pin No.

Name

Asserted
State

4-19

DAL

High

Data 1/0 Lines
The receivers are active
at all times. The drivers
are active only when CS
and RD are asserted and
WLB is unasserted. The
drivers will go inactive
(tristate) within 50 ns
whenever one or more of
the following occurs: (1)
CS goes unasserted, (2)
RD goes unasserted, or
(3) WLB goes asserted.

High

Register Byte Select
When this input is asserted, the high byte of the
register selected by A2,
A 1 is multiplexed to the
low byte of the DAL lines.
Reading is normal, but attempts to write have no
effect.

22,23

A2-1

High

Register Addr~ss Select
These inputs determine
which DLART internal
register is accessible
through the DAL lines
when the ES line is asserted.

147

Description
the register selected by
the A2, A1 lines. This line
has no effect on internal
registers if CS is unasserted or AO is asserted.

DC319·AA DLART
Pin No.

Name

Asserted
State

Description
AA

00
01
10
11

RCSR
RBUF
XCSR
XBUF

INIT

High

Init
This input is used to reset
only the RCV IE bit in the
RCSR register, and the
XMIT IE, MAINT, and
XMIT BRK bits in the
XCSR register.

RTCLK800

High

800 Hz Realtime clock Interrupt
This output provides an
800 Hz, 50% duty cycle
signal. After being high
for a minimum of 500 ns,
this output can be
cleared externally by
being forced low
(clamped to ground) with
an open collector transistor for a minimum of 100
ns.

RCVIRQ

High

Receiver I nterrupt Request
This interrupt output is
asserted only when both
the RCV DONE and RCV
I E bits in the RCSR are
set. This output can also
be cleared externally by
being forced low
(clamped to ground) by an
open collector transistor

148

DC319·AA DLART
Pin No.

Name

Asserted
State

Description
for a minimum of 100 ns
after being high for a minimum of 500 ns.

High

Serial Input
This input accepts an
asynchronous bit serial
data stream. The input
signal must remain in the
high (marking) state for at
least one half bit time before a high-to-Iow (markto-space) transition is
recognized. A mark-tospace transition is required to determine the
beginning of a start bit
and initiate data reception.

PBRI

Low

Programmable Baud Rate
Inhibit
This input is optionally
held low externally by a
jumper to ground or held
high internally. Holding
this line low disbles software programmable baud
rate selection (clears the
PBR2-0 and PBRE bits)
but makes the OLART OLsoftware compatible.

XMITIRQ

High

Transmitter I nterrupt Request
This interrupt request
output is asserted only
when both the XMIT ROY
and XMIT IE bits in the
XCSR are set. This output

149

DC319·AA DLART
Asserted
Pin No.

Name

State

Description

can also be cleared externally by being forced low
(clamped to ground) by an
open collector transistor
for a minimum of 100 ns
after being high for a minimum of 500 ns.
30

High

Serial Output
This output provides an
asynchronous bit serial
data stream. This line remains high (marking)
when no data is being
transmitted. This line will
remain low when the
XMIT BRK bit in the
XCSR register is set.

ClK

High

Clock In
This input requires a
614.4 KHz ± 0.1 % square
wave. All baud rates and
clocks are derived from
this input.

BRKIRQ

High

Break Detected Interrupt
Request
This interrupt request
output is asserted when
the RCV BRK bit is set
and is unasserted by
TEST or when the RE;3UF
is read. This output can
also be cleared externally
by being forced low
(clamped to ground) by an
open collector transistor
for a minimum of 100 ns
after being high for a minimum of 500 ns.

150

DC319·AA DLART
Pin No.

Name

Asserted
State

RTCLK77

High

76.8 KHz Realtime Clock
Interrupt
This output provides a
76.8 KHz, 50% duty cycle
signal. After being high
for a minimum of 500 ns,
this output can be
cleared externally by
being forced low
(clamped to ground) with
an open collector transistor for a minimum of 500
ns.

RTCLK50

High

50 Hz Realtime Clock Interrupt
This output provides a 50
Hz, 50% duty cycle signal. After being high for a
minimum of 500 ns, this
output can be cleared
externally by being forced
low (clamped to ground)
with an open collector
transistor for a minimum
of 100 ns.

RTCLK60

High

60 Hz Realtime Clock Interrupt
This output provides a 60
Hz, 50% duty cycle signal. After being high for a
minimum of 500 ns, this
output can be cleared
externally by being forced
low (clamped to ground)
with an open collector
transistor for a minimum
of 100 ns.

151

Description

DC319·AA DLART
Pin No.

Name

Asserted
State

BRS2-0

Low

Description

Baud Rate Select
These inputs provide for
external baud rate selection. These inputs are optionally asserted low
externally by a jumper to
ground or held high internally. The receiver and
transmitter baud rate is
determined by these lines
when the PBRE bit is
clear.

210

Baud
Rate

BRS
210

000
001
010
011
100
101
110
111

300
600
1200
2400
4800
9600
19200
38400

HHH
HHL
HLH
HLL
LHH
LHL
LLH
LLL

PBR

Test
This input is used during
module assembly and
test to disable all DLART
outputs. It is also used in
a system during powerup
to reset all internal logic.

High

TEST

REGISTERS
Receiver Control/Status Register (RCSR)

152

DC319·AA DLART
Bit

Name

Description

15-12

Zero (Read-Only)
These bits are always read as
zeros.

RCV ACT

Receiver Active (Read-Only)
When this bit is set, the receiver is active. Set at the center of
the start bit which is the beginning of the input serial data
and cleared one bit time prior
to the leading edge of RCV
DONE or TEST.

10-08

Zero (Read-Only)
These bits are always read as
zeros.

RCV DONE

Receiver Done (Read-Only)
This bit is set when an entire
byte has been received and
transferred to the RCV DATA
BUFFER. This bit is cleared by
reading the RCV DATA BUFFER or by TEST.

RCVIE

Receiver Interrupt Enable
(ReadlWrite)
When this bit is set under program control, the RCV IRQ line
follows the RCV DONE bit. This
allows an interrupt request to
be made when RCV DONE is
set. This bit is cleared by INIT
and by TEST.

05-00

Zero (Read-Only)
These bits are always read as
zeros.

153

DC319-AA DLART
Receiver Buffer Register (RBUF)
15

Al
1

~~~~==~~====~~RO~~==~~==~==~~
RBUF
ol----le---RCVDATABUF----t

Bit

Name

Description

ERR

Error (Read-Only)
This bit is set when the overrun
or the framing error bit is set
and cleared by removing the error-producing condition.

OR ERR

Overrun Error (Read-Only)
This bit is set when a received
byte is transferred to the ReV
DATA BUFFER before the ReV
DONE bit is cleared. An overrun
error indicates that reading of
the previously received byte
was not completed prior to receiving a new byte. This bit is
updated when a byte is transferred to the ReV DATA BUFFER and is cleared by TEST.

FRERR

Framing Error (Read-Only)
This bit is set when a received
byte without a valid stop bit is
transferred to the ReV DATA
BUFFER. This bit is cleared by
TEST or when a received byte
with a valid stop bit is transferred to the ReV DATA BUFFER.

Zero (Read-Only)
This bit is always read as a
zero.

Rev BRK

Received Break (Read-Only)
This bit is set when the serialin (SI) signal goes from a mark
to a space and stays in the

154

DC319·AA DLART
Bit

Name

Description
space condition for 11 bit times
after serial reception starts.
This bit is cieared when the Si
signal returns to the mark condition or by TEST.

10-08

Zero (Read-Only)
These bits are always read as
zeros.

07-00

RCVDATA
BUFFER

Received Data Buffer (ReadOnly)
These 8 bits hold the most recent byte received. When a new
byte is transferred to the RCV
DATA BUFFER, the RCV DONE
bit in the RCSR is set. These
bits are cleared by TEST.

Transmitter Data Buffer (XBUF)

Bit

Name

Description

15-08

Zero (Read-Only)
These bits are always read as
zeros.

07-00

XMITDATA
BUFFER

Transmitter Data Buffer (Readl
Write)
This byte register holds a copy
of the most recent byte written
into it. When a byte is written
into this register, the XMIT ROY
bit in the XCSR register is
cleared. This byte is copied
into the transmitter serial output register whenever that register is empty and the XMIT
ROY bit is clear. The XMIT ROY

155

DC319·AA DLART

Name

Bit

Description
bit is set when a byte is copied
from the XMIT DATA BUFFER
into the serial output register.
Reading the contents of this
register causes no other effect.
This register is cleared by
TEST.

Transmitter Control/Status Register (XCSR)
08

R
A2

XCSR

Bit

Name

Description

15-08

Zero (Read-Only)
These bits are always read as
zeros.

XMIT ROY

Transmitter Ready (Read-Only)
This bit is set when the XMIT
DATA BUFFER is ready to accept a byte. This bit is cleared
by writing to the XMIT DATA
BUFFER and is set by TEST.

XMITIE

Transmitter Interrupt Enable
(ReadlWrite)
When this bit is set under program control, the XMIT IRQ line
follows the XMIT ROY bit. This
allows an interrupt request to
be made when XMIT ROY is
set. This bit is cleared by INIT
and by TEST.

05-03

PBR2-0

Programmable Baud Rate Select*
When the PBRE bit is set, these
bits determine the baud rate as
shown in the table under the
BRS2-0 pins. These bits are

156

DC319·AA DLART
Bit

Name

Description
cleared by TEST or PBRI (programmable baud rate inhibit).

MAINT

Maintenance (ReadiWrite)
This bit is used to facilitate a
maintenance self-test. When
this bit is set, the transmitter
serial output is connected to
the receiver serial input while
disconnecting the external serial input. This bit is cleared by
INIT and by TEST.

PBRE

Programmable Baud Rate Enable*
This bit selects between internal and external baud rate selection. When set, the baud
rate is determined by the PBR2obit in this register. When
clear, the baud rate is determined by the BRS2-0 pins. This
bit is cleared by TEST or PBRI
(programmable baud rate inhibit).

XMIT BRK

Transmit Break (Read/Write)
When this bit is set, the serial
output (SO) I ine is forced to a
space condition. This bit is
cleared by INIT and by TEST.

157

DC319·AA DLART
VALID ADDRESS
ADRS - - - - - '

T PW 100 ns min

CTRL

TAe
READ

TTR
50 ns max

250ns max

10 ns min

DATA

T DS

WRITE

VALID DATA

100 ns min

TDH

o nsmin

T CYC 400 ns min

NOTE: READ CONTROL EQUALS CS ASSERTED AND RD ASSERTED AND
WLB UNASSERTED.
WRITE CONTROL EQUALS CS ASSERTED AND WLB ASSERTED
AND AO UNASSERTED.

Write/Read Data and Control Cycle

NOTE
READ CONTROL EQUALS CS ASSERTED AND RD
ASSERTED AND WLB UNASSERTED.
WRITE CONTROL EQUALS CS ASSERTED AND
WLB ASSERTED AND AO UNASSERTED.

158

DC319·AA DLART
AC Characteristics
(TA = OOC to 70°C, Vee = 5.0 V ± 5%, GND = 0 V)
Symbol

Parameter

Min.

Tcyc

Cycle time

400ns

Tpw

Controlling
puJse width

100 ns

Tas

Address setuptime

50ns

Tah

Address hold
time

Ons

Tac

Access time

Ons

250 ns

Tlr

Tristate time

10 ns

50ns

Tds

Data set-up
time

100 ns

Tdh

Data hold
time

Ons

Max.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias
Storage Temperature
Voltage On Any Pin
With Respect To Ground -0.5 V to *min7 V
Power Dissipation

* Stresses above those listed under "Absolute Maximum Ratings" may

cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

159

DCK11-AA,-AC
DCK11-AA, -AC PROGRAM TRANSFER INTERFACE
INTRODUCTION
The DCK11-AA and -AC CHIPKITs provide the logic necessary for a
program transfer interface to the LSI-11 bus.
The DCK11-AA kit contains:
1-DC003 Interrupt Chip
1-DC004 Protocol Chip
4-DCOOS Transceiver/Address Decoder/Vector Select Chips
The DCK11-AC kit contains the above chips plus:
1-W9S12 double-height, extended-length, high-density wire-wrappable module
1-BC07D-10 ten-foot, 40-conductor plug-in cable
Figure 1 shows a schematic of the program control CHIPKIT part of a
user's interface.
FEATURES
DC003 Interrupt Logic IC Features
• Two interrupts (A & B) per DC003
• Interrupt enable flip-flop on the IC
• Enable flip-flop outputs available to the user
• Interrupts initially disabled by BUS INIT
• VECTOR output to the DCOOSs to gate the Interrupt Vector address
directly onto the LSI-11 bus
• Interrupt B generates the second LSB of vector address directly
(VECRQST B H)
• BUS INIT buffered and made available to the user (INITO L)
• Contains logic for LSI-11 bus "daisy-chained" interrupts
DC004 Protocol Logic IC Features
• Device selection features
Four register select lines (SEL 6 L, SEL 4 L, SEL 2 L, SEL 0 L)
High and low byte output select lines (OUTHB L, OUTLB L)
Input select line (INWD L)
Enable input from higher level decode (ENB H)
• Bus functions
Bus reply generated for device addresses and for interrupts
(BRPLY L)
Ability to vary bus reply response by adding an RC network
provided (RXCX H)
160

DCK11-AA,-AC
DCOOS Bus Transceiver Ie Features

• Four bits per IC
• Three bits of address selection logic included on the chip
• LSi-11 bus drivers and receivers
Drivers-open collector with 70 mA sink capability
Receiver-65 IlA input loading (BUS 0-3L)
• Internal 3-state bus drivers and receivers
Drivers-20 mA sink
Receivers-standard TTL (OAT 0-3 H)
• Address selection
Enable input for use with a higher level decoded input (MENB L)
Address bits may be excluded from comparison by tying them
to VCC (JA(3:1 )L)
• Interrupt Vector
Vector address bits "ORed" directly onto LSI-11 bus (JV(3:1 )H)

SPECIFICATIONS
For complete Electrical Specifications refer to EJ 17475. A summary of
the more important specifications follow the pin/signal descriptions
for individuallCs.
DC003Pin/Signal Descriptions
Pin

Signal

Description

VECTORH

Interrupt Vector Gating. This signal should
be used to gate the appropriate vector address onto the bus and to form the bus signal called BRPLY L. Type: TTL-OUTPUT

VECRQSTB H

Vector Request "B." When asserted, indicates RQST "B" service vector address is
required. When unasserted, indicates
RQST "A" service vector address is required. VECTOR H is the gating signal for
the entire vector address; VECRQSTB H is
normally bit 2 of the vector address. Type:
TTL-OUTPUT

161

DCK11-AA, -AC
DCOO3 Pin/Signal Descriptions (Cont)
Pin

Signal

Description

BDIN L

Bus Data In. This signal, generated by the
processor BDIN, always precedes a BIAK
signal. Type: BUS-INPUT

INITOL

Initialize Out. This is the buffered BINIT L
signal used in the device interface for general initialization. Type: OPEN COLLECTOR
WITH 1K PULL UP - OUTPUT

BINITL

Bus Initialize. When asserted, this signal
brings all driven lines to their unasserted
state (except INITO L). Type: BUS-INPUT

BIAKO L

Bus Interrupt Acknowledge (Out). This signal is the daisy-chained signal that is
passed by all devices not requesting interrupt service (see BIAKI L). Once passed by
a device, it must remain passed until a new
BIAKI L is generated. Type: BUS-OUTPUT

BIAKI L

Bus Interrupt Acknowledge (In). This signal
is the processor's response to BIRO L true.
This signal is daisy-chained such that the
first requesting device blocks the signal
propagation while non-requesting devices
pass the signal on as BIAKO L to the next
device in the chain. The leading edge of
BIAKI L causes BIRO L to be unasserted by
the requesting device.
Type: BUS-INPUT

BIRO L

Bus Interrupt Request. This signal is generated when this device needs to interrupt the
processor. The request is generated by a
false to true transition of the ROST signal
along with the associated true interrupt enable signal. The request is removed after
the acceptance of the BDIN L signal and on
the leading edge of the BIAKI L signal or the
removal of the associated request signal.
Type: BUS-OUTPUT
162

DCK11-AA, -AC
DC003 Pin/Signal Descriptions (Cont)
Pin

Signal

Description

10
17

ROSTB H
ROSTAH

Device Interrupt Request. When asserted
with the enable flip-flop set, will cause the
assertion of BIRO l on the bus. This signal
line normally remains asserted until the request is serviced. Type: BUS-INPUT

ENBST H
ENASTH

Interrupt Enable Status. This signal indicates the state of the interrupt enable internal flip-flop which is controlled by the signal
ENX (where X is either A or B) DATA H, and
the ENX (where X is either A or B) ClK H
clock line. Type: TTL-OUTPUT

12
15

ENBDATAH
ENADATA H

Interrupt Enable Data. The level on this line,
in conjunction with the ENX (where X is either A or B) ClK H signal, determines the
state of the internal interrupt enable flipflop. The output of this flip-flop is monitored
by the ENX (where X is either A or B) ST H
signal.Type: TTL-INPUT

13
14

ENBClK H
ENAClK H

Interrupt Enable Clock. When asserted (on
the positive edge), interrupt enable flip-flop
assumes the state of the ENX (where X is
either A or B) DATA H, signal line. Type:
TTL-INPUT

Summary of Electrical Specifications for DC003
Ambient Temperatures
O°C to 70°C
TTL Input
High-level input current

50 p.A max.
IIH(V=2.7V)

Low-level input current
l,d V ,=0.5V)

-.55 rnA max.

Exceptions

Pins 12 & 15 ENX DATA H
IIH = 100 p.A max.
IlL = -2.0 rnA max.

163

DCK11-AA, -AC
TTL Outputs
High-level output voltage
V OH (10 = -1 mA max.)

2.7V min.
0.5V max.

Low-level output voltage
V OL (10= 20 mA max.)

Bus (Hi Z) input and (open collector) outputs.
Bus Inputs
High-level input current
I IH (V I = 3.BV)

40,uA max.
-10,uA max.

Low-level input current
IlL (V 1= OV)
Bus Outputs
Low-level output voltage
V LO (I sink = 70 mA max.)

O.BV max.

DC004 Pin/Signal Descriptions
Pin

Signal

Description

VECTOR H

Vector. This input causes BRPL Y L to be
generated through the delay circuit. Independent of BSYNC Land ENB H. Type:
TTL-INPUT

2
3
4

BDAL2 L
BDAL 1 L
BDALO L

Bus Data Address Lines. These signals are
latched at the assert edge of BSYNC L.
Lines 2 and 1 are decoded for the select
outputs; line 0 is used for byte selection.
Type: BUS-INPUTS

BWTBT L

Bus Write/Byte. While the BDOUT L input is
asserted, this signal indicates a byte or
word operation: asserted = byte, unasserted = word. Decoded with BDOUT Land
latched BDALO L to form OUTLB Land
OUTHB L. Type: BUS-INPUT

164

DCK11-AA, -AC
DC004 Pin/Signal Descriptions (Cont)
Pin

Signal

Description

BSYNC L

Bus Synchronize. At the assert edge of this
signal, address information is trapped in
four latches. While unasserted, disables all
outputs except the vector term of BRPL Y L.
Type: BUS-INPUT

BDIN L

Bus Data In. This is a strobing signal to effect a data input transaction. Generates
INWD Land BRPL Y L through the delay circuit and INWD L. Type: BUS-INPUT

BRPLY L

Bus Reply. This signal is generated through
an RC delay by VECTOR H, or BDIN L, or
BDOUT L and the AND of BSYNC Land
latched ENB H. Type: BUS-OUTPUT

BDOUT L

Bus Data Out. This is a strobing signal to
effect a data output transaction. Decoded
with BWTBT Land BDALO to form OUTLB L
and OUTHB L. Generates BRPL Y L through
the delay circuit. Type: BUS-INPUT

INWDL

In Word. Used to gate (read) data from a
selected register onto the data bus. Enabled by BSYNC L and strobed by BDIN L.
Type: TTL-OUTPUT

OUTLB L
OUTHB L

Out Low Byte. Out High Byte. Used to load
(write) data into the lower, higher, or both
bytes of a selected register. Enabled by
BSYNC L and decode of BWTBT Land
latched BDALO L, and strobed by BDOUT L.
Type: TTL-OUTPUT

14
15
16
17

SELO L
SEL2 L
SEL4 L
SEL6 L

Select Lines. One of these four signals is
true as a function of BDAL2 Land BDAL 1 L
if EN B H is asserted at the asserted edge of
BSYNC L. They indicate that a word register
has been selected for a data transaction.
These signals never become asserted except at the assertion of BSYNC L (then only

165

DCK11-AA, -AC
DC004 Pin/Signal Descriptions (Cont)
Pin

Signal

Description
if ENB H is asserted at that time) and once
asserted, are not unasserted until BSYNC L
becomes unasserted. Type: TTL-OUTPUT

RXCXH

External Resistor Capacitor Node. This
node is provided to vary the delay between
the BOIN L, BOOUT L, or VECTOR H inputs
and BRPLY L output. The external resistor
should be tied to Vee and the capacitor to
ground. As an output, it is the logical inversion of BRPLY L. Type: OPEN-COLLECTOR OUTPUT

ENBH

Enable. This signal is latched at the asserted edge of BSYNC L and is used to enable
the select outputs and the address term of
BRPLY L. Type: TTL-INPUT WITH 8501'2
PULL UP

Summary of Electrical Specifications for DCOO4
Ambient Temperatures

TTL Inputs
High level input current
I IH (V I = 2.7V)

50 p.A max.

Low level input current
I IL (V I = 0.5V)

-.70 mA max.

Exceptions

Pin 19 ENB H
IIH = -3.85 mA max.
IlL = -8.0 mA max.

TTL Outputs
High Level output voltage
V OH (I 0 = -1 mAl

2.7V min.

Low level output voltage
V OL (I 0 = 20 mAl

0.5V max.

Bus (Hi- Z) Inputs and (Open Collector) Outputs
Bus inputs

166

DCK11-AA, -AC
High level input current
I IH (V I = 3.8V)

40f..lA max.

Low level input current
III (V I = OV)

-10 J!A max .

Bus Outputs
Low level output voltage
V LO (I sink = 70 mA)

0.8V max.

......

DC005 Pin/Signal Descriptions
Pin

Signal

Description

12
11
9
8

BUS(3:0) L
BUSOL
BUS1L
BUS2L
BUS3L

Bus Data. This set of four lines constitutes
the bus side of the transceiver. Open collector outputs; high-impedance inputs. Low=
1. Type: BUS-INPUT/OUTPUT

DAT(3:0) H
DATOH
DAT1 H
DAT2H
DAT3H

14
15
16

JV(3:1) H
JV1 H
JV2 H
JV3 H

Vector Jumpers. These inputs, with internal
pull-down resistors, directly drive BUS
(3:1). A low or open on the jumper pin will
cause an open condition on the corresponding bus pin if XMIT H is low. A high will
cause a one (low) to be transmitted on the
bus pin. Note that BUSO L is not controlled
by any jumper input. TYPE: TTL-INPUT
WITH PULL DOWN

MENBL

Match Enable. A low on this line will enable
the Match output. A high will force MATCH
low, overriding the MATCH circuit. TYPE:
BUS-INPUT

18
17
7

Peripheral Device Data. These four tri-state
lines carry the inverted received data from
BUS (3:0) when the transceiver is in the receive mode. When in transmit data mode,
the data carried on these lines are passed
inverted to BUS (3:0). When in the disabled
mode, these lines go open (HI-Z). High = 1.
Type: TTL-INPUTS

167

DCK11-AA, -AC
DC005 Pin/Signal Descriptions (Cont)
Pin

Signal

Descriptions

MATCH H

Address Match. When BUS (3:1) match with
the state of JA (3:1) and MENB L is low, this
output is open; otherwise it is low. TYPE:
BUS-OUTPUT

JA(3:1) L
JA1 L
JA2 L
JA3 L

Address Jumpers. A strap to ground on
these inputs will allow a match to occur with
a 1 (low) on the corresponding BUS line; an
open will allow a match with a 0 (high); a
strap to Vee will disconnect the corresponding address bit from the comparison.
TYPE: TERNARY-INPUT (SEE TEXT)

5
4

XMITH
RECH

Control Inputs. These lines control the operation of the transceiver as follows:

REC

o
o
1
1

XMIT

o
1

DISABLE:BUS,DAT open
XMIT DATA:DAT~BUS
RECEIVE:BUS~DAT
RECEIVE:BUS~DAT

To avoid 3-state signal overlap conditions,
an internal circuit delays the change of
modes between XMIT DATA and RECEIVE
mode and delays 3-state drivers on the DAT
lines from enabling. This action is independent of the DISABLE mode.

Summary of Electrical Specifications for DC005
Ambient Temperatures
OCC to 70 c C
TTL Inputs
High level input current
I IH (V I = 2.7V)
REC H Pin 4

100}.LA max.

XMIT H Pin 5

50}.LA max.

Low level input current
I IL (V I = 0.5V)

168

DCK11-AA, -AC
REC H Pin 4

-2.2 mA max.

XMIT H Pin 5

-1.1 mA max.

TTL Outputs
High Level output voltage V OH (10 = -1
MA)
Low level output voltage V OL (I 0 = 20 mA)

3.65V min.

0.5V max.

Bus (Hi-Z) Inputs and (Open Collector) Outputs
Bus inputs
High level input current 65I-LA max.
IIH (V I = 3.8V)
Low level input current

-10 I-LA max.

IlL (V I = 0.5V)

Bus Outputs
Low level output voltage V LO (I sink = 70
mA)

O.BV max.

DESCRIPTION
PROGRAM CONTROL CHIPKIT APPLICATION
In Figure 1, the transceivers (four DC005s) provide data lines DO
through D15 to reflect the state of the bus lines BDAL 0-15, when REC
H is asserted, and to drive the BDAL lines when XMIT is asserted.
Address and interrupt vector information for interrupt request and
device selection is also provided by the DC005. The device address is
set up using input lines A3 through A12, while the interrupt vector
address is set up using input lines V3 through VB.
When the address lines (JA inputs on DC005s) match the state of the
associated BDAL lines, the MATCH output will float high such that all
DC005s will let ENB H on the DC004 be asserted, thus enabling the
DC004 to look for proper synchronizing signals from the bus. Once
these synchronizing signals (BDIN, BDOUT, BSYNC, and BWTBT) are
present, the DC004 generates the control signals (INWD, OUTHB,
OUTLB, and SEL 0, 2, 4, 6) for the user's device.
The protocol logic (DC004)"functions as a register selector to provide
169

DCK11-AA, -AC
the signals necessary to control data flow into and out of the user's
registers. When the proper device address has been decoded by the
device address comparator (all DCOOSs), the MATCH outputs let the
ENBH input go high, thus enabling the DC004 protocol logic. Address
bits 001 Hand 002 H are decoded by the protocol logic, producing
one of the SEL outputs, while bit DO and BWTBT are decoded for
output word/byte selection (OUTHB L, OUTLB L). The device select
line (SEL 0, 2, 4, 6) and word/byte select lines (INWD L, OUTHB L,
OUTLB L) are used by the user's logic. Each SEL output is used to
select one of four user's registers, and the word/byte lines are used to
determine the type of transfer (word or byte) to or from these registers.
Either BDIN L or BDOUT L, depending on the type of bus cycle, will
initiate a delay whose value is dependent on the time constant of the
RC network connected to pin RXCX H of the DC004. The end of this
delay will initiate a reply to the CPU indicating that the address has
been received.
The interrupt logic (DC003) performs an interrupt transaction. Two
channels (A and B) are provided for generating two interrupt requests,
with channel A having the highest priority. The interrupt enable flipflop within the interrupt logic must first be set when the user's device is
to interrupt the LSI-11. This is accomplished by asserting (logic H) the
ENX DATA* line and then clocking the enabled flip-flop by asserting
the ENX CLK* line. With the interrupt enable flip-flop set, the user's
device may then make an interrupt request by asserting (logic H)
RQSTX*. When RQST is asserted and the interrupt enable flip-flop is
set, the interrupt logic asserts BIRQ L to the bus which initiates the bus
"handshake" operation. This operation terminates with the generation
of the vector address by the DCOOS under the control of the DC003,
and it's signals VECTOR Hand VECRQSTB H.
The interrupt logic available to the user indicates the status of the
interrupt logic enable flip-flops. Each line is asserted (logic H) when
the appropriate interrupt enable flip-flop is set. These status lines can
function as part of the user's control status register (CSR). The
VECRQSTB H line is asserted (logic H) when the device connected to
channel B has been granted use of the bus for interrupt vector transfer
operation. When VECRQSTB H is unasserted (logic L), the user's device connected to channel A of the interrupt logic has been granted
use of the bus. The INITO L output from the interrupt logic can be used
to initialize the user's logic.
* X may be either A or B depending on which half of the interrupt logic is being

enabled.

170

DCK11-AA, -AC

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Figure 1

DCK11 Bus Interface Typical Application
171

DCK11-AA, -AC
DC0031nterrupt Logic
The interrupt chip is an 1B-pin, 0.762 cm center x 2.349 cm long (max)
(0.3 in center X 0.925 in long) dual-in-line-package (DIP) device that
provides the circuits to perform an interrupt transaction in a computer
system that uses a daisy-chain type of arbitration scheme. The device
is used in peripheral interfaces to provide two interrupt channels labeled "A" and "8," with the A section at a higher priority than the 8
section. 8us signals use high-impedance input circuits or high-current
open collector outputs, which allow the device to directly attach to the
computer system bus. Maximum current required from the Vee supply is 140 mAo

Figure 2 is a simplified logic diagram of the DC003 IC.

- - - - - - - - - - - - ( N " 5 T 1-1

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BOI ... L:3
INITO L

BINH L
BIAIt'O L
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DC003 Simplified Logic Diagram
172

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DCK11-AA, -AC
DC004 Protocol Logic
The protocol chip is in a 20-pin 0.762 cm center X 2.74 cm long (0.3 in.
center X 1.08 in. long) DIP device that functions as a register selector,
providing the signals to control the data flow into and out of up to four
word registers (eight bytes). Bus signals can directly attach to the
device because receivers and drivers are provided on the Chip. However, the DC004 is now ordinarily used with the user's three-state bus
to limit Bus loading. An RC delay circuit is provided to slow the response of the peripheral interface to data transfer requests. The circuit is designed such that if tight tolerance is not required, then only an
external 1K ±20 percent resistor is necessary. External RCs can be
added to vary the delay. Maximum current required from the Vee
supply is 120 mAo
Figure 3 is a simplified logic diagram of the DC004IC.
NOTE
The pin names shown in this diagram are for the
situation where the DC004 is connected to the internal 3-state bus of the DC005s, not connected directly
to the LSI-11 bus.
VECTOR H

BOAl2 L
BOAll L
BOALO L

ENS H

ENS H
85THC L

03
BOAl2 L

SEL 6 L

DECODER
SEL 4 L

BOAll L

SEL 2 l

-SEL C L

r---'-~:>--------il>----OUT Mel

SOALD L

*-------i-~.r---t_::Jlc>_--- OuT LSl
aWTST L

_ _ _ RXCXH

i
SOOUT L

BOIN L

SRPL'T

--{::>----{>~--t:::==::=D~---------- IOWO L

VECTOR H - - - - - - -

Figure 3

DC004 Simplified Logic Diagram
173

DCK11-AA, -AC
DeDDS Transceiver Logic
The 4-bit transceiver is a 20-pin, 0.762 cm center X 2.74 cm long (0.3
in. center X 1.08 in. long) DIP, low-power Schottky device; its primary
use is in peripheral device interfaces to function as a bidirectional
buffer between a data bus and peripheral device logic bus. It also
includes a comparison circuit for device address selection and a
constant generator for interrupt vector address generation. The bus
I/O port provides high-impedance inputs and high drive (70 mA) open
collector outputs to allow direct connection to a computer data bus
structure. On the peripheral device side, a bidirectional port is also
provided, with standard TTL inputs and 20 mA, tri-state drivers. Data
on this port are the logical inversion of the data on the bus side.
Three address "jumper" inputs are used to compare against three bus
inputs to generate the signal MATCH. The MATCH output is open
collector, which allows the output of several transceivers to be wireANDed to form a composite address match signal. The address jumpers can also be put into a third logical state that disables jumpers for
"don't care" address bits. In addition to the three address jumper
inputs, a fourth high-impedance input line is used to enable/disable
the MATCH output.
Three vector jumper inputs are used to generate a constant that can
be passed to the computer bus. The three inputs directly drive three of
the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three optional states: receive
data, transmit data, and disable.
Maximum current required from the V cc supply is 120 mAo
Figure 4 is a simplified logic diagram of the DCOOS IC.

174

DCK11-AA, -AC
JAl L

Vee

JA2 l

JA3 L

MATCH H 3

18 DATO H

REC H

17 OATl H

XMIT H

OAT2 H

BUSO

DeDas

JV3 H

:LJ;:~~~:

BUS3 l

'-3

BUSZ l

MENS l
BUSO L

GND

BUSl L

Jf>------+------1I

DATO

~----------------------t<:J===r=f===t~JVl
;'--'--t---,- DA T1

BUS'

H
H

JAl

~--------------+-------~

.........,~--=----+-,.---

JV2

>--'---t---,r DAT2

BUS2

JA2

~------------~+-------+<=r===r=t===i~JV3
>--'--+-r DA T3

BUS3

H
H

JA3

_____J::=:=t--r-t-------j-

MENS

XMIT

H -,-----------i~

REe

H ---,-~-

MATCH

-----"T)J
Ie DeD05

Figure 4

DCDD5 Simplified Logic Diagram

CONFIGURATION
The drawings on the following pages show sample circuits that may be
helpful in applying the CHIPKITS.

175

DCK11-AA, -AC
OUTPUT
REGISTER

INTERNAL
)-STATE

OUT

USER

DC005'S
(BUS
TRANSCEIVERS)

OPTIONAL
INPUT
REGISTER
,-- - - -- -

INPUT
()-STATE
DRIVERS)

I
I

' - - - - - -....., Q

.,
I
I

D~ USER

L ____ -1

Figure 5

Data Path Flow Diagram

OUTPUT REGISTER HIGH BYTE
)-STATE
DRIVERS

FROM OC005'S

HIGH OROER BITS

- t-- c

TO USER

74 LS374

-=-

(OU

FROM
DC004 .

THB
S£LX

L
L

WRITE OUTPUT
74LS02
REGISTER
) - - HIGH BYTE

OUTPUT REGISTER LOW BYTE
3-STATE
DRIVERS

8
FROM OC005'S _--I-_--I---l D
LON ORDER BITS

Qf----IL

>--+---,1--_ TO UseR

--C

74LS374

FROM OUlLB
OCOO4
SELX

74 LS02
WRITE OUTPUT
L
) - - REGISTER
L --a..--,
HIGH BYTE

Figure 6

Example of Output Register

176

DCK11-AA, -AC
LOW BYTE

'-STATE

DRIVERS

•

TO Devos

INTERNAL BUS
(LOW ORDER
8 BITS)

FROM
De004

]~
"-

Figure 7

to--

FROM
USER
STROBE
FROM
USER

74 LS374
READ DATA
lOW BYTE L

INWD L
SELX l

Example of Input Register (BYTE)

LOW BYTE REGISTER

3-STATE
DRIVERS
Q

,,~

FROM
USER

74LS374
TO DeOOS
INTERNAL
BUS
HIGH BYTE REGISTER

3-STATE
DRIVERS
Q

FROM
USER

le
STROBE
FROM
USER
74 LS374
74LS32
FROM (INWD L
DC004 SELX L

=rJ

Figure 8

READ DATA
WORD L

Example of Input Register (WORD)
177

DCK11-AA, -AC
This example is the interrupt enable bit for interrupt A which connects
to bit 6 of the example CSA.

0(005

3-STATE
DRIVER

0(003

74LS367
INTERNAL 3-STATE
BUS

I6
ENAST Hi-c:...-- - - - - - - 1

OAT 6
BDAL6 L

BUS
TRAN(EIVER
INTERRUPT
LOGI(

FROM (

0(004

LSI -11
BUS

(SR
READ
b - - - - - ' ENABLE L

SELO L
INWD l

74LS32

Figure 9

Typical CSR Bit

74lS367

INTr3~~~;
BUS

r:
i--t--<

0(005

f-----RQST INT A H
DATA BITS

15,12,11,&14
XMIT H

5 - - I - < h:-----, THESE BITS ARE
NOT USED so
i-"--~ THEY READ 0

0(005
DATA BITS

' 10 ,9,8, & 13

(SR

SEL 0 L

---c:r-'tr_--' READ l

XMIT H

INWD L--~

0(005
0(004

DATA BITS
7,6,5,0

74lS04

>-_-.,-___----'X=M:!!-IT'----+----1 XMIT H
74LS08
GMIT

SEL 0 l - - - - 1
I(SR REGISTER SELE(T
~ROM 0(004)

0(005
DATA BITS
4,3,2, I

XMIT H

WHEN THE CSR IS READ (SEL 0 L = 0) THE SIGNAL
GMIT WILL BE 0 CAUSING THE UNUSED DC005
BITS TO BE READ AS ZEROS. (HIGH ON BDAL LINES)
FOR ANY OTHER REGISTER GMIT = XMIT.
Figure 10

Sample Circuit to Cause Unused CSR Bits to be Read as
Zeros
178

DCK11-AA, -AC
This example is the A interrupt request and a DATA READY status bit
(bit 7 of the CSR).
TO DATA

LSI-ll
BUS

r-REGISTER
ClOCK INPUT
S

74LS7401 _ _-+-_---1R<~DC=OO"'-31
RQSTA

BlRQ l

74lS32
SEl2 l
INWD l ---<----.../

READ DATA
REGISTER L
(RDR II

BIAKI l

741508

(RDIH + INiT II

BIAKO l
INITO l
INTERRUPT LOGIC
3-STATE
DRIVERS

DATA 7

'>---- (CSR DATA READY Bm
74L5367

74 LS 32

SElO L~E-=:.L_---,

INWDL~

Figure 11

ITO INTERNAL 3-STATE
BUS BIT 71

Typical Interrupt Request

BUS REPLY DELAY TIMES
Bus Reply delays as a function of RC values connected to pin 18
(RXCX H) of the DC004.

k1. RX = 1KQ 5%
CX = 0
Delay'" 50 ns from falling edge of BDIN L, or BDOUT L, or rising
edge of VECTOR H to BRPL Y L falling edge.
2.

RX = 1KQ5%
CX = 470 pf5%
Delay as described in item 1 above", 200 ns.

RX = 10KQ 5%
CX = 1000 pf 5%
Delay as described above", 3.2 ,usec
BDIN L

BDOUT

~'--_----'

r---l,1'--_ __

VEcrOR
H
,,-,-,-~I

-----:I 8

~'-_ __

BRPLY L

WHERE6 = DELAY DESCRIBED IN ITEMS 1-3
Figure 12
179

DCK11-AB, -AD
DCK11-AB, -AD DIRECT MEMORY ACCESS INTERFACE
INTRODUCTION
The DCK11-AB and -AD CHIPKITs provide the logic necessary for a
Direct Memory Access (DMA) interface to the LSI-11 bus.
The DCK11-AB kit contains:

1-DC003lnterrupt Chip
1-DC004 Protocol Chip
4-DC005 Transceiver/Address Decoder/Vector Select Chips
2-DC006 Word Count/Bus Address Chips
1-DC010 DMA Control Chip
The DCK11-AD kit contains the above chips plus:
1-W9512 double-height, extended-length, high-density wire-wrappable module
1-BC07D-10 ten-foot, 40-conductor plug-in cable

Figure 1 shows a typical interconnection of DMA CHIPKIT components, in block diagram form.
DMA applications use the same chips as program control interfaces,
plus two DC006s for word or byte address counters and a DC010 DMA
bus control IC.
DC006 Word and Address Counter IC Features

• Two 8-bit counters on each IC
• 16-bit address and word counters available in two ICs cascaded
• Input and output share pins on the 3-state bus
• Read and write control logic located on the IC
• Maximum count decoded and brought out for user
DC010 DMA Logic Features

• Uses an external 8 MHz clock to generate LSI-11 bus signals for
DIN, DOUT, SYNC, and SACK
• Inputs allow selection of cycle type (DATI, DATO, DATIO)
• Interfaces with DMA daisy-chain signals
• Allows an external RC network to force a variable wait before the
next bus request is made (TMOUT H)
• An input which allows a maximum of four transfers before the bus is
released, when enabled (CNT 4 H)

180

DCK11-AB, -AD
SPECIFICATIONS
This section contains a summary of the most important specifications
for DC006 and DC010. See the previous section DCK11-AA, -AC for a
summary of specifications for DC003, DC004, and DeDDS.

DCDD6 Pin/Signal Descriptions
Pin

Signal

Description

CNT1A

Count A Counter by 1 (TTL Input). This signal controls the
least significant bit of the A
counter. When CNT1 A is low,
the A counter increments by
one. When high, the LSB is
prevented from toggling,
hence the counter increments
by two. When two counters are
cascaded, CNT1A on the highorder counter should be
grounded.

CLK-A

Clock A Counter (TTL Input).
This clock signal increments
the A counter on its negative
edge. The counter is incremented by one or two, depending on CNT1 A. CNT1 A
and LD must be stable while
CLK-A is high.

CLK-C

Clock C Counter (TTL Input).
This clock signal increments
the C counter by one on its negative edge. LD must be stable
while CLK-C is high.

S-A

Select A Counter (TTL Input).
This signal allows the selection
of the A counter according to
the truth tables.
181

DCK11-AB, -AD
DC006 Pin/Signal Descriptions (Cont)
Pin

Signal

Description

S-C

Select C Counter (TTL Input).
This signal allows the selection
of the A counter according to
the truth tables.

RD-A

Read A Counter (TTLInput).
This signal allows the selection
of the A counter according to
the truth tables.

RD-

Read (TTL Input). This signal
allows the read operation to
take place according to the
truth tables.

Load (TTL Input). When this
signal goes through a high-tolow transition, the load operation is allowed to take place
according to the truth tables.
No data changes permitted
while LD is low.

7-9

D/F (7:0)
11-15

Data Bus (Bidirectional, 3State Outputs/TTL Inputs).
These eight bidirectional lines
are used to carry data in and
out of the selected counter.

MAX-A

Maximum A Count(TTL Output). This signal is generated
by ANDing CLK-A and the
maximum count condition of
counter A (count 376 when
counting by 2 or count 377
when counting by 1).

MAX-C

Maximum C Count (TTL Output). This signal is generated
by ANDing CLK-C and the
maximum count conditions of
counter C (count 377).
182

DCK11-AB, -AD
Summary of Electrical Specifications for DC006
Ambient Temperatures
0 0 to 70 0
TTL Inputs
High level input current
IIH (V 1= 2.7V)
551lA max.
Low level input current
IlL (V I = 0.5V)

-1.7 rnA max.

TTL Outputs
High level output voltage V OH (I 0 = -1
rnA)

2.7V min.

0.5V max.

Low level output voltage V OL (10 = 20 rnA)

DC010 Pin/Signal Descriptions
Pin

Signal

Description

REOH

Request (TTL Input). A high on
this signal initiates the bus request transaction. A low allows
the termination of bus mastership to take place.

BDMGI L

DMA Grant Input (Hi-Z Input).
A low on this signal allows bus
mastership to be established if
a bus request was pending
(REO = high); otherwise, this
signal is delayed and output as
BDMGO L.

CNT4H

Count Four Input (TTL Input).
A high on this signal allows a
maximum of four transf-ers to
take place before giving up
bus mastership. A low disables this feature and an unlimited transfer will take place
as long as REO is high. If left
open, this pin will assume a
high state.
183

DCK11-AB, -AD
DC010 Pin/Signal Descriptions (Cont)
Pin

Signal

Description

TMOUT H

Time-Out (TTL Input/Open
Collector Output). This 110 pin
is low while MASTER ENA is
high. It goes into high impedence when MASTER ENA
is low. When driven low it prevents the assertion of BDMR;
when driven high it allows the
assertion of BDMR to take
place if BDMR has been negated due to the 4-maximum
transfer condition. An RC network may be used on this pin
to delay the assertion of
BDMR.

DATIN L

Data In (TTL Input). This signal
allows the selection of the type
of transfers to take place according to the truth table.

DATIO L

Data IN/Out (TTL Input). This
signal allows the selection of
the type of transfer to take
place according to the truth table. During a DATIO transfer,
this signal must be toggled in
order to allow the com pletion
of the output portion of the 110
transfer.
If left open, this pin will assume a high state.

RSYNC H

Receive Synchronize (TTL Input). This signal allows the device to become master
according to the following relationship:
184

DCK11-AA, -AC
DC010 Pin/Signal Descriptions (Cont)
Pin

Signal

Description
RSYNC L . RPL Y
H· MASTER
ENA = MASTER

CLKL

Clock (TTL Input). This clock
sig nal used to generate all
transfer timing sequences.

RPLYH

Reply (TTL Input). This signal
is used to enable or disable
the clock signal. This signal also allows the device to become master according to the
following relationship:
RSYNC L . RPL Y H . MASTER
ENA = MASTER

INITL

Initialize (TTL Input). This signal is used to initialize the chip
to the state where REO is
needed to start a bus reqest
transaction. When INIT is low,
the following signals are negated: BDMR L, MASTER H,
DATEN L, ADREN H, SYNC H,
DIN H, DOUT H.

BDMRL

DMA Request (Open Collector
Output). A low on this signal
indicates that the device is requesting bus mastership. This
output may be tied directly to
the bus.

MASTER H

Master (TTL Output). A high
on this signal indicates that the
device has bus mastership
and a transfer sequence is in
progress.

185

DCK11-AB, -AD
DC010 Pin/Signal Descriptions (Cont)
Pin

Signal

Description

BDMGOL

DMA Grant Output (Open Collector Output). This signal is
the delayed version of BDMGI
if no request is pending; otherwise, it is not asserted. This
output may be tied directly to
the bus.

TSYNC H

Transmit Synchronize (TTL
Output). This signal is asserted by the device to indicate
that a transfer is in progress.

DATEN L

Data Enable (TTL Output).
This signal is asserted to indicate that data may be placed
on the bus.

ADREN H

Address Enable (TTL Output).
This signal is asserted to indicate that an address may be
placed on the bus.

DIN H

Data In (TTL Output). This signal is asserted to indicate that
the bus master device is ready
to accept data.

DOUTH

Data Out (TTL Output). This
signal is asserted to indicate
that the bus master device has
output valid data.

Summary of Electrical Specifications for DC01 0
Ambient Temperatures
O°C to 70°C
TTL Inputs
High level input current
I IH (V I = 2.7V)

300 /.LA max.

186

DCK11-AB, -AD
Low level input current
I IL (V I = 0.5V)

-2.0 mA max.

TTL Outputs
u:"' ..... I -. ... _1
I II~II

_ 1 1 ... _

.....

111..-.1 ...

L.vvvi Viol LtJl.I L VVIL-

2.7Vmin.

age V aH (I a = -1
mA)
Low level output voltage V aL (I a = 8 mA)

0.5Vmax.

Bus (Hi - Z) Inputs and (Open Collector) Outputs
Bus inputs
High level input current 65 J.LA max.
I IH (V I = 3.8V)

Low level input current
I IL (V I = 0.5V)
Bus Outputs
Low level output voltage V La (I sink = 70
mA)

-10 J.LA max.

0.8V max.

DESCRIPTION
DMA CHIPKIT Application
Figure 1 shows how four DG005 transceivers are used to handle the
first 16 BDAL lines (BDAL O-BDAL 15) from the LSI-11 bus and to
provide the interface to the internal 3-state bus. The transceivers are
enabled to receive data from the LSI-11 bus when the REG H line is
driven high. Similarly, the transceivers transmit data to the LSI-11 bus
when the XMIT H line is driven high. Normally, the DC005s are in the
receive state (REG H line asserted) and allow the transceivers to monitor the LSI-11 bus for device addresses.

Device address and vector switch inputs to the transceivers provide
convenient address and vector selection.

187

DCK11-AB, -AD

BDAl12

B
9

BDAll1

BOAl15

Bv2
B52
BR2
BU2
A12
All

BUS 2
BUS 1

BOAL 14

52 2
52 1

BUS 0

V---..l} JA3
1

r;t

.,),.
B
9

BOAl9
BDAL 8
BOAL 13

JV2 15
JVl 14

XMITH~

MATCH H
MEM B L

REC H

r!- i

12
19
2
1

51-8
51 7
51 ·6

--,t
8
9

BOAL 7
BDAL 6
BOALS
BOAL 0

12
19
2
1

51-5
51 4

A7,-A6!::
AS

r -.

51 ·3

t-&-

.,),.

BUS 1
BUS 0

JA3
JA2
JAl

OAT3
7
OAT2
DATl 17
18
DATO
JV3 16

BUS 2

.,),.
BL2
8K2
8J2
AU2

E26

BUS 3

AWl
A9 ~
A8

JV3~

OC005

JA2
JAl

DATAlS
DATA12
DATAll
DATA14

BDAl 10

BP2
BN2
BM2
8T2

6
7
DATl 17
18
DATO

OAT3
DAn

BUS 3

DCOO5
E22

+5V

JV2~~,;!;VB

JVl 14
XMITH ~H
REC H

MATCH H
MEM B L

DAT3 i6

BUS 2
BUS 1
BUS 0

OAT?

DCOO5
E17

I
I

DATA7
OATAS
DATAS
DATAO

17
DATl
18
DATO
JV3 16
JV2 lS
JVl
XMITH ~
AEC H

i
V7
v6
VS

MATCH H
MEMBl

~R9
330
52-8

P-iI '

sus 3

JA3
JA2
JAl

DATA10
OATA9
OATAB
OATA13

t-i-

52-6
52-5

REC H

----.
52-7

XMlT H

8H2
8F2
BE2
AV2

8
9

BOAL2
BDAl1

E30

12
19
2

Sl 2

A'~
A3

]4lS04
RDOUT

BDAl4
BOAL3

51-1
+5V-

t-!-

BB$7L

AP2

BUS 3
BUS 2
BUS 1
BUSO

JA3
JA2
JAl

6
7
17
18
DATO
16
JV3
JV2 '5
JV' ~

DAT3

r,t MATCH H
MEM B L

XMITH

P.-

REC H j-..i..

.......,

--------."-i
52-4
!
52-3

INWO l

10
11

"S
74lS27

EN B H
~
$

SWl8T l

SWTBT L
BSYNC L

9
RSVNC

R6
680

MRPLY L

AK2

6
9 BDOUT l
8 BRPLY L

.~~
13

(;11
74lS86

,L BOIN L

DCOO4
E7

TRPL Y

'3v

RDIN~
~ BOIN L

74lS04

AL2
AT2
AM2
AN2

BIRO l
SINn l
BIAKI L
BrAKO l

7
6

.$~
R3
'$~
Rl
33D
33D

BIRO L
SINIT L
BIAKI l
BIAKO l
DC003

E6
R2
680

Figure 1

DATA2
DATAl

DATl

DCOO5
E,2

R"
680

INWO L
RXCX
SDALD
BOAL1

BOAL2
OUT HB L
OUT lB l
SElO l
SEl2 l
SEL4 l
SEl6 l
VECTOR H

VECTOR H
VECRQSTB H
ENAOATA H
ENBOATA H
ENAClK H
ENBCLK H
ROSTAH
AOSTBH
ENAST H
ENBST H
INITO l

DATA4
OATA3

OAT2

LfR7
330

U~$

•

I,1Cl

3
2
12
13
17
16
1$

-:;r470
PF

,.
1

DUTH8 L
OUTHB l
SELO l
SEL2 L
SEL4 l
SElti L

r?s----

DATA 14

'3
17
'0
16
11

CSAWHB
CSAW L
ROSTA H
ROSTB H
ENAST H
EN8ST H
INIT L

NOTE
A - SWITCHES ARE FOR DEVICE ADDRESS
SELECTION.
V - SWITCHES ARE FOR VECTOR
SE lECTION
CLOSE ION) SWITCH FOR "1"
OPEN JOFF) SWITCH FOR ·'0"

Typical DMA CHIPKIT Application

Switches A3 through A 12 are the device address selection switches
and switches V3 through V8 are for vector selection. Switches are ON
188

DCK11-AB, -AD
(closed) for a 1 bit and are OFF (open) for a 0 bit. The addressable
registers are:

Bank 7
Octal Addi&SS

Bus Address Register

1XXXXO

Word Count Register
Control/Status Register

1XXXX2
1XXXX4

Output Buffers

1XXXX6

The user selects a base address for the bus address register and sets
the device address selection switches to decode this address. The
remaining register addresses are then properly decoded as sequential
addresses beyond the bus address register (Figures 2 and 3).

DECODED BY BBS7

DECODED FOR
1 OF 4
REGISTERS

SELECTED BY SWITCHES

_ _ _ _ _ _~A_ _ _ _ _ _~,~,_ _ _ _ _ _ _ _ _ _ _ _ _ _~A~_ _ _ _ _ _ _ _ _ _ _ _ _ _~\~

All
152-11
A12
152·21

AB
151- 61

A10
(51 -BI

A7
151 -51

151 -71

A3
IS 1-11

151- 31

BYTE
CONTROL

A4
151 ·21

A6
151 41

MA 1009

Figure 2

Device Address Select Format
3RD OCTAL
DIGIT
(0 OR 41
1ST
OCTAL
DIGIT

2ND
OCTAL
DIGIT

PREASSIGNED
AS ZEROS

(S2-7)

(52-51

152 31

(52· BI

152-61

152·41

V2
(NOTEI

NOTES
V2 =

1 FOR TRANSFER COMPLETE INTERRUPT

0 FOR TIME OUT INTERRUPT
MH 1010

Figure 3

Interrupt Vector Select Format

189

DCK11-AB, -AD
The DC004 is the internal register selector. This integrated circuit
monitors BDAl lines 0, 1, and 2 to determine which register address
has been placed on the lSI-11 bus. The states of BDOUT and BDIN
are also monitored to determine the type of transfer (DATO or DATI).
When an address for an internal register is placed on the lSI-11 bus,
one of the SEl outputs from the DC004 is driven low. This selects that
particular register for the transfer (into or out of the master device) is
determined by the state of the OUTHB l, OUTlB l, or INWD l lines.
Internal register selection is summarized as follows:

Control Line

Select

INWD l (Read)
INWD l (Read)
OUTHB l (Write High Byte)
OUTHB l (Write High Byte)
OUTlB l (Write low Byte)
OUTlB l (Write low Byte)
INWD l (Read)

SElO l
SEl2l
SElOl
SEl2 l
SElOl
SEl2l
SEl4 l

OUTHB land MRPl Y l
(Write CSR High Byte)
OUTlB land MRPl Y l
(Write CSR low Byte)
OUTHB land MRPl Y l
(Write High Byte)
OUTlB land MRPl Y l
(Write low Byte)

SEl4l

SEl6 l

Bus Address Register
Word Count Register
Bus Address Register
Word Count Register
Bus Address Register
Word Count Register
Control/Status
Register
Control/Status
Register
Control/Status
Register
Output Buffer

SEl6 l

Output Buffer

SEl4l

Note that MRPl Y l is the BRPl Y l output of the DC004 and is used
along with OUTHB land OUTlB l to write either the high or low byte
in the control/status register or the output buffers. Write byte selection
for the bus address register and the word count register is controlled
only by the OUTHB land OUTlB l lines. Words can be written to the
control/status register or the output buffer registers by driving both
OUTHB land OUTlB l to the low state at the same time.
The DC004 integrated circuit was designed to operate directly from
the lSI-11 bus. However, since the introduction of the DC005, the
DC004 is usually interfaced to the lSI-11 bus through the DC005. Bus
signals (BDAl lines) passing through the DC005 are inverted. Therefore, BDAl 0, 1, and 2 signals applied to the DC004 are inverted.
Because of this inversion, it is necessary to change the nomenclature
190

DCK11-AB, -AD
on pins 12 through 17 on the DC004. The difference in nomenclature
between DC004s operated directly from the LSI-11 bus and through a
DC005 are as follows:
From Bus {Non-Inverted
BDALO,1,2)

From DeOOS (Inverted
BDAL 0,1,2)

Signal

OUTLB L

OUTHB L

OUTLB L

SELOL

SEL6L

SEL2 L

SEL4L

SEL2 L

SEL6 L

SELOL

It is recommended that when a DC005 is used, the DC004 be interfaced to the LSI-11 bus through the DC005 to avoid unnecessary bus
loading.
The DC003 IC performs an interrupt transaction that uses the daisychain type arbitration scheme to assign priorities to peripheral devices. The DC003 has two channels (A and B) for generating two
interrupt requests. Channel A has higher priority than channel B. If a
user's device wants control of the LSI-11 bus, the interrupt enable flipflop within the DC003 must be set. This is accomplished by asserting
(logic 1) the ENX* DATA line to the DC003 (writing bit 14 or bit 6 to a
one) and then clocking the enable flip-flop by asserting (logic 1)
RQST. RQST must be held asserted until the interrupt is serviced.
When the RQST is asserted and the interrupt enable flip-flop is set, the
DCD03 asserts (logic D) BIRQ L, thus making a bus request. When the
request is granted, the processor asserts (logic D) BDIN L. This causes
the DC003 to assert (logic 1) VECTOR H, which is applied to the
DCOD5. VECTOR H at the DC005 causes the device vector to be placed
on the BDAL lines to the processor. Interrupts are produced for bus
time-outs (CSR bits 15 and 14) and at the completion of a block transfer (CSR bits 7 and 6).
* X may be either A or B.

DMA Application
Figure 4 shows the DMA control (DC010), the word count/bus address
registers (both DC006), the output buffers (both 74LS273s), and the
input drivers (74LS367s).

191

DCK11-AB, -AD
The DC010 performs handshaking operations required to request and
gain control of the LSI-11 bus for DMA data transfers. After becoming
bus master, the DC010 produces the signals necessary to perform a
DIN or DOUT bus cycle as specified by the control lines. An 8-MHz
free-running clock is provided by E21. This clock is used by the DC010
to generate all transfer timing sequences. The actual clock frequency
is not critical and can be any frequency up to 8.3' MHz, provided it is
symmetrical. An RC time constant providecrby resistor R14 and capacitor C2 provides a delay for the reassertion-.of BDMR to the LSI-11
bus. This allows other direct memory access devices to obtain the bus
during the time the CNT4 logic releases the bus and re-requests the
bus.
+5V
R9

~~ USER REO L - - - 1 3300
DATA 8

(TOS+INITIH

REOH

+5V

R12

330

AR2 BDMGI L
AS2 BDMGO L
BDMR L
TDOUT H
TDIN
MASTER H
TSYNC
RSYNC
RPLY H

13
8
19
11
5

6
9
7
12
15

Rl0
330

R13

Rll

680

+5V

R8
330
REO H
BDMGIL
BDMGO L
DATIN H ~--+--- DATlflLL
INIT L
DATIOH
8DMR L
CNT4 H
DOUT H
DATIN L H t > : - : ; . - - - - - D A T N L
DINH
CLK H
R14
MASTER H
TMOUTH ~-+---r~--+5 V
lK
ADREN H
TSYNC H
".I' C2
RSYNC H E18
"'" !!lQQpf
RPLY H DCOlO
ADREN H
R15
270
'DISCRETIONARY WIRING
H = 4 XFERS MAX.
L = BURST MODE

Cl
~lBOpf

Figure 4

Typical Application (DC006, DC010, Output Delay, and
Input Drives)
(Sheet 1 of 2)
192

DCK11-AB, -AD

IN 15

IN 14

IN 13

IN 12

E29

DATA15
DATA14
DATA13
DATA12
DATA11
DATAlO
DATA9
DATA8

4riJ

iW
4~
I

IN 1 1

1
DATEX l
13

E29

I
IN 10

DATEX l
12

E29

I
IN9

15
12

IN 7

g~16

Q2~

DATEX l
11

E25

E20. E25. E29

I
vi

~:I~I

D8
OUTl5
12SDfF
QSI
OUT14
D7
64 DfF
07115 : E OUT13
D6
32 DfF
Q6~
D5
OUTl2
16 DfF
Q5
9 K
OUT11
D4
SDfF
iN> OUT 10
D3
4 DfF
D2
OUT9
2DfF
Q1
2 S
D1
OUT8
1 DfF
I
MAX-A f-:.1,.INlTl~ ClR
E28
MAX-C ,lZ.- WCNTO H
74lS273
E27
DCOO6
ClK

E25

I
IN 8

18
17
14
13
8
7
4
3

CHANH;=Il1

15
14
13
12
11
9
S
7

ClKA
~ ClKC
'II-~ CNTIA
OUTHBl- ~ lD
SElOl- ~ S-A
SEl21- ~ SoC
INWDl
~ RD
0"- RD-A

74lS367

DATAl
DATA6
DATA5
DATA4
DATA3
DATA2
DATAl
DATAO

.~~

IN 6

;~-~

IN 5

IiI~

IN 4

IN 3

2 E25

10 E20

2>i~

'i~
"~tE1

Figure 4

+3 V
OUTlB l
SElO l
SEl2 l
ADREN H

~ ClKA
ClKC

~ CNTlA

18
lD
2
SA
19
SoC
L-~ RD
RD-A

15
128 DfF
14
64 DfF
13
32 DfF
12
16 DfF
8 DfF 11
9
4 DfF
8
] DfF
7
1 DfF
MAX A
MAXC f-'-'-

E23
DC006

QS~ OUT7

D8
D7
14
D6
13
D5
8
D4
I
D3
4
D2
3 Dl
INITl~ ClA

OUT6
Q7~
15 Y

Q6~ OUT5
OUT4
Q5~ OUT3

6 EE

Q31

51HH;

OUT]
OUTl

g~~ aUTO

E2'
74lS273
ClK

~-.1 11

CHANlB
5

DATEX l

Typical Applic?tiQn (DC006, DC010, Output Delay, and
InputOrives)
(Sheet 2 of 2)
193

DCK11-AB, -AD
User devices initiate bus requests by driving the set input of the request flip-flop (E10) low. This asserts REO to the DC010 and generates
BDMR L to the LSI-11 bus. When the DC010 becomes bus master, it
asserts ADREN H to the DC006 bus address registers. ADREN H aI-lows the bus address registers to place the address of the slave (memory) onto the internal bus and, via the DCOOS transceivers, onto the
LSI-11 bus. The request flip-flop (E10) remains set until the DC006
word count overfows to zero (WCNTO). WCNTO then resets the request
flip-flop.
Two DC006 word count/bus address register ICs are used to provide
16 bits each of word count and bus address. The least significant bits
of the word count and bus address register and register C is the word
count register. Both registers can be read or written under program
control from the LSI-11 bus. Registers are selected by:
SELOL
INWDL

• Read bus address register

• Write high byte of bus address register

SELOL
OUTHB L

• Write low byte of bus address register

SELOL
OUTLB L
SEL2 L
INWDL

• Read word count register

• Write high byte of word count register

SEL2L
OUTHB L

• Write low byte of word count register

SEL2 L
OUTLB L

The bus address register is incremented by two for word transfers. To
accomplish the increment by two, the CNT1 A input to the most significant DC006 (E23) must be high, and the CNT1A input to the most
significant DC006 (E27) must be grounded. Clocking for DC006 E23 is
provided by the transition of the ADREN H line from the DC01 O. When
bus address register DC006 E23 overflows, MAX-A goes high, thus
clocking the DC006 E27 bus address register.

194

DCK11-AB, -AD
The word count register is incremented by one each time a word is
transferred. Initially, the word count register is loaded under program
control, with the 2's complement of the number of words to be
transferred. As words are transferred, the word count register is incremented toward zero. When DC006 E23 overflows, MAX-C goes high.
MAX-C clocks the DC006 E27 word count register until DC006 E27
overflows. When E27 overflows, WCNTO H is generated; WCNTO H
then resets the request flip-flop (E1 0), thus terminating data transfers.
During DMA data transactions input data from the DATI bus cycle is
placed on the internal 3-state bus via the DC005 transceivers and is
applied to he 74LS273 (E28 and E24) output buffers. These buffers are
then clocked by CHANH8 and CHANL8, thus placing the data on the
16 OUT lines to the user's device.
For output data transfers (DATO), the user's device places data on the
16 IN lines to the 74LS367 3-state drivers. The drivers are enabled by
DATEX L, which is asserted during a DATO cycle. The data passes
through the drivers, is applied to the internal 3-state bus and, via the
DC005 transceivers, to the LSI-11 bus.
Miscellaneous Logic
Miscellaneous logic is shown in Figure 5. This logic includes CSR,
output buffer and input driver control, non-existent address time-out,
DC005 transceiver receive/transmit control, the control/status register
(CSR), additional transceivers (8641 s), and the "8" request flip-flop.
The CSR, output buffers, and input driver control receive INWD L,
OUTH8 L, OUTL8 L, SEL 4 L, SEL 6 L, DATN H, and DIN H. These
signals are gated to produce enable signals for the CSR, the output
buffers, and the input drivers. CSR RD is produced by INWD Land
SEL 4 L to enable the eSR data (DATA 5 through DATA 14) (Figure 5,
sheet 1) to pass through the 74LS367 3-state drivers and onto the LSI11 bus via the DC005 transceivers. OUTH8 L, OUTL8 L, SEL 4 L, and
MRPL Y L produce either CSRWH8 Lor eSRWL8 L for writing bit 6 of
the eSR (74LS74 E10 on Figure 3, sheet 1), or for clocking the "8"
request flip-flop. DATEX L enables the 74LS367 3-state input drivers
(Figure 5, sheet 1) during an "input" cycle. The CHANH8 and CHANLB
signals clock the 74LS273 output buffers during an "output" cycle.
When bytes are transferred, OUTH8 L, MRPLY Land SEL 6l enable
the high byte (CHANH8 l asserted), while OUTlB l, MRPlY and SEl
6 l enable the low byte (CHANl8 l). 80th bytes are simultaneously
transferred (word transfer) when DIN H is negated.

195

DCK11-AB, -AD
The non-existent address time-out provides a 10 Ils time-out in the
event that a non-existent address is requested on the LSI-11 bus during a DMA operation. This prevents hanging-up the LSI-11 bus for periods longer than 10 Ils. When the DC010 becomes bus master, ADREN
H is asserted and cocks the 10 Ils one-shot (E8). Normally RPLY L from
the LSI-11 bus goes low and the one-shot is cleared. However, if RPLY
L is high (no response from slave), the one-shot times out and cocks
the 74LS74 flip-flop (E9). The flip-flop is set, generating (TOS + INIT) L;
this signal is applied to the DC010 (Figure 4, sheet 1) clearing the internal synchronization circuit and releasing the LSI-11 bus. The signal
(TOS + INIT) H resets the request flip-flop (E10). The 74LS74 flip-flop
(E9) can be set and reset with CSRW HB and DATA 15 (CSR bus timeout). This flip-flop is automatically reset during power-up.

r ~O;;U~F;;; ~;:;:~lT-;-IV~ C-;;;;R-;- -

I
I

3
INW~

. , . C-;;;;R~T::;S -;;;1;;;; ..,

I (CSRI READ LOGIC

~
OuTH8 l

MRPLY L

10
11

CSRRD

CSRWHB

OUTLBL

CSRWLB
SEL 4 L

INWD l

OUTHB l
MRPlY L

74LS221

eSR AD
E19,E20
74LS367

-3
10

r8~a=T -;:;-F:;; -

I
I

-l

OATAS 12 0 S a 9
DATIN l

WCNTOL
TO
OA T A 7

12 0

EIO
74LS74
9

RQST B H

CSRWLB

14~~74

I
I

11 C

INIT':

I
I

I
I
I
I _ _ _ _ _INfTl~
L
_____ I _____
CSAWLB

11 C

• SPARES

Figure 5

Typical Application (Miscellaneous Logic)
(Sheet 1 of 3)
196

DCK11-AB, -AD

r - - - - - - - - - - - - - - - - - - - - - - _I
i

I
I

I
I
I

DC005 TRANSCEIVERS RECIXMIT CONTROL

DATN H

ADREN H
TDOUT H

I
I

>-1:..::2_ _ _ REC H

TRPLY H
INWDH

1-------------NON-EXISTENT ADDRESS TIME-OUT

74LS04
CSRWHB

+5V

P
16

INIT H
INIT L

+3V

~6,_ _ _ _ _ _-,
74LS04

R15

1000 pi

15K

(TOS+INIT)H

4
CSRWHB
DATA 15

L ________________

MK-1122

Figure 5

Typical Application (Miscellaneous Logic)
(Sheet 2 of 3)
197

DCK11-AB, -AD

TRPLY
RPLY H

TDIN
RDIN

TSYNC
RSYNC

TDOUT H

8641/E1

MASTER H

DATN H

INWD H

WCNTO L

8641/E2

~---

Figure 5

- - - - - ______ J

Typical Application (Miscellaneous Logic)
(Sheet 3 of 3)
198

DCK11-AB, -AD
The DCOOS transceiver receive/transmit control determines the state
of the DC005 transceivers. Normally, the transceivers are in the
receive state to accept device addresses from the LSI-11 bus. When
REG H is asserted (high), XMIT is negated (low). XMIT is asserted
(high) when transferring data to the LSi-11 bus (TDOUT, DATEN, and
ADREN are high; TRPLY, INWD are low). REG is asserted (high) when
receiving data from the LSI-11 bus (TDOUT, DATEN, and ADREN are
low; TRPLY, INWD are high).
The control/status register (GSR) (Figure 5, sheet 1) has six active bits
and is a read/write register comprised of 74LS367 3-state drivers and
flip-flops which are part of other logic circuits shown in Figure 3, sheet
1 and Figure 5, sheet 2. Figure 6 shows the GSR format.

UNUSED

UNUSED
.13

INTERRUPT
ENABLE
FOR BIT 15

BUS TIME-OUT
(NON-EXISTENT
ADDRESS)

USER
TRANSFER
REQUEST

INTERRUPT
ENABLE
FOR BIT 7

BLOCK TRANSFER
COMPLETE
(WORD COUNT
OVERFLOW)

TRANSFER DIRECTION
SELECT BIT
DATa/DATI
1/0

Figure 6

Control/Status Register (CSR) Format

The quad transceivers (8641) shown in Figure 3,sheet 3 supplement
the DCDDS transceivers for interfacing to the LSI-11 bus. In this particular application, the 8641s are permanently enabled by grounding
pins 7 and 9.
199

DCK11-AB, -AD
CSR Bit Descriptions

Name
Unused

Description

DATO/DATI

When set to a 1, indicates a
DATO cycle; when set to a 0,
indicates DATI bus cycle.

Interrupt enable
for bit 7

This bit must be set (1) to enable the word count overflow
interrupt at the end of a block
transfer. When set to 0, the interrupt is inhibited.

Block transfer
complete

This bit sets (1) when the word
count register overflows, providing bit 06 is set.

User transfer
request

The user's device must set (1)
this bit to make a bus request
and transfer data. User REO L
(J1-PP) must be driven low (0)
to set bit 08. This bit is always
read as a zero. This is an example for test purposes.

09
10
11

Unused

Bit
00
01

02
03
04

12
13
14

Interrupt enable
for bit 15

Bus time-out

This bit must be set (1) to
enable the bus time-out interrupt. When set to a 0, the interrupt is inhibited.
This bit sets (1) when a slave
on the LSI-11 bus does not respond with BRPLY within 10 IlS
after being addressed. Bit 14
must be set (1) to enable the
bus time-out interrupt.

200

DCK11-AB, -AD

CNT1A

CLK-A

WRITE
CONTROL
LOGIC

S-A

SoC
READ
CONTROL
LOGiC
RD-A
RD

Figure 7

DC006 Simplified Block Diagram

DCOO6 WORD COUNT/BUS ADDRESS LOGIC
The word count/bus address (WC/BA) chip is a 20-pin, 0.762 cm center
x 2.74 cm long (0.3 in center x 1.08 in long) DIP, low-power Schottky
device. Its primary use is in DMA peripheral device interfaces. This IC
is designed to connect to the 3-state side of the DCOO5 transceiver.
The DCOOO has two 8-bit binary up-counters, one for the word (byte)
count and another for bus address. Two DC006 ICs may be cascaded
to increase register implementation.
The chip is controlled by the address latch protocol chip (DC004), the
DMA chip (DC010), and a minimum of ancillary logic. Both counters
may be cleared simultaneously. Each counter is separately loaded by
LD and the corresponding select line from the protocol chip. Each
counter is incremented separately. The we counter (word byte
counter) is always incremented by one; the A counter (bus address)
may be incremented by one or two for byte or word addressing, respectively.
Data from the De006 Ie is placed on the 3-state bus via internal 3state drivers. Each counter is separately read by RD and the corresponding select line.
201

DCK11-AB, -AD
Figure 7 is a block diagram of the De006 Ie while Figure 8 illustrates a
simplified logic diagram. The De006 pin/signal description is presented in Table 2.
TRUTH TABLES
WHERE

~ TTL LOW

L
H

~ HIGH IMPEDANCE
~

~ TTL ~IGH

DON'T CARE
HIGH TO LOW TRANSITION

READ CONT RO L
INPUTS
LD - H
RD
L
L
L
L
H
L
L
L
L
H
H
H
H

RD-A
L
L
L
L
L
H
H
H
H
H
H
H
H

OUTPUTS

vec

S-A

SoC

D/F<7.0>

SoC

L
L
H
H

L
H
L
H

CLEAR A&C AND READ C
A<7:0>
C<7:0>
Z

12BD/F

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

CLEAR A&C AND READ A
A<7:0>
A<7:0>
A<7:0>
CLEAR A&C AND READ A
A<7:0>
A<7:0>
A<7'O>

64D/F

MAX-C
CLK-C

2D/F

32D/F
16D/F
8D/F

WRITE CONTROL
INPUTS
RD - A = L, RD = H
LD
j
j
j

x
H
H
H

S-A

SoC

L
L
H
H
L
L
H

L
H
L
H
L
H
L

FUNCTION
·ILLEGAL
LOADA<7:0>
LOADC<7:0>
WClBA NOT SELECTED
CLEAR BOTH COUNTERS
LOADING DISABLED
LOADING DISABLED

·ILLEGAL CONDITION BECAUSE A LOAD OPERATION AND A CLEAR
OPERATION IS ATTEMPTED SIMULTANEOUSLY. RESULT OF THIS
OPERATION IS TO CLEAR BOTH COUNTERS,

C:l' : :

:_r-_______________--d:~~~Al t:lA
HMAXA

MAX A H

OF7
1071

04 I

S·C

l-:-r---------r-<:r,

~ :

.---------lCLR H

A COUNTER 07
8 BIT BINARY

S·A l-:-r--------t-'-r-----i-.q--."

~~7H

i
i

A7 H

i:C6H

DF6l4-h~

i'.' .: A6 H

UP COUNTER

'280 F H

640 F H

J..

[,F

320 F 1-4

RD l

AD·A H
Bo F H

40 F" H

C COUNTER

20 F H

8 BIT BINARY

UP COUNTER

Loe H

02 I
03 I

H-,-------------f-------QClKC l

lOl-:-,--------t------~cr~
eLK-C

g<! ')
04
I CIO 71
07

10 F H

'----~ClRH

MAXC l f - - - - - - - - - - - - d

o Fro 7!

Figure 8

De006 Simplified Logic Diagram
202

MAX C H

DCK11-AB, -AD
DC010 DIRECT MEMORY ACCESS LOGIC
The Direct Memory Access (DMA) chip is a 20-pin, 0.762 cm center X
2.74 cm long (0.3 in. center X 1.08 in. long) DIP, low-power Schottky
device for primary use in DMA peripheral device interfaces using the
LSI-11 bus.

This device provides the logic to perform the handshaking operations
required to request and to gain control of the system bus. Once bus
mastership has been established, the DC010 generates the required
signals to perform a DATI, DATa, or DATIO transfer as specified by
control lines to the chip. The DC010 IC has a control line that will allow
multiple transfers or only four transfers to take place before giving up
bus mastership.
Figure 9 is a simplified logic diagram of the DC010 IC. The logic symbols and truth table are presented in Figure 10.

(MASTER S"O HI

BOMR L
(MASTER L)

AEO H

(RPLY SO HI

(MASTER ENA)

(NIT L

BDMGO
BOMGI L
lEND Hj
CNT4 H

(MASTER ENA)
TMOUT H

CAT1N l
TSYNC H

DATEN L

DATtO l
(END CYCLE H)
(INIT HI

APLY H

elK l

>-_-+-MASTER H

ENA'==i=~===='=~D

(MASTER
ASYNC H

(END LI--t=========:=t:==---_.-I

Figure 9

DC010 Simplified Logic Diagram
203

DCK11-AB, -AD
REO H

VCC

DAlIO L

INIH

DATI'll L

DATEN L
CLK H

ADREN H

CNT4 H
RPLY H

DINH

TMOUT H
BDMGI L

BDMGO L
MASTER H

RSYNC H

GND

BDMR L
LOGIC SYMBOL

TRUTH TABLE
WHERE

INPUTS

L = TTL LOW
H = TTL HIGH
X = DON·T CARE

DATI'll

DAliO

L
H
H

L
H

Figure 10

TRANSFER
TYPE
DATIO
DAT I
DATO

DC010 Logic Symbol/Truth Table

204

DDV11-B
DDV11-B Backplane
INTRODUCTION

The DDV11-B is an optional LSI-11 bus expansion backplane for use
when additional logic space is required. The DDV11-8 is a 9 x 6,54slot backplane with a 9 x 4 slot section (18 individual double-height
or nine quad-height module slots) prebused specifically for LSI-11
bus signal, power, and ground connections. The remaining 9 x 2 slot
section is provided with + 5 Vdc, GND, and -12 Vdc powerconnections only; this leaves the remaining pins free for use with any special
double-height logic modules to be used in conjunction with the LSI-11
family of modules and bus requirements.
DESCRIPTION

The DDV11-B consists of an H034 system unit mounting-frame, six
H863 and three H8030 connector blocks, and the etched- board bus
structure necessary for signal routing. The etched board completely
overlays the entire pin side of all connector blocks and is recessed
sufficiently to allow wirewrapping on those same pins with 30-AWG
wire.
An optional cardcage, type H0341 , is also available to provide protection against physical damage to modules and to serve as a cardguide.
The cardcage completely surrounds the slot side of the system unit
and is shown in Figure 1. The DDV11-B can be mounted in the H909-C
enclosure.
NOTE

The H909-C includes the H0341 cardguide.

7920 ~ 2BW • AQ169

Figure 1

DDV11-8 with H0341 Card Assembly

205

DDV11-8
CONFIGURATION
Module Slot Assignments
Figure 2 shows the slot location assignments of the DDV11-B. Rows
A, B, C, and D are dedicated to the LSI-11 bus. Any module which conforms to the LSI-11 bus specifications can be used in this portion of
the DDV11-B. The position numbers indicate the bus-grant wiring
scheme with respect to the processor module. The bus-grant signals
propagate through the slot locations in the position order shown in
Figure 2 until they reach the requesting device. Any unused slots
must be jumpered to provide busgrant signal continuity, or it is recommended that unused locations occur only in the highest positionnumbered locations.

Rows E and F contain the 18 user-defined slots with power and
ground connections provided.
Equipment Supplied
The DDV11-B option consists of the following items:

Six H863 connector blocks
Three H8030 connector blocks
Etched-board bus structure
Installation
The DDV11-8 can be mounted on panels or chassis using standard
hardware. The overall dimensions of the unit are shown in Figure 3.
The H034 mounting frame of the DDV11-8 is provided with tapped
holes and clearance holes to enable the attachment of the system unit.
H0341 Card Assembly Mounting
The card assembly provides nylon guides which help to guide and
support the modules installed in the system unit. The H0341 card
assembly is supplied with the hardware necessary to mount to the
H034 mounting frame. Figure 4 shows the method of assembly. Two
screws (item 2) and two washers (item 1) are inserted through the
clearance holes of the PC board and H034 mounting frame and into
the two threaded inserts on each bracket of the card assembly.

206

DDV11-8
1-

--1

PROCESSOR

POSITION 3

POSITION 4

POSITION 7

-1
-1
7- 1
1
91

POSITION 11

POSITION 12

B-

ROW_

, ,

POSITION 8

POWER
TERMINAL
BLOCK
6-

POSITION 15

POSITION 16

OPTION POSITION 2

I I
I ,
I ,
I I
I ,
I ,
II

, ,

I
I
I
I
I
I
I
I

PROCESSOR OR OPTION 1 J

POSITION 5

POSITION 6

POSITION 9

POSITION 10

POSITION 13

POSITION 14

POSITION 17
C

I
I ,
I ,
II
I I
I I
I I

MODULE INSERTION SIDE

'------US-E-R-DE-FINED SLOTS

MODULE (COMPONENTS MOUNTED ON OPPOSITE SIDE)

"'r : ~:B==III:::!]"w.uI=;III::C~~I=::lIn=IIIII=D=::::!II;lr:WLlII=III~:E=:II~I~I=III
BACKPLANE

~_ _...J

' -_ _----'

' - -_ _--'

=/==::::!1;J

,r";'=11I=A=III!:!:::"LWl.III=1I

Figure 2

'-_ _ _-',

DDV11-8 Module Installation and Slot Assignments

207

DDV11-8
POWER SIGNAL PINS
BHALT L
DCOK Hi---.

N. c.

SPARE-L·0
N.C.t.

~J GND

BEVNT L Z y / " ' SRUN L
BPOK H

I
L

. ~GJ,

I2J

-12V
GND
GND
+5B
+5V
+5V

4.80 IN

(10.21CM)

~
121

1 - - - - - - - - 1 7 . 0 IN (43.18 C M ) - - - - - - - - - i ·

JUMPER
STRAP
MA 2002

T
12.19
14.80)
!

~~--------------------------------~
-..---r-- ------ - - - ---- - -- ----- -- --- -- - ----,
I

!-.... CARD CAGE

H0341

I
:
I

ASSEMBLY
CLEARANCE
OUTLINE

6· 32 X 0.25 10.641
MOUNTING HOLES
16 TOTAL)

22.07
18.69)

13.34
13.34
15.25115.251
41.97

7.65,
-13.012)!

~ ____________ 43.50 __ ':'5241-=-=-=~--·--J
117125!

I\!lR

Figure 3

DDV11-8 Power Wiring and Dimensions
208

1151

DDV11-B
H0341 CARD CAGE ASSEMBLY

BACKPLANE

TH READED -L------"~,...iJ.I
INSERTS

ITEMS 1 & 2 SUPPLIED WITH
CARD ASSEMBLY

DD11V-B SYSTEM UNIT

Figure 4

1157

H0341 Card Assembly Installation

dc Power and PowerSignal Connections
dc power is supplied to the modules in the DDV11-8 through the backplane PC board. The power and ground leads from the external
source connect to the seven-position terminal board mounted on the
edge of the PC board as shown in Figure 3. Any suitable connector
terminals, solder, or crimp style, can be attached to the powersupply
leads and inserted under the terminal strip screws. A jumpertab is
mounted between the two +5 V screws and between the two ground
(GND) screws on the terminal board. The total current c~pability of
the DDV11-8 and the wire size required are asfo"ows:
Terminal
+12V
+5V
+5V
+58
GND
GND
-12V

Current

Wire Size

(Max) .

Jumped

20A
40A

(AWG)
14
14

Jumped

20A
40A

20A

Figure 5 identifies the powersignal pins which are located at the opposite endof the backplane PC board from the power terminal strip-. A
mating female connector(DIGITAL PIN 12-11206-02 or 3M PIN 3473-3)
can be inserted over the pins and used to connect the external signals to the backplane.
209

Backplane Pin Assignments
Table 1 lists the backplane pin assignments for the LSI-11 bus signals and dc power and ground connections
on the OOV11-B backplane.
Table 1

DDV11-B Backplane Pin Assignments

Side
Row

A
B
C
0
I\)
...I.

E
F
H
J
K
L
M
N
P
R
S
T
U
V

2
A&C

1
A&C

+SV
-12V
GNO
+12V
BOOUT L
BRLPY L
BOIN L
BSYNC L
BWTBT L
BIRQL
BIAKI L
BIAKO L
BBS 7 L
BOMG 1 L
BOMG 0 L
BINIT L
BOALOL
BOAL 1 L

BSPARE1
BSPARE2
BOAL 17 L
BOAL 16 L
SSPARE1
SSPARE2
SSPARE3
GNO
MSPAREA
MSPAREA
GNO
BOMRL
BHALT L
BREFL
PSPARE3
GNO
+12B
+SB

B&D

1
B&D

2
E

2
F

+SV
-12V
GNO
+12V
BOAL2 L
BOAL3 L
BOAL4 L
BOALS L
BOAL6 L
BOAL7 L
BOAL8 L
BOAL9 L
BOAL 10 L
BOAL 11 L
BOAL 12 L
BOAL 13 L
BOAL 14 L
BOAL 15 L

BOCOKH
BPOKH
SSPARE4
SSPARES
SSPARE6
SSPARE 7
SSPARE8
GNO
MSPARE B
MSPARE B
GNO
BSACK L
BSPARE6
BEVNT L
PSPARE4
GNO
PSPARE2
+5

+SV
-12V
GNO
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK

BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
GNO
BLANK
BLANK

+SV
-12V
GNO
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK

BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
GNO
BLANK
BLANK

C
C

~
~

a:J

DLV11
DLV11 SERIAL LINE UNIT
SPECIFICATIONS
identification

M7940

Size

Double

Power

+5.0 Vdc ± 5% at 1.0 A (1.6 A
max)
+12.0 Vdc ± 3% at 0.18 A (0.25 A
max)

Bus loads
ac
dc

2.5
1.0

CONFIGURATION
The user can select the register address, parity, number of data bits,
number of stop bits, baud rate, and type of serial interface. The descriptions of the registers and their standard factory addresses are
listed in Table 1. Available jumpers are shown in Figure 1 and their
applications are listed in Table 2.

Table 1

Standard Addresses

Mnemonic

Receiver control status
Receiver data buffer
Transmit control/status
Transmit data buffer
Standard vectors

RCSR
RBUF
XCSR
XBUF
RCSR
XCSR

211

Console
177560
177562
177564
177566
060
064

Second
Module
176500
176502
176504
176506
300
304

DLV11

TPl

9,
,

__ l __

1111

,-T-,

TP2

<l:

:;j

INSERT .005fLF CAPACITOR WHEN
THE SERIAL LINE DEVICE IS A
TELETYPEWRITER (LT33 OR LT35)

>_Nm

wmmcna..

a.ZZNZ

11111

1111111111
ItlvU')W

CDmO=N

<l:<l:<l:<l:

<l:<l:;;:<l:<i

J:
W

CP·ISOI

Figure 1

DLV11 Jumper Locations

212

DLV11
Table 2

DLV11 SLU Factory Jumper Configuration

Jumper
Designation

Jumper
State*

A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

I
R
R
R
I
R
R
R
R
R

V3
V4
V5
V6
V7

I
R
R

This jumper arrangement implements
the interrupt vector: 60 for received data
and 64 for transmitted data.

NP
2S8
N82
N81

R
R
R
R

No parity
Two stop bits
Eight data bits

PEV
FEH
EIA

Even parity if NP installed
Halt on framing error
12 V EIA operation enabled

FRO
FR1
FR2
FR3

R
R
R
R

CL1
CL2
CL3
CL4

Function Implemented

This arrangement of jumpers A3 through
A 12 implements the octal device address 17756X, which is the assigned address for the console device SLU. The
least significant digit is hardwired on the
module to address the four SLU device
registers as follows:
X = 0, RCSR address
X = 2, Receive data register address
X = 4, XCSR address
X = 6, Transmit data register address

110 baud rate selected

20 rnA current loop active receiver and
transmitter selected
(jumpered with 180 ohm resistors)

* R = removed, I = installed

213

DLV11
Addresses
Addresses for the DLV11 can range from 160000s through 17777Xa.
The least-significant-three bits (only bits 1 and 2 are used; bit 0 is ignored) address the desired register in the DLV11, as described in Table 1.

Address bits 3 through 12 are jumper-selected, as shown in Figure 2.

Since each DLV11 module has four registers, each requires four addresses. Addresses 177560-177566 are reserved for the DLV11 used
with the console peripheral device. Additional DLV11 modules should
be assigned addresses from 176500 through 176670, allowing up to 30
additional DLV11 modules to be addressed.
80Al
BITS ,-',",,-5--,---_ _ _. , -_ _ _

I i' I' I

r-=-s_ _- ,_ _ _-----,-_ _--'0:.......,

aas 7 L
"Ill

O"!

!XI

,...

o:t

""'

~"'_"'_ _
" ' _ "_
'
_
"'~~~"'-"'_ _- " ' - " ' - - ' C l

O'CSR

1 = DATA BU~FER

L-~~~~;~I~~~TTER

}

~~R~\~~N
DECODING)

ADDRESS JUMPERS:
INSTALLED '0
REMOVED

RANGE =1600008 - 1777768
~p

Figure 2

1130.

eSR Address Selection

UART Operation
The UART operation is programmed by using jumpers NP, 2SB, NB1,
NB2, and PEV as shown below.
Number of Data Bits
NB1
5
Installed
Removed
6
Installed
7
Removed
8

NB2
Installed
Installed
Removed
Removed

Number of Stop Bits Transmitted
2SB installed = One stop bit
2SB removed = Two stop bits

214

DLV11
Parity Transmitted
NP removed = No parity bit
NP and PEV installed = Odd parity
NP instaiied and PEV removed = Even parity
Baud Rate Selection
Baud rate is programmed via jumpers FRO through FR3 as shown in
Table 3.
EIA Interface
EIA drivers are enabled when jumper EIA is installed. It should be removed during 20 rnA current loop operation.
20 mA Current Loop Interface
Jumpers CL1 through CL4 are associated with 20 rnA current loop interface operation. CL2 and CL3 are 180 ohm resistors.
Active Current Loop
Transmit

Receive

Passive Current Loop
Transmit

Receive

CL4 Jumper installed
CL3 Resistor installed
CL4 Jumper installed
CL3 Resistor installed

CL4 Jumper removed
CL3 Resistor removed
CL4 Jumper removed
CL3 Resistor removed

215

DLV11
Table 3

Baud Rate

FR3

Baud Rate Selection

FR2

FR1

FRO

110

134.5
150

R
R

200
300

600

1200

1800

2400

4800

9600

R
R

External
(via pin BH 1)
NOTE:
I = Installed

X = Irrelevant

216

R = Removed

DLV11-E
DLV11-E ASYNCHRONOUS LINE INTERFACE
INTRODUCTION
The DLV11-E is an asynchronous line interface module that interfaces

the LSI-11 bus to any of several types of serial communications lines.
The module receives serial data from peripheral devices, assembles it
into parallel data, and transfers it to the LSI-11 bus. It accepts data
from the LSI-11 bus, converts it into serial data, and transmits it to the
peripheral devices. The DL V11-E offers full modem control and EIAtype interface.

FEATURES
• Jumper- or program-selectable, crystal-controlled baud rates: 50,
75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400, 3600, 4800,
7200, 9600, and 19,200. Split transmit and receive baud rates are
possible.
• Provisions for user-supplied external clock inputs for baud rate control.
• Jumper-selectable data bit formats.
• LSI-11 bus interface and control logic for interrupt processing and
vectored addressing of interrupt service routines.
• Full modem control (Bell 103, 113, 202C, 2020, and 212-compatible).

SPECIFICATIONS
Identification

M8017

Size

Double

Power

+5.0 Vdc ±5% at 1.0A
+12.0 Vdc ±3% at 0.18 A

Bus loads
AC
DC

1.6
1.0

217

DLV11-E
DESCRIPTION
Major functions contained on the DLV11-E are shown in Figure 1.
Communications between the processor and the DLV11-E are executed via programmed liD operations or interrupt-driven routines.

Bus Interface
The bus interface circuit signal lines consist of data moving between
the LSI-11 bus and the module's internal tri-state bus. It decodes the
device address and produces an address match (MATCH H) signal
and it places interrupt vectors on the LSI-11 bus. The bus interface
receives from the LSI-11 bus unless it is switched to transmit to the
LSI-11 bus. The interrupt logic can cause the bus interface to transmit
either a transmitter or receiver interrupt vector and the liD control
logic can cause the bus interface to transmit to or receive data from
the LSI-11 bus.

The bus interface receives LSI-11 bus lines BDALOO L through
BDAL 15 L and places them on the module's tri-state bus. If BBS7 L is
asserted, the circuit decodes BDAL03 L through BDAL 12 L and asserts MATCH H. Jumpers A3-A 12 are configured to allow the option to
respond to specific device register addresses. Jumpers V3-V8 select
the options' interrupt vector.

I/O Control Logic
When the liD control logic receives MATCH H from the bus interface,
it decodes tri-state bus lines DATOO H through DAT02 H and selects
the addressed device register. The liD control logic exchanges bus
control signals with the processor to perform input and 'output data
transfers.

218

DATA
BUFFERS

~ ~ ~ ffi
iii 0 _

DEVICE
ADDRESS
DECODER

~J
1 ~~£{£;:~~]A [

VECTOR
ADDRESS
GENERATOR

D~RES' ~ECTDR
JUMPERS
AJ·-AI2

I ""

:TRANSMITTER ,I
CONTROL/STATUS

p_J T
REGISTER

.------+---------l

V3-V8

VECTOR H

TRANSMITTER

RECEIVER

CIRCUITRY

CHANNEL

DC-TO-DC
POWER
INVERTER

+12V

-"--t---

20 rnA CURRENT .....LOOP AND
READER RUN
iOLVI'-FONLYI ~

I
{'r

1/0 CONTROL

'AUD RATE CDNTRD'

I I J

RECEOVER
JUMPERS
RO-R3

C
r-

<
......
......

'-DATA
FORMAT
JUMPERS

IIIJ
TRANSMOTTER

JUMPERS
TO-TJ

14-',:::""K",D.::'_ _ _ _ _
alNIT L

INTERRUPT LOGIC

BOCOK H

Figure 1

-12V

I
CONTROL

J'REAK

BRPLY L

81AKI L

*g~ *

LOGIC

BWTBT L

~ ~ ~ ~ I-------------'--+--t-l ~~~~CRATION 1---

AND D
_ _ _ _'V_'_'

1--_ _ _+_--'I

"(7

______~~

SER'A,DUT

RBUr'_Y_"____--,

~r----~-_t~~--;::::::::~--_t_t~---t_----"\
TCL~
FE H
J BREAK
I
Lr-'T""-~..,~o:-J----'-"-'-'---j·1 ~~~;~TlON

'-------

~-4

LOGIC

v 'E ~ §M"NT~"~ill-_J

VECTOR H

+-____+-____

• e ~.

--e.

EIA DATA
LEADS
tBOTH DLV"-E

l,;R:;:E,:."':::'T:..:EyR__......J4-j

MATCH H
VECRQSTB H

EIADATA
4seT CONTROL
IDLVII.E ONLYI

I:RECElvER
CONTROL/STATUS

JUMPERS

~'~'Y~N~C~'_______________

~:
V
~

THREE-STATE BUS
TRANSCEIVERS

V~~~__~~~~4-~'N=W~D~'____l

aaS7 L

IN J MAINTENANCE
g:;: .....SERIAL
- - - j MOPE

7.-----"!-;-~-"-*+:"-~"'-:-"~'-f

BUS
INTERFACE

- ~

PERIPHERAL
INTERFACE

DLV11-E Asynchronous line Interface LogiC Block Diagram

DLV11-E
During an interrupt transaction, VECTOR H from the interrupt logic
causes the circuit to assert BRPL Y L in response to BDIN L. During
data transactions, the I/O control logic asserts INWD L to switch the
bus interface transceivers from receiving to transmitting.

Control/Status Registers
The receiver control/status register (RCSR) and the transmitter control/status register (XCSR) are enabled by selection signals from the
I/O control logic. The CSRs are byte addressable for reading status
bits or writing control bits.
Data Buffers
The receiver buffer (RBUF) and transmitter buffer (XBUF) provide
double-buffering, in that one byte of data can be held while another
byte is entering or exiting. This allows asynchronous, full-duplex operation. Data is handled in the low byte of the registers. The buffer
control circuitry places receiver buffer error flag bits in the high byte of
the RBUF. It also sends a status bit to the RCSR and a framing error bit
(FE H) to the break logiC.
Receiver Active Circuit
This circuit monitors the received serial data line and sets a status bit
(RCVR ACT) as soon as the RBUF begins receiving data. It clears the
bit when a character of data has been received.

Interrupt Logic
The DLV11-E can generate transmitter interrupts. If the XBUF is ready
to serialize another character of data and the transmitter interrupt
enable bit is set in the XCSR, the interrupt logic requests to interrupt
the processor (by asserting BIRO L.) If the processor acknowledges
via the BIAKI/BIAKO daisy-chain, the interrupt logic asserts VECTOR
Hand VECROSTB H. These signals cause the bus interface to place
the transmitter function interrupt vector address on the LSI-11 bus.
The module also can request a receiver interrupt if the RBUF has
received a character and the receiver interrupt bit is set in the RCSR.
When the interrupt request is acknowledged, the interrupt logic asserts VECTOR H. VECTOR H causes the bus interface circuit to place
the receiver function interrupt vector on the LSI-11 bus. (VECROSTB
H is used only for a transmitter interrupt.)

220

DLV11-E
The OL V11-E also generates a receiver interrupt as a result of data set
status. If the data set interrupt enable bit is set in the RCSR, a receiver
interrupt will result from a change of state on any of the modem controllines (ring, clear to send, carrier, or secondary received data).
The interrupt acknowledge daisy-chain (BIAKI/BIAKO) passes
through both the receiver and transmitter sections of the interrupt
logic. It goes through the receiver section first, thereby giving the
receiver channel priority over the transmitter channel.

Baud Rate Control
The baud rate control establishes the speed at which the data buffers
handle serial data. It produces clock Signals by dividing a crystal oscillator frequency by an amount selected by jumpers or the program.
The circuit can be jumpered to generate either independent transmitter and receiver clocks (split speed operation) or a common clock
(common speed operation).

When the programmable baud rate enable bit is set in the XCSR, the
baud rate control decodes tri-state bus lines OAT12 H through OAT15
H. These bits control the receive baud rate in split speed operation
and both transmit and receive baud rate in common speed operation.
When programmable baud rate is not enabled, the baud rates are
controlled by jumpers. In split speed operation, jumpers RO-R3 control the receive baud rate and jumpers TO-T3 control the transmit baud
rate. In common speed operation, RO-R3 control both baud rates.
The circuit also has provisions for a user-supplied external clock.

Break Logic
A break signal is a continuous spacing condition on the serial data
line. If the break bit is set in the XCSR, the module will transmit a break
signal to the peripheral device (normally another processor). If the
module receives a break signal from the peripheral device (normally a
console device), the RBUF control circuitry interprets the absence of
stop bits as a framing error. The circuit can be jumpered to ignore the
framing error, to place the processor in the halt mode, or to cause the
processor to reboot. The break logic asserts BHALT L to halt the
processor. It negates BOCOK H to reboot.

221

DLV11-E
Maintenance Mode Logic
The modules can check out their data paths up to (but not including)
the peripheral interface circuit by looping the XBUF's serial output
back to the RBUF's serial input. Data from the LSI-11 bus sti II goes to
the peripheral device, but no data is received from the peripheral in
this maintenance mode. The program can compare received (looped)
data with transmitted data to check for errors. The maintenance mode
i:; entered by setting the maintenance bit in the XCSR.
Signal Peripheral Interface
This circuit converts the module's TTL levels to EIA standard levels for
modem control. It receives ring, carrier, clear to send, and secondary
received data from the data set. It transmits data terminal ready, request to send, force busy, and secondary transmitted data to the data
set. (Request to send and force busy are jumper-selectable.) If data set
interrupts are enabled, a change in state on any of the received control
lines initiates a receiver interrupt. Data is received on the received
data line and transmitted on the transmitted data line. Handshake
sequences are under program control.
DC-to-DC Power Inverter
The power inverter uses the + 12V from the backplane to produce
-12V for the peripheral interface and data buffer circuitry. It consists
of an oscillator, rectifier, inductive charge pump, and a zener regulator.
CONFIGURATION
The following paragraphs describe how the user can configure the
module to function within his system. The user can select the register
addresses, interrupt vectors, data format, baud rate, and interface
mode. The descriptions of the registers and their standard factory
addresses are listed in Table 1. The jumpers used on this module
consist of wire-wrap pins to which the connections are made; their
the
locations are shown in Figure 2 . A complete listing of
jumpers and a description of their functions are contained in Table 2.

Addresses for the DLV11-E can range from 160000 through 1777708 ,
The least significant three bits (only bits 1 and 2 are used; bit 0 is
ignored) address the desired registers in the module, as described in
Table 1. Address bits 3 through 12 are jumper-selected as illustrated
in Figure 3.

222

DLV11-E
Since each module has four registers, each requires four addresses.
Addresses 177560-177566 are reserved for the module used with the
console peripheral device. Additional modules should be assigned
addresses from 175610 through 176176, allowing up to 30 additional
DLVII-E moduies to be addressed.

Table 1

Standard Assignments

Description

Mnemonic

Console
Module

RCSR
RBUF
XCSR
XBUF

177560
177562
177564
177566

175610
175612
175614
175616

60
64

300
304

Interrupts
Receiver
Transmitter

223

Second
Module

DLV11-E

MN.-OMN-O

1-1-1-1-0::0::0::0::

J~~IIIII
M

- S1

c::

-FOII-FR

(.)

...J

- M1

E
::J

"-)

IBG

T"""
T"""

...J

0
(\J

CO,.. <£)U)'<tM

»»»

IIIIII
II II I IIIII
N ... OcnCO"'<£)U)'<tM

CD
~

I ~

::J
C)

u::

cs-

:i:i:ic{c{c{c{c{c{c{

11-5172

224

DLV11-E
BDAl
BITS

I I

I R IR I R I I

BBS? L
~ 1 (U

ADD:ESS J:MPER::
INSTALLED., 1
REMOVED ~O

~ ~ ~J
o =RECEIVER

1 = TRANSMITTER

}

? ~ ~~A BUFFER} - - - '
0= LOW BYTE} _ _ _--'
1 =HIGH BYTE

RANGE = 1600008 - 177776 8
11-4911

Figure 3
Table 2

DLV11-E Addressing

DL V11-E Jumper Definitions

NOTE
Jumpers are inserted to enable the function they
control except for those jumpers which indicate negation (such as "-8" and "E"). Negated jumpers are
removed to enable the functions they control.
Jumper

Function

A3-A12

These jumpers correspond to bits 3 through 12 of
the address word. When inserted, they will cause the
bus interface to check for a true condition on the
corresponding address bit.

V3-V8

Used to generate the vector during an interrupt
transaction. Each inserted jumper will assert the corresponding vector bit on the LSI-11 bus.

RO-R3

Receiver and transmitter baud rate select jumpers
during common speed operation.
Receiver-only baud rate select jumpers during split
speed operation as defined in Table 3.

TO-T3

Transmitter baud rate select jumpers during split
speed operation.
80th receiver and transmitter baud rate if maintenance mode is entered during split speed operation
as defined in Table 3.

225

DLV11-E
BG

Jumper is inserted to enable break generation.

Jumper is inserted for operation with parity.

Removed for even parity; inserted for odd parity.

1,2

These jumpers select the desired number of data
bits, as defined in Table 4.

Jumper is inserted to enable the programmable
baud rate capability.

C,C1

These jumpers are inserted for common speed operation. (Note that Sand S1 must be removed when
C and C1 are inserted.)

S,S1

Inserted for split speed operation. (Note that C and
C1 must be removed when Sand S1 are inserted.)

This jumper is inserted to assert BHAL T L when a
framing error is received, except when the maintenance bit is set. This places the processor in the halt
mode.

B, -B

Jumper B is inserted to negate BDCOK H when a
break signal or framing error is received, except
when the maintenance bit is set. This causes the
processor to reboot. (Jumper -B must be removed
when B is inserted.)

-FD

Jumper is removed to force data terminal ready signalon.

-FR

Jumper is removed to force request to send signal
on.

This jumper is inserted to enable normal transmission of the request to send signal.

Inserted to enable transmission of the force busy
signal (for Bell model103E data sets).

M,M1

These are test jumpers used during the manufacture
of the module. They are not defined for field use.

226

DLV11-E
Interrupt Vectors
The interrupt vectors are selected by using jumpers V3 to VB. The
standard configuration is shown in Figure 4 and Table 1. The vectors
can range from 001 through 774. Note that vectors 60 and 64 are
reserved for the console device. Additional DLV11-E modules should
be assigned vectors following any DRV11 parallel interface modules
installed in the system that start at address 300.

BDAl
BITS

I I I I ...I

SELECTED BY USER.
ASSERTED BY INTERRUPT ~
lOGIC CIRCUIT. '

VECTOR JUMPERS:
INSTAllED~ 1
REMOVED~O

0 RECEIVER
1 ~TRANSMITTER

CONTROllED BY INTERRUPT
lOGIC CIRCUIT.
RANGE ~ 0-7748
11-4912

Figure 4

DLV11-E Interrupt Vector

Baud Rate Selection
The DLV11-E allows the user to configure jumpers TO-T3 and RO-R3
for the transmit baud rate and the receiver baud rate as shown in
Table 3.
Data Bit Selection
The number of data bits being transmitted or received by the DL V11-E
is user-selectable by installing or removing jumpers 1 and 2. The
specific number of data bits as controlled by the configuration of
jumpers 1 and 2 is shown in Table 4.
Factory Configuration
The user can reconfigure any of the jumpers to make the module meet
his requirements. The factory configuration as shipped is shown in
Table 5 to help the user determine if any changes are required.
Registers
The word format for the DL V11-E CSR is shown in Figure 5 and its
functions are described in Table 6.

227

DLV11-E
Table 3

DLV11-E Baud Rate Selection

Program Control
Receive Jumpers

Bit
15
R3

Bit
14
R2

Bit
13
R1

Bit
12
RO

Transmit Jumpers

Bit
11*
Baud
Rate

50
R

110

R
R

134.5
150

R
R

300
600

1200
1800

2000
2400

3600
4800

7200
9600

19200

I = jumper inserted = program bit cleared.
R = jumper removed = program bit set.
.. Bit 11 of the XCSR (write-only bit) must be set in order to select a new baud
rate under program control. Also, jumper PB must be inserted to enable
baud rate selection under program control.

228

DLV11-E
Table 4

DL V11-E Data Bit Selection

Jumpers
2

N umber of Data Bits
1
5
R

Table 5

DLV11-E Factory Jumper Configuration

Jumper
Designation

Jumper
State

A3
A4
A5
A6
A7

I
R
R
R

AB
A9
A10
A11
A12

V3
V4
V5
V6
V7
VB

R
R
R

RO
R1
R2
R3

I
R

Function Implemented
Jumpers A3 through A 12 implement device address 17561X. The least significant octal digit is hardwired on the module to address the four device registers
as follows:
X=O
X=2
X=4
X=6

RCSR
RBUF
XCSR
XBUF

This jumper selection implements interrupt vector address 300 8 for receiver
interrupts and 3048 for transmitter interrupts.

R
This module is configured to receive at
110baud.

229

DLV11-E
TO
T1
T2
T3

I
R
R
R

The transmitter is configured for 9600
baud if split speed operation is used.

BG
P

I
R

Break generation is enabled
Parity bit is disabled.

Parity type is not applicable when Pis
removed

1
2

R
R

Operation with eight data bits per character

Programmable baud rate function disabled.
Common speed operation enabled.

C
C1
S
S1

R
R

Split speed operation disabled.

Halt on framing error disabled.

B
-B

R
I

Boot on framing error disabled.

The data terminal ready signal is not
forced continuously true.

The circuitry controlling the request to
send signal is enabled.

The force busy signal is disabled.

Error flags are enabled.

Maintenance bit is disabled.

M
M1

R
R

Factory test jumpers. Not defined for
field use.

,,- 4964

Figure 5

DLV11-E RCSR Register Word Format
230

DLV11-E
Table 6

DLV11-E RCSR Bit Assignments

Bit: 15
Name: DATA SET INT
Description: (Data Set Interrupt)
This bit initiates an interrupt sequence provided the DSET INT ENB
(bit 5) is also set.
This bit is set whenever CAR DET, CLR TO SEND, or SEC REC
changes state, i.e., on a 0 to 1 or 1 to 0 transition of anyone of these
bits. It is also set when RING changes from 0 to 1.
Cleared by INIT or by reading the RCSR. Because reading the register
clears the bit, it is, in effect, a "read-once" bit.

Bit: 14
Name: RING
Description: When set, indicates that a ringing signal is being received from the data set. Note that the ringing signal is not a level but
an EIA control with a duty cycle of 2 seconds ON and 4 seconds OFF.
Read-only bit.
Bit: 13
Name: CLR TO SEND
Description: (Clear to Send)
This state of this bit is dependent on the state of the clear to send
signal from the data set. When set, this bit indicates an ON condition;
when clear, it indicates an OFF condition.
Read-only bit.
Bit: 12
Name: CAR DET
Description: (Carrier Detect)
This bit is set when the data carrier is received. When clear, it indicates
either the end of the current transmission activity or an error condition.
Read-only bit.
Bit: 11
Name: RCVR ACT
Description: (Receiver Active)
When set, this bit indicates that the DLV11-E's receiver is active. The
bit is set at the center of the start bit, which is the beginning of the input
serial data from the device, and is cleared by the leading edge of
ROaNE H.
Read-only bit; cleared by INIT or by RDONE H (bit 7).
Bit: 10
Name: SEC REC
Description: (Secondary Received or Supervisory Received Data)
This bit provides a receive capability for the reverse channel of a
remote station. A space (+6V) is read as a 1. (A transmit capability is
provided by bit 3.)
Read-only bit.
231

DLV11-E
Name: Not Used
Bit: 9-8
Description: Reserved for future use.
Bit: 7
Name: RCVR DONE
Description: (Receiver Done)
This bit is set when an entire character has been received and is ready
for transfer to the processor. When set, initiates an interrupt sequence
provided RCVR INT ENS (bit 6) is also set.
Cleared whenever the receiver buffer (RSUF) is addressed. Also
cleared by INIT.
Read-only bit.

Bit: 6
Name: RCVR INT ENS
Description: (Receiver Interrupt Enable)
When set, allows an interrupt sequence to start when RCVR DONE (bit
7) sets.
Read/write bit; cleared by INIT.
(See Note 1.)

Bit: 5
Name: DSET INT ENS
Description: (Data Set Interrupt Enable)
When set, allows an interrupt sequence to start when DATA SET INT
(bit 15) sets.
Read/write bit; cleared by INIT.
(See Note 1.)

Bit: 4
Name: Not Used
Description: Reserved for future use.
Bit: 3
Name: SEC XMIT
Description: (Secondary Transmitted or Supervisory Transmitted
Data)
This bit provides a transmit capability for a reverse channel of a remote station. When set, transmits a space (approx. +11.5V). (A receive capability is provided by bit 10.)
Read/write bit; cleared by INIT.

Bit: 2
Name: REO TO SEN D
Description: (Request to Send)
A control lead to the data set which is required for transmission. A
jumper on the DLV11-E ties this bit to REO TO SEND or force busy in
the data set.
Read/write bit; cleared by INIT.

232

DLV11-E
Bit: 1
Name: DTR
Description: (Data Terminal Ready)
A control lead for the data set communication channel. When set,
permits connection to the channel. When clear, disconnects the interface from the channel.
Read/write bit; must be cleared by the program; is not cleared by INIT.
(See Note 2.)
NOTES
1. When clearing an interrupt enable bit, first set the appropriate
processor status bit = 1. After the interrupt enable bit at the module is cleared, the processor may be returned to its normal
priority.
2. The state of this bit is not defined after power-up.
3. INIT = LSI-11 bus BINIT signal assertion.
The word format for the DLV11-E RBUF register is shown in Figure 6
and its functions are described in Table 7.
11

RESERVED

RECEIVED DATA BITS

, , - 4966

Figure 6

Table 7

DLV11-E RBUF Register Word Format

DLV11-E RBUF Bit Assignments

Name: ERROR
Bit: 15
Description: (Error)
Used to indicate that an error condition is present. This bit is the
logical OR of OR ERR, FR ERR, and P ERR (bits 14, 13, and 12,
respectively). Whenever one of these bits is set, it causes error to set.
This bit is not connected to the interrupt logic.
Read-only bit; cleared by removing the error-producing condition.

NOTE
Error indications remain present until the next character is received, at which time the error bits are
updated. INIT clears the error bits.
Bit: 14
Name: OR ERR
Description: (Overrun Error)
When set, indicates that reading of the previously received character
was not completed (RCVR DONE not cleared) prior to receiving a new
character.
Read-only bit. Cleared by INIT.
233

DLV11-E
Bit: 13
Name: FR ERR
Description: (Framing Error)
When set, indicates that the character that was read had no valid stop
bit.
Read-only bit. Cleared by INIT.

Bit: 12
Name: P ERR
Description: (Parity Error)
When set, indicates that the parity received does not agree with the
expected parity. This bit is always 0 if no parity is selected.
Read-only bit. Cleared by INIT.

Bit: 11-8
Name: Not Used
Description: Reserved for future use.
Bit: 7-0
Name: RECEIVED DATA
Description: Holds the character just read. If less than eight bits are
selected, then the buffer is right-justified into the least significant bit
positions. In this case, the unused bits are read as Os.
Read-only bits; not cleared by INIT.

NOTE
INIT = LSI-11 bus BINIT signal assertion.
The word format for the DLV11-E XCSR register is shown in Figure 7
and its functions are described in Table 8.
15

RESERVEO

RESERVED

"-4967

Figure 7

Table 8

DLV11-E XCSR Register Word Format

DLVll-E XCSR Bit Assignments

Bit: 15-12
Name: PBR SEL
Description: (Programmable Baud Rate Select)
When set, these bits choose a baud rate from 50-9600 baud.
See Table 3.
Write-only bits.

Bit: 11
Name: PBR ENB
Description: (Programmable Baud Rate Enable)
This bit must be set in orderto select a new baud rate indicated by bits
12-15.
Write-only bits.

234

DLV11-E
Name: Not Used
Bit: 10-8
Description: Reserved for future use.
Bit: 7
Name: XMIT ROY
Description: (Transmitter Ready)
This bit is set when the transmitter buffer (XBUF) can accept another
character. When set, it initiates an interrupt sequence provided XMIT
INT ENB (bit 6) is also set.
Bit: 6
Name: XMIT INT ENB
Description: (Transmitter Interrupt Enable)
When set, allows an interrupt sequence to start when XMIT ROY (bit 7)
is set.
Read/write bits; cleared by INIT.
(See Note.)

Bit: 5-3
Name~ Not Used
Description: Reserved for future use.
Bit: 2
Name: MAINT
Description: Used for maintenance function. When set, connects the
transmitter serial output to the receiver serial input while disconnecting the external device from the receiver serial input. It also forces the
receiver to run at transmitter baud rate speed when common speed
operation is enabled.
Read/write bit; cleared by INIT.

Bit: 1
Name: Not Used.
Description: Reserved for future use.
Bit: 0
Name: BREAK
Description: When set, transmits a continuous space to the external
device.
Read/write bit; cleared by INIT.

The word format for the OLV11-E XBUF register is shown in Figure 8
and its functions are described in Table 9.

235

DLV11-E
08

00
TRANSMITTER DATA BUFFER

RESERVED

Figure 8

DLV11-E XBUF Register Word Format

Table 9

DLV11-E XBUF Bit Assignments

11·5155

Bit: 15-8
Name: Not Used
Description: Not defined. Not necessarily read as Os.
Bit: 7-0
Name: TRANSMITTER DATA BUFFER
Description: Holds the character to be transferred to the external
device. If less than eight bits are used, the character must be loaded
so that it is right-justified into the least significant bits.
Write-only bits. Not necessarily read as Os.

Insta"ation
Prior to installing the DLV11-E on the backplane, first establish the
desired priority level to determine the backplane slot in which the
module will be installed. Then, check that module configuration jumpers are configured as required for your application. Connection to the
peripheral device is via an optional BC05C-X* modem cable for EIA
interface applications.
The BC05C cable provides the correct connection to the 40-pin connector on the DL V11-E. The peripheral device end of the cable is
terminated with a Cinch DB25P connector that is pin-compatible with
Bell 103, 113, 202C, 202D, and 212 modems. Connector pinning and
signal levels conform to EIA specification RS-232C. The EIA interface
circuit is shown in Figure 9; jumpers are shown in Figure 2.
*X = Length in feet. Standard length is 25 feet.

236

DLV11-E
DLVII-E

BC05C MODt:M CABLE

DATA SET

r-------------~~------------__,\

,~------------~'----------~

,----A------.,

XSUF

lr--------~.[>>------",-JII'-«BERG
F ell TRANSMITTED DATA

' - -_ _ _ _...J

RCSR
r-------~'------,

BIT #;---_ _ _ _-;
15

TTL/EIA

CO~~~~~ER

DATA SET
INTERRUPT

f---+---+-< x ( I RING INDICATOR

RING

CLEAR
TO SEND

CARRIER
DETECT

I
I

EIA/TTL
14

CINCH
EIA CIRCUIT
PI (
.L.--DESIGNATION
I 2 ~ I
BA

I
f---+---+-< T ( I CLEAR TO SEND
I
I--+--+<SS( i CARRIER

( 22

I
(5~CS

I
(B~CF

I
I

1-----+-< JJ ( I SECONDARY RECEIVED DATA

SECONDARY
RECEIVE

I
I

I PROTECTIVE GROUND

I
7

PROTECTIVE GROUND

B~~S~IG~N~A~L~G~R~O~UN~D~--------~

>------+-<FF ( I SECONDARY TRANSMITTED DATA

r<>--'-<>+< V ( I REQUEST TO SEND

REQUEST
TO SEND

'-0-.:0--,-( C ( : FORCE BUSY

DATA
TERMINAL
READY

>--------+-<DD(

. _____-+!I--« J

I DATA TERMINAL READY

L'I

I
<-r--

I
I
I
I
I

I
I
I

TTLIE IA
SECONDARY
TRANSMIT

( 11

ft--- SBA

( 4

f+----- CA

( 25

(20 ~ CD

~(-+II_R"'E=.:C~E"-IV.:..:E=-=D'---"DA:cT:.::A'----________--,--« 3 f"------ BB

I,...>------------------'-<'( J
M

RB UF

UU~~S~IG~N~A~L~G~R~O~UN~D~-----/

DSET
INT ENS

I
I
I

VV~~~~~~~~~-----,~ 1

(12~ SBB

~ A ~...:...:..:..:,-,-=:...:..:...:-=----:=-=.c,-,=_--..

f+----- CE

EIA
INTERLOCK

11 - 4931

Figure 9

DLV11-E Peripheral Interface Signal Flow

237

DLV11-F
DLV11-F ASYNCHRONOUS LINE INTERFACE
INTRODUCTION
The DLV11-F asynchronous line interface module interfaces the LSI11 bus to any of several standard types of serial communications lines.
The module receives serial data from peripheral devices, assembles it
into parallel data, and transfers it to the LSI-11 bus. It accepts data
from the LSI-11 bus, converts it into serial data, and transmits it to the
peripheral devices. The DLV11-F supports either 20 mA current loop
or EIA-standard lines, but does not include modem control.
FEATURES
• Jumper- or program-selectable, crystal-controlled baud rates: 50,
75, 110, 134.5,150,300,600, 1200, 1800,2000,2400,3600,4800,
7200, 9600, and 19,200. Split transmit and receive baud rates are
possible.
• Provisions for user-supplied external clock inputs for baud rate control.
• Jumper-selectable data bit formats.
• LSI-11 bus interface and control logic for interrupt processing and
vectored addressing of interrupt service routines.
• Control, status, and data buffer registers directly accessible via
processor instructions.
• Support for "data leads only" modem (Bell type 103, 113).
• Generation of reader run signal for use with ASR-type terminals
(when equipped with reader run relay).

SPECIFICATIONS
Identification

M8028

Size

Double

Power

+5.0 Vdc ±5% at 1.0 A
+12.0 Vdc ±3% at 0.18 A

Bus loads
AC
DC

2.2
1.0

DESCRIPTION
Major functions of the DLV11-F are shown in Figure 1. Communications between the processor and the DL V11 are executed via programmed I/O operations or interrupt-driven routines.

238

~~ffi "~...! 0:~ ~_RIALIN

BUS
INTERFACE

~
~

r---------~-~-~-------II

~ATOO"H

TRANSCEIVERS

OEV'CE
ADDRESS
DECODER

THREE STATE BUS

VECWR
ADDAESS
GENERATOR

~ ~
JUMPERS

JUMPERS

V3··V8

IrANSM'TTER
CONTROL/STATUS

I:REcmER
CONTROL/STATUS

~W
r

VECTOR H

L------

I
I

r----- -

VECROSTB H

BSVNC l
-.~

---

~~
~~

~ ~ !!!~ ~~
Z

«·.JCl

e:~~

LOG'C

e:tll

c·-

C-- c--

fOE H

BREAK

DETECTION

Q
BAUD RATE CONTROL

l..DATA
FOAMAT
JUMPERS

BRPLY l

GIRO L
BIAIO L
BIAKO L

I
CONTROL

TRANSMITTeR

RECEIVER

CIRCUITRY

CHANNEL

I I I

REC,,"ER
JUMPERS
RO-R3

IIII
TRANSM"',"
JUMPERS
TO-TJ

GINIT L

INTERRUPT LOGIC
SHALT L
aOCOK H

Figure 1

f-t-f--

-- -

+12V

BDtNL

20mA CURReNT
LOOP AND
READER RUN
IOLV11-F ONLY)

MAINTH

BoaUT L

IOOTH DlVII··E
AND DlV!! Fl

DC~TO-OC

I---

'1--

It-+
t--

LOGIC

1/0 CONTROL
LOGIC

EIADATA

BREAK
GENERATION
LOGIC

-12V

IDlV,' E ONLY)

LEADS

SERIAL OUT

E'A DATA
SET CONTROL

RBUSY H

TC~

_._--

INVERTER

VECTOR H

._------

wOw

POWEA

MATCH H
_

~ ~3 *~ffi~

MODE

--~

t
L

MAINTENANCE

7~" ~
",

ACLK H

STATUS
AEGISTERS

AJ AI2

SWTRT l

r---V'

l~'""',r sE

'NINO l

PERIPHERAL
INTERFACE

ACTIVE
CIRCUIT

DATA
BUFFERS

DLV11-F Asynchronous Line Interface Logic Block Diagram

<
.....
.....
I

DLV11-F
Bus Interface
The bus interface circuit signal levels consist of data moving between
the LSI-11 bus and the module's internal tri-state bus. The interface
decodes the device address and produces an address match (MATCH
H) signal, and places interrupt vectors on the LSI-11 bus. The interface
receives from the LSI-11 bus unless it is switched to transmit to the
LSI-11 bus. The interrupt logic can cause the bus interface to transmit
either a transmitter or a receiver interrupt vector; the 110 control logic
can cause the interface to transmit or receive data to or from the LSI11 bus.
The interface receives LSI-11 bus lines BDALOO L through BDAL 15 L
and places them on the module's tri-state bus. If BBS7 L is asserted,
the circuit decodes BDAL03 L through BDAL 12 L and asserts MATCH
H. Jumpers A3-A 12 are configured to let the option respond to specific device register addresses. Jumpers V3-V8 select the option's interrupt vector.

1/0 Control Logic
When the I/O control logic receives MATCH H from the bus interface,
it decodes tri-state bus lines DATOO H through DAT02 H and selects
the addressed device register. The 110 control logic exchanges bus
control Signals with the processor to perform input and output data
transfers. During an interrupt transaction, VECTOR H from the interrupt logic causes the circuit to assert BRPLY L in response to BDIN L.
During data transactions, the I/O control logic asserts INWD L to
switch the bus interface transceivers from receiving to transmitting.
Control/Status Registers
The receiver control/status register (RCSR) and the transmitter control/status register (XCSR) are enabled by selection signals from the 1/
o control logic. The CSRs are byte-addressable for reading status bits
or writing control bits.
Data Buffers
The receiver buffer (RBUF) and transmitter buffer (XBUF) provide double-buffering in that one byte of data can be held while another byte is
entering or exiting. This allows asynchronous, full-duplex operation.
Data is handled in the low byte of the registers. The buffer control circuitry places receiver buffer error flag bits in the high byte of the
RBUF. If also sends a status bit to the RCSR and a framing error bit
(FE H) to the break logic.

240

DLV11-F
Receiver Active Circuit
This circuit monitors the received serial data line and sets a status bit
(RCVR ACT) as soon as the RBUF begins receiving data. It clears the
bit when a full character of data has been received.
Interrupt Logic
The DLV11-F can generate transmitter interrupts. If the XBUF is ready
to serialize another character of data and the transmitter interrupt
enable bit is set in the XCSR, the interrupt logic requests to interrupt
the processor (by asserting BIRQ L). If the processor acknowledges
via the BIAKIIBIAKO daisy-chain, the interrupt logic asserts VECTOR
Hand VECRQSTB H. These signals cause the bus interface to place
the transmitter function interrupt vector address on the LSI-11 bus.

The module also can request a receiver interrupt if the RBUF has
received a character and the receiver interrupt bit is set in the RCSR.
When the interrupt request is acknowledged, the interrupt logic asserts VECTOR H. VECTOR H causes the bus interface circuit to place .
the receiver function interrupt vector address on the LSI-11 bus.
(VECRQSTB'H is used only for a transmitter interrupt.)
The interrupt acknowledge daisy-chain (BIAKI/BIAKO) passes
through both the receiver and transmitter sections of the interrupt
logic. It goes through the receiver section first, thereby giving the
receiver channel priority over the transmitter channel.
Baud Rate Control
The baud rate control establishes the speed at which the data buffers
handle serial data. It produces clock signals by dividing a crystal oscillator frequency by an amount selected by jumpers or by the program.
The circuit can be jumpered to generate either independent transmitter and receiver clocks (split speed operation) or a common clock
(common speed operation).

When the programmable baud rate enable bit is set in the XCSR, the
baud rate control decodes tri-state bus lines DAT12 H through DAT15
H. These bits control the receive baud rate in split speed operation
and both transmit and receive baud rate in common speed operation.
When programmable baud rate is not enabled, the baud rates are
controlled by jumpers. In split speed operation, jumpers RO-R3 control the receive baud rate and jumpers TO-T3 control the transmit baud
rate. In common speed operation, RO-R3 control both baud rates.
The circuit has provisions for a user-supplied external clock.
241

DLV11-F
Break Logic
A break signal is a continuous spacing condition on the serial data
line. If the break bit is set in the XCSR, the module will transmit a break
signal to the peripheral device (normally another processor). If the
module receives a break signal from the peripheral device (normally a
console device), the RBUF control circuitry interprets the absence of
stop bits as a framing error. The circuit can be jumpered to ignore the
framing error, to place the processor in the halt mode, or to cause the
processor to reboot. The break logic asserts BHAL T L to halt the
processor. It negates BDCOK H to reboot.

Maintenance Mode Logic
The modules can check out their data paths up to (but not including)
the peripheral interface circuit by looping the XBUF's serial output
back to the RBUF's serial input. Data from the LSI-11 bus still goes to
the peripheral device, but no data is received from the peripheral in
this maintenance mode. The program can compare received (looped)
data with transmitted data to check for errors. The maintenance mode
is entered by setting the maintenance bit in the XCSR.
Peripheral Interface
This circuit can be jumpered to support either EIA-Ievel data leads (no
modem control) or 20 mA current loop modes. When interfacing EIAlevel data leads ("data leads only" operation), request to send, force
busy, and data terminal ready are continuously true by separate EIA
drivers. No modem control signals are received.
In the current loop mode of operation, the circuit uses optical isolators
to interface TTL to 20 mA current loops. This operation is jumperselectable for either active or passive operation of the transmitter and
receiver circuitry.
The peripheral interface also produces a reader run current to advance the paper tape reader on a peripheral equipped with a reader
run relay. This is controlled by the reader enable bit in the DLV11-F's
RCSR.

DC-to-DC Power Inverter
The power inverter uses the + 12V from the backplane to produce 12V for the peripheral interface and data buffer circuitry. It consists of
an oscillator, rectifier, inductive charge pump, and a zener regulator.
242

DLV11-F
CONFIGURATION
The following paragraphs describe how the user can configure the
module to function within his system. The user can select the register
addresses, interrupt vectors, data format, baud rate, and interface
mode. The registers and their standard factory addresses are listed in
Table 1. The jumpers used on this module consist of wire-wrap pins to
which the connections are made; their locations are shown in Figure 2.
A complete listing of the jumpers and a description of their functions
are listed in Table 2.
Addresses
Addresses for the DL V11-F can range from 160000s through 177770s '
The least significant three bits (only bits 1 and 2 are used; bit Ois
ignored) address the desired registers in the module, as shown in
Table 1. Address bits 3 through 12 are jumper-selected as shown in
Figure 3.
Since each module has four registers, each requires four addresses.
Addresses 177560-177566 are reserved for the module used with the
console peripheral device. Additional modules should be assigned
addresses from 176500 through 176670, allowing up to 30 additional
DLV11-F modules to be addressed.
Interrupt Vectors
The interrupt vectors are selected by using jumpers V3 to VB. The
standard configuration is shown in Figure 4 and Table 1. The vectors
can range from 001 through 774 s . Note that vectors 60 s and 64 s are
reserved for the console device. Additional DL V11-F modules should
be assigned vectors following any DRV11 peripheral interface module
installed in the system that starts at address 300 s '
Table 1

Standard Assignments

Description

Mnemonic

Console
Module

RCSR
RBUF
XCSR
XBUF

177560
177562
177564
177566

176500
176502
176504
176506

60
64

300
304

Interrupts
Receiver
Transmitter
243

Second
Module

Through Etch Rev B

Etch Rev C or later

f\-------Il
I
~ I:iiillii
\I I

~% ~~

1111

Q02.

=----=

~~~2:::

II! I

lW"N

-c::::rC29
-3A
2P
2A
1P ---1A

- - 4P
4A:--: 3P
5A-R3
R2:---:R1
RO-

'2!a..

:i i ! i

:T3

C1M1:--:EF

-c
s:
=-E
1.

--2

=---=
B
-H

-S1
TO-_-.T1

T2:

Ie;;

-B

P-

_M
-BG
V5--_-MT

-v6

V7:
:A7
A6==='A5

E25

A12-

A11

Figure 2

-A10
A9-::='A8

DLV11-F Jumper Locations

A -4 --V8
-A3
V4_-_V3
PB=--=BP1
AA1==AB1

..".
..".
I

DLV11-F
Table 2

DLV11-F Jumper Definitions

Jumper

Function

A3-A12

These jumpers correspond to bits 3 through 12 of
the address word. When inserted, they cause the
bus interface to check for a true condition on the
corresponding address bit.

V3-V8

Used to generate the vector during an interrupt
transaction. Each inserted jumper asserts the corresponding vector bit on the L81-11 bus.

RO-R3

Receiver and transmitter baud rate select jumpers
during common speed operation.
Receiver-only baud rate select jumpers during split
speed operation, as defined in Table 3.

TO-T3

Transmitter baud rate select jumpers during split
speed operation.
80th receiver and transmitter baud rate if maintenance mode is entered during split speed operation,
as defined in Table 3.

Jumper is inserted to enable break generation.

Jumper is inserted for operation with parity.

Receiver checks for appropriate parity and transmitter inserts appropriate parity.

1,2

These jumpers select the desired number of data
bits, as defined in Table 4.

Jumper is inserted to enable the programmable
baud rate capabnity.

C,C1

These jumpers are inserted for common speed operation. (Note that 8 and 81 must be removed when
C and C1 are inserted.)
245

DLV11-F
S,S1

Inserted for split speed operation. (Note that C and
C1 must be removed when Sand S1 are inserted.)

This jumper is inserted to assert BHAL T L when a
framing error is received, except when the maintenance bit is set. This places the processor in the halt
mode.

B, -B

1A, 2A, 3A

These three jumpers are inserted to make the 20 mA
current loop receiver active. (Jumpers 1P and 2P
must be removed when 1A, 2A, and 3A are inserted.)

1P,2P

These jumpers are inserted to make the 20 mA current loop receiver passive. (Jumpers 1A, 2A, and 3A
must be removed when 1P and 2P are installed.)

4A,5A

Inserted to make the 20 mA current loop transmitter
active. (Jumpers 3P and 4P must be removed when
4A and 5A are inserted.)

3P,4P

Inserted to make the 20 mA current loop transmitter
passive. (Jumpers 4A and 5A must be removed
when 3P and 4P are inserted.)

Jumper is removed to enable the error flags to be
read in the high byte of the receiver buffer.

M,M1

These are test jumpers used during the manufacture
of the module. They are not defined for field use.

246

DLV11-F
BDAL
BITS

R IIIIIIR

BBS7 L
° I (Ll

~ ~J

::i

ADD:ESS J:MPER:'
I NSTA LLED ° 1
REMOVED 00

o • RECEIVER

}

I • TRANSMITTER

o ° CSR

I ° DATA BUFFER

} _ _---'

o • LOW BYTE } _ _ _----'
I ° HIGH BYTE

MR-1695

RANGE ° 160000 8 - 177776 8

Figure 3

DLV11-F Addressing

SELECTED BY USER.
ASSERTED BY INTERRUPT ~
LOGIC CIRCUIT
•

I I I I

I'-

(,!)

If)

OoRECEIVER
1 ° TRANSMITTER

'>t

VECTOR JUMPERS,
INSTALLEDo 1
REMOVEDoO

CONTROLLED BY INTERRUPT
LOGIC CIRCUIT.
RANGE ° 0- 774 8
MR-1694

Figure 4

DLV11-F Interrupt Vectors

Baud Rate Selection
The DL V11-F allows the user to configure jumpers TO-T3 and RO-R3
for the transmit baud rate and the receiver baud rate as shown in
Table 3.
Data Bit Selection
The number of data bits transmitted or received by the DLV11-F is
user-selectable by installing or removing jumpers 1 and 2. The specific number of data bits as controlled by the configuration of jumpers 1
and 2 is shown in Table 4.

247

DLV11-F
Table 3
Program Control
Receive Jumpers
Transmit Jumpers

DLV11-F Baud Rate Selection
Bit
14
R2
T2

Bit
15
R3
T3

I
R
R
R
R
I

I
I
R
R
R
R
R
R
R
R

R
R
R
R

Bit
13
R1
T1

Bit
12
RO
TO

Bit
11*
Baud
Rate

I
I
R
R
I
I
R
R
I
I
R
R
I
I
R
R

I
R
I
R
I
R
I
R
I
R
I
R
I
R
I
R

50
75
110**
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

I = Jumper inserted = program bit cleared
R = Jumper removed = program bit set
* Bit 11 of the XCSR (write-only bit) must be set in order to select a new baud

rate under program controL Also, jumper PB must be inserted to enable
baud rate selection under program control.
** When configured for 110 baud, the UART is set for two stop bits.

Table 4

DLV11-F Data Bit Selection
Number of Data Bits

Jumpers

5
R

R
R

6
7

248

DLV11-F
Factory Configuration
The user can reconfigure any of the jumpers to make the module meet
his requirements. The factory configuration, as shipped, is shown in
Table 5 to assist the user in determining what changes are needed.
Table 5

DLV11-F Factory Jumper Configuration

Jumper
Designation

Jumper
State

A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

R
I
I
R

Function Implemented
Jumpers A3 through A 12 implement device address 17756X. The least significant octal digit is hardwired on the module to address the four device registers
as follows:
X =0 RCSR
0
X =2 RBUF
2
X =4XCSR
4
X = 6 XBUF

V3
V4
V5
V6
V7
V8

R
I
R
R
R

This jumper selection implements interrupt vector 60s for receiver interrupts
and 64 s for transmitter interrupts.

RO
R1
R2
R3

I
R

The module is configured to receive at
110-baud.

TO
T1
T2
T3

I
R
R
R

The transmitter is configured for 9600
baud if split speed operation is used.

Break generation is enabled.
249

DLV11-F
P

Parity bit is disabled.

Parity type is not applicable when P is
removed.

1
2

R
R

Operation with eight data bits per character.

Programmable baud rate function disabled.
Common speed operation enabled.

C
C1
S
S1

R
R

Halt on framing error enabled.

H
8
-8

800t on framing error disabled.
The 20 rnA current loop receiver is configured as an active receiver.

1A
2A
3A
1P
2P

R
R

4A
5A
3P
4P

I
I
R
R

The 20 rnA current loop transmitter is
configured for active operation.

Error flags are disabled.

EF
MT

Split speed operation disabled.

Maintenance bit disabled.
Factory test jumpers. Not defined for
field use.

M
M1

Registers
The word format for the DL V11-F RCSR is shown in Figure 5 and
functionally described in Table 6.

Figure 5

DLV11-F RCSR Word Format
250

l' - 4965

DLV11-F
Table 6 DLV11-F RCSR Bit Assignments
Bit: 15-12
Name: Not used
Description: Reserved for future use.

Bii: 11

Name: RCVR ACT
Description: (Receiver Active)
When set, this bit indicates that the DL V11-F interface receiver is active. The bit is set at the center of the start bit, which is the beginning of
the input serial data from the device and is cleared by the leading edge
of RDONE H.
Read-only bit; cleared by INIT or by RCVR DONE (bit 7).
Bit: 10-8·
Name: Not used
Description: Reserved for future use.
Bit: 7
Name: RCVR DONE
Description: (Receiver Done)
This bit is set when an entire character has been received and is ready
for transfer to the processor. When set, initiates an interrupt sequence
provided RCVR INT ENS (bit 6) is also set.
Read-only bit.
Bit: 6
Name: RCVR INT ENS
Description: (Receiver Interrupt Enable)
When set, allows an interrupt sequence to start when RCVR DONE (bit
7) sets.
Read/write bit; cleared by INIT.
Bit: 5-1
Name: Not used
Description: Reserved for future use.
Bit: a
Name: RDR ENS
Description: (Reader Enable)
When set, this bit advances the paper tape reader in DIGIT AL-modified TTY units (L T33-C, LT35-A, C) and clears the RCVR DONE bit (bit
7).
This bit is cleared at the middle of the start bit, which is the beginning
of the serial input from an external device. Also cleared by INIT.
Write-only bit.
NOTE
INIT = LSI-11 bus SINIT signal assertion.
The word format for the DLV11-F RSUF register is shown in Figure 6
and functionally described in Table 7.
251

DLV11-F
14

RESERVED

RECEIVED DATA BITS

11 - 4966

Figure 6

DLV11-F RBUF Word Format

Table 7

DLV11-F RBUF Bit Assignments

Bit: 15
Name: ERROR
Description: Used to indicate that an error condition is present. This
bit is the logical OR of OR ERR, FR ERR, and P ERR (bits 14, 13, and
12, respectively). Whenever one of these bits is set, it causes bit 15 to
set. This bit is not connected to the interrupt logic.
Read-only bit; cleared by removing the error-producing condition.

Bit: 13
Name: FR ERR
Description: (Framing Error)
When set, indicates that the character that was read had no valid stop
bit.
Read-only bit. Cleared by INIT.

Bit: 11-8
Name: Not used
Description: Reserved for future use.
Bit: 7-0
Name: RECEIVED DATA BITS
Description: Holds the character just read. If less than eight bits are
252

DLV11-F
selected, then the buffer is right-justified into the least significant bit
positions. In this case, the higher unused bit or bits are read as Os.
Read-only bits; not cleared by INIT.

NOTE
INIT = LSI-11 bus BINIT signal assertion.
Tile word format for the OL V11-F XCSR register is shown in Figure 7
and functionally described in Table 8.
14

RESERVED

RESERVED
11-4967

Figure 7

Table 8

OLV11-F XCSR Word Format

DLV11-F XCSR Bit Assignments

Bit: 15-12
Name: PBR SEL
Description: (Programmable Baud Rate Enable)
When set, these bits choose a baud rate from 50-9600 baud. See
Table 3.
Write-only bits.

Bit: 11
Name: PBR ENB
Description: (Programmable Baud Rate Enable)
This bit must be set in order to select a new baud rate indicated by bits
12to15.
Write-only bits.

Bit: 10-8
Name: Not used
Description: Reserved for future use.
Bit: 7
Name: XMIT ROY
Description: (Transmitter Ready)
This bit is set when the transmitter buffer (XBUF) can accept another
character. When set, it initiates an interrupt sequence provided XMIT
INT ENB (bit 6) is also set.
Bit: 6
Name: XMIT INT ENB
Description: (Transmitter Interrupt Enable)
When set, allows an interrupt sequence to start when XMIT ROY (bit 7)
is set.
Read/write bit; cleared by INIT. (See Note.)
253

DLV11-F
Name: Not used
Bit: 5-3
Description: Reserved for future use.
Bit: 2
Name: MAINT
Description: Used for maintenance function. When set, connects the
transmitter serial output to the receiver serial input while disconnecting the external device from the receiver serial input. It also forces the
receiver to run at transmitter baud rate speed when common speed
operation is enabled.
Read/write bit; cleared by INIT.

Bit: 1
Name: Not used
Description: Reserved for future use.
Bit: 0
Name: BREAK
Description: When set, transmits a continuous space to the external
device.
Read/write bit; cleared by INIT.

NOTE
When clearing an interrupt enable bit, first set the
appropriate processor status word bit = 1. After the
interrupt enable bit at the module is cleared, the
processor may be returned to its normal priority.
The word format for the DLV11-F XBUF register is shown in Figure 8
and functionally described in Table 9.
os

07
TRANSMITTER DATA BUFFER

RESERVED

Figure 8

Table 9

DLV11-F XBUF Word Format

11-5155

DLV11-F XBUF Bit Assignments

Name: Not Used
Bit: 15-8
Description: Not defined. Not necessarily read as Os.
Name: TRANSMITTER DATA BUFFER
Bit: 7-0
Description: Holds the character to be transferred to the external
device. If fewer than eight bits are used, the character must be loaded
so it is right-justified into the least significant bits.
Write-only bits. Not necessarily read as Os.
254

DLV11-F
Installation
Before installing the DL V11-F on the backplane, first establish the
desired priority level to determine in which backplane slot to install the
module. Then ensure that the module configuration jumpers are configured correctly fOi your appiication. Connection to the peripheral
device is via an optional data interface cable. Cables are listed below.
Application
EIA Interface
20 mA Current Loop

Cable Type*
BC01V-X or BCOSC-X Modem Cable
BCOSM-X Cable Assembly

Interfacing EIA-Cornpatible Devices
The DLV11-F supports only the data leads of EIA-compatible devices.
It uses a BCOSC modem cable to interface devices such as the Teletype® Model 37 Teletypewriter and the Bell Data Set Model 103 (in
auto mode). The DLV11-F's EIA "data leads only" interface circuit is
shown in Figure 9 and the jumpers are shown in Table 5.
*

x = Length in feet. Standard length is 25 feet.

Teletype is a registered trademark of Teletype Corporation.
seal v-x 0' se05C

DLV11-F

MODEM CASLE
A

r:-7.
1

I
I FORCE BUSY

DD)

I
I DATA TERMINAL READY..

t:!
I

REQUEST TO SEND

)
B--c>f
I

I TRANSMITTED DATA
F . I
..

XBUF

~ J)

I RECEIVED DATA

•

:, "~m """'''"

~ ,~

11- 4932

Figure 9

EIA Data Leads Only Interface

Interfacing 20 rnA Current Loop Devices with the DLV11-F
When interfacing with 20 mA current loop devices, the BCOSM cable
assembly provides the correct connections to the 40-pin connector on
the DLV11-F. The peripheral device end of the cable is terminated with
2SS

DLV11-F
a Mate-N-Lok connector that is pin-compatible with all DIGITAL 20 mA
serial interface terminals.
The interface circuits provided by the BC05M cable and the associated DLV11-F jumpers are shown in Figures 9,10,11, and 12.
NOTE
When the DL V11-F is used with teletypewriter devices, a 0.005J.LF capacitor must be installed (see
DLVll-F
BC05MCABLE
Figure 1).
~

"
+5V

+12V

PART OF
ACTIVE
TRANSMITTER

14Al

Jl
0---7
AA )

' - . : > £ - - - - - - - 0 -.......

SERIAL
OUT 1+1
..

131'\
\
I
I

I
I
I

SWITCHING
CIRCUIT
XBUF

I
I

TRANSMIT
DATA

L -______~ __~~I

\
\14P1

r -_ _ _~:>-15A-lo__~ KK

SERIAL
OUT I-I

PART OF
ACTIVE
TRANSMITTER

Ion-:

+SV

1. Insert solid-line jumpers,
4A and 5a, to oonfigure
for active transmitter.
2. Insert- dotted-l1ne jumpers
to maintain compatibility
with DLV11 when configuri-ng for passive transmitter.

DATOOH
RCSR
REGISTER SELECT

BIT 0
READER
RUN
RELAY DRIVER

pp)

READER
RUN 1+1

RCVR
BUSYH

RECEIVER
ACTIVE
CIRCUIT

110
CONTROL
LOGIC

EE)

"Z'V

Figure 10

20 rnA Transmitter and Reader Run Circuits

256

READER
RUN I-I

•

11 4~X~

DLV11-F
+5V

+12V

i'--l
~2~-~< ~-r:fu~
T I
.. <----II

v,vwF'

FOR TTY
ONLY

r-~
~

(2A)

'-------

K .r-r- (+)

I SERIAL DATA IN

[

(3A)

~S>-r-(-)

.,}, [ [
~

20mA RECEIVED DATA

:n
I

------''-'--.::..:..::'--'-.::=....::-'-'-'-'-'-----'-:-}) H

20mA INTERLOCK

TTL SERIAL DATA IN
E

11-4934

Figure 11

Active Receive 20 rnA Current Loop_

+5V

(1P) J1

,---0--<:-,.-7

K:r,-- (+)
I

I
I SERIAL DATA IN

C29
O.005/L F

(2P)

FOR TTY
ONLY

'---0--<:>---+-7 S

>-+- (-)
I
I
[

20mA/TTl RECEIVED DATA

I
RBUF

TTL SERIAL DATA IN

::n".,

,,,"CO,,
!1-493!5

Figure 12

Passive Receive 20 rnA Current Loop

257

DLV11-J
DLV11·J FOUR·CHANNEL ASYNCHRONOUS
SERIAL INTERFACE
INTRODUCTION
The DL V11-J is a 4-channel asynchronous serial line unit used to
interface peripheral equipment to an LSI-11 bus. The interface transmits and receives data from the peripheral device over Electronics
Industry Association (EIA) "data leads only" lines which do not use
control lines. The module can be used with 20 rnA current loop devices (with "reader-run" capabilities) when the DLV11-KA option is
installed. With a DLV11-J interface, the processor can communicate
with a local terminal such as a console teleprinter, a remote terminal
via data sets and private line, or another local or remote processor.
FEATURES
• Four independent, full-duplex, asynchronous serial line interfaces to
the LSI-11 bus on one double-height module.
• Each channel independently configured for:
1. EIA RS-232C, RS-422, RS-423
2. Baud Rates: 150, 300, BOO, 1200, 2400, 4800, 9BOO, 19.2K, 38.4K
and external
3.

Variable character format:
7 or 8 data bits;
1 or 2 stop bits;
odd, even,or no parity

Support for data leads only: MODEMS (Bell type: 103, 113)

• One channel configurable as computer console device interface,
including halt or boot on received break.
• 8.9 in x 5.2 in (22.8cm X 13.2cm) module
• 20 rnA current loop and 110 baud capability optionally added using
the EIA to 20 rnA converter (DLV11-KA).
• The DLV11-KA provides:
1. Single line EIA to 20 rnA converter unit and 3 ft. (.91 m) cable for
connection to DLV11-J.
2.
3.

A program-controlled, reader advance function for DIGITALmodified ASR33 teletypes.
A 110 baud rate generator.

4.
5.

Choice of active or passive operation.
Operation up to 9BOO baud.

Cable drive capability up to 4000 feet.
258

DLV11-J
SPECIFICATIONS
Identification

MB043

Size

Double

Power

+5 V ±5% at 1.0 A
+12 V ±3% at 0.25 A

Bus Loading
AC

DESCRIPTION
The DL V11-J module is designed to interface peripheral devices that
transmit and receive asynchronous serial data over EIA-compatible
data lines or 20 rnA current loops to the parallel LSI-11 bus. When
configured, the module transmits and receives the specified EIA signal
levels on the receive and transmit data lines of the cable. Also, the
module constantly asserts the data-terminal-ready signal.

When configured for 20 rnA current loop operation (DLV11-KA option
installed), the DL V11-J can support devices which contain programcontrolled paper tape readers (such as DIGITAL's LT33 Teletypewriters or the ASR33 Teletypewriter with the LT33 modification kit.)
During operation, the module is required to convert data from parallel
to serial and serial to parallel. To accomplish this, a universal asynchronous receiver/transmitter (UART) is employed. When performing
this conversion, the UART must also alter the speed and character
format for the data (to meet user-selected parameters). In addition,
the UART creates error bits to allow the programmer to check data
transmission for errors. A block diagram of the DL V11-J module is
shown in Figure 1.

UART Operation
The DL V11-J module is equipped with four universal asynchronous
receiver/transmitters, one for each channel. The UART chip is capable
of parallel data transfers with the computer and serial data transfers
with the peripheral device. User-selectable jumpers determine the
character format used during transmission. The jumpers select:

7 or B data bits
1 or 2 stop bits
Parity or no parity
Even or odd parity
259

BOOUT

-I

-: :T
(1)

DATA ROUTE:. GA riNG BD DIN 80 DOUT

BDIN

::T
(1)

.....

BSYNC

BRPLY

:::J

CJ)

o
3 -0

CJ)

.....

(1)
p)

:::J

.....

0
_. .(1)

CJ)

(1)

<C .....
c:
-0
::T_

SDAL 11
BDAll0
BOAL9

(1)

BOALS

(")

o·
:::J

JJ-o

-0

CD)

=l.

[D(1)
Jl

"T1!:!:
. 0
:::J

0')

(1)

o.....
3CJ)

:::r

0'"(1)

CJ)

BOALlS
BOAl14
BOAL 13
BOAL 12
BOAL 7

(1)

.....

ii).

:::r

BOAl6
BOAL S

.....

BDAL4
BOAl3
BOAL ~
BOAll
BOM 0
BBS 7

:::J

--0

(1)

::Tp)
(1) .....
p)

(1)
(")

V5 V7
MODULE BASE
VECTOR
JUMPERS

:::J

<
.....
CJ)
(1)

.!."

1----- TO I/O CONTROL

0'"

o·
:::J

-:::: o

(1)

.....
p)

Figure 1

DL V11-J Block Diagram (Sheet 1 of 2)

.....

-I p)
::T
(1) p )

<
....
....•

C'..

vI:CTOf-l

GENl RAllON
LOGIC
.)2

BDCDK

FE3

tlHALT

OSCILLATOR

J3
M

GND
GND
GND

GND
GND
GND
'5V
'5 v
1·5 V
-112 V

IAC21
IAJII
,IAMII
IAlll
IBJII
IBMII
IBTlI
IBC2I
IAl2I
IAA2I
IBVII
IBA2I
IAD2I

MASTfR eLK

<
.....
.....
I

L.
GND
'5 V
12 V

CHARGE
PUMP

~12 V

UAUD
RATE

GENERATOR

CHARACTER
FO!1MAT
JUMPERS

112F

D, Eo, P, S

NOTES
DETAILED SCHEMATICS MAY BE ORDERED
USING PRINT SET ORDER NUMBER MP00586.

CD JUMPER ALWAYS INSTALLED.
REMOVED DURING FACTORY TEST,

r-----------~-JClKO
BAUD RATE

BAUD RATE OUTPU rs

JUMPERS
~

Figure 1

_ _ _ _ _ _ _ _ _ __ J - -

DLV11-J Block Diagram (Sheet 2 of 2)

ClK I
ClK 2
ClK3

DLV11-J
The transmitter performs parallel to serial conversion of data provided
by the LSI-11 bus. The character length, stop bit code, parity, and
baud rate are identical to the receiver section of the SLU channel. The
transmitter, however, appends the proper start, stop, and parity bits to
the data before transmission.
Baud Rate Generator
The baud rate control circuit generates clock signals that control the
speed at which the receive buffer (RBUF) and the transmit buffer
(XBUF) move serial data. The circuit provides a command clock to
both buffers of the channel.

The speed at which a channel will operate is configured by the selection of wire-wrap jumpers which supply the desired baud rate clock.
The clock is developed by a crystal-controlled oscillator driving a frequency division chip. The outputs of the frequency division chip are
connected to wire-wrap posts which may be selected when configuring the channel(s). If more than one channel is used for a particular
baud rate, the clock may be daisy-chained between channels.
When 110 baud operation is desired, the DLV11-KA option must be
used. This option provides the 110 clock to the channel via the peripheral device cable; no baud rate jumper may be configured on the
module for the 110 baud channel.

I/O Control Logic
The 1/0 control logic directs data transfers between the computer and
the DLV11-J module. The logic monitors the LSI-11 bus control lines
to determine the type of data transfer to be executed (from the LSI-11
bus to the register logic for an output operation or from the register
logic to the LSI-11 bus for an input operation). The following LSI-11
bus control lines are monitored by the 1/0 control logic during the
operation:
BSYNC

Bus Synchronized. Set when valid address has been
placed on LSI-11 bus.

BDIN

Bus Data Input. Set when processor is ready to
receive input data.

BDOUT

Bus Data Output. Set when processor is ready to
transmit output data.

The module asserts the BRPL Y (reply from module) bus control line
when the data transfer has been completed.

262

DLV11-J
During operation, the module receives the BSYNC signal indicating an
address has been placed onto the LSI-11 bus. The I/O control logic
gates this address into the address latch of the module with a SYNC H
gating signal. If the address received is a bus device address on the
DLV11-J, the address latch sends a BD SEL signal to the I/O control
logic (indicating a valid address has been received). The control logic
may now develop the proper gating signals (BDOUT /BDIN) to move
the data to its proper destination. When the data transfer is complete,
the module signals the processor via the BRPL Y control line.
Address Latch
The address latch is used to hold the channel address (0-3), the device
register address (RCSR, RBUF, XCSR, or XBUF), and the high-low
byte indicator of the pending operation. When the program addresses
the DL V11-J module, address bits 0-4 are presented to the address
latch by the bus interface circuit over the internal tri-state data bus.
Simultaneously, the address compare circuit and the bus interface
circuit supply the address latGh with the MATCH H signal and are
gated into the latch under the control of the I/O control logic circuit
(SYNC H signal). The address latch now holds the address and a
board select signal (BD SEL 1) to be used by the I/O control/register
logic during the completion of the desired operation.
Address Compare Circuit
The address compare circuit tests the user-configured base address
of the module (wire-wrap jumpers A5, A8-12) against the LSI-11 bus
input (BDAL 5, 8-12 L). If the addresses are same, the address compare circuit generates a portion of the MATCH H signal. (The remainder of MATCH H is supplied by the bus interface.) The MATCH H
signal is used by the address latch circuit when creating the BD SEL H
signal required by the I/O control logiC during data transfers.
When channel 3 is configured as a console device interface, the bus
interface logic tests for a proper console device address on the LSI-11
bus. If the address received by the bus interface is a proper console
address, the CON SEL 1 H signal is generated. This signal is transmitted from the bus interface to the address compare circuit to force
console address recognition.
Bus Interface
The module contains bus drivers and receivers which interface directly with the LSI-11 bus. This allows data movement between the LSI-11
bus and the module's internal tri-state bus. These drivers also have
263

DLV11-J
the ability to transmit vector addresses received from the interrupt
vector generation logic onto the LSI-11 bus.
If the LSI-11 bus holds an address within the I/O page, the BBS7 L
signal line is asserted. This will cause the bus interface circuit of the
DLV11-J to test the BDAL 6-7 L lines against the user-configured wirewrap pins (A6-7) when the addresses and the same MATCH H signal
are allowed to be asserted to the address latch. Since this is a "wiredAND," the MATCH H Signal from the address compare signal must
also be asserted. The MATCH H signal is required by the address latch
to allow I/O data transfers. If channel 3 has been selected as a console
device interface (jumpers C1 and C2 installed between wire-wrap
posts X and 1), the bus interface performs a match operation between
the LSI-11 bus lines (BDAL 3-5) and an internal address which is
enabled by console select jumper C1. If the addresses agree, a CON
SEL 1 H signal is produced for the address compare circuit which will
force a console address recognition.
Interrupt and Vector Generation Logic
When a peripheral device interfaced to a DLV11-J needs service, the
module can, if enabled, interrupt the computer program and vector to
a service routine. The interrupt logic can initiate two types of interrupts: a receiver interrupt and a transmitter interrupt. These interrupts
are handled through separate receiver and transmitter channels.

For an interrupt transaction to occur, the program must set the interrupt enable bit (bit 6) in the control/status register (CSR). Next, the
interrupt logic must recognize a condition requiring service (indicated
by the setting of bit 7 within the CSR) and then assert the interrupt
request line (BIRO L) on the LSI-11 bus. When the interrupt is acknowledged by the processor, the interrupt logic creates an input to
the module's vector generation circuit which reflects the channel
needing service (0, 1, 2, or 3) and the type of service needed (receive
or transmit). The vector generation logic creates a vector function
address which may be modified by the user-configured "base vector"
address jumpers (V5-7). This modified address is output to the LSI-11
bus by the bus interface circuit, thus causing the processor to jump to
the proper peripheral device service routine.
A receiver interrupt request is initiated when the receive buffer (RBUF)
has received and assembled a character of data and is ready to transfer it to the processor. A transmitter interrupt is initiated when the
transmitter buffer holding -register (XBUF) is empty and is ready for
another data input from the processor. The interrupt logic is also used
264

DLV11-J
to initialize the DLV11-J module. On a system power-up sequence, the
processor creates BINIT L on the LSI-11 bus which is converted by the
interrupt logic into INITO H. This signal is distributed on the module to
initialize the four UARTs and the interrupt status registers (held within
the interrupt logic).
Control/Status Registers
The control/status registers (CSRs) consist of a series of latches, data
selectors, and gating circuitry. During data transactions, the 1/0 control logic enables the XCSR or RCSR to either latch in control bits or
gate out status bits.
The RCSR uses only three bits during operation:
Receiver done (bit 7), set by RBUF
Receiver interrupt enable (bit 6), set by program
Reader enable (bit 0), set by program
All bits except the reader enable bit may be read by the program.
The XCSR uses three bits during operation:
Transmitter ready (bit 7), set by XBUF
Transmitter interrupt enable (bit 6), set by program
Break (bit 0), set by program and used only with the
DLV11-KA option
All bits may be read by the program.
Break Logic
During normal operation, the UART checks each received character
for the proper number of stop bits. It does this by testing for a marking
condition at the appropriate bit time. If it finds a spacing condition
instead, it sets the framing error (FE) flag. The BREAK signal is a
continuous spacing condition, and is interpreted by the UART as a
data character that is missing its stop bit(s). The UART, therefore,
responds to the BREAK signal by asserting FE H. If the channel 3
break response jumper is installed from X to B, FE H will negate
control fine BDCOK H; BDCOK H indicates to the processor that dc
power is "OK." When FE H negates this signal, it causes the computer
to restart at the bootstrap (provided proper processor power-up mode
is selected).
If the break jumper is installed from X to H, the computer will not
"boot" ona framing error, but FE H will negate control line BHAL T L.
This causes the computer to halt when a framing error is received.

265

DLV11-J
CAUTION
If the system is using MOS memory, data may be lost when SDCOK
is negated because this action interrupts the memory refresh cycle.
If the jumper is not installed, the module will not take action.

Peripheral Interface
Each SLU channel of the DLV11-J module can be independently configured for line signal compatibility with EIA RS-232C and RS-423, RS422, or 20 mA current loop operation (Figure 2). Each of the four
interfaces may be configured to support 20 mA current loop devices
with the addition of the DLV11-KA option. When installed, the peripheral interface supplies all power supply voltages needed by this
option. If the 20 mA device contains a paper tape reader that can be
program-controlled (such as DIGITAL's LT33 or an ASR33 Teletypewriter with LT33 modification kit), the interface can be configured
to advance the reader one character at a time.

RECEIVER INTERFACE
RCV
DATA

TRANSMITTER INTERFACE

0
t-

w
Z
Z

NO-3

u..

PERIPHERAL
DEVICE

....J

a:
w

READ RUN PULSE

CLK

ClK

+12 VDC

L-_

w
"-

+12 F

_ _ _ ..J

NOTES

CD RX IS INSTALLED WHEN CHANNEL IS

@Ry IS CHOSEN FOR PROPER SLEW RATE
WHEN CHANNE L IS CONFIGURED FOR
E IA RS232C/RS-423 OPE RATION
R10 SETS SLEW RATE FOR CHANNE LS 0
AND 1
R23 SETS SLEW RATE FOR CHANNE IS 2
AND 3

CONFIGURED FOR EIA RS-422 OPERATION
(loon, 1/4 W NON-WIRE WOUND)
R30 - CHANNEL 0
R31 - CHANNEL 1
R32 - CHANNEL 2
R33 - CHANNEL 3

Figure 2

Typical Peripheral Interface

266

DLV11-J
OCto-DC Power Converter
The power converter produces - 12 Vdc and + 5 Vdc from the LSI-11
power supply voltage of + 12 Vdc. These voltages are produced to
power a!! chips on the DLV11-J module and to supply the DLV11-KA 20
rnA option. The power converter circuit consists of a crystal-controlled
oscillator which drives a charge pump. The charge pump during operation supplies the desired power supply output voltage.

CONFIGURATION
The DLV11-J device and vector addressing, serial word formats, baud
rates, interface, type, etc., are selected by installing and/or removing
jumpers. Wire-wrap posts are provided on the module for this purpose.
The module is factory-configured and ready to use in most user applications. However, if a system requires different device register addresses and interrupt vectors or operations, the module may be reconfigured. The DLV11-J module is factory-configured for the following
operations:
• Base address = 176500
• Base vector address = 300
• Channel 3 enabled as the console device (device addresses
177560-177566 and vector addresses 60 and 64).
• Channel 3 halt on break enabled
• Baud rates (transmit and receive are identical):
Channels 0,1 and 2 = 9.6K baud
Channel 3 = 300 baud
• Data/parity/stop bit format (all channels):
Eight data bits
One stop bit
No parity
• Serial line signal interface levels (all channels) compatible with both
EIA RS-232C and RS-423, simultaneously (slew rate = 2 JLs)
Figure 3 gives jumper and pad locations on the DLV11-J module and
Table 1 gives a summary of the module's factory configuration.

267

DLV11-J

CHO AND

CH1 EIA{
SE LECTION

2 '_
3 R
MO _
NO _ _ e
M1 _ _
N1- - -

l!~P}::'AH
2

R10
CHO~
D __

E'"

CHO{

SELECTION

3~N
-LUT
e

CH1 TERM RESISTOR
CHO TERM RESISTOR
CH2 TERM RESISTOR
CH3 TERM RESISTOR

P-E'"
P_P_P-S ....
CH1

D __

CH1{
COMMUNICATION
LINE
PARAMETERS

S'"

CH2
D _'_
E
"

CH2{

S ....
CH3

D
_
E_
.......

CH3{

S ....

ADDRESS AND
VECTOR JUMPERS

A5 ........

AS .......
A12
__
A10 _ _
All _ _

~{~~::
--......

BXH
'---v--'

C1-V5 ........

BREAK SELECTION
ICHANNE L 3)

o1X

Figure 3

V6V7_

AS-C2 _ _

DL V11-J Jumper Locations

268

-M2

M3
- -_ _
eN2
_ _ _ N3

}

CH2 AND
CH3EIA
SE LECTION

DLV11-J
Table 1

Labei

Factory Jumper Configuration

Standard
Coniiguraiion

Function Implemented

A12
A11
A10
A9
A8
A7
A6
A5

Xto 0

C1
C2

X to 1
X to 1

These jumpers are used to enable
channel 3 for console operation. Base
address must be 176500 (factoryconfigured), 176540, or 177500 for the
console.

(Break
response)

Xto H

This jumper determines channel 3
break response. The board is configured for halt (console emulator mode)
on break condition.

Xto 1
X to 1
X to 1
Xto 0
Xto 1
R

V7
V6
V5

XtoO*

E
D
S
P

XtoO
Xto 1
XtoO
Xto 1

This arrangement of jumpers A5-A 12
implements the octal base device address 1765XX, which is the assigned
address for channel 0 RCSR. The
least significant digit is decoded on
the module during operation to address one of four SLU device registers as follows:
X = 0, RCSR
X = 2, RBUF
X = 4,XCSR
X = 6,XBUF

This arrangement of jumpers V5-V7
implements the octal "base" vector of
300 with channel 3 at 60 and 64.
Odd parity
8 data bits
1 stop bit
Parity inhibited
These jumpers determine the word
format used by the channel. All channels are configured the same at the
factory.

269

DLV11-J
Table 1

Factory Jumper Configuration (Cont)

Label

Standard
Configuration

0
1
2
3

OtoN
1 to N
2to N
3toT

9.6K baud
9.6K baud
9.6K baud
300 baud
These jumpers determine the baud
rate of the serial line channel for same
baud rate daisy-chain wire-wraps.

NO-3
MO-3

Xt03
Xt03

These jumpers determine the EIA
standard compatibility of the channel.
All channels are set at the factory to
be compatible to both EIA RS-423
and RS-232C simultaneously.

R10

22KQ

Channels 0 and 1, slew rate of 2 J,LS
(used when configured for EIA RS-

Function Implemented

423/RS-232C).

R23

22KQ

Channels 2 and 3, slew rate of 2 J,LS
(used when configured for EIA RS423/RS232C).

* See Interrupt Vector Format figure.

Device Registers- The DLV11-J contains 16 device registers that can
be individually addressed by the program. The four device registers
provided for each of the SLU channels (0 through 3) are:
Receive Control/Status Registers (RCSR)
Receive Buffer (RBUF)
Transmit Control/Status Register (XCSR)
Transmit Buffer (XBUF)
Wire-wrap jumpers are configured to establish the base address (BA)
for the module. This base address is the channel 0 RCSR address. The
device address format is shown. in Figure 4. The remaining device
addresses follow through 16 (total) contiguous word addresses; however, it is possible to independently dedicate the last four addresses
(channel 3) to a console device. When configured for console device
operation, the channel's device register addresses will be 177560270

DLV11-J
177566. For console operation, the board's base address must be one
of the following:
176500 (factory-configured)
176540
177500
The floating address configurations are listed in Table 2 and the fact0ry or standard configuration addresses are listed in Table 3.
17

: A12\ All : A10 : A9

\ AB

: A7

: A6

\ A5

BANK 7
SELECTED III
FACTORY
CONFIGUREO _
BASE ADDRESS

jllllllj
1

•

3 WIRE WRAP POSTS
IX, 1, O} ARE
PROVIDED FOR
EACH BIT.

2 WIRE WRAP
POSTS ARE
PROVIDED FOR
EACH BIT.

JUMPER X TO 1 = 1
JUMPER X TO 0= 0
NOTE:
lANGE 1600008 -1777708 NONEXTENDED ADDRESS
7600008 -777770 8 EXTENOED ADDRESS

JUMPER IN = 1
JUMPER OUT = 0

~~yJE
~~~~l~~E} ,SELEf

P,OINTER

00 = RCSR
01 = RBUF

'------v-----'J~'___.r__'
v

= 176500

-----.J1,-_--"-_-.10
11 =
= XCSR
XBUF

DO = CHANNEL 0
01 = CHANNEL 1
10 = CHANNEL 2
11 = CHANNEL 3

MR·0893

Figure 4

Table 2

Address

Channel 0 RCSR Address Format

Address Assignments (with Console Selected)
Device
Register

Associated
Vector

Channel 0
Module Base Vector
(BV)

RCSR

Module Base
Address (BA)
BA+2
BA+4
BA+6

RBUF
XCSR
XBUF

BA+10
BA+12
BA+14
BA+16

RCSR
RBUF
XCSR
XBUF

BV+4

Channel 1
BV+10
BV+14

271

DLV11-J
Table 2

Address Assignments (with Console Selected) (Cont)

Address

Device
Register

BA+20
BA+22
BA+24
BA+26

RCSR
RBUF
XCSR
XBUF

Associated
Vector

Channel 2

BV+20
BV+24
Channel 3*

RCSR
RBUF
XCSR
XBUF

177560
177562
177564
177566
*

Console
Selected

60
64

Channel 3 is used as a console device.

Table 3

Factory or Standard Addresses

Address

176500
176502
176504
176506

RCSR
RBUF
XCSR
XBUF

176510
176512
176514
176516

RCSR
RBUF
XCSR
XBUF

176520
176522
176524
176526

RCSR
RBUF
XCSR
XBUF

177560
177562
177564
177566

RCSR
RBUF
XCSR
XBUF

Vector

300
Channel 0
304
310
Channel 1
314
320
Channel 2
324
60
Channel 3
64
272

DLV11-J
Four word formats, one for each device register within a channel, are
shown in Figure 5 and described in Table 4. These word formats are
typical of all channels on the DLV11-J module.

RCSR

I o I

05
0

I
I

RECE\VER
DONE
(READ ONLY)

READER
ENABLE
(WRITE ONLY)
ON READ=O

RECEIVER
INTERRUPT
ENABLE
(READIWRITE)

RBUF
~------v-------J"L-------------__~--------------~
FRAMING
ERROR
NOT USED
RECEIVE DATA
(READ
(7,8 BIT DATA IS RIGHT JUSTIFIED.)
ONLY)
IF BIT UNUSED = 0
OVERRUN
PARITY
ERROR
ERROR
(READ
(READ
ONLY)
ONLY)

ERROR
(READ
ONLY)

XCSR

TRANSMIT BREAK
(R EADIW RITE)

TRANSMIT
READY
(READ ONLY)
TRANSMIT
INTERRUPT
ENABLE
(READIWRITE)

XBUF I

I 0

13
:

1 0

10
:

(NOT USED)

TRANSMIT DATA

(7,8 BIT DATA IS RIGHT JUSTIFIED.)
NOTE
ONEOFFOURCHANNELSSHOWN.
FORMAT THE SAME FOR ALL CHANNELS.

(WRITE ONLY) ON READ = 0

MR 0901

Figure 5

DL V11-J Device Register Formats

273

DLV11-J
Table 4

DLV11-J Word Formats

Receiver Control/Status Register
Bit: 8-15
Description:

Not used. Read as O.

Bit: 7
Description: Receiver Done. Set when an entire character has been
received and is ready for input to the processor. This bit is automatically cleared when RBUF is read, when BINIT L signal goes true (low),
or when reader enable bit is set. Read-only bit.
If Receiver Interrupt (bit 6) is set, the setting of Receiver Done starts an
interrupt sequence.

Bit: 6
Description: Receive Interrupt Enable. Set under program control
when it is desired to generate a receiver interrupt request (when a
character is ready for input to the processor signified by bit 7 being
set). Cleared under program control or by the BINIT signal. Read/write
bit.
Bit: 1-5
Description:

Not used. Read as O.

Bit: 0
Description: Reader Enable. Setting this bit advances the paper
tape reader on an L T33 terminal one character at a time. Setting of this
bit clears Receiver Done (bit 7). Write-only bit.
The DLV11-KA 20 rnA current loop option is required for operation of
this bit.

Receiver Buffer
Bit: 15
Description: Channel Error Status. Logical OR of bits 14, 13, and 12.
Read-only bit.
Bit: 14
Description: Overrun Error. When set, indicates that the reading of
the previously received character was not completed (Receiver Done
not cleared) prior to receiving a new character.
Cleared by BINIT signal. Read-only bit.

274

DLV11-J
NOTE
When "back-to-back" characters are received, one
full character time is allowed from the time instant
receiver done (bit 7) is set to the occurrence of an
overrun error.

Bit: 13
Description: Framing Error. When set, indicates that the character
read had no valid stop bit.
Cleared by BINIT signal. Read-only bit.

Bit: 12
Description: Parity Error. When set, indicates that the parity received does not agree with the expected parity. This bit is always 0 if
no-parity operation is configured for the channel. Read-only bit.

NOTE
Error bits remain valid until the next character is received, at which time the error bits are updated.

Bit: 8-11
Description:

Not used. Read as O.

Bit: 0-7
Description: Data bits. Contains seven or eight data bits in a rightjustified format. Bit 7 = 0 when 7 data bits are enabled. Read-only bits.
Transmitter Control/Status Register
Bit: 8-15
Description:

Not used. Read as o.

Bit: 7
Description: Transmit Ready. Set when XBUF is empty and can accept another character for transmission. It is also set by INIT during
the power-up sequence or during a reset instruction. Read-only bit.
If Transmitter Interrupt Enable (bit 6) is set, the setting of Transmit
Ready will start an interrupt sequence.

Bit: 6
Description: Transmit Interrupt Enable. Set under program control
when it is desired to generate a transmitter interrupt request (when
transmitter is ready to accept a character for transmission).
The bit is cleared under program control, during power-up sequence,
or reset instruction. Read/write bit.

275

DLV11-J
Bit: 1-5
Description:

Not used. Read as O.

Bit: a
Description: Transmit Break. Set or reset under program control.
When set, a continuous space level is transmitted. However,Transmit
Done and Transmit interrupt can still operate, allowing software timing
of break. When not set, normal character transmission can occur.
Cleared by BINIT. Read/write bit.

Transmit Buffer
Bit: 8-15
Description:

Not used. Read as O.

Bit: 0-7
Description: Data bits. Contains seven or eight right-justified data
bits. Loaded under program control for serial transmission.
Interrupt Vectors
Two interrupt vectors are provided for each of the four SLU channels
(eight vectors total). The procedure for configuring the vectors is similar to that used when configuring the base device register address; the
configured base vector is the channel a receiver interrupt vector. Each
interrupt vector references two word locations in memory (the
Program Counter address and the Processor Status Word). Hence,
sequential vectors appear in increments of four.
The module is factory-configured with an interrupt vector base of 300.
However, it is also configured for channel 3 operation as the console
device; thus, channel 3 will automatically have interrupt vectors of 60
and 64. The vector format is shown in Figure 6 and a summary of
vector jumper configurations is provided in Table 5. Table 6 gives a list
of the factory-configured vector assignments.
Interrupt priority within the DLV11-J module is structured as follows:

Interrupt Priority
1 (highest)
2
3
4
5
6
7
8 (lowest)

Requesting Function
Channel 0, receiver
Channel 1, receiver
Channel 2, receiver
Channel 3, receiver
Channel 0, transmitter
Channel 1, transmitter
Channel 2, transmitter
Channel 3, transmitter

276

DLV11-J

FACTORY-CONFIGURED
BASE INTERRUPT VECTOR
ADDRESS = 300
TWOWIREWRAP
POSTS ARE PROVIDED
FOR EACH BIT.
JUMPER IN = 1
JUMPE ROUT = 0

hIll
1

INTERRUPT

10-3)

1 = TRANSMITTER
INTERRUPT

'--v---'

THREE WIRE WRAP
POSTS ,\RE PROVIDED
FOR BIT V5.
JUMPE R X TO 1 = 1
JUMPER X TO 0 = 0 WITH CONSOLE
NO JUMPE R = 0 WITHOUT CONSO LE

NOTE:
RANGE 0-377 8 1040 8 NOT ALLOWED IN CONSOLE MODEl

Figure 6

Table 5

Interrupt Vector Format

Summary of Vector Jumper Configurations

Label

Logical 1

Logical 0

V7
V6

Jumper installed.
Jumper installed.
Jumper installed from
wire-wrap post X to 1.

Jumper removed.
Jumper removed.
Console not selected:
jumper removed.
Console selected:
jumper.
installed from wire-wrap
post X to o.

277

DLV11-J
Table 6

Vector Assignments (with Console Selected)
(Factory Configured)

Standard Address

Interrupt Vector

300 [Module Base
Vector (BV))
304 (BV+4)
310 (BV+10)
314 (BV+14)
320 (BV+20)
324 (BV+24)

Channel 0, Receiver
Channel 0, Transmitter
Channel 1, Receiver
Channel 1, Transmitter
Channel 2, Receiver
Channel 2, Transmitter

60
64

Console Selected

Channel 3, Receiver
Channel 3, Transmitter

NOTES
1. Module is factory-configured for channel 3 as a console device.
2. All addresses are in octal notation.
Character Formats
Each of the four channels may be independently configured for various character formats. When a character format is configured (by
wire-wrap jumpers) for a channel, both the transmitter and receiver
will use the same format. The character may contain:
7 or 8 data bits
1 or 2 stop bits
Parity or no parity
Even or odd parity
Configuration instructions for determining the character formats of
each channel are shown in Table 7.

Baud Rates
Each channel can be configured for baud rates ranging from 150 to
38,400 bits per second. One baud rate clock input wire-wrap pin is
provided for each channel (0 through 3). Both the transmitter and
receiver for a given channel must operate at the same baud rate; split
baud rate operation cannot be configured. Configure baud rates by
connecting a jumper from the appropriate baud rate generator output
wire-wrap pin to the clock input pin of the channel. One jumper is
278

DLV11-J
required for each channel. When configuring the same baud rate for
more than one channel, the wire-wrap pins may be daisy-chained.
Table 8 lists the possible baud rates for each channel and their associated labels.
Table 7

Character Format Jumpers

Channel
Parameter

Wire-wrap
XtoO

Connection
Xto1

Comments

No. of data
bits

7 bits

8 bits

LSB transm itted fi rst

No. of stop
bits

1 bit

2 bits

Parity inhibit

Parity generation and
detection
enabled

Parity bit
deleted;
parity error
=0

Even parity
enabled

Odd parity
expected

Even parity
expected

Label

Table 8

Onlywhen P
=0

Baud Rate Generator Outputs

Wire-Wrap
Pin Label

Baud Rate
(Bits/Second)

150

300

600

1,200

2,400

4,800

9,600

19,200

38,400

When using the DLV11-KA option, 110 bits/sec operation is possible.
A 110 baud rate clock generator circuit on the option will supply the
DLV11-J module with the proper clock; no baud rate jumper is configured on the module for the desired channel.
279

DLV11-J
.Console Device Selection
Channel 3 of the DLV11-J module may be independently dedicated for
console device operation. To accomplish this, the console select
jumpers must be properly configured. Table 9 gives channel 3 configuration instructions. When configured for console operation, the device addresses are 177560-177566 and the interrupt vectors are 60
and 64.
Table 9

Summary of Console Selection Jumper Configurations

Label

Console Selected

Console Not Selected

Install jumper from wirewrap pins X to 1.

Install jumper from wirewrap pins X to O.

Install jumper from wirewrap pins X to 1.

Install jumper from wirewrap pins X to O.

Break Response
Channel 3 may be configured to either bootstrap, halt (console emulator mode), or have no response to a receive break condition. A bootstrap operation upon a receive break condition will cause the
processor to execute the bootstrap program starting at the memory
location defined by the power-up mode jumpers of the processor. A
halt operation upon a receive break condition will cause the processor
to halt and the console octal debugging technique (ODT) microcode to
be invoked. Configuration instructions are given in Table 10.
Table 10

Channel 3 Break Operation Jumper Summary

Break
Operation
Response

Jumper Connection

Boot*
Halt
No Response

Install jumper between wire-wraps X to B.
Install jumper between wire-wrap pins X to H.
No jumper installed.

* Do not send continual breaks to a system so configured, as it will cause

continued reinitializing of any device on the bus.

280

DLV11-J
Peripheral Interface Configuration
Each of the channels can be independently configured for serial line
signal compatibility with EIA RS-423 (simultaneously RS-232C), RS422, or 20 mA current loop devices. When using 20 mA current loop
devices, the DL V11-KA option is required. Configuration instructions
for each of the standards are listed in Table 11. Table 12 is used when
configuring EIA RS-423 (RS-232C compatible) slew rates. Use this
tahle in conjunction with Table 11.

281

Table 11

Serial Channel
Signal Level
Modifiers
MO-3 Jumper

Summary of Serial Channel Signal Level
Configurations

EIA RS-422

EIA RS-232C
and RS-423

20 mA Current Loop
(Using DLV11-KA)

Connect wire-wrap pins X
and 2.

Connect wire-wrap pins X Connect wire-wrap pins X
and 3.
and 3.

Connect wire-wrap pins X
and 2

Connect wire-wrap pins X Connect wire-wrap pins X
and R for program-conand 3.
trolled paper tape reader.

......
•
c..

I\)

ex>

I\)

NO-3 Jumper

Termination Resistor (one Install a 100n, 114 W, nonper channel)
wire wound, fusible resistor.
Wave-Shaping Resistor
(one per channel pair;
channel pair 0 and 1; 2
and 3}
Fuse F1

Install resistor from Table
12 (1/4 W non-wire
wound).
Install 2.0 A Pico fuse

r
<
......

DLV11-J
Table 12

EIA RS-423 and RS-232C Slew Rate Resistor Values

Baud Rate

R10 or R23

38.4 K
19.2 K
9.6 K
4.8 K
2.4 K
1.2K
600
300
150
110

22KQ
51 KQ
120KQ
200KQ
430KQ
820 KQ
1 MQ
1 MQ
1 MQ
1 MQ

Cabling
Following are listed cables currently available that will mate with the
2X5 pin Amp connector on the DLV11-J, as well as some pOinters and
part numbers for constructing a cable.
DIGITAL cables for the DLV11-J:
BC20N-05

5' EIA RS-232C null modem cable to directly interface with an EIA RS-232C terminal
(2X5 pin Amp female to RS-232C female;
see Figure 8).

BC21B-05

5' EIA RS-232C modem cable to interface
with modems and acoustic couplers (2X5
pin Amp female to RS-232C male; see Figure 7).

BC20M-50

50' EIA RS-422 or RS-423 cable for highspeed transmission (19.2K baud) between
two DLV11-Js (2X5 pin Amp female to 2X5
pin Amp female).

DLV11-KA

20 rnA current loop converter option for the
DLV11-J. Comes with an EIA cable
(BC21A-03) which connects the DLV11-KB
converter box to the DLV11-J. The option
mates with standard DIGITAL 20 rnA cabling using the 8-pin Mate-'N'-Lock connector.
283

DLV11-J
When designing a cable for the DLV11-J, here are several points to
consider:
1.

The receivers on the DL V11-J have differential inputs. Therefore,
when designing an RS-232C or RS-423 cable, RECEIVE DATA
(pin 7 on the 2X5 pin Amp connector) must be tied to signal
ground (pins 2, 5, or 9) in order to maintain proper EIA levels. RS422 is balanced and uses both RECEIVE DATA+ and RECEIVE
DATA-.
To directly connect to a local EIA RS-232C terminal, it is necessary to use a null modem. To design the null modem into the cable,
one must switch RECEIVE DATA (pin 2) with TRANSMITTED OAT A (pin 3) on the RS-232C male connector as shown in Figure 8.
To mate to the 2X5 pin connector block, the following parts are
needed:
Cable Receptacle

AMP PN 87133-5
DEC PN 12-14268-02

Locking Clip Contacts

AMP PN 87124-1
DEC PN 12-14267-00

Key Pin (pin 6)

AMP PN 87179-1
DEC PN 12-15418-00

The pin out on the 2x5 pin connector block on the DLV11-J is as
follows:

Pin #
1
2
3

Signal
UART clock in or out
(16 X baud rate; CMOS)
Signal ground
TRANSMIT DATA+
TRANSMIT DATA-

Note: For EIA RS-423, this line is grounded. For DLV11-KA 20 mA
option, this line is the reader enable pulse.
5
6
7
8
9
10

Signal ground
Indexing key-no pin
RECEIVE DATARECEIVE DATA+
Signal ground
When F1 is installed
for the DLV11-KA, +12V
is supplied through a
fuse to this pin
284

DLV11-J

CIRCUIT
CARD
PRINTED

2X5 PIN CONNECTOR
BLOCK (Viewed from
Edge of Card)

EIA RS-232C

DLVll-J
r--

Clear to Send (CB)

GRD

>9)- -

RCV DATA ';7)- +12 VDC

75011

1/2 W

fu-7lO>
se

Request to Send (CA)

(

Data Set Ready (CC)

'--- -(I
/

Data Terminal Ready (CD)

RCV DATA +)8;

/3 (

Received Data (BB)

XMIT DATA + ) 3)

-(2 (

Transmitted Data (BA)

GRD

>2)

'-- 00-DLVII-J Module

Connector

Figure 7

Cable

(

1
EIA
RS 232C
Connector

Signal Ground (AD)
protective Ground (AA)
Modem

BC21 B-05 Modem Cable
285

DLV11-J
EIA RS-232C

DLVll-J
3

, 3

XMT DATA +

/"
"-

Rev DATA

XMT DATA

Rev DATA +

Rev DATA -

GRD

,,--2

GRD

-----

GRD

(

Shield

Important:
Attach to chassis
at entry point.

Figure 8

BC20N-05 "Null Modem" Cable

PROGRAMMING
The DLV11-J contains a bank of sixteen (16) contiguous registers that
may be positioned from 1600008 to 1777778 in address space by wire
wrap jumpers. Four registers are provided for each of the four SLU
channels.
The format of these registers is shown in Figure 1.
Similarly. the DLV11-J has a bank of eight contiguous interrupt vectors that may be positioned in vector space from 000 8 to 3778 by
jumpers. Two vectors (receive and transmit) are provided for each of
the four channels.
NOTE
One channel may be separately configured as the
computer console device (177560-6 8, vectors 60 and
64) provided the module base address is 1765008,
1765408 or 1775008.
To software. the DLV11-J appears to be four independent serial line
units similar to four single-channel DLV11 s.

286

DLV11-KA
DLV11-KA EIA TO 20 MA CONVERTER
INTRODUCTION
The DLVi i -KA option consists of the DLVII-KB EIA-to-20 rnA
converter unit and a BC21A-03 EIA interface cable. This option is
designed to allow 20 mA current loop capability to be added to a
standard RS-232 EIA serial line unit interface module, such as the
DLV11-J. The DLV11-KB is a small enclosed box with two connectors,
one (2 X 5 pin Berg) for the EIA/TTL signals from the interface module
and the other (standard DIGITAL 20 mA connector 8-pin Mate-N-Lok)
for the 20 mA signals to 20 mA peripherals using standard DIGITAL 20
mAcabling.
FEATURES
• EIA RS-232 to 20 rnA converter (XMT data)

• 20 mA to EIA RS-232 converter (RCVR data)
• A program-controlled, one character at a time reader advance function for DIGITAL-modified ASR-33 Teletypes*
• A 110 baud rate generator
• Optical isolation
• Choice of active or passive operation
• Operates up to 9600 baud rate
• Drive capability up to 4000 feet of cable
* Teletype is a registered trademark of Teletype Corporation.

SPECIFICATIONS

Size:

13.3cm (5.25 in.) long
11.4cm (4.5 in.) wide
2.64cm (1.04 in.) high

Power:

+ 12.0 Vdc ±5% at 0.275 A max

287

DLV11-KA
CONFIGURATION
The DLV11-KA requires the configuration of eleven jumper wire connections and one capacitor connection. The locations of these jumpers are shown in Figure 1 and their functions are listed in Table 1.
Current Loop Definition
In simplest terms, the current in a circuit loop which extends from the
sender to the receiver is switched on and off to represent some particular format for serial transmission of binary data. Besides the actual
current path (wire), the following other three functions are required in
every current loop:
1. Current source
2. Switch
3. Current detector

The switch has to be located in the transmitter, and the current
detector has to be located in the receiver. However, the current source
may be located in either the sender or receiver. The function that
includes the current source is designated active and the one without it
passive. Only one passive and one active function are allowed in a
current loop: never two active or two passive functions (Figure 2). In
order to minimize ground differential noise coupling into data leads,
the transmitter and receiver at one end of the line should be either
both active or both passive, not mixed. Also, it is usually better to
configure the computer (master computer) as active and the terminal
(slave computer) as passive.
110 Baud Rate Generator
This circuit provides a 16 x 110 (1760 Hz), TTL level, crystal-controlled
clock to be sent back to the serial line unit module in order to add 110
baud rate capability to the module. A solderable jumper (W11) is provided in order to select or deselect this function.

0-<)11
O-<)C

60-<)

0--01
70--0
0--08
--~ 90--0
0--03
...----r---' 4 0--0
0--05
20--<)

0--<) 10

~:OTE

THE NUMBER 2 INDICATES THAT
I T IS THE W2 JUMPER WIRE.

Figure

MR-2240

DLV11-KA Jumper Locations

288

DLV11-KA
Table 1

DLV11-K'd Jumper Configurations

Function

Jumper In

Passive 20 rnA Receiver
Active 20 mA Receiver*
Passive 20 mA:Transmitter
Active 20 mA Transmitter*
110 Baud Enabled *
110 Baud Disabled
Noise Suppression

\AI7
\AlO
.... , , "WV'

Jumper Out
'N6, 'NB, \N1 0

W6, W8, W10
W2,W4
W1, W3, W5
W11

W7,W9
W1, V '3, W5
W2,W4
W11

* Factory configuration.

ACTIVE TRANSMITTER
CURRENT
SOURCE

PASSIVE RECEIVER
XMIT

IN TERFA CE
CABLE
REC

1
T

20 MA
LOOP

J
CURRENT
DETECTOR

l RCVR
I

RECEIVED
DATA

I
I
_ _ _ _ _ _ _ _ ...1

XMIT

REC

TRANSMITTED
DATA

ACTIVE RECEIVER
RECEIVED
DATA

--------,I
I CURRENT I R!C
I DETECTOR I

CURRENT
SOURCE

REC

PASSIVE TRANSMITTER
XMIT

"
/

20MA
LOOP
XMTR

TR ANSMITTED
DA TA

XMIT

MR 2331

Figure 2 Standard Current Loop Interface
289

DLV11-KA
Installation
The DLV11-KA option can be installed in a system that requires conversion from EIA RS-232 standard to a 20 mA current loop. The
DLV11-KA option consists of a DLV11-KB converter box and a
BC21A-03 interface cable as shown in Figure 4. The BC21A-03 is a 0.9
m (3 ft.) cable that interconnects the DLV11-KB to a EIA SLU interface
module. The smaller connector (2 X 5 pin) connects to the SLU module and the larger connector (2 X 7 pin) connects to the DLV11-KB
box. Keying is provided on both connectors, and cable retention is
provided by locking pins on the SLU connector. To disengage, pull
back on the connector shell and the connector will slide free. However,
if the cable is pulled, the locking pins will hold the connector firmly in
place. A BC05F-XX cable can be used to connect the DLV11-KB
converter box to DIGITAL 20 mA terminals including the DIGITALmodified ASR-33 Teletype. External mounting dimensions for the
DLV11-KB box are shown in Figure 4.
Cabling
Cables other than the DIGITAL BC05F-XX can be used when installing
the DLV11-KA option. However, any other cable must conform to the
following parameters in order to meet the baud rate versus cable
length specification described in Table 2.
1. Resistance-not more than 30 ohms/1000 ft. (not less than 22
AWG)
2. Capacitance to ground-not more than 50 pF/ft.
3. Capacitance wire-to-wire-not more than 35 pF/ft.
The BC05F-XX cable meets the above requirements. If the user desires to use shielded cable, the shield should be grounded to the
chassis at entry point and not to the DLV11-KB converter box. The
user can fabricate custom cables for the 20 mA interface by using
DIGITAL connectors and pins.

Baud Rate
The DLV11-KA option will operate up to a maximum of 9600 baud,
provided that the interface module can accommodate these rates.

290

DLV11-KA
However, the maximum operational baud rate is also limited by the
length of cable. Table 2 provides maximum recommended cable
lengths for the specific baud rates. These recommendations are conservative and wi!! yield satisfactory operation for almost all applications. Exceeding these guidelines should be done only after reviewing
the DL V11-KA specifications, the severity of the operating environment, and the error rate that can be tolerated.
~

DLV11 KA OPTION
____________

_ _ _ _ _ _ _ _ _ _ _ _ _ _,

BC21A·03
CABLE

BC05F-XX
CABLE

,------J-----..
10

EIA OUT

I I

8
I

SIG GND

~;>
1

6:r-!

KEY

(NC)

1 ~(---------

I CL OUT( 2

, 2 (

<3
I

3 (

1-<4

<5
1
~6

J1
( 1

I
SIG GND

SIG GND

blA S~LJ
INTERFACE
MODULE
SUCH AS THE
DLV11·J

+12 vac

READER PLS

DLV11·KB
EIA TO 20 mA
CONVERTER
BOX

1 CL OUT +
1 READER +
6 (
I CL IN +

I
( 7

7 (

( 8

8 (

I (NC)

SIG GND

( 9
110 BAUD

1 )

(10

2 X 5 PI N
AMP CONN

I READER -

5 (

EIA IN

2 )

1CL IN-

2 X 5 PIN
BERG CONN

MATE 'N' LOK
CONN

TO 20 mA
DEVICE

J2 MATE 'N' LOK
CONNECTOR

KEY
INO PIN)

•

J1 BERG
CONNECTOR
MR-2332

Figure

DLV11-KA Typical Installation

291

DLV11-KA

...
o

w
...
<0

_ _ _- - - - 3 . 5 0 - - - - - - - t_ _
NOTE:
COMPATIBLE WITH RETIIJA RACK SPACING.
\IIR·2334

Figure

DLV11-KA Mounting Dimensions

Table 2

Baud Rate VS. Cable Length

Baud Rate

Max Cable Length

9600

30 m (100 ft.)

4800

76 m (250 ft.)

2400

152 m (500 ft.)

1200

305 m (1000 ft.)

600

610 m (2000 ft.)

300

1220 m (4000 ft.)

110

1220 m (4000 ft.)
292

DRV11
DRV11 PARALLEL LINE UNIT
INTRODUCTION
The DRV11 is a general purpose interface unit used for connecting
parallel line TTL or DTL devices to the LSI-11 bus over up to 7.6 m (25
ft) of cable. It permits program-controlled data transfers at rates up to
40K words per second and provides LSI-11 bus interface and control
logic for interrupt processing and vector generation. Data is handled
by 16 diode-clamped input lines and 16 latched output lines. The
device address is user-assigned and control/status registers (CSR)
and data registers are compatible with PDP-11 software routines.
FEATURES
• 16 diode-clamped data input lines
• 16 latched output lines
• 16-bit word or 8-bit byte programmed data transfers
• User-assigned device address decoding
• LSI-11 bus interface and control logic for interrupt processing and
vector generation
• Interrupt priority determined by electrical position along the LSI-11
bus
• Control/status registers (CSR) and data registers that are compatible with PDP-11 software routines
• Four control lines to the peripheral device for NEW DATA RDY,
DATA TRANS, REO A, and REO B
• Logic-compatible with TTL and DTL devices
• Program-controlled data transfer rate of 40K words per second
(maximum)
SPECIFICATIONS
Identification

M7941

Size

Double

Power

5.0 Vdc ±5% at 0.9 A

Bus Loads
AC
DC

1.4
1.0

DESCRIPTION
Major functions contained on the DRV11 module are shown in Figure
1. Communications between the processor and the DRV11 are execut-

293

DRV11
ed via programmed I/O operations or interrupt-driven routines .

-,J

BDAlO-15l

BIRQ l
BIAKI l
BIAKO l
BDAl 0-15 l

"'::::>

DROUTBUF

OUT 0-15

I
J INTERRUPT

INT ENB A
INT ENB B

.i.!.

lOGIC

DRCSR

REO A

CSRI
NEW DATA ROY
A..l!!U..~

'"
I
H

'"-'

BBS7 l
BSYNC l
BDAl 0-\5 l
BWTBT l
BDIN l
BDOUTl
BRPlY l
BINIT l

BINH
ADDRESS
AND I/O
CONTROL
lOGIC

,:!l

TO/FROM
USER
DEVICE
lOGIC

REQ B
CSRO
DATA TRANS

I DRINBUF

BDAl 0- \5 l

IN 0 -15

'--

Cp -, B08

Figure 1

DRV11 Parallel Line Unit

The DRV11 is capable of storing one 16-bit output word or two 8-bit
output bytes in DROUTBUF. The stored data (OUTO-15 H) is routed to
the user's device via an optional I/O cable connected to J1. Any programmed operation that loads a byte or a word in DROUTBUF causes
a NEW DATA RDY H signal to be generated, informing the user's
device of the operation.
Input data (DRINBUF) is gated onto the BDAL bus during a DATI bus
cycle. All 16 bits are placed on the bus simultaneously; however, when
the processor is involved in an 8-bit byte operation, it uses only the
high or low byte. When the data is taken by the processor, a DATA
TRANS H pulse is sent to the user's device to inform the device of the
transfer.
Addressing
When addressing a peripheral device interface such as the DRV11, the
processor places an address on BDALO-15 L, which is received and
distributed as BRDO-15 H in the DRV11. The address is in the upper
4K (28-32K) address space. On the leading edge of BSYNC L, the
address decoder decodes the address selected by jumpers A3-A 12
and sets the device selected flip-flop (not shown); the active flip-flop
output is the ME signal, which enables function selection and I/O
control logic operation. At the same time, function selection logic
stores address bits BRDO-2.

294

DRV11
NOTE
When addressed, the DRV11 always responds to either BDIN Lor BDOUT L by asserting BRPL Y L (L =
aSs6ition).

Function Selection
Function selection and I/O control logic monitors the ME signal and
bus signals BDIN L, BDOUT L, and BWTBT L. It responds by generating appropriate select signals which control internal data gating. NEW
DATA ROY H or DATA TRANS H output signals for the user's device,
and the BRPL Y L bus signal which informs the processor that the
DRV11 has responded to the programmed 1/0 operation. Since the
DRV11 appears to the processor as three addressable registers
(DRCSR, DROUTBUF, and DRINBUF) that can be involved in either
word or byte transfers, the three low-order address bits stored during
the addressing portion of the bus cycle are used for function selection.
The select signals relative to I/O bus control signals and address bits
0-2 are listed in Table 1.
Function selection is performed by a ROM located at E15 on the
DRV11. The inputs to this ROM consist of the address bits and other
LSI-11 bus signals as shown at the top of Table 1. This table shows the
functions performed by the ROM outputs for a specific input condition.
For example, when the output buffer is addressed by the processor,
the last octal digit is decoded by the ROM to provide the SEL21N Land
the RPL Y L signals. The RPL Y L signal is delayed and becomes the
BRPL Y L signal. The SEL21N L signal is used by the DRV11 logic to
enable the contents of the output buffer register to be placed on the
data lines of the LSI-11 bus so that the processor can read the data.
NEW DATA READY H is active for the duration of BDOUT L when in a
DROUTBUF write operation. This signal is normally active for 350 ns.
However, by adding an optional capacitor in the BRPLY L portion of
the circuit, the leading edge of BRPL Y is delayed, effectively increasing the duration of the NEW DATA ROY H pulse; adding the capacitor
also increases the DATA TRANS H pulse width by approximately the
same amount.
DATA TRANS H is active for the duration of BDIN L when in a DRINBUF read operation. This signal is normally active for 1150 ns. The
time, however, can be extended by adding the optional capaCitor to
the BRPL Y L portion of the circuit as previously described.

295

Table 1

DRV11 Device Function Decoding

Programmed
Operation

Stored
Device
Addr. Bits
0-2

BWTBTL
During
Data
Transfer

0
0

Write DRCSR
Read DRCSR

Write
DROUTBUF
Word

BDIN L

BDOUTL

Bus Cycle
Type

Select
Signals

H
H

L
L

DATO
DATOB

SELOOUT L

DATI or
DATIO

SELOIN L

DATO

SEL20UT
(W + HB) L,
SEL20UT
(W + LB) L, and
NEW DATA
READY H

en
Low Byte

DATOB

SEL20UT
(W + LB) L
and
NEW DATA
READY H

High Byte

DATOB

SEL20UT
(W + HB) L
and
NEW DATA
READY H

Read
DROUTBUF
Read
DRINBUF

SEL21N L

DATI or
DATIO
DATI

SEL41N Land
DATA TRANS H

C
:IJ

~
~

DRV11
Read Data Multiplexer
The read data multiplexer selects the proper data and places them on
the BDAL bus when the processor inputs DRCSR, DROUTBUF or interruot
vectors:
.
. DRINBUF contents are aated onto the bus seoaratelv.
.'"
The select signals (previously described) and VECTOR H, produced
by the interrupt logic, control read data selection.

DRCSR Functions
The control/status register (DRCSR) has separate functions. Four of
the six significant DRCSR bits can be involved in either write or read
operations. The remaining two bits, 7 and 15, are read-only bits that
are controlled by the external device via the REO A H and REO B H
signals, respectively. The four read/write bits are stored in the 4-bit
CSR latch. They represent CSRO and CSR1 (DRCSR bits 0 and 1,
respectively), which can be used to simulate interrupt requests when
used with an optional maintenance cable. INT ENB A and INT ENB B
(bits 6 and 5, respectively) enable interrupt logic operation. Note that
CSRO and CSR1 are available to the user's device for any user application.
DRINBUF Input Data Transfer
DRINBUF is an addressable 16-bit read-only register that receives
data from the user's device for transmission to the LSI-11 bus. Data to
be read are provided by the user's device on the INO-15 H signal lines.
Since the input buffer consists of gating logic rather than a flip-flop
register, the user's device must hold the data on the lines until the
data input transaction has been completed.

The input data are read during a DATI sequence while bus drivers are
enabled by the SEL~IN L signal. The DATA TRANS pulse that is sent to
the user's device by the function select logic informs the device of the
transaction. Input data can be removed on the trailing edge of this
pulse.
DROUTBUF Output Data Transfer
DROUTBUF comprises two 8-bit latches, enabling either 16-bit word
or 8-bit byte output transfers. Two SEL2 signals function as clock
signals for the latches. When in a DATO bus cycle, both signals clock
data from the internal BRDO-15 H bus into the latches. However, when
in a DATOB cycle, only one signal clocks data into an 8-bit latch, as
determined by address bit 0 previously stored during the addressing
portion of the bus cycle.

297

DRV11
The NEW DATA RDY H pulse generated by the function select logic is
sent to the user's device to inform the device of the data transaction.
The data can be input to the device on the trailing edge of this pulse.
Interrupts
The DRV11 contains LSI-11 bus-compatible interrupt logic that allows
the user's device to generate interrupt requests. Two independent
interrupt request signals (REO A H and REO B H) are capable of
requesting processor service via separate interrupt vectors. In
addition, DRCSR contains two interrupt enable bits (INT EN A and INT
EN B, bits 6 and 5, respectively), which independently enable or disable interrupt requests. REO A and REO B status can be read by the
processor in DRCSR bits 7 and 15, respectively. Since separate interrupt vectors are provided for each request, one of the requests could
be used to imply that device data is ready for input and the remaining
request could be used to imply that the device is ready to accept new
data.
An interrupt sequence is generated when a DRCSR INT EN bit (A or B)
is set and its respective REQ signal is asserted by the device. The
processor responds (if its PS bit 7 is not set) by asserting BDIN L; this
enables the device requesting the interrupt to place its vector on the
BDAL bus when the interrupt request is acknowledged. The processor
then asserts BIAKO L, acknowledging the interrupt request. The
DRV11 receives BIAKI L and the interrupt logic generates VECTOR H,
which gates the jumper-addressed vector information through the
read data multiplexer and bus drivers and onto the LSI-11 bus. The
processor then proceeds to service the interrupt request.
Maintenance Mode
The maintenance mode allows the user to check DRV11 operation by
installing an optional BC08R cable between connectors J1 and J2.
This maintenance cable allows the contents of the output buffer
DROUTBUF to be read during a DRINBUF DATI bus cycle. In addition,
interrupts can be simulated by using DRCSR bits CSRO and CSR1.
CSR1 is routed via the cable directly to the REQ B H input and CSRO is
routed to the REQ A H input. By setting or clearing INT EN A, INT EN
B, and CSRO and CSR1 bits in the DRCSR register, a maintenance program can test the'interrupt facility.
Initialization
BINIT L is received by a bus driver, inverted, and distributed to DRV11
logic to initialize the device interface. The buffered initialize signal is

298

DRV11
available to the user's device via the AINIT Hand SINIT H signal lines.
DRV11 logic functions cleared by the SINIT signal include DROUTSUF, DRCSR (bits 0, 1, 5, and 6), and interrupt logic.

CONFIGURATION
The following paragraphs describe how the user can configure the
module by inserting or removing jumpers (Figure 2) so that it will
function within his system. The jumpers, listed in Table 2, indicate the
factory configuration when shipped.

J 1

I VEC';;;-R--:;-U~ERS I
I
IV4-

-V5

I
1

I v3-vsl
L ___ ~v~

i ~m;~ss JU;-P~S--;
I

A3-

-A9

A4-

-A1Q

I
I

~~==
==~~h
,.7I
L".!==- _____ -.-l
I

SLI '.,

SL2

0---:::----0

OPTIONAL EXTERNAL
CAPACITOR

M7941 ETCH REV C
MR-oa09

Figure 2

DRV11 Jumper Locations

299

DRV11
Table 2

DRV11 PLU Factory Jumper Configuration

Jumper
Designation

Jumper
State

A3
A4
A5
A6
A7
A8
A9
A10
A 11
A12

R
R
R
R
R
R
R
R
R
I

V3
V4
V5
V6
V7

I
R
R

Function Implemented
This arrangement of jumpers A3 through
A 12 assigns the device address 16777X
to the PLU. This address is the starting
address of a reserved block in memory
bank 7 which is recommeded for user
device address assignments. The least
significant digit X is hardwired on the
module to implement the three PLU device addresses as follows:
X=O
X=2
X=4

DRCSR address
Output buffer address
Input buffer address

This factory-installed jumper configuration implements the two interrupt vector
addresses 300 and 304 for use as defined by application requirements.

R = Removed, I = Installed

Device Address
Addresses for the DRV11 can range from 16000X through 17777X.
The three least significant bits are predetermined for the other DRV11
registers as shown in Table 3 and Figure 3. Addresses within 177560
to 177566 are reserved for the console device and should not be used
for the DRV11.

300

DRV11
Table 3

Description
Register
Control and
Status
Output Buffer
Input Buffer
Interrupt
Request A
Request B

Standard Assignments

Mnemonic

Read!
Write

First
Second
Module Module
Address Address

DRCSR

R/W

167770

167760

DROUTBUF
DRINBUF

R/W
R

167772
167774

167762
167764

300
304

310
314

REQA
REQB

~
BBS? L
" llLl

I
N
\

'"<t
ADDRESS JUMPERS:
INSTALLED "0
REMOVED "1

'-------.------ -l
..,
<t

BYTE SELECT
P high bylelB-151
O=lowbyte(O-7)

Figure 3

DRV11 Device Address Selection

Jumpers for bits 3 through 12 are installed or removed to produce the
16-bit address word shown in Figure 3. The appropriate jumpers are
removed to produce logical 1 bits, and installed to produce logical 0
bits.
Vectors
The two vectors are selected within the range of 000 to 374 by using
jumpers V3 to V7. Vector bits 3 through 7 are selected by the user to
form the vector as described in Figure 4. The factory configuration
sets the interrupt vector for 300 as shown in Table 3 and Figure 4.

301

DRV11
8

t.-

I
If)

(DRCSR -15)
REOUEST I NG DEVICE
o ~ REO A
1 ~ REO B

VECTOR JUMPERS:
INSTALLED~O

REMOVED

Figure 4

~ 1

CP-1745

DRV11 Interrupt Vector

Registers
The word format for the control and status register (DRCSR) is shown
in Figure 5 and described in Table 4.

DRCSR

REQUEST A
(READ ONLY) (READ/WRITE)
INT ENB A
(READ / WRITE)

Figure 5

DRCSR Word Format

Table 4

DRCSR Word Formats

Name: Request B.
Bit: 15
Function: This bit is under control of the user's device and may be
used to initiate an interrupt sequence or togenerate a flag that may be
tested by the program.
When used as an interrupt request, it is asserted by the external device and initiates an interrupt provided the INT ENB B bit (bit 5) is also
set. When used as a flag, this bit can be read by the program to
monitor external device status.
When the maintenance cable is used, the -state of this bit is dependent
on the state of CSR1 (bit 1). This permits checking interface operation
by loading a 0 or 1 into CSR1 and then verifying that Request 8 is the
same value.
Read-only bit. Cleared by INITwhen in maintenance mode.
302

DRV11
Bit: 14-8 Name: Not used.
Function: Read as O.
Bit: 7
Name: Request A.
Function: Performs the same function as Request 8 (bit 15) except
that an interrupt is generated only if INT ENS A (bit 6) is also set.
When the maintenance cable is used, the state of Request A is identical to that of CSRO (bit 0).
Read-only bit. Cleared by INIT when in maintenance mode.
Bit: 6
Name: INT ENS A.
Function: Interrupt enable bit. When set, allows an interrupt request
to be generated, provided Request A (bit 7) becomes set.
Bit: 5
Name: INT ENS B.
Function: Interrupt enable bit. When set, allows an interrupt sequence to be initiated, provided Request S (bit 15) becomes set.
Bit: 4-2
Name: Not used.
Function: Read as O.
Bit: 1
Name: CSR1.
Function: This bit can be loaded or read (under program control)
and can be used for a user-defined command to the device (appears
only on connector number 1).
When the maintenance cable is used, setting or clearing this it causes
an identical state in bit 15 (request S). This permits checking operation
of bit 15 which cannot be loaded by the program.
Can be loaded or read by the program (read/write bit). Cleared by
INIT.
Bit: 0
Name: CSRO.
Function: Performs the same functions as CSR1 (bit 1) but appears
only on connector number 2.
When the maintenance cable is used, the state of this bit controls the
state of bit 7 (Request A).
Read/write bit; cleared by INIT

303

DRV11
The word format for the transmit output buffer (DROUTBUF) is shown
in Figure 6 and defined in Table 5.
8

DROUT SUFIL

_L-.....L_L-.....L_L-.--...L------''------'------'-.....l------'----'--~----'------L----'

DATA OUT
( READ/WRITE)
MR-08"

Figure 6

DROUTBUF Word Format

Table 5

DROUTBUF Word Format

Bit: 15-0 Name: Output Data Buffer.
Function: Contains a full 16-bit word or one or two a-bit bytes; high
byte = 15-8; low byte = 7-0.
Loading is accomplished under a program-controlled DATO or DATOB bus cycle. It can be read under a program-controlled DATI cycle.
The word format for the receiver input buffer (DRINBUF) is shown in
Figure 7 and defined in Table 6.

DRINSUF

~,~======~~~==~~~~========~~~
DATA IN
(READ ONLY)

"R-oei2

Figure 7

DRINBUF Word Format

Table 6

DRINBUF Word Format

Bit: 15-0 Name: Input Data Buffer.
Function: Contains a full 16-bit word or one or two 8-bit bytes. The
entire 16-bit word is read under a program-controlled DATI bus cycle.

304

DRV11
Installation
Prior to installing the DRV11 on the backplane, first establish the desired priority level for the backplane slot installation. Check that proper device address vector jumpers are installed. The DRV11 canthen be
installed on the backplane. Connection to the user's device is via optional cables.
Interfacing to the User's Device
Interfacing the DRV11 to the user's device is via the two board-mounted H854 40-pin male connectors. Pins are located as shown in Figure
8. Signal pin assignments for input interface J2 (connector number 2)
and output interface J1 (connector number 1) are listed in Table 7.
Optional cables and connectors for use with the DRV11 include:
BC08R-01-Maintenance cable; 40-conductor flat with H856 connectors on each end.
BC07D-X*-Signal cable; two 20-conductor ribbon cables with a single H856 connector on one end; remaining end is terminated by the
user. Available in lengths of 3,4.6, and 7.6 m (10,15, and 25 ft).
* The -X in the cable number denotes length in feet, -10, -12, -20. For example,

a 10-1t SC07D cable would be ordered as SC07D-1 O.

BC04Z-X*-Flat 40-conductor signal cable with a single H856 connector on one end; remaining end is terminated by the user. Available in
lengths of 3,4.6, and 7.6 m (10, 15, and 25 ft).

BCV11-X*-Flat, 40-conductor, twisted pair cable with a single H856
connector on one end. The remaining end is connected by the user.
Available in lengths of 1.5,3; 4.6, 6.1, and 7.6 m (5,10,15,20, and 25
ft).

H856-Socket, 40-pin female, for user-fabricated cables.

When using the SC07D cable, connect the free end of the ribbon
cables using the wiring data contained in Table 8.

305

DRV11

I :

\
\

H854
CON~ECTOR

H856 CONNECTOR

Figure 8

J1 or J2 Connector Pin Locations

306

DRV11
Table 7

DRV11 Input and Output Signal Pins

Inputs

S=--....
t!:lllGt•

Outputs

"" ............................. D= ...

,",Utlll':',","'1 r i l l

INOO
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
REQB
DATA
TRANS
CSRO
INIT

J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2

P
N
M
S
C

J2
J2

K
RR,NN

Table 8

LL
H,E
BB
KK
HH
EE
CC

Z
Y
W
V
U

.. .

CHgna l
...,.

Connecter Pin

OUTOO
OUT01
OUT02
OUT03
OUT04
OUT05
OUT06
OUT07
OUT08
OUT09
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
REQA
NEW DATA
ROY
CSR1
INIT

J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1

C
K
NN
U

L
N
R
T
W
X

Z
AA
BB

FF
HH
JJ

LL
VV
DD

BC07D Signal Cable Connections

Cable 2 (connector pins A-UU)
Cable 1 (connector pins B-VV)
J2
J1
J2
Wire
J1
Signal
Pins
Signal
Pins
Color
Signal
Signal
blk

open

brn

open

OUTOO

DATA
TRANS

red

open

IN02

307

DRV11
Table 8

SC07D Signal Cable Connections (Cont)

Cable 1 (connector pins S-VV)
Cable 2 (connector pins A-UU)
Wire
J1
J1
J2
J2
Pins
Signal
Color
Pins
Signal
Signal
Signal

orn

GNO

GND

open

IN02

yel

aUT04

GND

aUT01

eSRO

grn

aUT05

IN14

GND

IN15

blu

aUT06

GND

INIT

IN13

vio

aUTO?

GND

REQB

gry

GND

IN11

aUT03

IN12

wht

aUT09

GND

aUTOB

IN10

blk

aUT10

INOB

GND

IN09

brn

aUT12

IN03

aUT11

GND

red

eSR1

GND

INO?

orn

aUT13

open

GND

IN06

yel

aUT15

GND

aUT14

IN05

grn

REQA

IN01

GND

IN04

blu

aUT02

INIT

GNO

GND

vio

aUT02

INIT

GND

gry

open

INOO

GND

wht

NEW
DATA
ROY

open

GND

30B

DRV11
Table 9

BC08R Maintenance Cable Signal Connection

....

J2
Pin

Name

OPEN
GND
INOO
GND
INITH
GND
INIT
GND
IN01
IN04
GND
IN05
OPEN
IN06
GND
INO?
IN03
GND
INOB
IN09
GND
IN10
IN11
IN12
GND
REQ8
GND
IN13
IN14
IN15
GND
CSRO
GND

A
8
C
D
E
F
HH

OPEN
OPEN
OUTOO
OPEN
OPEN
OPEN
OPEN
GND
OUT01
OUT04
GND
OUT05
INITH
OUT06
GND
OUTO?
OUT03
GND
OUTOB
OUT09
GND
OUT10
OUT11
OUT12
GND
CSR1
GND
OUT13
OUT14
OUT15
GND
REQA
GND

UU
TT
SS
RR
PP
NN

MM
LL
KK
JJ
HH
FF
EE
DD
CC
88
AA
Z

y
X
W
V
U
T
S
R
P
N

M
L
K
J

K
L
M
N
P
R
S
T
U

V
W
X
y
Z
AA
88
CC
DD
EE
FF
HH

KK
LL
MM
309

DRV11
Table 9

BC08R Maintenance Cable Signal Connection (Cont)

J2
Pin

Name

H
F
E
0

IN02
OPEN
IN02
OPEN
DATA TRANS
OPEN
OPEN

NN
PP
RR
SS
TT
UU
VV

OUT02
GND
OUT02
GND
OPEN
GND
NEW DATA ROY

C
B
A

Output Data Interface
The output interface is the 16-bit buffer (DROUTBUF). It can be either
loaded or read under program control. When loaded by a DATO or
DATOB bus cycle, the NEW DATA ROY H pulse is generated to inform
the user's device of the data transfer. The trailing edge of this positivegoing pulse should be used to strobe the data into the user's device in
order to allow data to settle on the interface cable. The system initialize
signal (BIN IT L) will clear DROUTBUF.
All output signals are TTL levels capable of driving eight unit loads
except for the following:
New Data Ready = 10 unit loads
Data Transmitted = 30 unit loads
INIT (Initialize) = 10 units per connector

Input Data Interface
The input interface is the 16-bit DRINBUF read-only register, made up
of gated bus drivers that transfer data from the user's device onto the
LSI-11 bus under program control. DRINBUF is not capable of storing
data; hence the user must keep input data on the IN lines until read by
the processor. When read, the DRV11 generates a positive-going OATA TRANS H pulse which informs the user's device that the data has
been accepted. The trailing edge of the pulse indicates that the input
transfer has been completed.
All input signals are one standard TTL unit load; inputs are protected
by diode clamps to ground and +5 V.
310

DRV11
Request Flags
Two signal lines (REO A H and REO B H) can be asserted by the user's
device as flags in the DRCSR word. REO B is available via connector
number 2. and it can be read in DRCSR bit 15. REO A is available via
connector number 1, and it can be read in DRCSR bit 7. Two DRCSR
interrupt enable bits, INT ENB A (bit 6) and INT ENB B (bit 5), allow
automatic generation of an interrupt request when their respective
REO A or REO B signals are asserted. Interrupt enable bits can be set
or reset under program control.
In a typical application, REO A and REO B are generated by request
flip-flops in the user's device. The user's request flip-flop must be set
when servicing is required and must be cleared by the trailing edge of
NEW DATA ROY or DATA TRANS when the appropriate data transaction has been completed.
This timing is shown in Figure 9. The logic required by the user to
implement this is shown in Figure 10. The logic consists of a flip-flop
that is set by the User Request pulse, which indicates that the user's
device is requesting a transfer. The flip-flop is reset by the trailing
edge of the NEW DATA ROY signal or the DATA TRANS signal.

(do'o")

(do.o")

--------------,

DROUTBUF

X,-________ ~d~o.:..02.

(OUT0£1: DUTI5> ore set/reset
by the DRV 11 under control of
the ,,/03

(doto'0)

I
I
I

~ 300n5

NEW DATA READY
Pu Ised by DRV 11 when the

11/03 writes data to the DRV11

. " " om m
REQUEST A

,"""J

Set by user when ready for new data
from 11 /03 ~ reset by user upon
trailing edge of NEW DATA READY

DRCSR

bit 6> Interrupt Enable A
Set by user to allow interrupt-driven
data transfer

I
I
I
I

l'----_

DRCSR

<bit 7> Request A flag
Indicates state of REQUEST A line.

11- 4569

Figure 9

DRV11 Interface Signal Sequence
311

DRV11
~-------USER

REQUEST A*

RQSTAH+--------~------__.

o
7474

NEW DATA ROY H

A INIT H

r - - - - - - - - - U S E R REQUEST B*
RQST B H + - - - - - - - - + - - - - - - - - - - ,

o
7474
DATA TRANS H

">----lC

B INIT H

*SEE NOTE IN TEXT
MA·'276

Figure 10

User Request Logic

NOTE
The User Request signal must return to the "high"
state prior to the occurrence of the trailing edge of
NEW DATA RDY or DATA TRANS. The leading edge
of NEW DATA RDY or DATA TRANS can be used for
this purpose. In most applications, a pulse on the
User Request Line of less than 10 J,LS is adequate.

312

DRV11
Initialization
The BINIT L processor-generated initialize signal is applied to DRV11
circuits for interface logic initialization. It is also available to the user's.
circuits via connectors J1 and J2 as follows:
Connector/Pin
J1/P
J2/RR
J2/NN

Signal
AINIT H
BINITH
BINIT H

An active BINIT L signal will clear DROUTBUF data, DRCSR bits 6,5, 1,
0, bits 16 and 7 (when the maintenance cable is connected), and
interrupt request and interrupt acknowledge flip-flops.
NEW DATA ROY and DATA TRANS Pulse Width Modification
An optional capacitor can be added by the user to the DRV11 module
to extend the pulse width of both the NEW DATA RDY and DATA
TRANS pulse widths. The capacitor can be added in the location
shown in Figure 2 to produce the approximate pulse widths listed
below.
Optional External
Capacitance (F)
None
0.0047
0.01
0.02
0.03

Approximate Pulse Width (ns)
NEW DATA ROY
DATA TRANS
350
1150
750
1550
1550
2400
2330
3200
3150
3900

BC08R Maintenance Cable
When using the optional BC08R maintenance cable, the connections
listed in Table 9 are provided. Cable connectors P1 and P2 are connected to DRV11 connectors J1 and J2, respectively. Note that CSRO
(J2-K), which can be set or reset under program control, is routed to
the REO A input (J1-LL); similarly, CSR1 (J1-DD) is routed to REO B
(J2-S). Hence, a maintenance program can output data to DROUTBUF
and read the same data via the cable and DRINBUF. DRCSR bits 0
(CSRO) and 1 (CSR1) can be used to simulate REO A and REO B
signals, respectively. If the appropriate INT ENB bit (DRCSR bits 5 or
6) is set, the simulated signal will generate an interrupt request. Note
that the BC08R cabl.e must incorporate a half-twist when connected to
J1 and J2.
313

DRV11-B
DRV11-B DMA INTERFACE
INTRODUCTION

The DRV11-B is a general purpose direct memory access (DMA) interface used to transfer data directly between the LSI-11 system memory
and an I/O device. The interface is programmed by the processor to
move variable length blocks of 8- or 16-bit data words to or from specified locations in memory by means of the LSI-11 bus. Once programmed, no processor intervention is required. The DRV11-B can
transfer up to 250K 16-bit words per second in single cycle mode and
up to 500K 16-bit words per second in burst mode. The control structure also allows read-modify-write operations.
FEATURES

• Buffered input/output data
• Data transfer rate of up to 500K 16-bit words per second
• Each Transfer of up to 32K 16-bit words
• Compatible with LSI-11 bus
• 16-bit CSR available for control and status functions
• Two 40-pin I/O connectors mounted on module for interface with
user's hardware
• Switch-selectable device address and interrupt vector

SPECIFICATIONS

Identification

M7950

Size

Quad

Power

+5 Vdc ±5% at 1.9 A

Bus Loads
AC
DC

3.3
1

DESCRIPTION

Basic functions that make up the DRV11-B are shown in Figure 1. The
following paragraphs describe the DRV11-B registers, the bus operations required for DMA transfers and the DMA transfer timing.
314

DRV11-8
DRV11-B Registers
The DRV11-B contains five registers:

Word Count Register (WCR)
Bus Address Register (BAR)
Control/Status Register (CSR)
Output Data Buffer Register (ODBR)
Input Data Buffer Register (IDBR)
Word Count Register (WCR) - The WCR is a 16-bit read/write register that controls the number of transfers. This register is loaded (under
program control) with the 2's complement of the number of words to
be transferred. At the end of each transfer, the word count register is
incremented. When the contents of the WCR are incremented to zero,
transfers are terminated. READY is set, and if enabled, an interrupt is
requested. The WCR is word-addressable only.
Bus Address Register (BAR) - The BAR is a 15-bit read/write register. This register is loaded (under program control) with a bus address
(not including the address bit 0) which specifies the location to or from
which data is to be transferred. The BAR is incremented acros 32K
memory boundaries via the extended address feature of the DRV11-B.
Systems with only 16 address bits will "wrap-around" to location zero
when the extended address bits are incremented. The BAR is wordaddressable only.
Control/Status Register - The CSR is a 16-bit register used to control

the function and monitor the status of the interface. Bit 0 is a writeonly bit and always reads as zero. Bits 1-6 and bits 8 and 12 are read/
write bits; bits 7, 9-11, and 13-15 are read-only bits. Bit 14 can be written to a zero. Bits 4 and 5 are the extended addressing bits. The CSR is
both byte- and word-addressable.
The two DBRs are
16-bit registers. The input DBR is a read-only register and the output
DBR is a write-only register. Data is loaded into the input DBR by the
user's device and subsequently transferred into memory under DMA
control by the DRV11-A , or under program control by the processor.
Conversely, data is written into the output DBR from memory under
DMA control by the DRV11-B, or under program control by the processor, and read by the user's device. The input and output DBRs interface to the user's device by means of two separate 40-pin I/O connectors. These connectors may be cabled together (for maintenance
purposes) to function as a read/write register. The input and output
DBRs share the same bus address and are byte- and word-addressable.
315
Input and Output Data Buffer Registers (OBRs) -

BWTBT L

._--

BBS7 L

DATA
~ BUFFER

K
"

} FROM CSR

"16-BUS DATA IADDRESS/
VECTOR BITS
(BDAL 00 - IS L)

TRANSCEIVERS

'" 7

~
fJD~~~S
AI2 SELECTION

DEVICE
ADDRESS ,~)
SELECTOR
"
VECTOR
ADDRESS
GENERATOR

SWITCHES

v2 -v9 ]

DEVICE
ADDRESS
SELECTION

WORD COUNT
(DADO-IS H)

...

erN IT

BIAKI

BIAKO

BIRO

ATTN

READY H

(OAI)

STATUS A,B,C(DA1I,10,OS)

SWITCHES

CONTROL
STATUS
REGISTER
(CSR)

CYCLE (DADe)

r----

IE (I) H

~IE

DA06

r
L
L
L
L
L
L

DA 0

AB C H

CYCLE
REOUEST H

16 L

USER'S

liD
DEVICE

} TO

LSI-II

~_
17L

BUS

INPUT

TO
CSR
WCR
BAR
DBR'S

INPUT DATA BITS
(O-ISINH)

CO H
CI H

--_. _ _ .. _--00

DMA
CONTROL
LOGIC

SINGLE CYCLE H

-_.

INIT H

.___ ." _ _ ..lNIT V2 H
____BUSy'!.....

:;.

1\- 4\60

Figure 1

DRV11-B Logic Block Diagram

...I.
...I.

•

i'r

C
::D

DATA
BUFFER
(OBR)

SYNC
DIN

STAT

XAD 16,17 (OA04 ,05)

DA 0 I 2H

BDOUT
BDMR
eSACK
BDMGO
BDMGI
BRPLY
BO N
eSYNC

ATTN H

fNCT 12) (DAOI,02,O)

PROTOCOL
LOGIC

I 2 ) H

FNCT

~MAINL!DAI2) _ _

READY (I) H

BWTBT

we INC ENS H

NEX (DAI4)

INTERRUPT
LOGIC

WORD
COUNT
REGISTER
(WCR)

ERROR (DAIS)

I
I

READY (OA07)

'"m:::>

B'A INC ENS H

'----

3-STATE BUS (DATAl ADDRESS BITS DA 00-15H)

-----BBS7 L

AOO H

'--

ADDRESS
(DAOO-15H)

./ REGISTER
(DBR)

BAD 16L
BAD 17L

OUTPUT DATA BITS
(0-15 OUT H)

OUTPUT

BUS
ADDRESS
REGISTER
(BAR)

DRV11-B
User's 1/0 Device to System Memory Transfer (DATO or DATOB)
Data transfers from the user's 1/0 device to the memory are DMA
transfers. Figure 2 illustrates the data flow for a DMA DATO or DATOB cycle. Referring to Figure 1, DMA transfers are initialized under
program control by loading the DRV11-B WGR (in 2's complement)
with a count equal to the number of words to be transferred; loading
the BAR with the starting memory address for word storage; and setting the GSR for transfers.

(

h
f-l

)
--

\..=::;: DATA FLOW -

,-~

USERS
DEVICE

DRVI1-B

,--

h
f-l

DATO

DATOB

~
--v

MEMORY

PROCESSOR

11- 4187

Figure 2 DMA DATO/DATOB Data Flow Diagram
When the GO bit of the CSR is written to a "one," READY goes low, the
user's I/O device conditions the AOO, BA INC ENB, WC INC ENB,
ATTN, SINGLE CYCLE (high for normal DMA transfers), and the CO,
C1 (Table 6) lines, and then asserts CYCLE REQUEST. The input data
bits and the control bits (CO, C1, and SINGLE CYCLE) are latched into
the respective DRV11-B registers. CYCLE REQUEST sets CYCLE and
causes the DRV11-B to assert BDMR, which makes an LSI-11 bus
request and causes BUSY to go low. In response to BDMR, the
processor asserts BDMGO which is received as BDMGI. The DRV11-B
becomes bus master and asserts BSACK and negates BDMR. The
processor then terminates the bus grant sequence by negating
BDMGO.
When the DRV11-B becomes bus master, a DATI or DATIO bus cycle
is performed (a DATI is described). The DRV11-B places the address
of the memory location from which the first word is taken on the BDAL
317

DRV11-B
A
~

/1-

--+

DATA FLOW--

h
t-'

r
'--

USERS
DEVICE

DATI OR

DATIO - - +

)

MEMORY

)

PROCESSOR

/'
~

r'
DRVI1-B

'7
1\- 4188

Figure 3

DMA DATIO/DATI Data Flow Diagram

lines and asserts BSYNC. Memory decodes and latches the address.
The DRV11-B then removes the address from the BDAL lines and
asserts BDIN. Input data is now placed on the BDAL lines by the
memory and the memory asserts BRPLY. The input data is accepted
by the DRV11-B and BDIN is negated. Memory negates BRPLY and
the DRV11-B negates BSACK and BSYNC to terminate the bus cycle
and release the bus. The output data bits for the user's I/O device are
stored in the DRV11-B output data buffer register. These bits can be
read by the user's device at the low-to-high transition of BUSY.
At the end of the first transfer, the DRV11-B WCR and BAR are incremented, BUSY goes high and READY remains low. The user's device
can initiate another DATI or DATIO cycle by again setting CYCLE
REQUEST. DMA transfers to the user's device can continue until the
WCR increments to zero and causes an interrupt request to be
generated.
DMA Transfers
The DRV11-B interface is designed for DMA transfers which the user
can accomplish in several ways. DMA transfers are always set up by
the processor when it loads the BAR and WCR and sets the READY bit.
The user then has the option of initiating transfers either by program
control (setting the GO bit in the CSR) or by the user device asserting
CYCLE REQUEST for 1 Jl,s minimum.

318

DRV11-B
Type of I/O to be Performed - The user has the option of selecting
DATI, DATO, DATOB, or DATIO bus cycles by asserting CO and C1 per
Table 6. Note that iT byte transfers are being performed, the byte
address bit (ADO) must be manipulated by the user, (Refer to the
section entitled "Word or Byte Transfers.")

Burst Mode vs. Single Cycle DMA - Single cycle DMA allows the
asynchronous transfer of data to or from the user's device. Each time
the user's device is ready for a transfer, the user asserts CYCLE REQUEST for 1 jls. A DMA cycle is requested from the LSI-11 bus, and
when the bus is granted to the DRV11-B, the BUSY line is asserted to
inform the user that a data transfer is underway. The user must set up
input data when CYCLE REQUEST is asserted, and hold it valid until
the next assertion of CYCLE REQUEST. The user must strobe output
data out of the DRV11-B on the rising edge of BUSY. The data will be
valid 250 ns minimum before the rising edge of BUSY. (Figures 4 and 5
are detailed timing diagrams.)
Burst mode DMA allows synchronous transfer of data between a
user's device and the DRV11-B. Once a DMA sequence is started (either by the user or by the processor), data will be transferred at a synchronous rate of 500K words per second. One data word wi II be transferred every 2 jls. The user must strobe data out of the DRV11-B into
the user's device on the rising edge of BUSY. The data to be transferred to the DRV11-B must be set up when the READY line goes low
(for the first data transfer) or on the rising edge of BUSY (for subsequent data transfers). (Figures 6 and 7 are detailed timing diagrams.)
Word or Byte Transfers - The DRV11-B can transfer words or bytes
to memory. Transfers from memory are always on a word basis; if only
one byte is required, the unused bytes are disregarded. To transfer
data on a byte basis to memory, the following operations must be
performed:
1.

ADO must be manipulated by the user to address the proper byte
in memory.

The byte to be transferred to memory must be input in its proper
position in the input word, i.e., if ADO is 1, the byte to be input must
be on the input lines IN 8 H through IN 15 H (high byte being
transferred).

WC INC EN Hand BA INC EN H must be asserted during the write
cycle of the first byte of each word to inhibit the BAR and WCR
from incrementing.
319

DRV11-B

LOADWCK

LOAD BAA

INT ENABLE

'COCl
(DETERMINE
CYCLE TYPE)

·we INC ENABLE
SA INC ENABLE

·A(l(l

·SiNGLE CYCLE

··READY

'CYCLE REO

"'BUSY
SET UP INPUT

CYCLE REQUEST

~~;E~11~~N -----i

"DATA FROM USER
DEVICE TO DRVlT·8

(IF DATO(Sl!

I
I
I

IX
I

I
I

x=
I

I
I

i
"iJA1A I-rlLJilli DAVll·B
TO USER DEVICE
(I F DATI OR DAIIQ)

~--~--~--~~---'
LOW BYTE

"INPUT LINE Ffl'O~

WORD TRANSFERS

HIGH BYTE

BYTe TR A \;$J:: E!:IS

USERS DEVICE

"OUTPUT LINE
TO USERS

DEVICE

Figure 4

DRV11-8 Timing: Single Cycle, Asynchronous, UserInitiated

320

DRV11-B

LOAD WCR

LOAD BAR

I1'<T ENABLE

--~

'we INC ENABLE
SA INC ENABLE

_ _ _ _ _ _- J

'ADO

·SINGLE CYCLE

lOW TO HIGH
"READY

CAUSED BY

TRAr'I!SITION
CAUSES A LJ!V1A

SETTING GO

CYC~E

BIT

'CYClE REO

"BUSY

SET UP INPUT

~::~~~I~~ ~

------------,X
1

GOES LOW

'OATA FROM USER
DEVICETODRV11·B _ _ _ _ _ _ _ _ _ _- - '
IIF DATOIS))

I
I

_Of CYCLE REQ

.1 '-.______.J

'-_ _ _ _-'

i
I

~----"'n----'

•• DATA FROM 0 RV 11-8 7"7"":'7"'T77"77"":'7"'TT7-r""-;'7-r7>
TO USER DEVICE
(IF DATI OR DATIO)

LOW BYTE

'INPUT LINE FROM

L,'

Ifr-SETUPDATA
OR RI$ING EDGE

\...._ _ _ _~I

I
I

WORD TRAl\.SFERS

HIGH BYTE
BYTE TRANSFERS

USERS DEVICE

• 'OUTPUT LINE
TO USERS
DEVICE

Figure 5

DRV11-8 Timing: Single Cycle, Asynchronous, ProgramInitiated

321

DRV11-B

LOAD WCR

LOAD BAR

It\,)T ENABLE

/
---~

'eo,C1

(DETERMINES

CYCLE TYPE.I _

X'----------'x'----_x=

\..
_ _ _ _ _ _---'

\'---__-----J/

'we I !\Ie ENABLE
SA I~C Er\JABlE

. AOO

~.---~---~~-~--

__ ',". ~" l;:

--_.- ---~~------~ ---.----~----~
: , ' I 1 [;

Ir..,PL'T Lil\,: FP'J'.'

1".1, \sr E R~,

,~\

... ; ... ::.::. ", S; ; =t S

'_IS!: qS D~ \"C1:
'J(!1 1
P! I-.:IU[I ,~: cOUt.,'
~"\

~ '('~,':; UJ:"

Cll\Str':'J

'I,,'

I .... E ~\.~."lt.;..

8::-" \Ie ()~, .,.~,:: L~' ", !:hJS

.'.'-i'".::

'Ti-<'S";":

)~1-1~ ',';-'~~

rl~pL. 'r

'T'''-'::S

;'~f

"'Uf:'\,A.~

I. A~ 'J~

.3' r'"'l
'<,:S

(''\J ~.1! 'I1(

\'.·~\1"',)r liDe'

. . \'><:Lf

".'\

-"'F ~~

T.' ~·sn'n:··.'F\T::.\ Ti-E

",': \' ,) 1-.:" R E", " - '::: : T '~, ~,::';'." \.-4 ,-l "
:;

..'llO \~

Figure 6

DRV11-B Timing: Burst Mode, User-Initiated

322

DRV11-8

LOADWCR

LOAD BAR

INT ENABLE

------'

~~\.._ _ _ _---' '-_ _ _ _- ' '-_ _ _ _ _- ' '-_ _ __

(DETERMINES
·COCl
CYCLE TYPE I _

"we INC ENABLE

'1.--_ _---11

SA INC ENABLE

r---SEE NOTE 1---001

)

·AOO

·SINGLECYCLE///////////////~

""""~
BIT

·CYCLE REO

- - - - - - - - - - - ; 1 - . , STROBE
··BUSY
CAUSED BY SETTING
CYCLE REQUEST
BIT

I 150 NS MAXi-! I-I
I

·DATA FROM USER

DEVICE TO DRV11 B · · ·
{lFDATO(BIl

I
r-

DATA INTO
USER DEVICE

SEE...J
NOTE
2

~~N

I
\rt-250

~~~N

~~~N
LOW BYTE

··OUTPUT LINE
TO USERS
DEVICE
···INPUT DATA
MUST BE ST AS LE

NOTE 1
THIS PULSE WIDTH PERIOD IS eQUAL TO
THE TIME BETWEEN CONSECUTIVE ASSERTIONS OF BSVNC ON THE LSI-11 sus.
WHILE THIS IS DEPENDENT ON MEMORY
REPLY TIMES. THE NOMINAL VALUE IS

• ••

,rt-250

WORD TRANSFERS

'"INPUT LINE FROM
USER DEVICE

I
•••

~~ ~!~~ g~61;~'OI

1
•••

··OATAFROMDRV11-S77l7//7l7l7l7l7r+250

•••
_

I
I

~
HIGH BYTE

BYTE TRANSFERS

NOTE 2
THE WIDTH OF THIS PULSE IS DETERMINED

BY THE WIDTH OF BRPLY ON THE LSI-l1
BUS. WHI LE THIS IS DEPENDENT ON THE
MEMORY REPLY TIME, IT IS NOMINALLY
200 NS.

2/015.

Figure 7

DRV11-B Timing: Burst Mode, Program Initiated

323

DRV11-8
Miscellaneous Signals - Four sets of signals exist to perform handshaking and status exchange between the processor and the user's
device. They are:
STATUS A, B, G- These three TTL lines are used to input status to the
DRV11-B from the user's device.
FUNGT 1, 2, 3-These three TTL lines are used to output status from
the DRV11-B to the user's device.
INIT, INIT V2-INIT is asserted when the LSI-11 bus INIT signal is
asserted. INIT V2 js asserted either when the LSI-11 bus INIT is asserted or when FUNCT 2 is a 1.
A TTN-ATTN terminates a DMA transfer. This sets the READY bit and
causes an interrupt (if the interrupt enable bit has been set).

324

DRV11-8
CONFIGURATION
The interface consists of five registers (Table 1): word count register
(WCR), bus address' register (BAR), control/status register (CSR),
input data buffer register (IDBR), and output data buffer register
(ODBR). The module also includes bus transceivers and logic for interrupt requests, address control and protocol, and DMA requests.

Table 1

Standard Addresses

Description

Mnemonic

Read/
Write

Address

WCR
BAR
CSR
IDBR
ODBR

R/W
R/W
R/W
R
W

172410
172412
172414
172416
172416

Interrupt
Interrupt Vector

124

The DRV11-B contains two switch packs, one to assign an appropriate
device address to the DMA interface and one to select an interrupt
vector.
The address of both the DRV11-8 interface and the interrupt vector is
selected by the position of the switches in switch pack S2 and 81,
respectively. The location of the switches on the module is shown in
Figure 8. The switches are set to the OFF position (open) to select a
zero bit and the ON position (closed) to select a one.
Device Address Format
The DRV11-B decodes four addresses, one for each of the registers
listed:
Register

Octal Address

WCR
BAR
CSR
DBR

1XXXXO
1XXXX2
1XXXX4
1XXXX6

325

DRV11-B
Jl

DEVICE ADDRESS
SELECTION SWITCHES

VECTOR ADDRESS
SELECTION SWITCHES

...

-0

Figure 8

DRV11- B Connector and Switch Locations

Normally, the addresses assigned to the DMA start at 772410a and
progress upward. Switches S2-1 through S2-10 select the base address as indicated by the X portion of the octal code; the individual
registers are decoded by the DMA interface. The relationship between the address format and the switches is shown in Figure 9.

15
1

)

I I

SWITCH

OFF

I IoI
1

OFF

101

I I a I I x Ix I x I
0

I I I I I

OFF

I I I I I I I I I I

OPEN = ZERO = OFF
CLOSED = ONE = ON

, 6

SWITCH S2
MR 1302

Figure 9

Device Address Switch S2 Selection

Interrupt Vector Selection
The interrupt vectors for the LSI-11 systems are allocated from 0-7748.
The recommended vector assigned to the DRV11-8 is 1248. Switches
S1-1 through S1-8 are used to select the vector. The relationship between the switches and the vector format is shown in Figure 10.

326

DRV11-8
15

SWITCH.

OPEN = ZERO = OFF
CLOSED = ONE = ON

I I I I I I I I
I I I I I I I I

OFF

OFr

OFF

SWITCH Sl
MR·1299

Figure 10

Interrupt Vector Switch S1 Selection

Registers
Each of the five registers can be addressed by the processor. The
IDBR and ODBR are assigned the same address and are read-only
and write-only, respectively.
Word Count Register (WCR) - The WCR (Figure 11) is a 16-bit readl
write counter which is loaded by the program with the 2's complement of the number of words or bytes to be transferred at one time
between memory and the 1/0 device. At the end of each transfer, the
WCR is incremented. When the count becomes zero (all 16 bits
0),
the DMA generates an interrupt request. The contents of the WCR
can be monitored by the processor program.

ADDRESS

xxxxxo _

00
READiWRITE

~~~~~~--~~--~~--~~--~~--~~--~~
i

16 BIT COUNTER

Figure 11 Word Count Register

Bus Address Register (BAR) - The BAR (Figure 12) is a 16-bit readl
write register used to generate the bus address which specifies the
location to or from which data is to be transferred. The register is incremented after each transfer. It will increment across 32K boundary
lines via the extended address bits in the control/status register. Bus
address bit 0 is driven by the user device.
Control and Status Register (CSR) - The CSR (Figure 13) contains 16
bits of information used to control the function and monitor the status of the DMA transfers. The information in the CSR can be modified
or read by the processor program in either 8-bit bytes or 16-bit words.
Table 2 lists and defines each of the 16 bits.

327

DRV11-8
ADDRESS

XXXXX2

0-7,

0-1,

Figure 12 Bus Address Register

ADDRESS

XXXXX4

'VtR·1303

Figure 13 Control/Status Register

Table 2

DRV11-B Control/Status Register Bit Description

Bit: 15
Name: Error
Description: (Read-only)
Indicates a special condition
NEX (bit 14)
ATTN (bit 13)
Sets READY (bit 7) and causes interrupt if IE (bit 6) is set.
Cleared by removing the special condition.
NEX is cleared by writing to zero.
ATTN is cleared by the user device.

Bit: 14
Name: NEX
Description: (Read/Write zero)
Nonexistent memory indicates that as bus master, the DRV11-8 did
not receive 8RPLY or that a DATIO cycle was not completed.
Sets error (bit 15).
Cleared by INIT or by writing to zero.

Bit: 13
Name: ATTN
Description: (Read-only)
Indicates the state of the ATTN user signal.
Sets error (bit 15).

Bit: 12
Name: MAINT
Description: (Read/Write)
Maintenance bit used with diagnostic program.

328

DRV11-B
Bit: 11
Name: STAT A
Description: (Read-only)
Device status bit that indicates the state of the DSTAT A, 8, and C,
user signals.
Set and cleared by user control only.
Bit: 10
Name: STAT 8
Description: (Read-only)
Device status bit that indicates the state of the DSTAT A, 8, and Couser
signals.
Set and cleared by user control only.
Bit: 9
Name: STAT C
Description: (Read-only)
Device status bit that indicates the state of the DST A T A, 8, and C user
signals.
Set and cleared by user control only.
Bit: 8
Name: CYCL
Description: (Read/Write)
Cycle is used to prime a DMA bus cycle.
Bit: 7
Name: READY
Description: (Read-only)
Indicates that the DRV11-8 is able to accept a new command. Requests an interrupt if IE (bit 6) is set.
Set by INIT.
Bit: 6
Name: IE
Description: (Head/Write)
Enables interrupts to occur when READY (bit 7) is set.
Cleared by INIT.
Bit: 5
Name: XAD 17
Description: (Read/Write)
Extended access bit 17; cleared by INIT.
Bit: 4
Name: XAD 16
Description: (Read/Write)'
Extended address bit 16; cleared by INIT.
Bit: 3
Name: FNCT 3
Description: (Read/Write)
One of three bits made available to the user device. User defined.
Cleared by INIT.

329

DRV11-B
Bit: 2
Name: FNCT 2
Description: (Read/Write)
One of three bits made available to the user device. User defined.

Cleared by INIT.
Bit: 1
Name: FNCT 1
Description: (Read/Write)
One of three bits made available to the user device. User defined.

Cleared by INIT.
Bit: 0
Name: GO
Description: (Write-only)
Causes "NOT READY" to be sent to the user device indicating a command has been issued. Clears READY (bit 7). Enables DMA transfers.
Input Data Buffer Register (IDBR) - The IDBR (Figure 14) is used for
read-only operations. Data is loaded into the register by the user's device. The data may be read from the IDBA as a 16-bit word, an 8-bit
high byte or an 8-bit low byte. Transfers are usually via DATO or DATOB DMA bus cycles. The register input connects to J2 mounted on
the module.

ADDRESS
XXXXX6

15
8 BIT HIGH BYTE

8 BIT LOW BYTE

~~~~~~----~~--~~--~~--~~--~~--~~

16 BIT DEVICE INPUT DATA WORD
MR 1304

Figure 14 Input Data Buffer Register
Output Data Buffer Register (ODBR) - The ODBA (Figure 15) is used
during write-only operations. Data from the LSI-11 bus is loaded into
the register under program control and read from the register by the
user's device. The register can be loaded with a 16-bit data word or
with an 8-bit high byte or an 8-bit low byte. Transfers are usually via
DATI or DATIO DMA bus cycles. The output of the register connects
to J1 on the module.

ADDRESS
XXXXX6

8
8 BIT HIGH BYTE

8 BIT LOW BYTE

~~~----~~--~~----~~----~~--~~--~~----~~

16 BIT DATA WORD

Figure

Ouput Data Buffer Register

330

DRV11-B
PROGRAMMING

The DRV11-B interface operates as both a slave and a master device.
Prior to becoming bus master, all data transfers out (DATa) or data
transfers in (DATI) are in respect to the processor. Once the DRV11-B
is granted bus mastership by the processor, all data transfers are in
respect to the DRV11-B.
DMA operation is initialized under program control by loading the
WCR with the 2's complement of the number of words to be transferred, loading the BAR with the first address to or from which data is
to be transferred, or loading the CSR with the desired function bits.
After the interface is initialized, data transfers are under control of the
DMA logic.
Program Control Transfers
Data transfers may be performed under program control byaddressing the IDBR or ODBR and reading or writing data.
DMA Control Transfers
DMA input (DATI) or output (DATa) data transfers occur when the
processor clears READY. For a DATa cycle (DRV11-B to memory
transfer), the user's I/O device presets the control bits [word count
increment enable (WC INC ENB), bus address increment enable (BA
INC ENB), C1, CO, ADO, and ATTN], and asserts CYCLE REQUEST to
gain use of the LSI-11 bus. When CYCLE REQUEST is asserted, input
data is latched into the input DBR, the control bits are latched into the
DRV11-B DMA control and BUS goes low. A DATI cycle-memory to
DRV11-B transfer-is handled in a similar manner, except that the
output data is latched into the output DBR at the end of the bus cycle.

When the DRV11-B becomes bus master, a DATa or DATI cycle is
performed directly to or from the memory location specified by the
BAR. At the end of each cycle, the WCR and BAR are incremented and
BUSY goes high while READY remains low. A second DATa or DATI
cycle is performed when the user's 1/0 device again asserts CYCLE
REQUEST. DMA transfers will continue until the WCR increments to
zero, at which time READY goes high and the DRV11-B generates an
interrupt (if interrupt enable is set) to the processor.
If burst mode is selected (SINGLE CYCLE low), only one CYCLE
REQUEST is required for the complete transfer of the specified number of data words.
Device Cables and Signals
Data, status, and control signals are transferred between the user's

331

DRV11-8
liD device and DMA by an input and an output cable assembly. The
input cable attaches to connector J2 and the output cable attaches to
connector J 1. Tables 3 and 4 list the connector pin and designations
for each signal. Table 5 lists several recommended cable assemblies
that are available from DIGITAL in the lengths indicated. The H856
female connector mates with either J1 or J2 on the DRV11-S. To order
cable assemblies in lengths not listed, contact a DIGITAL sales office.
Cables up to 15.2 m (50 ft) maximum may be used.

Table 3

DRV11-8 Input Connector Signals

J2*
Connector Pin

Signal Name

S
D
F
J

SU8YH
ATTNH
AOOH
SA INC ENS H

10 (drive)
1
1
1

FNCT3 H
COH
FNCT 2 H
C1H
FNCT 1 H
081N H
091N H
10lN H
111N H
121N H
131N H
141N H
151N H
071N H
06INH
051N H
041NH
031N H
02 IN H
011N H
OOIN H

10 (drive)

~}
N
R
T
V
DD
FF
JJ
LL
NN
RR
TT
VV
CC
EE
HH

KK
MM

pp
88
UU

Unit Loads

1
10 (drive)
1
10 (drive)

* All remaining pins connect in common to logic ground by board etch.

332

DRV11-B
Table 4

J1*
Connector Pin
S

F
J
K
L
N
R

~}
DO

FF
JJ
LL
NN
RR
TT
VV
CC
EE
HH
KK

MM
pp
SS
UU

DRV11-B Output Connector Signals

Signal Name
CYCLE REQUEST H
INITV2H
READY H
WC INC ENS H
SINGLE CYCLE H
STATUS A
INIT H
STATUS S
STATUS C
OBOUT H
09 OUT H
10 OUT H
11 OUT H
12 OUT H
13 OUT H
140UT H
15 OUT H
07 OUT H
06 OUT H
05 OUT H
04 OUT H
030UT H
02 OUT H
01 OUT H
OOOUTH

Unit Loads
1
10 (drive)
10 (drive)
1
1
1
10 (drive)
1
1

10 (drive)

* All remaining pins connect in common to the logic ground by board etch.

333

DRV11-B
Table 5

Recommended Cable Assemblies

Cable No. Connectors

Type

BC07D-XX HB56 to open end

2,20 conductor 10, 15, 15
ribbon

BCOBR-XX HB56 to HB56
Shielded flat
BC04Z-XX HB56 to open end Shielded flat

Table 6

Standard Lengths (ft)

1,6,10,12,20,25,50
6,10,15,25,50

DRV11-B Interface Connector Signals

Mnemonic

Description

00 OUT -15 OUT

16 TTL data output lines from the DRV11-B.
One = high.

OOIN -151N

16 TTL data input lines from the user's device. One = high.

STATUS A, B, C

Three TTL status input lines from the user's
device. The function of these lines is defined by the user.

FUNCT 1, 2, 3

Three TTL output lines to the user's device.
The function of these lines is defined by the
user.

INIT

One TTL output line; used to initialize the
user's device.

INITV2

One TTL output line; present when INIT is
asserted or when FUNCT 2 is written to a
one. Used for interprocessor buffer applications.

AOO

One TTL input line from the user's device.
This line is normally high for word transfers.
During byte transfers this line controls address bit 00.
334

DRV11-8
Table 6

DRV11-B Interface Connector Signals

Mnemonic

Description

SUSY

One TTL output line to the user's device.
SUSY is low when the DRV11-S DMA
control logic is requesting control of the
LSI-11 bus or when a DMA cycle is in progress. A low-to-high transition indicates end
of cycle.

READY

One TTL output line to the user's device.
When the READY line goes low, DMA transfers may be initiated by the user's device.

CO, C1

Two TTL input lines from the user's device.
These lines control the LSI-11 bus cycle for
DMA transfers. CO, C1 codes for the four (4)
possible bus cycles as listed below:

Bus Cycle CO
DATI
0
1
DATIO
DATO
0
DATOS
1
SINGLE CYCLE

C1
0
0
1
1

One TTL input line from the user's device.
This line is internally pulled high for normal
DMA transfers. For burst mode operation,
SINGLE CYCLE is driven low by the user's
device.

CAUTION: When SINGLE CYCLE is driven
low, total system operation is affected because the LSI-11 bus becomes dedicated to
the DMA device and other devices cannot
use the bus.
WC INC ENS

One TTL input line from the user's device.
This line is normally high to enable incrementing the DRV11-S word counter. Low
inhibits incrementing.

SA INC ENS

One TTL input line from the user's device.
This line is normally high to enable incrementing the bus address counter. Low inhibits incrementing.

335

DRV11-B
Table 6

DRV11-8 Interface Connector Signals

Mnemonic

Description

CYCLE REQUEST

One TTL input line from the user's device. A
low-to-high transition of this line initiates a
DMA request.

ATTN

One TTL input line from the user's device.
This line is driven high to terminate DMA
transfers, to set READY, and to request an
interrupt if the interrupt enable bit is set.

As bus master, the DRV11-B performs a DATa or DATOB bus cycle by
placing the memory address on BDAL lines, asserting BWTBT, and
then asserting BSYNC. The memory decodes the address, then the
DRV11-B removes the address from the BDAL lines, negates BWTBT
(BWTBT will remain active for a DATOB), places the user's input data
on the BDAL lines and asserts BDOUT. Memory receives the data and
asserts BRPL Y. In response to BRPL Y, the DRV11-B negates BDOUT
and then removes the user's input data from the BDAL lines. Memory
now negates BRPL Y, the bus cycle is terminated, and the bus released
when the DRV11-B negates BSACK and BSYNC.
At the end of the first transfer, the DRV11-B WCR and BAR are incremented, BUSY goes high, and READY remains low. With BUSY high
and READY low, the user's 1/0 device can initiate another DATa or
DATOB cycle by again asserting CYCLE REOUEST.lf the interrupt
enable is set, DMA transfers can continue until the WCR increments to
zero and generates an interrupt request.When the WCR increments to
zero, READY goes high, and the DRV11-B generates an interrupt request (if the interrupt circuits are enabled). The processor responds to
the interrupt request (BIRO) by asserting BDIN followed by BIAKI
(interrupt acknowledge). BIAKI is received by the DRV11-B and in
response places a vector address on the BDAL lines, asserts BRPL Y,
and negates BIRO. The processor receives the vector address and
negates BDIN and BIAKI. The DRV11-B now negates BRPL Y, while the
processor exits from the main program and enters a service program
for the DRV11-B via the vector address.
Interrupt requests from the DRV11-B occur for the following conditions:
1. When the WCR increments to zero-this is a normal interrupt at
the end of a designated number of transfers.

336

DRV11-B
2.

When the user's I/O device asserts ATTN-this is a special condition interrupt which may be defined by the user to override the
WCR.
When a nonexistent memory location is addressed by the DRV11S-this special condition interrupt is produced when no SRPL Y is
received from the memory.

System Memory to User's Device Transfers (DATIO or DATI)
DMA transfers from the memory to the user's 1/0 device occur in a
manner similar to that described for user's 1/0 device to memory
transfers. Figure 3 illustrates the data flow for a DMA DATIO or DATI
cycle. Under program control, the DRV11-B WCR (Figure 11) is loaded
with a count equal to the number of transfers, while the BAR is loaded
with the starting address from which the first word will come; the
CSR is set for transfers.
With the CSR set, READY goes low and the user's I/O device conditions the CO, C1 lines (Table 6) for a DATI or a DATlO, conditions the
WC INC ENS, SA INC ENS, ATTN, SINGLE CYCLE (high for normal
DMA transfers) Signals, and asserts CYCLE REQUEST.

337

DRV11-J
HIGH DENSITY PARALLEL INTERFACE
INTRODUCTION
Sixty-four input/output data lines are now available on a doubleheight module for the LSI-11/2, LSI-11/23, PDP-11/03, and PDP11/23. The DRV11-J also includes an advanced interrupt structure
with bit interruptability up to 16 lines, programmable interrupt vectors,
and program selection of fixed or rotating interrupt priority within the
DRV11-J.

The DRV11-J's bit interrupts for realtime response make it especially
useful for sensor I/O applications. It can also be used as a general
purpose interface to custom devices, and two DRV11-Js can be connected back-to-back as a link between two LSI-11 buses.
FEATURES
• 64 tri-state bidirectional input/output lines organized as four 16-bit
ports, A through D.

• Data line direction selectable under program control for each 16-bit
port.
• Transitions on each of the 16 lines of Port A can generate unique
interrupt vectors (bit interrupts). This means high-priority inputs get
serviced by the CPU much faster.
• Transitions on the USER RPL Y lines of each port can generate
unique interrupt vectors (I/O interrupts). This means less processor
overhead. By selecting this feature, bit interrupts are reduced to 12.
• Double-height module: 22.Bcm x 13.2cm (B.9 in x 5.2 in )
• Drive up to 25 feet of shielded cable, 6 feet of unshielded flat or
round cable.
• Four external control lines per port: USER RDY, USER RPL Y,
DRV11-J RDY, and DRV11-J RPLY.
• Interrupt vectors (fixed or rotating priority) are set under program
control. This eliminates the need for jumper-defined vectors.
• Latched outputs, PNP-Schmitt-trigger inputs.
SPECIFICATIONS
MB049
Identification
Power
+5V±5% 1.6A typical, 1.BA maximum

Bus Loading:
2 ac loads, 1 dc load

33B

DRV11-J
Data Buffer Tri-State Outputs:
V OL = 0.5V @ I OL = B mA
V OL = O.4V @ I OL = 4 mA
VOH = 2.4V@!OH = -2J,mA
Data Buffer Inputs:
IlL = -0.2 mA @ V IL = O.4V
I IH = 20 JLA @ V IH = 2.7V
Protocol Signal Tri-State Outputs:
V OL = 0.55V @ I OL = 64 mA
V OH = 2.4V @ IOH = -15 mA
Protocol Signal Inputs:
Termination: 120 ohms
IlL
-27 rnA @ VIL
0.5V

=
=
IIH = 80/LA @ VIH = 2.7V

Environmental:
Storage temperature: -40°C to +60°C
Operating temperature: +5°C to +60°C
Adequate airflow must limit the inlet to outlet temperature rise to 10°C
(5°C if inlet air is 55°C).
NOTE
Derate maximum operating temperature by 1.BoC
for each 1000 meters of altitude above sea level.

Humidity: 10% to 90%, non-condensing
Size
Double-height module:
13.2cm (5.2in ) wide
22.Bcm (B.9in ) long
Cabling:
BC05W-xx-Shielded cable with 50-pin connectors at both ends.
Available in 3.0 and 7.5 meter (10 and 25 foot) lengths.
DESCRIPTION
Detailed information about the DRV11-J is supplied with the module.

339

DRV11-J
PROGRAMMING
The DRV11-J is programmed through eight contiguous directly addressable registers, which may be positioned to start from 7600008
through 777760 8 in address space by stake pin jumpers. There are
four Control Status Registers and four Data Buffers.
The Registers are:
Control Status Register A
Data Buffer Register A
Control Status Register B
Data Buffer Register B
Control Status Register C
Data Buffer Register C
Control Status Register D
Data Buffer Register D

(CSRA)
(DBRA)
(CSRB)
(DBRB)
(CSRC)
(DBRC)
(CSRD)
(DBRD)

7XXXXO a
7XXXX2a
7XXXX4a
7XXXX6 a
7XXX10 a
7XXX12a
7XXX14a
7XXX16 a

XXX X is jumper-selectable between '6000 a to 7776 a in a modulus of
16 and factory-set to 6416 a (CSRA = 764160 a ).
The format of these registers is shown in Figure 1.
Unlike other LSI-11 interface modules, the DRV11-J uses two sets of
eight internal registers to control interrupts. The first set of registers is
controlled through CSRA and CSRB and is responsible for interrupts
generated in bits 0-7 of Port A. The second set of registers is controlled through CSRC and CSRD and is responsible for either bits 8-15
of Port A or, when I/O interrupts are selected, the four USER RPL Y
lines and bits 8-11 of Port A (see Figure 1).
IRR
ISR
IMR
ACR

Interrupt Request Register
Interrupt Service Register
Interrupt Mask Register
Auto Clear Register
Status Register
Mode Register
Command Register
Byte Count
Vector Address Memory

Interrupt vectors are stored in Vector Address Memory. Vector addresses can be set from 0 to 1774a and must be loaded on power-up.
To provide for dynamic changing of interrupt subroutines, vectors are
programmable. Four vectors are available for each of the sixteen interrupts.

340

DRV11-J
CSRA
Location:::: device address

o
\.

USER
READY

~e?dTa~~~~

A
(READ
ONLY)

:NTERRUPT II
ENABLE
(READ/
WRITE)

~-----------v-------------~J
INTERRUPT CONTROL
STATUS/COMMAND - a LINES
(READ/WRITE)
• Not reset by binil
• Reset
• Manipulate internal registers
-Interrupt Request Register
-Interrupt Mask Register
-Interrupt Service Register
- Mode Register
- Read Status Register
• Preselect internal memory for
reading/writing through CSRB
- Vector Address Memory
- Interrupt Request Register
- Interrupt Mask Register
-Interrupt Service Register
. Auto Clear Register

DIRECTION
PORTA
(READ/WRITE)

CSRB
Location:::: device address + 4

UdERI.~-----y
READY
(READ
ONLY)
CSRC
location:::. device address + 8

read as zeros

,~-----~y

USER
READY

read as zeros

--------------Y'-----------~J
INTERRUPT CONTROL DATA
(READ/WRITE)

• As preselected in CSRA

:\.

:=g

DIRECTIONPORTC
(READ/WRITE)

NOT USED

DIRECTION
PORTB
(READ/WRITE)

NOTUSED

INTERRUPT CONTROL
STATUS/COMMAND - a lines
(READ/WRITE)

(READ
ONLY)

• Same as CSRA

CSRD
Location:::: device address + 12

I :

~'--------------_v-_---------------J

DIRECTlONPORTO

INTERRUPT CONTROL DATA - a lines
(READ/WRITE)
• As preselected in CSRC

DBRA. DBRB. DBRC. DBRD
Location:::: device address = + 2. + 6. -r-1 o. ~ 14 respectively

~~-------------------------------v_------------------------------J
INPUT DATA (when READ)
OUTPUT DATA (when WRITE)

Figure 1

341

DRV11-P
DRV11-P LSI-11 BUS FOUNDATION MODULE
INTRODUCTION

The DRV11-P is an LSI-11 bus-compatible foundation wire-wrap interface module. Approximately one-quarter of the module is occupied by
bus transceivers, interrupt vector generator logic, and a 40-pin I/O
connector. The remaining three-quarters of the module is for user application and has plated-through holes to accept ICs and wire-wrap
pins (WP) for interconnecting the user's circuits. The plated-through
holes can accept 6-, 8-,14-,16-,18-,20-,22-,24-, and 40-pin dual-in-line
ICs or IC sockets in various mounting areas of the module, or discrete
components can be inserted into the plated-though holes. The
DRV11-P can be inserted into anyone of the available interface option locations of any LSI-11 bus.
FEATURES

• An easy-to-use foundation module for custom interface applications.
• Factory-installed LSI-11 bus-compatible interface circuits.
• Device and interrupt vector that can be configured by the user.
• Compact-occupies only two device locations on the bus.
• Can accommodate up to 50 integrated circuits making up the
user's device logic.
• Wire-wrap pins are provided for all signals.
• All user control signal lines are TTL-compatible.
SPECIFICATIONS

Identification

M7948

Size

Quad

Power

5.0Vdc ±5% at 1.0A

Bus Loads
ac
dc

2.1
1 (plus user's logic)

CONFIGURATION

The DRV11-P (Figure 1) is a versatile wire-wrap module that contains
interface logic for operation with the LSI-11 bus and provides adequate board area for mounting and connecting integrated circuits
(ICs) or discrete components. Because the bus interface logic is in342

DRV11-P
cluded, the module can be efficiently configured by the user to satisfy a variety of device interface logic applications.
A 40-pin connector mounted at the board edge connects to a device
through several cable assembly types available from DIGITAL.
Except for the bus interface connections, all signals and voltages are
terminated to wire-wrap pins for user connections. The bus control
logic is provided with wire-wrap test pOints for monitoring the internal
signals. The test points are spaced at 0.254 cm (0.1 in.) between pins
to let the 40-pin connector be inserted over the wire-wrap pins for automated test functions.
Approximately two-thirds of the surface area on the module consists
of plated-through holes, each connected to a wire-wrap pin. The user
can mount three different types of dual-in-line les or a variety of discrete components into the holes and connect the proper voltages and
signals by wire-wrapping leads on the board.

Device Address Selection
The DRV11-P will respond to up to four consecutive addresses in the
bank 7 area (addresses between 160000a and 1777768). The register addresses are sequential by even numbers and are as follows:

3
4

BBS7
1
1
1
1

Octal Address
16XXXO
16XXX2
16XXX4
16XXX6

The user selects a base ending in zero for assignment to the first register by means of wire-wrap pins on the DRV11-P module. The module
decodes this base address and the remaining register addresses are
then properly decoded by the DRV11-P as they are received from the
LSI-11 bus.
Figure 2 shows the address select format and presents the wire-wrap
pin-to-bit relationship for device address selection. Bits to be decoded as 0 bits in the base address are wire-wrapped to ground wire-wrap
pins (WP). Bits to be decoded as 1 bits are left unwrapped as these
bits are pulled up to the 1 state.
343

+5V WIRE-W!l:AP PIN
lIPPERR1(,YT
PINor FIRST
VI!RE-WRAP PIN., fD, CONN[C f1N:J

GROUND WIRE-WRAP PIN
UPPER LEFT
PIN OF FIRST
FIVE MOUNTING
AREAS

WIRf-WRAPPINS
FOR INTERCONNECTING
USER IC'S

5:
l!~:

J K

••

[TI[] : ! [Q[J: ~ CTI!J :

10:

THR[F WIRE-WRAP PIN:'
FO~ ACCOMMODATlf-JG
CAlli f (;~O~JNDS

--:-i - -!-.-+~
i-h
o
•
0

'"0:

25:

~
N

....UJ

Z
UJ

...

20:

'"0:

....UJ

Z
UJ

30:

'":
.",
.~ Q:

••

"UJ

~::- -.~-- -t-.--~
o ••
ci

-z

"3: .

.... u

-l-5V WIRE -WRAP PIN
lOWER RIGHT
PIN OF All
MOUNTING
AREAS.
DESIGNATED
8Y PLUS (+)
SIGN.

.....

",UJ

3:a.
•U) - :

'01
: :81

0:'"

"-::;

GROUND WIRE-WRAP PIN
LOWER LEFT
PIN Of ALL
MOUNTING
AREAS. \
DESIGNATED
BY MINUS (-)
SIGN.
USER WIRE-WRAP

PINS fORCONNKTING
USER LOGIC TO "C'"
AND "D" DRVII-P
MODULE FINGERS

c
IlIAK[ l
81AKO l
CONTINUITY JUMPER.
REMOVl ONLY WHEN
USING THE CN2 AND
CM2 MODULt liNGERS.

aOMGI l - 80M GO I
CONTINUITY JUMP! R.
REMOVf ONLY WHtN
USING THE CR2 AND
07 MODULI flNGH!~.

B
.]V WJRl-WRAP PIN
IQRPUlllNG-IJp
tJNUSfD GAlf
INPUTS, He.

BOMGI L - BOMGO l
CONflNUITY JUMPlR.
RrMO,JE ONLY W.l/"N
OM,/\, GRANT ARBITRATION
lOGIC JS CUNSTRlICTtO
OI'J :JRVI J.j> MODUl.!.

SPlIT LUGS TO ACCOMMODATE
EXHRNAL CAPACITOR (CJ91 W:-tEN
l>.DJUSTlNG D~LAY BETWEEN
BDIN L. BDOUl l, AND
BETWEEN VECTO~ H INPUTS
l>.ND BRPlY l.
11-'1152

Figure

::z:J

<
.....

.....
•
."

-'"

wE
H

.JV WIRE-W!l:AP PIN
fOi{ PULLING-UP
UNUSED GATE
INPUTS, ETC.

DRV11-P Component Mounting Locations

DRV11-P
DECODED
BY BBS7

DECODED FOR
1 OF 4
REGISTERS

SELECTED By WIRE - WRAP PINS

,--------'----~ ~------"-------__"

r---"-------,
02

BYTE
CONTROL

WI RE - WRAP
TO A GROUND
WP FOR "ZERO"
BITS IN THE
ADDRESS

Figure

0 0 0'

:
wP'

I
WP I

63;

67 I

68 I

DRV11-P Device Address Select Format

Interrupt Vector Logic - The interrupt vector logic is used in conjunc- .
tion with the interrupt control logic to gener.:'te a vector on bus lines
BDAL 00 L-BDAL 07 L. The interrupt vector is specified by the user
and selected by installing jumper leads between wire-wrap pins on
the M7948 module. The vectors available are from 0 to 374a. The vector
range can be increased from 0 to 774a with additional logic and wiring.
When the VECTOR H signal is asserted as a result of a device interrupt request, the interrupt vector is placed on the bus lines.
Wire-wrap pins V3 through V7 are used to assign the vector bits. A
jumper lead installed selects a logical 0 address bit for its associated
line and no lead selects a logical 1 address bit according to the format in Figure 3.
Bit BDAL 02 L can be connected to the device interrupt request RQST
A signal to specify a separate vector address for channel A and channelB.
Status and control information can be multiplexed through the same
logic used to generate the vector address. Up to eight status and control bits can be assigned by the user and transferred to bus lines
BDAL 00 L-BDAL 07 L. The information can be gated onto the bus
lines using a select level generated by the address decoding logic.

345

DRV11-P
LEAST
SIGNIFICANT
OCTAL PREASSIGNED
DIGIT
AS
(0 OR 4)
ZEROS

2 NO
OCTAL
DIGIT

I ST
OCTAL
DIGIT

~,------A-----.,
08

r---'

81\~~ ~~~'~~g~~

ADDRESSING ~-------..,
SEE TE X T
L - __ '--y----'---,---'-.---'-...-'-----,C-.L-. .-'---'---...J

WIRE- WRAP
TO A GROUND
WP FOR "ZERO"
BITS IN THE
ADDRESS

(SEE TEXT)

----<

Figure

~ I
Wp?

~;L

FROM INTERRUPT LOGIC

DRV11-P Vector Selection

346

DUV11
DUV11 LINE INTERFACE
INTRODUCTION
The DUV11 line interface is a buffered; program-controlled, sing!e-line
communications interface device which is used to establish a data
communications line between any LSI-11 bus and a Bell 201 synchronous modem or the equivalent. The module is fully programmable
with respect to sync characters, character length (5 to 8 bits), and
parity selection. The DUV11 provides serial-to-parallel and parallel-toserial data communications, buffers TTL-to-EIA voltage levels and
EIA-to-TTL voltage levels, and controls the modem for half- or fullduplex operation.
FEATURES
• Interfaces synchronous and isochronous communications data
• Supports bisynchronous communications data
.. Interface signals meet EIA RS-232C standard

• Operates in full-duplex or half-duplex modes
• Maximum baud rate is 19.2K baud
• Uses variable length characters (5, 6, 7, or 8 bits plus parity)
• Generates odd or even parity bits that are transmitted with the data
character to the modem
• Verifies received character parity
• Inhibits transmitter output for maintenance purposes
• Provides control signals to the modem and monitors the modem
status lines
• Establishes synchronization prior to receiving data
• Generates program interrupt re-quests

SPECIFICATIONS
Identification

M7951

Size

Quad

Power

+5 Vdc ±5% at 0.86A
+12 Vdc ±3% at 0.32A

Bus Loads
AC
DC

1
1

347

DUV11
CONFIGURATION
The following paragraphs describe how the user can configure the
module for his own system. This module contains switches to select
the device address, vector interrupt, and special control functions.
The descriptions of the registers and their standard factory addresses
are listed in Table 1 and described below.

Table 1

DUV11 Factory Address Assignments

Mnemonic

Receiver Status
Receiver Data Buffer*
Parameter Status*
Transmitter Status
Transmitter Data Buffer
Interrupt Vector

RXCSR
RXDBUF
PARCSR
TXCSR
TXDBUF
DONE

Read/
Write

DUV11
Address

R/W
R
W
R/W
W

160010
160013
160012
160014
160016
440

Dual-purpose read or write register.

Device Address
The LSI-11 bus address and interrupt vector addresses, which are
selectable, must be determined prior to operating the DUV11. The bus
address (also referred to as the device address) is controlled by
switches contained in the two switch banks E38 and E39 (Figure 1),
located in the address comparator logic. The position of these switches determines the required address state (1 or 0) of bus address bits
12-3. If a switch is set to ON, the switch contacts are closed and an
address state of 1 is required on the related address bit to the address
of the DUV11. Hence, electrically, the DUV11 can have any device
address within the range of 160000 to 177777. However, DIGITAL software requires that the device address fall within the floating address
range of 160010 to 163776. The device address is set to 160010 at the
factory to facilitate manufacturing testing. The switch positions for
address selection are described in Table 1 and Figure2.
NOTE
If a device address is selected which falls outside the
floating address range, the software must be modified accordingly.
348

DUV11
CARRIER

SERIAL DATA OUT ~

SERIAL DATA I N \
OPTION
SWITCHES

TRANSMITTER

CHIP

RECEIVER
CHIP

ADDRESS/VECTOR
ROCKER SWITCHES
:'V1R 0816

Figure 1

DUV11 (M7951) Major Components

OFF OF F OF F OFF OFF OFF OFF OFF OFF

~ ~2 ~ ~ ~5 ~ ~ 8~ ~ ~
I

SWITCH NO. \ 1

E38 SWITCH
LOGICAL 1 = ON
LOGICAL 0 = OFF
FACTORY ADDRESS 1600

Figure 2

~
E39
SWITCH

o RXCSR
1 TXCSR
TXDBUF

Device Address Selection

349

DUV11
Interrupt Vector
The interrupt vector is also floating and is set to 440 at the factory to
facilitate factory testing. If it is necessary to change the vector, simply
change the six vector select switches contained in switch bank E39
(Figure 1) as required. These switches control vector bits 8-3; therefore, vectors can be generated in the range 000 to 774. However, the
software requires that the vector fall within the floating range of 300 to
777. The switch settings for vector selection are shown in Figure 3.
NOTE
If a vector is selected which falls outside the floating
address range, the software must be modified
accordingly.

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
10101010101010111 0 10111 0 10lxlolol

r r r r r r L~ ~~~~

ON OFF OFF ON OFF OFF
LOGICAL1=ON
LOGICAL 0 = OFF
FACTORY ADDRESS

SWITCH NO.

440

Figure 3

t t ~ t t
4

5. 6

E39 SWITCH

'lttR 1110

Interrupt Vector Selection

Option Switches
The DUV11 can select optional control functions that are used during
operation by using switches S 1 through S8 of E55. The detailed operation of these switches is listed in Table 2.
Table 2

Switch Assignments

Switch No.*

Function

SW1

Optional Clear-Switch ON enables CLR OPT, which
is used to clear RXCSR bits 3, 2,and 1.

SW2

Secondary Transmit-Switch ON enables secondary
data channel between the modem and DUV11.

* All switches are located on component reference designation E55.

350

DUV11
Table 2
Switch No. *

Switch Assignments (Cont)

Function

SW3

Secondary Receive-Switch ON enables secondary
data channel between the modem and DUV11.

SW4

Sync Characters-Switch ON enables the receiver to
synchronize internally upon receiving one sync character. The normal condition of receiving two sync
characters exists when SW4 is off.

SW5

Special Feature-Switch ON allows external clock to
be internally generated; used when a modem is not
being utilized.

SW6

Special Feature-Optional feature is switched ON
for program control of data rate selection.

SW7

Maintenance Clock-Switch ON enables the clock
that is used for maintenance purposes only.

SW8

Not used.

* All switches are located on component reference designation E55.

Optional Equipment
Mating Connector
Cable

H836
SC05C-XX

351

DZV11
DZV11 ASYCHRONOUS MULTIPLEXER
INTRODUCTION

The DZV11 is an asynchronous multiplexer interface module that interconnects the LSI-11 bus with up to four asynchronous serial data
communications channels. The module provides EIA interface levels
and enough data set control to permit dial-up (auto-answer) operation
with modems using full-duplex operations such as Bell models 103,
113,212, or equivalent. The DZV11 does not support half-duplex operations such as remote operation over private lines for full-duplex
point-to-point or full-duplex multipoint as a control (master) station.
The DZV11-B includes a BC11 U cable assembly for interconnection to
the communication devices.
The DZV11-B interface consists of the M7957 module, a BC11U-25 interface cable, and two accessory· test connectors (H329 and H325).
The H329 connector permits a staggered loopback. The H325 connec'tor is used with the BC11 U cable to provide the single-line loopback.

FEATURES

• Selectable baud rates of 50 to 9600
• Character length of 5, 6, 7, or 8-bits
• Stop bits, 1 or 2, for 6-, 7-, and 8-bit characters
• Stop bits, 1 or 1.5, for 5-bit characters
• Parity generation and detection for odd, even, and no parity
• Transmitter and receiver interrupts
• Generates and detects break signals
SPECIFICATIONS

Identification

M7957

Size

Quad

Power

+5Vdc ±5%at1.15A
+12Vdc ±3% at 0,40 A

Bus loads
ac
dc

4.1
1

Interface

EIA standard RS-232C

352

DZV11
CONFIGURATION

The software control of the DZV11 is performed by six device registers. These registers are assigned addresses and can be read or loaded by the program. DIGITAL software requires that the device addresses be within the range of 760000 to 777777. The M7957 module
utilizes the floating address space that starts at 760010 and extends
to 764000. The control and status register (CSR) is assigned the basic
address by setting the rocker switches of E30 on the module, as
shown in Figure 1. The correlation between the bit assignments and
the switches is detailed in Figure 2. The remaining register addresses
will sequentially follow the basic address, as shown in Table 1. A basic address is preset at the factory; if the user requires a different address, the switches allow him to change the addresses to comply
with his system. The interrupt vector is also programmable and can
be used with DIGITAL software, provided that the address is within
300 to 777. The switches of E2 on the module allow the user to select
an interrupt vector to function within his system. The correlation between the bit assignments and the switches is detailed in Figure 3.

[\~------,r;
i

W5
WB

~I________~

-r-B EJ::::. W6

'---------', '---~

-----'

_-----"I '---~_----'

'----?

W1 -.---!:
W4

~W2

~W3

Wg'

/=;,\
W13*

W14* W15* W16*

WijQQQQQul
W10*

W11*

ADDRESS SWITCHES

VECTOR SWITCHES

~C£
*NOTES:
JUMPERS W9, W12, W13, W14, W15, AND W16 .~.RE REMOVED ONLY FOR MANUFAC
TURING TESTS.
THEY SHOULD NOT BE RE'~. DVED IN THE FIELD.
JUMPERS W10 AND W11 MUST REMAIN IN~TALLED WHEN THE MODULE IS USED IN
A BACKPLANE THAT SUPPLIES LSI·11 BUS SIGNALS TO THE C AND D CONNECTORS
OF THE DZV11 (SUCH AS THE H92701.
WHEN THE MODULE IS USED IN A BACK·
PLANE THAT INTERCONNECTS THE C AND D SECTIONS TO AN ADJACENT MODULE,
JUMPE RS W10 AND W11 MUST BE REMOVED.

Figure

1 M7957 Module

DZV11
BITS 15

FACTORY
CONFIGURATION
CSR 160010

00000

000

!!!!!!!!! !

1 = SWITCH ON
0= SWITCH OFF

10, SWITCH

SWITCHES E30

Figure

Table 1

MR·1161

DZV11 CSR Address Bits

DZV11 Register Address Assignments

Mnemonic

Address·

Control and Status
Receiver Buffer
Line Parameter
Transmitter Control
Modem Status
Transmit Data

CSR
RBUF
LPR
TCR
MSR
TOR

76XXXO
76XXX2
76XXX2
76XXX4
76XXX6
76XXX6

Readl
Write

R/W

R
W

R/W

R
W

xxx = Selected in accordance with floating device address scheme. Dualpurpose register.

BITS 15

VECT~;R~~~RESS

0 ! 0 ! 0

I I I
0

val v71 v61 V5! v41 V3! 0 ! 0

I I I

111I 1 I

FACTORY
CONFIGURATION
=300
1 = SWITCH ON
2 = SWITCH OFF

,--_2_3c:.....,

I I
0

+ + + + ,5 ,6,
SWITCHES E2

Figure

',1R'11>'2

DZV11 Vector Bits

Jumpers
Modem Control - There are eight jumpers (W1-W8) used for modem
control. Jumpers W1 and W4 connect data-terminal-ready (DTR) to request-to-send (RTS). This allows the DZV11 to assert both DTR and
RTS when using a modem that requires the control of RTS. These

354

DZV11
jumpers must be installed to run the external cable and test diagnostic programs. Jumpers W5 through W8 connect the forced-busy leads
to the request-to-send leads. When these jumpers are installed, the
assertion of an RTS signal places an ON or busy signal on the corresponding forced busy iead. Forced busy jumpers W5-W8 are normally
removed unless they are required for the modem. These modem control jumpers are listed in Table 2.

Table 2

Modem Control Jumper Configuration

Jumper

Connection

Line

DTR to RTS

DTRto RTS

RTSto FB

Bus Signals - Jumpers W10 and W11 must remain installed when
the module is used in a backplane that supplies bus signals to C and
o connectors such as the H9270. When the module is in a backplane
that uses the C-D interconnect scheme (such as the H9273), the jumpers W10 and W11 must be removed.

Jumpers W9 and W12 through W16 are removed for manufacturing test purposes only. These jumpers should not be removed
by the user.

Testing -

Device Registers - All software control of the DZV11 is performed by
six device registers. Each register is assigned a bus address that can
be read or loaded.

355

DZV11
Control and Status Register - The control and status register (GSR)
is a byte- and word-addressable register. All bits in the GSR are
cleared by an occurrence of BINIT or by setting device master clear
(GSR 4).

356

H780
H780 POWER SUPPLY
INTRODUCTION
Six H780 power suppiy options are avaiiabie for use in system applicatons. The six models provide for a choice of input voltage (115 Vac
or 230 Vac, nominal), and master console, slave console, or no console.

All models are used for supplying dc operating voltages to an LSI-11
bus backplane. In addition, each model generates a proper power-up/
Power-down sequence of BDCOK Hand BPOK H LSI-11 bus signals.
Master console-equipped and slave console-equipped models can be
interconnected to allow control of both supplies from the master console.

FEATURES
• +5V ±3%, 18 A (maximum) and + 12V ±3%, 3.5 A (maximum);
combined dc power must not exceed 110 W.
• Overcurrent/short-circuit protection-Output voltages return to
normal after removal of overload or short; current is limited to approximately 1.2 times the required maximum rating.
• Overvoltage protection- + 5V I imited to + 6.3V (approximately);
+ 12V limited to + 15V (approximately).
• Line-time clock-A bus-compatible signal is generated by the
power supply for the event (line-time clock) interrupt input to the
processor. This signal is either 50 or 60 Hz, depending on primary
power line frequency input to the power supply.
• Power-fail/automatic restart-Fault detection and status circuits
monitor ac and dc voltages and generate bus-compatible BPOK H
and BDCOK H signals (respectively) to inform the LSI-11 bus modules of power supply status.
• Fans-Built-in fans provide cooling for the power supply and modules contained in the system backplane.
SPECIFICATIONS

Input voltage (Continuously-see Note 1)
100-127 Vac (H780-C, -H, -K)
200-254 Vac (H780-D, -J, -L)
Temporary Line Dips Allowed
100% of voltage, 20 msec max
357

H780
AC Inrush Current
70 A at 127V, 60 Hz (8.33 msec)
25 A at 254V, 50 Hz (10 msec)
Input Power (fans included)
340 W at full load max
290 W at full load typical
Input Protection
H780-C, -H, -K (100-127 Vac) fast blow, 5 A fuse
H780-D, -J, -L (200-254 Vac) fast blow, 2.5 A fuse
Hi-Pot
2 kV for 60 seconds from input to output, or input to chassis
Output Power (combinations not to exceed 110 W)
+5V,1.5A-18A
+ 12V, 0.25 A-3.5 A
Maximum DC Current under Fault Conditions
+5V bus = 28A
+12V bus = 9.5 A
+5V Output
5V±3%
Total Regulation
±0.5%
Line Regulation
±1.0%
Load Regulation
0.1%/1000 hours
Stability
0.025%IOC (See Note 2)
Thermal Drift
150 mV p-p (1% for f <3 kHz)
Ripple
±1.2%
Dynamic Load Regulation
dildt = 0.5 A ILs
delta 1= 5 A
1 % peak at f > 100 kHz (noise
Noise
is super-imposed on ripple)
±0.05%
Interaction due to + 12V
+12V Output
Total Regulation
Line Regulation
Load Regulation
Stability

12V ±3%
±0.25%
±0.5%
0.1 %/1 000 hours
(See Thermal Drift Note 2)
0.025%IOC above 25°C
358

H780
Ripple
Dynamic Load Regulation

Noise
Interaction due to +SV
Overvoltage Protection
+SV

+12V

Adjustments
+SV Output
+12V Output
Controls
Rear Panel
Front Console
(Master only)
Console Indicators

3S0 mVp-p (1 % for f <3 kHz)

±O.B%
di/dt = O.S A JLsec
f<SOO Hz
delta 1= 3 A
1 % peak at f > 100 kHz (noise
is super-imposed on ripple)
±0.02%

6.3V nominal
S.6SV min
6.BV max
1SV nominal
13.6V min
16.SV max
4.0SV-6.BV
Guarantee Range 4.SS-S.6SV
10.6V -16.SV
Guarantee range 11.7-13.6V
AC ON/OFF switch
DC ON/OFF switch
HALT/ENABLE switch
LC ON/OFF switch
DCON
RUN (Master)
SPARE (Master only)

Backplane Signals
BPOKH
BDCOK H
BEVNT L
Transmitted
BHALT L
SHRUN L
Received (Master only)

Mechanical
Cooling
Two self-contained fans provide 0.7140 m3/m in (30 fP/min) air flow.
3S9

H780
Size
13.97 cm w X 8.43 cm h X 37.15 cm I
(5-1/2 in w X 3-1/3 in h X 14-5/8 in I)
Weight
5.90 kg (13Ib)

Environmental
Temperature
Ambient
Storage

50 to 50 0 C (41 0 to 122 0 F)
-40 0 to +70 0 C (-40 0 to +158 0 F)

Humidity
90% maximum without condensation

NOTES
1. Operation from ac lines below 100V may cause the power supply
to overheat because of decreased air flow from the cooling fans.
2. These parameters apply after 5 minutes of warmup and are measured with an averaging meter at the processor backplane terminal block under system loading.

DESCRIPTION
Six H780 power supply options are available for use in LSI-11 bus
systems. Individual model numbers determine combinations of 115 or
230 Vac (nominal) primary power and selection of master console,
slave console, or no console. Models are listed below.

H780
Model No.
H780-C
H780-D
H780-H
H780-J
H780-K
H780-L

Input Power
115V
230V
115V
230V
115V
230V

Console
Description
None
None
Master
Master
Slave
Slave

The H780 master console contains RUN and DC ON indicators for
monitoring the processor states, as well as DC ON/DC OFF, LTC
ON/OFF; and . ENABLE/HALT switches for controlling the processor.
The slave console contains only a DC ON indicator for monitoring the
status of the slave power supply.
360

H780
Console Controls and Indicators - The H780-H or -J master-'Console .
has three LED indicators and three 2-position toggle switches. One of
the LED indicators is a spare indicator. Circuitry to drive this indicator is included on the console printed circuit board for user application. The console on the H780-K and -L slave supplies has. only one
LED indicator, DC ON. The H780 console controls and indicators are
described in Table 1. Additionally, the rear panel of the H780contains
an AC ON/OFF toggle switch and an ac line fuse.

+ 12 V and + 5 V Adjustment Procedure - The H780 power supply is
factory-adjusted to produce + 12 V and + 5 V outputs within theoperating tolerance of the system. The adjustment procedures presented allow the user to trim the dc outputs of the H780 to meet his particular needs. One adjustment is provided for the + 12 V output, while
two adjustments (one for the output voltage and one for the switching
regulator frequency) are provided for the + 5 V. A DVM, an oscilloscope, and a small screwdriver are required. Power supply loading is
provided by the LSI-11 bus or processor.

361

H780
Table 1

H780 Controls and Indicators

Control/
Indicator

Type

Function

DC ON

LED indicator

Illuminates when the DC
ON/OFF toggle switch is set to
ON and proper dc output voltages are being produced by the
H780.
If either the + 5 or + 12 V output
from the H780 is faulty. the DC
ON indicator will not illuminate.
This is the only indicator on the
H780-K and -L slave supplies.

RUN

LED indicator

Illuminates when the processor
is in the run state (see ENABLE/HALT).

SPARE

LED indicator

Not used by the H780 or processor. The H780 contains circuitry
for driving this indicator for user
applications.

DC ON/OFF

Two-position
toggle switch

When set to ON. enables the dc
outputs of the H780. The DC ON
indicator will illuminate if the
H780 dc output voltages are of
proper values. If a slave supply is
connected to a master. the slave
DC ON indicator will light if the
slave dc output voltages are of
proper value.
When set to OFF. the dc outputs
from the H780 are disabled and
the DC ON indicator is extinguished. If a slave supply is
connected to a master. the slave
DC ON indicator will also extinguish.

362

H780
Table 1
Controll
Indicator
ENABLE/HALT

H780 Controls and Indicators (Cont)

Type

Function

Two-position
toggle switch

When set to ENABLE. the B
HALT L line from the H7S0 to
the processor is not asserted and
the processor is in the Run mode
(RUN indicator illuminated).
When set to HALT. the B HALT L
line is asserted. allowing the processor to execute console ODT
microcode (RUN indicator extinguished).

LTC ON/OFF

Two-position
toggle switch

When set to ON. enables the
generation of the line-time clock
( LTC) B EVNT L signal by the
H7S0.
When set to OFF. disables the
H7S0 line time clock.

AC ON/OFF
(rear panel)

Two-position
toggle switch

When set to ON. applies ac
power to the H7S0.
When set to OFF. removes ac
power from the H 7 SO.

FUSE (rear panel)

5 A or 2.5 A
fast-blow

Protects H7S0 from excessive
current. H7S0-C. -H. and -K use
a 5 A fuse. H 7S0-D. -J. and -L
use a 2.5 A fuse.

363

H909-C
H909-C GENERAL PURPOSE LOGIC ENCLOSURE
INTRODUCTION

The H909-C is an enclosure for use with the DDV11-S.
SPECIFICATIONS
Width
Height
Depth

48.25 em (19 in )
13.33 em (5.25 in )
62.86 em (24.75 in )
70.48 em (27.50 in ) including
bezel

Weight

27.21 kg (60 lb.)

Mounting Space for Power
Supplies

12.7 em x 15.8 em x 50.8 em
(5 in x 6.25 in x 20 in )

Figure 1

H909-C Enclosure

364

H909-C
DESCRIPTION
The H909-C is a general purpose logic box designed to accommodate
the DDV11-8 backplane for anyone of several different standard logic
subsystems. A photograph of the H909-C enclosure is shown on the
opposite page. The H909-C features a distinctive front panel that can
be drilled for lights and switches as required by the user. A fan is provided for cooling purposes, and ample room is reserved for power supply installation.
CONFIGURATION
A detailed description of each, including application and configuration
information, is presented in the following table. The various options
available are listed below.

Options

Voltage
(V)
8ezel* Includes

H909-C

Fan and H0341
card guide

* Including switches

365

Mounting

H9270
H9270 BACKPLANE
INTRODUCTION
The H9270 consists of an 8-slot backplane with a card guide assembly. This backpiane is designed to accept up to eight double-height
modules (including processor), four quad modules, or a combination
of quad and double-height modules. When used for bus expansion in
multiple backplane systems, the H9270 provides space for up to six
option modules, plus the required expansion cable connector module(s) and/or terminator module.

DESCRIPTION
Mounting the Backplane
Mounting dimensions and possible methods of mounting the H9270
backplane (in any of three planes) are shown in Figure 1. Option positions are shown in Figure 2. Slot numbers indicate device interrupt
and DMA priority in LSI-11 bus systems. The lowest numbered positions receive the highest priority.

DC Power Connections
Voltage and Current Requirements - A power supply for a single
H9270 backplane LSI-11 system should have the following capacity:

+5V ±5% load; 0-18 A static/dynamic
+12V ±3% load; 1-2.5 A static/dynamic
+5 ripple; less than 1% of nominal voltage
+ 12 ripple; less than 150 mV p-p (frequency 5 kHz)
NOTE
Regulation at the H9270 backplane must be
maintained to the specifications listed above.

The H780 power supply option provides sufficient dc power and generates the required bus signals. Installation details are included in the
H780 power supply description.

366

H9270
REAR MOUNTING
10-32 THD x 1.27om (O.5in)
THREADED STUD (4 PLACES)

---i ~(g:~~::;)

0.2om

~, (0.08in)

CO~~6~~1[oR
il ':: ---------~~-. ~cm
-

(2.63in)

0.34 em (0.187 In) DIA
HOLES 4 PLCS.

=-=-----:22;7~.66c;.m;;C;(100_a.8~7i;in~)---::===~fl O.35em (0.14 in

~----

28.3em (11.15 in)

2.06em
(0.8Iin)

VIEW FROM REAR OF BACKPLANE
11-3301

TOP AND BOTTOM MOUNTING

28.3em
(11.15 in)

1
"~'"'~

-s-

18.5cm
(7.29in)
27.90m
(1I.Oin)

I LTi

22.96em

L~i
-1
--t-i

6- 32 THD HOLE
0.64em (o.25in) DEEP

3.5 em
(1.375 in)

- - - - - - - - -8 - - - - - - - - - - -.:e-

~
7.lcm
(2.80in)

CONNECTOR _
BLOCK
0.7gem
(0.31 in)

I ~

----j

~
7.5em
(2.95in--'

13.34em
(5.250in)

SIDE MOUNTING

11-3302

Figure 1

Backplane Mounting

VIEW FROM MODULE SIDE OF BACKPLANE
PROCESSOR
(HIGHEST PRIORITY LOCATION)

OPTION 1

OPTION 3

OPTION 2

OPTION 4

OPTION 5

OPTION 7
(LOWEST PRIORITY LOCATION)

OPTION 6

" ' / - - - - - - PREFERRED LOCATION FOR MMVll·A CORE MEMORY

Figure 2

H9270 Option Positions

367

1.9cm

(0.74in)

H9270
A multiple-backplane system using H9270 backplanes should have
the same voltage regulation and ripple specification as listed for the
single H9270 backplane. However, it will be necessary to calculate the
actual power requirements, based on individual power requirements
for modules used in the system.
Backplane Power Connections - If the H780 power supply option is
not used, perform the following steps to connect power to the H9270
backplane (Figure 3).
1. Select wire size. (14 gauge is recommended.) Consider load current and distance between the power supply and backplane.
2. For a standard system, connect the applicable wires to the H9270
connector block per Table 1.

3.
4.

For battery backup, remove the jumper between +5V and +58
and connect the applicable wires to the H9270 connector block.
Connect the ground terminals at the power source.
It is recommended that the backplane frame/casting be electrically connected to the system/power supply ground.

The signal connections to the H9270 backplane are shown in Figure 4.

Table 1

H9270 Backplane Standard Power Connections

Power Source
(From)

H9270 Connector Block
(To)

+12V
+5V

+12V
+5V
+58

GND
GND

-12V

Factory
Connected
Factory
Connected
This voltage is not required.
The connection is available
for custom interfaces.

NOTE
H9270 has 5.1 AC loads.

368

H9270

H9270 POWER AND
SIGNAL CONNECTIONS

ROW IDENTIFIER

TYPICAL MODULE
LOCATION
(SLOTS AI-BI)

MODULE SIDE IDENTIFIER
I = COMPONENT SIDE
2 = SOLDER SIDE

WIRE-WRAP PINS
PASS THROUGH
H9270 Pc. BOARD

CP-1773

o
@

+12V

3
4

@ : -12V

SIDE 2
-:::> .• "'62

Figure 3

H9270 Backplane Terminal Block (Pin Side View Shown)

RIBBON CABLE

\a ~MATING
~

CONNECTOR DEC PART No.12·11206·02
(3M PART No.3473-3)

0gg"4-- Boca K

BEVNT

7\~----BHALT
GND

BPOK
SRUN

H9270 PRINTED
C I RCU I T BOARD

2
3
4

SIDE 2
CP-1765

Figure 4

H9270 Backplane Signal Connections (Pin Side View
Shown)

369

H9270
CON FIGURATION
Backplane and Module Configuration
LSI-11 bus systems can be classified as either single-backplane or
multiple-backplane systems. The electrical characteristics of each
system are different; hence, two sets of rules have been devised and
must be observed. These rules have their basis in bus loading and
power consumption.
Single-Backplane Configuration Rules
1. The LSI-11 bus can support up to 20 ac loads, if unterminated at
the end.
2. The terminated bus can support up to 35 ac loads.
3. The bus can support up to 20 dc loads.
4. The amount of current drawn from each power supply should be
70 percent or less of the maximum rated output of the supply.

Multiple-Backplane Configuration Rules
1. No more than three backplanes can be connected together.
2. Each backplane can have no more than 20 ac loads.

3.
4.

The total number of dc loads cannot be more than 20.
Both ends of the termination line must be terminated with 120
ohms, i.e., the first backplane must have an impedance of 120
ohms, and the last backplane must have a termination of 120
ohms.

The cable connecting the first two backplanes (Le., the main box
and expander box 1) must be at least 60.96 cm (2 ft.) long. (A
182.88 cm (6 ft ) cable is recommended for ease of installation.)

The cable connecting the backplane of expander box 1 to the
backplane of expander box 2 must be at least 121.92 cm (4 ft )
longer or shorter than the cable connecting the main box and
expander box 1 (a 304.80 cm (10ft) cable is recommended for
ease of installation).

The combined length of both cables in a 3-backplane system
cannot exceed 487.68 cm (16 ft ).

The interbackplane cables must have a characteristic impedance
of 120 ohms.

The amount of current drawn from each power supply should be
70 percent or less of the maximum output of the supply.
370

H9270
To configure an LSI-11 bus system, take the following steps:
1. Choose the type of memory (MOS, PROM, or combination) required for the specific application.
I')

c:..

3.
4.
5.
6.

Select the CPU and memory combination most suited for the application.
Select additional memory, interface, and peripheral options.
Count the total number of module positions.
Count the total number of bus positions.
Choose a backplane configuration that satisfies both the module
position requirement, the bus position requirement, and also provides sufficient expansion space.
Enter the option names in the backplane positions of the selected
configuration.

371

H9273-A
H9273-A BACKPLANE
INTRODUCTION
The H9273-A backplane logic assembly consists of a 9 X 4 backplane
(nine rows of four slots) and a card frame assembly.
DESCRIPTION
The H9273-A backplane logic assembly is shown in Figure 1. Power
and signals are supplied to the backplane to conncectors J7 and J8.
These connectors are shown in Figures 1, 2, and 3. Connectors J9
(GNO) and J10 (-12V) are also shown in Figure 2.

CARD FRAME
ASSEMBLY

H9273 BACKPLANE

Figure 1

H9273-A Backplane Logic Assembly

<01

+12 VDCIBI

13 2

+ 12 VDC

G 3

GND + 12VDC

<0 4

GND +5VDC

13 5

+5VDC

ISJ 6

+5 VDCIBI

<0 7

GND + 5VDC

13 8

+5VDC

~
FIG.

I J9
GND

-12V

,~R

Figure 2

1154

H9273-A Power Connections
372

H9273-A
J8
AB 1
BR1·B

BPOK H
EVENT L

LTC
SRUN t

AF1

(ROW1)

GND

GND
BA2.DA2

+5VDC

APl

BHALT L

BAl

BDCOK H

Figure 3

11<;<",

H9273-A Signal Connections

The H9273-A backplane is designed to accept both double-height and
quad-height modules with the exception of the MMV11-A core memory module. The backplane structure is unique in that it provides two
distinct buses: the LSI-11 bus signals (slots A and S) and the CD bus
(slots C and D). The connectors that make up this backplane are
arranged in nine rows (Figure 4). Each connector has two slots, each
of which contains 36 pins, 18 on either side of the slot.
The connectors designated "Connector 1" in Figure 4 are wired according to the LSI-11 bus specifications. Slots A and S carry the LSI11 bus signals and are termed the LSI-11 bus slots. The connectors
designated "Connector 2" are wired for +5 V and ground, and have no
connections to the LSI-11 bus; instead, C- and D-slot pins on side 2 of
each row are connected to the C- and D-slot pins on side 1 in the next
lower row. Details of the CD interconnection scheme are depicted in
Figure 5.

CONFIGURATION
The H9273-A backplane logic assembly is designed to mount into a
SA 11-N mounting box or equivalent. Refer to the SA 11-N mounting
box description for more information.
NOTE
Connector block pins do not extend beyond the
H9273-A printed circuit etch card, thus eliminating
the possibility of backplane wire-wrapping.
H9273-A has 2.6 AC loads.
373

H9273-A
Three jumpers (W1, W2, and W3) are shown in Figure 4. Jumper W1
enables the line-time clock when inserted and disables it when removed.
NOTE
Only one BA 11-N mounting box in any system may
have the line-time clock enabled.

When inserted, jumpers W2 and W3 allow the LSI-11 quad-height
CPU to run in row 1. Jumpers W2 and W3 are removed when the
backplane is used as an expansion backplane in a system.

CONNECTOR 1

CONNECTOR 2

r------------~~--------~, rr----------~~----------~\
SLOTA

SLOTS

SLOTC

SLOT 0

ROW 1

ROW2

ROW3

ROW 4

ROW 5

ROW6

ROW7

ROWS

ROW9

VIEW IS FROM MODULE SIDE OF CONNECTORS.
MA-0740

Figure 4

H9273-A Backplane Connectors

374

H9273-A
COl

+5V

C02

COB

COO

GND

o
E02~____~~El

E02~______~

F02~____~~Fl

F~2-+____-1~

L __

-0

Tl t--

o-I---f-o

o
o

o-I-----if--<>

o
o

,r-- -- 0

J
~__~A-X~~~-+~_~x~_o-~t---+~_A-R__I
Ul

~t--

0--

r----

~:_~ V~2j~4--4~~V_l V~2~1-~---i~~ ~~t--r~t:o__~:r--r--t~____:~
__

001

002

DOB

o
o

--0

I Rl

L __ --0

o
o

009

o
o
o
o
o
o
o
o
o
o
o

~__-r~Til~~T~l~__-+~\~1_~~T22~__~~A-R__ )I~
Ul

L-:_~____V~2~~ -L~_-oV_l V~2~~ 1~~ ~O--+------L~_~____~-~T------~r-o_____:~
____

____

VIEW FROM PIN SIDE
FEATURES·
• ALL PINS Al CONNECT TO PINS Cl IN
THE NEXT LOWEST SLOT.
• ALL PI NS A2 CONNECT TO +5 VOLTS.
• ALL PINS T2 OF SLOT C ARE CON·
NECTED TO PIN T2 OF SLOT 0 IN THE
~JEXT LOWER SLOT.

Figure 5

• ALL PINS C2 AND PINS T1 ARE GROUND.
• JUMPER W2 IS CONNECTED ACROSS
PINS Kl AND LlIN SLOT CONLY.
• JUMPER W3 IS CONNECTED ACROSS
PINSKl AND LlINSLOTDONLY.

c-o Bus Interconnection Scheme
375

MR-1364

H9275·A
H9275·A BACKPLANE
INTRODUCTION

The H9275-A is an 18 position, LSI-11, terminated backplane that has
been designed to accept LSi-11 processors, memorres, and interface
modules. The nine slot by four row backplane accepts-up to 18 dualheight modules;or-9 quad-height modules, and uses a 22-bit address
bus (see Figure 1). Both dual-height and quad-height modules can be
mixed together in the H9275-A backplane because the LSI-11 bus is
repeated on both of its sides~
The H9275-A includes a wire frame card cage with integral card
guides. LSI-11 bus signals are terminated on the backplane with 120
ohm networks, eliminating the need for a terminator module.

CARD FRAME
ASSEMBLY

H9275-A BACKPLANE

Figure

H9275-A Backplane Assembly

DESCRIPTION

The H9275-A backplane assembly has nine jumper wires, designated
W1 through W9, which modify the bus configuration. The H9275-A
also has connectors that are positioned in four rows, called the A, B,
C, and 0 rows. (Please refer to Figure 2 for an illustration of the con-

376

H9275-A
nectors on the backplane). LSI-11 modules are plugged into these
rows and connected to the bus. Position 1 uses the row A and row B
connectors. Position 2 uses the row C and row 0 connectors. Therefore, row A is wired identically to row C, and row B is wired identically
to row D.
The H9275-A backplane supports the LSI-11/23 processor modules
four megabyte memory addressing capability. LSI-11 and LSI-1112
processor modules can also be used with the H9275-A with slight variations. Table 1, below, illustrates the jumper wires that must be removed or installed, depending on which processor is used.
The LSI-11/2 processor can be connected to the H9275-A backplane
after the W2, W3, W4, and W5 jumper wires have been removed. These
wires connect BDAL 18 through BDAL 21 (the extended address lines
that provide 22-bit addressing) address lines to position 1 (the processor position). If jumper wires W2-W5 are not removed, interference of
bus operation will result because the LSI-11/2 processor connects signals to these lines' jumper wires, which are not used for addressing.
The LSI-11 processor can also be used in the H9275-A backplane, provided jumper wires W6, W7, W8, and W9 are removed. Since the LSI11/2 processor is a quad-height module, it requires positions 1 and 2
on the backplane. Jumper wires W6 through W9 connect the BDAL 18
through BDAL 21 address lines to position 2, which is used by the
processor. The W2-W5 jumpers can either be installed or removed,
and will not interfere with the operation of the LSI-l1 processor.
Table 1

Jumper Wire Status for Microprocessors

LSI-1l/23

FALCON
AND
LSI -11/2

LSI - 11

W2-WS

INSTALLED

REMOVED

DON'T CARE

W6-W9

INSTALLED

REMOVED

CONFIGURATION
The H9275-A backplane uses three medium snap slide fasteners to
secure it to the mounting surface. The user provides three mounting

377

H9275·A
studs for the snap slide fasteners. These fasteners are available from
Dimco Gray Company as part no. 25-1-075-093. These studs are positioned in a plane defined by the length and width of the backplane.
The mounting stud locations within this backplane are defined in Figure 3.

§] §]

IW61

IW71

[§J El ~ QD
ROWA

ROWC

ROWB

~ [EJ
W8

ROW 0

SLOT 1

:oJ

SLOT 2

SLOT 3

SLOT 4

I I

SLOT 5

I I

SLOT 6

I I

SLOT 7

I I

SLOT 8

SLOT 9

Wl-W9

Z1-Z5

JUMPER WIRES
BUS TERMINATION RESISTORS

Figure

VIEW IS FROM MODULE SIDE OF CONNECTORS

H9275-A Backplane Connectors

378

H9275-A
FRONT SIDE
28.30 eM
(11.15IN)

-I

4-.,

21.60 eM
(8.50 IN)

3.35 eM
(1.32 IN)

+
.1

29.11 eM
(11.46IN)
27.50 eM
(10.84 IN)

14--_ _ 13 .35 eM
(5.23 IN)

----i-.t
I

1 1- 0 .75 eM

(0.29 IN)

REAR SIDE

Figure

Mounting Stud Locations

Connecting System Power
The H9275-A backplane requires external + 5 Vdc and + 12 Vdc power sources. The current rating of these power sources is defined by
the configuration of the user's system. The external power sources
are connected to the standard power connector, J1. The J1 connector
is a screw terminal strip located on the rear of the backplane, as
shown in Figure 4.

379

H9275-A

-8
-7
_6

.~
5 _

-5

4 _

J3 3 _
2 _

-3
1 -

L_-'

c_J

Figure

r-,

r-'

H9275-A Rear View

The J 1 terminal strip connectors are rated for 15 amperes per terminal
and accept up to a No. 12 wire. The backplane connector pins for the
modules are rated at one ampere. Additional + 5 Vdc power can be
connected to the backplane by using two push-on power tabs designated as J4 and J5. J4 and J5 power tabs are used only when the system requires more than 45 amperes of + 5 Vdc power. These power
tabs are located on the rear of the backplane as shown in Figure 4.

NOTE
The J4 and J5 power tabs should never be used as a
+ 5 Vdc power source from the bus to another device.

The J5 power tab is for the + 5 Vdc connection and is rated for 15
amperes. The J4 power tab is for the ground connection and is rated
for 15 amperes.

Connecting Control Bus Signals
Control bus signals are connected to the H9275-A backplane through
the J2 connector on the rear of the backplane as shown in Figure 4.
These signals include the power sequence signals BPOK Hand
BOCOK H, as well as the signals BHALT Land BEVNT L. The processor SRUN L Signal is available to monitor the processor-run condition.

380

H9275-A
The signal connections to the J2 connector are detailed in Figure 5.
The connector is keyed to accept the LSI-11 console/backplane cable
No. 70-11411-0K. This cable must not exceed one meter in length.

2--

BEVNT L

GND

-e7

-9

10:

BPOK H

-1

SRUN L

-3

GND

-5

+5.0 V

BHALT L

Figure

BDCOK H

5 Control Bus Signals J2 Connector

Bus Priority
The modules in the system are serviced on a priority basis for bus interrupts and Direct Memory Access (DMA) requests. Bus interrupts
function in either a position-dependent priority or a position-independent priority while DMA requests function only in the position-dependent priority. Position-independent priority is only implemented on the
LSI-11/23 CPU.
The bus positions described in Figure 6 are numbered in order for the
position-dependent priority structure. Priority is determi ned by the
381

H9275-A
physical placement of the module in the backplane. Position 1 is assigned the highest priority and position 18 is assigned the lowest priority. This priority structure operates with the condition that there are
no open or empty positions in the backplane between the placement
of the modules,

ROWA

SLOT 1

•

SLOT 2
SLOT 3

ROWB

Rowe

ROWD

POSITION 1

POSITION 2

POSITION 4

POSITION 3

POSITION 5

POSITION 6

POSITION 8

POSITION 7

POSITION 9

POSITION 10

POSITION 12

POSITION 11

POSITION 13

POSITION 14

POSITION 16

POSITION 15

POSITION 17

POSITION 18

)
~

SLOT 4

)

SLOT 5

SLOT 6
SLOT 7

SLOT 8
SLOT9

---

Figure

)'"

•

Horizontal Position Priority Structure

Bus Termination
The bused signals are terminated in the backplane with a characteristic impedance of 123 ohms connected to the 3.4 Vdc. The termination
resistors are located by Z1 through Z5 in Figure 2.
Bus Restrictions
The H9275-A backplane is a maximum LSI-11 system configuration
that will not support any external cabling of the bus. This limits any
system to the backplane and is not expandable by using additional
backplanes. The backplane contains 0.188 inch pins on the connector
blocks and will not accept any wirewrap connections_

382

H9276
H9276 BACKPLANE
INTRODUCTION
Theti9276 is a 9 x 4 (nine rows of four slots) backplane designed for
use with the BA11-S mounting box. It can accommodate both dualand quad-height extended LSI-11 bus modules used in the 22-bit addressing system.

SPECI FICATIONS
AC Loading: 3 Units

DESCRIPTION
The H9276 backplane provides two separate buses: the extended LSI11 bus and the CD bus. (The C and D rows of the backplane collectively comprise the CD bus). Figure 1 depicts these two buses and illustrates the H9276 backplane, as well as power and signal connectors
(J1-J3).
All modules are inserted in slots 1 through 9 of the H9276 backplane.
Rows A and B of each slot supply the extended LSI-11 bus signals,
while these signals, in turn, are bused to each of the nine slots. The
pins of the C and D rows are not bused, but the pins of the adjacent
slots are connected. This arrangement not o'1ly precludes the necessity of top connectors, but provides the means for designing buses
whose lengths are determined by the number of modules in a set.
The connector labeled "connector 1" in Figure 2 has two connector
slots wired in parallel (etch connections). When the PDP-11/23-PLUS
CPU module is inserted into rows A, B, C, and D of slot 1, rows A and B
carry the extended LSI-11 bus signals. Therefore, the A and B rows are
called the extended LSI-11 bus rows.
The connector labeled "connector 2" in Figure 2 carries the CD signals. These connectors are_not wired in parallel, except the + 5 V and
ground. These connectors have no connectors to the extended LSI-11
bus in rows A and B. The connectors that make up the H9276 backplane each have 36 pins. Four rows-- A-, B-, Co, and D-- each have nine
slots. Each slot has two rows of connector pins, 18 on either side of
the slot.
The extended LSI-11 bus signals are found on all 9 slots of rows A and
B, and use rows CD connector slots for communications between any
number of consecutive slots between slots 2 and 9. Figure 3 shows the
C-D bus interconnection scheme. LSI-11 double-height modules are inserted into the extended LSI-11 bus slots, rows A and B on the H9276
383

H9276
EXTENDED LSI 11 BUS ROWS
~

(

_______A,-________

ROWA
SIDE 1

SLOT 1
r

CD BUS ROWS

______

~A,-

______~

ROW B

ROWC

ROW 0

00
Wi

6--?)
W2

6--?)
W3

2{:'tl 1
r~,

r11 ~~

I(X~I
, ... ,

2'I -'
3"
1 ,J

("I

10 (Y,; 9
&-...J

J3
r .,
I ~'j16
IGI5
IGI4

4", I

I ,_
5... ,
16,1 ... J
I7',I
8',_ '

I GI3
IGI2

I ~'j 11
... ...J

SLOT 9

...

•

~-'" l~~

\ Al

\V2

NOTE
VIEW IS FROM MODULE
SIDE OF CONNECTORS

Figure 1

H9276 Backplane

backplane. If the extended LSI-11 bus is to be continued to a second
backplane, a M9404 connector module is inserted into rows A and B of
the next available slot, while an M9405 connector module is inserted
into slot 1 (rows A and B) of the second backplane. A pair of BC02D
cables is used with these modules to connect one H9276 backplane to
another.

384

H9276
EXTENDED LSI-ll BUS
CONNECTOR 1

CD BUS
CONNECTOR 2

,_ _ _ _ _ _A .....
- _ _ _----.y _ - - -......" -' - - - - - - - . ,'\
A

SiDE i

W1
SLOT 1
J2

~--)".,
OJ

'" W3 v

PROCfSSOR

r ,

2,("'{1 1

f'~"1
f;~~,
(

... , ...

OPTIPN 1

r ,-=
11~1

OPTI;ON 2

(",

,2~1

10 ~~~~ 9
L

-J

r-'
10'6

p~1

OPTlfN 3

,4~1

OPT~ON 4

I r'

OPTI:ON 5

5~'

,6~1

IGI5
1014

7~1

IGI3
I ~J12

OPTION 6

1(111
L.-.J

-'
,!!Ii
OPTION
7~

SLOT 9

\
\\

-L
~~

PIN\~

PIN A1

~~ERMINArOR MODULE\

~V1

PIN V2

Figure 2

H9276 Backplane Connectors (Module Side)

385

H9276
C02

COl

C08

EI
o

o
o

,-- -·0

L __ --0

o
o

W3
KI
r----O

;

L _ _ --0

<>-+----4--0

)

COO

o
o

o
o
o
o
o
o
o
o
o

VIEW FROM PIN SlOE
FEATURES
• ALL PINS AI CONNECT TO PINS CI IN
THE NEXT LOWEST SLOT
• ALL PINS A2 CONNECT TO '5 VOLTS
• ALL PINS T2 OF SLOT C ARE CON
~~ECTED TO PiN T2 OF SLOT D ir.; THE.
NEXT LOWER SLOT

Figure

• ALL PINS C2 AND PINS T1 ARE GROUND
• JUMPER W2 IS CONNECTED ACROSS
PINS KI AND LI IN SLOT CONLY.
• JUMPER W3 IS CONNECTED ACROSS
FiNS Ki AND L1 ii\ SLOT D ONLY

3 C-O Bus I nterconnection Scheme
386

MR -1364

H9281
H9281 BACKPLANE
INTRODUCTION

The H9281 backplane is designed to accept double-height modules
only. Six options of the H9281 backplane let the user configure compact LSI-11 bus systems that most efficiently use available system
space.
No quad-height modules can be installed in the H9281 backplane.
DESCRIPTION
The H9281 2-slot backplane is available in the following six options:
Backplane
Option
Designation
H9281-AA
H9281-AB
H9281-AC
H9281-BA
H9281-BB
H9281-BC

Description
4-module backplane
8-module backplane
12-module backplane
4-module backplane and card cage assembly
8-module backplane and card cage assembly
12-module backplane and card cage assembly

CONFIGURATION
Mounting dimensions for H9281 backplanes are shown in Figures 1
and 2. The H9281 backplanes can be mounted in any plane. The
enclosure in which the backplane is mounted, available system space,
and cooling air flow will determine an acceptable backplane position
in a particular system.

387

H9281

4.95 em
1.83 em
(0.72 in)

!ll.95inll

7.~ em .--11.,. r r - - - - - i l - - - - i o

.-t--!

(3.0 in)

4.52 em
(1.78 in)

H9281-AA

·~~~------~------~I~

1.2;

7L---------------'

HOLES (41
0.36 em
10.14 in I

(0.5 ill)
:

2.7~.·

MOUNTING

e m .:;1'
11.1 in)

,lJ

.~Il~.n-----------~--------o
,

- -l

I
I

4.83 em
(1.9 in)

H9281-AB

r--!t

15.24 em
(6.0 i n ) ,

I
I
I

4.83 em
(1.9 in)

I
I

.}--~L...tL-------ll-----'.~l... 2.79 em
11.1 in)

I;lll

~.--LI-~oIL-~_-_-___
_ -_-_-_-1-4.-61-e-m-__=__=__=__=__=__=__=__=_~~1
0.38 em
I
10.15 inl----; :---

'---J

(5.75 in I

.----

2 .79 em
(1.1 inl

I
HOLES 161
0.36 em
(0.14 in I

0.38 em

~ ~·(O.15inl

.r----~
,

MOUNTING

're

11 .27 em .I
10.5 inl ...,
4.45 em
11.75 inl

7 .37 em

I 2.9 inl

H9281-AC

20.32 em
18.0 inl

j
0

7.37 em
12.9 inl

'r- Li.

2.79 em
11.1 inl

MOUNTING

HOLES (61
0.36 em
(0.14 in I

MR·0459

Figure 1

H9281-AA,-AB;-AC Mounting Dimensions

388

H9281

~"'-

MOUNTING
DIMENSION
A

ASSEMBLY
LENGTH
B

H9281·BA

S.8Sem
(2.7 in!

7.S2 em
(3.0 in!

H9281·BB

11.94 em
(4.7 in!

15.24 em
(S.O in!

H9281-BC

17.02 em
(S.7 in!

20.32 em
(8.0 in!

MODEL

(4.57 in!

4.04 em

4.45 em
(1.75 in!

I
27.43 em
(10.8 in!

4.45 em
(1.75 in)

Ii>-

4.45 em
(1.75 in)

MOUNTING
HOLES I1S)
0.S4 em
10.25 in!

10-32
(TYP. 4 PLACES)

0.97 em
(0.38 in)

14.61 em
(5.75 in!

MR·0460

Figure 2

H9281-BA;-BB;-BC Mounting Dimensions

389

H9281
Connecting System Power
Seven screw terminals are provided on the slot 1 end of the backplane
for power connections. Connect system power (and optional battery
backup power) as shown in Figure 3. Power wiring should be done
with a wire gauge appropriate for the total power requirements for
options installed in the backplane. The recommended wire size for
H9281-AC and -BC backplanes is 12 gauge. 14 gauge is sufficient for
the other H9281 models.

SYSTEM {+12V
POWER
+5 V
SOURCE
GND------,

---------:-+-0

BATTERY
BACKUP
POWER
SOURCE
(OPTIONALI

{+5 V
GND _ _ _ _ _ _ _--1
+12 v

---------+-0 +12 B

MR·0461

Figure 3

H9281 Power Connections

Select a power supply that will meet LSI-11 system power specifications and supply sufficient current for the options in the system. The
H780 power supply is recommended.
Connecting Externally Generated Bus Signals
Externally generated bus signals can be connected to the H9281 backpanel via connector J2. These Signals include power sequence signals
BPOK H, BDCOK H, BHALT Land BEVNT L. In addition, the processor-generated SRUN L signal is available via J2 for driving a RUN
indicator circuit. J2 connector pins are fully compatible with the H780
model series power supply or the KPV11-A power-fail/iine-time clock.
Signal connector J2 pinning and signal names are identified in Figure
4.

390

H9281

MR-0462

Figure 4

H9281 Signal Connections (J2)

Device Priority
All LSI-11 bus backplanes are priority structured. Daisy-chained grant
signals for DMA and interrupt requests propagate away from the
processor from the first (highest priority device) to successively lower
priority devices. Processor module locations and device (option)
priorities are shown in Figure 5.
Bus Terminations
Backplane models H9281-AB, -BB, -AC, and -BC include 120 Q bus
termination resistors at the electrical end of the bus; therefore, it is not
necessary to install a separate 120 Q bus terminator module in these
backplanes.

391

H9281
POWER CONNECTOR
BLOCK (J1)
A

>
N

0
2

'"+ '"+
j

~
j

SIGNAL
CONNECTOR
PINS (J2)

'+
j

roo-,

L._-l

1 ~ PROCESSOR MODULE

H9281-AA. -BA
4-SLOT BACKPLANE

2 - OPTION 1 (HIGHEST PRIORITY)
3-OPTION 2

4 ~ OPTION 3 (LOWEST PRIORITY)

...

J l

o 0

LROWNUMBER
B + - - SLOT LETTER

0
1 - PROCESSOR MODULE

~------------~----------~
1--_
_ _ _ _ _ _+ ______-12 - OPTION 1 (HIGHEST PRIORITY)
3-OPTION 2

~----------~------~ 4 - OPTION 3

H9281-AB. -BB
8-SLOT BACKPLANE

~---------~r_---------~

5-OPTION 4
6-0PTION 5

1--------+------~7 -OPTION 6
8 - OPTION 7 (LOWEST PRIORITY)

120 OHM BUS TERMINATION RESISTORS

o 0

r-,

I..._-l

1 - PROCESSOR MODULE
2 - OPTION 1 (HIGHEST PRIORITY)

I
I

3-OPTION 2
4-0PTION 3
5-0PTlON 4

H9281-AC. -BC
12-SLOT BACKPLANE

6-0PTION 5
7 -OPTION 6

8-0PTlON 7
9~·OPTION 8

10-OPTION 9

11 +- OPTION 10

12 - OPTION 11 (LOWEST PRIORITY)

II...!\..

120 OHM BUS TERMINATION RESISTORS

Figure 5

MR-0463

H9281 Option and Connector Locations (Module Side)
392

IBV11-A
IBV11-A INSTRUMENT BUS INTERFACE
INTRODUCTION
The !BV11-A is an option that interfaces the LSI-11 bus with the instrument bus as described in IEEE Standard 488-1975, "Digital Interface
for Programmable Instrumentation." An IBV11-A can be installed in
any LSI-11 system. The IBV11-A consists of an M7954 interface module and a BN11A-04 cable for connecting the first instrument. Additional instruments may be connected using a BN01 A cable.

The IBV11-A makes an LSI-11 based programmable instrument system possible.
FEATURES
• PDP-1.1 software-compatible
• 40-Kbyte/sec maximum transfer capability of hardware
• Board-mounted, user-configured switches allow easy device
(register address) and interrupt vector address selection
• Software support available under FORTRAN IV
• 5-Kbyte/sec transfer rate under FORTRAN
• System hardware-compatible with the LSI-11 component system
• Instrument bus compatible with the IEEE 488-1975 standard
• The module supports cable lengths up to 20 m (65.6 ft) total
• 15 devices (maximum) can connect to the bus
SPECIFICATIONS
Identification

M7954

Size

Double

Power

+5.0 Vdc ±5% at 0.8 A

Bus Loads
AC
DC

1.8
1

The IBV11-A, when connected to the LSI-11, will meet the following
subsets of IEEE Standard 488-1975:
SH1
AH1
TS
TE5
LE3

SR1
RL1
PP2
DC1

C1
C2
C3
C4

393

IBV11-A
This module is designed to be the only controller on the IEEE bus.
Therefore, it will not respond to another controller on the bus that
issues either a parallel poll configure command or a parallel poll control signal.

DESCRIPTION
The functional logic blocks that make up the IBV11-A are shown in
Figure 1. LSI-11 software controls and communicates with the IBV11A via programmed I/O transfers and interrupts. Programmed 1/0
transfers are made possible by assigning unique device addresses
(also called "bus addresses") to the IBS and IBD registers.

LSI-11 Bus Interface
LSI-11 bus address selection, interrupt vector address generation,
and bus data driver/receiver (transceiver) functions are provided by
transceiver integrated circuits (DCOOS). Each integrated circuit provides the interface for four BDAL bus lines; thus, four transceivers
comprise the 16-line BDAL (0:15) L LSI-11 bus interface.
Bit 1 of the least significant octal digit (BDAL 0) selects the IBS or IBD
register. This is a byte pOinter and it is significant for DATOB and
DATIOB bus cycles only. Register address selection is actually performed in the LSI-11 bus protocol and register selection circuit
(DC004); the receiver integrated circuit (DCOOS) simply routes the received low-order three address bits [DA (2:0)] to that function.
All I/O transfers over the LSI-11 bus are done according to a strict
protocol. One bus protocol integrated circuit (DC004) performs both
this function and the register address selection previously discussed.
When an active ADDRESS MATCH signal is present and BSYNC L
signal is asserted, the bus protocol integrated circuit is enabled to
complete its register selection function. BWTBT L, BDOUT L, and
BDIN L bus signals are decoded in the integrated circuit, as appropriate, to produce the LOAD IBS LOW BYTE, SELECT IBS, LOAD IBD
LOW BYTE, and RECEIVE internal control signals from the IBV11-A
logic functions. The integrated circuit also asserts BRPL Y L as required during the I/O sequence to complete the programmed transfer.

394

L('f>.

I
BRPlY l
BSYNC l
BWTBT l
BeOUT l

lSI-II BUS
PROTOCOL

lOAD IBS
lOW BYTE

REGI STER
SELECTION

SELECT
IBS

BDIN l

(DC0041

ClK
.ClK

lOAD IBD
lOW BYTE

L
BBS7 l
V>

::>

ell

:,
~

~Al <15:00~

SI
VECTOR
ADDRESS
SWITCH
SA<8:4>

!i::;
!ll
w

0
0

()

w
u
w

lSI-II BUS
DEVICE
ADDRESS
SELECTION
INTERRUPT
VECTOR
GENERATION
DATA I/O
INTERFACE

IN~

INTERRUPT

ERROR
DETECT ION

SRO

SRO
IBC

SRO l

!!
~ 15 ~ 0

I BS

SELECT
IBS

rfi

REM
EOP

I-

hi
J

7 6 5 4 3 2 1 0

S~ ~

~:l ~ ~ M ~ S ~

RRRRRRRR

WWWWWWWW

16.~

TAKE
CONTROL

~
NRFD

INSTRUMENT
BUS
CONTROL

EOI l

HANDSHAKE
INTERFACE

ATN l

ell

::>

~~
DAC
RFD

s s § ss s ~ §

,r-

16
lOAD 18D
lOW BYTE

DA <7:0>

1----+ INIT

(ClK)

INSTRUMENT
BUS
RECEIVERS

IL-IB <16: I>

COMMAND
HINSTRUMENTI
AND
6
BUS
TALKER
DID <8:1> l
DATA liNE
OUTPUT
DRIVERS
I
BUFFER

11- 4897

Figure 1

IBV11-A Functional Block Diagram

-m<
...L
...L

NDAC l

---,

INTR CTl

'"V>f-

NRFD l

WWWWWWWW

RRRRRRRR

z
w

::;

DAV l

HANDSHAKE
CONTROL

S ~ ~ ; ffi ~ ~ g

ISO

<n
::>

SYNC

REN l

)\1514131211109617654 3 ~ 1 OJ

6
(DC003 )

w
-'A

lSI-II· BUS
INTERRUPT
INTERFACE

161
DA <15:00>

ATN
DAV

READY
FLAGS

31 15 141312 II 109 6

DA <7:0>

BINIT L
BDIN l

IFC
\
1251's
ONE SHOT

r----roj4

TKR

ERI
INHIBIT
SWITCH

VECTOR
CONTROL

DA15

(DC005)

et::

BIAKO l

ASSERT
SRQ

I ,

IFC

CMD
lNR

BIAKI l

CONTROL BUFFER

BIRQ l

. f>.

-----."

ENABLE

:t:

S2
DEVICE
ADDRESS
SWITCH
SA<12:3>

SRO
D-FlOP

DA15

DA <7'0>

IBV11-A
Interrupts are generated by one interrupt integrated circuit (DC003).
Four interrupt vectors can be generated by this bus interrupt interface
function. A 5-bit vector switch allows the user to select the interrupt
vector for the IBV11-A module. The IBV11-A base interrupt vector is
factory-configured for 420. The base interrupt vector can range from
300 to 760; however, the vector interrupt must not conflict with other
bus devices, or with those interrupts reserved for system vectors.

Interrupt Vector
000420
000424
000430
000434

Interrupt Source
Error
Service request
Command and talker
Listener

These interrupt vectors allow the IBV11-A to generate interrupts that
can most efficiently be serviced by four separate service routines.
Interrupt and vector control logic on the IBV11-A module generates
the INTR CTL signals that initiate the interrupts. Inputs for this logic
function include the interrupt enable (IE) bit (stored in the control
buffer), command or talker (CMD or TKR) and listener (LNR) ready
flags, error (ERR) status from the error detection logic, and the device
service request (instrument bus control signal).

Instrument Bus Control
The control buffer is an 8-bit register that functions as the low byte of
the ISS register. Bits stored in this register control generation of interrupts, instrument bus clear, and instrument bus control and status
logic. Setting the IBC bit actually triggers a one-shot producing a 125
J.lS pulse that clears the instrument bus. Take control sync and
handshake control logic function together with instrument bus control
and handshake interface logic to communicate with instruments on
the bus according to instrument bus protocol. Output transactions
with the low byte of the IBD register result in data being stored in the 8bit command and talker output buffer. Instrument bus line drivers gate
this byte onto the instrument bus when the IBV11-A is an active talker,
or when it is an active controller.
Instrument Bus Interface
The ISV11-A interfaces with the instrument bus via four integrated
circuits, type MC3441. These integrated circuits are bus transceivers,
each containing four bus drivers, four bus receivers, and bus terminations that comply with instrument bus specifications.
396

IBV11-A
CONFIGURATION
The IBV11-A option can be installed in any LSI-11 bus to interface
various instruments via an "interrupt bus." The instrument bus is defined in the !EEE Standard 488-1975, "Digital Interface for Programmable Instrumentation." Any instruments designed to interface with the
bus defined in that standard can be interfaced to the LSI-11 system via
the IBV11-A.
The following paragraphs contain only the basic information necessary for configuring device register addresses and vector interrupts,
general installation and interface to the instrument bus, and basic
programming (e.g., device register functions).

Device Address
Device address switches provide a convenient means for the user to
configure the IBV11-A's register addresses. Only switches
corresponding to BDAL lines (3: 12) are provided. By PDP-11 convention, the upper 4K address space (bank 7) is normally reserved for
peripheral devices, such as the IBV11-A. The processor module asserts BBS7 L whenever a bank 7 address [BDAL (13:15) L is asserted]
is placed on the bus. Thus, BBS7 L must be asserted to enable an
"address match" output from the address selection function. Any address ranging from 16000X to 17777X can be configured that does not
conflict with other device addresses within the system; the X in the
address represents register and byte selection within the module.
Each IBV11-A module is factory-configured for a standard device register address (160150) and interrupt vector (420). Switches S1
(interrupt vector) and S2 (device register address) configure the module. A summary of register addressing and interrupt vectors is provided in Figures 2 and 3. Observe that the IBD register address is always
the IBS address plus 2. Similarly, only the error interrupt vector is
configured. The remaining three vectors are permanently assigned
sequential addresses in address increments of four as shown in Table

397

IBV11-A
Table 1

Standard Assignments

Description

Mnemonic

Write

First
Module
Address

Registers
Control/Status
Data

ISS
ISO

R/W
R/W

160150
160152

Vectors
Error
Service
Command and Talker
Listener

ER2, ER1
SRQ
CMD, TKR
LNR

Readl

420
424
430
434

Switches S 1 and S2 are located on the ISV11-A module as shown in
Figure 4. S1 and S2 are switch assemblies, each containing several
individual switches. The individual switches indicated in Figures 2 and
3 are clearly marked on the S1 and S2 assemblies. The ON and OFF
positions are also clearly marked.
Interrupt Vectors
The ISV11-A is capable of generating four separate interrupt requests;
each have separate interrupt vectors and normally would have separate service routines. Interrupts can be requested only when the ISS IE
(interrupt enable) bit is set. Interrupt requests are priority structured in
the ISV11-A. A summary of the four types is provided below.
Priority

Vector

Associated
IBS Bit

Cause of Interrupt

Highest

OOOXNNOO

ER2, ER1

Error condition.

Second
highest

000XNN04

SRQ

A device connected to the
instrument bus is requesting service.

Third
highest

OOOXNN19

TKR, CMD

The ISV11-A is an active
talker and is ready for the
processor to output a byte
to the low byte of the ISO
register. (The ISV11-A will
normally then transmit the

398

IBV11-A
byte over the installation
bus to the active listener(s).)
I_...,
('\\A/oct
... ...,v'"

OOOXNN14

LNR

The !BV11-A is an active
listener and has a data
byte to be read by the
processor.

NOTES
1.

X = User-configured interrupt vector octal digit.

N = User-configured interrupt vector binary bits.

Associated ISS bits shown, when set, produce interrupt requests
if the I E bit is set.
IBS REGISTER ADDRESS FORMAT
15

"'",,, ,oo,,~ I I I I I I " j, ot
S2 INDIVIDUAL
SWITCH NUMBERS

NOTES:
1. OFF ~ Logical 0;

I 1
ON~

1
BYTE
L.POINTER
BIT

L.O~IBS REGISTER

1 ~ IBD REGISTER

NORMALLY 0
(RESERVED FOR
FUTURE USE)

t
10

Logical 1

2. Only the IBS REG ISTER ADDRESS is configured via S2.
ISS REGISTER ADDRESS +2.

I I

TTTTT j j j

,,,,,,c"''''' "''''''']'

The IBD REGISTER ADDRESS always equals the
".4667

Figure 2

OFF

STANDARD VECTOR ADDRESS
CONFIGURATION 1000420)

OFF

o ~ ERROR

SERVICE REQUEST

o ~ COMMAND AND TALKER
t

~ LISTENER

NOT USED

ON ~OISABLE ERR'

r-'L-----'L-----'L-----'L---''--~------''___, !~b~~~~PTS
51

INDIVIDUAL

SWITCH NUMBERS

OFF~ NORMAL IENABLE)
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _---' ERR1 INTERRUPTS

NOTES:
1

OFF = Logical 0; ON=Logical 1

2. Only the VECTOR ADDRESS bits (8:4) are configured via 51. Blts:3 and 2 Ore
hardwore - selected for the functions shown
3. 51-8 OFF= IBV1t-A

IBV11-A

the only system controller Connected to the instrument bus.

51-8 ON = Another system controller is connected to the instrument bus.
II- 4888

Figure 3

Interrupt Vector

399

IBV11-A

,,- 4B89

Figure 4

IBV11-A Module Switch Locations

400

IBV11-A
Interrupt
Error
Service
Command and Talker
Listener

Interrupt Vector
"n" (configured vector)

n+4
n + 10 8
n + 148

Preferred value range for "n" = 300 ~ n ~ 760
Registers
The ISV11-A communicates with devices connected to the instrument
bus under the control of the program being executed. All communication between the processor and the ISV11-A is via the instrument bus
status (ISS) and instrument bus data (ISO) registers. The programmer
must be aware of the functional significance of each bit in both registers before any programs can be written that will control specific devices on the instrument bus. In addition, the programmer must establish instrument (device) addresses, and conform to the programming
rules specified for each instrument connected to the instrument bus.
See Figure 5 for a description of the IEEE bus.

The instrument bus status (ISS) register is similar in function to other
device control/status register (CSRs). The instrument bus data (ISO)
register is a 16-bit register that contains eight read/write data bits in
the low byte and eight read-only bits in the high byte. The eight readonly bits allow the program to read the logical state of the control and
management signals of the instrument bus.
The ISS register provides the means for controlling the instrument bus
control and management signals, and ISV11-A functions relative to
the LSI-11 bus. The low byte of the ISO register, on the other hand, is
used for passing commands to devices connected to the bus, and for
transmitting and receiving data between the processor and talker and
listener devices. In addition, the high byte of the ISO register allows for
processor monitoring of all instrument bus signal (control) lines. ISS
and ISO registers are shown in Figure 6 and described in Tables 2 and

401

IBV11-A
INSTRUMENT BUS
~

DEVICE A

~
~

SIGNAL LI NES
__
_A,-_ _ _

iiiii iii 0
,
!
I

, i

I
!

I I
I

I I
j

DEVICE B

~l!!r
i ; II

. I

DEVICE C

\..

-~-Jllll
I' ii
,

II
i

DEVICE D

I
L..-

} DIO <1: 8>

DAV
NRFD
NDAC
IFC
ATN
SRQ
REN
EOI

}

8- LINE DATA 8US

MESSAGE
HANDSHAK ING

GENERAL
INTERFACE
MANAGEMENT

CONTROL
SIGNAL
LINES (8)

11-4717

Figure 5

Instrument Bus Signal Lines

402

IBV11-A
INSTRUMENT BUS STATUS (IBS)

INSTRUMENT BUS DATA (IBD)

MR-1272

Figure 6

Table 2

Instrument Bus Status Word Format

Bit: 15
Name: SRQ
Description: (Service Request)
Monitors the state of the instrument bus service request line at all
times. Set when the IB SRQ line is low. Will cause an interrupt when
both SRQ and the interrupt enable bits are set. When the ER1-inhibit
switch is set, this bit will be written by any type of instruction that writes
into the IBS. Read/write.
Bit: 14
Name: ER2
Description: (Error 2)
Asserted if the IB reports that DAC is true when the IBV11-A tries to
send a data or command byte. This condition will exist when there is
no active listener or command acceptor on the lB. An ERR interrupt
occurs when both the ER2 and the interrupt enable bits are set.
Cleared by clearing both TON the TCS. Read-only.
Bit: 13
Name: ER1
Description: (Error 1)
Unless inhibited by the ER1-inhibit switch, this bit is asserted whenever a conflict occurs between the IB ATN, IFC, or REN lines and their
IBV11-A control hardware, Le., if one or more of these control lines is
asserted when it should not be asserted or not asserted when it should
be asserted. When asserted, the IBV11-A will not assert the ATN line
even though the TCS bit remains set. An ERR interrupt occurs when
both the ER1 and the interrupt enable bits are set. This condition can
be cleared only by clearing the cause. Read-only.
Bit: 12
Name: Not used
Description: Always read as a zero. Read-only.
Bit: 11
Name: Not used
Description: Always read as a zero. Read-only.
403

IBV11-A
Bit: 10
Name: CMD
Description: (Command Done)
Set when the ISV11-A is ready to send a command byte; set by a
successsful TCS to indicate that ATN was asserted and the first command byte may be issued. Also set by DAC when a command has
been completely accepted. A CMD/TKR interrupt occurs when both
the CMD and the interrupt enable bits are set. This bit is cleared by
INIT, received IFC, writing a command into the ISD low byte, or by
turning TCS off. Read-only.
Bit: 9
Name: TKR
Description: (Talker Ready)
Set when the ISV11-A is ready to send a data byte; set when TON is on
while TCS is turned off, or by DAC when TON is on. A CMD/TKR
interrupt occurs when both the TKR and the interrupt enable bits are
set. Cleared by INIT, received IFC, writing a data byte into the ISD low
byte, or by turning TON off or TCS on. Read-only.
Bit: 8
Name: LNR
Description: (Listener Ready)
Set when the ISV11-A has a data or command byte ready for reading
from the ISD low byte; set by DAV when LON is on. An LNR interrupt
occurs when both the LNR and the interrupt enable bits are set.
Cleared by reading the ISD low byte if ACC is off or by clearing the ISD
low byte if ACC is on. Also cleared when LON is turned off and by INIT
or received IFC. Read-only.
BH:7
Name: ACC
Description: (Accept Data)
Set and cleared under program control. When clear, reading the ISD
will automatically clear the LNR and assert DAC. When set, the programmer must write 0 to the ISD low byte in order to clear the LNR bit
and assert DAC. When the TCS, LON, and TON bits are all off (clear),
setting this bit will assert NRFD. Cleared by INIT or received IFC.
Read/write,

Bit: 6
Name: IE
Description: (Interrupt Enable)
Set and cleared under program control to enable and disable all interrupts. Cleared by INIT. Read/write.
Bit: 5
Name: TON
Description: (Talker On)
Set and cleared under program control to enable and disable the
talker function. Cleared by INIT or received IFC. Read/write,

404

IBV11·A
Bit: 4
Name: LON
Description: (Listener On)
Set and cleareo under program control to enable and disable the
listener function. Cleared by INIT or received IFC. Read/write
Bit: 3
Name: IBC
Description: (Interface Bus Clear)
Set under program control to cause the IFC line to be asserted for
about 125 ,usec. TCS will automatically be asserted at the end of IBC
(out-going IFC). Cleared by INIT. Read/write
Bit: 2
Name: REM
Description: (Remote On)
Set and cleared under program control to assert and unassert the
REN line. Cleared by INIT or received IFC. Read/write
Bit: 1
Name: EOP
Description: (End of Poll)
Set and cleared under program control to assert and unassert the E01
line. Cleared by INIT or received IFC. Read/write
Bit: 0
Name: TCS
Description: (Take Control Synchronously)
Set and cleared under program control to take control synchronously,
or to unassert ATN. Setting TCS will cause NRFD to be asserted for at
least 500 ns before DAV is checked. ATN is then asserted when DAV is
unasserted; NRFD is unasserted and CMD is set no sooner than 500
ns after ATN is asserted. Cleared by INIT or received IFC. Read/write
Table 3

Instrument Bus Data Word Format

Bit: 15
Name: EOI
Function: (End or Identify)
Monitors the IB EOI line at all times. Set when the IB EOI line is low.
Read-only.
Bit: 14
Name: ATN
Function: (Attention)
Monitors the IB ATN line at all times. Set when the IB ATN line is low.
Read-only.
Bit: 13
Name: IFC
Function: (Interface Clear)
Monitors the IB IFC line at all times. Set when the IB IFC line is low.
Read-only.
405

IBV11-A
Bit: 12
Name: REN
Function: (Remote Enable)
Monitors the IB REN line at all times. Set when the IB REN line is low.
Read-only.
Name: SRO
Bit: 11
Function: (Service Request)
Monitors the state of the instrument bus service request line at all
times. Set when the IB SRO line is low. Will cause an interrupt when
both SRO and the interrupt enable bits are set Read-only.
Bit: 10
Name: RFD
Function: (Ready for Data)
Monitors the IB NRFD line at all times. Set when the IB NRFD line is
high. Read-only.
Bit: 9
Name: DAV
Function: (Data Valid)
Monitors the IB DAV line at all times. Set when the IB DAV line is low.
Read-only.
Bit: 8
Name: DAC
Function: (Data Accepted)
Monitors the IB NDAC line at all times. Set when the IB NDAC line is
high. Read-only.
Bit: 7-0
Name: 0108-0101
Function: IB Data I/O lines
Reading the IBD low byte picks up unlatched data directly from the IB
010 lines. Data on the IB 010 lines may change if the LNR bit is not set.
Generally, the only reason to read the 010 lines when LNR is not set is
when a parallel poll response is expected. Writing data to the IB 010
lines is permitted when TON is set and DAV is clear, or when TCS and
ATN are set and DAV is clear. Otherwise, writing into the IBD low byte
will have no effect on the 010 lines but will set DAC if both ACC and
LNR are set. Read/write.
The data and command output buffer is cleared by INIT or received
IFC.
Connecting the External Equipment
Connection from the IBV11-A to the first device on the instrument bus
is via a type BN11A cable (supplied with the M7954 module), as shown
in Figure 7. One end is terminated with a 20-pin connector that mates
with the 20-pin connector on the IBV11-A module; the other end is
terminated with a 24-pin "double-ended" connector that conforms to
406

IBV11-A
the IEEE 488 1975 standard; the cable can be connected to any device
conforming to that standard. The double-ended connector contains a
male 24-pin and a female 24-pin connector in the same connector
housing. This allows for "linear" and "star" connections to instruments
connected to the instrument bus, as shown in Figure 8. One BN11A is
included in the IBV11-A option.
The linear arrangement shown in the figure includes five devices (or
instruments), A through E. There is no particular significance to the
sequence shown, or the electrical position along the instrument bus.
Unlike the LSI-11 bus, the position along the bus does not structure
device priority in the system.
The star arrangement shown in the figure allows five devices to be
connected by stacking instrument cable connectors on the BN 11 A's
double-ended connector. Double-ended connectors on instrument
bus cables will normally include captive locking screws on each connector assembly (two each), allowing stacked connectors to be secured together in a single assembly.

PIN A

11-4890

Figure 7

BN11A Instrument Bus Cable

407

IBV11-A
BNOI A CABLES

C""J

DEVICE C

DEVICE D

(A) LINEAR ARRANGEMENT

DEVICE
CJ

BNIIA CABLE

(B)

STAR

ARRANGEMENT
11- 489\

Figure B

Linear and Star Configurations

The BN11A cable connector pin signal assignments are listed in Table
4 for each connector. One BN11A cable is required for each IBV11-A
module in a system.

Optional Cables
1. Connect M7954 module to first instrument:
BN11A-02
BN11A-04
2.

2 m (7B.7 in)
4m(157.5in)

Connect instrument to instrument:
BN01A-01
BN01A-02
BN01A-04

1 m (39.4 in )
2m(7B.7in)
4m (157.5 in )

40B

IBV11-A
Table 4
IBV11-A
Cormector Pin
U
S
P
M
R
T
V
X
B
J
F
W
K

H
E
C
D
N
A
L

BN11A Connector Pin Assignments
Signal
Name
DI01
DI02
DI03
DI04
EOI
DAV
NRFD
NDAC
IFe
SRO
ATN
(SHIELD)
DI05
DI06
DI07
DI08
REN
GND (DAV GND)
GND (NRFD GND)
GND (NDAC GND)
GND (IFCGND)
GND (SRO GND)
GND (ATN GND)
GND (LOGIC)

Instrument Bus
Connector Pin
1
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

PROGRAMMING
Example 1-IBV11-A to Listener Device
This programming example illustrates how the IBV11-A communicates with a listener device. Standard device and vector addresses are
used, as shown in Figures 2 and 3. Once the program is started, and
after pointers have been initialized and the IBV11-A has taken control
synchronously, it communicates with the IBV11-A via an interruptdriven service routine. No "background" program is used; the program simply waits until another interrupt occurs.
409

IBV11-A
Communication with the listener device includes the transmission of
two command bytes (read as words from a message buffer), followed
by 24 message bytes that program device functions. After all message
bytes have been transmitted, the program halts (displays HALT PC
address = 1066).
A program flowchart for this example is shown in Figure 9; a symbolic
listing is shown in Figure 10.

NO
IE, REM, TCS

END

"·5231

Figure 9

Communicating with a Listener Device (Program Flowchart)
410

IBV11-A

ADDF<ESS
(I " ,i ('j .~.!. :.-: :; <)

OCTAL
CODE

ASSEMBLER SYNTAX

CUf"if'iENTS

INTR RETURN ADDRESS

(> !~>..:> ./;. :. :~; .::.~

001. O;!.;)
000200

001000
001002
001004
001006
001010
00:1.012
001014

01.2706
000500
012700
002000
012737
000110
160150

START: MOV t500,R6

001016
001020
001022
001024
001026
001030
001032
001034
001036
001040

000777
020027
002004
100006
012737
000105

WAIT!

012(3)'
160152
000002

SEND:

001042
001044
00:1.046
00 1 0~50
001 0~j2
001054
00105,'S
001060
001062
001064

020027
002004
003003
012737
000144
160150
020027
002064

20$:

F'SW

MOV :JI:2000, FW

RO IS MSG BUFFER ADDRESS

i"iOV :ft:110d60150

TAi'\E CONTROL
SYNCHRONOUSLY TO BECOME
CONTROLLER-IN-CHARGE

BR.
CMF' FW, :fI:2004

WAIT FOR INTERRUPT
MORE COMMANDS TO BE SENT?

BPL 20$
MOU :fI:l05,160150

:l.601~'i0

SET UP STACK POINTER

IF NO,GO TO 20$
IF YES,SET IE,REM,AND
TCS BITS OF IBS REG TO
ACTIVATE CONTROLLER
MOV (RO)t,160152; SEND MSG TO IB

RTI
CMF' RO!, t2004
BGT JO$
MOV '1=:l.44,1601:iO
eMF' RO,t2064

:LOO:~64

BMI SEND

000000

HtlLT

RETURN TO WAIT--FOR
MSG TO BE ACCEPTED
IS TALKER ACTIVE?
IF YES,GO TO 30$
OTHERWISE SET IE,TON
AND REM BITS OF IBS REG
TO ACTIVATE TALKER
HAD ALL MSG BEEN SENT?
IF NO,GO SEND ANOTHER MSG
OTHERWISE STOP
11·5232

Figure 10

Communicating with a Listener Device (Program Listing)

411

IBV11·A
Example 2-IBV11-A to Talker Device
This programming example illustrates how the IBV11-A
communicates with a talker device. As in example 1, this programming example assumes standard IBV11-A device and interrupt vector
addresses. Communication between the instrument and the LSI-11
system is via IBV11-A interrupt-driven service routines. No background program is used; the program simply waits until another interrupt occurs.

Communication with the instrument involves first transmitting the content of the command message buffer, in a manner similar to the
program operation described for example 1, followed by accepting
instrument output data and storing it in a received data buffer. The
content of the command message buffer typically includes first activating the device via its listener address, followed by setting up range
mode, operating parameters for the instrument, an execute command, and finally, activating the device as an active talker via its talker
address. Once the device has received the command message buffer
data, it performs the programmed measurements (or the function,
depending on the instrument) and returns data to the LSI-11 system
via the IBV11-A. Note that during this portion of program operation,
the IBV11-A functions as an active listener on the instrument bus.
Once all measurements have been stored by the program, the program halts with a displayed PC address = 1102.
A program flowchart for this example is shown in Figure 11 and a
symbolic program listing is shown in Figure 12.

412

IBV11-A

END

11-5234

Figure 1,1

Communicating with a Talker Device (Program Flowchart)

413

IBV11-A
ADDRES~3

ASSEMBLER SYNTAX

CODE

C"",~, <::.,'

000200

(..!I..)()··~·.:::.';l·

0010~56

":",,,; .•~,:;(.

000200

001000
001002
001004
001006
001010
001012
001014
001016
001020
OO:lO;:>;:>
001024
001026
001030

Ol;~706

00103:~'

001034
001036
001040
001042
001044
001046
(J010'50
001052
0010S4

COMMENTS
COMMAND/TALKER INTR
RETURN ADDRESS
PSW
LISTENER RETURN ADDRESS
PSW

STAFn:

MOV

I~'")OO, R6

SET UP STACK

()OO~)OO

()12100
002000
OLD01
002500
012737
00()110
160150
000177
O127J?
000 1 O~;
160150
0227()()
002();:>4
001404
012037

MOV I?OOO,RO
MO~!

12500,R1

MOV 1110,160150
WIHT:

BR
MOV 1105,160150

IBV11--A MSG BUFFER
BUFF FOR RECEIVED MSG
TAKE CONTROL SYNCHFWNOUSL Y
TO BECOME CONTROLLEf(-·
IN·-CHARGE, C·" I '-C
WA IT -.._·FOR INTERRUPT
PF~EF'ARE TO SEND
C()MM(iND MESSAGES

CMF' 12024,RO

HAD ALL COMMANDS
BEEN SENT?
; IF YES,GO TO 2()$
BEQ 20$
M()V (RO)td60152; OTHEr,WISE SEND MSG

1601~)2

OOO()O2
(i127~37

InI

2()$;

000320
160150
O()OO02

00 1 ()!~jtj
001060
001062
001064
001066
0010}O
0010?2
001074

013721
160152
022701

001076
,.) 0 1.1 00

005037
OO()OOO

MOV 1320.160150

RETURN TO WAIT----FUF·:
MSG TO BE ACCEPTED
IBV11-A SWITCHES fROM
CONTROLLER TO LISTENER

RTI

RETURN TO WAIT'--; FOR DMM MSG
MOV 160152. (R1)t; SAVE THE RECEIVED
MSG IN R1
eMF' 12540,Pt
HAD 20 (OCTAL) MSG
BEEN ACCEF'T[[t?
BE(1 30$
IF YES.GO TO 30$
CLR 160152
OTHERWISE ISSUE DAC

002!540

001403
OOS03?
1601~52

O()OO02

RTI
3()$:

CLR l6015?
HALT

RETURN ro WAIT---FOR
ANOTHER [tMM MSG
ISSUE DAC TO IB
STOh 20 MSG RECEIVED
"·5235

Figure 12

Communicating with a Talker Device (Program Listing)

414

KPV11-A,-B ,-C
KPV11-A,-B ,-C
POWERFAIULINETIME
CLOCKITERMINATOR

The KPV11 is an LSI-11 powerfaililinetime clock (LTC) generator.
Three versions of the KPV11 are available: KPV11-A, which has only
powerfail and LTC functions; KPV11-B, which has 1200 bus terminations in addition to the powerfail and LTC; and KPV11-C, which is similar to the KPV11-B, but has 220 bus terminations. The KPV11 is compatible with all LSI-11 component systems and LSI-11 backplane
options. It is designed for installation into any LSI-11 bus-structured
backplane or remote installation (not installed into a backplane) via
an optional cable which connects the KPV11 to the LSI-11 backplane.
In order to use the KPV11-B or KPV11-C as bus terminators, they must
be installed in the LSI-11 backplane. An optional console panel and
bezel are available for annual control of the LTC and the display of dc
power onloff status and the processor run/halt state.
FEATURES
• Automatic generation of BPOK and BDCOK poweruplpowerdown
signal sequence
• Automatic program restoration and starting when used with nonvolatile memory and appropriate software routines
• Linetime clock time reference provided by a signal source (user
supplied) other than the powerline
• KPV11-B and KPV11-C provide bus termination when plugged into
an LSI-11 backplane
• Can be installed into the LSI-11 backplane or mounted remotely.
An optional cable (DIGITAL part no. 70-12754) connects the KPV11
to the LSI-11 backplane
• Expandable with the 54-11808 console panel option

415

KPV11-A, -B,-C
SPECIFICATIONS
Identification

MB016 (KPV11-A)
MB016-YB (KPV11-B)
MB016-YC (KPV11-C)

Size

Double

Power

+5 Vdc ±5% at 560 mA

System dc
dc Sensing
Inputs

+5 Vdc ±5% at 0.11 mA
+ 12 Vdc ±3% at 0.B2 mA
24 Vac ±10% at 200 mA with
grounded center tap (Figure 4)

ac Une Monitor
Input
Bus Loads
ac
dc

1.6
1.0

Options
54-11BOB

Console Panel (PC assembly)

70-11656

Console Bezel

70-12754

Remote Signal Cable (for remote
mounting of KPV11)

70-0B6120

Console Signal/Power Cable (for
connecting optional console panel to the KPV11)

416

KPV11-A, -B,-C
CONFIGURATION
The KPV11 can be installed into any LSI-11 system backplane or into
a remote installation (not installed in a backplane). All KPV11 installations require a user-supplied, 24 Vac, center-tapped transformer capable of supplying at least 0.2 A. Remote KPV11 installations also require the optional remote-signal cable (part no. 70-12754). Users
requiring manual control of the LTC and desiring the display of dc
power on/off status and processor run/halt status need the optional
console panel, console bezel, and console signal/powercable.
Mounting hardware for the console panel and remote installation
must be provided by the user.

Configuring LTC Jumpers
LTC jumpers are located on the KPV11 module as shown in Figure 7
and are factory-configured for programmable operation with the LKS
(line- clock status) register at address (177546) as shown in Figure 8.
Normally, it will not be necessary to reconfigure LTC jumpers; however, it is possible to alter LTC operation as listed in Table 1 and the
LKS device address as shown in Figure 8 and listed in Table 2.

417

KPV11-A, -8,-C
EX CL
REM DC

+t2V

o
wt4

+5V
R54'"

GND

W15

W12

~:=l:=E~=:j~I=+= Wl0
IT:
W9
W7
~W8
W6

~
~S~i=~~=f
~

Wll

(KPVI1-B,
KPV1'-C

E12

ONLY) { E17

c=J c=J c=J
c=J
-l'--_----"If-

W3
W2
W4

t+---t----1c--t- E3 (KPV1H3
KPV1t-C
ONLY)

c=J
-l'--_----"If-

• =MAY USE 4-40 HARDWARE

• * =Remove for 50 Hz operat ion

Figure 1

Jumper, Connector, Resistor, and Pad Locations

418

KPV11-A, -B,-C
,........:..:__,_--r-----.---r---r---r--~__,_...:..;....,______._-_,_____T-__,.__-.,_____r....:..:....., BIT

PREFERRED
ADDRESS

L----L---'------'---,-...J...-r-'--r-'-,...-'---T---'---r-""---1,...........--,---'--,.....--r--'--"-----'-----' (177546)
T

BAN K 7 ADDRESS
(BBS7 L ASSERTED)
ADDESS JUMPER W1

W.O

FIXED DECODED
"6" BY
LOGiC

I I I I I I I I I I

R FACTORY JUMPER CONFIGURATION
I 0 INSTALLED 0"1"
R 0 REMOVED 0 "0"
tl-4837

Figure 2

Device Address (LKS Register) Jumpers

Table 1

LTC Jumpers

Jumper

Installed

Removed

W12

Enable manual control
or continuous LTC
interrupt request operation. Do not install
when W13 is installed.

*Disable continuous or manual operation.

W13

*LTC interrupt requests can be enabled
and disabled by program. Do not install
when W12 is installed.

LTC interrupt requests cannot
be program controlled.

W14

*Console (optional)
LTC ON/OFF switch
enabled.

Console LTC ON/OFF switch
disabled.

W15

*L TC signal occurs at
the power line frequency.

LTC frequency is determined
by an external source via EXT
TIME REF etched pad on module.

* Factory-jumpered configuration

419

KWV11-A
KWV11-A PROGRAMMABLE REAL-TIME CLOCK
INTRODUCTION
The KWV11-A is a programmable clock/counter that provides a variety of means for determining time intervals or counting events. It can be
used to generate interrupts to the processor at predetermined intervals, or to synchronize the processor ratios between input and output
events. It can also be used to start the ADV11-A analog-to-digital
converter either by clock counter overflow or by the firing of a Schmitt
trigger.
The clock counter has a resolution of 16 bits and can be driven from
any of five internal crystal-controlled frequencies (100 Hz to 1 MHz),
from a line frequency input or from a Schmitt trigger fired by an external input. The KWV11-A can be operated in any of four programmable
modes: single interval, repeated interval, external event timing, and
external event timing from zero base.
The KWV11-A includes two Schmitt triggers, each with integral slope
and level controls. The Schmitt triggers permit the user to start the
clock, initiate A/D conversions, or generate program interrupts in response to external events.
FEATURES
• Resolution of 16 bits
• Can be driven by an external input or from any of five internal
frequencies
• Four programmable modes
• Slope and reference signal level selection switches
• Can be used to start the ADV11-A analog-to-digital converter.
SPECIFICATIONS
Identification
M7952
Size
Quad
Power
+5 Vdc ±5% at 1.75 A
+12Vdc ±3%atO.01 A
Bus Loads
ac
3.4
dc
1
Operational
Clock
Accuracy
0.01%
Range
Base frequency (10 MHz) divided
into five selectable rates (1 MHz,
100 kHz, 10 kHz, 1 kHz, 100 Hz);
line frequency; Schmitt trigger 1
input
420

KWV11-A
Input Signals
ST1 IN (Schmitt Trigger 1 Input)
Input Range
m(maximum limits)

-3Vto +30V

Assertion level

Depends upon position of slope
reference selector switch and level control; triggering range =
-12 Vto +12V

Origin

User device

Response Time

Depends on input waveform and
amplitude; typically 600 ns with
TTL logic input

Hysteresis

Approximately 0.5V, positive and
negative

Characteristics

Single-ended input; 100 Kfl impedance to ground

ST2 IN (Schmitt Trigger 2 Input)
Same description as ST11N
Output Signals
ClK OV (Clock Overflow)
Asserted level

low
User device or ADV11-A

Destination

Approximately 500 ns

Duration

TTL open-collector driver with
470 fl pull-up to +5V

Characteristics

Maximum source current from
output through load to ground
when output is high (~2.4V): 5
rnA
Maximum sink current from external source voltage through
load to output when output is low
(~0.8V): 8 rnA
ST1 Out (Schmitt Trigger 1 Output)
Same description as ClK OV
ST2 Out (Schmitt Trigger 2 Output)
Same description as ClK OV
421

KWV11-A
CONFIGURATION
The following paragraphs describe the procedure for device and interrupt vector address selection, slope and reference level selection,
user connections, and programming. (Refer to the ADV11-A when
using the KWV11-A with that module.)
Device Address Selection
The KWV11-A contains two device registers that can be addressed by
the processor. These registers are the control/status register (CSR)
and buffer/preset register (SPR). The SPR's address is always equal
to the CSR address plus two. Thus, only the CSR address is configured by the user, as shown in Table 1.

Table 1

Standard Assignments

Description

Mnemonic

Read!
Write

First
Module
Address

CSR
SPR

R/W
R/W

170420
170422

Interrupts
Clock Overflow
Schmitt Trigger 2

CLKOV
ST2

440
444

Switch pack S1 (Figure 2) contains 10 switches; each corresponds to
an address bit as shown in Figure 3. The ON positions select a logical 1
bit address; similarly, the OFF positions select logical Os. The CSR
address can be configured for any address ranging from 17000 to
17777r, with the least significant octal digit configured for 0 or 4. The
recommended KWV11-A CSA address is 170420; S1 is shown configured for this address in Figure 2. Note that the SPR address, based on
the recommended CSR address, is 170422.
Interrupt Vector Selection
The KWV11-A can interrupt the processor for clock overflow and
Schmitt trigger 2 (ST2) services. Thus, two interrupt vectors are produced by the KWV11-A. Switch pack S3 (Figure 4) selects the vector
for the clock overflow interrupts; the ST2 interrupt vector is always

422

KWV11-A
equal to the clock overflow interrupt vector plus four. S3 contains
seven switches (one not used) that correspond to vector bits (03:08),
as shown in Figure 4. Configure the desired clock overflow interrupt
vector. The recommended address is 000440.
o

o 00

CLK STl

BIT 11

BIT 2

BIT 8

ADDRESS
SWITCHES

81T 3

VECTOR
SWITCHES

MR-0817

Figure 2

KWV11-A Connectors, Switches, and Controls

BDALBIT
• POSITION

MR-0858

Figure 3

KWV11-A CSR Address Switches
423

KWV11-A
12

00
BDAl BIT
POSITION

STANDARD VECTOR

~~~IGURATION

r or or II orI orI

VECTOR
2
3
4
5
6
SWITCH (531'-_ _ _ _ _ _ _ _ _ _ _
7 .......

MR-0859

Figure 4

KWV11-A Vector Address Switches

Slope and Reference Level Selection
Slope and reference level switches and controls are shown in Figures
2 and 5. Two reference modes are selectable for each Schmitt trigger-one that picks a fixed level appropriate to TTL logic, and one that
picks a variable level that permits setting the ST threshold to any point
between -12V and + 12V.
OFF~\ON

I
I

TTL REFERENCE

I
I

(JI-N)

BOARD HANDLE

I ST LEVEL I
(J1-L)

I ST LEVEL 2

VARIABLE REFERENCE

R18~_ R19 : =

ST SLOPE 1 ( JI-Tl
ST SLOPE 2! JI-R)
~

BOARD FINGERS

NOT USED

1
11-4178

Figure 5

KWV11-A Slope/Reference Level Selector Switches and
Controls

Slope selection is accomplished by separate switches for ST1 and
ST2, respectively. When the related switch is on, the firing point effectively occurs on the positive slope of the input waveform. When the
switch is off, the firing pOint occurs on the negative slope. R18 or R19
is used to set the level of the reference. Typical slope selection is
shown in Figure 6.
424

KWV11-A
NOTE
Users should take care that both TTL and variable
switches for either Schmitt trigger are not on simultaneously. This condition will not damage
components, but produces unpredictabie reference
levels. Note also that if no signal is connected to a
Schmitt trigger input, both threshold switches for
that ST should be open for noise immunity. Alternatively, ST1 IN and ST2 IN can be grounded externalIy.

INPUT WAVEFORM

POSITIVE·GOING THRESHOLD

- - - - L - ~YSTERESIS

- - ,,_-O.5V
NEGATIVE·GOING THRESHOLD

OUTPUT

-II--- 500ns

NOTE:
ST IS RETRIGGERED ONLY AFTER INPUT WAVEFORM
HAS MOVED BEYOND OPPOSITE THRESHOLD AND
THEN AGAIN PASSED SELECTED THRESHOLD.

-I1---5QOns

(a) SLOPE SELECTION: SLOPE SWITCH ON (POSITIVE SLOPE)

SEE NOTE

POSITIVE·GOING THRESHOLD

-=-=-,= == ~6~J~RESIS
i
NEGATIVE·GOING THRESHOLD
,
OUTPUT ------iU.--------...,U

SELECTED TRIGGER - - - - LEVEL (R18 OR 19) - -

- - --

-II-- 500ns

NOTE:
ST IS RETRIGGERED ONLY AFTER INPUT WAVEFORM
HAS MOVED BEYOND OPPOSITE THRESHOLD AND
THEN AGAIN IS PASSED SELECTED THRESHOLD.

-II-- 500ns

(b) SLOPE SELECTION: SLOPE SWITCH OFF (NEGATIVE SLOPE)
11-4549

Figure 6

KWV11-A Slope Selection

425

KWV11·C
KWV11·C PROGRAMMABLE REALTIME CLOCK
INTRODUCTION
The KWV11·C is a programmable realtime clock printed circuit board,
M4002. It can be programmed to count from one of five crystal-controlled frequencies, from an external input frequency or event, or from
the 50/60 Hz line frequency on the LSI-11 bus. The board can generate
interrupts or can synchronize the processor to external events. The
KWV11-C has a counter that can be programmed to operate in anyone
of the following modes.
Mode

Counter Operation

Single interval
Repeated interval
External event timing
External event timing from zero base

1
2
3

The KWV11-C has two Schmitt triggers that can be set to operate at
any level between ± 12 V on either the positive or negative slope of the
external input signal. In response to external events, the Schmitt
triggers can start the clock, start AID conversions in an AID input
board, or generate program interrupts to the processor.
• Resolution of 16 bits
• Five internal crystal frequencies-1 MHz, 100 kHz, 10 kHz, 1 kHz,
and 100 Hz.
• Two Schmitt triggers, each with slope and level controls that can
be used to start the clock or generate program interrupts.
• Line frequency input from BEVNT bus signal (50/60 Hz).
• Four programmable modes.

SPECIFICATIONS
Identification

Dual-height module, M4002

Power Requirement

+5 V±5% @ 2.2A
+12V±3% @ 13mA

Bus Loads
DC bus loads

AC bus loads

1
1.0

Clock
Crystal oscillator 10 MHz base frequency
Output ranges

1 MHz, 100 kHz, 10 kHz, 1 kHz, and 100 Hz
426

KWV11·C
Oscillator accuracy

0.01 %

Other sources

Line frequency or input at Schmitt trigger 1

iiO Connector

40 pins; 3M no. 3417-7040

Schmitt Trigger Input Signals
No. of inputs

Input range

± 30 V (max limits)

Triggering range

-12 V to + 12 V adjustable

Triggering slope

Positive or negative, switch selectable

Source

User device

Response Time

Depends on input waveform and amplitude; for
TTL logic levels, typically 600 ns.

Hysteresis

Approximately 0.5 V, positive and negative

Characteristics

Single-ended input with 100 K n impedance to
ground

Clock Output
Single

ClK OV l (clock overflow, asserted low)

Output pins

J1 pin RR and elK OVFl tab

Function

Time base selection from an internal crystal-controlled frequency, an input at ST1, or a line frequencyat BEVNT bus line.

Duration

Approximately 500 ns

Line driver

TTL compatible, open collector circuit with 470 n
pull-up resistor to + 5 V.

Max source current

5 rnA when output is high (;::: 2.4 V), measuring
from source through load to ground.

Max sink current 8 rnA when output is low (~ 0.8 V), measuring
from external source voltage through load to output.
Schmitt Trigger 1 Output
Signal
ST1 OUT l (asserted low)
Output pins

J1 pin UU and ST1 OUT tab
427

KWV11·C
Function

External time base input or counter of external
events. Input frequency is a function of the input
signal.

Other character- Same as clock output.
istics
Schmitt Trigger 2 Output
ST2 OUT L (asserted low)
Signal
Output pins

J1 pin SS

Function

Starts counter, sets ST2 flag, and generates an
interrupt (if enabled); causes buffer preset register (BPR) to be loaded from counter.

Other character- Same as clock output.
istics

Environment
Temperature, operating

5°C to 60°C (41°F to 140°F)

Temperature, not operating

- 40°C to 66°C ( - 4Q°F to
150°F)

Relative humidity, operatin.g

10% to 95% with max. wet bulb
of 32°C (90°F) and min. dew
point of 2°C (35°F)not condensing

DESCRIPTION
Figure 1 shows a block diagram of the KWV11-C. It has two read/write
registers that can be addressed by the processor- the control/status
register (CSR) and the buffer/Preset register (BPR). Two switch packs
on the board allow the user to select the starting device address for
these registers and the starting interrupt vector address.
The DMA bus transceivers monitor and generate bus signals for interrupts, data transfers, and addressing and timing controls. The bus
transceivers receive address and data information from the LSI-11
bus. When an address match occurs, the bus transceivers transfer
data to or from the control/status register or the buffer/Preset register.

Control/Status Register
The control/status register (CSR) allows the processor to control the
operation of the KWV11-C and to get status information on its current
operating condition. The CSR has bits to enable interrupts, mode se428

KWV11·C
lection, clock rate selection, and starting the counter (GO bit). The
eSR monitors the counter overflow flag, flag overrun, and the Schmitt
trigger flag (ST2). In addition, the eSR enables some maintenance operations.
Buffer/P reset Register and Counter
The buffer/P reset register (SPR) is a 16-bit, word-addressable, readl
write register. This register has two functions, depending on the mode
of operation selected. In mode 0 or 1, the SPR is loaded from the program with the clock count. The clock count is the 2's complement of
the number of clock inputs the counter is to receive before it overflows. The clock overflow (elK OV l) sets a flag in the eSR and generates an interrupt request (if enabled). elK OV l can also be connected directly to an AID input board to start an AID conversion.
In mode 2 or 3, the SPR provides indirect reading of the clock counter.
An input to Schmitt trigger 2 (ST2) causes the SPR to be loaded with
the contents of the counter. The counter is an internal register that is
accessible only by reading the SPR in these modes. The counter
keeps track of the number of clock pulses from the clock selector or
the number of input pulses at Schmitt trigger 1 (ST1).
Oscillator, Divider, and Clock Selector
The clock selector provides the clock input to the counter. The clock
selector has eight inputs, five of which are derived from a 10M Hz crystal oscillator and frequency divider network. The other inputs are:
STOP, SEVNT, and ST1. STOP halts the counter; SEVNT is a 50 or 60
Hz line clock input from the lSI-11 bus; ST1 (Schmitt trigger 1) can be
used as an input for an external clock or as an input to count external
events.
Mode Control
eSR bits 1 and 2 determine the mode of operation of the KWV11-e.
These bits are decoded in the mode control logic as follows.

CSR Bit

Mode Selected

o
o

1
1

0
1

Mode O-Single interval
Mode 1-Repeated interval
Mode 2-External event timing
Mode 3-External event timing from zero base

429

CTR 15--.0

BUS CONTROL

SWITCH
PACK

w
~
w

~ u
~

VECTOR
ADDRESS
VECTOR H

a:
>--

PACK

I\..

~
ADDRESS

SWITCH

0 v"

BUS DATAl

BDAl 15-.0 l

015-.0
SEl2

f--

a:
w
X
w

...;::
::Ii

BBS7 L

l/1

~:::l " ' "BIAKO L. BIAKI l V/

CLK

MOD~

CTR lD l

----_...._-

I
CSR 5 3

BEVNT H
1 MHZ

ClK CV

DIVIDER

OSC

...J

~ BSYNC L, BDOUTV

CSR 1
CSR 2

iii

A BWBT l, BDIN L--""

~
MODE
M.QQ:?
CONTROL
MOD I

ICSRI

ST2 FLAG H

INTERRUPT
CONTROL

MI3

CSR 15-.0

ADDRESS AND
TIMING CONTROL

100 KHZ

~
RATE
CONTROL I CTR ClK H
CLOCK
SELECTOR

1.0 KHZ
1 KH7
ICC HZ

l,BRPlYl

SEVNT l

_ SeVNT H

,..:!2...
VV

EXTERNAL
INPUTS

SCHMITT TRIGGERS
~ .. STl lVLADJ

STlIN

h
TT

ST POT 1

ST POT 2

SLOPE 1

SLOPE 2

ST2 LVL ADJ

ST SLOPE 1

ST2 H

ST21N

STl H

f \ S T SLOPE 2

~I
~

r--

-8]STI
OUT

STOP

~~1

MOD 2 OR
MOD 3 _

"'L.7

l.Jy.

Figure

IJ11

lK
- - 8 ] g VFL

ClK
CLR lD

~ REGISTER ~

"-7" i'-r

BIRO L, BINIT L..I\..,

~
ClK OV l

,..

SEL .0

V-

I--

COUNTER I--

STATUS

...J

:::l

f----

~ CONTROL!

...J

"l ADDRESS LINES

SPR1S-C

ClK

A/ 'y--

z0(

BUFFER
PRESET
REGISTER
IBPRI

KWV11-C Functional Block Diagram

~SPR elK
lD SPR 2

KWV11·C
In either mode 0 or 1, the counter is loaded from the buffer/P reset register. In mode 0, the counter increments at the clock selected rate until
it overflOWS, then it waits for another GO corramand. In mode 1, the
counter continues to count even after an overflow and can cause an
interrupt at repeated intervals.
In mode 2, the counter increments at the clock-selected rate (or at rate
of external input). An input at ST2 causes the contents of the counter
to be loaded into the BPR, where it can be read by the processor. In
mode 3, the counter is reset to zero after loading its contents into the
BPA.
In all modes, if a second overflow occurs before the processor services the first overflow, or if a second ST2 input tries to set a previously set ST2 FLAG, a flag overrun bit is set in the CSA.
Schmitt Triggers
The KWV11-C has two Schmitt triggers-ST1 and ST2. Both have
switches to select the threshold level and the slope selection (positive
or negative). Selecting a positive slope allows the Schmitt trigger to
fire on a low-to-high transition of the input signal; selecting a negative
slope allows the Schmitt trigger to fire on a high-to-Iow transition.
The Schmitt triggers are used in different ways.
5T1 - Schmitt trigger 1 can be an external time base input or an external input for signals to be counted. ST1 is one of the inputs to the
clock selector and can be selected as the clock for the counter. ST1
also goes to connector J1 and to tab ST1 OUT. A jumper wire cna be
connected from this tab to the RTC IN jumper pin on the AID input
printed circuit board.
5T2 - Schmitt trigger 2 can be used to start the counter, to set a flag
in the CSR, or to generate an interrupt to the processor. When the ST2
GO ENABLE bit is set in the CSR, the ST2 input sets the GO bit, which
starts the counter, sets the ST2 flag in the CSR, and generates an interrupt (if enabled).
PROGRAMMING THE KWV11·C
The KWV11-C has the following two programmable read/write registers.

Control/Status Register (CSR)
Buffer/P reset Register (BPR)
431

KWV11·C
The standard address and interrupt vectors for the KWV11-C are
shown in Table 1. This paragraph describes these registers and defines their bits.

Table 1
Description

KWV11·C Standard Address Assignments
Mnemonic

Address

CSR
SPR

170420s
170422a

Registers
Control/Status
Suffer/P reset

4448

Interrupt Vectors
Clock Overflow
Schmitt Trigger 2

CLKOV
ST2

440s

KWV11·C Control/Status Register
Figure 2 shows the bit assignments in the control/status register.
Each bit can be written or read under program control; however, the
maintenance bits, the flags, and the go bits have special programming
considerations.
• The maintenance bits (8,9 and 10) always read O.
• The flags (7, 12, and 15) cannot be set by the program.
• The go bits (0, 13) can be cleared by more than one method.
Table 2 defines each bit in the CSA.

KWV11·C Buffer/Preset Register
The address of the buffer/p reset register is the standard device address + 2, or 170422a. This register has two purposes. During mode 0
or 1 operation, this register is used to load the number of clock counts
before the counter overflows. During mode 2 or 3 operations, this register is used to read the current count from the counter. Reading the
SPR, indirectly reads the counter.
432

KWV11·C

F LG

GO ENA

INT 2

Figure

Table 2

FOR

MAINT

I
F LG
MAINT

OSC

STl

I
INT OV

I
RATE

I
MODE
1

KWV11-C Control/Status Register

KWV11·C Control/Status Register Bit Definitions

Bit

Name

Function

Set By/C leared
By

ReadlWrite Setting this
bit starts the
counter at a
rate determined by the
rate bits 3-5.

The GO bit is set
and cleared under program control. In modes 1,
2, and 3, this bit
remains set until
cleared by the
program. In
mode a this bit is
cleared automatically when the
counter overflows. Clearing
bit a or a BUS
I NIT resets the
counter and
stops the counting.

1,2

MODE

ReadlWrite

The mode is set
and cleared under program control and by BUS
INIT. BUS INIT
causes the board
to go into mode

2 1

Mode

a a Mode a
a 1 Mode 1
1 a Mode 2
1

Mode 3

433

KWV11·C
Bit

Name

Function

Set By/C leared
By

3-5

RATE

ReadlWrite These bits select the clock
rate or counti ng source for
the counter.

The rate is set
and cleared under program control and by BUS
INIT.

S 4

3 Rat-

e
0 0 0 StoP
0 0 1 1
MHz
0 1 0 100
kHz
0 1 1 10
kHz
1 0 0 1
kHz
1 0 1 100
Hz
1 1 0 ST1
external input
1 1 1 line (SO/60 Hz)

INTOV
(Interrupt on
Overflow)

ReadlWrite When this bit
is set, the
assertion of
OVFLO FLAG
generates an
interrupt. I nterrupt is also
generated if
bit 6 is set
whileOVFLO
FLAG is set.
434

This bit is set
and cleared under program control. If either bit 6
or 7 is cleared
while an overflow interrupt request to the
processor is
pending, the request is cancelled.

KWV11·C
Bit

Name

OVFLO FLAG

Function

Set Byte teared
By

ReadlWrite to

This flag is set
each time the
counter overflows. It is
cleared under
program control,
or at the low-tohigh transition of
the GO bit, or by
BUS INIT.

o -If bit6 is

set, setting bit
7 generates
an interrupt.
Bit 7 must be
cleared after
the interrupt
has been serviced to enable
further overflow interrupts. If two
enabled interrupts are requested at the
same time by
bits 7 and 15,
bit 7 has the
higher priority.

MAINTST1

MAINTST2

Write Only Setting this
bit simulates
the firing of
ST1. All functions started
by ST1 can be
exercised under program
control by using this bit.

This bit is set under program control. Clearing is
not needed. It is
always read as a

WriteOnlySetting this
bit simulates
the firing of
Schmitt Trigger 2. All func-

This bit is set under program control. Clearing is
not needed. It is
always read as a

435

KWV11·C
Bit

Name

Function

Set By/C leared
By

tions started
byST2 can be
exercised under program
control by using this bit.
10

MAINTOSC

Write Only For maintenance purposes, setting
this bit simulates one
cycle of the
internal crystal oscillator
used to increment the
clock counter.
(Bit 11 must
be set.)

This bit is set under program control. Clearing is
not needed. It is
always read as a

010
(Disable Internal Oscillator)

ReadlWrite For maintenance purposes, this bit
prevents the
internal crystal oscillator
from incrementing the
clock counter.
This bit is
used with bit
10.

This bit is set
and cleared under program control.

FOR
(Flag Overrun)

Read/Write Flag Overrun
provides the
programmer

This flag is set
when an overflow occurs and
the OVFLO

436

KWV11·C
Bit

Name

Function

Set Byte leared
By

with an indication that
the hardware
is being
asked to operate at a speed
higher than is
compatible
with the software.

FLAG (bit 7) is
still set from a
previous occurrence, or when
ST2 fires and the
ST2 FLAG (bit
15) has been p reviously set. Bit
12 is cleared under program control, or at the
low-to-high transition of the GO
bit, or by BUS
INIT.

ST2GO ENABLE

ReadlWrite When set, the
assertion of
ST2 FLAG
sets the GO
bit and clears
the ST2 GO
ENABLE bit.

The ST2 GO ENABLE bit is
cleared under
program control,
or at the low-tohigh transition of
the GO bit, or by
BUS INIT.

INT2
(Interrupt on
ST2)

ReadlWrite When set, the
assertion of
ST2 FLAG (bit
15) causes an
interrupt. If
set while ST2
FLAG is set,
an interrupt
request is
generated.

This bit is set
and cleared under program control and by BUS
I NIT. When either bit 14 or 15
is cleared, any
pending ST2 interrupt request is
cancelled.

ST2 FLAG

ReadlWrite to
0- Setting
this flag

The ST2 FLAG is
set by the firing
of Schmitt Trig-

437

KWV11·C
Bit

Name

Function

Set By/C leared
By

starts an interrupt request if bit 14
is set. Bit 15
must be
cleared after
servicing an
ST2 interrupt
to enable further interrupts.

ger 2 or the setting of the
MAINT ST2 bit
(in any mode)
while the GO bit
orthe ST2 GO
ENABLE bit is
set. The ST2
FLAG is cleared
under program
control or at the
low-to-high transit ion of the GO
bit unless the
ST2 GO ENABLE
bit has previousIy been set. This
bit is also
cleared by BUS
INIT.

If two enabled
interrupts are
requested at
the same time
by bits 7 and
15, bit 7 has
the higher priority.

Typical Program Sequences
This paragraph describes typical program sequences for operating
the KWV11-C in each of the four modes of operation.
Single Interval (Mode 0)
This mode of operation is used to generate a fixed interval for such
applications as known delays.
1. The program loads the BPR with the 2's complement of the number of clock pulses needed to generate the time delay at the userselected clock rate. For example:

2.
3.

Loading the BPR with -100, at a clock frequency of 1 kHz, generates a 100 ms time delay.
The program loads the CSR with mode 0, the clock rate, and interrupt enable (INTOV) if needed.
The program sets the GO bit, or it sets the ST2 GO ENA bit and
waits for an external event to set the GO bit.

438

KWV11·C
4.

When the GO bit is set, the counter is loaded with the contents
of the SPR and starts counting. The counter increments until it
overflows, at which time it clears the GO bit and stops counting.
The overfiow causes the overfiow fiag (OVFLO) to be set in the
GSA. If INTOV has been previously set, the OVFlO causes an interrupt to occur. If not, the KWV11-C waits for another program
command.
The program either responds to the interrupt, or it responds as a
result of checking the flags in the KWV11-C or in the AID CSA. For
example:
The program can test the OVFlO flag in the CSR of the KWV11-C.

If elK OVl is used to start an AID conversion, the program can
check the AID DONE flag in the AID input board or allow the AID
DONE flag to generate an interrupt request.
The program reads the CSR, clears the OVFlO flag, and if no
counting or mode changes are needed, sets the GO bit (or ST2 GO
ENA bit) to start again at step 4 above.

Repeated Interval (Mode 1)

In this mode of operation, the user can generate a fixed frequency
pulse train with any period within the range of the clock counter and
the five crystal frequencies.
1. The program loads the BPR with the 2's complement of the number of clock pulses needed to generate the time delay at the userselected clock rate. For example:
loading the BPR with -1 and selecting a 100 KHz clock rate generates a 1 MHz pulse train.

2.
3.
4.

In general, the overflow rate (pulse train) is equal to the clock rate
divided by the absolute value that is loaded into the BPA.
The program loads the CSR with mode 1, the clock rate, and interrupt enable (I NTOV) if needed.
The program sets the GO bit, or it sets the ST2 GO ENA bit and
waits for an external event to set the GO bit.
When the GO bit is set, the counter is loaded with the contents
of the BPR and starts counting. The counter increments until it
overflows.
439

KWV11·C
5.

The overflow causes' the counter to be loaded again with the
count from the SPR and to start counting again. The overflow also
sets the OVFlO flag in the CSR, which generates an interrupt if
enabled.
If a second overflow occurs before the processor services the
first overflow flag, then the flag overrun (FOR) bit is set in the CSR
to inform the processor of a loss of data.
The program either responds to the interrupt, or it responds as a
result of checking the flags in the KWV11-C CSR or in the AID
CSA. For example:
The overflow (ClK OVl) can be used to start an AID conversion in
an AID input board. When the AID conversion is complete, AID
DONE in the AID CSR can generate an interrupt request.
The program writes the KWV11-C CSR to clear the OVFlO flag,
make necessary changes, and set the GO bit (or ST2 GO ENA bit).
Then the program starts again at step 4 above.

External Event Timing (Mode 2)
In this mode of operation, the user can generate a pulse train while
monitoring external events, can record the time of external events, or
can count external events. Two external events can be monitored with
respect to each other.
1. The program may load the SPR with the 2's complement of one
of the following:
• The number of line inputs (SEVNT) that will generate a realtime reference to record the time of an external event at ST2.
• The number of clock pulses needed to generate the time delay at
the user-selected clock frequency.
• The number of external events to be counted at ST1 before an overflow occurs.
2.

The program loads the CSR with mode 2, the clock input (ST1,
SEVNT, or one of five frequencies), and interrupt enable (INTOV or
I NT2) if needed.

The program sets the GO bit, or it sets the ST2 GO ENA bit and
waits for an external event to set the GO bit.
440

KWV11·C
4.
5.

When the GO bit is set, the counter is cleared and it starts counting at the selected clock rate or number of inputs at ST1.
An input at ST2 places the current contents of the counter in the
SPR and sets the ST2 fiag in the GSR. if iNT2 has Pi6viously been
set, an interrupt is generated to the processor. The program can
then read the SPR and record the time of the event.
If ST2 does not occur, the counter continues to increment even
after an overflow. The overflow sets the OVFlO flag and generates an inerrupt if INTOV is enabled.
The counter continues until the program clears the GO bit.

External Event Timing from Zero Base (Mode 3)
The program for this operation is the same as for mode 2, except the
counter is automatically cleared after every ST2 pulse.

CONFIGURATION
The KWV11-C, shown in Figure 3, has two switch packs, SW1 and
SW2, to set up its device address and interrupt vector address. It also
has a switch pack, SW3, to select Schmitt trigger slope and level controls. For each of the two Schmitt triggers on the board, the user may
select a fixed reference level for TTL logic or a variable reference level
that permits setting the Schmitt trigger threshold to any point between -12 V and + 12 V. The user may also select whether the
Schmitt trigger fires on the positive or negative slope of the input
waveform.
Two tabs on the board provide outputs from the clock counter (ClK
OVl) and Schmitt trigger 1 (ST1 OUT). Either of these output tabs can
be used to connect a short jumper wire to the AID input board (pin RTC
I N) to start an AID conversion.
This paragraph provides details on setting up the KWV11-C.

Selecting the KWV11·C Device Address
The KWV11-C device address is the base I/O address aSSigned to the
control/status register of the board. The device address is selected by
means of two switch packs, SW1 and SW2. The switches allow the
user to set the device address withi n the range of 170000s to 1777748 in
increments of 4s. The device address is usually set at 1704208, as
shown in Figure 4. A switch in the ON position decodes a 1 in the corresponding bit position; a switch in the OFF position decodes a O.
441

KWV11·C

OFF

u
Jl

1 ON

-=:l

-=::J

-=:l
-=:J
-=:J

STl
CLK
OVFL OUT

SW3

-=:l

-=:J
-=:J

~~
ST2 STl
LVL LVL
ADJ ADJ

NOTE:
THE SWITCH POSITIONS SHOWN ARE THE
FACTORY-SHIPPED CONFIGURATION_
THESE POSITIONS ARE NECESSARY TO
RUN DIAGNOSTICS.

r::::. 8
r::::.
IIEJ
r::::.
r::::. SW2
-=:J
c:::.
c:::. 1
-=:l

r::::.
c:.I
c::. SWl
-=:l
c::.
c::.
c::. 1
ON OFF

Figure

KWV11-C Physical Layout

442

KWV11·C
Selecting the KWV11·C Interrupt Vector Address
The KWV11-C is capable of generating two interrupt vectors to the LSI11 processor. These interrupts can occur when one of the following
occurs:
• Clock counter overflows
• Schmit trigger 2 fires
The base interrupt vector is assigned to the clock overflow interrupt
and can be assigned any address between 0 and 770s in increments of
10a. It is usually set to 440a by SW2, as shown in Figure 5. A switch in
the OFF position decodes a 0; a switch in the ON position decodes a

1.
The interrupt vector for ST2 is automatically 4 address locations higher than the selected base interrupt vector.

Selecting Schmitt Trigger Reference Levels and Slopes
The KWV11-C has two Schmitt triggers that condition the input waveforms to a form needed by the user. Both can be adjusted to trigger at
any level in the ± 12 V range (or at TTL fixed levels) and on either the
positive or negative slope of the input signal. Each Schmitt trigger has
three switches and a potentiometer, shown in Figure 6. The use of
these switches and potentiometers is given in Table 3.

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
11 11 11 1 1 1 0 10 10 11 10 10 0 11 10 1 0 10 0 :g~~I~~

STANDARD ADDRESS
CONFIGURATION
(170420)
ADDRESS
SWITCH (SW1)

I I I I I I I I I I
I I I I I I I I
I
I
OFF OFF OFF ON

OFF OFF OFF

t±J

I I

ON OFF OFF

PART OF
SWITCH SW2

LOGICAL 1 = ON
LOGICAL 0 = OFF

Figure

Selecting KWV11-C Device Address

443

KWV11-C
15

0 11

I I II I I I I I I

I I I I I I:g~~I~~

I I I I I I
~ ~ ~ ~ ~ !

STANDARD VECTOR
CONFIGURATION

ON OFF OFF ON

(4401

~!~;CO:

OFF OFF

3
4
5
6
7
8
(PART OF S W 2 1 ' - - - - - - - - - '

Figure

Selecting KWV11-C Interrupt Vector Address

OFF
TT L RE FERE NC E

1 ON

I
I
1

(Jl-NI

(Jl-Ll

3
4

VARIABLE REFERENCE
STl ~ ST2
LVL
LVL ~
ADJ
ADJ

6
~7

-=-

BOARD HANDLE

I ST LEVEL 1

I ST LEVEL 2
ST SLOPE 1 (Jl-TI
ST SLOPE 2 (Jl-Rl

BOARD FINGERS

NOT USED
NOT USED

SW3

Figure

KWV11-C Slope and Reference-Level Switches

Table 3
SW3
Switch No.

Setting Schmitt Triggers on KWV11·C

Function

With this switch ON and switch 2 OFF, ST1
fires at a level determined by the ST1 LVL
ADJ potentiometer within a range of ± 12

V.
NOTE
Switches 1 and 2 cannot be on together.

444

KWV11·C
SW3
Switch No.

Function

With this switch ON and switch 1 OFF, ST1
fires at a fixed reference ievei for TTL iogic. The potentiometer has no effect.

With this switch ON and switch 4 OFF, ST2
fires at a level determined by the ST2 LVL
ADJ potentiometer within a range of ± 12

V.
NOTE
Switches 3 and 4 cannot be on together.

With this switch ON and switch 3 OFF, ST2
fires at a fixed reference level for TTL logic. The potentiometer has no effect.

When this switch is OFF, ST1 fires on the
negative slope (high to low transition) of
the input signal. When ON, ST1 fires on the
positive slope (low to high transition).

When this switch is OFF, ST2 fires on the
negative slope of the input signal. When
ON, ST2 fires on the positive slope.

7,8

Not used.

Figure 7 shows the relationship of an analog input signal to the
Schmitt trigger output. Note that once the Schmitt trigger fires, it fires
again only after the input signal moves past the oppOSite threshold
and then again passes the user-selected threshold.

445

KWV11·C
UPPER THRESHOLD

- - - /I- '!YSTERESIS
- - - '.:::: - - 0.5 V

LOWER THRESHOLD

OUTPUT

-...II--- 500 ns'

-...11---500 ns'

NOTE:
ST IS TRIGGERED AGAIN ONLY AFTER THE INPUT
WAVEFORM DROPS BELOW THE LOWER THRESHOLD
AND EXCEEDS THE UPPER THRESHOLD.
(al POSITIVE SLOPE SELECTION (SLOPE SWITCHED ON)

SEE NOTE
(-) SCHMITT TRIGGER (STI- -

UPPER THRESHOLD

- - - -_______
- - ,-___
- - '.::::
/I-_ HYSTERESIS
"" 0.5 V

---- - --

OUTPUT

-----...,U
-...II.- 500 ns'

NOTE:
ST IS TRIGGERED AGAIN ONLY AFTER THE INPUT
WAVEFORM EXCEEDS THE UPPER THRESHOLD
AND DROPS BELOW THE LOWER THRESHOLD.

LOWER THRESHOLD

-H-- 5OOns'

(b) NEGATIVE SLOPE SELECTION (SLOPE SWITCHED OFF)
'400 ns MINIMUM

Figure

Input-to-Output Waveforms for Postive and Negative
Slopes

External Control of Schmitt Triggers
The connector J1 on the board allows the user to connect external
slope and level controls for each Schmitt trigger. Connect external potentiometers and switches as shown in Figure 8. The value of the potentiometers should be between 5 k 0 and 20 k O. Selecting a potentiometer with more turns provides for a finer adjustment over the ± 12
V range.
SW3 on the KWV11-C must be set as shown in Figure 8, and the potentiometers on the KWV11-C should be set to their center of rotation. At
the center, the screwdriver, slot should be aligned with the notch at its
edge.

446

KWV11-C
Jl

EXT STI
LEVEL POT
IS-20K)

EXT ST2
i

lEVEL POT , (S-20K)

NN OR PP
(80TH ARE GND)

L/c
OFF

SW3

OFF

UNUSED

BOARD
HANDLE

ON
2

EXTERNAL
SLOPE 1
SWITCH
EXTERNAL
SLOPE 2
SWITCH

BOARD
FINGERS

1
NOTES:

FOR PROPER OPERATION OF EXTERNAL
lEVEL CONTROLS. BOTH POTENTIOMETERS
ON THE KWV11·C BOARD MUST BE SET TO
APPROXIMATE CENTER OF ROTATION.

SW3 SWITCHES 1-4 MUST BE SET AS SHOWN;
SWITCHES SAND 6 CAN BE EITHER OFF FOR
NEGATIVE SLOPE TRIGGERING OR ON FOR
POSITIVE SLOPE TRIGGERING.

Figure

Example Circuit for External Control of Schmitt Triggers

447

KWV11·C
INTERFACING TO THE KWV11·C
Figure 9 shows the pin assignments of the 40-pin I/O connector J1 on
the KWV11-C. This connector is provided for user inputs and outputs.
In addition, two tabs (shown in Figure 3) provide output signals elK
OVFl and ST1 OUT. These tabs are electrically in parallel with pins RR
and UU of J1. These tabs make it easier for the user to connect an external start signal since an AID conversion can be from Schmitt trigger
1 or from the clock counter overflow.
The KWV11-C has two bus interface connectors that plug into the lSI11 bus. These connectors have signals defined by lSI-11 bus specifications.

ST 2 OUT L
ST lOUT L

+3V

POT 2
POT 1
SLOPE 2
SLOPE 1

eLK OV L

ST 2 IN
ST 1 IN

t
BOARD SIDE

Figure

KWV11-C 110 Connector J1 Pin Assignments

448

LPV11
LPV11 PRINTER OPTION
INTRODUCTION
The LPV11 printer option is a high-speed line printer system for use
with an LSI-11 system. The system consists of an LPV11 interface
module, an interface cable, and a line printer (either an LP05 or
LA 180). The LPV11 interface module functions that are used with an
LP05 or LA 180 line printer are similar; however, the printer strobe
signals required for each printer are different. The specific interface
cable allows the interface module to detect which printer it is interfacing to, and automatically supplies the correct timing signals for the
specific type of printer. The interface module is program-controlled to
transfer data from an LSI-11 bus to the line printer. There are 12
option numbers that define the type of printer and four primary power
(line) voltages. Printer types include the LA 180 DECprinter and two
LP05 line printer models (uppercase letters only, and both uppercase
and lowercase letters). These models and their interface cables are
defined in Table 1.
Table 1

LPV11 Option Model Numbers

Option No.
(Model)

Interface
Cable*

Primary
Power

Model

LPV11-PA
LPV11-PB
LPV11-PC
LPV11-PD

BC11S-25
BC11S-25
BC11S-25
BC11S-25

115V, 60Hz
230V, 60Hz
115V, 50Hz
230V, 50Hz

LA180-PA
LA180-PB
LA180-PC
LA180-PD

180 char /sec
printer, 132
column,
upper- and
lowercase
letters

LPV11-VA
LPV11-VB
LPV11-VC
LPV11-VD

70-11212-25 115V, 60Hz
70-11212-25 230V,60Hz
70-11212-25 115V, 50Hz
70-11212-25 230V,50Hz

LP05-VA
LP05-VB
LP05-VC
LP05-VD

300 line/min
printer,132
column,
uppercase
letters only

LPV11-WA
LPV11-WB
LPV11-WC
LPV11-WD

70-11212-25 115V, 60Hz
70-11212-25 230V, 60Hz
70-11212-25 115V, 50Hz
70-11212-25 230V, 50Hz

LP05-WA
LP05-WB
LP05-WC
LP05-WD

240 line/min
printer, 132
column
upper-and
lowercase letters

* 7.62 m (25 ft) interface cable is supplied with each option.

449

Printer
Description

LPVll
FEATURES
• Models available for 115 or 230 Vac operation at either 50 or 60Hz
• Line printers available with 132-column upper- and lowercase letters, or uppercase only
• Line printers available with speeds of 180 characters per second
(LA 180), or 300 or 240 lines per minute (LP05)
• Interface module and interface cable supplied.

SPECIFICATIONS
Module
Identification

M8027

Size

Double

Power

+5V ±5% at 0.8 A

Bus Loads
AC
DC

1.4
1

Interface Cable
Type

Length

LP05 Line Printer
Power

Printable Characters
64-Character set

BC11 S-25 or 70-11212-25, depending on LPV11 model (see
Table 1)
7.62 m (25 ft) maximum

115 Vac ±10% 50/60 Hz ±3 Hz or
230 Vac ± 10% 50/60 Hz ±3 Hz
700W
!//#$%&'O*+,->10123456789:;<=

>?@
ABCDEFGHIJKLMNOPQRS
TUVWXYZ[\]L
96-Character set

All of the above plus a through z:

Type

Open Gothic print

Size

Typically 0.024 cm (0.095 in.)
high; 0.065 cm (0.025 in.) wide
450

LPV11
Code Format

ASCII

Characters per line

132

Character drum speed

64-character drum: 1200 r/min
96-character drum: 800 r/min

Printer Characteristics
Format

Top-of-form control; single line
advance with automatic perforation step-over, and carriage return. Automatic vertical format
control is optional.

Paper-Feed

One pair of pin-feed tractors for
1.27 cm (% in ) hole center, edgepunched paper.

Paper Slew Speed

50.8 cm (20 in ) per second

Print Area

33.53 cm (13.2 in ) wide, left justified

Character Spacing
(horizontal)

0.254 ±0.0127 cm (0.1 ±0.005
in ) between centers; maximum
possible accumulative error for
normal spacing is 0.0254 cm (0.01 in ) per 80- or 132-character
line.

Line Spacing

0.424 ±0.025 cm (0.167 ±0.01
in ) at 6 lines per inch; 0.3175 cm
(0.125 in ) at 8 lines per inch.
Each character within ±0.254 cm
(0.1 in ) from mean line through
character.
50 msec maximum

Line Advance Time

Variable reluctance pick-off
senses drum position.

Character
Synchronization
Physical Characteristics
Height
Width
Depth
Weight

1.14 m (45 in )
0.81 m (32 in )
0.56 m (22 in )
150 kg (330 Ib )

451

LPV11
Ribbon Characteristics
Type
Width
Length
Thickness

Inked roll
38.1cm(15in)
18.288 m (20 yd)
0.01 cm (0.004 in )

Paper Characteristics
Type

Standard fanfold, edge punched,
27.94 cm (11 in ) between folds

Width

10.16 cm to 42.55 cm (4 in to 163/4 in )

Weight

15-lb. bond minimum (single copy) 12-lb. bond with single-sheet
carbon for up to six parts (multiple copy)

Environmental
Operating Temperature
Humidity

10° to 32° C (50° to 90° F)
30 to 90% (no condensation)

Print Rates
LP05-VA, -VB, -VC, -VD
(64-character drum)

300 lines per minute

LP05-WA, -WB, -WC, -WD
(96-character drum)
LA 180 DECprinter
Power

Printable Characters

240 lines per minute

90-132 Vac or 180-264 Vac
50 or 60 Hz ± 1 Hz
400 W max (printing)
200 W max (idle)
96 upper- and lowercase character set (7 x 7 dot matrix):
+ ,-.10123456789

:;<=>?@
ABCDEFGHIJK
LMNOPQRS
TUVWXYZ
[\]Labcdef
ghijklmnopqr
stuvwxyz
!~l '" !"#$%&'O*
452

LPV11
Code Format

ASCII

Non-printable Characters

Six Commands: BEL, BS, LF, FF,
CR, DEL

Number of Characters per Line

132 max

Type of Character Transfer

Parallel (7 -bit plus parity)

Printer Characteristics
Print Cycle Speed

Up to 180 characters per second

Line Printing Speeds

70 lines per minute on full line
300 lines per minute on short
lines

Print Size

0.254 cm (10 characters per inch)
horizontal
0.233 cm (6 lines per inch) vertical

DESCRIPTION
The M8027 interface module comprises functions that control the flow
of data between the LSI-11 bus and the line printer (see Figure 1). The
interface signals are different for the LP05 and the LA 180 line printers,
but the LPV11 detects a ground in the interface cable, and automatically configures itself for the proper printer. Each function of the interface is described in the following paragraphs. The LA 180 and LP05
strobe timing diagrams are shown in Figures 2 and 3.

453

-6V
DEVICE
ADDRESS
JUMPERS
ENB H
BBS7 L

- - - - - t ~~~~E~
- - - - - t LOGIC

BOAL' 8:12.- L

BOAL

~-L_r-

0:7.15' L

TO PAINTER
INTERFACE CABLE

>-__

_ _ _ _ _ _ _ _ _L-____

~",PDATA

'l:L.. H

PRINT
.~~~~~~_~

CHAR

BUFFEP
OAL . 0'2 ~ H

WB
PDATABH

-5V

VECTOR
ADDAESS
JUMPERS

r---_<}.....-------------+-PBUSVL

r-_~~~_ _~~r----------t--PFAULTL

-INTENH

BUSY H
-MON LINE H
-READYHAGH
~RRORH

EN8 H

ERROR

\--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ VEC,OR H
BSYNC L

READ CB H

FI'
LOGIC

M FAULTH

M ON liNE H

BDIN L

LPOS
SELECT

ON LINE H

LOGIC

f-----------+-- P ON LINE H

A
A

'>___________+-"' P STROBE

SEL

READY FLAG H

'--____________- - - < : } - - - + . E L E C T

I
I

BIRO L

f--"B::'A",C:.::KI:..oL'-t" ~NUTpEt·
I4---"B",IA",C:.:;KO::..=.L--l LOGIC
BINIT l

~--------~"=as-T-A-H--------------~

DEMAND H

f-------------------~--poeMANOH

INT EN H

VECTOR H

INIT l

Figure 1

LPV11 Interface Logic Functions

LPV11
P DEMAND H
(El6-1)

DEMANDH
IE7-121
READY H
(El5-5)
31-101 NS
READY· ERR
DELAY CKT
(E21-5)
READY· ERR L
(E21-5)

READY FLAG H
(E23-14)

---------+""1

RQSTA H
(E6-17) _ _ _ _ _ _ _ _ _ _1

BIRQ L
(E6-B)

DATA STROBE H
(E2-10)

TIME

LP STROBE L
(El5-BI

M STROBE
(E28-B)

PSTROBE
(E28-10) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _'1

NOTES:
1. TIMING SHOWN IS TYPICAL. AND SHOWN
FOR REFERENCE PURPOSES ONL Y
2. TIMING SHOWN WITH JUMPER Wl INSTALLED
3. (

I = INTEGRATED CIRCUIT PINS.

4. TIME IS DETERMINED BY LP05 PRINTER LOGIC.
11·5638

Figure 2

LP05 Internal Timing

455

LPV11

J
-J

P DEMAND H
IEl6-1)

i--n,,,.,

DEMAND H
IE7·12)

--1 b=~25NS

READY H

(El~5)

READY· ERR H
DELAY CKT
(E21·5)

READY' ERR L
(E21·5)

READY FLAG H
(E23-14)

______

-+..1

RQST A H
(E6-17) _ _ _ _ _ _ _- '

~--+---

BIRQ L
(E6-8)

DATA STROBE H

-----------if)--J

(E2·10)

P STROBE
(E28-10)

INOTE 1)

NOTES:
1. JUMPER Wl INSTALLED (REQUIRED) FOR TIMING SHOWN.
2. TIMING IS TYPICAL, AND SHOWN FOR REFERENCE PURPOSES ONLY.
3. (

) = INTEGRATED CIRCUIT PINS.
"·5637

Figure 3

LA 180 Internal Timing

Bus Transceivers and Drivers
Bus transceivers (DEC 8641) receive the LSI-11 bus BDAL (0:7) L
signals and distribute the bits on DAL (0:7) H lines. In addition, they
transmit LPCS bits or interrupt vector address bits during a DATI bus
cycle or interrupt sequence. Bus drivers (DEC 8881) transmit LPCS
bits 8 and 15 during a DATI bus cycle in which the LPCS is addressed.
456

REV11-A, -C
REV11-A TERMINATOR,
REV11-C DMA REFRESH, BOOTSTRAP
INTRODUCTION
The REV11-A DMA refresh. bootstrap/terminator module consists of
DMA refresh circuits. a bootstrap ROM, and 120-ohm termination circuits. The REV11-C is similar to the REV11-A, but does not have the
120-ohm termination circuits.
FEATURES
•

Dynamic MaS memory refresh

•

ROM programs for booting paper tapes. RXV11 floppy disks. and
R KV 11 cartridge disks

•

ROM diagnostics for CPU and memory

•

120-ohm LSI-l1 bus terminations (REV11-A only)

SPECIFICATIONS
Identification

M9400-Y A (REV11-A)
M9400-YC (REV11-C)

Size

Double

Power

+5 V ±5% at 1.64 A (REV11-A)
+5 V ±5% at 1.0 A (REV11-C)

Bus loads
ae
de

2.2
1

DESCRIPTION
Addressing - The module includes a 512 X 16-bit ROM array that is
addressed in two 256-word segments. These address segments are reserved for REV11 options and reside in the upper 4K address bank.
normally used for peripheral device addresses. The reserved addresses
range from 165000-165776 and 173000-173776. A power-up mode,
which will cause the processor to access ROM location 173000 upon
power-up, is jumper-selectable on the processor module.

457

REV11-A, -C
Initialization - The bootstrap ROM logic is initialized only when BDCOK
H goes false. This condition occurs during a power failure and produces
active BO INIT Hand BO INIT L signals. These signals clear the 9-bit
address latch and circuits contained in the OMA refresh logic. The option
does not respond to the LSI-11 bus BINIT L signal.
Terminations (REV11-A Only)
Each bus signal line terminates with two resistors.
These termination resistors are generally contained in a 1 6-pin, dual-inline package which is identical to an IC package. Each package contains
14 termination pairs. The values used are shown in the figure. Oaisychained grant signals are terminated and jumpered. BJAKI L is jumpered
(with etch) to BIAKO L, and BOMGI L is connected to BOMGO L via
factory-installed jumper Wl.

CONFIGURATION
Ii

., I,-.,
~R£SH
.• 1,--..;
~T5TRAP

BBBB
., 1

(ALWAYS

lffSTALLEDI

Figure 1
W2
W4

REV11-A, -C, Jumpers

Insert to enable DMA refresh.
Insert to enable bootstrap ROM.
458

RXV11
RXV11 FLOPPY DISK OPTION
SPECIFICATIONS
Module
Identification

M7946

Size

Double

Power

+5 V ±5% at l.5 A

Bus Loads
AC
DC

1.8
1

Drive
Identification

RX01

Size

46.3 cm w X 28.7 cm h X 53.3 cmd
(19 in w X 10.5 in h X 21 in d)

Recommmended Service Clearance (front and rear)

55 cm (22 in)

AC Power

4 A at 115 Vac; 2 A at 230 Vac
(dual drive)

Cable Included

BC05L-15 (15 tt)

Drive Performance
Capacity (8-bit bytes)
Per diskette
Per track
Per sector

262,144 bytes
3,328 bytes
128 bytes

Data Transfer Rate
Diskette to controller
buffer

4 ~sec/data bit (250K bits/sec)

Buffer to RXV11 interface

2 ~sec/bit (500K bits/sec)

RXV11 interface to LSI-11
I/O bus

18 ~sec/8-bit byte ( <50K
bytes/sec)

Track-to-track move

6 msec/track maximum

Head settle time

25 msec maximum

Rotational speed

360 rpm±2.5%; 166 msec/rev
nominal
459

RXV11
Recording surfaces per disk

Tracks per disk

77 (0-76) or (0-1148)

Sectors per track

26 (1-26) or (0-328)

Sectors per disk

2002

Recording technique

Double frequency

Bit density

3200 bits/in at inner track

Track density

48 tracks/in
262 msec, computed as follows:

Average access

Seek

Rotate

Settle

Total

(77 tks/3) x 6 msec + 25 msec + (166 msec/2) = 262 msec
Environmental Characteristics
Temperature
RX01, operating

15 0 to 32 0 C (59 0 to 90 0 F) ambient; maximum temperature
gradient = -6.7 0 C/hr (20 0 F/hr)

RX01, nonoperating

-35 0 to +60 0 C (-30 0 to +140 0
F)

Media, nonoperating

-35 0 to +52 0 C (-30 0 to + 125 0
F)

NOTE
Media temperature must be within operating temperature range before use.
Relative Humidity
RX01, operating

25 0 C (77 0 F) maximum wet bulb
2 0 C (36 0 F) minimum dew point
20% to 80% relative humidity

RX01, nonoperating

5% to 98% relative humidity (no
condensation)

Media, nonoperating

10% to 80% relative humidity

Magnetic field

Media exposed to a magnetic
field strength of 50 oersteds or
greater may lose data.
460

RXV11
System Reliability
Minimum number of
revolutions/track

3 million/media (head-loaded)

Seek error rate

1 in 105 seeks

Soft read error rate

1 in 109 bits read

Hard read error rate

1 in 1012 bits read

NOTE
The above error rates apply only to media that are
properly cared for. Seek error and soft read errors
are usually attributable to random effects in the
head/media interface, such as electrical noise, dirt,
or dust. Both are called "soft" errors if the error is
recoverable in ten additional tries or less. "Hard"
errors cannot be recovered. Seek error retries
should be preceded by an initialize.

CONFIGURATION
The factory jumper locations on the M7946 interface module are
shown in Figure 1. Note that two styles of modules are used; one style
(etch Rev B) has machine-inserted jumpers; the other (etch Rev e) has
wire-wrap jumpers. All M7946 interface modules are configured and
shipped with preselected register addresses and vectors as shown in
Figure 2. The control/status register (RXeS) address is 177170, and
the data buffer register (RXDB) address is 177172. The interrupt vector is 264 8 , As supplied, the factory-configured jumpers are for the
normal addresses used with DIGITAL software. However, in applications where more than one RXV11 system is required, appropriate
register addresses and vectors may be configured by installing or
removing jumpers. A second RXV11 system would normally be assigned register addresses 177174 (RXeS) and 177176 (RXDB), with an
interrupt vector of 270 8 (Table 2).

461

WI.

:D
_WI
_W2
_W3

_W'
_w,

Wi ....................... WJ
WZ e----e ...--.... WI!
W4....--... .......... W8
W1 ______ ------.. WI3
wa ____________ WI 4

_we

_WI

_we

W16 .......... ...--...W9

_WI

Wl0 ..............~W17
W" ______ ______ WIIS

.---w,o

W12e___e

___..W12

_____ WI'

......-...W16
W13"'--"" .....--.W18
Wi" .......... ...--.4Wl1

ETCH REV B . MACHINE INSERTED JUMPERS

Figure 1

ETCH REV C· WIRE-WRAP JUMPERS

RXV11 Device Register and Interrupt Vector Jumper
Locations

><
<
.....
.....

RXV11
DEVICE
ADDRESS

fACTOR'!'CONFIGURED-R
ADDRESS

RXCS"77170
RXDS ~ 177172

I I : : I : : I :
_Ii

OAL BITS-+fS
VECTOR
ADDRESS

00
0

JUMPER ON
M7946 MODULE

FACTORY-CONFIGURED _
VECTOR ADDRESS ~ 264

! I
I I I I I
1

NOTE'
I" Jumper ins1alled: L091COI 0
R. Jumper removed:: Loqicol 1
!'·3':'CI~

X: Don', core

Figure 2

Device Register Address and Interrupt Vector

Table 1

RXV11 Configurations

System

Disk Drive

Line Voltage*

RXV11-AA
RXV11-AC
RXV11-AD
RXV11-BA
RXV11-BC
RXV11-BD

Single drive system
Single drive system
Single drive system
Dual drive system
Dual drive system
Dual drive system

115V/60 Hz
115V/50 Hz
230V/50 Hz
115V/60 Hz
115V/50 Hz
230V/50 Hz

* 50 Hz versions are available_in voltages of 105, 115, 220, and 240 Vac by

field-pluggable conversion.

463

RXV11
Table 2

Standard Assignments

Description

Mnemonic

Read/
Write

First
Module
Address

Registers
Control/Status
Data Buffer

RXCS
RXDB

R/W
R/W

177170
177172

177174
177176

264

270

Interrupt
Function
Complete

Done

464

Second
Module
Address

RXV21
RXV21 FLOPPY DISK OPTION
INTRODUCTION
The RXV21 floppy disk option is a random access mass memory device that stores data in fixed-length blocks on a preformatted, flexible
diskette. Each diskette can store and retrieve up to 512K B.,.bit bytes of
data. The RXV21 system is rack-mountable and consists of an interface module, an interface cable, and either a single or dual RX02
floppy disk drive.
FEATURES
• Compact disk system
• Stores/retrieves 512K B-bit bytes of data

• Rack mountable
• Available with either single or dual disk drive
• Available for 115 or 230 Vac, 50 or 60 Hz
• Can be converted (50 Hz version) for 105, 115, 220 or 240 Vac
operation
• Direct Memory Access data tranfer
• Industry-compatible mode under software selection
SPECIFICATIONS
Module
Identification

MB029

Size

Double

Power

+5V ±5% at 1.BA typically

Bus Loads
AC
DC

3
1

Drive
Identification

RX02

Size

46.3 cm w X 2B.7 cm h X 53.3 cm
d
(19 in w X 10.5 in h X 21 in d)

Recommended Service

55 cm (22 in)
Clearance (front and rear)

465

RXV21
AC Power

4A at 115 Vac; 2A at 230 Vac
(dual drive)

Cable Included

BC05L-15 (15 ft)

Drive Performance
Capacity (8-bit bytes)
Per diskette

512,512 bytes

Per track

6,656 bytes

Per sector

256 bytes

Data Transfer Rate
Diskette to controller buffer

2 ~sec/data bit (500K bits/sec)

Buffer to RXV21 interface

1.2 ~sec/bit (500K bits/sec)

RXV21 interface to LSI-11
I/O bus

23 ~sec/16-bit word

Track-to-track move

6 msec/track maximum

Head settle time

25 msec maximum

Rotational speed

360 rpm ±2.5%; 166 msec/rev
nominal

Recording surfaces per disk

Tracks per disk

77 (0-76) or (0-1148)

Sectors per track

26 (1-26) or (0-328)

Sectors per disk

2002

Recording technique

Double frequency (FM) or modified (MFM)

Bit density

3200 bpi (FM); 6400 bpi (modified
MFM)

Track density

48 tracks/in
262 msec, computed as follows:

Average access

Seek

Rotate

Settle

Total

(77 tks/3) x 6 msec + 25 msec + (166 msec/2) = 262 msec

466

RXV21
Environmental Characteristics
Temperature
RX02, operating

15° to 32° C (59° to 90° F) ambient; maximum temperature
gradient = 11 °C/hr (20°F/hr)

RX02, nonoperating

-35° to +60° C (-30° to +140°
F)

Media, nonoperating

-35° to +52° C (-30° to +125°
F)

NOTE
Media temperature must be within operating temperature range before use.
Relative Humidity
RX02, operating

25° C (77° F) maximum wet bulb
2° C (36° F) minimum dew point
20% to 80% relative humidity

RX02, nonoperating

5% to 98% relative humidity (no
condensation)

Media, nonoperating

10% to 80% relative humidity

Magnetic field

Media exposed to a magnetic
field strength of 50 oersteds or
greater may lose data.

System Reliability
Minimum number of revolutions/track

3 million/media (head-loaded)

Seek error rate

1 in 106 seeks

Soft read error rate

1 in 109 bits read

Hard read error rate

1 in 1012 bits read

NOTE
The above error rates apply only to DIGIT AL-approved media that is properly cared for. Seek error
-and soft read errors are usually attributable to random effects in the head/media interface, such as
electrical noise, dirt, or dust. Both are called "soft"

467

RXV21
errors in that the error is recoverable in ten additional tries or less. "Hard" errors cannot be recovered.
Seek error retries should be preceded by an
initialize.

DESCRIPTION
The interface module converts the RX02 I/O bus to the LSI-11 bus
structure. It controls the RX02 interrupts to the processor, decodes
device addresses for register selection, and handles the data interchange between the RX02 and the processor via DMA transfers.
Power for the interface module is supplied by the LSI-11 bus.
The RXV21 floppy disk system is available in the configurations described in Table 1.

Table 1
System
RXV21-AA
RXV21-AC
RXV21-AD
RXV21-BA
RXV21-BC
RXV21-BD

RXV21 Configurations

Disk Drive
Single drive system
Single drive system
Single drive system
Dual drive system
Dual drive system
Dual drive system

Line Voltage·
115V/60 Hz
115V/50 Hz
230V/50 Hz
115V/60 Hz
115V/50 Hz
230V/50 Hz

* 50 Hz versions are available in voltages of 105. 115. 220. and 240 Vac by

field-pluggable conversion.

CONFIGURATION
The factory jumper locations on the M8029 interface module are
shown in Figure 1. All M8029 interface modules are configured and
shipped with preselected register addresses and vectors as shown in
Figure 2. The control/status register (RX2CS) address is 177170, and
the data buffer register (RX2DB) address is 177172. The interrupt
vector is 264 8 . As supplied, the factory-configured jumpers are for the
normal addresses used with DIGITAL software. However, in applications where more than one RXV21 system is required, appropriate
register addresses and vectors may be configured by installing or
removing jumpers. A second RXV21 system would normally be assigned register addresses 177200 (RX2CS) and 177202 (RX2DB), with
an interrupt vector of 270 8 (Table 2).
468

RXV21
Register Descriptions
Control/Status Register (RXCS)(177170) - The format for the RX2CS
register is shown in Figure 3. Bit descriptions are presented in Table 3.
Loading the RX2CS register while the RX01 is not busy and with bit 0 =
1 will initiate a function described in Table 3.

~================~"A

NOTES:
1. MODULE M7744 AND CABLE ASSEMBLY
BC05L ARE SUPPLIED WITH RX02
FLOPPY DISK SUBSYSTEM ASSEMBLY
2.RED STRIPE OF BCOSL INDICATES
PIN "A" ON THE CONNECTOR

Figure 1

RXV21 Device Register and Interrupt Vector Jumper
Locations

469

RXV21

To seiect the standard address, the following jumpers are installed:
A12
A11
A10
A9
Aa
A7
A6
A5
A4
A3

Installed
Installed
Installed
Installed
Removed
Removed
Installed
Installed
Installed
Installed

The standard Interrupt Vector is selected by installing the following jumpers:
V2
V3
V4
V5
V6
V7

Installed
Removed
Installed
Installed
Removed
Installed

Removed

Figure 2

Device Register Address and Interrupt Vector

Table 2

Standard Assignments

Description Mnemonic

First
Module
Address

Second
Module
Address

177170

177150

RX2DB

177172

177152

Done

264

270

Registers
Control!
Status
Data Buffer
Interrupt
Function
Complete

RX2CS

Readl
Write
See register
description

470

RXV21
3
FUNCTION

Figure 3

RXV21 Command and Status Register (RX2CS)

Table 3

RX2CS Bit Descriptions

Bit: 0
Name: GO
Function: Initiates a command to the RX02. Write-only.
Bit: 1-3
Name: Function Select
Function: These bits code one of the eight possible functions described in the Programming Specification. Write-only.
Bit: 4
Name: Unit Select
Function: This bit selects one of the two possible disks for execution
of the desired function. This bit is readable only when DONE is set. At
that time, it indicates the unit previously selected. At any other time it is
not valid.
Bit: 5
Name: DONE
Function: Indicates the completion of a function. DONE will generate
an interrupt upon being asserted if Interrupt Enable (RX2CS Bit 6) is
set. Read-only.
Bit: 6
Name: Interrupt Enable
Function: This bit is set by the program to enable an interrupt when
the RX02 has completed an operation (DONE). The condition of this bit
is normally determined at the time a function is initiated. Cleared by
initialize. Read/write.
Bit: 7
Name: Transfer Request
Function: This bit signifies that the RXV21 needs the next word in the
register protocol sequence (see Programming Specification). Readonly.
Bit: 8
Name: Density
Function: This bit determines the density of the function to be executed. This bit is readable only when DONE is set. At that time, it
indicates the density of the function previously executed. This bit is not
valid at any other time.

471

RXV21
Table 3

RX2CS Bit Descriptions (Cont)

Bit: 9
Name: Head Select
Function: This bit selects one of two heads for double-sided operation. This bit is readable only when DONE is set. At that time, it indicates the side that was previously selected. At any other time, it is not
valid.
Bit: 10
Name:
Function: Reserved.

Note: Must be written O.

Name: RX02
Bit: 11
Function: This bit is set by the interface to inform the programmer
that this is an RX02 system. Read-only.
Bit: 12-13 Name: Extended Address
Function: These bits are used to declare an extended bus address.
Write-only.
Bit: 14
Name: RXV21 Initialize
Function: This bit is set by the program to initialize the RXV21
without initializing all of the devices on the UNIBUS.
CAUTION: Loading the lower byte of the RX2CS will also load the
upper byte of the RX2CS. Upon setting this bit in the RX2CS, the
RXV21 will drop DONE and move the head position mechanism of
both drives (if two are available) to track zero. Upon completion of a
successful initialize, the RX02 will zero error and status and set DONE.
It will also read sector one of track one on drive O. At termination, drive
o head is at track one.

Bit: 15
Name: ERROR
Function: This bit is set by the RX02 to indicate that an error has
occurred during an attempt to execute a command. Cleared by the
initiation of a new command. Read-only.
RXV21 Data Buffer Register (RX2DB)
This register serves as a general purpose data path between the RX02
and the RXV21. It may represent one of six RX02 registers according
to the protocol in progress. (See Programming Specification.) This
register is read/write if the RX02 is not in the process of executing a
command; it may be manipulated without affecting the RX02.
Caution
Violation of protocol in manipulation of this register may
cause permanent data loss.

472

RXV21
RX2DB-RXV21 Data Buffer Register
o

RX2WC-RXV21 Word Count Register - For a double-density sector
the maximum word count is 12810 , For a single-density sector the
maximum word count is 64 10 , If a word count is beyond the limit for the
density indicated, the control asserts Word Count Overflow (Bit 10 of
RX2ES). Write-only register. The actual word count and not the 2's
complement of the word count is loaded into the register.
15

I I

....,..

0- 12810

RX2BA-RXV21 Bus Address Register - This register specifies the
bus address of data transferred during Fill Buffer, Empty Buffer, and
Read Definitive Error operations. Incrementation takes place after a
memory transaction has occurred. The RX2BA, therefore, is loaded
with the address of the first data word to be transferred. This is a 16-bit
write-only register (See Programming).
o

RX2CA-RXV21 Track Address Register - This is a write-only register which is loaded to indicate on which of the 77 10 tracks a given
function is to operate. It is addressed only under the protocol of the
function in progress.
15

8765432

o
)

0- 114 8

RX2SA-RXV21 Sector Address Register - This is a write-only
register which is loaded to indicate on which of the 26 10 sectors a given
function is to operate. It can be addressed only under the protocol of
the function in progress.
15

I0 I0 I0 I

.....,..
1 -328

473

)

RXV21
RX2ES-RXV21 Error and Status Register - The RX2ES is a readonly register available at the termination (DONE) of each function. The
Drive Ready bit is only updated during an Initialize or Read Status
function. At the termination of any other function, it reflects the drive
status of the last Read Status or Initialize command.
15

Name: CRC Error
Bit: 0
Function: The cyclic redundancy check at the end of the data field
has indicated an error. The data collected must be considered invalid.
It is suggested that the data transfer be re-tried up to 10 times, as most
data errors are recoverable (soft).
Bit: 1
Name: Side 1 Ready
Function: This bit, when set, indicates that a double-sided diskette is
mounted in a double-sided drive and is ready to execute a function.
This bit is only valid at the termination of an Initialize sequence or a
Maintenance Read Status command.
Bit: 2
Name: Initialize Done
Function: Indicates completion of the initialize routine. Can be asserted due to: a) a RX02 power failure, B) system power failure, C)
programmable or bus initialize.
Bit: 3
Name: RX AC La
Function: RX power failure. Bit is set when the subsystem power is
gone.
Bit: 4
Name: Density Error
Function: Indicates that the density of the function in progress does
not match the Drive Density. Upon detection of this error, the control
terminates the operation and asserts Error and Done.
Bit: 5
Name: Drive Density
Function: Indicates the density of the diskette mounted in the drive
indicated by the Unit Select bit.
Bit: 6
Name: Deleted Data
Function: In the course of recovering data, the "deleted data" address mark was detected at the begining of the data field. The Drv Den
bit(s) indicate whether the mark was an address mark. The data fol474

RXV21
lowing the mark will be collected and transferred normally, as the
deleted data mark has no further significance other than to establish
drive density. Any alteration of files or actual deletion of data, due to
this mark, must be accomplished by user software.
Bit: 7
Name: Drive Ready
Function: The selected drive is ready if Bit 7 = 1. All conditions for
disk operation are satisfied, such as door closed, power OK, diskette
up to speed, etc. The RX02 may be presumed to be ready to perform
any operation. This bit is only valid when retrieved with a Read Status
function or initialize.
Bit: 8
Name: Unit Select
Function: This bit indicates the drive on which the previous command was executed. This bit should agree with bit 4 of the RX2CSR for
commands which require drive operation.
Bit: 9
Name:
Function:
Reserved
Bit: 10
Name: Word Count Overflow
Function: The Word Count Register resides in the control. If the
control senses that the word count is beyond sector size it will terminate the Fill or Empty Buffer operation and set Error and,Done.
Name: Nonexistent Memory Error
Bit: 11
Function: This bit is set when a DMA transfer is being performed and
the memory address specified in RX2BA is nonexistent (does not respond to MSYN within 10 ~sec ).
PROGRAMMING
Data storage and recovery on the RXV21 occurs with careful manipulation of the two RXV21 registers (RX2CS, RX2DB) following the strict
protocol of the individual function. Data may be permanently lost if the
protocol is not followed. New functions given before the completion of
a previous function are ignored.

475

RXV21
Function Codes
The following is a detailed description of the programming protocol
associated with each function encoded and written into bits 1-3 of
RX2CS if DONE is set.
Function

Description

000

Fill Buffer
This function is used to fill the RX02 data buffer with
the number of words of data specified by the RX2WC
register. "Fill Buffer" is a complete function in itself.
The function ends when RX2WC overflows and, if
necessary, the control has zero-filled the remainder
of the buffer. The contents of the buffer may be written on the disk, by means of a subsequent Write
Sector command, or returned to the host processor
by an "Empty Buffer" command. To initiate this
function, the RX2CS is loaded with the function. Bit 4
of the RX2CS (Unit Select) does not affect this function, since no disk operation is involved. Bit 8 (Density) must be properly selected since this determines
the Word Count limit. When the command has been
loaded, the DONE bit (.RX2CS Bit 5) goes false. When
the TR bit is asserted, the RX2WC may be loaded
into the data buffer register. When TR is again asserted, the RX2BA may be loaded into the RX2DB.
The data words are transferred directly from memory and DONE goes true, ending the operation, when
RX2WC overflows and the control has zero-filled the
remainder of the sector buffer, if necessary. If bit 6
RX2CS (lnterrrupt Enable) is set, an interrupt is
initiated. Any read on the RX2DB during the data
transfer is ignored by the RXV21. After DONE is true,
the RX2ES is located in the RX2DB register.

001

Empty Buffer
This function is used to empty the contents of the
internal buffer through the RXV21 for use by the host
processor. This data is in the buffer as the result of a
previous "Fill Buffer" or "Read Sector" command.
The programming protocol for this function is identical to that for the "Fill Buffer" command. The RX2CS

476

RXV21
is loaded with the command to initiate the function.
This function will ignore bit 4 RX2CS (Unit Select).
RX2CS bit 8 (Density) must be selected to allow the
proper word count limit. When the command has
been loaded, the DONE bit (RX2CS bit 5) goes faise.
When the TR bit is asserted, the RX2WC may be
loaded into the RX2DB. When TR is again asserted,
the RX2BA may be loaded into the RX2DB. The
RXV21 assembles one word of data at a time and
transfers it directly to memory. Transfers occur until
Word Count overflow, at which time the operation is
complete and DONE goes true. If bit 6 RX2CS (Interrupt Enable) is set, an interrupt is initiated. After
DONE is true the RX2ES is located in the data buffer
register.
010

Write Sector
This function is used to locate a desired sector on
the diskette and fill it with the contents of the internal
buffer. The initiation of the function clears RX2ES,
TR, and DONE.
A. When TR is asserted, the program must load the
desired Sector Address into RX2DB, which will
drop TR.
TR will remain unasserted while the RX02 attempts to locate the desired sector. The diskette
density is determined at this time and is compared to the function density. If the densities do
not agree, the operation is terminated; bit 4
RX2ES is set, RX2ES is moved to the RX2DB,
Error (bit 15 RX2CS) is set, DONE is asserted,
and an interrupt is initiated if bit 6 RX2CS (Interrupt Enable) is set.
If the densities agree but the RX02 is unable to
locate the desired sector within two diskette revolutions, the RXV21 will abort the operation,
move the contents of RX2ES to the RX2DB, set
ERROR (bit 15 RX2CS), assert DONE, and initiate an interrupt if Bit 6 RX2CS (Interrupt Enable)
is set.

477

RXV21
B.

If the desired sector has been reached and the
densities agree, the RXV21 will write the 128 10 or
64 10 words stored in the internal buffer followed
by a CRC character which is automatically calculated by the RX02. The RXV21 ends the function by asserting DONE and if bit 6 RX2CS (Interrupt Enable) is set, initiating an interrupt.

CAUTION:
The contents of the sector buffer are not valid data
after a power loss has been detected by the RX02.
"Write Sector" however, will be accepted as a valid
instruction and the (random) contents of the buffer
will be written, followed by a valid CRC.
NOTE:
The contents of the sector buffer are not destroyed
during a write sector operation.
011

Read Sector
This function is used to locate the desired sector and
transfer the contents of the data field to the internal
buffer in the control. This function may also be used
to rapidly retrieve (5 ms) the current status of the
drive selected. The initiation of this function clears
RX2ES, TR, and DONE.
A. When TR is asserted, the program must load the
desired Sector Address into the RX2DB, which
will drop TR. When TR is again asserted, the
program must load the desired Cynlinder
Address into the RX2DB, which will drop TR.

TR and DONE will remain unasserted while the
RX02 attempts to locate the desired sector. If the
RX02 is unable to locate the desired sector within two diskette revolutions for any reason, the
RXV21 will abort the operation, set DONE and
ERROR (Bit 15 RX2CS), move the contents of
the RX2ES to the RX2DB, and if Bit 6 RX2CS
(Interrupt Enable) is set, initiate an interrupt.
If the desired sector is successfully located, the
control reads the data address mark and determines the density of the diskette. If the diskette
(drive) density does not agree with the function

478

RXV21

100

density, the operation is terminated and DONE
and ERROR (bit 15 RX2CS) are asserted. Bit 4
RX2ES is set (Density Error) and the RX2ES is
moved to the RX2DB. If Bit 6 RX2CS (Interrupt
Enabie) is set, an interrupt is initiated.
If the desired sector is successfully located, the
densities agree, and the data are transferred
with no CRC error, DONE will be set and if Bit 6
RX2CS (Interrupt Enable) is set, the RXV21 initiates an interrupt.

Set Media Density
This function causes the entire diskette to be reassigned to a new density. Bit 8 RX2CS (Density) indicates the new density. The control reformats the
diskette by writing new data address marks (double
or single density) and zeroing out all of the data
fields on the diskette.
The function is initiated by loading the RX2CS with
the command. Initiation of the function clears RX2ES
and DONE. When TR is set, an ASCII "I" (111) must
be loaded into the RX2DB to complete the protocol.
This extra character is a safeguard against an error
in loading the command. When the control recognizes this character it begins executing the command.
The control starts at Sector 1, Track 0 and reads the
header information, then starts a write operation. !f
the header information is damaged, the control will
abort the operation.
If the operation is successfully completed, DONE is
set and if Bit 6 RX2CS (Interrupt Enable) is set, an
interrupt is initiated.

NOTE:
If double-sided media is mounted in a double-sided
drive, both sides are set to the same density automatically.

479

RXV21
CAUTION:
This operation takes about 15 seconds and should
not be interrupted. If for any reason the operation is
interrupted, an illegal diskette has been generated
which may have data marks of both densities. This
diskette should again be completely reformatted.
101

Maintenance Read Status
This function is initiated by loading the RX2CS with
the command. DONE is cleared. The Drive Ready bit
(Bit 7 RX2ES) is updated by counting index pulses in
. the control. The Drive Density is updated by loading
the head of the selected drive and reading the first
data mark. All other RX2ES bits reflect the conditions created by the last command. During this
function, in addition to status, the control performs
the wraparound mode in the device electronics. If an
error occurs while wrapping the data from the Sector
Buffer through the device electronics, the Error bit
(Bit 15 RX2CS) is set. The RX2ES is moved into the
RX2DB. The RX2CS may be sampled when DONE
(Bit 5 RX2CS) is again asserted and if Bit RX2CS
(Interrupt Enable) is set, an interrupt will occur. This
operation requires approximately 250 msec to complete.

NOTE:
If double-sided media is mounted in a double-sided
drive, the Side 1 Ready bit (RX2ES bit 1) is set.
110

Write Sector With Deleted Data
This operation is identical to function 011 (Write Sector) with the exception that a deleted data address
mark is written preceding the data rather than the
standard data address mark. The Density bit associated with the function indicates whether a single or
double density deleted data address mark will be
written.

111

Read Error Code
The Read Error Code function implies a read extended status. In addition to the specific Error code,
a dump of the control's internal scratch pad registers
480

RXV21
also occurs. This is the only way that the Word Count
Register can be retrieved. This function is used to
retrieve specific information as well as drive status
information, depending on detection of the general
ERROR BIT.
The transfer of the registers is a DMA transfer. The
function is initiated by loading the RX2CS with the
command. DONE goes false. When TR is true, the
RX2BA may be loaded into the RX2DB and TR goes
false. The registers are assembled one word at a
time and transferred directly to memory.
Following is the Register Protocol.

NOTE:
The Density bit (bit 8 RX2CS) must be loaded with
the function. If the wrong assumption was made, an
error is returned.
Following is the Register Protocol.
15
WORD I

DIFINlT1VE ERROR CODE

15
WORD 2

CURRENT TRACK ADDR DRV 0

TARGET SECTOR

7
50FT STATUS

BAD TRACK •

Table 4

0
TARGET TRACK

15
WORD 4

CURRENT TRACK ADDR DRV I

WORD 3

WORD COUNT REGISTER

Definitive Error Codes

DRIVE 0 FAILED TO SEE HOME ON INITIALIZE

DRIVE 1 FAILED TO SEE HOME ON INITIALIZE

TRIED TO ACCESS A TRACK GREATER THAN 76

HOME WAS FOUND BEFORE DESIRED TRACK
WAS REACHED

481

RXV21
Table 4

Definitive Error Codes (Cont)

DESIRED SECTOR COULD NOT BE FOUND AFTER
52 TRIES

110

MORE THAN 40 MICROSECONDS AND NO SEP
CLOCK SEEN

120

A PREAMBLE COULD NOT BE FOUND

130

A PREAMBLE FOUND BUT NO ID MARK FOUND
WITHIN ALLOWABLE TIME

150

THE TRACK ADDRESS OF A GOOD HEADER DOES
NOT COMPARE WITH DESIRED TRACK

160

TOO MANY TRIES FOR IDAM

170

DATA ARE NOT FOUND IN ALLOTTED TIME

200

CRC ON READING THE SECTOR FROM THE DISK

220

FAILED MAINTENANCE WRAPAROUND CHECK

230

WORD COUNT OVERFLOW

240

DENSITY ERROR

250

INCORRECT KEY WORD ON SET DENSITY COMMAND

RX02 Power Fail or Initialize
When the RX02 control senses a loss of power within the RX02, it will
unload the head and abort all controller action. The RXAC L line is
asserted to indicate to the RXV21 that subsystem power is gone. The
RXV21 asserts DONE and ERROR and sets the RXAC L bit in the
RX2ES.
When the RX02 senses the return of power, it will remove DONE and
begin a sequence to:
1.

Move each drive head position mechanism to track 00

Clear any active error bits

Read sector 1 of track 1, on drive 0

Assert Initialize DONE in the RXES

Upon completion of the power-up sequence, DONE is again asserted.
There is no guarantee that information being written at the time of a
power failure will be retrievable; however, all other information on the
diskette will remain unaltered.
482

RXV21
lSI-11 Bus Power Fail
When the BPOK H line is negated by the LSI-11, the RXV21 asserts the
Initialize line and holds it asserted. The RX02 control unloads the head
and aborts controller action as detailed above. When LSI-11 power is
restored, the above power-up sequence is started.
* This is the only valid bit in the RX2ES at this time.

Programming Examples for Typical Operation
Disk Write

A typical disk write sequence, which is initiated by the user program,
would occur in two steps.
Fill Buffer-A command to fill the buffer is moved into the RX2CS. The
GO bit must be set. The program tests for TR. When TR is detected,
the program moves the desired word count into the RX2DB. TR goes
false while the word count is moved to the RX02. The program retests
TR and moves the Bus Address into the RX2DB. The device now
requests bus mastership and DMA's one data word at a time into the
RX2DB and shifts it across the RX02 data bus bit serially one 8-bit byte
at a time into the sector buffer. When the Word Count Register overflows and, if necessary, the RX02 control zero fills the remainder of the
sector buffer, the DONE bit is set and an interrupt will occur if the
program has enabled interrupts.
Write Sector-A command to write the contents of the sector buffer
onto the disk is moved into the RX2CS. The program tests TR and
when TR is set, moves the desired sector address to the RX2DB. TR
remains false while the sector address is shifted to the RX02 control.
The control retests TR and when it is again set, moves the desired
track address register to the RX2DB. Again TR is negated. The RX02
locates the desired track and sector and compares the diskette density against the assigned function density and writes the contents of the
sector buffer onto the disk if the densities agree. When the write operation is completed, the DONE bit is set and an interrupt will occur if the
program has enabled interrupts.
Disk Read
A typical disk read operation occurs in the reverse order. First, the
desired track and sector are located and the contents of the sector are
read into the sector buffer (Read Sector). Then, the contents of the
sector buffer are unloaded into memory (Empty Buffer). In either case,
the contents of the sector buffer are not valid if either a Power Failor
Initialize follows a Fill Buffer or Read Sector function.

483

RXV21
BOOTSTRAPPING THE RXV21
The RXV11 bootstrap loader program loads the system monitor from
disk into system memory. No system operation can occur until the
monitor is contained in system memory. Bootstrapping ("booting")
the system can be accomplished via a hardware-implemented
bootstrap in the REV11-A, or the BDV11 option, or it can be entered
and executed via the console device.
The following bootstraps are entered under microcode ODT. The bootable volume must be in drive zero. All devices are at standard addresses and vectors. Enter the code starting at location 1000. Inhibit
all interrupts by entering RS/_340 <CR>. Initialize the program
counter by entering R71_1000 <CR>. After the code has been entered, type P.
RX02 DOUBLE
DENSITY

RX02SINGLE
DENSITY

LOCATION

CODE

1000

12700

1002

100240

1004

12701

1006

177170

1010

5002

1012

12705

1014

200

100

1016

12704

1020

401

1022

12703

1024

177172

1026

30011

1030

1776

1032

100445

100437

1034

12711

1036

407

1040

30011

1042

1776

1044

100432

1046

100437

110413

484

RXV21
RX02DOUBLE
DENSITY

RX02SINGLE
DENSITY

LOCATION

CODE

1050

304

1052

30011

1054

1776

1056

110413

1060

304

1062

100431

30011

1064

1776

1066

100421

1070

12711

1072

403

1074

30011

1076

1776

1100

10414

100414

1102

10513

1104

30011

1106

1776

1110

100410

1112

10213

1114

60502

1116

60502

1120

122424

1122

120427

1124

1126

3735

1130

12700

1132

1134

5007

1136

120427

000003

485

TEV11
TEV11 TERMINATOR
INTRODUCTION
The TEV11 terminator module provides 120-ohm termination circuits
as shown in Figure 1.

SPECIFICATIONS
Identification

M9400-YB

Size

Double

Power

+5 Vdc ± 5% at O.54A

Bus Loads

o
o

AC
DC

DESCRIPTION
Each bus signal line terminates with two resistors as shown in Figure 2.
These termination resistors are generally contained in a 16-pin, dualin-line package which is identical to an IC package. Each package
contains 14 termination pairs. The values used are shown in the figure.
Daisy-chained grant signals are terminated and jumpered. BIAKI Lis
jumpered to BIAKO Land BDMGI L is connected to BDMGO L via
factory-installed jumper W1.
+5

180 n
M9400 - YB
UJ

::J

.:.. 14---+-----.-jL

120n BUS
TERMINATION

TO/FROM
SIGNAL - - - - - - /
LINES

...J

390n
11- 3597

Figure 1

TEV11 Functions
MR.1171

Figure 2

Typical

120-0hm Bus Termination
486

TU58
TU58 CARTRIDGE TAPE DRIVE
INTRODUCTION
The TU58 is a iow-cost inteiiigent mass memory device that offers random access to block-formatted data on pocket-size cartridge media. It
is ideal as inexpensive archive mass storage, or as a software update
distribution medium. A dual drive TU58 offers 512 Kb of storage space,
making it one of the lowest cost complete mass storage subsystems
available.

MA·2375

Figure 1

Loading a Cartridge

487

TU58
FEATURES
• 512 Kb per dual drive subsystem
• RS422, RS423, and RC232-C serial line I/O

• Reliable 30 inches per second read/write tape speed combined with
60 inches per second bidirectional search speed
• Flexible baud rates from 150 to 38,400
• Complete tape subsystem on one P.C. module for compact
mounting
• Microprocessor-based subsystem with automatic soft-error recovery via rereads.
SPECIFICATIONS
Performance
Capacity per cartridge

262,144 bytes, formatted in 512
blocks of 512 bytes each

Data reliability
Soft data error rate

1 in 107 bits read (before self-correction)

Hard error rate

1 in 109 bits read (unrecoverable
within eight automatic retries)

Hard error rate with write verify
and system correction

2 in 1011 bits read/written

Error checking

Checksum with rotation

Average access time

9.3 seconds

Maximum access time

28 seconds

Read/write tape speed

76 cm/s (30 ips)

Search tape speed

152 cm/s (60 ips)

Bit density

315 bits/cm (800 bitslin.)

Flux reversal density

945 fr/cm (2400 fr/in.)

Recording method

Ratio encoding

Medium

DECtape II cartridge with 42.7 m
(140 ft.) of 3.81 mm (0.150 in.)
tape
Size: 6.1 x 8.1 X 1.3 cm (2.4 X
3.2 X 0.5 in.)
488

TU58
Track format

Two tracks, each containing 1024
individually numbered, firmwareinterleaved "records." Firmware
..... ,.. ... ;..... Ia+"'s·
of"
a+• ea"h
IIIQIIlt-'UI
LO
I V....
U I '"""'''''''''''s
",-V, U
'-"
operation to form 512-byte
blocks.

Drive

Single motor, head integrally cast
into molded chassis.

Drives per controller

One or two. Only one may operate at a time.

Electrical
Power consumption

Module and one or two drives

11 W, typical, drive running
+5V ±5% at 0.75A, maximum
+12V + 10% -5% at 1.2A, peak
0.6A average running
0.1A idle

Serial interface standards

I n accordance with RS422 or
RS423; compatible with RS232·C.

Mechanical
Drive

8.1 H X 8.3 D X 10.6 W cm (3.2 X
3.3 X 4.1 in.) with 19 cm (7.5 in.)
cable 0.23 Kg (0.516Ibs.)

Board (Module)

13.2 H X 26.5 D X 3.5 W cm (5.19
X 10.44 X 1.4 in.) 0.24 Kg (0.5316
Ibs.)

Power connector to module

AM P 87159-6 with 87027-3 contacts (DEC part nos. 12-1220209, 12-12203-00)

Interface connector to module

AMP 87133-5 with 87124-1 locking clip contacts and 87179-1 index pin (DEC part nos. 12-1426802,12-14267-00,12-15418-00)

489

TU58
Environmental
Maximum dissipation
34 Btu/hour

TU58-AB, TU58-BB
Temperature
TU58-AB,BB operating
TU58- AB, BB nonoperating

-34°C (-30°F) to 60°C (140°F)

Medium operating
temperature

O°C (32°F) to 50°C (122°F)

Maximum temperature
difference between system
ambient and TU58 module
Relative Humidity, noncondensing
TU58 operating
Maximum wet bulb

26°C (79°F)

Minimum dew point

2°C (36°F)

Relative humidity

20% to 98%

TU58 nonoperating

5% to 98%

Medium nonoperating

10% to 80%

DRIVE AND MODULE INSTALLATION

Figures 2 and 3 provide the mounting dimensions for the circuit board
(module) and drive mechanism. The drive has a 19 cm (7.5 in.) cable
which plugs into the module header with the wires coming out of the
plug toward the center of the module. The plug is keyed to ensure
proper orientation. The cartridge extends 1.60 cm (0.62 in.) from the
front of the drive. If the drive is recessed in a panel, clearance must be
provided around the opening for fingers to grip the cartridge. Ideally,
the cartridge slot in a front panel will be somewhat larger than minimum, to allow easy insertion. The opening should be at least the dimensions of the cartridge, 1.3 cm (0.5 in.) x 8.1 cm (3.2 in.), located
not more than 0.53 cm (0.17 in.) above the bottom mounting surface.
The module should be mounted on a flat surface with 3 mm (4-40)
hardware and 1 cm (3/8 in.) standoffs. Both the module and the drive
490

russ
may be mounted at any angle. For mounting to a surface above the
drives, the 1.80 cm (0.71 in.) clearance is required; hole spacing is given in the outline drawings. For mounting to a surface below the
drives, an 8.18 em (3.22 in.) x R89 em (3.50 in.) chassis cutout is required, with the same mounting hole spacing.

CAUTION
The mounting sur:.face for the drives must be flat within
0.64 cm (0.025 in.).
I NTERFACE STANDARDS SELECTION AND SETUP
The TU58 is shipped with factory-installed jumpers for a transmission
rate of 38.4 kilobaud, and the RS-423 unbalanced line interface. A variety of standards and rates may be selected by changing the jumpers
on the controller module. Table 1 provides a list of all the pins on the
board and their functions, including the wire-wrap 0NW) pins, inter
face, and power connectors.

491

TU58

t f

4.57

(1.8)

5.46
(2.15)

14-_ _ _ 10.46 _ _---'~
(4.12)

8.18
(3.22)

I ~933~!

8.255
(3.25)

--Ld=:::::::::==::::::::::::;:::!.b

'(1.43) t(22)
i 3.63
.56

~
A

(71)

1.80

(138) DIA

1 4 - - - 8.89 _ _~
(3.50)

MEASUREMENTS ARE IN
CENTIMETERS EXCEPT
VALUES IN PARENTHESES
ARE IN INCHES.
MA-2369

Figure

Drive Outline Drawings

492

TUSS
24.853

1414---------(9.785)---------~

r
- - -=- -L-=-F:t;. .; ; ~. : ;:;.; : : :;:_: : :;:; ;: :;:; : : ; : :;:; : : ; : :;:; : : ;: : : :;: : ;: :;:; : : ; : :;:; : : ; ; ; ;:;.; ; ~ _et.::;_~.~=-=-=-=-=-====-:__4:ti~191
1.27 ~
(,501

14.775

.30

.64
(,251

(5.817)----~ (.121

.48

...
'

]

12.319
(4.850)

HEAT SINK

3.011.21 ABOVE (
0.5(0.21 BELOW!
'

f--------+I

1.52
406 (.61

3
5

SERIAL INTERFACE I
\ONNECTOfl

1~+12 POWER
GND CONNECTOR
+5
DRIVE 0

DRIVE 1

AMP HEADER #87633·6 AMP #87272·8
MATE. AMP #87159·6
DEC PT #12·13506·04
WITH # 87027 CONTACTS MATE AMP #87133·5
/
WITH #87124·1 CONTACTS

I
I

13.20
(5.197)
12.235
(4.817)

t-- 4.72

1}l=J-1'

1.86

-LJ-J.68
(.27)

I.
---1IIw=----i I
:.·;~I I.. I;

.48
(.191

14.643
(5.765) - - - - - - . I
17.734
(6.982)

t:.f}g)

1 + + - - .58
(,231

24.724

._ 1 4 - - - - - - - - - - - -2- 6- . 7 - 3 - - - (9. 734) --~
~-----------(l0.524)

MEASUREMENTS ARE IN
CENTIMETERS EXCEPT VALUES IN
PARENTHESES ARE IN INCHES
MEASUREMENTS ARE ± .013 (.0051 CENTER TO
CENTER
MA-2370

Module Outline Drawing

Table 1

TUSS Module Connections

Figure

Wire-Wrap
Pins
WW1
WW2
WW3
WW4
WW5
WW6
WW7
WW8
WW9
WW10
WW11
WW12
WW13

150 baud
300 baud
600 baud
1200 baud
2400 baud
4800 baud
9600 baud
19,200 baud
38,400 baud
UART Receive Clock
UART Transmit Clock
Auxiliary A (to interface connector pin L)
Auxiliary B (to interface connector pin A)
493

TUSS
WW14
WW1S
WW16
WW17
WW18
WW19
WW20
WW21
WW22
WW23
WW24

Factory Test Point
Ground
Boot Connect together for auto-boot on power-up
RS-423 Driver
RS-423 Common (Ground)
Transmit Line +
Transmit Line RS-422 Driver +
RS-422 Driver Receiver Series Resistor
(Jump for RS-422)

Serial Interface Connector
Auxiliary B
J2-10
J2-9
Ground
J2-8
Receive Line +
J2-7
Receive LineJ2-6
Key (no connection)

J2-S
J2-4
J2-3
J2-2
J2-1

Ground
Transmit Line Transmit Line +
Ground
Auxiliary A

J3,4-9
J3,4-10
J3,4-11
J3,4-12
J3,4-13
J3,4-14
J3,4-1S
J3,4-16

LED
Head Shield Ground
Erase Return
Erase 1
Erase 0
Head Return
Head 0
Head 1

Power Input Connector
J1-1
+12V
J1-3
Ground
J1-S
+SV
J1-6
Ground
Drive Cable
J3,4-1
Cart L
J3,4-2
No Connection
J3,4-3
Permit L
Signal Ground
J3,4-4
J3,4-S
Motor +
J3,4-6
Motor J3,4-7
+12V
J3,4-8
Tachometer

494

VK170-CA
SERIAL VIDEO MODULE
INTRODUCTION

The VK170 moduie forms an integrai part of a terminaL The moduie
accepts serial ASCII encoded data to be stored in a refresh memory
to generate a display for a video monitor. The VK170 also accepts parallel data from a keyboard (on strobe demand) to generate serial
ASCII output.
The VK170 is an extended-length, double-height, single-width board.
Mounting holes are provided for stand-oft mounting via handle rivets
and two holes located near the module fingers.

FEATURES

• Complete video subassembly on a double-height module
• Displays 80 characters per line and 25 lines
• 7 x 7 characters displayed in 8 x 8 character ce!ls using standard installed character ROM
• 8 x 8 character cell allows simple graphics with customer-defined character set
• Selectable attributes:
blink
half intensity
reverse video
characters, from customer-defined character set
• I.C. socket for two customer-defined character sets (2716 EPROM
or equivalent)
• EIA RS-423 serial interface for direct interconnect to DLV11-J or
MXV11
• Jumper-selectable baud rates: 150, 300, 600, 1200, 2400, 4800,
9600, 19,200, 38,400
• Smooth scrolling
• Drives standard video monitors over coaxial cable per EIA RS170,
or jumper-selectable for direct drive monitor
• Interfaces to a standard keyboard (8-bit ASCII)
• Can be plugged into LSI-11 backplanes or mounted on stand-ofts
applying power via H80? edge connector
495

VK170-CA
SPECI FICATIONS
Height

13.2 cm (5.2 in.)

Length

22.3 cm (8.5 in.)

Width

1.27 cm (0.5 in.)

Power Requirements

+5V ±5%, 1.2A
+ 12V (or -15V) ±3%, .15A

The VK170 module operates under the following conditions:
• Environment must conform to:
Temperature 5°C to 60°C
Humidity 10% to 95% (no condensation)
• Power dissipation is based on circuit requirements of 1.8 amps
maximum. If only 5 Vdc is used, power dissipation does not exceed
9 watts. An additional 2 watts (nominal) is dissipated when the
12 volts is enabled.

CONFIGURATION
Interface
This section describes the sequences of signal exchanges that occur
among the VK170 and other external devices. Figure 1 shows the pin
number locations of the interfacing connectors.
J3

97531

J1
12345

10864 2

2
MK-0689

Figure

1 Connector Pin Number Location Diagram

KeyboardNK170 Interface
The keyboard interfaces to the VK170 via a 20-pin connector (J2). The
DIGITAL mating connector is the H8561. Table 1 presents the connector pin numbers and associated signal names.

496

VK170-CA
Table 1
Pin No.
i

2
3
4
5
6
7
8
9
10

KeyboardlVK170 Connector (J2)

Signal Name
+5 Volts
-12 Volts
GND
KB8
KB7
GND
KB6
KBSTRB H
KB5
BREAK

Pin No.

Signal Name

11
I I

Io(RA
.'....,-r

12
13
14
15
16
17
18
19
20

Not used
KB3
BREAK (GND)
KB2
GND
KB1 (LSB)
GND
Not Used
Not Used

Edge Connector
VK170 edge connector pins and associated signals are presented in
Table 2.

Table 2
Pin No.

AA2,BA2
AC2,AT1 ,BC2, BT1
AB2
AD2
Others

VK170 Edge Connector
Signal Name
+5Vdc
GND
-15 Volts
+ 12 Volts
Not Connected

Video Output Connector
Video output is provided as RS170 compatible and as separate TTL
output lines. A 5-pin MOLEX* connector (J1) is used with pin assignments as shown in Table 3. (Mating connector = H8562.)
Composite video output provides RS170 output generated by combining the video signal with a composite sync signal. The picture from
the balancing level to reference white across 75 ohms is 1 volt. The
synchronizing levels are imposed at 40% of the signal.
* Vendor Trademark

497

VK170-CA
Table 3

Video Output Connector (J1)

Signal Name
HORIZONTAL DRIVE H
VERTICAL DRIVE L
VIDEOHIZ
GND
RS170 VIDEO

Pin No.
1
2

3
4
5

Timing/Freq
15.36 kHz/27 JlS
60 Hz/520 JlS

ovolts = SYNC
0.4 volts = BLACK
1.4 volts = WHITE
For direct drive output, jumper W4 must be cut, providing a high impedance source at the MOLEX* connector, pin 3. The VK170 has been
tested with the following direct drive monitors:
-ITOH
- Ball Brothers
- Elston

Communications Port Connector
The communications port is a 10-pin connector (J3), pinned for direct
DLV11-J connection. The electrical interface may be wired for RS-423
or 20 rnA communication (see Figure 2). The DIGITAL mating connector is H8560. Table 4 presents the pin assignments and associated
signal names.

RCV DATA _
RECV DATA +

~J:
8

UA18

,?::P
,
UA20

UA21

UA22

UAZl

-:-

Figure

KYBD MEM

Select RS-423/20 rnA Loop

* Vendor Trademark

498

VK170-CA
Table 4

Communications Port Connector (J3)

Pin No.

Signal Name

~I f"\~1(

GND

XMITDATA +

XMITDATA -

GND

NOT USED/POLARIZI NG POI NT

RCV DATA-

RCV DATA +

GND

20mASOURCE

""~""""''''''''I'

1/f"\
1',,-,

Installation Procedures
The following sections describe the installation of the VK170 module.
Jumper Configurations
Figure 3 illustrates the location of the various jumpers and wire wrap
posts of the VK170. Verify that the factory-installed jumpers are configured per Table 5. Any jumper configuration changes required for
user applications should be made at this time.
Data Rate Selection
The data rates are generated via a 13.5168 MHz crystal and selected
through a dual 4-bit decade and binary counter. The following data
rates are selectable: 150,300,600,1200,2400,4800,9600,19,200, and
38,400 bits per second.
The UART may be configured to transmit and receive at either the
same data rate or at split data rates. Data rates are configured by connecting a jumper from the selected data rate wire-wrap pin to the
clock input pin(s) of the UART. When configuring at the same data
rate, the wire-wrap pins may be daisy-chained. Table 6 lists the data
rates and their respective pin numbers.
The UART can be configured to operate from an external clock source
via pin 1 of J3. Both UA26 and UA27 must be jumpered to the external
clock. Do not select a data rate pin when using an external clock.
499

VK170-CA

RECE!VE
LEVEL

REMOVE TO
REVERSE VIDEO
r-t

UA20
UA19
UA18

COMPOSITE VIDEO
rI'I

..l-.

••• . .\ - . ~~.....

UA8::;l
UA 7

RECEIVE LEVEL

TRANSMIT
LEVEL

•

UA32
UA35
UA36
UA37

1~~
•••

UA24
UA25

} LOCAL
copy SELECT

UA2'

~:~~

UA60

UA34
UA33

.- •.J

r---I

_ _ LJ

HALF

INTENSITY

~:l

ATTRIBUTE SELECT

UA61
UA62

\
,---,

~::~

d=UJ···

UA41---.J

UM2

:~
••

UA43

E52 CHARACTER

SET SELECT

ATTRIBUTE
CONr OL

m
rI

e-----e

::
38

j ·.

----.

.....
W7

UA27 TRANSMIT CLOCK
UA26 RECEIVE CLOCK
UA12
UA17

1200
38400

UA16
UAll

19200
600

UA15 9600
UA10 300
UA14 4800
UA13 2400
UA9
150

UA40~

IN1T1AUZ~

UA39

FUNCTION

UA1
UA6
M7'4~

ETCH REV B

UA5

POWER PUMI='
VOLTAGE SELECT

UA3

UA4

Figure

Jumper and Wire Wrap Post Locations

Table 5

Factory-Installed Jumper Configurations

Jumper

Function Implemented

W1 (or UA 1 to UA5)

+ 12V operation

W2 (or UA4 to UA6)
W4

RS170 operation

Form feed receive enabled for remote initialization

UA59 to UA61 to UA62

8-bit-no parity

500

VK170-CA
Jumper

Function Implemented

UA18 to UA20

UA21 to U.A23

EIA RS-423 operation

UA34 to UA32
UA36 to UA37
W3

E52 character set enabled

UA39 to UA40

SI/SO (Shift In/Shift Out) attribute control

Forward video

UA41 to UA43

Blink attribute enabled

UA26 to UA27 to UA15

9600 data rate selected

Table 6
FROM

Transmit clock
pin UA27
and/or
Receiver clock
pin UA26

Data Rate Jumper Configurations
TO
Pin
UA9
UA10
UA11
UA12
UA13
UA14
UA15
UA16
UA17

Data Rate
150
300
600
1200
2400
4800
9600
19200
38400

Attributes and Attribute Control Selection
Several jumpers are used for attribute and attribute control selection.
Table 7 lists the various attribute and attribute control configurations.
Communications Selection
Four jumpers are used for communications selection. Table 8 lists
the jumper configurations required for either EIA RS-423 or 20 rnA current loop communications.

501

VK170-CA
Table 7

Attribute Jumper Configurations

Jumper

Characteristic

Install to enable character ROM E52
Remove to enable character ROM XE53

Install for forward video
Remove for reverse video

UA7to UA8

Install to disable half intensity

UA41 to UA42

Install to select reverse attribute

UA41 to UA43

I nstall to select bl i nk attri bute

UA40· to UA38

Install to select character bit 8 for attribute
control

UA40· to UA39

Install to select SI/SO for attribute control

* UA40 can either be jumpered to UA38 or UA39, but not both at the same

time.

Table 8

Communications Jumper Configurations

FROM

TO
RS423

20mA

UA18
UA21
UA34
UA36

UA20
UA23
UA32
UA37

UA19
UA22
UA33
UA35

Parity Selection
As many as three jumpers can be used to select ASCII serial data format. Table 9 lists the jumper configurations required to select either
odd, even, or no parity.

Voltage Selection
As many as six jumpers (two are optional) can be used for voltage selection. Table 10 lists the jumper configurations required for either
+ 12 Volt or -15 Volt operation.
502

VK170-CA
Table 9

Parity Jumper Configuration

Characteristic

Jumper

No Parity (8 data bits)

UA59 to UA61 to UA62

Odd Parity (7 data bits)

UA60 to UA61 to UA62 to UA63

Even Parity (7 data
bits)

UA60 to UA61 to UA62 and UA59 to UA60

Table 10

Voltage Jumper Configurations

Jumper
W1 (or UA1 to UA5)
W2 (or UA4 to UA6)
UA3to UA5
UA1 to UA6

+12V

-15V

In
In
Out
Out

Out
Out
In
In

Remote Initialize Selection
As many as three jumpers are used for remote initialize selection. Table 11 lists the jumper configuration required for remote initialization.
Table 11

Remote Initialize Jumper Configurations

Characteristic
Form Feed Receive
Break
None
Form Feed or Break

W6
Out
In
Out
In

W7
In
Out
Out
In

503

W8
Out
In
In
Out

W9500
W9500 HIGH-DENSITY WIRE-WRAPPABLE MODULES
INTRODUCTION
The W9500 series of high-density wire-wrappable modules enables a
user to easily configure special interface logic for the LSI-11 Microcomputer systems. These modules consist of DIGITAL's standard
double-and quad-height sizes and are available with or without premounted Dual-In-Line Packages (DIP) low-profile sockets.
SPECIFICATIONS
W9511 Quad-Height Without Sockets
Height
Quad, 10.5 in (26.6 cm)
Length

Extended, 8.9 in (22.8 cm)

Width

Single, 0.5 in (1.27 cm)

Vec Pins

AA2, BA2, CA2, DA2

GND Pins

AT1, BT1, CT1, DT1, AC2, BC2,
CC2, DC2

W9512 Double-Height Without Sockets
Height
Double, 5.2 in (13.2 cm)
Length

Extended, 8.9 in (22.8 em)

Width

Single, 0.5 in (1.27 cm)

Vce Pins

AA2, BA2

GND Pins

AT1, BT1, AC2, BC2

504

W9515

W9514

r
1D
D
D
D[JDDDD . DDDDD
DDDDDD ! DDDDD
DDDDDD ~ DDDDD
DDDDDD DDDDD
DDDDDD DDDDD
1\
/1I
I '-cONNECrORnJ

L_...!.-N~ ~~~t:P~ _ J

CONNECTOR J 1

I J2 WIRE WRAP PINS I

I Jl WIRE WRAP PINS I

~EVVR~

I C WIRE WRAP PINS I

I B WIRE WRAP PINS I

I A WIRE WRAP PINS I

ROW D

ROW C

ROW B

ROW A

EDGE CONNECTORS

00"''"0'"

'10-('

I J 1 WIRE WRAP PINS I

DDD DD
DDDD[] ..
DDD D[]
DDD D[]
DDD DD
(/)

II:
W

CD
U1

I B WIRE WRAP PINS I

~ I A WIRE WRAP PINS

r I

ROW B

IWW

o
o

EDGE CONNECTORS
MR

Figure 1

oil

LSI-11 Bus-Compatible Modules (With DIP Socketf,)

1160

W9S12

W9S11

SIDE 1
rj

SIDE 1

'-- CONNECTORJ2...J

~02.I~~O~I_ _

~~1
L

CONNECTORJ1

I J2 WIRC WRAP PINS I

CONNECTOR J 1

I J1 WIRE WRAP PINS I

LE WIRE WRAP PINS
r--

r--

.--

..--

<J)

0
Vl

I-

z
LU

I-

Vl
II:

II:

f')

f'}

I-

z
LU

w
~

Vl
II:

I-

W
l-

I-

olI

I-

W
I-

W
l-

0
Vl

f'}

'"0

I-

f'}

w
u

(,J1

olI

0
0

a'"
a

~
M

WIRE WRAP PINS

A WIRE WRAP PINS

ROW B

ROWA

LI...:B:..W:..:..:.:IR...:E:..;W;.:..:.cRAc.:.P:...,:..PI:.:.;N:.::S...JI._ I
.......
I I A WIRE WRAP PINS

ROWB

EDGE CONNECTORS

-r

ROW A

LSI-l1 Bus-Compatible Modules (No DIP Sockets)

I
I

EDGE CONNECTORS
MA

Figure 2

f'}

ROWC

f'}

ROWO

z·

C WIRE WRAP PINS

o WIRE WRAP PINS

1159

W9500
DESCRIPTION
The LSI-11 compatible series consists of four modules-- a quad-height
with and without premounted sockets and a double-height with and
without premounted sockets.
Table 1 provides a brief summary of each type. All modules are singlewidth; the height of each pin is 5/16 in
Each module without premounted sockets is configured to accept IC
packages with pin centers on 0.3 in (7.62 cm); 0.4 in (10.16 cm); and 0.6
in (15.24 cm). Each module can be wrapped by standard automatic
wrapping techniques as well as by hand.
Those modules with premounted sockets accept 16-pin ICs with 0.3 in
centers. Space is provided between the sockets for decoupling capacitors or other discrete components as required by the user. I n addition, these modules supplied with sockets also contain universal
areas that will accept ICs with pin centers of 0.3 in (7.62 cm); 0.4 in
(10.16 cm); and 0.6 in (15.24 cm). The accompanying drawings pOint out
these universal areas and their capacities.
The printed circuit on each board connects the appropriate edge connector pins to the Vcc plane on side 2 of the board and the ground
plane (GND) on side 1 (component side). The remaining edge connector pins terminate to a double row of wire-wrap pins for user designated functions. Each of the modules also includes a 40-pin male cable
connector to allow an interface cable to be attached to the module
logic. The pins of the cable connector are also terminated to a double
row of wire-wrap pins. The quad-height modules are also provided with
a space where an additional40-pin cable connector (labeled J2) can be
inserted by the user. When a connector is not required, additionallC
packages with .3, .4, and .6 in centers can be installed in the space
reserved for the connector. Each board contains insulated standoffs
to maintain the required clearance between adjacent modules and
prevent shorting of wire-wrap pins. A helpful alphanumeric X-V grid
pattern is also etched onto each board to facilitate ease in wire-wrap
pin location and identification.

507

W9500
Table 1

W9500 Series Modules

Module No.
Description

W9511

Quad-height, extended-length, single-width module with extractor handle. No DIP sockets included. One 40-pin male cable connector premounted
on board and space for additional 40-pin connector provided.

W9514

Same as W9511 except with 58 premounted DIP
sockets.

W9512

Double-height, extended-length, single-width
module with flip chip handle. No DIP sockets included. One 40-pin male cable connector premounted on board.

W9515

Same as W9512 except with 25 premounted DIP
sockets.

508

DMV11
DMV11 SYNCHRONOUS CONTROLLER
INTRODUCTION
The multipoint DDCMP-DMV11 Intelligent Communications Synchronous Line Controller is an interface device which provides efficient
high-speed synchronous communications for distributed networks.
The DMV11 uses LSI-11 CPUs as control or tributary stations, while
requiring a minimum of main CPU resources. The following provides
detailed information on the installation and operation of the DMV11.

FEATURES
• Support of point-to-point and multipoint operation
• Support of remote or local, full duplex, or half-duplex configurations
• Support of 12 tributaries and one control station in multipoint operation
• Switch and program selectable operating mode and tributary address
• Support for multiple-addressed tributaries
• Down-line loading and remote load detect capabilities
• Go/No-Go diagnostic testing by the microcode
• Go/No-Go extensive error reporting
• Modem control
There are three available DMV11 options. These are the DMV11-AA,
the DMV11-AB, and the DMV11-AC. The devices comprising each of
these three options are described below.

The DMV11·AA
• An M8053-MA microcontrollerlline unit (a quad-height module with
multipoint microcode)
• An H3254 (V.35 or integral modem) module test connector
• H3255 (RS-423-Al232-C) module test connector
• A BC55H cable and an H3250 and H3251 cable turnaround test
connector

509

DMV11
The DMV11·AB
• An M8053-MA microcontrollerlline unit (a quad-height module with
multipoint microcode)

• An H3254 (V.35 or integrai modem) module test connector
• H3255 (RS-423-A/232-C) module test connector
• A BC05Z-25 cable and an H3250 and cable turnaround test connector
The DMV11·AC
• An M8064-MA microcontrollerlline unit (a quad-height module with
multipoint microcode)

• An H3254 (V.35 or integral modem) module test connector
• H3255 (RS-423-A/232-C) module test connector
• A BC55F cable and H3257 and H3258 terminators
Table 1

Interface and Line Speed

Option

Interface

Line Speed
(DMV11 Limitations)

DMV11-AA

EIA RS-232-C
EIA RS-423-A

Up to 19.2K b/s
Upto 56K b/s

DMV11-AB

CCITTV.35

Upto 56K b/s

DMV11-AC

Integral modem

56K b/s only

System Requirements
• LSI·11 bus loading: The M8053-MA or the M8064-MA present two ac
loads and one dc load to the LSI-11 bus.

• Power requirements: Check the power supply before and after
installing the microcontrollerlline unit to ensure against overloading. Power requirements are listed in Table 2.
• Interrupt priority: The interrupt priority is preset to level four.
• Device address assignments: The DMV11 address resides in the
floati ng address space of the LSI-11 bus addresses. The selection of
the device address is accomplished by switch packs on the microcontroller/line unit module. Refer to Figures 1 and 2, and Table 3.
• Device vector address assignment: The DMV11 vectors reside in
the floating vector space of the LSI-11 bus addresses. The selection
of the vector address is accomplished by a switchpack on the m-icro510

DMV11
controller/line unit module. Refer to Figures 1 and 2, and Table 4.
• Device selectable feature: Please refer to Figures 1 and 2, and Table5.

Table 2

DMV11 Voltage Chart

Module

Voltage Rating

Maximum
Voltage

Minimum
Voltage

Backplane
Pin

MS053-MA

+5V@3.4A
+12 V @ 0.3S0 A

+5.25
+12.60

+5.0
+11.40

AA2
AD2

MS064-MA

+5 V@3.35A
+12 V @ 0.260 A

+5.25
+12.60

+5.0
+11.40

AA2
AD2

~IE10l

i.....--C

----J1 L..--C

_J2

----J1

_Jl

M8053

[§J

Figure

M8053 Switch Locations
511

DMV11

~I Elo71

M8064

~
~

Figure

M8064 Switch Locations

PROGRAMMING
Presented in the following paragraphs is a brief overview of the programming sequences relevant to DMV11 operation in network environments. For further detailed information covering programming and installation, the DMV11 User Guide is available and can be ordered as
supplementary material. The order number is EK-DMV11-UG-001.
Transfer of control and status information between the main CPU resident user program and the DMV11 is accomplished through four 16-bit
control and status registers (CSRs). I nput commands are issued to the
DMV11 by the user program, and output responses are issued to the
user program by the DMV11.
NOTE
Normally only four CSRs are used, but in 22-bit address mode, eight CSRs are available.

512

DMV11
Table 3

Device Address Selection

MSB
115114113112 111 110

I 1 I 1 I 1 I ..
I

I
I
I
SWITCH
NUMBER

I I

8 1 7

1 4

I
I
I

I
I
=;=1 M:~:3 I I

1 6

M8053 E53 M8064 E 58

2 11

1 0

I0 I

M8064
E59

I
I

1 3

LSB

I
Sl

DEVICE
ADDRESS
760020
760040

ON
ON

760060
760100

--ON

760200

--ON

760300
--760400

760500

760600
--760700

---

761000
--762000
--763000
--764000

ON
ON

ON
NOTE: SWITCH ON RESPONDS TO LOGICAL ONE ON THE BUS

Control and Status Registers
Four 16-bit CSRs are used to transfer control and status information.
These registers are both byte and word addressable. The eight bytes
are assigned addresses in the floating address space in the I/O page
as follows: 16XXXO, 16XXX1, 16XXX2, 16XXX3, 16XXX4, 16XXX5,
16XXX6, and 16XXX7.
For discussion, these byte addresses are designated byte select 0
through 7 (BSELO through BSEL07). BSEL 10 and BSEL11 are only used
in 22-bit address mode. BSEL12 through BSEL17 are not used bythe
user/DMV11-command structure and are not referred to in this section.
The four word addresses are the even numbered locations and are
designated select 0, 2, 4, and 6 (SELO, SEL2. SEL4, and SEL6). The CSR
addresses are assigned to the floating address space. The floating ad513

DMV11
Table 4

Vector Address Selection

MSB

LSB

SWITCH
NUMBER

817161S1413

M80S3 ES4
M8064 ES9

ON
ON
ON
ON
ON
ON
ON
ON

ON
ON
ON
ON
ON

ON
ON

1/0

•

ON
ON
ON
ON
ON
ON

VECTOR
ADDRESS
300
310
320
330
340
350
360
370
400

--SOO
---

600

--ON

700

---

NOTE: SWITCH ON PRODUCES LOGICAL ONE ON BUS

dress ranking for the DMV11 is 24. Detailed bit descriptions of SELO
and BSEL2 are provided in Tables 6 and 7 respectively.
The four bytes comprising SEL4 and SEL6 contain the fields pertinent
to each user-program command and DMV11 response.
Input Commands Overview
Input commands, in general, provide the means for the user program
to assign, receive, or transmit buffers to the DMV11.
There are four types of input commands that can be issued to the
DMV11 for execution. These commands are the microprocessor control/maintenance command; the mode definition; control; and buffer
address/character count.
With the exception of the microprocessor control/maintenance com. mand, input commands require an identifcation code in the first three
bits of BSEL2. These codes, which define each command and variations of specific commands within the command set, are defined in
Tables 7 and 8.
514

DMV11
Table 5
8

Switch Selectable Features
7

DDCMP ADDRESS REG!STER
TRIBUTARY/PASSWORD

E 119 IM8064)
E 113 IM8053)
8

MODE WHEN SWITCH
ONE IS SET

ZERO

REMOTE
LOAD
DETECT
ENABLE

= "ON"'

AUTO
ANSWER
POWER
ON

UNIT
NUMBER
FOR
BOOTING

MODE
ENABLE

BOOT
ENABLE
ZERO

E 107 IM8064)
E101 IM8053)

ON
ON
ON
ON
OFF

ON
ON
OFF
OFF
ON
ON
OFF
OFF

ON
OFF
ON
OFF
ON
OFF
ON
OFF

IOFF
OFF
OFF

SWITCH SETIING FOR THE MODE OF OPERATION.
HDX PT TO PT DMC COMPATIBLE
FDX PT TO PT DMC COMPATIBLE
HDX POINT TO POINT
FDX POINT TO POINT
HDX CONTROL STATION
FDX CONTROL STATION
HDX TRIBUTARY STATION
FDX TRIBUTARY STATION

9
HIGH SPEED SWITCH
MUST BE SET
FOR INTEGRAL
MODEM OR WHEN
RUNNING ABOVE 19.2KB

··ON·· = V.35
··OFF·· = EIA
M8053

= "ON"

HIGH
SPEED

* UNUSED
ON
M8064

E 1071M8064)
E 101 IM8053)
OFF = ··LOGIC ONE··

ZERO = ··ON·

515

DMV11
Table 6

SELO Bit Functions

Bits
BSELO

Name

Description

Interrupt
Enable In (lEI)

When set, this bit enables the DMV11,
upon asserting RDI (bit 4 of BSEL2),
to generate an interrupt to vector
address XXO.

1-3

Reserved

Interrupt
Enable Out
(lEO)

5-6

Reserved

Request In
(RQI)

This bit is set by the user program
to request access to the data port.
It is cleared by the user program when
the data port is not required for further
issuing of commands. The user program may leave RQI set if successive
requests for the data port are pending.

Maintenance
Request

When set, along with master clear (bit
14 of SEL4) , this bit causes the DMV11
to enter the maintenance register
emulation section of the microcode.

When set, this bit enables the DMV11,
upon asserting ROO (bit 7 of BSEL2),
to generate an interrupt to vector
address XX4.

BSEL1

NOTE
Detailed discussion of maintenance
register emulation is presented in
Section 4.8.

9-10

Reserved

Diagnostic Mode

Reserved

When set, this bit allows diagnostic
programs to change the mode of
operation of the DMV11 using the
mode definition command to override
the mode switches.

516

DMV11
Bits

Name

Description

Invoke P/MOP
Boot

Invoke primary MOP mode. When set
to one, this bit causes the DMV11 at
this multipoint station to request that
the control station initiate the primary
MOP (maintenance operation protocol)
boot procedure. In point-to-point networks, a DMV11 having this bit set
requests the other station to initiate
the primary MOP boot procedure.
NOTE
The master clear bit (bit 14) must
also be asserted to use invoke
P/MOP.

Master Clear

When set, this bit initializes the DMV11.
The clock is enabled and the RUN
flip-flop is set. Master clear is selfclearing.

Run

This bit controls running of the microprocessor. It is set by bus initialization
or master clear. When run is cleared
the microprocessor halts.

Table 7

BSEL2 Bit Functions

Bits

Name

Description

0-2

ControVResponse
Code

These bits define the type of input
command or output response as
follows.
Bits

Description

210

o 0 0 Buffer address/character
count (RCV) command or
buffer disposition (RCV
complete) response

517

DMV11
Bits

Name

Description

1 Control command or
control response

0 Mode definition command or information
response

0 0 Buffer address/character

1 Buffer disposition (RCV
unused) response
count (XMIT) command
or buffer disposition
(XMIT complete) response

1 Reserved

0 Buffer disposition (sent
but not acknowledged)
response

1 Buffer disposition (not
sent) response

22-Bit Mode

This bit when set indicates to the
DMV11 that the buffer address is in
the 22-bit format.

Ready In (RDI)

RDI is the DMV11 response to RQI,
indicating to the user program that it
has control of the CSRs to issue a
command. It is cleared by the user
program when the data port contains
the input command. Clearing RDI returns control back to the DMV11.

5-6

Reserved

Ready Out (ROO)

ROO is asserted by the DMV11 to
indicate that the data ports (SEL4 and
SEL6) contain an output response for
the user program. The user program
must clear ROO after it has read this
information. Clearing ROO returns the
CSRs to the DMV11.

518

DMV11
Table 8

I nput Command Codes

Input Command Type

Binary Code(BSEL2)

Mode definition
Control
Buffer address/character count
(receive)
Buffer address/character count
(transmit)

Bit

2
0
0
0

0
0

NOTE
CSR addresses are expressed in octal.

Output Responses Overview
Ouput responses provide a means for the DMV11 to report various normal and abnormal (error) conditions concerning the data transfer operation. The three basic responses are buffer disposition, control, and
information. The buffer disposition response is used to return both
used and unused buffers to the user program.
The control response is used to report error conditions concerning the
microcontrollerlline unit hardware, data link, physical link, or remote
station. It also passes protocol information to the user.
The information response provides information requested by a control
command from the user program.

519

DPV11·DA
DPV11·DA SERIAL SYNCHRONOUS LINE INTERFACE
INTRODUCTION
The DPV11·DA is a serial synchronous line interface for connecting an
LSI-11 bus to a serial synchronous modem that is compatible with EIA
RS-232-C interface standards and EIA RS-423-A and EIA RS-422-A
electrical standards. EIA compatibility is provided for use in local
communications only (timing and data leads only). The DPV11-DA is
intended for character-oriented protocols, such as BISYNC, byte
count-oriented protocols, such as DDCMP, or bit-oriented data communications protocols, such as SDLC. The DPV11-DA does not provide automatic error generating and checking for BISYNC.
The DPV11-DA is a bus request device only and must rely on the system software for service. Interrupt control logic generates requests for
the transfer of data between the DPV11-DA and the LSI-11 memory by
means of the LSI-11 bus. (Figure 1 illustrates the jumper locations for
the DPV11-DA.
The DPV11-DA consists of one double-height module and may be connected to an EIA RS-232-C modem by a BC26L-25 (RS-232-C) cable.

FEATURES
• Full-duplex or half-duplex operation
• Double-buffered transmitter and receiver
• EIA RS-232-C compatibility
• All EIA RS-449 Category 1 modem control
• Partial Category" modem control to include incoming call, test
mode, remote loopback, and local loopback
• Program interrupt on transitions of modem control signals
• Operating speeds of up to 56Kb/s (may be limited by software or
CPU memory)
• Software-selectable diagnostic loopback
• Operation with bit, byte count, or character-oriented protocols
• Internal cyclic redundancy check (CRC) character generation and
checking (not usable with BISYNC)
• Internal bit-stuff and detection with bit-oriented protocols
• Programmable sych character, sync insertion, and sync stripping
with byte count-oriented protocols
520

DPV11·DA
• Recognition of secondary station address with bit-oriented protocols

SPECI FICATIONS
Environment
Operating temperature
Relative humidity

5°C to 60°C (41°F to 140°F)
10% to 90% with max. wet bulb
temperature of 28°C (82°F) and a
min. dew point of 2°C (36°F)

Electrical specifications
The DPV11-DA requires these
voltages from the LSI-11 bus for
proper operation

12 V at 0.30 A max. (0.15 A typical) and 5 V at 1.2 A max. (0.92 A
typical)

Performance
Operating mode

Full- or half-duplex

Data format

Synchronous BISYNC, DDCMP,
and SDLC

Character size

Program-selectable (5-8 bits with
character-oriented protocols and
1-8 bits with bit-oriented protocols)

Max. configuration

16 DPV11-DA modules per LSI-11
bus

Max. distance

15 m (50 ft) for RS-232-C 61 m
(200 ft) for RS-423-A1RS-422-A
(Distance is directly dependent
on speed, and 200 ft is a suggested average. See RS-449
specifications for details.)

Max. serial data rates

56 Kb/s (May be less because of
software and memory refresh
limitations.)
521

DPV11·DA

.J1

0-0

0'00"00
3 4 5 6 7

WI 2

L-...--J~

ODO 0

8 9 10 11

~INTERFACE

TERMINAL/ 012}
TIMING
013
TERMINATING
014
RESISTOR
015
JUMPERS
016
FOR RS-422-A
017

SELECTION
JUMPERS

005b
W18 20

22
0'0
23

CLOCK JUMPERS

0C5660
24

26* 28

DATA SET CHANGE JUMPERS
"'W26 IS INPUT TO DSCNG FLIP FLOP

SHIPPED
ADDRESS
160010

SHIPPED
VECTOR
300

W2930 323436 38

40 42 44 46

.cQOOOOO

0909

000
41 43 45

00000
31 33 35 37 39

JUMPERS ARE
DAISY CHAINED

~
B

Figure

DPV11-DA Jumper Locations

Device Addresses
The five registers used in the OPV11 are shown in Table 4 (page 532).
Note that two of the registers (PCSAR and ROSR) have the same address. This does not constitute a conflict, however, because the
PCSAR is a write-only register and the ROSR is a read-only register.
These five registers occupy eight contigious byte addresses which begin on a boundary where the low-order three bits are zero, and can be
located anywhere between 1600008 and 177776s.
522

DPV11·DA
The OPV11-0A uses a universal-synchronous receiver/transmitter
(USYNRT) chip which accounts for a large portion of the OPV11-DA's
functionality. The USYNRT provides complete serialization, deserialization, and buffering of data to and from the modem.
Most of the OPV11-0A's registers are internal to the USYNRT. Only the
receiver control and status register (RXCSR) and the low byte of the
parameter control and character length register (PCSCR) are external.

NOTE
When using the special space sequence function, all
registers internal to the USYNRT must be written in
byte mode.

REGISTER BIT ASSIGNMENTS
Bit assignments for the five OPV11-0A registers are shown in Figure 2.
In the paragraphs below a description of each register using a bit assignment illustration and an accompanying table with a detailed description of each bit is provided.
Receive Control and Status Register (RXCSR) (Address 16xxxO)
Figure 3 shows the format for the receive control and status register.
Table 5, found on page 532, is a detailed description of the register.
This register is external to the USYNRT.

NOTE
The RXCSR can read in either word or byte mode.
However, reading either byte resets certain status
bits in both bytes.

Receive Data and Status Register (RDSR) (Address 16xxx2)
Figure 4 shows the the format for the receive data and status register.
It is a read-only register and shares its address with the parameter
control sync/address register (PCSAR) which is write-only. Table 3 is a
detailed description of the ROSA.
523

DPV11·DA
NOTE
The RDSR can read in either word or byte mode.
However, reading either byte resets data and certain
status bits in both bytes of this register as well as
bits 7 and 10 of the RXCSR.

Parameter Control Sync/Address Register (PCSAR) (Address 16xxx2)

The PCSAR is a write-only register which can be written in either byte
or word mode. Figure 5 shows the format and Table 7 is a detailed description of the PCSAR. This register shares its address with the
ROSR.
NOTE
Bit set (BIS) and bit clear (BIC) instructions cannot
be executed on the PCSCR, since they execute using
a read·modify·write sequence.

Parameter Control and Character Length Register (PCSCR) (Address
16xxx4)

The parameter control and character length register can be read from
or witten into in either word or byte mode. The low byte of this register
is external to the USYNRT and the high byte is internal. Figure 6
shows the format and Table 8 is a detailed description of the PCSCR.
Transmit Data and Status Register (TDSR) (Address 16xxx6)

The format for the transmit data and status register is shown in Figure
7 and in Table 9 is a detailed description. The TOSR is a read/write
register which can be accessed in either word or byte mode with no
restrictions. All bits can be read from or written into and are reset by
the Device Reset or Bus I NIT except where noted.

524

DPV11·DA
THE RXCSR CAN BE READ IN EITHER WORD OR
BYTE MODE. HOWEVER. READING EITHER BYTE
RESETS CERTAIN STATUS BITS IN BOTH BYTES

RXCSR
16XXXO
READ/WRITE

DATA
SET
CHANGE

RCV
ACTIVE

CLR
TO
SEND

INCOMING
CALL

LOCAL
ILl)
LOOP

SYNC
RCV
RX
INTR
OR
ENA
FLAG
EN
DETECT
THE RDSR CAN BE READ IN EITHER WORD OR
BYTE MODE. HOWEVER. READING EITHER BYTE
RESETS DATA AND CERTAIN STATUS BITS IN
BOTH BYTES OF THIS REGISTER AS WELL AS
BITS 7 AND 10 OF THE RXCSR
11

DATA
TERM
ROY

REO

SF/RL

TO
SEND

ASSEMBLED
BIT COUNT

ERROR
CHECK

DATA
SET
INTR
EN

RCVR
STATUS
READY

RCVR
READY

RDSR
16XXX2
READ ONLY
14

RCV
DATA
READY

DATA
MODE

00
RECEIVE DATA BUFFER

RCVR
OVER
RUN

END
OF
MESG
RCV
ABORT

START
OF
MESG

PCSAR
16XXX2
WRITE ONLY
10

ERROR DETECTION
SELECTION

ALL
PARTIES
ADDR

STRIP
SYNC OR
LOOP
MODE

PROTOCOL
SELECT

07
SECONDARY STATION

RECEIVER SYNC

IDLE
MODE
SELECT
SECD
ADRS
MODE
SEL

Figure 2 DPV11-DA Register Configurations and Bit Assignments
(Sheet 1 of 2)

525

DPV11·DA
PCSCR

16XXX4
READ/WRITE
15

R/W

'------.yr----

TRANSMITTER
CHARACTER LENGTH

RECBVER
RSVD
CHARACTER LENGTH

EXTD
ADDR
FIELD
EXTD
CONT
FIELD

SQ/TM

XMTR
ENAB

XMIT
INTR
EN

XMTR
ACTIVE

MAl NT
MODE
SELECT
XMTR
BUFFER
EMPTY

DEVICE
RESET

TDSR

16XXX6
READIWRITE
07
R/W

00
RfW

RiW

R,W

R, W

XMIT
DATA
LATE

RESERVED

TRANSMIT DATA BUFFER

END
OF
MESG

XMIT
GO
AHEAD
ABORT

START
OF
MESG

Figure 2
OPV11-0A Register Configurations and Bit Assignments
(Sheet 2 of 2)

DS'
CNG

8
SFD

. THIS BIT IS RESET BY READING EITHER BYTE OF THIS REGISTER
.. THESE BITS ARE RESET BY READING EITHER BYTE OF RSDR

Figure

Receive Control and Status Register (RXCSR) Format

526

DPV11·DA
Table 1

Jumper Configuration

(W1-W2) Driver Attenuation Jumper
Driver

Terminal
Timing

Normal'"
Configuration

Aiternate*
Option

W1 toW2

Not connected

Description

Bypasses attenuation resistor.
Jumper must be
removed for certain modems to
operate properly.

(W3-W11) Interface Selection Jumpers
Input
Signals

Normal*
Configuration

SO/TM
(PCSCR-5)

W5toW6

DM (DSR)
(RXCSR-9)

Not connected

Alternate*
Option

Description

Signal quality
W7toW6

Test mode

W10toW9

Data mode return
for RS-422-A

(W3-W11) Interface Selection Jumpers (Cont.)
Output
Signals

Normal*
Configuration

SF/RL
(RXCSR-O)

W3toW4

Local
Loopback

Alternate*
Option

Description

Select frequency
W5toW3

Remote loopback

W8toW9

Not connected

Local loopback

Not connected

W8 to W11

Local loopback
(alternate pin)

(W12-W17) Receiver Termination Jumpers
Receiver

Normal*
Configuration

Alternate*
Option

Receive Data

Not connected

W12toW13

527

Description

Connects terminating resistor for
RS-422-A compatibility

DPV11·DA
Receiver

Normal*
Configuration

Alternate*
Option

Send Timing

Not connected

W14 to W15

Receive Timing

Not connected

W16 to W17

Description

*Normal configuration is typically RS-423-A compatible. Alternate option is typically
RS-422-A compatible.

(W18-W23) Clock Jumpers
Function

NUll MODEM
ClK

Clock Enable

Normal*
Configuration

Alternate*
Option

Sets NUll ClK
MODEM ClK
to 2 kHz.

W20 to W18

W19 to W21
W22toW23

Description

W21 to W18

Sets NUll
MODEM ClK to
50 kHz.

W19 to W21
W22 toW23

Always installed
except for factory
testing.

(W24-W28) Data Set Change Jumpers
Modem Signal
Name

Normal*
Configuration

Alternate*
Option

Data Mode
(DSR)

W26toW24

Not connected

Clear to Send

W26toW25

Not connected

Incoming Call

W26toW27

Not connected

Receiver Ready W26toW28
(Carrier Detect)

Not connected

Description

Connects the
DSCNG flip-flop
to the respective
modem status
signal for transition detection.
Note: W26 is input
to DSCNG flip-flop

*Normal configuration is typically RS-423-A compatible. Alternate option is typically
RS-422-A compatible.

528

DPV11·DA
(W3-W11) Interface Selection Jumpers
Output
Signals

Normal*
Configuration

SF/Rl
(RXCSR-O)

W3toW4

local
loopback

AHernate*
Option

Description
Select frequency

W5 to W3

Remote loopback

W8toW9

Not connected

Local loopback

Not connected

W8 to W11

localloopback
(alternate pin)

(W12-W17) Receiver Termination Jumpers
Receiver

Normal*
Configuration

AHernate*
Option

Receive Data

Not connected

W12 to W13

Send Timing

Not connected

W14 toW15

Receive Timing Not connected

W16 to W17

Description
Connects terminating resistor for
RS-422-A compatibility

(W18-W23) Clock Jumpers
Function
NUll MODEM
ClK

Clock Enable

Normal*
Configuration

AHemate*
Option

Sets NUll ClK
MODEM ClK
to 2 kHz.

W20 toW18

W19toW21
W22toW23

Description

W21 to W18

Sets NUll
MODEM ClK to
50 kHz.

W19 to W21
W22toW23

Always installed
except for factory
testing.

529

DPV11-DA
(W24-W28) Data Set Change Jumpers
Modem Signal
Name

Normal*
Configuration

Alternate*
Option

Data Mode
(DSR)

W26toW24

Not connected

Clear to Send

W26toW25

Not connected

Incoming Call

W26toW27

Not connected

Receiver Ready W26toW28
(Carrier Detect)

Not connected

Description

Connects the
DSCNG flip-flop
to the respective
modem status
signal for transition detection.
Note: W26 is input
to DSCNG flip-flop

*Normal configuration is typically RS-423-A compatible. Alternate option is typically
RS-422-A compatible.

Table 2

Data Address Selection

DPVll-XX (MS0201 DEVICE ADDRESSING
MSB

LSB

13 112 111 1 10
1

I·I
•

I
W31

Is1716151413

•

JUMPERS

JUMPER
NUMBER

W30 W36 W33 W32 W39 W3S W37 W34 W35
X
X
X
X
X

X
X
X

X
X

DEVICE
ADDRESS
760010
760020
760030
760040
760050
760060
760070
760100

--760200

--X

760300
--760400

760500

--X

760600
---

X
X
X

. X INDICATES A CONNECTION TO W29. W29 IS TIED TO
GROUND JUMPERS ARE DAISY CHAINED.

530

760700
--761000
--762000
--763000
--764000

DPV11·DA
Table 3

Vector Address Selection

DPVll (MS0201 VECTOR ADDRESSING
MSB

LSB

JUMPER
NUMBER

S171615141

JUMPERS

1/0

W43 W42 W41 W40 W44 W45

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X

X
X

VECTOR
ADDRESS
300
310
320
330
340
350
360
370
400

--X

500

--X

600

--X

700

---

'X INDICATES A CONNECTION TO W46.
W46 IS THE SOURCE JUMPER FOR THE VECTOR ADDRESS
JUMPERS ARE DAISY CHAINED.

531

DPV11·DA
Table 4

DPV11· DA Registers

Address

Comments

Receive Control RXCSR
and Status

16xxxO

Word or byte*
addressable.
Read/write.

Receive Data
and Status

RDSR**

16xxx2

Word or byte*
addressable.
Read-only.

Parameter
Control
Sync/Address

PCSAR**

16xxx2

Word or byte
addressable.
Write-only.t

Parameter
Control and
Character
Length

PCSCR:j:

16xxx4

Word or byte
addressable.
Read/write.

Transmit Data
and Status

TDSR**

16xxx6

Word or byte
addressable.
Read/write.

*Reading either byte of these registers. clears data and certain status bits in other bytes
See Paragraphs 3.3.1 and 3.3.2.
**Registers contained within the USYNRT.
tit is not possible to do bit set or bit clear instructions on this register.
tThe high byte of this register is internal to the USYNRT.

Table 5

Receive Control and Status Register (RXCSR)
Bit Assignments

Bit

Name

Description

Data Set Change
(DSCNG)

This bit is set when a transition occurs on
any of the following modem control lines:
Clear to Send
Data Mode
Receiver Ready
Incoming Call
Transition detectors for each of these four
lines can be disabled by removing the
associated jumper.
Data Set Change is cleared by reading
either byte of the RXCSR or by Device
Reset or Bus INIT.

532

DPV11·DA
Bit

Name

Description
Data Set Change causes a receive inter_ •• _ .. :J: nS·Tr""II.. , .... :.. 5\
.... RV.TCII..
, .... :.. 6\J
r UlJl II U
II CI" \UIl - J allu
All ~I" \UIL
~-

are both set.
This bit reflects the state of the modem
Incoming Call line. Any transition of this bit
causes Data Set Change bit (bit 15) to be
asserted unless the Incoming Call line is
disabled by removing its jumper. This bit
is read-only and cannot be cleared
by software.

Incoming Call
(IC)

Clear to Send
(CTS)

This bit reflects the state of the Clear to
Send line of the modem. Any transition of
this line causes Data Set Change (bit 15)
to be set unless the jumper enabling the
Clear to Send signal is removed.
Clear to Send is a program read-only bit
and cannot be cleared by software.

Receiver Ready
(RR)

This bit is a direct reflection of modem
Receiver Ready lead. It indicates that the
modem is receiving a carrier signal. For
external maintenance loopback, this
signal must be high. If the line is open,
RR is pulled high by the circuitry.
Any transition of this bit causes Data Set
Change (bit 15) to be asserted unless the
jumper enabling the Receiver Ready signal
is removed.
Receiver Ready is a read-only bit and
cannot be cleared by software.

Receiver Active
(RXACT)

This bit is set when the USYNRT presents
the first character of a message to the
DPV11. It remains set until the receive data
path of the USYNRT becomes idle.
Receiver Active is cleared by any of the
following conditions: a terminating control
character is received in bit-oriented
protocol mode; an off transition of
Receiver Enable (RXENA) occurs; or
Device Reset or Bus INIT is issued.

533

DPV11·DA
Bit

Name

Description
Receiver Active is a read-only bit which
reflects the state of the USYNRT output
pin 5.

Receiver Status
Ready (RSTARY)

This bit indicates the availability of status
information in the upper byte of the receive
data and status register (RDSR). It is set
when any of the following bits of the RDSR
are set: Receiver End of Message
(REOM); Receiver Overrun (RCV OVRUN);
Receiver Abort or Go Ahead (RABORT);
Error Check (ERRCHK) if VRC is selected.
Receiver Status is cleared by any of the
following conditions: reading either byte of
the RDSR; clearing Receiver Enable (bit 4
of RXCSR); Device Reset, or Bus Init.
When set, Receiver Status Ready causes
a receive interrupt if Receive Interrupt
Enable (bit 6) is also set.
Receiver Status Ready is a read-only bit
which reflects the state of USYNRT pin 7.

Data Mode (DM)
(Data Set Ready)

This bit reflects the state of the Data Mode
signal from the modem.
When this bit is set it indicates that the
modem is powered on and not in test, talk
or dial mode.
Any transition of this bit causes the Data
Set Change bit (bit 15) to be asserted
unless the Data Mode jumper has been
removed.
Data Mode is a read-only bit and cannot
be cleared by software.

Sync or Flag
Detect (SFD)

This bit is set for one clock time when a
flag character is detected with bit -oriented
protocols, or a sync character is detected
with character-oriented protocols.
SFD is a read-only bit which reflects the
state of USYNRT pin 4.

534

DPV11·DA
Bit

Name

Description

Receive Data
Ready (RDATRY)

This bit indicates that the USYNRT has
assembied a data character and is ready
to present it to the processor.
If this bit becomes set while Receiver
Interrupt Enable (bit 6) is set, a receive
interrupt request will result.
Receive Data Ready is reset when either
byte of RDSR is read, Receiver Enable
(bit 4) is cleared, or Device Reset or Bus
INIT is issued.
RDATRY is a read-only bit which reflects
the state of USYNRT pin 6.

Receiver Interrupt
Enable (RXITEN)

Data Set Interrupt This bit, when set along with RXITEN,
Enable (DSITEN)
allows interrupt requests to be made to
the receiver vector whenever Data Set
Change (bit 15) becomes set.

When set, this bit allows interrupt requests
to be made to the receiver vector whenever RDATRY (bit 7) becomes set.
The conditions which cause the interrupt
request are the assertion of Receive Data
Ready (bit 7), Receive Status Ready
(bit 10), or Data Set Change (bit 15) if
DSITEN (bit 5) is also set.
RXITEN is a program read/write bit and is
cleared by Device Reset or Bus INIT.

DSITEN is a program read/write bit and is
cleared by Device Reset or Bus INIT.
4

Receiver Enable
(RXENA)

This bit controls the operation of the
receive section of the USYNRT.
When this bit is set, the receive section of
the USYNRT is enabled. When it is reset
the receive section is disabled.
In addition to disabling the receive section
of the USYNRT, resetting bit 4 initializes all
but two of the USYNRT receive registers.
The two registers not reinitialized are the

535

DPV11·DA
Bit

Name

Description
character length selection buffer and the
parameter control register.

Local Loopback
(LL)

Asserting this bit causes the modem connected to the DPV11 to establish a data
loopback test condition.
Clearing this bit restores normal modem
operation.
Local Loopback is program read/write
and is cleared by Device Reset or Bus
request to Send is program read/write
and is cleared by Device Reset or Bus INIT.

Request to Send
(RTS)

Setting this bit asserts the Request to
Send signal at the modem interface.
Request to Send is program read/write
and is cleared by Device Reset or Bus INIT.

Terminal Ready
(TR) (Data
Terminal Ready)

When set, this bit asserts the Terminal
Ready signal to the modem interface.
For auto dial and manual call origination, it
maintains the established call. For auto
answer, it allows handshaking in response
to a Ring signal.

Select Frequency This bit can be wire-wrap jumpered to
or Remote
function as either select frequency or
Loopback (SF/RL) remote loopback. When jumpered as
select frequency (W3 to W4), setting this
bit selects the modem's higher frequency
band for transmission to the line and the
lower frequency band for reception from
the line. The clear condition selects the
lower frequency for transmission and the
higher frequency for reception.
When jumpered for remote loopback (W5
to W3), this bit, when asserted, causes
the modem connected to the DPV11 to
signal when a remote loopback test
condition has been established in the
remote modem.

536

DPV11·DA
Bit

Description

Name

SF/RL is program read/write and is
cieared by Device Reset or Bus INIT.

REtEIVE DfTA

BU~FE'R

: :
9

ASSEMBLED
BIT COUNT

Figure

Receive Data and Status Register (ROSR) Format

Table 6

Receive Data and Status Register (RDSR)
Bit Assignments

Bit

Name

Description

Error Check
(ERR CHK)

This bit when set, indicates a possible
error. It is used in conjunction with the
error detection selection bits of the
parameter control sync/address register
(bits 8-10) to indicate either an error or
an all zeros state of the CRC register.
With bit-oriented protocols, ERR CHK
indicates that a CRC error has occurred. It
is set when the Receive End of Message
bit (ROSR bit 9) is set.
With character-oriented protocols ERR
CHK is asserted with each data character
if all zeros are in the CRC register. The
processor must then determine if this indicates an error-free message or not. If
VRC parity is selected, this bit is set for
every character which has a parity error.
ERR CHK is cleared by reading the ROSR,
clearing RXENA (RXCSR bit 4), Device
Reset or Bus INIT.

537

DPV11·DA
Bit

Name

14-12 Assembled Bit
Count (ABC)

Description

Used only with bit-oriented protocols,
these bits represent the number of valid
bits in the last character of a message.
They are all zeros unless the message
ends on an unstated boundary. The bits
are encoded to represent valid bits as
shown below.

Number of Valid Bits

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0

All bits are valid
One valid bit
Two valid bits
Three valid bits
Four valid bits
Five valid bits
Six valid bits
Seven valid bits

0
1

These bits are presented simultaneously
with the last bits of data and are cleared
by reading the RDSR or by resetting
RXENA (bit 4 of RXCSR).

Receiver Overrun
(RCVOVRUN)

This bit is used to indicate that an overrun
situation has occurred. Overrun exists
when the data buffer (bits 0- 7 of RDSR)
has not been serviced within one character time.
As a general rule, the overrun is indicated
when the last bit of the current character
has been received into the shift register of
the USYNRT and the data buffer is not yet
available for a new character.
Two factors exist which modify this
general rule and apply only to bit -oriented
protocols.
The first factor is the number of bits
inserted into the data stream for transparency. For each bit inserted during the
formatting of the current character, the
controller's maximum response time is
increased by one clock cycle.

538

DPV11·DA
Bit

Name

Description
The second factor is the result of termination of the current message. When this
occurs, the data of the terminated message which is within the USYNRT is not
overrunable. If an attempt is made to displace this data by the reception of a
subsequent message, the data of the
subsequent message is lost until the data
of the prior message has been released.

Receiver Abort or
Go Ahead
(RABORT)

This bit is used only with bit -oriented
protocols and indicate that either an abort
character or a go-ahead character has
been received. This is determined by the
Loop Mode bit (PCSAR bit 13). If the Loop
Mode bit is clear, RABORT indicates
reception of an abort character. If the
Loop Mode bit is set, RABORT indicates
a go-ahead character has been received.
The setting of RABORT causes Receiver
Status Ready (bit 10 of RXCSR) to be set.
RABORT is reset when the RDSR is read
or when Receiver Enable (bit 4 of RXCSR)
is reset.
The abort character is defined to be seven
or more contiguous one bits appearing in
the data stream. Reception of this bit pattern when Loop Mode is clear causes the
receive section of the USYNRT to stop
receiving and set RSTARY (bit 10 of
RXCSR). The abort character indicates
abnormal termination of the current
message.
The go-ahead character is defined as a
zero bit followed by seven consecutive
one bits. This character is recognized as a
normal terminating control character when
the Loop Mode bit is set. If Loop Mode is
cleared this character is interpreted as an
abort character.

Receiver End of
Message (REOM)

This bit is used only with bit -oriented
protocols and is asserted if Receiver

539

DPV11·DA
Bit

Name

Description
Active (bit 11 of RXCSR) is set and a message is terminated either normally or
abnormally. When REOM becomes set, it
sets RSTARY (bit 10 of RXCSR).
REOM is cleared when RDSR is read or
when Receive Enable (bit 4 of RXCSR) is
reset.

Receiver Start of
Message (RSOM)

Used only with bit-oriented protocols. This
bit is presented to the processor along
with the first data character of a message
and is synchronized to the last received
flag character. Setting of RSOM does not
set RSTARY (RXCSR bit 10).
RSOM is cleared by Device Reset, Bus
INIT, resetting Receiver Enable (RXCSR bit
4), or the next transfer into the Receive
Data buffer (lOW byte of RDSR).

7-0

Receive Data
Buffer

The low byte of the RDSR is the Receive
Data buffer. The serial data input to the
USYNRT is assembled and transferred to
the low byte of the RDSR for presentation
to the processor. When the RDSR receives
data, Receive Data Ready (bit 7 of RXCSR)
becomes set to indicate that the RDSR
has data to be picked up. If this data is
not read within one character time, a data
overrun occurs.
The characters in the Receive Data buffer
are right-justified with bit 0 being the least
significant bit.

540

DPV11·DA
432

Figure

Table 7

Parameter Control Sync/Address Register (PCSAR)
Format

Parameter Control Sync/Address Register (PCSAR)
Bit Assignments

Bit

Name

Description

All Parties
Addressed (APA)

This bit is set when automatic recognition
of the All Parties Addressed character is
desired. The All Parties Addressed character is eight bits of ones with necessary bit
stuffing so as not to be confused with the
abort character.
Recognition of this character is done in
the same way as the secondary station
address (see bit 12 of this register) except
that the broadcast address is essentially
hardwired within the receive data path.
The logic inspects the address character
of each frame for the broadcast address.
When the broadcast address is recognized, the USYNRT makes it available and
sets Receiver Start of Message (bit 8 of
ROSR).
If the broadcast address is not recognized,
one of two possible actions occurs.
1. If the Secondary Address Select mode
bit (bit 12) is set, a test of the secondary
station address is made.
2. If bit 12 is not set or the secondary station address is not recognized, the receive
section of the USYNRT renews its search
for synchronizing control characters.
541

DPV11·DA
Bit

Name

Description

Protocol Select
(PROT SEL)

This bit is used to select between
character- and byte count-oriented or
bit-oriented protocols. It is set for character- and byte count-oriented protocols
and reset for bit-oriented protocols.

Strip Sync or
Loop Mode
(STRIP SYNC)

This bit serves the following two functions.
1. Strip Sync {character-oriented protocols)-In character-oriented protocols, all
sync characters after the initial synchronization are deleted from the message
and not included in the CRC computation
if this bit is set. If it is cleared, all sync
characters remain in the message and
are included in the CRC computation.
2. Loop Mode (bit-oriented protocols)With bit -oriented protocols, this bit is
used to control the method of termination.
If it is set, either a flag or go-ahead character can cause a normal termination of a
message. If it is cleared, only a flag character can cause a normal termination.

Secondary
Address Mode
(SEC ADR MOE)

This bit is used with bit-oriented protocols
when automatic recognition of the secondary station address is desired. If it is
set, the station address of the incoming
message is compared with the address
stored in the low byte of this register.
Only messages prefixed with the correct
secondary address are presented to the
processor. If the addresses do not compare, the receive section of the USYNRT
goes back to searching for flag or goahead characters.
When SEC ADR MOE is cleared, the
receive section of the USYNRT recognizes all incoming messages.

Idle Mode Select
(IDLE)

This bit is used with both bit-and
character-oriented protocols.
With bit-oriented protocols, IDLE is used
to select the type of control character

542

DPV11·DA
Bit

Name

Description

issued when either Transmit Abort (bit 10
-zl Tll"'\uSR\ :- -_ ... - ... - ...... "' ... ,... •• _.....1_ .... .,.. ....... _ ......,... ..

J I;:) ;:)~l VI a u a l a UI IU~I I UI I ~I I VI

occurs. If IDLE is set, flag characters are
issued. If IDLE is clear, abort characters
are issued.
With character-oriented protocols, IDLE
is used to control the method in which
initial sync characters are transmitted and
the action of the transmit section of the
USYNRT when an underrun error occurs.
IDLE is cleared to cause sync characters
from the low byte of PCSAR to be transmitted. When IDLE is set, the transmit
data output is held asserted during an
underrun error and at the end of a message.
10-8

Error Detection
Selection
(ERR DEL SEL)

These bits are used to determine the type
of error detection used on received and
transmitted messages. In bit-oriented
protocols, the selection is independent of
character length. In character-and byte
count-oriented protocols, CRC error
detection is usable only with 8-bit character lengths. The maximum character
length for VRC is seven. The bits are
encoded as follows.

000

001

010
1
1

543

CRC Polynomial
X16+X12+X5+1 (CRC
CCITT) (Both CRC data
registers in the transmit
and receive sections are
set to all ones prior to the
computation.)
X16+X12+X5+1 (CRC
CeITT) (Both CRC data
registers set to all zeros.)

Not used
X16+X15+X2+1 (CRC 16)
(Both CRC registers set
to all zeros.)

DPV11·DA
Bit

Description

Name

Error Detection
Selection
(ERR DEL SEL)
(Cont)

10-8

7-0

Sync Character
or Secondary
Address

10
1

9
0

8
0

1
1

0
1

CRC Polynomial
Odd VRC Parity (A parity
bit is attached to each
transmitted character.)
Should be used only in
character -oriented
protocols.
Even VRC parity
(Resembles odd VRC
except that an even number of bits are generated.)
Not used.
All error detection is
inhibited.

The low byte of PCSAR is used as either
the sync character for character-oriented
protocols or as the secondary station
address for bit-oriented protocols.
The bits are right-justified with the least
significant bit being bit O.

EXTERNAL TO THE USYNRT
~

(

_______________

~A~

__________

INTERNAL TO THE USYNRT
~

(

___________
14

~A~

__________

8 '\

TRANSMITTER
CHARACTER LENGTH

Figure

Parameter Control and Character Length Register
(PCSCR) Format
544

DPV11·DA

Table 8

Bit

Parameter Control and Character Length
Register (PCSeR) Bit Assignments

Name

15-13 Transmitter
Character Length

Description
These bits can be read or written and are
used to determine length of the characters
to be transmitted.
They are encoded to set up character
lengths as follows.
15

0
1
1
1

0
1
1
0

0
1
0
1

Character Length
Eight bits per character
Seven bits per character
Six bits per character
Five bits per character
(bit-oriented protocol
only)
Four bits per character
(bit -oriented protocol
only)
Three bits per character
(bit-oriented protocol
only)
Two bits per character
(bit-oriented protocol
only)
One bit per character
(bit-oriented protocol
only)

These bits can be changed while the
transmitter is active, in which case the
new character length is assumed at
the completion of the current character.
This field is set to a character length of
eight by Device Reset or Bus INIT. When
VRC error detection is selected, the
default character length is eight bits
plus parity.
545

DPV11·DA
Bit

Name

Extended Address This bit is used with bit-oriented protocols
Field (EXADD)
and affects the address portion of a message in receiver operations. When it is set,
each address byte is tested for a one in
the least significant bit position. If the least
significant bit is zero, the next character is
an extension of the address field. If the
least significant bit is one, the current
character terminates the address field and
the next character is a control character.
EXADD is not used with Secondary
Address Mode (bit 12 of PCSAR).
EXADD is read/write and is reset by
Device Reset or Bus INIT.

Extended Control
Field (EXCON)

This bit is used with bit-oriented protocols
and affects the control character of a
message in receiver operations. When
EXCON is set it extends the control field
from one 8-bit byte to two 8-bit bytes.
EXCON is not used with Secondary
Address Mode (bit 12 of PCSAR).
EXCON is read/write and is reset by
Device Reset or Bus INIT.

10-8

Receiver
Character Length

These bits are used to determine the
length of the characters to be received.
They are encoded to set up character
lengths as follows.

Description

10
0
1
1
1
1

0
1
1
0
0

0
1
0
1
0

546

Character Length
Eight bits per character
Seven bits per character
Six bits per character
Five bits per character
Four bits per character
(bit-oriented protocols
only)
Three bits per character
(bit-oriented protocols
only)

DPV11·DA
Bit

Name

Description

10 9 8
010

Character Length

Two bits per character
(bit-oriented protocols
only)
One bit per character
(bit-oriented protocols
only)

Reserved

Transmit Interrupt When set, this bit allows a transmitter
Enable (TXINTEN) interrupt request to be made to the transmitter vector when Transmit Buffer Empty
(TBEMTY) is asserted. Transmit Interrupt
Enable (TXINTEN) is read/write and is
cleared by Device Reset or Bus INIT.

Signal Quality or
Test Mode
(SQITM)

Not used by the DPV11.

This bit can be wire-wrap jumpered to
function as either Signal Quality or Test
Mode.
When jumpered for signal quality (W5 to
W6), this bit reflects the state of the signal
quality line from the modem. When
asserted, it indicates that there is a low
probability of errors in the received data.
When clear it indicates that there is a high
probability of errors in the received data.
When jumpered for the test mode (W6 to
W7), this bit indicates that the modem has
been placed in a test condition when asserted. The modem test condition could
be established by asserting Local Loopback (bit 3 of RXCSR), Remote Loopback
(bit 0 of RXCSR) or other means external
to the DPV11.
When SQITM is clear, it indicates that the
modem is not in test mode and is available
for normal operation.
SQITM is program read-only and cannot
be cleared by software.

547

Bit

Name

Description

Transmitter
Enable (TXENA)

This bit must be set to initiate the transmission of data or control information.
When this bit is cleared, the transmitter
will revert back to the mark state once all
indicated sequences have been completed. TXENA should be cleared after
the last data character has been loaded
into the transmit data and status register
(TDSR). Transmit End of Message (bit 9 of
TDSR) should be asserted when TXENA
is reset (if it is to be asserted at all), and
remain asserted until the transmitter
entefs the idle mode. TXENA is connected
directly to USYNRT pin 37. It is a read/
write bit and is reset by Device Reset or
Bus INIT.

Maintenance
Mode Select
(MM SEL)

When this bit is asserted, it causes the
USYNRT's serial output to be internally
connected to the USYNRT's serial input.
The serial send data output line from the
interface is asserted and the receive data
serial input is disabled. Send timing and
receive timing to the USYNRT are disabled
and replaced with a clock signal generated
on the interface. The clock rate is either
49.1S2K b/s or 1.9661K b/s depending on
the position of a jumper on the interface
board.
Maintenance mode allows diagnostics to
run in loopback without disconnecting the
modem cable.
MM SEL is a read/write bit and is cleared
by Device Reset or Bus INIT. When it is
cleared, the interface is set for normal
operation.

Transmitter Buffer
Empty (TBEMTY)

This bit is asserted when the transmit
data and status register (TDSR) is available for new data or control information. It
is also set after a Device Reset or Bus
INIT.

548

Bit

Name

Description
Tho
Tn~o Shl"\lllrI
ho I"'arled ",
... 1.. ; ...
I IIC 1...,."-'11
IIVUIU Ir...IV IV U
Villy III

response to TBEMTY being set. When the
TDSR is written into, TBEMTY is cleared.
If TBEMTY becomes set while Transmit
Interrupt Enable (bit 6 of PCSCR) is set;
a transmit interrupt request results.
TBEMTY reflects the state of USYNRT pin

35.
1

Transmitter
Active (TXACT)

This bit indicates the state of the transmit
section of the USYNRT. It becomes set
when the first character of data or control
information is transmitted.
TXACT is cleared when the transmitter
has nothing to send or when Device Reset
or Bus INIT is issued.
TXACT reflects the state of USYNRT pin

34.

Device Reset
(RESET)

When a one is written to this bit all components of the interface are initialized. It
performs the same function as Bus INIT
with respect to this interface. Modem
Status (Data Mode, Clear to Send,
Receiver Ready, Incoming Call, Signal
Quality or Test Mode) is not affected.
RESET is write-only; it cannot be read by
software.

Figure

Transmit Data and Status Register (TDSR) Format

549

Table 9

Transmit Data and Status Register (TDSR)
Bit Assignments

Bit

Name

Description

Transmitter
Error (TERR)

This is a read-only bit which becomes
asserted when the Transmitter Buffer
Empty (TBEMTY) indication has not been
serviced for more than one character time.
When TERR occurs in bit-oriented protocols, the transmit section of the USYNRT
generates an abort or flag character
based on the state of the IDLE bit (PCSAR
bit 11). If IDLE is set, a flag character is
sent. If it is reset, an abort character is
sent.
When TERR occurs in character -oriented
protocols, the state of the IDLE bit again
determines the result. If IDLE is set, the
transmit serial output is held in the MARK
condition. If it is cleared, a sync character
is transmitted.
TERR is cleared when TSOM (TDSR bit 8)
becomes set or by Device Reset or
Bus INIT.
Clearing Transmitter Enable (PCSCR bit 4)
does not clear TERR and TERR is not set
with Transmit End of Message.

14-12 Reserved

Not used by the DPV11.

This bit, when asserted, modifies the bit
pattern of the control character initiated
by either Transmit Start of Message
(TSOM) or Transmit End of Message
(TEOM). TSOM or TEOM normally causes
a flag character to be sent. If TGA is set,
a go-ahead character is sent in place of
the flag character.

Transmit Go
Ahead (TGA)

TGA is only used with bit -oriented
protocols.
10

Transmit
Abort (TXABORT)

This bit is used only with bit-oriented
protocols to abnormally terminate a message or to transmit filler information used
to establish data link timing.
550

DPV11·DA
Table 9
Bit

Transmit Data and Status Register (TDSR)
Bit Assignments (Cont)

Name

Description
When TXABORT is asserted, the transmitter automatically transmits either flag
or abort characters depending on the
state of the IDLE mode bit. If IDLE is
cleared, abort characters are sent. If
IDLE is set, flag characters are sent.

Transmit End of
Message (TEOM)

This control bit is used to normally terminate a message in bit-oriented protocol.
It also terminates a message in characteroriented protocols when CRC error detection is used. As a secondary function, it is
used in conjunction with the Transmit Start
of Message (TSOM) bit to transmit a
SPACE SEQUENCE. Refer to the TSOM
bit description (bit 8 of this register) for
information regarding this sequence.
With bit-oriented protocols, asserting this
bit causes the CRC information to be
transmitted, if CRC is enabled, followed
by flag or go-ahead characters depending
on the state of the Transmit Go Ahead
(TGA) bit. See bit 11 of this register.
With character-oriented protocols,
asserting this bit causes CRC information,
if CRC is enabled, to be transmitted followed by either sync characters or a
MARK condition depending on the state
of the IDLE bit. If IDLE is cleared, sync
characters are transmitted.
The character following the CRC information is repeated until the transmitter is
disabled or the TEOM bit is cleared.
A subsequent message may be initiated
while the transmit section of the USYNRT
is active. This is accomplished by clearing
the TEOM bit and supplying new message
data without setting the Transmit Start
of Message bit. However, the CRC
character for the prior message must
have completed transmission.
551

DPV11·DA
Bit

Name

Description

Transmit Start
of Message
(TSOM)

This bit is used with either bit- or
character-oriented protocols. As long
as it remains asserted, flag characters
(bit-oriented protocols) or sync characters
(character -oriented protocols) are
transmitted.
With bit-oriented protocols, a space
sequence (byte mode only) of 16 zero bits
can be transmitted by asserting TSOM
and TEaM simultaneously provided the
transmitter is in the idle state and Transmit
Enable is cleared. This should not be done
.during the transfer of data, and must only
be done in byte mode.
NOTE
When using the special space sequence
function, all registers internal to the
USYNRT must be written in byte mode.

Normally at the completion of each sync,
flag, go-ahead or Abort character, the
TBEMTY indication is asserted. This allows
the software to count the number of
transmitted characters. In certain applications, the software may elect to ignore the
service of the Transmitter Buffer Empty
(TBEMTY) indication. Normally during
data transfers, this would cause a transmit data late error. The TSOM bit asserted
suppresses this error and provides the
necessary synchronization to automatically transmit another flag, go-ahead or
sync character.
7 -0

Transmit Data
Buffer

Data from the processor to be transmitted
on the serial output line is loaded into this
byte of the TO SA when Transmitter Buffer
Empty (TBEMTY) is asserted. If the transmitter buffer is not loaded within one
character time, an underrun error occurs.
The characters are right-justified, with
bit 0 being the least significant bit.

552

DPV11·DA
DATA TRANSFERS
A discussion on receive and transmit data transfers as they relate to
system software is addressed below.

Receive Data
Serial data to be presented to the OPV11-0A from the modem enters
the receiver circuit and is presented to the USYNRT. Recognition by
the USYNRT of a control character initiates the transfer. When a transfer has been initiated, a character is assembled by the USYNRT and
then placed in the low byte of the receive data and status register
(ROSR) when it is available. If the ROSR is not available, the transfer is
delayed until the previous character is serviced. This must take place
before the next character is fully assembled or an overrun error exists.
Refer to the description of bit 11 in Table 6 for more details on the Receiver Overrun.
Servicing the ROSR is the responsibility of the system software in response to the Receiver Data Ready (ROATRy) signal. This signal is asserted when a character has been transferred to the ROSA. The setting of the ROATRY would also create a receive interrupt request if
Receive Interrupt Enable (RXITEN) is set. The software's response to
ROATRY is to read the contents of the ROSA. At the completion of the
operation, the new information is loaded into the ROSR and ROATRY
is reasserted. This operation continues until terminated by some control character. The upper byte of the ROSR contains status and error
indications which the software can also read.
The OPV11-0A will also handle data in bite, byte-count- or characteroriented protocols.
With bit-oriented protocol, only flag characters are used to initiate the
transfer of the message. Information inserted into the data stream for
transparency or control is deleted before it is presented to the ROSA.
This means that only data characters are available to the software.
The first two characters of every message or frame are defined to be 8bit characters and the USYNRTwili handle them as such regardless of
the programmed character length. All subsequent data is formatted in
the selected character length. When CRC error detection is selected,
the received CRG check characters are not presented to the software,
but the error indication will be presented if an error has been detected.
If the secondary address mode is implemented, the first received data
character must be the selected address. If this is not the case, the

553

DPV11·DA
USYNRTwili renew its search for flag or go-ahead characters. Refer to
the description of bit 12 of the PCSAR in Table 7.
With byte count or character-oriented protocols, two consecutive sync
characters are required to synchronize the data transfer. The sync
characters used in the message must be the same as the sync character loaded by the software into the low byte of the parameter control
sync/address register. If leading sync characters subsequent to the
initial two syncs are to be deleted from the data stream, the Strip Sync
bit (bit 13) must alos be set in the upper byte of the PCSAR. The character length of the data to be received should also be set in bits 8, 9,
and 10 of the parameter control and character length register (PCSCR).
Sync -characters and data must have the same character length and
only characters of the selected length will be presented to the receive
buffer. Sync characters following the initial two will be presented to
the buffer and included in the CRC computation unless the Strip Sync
bit is set. If vertical redundancy check (VRG) parity checking is selected, the parity bit itself is deleted from the character before it is presented to the buffer.

Transmit Data
System software loads information to be transmitted to the modem
into the transmit data and status register. This does not ordinarily include error detection or control character information. Loading of the
TOSR occurs in response to the Transmitter Buffer Empty Signal from
the USYNRT. The character length is of information to be transmitted
is established by the software when it loads the transmit character
length register (bits 13, 14, and 15 of the PCSCR). The default length of
eight is assigned when the transmit character length register equals
zero. The length of the characters presented to the TDSR should not
exceed the aSSigned character length. When the information in the
TOSR is transmitted, the TBEMTY signal is again asserted to request
another character. The setting of TBEMTY also causes a transmit interrupt request if Transmit Interrupt Enable is set.
Byte count- or character-oriented protocols.require the transmission
of synchronizing information normally referrd to as sync characters.
The sync characters can then be transmitted when Transmit Start of
Message (TDSR bit 8) is set. This happens in one of two ways depending on the state of the IDLE bit (PCSAR bit 11). When the IDLE bit is
cleared, the sync character is taken directly from the the common
sync register (PCSAR bits 7-0). The sync register would have been previously loaded by the software. If the IDLE bit is set, the sync charac554

DPV11·DA
ter must be loaded into the TOSR by the software when it is to be
transmitted. If multiple sync characters are to be transmitted, the
TOSR must be loaded with only the first one in the sequence. This
character will be transmitted untii data information is ioaded into the
TOSA. The TBEMTY signal is asserted at the end of each sync character but the TSOM signal allows it to be ignored without causing a data
late error. With byte-oriented protocols, the USYNRT automatically
generates control characters as initiated by the software and inserts
necessary information into the data stream to maintain transperency.
Interrupt Vectors
The OPV11-0A generates two vector addresses, one for receive data
and modem control and the other for transmit data.
The receive and modem control interrupt has priority over the transmit
interrupt and is enabled by seeting bit 6 (RXITEN) of the receiver control and status register (RXCSR).
If bit 6 of the RXCSR is set, a receiver interrupt may occur when any
one of the following signals is asserted.
• Receive Data Ready (ROATRy)
• Receive Status Ready (RSTARY)
• Data Set Change (OAT SET CH)
The signal OAT SET CH causes an interrupt if bit 5 (OSITEN) of the
RXCSR is also set. It is possible that a data set change interrupt could
be pending while a receiver interrupt is being serviced, or the opposite
could be true. In either case, the hardware ensures that both interrupt
requests are recognized.

NOTE
The modem status change circuit interprets any
pulse of two microseconds or greater duration as a
data set change. This ensures that all legitimate
transitions of modem status will be detected. How·
ever, on a poor line, noise may be defined as a data
set change. Software written for the DPV11· DA must
account for this possibility.
A transmitter interrupt request occurs if Transmit Interrupt Enable
(TXINTEN) is set when Transmit Buffer Empty (TBEMTY) becomes asserted.

555

RLV12
RLV12 DISK CONTROLLER
INTRODUCTION
The RLV12 disk controller interfaces RL02 and RL01 disk drives to any
quad-or hex-size backplane that uses 16-, 18-, or 22-bit LSI-11 bus. One
RLV12 controls up to four disk drives. The RLV12 consists of one
quad-size module, a BCBOM cable, a drive terminator, and drive identification hardware.

The RL01 and the RL02 are random-access, mass storage subsystems
that store data in fixed-length blocks on a preformatted disk cartridge.
Each RL01 can store 5.24 million bytes, and each RL02 can store 10.48
million bytes. The drives are 26.67 cm (10.5 in) high, self-cooling rackmountable units and come complete with a power supply. Option
RLV12-AK includes one RL01 drive, and option RLV22-AK includes one
RL02 drive.
The RLV12 transfers data to and from the LSI-11 bus using Direct
Memory Access (DMA) transactions. This allows data transfers to occur without processor intervention.
FEATURES
• Single quad-size module; needs no C-D connections

• Supports DMA data transfers in 16-, 18-, or 22-bit addressing
modes
• Software-compatible with RLV11 controller (16-, or 18-bit modes
only)
• Supports 22-bit addressing on an LSI-11 bus
• Controls from one to four RL01 and RL02 disk drives
• Memory parity error abort feature for use with memories that have
a parity option

SPECIFICATIONS
RLV12 Disk Controller

Identification

M8061

Size

Quad-height: 26.56 cm x 1.27
cm x 22.70 cm (10.45 in x 0.5 in
x 8.94 in)

Power requirements

+5Vdc±5% at5.0Aand +12
Vdc±5% atO.1 A

556

RLV12
Bus loads
ac
dc

3
1

Jl.AArossinn I'T"Innoc::
v
II'~' 11"'''-'1'''''

16-, 18-, or 22-blt (determined by
the user)

Max. config. for 22-bit address
mode

H9275-A or similar backplane
that supports 22-bit addressing,
with memory capable of 22-bit
addresses, such as the MSV11-L
or the MSV11-P.

Limitations

The RLV12 will not fit in the dualheight LSI-11 mini-series H9281
backplane.

Drives per controller

Up to four RL01 and RL02 drives
in any combination

LSI-11 addressable registers

8 (5 are used; 3 are not used)

r"\UUI

Addressing
Mode
16-bit
18-bit
22-bit

Base Device
Address
17440a
774400a
17774400a

Device interrupt vector

0OO160a, jumper-selectable

Data transfer rates

4.9lLs/word (avg) drive to controller, controller to memory

13.9lLs/word (peak) drive to controller

2.0lLs/word (peak) controller to
memory
Error detection capability

eycl ic redundancy check (CRG)
on data and headers. Memory
parity error abort for use with
memories that have parity checking.

Max. cable length (controller to
last drive)

30 m(100ft)

557

RLV12
Environment
Temperature, operating

5°C to 60°C (41°F to 140°F)

Temperature, storage

- 40°C to 66°C ( - 40°F to
1SO°F)

Relative humidity, operating and
storage

10% to 95% noncondensing

RL01/RL02 Disk Drives
Medium

Magnetic disk cartridge

Recording surfaces

2 data surfaces

Magnetic heads

2 read/write heads

Recording Capacity (fonnatted)

Cylinders per cartridge
Tracks per cylinder
Tracks per cartridge
Sectors perJrack
Bytes per sector
Bytes per track
Bytes per cylinder
Bytes per cartridge
Recording method

Perfonnance
Transfer rate

RL01
RL02
256
512
2
2
512
1024
40
40
256
256
10,240
10,240
20,480
20,480
5.24 M
10.48 M
Modified frequency modulation
40-sector (16-bit data words):
4.9ILs/word (avg) drive to control·
ler, controller to memory; 3.9ILs/
word (peak) drive to controller

Head positioning time

55 ms (avg); 17 ms (one track);
100 ms (max)

Revolution latency

12.5 ms (avg)

Operating Environment
Temperature range

10°C to 40°C (SOoF to 114°F)at
sea level

Relative humidity

10% to 90%, noncondensing

Wet-bulb temperature

28°C (82°F) max

558

RLV12
Altitude

Up to 2400 m (8000 ft) at max
temperature of 36°C (96°F)

Heat dissipation

150 W (546 btu/hr)

Power
Drive

Single-phase

Starting current
5 A (rms) max, 120 V, 47/63 Hz;
2.5 A (rms) max, 240 V, Hz

Mechanical drive
Size

48 cm x 63.4 cm x 27 cm (19 in
x 25 in x 10.5 in)

Weight

33.75 kg (75 Ib)

Mounting

The drive mounts on slides in a
standard 48.26 cm (19 in) cabinet
(provided). Recommended max
height from floor is 18.9 cm (48
in).

Cartridge

Embedded servo. Top loading
cartridge with two data surfaces.

Standard length cables
Power cord

2.74 m (9ft)

Controller to first drive

1.83 m (6 tt)

Drive-to-drive

3.05 m (10 tt)

Optional drive cables

Cable

Part No.

Length

BC20J-20 7012122-206 m (20 ft)
BC20J-40 7012122-4012 m (40 tt)
BC20J-00 7012122-60 18 m (60 tt)

NOTE
Total length of the cable(s) from controller to the last
drive must not exceed 30 m (100 It).

559

RLV12
Device Address Selection
Software control of the RLV12 is performed by four or five device registers: CSR, BAR, DAR, MPR, and BAE. Four registers are used for 16- or
18-bit addressing; five registers are used for 22-bit addressing. The
bus address extension register (BAE) is added for upper address but
selection for 22-bit addressing. The usual device starting address is as
follows:
Starting Address (Octal)
Addressing Modes
16-bit

174400

18-bit

774400*

22-bit

17774400

* Factory configuration

NOTE
For 22·bit addressing, bit A3 is not decoded in the
starting address.

The first register, the CSR, is assigned to the starting address, and the
other registers are assigned to the next sequential address, as shown
in Table 1.
The device starting address is selected by jumpers for bits 3-12. These
jumpers are shown in Figure 1. A jumper from the selected bit to
ground (M22) decodes a 1; no jumper decodes a 0; and a jumper to 5 V
(M11) decodes an X (don't care) condition. Figure 2 shows the RLV12
device starti ng address format.
Bus Selection
The RLV12 module can be used on 16-, 18-, or 22-bit LSI-11 buses.
When sent from the factory, the module operates on a 16-, 18-bit
buses. To enable the module to operate on a 22-bit bus, install jumper
M1 to M2, shown in Figure 1. When installed, the jumper enables bank
select 7 (BBS?) to be determined by the upper address bits (13-21).
When the jumper is removedthe RLV12 has an 18-bit mode bank select
7 and can replace an existing RLV11 or RLV21 as the disk controller
for RL01 and RL02 disk drives.
Interrupt Vector
The interrupt vector has a range of 0 to 774. The interrupt vector is
preset at the factory to 160. The user may select another vector by
560

RLV12
changing the jumpers for bits V2-V8, as illustrated in Figure 3. A connection to VEC to BUS H (M3, shown in Figure 1) generates a 1 for that
bit; no connection generates a O.
interrupt Request Levei
The RLV12 interrupts a priority level 4 determined by the interrupt chip
E23, a DCOO3.

Table 1

Address Selection
18-Bit
Addressing*

22-Bit
Addressing

Device
Address

16-Bit
Addressing

Starting
Address
Range

160000-177770 760000-777770 17760000-17777760

Starting
Address

174400

774400

17774400

No. of
4
Registers

8 (5 are used;
3 are not)

Registers CSR (1 74400)
BAR (174402)
Used
DAR (174404)
MPR (174406)

CSR (774400)
BAR (774402)
DAR (774404)
MPR (774406)

CSR (17774400)
BAR (17774402)
DAR (17774404)
MPR (17774406)
BAE (17774410)

Tie M22 ("1 ")
to M17, M20,
and M21

Tie M22 ("1")
to M17, M20,
and M21

Tie M22 ("1 ")
to M17, M20,
and M21;
Tie M11 ("X") to M12

0-774

160

Tie M3 ("1")
to M6, M7,
andM8

Jumpers
Used

Interrupt
Vector

Vector
Range

Standard 160
Vector
Jumpers
Used

Tie M3 ("1")
to M6, M7,
andM8

*Factory Configuration

561

RLV12
II

ENABLE CRYSTAL

......-M29
:J-M28
ENABLE
VCOCLK
M27 M26

\.1

MEMORY PARITY ERROR
ABORT SELECTION
!J M23
{ M24 SEE NOTE
M25

•

TEST POINT
M30
W3

-=- DEVICE

NOTE:
THE MEMORY PARITY ERROR ABORT
FEATURE IS AVAILABLE FOR USE
WITH MEMORIES THAT HAVE PARITY
ERROR CHECKING.
THIS FEATURE DOES NOT HAVE TO
BE DISABLED FOR MEMORIES THAT
DO NOT HAVE PARITY ERROR
CHECKING. THE PINS ARE
CONNECTED AS FOLLOWS:
CONNECTION

FUNCTION

M23 - M24
M24 - M25

NO PARITY
PARITY ERROR ABORT

~~~_: ~~~

.·:
i

M1D MS M8 M7 M6 M5 M4 M3
,V8 V7 V6 V5 V4 V3 V2 VEf TO BUS H

AS
M18
M1S-A1D
M20 - All

E23

Ml
M2
ENABLE
22-BIT ADDRESSING

RLV12 Jumper Locations

~------~----~Il
BANK SELECT 7 FDR

,M21

22·BIT ADDRESSING
(CONNECT Ml TO M2)

:::!M!B

"'PASS CD PRIORITIES
(CDMG, CIAK)

FOR 18-BIT
ADD RESSI NG

CSR
BAR
DAR
MPR
BAE

~~~: ~~

ADDRESS M17 _A8
PINS

Figure

FACTORY
CONFIGURATION

Mll - +5V
M12-A3
M13-A4
M14-A5

OlD

1 1 ! !

M20

M19

M18

M17

1
M16

r I I r.

M15

M14

M13

M12

BUS ADDRESS PINS
CONNECT TO GROUND (PIN M22) TO DECODE A LOGICAL ONE. CONNECT
TO +5V (PIN Mll) FOR A DON'T CARE (X) CONDITION. NO CONNECTION
DECODES A LOGICAL ZERO.

7744()()
774402
774404
774406
774410

Figure

RLV12 Device Address Format
562

RLV12

INTERRUPT VECTOR PINS
CONNECT TO PIN M3 TO DECODE A LOGICAL ONE.
NO CONNECTION DECODES A LOGICAL ZERO.
MA-S750

Figure

RLV12 Interrupt Vector Format

Memory Parity Error Abort Feature
When reading the system's optional memory with parity error detection, a parity error will set OPI and NXM of the CSA. This is a unique
error condition that aborts the current command to the RLV12. This
error abort feature is possible only with memories that have parity
data bits.
The RLV12 is sent from the factory with the memory parity error abort
feature enabled. To disable the parity error abort, remove the jumper
between pins M24 and M25 and install a jumper between pins M23 and
M24. (See Figure 1.) This feature does not have to be disabled for nonparity memories, as parity errors are not generated. Parity error abort
uses data bits 16 and 17.

Jumpers That Remain Installed
The module has two jumpers, W1 and W2, that enable priority signals
to pass through the module. The module has these jumpers installed,
and they should be left in.
Signal
Jumper
W1

CIAKI to CIAKO

CDMGI to CDMGO

One jumper, the W3, enables the word count register to automatically
increment during a DMA operation. This jumper is used for factory
testing and should be left in.
563

RLV12
Two jumpers on the module disable the crystal oscillator and the voltage-controlled oscillator (VCO) during factory testing. These jumpers
should be left in.
Oscillator
Jumper
M26-M27

VCO

M28-M29

Crystal

INSTALLATION
The RLV12 can be installed in any quad LSI-11 bus slot. The controller's priority level is based on its electrical distance from the processor module. Use the following procedure to install the module.
1. Examine the module to make sure that the base address jumpers
and vector address jumpers are set correctly.
2. Check jumpers M1 and M2 for enabling the correct bank select 7
(BBS?) for the 18- or 22-bit LSI-11 bus.
3. If desired, disable the memory parity error abort feature. This
feature can only be used with system memories that have parity
options, but this feature does not have to be disabled for non-parity memories.
4. Insert the BC80M controller cable (or equivalent) into J1 on the
M8061 as shown in Figure 4.
5. Insert the M8061 in the selected slot in the LSI-11 bus.
6. Attach the ground strap on the cable to the metal cabinet
chassis.
7. Connect the other end to the BC80M cable to the back of the
first disk drive.
8. Continue with the disk installation. Refer to the RL01/RL02 Disk
Subsystem User Guide (EK-RL012-UG).

Acceptance Testing
The RLV12 controlleris tested by running the RLV12 diskless diagnostic test, and, if a drive is attached, by running the diagnostics that exercise the RL01 and RL02 disk drive. The diskless diagnostic should
be run first. The RLV12 diagnostics are available on different media.
Contact your local DIGITAL sales office for the types of media available and their part numbers.

564

RLV12
Run the XXDP + diagnostics in the following order:
1.

CVRLB RLV12 Diskless Diagnostic (16-,18-, or 22-bit mode)

NOTE
When the RLV12 is configured for 16- or 18-bit addressing, the RLV11 diskless diagnostic (CVRLA) is
compatable with the RLV12 diskless diagnostic and
checks the same logic.

2.
3.

CZRLG Controller Test, Part 1
CZRLG Controller Test, Part 1

4.
5.
6.
7.
8.

CZRLH Controller Test, Part 2

CZRLI Drive Test, Part 1
CZRLJ Drive Test, Part 2
CZRLN Drive Test, Part 3
CZRLK Performance Exerciser
CZRLL Compatibility Test

10. CZRLM Bad Sector File Utility

NOTE
The bad sector file Utility is not a diagnostic test. It
is used by field service to examine the bad sector
file on the disk and to write entries into that file.

565

RLV12

ATTACH TO
FIRST DISK
DRIVE

M8061

LSI-ll
BACKPLANE

MA·5898

Figure

RLV121nstallation

566

APPENDIX A

ASSIGNMENT OF ADDRESSES
AND VECTORS
ADDRESS MAP

2K
WORDS

FIXED ADDRESS AREA
RESERVED FOR USE BY
DIGITAL EQUIPMENT
CORPORATION

777 777

770 000

767777

WORDS

USER ADDRESSES AREA

764 000

763777

WORDS

FLOATING ADDRESSES AREA

760 010
760 006

RESERVED FOR USE BY
DIGITAL EQUIP CORP

760 000
757777

001 000

000 777

VECTORS

FLOATING VECTOR AREA

000300

TRAP & INTERRUPT
VECTOR AREA

000 277

VECTORS

000 000
MR-1545

FLOATING VECTORS
The conventions for the assignments of floating vectors for modules
on the LSI-11 bus will adhere to those established for UNIBUS devices. UNIBUS devices are used to explain the priority ranking for
floating vectors and are included in the subsequent table of trap and
interrupt vectors as a guide to the user.

The floating vector convention used for communications and for devices that interface with the PDP-11 series of products assigns vectors
sequentially starting at 300 and proceeding upward to 777. (Some LSI11 bus modules, such as the DLV11 and DRV11, have an upper vector
limit of 377). The following table shows the sequence for assigning
vectors to modules. It can be seen that the first vector address, 300, is
567

APPENDIX A
assigned to the first DLV11 in the system. If another DLV11 is used, it
would then be assigned vector address 310, etc. When the vector
addresses have been assigned to all the DLV11s (up to a maximum of
32), addresses are then assigned consecutively to each unit of the next
highest ranked device (DRV11 or DLV11-E, etc.), then to the other
devices according to their rank.
Ranking for Floating Vectors
(Start at 300 and proceed upward.)
LSI-11 Bus

Rank

UNIBUS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

DC11
KL 11, DL 11-A, -B
DP11
DM11-A
DN11
DM11-BB
DR11-A
DR11-C
PA611 Reader
PA611 Punch
DT11
DX11
DL 11-C, -D,-E
DJ11
DH11
GT40
LPS11
DQ11
KW11-W
DU11

DLV11, -F,-J

DRV11-B
DRV11

DLV11-E

KWV11-A,C
DUV11

INTERRUPT AND TRAP VECTORS
Vector

UNIBUS

LSI-11 Bus

000
004

DEC reserved
CPU errors

DEC reserved
Bus time-out and illegal instructions (e.g., JMP RO)
(odd address and stack
overflow traps not
568

APPENDIX A
INTERRUPT AND TRAP VECTORS (Cont)
Vector

010
014
020
024
030
034
040
044
050
054
060
064
070
074
100
104
110
114
120
124
130
134
140
144
150
154
160
164
170
174
200
204

LSI-11 Bus

UNIBUS

implemented on LSI-11)
Illegal and reserved
instructions
BPT instruction and T bit
lOT instruction
Power-fail
EMT instruction
TRAP instruction

Illegal and reserved
instructions
BPT, breakpoint trap
lOT, input/output trap
Power-fail
EMT, emulator trap
TRAP instruction
System software
System software
System software
System software
Console terminal,
Console terminal, input
keyboard/reader
Console terminal,
Console terminal, output
printer/punch
PC11, paper tape reader
PC11, paper tape punch
KW11-L, line clock
External event line interrupt
KW11-P, programmable clock
Memory system errors
XY plotter
DR11-B DMA interface;
(DA11-B)
AD01, A/D subsystem
AFC11, analog subsystem
AA 11, display
AA 11, light pen

RL 11

DRV11-B

RLV11

User reserved
User reserved
LAV11, LPV11
LP11 /LS11, line printer;
LA180
RS04/RF11, fixed head disk
569

APPENDIX A
INTERRUPT AND TRAP VECTORS (Cont)
LSI-11 Bus

Vector

210
214
220
224

RKV11

230
234
240
244
250
254
260
264
270
274
300

FIS (optional)

RXV1l RXVL1

User reserved

374
400
404
410
414
420
424
430
434
440
444
450

}

ADV11-A,C

}

IBV11-A

}

KWV11-A,C

User reserved
777

(End of floating vectors)
570

APPENDIX A
FLOATING ADDRESSES
The conventions for the assignment of floating addresses for modules
on the LSI-11 bus are the same as UNIBUS devices. UNIBUS devices
are used to explain the ranking sequence.

The floating address convention used for communications and for
other devices that interface with the PDP-11 series of products assigns
addresses sequentially starting at 760010 (or 160010) and proceeds
upward to 763 776 (or 163776). For compatiblity with UNIBUS convention, addresses are expressed as consisting of 18 bits (7XX XXX) rather than 16 bits (1 XX XXX).
Floating addresses are assigned in the following sequence:

Rank

1
2
3
4

5
6
7
8
9
10

LSI-11
Device

UNIBUS
Device

DJ11
DH11
D011
DU11
DUP11
LK11A
DMC11
DZ11
KMC11
RL 11 (extras)

DUV11

DZV11
RLV11 (extras)

DEVICE ADDRESSES
LSI-11 Bus

Address

UNIBUS

777776
777774
777772
777770

Processor status word (PS)
Stack limit
Program interrupt request (PIRO)

777720

J
I

DIGITAL reserved

571

APPENDIX A
DEVICE ADDRESSES (Cont.)
LSI-11 Bus

UNIBUS

Address
777716

CPU Registers
777710
777707
777706
777705
777704
777703
777702
777701
777700
777676

777600
777576
777574
777572
777570
777566
777564
777562
777560

R7 (PC) '"
R6 (SP)
R5
R4
~
R3
R2
R1
RO

~
IJ
}

Memory management

(SR2)
Memory mgt status register (SR1)
(SRO)
Console switch and display register

~~~~:~}

(RBUF)
(RCSR)

777556
777554
777552
777550
777546

}

777544

'",

General
Registers

Console
Terminal

Console
Terminal
DLV11-A,C

PC11/PR11
KW11-L, DL 11-W

XY11
777530
777526

}

Unassigned
572

(LTC) KPV11
BDV11

APPENDIX A
DEVICE ADDRESSES (Cont.)
Address
777524
777522
777520
777516
777514
777512
777510
777506

I}
}

UNIBUS

LSI-11 Bus

Unassigned

BDV11

LA180, LP11
LS11, LV11

}

LAV11, LPV11

TA11
777500
777476
RF11
777460
777456
RC11
777440
777436
777434
777432
777430
777426
777424
777422
777420
777416

DT07, bus switch

#8
#7
#6
#5
#4
#3
#2
#1

RKV11

RK11
777400

573

APPENDIX A
DEVICE ADDRESSES (Cont.)
LSI-11 Bus

UNIBUS

Address
777376

DC14-D
777360
777356
TC11
777340
777336
KE11-A, EAE #2
777320
777316
777314
777312
777310
777306
777304
777302
777300
777276

KE11-A, EAE #1

arithmetic shift
logical shift
normalize
step count/status register
multiply
multiplier quotient
accumulator
divide

DIGITAL reserved
777200
777176
777174
777172
777170
777166
777164
777162
777160

}
}

CR11,CM11,
CD11

574

RXV11
RXV11,RXV21

APPENDIX A
DEVICE ADDRESSES (Cont.)
Address

LSI-11 Bus

UNIBUS

777156
DIGIT AL reserved
777000
776776
AD01
776770
776766
AA11 #1
776750
776746
Unassigned
776740
776736
RP11
776700
776676
DL 11-A,-B
#4-#16
177530
177526
177524
177522
177520
177516
177514
177512
177510

}

DL 11-A,-B, #3

}

DL 11-A,-B #2

This area
reserved for 16
serial line units
without modem
c:ontrol capability
DLV11-A, -8, -F, -J

575

•

APPENDIX A
DEVICE ADDRESSES (Cont.)
LSI-11 Bus

UNIBUS

Address

177506
177504
177502 }OL 11-A,-B, #1
177500

- - - - - - --- - - -"

776476

#5
AA11

776400
776376

DX11
776200
776176
#6-#31
775660
775656
775654
775652
775650

}

775646
775644
775642
775640

}

775636
775634
775632
775630

}

775626
776624
775622
775620

}

#4
DL 11-C,-D,-E

This area
reserved for 31
serial line units
with modem
control capability

DLV11-E

576

APPENDIX A
DEVICE ADDRESSES (Cont.)
Address t

LSI-11 Bus

UNIBUS

I
775606
775604
775602
775600

}

776576

}

DIGITAL reserved
#4
D811

775400
775376

#1
#16
DN11

775200
775176

#1
#15
DM11

775000
774776

#1
#1
DP11

774416

RLV12

774410
774406
774404
774402
774400
774376

}

DP11
RL01
#32
#32
DC11

774000

#1
577

APPENDIX A
DEVICE ADDRESSES (Cont.)
Address

lSI-11 Bus

UNIBUS

773776
Maintenance loader
773700
773676

M792 diode ROM
773400
773376
BM792-YH cassette
773300
773276
BM792-YC card
773200
MR11-DB
773176
BM792-YB disk/DECtape
773100

REV11, BDV11
MRV11-AA
256-word ROM
space

- ----------

773076
BM792-YA paper tape
773000

- ---------

578

-- ---

APPENDIXA
DEVICE ADDRESSES (Cont.)
LSI-11 Bus

UNIBUS

Address

772776 I",
).

PA611 typeset punch

772700 )
772676

772600
772576
772574
772572
772570
772566

772560
772556

PA611 typeset reader

}
l

772550
772546
772544
772542
772540
772536
772534
772532
772530
~
772526
772524
772522
772520 .J

}

AFC11

DIGITAL reserved

KW11-P

TM11

579

APPENDIXA
DEVICE ADDRESSES (Cont.)
Address

LSI-11 Bus

UNIBUS

772516 I
772514

Memory mgt status register (SR3)

OST
772500
772456
DR11-B, #3
772450
772446
TJU16
772440
772436
772434
772432
772430
772426
772424
772422
772420
772416
772414
772412
772410
772406

}
}
}

DR11-B, #2

DIGIT AL reserved

DR11-B,-C, #1

KW11-W
772400
772376
Memory management
772200
'580

}

DRV11-B, #3

}

DRV11-B, #2

}

DRV11-B, #1

APPENDIX A
DEVICE ADDRESSES (Cont.)
Address

LSI-11 Bus

UNIBUS

772176
FP11
772160
772156
Unassigned
772140
772136
Memory parity
772110
772106
Unassigned
772102
772100
772076

MS11-K, -LP, MM11-LP

RL 11
772070
772066
RJS04
772040
772036
DIGITAL reserved
772020

581

APPENDIX A
DEVICE ADDRESSES (Cont.)
Address

UNIBUS

LSI-11 Bus

772016
GT40, VT48
772000
771 776
UDC functional 1/0 modules
771 000
770776

#8
KG11
#1
#16

770700
770676
DM11-BB

770500
770476
ADF11
770460
770456
Unassigned
770450
770446
770444
770442
770440
770436

}

LPS11

582

AAV11-A ,C

APPENDIX A
DEVICE ADDRESSES (Cont.)
Address

LSI-11 Bus

UNIBUS

LPS11
770424
770422
770420
770416

}

KWV11-A,C

}

ADV11-A,C

AR11, LPS11
770404
770402
770400
770376
DIGITAL reserved
770000
767776 }
767774
767772
767770

DR11-C, #1

767766
767764
767762
767760

}
DR11-C, #2

}

DRV11,#2

767756
767754
767752
767750
767746

}
DR11-C, #3

}

DRV11, #3

DRV11, #1

User
Reserved
Area
776000

583

User
Reserved
Area

APPENDIX A
DEVICE ADDRESSES (Cont.)
Address

LSI-11 Bus

UNIBUS

765776
REV11256-word
ROM space
765000
764776

764000

(start here and assign upwards to 767 776)

- - - - - -

- -1- - - -

- - - - --

763776

(tOPff floating addresses)

760154
760152
760150
760146

Floating
Addresses

760010

(start here and assign upwards to 763 776)

}

IBV11-A
Floating
Addresses

760006
DIGITAL reserved

DIGITAL
reserved

760000

584

APPENDIX B
ASYNCHRONOUS SERIAL LINE UNIT
(SLU) COMPARISONS
The characteristics listed in Tab!es 1, 2, and 3 compare the
different members of the DLV11 (LSI-11 bus) and DL 11 (UNIBUS)
families of asynchronous serial line products. All modules of the
DLV11 series are dual-height modules. The DLV11-E, -F, and -J modules detect overrun conditions which are reported in the receiver CSA.
These modules will not generate phantom interrupts on overrun.
DLV11-J
Each of the four serial ports on this module are separate and independent from the others. This is not a multiplexed module. Each port has
its own CSRs, data buffers, interrupt vectors, baud rates, UARTs, etc.
The net effect of this module is to achieve a 4:1 compression ratio over
the DL V11. The main functional difference between the ports of the
DL V11-J and the DLV11 is that the DL V11-J provides an RS-232Ccompatible interface (using RS-422 and RS-423) only and requires the
DLV11-KA module (one per port) to accommodate the 110 baud, 20
mA current loop interface.
DLV11-E
This module is functionally equivalent to the DL 11-E except that it has
programmable baud rates. This module provides one serial port that
has full modem control.
DLV11-F
This module is functionally equivalent to the DL 11-F except that it has
programmable baud rates. This module will eventually replace the
DLV11.
DZV11-8
The DZV11-B is a multiplexer interface between four asynchronous
serial data communication channels and the LSI-11 bus. The DZV11-B
provides EIA level conversion and full modem control suitable for
support of Bell series 103, 202, or equivalent modems. Program compatibility is maintained with the UNIBUS option, DZ11-A. The only
compatibility exception is the number of serial channels supported. As
a product enhancement feature, additional modem control leads are
supported to allow half-duplex operation on switched-network-type
lines.
MXV11-A
This multifunction module consists of two serial. ports, RAM and ROM
memory, and a 60 Hz clock. The two serial ports are RS-423 (RS-232C-c_ompatible, data leads only) The MXV11-A has two completely separate serial ports, where each port has its own CSRs, data buffers,
baud rate generation, etc.

585

Table 1

Comparison of Hardware Features
LSI-11 bus

Unibus
c(

,....
,....
I

,....

...J

,....
,....

,....
,....
I

...J

,....
,....
>
...J

...J

EIA RS-232C
Full modem control
Limited modem interface

(J)

,....

c
,....
,....

...J

No. of ports per module

u.
,....

,....
>
...J

,....
,....
>
...J
I

,....
,....
>
><
I

,....
,....
>
...J

:E
2

X
X

»
"'0
"'0

X
X
X

X
X

t Optional feature.
:j: Applies only to the port assigned to the console Device.

§ The loop-back cable is required to implement this function.

** RS-423 only

* The external 20 mA option (DLV11-KB) is required to implement this function.

I 110 baud only.

,....
,....
>
N
c

,....
,....
>
...J

EIA RS-423, RS-422
Data leads only
20 rnA current loop
RCVR active or passive
XMIT active or passive
XMIT active only

..,

X
X

*
*

X
X

C
X

LSI-11 bus

Unibus

,...
,...•

..J

CCITT

,...•

,...

..J

,...
,...

..J

,...
,...
C

•
,...
,...
C

,...
,...
I

>
..J
C

u.I

,...
,...
>
..J
C

.,
,...
,...
I

>
..J
C

c(
~

>
N
c

,...
,...
>
..J
I

Boot on fram ing errort

>
)(

:aE

:j:

.......

"tJ
"tJ

><
C

Baud rates (Table 3)
Programmable
On-board clocks for split speed

Reader run control

Error flags

X
X

X
X
X

t Optional feature.
:j: Applies only to the port assigned to the console Device.
§ The loop-back cable is required to implement this function.

X
X
X

* The external 20 mA option (DLV11-KB) is required to implement this function.

I 110 baud only.

• ,...•
,...
,... '....

X
X

Halt on framing errort
(J1

,...
,...
>
..J

X
X
*
X

LSI·11 bus

Unibus

<CI

IIII

Q
I

-J
Q

Break generation bit

Receiver active bit

Maintenace bit

UART cleared by INIT

,...
,...

C1I

(XI
(XI

,...
,...

,...
,...
I

UART cleared by DCOK
No trap on write to input buffer

,...
,...

>
-J
Q

,...
,...
I

>
-J
Q

,...
,...
>
-J
I

:/: Applies only to the port assigned to the console Device.
§ The loop-back cable is required to implement this function.

,...
,...
I

>
-J
Q

X
X

..,

,...
,...
>
-J
I

IIII

<CI

>
N

,...
,...
>
><

,...
,...
Q

::E

."
."

• The external 20 mA option (DLV11-KB) is required to implement this function.
t Optional feature.

I 110 baud only.

u..

-><
C

LSI-11 bus

Unibus

.....•
.....

..J

.....•
.....

..J

.....•
.....

..J

.....•
.....

..J

.....•

.....

..J

.....
.....

ex>

.....•

.....•
.....
>
..J

..,•

.....
.....
>
..J

>
..J
C

~
~

.....•
.....

>
..J
C

>
N
c

>
><

•
.....
.....

.....•

.....

:!
X

»
"tJ
"tJ

Stop bits
1

1.5
2

X
X

X
X
X

• The external 20 mA option (DLV11-KB) is required to implement this function.

t Optional feature.
:I: Applies only to the port assigned to the console Device.
§ The loop-back cable is required to implement this function.

I 110 baud only.

.....
>
..J

Easy configuration using wire-wrap
jumpers
(J1

X
X

X
X
X

X
X

-><C

Table 2

Baud Rates

Unibus

•

m
,...•

•

...I

>
...I

...I

X
X
X

X
X
X
X

X
X
X
X
X
X
X
X
X
X

X
X
X

oct

Baud
Rate

50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38,400

<0
0

External
*

,...
,...

c
•
,...
,...

,...
,...

,...

,...
,...

w
,...•

,...

,...•

LSI-11 bus
oct

u..
,...•

,...

..,•

,...
,...
>
...I

,...
>
...I

>
...I

X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X

X
X
X

The external 20 mA option (OLV11-KB) is required to implement this function.

,...•
,...
>
...I

m
,...•

,...
>
N
c

X
X
X
X
X

X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X

oct
,...•

,...

>
><

."
."

Z
C

X
X
X
X
X

Table 3

Comparison of Software Features
Unibus

<t:

,..
,..
I

...J

Bit

Name

RCSR

Data Set Status/
Interrupt

14
13
12
11
10
9,8,4

(]1

co
......

7
6
5
3
2
1
0
*

Ring
CTS
CD
Receiver Active
2d Receive
Unused
Receive Done
Receive Int Enb
Data Set Int Enb
2dXMT
RTS
PTR
Rdr Enable

,..
,..

...J

,..
,..
C

LSI-11 bus

,..
,..

II'"'
II'"'

,..
,..

...J

>
...J

,..
,..
I

>
...J
C

,..
,..
>
...J
I

<t:

,.,.-

,..
,..

>
_J

>
><

X
X
X

The external 20 mA option (DLV11-KB) is required to implement this funtion.

»
"tJ

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

X
X
X
X
X
X
X
X
X
X
X

"tJ

m
Z

X
X
X
X

-><m
C

)(

X
)(

X
X
X

LSI-11 bus

Unibus

m
I

'f""'
'f""'

...I

X
X

X
X
X
X
X
X

X
X
X
X
X

X
X
X
X
X
X

X
X

...I

XCSR

Error
OE
FE

12
11-8
7-0

PE
Unused
Receive Data

15-8
7
5-3,1
2
0

Unused
XMT Ready
XMT Int Enb
Unused
Maintenance
XMT Break

X
X
X
X
X

15-8
7-0

Unused
XMT BUF

X
X

15
14

XBUF

X
X

The external 20 rnA option (DLV11-KB) is required to implement this funtion.

..,

'f""'
'f""'

>
><

...I

>
c

...I

>
c

...I

X
X
X
X

X
X

X
X
X
X
X
X

X
X
X
X

X
X
X
X
X
X

X
X
X
X

X
X

X
X
X
X
X
X

X
X

>
c

...I

>
c

X
X
X

."
."

Z
C

-><
aJ

APPENDIXC

COMPARISON OF DATA
TRANSM!SS!ON TECHNIQUES
Frequently, the application arises where a data transmission path has
to be established between two devices. Usually the distance between
the device is known and also the rate of data transmission. The problem is deciding which is the best communication technique to use to
interconnect the devices.
Figure 1 is a graph of data versus distance for the various standard
transmission techniques. Parallel data transmission techniques (PLUs
and DMA) give the highest data rate; however, they are good only for
relatively short distances. The serial techniques (RS-232C, RS-422
and current loops) are good for longer distances but at limited data
rates.
While analyzing Figure 1, remember that the axes are logarithmic and
that the data in words per second rather than baud rate. The limits
established for distance and data rate are a function of both the inherent limitations of the transmission technique and of the DIGITAL device used to do the interconnection. As an example, look at the 422
section of the graph. Maximum distance is 4000 feet as established by
EIA standard RS-422, but the maximum data rate of 1920 words per
second is based on the maximum baud rate of the DL V11-J which
is 38.4K baud.
Table 1 is a summary of the LSI-11 bus and UNIBUS devices which
can be used with each communication technique. Currently, there is
no UNIBUS device for EIA RS-422.

593

APPENDIXC

lOOK

10K

EIA
RS-232C
WITH
MODEM

4K
1.5K

i=
u..

EIA
RS-422

u
z

«
fCJl

EIA
RS-423

120

CURRENT

100

LOOP

100
1920

__ 50

DMA (TRI-STATE)

EIA RS-232C

----

_ _ 15

10
ALL
TECHNIQUES

DMA

PLU

(TTL)

480
10

100

46K
10K

lOOK

500K
1M

DATA RATE (WORDS/S)
MR-1455

Figure 1

Data Rate vs Distance with DIGITAL Devices

Table 1

Loop
EIA (RS-232C)
EIA with Modem
RS422, RS423
PLU
DMA

Communication Techniques
LSI-11

UNIBUS

DLV11
DLV11
DLV11-E
DLV11-J
DRV11
DRV11-B

DL11-C
DL 11-D
DL 11-E
DR11-C
DR11-B

594

APPENDIXC
NOTES AND ASSUMPTIONS FOR FIGURE 1
1. Data Rate Definition

a.
b.

One word equals 16 bits.
For seriai techniques, one word equals two characters formatted with one start bit, eight data bits, and one stop bit.
Asynchronous serial transmission is assumed.
Serial Line Maximum Data Rate
a. Modems were limited to 120 words/sec (2400 baud) because
modems with higher rates. cost more than LSI-11 systems
usually warrant. Higher data rate modems are generally
synchronous rather than asynchronous.
b. 480 words/sec is equal to 9600 baud, the limit of the DLV11
SLU.
c. 1920 words/sec is equal to 38.4 baud, the limit of DLV11-J
SLU.
PLU (Parallel Line Unit) Limits
a. The TTL inputs/outputs of the DRV11 limit the distance to 15
feet.
b. 46K words/sec assumes non-interrupt-driven program servicing with bit testing (TSTB, BMI, MOV and SOB). 97K
words/sec is maximum rate with program servicing without
bit testing (MOV and BR). With interrupt-driven servicing, the
maximum limit is 20K words/sec assuming 50 J.Ls for interrupt
latency and software servicing of interrupt.
DMA (Direct Memory Access) Limits
a. The DRV11-B can be used up to 50 feet because it has tristate drivers and receivers. The distance is limited to 15 feet
with TTL devices like the DR11-B.
b. DMA transfer with the DRV11-B and the DR11-B are limited to
500K words/sec in burst mode operation; 250K words/sec is
the limit for single-cycle mode operation with either device.
These limits are device-dependent, not LSI-11 bus-dependent. Note that burst mode can disrupt memory refreshing if
bus refreshing (DMA and microcode) is used. Self-refreshing
memories (MSV11-CD or MSV11-D) eliminate this problem.

595

APPENDIX D

BUS RECEIVERS AND BUS DRIVERS

The equivalent circuits of LSI-11 bus-compatible drivers and receivers
are shown in Figure 1. To perform the receiver and driver functions.
Digital Equipment Corporation uses two monohthic integrated circuits
with the characteristics listed in Table 1. A typical bus driver circuit is
shown in Figure 2. Note that 8641 quad transceivers can be used.
combining LSI-11 bus receiver and driver functions in a single package.
Bus receiver (8640). bus driver (8881). and bus transceivers (8641) are
shown in Figures 3. 4. and 5. respectively.

OUT -

+34V

'Rl

IN -

R1 = 120K. MIN
R2 = 20K. MIN
Cl = 10pF MAX

-:R2

Figure 1

TRANSMITTER OFF ILOGICAL 01
A3 = 120K. MIN
C2 = 10pF.MAX
TRANSMITTER ON (LOGICAL 11
R3 = 11 OHMS. MAX
C2 = 10 pF. MAX
'VI~

1110

Bus Driver and Receiver Equivalent Circuits

+5V

TYPICAL

BUS DRIVER
11 - 3307

Figure 2

Typical Bus Driver Circuit

596

APPENDIX D
Vee

GND
CP-,27,

Figure 3
Vee
14

8640 Quad 2-lnput NOR Gates
(Bus Receiver)
13

GND
CP 1272

Figure 4

8881 Quad 2-lnput NAND Gate
(Bus Driver)
16

BUS 1

DATA IN 1
DATA OUT 1
BUS 2
DATA IN 2
DATA OUT 2

11
10

ENABLE A
GROUND

Vee
BUS 4
DATA IN 4
DATA OUT 4
BUS 3
DATA IN 3
DATA OUT 3
ENABLE B

ENABLE A
ENABLE B

Figure 5

8641 Quad Unified Bus Transceiver
(Bus Receiver/Driver)

597

APPENDIX 0
Table 1

Driver
(8881)
(8641 )

LSI-11 Bus Driver. Receiver. Transceiver
Characteristics

Characteristic

Sym

Specifications

Input high voltage
Input low voltage
Input current at 3.8 V
Input current at 0 V
Output high voltage
Output high current
Output low voltage
Output low current
Propagation delay to
high state
Propagation delay to
low state
Input high voltage
I nput low voltage
Input high current
Input low current
Output low voltage
70 rnA sink
Output high leakage
current at 3.5 V
Propagation delay to
low state
Propagation delay to
high state

VIH
VIL
IIH
IlL
VOH
VOH
VOL
10L
TPDH

VIH
VIL
IIH
IlL
VOL

1.7 V min
1.3 V max
80 f.J..A max
10 f.J..A max
2.4 V min
(16TIL loads)
0.4 V max
(16 TIL loads)
10 ns min
35 ns max
10 ns min
35 ns max
2.0V min
0.8 V max
60 f.J..A max
-2.0 mA max
0.8 V max

10H

25 f.J..A max

1.3

TPDL

25 ns max

1.5

TPDH

35 ns max

1.5

TPDL

1.5

6
6

NOTES
1. This is a critical parameter for use on the 110 bus.
All other parameters are shown for reference only.
2. This is equivalent to being capable of driving 16
unit loads of standard 7400 series TIL integrated
circuits.
3. Current flow is defined as positive if into the terminal.
4. Conditions of load are 390 n to +5 V and 1.6 kn
in parallel with 15 pF to ground for 10 ns min and
50 pF for 35 ns max.
5. Times are measured from 1.5 V level on input to
1.5 V level on output.
6. This is equivalent to 1.25 standard TIL unit loading of input.

Bus receivers and drivers should be well grounded and use VCC to
ground bypass capacitors. These gates should be located as close as
practical to the module fingers which plug into the backplane and all
etch runs to the bus should be kept as short as possible. Attention to
these cautions should yield a module design with minimum bus loading
(capacitance) .

598

APPENDIX E
CABLING SUMMARY

Preassembled cables are available in a variety of lengths and types as
listed in Table 1. The H854 and H856 connectors are shown in Figure 1.

H854
CONNECTOR

"856 CONNECTOR
(SHOWN WITH
CABLE INSTALL EO)

Figure 1

J 1 or J2 Connector Pin Locations

599

APPENDIX E

Function
Seriall/O-Asynchronous
20MA

Module Type

Cable Recommendations

DLV11-F 1-Line
DLV11-J 4-Line

BC05M-2C
DLV11-KA (1 per line)

EIA RS-232C
Data only
(DLV11-J is also
RS422/423)

DLV11-F 1-Line

BC01V-25 (M)

DLV11-J 4-Line
MXV11-A

BC21B-Q5 (M)
1 per line
or
BC20N-Q5 (T)

EIA RS-232C
with Modem Control

DLV11-E 1-Line
DZV11-B 4-Line MUX

BC01V-25 (M)
Cable included

DUV11-DA 1-Line

BC05C-25 (M)

SerialllO-Synchronous
EIA RS-232C
with Modem Control
Digital 1/0
Programmed Transfer

DRV1116 in/16 out
2ea

DMA Transfer
Analog 1/0
AID
D/A
Mass Storage
Tape Cartridge
Double Density Floppy
Diskette
Hard Disk
(H9273 Backplane Req'd)
Note: M-Connects to a Modem
U-User end unterminated

DRV11-B 16 in/16 out

BC07D-15(U)
or
BC08R-12(B)

ADV11-A 16 channel
AAV11-A 4 channel

BC07D-15(U)
BC08R-12 (B)

TU58-BB

BC20N-Q5 plus a
I
Serial Modem (M) cable'
Includes cable
Includes cable

RXV21-BA
RLV11-AK

T-Connects to an EIA Terminal
B-User end terminated with 40 pin Berg Connector

600

APPENDIX F
DIGITAL MICROCOMPUTER DOCUMEN~ATION
DiGiTAL oHers many microcomputei-ielated pioduct technical
guides, manuals, summaries, bulletins, handbooks, and brochures
that are very useful as supplementary material to this handbook. A
complete list of these support publications appears in alphanumeric
order according to the category specified below. To order a publication, call 800-258-1710 (between 8 am-5 pm EST), or mail your inquiry
to:
Digital Equipment Corporation
Accessories and Supplies Group
P.O. Box CS2008
Nashua, New Hampshire
03061
Technical Guides/User Manuals/Handbooks
CATALOG NO.

PUBLICATION

EK-AXV11-UG .

.AXV11-C, AAV11-C, ADV11-C User Guide

EK-BA11A-IP .

. . . . . BA11-A UnitAssembly IPB

EK-BA11A-TM.

.BA11-A Mounting Box & Power Tech

EK-BA11 F-IP .

· BA11-F Mounting Box IPB

EK-BA11K-IP .

· BA11-K Mounting Box IPB

EK-BA11 K-OP .

BA11-K Mounting Box User Manual

EK-BA11K-TM.

. BA11-K Mounting Box Tech Manual

EK-BA11L-IP .

· BA11-L Mounting Box IPB

EK-BA 11 L-TM .

· BA11-L Technical Manual

EK-BA11M-IP.

BA11-M Mounting Box IPB

EK-BA11N-IP .

.BA11-N Mounting Box IPB

601

APPENDIX F
CATALOG NO.

PUBLICATION

EK-BA 11 N-TM

BA11-N Mounting Box Configuration Guide

EK-BA 11 N-UG

. BA11-N Mounting Box User Manual

EK-BA11N-TM

. BA11-N Mounting Box Tech Manual

EK-BA11P-IP .

BA11-P Unit Assembly IPB

EK-BA11U-IP .

.BA11-U Mounting Box IPB

EK-BA11V-IP .

.BA11-V Box Assembly IPB

EK-BA 11 V-RG.

· BA11-VA Configuration Guide

EK-BA1KP-IN .

BA11-KP Installation Manual

EK-BAM11-TM

. . BAM11 Technical Manual

EK-BAM11-UG

BAM11 Status Alarm Monitor User Guide

EK-BDV11-TM.

BDV11 Technical Manual

EK-BDV11 N-TM .

BDV11 Technical Manual

EB-19187-75

. Cables Handbook

EK-01387-92

Chipkit User Guide

EK-DLV11 J-UG

. DLV11-J User Guide

EK-DLVKA-IN.

· DLV11-KA Installation Manual

EK-DLV11-0P .

· . . . DLV11-E/F User Manual

EK-DPV11-CG.

DPV11-DA Configuration Guide

EK-DPV11-UG.

. DPV-11 Synchronous Interface User Guide

EK-DPV11-TM .

. . . . . . . . . DPV-11 Technical Manual

602

APPENDIX F
CATALOG NO.

PUBLICATION

EK-DRV1B-OP

. DRV11-B Interface User Manual

EK-DRVIJ-UG.

. DRVI1-J Interface User Manuai

EK-DRV11-0P.

. DRV11-P Foundation Module User Manual

EK-DUV11-TM.

. DUV-11 Line Interface Technical Manual

EK-DUV11-0P.

. . . . . . . . . . DUV11 User Guide

EK-DZV11-TM.

DZV11 Asynch Multi Technical Manual

EK-DZV11-TM.

DZV11 Asynch Multi Technical Manual

EK-DZV11-UG.

. DZV11 Asynch Mtlpxr Guide & Addendum

EK-FPF11-TM .

. FPF11 Floating-Point Processor Technical Manual

EK-H927A-CG .

. H9275-A Configuration Guide

EK-IBV11-UG .

. . . . . IBV11-A User Manual

EK-KD1HA-CG

LSI-11/2 Processor Configuration Sheet

EK-KDF11-UG.

. . . . . . . . . KDF11-AA User Guide

EK-KDFAA-CG

.LSI-11/23 Processor Configuration Sheet

EK-KUV11-TM.

. LSI-11 WCS User Guide

EK-AXV11-UG.

. KWV11-C User Guide

EK-KXT11-UG.

. KXT11-AA User Guide

EK-KXT11-CG.

KXT11-AA Configuration Guide

EK-LA120-TM .

LA 120 Technical Manual

EK-LA120-UG.

. . LA120-RA User Guide

603

APPENDIX F
CATALOG NO.

PUBLICATION

EK-LSI11-MC .

. LSI-11 PDP-11/03 Maintenance Card

EK-LSI11-TM .

· LSI-11 PDP-11/03 User Manual

EK-LSI FS-SV .

-. LSI-11 System Service Manual

EK-MCV1 D-UG

· . . . . MCV11-D User Guide

EB-20912-20

. Microcomputer And Memories Handbook 1982

EB-20175-20

Microcomputer Interface Handbook 1981

EK-MSV1 D-OP

.MSV11-D/E User Manual

EK-MSVOL-UG

MSV11-L User Guide

EK-MSVOP-UG .

MSV11-P User Guide

EB-19402-20 .

PDP-11 Processor Handbook

EK-T03LO-OP.

· PDP-11IT03-L System Manual

EK-V03LO-OP.

· PDP-11IV03-L System Manual

EK-1V03L-IP

· PDP-11IV03-L Unit Assembly

EK-11V23-IP

PDP-11/V23 Unit Assembly I PB

EK-11V23-0P .

. PDP-111V23 System Manual

EK-PVVRPK-CL

. Power And Packing Catalog

EK-RL012-PG .

· RKL01/02 Pocket Service Guide

EK-RL012-TM .

· RL01/02 Disk Drive Tech Manual

EK-RL012-UG .

· . . . . . . RL01/02 User Guide

EK-RL012-WS.

RL01/02 P.M. Worksheet 25/P KG
604

APPENDIX F
CATALOG NO.

PUBLICATION

EK·RLTER-PS .

· RL01/02 Pocket Service Guide

EK-ORL01-IP .

. RL01 Disk Drive I PB

EK-ORL02-1 P .

. RL02 Disk Drive I PB

EK-RL012-TM .

· RL01/02 Disk Drive Tech Manual

EK-RLV11-TD .
EK-RLV12-UG.

RLV11 Controller Tech Desc. Manual
IPB
. . . RLV12 User Guide

EK-ORX01-IP .

. RX01 Floppy Disk I PB

EK-ORX01-MM

RX01/00/11 Maintenance Manual

EK-ORX02-IP .

· . . . . . RX02 Floppy Disk I PB

EK-ORX02-TM.

RX02 Floppy Disk Systems Technical Manual

EK-ORX02-UG.

. . . RX02 Floppy Disk System User Guide

EK-OSB11-DG.

. SB11 Series OEM Sys Design Users Guide

EK-OSB11-1 P .

· . . SB11 Microcomputer IPB

EK-TU58E-CG .

· TU58-EA Configuration Guide

EK-OTU58-EC .

TU58 DECtape Customer Equip Care

EK-OTU58-IP .

. . . . TU58 Cartridge Tape Drive Ipt

EK-OTU58-PS .

. TU58 DECtape II Pocket Service Guide

EK-OTU58-TM.

. TU58 DECtape-11 Technical Manual

EK-OTU58-UG.

· . TU58 DECtape-11 User Guide

EK-OTU58-WS

TU58 DECtape Installation Sheet
605

APPENDIX F
CATALOG NO.

PUBLICATION

EK-VT1 OO-UG .

. VT100 User Guide

ED-VT103-CG .

. VT103 Configuration Guide

EK-VT103-UG .

VT103 LSI-11 User Guide And Addendum

EK-VT103-IP .

. . . . . . . . VT103 Unit Assembly IPB

EK-VT1X3-CG. VT1X3-MM Maintenance Module Configuration Sheet
EK-VT125-UG . . . . . . . . . . . . . . . . . . . VT125 User Guide

Option Bulletins/Postcards/Miscellaneous
EJ-21725-53 .

.AAV11-C Analog 1/0 Board Postcard

EJ-21724-53 .

. ADV11-C Analog 1/0 Board Postcard

EJ-21726-53 .

. AXV11-C Analog I/O Board Postcard

ED-21 049-53

.AAV11-C, ADV11-C, AXV11-C Option Bulletin

ED-18321-53

. . Asynchronous Interface LSI-11 (DLV11-E)

AA-K724A-TC .

.Basic-11/RT-11 Installation Guide & Release Notes

ED-09371-53

· . . . . Battery Backup-LSI-11 Eng. Note

EA-19971-18

· Coming To Terms With IBM & Networking

GA-18195-75

· . Computer Maintenance Alternative Use

ED-06703-92

. DDV11-B 9X6 Slot LSI-11 Backplane Bulletin

EJ-19822-53 .

. DPV11-DA Synch ronous Li ne Interface

ED-20086-53

. . . DPV11-DA Option Bulletin
606

APPENDIX F
CATALOG NO.

PUBLICATION

ED-18511-53

. . . . . . . . . . . . DRV11-J Option Bulletin

ED-18326-53

EPROM/P ROM/ROM Module LSI-11 (MRV11-C)

ED-17472-53

EPROM/P ROM/ROM Module March 79

ED-18322-53

Four-Channel LSI-11 Micro (DLV11-J)

EA-20360-53

· . . . . . . H9275-A Option Bulletin

ED-18762-53

. High Density Parallel Interface DRV11-J

ED-07494-53

· IBV11-A Interface Option For LSI-11

ED-18328-53

· IEEE Interface OPT LSI-11 (IBV11-A)

EJ-21 048-53 .

.KWV11-C Programmable RealTime Clock Postcard

EJ-21347-53 .

KXT11-AA (SBC-11/21) Processor Board Postcard

ED-21608-20

. KXT11-AA Option Bulletin

ED-21394-53

. KWV11-C Option Bulletin

ED-18967-18

LA38 DECwriter II Terminal

ED-18966-18

LA120 DECwriter III Data Sheet

ED-19211-56

LA120-RA DECprinter III Bulletin 4/80

ED-08193-18

· LA180 DECprinter Data Sheet 06/78

ED-17474-53

LSI-11 Mounting Chassis/P Ower March 79

ED-18327-53

. . . LSI-11 Multifunction ModulE (MXV11)

ED-18324-53

LSI-11 Option Memory Module (MSV11-DD)

ED-18323-53

. LSI-11/2 Central Processor (KD11-HA)
607

APPENDIX F
CATALOG NO.

PUBLICATION

ED-18393-18

. . . . LSI-11/23 Data Sheet Oct 79

ED-18325-53

. LSI-11/23 High Performance (KDF11-AA)

EH-17898-20

LSI-11/23 (PDP-11/23) Reference Card

EA-17057-18

LSI-11/23 Microcomputer

ED-18393-53

LSI-11/23 Option Bulletin

EE-19213-53.

Micro Products Group Product Description

EJ-18382-53 .

· . Microcomputer Products Group U-note

EA-18334-53

· Microcomputer Products Selection Guide

EA-20065-53

· . . . Microcomputer Software Brochure

EJ-22088-53 .

. MCV11-D CMOS ReadlWrite Memory Postcard

ED-22045-53

MCV11-D Option Bulletin

ED-08012-53

MRV11-B Option Bulletin

ED-20881-53

MSV11-L Option Bulletin

ED-17470-53

MXV11 Multifunction Module March 79

EH-07043-53

. . PDP-11103, LSI-11 Reference Card

EA-19442-18

.RT-11 Single-User Realtime Systems

EJ-18922-28 .

. RT-11 Technical Summary

ED-20997-53

. .. RX02 Opt,ion Bulletin

AE-3438C-TC .

. SPD 9.2.2 Papertape Support Package

AE-J514A-TC .

. . . . . . . SPD 10.16.0 RT-11

608

APPENDIX F
CATALOG NO.

PUBLICATION

AE-D431F-TC .

. SPD 10.72.6 DECnet-RT

AE-3393M-TC.

.SPD 12.1.14 RT-11

AE-0007D-TC.

. . SPD 12.4.3 RT2

AE-3394H-TC .

SPD 12.5.8 BSC-11/RT-11

AE-3395L-TC .

. SPD 12.10.12 F IV/RT-11

AE-H257B-TC.

.SPD 12.14.1 Instrument Bus Sub

AE-3397F-TC .

. SPD 12.20.6 MU BSC-11/RT-11

AE-H585B-TC.

. SPD 12.21.1 PROM/RT-11

AE-H509C-TC.

.SPD 12.22.2 FMS-11/RT-11

AE-J673A-TC .

. SPD 12.29.0 Fortran/RT-11 Lab Extensions

AE-J698A-TC .

SPD 14.42.0 APL-11/RT

AE-D607C-TC .

. SPD 15.44.2 LSP-11

AE-3413E-TC .

. SPD 15.45.6 SSP-11

AE-D370C-TC .

SPD 15.90.2 LSI-11 Micro Tools

EA-18784-53

. The Story Behind LSI-11 Microcomputer

EA-19973-53

. . TU-58 Option Bulletin October 1980

ED-17473-53

. Universal Prom Programmer March 79

ED-19000-53

. VT103/L SI-11 Video Terminal April 1980

609

APPENDIX F
Brochures/Articles/Posters
CATALOG NO.

PUBLICATION

EJ-N0571-26

. LSI-11 Trio Calls The Tune Article

EJ-N0994-53

. Canadian Stock Exchange Article

EJ-N0995-53

. Manufacturing Memory Tester Article

EJ-NOOO2-53

It's An Inside Job Article

EJ-NOO17-53

. Digital Controls Article

EJ-N1198-53

. Low-cost 16-Bit Microcomputer Article

EJ-N1269-53

Airborne Data Acquisition System Article

EJ-NOO76-53

. If You Don't Have Millions In R&D Your
Microcomputer Should Ad Reprint

EJ-N0851-53

. . . .. We're Giving 8-BIT Micros A Run For Their
Money Ad Reprint

EJ-N0983-53

. We've Just Given Wyle The Business Ad Reprint

EJ-N1071-53

. We've Turned A Good Partnership Into A Great
Separation Ad Reprint

EJ-N1078-53 .. ,

. We've Designed Our Microcomputers For Your
Toughest Application Ad Reprint

EJ-N1093-53

. . . . We've Improved Our Memory Ad Reprint

EJ-N 1095-53

We've Just Given Pioneer The Business Ad Reprint

EJ-N1096-53

. . Digital's New 16-BIT Falcon Ad Reprint

EJ-N0888-53

Our Microcomputers Are Faster Ad Reprint

EJ-20855-53.

. . . . Mighty Micro Press Kit
610

APPENDIX F
CATALOG NO.

PUBLICATION

EJ-21875-53.

. Falcon Press Kit

EJ-21317-53.

.Mighty Micro Poster

EJ-22251-53.

. . . . Falcon Poster

EA-18097-18

Digital Family Of Terminals Brochure

EA-21333-18

. LSI-11 Family Brochure

EA-23312-18

MICRO/PDP-11 Brochure

EJ-22333-18.

. Microcomputer Products Chips-Systems-Supplies
Brochure

EA-21607-53

. . . . . . Micropower/Pascal Brochure

EA-18924-18

PDP-11 Microcomputer Members Brochure

EA-23755-18

. PDP-11 (Your Investment For The Future) Brochure

611

Index
AAV11-A four-channel, 12 bit digitalto-analog converter, 5, 29-36
AAV11-C analog output board,
37-44
address compare circuit,

addressing
by DRV11, 294-295
by REV11-A and REV11-C,

457

263

ADDRESS MATCH signal,

394

address space, I/O page in,

ADREN H signal,

186,194

ADV11-A analog-to-digital
converter, 5-6, 45-52
KWV11-A programmable realtime
clock for, 420
ADV11-C analog-to-digital
converter, 6, 53-69
AINIT H signal,

BA11-M expansion box,

13,88-94

BA11-N mounting box,

13,95-103

BA11-S expansion box,

13,104-112

BA11-VA mounting chassis/power
supply, 14,113-115
backplanes, 12-13
on BA11-M expansion box, 88
on BA11-N mounting box, 95-98
on BA11-S expansion box, 107109
DDV11-B, 205-210
H909-C general purpose logic
enclosure'for, 365
H9270, 366-371
H9273-A, 372-375
H9275-A, 376-382
H9276, 383-386
H9281 , 387-392
installation of DRV11 parallel Ii ne
unit on, 305

6-7,70-

BBS7 L bus signal,
BC05C cable,

5, 37-44

asynchronous line interfaces,
DLV11-E, 217-237
DLV11-F, 238-257
DLV11-J, 258-286
asynchronous multiplexer,
352-356
asynchronous receiver/
transmitter, 15, 144-161

baud rate control
on DLV11-E, 221,227
on DLV11-F, 241,247-248
on DLV11-J, 262,278-279
on DLV11-KA, 290-291

analog-to-digital converters
ADV11-A, 5-6,45-52
ADV11-C, 6, 53-69
87
analog output board,

AXV11-C analog input/output
board, 6-7, 70-87

bank 7 (I/O page),

300

analog input/output board,

324

263

addresses, 25
for DLV11 serial line unit, 214
memory, 4
ROM, BDV11 selection of, 119,
121
supported by LSI-11 bus, 2
see also device addresses; register
addresses

address latch,

ATTN signal,

2,264,397

236; 255

BC08R maintenance cable,
9-10

10-11,

313

BCV1 B bus expansion option,
90
BDAL lines, 3
inBDV11, 117,119
in DCK11-AA and DCK11-AC,
169
in DCK11-AB and DCK11-AD,
190

612

89,

164,
187,

in DLV11-E, 218
in DLV11-F, 240
in DLV11-J, 264
DRV11 and, 294,297,298
;~ nO\lii I:)
III L"IIIY I I - U ,

'li7_'HQ 'l'lt::

V"-VIV,VVV

in DRV11-P, 345
in IBV11-A, 394, 397
in LPV11, 456
BDCOK H signal
in DLV11-E, 221
in DLV11-F, 242
in DLV11-J, 265,266
in H780, 357
in H9275-A, 380
in H9281 , 390
BD INIT H signal,

458

BD INIT L signal,

458

BDIN L signal
in DCK11-AA and DCK11-AC,
165, 170
in DCK11-AB and DCK11-AD,
191
in DLV11-E, 220
in DLV11-F, 240
in DLV11-J, 262,263
in DRV11, 295,298
in DRV11-B, 318,336
in IBV11-A, 394

RXV21 floppy disk option
bootstrapped with, 484
BEVNT L signal,
429

74,136,380,390,

BEVNT registers,

131

BHALT L signal,
390

221, 242, 265, 380,

BIAKI L Signal,
in DCK11-AA and DCK11-AC,
in DLV11-E, 220,221
in DLV11-F, 241
in DRV11, 298
in DRV11-B, 336 BIAKO L

162

signal,
in DCK11-AA and DCK11-AC, 162
in DLV11-E, 220,221
in DLV11-F, 241
in DRV11, 298
162,
in REV11-A and REV11-C, 458
in TEV11, 486
190, BINIT H signal, 299
BINIT L signal,
in DCK11-AA and DCK11-AC, 162
in DLV11-J, 265
in DRV11, 298,310,313
in REV11-A and REV11-C, 458

BIRQ L signal
in DCK11-AA and DCK11-AC, 162,
BDMGI L signal, 183,317,458,486
170
BDMGO L signal, 186,317,458,486
in DCK11-AB and DCK11-AD, 191
BDMR L signal, 185,194,317
in DLV11-E, 220
in DLV11-F, 241
BDOUT L signal,
in DLV11-J, 262
in DCK11-AA and DCK11-AC, 165,
in DRV11-B, 336
170
DCK11-AB and DCK11-AD, 190
bootstrappi ng
in DLV11-J, 262,263
BDV11 for, 16,116-143
in DRV11, 295
REV11-A and REV11-C for, 17,
in DRV11-B, 336
457-458
in IBV11-A, 394
of RXV21 , 484-485
see also initialization
BD SEL signal, 263
BPOK H signal, 357, 380, 390, 483
BDV11 diagnostic bootstrap,
terminator, 16,116-143

613

break logic
on DLV11-E, 221
on DLV11-F, 242
on DLV11-J, 265-266,280
BREAK signal,

bus termination
on H9275-A backplane, 382
on H9281 backplane, 391

265

BRPLY L signal
in DCK11-AA and DCK11-AC,
in DCK11-AB and DCK11-AD,
in DLV11-F, 240
in DLV11-J, 262,263
in DRV11, 295
in DRV11-B, 318,336
in IBV11-A, 394
BSACK signal,

on H9276 backplane, 383
on H9281 backplane, 390
on TEV11 terminator, 486

165 bus transceivers,

190 bus transfer IC
in DCK11-AA and DCK11-AC,
167-169,174-179
in DCK11-AB and DCK11-AD,
190-191,194,199
in IBV11-A, 394

317, 318, 336

BSYNC L signal,
in DCK11-AA and DCK11-AC,
in DLV11-J, 262,263
in DRV11, 294
in DRV11-B, 318,336
in IBV11-A, 394

165

buffer/preset registers (BPRs)
on KWV11-A, 422
on KWV11-C, 428,429,431,432
burst mode DMA,

319

bus address registers (BARs)
on DCK11-AB and DCK11AD, 189,194
on DRV11-B, 315,318,325,327,
336,337
on RXV21, 473
bus interfaces
on DLV11-E, 218
on DLV11-F, 240
on DLV11-J, 263-264
bus priority, on H9275-A
backplane, 381-382
bus restrictions, on H9275-A
backplane, 382
bus signals
on DZV11, 355
on H9275-A backplane,

456

187,

BVENT L signal,

121

BWTBT L signal,

164,295,336,394

cables, 14
for BA11-M expansion box, 89
for DLV11-E asynchronous line
interface, 236
for DLV11-F asynchronrous line
interface, 255
for DLV11-J four-channel
asynchronous serial line
interface, 283-286
for DLV11-KA EIA-to-20 rnA
converter unit, 290
for DRV11-B DMA interface, 331332
for DRV11 parallel line unit, 305,
313
for H9276 backplane, 384
for IBV11-A instrument bus
interface, 408
in LPV11 printer option, 449,453
on W9500 high-density wirewrappable modules, 507
card cages,

205, 206, 376

cartridge tape drive,
380-381

161,

CD bus,

614

383

12,487-494

central processing units, see
processors
CHANHB signal,

195

r.~ANI
R _I~"I"""",
c:inn~1
_ ....... _-

1Q"
• "''''

CHIPKITs, 15-16
DCK11-AA and DCK11-AC program
transfer interfaces, 160-179
DCK11-AB and DCK11-AD direct
memory access interfaces, 180204
CLK-A signal,

181

CLK-C signal,

181

CLK-L signal,

185

clocks
with ADV11-A, 45
KPV11-A, KPV11-B and KPV11C, 415-419
KWV11-A, 45,420-425
KWV11-C, 426-448
CNT1A signal,

181

CNT4 signal,

183

communications,
DC319-AA DLART asynchronous
receiver/transmitter for, 144
DLV11-E asynchronous line
interface for, 217-237
DLV11-F asynchronous line
interface for, 238-257
DLV11-J four-channel
asynchronous serial line interface
for, 258-286
DLV11 serial line unit ;for, 211216
DUV11 line interface for, 347-351
DZV11 asynchronous multiplexer
for, 352-356
on LSI-11 bus, 2
options for, 9-11
VK170-CA serial video module
for, 498, 501
configuration registers,
configurations,

129

615

for AAV11-A four-channel, 12 -bit
digital-to-analog converter, 30-36
for AAV11-C analog output
board, 38-40
for ADV11-A analog-to-digital
converter, 48-52
for ADV11-C analog-to-digital
converter, 59-65
for AXV11-C ananalog input/output
board, 82-87
for BA11-M expansion box, 89-94
for BA11-N mounting box, 99-101
for BDV11 diagnostic, bootstrap,
terminator, 122-131
for DDV11-B backplane, 206-209
for DLV11-E asynchronous line
interface, 222-236
for DLV11-F asynchronous line
interface, 243-257
for DLV11-J four-channel
asynchronous serial line
interface, 267-285
for DLV11-KA EIA-to-20 rnA
converter unit, 288-292
for DLV11 serial line unit, 211-215
for DRV11-B DMA interface, 325330
for DRV11 parallel line unit, 299313
for DUV11 line interface, 348-351
for DZV11 asynchronous
multiplexer, 353-356
for H909-C general purpose logic
enclosure, 365
for H9270 backplane, 370-371
for H9273-A backplane, 373-375
for H9275-A baCkplane, 377-382
for H9281 backplane, 387-392
for IBV11-A instrument bus
interface, 397-409
for KPV11-A, KPV11-B and KPV11-C
powerfail/linetime clock!
terminators, 417
for KWV11-A programmable
realtime clock, 422-425

303,311,313
for KWV11-C programmable
on DRV11-B, 315,325,327-330,
realtime clock, 441-447
337
for REV11-A and REV11-C
on DRV11-J, 340
terminators, DMA refreshes,
on DZV11, 353, 356
bootstraps, 458
for RSV11 floppy disk option, 461· on KWV11-A, 422
on KWV11-C, 428-438
464
for RXV21 floppy disk option, 468- for options, 25
on RXV11, 461
475
on RXV21, 468-472
for VK170-CA serial video
module, 496-503
CPUs, see processors
W9500 high-density wire-wrappable CSRWHB L signal, 195,196
modules .for, 504
CSRWLB L signal, 195
see also Jumpers
CYCLE REQUEST signal, 317,319,
connections
331,336,337
for ADV11-A analog-to-digital
converter, 52
for ADV11-C analog-to-digital
converter, 65-66
for H9270 backplane, 338
DACs, see digital-to-analog
connector blocks, 205
converters
connectors, 14
DAL lines, 117, 119
for H9273-A backplane, 372,373
data buffer registers (DBRs), 3
for H9276 backplane, 383
on ADV11-C, 55,58,59,62
for H9281 backplane, 390
on AXV11-C, 73,74,80-81
for KWV11-C programmable
on DLV11-E, 220
realtime clock, 448
on DLV11-F. 240
for VK170-CA serial video
on DRV11-B, 315,325,330
module, 497
on DRV11-J, 340
see also jumpers
on RXV11, 461
CON SEL 1 H signal, 264
on RXV21, 468,472-473
control and status registers
data communications, see
(CSRs), 3
communications
on ADV11-A, 45, 50
data transfers
on ADV11-A, 55,57-61,63
DRV11-B DMA interface for, 314,
on AXV11-C, 73-74,77-80
317-319,331
on DCK11-AB andbCK11on DRV11 parallel line unit, 297AD, 189, 195, 199-200
298-310
on DLV11-E, 220-222,227,231-235
see also communications
on DLV11-F, 240-242,250-251,
data registers, 25
253-254
DATA TRAMS H pulse, 294,295,
on DLV11-J, 264,265,270,271,
297,310-313
274-276
on DRV11, 293,295,297,298,302- DATEN L signal, 186

616

DATEX L signal,

DCK11-AA program transfer
interface, 15,160-179

195

DATI bus cycle
in DCK11-AB and DCK11-AB,
in DRV11, 294,297
inDRV11-B, 331,337
in LPV11, 456
DATIN L signal,

394

DATIO bus cycle,

337

DATOB bus cycle,
318,336,394

DCK11-AC program transfer
interface, 15,160-179

184

DATIOB bus cycle,
DATIO L signal,

195 DCK11-AB direct memory access
interface, 15-16, 180-204

DCK11-AD direct memory access
interface, 15-16,180-204

184
297,310,317-

DDV11-B backplane, 13,205-210
H909-C general purpose logic,
enclosure for, 365

device addresses,
on ADV11-C, 58,64
DATO bus cycle,
on AXV11-C, 77,81-82
in DCK11-AB and DCK11-AD, 195, on DRV11, 300-301
in DRV11, 297,310
on DRV11-B, 325-326
in DRV11-B, 317-318,331,336
on DRV11-P, 343
DC003 interrupt logic IC
on DUV11, 348
in DCK11-AA and DCK11-AC, 160- on IBV11-A, 397-398
on KWV11-A, 422
164, 170, 172
on DCK11-AB and DCK11-AD, 191 on KWV11-C, 441
in IBV11-A, 396
device priority, on H9281

DCOO4 protocol logic IC,
in DCK11-AA and DCK11-AC,
164-167,169-170,173
in DCK11-AB and DCK11-AD,
191,
in IBV11-A, 394
DCOO5 bus transfer IC,
in DCK11-AA and DCK11-AC,
167-169, 174-179
in DCK11-AB and DCK11-AD,
190-191,194,199
in IBV11-A, 394

backplane, 391
160 device registers, 2-3
onAAV11-A, 32
190
on DLV11-J, 270-271
on DZV11, 353,355
on KWV11-A, 422
on RXV11, 463
161 D/F Signal,

187 diagnostics, BDV11 for,

DC006 word and address counter
IC, 180-183,194,195,201-202
DC010 DMA logic,
191-196,203-204

180,183-187,

DC319-AA DLART asynchronous
receiver/transmitter, 15, 144-161
DC-to-DC power inverters,
267

182

differential amplifiers,
differential inputs,

16,116-143
74

68-69

digital-to-analog converters
(DACs),
AAV11-A, 5,29-36
AAV11-C, 5,37-44
on AXV11-C, 70, 74-76, 82, 86
DIN H signal,

186, 195

222,242, direct memory access (DMA)
interfaces, 15-16

617

DCK11-AB and DCK11-AD,
204
DRV11-B, 314-337

180-

ENAST H signal,

129

display registers,

displays, on BDV11,

ENBClK H signal,

163

ENBDATA H signal,

163

ENB H signal,

121

166

ENBST H signal,

DLART (DC319-AA) asynchronous
receiver/transmitter, 15, 144-161

163

enclosures, 13-14
BA11-M expansion box, 88-94
DlV11-E asynchronous line
BA11-N mounting box, 95-103
interface, 9,217-237
BA11-S expansion box, 104-112
DlV11-F asynchronous line
BA11-VA mounting chassis/power
interface, 9-10,2389-257
supply, 113-115
H909-C general purpose logic
DlV11-J four-channel asynchronous
364-365
enclosure,
serial line interface, 10,258-286
ENX ClK* line, 170
DlV11-KA EIA-to-20 rnA converter
unit,

287-292

ENX DATA* line,

DlV11 serial line unit,
DMA logic,
203-204

9,211-216

errors
display of, on BDV11, 121
interrupts on, on ADV11-C, 58
interrupts on, on AXV11-C, 78

180,183-187,191-196,

DMA refresh option,

17,457-458

error and status registers,

DOUT H signal,

186

DRCSR register,
303,311,313

295,297,298,302-

DRINBUF register,
298,304,310,313

294,295,297,

DROUTBUF register,
298,304,310,313

170,191

expansion boxes, 13
BA 11-M, 88-94
BA11-N mounting box as,
BA11-S, 104-112

474-475

external triggers, see triggers,
294, 295, 297- external

DRV11-B DMA interface,

7,314-337

DRV11-J high-density parallel
interface, 7,338-341

flags, request, 311-312
7,293-313 floppy disks, 11
RXV11, 459-464
DRV11-P lSI-11 bus foundation
RXV21 , 465-485
module, 8, 342-346
DRV11 parallel line unit,

DUV11 line interface,

10,347-351

DZV11 asynchronous
multi plexer, 10-11, 352-356

four-channel asynchronous serial
line interface, 10,258-286
four-channel, 12-bit, digital-to-analog
converter module, 5, 29-36
FUNCT signals,

ENAClK H signal,

163

ENADATA H signal,

163

618

324

H034 system unit mountingframe, 205
H0341 cardcage,

205, 206

H403-A AC input panel,

H403-B AC input box,

104,107

initialization
of DRV11, 298-299,313
remote, of VK170-CA serial video
module, 503
of REV11-A and REV11-C, 458
of RXV21, 482
see also bootstrapping

H780 power supply, 14,357-363
included in BA11-M expansion
box, 88

INITO L signal,

H7861 power supply, 95
included in BA 11-N mounting
box, 95

input data buffer registers
(IDBRs), 315,325,330

H863 connector block,

107

H8030 connector block,

205

H9270 backplane, 12, 366-371
included in BA 11-M expansion
box, 88
H9273-A backplane, 12, 372~375
included in BA 11-N mounting
box, 95-98
H9275-A backplane,

12, 376-382

H9276 backplane, 12-13,383-386
on BA11-S expansion box, 107109
H9276 logic assembly,
H9281 backplane"

104,106

13,387-392

high-density parallel interface,
338-341
high-density wire-wrappable
modules, 14-15,504-508

IBV11-A instrument bus
interface, 8,393-414
ICs, see integrated circuits

324

input data interface, in DRV11,

205

H909-C general purpose logic
enclosure, 13, 364-365
DDV11-B backplane mounted
in, 205
H7861 power supply,

I NIT signals,

162,170,265

310

installation
of BA11-S expansion box, 109-112
of DDV11-B backplane, 206
of DLV11-E asynchronous line
interface, 236
of DLV11-F asynchronous line
interface, 255
of DLV11-KA EIA-to-20 rnA
converter unit, 290
of DRV11 parallel line unit, 305
of TU58 cartridge tape drive, 490491
of VK170-CA serial video
module, 499
instrument bus control (IBC)
registers, 396
instrument bus data (IBD)
registers, 401, 405-406
instrument bus interface,

8,393-414

instrument bus status (IBS)
registers, 401, 403-405
integrated circuits (ICs), 15-16
DC319-AA DLART asynchronous
receiver/transmitter, 144-161
DCK11-AA and DCK11-AC program
transfer interfaces, 160-179
DCK11-AB and DCK11-AD direct
memory access interfaces, 180204
mounted on DRV11-P LSI-11 bus

619

foundation module, 342
on W9500 high-density wirewrappable modules, 507

for TU58 cartridge tape drive,
for VK170-CA serial video
module, 496-497

491

interrupt bus, 397
interfaces,
AAV11-A four-channel, 12-bit
interrupt logic IC,
digital-to-analog converter, 5,29in DCK11-AA and DCK11-AC, 16036
164, 170, 172
AAV11-C analog output board, 5,
in DCK11-AB and DCK11-AD, 191
37-44
in IBV11-A, 396
ADV11-A analog-to-digital
interrupts, 3-4
converter, 5-6, 45-52
interrupt vectors,
ADV11-C analog-to-digital
on ADV11-A, 51
converter, 6, 53-69
on ADV11-C, 55, 58, 63
AXV11-C analog i nputloutput
on AXV11-C, 77-78,84
board, 6-7, 70-87
on
DLV11-E, 220-221,227
DCK11-AA and DCK11-AC program
on DLV11-F, 240,241,243
transfer interfaces, 160-179
on DLV11-J, 264-265,276-278
DCK11-AB and DCK11-AD direct
on DRV11, 298
memory access interfaces, 180on DRV11-B, 326
204
on DRV11-J, 340
DLV11-E asynchronous line
on DRV11-P, 345
interface, 217-237
on DUV11, 350
DLV11-F asynchronous line
on
DZV11, 353
interface, 238-257
IBV11-A,
396,398-401
on
DLV11-J four-channel
on KWV11-A, 422-423
asynchronous serial line
on KWV11-C, 432,443
interface, 258-286
on RXV11, 461
DRV11-B DMA interface, 7,314RXV21 , 468
337
DRV11-J high-density parallel
I NTR CTL signals, 396
interface, 7, 338-341
INWD L signal, 165,190,195,220,
DRV11 parallel line unit, 7,293240
313
I/O control logic,
DRV11-P LSI-11 bus foundation
on DLV11-E asynchronous line
module, 8, 342-346
interface, 218-220
DUV11 line interface, 10,347-351
on
DLV11-F asynchronous line
DZV11 asynchronous
interface,
240
multiplexer, 352-356
on Dl,V11-J four-channel
IBV11-A instrument bus
asynchronous
serial line
interface, 393-414
interface,
262-263
KWV11-A programmable realtime
on DRV11 parallel line unit, 295
clock, 8, 420-425
KWV11-C programmable realtime I/O page (bank 7), 2, 4
clock, 8-9, 426-448
in LPV11 printer option, 449,453 JA L signals, 168

620

jumpers,
on AAV11-A, 35
on AAV11-C, 41
on ADV11-C, 55,56,59,61,63-65
on AXV11-C, 73,74,81,82,85,87
on BDV11, 119,122,127
on DLV11-E, 218-222, 225-226,
229-230
on DLV11-F, 240,241,243,245250
on DLV11-J, 259,262,267-270,
279,280
on DLV11-KA EIA-to-20 rnA
converter unit, 288
on DRV11, 294, 299-301
on DZV11, 354-355
on H9273-A, 374
on H9275-A, 376-377
on KPV11-A, KPV11-B and KPV11C, 417
on RXV11, 461
for RXV21 , 468
on TEV11 , 486
on TU58, 491
on VK170-CA, 499,501-503
see also configurations,
keyboards, VK170-CA serial video
module interface for, 496-497
KVP11-A powerfailllinetime clockl
terminator, 16,415-419
KVP11-B powerfaililinetime clockl
terminator, 16,415-419
KVP11-C powerfail/linetime clockl
terminator, 16,415-419
KWV11-A programmable realtime
clock, 8, 420-425
used with ADV11-A, 45
KWV11-C programmable realtime
clock, 8-9, 426-448
LA180 lineprinter,
LD signal,

449,453

182

line interfaces
DUV11, 10,347-351

see also asynchronous line
interfaces
lineprinter systems,
linetime clocks,

449-456

415-419

logic box bases
for BA11-N mounting box, 98,101
for BA11-S expansion Box, 107
logic box covers
for BA11-N mounting box, 98-100
for BA11-S expansion box, 107
LP05 line printer,

449,453

LPV11 printer system option,
449-456

11,

LSI-11 bus, 1-3
BA 11-M expansion box for, 88, 89
configurations for, 25
DCK11-AA and DCK11-AC program
transfer interfaces for, 160
DLV11-E asynchronous line
interface for communications
by, 217,218
DLV11-F asynchronous line
interface for communications
by, 238,240
DLV11-J four-channel
asynchronous serial line interface
for peripherals to, 258,259,263264
DRV11-B DMA interface for data
transfers by means of, 314
DRV11 parallel line unit for, 293
DRV11-P foundation module
for, 342-346
DUV11 line interface for, 347
DZV11 asynchronous multiplexer
for, 352
H780 power supply for, 357, 360
on H9276 backplane, 383-384
on H9281 backplane, 387
IBV11-A instrument bus interface
for, 393-397
KWV11-C programmable realtime
clock for, 426
power fail on, 483

621

specifications for modules for,
5
lSI-11 bus foundation module,
342-346
lSI-11 family, 1-4

RXV11 floppy disk option,
RXV21 floppy disk option,
TU58 cartridge tape drive,
494

48,

memory addresses,
ME signal,

lSI-11/2 modules,

113

lSI-11/23 modules,

lSI-11 processors

see processors

459-464
465-485
12,487-

294, 295

modems
DUV11 line interface for, 347
DZV11 asynchronous multiplexer
for, 352, 354-355

modules
DlV11-E asynchronous line
interface, 217-237
M7946 interface module, 461
DlV11-F asynchronous line
M7954 interface module, 393
interface, 238-257
M7957 module, 352,353
DLV11-J four-channel
M8027 interface module, 453
asynchronous serial line
interface, 258-286
M8029 interface module, 468
DRV11-P LSI-11 bus
M9404 connector module, 384
foundation, 342-346
M9405 connector module, 384
DZV11 asynchronous
multiplexer, 352-356
maintenance mode logic
in LPV11 printer option, 449
on DlV11-E, 222
mounted in BA11-M expansion
on DlV11-F, 242
box, 89
on DRV11, 298
mounted
in BA11-N mounting
MASTER H Signal, 185
box, 96,98
MATCH H Signal
mounted in BA11-S expansion
in DCK11-AA and DCK11-AC, 168,
box, 107
170, 174
mounted in BA11-VA mounting
in DlV11-E, 218
chassis/power supply, 113-115
in DlV11-F, 240
mounted in DDV11-B
in DlV11-J, 263,264
backplane, 206, 209
MAX-A Signal, 182
mounted in H9276 backplane, 383
specifications
for, 4-5, 18-24
MAX-C signal, 182,195
TEV11 terminator, 486
memory
TU58 cartridge tape drive, 487-494
in BDV11, 16,116-143
VK170-CA serial video, 495-503
DCK11-AB and DCK11-AD direct
W9500 high-density wirememory access interfaces
wrappable, 14-15,504-508
for, 180-204
mounting boxes, 13
in DRV11, 295
BA11-N, 95-103
DRV11-B DMA interface for, 31411-S expansion box as, 104
BA
337
in REV11-A and REV11-C,

457

mounting chassis,

622

14,113-115

MRPLY L signal,

190, 195

multiplexers, asynchronous,
356

352-

MXV11 mu !tifunction module,

114

NEW DATA ROY H signal,
298,310-313

294,295,

options
BA11-M expansion box, 88-94
BA11-N mounting box, 95-103
BA 11-8 expansion box, 104-112
BA11-VA mounting chassis/power
supply, 113-115
backplane, 12-13
BDV11 diagnostic, bootstrap
terminator, 116-143
communications, 9-11
DC319-AA DLART asynchronous
receiver/transmitter, 144-161
DCK11-AA and DCK11-AC program
transfer interfaces, 160-179
DCK11-AB and DCK11-AD direct
memory access interfaces, 180204
DDV11-B backplane, 205-210
DLV11-E asynchronous line
interface, 217-237
DLV11-F asynchronous line
interface, 238-257
DLV11-J four-channel
asynchronous serial line
interface, 258-286
DRV11 parallel line unit, 293-313
DLV-KA EIA-to-20 rnA converter
unit, 287-292
DLV11 serial line unit, 211-216
DRV11-B DMA interface, 314-337
DRV11-J high-density parallel
interface, 338-341
DUV11 line interface, 347-351
DZV11 asynchronous
multiplexer, 352-356
enclosures, 13-14
H909-C general purpose logic
enclosure, 364-365

H9270 backplane, 366-371
H9273-A backplane, 372-375
H9275-A backplane, 376-382
H9276 backplane, 383-386
H9281 backplane, 387-392
IBV11-A instrument bus
interface, 393-414
integrated circuits, 15-16
interfaces, descriptions of, 5-9
KVP11-A, KVP11-B and KVP11-C
powerfail/linetime clock!
terminators, 415-419
KWV11-A programmable realtime
clock, 420-425
KWV11-C programmable realtime
clock, 426-448
LPV11 printer system, 449-456
miscellaneous, 16-17
peri pherals, 11-12
power supply, 14
REV11-A and REV11-C
terminator,
DMA refresh bootstrap, 457458
RXV11 floppy disk, 459-464
RXV21 floppy disk, 465-485
specifications for, 4-5
TEV11 terminator, 486
TU58 cartridge tape drive, 487-494
VK170-CA serial video
module, 495-503
W9500 high-density wire-wrappable
modules, 14-15,504-508
oscilloscopes,

OUTHB L signal,

165,190,195

OUTLB L signal,

165,190, 195

output buffers,

189

output data buffer registers
(IDBRs), 315,325,330
output data interface, in
DRV11, 310

623

page control registers (PCRs),
128-129, 139, 142
parallel iine unit,

119,

receiver/transmitter for data
communications by, 144
H9275-A backplane for, 376, 377
interrupts in, 3
transferring AID data to, on AXV11C, 76-77

293-313

PDP-11 systems, LSI-11 bus
compatibility with, 2
PDP-11/23-PLUS systems, BA 11-S
expansion box for, 104

processor status word (PS),

program counter (PC), 3
peripheral interfaces
programmable gain amplifiers,
on DLV11-E, 222
in ADV11-C, 57
on DLV11-F, 242
in
AXV11-C, 74
on DLV11-J, 266,281
peripherals
programmable realtime clocks
DC319-AA DLART asynchronous
KWV11-A, 45, 420-425
receiver/transmitter as, 144
KWV11-C, 426-448
device addresses for, 2
programming
device registers for, 3
of AAV11-C analog output
DLV11-J four-channel
board, 41-42
asynchronous serial line interface
of ADV11-C registers, 57-59
for, 258,266,281
ofAXV11-C analog input/output
interrupts requested by, 3-4
board, 76-82
options, 11-12
of BDV11 diagnostic, bootstrap,
powerfail, on RSV21 floppy disk
terminator, 116,132-143
option, 482, 483
of DLV11-J four-channel
asynchronous serial line
powerfailliinetime clock!
interface, 286
terminators, 16,415-419
of DRV11-B DMA interface, 314,
power supplies, 14
331-337
BA 11-VA, 113-115
of DRV11-J high-density parallel
for DDV11-B backplane, 209
interface, 340
H780, 357-363
of IBV11-A instrument bus
for H9270 backplane, 368
interface, 409-414
for H9275-A backplane, 379-380
of KWV11-C programmable
for H9281 backplane, 390
realtime clock, 431-441
KLV11-KA EIA-to-2O mA converter
of RXV21 floppy disk option, 475unit for, 287-292
483
printer system option, 11, 449-456
program transfer interfaces, 15,
priority levels
160-179
bus, on H9275-A backplane, 381protocol logic IC
382
in DCK11-AA and DCK11-AC, 160,
device, on H9281 backplane, 391
164-167,169-170,173
for interrupts, 3
in DCK11-AB and DCK11-AD, 190processors, 2
191
DC319-AA DLART asynchronous
in IBV11-A, 394

624

pseudo-differential inputs,

67-68

in RXV11,
in RXV21,

461
468

random access memory (RAM)
registers
programming, from read-only
on AAV11-A, 32
memory, on BDV11, 143
on RXV21 floppy disk option, 465 on AAV11-C, 38-41,44
on ADV11-A, 45, 50
RD-A signal, 182
on ADV11-C, 55, 57-63
RD- signal, 182
on AXV11-C, 70, 73-81
read data multiplexer, 297
on BDV11, 119,127-129,131,139,
142
read-only memory (ROM)
configuration and, 25
BDV11, 16,116-143
on DC319-AA DLART, 154-157
in DRV11, 295
on DCK11-AB and DCK11in REV11-A and REV11-C, 457
AD, 189,190,194-195,199-200
read/write registers
device, 2-3
on AAV11-C, 41
on DLV11-E, 220-223,227,231-236
onBDV11, 119,129
on DLV11-F, 240-243,250-255
realtime clocks
on DLV11-J, 260, 262, 264, 265,
KWV11-A, 45,420-425
270-276, 286
KWV11-C, 426-448
on DRV11, 295, 297-298, 302-304,
310,311,313
receiver active circuits
on DRV11-B, 315,318,325,327in DLV11-E, 220
331,336,337,
in DLV11-F, 241
on DRV11-J, 340
receiver buffer (RBUF) registers
on DRV11-P, 343
on DC319-AA DLART, 154-155
on
DZV11, 353-356
on DLV11-E, 220,233-234
on
IBV11-A,
396,401-406
on DLV11-F, 240-242,251-253
on KWV11-A, 422
on DLV11-J, 260,262,264,270,
on KWV11-C, 428-438
274-275
on RXV11, 461-464
receiver control/status registers
on RXV21, 468-475,481
(RCSRs)
REO A H Signal, 297, 298, 311, 313
on DLV11-E, 220-222,231-233
REO 8 H signal, 297,298,311,313
on DLV11-F, 240,241,250-251
on DLV11-J, 265,270,271,274
REO H signals, 183,194
receiver/transmitter,
asynchronous, 15,144-161
REC H signal,

168,169,187,199

register addresses
in DLV11-E, 223
in DLV11-F, 243
in DLV11-J, 270-271
in DRV11-B, 325-326
in DZV11, 353,354
in KWV11-C, 432

request flags,

311-312

REV11-A terminator, DMA refresh,
bootstrap, 17,457-458
REV11-C DMA refresh,
bootstrap, 17,457-458
RPLY H signal,

185

RPLY L signal,

295

ROSTA H signal,

625

163

tape drive,

ROSTX· signal,

170

terminals, VK170-CA serial video
module for, 12,495-503

RSYNC H signal,

184-185

RX02 disk drive,

468, 482

ROSTB H signal,
ROST signal,

191

RXAC L line,

482

RXCX H signal,

166

RXV11 floppy disk option,
464

11,459-

RXV21 floppy disk option,
485

11,465-

12, 487-494

termi nators, 16, 17
BDV11, 116-143
KPV11-A, KPV11-B and KPV11C, 415-419
REV11-A, 457-458
TEV11, 486
TEV11 terminator, 17, 486
used with BA11-M expansion
box, 89,90
TMOUT H signal,

184

track address registers,

transceivers
in BDV11 diagnostic, bootstrap,
terminator, 117
bus, in LPV11, 456
DCOO5, 161,167-169,174-179,187,
1~191, 194, 199,394

sample and hold amplifiers
in ADV11-C, 57
in AXV11-C, 74
S-A signal,

181

Schmitt triggers
on KWV11-A, 420, 424
on KWV11-C, 426,429,431,441,
443-447
S-C signal,

182

sector address registers,

473

SEL L signals,
295,297

165-166,190,195,

serial line unit,

9,211-216

serial video module,

12,495-503

signal peripheral interface,
single cycle DMA,
SRUN L signal,

473

222

319

380, 390

transmitter control/status registers
(XCSRs)
on DC319-AA DLART, 156-157
on DLV11-E, 220-222,234-235
on DLV11-F, 240-242,253-254
on DLV11-J, 265, 270, 275-276
transmitter data buffers (XBUFs)
on DC319-AA DLART, 155-156
on DLV11-E, 220,235-236
on DLV11-F, 240-242,254-255
on DLV11-J, 262,264,270,276
transmitters, DC319-AA DLART
asynchronous receiver/transmitter
as, 15,144-161

STATUS signals,

324

triggers, external
for ADV11-C, 65
for AXV11-C, 85-86
see a/so Schmitt triggers

SYNC H signal,

263

TSYNC H Signal,

standard device addresses,
seedevice addresses

system monitor, on RXV21 floppy
disk option, 484

186

TU58 cartridge tape drive,
494

626

12, 487-

universal asynchronous receiver!
transmitters (UARTs)
in DLV11-J four-channel
asynchronous serial line
interface, 259-262, 265
in DLV11 serial line unit, 214-215
on VK170-CA serial video
module, 499

W9500 high-density wire-wrappable
modules, 14-15,504-508
W9511 wire-wrappable module,
508

14,

W9512 wire-wrappable module,
508
W9514 wire-wrappable module,
15,508

15,
14-

W9515 wire-wrappable module,
508
VECRQSTB H signal,
241

161, 170, 220,

vector generation logic,

264-265

VECTOR H signal
in DCK11-AA and DCK11-AC,
164,170
in DCK11-AB and DCK11-AD,
in DLV11-E, 220
in DLV11-F, 240,241
in DRV11, 297,298
in DRV11-P, 345

WCNTO signal,

194

wire-wrappable modules,
504-508

14-15,

word and address counter IC,
161, 183,194,195,201-202
191

15,

180-

word count registers (WCRs)
on DCK11-AB and DCK11AD, 189, 194, 195
on DRV11-B, 315,318,325,327,
331,336,337
on RXV21, 473

vector interrupts, see interrupt
vectors
vectors
on DRV11, 301
see a/so interrupt vectors
video module,

XBUF, see transmitter data buffer
XCSR, see transmitter control/status
register

12, 495-503

VK17O-CA serial video module,
495-503

12,

XMIT H signal,
199

627

117, 119, 168, 169,

NOTES

MICROCOMPUTER INTERFACES HANDBOOK

1983-84

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